STM32H7B3xQ HAL User Manual: STM32H7xx HAL Drivers

STM32H7B3xQ HAL User Manual
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STM32H7xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32H7B3xQ HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL Exported Variables

  • Data Structures
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Variables
HAL Exported Variables
HAL

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT
__IO uint32_t | uwTick
uint32_t | uwTickPrio
HAL_TickFreqTypeDef uwTickFreq

Variable Documentation

__IO uint32_t uwTick

Definition at line 71 of file stm32h7xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

__IO uint32_t uwTick

Definition at line 71 of file stm32h7xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT

Definition at line 73 of file stm32h7xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

HAL_TickFreqTypeDef uwTickFreq

Definition at line 73 of file stm32h7xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS)

Definition at line 72 of file stm32h7xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), and HAL_SetTickFreq().

uint32_t uwTickPrio

Definition at line 72 of file stm32h7xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), and HAL_SetTickFreq().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Private Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface the NVIC allocation and initial clock
          configuration. It initializes the systick also when timeout is needed
          and the backup domain when enabled.
      (+) De-Initializes common part of the HAL.
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the systick.

This function is optional.

Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_AHB4_FORCE_RESET, __HAL_RCC_AHB4_RELEASE_RESET, __HAL_RCC_APB1H_FORCE_RESET, __HAL_RCC_APB1H_RELEASE_RESET, __HAL_RCC_APB1L_FORCE_RESET, __HAL_RCC_APB1L_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, __HAL_RCC_APB3_FORCE_RESET, __HAL_RCC_APB3_RELEASE_RESET, __HAL_RCC_APB4_FORCE_RESET, __HAL_RCC_APB4_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).

Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32h7xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 134 of file stm32h7xx_hal.c.

References HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), HAL_RCC_GetSysClockFreq(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

__weak HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 254 of file stm32h7xx_hal.c.

References CM7_CPUID, HAL_GetCurrentCPUID(), HAL_NVIC_SetPriority(), HAL_RCC_GetHCLKFreq(), HAL_SYSTICK_Config(), uwTickFreq, and uwTickPrio.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), and HAL_SetTickFreq().

__weak void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 231 of file stm32h7xx_hal.c.

Referenced by HAL_DeInit().

__weak void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 220 of file stm32h7xx_hal.c.

Referenced by HAL_Init().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Private Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
Return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_VDDMMC_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

__weak void HAL_Delay ( uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 417 of file stm32h7xx_hal.c.

References HAL_GetTick(), and uwTickFreq.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), HAL_DTS_Start(), HAL_DTS_Start_IT(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_PCDEx_BCD_VBUSDetect(), and HAL_SD_InitCard().

void HAL_DisableCompensationCell ( void )

Power-down the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 799 of file stm32h7xx_hal.c.

void HAL_DisableDBGSleepMode ( void )

Disable the Debug Module during Domain1/CDomain SLEEP mode.

Return values:
None

Definition at line 903 of file stm32h7xx_hal.c.

void HAL_DisableDBGStandbyMode ( void )

Disable the Debug Module during Domain1/CDomain STANDBY mode.

Return values:
None

Definition at line 940 of file stm32h7xx_hal.c.

void HAL_DisableDBGStopMode ( void )

Disable the Debug Module during Domain1/CDomain STOP mode.

Return values:
None

Definition at line 922 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStandbyMode ( void )

Disable the Debug Module during Domain3/SRDomain STANDBY mode.

Return values:
None

Definition at line 1031 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStopMode ( void )

Disable the Debug Module during Domain3/SRDomain STOP mode.

Return values:
None

Definition at line 1013 of file stm32h7xx_hal.c.

void HAL_EnableCompensationCell ( void )

Enables the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 788 of file stm32h7xx_hal.c.

void HAL_EnableDBGSleepMode ( void )

Enable the Debug Module during Domain1/CDomain SLEEP mode.

Return values:
None

Definition at line 894 of file stm32h7xx_hal.c.

void HAL_EnableDBGStandbyMode ( void )

Enable the Debug Module during Domain1/CDomain STANDBY mode.

Return values:
None

Definition at line 931 of file stm32h7xx_hal.c.

void HAL_EnableDBGStopMode ( void )

Enable the Debug Module during Domain1/CDomain STOP mode.

Return values:
None

Definition at line 913 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStandbyMode ( void )

Enable the Debug Module during Domain3/SRDomain STANDBY mode.

Return values:
None

Definition at line 1022 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStopMode ( void )

Enable the Debug Module during Domain3/SRDomain STOP mode.

Return values:
None

Definition at line 1005 of file stm32h7xx_hal.c.

void HAL_EXTI_D1_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
Return values:
None

Definition at line 1112 of file stm32h7xx_hal.c.

References assert_param, and IS_EXTI_D1_LINE.

void HAL_EXTI_D1_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Mode,
 |  | uint32_t | EXTI_LineCmd
 | ) |  |

Configure the EXTI input event line for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
EXTI_Mode,: Specifies which EXTI line is used as interrupt or an event. This parameter can be one or a combination of the following values :
  • EXTI_MODE_IT : Interrupt Mode selected
  • EXTI_MODE_EVT : Event Mode selected
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
Return values:
None

Definition at line 1147 of file stm32h7xx_hal.c.

References assert_param, EXTI_MODE_EVT, EXTI_MODE_IT, IS_EXTI_D1_LINE, and IS_EXTI_MODE_LINE.

void HAL_EXTI_D3_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_LineCmd,
 |  | uint32_t | EXTI_ClearSrc
 | ) |  |

Configure the EXTI input event line for Domain D3.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
EXTI_ClearSrc,: Specifies the clear source of D3 pending event. This parameter can be one of the following values :
  • BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
  • BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
  • LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
  • LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
Return values:
None

Definition at line 1241 of file stm32h7xx_hal.c.

References assert_param, IS_EXTI_D3_CLEAR, and IS_EXTI_D3_LINE.

void HAL_EXTI_EdgeConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Edge
 | ) |  |

Configure the EXTI input event line edge.

Note:
No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
EXTI_Edge,: Specifies EXTI line Edge used. This parameter can be one of the following values :
  • EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
  • EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
Return values:
None

Definition at line 1071 of file stm32h7xx_hal.c.

References assert_param, EXTI_FALLING_EDGE, EXTI_RISING_EDGE, IS_EXTI_EDGE_LINE, and IS_HAL_EXTI_CONFIG_LINE.

void HAL_EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt on selected EXTI line.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
Return values:
None

Definition at line 1097 of file stm32h7xx_hal.c.

References assert_param, and IS_HAL_EXTI_CONFIG_LINE.

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 487 of file stm32h7xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetFMCMemorySwappingConfig ( void )

Get FMC Bank mapping mode.

Return values:
The FMC Bank mapping mode. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2

Definition at line 1054 of file stm32h7xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 469 of file stm32h7xx_hal.c.

References __STM32H7xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 478 of file stm32h7xx_hal.c.

Referenced by ADC_ConfigureBoostMode(), HAL_ADC_Init(), HAL_CRYP_Init(), HAL_RCC_GetOscConfig(), HAL_RCCEx_CRSConfig(), and HAL_SAI_Init().

__weak uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 351 of file stm32h7xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_WaitOnOFNEFlag(), DelayBlock_Enable(), FLASH_CRC_WaitForLastOperation(), FLASH_OB_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_Suspend(), HAL_DMA_Abort(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DTS_Start(), HAL_DTS_Start_IT(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_TT_ConfigOperation(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_I2S_DMAPause(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Encode(), HAL_MDMA_Abort(), HAL_MDMA_Init(), HAL_MDMA_PollForTransfer(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ReadBlocks(), HAL_MMC_WriteBlocks(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), HAL_NAND_Write_SpareArea_8b(), HAL_NOR_GetStatus(), HAL_OSPI_Abort(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Transmit(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PSSI_Receive(), HAL_PSSI_Transmit(), HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), HAL_PWREx_EnableUSBReg(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), HAL_RNGEx_SetConfig(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetActiveSeed(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SWPMI_Init(), HAL_SWPMI_Receive(), HAL_SWPMI_Transmit(), HAL_SYSCFG_EnableVREFBUF(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), HASH_WaitOnFlagUntilTimeout(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), MMC_ReadExtCSD(), PSSI_WaitOnStatusUntilTimeout(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), RTC_EnterInitMode(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_PowerON(), SD_SendSDStatus(), SD_UltraHighSpeed(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPDIFRX_WaitOnFlagUntilTimeout(), SPI_WaitOnFlagUntilTimeout(), SWPMI_DMATransmitCplt(), SWPMI_WaitOnFlagSetUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

HAL_TickFreqTypeDef HAL_GetTickFreq ( void )

Return tick frequency.

Return values:
tick period in Hz

Definition at line 401 of file stm32h7xx_hal.c.

References uwTickFreq.

uint32_t HAL_GetTickPrio ( void )

This function returns a tick priority.

Return values:
tick priority

Definition at line 360 of file stm32h7xx_hal.c.

References uwTickPrio.

uint32_t HAL_GetUIDw0 ( void )

Return the first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 496 of file stm32h7xx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Return the second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 505 of file stm32h7xx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Return the third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 514 of file stm32h7xx_hal.c.

__weak void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 340 of file stm32h7xx_hal.c.

References uwTick, and uwTickFreq.

__weak void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 459 of file stm32h7xx_hal.c.

void HAL_SetFMCMemorySwappingConfig ( uint32_t BankMapConfig )

Set the FMC Memory Mapping Swapping config.

Parameters:
BankMapConfig,: Defines the FMC Bank mapping configuration. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
Return values:
HAL state

Definition at line 1042 of file stm32h7xx_hal.c.

References assert_param, and IS_FMC_SWAPBMAP_MODE.

HAL_StatusTypeDef HAL_SetTickFreq ( HAL_TickFreqTypeDef Freq )

Set new tick Freq.

Return values:
Status

Definition at line 369 of file stm32h7xx_hal.c.

References assert_param, HAL_InitTick(), IS_TICKFREQ, uwTickFreq, and uwTickPrio.

__weak void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 443 of file stm32h7xx_hal.c.

void HAL_SYSCFG_AnalogSwitchConfig | ( | uint32_t | SYSCFG_AnalogSwitch,
 |  | uint32_t | SYSCFG_SwitchState
 | ) |  |

Analog Switch control for dual analog pads.

Parameters:
SYSCFG_AnalogSwitch,: Selects the analog pad This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0 : Select PA0 analog switch
  • SYSCFG_SWITCH_PA1: Select PA1 analog switch
  • SYSCFG_SWITCH_PC2 : Select PC2 analog switch
  • SYSCFG_SWITCH_PC3: Select PC3 analog switch
SYSCFG_SwitchState,: Open or Close the analog switch between dual pads (PXn and PXn_C) This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0_OPEN
  • SYSCFG_SWITCH_PA0_CLOSE
  • SYSCFG_SWITCH_PA1_OPEN
  • SYSCFG_SWITCH_PA1_CLOSE
  • SYSCFG_SWITCH_PC2_OPEN
  • SYSCFG_SWITCH_PC2_CLOSE
  • SYSCFG_SWITCH_PC3_OPEN
  • SYSCFG_SWITCH_PC3_CLOSE
Return values:
None

Definition at line 643 of file stm32h7xx_hal.c.

References assert_param, IS_SYSCFG_ANALOG_SWITCH, and IS_SYSCFG_SWITCH_STATE.

void HAL_SYSCFG_CompensationCodeConfig | ( | uint32_t | SYSCFG_PMOSCode,
 |  | uint32_t | SYSCFG_NMOSCode
 | ) |  |

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_PMOSCode,: PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
SYSCFG_NMOSCode,: NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 862 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_CONFIG.

void HAL_SYSCFG_CompensationCodeSelect ( uint32_t SYSCFG_CompCode )

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_CompCode,: Selects the code to be applied for the I/O compensation cell This parameter can be one of the following values:
  • SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
  • SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
Return values:
None

Definition at line 845 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_SELECT.

void HAL_SYSCFG_DisableIOSpeedOptimize ( void )

To Disable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 828 of file stm32h7xx_hal.c.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 599 of file stm32h7xx_hal.c.

void HAL_SYSCFG_EnableIOSpeedOptimize ( void )

To Enable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 812 of file stm32h7xx_hal.c.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 573 of file stm32h7xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_VDDMMC_CompensationCodeConfig | ( | uint32_t | SYSCFG_PMOSCode,
 |  | uint32_t | SYSCFG_NMOSCode
 | ) |  |

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_PMOSCode,: VDDMMC PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
SYSCFG_NMOSCode,: VDDMMC NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 881 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_CONFIG.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
Return values:
None

Definition at line 549 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 561 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V. This requires VDDA equal to or higher than 1.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V. This requires VDDA equal to or higher than 2.1 V.
Return values:
None

Definition at line 533 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Tick Frequency

Enumerations
Tick Frequency
HAL

Enumerations

enum HAL_TickFreqTypeDef { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ }

Enumeration Type Documentation

enum HAL_TickFreqTypeDef
Enumerator:
HAL_TICK_FREQ_10HZ
HAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT

Definition at line 44 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: device revision ID

Defines
device revision ID
HAL

Defines

#define | REV_ID_Y ((uint32_t)0x1003)
#define | REV_ID_B ((uint32_t)0x2000)
#define | REV_ID_X ((uint32_t)0x2001)
#define | REV_ID_V ((uint32_t)0x2003)

Define Documentation

#define REV_ID_B ((uint32_t)0x2000)

STM32H7 rev.B

Definition at line 61 of file stm32h7xx_hal.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), and HAL_SAI_Init().

#define REV_ID_V ((uint32_t)0x2003)

STM32H7 rev.V

Definition at line 63 of file stm32h7xx_hal.h.

#define REV_ID_X ((uint32_t)0x2001)

STM32H7 rev.X

Definition at line 62 of file stm32h7xx_hal.h.

#define REV_ID_Y ((uint32_t)0x1003)

STM32H7 rev.Y

Definition at line 60 of file stm32h7xx_hal.h.

Referenced by ADC_ConfigureBoostMode(), HAL_ADC_Init(), HAL_RCC_GetOscConfig(), and HAL_RCCEx_CRSConfig().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
HAL

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)

Define Documentation

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))

Definition at line 78 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2

Voltage reference scale 0 (VREF_OUT2)

Definition at line 72 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1

Voltage reference scale 1 (VREF_OUT1)

Definition at line 73 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4

Voltage reference scale 2 (VREF_OUT4)

Definition at line 74 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3

Voltage reference scale 3 (VREF_OUT3)

Definition at line 75 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
HAL

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Define Documentation

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 94 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 97 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 91 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 92 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
HAL

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)

Define Documentation

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 115 of file stm32h7xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP

Fast-mode Plus driving capability on a specific GPIO.

Enable Fast-mode Plus on PB6

Definition at line 110 of file stm32h7xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP

Enable Fast-mode Plus on PB7

Definition at line 111 of file stm32h7xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP

Enable Fast-mode Plus on PB8

Definition at line 112 of file stm32h7xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP

Enable Fast-mode Plus on PB9

Definition at line 113 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Ethernet Config

Defines
Ethernet Config
HAL

Defines

#define | SYSCFG_ETH_MII ((uint32_t)0x00000000)
#define | SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2
#define | IS_SYSCFG_ETHERNET_CONFIG(CONFIG)

Define Documentation

#define IS_SYSCFG_ETHERNET_CONFIG ( CONFIG )
Value:
(((CONFIG) == SYSCFG_ETH_MII)        || \
                                          ((CONFIG) == SYSCFG_ETH_RMII))

Definition at line 131 of file stm32h7xx_hal.h.

#define SYSCFG_ETH_MII ((uint32_t)0x00000000)

Select the Media Independent Interface

Definition at line 128 of file stm32h7xx_hal.h.

#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2

Select the Reduced Media Independent Interface

Definition at line 129 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Analog Switch Config

Defines
Analog Switch Config
HAL

Defines

#define | SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
#define | IS_SYSCFG_ANALOG_SWITCH(SWITCH)
#define | SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)
#define | IS_SYSCFG_SWITCH_STATE(STATE)

Define Documentation

#define IS_SYSCFG_ANALOG_SWITCH ( SWITCH )
Value:
((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))

Definition at line 148 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_AnalogSwitchConfig().

#define IS_SYSCFG_SWITCH_STATE ( STATE )
Value:
((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))

Definition at line 163 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_AnalogSwitchConfig().

#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO

Select PA0 analog switch

Definition at line 142 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)

PA0 analog switch closed

Definition at line 155 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO

PA0 analog switch opened

Definition at line 154 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO

Select PA1 analog switch

Definition at line 143 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)

PA1 analog switch closed

Definition at line 157 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO

PA1 analog switch opened

Definition at line 156 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO

Select PC2 analog switch

Definition at line 144 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)

PC2 analog switch closed

Definition at line 159 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO

PC2 analog switch opened

Definition at line 158 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO

Select PC3 analog switch

Definition at line 145 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)

PC3 analog switch closed

Definition at line 161 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO

PC3 analog switch opened

Definition at line 160 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Boot Config

Defines
Boot Config
HAL

Defines

#define | SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)
#define | IS_SYSCFG_BOOT_REGISTER(REGISTER)
#define | IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)

Define Documentation

#define IS_SYSCFG_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) < PERIPH_BASE)

Definition at line 184 of file stm32h7xx_hal.h.

#define IS_SYSCFG_BOOT_REGISTER ( REGISTER )
Value:
(((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))

Definition at line 181 of file stm32h7xx_hal.h.

#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)

Select Boot address0

Definition at line 178 of file stm32h7xx_hal.h.

#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)

Select Boot address1

Definition at line 179 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IOCompenstionCell Config

Defines
IOCompenstionCell Config
HAL

Defines

#define | SYSCFG_CELL_CODE ((uint32_t)0x00000000)
#define | SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
#define | IS_SYSCFG_CODE_SELECT(SELECT)
#define | IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))

Define Documentation

#define IS_SYSCFG_CODE_CONFIG ( CONFIG ) ((CONFIG) < (0x10UL))

Definition at line 200 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CompensationCodeConfig(), and HAL_SYSCFG_VDDMMC_CompensationCodeConfig().

#define IS_SYSCFG_CODE_SELECT ( SELECT )
Value:
(((SELECT) == SYSCFG_CELL_CODE)|| \
                                        ((SELECT) == SYSCFG_REGISTER_CODE))

Definition at line 197 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CompensationCodeSelect().

#define SYSCFG_CELL_CODE ((uint32_t)0x00000000)

Select Code from the cell

Definition at line 194 of file stm32h7xx_hal.h.

#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS

Code from the SYSCFG compensation cell code register

Definition at line 195 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Event Input Config

Defines
Event Input Config
HAL

Defines

#define | EXTI_MODE_IT ((uint32_t)0x00010000)
#define | EXTI_MODE_EVT ((uint32_t)0x00020000)
#define | EXTI_RISING_EDGE ((uint32_t)0x00100000)
#define | EXTI_FALLING_EDGE ((uint32_t)0x00200000)
#define | IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
#define | IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
#define | EXTI_LINE0 ((uint32_t)0x00)
#define | EXTI_LINE1 ((uint32_t)0x01)
#define | EXTI_LINE2 ((uint32_t)0x02)
#define | EXTI_LINE3 ((uint32_t)0x03)
#define | EXTI_LINE4 ((uint32_t)0x04)
#define | EXTI_LINE5 ((uint32_t)0x05)
#define | EXTI_LINE6 ((uint32_t)0x06)
#define | EXTI_LINE7 ((uint32_t)0x07)
#define | EXTI_LINE8 ((uint32_t)0x08)
#define | EXTI_LINE9 ((uint32_t)0x09)
#define | EXTI_LINE10 ((uint32_t)0x0A)
#define | EXTI_LINE11 ((uint32_t)0x0B)
#define | EXTI_LINE12 ((uint32_t)0x0C)
#define | EXTI_LINE13 ((uint32_t)0x0D)
#define | EXTI_LINE14 ((uint32_t)0x0E)
#define | EXTI_LINE15 ((uint32_t)0x0F)
#define | EXTI_LINE16 ((uint32_t)0x10)
#define | EXTI_LINE17 ((uint32_t)0x11)
#define | EXTI_LINE18 ((uint32_t)0x12)
#define | EXTI_LINE19 ((uint32_t)0x13)
#define | EXTI_LINE20 ((uint32_t)0x14)
#define | EXTI_LINE21 ((uint32_t)0x15)
#define | EXTI_LINE22 ((uint32_t)0x16)
#define | EXTI_LINE23 ((uint32_t)0x17)
#define | EXTI_LINE24 ((uint32_t)0x18)
#define | EXTI_LINE25 ((uint32_t)0x19)
#define | EXTI_LINE26 ((uint32_t)0x1A)
#define | EXTI_LINE27 ((uint32_t)0x1B)
#define | EXTI_LINE28 ((uint32_t)0x1C)
#define | EXTI_LINE29 ((uint32_t)0x1D)
#define | EXTI_LINE30 ((uint32_t)0x1E)
#define | EXTI_LINE31 ((uint32_t)0x1F)
#define | EXTI_LINE32 ((uint32_t)0x20)
#define | EXTI_LINE33 ((uint32_t)0x21)
#define | EXTI_LINE34 ((uint32_t)0x22)
#define | EXTI_LINE35 ((uint32_t)0x23)
#define | EXTI_LINE36 ((uint32_t)0x24)
#define | EXTI_LINE37 ((uint32_t)0x25)
#define | EXTI_LINE38 ((uint32_t)0x26)
#define | EXTI_LINE39 ((uint32_t)0x27)
#define | EXTI_LINE40 ((uint32_t)0x28)
#define | EXTI_LINE41 ((uint32_t)0x29)
#define | EXTI_LINE42 ((uint32_t)0x2A)
#define | EXTI_LINE43 ((uint32_t)0x2B)
#define | EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */
#define | EXTI_LINE47 ((uint32_t)0x2F)
#define | EXTI_LINE48 ((uint32_t)0x30)
#define | EXTI_LINE49 ((uint32_t)0x31)
#define | EXTI_LINE50 ((uint32_t)0x32)
#define | EXTI_LINE51 ((uint32_t)0x33)
#define | EXTI_LINE52 ((uint32_t)0x34)
#define | EXTI_LINE53 ((uint32_t)0x35)
#define | EXTI_LINE54 ((uint32_t)0x36)
#define | EXTI_LINE55 ((uint32_t)0x37)
#define | EXTI_LINE56 ((uint32_t)0x38)
#define | EXTI_LINE57 ((uint32_t)0x39)
#define | EXTI_LINE58 ((uint32_t)0x3A)
#define | EXTI_LINE59 ((uint32_t)0x3B)
#define | EXTI_LINE60 ((uint32_t)0x3C)
#define | EXTI_LINE61 ((uint32_t)0x3D)
#define | EXTI_LINE62 ((uint32_t)0x3E)
#define | EXTI_LINE63 ((uint32_t)0x3F)
#define | EXTI_LINE64 ((uint32_t)0x40)
#define | EXTI_LINE65 ((uint32_t)0x41)
#define | EXTI_LINE66 ((uint32_t)0x42)
#define | EXTI_LINE67 ((uint32_t)0x43)
#define | EXTI_LINE68 ((uint32_t)0x44)
#define | EXTI_LINE69 ((uint32_t)0x45)
#define | EXTI_LINE70 ((uint32_t)0x46)
#define | EXTI_LINE71 ((uint32_t)0x47)
#define | EXTI_LINE72 ((uint32_t)0x48)
#define | EXTI_LINE73 ((uint32_t)0x49)
#define | EXTI_LINE74 ((uint32_t)0x4A)
#define | EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */
#define | EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */
#define | EXTI_LINE85 ((uint32_t)0x55)
#define | EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */
#define | EXTI_LINE87 ((uint32_t)0x57)
#define | EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */
#define | IS_HAL_EXTI_CONFIG_LINE(LINE)
#define | IS_EXTI_ALL_LINE(LINE)
#define | IS_EXTI_D1_LINE(LINE)
#define | IS_EXTI_D3_LINE(LINE)
#define | BDMA_CH6_CLEAR ((uint32_t)0x00000000)
#define | BDMA_CH7_CLEAR ((uint32_t)0x00000001)
#define | LPTIM2_OUT_CLEAR ((uint32_t)0x00000002)
#define | LPTIM3_OUT_CLEAR ((uint32_t)0x00000003)
#define | IS_EXTI_D3_CLEAR(SOURCE)

Define Documentation

#define BDMA_CH6_CLEAR ((uint32_t)0x00000000)

BDMA ch6 event selected as D3 domain pendclear source

Definition at line 630 of file stm32h7xx_hal.h.

#define BDMA_CH7_CLEAR ((uint32_t)0x00000001)

BDMA ch7 event selected as D3 domain pendclear source

Definition at line 631 of file stm32h7xx_hal.h.

#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)

Definition at line 216 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

#define EXTI_LINE0 ((uint32_t)0x00)

External interrupt LINE 0

Definition at line 221 of file stm32h7xx_hal.h.

#define EXTI_LINE1 ((uint32_t)0x01)

External interrupt LINE 1

Definition at line 222 of file stm32h7xx_hal.h.

#define EXTI_LINE10 ((uint32_t)0x0A)

External interrupt LINE 10

Definition at line 231 of file stm32h7xx_hal.h.

#define EXTI_LINE11 ((uint32_t)0x0B)

External interrupt LINE 11

Definition at line 232 of file stm32h7xx_hal.h.

#define EXTI_LINE12 ((uint32_t)0x0C)

External interrupt LINE 12

Definition at line 233 of file stm32h7xx_hal.h.

#define EXTI_LINE13 ((uint32_t)0x0D)

External interrupt LINE 13

Definition at line 234 of file stm32h7xx_hal.h.

#define EXTI_LINE14 ((uint32_t)0x0E)

External interrupt LINE 14

Definition at line 235 of file stm32h7xx_hal.h.

#define EXTI_LINE15 ((uint32_t)0x0F)

External interrupt LINE 15

Definition at line 236 of file stm32h7xx_hal.h.

#define EXTI_LINE16 ((uint32_t)0x10)

Definition at line 237 of file stm32h7xx_hal.h.

#define EXTI_LINE17 ((uint32_t)0x11)

Definition at line 238 of file stm32h7xx_hal.h.

#define EXTI_LINE18 ((uint32_t)0x12)

Definition at line 239 of file stm32h7xx_hal.h.

#define EXTI_LINE19 ((uint32_t)0x13)

Definition at line 240 of file stm32h7xx_hal.h.

#define EXTI_LINE2 ((uint32_t)0x02)

External interrupt LINE 2

Definition at line 223 of file stm32h7xx_hal.h.

#define EXTI_LINE20 ((uint32_t)0x14)

Definition at line 241 of file stm32h7xx_hal.h.

#define EXTI_LINE21 ((uint32_t)0x15)

Definition at line 242 of file stm32h7xx_hal.h.

#define EXTI_LINE22 ((uint32_t)0x16)

Definition at line 243 of file stm32h7xx_hal.h.

#define EXTI_LINE23 ((uint32_t)0x17)

Definition at line 244 of file stm32h7xx_hal.h.

#define EXTI_LINE24 ((uint32_t)0x18)

Definition at line 245 of file stm32h7xx_hal.h.

#define EXTI_LINE25 ((uint32_t)0x19)

Definition at line 246 of file stm32h7xx_hal.h.

#define EXTI_LINE26 ((uint32_t)0x1A)

Definition at line 247 of file stm32h7xx_hal.h.

#define EXTI_LINE27 ((uint32_t)0x1B)

Definition at line 248 of file stm32h7xx_hal.h.

#define EXTI_LINE28 ((uint32_t)0x1C)

Definition at line 249 of file stm32h7xx_hal.h.

#define EXTI_LINE29 ((uint32_t)0x1D)

Definition at line 250 of file stm32h7xx_hal.h.

#define EXTI_LINE3 ((uint32_t)0x03)

External interrupt LINE 3

Definition at line 224 of file stm32h7xx_hal.h.

#define EXTI_LINE30 ((uint32_t)0x1E)

Definition at line 251 of file stm32h7xx_hal.h.

#define EXTI_LINE31 ((uint32_t)0x1F)

Definition at line 252 of file stm32h7xx_hal.h.

#define EXTI_LINE32 ((uint32_t)0x20)

Definition at line 253 of file stm32h7xx_hal.h.

#define EXTI_LINE33 ((uint32_t)0x21)

Definition at line 254 of file stm32h7xx_hal.h.

#define EXTI_LINE34 ((uint32_t)0x22)

Definition at line 255 of file stm32h7xx_hal.h.

#define EXTI_LINE35 ((uint32_t)0x23)

Definition at line 256 of file stm32h7xx_hal.h.

#define EXTI_LINE36 ((uint32_t)0x24)

Definition at line 257 of file stm32h7xx_hal.h.

#define EXTI_LINE37 ((uint32_t)0x25)

Definition at line 258 of file stm32h7xx_hal.h.

#define EXTI_LINE38 ((uint32_t)0x26)

Definition at line 259 of file stm32h7xx_hal.h.

#define EXTI_LINE39 ((uint32_t)0x27)

Definition at line 260 of file stm32h7xx_hal.h.

#define EXTI_LINE4 ((uint32_t)0x04)

External interrupt LINE 4

Definition at line 225 of file stm32h7xx_hal.h.

#define EXTI_LINE40 ((uint32_t)0x28)

Definition at line 262 of file stm32h7xx_hal.h.

#define EXTI_LINE41 ((uint32_t)0x29)

Definition at line 263 of file stm32h7xx_hal.h.

#define EXTI_LINE42 ((uint32_t)0x2A)

Definition at line 264 of file stm32h7xx_hal.h.

#define EXTI_LINE43 ((uint32_t)0x2B)

Definition at line 265 of file stm32h7xx_hal.h.

#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */

Definition at line 266 of file stm32h7xx_hal.h.

#define EXTI_LINE47 ((uint32_t)0x2F)

Definition at line 273 of file stm32h7xx_hal.h.

#define EXTI_LINE48 ((uint32_t)0x30)

Definition at line 274 of file stm32h7xx_hal.h.

#define EXTI_LINE49 ((uint32_t)0x31)

Definition at line 275 of file stm32h7xx_hal.h.

#define EXTI_LINE5 ((uint32_t)0x05)

External interrupt LINE 5

Definition at line 226 of file stm32h7xx_hal.h.

#define EXTI_LINE50 ((uint32_t)0x32)

Definition at line 276 of file stm32h7xx_hal.h.

#define EXTI_LINE51 ((uint32_t)0x33)

Definition at line 277 of file stm32h7xx_hal.h.

#define EXTI_LINE52 ((uint32_t)0x34)

Definition at line 278 of file stm32h7xx_hal.h.

#define EXTI_LINE53 ((uint32_t)0x35)

Definition at line 279 of file stm32h7xx_hal.h.

#define EXTI_LINE54 ((uint32_t)0x36)

Definition at line 280 of file stm32h7xx_hal.h.

#define EXTI_LINE55 ((uint32_t)0x37)

Definition at line 281 of file stm32h7xx_hal.h.

#define EXTI_LINE56 ((uint32_t)0x38)

Definition at line 282 of file stm32h7xx_hal.h.

#define EXTI_LINE57 ((uint32_t)0x39)

Definition at line 283 of file stm32h7xx_hal.h.

#define EXTI_LINE58 ((uint32_t)0x3A)

Definition at line 284 of file stm32h7xx_hal.h.

#define EXTI_LINE59 ((uint32_t)0x3B)

Definition at line 285 of file stm32h7xx_hal.h.

#define EXTI_LINE6 ((uint32_t)0x06)

External interrupt LINE 6

Definition at line 227 of file stm32h7xx_hal.h.

#define EXTI_LINE60 ((uint32_t)0x3C)

Definition at line 286 of file stm32h7xx_hal.h.

#define EXTI_LINE61 ((uint32_t)0x3D)

Definition at line 287 of file stm32h7xx_hal.h.

#define EXTI_LINE62 ((uint32_t)0x3E)

Definition at line 288 of file stm32h7xx_hal.h.

#define EXTI_LINE63 ((uint32_t)0x3F)

Definition at line 289 of file stm32h7xx_hal.h.

#define EXTI_LINE64 ((uint32_t)0x40)

Definition at line 290 of file stm32h7xx_hal.h.

#define EXTI_LINE65 ((uint32_t)0x41)

Definition at line 291 of file stm32h7xx_hal.h.

#define EXTI_LINE66 ((uint32_t)0x42)

Definition at line 292 of file stm32h7xx_hal.h.

#define EXTI_LINE67 ((uint32_t)0x43)

Definition at line 293 of file stm32h7xx_hal.h.

#define EXTI_LINE68 ((uint32_t)0x44)

Definition at line 294 of file stm32h7xx_hal.h.

#define EXTI_LINE69 ((uint32_t)0x45)

Definition at line 295 of file stm32h7xx_hal.h.

#define EXTI_LINE7 ((uint32_t)0x07)

External interrupt LINE 7

Definition at line 228 of file stm32h7xx_hal.h.

#define EXTI_LINE70 ((uint32_t)0x46)

Definition at line 296 of file stm32h7xx_hal.h.

#define EXTI_LINE71 ((uint32_t)0x47)

Definition at line 297 of file stm32h7xx_hal.h.

#define EXTI_LINE72 ((uint32_t)0x48)

Definition at line 298 of file stm32h7xx_hal.h.

#define EXTI_LINE73 ((uint32_t)0x49)

Definition at line 299 of file stm32h7xx_hal.h.

#define EXTI_LINE74 ((uint32_t)0x4A)

Definition at line 300 of file stm32h7xx_hal.h.

#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */

Definition at line 301 of file stm32h7xx_hal.h.

#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */

Definition at line 302 of file stm32h7xx_hal.h.

#define EXTI_LINE8 ((uint32_t)0x08)

External interrupt LINE 8

Definition at line 229 of file stm32h7xx_hal.h.

#define EXTI_LINE85 ((uint32_t)0x55)

Definition at line 326 of file stm32h7xx_hal.h.

#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */

Definition at line 327 of file stm32h7xx_hal.h.

#define EXTI_LINE87 ((uint32_t)0x57)

Definition at line 328 of file stm32h7xx_hal.h.

#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */

Definition at line 329 of file stm32h7xx_hal.h.

#define EXTI_LINE9 ((uint32_t)0x09)

External interrupt LINE 9

Definition at line 230 of file stm32h7xx_hal.h.

#define EXTI_MODE_EVT ((uint32_t)0x00020000)

Definition at line 214 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define EXTI_MODE_IT ((uint32_t)0x00010000)

Definition at line 213 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define EXTI_RISING_EDGE ((uint32_t)0x00100000)

Definition at line 215 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

#define IS_EXTI_ALL_LINE ( LINE )

Definition at line 407 of file stm32h7xx_hal.h.

#define IS_EXTI_D1_LINE ( LINE )

Definition at line 493 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_ClearFlag(), and HAL_EXTI_D1_EventInputConfig().

#define IS_EXTI_D3_CLEAR ( SOURCE )
Value:
(((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))

Definition at line 646 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D3_EventInputConfig().

#define IS_EXTI_D3_LINE ( LINE )
Value:
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))

Definition at line 613 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D3_EventInputConfig().

#define IS_EXTI_EDGE_LINE ( EDGE ) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))

Definition at line 218 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

#define IS_EXTI_MODE_LINE ( MODE ) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))

Definition at line 219 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define IS_HAL_EXTI_CONFIG_LINE ( LINE )
Value:
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))

Definition at line 347 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig(), and HAL_EXTI_GenerateSWInterrupt().

#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002)

LPTIM2 out selected as D3 domain pendclear source

Definition at line 635 of file stm32h7xx_hal.h.

#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003)

LPTIM3 out selected as D3 domain pendclear source

Definition at line 640 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SwapBankMapping Config

Defines
SwapBankMapping Config
HAL

Defines

#define | FMC_SWAPBMAP_DISABLE (0x00000000U)
#define | FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
#define | FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
#define | IS_FMC_SWAPBMAP_MODE(__MODE__)

Define Documentation

#define FMC_SWAPBMAP_DISABLE (0x00000000U)

Definition at line 657 of file stm32h7xx_hal.h.

#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0

Definition at line 658 of file stm32h7xx_hal.h.

#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1

Definition at line 659 of file stm32h7xx_hal.h.

#define IS_FMC_SWAPBMAP_MODE ( __MODE__ )
Value:
(((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))

Definition at line 661 of file stm32h7xx_hal.h.

Referenced by HAL_SetFMCMemorySwappingConfig().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ART Exported Macros

ART Exported Macros
HAL
Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG Exported Macros

Defines
SYSCFG Exported Macros
HAL

Defines

#define | __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
SYSCFG Break AXIRAM double ECC lock.
#define | __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
SYSCFG Break ITCM double ECC lock.
#define | __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
SYSCFG Break DTCM double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
SYSCFG Break SRAM1 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
SYSCFG Break SRAM2 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
SYSCFG Break SRAM3 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
SYSCFG Break SRAM4 double ECC lock.
#define | __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
SYSCFG Break Backup SRAM double ECC lock.
#define | __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
SYSCFG Break Cortex-M7 Lockup lock.
#define | __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
SYSCFG Break FLASH double ECC lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Define Documentation

#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)

SYSCFG Break AXIRAM double ECC lock.

Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 704 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)

SYSCFG Break Backup SRAM double ECC lock.

Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 753 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)

SYSCFG Break Cortex-M7 Lockup lock.

Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 760 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)

SYSCFG Break DTCM double ECC lock.

Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 718 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)

SYSCFG Break FLASH double ECC lock.

Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 767 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)

SYSCFG Break ITCM double ECC lock.

Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 711 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)

SYSCFG Break PVD lock.

Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 774 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)

SYSCFG Break SRAM1 double ECC lock.

Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 725 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)

SYSCFG Break SRAM2 double ECC lock.

Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 732 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)

SYSCFG Break SRAM3 double ECC lock.

Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 739 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)

SYSCFG Break SRAM4 double ECC lock.

Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 746 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
                                                               }while(0)

Definition at line 797 of file stm32h7xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
                                                               }while(0)

Fast-mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__ This parameter can be a value of :
  • SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
  • SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
  • SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
  • SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

Definition at line 793 of file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL Private Macros

Defines
HAL Private Macros
HAL

Defines

#define IS_TICKFREQ(FREQ)

Define Documentation

#define IS_TICKFREQ ( FREQ )
Value:
(((FREQ) == HAL_TICK_FREQ_10HZ)  || \
                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
                           ((FREQ) == HAL_TICK_FREQ_1KHZ))

Definition at line 955 of file stm32h7xx_hal.h.

Referenced by HAL_SetTickFreq().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL

Modules | Defines | Functions
HAL
STM32H7xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Variables
HAL Private Functions
Tick Frequency
device revision ID
VREFBUF Voltage Scale
VREFBUF High Impedance
Fast-mode Plus on GPIO
Ethernet Config
Analog Switch Config
Boot Config
IOCompenstionCell Config
Event Input Config
SwapBankMapping Config
ART Exported Macros
SYSCFG Exported Macros
HAL Private Macros

Defines

#define | __STM32H7xx_HAL_VERSION_MAIN (0x01UL)
STM32H7xx HAL Driver version number V1.7.0RC2.
#define | __STM32H7xx_HAL_VERSION_SUB1 (0x07UL)
#define | __STM32H7xx_HAL_VERSION_SUB2 (0x00UL)
#define | __STM32H7xx_HAL_VERSION_RC (0x02UL)
#define | __STM32H7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
#define | __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
#define | __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
#define | __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
void | HAL_MspInit (void)
Initializes the MSP.
void | HAL_MspDeInit (void)
DeInitializes the MSP.
HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
Return tick frequency.
void | HAL_SuspendTick (void)
Suspend Tick increment.
void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_VDDMMC_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).

Detailed Description

HAL module driver.

Define Documentation

#define __HAL_DBGMCU_FREEZE_FDCAN ( ) (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))

Definition at line 823 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_HRTIM ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))

Definition at line 831 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))

Definition at line 820 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))

Definition at line 821 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))

Definition at line 822 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C4 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))

Definition at line 833 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG1 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))

Definition at line 839 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))

Definition at line 819 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM2 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))

Definition at line 834 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM3 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))

Definition at line 835 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM4 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))

Definition at line 836 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM5 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))

Definition at line 837 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))

Definition at line 838 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))

Definition at line 826 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM12 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))

Definition at line 816 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM13 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))

Definition at line 817 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))

Definition at line 818 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))

Definition at line 828 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))

Definition at line 829 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))

Definition at line 830 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))

Definition at line 810 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))

Definition at line 811 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))

Definition at line 812 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))

Definition at line 813 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))

Definition at line 814 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))

Definition at line 815 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))

Definition at line 827 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG1 ( ) (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 808 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_FDCAN ( ) (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))

Definition at line 857 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_HRTIM ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))

Definition at line 865 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C1 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))

Definition at line 854 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C2 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))

Definition at line 855 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C3 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))

Definition at line 856 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C4 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))

Definition at line 867 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_IWDG1 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

Definition at line 873 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM1 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))

Definition at line 853 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM2 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))

Definition at line 868 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM3 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))

Definition at line 869 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM4 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))

Definition at line 870 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM5 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))

Definition at line 871 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_RTC ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))

Definition at line 872 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM1 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))

Definition at line 860 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM12 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))

Definition at line 850 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM13 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))

Definition at line 851 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM14 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))

Definition at line 852 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM15 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))

Definition at line 862 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM16 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))

Definition at line 863 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM17 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))

Definition at line 864 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM2 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))

Definition at line 844 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM3 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))

Definition at line 845 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM4 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))

Definition at line 846 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM5 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))

Definition at line 847 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM6 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))

Definition at line 848 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM7 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))

Definition at line 849 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM8 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))

Definition at line 861 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_WWDG1 ( ) (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))

Definition at line 842 of file stm32h7xx_hal.h.

#define __STM32H7xx_HAL_VERSION
Value:
((__STM32H7xx_HAL_VERSION_MAIN << 24)\
                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
                                        |(__STM32H7xx_HAL_VERSION_RC))

Definition at line 56 of file stm32h7xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL)

STM32H7xx HAL Driver version number V1.7.0RC2.

[31:24] main version

Definition at line 52 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_RC (0x02UL)

[7:0] release candidate

Definition at line 55 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL)

[23:16] sub1 version

Definition at line 53 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL)

[15:8] sub2 version

Definition at line 54 of file stm32h7xx_hal.c.

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Definition at line 61 of file stm32h7xx_hal.c.

Referenced by HAL_GetDEVID().

#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */

Definition at line 62 of file stm32h7xx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the systick.

This function is optional.

Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_AHB4_FORCE_RESET, __HAL_RCC_AHB4_RELEASE_RESET, __HAL_RCC_APB1H_FORCE_RESET, __HAL_RCC_APB1H_RELEASE_RESET, __HAL_RCC_APB1L_FORCE_RESET, __HAL_RCC_APB1L_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, __HAL_RCC_APB3_FORCE_RESET, __HAL_RCC_APB3_RELEASE_RESET, __HAL_RCC_APB4_FORCE_RESET, __HAL_RCC_APB4_RELEASE_RESET, and HAL_MspDeInit().

void HAL_Delay ( uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 417 of file stm32h7xx_hal.c.

References HAL_GetTick(), and uwTickFreq.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), HAL_DTS_Start(), HAL_DTS_Start_IT(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_PCDEx_BCD_VBUSDetect(), and HAL_SD_InitCard().

void HAL_DisableCompensationCell ( void )

Power-down the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 799 of file stm32h7xx_hal.c.

void HAL_DisableDBGSleepMode ( void )

Disable the Debug Module during Domain1/CDomain SLEEP mode.

Return values:
None

Definition at line 903 of file stm32h7xx_hal.c.

void HAL_DisableDBGStandbyMode ( void )

Disable the Debug Module during Domain1/CDomain STANDBY mode.

Return values:
None

Definition at line 940 of file stm32h7xx_hal.c.

void HAL_DisableDBGStopMode ( void )

Disable the Debug Module during Domain1/CDomain STOP mode.

Return values:
None

Definition at line 922 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStandbyMode ( void )

Disable the Debug Module during Domain3/SRDomain STANDBY mode.

Return values:
None

Definition at line 1031 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStopMode ( void )

Disable the Debug Module during Domain3/SRDomain STOP mode.

Return values:
None

Definition at line 1013 of file stm32h7xx_hal.c.

void HAL_EnableCompensationCell ( void )

Enables the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 788 of file stm32h7xx_hal.c.

void HAL_EnableDBGSleepMode ( void )

Enable the Debug Module during Domain1/CDomain SLEEP mode.

Return values:
None

Definition at line 894 of file stm32h7xx_hal.c.

void HAL_EnableDBGStandbyMode ( void )

Enable the Debug Module during Domain1/CDomain STANDBY mode.

Return values:
None

Definition at line 931 of file stm32h7xx_hal.c.

void HAL_EnableDBGStopMode ( void )

Enable the Debug Module during Domain1/CDomain STOP mode.

Return values:
None

Definition at line 913 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStandbyMode ( void )

Enable the Debug Module during Domain3/SRDomain STANDBY mode.

Return values:
None

Definition at line 1022 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStopMode ( void )

Enable the Debug Module during Domain3/SRDomain STOP mode.

Return values:
None

Definition at line 1005 of file stm32h7xx_hal.c.

void HAL_EXTI_D1_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
Return values:
None

Definition at line 1112 of file stm32h7xx_hal.c.

References assert_param, and IS_EXTI_D1_LINE.

void HAL_EXTI_D1_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Mode,
 |  | uint32_t | EXTI_LineCmd
 | ) |  |

Configure the EXTI input event line for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
EXTI_Mode,: Specifies which EXTI line is used as interrupt or an event. This parameter can be one or a combination of the following values :
  • EXTI_MODE_IT : Interrupt Mode selected
  • EXTI_MODE_EVT : Event Mode selected
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
Return values:
None

Definition at line 1147 of file stm32h7xx_hal.c.

References assert_param, EXTI_MODE_EVT, EXTI_MODE_IT, IS_EXTI_D1_LINE, and IS_EXTI_MODE_LINE.

void HAL_EXTI_D3_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_LineCmd,
 |  | uint32_t | EXTI_ClearSrc
 | ) |  |

Configure the EXTI input event line for Domain D3.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
EXTI_ClearSrc,: Specifies the clear source of D3 pending event. This parameter can be one of the following values :
  • BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
  • BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
  • LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
  • LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
Return values:
None

Definition at line 1241 of file stm32h7xx_hal.c.

References assert_param, IS_EXTI_D3_CLEAR, and IS_EXTI_D3_LINE.

void HAL_EXTI_EdgeConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Edge
 | ) |  |

Configure the EXTI input event line edge.

Note:
No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
EXTI_Edge,: Specifies EXTI line Edge used. This parameter can be one of the following values :
  • EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
  • EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
Return values:
None

Definition at line 1071 of file stm32h7xx_hal.c.

References assert_param, EXTI_FALLING_EDGE, EXTI_RISING_EDGE, IS_EXTI_EDGE_LINE, and IS_HAL_EXTI_CONFIG_LINE.

void HAL_EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt on selected EXTI line.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
Return values:
None

Definition at line 1097 of file stm32h7xx_hal.c.

References assert_param, and IS_HAL_EXTI_CONFIG_LINE.

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 487 of file stm32h7xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetFMCMemorySwappingConfig ( void )

Get FMC Bank mapping mode.

Return values:
The FMC Bank mapping mode. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2

Definition at line 1054 of file stm32h7xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 469 of file stm32h7xx_hal.c.

References __STM32H7xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 478 of file stm32h7xx_hal.c.

Referenced by ADC_ConfigureBoostMode(), HAL_ADC_Init(), HAL_CRYP_Init(), HAL_RCC_GetOscConfig(), HAL_RCCEx_CRSConfig(), and HAL_SAI_Init().

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 351 of file stm32h7xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_WaitOnOFNEFlag(), DelayBlock_Enable(), FLASH_CRC_WaitForLastOperation(), FLASH_OB_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_Suspend(), HAL_DMA_Abort(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DTS_Start(), HAL_DTS_Start_IT(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_TT_ConfigOperation(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_I2S_DMAPause(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Encode(), HAL_MDMA_Abort(), HAL_MDMA_Init(), HAL_MDMA_PollForTransfer(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ReadBlocks(), HAL_MMC_WriteBlocks(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), HAL_NAND_Write_SpareArea_8b(), HAL_NOR_GetStatus(), HAL_OSPI_Abort(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Transmit(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PSSI_Receive(), HAL_PSSI_Transmit(), HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), HAL_PWREx_EnableUSBReg(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), HAL_RNGEx_SetConfig(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetActiveSeed(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SWPMI_Init(), HAL_SWPMI_Receive(), HAL_SWPMI_Transmit(), HAL_SYSCFG_EnableVREFBUF(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), HASH_WaitOnFlagUntilTimeout(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), MMC_ReadExtCSD(), PSSI_WaitOnStatusUntilTimeout(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), RTC_EnterInitMode(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_PowerON(), SD_SendSDStatus(), SD_UltraHighSpeed(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPDIFRX_WaitOnFlagUntilTimeout(), SPI_WaitOnFlagUntilTimeout(), SWPMI_DMATransmitCplt(), SWPMI_WaitOnFlagSetUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

HAL_TickFreqTypeDef HAL_GetTickFreq ( void )

Return tick frequency.

Return values:
tick period in Hz

Definition at line 401 of file stm32h7xx_hal.c.

References uwTickFreq.

uint32_t HAL_GetTickPrio ( void )

This function returns a tick priority.

Return values:
tick priority

Definition at line 360 of file stm32h7xx_hal.c.

References uwTickPrio.

uint32_t HAL_GetUIDw0 ( void )

Return the first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 496 of file stm32h7xx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Return the second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 505 of file stm32h7xx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Return the third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 514 of file stm32h7xx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 340 of file stm32h7xx_hal.c.

References uwTick, and uwTickFreq.

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).

Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32h7xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 134 of file stm32h7xx_hal.c.

References HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), HAL_RCC_GetSysClockFreq(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 254 of file stm32h7xx_hal.c.

References CM7_CPUID, HAL_GetCurrentCPUID(), HAL_NVIC_SetPriority(), HAL_RCC_GetHCLKFreq(), HAL_SYSTICK_Config(), uwTickFreq, and uwTickPrio.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), and HAL_SetTickFreq().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 231 of file stm32h7xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 220 of file stm32h7xx_hal.c.

Referenced by HAL_Init().

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 459 of file stm32h7xx_hal.c.

void HAL_SetFMCMemorySwappingConfig ( uint32_t BankMapConfig )

Set the FMC Memory Mapping Swapping config.

Parameters:
BankMapConfig,: Defines the FMC Bank mapping configuration. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
Return values:
HAL state

Definition at line 1042 of file stm32h7xx_hal.c.

References assert_param, and IS_FMC_SWAPBMAP_MODE.

HAL_StatusTypeDef HAL_SetTickFreq ( HAL_TickFreqTypeDef Freq )

Set new tick Freq.

Return values:
Status

Definition at line 369 of file stm32h7xx_hal.c.

References assert_param, HAL_InitTick(), IS_TICKFREQ, uwTickFreq, and uwTickPrio.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 443 of file stm32h7xx_hal.c.

void HAL_SYSCFG_AnalogSwitchConfig | ( | uint32_t | SYSCFG_AnalogSwitch,
 |  | uint32_t | SYSCFG_SwitchState
 | ) |  |

Analog Switch control for dual analog pads.

Parameters:
SYSCFG_AnalogSwitch,: Selects the analog pad This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0 : Select PA0 analog switch
  • SYSCFG_SWITCH_PA1: Select PA1 analog switch
  • SYSCFG_SWITCH_PC2 : Select PC2 analog switch
  • SYSCFG_SWITCH_PC3: Select PC3 analog switch
SYSCFG_SwitchState,: Open or Close the analog switch between dual pads (PXn and PXn_C) This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0_OPEN
  • SYSCFG_SWITCH_PA0_CLOSE
  • SYSCFG_SWITCH_PA1_OPEN
  • SYSCFG_SWITCH_PA1_CLOSE
  • SYSCFG_SWITCH_PC2_OPEN
  • SYSCFG_SWITCH_PC2_CLOSE
  • SYSCFG_SWITCH_PC3_OPEN
  • SYSCFG_SWITCH_PC3_CLOSE
Return values:
None

Definition at line 643 of file stm32h7xx_hal.c.

References assert_param, IS_SYSCFG_ANALOG_SWITCH, and IS_SYSCFG_SWITCH_STATE.

void HAL_SYSCFG_CompensationCodeConfig | ( | uint32_t | SYSCFG_PMOSCode,
 |  | uint32_t | SYSCFG_NMOSCode
 | ) |  |

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_PMOSCode,: PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
SYSCFG_NMOSCode,: NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 862 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_CONFIG.

void HAL_SYSCFG_CompensationCodeSelect ( uint32_t SYSCFG_CompCode )

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_CompCode,: Selects the code to be applied for the I/O compensation cell This parameter can be one of the following values:
  • SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
  • SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
Return values:
None

Definition at line 845 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_SELECT.

void HAL_SYSCFG_DisableIOSpeedOptimize ( void )

To Disable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 828 of file stm32h7xx_hal.c.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 599 of file stm32h7xx_hal.c.

void HAL_SYSCFG_EnableIOSpeedOptimize ( void )

To Enable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 812 of file stm32h7xx_hal.c.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 573 of file stm32h7xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_VDDMMC_CompensationCodeConfig | ( | uint32_t | SYSCFG_PMOSCode,
 |  | uint32_t | SYSCFG_NMOSCode
 | ) |  |

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_PMOSCode,: VDDMMC PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
SYSCFG_NMOSCode,: VDDMMC NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 881 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_CONFIG.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
Return values:
None

Definition at line 549 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 561 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V. This requires VDDA equal to or higher than 1.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V. This requires VDDA equal to or higher than 2.1 V.
Return values:
None

Definition at line 533 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR2_FIELDS
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)

Define Documentation

#define ADC_CFGR2_FIELDS
Value:
((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
                                       ADC_CFGR2_ROVSM))

ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 330 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_FIELDS_1
Value:
((uint32_t)(ADC_CFGR_RES    |\
                                       ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                                       ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))

ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going

Definition at line 324 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)

ADC conversion completion time-out value

Definition at line 349 of file stm32h7xx_hal_adc.c.

Referenced by ADC_ConversionStop().

#define ADC_DISABLE_TIMEOUT (2UL)

ADC disable time-out value

Definition at line 340 of file stm32h7xx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT (2UL)

ADC enable time-out value

Definition at line 339 of file stm32h7xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_STAB_DELAY_US ((uint32_t) 10)

ADC voltage regulator startup time

Definition at line 1047 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADCEx_LinearCalibration_SetValue().

#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL)

ADC stop time-out value

Definition at line 1037 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

Definition at line 1042 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

ADC Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Detailed Description

ADC Initialization and Configuration functions.

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
For devices with several ADCs: reset of ADC common registers is done only if all ADCs sharing the same common group are disabled. (function "HAL_ADC_MspDeInit()" is also called under the same conditions: all ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances). If this is not the case, reset of these common parameters reset is bypassed without error reporting: it can be the intended behavior in case of reset of a single ADC while the other ADCs sharing the same common group is still running.
By default, HAL_ADC_DeInit() set ADC in mode deep power-down: this saves more power by reducing leakage currents and is particularly interesting before entering MCU low-power modes.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 734 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CLEAR_COMMON_CONTROL_REGISTER, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_IT_RDY, ADC_REGULAR_INJECTED_GROUP, ADC_SMPR1_FIELDS, assert_param, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, __ADC_HandleTypeDef::MspDeInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (refer to description of RCC configuration for ADC in header of this file).
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters related to common ADC registers (ADC clock mode) are set only if all ADCs are disabled. If this is not the case, these common parameters setting are bypassed without error reporting: it can be the intended behaviour in case of update of a parameter of ADC_InitTypeDef on the fly, without disabling the other ADCs.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 406 of file stm32h7xx_hal_adc.c.

References __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CFGR2_FIELDS, ADC_CFGR_AUTOWAIT, ADC_CFGR_CONTINUOUS, ADC_CFGR_DISCONTINUOUS_NUM, ADC_CFGR_DMACONTREQ, ADC_CFGR_FIELDS_1, ADC_CFGR_FIELDS_2, ADC_CFGR_REG_DISCONTINUOUS, ADC_CLEAR_ERRORCODE, ADC_ConfigureBoostMode(), ADC_EXTERNALTRIGCONVEDGE_NONE, ADC_RESOLUTION_8B, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SOFTWARE_START, ADC_STATE_CLR_SET, ADC_TRIGGEREDMODE_SINGLE_TRIGGER, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, ADC_InitTypeDef::ConversionDataManagement, __ADC_HandleTypeDef::ConvHalfCpltCallback, ADC_InitTypeDef::DiscontinuousConvMode, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ConvCpltCallback(), HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), HAL_GetREVID(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_CONVERSIONDATAMGT, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGOVERSAMPLING_MODE, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SCAN_MODE, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, ADC_InitTypeDef::LeftBitShift, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_DELAY_INTERNAL_REGUL_STAB_US, LL_ADC_DisableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsDeepPowerDownEnabled(), LL_ADC_IsEnabled(), LL_ADC_IsInternalRegulatorEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCommonClock(), __ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoWait, __ADC_HandleTypeDef::MspInitCallback, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::OversamplingStopReset, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, REV_ID_Y, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, __ADC_HandleTypeDef::State, and ADC_OversamplingTypeDef::TriggeredMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc ADC handle
Note:
All ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances).
Return values:
None

Definition at line 961 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 944 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_RegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID,
 |  | pADC_CallbackTypeDef | pCallback
 | ) |  |

Register a User ADC Callback To be used instead of the weak predefined callback.

Parameters:
hadc | Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 993 of file stm32h7xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_UnRegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Parameters:
hadc Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
Return values:
HAL status

Definition at line 1115 of file stm32h7xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_ErrorCallback(), HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspDeInit(), HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MspInit(), HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Input and Output operation functions

Functions
ADC Input and Output operation functions
ADC Exported Functions

ADC IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

ADC IO operation functions.

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2546 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2561 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Note:
In case of error due to overrun when using ADC with DMA transfer (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  • Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  • If needed, restart a new ADC conversion using function "HAL_ADC_Start_DMA()" (this function is also clearing overrun flag)
Parameters:
hadc ADC handle
Return values:
None

Definition at line 2598 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc ADC handle
Return values:
ADC group regular conversion data

Definition at line 2171 of file stm32h7xx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2188 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_GetMultiDMATransfer(), LL_ADC_GetMultimode(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2576 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function, with an exception: if low power feature "LowPowerAutoWait" is enabled, flags are not cleared to not interfere with this feature until data register is read using function HAL_ADC_GetValue().
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence (ADC init parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1421 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultiDMATransfer(), LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
  • ADC_OVR_EVENT ADC Overrun event
  • ADC_JQOVF_EVENT ADC Injected context queue overflow event
Timeout | Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1580 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_JQOVF_EVENT, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled (when multimode feature is available): if ADC is Slave, ADC is enabled but conversion is not started, if ADC is master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1246 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
Parameters:
hadc | ADC handle
pData | Destination Buffer address.
Length | Number of data to be transferred from ADC peripheral to memory
Return values:
HAL status.

Definition at line 1953 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ConversionDataManagement, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_SetDataTransferMode(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_IT() must be called for ADC Slave first, then for ADC Master. For ADC Slave, ADC is enabled only (conversion is not started). For ADC Master, ADC is enabled and multimode conversion is started.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() does not enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must: 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1725 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1367 of file stm32h7xx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on ADC group injected. If ADC group injected is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2086 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_DMA_STATE_BUSY, __ADC_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1900 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
On this STM32 serie, analog watchdog thresholds cannot be modified while ADC conversion is on going.
Parameters:
hadc | ADC handle
AnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2893 of file stm32h7xx_hal_adc.c.

References __LL_ADC_ANALOGWD_CHANNEL_GROUP, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_ALL_INJEC, ADC_ANALOGWATCHDOG_ALL_REG, ADC_ANALOGWATCHDOG_ALL_REGINJEC, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_AWD23THRESHOLD_SHIFT_RESOLUTION, ADC_GET_RESOLUTION, assert_param, ADC_AnalogWDGConfTypeDef::Channel, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_CONFIG, ADC_AnalogWDGConfTypeDef::HighThreshold, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ, LL_ADC_AWD_ALL_CHANNELS_REG, LL_ADC_AWD_ALL_CHANNELS_REG_INJ, LL_ADC_AWD_DISABLE, LL_ADC_ClearFlag_AWD1(), LL_ADC_ClearFlag_AWD2(), LL_ADC_ClearFlag_AWD3(), LL_ADC_DisableIT_AWD1(), LL_ADC_DisableIT_AWD2(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD1(), LL_ADC_EnableIT_AWD2(), LL_ADC_EnableIT_AWD3(), LL_ADC_GROUP_INJECTED, LL_ADC_GROUP_REGULAR, LL_ADC_GROUP_REGULAR_INJECTED, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetAnalogWDMonitChannels(), ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::Ratio, __ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configure a channel to be assigned to ADC group regular.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into ADC group regular, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
sConfig | Structure of ADC channel assigned to ADC group regular.
Return values:
HAL status

Definition at line 2644 of file stm32h7xx_hal_adc.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_GET_RESOLUTION, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_OFR_CHANNEL, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC1_DIFF_CHANNEL, IS_ADC2_DIFF_CHANNEL, IS_ADC3_DIFF_CHANNEL, IS_ADC_CHANNEL, IS_ADC_OFFSET_NUMBER, IS_ADC_RANGE, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_RSHIFT_DISABLE, LL_ADC_OFFSET_RSHIFT_ENABLE, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE, LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetDataRightShift(), LL_ADC_SetOffset(), LL_ADC_SetOffsetSignedSaturation(), ADC_ChannelConfTypeDef::Offset, ADC_ChannelConfTypeDef::OffsetNumber, ADC_ChannelConfTypeDef::OffsetRightShift, ADC_ChannelConfTypeDef::OffsetSignedSaturation, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_ChannelConfTypeDef::Rank, ADC_OversamplingTypeDef::Ratio, ADC_ChannelConfTypeDef::SamplingTime, ADC_ChannelConfTypeDef::SingleDiff, and __ADC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc ADC handle
Return values:
ADC error code (bitfield on 32 bits)

Definition at line 3178 of file stm32h7xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, and __ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Note:
ADC state machine is managed by bitfields, ADC status must be compared with states bits. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
Parameters:
hadc ADC handle
Return values:
ADC handle state (bitfield on 32 bits)

Definition at line 3164 of file stm32h7xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
void | ADC_ConfigureBoostMode (ADC_HandleTypeDef *hadc)
Configure boost mode of selected ADC.

Function Documentation

void ADC_ConfigureBoostMode ( ADC_HandleTypeDef * hadc )

Configure boost mode of selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
None.

Definition at line 3593 of file stm32h7xx_hal_adc.c.

References ADC_CLOCK_ASYNC_DIV10, ADC_CLOCK_ASYNC_DIV12, ADC_CLOCK_ASYNC_DIV128, ADC_CLOCK_ASYNC_DIV16, ADC_CLOCK_ASYNC_DIV2, ADC_CLOCK_ASYNC_DIV256, ADC_CLOCK_ASYNC_DIV32, ADC_CLOCK_ASYNC_DIV4, ADC_CLOCK_ASYNC_DIV6, ADC_CLOCK_ASYNC_DIV64, ADC_CLOCK_ASYNC_DIV8, ADC_CLOCK_SYNC_PCLK_DIV1, ADC_CLOCK_SYNC_PCLK_DIV2, ADC_CLOCK_SYNC_PCLK_DIV4, ADC_IS_SYNCHRONOUS_CLOCK_MODE, ADC_InitTypeDef::ClockPrescaler, HAL_GetREVID(), HAL_RCC_GetHCLKFreq(), HAL_RCCEx_GetPeriphCLKFreq(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, RCC_PERIPHCLK_ADC, and REV_ID_Y.

Referenced by HAL_ADC_Init().

HAL_StatusTypeDef ADC_ConversionStop | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | ConversionGroup
 | ) |  |

Stop ADC conversion.

Parameters:
hadc ADC handle
ConversionGroup ADC group regular and/or injected. This parameter can be one of the following values:
  • ADC_REGULAR_GROUP ADC regular conversion type.
  • ADC_INJECTED_GROUP ADC injected conversion type.
  • ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
Return values:
HAL status.

Definition at line 3208 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_CONVERSION_TIME_MAX_CPU_CYCLES, ADC_FLAG_JEOS, ADC_INJECTED_GROUP, ADC_REGULAR_GROUP, ADC_REGULAR_INJECTED_GROUP, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CONVERSION_GROUP, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StopConversion(), LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StopConversion(), ADC_InitTypeDef::LowPowerAutoWait, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 3413 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_DISABLE_TIMEOUT, ADC_FLAG_EOSMP, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3471 of file stm32h7xx_hal_adc.c.

References ADC_FLAG_EOS, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCallback, HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsTriggerSourceSWStart(), __ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3567 of file stm32h7xx_hal_adc.c.

References __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3549 of file stm32h7xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvHalfCpltCallback, and HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 3338 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_ENABLE_TIMEOUT, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Enable(), LL_ADC_GetMultimode(), LL_ADC_IsEnabled(), LL_ADC_MULTI_INDEPENDENT, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Define Documentation

#define HAL_ADC_STATE_AWD1 (0x00010000UL)

Out-of-window occurrence of ADC analog watchdog 1

Definition at line 346 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 (0x00020000UL)

Out-of-window occurrence of ADC analog watchdog 2

Definition at line 347 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 (0x00040000UL)

Out-of-window occurrence of ADC analog watchdog 3

Definition at line 348 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)

ADC is busy due to an internal process (initialization, calibration)

Definition at line 324 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)

Configuration error occurrence

Definition at line 329 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL)

DMA error occurrence

Definition at line 330 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)

Internal error occurrence

Definition at line 328 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL)

A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 340 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_INJ_EOC (0x00002000UL)

Conversion data available on group injected

Definition at line 342 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)

Injected queue overflow occurrence

Definition at line 343 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADCEx_EnableInjectedQueue().

#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 351 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_READY (0x00000001UL)

ADC peripheral ready for use

Definition at line 323 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_BUSY (0x00000100UL)

A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 333 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_EOC (0x00000200UL)

Conversion data available on group regular

Definition at line 335 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL)

Not available on this STM32 serie: End Of Sampling flag raised

Definition at line 337 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR (0x00000400UL)

Overrun occurrence

Definition at line 336 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET (0x00000000UL)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " ADC not yet initialized or disabled

Definition at line 322 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_STATE_TIMEOUT (0x00000004UL)

TimeOut occurrence

Definition at line 325 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Exported Types

Data Structures | Modules | Typedefs | Enumerations
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Modules

ADC States

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __ADC_HandleTypeDef ADC_HandleTypeDef

ADC handle Structure definition.

typedef void(* pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc)

HAL ADC Callback pointer definition.

pointer to a ADC callback function

Definition at line 410 of file stm32h7xx_hal_adc.h.

Enumeration Type Documentation

enum HAL_ADC_CallbackIDTypeDef

HAL ADC Callback ID enumeration definition.

Enumerator:
HAL_ADC_CONVERSION_COMPLETE_CB_ID

ADC conversion complete callback ID

HAL_ADC_CONVERSION_HALF_CB_ID

ADC conversion DMA half-transfer callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID

ADC analog watchdog 1 callback ID

HAL_ADC_ERROR_CB_ID

ADC error callback ID

HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID

ADC group injected conversion complete callback ID

HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID

ADC group injected context queue overflow callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID

ADC analog watchdog 2 callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID

ADC analog watchdog 3 callback ID

HAL_ADC_END_OF_SAMPLING_CB_ID

ADC end of sampling callback ID

HAL_ADC_MSPINIT_CB_ID

ADC Msp Init callback ID

HAL_ADC_MSPDEINIT_CB_ID

ADC Msp DeInit callback ID

Definition at line 392 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC group regular oversampling structure definition. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode
uint32_t | OversamplingStopReset

Detailed Description

ADC group regular oversampling structure definition.

Definition at line 50 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::OversamplingStopReset

Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of Oversampling - Oversampling scope for ADC group regular

Definition at line 61 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value between 1 and 1024

Definition at line 52 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 55 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of Oversampling - Discontinuous mode

Definition at line 58 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC instance and ADC group regular. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | ScanConvMode
uint32_t | EOCSelection
FunctionalState | LowPowerAutoWait
FunctionalState | ContinuousConvMode
uint32_t | NbrOfConversion
FunctionalState | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | ConversionDataManagement
uint32_t | Overrun
uint32_t | LeftBitShift
FunctionalState | OversamplingMode
ADC_OversamplingTypeDef Oversampling

Detailed Description

Structure definition of ADC instance and ADC group regular.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
  • For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 87 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of ADC common - Clock source. Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled.

Definition at line 89 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode(), and HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::ContinuousConvMode

Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 126 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_Init(), HAL_ADC_PollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::ConversionDataManagement

Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be a value of ADC Conversion Data Management. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 155 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_Start_DMA().

FunctionalState ADC_InitTypeDef::DiscontinuousConvMode

Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 136 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InitTypeDef::EOCSelection

Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of ADC sequencer end of unitary conversion or sequence conversions.

Definition at line 111 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group regular trigger source. Caution: external trigger source is common to all ADC instances.

Definition at line 146 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC group regular trigger edge (when external trigger is selected)

Definition at line 151 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::LeftBitShift

Configures the left shifting applied to the final result with or without oversampling. This parameter can be a value of ADC Extended Oversampling left Shift

Definition at line 172 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoWait

Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).

Definition at line 114 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 130 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 142 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of ADC group regular - Overrun behavior on conversion data. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 161 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled.

Definition at line 178 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InitTypeDef::OversamplingMode

Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected

Definition at line 174 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InitTypeDef::Resolution

Configure the ADC resolution. This parameter can be a value of ADC instance - Resolution

Definition at line 100 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of ADC sequencer scan mode

Definition at line 103 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | SingleDiff
uint32_t | OffsetNumber
uint32_t | Offset
FunctionalState | OffsetRightShift
FunctionalState | OffsetSignedSaturation

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  • For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  • For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 194 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specify the channel to configure into ADC regular group. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 196 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 232 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetNumber

Select the offset number This parameter can be a value of ADC instance - Offset number Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 228 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

FunctionalState ADC_ChannelConfTypeDef::OffsetRightShift

Define the Right-shift data after Offset correction. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 239 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

FunctionalState ADC_ChannelConfTypeDef::OffsetSignedSaturation

Specify whether the Signed saturation feature is used or not. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 243 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specify the rank in the regular group sequencer. This parameter can be a value of ADC group regular - Sequencer ranks Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 200 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 205 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SingleDiff

Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of Channel - Single or differential ending Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 216 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
FunctionalState | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.

Definition at line 255 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC instance - Channel number.

Definition at line 267 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling intermediate computation (after ratio, before shift application): intermediate register bitfield [32:7] (26 most significant bits).

Definition at line 275 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

FunctionalState ADC_AnalogWDGConfTypeDef::ITMode

Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 272 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling intermediate computation (after ratio, before shift application): intermediate register bitfield [32:7] (26 most significant bits).

Definition at line 285 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. This parameter can be a value of ADC Analog Watchdog Mode.

Definition at line 262 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of Analog watchdog - Analog watchdog number.

Definition at line 257 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_InjectionConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfigTypeDef Struct Reference
ADC Exported Types

ADC group injected contexts queue configuration. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | ContextQueue
uint32_t | ChannelCount

Detailed Description

ADC group injected contexts queue configuration.

Note:
Structure intended to be used only through structure "ADC_HandleTypeDef"

Definition at line 300 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_InjectionConfigTypeDef::ChannelCount

Number of channels in the injected sequence

Definition at line 306 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfigTypeDef::ContextQueue

Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call

Definition at line 302 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
ADC_InjectionConfigTypeDef InjectionConfig
void(* | ConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ConvHalfCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ErrorCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedQueueOverflowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow2Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow3Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | EndOfSamplingCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspInitCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspDeInitCallback )(struct __ADC_HandleTypeDef *hadc)

Detailed Description

ADC handle Structure definition.

Definition at line 361 of file stm32h7xx_hal_adc.h.

Field Documentation

void(* __ADC_HandleTypeDef::ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion complete callback

Definition at line 374 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion DMA half-transfer callback

Definition at line 375 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

DMA_HandleTypeDef* __ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 368 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

void(* __ADC_HandleTypeDef::EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc)

ADC end of sampling callback

Definition at line 382 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ErrorCallback)(struct __ADC_HandleTypeDef *hadc)

ADC error callback

Definition at line 377 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 371 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_LinearCalibration_SetValue().

ADC_InitTypeDef __ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 367 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode(), ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

void(* __ADC_HandleTypeDef::InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected conversion complete callback

Definition at line 378 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected context queue overflow callback

Definition at line 379 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

ADC_InjectionConfigTypeDef __ADC_HandleTypeDef::InjectionConfig

ADC injected channel configuration build-up structure

Definition at line 372 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

ADC_TypeDef* __ADC_HandleTypeDef::Instance

Register base address

Definition at line 366 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode(), ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_FactorLoad(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void(* __ADC_HandleTypeDef::LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 2 callback

Definition at line 380 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 3 callback

Definition at line 381 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 1 callback

Definition at line 376 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

HAL_LockTypeDef __ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 369 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

void(* __ADC_HandleTypeDef::MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp DeInit callback

Definition at line 384 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::MspInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp Init callback

Definition at line 383 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 370 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Define Documentation

#define HAL_ADC_ERROR_DMA (0x04U)

DMA transfer error

Definition at line 432 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL (0x01U)

ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...)

Definition at line 429 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_LinearCalibration_SetValue().

#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Invalid Callback error

Definition at line 435 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_ERROR_JQOVF (0x08U)

Injected context queue overflow error

Definition at line 433 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_ERROR_NONE (0x00U)

No error

Definition at line 428 of file stm32h7xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR (0x02U)

Overrun error

Definition at line 431 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)

ADC asynchronous clock without prescaler

Definition at line 448 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)

ADC asynchronous clock with prescaler division by 10

Definition at line 453 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)

ADC asynchronous clock with prescaler division by 12

Definition at line 454 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)

ADC asynchronous clock with prescaler division by 128

Definition at line 458 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)

ADC asynchronous clock with prescaler division by 16

Definition at line 455 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)

ADC asynchronous clock with prescaler division by 2

Definition at line 449 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

ADC asynchronous clock with prescaler division by 256

Definition at line 459 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)

ADC asynchronous clock with prescaler division by 32

Definition at line 456 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)

ADC asynchronous clock with prescaler division by 4

Definition at line 450 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)

ADC asynchronous clock with prescaler division by 6

Definition at line 451 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)

ADC asynchronous clock with prescaler division by 64

Definition at line 457 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)

ADC asynchronous clock with prescaler division by 8

Definition at line 452 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 444 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 445 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 446 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B)
#define | ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B)
#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)

Define Documentation

#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)

ADC resolution 10 bits

Definition at line 470 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)

ADC resolution 12 bits

Definition at line 469 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B)

ADC resolution 14 bits

Definition at line 468 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B)

ADC resolution 16 bits

Definition at line 467 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)

ADC resolution 8 bits

Definition at line 471 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC sequencer scan mode

Defines
ADC sequencer scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)

Define Documentation

#define ADC_SCAN_DISABLE (0x00000000UL)

Scan mode disabled

Definition at line 479 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE (0x00000001UL)

Scan mode enabled

Definition at line 480 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular trigger source

Defines
ADC group regular trigger source
ADC Exported Constants

Defines

#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)
#define | ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)
#define | ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting).

Definition at line 496 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)

ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting).

Definition at line 506 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)

ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting).

Definition at line 507 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)

ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 508 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)

ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 509 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)

ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting).

Definition at line 510 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 504 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 490 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 491 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 492 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 499 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 500 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 493 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 501 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)

ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 505 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 494 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)

ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 495 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 502 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 503 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 497 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 498 of file stm32h7xx_hal_adc.h.

#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)

ADC group regular conversion trigger internal: SW start.

Definition at line 489 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular trigger edge (when external trigger is selected)

Defines
ADC group regular trigger edge (when external trigger is selected)
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)

ADC group regular conversion trigger polarity set to falling edge

Definition at line 520 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)

Regular conversions hardware trigger detection disabled

Definition at line 518 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 519 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 521 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC sequencer end of unitary conversion or sequence conversions

Defines
ADC sequencer end of unitary conversion or sequence conversions
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

Define Documentation

#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

End of sequence conversions flag

Definition at line 530 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)

End of unitary conversion flag

Definition at line 529 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 539 of file stm32h7xx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)

ADC group regular behavior in case of overrun: data preserved

Definition at line 538 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

Define Documentation

#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)

ADC group regular sequencer rank 1

Definition at line 547 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)

ADC group regular sequencer rank 10

Definition at line 556 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)

ADC group regular sequencer rank 11

Definition at line 557 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)

ADC group regular sequencer rank 12

Definition at line 558 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)

ADC group regular sequencer rank 13

Definition at line 559 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)

ADC group regular sequencer rank 14

Definition at line 560 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)

ADC group regular sequencer rank 15

Definition at line 561 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

ADC group regular sequencer rank 16

Definition at line 562 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)

ADC group regular sequencer rank 2

Definition at line 548 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)

ADC group regular sequencer rank 3

Definition at line 549 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)

ADC group regular sequencer rank 4

Definition at line 550 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)

ADC group regular sequencer rank 5

Definition at line 551 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)

ADC group regular sequencer rank 6

Definition at line 552 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)

ADC group regular sequencer rank 7

Definition at line 553 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)

ADC group regular sequencer rank 8

Definition at line 554 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)

ADC group regular sequencer rank 9

Definition at line 555 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)
#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5)
#define | ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5)
#define | ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5)
#define | ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5)
#define | ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5)
#define | ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5)

Define Documentation

#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5)

Sampling time 16.5 ADC clock cycles

Definition at line 573 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)

Sampling time 1.5 ADC clock cycles

Definition at line 570 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)

Sampling time 2.5 ADC clock cycles

Definition at line 571 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5)

Sampling time 32.5 ADC clock cycles

Definition at line 574 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5)

Sampling time 387.5 ADC clock cycles

Definition at line 576 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5)

Sampling time 64.5 ADC clock cycles

Definition at line 575 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5)

Sampling time 810.5 ADC clock cycles

Definition at line 577 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5)

Sampling time 8.5 ADC clock cycles

Definition at line 572 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Extended Calibration mode offset mode or linear mode

Defines
ADC Extended Calibration mode offset mode or linear mode
ADC Exported Constants

Defines

#define | ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
#define | ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)

Define Documentation

#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)

Definition at line 585 of file stm32h7xx_hal_adc.h.

#define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)

Definition at line 586 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_19 (LL_ADC_CHANNEL_19)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2)
#define | ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2)
#define | ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2)

Define Documentation

#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 596 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 597 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 606 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 607 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 608 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 609 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 610 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 611 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 612 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 613 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 614 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19)

ADC external channel (channel connected to GPIO pin) ADCx_IN19

Definition at line 615 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 598 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 599 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 600 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 601 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 602 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 603 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 604 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 605 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2)

ADC internal channel connected to DAC1 channel 1, channel specific to ADC2

Definition at line 619 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2)

ADC internal channel connected to DAC1 channel 2, channel specific to ADC2

Definition at line 620 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2)

ADC internal channel connected to DAC2 channel 1, channel specific to ADC2

Definition at line 622 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)

ADC internal channel connected to Temperature sensor, channel specific to ADC3.

Definition at line 617 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3.

Definition at line 618 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)

ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3.

Definition at line 616 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Conversion Data Management

Defines
ADC Conversion Data Management
ADC Exported Constants

Defines

#define | ADC_CONVERSIONDATA_DR (0x00000000UL)
#define | ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1)
#define | ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0)
#define | ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)

Define Documentation

#define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1)

DFSDM mode selected

Definition at line 632 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)

DMA circular mode selected

Definition at line 634 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0)

DMA one shot mode selected

Definition at line 633 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DR (0x00000000UL)

Regular Conversion data stored in DR register only

Definition at line 631 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)

ADC analog watchdog number 1

Definition at line 641 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)

ADC analog watchdog number 2

Definition at line 642 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

ADC analog watchdog number 3

Definition at line 643 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC Analog Watchdog Mode

Defines
ADC Analog Watchdog Mode
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)

Analog watchdog applied to injected group all channels

Definition at line 656 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)

Analog watchdog applied to regular group all channels

Definition at line 655 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Analog watchdog applied to regular and injected groups all channels

Definition at line 657 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL)

No analog watchdog selected

Definition at line 651 of file stm32h7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)

Analog watchdog applied to an injected group single channel

Definition at line 653 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)

Analog watchdog applied to a regular group single channel

Definition at line 652 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Analog watchdog applied to a regular and injected groups single channel

Definition at line 654 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32H7B3xQ HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9)
#define | ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)
#define | ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)

Define Documentation

#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 666 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)

ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data)

Definition at line 675 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)

ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data)

Definition at line 676 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 667 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 668 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 669 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 670 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 671 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 672 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 673 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9)

ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data)

Definition at line 674 of file stm32h7xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 665 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC Extended Oversampling left Shift

Defines
ADC Extended Oversampling left Shift
ADC Exported Constants

Defines

#define | ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE)
#define | ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1)
#define | ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2)
#define | ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3)
#define | ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4)
#define | ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5)
#define | ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6)
#define | ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7)
#define | ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8)
#define | ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9)
#define | ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10)
#define | ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11)
#define | ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12)
#define | ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13)
#define | ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14)
#define | ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15)

Define Documentation

#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1)

ADC 1 bit shift

Definition at line 685 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10)

ADC 10 bits shift

Definition at line 694 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11)

ADC 11 bits shift

Definition at line 695 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12)

ADC 12 bits shift

Definition at line 696 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13)

ADC 13 bits shift

Definition at line 697 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14)

ADC 14 bits shift

Definition at line 698 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15)

ADC 15 bits shift

Definition at line 699 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2)

ADC 2 bits shift

Definition at line 686 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3)

ADC 3 bits shift

Definition at line 687 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4)

ADC 4 bits shift

Definition at line 688 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5)

ADC 5 bits shift

Definition at line 689 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6)

ADC 6 bits shift

Definition at line 690 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7)

ADC 7 bits shift

Definition at line 691 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8)

ADC 8 bits shift

Definition at line 692 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9)

ADC 9 bits shift

Definition at line 693 of file stm32h7xx_hal_adc.h.

#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE)

ADC No bit shift

Definition at line 684 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 708 of file stm32h7xx_hal_adc.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 707 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

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STM32H7B3xQ HAL User Manual: Oversampling - Oversampling scope for ADC group regular

Defines
Oversampling - Oversampling scope for ADC group regular
ADC Exported Constants

Defines

#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Define Documentation

#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)

Oversampling buffer maintained during injection sequence

Definition at line 716 of file stm32h7xx_hal_adc.h.

#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Oversampling buffer zeroed during injection sequence

Definition at line 717 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC Event type

Defines
ADC Event type
ADC Exported Constants

Defines

#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

Define Documentation

#define ADC_AWD1_EVENT (ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series)

Definition at line 727 of file stm32h7xx_hal_adc.h.

#define ADC_AWD2_EVENT (ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series)

Definition at line 728 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT (ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series)

Definition at line 729 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)

ADC End of Sampling event

Definition at line 726 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

ADC Injected Context Queue Overflow event

Definition at line 731 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT (ADC_FLAG_OVR)

ADC overrun event

Definition at line 730 of file stm32h7xx_hal_adc.h.

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STM32H7B3xQ HAL User Manual: ADC interrupts definition

Defines
ADC interrupts definition
ADC Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | ADC_IT_AWD ADC_IT_AWD1

Define Documentation

#define ADC_IT_AWD ADC_IT_AWD1

ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 752 of file stm32h7xx_hal_adc.h.

#define ADC_IT_AWD1 ADC_IER_AWD1IE

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 747 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2IE

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 748 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3IE

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 749 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOCIE

ADC End of regular conversion interrupt source

Definition at line 742 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOS ADC_IER_EOSIE

ADC End of regular sequence of conversions interrupt source

Definition at line 743 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC End of sampling interrupt source

Definition at line 741 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_JEOC ADC_IER_JEOCIE

ADC End of injected conversion interrupt source

Definition at line 745 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JEOS ADC_IER_JEOSIE

ADC End of injected sequence of conversions interrupt source

Definition at line 746 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC Injected Context Queue Overflow interrupt source

Definition at line 750 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVRIE

ADC overrun interrupt source

Definition at line 744 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_RDY ADC_IER_ADRDYIE

ADC Ready interrupt source

Definition at line 740 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit().

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STM32H7B3xQ HAL User Manual: ADC flags definition

Defines
ADC flags definition
ADC Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF

Define Documentation

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag (main analog watchdog)

Definition at line 768 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag (additional analog watchdog)

Definition at line 769 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag (additional analog watchdog)

Definition at line 770 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 763 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 764 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 762 of file stm32h7xx_hal_adc.h.

Referenced by ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_JEOC ADC_ISR_JEOC

ADC End of Injected Conversion flag

Definition at line 766 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JEOS ADC_ISR_JEOS

ADC End of Injected sequence of Conversions flag

Definition at line 767 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC Injected Context Queue Overflow flag

Definition at line 771 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 765 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_RDY ADC_ISR_ADRDY

ADC Ready flag

Definition at line 761 of file stm32h7xx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), and HAL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Exported Constants

Modules | Defines
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC common - Clock source
ADC instance - Resolution
ADC sequencer scan mode
ADC group regular trigger source
ADC group regular trigger edge (when external trigger is selected)
ADC sequencer end of unitary conversion or sequence conversions
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer ranks
Channel - Sampling time
ADC Extended Calibration mode offset mode or linear mode
ADC instance - Channel number
ADC Conversion Data Management
Analog watchdog - Analog watchdog number
ADC Analog Watchdog Mode
Oversampling - Data shift
ADC Extended Oversampling left Shift
Oversampling - Discontinuous mode
Oversampling - Oversampling scope for ADC group regular
ADC Event type
ADC interrupts definition
ADC flags definition

Defines

#define ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 735 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

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STM32H7B3xQ HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_ADC_CONVERSIONDATAMGT(DATA)
Verify the ADC data conversion setting.
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
Check if conversion is on going on regular group.
#define | ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
Check if ADC clock mode is synchronous.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
Verify the ADC resolution setting when limited to 8 bits.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 813 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR register RES[1:0] field.

Parameters:
__HANDLE__ ADC handle
Return values:
Value of bitfield RES in CFGR register.

Definition at line 805 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_CONVERSION_ONGOING_REGULAR ( __HANDLE__ ) (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))

Check if conversion is on going on regular group.

Parameters:
__HANDLE__ ADC handle
Return values:
Value "0" (no conversion is on going) or value "1" (conversion is on going)

Definition at line 830 of file stm32h7xx_hal_adc.h.

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
        ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__ ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 820 of file stm32h7xx_hal_adc.h.

#define ADC_IS_SYNCHRONOUS_CLOCK_MODE ( __HANDLE__ ) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)

Check if ADC clock mode is synchronous.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (clock mode is synchronous) or RESET (clock mode is asynchronous)

Definition at line 844 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConfigureBoostMode().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note:
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 855 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__ )
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )

Verify the ADC clock setting.

Parameters:
__ADC_CLOCK__ programmed ADC clock.
Return values:
SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)

Definition at line 887 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_CONVERSIONDATAMGT ( DATA )
Value:
((((DATA) == ADC_CONVERSIONDATA_DR))          || \
    (((DATA) == ADC_CONVERSIONDATA_DFSDM))       || \
    (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
    (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))

Verify the ADC data conversion setting.

Parameters:
DATA : programmed DATA conversion mode.
Return values:
SET (DATA is a valid value) or RESET (DATA is invalid)

Definition at line 794 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( __EOC_SELECTION__ )
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )

Verify the ADC regular conversions check for converted data availability.

Parameters:
__EOC_SELECTION__ converted data availability check.
Return values:
SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)

Definition at line 971 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EXTTRIG ( __REGTRIG__ )
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)      || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)      || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)      || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)       || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)      || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT)    || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT)    || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT)    || \
                                     ((__REGTRIG__) == ADC_SOFTWARE_START)           )

Verify the ADC regular conversions external trigger.

Parameters:
__REGTRIG__ programmed ADC regular conversions external trigger.
Return values:
SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)

Definition at line 943 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for regular group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 933 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_OVERRUN ( __OVR__ )
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )

Verify the ADC regular conversions overrun handling.

Parameters:
__OVR__ ADC regular conversions overrun handling.
Return values:
SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)

Definition at line 979 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) | ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters:
__RESOLUTION__ | ADC resolution (16, 14, 12, 10 or 8 bits).
__ADC_VALUE__ | value checked against the resolution.
Return values:
SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

Definition at line 863 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters:
NUMBER number of scheduled regular conversions in discontinuous mode.
Return values:
SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

Definition at line 879 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

Verify the length of the scheduled regular conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 871 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

Verify the ADC regular channel setting.

Parameters:
__CHANNEL__ programmed ADC regular channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1001 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)    )

Verify the ADC resolution setting.

Parameters:
__RESOLUTION__ programmed ADC resolution.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 908 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION_8_BITS ( __RESOLUTION__ ) (((__RESOLUTION__) == ADC_RESOLUTION_8B))

Verify the ADC resolution setting when limited to 8 bits.

Parameters:
__RESOLUTION__ programmed ADC resolution when limited to 8 bits.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 918 of file stm32h7xx_hal_adc.h.

#define IS_ADC_SAMPLE_TIME ( __TIME__ )
Value:
(((__TIME__) == ADC_SAMPLETIME_1CYCLE_5)    || \
                                      ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
                                      ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5)   )

Verify the ADC conversions sampling time.

Parameters:
__TIME__ ADC conversions sampling time.
Return values:
SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)

Definition at line 987 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( __SCAN_MODE__ )
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
__SCAN_MODE__ programmed ADC scan mode.
Return values:
SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)

Definition at line 925 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL ADC macro to manage HAL ADC handle, IT and flags.

Defines
HAL ADC macro to manage HAL ADC handle, IT and flags.
ADC Exported Macros

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear the specified ADC flag.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
None

Definition at line 1183 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1120 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1099 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Check whether the specified ADC flag is set or not.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
State of flag (TRUE or FALSE).

Definition at line 1161 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
State of interruption (SET or RESET)

Definition at line 1140 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                                          \
    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
    (__HANDLE__)->MspInitCallback = NULL;                                      \
    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
  } while(0)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 1070 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL ADC helper macro

Defines
HAL ADC helper macro
ADC Exported Macros

Defines

#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __HAL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
                                (__ADC_DATA__),                                \
                                (__ADC_RESOLUTION__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1541 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
                            (__TEMPSENSOR_ADC_DATA__),                         \
                            (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1625 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
                                      (__TEMPSENSOR_TYP_CALX_V__),             \
                                      (__TEMPSENSOR_CALX_TEMP__),              \
                                      (__VREFANALOG_VOLTAGE__),                \
                                      (__TEMPSENSOR_ADC_DATA__),               \
                                      (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32H7, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1677 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
                                  (__ADC_RESOLUTION__))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
Analog reference voltage (unit: mV)

Definition at line 1574 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0 (3)
  • ADC_CHANNEL_1 (3)
  • ADC_CHANNEL_2 (3)
  • ADC_CHANNEL_3 (3)
  • ADC_CHANNEL_4 (3)
  • ADC_CHANNEL_5 (3)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (1)
  • ADC_CHANNEL_VBAT (1)
  • ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18

Definition at line 1399 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))

Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.

Note:
Example: __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0 (3)
  • ADC_CHANNEL_1 (3)
  • ADC_CHANNEL_2 (3)
  • ADC_CHANNEL_3 (3)
  • ADC_CHANNEL_4 (3)
  • ADC_CHANNEL_5 (3)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (1)
  • ADC_CHANNEL_VBAT (1)
  • ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1235 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_COMMON_INSTANCE ( __ADCx__ ) __LL_ADC_COMMON_INSTANCE((__ADCx__))

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1457 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
                                   (__ADC_RESOLUTION_CURRENT__),                \
                                   (__ADC_RESOLUTION_TARGET__))

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
ADC conversion data to the requested resolution

Definition at line 1517 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))

Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.

Note:
Example: __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0 (3)
  • ADC_CHANNEL_1 (3)
  • ADC_CHANNEL_2 (3)
  • ADC_CHANNEL_3 (3)
  • ADC_CHANNEL_4 (3)
  • ADC_CHANNEL_5 (3)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (1)
  • ADC_CHANNEL_VBAT (1)
  • ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1279 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_16B
  • ADC_RESOLUTION_14B
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
Return values:
ADC conversion data full-scale digital value

Definition at line 1494 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): ADC_CHANNEL_1, ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0 (3)
  • ADC_CHANNEL_1 (3)
  • ADC_CHANNEL_2 (3)
  • ADC_CHANNEL_3 (3)
  • ADC_CHANNEL_4 (3)
  • ADC_CHANNEL_5 (3)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (1)
  • ADC_CHANNEL_VBAT (1)
  • ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1332 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (1)
  • ADC_CHANNEL_VBAT (1)
  • ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1428 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1477 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled: refer to function LL_ADC_SetMultiDMATransfer(). In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1444 of file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (633600000U)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT (633600000U)

ADC calibration time-out value

Definition at line 77 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_JSQR_FIELDS
Value:
((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                           ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))

ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled

Definition at line 63 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_FactorLoad (ADC_HandleTypeDef *hadc)
Load the calibration factor from engi bytes.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

      (+) Start conversion of ADC group injected.
      (+) Stop conversion of ADC group injected.
      (+) Poll for conversion complete on ADC group injected.
      (+) Get result of ADC group injected channel conversion.
      (+) Start conversion of ADC group injected and enable interruptions.
      (+) Stop conversion of ADC group injected and disable interruptions.

      (+) When multimode feature is available, start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Get the calibration factor.

Parameters:
hadc ADC handle.
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
Calibration value.

Definition at line 210 of file stm32h7xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, and LL_ADC_GetCalibrationOffsetFactor().

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result.

ADC must be enabled and no conversion is ongoing.

Parameters:
hadc | ADC handle
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
CalibrationFactor | Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 271 of file stm32h7xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCalibrationOffsetFactor(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | CalibrationMode,
 |  | uint32_t | SingleDiff
 | ) |  |

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Parameters:
hadc ADC handle
CalibrationMode Selection of calibration offset or linear calibration offset.
  • ADC_CALIB_OFFSET Channel in mode calibration offset
  • ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
SingleDiff Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
HAL status

Definition at line 136 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_IsCalibrationOnGoing(), LL_ADC_StartCalibration(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1379 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1314 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 families). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc ADC handle
InjectedRank the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1 ADC group injected rank 1
  • ADC_INJECTED_RANK_2 ADC group injected rank 2
  • ADC_INJECTED_RANK_3 ADC group injected rank 3
  • ADC_INJECTED_RANK_4 ADC group injected rank 4
Return values:
ADC group injected conversion data

Definition at line 1279 of file stm32h7xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, __ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, JEOS or JEOC is checked and cleared depending on AUTDLY bit status.
Return values:
HAL status

Definition at line 648 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedQueueOverflowCallback ( ADC_HandleTypeDef * hadc )

Injected context queue overflow callback.

Note:
This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts).
Parameters:
hadc ADC handle
Return values:
None

Definition at line 1333 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled when multimode feature is available: HAL_ADCEx_InjectedStart() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 456 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : JEOC (end of conversion) or JEOS (end of sequence)
Case of multimode enabled (when multimode feature is enabled): HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle.
Return values:
HAL status.

Definition at line 779 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of multimode enabled (when multimode feature is available), HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 593 of file stm32h7xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Case of multimode enabled (when multimode feature is available): HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
In case of auto-injection mode, HAL_ADC_Stop() must be used.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 940 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_JQOVF, ADC_INJECTED_GROUP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1348 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1363 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad ( ADC_HandleTypeDef * hadc )

Load the calibration factor from engi bytes.

Parameters:
hadc ADC handle
Return values:
HAL state

Definition at line 412 of file stm32h7xx_hal_adc_ex.c.

References ADC_LINEAR_CALIB_REG_1_ADDR, ADC_LINEAR_CALIB_REG_COUNT, HAL_ADCEx_LinearCalibration_SetValue(), and __ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | LinearCalib_Buffer
 | ) |  |

Get the calibration factor from automatic conversion result.

Parameters:
hadc ADC handle
LinearCalib_Buffer,: Linear calibration factor
Return values:
HAL state

Definition at line 226 of file stm32h7xx_hal_adc_ex.c.

References ADC_Enable(), ADC_LINEAR_CALIB_REG_COUNT, assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_GetCalibrationLinearFactor(), LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), and LL_ADC_REG_StopConversion().

HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | LinearCalib_Buffer
 | ) |  |

Set the linear calibration factor.

Parameters:
hadc ADC handle
LinearCalib_Buffer,: Linear calibration factor
Return values:
HAL state

Definition at line 322 of file stm32h7xx_hal_adc_ex.c.

References ADC_Disable(), ADC_Enable(), ADC_LINEAR_CALIB_REG_COUNT, ADC_STAB_DELAY_US, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, __ADC_HandleTypeDef::Instance, LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), LL_ADC_SetCalibrationLinearFactor(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADCEx_LinearCalibration_FactorLoad().

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Return the last ADC Master and Slave regular conversions results when in multimode configuration.

Parameters:
hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
Return values:
The converted data values.

Definition at line 1233 of file stm32h7xx_hal_adc_ex.c.

References __LL_ADC_COMMON_INSTANCE, assert_param, and __ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start MultiMode conversion and transfer regular results through DMA.

Note:
Multimode must have been previously configured using HAL_ADCEx_MultiModeConfigChannel() function. Interruptions enabled in this function: overrun, DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
State field of Slave ADC handle is not updated in this configuration: user should not rely on it for information related to Slave regular conversions.
Parameters:
hadc | ADC handle of ADC master (handle of ADC slave must not be used)
pData | Destination Buffer address.
Length | Length of data to be transferred from ADC peripheral to memory (in bytes).
Return values:
HAL status

Definition at line 1006 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EXTTRIG_EDGE, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.

Note:
Multimode is kept enabled after this function. MultiMode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADC_Stop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 1120 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Note:
Multimode is kept enabled after this function. Multimode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 1600 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1396 of file stm32h7xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.

Note:
HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. For multimode (when multimode feature is available), HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1514 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1454 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Extended Peripheral Control functions

Functions
ADC Extended Peripheral Control functions
ADC Extended Exported Functions

ADC Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

ADC Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode when multimode feature is available
      (+) Enable or Disable Injected Queue
      (+) Disable ADC voltage regulator
      (+) Enter ADC deep-power-down mode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue ( ADC_HandleTypeDef * hadc )

Disable Injected Queue.

Note:
This function sets CFGR register JQDIS bit in order to disable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2380 of file stm32h7xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_QUEUE_DISABLE, LL_ADC_INJ_SetQueueMode(), and LL_ADC_REG_IsConversionOngoing().

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2417 of file stm32h7xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue ( ADC_HandleTypeDef * hadc )

Enable Injected Queue.

Note:
This function resets CFGR register JQDIS bit in order to enable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2339 of file stm32h7xx_hal_adc_ex.c.

References assert_param, HAL_ADC_STATE_INJ_JQOVF, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode ( ADC_HandleTypeDef * hadc )

Enter ADC deep-power-down mode.

Note:
This mode is achieved in setting DEEPPWD bit and allows to save power in reducing leakage currents. It is particularly interesting before entering stop modes.
Setting DEEPPWD automatically clears ADVREGEN bit and disables the ADC voltage regulator. This means that this API encompasses HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal calibration is lost.
To exit the ADC deep-power-down mode, the user is expected to resort to HAL_ADC_Init() API as well as to relaunch a calibration with HAL_ADCEx_Calibration_Start() API or to re-apply a previously saved calibration factor.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2454 of file stm32h7xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_EnableDeepPowerDown(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configure a channel to be assigned to ADC group injected.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_InjectionConfTypeDef".
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Caution: For Injected Context Queue use, a context must be fully defined before start of injected conversion. All channels are configured consecutively for the same ADC instance. Therefore, the number of calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter InjectedNbrOfConversion for each context.
  • Example 1: If 1 context is intended to be used (or if there is no use of the Injected Queue Context feature) and if the context contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel (i.e. 3 times) before starting a conversion. This function must not be called to configure a 4th injected channel: it would start a new context into context queue.
  • Example 2: If 2 contexts are intended to be used and each of them contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and for each context (3 channels x 2 contexts = 6 calls). Conversion can start once the 1st context is set, that is after the first three HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
Parameters:
hadc | ADC handle
sConfigInjected | Structure of ADC injected group and ADC channel for injected group.
Return values:
HAL status

Definition at line 1773 of file stm32h7xx_hal_adc_ex.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CFGR_INJECT_CONTEXT_QUEUE, ADC_CFGR_INJECT_DISCCONTINUOUS, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, ADC_GET_RESOLUTION, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_JSQR_FIELDS, ADC_JSQR_RK, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_SCAN_DISABLE, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjecOversampling, ADC_InjectionConfTypeDef::InjecOversamplingMode, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedOffsetNumber, ADC_InjectionConfTypeDef::InjectedOffsetRightShift, ADC_InjectionConfTypeDef::InjectedOffsetSignedSaturation, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_InjectionConfTypeDef::InjectedSingleDiff, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, IS_ADC1_DIFF_CHANNEL, IS_ADC2_DIFF_CHANNEL, IS_ADC3_DIFF_CHANNEL, IS_ADC_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_EXTTRIGINJEC_EDGE, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_OFFSET_NUMBER, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_RANGE, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_GetOffsetChannel(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_1, LL_ADC_OFFSET_2, LL_ADC_OFFSET_3, LL_ADC_OFFSET_4, LL_ADC_OFFSET_RSHIFT_DISABLE, LL_ADC_OFFSET_RSHIFT_ENABLE, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE, LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetDataRightShift(), LL_ADC_SetOffset(), LL_ADC_SetOffsetSignedSaturation(), ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_InjectionConfTypeDef::QueueInjectedContext, ADC_InjOversamplingTypeDef::Ratio, ADC_OversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Enable ADC multimode and configure multimode parameters.

Note:
Possibility to update parameters on the fly: This function initializes multimode parameters, following calls to this function can be used to reconfigure some parameters of structure "ADC_MultiModeTypeDef" on the fly, without resetting the ADCs. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_MultiModeTypeDef".
To move back configuration from multimode to single mode, ADC must be reset (using function HAL_ADC_Init() ).
Parameters:
hadc | Master ADC handle
multimode | Structure of ADC multimode configuration
Return values:
HAL status

Definition at line 2229 of file stm32h7xx_hal_adc_ex.c.

References __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_MODE_INDEPENDENT, ADC_MULTI_SLAVE, assert_param, ADC_MultiModeTypeDef::DualModeData, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Instance, IS_ADC_DUAL_DATA_MODE, IS_ADC_MULTIMODE, IS_ADC_SAMPLING_DELAY, LL_ADC_REG_IsConversionOngoing(), ADC_MultiModeTypeDef::Mode, __ADC_HandleTypeDef::State, and ADC_MultiModeTypeDef::TwoSamplingDelay.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_InjOversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjOversamplingTypeDef Struct Reference
ADC Extended Exported Types

ADC Injected Conversion Oversampling structure definition. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift

Detailed Description

ADC Injected Conversion Oversampling structure definition.

Definition at line 47 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjOversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value between 1 and 1024

Definition at line 49 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjOversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 52 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedSingleDiff
uint32_t | InjectedOffsetNumber
uint32_t | InjectedOffset
uint32_t | InjectedOffsetRightShift
FunctionalState | InjectedOffsetSignedSaturation
uint32_t | InjectedLeftBitShift
uint32_t | InjectedNbrOfConversion
FunctionalState | InjectedDiscontinuousConvMode
FunctionalState | AutoInjectedConv
FunctionalState | QueueInjectedContext
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge
FunctionalState | InjecOversamplingMode
ADC_InjOversamplingTypeDef InjecOversampling

Detailed Description

Structure definition of ADC group injected and ADC channel affected to ADC group injected.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
  • Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
  • For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
  • For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
  • For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 72 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

FunctionalState ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 143 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group injected trigger source. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 163 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC group injected trigger edge (when external trigger is selected). If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 169 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

ADC_InjOversamplingTypeDef ADC_InjectionConfTypeDef::InjecOversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 179 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjecOversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 175 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Specifies the channel to configure into ADC group injected. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 74 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 133 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedLeftBitShift

Configures the left shifting applied to the final result with or without oversampling. This parameter can be a value of ADC Extended Oversampling left Shift

Definition at line 124 of file stm32h7xx_hal_adc_ex.h.

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 127 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 110 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetNumber

Selects the offset number. This parameter can be a value of ADC instance - Offset number. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 106 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetRightShift

Specifies whether the 1 bit Right-shift feature is used or not. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 117 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedOffsetSignedSaturation

Specifies whether the Signed saturation feature is used or not. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 121 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Specifies the rank in the ADC group injected sequencer. This parameter must be a value of ADC group injected - Sequencer ranks. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 78 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 83 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of Channel - Single or differential ending. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 94 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::QueueInjectedContext

Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

Definition at line 152 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC multimode. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DualModeData
uint32_t | TwoSamplingDelay

Detailed Description

Structure definition of ADC multimode.

Note:
The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). Both Master and Slave ADCs must be disabled.

Definition at line 189 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DualModeData

Configures the Dual ADC Mode Data Format: This parameter can be a value of ADC Extended Dual Mode Data Formatting

Definition at line 194 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multimode. This parameter can be a value of Multimode - Mode.

Definition at line 191 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of Multimode - Delay between two sampling phases. Delay range depends on selected resolution: from 1 to 9 clock cycles for 16 bits, from 1 to 9 clock cycles for 14 bits from 1 to 8 clock cycles for 12 bits from 1 to 6 clock cycles for 10 bits from 1 to 6 clock cycles for 8 bits

Definition at line 197 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group injected trigger source

Defines
ADC group injected trigger source
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)
#define | ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)
#define | ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)

ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 228 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)

ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting).

Definition at line 238 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)

ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting).

Definition at line 239 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)

ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 240 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)

ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 241 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)

ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 242 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)

ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 237 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 223 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 222 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 230 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 225 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 224 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)

ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 235 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)

ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 233 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)

ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 226 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)

ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 234 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)

ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 227 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)

ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 236 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 229 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 231 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 232 of file stm32h7xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)

Software triggers injected group conversion start

Definition at line 221 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

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STM32H7B3xQ HAL User Manual: ADC group injected trigger edge (when external trigger is selected)

Defines
ADC group injected trigger edge (when external trigger is selected)
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)

Injected conversions hardware trigger detection on the falling edge

Definition at line 252 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)

Injected conversions hardware trigger detection disabled

Definition at line 250 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)

Injected conversions hardware trigger detection on the rising edge

Definition at line 251 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Injected conversions hardware trigger detection on both the rising and falling edges

Definition at line 253 of file stm32h7xx_hal_adc_ex.h.

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STM32H7B3xQ HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Extended Exported Constants

Defines

#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 262 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 261 of file stm32h7xx_hal_adc_ex.h.

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STM32H7B3xQ HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)

Define Documentation

#define ADC_OFFSET_1 (LL_ADC_OFFSET_1)

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 271 of file stm32h7xx_hal_adc_ex.h.

#define ADC_OFFSET_2 (LL_ADC_OFFSET_2)

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 272 of file stm32h7xx_hal_adc_ex.h.

#define ADC_OFFSET_3 (LL_ADC_OFFSET_3)

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 273 of file stm32h7xx_hal_adc_ex.h.

#define ADC_OFFSET_4 (LL_ADC_OFFSET_4)

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 274 of file stm32h7xx_hal_adc_ex.h.

#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)

ADC offset disabled: no offset correction for the selected ADC channel

Definition at line 270 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32H7B3xQ HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

Define Documentation

#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)

ADC group injected sequencer rank 1

Definition at line 282 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)

ADC group injected sequencer rank 2

Definition at line 283 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)

ADC group injected sequencer rank 3

Definition at line 284 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

ADC group injected sequencer rank 4

Definition at line 285 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

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STM32H7B3xQ HAL User Manual: ADC Extended Dual Mode Data Formatting

Defines
ADC Extended Dual Mode Data Formatting
Multimode - Mode

Defines

#define | ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL)
#define | ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1)
#define | ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))

Define Documentation

#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1)

Data formatting mode for 32 down to 10-bit resolution

Definition at line 306 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))

Data formatting mode for 8-bit resolution

Definition at line 307 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL)

Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used

Definition at line 305 of file stm32h7xx_hal_adc_ex.h.

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STM32H7B3xQ HAL User Manual: Multimode - Delay between two sampling phases

Defines
Multimode - Delay between two sampling phases
Multimode - Mode

Defines

#define | ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)
#define | ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
#define | ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)

Define Documentation

#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)

ADC multimode delay between two sampling phases: 1 ADC clock cycle

Definition at line 315 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)

ADC multimode delay between two sampling phases: 2 ADC clock cycles

Definition at line 316 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)

ADC multimode delay between two sampling phases: 3 ADC clock cycles

Definition at line 317 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)

ADC multimode delay between two sampling phases: 4 ADC clock cycles

Definition at line 318 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)

ADC multimode delay between two sampling phases: 5 ADC clock cycles

Definition at line 319 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)

ADC multimode delay between two sampling phases: 6 ADC clock cycles

Definition at line 320 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)

ADC multimode delay between two sampling phases: 7 ADC clock cycles

Definition at line 321 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)

ADC multimode delay between two sampling phases: 8 ADC clock cycles

Definition at line 322 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)

ADC multimode delay between two sampling phases: 9 ADC clock cycles

Definition at line 323 of file stm32h7xx_hal_adc_ex.h.

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STM32H7B3xQ HAL User Manual: Multimode - Mode

Modules | Defines
Multimode - Mode
ADC Extended Exported Constants

Modules

ADC Extended Dual Mode Data Formatting
Multimode - Delay between two sampling phases

Defines

#define | ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
#define | ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
#define | ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
#define | ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
#define | ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)

Define Documentation

#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)

Definition at line 297 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)

ADC dual mode enabled: group injected simultaneous

Definition at line 296 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)

ADC dual mode enabled: Combined group regular interleaved

Definition at line 295 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Definition at line 300 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)

ADC dual mode enabled: group regular simultaneous

Definition at line 294 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 299 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 298 of file stm32h7xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)

ADC dual mode disabled (ADC independent mode)

Definition at line 293 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

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STM32H7B3xQ HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

Define Documentation

#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)

ADC group injected (not available on all STM32 devices)

Definition at line 336 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)

ADC group regular (available on all STM32 devices)

Definition at line 335 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

ADC both groups regular and injected

Definition at line 337 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

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STM32H7B3xQ HAL User Manual: ADCx CFGR fields

Defines
ADCx CFGR fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS

Define Documentation

#define ADC_CFGR_FIELDS
Value:
(ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )

Definition at line 345 of file stm32h7xx_hal_adc_ex.h.

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STM32H7B3xQ HAL User Manual: ADCx SMPR1 fields

Defines
ADCx SMPR1 fields
ADC Extended Exported Constants

Defines

#define ADC_SMPR1_FIELDS

Define Documentation

#define ADC_SMPR1_FIELDS
Value:
(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
                             ADC_SMPR1_SMP0)

Definition at line 358 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADCx CFGR sub fields

Defines
ADCx CFGR sub fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))

Define Documentation

#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))

Definition at line 371 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular - DFSDM transfer of ADC conversion data

Defines
ADC group regular - DFSDM transfer of ADC conversion data
ADC Extended Exported Constants

Defines

#define | ADC_DFSDM_MODE_DISABLE (0x00000000UL)
#define | ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE)

Define Documentation

#define ADC_DFSDM_MODE_DISABLE (0x00000000UL)

ADC conversions are not transferred by DFSDM.

Definition at line 380 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE)

ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled.

Definition at line 381 of file stm32h7xx_hal_adc_ex.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Extended Exported Macros

Defines
ADC Extended Exported Macros
ADCEx

Defines

#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
Force ADC instance in multimode mode independent (multimode disable).

Define Documentation

#define ADC_FORCE_MODE_INDEPENDENT ( __HANDLE__ ) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)

Force ADC instance in multimode mode independent (multimode disable).

Note:
This macro must be used only in case of transition from multimode to mode independent and in case of unknown previous state, to ensure ADC configuration is in mode independent.
Standard way of multimode configuration change is done from HAL ADC handle of ADC master using function "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". Usage of this macro is not the Standard way of multimode configuration and can lead to have HAL ADC handles status misaligned. Usage of this macro must be limited to cases mentionned above.
Parameters:
__HANDLE__ ADC handle.
Return values:
None

Definition at line 411 of file stm32h7xx_hal_adc_ex.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if conversion is on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
Check if conversion is on going on injected group.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
Check whether or not ADC is independent.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
Enable the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
Configure calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)
Shift the offset in function of the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD1 threshold in function of the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
#define | ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
Clear Common Control Register.
#define | ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
Report Master Instance.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC1_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC1.
#define | IS_ADC2_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC2.
#define | IS_ADC3_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC3.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DUAL_DATA_MODE(MODE)
Verify the ADC dual data mode setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
Return the DFSDM configuration mode.

Define Documentation

#define ADC12_COMMON_REGISTER ( __HANDLE__ ) (ADC12_COMMON)

Clear Common Control Register.

Parameters:
__HANDLE__ ADC handle.
Return values:
None Report common register to ADC1 and ADC2
Parameters:
__HANDLE__,: ADC handle
Return values:
Common control register

Definition at line 675 of file stm32h7xx_hal_adc_ex.h.

#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \
    )?                                                                         \
     SET                                                                       \
     :                                                                         \
     ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
  )

Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

Definition at line 722 of file stm32h7xx_hal_adc_ex.h.

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) |
Value:
(                                                                                                         \
           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \
            ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
              :                                                                                                   \
              ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
        )

Shift the AWD1 threshold in function of the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 614 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) |
Value:
(                                                                                                           \
            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \
              ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
                :                                                                                                   \
                ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
        )

Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 647 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_BATTERY_VOLTAGE_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the battery voltage VBAT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 832 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CALFACT_DIFF_GET ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)

Calibration factor in differential mode to be retrieved from calibration register.

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
None

Definition at line 551 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CALFACT_DIFF_SET ( __CALIBRATION_FACTOR__ ) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)

Configure calibration factor in differential mode to be set into calibration register.

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
None

Definition at line 544 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CCR_MULTI_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)

Configure the ADC DMA continuous request for ADC multimode.

Parameters:
__DMACONTREQ_MODE__ DMA continuous request mode.
Return values:
None

Definition at line 565 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CFGR_AUTOWAIT ( __AUTOWAIT__ ) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)

Configure the ADC auto delay mode.

Parameters:
__AUTOWAIT__ Auto delay bit enable or disable.
Return values:
None

Definition at line 509 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_CONTINUOUS ( __CONTINUOUS_MODE__ ) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)

Configure ADC continuous conversion mode.

Parameters:
__CONTINUOUS_MODE__ Continuous mode.
Return values:
None

Definition at line 516 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DFSDM ( __HANDLE__ ) ((__HANDLE__)->Init.DFSDMConfig)

Return the DFSDM configuration mode.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
DFSDM configuration mode

Definition at line 1145 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CFGR_DISCONTINUOUS_NUM ( __NBR_DISCONTINUOUS_CONV__ ) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)

Configure the number of discontinuous conversions for regular group.

Parameters:
__NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
Return values:
None

Definition at line 502 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__))

Enable the ADC DMA continuous request.

Parameters:
__DMACONTREQ_MODE__,: DMA continuous request mode.
Return values:
None

Definition at line 523 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_INJECT_CONTEXT_QUEUE ( __INJECT_CONTEXT_QUEUE_MODE__ ) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)

Configure ADC injected context queue.

Parameters:
__INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
Return values:
None

Definition at line 481 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_INJECT_DISCCONTINUOUS ( __INJECT_DISCONTINUOUS_MODE__ ) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)

Configure ADC discontinuous conversion mode for injected group.

Parameters:
__INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
Return values:
None

Definition at line 488 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_REG_DISCONTINUOUS ( __REG_DISCONTINUOUS_MODE__ ) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)

Configure ADC discontinuous conversion mode for regular group.

Parameters:
__REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
Return values:
None

Definition at line 495 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CLEAR_COMMON_CONTROL_REGISTER ( __HANDLE__ )
Value:
CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE    | \
                                                                                ADC_CCR_PRESC     | \
                                                                                ADC_CCR_VBATEN    | \
                                                                                ADC_CCR_TSEN      | \
                                                                                ADC_CCR_VREFEN    | \
                                                                                ADC_CCR_DAMDF     | \
                                                                                ADC_CCR_DELAY     | \
                                                                                ADC_CCR_DUAL  )

Definition at line 793 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

#define ADC_DIFSEL_CHANNEL ( __CHANNEL__ ) (1UL << (__CHANNEL__))

Configure the channel number into differential mode selection register.

Parameters:
__CHANNEL__ ADC Channel.
Return values:
None

Definition at line 537 of file stm32h7xx_hal_adc_ex.h.

#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1)                                    \
    )?                                                                     \
     SET                                                                   \
     :                                                                     \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)

Definition at line 783 of file stm32h7xx_hal_adc_ex.h.

#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1)                                      \
    )?                                                                      \
     SET                                                                    \
     :                                                                      \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)

Definition at line 758 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_CONVERSION_ONGOING_INJECTED ( __HANDLE__ ) (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))

Check if conversion is on going on injected group.

Parameters:
__HANDLE__ ADC handle.
Return values:
Value "0" (no conversion is on going) or value "1" (conversion is on going)

Definition at line 449 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
        ) ? RESET : SET)

Check if conversion is on going on regular or injected groups.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (conversion is on going) or RESET (no conversion is on going).

Definition at line 440 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
    )?                                                                           \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
     :                                                                           \
     RESET                                                                       \
  )

Check whether or not dual regular conversions are enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

Definition at line 707 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (software start) or RESET (external trigger).

Definition at line 432 of file stm32h7xx_hal_adc_ex.h.

#define ADC_JSQR_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

Check whether or not ADC is independent.

Parameters:
__HANDLE__ ADC handle.
Note:
When multimode feature is not available, the macro always returns SET.
Return values:
SET (ADC is independent) or RESET (ADC is not). Set the selected injected Channel rank.
Parameters:
__CHANNELNB__ | Channel number.
__RANKNB__ | Rank number.
Return values:
None

Definition at line 474 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_MASTER_REGISTER ( __HANDLE__ ) ( (ADC1))

Report Master Instance.

Parameters:
__HANDLE__,: ADC handle
Note:
return same instance if ADC of input handle is independent ADC
Return values:
Master Instance

Definition at line 699 of file stm32h7xx_hal_adc_ex.h.

#define ADC_MULTI_SLAVE | ( | __HANDLE_MASTER__,
 |  | __HANDLE_SLAVE__
 | ) | ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )

Set handle instance of the ADC slave associated to the ADC master.

Parameters:
__HANDLE_MASTER__ | ADC master handle.
__HANDLE_SLAVE__ | ADC slave handle.
Note:
if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
Return values:
None

Definition at line 809 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_OFFSET_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __OFFSET__
 | ) |
Value:
(                                                                                                       \
           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                           \
              ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \
               :                                                                                                \
               ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
        )

Shift the offset in function of the selected ADC resolution.

Note:
Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
Parameters:
__HANDLE__,: ADC handle
__OFFSET__,: Value to be shifted
Return values:
None

Definition at line 581 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFR_CHANNEL ( __CHANNEL__ ) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)

Configure the channel number into offset OFRx register.

Parameters:
__CHANNEL__ ADC Channel.
Return values:
None

Definition at line 530 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_TEMPERATURE_SENSOR_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the temperature sensor.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 821 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_TRX_HIGHTHRESHOLD ( __THRESHOLD__ ) ((__THRESHOLD__) << 16UL)

Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.

Parameters:
__THRESHOLD__ Threshold value.
Return values:
None

Definition at line 558 of file stm32h7xx_hal_adc_ex.h.

#define ADC_VREFINT_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the internal voltage reference VREFINT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 843 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC1_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_2)      ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_3)      ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_4)      ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_5)      ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_10)     ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_11)     ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_12)     ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_16)     ||\
                                           ((__CHANNEL__) == ADC_CHANNEL_18)      )

Verify the ADC channel setting in differential mode for ADC1.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 897 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC2_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_2)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_3)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_4)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_5)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_10)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_11)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_12)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_18)      )

Verify the ADC channel setting in differential mode for ADC2.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 913 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC3_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_2)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_3)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_4)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_5)      || \
                                           ((__CHANNEL__) == ADC_CHANNEL_10)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_11)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_13)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_14)     || \
                                           ((__CHANNEL__) == ADC_CHANNEL_15)       )

Verify the ADC channel setting in differential mode for ADC3.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 928 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( __WATCHDOG_MODE__ )
Value:
(((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Verify the ADC analog watchdog mode setting.

Parameters:
__WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
Return values:
SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)

Definition at line 1054 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( __WATCHDOG__ )
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )

Verify the ADC analog watchdog setting.

Parameters:
__WATCHDOG__ programmed ADC analog watchdog setting.
Return values:
SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)

Definition at line 1045 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CALFACT ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) <= (0x7FU))

Calibration factor size verification (7 bits maximum).

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

Definition at line 858 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_0)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_1)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_2)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_3)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_4)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_5)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_6)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_7)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_8)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_9)           || \
                                     ((__CHANNEL__) == ADC_CHANNEL_10)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_11)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_12)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_13)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_14)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_15)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_16)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_17)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_18)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_19)          || \
                                     ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
                                     ((__CHANNEL__) == ADC_CHANNEL_VBAT)        || \
                                     ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
                                     ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
                                     ((__CHANNEL__) == ADC_CHANNEL_VREFINT)       )

Verify the ADC channel setting.

Parameters:
__CHANNEL__ programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 866 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( __CONVERSION__ )
Value:
(((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )

Verify the ADC conversion (regular or injected or both).

Parameters:
__CONVERSION__ ADC conversion group.
Return values:
SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)

Definition at line 1067 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop().

#define IS_ADC_DFSDMCFG_MODE ( __HANDLE__ )
Value:
(((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
                                          ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )

Verify the DFSDM mode configuration.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports SET. For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

Definition at line 1130 of file stm32h7xx_hal_adc_ex.h.

#define IS_ADC_DUAL_DATA_MODE ( MODE )
Value:
(((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED)   || \
                                     ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
                                     ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS)     )

Verify the ADC dual data mode setting.

Parameters:
MODE,: programmed ADC dual mode setting.
Return values:
SET (MODE is valid) or RESET (MODE is invalid)

Definition at line 1021 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EVENT_TYPE ( __EVENT__ )
Value:
(((__EVENT__) == ADC_EOSMP_EVENT)  || \
                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )

Verify the ADC event type.

Parameters:
__EVENT__ ADC event.
Return values:
SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)

Definition at line 1076 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIGINJEC ( __INJTRIG__ )
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
                                                                                \
                                           ((__INJTRIG__) == ADC_SOFTWARE_START)                   )

Verify the ADC injected conversions external trigger.

Parameters:
__INJTRIG__ programmed ADC injected conversions external trigger.
Return values:
SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)

Definition at line 973 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )

Verify the ADC edge trigger setting for injected group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 997 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))

Verify the length of scheduled injected conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 851 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )

Verify the ADC injected channel setting.

Parameters:
__CHANNEL__ programmed ADC injected channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 963 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MULTIMODE ( __MODE__ )
Value:
(((__MODE__) == ADC_MODE_INDEPENDENT)               || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )

Verify the ADC multimode setting.

Parameters:
__MODE__ programmed ADC multimode setting.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1007 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_OFFSET_NUMBER ( __OFFSET_NUMBER__ )
Value:
(((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )

Verify the ADC offset management setting.

Parameters:
__OFFSET_NUMBER__ ADC offset management.
Return values:
SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)

Definition at line 952 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OVERSAMPLING_RATIO ( RATIO ) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))

Verify the ADC oversampling ratio.

Parameters:
RATIO,: programmed ADC oversampling ratio.
Return values:
SET (RATIO is a valid value) or RESET (RATIO is invalid)

Definition at line 1088 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGOVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters:
__MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1118 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RIGHT_BIT_SHIFT ( __SHIFT__ )
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling shift.

Parameters:
__SHIFT__ programmed ADC oversampling shift.
Return values:
SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

Definition at line 1095 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( __DELAY__ )
Value:
(((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)    )

Verify the ADC multimode delay setting.

Parameters:
__DELAY__ programmed ADC multimode delay setting.
Return values:
SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)

Definition at line 1030 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_SINGLE_DIFFERENTIAL ( __SING_DIFF__ )
Value:
(((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )

Verify the ADC single-ended input or differential mode setting.

Parameters:
__SING_DIFF__ programmed channel setting.
Return values:
SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)

Definition at line 944 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
__MODE__ programmed ADC oversampling triggered mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1110 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Private Constants

CEC Private Constants
CEC
Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Private Functions

CEC Private Functions
CEC
Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CEC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the CEC
      (+) The following parameters need to be configured:
        (++) SignalFreeTime
        (++) Tolerance
        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
        (++) SignalFreeTimeOption      (SFT Timer start definition)
        (++) OwnAddress                (CEC device address)
        (++) ListenMode

Function Documentation

HAL_StatusTypeDef HAL_CEC_DeInit ( CEC_HandleTypeDef * hcec )

DeInitializes the CEC peripheral.

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 273 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, assert_param, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_ISR_ALL_ERROR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspDeInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_RESET, __CEC_HandleTypeDef::Instance, __CEC_HandleTypeDef::MspDeInitCallback, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_Init ( CEC_HandleTypeDef * hcec )

Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 181 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, assert_param, CEC_InitTypeDef::BREErrorBitGen, CEC_InitTypeDef::BRERxStop, CEC_InitTypeDef::BroadcastMsgNoErrorBitGen, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_ErrorCallback(), HAL_CEC_MspInit(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::Init, __CEC_HandleTypeDef::Instance, IS_CEC_BREERRORBITGEN, IS_CEC_BRERXSTOP, IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION, IS_CEC_LBPEERRORBITGEN, IS_CEC_LISTENING_MODE, IS_CEC_OWN_ADDRESS, IS_CEC_SFTOP, IS_CEC_SIGNALFREETIME, IS_CEC_TOLERANCE, CEC_InitTypeDef::LBPEErrorBitGen, CEC_InitTypeDef::ListenMode, __CEC_HandleTypeDef::Lock, __CEC_HandleTypeDef::MspInitCallback, CEC_InitTypeDef::OwnAddress, CEC_InitTypeDef::RxBuffer, __CEC_HandleTypeDef::RxCpltCallback, __CEC_HandleTypeDef::RxState, CEC_InitTypeDef::SignalFreeTime, CEC_InitTypeDef::SignalFreeTimeOption, CEC_InitTypeDef::Tolerance, and __CEC_HandleTypeDef::TxCpltCallback.

void HAL_CEC_MspDeInit ( CEC_HandleTypeDef * hcec )

CEC MSP DeInit.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 400 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_UnRegisterCallback().

void HAL_CEC_MspInit ( CEC_HandleTypeDef * hcec )

CEC MSP Init.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 386 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_Init(), and HAL_CEC_UnRegisterCallback().

HAL_StatusTypeDef HAL_CEC_RegisterCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | HAL_CEC_CallbackIDTypeDef | CallbackID,
 |  | pCEC_CallbackTypeDef | pCallback
 | ) |  |

Register a User CEC Callback To be used instead of the weak predefined callback.

Parameters:
hcec | CEC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
  • HAL_CEC_ERROR_CB_ID Error callback ID
  • HAL_CEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 422 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_CB_ID, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_MSPDEINIT_CB_ID, HAL_CEC_MSPINIT_CB_ID, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TX_CPLT_CB_ID, __CEC_HandleTypeDef::MspDeInitCallback, __CEC_HandleTypeDef::MspInitCallback, and __CEC_HandleTypeDef::TxCpltCallback.

HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | pCEC_RxCallbackTypeDef | pCallback
 | ) |  |

Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.

Parameters:
hcec | CEC handle
pCallback | pointer to the Rx transfer compelete Callback function
Return values:
HAL status

Definition at line 586 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::RxCpltCallback, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_SetDeviceAddress | ( | CEC_HandleTypeDef * | hcec,
 |  | uint16_t | CEC_OwnAddress
 | ) |  |

Initializes the Own Address of the CEC device.

Parameters:
hcec | CEC handle
CEC_OwnAddress | The CEC own address.
Return values:
HAL status

Definition at line 340 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, assert_param, CEC_OWN_ADDRESS_NONE, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::Instance, IS_CEC_OWN_ADDRESS, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_UnRegisterCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | HAL_CEC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an CEC Callback CEC callabck is redirected to the weak predefined callback.

Parameters:
hcec uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
  • HAL_CEC_ERROR_CB_ID Error callback ID
  • HAL_CEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 510 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_CB_ID, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_ErrorCallback(), HAL_CEC_MspDeInit(), HAL_CEC_MSPDEINIT_CB_ID, HAL_CEC_MspInit(), HAL_CEC_MSPINIT_CB_ID, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TX_CPLT_CB_ID, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::MspDeInitCallback, __CEC_HandleTypeDef::MspInitCallback, and __CEC_HandleTypeDef::TxCpltCallback.

HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback ( CEC_HandleTypeDef * hcec )

UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 622 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_READY, __CEC_HandleTypeDef::RxCpltCallback, and __CEC_HandleTypeDef::RxState.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CEC Exported Functions

CEC Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.

Detailed Description

CEC Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the CEC data transfers.

    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)

    (#) The communication is performed using Interrupts.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated CEC IRQ when using Interrupt mode.
           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_CEC_ErrorCallback() user callback will be executed when a communication
           error is detected

    (#) API's with Interrupt are :
         (+) HAL_CEC_Transmit_IT()
         (+) HAL_CEC_IRQHandler()

    (#) A set of User Callbacks are provided:
         (+) HAL_CEC_TxCpltCallback()
         (+) HAL_CEC_RxCpltCallback()
         (+) HAL_CEC_ErrorCallback()

Function Documentation

void HAL_CEC_ChangeRxBuffer | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | Rxbuffer
 | ) |  |

Change Rx Buffer.

Parameters:
hcec | CEC handle
Rxbuffer | Rx Buffer
Note:
This function can be called only inside the HAL_CEC_RxCpltCallback()
Return values:
Frame size

Definition at line 764 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::Init, and CEC_InitTypeDef::RxBuffer.

void HAL_CEC_ErrorCallback ( CEC_HandleTypeDef * hcec )

CEC error callbacks.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 932 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterCallback().

uint32_t HAL_CEC_GetLastReceivedFrameSize ( CEC_HandleTypeDef * hcec )

Get size of the received frame.

Parameters:
hcec CEC handle
Return values:
Frame size

Definition at line 752 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::RxXferSize.

void HAL_CEC_IRQHandler ( CEC_HandleTypeDef * hcec )

This function handles CEC interrupt requests.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 774 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, CEC_FLAG_ARBLST, CEC_FLAG_LBPE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_SBPE, CEC_FLAG_TXBR, CEC_FLAG_TXEND, __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_ARBLST, HAL_CEC_ERROR_BRE, HAL_CEC_ERROR_NONE, HAL_CEC_ERROR_RXACKE, HAL_CEC_ERROR_RXOVR, HAL_CEC_ERROR_TXACKE, HAL_CEC_ERROR_TXERR, HAL_CEC_ERROR_TXUDR, HAL_CEC_ErrorCallback(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY_RX, HAL_CEC_STATE_READY, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::Init, __CEC_HandleTypeDef::Instance, __CEC_HandleTypeDef::pTxBuffPtr, CEC_InitTypeDef::RxBuffer, __CEC_HandleTypeDef::RxCpltCallback, __CEC_HandleTypeDef::RxState, __CEC_HandleTypeDef::RxXferSize, __CEC_HandleTypeDef::TxCpltCallback, and __CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_RxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | uint32_t | RxFrameSize
 | ) |  |

Rx Transfer completed callback.

Parameters:
hcec | CEC handle
RxFrameSize | Size of frame
Return values:
None

Definition at line 917 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_StatusTypeDef HAL_CEC_Transmit_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | InitiatorAddress,
 |  | uint8_t | DestinationAddress,
 |  | uint8_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Send data in interrupt mode.

Parameters:
hcec | CEC handle
InitiatorAddress | Initiator address
DestinationAddress | destination logical address
pData | pointer to input byte data buffer
Size | amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Return values:
HAL status

Definition at line 696 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_INITIATOR_LSB_POS, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, __CEC_HandleTypeDef::pTxBuffPtr, and __CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_TxCpltCallback ( CEC_HandleTypeDef * hcec )

Tx Transfer completed callback.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 902 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control function

Functions
Peripheral Control function
CEC Exported Functions

CEC control functions. More...

Functions

HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC control functions.

 ===============================================================================
                      ##### Peripheral Control function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the CEC.
     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
     (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.

Function Documentation

uint32_t HAL_CEC_GetError ( CEC_HandleTypeDef * hcec )

Return the CEC error code.

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC.
Return values:
CEC Error Code

Definition at line 979 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode.

HAL_CEC_StateTypeDef HAL_CEC_GetState ( CEC_HandleTypeDef * hcec )

return the CEC state

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC module.
Return values:
HAL state

Definition at line 964 of file stm32h7xx_hal_cec.c.

References __CEC_HandleTypeDef::gState, and __CEC_HandleTypeDef::RxState.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Exported Types

Data Structures | Typedefs | Enumerations
CEC Exported Types
CEC

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | __CEC_HandleTypeDef
CEC handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_CEC_StateTypeDef
HAL CEC State definition.
typedef struct __CEC_HandleTypeDef | CEC_HandleTypeDef
CEC handle Structure definition.
typedef void(* | pCEC_CallbackTypeDef )(CEC_HandleTypeDef *hcec)
HAL CEC Callback pointer definition.
typedef void(* | pCEC_RxCallbackTypeDef )(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

Enumerations

enum HAL_CEC_CallbackIDTypeDef {
HAL_CEC_TX_CPLT_CB_ID = 0x00U, HAL_CEC_RX_CPLT_CB_ID = 0x01U, HAL_CEC_ERROR_CB_ID = 0x02U, HAL_CEC_MSPINIT_CB_ID = 0x03U,
HAL_CEC_MSPDEINIT_CB_ID = 0x04U
}
HAL CEC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __CEC_HandleTypeDef CEC_HandleTypeDef

CEC handle Structure definition.

typedef uint32_t HAL_CEC_StateTypeDef

HAL CEC State definition.

Note:
HAL CEC State value is a combination of 2 different substates: gState and RxState (see CEC State Code Definition).
  • gState contains CEC state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7 (not used) x : Should be set to 0 b6 Error information 0 : No Error 1 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized. HAL CEC Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 152 of file stm32h7xx_hal_cec.h.

typedef void(* pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec)

HAL CEC Callback pointer definition.

pointer to an CEC callback function

Definition at line 214 of file stm32h7xx_hal_cec.h.

typedef void(* pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

pointer to an Rx Transfer completed callback function

Definition at line 215 of file stm32h7xx_hal_cec.h.

Enumeration Type Documentation

enum HAL_CEC_CallbackIDTypeDef

HAL CEC Callback ID enumeration definition.

Enumerator:
HAL_CEC_TX_CPLT_CB_ID

CEC Tx Transfer completed callback ID

HAL_CEC_RX_CPLT_CB_ID

CEC Rx Transfer completed callback ID

HAL_CEC_ERROR_CB_ID

CEC error callback ID

HAL_CEC_MSPINIT_CB_ID

CEC Msp Init callback ID

HAL_CEC_MSPDEINIT_CB_ID

CEC Msp DeInit callback ID

Definition at line 202 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_InitTypeDef Struct Reference
CEC Exported Types

CEC Init Structure definition. More...

#include <stm32h7xx_hal_cec.h>

Data Fields

uint32_t | SignalFreeTime
uint32_t | Tolerance
uint32_t | BRERxStop
uint32_t | BREErrorBitGen
uint32_t | LBPEErrorBitGen
uint32_t | BroadcastMsgNoErrorBitGen
uint32_t | SignalFreeTimeOption
uint32_t | ListenMode
uint16_t | OwnAddress
uint8_t * | RxBuffer

Detailed Description

CEC Init Structure definition.

Definition at line 49 of file stm32h7xx_hal_cec.h.

Field Documentation

uint32_t CEC_InitTypeDef::BREErrorBitGen

Set BREGEN bit CEC Error Bit Generation if Bit Rise Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set.

Definition at line 65 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BRERxStop

Set BRESTP bit CEC Reception Stop on Error : specifies whether or not a Bit Rising Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped.

Definition at line 61 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BroadcastMsgNoErrorBitGen

Set BRDNOGEN bit CEC Error Bit Generation on Broadcast message : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message.

It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.

2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set.

Definition at line 75 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::LBPEErrorBitGen

Set LBPEGEN bit CEC Error Bit Generation if Long Bit Period Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation.

Definition at line 70 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::ListenMode

Set LSTN bit CEC Listening mode option : specifies device listening mode. It can take two values:

CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

Definition at line 95 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint16_t CEC_InitTypeDef::OwnAddress

Own addresses configuration This parameter can be a value of CEC Own Address

Definition at line 105 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_InitTypeDef::RxBuffer

CEC Rx buffer pointeur

Definition at line 108 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

uint32_t CEC_InitTypeDef::SignalFreeTime

Set SFT field, specifies the Signal Free Time. It can be one of CEC Signal Free Time setting parameter and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods

Definition at line 51 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTimeOption

Set SFTOP bit CEC Signal Free Time start option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception.

Definition at line 91 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::Tolerance

Set RXTOL bit, specifies the tolerance accepted on the received waveforms, it can be a value of CEC Receiver Tolerance : it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE

Definition at line 57 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cec.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __CEC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CEC_HandleTypeDef Struct Reference
CEC Exported Types

CEC handle Structure definition. More...

#include <stm32h7xx_hal_cec.h>

Data Fields

CEC_TypeDef * | Instance
CEC_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferCount
uint16_t | RxXferSize
HAL_LockTypeDef | Lock
HAL_CEC_StateTypeDef gState
HAL_CEC_StateTypeDef RxState
uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | RxCpltCallback )(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
void(* | ErrorCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | MspInitCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | MspDeInitCallback )(struct __CEC_HandleTypeDef *hcec)

Detailed Description

CEC handle Structure definition.

Definition at line 158 of file stm32h7xx_hal_cec.h.

Field Documentation

void(* __CEC_HandleTypeDef::ErrorCallback)(struct __CEC_HandleTypeDef *hcec)

CEC error callback

Definition at line 190 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

uint32_t __CEC_HandleTypeDef::ErrorCode

For errors handling purposes, copy of ISR register in case error is reported

Definition at line 182 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetError(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_CEC_StateTypeDef __CEC_HandleTypeDef::gState

CEC state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 175 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), and HAL_CEC_UnRegisterCallback().

CEC_InitTypeDef __CEC_HandleTypeDef::Init

CEC communication parameters

Definition at line 165 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

CEC_TypeDef* __CEC_HandleTypeDef::Instance

CEC registers base address

Definition at line 163 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_LockTypeDef __CEC_HandleTypeDef::Lock

Locking object

Definition at line 173 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

void(* __CEC_HandleTypeDef::MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Msp DeInit callback

Definition at line 193 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

void(* __CEC_HandleTypeDef::MspInitCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Msp Init callback

Definition at line 192 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

uint8_t* __CEC_HandleTypeDef::pTxBuffPtr

Pointer to CEC Tx transfer Buffer

Definition at line 167 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

void(* __CEC_HandleTypeDef::RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

CEC Rx Transfer completed callback

Definition at line 188 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterRxCpltCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_CEC_StateTypeDef __CEC_HandleTypeDef::RxState

CEC state information related to Rx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 179 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_UnRegisterRxCpltCallback().

uint16_t __CEC_HandleTypeDef::RxXferSize

CEC Rx Transfer size, 0: header received only

Definition at line 171 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_GetLastReceivedFrameSize(), and HAL_CEC_IRQHandler().

void(* __CEC_HandleTypeDef::TxCpltCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Tx Transfer completed callback

Definition at line 186 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

uint16_t __CEC_HandleTypeDef::TxXferCount

CEC Tx Transfer Counter

Definition at line 169 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cec.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC State Code Definition

Defines
CEC State Code Definition
CEC Exported Constants

Defines

#define | HAL_CEC_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_CEC_STATE_READY ((uint32_t)0x00000020)
#define | HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)
#define | HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)
#define | HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)
#define | HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)

Define Documentation

#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)

an internal process is ongoing Value is allowed for gState only

Definition at line 233 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 235 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)

an internal process is ongoing Value is allowed for gState only

Definition at line 239 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 237 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)

Error Value is allowed for gState only

Definition at line 241 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_STATE_READY ((uint32_t)0x00000020)

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 231 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000)

Peripheral is not yet Initialized Value is allowed for gState and RxState

Definition at line 229 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Error Code

Defines
CEC Error Code
CEC Exported Constants

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)

Define Documentation

#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST

CEC Arbitration Lost

Definition at line 254 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_BRE CEC_ISR_BRE

CEC Rx Bit Rising Error

Definition at line 250 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)

Invalid Callback Error

Definition at line 259 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE

CEC Rx Long Bit period Error

Definition at line 252 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U

no error

Definition at line 248 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE

CEC Rx Missing Acknowledge

Definition at line 253 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR

CEC Rx-Overrun

Definition at line 249 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE

CEC Rx Short Bit period Error

Definition at line 251 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

CEC Tx Missing Acknowledge

Definition at line 257 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR

CEC Tx-Error

Definition at line 256 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR

CEC Tx-Buffer Underrun

Definition at line 255 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Signal Free Time setting parameter

Defines
CEC Signal Free Time setting parameter
CEC Exported Constants

Defines

#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Define Documentation

#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)

Definition at line 269 of file stm32h7xx_hal_cec.h.

#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)

Definition at line 270 of file stm32h7xx_hal_cec.h.

#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)

Definition at line 271 of file stm32h7xx_hal_cec.h.

#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)

Definition at line 272 of file stm32h7xx_hal_cec.h.

#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)

Definition at line 273 of file stm32h7xx_hal_cec.h.

#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)

Definition at line 274 of file stm32h7xx_hal_cec.h.

#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Definition at line 275 of file stm32h7xx_hal_cec.h.

#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)

Definition at line 268 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Receiver Tolerance

Defines
CEC Receiver Tolerance
CEC Exported Constants

Defines

#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Define Documentation

#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Definition at line 284 of file stm32h7xx_hal_cec.h.

#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)

Definition at line 283 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Reception Stop on Error

Defines
CEC Reception Stop on Error
CEC Exported Constants

Defines

#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Define Documentation

#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)

Definition at line 292 of file stm32h7xx_hal_cec.h.

#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Definition at line 293 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Error Bit Generation if Bit Rise Error reported

Defines
CEC Error Bit Generation if Bit Rise Error reported
CEC Exported Constants

Defines

#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Define Documentation

#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Definition at line 302 of file stm32h7xx_hal_cec.h.

#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 301 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Error Bit Generation if Long Bit Period Error reported

Defines
CEC Error Bit Generation if Long Bit Period Error reported
CEC Exported Constants

Defines

#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Define Documentation

#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Definition at line 311 of file stm32h7xx_hal_cec.h.

#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 310 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Error Bit Generation on Broadcast message

Defines
CEC Error Bit Generation on Broadcast message
CEC Exported Constants

Defines

#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Define Documentation

#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)

Definition at line 319 of file stm32h7xx_hal_cec.h.

#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Definition at line 320 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Signal Free Time start option

Defines
CEC Signal Free Time start option
CEC Exported Constants

Defines

#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Define Documentation

#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Definition at line 329 of file stm32h7xx_hal_cec.h.

#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)

Definition at line 328 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Listening mode option

Defines
CEC Listening mode option
CEC Exported Constants

Defines

#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Define Documentation

#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Definition at line 338 of file stm32h7xx_hal_cec.h.

#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)

Definition at line 337 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Device Own Address position in CEC CFGR register

Defines
CEC Device Own Address position in CEC CFGR register
CEC Exported Constants

Defines

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Define Documentation

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Definition at line 346 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Initiator logical address position in message header

Defines
CEC Initiator logical address position in message header
CEC Exported Constants

Defines

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Define Documentation

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Definition at line 354 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Own Address

Defines
CEC Own Address
CEC Exported Constants

Defines

#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Define Documentation

#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */

Definition at line 363 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */

Definition at line 364 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */

Definition at line 373 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */

Definition at line 374 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */

Definition at line 375 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */

Definition at line 376 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Definition at line 377 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */

Definition at line 365 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */

Definition at line 366 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */

Definition at line 367 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */

Definition at line 368 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */

Definition at line 369 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */

Definition at line 370 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */

Definition at line 371 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */

Definition at line 372 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */

Definition at line 362 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_SetDeviceAddress().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Interrupts definition

Defines
CEC Interrupts definition
CEC Exported Constants

Defines

#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE

Define Documentation

#define CEC_IT_ARBLST CEC_IER_ARBLSTIE

Definition at line 390 of file stm32h7xx_hal_cec.h.

#define CEC_IT_BRE CEC_IER_BREIE

Definition at line 394 of file stm32h7xx_hal_cec.h.

#define CEC_IT_LBPE CEC_IER_LBPEIE

Definition at line 392 of file stm32h7xx_hal_cec.h.

#define CEC_IT_RXACKE CEC_IER_RXACKEIE

Definition at line 391 of file stm32h7xx_hal_cec.h.

#define CEC_IT_RXBR CEC_IER_RXBRIE

Definition at line 397 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXEND CEC_IER_RXENDIE

Definition at line 396 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXOVR CEC_IER_RXOVRIE

Definition at line 395 of file stm32h7xx_hal_cec.h.

#define CEC_IT_SBPE CEC_IER_SBPEIE

Definition at line 393 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXACKE CEC_IER_TXACKEIE

Definition at line 385 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXBR CEC_IER_TXBRIE

Definition at line 389 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXEND CEC_IER_TXENDIE

Definition at line 388 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXERR CEC_IER_TXERRIE

Definition at line 386 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXUDR CEC_IER_TXUDRIE

Definition at line 387 of file stm32h7xx_hal_cec.h.

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STM32H7B3xQ HAL User Manual: CEC Flags definition

Defines
CEC Flags definition
CEC Exported Constants

Defines

#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR

Define Documentation

#define CEC_FLAG_ARBLST CEC_ISR_ARBLST

Definition at line 410 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_BRE CEC_ISR_BRE

Definition at line 414 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_LBPE CEC_ISR_LBPE

Definition at line 412 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_RXACKE CEC_ISR_RXACKE

Definition at line 411 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_RXBR CEC_ISR_RXBR

Definition at line 417 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXEND CEC_ISR_RXEND

Definition at line 416 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXOVR CEC_ISR_RXOVR

Definition at line 415 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_SBPE CEC_ISR_SBPE

Definition at line 413 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_TXACKE CEC_ISR_TXACKE

Definition at line 405 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_TXBR CEC_ISR_TXBR

Definition at line 409 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXEND CEC_ISR_TXEND

Definition at line 408 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXERR CEC_ISR_TXERR

Definition at line 406 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_TXUDR CEC_ISR_TXUDR

Definition at line 407 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC all RX or TX errors flags

Defines
CEC all RX or TX errors flags
CEC Exported Constants

Defines

#define CEC_ISR_ALL_ERROR

Define Documentation

#define CEC_ISR_ALL_ERROR
Value:
((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
                                        CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

Definition at line 425 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC all RX errors interrupts enabling flag

Defines
CEC all RX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Define Documentation

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Definition at line 434 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC all TX errors interrupts enabling flag

Defines
CEC all TX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Define Documentation

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Definition at line 442 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Exported Macros

Defines
CEC Exported Macros
CEC

Defines

#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Define Documentation

#define __HAL_CEC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR |= (__FLAG__))

Clears the interrupt or status flag when raised (write at 1)

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the interrupt/status flag to clear. This parameter can be one of the following values:
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
none

Definition at line 512 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define __HAL_CEC_CLEAR_OAR ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

Clear OAR register.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 618 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)

Disables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 587 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to disable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 554 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

#define __HAL_CEC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)

Enables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 581 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to enable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 533 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define __HAL_CEC_FIRST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)

Set Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 593 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define __HAL_CEC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Checks whether or not the specified CEC interrupt flag is set.

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the flag to check.
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
ITStatus

Definition at line 491 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether or not the specified CEC interrupt is enabled.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to check. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
FlagStatus

Definition at line 575 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_END_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

Get Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 612 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_START_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

Get Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 606 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_LAST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)

Set Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

Definition at line 600 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
                                                       (__HANDLE__)->MspInitCallback = NULL;           \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                     } while(0)

Reset CEC handle gstate & RxState.

Parameters:
__HANDLE__ CEC handle.
Return values:
None

Definition at line 461 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_SET_OAR | ( | __HANDLE__,
 |  | __ADDRESS__
 | ) | SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Parameters:
__HANDLE__ | specifies the CEC Handle.
__ADDRESS__ | Own Address value (CEC logical address is identified by bit position)
Return values:
none

Definition at line 626 of file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Private Types

CEC Private Types
CEC
Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Private Variables

CEC Private Variables
CEC
Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CEC Private Macros

Defines
CEC Private Macros
CEC

Defines

#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
Check CEC initiator or destination logical address setting.

Define Documentation

#define IS_CEC_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0xFU)

Check CEC initiator or destination logical address setting.

Initiator and destination addresses are coded over 4 bits.

Parameters:
__ADDRESS__ CEC initiator or logical address.
Return values:
Test result (TRUE or FALSE).

Definition at line 765 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_BREERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

Definition at line 729 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BRERXSTOP ( __BRERXSTOP__ )
Value:
(((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

Definition at line 726 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

Definition at line 735 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LBPEERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

Definition at line 732 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LISTENING_MODE ( __MODE__ )
Value:
(((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

Definition at line 741 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_MSGSIZE ( __SIZE__ ) ((__SIZE__) <= 0x10U)

Check CEC message size.

The message size is the payload size: without counting the header, it varies from 0 byte (ping operation, one header only, no payload) to 15 bytes (1 opcode and up to 14 operands following the header).

Parameters:
__SIZE__ CEC message size.
Return values:
Test result (TRUE or FALSE).

Definition at line 751 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_OWN_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x7FFFU)

Check CEC device Own Address Register (OAR) setting.

OAR address is written in a 15-bit field within CEC_CFGR register.

Parameters:
__ADDRESS__ CEC own address.
Return values:
Test result (TRUE or FALSE).

Definition at line 758 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define IS_CEC_SFTOP ( __SFTOP__ )
Value:
(((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

Definition at line 738 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SIGNALFREETIME ( __SFT__ ) ((__SFT__) <= CEC_CFGR_SFT)

Definition at line 721 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_TOLERANCE ( __RXTOL__ )
Value:
(((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

Definition at line 723 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 464 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, __COMP_HandleTypeDef::MspDeInitCallback, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 264 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_CLEAR_ERRORCODE, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TriggerCallback(), COMP_InitTypeDef::Hysteresis, __COMP_HandleTypeDef::Init, __COMP_HandleTypeDef::Instance, COMP_InitTypeDef::InvertingInput, IS_COMP_BLANKINGSRCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_POWERMODE, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, __COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, __COMP_HandleTypeDef::MspInitCallback, COMP_InitTypeDef::NonInvertingInput, COMP_InitTypeDef::OutputPol, __COMP_HandleTypeDef::State, __COMP_HandleTypeDef::TriggerCallback, COMP_InitTypeDef::TriggerMode, and COMP_InitTypeDef::WindowMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 527 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_DeInit(), and HAL_COMP_UnRegisterCallback().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 513 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Init(), and HAL_COMP_UnRegisterCallback().

HAL_StatusTypeDef HAL_COMP_RegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID,
 |  | pCOMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User COMP Callback To be used instead of the weak predefined callback.

Parameters:
hcomp | Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 550 of file stm32h7xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_UnRegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Parameters:
hcomp Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 632 of file stm32h7xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MspDeInit(), HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MspInit(), HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a Comparator instance without interrupt.
      (+) Stop a Comparator instance without interrupt.
      (+) Start a Comparator instance with interrupt generation.
      (+) Stop a Comparator instance with interrupt generation.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ Handler.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 893 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_CLEAR_C1IFLAG, __HAL_COMP_CLEAR_C2IFLAG, __HAL_COMP_DISABLE_IT, __HAL_COMP_GET_FLAG, __HAL_COMP_GET_IT_SOURCE, CM7_CPUID, COMP_EXTI_LINE_COMP1, COMP_EXTI_LINE_COMP2, COMP_FLAG_C1I, COMP_FLAG_C2I, COMP_GET_EXTI_LINE, COMP_IT_EN, HAL_COMP_STATE_READY, HAL_COMP_TriggerCallback(), HAL_GetCurrentCPUID(), __COMP_HandleTypeDef::Instance, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 721 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Start_IT ( COMP_HandleTypeDef * hcomp )

Enable the interrupt and start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 817 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 774 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Referenced by HAL_COMP_Stop_IT().

HAL_StatusTypeDef HAL_COMP_Stop_IT ( COMP_HandleTypeDef * hcomp )

Disable the interrupt and Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 872 of file stm32h7xx_hal_comp.c.

References COMP_GET_EXTI_LINE, HAL_COMP_Stop(), and __COMP_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

Note:
The output level depends on the selected polarity. If the polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Parameters:
hcomp COMP handle
Return values:
Returns the selected comparator output level:
  • COMP_OUTPUT_LEVEL_LOW
  • COMP_OUTPUT_LEVEL_HIGH

Definition at line 1120 of file stm32h7xx_hal_comp.c.

References assert_param, and __COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 1059 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, HAL_COMP_STATE_BUSY_LOCKED, HAL_COMP_STATE_READY, HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_RESET, HAL_COMP_STATE_RESET_LOCKED, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator trigger callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 1140 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_COMP_GetError ( COMP_HandleTypeDef * hcomp )

Return the COMP error code.

Parameters:
hcomp COMP handle
Return values:
COMP error code

Definition at line 1193 of file stm32h7xx_hal_comp.c.

References assert_param, __COMP_HandleTypeDef::ErrorCode, and __COMP_HandleTypeDef::Instance.

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 1173 of file stm32h7xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Exported Types

Data Structures | Defines | Typedefs | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Define Documentation

#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)

HAL COMP state machine: HAL COMP states definition.

Definition at line 83 of file stm32h7xx_hal_comp.h.

Typedef Documentation

typedef struct __COMP_HandleTypeDef COMP_HandleTypeDef

COMP Handle Structure definition.

typedef void(* pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp)

HAL COMP Callback pointer definition.

pointer to a COMP callback function

Definition at line 130 of file stm32h7xx_hal_comp.h.

Enumeration Type Documentation

enum HAL_COMP_CallbackIDTypeDef

HAL COMP Callback ID enumeration definition.

Enumerator:
HAL_COMP_TRIGGER_CB_ID

COMP trigger callback ID

HAL_COMP_MSPINIT_CB_ID

COMP Msp Init callback ID

HAL_COMP_MSPDEINIT_CB_ID

COMP Msp DeInit callback ID

Definition at line 120 of file stm32h7xx_hal_comp.h.

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 84 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32h7xx_hal_comp.h>

Data Fields

uint32_t | WindowMode
uint32_t | Mode
uint32_t | NonInvertingInput
uint32_t | InvertingInput
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 47 of file stm32h7xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP Blanking Source

Definition at line 72 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 66 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InvertingInput

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 63 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Set comparator operating mode to adjust power and speed. Note: For the characteritics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of COMP power mode

Definition at line 55 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::NonInvertingInput

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 60 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP Output Polarity

Definition at line 69 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 75 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowMode

Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of COMP Window Mode

Definition at line 50 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_comp.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32h7xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TriggerCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspInitCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspDeInitCallback )(struct __COMP_HandleTypeDef *hcomp)

Detailed Description

COMP Handle Structure definition.

Definition at line 98 of file stm32h7xx_hal_comp.h.

Field Documentation

__IO uint32_t __COMP_HandleTypeDef::ErrorCode

COMP error code

Definition at line 107 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_GetError(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

COMP_InitTypeDef __COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 104 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* __COMP_HandleTypeDef::Instance

Register base address

Definition at line 103 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), and HAL_COMP_Stop_IT().

HAL_LockTypeDef __COMP_HandleTypeDef::Lock

Locking object

Definition at line 105 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

void(* __COMP_HandleTypeDef::MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp DeInit callback

Definition at line 111 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::MspInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp Init callback

Definition at line 110 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

__IO HAL_COMP_StateTypeDef __COMP_HandleTypeDef::State

COMP communication state

Definition at line 106 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_RegisterCallback(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::TriggerCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP trigger callback

Definition at line 109 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_comp.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Error Code

Defines
COMP Error Code
COMP Exported Constants

Defines

#define | HAL_COMP_ERROR_NONE (0x00U)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)

Define Documentation

#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)

Invalid Callback error

Definition at line 147 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

#define HAL_COMP_ERROR_NONE (0x00U)

No error

Definition at line 145 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Window Mode

Defines
COMP Window Mode
COMP Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Define Documentation

#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 157 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)

Window mode disable: Comparators instances pair COMP1 and COMP2 are independent

Definition at line 156 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP power mode

Defines
COMP power mode
COMP Exported Constants

Defines

#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)

Define Documentation

#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)

High Speed

Definition at line 169 of file stm32h7xx_hal_comp.h.

#define COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)

Medium Speed

Definition at line 170 of file stm32h7xx_hal_comp.h.

#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)

Ultra-low power mode

Definition at line 171 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)
#define | COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)

Define Documentation

#define COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)

Comparator input plus 2 connected to (DAC2_CH1 for COMP1)

Definition at line 182 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)

Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2)

Definition at line 179 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2)

Definition at line 180 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )
#define | COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )
#define | COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )
#define | COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 192 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 191 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 193 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 195 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 196 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2)

Definition at line 197 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2)

Definition at line 198 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )

Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2)

Definition at line 200 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2)

Definition at line 201 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 194 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)

Define Documentation

#define COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)

Hysteresis level high

Definition at line 213 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)

Hysteresis level low

Definition at line 211 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)

Hysteresis level medium

Definition at line 212 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)

No hysteresis

Definition at line 210 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Output Polarity

Defines
COMP Output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 222 of file stm32h7xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 221 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Blanking Source

Defines
COMP Blanking Source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

Define Documentation

#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)

No blanking source

Definition at line 232 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

TIM15 OC1 selected as blanking source for comparator

Definition at line 238 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)

TIM1 OC5 selected as blanking source for comparator

Definition at line 233 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)

TIM2 OC3 selected as blanking source for comparator

Definition at line 234 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)

TIM3 OC3 selected as blanking source for compartor

Definition at line 235 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)

TIM3 OC4 selected as blanking source for comparator

Definition at line 236 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)

TIM8 OC5 selected as blanking source for comparator

Definition at line 237 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Definition at line 259 of file stm32h7xx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)

Definition at line 256 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 273 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 272 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 274 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 270 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 269 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 271 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)

Comparator output triggering no External Interrupt Line

Definition at line 268 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Flag

Defines
COMP Flag
COMP Exported Constants

Defines

#define | COMP_FLAG_C1I COMP_SR_C1IF
#define | COMP_FLAG_C2I COMP_SR_C2IF
#define | COMP_FLAG_LOCK COMP_CFGRx_LOCK

Define Documentation

#define COMP_FLAG_C1I COMP_SR_C1IF

Comparator 1 Interrupt Flag

Definition at line 283 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_FLAG_C2I COMP_SR_C2IF

Comparator 2 Interrupt Flag

Definition at line 284 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_FLAG_LOCK COMP_CFGRx_LOCK

Lock flag

Definition at line 285 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Interruption Clear Flags

Defines
COMP Interruption Clear Flags
COMP Exported Constants

Defines

#define | COMP_CLEAR_C1IF COMP_ICFR_C1IF
#define | COMP_CLEAR_C2IF COMP_ICFR_C2IF

Define Documentation

#define COMP_CLEAR_C1IF COMP_ICFR_C1IF

Clear Comparator 1 Interrupt Flag

Definition at line 292 of file stm32h7xx_hal_comp.h.

#define COMP_CLEAR_C2IF COMP_ICFR_C2IF

Clear Comparator 2 Interrupt Flag

Definition at line 293 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Interrupts Definitions

Defines
COMP Interrupts Definitions
COMP Exported Constants

Defines

#define COMP_IT_EN COMP_CFGRx_ITEN

Define Documentation

#define COMP_IT_EN COMP_CFGRx_ITEN

Definition at line 300 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 352 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 345 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 370 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 363 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                 \
                                                     (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
                                                     (__HANDLE__)->MspInitCallback = NULL;            \
                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 324 of file stm32h7xx_hal_comp.h.

#define COMP_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)

Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 338 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Clear the the COMP2 EXTI flag.
#define | __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified COMP interrupt source is enabled or disabled.
#define | __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified COMP flag is set or not.
#define | __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
Clears the specified COMP pending flag.
#define | __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
Clear the COMP C1I flag.
#define | __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
Clear the COMP C2I flag.
#define | __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
Enable the specified COMP interrupt.
#define | __HAL_COMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
Disable the specified COMP interrupt.

Define Documentation

#define __HAL_COMP_CLEAR_C1IFLAG ( ) __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)

Clear the COMP C1I flag.

Return values:
None

Definition at line 689 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_CLEAR_C2IFLAG ( ) __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)

Clear the COMP C2I flag.

Return values:
None

Definition at line 694 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_CLEAR_FLAG ( __FLAG__ ) (COMP12->ICFR = (__FLAG__))

Clears the specified COMP pending flag.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • COMP_CLEAR_C1IF : Clear Comparator 1 Interrupt Flag
  • COMP_CLEAR_C2IF : Clear Comparator 2 Interrupt Flag
Return values:
None

Definition at line 684 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 459 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI Line in event mode.

Return values:
None

Definition at line 448 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 403 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 436 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 391 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                            \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();  \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 420 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI Line in event mode.

Return values:
None

Definition at line 442 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 397 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 430 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 384 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                           \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();  \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 410 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 465 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 454 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 D3 EXTI Line in event mode.

Return values:
None

Definition at line 477 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT ( ) SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 D3 EXTI Line in event mode.

Return values:
None

Definition at line 471 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

Clear the the COMP2 EXTI flag.

Return values:
None

Definition at line 593 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI Line in event mode.

Return values:
None

Definition at line 581 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 540 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line.

Return values:
None

Definition at line 569 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 528 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                           \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();  \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 555 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI Line in event mode.

Return values:
None

Definition at line 575 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 534 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line.

Return values:
None

Definition at line 563 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 522 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                           \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();  \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 546 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 611 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 587 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 D3 EXTI Line in event mode.

Return values:
None

Definition at line 605 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT ( ) SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 D3 EXTI Line in event mode.

Return values:
None

Definition at line 599 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))

Disable the specified COMP interrupt.

Parameters:
__HANDLE__,: specifies the COMP Handle.
__INTERRUPT__,: specifies the COMP interrupt source to enable. This parameter can be one of the following values:
  • COMP_CFGRx_ITEN : Comparator interrupt
Return values:
None

Definition at line 712 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )

Enable the specified COMP interrupt.

Parameters:
__HANDLE__,: specifies the COMP Handle.
__INTERRUPT__,: specifies the COMP interrupt source to enable. This parameter can be one of the following values:
  • COMP_CFGRx_ITEN : Comparator interrupt
Return values:
None

Definition at line 703 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_GET_FLAG ( __FLAG__ ) ((COMP12->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified COMP flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • COMP_FLAG_C1I: Comparator 1 Interrupt Flag
  • COMP_FLAG_C2I: Comparator 2 Interrupt Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE)

Definition at line 675 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified COMP interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the COMP Handle. This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
__INTERRUPT__,: specifies the COMP interrupt source to check. This parameter can be one of the following values:
  • COMP_IT_EN: Comparator interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE)

Definition at line 666 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Exported Macros

Modules | Defines
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management

Defines

#define | __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
Enable the specified bit in the Option register.
#define | __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
Disable the specified bit in the Option register.

Define Documentation

#define __HAL_COMP_DISABLE_OR ( __AF__ ) CLEAR_BIT(COMP12->OR, (__AF__))

Disable the specified bit in the Option register.

Parameters:
__AF__,: specifies the Alternate Function source selection . This parameter can be one of the following values:
  • COMP_OR_AFOPA6 : Alternate Function PA6 source selection
  • COMP_OR_AFOPA8 : Alternate Function PA8 source selection
  • COMP_OR_AFOPB12 : Alternate Function PB12 source selection
  • COMP_OR_AFOPE6 : Alternate Function PE6 source selection
  • COMP_OR_AFOPE15 : Alternate Function PE15 source selection
  • COMP_OR_AFOPG2 : Alternate Function PG2 source selection
  • COMP_OR_AFOPG3 : Alternate Function PG3 source selection
  • COMP_OR_AFOPG4 : Alternate Function PG4 source selection
  • COMP_OR_AFOPI1 : Alternate Function PI1 source selection
  • COMP_OR_AFOPI4 : Alternate Function PI4 source selection
  • COMP_OR_AFOPK2 : Alternate Function PK2 source selection
Return values:
None

Definition at line 751 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_ENABLE_OR ( __AF__ ) SET_BIT(COMP12->OR, (__AF__))

Enable the specified bit in the Option register.

Parameters:
__AF__,: specifies the Alternate Function source selection . This parameter can be one of the following values:
  • COMP_OR_AFOPA6 : Alternate Function PA6 source selection
  • COMP_OR_AFOPA8 : Alternate Function PA8 source selection
  • COMP_OR_AFOPB12 : Alternate Function PB12 source selection
  • COMP_OR_AFOPE6 : Alternate Function PE6 source selection
  • COMP_OR_AFOPE15 : Alternate Function PE15 source selection
  • COMP_OR_AFOPG2 : Alternate Function PG2 source selection
  • COMP_OR_AFOPG3 : Alternate Function PG3 source selection
  • COMP_OR_AFOPG4 : Alternate Function PG4 source selection
  • COMP_OR_AFOPI1 : Alternate Function PI1 source selection
  • COMP_OR_AFOPI4 : Alternate Function PI4 source selection
  • COMP_OR_AFOPK2 : Alternate Function PK2 source selection
Return values:
None

Definition at line 733 of file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)

Define Documentation

#define COMP_EXTI_EVENT ((uint32_t) 0x02)

EXTI line event only (without interruption)

Definition at line 773 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING ((uint32_t) 0x20)

EXTI line event on falling edge

Definition at line 775 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT ((uint32_t) 0x01)

EXTI line event with interruption

Definition at line 772 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)

EXTI line 20 connected to COMP1 output

Definition at line 764 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)

EXTI line 21 connected to COMP2 output

Definition at line 765 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING ((uint32_t) 0x10)

EXTI line event on rising edge

Definition at line 774 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Define Documentation

#define COMP_DELAY_STARTUP_US (80UL)

Delay for COMP startup time

Definition at line 221 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 227 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Private macros to get EXTI line associated with Comparators

Defines
COMP Private macros to get EXTI line associated with Comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
                                                      COMP_EXTI_LINE_COMP2)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__,: specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 795 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_Stop_IT().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRCE ( __SOURCE__ )
Value:
(((__SOURCE__) == COMP_BLANKINGSRC_NONE)      || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))

Definition at line 850 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 842 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)        || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)       || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)       || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)            || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)            || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_TPSENS_DAC2CH1) || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT_VDDAP))

Definition at line 821 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC2_CH1))

Definition at line 811 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 867 of file stm32h7xx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 847 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_POWERMODE ( __POWERMODE__ )
Value:
(((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )

Definition at line 806 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 859 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE ( __WINDOWMODE__ )
Value:
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )

Definition at line 803 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 203 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 187 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn | External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
PreemptPriority | The preemption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority | the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 165 of file stm32h7xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 143 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 216 of file stm32h7xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb Specifies the ticks Number of ticks between two interrupts.
Return values:
status - 0 Function succeeded.
  • 1 Function failed.

Definition at line 229 of file stm32h7xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

uint32_t HAL_GetCurrentCPUID ( void )

Returns the current CPU ID.

Return values:
CPU identifier

Definition at line 510 of file stm32h7xx_hal_cortex.c.

References CM7_CPUID.

Referenced by HAL_COMP_IRQHandler(), HAL_EXTI_ClearPending(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), HAL_HSEM_ActivateNotification(), HAL_HSEM_DeactivateNotification(), HAL_HSEM_FastTake(), HAL_HSEM_IRQHandler(), HAL_HSEM_Release(), HAL_HSEM_Take(), HAL_InitTick(), HAL_MDIOS_IRQHandler(), HAL_PWR_EnterSTANDBYMode(), HAL_PWR_EnterSTOPMode(), HAL_PWR_PVD_IRQHandler(), HAL_PWREx_ClearPendingEvent(), HAL_PWREx_EnterSTANDBYMode(), HAL_PWREx_EnterSTOPMode(), HAL_PWREx_PVD_AVD_IRQHandler(), HAL_RTC_AlarmIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initializes and configures the Region and the memory to be protected.

Parameters:
MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 298 of file stm32h7xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_MPU_Disable ( void )

Disables the MPU.

Return values:
None

Definition at line 257 of file stm32h7xx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 280 of file stm32h7xx_hal_cortex.c.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 418 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
status - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 435 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
status - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 402 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn | External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
PriorityGroup the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
pPreemptPriority | Pointer on the Preemptive priority value (starting from 0).
pSubPriority | Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 369 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 342 of file stm32h7xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 384 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 479 of file stm32h7xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 452 of file stm32h7xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 470 of file stm32h7xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32h7xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 48 of file stm32h7xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 61 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 54 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 63 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 50 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 69 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 67 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 65 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 52 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 55 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 57 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of MPU TEX Levels

Definition at line 59 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

Define Documentation

#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 90 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 92 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 94 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 96 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 98 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_Init().

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STM32H7B3xQ HAL User Manual: CORTEX _SysTick clock source

Defines
CORTEX _SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Definition at line 108 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)

Definition at line 107 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU HFNMI and PRIVILEGED Access control

Defines
MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Define Documentation

#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)

Definition at line 119 of file stm32h7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Definition at line 121 of file stm32h7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)

Definition at line 118 of file stm32h7xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)

Definition at line 120 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 130 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 129 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 139 of file stm32h7xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 138 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 148 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 147 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 156 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 157 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 165 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 166 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU TEX Levels

Defines
MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 174 of file stm32h7xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 175 of file stm32h7xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 176 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 186 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 196 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 206 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 193 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 203 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 209 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 189 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 199 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 187 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 197 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 207 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 210 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 190 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 200 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 184 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 194 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 204 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 211 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 191 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 201 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 188 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 198 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 208 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 185 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 195 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 205 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 192 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 202 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 222 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 219 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 223 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 224 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 220 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 221 of file stm32h7xx_hal_cortex.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | MPU_REGION_NUMBER8 ((uint8_t)0x08)
#define | MPU_REGION_NUMBER9 ((uint8_t)0x09)
#define | MPU_REGION_NUMBER10 ((uint8_t)0x0A)
#define | MPU_REGION_NUMBER11 ((uint8_t)0x0B)
#define | MPU_REGION_NUMBER12 ((uint8_t)0x0C)
#define | MPU_REGION_NUMBER13 ((uint8_t)0x0D)
#define | MPU_REGION_NUMBER14 ((uint8_t)0x0E)
#define | MPU_REGION_NUMBER15 ((uint8_t)0x0F)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 232 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 233 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)

Definition at line 243 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)

Definition at line 244 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)

Definition at line 245 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)

Definition at line 246 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)

Definition at line 247 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)

Definition at line 248 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 234 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 235 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 236 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 237 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 238 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 239 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER8 ((uint8_t)0x08)

Definition at line 241 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER9 ((uint8_t)0x09)

Definition at line 242 of file stm32h7xx_hal_cortex.h.

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STM32H7B3xQ HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CORTEX_CPU_Identifier

Defines
CORTEX_CPU_Identifier
CORTEX

Defines

#define CM7_CPUID ((uint32_t)0x00000003)

Define Documentation

#define CM7_CPUID ((uint32_t)0x00000003)

Definition at line 275 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_COMP_IRQHandler(), HAL_EXTI_ClearPending(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), HAL_GetCurrentCPUID(), HAL_InitTick(), HAL_MDIOS_IRQHandler(), HAL_PWR_EnterSTANDBYMode(), HAL_PWR_EnterSTOPMode(), HAL_PWR_PVD_IRQHandler(), HAL_PWREx_ClearPendingEvent(), HAL_PWREx_EnterSTANDBYMode(), HAL_PWREx_EnterSTOPMode(), HAL_PWREx_PVD_AVD_IRQHandler(), HAL_RTC_AlarmIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
#define | IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 368 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 365 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 362 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 359 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 356 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \
                                         ((NUMBER) == MPU_REGION_NUMBER10) || \
                                         ((NUMBER) == MPU_REGION_NUMBER11) || \
                                         ((NUMBER) == MPU_REGION_NUMBER12) || \
                                         ((NUMBER) == MPU_REGION_NUMBER13) || \
                                         ((NUMBER) == MPU_REGION_NUMBER14) || \
                                         ((NUMBER) == MPU_REGION_NUMBER15))

Definition at line 383 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 375 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 410 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FF)

Definition at line 439 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 371 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) (((int32_t)IRQ) >= 0x00)

Definition at line 350 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10UL)

Definition at line 346 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 340 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10UL)

Definition at line 348 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 352 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 483 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 432 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 103 of file stm32h7xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 238 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 223 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

       [..]  or

      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 287 of file stm32h7xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 339 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc CRC handle
Return values:
HAL state

Definition at line 406 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 47 of file stm32h7xx_hal_crc.h.

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STM32H7B3xQ HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32h7xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 59 of file stm32h7xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the peripheral and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 77 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 67 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 61 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 72 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 84 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 87 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 94 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_crc.h
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STM32H7B3xQ HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32h7xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 103 of file stm32h7xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 107 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 113 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 105 of file stm32h7xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 109 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 111 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_crc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7U

X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1

Definition at line 134 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Initial CRC default value

Definition at line 142 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H7B3xQ HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Disable default generating polynomial 0x04C11DB7

Definition at line 151 of file stm32h7xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Enable default generating polynomial 0x04C11DB7

Definition at line 150 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Disable initial CRC default value

Definition at line 160 of file stm32h7xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Enable initial CRC default value

Definition at line 159 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Polynomial sizes to configure the peripheral

Defines
Polynomial sizes to configure the peripheral
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Define Documentation

#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

Resort to a 16-bit long generating polynomial

Definition at line 169 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B 0x00000000U

Resort to a 32-bit long generating polynomial

Definition at line 168 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Resort to a 7-bit long generating polynomial

Definition at line 171 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

Resort to a 8-bit long generating polynomial

Definition at line 170 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32H7B3xQ HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U

Define Documentation

#define HAL_CRC_LENGTH_16B 16U

16-bit long CRC

Definition at line 180 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32U

32-bit long CRC

Definition at line 179 of file stm32h7xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7U

7-bit long CRC

Definition at line 182 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8U

8-bit long CRC

Definition at line 181 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32H7B3xQ HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U

Input data in byte format

Definition at line 195 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U

Input data in half-word format

Definition at line 196 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U

Undefined input data format

Definition at line 194 of file stm32h7xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Input data in word format

Definition at line 197 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32H7B3xQ HAL User Manual: CRC API aliases

Defines
CRC API aliases
CRC Exported Constants

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility

Definition at line 205 of file stm32h7xx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility

Definition at line 206 of file stm32h7xx_hal_crc.h.

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STM32H7B3xQ HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 231 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the data stored in the Independent Data (ID) register.

Parameters:
__HANDLE__ CRC handle
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
Value of the ID register

Definition at line 256 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | CRC handle
__INIT__ | 32-bit initial value
Return values:
None

Definition at line 239 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__ CRC handle.
Return values:
None

Definition at line 224 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store data in the Independent Data (ID) register.

Parameters:
__HANDLE__ | CRC handle
__VALUE__ | Value to be stored in the ID register
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
None

Definition at line 248 of file stm32h7xx_hal_crc.h.

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STM32H7B3xQ HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 278 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 273 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 270 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 267 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H7B3xQ HAL User Manual: Extended Initialization/de-initialization functions

Functions
Extended Initialization/de-initialization functions
CRC Extended Exported Functions

Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc CRC handle
InputReverseMode Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
Return values:
HAL status

Definition at line 159 of file stm32h7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc CRC handle
OutputReverseMode Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 185 of file stm32h7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc CRC handle
Pol CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 89 of file stm32h7xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

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STM32H7B3xQ HAL User Manual: Input Data Inversion Modes

Defines
Input Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0

Byte-wise input data inversion

Definition at line 49 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1

HalfWord-wise input data inversion

Definition at line 50 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U

No input data inversion

Definition at line 48 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Word-wise input data inversion

Definition at line 51 of file stm32h7xx_hal_crc_ex.h.

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STM32H7B3xQ HAL User Manual: Output Data Inversion Modes

Defines
Output Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U

No output data inversion

Definition at line 59 of file stm32h7xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Bit-wise output data inversion

Definition at line 60 of file stm32h7xx_hal_crc_ex.h.

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STM32H7B3xQ HAL User Manual: CRC Extended Exported Macros

Defines
CRC Extended Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 86 of file stm32h7xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 79 of file stm32h7xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ | CRC handle
__POLYNOMIAL__ | 7, 8, 16 or 32-bit polynomial
Return values:
None

Definition at line 94 of file stm32h7xx_hal_crc_ex.h.

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STM32H7B3xQ HAL User Manual: CRC Extended Private Macros

Defines
CRC Extended Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 105 of file stm32h7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 110 of file stm32h7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRYP Exported Functions

CRYP Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callabck is redirected to the weak predefined callback.

Detailed Description

CRYP Initialization and Configuration functions.

  ========================================================================================
     ##### Initialization, de-initialization and Set and Get configuration functions #####
  ========================================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRYP
      (+) DeInitialize the CRYP
      (+) Initialize the CRYP MSP
      (+) DeInitialize the CRYP MSP
      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
          Parameters which are configured in This section are :
          (++) Key size
          (++) Data Type : 32,16, 8 or 1bit
          (++) AlgoMode : for CRYP1 IP
                 ECB and CBC in DES/TDES Standard
                 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef

Function Documentation

HAL_StatusTypeDef HAL_CRYP_DeInit ( CRYP_HandleTypeDef * hcryp )

De-Initializes the CRYP peripheral.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 474 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_PHASE_READY, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_MspDeInit(), HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_GetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Get CRYP Configuration parameters in associated handle.

Parameters:
pConf,: pointer to a CRYP_ConfigTypeDef structure
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 593 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Init ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 406 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_NONE, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_MspInit(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, HAL_GetREVID(), __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Lock, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

void HAL_CRYP_MspDeInit ( CRYP_HandleTypeDef * hcryp )

DeInitializes CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 661 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_MspInit ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 645 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

HAL_StatusTypeDef HAL_CRYP_RegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID,
 |  | pCRYP_CallbackTypeDef | pCallback
 | ) |  |

Register a User CRYP Callback To be used instead of the weak predefined callback.

Parameters:
hcryp | cryp handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 686 of file stm32h7xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_SetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
pConf,: pointer to a CRYP_ConfigTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 524 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_ConfigTypeDef::B0, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NONE, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an CRYP Callback CRYP callabck is redirected to the weak predefined callback.

Parameters:
hcryp cryp handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 780 of file stm32h7xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MspDeInit(), HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MspInit(), HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OutCpltCallback(), HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Encrypt Decrypt functions

Functions
Encrypt Decrypt functions
CRYP Exported Functions

CRYP processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.

Detailed Description

CRYP processing functions.

  ==============================================================================
                      ##### Encrypt Decrypt  functions #####
  ==============================================================================
    [..]  This section provides API allowing to Encrypt/Decrypt Data following
          Standard DES/TDES or AES, and Algorithm configured by the user:
      (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
           (++)  Electronic Code Book(ECB)
           (++) Cipher Block Chaining (CBC)
      (+) Standard AES  supported by CRYP1 IP , list of Algorithm supported:
           (++) Electronic Code Book(ECB)
           (++) Cipher Block Chaining (CBC)
           (++) Counter mode (CTR)
           (++) Cipher Block Chaining (CBC)
           (++) Counter mode (CTR)
           (++) Galois/counter mode (GCM)
           (++) Counter with Cipher Block Chaining-Message(CCM)
    [..]  Three processing functions are available:
      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

Function Documentation

HAL_StatusTypeDef HAL_CRYP_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Decryption mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(plaintext)
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 1028 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_Process(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word
Output,: Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1526 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_DMA(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_TDES_CBC, CRYP_TDES_ECB, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in itnterrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1275 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_IT(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Encryption mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(ciphertext)
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 898 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt(), CRYP_AES_GCM, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_Process(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1394 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TDES_CBC, CRYP_TDES_ECB, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word
Output,: Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1158 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt_IT(), CRYP_AES_GCM, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_DES_CBC, CRYP_DES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP IRQ handler management

Functions
CRYP IRQ handler management
CRYP Exported Functions

CRYP IRQ handler. More...

Functions

void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP IRQ handler.

  ==============================================================================
                ##### CRYP IRQ handler management #####
  ==============================================================================
[..]  This section provides CRYP IRQ handler and callback functions.
      (+) HAL_CRYP_IRQHandler CRYP interrupt request
      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
      (+) HAL_CRYP_ErrorCallback  CRYP error callback
      (+) HAL_CRYP_GetState return the CRYP state
      (+) HAL_CRYP_GetError return the CRYP error code

Function Documentation

void HAL_CRYP_ErrorCallback ( CRYP_HandleTypeDef * hcryp )

CRYP error callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1756 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_SetDMAConfig(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

uint32_t HAL_CRYP_GetError ( CRYP_HandleTypeDef * hcryp )

Return the CRYP error code.

Parameters:
hcryp : pointer to a CRYP_HandleTypeDef structure that contains the configuration information for the CRYP IP
Return values:
CRYP error code

Definition at line 1702 of file stm32h7xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCode.

HAL_CRYP_STATETypeDef HAL_CRYP_GetState ( CRYP_HandleTypeDef * hcryp )

Returns the CRYP state.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL state

Definition at line 1713 of file stm32h7xx_hal_cryp.c.

References __CRYP_HandleTypeDef::State.

void HAL_CRYP_InCpltCallback ( CRYP_HandleTypeDef * hcryp )

Input FIFO transfer completed callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1724 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_IRQHandler ( CRYP_HandleTypeDef * hcryp )

This function handles cryptographic interrupt request.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1662 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AES_IT(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_HEADER, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_IT(), __CRYP_HandleTypeDef::Init, and __CRYP_HandleTypeDef::Instance.

void HAL_CRYP_OutCpltCallback ( CRYP_HandleTypeDef * hcryp )

Output FIFO transfer completed callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1740 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Private Functions

Functions
CRYP Private Functions
CRYP | CRYP Exported Functions

Functions

static HAL_StatusTypeDef | CRYP_TDES_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC Algorithm with DES/TDES standard.
static void | CRYP_TDES_IT (CRYP_HandleTypeDef *hcryp)
CRYP block input/output data handling under interruption with DES/TDES standard.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in iterrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_WaitOnIFEMFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBUSYFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnOFNEFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.

Function Documentation

static HAL_StatusTypeDef CRYP_AES_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Decryption in ECB/CBC & CTR mode with AES Standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 2047 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_WaitOnBUSYFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt().

static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2205 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_FLAG_BUSY, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA().

static HAL_StatusTypeDef CRYP_AES_Decrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2127 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_FLAG_BUSY, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT().

static HAL_StatusTypeDef CRYP_AES_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC & CTR Algorithm with AES Standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
Timeout,: specify Timeout value
Return values:
HAL status

Definition at line 1955 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_PHASE_PROCESS, CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AES_Encrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2003 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PROCESS, CRYP_SetKey(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt_IT().

static void CRYP_AES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Handle CRYP block input/output data handling under interruption.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 2596 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_IT_INI, CRYP_IT_OUTI, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_AES_ProcessData | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Process Data: Write Input data in polling mode and used in AES functions.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Specify Timeout value
Return values:
None

Definition at line 2524 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_WaitOnOFNEFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_AESCCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

AES CCM encryption/decryption processing in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 3218 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_AES_ProcessData(), CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_GCMCCM_SetHeaderPhase(), CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnOFNEFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3594 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESCCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3489 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_IT_INI, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, REV_ID_B, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static HAL_StatusTypeDef CRYP_AESGCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2741 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_AES_ProcessData(), CRYP_FLAG_OFNE, CRYP_GCMCCM_SetHeaderPhase(), CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnOFNEFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3029 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_FLAG_OFNE, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESGCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2964 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_IT_INI, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static void CRYP_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2436 of file stm32h7xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP input data process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2285 of file stm32h7xx_hal_cryp.c.

References HAL_CRYP_InCpltCallback(), __CRYP_HandleTypeDef::InCpltCallback, and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP output data process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2308 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM, CRYP_FLAG_OFNE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by CRYP_SetDMAConfig().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Sets the header phase in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Timeout,: Timeout value
Return values:
state

Definition at line 4029 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase when using DMA in process.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4154 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_FLAG_BUSY, CRYP_FLAG_IFEM, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process_DMA(), and CRYP_AESGCM_Process_DMA().

static void CRYP_GCMCCM_SetHeaderPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4296 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, REV_ID_B, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_GCMCCM_SetPayloadPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the payload phase in iterrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
state

Definition at line 3823 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM, CRYP_FLAG_OFNE, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
inputaddr,: address of the input buffer
Size,: size of the input buffer, must be a multiple of 16.
outputaddr,: address of the output buffer
Return values:
None

Definition at line 2465 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_DMA_Start_IT(), __CRYP_HandleTypeDef::hdmain, __CRYP_HandleTypeDef::hdmaout, __CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static void CRYP_SetKey | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | KeySize
 | ) |  | [static]

Writes Key in Key registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
KeySize,: Size of Key
Return values:
None

Definition at line 2700 of file stm32h7xx_hal_cryp.c.

References CRYP_KEYSIZE_128B, CRYP_KEYSIZE_192B, CRYP_KEYSIZE_256B, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and CRYP_ConfigTypeDef::pKey.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

static void CRYP_TDES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

CRYP block input/output data handling under interruption with DES/TDES standard.

Note:
The function is called under interruption only, once interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 1862 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_GET_FLAG, __HAL_CRYP_GET_IT, CRYP_FLAG_INRIS, CRYP_FLAG_OUTRIS, CRYP_IT_INI, CRYP_IT_OUTI, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_TDES_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC Algorithm with DES/TDES standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout value
Return values:
HAL status

Definition at line 1781 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_WaitOnOFNEFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag | ( | const CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 4745 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_BUSY, HAL_GetTick(), and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_Decrypt(), and CRYP_GCMCCM_SetHeaderPhase().

static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag | ( | const CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 4718 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_IFEM, HAL_GetTick(), and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_GCMCCM_SetHeaderPhase().

static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag | ( | const CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 4774 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_OFNE, HAL_GetTick(), and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), and CRYP_TDES_Process().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Exported Types

Data Structures | Typedefs | Enumerations
CRYP Exported Types
CRYP

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...

Typedef Documentation

typedef struct __CRYP_HandleTypeDef CRYP_HandleTypeDef

CRYP handle Structure definition.

Enumeration Type Documentation

enum HAL_CRYP_STATETypeDef

CRYP State Structure definition.

Enumerator:
HAL_CRYP_STATE_RESET

CRYP not yet initialized or disabled

HAL_CRYP_STATE_READY

CRYP initialized and ready for use

HAL_CRYP_STATE_BUSY

CRYP BUSY, internal processing is ongoing

Definition at line 75 of file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_ConfigTypeDef Struct Reference
CRYP Exported Types

CRYP Init Structure definition. More...

#include <stm32h7xx_hal_cryp.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint32_t * | pKey
uint32_t * | pInitVect
uint32_t | Algorithm
uint32_t * | Header
uint32_t | HeaderSize
uint32_t * | B0
uint32_t | DataWidthUnit

Detailed Description

CRYP Init Structure definition.

Definition at line 49 of file stm32h7xx_hal_cryp.h.

Field Documentation

uint32_t CRYP_ConfigTypeDef::Algorithm

DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of CRYP Algorithm Mode

Definition at line 58 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::B0

B0 is first authentication block used only in AES CCM mode

Definition at line 65 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of CRYP Data Type

Definition at line 51 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::DataWidthUnit

Data With Unit, this parameter can be value of CRYP Data Width Unit

Definition at line 66 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::Header

used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data.

Definition at line 61 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::HeaderSize

The size of header buffer in word

Definition at line 64 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::KeySize

Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. This parameter can be a value of CRYP Key Size

Definition at line 53 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pInitVect

The initialization vector used also as initialization counter in CTR mode

Definition at line 56 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pKey

The key used for encryption/decryption

Definition at line 55 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cryp.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __CRYP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CRYP_HandleTypeDef Struct Reference
CRYP Exported Types

CRYP handle Structure definition. More...

#include <stm32h7xx_hal_cryp.h>

Data Fields

CRYP_TypeDef * | Instance
CRYP_ConfigTypeDef Init
uint32_t * | pCrypInBuffPtr
uint32_t * | pCrypOutBuffPtr
__IO uint16_t | CrypHeaderCount
__IO uint16_t | CrypInCount
__IO uint16_t | CrypOutCount
uint16_t | Size
uint32_t | Phase
DMA_HandleTypeDef * hdmain
DMA_HandleTypeDef * hdmaout
HAL_LockTypeDef | Lock
__IO HAL_CRYP_STATETypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Version
void(* | InCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | OutCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | ErrorCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspInitCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspDeInitCallback )(struct __CRYP_HandleTypeDef *hcryp)

Detailed Description

CRYP handle Structure definition.

Definition at line 88 of file stm32h7xx_hal_cryp.h.

Field Documentation

__IO uint16_t __CRYP_HandleTypeDef::CrypHeaderCount

Counter of header data

Definition at line 102 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), and HAL_CRYP_DeInit().

__IO uint16_t __CRYP_HandleTypeDef::CrypInCount

Counter of input data

Definition at line 104 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

__IO uint16_t __CRYP_HandleTypeDef::CrypOutCount

Counter of output data

Definition at line 106 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

void(* __CRYP_HandleTypeDef::ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Error callback

Definition at line 127 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_SetDMAConfig(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

__IO uint32_t __CRYP_HandleTypeDef::ErrorCode

CRYP peripheral error code

Definition at line 120 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_SetDMAConfig(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetError(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), HAL_CRYP_SetConfig(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmain

CRYP In DMA handle parameters

Definition at line 112 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmaout

CRYP Out DMA handle parameters

Definition at line 114 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

void(* __CRYP_HandleTypeDef::InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Input FIFO transfer completed callback

Definition at line 125 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

CRYP_ConfigTypeDef __CRYP_HandleTypeDef::Init

CRYP required parameters

Definition at line 96 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetKey(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

CRYP_TypeDef* __CRYP_HandleTypeDef::Instance

CRYP registers base address

Definition at line 94 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_WaitOnOFNEFlag(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

HAL_LockTypeDef __CRYP_HandleTypeDef::Lock

CRYP locking object

Definition at line 116 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

void(* __CRYP_HandleTypeDef::MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp DeInit callback

Definition at line 130 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp Init callback

Definition at line 129 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Output FIFO transfer completed callback

Definition at line 126 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

uint32_t* __CRYP_HandleTypeDef::pCrypInBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 98 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t* __CRYP_HandleTypeDef::pCrypOutBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 100 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t __CRYP_HandleTypeDef::Phase

CRYP peripheral phase

Definition at line 110 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint16_t __CRYP_HandleTypeDef::Size

length of input data in word

Definition at line 108 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

__IO HAL_CRYP_STATETypeDef __CRYP_HandleTypeDef::State

CRYP peripheral state

Definition at line 118 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetState(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), HAL_CRYP_SetConfig(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t __CRYP_HandleTypeDef::Version

CRYP1 IP version

Definition at line 122 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cryp.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL CRYP Callback ID enumeration definition

Enumerations
HAL CRYP Callback ID enumeration definition
CRYP

HAL CRYP Callback ID enumeration definition. More...

Enumerations

enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_ERROR_CB_ID = 0x03U, HAL_CRYP_MSPINIT_CB_ID = 0x04U,
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U
}

Detailed Description

HAL CRYP Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_CRYP_CallbackIDTypeDef
Enumerator:
HAL_CRYP_INPUT_COMPLETE_CB_ID

CRYP Input FIFO transfer completed callback ID

HAL_CRYP_OUTPUT_COMPLETE_CB_ID

CRYP Output FIFO transfer completed callback ID

HAL_CRYP_ERROR_CB_ID

CRYP Error callback ID

HAL_CRYP_MSPINIT_CB_ID

CRYP MspInit callback ID

HAL_CRYP_MSPDEINIT_CB_ID

CRYP MspDeInit callback ID

Definition at line 146 of file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL CRYP Callback pointer definition

Typedefs
HAL CRYP Callback pointer definition
CRYP

HAL CRYP Callback pointer definition. More...

Typedefs

typedef void(* pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Detailed Description

HAL CRYP Callback pointer definition.

Typedef Documentation

typedef void(* pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp)

pointer to a common CRYP callback function

Definition at line 165 of file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Error Definition

Defines
CRYP Error Definition
CRYP Exported Constants

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Define Documentation

#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U

Sequence are not respected only for GCM or CCM

Definition at line 188 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_BUSY 0x00000008U

Busy flag error

Definition at line 185 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_DMA 0x00000004U

DMA error

Definition at line 184 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_DMAError(), and CRYP_SetDMAConfig().

#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Invalid Callback error

Definition at line 190 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

#define HAL_CRYP_ERROR_NONE 0x00000000U

No error

Definition at line 181 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U

Not supported mode

Definition at line 187 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define HAL_CRYP_ERROR_READ 0x00000002U

Read error

Definition at line 183 of file stm32h7xx_hal_cryp.h.

#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U

Timeout error

Definition at line 186 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_TDES_Process(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_WRITE 0x00000001U

Write error

Definition at line 182 of file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Data Width Unit

Defines
CRYP Data Width Unit
CRYP Exported Constants

Defines

#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

Define Documentation

#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

By default, size unit is word

Definition at line 203 of file stm32h7xx_hal_cryp.h.

#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U

By default, size unit is word

Definition at line 202 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Algorithm Mode

Defines
CRYP Algorithm Mode
CRYP Exported Constants

Defines

#define | CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define | CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define | CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
#define | CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define | CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define | CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define | CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#define | CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define | CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM

Define Documentation

#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC

Definition at line 218 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM

Definition at line 221 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR

Definition at line 219 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB

Definition at line 217 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM

Definition at line 220 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC

Definition at line 214 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB

Definition at line 213 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC

Definition at line 216 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB

Definition at line 215 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Key Size

Defines
CRYP Key Size
CRYP Exported Constants

Defines

#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define | CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1

Define Documentation

#define CRYP_KEYSIZE_128B 0x00000000U

Definition at line 231 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0

Definition at line 232 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1

Definition at line 233 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Data Type

Defines
CRYP Data Type
CRYP Exported Constants

Defines

#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B CRYP_CR_DATATYPE

Define Documentation

#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0

Definition at line 244 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE

Definition at line 246 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_32B 0x00000000U

Definition at line 243 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1

Definition at line 245 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Interrupt

Defines
CRYP Interrupt
CRYP Exported Constants

Defines

#define | CRYP_IT_INI CRYP_IMSCR_INIM
#define | CRYP_IT_OUTI CRYP_IMSCR_OUTIM

Define Documentation

#define CRYP_IT_INI CRYP_IMSCR_INIM

Input FIFO Interrupt

Definition at line 256 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM

Output FIFO Interrupt

Definition at line 257 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Flags

Defines
CRYP Flags
CRYP Exported Constants

Defines

#define | CRYP_FLAG_IFEM CRYP_SR_IFEM
#define | CRYP_FLAG_IFNF CRYP_SR_IFNF
#define | CRYP_FLAG_OFNE CRYP_SR_OFNE
#define | CRYP_FLAG_OFFU CRYP_SR_OFFU
#define | CRYP_FLAG_BUSY CRYP_SR_BUSY
#define | CRYP_FLAG_OUTRIS 0x01000002U
#define | CRYP_FLAG_INRIS 0x01000001U

Define Documentation

#define CRYP_FLAG_BUSY CRYP_SR_BUSY

The CRYP core is currently processing a block of data or a key preparation (for AES decryption).

Definition at line 272 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_WaitOnBUSYFlag().

#define CRYP_FLAG_IFEM CRYP_SR_IFEM

Input FIFO is empty

Definition at line 268 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_WaitOnIFEMFlag().

#define CRYP_FLAG_IFNF CRYP_SR_IFNF

Input FIFO is not Full

Definition at line 269 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), and CRYP_TDES_Process().

#define CRYP_FLAG_INRIS 0x01000001U

Input FIFO service raw interrupt status

Definition at line 276 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

#define CRYP_FLAG_OFFU CRYP_SR_OFFU

Output FIFO is Full

Definition at line 271 of file stm32h7xx_hal_cryp.h.

#define CRYP_FLAG_OFNE CRYP_SR_OFNE

Output FIFO is not empty

Definition at line 270 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_Process(), CRYP_WaitOnOFNEFlag(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_FLAG_OUTRIS 0x01000002U

Output FIFO service raw interrupt status

Definition at line 275 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Exported Macros

Defines
CRYP Exported Macros
CRYP

Defines

#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.

Define Documentation

#define __HAL_CRYP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)

Definition at line 313 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), HAL_CRYP_DeInit(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))

Disable the CRYP interrupt.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 366 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), and CRYP_TDES_IT().

#define __HAL_CRYP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)

Enable/Disable the CRYP peripheral.

Parameters:
__HANDLE__,: specifies the CRYP handle.
Return values:
None

Definition at line 312 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), CRYP_TDES_Process(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))

Enable the CRYP interrupt.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 354 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

#define __HAL_CRYP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
                                                   ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))

Definition at line 330 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

#define __HAL_CRYP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt is set or not.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: specifies the interrupt to check. This parameter can be one of the following values for CRYP:
  • CRYP_IT_INI: Input FIFO service masked interrupt status
  • CRYP_IT_OUTI: Output FIFO service masked interrupt status
Return values:
The state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 342 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

#define __HAL_CRYP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0)

Reset CRYP handle state.

Parameters:
__HANDLE__ specifies the CRYP handle.
Return values:
None

Definition at line 297 of file stm32h7xx_hal_cryp.h.

#define CRYP_FLAG_MASK 0x0000001FU

Check whether the specified CRYP status flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values for CRYP:
  • CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data or a key preparation (for AES decryption).
  • CRYP_FLAG_IFEM: Input FIFO is empty
  • CRYP_FLAG_IFNF: Input FIFO is not full
  • CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
  • CRYP_FLAG_OFNE: Output FIFO is not empty
  • CRYP_FLAG_OFFU: Output FIFO is full
  • CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
Return values:
The state of __FLAG__ (TRUE or FALSE).

Definition at line 328 of file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Private macros to check input parameters

Defines
CRYP Private macros to check input parameters
CRYP Private Macros

Defines

#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)

Define Documentation

#define IS_CRYP_ALGORITHM ( ALGORITHM )
Value:
(((ALGORITHM) == CRYP_DES_ECB)   || \
                                      ((ALGORITHM)  == CRYP_DES_CBC)   || \
                                      ((ALGORITHM)  == CRYP_TDES_ECB)  || \
                                      ((ALGORITHM)  == CRYP_TDES_CBC)  || \
                                      ((ALGORITHM)  == CRYP_AES_ECB)   || \
                                      ((ALGORITHM)  == CRYP_AES_CBC)   || \
                                      ((ALGORITHM)  == CRYP_AES_CTR)   || \
                                      ((ALGORITHM)  == CRYP_AES_GCM)   || \
                                      ((ALGORITHM)  == CRYP_AES_CCM))

Definition at line 445 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_DATATYPE ( DATATYPE )
Value:
(((DATATYPE) == CRYP_DATATYPE_32B)   || \
                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_1B))

Definition at line 459 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_KEYSIZE ( KEYSIZE )
Value:
(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))

Definition at line 455 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

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STM32H7B3xQ HAL User Manual: CRYP Private Macros

Modules | Defines
CRYP Private Macros
CRYP

Modules

CRYP Private macros to check input parameters

Defines

#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__)
#define | HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Define Documentation

#define CRYP_SET_PHASE | ( | __HANDLE__,
 |  | __PHASE__
 | ) |
Value:
do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
                                                        (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
                                                       }while(0)

Definition at line 312 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_GCMCCM_SetHeaderPhase_IT().

#define HAL_CRYP_FIFO_FLUSH ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Definition at line 316 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

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STM32H7B3xQ HAL User Manual: CRYP Private Constants

CRYP Private Constants
CRYP
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STM32H7B3xQ HAL User Manual: CRYP Private Defines

Defines
CRYP Private Defines
CRYP

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U

Define Documentation

#define CRYP_CCM_CTR1_0 0x07FFFFFFU

Definition at line 298 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_CCM_CTR1_1 0xFFFFFF00U

Definition at line 299 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_CCM_CTR1_2 0x00000001U

Definition at line 300 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR

Decryption

Definition at line 294 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Decrypt_IT().

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode

Definition at line 293 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH

GCM/GMAC or CCM final phase

Definition at line 292 of file stm32h7xx_hal_cryp.c.

#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0

GCM/GMAC or CCM header phase

Definition at line 290 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and HAL_CRYP_IRQHandler().

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 289 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1

GCM(/CCM) payload phase

Definition at line 291 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_GCMCCM_SetHeaderPhase_IT().

#define CRYP_PHASE_PROCESS 0x00000002U

CRYP peripheral is in processing phase

Definition at line 287 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_PHASE_READY 0x00000001U

CRYP peripheral is ready for initialization.

Definition at line 286 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/

Definition at line 284 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), and CRYP_GCMCCM_SetHeaderPhase_DMA().

#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/

Definition at line 283 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/

Definition at line 282 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP Private Variables

CRYP Private Variables
CRYP
Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYP_Private_Functions_prototypes

CRYP_Private_Functions_prototypes
CRYP
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STM32H7B3xQ HAL User Manual: CRYPEx Private Types

CRYPEx Private Types
CRYPEx
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STM32H7B3xQ HAL User Manual: CRYPEx Private Variables

CRYPEx Private Variables
CRYPEx
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STM32H7B3xQ HAL User Manual: CRYPEx Private Constants

CRYPEx Private Constants
CRYPEx
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STM32H7B3xQ HAL User Manual: CRYPEx Private Macros

CRYPEx Private Macros
CRYPEx
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STM32H7B3xQ HAL User Manual: CRYPEx Private Functions

CRYPEx Private Functions
CRYPEx
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STM32H7B3xQ HAL User Manual: Extended AES processing functions

Functions
Extended AES processing functions
CRYPEx Exported Functions

CRYPEx Extended processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

CRYPEx Extended processing functions.

  ==============================================================================
              ##### Extended AES processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to generate the authentication
          TAG in Polling mode
      (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
      (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
         they should be used after Encrypt/Decrypt operation.

Function Documentation

HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

AES CCM Authentication TAG generation.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag,: Pointer to the authentication buffer
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 266 of file stm32h7xx_hal_cryp_ex.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR0_0, CRYP_CCM_CTR0_3, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, REV_ID_B, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

generate the GCM authentication TAG.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag,: Pointer to the authentication buffer
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 109 of file stm32h7xx_hal_cryp_ex.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_32B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, REV_ID_B, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::Version.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRYPEx_Private_Defines

Defines
CRYPEx_Private_Defines
CRYPEx

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Define Documentation

#define CRYP_CCM_CTR0_0 0x07FFFFFFU

Definition at line 65 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_CCM_CTR0_3 0xFFFFFF00U

Definition at line 66 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR

Definition at line 59 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Definition at line 58 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH

Definition at line 56 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0

Definition at line 54 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_PHASE_INIT 0x00000000U

Definition at line 53 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1

Definition at line 55 of file stm32h7xx_hal_cryp_ex.c.

#define CRYPEx_PHASE_FINAL 0x03U

CRYP peripheral is in final phase this is relevant only with CCM and GCM modes

Definition at line 62 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYPEx_PHASE_PROCESS 0x02U

CRYP peripheral is in processing phase

Definition at line 61 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 419 of file stm32h7xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::MspDeInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 358 of file stm32h7xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_NONE, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::Lock, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 480 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 464 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1248 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1355 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 895 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 911 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 943 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 927 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 792 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1248 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data | Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 863 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 522 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, DAC_TRIGGER_SOFTWARE, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData | The destination peripheral Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 607 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 575 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 735 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1355 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 1009 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_CHIPCONNECT_EXTERNAL, DAC_CHIPCONNECT_INTERNAL, DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral, DAC_SampleAndHoldConfTypeDef::DAC_HoldTime, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_OUTPUTBUFFER_ENABLE, DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime, DAC_ChannelConfTypeDef::DAC_SampleAndHold, DAC_SAMPLEANDHOLD_ENABLE, DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig, DAC_SampleAndHoldConfTypeDef::DAC_SampleTime, DAC_ChannelConfTypeDef::DAC_Trigger, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_TIMEOUT, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_TIMEOUT, HAL_Delay(), HAL_GetTick(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_CHIP_CONNECTION, IS_DAC_HOLDTIME, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_REFRESHTIME, IS_DAC_SAMPLEANDHOLD, IS_DAC_SAMPLETIME, IS_DAC_TRIGGER, IS_DAC_TRIMMING, IS_DAC_TRIMMINGVALUE, __DAC_HandleTypeDef::State, and TIMEOUT_DAC_CALIBCONFIG.

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 982 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 1206 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 1193 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Exported Types

Data Structures | Typedefs | Enumerations
DAC Exported Types
DAC

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __DAC_HandleTypeDef DAC_HandleTypeDef

DAC handle Structure definition.

typedef void(* pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac)

HAL DAC Callback pointer definition.

Definition at line 166 of file stm32h7xx_hal_dac.h.

Enumeration Type Documentation

enum HAL_DAC_CallbackIDTypeDef

HAL DAC Callback ID enumeration definition.

Enumerator:
HAL_DAC_CH1_COMPLETE_CB_ID

DAC CH1 Complete Callback ID

HAL_DAC_CH1_HALF_COMPLETE_CB_ID

DAC CH1 half Complete Callback ID

HAL_DAC_CH1_ERROR_ID

DAC CH1 error Callback ID

HAL_DAC_CH1_UNDERRUN_CB_ID

DAC CH1 underrun Callback ID

HAL_DAC_CH2_COMPLETE_CB_ID

DAC CH2 Complete Callback ID

HAL_DAC_CH2_HALF_COMPLETE_CB_ID

DAC CH2 half Complete Callback ID

HAL_DAC_CH2_ERROR_ID

DAC CH2 error Callback ID

HAL_DAC_CH2_UNDERRUN_CB_ID

DAC CH2 underrun Callback ID

HAL_DAC_MSPINIT_CB_ID

DAC MspInit Callback ID

HAL_DAC_MSPDEINIT_CB_ID

DAC MspDeInit Callback ID

HAL_DAC_ALL_CB_ID

DAC All ID

Definition at line 148 of file stm32h7xx_hal_dac.h.

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 50 of file stm32h7xx_hal_dac.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode
void(* | ConvCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | MspInitCallback )(struct __DAC_HandleTypeDef *hdac)
void(* | MspDeInitCallback )(struct __DAC_HandleTypeDef *hdac)

Detailed Description

DAC handle Structure definition.

Definition at line 64 of file stm32h7xx_hal_dac.h.

Field Documentation

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 82 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 86 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 83 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 87 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 75 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 77 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 85 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 89 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 84 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 88 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO uint32_t __DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 79 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start_DMA(), HAL_DAC_UnRegisterCallback(), and HAL_DACEx_DualStart_DMA().

DAC_TypeDef* __DAC_HandleTypeDef::Instance

Register base address

Definition at line 69 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef __DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 73 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Init().

void(* __DAC_HandleTypeDef::MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 92 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::MspInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 91 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO HAL_DAC_StateTypeDef __DAC_HandleTypeDef::State

DAC communication state

Definition at line 71 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DAC_UnRegisterCallback(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC_SampleAndHoldConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_SampleAndHoldConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration sample and hold Channel structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleTime
uint32_t | DAC_HoldTime
uint32_t | DAC_RefreshTime

Detailed Description

DAC Configuration sample and hold Channel structure definition.

Definition at line 100 of file stm32h7xx_hal_dac.h.

Field Documentation

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_HoldTime

Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 106 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime

Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255

Definition at line 110 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_SampleTime

Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 102 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleAndHold
uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer
uint32_t | DAC_ConnectOnChipPeripheral
uint32_t | DAC_UserTrimming
uint32_t | DAC_TrimmingValue
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 118 of file stm32h7xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral

Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of DAC ConnectOnChipPeripheral

Definition at line 129 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer

Definition at line 126 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_SampleAndHold

Specifies whether the DAC mode. This parameter can be a value of DAC power mode

Definition at line 120 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

DAC_SampleAndHoldConfTypeDef DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig

Sample and Hold settings

Definition at line 140 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection

Definition at line 123 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_TrimmingValue

Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 136 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

uint32_t DAC_ChannelConfTypeDef::DAC_UserTrimming

Specifies the trimming mode This parameter must be a value of DAC User Trimming DAC_UserTrimming is either factory or user trimming

Definition at line 132 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04U

DMA error

Definition at line 185 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U

DAC channel1 DMA underrun error

Definition at line 183 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U

DAC channel2 DMA underrun error

Definition at line 184 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Invalid callback error

Definition at line 188 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

#define HAL_DAC_ERROR_NONE 0x00U

No error

Definition at line 182 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

#define HAL_DAC_ERROR_TIMEOUT 0x08U

Timeout error

Definition at line 186 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC trigger selection

Defines
DAC trigger selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE 0x00000000U
#define | DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

Define Documentation

#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 214 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel

Definition at line 212 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)

LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel

Definition at line 213 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel

Definition at line 222 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_NONE 0x00000000U

Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger

Definition at line 198 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)

Conversion started by software trigger for DAC channel

Definition at line 199 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start().

#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)

TIM15 TRGO selected as external conversion trigger for DAC channel

Definition at line 207 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM1 TRGO selected as external conversion trigger for DAC channel

Definition at line 200 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 201 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 202 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 203 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 204 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 205 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM8 TRGO selected as external conversion trigger for DAC channel

Definition at line 206 of file stm32h7xx_hal_dac.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Definition at line 233 of file stm32h7xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U

Definition at line 232 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Channel selection

Defines
DAC Channel selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U

Define Documentation

#define DAC_CHANNEL_1 0x00000000U

Definition at line 242 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_CHANNEL_2 0x00000010U

Definition at line 243 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), and HAL_DACEx_DualStop_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC data alignment

Defines
DAC data alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U

Define Documentation

#define DAC_ALIGN_12B_L 0x00000004U

Definition at line 252 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define DAC_ALIGN_12B_R 0x00000000U

Definition at line 251 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_ALIGN_8B_R 0x00000008U

Definition at line 253 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DACEx_DualSetValue(), and HAL_DACEx_DualStart_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 262 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 263 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC IT definition

Defines
DAC IT definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 272 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 273 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC ConnectOnChipPeripheral

Defines
DAC ConnectOnChipPeripheral
DAC Exported Constants

Defines

#define | DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define | DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define | DAC_CHIPCONNECT_BOTH (1UL << 2)

Define Documentation

#define DAC_CHIPCONNECT_BOTH (1UL << 2)

Definition at line 284 of file stm32h7xx_hal_dac.h.

#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)

Definition at line 282 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)

Definition at line 283 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC User Trimming

Defines
DAC User Trimming
DAC Exported Constants

Defines

#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)

Define Documentation

#define DAC_TRIMMING_FACTORY (0x00000000UL)

Factory trimming

Definition at line 293 of file stm32h7xx_hal_dac.h.

#define DAC_TRIMMING_USER (0x00000001UL)

User trimming

Definition at line 294 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC power mode

Defines
DAC power mode
DAC Exported Constants

Defines

#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Define Documentation

#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)

Definition at line 302 of file stm32h7xx_hal_dac.h.

#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Definition at line 303 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 414 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Disable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle
__DAC_Channel__ | specifies the DAC channel.
Return values:
None

Definition at line 345 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStop(), and HAL_DACEx_DualStop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 384 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Stop_DMA(), and HAL_DACEx_DualStop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Enable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle.
__DAC_Channel__ | specifies the DAC channel
Return values:
None

Definition at line 337 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart(), and HAL_DACEx_DualStart_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 374 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 404 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__ DAC handle
__INTERRUPT__ DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 394 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
                                                     } while(0)

Reset DAC handle state.

Parameters:
__HANDLE__ specifies the DAC handle.
Return values:
None

Definition at line 323 of file stm32h7xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (0x00000008UL + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 352 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (0x00000014UL + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 358 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (0x00000020UL + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 364 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 431 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), HAL_DACEx_DualSetValue(), and HAL_DACEx_DualStart_DMA().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 428 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0UL)

Definition at line 435 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 425 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_REFRESHTIME ( TIME ) ((TIME) <= 0x000000FFUL)

Definition at line 437 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DAC

Functions

void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1466 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1502 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1485 of file stm32h7xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, and HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Define Documentation

#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Definition at line 321 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
DACEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.

Detailed Description

Extended IO operation functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 495 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 511 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 543 of file stm32h7xx_hal_dac_ex.c.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 769 of file stm32h7xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment | Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1 | Data for DAC Channel1 to be loaded in the selected data holding register.
Data2 | Data for DAC Channel2 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 459 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DACEx_DualStart ( DAC_HandleTypeDef * hdac )

Enables DAC and starts conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 115 of file stm32h7xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, DAC_CHANNEL_1, DAC_CHANNEL_2, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_DualStart_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The DAC channel that will request data from DMA. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData | The destination peripheral Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 189 of file stm32h7xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DACEx_DualStop ( DAC_HandleTypeDef * hdac )

Disables DAC and stop conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 158 of file stm32h7xx_hal_dac_ex.c.

References __HAL_DAC_DISABLE, DAC_CHANNEL_1, DAC_CHANNEL_2, HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_DualStop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion both channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The DAC channel that requests data from DMA. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 298 of file stm32h7xx_hal_dac_ex.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 527 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 736 of file stm32h7xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 419 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 566 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 694 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 370 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DACEx Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 769 of file stm32h7xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 736 of file stm32h7xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 566 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 694 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DACEx private functions

Functions
DACEx private functions
DACEx

Extended private functions. More...

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended private functions.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 801 of file stm32h7xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh2, HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 837 of file stm32h7xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 820 of file stm32h7xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, and HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DACEx lfsrunmask triangle amplitude

Defines
DACEx lfsrunmask triangle amplitude
DACEx Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 0x00000000UL

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 56 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 66 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 67 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 57 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 58 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 59 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 60 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 61 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 62 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 63 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 64 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 65 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL

Select max triangle amplitude of 1

Definition at line 68 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 77 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 127

Definition at line 74 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 71 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 2047

Definition at line 78 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 75 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 69 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Select max triangle amplitude of 31

Definition at line 72 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 79 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )

Select max triangle amplitude of 511

Definition at line 76 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 73 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Select max triangle amplitude of 7

Definition at line 70 of file stm32h7xx_hal_dac_ex.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_CHIP_CONNECTION ( CONNECT )
Value:
(((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_BOTH))

Definition at line 157 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HOLDTIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 148 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 164 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_NEWTRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 155 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SetUserTrimming().

#define IS_DAC_SAMPLEANDHOLD ( MODE )
Value:
(((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

Definition at line 150 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAMPLETIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 146 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE)       || \
                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
                                 ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 114 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == DAC_TRIMMING_FACTORY) || \
                                   ((TRIMMING) == DAC_TRIMMING_USER))

Definition at line 161 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 153 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
DCMI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
HAL_StatusTypeDef | HAL_DCMI_RegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
Register a User DCMI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DCMI_UnRegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
Unregister a DCMI Callback DCMI callabck is redirected to the weak predefined callback.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DCMI
      (+) De-initialize the DCMI

Function Documentation

HAL_StatusTypeDef HAL_DCMI_DeInit ( DCMI_HandleTypeDef * hdcmi )

Deinitializes the DCMI peripheral registers to their default reset values.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 265 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspDeInit(), HAL_DCMI_STATE_RESET, __DCMI_HandleTypeDef::MspDeInitCallback, and __DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Init ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 173 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE_IT, assert_param, DCMI_InitTypeDef::ByteSelectMode, DCMI_InitTypeDef::ByteSelectStart, DCMI_InitTypeDef::CaptureRate, DCMI_IT_ERR, DCMI_IT_LINE, DCMI_IT_OVR, DCMI_IT_VSYNC, DCMI_SYNCHRO_EMBEDDED, __DCMI_HandleTypeDef::ErrorCallback, __DCMI_HandleTypeDef::ErrorCode, DCMI_InitTypeDef::ExtendedDataMode, DCMI_CodesInitTypeDef::FrameEndCode, __DCMI_HandleTypeDef::FrameEventCallback, DCMI_CodesInitTypeDef::FrameStartCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_ErrorCallback(), HAL_DCMI_FrameEventCallback(), HAL_DCMI_LineEventCallback(), HAL_DCMI_MspInit(), HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, HAL_DCMI_VsyncEventCallback(), DCMI_InitTypeDef::HSPolarity, __DCMI_HandleTypeDef::Init, __DCMI_HandleTypeDef::Instance, IS_DCMI_BYTE_SELECT_MODE, IS_DCMI_BYTE_SELECT_START, IS_DCMI_CAPTURE_RATE, IS_DCMI_EXTENDED_DATA, IS_DCMI_HSPOLARITY, IS_DCMI_LINE_SELECT_MODE, IS_DCMI_LINE_SELECT_START, IS_DCMI_MODE_JPEG, IS_DCMI_PCKPOLARITY, IS_DCMI_SYNCHRO, IS_DCMI_VSPOLARITY, DCMI_InitTypeDef::JPEGMode, DCMI_CodesInitTypeDef::LineEndCode, __DCMI_HandleTypeDef::LineEventCallback, DCMI_InitTypeDef::LineSelectMode, DCMI_InitTypeDef::LineSelectStart, DCMI_CodesInitTypeDef::LineStartCode, __DCMI_HandleTypeDef::MspInitCallback, DCMI_InitTypeDef::PCKPolarity, __DCMI_HandleTypeDef::State, DCMI_InitTypeDef::SynchroMode, DCMI_InitTypeDef::SyncroCode, DCMI_InitTypeDef::VSPolarity, and __DCMI_HandleTypeDef::VsyncEventCallback.

void HAL_DCMI_MspDeInit ( DCMI_HandleTypeDef * hdcmi )

DeInitializes the DCMI MSP.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 502 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_DeInit(), and HAL_DCMI_UnRegisterCallback().

void HAL_DCMI_MspInit ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI MSP.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 486 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_UnRegisterCallback().

HAL_StatusTypeDef HAL_DCMI_RegisterCallback | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | HAL_DCMI_CallbackIDTypeDef | CallbackID,
 |  | pDCMI_CallbackTypeDef | pCallback
 | ) |  |

Register a User DCMI Callback To be used instead of the weak predefined callback.

Parameters:
hdcmi | DCMI handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
  • HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
  • HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
  • HAL_DCMI_ERROR_CB_ID Error callback ID
  • HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
  • HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 308 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::ErrorCallback, __DCMI_HandleTypeDef::ErrorCode, __DCMI_HandleTypeDef::FrameEventCallback, HAL_DCMI_ERROR_CB_ID, HAL_DCMI_ERROR_INVALID_CALLBACK, HAL_DCMI_FRAME_EVENT_CB_ID, HAL_DCMI_LINE_EVENT_CB_ID, HAL_DCMI_MSPDEINIT_CB_ID, HAL_DCMI_MSPINIT_CB_ID, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, HAL_DCMI_VSYNC_EVENT_CB_ID, __DCMI_HandleTypeDef::LineEventCallback, __DCMI_HandleTypeDef::MspDeInitCallback, __DCMI_HandleTypeDef::MspInitCallback, __DCMI_HandleTypeDef::State, and __DCMI_HandleTypeDef::VsyncEventCallback.

HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | HAL_DCMI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a DCMI Callback DCMI callabck is redirected to the weak predefined callback.

Parameters:
hdcmi DCMI handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
  • HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
  • HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
  • HAL_DCMI_ERROR_CB_ID Error callback ID
  • HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
  • HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 404 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::ErrorCallback, __DCMI_HandleTypeDef::ErrorCode, __DCMI_HandleTypeDef::FrameEventCallback, HAL_DCMI_ERROR_CB_ID, HAL_DCMI_ERROR_INVALID_CALLBACK, HAL_DCMI_ErrorCallback(), HAL_DCMI_FRAME_EVENT_CB_ID, HAL_DCMI_FrameEventCallback(), HAL_DCMI_LINE_EVENT_CB_ID, HAL_DCMI_LineEventCallback(), HAL_DCMI_MspDeInit(), HAL_DCMI_MSPDEINIT_CB_ID, HAL_DCMI_MspInit(), HAL_DCMI_MSPINIT_CB_ID, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, HAL_DCMI_VSYNC_EVENT_CB_ID, HAL_DCMI_VsyncEventCallback(), __DCMI_HandleTypeDef::LineEventCallback, __DCMI_HandleTypeDef::MspDeInitCallback, __DCMI_HandleTypeDef::MspInitCallback, __DCMI_HandleTypeDef::State, and __DCMI_HandleTypeDef::VsyncEventCallback.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
DCMI Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure destination address and data length and
          Enables DCMI DMA request and enables DCMI capture
      (+) Stop the DCMI capture.
      (+) Handles DCMI interrupt request.

Function Documentation

void HAL_DCMI_ErrorCallback ( DCMI_HandleTypeDef * hdcmi )

Error DCMI callback.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 870 of file stm32h7xx_hal_dcmi.c.

Referenced by DCMI_DMAError(), HAL_DCMI_Init(), and HAL_DCMI_UnRegisterCallback().

void HAL_DCMI_FrameEventCallback ( DCMI_HandleTypeDef * hdcmi )

Frame Event callback.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 917 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), and HAL_DCMI_UnRegisterCallback().

void HAL_DCMI_IRQHandler ( DCMI_HandleTypeDef * hdcmi )

Handles DCMI interrupt request.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for the DCMI.
Return values:
None

Definition at line 771 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_CLEAR_FLAG, __HAL_DCMI_DISABLE_IT, DCMI_DMAError(), DCMI_FLAG_ERRRI, DCMI_FLAG_FRAMERI, DCMI_FLAG_LINERI, DCMI_FLAG_OVRRI, DCMI_FLAG_VSYNCRI, DCMI_IT_ERR, DCMI_IT_FRAME, DCMI_IT_LINE, DCMI_IT_OVR, DCMI_IT_VSYNC, DCMI_MODE_SNAPSHOT, __DCMI_HandleTypeDef::DMA_Handle, __DCMI_HandleTypeDef::ErrorCode, __DCMI_HandleTypeDef::FrameEventCallback, HAL_DCMI_ERROR_OVR, HAL_DCMI_ERROR_SYNC, HAL_DCMI_FrameEventCallback(), HAL_DCMI_LineEventCallback(), HAL_DCMI_STATE_ERROR, HAL_DCMI_VsyncEventCallback(), HAL_DMA_Abort_IT(), __DCMI_HandleTypeDef::Instance, __DCMI_HandleTypeDef::LineEventCallback, __DCMI_HandleTypeDef::State, __DCMI_HandleTypeDef::VsyncEventCallback, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_DCMI_LineEventCallback ( DCMI_HandleTypeDef * hdcmi )

Line Event callback.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 886 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), and HAL_DCMI_UnRegisterCallback().

HAL_StatusTypeDef HAL_DCMI_Resume ( DCMI_HandleTypeDef * hdcmi )

Resume DCMI capture.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 745 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_SUSPENDED, __DCMI_HandleTypeDef::Instance, and __DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Start_DMA | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | DCMI_Mode,
 |  | uint32_t | pData,
 |  | uint32_t | Length
 | ) |  |

Enables DCMI DMA request and enables DCMI capture.

Parameters:
hdcmi | pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
DCMI_Mode | DCMI capture mode snapshot or continuous grab.
pData | The destination memory Buffer address (LCD Frame buffer).
Length | The length of capture to be transferred.
Return values:
HAL status

Definition at line 541 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE, assert_param, DCMI_DMAError(), DCMI_DMAXferCplt(), __DCMI_HandleTypeDef::DMA_Handle, __DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_DMA, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart_IT(), __DCMI_HandleTypeDef::Instance, IS_DCMI_CAPTURE_MODE, __DCMI_HandleTypeDef::pBuffPtr, __DCMI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DCMI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferM1CpltCallback, __DCMI_HandleTypeDef::XferSize, and __DCMI_HandleTypeDef::XferTransferNumber.

HAL_StatusTypeDef HAL_DCMI_Stop ( DCMI_HandleTypeDef * hdcmi )

Disable DCMI DMA request and Disable DCMI capture.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 644 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_DISABLE, __DCMI_HandleTypeDef::DMA_Handle, __DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_ERROR_TIMEOUT, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DMA_Abort(), HAL_TIMEOUT_DCMI_STOP, __DCMI_HandleTypeDef::Instance, and __DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Suspend ( DCMI_HandleTypeDef * hdcmi )

Suspend DCMI capture.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 698 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_TIMEOUT, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_SUSPENDED, HAL_TIMEOUT_DCMI_STOP, __DCMI_HandleTypeDef::Instance, and __DCMI_HandleTypeDef::State.

void HAL_DCMI_VsyncEventCallback ( DCMI_HandleTypeDef * hdcmi )

VSYNC Event callback.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 901 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), and HAL_DCMI_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DCMI Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
[..]  This section provides functions allowing to:
      (+) Configure the CROP feature.
      (+) Enable/Disable the CROP feature.

Function Documentation

HAL_StatusTypeDef HAL_DCMI_ConfigCrop | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize
 | ) |  |

Configure the DCMI CROP coordinate.

Parameters:
hdcmi | pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
YSize | DCMI Line number
XSize | DCMI Pixel per line
X0 | DCMI window X offset
Y0 | DCMI window Y offset
Return values:
HAL status

Definition at line 956 of file stm32h7xx_hal_dcmi.c.

References assert_param, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, __DCMI_HandleTypeDef::Instance, IS_DCMI_WINDOW_COORDINATE, IS_DCMI_WINDOW_HEIGHT, and __DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_DisableCrop ( DCMI_HandleTypeDef * hdcmi )

Disable the Crop feature.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 989 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, __DCMI_HandleTypeDef::Instance, and __DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_EnableCrop ( DCMI_HandleTypeDef * hdcmi )

Enable the Crop feature.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 1015 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, __DCMI_HandleTypeDef::Instance, and __DCMI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DCMI Exported Functions

Peripheral State functions. More...

Functions

HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
               ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DCMI state.
      (+) Get the specific DCMI error flag.

Function Documentation

uint32_t HAL_DCMI_GetError ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI error code.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
DCMI Error Code

Definition at line 1072 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::ErrorCode.

HAL_DCMI_StateTypeDef HAL_DCMI_GetState ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI state.

Parameters:
hdcmi pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL state

Definition at line 1061 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Private Functions

Functions
DCMI Private Functions
DCMI Exported Functions | DCMI

Functions

static void | DCMI_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DCMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1155 of file stm32h7xx_hal_dcmi.c.

References __DCMI_HandleTypeDef::DMA_Handle, __DCMI_HandleTypeDef::ErrorCallback, __DCMI_HandleTypeDef::ErrorCode, __DMA_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_DMA, HAL_DCMI_ErrorCallback(), HAL_DCMI_STATE_READY, HAL_DMA_ERROR_FE, and __DCMI_HandleTypeDef::State.

Referenced by HAL_DCMI_IRQHandler(), and HAL_DCMI_Start_DMA().

static void DCMI_DMAXferCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1090 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE_IT, DCMI_IT_FRAME, DCMI_MODE_SNAPSHOT, __DCMI_HandleTypeDef::DMA_Handle, HAL_DCMI_STATE_READY, HAL_DMAEx_ChangeMemory(), __DCMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, MEMORY0, MEMORY1, __DCMI_HandleTypeDef::pBuffPtr, __DCMI_HandleTypeDef::State, __DCMI_HandleTypeDef::XferCount, __DCMI_HandleTypeDef::XferSize, and __DCMI_HandleTypeDef::XferTransferNumber.

Referenced by HAL_DCMI_Start_DMA().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Exported Types

Data Structures | Typedefs | Enumerations
DCMI Exported Types
DCMI

Data Structures

struct | DCMI_CodesInitTypeDef
DCMI Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...
struct | __DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Typedefs

typedef struct __DCMI_HandleTypeDef | DCMI_HandleTypeDef
DCMI handle Structure definition.
typedef void(* | pDCMI_CallbackTypeDef )(DCMI_HandleTypeDef *hdcmi)
HAL DCMI Callback pointer definition.

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00U, HAL_DCMI_STATE_READY = 0x01U, HAL_DCMI_STATE_BUSY = 0x02U, HAL_DCMI_STATE_TIMEOUT = 0x03U,
HAL_DCMI_STATE_ERROR = 0x04U, HAL_DCMI_STATE_SUSPENDED = 0x05U
}
HAL DCMI State structures definition. More...
enum HAL_DCMI_CallbackIDTypeDef {
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, HAL_DCMI_ERROR_CB_ID = 0x03U,
HAL_DCMI_MSPINIT_CB_ID = 0x04U, HAL_DCMI_MSPDEINIT_CB_ID = 0x05U
}
HAL DCMI Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __DCMI_HandleTypeDef DCMI_HandleTypeDef

DCMI handle Structure definition.

typedef void(* pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi)

HAL DCMI Callback pointer definition.

pointer to a DCMI callback function

Definition at line 171 of file stm32h7xx_hal_dcmi.h.

Enumeration Type Documentation

enum HAL_DCMI_CallbackIDTypeDef

HAL DCMI Callback ID enumeration definition.

Enumerator:
HAL_DCMI_FRAME_EVENT_CB_ID

DCMI Frame event Callback ID

HAL_DCMI_VSYNC_EVENT_CB_ID

DCMI Vsync event Callback ID

HAL_DCMI_LINE_EVENT_CB_ID

DCMI Line event Callback ID

HAL_DCMI_ERROR_CB_ID

DCMI Error Callback ID

HAL_DCMI_MSPINIT_CB_ID

DCMI MspInit callback ID

HAL_DCMI_MSPDEINIT_CB_ID

DCMI MspDeInit callback ID

Definition at line 157 of file stm32h7xx_hal_dcmi.h.

enum HAL_DCMI_StateTypeDef

HAL DCMI State structures definition.

Enumerator:
HAL_DCMI_STATE_RESET

DCMI not yet initialized or disabled

HAL_DCMI_STATE_READY

DCMI initialized and ready for use

HAL_DCMI_STATE_BUSY

DCMI internal processing is ongoing

HAL_DCMI_STATE_TIMEOUT

DCMI timeout state

HAL_DCMI_STATE_ERROR

DCMI error state

HAL_DCMI_STATE_SUSPENDED

DCMI suspend state

Definition at line 48 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI_CodesInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_CodesInitTypeDef Struct Reference
DCMI Exported Types

DCMI Embedded Synchronisation CODE Init structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

uint8_t | FrameStartCode
uint8_t | LineStartCode
uint8_t | LineEndCode
uint8_t | FrameEndCode

Detailed Description

DCMI Embedded Synchronisation CODE Init structure definition.

Definition at line 61 of file stm32h7xx_hal_dcmi.h.

Field Documentation

uint8_t DCMI_CodesInitTypeDef::FrameEndCode

Specifies the code of the frame end delimiter.

Definition at line 66 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::FrameStartCode

Specifies the code of the frame start delimiter.

Definition at line 63 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineEndCode

Specifies the code of the line end delimiter.

Definition at line 65 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineStartCode

Specifies the code of the line start delimiter.

Definition at line 64 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_InitTypeDef Struct Reference
DCMI Exported Types

DCMI Init structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

uint32_t | SynchroMode
uint32_t | PCKPolarity
uint32_t | VSPolarity
uint32_t | HSPolarity
uint32_t | CaptureRate
uint32_t | ExtendedDataMode
DCMI_CodesInitTypeDef SyncroCode
uint32_t | JPEGMode
uint32_t | ByteSelectMode
uint32_t | ByteSelectStart
uint32_t | LineSelectMode
uint32_t | LineSelectStart

Detailed Description

DCMI Init structure definition.

Definition at line 72 of file stm32h7xx_hal_dcmi.h.

Field Documentation

uint32_t DCMI_InitTypeDef::ByteSelectMode

Specifies the data to be captured by the interface This parameter can be a value of DCMI Byte Select Mode

Definition at line 98 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ByteSelectStart

Specifies if the data to be captured by the interface is even or odd This parameter can be a value of DCMI Byte Select Start

Definition at line 101 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::CaptureRate

Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of DCMI Capture Rate

Definition at line 86 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ExtendedDataMode

Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of DCMI Extended Data Mode

Definition at line 89 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::HSPolarity

Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of DCMI HSYNC Polarity

Definition at line 83 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::JPEGMode

Enable or Disable the JPEG mode. This parameter can be a value of DCMI MODE JPEG

Definition at line 95 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectMode

Specifies the line of data to be captured by the interface This parameter can be a value of DCMI Line Select Mode

Definition at line 104 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectStart

Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of DCMI Line Select Start

Definition at line 107 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::PCKPolarity

Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of DCMI PIXCK Polarity

Definition at line 77 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::SynchroMode

Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of DCMI Synchronization Mode

Definition at line 74 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

DCMI_CodesInitTypeDef DCMI_InitTypeDef::SyncroCode

Specifies the code of the line/frame start delimiter and the line/frame end delimiter

Definition at line 92 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::VSPolarity

Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of DCMI VSYNC Polarity

Definition at line 80 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __DCMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DCMI_HandleTypeDef Struct Reference
DCMI Exported Types

DCMI handle Structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

DCMI_TypeDef * | Instance
DCMI_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DCMI_StateTypeDef | State
__IO uint32_t | XferCount
__IO uint32_t | XferSize
uint32_t | XferTransferNumber
uint32_t | pBuffPtr
DMA_HandleTypeDef * DMA_Handle
__IO uint32_t | ErrorCode
void(* | LineEventCallback )(struct __DCMI_HandleTypeDef *hdcmi)
void(* | FrameEventCallback )(struct __DCMI_HandleTypeDef *hdcmi)
void(* | VsyncEventCallback )(struct __DCMI_HandleTypeDef *hdcmi)
void(* | ErrorCallback )(struct __DCMI_HandleTypeDef *hdcmi)
void(* | MspInitCallback )(struct __DCMI_HandleTypeDef *hdcmi)
void(* | MspDeInitCallback )(struct __DCMI_HandleTypeDef *hdcmi)

Detailed Description

DCMI handle Structure definition.

Definition at line 115 of file stm32h7xx_hal_dcmi.h.

Field Documentation

DMA_HandleTypeDef* __DCMI_HandleTypeDef::DMA_Handle

Pointer to the DMA handler

Definition at line 136 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), DCMI_DMAXferCplt(), HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), and HAL_DCMI_Stop().

void(* __DCMI_HandleTypeDef::ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Error callback

Definition at line 144 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), HAL_DCMI_Init(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

__IO uint32_t __DCMI_HandleTypeDef::ErrorCode

DCMI Error code

Definition at line 138 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), HAL_DCMI_DeInit(), HAL_DCMI_GetError(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_RegisterCallback(), HAL_DCMI_Start_DMA(), HAL_DCMI_Stop(), HAL_DCMI_Suspend(), and HAL_DCMI_UnRegisterCallback().

void(* __DCMI_HandleTypeDef::FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Frame Event callback

Definition at line 142 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

DCMI_InitTypeDef __DCMI_HandleTypeDef::Init

DCMI parameters

Definition at line 122 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

DCMI_TypeDef* __DCMI_HandleTypeDef::Instance

DCMI Register base address

Definition at line 120 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), HAL_DCMI_ConfigCrop(), HAL_DCMI_DisableCrop(), HAL_DCMI_EnableCrop(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_Resume(), HAL_DCMI_Start_DMA(), HAL_DCMI_Stop(), HAL_DCMI_Suspend(), and HAL_DFSDM_IRQHandler().

void(* __DCMI_HandleTypeDef::LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Line Event callback

Definition at line 141 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

HAL_LockTypeDef __DCMI_HandleTypeDef::Lock

DCMI locking object

Definition at line 124 of file stm32h7xx_hal_dcmi.h.

void(* __DCMI_HandleTypeDef::MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Msp DeInit callback

Definition at line 147 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_DeInit(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

void(* __DCMI_HandleTypeDef::MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Msp Init callback

Definition at line 146 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

uint32_t __DCMI_HandleTypeDef::pBuffPtr

Pointer to DMA output buffer

Definition at line 134 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

__IO HAL_DCMI_StateTypeDef __DCMI_HandleTypeDef::State

DCMI state

Definition at line 126 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), DCMI_DMAXferCplt(), HAL_DCMI_ConfigCrop(), HAL_DCMI_DeInit(), HAL_DCMI_DisableCrop(), HAL_DCMI_EnableCrop(), HAL_DCMI_GetState(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_RegisterCallback(), HAL_DCMI_Resume(), HAL_DCMI_Start_DMA(), HAL_DCMI_Stop(), HAL_DCMI_Suspend(), and HAL_DCMI_UnRegisterCallback().

void(* __DCMI_HandleTypeDef::VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi)

DCMI Vsync Event callback

Definition at line 143 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

__IO uint32_t __DCMI_HandleTypeDef::XferCount

DMA transfer counter

Definition at line 128 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

__IO uint32_t __DCMI_HandleTypeDef::XferSize

DMA transfer size

Definition at line 130 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

uint32_t __DCMI_HandleTypeDef::XferTransferNumber

DMA transfer number

Definition at line 132 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Error Code

Defines
DCMI Error Code
DCMI Exported Constants

Defines

#define | HAL_DCMI_ERROR_NONE (0x00000000U)
#define | HAL_DCMI_ERROR_OVR (0x00000001U)
#define | HAL_DCMI_ERROR_SYNC (0x00000002U)
#define | HAL_DCMI_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DCMI_ERROR_DMA (0x00000040U)
#define | HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Define Documentation

#define HAL_DCMI_ERROR_DMA (0x00000040U)

DMA error

Definition at line 190 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), and HAL_DCMI_Start_DMA().

#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Invalid Callback error

Definition at line 192 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_RegisterCallback(), and HAL_DCMI_UnRegisterCallback().

#define HAL_DCMI_ERROR_NONE (0x00000000U)

No error

Definition at line 186 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_DeInit(), HAL_DCMI_Init(), and HAL_DCMI_Stop().

#define HAL_DCMI_ERROR_OVR (0x00000001U)

Overrun error

Definition at line 187 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_SYNC (0x00000002U)

Synchronization error

Definition at line 188 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 189 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Capture Mode

Defines
DCMI Capture Mode
DCMI Exported Constants

Defines

#define | DCMI_MODE_CONTINUOUS (0x00000000U)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Define Documentation

#define DCMI_MODE_CONTINUOUS (0x00000000U)

The received data are transferred continuously into the destination memory through the DMA

Definition at line 201 of file stm32h7xx_hal_dcmi.h.

#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA

Definition at line 203 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Synchronization Mode

Defines
DCMI Synchronization Mode
DCMI Exported Constants

Defines

#define | DCMI_SYNCHRO_HARDWARE (0x00000000U)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Define Documentation

#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow

Definition at line 214 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define DCMI_SYNCHRO_HARDWARE (0x00000000U)

Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals

Definition at line 212 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI PIXCK Polarity

Defines
DCMI PIXCK Polarity
DCMI Exported Constants

Defines

#define | DCMI_PCKPOLARITY_FALLING (0x00000000U)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Define Documentation

#define DCMI_PCKPOLARITY_FALLING (0x00000000U)

Pixel clock active on Falling edge

Definition at line 224 of file stm32h7xx_hal_dcmi.h.

#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Pixel clock active on Rising edge

Definition at line 225 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI VSYNC Polarity

Defines
DCMI VSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_VSPOLARITY_LOW (0x00000000U)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Define Documentation

#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Vertical synchronization active High

Definition at line 235 of file stm32h7xx_hal_dcmi.h.

#define DCMI_VSPOLARITY_LOW (0x00000000U)

Vertical synchronization active Low

Definition at line 234 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI HSYNC Polarity

Defines
DCMI HSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_HSPOLARITY_LOW (0x00000000U)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Define Documentation

#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Horizontal synchronization active High

Definition at line 245 of file stm32h7xx_hal_dcmi.h.

#define DCMI_HSPOLARITY_LOW (0x00000000U)

Horizontal synchronization active Low

Definition at line 244 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI MODE JPEG

Defines
DCMI MODE JPEG
DCMI Exported Constants

Defines

#define | DCMI_JPEG_DISABLE (0x00000000U)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Define Documentation

#define DCMI_JPEG_DISABLE (0x00000000U)

Mode JPEG Disabled

Definition at line 254 of file stm32h7xx_hal_dcmi.h.

#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Mode JPEG Enabled

Definition at line 255 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Capture Rate

Defines
DCMI Capture Rate
DCMI Exported Constants

Defines

#define | DCMI_CR_ALL_FRAME (0x00000000U)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

Define Documentation

#define DCMI_CR_ALL_FRAME (0x00000000U)

All frames are captured

Definition at line 264 of file stm32h7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)

Every alternate frame captured

Definition at line 265 of file stm32h7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

One frame in 4 frames captured

Definition at line 266 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Extended Data Mode

Defines
DCMI Extended Data Mode
DCMI Exported Constants

Defines

#define | DCMI_EXTEND_DATA_8B (0x00000000U)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Define Documentation

#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)

Interface captures 10-bit data on every pixel clock

Definition at line 276 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)

Interface captures 12-bit data on every pixel clock

Definition at line 277 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Interface captures 14-bit data on every pixel clock

Definition at line 278 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_8B (0x00000000U)

Interface captures 8-bit data on every pixel clock

Definition at line 275 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Window Coordinate

Defines
DCMI Window Coordinate
DCMI Exported Constants

Defines

#define DCMI_WINDOW_COORDINATE (0x3FFFU)

Define Documentation

#define DCMI_WINDOW_COORDINATE (0x3FFFU)

Window coordinate

Definition at line 287 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Window Height

Defines
DCMI Window Height
DCMI Exported Constants

Defines

#define DCMI_WINDOW_HEIGHT (0x1FFFU)

Define Documentation

#define DCMI_WINDOW_HEIGHT (0x1FFFU)

Window Height

Definition at line 296 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI interrupt sources

Defines
DCMI interrupt sources
DCMI Exported Constants

Defines

#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Define Documentation

#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)

Synchronization error interrupt

Definition at line 307 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)

Capture complete interrupt

Definition at line 305 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Line interrupt

Definition at line 309 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)

Overrun interrupt

Definition at line 306 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)

VSYNC interrupt

Definition at line 308 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Flags

Defines
DCMI Flags
DCMI Exported Constants

Defines

#define | DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)
#define | DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)
DCMI RIS register.
#define | DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)
DCMI MIS register.
#define | DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )
#define | DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )
#define | DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)
#define | DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )

Define Documentation

#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )

DCMI Synchronization error masked interrupt status

Definition at line 337 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)

Synchronization error interrupt flag

Definition at line 329 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)

FIFO not empty flag

Definition at line 323 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)

DCMI MIS register.

DCMI Frame capture complete masked interrupt status

Definition at line 335 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)

DCMI RIS register.

Frame capture complete interrupt flag

Definition at line 327 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)

DCMI SR register.

HSYNC pin state (active line / synchronization between lines)

Definition at line 321 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )

DCMI Line masked interrupt status

Definition at line 339 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)

Line interrupt flag

Definition at line 331 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )

DCMI Overrun masked interrupt status

Definition at line 336 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)

Overrun interrupt flag

Definition at line 328 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)

VSYNC pin state (active frame / synchronization between frames)

Definition at line 322 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)

DCMI VSYNC masked interrupt status

Definition at line 338 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)

VSYNC interrupt flag

Definition at line 330 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Byte Select Mode

Defines
DCMI Byte Select Mode
DCMI Exported Constants

Defines

#define | DCMI_BSM_ALL (0x00000000U)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Define Documentation

#define DCMI_BSM_ALL (0x00000000U)

Interface captures all received data

Definition at line 347 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Interface captures two bytes out of four

Definition at line 350 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)

Interface captures one byte out of four

Definition at line 349 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)

Interface captures every other byte from the received data

Definition at line 348 of file stm32h7xx_hal_dcmi.h.

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STM32H7B3xQ HAL User Manual: DCMI Byte Select Start

Defines
DCMI Byte Select Start
DCMI Exported Constants

Defines

#define | DCMI_OEBS_ODD (0x00000000U)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Define Documentation

#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Interface captures second data from the frame/line start, first one being dropped

Definition at line 360 of file stm32h7xx_hal_dcmi.h.

#define DCMI_OEBS_ODD (0x00000000U)

Interface captures first data from the frame/line start, second one being dropped

Definition at line 359 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Line Select Mode

Defines
DCMI Line Select Mode
DCMI Exported Constants

Defines

#define | DCMI_LSM_ALL (0x00000000U)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Define Documentation

#define DCMI_LSM_ALL (0x00000000U)

Interface captures all received lines

Definition at line 369 of file stm32h7xx_hal_dcmi.h.

#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Interface captures one line out of two

Definition at line 370 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Line Select Start

Defines
DCMI Line Select Start
DCMI Exported Constants

Defines

#define | DCMI_OELS_ODD (0x00000000U)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Define Documentation

#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Interface captures second line from the frame start, first one being dropped

Definition at line 380 of file stm32h7xx_hal_dcmi.h.

#define DCMI_OELS_ODD (0x00000000U)

Interface captures first line from the frame start, second one being dropped

Definition at line 379 of file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI Exported Macros

Defines
DCMI Exported Macros
DCMI

Defines

#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flag.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.

Define Documentation

#define __HAL_DCMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the DCMI pending flags.

Parameters:
__HANDLE__ DCMI handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVFRI: Overflow flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
Return values:
None

Definition at line 460 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))

Disable the DCMI.

Parameters:
__HANDLE__ DCMI handle
Return values:
None

Definition at line 421 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop().

#define __HAL_DCMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disable the specified DCMI interrupts.

Parameters:
__HANDLE__ DCMI handle
__INTERRUPT__ specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 488 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)

Enable the DCMI.

Parameters:
__HANDLE__ DCMI handle
Return values:
None

Definition at line 414 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Start_DMA().

#define __HAL_DCMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified DCMI interrupts.

Parameters:
__HANDLE__ DCMI handle
__INTERRUPT__ specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 474 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Init().

#define __HAL_DCMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
 (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))

Get the DCMI pending flag.

Parameters:
__HANDLE__ DCMI handle
__FLAG__ Get the specified flag. This parameter can be one of the following values (no combination allowed)
  • DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
  • DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
  • DCMI_FLAG_FNE: FIFO empty flag
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVRRI: Overrun flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
  • DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
  • DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
  • DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
  • DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
  • DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
Return values:
The state of FLAG.

Definition at line 444 of file stm32h7xx_hal_dcmi.h.

#define __HAL_DCMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))

Check whether the specified DCMI interrupt has occurred or not.

Parameters:
__HANDLE__ DCMI handle
__INTERRUPT__ specifies the DCMI interrupt source to check. This parameter can be one of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
The state of INTERRUPT.

Definition at line 502 of file stm32h7xx_hal_dcmi.h.

#define __HAL_DCMI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                             \
                                                       (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
                                                       (__HANDLE__)->MspInitCallback = NULL;       \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                     } while(0)

Reset DCMI handle state.

Parameters:
__HANDLE__ specifies the DCMI handle.
Return values:
None

Definition at line 400 of file stm32h7xx_hal_dcmi.h.

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STM32H7B3xQ HAL User Manual: DCMI Private Constants

Defines
DCMI Private Constants
DCMI

Defines

#define | DCMI_MIS_INDEX (0x1000)
#define | DCMI_SR_INDEX (0x2000)

Define Documentation

#define DCMI_MIS_INDEX (0x1000)

DCMI MIS register index

Definition at line 581 of file stm32h7xx_hal_dcmi.h.

#define DCMI_SR_INDEX (0x2000)

DCMI SR register index

Definition at line 582 of file stm32h7xx_hal_dcmi.h.

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STM32H7B3xQ HAL User Manual: DCMI Private Macros

Defines
DCMI Private Macros
DCMI

Defines

#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Define Documentation

#define IS_DCMI_BYTE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_BSM_ALL) || \
                                       ((MODE) == DCMI_BSM_OTHER) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_2))

Definition at line 621 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_BYTE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OEBS_ODD) || \
                                            ((POLARITY) == DCMI_OEBS_EVEN))

Definition at line 626 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_CAPTURE_MODE ( MODE )
Value:
(((MODE) == DCMI_MODE_CONTINUOUS) || \
                                   ((MODE) == DCMI_MODE_SNAPSHOT))

Definition at line 590 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Start_DMA().

#define IS_DCMI_CAPTURE_RATE ( RATE )
Value:
(((RATE) == DCMI_CR_ALL_FRAME)         || \
                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))

Definition at line 608 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_EXTENDED_DATA ( DATA )
Value:
(((DATA) == DCMI_EXTEND_DATA_8B)  || \
                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_14B))

Definition at line 612 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_HSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))

Definition at line 602 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_LSM_ALL) || \
                                       ((MODE) == DCMI_LSM_ALTERNATE_2))

Definition at line 629 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OELS_ODD) || \
                                            ((POLARITY) == DCMI_OELS_EVEN))

Definition at line 632 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_MODE_JPEG ( JPEG_MODE )
Value:
(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))

Definition at line 605 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_PCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))

Definition at line 596 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_SYNCHRO ( MODE )
Value:
(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))

Definition at line 593 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_VSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))

Definition at line 599 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_WINDOW_COORDINATE ( COORDINATE ) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)

Definition at line 617 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCrop().

#define IS_DCMI_WINDOW_HEIGHT ( HEIGHT ) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

Definition at line 619 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCrop().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DCMI

Modules | Defines
DCMI
STM32H7xx_HAL_Driver

DCMI HAL module driver. More...

Modules

DCMI Exported Functions
DCMI Exported Types
DCMI Exported Constants
DCMI Exported Macros
DCMI Private Constants
DCMI Private Macros
DCMI Private Functions

Defines

#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */

Detailed Description

DCMI HAL module driver.

Define Documentation

#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */

Definition at line 137 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Private Define

Defines
DFSDM Private Define
DFSDM

Defines

#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_MSB_MASK 0xFFFF0000U
#define | DFSDM_LSB_MASK 0x0000FFFFU
#define | DFSDM_CKAB_TIMEOUT 5000U
#define | DFSDM1_CHANNEL_NUMBER 8U
#define | DFSDM2_CHANNEL_NUMBER 2U

Define Documentation

#define DFSDM1_CHANNEL_NUMBER 8U

Definition at line 289 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM2_CHANNEL_NUMBER 2U

Definition at line 291 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_CKAB_TIMEOUT 5000U

Definition at line 288 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), and HAL_DFSDM_ChannelCkabStart_IT().

#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8

Definition at line 285 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define DFSDM_LSB_MASK 0x0000FFFFU

Definition at line 287 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_GetInjChannelsNbr(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define DFSDM_MSB_MASK 0xFFFF0000U

Definition at line 286 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Private Variables

Variables
DFSDM Private Variables
DFSDM

Variables

static __IO uint32_t | v_dfsdm1ChannelCounter = 0
static
DFSDM_Channel_HandleTypeDef * 		a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}
static __IO uint32_t | v_dfsdm2ChannelCounter = 0
static
DFSDM_Channel_HandleTypeDef * 		a_dfsdm2ChannelHandle [DFSDM2_CHANNEL_NUMBER] = {NULL}

Variable Documentation

DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL} [static]

Definition at line 303 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL} [static]

Definition at line 306 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

__IO uint32_t v_dfsdm1ChannelCounter = 0 [static]

Definition at line 302 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), and HAL_DFSDM_ChannelInit().

__IO uint32_t v_dfsdm2ChannelCounter = 0 [static]

Definition at line 305 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), and HAL_DFSDM_ChannelInit().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Private Functions

Functions
DFSDM Private Functions
DFSDM

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (const DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DFSDM_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3523 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_ERROR_DMA, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, and HAL_DFSDM_FilterErrorCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMAInjectedConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for injected conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3505 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvCpltCallback(), and __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMAInjectedHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for injected conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3487 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvHalfCpltCallback(), and __DFSDM_Filter_HandleTypeDef::InjConvHalfCpltCallback.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMARegularConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for regular conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3469 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvCpltCallback(), and __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMARegularHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for regular conversion.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3451 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvHalfCpltCallback(), and __DFSDM_Filter_HandleTypeDef::RegConvHalfCpltCallback.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static uint32_t DFSDM_GetChannelFromInstance ( const DFSDM_Channel_TypeDef * Instance ) [static]

This function allows to get the channel number from channel instance.

Parameters:
Instance DFSDM channel instance.
Return values:
Channel number.

Definition at line 3567 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

static uint32_t DFSDM_GetInjChannelsNbr ( uint32_t Channels ) [static]

This function allows to get the number of injected channels.

Parameters:
Channels bitfield of injected channels.
Return values:
Number of injected channels.

Definition at line 3544 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_LSB_MASK.

Referenced by HAL_DFSDM_FilterConfigInjChannel().

static void DFSDM_InjConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start injected conversion.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3700 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, __DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::RegularTrigger, and __DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStart_IT().

static void DFSDM_InjConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop injected conversion.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3744 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::RegularTrigger, and __DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), and HAL_DFSDM_FilterInjectedStop_IT().

static void DFSDM_RegConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start regular conversion.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3623 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::RegularTrigger, and __DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStart_IT().

static void DFSDM_RegConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop regular conversion.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3664 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::RegularTrigger, and __DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), and HAL_DFSDM_FilterRegularStop_IT().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Channel initialization and de-initialization functions

Functions
Channel initialization and de-initialization functions
DFSDM Exported Functions

Channel initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_Channel_RegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback)
Register a user DFSDM channel callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Channel_UnRegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM channel callback.

Detailed Description

Channel initialization and de-initialization functions.

  ==============================================================================
        ##### Channel initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM channel.
      (+) De-initialize the DFSDM channel.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | HAL_DFSDM_Channel_CallbackIDTypeDef | CallbackID,
 |  | pDFSDM_Channel_CallbackTypeDef | pCallback
 | ) |  |

Register a user DFSDM channel callback to be used instead of the weak predefined callback.

Parameters:
hdfsdm_channel | DFSDM channel handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
  • HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
  • HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
  • HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 602 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Channel_HandleTypeDef::CkabCallback, HAL_DFSDM_CHANNEL_CKAB_CB_ID, HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID, HAL_DFSDM_CHANNEL_MSPINIT_CB_ID, HAL_DFSDM_CHANNEL_SCD_CB_ID, HAL_DFSDM_CHANNEL_STATE_READY, HAL_DFSDM_CHANNEL_STATE_RESET, __DFSDM_Channel_HandleTypeDef::MspDeInitCallback, __DFSDM_Channel_HandleTypeDef::MspInitCallback, __DFSDM_Channel_HandleTypeDef::ScdCallback, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | HAL_DFSDM_Channel_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user DFSDM channel callback.

DFSDM channel callback is redirected to the weak predefined callback.

Parameters:
hdfsdm_channel DFSDM channel handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
  • HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
  • HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
  • HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 674 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Channel_HandleTypeDef::CkabCallback, HAL_DFSDM_CHANNEL_CKAB_CB_ID, HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID, HAL_DFSDM_CHANNEL_MSPINIT_CB_ID, HAL_DFSDM_CHANNEL_SCD_CB_ID, HAL_DFSDM_CHANNEL_STATE_READY, HAL_DFSDM_CHANNEL_STATE_RESET, HAL_DFSDM_ChannelCkabCallback(), HAL_DFSDM_ChannelMspDeInit(), HAL_DFSDM_ChannelMspInit(), HAL_DFSDM_ChannelScdCallback(), __DFSDM_Channel_HandleTypeDef::MspDeInitCallback, __DFSDM_Channel_HandleTypeDef::MspInitCallback, __DFSDM_Channel_HandleTypeDef::ScdCallback, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status.

Definition at line 486 of file stm32h7xx_hal_dfsdm.c.

References a_dfsdm1ChannelHandle, a_dfsdm2ChannelHandle, assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_RESET, HAL_DFSDM_ChannelMspDeInit(), __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, __DFSDM_Channel_HandleTypeDef::MspDeInitCallback, __DFSDM_Channel_HandleTypeDef::State, v_dfsdm1ChannelCounter, and v_dfsdm2ChannelCounter.

HAL_StatusTypeDef HAL_DFSDM_ChannelInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status.

Definition at line 356 of file stm32h7xx_hal_dfsdm.c.

References a_dfsdm1ChannelHandle, a_dfsdm2ChannelHandle, DFSDM_Channel_OutputClockTypeDef::Activation, assert_param, DFSDM_Channel_InitTypeDef::Awd, __DFSDM_Channel_HandleTypeDef::CkabCallback, DFSDM_Channel_InputTypeDef::DataPacking, DFSDM_GetChannelFromInstance(), DFSDM_Channel_OutputClockTypeDef::Divider, DFSDM_Channel_AwdTypeDef::FilterOrder, HAL_DFSDM_CHANNEL_STATE_READY, HAL_DFSDM_ChannelCkabCallback(), HAL_DFSDM_ChannelMspInit(), HAL_DFSDM_ChannelScdCallback(), __DFSDM_Channel_HandleTypeDef::Init, DFSDM_Channel_InitTypeDef::Input, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, IS_DFSDM_CHANNEL_DATA_PACKING, IS_DFSDM_CHANNEL_FILTER_ORDER, IS_DFSDM_CHANNEL_FILTER_OVS_RATIO, IS_DFSDM_CHANNEL_INPUT, IS_DFSDM_CHANNEL_INPUT_PINS, IS_DFSDM_CHANNEL_OFFSET, IS_DFSDM_CHANNEL_OUTPUT_CLOCK, IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER, IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT, IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE, IS_DFSDM_CHANNEL_SPI_CLOCK, __DFSDM_Channel_HandleTypeDef::MspInitCallback, DFSDM_Channel_InputTypeDef::Multiplexer, DFSDM_Channel_InitTypeDef::Offset, DFSDM_Channel_InitTypeDef::OutputClock, DFSDM_Channel_AwdTypeDef::Oversampling, DFSDM_Channel_InputTypeDef::Pins, DFSDM_Channel_InitTypeDef::RightBitShift, __DFSDM_Channel_HandleTypeDef::ScdCallback, DFSDM_Channel_OutputClockTypeDef::Selection, DFSDM_Channel_InitTypeDef::SerialInterface, DFSDM_Channel_SerialInterfaceTypeDef::SpiClock, __DFSDM_Channel_HandleTypeDef::State, DFSDM_Channel_SerialInterfaceTypeDef::Type, v_dfsdm1ChannelCounter, and v_dfsdm2ChannelCounter.

void HAL_DFSDM_ChannelMspDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
None

Definition at line 578 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Channel_UnRegisterCallback(), and HAL_DFSDM_ChannelDeInit().

void HAL_DFSDM_ChannelMspInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
None

Definition at line 563 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Channel_UnRegisterCallback(), and HAL_DFSDM_ChannelInit().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Channel operation functions

Functions
Channel operation functions
DFSDM Exported Functions

Channel operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.

Detailed Description

Channel operation functions.

  ==============================================================================
                   ##### Channel operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Manage clock absence detector feature.
      (+) Manage short circuit detector feature.
      (+) Get analog watchdog value.
      (+) Modify offset value.

Function Documentation

void HAL_DFSDM_ChannelCkabCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Clock absence detection callback.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
None

Definition at line 1005 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in polling mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 755 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in interrupt mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 936 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in polling mode.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 886 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 1021 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

int16_t HAL_DFSDM_ChannelGetAwdValue ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get channel analog watchdog value.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
Channel analog watchdog value.

Definition at line 1345 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Channel_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | int32_t | Offset
 | ) |  |

This function allows to modify channel offset value.

Parameters:
hdfsdm_channel | DFSDM channel handle.
Offset | DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
Return values:
HAL status.

Definition at line 1357 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_OFFSET, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the clock absence detection.

Parameters:
hdfsdm_channel | DFSDM channel handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 822 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the short circuit detection.

Parameters:
hdfsdm_channel | DFSDM channel handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1112 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

void HAL_DFSDM_ChannelScdCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Short circuit detection callback.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in polling mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | DFSDM channel handle.
Threshold | Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 1075 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in interrupt mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | DFSDM channel handle.
Threshold | Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 1227 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in polling mode.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 1176 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
HAL status

Definition at line 1296 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM1_CHANNEL_INSTANCE, and __DFSDM_Channel_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Channel state function

Functions
Channel state function
DFSDM Exported Functions

Channel state function. More...

Functions

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.

Detailed Description

Channel state function.

  ==============================================================================
                   ##### Channel state function #####
  ==============================================================================
    [..]  This section provides function allowing to:
      (+) Get channel handle state.

Function Documentation

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get the current DFSDM channel handle state.

Parameters:
hdfsdm_channel DFSDM channel handle.
Return values:
DFSDM channel state.

Definition at line 1404 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Channel_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Filter initialization and de-initialization functions

Functions
Filter initialization and de-initialization functions
DFSDM Exported Functions

Filter initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback)
Register a user DFSDM filter callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM filter callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback)
Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Unregister a user DFSDM filter analog watchdog callback.

Detailed Description

Filter initialization and de-initialization functions.

  ==============================================================================
        ##### Filter initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM filter.
      (+) De-initialize the DFSDM filter.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | pDFSDM_Filter_AwdCallbackTypeDef | pCallback
 | ) |  |

Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callback.

Parameters:
hdfsdm_filter | DFSDM filter handle.
pCallback | pointer to the DFSDM filter analog watchdog callback function.
Return values:
HAL status.

Definition at line 1819 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Filter_HandleTypeDef::AwdCallback, DFSDM_FILTER_ERROR_INVALID_CALLBACK, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_READY, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | HAL_DFSDM_Filter_CallbackIDTypeDef | CallbackID,
 |  | pDFSDM_Filter_CallbackTypeDef | pCallback
 | ) |  |

Register a user DFSDM filter callback to be used instead of the weak predefined callback.

Parameters:
hdfsdm_filter | DFSDM filter handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
  • HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
  • HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
  • HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
  • HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
  • HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
  • HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 1654 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_ERROR_INVALID_CALLBACK, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_ERROR_CB_ID, HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID, HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID, HAL_DFSDM_FILTER_MSPDEINIT_CB_ID, HAL_DFSDM_FILTER_MSPINIT_CB_ID, HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID, HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback, __DFSDM_Filter_HandleTypeDef::InjConvHalfCpltCallback, __DFSDM_Filter_HandleTypeDef::MspDeInitCallback, __DFSDM_Filter_HandleTypeDef::MspInitCallback, __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback, __DFSDM_Filter_HandleTypeDef::RegConvHalfCpltCallback, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Unregister a user DFSDM filter analog watchdog callback.

DFSDM filter AWD callback is redirected to the weak predefined callback.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status.

Definition at line 1854 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Filter_HandleTypeDef::AwdCallback, DFSDM_FILTER_ERROR_INVALID_CALLBACK, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FilterAwdCallback(), and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | HAL_DFSDM_Filter_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user DFSDM filter callback.

DFSDM filter callback is redirected to the weak predefined callback.

Parameters:
hdfsdm_filter DFSDM filter handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
  • HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
  • HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
  • HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
  • HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
  • HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
  • HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 1746 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_ERROR_INVALID_CALLBACK, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_ERROR_CB_ID, HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID, HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID, HAL_DFSDM_FILTER_MSPDEINIT_CB_ID, HAL_DFSDM_FILTER_MSPINIT_CB_ID, HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID, HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_RESET, HAL_DFSDM_FilterErrorCallback(), HAL_DFSDM_FilterInjConvCpltCallback(), HAL_DFSDM_FilterInjConvHalfCpltCallback(), HAL_DFSDM_FilterMspDeInit(), HAL_DFSDM_FilterMspInit(), HAL_DFSDM_FilterRegConvCpltCallback(), HAL_DFSDM_FilterRegConvHalfCpltCallback(), __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback, __DFSDM_Filter_HandleTypeDef::InjConvHalfCpltCallback, __DFSDM_Filter_HandleTypeDef::MspDeInitCallback, __DFSDM_Filter_HandleTypeDef::MspInitCallback, __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback, __DFSDM_Filter_HandleTypeDef::RegConvHalfCpltCallback, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status.

Definition at line 1576 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_RESET, HAL_DFSDM_FilterMspDeInit(), __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::MspDeInitCallback, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status.

Definition at line 1434 of file stm32h7xx_hal_dfsdm.c.

References assert_param, __DFSDM_Filter_HandleTypeDef::AwdCallback, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_NONE, DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, DFSDM_Filter_RegularParamTypeDef::DmaMode, DFSDM_Filter_InjectedParamTypeDef::DmaMode, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, DFSDM_Filter_InjectedParamTypeDef::ExtTrigger, DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge, __DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, DFSDM_Filter_RegularParamTypeDef::FastMode, DFSDM_Filter_InitTypeDef::FilterParam, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FilterAwdCallback(), HAL_DFSDM_FilterErrorCallback(), HAL_DFSDM_FilterInjConvCpltCallback(), HAL_DFSDM_FilterInjConvHalfCpltCallback(), HAL_DFSDM_FilterMspInit(), HAL_DFSDM_FilterRegConvCpltCallback(), HAL_DFSDM_FilterRegConvHalfCpltCallback(), __DFSDM_Filter_HandleTypeDef::Init, __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback, __DFSDM_Filter_HandleTypeDef::InjConvHalfCpltCallback, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_InitTypeDef::InjectedParam, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_FilterParamTypeDef::IntOversampling, IS_DFSDM1_FILTER_INSTANCE, IS_DFSDM_FILTER_EXT_TRIG, IS_DFSDM_FILTER_EXT_TRIG_EDGE, IS_DFSDM_FILTER_INJ_TRIGGER, IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO, IS_DFSDM_FILTER_OVS_RATIO, IS_DFSDM_FILTER_REG_TRIGGER, IS_DFSDM_FILTER_SINC_ORDER, __DFSDM_Filter_HandleTypeDef::MspInitCallback, DFSDM_Filter_FilterParamTypeDef::Oversampling, __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback, __DFSDM_Filter_HandleTypeDef::RegConvHalfCpltCallback, __DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_InitTypeDef::RegularParam, __DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_InjectedParamTypeDef::ScanMode, DFSDM_Filter_FilterParamTypeDef::SincOrder, __DFSDM_Filter_HandleTypeDef::State, DFSDM_Filter_RegularParamTypeDef::Trigger, and DFSDM_Filter_InjectedParamTypeDef::Trigger.

void HAL_DFSDM_FilterMspDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 1627 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterDeInit().

void HAL_DFSDM_FilterMspInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 1612 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Filter control functions

Functions
Filter control functions
DFSDM Exported Functions

Filter control functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.

Detailed Description

Filter control functions.

  ==============================================================================
                    ##### Filter control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Select channel and enable/disable continuous mode for regular conversion.
      (+) Select channels for injected conversion.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to select channels for injected conversion.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Channels for injected conversion. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 1946 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetInjChannelsNbr(), DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | ContinuousMode
 | ) |  |

This function allows to select channel and to enable/disable continuous mode for regular conversion.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Channel for regular conversion. This parameter can be a value of DFSDM Channel Selection.
ContinuousMode | Enable/disable continuous mode for regular conversion. This parameter can be a value of DFSDM Continuous Mode.
Return values:
HAL status

Definition at line 1901 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_ON, DFSDM_FLTCR1_MSB_RCH_OFFSET, DFSDM_MSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_CONTINUOUS_MODE, IS_DFSDM_REGULAR_CHANNEL, __DFSDM_Filter_HandleTypeDef::RegularContMode, and __DFSDM_Filter_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Filter operation functions

Functions
Filter operation functions
DFSDM Exported Functions

Filter operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.

Detailed Description

Filter operation functions.

  ==============================================================================
                    ##### Filter operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular/injected channel.
      (+) Poll for the end of regular/injected conversion.
      (+) Stop conversion of regular/injected channel.
      (+) Start conversion of regular/injected channel and enable interrupt.
      (+) Call the callback functions at the end of regular/injected conversions.
      (+) Stop conversion of regular/injected channel and disable interrupt.
      (+) Start conversion of regular/injected channel and enable DMA transfer.
      (+) Stop conversion of regular/injected channel and disable DMA transfer.
      (+) Start analog watchdog and enable interrupt.
      (+) Call the callback function when analog watchdog occurs.
      (+) Stop analog watchdog and disable interrupt.
      (+) Start extreme detector.
      (+) Stop extreme detector.
      (+) Get result of regular channel conversion.
      (+) Get result of injected channel conversion.
      (+) Get extreme detector maximum and minimum values.
      (+) Get conversion time.
      (+) Handle DFSDM interrupt request.

Function Documentation

void HAL_DFSDM_FilterAwdCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | Threshold
 | ) |  |

Filter analog watchdog callback.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Corresponding channel.
Threshold | Low or high threshold has been reached.
Return values:
None

Definition at line 3365 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_Filter_UnRegisterAwdCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | DFSDM_Filter_AwdParamTypeDef * | awdParam
 | ) |  |

This function allows to start filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter | DFSDM filter handle.
awdParam | DFSDM filter analog watchdog parameters.
Return values:
HAL status

Definition at line 2843 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_Filter_AwdParamTypeDef::Channel, DFSDM_Filter_AwdParamTypeDef::DataSource, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_AwdParamTypeDef::HighBreakSignal, DFSDM_Filter_AwdParamTypeDef::HighThreshold, __DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_FILTER_AWD_DATA_SOURCE, IS_DFSDM_FILTER_AWD_THRESHOLD, IS_DFSDM_INJECTED_CHANNEL, DFSDM_Filter_AwdParamTypeDef::LowBreakSignal, DFSDM_Filter_AwdParamTypeDef::LowThreshold, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2892 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterErrorCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Error callback.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3383 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAError(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterExdStart | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to start extreme detector feature.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Channels where extreme detector is enabled. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 2932 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterExdStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop extreme detector feature.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2963 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

uint32_t HAL_DFSDM_FilterGetConvTimeValue ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get conversion time value.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
Conversion time value
Note:
To get time in second, this value has to be divided by DFSDM clock frequency.

Definition at line 3062 of file stm32h7xx_hal_dfsdm.c.

References assert_param, and __DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMaxValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector maximum value.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Corresponding channel.
Return values:
Extreme detector maximum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 3001 of file stm32h7xx_hal_dfsdm.c.

References assert_param, and __DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMinValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector minimum value.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Corresponding channel.
Return values:
Extreme detector minimum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 3032 of file stm32h7xx_hal_dfsdm.c.

References assert_param, and __DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetInjectedValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get injected conversion value.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Corresponding channel of injected conversion.
Return values:
Injected conversion value

Definition at line 2813 of file stm32h7xx_hal_dfsdm.c.

References assert_param, and __DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetRegularValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get regular conversion value.

Parameters:
hdfsdm_filter | DFSDM filter handle.
Channel | Corresponding channel of regular conversion.
Return values:
Regular conversion value

Definition at line 2396 of file stm32h7xx_hal_dfsdm.c.

References assert_param, and __DFSDM_Filter_HandleTypeDef::Instance.

void HAL_DFSDM_FilterInjConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Injected conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetInjectedValue.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3333 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedConvCplt(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterInjConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half injected conversion complete callback.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3348 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedHalfConvCplt(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of injected conversion.
Parameters:
hdfsdm_filter | DFSDM filter handle.
pData | The destination buffer address.
Length | The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2705 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), __DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2427 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed injected conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | DFSDM filter handle.
pData | The destination buffer address.
Length | The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2630 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), __DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2561 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in polling mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2531 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in DMA mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2774 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), __DFSDM_Filter_HandleTypeDef::hdmaInj, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in interrupt mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2592 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of injected conversion.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter | DFSDM filter handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 2456 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_SW_TRIGGER, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of regular conversion.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter | DFSDM filter handle.
Timeout | Timeout value in milliseconds.
Return values:
HAL status

Definition at line 2045 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), __DFSDM_Filter_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::RegularContMode, __DFSDM_Filter_HandleTypeDef::RegularTrigger, and __DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterRegConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Regular conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetRegularValue.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3301 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularConvCplt(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterRegConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half regular conversion complete callback.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3316 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularHalfConvCplt(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of regular conversion.
Parameters:
hdfsdm_filter | DFSDM filter handle.
pData | The destination buffer address.
Length | The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2286 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), __DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, __DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DFSDM_Filter_HandleTypeDef::RegularContMode, __DFSDM_Filter_HandleTypeDef::RegularTrigger, __DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2016 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed regular conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | DFSDM filter handle.
pData | The destination buffer address.
Length | The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2209 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), __DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, __DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DFSDM_Filter_HandleTypeDef::RegularContMode, __DFSDM_Filter_HandleTypeDef::RegularTrigger, __DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2140 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in polling mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2110 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in DMA mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2357 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), __DFSDM_Filter_HandleTypeDef::hdmaReg, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in interrupt mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
HAL status

Definition at line 2171 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, __DFSDM_Filter_HandleTypeDef::Instance, and __DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_IRQHandler ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function handles the DFSDM interrupts.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
None

Definition at line 3085 of file stm32h7xx_hal_dfsdm.c.

References a_dfsdm1ChannelHandle, a_dfsdm2ChannelHandle, __DFSDM_Filter_HandleTypeDef::AwdCallback, __DFSDM_Channel_HandleTypeDef::CkabCallback, DFSDM1_CHANNEL_NUMBER, DFSDM2_CHANNEL_NUMBER, DFSDM_AWD_HIGH_THRESHOLD, DFSDM_AWD_LOW_THRESHOLD, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, __DFSDM_Filter_HandleTypeDef::ErrorCallback, __DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_ChannelCkabCallback(), HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FilterAwdCallback(), HAL_DFSDM_FilterErrorCallback(), HAL_DFSDM_FilterInjConvCpltCallback(), HAL_DFSDM_FilterRegConvCpltCallback(), __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback, __DFSDM_Filter_HandleTypeDef::InjConvRemaining, __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, __DFSDM_Filter_HandleTypeDef::InjectedScanMode, __DFSDM_Filter_HandleTypeDef::InjectedTrigger, __DCMI_HandleTypeDef::Instance, __DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM1_FILTER_INSTANCE, __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback, __DFSDM_Filter_HandleTypeDef::RegularContMode, __DFSDM_Filter_HandleTypeDef::RegularTrigger, __DFSDM_Channel_HandleTypeDef::ScdCallback, and __DFSDM_Filter_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:13 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Filter state functions

Functions
Filter state functions
DFSDM Exported Functions

Filter state functions. More...

Functions

HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Filter state functions.

  ==============================================================================
                     ##### Filter state functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the DFSDM filter state.
      (+) Get the DFSDM filter error.

Function Documentation

uint32_t HAL_DFSDM_FilterGetError ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter error.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
DFSDM filter error code.

Definition at line 3427 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Filter_HandleTypeDef::ErrorCode.

HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter handle state.

Parameters:
hdfsdm_filter DFSDM filter handle.
Return values:
DFSDM filter state.

Definition at line 3416 of file stm32h7xx_hal_dfsdm.c.

References __DFSDM_Filter_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Exported Types

Data Structures | Typedefs | Enumerations
DFSDM Exported Types
DFSDM

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | __DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | __DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Typedefs

typedef struct
__DFSDM_Channel_HandleTypeDef 		DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition.
typedef void(* | pDFSDM_Channel_CallbackTypeDef )(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
DFSDM channel callback pointer definition.
typedef struct
__DFSDM_Filter_HandleTypeDef 		DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition.
typedef void(* | pDFSDM_Filter_CallbackTypeDef )(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
DFSDM filter callback pointer definition.
typedef void(* | pDFSDM_Filter_AwdCallbackTypeDef )(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU }
HAL DFSDM Channel states definition. More...
enum | HAL_DFSDM_Channel_CallbackIDTypeDef { HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U }
DFSDM channel callback ID enumeration definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, HAL_DFSDM_FILTER_STATE_READY = 0x01U, HAL_DFSDM_FILTER_STATE_REG = 0x02U, HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
}
HAL DFSDM Filter states definition. More...
enum HAL_DFSDM_Filter_CallbackIDTypeDef {
HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U,
HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U
}
DFSDM filter callback ID enumeration definition. More...

Typedef Documentation

typedef struct __DFSDM_Channel_HandleTypeDef DFSDM_Channel_HandleTypeDef

DFSDM channel handle structure definition.

typedef struct __DFSDM_Filter_HandleTypeDef DFSDM_Filter_HandleTypeDef

DFSDM filter handle structure definition.

typedef void(* pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

DFSDM channel callback pointer definition.

Definition at line 151 of file stm32h7xx_hal_dfsdm.h.

typedef void(* pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)

Definition at line 289 of file stm32h7xx_hal_dfsdm.h.

typedef void(* pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter callback pointer definition.

Definition at line 288 of file stm32h7xx_hal_dfsdm.h.

Enumeration Type Documentation

enum HAL_DFSDM_Channel_CallbackIDTypeDef

DFSDM channel callback ID enumeration definition.

Enumerator:
HAL_DFSDM_CHANNEL_CKAB_CB_ID

DFSDM channel clock absence detection callback ID

HAL_DFSDM_CHANNEL_SCD_CB_ID

DFSDM channel short circuit detection callback ID

HAL_DFSDM_CHANNEL_MSPINIT_CB_ID

DFSDM channel MSP init callback ID

HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID

DFSDM channel MSP de-init callback ID

Definition at line 140 of file stm32h7xx_hal_dfsdm.h.

enum HAL_DFSDM_Channel_StateTypeDef

HAL DFSDM Channel states definition.

Enumerator:
HAL_DFSDM_CHANNEL_STATE_RESET

DFSDM channel not initialized

HAL_DFSDM_CHANNEL_STATE_READY

DFSDM channel initialized and ready for use

HAL_DFSDM_CHANNEL_STATE_ERROR

DFSDM channel state error

Definition at line 47 of file stm32h7xx_hal_dfsdm.h.

enum HAL_DFSDM_Filter_CallbackIDTypeDef

DFSDM filter callback ID enumeration definition.

Enumerator:
HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID

DFSDM filter regular conversion complete callback ID

HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID

DFSDM filter half regular conversion complete callback ID

HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID

DFSDM filter injected conversion complete callback ID

HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID

DFSDM filter half injected conversion complete callback ID

HAL_DFSDM_FILTER_ERROR_CB_ID

DFSDM filter error callback ID

HAL_DFSDM_FILTER_MSPINIT_CB_ID

DFSDM filter MSP init callback ID

HAL_DFSDM_FILTER_MSPDEINIT_CB_ID

DFSDM filter MSP de-init callback ID

Definition at line 274 of file stm32h7xx_hal_dfsdm.h.

enum HAL_DFSDM_Filter_StateTypeDef

HAL DFSDM Filter states definition.

Enumerator:
HAL_DFSDM_FILTER_STATE_RESET

DFSDM filter not initialized

HAL_DFSDM_FILTER_STATE_READY

DFSDM filter initialized and ready for use

HAL_DFSDM_FILTER_STATE_REG

DFSDM filter regular conversion in progress

HAL_DFSDM_FILTER_STATE_INJ

DFSDM filter injected conversion in progress

HAL_DFSDM_FILTER_STATE_REG_INJ

DFSDM filter regular and injected conversions in progress

HAL_DFSDM_FILTER_STATE_ERROR

DFSDM filter state error

Definition at line 157 of file stm32h7xx_hal_dfsdm.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Channel_OutputClockTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_OutputClockTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel output clock structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

FunctionalState | Activation
uint32_t | Selection
uint32_t | Divider

Detailed Description

DFSDM channel output clock structure definition.

Definition at line 57 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Channel_OutputClockTypeDef::Activation

Output clock enable/disable

Definition at line 59 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Divider

Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256

Definition at line 62 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Selection

Output clock is system clock or audio clock. This parameter can be a value of DFSDM channel output clock selection

Definition at line 60 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Channel_InputTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InputTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel input structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Multiplexer
uint32_t | DataPacking
uint32_t | Pins

Detailed Description

DFSDM channel input structure definition.

Definition at line 69 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_InputTypeDef::DataPacking

Standard, interleaved or dual mode for internal register. This parameter can be a value of DFSDM channel input data packing

Definition at line 73 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Multiplexer

Input is external serial inputs, internal register or ADC output. This parameter can be a value of DFSDM channel input multiplexer

Definition at line 71 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Pins

Input pins are taken from same or following channel. This parameter can be a value of DFSDM channel input pins

Definition at line 75 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Channel_SerialInterfaceTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_SerialInterfaceTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel serial interface structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Type
uint32_t | SpiClock

Detailed Description

DFSDM channel serial interface structure definition.

Definition at line 82 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::SpiClock

SPI clock select (external or internal with different sampling point). This parameter can be a value of DFSDM channel SPI clock selection

Definition at line 86 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::Type

SPI or Manchester modes. This parameter can be a value of DFSDM channel serial interface type

Definition at line 84 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Channel_AwdTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_AwdTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel analog watchdog structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | FilterOrder
uint32_t | Oversampling

Detailed Description

DFSDM channel analog watchdog structure definition.

Definition at line 93 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_AwdTypeDef::FilterOrder

Analog watchdog Sinc filter order. This parameter can be a value of DFSDM channel analog watchdog filter order

Definition at line 95 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_AwdTypeDef::Oversampling

Analog watchdog filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 97 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Channel_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel init structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_OutputClockTypeDef OutputClock
DFSDM_Channel_InputTypeDef Input
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
DFSDM_Channel_AwdTypeDef Awd
int32_t | Offset
uint32_t | RightBitShift

Detailed Description

DFSDM channel init structure definition.

Definition at line 104 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

DFSDM_Channel_AwdTypeDef DFSDM_Channel_InitTypeDef::Awd

DFSDM channel analog watchdog parameters

Definition at line 109 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_InputTypeDef DFSDM_Channel_InitTypeDef::Input

DFSDM channel input parameters

Definition at line 107 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

int32_t DFSDM_Channel_InitTypeDef::Offset

DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 110 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_OutputClockTypeDef DFSDM_Channel_InitTypeDef::OutputClock

DFSDM channel output clock parameters

Definition at line 106 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InitTypeDef::RightBitShift

DFSDM channel right bit shift. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 112 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_SerialInterfaceTypeDef DFSDM_Channel_InitTypeDef::SerialInterface

DFSDM channel serial interface parameters

Definition at line 108 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __DFSDM_Channel_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DFSDM_Channel_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel handle structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_TypeDef * | Instance
DFSDM_Channel_InitTypeDef Init
HAL_DFSDM_Channel_StateTypeDef State
void(* | CkabCallback )(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
void(* | ScdCallback )(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
void(* | MspInitCallback )(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
void(* | MspDeInitCallback )(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

Detailed Description

DFSDM channel handle structure definition.

Definition at line 120 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

void(* __DFSDM_Channel_HandleTypeDef::CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

DFSDM channel clock absence detection callback

Definition at line 129 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

DFSDM_Channel_InitTypeDef __DFSDM_Channel_HandleTypeDef::Init

DFSDM channel init parameters

Definition at line 126 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_TypeDef* __DFSDM_Channel_HandleTypeDef::Instance

DFSDM channel instance

Definition at line 125 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFDSMEx_ChannelGetPulsesSkipping(), HAL_DFDSMEx_ChannelSetPulsesSkipping(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetAwdValue(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

void(* __DFSDM_Channel_HandleTypeDef::MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

DFSDM channel MSP de-init callback

Definition at line 132 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), and HAL_DFSDM_ChannelDeInit().

void(* __DFSDM_Channel_HandleTypeDef::MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

DFSDM channel MSP init callback

Definition at line 131 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), and HAL_DFSDM_ChannelInit().

void(* __DFSDM_Channel_HandleTypeDef::ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel)

DFSDM channel short circuit detection callback

Definition at line 130 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_ChannelInit(), and HAL_DFSDM_IRQHandler().

HAL_DFSDM_Channel_StateTypeDef __DFSDM_Channel_HandleTypeDef::State

DFSDM channel state

Definition at line 127 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFDSMEx_ChannelGetPulsesSkipping(), HAL_DFDSMEx_ChannelSetPulsesSkipping(), HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetState(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Filter_RegularParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_RegularParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter regular conversion parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | FastMode
FunctionalState | DmaMode

Detailed Description

DFSDM filter regular conversion parameters structure definition.

Definition at line 170 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_RegularParamTypeDef::DmaMode

Enable/disable DMA for regular conversion

Definition at line 175 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_RegularParamTypeDef::FastMode

Enable/disable fast mode for regular conversion

Definition at line 174 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_RegularParamTypeDef::Trigger

Trigger used to start regular conversion: software or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 172 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Filter_InjectedParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InjectedParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter injected conversion parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | ScanMode
FunctionalState | DmaMode
uint32_t | ExtTrigger
uint32_t | ExtTriggerEdge

Detailed Description

DFSDM filter injected conversion parameters structure definition.

Definition at line 181 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_InjectedParamTypeDef::DmaMode

Enable/disable DMA for injected conversion

Definition at line 186 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTrigger

External trigger. This parameter can be a value of DFSDM filter external trigger

Definition at line 187 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge

External trigger edge: rising, falling or both. This parameter can be a value of DFSDM filter external trigger edge

Definition at line 189 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_InjectedParamTypeDef::ScanMode

Enable/disable scanning mode for injected conversion

Definition at line 185 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::Trigger

Trigger used to start injected conversion: software, external or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 183 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Filter_FilterParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_FilterParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | SincOrder
uint32_t | Oversampling
uint32_t | IntOversampling

Detailed Description

DFSDM filter parameters structure definition.

Definition at line 196 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_FilterParamTypeDef::IntOversampling

Integrator oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 256

Definition at line 202 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::Oversampling

Filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 200 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::SincOrder

Sinc filter order. This parameter can be a value of DFSDM filter sinc order

Definition at line 198 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Filter_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter init structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_RegularParamTypeDef RegularParam
DFSDM_Filter_InjectedParamTypeDef InjectedParam
DFSDM_Filter_FilterParamTypeDef FilterParam

Detailed Description

DFSDM filter init structure definition.

Definition at line 209 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

DFSDM_Filter_FilterParamTypeDef DFSDM_Filter_InitTypeDef::FilterParam

DFSDM filter parameters

Definition at line 213 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_InjectedParamTypeDef DFSDM_Filter_InitTypeDef::InjectedParam

DFSDM injected conversion parameters

Definition at line 212 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_RegularParamTypeDef DFSDM_Filter_InitTypeDef::RegularParam

DFSDM regular conversion parameters

Definition at line 211 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __DFSDM_Filter_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DFSDM_Filter_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter handle structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_TypeDef * | Instance
DFSDM_Filter_InitTypeDef Init
DMA_HandleTypeDef * hdmaReg
DMA_HandleTypeDef * hdmaInj
uint32_t | RegularContMode
uint32_t | RegularTrigger
uint32_t | InjectedTrigger
uint32_t | ExtTriggerEdge
FunctionalState | InjectedScanMode
uint32_t | InjectedChannelsNbr
uint32_t | InjConvRemaining
HAL_DFSDM_Filter_StateTypeDef State
uint32_t | ErrorCode
void(* | AwdCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
void(* | RegConvCpltCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | RegConvHalfCpltCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | InjConvCpltCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | InjConvHalfCpltCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | ErrorCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | MspInitCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
void(* | MspDeInitCallback )(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

Detailed Description

DFSDM filter handle structure definition.

Definition at line 220 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

void(* __DFSDM_Filter_HandleTypeDef::AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)

DFSDM filter analog watchdog callback

Definition at line 239 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Filter_RegisterAwdCallback(), HAL_DFSDM_Filter_UnRegisterAwdCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

void(* __DFSDM_Filter_HandleTypeDef::ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter error callback

Definition at line 245 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

uint32_t __DFSDM_Filter_HandleTypeDef::ErrorCode

DFSDM filter error code

Definition at line 237 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError(), HAL_DFSDM_Filter_RegisterAwdCallback(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterAwdCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterGetError(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

uint32_t __DFSDM_Filter_HandleTypeDef::ExtTriggerEdge

Rising, falling or both edges selected

Definition at line 232 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), and HAL_DFSDM_FilterInit().

DMA_HandleTypeDef* __DFSDM_Filter_HandleTypeDef::hdmaInj

Pointer on DMA handler for injected conversions

Definition at line 228 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStop_DMA().

DMA_HandleTypeDef* __DFSDM_Filter_HandleTypeDef::hdmaReg

Pointer on DMA handler for regular conversions

Definition at line 227 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStop_DMA().

DFSDM_Filter_InitTypeDef __DFSDM_Filter_HandleTypeDef::Init

DFSDM filter init parameters

Definition at line 226 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

void(* __DFSDM_Filter_HandleTypeDef::InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter injected conversion complete callback

Definition at line 243 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAInjectedConvCplt(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

void(* __DFSDM_Filter_HandleTypeDef::InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter half injected conversion complete callback

Definition at line 244 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAInjectedHalfConvCplt(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

uint32_t __DFSDM_Filter_HandleTypeDef::InjConvRemaining

Injected conversions remaining

Definition at line 235 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t __DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr

Number of channels in injected sequence

Definition at line 234 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

FunctionalState __DFSDM_Filter_HandleTypeDef::InjectedScanMode

Injected scanning mode

Definition at line 233 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t __DFSDM_Filter_HandleTypeDef::InjectedTrigger

Trigger used for injected conversion

Definition at line 231 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

DFSDM_Filter_TypeDef* __DFSDM_Filter_HandleTypeDef::Instance

DFSDM filter instance

Definition at line 225 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

void(* __DFSDM_Filter_HandleTypeDef::MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter MSP de-init callback

Definition at line 247 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterDeInit().

void(* __DFSDM_Filter_HandleTypeDef::MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter MSP init callback

Definition at line 246 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

void(* __DFSDM_Filter_HandleTypeDef::RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter regular conversion complete callback

Definition at line 241 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMARegularConvCplt(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

void(* __DFSDM_Filter_HandleTypeDef::RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter)

DFSDM filter half regular conversion complete callback

Definition at line 242 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMARegularHalfConvCplt(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), and HAL_DFSDM_FilterInit().

uint32_t __DFSDM_Filter_HandleTypeDef::RegularContMode

Regular conversion continuous mode

Definition at line 229 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

uint32_t __DFSDM_Filter_HandleTypeDef::RegularTrigger

Trigger used for regular conversion

Definition at line 230 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

HAL_DFSDM_Filter_StateTypeDef __DFSDM_Filter_HandleTypeDef::State

DFSDM filter state

Definition at line 236 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_Filter_RegisterAwdCallback(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterAwdCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetState(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM_Filter_AwdParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_AwdParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter analog watchdog parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | DataSource
uint32_t | Channel
int32_t | HighThreshold
int32_t | LowThreshold
uint32_t | HighBreakSignal
uint32_t | LowBreakSignal

Detailed Description

DFSDM filter analog watchdog parameters structure definition.

Definition at line 254 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_AwdParamTypeDef::Channel

Analog watchdog channel selection. This parameter can be a values combination of DFSDM Channel Selection

Definition at line 258 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::DataSource

Values from digital filter or from channel watchdog filter. This parameter can be a value of DFSDM filter analog watchdog data source

Definition at line 256 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::HighBreakSignal

Break signal assigned to analog watchdog high threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 264 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::HighThreshold

High threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 260 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::LowBreakSignal

Break signal assigned to analog watchdog low threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 266 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::LowThreshold

Low threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 262 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM channel output clock selection

Defines
DFSDM channel output clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Define Documentation

#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Source for ouput clock is audio clock

Definition at line 306 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U

Source for ouput clock is system clock

Definition at line 305 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel input multiplexer

Defines
DFSDM channel input multiplexer
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U
#define | DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Define Documentation

#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0

Data are taken from ADC output

Definition at line 315 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U

Data are taken from external inputs

Definition at line 314 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Data are taken from internal register

Definition at line 316 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel input data packing

Defines
DFSDM channel input data packing
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_STANDARD_MODE 0x00000000U
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Define Documentation

#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Dual data packing mode

Definition at line 326 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0

Interleaved data packing mode

Definition at line 325 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U

Standard data packing mode

Definition at line 324 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel input pins

Defines
DFSDM channel input pins
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Define Documentation

#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Input from pins on following channel

Definition at line 335 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U

Input from pins on same channel

Definition at line 334 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel serial interface type

Defines
DFSDM channel serial interface type
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_RISING 0x00000000U
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Define Documentation

#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Manchester with falling edge

Definition at line 346 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1

Manchester with rising edge

Definition at line 345 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0

SPI with falling edge

Definition at line 344 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_RISING 0x00000000U

SPI with rising edge

Definition at line 343 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel SPI clock selection

Defines
DFSDM channel SPI clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Define Documentation

#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U

External SPI clock

Definition at line 354 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0

Internal SPI clock

Definition at line 355 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1

Internal SPI clock divided by 2, falling edge

Definition at line 356 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Internal SPI clock divided by 2, rising edge

Definition at line 357 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM channel analog watchdog filter order

Defines
DFSDM channel analog watchdog filter order
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Define Documentation

#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U

FastSinc filter type

Definition at line 365 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0

Sinc 1 filter type

Definition at line 366 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1

Sinc 2 filter type

Definition at line 367 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Sinc 3 filter type

Definition at line 368 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM filter conversion trigger

Defines
DFSDM filter conversion trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_SW_TRIGGER 0x00000000U
#define | DFSDM_FILTER_SYNC_TRIGGER 0x00000001U
#define | DFSDM_FILTER_EXT_TRIGGER 0x00000002U

Define Documentation

#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U

External trigger (only for injected conversion)

Definition at line 378 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), and HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_SW_TRIGGER 0x00000000U

Software trigger

Definition at line 376 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U

Synchronous with DFSDM_FLT0

Definition at line 377 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStop(), and HAL_DFSDM_FilterInit().

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STM32H7B3xQ HAL User Manual: DFSDM filter external trigger

Defines
DFSDM filter external trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_COMP1_OUT
#define | DFSDM_FILTER_EXT_TRIG_COMP2_OUT

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT
Value:
(DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)

Definition at line 403 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT
Value:
(DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

Definition at line 405 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)

For all DFSDM filters

Definition at line 397 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)

For all DFSDM filters

Definition at line 398 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)

Definition at line 395 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)

Definition at line 396 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)

For all DFSDM filters

Definition at line 399 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)

For all DFSDM filters

Definition at line 400 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)

For all DFSDM filters

Definition at line 401 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

For all DFSDM filters

Definition at line 392 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U

For all DFSDM filters

Definition at line 386 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0

For all DFSDM filters

Definition at line 387 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2

For all DFSDM filters

Definition at line 390 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

For all DFSDM filters

Definition at line 391 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

For all DFSDM filters

Definition at line 393 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3

For all DFSDM filters

Definition at line 394 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1

For all DFSDM filters

Definition at line 388 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

For all DFSDM filters

Definition at line 389 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM filter external trigger edge

Defines
DFSDM filter external trigger edge
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

External rising and falling edges

Definition at line 417 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1

External falling edge

Definition at line 416 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0

External rising edge

Definition at line 415 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM filter sinc order

Defines
DFSDM filter sinc order
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_FASTSINC_ORDER 0x00000000U
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Define Documentation

#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U

FastSinc filter type

Definition at line 425 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0

Sinc 1 filter type

Definition at line 426 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1

Sinc 2 filter type

Definition at line 427 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)

Sinc 3 filter type

Definition at line 428 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2

Sinc 4 filter type

Definition at line 429 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Sinc 5 filter type

Definition at line 430 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM filter analog watchdog data source

Defines
DFSDM filter analog watchdog data source
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

Define Documentation

#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

From analog watchdog channel

Definition at line 439 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U

From digital filter

Definition at line 438 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM filter error code

Defines
DFSDM filter error code
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_ERROR_NONE 0x00000000U
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U
#define | DFSDM_FILTER_ERROR_DMA 0x00000003U
#define | DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U

Define Documentation

#define DFSDM_FILTER_ERROR_DMA 0x00000003U

DMA error occurs

Definition at line 450 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError().

#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U

Overrun occurs during injected conversion

Definition at line 449 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U

Invalid callback error occurs

Definition at line 452 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_Filter_RegisterAwdCallback(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterAwdCallback(), and HAL_DFSDM_Filter_UnRegisterCallback().

#define DFSDM_FILTER_ERROR_NONE 0x00000000U

No error

Definition at line 447 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U

Overrun occurs during regular conversion

Definition at line 448 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

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STM32H7B3xQ HAL User Manual: DFSDM break signals

Defines
DFSDM break signals
DFSDM Exported Constants

Defines

#define | DFSDM_NO_BREAK_SIGNAL 0x00000000U
#define | DFSDM_BREAK_SIGNAL_0 0x00000001U
#define | DFSDM_BREAK_SIGNAL_1 0x00000002U
#define | DFSDM_BREAK_SIGNAL_2 0x00000004U
#define | DFSDM_BREAK_SIGNAL_3 0x00000008U

Define Documentation

#define DFSDM_BREAK_SIGNAL_0 0x00000001U

Break signal 0

Definition at line 462 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_1 0x00000002U

Break signal 1

Definition at line 463 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_2 0x00000004U

Break signal 2

Definition at line 464 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_3 0x00000008U

Break signal 3

Definition at line 465 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_NO_BREAK_SIGNAL 0x00000000U

No break signal

Definition at line 461 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM Channel Selection

Defines
DFSDM Channel Selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_0 0x00000001U
#define | DFSDM_CHANNEL_1 0x00010002U
#define | DFSDM_CHANNEL_2 0x00020004U
#define | DFSDM_CHANNEL_3 0x00030008U
#define | DFSDM_CHANNEL_4 0x00040010U
#define | DFSDM_CHANNEL_5 0x00050020U
#define | DFSDM_CHANNEL_6 0x00060040U
#define | DFSDM_CHANNEL_7 0x00070080U

Define Documentation

#define DFSDM_CHANNEL_0 0x00000001U

Definition at line 481 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_1 0x00010002U

Definition at line 482 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_2 0x00020004U

Definition at line 483 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_3 0x00030008U

Definition at line 484 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_4 0x00040010U

Definition at line 485 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_5 0x00050020U

Definition at line 486 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_6 0x00060040U

Definition at line 487 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_7 0x00070080U

Definition at line 488 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM Continuous Mode

Defines
DFSDM Continuous Mode
DFSDM Exported Constants

Defines

#define | DFSDM_CONTINUOUS_CONV_OFF 0x00000000U
#define | DFSDM_CONTINUOUS_CONV_ON 0x00000001U

Define Documentation

#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U

Conversion are not continuous

Definition at line 496 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U

Conversion are continuous

Definition at line 497 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM analog watchdog threshold

Defines
DFSDM analog watchdog threshold
DFSDM Exported Constants

Defines

#define | DFSDM_AWD_HIGH_THRESHOLD 0x00000000U
#define | DFSDM_AWD_LOW_THRESHOLD 0x00000001U

Define Documentation

#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U

Analog watchdog high threshold

Definition at line 505 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U

Analog watchdog low threshold

Definition at line 506 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Exported Macros

Defines
DFSDM Exported Macros
DFSDM

Defines

#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__)
Reset DFSDM filter handle state.

Define Documentation

#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                      \
                                                               (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;                \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;              \
                                                             } while(0)

Reset DFSDM channel handle state.

Parameters:
__HANDLE__ DFSDM channel handle.
Return values:
None

Definition at line 526 of file stm32h7xx_hal_dfsdm.h.

#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                     \
                                                              (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
                                                              (__HANDLE__)->MspInitCallback = NULL;               \
                                                              (__HANDLE__)->MspDeInitCallback = NULL;             \
                                                            } while(0)

Reset DFSDM filter handle state.

Parameters:
__HANDLE__ DFSDM filter handle.
Return values:
None

Definition at line 540 of file stm32h7xx_hal_dfsdm.h.

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STM32H7B3xQ HAL User Manual: DFSDM Private Macros

Defines
DFSDM Private Macros
DFSDM

Defines

#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)
#define | IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)
#define | IS_DFSDM1_FILTER_INSTANCE(INSTANCE)

Define Documentation

#define IS_DFSDM1_CHANNEL_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == DFSDM1_Channel0) || \
                                                       ((INSTANCE) == DFSDM1_Channel1) || \
                                                       ((INSTANCE) == DFSDM1_Channel2) || \
                                                       ((INSTANCE) == DFSDM1_Channel3) || \
                                                       ((INSTANCE) == DFSDM1_Channel4) || \
                                                       ((INSTANCE) == DFSDM1_Channel5) || \
                                                       ((INSTANCE) == DFSDM1_Channel6) || \
                                                       ((INSTANCE) == DFSDM1_Channel7))

Definition at line 815 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

#define IS_DFSDM1_FILTER_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == DFSDM1_Filter0) || \
                                                       ((INSTANCE) == DFSDM1_Filter1) || \
                                                       ((INSTANCE) == DFSDM1_Filter2) || \
                                                       ((INSTANCE) == DFSDM1_Filter3) || \
                                                       ((INSTANCE) == DFSDM1_Filter4) || \
                                                       ((INSTANCE) == DFSDM1_Filter5) || \
                                                       ((INSTANCE) == DFSDM1_Filter6) || \
                                                       ((INSTANCE) == DFSDM1_Filter7))

Definition at line 823 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit(), and HAL_DFSDM_IRQHandler().

#define IS_DFSDM_BREAK_SIGNALS ( VALUE ) ((VALUE) <= 0xFU)

Definition at line 802 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), and HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_CHANNEL_DATA_PACKING ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))

Definition at line 727 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

Definition at line 740 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO ( RATIO ) ((1U <= (RATIO)) && ((RATIO) <= 32U))

Definition at line 744 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT ( INPUT )
Value:
(((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

Definition at line 724 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT_PINS ( PINS )
Value:
(((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

Definition at line 730 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OFFSET ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 745 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit(), and HAL_DFSDM_ChannelModifyOffset().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK ( CLOCK )
Value:
(((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

Definition at line 721 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER ( DIVIDER ) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))

Definition at line 723 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT ( VALUE ) ((VALUE) <= 0x1FU)

Definition at line 746 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SCD_THRESHOLD ( VALUE ) ((VALUE) <= 0xFFU)

Definition at line 747 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), and HAL_DFSDM_ChannelScdStart_IT().

#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

Definition at line 732 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SPI_CLOCK ( TYPE )
Value:
(((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

Definition at line 736 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CONTINUOUS_MODE ( MODE )
Value:
(((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))

Definition at line 812 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define IS_DFSDM_FILTER_AWD_DATA_SOURCE ( DATA )
Value:
(((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

Definition at line 799 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_AWD_THRESHOLD ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 801 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_EXT_TRIG ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))

Definition at line 754 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_EXT_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

Definition at line 788 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INJ_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

Definition at line 750 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO ( RATIO ) ((1U <= (RATIO)) && ((RATIO) <= 256U))

Definition at line 798 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_OVS_RATIO ( RATIO ) ((1U <= (RATIO)) && ((RATIO) <= 1024U))

Definition at line 797 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_REG_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

Definition at line 748 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_SINC_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))

Definition at line 791 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_INJECTED_CHANNEL ( CHANNEL ) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))

Definition at line 811 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define IS_DFSDM_REGULAR_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DFSDM_CHANNEL_0)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_7))

Definition at line 803 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended channel operation functions

Functions
Extended channel operation functions
DFSDM Extended Exported Functions

DFSDM extended channel operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFDSMEx_ChannelSetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
Set value of pulses skipping.
HAL_StatusTypeDef | HAL_DFDSMEx_ChannelGetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
Get value of pulses skipping.

Detailed Description

DFSDM extended channel operation functions.

 ===============================================================================
               ##### Extended channel operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Set and get value of pulses skipping on channel

Function Documentation

HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t * | PulsesValue
 | ) |  |

Get value of pulses skipping.

Parameters:
hdfsdm_channel | DFSDM channel handle.
PulsesValue | Value of pulses to be skipped.
Return values:
HAL status.

Definition at line 98 of file stm32h7xx_hal_dfsdm_ex.c.

References HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, and __DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | PulsesValue
 | ) |  |

Set value of pulses skipping.

Parameters:
hdfsdm_channel | DFSDM channel handle.
PulsesValue | Value of pulses to be skipped. This parameter must be a number between Min_Data = 0 and Max_Data = 63.
Return values:
HAL status.

Definition at line 72 of file stm32h7xx_hal_dfsdm_ex.c.

References assert_param, HAL_DFSDM_CHANNEL_STATE_READY, __DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_SKIPPING_VALUE, and __DFSDM_Channel_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DFSDM Extended Private Macros

Defines
DFSDM Extended Private Macros
DFSDMEx

Defines

#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U)

Define Documentation

#define IS_DFSDM_CHANNEL_SKIPPING_VALUE ( VALUE ) ((VALUE) < 64U)

Definition at line 71 of file stm32h7xx_hal_dfsdm_ex.h.

Referenced by HAL_DFDSMEx_ChannelSetPulsesSkipping().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

DMA Exported Types. More...

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Transfer complete level structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U
}
HAL DMA Callbacks IDs structure definition. More...

Detailed Description

DMA Exported Types.

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callbacks IDs structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half Transfer

HAL_DMA_XFER_M1CPLT_CB_ID

M1 Full Transfer

HAL_DMA_XFER_M1HALFCPLT_CB_ID

M1 Half Transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 123 of file stm32h7xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Transfer complete level structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 114 of file stm32h7xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_ERROR

DMA error state

HAL_DMA_STATE_ABORT

DMA Abort state

Definition at line 102 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32h7xx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority
uint32_t | FIFOMode
uint32_t | FIFOThreshold
uint32_t | MemBurst
uint32_t | PeriphBurst

Detailed Description

DMA Configuration Structure definition.

Definition at line 49 of file stm32h7xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 54 of file stm32h7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t DMA_InitTypeDef::FIFOMode

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of DMA FIFO direct mode

Note:
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream

Definition at line 78 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::FIFOThreshold

Specifies the FIFO threshold level. This parameter can be a value of DMA FIFO threshold level

Definition at line 83 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemBurst

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Memory burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 86 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 67 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 61 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream

Definition at line 70 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), I2S_DMARxCplt(), I2S_DMATxCplt(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

uint32_t DMA_InitTypeDef::PeriphBurst

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Peripheral burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 92 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 64 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 58 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Streamx. This parameter can be a value of DMA Priority level

Definition at line 75 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified stream. This parameter can be a value of DMA Request selection

Definition at line 51 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32h7xx_hal_dma.h>

Data Fields

void * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1CpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1HalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
uint32_t | StreamBaseAddress
uint32_t | StreamIndex
DMAMUX_Channel_TypeDef * | DMAmuxChannel
DMAMUX_ChannelStatus_TypeDef * | DMAmuxChannelStatus
uint32_t | DMAmuxChannelStatusMask
DMAMUX_RequestGen_TypeDef * | DMAmuxRequestGen
DMAMUX_RequestGenStatus_TypeDef * | DMAmuxRequestGenStatus
uint32_t | DMAmuxRequestGenStatusMask

Detailed Description

DMA handle Structure definition.

Definition at line 137 of file stm32h7xx_hal_dma.h.

Field Documentation

DMAMUX_Channel_TypeDef* __DMA_HandleTypeDef::DMAmuxChannel

DMAMUX Channel Base Address

Definition at line 167 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_ChannelStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxChannelStatus

DMAMUX Channels Status Base Address

Definition at line 169 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxChannelStatusMask

DMAMUX Channel Status Mask

Definition at line 171 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGen_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGen

DMAMUX request generator Base Address

Definition at line 174 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGenStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGenStatus

DMAMUX request generator Status Address

Definition at line 176 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask

DMAMUX request generator Status mask

Definition at line 178 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 161 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAError(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_DMAEx_MUX_IRQHandler(), HAL_SAI_Abort(), and HAL_SAI_DMAStop().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 141 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_CheckFifoParam(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), I2S_DMARxCplt(), I2S_DMATxCplt(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

void* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 139 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAXferCplt(), DMA_CalcBaseAndBitshift(), DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ChangeMemory(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_HASH_DMAFeed_ProcessSuspend(), SWPMI_DMAReceiveCplt(), and SWPMI_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 143 of file stm32h7xx_hal_dma.h.

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 147 of file stm32h7xx_hal_dma.h.

Referenced by IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 145 of file stm32h7xx_hal_dma.h.

Referenced by HAL_ADC_Stop_DMA(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamBaseAddress

DMA Stream Base Address

Definition at line 163 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamIndex

DMA Stream Index

Definition at line 165 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer Abort callback

Definition at line 159 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_IRQHandler(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), PSSI_DMAAbort(), PSSI_Error(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 149 of file stm32h7xx_hal_dma.h.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_DMAXferCplt(), HASH_Start_DMA(), and HMAC_Start_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 157 of file stm32h7xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MUX_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_Start_DMA(), and HMAC_Start_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 151 of file stm32h7xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MultiBufferStart_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete Memory1 callback

Definition at line 153 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DCMI_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), and HAL_DMA_UnRegisterCallback().

void(* __DMA_HandleTypeDef::XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer Half complete Memory1 callback

Definition at line 155 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), and HAL_DMAEx_MultiBufferStart_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

DMA Error Code. More...

Defines

#define | HAL_DMA_ERROR_NONE (0x00000000U)
#define | HAL_DMA_ERROR_TE (0x00000001U)
#define | HAL_DMA_ERROR_FE (0x00000002U)
#define | HAL_DMA_ERROR_DME (0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DMA_ERROR_PARAM (0x00000040U)
#define | HAL_DMA_ERROR_NO_XFER (0x00000080U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
#define | HAL_DMA_ERROR_SYNC (0x00000200U)
#define | HAL_DMA_ERROR_REQGEN (0x00000400U)
#define | HAL_DMA_ERROR_BUSY (0x00000800U)

Detailed Description

DMA Error Code.

Define Documentation

#define HAL_DMA_ERROR_BUSY (0x00000800U)

DMA Busy error

Definition at line 208 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define HAL_DMA_ERROR_DME (0x00000004U)

Direct Mode error

Definition at line 201 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_FE (0x00000002U)

FIFO error

Definition at line 200 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAError(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), I2C_DMAError(), SAI_DMAError(), and SPI_DMAError().

#define HAL_DMA_ERROR_NO_XFER (0x00000080U)

Abort requested with no Xfer ongoing

Definition at line 204 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_PollForTransfer(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), and HAL_SPI_Abort_IT().

#define HAL_DMA_ERROR_NONE (0x00000000U)

No error

Definition at line 198 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_MMC_Init(), and HAL_MMC_ReadBlocks_DMA().

#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)

Not supported mode

Definition at line 205 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define HAL_DMA_ERROR_PARAM (0x00000040U)

Parameter error

Definition at line 203 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init(), and HAL_DMAEx_ConfigMuxRequestGenerator().

#define HAL_DMA_ERROR_REQGEN (0x00000400U)

DMAMUX request generator overrun error

Definition at line 207 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_SYNC (0x00000200U)

DMAMUX sync overrun error

Definition at line 206 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_TE (0x00000001U)

Transfer error

Definition at line 199 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 202 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Request selection

Defines
DMA Request selection
DMA Exported Constants

DMA Request selection. More...

Defines

#define | DMA_REQUEST_MEM2MEM 0U
#define | DMA_REQUEST_GENERATOR0 1U
#define | DMA_REQUEST_GENERATOR1 2U
#define | DMA_REQUEST_GENERATOR2 3U
#define | DMA_REQUEST_GENERATOR3 4U
#define | DMA_REQUEST_GENERATOR4 5U
#define | DMA_REQUEST_GENERATOR5 6U
#define | DMA_REQUEST_GENERATOR6 7U
#define | DMA_REQUEST_GENERATOR7 8U
#define | DMA_REQUEST_ADC1 9U
#define | DMA_REQUEST_ADC2 10U
#define | DMA_REQUEST_TIM1_CH1 11U
#define | DMA_REQUEST_TIM1_CH2 12U
#define | DMA_REQUEST_TIM1_CH3 13U
#define | DMA_REQUEST_TIM1_CH4 14U
#define | DMA_REQUEST_TIM1_UP 15U
#define | DMA_REQUEST_TIM1_TRIG 16U
#define | DMA_REQUEST_TIM1_COM 17U
#define | DMA_REQUEST_TIM2_CH1 18U
#define | DMA_REQUEST_TIM2_CH2 19U
#define | DMA_REQUEST_TIM2_CH3 20U
#define | DMA_REQUEST_TIM2_CH4 21U
#define | DMA_REQUEST_TIM2_UP 22U
#define | DMA_REQUEST_TIM3_CH1 23U
#define | DMA_REQUEST_TIM3_CH2 24U
#define | DMA_REQUEST_TIM3_CH3 25U
#define | DMA_REQUEST_TIM3_CH4 26U
#define | DMA_REQUEST_TIM3_UP 27U
#define | DMA_REQUEST_TIM3_TRIG 28U
#define | DMA_REQUEST_TIM4_CH1 29U
#define | DMA_REQUEST_TIM4_CH2 30U
#define | DMA_REQUEST_TIM4_CH3 31U
#define | DMA_REQUEST_TIM4_UP 32U
#define | DMA_REQUEST_I2C1_RX 33U
#define | DMA_REQUEST_I2C1_TX 34U
#define | DMA_REQUEST_I2C2_RX 35U
#define | DMA_REQUEST_I2C2_TX 36U
#define | DMA_REQUEST_SPI1_RX 37U
#define | DMA_REQUEST_SPI1_TX 38U
#define | DMA_REQUEST_SPI2_RX 39U
#define | DMA_REQUEST_SPI2_TX 40U
#define | DMA_REQUEST_USART1_RX 41U
#define | DMA_REQUEST_USART1_TX 42U
#define | DMA_REQUEST_USART2_RX 43U
#define | DMA_REQUEST_USART2_TX 44U
#define | DMA_REQUEST_USART3_RX 45U
#define | DMA_REQUEST_USART3_TX 46U
#define | DMA_REQUEST_TIM8_CH1 47U
#define | DMA_REQUEST_TIM8_CH2 48U
#define | DMA_REQUEST_TIM8_CH3 49U
#define | DMA_REQUEST_TIM8_CH4 50U
#define | DMA_REQUEST_TIM8_UP 51U
#define | DMA_REQUEST_TIM8_TRIG 52U
#define | DMA_REQUEST_TIM8_COM 53U
#define | DMA_REQUEST_TIM5_CH1 55U
#define | DMA_REQUEST_TIM5_CH2 56U
#define | DMA_REQUEST_TIM5_CH3 57U
#define | DMA_REQUEST_TIM5_CH4 58U
#define | DMA_REQUEST_TIM5_UP 59U
#define | DMA_REQUEST_TIM5_TRIG 60U
#define | DMA_REQUEST_SPI3_RX 61U
#define | DMA_REQUEST_SPI3_TX 62U
#define | DMA_REQUEST_UART4_RX 63U
#define | DMA_REQUEST_UART4_TX 64U
#define | DMA_REQUEST_UART5_RX 65U
#define | DMA_REQUEST_UART5_TX 66U
#define | DMA_REQUEST_DAC1_CH1 67U
#define | DMA_REQUEST_DAC1_CH2 68U
#define | DMA_REQUEST_TIM6_UP 69U
#define | DMA_REQUEST_TIM7_UP 70U
#define | DMA_REQUEST_USART6_RX 71U
#define | DMA_REQUEST_USART6_TX 72U
#define | DMA_REQUEST_I2C3_RX 73U
#define | DMA_REQUEST_I2C3_TX 74U
#define | DMA_REQUEST_DCMI_PSSI 75U
#define | DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
#define | DMA_REQUEST_CRYP_IN 76U
#define | DMA_REQUEST_CRYP_OUT 77U
#define | DMA_REQUEST_HASH_IN 78U
#define | DMA_REQUEST_UART7_RX 79U
#define | DMA_REQUEST_UART7_TX 80U
#define | DMA_REQUEST_UART8_RX 81U
#define | DMA_REQUEST_UART8_TX 82U
#define | DMA_REQUEST_SPI4_RX 83U
#define | DMA_REQUEST_SPI4_TX 84U
#define | DMA_REQUEST_SPI5_RX 85U
#define | DMA_REQUEST_SPI5_TX 86U
#define | DMA_REQUEST_SAI1_A 87U
#define | DMA_REQUEST_SAI1_B 88U
#define | DMA_REQUEST_SAI2_A 89U
#define | DMA_REQUEST_SAI2_B 90U
#define | DMA_REQUEST_SWPMI_RX 91U
#define | DMA_REQUEST_SWPMI_TX 92U
#define | DMA_REQUEST_SPDIF_RX_DT 93U
#define | DMA_REQUEST_SPDIF_RX_CS 94U
#define | DMA_REQUEST_DFSDM1_FLT0 101U
#define | DMA_REQUEST_DFSDM1_FLT1 102U
#define | DMA_REQUEST_DFSDM1_FLT2 103U
#define | DMA_REQUEST_DFSDM1_FLT3 104U
#define | DMA_REQUEST_TIM15_CH1 105U
#define | DMA_REQUEST_TIM15_UP 106U
#define | DMA_REQUEST_TIM15_TRIG 107U
#define | DMA_REQUEST_TIM15_COM 108U
#define | DMA_REQUEST_TIM16_CH1 109U
#define | DMA_REQUEST_TIM16_UP 110U
#define | DMA_REQUEST_TIM17_CH1 111U
#define | DMA_REQUEST_TIM17_UP 112U
#define | DMA_REQUEST_UART9_RX 116U
#define | DMA_REQUEST_UART9_TX 117U
#define | DMA_REQUEST_USART10_RX 118U
#define | DMA_REQUEST_USART10_TX 119U
#define | BDMA_REQUEST_MEM2MEM 0U
#define | BDMA_REQUEST_GENERATOR0 1U
#define | BDMA_REQUEST_GENERATOR1 2U
#define | BDMA_REQUEST_GENERATOR2 3U
#define | BDMA_REQUEST_GENERATOR3 4U
#define | BDMA_REQUEST_GENERATOR4 5U
#define | BDMA_REQUEST_GENERATOR5 6U
#define | BDMA_REQUEST_GENERATOR6 7U
#define | BDMA_REQUEST_GENERATOR7 8U
#define | BDMA_REQUEST_LPUART1_RX 9U
#define | BDMA_REQUEST_LPUART1_TX 10U
#define | BDMA_REQUEST_SPI6_RX 11U
#define | BDMA_REQUEST_SPI6_TX 12U
#define | BDMA_REQUEST_I2C4_RX 13U
#define | BDMA_REQUEST_I2C4_TX 14U
#define | BDMA_REQUEST_DAC2_CH1 17U
#define | BDMA_REQUEST_DFSDM2 18U

Detailed Description

DMA Request selection.

Define Documentation

#define BDMA_REQUEST_DAC2_CH1 17U

DMAMUX2 DAC2 CH1 request

Definition at line 415 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_DFSDM2 18U

DMAMUX2 DFSDM2 request

Definition at line 418 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR0 1U

DMAMUX2 request generator 0

Definition at line 393 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR1 2U

DMAMUX2 request generator 1

Definition at line 394 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR2 3U

DMAMUX2 request generator 2

Definition at line 395 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR3 4U

DMAMUX2 request generator 3

Definition at line 396 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR4 5U

DMAMUX2 request generator 4

Definition at line 397 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR5 6U

DMAMUX2 request generator 5

Definition at line 398 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR6 7U

DMAMUX2 request generator 6

Definition at line 399 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR7 8U

DMAMUX2 request generator 7

Definition at line 400 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_I2C4_RX 13U

DMAMUX2 I2C4 RX request

Definition at line 405 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_I2C4_TX 14U

DMAMUX2 I2C4 TX request

Definition at line 406 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_LPUART1_RX 9U

DMAMUX2 LP_UART1_RX request

Definition at line 401 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_LPUART1_TX 10U

DMAMUX2 LP_UART1_TX request

Definition at line 402 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_MEM2MEM 0U

memory to memory transfer

Definition at line 392 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SPI6_RX 11U

DMAMUX2 SPI6 RX request

Definition at line 403 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SPI6_TX 12U

DMAMUX2 SPI6 TX request

Definition at line 404 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_ADC1 9U

DMAMUX1 ADC1 request

Definition at line 230 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_ADC2 10U

DMAMUX1 ADC2 request

Definition at line 231 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_CRYP_IN 76U

DMAMUX1 CRYP IN request

Definition at line 318 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_CRYP_OUT 77U

DMAMUX1 CRYP OUT request

Definition at line 319 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CH1 67U

DMAMUX1 DAC1 Channel 1 request

Definition at line 299 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CH2 68U

DMAMUX1 DAC1 Channel 2 request

Definition at line 300 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */

Definition at line 313 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DCMI_PSSI 75U

DMAMUX1 DCMI/PSSI request

Definition at line 312 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT0 101U

DMAMUX1 DFSDM Filter0 request

Definition at line 354 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT1 102U

DMAMUX1 DFSDM Filter1 request

Definition at line 355 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT2 103U

DMAMUX1 DFSDM Filter2 request

Definition at line 356 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT3 104U

DMAMUX1 DFSDM Filter3 request

Definition at line 357 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR0 1U

DMAMUX1 request generator 0

Definition at line 221 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

#define DMA_REQUEST_GENERATOR1 2U

DMAMUX1 request generator 1

Definition at line 222 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR2 3U

DMAMUX1 request generator 2

Definition at line 223 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR3 4U

DMAMUX1 request generator 3

Definition at line 224 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR4 5U

DMAMUX1 request generator 4

Definition at line 225 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR5 6U

DMAMUX1 request generator 5

Definition at line 226 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR6 7U

DMAMUX1 request generator 6

Definition at line 227 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR7 8U

DMAMUX1 request generator 7

Definition at line 228 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

#define DMA_REQUEST_HASH_IN 78U

DMAMUX1 HASH IN request

Definition at line 321 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C1_RX 33U

DMAMUX1 I2C1 RX request

Definition at line 259 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C1_TX 34U

DMAMUX1 I2C1 TX request

Definition at line 260 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C2_RX 35U

DMAMUX1 I2C2 RX request

Definition at line 261 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C2_TX 36U

DMAMUX1 I2C2 TX request

Definition at line 262 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C3_RX 73U

DMAMUX1 I2C3 RX request

Definition at line 308 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C3_TX 74U

DMAMUX1 I2C3 TX request

Definition at line 309 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_MEM2MEM 0U

memory to memory transfer

Definition at line 219 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_REQUEST_SAI1_A 87U

DMAMUX1 SAI1 A request

Definition at line 333 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI1_B 88U

DMAMUX1 SAI1 B request

Definition at line 334 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI2_A 89U

DMAMUX1 SAI2 A request

Definition at line 335 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI2_B 90U

DMAMUX1 SAI2 B request

Definition at line 336 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPDIF_RX_CS 94U

DMAMUX1 SPDIF RXCS request

Definition at line 342 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPDIF_RX_DT 93U

DMAMUX1 SPDIF RXDT request

Definition at line 341 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI1_RX 37U

DMAMUX1 SPI1 RX request

Definition at line 264 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI1_TX 38U

DMAMUX1 SPI1 TX request

Definition at line 265 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI2_RX 39U

DMAMUX1 SPI2 RX request

Definition at line 266 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI2_TX 40U

DMAMUX1 SPI2 TX request

Definition at line 267 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI3_RX 61U

DMAMUX1 SPI3 RX request

Definition at line 291 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI3_TX 62U

DMAMUX1 SPI3 TX request

Definition at line 292 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI4_RX 83U

DMAMUX1 SPI4 RX request

Definition at line 328 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI4_TX 84U

DMAMUX1 SPI4 TX request

Definition at line 329 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI5_RX 85U

DMAMUX1 SPI5 RX request

Definition at line 330 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI5_TX 86U

DMAMUX1 SPI5 TX request

Definition at line 331 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SWPMI_RX 91U

DMAMUX1 SWPMI RX request

Definition at line 338 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SWPMI_TX 92U

DMAMUX1 SWPMI TX request

Definition at line 339 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_CH1 105U

DMAMUX1 TIM15 CH1 request

Definition at line 360 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_COM 108U

DMAMUX1 TIM15 COM request

Definition at line 363 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_TRIG 107U

DMAMUX1 TIM15 TRIG request

Definition at line 362 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_UP 106U

DMAMUX1 TIM15 UP request

Definition at line 361 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM16_CH1 109U

DMAMUX1 TIM16 CH1 request

Definition at line 365 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM16_UP 110U

DMAMUX1 TIM16 UP request

Definition at line 366 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM17_CH1 111U

DMAMUX1 TIM17 CH1 request

Definition at line 368 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM17_UP 112U

DMAMUX1 TIM17 UP request

Definition at line 369 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH1 11U

DMAMUX1 TIM1 CH1 request

Definition at line 233 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH2 12U

DMAMUX1 TIM1 CH2 request

Definition at line 234 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH3 13U

DMAMUX1 TIM1 CH3 request

Definition at line 235 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH4 14U

DMAMUX1 TIM1 CH4 request

Definition at line 236 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_COM 17U

DMAMUX1 TIM1 COM request

Definition at line 239 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_TRIG 16U

DMAMUX1 TIM1 TRIG request

Definition at line 238 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_UP 15U

DMAMUX1 TIM1 UP request

Definition at line 237 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH1 18U

DMAMUX1 TIM2 CH1 request

Definition at line 241 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH2 19U

DMAMUX1 TIM2 CH2 request

Definition at line 242 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH3 20U

DMAMUX1 TIM2 CH3 request

Definition at line 243 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH4 21U

DMAMUX1 TIM2 CH4 request

Definition at line 244 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_UP 22U

DMAMUX1 TIM2 UP request

Definition at line 245 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH1 23U

DMAMUX1 TIM3 CH1 request

Definition at line 247 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH2 24U

DMAMUX1 TIM3 CH2 request

Definition at line 248 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH3 25U

DMAMUX1 TIM3 CH3 request

Definition at line 249 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH4 26U

DMAMUX1 TIM3 CH4 request

Definition at line 250 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_TRIG 28U

DMAMUX1 TIM3 TRIG request

Definition at line 252 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_UP 27U

DMAMUX1 TIM3 UP request

Definition at line 251 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH1 29U

DMAMUX1 TIM4 CH1 request

Definition at line 254 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH2 30U

DMAMUX1 TIM4 CH2 request

Definition at line 255 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH3 31U

DMAMUX1 TIM4 CH3 request

Definition at line 256 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_UP 32U

DMAMUX1 TIM4 UP request

Definition at line 257 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH1 55U

DMAMUX1 TIM5 CH1 request

Definition at line 284 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH2 56U

DMAMUX1 TIM5 CH2 request

Definition at line 285 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH3 57U

DMAMUX1 TIM5 CH3 request

Definition at line 286 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH4 58U

DMAMUX1 TIM5 CH4 request

Definition at line 287 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_TRIG 60U

DMAMUX1 TIM5 TRIG request

Definition at line 289 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_UP 59U

DMAMUX1 TIM5 UP request

Definition at line 288 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM6_UP 69U

DMAMUX1 TIM6 UP request

Definition at line 302 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM7_UP 70U

DMAMUX1 TIM7 UP request

Definition at line 303 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH1 47U

DMAMUX1 TIM8 CH1 request

Definition at line 276 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH2 48U

DMAMUX1 TIM8 CH2 request

Definition at line 277 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH3 49U

DMAMUX1 TIM8 CH3 request

Definition at line 278 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH4 50U

DMAMUX1 TIM8 CH4 request

Definition at line 279 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_COM 53U

DMAMUX1 TIM8 COM request

Definition at line 282 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_TRIG 52U

DMAMUX1 TIM8 TRIG request

Definition at line 281 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_UP 51U

DMAMUX1 TIM8 UP request

Definition at line 280 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART4_RX 63U

DMAMUX1 UART4 RX request

Definition at line 294 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART4_TX 64U

DMAMUX1 UART4 TX request

Definition at line 295 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART5_RX 65U

DMAMUX1 UART5 RX request

Definition at line 296 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART5_TX 66U

DMAMUX1 UART5 TX request

Definition at line 297 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART7_RX 79U

DMAMUX1 UART7 RX request

Definition at line 323 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART7_TX 80U

DMAMUX1 UART7 TX request

Definition at line 324 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART8_RX 81U

DMAMUX1 UART8 RX request

Definition at line 325 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART8_TX 82U

DMAMUX1 UART8 TX request

Definition at line 326 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART9_RX 116U

DMAMUX1 UART9 request

Definition at line 381 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART9_TX 117U

DMAMUX1 UART9 request

Definition at line 382 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART10_RX 118U

DMAMUX1 USART10 request

Definition at line 386 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART10_TX 119U

DMAMUX1 USART10 request

Definition at line 387 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART1_RX 41U

DMAMUX1 USART1 RX request

Definition at line 269 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART1_TX 42U

DMAMUX1 USART1 TX request

Definition at line 270 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART2_RX 43U

DMAMUX1 USART2 RX request

Definition at line 271 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART2_TX 44U

DMAMUX1 USART2 TX request

Definition at line 272 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART3_RX 45U

DMAMUX1 USART3 RX request

Definition at line 273 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART3_TX 46U

DMAMUX1 USART3 TX request

Definition at line 274 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART6_RX 71U

DMAMUX1 USART6 RX request

Definition at line 305 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART6_TX 72U

DMAMUX1 USART6 TX request

Definition at line 306 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

DMA data transfer direction. More...

Defines

#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Detailed Description

DMA data transfer direction.

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Memory to memory direction

Definition at line 431 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)

Memory to peripheral direction

Definition at line 430 of file stm32h7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), and DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)

Peripheral to memory direction

Definition at line 429 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

DMA peripheral incremented mode. More...

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA peripheral incremented mode.

Define Documentation

#define DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Peripheral increment mode disable

Definition at line 441 of file stm32h7xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)

Peripheral increment mode enable

Definition at line 440 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

DMA memory incremented mode. More...

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA memory incremented mode.

Define Documentation

#define DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Memory increment mode disable

Definition at line 451 of file stm32h7xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)

Memory increment mode enable

Definition at line 450 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

DMA peripheral data size. More...

Defines

#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Detailed Description

DMA peripheral data size.

Define Documentation

#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)

Peripheral data alignment: Byte

Definition at line 460 of file stm32h7xx_hal_dma.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)

Peripheral data alignment: HalfWord

Definition at line 461 of file stm32h7xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Peripheral data alignment: Word

Definition at line 462 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

DMA memory data size. More...

Defines

#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Detailed Description

DMA memory data size.

Define Documentation

#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)

Memory data alignment: Byte

Definition at line 471 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)

Memory data alignment: HalfWord

Definition at line 472 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Memory data alignment: Word

Definition at line 473 of file stm32h7xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

DMA mode. More...

Defines

#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
#define | DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)
#define | DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))

Detailed Description

DMA mode.

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)

Circular mode

Definition at line 483 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)

Double buffer mode with first target memory M0

Definition at line 485 of file stm32h7xx_hal_dma.h.

#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))

Double buffer mode with first target memory M1

Definition at line 486 of file stm32h7xx_hal_dma.h.

#define DMA_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 482 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_SPI_IRQHandler(), I2S_DMARxCplt(), and I2S_DMATxCplt().

#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Peripheral flow control mode

Definition at line 484 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

DMA priority levels. More...

Defines

#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Detailed Description

DMA priority levels.

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)

Priority level: High

Definition at line 497 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level: Low

Definition at line 495 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)

Priority level: Medium

Definition at line 496 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Priority level: Very High

Definition at line 498 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA FIFO direct mode

Defines
DMA FIFO direct mode
DMA Exported Constants

DMA FIFO direct mode. More...

Defines

#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

Detailed Description

DMA FIFO direct mode.

Define Documentation

#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)

FIFO mode disable

Definition at line 507 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

FIFO mode enable

Definition at line 508 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA FIFO threshold level

Defines
DMA FIFO threshold level
DMA Exported Constants

DMA FIFO level. More...

Defines

#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

Detailed Description

DMA FIFO level.

Define Documentation

#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)

FIFO threshold 1 quart full configuration

Definition at line 517 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)

FIFO threshold 3 quarts full configuration

Definition at line 519 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

FIFO threshold full configuration

Definition at line 520 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)

FIFO threshold half full configuration

Definition at line 518 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Memory burst

Defines
DMA Memory burst
DMA Exported Constants

DMA memory burst. More...

Defines

#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Detailed Description

DMA memory burst.

Define Documentation

#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Definition at line 532 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)

Definition at line 530 of file stm32h7xx_hal_dma.h.

#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)

Definition at line 531 of file stm32h7xx_hal_dma.h.

#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 529 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Peripheral burst

Defines
DMA Peripheral burst
DMA Exported Constants

DMA peripheral burst. More...

Defines

#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Detailed Description

DMA peripheral burst.

Define Documentation

#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Definition at line 544 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)

Definition at line 542 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)

Definition at line 543 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 541 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

DMA interrupts definition. More...

Defines

#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)

Detailed Description

DMA interrupts definition.

Define Documentation

#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)

Definition at line 556 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_FE ((uint32_t)0x00000080U)

Definition at line 557 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)

Definition at line 554 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)

Definition at line 553 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)

Definition at line 555 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

DMA flag definitions. More...

Defines

#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Detailed Description

DMA flag definitions.

Define Documentation

#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)

Definition at line 567 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)

Definition at line 572 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)

Definition at line 577 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)

Definition at line 582 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)

Definition at line 566 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)

Definition at line 571 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)

Definition at line 576 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)

Definition at line 581 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)

Definition at line 569 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)

Definition at line 574 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)

Definition at line 579 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)

Definition at line 584 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)

Definition at line 570 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)

Definition at line 575 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)

Definition at line 580 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Definition at line 585 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)

Definition at line 568 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)

Definition at line 573 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)

Definition at line 578 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)

Definition at line 583 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BDMA flag definitions

Defines
BDMA flag definitions
DMA Exported Constants

BDMA flag definitions. More...

Defines

#define | BDMA_FLAG_GL0 ((uint32_t)0x00000001)
#define | BDMA_FLAG_TC0 ((uint32_t)0x00000002)
#define | BDMA_FLAG_HT0 ((uint32_t)0x00000004)
#define | BDMA_FLAG_TE0 ((uint32_t)0x00000008)
#define | BDMA_FLAG_GL1 ((uint32_t)0x00000010)
#define | BDMA_FLAG_TC1 ((uint32_t)0x00000020)
#define | BDMA_FLAG_HT1 ((uint32_t)0x00000040)
#define | BDMA_FLAG_TE1 ((uint32_t)0x00000080)
#define | BDMA_FLAG_GL2 ((uint32_t)0x00000100)
#define | BDMA_FLAG_TC2 ((uint32_t)0x00000200)
#define | BDMA_FLAG_HT2 ((uint32_t)0x00000400)
#define | BDMA_FLAG_TE2 ((uint32_t)0x00000800)
#define | BDMA_FLAG_GL3 ((uint32_t)0x00001000)
#define | BDMA_FLAG_TC3 ((uint32_t)0x00002000)
#define | BDMA_FLAG_HT3 ((uint32_t)0x00004000)
#define | BDMA_FLAG_TE3 ((uint32_t)0x00008000)
#define | BDMA_FLAG_GL4 ((uint32_t)0x00010000)
#define | BDMA_FLAG_TC4 ((uint32_t)0x00020000)
#define | BDMA_FLAG_HT4 ((uint32_t)0x00040000)
#define | BDMA_FLAG_TE4 ((uint32_t)0x00080000)
#define | BDMA_FLAG_GL5 ((uint32_t)0x00100000)
#define | BDMA_FLAG_TC5 ((uint32_t)0x00200000)
#define | BDMA_FLAG_HT5 ((uint32_t)0x00400000)
#define | BDMA_FLAG_TE5 ((uint32_t)0x00800000)
#define | BDMA_FLAG_GL6 ((uint32_t)0x01000000)
#define | BDMA_FLAG_TC6 ((uint32_t)0x02000000)
#define | BDMA_FLAG_HT6 ((uint32_t)0x04000000)
#define | BDMA_FLAG_TE6 ((uint32_t)0x08000000)
#define | BDMA_FLAG_GL7 ((uint32_t)0x10000000)
#define | BDMA_FLAG_TC7 ((uint32_t)0x20000000)
#define | BDMA_FLAG_HT7 ((uint32_t)0x40000000)
#define | BDMA_FLAG_TE7 ((uint32_t)0x80000000)

Detailed Description

BDMA flag definitions.

Define Documentation

#define BDMA_FLAG_GL0 ((uint32_t)0x00000001)

Definition at line 594 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL1 ((uint32_t)0x00000010)

Definition at line 598 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL2 ((uint32_t)0x00000100)

Definition at line 602 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL3 ((uint32_t)0x00001000)

Definition at line 606 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL4 ((uint32_t)0x00010000)

Definition at line 610 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL5 ((uint32_t)0x00100000)

Definition at line 614 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL6 ((uint32_t)0x01000000)

Definition at line 618 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL7 ((uint32_t)0x10000000)

Definition at line 622 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT0 ((uint32_t)0x00000004)

Definition at line 596 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_HT1 ((uint32_t)0x00000040)

Definition at line 600 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT2 ((uint32_t)0x00000400)

Definition at line 604 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT3 ((uint32_t)0x00004000)

Definition at line 608 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT4 ((uint32_t)0x00040000)

Definition at line 612 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT5 ((uint32_t)0x00400000)

Definition at line 616 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT6 ((uint32_t)0x04000000)

Definition at line 620 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT7 ((uint32_t)0x40000000)

Definition at line 624 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC0 ((uint32_t)0x00000002)

Definition at line 595 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_TC1 ((uint32_t)0x00000020)

Definition at line 599 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC2 ((uint32_t)0x00000200)

Definition at line 603 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC3 ((uint32_t)0x00002000)

Definition at line 607 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC4 ((uint32_t)0x00020000)

Definition at line 611 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC5 ((uint32_t)0x00200000)

Definition at line 615 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC6 ((uint32_t)0x02000000)

Definition at line 619 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC7 ((uint32_t)0x20000000)

Definition at line 623 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE0 ((uint32_t)0x00000008)

Definition at line 597 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_TE1 ((uint32_t)0x00000080)

Definition at line 601 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE2 ((uint32_t)0x00000800)

Definition at line 605 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE3 ((uint32_t)0x00008000)

Definition at line 609 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE4 ((uint32_t)0x00080000)

Definition at line 613 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE5 ((uint32_t)0x00800000)

Definition at line 617 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE6 ((uint32_t)0x08000000)

Definition at line 621 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE7 ((uint32_t)0x80000000)

Definition at line 625 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)
Returns the current BDMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | DMA_TO_BDMA_IT(__DMA_IT__)
#define | __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
#define | __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__)
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__)
Returns the number of remaining data units in the current DMAy Streamx transfer.

Define Documentation

#define __HAL_BDMA_CHANNEL_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))

Definition at line 1062 of file stm32h7xx_hal_dma.h.

#define __HAL_BDMA_CHANNEL_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))

Definition at line 1039 of file stm32h7xx_hal_dma.h.

#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))

Definition at line 1084 of file stm32h7xx_hal_dma.h.

#define __HAL_BDMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
 (uint32_t)0x00000000)

Returns the current BDMA Channel Global interrupt flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 941 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

Clear the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
None

Definition at line 1014 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ )
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))

Disable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 674 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_SPDIFRX_DMAStop().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))

Disable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 1079 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_ENABLE ( __HANDLE__ )
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))

Enable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 665 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))

Enable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 1057 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ )
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))

Returns the number of remaining data units in the current DMAy Streamx transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Stream transfer.

Definition at line 1133 of file stm32h7xx_hal_dma.h.

Referenced by I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

#define __HAL_DMA_GET_DME_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
  (uint32_t)0x00000000)

Return the current DMA Stream direct mode error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified direct mode error flag index.

Definition at line 916 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
  (uint32_t)0x00000000)

Return the current DMA Stream FIFO error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified FIFO error flag index.

Definition at line 892 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

Get the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 986 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FS ( __HANDLE__ ) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)

Return the current DMA Stream FIFO filled level.

Parameters:
__HANDLE__,: DMA handle
Return values:
The FIFO filling state.
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  • DMA_FIFOStatus_Empty: when FIFO is empty
  • DMA_FIFOStatus_Full: when FIFO is full

Definition at line 658 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )

Return the current DMA Stream half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 755 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))

Check whether the specified DMA Stream interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
The state of DMA_IT.

Definition at line 1102 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )

Return the current DMA Stream transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 686 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )

Return the current DMA Stream transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 824 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: specifies the DMA handle.
Return values:
None

Definition at line 644 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) |
Value:
((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))

Writes the number of data units to be transferred on the DMA Stream.

Parameters:
__HANDLE__,: DMA handle
__COUNTER__,: Number of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
Note:
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
Return values:
The number of remaining data units in the current DMAy Streamx transfer.

Definition at line 1123 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_STREAM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))

Definition at line 1064 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_STREAM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))

Definition at line 1042 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_STREAM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))

Definition at line 1086 of file stm32h7xx_hal_dma.h.

#define DMA_TO_BDMA_IT ( __DMA_IT__ )
Value:
((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
 (uint32_t)0x00000000)

Definition at line 1028 of file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Stream source
    and destination incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.
    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitializes the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 436 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_CalcBaseAndBitshift(), DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR7, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, DMA_Base_Registers::IFCR, BDMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 198 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, DMA_InitTypeDef::Direction, DMA_CalcBaseAndBitshift(), DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_CheckFifoParam(), DMA_FIFOMODE_DISABLE, DMA_FIFOMODE_ENABLE, DMA_MBURST_SINGLE, DMA_MEMORY_TO_MEMORY, DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR7, DMA_REQUEST_MEM2MEM, DMA_TO_BDMA_DIRECTION, DMA_TO_BDMA_MDATA_SIZE, DMA_TO_BDMA_MEMORY_INC, DMA_TO_BDMA_MODE, DMA_TO_BDMA_PDATA_SIZE, DMA_TO_BDMA_PERIPHERAL_INC, DMA_TO_BDMA_PRIORITY, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, DMA_InitTypeDef::FIFOMode, DMA_InitTypeDef::FIFOThreshold, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, DMA_Base_Registers::IFCR, BDMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_BDMA_REQUEST, IS_DMA_DIRECTION, IS_DMA_FIFO_MODE_STATE, IS_DMA_FIFO_THRESHOLD, IS_DMA_MEMORY_BURST, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_BURST, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, IS_DMA_REQUEST, DMA_InitTypeDef::MemBurst, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphBurst, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::StreamIndex.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I/O operation functions

Functions
I/O operation functions
DMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Register and Unregister DMA callbacks
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Note:
After disabling a DMA Stream, a check for wait until the DMA Stream is effectively disabled is added. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 747 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, DMA_Base_Registers::IFCR, BDMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStop_DMA(), HAL_DCMI_Stop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DMA_PollForTransfer(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_I2S_DMAStop(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SWPMI_DMAStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 863 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_ABORT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, BDMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_DCMI_IRQHandler(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), HAL_SAI_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SWPMI_IRQHandler(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_ITError(), and PSSI_Error().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 1174 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_GET_IT_SOURCE, BDMA_FLAG_HT0, BDMA_FLAG_TC0, BDMA_FLAG_TE0, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_TE, HAL_DMA_STATE_ABORT, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CompleteLevel,: Specifies the DMA level complete.
Note:
The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. This model could be used for debug purpose.
The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
Parameters:
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 947 of file stm32h7xx_hal_dma.c.

References BDMA_FLAG_HT0, BDMA_FLAG_TC0, BDMA_FLAG_TE0, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifier a DMA_HandleTypeDef structure as parameter.
pCallback,: pointer to private callback function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 1544 of file stm32h7xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, HAL_DMA_XFER_M1CPLT_CB_ID, HAL_DMA_XFER_M1HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 591 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 647 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_IT_DME, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_DMAXferCplt(), HASH_Start_DMA(), HMAC_Start_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifier a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 1610 of file stm32h7xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, HAL_DMA_XFER_M1CPLT_CB_ID, HAL_DMA_XFER_M1HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
DMA Error Code

Definition at line 1712 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), HAL_USART_DMAStop(), I2C_DMAError(), SAI_DMAError(), and SPI_DMAError().

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Returns the DMA state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL state

Definition at line 1701 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

DMA private defines and constants. More...

Defines

#define | HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
#define | BDMA_PERIPH_TO_MEMORY (0x00000000U)
#define | BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)
#define | BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)
#define | DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__)
#define | DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
#define | DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
#define | DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
#define | DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
#define | DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
#define | DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)

Detailed Description

DMA private defines and constants.

Define Documentation

#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)

Memory to memory direction

Definition at line 132 of file stm32h7xx_hal_dma.c.

#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)

Memory to peripheral direction

Definition at line 131 of file stm32h7xx_hal_dma.c.

#define BDMA_PERIPH_TO_MEMORY (0x00000000U)

Peripheral to memory direction

Definition at line 130 of file stm32h7xx_hal_dma.c.

#define DMA_TO_BDMA_DIRECTION ( __DMA_DIRECTION__ )
Value:
(((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
                                                  ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
                                                  BDMA_PERIPH_TO_MEMORY)

Definition at line 135 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_MDATA_SIZE ( __DMA_MDATA_SIZE__ ) ((__DMA_MDATA_SIZE__) >> 3U)

Definition at line 143 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_MEMORY_INC ( __DMA_MEMORY_INC__ ) ((__DMA_MEMORY_INC__) >> 3U)

Definition at line 140 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_MODE ( __DMA_MODE__ ) ((__DMA_MODE__) >> 3U)

Definition at line 145 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_PDATA_SIZE ( __DMA_PDATA_SIZE__ ) ((__DMA_PDATA_SIZE__) >> 3U)

Definition at line 142 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_PERIPHERAL_INC ( __DMA_PERIPHERAL_INC__ ) ((__DMA_PERIPHERAL_INC__) >> 3U)

Definition at line 139 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define DMA_TO_BDMA_PRIORITY ( __DMA_PRIORITY__ ) ((__DMA_PRIORITY__) >> 4U)

Definition at line 147 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */

Definition at line 128 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Abort(), and HAL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

DMA private macros. More...

Defines

#define | IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
#define | IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Detailed Description

DMA private macros.

Define Documentation

#define IS_BDMA_REQUEST ( REQUEST ) (((REQUEST) <= BDMA_REQUEST_DFSDM2))

Definition at line 1214 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))

Definition at line 1221 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 1217 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_MODE_STATE ( STATE )
Value:
(((STATE) == DMA_FIFOMODE_DISABLE ) || \
                                       ((STATE) == DMA_FIFOMODE_ENABLE))

Definition at line 1248 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))

Definition at line 1251 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_BURST ( BURST )
Value:
(((BURST) == DMA_MBURST_SINGLE) || \
                                    ((BURST) == DMA_MBURST_INC4)   || \
                                    ((BURST) == DMA_MBURST_INC8)   || \
                                    ((BURST) == DMA_MBURST_INC16))

Definition at line 1256 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 1233 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 1226 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )           || \
                           ((MODE) == DMA_CIRCULAR)          || \
                           ((MODE) == DMA_PFCTRL)            || \
                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
                           ((MODE) == DMA_DOUBLE_BUFFER_M1))

Definition at line 1237 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_BURST ( BURST )
Value:
(((BURST) == DMA_PBURST_SINGLE) || \
                                        ((BURST) == DMA_PBURST_INC4)   || \
                                        ((BURST) == DMA_PBURST_INC8)   || \
                                        ((BURST) == DMA_PBURST_INC16))

Definition at line 1261 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 1229 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 1223 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 1243 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_REQUEST ( REQUEST ) (((REQUEST) <= DMA_REQUEST_USART10_TX))

Definition at line 1208 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

DMA private functions. More...

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
static HAL_StatusTypeDef | DMA_CheckFifoParam (DMA_HandleTypeDef *hdma)
Check compatibility between FIFO threshold level and size of the memory burst.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.

Detailed Description

DMA private functions.

Function Documentation

static uint32_t DMA_CalcBaseAndBitshift ( DMA_HandleTypeDef * hdma ) [static]

Returns the DMA Stream base address depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
Stream base address

Definition at line 1825 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXChannelBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1955 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXRequestGenBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX request generator params.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1990 of file stm32h7xx_hal_dma.c.

References DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR7, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, and DMA_InitTypeDef::Request.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static HAL_StatusTypeDef DMA_CheckFifoParam ( DMA_HandleTypeDef * hdma ) [static]

Check compatibility between FIFO threshold level and size of the memory burst.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1861 of file stm32h7xx_hal_dma.c.

References DMA_FIFO_THRESHOLD_1QUARTERFULL, DMA_FIFO_THRESHOLD_3QUARTERSFULL, DMA_FIFO_THRESHOLD_FULL, DMA_FIFO_THRESHOLD_HALFFULL, DMA_MBURST_INC16, DMA_MDATAALIGN_BYTE, DMA_MDATAALIGN_HALFWORD, DMA_InitTypeDef::FIFOThreshold, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::MemBurst, and DMA_InitTypeDef::MemDataAlignment.

Referenced by HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
None

Definition at line 1738 of file stm32h7xx_hal_dma.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_Base_Registers Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_Base_Registers Struct Reference
DMA

Data Fields

__IO uint32_t | ISR
__IO uint32_t | Reserved0
__IO uint32_t | IFCR

Detailed Description

Definition at line 110 of file stm32h7xx_hal_dma.c.

Field Documentation

__IO uint32_t DMA_Base_Registers::IFCR

DMA interrupt flag clear register

Definition at line 114 of file stm32h7xx_hal_dma.c.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), and HAL_DMA_IRQHandler().

__IO uint32_t DMA_Base_Registers::ISR

DMA interrupt status register

Definition at line 112 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_IRQHandler().

__IO uint32_t DMA_Base_Registers::Reserved0

Definition at line 113 of file stm32h7xx_hal_dma.c.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.c
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BDMA_Base_Registers Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
BDMA_Base_Registers Struct Reference
DMA

Data Fields

__IO uint32_t | ISR
__IO uint32_t | IFCR

Detailed Description

Definition at line 117 of file stm32h7xx_hal_dma.c.

Field Documentation

__IO uint32_t BDMA_Base_Registers::IFCR

BDMA interrupt flag clear register

Definition at line 120 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), and HAL_DMA_Init().

__IO uint32_t BDMA_Base_Registers::ISR

BDMA interrupt status register

Definition at line 119 of file stm32h7xx_hal_dma.c.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.c
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA2D Time Out

Defines
DMA2D Time Out
DMA2D Private Constants

Defines

#define | DMA2D_TIMEOUT_ABORT (1000U)
#define | DMA2D_TIMEOUT_SUSPEND (1000U)

Define Documentation

#define DMA2D_TIMEOUT_ABORT (1000U)

1s

Definition at line 187 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Abort(), and HAL_DMA2D_CLUTLoading_Abort().

#define DMA2D_TIMEOUT_SUSPEND (1000U)

1s

Definition at line 188 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_CLUTLoading_Suspend(), and HAL_DMA2D_Suspend().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA2D Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_RegisterCallback (DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
Register a User DMA2D Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DMA2D_UnRegisterCallback (DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
Unregister a DMA2D Callback DMA2D Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DMA2D
      (+) De-initialize the DMA2D

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_DeInit ( DMA2D_HandleTypeDef * hdma2d )

Deinitializes the DMA2D peripheral registers to their default reset values.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 311 of file stm32h7xx_hal_dma2d.c.

References __HAL_RCC_DMA2D_IS_CLK_ENABLED, HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), and HAL_DMA2D_MspDeInit().

HAL_StatusTypeDef HAL_DMA2D_Init ( DMA2D_HandleTypeDef * hdma2d )

Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 237 of file stm32h7xx_hal_dma2d.c.

References assert_param, HAL_DMA2D_CLUTLoadingCpltCallback(), HAL_DMA2D_LineEventCallback(), and HAL_DMA2D_MspInit().

__weak void HAL_DMA2D_MspDeInit ( DMA2D_HandleTypeDef * hdma2d )

DeInitializes the DMA2D MSP.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 417 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_DeInit(), and HAL_DMA2D_UnRegisterCallback().

__weak void HAL_DMA2D_MspInit ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D MSP.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 401 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init(), and HAL_DMA2D_UnRegisterCallback().

HAL_StatusTypeDef HAL_DMA2D_RegisterCallback | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | HAL_DMA2D_CallbackIDTypeDef | CallbackID,
 |  | pDMA2D_CallbackTypeDef | pCallback
 | ) |  |

Register a User DMA2D Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hdma2d | DMA2D handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
  • HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
  • HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
  • HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
  • HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
  • HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
pCallback | pointer to the Callback function
Note:
No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
Return values:
status

Definition at line 444 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | HAL_DMA2D_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a DMA2D Callback DMA2D Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hdma2d DMA2D handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
  • HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
  • HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
  • HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
  • HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
  • HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
Note:
No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
Return values:
status

Definition at line 541 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_CLUTLoadingCpltCallback(), HAL_DMA2D_LineEventCallback(), HAL_DMA2D_MspDeInit(), and HAL_DMA2D_MspInit().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
DMA2D Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad_IT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Abort (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Suspend (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Resume (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
__weak void | HAL_DMA2D_LineEventCallback (DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
__weak void | HAL_DMA2D_CLUTLoadingCpltCallback (DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the pdata, destination address and data size then
          start the DMA2D transfer.
      (+) Configure the source for foreground and background, destination address
          and data size then start a MultiBuffer DMA2D transfer.
      (+) Configure the pdata, destination address and data size then
          start the DMA2D transfer with interrupt.
      (+) Configure the source for foreground and background, destination address
          and data size then start a MultiBuffer DMA2D transfer with interrupt.
      (+) Abort DMA2D transfer.
      (+) Suspend DMA2D transfer.
      (+) Resume DMA2D transfer.
      (+) Enable CLUT transfer.
      (+) Configure CLUT loading then start transfer in polling mode.
      (+) Configure CLUT loading then start transfer in interrupt mode.
      (+) Abort DMA2D CLUT loading.
      (+) Suspend DMA2D CLUT loading.
      (+) Resume DMA2D CLUT loading.
      (+) Poll for transfer complete.
      (+) handle DMA2D interrupt request.
      (+) Transfer watermark callback.
      (+) CLUT Transfer Complete callback.

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_Abort ( DMA2D_HandleTypeDef * hdma2d )

Abort the DMA2D Transfer.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 841 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_ABORT, and HAL_GetTick().

Referenced by HAL_DMA2D_DeInit().

HAL_StatusTypeDef HAL_DMA2D_BlendingStart | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1 | The source memory Buffer address for the foreground layer.
SrcAddress2 | The source memory Buffer address for the background layer.
DstAddress | The destination memory Buffer address.
Width | The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height | The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 740 of file stm32h7xx_hal_dma2d.c.

References assert_param, and DMA2D_SetConfig().

HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1 | The source memory Buffer address for the foreground layer.
SrcAddress2 | The source memory Buffer address for the background layer.
DstAddress | The destination memory Buffer address.
Width | The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height | The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 792 of file stm32h7xx_hal_dma2d.c.

References assert_param, and DMA2D_SetConfig().

HAL_StatusTypeDef HAL_DMA2D_CLUTLoad | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Start DMA2D CLUT Loading.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg | Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Note:
Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
Return values:
HAL status

Definition at line 1005 of file stm32h7xx_hal_dma2d.c.

References assert_param.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Start DMA2D CLUT Loading with interrupt enabled.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg | Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1059 of file stm32h7xx_hal_dma2d.c.

References assert_param.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Abort the DMA2D CLUT loading.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1117 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_ABORT, and HAL_GetTick().

Referenced by HAL_DMA2D_DeInit().

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Resume the DMA2D CLUT loading.

Parameters:
hdma2d | pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1235 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Suspend the DMA2D CLUT loading.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1174 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_SUSPEND, and HAL_GetTick().

__weak void HAL_DMA2D_CLUTLoadingCpltCallback ( DMA2D_HandleTypeDef * hdma2d )

CLUT Transfer Complete callback.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 1592 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_UnRegisterCallback().

HAL_StatusTypeDef HAL_DMA2D_EnableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the DMA2D CLUT Transfer.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 967 of file stm32h7xx_hal_dma2d.c.

References assert_param.

void HAL_DMA2D_IRQHandler ( DMA2D_HandleTypeDef * hdma2d )

Handle DMA2D interrupt request.

Parameters:
hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 1406 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_CLUTLoadingCpltCallback(), and HAL_DMA2D_LineEventCallback().

__weak void HAL_DMA2D_LineEventCallback ( DMA2D_HandleTypeDef * hdma2d )

Transfer watermark callback.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 1576 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_UnRegisterCallback().

HAL_StatusTypeDef HAL_DMA2D_PollForTransfer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete or CLUT loading.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1278 of file stm32h7xx_hal_dma2d.c.

References HAL_GetTick().

HAL_StatusTypeDef HAL_DMA2D_Resume ( DMA2D_HandleTypeDef * hdma2d )

Resume the DMA2D Transfer.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 939 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_Start | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata | Configure the source memory Buffer address if Memory-to-Memory or Memory-to-Memory with pixel format conversion mode is selected, or configure the color value if Register-to-Memory mode is selected.
DstAddress | The destination memory Buffer address.
Width | The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height | The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 671 of file stm32h7xx_hal_dma2d.c.

References assert_param, and DMA2D_SetConfig().

HAL_StatusTypeDef HAL_DMA2D_Start_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata | Configure the source memory Buffer address if the Memory-to-Memory or Memory-to-Memory with pixel format conversion mode is selected, or configure the color value if Register-to-Memory mode is selected.
DstAddress | The destination memory Buffer address.
Width | The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height | The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 705 of file stm32h7xx_hal_dma2d.c.

References assert_param, and DMA2D_SetConfig().

HAL_StatusTypeDef HAL_DMA2D_Suspend ( DMA2D_HandleTypeDef * hdma2d )

Suspend the DMA2D Transfer.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 890 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_SUSPEND, and HAL_GetTick().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DMA2D Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_HandleTypeDef.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
HAL_StatusTypeDef | HAL_DMA2D_EnableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_DisableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_ConfigDeadTime (DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the DMA2D foreground or background layer parameters.
      (+) Configure the DMA2D CLUT transfer.
      (+) Configure the line watermark
      (+) Configure the dead time value.
      (+) Enable or disable the dead time value functionality.

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D CLUT Transfer.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg | Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1739 of file stm32h7xx_hal_dma2d.c.

References assert_param.

HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint8_t | DeadTime
 | ) |  |

Configure dead time.

Note:
The dead time value represents the guaranteed minimum number of cycles between two consecutive transactions on the AHB bus.
Parameters:
hdma2d | DMA2D handle.
DeadTime | dead time value.
Return values:
HAL status

Definition at line 1880 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_ConfigLayer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D Layer according to the specified parameters in the DMA2D_HandleTypeDef.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
Return values:
HAL status

Definition at line 1635 of file stm32h7xx_hal_dma2d.c.

References assert_param.

HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime ( DMA2D_HandleTypeDef * hdma2d )

Disable DMA2D dead time feature.

Parameters:
hdma2d DMA2D handle.
Return values:
HAL status

Definition at line 1854 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime ( DMA2D_HandleTypeDef * hdma2d )

Enable DMA2D dead time feature.

Parameters:
hdma2d DMA2D handle.
Return values:
HAL status

Definition at line 1831 of file stm32h7xx_hal_dma2d.c.

HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Line
 | ) |  |

Configure the line watermark.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Line | Line Watermark configuration (maximum 16-bit long value expected).
Note:
HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
The transfer watermark interrupt is disabled once it has occurred.
Return values:
HAL status

Definition at line 1793 of file stm32h7xx_hal_dma2d.c.

References assert_param.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
DMA2D Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                  ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to:
      (+) Get the DMA2D state
      (+) Get the DMA2D error code

Function Documentation

uint32_t HAL_DMA2D_GetError ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D error code.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for DMA2D.
Return values:
DMA2D Error Code

Definition at line 1936 of file stm32h7xx_hal_dma2d.c.

HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D state.

Parameters:
hdma2d pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL state

Definition at line 1925 of file stm32h7xx_hal_dma2d.c.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA2D Private Functions

Functions
DMA2D Private Functions
DMA2D

Functions

static void DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D transfer parameters.

Function Documentation

static void DMA2D_SetConfig | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  | [static]

Set the DMA2D transfer parameters.

Parameters:
hdma2d | Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the specified DMA2D.
pdata | The source memory Buffer address
DstAddress | The destination memory Buffer address
Width | The width of data to be transferred from source to destination.
Height | The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 1964 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx Exported Types

Data Structures | Enumerations
DMAEx Exported Types
DMAEx

DMAEx Exported types. More...

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Detailed Description

DMAEx Exported types.

Enumeration Type Documentation

enum HAL_DMA_MemoryTypeDef

HAL DMA Memory definition.

Enumerator:
MEMORY0

Memory 0

MEMORY1

Memory 1

Definition at line 48 of file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_DMA_MuxSyncConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxSyncConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX Synchronization configuration structure definition. More...

#include <stm32h7xx_hal_dma_ex.h>

Data Fields

uint32_t | SyncSignalID
uint32_t | SyncPolarity
FunctionalState | SyncEnable
FunctionalState | EventEnable
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX Synchronization configuration structure definition.

Definition at line 58 of file stm32h7xx_hal_dma_ex.h.

Field Documentation

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::EventEnable

Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE

Definition at line 70 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be authorized after a sync event. This parameters can be in the range 1 to 32

Definition at line 73 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::SyncEnable

Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE

Definition at line 66 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity

Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of DMAEx MUX SyncPolarity selection

Definition at line 63 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID

Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of DMAEx MUX SyncSignalID selection

Definition at line 60 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma_ex.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX request generator parameters structure definition. More...

#include <stm32h7xx_hal_dma_ex.h>

Data Fields

uint32_t | SignalID
uint32_t | Polarity
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX request generator parameters structure definition.

Definition at line 82 of file stm32h7xx_hal_dma_ex.h.

Field Documentation

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity

Specifies the polarity of the signal on which the request is generated. This parameter can be a value of DMAEx MUX RequestGeneneratorPolarity selection

Definition at line 87 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be generated after a signal event. This parameters can be in the range 1 to 32

Definition at line 90 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID

Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMAEx MUX SignalGeneratorID selection

Definition at line 84 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma_ex.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx MUX SyncSignalID selection

Defines
DMAEx MUX SyncSignalID selection
DMA Exported Constants

DMAEx MUX SyncSignalID selection. More...

Defines

#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U
#define | HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U
#define | HAL_DMAMUX1_SYNC_EXTI0 6U
#define | HAL_DMAMUX1_SYNC_TIM12_TRGO 7U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U
#define | HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U
#define | HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U
#define | HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U
#define | HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U
#define | HAL_DMAMUX2_SYNC_I2C4_WKUP 10U
#define | HAL_DMAMUX2_SYNC_SPI6_WKUP 11U
#define | HAL_DMAMUX2_SYNC_COMP1_OUT 12U
#define | HAL_DMAMUX2_SYNC_RTC_WKUP 13U
#define | HAL_DMAMUX2_SYNC_EXTI0 14U
#define | HAL_DMAMUX2_SYNC_EXTI2 15U

Detailed Description

DMAEx MUX SyncSignalID selection.

Define Documentation

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U

DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event

Definition at line 110 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U

DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event

Definition at line 111 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U

DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event

Definition at line 112 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI0 6U

DMAMUX1 synchronization Signal is EXTI0 IT

Definition at line 116 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U

DMAMUX1 synchronization Signal is LPTIM1 OUT

Definition at line 113 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U

DMAMUX1 synchronization Signal is LPTIM2 OUT

Definition at line 114 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U

DMAMUX1 synchronization Signal is LPTIM3 OUT

Definition at line 115 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U

DMAMUX1 synchronization Signal is TIM12 TRGO

Definition at line 117 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U

DMAMUX2 synchronization Signal is Comparator 1 output

Definition at line 131 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U

DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event

Definition at line 119 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U

DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event

Definition at line 120 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U

DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event

Definition at line 121 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U

DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event

Definition at line 122 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U

DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event

Definition at line 123 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U

DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event

Definition at line 124 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_EXTI0 14U

DMAMUX2 synchronization Signal is EXTI0 IT

Definition at line 133 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_EXTI2 15U

DMAMUX2 synchronization Signal is EXTI2 IT

Definition at line 134 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U

DMAMUX2 synchronization Signal is I2C4 Wakeup

Definition at line 129 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U

DMAMUX2 synchronization Signal is LPTIM2 output

Definition at line 127 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U

DMAMUX2 synchronization Signal is LPTIM3 output

Definition at line 128 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U

DMAMUX2 synchronization Signal is LPUART1 RX Wakeup

Definition at line 125 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U

DMAMUX2 synchronization Signal is LPUART1 TX Wakeup

Definition at line 126 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U

DMAMUX2 synchronization Signal is RTC Wakeup

Definition at line 132 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U

DMAMUX2 synchronization Signal is SPI6 Wakeup

Definition at line 130 of file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx MUX SyncPolarity selection

Defines
DMAEx MUX SyncPolarity selection
DMA Exported Constants

DMAEx MUX SyncPolarity selection. More...

Defines

#define | HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0
#define | HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1
#define | HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL

Detailed Description

DMAEx MUX SyncPolarity selection.

Define Documentation

#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1

synchronize with falling edge events

Definition at line 146 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U

block synchronization events

Definition at line 144 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0

synchronize with rising edge events

Definition at line 145 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL

synchronize with rising and falling edge events

Definition at line 147 of file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx MUX SignalGeneratorID selection

Defines
DMAEx MUX SignalGeneratorID selection
DMA Exported Constants

DMAEx MUX SignalGeneratorID selection. More...

Defines

#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
#define | HAL_DMAMUX1_REQ_GEN_EXTI0 6U
#define | HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
#define | HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
#define | HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
#define | HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
#define | HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
#define | HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
#define | HAL_DMAMUX2_REQ_GEN_EXTI0 20U
#define | HAL_DMAMUX2_REQ_GEN_EXTI2 21U
#define | HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
#define | HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
#define | HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
#define | HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U

Detailed Description

DMAEx MUX SignalGeneratorID selection.

Define Documentation

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U

DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event

Definition at line 158 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U

DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event

Definition at line 159 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U

DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event

Definition at line 160 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U

DMAMUX1 Request generator Signal is EXTI0 IT

Definition at line 164 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U

DMAMUX1 Request generator Signal is LPTIM1 OUT

Definition at line 161 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U

DMAMUX1 Request generator Signal is LPTIM2 OUT

Definition at line 162 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U

DMAMUX1 Request generator Signal is LPTIM3 OUT

Definition at line 163 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U

DMAMUX1 Request generator Signal is TIM12 TRGO

Definition at line 165 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U

DMAMUX2 Request generator Signal is BDMA Channel 0 IT

Definition at line 201 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U

DMAMUX2 Request generator Signal is BDMA Channel 1 IT

Definition at line 202 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U

DMAMUX2 Request generator Signal is Comparator 1 output

Definition at line 188 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U

DMAMUX2 Request generator Signal is Comparator 2 output

Definition at line 189 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U

DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event

Definition at line 167 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U

DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event

Definition at line 168 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U

DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event

Definition at line 169 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U

DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event

Definition at line 170 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U

DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event

Definition at line 171 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U

DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event

Definition at line 172 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U

DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event

Definition at line 173 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U

DMAMUX2 Request generator Signal is EXTI0

Definition at line 191 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U

DMAMUX2 Request generator Signal is EXTI2

Definition at line 192 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U

DMAMUX2 Request generator Signal is I2C4 IT Event

Definition at line 193 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U

DMAMUX2 Request generator Signal is I2C4 Wakeup

Definition at line 186 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U

DMAMUX2 Request generator Signal is LPTIM2 OUT

Definition at line 177 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U

DMAMUX2 Request generator Signal is LPTIM2 Wakeup

Definition at line 176 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U

DMAMUX2 Request generator Signal is LPTIM3 OUT

Definition at line 179 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U

DMAMUX2 Request generator Signal is LPTIM3 Wakeup

Definition at line 178 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U

DMAMUX2 Request generator Signal is LPUART1 Rx IT

Definition at line 196 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U

DMAMUX2 Request generator Signal is LPUART1 RX Wakeup

Definition at line 174 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U

DMAMUX2 Request generator Signal is LPUART1 Tx IT

Definition at line 195 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U

DMAMUX2 Request generator Signal is LPUART1 TX Wakeup

Definition at line 175 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U

DMAMUX2 Request generator Signal is RTC Wakeup

Definition at line 190 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U

DMAMUX2 Request generator Signal is SPI6 IT

Definition at line 194 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U

DMAMUX2 Request generator Signal is SPI6 Wakeup

Definition at line 187 of file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx MUX RequestGeneneratorPolarity selection

Defines
DMAEx MUX RequestGeneneratorPolarity selection
DMA Exported Constants

DMAEx MUX RequestGeneneratorPolarity selection. More...

Defines

#define | HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
#define | HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL

Detailed Description

DMAEx MUX RequestGeneneratorPolarity selection.

Define Documentation

#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1

generate request on falling edge events

Definition at line 215 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

block request generator events

Definition at line 213 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0

generate request on rising edge events

Definition at line 214 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL

generate request on rising and falling edge events

Definition at line 216 of file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended features functions

Functions
Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer with interrupt
      (+) Change on the fly the memory0 or memory1 address.
      (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
      (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
      (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
          to respectively enable/disable the request generator.
      (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
          the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ChangeMemory | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | Address,
 |  | HAL_DMA_MemoryTypeDef | memory
 | ) |  |

Change the memory0 or memory1 address on the fly.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Address,: The new address
memory,: the memory to be changed, This parameter can be one of the following values: MEMORY0 / MEMORY1
Note:
The MEMORY0 address can be changed only when the current transfer use MEMORY1 and the MEMORY1 address can be changed only when the current transfer use MEMORY0.
Return values:
HAL status

Definition at line 358 of file stm32h7xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::Instance, and MEMORY0.

Referenced by DCMI_DMAXferCplt().

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxRequestGeneratorConfigTypeDef * | pRequestGeneratorConfig
 | ) |  |

Configure the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator parameters.
Return values:
HAL status

Definition at line 465 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_PARAM, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID, IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID, IS_DMAMUX_REQUEST_GEN_POLARITY, IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER, HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity, HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber, HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxSyncConfigTypeDef * | pSyncConfig
 | ) |  |

Configure the DMAMUX synchronization parameters for a given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
Return values:
HAL status

Definition at line 397 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_MuxSyncConfigTypeDef::EventEnable, HAL_DMA_ERROR_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_BDMA_DMAMUX_SYNC_SIGNAL_ID, IS_DMA_DMAMUX_SYNC_SIGNAL_ID, IS_DMAMUX_SYNC_EVENT, IS_DMAMUX_SYNC_POLARITY, IS_DMAMUX_SYNC_REQUEST_NUMBER, IS_DMAMUX_SYNC_STATE, HAL_DMA_MuxSyncConfigTypeDef::RequestNumber, __DMA_HandleTypeDef::State, HAL_DMA_MuxSyncConfigTypeDef::SyncEnable, HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity, and HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID.

HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Disable the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 557 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Enable the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 531 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 121 of file stm32h7xx_hal_dma_ex.c.

References __HAL_DMA_ENABLE, assert_param, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_MEMORY, DMA_MultiBufferSetConfig(), __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 218 of file stm32h7xx_hal_dma_ex.c.

References __HAL_DMA_ENABLE, assert_param, DMA_InitTypeDef::Direction, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_MEMORY_TO_MEMORY, DMA_MultiBufferSetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferHalfCpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

Referenced by HAL_DCMI_Start_DMA().

void HAL_DMAEx_MUX_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMAMUX interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 583 of file stm32h7xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMAEx

DMAEx private macros. More...

Defines

#define | IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
#define | IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
#define | IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Detailed Description

DMAEx private macros.

Define Documentation

#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)

Definition at line 276 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)

Definition at line 261 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)

Definition at line 275 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)

Definition at line 260 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_REQUEST_GEN_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))

Definition at line 280 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 278 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_SYNC_EVENT ( EVENT )
Value:
(((EVENT) == DISABLE)   || \
                                     ((EVENT) == ENABLE))

Definition at line 272 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

Definition at line 265 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 263 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_STATE ( SYNC ) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))

Definition at line 270 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAEx Private Functions

Functions
DMAEx Private Functions
DMAEx

DMAEx Private functions. More...

Functions

static void DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.

Detailed Description

DMAEx Private functions.

Function Documentation

static void DMA_MultiBufferSetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Set the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 649 of file stm32h7xx_hal_dma_ex.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
DTS Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DTS_Init (DTS_HandleTypeDef *hdts)
Initialize the DTS according to the specified parameters in the DTS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DTS_DeInit (DTS_HandleTypeDef *hdts)
DeInitialize the DTS peripheral.
__weak void | HAL_DTS_MspInit (DTS_HandleTypeDef *hdts)
Initialize the DTS MSP.
__weak void | HAL_DTS_MspDeInit (DTS_HandleTypeDef *hdts)
DeInitialize the DTS MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_DTS_DeInit ( DTS_HandleTypeDef * hdts )

DeInitialize the DTS peripheral.

Note:
Deinitialization cannot be performed if the DTS configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 214 of file stm32h7xx_hal_dts.c.

References assert_param, and HAL_DTS_MspDeInit().

HAL_StatusTypeDef HAL_DTS_Init ( DTS_HandleTypeDef * hdts )

Initialize the DTS according to the specified parameters in the DTS_InitTypeDef and initialize the associated handle.

Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 110 of file stm32h7xx_hal_dts.c.

References assert_param, DTS_ResetCallback(), and HAL_DTS_MspInit().

__weak void HAL_DTS_MspDeInit ( DTS_HandleTypeDef * hdts )

DeInitialize the DTS MSP.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 266 of file stm32h7xx_hal_dts.c.

Referenced by HAL_DTS_DeInit().

__weak void HAL_DTS_MspInit ( DTS_HandleTypeDef * hdts )

Initialize the DTS MSP.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 251 of file stm32h7xx_hal_dts.c.

Referenced by HAL_DTS_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
DTS Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DTS_Start (DTS_HandleTypeDef *hdts)
Start the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_Stop (DTS_HandleTypeDef *hdts)
Stop the DTS Sensor.
HAL_StatusTypeDef | HAL_DTS_Start_IT (DTS_HandleTypeDef *hdts)
Enable the interrupt(s) and start the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_Stop_IT (DTS_HandleTypeDef *hdts)
Disable the interrupt(s) and stop the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_GetTemperature (DTS_HandleTypeDef *hdts, int32_t *Temperature)
Get temperature from DTS.
void | HAL_DTS_IRQHandler (DTS_HandleTypeDef *hdts)
DTS sensor IRQ Handler.
__weak void | HAL_DTS_EndCallback (DTS_HandleTypeDef *hdts)
DTS Sensor End measure callback.
__weak void | HAL_DTS_LowCallback (DTS_HandleTypeDef *hdts)
DTS Sensor low threshold measure callback.
__weak void | HAL_DTS_HighCallback (DTS_HandleTypeDef *hdts)
DTS Sensor high threshold measure callback.
__weak void | HAL_DTS_AsyncEndCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous end measure callback.
__weak void | HAL_DTS_AsyncLowCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous low threshold measure callback.
__weak void | HAL_DTS_AsyncHighCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous high threshold measure callback.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### DTS Start Stop operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a DTS Sensor without interrupt.
      (+) Stop a DTS Sensor without interrupt.
      (+) Start a DTS Sensor with interrupt generation.
      (+) Stop a DTS Sensor with interrupt generation.

Function Documentation

__weak void HAL_DTS_AsyncEndCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor asynchronous end measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 702 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

__weak void HAL_DTS_AsyncHighCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor asynchronous high threshold measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 732 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

__weak void HAL_DTS_AsyncLowCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor asynchronous low threshold measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 717 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

__weak void HAL_DTS_EndCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor End measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 657 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

HAL_StatusTypeDef HAL_DTS_GetTemperature | ( | DTS_HandleTypeDef * | hdts,
 |  | int32_t * | Temperature
 | ) |  |

Get temperature from DTS.

Parameters:
hdts | DTS handle
Temperature | Temperature in deg C
Note:
This function retrieves latest available measure
Return values:
HAL status

Definition at line 502 of file stm32h7xx_hal_dts.c.

References HAL_RCCEx_GetD3PCLK1Freq(), and LSE_VALUE.

__weak void HAL_DTS_HighCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor high threshold measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 687 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

void HAL_DTS_IRQHandler ( DTS_HandleTypeDef * hdts )

DTS sensor IRQ Handler.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 577 of file stm32h7xx_hal_dts.c.

References HAL_DTS_AsyncEndCallback(), HAL_DTS_AsyncHighCallback(), HAL_DTS_AsyncLowCallback(), HAL_DTS_EndCallback(), HAL_DTS_HighCallback(), and HAL_DTS_LowCallback().

__weak void HAL_DTS_LowCallback ( DTS_HandleTypeDef * hdts )

DTS Sensor low threshold measure callback.

Parameters:
hdts DTS handle
Return values:
None

Definition at line 672 of file stm32h7xx_hal_dts.c.

Referenced by DTS_ResetCallback(), and HAL_DTS_IRQHandler().

HAL_StatusTypeDef HAL_DTS_Start ( DTS_HandleTypeDef * hdts )

Start the DTS sensor.

Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 302 of file stm32h7xx_hal_dts.c.

References DTS_DELAY_STARTUP, HAL_Delay(), HAL_GetTick(), and TS_TIMEOUT_MS.

HAL_StatusTypeDef HAL_DTS_Start_IT ( DTS_HandleTypeDef * hdts )

Enable the interrupt(s) and start the DTS sensor.

Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 390 of file stm32h7xx_hal_dts.c.

References DTS_DELAY_STARTUP, HAL_Delay(), HAL_GetTick(), and TS_TIMEOUT_MS.

HAL_StatusTypeDef HAL_DTS_Stop ( DTS_HandleTypeDef * hdts )

Stop the DTS Sensor.

Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 355 of file stm32h7xx_hal_dts.c.

HAL_StatusTypeDef HAL_DTS_Stop_IT ( DTS_HandleTypeDef * hdts )

Disable the interrupt(s) and stop the DTS sensor.

Parameters:
hdts DTS handle
Return values:
HAL status

Definition at line 454 of file stm32h7xx_hal_dts.c.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DTS Exported Functions

Peripheral State functions. More...

Functions

HAL_DTS_StateTypeDef HAL_DTS_GetState (DTS_HandleTypeDef *hdts)
Return the DTS handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_DTS_StateTypeDef HAL_DTS_GetState ( DTS_HandleTypeDef * hdts )

Return the DTS handle state.

Parameters:
hdts DTS handle
Return values:
HAL state

Definition at line 765 of file stm32h7xx_hal_dts.c.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DTS Private Functions

Functions
DTS Private Functions
DTS_Private_Constants

Functions

static void DTS_ResetCallback (DTS_HandleTypeDef *hdts)
Reset interrupt callbacks to the legacy weak callbacks.

Function Documentation

static void DTS_ResetCallback ( DTS_HandleTypeDef * hdts ) [static]

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
hdts pointer to a DTS_HandleTypeDef structure that contains the configuration information for DTS module.
Return values:
None

Definition at line 796 of file stm32h7xx_hal_dts.c.

References HAL_DTS_AsyncEndCallback(), HAL_DTS_AsyncHighCallback(), HAL_DTS_AsyncLowCallback(), HAL_DTS_EndCallback(), HAL_DTS_HighCallback(), and HAL_DTS_LowCallback().

Referenced by HAL_DTS_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DTS_Private_Constants

Modules | Defines
DTS_Private_Constants
DTS

Modules

DTS Exported Functions
DTS Private Functions

Defines

#define | DTS_DELAY_STARTUP (1UL)
#define | TS_TIMEOUT_MS (5UL)

Define Documentation

#define DTS_DELAY_STARTUP (1UL)

Definition at line 69 of file stm32h7xx_hal_dts.c.

Referenced by HAL_DTS_Start(), and HAL_DTS_Start_IT().

#define TS_TIMEOUT_MS (5UL)

Definition at line 77 of file stm32h7xx_hal_dts.c.

Referenced by HAL_DTS_Start(), and HAL_DTS_Start_IT().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Private Constants

Defines
EXTI Private Constants
EXTI

Defines

#define | EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */
#define | EXTI_PROPERTY_SHIFT 24U
EXTI Line property definition.
#define | EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_EVENT_PRESENCE_SHIFT 28U
EXTI Event presence definition.
#define | EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
#define | EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
#define | EXTI_REG_SHIFT 16U
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00UL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01UL << EXTI_REG_SHIFT)
#define | EXTI_REG3 (0x02UL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
#define | EXTI_PIN_MASK 0x0000001FUL
#define | EXTI_TARGET_SHIFT 20U
EXTI Target and bit usage.
#define | EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
#define | EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1
#define | EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 89UL
EXTI Line number.

Define Documentation

#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT)

Definition at line 325 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */

Definition at line 139 of file stm32h7xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT)

Definition at line 324 of file stm32h7xx_hal_exti.h.

#define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)

Definition at line 334 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)

Definition at line 335 of file stm32h7xx_hal_exti.h.

#define EXTI_EVENT_PRESENCE_SHIFT 28U

EXTI Event presence definition.

Definition at line 333 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

Definition at line 326 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_LINE_NB 89UL

EXTI Line number.

Definition at line 382 of file stm32h7xx_hal_exti.h.

#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)

EXTI Mask for interrupt & event mode.

Definition at line 370 of file stm32h7xx_hal_exti.h.

#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */

Definition at line 138 of file stm32h7xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_PIN_MASK 0x0000001FUL

Definition at line 345 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)

Definition at line 328 of file stm32h7xx_hal_exti.h.

#define EXTI_PROPERTY_SHIFT 24U

EXTI Line property definition.

Definition at line 323 of file stm32h7xx_hal_exti.h.

#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT)

Definition at line 341 of file stm32h7xx_hal_exti.h.

#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT)

Definition at line 342 of file stm32h7xx_hal_exti.h.

#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT)

Definition at line 343 of file stm32h7xx_hal_exti.h.

#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)

Definition at line 344 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_REG_SHIFT 16U

EXTI Register and bit usage.

Definition at line 340 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT)

Definition at line 327 of file stm32h7xx_hal_exti.h.

#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)

Definition at line 359 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK

Definition at line 362 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1

Definition at line 360 of file stm32h7xx_hal_exti.h.

#define EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT)

Definition at line 353 of file stm32h7xx_hal_exti.h.

#define EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT)

Definition at line 352 of file stm32h7xx_hal_exti.h.

#define EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT)

Definition at line 351 of file stm32h7xx_hal_exti.h.

#define EXTI_TARGET_SHIFT 20U

EXTI Target and bit usage.

Definition at line 350 of file stm32h7xx_hal_exti.h.

#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

EXTI Mask for trigger possibilities.

Definition at line 376 of file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Exported Types

Data Structures | Enumerations
EXTI Exported Types
EXTI

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U }

Enumeration Type Documentation

enum EXTI_CallbackIDTypeDef
Enumerator:
HAL_EXTI_COMMON_CB_ID

Definition at line 45 of file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_HandleTypeDef Struct Reference
EXTI Exported Types

EXTI Handle structure definition. More...

#include <stm32h7xx_hal_exti.h>

Data Fields

uint32_t | Line
void(* | PendingCallback )(void)

Detailed Description

EXTI Handle structure definition.

Definition at line 54 of file stm32h7xx_hal_exti.h.

Field Documentation

uint32_t EXTI_HandleTypeDef::Line

Exti line number

Definition at line 56 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

void(* EXTI_HandleTypeDef::PendingCallback)(void)

Exti pending callback

Definition at line 57 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_IRQHandler(), and HAL_EXTI_RegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_exti.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_ConfigTypeDef Struct Reference
EXTI Exported Types

EXTI Configuration structure definition. More...

#include <stm32h7xx_hal_exti.h>

Data Fields

uint32_t | Line
uint32_t | Mode
uint32_t | Trigger
uint32_t | GPIOSel
uint32_t | PendClearSource

Detailed Description

EXTI Configuration structure definition.

Definition at line 63 of file stm32h7xx_hal_exti.h.

Field Documentation

uint32_t EXTI_ConfigTypeDef::GPIOSel

The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of EXTI GPIOSel

Definition at line 71 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Line

The Exti line to be configured. This parameter can be a value of EXTI Line

Definition at line 65 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Mode

The Exit Mode to be configured for a core. This parameter can be a combination of EXTI Mode

Definition at line 67 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::PendClearSource

Specifies the event pending clear source for D3/SRD domain. This parameter can be a value of EXTI PendClear Source

Definition at line 75 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Trigger

The Exti Trigger to be configured. This parameter can be a value of EXTI Trigger

Definition at line 69 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_exti.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Line

Defines
EXTI Line
EXTI Exported Constants

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
#define | EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
#define | EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
#define | EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
#define | EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
#define | EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
#define | EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
#define | EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define | EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#define | EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU)
#define | EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU)
#define | EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU)
#define | EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
#define | EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U)
#define | EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)
#define | EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)
#define | EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)
#define | EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
#define | EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#define | EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define | EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
#define | EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
#define | EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#define | EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#define | EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define | EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define | EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
#define | EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
#define | EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
#define | EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
#define | EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
#define | EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
#define | EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
#define | EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
#define | EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
#define | EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
#define | EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define | EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
#define | EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define | EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU)
#define | EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU)
#define | EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
#define | EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#define | EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
#define | EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#define | EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
#define | EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
#define | EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#define | EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
#define | EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#define | EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
#define | EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)

Define Documentation

#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U)

Definition at line 93 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U)

Definition at line 94 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU)

Definition at line 103 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU)

Definition at line 104 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU)

Definition at line 105 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU)

Definition at line 106 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU)

Definition at line 107 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU)

Definition at line 108 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)

Definition at line 109 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)

Definition at line 110 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)

Definition at line 111 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U)

Definition at line 112 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U)

Definition at line 95 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U)

Definition at line 113 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U)

Definition at line 114 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)

Definition at line 115 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

Definition at line 116 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)

Definition at line 117 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U)

Definition at line 118 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)

Definition at line 119 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)

Definition at line 120 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)

Definition at line 121 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)

Definition at line 122 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U)

Definition at line 96 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)

Definition at line 123 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)

Definition at line 124 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)

Definition at line 125 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)

Definition at line 126 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U)

Definition at line 127 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U)

Definition at line 128 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)

Definition at line 129 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)

Definition at line 130 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)

Definition at line 131 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)

Definition at line 132 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U)

Definition at line 97 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)

Definition at line 133 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U)

Definition at line 134 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)

Definition at line 135 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)

Definition at line 136 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU)

Definition at line 138 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU)

Definition at line 142 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU)

Definition at line 146 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)

Definition at line 148 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U)

Definition at line 149 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)

Definition at line 150 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U)

Definition at line 98 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)

Definition at line 151 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)

Definition at line 152 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)

Definition at line 156 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)

Definition at line 161 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)

Definition at line 163 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

Definition at line 164 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)

Definition at line 165 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)

Definition at line 166 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)

Definition at line 167 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)

Definition at line 168 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U)

Definition at line 99 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)

Definition at line 169 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)

Definition at line 170 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)

Definition at line 171 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)

Definition at line 172 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)

Definition at line 173 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)

Definition at line 174 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)

Definition at line 175 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)

Definition at line 176 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)

Definition at line 177 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)

Definition at line 178 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U)

Definition at line 100 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)

Definition at line 179 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)

Definition at line 180 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)

Definition at line 181 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)

Definition at line 182 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)

Definition at line 183 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU)

Definition at line 187 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU)

Definition at line 192 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)

Definition at line 200 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)

Definition at line 201 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)

Definition at line 202 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U)

Definition at line 101 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)

Definition at line 203 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)

Definition at line 206 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)

Definition at line 211 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)

Definition at line 214 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)

Definition at line 218 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)

Definition at line 220 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)

Definition at line 224 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

Definition at line 226 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)

Definition at line 228 of file stm32h7xx_hal_exti.h.

#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U)

Definition at line 102 of file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Mode

Defines
EXTI Mode
EXTI Exported Constants

Defines

#define | EXTI_MODE_NONE 0x00000000U
#define | EXTI_MODE_INTERRUPT 0x00000001U
#define | EXTI_MODE_EVENT 0x00000002U

Define Documentation

#define EXTI_MODE_EVENT 0x00000002U

Definition at line 240 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_INTERRUPT 0x00000001U

Definition at line 239 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_NONE 0x00000000U

Definition at line 238 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Trigger

Defines
EXTI Trigger
EXTI Exported Constants

Defines

#define | EXTI_TRIGGER_NONE 0x00000000U
#define | EXTI_TRIGGER_RISING 0x00000001U
#define | EXTI_TRIGGER_FALLING 0x00000002U
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Define Documentation

#define EXTI_TRIGGER_FALLING 0x00000002U

Definition at line 256 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_NONE 0x00000000U

Definition at line 254 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

#define EXTI_TRIGGER_RISING 0x00000001U

Definition at line 255 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Definition at line 257 of file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI GPIOSel

Defines
EXTI GPIOSel
EXTI Exported Constants

Defines

#define | EXTI_GPIOA 0x00000000U
#define | EXTI_GPIOB 0x00000001U
#define | EXTI_GPIOC 0x00000002U
#define | EXTI_GPIOD 0x00000003U
#define | EXTI_GPIOE 0x00000004U
#define | EXTI_GPIOF 0x00000005U
#define | EXTI_GPIOG 0x00000006U
#define | EXTI_GPIOH 0x00000007U
#define | EXTI_GPIOI 0x00000008U
#define | EXTI_GPIOJ 0x00000009U
#define | EXTI_GPIOK 0x0000000AU

Define Documentation

#define EXTI_GPIOA 0x00000000U

Definition at line 266 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOB 0x00000001U

Definition at line 267 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOC 0x00000002U

Definition at line 268 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOD 0x00000003U

Definition at line 269 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOE 0x00000004U

Definition at line 270 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOF 0x00000005U

Definition at line 271 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOG 0x00000006U

Definition at line 272 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOH 0x00000007U

Definition at line 273 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOI 0x00000008U

Definition at line 274 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOJ 0x00000009U

Definition at line 275 of file stm32h7xx_hal_exti.h.

#define EXTI_GPIOK 0x0000000AU

Definition at line 276 of file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI PendClear Source

Defines
EXTI PendClear Source
EXTI Exported Constants

Defines

#define | EXTI_D3_PENDCLR_SRC_NONE 0x00000000U
#define | EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U
#define | EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U
#define | EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U
#define | EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U

Define Documentation

#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U

DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1

Definition at line 287 of file stm32h7xx_hal_exti.h.

#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U

DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1

Definition at line 288 of file stm32h7xx_hal_exti.h.

#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U

LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1

Definition at line 292 of file stm32h7xx_hal_exti.h.

#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U

LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1

Definition at line 297 of file stm32h7xx_hal_exti.h.

#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U

No D3 domain pendclear source , PMRx register to be set to zero

Definition at line 286 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Exported Macros

EXTI Exported Macros
EXTI
Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_EXTI_PROPERTY(__LINE__)
#define | IS_EXTI_TARGET(__LINE__)
#define | IS_EXTI_LINE(__LINE__)
#define | IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
#define | IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
#define | IS_EXTI_PENDING_EDGE(__LINE__)
#define | IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL)
#define | IS_EXTI_D3_PENDCLR_SRC(__SRC__)

Define Documentation

#define IS_EXTI_CONFIG_LINE ( __LINE__ ) (((__LINE__) & EXTI_CONFIG) != 0x00UL)

Definition at line 421 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), and HAL_EXTI_GetPending().

#define IS_EXTI_D3_PENDCLR_SRC ( __SRC__ )
Value:
(((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))

Definition at line 443 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_GPIO_PIN ( __PIN__ ) ((__PIN__) < 16UL)

Definition at line 435 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_GPIO_PORT ( __PORT__ )
Value:
(((__PORT__) == EXTI_GPIOA) || \
                                         ((__PORT__) == EXTI_GPIOB) || \
                                         ((__PORT__) == EXTI_GPIOC) || \
                                         ((__PORT__) == EXTI_GPIOD) || \
                                         ((__PORT__) == EXTI_GPIOE) || \
                                         ((__PORT__) == EXTI_GPIOF) || \
                                         ((__PORT__) == EXTI_GPIOG) || \
                                         ((__PORT__) == EXTI_GPIOH) || \
                                         ((__PORT__) == EXTI_GPIOI) || \
                                         ((__PORT__) == EXTI_GPIOJ) || \
                                         ((__PORT__) == EXTI_GPIOK))

Definition at line 423 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_LINE ( __LINE__ )
Value:
((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))

Definition at line 408 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_MODE ( __MODE__ ) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)

Definition at line 413 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_PENDING_EDGE ( __LINE__ )
Value:
(((__LINE__) == EXTI_TRIGGER_RISING) || \
                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))

Definition at line 417 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), and HAL_EXTI_GetPending().

#define IS_EXTI_PROPERTY ( __LINE__ )
Value:
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))

Definition at line 395 of file stm32h7xx_hal_exti.h.

#define IS_EXTI_TARGET ( __LINE__ )
Value:
((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))

Definition at line 404 of file stm32h7xx_hal_exti.h.

#define IS_EXTI_TRIGGER ( __LINE__ ) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)

Definition at line 415 of file stm32h7xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions

Functions
Configuration functions
EXTI Exported Functions

Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.

Detailed Description

Configuration functions.

 ===============================================================================
              ##### Configuration functions #####
 ===============================================================================

Function Documentation

HAL_StatusTypeDef HAL_EXTI_ClearConfigLine ( EXTI_HandleTypeDef * hexti )

Clear whole configuration of a dedicated Exti line.

Parameters:
hexti Exti handle.
Return values:
HAL Status.

Definition at line 529 of file stm32h7xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TARGET_MASK, EXTI_TARGET_MSK_ALL, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_GetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Get configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on structure to store Exti configuration.
Return values:
HAL Status.

Definition at line 375 of file stm32h7xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_D3_PENDCLR_SRC_NONE, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_NONE, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TARGET_MASK, EXTI_TARGET_MSK_ALL, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_NONE, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, EXTI_ConfigTypeDef::PendClearSource, and EXTI_ConfigTypeDef::Trigger.

HAL_StatusTypeDef HAL_EXTI_GetHandle | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | ExtiLine
 | ) |  |

Store line number as handle private field.

Parameters:
hexti | Exti handle.
ExtiLine | Exti line number. This parameter can be from 0 to EXTI_LINE_NB.
Return values:
HAL Status.

Definition at line 661 of file stm32h7xx_hal_exti.c.

References assert_param, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_RegisterCallback | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_CallbackIDTypeDef | CallbackID,
 |  | void(*)(void) | pPendingCbfn
 | ) |  |

Register callback for a dedicated Exti line.

Parameters:
hexti | Exti handle.
CallbackID User callback identifier. This parameter can be one of
  • EXTI_CallbackIDTypeDef values.
pPendingCbfn | function pointer to be stored as callback.
Return values:
HAL Status.

Definition at line 629 of file stm32h7xx_hal_exti.c.

References HAL_EXTI_COMMON_CB_ID, and EXTI_HandleTypeDef::PendingCallback.

HAL_StatusTypeDef HAL_EXTI_SetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Set configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on EXTI configuration to be set.
Return values:
HAL Status.

Definition at line 171 of file stm32h7xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_D3_PENDCLR_SRC_NONE, EXTI_EVENT, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TARGET_MASK, EXTI_TARGET_MSK_ALL, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_D3_PENDCLR_SRC, IS_EXTI_GPIO_PIN, IS_EXTI_GPIO_PORT, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, EXTI_ConfigTypeDef::PendClearSource, and EXTI_ConfigTypeDef::Trigger.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
EXTI Exported Functions

IO operation functions. More...

Functions

void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

IO operation functions.

EXTI IO functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_EXTI_ClearPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Clear interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be clear. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING_FALLING This parameter is kept for compatibility with other series.
Return values:
None.

Definition at line 802 of file stm32h7xx_hal_exti.c.

References assert_param, CM7_CPUID, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, HAL_GetCurrentCPUID(), IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_GenerateSWI ( EXTI_HandleTypeDef * hexti )

Generate a software interrupt for a dedicated line.

Parameters:
hexti Exti handle.
Return values:
None.

Definition at line 841 of file stm32h7xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

uint32_t HAL_EXTI_GetPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Get interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be checked. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING_FALLING This parameter is kept for compatibility with other series.
Return values:
1 if interrupt is pending else 0.

Definition at line 754 of file stm32h7xx_hal_exti.c.

References assert_param, CM7_CPUID, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, HAL_GetCurrentCPUID(), IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_IRQHandler ( EXTI_HandleTypeDef * hexti )

Handle EXTI interrupt request.

Parameters:
hexti Exti handle.
Return values:
none.

Definition at line 702 of file stm32h7xx_hal_exti.c.

References CM7_CPUID, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, HAL_GetCurrentCPUID(), EXTI_HandleTypeDef::Line, and EXTI_HandleTypeDef::PendingCallback.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FDCAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
Register Clock Calibration FDCAN Callback To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Clock Calibration FDCAN Callback Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
Register TT Schedule Synchronization FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Schedule Synchronization FDCAN Callback TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
Register TT Time Mark FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Time Mark FDCAN Callback TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
Register TT Stop Watch FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Stop Watch FDCAN Callback TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
Register TT Global Time FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Global Time FDCAN Callback TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the FDCAN.
      (+) De-initialize the FDCAN.
      (+) Enter FDCAN peripheral in power down mode.
      (+) Exit power down mode.
      (+) Register callbacks.
      (+) Unregister callbacks.

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_DeInit ( FDCAN_HandleTypeDef * hfdcan )

Deinitializes the FDCAN peripheral registers to their default reset values.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 590 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_MspDeInit(), HAL_FDCAN_STATE_RESET, HAL_FDCAN_Stop(), __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::MspDeInitCallback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Enter FDCAN peripheral in sleep mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 666 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Exit power down mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 701 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Init ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 285 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_InitTypeDef::AutoRetransmission, __FDCAN_HandleTypeDef::ClockCalibrationCallback, FDCAN_InitTypeDef::DataPrescaler, FDCAN_InitTypeDef::DataSyncJumpWidth, FDCAN_InitTypeDef::DataTimeSeg1, FDCAN_InitTypeDef::DataTimeSeg2, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_CalcultateRamBlockAddresses(), FDCAN_FRAME_FD_BRS, FDCAN_MODE_BUS_MONITORING, FDCAN_MODE_INTERNAL_LOOPBACK, FDCAN_MODE_NORMAL, FDCAN_MODE_RESTRICTED_OPERATION, FDCAN_TIMEOUT_VALUE, FDCAN_InitTypeDef::FrameFormat, HAL_FDCAN_ClockCalibrationCallback(), HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspInit(), HAL_FDCAN_RxBufferNewMessageCallback(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TT_GlobalTimeCallback(), HAL_FDCAN_TT_ScheduleSyncCallback(), HAL_FDCAN_TT_StopWatchCallback(), HAL_FDCAN_TT_TimeMarkCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), HAL_GetTick(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_DATA_PRESCALER, IS_FDCAN_DATA_SIZE, IS_FDCAN_DATA_SJW, IS_FDCAN_DATA_TSEG1, IS_FDCAN_DATA_TSEG2, IS_FDCAN_FRAME_FORMAT, IS_FDCAN_MAX_VALUE, IS_FDCAN_MODE, IS_FDCAN_NOMINAL_PRESCALER, IS_FDCAN_NOMINAL_SJW, IS_FDCAN_NOMINAL_TSEG1, IS_FDCAN_NOMINAL_TSEG2, IS_FDCAN_TX_FIFO_QUEUE_MODE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, __FDCAN_HandleTypeDef::Lock, FDCAN_InitTypeDef::Mode, __FDCAN_HandleTypeDef::MspInitCallback, FDCAN_InitTypeDef::NominalPrescaler, FDCAN_InitTypeDef::NominalSyncJumpWidth, FDCAN_InitTypeDef::NominalTimeSeg1, FDCAN_InitTypeDef::NominalTimeSeg2, FDCAN_InitTypeDef::ProtocolException, __FDCAN_HandleTypeDef::RxBufferNewMessageCallback, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, __FDCAN_HandleTypeDef::RxFifo0Callback, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_InitTypeDef::RxFifo0ElmtsNbr, __FDCAN_HandleTypeDef::RxFifo1Callback, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_InitTypeDef::RxFifo1ElmtsNbr, __FDCAN_HandleTypeDef::State, FDCAN_InitTypeDef::StdFiltersNbr, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, FDCAN_InitTypeDef::TransmitPause, __FDCAN_HandleTypeDef::TT_GlobalTimeCallback, __FDCAN_HandleTypeDef::TT_ScheduleSyncCallback, __FDCAN_HandleTypeDef::TT_StopWatchCallback, __FDCAN_HandleTypeDef::TT_TimeMarkCallback, __FDCAN_HandleTypeDef::ttcan, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, FDCAN_InitTypeDef::TxBuffersNbr, FDCAN_InitTypeDef::TxElmtSize, __FDCAN_HandleTypeDef::TxEventFifoCallback, FDCAN_InitTypeDef::TxEventsNbr, __FDCAN_HandleTypeDef::TxFifoEmptyCallback, FDCAN_InitTypeDef::TxFifoQueueElmtsNbr, and FDCAN_InitTypeDef::TxFifoQueueMode.

void HAL_FDCAN_MspDeInit ( FDCAN_HandleTypeDef * hfdcan )

DeInitializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 651 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_DeInit(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_MspInit ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 636 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), and HAL_FDCAN_UnRegisterCallback().

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | void(*)(FDCAN_HandleTypeDef *_hFDCAN) | pCallback
 | ) |  |

Register a FDCAN CallBack.

To be used instead of the weak predefined callback

Parameters:
hfdcan | pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 752 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::RxBufferNewMessageCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | pFDCAN_CallbackTypeDef | pCallback
 | ) |  |
HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_ClockCalibrationCallbackTypeDef | pCallback
 | ) |  |

Register Clock Calibration FDCAN Callback To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Clock Calibration Callback function
Return values:
HAL status

Definition at line 948 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ClockCalibrationCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_ErrorStatusCallbackTypeDef | pCallback
 | ) |  |

Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Error Status Callback function
Return values:
HAL status

Definition at line 1308 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo0CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 0 Callback function
Return values:
HAL status

Definition at line 1068 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo1CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 1 Callback function
Return values:
HAL status

Definition at line 1128 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TT_GlobalTimeCallbackTypeDef | pCallback
 | ) |  |

Register TT Global Time FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the TT Global Time Callback function
Return values:
HAL status

Definition at line 1548 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_GlobalTimeCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TT_ScheduleSyncCallbackTypeDef | pCallback
 | ) |  |

Register TT Schedule Synchronization FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the TT Schedule Synchronization Callback function
Return values:
HAL status

Definition at line 1368 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_ScheduleSyncCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TT_StopWatchCallbackTypeDef | pCallback
 | ) |  |

Register TT Stop Watch FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the TT Stop Watch Callback function
Return values:
HAL status

Definition at line 1488 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_StopWatchCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TT_TimeMarkCallbackTypeDef | pCallback
 | ) |  |

Register TT Time Mark FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the TT Time Mark Callback function
Return values:
HAL status

Definition at line 1428 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_TimeMarkCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferAbortCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Abort Callback function
Return values:
HAL status

Definition at line 1248 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferCompleteCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Complete Callback function
Return values:
HAL status

Definition at line 1188 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxEventFifoCallbackTypeDef | pCallback
 | ) |  |

Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Event Fifo Callback function
Return values:
HAL status

Definition at line 1008 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a FDCAN CallBack.

FDCAN callback is redirected to the weak predefined callback

Parameters:
hfdcan pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 859 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspDeInit(), HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MspInit(), HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID, HAL_FDCAN_RxBufferNewMessageCallback(), HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::RxBufferNewMessageCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Clock Calibration FDCAN Callback Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 981 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ClockCalibrationCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ClockCalibrationCallback(), HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1341 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1101 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1161 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the TT Global Time FDCAN Callback TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1581 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TT_GlobalTimeCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_GlobalTimeCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the TT Schedule Synchronization FDCAN Callback TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1401 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TT_ScheduleSyncCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_ScheduleSyncCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the TT Stop Watch FDCAN Callback TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1521 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TT_StopWatchCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_StopWatchCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the TT Time Mark FDCAN Callback TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1461 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TT_TimeMarkCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TT_TimeMarkCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1281 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferAbortCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1221 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferCompleteCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1041 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxEventFifoCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions

Functions
Configuration functions
FDCAN Exported Functions

FDCAN Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.

Detailed Description

FDCAN Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ClkCalUnitTypeDef * | sCcuConfig
 | ) |  |

Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sCcuConfig | pointer to an FDCAN_ClkCalUnitTypeDef structure that contains the clock calibration information
Return values:
HAL status

Definition at line 1656 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_ClkCalUnitTypeDef::CalFieldLength, FDCAN_ClkCalUnitTypeDef::ClockCalibration, FDCAN_ClkCalUnitTypeDef::ClockDivider, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_CLOCK_CALIBRATION_DISABLE, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_CALIBRATION_FIELD_LENGTH, IS_FDCAN_CKDIV, IS_FDCAN_CLOCK_CALIBRATION, IS_FDCAN_MAX_VALUE, IS_FDCAN_MIN_VALUE, FDCAN_ClkCalUnitTypeDef::MinOscClkPeriods, __FDCAN_HandleTypeDef::State, FDCAN_ClkCalUnitTypeDef::TimeQuantaPerBitTime, and FDCAN_ClkCalUnitTypeDef::WatchdogStartValue.

HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Mask
 | ) |  |

Configure the extended ID mask.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Mask | Extended ID Mask. This parameter must be a number between 0 and 0x1FFFFFFF
Return values:
HAL status

Definition at line 1957 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | FIFO,
 |  | uint32_t | Watermark
 | ) |  |

Configure the FIFO watermark.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
FIFO select the FIFO to be configured. This parameter can be a value of
  • FDCAN_FIFO_watermark.
Watermark level for FIFO watermark interrupt. This parameter must be a number between:
  • 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
  • 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
Return values:
HAL status

Definition at line 2034 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_CFG_RX_FIFO0, FDCAN_CFG_TX_EVENT_FIFO, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_FIFO_WATERMARK, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_FilterTypeDef * | sFilterConfig
 | ) |  |

Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sFilterConfig | pointer to an FDCAN_FilterTypeDef structure that contains the filter configuration information
Return values:
HAL status

Definition at line 1805 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_FILTER_TO_RXBUFFER, FDCAN_STANDARD_ID, FDCAN_FilterTypeDef::FilterConfig, FDCAN_FilterTypeDef::FilterID1, FDCAN_FilterTypeDef::FilterID2, FDCAN_FilterTypeDef::FilterIndex, FDCAN_FilterTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_FilterTypeDef::IdType, __FDCAN_HandleTypeDef::Init, IS_FDCAN_EXT_FILTER_TYPE, IS_FDCAN_FILTER_CFG, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_STD_FILTER_TYPE, FDCAN_FilterTypeDef::IsCalibrationMsg, __FDCAN_HandleTypeDef::msgRam, FDCAN_FilterTypeDef::RxBufferIndex, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, __FDCAN_HandleTypeDef::State, and FDCAN_InitTypeDef::StdFiltersNbr.

HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NonMatchingStd,
 |  | uint32_t | NonMatchingExt,
 |  | uint32_t | RejectRemoteStd,
 |  | uint32_t | RejectRemoteExt
 | ) |  |

Configure the FDCAN global filter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NonMatchingStd Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
NonMatchingExt Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
Return values:
HAL status

Definition at line 1917 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_NON_MATCHING, IS_FDCAN_REJECT_REMOTE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | CounterStartValue
 | ) |  |

Configure the RAM watchdog.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
CounterStartValue | Start value of the Message RAM Watchdog Counter, This parameter must be a number between 0x00 and 0xFF, with the reset value of 0x00 the counter is disabled.
Return values:
HAL status

Definition at line 2084 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo,
 |  | uint32_t | OperationMode
 | ) |  |

Configure the Rx FIFO operation mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
OperationMode operation mode. This parameter can be a value of
  • FDCAN_Rx_FIFO_operation_mode.
Return values:
HAL status

Definition at line 1991 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RX_FIFO0, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, IS_FDCAN_RX_FIFO_MODE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeoutOperation,
 |  | uint32_t | TimeoutPeriod
 | ) |  |

Configure the timeout counter.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeoutOperation Timeout counter operation. This parameter can be a value of
  • FDCAN_Timeout_Operation.
TimeoutPeriod | Start value of the timeout down-counter. This parameter must be a number between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 2239 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TIMEOUT, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampPrescaler
 | ) |  |

Configure the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampPrescaler Timestamp Counter Prescaler. This parameter can be a value of
  • FDCAN_Timestamp_Prescaler.
Return values:
HAL status

Definition at line 2114 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP_PRESCALER, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TdcOffset,
 |  | uint32_t | TdcFilter
 | ) |  |

Configure the transmitter delay compensation.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TdcOffset | Transmitter Delay Compensation Offset. This parameter must be a number between 0x00 and 0x7F.
TdcFilter | Transmitter Delay Compensation Filter Window Length. This parameter must be a number between 0x00 and 0x7F.
Return values:
HAL status

Definition at line 2359 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Disable edge filtering during bus integration.

One dominant tq is required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2517 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Disable ISO 11898-1 protocol mode.

CAN FD frame format is according to Bosch CAN FD specification V1.0.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2465 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2293 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2172 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Disable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2413 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Enable edge filtering during bus integration.

Two consecutive dominant tq are required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2491 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Enable ISO 11898-1 protocol mode.

CAN FD frame format is according to ISO 11898-1 standard.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2439 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Enable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2268 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampOperation
 | ) |  |

Enable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampOperation Timestamp counter operation. This parameter can be a value of
  • FDCAN_Timestamp.
Return values:
HAL status

Definition at line 2144 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Enable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2388 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

uint32_t HAL_FDCAN_GetClockCalibrationCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Counter
 | ) |  |

Get the clock calibration counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Counter clock calibration counter. This parameter can be a value of
  • FDCAN_calibration_counter.
Return values:
Value clock calibration counter value

Definition at line 1774 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_CALIB_CLOCK_PERIOD_COUNTER, FDCAN_CALIB_TIME_QUANTA_COUNTER, and IS_FDCAN_CALIBRATION_COUNTER.

uint32_t HAL_FDCAN_GetClockCalibrationState ( FDCAN_HandleTypeDef * hfdcan )

Get the clock calibration state.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
State clock calibration state (can be a value of
  • FDCAN_calibration_state)

Definition at line 1724 of file stm32h7xx_hal_fdcan.c.

uint16_t HAL_FDCAN_GetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timeout counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Value Timeout counter value

Definition at line 2318 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint16_t HAL_FDCAN_GetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timestamp counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Value Timestamp counter value

Definition at line 2197 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState ( FDCAN_HandleTypeDef * hfdcan )

Reset the clock calibration state.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1738 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timeout counter to its start value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2329 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_CONTINUOUS, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timestamp counter to zero.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2208 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMESTAMP_EXTERNAL, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Control functions

Functions
Control functions
FDCAN Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.

Detailed Description

Control functions.

  ==============================================================================
                          ##### Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_Start                         : Start the FDCAN module
      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Abort transmission request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 2877 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  |

Add a message to a dedicated Tx buffer.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
BufferIndex index of the buffer to be configured. This parameter can be a value of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 2768 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TX_LOCATION, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData
 | ) |  |

Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
Return values:
HAL status

Definition at line 2690 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_FULL, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Enable transmission request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 2836 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Exit Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3366 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ErrorCountersTypeDef * | ErrorCounters
 | ) |  |

Get error counter values.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorCounters | pointer to an FDCAN_ErrorCountersTypeDef structure.
Return values:
HAL status

Definition at line 3221 of file stm32h7xx_hal_fdcan.c.

References FDCAN_ErrorCountersTypeDef::ErrorLogging, __FDCAN_HandleTypeDef::Instance, FDCAN_ErrorCountersTypeDef::RxErrorCnt, FDCAN_ErrorCountersTypeDef::RxErrorPassive, and FDCAN_ErrorCountersTypeDef::TxErrorCnt.

HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_HpMsgStatusTypeDef * | HpMsgStatus
 | ) |  |

Get high priority message status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
HpMsgStatus | pointer to an FDCAN_HpMsgStatusTypeDef structure.
Return values:
HAL status

Definition at line 3172 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HpMsgStatusTypeDef::FilterIndex, FDCAN_HpMsgStatusTypeDef::FilterList, __FDCAN_HandleTypeDef::Instance, FDCAN_HpMsgStatusTypeDef::MessageIndex, and FDCAN_HpMsgStatusTypeDef::MessageStorage.

uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer ( FDCAN_HandleTypeDef * hfdcan )

Get Tx buffer index of latest Tx FIFO/Queue request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Tx buffer index of last Tx FIFO/Queue request
  • Any value of
    • FDCAN_Tx_location if Tx request has been submitted.
  • 0 if no Tx FIFO/Queue request have been submitted.

Definition at line 2863 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::LatestTxFifoQRequest.

HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ProtocolStatusTypeDef * | ProtocolStatus
 | ) |  |

Get protocol status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ProtocolStatus | pointer to an FDCAN_ProtocolStatusTypeDef structure.
Return values:
HAL status

Definition at line 3190 of file stm32h7xx_hal_fdcan.c.

References FDCAN_ProtocolStatusTypeDef::Activity, FDCAN_ProtocolStatusTypeDef::BusOff, FDCAN_ProtocolStatusTypeDef::DataLastErrorCode, FDCAN_ProtocolStatusTypeDef::ErrorPassive, __FDCAN_HandleTypeDef::Instance, FDCAN_ProtocolStatusTypeDef::LastErrorCode, FDCAN_ProtocolStatusTypeDef::ProtocolException, FDCAN_ProtocolStatusTypeDef::RxBRSflag, FDCAN_ProtocolStatusTypeDef::RxESIflag, FDCAN_ProtocolStatusTypeDef::RxFDFflag, FDCAN_ProtocolStatusTypeDef::TDCvalue, and FDCAN_ProtocolStatusTypeDef::Warning.

uint32_t HAL_FDCAN_GetRxFifoFillLevel | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo
 | ) |  |

Return Rx FIFO fill level.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
Return values:
Level Rx FIFO fill level.

Definition at line 3305 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_RX_FIFO0, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_RX_FIFO.

HAL_StatusTypeDef HAL_FDCAN_GetRxMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxLocation,
 |  | FDCAN_RxHeaderTypeDef * | pRxHeader,
 |  | uint8_t * | pRxData
 | ) |  |

Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxLocation Location of the received message to be read. This parameter can be a value of
  • FDCAN_Rx_location.
pRxHeader | pointer to a FDCAN_RxHeaderTypeDef structure.
pRxData | pointer to a buffer where the payload of the Rx frame will be stored.
Return values:
HAL status

Definition at line 2906 of file stm32h7xx_hal_fdcan.c.

References FDCAN_RxHeaderTypeDef::BitRateSwitch, FDCAN_RxHeaderTypeDef::DataLength, DLCtoBytes, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RxHeaderTypeDef::ErrorStateIndicator, FDCAN_ELEMENT_MASK_ANMF, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_FIDX, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_RX_BUFFER32, FDCAN_RX_FIFO0, FDCAN_RX_FIFO1, FDCAN_STANDARD_ID, FDCAN_RxHeaderTypeDef::FDFormat, FDCAN_RxHeaderTypeDef::FilterIndex, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, FDCAN_RxHeaderTypeDef::Identifier, FDCAN_RxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxBufferSA, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_RxHeaderTypeDef::RxFrameType, FDCAN_RxHeaderTypeDef::RxTimestamp, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetTxEvent | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxEventFifoTypeDef * | pTxEvent
 | ) |  |

Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxEvent | pointer to a FDCAN_TxEventFifoTypeDef structure.
Return values:
HAL status

Definition at line 3077 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxEventFifoTypeDef::BitRateSwitch, FDCAN_TxEventFifoTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxEventFifoTypeDef::ErrorStateIndicator, FDCAN_TxEventFifoTypeDef::EventType, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_ET, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_MM, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_STANDARD_ID, FDCAN_TxEventFifoTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, FDCAN_TxEventFifoTypeDef::Identifier, FDCAN_TxEventFifoTypeDef::IdType, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MIN_VALUE, FDCAN_TxEventFifoTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, __FDCAN_HandleTypeDef::State, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_InitTypeDef::TxEventsNbr, FDCAN_TxEventFifoTypeDef::TxFrameType, and FDCAN_TxEventFifoTypeDef::TxTimestamp.

uint32_t HAL_FDCAN_GetTxFifoFreeLevel ( FDCAN_HandleTypeDef * hfdcan )

Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Level Tx FIFO free level.

Definition at line 3332 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Check if the FDCAN peripheral entered Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Status
  • 0 : Normal FDCAN operation.
  • 1 : Restricted Operation Mode active.

Definition at line 3350 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRxBufferMessageAvailable | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxBufferIndex
 | ) |  |

Check if a new message is received in the selected Rx buffer.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxBufferIndex | Rx buffer index. This parameter must be a number between 0 and 63.
Return values:
Status
  • 0 : No new message on RxBufferIndex.
  • 1 : New message received on RxBufferIndex.

Definition at line 3248 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_MAX_VALUE.

uint32_t HAL_FDCAN_IsTxBufferMessagePending | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxBufferIndex
 | ) |  |

Check if a transmission request is pending on the selected Tx buffer.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxBufferIndex Tx buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
Status
  • 0 : No pending transmission request on TxBufferIndex.
  • 1 : Pending transmission request on TxBufferIndex.

Definition at line 3285 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_Start ( FDCAN_HandleTypeDef * hfdcan )

Start the FDCAN module.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2577 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Stop ( FDCAN_HandleTypeDef * hfdcan )

Stop the FDCAN module and enable access to configuration registers.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2608 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, and __FDCAN_HandleTypeDef::State.

Referenced by HAL_FDCAN_DeInit().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TT Configuration and control functions

Functions
TT Configuration and control functions
FDCAN Exported Functions

TT Configuration and control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.

Detailed Description

TT Configuration and control functions.

  ==============================================================================
              ##### TT Configuration and control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TargetPhase
 | ) |  |

Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TargetPhase | defines target value of cycle time when a rising edge of fdcan1_evt is expected. This parameter must be a number between 0 and 0xFFFF.
Return values:
HAL status

Definition at line 4712 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TT_ConfigTypeDef * | pTTParams
 | ) |  |

Initialize TT operation parameters.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTTParams | pointer to a FDCAN_TT_ConfigTypeDef structure.
Return values:
HAL status

Definition at line 3432 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TT_ConfigTypeDef::AppWdgLimit, assert_param, FDCAN_TT_ConfigTypeDef::BasicCyclesNbr, FDCAN_TT_ConfigTypeDef::ClockCalibration, FDCAN_TT_ConfigTypeDef::CycleStartSync, FDCAN_MsgRamAddressTypeDef::EndAddress, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TT_ConfigTypeDef::EventTrigSel, FDCAN_TT_ConfigTypeDef::EvtTrigPolarity, FDCAN_TT_ConfigTypeDef::ExpTxTrigNbr, FDCAN_TT_ConfigTypeDef::ExternalClkSync, FDCAN_MESSAGE_RAM_END_ADDRESS, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, FDCAN_TT_COMMUNICATION_LEVEL1, FDCAN_TT_POTENTIAL_MASTER, FDCAN_TT_ConfigTypeDef::GapEnable, FDCAN_TT_ConfigTypeDef::GlobalTimeFilter, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_GetTick(), FDCAN_TT_ConfigTypeDef::InitRefTrigOffset, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_AUTO_CLK_CALIBRATION, IS_FDCAN_TT_BASIC_CYCLES_NUMBER, IS_FDCAN_TT_CYCLE_START_SYNC, IS_FDCAN_TT_EVENT_TRIGGER, IS_FDCAN_TT_EVENT_TRIGGER_POLARITY, IS_FDCAN_TT_EXTERNAL_CLK_SYNC, IS_FDCAN_TT_GLOBAL_TIME_FILTERING, IS_FDCAN_TT_OPERATION, IS_FDCAN_TT_STOP_WATCH_TRIGGER, IS_FDCAN_TT_TIME_MASTER, IS_FDCAN_TT_TUR_DENOMINATOR, IS_FDCAN_TT_TUR_LEVEL_0_2, IS_FDCAN_TT_TUR_LEVEL_1, IS_FDCAN_TT_TUR_NUMERATOR, IS_FDCAN_TT_TX_ENABLE_WINDOW, __FDCAN_HandleTypeDef::msgRam, FDCAN_TT_ConfigTypeDef::OperationMode, __FDCAN_HandleTypeDef::State, FDCAN_TT_ConfigTypeDef::StopWatchTrigSel, FDCAN_TT_ConfigTypeDef::SyncDevLimit, FDCAN_TT_ConfigTypeDef::TimeMaster, FDCAN_TT_ConfigTypeDef::TriggerMemoryNbr, __FDCAN_HandleTypeDef::ttcan, FDCAN_MsgRamAddressTypeDef::TTMemorySA, FDCAN_TT_ConfigTypeDef::TURDenominator, FDCAN_TT_ConfigTypeDef::TURNumerator, and FDCAN_TT_ConfigTypeDef::TxEnableWindow.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | IdType,
 |  | uint32_t | Identifier,
 |  | uint32_t | Payload
 | ) |  |

Configure the reference message.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
IdType Identifier Type. This parameter can be a value of
  • FDCAN_id_type.
Identifier Reference Identifier. This parameter must be a number between:
  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
Payload Enable or disable the additional payload. This parameter can be a value of
  • FDCAN_TT_Reference_Message_Payload. This parameter is ignored in case of time slaves. If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the following elements are taken from Tx Buffer 0:
    • MessageMarker
    • TxEventFifoControl
    • DataLength
    • Data Bytes (payload):
      • bytes 2-8, for Level 1
      • bytes 5-8, for Level 0 and Level 2
Return values:
HAL status

Definition at line 3610 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeMarkSource,
 |  | uint32_t | TimeMarkValue,
 |  | uint32_t | RepeatFactor,
 |  | uint32_t | StartCycle
 | ) |  |

Configure register time mark pulse generation.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeMarkSource time mark source. This parameter can be a value of
  • FDCAN_TT_time_mark_source.
TimeMarkValue | time mark value (reference). This parameter must be a number between 0 and 0xFFFF.
RepeatFactor repeat factor of the cycle for which the time mark is valid. This parameter can be a value of
  • FDCAN_TT_Repeat_Factor.
StartCycle | index of the first cycle in which the time mark becomes valid. This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. This parameter must be a number between 0 and RepeatFactor.
Return values:
HAL status

Definition at line 3979 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_REG_TIMEMARK_DIABLED, FDCAN_TT_REPEAT_EVERY_CYCLE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE, IS_FDCAN_TT_REPEAT_FACTOR, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Configure stop watch source and polarity.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Source stop watch source. This parameter can be a value of
  • FDCAN_TT_stop_watch_source.
Polarity stop watch polarity. This parameter can be a value of
  • FDCAN_TT_stop_watch_polarity.
Return values:
HAL status

Definition at line 3918 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_STOP_WATCH_POLARITY, IS_FDCAN_TT_STOP_WATCH_SOURCE, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TriggerTypeDef * | sTriggerConfig
 | ) |  |

Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sTriggerConfig | pointer to an FDCAN_TriggerTypeDef structure that contains the trigger configuration information
Return values:
HAL status

Definition at line 3658 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_STANDARD_ID, FDCAN_TT_REPEAT_EVERY_CYCLE, FDCAN_TT_RX_TRIGGER, FDCAN_TT_TX_TRIGGER_ARBITRATION, FDCAN_TT_TX_TRIGGER_CONTINUOUS, FDCAN_TT_TX_TRIGGER_MERGED, FDCAN_TT_TX_TRIGGER_SINGLE, FDCAN_TriggerTypeDef::FilterIndex, FDCAN_TriggerTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REPEAT_FACTOR, IS_FDCAN_TT_TM_EVENT_EXTERNAL, IS_FDCAN_TT_TM_EVENT_INTERNAL, IS_FDCAN_TT_TRIGGER_TYPE, IS_FDCAN_TX_LOCATION, __FDCAN_HandleTypeDef::msgRam, FDCAN_TriggerTypeDef::RepeatFactor, FDCAN_TriggerTypeDef::StartCycle, __FDCAN_HandleTypeDef::State, FDCAN_TriggerTypeDef::TimeMark, FDCAN_TriggerTypeDef::TmEventExt, FDCAN_TriggerTypeDef::TmEventInt, FDCAN_TriggerTypeDef::TriggerIndex, FDCAN_TriggerTypeDef::TriggerType, FDCAN_MsgRamAddressTypeDef::TTMemorySA, and FDCAN_TriggerTypeDef::TxBufferIndex.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization ( FDCAN_HandleTypeDef * hfdcan )

Disable external schedule synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4803 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl ( FDCAN_HandleTypeDef * hfdcan )

Disable gap control by input pin fdcan1_evt.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4383 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Disable register time mark pulse generation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4150 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl ( FDCAN_HandleTypeDef * hfdcan )

Disable gap control by register time mark interrupt.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4507 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Disable trigger time mark pulse generation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4261 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization ( FDCAN_HandleTypeDef * hfdcan )

Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4753 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl ( FDCAN_HandleTypeDef * hfdcan )

Enable gap control by input pin fdcan1_evt.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4322 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Enable register time mark pulse generation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4100 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl ( FDCAN_HandleTypeDef * hfdcan )

Enable gap control (finish only) by register time mark interrupt.

The next register time mark interrupt (TTIR.RTMI = "1") will finish the Gap and start the reference message.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4446 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Enable trigger time mark pulse generation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4200 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TTOperationStatusTypeDef * | TTOpStatus
 | ) |  |

Get TT operation status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTOpStatus | pointer to an FDCAN_TTOperationStatusTypeDef structure.
Return values:
HAL status

Definition at line 4854 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TTOperationStatusTypeDef::AppWdgEvt, assert_param, FDCAN_TTOperationStatusTypeDef::ClockQuality, FDCAN_TTOperationStatusTypeDef::ECSPending, FDCAN_TTOperationStatusTypeDef::ErrorLevel, FDCAN_TTOperationStatusTypeDef::GapFinished, FDCAN_TTOperationStatusTypeDef::GapStarted, FDCAN_TTOperationStatusTypeDef::GTimeDiscPending, FDCAN_TTOperationStatusTypeDef::GTimeQuality, __FDCAN_HandleTypeDef::Instance, FDCAN_TTOperationStatusTypeDef::MasterPriority, FDCAN_TTOperationStatusTypeDef::MasterState, FDCAN_TTOperationStatusTypeDef::PhaseLock, FDCAN_TTOperationStatusTypeDef::RefTrigOffset, FDCAN_TTOperationStatusTypeDef::SyncState, __FDCAN_HandleTypeDef::ttcan, and FDCAN_TTOperationStatusTypeDef::WaitForEvt.

HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NewTURNumerator
 | ) |  |

Schedule TUR numerator update for the next reference message.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NewTURNumerator | new value of the TUR numerator. This parameter must be a number between 0x10000 and 0x1FFFF.
Return values:
HAL status

Definition at line 3842 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_TUR_NUMERATOR, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap ( FDCAN_HandleTypeDef * hfdcan )

Finish a Gap by requesting start of reference message.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4638 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimePreset
 | ) |  |

Schedule global time adjustment for the next reference message.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimePreset time preset value. This parameter must be a number between:
  • 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset or
  • 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
Return values:
HAL status

Definition at line 3768 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_TIME_PRESET, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap ( FDCAN_HandleTypeDef * hfdcan )

Transmit next reference message with Next_is_Gap = "1".

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4568 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Interrupts management

Functions
Interrupts management
FDCAN Exported Functions

Interrupts management. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.

Detailed Description

Interrupts management.

  ==============================================================================
                       ##### Interrupts management #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveITs,
 |  | uint32_t | BufferIndexes
 | ) |  |

Enable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveITs indicates which interrupts will be enabled. This parameter can be any combination of
  • FDCAN_Interrupts.
BufferIndexes Tx Buffer Indexes. This parameter can be any combination of
  • FDCAN_Tx_location. This parameter is ignored if ActiveITs does not include one of the following:
    • FDCAN_IT_TX_COMPLETE
    • FDCAN_IT_TX_ABORT_COMPLETE
Return values:
HAL status

Definition at line 5006 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_ENABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ITList indicates which interrupts will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_Interrupts.
InterruptLine Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 4918 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, IS_FDCAN_IT_LINE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveITs
 | ) |  |

Disable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveITs indicates which interrupts will be disabled. This parameter can be any combination of
  • FDCAN_Interrupts.
Return values:
HAL status

Definition at line 5069 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_DISABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, and __FDCAN_HandleTypeDef::State.

void HAL_FDCAN_IRQHandler ( FDCAN_HandleTypeDef * hfdcan )

Handles FDCAN interrupt request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 5224 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_CLEAR_FLAG, __HAL_FDCAN_GET_FLAG, __HAL_FDCAN_GET_IT_SOURCE, __HAL_FDCAN_TT_CLEAR_FLAG, __HAL_FDCAN_TT_GET_FLAG, __HAL_FDCAN_TT_GET_IT_SOURCE, __FDCAN_HandleTypeDef::ClockCalibrationCallback, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_ERROR_MASK, FDCAN_ERROR_STATUS_MASK, FDCAN_FLAG_RAM_ACCESS_FAILURE, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG, FDCAN_FLAG_TIMEOUT_OCCURRED, FDCAN_FLAG_TIMESTAMP_WRAPAROUND, FDCAN_FLAG_TX_ABORT_COMPLETE, FDCAN_FLAG_TX_COMPLETE, FDCAN_FLAG_TX_FIFO_EMPTY, FDCAN_IT_RAM_ACCESS_FAILURE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE, FDCAN_IT_RX_HIGH_PRIORITY_MSG, FDCAN_IT_TIMEOUT_OCCURRED, FDCAN_IT_TIMESTAMP_WRAPAROUND, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, FDCAN_IT_TX_FIFO_EMPTY, FDCAN_RX_FIFO0_MASK, FDCAN_RX_FIFO1_MASK, FDCAN_TT_DISTURBING_ERROR_MASK, FDCAN_TT_FATAL_ERROR_MASK, FDCAN_TT_FLAG_STOP_WATCH, FDCAN_TT_GLOBAL_TIME_MASK, FDCAN_TT_IT_STOP_WATCH, FDCAN_TT_SCHEDULE_SYNC_MASK, FDCAN_TT_TIME_MARK_MASK, FDCAN_TX_EVENT_FIFO_MASK, HAL_FDCAN_ClockCalibrationCallback(), HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_RAM_ACCESS, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_RxBufferNewMessageCallback(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TT_GlobalTimeCallback(), HAL_FDCAN_TT_ScheduleSyncCallback(), HAL_FDCAN_TT_StopWatchCallback(), HAL_FDCAN_TT_TimeMarkCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::RxBufferNewMessageCallback, __FDCAN_HandleTypeDef::RxFifo0Callback, __FDCAN_HandleTypeDef::RxFifo1Callback, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, __FDCAN_HandleTypeDef::TT_GlobalTimeCallback, __FDCAN_HandleTypeDef::TT_ScheduleSyncCallback, __FDCAN_HandleTypeDef::TT_StopWatchCallback, __FDCAN_HandleTypeDef::TT_TimeMarkCallback, __FDCAN_HandleTypeDef::ttcan, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, __FDCAN_HandleTypeDef::TxEventFifoCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveTTITs
 | ) |  |

Enable TT interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveTTITs indicates which TT interrupts will be enabled. This parameter can be any combination of
  • FDCAN_TTInterrupts.
Return values:
HAL status

Definition at line 5128 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_TT_ENABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_IT, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign TT interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTITList indicates which interrupts will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_TTInterrupts.
InterruptLine Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 4960 of file stm32h7xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT_LINE, IS_FDCAN_TT_IT, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveTTITs
 | ) |  |

Disable TT interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveTTITs indicates which TT interrupts will be disabled. This parameter can be any combination of
  • FDCAN_TTInterrupts.
Return values:
HAL status

Definition at line 5178 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_TT_DISABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_IT, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::ttcan.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Callback functions

Functions
Callback functions
FDCAN Exported Functions

FDCAN Callback functions. More...

Functions

__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.

Detailed Description

FDCAN Callback functions.

  ==============================================================================
                          ##### Callback functions #####
  ==============================================================================
    [..]
    This subsection provides the following callback functions:
      (+) HAL_FDCAN_ClockCalibrationCallback
      (+) HAL_FDCAN_TxEventFifoCallback
      (+) HAL_FDCAN_RxFifo0Callback
      (+) HAL_FDCAN_RxFifo1Callback
      (+) HAL_FDCAN_TxFifoEmptyCallback
      (+) HAL_FDCAN_TxBufferCompleteCallback
      (+) HAL_FDCAN_TxBufferAbortCallback
      (+) HAL_FDCAN_RxBufferNewMessageCallback
      (+) HAL_FDCAN_HighPriorityMessageCallback
      (+) HAL_FDCAN_TimestampWraparoundCallback
      (+) HAL_FDCAN_TimeoutOccurredCallback
      (+) HAL_FDCAN_ErrorCallback
      (+) HAL_FDCAN_ErrorStatusCallback
      (+) HAL_FDCAN_TT_ScheduleSyncCallback
      (+) HAL_FDCAN_TT_TimeMarkCallback
      (+) HAL_FDCAN_TT_StopWatchCallback
      (+) HAL_FDCAN_TT_GlobalTimeCallback

Function Documentation

void HAL_FDCAN_ClockCalibrationCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ClkCalibrationITs
 | ) |  |

Clock Calibration callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ClkCalibrationITs indicates which Clock Calibration interrupts are signaled. This parameter can be any combination of
  • FDCAN_Clock_Calibration_Interrupts.
Return values:
None

Definition at line 5646 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterClockCalibrationCallback().

void HAL_FDCAN_ErrorCallback ( FDCAN_HandleTypeDef * hfdcan )

Error callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5838 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_ErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ErrorStatusITs
 | ) |  |

Error status callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorStatusITs indicates which Error Status interrupts are signaled. This parameter can be any combination of
  • FDCAN_Error_Status_Interrupts.
Return values:
None

Definition at line 5856 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void HAL_FDCAN_HighPriorityMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

High Priority Message callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5822 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_RxBufferNewMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

Rx Buffer New Message callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5774 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_RxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo0ITs
 | ) |  |

Rx FIFO 0 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. This parameter can be any combination of
  • FDCAN_Rx_Fifo0_Interrupts.
Return values:
None

Definition at line 5684 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void HAL_FDCAN_RxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo1ITs
 | ) |  |

Rx FIFO 1 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. This parameter can be any combination of
  • FDCAN_Rx_Fifo1_Interrupts.
Return values:
None

Definition at line 5703 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

void HAL_FDCAN_TimeoutOccurredCallback ( FDCAN_HandleTypeDef * hfdcan )

Timeout Occurred callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5806 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TimestampWraparoundCallback ( FDCAN_HandleTypeDef * hfdcan )

Timestamp Wraparound callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5790 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TT_GlobalTimeCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTGlobTimeITs
 | ) |  |

TT Global Time callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTGlobTimeITs indicates which TT Global Time interrupts are signaled. This parameter can be any combination of
  • FDCAN_TTGlobalTime_Interrupts.
Return values:
None

Definition at line 5936 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTTGlobalTimeCallback().

void HAL_FDCAN_TT_ScheduleSyncCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTSchedSyncITs
 | ) |  |

TT Schedule Synchronization callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled. This parameter can be any combination of
  • FDCAN_TTScheduleSynchronization_Interrupts.
Return values:
None

Definition at line 5875 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTTScheduleSyncCallback().

void HAL_FDCAN_TT_StopWatchCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | SWTime,
 |  | uint32_t | SWCycleCount
 | ) |  |

TT Stop Watch callback.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
SWTime | Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising edge (as configured via HAL_FDCAN_TTConfigStopWatch). This parameter is a number between 0 and 0xFFFF.
SWCycleCount | Cycle count value captured together with SWTime. This parameter is a number between 0 and 0x3F.
Return values:
None

Definition at line 5916 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTTStopWatchCallback().

void HAL_FDCAN_TT_TimeMarkCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTTimeMarkITs
 | ) |  |

TT Time Mark callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled. This parameter can be any combination of
  • FDCAN_TTTimeMark_Interrupts.
Return values:
None

Definition at line 5894 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTTTimeMarkCallback().

void HAL_FDCAN_TxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Cancellation callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the aborted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 5757 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void HAL_FDCAN_TxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Complete callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the transmitted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 5738 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void HAL_FDCAN_TxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxEventFifoITs
 | ) |  |

Tx Event callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. This parameter can be any combination of
  • FDCAN_Tx_Event_Fifo_Interrupts.
Return values:
None

Definition at line 5665 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void HAL_FDCAN_TxFifoEmptyCallback ( FDCAN_HandleTypeDef * hfdcan )

Tx FIFO Empty callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 5720 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
FDCAN Exported Functions

FDCAN Peripheral State functions. More...

Functions

HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Detailed Description

FDCAN Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.

Function Documentation

uint32_t HAL_FDCAN_GetError ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN error code.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
FDCAN Error Code

Definition at line 5984 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode.

HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN state.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL state

Definition at line 5972 of file stm32h7xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Exported Types

Data Structures | Typedefs | Enumerations
FDCAN Exported Types
FDCAN

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_ClkCalUnitTypeDef
FDCAN clock calibration unit structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_TT_ConfigTypeDef
FDCAN TT Init structure definition. More...
struct | FDCAN_TriggerTypeDef
FDCAN Trigger structure definition. More...
struct | FDCAN_TTOperationStatusTypeDef
FDCAN TT Operation Status structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_ClockCalibrationCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
typedef void(* | pFDCAN_TT_ScheduleSyncCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
typedef void(* | pFDCAN_TT_TimeMarkCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
typedef void(* | pFDCAN_TT_StopWatchCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
typedef void(* | pFDCAN_TT_GlobalTimeCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U,
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, HAL_FDCAN_MSPINIT_CB_ID = 0x06U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U
}
HAL FDCAN common Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __FDCAN_HandleTypeDef FDCAN_HandleTypeDef

FDCAN handle structure definition.

typedef void(* pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan)

HAL FDCAN Callback pointer definition.

pointer to a common FDCAN callback function

Definition at line 773 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)

pointer to Clock Calibration FDCAN callback function

Definition at line 774 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

pointer to Error Status callback function

Definition at line 780 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

pointer to Rx Fifo 0 FDCAN callback function

Definition at line 776 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

pointer to Rx Fifo 1 FDCAN callback function

Definition at line 777 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)

pointer to TT Global Time FDCAN callback function

Definition at line 784 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)

pointer to TT Schedule Synchronization FDCAN callback function

Definition at line 781 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)

pointer to TT Stop Watch FDCAN callback function

Definition at line 783 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)

pointer to TT Time Mark FDCAN callback function

Definition at line 782 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer abort FDCAN callback function

Definition at line 779 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer complete FDCAN callback function

Definition at line 778 of file stm32h7xx_hal_fdcan.h.

typedef void(* pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

pointer to Tx event Fifo FDCAN callback function

Definition at line 775 of file stm32h7xx_hal_fdcan.h.

Enumeration Type Documentation

enum HAL_FDCAN_CallbackIDTypeDef

HAL FDCAN common Callback ID enumeration definition.

Enumerator:
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID

FDCAN Tx Fifo Empty callback ID

HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID

FDCAN Rx buffer new message callback ID

HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID

FDCAN High priority message callback ID

HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID

FDCAN Timestamp wraparound callback ID

HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID

FDCAN Timeout occurred callback ID

HAL_FDCAN_ERROR_CALLBACK_CB_ID

FDCAN Error callback ID

HAL_FDCAN_MSPINIT_CB_ID

FDCAN MspInit callback ID

HAL_FDCAN_MSPDEINIT_CB_ID

FDCAN MspDeInit callback ID

Definition at line 756 of file stm32h7xx_hal_fdcan.h.

enum HAL_FDCAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_FDCAN_STATE_RESET

FDCAN not yet initialized or disabled

HAL_FDCAN_STATE_READY

FDCAN initialized and ready for use

HAL_FDCAN_STATE_BUSY

FDCAN process is ongoing

HAL_FDCAN_STATE_ERROR

FDCAN error state

Definition at line 47 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_InitTypeDef Struct Reference
FDCAN Exported Types

FDCAN Init structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | FrameFormat
uint32_t | Mode
FunctionalState | AutoRetransmission
FunctionalState | TransmitPause
FunctionalState | ProtocolException
uint32_t | NominalPrescaler
uint32_t | NominalSyncJumpWidth
uint32_t | NominalTimeSeg1
uint32_t | NominalTimeSeg2
uint32_t | DataPrescaler
uint32_t | DataSyncJumpWidth
uint32_t | DataTimeSeg1
uint32_t | DataTimeSeg2
uint32_t | MessageRAMOffset
uint32_t | StdFiltersNbr
uint32_t | ExtFiltersNbr
uint32_t | RxFifo0ElmtsNbr
uint32_t | RxFifo0ElmtSize
uint32_t | RxFifo1ElmtsNbr
uint32_t | RxFifo1ElmtSize
uint32_t | RxBuffersNbr
uint32_t | RxBufferSize
uint32_t | TxEventsNbr
uint32_t | TxBuffersNbr
uint32_t | TxFifoQueueElmtsNbr
uint32_t | TxFifoQueueMode
uint32_t | TxElmtSize

Detailed Description

FDCAN Init structure definition.

Definition at line 58 of file stm32h7xx_hal_fdcan.h.

Field Documentation

FunctionalState FDCAN_InitTypeDef::AutoRetransmission

Enable or disable the automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 66 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataPrescaler

Specifies the value by which the oscillator frequency is divided for generating the data bit time quanta. This parameter must be a number between 1 and 32

Definition at line 90 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a data bit to perform resynchronization. This parameter must be a number between 1 and 16

Definition at line 94 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg1

Specifies the number of time quanta in Data Bit Segment 1. This parameter must be a number between 1 and 32

Definition at line 99 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg2

Specifies the number of time quanta in Data Bit Segment 2. This parameter must be a number between 1 and 16

Definition at line 102 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ExtFiltersNbr

Specifies the number of extended Message ID filters. This parameter must be a number between 0 and 64

Definition at line 111 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::FrameFormat

Specifies the FDCAN frame format. This parameter can be a value of FDCAN Frame Format

Definition at line 60 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::MessageRAMOffset

Specifies the message RAM start address. This parameter must be a number between 0 and 2560

Definition at line 105 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses().

uint32_t FDCAN_InitTypeDef::Mode

Specifies the FDCAN mode. This parameter can be a value of FDCAN Operating Mode

Definition at line 63 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalPrescaler

Specifies the value by which the oscillator frequency is divided for generating the nominal bit time quanta. This parameter must be a number between 1 and 512

Definition at line 75 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter must be a number between 1 and 128

Definition at line 79 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg1

Specifies the number of time quanta in Bit Segment 1. This parameter must be a number between 2 and 256

Definition at line 84 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg2

Specifies the number of time quanta in Bit Segment 2. This parameter must be a number between 2 and 128

Definition at line 87 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::ProtocolException

Enable or disable the Protocol Exception Handling. This parameter can be set to ENABLE or DISABLE

Definition at line 72 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxBufferSize

Specifies the Data Field Size in an Rx Buffer element. This parameter can be a value of FDCAN Data Field Size

Definition at line 129 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxBuffersNbr

Specifies the number of Dedicated Rx Buffer elements. This parameter must be a number between 0 and 64

Definition at line 126 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo0ElmtSize

Specifies the Data Field Size in an Rx FIFO 0 element. This parameter can be a value of FDCAN Data Field Size

Definition at line 117 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo0ElmtsNbr

Specifies the number of Rx FIFO0 Elements. This parameter must be a number between 0 and 64

Definition at line 114 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo1ElmtSize

Specifies the Data Field Size in an Rx FIFO 1 element. This parameter can be a value of FDCAN Data Field Size

Definition at line 123 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo1ElmtsNbr

Specifies the number of Rx FIFO 1 Elements. This parameter must be a number between 0 and 64

Definition at line 120 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::StdFiltersNbr

Specifies the number of standard Message ID filters. This parameter must be a number between 0 and 128

Definition at line 108 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::TransmitPause

Enable or disable the Transmit Pause feature. This parameter can be set to ENABLE or DISABLE

Definition at line 69 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxBuffersNbr

Specifies the number of Dedicated Tx Buffers. This parameter must be a number between 0 and 32

Definition at line 135 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxElmtSize

Specifies the Data Field Size in a Tx Element. This parameter can be a value of FDCAN Data Field Size

Definition at line 144 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxEventsNbr

Specifies the number of Tx Event FIFO elements. This parameter must be a number between 0 and 32

Definition at line 132 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueElmtsNbr

Specifies the number of Tx Buffers used for Tx FIFO/Queue. This parameter must be a number between 0 and 32

Definition at line 138 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueMode

Tx FIFO/Queue Mode selection. This parameter can be a value of FDCAN Tx FIFO/Queue Mode

Definition at line 141 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_ClkCalUnitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ClkCalUnitTypeDef Struct Reference
FDCAN Exported Types

FDCAN clock calibration unit structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | ClockCalibration
uint32_t | ClockDivider
uint32_t | MinOscClkPeriods
uint32_t | CalFieldLength
uint32_t | TimeQuantaPerBitTime
uint32_t | WatchdogStartValue

Detailed Description

FDCAN clock calibration unit structure definition.

Definition at line 152 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ClkCalUnitTypeDef::CalFieldLength

Specifies the calibration field length. This parameter can be a value of FDCAN Calibration Field Length

Definition at line 165 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::ClockCalibration

Enable or disable the clock calibration. This parameter can be a value of FDCAN Clock Calibration.

Definition at line 154 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::ClockDivider

Specifies the FDCAN kernel clock divider when the clock calibration is bypassed. This parameter can be a value of FDCAN Clock Divider

Definition at line 157 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::MinOscClkPeriods

Configures the minimum number of periods in two CAN bit times. The actual configured number of periods is MinOscClkPeriods x 32. This parameter must be a number between 0x00 and 0xFF

Definition at line 161 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::TimeQuantaPerBitTime

Configures the number of time quanta per bit time. This parameter must be a number between 4 and 25

Definition at line 168 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::WatchdogStartValue

Start value of the Calibration Watchdog Counter. If set to zero the counter is disabled. This parameter must be a number between 0x0000 and 0xFFFF

Definition at line 171 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_FilterTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_FilterTypeDef Struct Reference
FDCAN Exported Types

FDCAN filter structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | IdType
uint32_t | FilterIndex
uint32_t | FilterType
uint32_t | FilterConfig
uint32_t | FilterID1
uint32_t | FilterID2
uint32_t | RxBufferIndex
uint32_t | IsCalibrationMsg

Detailed Description

FDCAN filter structure definition.

Definition at line 180 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_FilterTypeDef::FilterConfig

Specifies the filter configuration. This parameter can be a value of FDCAN Filter Configuration

Definition at line 197 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID1

Specifies the filter identification 1. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 200 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID2

Specifies the filter identification 2. This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 205 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterIndex

Specifies the filter which will be initialized. This parameter must be a number between:

  • 0 and 127, if IdType is FDCAN_STANDARD_ID
  • 0 and 63, if IdType is FDCAN_EXTENDED_ID

Definition at line 185 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterType

Specifies the filter type. This parameter can be a value of FDCAN Filter Type. The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted only when IdType is FDCAN_EXTENDED_ID. This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER

Definition at line 190 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IdType

Specifies the identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 182 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IsCalibrationMsg

Specifies whether the filter is configured for calibration messages. This parameter is ignored if FilterConfig is different from FDCAN_FILTER_TO_RXBUFFER. This parameter can be:

  • 0 : ordinary message
  • 1 : calibration message

Definition at line 218 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::RxBufferIndex

Contains the index of the Rx buffer in which the matching message will be stored. This parameter must be a number between 0 and 63. This parameter is ignored if FilterConfig is different from FDCAN_FILTER_TO_RXBUFFER

Definition at line 212 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_TxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx header structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxEventFifoControl
uint32_t | MessageMarker

Detailed Description

FDCAN Tx header structure definition.

Definition at line 231 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxHeaderTypeDef::BitRateSwitch

Specifies whether the Tx frame will be transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 251 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::DataLength

Specifies the length of the frame that will be transmitted. This parameter can be a value of FDCAN Data Length Code

Definition at line 245 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 248 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::FDFormat

Specifies whether the Tx frame will be transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 255 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 233 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::IdType

Specifies the identifier type for the message that will be transmitted. This parameter can be a value of FDCAN ID Type

Definition at line 238 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::MessageMarker

Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 262 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxEventFifoControl

Specifies the event FIFO control. This parameter can be a value of FDCAN Event FIFO control

Definition at line 259 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxFrameType

Specifies the frame type of the message that will be transmitted. This parameter can be a value of FDCAN Frame Type

Definition at line 242 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_RxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_RxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Rx header structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | RxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | RxTimestamp
uint32_t | FilterIndex
uint32_t | IsFilterMatchingFrame

Detailed Description

FDCAN Rx header structure definition.

Definition at line 271 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_RxHeaderTypeDef::BitRateSwitch

Specifies whether the Rx frame is received with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 290 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::DataLength

Specifies the received frame length. This parameter can be a value of FDCAN Data Length Code

Definition at line 284 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 287 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FDFormat

Specifies whether the Rx frame is received in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 294 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FilterIndex

Specifies the index of matching Rx acceptance filter element. This parameter must be a number between:

  • 0 and 127, if IdType is FDCAN_STANDARD_ID
  • 0 and 63, if IdType is FDCAN_EXTENDED_ID

Definition at line 302 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 273 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IdType

Specifies the identifier type of the received message. This parameter can be a value of FDCAN ID Type

Definition at line 278 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame

Specifies whether the accepted frame did not match any Rx filter. Acceptance of non-matching frames may be enabled via HAL_FDCAN_ConfigGlobalFilter(). This parameter can be 0 or 1

Definition at line 307 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxFrameType

Specifies the the received message frame type. This parameter can be a value of FDCAN Frame Type

Definition at line 281 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxTimestamp

Specifies the timestamp counter value captured on start of frame reception. This parameter must be a number between 0 and 0xFFFF

Definition at line 298 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_TxEventFifoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxEventFifoTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx event FIFO structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxTimestamp
uint32_t | MessageMarker
uint32_t | EventType

Detailed Description

FDCAN Tx event FIFO structure definition.

Definition at line 317 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxEventFifoTypeDef::BitRateSwitch

Specifies whether the Tx frame is transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 336 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::DataLength

Specifies the length of the transmitted frame. This parameter can be a value of FDCAN Data Length Code

Definition at line 330 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 333 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::EventType

Specifies the event type. This parameter can be a value of FDCAN Event Type

Definition at line 352 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::FDFormat

Specifies whether the Tx frame is transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 340 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 319 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::IdType

Specifies the identifier type for the transmitted message. This parameter can be a value of FDCAN ID Type

Definition at line 324 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::MessageMarker

Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 348 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxFrameType

Specifies the frame type of the transmitted message. This parameter can be a value of FDCAN Frame Type

Definition at line 327 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxTimestamp

Specifies the timestamp counter value captured on start of frame transmission. This parameter must be a number between 0 and 0xFFFF

Definition at line 344 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_HpMsgStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_HpMsgStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN High Priority Message Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | FilterList
uint32_t | FilterIndex
uint32_t | MessageStorage
uint32_t | MessageIndex

Detailed Description

FDCAN High Priority Message Status structure definition.

Definition at line 360 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_HpMsgStatusTypeDef::FilterIndex

Specifies the index of matching filter element. This parameter can be a number between:

  • 0 and 127, if FilterList is 0 (Standard)
  • 0 and 63, if FilterList is 1 (Extended)

Definition at line 367 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::FilterList

Specifies the filter list of the matching filter element. This parameter can be:

  • 0 : Standard Filter List
  • 1 : Extended Filter List

Definition at line 362 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageIndex

Specifies the Index of Rx FIFO element to which the message was stored. This parameter is valid only when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or FDCAN_HP_STORAGE_RXFIFO1

Definition at line 375 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageStorage

Specifies the HP Message Storage. This parameter can be a value of FDCAN High Priority Message Storage

Definition at line 372 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_ProtocolStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ProtocolStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN Protocol Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | LastErrorCode
uint32_t | DataLastErrorCode
uint32_t | Activity
uint32_t | ErrorPassive
uint32_t | Warning
uint32_t | BusOff
uint32_t | RxESIflag
uint32_t | RxBRSflag
uint32_t | RxFDFflag
uint32_t | ProtocolException
uint32_t | TDCvalue

Detailed Description

FDCAN Protocol Status structure definition.

Definition at line 387 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ProtocolStatusTypeDef::Activity

Specifies the FDCAN module communication state. This parameter can be a value of FDCAN communication state

Definition at line 396 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::BusOff

Specifies the FDCAN module Bus_Off status. This parameter can be:

  • 0 : The FDCAN is not in Bus_Off state
  • 1 : The FDCAN is in Bus_Off state

Definition at line 409 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::DataLastErrorCode

Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. This parameter can be a value of FDCAN protocol error code

Definition at line 392 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ErrorPassive

Specifies the FDCAN module error status. This parameter can be:

  • 0 : The FDCAN is in Error_Active state
  • 1 : The FDCAN is in Error_Passive state

Definition at line 399 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::LastErrorCode

Specifies the type of the last error that occurred on the FDCAN bus. This parameter can be a value of FDCAN protocol error code

Definition at line 389 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ProtocolException

Specifies the FDCAN module Protocol Exception status. This parameter can be:

  • 0 : No protocol exception event occurred since last read access
  • 1 : Protocol exception event occurred

Definition at line 429 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxBRSflag

Specifies BRS flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its BRS flag set
  • 1 : Last received CAN FD message had its BRS flag set

Definition at line 419 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxESIflag

Specifies ESI flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its ESI flag set
  • 1 : Last received CAN FD message had its ESI flag set

Definition at line 414 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxFDFflag

Specifies if CAN FD message (FDF flag set) has been received since last protocol status. This parameter can be:

  • 0 : no CAN FD message received
  • 1 : CAN FD message received

Definition at line 424 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::TDCvalue

Specifies the Transmitter Delay Compensation Value. This parameter can be a number between 0 and 127

Definition at line 434 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::Warning

Specifies the FDCAN module warning status. This parameter can be:

  • 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
  • 1 : at least one of error counters has reached the Error_Warning limit of 96

Definition at line 404 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_ErrorCountersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ErrorCountersTypeDef Struct Reference
FDCAN Exported Types

FDCAN Error Counters structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | TxErrorCnt
uint32_t | RxErrorCnt
uint32_t | RxErrorPassive
uint32_t | ErrorLogging

Detailed Description

FDCAN Error Counters structure definition.

Definition at line 442 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ErrorCountersTypeDef::ErrorLogging

Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW

Definition at line 455 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorCnt

Specifies the Receive Error Counter Value. This parameter can be a number between 0 and 127

Definition at line 447 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorPassive

Specifies the Receive Error Passive status. This parameter can be:

  • 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
  • 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128

Definition at line 450 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::TxErrorCnt

Specifies the Transmit Error Counter Value. This parameter can be a number between 0 and 255

Definition at line 444 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_TT_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TT_ConfigTypeDef Struct Reference
FDCAN Exported Types

FDCAN TT Init structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | OperationMode
uint32_t | GapEnable
uint32_t | TimeMaster
uint32_t | SyncDevLimit
uint32_t | InitRefTrigOffset
uint32_t | ExternalClkSync
uint32_t | AppWdgLimit
uint32_t | GlobalTimeFilter
uint32_t | ClockCalibration
uint32_t | EvtTrigPolarity
uint32_t | BasicCyclesNbr
uint32_t | CycleStartSync
uint32_t | TxEnableWindow
uint32_t | ExpTxTrigNbr
uint32_t | TURNumerator
uint32_t | TURDenominator
uint32_t | TriggerMemoryNbr
uint32_t | StopWatchTrigSel
uint32_t | EventTrigSel

Detailed Description

FDCAN TT Init structure definition.

Definition at line 466 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TT_ConfigTypeDef::AppWdgLimit

Specifies the Application Watchdog Limit : maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. The application watchdog can be disabled by setting AppWdgLimit to 0. This parameter must be a number between 0 and 255. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 492 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::BasicCyclesNbr

Specifies the nubmer of basic cycles in the system matrix. This parameter can be a value of FDCAN TT Basic Cycle Number

Definition at line 515 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ClockCalibration

Enable or disable Automatic Clock Calibration. This parameter can be a value of FDCAN TT Automatic Clock Calibration. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 505 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::CycleStartSync

Enable or disable synchronization pulse output at pin fdcan1_soc. This parameter can be a value of FDCAN TT Cycle Start Sync

Definition at line 518 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::EventTrigSel

Specifies the input to be used as event trigger. This parameter can be a value of FDCAN TT Event Trigger Selection

Definition at line 542 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::EvtTrigPolarity

Specifies the Event Trigger Polarity. This parameter can be a value of FDCAN TT Event Trigger Polarity. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 510 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ExpTxTrigNbr

Specifies the number of expected Tx_Triggers in the system matrix. This is the sum of Tx_Triggers for exclusive, single arbitrating and merged arbitrating windows. This parameter must be a number between 0 and 4095

Definition at line 524 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ExternalClkSync

Enable or disable External Clock Synchronization. This parameter can be a value of FDCAN TT External Clock Synchronization. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 487 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::GapEnable

Specifies the FDCAN TT Operation. This parameter can be a value of FDCAN TT Operation. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 471 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::GlobalTimeFilter

Enable or disable Global Time Filtering. This parameter can be a value of FDCAN TT Global Time Filtering. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 500 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::InitRefTrigOffset

Specifies the Initial Reference Trigger Offset. This parameter must be a number between 0 and 127

Definition at line 484 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::OperationMode

Specifies the FDCAN Operation Mode. This parameter can be a value of FDCAN Operation Mode

Definition at line 468 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::StopWatchTrigSel

Specifies the input to be used as stop watch trigger. This parameter can be a value of FDCAN TT Stop Watch Trigger Selection

Definition at line 539 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::SyncDevLimit

Specifies the Synchronization Deviation Limit SDL of the TUR numerator : TUR = (Numerator ± SDL) / Denominator. With : SDL = 2^(SyncDevLimit+5). This parameter must be a number between 0 and 7

Definition at line 479 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TimeMaster

Specifies whether the instance is a slave or a potential master. This parameter can be a value of FDCAN TT Time Master

Definition at line 476 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TriggerMemoryNbr

Specifies the number of trigger memory elements. This parameter must be a number between 0 and 64

Definition at line 536 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TURDenominator

Specifies the TUR (Time Unit Ratio) denominator. This parameter must be a number between 0x0001 and 0x3FFF

Definition at line 533 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TURNumerator

Specifies the TUR (Time Unit Ratio) numerator. It is adviced to set this parameter to the largest applicable value. This parameter must be a number between 0x10000 and 0x1FFFF

Definition at line 529 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TxEnableWindow

Specifies the length of Tx enable window in NTUs. This parameter must be a number between 1 and 16

Definition at line 521 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_TriggerTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TriggerTypeDef Struct Reference
FDCAN Exported Types

FDCAN Trigger structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | TriggerIndex
uint32_t | TimeMark
uint32_t | RepeatFactor
uint32_t | StartCycle
uint32_t | TmEventInt
uint32_t | TmEventExt
uint32_t | TriggerType
uint32_t | FilterType
uint32_t | TxBufferIndex
uint32_t | FilterIndex

Detailed Description

FDCAN Trigger structure definition.

Definition at line 550 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TriggerTypeDef::FilterIndex

Specifies the filter for which the trigger is valid. This parameter is taken in consideration only if the trigger is configured for reception. This parameter must be a number between:

  • 0 and 127, if FilterType is FDCAN_STANDARD_ID
  • 0 and 63, if FilterType is FDCAN_EXTENDED_ID

Definition at line 586 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::FilterType

Specifies the filter identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 578 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::RepeatFactor

Specifies the trigger repeat factor. This parameter can be a value of FDCAN TT repeat factor

Definition at line 558 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::StartCycle

Specifies the index of the first cycle in which the trigger becomes active. This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. This parameter must be a number between 0 and RepeatFactor

Definition at line 561 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TimeMark

Specifies the cycle time for which the trigger becomes active. This parameter must be a number between 0 and 0xFFFF

Definition at line 555 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TmEventExt

Enable or disable the external time mark event. If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when trigger memory element becomes active. This parameter can be a value of FDCAN TT time mark event external

Definition at line 570 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TmEventInt

Enable or disable the internal time mark event. If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element becomes active. This parameter can be a value of FDCAN TT time mark event internal

Definition at line 565 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TriggerIndex

Specifies the trigger which will be configured. This parameter must be a number between 0 and 63

Definition at line 552 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TriggerType

Specifies the trigger type. This parameter can be a value of FDCAN TT trigger type

Definition at line 575 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TxBufferIndex

Specifies the index of the Tx buffer for which the trigger is valid. This parameter can be a value of FDCAN Tx Location. This parameter is taken in consideration only if the trigger is configured for transmission.

Definition at line 581 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_TTOperationStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TTOperationStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN TT Operation Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | ErrorLevel
uint32_t | MasterState
uint32_t | SyncState
uint32_t | GTimeQuality
uint32_t | ClockQuality
uint32_t | RefTrigOffset
uint32_t | GTimeDiscPending
uint32_t | GapFinished
uint32_t | MasterPriority
uint32_t | GapStarted
uint32_t | WaitForEvt
uint32_t | AppWdgEvt
uint32_t | ECSPending
uint32_t | PhaseLock

Detailed Description

FDCAN TT Operation Status structure definition.

Definition at line 598 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TTOperationStatusTypeDef::AppWdgEvt

Specifies the Application Watchdog State. This parameter can be:

  • 0 : Application Watchdog served in time
  • 1 : Failed to serve Application Watchdog in time

Definition at line 647 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ClockQuality

Specifies the Quality of Clock Speed. This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. This parameter can be:

  • 0 : Local clock speed not synchronized to Time Master clock speed
  • 1 : Synchronization Deviation = SDL

Definition at line 615 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ECSPending

Specifies the External Clock Synchronization State. This parameter can be:

  • 0 : No external clock synchronization pending
  • 1 : Node waits for external clock synchronization to take effect

Definition at line 652 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ErrorLevel

Specifies the type of the TT operation error level. This parameter can be a value of FDCAN TT Error Level

Definition at line 600 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GapFinished

Specifies whether a Gap is finished. This parameter can be:

  • 0 : Reset at the end of each reference message
  • 1 : Gap finished

Definition at line 629 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GapStarted

Specifies whether a Gap is started. This parameter can be:

  • 0 : No Gap in schedule
  • 1 : Gap time after Basic Cycle has started

Definition at line 637 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GTimeDiscPending

Specifies the Global Time Discontinuity State. This parameter can be:

  • 0 : No global time preset pending
  • 1 : Node waits for the global time preset to take effect

Definition at line 624 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GTimeQuality

Specifies the Quality of Global Time Phase. This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. This parameter can be:

  • 0 : Global time not valid
  • 1 : Global time in phase with Time Master

Definition at line 609 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::MasterPriority

Specifies the Priority of actual Time Master. This parameter can be a number between 0 and 0x7

Definition at line 634 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::MasterState

Specifies the type of the TT master state. This parameter can be a value of FDCAN TT Master State

Definition at line 603 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::PhaseLock

Specifies the Phase Lock State. This parameter can be:

  • 0 : Phase outside range
  • 1 : Phase inside range

Definition at line 657 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::RefTrigOffset

Specifies the Actual Reference Trigger Offset Value. This parameter can be a number between 0 and 0xFF

Definition at line 621 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::SyncState

Specifies the type of the TT synchronization state. This parameter can be a value of FDCAN TT Synchronization State

Definition at line 606 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::WaitForEvt

Specifies whether a Gap is annouced. This parameter can be:

  • 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
  • 1 : Reference message with Next_is_Gap = 1 received

Definition at line 642 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN_MsgRamAddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_MsgRamAddressTypeDef Struct Reference
FDCAN Exported Types

FDCAN Message RAM blocks. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | StandardFilterSA
uint32_t | ExtendedFilterSA
uint32_t | RxFIFO0SA
uint32_t | RxFIFO1SA
uint32_t | RxBufferSA
uint32_t | TxEventFIFOSA
uint32_t | TxBufferSA
uint32_t | TxFIFOQSA
uint32_t | TTMemorySA
uint32_t | EndAddress

Detailed Description

FDCAN Message RAM blocks.

Definition at line 667 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_MsgRamAddressTypeDef::EndAddress

Specifies the End Address of the allocated RAM. This parameter must be a 32-bit word address

Definition at line 696 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA

Specifies the Extended Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 672 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::RxBufferSA

Specifies the Rx Buffer Start Address. This parameter must be a 32-bit word address

Definition at line 681 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO0SA

Specifies the Rx FIFO 0 Start Address. This parameter must be a 32-bit word address

Definition at line 675 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO1SA

Specifies the Rx FIFO 1 Start Address. This parameter must be a 32-bit word address

Definition at line 678 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::StandardFilterSA

Specifies the Standard Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 669 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::TTMemorySA

Specifies the Trigger Memory Start Address. This parameter must be a 32-bit word address

Definition at line 693 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_MsgRamAddressTypeDef::TxBufferSA

Specifies the Tx Buffers Start Address. This parameter must be a 32-bit word address

Definition at line 687 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and FDCAN_CopyMessageToRAM().

uint32_t FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA

Specifies the Tx Event FIFO Start Address. This parameter must be a 32-bit word address

Definition at line 684 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_MsgRamAddressTypeDef::TxFIFOQSA

Specifies the Tx FIFO/Queue Start Address. This parameter must be a 32-bit word address

Definition at line 690 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __FDCAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__FDCAN_HandleTypeDef Struct Reference
FDCAN Exported Types

FDCAN handle structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

FDCAN_GlobalTypeDef * | Instance
TTCAN_TypeDef * | ttcan
FDCAN_InitTypeDef Init
FDCAN_MsgRamAddressTypeDef msgRam
uint32_t | LatestTxFifoQRequest
__IO HAL_FDCAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
void(* | ClockCalibrationCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
void(* | TxEventFifoCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
void(* | RxFifo0Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
void(* | RxFifo1Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
void(* | TxFifoEmptyCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TxBufferCompleteCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | TxBufferAbortCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | RxBufferNewMessageCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | HighPriorityMessageCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimestampWraparoundCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimeoutOccurredCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorStatusCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
void(* | TT_ScheduleSyncCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
void(* | TT_TimeMarkCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
void(* | TT_StopWatchCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
void(* | TT_GlobalTimeCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
void(* | MspInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | MspDeInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)

Detailed Description

FDCAN handle structure definition.

Definition at line 705 of file stm32h7xx_hal_fdcan.h.

Field Documentation

void(* __FDCAN_HandleTypeDef::ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)

FDCAN Clock Calibration callback

Definition at line 728 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterClockCalibrationCallback(), and HAL_FDCAN_UnRegisterClockCalibrationCallback().

void(* __FDCAN_HandleTypeDef::ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Error callback

Definition at line 739 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

__IO uint32_t __FDCAN_HandleTypeDef::ErrorCode

FDCAN Error code

Definition at line 725 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetError(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTTGlobalTimeCallback(), HAL_FDCAN_RegisterTTScheduleSyncCallback(), HAL_FDCAN_RegisterTTStopWatchCallback(), HAL_FDCAN_RegisterTTTimeMarkCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_ResetClockCalibrationState(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), HAL_FDCAN_TT_SetNextIsGap(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterClockCalibrationCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTTGlobalTimeCallback(), HAL_FDCAN_UnRegisterTTScheduleSyncCallback(), HAL_FDCAN_UnRegisterTTStopWatchCallback(), HAL_FDCAN_UnRegisterTTTimeMarkCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

FDCAN Error status callback

Definition at line 740 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterErrorStatusCallback(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void(* __FDCAN_HandleTypeDef::HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN High priority message callback

Definition at line 736 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

FDCAN_InitTypeDef __FDCAN_HandleTypeDef::Init

FDCAN required parameters

Definition at line 714 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Init().

FDCAN_GlobalTypeDef* __FDCAN_HandleTypeDef::Instance

Register base address

Definition at line 710 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetErrorCounters(), HAL_FDCAN_GetHighPriorityMessageStatus(), HAL_FDCAN_GetProtocolStatus(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTimeoutCounter(), HAL_FDCAN_GetTimestampCounter(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_GetTxFifoFreeLevel(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_IsRestrictedOperationMode(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FDCAN_ResetClockCalibrationState(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

uint32_t __FDCAN_HandleTypeDef::LatestTxFifoQRequest

FDCAN Tx buffer index of latest Tx FIFO/Queue request

Definition at line 718 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetLatestTxFifoQRequestBuffer(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

HAL_LockTypeDef __FDCAN_HandleTypeDef::Lock

FDCAN locking object

Definition at line 723 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FDCAN_MsgRamAddressTypeDef __FDCAN_HandleTypeDef::msgRam

FDCAN Message RAM blocks

Definition at line 716 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_ConfigTrigger().

void(* __FDCAN_HandleTypeDef::MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp DeInit callback

Definition at line 747 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp Init callback

Definition at line 746 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Rx Buffer New Message callback

Definition at line 735 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

FDCAN Rx Fifo 0 callback

Definition at line 730 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo0Callback(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void(* __FDCAN_HandleTypeDef::RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

FDCAN Rx Fifo 1 callback

Definition at line 731 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo1Callback(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

__IO HAL_FDCAN_StateTypeDef __FDCAN_HandleTypeDef::State

FDCAN communication state

Definition at line 721 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetState(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTTGlobalTimeCallback(), HAL_FDCAN_RegisterTTScheduleSyncCallback(), HAL_FDCAN_RegisterTTStopWatchCallback(), HAL_FDCAN_RegisterTTTimeMarkCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_ResetClockCalibrationState(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), HAL_FDCAN_TT_SetNextIsGap(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterClockCalibrationCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTTGlobalTimeCallback(), HAL_FDCAN_UnRegisterTTScheduleSyncCallback(), HAL_FDCAN_UnRegisterTTStopWatchCallback(), HAL_FDCAN_UnRegisterTTTimeMarkCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timeout occurred callback

Definition at line 738 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timestamp wraparound callback

Definition at line 737 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)

FDCAN TT Global Time callback

Definition at line 744 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTTGlobalTimeCallback(), and HAL_FDCAN_UnRegisterTTGlobalTimeCallback().

void(* __FDCAN_HandleTypeDef::TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)

FDCAN T Schedule Synchronization callback

Definition at line 741 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTTScheduleSyncCallback(), and HAL_FDCAN_UnRegisterTTScheduleSyncCallback().

void(* __FDCAN_HandleTypeDef::TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)

FDCAN TT Stop Watch callback

Definition at line 743 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTTStopWatchCallback(), and HAL_FDCAN_UnRegisterTTStopWatchCallback().

void(* __FDCAN_HandleTypeDef::TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)

FDCAN TT Time Mark callback

Definition at line 742 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTTTimeMarkCallback(), and HAL_FDCAN_UnRegisterTTTimeMarkCallback().

TTCAN_TypeDef* __FDCAN_HandleTypeDef::ttcan

TT register base address

Definition at line 712 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

void(* __FDCAN_HandleTypeDef::TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer abort callback

Definition at line 734 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferAbortCallback(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void(* __FDCAN_HandleTypeDef::TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer complete callback

Definition at line 733 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void(* __FDCAN_HandleTypeDef::TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

FDCAN Tx Event Fifo callback

Definition at line 729 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxEventFifoCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Tx Fifo Empty callback

Definition at line 732 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL FDCAN Error Code

Defines
HAL FDCAN Error Code
FDCAN Exported Constants

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE
#define | HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU
#define | HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO
#define | HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1
#define | HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2
#define | HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT
#define | HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT
#define | HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW
#define | HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Define Documentation

#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)

Put element in full FIFO

Definition at line 808 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)

Get element from empty FIFO

Definition at line 809 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Invalid Callback error

Definition at line 826 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTTGlobalTimeCallback(), HAL_FDCAN_RegisterTTScheduleSyncCallback(), HAL_FDCAN_RegisterTTStopWatchCallback(), HAL_FDCAN_RegisterTTTimeMarkCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterClockCalibrationCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTTGlobalTimeCallback(), HAL_FDCAN_UnRegisterTTScheduleSyncCallback(), HAL_FDCAN_UnRegisterTTStopWatchCallback(), HAL_FDCAN_UnRegisterTTTimeMarkCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO

Overflow of CAN Error Logging Counter

Definition at line 810 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 799 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)

Peripheral not initialized

Definition at line 801 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)

Peripheral not ready

Definition at line 802 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_ResetClockCalibrationState(), HAL_FDCAN_Start(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)

Peripheral not started

Definition at line 803 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Stop().

#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)

Mode not supported

Definition at line 804 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)

Parameter error

Definition at line 805 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_ResetClockCalibrationState(), and HAL_FDCAN_TT_ConfigOperation().

#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)

Pending operation

Definition at line 806 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_SetClockSynchronization(), and HAL_FDCAN_TT_SetGlobalTime().

#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA

Protocol Error in Arbitration Phase (Nominal Bit Time is used)

Definition at line 812 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED

Protocol Error in Data Phase (Data Bit Time is used)

Definition at line 813 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)

Message RAM Access Failure

Definition at line 807 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI

Message RAM Watchdog event occurred

Definition at line 811 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA

Access to Reserved Address

Definition at line 814 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 800 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW

Application watchdog not served in time

Definition at line 822 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER

Error found in trigger list

Definition at line 823 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE

Global Time Error : Synchronization deviation exceeded limit

Definition at line 815 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT

No system startup due to missing reference message

Definition at line 820 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT

Missing reference message

Definition at line 821 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1

Scheduling error 1

Definition at line 818 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2

Scheduling error 2

Definition at line 819 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO

Tx Count Overflow : More Tx trigger than expected in one matrix cycle

Definition at line 817 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU

Tx Count Underflow : Less Tx trigger than expected in one matrix cycle

Definition at line 816 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Frame Format

Defines
FDCAN Frame Format
FDCAN Exported Constants

Defines

#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

Define Documentation

#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)

Classic mode

Definition at line 835 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

FD mode with BitRate Switching

Definition at line 837 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)

FD mode without BitRate Switching

Definition at line 836 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Operating Mode

Defines
FDCAN Operating Mode
FDCAN Exported Constants

Defines

#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)

Bus Monitoring mode

Definition at line 847 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

External LoopBack mode

Definition at line 849 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)

Internal LoopBack mode

Definition at line 848 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 845 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)

Restricted Operation mode

Definition at line 846 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Clock Calibration

Defines
FDCAN Clock Calibration
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U)

Disable Clock Calibration

Definition at line 857 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U)

Enable Clock Calibration

Definition at line 858 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Clock Divider

Defines
FDCAN Clock Divider
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)

Divide kernel clock by 1

Definition at line 866 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)

Divide kernel clock by 10

Definition at line 871 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)

Divide kernel clock by 12

Definition at line 872 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)

Divide kernel clock by 14

Definition at line 873 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)

Divide kernel clock by 16

Definition at line 874 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)

Divide kernel clock by 18

Definition at line 875 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)

Divide kernel clock by 2

Definition at line 867 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)

Divide kernel clock by 20

Definition at line 876 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)

Divide kernel clock by 22

Definition at line 877 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)

Divide kernel clock by 24

Definition at line 878 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)

Divide kernel clock by 26

Definition at line 879 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)

Divide kernel clock by 28

Definition at line 880 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)

Divide kernel clock by 30

Definition at line 881 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)

Divide kernel clock by 4

Definition at line 868 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)

Divide kernel clock by 6

Definition at line 869 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)

Divide kernel clock by 8

Definition at line 870 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Calibration Field Length

Defines
FDCAN Calibration Field Length
FDCAN Exported Constants

Defines

#define | FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)

Define Documentation

#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)

Calibration field length is 32 bits

Definition at line 889 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)

Calibration field length is 64 bits

Definition at line 890 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Calibration State

Defines
FDCAN Calibration State
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)
#define | FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)

Clock basic calibrated

Definition at line 899 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)

Clock not calibrated

Definition at line 898 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)

Clock precision calibrated

Definition at line 900 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Calibration Counter

Defines
FDCAN Calibration Counter
FDCAN Exported Constants

Defines

#define | FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)
#define | FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)

Oscillator Clock Period Counter

Definition at line 909 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetClockCalibrationCounter().

#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)

Time Quanta Counter

Definition at line 908 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetClockCalibrationCounter().

#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)

Calibration Watchdog Counter

Definition at line 910 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Data Field Size

Defines
FDCAN Data Field Size
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)
#define | FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)
#define | FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)
#define | FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)
#define | FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)
#define | FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)
#define | FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)

Define Documentation

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)

12 bytes data field

Definition at line 919 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)

16 bytes data field

Definition at line 920 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)

20 bytes data field

Definition at line 921 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)

24 bytes data field

Definition at line 922 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)

32 bytes data field

Definition at line 923 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)

48 bytes data field

Definition at line 924 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)

64 bytes data field

Definition at line 925 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)

8 bytes data field

Definition at line 918 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Tx FIFO/Queue Mode

Defines
FDCAN Tx FIFO/Queue Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Define Documentation

#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)

FIFO mode

Definition at line 933 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Queue mode

Definition at line 934 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN ID Type

Defines
FDCAN ID Type
FDCAN Exported Constants

Defines

#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Define Documentation

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Extended ID element

Definition at line 943 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_TT_ConfigReferenceMessage().

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U)

Standard ID element

Definition at line 942 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Frame Type

Defines
FDCAN Frame Type
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Define Documentation

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U)

Data frame

Definition at line 951 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Remote frame

Definition at line 952 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Data Length Code

Defines
FDCAN Data Length Code
FDCAN Exported Constants

Defines

#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)

0 bytes data field

Definition at line 960 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)

1 bytes data field

Definition at line 961 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)

12 bytes data field

Definition at line 969 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)

16 bytes data field

Definition at line 970 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)

2 bytes data field

Definition at line 962 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)

20 bytes data field

Definition at line 971 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)

24 bytes data field

Definition at line 972 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)

3 bytes data field

Definition at line 963 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)

32 bytes data field

Definition at line 973 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)

4 bytes data field

Definition at line 964 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)

48 bytes data field

Definition at line 974 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)

5 bytes data field

Definition at line 965 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)

6 bytes data field

Definition at line 966 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

64 bytes data field

Definition at line 975 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)

7 bytes data field

Definition at line 967 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)

8 bytes data field

Definition at line 968 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Error State Indicator

Defines
FDCAN Error State Indicator
FDCAN Exported Constants

Defines

#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)

Transmitting node is error active

Definition at line 983 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Transmitting node is error passive

Definition at line 984 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Bit Rate Switching

Defines
FDCAN Bit Rate Switching
FDCAN Exported Constants

Defines

#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)

Define Documentation

#define FDCAN_BRS_OFF ((uint32_t)0x00000000U)

FDCAN frames transmitted/received without bit rate switching

Definition at line 992 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_BRS_ON ((uint32_t)0x00100000U)

FDCAN frames transmitted/received with bit rate switching

Definition at line 993 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN format

Defines
FDCAN format
FDCAN Exported Constants

Defines

#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)

Define Documentation

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)

Frame transmitted/received in Classic CAN format

Definition at line 1001 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FD_CAN ((uint32_t)0x00200000U)

Frame transmitted/received in FDCAN format

Definition at line 1002 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Event FIFO control

Defines
FDCAN Event FIFO control
FDCAN Exported Constants

Defines

#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)

Do not store Tx events

Definition at line 1010 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Store Tx events

Definition at line 1011 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Filter Type

Defines
FDCAN Filter Type
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)

Dual ID filter for FilterID1 or FilterID2

Definition at line 1020 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U)

Classic filter: FilterID1 = filter, FilterID2 = mask

Definition at line 1021 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)

Range filter from FilterID1 to FilterID2

Definition at line 1019 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Range filter from FilterID1 to FilterID2, EIDM mask not applied

Definition at line 1022 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Filter Configuration

Defines
FDCAN Filter Configuration
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)

Disable filter element

Definition at line 1030 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_HP ((uint32_t)0x00000004U)

Set high priority if filter matches

Definition at line 1034 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)

Reject ID if filter matches

Definition at line 1033 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)

Store into Rx Buffer, configuration of FilterType ignored

Definition at line 1037 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)

Store in Rx FIFO 0 if filter matches

Definition at line 1031 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)

Set high priority and store in FIFO 0 if filter matches

Definition at line 1035 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)

Store in Rx FIFO 1 if filter matches

Definition at line 1032 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Set high priority and store in FIFO 1 if filter matches

Definition at line 1036 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Tx Location

Defines
FDCAN Tx Location
FDCAN Exported Constants

Defines

#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)
#define | FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)
#define | FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)
#define | FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)
#define | FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)
#define | FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)
#define | FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)
#define | FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)
#define | FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)
#define | FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)
#define | FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)
#define | FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)
#define | FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)
#define | FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)
#define | FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)
#define | FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)
#define | FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)
#define | FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)
#define | FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)
#define | FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)
#define | FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)
#define | FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)
#define | FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)
#define | FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)
#define | FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)
#define | FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)
#define | FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)
#define | FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)
#define | FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)

Add message to Tx Buffer 0

Definition at line 1045 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)

Add message to Tx Buffer 1

Definition at line 1046 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)

Add message to Tx Buffer 10

Definition at line 1055 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)

Add message to Tx Buffer 11

Definition at line 1056 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)

Add message to Tx Buffer 12

Definition at line 1057 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)

Add message to Tx Buffer 13

Definition at line 1058 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)

Add message to Tx Buffer 14

Definition at line 1059 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)

Add message to Tx Buffer 15

Definition at line 1060 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)

Add message to Tx Buffer 16

Definition at line 1061 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)

Add message to Tx Buffer 17

Definition at line 1062 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)

Add message to Tx Buffer 18

Definition at line 1063 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)

Add message to Tx Buffer 19

Definition at line 1064 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Add message to Tx Buffer 2

Definition at line 1047 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)

Add message to Tx Buffer 20

Definition at line 1065 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)

Add message to Tx Buffer 21

Definition at line 1066 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)

Add message to Tx Buffer 22

Definition at line 1067 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)

Add message to Tx Buffer 23

Definition at line 1068 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)

Add message to Tx Buffer 24

Definition at line 1069 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)

Add message to Tx Buffer 25

Definition at line 1070 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)

Add message to Tx Buffer 26

Definition at line 1071 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)

Add message to Tx Buffer 27

Definition at line 1072 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)

Add message to Tx Buffer 28

Definition at line 1073 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)

Add message to Tx Buffer 29

Definition at line 1074 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)

Add message to Tx Buffer 3

Definition at line 1048 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)

Add message to Tx Buffer 30

Definition at line 1075 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)

Add message to Tx Buffer 31

Definition at line 1076 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)

Add message to Tx Buffer 4

Definition at line 1049 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)

Add message to Tx Buffer 5

Definition at line 1050 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)

Add message to Tx Buffer 6

Definition at line 1051 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)

Add message to Tx Buffer 7

Definition at line 1052 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)

Add message to Tx Buffer 8

Definition at line 1053 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)

Add message to Tx Buffer 9

Definition at line 1054 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Rx Location

Defines
FDCAN Rx Location
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)
#define | FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)
#define | FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)
#define | FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)
#define | FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)
#define | FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)
#define | FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)
#define | FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)
#define | FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)
#define | FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)
#define | FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)
#define | FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)
#define | FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)
#define | FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)
#define | FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)
#define | FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)
#define | FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)
#define | FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)
#define | FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)
#define | FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)
#define | FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)
#define | FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)
#define | FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)
#define | FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)
#define | FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)
#define | FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)
#define | FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)
#define | FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)
#define | FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)
#define | FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)
#define | FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)
#define | FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)
#define | FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)
#define | FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)
#define | FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)
#define | FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)
#define | FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)
#define | FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)
#define | FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)
#define | FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)
#define | FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)
#define | FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)
#define | FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)
#define | FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)
#define | FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)
#define | FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)
#define | FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)
#define | FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)
#define | FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)
#define | FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)
#define | FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)
#define | FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)
#define | FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)
#define | FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)
#define | FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)
#define | FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)
#define | FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)
#define | FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)
#define | FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)
#define | FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)
#define | FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)
#define | FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)
#define | FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)
#define | FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)

Define Documentation

#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)

Get received message from Rx Buffer 0

Definition at line 1086 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)

Get received message from Rx Buffer 1

Definition at line 1087 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)

Get received message from Rx Buffer 10

Definition at line 1096 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)

Get received message from Rx Buffer 11

Definition at line 1097 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)

Get received message from Rx Buffer 12

Definition at line 1098 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)

Get received message from Rx Buffer 13

Definition at line 1099 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)

Get received message from Rx Buffer 14

Definition at line 1100 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)

Get received message from Rx Buffer 15

Definition at line 1101 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)

Get received message from Rx Buffer 16

Definition at line 1102 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)

Get received message from Rx Buffer 17

Definition at line 1103 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)

Get received message from Rx Buffer 18

Definition at line 1104 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)

Get received message from Rx Buffer 19

Definition at line 1105 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)

Get received message from Rx Buffer 2

Definition at line 1088 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)

Get received message from Rx Buffer 20

Definition at line 1106 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)

Get received message from Rx Buffer 21

Definition at line 1107 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)

Get received message from Rx Buffer 22

Definition at line 1108 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)

Get received message from Rx Buffer 23

Definition at line 1109 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)

Get received message from Rx Buffer 24

Definition at line 1110 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)

Get received message from Rx Buffer 25

Definition at line 1111 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)

Get received message from Rx Buffer 26

Definition at line 1112 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)

Get received message from Rx Buffer 27

Definition at line 1113 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)

Get received message from Rx Buffer 28

Definition at line 1114 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)

Get received message from Rx Buffer 29

Definition at line 1115 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)

Get received message from Rx Buffer 3

Definition at line 1089 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)

Get received message from Rx Buffer 30

Definition at line 1116 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)

Get received message from Rx Buffer 31

Definition at line 1117 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)

Get received message from Rx Buffer 32

Definition at line 1118 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)

Get received message from Rx Buffer 33

Definition at line 1119 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)

Get received message from Rx Buffer 34

Definition at line 1120 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)

Get received message from Rx Buffer 35

Definition at line 1121 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)

Get received message from Rx Buffer 36

Definition at line 1122 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)

Get received message from Rx Buffer 37

Definition at line 1123 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)

Get received message from Rx Buffer 38

Definition at line 1124 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)

Get received message from Rx Buffer 39

Definition at line 1125 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)

Get received message from Rx Buffer 4

Definition at line 1090 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)

Get received message from Rx Buffer 40

Definition at line 1126 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)

Get received message from Rx Buffer 41

Definition at line 1127 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)

Get received message from Rx Buffer 42

Definition at line 1128 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)

Get received message from Rx Buffer 43

Definition at line 1129 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)

Get received message from Rx Buffer 44

Definition at line 1130 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)

Get received message from Rx Buffer 45

Definition at line 1131 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)

Get received message from Rx Buffer 46

Definition at line 1132 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)

Get received message from Rx Buffer 47

Definition at line 1133 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)

Get received message from Rx Buffer 48

Definition at line 1134 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)

Get received message from Rx Buffer 49

Definition at line 1135 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)

Get received message from Rx Buffer 5

Definition at line 1091 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)

Get received message from Rx Buffer 50

Definition at line 1136 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)

Get received message from Rx Buffer 51

Definition at line 1137 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)

Get received message from Rx Buffer 52

Definition at line 1138 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)

Get received message from Rx Buffer 53

Definition at line 1139 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)

Get received message from Rx Buffer 54

Definition at line 1140 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)

Get received message from Rx Buffer 55

Definition at line 1141 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)

Get received message from Rx Buffer 56

Definition at line 1142 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)

Get received message from Rx Buffer 57

Definition at line 1143 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)

Get received message from Rx Buffer 58

Definition at line 1144 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)

Get received message from Rx Buffer 59

Definition at line 1145 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)

Get received message from Rx Buffer 6

Definition at line 1092 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)

Get received message from Rx Buffer 60

Definition at line 1146 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)

Get received message from Rx Buffer 61

Definition at line 1147 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)

Get received message from Rx Buffer 62

Definition at line 1148 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)

Get received message from Rx Buffer 63

Definition at line 1149 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)

Get received message from Rx Buffer 7

Definition at line 1093 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)

Get received message from Rx Buffer 8

Definition at line 1094 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)

Get received message from Rx Buffer 9

Definition at line 1095 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)

Get received message from Rx FIFO 0

Definition at line 1084 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Get received message from Rx FIFO 1

Definition at line 1085 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Event Type

Defines
FDCAN Event Type
FDCAN Exported Constants

Defines

#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_TX_EVENT ((uint32_t)0x00400000U)

Tx event

Definition at line 1157 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Transmission in spite of cancellation

Definition at line 1158 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN High Priority Message Storage

Defines
FDCAN High Priority Message Storage
FDCAN Exported Constants

Defines

#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)

FIFO message lost

Definition at line 1167 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)

No FIFO selected

Definition at line 1166 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)

Message stored in FIFO 0

Definition at line 1168 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Message stored in FIFO 1

Definition at line 1169 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN protocol error code

Defines
FDCAN protocol error code
FDCAN Exported Constants

Defines

#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)

Acknowledge error

Definition at line 1180 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)

Bit 0 (dominant) error

Definition at line 1182 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)

Bit 1 (recessive) error

Definition at line 1181 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)

CRC check sum error

Definition at line 1183 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)

Form error

Definition at line 1179 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

No change since last read

Definition at line 1184 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)

No error occurred

Definition at line 1177 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)

Stuff error

Definition at line 1178 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN communication state

Defines
FDCAN communication state
FDCAN Exported Constants

Defines

#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Define Documentation

#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)

Node is neither receiver nor transmitter

Definition at line 1193 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)

Node is operating as receiver

Definition at line 1194 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)

Node is synchronizing on CAN communication

Definition at line 1192 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Node is operating as transmitter

Definition at line 1195 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN FIFO watermark

Defines
FDCAN FIFO watermark
FDCAN Exported Constants

Defines

#define | FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)

Rx FIFO0

Definition at line 1204 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)

Rx FIFO1

Definition at line 1205 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)

Tx event FIFO

Definition at line 1203 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

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STM32H7B3xQ HAL User Manual: FDCAN FIFO operation mode

Defines
FDCAN FIFO operation mode
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)

Rx FIFO blocking mode

Definition at line 1213 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)

Rx FIFO overwrite mode

Definition at line 1214 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN non-matching frames

Defines
FDCAN non-matching frames
FDCAN Exported Constants

Defines

#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)

Accept in Rx FIFO 0

Definition at line 1222 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)

Accept in Rx FIFO 1

Definition at line 1223 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_REJECT ((uint32_t)0x00000002U)

Reject

Definition at line 1224 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN reject remote frames

Defines
FDCAN reject remote frames
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)

Filter remote frames

Definition at line 1232 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Reject all remote frames

Definition at line 1233 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN interrupt line

Defines
FDCAN interrupt line
FDCAN Exported Constants

Defines

#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)

Interrupt Line 0

Definition at line 1241 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigInterruptLines(), and HAL_FDCAN_TT_DeactivateNotification().

#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Interrupt Line 1

Definition at line 1242 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_TT_ActivateNotification(), and HAL_FDCAN_TT_DeactivateNotification().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN timestamp

Defines
FDCAN timestamp
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

External timestamp counter value used

Definition at line 1251 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimestampCounter().

#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)

Timestamp counter value incremented according to TCP

Definition at line 1250 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN timestamp prescaler

Defines
FDCAN timestamp prescaler
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)

Timestamp counter time unit in equal to CAN bit time

Definition at line 1259 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)

Timestamp counter time unit in equal to CAN bit time multipled by 10

Definition at line 1268 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 11

Definition at line 1269 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 12

Definition at line 1270 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 13

Definition at line 1271 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 14

Definition at line 1272 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 15

Definition at line 1273 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 16

Definition at line 1274 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)

Timestamp counter time unit in equal to CAN bit time multipled by 2

Definition at line 1260 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)

Timestamp counter time unit in equal to CAN bit time multipled by 3

Definition at line 1261 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)

Timestamp counter time unit in equal to CAN bit time multipled by 4

Definition at line 1262 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)

Timestamp counter time unit in equal to CAN bit time multipled by 5

Definition at line 1263 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)

Timestamp counter time unit in equal to CAN bit time multipled by 6

Definition at line 1264 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)

Timestamp counter time unit in equal to CAN bit time multipled by 7

Definition at line 1265 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)

Timestamp counter time unit in equal to CAN bit time multipled by 8

Definition at line 1266 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)

Timestamp counter time unit in equal to CAN bit time multipled by 9

Definition at line 1267 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN timeout operation

Defines
FDCAN timeout operation
FDCAN Exported Constants

Defines

#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)

Timeout continuous operation

Definition at line 1282 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter().

#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)

Timeout controlled by Rx FIFO 0

Definition at line 1284 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Timeout controlled by Rx FIFO 1

Definition at line 1285 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)

Timeout controlled by Tx Event FIFO

Definition at line 1283 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT reference message payload

Defines
FDCAN TT reference message payload
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)
#define | FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)

Define Documentation

#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)

Additional payload is taken from Tx Buffer 0

Definition at line 1294 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)

Reference message has no additional payload

Definition at line 1293 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT repeat factor

Defines
FDCAN TT repeat factor
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)
#define | FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)
#define | FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)
#define | FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)
#define | FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)

Define Documentation

#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)

Trigger valid every 16th cycle

Definition at line 1306 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)

Trigger valid every 2dn cycle

Definition at line 1303 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)

Trigger valid every 32nd cycle

Definition at line 1307 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)

Trigger valid every 4th cycle

Definition at line 1304 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)

Trigger valid every 64th cycle

Definition at line 1308 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)

Trigger valid every 8th cycle

Definition at line 1305 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)

Trigger valid for all cycles

Definition at line 1302 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

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STM32H7B3xQ HAL User Manual: FDCAN TT trigger type

Defines
FDCAN TT trigger type
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)
#define | FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)
#define | FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)
#define | FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)
#define | FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)
#define | FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)
#define | FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)
#define | FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)
#define | FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)
#define | FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)

Define Documentation

#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)

Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP

Definition at line 1326 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)

Check for the reception of periodic messages in exclusive time windows

Definition at line 1324 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)

Generate internal/external events depending on TmEventInt/TmEventExt configuration

Definition at line 1325 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)

Transmit reference message in strictly time-triggered operation

Definition at line 1316 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)

Transmit reference message in external event-synchronized time-triggered operation

Definition at line 1317 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)

Start a transmission in an arbitration time window

Definition at line 1320 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)

Start a continuous transmission in an exclusive time window

Definition at line 1319 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)

Start a merged arbitration window

Definition at line 1321 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)

Start a single transmission in an exclusive time window

Definition at line 1318 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)

Check for missing reference messages in strictly time-triggered operation

Definition at line 1322 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)

Check for missing reference messages in external event-synchronized time-triggered operation

Definition at line 1323 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT time mark event internal

Defines
FDCAN TT time mark event internal
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)

Define Documentation

#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)

Internal event is generated when trigger becomes active

Definition at line 1335 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)

No action

Definition at line 1334 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT time mark event external

Defines
FDCAN TT time mark event external
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)

Define Documentation

#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)

External event (pulse) is generated when trigger becomes active

Definition at line 1344 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)

No action

Definition at line 1343 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Operation Mode

Defines
FDCAN Operation Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)

Time triggered communication, level 0

Definition at line 1354 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetEndOfGap(), and HAL_FDCAN_TT_SetNextIsGap().

#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)

Time triggered communication, level 1

Definition at line 1352 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)

Time triggered communication, level 2

Definition at line 1353 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT Operation

Defines
FDCAN TT Operation
FDCAN Exported Constants

Defines

#define | FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)

Define Documentation

#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)

External event-synchronized time-triggered operation

Definition at line 1363 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)

Strictly time-triggered operation

Definition at line 1362 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT Time Master

Defines
FDCAN TT Time Master
FDCAN Exported Constants

Defines

#define | FDCAN_TT_SLAVE ((uint32_t)0x00000000U)
#define | FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)

Define Documentation

#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)

Potential time master

Definition at line 1372 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U)

Time slave

Definition at line 1371 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT External Clock Synchronization

Defines
FDCAN TT External Clock Synchronization
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)

Define Documentation

#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)

External clock synchronization in Level 0,2 disabled

Definition at line 1380 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)

External clock synchronization in Level 0,2 enabled

Definition at line 1381 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Global Time Filtering

Defines
FDCAN TT Global Time Filtering
FDCAN Exported Constants

Defines

#define | FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)

Define Documentation

#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)

Global time filtering in Level 0,2 disabled

Definition at line 1389 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)

Global time filtering in Level 0,2 enabled

Definition at line 1390 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT Automatic Clock Calibration

Defines
FDCAN TT Automatic Clock Calibration
FDCAN Exported Constants

Defines

#define | FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)

Define Documentation

#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)

Automatic clock calibration in Level 0,2 disabled

Definition at line 1398 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)

Automatic clock calibration in Level 0,2 enabled

Definition at line 1399 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Event Trigger Polarity

Defines
FDCAN TT Event Trigger Polarity
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)

Define Documentation

#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)

Falling edge trigger

Definition at line 1408 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)

Rising edge trigger

Definition at line 1407 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT Basic Cycle Number

Defines
FDCAN TT Basic Cycle Number
FDCAN Exported Constants

Defines

#define | FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)

Define Documentation

#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)

1 Basic Cycle per Matrix

Definition at line 1416 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)

16 Basic Cycles per Matrix

Definition at line 1420 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)

2 Basic Cycles per Matrix

Definition at line 1417 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)

32 Basic Cycles per Matrix

Definition at line 1421 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)

4 Basic Cycles per Matrix

Definition at line 1418 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)

64 Basic Cycles per Matrix

Definition at line 1422 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)

8 Basic Cycles per Matrix

Definition at line 1419 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Cycle Start Sync

Defines
FDCAN TT Cycle Start Sync
FDCAN Exported Constants

Defines

#define | FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)
#define | FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)

Define Documentation

#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)

No sync pulse

Definition at line 1430 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)

Sync pulse at start of basic cycle

Definition at line 1431 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)

Sync pulse at start of matrix

Definition at line 1432 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Stop Watch Trigger Selection

Defines
FDCAN TT Stop Watch Trigger Selection
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)

TIM2 selected as stop watch trigger

Definition at line 1440 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)

TIM3 selected as stop watch trigger

Definition at line 1441 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)

ETH selected as stop watch trigger

Definition at line 1442 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)

HRTIM selected as stop watch trigger

Definition at line 1443 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Event Trigger Selection

Defines
FDCAN TT Event Trigger Selection
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)
#define | FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)
#define | FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)

Define Documentation

#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)

TIM2 selected as event trigger

Definition at line 1451 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)

TIM3 selected as event trigger

Definition at line 1452 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)

ETH selected as event trigger

Definition at line 1453 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)

HRTIM selected as event trigger

Definition at line 1454 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Stop Watch Source

Defines
FDCAN TT Stop Watch Source
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)
#define | FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)
#define | FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)

Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1463 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)

Stop Watch disabled

Definition at line 1462 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)

Actual value of global time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1465 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)

Actual value of local time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1464 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN TT Stop Watch Polarity

Defines
FDCAN TT Stop Watch Polarity
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)

Selected stop watch source is captured at falling edge of fdcan1_swt

Definition at line 1474 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)

Selected stop watch source is captured at rising edge of fdcan1_swt

Definition at line 1473 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Time Mark Source

Defines
FDCAN TT Time Mark Source
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)
#define | FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)
#define | FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)

Register Time Mark Interrupt if Time Mark = cycle time

Definition at line 1483 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)

No Register Time Mark Interrupt generated

Definition at line 1482 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark().

#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)

Register Time Mark Interrupt if Time Mark = global time

Definition at line 1485 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)

Register Time Mark Interrupt if Time Mark = local time

Definition at line 1484 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Error Level

Defines
FDCAN TT Error Level
FDCAN Exported Constants

Defines

#define | FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)
#define | FDCAN_TT_WARNING ((uint32_t)0x00000001U)
#define | FDCAN_TT_ERROR ((uint32_t)0x00000002U)
#define | FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_ERROR ((uint32_t)0x00000002U)

Severity 2 - Error

Definition at line 1495 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)

Severity 0 - No Error

Definition at line 1493 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)

Severity 3 - Severe Error

Definition at line 1496 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_WARNING ((uint32_t)0x00000001U)

Severity 1 - Warning

Definition at line 1494 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Master State

Defines
FDCAN TT Master State
FDCAN Exported Constants

Defines

#define | FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)
#define | FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)
#define | FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)
#define | FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)

Define Documentation

#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)

Operating as Backup Time Master

Definition at line 1506 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)

Operating as current Time Master

Definition at line 1507 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)

Master_Off, no master properties relevant

Definition at line 1504 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)

Operating as Time Slave

Definition at line 1505 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Synchronization State

Defines
FDCAN TT Synchronization State
FDCAN Exported Constants

Defines

#define | FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)
#define | FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)
#define | FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)

Define Documentation

#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)

Schedule suspended by Gap

Definition at line 1517 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)

Synchronized to schedule

Definition at line 1518 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)

Out of Synchronization

Definition at line 1515 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)

Synchronizing to communication

Definition at line 1516 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Interrupt masks

Defines
Interrupt masks
FDCAN Exported Constants

Defines

#define | FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)
#define | CCU_IR_MASK ((uint32_t)0xC0000000U)

Define Documentation

#define CCU_IR_MASK ((uint32_t)0xC0000000U)

CCU interrupts mask

Definition at line 1527 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)

FDCAN interrupts mask

Definition at line 1526 of file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Flags

Defines
FDCAN Flags
FDCAN Exported Constants

Defines

#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)
#define | FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)

Define Documentation

#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA

Protocol error in arbitration phase detected

Definition at line 1558 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO

Bus_Off status changed

Definition at line 1556 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)

Clock calibration state changed

Definition at line 1563 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)

Clock calibration watchdog event occurred

Definition at line 1564 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED

Protocol error in data phase detected

Definition at line 1559 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO

Overflow of FDCAN Error Logging Counter occurred

Definition at line 1553 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP

Error_Passive status changed

Definition at line 1554 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW

Error_Warning status changed

Definition at line 1555 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF

Message RAM access failure occurred

Definition at line 1552 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI

Message RAM Watchdog event due to missing READY

Definition at line 1557 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA

Access to reserved address occurred

Definition at line 1560 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX

At least one received message stored into a Rx Buffer

Definition at line 1539 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F

Rx FIFO 0 full

Definition at line 1545 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L

Rx FIFO 0 message lost

Definition at line 1544 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N

New message written to Rx FIFO 0

Definition at line 1547 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W

Rx FIFO 0 fill level reached watermark

Definition at line 1546 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F

Rx FIFO 1 full

Definition at line 1549 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L

Rx FIFO 1 message lost

Definition at line 1548 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N

New message written to Rx FIFO 1

Definition at line 1551 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W

Rx FIFO 1 fill level reached watermark

Definition at line 1550 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM

High priority message received

Definition at line 1538 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Timeout reached

Definition at line 1562 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW

Timestamp counter wrapped around

Definition at line 1561 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF

Transmission Cancellation Finished

Definition at line 1536 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC

Transmission Completed

Definition at line 1535 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL

Tx Event FIFO element lost

Definition at line 1540 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF

Tx Event FIFO full

Definition at line 1541 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN

Tx Handler wrote Tx Event FIFO element

Definition at line 1543 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW

Tx Event FIFO fill level reached watermark

Definition at line 1542 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE

Tx FIFO Empty

Definition at line 1537 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H7B3xQ HAL User Manual: FDCAN Tx Interrupts

Defines
FDCAN Tx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Define Documentation

#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE

Transmission Cancellation Finished

Definition at line 1577 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE

Transmission Completed

Definition at line 1576 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Tx FIFO Empty

Definition at line 1578 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H7B3xQ HAL User Manual: FDCAN Rx Interrupts

Defines
FDCAN Rx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE

Define Documentation

#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE

At least one received message stored into a Rx Buffer

Definition at line 1587 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

High priority message received

Definition at line 1586 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H7B3xQ HAL User Manual: FDCAN Counter Interrupts

Defines
FDCAN Counter Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Define Documentation

#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Timeout reached

Definition at line 1596 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE

Timestamp counter wrapped around

Definition at line 1595 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Calibration Interrupts

Defines
Clock Calibration Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)
#define | FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)

Define Documentation

#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)

Clock calibration state changed

Definition at line 1604 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)

Clock calibration watchdog event occurred

Definition at line 1605 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Tx Event FIFO Interrupts

Defines
FDCAN Tx Event FIFO Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Define Documentation

#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE

Tx Event FIFO element lost

Definition at line 1613 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE

Tx Event FIFO full

Definition at line 1614 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Tx Handler wrote Tx Event FIFO element

Definition at line 1616 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE

Tx Event FIFO fill level reached watermark

Definition at line 1615 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Rx FIFO 0 Interrupts

Defines
FDCAN Rx FIFO 0 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

Define Documentation

#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE

Rx FIFO 0 full

Definition at line 1625 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE

Rx FIFO 0 message lost

Definition at line 1624 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

New message written to Rx FIFO 0

Definition at line 1627 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE

Rx FIFO 0 fill level reached watermark

Definition at line 1626 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Rx FIFO 1 Interrupts

Defines
FDCAN Rx FIFO 1 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

Define Documentation

#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE

Rx FIFO 1 full

Definition at line 1636 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE

Rx FIFO 1 message lost

Definition at line 1635 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

New message written to Rx FIFO 1

Definition at line 1638 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE

Rx FIFO 1 fill level reached watermark

Definition at line 1637 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Error Interrupts

Defines
FDCAN Error Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Define Documentation

#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE

Protocol error in arbitration phase detected

Definition at line 1649 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE

Protocol error in data phase detected

Definition at line 1650 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE

Overflow of FDCAN Error Logging Counter occurred

Definition at line 1647 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE

Message RAM access failure occurred

Definition at line 1646 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE

Message RAM Watchdog event due to missing READY

Definition at line 1648 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Access to reserved address occurred

Definition at line 1651 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Error Status Interrupts

Defines
FDCAN Error Status Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Define Documentation

#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Bus_Off status changed

Definition at line 1661 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE

Error_Passive status changed

Definition at line 1659 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE

Error_Warning status changed

Definition at line 1660 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Flags

Defines
FDCAN TT Flags
FDCAN Exported Constants

Defines

#define | FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC
#define | FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC
#define | FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM
#define | FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG
#define | FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI
#define | FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI
#define | FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE
#define | FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW
#define | FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD
#define | FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE
#define | FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU
#define | FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2
#define | FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC
#define | FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT
#define | FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT
#define | FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW
#define | FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER

Define Documentation

#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW

Application Watchdog

Definition at line 1690 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC

Start of Basic Cycle

Definition at line 1673 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER

Configuration Error

Definition at line 1691 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC

Error Level Changed

Definition at line 1687 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD

Global Time Discontinuity

Definition at line 1681 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE

Global Time Error

Definition at line 1682 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW

Global Time Wrap

Definition at line 1680 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT

Initialization Watch Trigger

Definition at line 1688 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC

Start of Matrix Cycle

Definition at line 1674 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI

Register Time Mark Interrupt

Definition at line 1677 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1

Scheduling Error 1

Definition at line 1685 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2

Scheduling Error 2

Definition at line 1686 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG

Start of Gap

Definition at line 1676 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE

Stop Watch Event

Definition at line 1679 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM

Change of Synchronization Mode

Definition at line 1675 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI

Trigger Time Mark Event Internal

Definition at line 1678 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO

Tx Count Overflow

Definition at line 1684 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU

Tx Count Underflow

Definition at line 1683 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT

Watch Trigger

Definition at line 1689 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Schedule Synchronization Interrupts

Defines
FDCAN TT Schedule Synchronization Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE
#define | FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE
#define | FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME
#define | FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE

Define Documentation

#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE

Start of Basic Cycle

Definition at line 1703 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE

Start of Matrix Cycle

Definition at line 1704 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE

Start of Gap

Definition at line 1706 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME

Change of Synchronization Mode

Definition at line 1705 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Time Mark Interrupts

Defines
FDCAN TT Time Mark Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE
#define | FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE

Define Documentation

#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE

Register Time Mark Interrupt

Definition at line 1714 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE

Trigger Time Mark Event Internal

Definition at line 1715 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Stop Watch Interrupt

Defines
FDCAN TT Stop Watch Interrupt
FDCAN TT Interrupts

Defines

#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE

Define Documentation

#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE

Stop Watch Event

Definition at line 1723 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H7B3xQ HAL User Manual: FDCAN TT Global Time Interrupts

Defines
FDCAN TT Global Time Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE
#define | FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE

Define Documentation

#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE

Global Time Discontinuity

Definition at line 1732 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE

Global Time Wrap

Definition at line 1731 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Disturbing Error Interrupts

Defines
FDCAN TT Disturbing Error Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE
#define | FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE
#define | FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE
#define | FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E
#define | FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E
#define | FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE

Define Documentation

#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE

Error Level Changed

Definition at line 1745 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE

Global Time Error

Definition at line 1740 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E

Scheduling Error 1

Definition at line 1743 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E

Scheduling Error 2

Definition at line 1744 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE

Tx Count Overflow

Definition at line 1742 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE

Tx Count Underflow

Definition at line 1741 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN TT Fatal Error Interrupts

Defines
FDCAN TT Fatal Error Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE
#define | FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE
#define | FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE
#define | FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE

Define Documentation

#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE

Application Watchdog

Definition at line 1755 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE

Configuration Error

Definition at line 1756 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE

Initialization Watch Trigger

Definition at line 1753 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE

Watch Trigger

Definition at line 1754 of file stm32h7xx_hal_fdcan.h.

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STM32H7B3xQ HAL User Manual: FDCAN Exported Macros

Defines
FDCAN Exported Macros
FDCAN

Defines

#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
Enable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
Disable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
Check whether the specified FDCAN TT interrupt is set or not.
#define | __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
Clear the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
Check whether the specified FDCAN TT flag is set or not.
#define | __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
Clear the specified FDCAN TT flags.
#define | __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
Check if the specified FDCAN TT interrupt source is enabled or disabled.

Define Documentation

#define __HAL_FDCAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
do{                                                              \
    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Clear the specified FDCAN flags.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ specifies the flags to clear. This parameter can be any combination of
  • FDCAN_flags
Return values:
None

Definition at line 1853 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                                   \
    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Clear the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the interrupts to clear. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1831 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                                   \
    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Disable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1809 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeactivateNotification().

#define __HAL_FDCAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                                \
    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
  }while(0)

Enable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1795 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification().

#define __HAL_FDCAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))

Check whether the specified FDCAN flag is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ FDCAN flag. This parameter can be one of
  • FDCAN_flags
Return values:
FlagStatus

Definition at line 1844 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))

Check whether the specified FDCAN interrupt is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be one of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1822 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))

Check if the specified FDCAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the FDCAN interrupt source to check. This parameter can be a value of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1865 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                \
                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
                                                      (__HANDLE__)->MspInitCallback = NULL;           \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                     } while(0)

Reset FDCAN handle state.

Parameters:
__HANDLE__ FDCAN handle.
Return values:
None

Definition at line 1779 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))

Clear the specified FDCAN TT flags.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ specifies the TT flags to clear. This parameter can be any combination of
  • FDCAN_TTflags
Return values:
None

Definition at line 1919 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_TT_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))

Clear the specified FDCAN TT interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the TT interrupts to clear. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1901 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))

Disable the specified FDCAN TT interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN TT interrupt. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1883 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_DeactivateNotification().

#define __HAL_FDCAN_TT_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))

Enable the specified FDCAN TT interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN TT interrupt. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1874 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ActivateNotification().

#define __HAL_FDCAN_TT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))

Check whether the specified FDCAN TT flag is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ FDCAN TT flag. This parameter can be one of
  • FDCAN_TTflags
Return values:
FlagStatus

Definition at line 1910 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_TT_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))

Check whether the specified FDCAN TT interrupt is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN TT interrupt. This parameter can be one of
  • FDCAN_TTInterrupts
Return values:
ITStatus

Definition at line 1892 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))

Check if the specified FDCAN TT interrupt source is enabled or disabled.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the FDCAN TT interrupt source to check. This parameter can be a value of
  • FDCAN_TTInterrupts
Return values:
ITStatus

Definition at line 1927 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Types

FDCAN Private Types
FDCAN
Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Variables

FDCAN Private Variables
FDCAN
Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Constants

Defines
FDCAN Private Constants
FDCAN

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
#define | FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
#define | FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
#define | FDCAN_TT_DISTURBING_ERROR_MASK
#define | FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | FDCAN_MESSAGE_RAM_SIZE 0x2800U
#define | FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */

Define Documentation

#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */

Definition at line 230 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */

Definition at line 225 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */

Definition at line 224 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */

Definition at line 227 of file stm32h7xx_hal_fdcan.c.

#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */

Definition at line 222 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Definition at line 231 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */

Definition at line 219 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */

Definition at line 226 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */

Definition at line 229 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */

Definition at line 228 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */

Definition at line 220 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */

Definition at line 218 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */

Definition at line 223 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */

Definition at line 221 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)

Definition at line 209 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)

Definition at line 210 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */

Definition at line 234 of file stm32h7xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_TT_ConfigOperation().

#define FDCAN_MESSAGE_RAM_SIZE 0x2800U

Definition at line 233 of file stm32h7xx_hal_fdcan.c.

#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)

Definition at line 207 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)

Definition at line 208 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TIMEOUT_VALUE 10U

Definition at line 204 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define FDCAN_TT_DISTURBING_ERROR_MASK
Value:
(FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)

Definition at line 214 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)

Definition at line 216 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)

Definition at line 213 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)

Definition at line 211 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)

Definition at line 212 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)

Definition at line 206 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Macros

Defines
FDCAN Private Macros
FDCAN

Defines

#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
#define | IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
#define | IS_FDCAN_DATA_SIZE(SIZE)
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
#define | IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
#define | IS_FDCAN_FIFO_WATERMARK(FIFO)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH)
#define | IS_FDCAN_CALIBRATION_COUNTER(COUNTER)
#define | IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD)
#define | IS_FDCAN_TT_REPEAT_FACTOR(FACTOR)
#define | IS_FDCAN_TT_TRIGGER_TYPE(TYPE)
#define | IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT)
#define | IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT)
#define | IS_FDCAN_OPERATION_MODE(MODE)
#define | IS_FDCAN_TT_OPERATION(OPERATION)
#define | IS_FDCAN_TT_TIME_MASTER(FUNCTION)
#define | IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC)
#define | IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING)
#define | IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY)
#define | IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER)
#define | IS_FDCAN_TT_CYCLE_START_SYNC(SYNC)
#define | IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
#define | IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
#define | IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
#define | IS_FDCAN_TT_TUR_LEVEL_1(NC, DC) ((NC) >= (4U * (DC)))
#define | IS_FDCAN_TT_TUR_LEVEL_0_2(NC, DC) ((NC) >= (8U * (DC)))
#define | IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
#define | IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE)
#define | IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY)
#define | IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE)

Define Documentation

#define IS_FDCAN_BRS ( BRS )
Value:
(((BRS) == FDCAN_BRS_OFF) || \
                           ((BRS) == FDCAN_BRS_ON ))

Definition at line 2260 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_CALIBRATION_COUNTER ( COUNTER )
Value:
(((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))

Definition at line 2302 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetClockCalibrationCounter().

#define IS_FDCAN_CALIBRATION_FIELD_LENGTH ( LENGTH )
Value:
(((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))

Definition at line 2300 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define IS_FDCAN_CKDIV ( CKDIV )
Value:
(((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV30))

Definition at line 2167 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define IS_FDCAN_CLOCK_CALIBRATION ( CALIBRATION )
Value:
(((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))

Definition at line 2164 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define IS_FDCAN_DATA_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))

Definition at line 2187 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SIZE ( SIZE )
Value:
(((SIZE) == FDCAN_DATA_BYTES_8 ) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_64))

Definition at line 2193 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 16U))

Definition at line 2188 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))

Definition at line 2189 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))

Definition at line 2190 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DLC ( DLC )
Value:
(((DLC) == FDCAN_DLC_BYTES_0 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_12) || \
                           ((DLC) == FDCAN_DLC_BYTES_16) || \
                           ((DLC) == FDCAN_DLC_BYTES_20) || \
                           ((DLC) == FDCAN_DLC_BYTES_24) || \
                           ((DLC) == FDCAN_DLC_BYTES_32) || \
                           ((DLC) == FDCAN_DLC_BYTES_48) || \
                           ((DLC) == FDCAN_DLC_BYTES_64))

Definition at line 2242 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EFC ( EFC )
Value:
(((EFC) == FDCAN_NO_TX_EVENTS   ) || \
                           ((EFC) == FDCAN_STORE_TX_EVENTS))

Definition at line 2264 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ESI ( ESI )
Value:
(((ESI) == FDCAN_ESI_ACTIVE ) || \
                           ((ESI) == FDCAN_ESI_PASSIVE))

Definition at line 2258 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EXT_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE        ) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))

Definition at line 2236 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FDF ( FDF )
Value:
(((FDF) == FDCAN_CLASSIC_CAN) || \
                           ((FDF) == FDCAN_FD_CAN     ))

Definition at line 2262 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_FIFO_WATERMARK ( FIFO )
Value:
(((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))

Definition at line 2268 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

#define IS_FDCAN_FILTER_CFG ( CONFIG )
Value:
(((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))

Definition at line 2205 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FRAME_FORMAT ( FORMAT )
Value:
(((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))

Definition at line 2155 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_FRAME_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_DATA_FRAME  ) || \
                                   ((TYPE) == FDCAN_REMOTE_FRAME))

Definition at line 2240 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ID_TYPE ( ID_TYPE )
Value:
(((ID_TYPE) == FDCAN_STANDARD_ID) || \
                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))

Definition at line 2203 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_IT ( IT ) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)

Definition at line 2266 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), and HAL_FDCAN_DeactivateNotification().

#define IS_FDCAN_IT_LINE ( IT_LINE )
Value:
(((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))

Definition at line 2276 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines(), and HAL_FDCAN_TT_ConfigInterruptLines().

#define IS_FDCAN_MAX_VALUE | ( | VALUE,
 |  | MAX
 | ) | ((VALUE) <= (MAX))

Definition at line 2191 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_Init(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_MIN_VALUE | ( | VALUE,
 |  | MIN
 | ) | ((VALUE) >= (MIN))

Definition at line 2192 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration(), and HAL_FDCAN_GetTxEvent().

#define IS_FDCAN_MODE ( MODE )
Value:
(((MODE) == FDCAN_MODE_NORMAL              ) || \
                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))

Definition at line 2158 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))

Definition at line 2183 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 128U))

Definition at line 2184 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))

Definition at line 2185 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))

Definition at line 2186 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NON_MATCHING ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
                                            ((DESTINATION) == FDCAN_REJECT            ))

Definition at line 2271 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_OPERATION_MODE ( MODE )
Value:
(((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))

Definition at line 2329 of file stm32h7xx_hal_fdcan.h.

#define IS_FDCAN_REJECT_REMOTE ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_FILTER_REMOTE) || \
                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))

Definition at line 2274 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_RX_FIFO ( FIFO )
Value:
(((FIFO) == FDCAN_RX_FIFO0) || \
                                ((FIFO) == FDCAN_RX_FIFO1))

Definition at line 2229 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), and HAL_FDCAN_GetRxFifoFillLevel().

#define IS_FDCAN_RX_FIFO_MODE ( MODE )
Value:
(((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))

Definition at line 2231 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite().

#define IS_FDCAN_STD_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK ))

Definition at line 2233 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_TIMEOUT ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))

Definition at line 2296 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimeoutCounter().

#define IS_FDCAN_TIMESTAMP ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))

Definition at line 2278 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnableTimestampCounter().

#define IS_FDCAN_TIMESTAMP_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))

Definition at line 2280 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimestampCounter().

#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION ( CALIBRATION )
Value:
(((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))

Definition at line 2340 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER ( NUMBER )
Value:
(((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))

Definition at line 2344 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_CYCLE_START_SYNC ( SYNC )
Value:
(((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))

Definition at line 2351 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EVENT_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))

Definition at line 2363 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY ( POLARITY )
Value:
(((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))

Definition at line 2342 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC ( SYNC )
Value:
(((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))

Definition at line 2336 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING ( FILTERING )
Value:
(((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))

Definition at line 2338 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_IT ( IT ) (((IT) & 0xFFF80000U) == 0U)

Definition at line 2267 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigInterruptLines(), and HAL_FDCAN_TT_DeactivateNotification().

#define IS_FDCAN_TT_OPERATION ( OPERATION )
Value:
(((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))

Definition at line 2332 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD ( PAYLOAD )
Value:
(((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))

Definition at line 2305 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigReferenceMessage().

#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE ( SOURCE )
Value:
(((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))

Definition at line 2374 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark().

#define IS_FDCAN_TT_REPEAT_FACTOR ( FACTOR )
Value:
(((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))

Definition at line 2307 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_STOP_WATCH_POLARITY ( POLARITY )
Value:
(((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))

Definition at line 2372 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigStopWatch().

#define IS_FDCAN_TT_STOP_WATCH_SOURCE ( SOURCE )
Value:
(((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))

Definition at line 2368 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigStopWatch().

#define IS_FDCAN_TT_STOP_WATCH_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))

Definition at line 2359 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TIME_MASTER ( FUNCTION )
Value:
(((FUNCTION) == FDCAN_TT_SLAVE           ) || \
                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))

Definition at line 2334 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TIME_PRESET ( TIME ) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))

Definition at line 2367 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_SetGlobalTime().

#define IS_FDCAN_TT_TM_EVENT_EXTERNAL ( EVENT )
Value:
(((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))

Definition at line 2327 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TM_EVENT_INTERNAL ( EVENT )
Value:
(((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))

Definition at line 2325 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TRIGGER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))

Definition at line 2314 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TUR_DENOMINATOR ( DENOMINATOR ) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))

Definition at line 2356 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_LEVEL_0_2 | ( | NC,
 |  | DC
 | ) | ((NC) >= (8U * (DC)))

Definition at line 2358 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_LEVEL_1 | ( | NC,
 |  | DC
 | ) | ((NC) >= (4U * (DC)))

Definition at line 2357 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_NUMERATOR ( NUMERATOR ) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))

Definition at line 2355 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_SetClockSynchronization().

#define IS_FDCAN_TT_TX_ENABLE_WINDOW ( NTU ) (((NTU) >= 1U) && ((NTU) <= 16U))

Definition at line 2354 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TX_FIFO_QUEUE_MODE ( MODE )
Value:
(((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))

Definition at line 2201 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_TX_LOCATION ( LOCATION )
Value:
(((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))

Definition at line 2213 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_TT_ConfigTrigger().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Functions Prototypes

FDCAN Private Functions Prototypes
FDCAN
Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN Private Functions

Functions
FDCAN Private Functions
FDCAN

Functions

static HAL_StatusTypeDef | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.

Function Documentation

static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses ( FDCAN_HandleTypeDef * hfdcan ) [static]

Calculate each RAM block start address and size.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 6008 of file stm32h7xx_hal_fdcan.c.

References FDCAN_MsgRamAddressTypeDef::EndAddress, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_MESSAGE_RAM_END_ADDRESS, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_ERROR, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, FDCAN_InitTypeDef::MessageRAMOffset, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxBufferSA, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_InitTypeDef::RxFifo0ElmtsNbr, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_InitTypeDef::RxFifo1ElmtsNbr, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, __FDCAN_HandleTypeDef::State, FDCAN_InitTypeDef::StdFiltersNbr, FDCAN_MsgRamAddressTypeDef::TxBufferSA, FDCAN_InitTypeDef::TxBuffersNbr, FDCAN_InitTypeDef::TxElmtSize, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_InitTypeDef::TxEventsNbr, FDCAN_MsgRamAddressTypeDef::TxFIFOQSA, and FDCAN_InitTypeDef::TxFifoQueueElmtsNbr.

Referenced by HAL_FDCAN_Init().

static void FDCAN_CopyMessageToRAM | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  | [static]

Copy Tx message to the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
BufferIndex | index of the buffer to be configured.
Return values:
HAL status

Definition at line 6107 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, DLCtoBytes, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Init, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::TxBufferSA, FDCAN_InitTypeDef::TxElmtSize, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FDCAN

Modules | Variables
FDCAN
STM32H7xx_HAL_Driver

FDCAN HAL module driver. More...

Modules

FDCAN Exported Functions
FDCAN Exported Types
FDCAN Exported Constants
FDCAN Exported Macros
FDCAN Private Types
FDCAN Private Variables
FDCAN Private Constants
FDCAN Private Macros
FDCAN Private Functions Prototypes
FDCAN Private Functions

Variables

static const uint8_t DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Detailed Description

FDCAN HAL module driver.

Variable Documentation

const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64} [static]

Definition at line 242 of file stm32h7xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_GetRxMessage().

Generated on Tue Nov 12 2019 18:50:14 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that all the selected sectors have been erased) Program: Address which was selected for data program
Return values:
None

Definition at line 651 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

This function handles FLASH interrupt request.

Return values:
None

Definition at line 389 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_DISABLE_IT_BANK1, __HAL_FLASH_DISABLE_IT_BANK2, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_PGSERR_BANK1, FLASH_FLAG_PGSERR_BANK2, FLASH_FLAG_STRBERR_BANK1, FLASH_FLAG_STRBERR_BANK2, FLASH_FLAG_WRPERR_BANK1, FLASH_FLAG_WRPERR_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_NONE, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_ProcessTypeDef::Sector, and FLASH_ProcessTypeDef::VoltageForErase.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 669 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint32_t | DataAddress
 | ) |  |

Program flash word at a specified address.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data to be programmed
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 146 of file stm32h7xx_hal_flash.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_OTPWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_OTP, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint32_t | DataAddress
 | ) |  |

Program flash words of 256 bits at a specified address with interrupt enabled.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data (256 bits) to be programmed
Return values:
HAL Status

Definition at line 268 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_OTPWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_OTP, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option bytes loading.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control registers access.

Return values:
HAL Status

Definition at line 737 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option bytes loading.

Return values:
HAL Status

Definition at line 804 of file stm32h7xx_hal_flash.c.

References FLASH_BANK_1, FLASH_BANK_2, FLASH_CRC_WaitForLastOperation(), FLASH_OB_WaitForLastOperation(), and FLASH_TIMEOUT_VALUE.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 786 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 764 of file stm32h7xx_hal_flash.c.

References FLASH_OPT_KEY1, and FLASH_OPT_KEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control registers access.

Return values:
HAL Status

Definition at line 702 of file stm32h7xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
HAL_FLASH_ERRORCode The returned value can be:
  • HAL_FLASH_ERROR_NONE : No error set
  • HAL_FLASH_ERROR_WRP_BANK1 : Write Protection Error on Bank 1
  • HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1
  • HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
  • HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1
  • HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1
  • HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1
  • HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1
  • HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
  • HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
  • HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
  • HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2
  • HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2
  • HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
  • HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2
  • HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2
  • HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2
  • HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2
  • HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
  • HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
  • HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2

Definition at line 880 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_PROGRAM_BANK1,
FLASH_PROC_SECTERASE_BANK2, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_ALLBANK_MASSERASE
}
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_SECTERASE_BANK1
FLASH_PROC_MASSERASE_BANK1
FLASH_PROC_PROGRAM_BANK1
FLASH_PROC_SECTERASE_BANK2
FLASH_PROC_MASSERASE_BANK2
FLASH_PROC_PROGRAM_BANK2
FLASH_PROC_ALLBANK_MASSERASE

Definition at line 47 of file stm32h7xx_hal_flash.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32h7xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | NbSectorsToErase
__IO uint32_t | VoltageForErase
__IO uint32_t | Sector
__IO uint32_t | Address
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 63 of file stm32h7xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Internal variable to save address selected for program

Definition at line 73 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

FLASH error code

Definition at line 77 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_OB_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_FLASH_GetError(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

FLASH locking object

Definition at line 75 of file stm32h7xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbSectorsToErase

Internal variable to save the remaining sectors to erase in IT context

Definition at line 67 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Internal variable to indicate which procedure is ongoing or not in IT context

Definition at line 65 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Sector

Internal variable to define the current sector which is erasing

Definition at line 71 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::VoltageForErase

Internal variable to provide voltage range selected by user in IT context

Definition at line 69 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Error Code

Defines
FLASH Error Code
FLASH Exported Constants

FLASH Error Code. More...

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR
#define | HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR
#define | HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR
#define | HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR
#define | HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR
#define | HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR
#define | HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR
#define | HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1
#define | HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1
#define | HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1
#define | HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1
#define | HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1
#define | HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1
#define | HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1
#define | HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1
#define | HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1
#define | HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2
#define | HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2
#define | HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2
#define | HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2
#define | HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2
#define | HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2
#define | HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2
#define | HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2
#define | HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2
#define | HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR

Detailed Description

FLASH Error Code.

Define Documentation

#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR

CRC Read Error

Definition at line 107 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1

CRC Read Error on Bank1

Definition at line 120 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation().

#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2

CRC Read Error on Bank2

Definition at line 133 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation().

#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR

ECC Double Detection Error

Definition at line 106 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1

ECC Double Detection Error on Bank 1

Definition at line 119 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2

ECC Double Detection Error on Bank 2

Definition at line 132 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR

Inconsistency Error

Definition at line 99 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1

Inconsistency Error on Bank 1

Definition at line 112 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2

Inconsistency Error on Bank 2

Definition at line 125 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_NONE 0x00000000U

No error

Definition at line 94 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR

Option Byte Change Error

Definition at line 135 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_WaitForLastOperation().

#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR

Program Sequence Error

Definition at line 97 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1

Program Sequence Error on Bank 1

Definition at line 110 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2

Program Sequence Error on Bank 2

Definition at line 123 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR

Read Protection Error

Definition at line 103 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1

Read Protection Error on Bank 1

Definition at line 116 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2

Read Protection Error on Bank 2

Definition at line 129 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR

Read Secured Error

Definition at line 104 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1

Read Secured Error on Bank 1

Definition at line 117 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2

Read Secured Error on Bank 2

Definition at line 130 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR

ECC Single Correction Error

Definition at line 105 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1

ECC Single Correction Error on Bank 1

Definition at line 118 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2

ECC Single Correction Error on Bank 2

Definition at line 131 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR

Strobe Error

Definition at line 98 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1

Strobe Error on Bank 1

Definition at line 111 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2

Strobe Error on Bank 2

Definition at line 124 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR

Write Protection Error

Definition at line 96 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1

Write Protection Error on Bank 1

Definition at line 109 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2

Write Protection Error on Bank 2

Definition at line 122 of file stm32h7xx_hal_flash.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_FLASHWORD 0x01U
#define | FLASH_TYPEPROGRAM_OTPWORD 0x02U

Define Documentation

#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U

Program a flash word at a specified address

Definition at line 143 of file stm32h7xx_hal_flash.h.

#define FLASH_TYPEPROGRAM_OTPWORD 0x02U

Program an OTP word at a specified address

Definition at line 145 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Flag definition

Defines
FLASH Flag definition
FLASH Exported Constants

Flag definition. More...

Defines

#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_WBNE FLASH_SR_WBNE
#define | FLASH_FLAG_QW FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR FLASH_SR_INCERR
#define | FLASH_FLAG_RDPERR FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND FLASH_SR_CRCEND
#define | FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR
#define | FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY
#define | FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE
#define | FLASH_FLAG_QW_BANK1 FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR
#define | FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND
#define | FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR
#define | FLASH_FLAG_ALL_ERRORS_BANK1
#define | FLASH_FLAG_ALL_BANK1
#define | FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)
#define | FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)
#define | FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)
#define | FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)
#define | FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)
#define | FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)
#define | FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)
#define | FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U)
#define | FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)
#define | FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)
#define | FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)
#define | FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U)
#define | FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U)
#define | FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)
#define | FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U)
#define | FLASH_FLAG_ALL_ERRORS_BANK2
#define | FLASH_FLAG_ALL_BANK2

Detailed Description

Flag definition.

Define Documentation

#define FLASH_FLAG_ALL_BANK1
Value:
(FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
                                           FLASH_FLAG_ALL_ERRORS_BANK1)

All Bank 1 flags

Definition at line 207 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_ALL_BANK2
Value:
(FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
                                           FLASH_FLAG_ALL_ERRORS_BANK2)

All Bank 2 flags

Definition at line 245 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_ALL_ERRORS_BANK1
Value:
(FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
                                           FLASH_FLAG_CRCRDERR_BANK1)

All Bank 1 error flags

Definition at line 200 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_ALL_ERRORS_BANK2
Value:
(FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
                                           FLASH_FLAG_CRCRDERR_BANK2)

All Bank 2 error flags

Definition at line 238 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 155 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY

FLASH Bank 1 Busy flag

Definition at line 174 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)

FLASH Bank 2 Busy flag

Definition at line 212 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY

CRC Busy flag

Definition at line 158 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY

CRC Busy on Bank 1 flag

Definition at line 177 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation().

#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)

CRC Busy on Bank 2 flag

Definition at line 215 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation().

#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND

CRC End of Calculation flag

Definition at line 171 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND

CRC End of Calculation on Bank 1 flag

Definition at line 190 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASHEx_ComputeCRC().

#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)

CRC End of Calculation on Bank 2 flag

Definition at line 228 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASHEx_ComputeCRC().

#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR

CRC Read Error on bank flag

Definition at line 172 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR

CRC Read error on Bank 1 flag

Definition at line 191 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), and HAL_FLASHEx_ComputeCRC().

#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U)

CRC Read error on Bank 2 flag

Definition at line 229 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), and HAL_FLASHEx_ComputeCRC().

#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR

Double Detection ECC Error on flag

Definition at line 170 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR

Double Detection ECC Error on Bank 1 flag

Definition at line 189 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U)

Double Detection ECC Error on Bank 2 flag

Definition at line 227 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_EOP FLASH_SR_EOP

End Of Program on flag

Definition at line 159 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP

End Of Program on Bank 1 flag

Definition at line 178 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)

End Of Program on Bank 2 flag

Definition at line 216 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_INCERR FLASH_SR_INCERR

Inconsistency Error on flag

Definition at line 163 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR

Inconsistency Error on Bank 1 flag

Definition at line 182 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)

Inconsistency Error on Bank 2 flag

Definition at line 220 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

Program Sequence Error on flag

Definition at line 161 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR

Program Sequence Error on Bank 1 flag

Definition at line 180 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)

Program Sequence Error on Bank 2 flag

Definition at line 218 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define FLASH_FLAG_QW FLASH_SR_QW

Wait Queue on flag

Definition at line 157 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW

Wait Queue on Bank 1 flag

Definition at line 176 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)

Wait Queue on Bank 2 flag

Definition at line 214 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR

Read Protection Error on flag

Definition at line 167 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR

Read Protection Error on Bank 1 flag

Definition at line 186 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)

Read Protection Error on Bank 2 flag

Definition at line 224 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR

Read Secured Error on flag

Definition at line 168 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR

Read Secured Error on Bank 1 flag

Definition at line 187 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)

Read Secured Error on Bank 2 flag

Definition at line 225 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR

Single ECC Error Correction on flag

Definition at line 169 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR

Single ECC Error Correction on Bank 1 flag

Definition at line 188 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U)

Single ECC Error Correction on Bank 2 flag

Definition at line 226 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR

Strobe Error flag

Definition at line 162 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR

Strobe Error on Bank 1 flag

Definition at line 181 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U)

Strobe Error on Bank 2 flag

Definition at line 219 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WBNE FLASH_SR_WBNE

Write Buffer Not Empty flag

Definition at line 156 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE

Write Buffer Not Empty on Bank 1 flag

Definition at line 175 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)

Write Buffer Not Empty on Bank 2 flag

Definition at line 213 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

Write Protection Error on flag

Definition at line 160 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR

Write Protection Error on Bank 1 flag

Definition at line 179 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)

Write Protection Error on Bank 2 flag

Definition at line 217 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Interrupt definition

Defines
FLASH Interrupt definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE
#define | FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE
#define | FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE
#define | FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE
#define | FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE
#define | FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE
#define | FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE
#define | FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE
#define | FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE
#define | FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE
#define | FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE
#define | FLASH_IT_ALL_BANK1
#define | FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)
#define | FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)
#define | FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)
#define | FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)
#define | FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)
#define | FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)
#define | FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)
#define | FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)
#define | FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)
#define | FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)
#define | FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U)
#define | FLASH_IT_ALL_BANK2

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ALL_BANK1
Value:
(FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
                                            FLASH_IT_CRCRDERR_BANK1)

All Bank 1 Interrupt sources

Definition at line 280 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_ALL_BANK2
Value:
(FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
                                            FLASH_IT_CRCRDERR_BANK2)

All Bank 2 Interrupt sources

Definition at line 311 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE

CRC End on Bank 1 Interrupt source

Definition at line 269 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)

CRC End on Bank 2 Interrupt source

Definition at line 300 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE

CRC Read error on Bank 1 Interrupt source

Definition at line 270 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U)

CRC Read Error on Bank 2 Interrupt source

Definition at line 301 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE

Double Detection ECC Error on Bank 1 Interrupt source

Definition at line 268 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)

Double Detection ECC Error on Bank 2 Interrupt source

Definition at line 299 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE

End of FLASH Bank 1 Operation Interrupt source

Definition at line 257 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)

End of FLASH Bank 2 Operation Interrupt source

Definition at line 288 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE

Inconsistency Error on Bank 1 Interrupt source

Definition at line 261 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)

Inconsistency Error on Bank 2 Interrupt source

Definition at line 292 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE

Program Sequence Error on Bank 1 Interrupt source

Definition at line 259 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)

Program Sequence Error on Bank 2 Interrupt source

Definition at line 290 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE

Read protection Error on Bank 1 Interrupt source

Definition at line 265 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)

Read protection Error on Bank 2 Interrupt source

Definition at line 296 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE

Read Secured Error on Bank 1 Interrupt source

Definition at line 266 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)

Read Secured Error on Bank 2 Interrupt source

Definition at line 297 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE

Single ECC Error Correction on Bank 1 Interrupt source

Definition at line 267 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)

Single ECC Error Correction on Bank 2 Interrupt source

Definition at line 298 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE

Strobe Error on Bank 1 Interrupt source

Definition at line 260 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)

Strobe Error on Bank 2 Interrupt source

Definition at line 291 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE

Write Protection Error on Bank 1 Interrupt source

Definition at line 258 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)

Write Protection Error on Bank 2 Interrupt source

Definition at line 289 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPT_KEY1 0x08192A3BU
#define | FLASH_OPT_KEY2 0x4C5D6E7FU

Define Documentation

#define FLASH_KEY1 0x45670123U

Definition at line 339 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock(), HAL_FLASHEx_Unlock_Bank1(), and HAL_FLASHEx_Unlock_Bank2().

#define FLASH_KEY2 0xCDEF89ABU

Definition at line 340 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock(), HAL_FLASHEx_Unlock_Bank1(), and HAL_FLASHEx_Unlock_Bank2().

#define FLASH_OPT_KEY1 0x08192A3BU

Definition at line 341 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPT_KEY2 0x4C5D6E7FU

Definition at line 342 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Sectors

Defines
FLASH Sectors
FLASH Exported Constants

Defines

#define | FLASH_SECTOR_0 0U
#define | FLASH_SECTOR_1 1U
#define | FLASH_SECTOR_2 2U
#define | FLASH_SECTOR_3 3U
#define | FLASH_SECTOR_4 4U
#define | FLASH_SECTOR_5 5U
#define | FLASH_SECTOR_6 6U
#define | FLASH_SECTOR_7 7U
#define | FLASH_SECTOR_8 8U
#define | FLASH_SECTOR_9 9U
#define | FLASH_SECTOR_10 10U
#define | FLASH_SECTOR_11 11U
#define | FLASH_SECTOR_12 12U
#define | FLASH_SECTOR_13 13U
#define | FLASH_SECTOR_14 14U
#define | FLASH_SECTOR_15 15U
#define | FLASH_SECTOR_16 16U
#define | FLASH_SECTOR_17 17U
#define | FLASH_SECTOR_18 18U
#define | FLASH_SECTOR_19 19U
#define | FLASH_SECTOR_20 20U
#define | FLASH_SECTOR_21 21U
#define | FLASH_SECTOR_22 22U
#define | FLASH_SECTOR_23 23U
#define | FLASH_SECTOR_24 24U
#define | FLASH_SECTOR_25 25U
#define | FLASH_SECTOR_26 26U
#define | FLASH_SECTOR_27 27U
#define | FLASH_SECTOR_28 28U
#define | FLASH_SECTOR_29 29U
#define | FLASH_SECTOR_30 30U
#define | FLASH_SECTOR_31 31U
#define | FLASH_SECTOR_32 32U
#define | FLASH_SECTOR_33 33U
#define | FLASH_SECTOR_34 34U
#define | FLASH_SECTOR_35 35U
#define | FLASH_SECTOR_36 36U
#define | FLASH_SECTOR_37 37U
#define | FLASH_SECTOR_38 38U
#define | FLASH_SECTOR_39 39U
#define | FLASH_SECTOR_40 40U
#define | FLASH_SECTOR_41 41U
#define | FLASH_SECTOR_42 42U
#define | FLASH_SECTOR_43 43U
#define | FLASH_SECTOR_44 44U
#define | FLASH_SECTOR_45 45U
#define | FLASH_SECTOR_46 46U
#define | FLASH_SECTOR_47 47U
#define | FLASH_SECTOR_48 48U
#define | FLASH_SECTOR_49 49U
#define | FLASH_SECTOR_50 50U
#define | FLASH_SECTOR_51 51U
#define | FLASH_SECTOR_52 52U
#define | FLASH_SECTOR_53 53U
#define | FLASH_SECTOR_54 54U
#define | FLASH_SECTOR_55 55U
#define | FLASH_SECTOR_56 56U
#define | FLASH_SECTOR_57 57U
#define | FLASH_SECTOR_58 58U
#define | FLASH_SECTOR_59 59U
#define | FLASH_SECTOR_60 60U
#define | FLASH_SECTOR_61 61U
#define | FLASH_SECTOR_62 62U
#define | FLASH_SECTOR_63 63U
#define | FLASH_SECTOR_64 64U
#define | FLASH_SECTOR_65 65U
#define | FLASH_SECTOR_66 66U
#define | FLASH_SECTOR_67 67U
#define | FLASH_SECTOR_68 68U
#define | FLASH_SECTOR_69 69U
#define | FLASH_SECTOR_70 70U
#define | FLASH_SECTOR_71 71U
#define | FLASH_SECTOR_72 72U
#define | FLASH_SECTOR_73 73U
#define | FLASH_SECTOR_74 74U
#define | FLASH_SECTOR_75 75U
#define | FLASH_SECTOR_76 76U
#define | FLASH_SECTOR_77 77U
#define | FLASH_SECTOR_78 78U
#define | FLASH_SECTOR_79 79U
#define | FLASH_SECTOR_80 80U
#define | FLASH_SECTOR_81 81U
#define | FLASH_SECTOR_82 82U
#define | FLASH_SECTOR_83 83U
#define | FLASH_SECTOR_84 84U
#define | FLASH_SECTOR_85 85U
#define | FLASH_SECTOR_86 86U
#define | FLASH_SECTOR_87 87U
#define | FLASH_SECTOR_88 88U
#define | FLASH_SECTOR_89 89U
#define | FLASH_SECTOR_90 90U
#define | FLASH_SECTOR_91 91U
#define | FLASH_SECTOR_92 92U
#define | FLASH_SECTOR_93 93U
#define | FLASH_SECTOR_94 94U
#define | FLASH_SECTOR_95 95U
#define | FLASH_SECTOR_96 96U
#define | FLASH_SECTOR_97 97U
#define | FLASH_SECTOR_98 98U
#define | FLASH_SECTOR_99 99U
#define | FLASH_SECTOR_100 100U
#define | FLASH_SECTOR_101 101U
#define | FLASH_SECTOR_102 102U
#define | FLASH_SECTOR_103 103U
#define | FLASH_SECTOR_104 104U
#define | FLASH_SECTOR_105 105U
#define | FLASH_SECTOR_106 106U
#define | FLASH_SECTOR_107 107U
#define | FLASH_SECTOR_108 108U
#define | FLASH_SECTOR_109 109U
#define | FLASH_SECTOR_110 110U
#define | FLASH_SECTOR_111 111U
#define | FLASH_SECTOR_112 112U
#define | FLASH_SECTOR_113 113U
#define | FLASH_SECTOR_114 114U
#define | FLASH_SECTOR_115 115U
#define | FLASH_SECTOR_116 116U
#define | FLASH_SECTOR_117 117U
#define | FLASH_SECTOR_118 118U
#define | FLASH_SECTOR_119 119U
#define | FLASH_SECTOR_120 120U
#define | FLASH_SECTOR_121 121U
#define | FLASH_SECTOR_122 122U
#define | FLASH_SECTOR_123 123U
#define | FLASH_SECTOR_124 124U
#define | FLASH_SECTOR_125 125U
#define | FLASH_SECTOR_126 126U
#define | FLASH_SECTOR_127 127U

Define Documentation

#define FLASH_SECTOR_0 0U

Sector Number 0

Definition at line 350 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_1 1U

Sector Number 1

Definition at line 351 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_10 10U

Sector Number 10

Definition at line 361 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_100 100U

Sector Number 100

Definition at line 451 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_101 101U

Sector Number 101

Definition at line 452 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_102 102U

Sector Number 102

Definition at line 453 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_103 103U

Sector Number 103

Definition at line 454 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_104 104U

Sector Number 104

Definition at line 455 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_105 105U

Sector Number 105

Definition at line 456 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_106 106U

Sector Number 106

Definition at line 457 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_107 107U

Sector Number 107

Definition at line 458 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_108 108U

Sector Number 108

Definition at line 459 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_109 109U

Sector Number 109

Definition at line 460 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_11 11U

Sector Number 11

Definition at line 362 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_110 110U

Sector Number 110

Definition at line 461 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_111 111U

Sector Number 111

Definition at line 462 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_112 112U

Sector Number 112

Definition at line 463 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_113 113U

Sector Number 113

Definition at line 464 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_114 114U

Sector Number 114

Definition at line 465 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_115 115U

Sector Number 115

Definition at line 466 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_116 116U

Sector Number 116

Definition at line 467 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_117 117U

Sector Number 117

Definition at line 468 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_118 118U

Sector Number 118

Definition at line 469 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_119 119U

Sector Number 119

Definition at line 470 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_12 12U

Sector Number 12

Definition at line 363 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_120 120U

Sector Number 120

Definition at line 471 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_121 121U

Sector Number 121

Definition at line 472 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_122 122U

Sector Number 122

Definition at line 473 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_123 123U

Sector Number 123

Definition at line 474 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_124 124U

Sector Number 124

Definition at line 475 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_125 125U

Sector Number 125

Definition at line 476 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_126 126U

Sector Number 126

Definition at line 477 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_127 127U

Sector Number 127

Definition at line 478 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_13 13U

Sector Number 13

Definition at line 364 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_14 14U

Sector Number 14

Definition at line 365 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_15 15U

Sector Number 15

Definition at line 366 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_16 16U

Sector Number 16

Definition at line 367 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_17 17U

Sector Number 17

Definition at line 368 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_18 18U

Sector Number 18

Definition at line 369 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_19 19U

Sector Number 19

Definition at line 370 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_2 2U

Sector Number 2

Definition at line 352 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_20 20U

Sector Number 20

Definition at line 371 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_21 21U

Sector Number 21

Definition at line 372 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_22 22U

Sector Number 22

Definition at line 373 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_23 23U

Sector Number 23

Definition at line 374 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_24 24U

Sector Number 24

Definition at line 375 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_25 25U

Sector Number 25

Definition at line 376 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_26 26U

Sector Number 26

Definition at line 377 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_27 27U

Sector Number 27

Definition at line 378 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_28 28U

Sector Number 28

Definition at line 379 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_29 29U

Sector Number 29

Definition at line 380 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_3 3U

Sector Number 3

Definition at line 353 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_30 30U

Sector Number 30

Definition at line 381 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_31 31U

Sector Number 31

Definition at line 382 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_32 32U

Sector Number 32

Definition at line 383 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_33 33U

Sector Number 33

Definition at line 384 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_34 34U

Sector Number 34

Definition at line 385 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_35 35U

Sector Number 35

Definition at line 386 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_36 36U

Sector Number 36

Definition at line 387 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_37 37U

Sector Number 37

Definition at line 388 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_38 38U

Sector Number 38

Definition at line 389 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_39 39U

Sector Number 39

Definition at line 390 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_4 4U

Sector Number 4

Definition at line 354 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_40 40U

Sector Number 40

Definition at line 391 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_41 41U

Sector Number 41

Definition at line 392 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_42 42U

Sector Number 42

Definition at line 393 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_43 43U

Sector Number 43

Definition at line 394 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_44 44U

Sector Number 44

Definition at line 395 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_45 45U

Sector Number 45

Definition at line 396 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_46 46U

Sector Number 46

Definition at line 397 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_47 47U

Sector Number 47

Definition at line 398 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_48 48U

Sector Number 48

Definition at line 399 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_49 49U

Sector Number 49

Definition at line 400 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_5 5U

Sector Number 5

Definition at line 355 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_50 50U

Sector Number 50

Definition at line 401 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_51 51U

Sector Number 51

Definition at line 402 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_52 52U

Sector Number 52

Definition at line 403 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_53 53U

Sector Number 53

Definition at line 404 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_54 54U

Sector Number 54

Definition at line 405 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_55 55U

Sector Number 55

Definition at line 406 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_56 56U

Sector Number 56

Definition at line 407 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_57 57U

Sector Number 57

Definition at line 408 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_58 58U

Sector Number 58

Definition at line 409 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_59 59U

Sector Number 59

Definition at line 410 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_6 6U

Sector Number 6

Definition at line 356 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_60 60U

Sector Number 60

Definition at line 411 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_61 61U

Sector Number 61

Definition at line 412 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_62 62U

Sector Number 62

Definition at line 413 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_63 63U

Sector Number 63

Definition at line 414 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_64 64U

Sector Number 64

Definition at line 415 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_65 65U

Sector Number 65

Definition at line 416 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_66 66U

Sector Number 66

Definition at line 417 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_67 67U

Sector Number 67

Definition at line 418 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_68 68U

Sector Number 68

Definition at line 419 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_69 69U

Sector Number 69

Definition at line 420 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_7 7U

Sector Number 7

Definition at line 357 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_70 70U

Sector Number 70

Definition at line 421 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_71 71U

Sector Number 71

Definition at line 422 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_72 72U

Sector Number 72

Definition at line 423 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_73 73U

Sector Number 73

Definition at line 424 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_74 74U

Sector Number 74

Definition at line 425 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_75 75U

Sector Number 75

Definition at line 426 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_76 76U

Sector Number 76

Definition at line 427 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_77 77U

Sector Number 77

Definition at line 428 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_78 78U

Sector Number 78

Definition at line 429 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_79 79U

Sector Number 79

Definition at line 430 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_8 8U

Sector Number 8

Definition at line 359 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_80 80U

Sector Number 80

Definition at line 431 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_81 81U

Sector Number 81

Definition at line 432 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_82 82U

Sector Number 82

Definition at line 433 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_83 83U

Sector Number 83

Definition at line 434 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_84 84U

Sector Number 84

Definition at line 435 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_85 85U

Sector Number 85

Definition at line 436 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_86 86U

Sector Number 86

Definition at line 437 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_87 87U

Sector Number 87

Definition at line 438 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_88 88U

Sector Number 88

Definition at line 439 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_89 89U

Sector Number 89

Definition at line 440 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_9 9U

Sector Number 9

Definition at line 360 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_90 90U

Sector Number 90

Definition at line 441 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_91 91U

Sector Number 91

Definition at line 442 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_92 92U

Sector Number 92

Definition at line 443 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_93 93U

Sector Number 93

Definition at line 444 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_94 94U

Sector Number 94

Definition at line 445 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_95 95U

Sector Number 95

Definition at line 446 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_96 96U

Sector Number 96

Definition at line 447 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_97 97U

Sector Number 97

Definition at line 448 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_98 98U

Sector Number 98

Definition at line 449 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_99 99U

Sector Number 99

Definition at line 450 of file stm32h7xx_hal_flash.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
Checks whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
#define | __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
Clear the specified FLASH flag.
#define | __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
(IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))

Definition at line 685 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define __HAL_FLASH_CLEAR_FLAG_BANK1 ( __FLAG__ ) WRITE_REG(FLASH->CCR1, (__FLAG__))

Clear the specified FLASH flag.

Parameters:
__FLAG__,: specifies the FLASH flags to clear. In case of Bank 1, this parameter can be any combination of the following values:
  • FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
  • FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
  • FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
  • FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
  • FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
  • FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
  • FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
  • FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
  • FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
  • FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
  • FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
  • FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
  • FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
  • FLASH_FLAG_ALL_BANK1 : All Bank 1 flags
In case of Bank 2, this parameter can be any combination of the following values :
  • FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
  • FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
  • FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
  • FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
  • FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
  • FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
  • FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
  • FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
  • FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
  • FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
  • FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
  • FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
  • FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
  • FLASH_FLAG_ALL_BANK2 : All Bank 2 flags
Return values:
none

Definition at line 681 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_ComputeCRC().

#define __HAL_FLASH_CLEAR_FLAG_BANK2 ( __FLAG__ ) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))

Definition at line 683 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_ComputeCRC().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
(IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))

Definition at line 591 of file stm32h7xx_hal_flash.h.

#define __HAL_FLASH_DISABLE_IT_BANK1 ( __INTERRUPT__ ) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt In case of Bank 1 This parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
  • FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
  • FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
  • FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
  • FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
  • FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
  • FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
  • FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
  • FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
  • FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
  • FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
  • FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
In case of Bank 2, this parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
  • FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
  • FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
  • FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
  • FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
  • FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
  • FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
  • FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
  • FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
  • FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
  • FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
  • FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
Return values:
none

Definition at line 587 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT_BANK2 ( __INTERRUPT__ ) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))

Definition at line 589 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
(IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))

Definition at line 547 of file stm32h7xx_hal_flash.h.

#define __HAL_FLASH_ENABLE_IT_BANK1 ( __INTERRUPT__ ) (FLASH->CR1 |= (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt In case of Bank 1 This parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
  • FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
  • FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
  • FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
  • FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
  • FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
  • FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
  • FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
  • FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
  • FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
  • FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
  • FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
In case of Bank 2, this parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
  • FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
  • FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
  • FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
  • FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
  • FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
  • FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
  • FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
  • FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
  • FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
  • FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
  • FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
Return values:
none

Definition at line 543 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_ENABLE_IT_BANK2 ( __INTERRUPT__ ) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))

Definition at line 545 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
(IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))

Definition at line 640 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), and FLASH_WaitForLastOperation().

#define __HAL_FLASH_GET_FLAG_BANK1 ( __FLAG__ ) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))

Checks whether the specified FLASH flag is set or not.

Parameters:
__FLAG__,: specifies the FLASH flag to check. In case of Bank 1 This parameter can be one of the following values :
  • FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
  • FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag
  • FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag
  • FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
  • FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
  • FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
  • FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
  • FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
  • FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
  • FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
  • FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
  • FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
  • FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
  • FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
  • FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
  • FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
In case of Bank 2 This parameter can be one of the following values :
  • FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
  • FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag
  • FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag
  • FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
  • FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
  • FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
  • FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
  • FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
  • FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
  • FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
  • FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
  • FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
  • FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
  • FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
  • FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
  • FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 636 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_GET_FLAG_BANK2 ( __FLAG__ ) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))

Definition at line 638 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency The value of this parameter depend on device used within the same series

Definition at line 506 of file stm32h7xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__,: FLASH Latency The value of this parameter depend on device used within the same series
Return values:
none

Definition at line 498 of file stm32h7xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 114 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Definition at line 107 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define | IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
#define | IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define | IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)
#define | IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)

Define Documentation

#define IS_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) <= (0x3FFF0000U))

Definition at line 791 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_BootAddConfig().

#define IS_FLASH_BANK ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2)  || \
                                            ((BANK) == FLASH_BANK_BOTH))

Definition at line 793 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define IS_FLASH_BANK_EXCLUSIVE ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2))

Definition at line 797 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_WaitForLastOperation(), FLASH_Erase_Sector(), FLASH_WaitForLastOperation(), and HAL_FLASHEx_ComputeCRC().

#define IS_FLASH_FLAG_BANK1 ( FLAG ) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))

Definition at line 774 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_FLAG_BANK2 ( FLAG ) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))

Definition at line 776 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_IT_BANK1 ( IT ) (((IT) & FLASH_IT_ALL_BANK1) == (IT))

Definition at line 770 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_IT_BANK2 ( IT ) (((IT) & FLASH_IT_ALL_BANK2) == (IT))

Definition at line 772 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS )
Value:
(IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))

Definition at line 783 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_ADDRESS_BANK1 ( ADDRESS ) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))

Definition at line 778 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_SelectAddress(), FLASH_OB_PCROPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_ADDRESS_BANK2 ( ADDRESS ) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))

Definition at line 779 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_CRC_SelectAddress(), FLASH_OB_PCROPConfig(), and FLASH_OB_SecureAreaConfig().

#define IS_FLASH_PROGRAM_ADDRESS_OTP ( ADDRESS ) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))

Definition at line 782 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))

Definition at line 764 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Private functions

Functions
FLASH Private functions
FLASH

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.
HAL_StatusTypeDef | FLASH_CRC_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH CRC computation to complete.

Function Documentation

HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation | ( | uint32_t | Timeout,
 |  | uint32_t | Bank
 | ) |  |

Wait for a FLASH CRC computation to complete.

Parameters:
Timeout | maximum flash operation timeout
Bank | flash FLASH_BANK_1 or FLASH_BANK_2
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 1024 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_GET_FLAG, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_FLAG_CRC_BUSY_BANK1, FLASH_FLAG_CRC_BUSY_BANK2, FLASH_FLAG_CRCRDERR_BANK1, FLASH_FLAG_CRCRDERR_BANK2, HAL_FLASH_ERROR_CRCRD_BANK1, HAL_FLASH_ERROR_CRCRD_BANK2, HAL_GetTick(), and IS_FLASH_BANK_EXCLUSIVE.

Referenced by HAL_FLASH_OB_Launch(), and HAL_FLASHEx_ComputeCRC().

HAL_StatusTypeDef FLASH_OB_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH Option Bytes change operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 985 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, HAL_FLASH_ERROR_OB_CHANGE, and HAL_GetTick().

Referenced by HAL_FLASH_OB_Launch(), and HAL_FLASHEx_ComputeCRC().

HAL_StatusTypeDef FLASH_WaitForLastOperation | ( | uint32_t | Timeout,
 |  | uint32_t | Bank
 | ) |  |

Wait for a FLASH operation to complete.

Parameters:
Timeout | maximum flash operation timeout
Bank | flash FLASH_BANK_1 or FLASH_BANK_2
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 905 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_GET_FLAG, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_QW_BANK1, FLASH_FLAG_QW_BANK2, HAL_GetTick(), and IS_FLASH_BANK_EXCLUSIVE.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH

Modules | Variables
FLASH
STM32H7xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Exported functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros
FLASH Private Variables
FLASH Private Constants
FLASH Private Macros
FLASH Private functions

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 114 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx | FLASH Exported Constants

Functions

static void | FLASH_MassErase (uint32_t VoltageRange, uint32_t Banks)
Mass erase of FLASH memory.
static void | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_GetWRP (uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
Get the write protection of the given bank 1 or bank 2 sectors.
static void | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static uint32_t | FLASH_OB_GetRDP (void)
Get the read protection level.
static void | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
Get the Proprietary code readout protection configuration on a given Bank.
static void | FLASH_OB_BOR_LevelConfig (uint32_t Level)
Set the BOR Level.
static uint32_t | FLASH_OB_GetBOR (void)
Get the BOR Level.
static void | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_BootAddConfig (uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
Set Boot address.
static void | FLASH_OB_GetBootAdd (uint32_t *BootAddress0, uint32_t *BootAddress1)
Get Boot address.
static void | FLASH_OB_SecureAreaConfig (uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
Set secure area configuration.
static void | FLASH_OB_GetSecureArea (uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
Get secure area configuration.
static void | FLASH_CRC_AddSector (uint32_t Sector, uint32_t Bank)
Add a CRC sector to the list of sectors on which the CRC will be calculated.
static void | FLASH_CRC_SelectAddress (uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
Select CRC start and end memory addresses on which the CRC will be calculated.
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
Erase the specified FLASH memory sector.

Function Documentation

static void FLASH_CRC_AddSector | ( | uint32_t | Sector,
 |  | uint32_t | Bank
 | ) |  | [static]

Add a CRC sector to the list of sectors on which the CRC will be calculated.

Parameters:
Sector | Specifies the CRC sector number
Bank | Specifies the Bank
Return values:
None

Definition at line 1617 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, and IS_FLASH_SECTOR.

Referenced by HAL_FLASHEx_ComputeCRC().

static void FLASH_CRC_SelectAddress | ( | uint32_t | CRCStartAddr,
 |  | uint32_t | CRCEndAddr,
 |  | uint32_t | Bank
 | ) |  | [static]

Select CRC start and end memory addresses on which the CRC will be calculated.

Parameters:
CRCStartAddr | Specifies the CRC start address
CRCEndAddr | Specifies the CRC end address
Bank | Specifies the Bank
Return values:
None

Definition at line 1647 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_PROGRAM_ADDRESS_BANK1, and IS_FLASH_PROGRAM_ADDRESS_BANK2.

Referenced by HAL_FLASHEx_ComputeCRC().

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint32_t | Banks,
 |  | uint32_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector FLASH sector to erase This parameter can be a value of FLASH Sectors
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
VoltageRange The device program/erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
  • FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
  • FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
  • FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
Return values:
None

Definition at line 852 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK_EXCLUSIVE, and IS_FLASH_SECTOR.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_MassErase | ( | uint32_t | VoltageRange,
 |  | uint32_t | Banks
 | ) |  | [static]

Mass erase of FLASH memory.

Parameters:
VoltageRange The device program/erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
  • FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
  • FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
  • FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
Return values:
HAL Status

Definition at line 780 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, and IS_FLASH_BANK.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_OB_BootAddConfig | ( | uint32_t | BootOption,
 |  | uint32_t | BootAddress0,
 |  | uint32_t | BootAddress1
 | ) |  | [static]

Set Boot address.

Parameters:
BootOption | Boot address option byte to be programmed, This parameter must be a value of FLASHEx OB BOOT OPTION (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
BootAddress0 | Specifies the Boot Address 0
BootAddress1 | Specifies the Boot Address 1
Return values:
HAL Status

Definition at line 1424 of file stm32h7xx_hal_flash_ex.c.

References assert_param, IS_BOOT_ADDRESS, IS_OB_BOOT_ADD_OPTION, OB_BOOT_ADD0, and OB_BOOT_ADD1.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_BOR_LevelConfig ( uint32_t Level ) [static]

Set the BOR Level.

Parameters:
Level specifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
  • OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
  • OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
  • OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
Return values:
None

Definition at line 1392 of file stm32h7xx_hal_flash_ex.c.

References assert_param, and IS_OB_BOR_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_DisableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Disable the write protection of the desired bank1 or bank 2 sectors.

Parameters:
WRPSector specifies the sector(s) to disable write protection. This parameter can be one of the following values:
  • WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
Banks the specific bank to apply WRP sectors This parameter can be one of the following values:
  • FLASH_BANK_1: disable WRP on specified bank1 sectors
  • FLASH_BANK_2: disable WRP on specified bank2 sectors
  • FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
Return values:
HAL FLASH State

Definition at line 940 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK, and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_EnableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Enable the write protection of the desired bank1 or bank 2 sectors.

Parameters:
WRPSector specifies the sector(s) to be write protected. This parameter can be one of the following values:
  • WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
Banks the specific bank to apply WRP sectors This parameter can be one of the following values:
  • FLASH_BANK_1: enable WRP on specified bank1 sectors
  • FLASH_BANK_2: enable WRP on specified bank2 sectors
  • FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
Return values:
HAL FLASH State

Definition at line 907 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK, and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetBootAdd | ( | uint32_t * | BootAddress0,
 |  | uint32_t * | BootAddress1
 | ) |  | [static]

Get Boot address.

Parameters:
BootAddress0 | Specifies the Boot Address 0.
BootAddress1 | Specifies the Boot Address 1.
Return values:
HAL Status

Definition at line 1462 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetBOR ( void ) [static]

Get the BOR Level.

Return values:
The Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
  • OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
  • OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
  • OB_BOR_LEVEL3: Reset level threshold is set to 2.7V

Definition at line 1409 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROPStartAddr,
 |  | uint32_t * | PCROPEndAddr,
 |  | uint32_t | Bank
 | ) |  | [static]

Get the Proprietary code readout protection configuration on a given Bank.

Parameters:
PCROPConfig | indicates if the PCROP area for the given Bank shall be erased or not when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
PCROPStartAddr | gives the start address of the Proprietary code readout protection of the bank
PCROPEndAddr | gives the end address of the Proprietary code readout protection of the bank
Bank the specific bank to apply PCROP protection This parameter can be exclusively one of the following values:
  • FLASH_BANK_1: PCROP on specified bank1 area
  • FLASH_BANK_2: PCROP on specified bank2 area
  • FLASH_BANK_BOTH: is not allowed here
Return values:
None

Definition at line 1358 of file stm32h7xx_hal_flash_ex.c.

References FLASH_BANK_1, FLASH_BANK_2, and FLASH_BANK_BOTH.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Get the read protection level.

Return values:
RDPLevel specifies the read protection level. This return value can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 1038 of file stm32h7xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetSecureArea | ( | uint32_t * | SecureAreaConfig,
 |  | uint32_t * | SecureAreaStartAddr,
 |  | uint32_t * | SecureAreaEndAddr,
 |  | uint32_t | Bank
 | ) |  | [static]

Get secure area configuration.

Parameters:
SecureAreaConfig | indicates if the secure area will be deleted or not when RDP level decreased from Level 1 to Level 0 or during a mass erase.
SecureAreaStartAddr | gives the secure area start address
SecureAreaEndAddr | gives the secure area end address
Bank | Specifies the Bank
Return values:
None

Definition at line 1586 of file stm32h7xx_hal_flash_ex.c.

References FLASH_BANK_1, FLASH_BANK_2, and FLASH_BANK_BOTH.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).

Definition at line 1277 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetWRP | ( | uint32_t * | WRPState,
 |  | uint32_t * | WRPSector,
 |  | uint32_t | Bank
 | ) |  | [static]

Get the write protection of the given bank 1 or bank 2 sectors.

Parameters:
WRPState gives the write protection state on the given bank. This parameter can be one of the following values:
  • WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
WRPSector gives the write protected sector(s) on the given bank . This parameter can be one of the following values:
  • WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
Bank the specific bank to apply WRP sectors This parameter can be exclusively one of the following values:
  • FLASH_BANK_1: Get bank1 WRP sectors
  • FLASH_BANK_2: Get bank2 WRP sectors
  • FLASH_BANK_BOTH: note allowed in this functions
Return values:
HAL FLASH State

Definition at line 977 of file stm32h7xx_hal_flash_ex.c.

References FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, OB_WRPSTATE_DISABLE, and OB_WRPSTATE_ENABLE.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_PCROPConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROPStartAddr,
 |  | uint32_t | PCROPEndAddr,
 |  | uint32_t | Banks
 | ) |  | [static]

Configure the Proprietary code readout protection of the desired addresses.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the PCROP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal This parameter must be a value of
  • FLASHEx_OB_PCROP_RDP enumeration
PCROPStartAddr | specifies the start address of the Proprietary code readout protection This parameter can be an address between begin and end of the bank
PCROPEndAddr | specifies the end address of the Proprietary code readout protection This parameter can be an address between PCROPStartAddr and end of the bank
Banks the specific bank to apply PCROP protection This parameter can be one of the following values:
  • FLASH_BANK_1: PCROP on specified bank1 area
  • FLASH_BANK_2: PCROP on specified bank2 area
  • FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
Return values:
None

Definition at line 1311 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_BANK2, and IS_OB_PCROP_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_RDPConfig ( uint32_t RDPLevel ) [static]

Set the read protection level.

Note:
To configure the RDP level, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the RDP level, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
!!! Warning : When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 !!!
Parameters:
RDPLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection
Return values:
HAL status

Definition at line 1021 of file stm32h7xx_hal_flash_ex.c.

References assert_param, and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_SecureAreaConfig | ( | uint32_t | SecureAreaConfig,
 |  | uint32_t | SecureAreaStartAddr,
 |  | uint32_t | SecureAreaEndAddr,
 |  | uint32_t | Banks
 | ) |  | [static]

Set secure area configuration.

Parameters:
SecureAreaConfig | specify if the secure area will be deleted or not when RDP level decreased from Level 1 to Level 0 or during a mass erase.
SecureAreaStartAddr | Specifies the secure area start address
SecureAreaEndAddr | Specifies the secure area end address
Banks the specific bank to apply Security protection This parameter can be one of the following values:
  • FLASH_BANK_1: Secure area on specified bank1 area
  • FLASH_BANK_2: Secure area on specified bank2 area
  • FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
Return values:
None

Definition at line 1546 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_BANK2, and IS_OB_SECURE_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_UserConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig
 | ) |  | [static]

Program the FLASH User Option Byte.

Note:
To configure the user option bytes, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the user option bytes, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
UserType The FLASH User Option Bytes to be modified : a combination of
  • FLASHEx_OB_USER_Type
UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
Return values:
HAL status

Definition at line 1094 of file stm32h7xx_hal_flash_ex.c.

References assert_param, IS_OB_IWDG1_SOURCE, IS_OB_STDBY_D1_RESET, IS_OB_STOP_D1_RESET, IS_OB_USER_IOHSLV, IS_OB_USER_IWDG_STDBY, IS_OB_USER_IWDG_STOP, IS_OB_USER_SECURITY, IS_OB_USER_ST_RAM_SIZE, IS_OB_USER_SWAP_BANK, IS_OB_USER_TYPE, IS_OB_USER_VDDMMC_HSLV, OB_USER_IOHSLV, OB_USER_IWDG1_SW, OB_USER_IWDG_STDBY, OB_USER_IWDG_STOP, OB_USER_NRST_STDBY_D1, OB_USER_NRST_STOP_D1, OB_USER_SECURITY, OB_USER_ST_RAM_SIZE, OB_USER_SWAP_BANK, and OB_USER_VDDMMC_HSLV.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASHEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_ComputeCRC (FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extension FLASH
    programming operations Operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC | ( | FLASH_CRCInitTypeDef * | pCRCInit,
 |  | uint32_t * | CRC_Result
 | ) |  |

Definition at line 634 of file stm32h7xx_hal_flash_ex.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, assert_param, FLASH_CRCInitTypeDef::Bank, FLASH_CRCInitTypeDef::BurstSize, FLASH_CRCInitTypeDef::CRCEndAddr, FLASH_CRCInitTypeDef::CRCStartAddr, FLASH_BANK_1, FLASH_BANK_2, FLASH_CRC_AddSector(), FLASH_CRC_BANK, FLASH_CRC_SECTORS, FLASH_CRC_SelectAddress(), FLASH_CRC_WaitForLastOperation(), FLASH_FLAG_CRCEND_BANK1, FLASH_FLAG_CRCEND_BANK2, FLASH_FLAG_CRCRDERR_BANK1, FLASH_FLAG_CRCRDERR_BANK2, FLASH_OB_WaitForLastOperation(), FLASH_TIMEOUT_VALUE, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_TYPECRC, FLASH_CRCInitTypeDef::NbSectors, FLASH_CRCInitTypeDef::Sector, and FLASH_CRCInitTypeDef::TypeCRC.

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | SectorError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory sectors.

Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | SectorError | pointer to variable that contains the configuration information on faulty sector in case of error (0xFFFFFFFF means that all the sectors have been correctly erased)
Return values:
HAL Status

Definition at line 166 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_BANK, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, pFlash, FLASH_EraseInitTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.

Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 276 of file stm32h7xx_hal_flash_ex.c.

References __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_MassErase(), FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_BANK, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, FLASH_ProcessTypeDef::NbSectorsToErase, pFlash, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_EraseInitTypeDef::Sector, FLASH_ProcessTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, FLASH_ProcessTypeDef::VoltageForErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1 ( void )

Locks the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 583 of file stm32h7xx_hal_flash_ex.c.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2 ( void )

Locks the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 616 of file stm32h7xx_hal_flash_ex.c.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Note:
The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
Return values:
None

Definition at line 511 of file stm32h7xx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_BANK_1, FLASH_BANK_2, FLASH_OB_GetBootAdd(), FLASH_OB_GetBOR(), FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), FLASH_OB_OTP_GetLock(), OPTIONBYTE_BOOTADD, OPTIONBYTE_BOR, OPTIONBYTE_OTP_LOCK, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SECURE_AREA, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::OTPBlockLock, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 386 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BootConfig, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_OTP_LockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_BANK, IS_OPTIONBYTE, IS_WRPSTATE, OB_WRPSTATE_ENABLE, OPTIONBYTE_BOOTADD, OPTIONBYTE_BOR, OPTIONBYTE_OTP_LOCK, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SECURE_AREA, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::OTPBlockLock, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, pFlash, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1 ( void )

Unlock the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 561 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2 ( void )

Unlock the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 594 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32h7xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Sector
uint32_t | NbSectors
uint32_t | VoltageRange

Detailed Description

FLASH Erase structure definition.

Definition at line 47 of file stm32h7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select banks to erase when Mass erase is enabled. This parameter must be a value of FLASH Banks

Definition at line 52 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbSectors

Number of sectors to be erased. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)

Definition at line 58 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Sector

Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of FLASH Sectors

Definition at line 55 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or sector Erase. This parameter can be a value of FLASH Type Erase

Definition at line 49 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::VoltageRange

The device voltage range which defines the erase parallelism This parameter must be a value of FLASHEx_Voltage_Range

Definition at line 61 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash_ex.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32h7xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPSector
uint32_t | RDPLevel
uint32_t | BORLevel
uint32_t | USERType
uint32_t | USERConfig
uint32_t | Banks
uint32_t | PCROPConfig
uint32_t | PCROPStartAddr
uint32_t | PCROPEndAddr
uint32_t | BootConfig
uint32_t | BootAddr0
uint32_t | BootAddr1
uint32_t | SecureAreaConfig
uint32_t | SecureAreaStartAddr
uint32_t | SecureAreaEndAddr
uint32_t | OTPBlockLock

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 70 of file stm32h7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::Banks

Select banks for WRP , PCROP and secure area config . This parameter must be a value of FLASH Banks

Definition at line 93 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootAddr0

Boot Address 0. This parameter must be a value between begin and end of a bank

Definition at line 109 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootAddr1

Boot Address 1. This parameter must be a value between begin and end of a bank

Definition at line 112 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootConfig

Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 or both. This parameter must be a value of FLASHEx OB BOOT OPTION enumeration

Definition at line 106 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BORLevel

Set the BOR Level. This parameter can be a value of FLASH BOR Reset Level

Definition at line 84 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a value of FLASH Option Type

Definition at line 72 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OTPBlockLock

Specifies the OTP block(s) to be locked. This parameter must be a value of FLASH OTP blocks

Definition at line 137 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

specifies if the PCROP area shall be erased or not when RDP level decreased from Level 1 to Level 0 or during a mass erase. This parameter must be a value of FLASHEx OB PCROP RDP enumeration

Definition at line 96 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of a bank

Definition at line 103 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of a bank

Definition at line 100 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level. This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 81 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaConfig

specifies if the bank secured area shall be erased or not when RDP level decreased from Level 1 to Level 0 or during a mass erase. This parameter must be a value of FLASHEx OB SECURE RDP enumeration

Definition at line 126 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaEndAddr

Bank Secure area End address. This parameter must be a value between Secure Area Start address and end address of a bank1

Definition at line 133 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaStartAddr

Bank Secure area Start address. This parameter must be a value between begin address and end address of bank1

Definition at line 130 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT

Definition at line 90 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASHEx OB USER Type

Definition at line 87 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPSector

Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series

Definition at line 78 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

Write protection activation or deactivation. This parameter can be a value of FLASH WRP State

Definition at line 75 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash_ex.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH_CRCInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_CRCInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32h7xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeCRC
uint32_t | BurstSize
uint32_t | Bank
uint32_t | Sector
uint32_t | NbSectors
uint32_t | CRCStartAddr
uint32_t | CRCEndAddr

Detailed Description

FLASH Erase structure definition.

Definition at line 146 of file stm32h7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_CRCInitTypeDef::Bank

Select bank where CRC computation is enabled. This parameter must be FLASH_BANK_1 or FLASH_BANK_2

Definition at line 154 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::BurstSize

CRC Burst Size. This parameter can be a value of FLASH CRC Burst Size

Definition at line 151 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::CRCEndAddr

CRC End address. This parameter must be a value between CRC Start address and end address of a bank

Definition at line 166 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::CRCStartAddr

CRC Start address. This parameter must be a value between begin address and end address of a bank

Definition at line 163 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::NbSectors

Number of sectors to be computed. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)

Definition at line 160 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::Sector

Initial FLASH sector from which starts the CRC computation This parameter must be a value of FLASH Sectors

Definition at line 157 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

uint32_t FLASH_CRCInitTypeDef::TypeCRC

CRC Selection Type. This parameter can be a value of FLASH CRC Selection Type

Definition at line 148 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash_ex.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Type Erase

Defines
FLASH Type Erase
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_SECTORS 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x01U

Define Documentation

#define FLASH_TYPEERASE_MASSERASE 0x01U

Flash Mass erase activation

Definition at line 184 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_SECTORS 0x00U

Sectors erase only

Definition at line 183 of file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH WRP State

Defines
FLASH WRP State
FLASH Exported Constants

Defines

#define | OB_WRPSTATE_DISABLE 0x00000000U
#define | OB_WRPSTATE_ENABLE 0x00000001U

Define Documentation

#define OB_WRPSTATE_DISABLE 0x00000000U

Disable the write protection of the desired bank 1 sectors

Definition at line 205 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetWRP().

#define OB_WRPSTATE_ENABLE 0x00000001U

Enable the write protection of the desired bank 1 sectors

Definition at line 206 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetWRP(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Option Type

Defines
FLASH Option Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_PCROP 0x08U
#define | OPTIONBYTE_BOR 0x10U
#define | OPTIONBYTE_SECURE_AREA 0x20U
#define | OPTIONBYTE_BOOTADD 0x40U
#define | OPTIONBYTE_OTP_LOCK 0x80U

Define Documentation

#define OPTIONBYTE_BOOTADD 0x40U

BOOT ADD option byte configuration

Definition at line 225 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_BOR 0x10U

BOR option byte configuration

Definition at line 218 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_OTP_LOCK 0x80U

OTP Lock option byte configuration

Definition at line 228 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_PCROP 0x08U

PCROP option byte configuration

Definition at line 217 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP 0x02U

RDP option byte configuration

Definition at line 215 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_SECURE_AREA 0x20U

secure area option byte configuration

Definition at line 219 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER 0x04U

USER option byte configuration

Definition at line 216 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP 0x01U

WRP option byte configuration

Definition at line 214 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 0xAA00U
#define | OB_RDP_LEVEL_1 0x5500U
#define | OB_RDP_LEVEL_2 0xCC00U

Define Documentation

#define OB_RDP_LEVEL_0 0xAA00U

Definition at line 237 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 0x5500U

Definition at line 238 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 0xCC00U

Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0

Definition at line 239 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Option Bytes WWatchdog

Defines
FLASH Option Bytes WWatchdog
FLASH Exported Constants

Defines

#define | OB_WWDG_SW 0x10U
#define | OB_WWDG_HW 0x00U

Define Documentation

#define OB_WWDG_HW 0x00U

Hardware WWDG selected

Definition at line 249 of file stm32h7xx_hal_flash_ex.h.

#define OB_WWDG_SW 0x10U

Software WWDG selected

Definition at line 248 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Option Bytes IWatchdog

Defines
FLASH Option Bytes IWatchdog
FLASH Exported Constants

Defines

#define | OB_IWDG_SW 0x20U
#define | OB_IWDG_HW 0x00U

Define Documentation

#define OB_IWDG_HW 0x00U

Hardware IWDG selected

Definition at line 259 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_SW 0x20U

Software IWDG selected

Definition at line 258 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Option Bytes nRST_STOP

Defines
FLASH Option Bytes nRST_STOP
FLASH Exported Constants

Defines

#define | OB_STOP_NO_RST 0x40U
#define | OB_STOP_RST 0x00U

Define Documentation

#define OB_STOP_NO_RST 0x40U

No reset generated when entering in STOP

Definition at line 267 of file stm32h7xx_hal_flash_ex.h.

#define OB_STOP_RST 0x00U

Reset generated when entering in STOP

Definition at line 268 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Option Bytes nRST_STDBY

Defines
FLASH Option Bytes nRST_STDBY
FLASH Exported Constants

Defines

#define | OB_STDBY_NO_RST 0x80U
#define | OB_STDBY_RST 0x00U

Define Documentation

#define OB_STDBY_NO_RST 0x80U

No reset generated when entering in STANDBY

Definition at line 276 of file stm32h7xx_hal_flash_ex.h.

#define OB_STDBY_RST 0x00U

Reset generated when entering in STANDBY

Definition at line 277 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH IWDG Counter Freeze in STOP

Defines
FLASH IWDG Counter Freeze in STOP
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP

Define Documentation

#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP

IWDG counter active in STOP mode

Definition at line 286 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_STOP_FREEZE 0x00000000U

Freeze IWDG counter in STOP mode

Definition at line 285 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH IWDG Counter Freeze in STANDBY

Defines
FLASH IWDG Counter Freeze in STANDBY
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY

Define Documentation

#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY

IWDG counter active in STANDBY mode

Definition at line 295 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_STDBY_FREEZE 0x00000000U

Freeze IWDG counter in STANDBY mode

Definition at line 294 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH BOR Reset Level

Defines
FLASH BOR Reset Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL0 0x00000000U
#define | OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
#define | OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
#define | OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)

Define Documentation

#define OB_BOR_LEVEL0 0x00000000U

Reset level threshold is set to 1.6V

Definition at line 303 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0

Reset level threshold is set to 2.1V

Definition at line 304 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1

Reset level threshold is set to 2.4V

Definition at line 305 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)

Reset level threshold is set to 2.7V

Definition at line 306 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Boot Address

Defines
FLASH Boot Address
FLASH Exported Constants

Defines

#define | OB_BOOTADDR_ITCM_RAM 0x0000U
#define | OB_BOOTADDR_SYSTEM 0x0040U
#define | OB_BOOTADDR_ITCM_FLASH 0x0080U
#define | OB_BOOTADDR_AXIM_FLASH 0x2000U
#define | OB_BOOTADDR_DTCM_RAM 0x8000U
#define | OB_BOOTADDR_SRAM1 0x8004U
#define | OB_BOOTADDR_SRAM2 0x8013U

Define Documentation

#define OB_BOOTADDR_AXIM_FLASH 0x2000U

Boot from Flash on AXIM interface (0x08000000)

Definition at line 319 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_DTCM_RAM 0x8000U

Boot from DTCM RAM (0x20000000)

Definition at line 320 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_FLASH 0x0080U

Boot from Flash on ITCM interface (0x00200000)

Definition at line 318 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_RAM 0x0000U

Boot from ITCM RAM (0x00000000)

Definition at line 316 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM1 0x8004U

Boot from SRAM1 (0x20010000)

Definition at line 321 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM2 0x8013U

Boot from SRAM2 (0x2004C000)

Definition at line 322 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SYSTEM 0x0040U

Boot from System memory bootloader (0x00100000)

Definition at line 317 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero Latency cycle

Definition at line 330 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One Latency cycle

Definition at line 331 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS

FLASH Ten Latency cycles

Definition at line 340 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS

FLASH Eleven Latency cycles

Definition at line 341 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS

FLASH Twelve Latency cycles

Definition at line 342 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS

FLASH Thirteen Latency cycles

Definition at line 343 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS

FLASH Fourteen Latency cycles

Definition at line 344 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

FLASH Fifteen Latency cycles

Definition at line 345 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two Latency cycles

Definition at line 332 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three Latency cycles

Definition at line 333 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four Latency cycles

Definition at line 334 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH Five Latency cycles

Definition at line 335 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH Six Latency cycles

Definition at line 336 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH Seven Latency cycles

Definition at line 337 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS

FLASH Eight Latency cycle

Definition at line 338 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS

FLASH Nine Latency cycle

Definition at line 339 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define | FLASH_BANK_1 0x01U
#define | FLASH_BANK_2 0x02U
#define | FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)

Define Documentation

#define FLASH_BANK_1 0x01U

Bank 1

Definition at line 353 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_CRC_AddSector(), FLASH_CRC_SelectAddress(), FLASH_CRC_WaitForLastOperation(), FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_ComputeCRC(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define FLASH_BANK_2 0x02U

Bank 2

Definition at line 354 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASH_IRQHandler(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_ComputeCRC(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)

Bank1 and Bank2

Definition at line 355 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_MassErase(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), and FLASH_OB_GetWRP().

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STM32H7B3xQ HAL User Manual: FLASHEx OB PCROP RDP

Defines
FLASHEx OB PCROP RDP
FLASH Exported Constants

Defines

#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP

Define Documentation

#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 365 of file stm32h7xx_hal_flash_ex.h.

#define OB_PCROP_RDP_NOT_ERASE 0x00000000U

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase

Definition at line 363 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Option Bytes Write Protection

Defines
FLASH Option Bytes Write Protection
FLASH Exported Constants

Defines

#define | OB_WRP_SECTOR_0TO3 0x00000001U
#define | OB_WRP_SECTOR_4TO7 0x00000002U
#define | OB_WRP_SECTOR_8TO11 0x00000004U
#define | OB_WRP_SECTOR_12TO15 0x00000008U
#define | OB_WRP_SECTOR_16TO19 0x00000010U
#define | OB_WRP_SECTOR_20TO23 0x00000020U
#define | OB_WRP_SECTOR_24TO27 0x00000040U
#define | OB_WRP_SECTOR_28TO31 0x00000080U
#define | OB_WRP_SECTOR_32TO35 0x00000100U
#define | OB_WRP_SECTOR_36TO39 0x00000200U
#define | OB_WRP_SECTOR_40TO43 0x00000400U
#define | OB_WRP_SECTOR_44TO47 0x00000800U
#define | OB_WRP_SECTOR_48TO51 0x00001000U
#define | OB_WRP_SECTOR_52TO55 0x00002000U
#define | OB_WRP_SECTOR_56TO59 0x00004000U
#define | OB_WRP_SECTOR_60TO63 0x00008000U
#define | OB_WRP_SECTOR_64TO67 0x00010000U
#define | OB_WRP_SECTOR_68TO71 0x00020000U
#define | OB_WRP_SECTOR_72TO75 0x00040000U
#define | OB_WRP_SECTOR_76TO79 0x00080000U
#define | OB_WRP_SECTOR_80TO83 0x00100000U
#define | OB_WRP_SECTOR_84TO87 0x00200000U
#define | OB_WRP_SECTOR_88TO91 0x00400000U
#define | OB_WRP_SECTOR_92TO95 0x00800000U
#define | OB_WRP_SECTOR_96TO99 0x01000000U
#define | OB_WRP_SECTOR_100TO103 0x02000000U
#define | OB_WRP_SECTOR_104TO107 0x04000000U
#define | OB_WRP_SECTOR_108TO111 0x08000000U
#define | OB_WRP_SECTOR_112TO115 0x10000000U
#define | OB_WRP_SECTOR_116TO119 0x20000000U
#define | OB_WRP_SECTOR_120TO123 0x40000000U
#define | OB_WRP_SECTOR_124TO127 0x80000000U
#define | OB_WRP_SECTOR_ALL 0xFFFFFFFFU

Define Documentation

#define OB_WRP_SECTOR_0TO3 0x00000001U

Write protection of Sector0 to Sector3

Definition at line 376 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_100TO103 0x02000000U

Write protection of Sector100 to Sector103

Definition at line 401 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_104TO107 0x04000000U

Write protection of Sector104 to Sector107

Definition at line 402 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_108TO111 0x08000000U

Write protection of Sector108 to Sector111

Definition at line 403 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_112TO115 0x10000000U

Write protection of Sector112 to Sector115

Definition at line 404 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_116TO119 0x20000000U

Write protection of Sector116 to Sector119

Definition at line 405 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_120TO123 0x40000000U

Write protection of Sector120 to Sector123

Definition at line 406 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_124TO127 0x80000000U

Write protection of Sector124 to Sector127

Definition at line 407 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_12TO15 0x00000008U

Write protection of Sector12 to Sector15

Definition at line 379 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_16TO19 0x00000010U

Write protection of Sector16 to Sector19

Definition at line 380 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_20TO23 0x00000020U

Write protection of Sector20 to Sector23

Definition at line 381 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_24TO27 0x00000040U

Write protection of Sector24 to Sector27

Definition at line 382 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_28TO31 0x00000080U

Write protection of Sector28 to Sector31

Definition at line 383 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_32TO35 0x00000100U

Write protection of Sector32 to Sector35

Definition at line 384 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_36TO39 0x00000200U

Write protection of Sector36 to Sector39

Definition at line 385 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_40TO43 0x00000400U

Write protection of Sector40 to Sector43

Definition at line 386 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_44TO47 0x00000800U

Write protection of Sector44 to Sector47

Definition at line 387 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_48TO51 0x00001000U

Write protection of Sector48 to Sector51

Definition at line 388 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_4TO7 0x00000002U

Write protection of Sector4 to Sector7

Definition at line 377 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_52TO55 0x00002000U

Write protection of Sector52 to Sector55

Definition at line 389 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_56TO59 0x00004000U

Write protection of Sector56 to Sector59

Definition at line 390 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_60TO63 0x00008000U

Write protection of Sector60 to Sector63

Definition at line 391 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_64TO67 0x00010000U

Write protection of Sector64 to Sector67

Definition at line 392 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_68TO71 0x00020000U

Write protection of Sector68 to Sector71

Definition at line 393 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_72TO75 0x00040000U

Write protection of Sector72 to Sector75

Definition at line 394 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_76TO79 0x00080000U

Write protection of Sector76 to Sector79

Definition at line 395 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_80TO83 0x00100000U

Write protection of Sector80 to Sector83

Definition at line 396 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_84TO87 0x00200000U

Write protection of Sector84 to Sector87

Definition at line 397 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_88TO91 0x00400000U

Write protection of Sector88 to Sector91

Definition at line 398 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_8TO11 0x00000004U

Write protection of Sector8 to Sector11

Definition at line 378 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_92TO95 0x00800000U

Write protection of Sector92 to Sector95

Definition at line 399 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_96TO99 0x01000000U

Write protection of Sector96 to Sector99

Definition at line 400 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU

Write protection of all Sectors

Definition at line 408 of file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx OB SECURITY

Defines
FLASHEx OB SECURITY
FLASH Exported Constants

Defines

#define | OB_SECURITY_DISABLE 0x00000000U
#define | OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY

Define Documentation

#define OB_SECURITY_DISABLE 0x00000000U

security enabled

Definition at line 427 of file stm32h7xx_hal_flash_ex.h.

#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY

security disabled

Definition at line 428 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB ST RAM SIZE

Defines
FLASHEx OB ST RAM SIZE
FLASH Exported Constants

Defines

#define | OB_ST_RAM_SIZE_2KB 0x00000000U
#define | OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
#define | OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
#define | OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE

Define Documentation

#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE

16 Kbytes reserved to ST code

Definition at line 439 of file stm32h7xx_hal_flash_ex.h.

#define OB_ST_RAM_SIZE_2KB 0x00000000U

2 Kbytes reserved to ST code

Definition at line 436 of file stm32h7xx_hal_flash_ex.h.

#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0

4 Kbytes reserved to ST code

Definition at line 437 of file stm32h7xx_hal_flash_ex.h.

#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1

8 Kbytes reserved to ST code

Definition at line 438 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB IWDG1 SW

Defines
FLASHEx OB IWDG1 SW
FLASH Exported Constants

Defines

#define | OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
#define | OB_IWDG1_HW 0x00000000U

Define Documentation

#define OB_IWDG1_HW 0x00000000U

Software independent watchdog 1

Definition at line 469 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW

Hardware independent watchdog 1

Definition at line 468 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB NRST STOP D1

Defines
FLASHEx OB NRST STOP D1
FLASH Exported Constants

Defines

#define | OB_STOP_RST_D1 0x00000000U
#define | OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1

Define Documentation

#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1

No reset generated when entering the D1 to stop mode

Definition at line 489 of file stm32h7xx_hal_flash_ex.h.

#define OB_STOP_RST_D1 0x00000000U

Reset generated when entering the D1 to stop mode

Definition at line 488 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB NRST STDBY D1

Defines
FLASHEx OB NRST STDBY D1
FLASH Exported Constants

Defines

#define | OB_STDBY_RST_D1 0x00000000U
#define | OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1

Define Documentation

#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1

No reset generated when entering the D1 to standby mode

Definition at line 498 of file stm32h7xx_hal_flash_ex.h.

#define OB_STDBY_RST_D1 0x00000000U

Reset generated when entering the D1 to standby mode

Definition at line 497 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB SWAP BANK

Defines
FLASHEx OB SWAP BANK
FLASH Exported Constants

Defines

#define | OB_SWAP_BANK_DISABLE 0x00000000U
#define | OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT

Define Documentation

#define OB_SWAP_BANK_DISABLE 0x00000000U

Bank swap disabled

Definition at line 526 of file stm32h7xx_hal_flash_ex.h.

#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT

Bank swap enabled

Definition at line 527 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB IOHSLV

Defines
FLASHEx OB IOHSLV
FLASH Exported Constants

Defines

#define | OB_IOHSLV_DISABLE 0x00000000U
#define | OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV

Define Documentation

#define OB_IOHSLV_DISABLE 0x00000000U

IOHSLV disabled

Definition at line 535 of file stm32h7xx_hal_flash_ex.h.

#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV

IOHSLV enabled

Definition at line 536 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB VDDMMC HSLV

Defines
FLASHEx OB VDDMMC HSLV
FLASH Exported Constants

Defines

#define | OB_VDDMMC_HSLV_DISABLE 0x00000000U
#define | OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV

Define Documentation

#define OB_VDDMMC_HSLV_DISABLE 0x00000000U

VDDMMC HSLV disabled

Definition at line 545 of file stm32h7xx_hal_flash_ex.h.

#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV

VDDMMC HSLV enabled

Definition at line 546 of file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx OB BOOT OPTION

Defines
FLASHEx OB BOOT OPTION
FLASH Exported Constants

Defines

#define | OB_BOOT_ADD0 0x01U
#define | OB_BOOT_ADD1 0x02U
#define | OB_BOOT_ADD_BOTH 0x03U

Define Documentation

#define OB_BOOT_ADD0 0x01U

Select Boot Address 0

Definition at line 555 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define OB_BOOT_ADD1 0x02U

Select Boot Address 1

Definition at line 556 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define OB_BOOT_ADD_BOTH 0x03U

Select Boot Address 0 and 1

Definition at line 557 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASHEx OB USER Type

Defines
FLASHEx OB USER Type
FLASH Exported Constants

Defines

#define | OB_USER_IWDG1_SW 0x0001U
#define | OB_USER_NRST_STOP_D1 0x0002U
#define | OB_USER_NRST_STDBY_D1 0x0004U
#define | OB_USER_IWDG_STOP 0x0008U
#define | OB_USER_IWDG_STDBY 0x0010U
#define | OB_USER_ST_RAM_SIZE 0x0020U
#define | OB_USER_SECURITY 0x0040U
#define | OB_USER_IOHSLV 0x0080U
#define | OB_USER_SWAP_BANK 0x0100U
#define | OB_USER_VDDMMC_HSLV 0x0200U

Define Documentation

#define OB_USER_IOHSLV 0x0080U

IO HSLV selection

Definition at line 572 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG1_SW 0x0001U

Independent watchdog selection

Definition at line 565 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STDBY 0x0010U

Independent watchdog counter freeze in standby mode

Definition at line 569 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STOP 0x0008U

Independent watchdog counter freeze in stop mode

Definition at line 568 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_NRST_STDBY_D1 0x0004U

Reset when entering standby mode selection

Definition at line 567 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_NRST_STOP_D1 0x0002U

Reset when entering Stop mode selection

Definition at line 566 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SECURITY 0x0040U

security selection

Definition at line 571 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_ST_RAM_SIZE 0x0020U

dedicated DTCM Ram size selection

Definition at line 570 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SWAP_BANK 0x0100U

Bank swap selection

Definition at line 573 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_VDDMMC_HSLV 0x0200U

VDDMMC HSLV selection

Definition at line 575 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

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STM32H7B3xQ HAL User Manual: FLASHEx OB SECURE RDP

Defines
FLASHEx OB SECURE RDP
FLASH Exported Constants

Defines

#define | OB_SECURE_RDP_NOT_ERASE 0x00000000U
#define | OB_SECURE_RDP_ERASE FLASH_SCAR_DMES

Define Documentation

#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES

Secure area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 594 of file stm32h7xx_hal_flash_ex.h.

#define OB_SECURE_RDP_NOT_ERASE 0x00000000U

Secure area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase

Definition at line 592 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH CRC Selection Type

Defines
FLASH CRC Selection Type
FLASH Exported Constants

Defines

#define | FLASH_CRC_ADDR 0x00000000U
#define | FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
#define | FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)

Define Documentation

#define FLASH_CRC_ADDR 0x00000000U

CRC selection type by address

Definition at line 603 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)

CRC selection type by bank

Definition at line 605 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT

CRC selection type by sectors

Definition at line 604 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

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STM32H7B3xQ HAL User Manual: FLASH CRC Burst Size

Defines
FLASH CRC Burst Size
FLASH Exported Constants

Defines

#define | FLASH_CRC_BURST_SIZE_4 0x00000000U
#define | FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
#define | FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
#define | FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST

Define Documentation

#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0

Every burst has a size of 16 Flash words (256-bit)

Definition at line 614 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST

Every burst has a size of 256 Flash words (256-bit)

Definition at line 616 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_CRC_BURST_SIZE_4 0x00000000U

Every burst has a size of 4 Flash words (256-bit)

Definition at line 613 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1

Every burst has a size of 64 Flash words (256-bit)

Definition at line 615 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Programming Delay

Defines
FLASH Programming Delay
FLASH Exported Constants

Defines

#define | FLASH_PROGRAMMING_DELAY_0 0x00000000U
#define | FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
#define | FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
#define | FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ

Define Documentation

#define FLASH_PROGRAMMING_DELAY_0 0x00000000U

programming delay set for Flash running at 70 MHz or below

Definition at line 624 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0

programming delay set for Flash running between 70 MHz and 185 MHz

Definition at line 625 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1

programming delay set for Flash running between 185 MHz and 225 MHz

Definition at line 626 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ

programming delay set for Flash at startup

Definition at line 627 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH OTP blocks

Defines
FLASH OTP blocks
FLASH Exported Constants

Defines

#define | FLASH_OTP_BLOCK_0 0x00000001U
#define | FLASH_OTP_BLOCK_1 0x00000002U
#define | FLASH_OTP_BLOCK_2 0x00000004U
#define | FLASH_OTP_BLOCK_3 0x00000008U
#define | FLASH_OTP_BLOCK_4 0x00000010U
#define | FLASH_OTP_BLOCK_5 0x00000020U
#define | FLASH_OTP_BLOCK_6 0x00000040U
#define | FLASH_OTP_BLOCK_7 0x00000080U
#define | FLASH_OTP_BLOCK_8 0x00000100U
#define | FLASH_OTP_BLOCK_9 0x00000200U
#define | FLASH_OTP_BLOCK_10 0x00000400U
#define | FLASH_OTP_BLOCK_11 0x00000800U
#define | FLASH_OTP_BLOCK_12 0x00001000U
#define | FLASH_OTP_BLOCK_13 0x00002000U
#define | FLASH_OTP_BLOCK_14 0x00004000U
#define | FLASH_OTP_BLOCK_15 0x00008000U
#define | FLASH_OTP_BLOCK_ALL 0x0000FFFFU

Define Documentation

#define FLASH_OTP_BLOCK_0 0x00000001U

OTP Block0

Definition at line 636 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_1 0x00000002U

OTP Block1

Definition at line 637 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_10 0x00000400U

OTP Block10

Definition at line 646 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_11 0x00000800U

OTP Block11

Definition at line 647 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_12 0x00001000U

OTP Block12

Definition at line 648 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_13 0x00002000U

OTP Block13

Definition at line 649 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_14 0x00004000U

OTP Block14

Definition at line 650 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_15 0x00008000U

OTP Block15

Definition at line 651 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_2 0x00000004U

OTP Block2

Definition at line 638 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_3 0x00000008U

OTP Block3

Definition at line 639 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_4 0x00000010U

OTP Block4

Definition at line 640 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_5 0x00000020U

OTP Block5

Definition at line 641 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_6 0x00000040U

OTP Block6

Definition at line 642 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_7 0x00000080U

OTP Block7

Definition at line 643 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_8 0x00000100U

OTP Block8

Definition at line 644 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_9 0x00000200U

OTP Block9

Definition at line 645 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU

OTP All Blocks

Definition at line 652 of file stm32h7xx_hal_flash_ex.h.

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STM32H7B3xQ HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH Exported Constants

Defines

#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)

Define Documentation

#define __HAL_FLASH_CALC_BOOT_BASE_ADR ( __ADDRESS__ ) ((__ADDRESS__) >> 14U)

Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)

Note:
Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
Parameters:
__ADDRESS__,: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
Return values:
The FLASH Boot Base Adress

Definition at line 668 of file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx Private macros to check input parameters

Defines
FLASHEx Private macros to check input parameters
FLASHEx Private Macros

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
#define | IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define | IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
#define | IS_OB_PCROP_RDP(CONFIG)
#define | IS_OB_SECURE_RDP(CONFIG)
#define | IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
#define | IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define | IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
#define | IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#define | IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define | IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_USER_ST_RAM_SIZE(VALUE)
#define | IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
#define | IS_OB_BOOT_ADD_OPTION(VALUE)
#define | IS_FLASH_TYPECRC(VALUE)
#define | IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))

Define Documentation

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0)  || \
                                          ((LATENCY) == FLASH_LATENCY_1)  || \
                                          ((LATENCY) == FLASH_LATENCY_2)  || \
                                          ((LATENCY) == FLASH_LATENCY_3)  || \
                                          ((LATENCY) == FLASH_LATENCY_4)  || \
                                          ((LATENCY) == FLASH_LATENCY_5)  || \
                                          ((LATENCY) == FLASH_LATENCY_6)  || \
                                          ((LATENCY) == FLASH_LATENCY_7)  || \
                                          ((LATENCY) == FLASH_LATENCY_8)  || \
                                          ((LATENCY) == FLASH_LATENCY_9)  || \
                                          ((LATENCY) == FLASH_LATENCY_10) || \
                                          ((LATENCY) == FLASH_LATENCY_11) || \
                                          ((LATENCY) == FLASH_LATENCY_12) || \
                                          ((LATENCY) == FLASH_LATENCY_13) || \
                                          ((LATENCY) == FLASH_LATENCY_14) || \
                                          ((LATENCY) == FLASH_LATENCY_15))

Definition at line 793 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_SECTOR ( SECTOR ) ((SECTOR) < FLASH_SECTOR_TOTAL)

Definition at line 810 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_CRC_AddSector(), and FLASH_Erase_Sector().

#define IS_FLASH_TYPECRC ( VALUE )
Value:
(((VALUE) == FLASH_CRC_ADDR)    || \
                                          ((VALUE) == FLASH_CRC_SECTORS) || \
                                          ((VALUE) == FLASH_CRC_BANK))

Definition at line 868 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ComputeCRC().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 751 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_BOOT_ADD_OPTION ( VALUE )
Value:
(((VALUE) == OB_BOOT_ADD0)  || \
                                          ((VALUE) == OB_BOOT_ADD1)  || \
                                          ((VALUE) == OB_BOOT_ADD_BOTH))

Definition at line 864 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define IS_OB_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0x8013U)

Definition at line 772 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))

Definition at line 790 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BOR_LevelConfig().

#define IS_OB_IWDG1_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))

Definition at line 832 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 780 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_IWDG_STDBY_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))

Definition at line 788 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_IWDG_STOP_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))

Definition at line 786 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_PCROP_RDP ( CONFIG )
Value:
(((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
                                          ((CONFIG) == OB_PCROP_RDP_ERASE))

Definition at line 818 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_PCROPConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
                                          ((LEVEL) == OB_RDP_LEVEL_2))

Definition at line 774 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDPConfig().

#define IS_OB_SECURE_RDP ( CONFIG )
Value:
(((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
                                          ((CONFIG) == OB_SECURE_RDP_ERASE))

Definition at line 821 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_SecureAreaConfig().

#define IS_OB_STDBY_D1_RESET ( VALUE ) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))

Definition at line 838 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 784 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_STOP_D1_RESET ( VALUE ) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))

Definition at line 836 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 782 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_USER_IOHSLV ( VALUE ) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))

Definition at line 826 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STDBY ( VALUE ) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))

Definition at line 842 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STOP ( VALUE ) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))

Definition at line 840 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SECURITY ( VALUE ) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))

Definition at line 847 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_ST_RAM_SIZE ( VALUE )
Value:
(((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))

Definition at line 844 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SWAP_BANK ( VALUE ) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))

Definition at line 824 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_TYPE ( TYPE ) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))

Definition at line 861 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_VDDMMC_HSLV ( VALUE ) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))

Definition at line 829 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP_SECTOR ( SECTOR ) ((SECTOR) != 0x00000000U)

Definition at line 815 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OB_WWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))

Definition at line 778 of file stm32h7xx_hal_flash_ex.h.

#define IS_OPTIONBYTE ( VALUE ) (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))

Definition at line 765 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_OTP_BLOCK ( VALUE ) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))

Definition at line 873 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_OTP_LockConfig().

#define IS_WRPSTATE ( VALUE )
Value:
(((VALUE) == OB_WRPSTATE_DISABLE) || \
                                          ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 761 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH Exported Constants

Modules | Defines
FLASH Exported Constants
FLASHEx

Modules

FLASH Type Erase
FLASH WRP State
FLASH Option Type
FLASH Option Bytes Read Protection
FLASH Option Bytes WWatchdog
FLASH Option Bytes IWatchdog
FLASH Option Bytes nRST_STOP
FLASH Option Bytes nRST_STDBY
FLASH IWDG Counter Freeze in STOP
FLASH IWDG Counter Freeze in STANDBY
FLASH BOR Reset Level
FLASH Boot Address
FLASH Latency
FLASH Banks
FLASHEx OB PCROP RDP
FLASH Option Bytes Write Protection
FLASHEx OB SECURITY
FLASHEx OB ST RAM SIZE
FLASHEx OB IWDG1 SW
FLASHEx OB NRST STOP D1
FLASHEx OB NRST STDBY D1
FLASHEx OB SWAP BANK
FLASHEx OB IOHSLV
FLASHEx OB VDDMMC HSLV
FLASHEx OB BOOT OPTION
FLASHEx OB USER Type
FLASHEx OB SECURE RDP
FLASH CRC Selection Type
FLASH CRC Burst Size
FLASH Programming Delay
FLASH OTP blocks
FLASH Exported Macros
FLASHEx Private Macros
FLASHEx Private Functions
FLASHEx Exported Functions

Defines

#define | __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
Set the FLASH Programming Delay.
#define | __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
Get the FLASH Programming Delay.

Define Documentation

#define __HAL_FLASH_GET_PROGRAM_DELAY ( ) READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)

Get the FLASH Programming Delay.

Return values:
FLASH Programming Delay This return value can be a value of FLASH Programming Delay

Definition at line 709 of file stm32h7xx_hal_flash_ex.h.

#define __HAL_FLASH_SET_PROGRAM_DELAY ( __DELAY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))

Set the FLASH Programming Delay.

Parameters:
__DELAY__ FLASH Programming Delay This parameter can be a value of FLASH Programming Delay
Return values:
none

Definition at line 702 of file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx_Private_Constants

Defines
FLASHEx_Private_Constants
FLASHEx

Defines

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Definition at line 93 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_ComputeCRC(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASHEx

Modules | Functions
FLASHEx
STM32H7xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

FLASHEx Private Functions
FLASHEx Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASHEx_Private_Constants

Functions

static void | FLASH_OB_OTP_LockConfig (uint32_t OTP_Block)
Configure the OTP Block Lock.
static uint32_t | FLASH_OB_OTP_GetLock (void)
Get the OTP Block Lock.

Detailed Description

FLASH HAL Extension module driver.

Function Documentation

static uint32_t FLASH_OB_OTP_GetLock ( void ) [static]

Get the OTP Block Lock.

Return values:
OTP_Block specifies the OTP Block to lock. This return value can be a value of FLASH OTP blocks

Definition at line 1693 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_OTP_LockConfig ( uint32_t OTP_Block ) [static]

Configure the OTP Block Lock.

Parameters:
OTP_Block specifies the OTP Block to lock. This parameter can be a value of FLASH OTP blocks
Return values:
None

Definition at line 1679 of file stm32h7xx_hal_flash_ex.c.

References assert_param, and IS_OTP_BLOCK.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Tue Nov 12 2019 18:50:15 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GFXMMU Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_GFXMMU_Init (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU according to the specified parameters in the GFXMMU_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_GFXMMU_DeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU.
__weak void | HAL_GFXMMU_MspInit (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU MSP.
__weak void | HAL_GFXMMU_MspDeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU MSP.
HAL_StatusTypeDef | HAL_GFXMMU_RegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID, pGFXMMU_CallbackTypeDef pCallback)
Register a user GFXMMU callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_GFXMMU_UnRegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID)
Unregister a user GFXMMU callback.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the GFXMMU.
      (+) De-initialize the GFXMMU.

Function Documentation

HAL_StatusTypeDef HAL_GFXMMU_DeInit ( GFXMMU_HandleTypeDef * hgfxmmu )

De-initialize the GFXMMU.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
HAL status.

Definition at line 280 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, HAL_GFXMMU_MspDeInit(), HAL_GFXMMU_STATE_RESET, __GFXMMU_HandleTypeDef::Instance, __GFXMMU_HandleTypeDef::MspDeInitCallback, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_Init ( GFXMMU_HandleTypeDef * hgfxmmu )

Initialize the GFXMMU according to the specified parameters in the GFXMMU_InitTypeDef structure and initialize the associated handle.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
HAL status.

Definition at line 183 of file stm32h7xx_hal_gfxmmu.c.

References GFXMMU_CachePrefetchTypeDef::Activation, GFXMMU_InterruptsTypeDef::Activation, assert_param, GFXMMU_InitTypeDef::BlocksPerLine, GFXMMU_BuffersTypeDef::Buf0Address, GFXMMU_BuffersTypeDef::Buf1Address, GFXMMU_BuffersTypeDef::Buf2Address, GFXMMU_BuffersTypeDef::Buf3Address, GFXMMU_InitTypeDef::Buffers, GFXMMU_CachePrefetchTypeDef::CacheForce, GFXMMU_CachePrefetchTypeDef::CacheLock, GFXMMU_CachePrefetchTypeDef::CacheLockBuffer, GFXMMU_InitTypeDef::CachePrefetch, GFXMMU_InitTypeDef::DefaultValue, __GFXMMU_HandleTypeDef::ErrorCallback, __GFXMMU_HandleTypeDef::ErrorCode, GFXMMU_CACHE_FORCE_INVALIDATE, GFXMMU_CACHE_LOCK_ENABLE, GFXMMU_ERROR_NONE, HAL_GFXMMU_ErrorCallback(), HAL_GFXMMU_MspInit(), HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Init, __GFXMMU_HandleTypeDef::Instance, GFXMMU_InitTypeDef::Interrupts, IS_GFXMMU_BLOCKS_PER_LINE, IS_GFXMMU_BUFFER_ADDRESS, IS_GFXMMU_CACHE_FORCE, IS_GFXMMU_CACHE_LOCK, IS_GFXMMU_CACHE_LOCK_BUFFER, IS_GFXMMU_INTERRUPTS, IS_GFXMMU_OUTTER_BUFFERABILITY, IS_GFXMMU_OUTTER_CACHABILITY, IS_GFXMMU_PREFETCH, __GFXMMU_HandleTypeDef::MspInitCallback, GFXMMU_CachePrefetchTypeDef::OutterBufferability, GFXMMU_CachePrefetchTypeDef::OutterCachability, GFXMMU_CachePrefetchTypeDef::Prefetch, __GFXMMU_HandleTypeDef::State, and GFXMMU_InterruptsTypeDef::UsedInterrupts.

void HAL_GFXMMU_MspDeInit ( GFXMMU_HandleTypeDef * hgfxmmu )

De-initialize the GFXMMU MSP.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
None.

Definition at line 336 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_DeInit(), and HAL_GFXMMU_UnRegisterCallback().

void HAL_GFXMMU_MspInit ( GFXMMU_HandleTypeDef * hgfxmmu )

Initialize the GFXMMU MSP.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
None.

Definition at line 321 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_UnRegisterCallback().

HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | HAL_GFXMMU_CallbackIDTypeDef | CallbackID,
 |  | pGFXMMU_CallbackTypeDef | pCallback
 | ) |  |

Register a user GFXMMU callback to be used instead of the weak predefined callback.

Parameters:
hgfxmmu | GFXMMU handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_GFXMMU_ERROR_CB_ID error callback ID.
  • HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
  • HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 359 of file stm32h7xx_hal_gfxmmu.c.

References __GFXMMU_HandleTypeDef::ErrorCallback, __GFXMMU_HandleTypeDef::ErrorCode, GFXMMU_ERROR_INVALID_CALLBACK, HAL_GFXMMU_ERROR_CB_ID, HAL_GFXMMU_MSPDEINIT_CB_ID, HAL_GFXMMU_MSPINIT_CB_ID, HAL_GFXMMU_STATE_READY, HAL_GFXMMU_STATE_RESET, __GFXMMU_HandleTypeDef::MspDeInitCallback, __GFXMMU_HandleTypeDef::MspInitCallback, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | HAL_GFXMMU_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user GFXMMU callback.

GFXMMU callback is redirected to the weak predefined callback.

Parameters:
hgfxmmu GFXMMU handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_GFXMMU_ERROR_CB_ID error callback ID.
  • HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
  • HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 435 of file stm32h7xx_hal_gfxmmu.c.

References __GFXMMU_HandleTypeDef::ErrorCallback, __GFXMMU_HandleTypeDef::ErrorCode, GFXMMU_ERROR_INVALID_CALLBACK, HAL_GFXMMU_ERROR_CB_ID, HAL_GFXMMU_ErrorCallback(), HAL_GFXMMU_MspDeInit(), HAL_GFXMMU_MSPDEINIT_CB_ID, HAL_GFXMMU_MspInit(), HAL_GFXMMU_MSPINIT_CB_ID, HAL_GFXMMU_STATE_READY, HAL_GFXMMU_STATE_RESET, __GFXMMU_HandleTypeDef::MspDeInitCallback, __GFXMMU_HandleTypeDef::MspInitCallback, and __GFXMMU_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operations functions

Functions
Operations functions
GFXMMU Exported Functions

GFXMMU operation functions. More...

Functions

HAL_StatusTypeDef | HAL_GFXMMU_ConfigLut (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address)
This function allows to copy LUT from flash to look up RAM.
HAL_StatusTypeDef | HAL_GFXMMU_DisableLutLines (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber)
This function allows to disable a range of LUT lines.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigLutLine (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
This function allows to configure one line of LUT.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigForceCache (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
This function allows to force flush and/or invalidate of cache.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyBuffers (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
This function allows to modify physical buffer addresses.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyCachePrefetch (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_CachePrefetchTypeDef *CachePrefetch)
This function allows to modify cache and pre-fetch parameters.
void | HAL_GFXMMU_IRQHandler (GFXMMU_HandleTypeDef *hgfxmmu)
This function handles the GFXMMU interrupts.
__weak void | HAL_GFXMMU_ErrorCallback (GFXMMU_HandleTypeDef *hgfxmmu)
Error callback.

Detailed Description

GFXMMU operation functions.

  ==============================================================================
                      ##### Operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure LUT.
      (+) Force flush and/or invalidate of cache.
      (+) Modify physical buffer adresses.
      (+) Modify cache and pre-fetch parameters.
      (+) Manage error.

Function Documentation

HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | uint32_t | ForceParam
 | ) |  |

This function allows to force flush and/or invalidate of cache.

Parameters:
hgfxmmu | GFXMMU handle.
ForceParam | Force cache parameter. This parameter can be a values combination of GFXMMU cache force parameter.
Return values:
HAL status.

Definition at line 670 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_CACHE_FORCE_ACTION, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_ConfigLut | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | uint32_t | FirstLine,
 |  | uint32_t | LinesNumber,
 |  | uint32_t | Address
 | ) |  |

This function allows to copy LUT from flash to look up RAM.

Parameters:
hgfxmmu | GFXMMU handle.
FirstLine | First line enabled on LUT. This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
LinesNumber | Number of lines enabled on LUT. This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
Address | Start address of LUT in flash.
Return values:
HAL status.

Definition at line 521 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_LUT_LINE, IS_GFXMMU_LUT_LINES_NUMBER, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | GFXMMU_LutLineTypeDef * | lutLine
 | ) |  |

This function allows to configure one line of LUT.

Parameters:
hgfxmmu | GFXMMU handle.
lutLine | LUT line parameters.
Return values:
HAL status.

Definition at line 618 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, GFXMMU_LutLineTypeDef::FirstVisibleBlock, GFXMMU_LUT_LINE_ENABLE, GFXMMU_LUTXL_FVB_OFFSET, GFXMMU_LUTXL_LVB_OFFSET, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_LUT_BLOCK, IS_GFXMMU_LUT_LINE, IS_GFXMMU_LUT_LINE_OFFSET, IS_GFXMMU_LUT_LINE_STATUS, GFXMMU_LutLineTypeDef::LastVisibleBlock, GFXMMU_LutLineTypeDef::LineNumber, GFXMMU_LutLineTypeDef::LineOffset, GFXMMU_LutLineTypeDef::LineStatus, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | uint32_t | FirstLine,
 |  | uint32_t | LinesNumber
 | ) |  |

This function allows to disable a range of LUT lines.

Parameters:
hgfxmmu | GFXMMU handle.
FirstLine | First line to disable on LUT. This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
LinesNumber | Number of lines to disable on LUT. This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
Return values:
HAL status.

Definition at line 573 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_LUT_LINE, IS_GFXMMU_LUT_LINES_NUMBER, and __GFXMMU_HandleTypeDef::State.

void HAL_GFXMMU_ErrorCallback ( GFXMMU_HandleTypeDef * hgfxmmu )

Error callback.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
None.

Definition at line 811 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_Init(), HAL_GFXMMU_IRQHandler(), and HAL_GFXMMU_UnRegisterCallback().

void HAL_GFXMMU_IRQHandler ( GFXMMU_HandleTypeDef * hgfxmmu )

This function handles the GFXMMU interrupts.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
None.

Definition at line 780 of file stm32h7xx_hal_gfxmmu.c.

References __GFXMMU_HandleTypeDef::ErrorCallback, __GFXMMU_HandleTypeDef::ErrorCode, GFXMMU_CR_ITS_MASK, HAL_GFXMMU_ErrorCallback(), and __GFXMMU_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | GFXMMU_BuffersTypeDef * | Buffers
 | ) |  |

This function allows to modify physical buffer addresses.

Parameters:
hgfxmmu | GFXMMU handle.
Buffers | Buffers parameters.
Return values:
HAL status.

Definition at line 698 of file stm32h7xx_hal_gfxmmu.c.

References assert_param, GFXMMU_BuffersTypeDef::Buf0Address, GFXMMU_BuffersTypeDef::Buf1Address, GFXMMU_BuffersTypeDef::Buf2Address, GFXMMU_BuffersTypeDef::Buf3Address, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_BUFFER_ADDRESS, and __GFXMMU_HandleTypeDef::State.

HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch | ( | GFXMMU_HandleTypeDef * | hgfxmmu,
 |  | GFXMMU_CachePrefetchTypeDef * | CachePrefetch
 | ) |  |

This function allows to modify cache and pre-fetch parameters.

Parameters:
hgfxmmu | GFXMMU handle.
CachePrefetch | Cache and pre-fetch parameters.
Return values:
HAL status.

Definition at line 732 of file stm32h7xx_hal_gfxmmu.c.

References GFXMMU_CachePrefetchTypeDef::Activation, assert_param, GFXMMU_CachePrefetchTypeDef::CacheForce, GFXMMU_CachePrefetchTypeDef::CacheLock, GFXMMU_CachePrefetchTypeDef::CacheLockBuffer, GFXMMU_CACHE_LOCK_ENABLE, HAL_GFXMMU_STATE_READY, __GFXMMU_HandleTypeDef::Instance, IS_GFXMMU_CACHE_FORCE, IS_GFXMMU_CACHE_LOCK, IS_GFXMMU_CACHE_LOCK_BUFFER, IS_GFXMMU_OUTTER_BUFFERABILITY, IS_GFXMMU_OUTTER_CACHABILITY, IS_GFXMMU_PREFETCH, GFXMMU_CachePrefetchTypeDef::OutterBufferability, GFXMMU_CachePrefetchTypeDef::OutterCachability, GFXMMU_CachePrefetchTypeDef::Prefetch, and __GFXMMU_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: State functions

Functions
State functions
GFXMMU Exported Functions

GFXMMU state functions. More...

Functions

HAL_GFXMMU_StateTypeDef | HAL_GFXMMU_GetState (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU handle state.
uint32_t | HAL_GFXMMU_GetError (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU error code.

Detailed Description

GFXMMU state functions.

  ==============================================================================
                         ##### State functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Get GFXMMU handle state.
      (+) Get GFXMMU error code.

Function Documentation

uint32_t HAL_GFXMMU_GetError ( GFXMMU_HandleTypeDef * hgfxmmu )

This function allows to get the current GFXMMU error code.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
GFXMMU error code.

Definition at line 855 of file stm32h7xx_hal_gfxmmu.c.

References __GFXMMU_HandleTypeDef::ErrorCode, and GFXMMU_ERROR_NONE.

HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState ( GFXMMU_HandleTypeDef * hgfxmmu )

This function allows to get the current GFXMMU handle state.

Parameters:
hgfxmmu GFXMMU handle.
Return values:
GFXMMU state.

Definition at line 844 of file stm32h7xx_hal_gfxmmu.c.

References __GFXMMU_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU Exported Types

Data Structures | Typedefs | Enumerations
GFXMMU Exported Types
GFXMMU

Data Structures

struct | GFXMMU_BuffersTypeDef
GFXMMU buffers structure definition. More...
struct | GFXMMU_CachePrefetchTypeDef
GFXMMU cache and pre-fetch structure definition. More...
struct | GFXMMU_InterruptsTypeDef
GFXMMU interrupts structure definition. More...
struct | GFXMMU_InitTypeDef
GFXMMU init structure definition. More...
struct | __GFXMMU_HandleTypeDef
GFXMMU handle structure definition. More...
struct | GFXMMU_LutLineTypeDef
GFXMMU LUT line structure definition. More...

Typedefs

typedef struct
__GFXMMU_HandleTypeDef 		GFXMMU_HandleTypeDef
GFXMMU handle structure definition.
typedef void(* | pGFXMMU_CallbackTypeDef )(GFXMMU_HandleTypeDef *hgfxmmu)
GFXMMU callback pointer definition.

Enumerations

enum | HAL_GFXMMU_StateTypeDef { HAL_GFXMMU_STATE_RESET = 0x00U, HAL_GFXMMU_STATE_READY = 0x01U }
HAL GFXMMU states definition. More...
enum | HAL_GFXMMU_CallbackIDTypeDef { HAL_GFXMMU_ERROR_CB_ID = 0x00U, HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U }
GFXMMU callback ID enumeration definition. More...

Typedef Documentation

typedef struct __GFXMMU_HandleTypeDef GFXMMU_HandleTypeDef

GFXMMU handle structure definition.

typedef void(* pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu)

GFXMMU callback pointer definition.

Definition at line 166 of file stm32h7xx_hal_gfxmmu.h.

Enumeration Type Documentation

enum HAL_GFXMMU_CallbackIDTypeDef

GFXMMU callback ID enumeration definition.

Enumerator:
HAL_GFXMMU_ERROR_CB_ID

GFXMMU error callback ID

HAL_GFXMMU_MSPINIT_CB_ID

GFXMMU MSP init callback ID

HAL_GFXMMU_MSPDEINIT_CB_ID

GFXMMU MSP de-init callback ID

Definition at line 156 of file stm32h7xx_hal_gfxmmu.h.

enum HAL_GFXMMU_StateTypeDef

HAL GFXMMU states definition.

Enumerator:
HAL_GFXMMU_STATE_RESET

GFXMMU not initialized

HAL_GFXMMU_STATE_READY

GFXMMU initialized and ready for use

Definition at line 49 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU_BuffersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GFXMMU_BuffersTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU buffers structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

uint32_t | Buf0Address
uint32_t | Buf1Address
uint32_t | Buf2Address
uint32_t | Buf3Address

Detailed Description

GFXMMU buffers structure definition.

Definition at line 58 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

uint32_t GFXMMU_BuffersTypeDef::Buf0Address

Physical address of buffer 0.

Definition at line 60 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyBuffers().

uint32_t GFXMMU_BuffersTypeDef::Buf1Address

Physical address of buffer 1.

Definition at line 61 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyBuffers().

uint32_t GFXMMU_BuffersTypeDef::Buf2Address

Physical address of buffer 2.

Definition at line 62 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyBuffers().

uint32_t GFXMMU_BuffersTypeDef::Buf3Address

Physical address of buffer 3.

Definition at line 63 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyBuffers().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU_CachePrefetchTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GFXMMU_CachePrefetchTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU cache and pre-fetch structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

FunctionalState | Activation
uint32_t | CacheLock
uint32_t | CacheLockBuffer
uint32_t | CacheForce
uint32_t | OutterBufferability
uint32_t | OutterCachability
uint32_t | Prefetch

Detailed Description

GFXMMU cache and pre-fetch structure definition.

Definition at line 69 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

FunctionalState GFXMMU_CachePrefetchTypeDef::Activation

Cache and pre-fetch enable/disable.

Note:
: All following parameters are usefull only if cache and pre-fetch are enabled.

Definition at line 71 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::CacheForce

Forcing the cache regardless MPU attributes. This parameter can be a value of GFXMMU cache force.

Note:
: Usefull only when lock of the cache is enabled.

Definition at line 78 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::CacheLock

Locking the cache to a buffer. This parameter can be a value of GFXMMU cache lock.

Definition at line 73 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::CacheLockBuffer

Buffer on which the cache is locked. This parameter can be a value of GFXMMU cache lock buffer.

Note:
: Usefull only when lock of the cache is enabled.

Definition at line 75 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::OutterBufferability

Bufferability of an access generated by the GFXMMU cache. This parameter can be a value of GFXMMU outter bufferability.

Definition at line 81 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::OutterCachability

Cachability of an access generated by the GFXMMU cache. This parameter can be a value of GFXMMU outter cachability.

Definition at line 83 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

uint32_t GFXMMU_CachePrefetchTypeDef::Prefetch

Pre-fetch enable/disable. This parameter can be a value of GFXMMU pre-fetch.

Definition at line 85 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU_InterruptsTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GFXMMU_InterruptsTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU interrupts structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

FunctionalState | Activation
uint32_t | UsedInterrupts

Detailed Description

GFXMMU interrupts structure definition.

Definition at line 92 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

FunctionalState GFXMMU_InterruptsTypeDef::Activation

Interrupts enable/disable

Definition at line 94 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

uint32_t GFXMMU_InterruptsTypeDef::UsedInterrupts

Interrupts used. This parameter can be a values combination of GFXMMU interrupts.

Note:
: Usefull only when interrupts are enabled.

Definition at line 95 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GFXMMU_InitTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU init structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

uint32_t | BlocksPerLine
uint32_t | DefaultValue
GFXMMU_BuffersTypeDef Buffers
GFXMMU_CachePrefetchTypeDef CachePrefetch
GFXMMU_InterruptsTypeDef Interrupts

Detailed Description

GFXMMU init structure definition.

Definition at line 103 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

uint32_t GFXMMU_InitTypeDef::BlocksPerLine

Number of blocks of 16 bytes per line. This parameter can be a value of GFXMMU blocks per line.

Definition at line 105 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

GFXMMU_BuffersTypeDef GFXMMU_InitTypeDef::Buffers

Physical buffers addresses.

Definition at line 108 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

GFXMMU_CachePrefetchTypeDef GFXMMU_InitTypeDef::CachePrefetch

Cache and pre-fetch parameters.

Definition at line 109 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

uint32_t GFXMMU_InitTypeDef::DefaultValue

Value returned when virtual memory location not physically mapped.

Definition at line 107 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

GFXMMU_InterruptsTypeDef GFXMMU_InitTypeDef::Interrupts

Interrupts parameters.

Definition at line 110 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __GFXMMU_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__GFXMMU_HandleTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU handle structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

GFXMMU_TypeDef * | Instance
GFXMMU_InitTypeDef Init
HAL_GFXMMU_StateTypeDef State
__IO uint32_t | ErrorCode
void(* | ErrorCallback )(struct __GFXMMU_HandleTypeDef *hgfxmmu)
void(* | MspInitCallback )(struct __GFXMMU_HandleTypeDef *hgfxmmu)
void(* | MspDeInitCallback )(struct __GFXMMU_HandleTypeDef *hgfxmmu)

Detailed Description

GFXMMU handle structure definition.

Definition at line 117 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

void(* __GFXMMU_HandleTypeDef::ErrorCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu)

GFXMMU error callback

Definition at line 127 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), HAL_GFXMMU_IRQHandler(), HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

__IO uint32_t __GFXMMU_HandleTypeDef::ErrorCode

GFXMMU error code

Definition at line 125 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_GetError(), HAL_GFXMMU_Init(), HAL_GFXMMU_IRQHandler(), HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

GFXMMU_InitTypeDef __GFXMMU_HandleTypeDef::Init

GFXMMU init parameters

Definition at line 123 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

GFXMMU_TypeDef* __GFXMMU_HandleTypeDef::Instance

GFXMMU instance

Definition at line 122 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigForceCache(), HAL_GFXMMU_ConfigLut(), HAL_GFXMMU_ConfigLutLine(), HAL_GFXMMU_DeInit(), HAL_GFXMMU_DisableLutLines(), HAL_GFXMMU_Init(), HAL_GFXMMU_IRQHandler(), HAL_GFXMMU_ModifyBuffers(), and HAL_GFXMMU_ModifyCachePrefetch().

void(* __GFXMMU_HandleTypeDef::MspDeInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu)

GFXMMU MSP de-init callback

Definition at line 129 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_DeInit(), HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

void(* __GFXMMU_HandleTypeDef::MspInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu)

GFXMMU MSP init callback

Definition at line 128 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

HAL_GFXMMU_StateTypeDef __GFXMMU_HandleTypeDef::State

GFXMMU state

Definition at line 124 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigForceCache(), HAL_GFXMMU_ConfigLut(), HAL_GFXMMU_ConfigLutLine(), HAL_GFXMMU_DeInit(), HAL_GFXMMU_DisableLutLines(), HAL_GFXMMU_GetState(), HAL_GFXMMU_Init(), HAL_GFXMMU_ModifyBuffers(), HAL_GFXMMU_ModifyCachePrefetch(), HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU_LutLineTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GFXMMU_LutLineTypeDef Struct Reference
GFXMMU Exported Types

GFXMMU LUT line structure definition. More...

#include <stm32h7xx_hal_gfxmmu.h>

Data Fields

uint32_t | LineNumber
uint32_t | LineStatus
uint32_t | FirstVisibleBlock
uint32_t | LastVisibleBlock
int32_t | LineOffset

Detailed Description

GFXMMU LUT line structure definition.

Definition at line 136 of file stm32h7xx_hal_gfxmmu.h.

Field Documentation

uint32_t GFXMMU_LutLineTypeDef::FirstVisibleBlock

First visible block on this line. This parameter must be a number between Min_Data = 0 and Max_Data = 255.

Definition at line 142 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

uint32_t GFXMMU_LutLineTypeDef::LastVisibleBlock

Last visible block on this line. This parameter must be a number between Min_Data = 0 and Max_Data = 255.

Definition at line 144 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

uint32_t GFXMMU_LutLineTypeDef::LineNumber

LUT line number. This parameter must be a number between Min_Data = 0 and Max_Data = 1023.

Definition at line 138 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

int32_t GFXMMU_LutLineTypeDef::LineOffset

Offset of block 0 of the current line in physical buffer. This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.

Note:
: Line offset has to be computed with the following formula: LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize.

Definition at line 146 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

uint32_t GFXMMU_LutLineTypeDef::LineStatus

LUT line enable/disable. This parameter can be a value of GFXMMU LUT line status.

Definition at line 140 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gfxmmu.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU blocks per line

Defines
GFXMMU blocks per line
GFXMMU Exported Constants

Defines

#define | GFXMMU_256BLOCKS 0x00000000U
#define | GFXMMU_192BLOCKS GFXMMU_CR_192BM

Define Documentation

#define GFXMMU_192BLOCKS GFXMMU_CR_192BM

192 blocks of 16 bytes per line

Definition at line 183 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_256BLOCKS 0x00000000U

256 blocks of 16 bytes per line

Definition at line 182 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU cache lock

Defines
GFXMMU cache lock
GFXMMU Exported Constants

Defines

#define | GFXMMU_CACHE_LOCK_DISABLE 0x00000000U
#define | GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL

Define Documentation

#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U

Cache not locked to a buffer

Definition at line 191 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL

Cache locked to a buffer

Definition at line 192 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU cache lock buffer

Defines
GFXMMU cache lock buffer
GFXMMU Exported Constants

Defines

#define | GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U
#define | GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0
#define | GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1
#define | GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB

Define Documentation

#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U

Cache locked to buffer 0

Definition at line 200 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0

Cache locked to buffer 1

Definition at line 201 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1

Cache locked to buffer 2

Definition at line 202 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB

Cache locked to buffer 3

Definition at line 203 of file stm32h7xx_hal_gfxmmu.h.

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STM32H7B3xQ HAL User Manual: GFXMMU cache force

Defines
GFXMMU cache force
GFXMMU Exported Constants

Defines

#define | GFXMMU_CACHE_FORCE_DISABLE 0x00000000U
#define | GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC

Define Documentation

#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U

Caching not forced

Definition at line 211 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC

Caching forced

Definition at line 212 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU outter bufferability

Defines
GFXMMU outter bufferability
GFXMMU Exported Constants

Defines

#define | GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U
#define | GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB

Define Documentation

#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U

No bufferable

Definition at line 220 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB

Bufferable

Definition at line 221 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU outter cachability

Defines
GFXMMU outter cachability
GFXMMU Exported Constants

Defines

#define | GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U
#define | GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC

Define Documentation

#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U

No cachable

Definition at line 229 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC

Cachable

Definition at line 230 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU pre-fetch

Defines
GFXMMU pre-fetch
GFXMMU Exported Constants

Defines

#define | GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD
#define | GFXMMU_PREFETCH_ENABLE 0x00000000U

Define Documentation

#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD

Pre-fetch disable

Definition at line 238 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_PREFETCH_ENABLE 0x00000000U

Pre-fetch enable

Definition at line 239 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU interrupts

Defines
GFXMMU interrupts
GFXMMU Exported Constants

Defines

#define | GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE
#define | GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE
#define | GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE
#define | GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE
#define | GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE

Define Documentation

#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE

AHB master error interrupt

Definition at line 247 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE

Buffer 0 overflow interrupt

Definition at line 248 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE

Buffer 1 overflow interrupt

Definition at line 249 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE

Buffer 2 overflow interrupt

Definition at line 250 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE

Buffer 3 overflow interrupt

Definition at line 251 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU Error Code

Defines
GFXMMU Error Code
GFXMMU Exported Constants

Defines

#define | GFXMMU_ERROR_NONE 0x00000000U
#define | GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF
#define | GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF
#define | GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF
#define | GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF
#define | GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF
#define | GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U

Define Documentation

#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF

AHB master error

Definition at line 264 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF

Buffer 0 overflow

Definition at line 260 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF

Buffer 1 overflow

Definition at line 261 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF

Buffer 2 overflow

Definition at line 262 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF

Buffer 3 overflow

Definition at line 263 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U

Invalid callback error

Definition at line 266 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_RegisterCallback(), and HAL_GFXMMU_UnRegisterCallback().

#define GFXMMU_ERROR_NONE 0x00000000U

No error

Definition at line 259 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_GetError(), and HAL_GFXMMU_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU LUT line status

Defines
GFXMMU LUT line status
GFXMMU Exported Constants

Defines

#define | GFXMMU_LUT_LINE_DISABLE 0x00000000U
#define | GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN

Define Documentation

#define GFXMMU_LUT_LINE_DISABLE 0x00000000U

LUT line disabled

Definition at line 275 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN

LUT line enabled

Definition at line 276 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU cache force parameter

Defines
GFXMMU cache force parameter
GFXMMU Exported Constants

Defines

#define | GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF
#define | GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI

Define Documentation

#define GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF

Force cache flush

Definition at line 284 of file stm32h7xx_hal_gfxmmu.h.

#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI

Force cache invalidate

Definition at line 285 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU Exported Macros

Defines
GFXMMU Exported Macros
GFXMMU

Defines

#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__)
Reset GFXMMU handle state.

Define Documentation

#define __HAL_GFXMMU_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                               \
                                                        (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback = NULL;         \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;       \
                                                      } while(0)

Reset GFXMMU handle state.

Parameters:
__HANDLE__ GFXMMU handle.
Return values:
None

Definition at line 305 of file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU Private Macros

Defines
GFXMMU Private Macros
GFXMMU

Defines

#define | IS_GFXMMU_BLOCKS_PER_LINE(VALUE)
#define | IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
#define | IS_GFXMMU_CACHE_LOCK(VALUE)
#define | IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE)
#define | IS_GFXMMU_CACHE_FORCE(VALUE)
#define | IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE)
#define | IS_GFXMMU_OUTTER_CACHABILITY(VALUE)
#define | IS_GFXMMU_PREFETCH(VALUE)
#define | IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
#define | IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
#define | IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
#define | IS_GFXMMU_LUT_LINE_STATUS(VALUE)
#define | IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
#define | IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
#define | IS_GFXMMU_CACHE_FORCE_ACTION(VALUE)

Define Documentation

#define IS_GFXMMU_BLOCKS_PER_LINE ( VALUE )
Value:
(((VALUE) == GFXMMU_256BLOCKS) || \
                                          ((VALUE) == GFXMMU_192BLOCKS))

Definition at line 393 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

#define IS_GFXMMU_BUFFER_ADDRESS ( VALUE ) (((VALUE) & 0xFU) == 0U)

Definition at line 396 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyBuffers().

#define IS_GFXMMU_CACHE_FORCE ( VALUE )
Value:
(((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
                                      ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))

Definition at line 406 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

#define IS_GFXMMU_CACHE_FORCE_ACTION ( VALUE )
Value:
(((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
                                             ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
                                             ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))

Definition at line 431 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigForceCache().

#define IS_GFXMMU_CACHE_LOCK ( VALUE )
Value:
(((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
                                     ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))

Definition at line 398 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

#define IS_GFXMMU_CACHE_LOCK_BUFFER ( VALUE )
Value:
(((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))

Definition at line 401 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

#define IS_GFXMMU_INTERRUPTS ( VALUE ) (((VALUE) & 0x1FU) != 0U)

Definition at line 418 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init().

#define IS_GFXMMU_LUT_BLOCK ( VALUE ) ((VALUE) < 256U)

Definition at line 427 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

#define IS_GFXMMU_LUT_LINE ( VALUE ) ((VALUE) < 1024U)

Definition at line 420 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLut(), HAL_GFXMMU_ConfigLutLine(), and HAL_GFXMMU_DisableLutLines().

#define IS_GFXMMU_LUT_LINE_OFFSET ( VALUE ) (((VALUE) >= -4080) && ((VALUE) <= 4190208))

Definition at line 429 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

#define IS_GFXMMU_LUT_LINE_STATUS ( VALUE )
Value:
(((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
                                          ((VALUE) == GFXMMU_LUT_LINE_ENABLE))

Definition at line 424 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLutLine().

#define IS_GFXMMU_LUT_LINES_NUMBER ( VALUE ) (((VALUE) > 0U) && ((VALUE) <= 1024U))

Definition at line 422 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_ConfigLut(), and HAL_GFXMMU_DisableLutLines().

#define IS_GFXMMU_OUTTER_BUFFERABILITY ( VALUE )
Value:
(((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
                                               ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))

Definition at line 409 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

#define IS_GFXMMU_OUTTER_CACHABILITY ( VALUE )
Value:
(((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
                                             ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))

Definition at line 412 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

#define IS_GFXMMU_PREFETCH ( VALUE )
Value:
(((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
                                   ((VALUE) == GFXMMU_PREFETCH_ENABLE))

Definition at line 415 of file stm32h7xx_hal_gfxmmu.h.

Referenced by HAL_GFXMMU_Init(), and HAL_GFXMMU_ModifyCachePrefetch().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GFXMMU

Modules | Defines
GFXMMU
STM32H7xx_HAL_Driver

GFXMMU HAL driver module. More...

Modules

GFXMMU Exported Functions
GFXMMU Exported Types
GFXMMU Exported Constants
GFXMMU Exported Macros
GFXMMU Private Macros

Defines

#define | GFXMMU_LUTXL_FVB_OFFSET 8U
#define | GFXMMU_LUTXL_LVB_OFFSET 16U
#define | GFXMMU_CR_ITS_MASK 0x1FU

Detailed Description

GFXMMU HAL driver module.

Define Documentation

#define GFXMMU_CR_ITS_MASK 0x1FU

Definition at line 154 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_IRQHandler().

#define GFXMMU_LUTXL_FVB_OFFSET 8U

Definition at line 152 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_ConfigLutLine().

#define GFXMMU_LUTXL_LVB_OFFSET 16U

Definition at line 153 of file stm32h7xx_hal_gfxmmu.c.

Referenced by HAL_GFXMMU_ConfigLutLine().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 305 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 173 of file stm32h7xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read, Write, Toggle, Lock and EXTI management functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 532 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 509 of file stm32h7xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
GPIO_Pin,: specifies the port bit to be locked. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 474 of file stm32h7xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 392 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: Where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 448 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_NUMBER, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Sets or clears the selected data port bit.

Note:
This function uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 426 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_NUMBER, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 68 of file stm32h7xx_hal_gpio.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32h7xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 47 of file stm32h7xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins. This parameter can be a value of GPIO Alternate Function Selection

Definition at line 61 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode define

Definition at line 52 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins define

Definition at line 49 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull define

Definition at line 55 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed define

Definition at line 58 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gpio.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO pins define

Defines
GPIO pins define
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 86 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 87 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 96 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 97 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 98 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 99 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 100 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 101 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 88 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 89 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 90 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 91 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 92 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 93 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 94 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 95 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 102 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Definition at line 104 of file stm32h7xx_hal_gpio.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO mode define

Defines
GPIO mode define
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT (0x00000000U)
#define | GPIO_MODE_OUTPUT_PP (0x00000001U)
#define | GPIO_MODE_OUTPUT_OD (0x00000011U)
#define | GPIO_MODE_AF_PP (0x00000002U)
#define | GPIO_MODE_AF_OD (0x00000012U)
#define | GPIO_MODE_ANALOG (0x00000003U)
#define | GPIO_MODE_IT_RISING (0x11110000U)
#define | GPIO_MODE_IT_FALLING (0x11210000U)
#define | GPIO_MODE_IT_RISING_FALLING (0x11310000U)
#define | GPIO_MODE_EVT_RISING (0x11120000U)
#define | GPIO_MODE_EVT_FALLING (0x11220000U)
#define | GPIO_MODE_EVT_RISING_FALLING (0x11320000U)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD (0x00000012U)

Alternate Function Open Drain Mode

Definition at line 123 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP (0x00000002U)

Alternate Function Push Pull Mode

Definition at line 122 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG (0x00000003U)

Analog Mode

Definition at line 125 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING (0x11220000U)

External Event Mode with Falling edge trigger detection

Definition at line 132 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING (0x11120000U)

External Event Mode with Rising edge trigger detection

Definition at line 131 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 133 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_INPUT (0x00000000U)

Input Floating Mode

Definition at line 119 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING (0x11210000U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 128 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING (0x11110000U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 127 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING (0x11310000U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 129 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD (0x00000011U)

Output Open Drain Mode

Definition at line 121 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP (0x00000001U)

Output Push Pull Mode

Definition at line 120 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

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STM32H7B3xQ HAL User Manual: GPIO speed define

Defines
GPIO speed define
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH (0x00000002U)

Fast speed

Definition at line 144 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW (0x00000000U)

Low speed

Definition at line 142 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U)

Medium speed

Definition at line 143 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)

High speed

Definition at line 145 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

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STM32H7B3xQ HAL User Manual: GPIO pull define

Defines
GPIO pull define
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL (0x00000000U)

No Pull-up or Pull-down activation

Definition at line 154 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN (0x00000002U)

Pull-down activation

Definition at line 156 of file stm32h7xx_hal_gpio.h.

#define GPIO_PULLUP (0x00000001U)

Pull-up activation

Definition at line 155 of file stm32h7xx_hal_gpio.h.

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STM32H7B3xQ HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clears the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 184 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clears the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 200 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 242 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Checks whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 176 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Checks whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 192 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

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STM32H7B3xQ HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

Defines

#define | GPIO_MODE (0x00000003U)
#define | ANALOG_MODE (0x00000008U)
#define | EXTI_MODE (0x10000000U)
#define | GPIO_MODE_IT (0x00010000U)
#define | GPIO_MODE_EVT (0x00020000U)
#define | RISING_EDGE (0x00100000U)
#define | FALLING_EDGE (0x00200000U)
#define | GPIO_OUTPUT_TYPE (0x00000010U)
#define | GPIO_NUMBER (16U)

Define Documentation

#define ANALOG_MODE (0x00000008U)

Definition at line 126 of file stm32h7xx_hal_gpio.c.

#define EXTI_MODE (0x10000000U)

Definition at line 127 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE (0x00200000U)

Definition at line 131 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE (0x00000003U)

Definition at line 125 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT (0x00020000U)

Definition at line 129 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT (0x00010000U)

Definition at line 128 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER (16U)

Definition at line 138 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define GPIO_OUTPUT_TYPE (0x00000010U)

Definition at line 132 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE (0x00100000U)

Definition at line 130 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

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STM32H7B3xQ HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_MODE_INPUT)              ||\
                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
                            ((MODE) == GPIO_MODE_AF_PP)              ||\
                            ((MODE) == GPIO_MODE_AF_OD)              ||\
                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
                            ((MODE) == GPIO_MODE_ANALOG))

Definition at line 301 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ )
Value:
((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
                                    (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))

Definition at line 299 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 298 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( PULL )
Value:
(((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                            ((PULL) == GPIO_PULLDOWN))

Definition at line 316 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 313 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

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STM32H7B3xQ HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIO
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STM32H7B3xQ HAL User Manual: HASH Digest Calculation Status

Defines
HASH Digest Calculation Status
HASH Private Constants

Defines

#define | HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U)
#define | HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U)

Define Documentation

#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U)

DCAL not set after input data written in DIN register

Definition at line 191 of file stm32h7xx_hal_hash.c.

Referenced by HASH_Write_Block_Data().

#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U)

DCAL set after input data written in DIN register

Definition at line 192 of file stm32h7xx_hal_hash.c.

Referenced by HASH_IT(), and HASH_Write_Block_Data().

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STM32H7B3xQ HAL User Manual: HASH Number of Context Swap Registers

Defines
HASH Number of Context Swap Registers
HASH Private Constants

Defines

#define HASH_NUMBER_OF_CSR_REGISTERS 54U

Define Documentation

#define HASH_NUMBER_OF_CSR_REGISTERS 54U

Number of Context Swap Registers

Definition at line 200 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_ContextRestoring(), and HAL_HASH_ContextSaving().

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STM32H7B3xQ HAL User Manual: HASH TimeOut Value

Defines
HASH TimeOut Value
HASH Private Constants

Defines

#define HASH_TIMEOUTVALUE 1000U

Define Documentation

#define HASH_TIMEOUTVALUE 1000U

Time-out value

Definition at line 208 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_IT(), and HASH_WriteData().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH DMA suspension words limit

Defines
HASH DMA suspension words limit
HASH Private Constants

Defines

#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U

Define Documentation

#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U

Number of words below which DMA suspension is aborted

Definition at line 216 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend().

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STM32H7B3xQ HAL User Manual: HASH Private Functions

Functions
HASH Private Functions
HASH

Functions

static void | HASH_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA HASH Input Data transfer completion callback.
static void | HASH_DMAError (DMA_HandleTypeDef *hdma)
DMA HASH communication error callback.
static void | HASH_GetDigest (uint8_t *pMsgDigest, uint8_t Size)
Retrieve the message digest.
static HAL_StatusTypeDef | HASH_WaitOnFlagUntilTimeout (HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle HASH processing Timeout.
static HAL_StatusTypeDef | HASH_WriteData (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Feed the input buffer to the HASH IP.
static HAL_StatusTypeDef | HASH_IT (HASH_HandleTypeDef *hhash)
HASH processing in interruption mode.
static uint32_t | HASH_Write_Block_Data (HASH_HandleTypeDef *hhash)
Write a block of data in HASH IP in interruption mode.
static HAL_StatusTypeDef | HMAC_Processing (HASH_HandleTypeDef *hhash, uint32_t Timeout)
HMAC processing in polling mode.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Function Documentation

HAL_StatusTypeDef HASH_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

If not already done, initialize the HASH peripheral then processes pInBuffer.

Note:
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2374 of file stm32h7xx_hal_hash.c.

References assert_param, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_WriteData(), __HASH_HandleTypeDef::HashInCount, IS_HASH_POLLING_MULTIBUFFER_SIZE, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_MD5_Accumulate(), HAL_HASH_SHA1_Accumulate(), HAL_HASHEx_SHA224_Accumulate(), and HAL_HASHEx_SHA256_Accumulate().

static void HASH_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA HASH communication error callback.

Parameters:
hdma,: DMA handle.
Note:
HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that can contain user code to manage the error.
Return values:
None

Definition at line 1613 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::ErrorCallback, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_ERROR_DMA, HAL_HASH_ErrorCallback(), HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

Referenced by HASH_Start_DMA(), and HMAC_Start_DMA().

static void HASH_DMAXferCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA HASH Input Data transfer completion callback.

Parameters:
hdma,: DMA handle.
Note:
In case of HMAC processing, HASH_DMAXferCplt() initiates the next DMA transfer for the following HMAC step.
Return values:
None

Definition at line 1473 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_MDMAT, __HAL_HASH_SET_NBVALIDBITS, __HASH_HandleTypeDef::DigestCalculationDisable, HAL_DMA_Start_IT(), HAL_HASH_InCpltCallback(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_ERROR, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::hdmain, __HASH_HandleTypeDef::InCpltCallback, __HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::NbWordsAlreadyPushed, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_InitTypeDef::pKey, __HASH_HandleTypeDef::State, and __DMA_HandleTypeDef::XferCpltCallback.

Referenced by HASH_Start_DMA(), and HMAC_Start_DMA().

HAL_StatusTypeDef HASH_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest.

Note:
The API waits for DCIS to be set then reads the computed digest.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 2671 of file stm32h7xx_hal_hash.c.

References HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HASH_DIGEST_LENGTH, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), and __HASH_HandleTypeDef::State.

Referenced by HAL_HASH_MD5_Finish(), HAL_HASH_SHA1_Finish(), HAL_HASHEx_SHA224_Finish(), and HAL_HASHEx_SHA256_Finish().

static void HASH_GetDigest | ( | uint8_t * | pMsgDigest,
 |  | uint8_t | Size
 | ) |  | [static]

Retrieve the message digest.

Parameters:
pMsgDigest,: pointer to the computed digest.
Size,: message digest size in bytes.
Return values:
None

Definition at line 1719 of file stm32h7xx_hal_hash.c.

Referenced by HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

static HAL_StatusTypeDef HASH_IT ( HASH_HandleTypeDef * hhash ) [static]

HASH processing in interruption mode.

Parameters:
hhash,: HASH handle.
Note:
HASH_IT() regularly reads hhash->SuspendRequest to check whether or not the HASH processing must be suspended. If this is the case, the processing is suspended when possible and the IP feeding point reached at suspension time is stored in the handle for resumption later on.
Return values:
HAL status

Definition at line 1855 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_DISABLE_IT, __HAL_HASH_ENABLE_IT, __HAL_HASH_GET_FLAG, __HAL_HASH_SET_NBVALIDBITS, __HASH_HandleTypeDef::DgstCpltCallback, HAL_HASH_DgstCpltCallback(), HAL_HASH_InCpltCallback(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HAL_HASH_SUSPEND, HAL_HASH_SUSPEND_NONE, HASH_DIGEST_CALCULATION_STARTED, HASH_DIGEST_LENGTH, HASH_FLAG_BUSY, HASH_FLAG_DCIS, HASH_FLAG_DINIS, HASH_GetDigest(), HASH_IT_DCI, HASH_IT_DINI, HASH_TIMEOUTVALUE, HASH_WaitOnFlagUntilTimeout(), HASH_Write_Block_Data(), __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, __HASH_HandleTypeDef::InCpltCallback, __HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashMsgBuffPtr, __HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::SuspendRequest.

Referenced by HAL_HASH_IRQHandler().

HAL_StatusTypeDef HASH_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2241 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, __HAL_HASH_START_DIGEST, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DIGEST_LENGTH, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_MD5_Start(), HAL_HASH_SHA1_Start(), HAL_HASHEx_SHA224_Start(), and HAL_HASHEx_SHA256_Start().

HAL_StatusTypeDef HASH_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.

Note:
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2552 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, assert_param, HAL_DMA_Start_IT(), HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_ERROR, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DMAError(), HASH_DMAXferCplt(), HASH_NBW_PUSHED, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::hdmain, IS_HASH_DMA_MULTIBUFFER_SIZE, IS_HASH_PROCESSING, __HASH_HandleTypeDef::NbWordsAlreadyPushed, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_HASH_MD5_Start_DMA(), HAL_HASH_SHA1_Start_DMA(), HAL_HASHEx_SHA224_Start_DMA(), and HAL_HASHEx_SHA256_Start_DMA().

HAL_StatusTypeDef HASH_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2472 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_ENABLE_IT, __HAL_HASH_SET_NBVALIDBITS, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_IT_DCI, HASH_IT_DINI, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashOutBuffPtr, and __HASH_HandleTypeDef::State.

Referenced by HAL_HASH_MD5_Start_IT(), HAL_HASH_SHA1_Start_IT(), HAL_HASHEx_SHA224_Start_IT(), and HAL_HASHEx_SHA256_Start_IT().

static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout | ( | HASH_HandleTypeDef * | hhash,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle HASH processing Timeout.

Parameters:
hhash,: HASH handle.
Flag,: specifies the HASH flag to check.
Status,: the Flag status (SET or RESET).
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1793 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_GET_FLAG, HAL_GetTick(), HAL_HASH_STATE_READY, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Finish(), HASH_IT(), HASH_Start(), HASH_WriteData(), and HMAC_Processing().

static uint32_t HASH_Write_Block_Data ( HASH_HandleTypeDef * hhash ) [static]

Write a block of data in HASH IP in interruption mode.

Parameters:
hhash,: HASH handle.
Note:
HASH_Write_Block_Data() is called under interruption by HASH_IT().
Return values:
HAL status

Definition at line 1992 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_DISABLE_IT, __HAL_HASH_START_DIGEST, HASH_DIGEST_CALCULATION_NOT_STARTED, HASH_DIGEST_CALCULATION_STARTED, HASH_IT_DINI, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, and __HASH_HandleTypeDef::pHashInBuffPtr.

Referenced by HASH_IT().

static HAL_StatusTypeDef HASH_WriteData | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  | [static]

Feed the input buffer to the HASH IP.

Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to input buffer.
Size,: the size of input buffer in bytes.
Note:
HASH_WriteData() regularly reads hhash->SuspendRequest to check whether or not the HASH processing must be suspended. If this is the case, the processing is suspended when possible and the IP feeding point reached at suspension time is stored in the handle for resumption later on.
Return values:
HAL status

Definition at line 1647 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_GET_FLAG, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_PHASE_PROCESS, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HAL_HASH_SUSPEND, HAL_HASH_SUSPEND_NONE, HASH_FLAG_BUSY, HASH_FLAG_DINIS, HASH_TIMEOUTVALUE, HASH_WaitOnFlagUntilTimeout(), __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashKeyCount, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashKeyBuffPtr, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::SuspendRequest.

Referenced by HASH_Accumulate(), HASH_Start(), and HMAC_Processing().

static HAL_StatusTypeDef HMAC_Processing | ( | HASH_HandleTypeDef * | hhash,
 |  | uint32_t | Timeout
 | ) |  | [static]

HMAC processing in polling mode.

Parameters:
hhash,: HASH handle.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 2077 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, __HAL_HASH_START_DIGEST, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DIGEST_LENGTH, HASH_FLAG_BUSY, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashKeyCount, __HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashKeyBuffPtr, __HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

Referenced by HMAC_Start().

HAL_StatusTypeDef HMAC_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2729 of file stm32h7xx_hal_hash.c.

References HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_HMAC_KEYTYPE_LONGKEY, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashKeyCount, HMAC_Processing(), __HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashKeyBuffPtr, __HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, and __HASH_HandleTypeDef::State.

Referenced by HAL_HMAC_MD5_Start(), HAL_HMAC_SHA1_Start(), HAL_HMACEx_SHA224_Start(), and HAL_HMACEx_SHA256_Start().

HAL_StatusTypeDef HMAC_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
In case of multi-buffer HMAC processing, the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only the length of the last buffer of the thread doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2906 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_RESET_MDMAT, __HAL_HASH_SET_NBVALIDBITS, assert_param, __HASH_HandleTypeDef::DigestCalculationDisable, HAL_DMA_Start_IT(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_ERROR, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_DMAError(), HASH_DMAXferCplt(), HASH_HMAC_KEYTYPE_LONGKEY, HASH_NBW_PUSHED, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::hdmain, __HASH_HandleTypeDef::Init, IS_HMAC_DMA_MULTIBUFFER_SIZE, IS_HMAC_PROCESSING, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::NbWordsAlreadyPushed, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashKeyBuffPtr, __HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_InitTypeDef::pKey, __HASH_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_HMAC_MD5_Start_DMA(), HAL_HMAC_SHA1_Start_DMA(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), HAL_HMACEx_MD5_Step2_DMA(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), HAL_HMACEx_SHA1_Step2_DMA(), HAL_HMACEx_SHA224_Start_DMA(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), HAL_HMACEx_SHA224_Step2_DMA(), HAL_HMACEx_SHA256_Start_DMA(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), and HAL_HMACEx_SHA256_Step2_DMA().

HAL_StatusTypeDef HMAC_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2799 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_ENABLE_IT, __HAL_HASH_SET_NBVALIDBITS, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_HMAC_KEYTYPE_LONGKEY, HASH_IT_DCI, HASH_IT_DINI, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, __HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::pHashInBuffPtr, __HASH_HandleTypeDef::pHashKeyBuffPtr, __HASH_HandleTypeDef::pHashMsgBuffPtr, __HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, and __HASH_HandleTypeDef::State.

Referenced by HAL_HMAC_MD5_Start_IT(), HAL_HMAC_SHA1_Start_IT(), HAL_HMACEx_SHA224_Start_IT(), and HAL_HMACEx_SHA256_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HASH Exported Functions

Initialization, configuration and call-back functions. More...

Functions

HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.
HAL_StatusTypeDef | HAL_HASH_RegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
Register a User HASH Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_HASH_UnRegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
Unregister a HASH Callback HASH Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization, configuration and call-back functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the HASH according to the specified parameters
          in the HASH_InitTypeDef and create the associated handle
      (+) DeInitialize the HASH peripheral
      (+) Initialize the HASH MCU Specific Package (MSP)
      (+) DeInitialize the HASH MSP

    [..]  This section provides as well call back functions definitions for user
          code to manage:
      (+) Input data transfer to IP completion
      (+) Calculated digest retrieval completion
      (+) Error management

Function Documentation

HAL_StatusTypeDef HAL_HASH_DeInit ( HASH_HandleTypeDef * hhash )

DeInitialize the HASH peripheral.

Parameters:
hhash,: HASH handle.
Return values:
HAL status

Definition at line 360 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_ERROR_NONE, HAL_HASH_MspDeInit(), HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_RESET, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, __HASH_HandleTypeDef::MspDeInitCallback, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

void HAL_HASH_DgstCpltCallback ( HASH_HandleTypeDef * hhash )

Digest computation complete call back.

Note:
HAL_HASH_DgstCpltCallback() is used under interruption, is not relevant with DMA.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 466 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_Init(), HAL_HASH_UnRegisterCallback(), and HASH_IT().

void HAL_HASH_ErrorCallback ( HASH_HandleTypeDef * hhash )

Error callback.

Note:
Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) to retrieve the error type.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 483 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_Init(), HAL_HASH_IRQHandler(), HAL_HASH_UnRegisterCallback(), and HASH_DMAError().

void HAL_HASH_InCpltCallback ( HASH_HandleTypeDef * hhash )

Input data transfer complete call back.

Note:
HAL_HASH_InCpltCallback() is called when the complete input message has been fed to the IP. This API is invoked only when input data are entered under interruption or thru DMA.
In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), HAL_HASH_InCpltCallback() is called at the end of each buffer feeding to the IP.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 449 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_Init(), HAL_HASH_UnRegisterCallback(), HASH_DMAXferCplt(), and HASH_IT().

HAL_StatusTypeDef HAL_HASH_Init ( HASH_HandleTypeDef * hhash )

Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.

Note:
Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(), other configuration bits are set by HASH or HMAC processing APIs.
MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for multi-buffer HASH processing, user needs to resort to __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the relevant APIs manage themselves the MDMAT bit.
Parameters:
hhash,: HASH handle
Return values:
HAL status

Definition at line 285 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_RESET_MDMAT, assert_param, HASH_InitTypeDef::DataType, __HASH_HandleTypeDef::DgstCpltCallback, __HASH_HandleTypeDef::DigestCalculationDisable, __HASH_HandleTypeDef::ErrorCallback, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_DgstCpltCallback(), HAL_HASH_ERROR_NONE, HAL_HASH_ErrorCallback(), HAL_HASH_InCpltCallback(), HAL_HASH_MspInit(), HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_RESET, __HASH_HandleTypeDef::HashBuffSize, __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::HashITCounter, __HASH_HandleTypeDef::InCpltCallback, __HASH_HandleTypeDef::Init, IS_HASH_DATATYPE, __HASH_HandleTypeDef::Lock, __HASH_HandleTypeDef::MspInitCallback, __HASH_HandleTypeDef::NbWordsAlreadyPushed, __HASH_HandleTypeDef::Phase, __HASH_HandleTypeDef::State, and __HASH_HandleTypeDef::Status.

void HAL_HASH_MspDeInit ( HASH_HandleTypeDef * hhash )

DeInitialize the HASH MSP.

Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 428 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_DeInit(), and HAL_HASH_UnRegisterCallback().

void HAL_HASH_MspInit ( HASH_HandleTypeDef * hhash )

Initialize the HASH MSP.

Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 413 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_Init(), and HAL_HASH_UnRegisterCallback().

HAL_StatusTypeDef HAL_HASH_RegisterCallback | ( | HASH_HandleTypeDef * | hhash,
 |  | HAL_HASH_CallbackIDTypeDef | CallbackID,
 |  | pHASH_CallbackTypeDef | pCallback
 | ) |  |

Register a User HASH Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hhash | HASH handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
  • HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
  • HAL_HASH_ERROR_CB_ID HASH error Callback ID
  • HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
  • HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 508 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::DgstCpltCallback, __HASH_HandleTypeDef::ErrorCallback, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_DGSTCPLT_CB_ID, HAL_HASH_ERROR_CB_ID, HAL_HASH_ERROR_INVALID_CALLBACK, HAL_HASH_INPUTCPLT_CB_ID, HAL_HASH_MSPDEINIT_CB_ID, HAL_HASH_MSPINIT_CB_ID, HAL_HASH_STATE_READY, HAL_HASH_STATE_RESET, __HASH_HandleTypeDef::InCpltCallback, __HASH_HandleTypeDef::MspDeInitCallback, __HASH_HandleTypeDef::MspInitCallback, and __HASH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HASH_UnRegisterCallback | ( | HASH_HandleTypeDef * | hhash,
 |  | HAL_HASH_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a HASH Callback HASH Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hhash HASH handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
  • HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
  • HAL_HASH_ERROR_CB_ID HASH error Callback ID
  • HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
  • HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
Return values:
status

Definition at line 599 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::DgstCpltCallback, __HASH_HandleTypeDef::ErrorCallback, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_DGSTCPLT_CB_ID, HAL_HASH_DgstCpltCallback(), HAL_HASH_ERROR_CB_ID, HAL_HASH_ERROR_INVALID_CALLBACK, HAL_HASH_ErrorCallback(), HAL_HASH_InCpltCallback(), HAL_HASH_INPUTCPLT_CB_ID, HAL_HASH_MspDeInit(), HAL_HASH_MSPDEINIT_CB_ID, HAL_HASH_MspInit(), HAL_HASH_MSPINIT_CB_ID, HAL_HASH_STATE_READY, HAL_HASH_STATE_RESET, __HASH_HandleTypeDef::InCpltCallback, __HASH_HandleTypeDef::MspDeInitCallback, __HASH_HandleTypeDef::MspInitCallback, and __HASH_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH processing functions in polling mode

Functions
HASH processing functions in polling mode
HASH Exported Functions

HASH processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.

Detailed Description

HASH processing functions using polling mode.

 ===============================================================================
                 ##### Polling mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start()
         (++) HAL_HASH_MD5_Accumulate()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start()
         (++) HAL_HASH_SHA1_Accumulate()

    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().

    [..]  In case of multi-buffer HASH processing (a single digest is computed while
          several buffers are fed to the IP), the user can resort to successive calls
          to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
          to HAL_HASH_xxx_Start().

Function Documentation

HAL_StatusTypeDef HAL_HASH_MD5_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_MD5_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 739 of file stm32h7xx_hal_hash.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_MD5.

HAL_StatusTypeDef HAL_HASH_MD5_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 714 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start().

HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_SHA1_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 780 of file stm32h7xx_hal_hash.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA1.

HAL_StatusTypeDef HAL_HASH_SHA1_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 755 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH processing functions in interrupt mode

Functions
HASH processing functions in interrupt mode
HASH Exported Functions

HASH processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.

Detailed Description

HASH processing functions using interrupt mode.

 ===============================================================================
                 ##### Interruption mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start_IT()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start_IT()

    [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.

    [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
         HMAC processing mode.

Function Documentation

void HAL_HASH_IRQHandler ( HASH_HandleTypeDef * hhash )

Handle HASH interrupt request.

Parameters:
hhash,: HASH handle.
Note:
HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
In case of error reported during the HASH interruption processing, HAL_HASH_ErrorCallback() API is called so that user code can manage the error. The error type is available in hhash->Status field.
Return values:
None

Definition at line 854 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::ErrorCallback, __HASH_HandleTypeDef::ErrorCode, HAL_HASH_ERROR_IT, HAL_HASH_ErrorCallback(), HASH_IT(), and __HASH_HandleTypeDef::Status.

HAL_StatusTypeDef HAL_HASH_MD5_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Return values:
HAL status

Definition at line 824 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start_IT().

HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Return values:
HAL status

Definition at line 840 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH processing functions in DMA mode

Functions
HASH processing functions in DMA mode
HASH Exported Functions

HASH processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.

Detailed Description

HASH processing functions using DMA mode.

 ===============================================================================
                    ##### DMA mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start_DMA()
         (++) HAL_HASH_MD5_Finish()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start_DMA()
         (++) HAL_HASH_SHA1_Finish()

    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
          to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
          HAL_HASH_xxx_Finish().
    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
          the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
          reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
          retrieved thanks to HAL_HASH_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HASH_MD5_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in MD5 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in HMAC MD5 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 927 of file stm32h7xx_hal_hash.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 912 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start_DMA().

HAL_StatusTypeDef HAL_HASH_SHA1_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA1 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in HMAC SHA1 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 958 of file stm32h7xx_hal_hash.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 942 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC processing functions in polling mode

Functions
HMAC processing functions in polling mode
HASH Exported Functions

HMAC processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.

Detailed Description

HMAC processing functions using polling mode.

 ===============================================================================
                 ##### Polling mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start()

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 999 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 1017 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC processing functions in interrupt mode

Functions
HMAC processing functions in interrupt mode
HASH Exported Functions

HMAC processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.

Detailed Description

HMAC processing functions using interrupt mode.

 ===============================================================================
                 ##### Interrupt mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start_IT()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Return values:
HAL status

Definition at line 1058 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start_IT().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Return values:
HAL status

Definition at line 1075 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC processing functions in DMA mode

Functions
HMAC processing functions in DMA mode
HASH Exported Functions

HMAC processing functions using DMA modes. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HMAC processing functions using DMA modes.

 ===============================================================================
                 ##### DMA mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start_DMA()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start_DMA()

    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
          user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
          with HAL_HASH_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 1128 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 1153 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral states functions

Functions
Peripheral states functions
HASH Exported Functions

Peripheral State functions. More...

Functions

HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.
uint32_t | HAL_HASH_GetError (HASH_HandleTypeDef *hhash)
Return the HASH handle error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State methods #####
 ===============================================================================
    [..]
    This section permits to get in run-time the state and the peripheral handle
    status of the peripheral:
      (+) HAL_HASH_GetState()
      (+) HAL_HASH_GetStatus()

    [..]
    Additionally, this subsection provides functions allowing to save and restore
    the HASH or HMAC processing context in case of calculation suspension:
      (+) HAL_HASH_ContextSaving()
      (+) HAL_HASH_ContextRestoring()

    [..]
    This subsection provides functions allowing to suspend the HASH processing
      (+) when input are fed to the IP by software
          (++) HAL_HASH_SwFeed_ProcessSuspend()
      (+) when input are fed to the IP by DMA
          (++) HAL_HASH_DMAFeed_ProcessSuspend()

Function Documentation

void HAL_HASH_ContextRestoring | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pMemBuffer
 | ) |  |

Restore the HASH context in case of processing resumption.

Parameters:
hhash,: HASH handle.
pMemBuffer,: pointer to the memory buffer where the HASH context is stored.
Note:
The IMR, STR, CR then all the CSR registers are restored in that order. Only the r/w bits are restored.
By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS of those) are restored (all of them have been saved by default beforehand).
Return values:
None

Definition at line 1271 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_INIT, and HASH_NUMBER_OF_CSR_REGISTERS.

void HAL_HASH_ContextSaving | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pMemBuffer
 | ) |  |

Save the HASH context in case of processing suspension.

Parameters:
hhash,: HASH handle.
pMemBuffer,: pointer to the memory buffer where the HASH context is saved.
Note:
The IMR, STR, CR then all the CSR registers are saved in that order. Only the r/w bits are read to be restored later on.
By default, all the context swap registers (there are HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
pMemBuffer points to a buffer allocated by the user. The buffer size must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
Return values:
None

Definition at line 1231 of file stm32h7xx_hal_hash.c.

References HASH_IT_DCI, HASH_IT_DINI, and HASH_NUMBER_OF_CSR_REGISTERS.

HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend ( HASH_HandleTypeDef * hhash )

Suspend the HASH processing when in DMA mode.

Parameters:
hhash,: HASH handle.
Note:
When suspension attempt occurs at the very end of a DMA transfer and all the data have already been entered in the IP, hhash->State is set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is recommended to wrap-up the processing in reading the digest as usual.
Return values:
HAL status

Definition at line 1329 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_GET_FLAG, HAL_DMA_Abort(), HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DMA_SUSPENSION_WORDS_LIMIT, HASH_FLAG_BUSY, HASH_FLAG_DCIS, HASH_NBW_PUSHED, HASH_TIMEOUTVALUE, HASH_WaitOnFlagUntilTimeout(), __HASH_HandleTypeDef::HashInCount, __HASH_HandleTypeDef::hdmain, __DMA_HandleTypeDef::Instance, __HASH_HandleTypeDef::NbWordsAlreadyPushed, __HASH_HandleTypeDef::pHashInBuffPtr, and __HASH_HandleTypeDef::State.

uint32_t HAL_HASH_GetError ( HASH_HandleTypeDef * hhash )

Return the HASH handle error code.

Parameters:
hhash,: pointer to a HASH_HandleTypeDef structure.
Return values:
HASH Error Code

Definition at line 1448 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::ErrorCode.

HAL_HASH_StateTypeDef HAL_HASH_GetState ( HASH_HandleTypeDef * hhash )

Return the HASH handle state.

Note:
The API yields the current state of the handle (BUSY, READY,...).
Parameters:
hhash,: HASH handle.
Return values:
HAL HASH state

Definition at line 1200 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HASH_GetStatus ( HASH_HandleTypeDef * hhash )

Return the HASH HAL status.

Note:
The API yields the HAL status of the handle: it is the result of the latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
Parameters:
hhash,: HASH handle.
Return values:
HAL status

Definition at line 1213 of file stm32h7xx_hal_hash.c.

References __HASH_HandleTypeDef::Status.

void HAL_HASH_SwFeed_ProcessSuspend ( HASH_HandleTypeDef * hhash )

Initiate HASH processing suspension when in polling or interruption mode.

Parameters:
hhash,: HASH handle.
Note:
Set the handle field SuspendRequest to the appropriate value so that the on-going HASH processing is suspended as soon as the required conditions are met. Note that the actual suspension is carried out by the functions HASH_WriteData() in polling mode and HASH_IT() in interruption mode.
Return values:
None

Definition at line 1314 of file stm32h7xx_hal_hash.c.

References HAL_HASH_SUSPEND, and __HASH_HandleTypeDef::SuspendRequest.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH Exported Types

Data Structures | Typedefs | Enumerations
HASH Exported Types
HASH

Data Structures

struct | HASH_InitTypeDef
HASH Configuration Structure definition. More...
struct | __HASH_HandleTypeDef
HASH Handle Structure definition. More...

Typedefs

typedef struct __HASH_HandleTypeDef | HASH_HandleTypeDef
HASH Handle Structure definition.
typedef void(* | pHASH_CallbackTypeDef )(HASH_HandleTypeDef *hhash)
HAL HASH Callback pointer definition.

Enumerations

enum HAL_HASH_StateTypeDef {
HAL_HASH_STATE_RESET = 0x00U, HAL_HASH_STATE_READY = 0x01U, HAL_HASH_STATE_BUSY = 0x02U, HAL_HASH_STATE_TIMEOUT = 0x06U,
HAL_HASH_STATE_ERROR = 0x07U, HAL_HASH_STATE_SUSPENDED = 0x08U
}
HAL State structures definition. More...
enum HAL_HASH_PhaseTypeDef {
HAL_HASH_PHASE_READY = 0x01U, HAL_HASH_PHASE_PROCESS = 0x02U, HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U,
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U
}
HAL phase structures definition. More...
enum | HAL_HASH_SuspendTypeDef { HAL_HASH_SUSPEND_NONE = 0x00U, HAL_HASH_SUSPEND = 0x01U }
HAL HASH mode suspend definitions. More...
enum HAL_HASH_CallbackIDTypeDef {
HAL_HASH_MSPINIT_CB_ID = 0x00U, HAL_HASH_MSPDEINIT_CB_ID = 0x01U, HAL_HASH_INPUTCPLT_CB_ID = 0x02U, HAL_HASH_DGSTCPLT_CB_ID = 0x03U,
HAL_HASH_ERROR_CB_ID = 0x04U
}
HAL HASH common Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __HASH_HandleTypeDef HASH_HandleTypeDef

HASH Handle Structure definition.

typedef void(* pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash)

HAL HASH Callback pointer definition.

pointer to a HASH common callback functions

Definition at line 173 of file stm32h7xx_hal_hash.h.

Enumeration Type Documentation

enum HAL_HASH_CallbackIDTypeDef

HAL HASH common Callback ID enumeration definition.

Enumerator:
HAL_HASH_MSPINIT_CB_ID

HASH MspInit callback ID

HAL_HASH_MSPDEINIT_CB_ID

HASH MspDeInit callback ID

HAL_HASH_INPUTCPLT_CB_ID

HASH input completion callback ID

HAL_HASH_DGSTCPLT_CB_ID

HASH digest computation completion callback ID

HAL_HASH_ERROR_CB_ID

HASH error callback ID

Definition at line 99 of file stm32h7xx_hal_hash.h.

enum HAL_HASH_PhaseTypeDef

HAL phase structures definition.

Enumerator:
HAL_HASH_PHASE_READY

HASH peripheral is ready to start

HAL_HASH_PHASE_PROCESS

HASH peripheral is in HASH processing phase

HAL_HASH_PHASE_HMAC_STEP_1

HASH peripheral is in HMAC step 1 processing phase (step 1 consists in entering the inner hash function key)

HAL_HASH_PHASE_HMAC_STEP_2

HASH peripheral is in HMAC step 2 processing phase (step 2 consists in entering the message text)

HAL_HASH_PHASE_HMAC_STEP_3

HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key)

Definition at line 74 of file stm32h7xx_hal_hash.h.

enum HAL_HASH_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_HASH_STATE_RESET

Peripheral is not initialized

HAL_HASH_STATE_READY

Peripheral Initialized and ready for use

HAL_HASH_STATE_BUSY

Processing (hashing) is ongoing

HAL_HASH_STATE_TIMEOUT

Timeout state

HAL_HASH_STATE_ERROR

Error state

HAL_HASH_STATE_SUSPENDED

Suspended state

Definition at line 61 of file stm32h7xx_hal_hash.h.

enum HAL_HASH_SuspendTypeDef

HAL HASH mode suspend definitions.

Enumerator:
HAL_HASH_SUSPEND_NONE

HASH peripheral suspension not requested

HAL_HASH_SUSPEND

HASH peripheral suspension is requested

Definition at line 89 of file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HASH_InitTypeDef Struct Reference
HASH Exported Types

HASH Configuration Structure definition. More...

#include <stm32h7xx_hal_hash.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint8_t * | pKey

Detailed Description

HASH Configuration Structure definition.

Definition at line 47 of file stm32h7xx_hal_hash.h.

Field Documentation

uint32_t HASH_InitTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit data. This parameter can be a value of HASH input data type.

Definition at line 49 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

uint32_t HASH_InitTypeDef::KeySize

The key size is used only in HMAC operation.

Definition at line 52 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_InitTypeDef::pKey

The key is used only in HMAC operation.

Definition at line 54 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hash.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __HASH_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__HASH_HandleTypeDef Struct Reference
HASH Exported Types

HASH Handle Structure definition. More...

#include <stm32h7xx_hal_hash.h>

Data Fields

HASH_InitTypeDef Init
uint8_t * | pHashInBuffPtr
uint8_t * | pHashOutBuffPtr
uint8_t * | pHashKeyBuffPtr
uint8_t * | pHashMsgBuffPtr
uint32_t | HashBuffSize
__IO uint32_t | HashInCount
__IO uint32_t | HashITCounter
__IO uint32_t | HashKeyCount
HAL_StatusTypeDef | Status
HAL_HASH_PhaseTypeDef Phase
DMA_HandleTypeDef * hdmain
HAL_LockTypeDef | Lock
__IO HAL_HASH_StateTypeDef | State
HAL_HASH_SuspendTypeDef SuspendRequest
FlagStatus | DigestCalculationDisable
__IO uint32_t | NbWordsAlreadyPushed
__IO uint32_t | ErrorCode
void(* | InCpltCallback )(struct __HASH_HandleTypeDef *hhash)
void(* | DgstCpltCallback )(struct __HASH_HandleTypeDef *hhash)
void(* | ErrorCallback )(struct __HASH_HandleTypeDef *hhash)
void(* | MspInitCallback )(struct __HASH_HandleTypeDef *hhash)
void(* | MspDeInitCallback )(struct __HASH_HandleTypeDef *hhash)

Detailed Description

HASH Handle Structure definition.

Definition at line 114 of file stm32h7xx_hal_hash.h.

Field Documentation

void(* __HASH_HandleTypeDef::DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash)

HASH digest computation completion callback

Definition at line 158 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HAL_HASH_RegisterCallback(), HAL_HASH_UnRegisterCallback(), and HASH_IT().

FlagStatus __HASH_HandleTypeDef::DigestCalculationDisable

Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation

Definition at line 149 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), HAL_HMACEx_MD5_Step2_DMA(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), HAL_HMACEx_SHA1_Step2_DMA(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), HAL_HMACEx_SHA224_Step2_DMA(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), HAL_HMACEx_SHA256_Step2_DMA(), HASH_DMAXferCplt(), and HMAC_Start_DMA().

void(* __HASH_HandleTypeDef::ErrorCallback)(struct __HASH_HandleTypeDef *hhash)

HASH error callback

Definition at line 160 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HAL_HASH_IRQHandler(), HAL_HASH_RegisterCallback(), HAL_HASH_UnRegisterCallback(), and HASH_DMAError().

__IO uint32_t __HASH_HandleTypeDef::ErrorCode

HASH Error code

Definition at line 153 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_GetError(), HAL_HASH_Init(), HAL_HASH_IRQHandler(), HAL_HASH_RegisterCallback(), HAL_HASH_UnRegisterCallback(), and HASH_DMAError().

uint32_t __HASH_HandleTypeDef::HashBuffSize

Size of buffer to be processed

Definition at line 129 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

__IO uint32_t __HASH_HandleTypeDef::HashInCount

Counter of inputted data

Definition at line 131 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HASH_Init(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_Write_Block_Data(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

__IO uint32_t __HASH_HandleTypeDef::HashITCounter

Counter of issued interrupts

Definition at line 133 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_IT(), HASH_Start_IT(), HASH_Write_Block_Data(), and HMAC_Start_IT().

__IO uint32_t __HASH_HandleTypeDef::HashKeyCount

Counter for Key inputted data (HMAC only)

Definition at line 135 of file stm32h7xx_hal_hash.h.

Referenced by HASH_WriteData(), HMAC_Processing(), and HMAC_Start().

DMA_HandleTypeDef* __HASH_HandleTypeDef::hdmain

HASH In DMA Handle parameters

Definition at line 141 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_DMAXferCplt(), HASH_Start_DMA(), and HMAC_Start_DMA().

void(* __HASH_HandleTypeDef::InCpltCallback)(struct __HASH_HandleTypeDef *hhash)

HASH input completion callback

Definition at line 156 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HAL_HASH_RegisterCallback(), HAL_HASH_UnRegisterCallback(), HASH_DMAXferCplt(), and HASH_IT().

HASH_InitTypeDef __HASH_HandleTypeDef::Init

HASH required parameters

Definition at line 119 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

HAL_LockTypeDef __HASH_HandleTypeDef::Lock

Locking object

Definition at line 143 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

void(* __HASH_HandleTypeDef::MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash)

HASH Msp DeInit callback

Definition at line 164 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_RegisterCallback(), and HAL_HASH_UnRegisterCallback().

void(* __HASH_HandleTypeDef::MspInitCallback)(struct __HASH_HandleTypeDef *hhash)

HASH Msp Init callback

Definition at line 162 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HAL_HASH_RegisterCallback(), and HAL_HASH_UnRegisterCallback().

__IO uint32_t __HASH_HandleTypeDef::NbWordsAlreadyPushed

Numbers of words already pushed in FIFO before inputting new block

Definition at line 151 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HASH_Init(), HASH_DMAXferCplt(), HASH_Start_DMA(), and HMAC_Start_DMA().

HAL_HASH_PhaseTypeDef __HASH_HandleTypeDef::Phase

HASH peripheral phase

Definition at line 139 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* __HASH_HandleTypeDef::pHashInBuffPtr

Pointer to input buffer

Definition at line 121 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_Write_Block_Data(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* __HASH_HandleTypeDef::pHashKeyBuffPtr

Pointer to key buffer (HMAC only)

Definition at line 125 of file stm32h7xx_hal_hash.h.

Referenced by HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* __HASH_HandleTypeDef::pHashMsgBuffPtr

Pointer to message buffer (HMAC only)

Definition at line 127 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* __HASH_HandleTypeDef::pHashOutBuffPtr

Pointer to output buffer (digest)

Definition at line 123 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), HASH_Start_IT(), HMAC_Processing(), HMAC_Start(), and HMAC_Start_IT().

__IO HAL_HASH_StateTypeDef __HASH_HandleTypeDef::State

HASH peripheral state

Definition at line 145 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HASH_GetState(), HAL_HASH_Init(), HAL_HASH_RegisterCallback(), HAL_HASH_UnRegisterCallback(), HASH_Accumulate(), HASH_DMAError(), HASH_DMAXferCplt(), HASH_Finish(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

HAL_StatusTypeDef __HASH_HandleTypeDef::Status

HASH peripheral status

Definition at line 137 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_GetStatus(), HAL_HASH_Init(), HAL_HASH_IRQHandler(), HASH_Accumulate(), HASH_DMAError(), HASH_Start(), HASH_WaitOnFlagUntilTimeout(), and HMAC_Processing().

HAL_HASH_SuspendTypeDef __HASH_HandleTypeDef::SuspendRequest

HASH peripheral suspension request flag

Definition at line 147 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_SwFeed_ProcessSuspend(), HASH_IT(), and HASH_WriteData().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hash.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH algorithm selection

Defines
HASH algorithm selection
HASH Exported Constants

Defines

#define | HASH_ALGOSELECTION_SHA1 0x00000000U
#define | HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0
#define | HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1
#define | HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO

Define Documentation

#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0

HASH function is MD5

Definition at line 190 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_MD5_Accumulate(), HAL_HASH_MD5_Start(), HAL_HASH_MD5_Start_DMA(), HAL_HASH_MD5_Start_IT(), HAL_HMAC_MD5_Start(), HAL_HMAC_MD5_Start_DMA(), HAL_HMAC_MD5_Start_IT(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), and HAL_HMACEx_MD5_Step2_DMA().

#define HASH_ALGOSELECTION_SHA1 0x00000000U

HASH function is SHA1

Definition at line 189 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_SHA1_Accumulate(), HAL_HASH_SHA1_Start(), HAL_HASH_SHA1_Start_DMA(), HAL_HASH_SHA1_Start_IT(), HAL_HMAC_SHA1_Start(), HAL_HMAC_SHA1_Start_DMA(), HAL_HMAC_SHA1_Start_IT(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), and HAL_HMACEx_SHA1_Step2_DMA().

#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1

HASH function is SHA224

Definition at line 191 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASHEx_SHA224_Accumulate(), HAL_HASHEx_SHA224_Start(), HAL_HASHEx_SHA224_Start_DMA(), HAL_HASHEx_SHA224_Start_IT(), HAL_HMACEx_SHA224_Start(), HAL_HMACEx_SHA224_Start_DMA(), HAL_HMACEx_SHA224_Start_IT(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), and HAL_HMACEx_SHA224_Step2_DMA().

#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO

HASH function is SHA256

Definition at line 192 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASHEx_SHA256_Accumulate(), HAL_HASHEx_SHA256_Start(), HAL_HASHEx_SHA256_Start_DMA(), HAL_HASHEx_SHA256_Start_IT(), HAL_HMACEx_SHA256_Start(), HAL_HMACEx_SHA256_Start_DMA(), HAL_HMACEx_SHA256_Start_IT(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), and HAL_HMACEx_SHA256_Step2_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH algorithm mode

Defines
HASH algorithm mode
HASH Exported Constants

Defines

#define | HASH_ALGOMODE_HASH 0x00000000U
#define | HASH_ALGOMODE_HMAC HASH_CR_MODE

Define Documentation

#define HASH_ALGOMODE_HASH 0x00000000U

Algorithm is HASH

Definition at line 200 of file stm32h7xx_hal_hash.h.

#define HASH_ALGOMODE_HMAC HASH_CR_MODE

Algorithm is HMAC

Definition at line 201 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH input data type

Defines
HASH input data type
HASH Exported Constants

Defines

#define | HASH_DATATYPE_32B 0x00000000U
#define | HASH_DATATYPE_16B HASH_CR_DATATYPE_0
#define | HASH_DATATYPE_8B HASH_CR_DATATYPE_1
#define | HASH_DATATYPE_1B HASH_CR_DATATYPE

Define Documentation

#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0

16-bit data. Each half word is swapped

Definition at line 210 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_1B HASH_CR_DATATYPE

1-bit data. In the word all bits are swapped

Definition at line 212 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_32B 0x00000000U

32-bit data. No swapping

Definition at line 209 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1

8-bit data. All bytes are swapped

Definition at line 211 of file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC key length type

Defines
HMAC key length type
HASH Exported Constants

Defines

#define | HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U
#define | HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY

Define Documentation

#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY

HMAC Key size is > 64 bytes

Definition at line 221 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U

HMAC Key size is <= 64 bytes

Definition at line 220 of file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH flags definitions

Defines
HASH flags definitions
HASH Exported Constants

Defines

#define | HASH_FLAG_DINIS HASH_SR_DINIS
#define | HASH_FLAG_DCIS HASH_SR_DCIS
#define | HASH_FLAG_DMAS HASH_SR_DMAS
#define | HASH_FLAG_BUSY HASH_SR_BUSY
#define | HASH_FLAG_DINNE HASH_CR_DINNE

Define Documentation

#define HASH_FLAG_BUSY HASH_SR_BUSY

The hash core is Busy, processing a block of data

Definition at line 232 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_IT(), HASH_WriteData(), and HMAC_Processing().

#define HASH_FLAG_DCIS HASH_SR_DCIS

Digest calculation complete

Definition at line 230 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

#define HASH_FLAG_DINIS HASH_SR_DINIS

16 locations are free in the DIN : a new block can be entered in the IP

Definition at line 229 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), and HASH_WriteData().

#define HASH_FLAG_DINNE HASH_CR_DINNE

DIN not empty : the input buffer contains at least one word of data

Definition at line 233 of file stm32h7xx_hal_hash.h.

#define HASH_FLAG_DMAS HASH_SR_DMAS

DMA interface is enabled (DMAE=1) or a transfer is ongoing

Definition at line 231 of file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH interrupts definitions

Defines
HASH interrupts definitions
HASH Exported Constants

Defines

#define | HASH_IT_DINI HASH_IMR_DINIE
#define | HASH_IT_DCI HASH_IMR_DCIE

Define Documentation

#define HASH_IT_DCI HASH_IMR_DCIE

Digest calculation complete

Definition at line 243 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextSaving(), HASH_IT(), HASH_Start_IT(), and HMAC_Start_IT().

#define HASH_IT_DINI HASH_IMR_DINIE

A new block can be entered into the input buffer (DIN)

Definition at line 242 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextSaving(), HASH_IT(), HASH_Start_IT(), HASH_Write_Block_Data(), and HMAC_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH API alias

Defines
HASH API alias
HASH Exported Constants

Defines

#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler

Define Documentation

#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler

HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code

Definition at line 251 of file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH Error Definition

Defines
HASH Error Definition
HASH Exported Constants

Defines

#define | HAL_HASH_ERROR_NONE 0x00000000U
#define | HAL_HASH_ERROR_IT 0x00000001U
#define | HAL_HASH_ERROR_DMA 0x00000002U
#define | HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U

Define Documentation

#define HAL_HASH_ERROR_DMA 0x00000002U

DMA-based process error

Definition at line 261 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAError().

#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U

Invalid Callback error

Definition at line 263 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_RegisterCallback(), and HAL_HASH_UnRegisterCallback().

#define HAL_HASH_ERROR_IT 0x00000001U

IT-based process error

Definition at line 260 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_IRQHandler().

#define HAL_HASH_ERROR_NONE 0x00000000U

No error

Definition at line 259 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), and HAL_HASH_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH Exported Macros

Defines
HASH Exported Macros
HASH

Defines

#define | __HAL_HASH_GET_FLAG(__FLAG__)
Check whether or not the specified HASH flag is set.
#define | __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
Clear the specified HASH flag.
#define | __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
Enable the specified HASH interrupt.
#define | __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
Disable the specified HASH interrupt.
#define | __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__)
Reset HASH handle state.
#define | __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
Reset HASH handle status.
#define | __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
Enable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
Disable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
Start the digest computation.
#define | __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
Set the number of valid bits in the last word written in data register DIN.
#define | __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
Reset the HASH core.

Define Documentation

#define __HAL_HASH_CLEAR_FLAG ( __FLAG__ ) CLEAR_BIT(HASH->SR, (__FLAG__))

Clear the specified HASH flag.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • HASH_FLAG_DINIS A new block can be entered into the input buffer.
  • HASH_FLAG_DCIS Digest calculation complete
Return values:
None

Definition at line 300 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))

Disable the specified HASH interrupt.

Parameters:
__INTERRUPT__,: specifies the HASH interrupt source to disable. This parameter can be one of the following values:
  • HASH_IT_DINI A new block can be entered into the input buffer (DIN)
  • HASH_IT_DCI Digest calculation complete
Return values:
None

Definition at line 319 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), and HASH_Write_Block_Data().

#define __HAL_HASH_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(HASH->IMR, (__INTERRUPT__))

Enable the specified HASH interrupt.

Parameters:
__INTERRUPT__,: specifies the HASH interrupt source to enable. This parameter can be one of the following values:
  • HASH_IT_DINI A new block can be entered into the input buffer (DIN)
  • HASH_IT_DCI Digest calculation complete
Return values:
None

Definition at line 310 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), HASH_Start_IT(), and HMAC_Start_IT().

#define __HAL_HASH_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) > 8U)  ?                    \
                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )

Check whether or not the specified HASH flag is set.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • HASH_FLAG_DINIS A new block can be entered into the input buffer.
  • HASH_FLAG_DCIS Digest calculation complete.
  • HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
  • HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
  • HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 288 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_IT(), HASH_WaitOnFlagUntilTimeout(), and HASH_WriteData().

#define __HAL_HASH_INIT ( ) SET_BIT(HASH->CR, HASH_CR_INIT)

Reset the HASH core.

Return values:
None

Definition at line 374 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextRestoring().

#define __HAL_HASH_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;      \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
                                                     }while(0)

Reset HASH handle state.

Parameters:
__HANDLE__,: HASH handle.
Return values:
None

Definition at line 327 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_RESET_HANDLE_STATUS ( __HANDLE__ ) ((__HANDLE__)->Status = HAL_OK)

Reset HASH handle status.

Parameters:
__HANDLE__,: HASH handle.
Return values:
None

Definition at line 341 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_RESET_MDMAT ( ) CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)

Disable the multi-buffer DMA transfer mode.

Return values:
None

Definition at line 354 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), and HMAC_Start_DMA().

#define __HAL_HASH_SET_MDMAT ( ) SET_BIT(HASH->CR, HASH_CR_MDMAT)

Enable the multi-buffer DMA transfer mode.

Note:
This bit is set when hashing large files when multiple DMA transfers are needed.
Return values:
None

Definition at line 348 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt().

#define __HAL_HASH_SET_NBVALIDBITS ( __SIZE__ ) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))

Set the number of valid bits in the last word written in data register DIN.

Parameters:
__SIZE__,: size in bytes of last data written in Data register.
Return values:
None

Definition at line 368 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HMAC_Processing(), HMAC_Start_DMA(), and HMAC_Start_IT().

#define __HAL_HASH_START_DIGEST ( ) SET_BIT(HASH->STR, HASH_STR_DCAL)

Start the digest computation.

Return values:
None

Definition at line 361 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start(), HASH_Write_Block_Data(), and HMAC_Processing().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH Private Macros

Defines
HASH Private Macros
HASH

Defines

#define | HASH_DIGEST_LENGTH()
Return digest length in bytes.
#define | HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
Return number of words already pushed in the FIFO.
#define | IS_HASH_DATATYPE(__DATATYPE__)
Ensure that HASH input data type is valid.
#define | IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.
#define | IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.
#define | IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__, __SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.
#define | IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
Ensure that handle phase is set to HASH processing.
#define | IS_HMAC_PROCESSING(__HANDLE__)
Ensure that handle phase is set to HMAC processing.

Define Documentation

#define HASH_DIGEST_LENGTH ( )
Value:
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : \
                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28U : \
                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32U : 16U ) ) )

Return digest length in bytes.

Return values:
Digest length

Definition at line 389 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

#define HASH_NBW_PUSHED ( ) ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)

Return number of words already pushed in the FIFO.

Return values:
Number of words already pushed in the FIFO

Definition at line 396 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Start_DMA(), and HMAC_Start_DMA().

#define IS_HASH_DATATYPE ( __DATATYPE__ )
Value:
(((__DATATYPE__) == HASH_DATATYPE_32B)|| \
                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
                                        ((__DATATYPE__) == HASH_DATATYPE_1B))

Ensure that HASH input data type is valid.

Parameters:
__DATATYPE__,: HASH input data type.
Return values:
SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)

Definition at line 403 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

#define IS_HASH_DMA_MULTIBUFFER_SIZE ( __SIZE__ ) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))

Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.

Note:
This check is valid only for multi-buffer HASH processing in DMA mode.
Parameters:
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 425 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start_DMA().

#define IS_HASH_POLLING_MULTIBUFFER_SIZE ( __SIZE__ ) (((__SIZE__) % 4U) == 0U)

Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.

Note:
This check is valid only for multi-buffer HASH processing in polling mode.
Parameters:
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 417 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Accumulate().

#define IS_HASH_PROCESSING ( __HANDLE__ ) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)

Ensure that handle phase is set to HASH processing.

Parameters:
__HANDLE__,: HASH handle.
Return values:
SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)

Definition at line 441 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start_DMA().

#define IS_HMAC_DMA_MULTIBUFFER_SIZE | ( | __HANDLE__,
 |  | __SIZE__
 | ) | ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))

Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.

Note:
This check is valid only for multi-buffer HMAC processing in DMA mode.
Parameters:
__HANDLE__,: HASH handle.
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 435 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start_DMA().

#define IS_HMAC_PROCESSING ( __HANDLE__ )
Value:
(((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))

Ensure that handle phase is set to HMAC processing.

Parameters:
__HANDLE__,: HASH handle.
Return values:
SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)

Definition at line 448 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH extended processing functions in polling mode

Functions
HASH extended processing functions in polling mode
HASH Extended Exported Functions

HASH extended processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.

Detailed Description

HASH extended processing functions using polling mode.

 ===============================================================================
               ##### Polling mode HASH extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start()
         (++) HAL_HASHEx_SHA224_Accumulate()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start()
         (++) HAL_HASHEx_SHA256_Accumulate()

    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().

    [..]  In case of multi-buffer HASH processing (a single digest is computed while
          several buffers are fed to the IP), the user can resort to successive calls
          to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
          to HAL_HASHEx_xxx_Start().

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASHEx_SHA224_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 168 of file stm32h7xx_hal_hash_ex.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA224.

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 143 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASHEx_SHA256_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 209 of file stm32h7xx_hal_hash_ex.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA256.

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 184 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH extended processing functions in interrupt mode

Functions
HASH extended processing functions in interrupt mode
HASH Extended Exported Functions

HASH extended processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.

Detailed Description

HASH extended processing functions using interrupt mode.

 ===============================================================================
          ##### Interruption mode HASH extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start_IT()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Return values:
HAL status

Definition at line 248 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start_IT().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Return values:
HAL status

Definition at line 263 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH extended processing functions in DMA mode

Functions
HASH extended processing functions in DMA mode
HASH Extended Exported Functions

HASH extended processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.

Detailed Description

HASH extended processing functions using DMA mode.

 ===============================================================================
                ##### DMA mode HASH extended  processing functionss #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start_DMA()
         (++) HAL_HASHEx_SHA224_Finish()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start_DMA()
         (++) HAL_HASHEx_SHA256_Finish()

    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
          to  HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
          HAL_HASHEx_xxx_Finish().

    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
          the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
          reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
          retrieved thanks to HAL_HASHEx_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA224 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in HMAC SHA224 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 329 of file stm32h7xx_hal_hash_ex.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 314 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start_DMA().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA256 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in HMAC SHA256 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 359 of file stm32h7xx_hal_hash_ex.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 344 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC extended processing functions in polling mode

Functions
HMAC extended processing functions in polling mode
HASH Extended Exported Functions

HMAC extended processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.

Detailed Description

HMAC extended processing functions using polling mode.

 ===============================================================================
             ##### Polling mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start()

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 401 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 419 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC extended processing functions in interrupt mode

Functions
HMAC extended processing functions in interrupt mode
HASH Extended Exported Functions

HMAC extended processing functions using interruption mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.

Detailed Description

HMAC extended processing functions using interruption mode.

 ===============================================================================
             ##### Interrupt mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start_IT()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Return values:
HAL status

Definition at line 461 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start_IT().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Return values:
HAL status

Definition at line 478 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HMAC extended processing functions in DMA mode

Functions
HMAC extended processing functions in DMA mode
HASH Extended Exported Functions

HMAC extended processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HMAC extended processing functions using DMA mode.

 ===============================================================================
              ##### DMA mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start_DMA()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start_DMA()

    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
          user must resort to  HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
          with HAL_HASHEx_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 535 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 559 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Multi-buffer HMAC extended processing functions in DMA mode

Functions
Multi-buffer HMAC extended processing functions in DMA mode
HASH Extended Exported Functions

HMAC extended processing functions in multi-buffer DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

HMAC extended processing functions in multi-buffer DMA mode.

 ===============================================================================
      ##### Multi-buffer DMA mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions to manage HMAC multi-buffer
          DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
      (+) MD5
         (++) HAL_HMACEx_MD5_Step1_2_DMA()
         (++) HAL_HMACEx_MD5_Step2_DMA()
         (++) HAL_HMACEx_MD5_Step2_3_DMA()
      (+) SHA1
         (++) HAL_HMACEx_SHA1_Step1_2_DMA()
         (++) HAL_HMACEx_SHA1_Step2_DMA()
         (++) HAL_HMACEx_SHA1_Step2_3_DMA()

      (+) SHA256
         (++) HAL_HMACEx_SHA224_Step1_2_DMA()
         (++) HAL_HMACEx_SHA224_Step2_DMA()
         (++) HAL_HMACEx_SHA224_Step2_3_DMA()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Step1_2_DMA()
         (++) HAL_HMACEx_SHA256_Step2_DMA()
         (++) HAL_HMACEx_SHA256_Step2_3_DMA()

    [..]  User must first start-up the multi-buffer DMA-based HMAC computation in
          calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
          intiates step 2 with the first input buffer.

    [..]  The following buffers are next fed to the IP with a call to the API
          HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
          to this API.

    [..]  Multi-buffer DMA-based HMAC computation is wrapped up by a call to
          HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
          buffer to the IP then carries out step 3.

    [..]  Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
          SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.

    [..]  If only two buffers need to be consecutively processed, a call to
          HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
          is sufficient.

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 635 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 682 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 656 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 705 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 752 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 726 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 774 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 821 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 795 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 843 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 890 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 864 of file stm32h7xx_hal_hash_ex.c.

References __HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Private Functions

Functions
HCD Private Functions
HCD

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.

Function Documentation

static void HCD_HC_IN_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel IN interrupt requests.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 1160 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), __HCD_HandleTypeDef::hc, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, __HCD_HandleTypeDef::Init, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_HC_OUT_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel OUT interrupt requests.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 1346 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), __HCD_HandleTypeDef::hc, HCD_SPEED_HIGH, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_Port_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Host Port interrupt requests.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 1550 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, HAL_HCD_Connect_Callback(), HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HCD_SPEED_FULL, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::Instance, __HCD_HandleTypeDef::PortDisabledCallback, and __HCD_HandleTypeDef::PortEnabledCallback.

Referenced by HAL_HCD_IRQHandler().

static void HCD_RXQLVL_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Rx Queue Level interrupt requests.

Parameters:
hhcd HCD handle
Return values:
none

Definition at line 1496 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL USB OTG HCD Callback ID enumeration definition

Enumerations
HAL USB OTG HCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG HCD Callback ID enumeration definition. More...

Enumerations

enum HAL_HCD_CallbackIDTypeDef {
HAL_HCD_SOF_CB_ID = 0x01, HAL_HCD_CONNECT_CB_ID = 0x02, HAL_HCD_DISCONNECT_CB_ID = 0x03, HAL_HCD_PORT_ENABLED_CB_ID = 0x04,
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, HAL_HCD_MSPINIT_CB_ID = 0x06, HAL_HCD_MSPDEINIT_CB_ID = 0x07
}

Detailed Description

HAL USB OTG HCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_HCD_CallbackIDTypeDef
Enumerator:
HAL_HCD_SOF_CB_ID

USB HCD SOF callback ID

HAL_HCD_CONNECT_CB_ID

USB HCD Connect callback ID

HAL_HCD_DISCONNECT_CB_ID

USB HCD Disconnect callback ID

HAL_HCD_PORT_ENABLED_CB_ID

USB HCD Port Enable callback ID

HAL_HCD_PORT_DISABLED_CB_ID

USB HCD Port Disable callback ID

HAL_HCD_MSPINIT_CB_ID

USB HCD MspInit callback ID

HAL_HCD_MSPDEINIT_CB_ID

USB HCD MspDeInit callback ID

Definition at line 192 of file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL USB OTG HCD Callback pointer definition

Typedefs
HAL USB OTG HCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG HCD Callback pointer definition. More...

Typedefs

typedef void(* | pHCD_CallbackTypeDef )(HCD_HandleTypeDef *hhcd)
typedef void(* | pHCD_HC_NotifyURBChangeCallbackTypeDef )(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

Detailed Description

HAL USB OTG HCD Callback pointer definition.

Typedef Documentation

typedef void(* pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd)

pointer to a common USB OTG HCD callback function

Definition at line 213 of file stm32h7xx_hal_hcd.h.

typedef void(* pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

pointer to USB OTG HCD host channel callback

Definition at line 214 of file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
HCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG HCD Callback ID enumeration definition

HAL USB OTG HCD Callback ID enumeration definition.

HAL USB OTG HCD Callback pointer definition

HAL USB OTG HCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_HCD_DeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 265 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, HAL_HCD_MspDeInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_HC_Halt | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

Halt a host channel.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 249 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_HC_Init | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | dev_address,
 |  | uint8_t | speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | mps
 | ) |  |

Initialize a host channel.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
epnum | Endpoint number. This parameter can be a value from 1 to 15
dev_address | Current device address This parameter can be a value from 0 to 255
speed | Current device speed. This parameter can be one of these values: HCD_SPEED_HIGH: High speed mode, HCD_SPEED_FULL: Full speed mode, HCD_SPEED_LOW: Low speed mode
ep_type | Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type, EP_TYPE_ISOC: Isochronous type, EP_TYPE_BULK: Bulk type, EP_TYPE_INTR: Interrupt type
mps | Max Packet Size. This parameter can be a value from 0 to32K
Return values:
HAL status

Definition at line 201 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Init ( HCD_HandleTypeDef * hhcd )

Initialize the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 111 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, assert_param, __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, HAL_HCD_Connect_Callback(), HAL_HCD_Disconnect_Callback(), HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_MspInit(), HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::Instance, __HCD_HandleTypeDef::Lock, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

void HAL_HCD_MspDeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the HCD MSP.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 315 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_UnRegisterCallback().

void HAL_HCD_MspInit ( HCD_HandleTypeDef * hhcd )

Initialize the HCD MSP.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 300 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), and HAL_HCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_HCD_RegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID,
 |  | pHCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB HCD Callback To be used instead of the weak predefined callback.

Parameters:
hhcd | USB HCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 721 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_CONNECT_CB_ID, HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | pHCD_HC_NotifyURBChangeCallbackTypeDef | pCallback
 | ) |  |

Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd | HCD handle
pCallback | pointer to the USB HCD Host Channel Notify URB Change Callback function
Return values:
HAL status

Definition at line 913 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_UnRegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.

Parameters:
hhcd USB HCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 822 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_Connect_Callback(), HAL_HCD_CONNECT_CB_ID, HAL_HCD_Disconnect_Callback(), HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MspDeInit(), HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MspInit(), HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback ( HCD_HandleTypeDef * hhcd )

UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 953 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
HCD Exported Functions

HCD IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Detailed Description

HCD IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..] This subsection provides a set of functions allowing to manage the USB Host Data
    Transfer

Function Documentation

void HAL_HCD_Connect_Callback ( HCD_HandleTypeDef * hhcd )

Connection Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 622 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void HAL_HCD_Disconnect_Callback ( HCD_HandleTypeDef * hhcd )

Disconnection Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 637 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), and HAL_HCD_UnRegisterCallback().

void HAL_HCD_HC_NotifyURBChange_Callback | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum,
 |  | HCD_URBStateTypeDef | urb_state
 | ) |  |

Notify URB state change callback.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
urb_state,: This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/
Return values:
None

Definition at line 692 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(), HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | direction,
 |  | uint8_t | ep_type,
 |  | uint8_t | token,
 |  | uint8_t * | pbuff,
 |  | uint16_t | length,
 |  | uint8_t | do_ping
 | ) |  |

Submit a new URB for processing.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
direction | Channel number. This parameter can be one of these values: 0 : Output / 1 : Input
ep_type | Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type/ EP_TYPE_ISOC: Isochronous type/ EP_TYPE_BULK: Bulk type/ EP_TYPE_INTR: Interrupt type/
token | Endpoint Type. This parameter can be one of these values: 0: HC_PID_SETUP / 1: HC_PID_DATA1
pbuff | pointer to URB data
length | Length of URB data
do_ping | activate do ping protocol (for high speed only). This parameter can be one of these values: 0 : do ping inactive / 1 : do ping active
Return values:
HAL status

Definition at line 367 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, __HCD_HandleTypeDef::Init, and __HCD_HandleTypeDef::Instance.

void HAL_HCD_IRQHandler ( HCD_HandleTypeDef * hhcd )

Handle HCD interrupt request.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 494 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_FLAG, __HAL_HCD_GET_FLAG, __HAL_HCD_IS_INVALID_INTERRUPT, __HCD_HandleTypeDef::DisconnectCallback, HAL_HCD_Disconnect_Callback(), HAL_HCD_SOF_Callback(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), HCD_RXQLVL_IRQHandler(), __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::Instance, and __HCD_HandleTypeDef::SOFCallback.

void HAL_HCD_PortDisabled_Callback ( HCD_HandleTypeDef * hhcd )

Port Disabled Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 667 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void HAL_HCD_PortEnabled_Callback ( HCD_HandleTypeDef * hhcd )

Port Enabled Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 652 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

HAL_StatusTypeDef HAL_HCD_RegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID,
 |  | pHCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB HCD Callback To be used instead of the weak predefined callback.

Parameters:
hhcd | USB HCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 721 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_CONNECT_CB_ID, HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | pHCD_HC_NotifyURBChangeCallbackTypeDef | pCallback
 | ) |  |

Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd | HCD handle
pCallback | pointer to the USB HCD Host Channel Notify URB Change Callback function
Return values:
HAL status

Definition at line 913 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

void HAL_HCD_SOF_Callback ( HCD_HandleTypeDef * hhcd )

SOF callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 607 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), and HAL_HCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_HCD_UnRegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.

Parameters:
hhcd USB HCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 822 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_Connect_Callback(), HAL_HCD_CONNECT_CB_ID, HAL_HCD_Disconnect_Callback(), HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MspDeInit(), HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MspInit(), HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback ( HCD_HandleTypeDef * hhcd )

UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 953 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
HCD Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the HCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_HCD_ResetPort ( HCD_HandleTypeDef * hhcd )

Reset the host port.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1034 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Start ( HCD_HandleTypeDef * hhcd )

Start the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1004 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_ENABLE, and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Stop ( HCD_HandleTypeDef * hhcd )

Stop the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1020 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
HCD Exported Functions

Peripheral State functions. More...

Functions

HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_HCD_GetCurrentFrame ( HCD_HandleTypeDef * hhcd )

Return the current Host frame number.

Parameters:
hhcd HCD handle
Return values:
Current Host frame number

Definition at line 1127 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

uint32_t HAL_HCD_GetCurrentSpeed ( HCD_HandleTypeDef * hhcd )

Return the Host enumeration speed.

Parameters:
hhcd HCD handle
Return values:
Enumeration speed

Definition at line 1137 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

HCD_StateTypeDef HAL_HCD_GetState ( HCD_HandleTypeDef * hhcd )

Return the HCD handle state.

Parameters:
hhcd HCD handle
Return values:
HAL state

Definition at line 1063 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::State.

HCD_HCStateTypeDef HAL_HCD_HC_GetState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the Host Channel state.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
Host channel state This parameter can be one of these values: HC_IDLE/ HC_XFRC/ HC_HALTED/ HC_NYET/ HC_NAK/ HC_STALL/ HC_XACTERR/ HC_BBLERR/ HC_DATATGLERR

Definition at line 1117 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

HCD_URBStateTypeDef HAL_HCD_HC_GetURBState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return URB state for a channel.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
URB state. This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL

Definition at line 1082 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

uint32_t HAL_HCD_HC_GetXferCount | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the last host transfer size.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
last transfer size in byte

Definition at line 1095 of file stm32h7xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD State Structure definition

Typedefs | Enumerations
HCD State Structure definition
HCD Exported Types

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Typedef Documentation

typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef

Definition at line 61 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_HCTypeDef HCD_HCTypeDef

Definition at line 59 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_CfgTypeDef HCD_InitTypeDef

Definition at line 58 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_GlobalTypeDef HCD_TypeDef

Definition at line 57 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef

Definition at line 60 of file stm32h7xx_hal_hcd.h.

Enumeration Type Documentation

enum HCD_StateTypeDef
Enumerator:
HAL_HCD_STATE_RESET
HAL_HCD_STATE_READY
HAL_HCD_STATE_ERROR
HAL_HCD_STATE_BUSY
HAL_HCD_STATE_TIMEOUT

Definition at line 48 of file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Handle Structure definition

Data Structures | Typedefs
HCD Handle Structure definition
HCD Exported Types

Data Structures

struct | __HCD_HandleTypeDef

Typedefs

typedef struct __HCD_HandleTypeDef | HCD_HandleTypeDef

Typedef Documentation

typedef struct __HCD_HandleTypeDef HCD_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __HCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__HCD_HandleTypeDef Struct Reference
HCD Handle Structure definition

#include <stm32h7xx_hal_hcd.h>

Data Fields

HCD_TypeDef * Instance
HCD_InitTypeDef Init
HCD_HCTypeDef | hc [16]
HAL_LockTypeDef | Lock
__IO HCD_StateTypeDef | State
__IO uint32_t | ErrorCode
void * | pData
void(* | SOFCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | ConnectCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | DisconnectCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | PortEnabledCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | PortDisabledCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | HC_NotifyURBChangeCallback )(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
void(* | MspInitCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | MspDeInitCallback )(struct __HCD_HandleTypeDef *hhcd)

Detailed Description

Definition at line 70 of file stm32h7xx_hal_hcd.h.

Field Documentation

void(* __HCD_HandleTypeDef::ConnectCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Connect callback

Definition at line 84 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void(* __HCD_HandleTypeDef::DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Disconnect callback

Definition at line 85 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

__IO uint32_t __HCD_HandleTypeDef::ErrorCode

HCD Error code

Definition at line 80 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback().

HCD_HCTypeDef __HCD_HandleTypeDef::hc[16]

Host channels parameters

Definition at line 77 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_GetState(), HAL_HCD_HC_GetURBState(), HAL_HCD_HC_GetXferCount(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), and HCD_RXQLVL_IRQHandler().

void(* __HCD_HandleTypeDef::HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)

USB OTG HCD Host Channel Notify URB Change callback

Definition at line 88 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(), and HCD_HC_IN_IRQHandler().

HCD_InitTypeDef __HCD_HandleTypeDef::Init

HCD required parameters

Definition at line 76 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HCD_HC_IN_IRQHandler(), and HCD_Port_IRQHandler().

HCD_TypeDef* __HCD_HandleTypeDef::Instance

Register base address

Definition at line 75 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_GetCurrentFrame(), HAL_HCD_GetCurrentSpeed(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), HAL_HCD_Start(), HAL_HCD_Stop(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HAL_LockTypeDef __HCD_HandleTypeDef::Lock

HCD peripheral status

Definition at line 78 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

void(* __HCD_HandleTypeDef::MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Msp DeInit callback

Definition at line 92 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void(* __HCD_HandleTypeDef::MspInitCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Msp Init callback

Definition at line 91 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void* __HCD_HandleTypeDef::pData

Pointer Stack Handler

Definition at line 81 of file stm32h7xx_hal_hcd.h.

void(* __HCD_HandleTypeDef::PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Port Disable callback

Definition at line 87 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void(* __HCD_HandleTypeDef::PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Port Enable callback

Definition at line 86 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void(* __HCD_HandleTypeDef::SOFCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD SOF callback

Definition at line 83 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

__IO HCD_StateTypeDef __HCD_HandleTypeDef::State

HCD communication state

Definition at line 79 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_GetState(), HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hcd.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Speed

Defines
HCD Speed
HCD Exported Constants

Defines

#define | HCD_SPEED_HIGH USBH_HS_SPEED
#define | HCD_SPEED_FULL USBH_FS_SPEED
#define | HCD_SPEED_LOW USBH_LS_SPEED

Define Documentation

#define HCD_SPEED_FULL USBH_FS_SPEED

Definition at line 112 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_HIGH USBH_HS_SPEED

Definition at line 111 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_OUT_IRQHandler().

#define HCD_SPEED_LOW USBH_LS_SPEED

Definition at line 113 of file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD PHY Module

Defines
HCD PHY Module
HCD Exported Constants

Defines

#define | HCD_PHY_ULPI 1U
#define | HCD_PHY_EMBEDDED 2U

Define Documentation

#define HCD_PHY_EMBEDDED 2U

Definition at line 123 of file stm32h7xx_hal_hcd.h.

#define HCD_PHY_ULPI 1U

Definition at line 122 of file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Error Code definition

Defines
HCD Error Code definition
HCD Exported Constants

HCD Error Code definition. More...

Defines

#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

HCD Error Code definition.

Define Documentation

#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 133 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Exported Macros

Defines
HCD Exported Macros
HCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_HCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 153 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_CLEAR_HC_INT | ( | chnum,
 |  | __INTERRUPT__
 | ) | (USBx_HC(chnum)->HCINT = (__INTERRUPT__))

Definition at line 156 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 150 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_Init().

#define __HAL_HCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 149 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Start().

#define __HAL_HCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 152 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)

Definition at line 154 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_MASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)

Definition at line 159 of file stm32h7xx_hal_hcd.h.

#define __HAL_HCD_MASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

Definition at line 157 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_UNMASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Definition at line 160 of file stm32h7xx_hal_hcd.h.

#define __HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)

Definition at line 158 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Private Macros

HCD Private Macros
HCD
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STM32H7B3xQ HAL User Manual: HCD Private Functions Prototypes

HCD Private Functions Prototypes
HCD
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Take and Release functions

Functions
Take and Release functions
HSEM Exported Functions

HSEM Take and Release functions. More...

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .

Detailed Description

HSEM Take and Release functions.

 ==============================================================================
              ##### HSEM Take and Release functions #####
 ==============================================================================
[..] This section provides functions allowing to:
      (+) Take a semaphore with 2 Step method
      (+) Fast Take a semaphore with 1 Step method
      (+) Check semaphore state Taken or not
      (+) Release a semaphore
      (+) Release all semaphore at once

Function Documentation

HAL_StatusTypeDef HAL_HSEM_FastTake ( uint32_t SemID )

Fast Take a semaphore with 1 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
Return values:
HAL status

Definition at line 188 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), and IS_HSEM_SEMID.

uint32_t HAL_HSEM_IsSemTaken ( uint32_t SemID )

Check semaphore state Taken or not.

Parameters:
SemID,: semaphore ID
Return values:
HAL HSEM state

Definition at line 217 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_Release | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Release a semaphore.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
None

Definition at line 229 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

void HAL_HSEM_ReleaseAll | ( | uint32_t | Key,
 |  | uint32_t | CoreID
 | ) |  |

Release All semaphore used by a given Master .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
CoreID,: CoreID of the CPU that is using semaphores to be released
Return values:
None

Definition at line 250 of file stm32h7xx_hal_hsem.c.

References assert_param, IS_HSEM_COREID, and IS_HSEM_KEY.

HAL_StatusTypeDef HAL_HSEM_Take | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Take a semaphore in 2 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
HAL status

Definition at line 151 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSEM Set and Get Key functions

Functions
HSEM Set and Get Key functions
HSEM Exported Functions

HSEM Set and Get Key functions. More...

Functions

void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .

Detailed Description

HSEM Set and Get Key functions.

  ==============================================================================
              ##### HSEM Set and Get Key functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set semaphore Key
      (+) Get semaphore Key

Function Documentation

uint32_t HAL_HSEM_GetClearKey ( void )

Get semaphore Key .

Return values:
Semaphore Key , value from 0 to 0xFFFF

Definition at line 294 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_SetClearKey ( uint32_t Key )

Set semaphore Key .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
Return values:
None

Definition at line 282 of file stm32h7xx_hal_hsem.c.

References assert_param, and IS_HSEM_KEY.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSEM IRQ handler management

Functions
HSEM IRQ handler management
HSEM Exported Functions

HSEM Notification functions. More...

Functions

void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM Notification functions.

  ==============================================================================
      ##### HSEM IRQ handler management and Notification functions #####
  ==============================================================================
[..]  This section provides HSEM IRQ handler and Notification function.

Function Documentation

void HAL_HSEM_ActivateNotification ( uint32_t SemMask )

Activate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 321 of file stm32h7xx_hal_hsem.c.

References HAL_GetCurrentCPUID().

void HAL_HSEM_DeactivateNotification ( uint32_t SemMask )

Deactivate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 345 of file stm32h7xx_hal_hsem.c.

References HAL_GetCurrentCPUID().

void HAL_HSEM_FreeCallback ( uint32_t SemMask )

Semaphore Released Callback.

Parameters:
SemMask,: Mask of Released semaphores
Return values:
None

Definition at line 414 of file stm32h7xx_hal_hsem.c.

Referenced by HAL_HSEM_IRQHandler().

void HAL_HSEM_IRQHandler ( void )

This function handles HSEM interrupt request.

Return values:
None

Definition at line 368 of file stm32h7xx_hal_hsem.c.

References HAL_GetCurrentCPUID(), and HAL_HSEM_FreeCallback().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSEM Exported Macros

Defines
HSEM Exported Macros
HSEM

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.

Define Documentation

#define __HAL_HSEM_CLEAR_FLAG ( __SEM_MASK__ ) (HSEM->ICR |= (__SEM_MASK__))

Clears the HSEM Interrupt flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 112 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_DISABLE_IT ( __SEM_MASK__ ) (HSEM->IER &= ~(__SEM_MASK__))

Disables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 73 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_ENABLE_IT ( __SEM_MASK__ ) (HSEM->IER |= (__SEM_MASK__))

Enables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 61 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_GET_FLAG ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->ISR)

Get the semaphores release status flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where Release flags rise.

Definition at line 99 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_GET_IT ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->MISR)

Checks whether interrupt has occurred or not for semaphores specified by a mask.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where an interrupt occurred.

Definition at line 86 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_SEMID_TO_MASK ( __SEMID__ ) (1 << (__SEMID__))

SemID to mask helper Macro.

Parameters:
__SEMID__,: semaphore ID from 0 to 31
Return values:
Semaphore Mask.

Definition at line 49 of file stm32h7xx_hal_hsem.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSEM Private Macros

Defines
HSEM Private Macros
HSEM

Defines

#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)

Define Documentation

#define IS_HSEM_COREID ( __COREID__ ) ((__COREID__) == HSEM_CPU1_COREID)

Definition at line 192 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll().

#define IS_HSEM_KEY ( __KEY__ ) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )

Definition at line 186 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll(), and HAL_HSEM_SetClearKey().

#define IS_HSEM_PROCESSID ( __PROCESSID__ ) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )

Definition at line 184 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_Release(), and HAL_HSEM_Take().

#define IS_HSEM_SEMID ( __SEMID__ ) ((__SEMID__) <= HSEM_SEMID_MAX )

Definition at line 182 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_FastTake(), HAL_HSEM_Release(), and HAL_HSEM_Take().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 363 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 346 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 345 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 350 of file stm32h7xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 349 of file stm32h7xx_hal_i2c.c.

#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 343 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 344 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), and I2C_ITSlaveCplt().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 348 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveSeqCplt().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 347 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveSeqCplt().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 328 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 329 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 330 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 336 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 331 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 332 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 333 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 334 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 335 of file stm32h7xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (0x00000012U)

Definition at line 359 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT (0x00000011U)

Definition at line 358 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT (0x00000004U)

Definition at line 356 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (0x00000012U)

Definition at line 360 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (0x00000002U)

Definition at line 355 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define I2C_XFER_TX_IT (0x00000001U)

Definition at line 354 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 338 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 340 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SlaveAddr_SHIFT 7U

Definition at line 339 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 327 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.

Function Documentation

static void I2C_ConvertOtherXferOptions ( I2C_HandleTypeDef * hi2c ) [static]

Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6487 of file stm32h7xx_hal_i2c.c.

References I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_OTHER_AND_LAST_FRAME, I2C_OTHER_FRAME, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

static void I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 6424 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 6061 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, __I2C_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6023 of file stm32h7xx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, HAL_DMA_ERROR_FE, HAL_DMA_GetError(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5948 of file stm32h7xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5873 of file stm32h7xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5996 of file stm32h7xx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __I2C_HandleTypeDef::hdmarx, I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5921 of file stm32h7xx_hal_i2c.c.

References I2C_FIRST_FRAME, I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 6353 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Master_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5852 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6266 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5223 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SlaveAddr_MSK, SlaveAddr_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 5734 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5683 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5427 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITMasterSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5318 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5546 of file stm32h7xx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5371 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4868 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4595 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5176 of file stm32h7xx_hal_i2c.c.

References I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5123 of file stm32h7xx_hal_i2c.c.

References I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5003 of file stm32h7xx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4732 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 6334 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6102 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6203 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6169 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6132 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 578 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 469 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_AbortCpltCallback(), HAL_I2C_AddrCallback(), HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspInitCallback, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 640 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), and HAL_I2C_UnRegisterCallback().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 624 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), and HAL_I2C_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | pI2C_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 906 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_RegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID,
 |  | pI2C_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2C Callback To be used instead of the weak predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 672 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback ( I2C_HandleTypeDef * hi2c )

UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 945 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_AddrCallback(), HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 799 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_ErrorCallback(), HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_ListenCpltCallback(), HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MspDeInit(), HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MspInit(), HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()
        (++) HAL_I2C_Master_Seq_Transmit_IT()
        (++) HAL_I2C_Master_Seq_Receive_IT()
        (++) HAL_I2C_Slave_Seq_Transmit_IT()
        (++) HAL_I2C_Slave_Seq_Receive_IT()
        (++) HAL_I2C_EnableListen_IT()
        (++) HAL_I2C_DisableListen_IT()
        (++) HAL_I2C_Master_Abort_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()
        (++) HAL_I2C_Master_Seq_Transmit_DMA()
        (++) HAL_I2C_Master_Seq_Receive_DMA()
        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
        (++) HAL_I2C_Slave_Seq_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_AddrCallback()
        (++) HAL_I2C_ListenCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 4214 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 4190 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3014 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 4247 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1174 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1929 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1619 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3486 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3402 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3240 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3156 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1060 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1786 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1550 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2415 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2873 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2639 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2280 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2729 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2548 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1424 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2173 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1735 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4015 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3920 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3741 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3646 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1287 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2070 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1686 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4512 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C Transfer Direction Master Point of View
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 4430 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4316 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4496 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4297 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4448 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4381 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4365 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4480 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4464 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4412 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4396 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 4570 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 4559 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 4547 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32h7xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 48 of file stm32h7xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 57 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 60 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 69 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 72 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 54 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 63 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C Own Address2 Masks

Definition at line 66 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 50 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2c.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}

Detailed Description

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 Peripheral initialization status
0 : Reset (peripheral not initialized)
1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (peripheral in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (peripheral busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 108 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 148 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 168 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 167 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 166 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 170 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)

DMA Parameter Error

Definition at line 173 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 175 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterAddrCallback(), and HAL_I2C_UnRegisterCallback().

#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 177 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 165 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 169 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 172 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 171 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs | Enumerations
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
typedef void(* pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an I2C Address Match callback function

Definition at line 263 of file stm32h7xx_hal_i2c.h.

typedef void(* pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c)

HAL I2C Callback pointer definition.

pointer to an I2C callback function

Definition at line 262 of file stm32h7xx_hal_i2c.h.

Enumeration Type Documentation

enum HAL_I2C_CallbackIDTypeDef

HAL I2C Callback ID enumeration definition.

Enumerator:
HAL_I2C_MASTER_TX_COMPLETE_CB_ID

I2C Master Tx Transfer completed callback ID

HAL_I2C_MASTER_RX_COMPLETE_CB_ID

I2C Master Rx Transfer completed callback ID

HAL_I2C_SLAVE_TX_COMPLETE_CB_ID

I2C Slave Tx Transfer completed callback ID

HAL_I2C_SLAVE_RX_COMPLETE_CB_ID

I2C Slave Rx Transfer completed callback ID

HAL_I2C_LISTEN_COMPLETE_CB_ID

I2C Listen Complete callback ID

HAL_I2C_MEM_TX_COMPLETE_CB_ID

I2C Memory Tx Transfer callback ID

HAL_I2C_MEM_RX_COMPLETE_CB_ID

I2C Memory Rx Transfer completed callback ID

HAL_I2C_ERROR_CB_ID

I2C Error callback ID

HAL_I2C_ABORT_CB_ID

I2C Abort callback ID

HAL_I2C_MSPINIT_CB_ID

I2C Msp Init callback ID

HAL_I2C_MSPDEINIT_CB_ID

I2C Msp DeInit callback ID

Definition at line 242 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32h7xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount
void(* | MasterTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MasterRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ListenCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ErrorCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AbortCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AddrCallback )(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MspDeInitCallback )(struct __I2C_HandleTypeDef *hi2c)

Detailed Description

Definition at line 186 of file stm32h7xx_hal_i2c.h.

Field Documentation

void(* __I2C_HandleTypeDef::AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Abort callback

Definition at line 228 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void(* __I2C_HandleTypeDef::AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

I2C Slave Address Match callback

Definition at line 230 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 217 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

void(* __I2C_HandleTypeDef::ErrorCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Error callback

Definition at line 227 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 215 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 207 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 205 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 190 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 188 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

void(* __I2C_HandleTypeDef::ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Listen Complete callback

Definition at line 224 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 209 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

void(* __I2C_HandleTypeDef::MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Rx Transfer completed callback

Definition at line 221 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Tx Transfer completed callback

Definition at line 220 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Rx Transfer completed callback

Definition at line 226 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void(* __I2C_HandleTypeDef::MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Tx Transfer completed callback

Definition at line 225 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 213 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

void(* __I2C_HandleTypeDef::MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp DeInit callback

Definition at line 233 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

void(* __I2C_HandleTypeDef::MspInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp Init callback

Definition at line 232 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 192 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 201 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Rx Transfer completed callback

Definition at line 223 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Tx Transfer completed callback

Definition at line 222 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 211 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 196 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 203 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 198 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 194 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2c.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 285 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 283 of file stm32h7xx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 282 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 286 of file stm32h7xx_hal_i2c.h.

#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 287 of file stm32h7xx_hal_i2c.h.

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 284 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Definition at line 293 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

#define I2C_OTHER_FRAME (0x000000AAU)

Definition at line 292 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 302 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 301 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 310 of file stm32h7xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 311 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 320 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 321 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 322 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 323 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 324 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 325 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 326 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 319 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 334 of file stm32h7xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 335 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 343 of file stm32h7xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 344 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 353 of file stm32h7xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 352 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Transfer Direction Master Point of View

Defines
I2C Transfer Direction Master Point of View
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 362 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 361 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 371 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 370 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 372 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 382 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 383 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 381 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 380 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 398 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 394 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 397 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 399 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 396 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 395 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 400 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 411 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 412 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 421 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 417 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 416 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 422 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 423 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 418 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 419 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 410 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 413 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 414 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 415 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 420 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 408 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 409 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 543 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 556 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 482 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 550 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 466 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 562 of file stm32h7xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 524 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 498 of file stm32h7xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 443 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_MASK (0x0001FFFFU)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 523 of file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define | I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Define Documentation

#define I2C_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

Definition at line 752 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 753 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 749 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ ) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))

Definition at line 737 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ ) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))

Definition at line 738 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))

Definition at line 740 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

Definition at line 741 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 739 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 747 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 746 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 735 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 691 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 694 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 706 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 712 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 709 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 743 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 744 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 697 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 724 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_OTHER_FRAME)     || \
                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

Definition at line 732 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 715 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 719 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
Extended features functions
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
Extended features functions

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 107 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 110 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))

Definition at line 113 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
Extended features functions
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Modules

I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature
      (+) Configure Fast Mode Plus

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 97 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 141 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 310 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 231 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 281 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 192 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 50 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE 0x00000000U

Definition at line 49 of file stm32h7xx_hal_i2c_ex.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 62 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 63 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 64 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP

Enable Fast Mode Plus on I2C4 pins

Definition at line 65 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 58 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 59 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 60 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 61 of file stm32h7xx_hal_i2c_ex.h.

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STM32H7B3xQ HAL User Manual: I2S Private Functions

I2S Private Functions
I2S
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity

     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 455 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::MspDeInitCallback, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 256 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::Data24BitAlignment, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, I2S_InitTypeDef::FirstBit, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_PRESCALER, HAL_I2S_ErrorCallback(), HAL_I2S_MspInit(), HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), HAL_RCCEx_GetPeriphCLKFreq(), I2S_AUDIOFREQ_DEFAULT, I2S_DATAFORMAT_16B, I2S_MCLKOUTPUT_ENABLE, I2S_STANDARD_PCM_LONG, I2S_STANDARD_PCM_SHORT, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_24BIT_ALIGNMENT, IS_I2S_DATA_FORMAT, IS_I2S_FIRST_BIT, IS_I2S_MASTER, IS_I2S_MASTER_KEEP_IO_STATE, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, IS_I2S_WS_INVERSION, __I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MasterKeepIOState, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::MspInitCallback, RCC_PERIPHCLK_SPI123, RCC_PERIPHCLK_SPI6, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, I2S_InitTypeDef::Standard, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, __I2S_HandleTypeDef::TxHalfCpltCallback, and I2S_InitTypeDef::WSInversion.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 515 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit(), and HAL_I2S_UnRegisterCallback().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 499 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), and HAL_I2S_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2S_RegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID,
 |  | pI2S_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2S Callback To be used instead of the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 535 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_UnRegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 633 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_ErrorCallback(), HAL_I2S_MspDeInit(), HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MspInit(), HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1292 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __I2S_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2S_ERROR_NO_OGT, HAL_I2S_ERROR_NOT_SUPPORTED, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_READY, I2S_TIMEOUT, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_MASTER, I2S_InitTypeDef::Mode, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1364 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Stops the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1399 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_I2S_ERROR_DMA, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, __I2S_HandleTypeDef::hdmatx, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1584 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1448 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_FRE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_CHECK_FLAG, I2S_FLAG_FRE, I2S_FLAG_OVR, I2S_FLAG_RXP, I2S_FLAG_TXP, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_FRE, I2S_IT_RXP, I2S_IT_TXP, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxISR.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 886 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_OVR, I2S_FLAG_RXP, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1216 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronization between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 1059 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_FRE, I2S_IT_OVR, I2S_IT_RXP, I2S_MODE_SLAVE_RX, I2S_Receive_16Bit_IT(), I2S_Receive_32Bit_IT(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1568 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), I2S_Receive_16Bit_IT(), and I2S_Receive_32Bit_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1552 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 777 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ERROR_UDR, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_TXP, I2S_FLAG_UDR, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Transmit data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1133 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmatx, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 982 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_FRE, I2S_IT_TXP, I2S_IT_UDR, I2S_MODE_SLAVE_TX, I2S_Transmit_16Bit_IT(), I2S_Transmit_32Bit_IT(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxISR, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1536 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1520 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1630 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1619 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Exported Functions

Modules | Functions
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_16Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the transmission 16-bit in Interrupt context.
static void | I2S_Transmit_32Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the transmission 32-bit in Interrupt context.
static void | I2S_Receive_16Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the reception 16-bit in Interrupt context.
static void | I2S_Receive_32Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the reception 32-bit in Interrupt context.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1734 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1690 of file stm32h7xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1716 of file stm32h7xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback(), and __I2S_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1645 of file stm32h7xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1672 of file stm32h7xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback(), and __I2S_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_Receive_16Bit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Manage the reception 16-bit in Interrupt context.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1817 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXP, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_IT().

static void I2S_Receive_32Bit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Manage the reception 32-bit in Interrupt context.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1845 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXP, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_IT().

static void I2S_Transmit_16Bit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Manage the transmission 16-bit in Interrupt context.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1761 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXP, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_IT().

static void I2S_Transmit_32Bit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Manage the transmission 32-bit in Interrupt context.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1789 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXP, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_IT().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag | Flag checked
State | Value of the flag expected
Timeout | Duration of the timeout
Return values:
HAL status

Definition at line 1876 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Exported Types

Data Structures | Typedefs | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00UL, HAL_I2S_STATE_READY = 0x01UL, HAL_I2S_STATE_BUSY = 0x02UL, HAL_I2S_STATE_BUSY_TX = 0x03UL,
HAL_I2S_STATE_BUSY_RX = 0x04UL, HAL_I2S_STATE_TIMEOUT = 0x06UL, HAL_I2S_STATE_ERROR = 0x07UL
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL,
HAL_I2S_ERROR_CB_ID = 0x06UL, HAL_I2S_MSPINIT_CB_ID = 0x07UL, HAL_I2S_MSPDEINIT_CB_ID = 0x08UL
}
HAL I2S Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __I2S_HandleTypeDef I2S_HandleTypeDef

I2S handle Structure definition.

typedef void(* pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s)

HAL I2S Callback pointer definition.

pointer to an I2S callback function

Definition at line 168 of file stm32h7xx_hal_i2s.h.

Enumeration Type Documentation

enum HAL_I2S_CallbackIDTypeDef

HAL I2S Callback ID enumeration definition.

Enumerator:
HAL_I2S_TX_COMPLETE_CB_ID

I2S Tx Completed callback ID

HAL_I2S_RX_COMPLETE_CB_ID

I2S Rx Completed callback ID

HAL_I2S_TX_HALF_COMPLETE_CB_ID

I2S Tx Half Completed callback ID

HAL_I2S_RX_HALF_COMPLETE_CB_ID

I2S Rx Half Completed callback ID

HAL_I2S_ERROR_CB_ID

I2S Error callback ID

HAL_I2S_MSPINIT_CB_ID

I2S Msp Init callback ID

HAL_I2S_MSPDEINIT_CB_ID

I2S Msp DeInit callback ID

Definition at line 153 of file stm32h7xx_hal_i2s.h.

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 84 of file stm32h7xx_hal_i2s.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32h7xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL
uint32_t | FirstBit
uint32_t | WSInversion
uint32_t | Data24BitAlignment
uint32_t | MasterKeepIOState

Detailed Description

I2S Init structure definition.

Definition at line 47 of file stm32h7xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 61 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S_Clock_Polarity

Definition at line 64 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Data24BitAlignment

Specifies the Data Padding for 24 bits data length This parameter can be a value of Data Padding 24Bit

Definition at line 73 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 55 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), and HAL_I2S_Transmit_IT().

uint32_t I2S_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of I2S_MSB_LSB_transmission

Definition at line 67 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MasterKeepIOState

Control of Alternate function GPIOs state This parameter can be a value of Keep IO State

Definition at line 76 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S MCLK Output

Definition at line 58 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 49 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_Init(), HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 52 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::WSInversion

Control the Word Select Inversion. This parameter can be a value of I2S Word Select Inversion

Definition at line 70 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2s.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32h7xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
void(* | RxISR )(struct __I2S_HandleTypeDef *hi2s)
void(* | TxISR )(struct __I2S_HandleTypeDef *hi2s)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | TxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | ErrorCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspInitCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspDeInitCallback )(struct __I2S_HandleTypeDef *hi2s)

Detailed Description

I2S handle Structure definition.

Definition at line 98 of file stm32h7xx_hal_i2s.h.

Field Documentation

void(* __I2S_HandleTypeDef::ErrorCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Error callback

Definition at line 141 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

__IO uint32_t __I2S_HandleTypeDef::ErrorCode

I2S Error code This parameter can be a value of I2S Error

Definition at line 133 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmarx

I2S Rx DMA handle parameters

Definition at line 127 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmatx

I2S Tx DMA handle parameters

Definition at line 125 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef __I2S_HandleTypeDef::Init

I2S communication parameters

Definition at line 102 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), and HAL_I2S_Transmit_IT().

SPI_TypeDef* __I2S_HandleTypeDef::Instance

I2S registers base address

Definition at line 100 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_16Bit_IT(), I2S_Receive_32Bit_IT(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

__IO HAL_LockTypeDef __I2S_HandleTypeDef::Lock

I2S locking object

Definition at line 129 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

void(* __I2S_HandleTypeDef::MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp DeInit callback

Definition at line 143 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

void(* __I2S_HandleTypeDef::MspInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp Init callback

Definition at line 142 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

uint16_t* __I2S_HandleTypeDef::pRxBuffPtr

Pointer to I2S Rx transfer buffer

Definition at line 110 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_Receive_16Bit_IT(), and I2S_Receive_32Bit_IT().

uint16_t* __I2S_HandleTypeDef::pTxBuffPtr

Pointer to I2S Tx transfer buffer

Definition at line 104 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

void(* __I2S_HandleTypeDef::RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Completed callback

Definition at line 138 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), I2S_Receive_16Bit_IT(), and I2S_Receive_32Bit_IT().

void(* __I2S_HandleTypeDef::RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Half Completed callback

Definition at line 140 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

void(* __I2S_HandleTypeDef::RxISR)(struct __I2S_HandleTypeDef *hi2s)

function pointer on Rx ISR

Definition at line 121 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive_IT().

__IO uint16_t __I2S_HandleTypeDef::RxXferCount

I2S Rx transfer counter (This field is initialized at the same value as transfer size at the beginning of the transfer and decremented when a sample is received NbSamplesReceived = RxBufferSize-RxBufferCount)

Definition at line 114 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_Receive_16Bit_IT(), and I2S_Receive_32Bit_IT().

__IO uint16_t __I2S_HandleTypeDef::RxXferSize

I2S Rx transfer size

Definition at line 112 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

__IO HAL_I2S_StateTypeDef __I2S_HandleTypeDef::State

I2S communication state

Definition at line 131 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_16Bit_IT(), I2S_Receive_32Bit_IT(), I2S_Transmit_16Bit_IT(), I2S_Transmit_32Bit_IT(), and I2S_WaitFlagStateUntilTimeout().

void(* __I2S_HandleTypeDef::TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Completed callback

Definition at line 137 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

void(* __I2S_HandleTypeDef::TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Half Completed callback

Definition at line 139 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

void(* __I2S_HandleTypeDef::TxISR)(struct __I2S_HandleTypeDef *hi2s)

function pointer on Tx ISR

Definition at line 123 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit_IT().

__IO uint16_t __I2S_HandleTypeDef::TxXferCount

I2S Tx transfer Counter

Definition at line 108 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMATxCplt(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

__IO uint16_t __I2S_HandleTypeDef::TxXferSize

I2S Tx transfer size

Definition at line 106 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2s.h
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Error

Defines
I2S Error
I2S Exported Constants

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000UL)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001UL)
#define | HAL_I2S_ERROR_OVR (0x00000002UL)
#define | HAL_I2S_ERROR_UDR (0x00000004UL)
#define | HAL_I2S_ERROR_DMA (0x00000008UL)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010UL)
#define | HAL_I2S_ERROR_FRE (0x00000020UL)
#define | HAL_I2S_ERROR_NO_OGT (0x00000040UL)
#define | HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL)

Define Documentation

#define HAL_I2S_ERROR_DMA (0x00000008UL)

DMA transfer error

Definition at line 186 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), and I2S_DMAError().

#define HAL_I2S_ERROR_FRE (0x00000020UL)

FRE error

Definition at line 188 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL)

Invalid Callback error

Definition at line 192 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

#define HAL_I2S_ERROR_NO_OGT (0x00000040UL)

No On Going Transfer error

Definition at line 189 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause().

#define HAL_I2S_ERROR_NONE (0x00000000UL)

No error

Definition at line 182 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAResume(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL)

Requested operation not supported

Definition at line 190 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause().

#define HAL_I2S_ERROR_OVR (0x00000002UL)

OVR error

Definition at line 184 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define HAL_I2S_ERROR_PRESCALER (0x00000010UL)

Prescaler Calculation error

Definition at line 187 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL)

Timeout error

Definition at line 183 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_Receive(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UDR (0x00000004UL)

UDR error

Definition at line 185 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX (0x00000000UL)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define | I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

Define Documentation

#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

Definition at line 206 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Definition at line 204 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Definition at line 203 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)

Definition at line 205 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Definition at line 202 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT().

#define I2S_MODE_SLAVE_TX (0x00000000UL)

Definition at line 201 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit_IT().

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STM32H7B3xQ HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS (0x00000000UL)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

Definition at line 216 of file stm32h7xx_hal_i2s.h.

#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

Definition at line 215 of file stm32h7xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Definition at line 218 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

Definition at line 217 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PHILIPS (0x00000000UL)

Definition at line 214 of file stm32h7xx_hal_i2s.h.

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STM32H7B3xQ HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B (0x00000000UL)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
#define | I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define I2S_DATAFORMAT_16B (0x00000000UL)

Definition at line 226 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Definition at line 227 of file stm32h7xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)

Definition at line 228 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)

Definition at line 229 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), and HAL_I2S_Transmit_IT().

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STM32H7B3xQ HAL User Manual: I2S MCLK Output

Defines
I2S MCLK Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000UL)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)

Definition at line 238 of file stm32h7xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)

Definition at line 237 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K (192000UL)
#define | I2S_AUDIOFREQ_96K (96000UL)
#define | I2S_AUDIOFREQ_48K (48000UL)
#define | I2S_AUDIOFREQ_44K (44100UL)
#define | I2S_AUDIOFREQ_32K (32000UL)
#define | I2S_AUDIOFREQ_22K (22050UL)
#define | I2S_AUDIOFREQ_16K (16000UL)
#define | I2S_AUDIOFREQ_11K (11025UL)
#define | I2S_AUDIOFREQ_8K (8000UL)
#define | I2S_AUDIOFREQ_DEFAULT (2UL)

Define Documentation

#define I2S_AUDIOFREQ_11K (11025UL)

Definition at line 253 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K (16000UL)

Definition at line 252 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K (192000UL)

Definition at line 246 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K (22050UL)

Definition at line 251 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K (32000UL)

Definition at line 250 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K (44100UL)

Definition at line 249 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K (48000UL)

Definition at line 248 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K (8000UL)

Definition at line 254 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K (96000UL)

Definition at line 247 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT (2UL)

Definition at line 255 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

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STM32H7B3xQ HAL User Manual: I2S FullDuplex Mode

Defines
I2S FullDuplex Mode
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW (0x00000000UL)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Definition at line 264 of file stm32h7xx_hal_i2s.h.

#define I2S_CPOL_LOW (0x00000000UL)

Definition at line 263 of file stm32h7xx_hal_i2s.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S MSB LSB Transmission

Defines
I2S MSB LSB Transmission
I2S Exported Constants

Defines

#define | I2S_FIRSTBIT_MSB (0x00000000UL)
#define | I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Define Documentation

#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Definition at line 273 of file stm32h7xx_hal_i2s.h.

#define I2S_FIRSTBIT_MSB (0x00000000UL)

Definition at line 272 of file stm32h7xx_hal_i2s.h.

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STM32H7B3xQ HAL User Manual: I2S Word Select Inversion

Defines
I2S Word Select Inversion
I2S Exported Constants

Defines

#define | I2S_WS_INVERSION_DISABLE (0x00000000UL)
#define | I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV

Define Documentation

#define I2S_WS_INVERSION_DISABLE (0x00000000UL)

Definition at line 281 of file stm32h7xx_hal_i2s.h.

#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV

Definition at line 282 of file stm32h7xx_hal_i2s.h.

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STM32H7B3xQ HAL User Manual: Data Padding 24Bit

Defines
Data Padding 24Bit
I2S Exported Constants

Defines

#define | I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
#define | I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT

Define Documentation

#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT

Definition at line 291 of file stm32h7xx_hal_i2s.h.

#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)

Definition at line 290 of file stm32h7xx_hal_i2s.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Keep IO State

Defines
Keep IO State
I2S Exported Constants

Defines

#define | I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Define Documentation

#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)

Definition at line 299 of file stm32h7xx_hal_i2s.h.

#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Definition at line 300 of file stm32h7xx_hal_i2s.h.

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STM32H7B3xQ HAL User Manual: I2S Interrupts Definition

Defines
I2S Interrupts Definition
I2S Exported Constants

Defines

#define | I2S_IT_RXP SPI_IER_RXPIE
#define | I2S_IT_TXP SPI_IER_TXPIE
#define | I2S_IT_UDR SPI_IER_UDRIE
#define | I2S_IT_OVR SPI_IER_OVRIE
#define | I2S_IT_FRE SPI_IER_TIFREIE
#define | I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)

Define Documentation

#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)

Definition at line 313 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_16Bit_IT(), I2S_Receive_32Bit_IT(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

#define I2S_IT_FRE SPI_IER_TIFREIE

Definition at line 312 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define I2S_IT_OVR SPI_IER_OVRIE

Definition at line 311 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT().

#define I2S_IT_RXP SPI_IER_RXPIE

Definition at line 308 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), I2S_Receive_16Bit_IT(), and I2S_Receive_32Bit_IT().

#define I2S_IT_TXP SPI_IER_TXPIE

Definition at line 309 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

#define I2S_IT_UDR SPI_IER_UDRIE

Definition at line 310 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit_IT().

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STM32H7B3xQ HAL User Manual: I2S Flags Definition

Defines
I2S Flags Definition
I2S Exported Constants

Defines

#define | I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
#define | I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
#define | I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
#define | I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
#define | I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
#define | I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)

Define Documentation

#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */

Definition at line 325 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)

Definition at line 327 of file stm32h7xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */

Definition at line 324 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */

Definition at line 321 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */

Definition at line 322 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */

Definition at line 323 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the I2S UDR pending flag.
#define | __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the I2S FRE pending flag.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

Clear the I2S OVR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 430 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define __HAL_I2S_CLEAR_TIFREFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

Clear the I2S FRE pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 442 of file stm32h7xx_hal_i2s.h.

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

Clear the I2S UDR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 436 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define __HAL_I2S_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))

Disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 365 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), and HAL_I2S_Init().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_RXP : Rx-Packet available interrupt
  • I2S_IT_TXP : Tx-Packet space available interrupt
  • I2S_IT_UDR : Underrun interrupt
  • I2S_IT_OVR : Overrun interrupt
  • I2S_IT_FRE : TI mode frame format error interrupt
  • I2S_IT_ERR : Error interrupt enable
Return values:
None

Definition at line 395 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_16Bit_IT(), I2S_Receive_32Bit_IT(), I2S_Transmit_16Bit_IT(), and I2S_Transmit_32Bit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))

Enable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 359 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_RXP : Rx-Packet available interrupt
  • I2S_IT_TXP : Tx-Packet space available interrupt
  • I2S_IT_UDR : Underrun interrupt
  • I2S_IT_OVR : Overrun interrupt
  • I2S_IT_FRE : TI mode frame format error interrupt
  • I2S_IT_ERR : Error interrupt enable
Return values:
None

Definition at line 380 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified I2S flag is set or not.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXP : Rx-Packet available flag
  • I2S_FLAG_TXP : Tx-Packet space available flag
  • I2S_FLAG_UDR : Underrun flag
  • I2S_FLAG_OVR : Overrun flag
  • I2S_FLAG_FRE : TI mode frame format error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 424 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_RXP : Rx-Packet available interrupt
  • I2S_IT_TXP : Tx-Packet space available interrupt
  • I2S_IT_UDR : Underrun interrupt
  • I2S_IT_OVR : Overrun interrupt
  • I2S_IT_FRE : TI mode frame format error interrupt
  • I2S_IT_ERR : Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 410 of file stm32h7xx_hal_i2s.h.

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset I2S handle state.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 346 of file stm32h7xx_hal_i2s.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Private Constants

I2S Private Constants
I2S
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_MASTER(__MODE__)
#define | IS_I2S_SLAVE(__MODE__)
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
#define | IS_I2S_FIRST_BIT(__BIT__)
#define | IS_I2S_WS_INVERSION(__WSINV__)
#define | IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__)
#define | IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__)

Define Documentation

#define I2S_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) | ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of I2S SR register.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXP : Rx-Packet available flag
  • I2S_FLAG_TXP : Tx-Packet space available flag
  • I2S_FLAG_UDR : Underrun flag
  • I2S_FLAG_OVR : Overrun flag
  • I2S_FLAG_FRE : TI mode frame format error flag
Return values:
SET or RESET.

Definition at line 543 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_CHECK_IT_SOURCE | ( | __IER__,
 |  | __INTERRUPT__
 | ) | ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__IER__ copy of I2S IER register.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_RXP : Rx-Packet available interrupt
  • I2S_IT_TXP : Tx-Packet space available interrupt
  • I2S_IT_UDR : Underrun interrupt
  • I2S_IT_OVR : Overrun interrupt
  • I2S_IT_FRE : TI mode frame format error interrupt
  • I2S_IT_ERR : Error interrupt enable
Return values:
SET or RESET.

Definition at line 557 of file stm32h7xx_hal_i2s.h.

#define IS_I2S_AUDIO_FREQ ( __FREQ__ )
Value:
((((__FREQ__) >= I2S_AUDIOFREQ_8K)                    && \
                                                     ((__FREQ__) <= I2S_AUDIOFREQ_192K))                 || \
                                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 593 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == I2S_CPOL_LOW)                        || \
                                                     ((__CPOL__) == I2S_CPOL_HIGH))

Definition at line 597 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_24BIT_ALIGNMENT ( __ALIGNMENT__ )
Value:
(((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
                                                     ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))

Definition at line 606 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == I2S_DATAFORMAT_16B)                || \
                                                     ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)       || \
                                                     ((__FORMAT__) == I2S_DATAFORMAT_24B)                || \
                                                     ((__FORMAT__) == I2S_DATAFORMAT_32B))

Definition at line 585 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_FIRST_BIT ( __BIT__ )
Value:
(((__BIT__) == I2S_FIRSTBIT_MSB)                     || \
                                                     ((__BIT__) == I2S_FIRSTBIT_LSB))

Definition at line 600 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MASTER ( __MODE__ )
Value:
(((__MODE__) == I2S_MODE_MASTER_TX)                  || \
                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))

Definition at line 571 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), and HAL_I2S_Init().

#define IS_I2S_MASTER_KEEP_IO_STATE ( __AFCNTR__ )
Value:
(((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE)  || \
                                                     ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))

Definition at line 609 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)             || \
                                                     ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 590 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( __MODE__ )
Value:
(((__MODE__) == I2S_MODE_SLAVE_TX)                   || \
                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                   || \
                                                     ((__MODE__) == I2S_MODE_MASTER_TX)                  || \
                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)           || \
                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))

Checks if I2S Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the I2S Mode. This parameter can be a value of I2S Mode
Return values:
None

Definition at line 564 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_SLAVE ( __MODE__ )
Value:
(((__MODE__) == I2S_MODE_SLAVE_TX)                  || \
                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                  || \
                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))

Definition at line 575 of file stm32h7xx_hal_i2s.h.

#define IS_I2S_STANDARD ( __STANDARD__ )
Value:
(((__STANDARD__) == I2S_STANDARD_PHILIPS)            || \
                                                     ((__STANDARD__) == I2S_STANDARD_MSB)                || \
                                                     ((__STANDARD__) == I2S_STANDARD_LSB)                || \
                                                     ((__STANDARD__) == I2S_STANDARD_PCM_SHORT)          || \
                                                     ((__STANDARD__) == I2S_STANDARD_PCM_LONG))

Definition at line 579 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_WS_INVERSION ( __WSINV__ )
Value:
(((__WSINV__) == I2S_WS_INVERSION_DISABLE)           || \
                                                     ((__WSINV__) == I2S_WS_INVERSION_ENABLE))

Definition at line 603 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S

Modules | Defines
I2S
STM32H7xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Private Functions
I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Constants
I2S Private Macros

Defines

#define I2S_TIMEOUT 0xFFFFUL

Detailed Description

I2S HAL module driver.

Define Documentation

#define I2S_TIMEOUT 0xFFFFUL

Definition at line 192 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_DMAPause().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2SEx

I2SEx
STM32H7xx_HAL_Driver

I2S Extended HAL module driver. More...

I2S Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                     | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 208 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000U

IRDA TX or RX enable acknowledge time-out value

Definition at line 206 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 213 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 211 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) |
Value:
((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
                                                                  + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | IRDA clock source.
__BAUD__ | Baud rate set by the user.
__PRESCALER__ | IRDA clock prescaler value.
Return values:
Division result

Definition at line 228 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201U)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__ specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 694 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))

Ensure that IRDA clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ IRDA clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 728 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__ IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 773 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__ IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 766 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__ IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 752 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__ IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 759 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__ IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 706 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__ IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 721 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0U)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__ specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 700 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__ IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 780 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__ IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 745 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ )
Value:
((((__MODE__)\
                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__ IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 714 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 392 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::MspDeInitCallback, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 327 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, __IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_InitCallbacksToDefault(), IRDA_SetConfig(), __IRDA_HandleTypeDef::Lock, and __IRDA_HandleTypeDef::MspInitCallback.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 451 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_UnRegisterCallback().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 435 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_Init(), and HAL_IRDA_UnRegisterCallback().

HAL_StatusTypeDef HAL_IRDA_RegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID,
 |  | pIRDA_CallbackTypeDef | pCallback
 | ) |  |

Register a User IRDA Callback To be used instead of the weak predefined callback.

Parameters:
hirda | irda handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 481 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Parameters:
hirda irda handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 603 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_ErrorCallback(), HAL_IRDA_MspDeInit(), HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MspInit(), HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

 ===============================================================================
                         ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

  [..]
    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_IRDA_Abort()
        (++) HAL_IRDA_AbortTransmit()
        (++) HAL_IRDA_AbortReceive()
        (++) HAL_IRDA_Abort_IT()
        (++) HAL_IRDA_AbortTransmit_IT()
        (++) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_IRDA_AbortCpltCallback()
        (++) HAL_IRDA_AbortTransmitCpltCallback()
        (++) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1576 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2102 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1518 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1786 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2134 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1466 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1708 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2118 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1230 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1268 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1303 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and __IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2086 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1862 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 887 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
When the IRDA parity is enabled (PCE = 1), the received data contains the parity bit (MSB position).
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1154 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1022 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2054 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2070 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 798 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1074 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 977 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and __IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2022 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 2038 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 2190 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 2173 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, and __IRDA_HandleTypeDef::RxState.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2327 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2595 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_ErrorCallback(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2555 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2500 of file stm32h7xx_hal_irda.c.

References DMA_CIRCULAR, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2536 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2666 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2741 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2445 of file stm32h7xx_hal_irda.c.

References DMA_CIRCULAR, HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2481 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2618 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2714 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2428 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static void IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2810 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::TxCpltCallback.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2412 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and __IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

void IRDA_InitCallbacksToDefault ( IRDA_HandleTypeDef * hirda )

Initialize the callbacks to their default values.

Parameters:
hirda IRDA handle.
Return values:
none

Definition at line 2213 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ErrorCallback(), HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Init().

static void IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2835 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2234 of file stm32h7xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, IRDA_InitTypeDef::ClockPrescaler, CSI_VALUE, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_CSI, IRDA_CLOCKSOURCE_D2PCLK1, IRDA_CLOCKSOURCE_D2PCLK2, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PLL2Q, IRDA_CLOCKSOURCE_PLL3Q, IRDA_CR1_FIELDS, IRDA_DIV_SAMPLING16, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_CLOCKPRESCALER, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, USART_BRR_MAX, USART_BRR_MIN, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static void IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2771 of file stm32h7xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2378 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA Exported Types

Data Structures | Typedefs | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_D2PCLK1 = 0x11U, IRDA_CLOCKSOURCE_D2PCLK2 = 0x12U, IRDA_CLOCKSOURCE_PLL2Q = 0x14U, IRDA_CLOCKSOURCE_PLL3Q = 0x18U,
IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_CSI = 0x08U, IRDA_CLOCKSOURCE_LSE = 0x10U, IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_IRDA_StateTypeDef

HAL IRDA State definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState (see IRDA State Code Definition).
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 118 of file stm32h7xx_hal_irda.h.

typedef struct __IRDA_HandleTypeDef IRDA_HandleTypeDef

IRDA handle Structure definition.

typedef void(* pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda)

HAL IRDA Callback pointer definition.

pointer to an IRDA callback function

Definition at line 225 of file stm32h7xx_hal_irda.h.

Enumeration Type Documentation

enum HAL_IRDA_CallbackIDTypeDef

HAL IRDA Callback ID enumeration definition.

Enumerator:
HAL_IRDA_TX_HALFCOMPLETE_CB_ID

IRDA Tx Half Complete Callback ID

HAL_IRDA_TX_COMPLETE_CB_ID

IRDA Tx Complete Callback ID

HAL_IRDA_RX_HALFCOMPLETE_CB_ID

IRDA Rx Half Complete Callback ID

HAL_IRDA_RX_COMPLETE_CB_ID

IRDA Rx Complete Callback ID

HAL_IRDA_ERROR_CB_ID

IRDA Error Callback ID

HAL_IRDA_ABORT_COMPLETE_CB_ID

IRDA Abort Complete Callback ID

HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID

IRDA Abort Transmit Complete Callback ID

HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID

IRDA Abort Receive Complete Callback ID

HAL_IRDA_MSPINIT_CB_ID

IRDA MspInit callback ID

HAL_IRDA_MSPDEINIT_CB_ID

IRDA MspDeInit callback ID

Definition at line 206 of file stm32h7xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

IRDA_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

IRDA_CLOCKSOURCE_PLL2Q

PLL2Q clock source

IRDA_CLOCKSOURCE_PLL3Q

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_CSI

CSI clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 123 of file stm32h7xx_hal_irda.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32h7xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode
uint32_t | ClockPrescaler

Detailed Description

IRDA Init Structure definition.

Definition at line 47 of file stm32h7xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) where usart_ker_ckpres is the IRDA input clock divided by a prescaler

Definition at line 49 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the IRDA clock source. This parameter can be a value of IRDA Clock Prescaler.

Definition at line 74 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 64 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 57 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 71 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 67 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDAEx Word Length

Definition at line 54 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_irda.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32h7xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | TxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | ErrorCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortTransmitCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortReceiveCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspInitCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspDeInitCallback )(struct __IRDA_HandleTypeDef *hirda)

Detailed Description

IRDA handle Structure definition.

Definition at line 139 of file stm32h7xx_hal_irda.h.

Field Documentation

void(* __IRDA_HandleTypeDef::AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Complete Callback

Definition at line 188 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Receive Complete Callback

Definition at line 192 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Transmit Complete Callback

Definition at line 190 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::ErrorCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Error Callback

Definition at line 186 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

__IO uint32_t __IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 175 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DeInit(), HAL_IRDA_DMAStop(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 168 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 164 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 162 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef __IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 146 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* __IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 144 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef __IRDA_HandleTypeDef::Lock

Locking object

Definition at line 166 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t __IRDA_HandleTypeDef::Mask

USART RX RDR register mask

Definition at line 160 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp DeInit callback

Definition at line 197 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

void(* __IRDA_HandleTypeDef::MspInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp Init callback

Definition at line 195 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

uint8_t* __IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 154 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* __IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 148 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

void(* __IRDA_HandleTypeDef::RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Complete Callback

Definition at line 184 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Half Complete Callback

Definition at line 182 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 172 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t __IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 158 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t __IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 156 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Complete Callback

Definition at line 180 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Half Complete Callback

Definition at line 178 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO uint16_t __IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 152 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t __IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 150 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_irda.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDA State Code Definition

Defines
IRDA State Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_IRDA_STATE_BUSY 0x00000024U

An internal process is ongoing Value is allowed for gState only

Definition at line 245 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define HAL_IRDA_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 249 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), and IRDA_Receive_IT().

#define HAL_IRDA_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 247 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), and IRDA_Transmit_IT().

#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 251 of file stm32h7xx_hal_irda.h.

#define HAL_IRDA_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 256 of file stm32h7xx_hal_irda.h.

#define HAL_IRDA_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 243 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define HAL_IRDA_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 241 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 254 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Error Code Definition

Defines
IRDA Error Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)

Busy Error

Definition at line 271 of file stm32h7xx_hal_irda.h.

#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 270 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), and IRDA_DMAError().

#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)

frame error

Definition at line 268 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 273 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 267 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 265 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 269 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 266 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

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STM32H7B3xQ HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define IRDA_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 283 of file stm32h7xx_hal_irda.h.

#define IRDA_PARITY_NONE 0x00000000U

No parity

Definition at line 282 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 284 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define IRDA_MODE_RX USART_CR1_RE

RX mode

Definition at line 292 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_TX USART_CR1_TE

TX mode

Definition at line 293 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 294 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

Define Documentation

#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

IRDA low power mode

Definition at line 303 of file stm32h7xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL 0x00000000U

IRDA normal power mode

Definition at line 302 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Clock Prescaler

Defines
IRDA Clock Prescaler
IRDA Exported Constants

Defines

#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define IRDA_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 311 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 316 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 317 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 321 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 318 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 312 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 322 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 319 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 313 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 314 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 320 of file stm32h7xx_hal_irda.h.

#define IRDA_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 315 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE

Define Documentation

#define IRDA_STATE_DISABLE 0x00000000U

IRDA disabled

Definition at line 330 of file stm32h7xx_hal_irda.h.

#define IRDA_STATE_ENABLE USART_CR1_UE

IRDA enabled

Definition at line 331 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN

Define Documentation

#define IRDA_MODE_DISABLE 0x00000000U

Associated UART disabled in IRDA mode

Definition at line 339 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_ENABLE USART_CR3_IREN

Associated UART enabled in IRDA mode

Definition at line 340 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disabled

Definition at line 348 of file stm32h7xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enabled

Definition at line 349 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define IRDA_DMA_TX_DISABLE 0x00000000U

IRDA DMA TX disabled

Definition at line 357 of file stm32h7xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT

IRDA DMA TX enabled

Definition at line 358 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define IRDA_DMA_RX_DISABLE 0x00000000U

IRDA DMA RX disabled

Definition at line 366 of file stm32h7xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR

IRDA DMA RX enabled

Definition at line 367 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 375 of file stm32h7xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 376 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 377 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE USART_ISR_ABRE

IRDA auto Baud rate error

Definition at line 391 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_ABRF USART_ISR_ABRF

IRDA auto Baud rate flag

Definition at line 390 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_BUSY USART_ISR_BUSY

IRDA busy flag

Definition at line 389 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_FE USART_ISR_FE

IRDA frame error

Definition at line 397 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_NE USART_ISR_NE

IRDA noise error

Definition at line 396 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_ORE USART_ISR_ORE

IRDA overrun error

Definition at line 395 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_PE USART_ISR_PE

IRDA parity error

Definition at line 398 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_REACK USART_ISR_REACK

IRDA receive enable acknowledge flag

Definition at line 387 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE

IRDA read data register not empty

Definition at line 394 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC USART_ISR_TC

IRDA transmission complete

Definition at line 393 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK USART_ISR_TEACK

IRDA transmit enable acknowledge flag

Definition at line 388 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF

IRDA transmit data register empty

Definition at line 392 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

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STM32H7B3xQ HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR 0x0060U

IRDA Error interruption

Definition at line 425 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_FE 0x0100U

IRDA Frame error interruption

Definition at line 431 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_IDLE 0x0424U

IRDA Idle interruption

Definition at line 417 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_NE 0x0200U

IRDA Noise error interruption

Definition at line 430 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_ORE 0x0300U

IRDA Overrun error interruption

Definition at line 429 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_PE 0x0028U

IRDA Parity error interruption

Definition at line 413 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_RXNE 0x0525U

IRDA Read data register not empty interruption

Definition at line 416 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_TC 0x0626U

IRDA Transmission complete interruption

Definition at line 415 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_TXE 0x0727U

IRDA Transmit data register empty interruption

Definition at line 414 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 440 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 443 of file stm32h7xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 441 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 442 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 439 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 444 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

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STM32H7B3xQ HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U

Define Documentation

#define IRDA_CR_MASK 0x00E0U

IRDA control register mask

Definition at line 453 of file stm32h7xx_hal_irda.h.

#define IRDA_CR_POS 5U

IRDA control register position

Definition at line 454 of file stm32h7xx_hal_irda.h.

#define IRDA_ISR_MASK 0x1F00U

IRDA ISR register mask

Definition at line 455 of file stm32h7xx_hal_irda.h.

#define IRDA_ISR_POS 8U

IRDA ISR register position

Definition at line 456 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_MASK 0x001FU

IRDA Interruptions flags mask

Definition at line 452 of file stm32h7xx_hal_irda.h.

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STM32H7B3xQ HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 523 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 510 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 541 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 642 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 529 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 535 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 516 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 679 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 592 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 673 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 576 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the IRDA DR register.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 492 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 561 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                        & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 611 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
                                                                (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
                                                                 (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 626 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 666 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 660 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset IRDA handle state.

Parameters:
__HANDLE__ IRDA handle.
Return values:
None

Definition at line 475 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 654 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDAEx Word Length

Defines
IRDAEx Word Length
IRDAEx Extended Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define IRDA_WORDLENGTH_7B USART_CR1_M1

7-bit long frame

Definition at line 49 of file stm32h7xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_8B 0x00000000U

8-bit long frame

Definition at line 50 of file stm32h7xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_9B USART_CR1_M0

9-bit long frame

Definition at line 51 of file stm32h7xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__ | specifies the IRDA Handle.
__CLOCKSOURCE__ | output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 74 of file stm32h7xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 582 of file stm32h7xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__ IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 627 of file stm32h7xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Definition at line 115 of file stm32h7xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32h7xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 47 of file stm32h7xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 49 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 52 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 55 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_iwdg.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32h7xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 63 of file stm32h7xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 67 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 65 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_iwdg.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 88 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 85 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 89 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 86 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 83 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 87 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 84 of file stm32h7xx_hal_iwdg.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 98 of file stm32h7xx_hal_iwdg.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 126 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 118 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 155 of file stm32h7xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 239 of file stm32h7xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

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STM32H7B3xQ HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 168 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 167 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 170 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 169 of file stm32h7xx_hal_iwdg.h.

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STM32H7B3xQ HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 200 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 213 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 220 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 193 of file stm32h7xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 186 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

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STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
JPEG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.
HAL_StatusTypeDef | HAL_JPEG_RegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, pJPEG_CallbackTypeDef pCallback)
Register a User JPEG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
Unregister a JPEG Callback JPEG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_InfoReadyCallbackTypeDef pCallback)
Register Info Ready JPEG Callback To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Info Ready JPEG Callback Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
Register Get Data JPEG Callback To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Get Data JPEG Callback Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_DataReadyCallbackTypeDef pCallback)
Register Data Ready JPEG Callback To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Data Ready JPEG Callback Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the JPEG peripheral and creates the associated handle
      (+) DeInitialize the JPEG peripheral

Function Documentation

HAL_StatusTypeDef HAL_JPEG_DeInit ( JPEG_HandleTypeDef * hjpeg )

DeInitializes the JPEG peripheral.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 608 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_NONE, HAL_JPEG_MspDeInit(), HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_RESET, __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::MspDeInitCallback, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Init ( JPEG_HandleTypeDef * hjpeg )

Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 484 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, __JPEG_HandleTypeDef::GetDataCallback, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_ERROR_HUFF_TABLE, HAL_JPEG_ERROR_NONE, HAL_JPEG_ErrorCallback(), HAL_JPEG_GetDataCallback(), HAL_JPEG_InfoReadyCallback(), HAL_JPEG_MspInit(), HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, HAL_JPEG_STATE_RESET, __JPEG_HandleTypeDef::InfoReadyCallback, __JPEG_HandleTypeDef::Instance, JPEG_FLAG_ALL, JPEG_INTERRUPT_MASK, JPEG_QUANT_TABLE_SIZE, JPEG_Set_HuffEnc_Mem(), __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::Lock, __JPEG_HandleTypeDef::MspInitCallback, __JPEG_HandleTypeDef::QuantTable0, __JPEG_HandleTypeDef::QuantTable1, __JPEG_HandleTypeDef::QuantTable2, __JPEG_HandleTypeDef::QuantTable3, and __JPEG_HandleTypeDef::State.

void HAL_JPEG_MspDeInit ( JPEG_HandleTypeDef * hjpeg )

DeInitializes JPEG MSP.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 675 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_DeInit(), and HAL_JPEG_UnRegisterCallback().

void HAL_JPEG_MspInit ( JPEG_HandleTypeDef * hjpeg )

Initializes the JPEG MSP.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 659 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), and HAL_JPEG_UnRegisterCallback().

HAL_StatusTypeDef HAL_JPEG_RegisterCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | HAL_JPEG_CallbackIDTypeDef | CallbackID,
 |  | pJPEG_CallbackTypeDef | pCallback
 | ) |  |

Register a User JPEG Callback To be used instead of the weak predefined callback.

Parameters:
hjpeg | JPEG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
  • HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
  • HAL_JPEG_ERROR_CB_ID Error callback ID
  • HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
  • HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 700 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_DECODE_CPLT_CB_ID, HAL_JPEG_ENCODE_CPLT_CB_ID, HAL_JPEG_ERROR_CB_ID, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_MSPDEINIT_CB_ID, HAL_JPEG_MSPINIT_CB_ID, HAL_JPEG_STATE_READY, HAL_JPEG_STATE_RESET, __JPEG_HandleTypeDef::MspDeInitCallback, __JPEG_HandleTypeDef::MspInitCallback, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | pJPEG_DataReadyCallbackTypeDef | pCallback
 | ) |  |

Register Data Ready JPEG Callback To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback.

Parameters:
hjpeg | JPEG handle
pCallback | pointer to the Get Data Callback function
Return values:
HAL status

Definition at line 1007 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_STATE_READY, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | pJPEG_GetDataCallbackTypeDef | pCallback
 | ) |  |

Register Get Data JPEG Callback To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback.

Parameters:
hjpeg | JPEG handle
pCallback | pointer to the Get Data Callback function
Return values:
HAL status

Definition at line 940 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::ErrorCode, __JPEG_HandleTypeDef::GetDataCallback, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_STATE_READY, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | pJPEG_InfoReadyCallbackTypeDef | pCallback
 | ) |  |

Register Info Ready JPEG Callback To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback.

Parameters:
hjpeg | JPEG handle
pCallback | pointer to the Info Ready Callback function
Return values:
HAL status

Definition at line 872 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InfoReadyCallback, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | HAL_JPEG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a JPEG Callback JPEG callabck is redirected to the weak predefined callback.

Parameters:
hjpeg JPEG handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
  • HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
  • HAL_JPEG_ERROR_CB_ID Error callback ID
  • HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
  • HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 793 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_DECODE_CPLT_CB_ID, HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_ENCODE_CPLT_CB_ID, HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_ERROR_CB_ID, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_ErrorCallback(), HAL_JPEG_MspDeInit(), HAL_JPEG_MSPDEINIT_CB_ID, HAL_JPEG_MspInit(), HAL_JPEG_MSPINIT_CB_ID, HAL_JPEG_STATE_READY, HAL_JPEG_STATE_RESET, __JPEG_HandleTypeDef::MspDeInitCallback, __JPEG_HandleTypeDef::MspInitCallback, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback ( JPEG_HandleTypeDef * hjpeg )

UnRegister the Data Ready JPEG Callback Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback.

Parameters:
hjpeg JPEG handle
Return values:
HAL status

Definition at line 1044 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_DataReadyCallback(), HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_STATE_READY, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback ( JPEG_HandleTypeDef * hjpeg )

UnRegister the Get Data JPEG Callback Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback.

Parameters:
hjpeg JPEG handle
Return values:
HAL status

Definition at line 976 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::ErrorCode, __JPEG_HandleTypeDef::GetDataCallback, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_GetDataCallback(), HAL_JPEG_STATE_READY, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback ( JPEG_HandleTypeDef * hjpeg )

UnRegister the Info Ready JPEG Callback Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback.

Parameters:
hjpeg JPEG handle
Return values:
HAL status

Definition at line 909 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_INVALID_CALLBACK, HAL_JPEG_InfoReadyCallback(), HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InfoReadyCallback, and __JPEG_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: Configuration functions

Functions
Configuration functions
JPEG Exported Functions

JPEG Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.

Detailed Description

JPEG Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
      (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding
      (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding
      (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
      (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.

Function Documentation

HAL_StatusTypeDef HAL_JPEG_ConfigEncoding | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pConf
 | ) |  |

Set the JPEG encoding configuration.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pConf | pointer to a JPEG_ConfTypeDef structure that contains the encoding configuration
Return values:
HAL status

Definition at line 1100 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_ConfTypeDef::ChromaSubsampling, JPEG_ConfTypeDef::ColorSpace, __JPEG_HandleTypeDef::Conf, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_QUANT_TABLE, HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_ConfTypeDef::ImageHeight, JPEG_ConfTypeDef::ImageQuality, JPEG_ConfTypeDef::ImageWidth, __JPEG_HandleTypeDef::Instance, IS_JPEG_CHROMASUBSAMPLING, IS_JPEG_COLORSPACE, IS_JPEG_IMAGE_QUALITY, JPEG_420_SUBSAMPLING, JPEG_422_SUBSAMPLING, JPEG_444_SUBSAMPLING, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_GRAYSCALE_COLORSPACE, JPEG_Set_Quantization_Mem(), JPEG_SetColorCMYK(), JPEG_SetColorGrayScale(), JPEG_SetColorYCBCR(), JPEG_YCBCR_COLORSPACE, __JPEG_HandleTypeDef::QuantTable0, __JPEG_HandleTypeDef::QuantTable1, __JPEG_HandleTypeDef::QuantTable2, __JPEG_HandleTypeDef::QuantTable3, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing ( JPEG_HandleTypeDef * hjpeg )

Disable JPEG Header parsing for decoding.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the JPEG.
Return values:
HAL status

Definition at line 1393 of file stm32h7xx_hal_jpeg.c.

References HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::Instance, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing ( JPEG_HandleTypeDef * hjpeg )

Enable JPEG Header parsing for decoding.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the JPEG.
Return values:
HAL status

Definition at line 1357 of file stm32h7xx_hal_jpeg.c.

References HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::Instance, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_GetInfo | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pInfo
 | ) |  |

Extract the image configuration from the JPEG header during the decoding.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pInfo | pointer to a JPEG_ConfTypeDef structure that contains The JPEG decoded header informations
Return values:
HAL status

Definition at line 1286 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, JPEG_ConfTypeDef::ColorSpace, JPEG_ConfTypeDef::ImageHeight, JPEG_ConfTypeDef::ImageQuality, JPEG_ConfTypeDef::ImageWidth, __JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, JPEG_422_SUBSAMPLING, JPEG_444_SUBSAMPLING, JPEG_CMYK_COLORSPACE, JPEG_GetQuality(), JPEG_GRAYSCALE_COLORSPACE, and JPEG_YCBCR_COLORSPACE.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_Process().

HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | QTable0,
 |  | uint8_t * | QTable1,
 |  | uint8_t * | QTable2,
 |  | uint8_t * | QTable3
 | ) |  |

Modify the default Quantization tables used for JPEG encoding.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
QTable0 | pointer to uint8_t , define the user quantification table for color component 1. If NULL assume no need to update the table and no error return
QTable1 | pointer to uint8_t , define the user quantification table for color component 2. If NULL assume no need to update the table and no error return.
QTable2 | pointer to uint8_t , define the user quantification table for color component 3, If NULL assume no need to update the table and no error return.
QTable3 | pointer to uint8_t , define the user quantification table for color component 4. If NULL assume no need to update the table and no error return.
Return values:
HAL status

Definition at line 1440 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_CONTEXT_CUSTOM_TABLES, __JPEG_HandleTypeDef::QuantTable0, __JPEG_HandleTypeDef::QuantTable1, __JPEG_HandleTypeDef::QuantTable2, __JPEG_HandleTypeDef::QuantTable3, and __JPEG_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: encoding/decoding processing functions

Functions
encoding/decoding processing functions
JPEG Exported Functions

processing functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.

Detailed Description

processing functions.

  ==============================================================================
                      ##### JPEG processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_JPEG_Encode()     : JPEG encoding with polling process
      (+) HAL_JPEG_Decode()     : JPEG decoding with polling process
      (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process
      (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process
      (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
      (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
      (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing
      (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing
      (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer
      (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
      (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding

Function Documentation

HAL_StatusTypeDef HAL_JPEG_Abort ( JPEG_HandleTypeDef * hjpeg )

Aborts the JPEG Encoding/Decoding.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 2193 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, __MDMA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_DMA, HAL_JPEG_ERROR_NONE, HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_ERROR, HAL_JPEG_STATE_READY, HAL_MDMA_Abort(), HAL_MDMA_ERROR_TIMEOUT, __JPEG_HandleTypeDef::hdmain, __JPEG_HandleTypeDef::hdmaout, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_ALL, JPEG_FLAG_COF, JPEG_INTERRUPT_MASK, JPEG_TIMEOUT_VALUE, __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, and __JPEG_HandleTypeDef::State.

void HAL_JPEG_ConfigInputBuffer | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pNewInputBuffer,
 |  | uint32_t | InDataLength
 | ) |  |

Config Encoding/Decoding Input Buffer.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module.
pNewInputBuffer | Pointer to the new input data buffer
InDataLength | Size in bytes of the new Input data buffer
Return values:
HAL status

Definition at line 2167 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::InDataLength, and __JPEG_HandleTypeDef::pJpegInBuffPtr.

void HAL_JPEG_ConfigOutputBuffer | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pNewOutputBuffer,
 |  | uint32_t | OutDataLength
 | ) |  |

Config Encoding/Decoding Output Buffer.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module.
pNewOutputBuffer | Pointer to the new output data buffer
OutDataLength | Size in bytes of the new Output data buffer
Return values:
HAL status

Definition at line 2181 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::OutDataLength, and __JPEG_HandleTypeDef::pJpegOutBuffPtr.

HAL_StatusTypeDef HAL_JPEG_Decode | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength,
 |  | uint32_t | Timeout
 | ) |  |

Starts JPEG decoding with polling processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn | Pointer to the input data buffer
InDataLength | size in bytes Input buffer
pDataOutMCU | Pointer to the Output data buffer
OutDataLength | size in bytes of the Output buffer
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1619 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_POLLING, JPEG_Init_Process(), JPEG_Process(), JPEG_PROCESS_ONGOING, __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Decode_DMA | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG decoding with DMA processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn | Pointer to the input data buffer
InDataLength | size in bytes Input buffer
pDataOutMCU | Pointer to the Output data buffer
OutDataLength | size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1924 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_ERROR, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_StartProcess(), JPEG_Init_Process(), __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Decode_IT | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG decoding with interrupt processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn | Pointer to the input data buffer
InDataLength | size in bytes Input buffer
pDataOutMCU | Pointer to the Output data buffer
OutDataLength | size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1783 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_Init_Process(), __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength,
 |  | uint32_t | Timeout
 | ) |  |

Starts JPEG encoding with polling processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU | Pointer to the Input buffer
InDataLength | size in bytes Input buffer
pDataOut | Pointer to the jpeg output data buffer
OutDataLength | size in bytes of the Output buffer
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1515 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_POLLING, JPEG_Init_Process(), JPEG_Process(), JPEG_PROCESS_ONGOING, __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode_DMA | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG encoding with DMA processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU | Pointer to the Input buffer
InDataLength | size in bytes Input buffer
pDataOut | Pointer to the jpeg output data buffer
OutDataLength | size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1843 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_ERROR, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_StartProcess(), JPEG_Init_Process(), __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode_IT | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG encoding with interrupt processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU | Pointer to the Input buffer
InDataLength | size in bytes Input buffer
pDataOut | Pointer to the jpeg output data buffer
OutDataLength | size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1713 of file stm32h7xx_hal_jpeg.c.

References assert_param, __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_Init_Process(), __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Pause | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | XferSelection
 | ) |  |

Pause the JPEG Input/Output processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
XferSelection | This parameter can be one of the following values : JPEG_PAUSE_RESUME_INPUT : Pause Input processing JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
Return values:
HAL status

Definition at line 1994 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, assert_param, __JPEG_HandleTypeDef::Context, IS_JPEG_PAUSE_RESUME_STATE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_IT_EOC, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, JPEG_IT_OFT, JPEG_PAUSE_RESUME_INPUT, and JPEG_PAUSE_RESUME_OUTPUT.

Referenced by JPEG_ReadInputData().

HAL_StatusTypeDef HAL_JPEG_Resume | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | XferSelection
 | ) |  |

Resume the JPEG Input/Output processing.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
XferSelection | This parameter can be one of the following values : JPEG_PAUSE_RESUME_INPUT : Resume Input processing JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
Return values:
HAL status

Definition at line 2047 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_ENABLE_IT, assert_param, MDMA_InitTypeDef::BufferTransferLength, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_DMA, HAL_JPEG_STATE_ERROR, HAL_MDMA_Start_IT(), __JPEG_HandleTypeDef::hdmain, __JPEG_HandleTypeDef::hdmaout, __JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, __JPEG_HandleTypeDef::Instance, IS_JPEG_PAUSE_RESUME_STATE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_DMA_PollResidualData(), JPEG_IT_EOC, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, JPEG_IT_OFT, JPEG_PAUSE_RESUME_INPUT, JPEG_PAUSE_RESUME_OUTPUT, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: JPEG Decode/Encode callback functions

Functions
JPEG Decode/Encode callback functions
JPEG Exported Functions

JPEG process callback functions. More...

Functions

__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.

Detailed Description

JPEG process callback functions.

  ==============================================================================
              #####  JPEG Decode and Encode callback functions  #####
  ==============================================================================
    [..]  This section provides callback functions:
      (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback
      (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
      (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
      (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.
      (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback.
      (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback.

Function Documentation

void HAL_JPEG_DataReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Decoded/Encoded Data ready callback.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataOut | pointer to the output data buffer
OutDataLength | number in bytes of data available in the specified output buffer
Return values:
None

Definition at line 2397 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterDataReadyCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

void HAL_JPEG_DecodeCpltCallback ( JPEG_HandleTypeDef * hjpeg )

Decoding complete callback.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2345 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void HAL_JPEG_EncodeCpltCallback ( JPEG_HandleTypeDef * hjpeg )

Encoding complete callback.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2329 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void HAL_JPEG_ErrorCallback ( JPEG_HandleTypeDef * hjpeg )

JPEG error callback.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2361 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterCallback(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

void HAL_JPEG_GetDataCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | NbDecodedData
 | ) |  |

Get New Data chunk callback.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
NbDecodedData | Number of consummed data in the previous chunk in bytes
Return values:
None

Definition at line 2378 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterGetDataCallback(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

void HAL_JPEG_InfoReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pInfo
 | ) |  |

Decoding JPEG Info ready callback.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pInfo | pointer to a JPEG_ConfTypeDef structure that contains The JPEG decoded header informations
Return values:
None

Definition at line 2312 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), HAL_JPEG_UnRegisterInfoReadyCallback(), JPEG_DMA_ContinueProcess(), and JPEG_Process().

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STM32H7B3xQ HAL User Manual: JPEG IRQ handler management

Functions
JPEG IRQ handler management
JPEG Exported Functions

JPEG IRQ handler. More...

Functions

void HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.

Detailed Description

JPEG IRQ handler.

  ==============================================================================
                ##### JPEG IRQ handler management #####
  ==============================================================================
    [..]  This section provides JPEG IRQ handler function.
      (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request

Function Documentation

void HAL_JPEG_IRQHandler ( JPEG_HandleTypeDef * hjpeg )

This function handles JPEG interrupt request.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2434 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_BUSY_ENCODING, JPEG_CONTEXT_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_DMA_ContinueProcess(), JPEG_Process(), and __JPEG_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
JPEG Exported Functions

Peripheral State functions. More...

Functions

HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Detailed Description

Peripheral State functions.

  ==============================================================================
                    ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]  This section provides JPEG State and Errors function.
      (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.
      (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.

Function Documentation

uint32_t HAL_JPEG_GetError ( JPEG_HandleTypeDef * hjpeg )

Return the JPEG error code.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the specified JPEG.
Return values:
JPEG Error Code

Definition at line 2497 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::ErrorCode.

HAL_JPEG_STATETypeDef HAL_JPEG_GetState ( JPEG_HandleTypeDef * hjpeg )

Returns the JPEG state.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG state

Definition at line 2486 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: JPEG_ConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_ConfTypeDef Struct Reference
JPEG Configuration for encoding Structure definition

#include <stm32h7xx_hal_jpeg.h>

Data Fields

uint32_t | ColorSpace
uint32_t | ChromaSubsampling
uint32_t | ImageHeight
uint32_t | ImageWidth
uint32_t | ImageQuality

Detailed Description

Definition at line 50 of file stm32h7xx_hal_jpeg.h.

Field Documentation

uint32_t JPEG_ConfTypeDef::ChromaSubsampling

Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 This parameter can be a value of JPEG Chrominance Sampling

Definition at line 55 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

uint32_t JPEG_ConfTypeDef::ColorSpace

Image Color space : gray-scale, YCBCR, RGB or CMYK This parameter can be a value of JPEG ColorSpace

Definition at line 52 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

uint32_t JPEG_ConfTypeDef::ImageHeight

Image height : number of lines

Definition at line 58 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

uint32_t JPEG_ConfTypeDef::ImageQuality

Quality of the JPEG encoding : from 1 to 100

Definition at line 62 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_DMA_ContinueProcess(), JPEG_Process(), and JPEG_Set_Quantization_Mem().

uint32_t JPEG_ConfTypeDef::ImageWidth

Image width : number of pixels per line

Definition at line 60 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.h
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STM32H7B3xQ HAL User Manual: HAL JPEG state structure definition

Enumerations
HAL JPEG state structure definition
JPEG Exported Types

HAL JPEG State structure definition. More...

Enumerations

enum HAL_JPEG_STATETypeDef {
HAL_JPEG_STATE_RESET = 0x00U, HAL_JPEG_STATE_READY = 0x01U, HAL_JPEG_STATE_BUSY = 0x02U, HAL_JPEG_STATE_BUSY_ENCODING = 0x03U,
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, HAL_JPEG_STATE_TIMEOUT = 0x05U, HAL_JPEG_STATE_ERROR = 0x06U
}

Detailed Description

HAL JPEG State structure definition.

Enumeration Type Documentation

enum HAL_JPEG_STATETypeDef
Enumerator:
HAL_JPEG_STATE_RESET

JPEG not yet initialized or disabled

HAL_JPEG_STATE_READY

JPEG initialized and ready for use

HAL_JPEG_STATE_BUSY

JPEG internal processing is ongoing

HAL_JPEG_STATE_BUSY_ENCODING

JPEG encoding processing is ongoing

HAL_JPEG_STATE_BUSY_DECODING

JPEG decoding processing is ongoing

HAL_JPEG_STATE_TIMEOUT

JPEG timeout state

HAL_JPEG_STATE_ERROR

JPEG error state

Definition at line 73 of file stm32h7xx_hal_jpeg.h.

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STM32H7B3xQ HAL User Manual: JPEG handle Structure definition

Data Structures | Typedefs
JPEG handle Structure definition
JPEG Exported Types

JPEG handle Structure definition. More...

Data Structures

struct | __JPEG_HandleTypeDef

Typedefs

typedef struct __JPEG_HandleTypeDef | JPEG_HandleTypeDef

Detailed Description

JPEG handle Structure definition.

Typedef Documentation

typedef struct __JPEG_HandleTypeDef JPEG_HandleTypeDef
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STM32H7B3xQ HAL User Manual: __JPEG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__JPEG_HandleTypeDef Struct Reference
JPEG handle Structure definition

#include <stm32h7xx_hal_jpeg.h>

Data Fields

JPEG_TypeDef * | Instance
JPEG_ConfTypeDef Conf
uint8_t * | pJpegInBuffPtr
uint8_t * | pJpegOutBuffPtr
__IO uint32_t | JpegInCount
__IO uint32_t | JpegOutCount
uint32_t | InDataLength
uint32_t | OutDataLength
MDMA_HandleTypeDef * hdmain
MDMA_HandleTypeDef * hdmaout
uint8_t | CustomQuanTable
uint8_t * | QuantTable0
uint8_t * | QuantTable1
uint8_t * | QuantTable2
uint8_t * | QuantTable3
HAL_LockTypeDef | Lock
__IO HAL_JPEG_STATETypeDef | State
__IO uint32_t | ErrorCode
__IO uint32_t | Context
void(* | InfoReadyCallback )(struct __JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
void(* | EncodeCpltCallback )(struct __JPEG_HandleTypeDef *hjpeg)
void(* | DecodeCpltCallback )(struct __JPEG_HandleTypeDef *hjpeg)
void(* | ErrorCallback )(struct __JPEG_HandleTypeDef *hjpeg)
void(* | GetDataCallback )(struct __JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
void(* | DataReadyCallback )(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
void(* | MspInitCallback )(struct __JPEG_HandleTypeDef *hjpeg)
void(* | MspDeInitCallback )(struct __JPEG_HandleTypeDef *hjpeg)

Detailed Description

Definition at line 94 of file stm32h7xx_hal_jpeg.h.

Field Documentation

JPEG_ConfTypeDef __JPEG_HandleTypeDef::Conf

Current JPEG encoding/decoding parameters

Definition at line 101 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), JPEG_DMA_ContinueProcess(), JPEG_Process(), JPEG_Set_Quantization_Mem(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

__IO uint32_t __JPEG_HandleTypeDef::Context

JPEG Internal context

Definition at line 135 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), HAL_JPEG_SetUserQuantTables(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_ReadInputData().

uint8_t __JPEG_HandleTypeDef::CustomQuanTable

If set to 1 specify that user customized quantization tables are used

Definition at line 119 of file stm32h7xx_hal_jpeg.h.

void(* __JPEG_HandleTypeDef::DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)

JPEG Data ready callback

Definition at line 148 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterDataReadyCallback(), HAL_JPEG_UnRegisterDataReadyCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

void(* __JPEG_HandleTypeDef::DecodeCpltCallback)(struct __JPEG_HandleTypeDef *hjpeg)

JPEG Decode complete callback

Definition at line 142 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterCallback(), HAL_JPEG_UnRegisterCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void(* __JPEG_HandleTypeDef::EncodeCpltCallback)(struct __JPEG_HandleTypeDef *hjpeg)

JPEG Encode complete callback

Definition at line 140 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterCallback(), HAL_JPEG_UnRegisterCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void(* __JPEG_HandleTypeDef::ErrorCallback)(struct __JPEG_HandleTypeDef *hjpeg)

JPEG Error callback

Definition at line 144 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterCallback(), HAL_JPEG_UnRegisterCallback(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

__IO uint32_t __JPEG_HandleTypeDef::ErrorCode

JPEG Error code

Definition at line 133 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_GetError(), HAL_JPEG_Init(), HAL_JPEG_RegisterCallback(), HAL_JPEG_RegisterDataReadyCallback(), HAL_JPEG_RegisterGetDataCallback(), HAL_JPEG_RegisterInfoReadyCallback(), HAL_JPEG_Resume(), HAL_JPEG_UnRegisterCallback(), HAL_JPEG_UnRegisterDataReadyCallback(), HAL_JPEG_UnRegisterGetDataCallback(), HAL_JPEG_UnRegisterInfoReadyCallback(), JPEG_DMA_StartProcess(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

void(* __JPEG_HandleTypeDef::GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)

JPEG Get Data callback

Definition at line 146 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterGetDataCallback(), HAL_JPEG_UnRegisterGetDataCallback(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

MDMA_HandleTypeDef* __JPEG_HandleTypeDef::hdmain

JPEG In MDMA handle parameters

Definition at line 115 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_StartProcess(), and JPEG_MDMAInCpltCallback().

MDMA_HandleTypeDef* __JPEG_HandleTypeDef::hdmaout

JPEG Out MDMA handle parameters

Definition at line 117 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_StartProcess(), and JPEG_MDMAOutCpltCallback().

uint32_t __JPEG_HandleTypeDef::InDataLength

Input Buffer Length in Bytes

Definition at line 111 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigInputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

void(* __JPEG_HandleTypeDef::InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)

JPEG Info ready callback

Definition at line 138 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterInfoReadyCallback(), HAL_JPEG_UnRegisterInfoReadyCallback(), JPEG_DMA_ContinueProcess(), and JPEG_Process().

JPEG_TypeDef* __JPEG_HandleTypeDef::Instance

JPEG peripheral register base address

Definition at line 99 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_DisableHeaderParsing(), HAL_JPEG_EnableHeaderParsing(), HAL_JPEG_GetInfo(), HAL_JPEG_Init(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_GetQuality(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), JPEG_ReadInputData(), JPEG_Set_Huff_DHTMem(), JPEG_Set_HuffAC_Mem(), JPEG_Set_HuffDC_Mem(), JPEG_Set_HuffEnc_Mem(), JPEG_SetColorCMYK(), JPEG_SetColorGrayScale(), JPEG_SetColorYCBCR(), and JPEG_StoreOutputData().

__IO uint32_t __JPEG_HandleTypeDef::JpegInCount

Internal Counter of input data

Definition at line 107 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

__IO uint32_t __JPEG_HandleTypeDef::JpegOutCount

Internal Counter of output data

Definition at line 109 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

HAL_LockTypeDef __JPEG_HandleTypeDef::Lock

JPEG locking object

Definition at line 129 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

void(* __JPEG_HandleTypeDef::MspDeInitCallback)(struct __JPEG_HandleTypeDef *hjpeg)

JPEG Msp DeInit callback

Definition at line 152 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_DeInit(), HAL_JPEG_RegisterCallback(), and HAL_JPEG_UnRegisterCallback().

void(* __JPEG_HandleTypeDef::MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg)

JPEG Msp Init callback

Definition at line 151 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), HAL_JPEG_RegisterCallback(), and HAL_JPEG_UnRegisterCallback().

uint32_t __JPEG_HandleTypeDef::OutDataLength

Output Buffer Length in Bytes

Definition at line 113 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigOutputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_MDMAOutCpltCallback(), and JPEG_StoreOutputData().

uint8_t* __JPEG_HandleTypeDef::pJpegInBuffPtr

Pointer to JPEG processing (encoding, decoding,...) input buffer

Definition at line 103 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigInputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

uint8_t* __JPEG_HandleTypeDef::pJpegOutBuffPtr

Pointer to JPEG processing (encoding, decoding,...) output buffer

Definition at line 105 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigOutputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

uint8_t* __JPEG_HandleTypeDef::QuantTable0

Basic Quantization Table for component 0

Definition at line 121 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), HAL_JPEG_SetUserQuantTables(), and JPEG_GetQuality().

uint8_t* __JPEG_HandleTypeDef::QuantTable1

Basic Quantization Table for component 1

Definition at line 123 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

uint8_t* __JPEG_HandleTypeDef::QuantTable2

Basic Quantization Table for component 2

Definition at line 125 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

uint8_t* __JPEG_HandleTypeDef::QuantTable3

Basic Quantization Table for component 3

Definition at line 127 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

__IO HAL_JPEG_STATETypeDef __JPEG_HandleTypeDef::State

JPEG peripheral state

Definition at line 131 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_DisableHeaderParsing(), HAL_JPEG_EnableHeaderParsing(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_GetState(), HAL_JPEG_Init(), HAL_JPEG_IRQHandler(), HAL_JPEG_RegisterCallback(), HAL_JPEG_RegisterDataReadyCallback(), HAL_JPEG_RegisterGetDataCallback(), HAL_JPEG_RegisterInfoReadyCallback(), HAL_JPEG_Resume(), HAL_JPEG_SetUserQuantTables(), HAL_JPEG_UnRegisterCallback(), HAL_JPEG_UnRegisterDataReadyCallback(), HAL_JPEG_UnRegisterGetDataCallback(), HAL_JPEG_UnRegisterInfoReadyCallback(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.h
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STM32H7B3xQ HAL User Manual: HAL JPEG Callback ID enumeration definition

Enumerations
HAL JPEG Callback ID enumeration definition
JPEG Exported Types

HAL JPEG Callback ID enumeration definition. More...

Enumerations

enum HAL_JPEG_CallbackIDTypeDef {
HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, HAL_JPEG_ERROR_CB_ID = 0x03U, HAL_JPEG_MSPINIT_CB_ID = 0x04U,
HAL_JPEG_MSPDEINIT_CB_ID = 0x05U
}

Detailed Description

HAL JPEG Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_JPEG_CallbackIDTypeDef
Enumerator:
HAL_JPEG_ENCODE_CPLT_CB_ID

JPEG Encode Complete callback ID

HAL_JPEG_DECODE_CPLT_CB_ID

JPEG Decode Complete callback ID

HAL_JPEG_ERROR_CB_ID

JPEG Error callback ID

HAL_JPEG_MSPINIT_CB_ID

JPEG MspInit callback ID

HAL_JPEG_MSPDEINIT_CB_ID

JPEG MspDeInit callback ID

Definition at line 170 of file stm32h7xx_hal_jpeg.h.

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STM32H7B3xQ HAL User Manual: HAL JPEG Callback pointer definition

Typedefs
HAL JPEG Callback pointer definition
JPEG Exported Types

HAL JPEG Callback pointer definition. More...

Typedefs

typedef void(* | pJPEG_CallbackTypeDef )(JPEG_HandleTypeDef *hjpeg)
typedef void(* | pJPEG_InfoReadyCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
typedef void(* | pJPEG_GetDataCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
typedef void(* | pJPEG_DataReadyCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)

Detailed Description

HAL JPEG Callback pointer definition.

Typedef Documentation

typedef void(* pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg)

pointer to a common JPEG callback function

Definition at line 188 of file stm32h7xx_hal_jpeg.h.

typedef void(* pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)

pointer to a Data ready JPEG callback function

Definition at line 193 of file stm32h7xx_hal_jpeg.h.

typedef void(* pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)

pointer to a Get data JPEG callback function

Definition at line 191 of file stm32h7xx_hal_jpeg.h.

typedef void(* pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)

pointer to an Info ready JPEG callback function

Definition at line 189 of file stm32h7xx_hal_jpeg.h.

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STM32H7B3xQ HAL User Manual: JPEG Error Code definition

Defines
JPEG Error Code definition
JPEG Exported Constants

JPEG Error Code definition. More...

Defines

#define | HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)
#define | HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)
#define | HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)
#define | HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)

Detailed Description

JPEG Error Code definition.

Define Documentation

#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)

DMA transfer error

Definition at line 219 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_StartProcess(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)

HUffman Table programming error

Definition at line 217 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)

Invalid Callback error

Definition at line 222 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_RegisterCallback(), HAL_JPEG_RegisterDataReadyCallback(), HAL_JPEG_RegisterGetDataCallback(), HAL_JPEG_RegisterInfoReadyCallback(), HAL_JPEG_UnRegisterCallback(), HAL_JPEG_UnRegisterDataReadyCallback(), HAL_JPEG_UnRegisterGetDataCallback(), and HAL_JPEG_UnRegisterInfoReadyCallback().

#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 216 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_DeInit(), and HAL_JPEG_Init().

#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)

Quantization Table programming error

Definition at line 218 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)

Timeout error

Definition at line 220 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), and HAL_JPEG_Encode().

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STM32H7B3xQ HAL User Manual: JPEG Quantization Table Size

Defines
JPEG Quantization Table Size
JPEG Exported Constants

JPEG Quantization Table Size. More...

Defines

#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)

Detailed Description

JPEG Quantization Table Size.

Define Documentation

#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)

JPEG Quantization Table Size in bytes

Definition at line 232 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init(), JPEG_GetQuality(), and JPEG_Set_Quantization_Mem().

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STM32H7B3xQ HAL User Manual: JPEG ColorSpace

Defines
JPEG ColorSpace
JPEG Exported Constants

JPEG Color Space. More...

Defines

#define | JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define | JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define | JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE

Detailed Description

JPEG Color Space.

Define Documentation

#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE

Definition at line 244 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_GetInfo().

#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)

Definition at line 242 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0

Definition at line 243 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

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STM32H7B3xQ HAL User Manual: JPEG Chrominance Sampling

Defines
JPEG Chrominance Sampling
JPEG Exported Constants

JPEG Chrominance Sampling. More...

Defines

#define | JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)
#define | JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)
#define | JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)

Detailed Description

JPEG Chrominance Sampling.

Define Documentation

#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)

Chroma Subsampling 4:2:0

Definition at line 257 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)

Chroma Subsampling 4:2:2

Definition at line 258 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)

Chroma Subsampling 4:4:4

Definition at line 256 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

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STM32H7B3xQ HAL User Manual: JPEG Image Quality

Defines
JPEG Image Quality
JPEG Exported Constants

JPEG Min and Max Image Quality. More...

Defines

#define | JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)
#define | JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)

Detailed Description

JPEG Min and Max Image Quality.

Define Documentation

#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)

Maximum JPEG quality

Definition at line 269 of file stm32h7xx_hal_jpeg.h.

#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)

Minimum JPEG quality

Definition at line 268 of file stm32h7xx_hal_jpeg.h.

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STM32H7B3xQ HAL User Manual: JPEG Interrupt configuration definition

Defines
JPEG Interrupt configuration definition
JPEG Exported Constants

JPEG Interrupt definition. More...

Defines

#define | JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)
#define | JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)
#define | JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)
#define | JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)

Detailed Description

JPEG Interrupt definition.

Define Documentation

#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)

End of Conversion Interrupt

Definition at line 283 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)

Header Parsing Done Interrupt

Definition at line 284 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)

Input FIFO Not Full Interrupt

Definition at line 280 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)

Input FIFO Threshold Interrupt

Definition at line 279 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)

Output FIFO Not Empty Interrupt

Definition at line 282 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)

Output FIFO Threshold Interrupt

Definition at line 281 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

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STM32H7B3xQ HAL User Manual: JPEG Flag definition

Defines
JPEG Flag definition
JPEG Exported Constants

JPEG Flags definition. More...

Defines

#define | JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)
#define | JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)
#define | JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)
#define | JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)
#define | JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)
#define | JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)
#define | JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)
#define | JPEG_FLAG_ALL ((uint32_t)0x000000FEU)

Detailed Description

JPEG Flags definition.

Define Documentation

#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU)

JPEG Codec All previous flag

Definition at line 301 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)

JPEG Codec operation on going flag

Definition at line 299 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort().

#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)

JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO

Definition at line 297 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)

JPEG Codec has finished the parsing of the headers and the internal registers have been updated

Definition at line 298 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_Process().

#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)

Input FIFO Not Full Flag, a data can be written

Definition at line 294 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)

Input FIFO is not full and is bellow its threshold flag

Definition at line 293 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)

Output FIFO is not empty, a data is available

Definition at line 296 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)

Output FIFO is not empty and has reach its threshold

Definition at line 295 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Process Pause Resume definition

Defines
JPEG Process Pause Resume definition
JPEG Exported Constants

JPEG process pause, resume definition. More...

Defines

#define | JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)
#define | JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)
#define | JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)

Detailed Description

JPEG process pause, resume definition.

Define Documentation

#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)

Pause/Resume Input FIFO Xfer

Definition at line 310 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_ReadInputData().

#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)

Pause/Resume Input and Output FIFO Xfer

Definition at line 312 of file stm32h7xx_hal_jpeg.h.

#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)

Pause/Resume Output FIFO Xfer

Definition at line 311 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), and HAL_JPEG_Resume().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Exported Macros

Defines
JPEG Exported Macros
JPEG

Defines

#define | __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__)
Reset JPEG handle state.
#define | __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
Enable the JPEG peripheral.
#define | __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
Disable the JPEG peripheral.
#define | __HAL_JPEG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
Check the specified JPEG status flag.
#define | __HAL_JPEG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
Clear the specified JPEG status flag.
#define | __HAL_JPEG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
Enable Interrupt.
#define | __HAL_JPEG_DISABLE_IT(__HANDLE__, __INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
Disable Interrupt.
#define | __HAL_JPEG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Get Interrupt state.

Define Documentation

#define __HAL_JPEG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))

Clear the specified JPEG status flag.

Parameters:
__HANDLE__ specifies the JPEG handle.
__FLAG__ specifies the flag to clear This parameter can be one of the following values:
  • JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO
  • JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
Return values:
None

Definition at line 387 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), and JPEG_Process().

#define __HAL_JPEG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)

Disable the JPEG peripheral.

Parameters:
__HANDLE__ specifies the JPEG handle.
Return values:
None

Definition at line 353 of file stm32h7xx_hal_jpeg.h.

#define __HAL_JPEG_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)

Disable Interrupt.

Parameters:
__HANDLE__ specifies the JPEG handle.
__INTERRUPT__ specifies the interrupt to disable This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Note:
To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits located in the same IT enable register (CR register).
Return values:
No retrun

Definition at line 422 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), HAL_JPEG_Pause(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define __HAL_JPEG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)

Enable the JPEG peripheral.

Parameters:
__HANDLE__ specifies the JPEG handle.
Return values:
None

Definition at line 346 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

#define __HAL_JPEG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )

Enable Interrupt.

Parameters:
__HANDLE__ specifies the JPEG handle.
__INTERRUPT__ specifies the interrupt to enable This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Return values:
No retrun

Definition at line 404 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define __HAL_JPEG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)))

Check the specified JPEG status flag.

Parameters:
__HANDLE__ specifies the JPEG handle.
__FLAG__ specifies the flag to check This parameter can be one of the following values:
  • JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
  • JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
  • JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
  • JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
  • JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO
  • JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers and the internal registers have been updated
  • JPEG_FLAG_COF : JPEG Codec operation on going flag
Return values:
__HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)

Definition at line 374 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define __HAL_JPEG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Get Interrupt state.

Parameters:
__HANDLE__ specifies the JPEG handle.
__INTERRUPT__ specifies the interrupt to check This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Return values:
returns The new state of __INTERRUPT__ (Enabled or disabled)

Definition at line 439 of file stm32h7xx_hal_jpeg.h.

#define __HAL_JPEG_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                      }while(0)

Reset JPEG handle state.

Parameters:
__HANDLE__ specifies the JPEG handle.
Return values:
None

Definition at line 331 of file stm32h7xx_hal_jpeg.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG_ACHuffTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_ACHuffTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | Bits [16]
uint8_t | HuffVal [162]

Detailed Description

Definition at line 283 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_ACHuffTableTypeDef::Bits[16]

bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C

Definition at line 286 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

uint8_t JPEG_ACHuffTableTypeDef::HuffVal[162]

The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C

Definition at line 288 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG_DCHuffTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_DCHuffTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | Bits [16]
uint8_t | HuffVal [12]

Detailed Description

Definition at line 293 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_DCHuffTableTypeDef::Bits[16]

bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C

Definition at line 296 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

uint8_t JPEG_DCHuffTableTypeDef::HuffVal[12]

The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C

Definition at line 298 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG_AC_HuffCodeTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_AC_HuffCodeTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | CodeLength [JPEG_AC_HUFF_TABLE_SIZE]
uint32_t | HuffmanCode [JPEG_AC_HUFF_TABLE_SIZE]

Detailed Description

Definition at line 303 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_AC_HuffCodeTableTypeDef::CodeLength[JPEG_AC_HUFF_TABLE_SIZE]

Code length

Definition at line 305 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

uint32_t JPEG_AC_HuffCodeTableTypeDef::HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]

HuffmanCode

Definition at line 307 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG_DC_HuffCodeTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_DC_HuffCodeTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | CodeLength [JPEG_DC_HUFF_TABLE_SIZE]
uint32_t | HuffmanCode [JPEG_DC_HUFF_TABLE_SIZE]

Detailed Description

Definition at line 311 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_DC_HuffCodeTableTypeDef::CodeLength[JPEG_DC_HUFF_TABLE_SIZE]

Code length

Definition at line 313 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

uint32_t JPEG_DC_HuffCodeTableTypeDef::HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]

HuffmanCode

Definition at line 315 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Defines

JPEG Private Defines
JPEG
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Variables

Variables
JPEG Private Variables
JPEG

Variables

static const
JPEG_DCHuffTableTypeDef 		JPEG_DCLUM_HuffTable
static const
JPEG_DCHuffTableTypeDef 		JPEG_DCCHROM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACLUM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACCHROM_HuffTable
static const uint8_t JPEG_ZIGZAG_ORDER [JPEG_QUANT_TABLE_SIZE]

Variable Documentation

const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable [static]
Initial value:
{
  { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },

  {
    0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,
    0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
    0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
    0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
    0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
    0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
    0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
    0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
    0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
    0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
    0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
    0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
    0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
    0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
    0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
    0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
    0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
    0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
    0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
    0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
    0xf9, 0xfa
  }
}

Definition at line 373 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Set_Huff_DHTMem().

const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable [static]
Initial value:
{
  { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },

  {
    0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
    0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
    0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
    0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
    0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
    0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
    0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
    0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
    0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
    0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
    0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
    0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
    0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
    0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
    0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
    0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
    0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
    0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
    0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
    0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
    0xf9, 0xfa
  }
}

Definition at line 344 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Set_Huff_DHTMem().

const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable [static]
Initial value:
{
  { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },

  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }
}

Definition at line 337 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Set_Huff_DHTMem().

const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable [static]
Initial value:
{
  { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },

  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }

}

Definition at line 329 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Set_Huff_DHTMem().

const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] [static]
Initial value:
{
  0,   1,   8,  16,   9,   2,   3,  10,
  17,  24,  32,  25,  18,  11,   4,   5,
  12,  19,  26,  33,  40,  48,  41,  34,
  27,  20,  13,   6,   7,  14,  21,  28,
  35,  42,  49,  56,  57,  50,  43,  36,
  29,  22,  15,  23,  30,  37,  44,  51,
  58,  59,  52,  45,  38,  31,  39,  46,
  53,  60,  61,  54,  47,  55,  62,  63
}

Definition at line 402 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_GetQuality(), and JPEG_Set_Quantization_Mem().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Constants

Defines
JPEG Private Constants
JPEG

Defines

#define | JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
#define | JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/
#define | JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/
#define | JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
#define | JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/
#define | JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
#define | JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/
#define | JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/
#define | JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */
#define | JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */
#define | JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */
#define | JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */
#define | JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */
#define | JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */
#define | JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */
#define | JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */
#define | JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */
#define | JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */
#define | JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */
#define | JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */

Define Documentation

#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/

Definition at line 240 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */

Definition at line 259 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */

Definition at line 264 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_SetUserQuantTables(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/

Definition at line 250 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */

Definition at line 255 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Encode_DMA(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/

Definition at line 249 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), and HAL_JPEG_Encode_IT().

#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */

Definition at line 266 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */

Definition at line 254 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode_IT(), HAL_JPEG_Encode_IT(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */

Definition at line 256 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */

Definition at line 251 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */

Definition at line 261 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_Process(), and JPEG_ReadInputData().

#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */

Definition at line 262 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */

Definition at line 253 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), and HAL_JPEG_Encode().

#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/

Definition at line 241 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/

Definition at line 243 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_PollResidualData().

#define JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/

Definition at line 245 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Process().

#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/

Definition at line 247 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */

Definition at line 269 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Process().

#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */

Definition at line 268 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Encode(), and JPEG_Process().

#define JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */

Definition at line 239 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Macros

Defines
JPEG Private Macros
JPEG

Defines

#define | IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING)
#define | IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define | IS_JPEG_COLORSPACE(COLORSPACE)
#define | IS_JPEG_PAUSE_RESUME_STATE(VALUE)

Define Documentation

#define IS_JPEG_CHROMASUBSAMPLING ( SUBSAMPLING )
Value:
(((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
                                                ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
                                                ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))

Definition at line 603 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_COLORSPACE ( COLORSPACE )
Value:
(((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
                                        ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \
                                        ((COLORSPACE) == JPEG_CMYK_COLORSPACE))

Definition at line 609 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_IMAGE_QUALITY ( NUMBER ) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))

Definition at line 607 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_PAUSE_RESUME_STATE ( VALUE )
Value:
(((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
                                           ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
                                           ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))

Definition at line 613 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), and HAL_JPEG_Resume().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Functions Prototypes

JPEG Private Functions Prototypes
JPEG
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: JPEG Private Functions

Functions
JPEG Private Functions
JPEG

Functions

static HAL_StatusTypeDef | JPEG_Bits_To_SizeCodes (uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
Generates Huffman sizes/Codes Table from Bits/vals Table.
static HAL_StatusTypeDef | JPEG_ACHuff_BitsVals_To_SizeCodes (JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_DCHuff_BitsVals_To_SizeCodes (JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_Set_HuffDC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, const __IO uint32_t *DCTableAddress)
Set the JPEG register with an DC huffman table at the given DC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffAC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, const __IO uint32_t *ACTableAddress)
Set the JPEG register with an AC huffman table at the given AC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffEnc_Mem (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG encoder register huffman tables to used during the encdoing operation.
static void | JPEG_Set_Huff_DHTMem (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)
static uint32_t | JPEG_Set_Quantization_Mem (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
Configure the JPEG registers with a given quantization table.
static void | JPEG_SetColorYCBCR (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for YCbCr color space.
static void | JPEG_SetColorGrayScale (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for GrayScale color space.
static void | JPEG_SetColorCMYK (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for CMYK color space.
static void | JPEG_Init_Process (JPEG_HandleTypeDef *hjpeg)
Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.
static uint32_t | JPEG_Process (JPEG_HandleTypeDef *hjpeg)
JPEG encoding/decoding process in case of Polling or Interrupt.
static void | JPEG_StoreOutputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
Store some output data from the JPEG peripheral to the output buffer.
static void | JPEG_ReadInputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
Read some input Data from the input buffer.
static HAL_StatusTypeDef | JPEG_DMA_StartProcess (JPEG_HandleTypeDef *hjpeg)
Start the JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_ContinueProcess (JPEG_HandleTypeDef *hjpeg)
Continue the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_EndProcess (JPEG_HandleTypeDef *hjpeg)
Finalize the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_PollResidualData (JPEG_HandleTypeDef *hjpeg)
Poll residual output data when DMA process (encoding/decoding)
static void | JPEG_MDMAInCpltCallback (MDMA_HandleTypeDef *hmdma)
MDMA input transfer complete callback.
static void | JPEG_MDMAOutCpltCallback (MDMA_HandleTypeDef *hmdma)
MDMA output transfer complete callback.
static void | JPEG_MDMAErrorCallback (MDMA_HandleTypeDef *hmdma)
MDMA Transfer error callback.
static void | JPEG_MDMAOutAbortCallback (MDMA_HandleTypeDef *hmdma)
MDMA output Abort callback.
static uint32_t | JPEG_GetQuality (JPEG_HandleTypeDef *hjpeg)
Calculate the decoded image quality (from 1 to 100)

Function Documentation

static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes | ( | JPEG_ACHuffTableTypeDef * | AC_BitsValsTable,
 |  | JPEG_AC_HuffCodeTableTypeDef * | AC_SizeCodesTable
 | ) |  | [static]

Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.

Parameters:
AC_BitsValsTable | pointer to AC huffman bits/vals table
AC_SizeCodesTable | pointer to AC huffman Sizes/Codes table
Return values:
HAL status

Definition at line 2582 of file stm32h7xx_hal_jpeg.c.

References JPEG_ACHuffTableTypeDef::Bits, JPEG_AC_HuffCodeTableTypeDef::CodeLength, JPEG_AC_HuffCodeTableTypeDef::HuffmanCode, JPEG_ACHuffTableTypeDef::HuffVal, JPEG_AC_HUFF_TABLE_SIZE, and JPEG_Bits_To_SizeCodes().

Referenced by JPEG_Set_HuffAC_Mem().

static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes | ( | uint8_t * | Bits,
 |  | uint8_t * | Huffsize,
 |  | uint32_t * | Huffcode,
 |  | uint32_t * | LastK
 | ) |  | [static]

Generates Huffman sizes/Codes Table from Bits/vals Table.

Parameters:
Bits | pointer to bits table
Huffsize | pointer to sizes table
Huffcode | pointer to codes table
LastK | pointer to last Coeff (table dimmension)
Return values:
HAL status

Definition at line 2523 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_DCHuff_BitsVals_To_SizeCodes().

static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes | ( | JPEG_DCHuffTableTypeDef * | DC_BitsValsTable,
 |  | JPEG_DC_HuffCodeTableTypeDef * | DC_SizeCodesTable
 | ) |  | [static]

Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.

Parameters:
DC_BitsValsTable | pointer to DC huffman bits/vals table
DC_SizeCodesTable | pointer to DC huffman Sizes/Codes table
Return values:
HAL status

Definition at line 2641 of file stm32h7xx_hal_jpeg.c.

References JPEG_DCHuffTableTypeDef::Bits, JPEG_DC_HuffCodeTableTypeDef::CodeLength, JPEG_DC_HuffCodeTableTypeDef::HuffmanCode, JPEG_DCHuffTableTypeDef::HuffVal, JPEG_Bits_To_SizeCodes(), and JPEG_DC_HUFF_TABLE_SIZE.

Referenced by JPEG_Set_HuffDC_Mem().

static void JPEG_DMA_ContinueProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Continue the current JPEG DMA process (encoding/decoding)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING

Definition at line 3702 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Conf, __JPEG_HandleTypeDef::Context, HAL_JPEG_GetInfo(), HAL_JPEG_InfoReadyCallback(), HAL_MDMA_Abort_IT(), HAL_MDMA_STATE_BUSY, __JPEG_HandleTypeDef::hdmain, __JPEG_HandleTypeDef::hdmaout, JPEG_ConfTypeDef::ImageQuality, __JPEG_HandleTypeDef::InfoReadyCallback, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_EndProcess(), JPEG_FLAG_ALL, JPEG_FLAG_EOCF, JPEG_FLAG_HPDF, JPEG_INTERRUPT_MASK, JPEG_IT_HPD, and __MDMA_HandleTypeDef::State.

Referenced by HAL_JPEG_IRQHandler().

static void JPEG_DMA_EndProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Finalize the current JPEG DMA process (encoding/decoding)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE

Definition at line 3771 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::hdmaout, __JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_DMA_PollResidualData(), JPEG_FLAG_OFNEF, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_MDMAOutAbortCallback().

static void JPEG_DMA_PollResidualData ( JPEG_HandleTypeDef * hjpeg ) [static]

Poll residual output data when DMA process (encoding/decoding)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None.

Definition at line 3851 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FIFO_SIZE, JPEG_FLAG_OFNEF, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

Referenced by HAL_JPEG_Resume(), and JPEG_DMA_EndProcess().

static HAL_StatusTypeDef JPEG_DMA_StartProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Start the JPEG DMA process (encoding/decoding)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING

Definition at line 3632 of file stm32h7xx_hal_jpeg.c.

References MDMA_InitTypeDef::BufferTransferLength, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_DMA, HAL_MDMA_Start_IT(), __JPEG_HandleTypeDef::hdmain, __JPEG_HandleTypeDef::hdmaout, __JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, __JPEG_HandleTypeDef::Instance, JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), JPEG_MDMAOutCpltCallback(), __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegInBuffPtr, __JPEG_HandleTypeDef::pJpegOutBuffPtr, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_JPEG_Decode_DMA(), and HAL_JPEG_Encode_DMA().

static uint32_t JPEG_GetQuality ( JPEG_HandleTypeDef * hjpeg ) [static]

Calculate the decoded image quality (from 1 to 100)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG image quality from 1 to 100.

Definition at line 4119 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Instance, JPEG_QUANT_TABLE_SIZE, JPEG_ZIGZAG_ORDER, and __JPEG_HandleTypeDef::QuantTable0.

Referenced by HAL_JPEG_GetInfo().

static void JPEG_Init_Process ( JPEG_HandleTypeDef * hjpeg ) [static]

Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 3255 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_ALL, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, and JPEG_IT_OFT.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), and HAL_JPEG_Encode_IT().

static void JPEG_MDMAErrorCallback ( MDMA_HandleTypeDef * hmdma ) [static]

MDMA Transfer error callback.

Parameters:
hmdma pointer to a MDMA_HandleTypeDef structure.
Return values:
None

Definition at line 4077 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_DMA, HAL_JPEG_ErrorCallback(), HAL_JPEG_STATE_READY, __JPEG_HandleTypeDef::Instance, JPEG_INTERRUPT_MASK, and __JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAInCpltCallback ( MDMA_HandleTypeDef * hmdma ) [static]

MDMA input transfer complete callback.

Parameters:
hmdma pointer to a MDMA_HandleTypeDef structure.
Return values:
None

Definition at line 3938 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, MDMA_InitTypeDef::BufferTransferLength, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, __JPEG_HandleTypeDef::GetDataCallback, HAL_JPEG_ERROR_DMA, HAL_JPEG_ErrorCallback(), HAL_JPEG_GetDataCallback(), HAL_JPEG_STATE_ERROR, HAL_MDMA_Start_IT(), __JPEG_HandleTypeDef::hdmain, __JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, __JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, __JPEG_HandleTypeDef::JpegInCount, __JPEG_HandleTypeDef::pJpegInBuffPtr, and __JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAOutAbortCallback ( MDMA_HandleTypeDef * hmdma ) [static]

MDMA output Abort callback.

Parameters:
hmdma pointer to a MDMA_HandleTypeDef structure.
Return values:
None

Definition at line 4102 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Context, JPEG_CONTEXT_ENDING_DMA, and JPEG_DMA_EndProcess().

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAOutCpltCallback ( MDMA_HandleTypeDef * hmdma ) [static]

MDMA output transfer complete callback.

Parameters:
hmdma pointer to a MDMA_HandleTypeDef structure.
Return values:
None

Definition at line 4026 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::ErrorCallback, __JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_DataReadyCallback(), HAL_JPEG_ERROR_DMA, HAL_JPEG_ErrorCallback(), HAL_JPEG_STATE_ERROR, HAL_MDMA_Start_IT(), __JPEG_HandleTypeDef::hdmaout, __JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_EOCF, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_StartProcess().

static uint32_t JPEG_Process ( JPEG_HandleTypeDef * hjpeg ) [static]

JPEG encoding/decoding process in case of Polling or Interrupt.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING

Definition at line 3310 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, __JPEG_HandleTypeDef::Conf, __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::DataReadyCallback, __JPEG_HandleTypeDef::DecodeCpltCallback, __JPEG_HandleTypeDef::EncodeCpltCallback, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_GetInfo(), HAL_JPEG_InfoReadyCallback(), HAL_JPEG_STATE_READY, JPEG_ConfTypeDef::ImageQuality, __JPEG_HandleTypeDef::InfoReadyCallback, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FIFO_TH_SIZE, JPEG_FLAG_ALL, JPEG_FLAG_EOCF, JPEG_FLAG_HPDF, JPEG_FLAG_IFNFF, JPEG_FLAG_IFTF, JPEG_FLAG_OFNEF, JPEG_FLAG_OFTF, JPEG_INTERRUPT_MASK, JPEG_IT_HPD, JPEG_PROCESS_DONE, JPEG_PROCESS_ONGOING, JPEG_ReadInputData(), JPEG_StoreOutputData(), __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::pJpegOutBuffPtr, and __JPEG_HandleTypeDef::State.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Encode(), and HAL_JPEG_IRQHandler().

static void JPEG_ReadInputData | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | nbRequestWords
 | ) |  | [static]

Read some input Data from the input buffer.

This function is used when the JPEG peripheral needs new data in case of Polling or Interrupt process

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
nbRequestWords | Number of input words (of 32 bits) that the JPE peripheral request
Return values:
None

Definition at line 3547 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Context, __JPEG_HandleTypeDef::GetDataCallback, HAL_JPEG_GetDataCallback(), HAL_JPEG_Pause(), __JPEG_HandleTypeDef::InDataLength, __JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_PAUSE_INPUT, JPEG_PAUSE_RESUME_INPUT, __JPEG_HandleTypeDef::JpegInCount, and __JPEG_HandleTypeDef::pJpegInBuffPtr.

Referenced by JPEG_Process().

static void JPEG_Set_Huff_DHTMem ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2862 of file stm32h7xx_hal_jpeg.c.

References JPEG_ACHuffTableTypeDef::Bits, JPEG_DCHuffTableTypeDef::Bits, JPEG_ACHuffTableTypeDef::HuffVal, JPEG_DCHuffTableTypeDef::HuffVal, __JPEG_HandleTypeDef::Instance, JPEG_ACCHROM_HuffTable, JPEG_ACLUM_HuffTable, JPEG_DCCHROM_HuffTable, and JPEG_DCLUM_HuffTable.

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC,
 |  | const __IO uint32_t * | ACTableAddress
 | ) |  | [static]

Set the JPEG register with an AC huffman table at the given AC table address.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableAC | pointer to AC huffman table
ACTableAddress | Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
Return values:
HAL status

Definition at line 2746 of file stm32h7xx_hal_jpeg.c.

References JPEG_AC_HuffCodeTableTypeDef::CodeLength, JPEG_AC_HuffCodeTableTypeDef::HuffmanCode, __JPEG_HandleTypeDef::Instance, JPEG_AC_HUFF_TABLE_SIZE, and JPEG_ACHuff_BitsVals_To_SizeCodes().

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC,
 |  | const __IO uint32_t * | DCTableAddress
 | ) |  | [static]

Set the JPEG register with an DC huffman table at the given DC table address.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableDC | pointer to DC huffman table
DCTableAddress | Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
Return values:
HAL status

Definition at line 2686 of file stm32h7xx_hal_jpeg.c.

References JPEG_DC_HuffCodeTableTypeDef::CodeLength, JPEG_DC_HuffCodeTableTypeDef::HuffmanCode, __JPEG_HandleTypeDef::Instance, JPEG_DC_HUFF_TABLE_SIZE, and JPEG_DCHuff_BitsVals_To_SizeCodes().

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG encoder register huffman tables to used during the encdoing operation.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2819 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Instance, JPEG_Set_Huff_DHTMem(), JPEG_Set_HuffAC_Mem(), and JPEG_Set_HuffDC_Mem().

Referenced by HAL_JPEG_Init().

static uint32_t JPEG_Set_Quantization_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | QTable,
 |  | __IO uint32_t * | QTableAddress
 | ) |  | [static]

Configure the JPEG registers with a given quantization table.

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
QTable | pointer to an array of 64 bytes giving the quantization table
QTableAddress | destination quantization address in the JPEG peripheral it could be QMEM0, QMEM1, QMEM2 or QMEM3
Return values:
0 if no error, 1 if error

Definition at line 3053 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Conf, JPEG_ConfTypeDef::ImageQuality, JPEG_QUANT_TABLE_SIZE, and JPEG_ZIGZAG_ORDER.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorCMYK ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for CMYK color space.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 3196 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, __JPEG_HandleTypeDef::Conf, __JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, and JPEG_422_SUBSAMPLING.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorGrayScale ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for GrayScale color space.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 3176 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::Instance.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorYCBCR ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for YCbCr color space.

Parameters:
hjpeg pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 3115 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, __JPEG_HandleTypeDef::Conf, __JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, and JPEG_422_SUBSAMPLING.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_StoreOutputData | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | nbOutputWords
 | ) |  | [static]

Store some output data from the JPEG peripheral to the output buffer.

This function is used when the JPEG peripheral has new data to output in case of Polling or Interrupt process

Parameters:
hjpeg | pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
nbOutputWords | Number of output words (of 32 bits) ready from the JPEG peripheral
Return values:
None

Definition at line 3456 of file stm32h7xx_hal_jpeg.c.

References __JPEG_HandleTypeDef::DataReadyCallback, HAL_JPEG_DataReadyCallback(), __JPEG_HandleTypeDef::Instance, __JPEG_HandleTypeDef::JpegOutCount, __JPEG_HandleTypeDef::OutDataLength, and __JPEG_HandleTypeDef::pJpegOutBuffPtr.

Referenced by JPEG_Process().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 352 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_GetState(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::MspDeInitCallback, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 223 of file stm32h7xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, __LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, __LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ResetCallback(), LPTIM_TRIGSOURCE_SOFTWARE, __LPTIM_HandleTypeDef::MspInitCallback, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 414 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit(), and HAL_LPTIM_UnRegisterCallback().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 399 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init(), and HAL_LPTIM_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1539 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1617 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1587 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1682 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1130 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1222 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1189 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1299 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 686 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 773 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 741 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 858 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 463 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 550 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 518 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 635 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 909 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 996 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 964 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1081 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1342 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1434 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_CMPM, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1397 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1503 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and __LPTIM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim LPTIM handle
Return values:
Autoreload value.

Definition at line 1747 of file stm32h7xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim LPTIM handle
Return values:
Compare value.

Definition at line 1760 of file stm32h7xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim LPTIM handle
Return values:
Counter value.

Definition at line 1734 of file stm32h7xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Detailed Description

LPTIM IRQ handler.

LPTIM IRQ handler and callback functions.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler:
   (+) LPTIM interrupt request handler
   (+) Compare match Callback
   (+) Auto-reload match Callback
   (+) External trigger event detection Callback
   (+) Compare register write complete Callback
   (+) Auto-reload register write complete Callback
   (+) Up-counting direction change Callback
   (+) Down-counting direction change Callback

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1941 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1986 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1926 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1971 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2016 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2001 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1799 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_LPTIM_RegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID,
 |  | pLPTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User LPTIM callback to be used instead of the weak predefined callback.

Parameters:
hlptim | LPTIM handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 2044 of file stm32h7xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1956 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Parameters:
hlptim LPTIM handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
Return values:
status

Definition at line 2151 of file stm32h7xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MspInit(), HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, HAL_LPTIM_TriggerCallback(), __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim LPTIM handle
Return values:
HAL state

Definition at line 2259 of file stm32h7xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::State.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Private Functions

Functions
LPTIM Private Functions
LPTIM | LPTIM

Functions

void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.
static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.

Function Documentation

void LPTIM_Disable ( LPTIM_HandleTypeDef * hlptim )

Disable LPTIM HW instance.

Parameters:
hlptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 2332 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPTIM3_SOURCE, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM1_FORCE_RESET, __HAL_RCC_LPTIM1_RELEASE_RESET, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPTIM2_FORCE_RESET, __HAL_RCC_LPTIM2_RELEASE_RESET, __HAL_RCC_LPTIM3_CONFIG, __HAL_RCC_LPTIM3_FORCE_RESET, __HAL_RCC_LPTIM3_RELEASE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), RCC_LPTIM1CLKSOURCE_D2PCLK1, RCC_LPTIM2CLKSOURCE_D3PCLK1, RCC_LPTIM3CLKSOURCE_D3PCLK1, and __LPTIM_HandleTypeDef::State.

static void LPTIM_ResetCallback ( LPTIM_HandleTypeDef * lptim ) [static]

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
lptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Return values:
None

Definition at line 2286 of file stm32h7xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), and __LPTIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_LPTIM_Init().

static HAL_StatusTypeDef LPTIM_WaitForFlag | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | flag
 | ) |  | [static]

LPTimer Wait for flag set.

Parameters:
hlptim | pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
flag | The lptim flag
Return values:
HAL status

Definition at line 2306 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_GET_FLAG, and TIMEOUT.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Exported Types

Data Structures | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __LPTIM_HandleTypeDef LPTIM_HandleTypeDef

LPTIM handle Structure definition.

typedef void(* pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim)

HAL TIM Callback pointer definition.

pointer to the LPTIM callback function

Definition at line 189 of file stm32h7xx_hal_lptim.h.

Enumeration Type Documentation

enum HAL_LPTIM_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_LPTIM_MSPINIT_CB_ID

LPTIM Base Msp Init Callback ID

HAL_LPTIM_MSPDEINIT_CB_ID

LPTIM Base Msp DeInit Callback ID

HAL_LPTIM_COMPARE_MATCH_CB_ID

Compare match Callback ID

HAL_LPTIM_AUTORELOAD_MATCH_CB_ID

Auto-reload match Callback ID

HAL_LPTIM_TRIGGER_CB_ID

External trigger event detection Callback ID

HAL_LPTIM_COMPARE_WRITE_CB_ID

Compare register write complete Callback ID

HAL_LPTIM_AUTORELOAD_WRITE_CB_ID

Auto-reload register write complete Callback ID

HAL_LPTIM_DIRECTION_UP_CB_ID

Up-counting direction change Callback ID

HAL_LPTIM_DIRECTION_DOWN_CB_ID

Down-counting direction change Callback ID

Definition at line 173 of file stm32h7xx_hal_lptim.h.

enum HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 128 of file stm32h7xx_hal_lptim.h.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 49 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 54 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 51 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 62 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 64 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 71 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 80 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 85 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 89 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 82 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 97 of file stm32h7xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 99 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 112 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 116 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 119 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 105 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 103 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 101 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 108 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State
void(* | MspInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | MspDeInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | TriggerCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionUpCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionDownCallback )(struct __LPTIM_HandleTypeDef *hlptim)

Detailed Description

LPTIM handle Structure definition.

Definition at line 141 of file stm32h7xx_hal_lptim.h.

Field Documentation

void(* __LPTIM_HandleTypeDef::AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload match Callback

Definition at line 160 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload register write complete Callback

Definition at line 163 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare match Callback

Definition at line 159 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare register write complete Callback

Definition at line 162 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Down-counting direction change Callback

Definition at line 165 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Up-counting direction change Callback

Definition at line 164 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

LPTIM_InitTypeDef __LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 148 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* __LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 146 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), and LPTIM_Disable().

HAL_LockTypeDef __LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 152 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

void(* __LPTIM_HandleTypeDef::MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp DeInit Callback

Definition at line 158 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_DeInit(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

void(* __LPTIM_HandleTypeDef::MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp Init Callback

Definition at line 157 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

__IO HAL_LPTIM_StateTypeDef __LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 154 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_Disable().

HAL_StatusTypeDef __LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 150 of file stm32h7xx_hal_lptim.h.

void(* __LPTIM_HandleTypeDef::TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim)

External trigger event detection Callback

Definition at line 161 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U

Definition at line 204 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 205 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LPTIM_PRESCALER_DIV1 0x00000000U

Definition at line 213 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Definition at line 220 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 217 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 214 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)

Definition at line 218 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 215 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)

Definition at line 219 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)

Definition at line 216 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U

Definition at line 229 of file stm32h7xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Definition at line 230 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 239 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 240 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 241 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 238 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 250 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U

Definition at line 249 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 251 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LPTIM_TRIGSOURCE_0 0x00000000U

Definition at line 260 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0

Definition at line 261 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 262 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 263 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 264 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 265 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 266 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Definition at line 267 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU

Definition at line 259 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

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STM32H7B3xQ HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 276 of file stm32h7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 275 of file stm32h7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 277 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 286 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 287 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 288 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 285 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 298 of file stm32h7xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE 0x00000000U

Definition at line 297 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 308 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U

Definition at line 307 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U
#define | LPTIM_INPUT1SOURCE_SAI4_FSA LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_SAI4_FSB LPTIM_CFGR2_IN1SEL_1

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0

For LPTIM1 and LPTIM2

Definition at line 318 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

For LPTIM2

Definition at line 320 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1

For LPTIM2

Definition at line 319 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 317 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U

For LPTIM3

Definition at line 321 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_SAI4_FSA LPTIM_CFGR2_IN1SEL_0

For LPTIM3

Definition at line 322 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_SAI4_FSB LPTIM_CFGR2_IN1SEL_1

For LPTIM3

Definition at line 323 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0

For LPTIM1

Definition at line 333 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U

For LPTIM1

Definition at line 332 of file stm32h7xx_hal_lptim.h.

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STM32H7B3xQ HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 347 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 344 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 348 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 345 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 342 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 346 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 343 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

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STM32H7B3xQ HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 361 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 358 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 362 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 359 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 356 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 360 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 357 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

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STM32H7B3xQ HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Autoreload value
Return values:
None
Note:
The ARR register can only be modified when the LPTIM instance is enabled.

Definition at line 443 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__ LPTIM handle.
__FLAG__ LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 484 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Compare value
Return values:
None
Note:
The CMP register can only be modified when the LPTIM instance is enabled.

Definition at line 452 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) LPTIM_Disable(__HANDLE__)

Disable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Please call HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to check for TIMEOUT.
Return values:
None

Definition at line 407 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.

Definition at line 518 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 395 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.

Definition at line 501 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__ LPTIM handle
__FLAG__ LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 468 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), and LPTIM_WaitForFlag().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt source is enabled or not.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 535 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_RESET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)

Reset the LPTIM Counter register in synchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 427 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)

Reset after read of the LPTIM Counter register in asynchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 434 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback   = NULL;                  \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;                  \
                                                     } while(0)

Reset LPTIM handle state.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 381 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 414 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Start the LPTIM peripheral in single mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 420 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Private Constants

Defines
LPTIM Private Constants
LPTIM

Defines

#define TIMEOUT 1000UL /* Timeout is 1s */

Define Documentation

#define TIMEOUT 1000UL /* Timeout is 1s */

Definition at line 181 of file stm32h7xx_hal_lptim.c.

Referenced by LPTIM_WaitForFlag().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFFUL)

Definition at line 752 of file stm32h7xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 723 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 704 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 713 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 718 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 700 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFFUL)

Definition at line 754 of file stm32h7xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 749 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 737 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                          \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))           \
     ||                                                      \
     (((__INSTANCE__) == LPTIM2) &&                          \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||          \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||          \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))     \
     ||                                                      \
     (((__INSTANCE__) == LPTIM3) &&                          \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) ||  \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))

Definition at line 760 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) ||                      \
       ((__INSTANCE__) == LPTIM2)) &&                     \
     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

Definition at line 776 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 715 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ ) ((__PERIOD__) <= 0x0000FFFFUL)

Definition at line 756 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFFUL)

Definition at line 758 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

Definition at line 727 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 741 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 746 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
LTDC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
HAL_StatusTypeDef | HAL_LTDC_RegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
Register a User LTDC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LTDC_UnRegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
Unregister an LTDC Callback LTDC callabck is redirected to the weak predefined callback.
void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the LTDC
      (+) De-initialize the LTDC

Function Documentation

HAL_StatusTypeDef HAL_LTDC_DeInit ( LTDC_HandleTypeDef * hltdc )

De-initialize the LTDC peripheral.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 321 of file stm32h7xx_hal_ltdc.c.

References __LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_NONE, HAL_LTDC_MspDeInit(), HAL_LTDC_STATE_RESET, __LTDC_HandleTypeDef::MspDeInitCallback, and __LTDC_HandleTypeDef::State.

void HAL_LTDC_ErrorCallback ( LTDC_HandleTypeDef * hltdc )

Error LTDC callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 702 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

HAL_StatusTypeDef HAL_LTDC_Init ( LTDC_HandleTypeDef * hltdc )

Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 212 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_ENABLE, __HAL_LTDC_ENABLE_IT, LTDC_InitTypeDef::AccumulatedActiveH, LTDC_InitTypeDef::AccumulatedActiveW, LTDC_InitTypeDef::AccumulatedHBP, LTDC_InitTypeDef::AccumulatedVBP, assert_param, LTDC_InitTypeDef::Backcolor, LTDC_ColorTypeDef::Blue, LTDC_InitTypeDef::DEPolarity, __LTDC_HandleTypeDef::ErrorCallback, __LTDC_HandleTypeDef::ErrorCode, LTDC_ColorTypeDef::Green, HAL_LTDC_ERROR_NONE, HAL_LTDC_ErrorCallback(), HAL_LTDC_LineEventCallback(), HAL_LTDC_MspInit(), HAL_LTDC_ReloadEventCallback(), HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, HAL_LTDC_STATE_RESET, LTDC_InitTypeDef::HorizontalSync, LTDC_InitTypeDef::HSPolarity, __LTDC_HandleTypeDef::Init, __LTDC_HandleTypeDef::Instance, IS_LTDC_AAH, IS_LTDC_AAW, IS_LTDC_AHBP, IS_LTDC_AVBP, IS_LTDC_DEPOL, IS_LTDC_HSPOL, IS_LTDC_HSYNC, IS_LTDC_PCPOL, IS_LTDC_TOTALH, IS_LTDC_TOTALW, IS_LTDC_VSPOL, IS_LTDC_VSYNC, __LTDC_HandleTypeDef::LineEventCallback, __LTDC_HandleTypeDef::Lock, LTDC_IT_FU, LTDC_IT_TE, __LTDC_HandleTypeDef::MspInitCallback, LTDC_InitTypeDef::PCPolarity, LTDC_ColorTypeDef::Red, __LTDC_HandleTypeDef::ReloadEventCallback, __LTDC_HandleTypeDef::State, LTDC_InitTypeDef::TotalHeigh, LTDC_InitTypeDef::TotalWidth, LTDC_InitTypeDef::VerticalSync, and LTDC_InitTypeDef::VSPolarity.

void HAL_LTDC_LineEventCallback ( LTDC_HandleTypeDef * hltdc )

Line Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 718 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

void HAL_LTDC_MspDeInit ( LTDC_HandleTypeDef * hltdc )

De-initialize the LTDC MSP.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 369 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_DeInit(), and HAL_LTDC_UnRegisterCallback().

void HAL_LTDC_MspInit ( LTDC_HandleTypeDef * hltdc )

Initialize the LTDC MSP.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 353 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), and HAL_LTDC_UnRegisterCallback().

HAL_StatusTypeDef HAL_LTDC_RegisterCallback | ( | LTDC_HandleTypeDef * | hltdc,
 |  | HAL_LTDC_CallbackIDTypeDef | CallbackID,
 |  | pLTDC_CallbackTypeDef | pCallback
 | ) |  |

Register a User LTDC Callback To be used instead of the weak predefined callback.

Parameters:
hltdc | ltdc handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
  • HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
  • HAL_LTDC_ERROR_CB_ID Error Callback ID
  • HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
  • HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 394 of file stm32h7xx_hal_ltdc.c.

References __LTDC_HandleTypeDef::ErrorCallback, __LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_CB_ID, HAL_LTDC_ERROR_INVALID_CALLBACK, HAL_LTDC_LINE_EVENT_CB_ID, HAL_LTDC_MSPDEINIT_CB_ID, HAL_LTDC_MSPINIT_CB_ID, HAL_LTDC_RELOAD_EVENT_CB_ID, HAL_LTDC_STATE_READY, HAL_LTDC_STATE_RESET, __LTDC_HandleTypeDef::LineEventCallback, __LTDC_HandleTypeDef::MspDeInitCallback, __LTDC_HandleTypeDef::MspInitCallback, __LTDC_HandleTypeDef::ReloadEventCallback, and __LTDC_HandleTypeDef::State.

void HAL_LTDC_ReloadEventCallback ( LTDC_HandleTypeDef * hltdc )

Reload Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 734 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback | ( | LTDC_HandleTypeDef * | hltdc,
 |  | HAL_LTDC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an LTDC Callback LTDC callabck is redirected to the weak predefined callback.

Parameters:
hltdc ltdc handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
  • HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
  • HAL_LTDC_ERROR_CB_ID Error Callback ID
  • HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
  • HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 487 of file stm32h7xx_hal_ltdc.c.

References __LTDC_HandleTypeDef::ErrorCallback, __LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_CB_ID, HAL_LTDC_ERROR_INVALID_CALLBACK, HAL_LTDC_ErrorCallback(), HAL_LTDC_LINE_EVENT_CB_ID, HAL_LTDC_LineEventCallback(), HAL_LTDC_MspDeInit(), HAL_LTDC_MSPDEINIT_CB_ID, HAL_LTDC_MspInit(), HAL_LTDC_MSPINIT_CB_ID, HAL_LTDC_RELOAD_EVENT_CB_ID, HAL_LTDC_ReloadEventCallback(), HAL_LTDC_STATE_READY, HAL_LTDC_STATE_RESET, __LTDC_HandleTypeDef::LineEventCallback, __LTDC_HandleTypeDef::MspDeInitCallback, __LTDC_HandleTypeDef::MspInitCallback, __LTDC_HandleTypeDef::ReloadEventCallback, and __LTDC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
LTDC Exported Functions

IO operation functions. More...

Functions

void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
__weak void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
__weak void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
__weak void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides function allowing to:
      (+) Handle LTDC interrupt request

Function Documentation

__weak void HAL_LTDC_ErrorCallback ( LTDC_HandleTypeDef * hltdc )

Error LTDC callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 702 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

void HAL_LTDC_IRQHandler ( LTDC_HandleTypeDef * hltdc )

Handle LTDC interrupt request.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 584 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_CLEAR_FLAG, __HAL_LTDC_DISABLE_IT, __LTDC_HandleTypeDef::ErrorCallback, __LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_FU, HAL_LTDC_ERROR_TE, HAL_LTDC_ErrorCallback(), HAL_LTDC_LineEventCallback(), HAL_LTDC_ReloadEventCallback(), HAL_LTDC_STATE_ERROR, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, __LTDC_HandleTypeDef::LineEventCallback, LTDC_FLAG_FU, LTDC_FLAG_LI, LTDC_FLAG_RR, LTDC_FLAG_TE, LTDC_IT_FU, LTDC_IT_LI, LTDC_IT_RR, LTDC_IT_TE, __LTDC_HandleTypeDef::ReloadEventCallback, and __LTDC_HandleTypeDef::State.

__weak void HAL_LTDC_LineEventCallback ( LTDC_HandleTypeDef * hltdc )

Line Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 718 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

__weak void HAL_LTDC_ReloadEventCallback ( LTDC_HandleTypeDef * hltdc )

Reload Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 734 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), and HAL_LTDC_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
LTDC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the LTDC foreground or/and background parameters.
      (+) Set the active layer.
      (+) Configure the color keying.
      (+) Configure the C-LUT.
      (+) Enable / Disable the color keying.
      (+) Enable / Disable the C-LUT.
      (+) Update the layer position.
      (+) Update the layer size.
      (+) Update pixel format on the fly.
      (+) Update transparency on the fly.
      (+) Update address on the fly.

Function Documentation

HAL_StatusTypeDef HAL_LTDC_ConfigCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t * | pCLUT,
 |  | uint32_t | CLUTSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Load the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pCLUT | pointer to the color lookup table address.
CLUTSize | the color lookup table size.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 872 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL44, LTDC_LayerCfgTypeDef::PixelFormat, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | RGBValue,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
RGBValue | the color key value
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 834 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | RGBValue,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the color keying without reloading.

Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
RGBValue | the color key value
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1857 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigLayer | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | pointer to a LTDC_LayerCfgTypeDef structure that contains the configuration information for the Layer.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 784 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, assert_param, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, __LTDC_HandleTypeDef::Instance, IS_LTDC_ALPHA, IS_LTDC_BLENDING_FACTOR1, IS_LTDC_BLENDING_FACTOR2, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_HCONFIGSP, IS_LTDC_HCONFIGST, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, IS_LTDC_VCONFIGSP, IS_LTDC_VCONFIGST, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.

Variant of the function HAL_LTDC_ConfigLayer without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | pointer to a LTDC_LayerCfgTypeDef structure that contains the configuration information for the Layer.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1507 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, assert_param, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_ALPHA, IS_LTDC_BLENDING_FACTOR1, IS_LTDC_BLENDING_FACTOR2, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_HCONFIGSP, IS_LTDC_HCONFIGST, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, IS_LTDC_VCONFIGSP, IS_LTDC_VCONFIGST, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_DisableCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1026 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color lookup table without reloading.

Variant of the function HAL_LTDC_DisableCLUT without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1990 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 956 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color keying without reloading.

Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1924 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableDither ( LTDC_HandleTypeDef * hltdc )

Disable Dither.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 1086 of file stm32h7xx_hal_ltdc.c.

References HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 991 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color lookup table without reloading.

Variant of the function HAL_LTDC_EnableCLUT without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1957 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 921 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color keying without reloading.

Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1891 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableDither ( LTDC_HandleTypeDef * hltdc )

Enable Dither.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 1059 of file stm32h7xx_hal_ltdc.c.

References HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Line
 | ) |  |

Define the position of the line interrupt.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Line | Line Interrupt Position.
Note:
User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
Return values:
HAL status

Definition at line 1429 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_DISABLE_IT, __HAL_LTDC_ENABLE_IT, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LIPOS, LTDC_IT_LI, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_Reload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | ReloadType
 | ) |  |

Reload LTDC Layers configuration.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
ReloadType | This parameter can be one of the following values : LTDC_RELOAD_IMMEDIATE : Immediate Reload LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
Note:
User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
Return values:
HAL status

Definition at line 1468 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_ENABLE_IT, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_RELOAD, LTDC_IT_RR, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAddress | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Address,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the frame buffer Address.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Address | new address value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1313 of file stm32h7xx_hal_ltdc.c.

References assert_param, LTDC_LayerCfgTypeDef::FBStartAdress, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Address,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the frame buffer Address without reloading.

Variant of the function HAL_LTDC_SetAddress without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Address | new address value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1745 of file stm32h7xx_hal_ltdc.c.

References assert_param, LTDC_LayerCfgTypeDef::FBStartAdress, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAlpha | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Alpha,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the layer alpha value.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Alpha | new alpha value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1269 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_ALPHA, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Alpha,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the layer alpha value without reloading.

Variant of the function HAL_LTDC_SetAlpha without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Alpha | new alpha value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1702 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_ALPHA, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPitch | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LinePitchInPixels,
 |  | uint32_t | LayerIdx
 | ) |  |

Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.

Example of a buffer 800x480 attached to layer for which we want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().

Note:
This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LinePitchInPixels | New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
LayerIdx | LTDC layer index concerned by the modification of line pitch.
Return values:
HAL status

Definition at line 1360 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LinePitchInPixels,
 |  | uint32_t | LayerIdx
 | ) |  |

Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.

Example of a buffer 800x480 attached to layer for which we want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().

Note:
This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). Variant of the function HAL_LTDC_SetPitch without immediate reload.
Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LinePitchInPixels | New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
LayerIdx | LTDC layer index concerned by the modification of line pitch.
Return values:
HAL status

Definition at line 1790 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPixelFormat | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Pixelformat,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the pixel format.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Pixelformat | new pixel format value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1224 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, __LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Pixelformat,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the pixel format without reloading.

Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDfef structure that contains the configuration information for the LTDC.
Pixelformat | new pixel format value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1659 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, and __LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetWindowPosition | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window position.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
X0 | LTDC window X offset
Y0 | LTDC window Y offset
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1173 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, __LTDC_HandleTypeDef::Instance, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window position without reloading.

Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
X0 | LTDC window X offset
Y0 | LTDC window Y offset
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1610 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowSize | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window size.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
XSize | LTDC Pixel per line
YSize | LTDC Line number
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1117 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, __LTDC_HandleTypeDef::Instance, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window size without reloading.

Variant of the function HAL_LTDC_SetWindowSize without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
XSize | LTDC Pixel per line
YSize | LTDC Line number
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1556 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, __LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), __LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
LTDC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
                  ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the LTDC handle state.
      (+) Get the LTDC handle error code.

Function Documentation

uint32_t HAL_LTDC_GetError ( LTDC_HandleTypeDef * hltdc )

Return the LTDC handle error code.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
LTDC Error Code

Definition at line 2050 of file stm32h7xx_hal_ltdc.c.

References __LTDC_HandleTypeDef::ErrorCode.

HAL_LTDC_StateTypeDef HAL_LTDC_GetState ( LTDC_HandleTypeDef * hltdc )

Return the LTDC handle state.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL state

Definition at line 2039 of file stm32h7xx_hal_ltdc.c.

References __LTDC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Private Functions

Functions
LTDC Private Functions
LTDC

Functions

static void LTDC_SetConfig (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC peripheral.

Function Documentation

static void LTDC_SetConfig | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  | [static]

Configure the LTDC peripheral.

Parameters:
hltdc | Pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | Pointer LTDC Layer Configuration structure
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
None

Definition at line 2076 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, LTDC_LayerCfgTypeDef::Backcolor, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, LTDC_ColorTypeDef::Blue, LTDC_LayerCfgTypeDef::FBStartAdress, LTDC_ColorTypeDef::Green, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, __LTDC_HandleTypeDef::Instance, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, LTDC_ColorTypeDef::Red, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Exported Types

Data Structures | Defines | Typedefs | Enumerations
LTDC Exported Types
LTDC

Data Structures

struct | LTDC_ColorTypeDef
LTDC color structure definition. More...
struct | LTDC_InitTypeDef
LTDC Init structure definition. More...
struct | LTDC_LayerCfgTypeDef
LTDC Layer structure definition. More...
struct | __LTDC_HandleTypeDef
LTDC handle Structure definition. More...

Defines

#define | MAX_LAYER 2U

Typedefs

typedef struct __LTDC_HandleTypeDef | LTDC_HandleTypeDef
LTDC handle Structure definition.
typedef void(* | pLTDC_CallbackTypeDef )(LTDC_HandleTypeDef *hltdc)
HAL LTDC Callback pointer definition.

Enumerations

enum HAL_LTDC_StateTypeDef {
HAL_LTDC_STATE_RESET = 0x00U, HAL_LTDC_STATE_READY = 0x01U, HAL_LTDC_STATE_BUSY = 0x02U, HAL_LTDC_STATE_TIMEOUT = 0x03U,
HAL_LTDC_STATE_ERROR = 0x04U
}
HAL LTDC State structures definition. More...
enum HAL_LTDC_CallbackIDTypeDef {
HAL_LTDC_MSPINIT_CB_ID = 0x00U, HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U,
HAL_LTDC_ERROR_CB_ID = 0x04U
}
HAL LTDC Callback ID enumeration definition. More...

Define Documentation

#define MAX_LAYER 2U

Definition at line 46 of file stm32h7xx_hal_ltdc.h.

Typedef Documentation

typedef struct __LTDC_HandleTypeDef LTDC_HandleTypeDef

LTDC handle Structure definition.

typedef void(* pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc)

HAL LTDC Callback pointer definition.

pointer to an LTDC callback function

Definition at line 216 of file stm32h7xx_hal_ltdc.h.

Enumeration Type Documentation

enum HAL_LTDC_CallbackIDTypeDef

HAL LTDC Callback ID enumeration definition.

Enumerator:
HAL_LTDC_MSPINIT_CB_ID

LTDC MspInit callback ID

HAL_LTDC_MSPDEINIT_CB_ID

LTDC MspDeInit callback ID

HAL_LTDC_LINE_EVENT_CB_ID

LTDC Line Event Callback ID

HAL_LTDC_RELOAD_EVENT_CB_ID

LTDC Reload Callback ID

HAL_LTDC_ERROR_CB_ID

LTDC Error Callback ID

Definition at line 202 of file stm32h7xx_hal_ltdc.h.

enum HAL_LTDC_StateTypeDef

HAL LTDC State structures definition.

Enumerator:
HAL_LTDC_STATE_RESET

LTDC not yet initialized or disabled

HAL_LTDC_STATE_READY

LTDC initialized and ready for use

HAL_LTDC_STATE_BUSY

LTDC internal process is ongoing

HAL_LTDC_STATE_TIMEOUT

LTDC Timeout state

HAL_LTDC_STATE_ERROR

LTDC state error

Definition at line 155 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC_ColorTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_ColorTypeDef Struct Reference
LTDC Exported Types

LTDC color structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint8_t | Blue
uint8_t | Green
uint8_t | Red
uint8_t | Reserved

Detailed Description

LTDC color structure definition.

Definition at line 51 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint8_t LTDC_ColorTypeDef::Blue

Configures the blue value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 53 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Green

Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 56 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Red

Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 59 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Reserved

Reserved 0xFF

Definition at line 62 of file stm32h7xx_hal_ltdc.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_InitTypeDef Struct Reference
LTDC Exported Types

LTDC Init structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint32_t | HSPolarity
uint32_t | VSPolarity
uint32_t | DEPolarity
uint32_t | PCPolarity
uint32_t | HorizontalSync
uint32_t | VerticalSync
uint32_t | AccumulatedHBP
uint32_t | AccumulatedVBP
uint32_t | AccumulatedActiveW
uint32_t | AccumulatedActiveH
uint32_t | TotalWidth
uint32_t | TotalHeigh
LTDC_ColorTypeDef Backcolor

Detailed Description

LTDC Init structure definition.

Definition at line 68 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint32_t LTDC_InitTypeDef::AccumulatedActiveH

configures the accumulated active height. This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF.

Definition at line 97 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedActiveW

configures the accumulated active width. This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF.

Definition at line 94 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedHBP

configures the accumulated horizontal back porch width. This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF.

Definition at line 88 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedVBP

configures the accumulated vertical back porch height. This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF.

Definition at line 91 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

LTDC_ColorTypeDef LTDC_InitTypeDef::Backcolor

Configures the background color.

Definition at line 106 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::DEPolarity

configures the data enable polarity. This parameter can be one of value of LTDC DE POLARITY

Definition at line 76 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::HorizontalSync

configures the number of Horizontal synchronization width. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 82 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::HSPolarity

configures the horizontal synchronization polarity. This parameter can be one value of LTDC HS POLARITY

Definition at line 70 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::PCPolarity

configures the pixel clock polarity. This parameter can be one of value of LTDC PC POLARITY

Definition at line 79 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::TotalHeigh

configures the total height. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF.

Definition at line 103 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::TotalWidth

configures the total width. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF.

Definition at line 100 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::VerticalSync

configures the number of Vertical synchronization height. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 85 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::VSPolarity

configures the vertical synchronization polarity. This parameter can be one value of LTDC VS POLARITY

Definition at line 73 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC_LayerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_LayerCfgTypeDef Struct Reference
LTDC Exported Types

LTDC Layer structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint32_t | WindowX0
uint32_t | WindowX1
uint32_t | WindowY0
uint32_t | WindowY1
uint32_t | PixelFormat
uint32_t | Alpha
uint32_t | Alpha0
uint32_t | BlendingFactor1
uint32_t | BlendingFactor2
uint32_t | FBStartAdress
uint32_t | ImageWidth
uint32_t | ImageHeight
LTDC_ColorTypeDef Backcolor

Detailed Description

LTDC Layer structure definition.

Definition at line 112 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint32_t LTDC_LayerCfgTypeDef::Alpha

Specifies the constant alpha used for blending. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 129 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::Alpha0

Configures the default alpha value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 132 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

LTDC_ColorTypeDef LTDC_LayerCfgTypeDef::Backcolor

Configures the layer background color.

Definition at line 149 of file stm32h7xx_hal_ltdc.h.

Referenced by LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::BlendingFactor1

Select the blending factor 1. This parameter can be one of value of LTDC Blending Factor1

Definition at line 135 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::BlendingFactor2

Select the blending factor 2. This parameter can be one of value of LTDC Blending Factor2

Definition at line 138 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::FBStartAdress

Configures the color frame buffer address

Definition at line 141 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::ImageHeight

Specifies the number of line in frame buffer. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 146 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::ImageWidth

Configures the color frame buffer line length. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF.

Definition at line 143 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::PixelFormat

Specifies the pixel format. This parameter can be one of value of LTDC Pixel format

Definition at line 126 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowX0

Configures the Window Horizontal Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 114 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowX1

Configures the Window Horizontal Stop Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 117 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowY0

Configures the Window vertical Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 120 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowY1

Configures the Window vertical Stop Position. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF.

Definition at line 123 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __LTDC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__LTDC_HandleTypeDef Struct Reference
LTDC Exported Types

LTDC handle Structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

LTDC_TypeDef * | Instance
LTDC_InitTypeDef Init
LTDC_LayerCfgTypeDef LayerCfg [MAX_LAYER]
HAL_LockTypeDef | Lock
__IO HAL_LTDC_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | LineEventCallback )(struct __LTDC_HandleTypeDef *hltdc)
void(* | ReloadEventCallback )(struct __LTDC_HandleTypeDef *hltdc)
void(* | ErrorCallback )(struct __LTDC_HandleTypeDef *hltdc)
void(* | MspInitCallback )(struct __LTDC_HandleTypeDef *hltdc)
void(* | MspDeInitCallback )(struct __LTDC_HandleTypeDef *hltdc)

Detailed Description

LTDC handle Structure definition.

Definition at line 168 of file stm32h7xx_hal_ltdc.h.

Field Documentation

void(* __LTDC_HandleTypeDef::ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc)

LTDC Error Callback

Definition at line 188 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

__IO uint32_t __LTDC_HandleTypeDef::ErrorCode

LTDC Error code

Definition at line 183 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_DeInit(), HAL_LTDC_GetError(), HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

LTDC_InitTypeDef __LTDC_HandleTypeDef::Init

LTDC parameters

Definition at line 175 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

LTDC_TypeDef* __LTDC_HandleTypeDef::Instance

LTDC Register base address

Definition at line 173 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigLayer(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowSize(), and LTDC_SetConfig().

LTDC_LayerCfgTypeDef __LTDC_HandleTypeDef::LayerCfg[MAX_LAYER]

LTDC Layers parameters

Definition at line 177 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

void(* __LTDC_HandleTypeDef::LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc)

LTDC Line Event Callback

Definition at line 186 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

HAL_LockTypeDef __LTDC_HandleTypeDef::Lock

LTDC Lock

Definition at line 179 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

void(* __LTDC_HandleTypeDef::MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc)

LTDC Msp DeInit callback

Definition at line 191 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_DeInit(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

void(* __LTDC_HandleTypeDef::MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc)

LTDC Msp Init callback

Definition at line 190 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

void(* __LTDC_HandleTypeDef::ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc)

LTDC Reload Event Callback

Definition at line 187 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

__IO HAL_LTDC_StateTypeDef __LTDC_HandleTypeDef::State

LTDC state

Definition at line 181 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DeInit(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_DisableDither(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_EnableDither(), HAL_LTDC_GetState(), HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_ProgramLineEvent(), HAL_LTDC_RegisterCallback(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and HAL_LTDC_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Error Code

Defines
LTDC Error Code
LTDC Exported Constants

Defines

#define | HAL_LTDC_ERROR_NONE 0x00000000U
#define | HAL_LTDC_ERROR_TE 0x00000001U
#define | HAL_LTDC_ERROR_FU 0x00000002U
#define | HAL_LTDC_ERROR_TIMEOUT 0x00000020U
#define | HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U

Define Documentation

#define HAL_LTDC_ERROR_FU 0x00000002U

LTDC FIFO Underrun

Definition at line 234 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U

LTDC Invalid Callback error

Definition at line 237 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_RegisterCallback(), and HAL_LTDC_UnRegisterCallback().

#define HAL_LTDC_ERROR_NONE 0x00000000U

LTDC No error

Definition at line 232 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_DeInit(), and HAL_LTDC_Init().

#define HAL_LTDC_ERROR_TE 0x00000001U

LTDC Transfer error

Definition at line 233 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U

LTDC Timeout error

Definition at line 235 of file stm32h7xx_hal_ltdc.h.

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STM32H7B3xQ HAL User Manual: LTDC Layer

Defines
LTDC Layer
LTDC Exported Constants

Defines

#define | LTDC_LAYER_1 0x00000000U
#define | LTDC_LAYER_2 0x00000001U

Define Documentation

#define LTDC_LAYER_1 0x00000000U

LTDC Layer 1

Definition at line 246 of file stm32h7xx_hal_ltdc.h.

#define LTDC_LAYER_2 0x00000001U

LTDC Layer 2

Definition at line 247 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC HS POLARITY

Defines
LTDC HS POLARITY
LTDC Exported Constants

Defines

#define | LTDC_HSPOLARITY_AL 0x00000000U
#define | LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL

Define Documentation

#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL

Horizontal Synchronization is active high.

Definition at line 256 of file stm32h7xx_hal_ltdc.h.

#define LTDC_HSPOLARITY_AL 0x00000000U

Horizontal Synchronization is active low.

Definition at line 255 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC VS POLARITY

Defines
LTDC VS POLARITY
LTDC Exported Constants

Defines

#define | LTDC_VSPOLARITY_AL 0x00000000U
#define | LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL

Define Documentation

#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL

Vertical Synchronization is active high.

Definition at line 265 of file stm32h7xx_hal_ltdc.h.

#define LTDC_VSPOLARITY_AL 0x00000000U

Vertical Synchronization is active low.

Definition at line 264 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC DE POLARITY

Defines
LTDC DE POLARITY
LTDC Exported Constants

Defines

#define | LTDC_DEPOLARITY_AL 0x00000000U
#define | LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL

Define Documentation

#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL

Data Enable, is active high.

Definition at line 274 of file stm32h7xx_hal_ltdc.h.

#define LTDC_DEPOLARITY_AL 0x00000000U

Data Enable, is active low.

Definition at line 273 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC PC POLARITY

Defines
LTDC PC POLARITY
LTDC Exported Constants

Defines

#define | LTDC_PCPOLARITY_IPC 0x00000000U
#define | LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL

Define Documentation

#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL

inverted input pixel clock.

Definition at line 283 of file stm32h7xx_hal_ltdc.h.

#define LTDC_PCPOLARITY_IPC 0x00000000U

input pixel clock.

Definition at line 282 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC SYNC

Defines
LTDC SYNC
LTDC Exported Constants

Defines

#define | LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U)
#define | LTDC_VERTICALSYNC LTDC_SSCR_VSH

Define Documentation

#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U)

Horizontal synchronization width.

Definition at line 291 of file stm32h7xx_hal_ltdc.h.

#define LTDC_VERTICALSYNC LTDC_SSCR_VSH

Vertical synchronization height.

Definition at line 292 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC BACK COLOR

Defines
LTDC BACK COLOR
LTDC Exported Constants

Defines

#define LTDC_COLOR 0x000000FFU

Define Documentation

#define LTDC_COLOR 0x000000FFU

Color mask

Definition at line 300 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Blending Factor1

Defines
LTDC Blending Factor1
LTDC Exported Constants

Defines

#define | LTDC_BLENDING_FACTOR1_CA 0x00000400U
#define | LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U

Define Documentation

#define LTDC_BLENDING_FACTOR1_CA 0x00000400U

Blending factor : Cte Alpha

Definition at line 308 of file stm32h7xx_hal_ltdc.h.

#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U

Blending factor : Cte Alpha x Pixel Alpha

Definition at line 309 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Blending Factor2

Defines
LTDC Blending Factor2
LTDC Exported Constants

Defines

#define | LTDC_BLENDING_FACTOR2_CA 0x00000005U
#define | LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U

Define Documentation

#define LTDC_BLENDING_FACTOR2_CA 0x00000005U

Blending factor : Cte Alpha

Definition at line 317 of file stm32h7xx_hal_ltdc.h.

#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U

Blending factor : Cte Alpha x Pixel Alpha

Definition at line 318 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Pixel format

Defines
LTDC Pixel format
LTDC Exported Constants

Defines

#define | LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U
#define | LTDC_PIXEL_FORMAT_RGB888 0x00000001U
#define | LTDC_PIXEL_FORMAT_RGB565 0x00000002U
#define | LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U
#define | LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U
#define | LTDC_PIXEL_FORMAT_L8 0x00000005U
#define | LTDC_PIXEL_FORMAT_AL44 0x00000006U
#define | LTDC_PIXEL_FORMAT_AL88 0x00000007U

Define Documentation

#define LTDC_PIXEL_FORMAT_AL44 0x00000006U

AL44 LTDC pixel format

Definition at line 332 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT().

#define LTDC_PIXEL_FORMAT_AL88 0x00000007U

AL88 LTDC pixel format

Definition at line 333 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U

ARGB1555 LTDC pixel format

Definition at line 329 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U

ARGB4444 LTDC pixel format

Definition at line 330 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U

ARGB8888 LTDC pixel format

Definition at line 326 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_L8 0x00000005U

L8 LTDC pixel format

Definition at line 331 of file stm32h7xx_hal_ltdc.h.

#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U

RGB565 LTDC pixel format

Definition at line 328 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U

RGB888 LTDC pixel format

Definition at line 327 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Alpha

Defines
LTDC Alpha
LTDC Exported Constants

Defines

#define LTDC_ALPHA LTDC_LxCACR_CONSTA

Define Documentation

#define LTDC_ALPHA LTDC_LxCACR_CONSTA

LTDC Constant Alpha mask

Definition at line 341 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC LAYER Config

Defines
LTDC LAYER Config
LTDC Exported Constants

Defines

#define | LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U)
#define | LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS
#define | LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL
#define | LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR

Define Documentation

#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL

LTDC Layer Line length

Definition at line 352 of file stm32h7xx_hal_ltdc.h.

#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR

LTDC Layer Line number

Definition at line 353 of file stm32h7xx_hal_ltdc.h.

#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS

LTDC Layer start position

Definition at line 350 of file stm32h7xx_hal_ltdc.h.

#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U)

LTDC Layer stop position

Definition at line 349 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Interrupts

Defines
LTDC Interrupts
LTDC Exported Constants

Defines

#define | LTDC_IT_LI LTDC_IER_LIE
#define | LTDC_IT_FU LTDC_IER_FUIE
#define | LTDC_IT_TE LTDC_IER_TERRIE
#define | LTDC_IT_RR LTDC_IER_RRIE

Define Documentation

#define LTDC_IT_FU LTDC_IER_FUIE

LTDC FIFO Underrun Interrupt

Definition at line 362 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and HAL_LTDC_IRQHandler().

#define LTDC_IT_LI LTDC_IER_LIE

LTDC Line Interrupt

Definition at line 361 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_ProgramLineEvent().

#define LTDC_IT_RR LTDC_IER_RRIE

LTDC Register Reload Interrupt

Definition at line 364 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_Reload().

#define LTDC_IT_TE LTDC_IER_TERRIE

LTDC Transfer Error Interrupt

Definition at line 363 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and HAL_LTDC_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Flags

Defines
LTDC Flags
LTDC Exported Constants

Defines

#define | LTDC_FLAG_LI LTDC_ISR_LIF
#define | LTDC_FLAG_FU LTDC_ISR_FUIF
#define | LTDC_FLAG_TE LTDC_ISR_TERRIF
#define | LTDC_FLAG_RR LTDC_ISR_RRIF

Define Documentation

#define LTDC_FLAG_FU LTDC_ISR_FUIF

LTDC FIFO Underrun interrupt Flag

Definition at line 373 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_LI LTDC_ISR_LIF

LTDC Line Interrupt Flag

Definition at line 372 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_RR LTDC_ISR_RRIF

LTDC Register Reload interrupt Flag

Definition at line 375 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_TE LTDC_ISR_TERRIF

LTDC Transfer Error interrupt Flag

Definition at line 374 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Reload Type

Defines
LTDC Reload Type
LTDC Exported Constants

Defines

#define | LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR
#define | LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR

Define Documentation

#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR

Immediate Reload

Definition at line 383 of file stm32h7xx_hal_ltdc.h.

#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR

Vertical Blanking Reload

Definition at line 384 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Exported Macros

Defines
LTDC Exported Macros
LTDC

Defines

#define | __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__)
Reset LTDC handle state.
#define | __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
Enable the LTDC.
#define | __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
Disable the LTDC.
#define | __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
Enable the LTDC Layer.
#define | __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
Disable the LTDC Layer.
#define | __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
Reload immediately all LTDC Layers.
#define | __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
Reload during vertical blanking period all LTDC Layers.
#define | __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the LTDC pending flags.
#define | __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the LTDC pending flags.
#define | __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified LTDC interrupts.
#define | __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disables the specified LTDC interrupts.
#define | __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Check whether the specified LTDC interrupt has occurred or not.

Define Documentation

#define __HAL_LTDC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clears the LTDC pending flags.

Parameters:
__HANDLE__ LTDC handle
__FLAG__ Specify the flag to clear. This parameter can be any combination of the following values:
  • LTDC_FLAG_LI: Line Interrupt flag
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag
  • LTDC_FLAG_TE: Transfer Error interrupt flag
  • LTDC_FLAG_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 483 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define __HAL_LTDC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))

Disable the LTDC.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 424 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disables the specified LTDC interrupts.

Parameters:
__HANDLE__ LTDC handle
__INTERRUPT__ Specify the LTDC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 509 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_ProgramLineEvent().

#define __HAL_LTDC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)

Enable the LTDC.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 417 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define __HAL_LTDC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified LTDC interrupts.

Parameters:
__HANDLE__ LTDC handle
__INTERRUPT__ Specify the LTDC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 496 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_ProgramLineEvent(), and HAL_LTDC_Reload().

#define __HAL_LTDC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Get the LTDC pending flags.

Parameters:
__HANDLE__ LTDC handle
__FLAG__ Get the specified flag. This parameter can be any combination of the following values:
  • LTDC_FLAG_LI: Line Interrupt flag
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag
  • LTDC_FLAG_TE: Transfer Error interrupt flag
  • LTDC_FLAG_RR: Register Reload Interrupt Flag
Return values:
The state of FLAG (SET or RESET).

Definition at line 470 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Check whether the specified LTDC interrupt has occurred or not.

Parameters:
__HANDLE__ LTDC handle
__INTERRUPT__ Specify the LTDC interrupt source to check. This parameter can be one of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
The state of INTERRUPT (SET or RESET).

Definition at line 522 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_LAYER_DISABLE | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)

Disable the LTDC Layer.

Parameters:
__HANDLE__ | LTDC handle
__LAYER__ | Specify the layer to be disabled. This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
None.

Definition at line 442 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_LAYER_ENABLE | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)

Enable the LTDC Layer.

Parameters:
__HANDLE__ | LTDC handle
__LAYER__ | Specify the layer to be enabled. This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
None.

Definition at line 433 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG ( __HANDLE__ ) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)

Reload immediately all LTDC Layers.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 449 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                      (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \
                                                      (__HANDLE__)->MspInitCallback = NULL;           \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                    } while(0)

Reset LTDC handle state.

Parameters:
__HANDLE__ LTDC handle
Return values:
None

Definition at line 403 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG ( __HANDLE__ ) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)

Reload during vertical blanking period all LTDC Layers.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 456 of file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LTDC Private Macros

Defines
LTDC Private Macros
LTDC

Defines

#define | LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
#define | IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define | IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define | IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define | IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define | IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define | IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define | IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define | IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define | IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__)
#define | IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__)
#define | IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)
#define | IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define | IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define | IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define | IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Define Documentation

#define IS_LTDC_AAH ( __AAH__ ) ((__AAH__) <= LTDC_VERTICALSYNC)

Definition at line 635 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_AAW ( __AAW__ ) ((__AAW__) <= LTDC_HORIZONTALSYNC)

Definition at line 634 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_AHBP ( __AHBP__ ) ((__AHBP__) <= LTDC_HORIZONTALSYNC)

Definition at line 632 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_ALPHA ( __ALPHA__ ) ((__ALPHA__) <= LTDC_ALPHA)

Definition at line 649 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAlpha(), and HAL_LTDC_SetAlpha_NoReload().

#define IS_LTDC_AVBP ( __AVBP__ ) ((__AVBP__) <= LTDC_VERTICALSYNC)

Definition at line 633 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_BLENDING_FACTOR1 ( __BLENDING_FACTOR1__ )
Value:
(((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))

Definition at line 641 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_BLENDING_FACTOR2 ( __BLENDING_FACTOR1__ )
Value:
(((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))

Definition at line 643 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_BLUEVALUE ( __BBLUE__ ) ((__BBLUE__) <= LTDC_COLOR)

Definition at line 638 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_CFBLL ( __CFBLL__ ) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)

Definition at line 655 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_CFBLNBR ( __CFBLNBR__ ) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)

Definition at line 656 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_CFBP ( __CFBP__ ) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)

Definition at line 654 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_DEPOL ( __DEPOL__ ) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))

Definition at line 628 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_GREENVALUE ( __BGREEN__ ) ((__BGREEN__) <= LTDC_COLOR)

Definition at line 639 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_HCONFIGSP ( __HCONFIGSP__ ) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)

Definition at line 651 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_HCONFIGST ( __HCONFIGST__ ) ((__HCONFIGST__) <= LTDC_STARTPOSITION)

Definition at line 650 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_HSPOL ( __HSPOL__ ) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))

Definition at line 626 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_HSYNC ( __HSYNC__ ) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)

Definition at line 630 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_LAYER ( __LAYER__ ) ((__LAYER__) < MAX_LAYER)

Definition at line 625 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_LIPOS ( __LIPOS__ ) ((__LIPOS__) <= 0x7FFU)

Definition at line 657 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ProgramLineEvent().

#define IS_LTDC_PCPOL ( __PCPOL__ ) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))

Definition at line 629 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_PIXEL_FORMAT ( __PIXEL_FORMAT__ )
Value:
(((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))

Definition at line 645 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetPixelFormat(), and HAL_LTDC_SetPixelFormat_NoReload().

#define IS_LTDC_REDVALUE ( __BRED__ ) ((__BRED__) <= LTDC_COLOR)

Definition at line 640 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_RELOAD ( __RELOADTYPE__ ) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Definition at line 658 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Reload().

#define IS_LTDC_TOTALH ( __TOTALH__ ) ((__TOTALH__) <= LTDC_VERTICALSYNC)

Definition at line 637 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_TOTALW ( __TOTALW__ ) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)

Definition at line 636 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_VCONFIGSP ( __VCONFIGSP__ ) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)

Definition at line 653 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_VCONFIGST ( __VCONFIGST__ ) ((__VCONFIGST__) <= LTDC_STARTPOSITION)

Definition at line 652 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_VSPOL ( __VSPOL__ ) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))

Definition at line 627 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_VSYNC ( __VSYNC__ ) ((__VSYNC__) <= LTDC_VERTICALSYNC)

Definition at line 631 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define LTDC_LAYER | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))

Definition at line 624 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
MDIOS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.
HAL_StatusTypeDef | HAL_MDIOS_RegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
Register a User MDIOS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_MDIOS_UnRegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
Unregister an MDIOS Callback MDIOS callabck is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the MDIOS
      (+) The following parameters can be configured:
        (++) Port Address
        (++) Preamble Check

Function Documentation

HAL_StatusTypeDef HAL_MDIOS_DeInit ( MDIOS_HandleTypeDef * hmdios )

DeInitializes the MDIOS peripheral.

Parameters:
hmdios,: MDIOS handle
Return values:
HAL status

Definition at line 264 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_DISABLE, assert_param, HAL_MDIOS_MspDeInit(), HAL_MDIOS_STATE_BUSY, HAL_MDIOS_STATE_RESET, __MDIOS_HandleTypeDef::Instance, __MDIOS_HandleTypeDef::MspDeInitCallback, and __MDIOS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDIOS_Init ( MDIOS_HandleTypeDef * hmdios )

Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .

Parameters:
hmdios,: pointer to a MDIOS_HandleTypeDef structure that contains the configuration information for MDIOS module
Return values:
HAL status

Definition at line 189 of file stm32h7xx_hal_mdios.c.

References assert_param, __MDIOS_HandleTypeDef::ErrorCode, HAL_MDIOS_ERROR_NONE, HAL_MDIOS_MspInit(), HAL_MDIOS_STATE_BUSY, HAL_MDIOS_STATE_READY, HAL_MDIOS_STATE_RESET, __MDIOS_HandleTypeDef::Init, __MDIOS_HandleTypeDef::Instance, IS_MDIOS_PORTADDRESS, IS_MDIOS_PREAMBLECHECK, MDIOS_InitCallbacksToDefault(), MDIOS_PORT_ADDRESS_SHIFT, __MDIOS_HandleTypeDef::MspInitCallback, MDIOS_InitTypeDef::PortAddress, MDIOS_InitTypeDef::PreambleCheck, and __MDIOS_HandleTypeDef::State.

void HAL_MDIOS_MspDeInit ( MDIOS_HandleTypeDef * hmdios )

MDIOS MSP DeInit.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 326 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_DeInit(), and HAL_MDIOS_UnRegisterCallback().

void HAL_MDIOS_MspInit ( MDIOS_HandleTypeDef * hmdios )

MDIOS MSP Init.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 311 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_Init(), and HAL_MDIOS_UnRegisterCallback().

HAL_StatusTypeDef HAL_MDIOS_RegisterCallback | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | HAL_MDIOS_CallbackIDTypeDef | CallbackID,
 |  | pMDIOS_CallbackTypeDef | pCallback
 | ) |  |

Register a User MDIOS Callback To be used instead of the weak predefined callback.

Parameters:
hmdios | mdios handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
  • HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
  • HAL_MDIOS_ERROR_CB_ID Error Callback ID
  • HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
  • HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
  • HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 352 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::ErrorCallback, __MDIOS_HandleTypeDef::ErrorCode, HAL_MDIOS_ERROR_CB_ID, HAL_MDIOS_ERROR_INVALID_CALLBACK, HAL_MDIOS_MSPDEINIT_CB_ID, HAL_MDIOS_MSPINIT_CB_ID, HAL_MDIOS_READ_COMPLETE_CB_ID, HAL_MDIOS_STATE_READY, HAL_MDIOS_STATE_RESET, HAL_MDIOS_WAKEUP_CB_ID, HAL_MDIOS_WRITE_COMPLETE_CB_ID, __MDIOS_HandleTypeDef::MspDeInitCallback, __MDIOS_HandleTypeDef::MspInitCallback, __MDIOS_HandleTypeDef::ReadCpltCallback, __MDIOS_HandleTypeDef::State, __MDIOS_HandleTypeDef::WakeUpCallback, and __MDIOS_HandleTypeDef::WriteCpltCallback.

HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | HAL_MDIOS_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an MDIOS Callback MDIOS callabck is redirected to the weak predefined callback.

Parameters:
hmdios mdios handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
  • HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
  • HAL_MDIOS_ERROR_CB_ID Error Callback ID
  • HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
  • HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
  • HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 450 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::ErrorCallback, __MDIOS_HandleTypeDef::ErrorCode, HAL_MDIOS_ERROR_CB_ID, HAL_MDIOS_ERROR_INVALID_CALLBACK, HAL_MDIOS_ErrorCallback(), HAL_MDIOS_MspDeInit(), HAL_MDIOS_MSPDEINIT_CB_ID, HAL_MDIOS_MspInit(), HAL_MDIOS_MSPINIT_CB_ID, HAL_MDIOS_READ_COMPLETE_CB_ID, HAL_MDIOS_ReadCpltCallback(), HAL_MDIOS_STATE_READY, HAL_MDIOS_STATE_RESET, HAL_MDIOS_WAKEUP_CB_ID, HAL_MDIOS_WakeUpCallback(), HAL_MDIOS_WRITE_COMPLETE_CB_ID, HAL_MDIOS_WriteCpltCallback(), __MDIOS_HandleTypeDef::MspDeInitCallback, __MDIOS_HandleTypeDef::MspInitCallback, __MDIOS_HandleTypeDef::ReadCpltCallback, __MDIOS_HandleTypeDef::State, __MDIOS_HandleTypeDef::WakeUpCallback, and __MDIOS_HandleTypeDef::WriteCpltCallback.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
MDIOS Exported Functions

MDIOS Read/Write functions. More...

Functions

HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.

Detailed Description

MDIOS Read/Write functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the MDIOS
    read and write operations.

    (#) APIs that allow to the MDIOS to read/write from/to the
        values of one of the DINn/DOUTn registers:
        (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
        (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()

    (#) APIs that provide if there are some Slave registres have been
        read or written by the Master:
        (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
        (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()

    (#) APIs that Clear the read/write flags:
        (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
        (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()

    (#) A set of Callbacks are provided:
        (+) HAL_MDIOS_WriteCpltCallback()
        (+) HAL_MDIOS_ReadCpltCallback()
        (+) HAL_MDIOS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum
 | ) |  |

Clears Read register flag.

Parameters:
hmdios,: mdios handle
RegNum,: registers addresses to be cleared
Return values:
HAL status

Definition at line 672 of file stm32h7xx_hal_mdios.c.

References assert_param, __MDIOS_HandleTypeDef::Instance, and IS_MDIOS_REGISTER.

HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum
 | ) |  |

Clears Write registers flag.

Parameters:
hmdios,: mdios handle
RegNum,: registers addresses to be cleared
Return values:
HAL status

Definition at line 649 of file stm32h7xx_hal_mdios.c.

References assert_param, __MDIOS_HandleTypeDef::Instance, and IS_MDIOS_REGISTER.

HAL_StatusTypeDef HAL_MDIOS_EnableEvents ( MDIOS_HandleTypeDef * hmdios )

Enables Events for MDIOS peripheral.

Parameters:
hmdios,: mdios handle
Return values:
HAL status

Definition at line 694 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_ENABLE_IT, MDIOS_IT_ERROR, MDIOS_IT_READ, and MDIOS_IT_WRITE.

void HAL_MDIOS_ErrorCallback ( MDIOS_HandleTypeDef * hmdios )

Error Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 859 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

uint32_t HAL_MDIOS_GetReadRegAddress ( MDIOS_HandleTypeDef * hmdios )

Gets Read registers by MDIO master.

Parameters:
hmdios,: mdios handle
Return values:
bit map of read registers addresses

Definition at line 638 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::Instance.

Referenced by HAL_MDIOS_IRQHandler().

uint32_t HAL_MDIOS_GetWrittenRegAddress ( MDIOS_HandleTypeDef * hmdios )

Gets Written registers by MDIO master.

Parameters:
hmdios,: mdios handle
Return values:
bit map of written registers addresses

Definition at line 628 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::Instance.

Referenced by HAL_MDIOS_IRQHandler().

void HAL_MDIOS_IRQHandler ( MDIOS_HandleTypeDef * hmdios )

This function handles MDIOS interrupt request.

Parameters:
hmdios,: MDIOS handle
Return values:
None

Definition at line 713 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_CLEAR_ERROR_FLAG, __HAL_MDIOS_GET_ERROR_FLAG, __HAL_MDIOS_GET_IT_SOURCE, __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG, __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG, CM7_CPUID, __MDIOS_HandleTypeDef::ErrorCallback, __MDIOS_HandleTypeDef::ErrorCode, HAL_GetCurrentCPUID(), HAL_MDIOS_ERROR_DATA, HAL_MDIOS_ERROR_NONE, HAL_MDIOS_ErrorCallback(), HAL_MDIOS_GetReadRegAddress(), HAL_MDIOS_GetWrittenRegAddress(), HAL_MDIOS_ReadCpltCallback(), HAL_MDIOS_WakeUpCallback(), HAL_MDIOS_WriteCpltCallback(), __MDIOS_HandleTypeDef::Instance, MDIOS_ALL_ERRORS_FLAG, MDIOS_ALL_REG_FLAG, MDIOS_IT_ERROR, MDIOS_IT_READ, MDIOS_IT_WRITE, MDIOS_WAKEUP_EXTI_LINE, __MDIOS_HandleTypeDef::ReadCpltCallback, __MDIOS_HandleTypeDef::WakeUpCallback, and __MDIOS_HandleTypeDef::WriteCpltCallback.

void HAL_MDIOS_ReadCpltCallback ( MDIOS_HandleTypeDef * hmdios )

Read Complete Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 844 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_MDIOS_ReadReg | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum,
 |  | uint16_t * | pData
 | ) |  |

Reads an MDIOS input register.

Parameters:
hmdios,: mdios handle
RegNum,: MDIOS input register address
pData,: pointer to Data
Return values:
HAL status

Definition at line 601 of file stm32h7xx_hal_mdios.c.

References assert_param, IS_MDIOS_REGISTER, and MDIOS_DIN_BASE_ADDR.

void HAL_MDIOS_WakeUpCallback ( MDIOS_HandleTypeDef * hmdios )

MDIOS WAKEUP interrupt callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 874 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

void HAL_MDIOS_WriteCpltCallback ( MDIOS_HandleTypeDef * hmdios )

Write Complete Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 829 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_MDIOS_WriteReg | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum,
 |  | uint16_t | Data
 | ) |  |

Writes to an MDIOS output register.

Parameters:
hmdios,: mdios handle
RegNum,: MDIOS output register address
Data,: Data to write
Return values:
HAL status

Definition at line 572 of file stm32h7xx_hal_mdios.c.

References assert_param, IS_MDIOS_REGISTER, and MDIOS_DOUT_BASE_ADDR.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
MDIOS Exported Functions

MDIOS control functions. More...

Functions

uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error code.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

MDIOS control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the MDIOS.
     (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
     (+) HAL_MDIOS_GetError() API, returns the errors code of the HAL state machine.

Function Documentation

uint32_t HAL_MDIOS_GetError ( MDIOS_HandleTypeDef * hmdios )

Gets MDIOS error code.

Parameters:
hmdios,: mdios handle
Return values:
mdios error code

Definition at line 909 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::ErrorCode.

HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState ( MDIOS_HandleTypeDef * hmdios )

Return the MDIOS HAL state.

Parameters:
hmdios,: mdios handle
Return values:
HAL state

Definition at line 920 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS State structures definition

Enumerations
MDIOS State structures definition
MDIOS Exported Types

Enumerations

enum HAL_MDIOS_StateTypeDef { HAL_MDIOS_STATE_RESET = 0x00U, HAL_MDIOS_STATE_READY = 0x01U, HAL_MDIOS_STATE_BUSY = 0x02U, HAL_MDIOS_STATE_ERROR = 0x04U }

Enumeration Type Documentation

enum HAL_MDIOS_StateTypeDef
Enumerator:
HAL_MDIOS_STATE_RESET

Peripheral not yet Initialized or disabled

HAL_MDIOS_STATE_READY

Peripheral Initialized and ready for use

HAL_MDIOS_STATE_BUSY

an internal process is ongoing

HAL_MDIOS_STATE_ERROR

Reception process is ongoing

Definition at line 51 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDIOS_InitTypeDef Struct Reference
MDIOS Init Structure definition

#include <stm32h7xx_hal_mdios.h>

Data Fields

uint32_t | PortAddress
uint32_t | PreambleCheck

Detailed Description

Definition at line 67 of file stm32h7xx_hal_mdios.h.

Field Documentation

uint32_t MDIOS_InitTypeDef::PortAddress

Specifies the MDIOS port address. This parameter can be a value from 0 to 31

Definition at line 69 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

uint32_t MDIOS_InitTypeDef::PreambleCheck

Specifies whether the preamble check is enabled or disabled. This parameter can be a value of MDIOS Preamble Check

Definition at line 71 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdios.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS handle Structure definition

Data Structures | Typedefs
MDIOS handle Structure definition
MDIOS Exported Types

Data Structures

struct __MDIOS_HandleTypeDef

Typedefs

typedef struct
__MDIOS_HandleTypeDef 		MDIOS_HandleTypeDef

Typedef Documentation

typedef struct __MDIOS_HandleTypeDef MDIOS_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __MDIOS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__MDIOS_HandleTypeDef Struct Reference
MDIOS handle Structure definition

#include <stm32h7xx_hal_mdios.h>

Data Fields

MDIOS_TypeDef * | Instance
MDIOS_InitTypeDef Init
__IO HAL_MDIOS_StateTypeDef | State
__IO uint32_t | ErrorCode
HAL_LockTypeDef | Lock
void(* | WriteCpltCallback )(struct __MDIOS_HandleTypeDef *hmdios)
void(* | ReadCpltCallback )(struct __MDIOS_HandleTypeDef *hmdios)
void(* | ErrorCallback )(struct __MDIOS_HandleTypeDef *hmdios)
void(* | WakeUpCallback )(struct __MDIOS_HandleTypeDef *hmdios)
void(* | MspInitCallback )(struct __MDIOS_HandleTypeDef *hmdios)
void(* | MspDeInitCallback )(struct __MDIOS_HandleTypeDef *hmdios)

Detailed Description

Definition at line 84 of file stm32h7xx_hal_mdios.h.

Field Documentation

void(* __MDIOS_HandleTypeDef::ErrorCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Error Callback

Definition at line 105 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_RegisterCallback(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

__IO uint32_t __MDIOS_HandleTypeDef::ErrorCode

Holds the global Error code of the MDIOS HAL status machine This parameter can be a value of of MDIOS Error Code

Definition at line 96 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_GetError(), HAL_MDIOS_Init(), HAL_MDIOS_IRQHandler(), HAL_MDIOS_RegisterCallback(), and HAL_MDIOS_UnRegisterCallback().

MDIOS_InitTypeDef __MDIOS_HandleTypeDef::Init

MDIOS Init Structure

Definition at line 91 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

MDIOS_TypeDef* __MDIOS_HandleTypeDef::Instance

Register base address

Definition at line 89 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_DeInit(), HAL_MDIOS_GetReadRegAddress(), HAL_MDIOS_GetWrittenRegAddress(), HAL_MDIOS_Init(), and HAL_MDIOS_IRQHandler().

HAL_LockTypeDef __MDIOS_HandleTypeDef::Lock

MDIOS Lock

Definition at line 99 of file stm32h7xx_hal_mdios.h.

void(* __MDIOS_HandleTypeDef::MspDeInitCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Msp DeInit callback

Definition at line 109 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_DeInit(), HAL_MDIOS_RegisterCallback(), and HAL_MDIOS_UnRegisterCallback().

void(* __MDIOS_HandleTypeDef::MspInitCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Msp Init callback

Definition at line 108 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init(), HAL_MDIOS_RegisterCallback(), and HAL_MDIOS_UnRegisterCallback().

void(* __MDIOS_HandleTypeDef::ReadCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Read Complete Callback

Definition at line 104 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_RegisterCallback(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

__IO HAL_MDIOS_StateTypeDef __MDIOS_HandleTypeDef::State

MDIOS communication state This parameter can be a value of of HAL_MDIOS_StateTypeDef

Definition at line 93 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_DeInit(), HAL_MDIOS_GetState(), HAL_MDIOS_Init(), HAL_MDIOS_RegisterCallback(), and HAL_MDIOS_UnRegisterCallback().

void(* __MDIOS_HandleTypeDef::WakeUpCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Wake UP Callback

Definition at line 106 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_RegisterCallback(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

void(* __MDIOS_HandleTypeDef::WriteCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios)

MDIOS Write Complete Callback

Definition at line 103 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler(), HAL_MDIOS_RegisterCallback(), HAL_MDIOS_UnRegisterCallback(), and MDIOS_InitCallbacksToDefault().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdios.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Exported Types

Modules | Typedefs | Enumerations
MDIOS Exported Types
MDIOS

Modules

MDIOS State structures definition
MDIOS Init Structure definition
MDIOS handle Structure definition

Typedefs

typedef void(* pMDIOS_CallbackTypeDef )(MDIOS_HandleTypeDef *hmdios)
HAL MDIOS Callback pointer definition.

Enumerations

enum HAL_MDIOS_CallbackIDTypeDef {
HAL_MDIOS_MSPINIT_CB_ID = 0x00U, HAL_MDIOS_MSPDEINIT_CB_ID = 0x01U, HAL_MDIOS_WRITE_COMPLETE_CB_ID = 0x02U, HAL_MDIOS_READ_COMPLETE_CB_ID = 0x03U,
HAL_MDIOS_ERROR_CB_ID = 0x04U, HAL_MDIOS_WAKEUP_CB_ID = 0x05U
}
HAL MDIOS Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef *hmdios)

HAL MDIOS Callback pointer definition.

pointer to an MDIOS callback function

Definition at line 136 of file stm32h7xx_hal_mdios.h.

Enumeration Type Documentation

enum HAL_MDIOS_CallbackIDTypeDef

HAL MDIOS Callback ID enumeration definition.

Enumerator:
HAL_MDIOS_MSPINIT_CB_ID

MDIOS MspInit callback ID

HAL_MDIOS_MSPDEINIT_CB_ID

MDIOS MspDeInit callback ID

HAL_MDIOS_WRITE_COMPLETE_CB_ID

MDIOS Write Complete Callback ID

HAL_MDIOS_READ_COMPLETE_CB_ID

MDIOS Read Complete Callback ID

HAL_MDIOS_ERROR_CB_ID

MDIOS Error Callback ID

HAL_MDIOS_WAKEUP_CB_ID

MDIOS Wake UP Callback ID

Definition at line 122 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Preamble Check

Defines
MDIOS Preamble Check
MDIOS Exported Constants

Defines

#define | MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define | MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC

Define Documentation

#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC

Definition at line 153 of file stm32h7xx_hal_mdios.h.

#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)

Definition at line 152 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Input Output Registers Definitions

Defines
MDIOS Input Output Registers Definitions
MDIOS Exported Constants

Defines

#define | MDIOS_REG0 ((uint32_t)0x00000000U)
#define | MDIOS_REG1 ((uint32_t)0x00000001U)
#define | MDIOS_REG2 ((uint32_t)0x00000002U)
#define | MDIOS_REG3 ((uint32_t)0x00000003U)
#define | MDIOS_REG4 ((uint32_t)0x00000004U)
#define | MDIOS_REG5 ((uint32_t)0x00000005U)
#define | MDIOS_REG6 ((uint32_t)0x00000006U)
#define | MDIOS_REG7 ((uint32_t)0x00000007U)
#define | MDIOS_REG8 ((uint32_t)0x00000008U)
#define | MDIOS_REG9 ((uint32_t)0x00000009U)
#define | MDIOS_REG10 ((uint32_t)0x0000000AU)
#define | MDIOS_REG11 ((uint32_t)0x0000000BU)
#define | MDIOS_REG12 ((uint32_t)0x0000000CU)
#define | MDIOS_REG13 ((uint32_t)0x0000000DU)
#define | MDIOS_REG14 ((uint32_t)0x0000000EU)
#define | MDIOS_REG15 ((uint32_t)0x0000000FU)
#define | MDIOS_REG16 ((uint32_t)0x00000010U)
#define | MDIOS_REG17 ((uint32_t)0x00000011U)
#define | MDIOS_REG18 ((uint32_t)0x00000012U)
#define | MDIOS_REG19 ((uint32_t)0x00000013U)
#define | MDIOS_REG20 ((uint32_t)0x00000014U)
#define | MDIOS_REG21 ((uint32_t)0x00000015U)
#define | MDIOS_REG22 ((uint32_t)0x00000016U)
#define | MDIOS_REG23 ((uint32_t)0x00000017U)
#define | MDIOS_REG24 ((uint32_t)0x00000018U)
#define | MDIOS_REG25 ((uint32_t)0x00000019U)
#define | MDIOS_REG26 ((uint32_t)0x0000001AU)
#define | MDIOS_REG27 ((uint32_t)0x0000001BU)
#define | MDIOS_REG28 ((uint32_t)0x0000001CU)
#define | MDIOS_REG29 ((uint32_t)0x0000001DU)
#define | MDIOS_REG30 ((uint32_t)0x0000001EU)
#define | MDIOS_REG31 ((uint32_t)0x0000001FU)

Define Documentation

#define MDIOS_REG0 ((uint32_t)0x00000000U)

Definition at line 161 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG1 ((uint32_t)0x00000001U)

Definition at line 162 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG10 ((uint32_t)0x0000000AU)

Definition at line 171 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG11 ((uint32_t)0x0000000BU)

Definition at line 172 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG12 ((uint32_t)0x0000000CU)

Definition at line 173 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG13 ((uint32_t)0x0000000DU)

Definition at line 174 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG14 ((uint32_t)0x0000000EU)

Definition at line 175 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG15 ((uint32_t)0x0000000FU)

Definition at line 176 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG16 ((uint32_t)0x00000010U)

Definition at line 177 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG17 ((uint32_t)0x00000011U)

Definition at line 178 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG18 ((uint32_t)0x00000012U)

Definition at line 179 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG19 ((uint32_t)0x00000013U)

Definition at line 180 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG2 ((uint32_t)0x00000002U)

Definition at line 163 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG20 ((uint32_t)0x00000014U)

Definition at line 181 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG21 ((uint32_t)0x00000015U)

Definition at line 182 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG22 ((uint32_t)0x00000016U)

Definition at line 183 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG23 ((uint32_t)0x00000017U)

Definition at line 184 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG24 ((uint32_t)0x00000018U)

Definition at line 185 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG25 ((uint32_t)0x00000019U)

Definition at line 186 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG26 ((uint32_t)0x0000001AU)

Definition at line 187 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG27 ((uint32_t)0x0000001BU)

Definition at line 188 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG28 ((uint32_t)0x0000001CU)

Definition at line 189 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG29 ((uint32_t)0x0000001DU)

Definition at line 190 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG3 ((uint32_t)0x00000003U)

Definition at line 164 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG30 ((uint32_t)0x0000001EU)

Definition at line 191 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG31 ((uint32_t)0x0000001FU)

Definition at line 192 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG4 ((uint32_t)0x00000004U)

Definition at line 165 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG5 ((uint32_t)0x00000005U)

Definition at line 166 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG6 ((uint32_t)0x00000006U)

Definition at line 167 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG7 ((uint32_t)0x00000007U)

Definition at line 168 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG8 ((uint32_t)0x00000008U)

Definition at line 169 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG9 ((uint32_t)0x00000009U)

Definition at line 170 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Registers Flags

Defines
MDIOS Registers Flags
MDIOS Exported Constants

Defines

#define | MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define | MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define | MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define | MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define | MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define | MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define | MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define | MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define | MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define | MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define | MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define | MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define | MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define | MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define | MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define | MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define | MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define | MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define | MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define | MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define | MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define | MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define | MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define | MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define | MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define | MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define | MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define | MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define | MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define | MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define | MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define | MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define | MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)

Define Documentation

#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)

Definition at line 232 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)

Definition at line 200 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)

Definition at line 210 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)

Definition at line 211 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)

Definition at line 212 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)

Definition at line 213 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)

Definition at line 214 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)

Definition at line 215 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)

Definition at line 216 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)

Definition at line 217 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)

Definition at line 218 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)

Definition at line 219 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)

Definition at line 201 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)

Definition at line 220 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)

Definition at line 221 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)

Definition at line 222 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)

Definition at line 223 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)

Definition at line 224 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)

Definition at line 225 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)

Definition at line 226 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)

Definition at line 227 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)

Definition at line 228 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)

Definition at line 229 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)

Definition at line 202 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)

Definition at line 230 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)

Definition at line 231 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)

Definition at line 203 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)

Definition at line 204 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)

Definition at line 205 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)

Definition at line 206 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)

Definition at line 207 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)

Definition at line 208 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)

Definition at line 209 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Interrupt Sources

Defines
Interrupt Sources
MDIOS Exported Constants

Defines

#define | MDIOS_IT_WRITE MDIOS_CR_WRIE
#define | MDIOS_IT_READ MDIOS_CR_RDIE
#define | MDIOS_IT_ERROR MDIOS_CR_EIE

Define Documentation

#define MDIOS_IT_ERROR MDIOS_CR_EIE

Definition at line 242 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

#define MDIOS_IT_READ MDIOS_CR_RDIE

Definition at line 241 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

#define MDIOS_IT_WRITE MDIOS_CR_WRIE

Definition at line 240 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Interrupt Flags

Defines
MDIOS Interrupt Flags
MDIOS Exported Constants

Defines

#define | MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define | MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define | MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF

Define Documentation

#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF

Definition at line 252 of file stm32h7xx_hal_mdios.h.

#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF

Definition at line 251 of file stm32h7xx_hal_mdios.h.

#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF

Definition at line 250 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Error Code

Defines
MDIOS Error Code
MDIOS Exported Constants

Defines

#define | HAL_MDIOS_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDIOS_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_MDIOS_ERROR_BUSY ((uint32_t)0x00000002U)
#define | HAL_MDIOS_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_MDIOS_ERROR_DATA ((uint32_t)0x00000010U)
#define | HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Define Documentation

#define HAL_MDIOS_ERROR_BUSY ((uint32_t)0x00000002U)

Parameter error

Definition at line 262 of file stm32h7xx_hal_mdios.h.

#define HAL_MDIOS_ERROR_DATA ((uint32_t)0x00000010U)

Data transfer error

Definition at line 264 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Invalid Callback error

Definition at line 266 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_RegisterCallback(), and HAL_MDIOS_UnRegisterCallback().

#define HAL_MDIOS_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 260 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init(), and HAL_MDIOS_IRQHandler().

#define HAL_MDIOS_ERROR_PARAM ((uint32_t)0x00000001U)

Busy error

Definition at line 261 of file stm32h7xx_hal_mdios.h.

#define HAL_MDIOS_ERROR_TIMEOUT ((uint32_t)0x00000004U)

Timeout error

Definition at line 263 of file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Wakeup Line

Defines
MDIOS Wakeup Line
MDIOS Exported Constants

Defines

#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */

Define Documentation

#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */

Definition at line 275 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Exported Macros

Defines
MDIOS Exported Macros
MDIOS

Defines

#define | __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__)
Reset MDIOS handle state.
#define | __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
Enable/Disable the MDIOS peripheral.
#define | __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
#define | __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the MDIOS device interrupt.
#define | __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the MDIOS device interrupt.
#define | __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
Set MDIOS slave get write register flag.
#define | __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
MDIOS slave get read register flag.
#define | __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
MDIOS slave get interrupt.
#define | __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
MDIOS slave clear interrupt.
#define | __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified MDIOS interrupt is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR2 |= (__EXTI_LINE__))
Enable the MDIOS WAKEUP Exti Line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR2 & (__EXTI_LINE__))
checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__))
Clear the MDIOS WAKEUP Exti flag.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_MDIOS_CLEAR_ERROR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)

MDIOS slave clear interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__ : specifies the Error flag. This parameter can be one or a combination of the following values:
  • MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
  • MDIOS_START_ERROR_FLAG: Register read interrupt
  • MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
Return values:
none

Definition at line 369 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)

Definition at line 308 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_DeInit().

#define __HAL_MDIOS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the MDIOS device interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
None

Definition at line 333 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)

Enable/Disable the MDIOS peripheral.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
Return values:
None

Definition at line 307 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the MDIOS device interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
None

Definition at line 321 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents().

#define __HAL_MDIOS_GET_ERROR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR & (__FLAG__))

MDIOS slave get interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__ : specifies the Error flag. This parameter can be one or a combination of the following values:
  • MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
  • MDIOS_START_ERROR_FLAG: Register read interrupt
  • MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
Return values:
The state of the error flag

Definition at line 358 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Checks whether the specified MDIOS interrupt is set or not.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
The state of the interrupt source

Definition at line 381 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_GET_READ_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->RDFR & (__FLAG__))

MDIOS slave get read register flag.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__,: specifies the read register flag
Return values:
The state of read flag

Definition at line 347 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_GET_WRITE_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->WRFR & (__FLAG__))

Set MDIOS slave get write register flag.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__,: specifies the write register flag
Return values:
The state of write flag

Definition at line 340 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->State = HAL_MDIOS_STATE_RESET;      \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0)

Reset MDIOS handle state.

Parameters:
__HANDLE__,: MDIOS handle.
Return values:
None

Definition at line 293 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR2 = (__EXTI_LINE__))

Clear the MDIOS WAKEUP Exti flag.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be cleared. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 429 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR2 &= ~(__EXTI_LINE__));\
                                                                 (EXTI->FTSR2 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP EXTI sources to be disabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 459 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT ( __EXTI_LINE__ ) (EXTI->IMR2 |= (__EXTI_LINE__))

Enable the MDIOS WAKEUP Exti Line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be enabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 390 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
                                                                   (EXTI->RTSR2 |= (__EXTI_LINE__))

enable rising edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP EXTI sources to be disabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 449 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR2 |= (__EXTI_LINE__));\
                                                                          (EXTI->FTSR2 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP EXTI sources to be disabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 469 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER2 |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP EXTI sources to be disabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 479 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR2 & (__EXTI_LINE__))

checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be cleared. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
EXTI MDIOS WAKEUP Line Status.

Definition at line 410 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Private Types

MDIOS Private Types
MDIOS
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Private Variables

MDIOS Private Variables
MDIOS
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Private Constants

MDIOS Private Constants
MDIOS
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Private Macros

Defines
MDIOS Private Macros
MDIOS

Defines

#define | IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U)
#define | IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U)
#define | IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__)

Define Documentation

#define IS_MDIOS_PORTADDRESS ( __ADDR__ ) ((__ADDR__) < 32U)

Definition at line 573 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

#define IS_MDIOS_PREAMBLECHECK ( __PREAMBLECHECK__ )
Value:
(((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
                                                   ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))

Definition at line 577 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

#define IS_MDIOS_REGISTER ( __REGISTER__ ) ((__REGISTER__) < 32U)

Definition at line 575 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_ReadReg(), and HAL_MDIOS_WriteReg().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS Private Functions

MDIOS Private Functions
MDIOS
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDIOS

Modules | Defines | Functions
MDIOS
STM32H7xx_HAL_Driver

HAL MDIOS module driver. More...

Modules

MDIOS Exported Functions
MDIOS Exported Types
MDIOS Exported Constants
MDIOS Exported Macros
MDIOS Private Types
MDIOS Private Variables
MDIOS Private Constants
MDIOS Private Macros
MDIOS Private Functions

Defines

#define | MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define | MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define | MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U)
#define | MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U)

Functions

static void | MDIOS_InitCallbacksToDefault (MDIOS_HandleTypeDef *hmdios)

Detailed Description

HAL MDIOS module driver.

Define Documentation

#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))

Definition at line 148 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)

Definition at line 147 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U)

Definition at line 150 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_ReadReg().

#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U)

Definition at line 151 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_WriteReg().

#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)

Definition at line 146 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_Init().

Function Documentation

static void MDIOS_InitCallbacksToDefault ( MDIOS_HandleTypeDef * hmdios ) [static]

Definition at line 935 of file stm32h7xx_hal_mdios.c.

References __MDIOS_HandleTypeDef::ErrorCallback, HAL_MDIOS_ErrorCallback(), HAL_MDIOS_ReadCpltCallback(), HAL_MDIOS_WakeUpCallback(), HAL_MDIOS_WriteCpltCallback(), __MDIOS_HandleTypeDef::ReadCpltCallback, __MDIOS_HandleTypeDef::WakeUpCallback, and __MDIOS_HandleTypeDef::WriteCpltCallback.

Referenced by HAL_MDIOS_Init().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Exported Types

Data Structures | Typedefs | Enumerations
MDMA Exported Types
MDMA

MDMA Exported Types. More...

Data Structures

struct | MDMA_InitTypeDef
MDMA Configuration Structure definition. More...
struct | MDMA_LinkNodeTypeDef
HAL MDMA linked list node structure definition. More...
struct | MDMA_LinkNodeConfTypeDef
HAL MDMA linked list node configuration structure definition. More...
struct | __MDMA_HandleTypeDef
MDMA handle Structure definition. More...

Typedefs

typedef struct __MDMA_HandleTypeDef | MDMA_HandleTypeDef
MDMA handle Structure definition.

Enumerations

enum HAL_MDMA_StateTypeDef {
HAL_MDMA_STATE_RESET = 0x00U, HAL_MDMA_STATE_READY = 0x01U, HAL_MDMA_STATE_BUSY = 0x02U, HAL_MDMA_STATE_ERROR = 0x03U,
HAL_MDMA_STATE_ABORT = 0x04U
}
HAL MDMA State structure definition. More...
enum | HAL_MDMA_LevelCompleteTypeDef { HAL_MDMA_FULL_TRANSFER = 0x00U, HAL_MDMA_BUFFER_TRANSFER = 0x01U, HAL_MDMA_BLOCK_TRANSFER = 0x02U, HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U }
HAL MDMA Level Complete structure definition. More...
enum HAL_MDMA_CallbackIDTypeDef {
HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U,
HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, HAL_MDMA_XFER_ALL_CB_ID = 0x06U
}
HAL MDMA Callbacks IDs structure definition. More...

Detailed Description

MDMA Exported Types.

Typedef Documentation

typedef struct __MDMA_HandleTypeDef MDMA_HandleTypeDef

MDMA handle Structure definition.

Enumeration Type Documentation

enum HAL_MDMA_CallbackIDTypeDef

HAL MDMA Callbacks IDs structure definition.

Enumerator:
HAL_MDMA_XFER_CPLT_CB_ID

Full transfer

HAL_MDMA_XFER_BUFFERCPLT_CB_ID

Buffer Transfer

HAL_MDMA_XFER_BLOCKCPLT_CB_ID

Block Transfer

HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID

Repeated Block Transfer

HAL_MDMA_XFER_ERROR_CB_ID

Error

HAL_MDMA_XFER_ABORT_CB_ID

Abort

HAL_MDMA_XFER_ALL_CB_ID

All

Definition at line 187 of file stm32h7xx_hal_mdma.h.

enum HAL_MDMA_LevelCompleteTypeDef

HAL MDMA Level Complete structure definition.

Enumerator:
HAL_MDMA_FULL_TRANSFER

Full transfer

HAL_MDMA_BUFFER_TRANSFER

Buffer Transfer

HAL_MDMA_BLOCK_TRANSFER

Block Transfer

HAL_MDMA_REPEAT_BLOCK_TRANSFER

repeat block Transfer

Definition at line 175 of file stm32h7xx_hal_mdma.h.

enum HAL_MDMA_StateTypeDef

HAL MDMA State structure definition.

Enumerator:
HAL_MDMA_STATE_RESET

MDMA not yet initialized or disabled

HAL_MDMA_STATE_READY

MDMA initialized and ready for use

HAL_MDMA_STATE_BUSY

MDMA process is ongoing

HAL_MDMA_STATE_ERROR

MDMA error state

HAL_MDMA_STATE_ABORT

MDMA Abort state

Definition at line 162 of file stm32h7xx_hal_mdma.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_InitTypeDef Struct Reference
MDMA Exported Types

MDMA Configuration Structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

uint32_t | Request
uint32_t | TransferTriggerMode
uint32_t | Priority
uint32_t | Endianness
uint32_t | SourceInc
uint32_t | DestinationInc
uint32_t | SourceDataSize
uint32_t | DestDataSize
uint32_t | DataAlignment
uint32_t | BufferTransferLength
uint32_t | SourceBurst
uint32_t | DestBurst
int32_t | SourceBlockAddressOffset
int32_t | DestBlockAddressOffset

Detailed Description

MDMA Configuration Structure definition.

Definition at line 49 of file stm32h7xx_hal_mdma.h.

Field Documentation

uint32_t MDMA_InitTypeDef::BufferTransferLength

Specifies the buffer Transfer Length (number of bytes), this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)

Definition at line 81 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Resume(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DataAlignment

Specifies the source to destination Memory data packing/padding mode. This parameter can be a value of MDMA data alignment

Definition at line 78 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

int32_t MDMA_InitTypeDef::DestBlockAddressOffset

this field specifies the Next block destination address offset signed value : if > 0 then increment the next block destination Address by offset from where the last block ends if < 0 then decrement the next block destination Address by offset from where the last block ends if == 0, the next block destination address starts from where the last block ends

Definition at line 107 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DestBurst

Specifies the Burst transfer configuration for the destination memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of MDMA Destination burst

Note:
: the burst may be FIXED/INCR based on DestinationInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength

Definition at line 92 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_InitTypeDef::DestDataSize

Specifies the destination data size. This parameter can be a value of MDMA Destination data size

Definition at line 74 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_OSPI_Receive_DMA(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DestinationInc

Specifies if the Destination increment mode . This parameter can be a value of MDMA Destination increment mode

Definition at line 68 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Endianness

Specifies if the MDMA transactions preserve the Little endianness. This parameter can be a value of MDMA Endianness

Definition at line 62 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Priority

Specifies the software priority for the MDMAy channelx. This parameter can be a value of MDMA Priority level

Definition at line 59 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Request

Specifies the MDMA request. This parameter can be a value of MDMA Request selection

Definition at line 52 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), and MDMA_Init().

int32_t MDMA_InitTypeDef::SourceBlockAddressOffset

this field specifies the Next block source address offset signed value : if > 0 then increment the next block source Address by offset from where the last block ends if < 0 then decrement the next block source Address by offset from where the last block ends if == 0, the next block source address starts from where the last block ends

Definition at line 100 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::SourceBurst

Specifies the Burst transfer configuration for the source memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of MDMA Source burst

Note:
: the burst may be FIXED/INCR based on SourceInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength

Definition at line 84 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::SourceDataSize

Specifies the source data size. This parameter can be a value of MDMA Source data size

Definition at line 71 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and HAL_OSPI_Transmit_DMA().

uint32_t MDMA_InitTypeDef::SourceInc

Specifies if the Source increment mode . This parameter can be a value of MDMA Source increment mode

Definition at line 65 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::TransferTriggerMode

Specifies the Trigger Transfer mode : each request triggers a : a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer This parameter can be a value of MDMA Transfer Trigger Mode

Definition at line 55 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA_LinkNodeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_LinkNodeTypeDef Struct Reference
MDMA Exported Types

HAL MDMA linked list node structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

__IO uint32_t | CTCR
__IO uint32_t | CBNDTR
__IO uint32_t | CSAR
__IO uint32_t | CDAR
__IO uint32_t | CBRUR
__IO uint32_t | CLAR
__IO uint32_t | CTBR
__IO uint32_t | Reserved
__IO uint32_t | CMAR
__IO uint32_t | CMDR

Detailed Description

HAL MDMA linked list node structure definition.

Note:
The Linked list node allows to define a new MDMA configuration (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). When CLAR register is configured to a non NULL value , each time a transfer ends, a new configuration (linked list node) is automatically loaded from the address given in CLAR register.

Definition at line 122 of file stm32h7xx_hal_mdma.h.

Field Documentation

__IO uint32_t MDMA_LinkNodeTypeDef::CBNDTR

New CBNDTR register configuration for the given MDMA linked list node

Definition at line 125 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CBRUR

New CBRUR register configuration for the given MDMA linked list node

Definition at line 128 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CDAR

New CDAR register configuration for the given MDMA linked list node

Definition at line 127 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CLAR

New CLAR register configuration for the given MDMA linked list node

Definition at line 129 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CMAR

New CMAR register configuration for the given MDMA linked list node

Definition at line 132 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CMDR

New CMDR register configuration for the given MDMA linked list node

Definition at line 133 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CSAR

New CSAR register configuration for the given MDMA linked list node

Definition at line 126 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CTBR

New CTBR register configuration for the given MDMA linked list node

Definition at line 130 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CTCR

New CTCR register configuration for the given MDMA linked list node

Definition at line 124 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::Reserved

Reserved register

Definition at line 131 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA_LinkNodeConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_LinkNodeConfTypeDef Struct Reference
MDMA Exported Types

HAL MDMA linked list node configuration structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

MDMA_InitTypeDef Init
uint32_t | SrcAddress
uint32_t | DstAddress
uint32_t | BlockDataLength
uint32_t | BlockCount
uint32_t | PostRequestMaskAddress
uint32_t | PostRequestMaskData

Detailed Description

HAL MDMA linked list node configuration structure definition.

Note:
used with HAL_MDMA_LinkedList_CreateNode function

Definition at line 141 of file stm32h7xx_hal_mdma.h.

Field Documentation

uint32_t MDMA_LinkNodeConfTypeDef::BlockCount

The number of blocks to be transferred

Definition at line 147 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::BlockDataLength

The data length of a block in bytes

Definition at line 146 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::DstAddress

The destination memory address for the Linked list Node

Definition at line 145 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

MDMA_InitTypeDef MDMA_LinkNodeConfTypeDef::Init

configuration of the specified MDMA Linked List Node

Definition at line 143 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::PostRequestMaskAddress

specifies the address to be updated (written) with PostRequestMaskData after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served

Definition at line 149 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::PostRequestMaskData

specifies the value to be written to PostRequestMaskAddress after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served

Definition at line 152 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::SrcAddress

The source memory address for the Linked list Node

Definition at line 144 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __MDMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__MDMA_HandleTypeDef Struct Reference
MDMA Exported Types

MDMA handle Structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

MDMA_Channel_TypeDef * | Instance
MDMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_MDMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferBufferCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferBlockCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferRepeatBlockCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferErrorCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferAbortCallback )(struct __MDMA_HandleTypeDef *hmdma)
MDMA_LinkNodeTypeDef * FirstLinkedListNodeAddress
MDMA_LinkNodeTypeDef * LastLinkedListNodeAddress
uint32_t | LinkedListNodeCounter
__IO uint32_t | ErrorCode

Detailed Description

MDMA handle Structure definition.

Definition at line 203 of file stm32h7xx_hal_mdma.h.

Field Documentation

__IO uint32_t __MDMA_HandleTypeDef::ErrorCode

MDMA Error code

Definition at line 240 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Abort(), HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_DeInit(), HAL_MDMA_GenerateSWRequest(), HAL_MDMA_GetError(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

MDMA_LinkNodeTypeDef* __MDMA_HandleTypeDef::FirstLinkedListNodeAddress

specifies the first node address of the transfer list (after the initial node defined by the Init struct) this parameter is used internally by the MDMA driver to construct the linked list node

Definition at line 228 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), HAL_MDMA_LinkedList_RemoveNode(), and MDMA_SetConfig().

MDMA_InitTypeDef __MDMA_HandleTypeDef::Init

MDMA communication parameters

Definition at line 207 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Resume(), HAL_MDMA_Init(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_InitCard(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), MDMA_Init(), and MMC_InitCard().

MDMA_Channel_TypeDef* __MDMA_HandleTypeDef::Instance

Register base address

Definition at line 205 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_ConfigPostRequestMask(), HAL_MDMA_DeInit(), HAL_MDMA_GenerateSWRequest(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_RemoveNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), JPEG_DMA_EndProcess(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), MDMA_Init(), and MDMA_SetConfig().

MDMA_LinkNodeTypeDef* __MDMA_HandleTypeDef::LastLinkedListNodeAddress

specifies the last node address of the transfer list this parameter is used internally by the MDMA driver to construct the linked list node

Definition at line 234 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

uint32_t __MDMA_HandleTypeDef::LinkedListNodeCounter

Number of nodes in the MDMA linked list

Definition at line 238 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

HAL_LockTypeDef __MDMA_HandleTypeDef::Lock

MDMA locking object

Definition at line 209 of file stm32h7xx_hal_mdma.h.

void* __MDMA_HandleTypeDef::Parent

Parent object state

Definition at line 213 of file stm32h7xx_hal_mdma.h.

__IO HAL_MDMA_StateTypeDef __MDMA_HandleTypeDef::State

MDMA transfer state

Definition at line 211 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_ConfigPostRequestMask(), HAL_MDMA_DeInit(), HAL_MDMA_GetState(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), HAL_MDMA_LinkedList_RemoveNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MDMA_UnRegisterCallback(), and JPEG_DMA_ContinueProcess().

void(* __MDMA_HandleTypeDef::XferAbortCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer Abort callback

Definition at line 225 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_OSPI_Abort_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferBlockCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA block transfer complete callback

Definition at line 219 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

void(* __MDMA_HandleTypeDef::XferBufferCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA buffer transfer complete callback

Definition at line 217 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

void(* __MDMA_HandleTypeDef::XferCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer complete callback

Definition at line 215 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferErrorCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer error callback

Definition at line 223 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA block transfer repeat callback

Definition at line 221 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Error Codes

Defines
MDMA Error Codes
MDMA Exported Constants

MDMA Error Codes. More...

Defines

#define | HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)
#define | HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)
#define | HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)
#define | HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)
#define | HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)
#define | HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)
#define | HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)

Detailed Description

MDMA Error Codes.

Define Documentation

#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)

Address/Size alignment error

Definition at line 264 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)

Block Size error

Definition at line 265 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)

DeInit or SW trigger requested with Xfer ongoing

Definition at line 268 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_GenerateSWRequest().

#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)

Linked list Data error

Definition at line 263 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)

Error Mask Data error

Definition at line 262 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)

Abort or SW trigger requested with no Xfer ongoing

Definition at line 267 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_GenerateSWRequest(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 259 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)

Read Transfer error

Definition at line 260 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)

Timeout error

Definition at line 266 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Abort(), HAL_MDMA_Abort(), HAL_MDMA_Init(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)

Write Transfer error

Definition at line 261 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Request selection

Defines
MDMA Request selection
MDMA Exported Constants

MDMA_Request_selection. More...

Defines

#define | MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)
#define | MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)
#define | MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)
#define | MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)
#define | MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)
#define | MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)
#define | MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)
#define | MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)
#define | MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)
#define | MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)
#define | MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)
#define | MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)
#define | MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)
#define | MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)
#define | MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)
#define | MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)
#define | MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)
#define | MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)
#define | MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)
#define | MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)
#define | MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U)
#define | MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U)
#define | MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)
#define | MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)
#define | MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)
#define | MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)
#define | MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)
#define | MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU)
#define | MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U)
#define | MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U)
#define | MDMA_REQUEST_SW ((uint32_t)0x40000000U)

Detailed Description

MDMA_Request_selection.

Define Documentation

#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)

MDMA HW request is DMA1 Stream 0 Transfer Complete Flag

Definition at line 279 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)

MDMA HW request is DMA1 Stream 1 Transfer Complete Flag

Definition at line 280 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)

MDMA HW request is DMA1 Stream 2 Transfer Complete Flag

Definition at line 281 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)

MDMA HW request is DMA1 Stream 3 Transfer Complete Flag

Definition at line 282 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)

MDMA HW request is DMA1 Stream 4 Transfer Complete Flag

Definition at line 283 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)

MDMA HW request is DMA1 Stream 5 Transfer Complete Flag

Definition at line 284 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)

MDMA HW request is DMA1 Stream 6 Transfer Complete Flag

Definition at line 285 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)

MDMA HW request is DMA1 Stream 7 Transfer Complete Flag

Definition at line 286 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)

MDMA HW request is DMA2 Stream 0 Transfer Complete Flag

Definition at line 287 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)

MDMA HW request is DMA2 Stream 1 Transfer Complete Flag

Definition at line 288 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)

MDMA HW request is DMA2 Stream 2 Transfer Complete Flag

Definition at line 289 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)

MDMA HW request is DMA2 Stream 3 Transfer Complete Flag

Definition at line 290 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)

MDMA HW request is DMA2 Stream 4 Transfer Complete Flag

Definition at line 291 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)

MDMA HW request is DMA2 Stream 5 Transfer Complete Flag

Definition at line 292 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)

MDMA HW request is DMA2 Stream 6 Transfer Complete Flag

Definition at line 293 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)

MDMA HW request is DMA2 Stream 7 Transfer Complete Flag

Definition at line 294 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)

MDMA HW request is DMA2D CLUT Transfer Complete Flag

Definition at line 313 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)

MDMA HW request is DMA2D Transfer Complete Flag

Definition at line 314 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)

MDMA HW request is DMA2D Transfer Watermark Flag

Definition at line 315 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)

MDMA HW request is JPEG End of conversion Flag

Definition at line 303 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)

MDMA HW request is JPEG Input FIFO not full Flag

Definition at line 300 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)

MDMA HW request is JPEG Input FIFO threshold Flag

Definition at line 299 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)

MDMA HW request is JPEG Output FIFO not empty Flag

Definition at line 302 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)

MDMA HW request is JPEG Output FIFO threshold Flag

Definition at line 301 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)

MDMA HW request is LTDC Line interrupt Flag

Definition at line 296 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U)

MDMA HW request is OCTOSPI1 FIFO threshold Flag

Definition at line 306 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U)

MDMA HW request is OCTOSPI1 Transfer complete Flag

Definition at line 307 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U)

MDMA HW request is OCTOSPI2 FIFO threshold Flag

Definition at line 328 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U)

MDMA HW request is OCTOSPI2 Transfer complete Flag

Definition at line 329 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU)

MDMA HW request is SDMMC1 Command End Flag

Definition at line 325 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)

MDMA HW request is SDMMC1 Internal DMA buffer End Flag

Definition at line 324 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)

MDMA HW request is SDMMC1 End of Data Flag

Definition at line 322 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SW ((uint32_t)0x40000000U)

MDMA SW request

Definition at line 332 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), and MDMA_Init().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Transfer Trigger Mode

Defines
MDMA Transfer Trigger Mode
MDMA Exported Constants

MDMA Transfer Trigger Mode. More...

Defines

#define | MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)
#define | MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)
#define | MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)
#define | MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)

Detailed Description

MDMA Transfer Trigger Mode.

Define Documentation

#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)

Each MDMA request (SW or HW) triggers a block transfer

Definition at line 343 of file stm32h7xx_hal_mdma.h.

#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)

Each MDMA request (SW or HW) triggers a buffer transfer

Definition at line 342 of file stm32h7xx_hal_mdma.h.

#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)

Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any

Definition at line 345 of file stm32h7xx_hal_mdma.h.

#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)

Each MDMA request (SW or HW) triggers a repeated block transfer

Definition at line 344 of file stm32h7xx_hal_mdma.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Priority level

Defines
MDMA Priority level
MDMA Exported Constants

MDMA Priority level. More...

Defines

#define | MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)
#define | MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)
#define | MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)

Detailed Description

MDMA Priority level.

Define Documentation

#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)

Priority level: High

Definition at line 357 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level: Low

Definition at line 355 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)

Priority level: Medium

Definition at line 356 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)

Priority level: Very High

Definition at line 358 of file stm32h7xx_hal_mdma.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Endianness

Defines
MDMA Endianness
MDMA Exported Constants

MDMA Endianness. More...

Defines

#define | MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)
#define | MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)
#define | MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)
#define | MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)

Detailed Description

MDMA Endianness.

Define Documentation

#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)

BYTEs endianness exchange when destination data size is > Byte

Definition at line 370 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)

little endianness preserve

Definition at line 369 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)

HALF WORDs endianness exchange when destination data size is > HALF WORD

Definition at line 371 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)

WORDs endianness exchange when destination data size is > DOUBLE WORD

Definition at line 372 of file stm32h7xx_hal_mdma.h.

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STM32H7B3xQ HAL User Manual: MDMA Source increment mode

Defines
MDMA Source increment mode
MDMA Exported Constants

MDMA Source increment mode. More...

Defines

#define | MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)
#define | MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)
#define | MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)

Detailed Description

MDMA Source increment mode.

Define Documentation

#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)

Source address pointer is decremented by a BYTE (8 bits)

Definition at line 387 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)

Source address pointer is decremented by a double Word (64 bits))

Definition at line 390 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)

Source address pointer is decremented by a half Word (16 bits)

Definition at line 388 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)

Source address pointer is decremented by a Word (32 bits)

Definition at line 389 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)

Source address pointer is incremented by a BYTE (8 bits)

Definition at line 383 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)

Source address pointer is fixed

Definition at line 382 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)

Source address pointer is incremented by a double Word (64 bits))

Definition at line 386 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)

Source address pointer is incremented by a half Word (16 bits)

Definition at line 384 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)

Source address pointer is incremented by a Word (32 bits)

Definition at line 385 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

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STM32H7B3xQ HAL User Manual: MDMA Destination increment mode

Defines
MDMA Destination increment mode
MDMA Exported Constants

MDMA Destination increment mode. More...

Defines

#define | MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)
#define | MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)
#define | MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)

Detailed Description

MDMA Destination increment mode.

Define Documentation

#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)

Source address pointer is decremented by a BYTE (8 bits)

Definition at line 405 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)

Source address pointer is decremented by a double Word (64 bits))

Definition at line 408 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)

Source address pointer is decremented by a half Word (16 bits)

Definition at line 406 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)

Source address pointer is decremented by a Word (32 bits)

Definition at line 407 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)

Source address pointer is incremented by a BYTE (8 bits)

Definition at line 401 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)

Source address pointer is fixed

Definition at line 400 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)

Source address pointer is incremented by a double Word (64 bits))

Definition at line 404 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)

Source address pointer is incremented by a half Word (16 bits)

Definition at line 402 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)

Source address pointer is incremented by a Word (32 bits)

Definition at line 403 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

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STM32H7B3xQ HAL User Manual: MDMA Source data size

Defines
MDMA Source data size
MDMA Exported Constants

MDMA Source data size. More...

Defines

#define | MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)
#define | MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)
#define | MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)

Detailed Description

MDMA Source data size.

Define Documentation

#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)

Source data size is Byte

Definition at line 418 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)

Source data size is double word

Definition at line 421 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)

Source data size is half word

Definition at line 419 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)

Source data size is word

Definition at line 420 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Transmit_DMA().

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STM32H7B3xQ HAL User Manual: MDMA Destination data size

Defines
MDMA Destination data size
MDMA Exported Constants

MDMA Destination data size. More...

Defines

#define | MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)
#define | MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)
#define | MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)

Detailed Description

MDMA Destination data size.

Define Documentation

#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)

Destination data size is Byte

Definition at line 431 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)

Destination data size is double word

Definition at line 434 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)

Destination data size is half word

Definition at line 432 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)

Destination data size is word

Definition at line 433 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_OSPI_Receive_DMA().

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STM32H7B3xQ HAL User Manual: MDMA data alignment

Defines
MDMA data alignment
MDMA Exported Constants

MDMA data alignment. More...

Defines

#define | MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)
#define | MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)
#define | MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)

Detailed Description

MDMA data alignment.

Define Documentation

#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)

Left Aligned (padded with 0s)

Definition at line 449 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)

The source data is packed/un-packed into the destination data size All data are right aligned, in Little Endien mode.

Definition at line 444 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)

Right Aligned, padded w/ 0s (default)

Definition at line 446 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)

Right Aligned, Sign extended , Note : this mode is allowed only if the Source data size is smaller than Destination data size

Definition at line 447 of file stm32h7xx_hal_mdma.h.

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STM32H7B3xQ HAL User Manual: MDMA Source burst

Defines
MDMA Source burst
MDMA Exported Constants

MDMA Source burst. More...

Defines

#define | MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)
#define | MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)

Detailed Description

MDMA Source burst.

Define Documentation

#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)

Burst 128 beats

Definition at line 466 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)

Burst 16 beats

Definition at line 463 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)

Burst 2 beats

Definition at line 460 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)

Burst 32 beats

Definition at line 464 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)

Burst 4 beats

Definition at line 461 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)

Burst 64 beats

Definition at line 465 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)

Burst 8 beats

Definition at line 462 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)

single transfer

Definition at line 459 of file stm32h7xx_hal_mdma.h.

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STM32H7B3xQ HAL User Manual: MDMA Destination burst

Defines
MDMA Destination burst
MDMA Exported Constants

MDMA Destination burst. More...

Defines

#define | MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)
#define | MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)

Detailed Description

MDMA Destination burst.

Define Documentation

#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)

Burst 128 beats

Definition at line 483 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)

Burst 16 beats

Definition at line 480 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)

Burst 2 beats

Definition at line 477 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)

Burst 32 beats

Definition at line 481 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)

Burst 4 beats

Definition at line 478 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)

Burst 64 beats

Definition at line 482 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)

Burst 8 beats

Definition at line 479 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)

single transfer

Definition at line 476 of file stm32h7xx_hal_mdma.h.

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STM32H7B3xQ HAL User Manual: MDMA interrupt enable definitions

Defines
MDMA interrupt enable definitions
MDMA Exported Constants

MDMA interrupt enable definitions. More...

Defines

#define | MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)
#define | MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)
#define | MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)
#define | MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)
#define | MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)

Detailed Description

MDMA interrupt enable definitions.

Define Documentation

#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)

Buffer Transfer Complete interrupt

Definition at line 497 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)

Block Repeat Transfer interrupt

Definition at line 495 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)

Block Transfer interrupt

Definition at line 496 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)

Channel Transfer Complete interrupt

Definition at line 494 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)

Transfer Error interrupt

Definition at line 493 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

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STM32H7B3xQ HAL User Manual: MDMA flag definitions

Defines
MDMA flag definitions
MDMA Exported Constants

MDMA flag definitions. More...

Defines

#define | MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)
#define | MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)
#define | MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)
#define | MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)
#define | MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)
#define | MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)

Detailed Description

MDMA flag definitions.

Define Documentation

#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)

BuFfer Transfer complete flag

Definition at line 511 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)

Block Repeat Transfer complete flag

Definition at line 509 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)

Block Transfer complete flag

Definition at line 510 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)

Channel ReQest Active flag

Definition at line 512 of file stm32h7xx_hal_mdma.h.

#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)

Channel Transfer Complete flag

Definition at line 508 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)

Transfer Error flag

Definition at line 507 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Exported Macros

Defines
MDMA Exported Macros
MDMA

Defines

#define | __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
Enable the specified MDMA Channel.
#define | __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
Disable the specified MDMA Channel.
#define | __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
Get the MDMA Channel pending flags.
#define | __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
Clear the MDMA Stream pending flags.
#define | __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified MDMA Channel interrupt is enabled or not.

Define Documentation

#define __HAL_MDMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CIFCR = (__FLAG__))

Clear the MDMA Stream pending flags.

Parameters:
__HANDLE__,: MDMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • MDMA_FLAG_TE : Transfer Error flag.
  • MDMA_FLAG_CTC : Channel Transfer Complete flag.
  • MDMA_FLAG_BRT : Block Repeat Transfer flag.
  • MDMA_FLAG_BT : Block Transfer complete flag.
  • MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
Return values:
None

Definition at line 569 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

#define __HAL_MDMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)

Disable the specified MDMA Channel.

Parameters:
__HANDLE__,: MDMA handle
Return values:
None

Definition at line 540 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define __HAL_MDMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disables the specified MDMA Channel interrupts.

Parameters:
__HANDLE__,: MDMA handle
__INTERRUPT__,: specifies the MDMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
None

Definition at line 597 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), and HAL_MDMA_IRQHandler().

#define __HAL_MDMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)

Enable the specified MDMA Channel.

Parameters:
__HANDLE__,: MDMA handle
Return values:
None

Definition at line 533 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define __HAL_MDMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enables the specified MDMA Channel interrupts.

Parameters:
__HANDLE__,: MDMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
None

Definition at line 583 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Start_IT().

#define __HAL_MDMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CISR & (__FLAG__))

Get the MDMA Channel pending flags.

Parameters:
__HANDLE__,: MDMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • MDMA_FLAG_TE : Transfer Error flag.
  • MDMA_FLAG_CTC : Channel Transfer Complete flag.
  • MDMA_FLAG_BRT : Block Repeat Transfer flag.
  • MDMA_FLAG_BT : Block Transfer complete flag.
  • MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
  • MDMA_FLAG_CRQA : Channel ReQest Active flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 555 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define __HAL_MDMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Checks whether the specified MDMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check.
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
The state of MDMA_IT (SET or RESET).

Definition at line 610 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
MDMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to :
      Initialize and de-initialize the MDMA channel.
      Register and Unregister MDMA callbacks
    [..]
    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
    reference manual.
    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
    respectevely to register/unregister an MDMA callback function.

Function Documentation

HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | MaskAddress,
 |  | uint32_t | MaskData
 | ) |  |

Config the Post request Mask address and Mask data.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
MaskAddress,: specifies the address to be updated (written) with MaskData after a request is served.
MaskData,: specifies the value to be written to MaskAddress after a request is served. MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
Return values:
HAL status

Definition at line 348 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_DeInit ( MDMA_HandleTypeDef * hmdma )

DeInitializes the MDMA peripheral.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 295 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __MDMA_HandleTypeDef::ErrorCode, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_RESET, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Init ( MDMA_HandleTypeDef * hmdma )

Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.

Parameters:
hmdma,: Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 219 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, assert_param, MDMA_InitTypeDef::BufferTransferLength, MDMA_InitTypeDef::DataAlignment, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestBurst, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_InitTypeDef::Endianness, __MDMA_HandleTypeDef::ErrorCode, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_GetTick(), HAL_MDMA_ERROR_NONE, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, HAL_TIMEOUT_MDMA_ABORT, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_ADDR_OFFSET, IS_MDMA_BUFFER_TRANSFER_LENGTH, IS_MDMA_DATA_ALIGNMENT, IS_MDMA_DESTINATION_BURST, IS_MDMA_DESTINATION_DATASIZE, IS_MDMA_DESTINATION_INC, IS_MDMA_ENDIANNESS_MODE, IS_MDMA_PRIORITY, IS_MDMA_REQUEST, IS_MDMA_SOURCE_BURST, IS_MDMA_SOURCE_DATASIZE, IS_MDMA_SOURCE_INC, IS_MDMA_TRANSFER_TRIGGER_MODE, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, MDMA_Init(), MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, MDMA_InitTypeDef::SourceDataSize, MDMA_InitTypeDef::SourceInc, __MDMA_HandleTypeDef::State, and MDMA_InitTypeDef::TransferTriggerMode.

HAL_StatusTypeDef HAL_MDMA_RegisterCallback | ( | MDMA_HandleTypeDef * | hmdma,
 |  | HAL_MDMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(MDMA_HandleTypeDef *_hmdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CallbackID,: User Callback identifier
pCallback,: pointer to callbacsk function.
Return values:
HAL status

Definition at line 410 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, HAL_MDMA_XFER_ABORT_CB_ID, HAL_MDMA_XFER_BLOCKCPLT_CB_ID, HAL_MDMA_XFER_BUFFERCPLT_CB_ID, HAL_MDMA_XFER_CPLT_CB_ID, HAL_MDMA_XFER_ERROR_CB_ID, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback | ( | MDMA_HandleTypeDef * | hmdma,
 |  | HAL_MDMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CallbackID,: User Callback identifier a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 475 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, HAL_MDMA_XFER_ABORT_CB_ID, HAL_MDMA_XFER_ALL_CB_ID, HAL_MDMA_XFER_BLOCKCPLT_CB_ID, HAL_MDMA_XFER_BUFFERCPLT_CB_ID, HAL_MDMA_XFER_CPLT_CB_ID, HAL_MDMA_XFER_ERROR_CB_ID, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Linked List operation functions

Functions
Linked List operation functions
MDMA Exported Functions

Linked list operation functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.

Detailed Description

Linked list operation functions.

 ===============================================================================
                      #####  Linked list operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Create a linked list node
      (+) Add a node to the MDMA linked list
      (+) Remove a node from the MDMA linked list
      (+) Enable/Disable linked list circular mode

Function Documentation

HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode | ( | MDMA_HandleTypeDef * | hmdma,
 |  | MDMA_LinkNodeTypeDef * | pNewNode,
 |  | MDMA_LinkNodeTypeDef * | pPrevNode
 | ) |  |

Connect a node to the linked list.

Parameters:
hmdma | : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
pNewNode | : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node to be add to the list.
pPrevNode | : Pointer to the new node position in the linked list or zero to insert the new node at the end of the list
Return values:
HAL status

Definition at line 712 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode | ( | MDMA_LinkNodeTypeDef * | pNode,
 |  | MDMA_LinkNodeConfTypeDef * | pNodeConfig
 | ) |  |

Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .

Parameters:
pNode,: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node registers configurations.
pNodeConfig,: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains the configuration information for the specified MDMA Linked List Node.
Return values:
HAL status

Definition at line 569 of file stm32h7xx_hal_mdma.c.

References assert_param, MDMA_LinkNodeConfTypeDef::BlockCount, MDMA_LinkNodeConfTypeDef::BlockDataLength, MDMA_InitTypeDef::BufferTransferLength, MDMA_LinkNodeTypeDef::CBNDTR, MDMA_LinkNodeTypeDef::CBRUR, MDMA_LinkNodeTypeDef::CDAR, MDMA_LinkNodeTypeDef::CLAR, MDMA_LinkNodeTypeDef::CMAR, MDMA_LinkNodeTypeDef::CMDR, MDMA_LinkNodeTypeDef::CSAR, MDMA_LinkNodeTypeDef::CTBR, MDMA_LinkNodeTypeDef::CTCR, MDMA_InitTypeDef::DataAlignment, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestBurst, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_LinkNodeConfTypeDef::DstAddress, MDMA_InitTypeDef::Endianness, MDMA_LinkNodeConfTypeDef::Init, IS_MDMA_BLOCK_ADDR_OFFSET, IS_MDMA_BLOCK_COUNT, IS_MDMA_BUFFER_TRANSFER_LENGTH, IS_MDMA_DATA_ALIGNMENT, IS_MDMA_DESTINATION_BURST, IS_MDMA_DESTINATION_DATASIZE, IS_MDMA_DESTINATION_INC, IS_MDMA_ENDIANNESS_MODE, IS_MDMA_PRIORITY, IS_MDMA_REQUEST, IS_MDMA_SOURCE_BURST, IS_MDMA_SOURCE_DATASIZE, IS_MDMA_SOURCE_INC, IS_MDMA_TRANSFER_LENGTH, IS_MDMA_TRANSFER_TRIGGER_MODE, MDMA_REQUEST_SW, MDMA_LinkNodeConfTypeDef::PostRequestMaskAddress, MDMA_LinkNodeConfTypeDef::PostRequestMaskData, MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_LinkNodeTypeDef::Reserved, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, MDMA_InitTypeDef::SourceDataSize, MDMA_InitTypeDef::SourceInc, MDMA_LinkNodeConfTypeDef::SrcAddress, and MDMA_InitTypeDef::TransferTriggerMode.

HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode ( MDMA_HandleTypeDef * hmdma )

Disable the linked list circular mode by setting the last node connection to null.

Parameters:
hmdma : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 1002 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode ( MDMA_HandleTypeDef * hmdma )

Make the linked list circular by connecting the last node to the first.

Parameters:
hmdma : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 958 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode | ( | MDMA_HandleTypeDef * | hmdma,
 |  | MDMA_LinkNodeTypeDef * | pNode
 | ) |  |

Disconnect/Remove a node from the transfer linked list.

Parameters:
hmdma | : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
pNode | : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node to be removed from the list.
Return values:
HAL status

Definition at line 845 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I/O operation functions

Functions
I/O operation functions
MDMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start MDMA transfer
      (+) Configure the source, destination address and data length and
          Start MDMA transfer with interrupt
      (+) Abort MDMA transfer
      (+) Poll for transfer complete
      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
      (+) Handle MDMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_MDMA_Abort ( MDMA_HandleTypeDef * hmdma )

Aborts the MDMA Transfer.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Note:
After disabling a MDMA Channel, a check for wait until the MDMA Channel is effectively disabled is added. If a Channel is disabled while a data transfer is ongoing, the current data will be transferred and the Channel will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 1216 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __HAL_MDMA_DISABLE_IT, __MDMA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, HAL_TIMEOUT_MDMA_ABORT, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, and __MDMA_HandleTypeDef::State.

Referenced by HAL_JPEG_Abort(), HAL_MDMA_PollForTransfer(), and HAL_OSPI_Abort().

HAL_StatusTypeDef HAL_MDMA_Abort_IT ( MDMA_HandleTypeDef * hmdma )

Aborts the MDMA Transfer in Interrupt mode.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 1281 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_STATE_ABORT, HAL_MDMA_STATE_BUSY, and __MDMA_HandleTypeDef::State.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_IRQHandler(), and JPEG_DMA_ContinueProcess().

HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest ( MDMA_HandleTypeDef * hmdma )

Generate an MDMA SW request trigger to activate the request on the given Channel.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
HAL status

Definition at line 1463 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_BUSY, HAL_MDMA_ERROR_NO_XFER, and __MDMA_HandleTypeDef::Instance.

void HAL_MDMA_IRQHandler ( MDMA_HandleTypeDef * hmdma )

Handles MDMA interrupt request.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
None

Definition at line 1505 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __HAL_MDMA_DISABLE_IT, __HAL_MDMA_GET_FLAG, __HAL_MDMA_GET_IT_SOURCE, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_CHANNEL_SIZE, HAL_MDMA_ERROR_ALIGNMENT, HAL_MDMA_ERROR_BLOCK_SIZE, HAL_MDMA_ERROR_LINKED_LIST, HAL_MDMA_ERROR_MASK_DATA, HAL_MDMA_ERROR_NONE, HAL_MDMA_ERROR_READ_XFER, HAL_MDMA_ERROR_WRITE_XFER, HAL_MDMA_STATE_ABORT, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

HAL_StatusTypeDef HAL_MDMA_PollForTransfer | ( | MDMA_HandleTypeDef * | hmdma,
 |  | HAL_MDMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CompleteLevel,: Specifies the MDMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1316 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_GET_FLAG, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_Abort(), HAL_MDMA_BLOCK_TRANSFER, HAL_MDMA_BUFFER_TRANSFER, HAL_MDMA_ERROR_ALIGNMENT, HAL_MDMA_ERROR_BLOCK_SIZE, HAL_MDMA_ERROR_LINKED_LIST, HAL_MDMA_ERROR_MASK_DATA, HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_ERROR_READ_XFER, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_ERROR_WRITE_XFER, HAL_MDMA_FULL_TRANSFER, HAL_MDMA_REPEAT_BLOCK_TRANSFER, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, IS_MDMA_LEVEL_COMPLETE, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Start | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  |

Starts the MDMA Transfer.

Parameters:
hmdma | : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
SrcAddress | : The source memory Buffer address
DstAddress | : The destination memory Buffer address
BlockDataLength | : The length of a block transfer in bytes
BlockCount | : The number of a blocks to be transfer
Return values:
HAL status

Definition at line 1073 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __HAL_MDMA_ENABLE, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_COUNT, IS_MDMA_TRANSFER_LENGTH, MDMA_REQUEST_SW, MDMA_SetConfig(), MDMA_InitTypeDef::Request, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Start_IT | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  |

Starts the MDMA Transfer with interrupts enabled.

Parameters:
hmdma | : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
SrcAddress | : The source memory Buffer address
DstAddress | : The destination memory Buffer address
BlockDataLength | : The length of a block transfer in bytes
BlockCount | : The number of a blocks to be transfer
Return values:
HAL status

Definition at line 1133 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __HAL_MDMA_ENABLE, __HAL_MDMA_ENABLE_IT, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_COUNT, IS_MDMA_TRANSFER_LENGTH, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, MDMA_REQUEST_SW, MDMA_SetConfig(), MDMA_InitTypeDef::Request, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

Referenced by HAL_JPEG_Resume(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
MDMA Exported Functions

Peripheral State functions. More...

Functions

HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the MDMA state
      (+) Get error code

Function Documentation

uint32_t HAL_MDMA_GetError ( MDMA_HandleTypeDef * hmdma )

Return the MDMA error code.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
MDMA Error Code

Definition at line 1734 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::ErrorCode.

HAL_MDMA_StateTypeDef HAL_MDMA_GetState ( MDMA_HandleTypeDef * hmdma )

Returns the MDMA state.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL state

Definition at line 1723 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: MDMA Private Types

MDMA Private Types
MDMA
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STM32H7B3xQ HAL User Manual: MDMA Private Defines

MDMA Private Defines
MDMA
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STM32H7B3xQ HAL User Manual: MDMA Private Variables

MDMA Private Variables
MDMA
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STM32H7B3xQ HAL User Manual: MDMA Private Constants

Defines
MDMA Private Constants
MDMA

Defines

#define | HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */
#define | HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */

Define Documentation

#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */

Definition at line 170 of file stm32h7xx_hal_mdma.c.

Referenced by HAL_MDMA_IRQHandler().

#define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */

Definition at line 169 of file stm32h7xx_hal_mdma.c.

Referenced by HAL_MDMA_Abort(), and HAL_MDMA_Init().

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STM32H7B3xQ HAL User Manual: MDMA Private Macros

Defines
MDMA Private Macros
MDMA

Defines

#define | IS_MDMA_LEVEL_COMPLETE(__LEVEL__)
#define | IS_MDMA_PRIORITY(__PRIORITY__)
#define | IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__)
#define | IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
#define | IS_MDMA_SOURCE_INC(__INC__)
#define | IS_MDMA_DESTINATION_INC(__INC__)
#define | IS_MDMA_SOURCE_DATASIZE(__SIZE__)
#define | IS_MDMA_DESTINATION_DATASIZE(__SIZE__)
#define | IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__)
#define | IS_MDMA_SOURCE_BURST(__BURST__)
#define | IS_MDMA_DESTINATION_BURST(__BURST__)
#define | IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__)
#define | IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
#define | IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
#define | IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
#define | IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Define Documentation

#define IS_MDMA_BLOCK_ADDR_OFFSET ( __BLOCK_ADD_OFFSET__ ) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Definition at line 817 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_BLOCK_COUNT ( __COUNT__ ) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))

Definition at line 813 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define IS_MDMA_BUFFER_TRANSFER_LENGTH ( __LENGTH__ ) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))

Definition at line 811 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DATA_ALIGNMENT ( __ALIGNMENT__ )
Value:
(((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))

Definition at line 781 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_BURST ( __BURST__ )
Value:
(((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))

Definition at line 797 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_DATASIZE ( __SIZE__ )
Value:
(((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))

Definition at line 776 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_INC ( __INC__ )
Value:
(((__INC__) == MDMA_DEST_INC_DISABLE )   || \
                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))

Definition at line 761 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_ENDIANNESS_MODE ( __ENDIANNESS__ )
Value:
(((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))

Definition at line 739 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_LEVEL_COMPLETE ( __LEVEL__ )
Value:
(((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))

Definition at line 728 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_PollForTransfer().

#define IS_MDMA_PRIORITY ( __PRIORITY__ )
Value:
(((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))

Definition at line 734 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_REQUEST ( __REQUEST__ ) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))

Definition at line 746 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_BURST ( __BURST__ )
Value:
(((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))

Definition at line 787 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_DATASIZE ( __SIZE__ )
Value:
(((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))

Definition at line 771 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_INC ( __INC__ )
Value:
(((__INC__) == MDMA_SRC_INC_DISABLE )   || \
                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))

Definition at line 751 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_TRANSFER_LENGTH ( SIZE ) (((SIZE) > 0U) && ((SIZE) <= 65536U))

Definition at line 815 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define IS_MDMA_TRANSFER_TRIGGER_MODE ( __MODE__ )
Value:
(((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
                                                  ((__MODE__) == MDMA_FULL_TRANSFER))

Definition at line 806 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Private Functions Prototypes

MDMA Private Functions Prototypes
MDMA
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STM32H7B3xQ HAL User Manual: MDMA Private Functions

Functions
MDMA Private Functions
MDMA

Functions

static void | MDMA_SetConfig (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Sets the MDMA Transfer parameter.
static void | MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA handle according to the specified parameters in the MDMA_InitTypeDef.

Function Documentation

static void MDMA_Init ( MDMA_HandleTypeDef * hmdma ) [static]

Initializes the MDMA handle according to the specified parameters in the MDMA_InitTypeDef.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
None

Definition at line 1815 of file stm32h7xx_hal_mdma.c.

References MDMA_InitTypeDef::BufferTransferLength, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_InitTypeDef::Endianness, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, MDMA_REQUEST_SW, MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, and MDMA_InitTypeDef::SourceInc.

Referenced by HAL_MDMA_Init().

static void MDMA_SetConfig | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  | [static]

Sets the MDMA Transfer parameter.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
BlockDataLength : The length of a block transfer in bytes
BlockCount,: The number of blocks to be transfered
Return values:
HAL status

Definition at line 1761 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_CTC, and MDMA_FLAG_TE.

Referenced by HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Private Functions

Functions
MMC Private Functions
MMC | MMC Exported Functions

Functions

static uint32_t | MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the mmc card.
static uint32_t | MMC_PowerON (MMC_HandleTypeDef *hmmc)
Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.
static uint32_t | MMC_SendStatus (MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
Returns the current card's status.
static void | MMC_PowerOFF (MMC_HandleTypeDef *hmmc)
Turns the SDMMC output signals off.
static void | MMC_Write_IT (MMC_HandleTypeDef *hmmc)
Wrap up writing in non-blocking mode.
static void | MMC_Read_IT (MMC_HandleTypeDef *hmmc)
Wrap up reading in non-blocking mode.
static uint32_t | MMC_HighSpeed (MMC_HandleTypeDef *hmmc, FunctionalState state)
Switches the MMC card to high speed mode.
static uint32_t | MMC_DDR_Mode (MMC_HandleTypeDef *hmmc, FunctionalState state)
Switches the MMC card to Double Data Rate (DDR) mode.
HAL_StatusTypeDef | MMC_ReadExtCSD (MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
Reads extended CSD register to get the sectors number of the device.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Function Documentation

__weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3059 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

__weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3074 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

__weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3089 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

__weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3104 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

static uint32_t MMC_DDR_Mode | ( | MMC_HandleTypeDef * | hmmc,
 |  | FunctionalState | state
 | ) |  | [static]

Switches the MMC card to Double Data Rate (DDR) mode.

Parameters:
hmmc,: MMC handle
state,: State of DDR mode
Return values:
MMC Card error state

Definition at line 2972 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_ERROR_NONE, __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_ConfigSpeedBusOperation().

static uint32_t MMC_HighSpeed | ( | MMC_HandleTypeDef * | hmmc,
 |  | FunctionalState | state
 | ) |  | [static]

Switches the MMC card to high speed mode.

Parameters:
hmmc,: MMC handle
state,: State of high speed mode
Return values:
MMC Card error state

Definition at line 2900 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_ERROR_NONE, __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_ConfigSpeedBusOperation().

static uint32_t MMC_InitCard ( MMC_HandleTypeDef * hmmc ) [static]

Initializes the mmc card.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
MMC Card error state

Definition at line 2536 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::CID, HAL_MMC_CardInfoTypeDef::Class, __MMC_HandleTypeDef::CSD, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_GetCardCSD(), __MMC_HandleTypeDef::Init, __MDMA_HandleTypeDef::Init, __MMC_HandleTypeDef::Instance, MMC_InitTypeDef, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_InitCard().

static void MMC_PowerOFF ( MMC_HandleTypeDef * hmmc ) [static]

Turns the SDMMC output signals off.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 2685 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::Instance.

Referenced by HAL_MMC_DeInit().

static uint32_t MMC_PowerON ( MMC_HandleTypeDef * hmmc ) [static]

Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
error state

Definition at line 2633 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::CardType, eMMC_HIGH_VOLTAGE_RANGE, HAL_MMC_ERROR_INVALID_VOLTRANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_UNSUPPORTED_FEATURE, __MMC_HandleTypeDef::Instance, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, and __MMC_HandleTypeDef::MmcCard.

Referenced by HAL_MMC_InitCard().

static void MMC_Read_IT ( MMC_HandleTypeDef * hmmc ) [static]

Wrap up reading in non-blocking mode.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
None

Definition at line 2832 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::pRxBuffPtr, and __MMC_HandleTypeDef::RxXferSize.

Referenced by HAL_MMC_IRQHandler().

HAL_StatusTypeDef MMC_ReadExtCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pFieldData,
 |  | uint16_t | FieldIndex,
 |  | uint32_t | Timeout
 | ) |  |

Reads extended CSD register to get the sectors number of the device.

Parameters:
hmmc,: Pointer to MMC handle
pFieldData,: Pointer to the read buffer
pFieldIndex,: Index of the field to be read
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 2728 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, __MMC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_TIMEOUT, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, MMC_BLOCKSIZE, __MMC_HandleTypeDef::MmcCard, HAL_MMC_CardInfoTypeDef::RelCardAdd, and __MMC_HandleTypeDef::State.

Referenced by HAL_MMC_ConfigSpeedBusOperation(), and HAL_MMC_GetCardCSD().

static uint32_t MMC_SendStatus | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hmmc,: Pointer to MMC handle
pCardStatus,: pointer to the buffer that will contain the MMC card status (Card Status register)
Return values:
error state

Definition at line 2698 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_GetCardState().

static void MMC_Write_IT ( MMC_HandleTypeDef * hmmc ) [static]

Wrap up writing in non-blocking mode.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
None

Definition at line 2866 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::pTxBuffPtr, and __MMC_HandleTypeDef::TxXferSize.

Referenced by HAL_MMC_IRQHandler().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC State enumeration structure

Enumerations
MMC State enumeration structure
MMC Exported Types

Enumerations

enum HAL_MMC_StateTypeDef {
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU)
}

Enumeration Type Documentation

enum HAL_MMC_StateTypeDef
Enumerator:
HAL_MMC_STATE_RESET

MMC not yet initialized or disabled

HAL_MMC_STATE_READY

MMC initialized and ready for use

HAL_MMC_STATE_TIMEOUT

MMC Timeout state

HAL_MMC_STATE_BUSY

MMC process ongoing

HAL_MMC_STATE_PROGRAMMING

MMC Programming State

HAL_MMC_STATE_RECEIVING

MMC Receinving State

HAL_MMC_STATE_TRANSFER

MMC Transfert State

HAL_MMC_STATE_ERROR

MMC is in error state

Definition at line 47 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Card State enumeration structure

Defines | Typedefs
MMC Card State enumeration structure
MMC Exported Types

Defines

#define | HAL_MMC_CARD_READY 0x00000001U
#define | HAL_MMC_CARD_IDENTIFICATION 0x00000002U
#define | HAL_MMC_CARD_STANDBY 0x00000003U
#define | HAL_MMC_CARD_TRANSFER 0x00000004U
#define | HAL_MMC_CARD_SENDING 0x00000005U
#define | HAL_MMC_CARD_RECEIVING 0x00000006U
#define | HAL_MMC_CARD_PROGRAMMING 0x00000007U
#define | HAL_MMC_CARD_DISCONNECTED 0x00000008U
#define | HAL_MMC_CARD_ERROR 0x000000FFU

Typedefs

typedef uint32_t | HAL_MMC_CardStateTypeDef

Define Documentation

#define HAL_MMC_CARD_DISCONNECTED 0x00000008U

Card is disconnected

Definition at line 74 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_ERROR 0x000000FFU

Card response Error

Definition at line 75 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U

Card is in identification state

Definition at line 68 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_PROGRAMMING 0x00000007U

Card is in programming state

Definition at line 73 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_READY 0x00000001U

Card state is ready

Definition at line 67 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_RECEIVING 0x00000006U

Card is receiving operation information

Definition at line 72 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), and HAL_MMC_Abort_IT().

#define HAL_MMC_CARD_SENDING 0x00000005U

Card is sending an operation

Definition at line 71 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), and HAL_MMC_Abort_IT().

#define HAL_MMC_CARD_STANDBY 0x00000003U

Card is in standby state

Definition at line 69 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_CARD_TRANSFER 0x00000004U

Card is in transfer state

Definition at line 70 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigSpeedBusOperation().

Typedef Documentation

typedef uint32_t HAL_MMC_CardStateTypeDef

Definition at line 65 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Handle Structure definition

Data Structures | Defines | Typedefs
MMC Handle Structure definition
MMC Exported Types

Data Structures

struct | HAL_MMC_CardInfoTypeDef
MMC Card Information Structure definition. More...
struct | __MMC_HandleTypeDef
MMC handle Structure definition. More...

Defines

#define | MMC_InitTypeDef SDMMC_InitTypeDef
#define | MMC_TypeDef SDMMC_TypeDef

Typedefs

typedef struct __MMC_HandleTypeDef | MMC_HandleTypeDef
MMC handle Structure definition.

Define Documentation

#define MMC_InitTypeDef SDMMC_InitTypeDef

Definition at line 83 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_InitCard(), and MMC_InitCard().

#define MMC_TypeDef SDMMC_TypeDef

Definition at line 84 of file stm32h7xx_hal_mmc.h.

Typedef Documentation

typedef struct __MMC_HandleTypeDef MMC_HandleTypeDef

MMC handle Structure definition.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_MMC_CardInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardInfoTypeDef Struct Reference
MMC Handle Structure definition

MMC Card Information Structure definition. More...

#include <stm32h7xx_hal_mmc.h>

Data Fields

uint32_t | CardType
uint32_t | Class
uint32_t | RelCardAdd
uint32_t | BlockNbr
uint32_t | BlockSize
uint32_t | LogBlockNbr
uint32_t | LogBlockSize

Detailed Description

MMC Card Information Structure definition.

Definition at line 89 of file stm32h7xx_hal_mmc.h.

Field Documentation

uint32_t HAL_MMC_CardInfoTypeDef::BlockNbr

Specifies the Card Capacity in blocks

Definition at line 97 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::BlockSize

Specifies one block size in bytes

Definition at line 99 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::CardType

Specifies the card Type

Definition at line 91 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_PowerON().

uint32_t HAL_MMC_CardInfoTypeDef::Class

Specifies the class of the card class

Definition at line 93 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardInfo(), and MMC_InitCard().

uint32_t HAL_MMC_CardInfoTypeDef::LogBlockNbr

Specifies the Card logical Capacity in blocks

Definition at line 101 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

uint32_t HAL_MMC_CardInfoTypeDef::LogBlockSize

Specifies logical block size in bytes

Definition at line 103 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::RelCardAdd

Specifies the Relative Card Address

Definition at line 95 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_GetCardInfo(), MMC_DDR_Mode(), MMC_HighSpeed(), MMC_InitCard(), MMC_ReadExtCSD(), and MMC_SendStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __MMC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__MMC_HandleTypeDef Struct Reference
MMC Handle Structure definition

MMC handle Structure definition. More...

#include <stm32h7xx_hal_mmc.h>

Data Fields

MMC_TypeDef * Instance
MMC_InitTypeDef Init
HAL_LockTypeDef | Lock
uint8_t * | pTxBuffPtr
uint32_t | TxXferSize
uint8_t * | pRxBuffPtr
uint32_t | RxXferSize
__IO uint32_t | Context
__IO HAL_MMC_StateTypeDef | State
__IO uint32_t | ErrorCode
HAL_MMC_CardInfoTypeDef MmcCard
uint32_t | CSD [4U]
uint32_t | CID [4U]
uint32_t | Ext_CSD [128]
void(* | TxCpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | RxCpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | ErrorCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | AbortCpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | Read_DMADblBuf0CpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | Read_DMADblBuf1CpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | Write_DMADblBuf0CpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | Write_DMADblBuf1CpltCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | MspInitCallback )(struct __MMC_HandleTypeDef *hmmc)
void(* | MspDeInitCallback )(struct __MMC_HandleTypeDef *hmmc)

Detailed Description

MMC handle Structure definition.

Definition at line 111 of file stm32h7xx_hal_mmc.h.

Field Documentation

void(* __MMC_HandleTypeDef::AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 148 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort_IT(), HAL_MMC_Init(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

uint32_t __MMC_HandleTypeDef::CID[4U]

MMC card identification number table

Definition at line 140 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID(), and MMC_InitCard().

__IO uint32_t __MMC_HandleTypeDef::Context

MMC transfer context

Definition at line 130 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

uint32_t __MMC_HandleTypeDef::CSD[4U]

MMC card specific data table

Definition at line 138 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and MMC_InitCard().

void(* __MMC_HandleTypeDef::ErrorCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 147 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

__IO uint32_t __MMC_HandleTypeDef::ErrorCode

MMC Card Error codes

Definition at line 134 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardState(), HAL_MMC_GetError(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_RegisterCallback(), HAL_MMC_UnRegisterCallback(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_InitCard(), and MMC_ReadExtCSD().

uint32_t __MMC_HandleTypeDef::Ext_CSD[128]

Definition at line 142 of file stm32h7xx_hal_mmc.h.

MMC_InitTypeDef __MMC_HandleTypeDef::Init

MMC required parameters

Definition at line 118 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Init(), and MMC_InitCard().

MMC_TypeDef* __MMC_HandleTypeDef::Instance

MMC registers base address

Definition at line 116 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ChangeDMABuffer(), HAL_MMCEx_ConfigDMAMultiBuffer(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_DDR_Mode(), MMC_HighSpeed(), MMC_InitCard(), MMC_PowerOFF(), MMC_PowerON(), MMC_Read_IT(), MMC_ReadExtCSD(), MMC_SendStatus(), and MMC_Write_IT().

HAL_LockTypeDef __MMC_HandleTypeDef::Lock

MMC locking object

Definition at line 120 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init().

HAL_MMC_CardInfoTypeDef __MMC_HandleTypeDef::MmcCard

MMC Card information

Definition at line 136 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_DDR_Mode(), MMC_HighSpeed(), MMC_InitCard(), MMC_PowerON(), MMC_ReadExtCSD(), and MMC_SendStatus().

void(* __MMC_HandleTypeDef::MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 155 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_DeInit(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

void(* __MMC_HandleTypeDef::MspInitCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 154 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

uint8_t* __MMC_HandleTypeDef::pRxBuffPtr

Pointer to MMC Rx transfer Buffer

Definition at line 126 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), and MMC_Read_IT().

uint8_t* __MMC_HandleTypeDef::pTxBuffPtr

Pointer to MMC Tx transfer Buffer

Definition at line 122 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_Write_IT().

void(* __MMC_HandleTypeDef::Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 149 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

void(* __MMC_HandleTypeDef::Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 150 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

void(* __MMC_HandleTypeDef::RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 146 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

uint32_t __MMC_HandleTypeDef::RxXferSize

MMC Rx Transfer size

Definition at line 128 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), and MMC_Read_IT().

__IO HAL_MMC_StateTypeDef __MMC_HandleTypeDef::State

MMC card State

Definition at line 132 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetState(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_RegisterCallback(), HAL_MMC_UnRegisterCallback(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ConfigDMAMultiBuffer(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_ReadExtCSD().

void(* __MMC_HandleTypeDef::TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 145 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

uint32_t __MMC_HandleTypeDef::TxXferSize

MMC Tx Transfer size

Definition at line 124 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_Write_IT().

void(* __MMC_HandleTypeDef::Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 151 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

void(* __MMC_HandleTypeDef::Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc)

Definition at line 152 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_MMC_CardCSDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardCSDTypeDef Struct Reference
Card Specific Data: CSD Register

#include <stm32h7xx_hal_mmc.h>

Data Fields

__IO uint8_t | CSDStruct
__IO uint8_t | SysSpecVersion
__IO uint8_t | Reserved1
__IO uint8_t | TAAC
__IO uint8_t | NSAC
__IO uint8_t | MaxBusClkFrec
__IO uint16_t | CardComdClasses
__IO uint8_t | RdBlockLen
__IO uint8_t | PartBlockRead
__IO uint8_t | WrBlockMisalign
__IO uint8_t | RdBlockMisalign
__IO uint8_t | DSRImpl
__IO uint8_t | Reserved2
__IO uint32_t | DeviceSize
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | DeviceSizeMul
__IO uint8_t | EraseGrSize
__IO uint8_t | EraseGrMul
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | ManDeflECC
__IO uint8_t | WrSpeedFact
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | Reserved3
__IO uint8_t | ContentProtectAppli
__IO uint8_t | FileFormatGroup
__IO uint8_t | CopyFlag
__IO uint8_t | PermWrProtect
__IO uint8_t | TempWrProtect
__IO uint8_t | FileFormat
__IO uint8_t | ECC
__IO uint8_t | CSD_CRC
__IO uint8_t | Reserved4

Detailed Description

Definition at line 167 of file stm32h7xx_hal_mmc.h.

Field Documentation

__IO uint16_t HAL_MMC_CardCSDTypeDef::CardComdClasses

Card command classes

Definition at line 175 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ContentProtectAppli

Content protection application

Definition at line 197 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CopyFlag

Copy flag (OTP)

Definition at line 199 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CSD_CRC

CSD CRC

Definition at line 204 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CSDStruct

CSD structure

Definition at line 169 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint32_t HAL_MMC_CardCSDTypeDef::DeviceSize

Device Size

Definition at line 182 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::DeviceSizeMul

Device size multiplier

Definition at line 187 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::DSRImpl

DSR implemented

Definition at line 180 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ECC

ECC code

Definition at line 203 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::EraseGrMul

Erase group size multiplier

Definition at line 189 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::EraseGrSize

Erase group size

Definition at line 188 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::FileFormat

File format

Definition at line 202 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::FileFormatGroup

File format group

Definition at line 198 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ManDeflECC

Manufacturer default ECC

Definition at line 192 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxBusClkFrec

Max. bus clock frequency

Definition at line 174 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 184 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 183 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrBlockLen

Max. write data block length

Definition at line 194 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 186 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 185 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::NSAC

Data read access time 2 in CLK cycles

Definition at line 173 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::PartBlockRead

Partial blocks for read allowed

Definition at line 177 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::PermWrProtect

Permanent write protection

Definition at line 200 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::RdBlockLen

Max. read data block length

Definition at line 176 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::RdBlockMisalign

Read block misalignment

Definition at line 179 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved1

Reserved

Definition at line 171 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved2

Reserved

Definition at line 181 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved3

Reserved

Definition at line 196 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved4

Always 1

Definition at line 205 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::SysSpecVersion

System specification version

Definition at line 170 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::TAAC

Data read access time 1

Definition at line 172 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::TempWrProtect

Temporary write protection

Definition at line 201 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrBlockMisalign

Write block misalignment

Definition at line 178 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 195 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrProtectGrEnable

Write protect group enable

Definition at line 191 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrProtectGrSize

Write protect group size

Definition at line 190 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrSpeedFact

Write speed factor

Definition at line 193 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_MMC_CardCIDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardCIDTypeDef Struct Reference
Card Identification Data: CID Register

#include <stm32h7xx_hal_mmc.h>

Data Fields

__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint16_t | ManufactDate
__IO uint8_t | CID_CRC
__IO uint8_t | Reserved2

Detailed Description

Definition at line 215 of file stm32h7xx_hal_mmc.h.

Field Documentation

__IO uint8_t HAL_MMC_CardCIDTypeDef::CID_CRC

CID CRC

Definition at line 225 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint16_t HAL_MMC_CardCIDTypeDef::ManufactDate

Manufacturing Date

Definition at line 224 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypeDef::ManufacturerID

Manufacturer ID

Definition at line 217 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint16_t HAL_MMC_CardCIDTypeDef::OEM_AppliID

OEM/Application ID

Definition at line 218 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint32_t HAL_MMC_CardCIDTypeDef::ProdName1

Product Name part1

Definition at line 219 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypeDef::ProdName2

Product Name part2

Definition at line 220 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypeDef::ProdRev

Product Revision

Definition at line 221 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint32_t HAL_MMC_CardCIDTypeDef::ProdSN

Product Serial Number

Definition at line 222 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypeDef::Reserved1

Reserved1

Definition at line 223 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypeDef::Reserved2

Always 1

Definition at line 226 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Callback ID enumeration definition

Enumerations
MMC Callback ID enumeration definition
MMC Exported Types

Enumerations

enum HAL_MMC_CallbackIDTypeDef {
HAL_MMC_TX_CPLT_CB_ID = 0x00U, HAL_MMC_RX_CPLT_CB_ID = 0x01U, HAL_MMC_ERROR_CB_ID = 0x02U, HAL_MMC_ABORT_CB_ID = 0x03U,
HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,
HAL_MMC_MSP_INIT_CB_ID = 0x10U, HAL_MMC_MSP_DEINIT_CB_ID = 0x11U
}

Enumeration Type Documentation

enum HAL_MMC_CallbackIDTypeDef
Enumerator:
HAL_MMC_TX_CPLT_CB_ID

MMC Tx Complete Callback ID

HAL_MMC_RX_CPLT_CB_ID

MMC Rx Complete Callback ID

HAL_MMC_ERROR_CB_ID

MMC Error Callback ID

HAL_MMC_ABORT_CB_ID

MMC Abort Callback ID

HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID

MMC Rx DMA Double Buffer 0 Complete Callback ID

HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID

MMC Rx DMA Double Buffer 1 Complete Callback ID

HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID

MMC Tx DMA Double Buffer 0 Complete Callback ID

HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID

MMC Tx DMA Double Buffer 1 Complete Callback ID

HAL_MMC_MSP_INIT_CB_ID

MMC MspInit Callback ID

HAL_MMC_MSP_DEINIT_CB_ID

MMC MspDeInit Callback ID

Definition at line 237 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Callback pointer definition

Typedefs
MMC Callback pointer definition
MMC Exported Types

Typedefs

typedef void(* pMMC_CallbackTypeDef )(MMC_HandleTypeDef *hmmc)

Typedef Documentation

typedef void(* pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc)

Definition at line 258 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Error status enumeration Structure definition

Defines
MMC Error status enumeration Structure definition
Exported Constants

Defines

#define | HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER

Define Documentation

#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED

Misaligned address

Definition at line 284 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE

Error when addressed block is out of range

Definition at line 306 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR

Error in sequence of authentication

Definition at line 304 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM

An invalid selection for erase groups

Definition at line 288 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

Definition at line 285 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY

Error when transfer process is busy

Definition at line 310 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED

Command has been executed without using internal ECC

Definition at line 301 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

Definition at line 294 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR

Internal card controller error

Definition at line 295 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE

CID/CSD overwrite error

Definition at line 299 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL

Command response received (but CRC check failed)

Definition at line 278 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT

Command response timeout

Definition at line 280 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED

CRC check of the previous command failed

Definition at line 292 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL

Data block sent/received (CRC check failed)

Definition at line 279 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT

Data timeout

Definition at line 281 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA

Error while DMA transfer

Definition at line 311 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

Definition at line 302 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR

An error in the sequence of erase command occurs

Definition at line 287 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR

General or unknown error

Definition at line 296 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD

Command is not legal for the card state

Definition at line 293 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER

Invalid callback error

Definition at line 315 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_RegisterCallback(), and HAL_MMC_UnRegisterCallback().

#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE

Error in case of invalid voltage range

Definition at line 305 of file stm32h7xx_hal_mmc.h.

Referenced by MMC_PowerON().

#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

Definition at line 290 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase().

#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE

No error

Definition at line 277 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardState(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_DDR_Mode(), MMC_HighSpeed(), MMC_InitCard(), MMC_PowerON(), MMC_ReadExtCSD(), and MMC_SendStatus().

#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER

the used parameter is not valid

Definition at line 308 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_SendStatus().

#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE

Error when command request is not applicable

Definition at line 307 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), and MMC_InitCard().

#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN

Receive FIFO overrun

Definition at line 283 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), and HAL_MMC_ReadBlocks().

#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN

The card could not sustain data reading in stream rmode

Definition at line 297 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

Definition at line 298 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Timeout error

Definition at line 312 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ReadBlocks(), and MMC_ReadExtCSD().

#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN

Transmit FIFO underrun

Definition at line 282 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE

Error when feature is not insupported

Definition at line 309 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_GetCardCSD(), and MMC_PowerON().

#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP

Only partial address space was erased

Definition at line 300 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION

Attempt to program a write protect block

Definition at line 289 of file stm32h7xx_hal_mmc.h.

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STM32H7B3xQ HAL User Manual: MMC context enumeration

Defines
MMC context enumeration
Exported Constants

Defines

#define | MMC_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | MMC_CONTEXT_IT ((uint32_t)0x00000008U)
#define | MMC_CONTEXT_DMA ((uint32_t)0x00000080U)

Define Documentation

#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U)

Process in DMA mode

Definition at line 330 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_WriteBlocks_DMA(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define MMC_CONTEXT_IT ((uint32_t)0x00000008U)

Process in Interrupt mode

Definition at line 329 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_IT(), and HAL_MMC_WriteBlocks_IT().

#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U)

None

Definition at line 324 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), and HAL_MMC_Init().

#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)

Read multiple blocks operation

Definition at line 326 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), and HAL_MMCEx_ReadBlocksDMAMultiBuffer().

#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)

Read single block operation

Definition at line 325 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), and HAL_MMC_ReadBlocks_IT().

#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)

Write multiple blocks operation

Definition at line 328 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)

Write single block operation

Definition at line 327 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), and HAL_MMC_WriteBlocks_IT().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Voltage mode

Defines
MMC Voltage mode
Exported Constants

Defines

#define | MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U
#define | MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U
#define | eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U
#define | eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U
#define | MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U

Define Documentation

#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U

for eMMC > 2Gb sector mode

Definition at line 345 of file stm32h7xx_hal_mmc.h.

#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U

for eMMC > 2Gb sector mode

Definition at line 344 of file stm32h7xx_hal_mmc.h.

Referenced by MMC_PowerON().

#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U

VALUE OF ARGUMENT

Definition at line 343 of file stm32h7xx_hal_mmc.h.

#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U

VALUE OF ARGUMENT

Definition at line 342 of file stm32h7xx_hal_mmc.h.

#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U

Definition at line 346 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Memory Cards

Defines
MMC Memory Cards
Exported Constants

Defines

#define | MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)
#define | MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)

Define Documentation

#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)

MMC Card Capacity >2Gbytes and <2Tbytes

Definition at line 355 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_PowerON().

#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)

MMC Card Capacity <=2Gbytes

Definition at line 354 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and MMC_PowerON().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Exported Constants

Modules | Defines
Exported Constants
MMC

Modules

MMC Error status enumeration Structure definition
MMC context enumeration
MMC Voltage mode
MMC Memory Cards

Defines

#define MMC_BLOCKSIZE ((uint32_t)512U)

Define Documentation

#define MMC_BLOCKSIZE ((uint32_t)512U)

Block size is 512 bytes

Definition at line 272 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_ReadExtCSD().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Exported Macros

Defines
MMC Exported Macros
MMC

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)
Reset MMC handle state.
#define | __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the MMC device interrupt.
#define | __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the MMC device interrupt.
#define | __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified MMC flag is set or not.
#define | __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the MMC's pending flags.
#define | __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified MMC interrupt has occurred or not.
#define | __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the MMC's interrupt pending bits.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_MMC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

Clear the MMC's pending flags.

Parameters:
__HANDLE__,: MMC Handle
__FLAG__,: specifies the flag to clear. This parameter can be one or a combination of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
None

Definition at line 513 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_ReadExtCSD().

#define __HAL_MMC_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Clear the MMC's interrupt pending bits.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 577 of file stm32h7xx_hal_mmc.h.

#define __HAL_MMC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Disable the MMC device interrupt.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 446 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_DMA(), and HAL_MMC_WriteBlocks_DMA().

#define __HAL_MMC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Enable the MMC device interrupt.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 414 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define __HAL_MMC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

Check whether the specified MMC flag is set or not.

Parameters:
__HANDLE__,: MMC Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_DPSMACT: Data path state machine active
  • SDMMC_FLAG_CPSMACT: Command path state machine active
  • SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDMMC_FLAG_TXFIFOF: Transmit FIFO full
  • SDMMC_FLAG_RXFIFOF: Receive FIFO full
  • SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
  • SDMMC_FLAG_RXFIFOE: Receive FIFO empty
  • SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
The new state of MMC FLAG (SET or RESET).

Definition at line 484 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_WriteBlocks(), and MMC_ReadExtCSD().

#define __HAL_MMC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Check whether the specified MMC interrupt has occurred or not.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt source to check. This parameter can be one of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
The new state of MMC IT (SET or RESET).

Definition at line 545 of file stm32h7xx_hal_mmc.h.

#define __HAL_MMC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                              \
                                                               (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                             } while(0)

Reset MMC handle state.

Parameters:
__HANDLE__ : MMC handle.
Return values:
None

Definition at line 375 of file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
MMC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the MMC
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_MMC_DeInit ( MMC_HandleTypeDef * hmmc )

De-Initializes the MMC card.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
HAL status

Definition at line 439 of file stm32h7xx_hal_mmc.c.

References assert_param, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_MspDeInit(), HAL_MMC_STATE_BUSY, HAL_MMC_STATE_RESET, __MMC_HandleTypeDef::Instance, MMC_PowerOFF(), __MMC_HandleTypeDef::MspDeInitCallback, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Init ( MMC_HandleTypeDef * hmmc )

Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.

Parameters:
hmmc,: Pointer to the MMC handle
Return values:
HAL status

Definition at line 315 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::AbortCpltCallback, assert_param, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCallback, __MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_AbortCallback(), HAL_MMC_ErrorCallback(), HAL_MMC_InitCard(), HAL_MMC_MspInit(), HAL_MMC_RxCpltCallback(), HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, HAL_MMC_STATE_RESET, HAL_MMC_TxCpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(), __MMC_HandleTypeDef::Init, __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::Lock, MMC_CONTEXT_NONE, __MMC_HandleTypeDef::MspInitCallback, __MMC_HandleTypeDef::Read_DMADblBuf0CpltCallback, __MMC_HandleTypeDef::Read_DMADblBuf1CpltCallback, __MMC_HandleTypeDef::RxCpltCallback, __MMC_HandleTypeDef::State, __MMC_HandleTypeDef::TxCpltCallback, __MMC_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __MMC_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_MMC_InitCard ( MMC_HandleTypeDef * hmmc )

Initializes the MMC Card.

Parameters:
hmmc,: Pointer to MMC handle
Note:
This function initializes the MMC card. It could be used when a card re-initialization is needed.
Return values:
HAL status

Definition at line 386 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_READY, __MDMA_HandleTypeDef::Init, __MMC_HandleTypeDef::Instance, MMC_InitCard(), MMC_InitTypeDef, MMC_PowerON(), and __MMC_HandleTypeDef::State.

Referenced by HAL_MMC_Init().

void HAL_MMC_MspDeInit ( MMC_HandleTypeDef * hmmc )

De-Initialize MMC MSP.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 495 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_DeInit(), and HAL_MMC_UnRegisterCallback().

void HAL_MMC_MspInit ( MMC_HandleTypeDef * hmmc )

Initializes the MMC MSP.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 480 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), and HAL_MMC_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
MMC Exported Functions

Data transfer functions. More...

Functions

HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.
HAL_StatusTypeDef | HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
Register a User MMC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_MMC_UnRegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
Unregister a User MMC Callback MMC Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to MMC card.

Function Documentation

void HAL_MMC_AbortCallback ( MMC_HandleTypeDef * hmmc )

MMC Abort callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1726 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Abort_IT(), HAL_MMC_Init(), and HAL_MMC_UnRegisterCallback().

HAL_StatusTypeDef HAL_MMC_Erase | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockStartAdd,
 |  | uint32_t | BlockEndAdd
 | ) |  |

Erases the specified memory area of the given MMC card.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
BlockStartAdd,: Start Block address
BlockEndAdd,: End Block address
Return values:
HAL status

Definition at line 1327 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_LOCK_UNLOCK_FAILED, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, and __MMC_HandleTypeDef::State.

void HAL_MMC_ErrorCallback ( MMC_HandleTypeDef * hmmc )

MMC error callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1711 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

uint32_t HAL_MMC_GetError ( MMC_HandleTypeDef * hmmc )

Return the MMC error code.

Parameters:
hmmc : Pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
MMC Error Code

Definition at line 1671 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::ErrorCode.

HAL_MMC_StateTypeDef HAL_MMC_GetState ( MMC_HandleTypeDef * hmmc )

return the MMC state

Parameters:
hmmc,: Pointer to mmc handle
Return values:
HAL state

Definition at line 1660 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::State.

void HAL_MMC_IRQHandler ( MMC_HandleTypeDef * hmmc )

This function handles MMC card interrupt request.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 1424 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_GET_FLAG, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCallback, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_DATA_CRC_FAIL, HAL_MMC_ERROR_DATA_TIMEOUT, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_RX_OVERRUN, HAL_MMC_ERROR_TX_UNDERRUN, HAL_MMC_ErrorCallback(), HAL_MMC_RxCpltCallback(), HAL_MMC_STATE_READY, HAL_MMC_TxCpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(), __MMC_HandleTypeDef::Instance, MMC_CONTEXT_DMA, MMC_CONTEXT_IT, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_Read_IT(), MMC_Write_IT(), __MMC_HandleTypeDef::Read_DMADblBuf0CpltCallback, __MMC_HandleTypeDef::Read_DMADblBuf1CpltCallback, __MMC_HandleTypeDef::RxCpltCallback, __MMC_HandleTypeDef::State, __MMC_HandleTypeDef::TxCpltCallback, __MMC_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __MMC_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_MMC_ReadBlocks | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
pData,: pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of MMC blocks to read
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 536 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_BUSY, HAL_MMC_ERROR_DATA_CRC_FAIL, HAL_MMC_ERROR_DATA_TIMEOUT, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_RX_OVERRUN, HAL_MMC_ERROR_TIMEOUT, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the DMA transfer process through the MMC Rx interrupt event.
Parameters:
hmmc,: Pointer MMC handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 1114 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_DMA, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, __MMC_HandleTypeDef::pRxBuffPtr, __MMC_HandleTypeDef::RxXferSize, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the IT transfer process through the MMC Rx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 905 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_IT, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, __MMC_HandleTypeDef::pRxBuffPtr, __MMC_HandleTypeDef::RxXferSize, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_RegisterCallback | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CallbackIDTypeDef | CallbackId,
 |  | pMMC_CallbackTypeDef | pCallback
 | ) |  |

Register a User MMC Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hmmc | : MMC handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
  • HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
  • HAL_MMC_ERROR_CB_ID MMC Error Callback ID
  • HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
  • HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID
  • HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID
  • HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
  • HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
  • HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
  • HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1756 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::AbortCpltCallback, __MMC_HandleTypeDef::ErrorCallback, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ABORT_CB_ID, HAL_MMC_ERROR_CB_ID, HAL_MMC_ERROR_INVALID_CALLBACK, HAL_MMC_MSP_DEINIT_CB_ID, HAL_MMC_MSP_INIT_CB_ID, HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID, HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID, HAL_MMC_RX_CPLT_CB_ID, HAL_MMC_STATE_READY, HAL_MMC_STATE_RESET, HAL_MMC_TX_CPLT_CB_ID, HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID, HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID, __MMC_HandleTypeDef::MspDeInitCallback, __MMC_HandleTypeDef::MspInitCallback, __MMC_HandleTypeDef::Read_DMADblBuf0CpltCallback, __MMC_HandleTypeDef::Read_DMADblBuf1CpltCallback, __MMC_HandleTypeDef::RxCpltCallback, __MMC_HandleTypeDef::State, __MMC_HandleTypeDef::TxCpltCallback, __MMC_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __MMC_HandleTypeDef::Write_DMADblBuf1CpltCallback.

void HAL_MMC_RxCpltCallback ( MMC_HandleTypeDef * hmmc )

Rx Transfer completed callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1696 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

void HAL_MMC_TxCpltCallback ( MMC_HandleTypeDef * hmmc )

Tx Transfer completed callbacks.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 1681 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

HAL_StatusTypeDef HAL_MMC_UnRegisterCallback | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User MMC Callback MMC Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hmmc : MMC handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
  • HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
  • HAL_MMC_ERROR_CB_ID MMC Error Callback ID
  • HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
  • HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID
  • HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID
  • HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
  • HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
  • HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
  • HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
Return values:
status

Definition at line 1861 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::AbortCpltCallback, __MMC_HandleTypeDef::ErrorCallback, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ABORT_CB_ID, HAL_MMC_AbortCallback(), HAL_MMC_ERROR_CB_ID, HAL_MMC_ERROR_INVALID_CALLBACK, HAL_MMC_ErrorCallback(), HAL_MMC_MSP_DEINIT_CB_ID, HAL_MMC_MSP_INIT_CB_ID, HAL_MMC_MspDeInit(), HAL_MMC_MspInit(), HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID, HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID, HAL_MMC_RX_CPLT_CB_ID, HAL_MMC_RxCpltCallback(), HAL_MMC_STATE_READY, HAL_MMC_STATE_RESET, HAL_MMC_TX_CPLT_CB_ID, HAL_MMC_TxCpltCallback(), HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID, HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID, HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(), __MMC_HandleTypeDef::MspDeInitCallback, __MMC_HandleTypeDef::MspInitCallback, __MMC_HandleTypeDef::Read_DMADblBuf0CpltCallback, __MMC_HandleTypeDef::Read_DMADblBuf1CpltCallback, __MMC_HandleTypeDef::RxCpltCallback, __MMC_HandleTypeDef::State, __MMC_HandleTypeDef::TxCpltCallback, __MMC_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __MMC_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_MMC_WriteBlocks | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of MMC blocks to write
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 720 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_BUSY, HAL_MMC_ERROR_DATA_CRC_FAIL, HAL_MMC_ERROR_DATA_TIMEOUT, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_TX_UNDERRUN, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the DMA transfer process through the MMC Tx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1222 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_DMA, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, __MMC_HandleTypeDef::pTxBuffPtr, __MMC_HandleTypeDef::State, and __MMC_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the IT transfer process through the MMC Tx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1009 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_IT, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, __MMC_HandleTypeDef::pTxBuffPtr, __MMC_HandleTypeDef::State, and __MMC_HandleTypeDef::TxXferSize.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
MMC Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_MMC_ConfigSpeedBusOperation (MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_MMC_CardStateTypeDef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the MMC card
    operations and get the related information

Function Documentation

HAL_StatusTypeDef HAL_MMC_Abort ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 2443 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, MMC_CONTEXT_NONE, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Abort_IT ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC (IT mode).

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 2480 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __MMC_HandleTypeDef::AbortCpltCallback, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_AbortCallback(), HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | SpeedMode
 | ) |  |

Configure the speed bus mode.

Parameters:
hmmc,: Pointer to the MMC handle
SpeedMode,: Specifies the MMC card speed bus mode This parameter can be one of the following values:
  • SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
  • SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
  • SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
  • SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
Return values:
HAL status

Definition at line 2271 of file stm32h7xx_hal_mmc.c.

References assert_param, __MMC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MMC_CARD_TRANSFER, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_TIMEOUT, HAL_MMC_ERROR_UNSUPPORTED_FEATURE, HAL_MMC_GetCardState(), HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, MMC_DDR_Mode(), MMC_HighSpeed(), MMC_ReadExtCSD(), and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hmmc,: Pointer to MMC handle
WideMode,: Specifies the MMC card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
HAL status

Definition at line 2144 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, assert_param, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Init, __MDMA_HandleTypeDef::Init, __MMC_HandleTypeDef::Instance, __MMC_HandleTypeDef::MmcCard, HAL_MMC_CardInfoTypeDef::RelCardAdd, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_GetCardCID | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCIDTypeDef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hmmc,: Pointer to MMC handle
pCID,: Pointer to a HAL_MMC_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1969 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::CID, HAL_MMC_CardCIDTypeDef::CID_CRC, HAL_MMC_CardCIDTypeDef::ManufactDate, HAL_MMC_CardCIDTypeDef::ManufacturerID, HAL_MMC_CardCIDTypeDef::OEM_AppliID, HAL_MMC_CardCIDTypeDef::ProdName1, HAL_MMC_CardCIDTypeDef::ProdName2, HAL_MMC_CardCIDTypeDef::ProdRev, HAL_MMC_CardCIDTypeDef::ProdSN, HAL_MMC_CardCIDTypeDef::Reserved1, and HAL_MMC_CardCIDTypeDef::Reserved2.

HAL_StatusTypeDef HAL_MMC_GetCardCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hmmc,: Pointer to MMC handle
pCSD,: Pointer to a HAL_MMC_CardCSDTypeDef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 2002 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardCSDTypeDef::CardComdClasses, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardCSDTypeDef::ContentProtectAppli, HAL_MMC_CardCSDTypeDef::CopyFlag, __MMC_HandleTypeDef::CSD, HAL_MMC_CardCSDTypeDef::CSD_CRC, HAL_MMC_CardCSDTypeDef::CSDStruct, HAL_MMC_CardCSDTypeDef::DeviceSize, HAL_MMC_CardCSDTypeDef::DeviceSizeMul, HAL_MMC_CardCSDTypeDef::DSRImpl, HAL_MMC_CardCSDTypeDef::ECC, HAL_MMC_CardCSDTypeDef::EraseGrMul, HAL_MMC_CardCSDTypeDef::EraseGrSize, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_CardCSDTypeDef::FileFormat, HAL_MMC_CardCSDTypeDef::FileFormatGroup, HAL_MMC_ERROR_UNSUPPORTED_FEATURE, HAL_MMC_STATE_READY, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, HAL_MMC_CardCSDTypeDef::ManDeflECC, HAL_MMC_CardCSDTypeDef::MaxBusClkFrec, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_MMC_CardCSDTypeDef::MaxWrBlockLen, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, MMC_ReadExtCSD(), __MMC_HandleTypeDef::MmcCard, HAL_MMC_CardCSDTypeDef::NSAC, HAL_MMC_CardCSDTypeDef::PartBlockRead, HAL_MMC_CardCSDTypeDef::PermWrProtect, HAL_MMC_CardCSDTypeDef::RdBlockLen, HAL_MMC_CardCSDTypeDef::RdBlockMisalign, HAL_MMC_CardCSDTypeDef::Reserved1, HAL_MMC_CardCSDTypeDef::Reserved2, HAL_MMC_CardCSDTypeDef::Reserved3, HAL_MMC_CardCSDTypeDef::Reserved4, __MMC_HandleTypeDef::State, HAL_MMC_CardCSDTypeDef::SysSpecVersion, HAL_MMC_CardCSDTypeDef::TAAC, HAL_MMC_CardCSDTypeDef::TempWrProtect, HAL_MMC_CardCSDTypeDef::WrBlockMisalign, HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial, HAL_MMC_CardCSDTypeDef::WrProtectGrEnable, HAL_MMC_CardCSDTypeDef::WrProtectGrSize, and HAL_MMC_CardCSDTypeDef::WrSpeedFact.

Referenced by MMC_InitCard().

HAL_StatusTypeDef HAL_MMC_GetCardInfo | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the MMC card info.

Parameters:
hmmc,: Pointer to MMC handle
pCardInfo,: Pointer to the HAL_MMC_CardInfoTypeDef structure that will contain the MMC card status information
Return values:
HAL status

Definition at line 2120 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState ( MMC_HandleTypeDef * hmmc )

Gets the current mmc card data state.

Parameters:
hmmc,: pointer to MMC handle
Return values:
Card state

Definition at line 2420 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, and MMC_SendStatus().

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), and HAL_MMC_ConfigSpeedBusOperation().

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STM32H7B3xQ HAL User Manual: MMC card related functions

Functions
MMC card related functions
MMC Exported Functions

Functions

HAL_MMC_CardStateTypeDef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.

Function Documentation

HAL_StatusTypeDef HAL_MMC_GetCardCID | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCIDTypeDef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hmmc,: Pointer to MMC handle
pCID,: Pointer to a HAL_MMC_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1969 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::CID, HAL_MMC_CardCIDTypeDef::CID_CRC, HAL_MMC_CardCIDTypeDef::ManufactDate, HAL_MMC_CardCIDTypeDef::ManufacturerID, HAL_MMC_CardCIDTypeDef::OEM_AppliID, HAL_MMC_CardCIDTypeDef::ProdName1, HAL_MMC_CardCIDTypeDef::ProdName2, HAL_MMC_CardCIDTypeDef::ProdRev, HAL_MMC_CardCIDTypeDef::ProdSN, HAL_MMC_CardCIDTypeDef::Reserved1, and HAL_MMC_CardCIDTypeDef::Reserved2.

HAL_StatusTypeDef HAL_MMC_GetCardCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hmmc,: Pointer to MMC handle
pCSD,: Pointer to a HAL_MMC_CardCSDTypeDef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 2002 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardCSDTypeDef::CardComdClasses, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardCSDTypeDef::ContentProtectAppli, HAL_MMC_CardCSDTypeDef::CopyFlag, __MMC_HandleTypeDef::CSD, HAL_MMC_CardCSDTypeDef::CSD_CRC, HAL_MMC_CardCSDTypeDef::CSDStruct, HAL_MMC_CardCSDTypeDef::DeviceSize, HAL_MMC_CardCSDTypeDef::DeviceSizeMul, HAL_MMC_CardCSDTypeDef::DSRImpl, HAL_MMC_CardCSDTypeDef::ECC, HAL_MMC_CardCSDTypeDef::EraseGrMul, HAL_MMC_CardCSDTypeDef::EraseGrSize, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_CardCSDTypeDef::FileFormat, HAL_MMC_CardCSDTypeDef::FileFormatGroup, HAL_MMC_ERROR_UNSUPPORTED_FEATURE, HAL_MMC_STATE_READY, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, HAL_MMC_CardCSDTypeDef::ManDeflECC, HAL_MMC_CardCSDTypeDef::MaxBusClkFrec, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_MMC_CardCSDTypeDef::MaxWrBlockLen, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, MMC_ReadExtCSD(), __MMC_HandleTypeDef::MmcCard, HAL_MMC_CardCSDTypeDef::NSAC, HAL_MMC_CardCSDTypeDef::PartBlockRead, HAL_MMC_CardCSDTypeDef::PermWrProtect, HAL_MMC_CardCSDTypeDef::RdBlockLen, HAL_MMC_CardCSDTypeDef::RdBlockMisalign, HAL_MMC_CardCSDTypeDef::Reserved1, HAL_MMC_CardCSDTypeDef::Reserved2, HAL_MMC_CardCSDTypeDef::Reserved3, HAL_MMC_CardCSDTypeDef::Reserved4, __MMC_HandleTypeDef::State, HAL_MMC_CardCSDTypeDef::SysSpecVersion, HAL_MMC_CardCSDTypeDef::TAAC, HAL_MMC_CardCSDTypeDef::TempWrProtect, HAL_MMC_CardCSDTypeDef::WrBlockMisalign, HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial, HAL_MMC_CardCSDTypeDef::WrProtectGrEnable, HAL_MMC_CardCSDTypeDef::WrProtectGrSize, and HAL_MMC_CardCSDTypeDef::WrSpeedFact.

Referenced by MMC_InitCard().

HAL_StatusTypeDef HAL_MMC_GetCardInfo | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the MMC card info.

Parameters:
hmmc,: Pointer to MMC handle
pCardInfo,: Pointer to the HAL_MMC_CardInfoTypeDef structure that will contain the MMC card status information
Return values:
HAL status

Definition at line 2120 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, __MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState ( MMC_HandleTypeDef * hmmc )

Gets the current mmc card data state.

Parameters:
hmmc,: pointer to MMC handle
Return values:
Card state

Definition at line 2420 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, and MMC_SendStatus().

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), and HAL_MMC_ConfigSpeedBusOperation().

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STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
MMC Exported Functions

Functions

HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.

Function Documentation

uint32_t HAL_MMC_GetError ( MMC_HandleTypeDef * hmmc )

Return the MMC error code.

Parameters:
hmmc : Pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
MMC Error Code

Definition at line 1671 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::ErrorCode.

HAL_MMC_StateTypeDef HAL_MMC_GetState ( MMC_HandleTypeDef * hmmc )

return the MMC state

Parameters:
hmmc,: Pointer to mmc handle
Return values:
HAL state

Definition at line 1660 of file stm32h7xx_hal_mmc.c.

References __MMC_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: Perioheral Abort management

Functions
Perioheral Abort management
MMC Exported Functions

Functions

HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Function Documentation

HAL_StatusTypeDef HAL_MMC_Abort ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 2443 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, MMC_CONTEXT_NONE, and __MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Abort_IT ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC (IT mode).

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 2480 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __MMC_HandleTypeDef::AbortCpltCallback, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_AbortCallback(), HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, and __MMC_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: MMC Private Types

MMC Private Types
MMC Exported Functions
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STM32H7B3xQ HAL User Manual: MMC Private Defines

MMC Private Defines
MMC Exported Functions | MMC
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STM32H7B3xQ HAL User Manual: MMC Private Variables

MMC Private Variables
MMC Exported Functions
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STM32H7B3xQ HAL User Manual: MMC Private Constants

MMC Private Constants
MMC Exported Functions
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STM32H7B3xQ HAL User Manual: MMC Private Macros

MMC Private Macros
MMC Exported Functions
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STM32H7B3xQ HAL User Manual: MMC Private Functions Prototypes

MMC Private Functions Prototypes
MMC Exported Functions
Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMC Internal DMA Buffer structure

Enumerations
MMC Internal DMA Buffer structure
MMCEx Exported Types

Enumerations

enum HAL_MMCEx_DMABuffer_MemoryTypeDef { MMC_DMA_BUFFER0 = 0x00U, MMC_DMA_BUFFER1 = 0x01U }

Enumeration Type Documentation

enum HAL_MMCEx_DMABuffer_MemoryTypeDef
Enumerator:
MMC_DMA_BUFFER0

selects MMC internal DMA Buffer 0

MMC_DMA_BUFFER1

selects MMC internal DMA Buffer 1

Definition at line 48 of file stm32h7xx_hal_mmc_ex.h.

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STM32H7B3xQ HAL User Manual: MultiBuffer functions

Functions
MultiBuffer functions
MMCEx Exported Functions

Multibuffer functions. More...

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Multibuffer functions.

  ==============================================================================
          ##### Multibuffer functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to configure the multibuffer mode and start read and write
    multibuffer mode for MMC HAL driver.

Function Documentation

HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMCEx_DMABuffer_MemoryTypeDef | Buffer,
 |  | uint32_t * | pDataBuffer
 | ) |  |

Change the DMA Buffer0 or Buffer1 address on the fly.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure.
Buffer,: the buffer to be changed, This parameter can be one of the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
pDataBuffer,: The new address
Note:
The BUFFER0 address can be changed only when the current transfer use BUFFER1 and the BUFFER1 address can be changed only when the current transfer use BUFFER0.
Return values:
HAL status

Definition at line 269 of file stm32h7xx_hal_mmc_ex.c.

References __MMC_HandleTypeDef::Instance, and MMC_DMA_BUFFER0.

HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pDataBuffer0,
 |  | uint32_t * | pDataBuffer1,
 |  | uint32_t | BufferSize
 | ) |  |

Configure DMA Dual Buffer mode.

The Data transfer is managed by an Internal DMA.

Parameters:
hmmc,: MMC handle
pDataBuffer0,: Pointer to the buffer0 that will contain/receive the transfered data
pDataBuffer1,: Pointer to the buffer1 that will contain/receive the transfered data
BufferSize,: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
Return values:
HAL status

Definition at line 83 of file stm32h7xx_hal_mmc_ex.c.

References HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, and __MMC_HandleTypeDef::State.

void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3059 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3074 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The received Data will be stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hmmc,: MMC handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 107 of file stm32h7xx_hal_mmc_ex.c.

References __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_DMA, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, and __MMC_HandleTypeDef::State.

void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3089 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 3104 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), and HAL_MMC_UnRegisterCallback().

HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Write block(s) to a specified address in a card.

The transfered Data are stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hmmc,: MMC handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 187 of file stm32h7xx_hal_mmc_ex.c.

References __HAL_MMC_ENABLE_IT, HAL_MMC_CardInfoTypeDef::CardType, __MMC_HandleTypeDef::Context, __MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, __MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_BLOCKSIZE, MMC_CONTEXT_DMA, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_HIGH_CAPACITY_CARD, __MMC_HandleTypeDef::MmcCard, and __MMC_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NAND Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### NAND Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NAND memory

Function Documentation

HAL_StatusTypeDef HAL_NAND_ConfigDevice | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_DeviceConfigTypeDef * | pDeviceConfig
 | ) |  |

Configure the device: Enter the physical parameters of the device.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pDeviceConfig | pointer to NAND_DeviceConfigTypeDef structure
Return values:
HAL status

Definition at line 495 of file stm32h7xx_hal_nand.c.

References NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::PlaneNbr, NAND_DeviceConfigTypeDef::PlaneSize, and NAND_DeviceConfigTypeDef::SpareAreaSize.

HAL_StatusTypeDef HAL_NAND_DeInit ( NAND_HandleTypeDef * hnand )

Perform NAND memory De-Initialization sequence.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 211 of file stm32h7xx_hal_nand.c.

References HAL_NAND_MspDeInit(), HAL_NAND_STATE_RESET, __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, __NAND_HandleTypeDef::MspDeInitCallback, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Init | ( | NAND_HandleTypeDef * | hnand,
 |  | FMC_NAND_PCC_TimingTypeDef * | ComSpace_Timing,
 |  | FMC_NAND_PCC_TimingTypeDef * | AttSpace_Timing
 | ) |  |

Perform NAND memory Initialization sequence.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ComSpace_Timing | pointer to Common space timing structure
AttSpace_Timing | pointer to Attribute space timing structure
Return values:
HAL status

Definition at line 157 of file stm32h7xx_hal_nand.c.

References HAL_NAND_ITCallback(), HAL_NAND_MspInit(), HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, __NAND_HandleTypeDef::ItCallback, __NAND_HandleTypeDef::Lock, __NAND_HandleTypeDef::MspInitCallback, and __NAND_HandleTypeDef::State.

void HAL_NAND_IRQHandler ( NAND_HandleTypeDef * hnand )

This function handles NAND device interrupt request.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 277 of file stm32h7xx_hal_nand.c.

References HAL_NAND_ITCallback(), __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, and __NAND_HandleTypeDef::ItCallback.

void HAL_NAND_ITCallback ( NAND_HandleTypeDef * hnand )

NAND interrupt feature callback.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 343 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_Init(), HAL_NAND_IRQHandler(), and HAL_NAND_UnRegisterCallback().

void HAL_NAND_MspDeInit ( NAND_HandleTypeDef * hnand )

NAND MSP DeInit.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 260 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_DeInit(), and HAL_NAND_UnRegisterCallback().

void HAL_NAND_MspInit ( NAND_HandleTypeDef * hnand )

NAND MSP Init.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 244 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_Init(), and HAL_NAND_UnRegisterCallback().

HAL_StatusTypeDef HAL_NAND_Read_ID | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_IDTypeDef * | pNAND_ID
 | ) |  |

Read the NAND memory electronic signature.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_ID | NAND ID structure
Return values:
HAL status

Definition at line 379 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, CMD_AREA, NAND_IDTypeDef::Device_Id, NAND_IDTypeDef::Fourth_Id, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, __NAND_HandleTypeDef::Init, NAND_IDTypeDef::Maker_Id, NAND_CMD_READID, NAND_DEVICE, __NAND_HandleTypeDef::State, and NAND_IDTypeDef::Third_Id.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output functions

Functions
Input and Output functions
NAND Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
Register a User NAND Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
Unregister a User NAND Callback NAND Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### NAND Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NAND
    memory

Function Documentation

uint32_t HAL_NAND_Address_Inc | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

Increment the NAND memory address.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
Return values:
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 1814 of file stm32h7xx_hal_nand.c.

References NAND_AddressTypeDef::Block, NAND_DeviceConfigTypeDef::BlockSize, __NAND_HandleTypeDef::Config, NAND_INVALID_ADDRESS, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_AddressTypeDef::Plane, NAND_DeviceConfigTypeDef::PlaneNbr, and NAND_DeviceConfigTypeDef::PlaneSize.

HAL_StatusTypeDef HAL_NAND_ConfigDevice | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_DeviceConfigTypeDef * | pDeviceConfig
 | ) |  |

Configure the device: Enter the physical parameters of the device.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pDeviceConfig | pointer to NAND_DeviceConfigTypeDef structure
Return values:
HAL status

Definition at line 495 of file stm32h7xx_hal_nand.c.

References NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::PlaneNbr, NAND_DeviceConfigTypeDef::PlaneSize, and NAND_DeviceConfigTypeDef::SpareAreaSize.

HAL_StatusTypeDef HAL_NAND_Erase_Block | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

NAND memory Block erase.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
Return values:
HAL status

Definition at line 1758 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_DEVICE, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_ID | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_IDTypeDef * | pNAND_ID
 | ) |  |

Read the NAND memory electronic signature.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_ID | NAND ID structure
Return values:
HAL status

Definition at line 379 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, CMD_AREA, NAND_IDTypeDef::Device_Id, NAND_IDTypeDef::Fourth_Id, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, __NAND_HandleTypeDef::Init, NAND_IDTypeDef::Maker_Id, NAND_CMD_READID, NAND_DEVICE, __NAND_HandleTypeDef::State, and NAND_IDTypeDef::Third_Id.

HAL_StatusTypeDef HAL_NAND_Read_Page_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block (16-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to destination read buffer. pBuffer should be 16bits aligned
NumPageToRead | number of pages to read from block
Return values:
HAL status

Definition at line 673 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_Page_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block (8-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to destination read buffer
NumPageToRead | number of pages to read from block
Return values:
HAL status

Definition at line 518 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory (16-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaToRead | Number of spare area to read
Return values:
HAL status

Definition at line 1284 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory (8-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write
NumSpareAreaToRead | Number of spare area to read
Return values:
HAL status

Definition at line 1124 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, __NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_RegisterCallback | ( | NAND_HandleTypeDef * | hnand,
 |  | HAL_NAND_CallbackIDTypeDef | CallbackId,
 |  | pNAND_CallbackTypeDef | pCallback
 | ) |  |

Register a User NAND Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hnand | : NAND handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
  • HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
  • HAL_NAND_IT_CB_ID NAND IT callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1855 of file stm32h7xx_hal_nand.c.

References HAL_NAND_IT_CB_ID, HAL_NAND_MSP_DEINIT_CB_ID, HAL_NAND_MSP_INIT_CB_ID, HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, __NAND_HandleTypeDef::ItCallback, __NAND_HandleTypeDef::MspDeInitCallback, __NAND_HandleTypeDef::MspInitCallback, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Reset ( NAND_HandleTypeDef * hnand )

NAND memory reset.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 450 of file stm32h7xx_hal_nand.c.

References CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_DEVICE, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_UnRegisterCallback | ( | NAND_HandleTypeDef * | hnand,
 |  | HAL_NAND_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User NAND Callback NAND Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hnand : NAND handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
  • HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
  • HAL_NAND_IT_CB_ID NAND IT callback ID
Return values:
status

Definition at line 1924 of file stm32h7xx_hal_nand.c.

References HAL_NAND_IT_CB_ID, HAL_NAND_ITCallback(), HAL_NAND_MSP_DEINIT_CB_ID, HAL_NAND_MSP_INIT_CB_ID, HAL_NAND_MspDeInit(), HAL_NAND_MspInit(), HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, __NAND_HandleTypeDef::ItCallback, __NAND_HandleTypeDef::MspDeInitCallback, __NAND_HandleTypeDef::MspInitCallback, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block (16-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write. pBuffer should be 16bits aligned
NumPageToWrite | number of pages to write to block
Return values:
HAL status

Definition at line 975 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, __NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block (8-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write
NumPageToWrite | number of pages to write to block
Return values:
HAL status

Definition at line 826 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, __NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory (16-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaTowrite | number of spare areas to write to block
Return values:
HAL status

Definition at line 1602 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, __NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory (8-bits addressing)

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | pointer to NAND address structure
pBuffer | pointer to source buffer to write
NumSpareAreaTowrite | number of spare areas to write to block
Return values:
HAL status

Definition at line 1444 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, __NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_ERROR, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and __NAND_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
NAND Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.

Detailed Description

management functions

  ==============================================================================
                         ##### NAND Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NAND interface.

Function Documentation

HAL_StatusTypeDef HAL_NAND_ECC_Disable ( NAND_HandleTypeDef * hnand )

Disables dynamically FMC_NAND ECC feature.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 2036 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_ECC_Enable ( NAND_HandleTypeDef * hnand )

Enables dynamically NAND ECC feature.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 2004 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, and __NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_GetECC | ( | NAND_HandleTypeDef * | hnand,
 |  | uint32_t * | ECCval,
 |  | uint32_t | Timeout
 | ) |  |

Disables dynamically NAND ECC feature.

Parameters:
hnand | pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ECCval | pointer to ECC value
Timeout | maximum timeout to wait
Return values:
HAL status

Definition at line 2070 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, __NAND_HandleTypeDef::Init, __NAND_HandleTypeDef::Instance, and __NAND_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
NAND Exported Functions

Peripheral State functions. More...

Functions

HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                         ##### NAND State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NAND controller
    and the data flow.

Function Documentation

HAL_NAND_StateTypeDef HAL_NAND_GetState ( NAND_HandleTypeDef * hnand )

return the NAND state

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL state

Definition at line 2124 of file stm32h7xx_hal_nand.c.

References __NAND_HandleTypeDef::State.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 2135 of file stm32h7xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND Exported Types

Data Structures | Typedefs | Enumerations
NAND Exported Types
NAND

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_DeviceConfigTypeDef
NAND Memory info Structure definition. More...
struct | __NAND_HandleTypeDef
NAND handle Structure definition. More...

Typedefs

typedef struct __NAND_HandleTypeDef | NAND_HandleTypeDef
NAND handle Structure definition.
typedef void(* | pNAND_CallbackTypeDef )(NAND_HandleTypeDef *hnand)
HAL NAND Callback pointer definition.

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00U, HAL_NAND_STATE_READY = 0x01U, HAL_NAND_STATE_BUSY = 0x02U, HAL_NAND_STATE_ERROR = 0x03U }
HAL NAND State structures definition. More...
enum | HAL_NAND_CallbackIDTypeDef { HAL_NAND_MSP_INIT_CB_ID = 0x00U, HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, HAL_NAND_IT_CB_ID = 0x02U }
HAL NAND Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __NAND_HandleTypeDef NAND_HandleTypeDef

NAND handle Structure definition.

typedef void(* pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand)

HAL NAND Callback pointer definition.

Definition at line 152 of file stm32h7xx_hal_nand.h.

Enumeration Type Documentation

enum HAL_NAND_CallbackIDTypeDef

HAL NAND Callback ID enumeration definition.

Enumerator:
HAL_NAND_MSP_INIT_CB_ID

NAND MspInit Callback ID

HAL_NAND_MSP_DEINIT_CB_ID

NAND MspDeInit Callback ID

HAL_NAND_IT_CB_ID

NAND IT Callback ID

Definition at line 142 of file stm32h7xx_hal_nand.h.

enum HAL_NAND_StateTypeDef

HAL NAND State structures definition.

Enumerator:
HAL_NAND_STATE_RESET

NAND not yet initialized or disabled

HAL_NAND_STATE_READY

NAND initialized and ready for use

HAL_NAND_STATE_BUSY

NAND internal process is ongoing

HAL_NAND_STATE_ERROR

NAND error state

Definition at line 48 of file stm32h7xx_hal_nand.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_IDTypeDef Struct Reference
NAND Exported Types

NAND Memory electronic signature Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint8_t | Maker_Id
uint8_t | Device_Id
uint8_t | Third_Id
uint8_t | Fourth_Id

Detailed Description

NAND Memory electronic signature Structure definition.

Definition at line 59 of file stm32h7xx_hal_nand.h.

Field Documentation

uint8_t NAND_IDTypeDef::Device_Id

Definition at line 65 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Fourth_Id

Definition at line 69 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Maker_Id

Definition at line 63 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Third_Id

Definition at line 67 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND_AddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_AddressTypeDef Struct Reference
NAND Exported Types

NAND Memory address Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint16_t | Page
uint16_t | Plane
uint16_t | Block

Detailed Description

NAND Memory address Structure definition.

Definition at line 75 of file stm32h7xx_hal_nand.h.

Field Documentation

uint16_t NAND_AddressTypeDef::Block

NAND memory Block address

Definition at line 81 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Page

NAND memory Page address

Definition at line 77 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Plane

NAND memory Zone address

Definition at line 79 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND_DeviceConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_DeviceConfigTypeDef Struct Reference
NAND Exported Types

NAND Memory info Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint32_t | PageSize
uint32_t | SpareAreaSize
uint32_t | BlockSize
uint32_t | BlockNbr
uint32_t | PlaneNbr
uint32_t | PlaneSize
FunctionalState | ExtraCommandEnable

Detailed Description

NAND Memory info Structure definition.

Definition at line 88 of file stm32h7xx_hal_nand.h.

Field Documentation

uint32_t NAND_DeviceConfigTypeDef::BlockNbr

NAND memory number of total blocks

Definition at line 98 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::BlockSize

NAND memory block size measured in number of pages

Definition at line 96 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

FunctionalState NAND_DeviceConfigTypeDef::ExtraCommandEnable

NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE Please check the Read Mode sequnece in the NAND device datasheet

Definition at line 104 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), and HAL_NAND_Read_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::PageSize

NAND memory page (without spare area) size measured in bytes for 8 bits adressing or words for 16 bits addressing

Definition at line 90 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::PlaneNbr

NAND memory number of planes

Definition at line 100 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and HAL_NAND_ConfigDevice().

uint32_t NAND_DeviceConfigTypeDef::PlaneSize

NAND memory zone size measured in number of blocks

Definition at line 102 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and HAL_NAND_ConfigDevice().

uint32_t NAND_DeviceConfigTypeDef::SpareAreaSize

NAND memory spare area size measured in bytes for 8 bits adressing or words for 16 bits addressing

Definition at line 93 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __NAND_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__NAND_HandleTypeDef Struct Reference
NAND Exported Types

NAND handle Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

FMC_NAND_TypeDef * | Instance
FMC_NAND_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NAND_StateTypeDef | State
NAND_DeviceConfigTypeDef Config
void(* | MspInitCallback )(struct __NAND_HandleTypeDef *hnand)
void(* | MspDeInitCallback )(struct __NAND_HandleTypeDef *hnand)
void(* | ItCallback )(struct __NAND_HandleTypeDef *hnand)

Detailed Description

NAND handle Structure definition.

Definition at line 116 of file stm32h7xx_hal_nand.h.

Field Documentation

NAND_DeviceConfigTypeDef __NAND_HandleTypeDef::Config

NAND phusical characteristic information structure

Definition at line 129 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

FMC_NAND_InitTypeDef __NAND_HandleTypeDef::Init

NAND device control configuration parameters

Definition at line 123 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), HAL_NAND_IRQHandler(), and HAL_NAND_Read_ID().

FMC_NAND_TypeDef* __NAND_HandleTypeDef::Instance

Register base address

Definition at line 121 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

void(* __NAND_HandleTypeDef::ItCallback)(struct __NAND_HandleTypeDef *hnand)

NAND IT callback

Definition at line 134 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Init(), HAL_NAND_IRQHandler(), HAL_NAND_RegisterCallback(), and HAL_NAND_UnRegisterCallback().

HAL_LockTypeDef __NAND_HandleTypeDef::Lock

NAND locking object

Definition at line 125 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Init().

void(* __NAND_HandleTypeDef::MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand)

NAND Msp DeInit callback

Definition at line 133 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_RegisterCallback(), and HAL_NAND_UnRegisterCallback().

void(* __NAND_HandleTypeDef::MspInitCallback)(struct __NAND_HandleTypeDef *hnand)

NAND Msp Init callback

Definition at line 132 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Init(), HAL_NAND_RegisterCallback(), and HAL_NAND_UnRegisterCallback().

__IO HAL_NAND_StateTypeDef __NAND_HandleTypeDef::State

NAND device access state

Definition at line 127 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_Erase_Block(), HAL_NAND_GetECC(), HAL_NAND_GetState(), HAL_NAND_Init(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_RegisterCallback(), HAL_NAND_Reset(), HAL_NAND_UnRegisterCallback(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND Exported Macros

Defines
NAND Exported Macros
NAND

Defines

#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)
Reset NAND handle state.

Define Documentation

#define __HAL_NAND_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                             \
                                                               (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                             } while(0)

Reset NAND handle state.

Parameters:
__HANDLE__ specifies the NAND handle.
Return values:
None

Definition at line 170 of file stm32h7xx_hal_nand.h.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND Private Constants

Defines
NAND Private Constants
NAND

Defines

#define | NAND_DEVICE ((uint32_t)0x80000000U)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define | CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define | NAND_BUSY ((uint32_t)0x00000000U)
#define | NAND_ERROR ((uint32_t)0x00000001U)
#define | NAND_READY ((uint32_t)0x00000040U)

Define Documentation

#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */

Definition at line 277 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */

Definition at line 276 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_BUSY ((uint32_t)0x00000000U)

Definition at line 297 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_AREA_A ((uint8_t)0x00U)

Definition at line 279 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_AREA_B ((uint8_t)0x01U)

Definition at line 280 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_AREA_C ((uint8_t)0x50U)

Definition at line 281 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)

Definition at line 282 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), and HAL_NAND_Read_SpareArea_8b().

#define NAND_CMD_ERASE0 ((uint8_t)0x60U)

Definition at line 286 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)

Definition at line 287 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)

Definition at line 290 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_READID ((uint8_t)0x90U)

Definition at line 288 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define NAND_CMD_RESET ((uint8_t)0xFFU)

Definition at line 291 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_STATUS ((uint8_t)0x70U)

Definition at line 289 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_WRITE0 ((uint8_t)0x80U)

Definition at line 284 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)

Definition at line 285 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_DEVICE ((uint32_t)0x80000000U)

Definition at line 273 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_ERROR ((uint32_t)0x00000001U)

Definition at line 298 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)

Definition at line 295 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_READY ((uint32_t)0x00000040U)

Definition at line 299 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)

Definition at line 296 of file stm32h7xx_hal_nand.h.

#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)

Definition at line 294 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)

Definition at line 274 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND Private Macros

Defines
NAND Private Macros
NAND

Defines

#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | COLUMN_ADDRESS(__HANDLE__) ((__HANDLE__)->Config.PageSize)
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
NAND memory Columns cycling.
#define | COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Define Documentation

#define ADDR_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */

NAND memory address cycling.

Parameters:
__ADDRESS__ NAND memory address.
Return values:
NAND address cycling value.

Definition at line 325 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */

Definition at line 326 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_3RD_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */

Definition at line 327 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_4TH_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Definition at line 328 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define ARRAY_ADDRESS | ( | __ADDRESS__,
 |  | __HANDLE__
 | ) |
Value:
((__ADDRESS__)->Page + \
                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))

NAND memory address computation.

Parameters:
__ADDRESS__ | NAND memory address.
__HANDLE__ | NAND handle.
Return values:
NAND Raw address value

Definition at line 315 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */

NAND memory Columns cycling.

Parameters:
__ADDRESS__ NAND memory address.
Return values:
NAND Column address cycling value.

Definition at line 335 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Definition at line 336 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_ADDRESS ( __HANDLE__ ) ((__HANDLE__)->Config.PageSize)

Definition at line 318 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Private Defines

Defines
NOR Private Defines
NOR

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Define Documentation

#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA

Definition at line 133 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555

Definition at line 128 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055

Definition at line 129 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555

Definition at line 132 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA

Definition at line 130 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555

Definition at line 134 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555

Definition at line 131 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090

Definition at line 140 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_ID().

#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30

Definition at line 150 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block().

#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25

Definition at line 148 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29

Definition at line 149 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_CFI (uint16_t)0x0098

Definition at line 146 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055

Definition at line 144 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA

Definition at line 143 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080

Definition at line 142 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010

Definition at line 145 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA

Definition at line 138 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0

Definition at line 141 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Program().

#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0

Definition at line 137 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_CMD_DATA_SECOND (uint16_t)0x0055

Definition at line 139 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020

Definition at line 153 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Definition at line 154 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Private Variables

Variables
NOR Private Variables
NOR

Variables

static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B

Variable Documentation

uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B [static]

Definition at line 166 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NOR Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### NOR Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_DeInit ( NOR_HandleTypeDef * hnor )

Perform NOR memory De-Initialization sequence.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 265 of file stm32h7xx_hal_nor.c.

References __NOR_HandleTypeDef::Extended, HAL_NOR_MspDeInit(), HAL_NOR_STATE_RESET, __NOR_HandleTypeDef::Init, __NOR_HandleTypeDef::Instance, __NOR_HandleTypeDef::MspDeInitCallback, and __NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Init | ( | NOR_HandleTypeDef * | hnor,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timing | pointer to NOR control timing structure
ExtTiming | pointer to NOR extended mode timing structure
Return values:
HAL status

Definition at line 201 of file stm32h7xx_hal_nor.c.

References __NOR_HandleTypeDef::Extended, HAL_NOR_MspInit(), HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, __NOR_HandleTypeDef::Init, __NOR_HandleTypeDef::Instance, __NOR_HandleTypeDef::Lock, __NOR_HandleTypeDef::MspInitCallback, NOR_MEMORY_16B, NOR_MEMORY_8B, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

void HAL_NOR_MspDeInit ( NOR_HandleTypeDef * hnor )

NOR MSP DeInit.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 314 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_DeInit(), and HAL_NOR_UnRegisterCallback().

void HAL_NOR_MspInit ( NOR_HandleTypeDef * hnor )

NOR MSP Init.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 298 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Init(), and HAL_NOR_UnRegisterCallback().

void HAL_NOR_MspWait | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Timeout
 | ) |  |

NOR MSP Wait for Ready/Busy signal.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timeout | Maximum timeout value
Return values:
None

Definition at line 331 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output functions

Functions
Input and Output functions
NOR Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
Register a User NOR Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
Unregister a User NOR Callback NOR Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                ##### NOR Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_Erase_Block | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | BlockAddress,
 |  | uint32_t | Address
 | ) |  |

Erase the specified block of the NOR memory.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
BlockAddress | Block to erase address
Address | Device address
Return values:
HAL status

Definition at line 792 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_BLOCK_ERASE, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Erase_Chip | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address
 | ) |  |

Erase the entire NOR chip.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address | Device address
Return values:
HAL status

Definition at line 857 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_SIXTH, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_CHIP_ERASE, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Program | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Program data to NOR memory.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress | Device address
pData | pointer to the data to write
Return values:
HAL status

Definition at line 563 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_PROGRAM, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ProgramBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Writes a half-word buffer to the NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
hnor | pointer to the NOR handle
uwAddress | NOR memory internal start write address
pData | pointer to source data buffer.
uwBufferSize | Size of the buffer to write
Return values:
HAL status

Definition at line 704 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_BUFFER_AND_PROG, NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Read data from NOR memory.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress | pointer to Device address
pData | pointer to read data
Return values:
HAL status

Definition at line 496 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_CFI | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_CFITypeDef * | pNOR_CFI
 | ) |  |

Read NOR flash CFI IDs.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_CFI | pointer to NOR CFI IDs structure
Return values:
HAL status

Definition at line 922 of file stm32h7xx_hal_nor.c.

References CFI1_ADDRESS, CFI2_ADDRESS, CFI3_ADDRESS, CFI4_ADDRESS, NOR_CFITypeDef::CFI_1, NOR_CFITypeDef::CFI_2, NOR_CFITypeDef::CFI_3, NOR_CFITypeDef::CFI_4, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST_CFI, NOR_CMD_DATA_CFI, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_ID | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_IDTypeDef * | pNOR_ID
 | ) |  |

Read NOR flash IDs.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_ID | pointer to NOR ID structure
Return values:
HAL status

Definition at line 367 of file stm32h7xx_hal_nor.c.

References NOR_IDTypeDef::Device_Code1, DEVICE_CODE1_ADDR, NOR_IDTypeDef::Device_Code2, DEVICE_CODE2_ADDR, NOR_IDTypeDef::Device_Code3, DEVICE_CODE3_ADDR, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_IDTypeDef::Manufacturer_Code, MC_ADDRESS, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_AUTO_SELECT, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ReadBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Reads a half-word buffer from the NOR memory.

Parameters:
hnor | pointer to the NOR handle
uwAddress | NOR memory internal address to read from.
pData | pointer to the buffer that receives the data read from the NOR memory.
uwBufferSize | number of Half word to read.
Return values:
HAL status

Definition at line 629 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, __NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_RegisterCallback | ( | NOR_HandleTypeDef * | hnor,
 |  | HAL_NOR_CallbackIDTypeDef | CallbackId,
 |  | pNOR_CallbackTypeDef | pCallback
 | ) |  |

Register a User NOR Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hnor | : NOR handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  • HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 994 of file stm32h7xx_hal_nor.c.

References HAL_NOR_MSP_DEINIT_CB_ID, HAL_NOR_MSP_INIT_CB_ID, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, __NOR_HandleTypeDef::MspDeInitCallback, __NOR_HandleTypeDef::MspInitCallback, and __NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_ReturnToReadMode ( NOR_HandleTypeDef * hnor )

Returns the NOR memory to Read mode.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 435 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, NOR_CMD_DATA_READ_RESET, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and __NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_UnRegisterCallback | ( | NOR_HandleTypeDef * | hnor,
 |  | HAL_NOR_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User NOR Callback NOR Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hnor : NOR handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  • HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
Return values:
status

Definition at line 1045 of file stm32h7xx_hal_nor.c.

References HAL_NOR_MSP_DEINIT_CB_ID, HAL_NOR_MSP_INIT_CB_ID, HAL_NOR_MspDeInit(), HAL_NOR_MspInit(), HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, __NOR_HandleTypeDef::MspDeInitCallback, __NOR_HandleTypeDef::MspInitCallback, and __NOR_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Control functions

Functions
NOR Control functions
NOR Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.

Detailed Description

management functions

  ==============================================================================
                        ##### NOR Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NOR interface.

Function Documentation

HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable ( NOR_HandleTypeDef * hnor )

Disables dynamically NOR write operation.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 1141 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, __NOR_HandleTypeDef::Instance, and __NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable ( NOR_HandleTypeDef * hnor )

Enables dynamically NOR write operation.

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 1107 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, HAL_NOR_STATE_READY, __NOR_HandleTypeDef::Init, __NOR_HandleTypeDef::Instance, and __NOR_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR State functions

Functions
NOR State functions
NOR Exported Functions

Peripheral State functions. More...

Functions

HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### NOR State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NOR controller
    and the data flow.

Function Documentation

HAL_NOR_StateTypeDef HAL_NOR_GetState ( NOR_HandleTypeDef * hnor )

return the NOR controller state

Parameters:
hnor pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
NOR controller state

Definition at line 1194 of file stm32h7xx_hal_nor.c.

References __NOR_HandleTypeDef::State.

HAL_NOR_StatusTypeDef HAL_NOR_GetStatus | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address,
 |  | uint32_t | Timeout
 | ) |  |

Returns the NOR operation status.

Parameters:
hnor | pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address | Device address
Timeout | NOR programming Timeout
Return values:
NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR or HAL_NOR_STATUS_TIMEOUT

Definition at line 1208 of file stm32h7xx_hal_nor.c.

References HAL_GetTick(), HAL_NOR_MspWait(), HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_TIMEOUT, NOR_MASK_STATUS_DQ5, and NOR_MASK_STATUS_DQ6.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Exported Types

Data Structures | Typedefs | Enumerations
NOR Exported Types
NOR

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | __NOR_HandleTypeDef
NOR handle Structure definition. More...

Typedefs

typedef struct __NOR_HandleTypeDef | NOR_HandleTypeDef
NOR handle Structure definition.
typedef void(* | pNOR_CallbackTypeDef )(NOR_HandleTypeDef *hnor)
HAL NOR Callback pointer definition.

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00U, HAL_NOR_STATE_READY = 0x01U, HAL_NOR_STATE_BUSY = 0x02U, HAL_NOR_STATE_ERROR = 0x03U,
HAL_NOR_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...
enum | HAL_NOR_CallbackIDTypeDef { HAL_NOR_MSP_INIT_CB_ID = 0x00U, HAL_NOR_MSP_DEINIT_CB_ID = 0x01U }
HAL NOR Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __NOR_HandleTypeDef NOR_HandleTypeDef

NOR handle Structure definition.

typedef void(* pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor)

HAL NOR Callback pointer definition.

Definition at line 142 of file stm32h7xx_hal_nor.h.

Enumeration Type Documentation

enum HAL_NOR_CallbackIDTypeDef

HAL NOR Callback ID enumeration definition.

Enumerator:
HAL_NOR_MSP_INIT_CB_ID

NOR MspInit Callback ID

HAL_NOR_MSP_DEINIT_CB_ID

NOR MspDeInit Callback ID

Definition at line 133 of file stm32h7xx_hal_nor.h.

enum HAL_NOR_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_NOR_STATE_RESET

NOR not yet initialized or disabled

HAL_NOR_STATE_READY

NOR initialized and ready for use

HAL_NOR_STATE_BUSY

NOR internal processing is ongoing

HAL_NOR_STATE_ERROR

NOR error state

HAL_NOR_STATE_PROTECTED

NOR NORSRAM device write protected

Definition at line 48 of file stm32h7xx_hal_nor.h.

enum HAL_NOR_StatusTypeDef

FMC NOR Status typedef.

Enumerator:
HAL_NOR_STATUS_SUCCESS
HAL_NOR_STATUS_ONGOING
HAL_NOR_STATUS_ERROR
HAL_NOR_STATUS_TIMEOUT

Definition at line 60 of file stm32h7xx_hal_nor.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_IDTypeDef Struct Reference
NOR Exported Types

FMC NOR ID typedef. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

uint16_t | Manufacturer_Code
uint16_t | Device_Code1
uint16_t | Device_Code2
uint16_t | Device_Code3

Detailed Description

FMC NOR ID typedef.

Definition at line 71 of file stm32h7xx_hal_nor.h.

Field Documentation

uint16_t NOR_IDTypeDef::Device_Code1

Definition at line 75 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code2

Definition at line 77 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code3

Defines the device's codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command

Definition at line 79 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Manufacturer_Code

Defines the device's manufacturer code used to identify the memory

Definition at line 73 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR_CFITypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_CFITypeDef Struct Reference
NOR Exported Types

FMC NOR CFI typedef. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

uint16_t | CFI_1
uint16_t | CFI_2
uint16_t | CFI_3
uint16_t | CFI_4

Detailed Description

FMC NOR CFI typedef.

Definition at line 88 of file stm32h7xx_hal_nor.h.

Field Documentation

uint16_t NOR_CFITypeDef::CFI_1

< Defines the information stored in the memory's Common flash interface which contains a description of various electrical and timing parameters, density information and functions supported by the memory

Definition at line 94 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_2

Definition at line 96 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_3

Definition at line 98 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_4

Definition at line 100 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __NOR_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__NOR_HandleTypeDef Struct Reference
NOR Exported Types

NOR handle Structure definition. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NOR_StateTypeDef | State
void(* | MspInitCallback )(struct __NOR_HandleTypeDef *hnor)
void(* | MspDeInitCallback )(struct __NOR_HandleTypeDef *hnor)

Detailed Description

NOR handle Structure definition.

Definition at line 107 of file stm32h7xx_hal_nor.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* __NOR_HandleTypeDef::Extended

Extended mode register base address

Definition at line 115 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), and HAL_NOR_Init().

FMC_NORSRAM_InitTypeDef __NOR_HandleTypeDef::Init

NOR device control configuration parameters

Definition at line 117 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* __NOR_HandleTypeDef::Instance

Register base address

Definition at line 113 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Init(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

HAL_LockTypeDef __NOR_HandleTypeDef::Lock

NOR locking object

Definition at line 119 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

void(* __NOR_HandleTypeDef::MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor)

NOR Msp DeInit callback

Definition at line 125 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_RegisterCallback(), and HAL_NOR_UnRegisterCallback().

void(* __NOR_HandleTypeDef::MspInitCallback)(struct __NOR_HandleTypeDef *hnor)

NOR Msp Init callback

Definition at line 124 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init(), HAL_NOR_RegisterCallback(), and HAL_NOR_UnRegisterCallback().

__IO HAL_NOR_StateTypeDef __NOR_HandleTypeDef::State

NOR device access state

Definition at line 121 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_GetState(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_RegisterCallback(), HAL_NOR_ReturnToReadMode(), HAL_NOR_UnRegisterCallback(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Exported Macros

Defines
NOR Exported Macros
NOR

Defines

#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)
Reset NOR handle state.

Define Documentation

#define __HAL_NOR_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                             \
                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                             } while(0)

Reset NOR handle state.

Parameters:
__HANDLE__ specifies the NOR handle.
Return values:
None

Definition at line 158 of file stm32h7xx_hal_nor.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Private Constants

Defines
NOR Private Constants
NOR

Defines

#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x61U)
#define | CFI2_ADDRESS ((uint16_t)0x62U)
#define | CFI3_ADDRESS ((uint16_t)0x63U)
#define | CFI4_ADDRESS ((uint16_t)0x64U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)

Define Documentation

#define CFI1_ADDRESS ((uint16_t)0x61U)

Definition at line 254 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI2_ADDRESS ((uint16_t)0x62U)

Definition at line 255 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI3_ADDRESS ((uint16_t)0x63U)

Definition at line 256 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI4_ADDRESS ((uint16_t)0x64U)

Definition at line 257 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)

Definition at line 249 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)

Definition at line 250 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)

Definition at line 251 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define MC_ADDRESS ((uint16_t)0x0000U)

Definition at line 248 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define NOR_MEMORY_16B ((uint8_t)0x1U)

Definition at line 264 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_8B ((uint8_t)0x0U)

Definition at line 263 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)

Definition at line 267 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)

Definition at line 268 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)

Definition at line 269 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)

Definition at line 270 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_TMEOUT ((uint16_t)0xFFFFU)

Definition at line 260 of file stm32h7xx_hal_nor.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NOR Private Macros

Defines
NOR Private Macros
NOR

Defines

#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Define Documentation

#define NOR_ADDR_SHIFT | ( | __NOR_ADDRESS,
 |  | __NOR_MEMORY_WIDTH_,
 |  | __ADDRESS__
 | ) |
Value:
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

NOR memory address shifting.

Parameters:
__NOR_ADDRESS | NOR base address
__NOR_MEMORY_WIDTH_ | NOR memory width
__ADDRESS__ | NOR memory address
Return values:
NOR shifted address value

Definition at line 286 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_WRITE | ( | __ADDRESS__,
 |  | __DATA__
 | ) |
Value:
do{                                                             \
                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
                                               __DSB();                                                    \
                                             } while(0)

NOR memory write data to specified address.

Parameters:
__ADDRESS__ | NOR memory address
__DATA__ | Data to write
Return values:
None

Definition at line 297 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_DeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize the OPAMP peripheral.

Note:
Deinitialization can be performed if the OPAMP configuration is locked. (the lock is SW in H7)
Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 433 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspDeInit(), HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, __OPAMP_HandleTypeDef::MspDeInitCallback, OPAMP_CSR_RESET_VALUE, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Init ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.

Note:
If the selected opamp is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 278 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspInit(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, OPAMP_InitTypeDef::InvertingInput, IS_OPAMP_FUNCTIONAL_NORMALMODE, IS_OPAMP_INVERTING_INPUT_STANDALONE, IS_OPAMP_NONINVERTING_INPUT, IS_OPAMP_PGA_GAIN, IS_OPAMP_PGACONNECT, IS_OPAMP_POWERMODE, IS_OPAMP_TRIMMING, IS_OPAMP_TRIMMINGVALUE, __OPAMP_HandleTypeDef::Lock, OPAMP_InitTypeDef::Mode, __OPAMP_HandleTypeDef::MspInitCallback, OPAMP_InitTypeDef::NonInvertingInput, OPAMP_CSR_INIT_MASK_FOLLOWER, OPAMP_CSR_INIT_MASK_PGA, OPAMP_CSR_INIT_MASK_STANDALONE, OPAMP_FOLLOWER_MODE, OPAMP_INPUT_NONINVERTING, OPAMP_PGA_MODE, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PgaConnect, OPAMP_InitTypeDef::PgaGain, OPAMP_InitTypeDef::PowerMode, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

void HAL_OPAMP_MspDeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize OPAMP MSP.

Parameters:
hopamp OPAMP handle
Return values:
None

Definition at line 498 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit(), and HAL_OPAMP_UnRegisterCallback().

void HAL_OPAMP_MspInit ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP MSP.

Parameters:
hopamp OPAMP handle
Return values:
None

Definition at line 483 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init(), and HAL_OPAMP_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
OPAMP Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.

Detailed Description

IO operation functions.

 ===============================================================================
                        ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the OPAMP
    start, stop and calibration actions.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate ( OPAMP_HandleTypeDef * hopamp )

Run the self calibration of one OPAMP.

Note:
Calibration is performed in the mode specified in OPAMP init structure (mode normal or high-speed). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Parameters:
hopamp handle
Return values:
Updated | offset trimming values (PMOS & NMOS), user trimming is enabled
HAL | status

Definition at line 625 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, OPAMP_InitTypeDef::PowerMode, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

HAL_StatusTypeDef HAL_OPAMP_Start ( OPAMP_HandleTypeDef * hopamp )

Start the OPAMP.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 532 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Stop ( OPAMP_HandleTypeDef * hopamp )

Stop the OPAMP.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 574 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMP Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the OPAMP data
    transfers.

Function Documentation

HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | uint32_t | trimmingoffset
 | ) |  |

Return the OPAMP factory trimming value.

Note:
On STM32H7 OPAMP, user can retrieve factory trimming if OPAMP has never been set to user trimming before. Therefore, this function must be called when OPAMP init parameter "UserTrimming" is set to trimming factory, and before OPAMP calibration (function "HAL_OPAMP_SelfCalibrate()"). Otherwise, factory trimming value cannot be retrieved and error status is returned.
Parameters:
hopamp | OPAMP handle
trimmingoffset | Trimming offset (P or N) This parameter must be a value of OPAMP Factory Trimming
Note:
Calibration parameter retrieved is corresponding to the mode specified in OPAMP init structure (mode normal or high-speed). To retrieve calibration parameters for both modes, repeat this function after OPAMP init structure accordingly updated.
Return values:
Trimming value (P or N): range: 0->31 or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available

Definition at line 909 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, IS_OPAMP_FACTORYTRIMMING, IS_OPAMP_POWERMODE, OPAMP_FACTORYTRIMMING_DUMMY, OPAMP_FACTORYTRIMMING_P, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_NORMAL, OPAMP_InitTypeDef::PowerMode, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Lock ( OPAMP_HandleTypeDef * hopamp )

Lock the selected OPAMP configuration.

Note:
On STM32H7, HAL OPAMP lock is software lock only (in contrast of hardware lock available on some other STM32 devices)
Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 860 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_RegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId,
 |  | pOPAMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hopamp | OPAMP handle
CallbackId ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1026 of file stm32h7xx_hal_opamp.c.

References HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hopamp OPAMP handle
CallbackId ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID
  • HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
Return values:
status

Definition at line 1092 of file stm32h7xx_hal_opamp.c.

References HAL_OPAMP_ALL_CB_ID, HAL_OPAMP_MspDeInit(), HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MspInit(), HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
OPAMP Exported Functions

Peripheral State functions. More...

Functions

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState ( OPAMP_HandleTypeDef * hopamp )

Return the OPAMP handle state.

Parameters:
hopamp OPAMP handle
Return values:
HAL state

Definition at line 995 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Exported Functions

Modules | Functions
OPAMP Exported Functions
OPAMP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_RegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId,
 |  | pOPAMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hopamp | OPAMP handle
CallbackId ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1026 of file stm32h7xx_hal_opamp.c.

References HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hopamp OPAMP handle
CallbackId ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID
  • HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
Return values:
status

Definition at line 1092 of file stm32h7xx_hal_opamp.c.

References HAL_OPAMP_ALL_CB_ID, HAL_OPAMP_MspDeInit(), HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MspInit(), HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Exported Types

Data Structures | Typedefs | Enumerations
OPAMP Exported Types
OPAMP

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | __OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Typedefs

typedef struct
__OPAMP_HandleTypeDef 		OPAMP_HandleTypeDef
OPAMP Handle Structure definition.
typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000U, HAL_OPAMP_STATE_READY = 0x00000001U, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, HAL_OPAMP_STATE_BUSY = 0x00000004U,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U
}
HAL State structures definition. More...

Typedef Documentation

typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef

HAl_OPAMP_TrimmingValueTypeDef definition.

Definition at line 147 of file stm32h7xx_hal_opamp.h.

typedef struct __OPAMP_HandleTypeDef OPAMP_HandleTypeDef

OPAMP Handle Structure definition.

Enumeration Type Documentation

enum HAL_OPAMP_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_OPAMP_STATE_RESET

OPAMP is not yet Initialized

HAL_OPAMP_STATE_READY

OPAMP is initialized and ready for use

HAL_OPAMP_STATE_CALIBBUSY

OPAMP is enabled in auto calibration mode

HAL_OPAMP_STATE_BUSY

OPAMP is enabled and running in normal mode

HAL_OPAMP_STATE_BUSYLOCKED

OPAMP is locked only system reset allows reconfiguring the opamp.

Definition at line 109 of file stm32h7xx_hal_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_InitTypeDef Struct Reference
OPAMP Exported Types

OPAMP Init structure definition. More...

#include <stm32h7xx_hal_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | Mode
uint32_t | InvertingInput
uint32_t | NonInvertingInput
uint32_t | PgaGain
uint32_t | PgaConnect
uint32_t | UserTrimming
uint32_t | TrimmingValueP
uint32_t | TrimmingValueN
uint32_t | TrimmingValuePHighSpeed
uint32_t | TrimmingValueNHighSpeed

Detailed Description

OPAMP Init structure definition.

Definition at line 49 of file stm32h7xx_hal_opamp.h.

Field Documentation

uint32_t OPAMP_InitTypeDef::InvertingInput

Specifies the inverting input in Standalone & PGA modes

  • In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE This parameter must be a value of OPAMP Inverting Input
  • In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE & In PGA mode i.e when mode is OPAMP_PGA_MODE This parameter is Not Applicable

Definition at line 59 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::Mode

Specifies the OPAMP mode This parameter must be a value of OPAMP Mode mode is either Standalone, - Follower or PGA

Definition at line 55 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::NonInvertingInput

Specifies the non inverting input of the opamp: This parameter must be a value of OPAMP Non Inverting Input

Definition at line 66 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaConnect

Specifies the inverting pin in PGA mode i.e. when mode is OPAMP_PGA_MODE This parameter must be a value of OPAMP Pga Connect Either: not connected, connected to VINM0, connected to VINM1 (VINM0 or VINM1 are typically used for external filtering)

Definition at line 73 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaGain

Specifies the gain in PGA mode i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of OPAMP Pga Gain

Definition at line 69 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PowerMode

Specifies the power mode Normal or High Speed. This parameter must be a value of OPAMP PowerMode

Definition at line 52 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueN

Specifies the offset trimming value (NMOS) in Normal Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 88 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueNHighSpeed

Specifies the offset trimming value (NMOS) in High Speed Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 98 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueP

Specifies the offset trimming value (PMOS) in Normal Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 83 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValuePHighSpeed

Specifies the offset trimming value (PMOS) in High Speed Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 93 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::UserTrimming

Specifies the trimming mode This parameter must be a value of OPAMP User Trimming UserTrimming is either factory or user trimming.

Definition at line 79 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_opamp.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __OPAMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__OPAMP_HandleTypeDef Struct Reference
OPAMP Exported Types

OPAMP Handle Structure definition. More...

#include <stm32h7xx_hal_opamp.h>

Data Fields

OPAMP_TypeDef * | Instance
OPAMP_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_OPAMP_StateTypeDef | State
void(* | MspInitCallback )(struct __OPAMP_HandleTypeDef *hopamp)
void(* | MspDeInitCallback )(struct __OPAMP_HandleTypeDef *hopamp)

Detailed Description

OPAMP Handle Structure definition.

Definition at line 126 of file stm32h7xx_hal_opamp.h.

Field Documentation

OPAMP_InitTypeDef __OPAMP_HandleTypeDef::Init

OPAMP required parameters

Definition at line 132 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

OPAMP_TypeDef* __OPAMP_HandleTypeDef::Instance

OPAMP instance's registers base address

Definition at line 131 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_LockTypeDef __OPAMP_HandleTypeDef::Lock

Locking object

Definition at line 134 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

void(* __OPAMP_HandleTypeDef::MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp)

Definition at line 139 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_RegisterCallback(), and HAL_OPAMP_UnRegisterCallback().

void(* __OPAMP_HandleTypeDef::MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp)

Definition at line 138 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_RegisterCallback(), and HAL_OPAMP_UnRegisterCallback().

__IO HAL_OPAMP_StateTypeDef __OPAMP_HandleTypeDef::State

OPAMP communication state

Definition at line 135 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_RegisterCallback(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMP_UnRegisterCallback(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_StatusTypeDef __OPAMP_HandleTypeDef::Status

OPAMP peripheral status

Definition at line 133 of file stm32h7xx_hal_opamp.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_opamp.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Mode

Defines
OPAMP Mode
OPAMP Exported Constants

Defines

#define | OPAMP_STANDALONE_MODE 0x00000000U
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

Define Documentation

#define OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

follower mode

Definition at line 181 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1

PGA mode

Definition at line 180 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_STANDALONE_MODE 0x00000000U

standalone mode

Definition at line 179 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Non Inverting Input

Defines
OPAMP Non Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_NONINVERTINGINPUT_IO0 0x00000000U
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0
#define | OPAMP_NONINVERTINGINPUT_DAC2_CH OPAMP_CSR_VPSEL_1

Define Documentation

#define OPAMP_NONINVERTINGINPUT_DAC2_CH OPAMP_CSR_VPSEL_1

Only OPAMP2 non-inverting input connected internally to DAC2 channel

Definition at line 194 of file stm32h7xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0

OPAMP non-inverting input connected internally to DAC channel

Definition at line 192 of file stm32h7xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U

OPAMP non-inverting input connected to dedicated IO pin

Definition at line 191 of file stm32h7xx_hal_opamp.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Inverting Input

Defines
OPAMP Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_INVERTINGINPUT_IO0 0x00000000U
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

Define Documentation

#define OPAMP_INVERTINGINPUT_IO0 0x00000000U

OPAMP inverting input connected to dedicated IO pin

Definition at line 205 of file stm32h7xx_hal_opamp.h.

#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

OPAMP inverting input connected to dedicated IO pin

Definition at line 206 of file stm32h7xx_hal_opamp.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Pga Connect

Defines
OPAMP Pga Connect
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 0x00000000U
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)

Define Documentation

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2

In PGA mode, the inverting input is connected to VINM0

Definition at line 217 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3

In PGA mode, the inverting input is connected to VINM0 or bias

Definition at line 218 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)

In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering

Definition at line 219 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 0x00000000U

In PGA mode, the inverting input is not connected

Definition at line 216 of file stm32h7xx_hal_opamp.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Pga Gain

Defines
OPAMP Pga Gain
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

Define Documentation

#define OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

PGA gain could be 16 or -15

Definition at line 233 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U

PGA gain could be 2 or -1

Definition at line 230 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0

PGA gain could be 4 or -3

Definition at line 231 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1

PGA gain could be 8 or -7

Definition at line 232 of file stm32h7xx_hal_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | OPAMP_POWERMODE_NORMAL 0x00000000U
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM

Define Documentation

#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM

Definition at line 243 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_POWERMODE_NORMAL 0x00000000U

Definition at line 242 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP VREF

Defines
OPAMP VREF
OPAMP Exported Constants

Defines

#define | OPAMP_VREF_3VDDA 0x00000000U
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

Define Documentation

#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0

OPAMP Vref = 10% VDDA

Definition at line 255 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_VREF_3VDDA 0x00000000U

OPAMP Vref = 3.3% VDDA

Definition at line 254 of file stm32h7xx_hal_opamp.h.

#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1

OPAMP Vref = 50% VDDA

Definition at line 256 of file stm32h7xx_hal_opamp.h.

#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

OPAMP Vref = 90% VDDA

Definition at line 257 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP User Trimming

Defines
OPAMP User Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_TRIMMING_FACTORY 0x00000000U
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

Define Documentation

#define OPAMP_TRIMMING_FACTORY 0x00000000U

Factory trimming

Definition at line 266 of file stm32h7xx_hal_opamp.h.

#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

User trimming

Definition at line 267 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Factory Trimming

Defines
OPAMP Factory Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU
#define | OPAMP_FACTORYTRIMMING_N 0x00000000U
#define | OPAMP_FACTORYTRIMMING_P 0x00000001U

Define Documentation

#define OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU

Dummy value if trimming value could not be retrieved

Definition at line 277 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define OPAMP_FACTORYTRIMMING_N 0x00000000U

Offset trimming N

Definition at line 279 of file stm32h7xx_hal_opamp.h.

#define OPAMP_FACTORYTRIMMING_P 0x00000001U

Offset trimming P

Definition at line 280 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

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STM32H7B3xQ HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

OPAMP Private constants and defines. More...

Defines

#define | OPAMP_CSR_RESET_VALUE 0x00000000U
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE
#define | OPAMP_INPUT_NONINVERTING (8U)
#define | OPAMP_TRIMMING_DELAY (2U)

Detailed Description

OPAMP Private constants and defines.

Define Documentation

#define OPAMP_CSR_INIT_MASK_FOLLOWER
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
                                    | OPAMP_CSR_USERTRIM)

Definition at line 240 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_PGA
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_PGGAIN | OPAMP_CSR_PGGAIN  \
                                | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)

Definition at line 236 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_STANDALONE
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
                                       | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)

Definition at line 244 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_RESET_VALUE 0x00000000U

Definition at line 232 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_INPUT_NONINVERTING (8U)

Non inverting input

Definition at line 297 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_TRIMMING_DELAY (2U)

Definition at line 303 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

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STM32H7B3xQ HAL User Manual: OPAMP Exported Macros

Defines
OPAMP Exported Macros
OPAMP

Defines

#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.

Define Documentation

#define __HAL_OPAMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

Reset OPAMP handle state.

Parameters:
__HANDLE__,: OPAMP handle.
Return values:
None

Definition at line 318 of file stm32h7xx_hal_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_VREF(VREF)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Define Documentation

#define IS_OPAMP_FACTORYTRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))

Definition at line 372 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define IS_OPAMP_FUNCTIONAL_NORMALMODE ( INPUT )
Value:
(((INPUT) == OPAMP_STANDALONE_MODE) || \
                                               ((INPUT) == OPAMP_PGA_MODE) || \
                                               ((INPUT) == OPAMP_FOLLOWER_MODE))

Definition at line 330 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_INVERTING_INPUT_STANDALONE ( INPUT )
Value:
(((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))

Definition at line 334 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_NONINVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC2_CH))

Definition at line 338 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGA_GAIN ( GAIN )
Value:
(((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))

Definition at line 351 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGACONNECT ( CONNECT )
Value:
(((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))

Definition at line 346 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_POWERMODE ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
                                      ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )

Definition at line 362 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

Definition at line 366 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 370 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_VREF ( VREF )
Value:
(((VREF) == OPAMP_VREF_3VDDA)  || \
                             ((VREF) == OPAMP_VREF_10VDDA) || \
                             ((VREF) == OPAMP_VREF_50VDDA) || \
                             ((VREF) == OPAMP_VREF_90VDDA))

Definition at line 357 of file stm32h7xx_hal_opamp.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP

Modules | Typedefs | Enumerations
OPAMP
STM32H7xx_HAL_Driver

OPAMP module driver. More...

Modules

OPAMP Exported Functions
OPAMP Exported Types
OPAMP Exported Constants
OPAMP Private Constants

OPAMP Private constants and defines.

OPAMP Exported Macros
OPAMP Private Macros

Typedefs

typedef void(* | pOPAMP_CallbackTypeDef )(OPAMP_HandleTypeDef *hopamp)
HAL OPAMP Callback pointer definition.

Enumerations

enum | HAL_OPAMP_CallbackIDTypeDef { HAL_OPAMP_MSPINIT_CB_ID = 0x01U, HAL_OPAMP_MSPDEINIT_CB_ID = 0x02U, HAL_OPAMP_ALL_CB_ID = 0x03U }
HAL OPAMP Callback ID enumeration definition. More...

Detailed Description

OPAMP module driver.

Typedef Documentation

typedef void(* pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp)

HAL OPAMP Callback pointer definition.

Definition at line 167 of file stm32h7xx_hal_opamp.h.

Enumeration Type Documentation

enum HAL_OPAMP_CallbackIDTypeDef

HAL OPAMP Callback ID enumeration definition.

Enumerator:
HAL_OPAMP_MSPINIT_CB_ID

OPAMP MspInit Callback ID

HAL_OPAMP_MSPDEINIT_CB_ID

OPAMP MspDeInit Callback ID

HAL_OPAMP_ALL_CB_ID

OPAMP All ID

Definition at line 157 of file stm32h7xx_hal_opamp.h.

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STM32H7B3xQ HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
OSPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
Initialize the OSPI mode according to the specified parameters in the OSPI_InitTypeDef and initialize the associated handle.
__weak void | HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi)
Initialize the OSPI MSP.
HAL_StatusTypeDef | HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi)
De-Initialize the OSPI peripheral.
__weak void | HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi)
DeInitialize the OSPI MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Initialize the OctoSPI.
      (+) De-initialize the OctoSPI.

Function Documentation

HAL_StatusTypeDef HAL_OSPI_DeInit ( OSPI_HandleTypeDef * hospi )

De-Initialize the OSPI peripheral.

Parameters:
hospi : OSPI handle
Return values:
HAL status

Definition at line 466 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_DISABLE, HAL_OSPI_MspDeInit(), HAL_OSPI_STATE_RESET, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::MspDeInitCallback, and __OSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OSPI_Init ( OSPI_HandleTypeDef * hospi )

Initialize the OSPI mode according to the specified parameters in the OSPI_InitTypeDef and initialize the associated handle.

Parameters:
hospi : OSPI handle
Return values:
HAL status

Definition at line 318 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_ENABLE, __OSPI_HandleTypeDef::AbortCpltCallback, assert_param, OSPI_InitTypeDef::ChipSelectBoundary, OSPI_InitTypeDef::ChipSelectHighTime, OSPI_InitTypeDef::ClkChipSelectHighTime, OSPI_InitTypeDef::ClockMode, OSPI_InitTypeDef::ClockPrescaler, __OSPI_HandleTypeDef::CmdCpltCallback, OSPI_InitTypeDef::DelayBlockBypass, OSPI_InitTypeDef::DelayHoldQuarterCycle, OSPI_InitTypeDef::DeviceSize, OSPI_InitTypeDef::DualQuad, __OSPI_HandleTypeDef::ErrorCallback, __OSPI_HandleTypeDef::ErrorCode, OSPI_InitTypeDef::FifoThreshold, __OSPI_HandleTypeDef::FifoThresholdCallback, OSPI_InitTypeDef::FreeRunningClock, HAL_GetTick(), HAL_OSPI_AbortCpltCallback(), HAL_OSPI_CmdCpltCallback(), HAL_OSPI_ERROR_NONE, HAL_OSPI_ErrorCallback(), HAL_OSPI_FifoThresholdCallback(), HAL_OSPI_FLAG_BUSY, HAL_OSPI_FREERUNCLK_ENABLE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_MspInit(), HAL_OSPI_RxCpltCallback(), HAL_OSPI_RxHalfCpltCallback(), HAL_OSPI_SetTimeout(), HAL_OSPI_STATE_HYPERBUS_INIT, HAL_OSPI_STATE_READY, HAL_OSPI_STATE_RESET, HAL_OSPI_StatusMatchCallback(), HAL_OSPI_TIMEOUT_DEFAULT_VALUE, HAL_OSPI_TimeOutCallback(), HAL_OSPI_TxCpltCallback(), HAL_OSPI_TxHalfCpltCallback(), __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_InitTypeDef::MaxTran, OSPI_InitTypeDef::MemoryType, __OSPI_HandleTypeDef::MspInitCallback, OSPI_InitTypeDef::Refresh, __OSPI_HandleTypeDef::RxCpltCallback, __OSPI_HandleTypeDef::RxHalfCpltCallback, OSPI_InitTypeDef::SampleShifting, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::StatusMatchCallback, __OSPI_HandleTypeDef::Timeout, __OSPI_HandleTypeDef::TimeOutCallback, __OSPI_HandleTypeDef::TxCpltCallback, __OSPI_HandleTypeDef::TxHalfCpltCallback, and OSPI_InitTypeDef::WrapSize.

void HAL_OSPI_MspDeInit ( OSPI_HandleTypeDef * hospi )

DeInitialize the OSPI MSP.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 509 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_DeInit(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_MspInit ( OSPI_HandleTypeDef * hospi )

Initialize the OSPI MSP.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 451 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), and HAL_OSPI_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
OSPI Exported Functions

OSPI Transmit/Receive functions. More...

Functions

void | HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi)
Handle OSPI interrupt request.
HAL_StatusTypeDef | HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
Configure the Hyperbus parameters.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
Set the Hyperbus command configuration.
HAL_StatusTypeDef | HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the OSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
Configure the OSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi)
Transfer Error callback.
__weak void | HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi)
Abort completed callback.
__weak void | HAL_OSPI_FifoThresholdCallback (OSPI_HandleTypeDef *hospi)
FIFO Threshold callback.
__weak void | HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi)
Command completed callback.
__weak void | HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Transfer completed callback.
__weak void | HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Transfer completed callback.
__weak void | HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Half Transfer completed callback.
__weak void | HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Half Transfer completed callback.
__weak void | HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi)
Status Match callback.
__weak void | HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi)
Timeout callback.
HAL_StatusTypeDef | HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
Register a User OSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
Unregister a User OSPI Callback OSPI Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

OSPI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Handle the interrupts.
      (+) Handle the command sequence (regular and Hyperbus).
      (+) Handle the Hyperbus configuration.
      (+) Transmit data in blocking, interrupt or DMA mode.
      (+) Receive data in blocking, interrupt or DMA mode.
      (+) Manage the auto-polling functional mode.
      (+) Manage the memory-mapped functional mode.

Function Documentation

void HAL_OSPI_AbortCpltCallback ( OSPI_HandleTypeDef * hospi )

Abort completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1839 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_OSPI_AutoPolling | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the OSPI Automatic Polling Mode in blocking mode.

Parameters:
hospi | : OSPI handle
cfg | : structure that contains the polling configuration information.
Timeout | : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1618 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, assert_param, OSPI_AutoPollingTypeDef::AutomaticStop, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_AUTOMATIC_STOP_ENABLE, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_SM, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_AutoPollingTypeDef::Interval, OSPI_AutoPollingTypeDef::Mask, OSPI_AutoPollingTypeDef::Match, OSPI_AutoPollingTypeDef::MatchMode, OSPI_InitTypeDef::MemoryType, and __OSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the OSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hospi | : OSPI handle
cfg | : structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1696 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, assert_param, OSPI_AutoPollingTypeDef::AutomaticStop, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_SM, HAL_OSPI_FLAG_TE, HAL_OSPI_IT_SM, HAL_OSPI_IT_TE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_BUSY_AUTO_POLLING, HAL_OSPI_STATE_CMD_CFG, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_AutoPollingTypeDef::Interval, OSPI_AutoPollingTypeDef::Mask, OSPI_AutoPollingTypeDef::Match, OSPI_AutoPollingTypeDef::MatchMode, OSPI_InitTypeDef::MemoryType, __OSPI_HandleTypeDef::State, and __OSPI_HandleTypeDef::Timeout.

void HAL_OSPI_CmdCpltCallback ( OSPI_HandleTypeDef * hospi )

Command completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1869 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_OSPI_Command | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_RegularCmdTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hospi | : OSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 780 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, OSPI_RegularCmdTypeDef::AddressDtrMode, OSPI_RegularCmdTypeDef::AddressMode, OSPI_RegularCmdTypeDef::AddressSize, OSPI_RegularCmdTypeDef::AlternateBytesDtrMode, OSPI_RegularCmdTypeDef::AlternateBytesMode, OSPI_RegularCmdTypeDef::AlternateBytesSize, assert_param, OSPI_RegularCmdTypeDef::DataDtrMode, OSPI_RegularCmdTypeDef::DataMode, OSPI_RegularCmdTypeDef::DQSMode, OSPI_InitTypeDef::DualQuad, OSPI_RegularCmdTypeDef::DummyCycles, __OSPI_HandleTypeDef::ErrorCode, OSPI_RegularCmdTypeDef::FlashId, HAL_GetTick(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ALTERNATE_BYTES_NONE, HAL_OSPI_DATA_NONE, HAL_OSPI_DUALQUAD_DISABLE, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_ERROR_NONE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_TC, HAL_OSPI_INSTRUCTION_NONE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_OPTYPE_COMMON_CFG, HAL_OSPI_OPTYPE_READ_CFG, HAL_OSPI_OPTYPE_WRAP_CFG, HAL_OSPI_OPTYPE_WRITE_CFG, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READ_CMD_CFG, HAL_OSPI_STATE_READY, HAL_OSPI_STATE_WRITE_CMD_CFG, __OSPI_HandleTypeDef::Init, OSPI_RegularCmdTypeDef::InstructionDtrMode, OSPI_RegularCmdTypeDef::InstructionMode, OSPI_RegularCmdTypeDef::InstructionSize, OSPI_InitTypeDef::MemoryType, OSPI_RegularCmdTypeDef::NbData, OSPI_RegularCmdTypeDef::OperationType, OSPI_RegularCmdTypeDef::SIOOMode, and __OSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OSPI_Command_IT | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_RegularCmdTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hospi | : OSPI handle
cmd | : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 910 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, OSPI_RegularCmdTypeDef::AddressDtrMode, OSPI_RegularCmdTypeDef::AddressMode, OSPI_RegularCmdTypeDef::AddressSize, OSPI_RegularCmdTypeDef::AlternateBytesDtrMode, OSPI_RegularCmdTypeDef::AlternateBytesMode, OSPI_RegularCmdTypeDef::AlternateBytesSize, assert_param, OSPI_RegularCmdTypeDef::DataDtrMode, OSPI_RegularCmdTypeDef::DataMode, OSPI_RegularCmdTypeDef::DQSMode, OSPI_InitTypeDef::DualQuad, OSPI_RegularCmdTypeDef::DummyCycles, __OSPI_HandleTypeDef::ErrorCode, OSPI_RegularCmdTypeDef::FlashId, HAL_GetTick(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ALTERNATE_BYTES_NONE, HAL_OSPI_DATA_NONE, HAL_OSPI_DUALQUAD_DISABLE, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_ERROR_NONE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_INSTRUCTION_NONE, HAL_OSPI_IT_TC, HAL_OSPI_IT_TE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_OPTYPE_COMMON_CFG, HAL_OSPI_STATE_BUSY_CMD, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Init, OSPI_RegularCmdTypeDef::InstructionDtrMode, OSPI_RegularCmdTypeDef::InstructionMode, OSPI_RegularCmdTypeDef::InstructionSize, OSPI_InitTypeDef::MemoryType, OSPI_RegularCmdTypeDef::NbData, OSPI_RegularCmdTypeDef::OperationType, OSPI_RegularCmdTypeDef::SIOOMode, __OSPI_HandleTypeDef::State, and __OSPI_HandleTypeDef::Timeout.

void HAL_OSPI_ErrorCallback ( OSPI_HandleTypeDef * hospi )

Transfer Error callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1824 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_FifoThresholdCallback ( OSPI_HandleTypeDef * hospi )

FIFO Threshold callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1854 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_OSPI_HyperbusCfg | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_HyperbusCfgTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the Hyperbus parameters.

Parameters:
hospi | : OSPI handle
cfg | : Structure containing the Hyperbus configuration
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 1000 of file stm32h7xx_hal_ospi.c.

References OSPI_HyperbusCfgTypeDef::AccessTime, assert_param, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_STATE_HYPERBUS_INIT, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Instance, OSPI_HyperbusCfgTypeDef::LatencyMode, OSPI_HyperbusCfgTypeDef::RWRecoveryTime, __OSPI_HandleTypeDef::State, and OSPI_HyperbusCfgTypeDef::WriteZeroLatency.

HAL_StatusTypeDef HAL_OSPI_HyperbusCmd | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_HyperbusCmdTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the Hyperbus command configuration.

Parameters:
hospi | : OSPI handle
cmd | : Structure containing the Hyperbus command
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 1047 of file stm32h7xx_hal_ospi.c.

References OSPI_HyperbusCmdTypeDef::Address, OSPI_HyperbusCmdTypeDef::AddressSize, OSPI_HyperbusCmdTypeDef::AddressSpace, assert_param, OSPI_HyperbusCmdTypeDef::DQSMode, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_InitTypeDef::MemoryType, OSPI_HyperbusCmdTypeDef::NbData, and __OSPI_HandleTypeDef::State.

void HAL_OSPI_IRQHandler ( OSPI_HandleTypeDef * hospi )

Handle OSPI interrupt request.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 549 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_DISABLE_IT, __OSPI_HandleTypeDef::AbortCpltCallback, __OSPI_HandleTypeDef::CmdCpltCallback, __OSPI_HandleTypeDef::ErrorCallback, __OSPI_HandleTypeDef::ErrorCode, __OSPI_HandleTypeDef::FifoThresholdCallback, HAL_MDMA_Abort_IT(), HAL_OSPI_AbortCpltCallback(), HAL_OSPI_CmdCpltCallback(), HAL_OSPI_ERROR_NONE, HAL_OSPI_ERROR_TRANSFER, HAL_OSPI_ErrorCallback(), HAL_OSPI_FifoThresholdCallback(), HAL_OSPI_FLAG_FT, HAL_OSPI_FLAG_SM, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_FLAG_TO, HAL_OSPI_IT_FT, HAL_OSPI_IT_SM, HAL_OSPI_IT_TC, HAL_OSPI_IT_TE, HAL_OSPI_IT_TO, HAL_OSPI_RxCpltCallback(), HAL_OSPI_STATE_ABORT, HAL_OSPI_STATE_BUSY_CMD, HAL_OSPI_STATE_BUSY_RX, HAL_OSPI_STATE_BUSY_TX, HAL_OSPI_STATE_READY, HAL_OSPI_StatusMatchCallback(), HAL_OSPI_TimeOutCallback(), HAL_OSPI_TxCpltCallback(), __OSPI_HandleTypeDef::hmdma, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::RxCpltCallback, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::StatusMatchCallback, __OSPI_HandleTypeDef::TimeOutCallback, __OSPI_HandleTypeDef::TxCpltCallback, __MDMA_HandleTypeDef::XferAbortCallback, and __OSPI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_OSPI_MemoryMapped | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hospi | : OSPI handle
cfg | : structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1771 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, assert_param, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_TO, HAL_OSPI_IT_TO, HAL_OSPI_STATE_BUSY_MEM_MAPPED, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_TIMEOUT_COUNTER_ENABLE, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::Timeout, OSPI_MemoryMappedTypeDef::TimeOutActivation, and OSPI_MemoryMappedTypeDef::TimeOutPeriod.

HAL_StatusTypeDef HAL_OSPI_Receive | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1183 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_FT, HAL_OSPI_FLAG_TC, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_InitTypeDef::MemoryType, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::XferCount, and __OSPI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_OSPI_Receive_DMA | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1500 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, MDMA_InitTypeDef::DestDataSize, __OSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Start_IT(), HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ERROR_DMA, HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_IT_TE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_BUSY_RX, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::hmdma, __OSPI_HandleTypeDef::Init, __MDMA_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, MDMA_DEST_DATASIZE_BYTE, MDMA_DEST_DATASIZE_HALFWORD, MDMA_DEST_DATASIZE_WORD, MDMA_DEST_INC_BYTE, MDMA_DEST_INC_HALFWORD, MDMA_DEST_INC_WORD, MDMA_SRC_INC_DISABLE, OSPI_InitTypeDef::MemoryType, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __OSPI_HandleTypeDef::XferCount, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __OSPI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_OSPI_Receive_IT | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1325 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, __OSPI_HandleTypeDef::ErrorCode, HAL_OSPI_ADDRESS_NONE, HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_IT_FT, HAL_OSPI_IT_TC, HAL_OSPI_IT_TE, HAL_OSPI_MEMTYPE_HYPERBUS, HAL_OSPI_STATE_BUSY_RX, HAL_OSPI_STATE_CMD_CFG, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, OSPI_InitTypeDef::MemoryType, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::XferCount, and __OSPI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_OSPI_RegisterCallback | ( | OSPI_HandleTypeDef * | hospi,
 |  | HAL_OSPI_CallbackIDTypeDef | CallbackID,
 |  | pOSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User OSPI Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hospi | : OSPI handle
CallbackID : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
  • HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
  • HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
  • HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
  • HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
  • HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
  • HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
  • HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
  • HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
  • HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
  • HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
  • HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1991 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::AbortCpltCallback, __OSPI_HandleTypeDef::CmdCpltCallback, __OSPI_HandleTypeDef::ErrorCallback, __OSPI_HandleTypeDef::ErrorCode, __OSPI_HandleTypeDef::FifoThresholdCallback, HAL_OSPI_ABORT_CB_ID, HAL_OSPI_CMD_CPLT_CB_ID, HAL_OSPI_ERROR_CB_ID, HAL_OSPI_ERROR_INVALID_CALLBACK, HAL_OSPI_FIFO_THRESHOLD_CB_ID, HAL_OSPI_MSP_DEINIT_CB_ID, HAL_OSPI_MSP_INIT_CB_ID, HAL_OSPI_RX_CPLT_CB_ID, HAL_OSPI_RX_HALF_CPLT_CB_ID, HAL_OSPI_STATE_READY, HAL_OSPI_STATE_RESET, HAL_OSPI_STATUS_MATCH_CB_ID, HAL_OSPI_TIMEOUT_CB_ID, HAL_OSPI_TX_CPLT_CB_ID, HAL_OSPI_TX_HALF_CPLT_CB_ID, __OSPI_HandleTypeDef::MspDeInitCallback, __OSPI_HandleTypeDef::MspInitCallback, __OSPI_HandleTypeDef::RxCpltCallback, __OSPI_HandleTypeDef::RxHalfCpltCallback, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::StatusMatchCallback, __OSPI_HandleTypeDef::TimeOutCallback, __OSPI_HandleTypeDef::TxCpltCallback, and __OSPI_HandleTypeDef::TxHalfCpltCallback.

void HAL_OSPI_RxCpltCallback ( OSPI_HandleTypeDef * hospi )

Rx Transfer completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1884 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_RxHalfCpltCallback ( OSPI_HandleTypeDef * hospi )

Rx Half Transfer completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1914 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_StatusMatchCallback ( OSPI_HandleTypeDef * hospi )

Status Match callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1944 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_TimeOutCallback ( OSPI_HandleTypeDef * hospi )

Timeout callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1959 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_OSPI_Transmit | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer
Timeout | : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1109 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_FT, HAL_OSPI_FLAG_TC, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::XferCount, and __OSPI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_OSPI_Transmit_DMA | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1398 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, __OSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Start_IT(), HAL_OSPI_ERROR_DMA, HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_IT_TE, HAL_OSPI_STATE_BUSY_TX, HAL_OSPI_STATE_CMD_CFG, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::hmdma, __MDMA_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, MDMA_DEST_INC_DISABLE, MDMA_SRC_DATASIZE_BYTE, MDMA_SRC_DATASIZE_HALFWORD, MDMA_SRC_DATASIZE_WORD, MDMA_SRC_INC_BYTE, MDMA_SRC_INC_HALFWORD, MDMA_SRC_INC_WORD, __OSPI_HandleTypeDef::pBuffPtr, MDMA_InitTypeDef::SourceDataSize, __OSPI_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __OSPI_HandleTypeDef::XferCount, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __OSPI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_OSPI_Transmit_IT | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hospi | : OSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1275 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_ENABLE_IT, __OSPI_HandleTypeDef::ErrorCode, HAL_OSPI_ERROR_INVALID_PARAM, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_TC, HAL_OSPI_FLAG_TE, HAL_OSPI_IT_FT, HAL_OSPI_IT_TC, HAL_OSPI_IT_TE, HAL_OSPI_STATE_BUSY_TX, HAL_OSPI_STATE_CMD_CFG, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::pBuffPtr, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::XferCount, and __OSPI_HandleTypeDef::XferSize.

void HAL_OSPI_TxCpltCallback ( OSPI_HandleTypeDef * hospi )

Tx Transfer completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1899 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), and HAL_OSPI_UnRegisterCallback().

void HAL_OSPI_TxHalfCpltCallback ( OSPI_HandleTypeDef * hospi )

Tx Half Transfer completed callback.

Parameters:
hospi : OSPI handle
Return values:
None

Definition at line 1929 of file stm32h7xx_hal_ospi.c.

Referenced by HAL_OSPI_Init(), and HAL_OSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback | ( | OSPI_HandleTypeDef * | hospi,
 |  | HAL_OSPI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User OSPI Callback OSPI Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hospi : OSPI handle
CallbackID : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
  • HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
  • HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
  • HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
  • HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
  • HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
  • HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
  • HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
  • HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
  • HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
  • HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
  • HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
Return values:
status

Definition at line 2099 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::AbortCpltCallback, __OSPI_HandleTypeDef::CmdCpltCallback, __OSPI_HandleTypeDef::ErrorCallback, __OSPI_HandleTypeDef::ErrorCode, __OSPI_HandleTypeDef::FifoThresholdCallback, HAL_OSPI_ABORT_CB_ID, HAL_OSPI_AbortCpltCallback(), HAL_OSPI_CMD_CPLT_CB_ID, HAL_OSPI_CmdCpltCallback(), HAL_OSPI_ERROR_CB_ID, HAL_OSPI_ERROR_INVALID_CALLBACK, HAL_OSPI_ErrorCallback(), HAL_OSPI_FIFO_THRESHOLD_CB_ID, HAL_OSPI_FifoThresholdCallback(), HAL_OSPI_MSP_DEINIT_CB_ID, HAL_OSPI_MSP_INIT_CB_ID, HAL_OSPI_MspDeInit(), HAL_OSPI_MspInit(), HAL_OSPI_RX_CPLT_CB_ID, HAL_OSPI_RX_HALF_CPLT_CB_ID, HAL_OSPI_RxCpltCallback(), HAL_OSPI_RxHalfCpltCallback(), HAL_OSPI_STATE_READY, HAL_OSPI_STATE_RESET, HAL_OSPI_STATUS_MATCH_CB_ID, HAL_OSPI_StatusMatchCallback(), HAL_OSPI_TIMEOUT_CB_ID, HAL_OSPI_TimeOutCallback(), HAL_OSPI_TX_CPLT_CB_ID, HAL_OSPI_TX_HALF_CPLT_CB_ID, HAL_OSPI_TxCpltCallback(), HAL_OSPI_TxHalfCpltCallback(), __OSPI_HandleTypeDef::MspDeInitCallback, __OSPI_HandleTypeDef::MspInitCallback, __OSPI_HandleTypeDef::RxCpltCallback, __OSPI_HandleTypeDef::RxHalfCpltCallback, __OSPI_HandleTypeDef::State, __OSPI_HandleTypeDef::StatusMatchCallback, __OSPI_HandleTypeDef::TimeOutCallback, __OSPI_HandleTypeDef::TxCpltCallback, and __OSPI_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control and State functions

Functions
Peripheral Control and State functions
OSPI Exported Functions

OSPI control and State functions. More...

Functions

HAL_StatusTypeDef | HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi)
Abort the current transmission (non-blocking function)
HAL_StatusTypeDef | HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold)
Set OSPI Fifo threshold.
uint32_t | HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi)
Get OSPI Fifo threshold.
HAL_StatusTypeDef | HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout)
Set OSPI timeout.
uint32_t | HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi)
Return the OSPI error code.
uint32_t | HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi)
Return the OSPI handle state.

Detailed Description

OSPI control and State functions.

 ===============================================================================
                  ##### Peripheral Control and State functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Check in run-time the state of the driver.
      (+) Check the error code set during last operation.
      (+) Abort any operation.
      (+) Manage the Fifo threshold.
      (+) Configure the timeout duration used in the driver.

Function Documentation

HAL_StatusTypeDef HAL_OSPI_Abort ( OSPI_HandleTypeDef * hospi )

Abort the current transmission.

Parameters:
hospi : OSPI handle
Return values:
HAL status

Definition at line 2209 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_GET_FLAG, __OSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_Abort(), HAL_OSPI_ERROR_DMA, HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_TC, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::hmdma, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::State, and __OSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_OSPI_Abort_IT ( OSPI_HandleTypeDef * hospi )

Abort the current transmission (non-blocking function)

Parameters:
hospi : OSPI handle
Return values:
HAL status

Definition at line 2277 of file stm32h7xx_hal_ospi.c.

References __HAL_OSPI_CLEAR_FLAG, __HAL_OSPI_DISABLE_IT, __HAL_OSPI_ENABLE_IT, __HAL_OSPI_GET_FLAG, __OSPI_HandleTypeDef::AbortCpltCallback, __OSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Abort_IT(), HAL_OSPI_AbortCpltCallback(), HAL_OSPI_ERROR_INVALID_SEQUENCE, HAL_OSPI_FLAG_BUSY, HAL_OSPI_FLAG_TC, HAL_OSPI_IT_FT, HAL_OSPI_IT_SM, HAL_OSPI_IT_TC, HAL_OSPI_IT_TE, HAL_OSPI_IT_TO, HAL_OSPI_STATE_ABORT, HAL_OSPI_STATE_READY, __OSPI_HandleTypeDef::hmdma, __OSPI_HandleTypeDef::Instance, __OSPI_HandleTypeDef::State, and __MDMA_HandleTypeDef::XferAbortCallback.

uint32_t HAL_OSPI_GetError ( OSPI_HandleTypeDef * hospi )

Return the OSPI error code.

Parameters:
hospi : OSPI handle
Return values:
OSPI Error Code

Definition at line 2404 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_OSPI_GetFifoThreshold ( OSPI_HandleTypeDef * hospi )

Get OSPI Fifo threshold.

Parameters:
hospi : OSPI handle.
Return values:
Fifo threshold

Definition at line 2383 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::Instance.

uint32_t HAL_OSPI_GetState ( OSPI_HandleTypeDef * hospi )

Return the OSPI handle state.

Parameters:
hospi : OSPI handle
Return values:
HAL state

Definition at line 2414 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint32_t | Threshold
 | ) |  |

Set OSPI Fifo threshold.

Parameters:
hospi | : OSPI handle.
Threshold | : Threshold of the Fifo.
Return values:
HAL status

Definition at line 2355 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::ErrorCode, OSPI_InitTypeDef::FifoThreshold, HAL_OSPI_ERROR_INVALID_SEQUENCE, __OSPI_HandleTypeDef::Init, __OSPI_HandleTypeDef::Instance, and __OSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OSPI_SetTimeout | ( | OSPI_HandleTypeDef * | hospi,
 |  | uint32_t | Timeout
 | ) |  |

Set OSPI timeout.

Parameters:
hospi | : OSPI handle.
Timeout | : Timeout for the memory access.
Return values:
None

Definition at line 2393 of file stm32h7xx_hal_ospi.c.

References __OSPI_HandleTypeDef::Timeout.

Referenced by HAL_OSPI_Init().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO Manager configuration function

Functions
IO Manager configuration function
OSPI Exported Functions

OSPI IO Manager configuration function. More...

Functions

HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
Configure the OctoSPI IO manager.

Detailed Description

OSPI IO Manager configuration function.

 ===============================================================================
                  ##### IO Manager configuration function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Configure the IO manager.

Function Documentation

HAL_StatusTypeDef HAL_OSPIM_Config | ( | OSPI_HandleTypeDef * | hospi,
 |  | OSPIM_CfgTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the OctoSPI IO manager.

Parameters:
hospi | : OSPI handle
cfg | : Configuration of the IO Manager for the instance
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 2446 of file stm32h7xx_hal_ospi.c.

References assert_param, OSPIM_CfgTypeDef::ClkPort, OSPIM_CfgTypeDef::DQSPort, __OSPI_HandleTypeDef::ErrorCode, HAL_OSPI_ERROR_INVALID_PARAM, __OSPI_HandleTypeDef::Instance, OSPIM_CfgTypeDef::IOHighPort, OSPIM_CfgTypeDef::IOLowPort, and OSPIM_CfgTypeDef::NCSPort.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Exported Types

Data Structures | Typedefs | Enumerations
OSPI Exported Types
OSPI

Data Structures

struct | OSPI_InitTypeDef
OSPI Init structure definition. More...
struct | __OSPI_HandleTypeDef
HAL OSPI Handle Structure definition. More...
struct | OSPI_RegularCmdTypeDef
HAL OSPI Regular Command Structure definition. More...
struct | OSPI_HyperbusCfgTypeDef
HAL OSPI Hyperbus Configuration Structure definition. More...
struct | OSPI_HyperbusCmdTypeDef
HAL OSPI Hyperbus Command Structure definition. More...
struct | OSPI_AutoPollingTypeDef
HAL OSPI Auto Polling mode configuration structure definition. More...
struct | OSPI_MemoryMappedTypeDef
HAL OSPI Memory Mapped mode configuration structure definition. More...
struct | OSPIM_CfgTypeDef
HAL OSPI IO Manager Configuration structure definition. More...

Typedefs

typedef struct __OSPI_HandleTypeDef | OSPI_HandleTypeDef
HAL OSPI Handle Structure definition.
typedef void(* | pOSPI_CallbackTypeDef )(OSPI_HandleTypeDef *hospi)
HAL OSPI Callback pointer definition.

Enumerations

enum HAL_OSPI_CallbackIDTypeDef {
HAL_OSPI_ERROR_CB_ID = 0x00U, HAL_OSPI_ABORT_CB_ID = 0x01U, HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, HAL_OSPI_CMD_CPLT_CB_ID = 0x03U,
HAL_OSPI_RX_CPLT_CB_ID = 0x04U, HAL_OSPI_TX_CPLT_CB_ID = 0x05U, HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U,
HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, HAL_OSPI_TIMEOUT_CB_ID = 0x09U, HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU
}
HAL OSPI Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __OSPI_HandleTypeDef OSPI_HandleTypeDef

HAL OSPI Handle Structure definition.

typedef void(* pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi)

HAL OSPI Callback pointer definition.

Definition at line 288 of file stm32h7xx_hal_ospi.h.

Enumeration Type Documentation

enum HAL_OSPI_CallbackIDTypeDef

HAL OSPI Callback ID enumeration definition.

Enumerator:
HAL_OSPI_ERROR_CB_ID

OSPI Error Callback ID

HAL_OSPI_ABORT_CB_ID

OSPI Abort Callback ID

HAL_OSPI_FIFO_THRESHOLD_CB_ID

OSPI FIFO Threshold Callback ID

HAL_OSPI_CMD_CPLT_CB_ID

OSPI Command Complete Callback ID

HAL_OSPI_RX_CPLT_CB_ID

OSPI Rx Complete Callback ID

HAL_OSPI_TX_CPLT_CB_ID

OSPI Tx Complete Callback ID

HAL_OSPI_RX_HALF_CPLT_CB_ID

OSPI Rx Half Complete Callback ID

HAL_OSPI_TX_HALF_CPLT_CB_ID

OSPI Tx Half Complete Callback ID

HAL_OSPI_STATUS_MATCH_CB_ID

OSPI Status Match Callback ID

HAL_OSPI_TIMEOUT_CB_ID

OSPI Timeout Callback ID

HAL_OSPI_MSP_INIT_CB_ID

OSPI MspInit Callback ID

HAL_OSPI_MSP_DEINIT_CB_ID

OSPI MspDeInit Callback ID

Definition at line 268 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_InitTypeDef Struct Reference
OSPI Exported Types

OSPI Init structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | FifoThreshold
uint32_t | DualQuad
uint32_t | MemoryType
uint32_t | DeviceSize
uint32_t | ChipSelectHighTime
uint32_t | FreeRunningClock
uint32_t | ClockMode
uint32_t | WrapSize
uint32_t | ClockPrescaler
uint32_t | SampleShifting
uint32_t | DelayHoldQuarterCycle
uint32_t | ChipSelectBoundary
uint32_t | ClkChipSelectHighTime
uint32_t | DelayBlockBypass
uint32_t | MaxTran
uint32_t | Refresh

Detailed Description

OSPI Init structure definition.

Definition at line 49 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_InitTypeDef::ChipSelectBoundary

Definition at line 81 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::ChipSelectHighTime

Definition at line 64 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::ClkChipSelectHighTime

Definition at line 84 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::ClockMode

Definition at line 69 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::ClockPrescaler

Definition at line 73 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::DelayBlockBypass

Definition at line 87 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::DelayHoldQuarterCycle

Definition at line 79 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::DeviceSize

Definition at line 60 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::DualQuad

Definition at line 55 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), HAL_OSPI_Command_IT(), and HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::FifoThreshold

Definition at line 51 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), and HAL_OSPI_SetFifoThreshold().

uint32_t OSPI_InitTypeDef::FreeRunningClock

Definition at line 67 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::MaxTran

Definition at line 90 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::MemoryType

Definition at line 58 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Receive_IT().

uint32_t OSPI_InitTypeDef::Refresh

Definition at line 94 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::SampleShifting

Definition at line 76 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

uint32_t OSPI_InitTypeDef::WrapSize

Definition at line 71 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __OSPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__OSPI_HandleTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Handle Structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

OCTOSPI_TypeDef * | Instance
OSPI_InitTypeDef Init
uint8_t * | pBuffPtr
__IO uint32_t | XferSize
__IO uint32_t | XferCount
MDMA_HandleTypeDef * hmdma
__IO uint32_t | State
__IO uint32_t | ErrorCode
uint32_t | Timeout
void(* | ErrorCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | AbortCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | FifoThresholdCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | CmdCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | RxCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | TxCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | RxHalfCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | TxHalfCpltCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | StatusMatchCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | TimeOutCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | MspInitCallback )(struct __OSPI_HandleTypeDef *hospi)
void(* | MspDeInitCallback )(struct __OSPI_HandleTypeDef *hospi)

Detailed Description

HAL OSPI Handle Structure definition.

Definition at line 103 of file stm32h7xx_hal_ospi.h.

Field Documentation

void(* __OSPI_HandleTypeDef::AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 119 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 121 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::ErrorCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 118 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

__IO uint32_t __OSPI_HandleTypeDef::ErrorCode

Definition at line 115 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_GetError(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_RegisterCallback(), HAL_OSPI_SetFifoThreshold(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), HAL_OSPI_Transmit_IT(), HAL_OSPI_UnRegisterCallback(), and HAL_OSPIM_Config().

void(* __OSPI_HandleTypeDef::FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 120 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

MDMA_HandleTypeDef* __OSPI_HandleTypeDef::hmdma

Definition at line 113 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Transmit_DMA().

OSPI_InitTypeDef __OSPI_HandleTypeDef::Init

Definition at line 109 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), and HAL_OSPI_SetFifoThreshold().

OCTOSPI_TypeDef* __OSPI_HandleTypeDef::Instance

Definition at line 108 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_DeInit(), HAL_OSPI_GetFifoThreshold(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_SetFifoThreshold(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), HAL_OSPI_Transmit_IT(), and HAL_OSPIM_Config().

void(* __OSPI_HandleTypeDef::MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 130 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_DeInit(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::MspInitCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 129 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

uint8_t* __OSPI_HandleTypeDef::pBuffPtr

Definition at line 110 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

void(* __OSPI_HandleTypeDef::RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 122 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 124 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

__IO uint32_t __OSPI_HandleTypeDef::State

Definition at line 114 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_DeInit(), HAL_OSPI_GetState(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_RegisterCallback(), HAL_OSPI_SetFifoThreshold(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), HAL_OSPI_Transmit_IT(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 126 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

uint32_t __OSPI_HandleTypeDef::Timeout

Definition at line 116 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command_IT(), HAL_OSPI_Init(), HAL_OSPI_MemoryMapped(), and HAL_OSPI_SetTimeout().

void(* __OSPI_HandleTypeDef::TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 127 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 123 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

void(* __OSPI_HandleTypeDef::TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi)

Definition at line 125 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

__IO uint32_t __OSPI_HandleTypeDef::XferCount

Definition at line 112 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

__IO uint32_t __OSPI_HandleTypeDef::XferSize

Definition at line 111 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_RegularCmdTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_RegularCmdTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Regular Command Structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | OperationType
uint32_t | FlashId
uint32_t | Instruction
uint32_t | InstructionMode
uint32_t | InstructionSize
uint32_t | InstructionDtrMode
uint32_t | Address
uint32_t | AddressMode
uint32_t | AddressSize
uint32_t | AddressDtrMode
uint32_t | AlternateBytes
uint32_t | AlternateBytesMode
uint32_t | AlternateBytesSize
uint32_t | AlternateBytesDtrMode
uint32_t | DataMode
uint32_t | NbData
uint32_t | DataDtrMode
uint32_t | DummyCycles
uint32_t | DQSMode
uint32_t | SIOOMode

Detailed Description

HAL OSPI Regular Command Structure definition.

Definition at line 137 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_RegularCmdTypeDef::Address

Definition at line 154 of file stm32h7xx_hal_ospi.h.

uint32_t OSPI_RegularCmdTypeDef::AddressDtrMode

Definition at line 160 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::AddressMode

Definition at line 156 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::AddressSize

Definition at line 158 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::AlternateBytes

Definition at line 162 of file stm32h7xx_hal_ospi.h.

uint32_t OSPI_RegularCmdTypeDef::AlternateBytesDtrMode

Definition at line 168 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::AlternateBytesMode

Definition at line 164 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::AlternateBytesSize

Definition at line 166 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::DataDtrMode

Definition at line 175 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::DataMode

Definition at line 170 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::DQSMode

Definition at line 179 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::DummyCycles

Definition at line 177 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::FlashId

Definition at line 143 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::Instruction

Definition at line 146 of file stm32h7xx_hal_ospi.h.

uint32_t OSPI_RegularCmdTypeDef::InstructionDtrMode

Definition at line 152 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::InstructionMode

Definition at line 148 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::InstructionSize

Definition at line 150 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::NbData

Definition at line 172 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::OperationType

Definition at line 139 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

uint32_t OSPI_RegularCmdTypeDef::SIOOMode

Definition at line 181 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_HyperbusCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_HyperbusCfgTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Hyperbus Configuration Structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | RWRecoveryTime
uint32_t | AccessTime
uint32_t | WriteZeroLatency
uint32_t | LatencyMode

Detailed Description

HAL OSPI Hyperbus Configuration Structure definition.

Definition at line 188 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_HyperbusCfgTypeDef::AccessTime

Definition at line 192 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCfg().

uint32_t OSPI_HyperbusCfgTypeDef::LatencyMode

Definition at line 196 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCfg().

uint32_t OSPI_HyperbusCfgTypeDef::RWRecoveryTime

Definition at line 190 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCfg().

uint32_t OSPI_HyperbusCfgTypeDef::WriteZeroLatency

Definition at line 194 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCfg().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_HyperbusCmdTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_HyperbusCmdTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Hyperbus Command Structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | AddressSpace
uint32_t | Address
uint32_t | AddressSize
uint32_t | NbData
uint32_t | DQSMode

Detailed Description

HAL OSPI Hyperbus Command Structure definition.

Definition at line 203 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_HyperbusCmdTypeDef::Address

Definition at line 207 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCmd().

uint32_t OSPI_HyperbusCmdTypeDef::AddressSize

Definition at line 209 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCmd().

uint32_t OSPI_HyperbusCmdTypeDef::AddressSpace

Definition at line 205 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCmd().

uint32_t OSPI_HyperbusCmdTypeDef::DQSMode

Definition at line 215 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCmd().

uint32_t OSPI_HyperbusCmdTypeDef::NbData

Definition at line 211 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCmd().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_AutoPollingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_AutoPollingTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Auto Polling mode configuration structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | Match
uint32_t | Mask
uint32_t | MatchMode
uint32_t | AutomaticStop
uint32_t | Interval

Detailed Description

HAL OSPI Auto Polling mode configuration structure definition.

Definition at line 222 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_AutoPollingTypeDef::AutomaticStop

Definition at line 230 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), and HAL_OSPI_AutoPolling_IT().

uint32_t OSPI_AutoPollingTypeDef::Interval

Definition at line 232 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), and HAL_OSPI_AutoPolling_IT().

uint32_t OSPI_AutoPollingTypeDef::Mask

Definition at line 226 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), and HAL_OSPI_AutoPolling_IT().

uint32_t OSPI_AutoPollingTypeDef::Match

Definition at line 224 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), and HAL_OSPI_AutoPolling_IT().

uint32_t OSPI_AutoPollingTypeDef::MatchMode

Definition at line 228 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), and HAL_OSPI_AutoPolling_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI_MemoryMappedTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPI_MemoryMappedTypeDef Struct Reference
OSPI Exported Types

HAL OSPI Memory Mapped mode configuration structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | TimeOutActivation
uint32_t | TimeOutPeriod

Detailed Description

HAL OSPI Memory Mapped mode configuration structure definition.

Definition at line 239 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPI_MemoryMappedTypeDef::TimeOutActivation

Definition at line 241 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_MemoryMapped().

uint32_t OSPI_MemoryMappedTypeDef::TimeOutPeriod

Definition at line 243 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_MemoryMapped().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPIM_CfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OSPIM_CfgTypeDef Struct Reference
OSPI Exported Types

HAL OSPI IO Manager Configuration structure definition. More...

#include <stm32h7xx_hal_ospi.h>

Data Fields

uint32_t | ClkPort
uint32_t | DQSPort
uint32_t | NCSPort
uint32_t | IOLowPort
uint32_t | IOHighPort

Detailed Description

HAL OSPI IO Manager Configuration structure definition.

Definition at line 250 of file stm32h7xx_hal_ospi.h.

Field Documentation

uint32_t OSPIM_CfgTypeDef::ClkPort

Definition at line 252 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPIM_Config().

uint32_t OSPIM_CfgTypeDef::DQSPort

Definition at line 254 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPIM_Config().

uint32_t OSPIM_CfgTypeDef::IOHighPort

Definition at line 260 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPIM_Config().

uint32_t OSPIM_CfgTypeDef::IOLowPort

Definition at line 258 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPIM_Config().

uint32_t OSPIM_CfgTypeDef::NCSPort

Definition at line 256 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPIM_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI State

Defines
OSPI State
OSPI Exported Constants

Defines

#define | HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U)
#define | HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U)
#define | HAL_OSPI_STATE_READY ((uint32_t)0x00000002U)
#define | HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U)
#define | HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U)
#define | HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U)
#define | HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U)
#define | HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U)
#define | HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U)
#define | HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U)
#define | HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U)
#define | HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U)
#define | HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U)

Define Documentation

#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U)

Abort on-going

Definition at line 313 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), and HAL_OSPI_IRQHandler().

#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U)

Auto-polling on-going

Definition at line 311 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling_IT().

#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U)

Command without data on-going

Definition at line 308 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command_IT(), and HAL_OSPI_IRQHandler().

#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U)

Memory-mapped on-going

Definition at line 312 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_MemoryMapped().

#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U)

Indirect Rx on-going

Definition at line 310 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Receive_IT().

#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U)

Indirect Tx on-going

Definition at line 309 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U)

Command (regular or hyperbus) configured, ready for an action

Definition at line 305 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U)

Blocking error, driver should be re-initialized

Definition at line 314 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U)

Initialization done in hyperbus mode but timing configuration not done

Definition at line 303 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_HyperbusCfg(), and HAL_OSPI_Init().

#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U)

Read command configuration done, not the write command configuration

Definition at line 306 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command().

#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U)

Driver ready to be used

Definition at line 304 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_RegisterCallback(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_UnRegisterCallback().

#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U)

Initial state

Definition at line 302 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_DeInit(), HAL_OSPI_Init(), HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U)

Write command configuration done, not the read command configuration

Definition at line 307 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Error Code

Defines
OSPI Error Code
OSPI Exported Constants

Defines

#define | HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
#define | HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
#define | HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U)
#define | HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Define Documentation

#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U)

DMA transfer error

Definition at line 325 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Transmit_DMA().

#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Invalid callback error

Definition at line 329 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_RegisterCallback(), and HAL_OSPI_UnRegisterCallback().

#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)

Invalid parameters error

Definition at line 326 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), HAL_OSPI_Transmit_IT(), and HAL_OSPIM_Config().

#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U)

Sequence of the state machine is incorrect

Definition at line 327 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_SetFifoThreshold(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 322 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_Init(), and HAL_OSPI_IRQHandler().

#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 323 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)

Transfer error

Definition at line 324 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Dual-Quad

Defines
OSPI Dual-Quad
OSPI Exported Constants

Defines

#define | HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM)

Define Documentation

#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U)

Dual-Quad mode disabled

Definition at line 338 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM)

Dual-Quad mode enabled

Definition at line 339 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Memory Type

Defines
OSPI Memory Type
OSPI Exported Constants

Defines

#define | HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U)
#define | HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0)
#define | HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1)
#define | HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))
#define | HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2)

Define Documentation

#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1)

AP Memory mode

Definition at line 349 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2)

Hyperbus mode

Definition at line 351 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Receive_IT().

#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0)

Macronix mode

Definition at line 348 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))

Macronix RAM mode

Definition at line 350 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U)

Micron mode

Definition at line 347 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Free Running Clock

Defines
OSPI Free Running Clock
OSPI Exported Constants

Defines

#define | HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK)

Define Documentation

#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U)

CLK is not free running

Definition at line 359 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK)

CLK is free running (always provided)

Definition at line 360 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Clock Mode

Defines
OSPI Clock Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)
#define | HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE)

Define Documentation

#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)

CLK must stay low while nCS is high

Definition at line 368 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE)

CLK must stay high while nCS is high

Definition at line 369 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Wrap-Size

Defines
OSPI Wrap-Size
OSPI Exported Constants

Defines

#define | HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U)
#define | HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)
#define | HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1))
#define | HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)
#define | HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2))

Define Documentation

#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2))

external memory supports wrap size of 128 bytes

Definition at line 381 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)

external memory supports wrap size of 16 bytes

Definition at line 378 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1))

external memory supports wrap size of 32 bytes

Definition at line 379 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)

external memory supports wrap size of 64 bytes

Definition at line 380 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U)

wrapped reads are not supported by the memory

Definition at line 377 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Sample Shifting

Defines
OSPI Sample Shifting
OSPI Exported Constants

Defines

#define | HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT)

Define Documentation

#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT)

1/2 cycle shift

Definition at line 390 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)

No shift

Definition at line 389 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Delay Hold Quarter Cycle

Defines
OSPI Delay Hold Quarter Cycle
OSPI Exported Constants

Defines

#define | HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC)

Define Documentation

#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U)

No Delay

Definition at line 398 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC)

Delay Hold 1/4 cycle

Definition at line 399 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Delay Block Bypaas

Defines
OSPI Delay Block Bypaas
OSPI Exported Constants

Defines

#define | HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U)
#define | HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP)

Define Documentation

#define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP)

Delay block is bypassed

Definition at line 408 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U)

Sampling clock is delayed by the delay block

Definition at line 407 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Operation Type

Defines
OSPI Operation Type
OSPI Exported Constants

Defines

#define | HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U)
#define | HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U)
#define | HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U)
#define | HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U)

Define Documentation

#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U)

Common configuration (indirect or auto-polling mode)

Definition at line 416 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U)

Read configuration (memory-mapped mode)

Definition at line 417 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command().

#define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U)

Wrap configuration (memory-mapped mode)

Definition at line 419 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command().

#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U)

Write configuration (memory-mapped mode)

Definition at line 418 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Flash Id

Defines
OSPI Flash Id
OSPI Exported Constants

Defines

#define | HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
#define | HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL)

Define Documentation

#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U)

FLASH 1 selected

Definition at line 427 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL)

FLASH 2 selected

Definition at line 428 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Instruction Mode

Defines
OSPI Instruction Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0)
#define | HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1)
#define | HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))
#define | HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2)

Define Documentation

#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0)

Instruction on a single line

Definition at line 437 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1)

Instruction on two lines

Definition at line 438 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))

Instruction on four lines

Definition at line 439 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2)

Instruction on eight lines

Definition at line 440 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)

No instruction

Definition at line 436 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Instruction Size

Defines
OSPI Instruction Size
OSPI Exported Constants

Defines

#define | HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0)
#define | HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1)
#define | HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE)

Define Documentation

#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0)

16-bit instruction

Definition at line 449 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1)

24-bit instruction

Definition at line 450 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE)

32-bit instruction

Definition at line 451 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U)

8-bit instruction

Definition at line 448 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Instruction DTR Mode

Defines
OSPI Instruction DTR Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR)

Define Documentation

#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U)

DTR mode disabled for instruction phase

Definition at line 459 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR)

DTR mode enabled for instruction phase

Definition at line 460 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Address Mode

Defines
OSPI Address Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0)
#define | HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1)
#define | HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))
#define | HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2)

Define Documentation

#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0)

Address on a single line

Definition at line 469 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1)

Address on two lines

Definition at line 470 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))

Address on four lines

Definition at line 471 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2)

Address on eight lines

Definition at line 472 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U)

No address

Definition at line 468 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), and HAL_OSPI_Receive_IT().

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STM32H7B3xQ HAL User Manual: OSPI Address Size

Defines
OSPI Address Size
OSPI Exported Constants

Defines

#define | HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0)
#define | HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1)
#define | HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE)

Define Documentation

#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0)

16-bit address

Definition at line 481 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1)

24-bit address

Definition at line 482 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE)

32-bit address

Definition at line 483 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)

8-bit address

Definition at line 480 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Address DTR Mode

Defines
OSPI Address DTR Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR)

Define Documentation

#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U)

DTR mode disabled for address phase

Definition at line 491 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR)

DTR mode enabled for address phase

Definition at line 492 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Alternate Bytes Mode

Defines
OSPI Alternate Bytes Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0)
#define | HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1)
#define | HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))
#define | HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2)

Define Documentation

#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0)

Alternate bytes on a single line

Definition at line 501 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1)

Alternate bytes on two lines

Definition at line 502 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))

Alternate bytes on four lines

Definition at line 503 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2)

Alternate bytes on eight lines

Definition at line 504 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)

No alternate bytes

Definition at line 500 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

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STM32H7B3xQ HAL User Manual: OSPI Alternate Bytes Size

Defines
OSPI Alternate Bytes Size
OSPI Exported Constants

Defines

#define | HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0)
#define | HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1)
#define | HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE)

Define Documentation

#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0)

16-bit alternate bytes

Definition at line 513 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1)

24-bit alternate bytes

Definition at line 514 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE)

32-bit alternate bytes

Definition at line 515 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)

8-bit alternate bytes

Definition at line 512 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Alternate Bytes DTR Mode

Defines
OSPI Alternate Bytes DTR Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR)

Define Documentation

#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)

DTR mode disabled for alternate bytes phase

Definition at line 523 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR)

DTR mode enabled for alternate bytes phase

Definition at line 524 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Data Mode

Defines
OSPI Data Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0)
#define | HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1)
#define | HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))
#define | HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2)

Define Documentation

#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0)

Data on a single line

Definition at line 533 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1)

Data on two lines

Definition at line 534 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))

Data on four lines

Definition at line 535 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2)

Data on eight lines

Definition at line 536 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U)

No data

Definition at line 532 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Command(), and HAL_OSPI_Command_IT().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Data DTR Mode

Defines
OSPI Data DTR Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR)

Define Documentation

#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U)

DTR mode disabled for data phase

Definition at line 544 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR)

DTR mode enabled for data phase

Definition at line 545 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI DQS Mode

Defines
OSPI DQS Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE)

Define Documentation

#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U)

DQS disabled

Definition at line 553 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE)

DQS enabled

Definition at line 554 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI SIOO Mode

Defines
OSPI SIOO Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)
#define | HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO)

Define Documentation

#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)

Send instruction on every transaction

Definition at line 562 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO)

Send instruction only for the first command

Definition at line 563 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Hyperbus Write Zero Latency Activation

Defines
OSPI Hyperbus Write Zero Latency Activation
OSPI Exported Constants

Defines

#define | HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U)
#define | HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL)

Define Documentation

#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U)

Latency on write accesses

Definition at line 571 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL)

No latency on write accesses

Definition at line 572 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Hyperbus Latency Mode

Defines
OSPI Hyperbus Latency Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U)
#define | HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM)

Define Documentation

#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM)

Fixed latency

Definition at line 581 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U)

Variable initial latency

Definition at line 580 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Hyperbus Address Space

Defines
OSPI Hyperbus Address Space
OSPI Exported Constants

Defines

#define | HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U)
#define | HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0)

Define Documentation

#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U)

HyperBus memory mode

Definition at line 589 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0)

HyperBus register mode

Definition at line 590 of file stm32h7xx_hal_ospi.h.

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STM32H7B3xQ HAL User Manual: OSPI Match Mode

Defines
OSPI Match Mode
OSPI Exported Constants

Defines

#define | HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)
#define | HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM)

Define Documentation

#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)

AND match mode between unmasked bits

Definition at line 598 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM)

OR match mode between unmasked bits

Definition at line 599 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Automatic Stop

Defines
OSPI Automatic Stop
OSPI Exported Constants

Defines

#define | HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS)

Define Documentation

#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)

AutoPolling stops only with abort or OSPI disabling

Definition at line 607 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS)

AutoPolling stops as soon as there is a match

Definition at line 608 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Timeout Activation

Defines
OSPI Timeout Activation
OSPI Exported Constants

Defines

#define | HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN)

Define Documentation

#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)

Timeout counter disabled, nCS remains active

Definition at line 616 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN)

Timeout counter enabled, nCS released when timeout expires

Definition at line 617 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_MemoryMapped().

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STM32H7B3xQ HAL User Manual: OSPI Flags

Defines
OSPI Flags
OSPI Exported Constants

Defines

#define | HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY
#define | HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF
#define | HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF
#define | HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF
#define | HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF
#define | HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF

Define Documentation

#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY

Busy flag: operation is ongoing

Definition at line 625 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), and HAL_OSPI_MemoryMapped().

#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF

Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete

Definition at line 628 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), HAL_OSPI_Receive(), and HAL_OSPI_Transmit().

#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF

Status match flag: received data matches in autopolling mode

Definition at line 627 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), and HAL_OSPI_IRQHandler().

#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF

Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted

Definition at line 629 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF

Transfer error flag: invalid address is being accessed

Definition at line 630 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF

Timeout flag: timeout occurs in memory-mapped mode

Definition at line 626 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_IRQHandler(), and HAL_OSPI_MemoryMapped().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Interrupts

Defines
OSPI Interrupts
OSPI Exported Constants

Defines

#define | HAL_OSPI_IT_TO OCTOSPI_CR_TOIE
#define | HAL_OSPI_IT_SM OCTOSPI_CR_SMIE
#define | HAL_OSPI_IT_FT OCTOSPI_CR_FTIE
#define | HAL_OSPI_IT_TC OCTOSPI_CR_TCIE
#define | HAL_OSPI_IT_TE OCTOSPI_CR_TEIE

Define Documentation

#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE

Interrupt on the fifo threshold flag

Definition at line 640 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_IT(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE

Interrupt on the status match flag

Definition at line 639 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling_IT(), and HAL_OSPI_IRQHandler().

#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE

Interrupt on the transfer complete flag

Definition at line 641 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_Command_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_IT(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE

Interrupt on the transfer error flag

Definition at line 642 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command_IT(), HAL_OSPI_IRQHandler(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE

Interrupt on the timeout flag

Definition at line 638 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_IRQHandler(), and HAL_OSPI_MemoryMapped().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Timeout definition

Defines
OSPI Timeout definition
OSPI Exported Constants

Defines

#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */

Define Documentation

#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */

Definition at line 650 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI IO Manager IO Port

Defines
OSPI IO Manager IO Port
OSPI Exported Constants

Defines

#define | HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))
#define | HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))
#define | HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))
#define | HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))
#define | HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))
#define | HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))
#define | HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))
#define | HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))
#define | HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))
#define | HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))
#define | HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))
#define | HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))
#define | HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))
#define | HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))
#define | HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))
#define | HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))

Define Documentation

#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))

Port 1 - IO[7:4]

Definition at line 659 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))

Port 1 - IO[3:0]

Definition at line 658 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))

Port 2 - IO[7:4]

Definition at line 661 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))

Port 2 - IO[3:0]

Definition at line 660 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))

Port 3 - IO[7:4]

Definition at line 663 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))

Port 3 - IO[3:0]

Definition at line 662 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))

Port 4 - IO[7:4]

Definition at line 665 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))

Port 4 - IO[3:0]

Definition at line 664 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))

Port 5 - IO[7:4]

Definition at line 667 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))

Port 5 - IO[3:0]

Definition at line 666 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))

Port 6 - IO[7:4]

Definition at line 669 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))

Port 6 - IO[3:0]

Definition at line 668 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))

Port 7 - IO[7:4]

Definition at line 671 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))

Port 7 - IO[3:0]

Definition at line 670 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))

Port 8 - IO[7:4]

Definition at line 673 of file stm32h7xx_hal_ospi.h.

#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))

Port 8 - IO[3:0]

Definition at line 672 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSPI Exported Macros

Defines
OSPI Exported Macros
OSPI

Defines

#define | __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)
Reset OSPI handle state.
#define | __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
Enable the OSPI peripheral.
#define | __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
Disable the OSPI peripheral.
#define | __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified OSPI interrupt.
#define | __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified OSPI interrupt.
#define | __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified OSPI interrupt source is enabled or not.
#define | __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
Check whether the selected OSPI flag is set or not.
#define | __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified OSPI's flag status.

Define Documentation

#define __HAL_OSPI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

Clears the specified OSPI's flag status.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
__FLAG__,: specifies the OSPI clear register flag that needs to be set This parameter can be one of the following values:
  • HAL_OSPI_FLAG_TO: OSPI Timeout flag
  • HAL_OSPI_FLAG_SM: OSPI Status match flag
  • HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
  • HAL_OSPI_FLAG_TE: OSPI Transfer error flag
Return values:
None

Definition at line 776 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define __HAL_OSPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)

Disable the OSPI peripheral.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
Return values:
None

Definition at line 709 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_DeInit().

#define __HAL_OSPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Disable the specified OSPI interrupt.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
__INTERRUPT__,: specifies the OSPI interrupt source to disable. This parameter can be one of the following values:
  • HAL_OSPI_IT_TO: OSPI Timeout interrupt
  • HAL_OSPI_IT_SM: OSPI Status match interrupt
  • HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
  • HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
  • HAL_OSPI_IT_TE: OSPI Transfer error interrupt
Return values:
None

Definition at line 736 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), and HAL_OSPI_IRQHandler().

#define __HAL_OSPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)

Enable the OSPI peripheral.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
Return values:
None

Definition at line 703 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Init().

#define __HAL_OSPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Enable the specified OSPI interrupt.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
__INTERRUPT__,: specifies the OSPI interrupt source to enable. This parameter can be one of the following values:
  • HAL_OSPI_IT_TO: OSPI Timeout interrupt
  • HAL_OSPI_IT_SM: OSPI Status match interrupt
  • HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
  • HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
  • HAL_OSPI_IT_TE: OSPI Transfer error interrupt
Return values:
None

Definition at line 722 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort_IT(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command_IT(), HAL_OSPI_MemoryMapped(), HAL_OSPI_Receive_DMA(), HAL_OSPI_Receive_IT(), HAL_OSPI_Transmit_DMA(), and HAL_OSPI_Transmit_IT().

#define __HAL_OSPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)

Check whether the selected OSPI flag is set or not.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
__FLAG__,: specifies the OSPI flag to check. This parameter can be one of the following values:
  • HAL_OSPI_FLAG_BUSY: OSPI Busy flag
  • HAL_OSPI_FLAG_TO: OSPI Timeout flag
  • HAL_OSPI_FLAG_SM: OSPI Status match flag
  • HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag
  • HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
  • HAL_OSPI_FLAG_TE: OSPI Transfer error flag
Return values:
None

Definition at line 764 of file stm32h7xx_hal_ospi.h.

Referenced by HAL_OSPI_Abort(), and HAL_OSPI_Abort_IT().

#define __HAL_OSPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified OSPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the OSPI Handle.
__INTERRUPT__,: specifies the OSPI interrupt source to check. This parameter can be one of the following values:
  • HAL_OSPI_IT_TO: OSPI Timeout interrupt
  • HAL_OSPI_IT_SM: OSPI Status match interrupt
  • HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
  • HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
  • HAL_OSPI_IT_TE: OSPI Transfer error interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 749 of file stm32h7xx_hal_ospi.h.

#define __HAL_OSPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                              \
                                                                  (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                               } while(0)

Reset OSPI handle state.

Parameters:
__HANDLE__,: OSPI handle.
Return values:
None

Definition at line 690 of file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OTFDEC_Exported_Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OTFDEC_Init (OTFDEC_HandleTypeDef *hotfdec)
Initialize the OTFDEC peripheral and create the associated handle.
HAL_StatusTypeDef | HAL_OTFDEC_DeInit (OTFDEC_HandleTypeDef *hotfdec)
DeInitialize the OTFDEC peripheral.
__weak void | HAL_OTFDEC_MspInit (OTFDEC_HandleTypeDef *hotfdec)
Initialize the OTFDEC MSP.
__weak void | HAL_OTFDEC_MspDeInit (OTFDEC_HandleTypeDef *hotfdec)
DeInitialize OTFDEC MSP.
HAL_StatusTypeDef | HAL_OTFDEC_RegisterCallback (OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback)
Register a User OTFDEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_OTFDEC_UnRegisterCallback (OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
Unregister a OTFDEC Callback OTFDEC callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================

Function Documentation

HAL_StatusTypeDef HAL_OTFDEC_DeInit ( OTFDEC_HandleTypeDef * hotfdec )

DeInitialize the OTFDEC peripheral.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
HAL status

Definition at line 222 of file stm32h7xx_hal_otfdec.c.

References assert_param, and HAL_OTFDEC_MspDeInit().

HAL_StatusTypeDef HAL_OTFDEC_Init ( OTFDEC_HandleTypeDef * hotfdec )

Initialize the OTFDEC peripheral and create the associated handle.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
HAL status

Definition at line 176 of file stm32h7xx_hal_otfdec.c.

References assert_param, HAL_OTFDEC_ErrorCallback(), and HAL_OTFDEC_MspInit().

__weak void HAL_OTFDEC_MspDeInit ( OTFDEC_HandleTypeDef * hotfdec )

DeInitialize OTFDEC MSP.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
None

Definition at line 284 of file stm32h7xx_hal_otfdec.c.

Referenced by HAL_OTFDEC_DeInit(), and HAL_OTFDEC_UnRegisterCallback().

__weak void HAL_OTFDEC_MspInit ( OTFDEC_HandleTypeDef * hotfdec )

Initialize the OTFDEC MSP.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
None

Definition at line 268 of file stm32h7xx_hal_otfdec.c.

Referenced by HAL_OTFDEC_Init(), and HAL_OTFDEC_UnRegisterCallback().

HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | HAL_OTFDEC_CallbackIDTypeDef | CallbackID,
 |  | pOTFDEC_CallbackTypeDef | pCallback
 | ) |  |

Register a User OTFDEC Callback To be used instead of the weak predefined callback.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
  • HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 308 of file stm32h7xx_hal_otfdec.c.

HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | HAL_OTFDEC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a OTFDEC Callback OTFDEC callback is redirected to the weak predefined callback.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
  • HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 390 of file stm32h7xx_hal_otfdec.c.

References HAL_OTFDEC_ErrorCallback(), HAL_OTFDEC_MspDeInit(), and HAL_OTFDEC_MspInit().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OTFDEC IRQ handler management

Functions
OTFDEC IRQ handler management
OTFDEC_Exported_Functions

OTFDEC IRQ handler. More...

Functions

void | HAL_OTFDEC_IRQHandler (OTFDEC_HandleTypeDef *hotfdec)
Handle OTFDEC interrupt request.
__weak void | HAL_OTFDEC_ErrorCallback (OTFDEC_HandleTypeDef *hotfdec)
OTFDEC error callback.

Detailed Description

OTFDEC IRQ handler.

  ==============================================================================
                ##### OTFDEC IRQ handler management #####
  ==============================================================================
[..]  This section provides OTFDEC IRQ handler function.

Function Documentation

__weak void HAL_OTFDEC_ErrorCallback ( OTFDEC_HandleTypeDef * hotfdec )

OTFDEC error callback.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
None

Definition at line 511 of file stm32h7xx_hal_otfdec.c.

Referenced by HAL_OTFDEC_Init(), HAL_OTFDEC_IRQHandler(), and HAL_OTFDEC_UnRegisterCallback().

void HAL_OTFDEC_IRQHandler ( OTFDEC_HandleTypeDef * hotfdec )

Handle OTFDEC interrupt request.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
None

Definition at line 477 of file stm32h7xx_hal_otfdec.c.

References HAL_OTFDEC_ErrorCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OTFDEC_Exported_Functions

Peripheral control functions. More...

Functions

HAL_StatusTypeDef | HAL_OTFDEC_RegionKeyLock (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Lock region keys.
HAL_StatusTypeDef | HAL_OTFDEC_RegionSetKey (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
Set region keys.
HAL_StatusTypeDef | HAL_OTFDEC_RegionSetMode (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
Set region mode.
HAL_StatusTypeDef | HAL_OTFDEC_RegionConfig (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
Set region configuration.
uint32_t | HAL_OTFDEC_KeyCRCComputation (uint32_t *pKey)
Compute Key CRC.
HAL_StatusTypeDef | HAL_OTFDEC_RegionEnable (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Enable region deciphering.
HAL_StatusTypeDef | HAL_OTFDEC_RegionDisable (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Disable region deciphering.

Detailed Description

Peripheral control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
    This subsection permits to configure the OTFDEC peripheral

Function Documentation

uint32_t HAL_OTFDEC_KeyCRCComputation ( uint32_t * pKey )

Compute Key CRC.

Parameters:
pKey pointer at set of keys
Return values:
CRC value

Definition at line 751 of file stm32h7xx_hal_otfdec.c.

Referenced by HAL_OTFDEC_RegionSetKey().

HAL_StatusTypeDef HAL_OTFDEC_RegionConfig | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex,
 |  | OTFDEC_RegionConfigTypeDef * | Config,
 |  | uint32_t | lock
 | ) |  |

Set region configuration.

Note:
Region deciphering is enabled at the end of this function
Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region that is configured
Config | pointer on structure containing the region configuration parameters
lock configuration lock enable or disable parameter This parameter can be one of the following values:
  • OTFDEC_REG_CONFIGR_LOCK_DISABLE OTFDEC region configuration is not locked
  • OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked
Return values:
HAL state

Definition at line 692 of file stm32h7xx_hal_otfdec.c.

References assert_param.

HAL_StatusTypeDef HAL_OTFDEC_RegionDisable | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex
 | ) |  |

Disable region deciphering.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the deciphering is disabled
Note:
An error is reported when the configuration is locked.
Return values:
HAL state

Definition at line 840 of file stm32h7xx_hal_otfdec.c.

References assert_param.

HAL_StatusTypeDef HAL_OTFDEC_RegionEnable | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex
 | ) |  |

Enable region deciphering.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the deciphering is enabled
Note:
An error is reported when the configuration is locked.
Return values:
HAL state

Definition at line 799 of file stm32h7xx_hal_otfdec.c.

References assert_param.

HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex
 | ) |  |

Lock region keys.

Note:
Writes to this region KEYRx registers are ignored until next OTFDEC reset.
Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the keys of which are locked
Return values:
HAL state

Definition at line 550 of file stm32h7xx_hal_otfdec.c.

References assert_param.

HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex,
 |  | uint32_t * | pKey
 | ) |  |

Set region keys.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the keys of which are set
pKey | pointer at set of keys
Note:
The API reads the key CRC computed by the peripheral and compares it with thzt theoretically expected. An error is reported if they are different.
Return values:
HAL state

Definition at line 584 of file stm32h7xx_hal_otfdec.c.

References assert_param, HAL_OTFDEC_KeyCRCComputation(), and HAL_OTFDEC_RegionGetKeyCRC().

HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex,
 |  | uint32_t | mode
 | ) |  |

Set region mode.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the mode of which is set
mode This parameter can be only:
  • OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY Only instruction accesses are decrypted
  • OTFDEC_REG_MODE_DATA_ACCESSES_ONLY Only data accesses are decrypted
  • OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES All read accesses are decrypted (instruction or data)
  • OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated
Return values:
HAL state

Definition at line 653 of file stm32h7xx_hal_otfdec.c.

References assert_param.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Status functions

Functions
Peripheral State and Status functions
OTFDEC_Exported_Functions

Peripheral State functions. More...

Functions

HAL_OTFDEC_StateTypeDef | HAL_OTFDEC_GetState (OTFDEC_HandleTypeDef *hotfdec)
Return the OTFDEC state.
uint32_t | HAL_OTFDEC_RegionGetKeyCRC (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Return region keys CRC.
HAL_StatusTypeDef | HAL_OTFDEC_RegionGetConfig (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config)
Return region configuration parameters.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState ( OTFDEC_HandleTypeDef * hotfdec )

Return the OTFDEC state.

Parameters:
hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
Return values:
HAL state

Definition at line 897 of file stm32h7xx_hal_otfdec.c.

HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex,
 |  | OTFDEC_RegionConfigTypeDef * | Config
 | ) |  |

Return region configuration parameters.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the configuration of which is read
Config | pointer on structure that will be filled up with the region configuration parameters
Return values:
HAL state

Definition at line 938 of file stm32h7xx_hal_otfdec.c.

References assert_param.

uint32_t HAL_OTFDEC_RegionGetKeyCRC | ( | OTFDEC_HandleTypeDef * | hotfdec,
 |  | uint32_t | RegionIndex
 | ) |  |

Return region keys CRC.

Parameters:
hotfdec | pointer to an OTFDEC_HandleTypeDef structure that contains the configuration information for OTFDEC module
RegionIndex | index of region the keys CRC of which is read
Return values:
Key CRC

Definition at line 910 of file stm32h7xx_hal_otfdec.c.

References assert_param.

Referenced by HAL_OTFDEC_RegionSetKey().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Define Documentation

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 81 of file stm32h7xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 80 of file stm32h7xx_hal_pcd.c.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef | PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.
static HAL_StatusTypeDef | PCD_EP_OutXfrComplete_int (PCD_HandleTypeDef *hpcd, uint32_t epnum)
process EP OUT transfer complete interrupt.
static HAL_StatusTypeDef | PCD_EP_OutSetupPacket_int (PCD_HandleTypeDef *hpcd, uint32_t epnum)
process EP OUT setup packet received interrupt.

Function Documentation

static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

process EP OUT setup packet received interrupt.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
HAL status

Definition at line 2157 of file stm32h7xx_hal_pcd.c.

References HAL_PCD_SetupStageCallback(), __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::Setup, and __PCD_HandleTypeDef::SetupStageCallback.

Referenced by HAL_PCD_IRQHandler().

static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

process EP OUT transfer complete interrupt.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
HAL status

Definition at line 2052 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, HAL_PCD_DataOutStageCallback(), __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, and __PCD_HandleTypeDef::Setup.

Referenced by HAL_PCD_IRQHandler().

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

Check FIFO for the next packet to be loaded.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
HAL status

Definition at line 1992 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_IRQHandler().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL USB OTG PCD Callback ID enumeration definition

Enumerations
HAL USB OTG PCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback ID enumeration definition. More...

Enumerations

enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Detailed Description

HAL USB OTG PCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_PCD_CallbackIDTypeDef
Enumerator:
HAL_PCD_SOF_CB_ID

USB PCD SOF callback ID

HAL_PCD_SETUPSTAGE_CB_ID

USB PCD Setup Stage callback ID

HAL_PCD_RESET_CB_ID

USB PCD Reset callback ID

HAL_PCD_SUSPEND_CB_ID

USB PCD Suspend callback ID

HAL_PCD_RESUME_CB_ID

USB PCD Resume callback ID

HAL_PCD_CONNECT_CB_ID

USB PCD Connect callback ID

HAL_PCD_DISCONNECT_CB_ID

USB PCD Disconnect callback ID

HAL_PCD_MSPINIT_CB_ID

USB PCD MspInit callback ID

HAL_PCD_MSPDEINIT_CB_ID

USB PCD MspDeInit callback ID

Definition at line 239 of file stm32h7xx_hal_pcd.h.

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STM32H7B3xQ HAL User Manual: HAL USB OTG PCD Callback pointer definition

Typedefs
HAL USB OTG PCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback pointer definition. More...

Typedefs

typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Detailed Description

HAL USB OTG PCD Callback pointer definition.

Typedef Documentation

typedef void(* pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

pointer to USB OTG PCD BCD callback

Definition at line 268 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd)

pointer to a common USB OTG PCD callback function

Definition at line 262 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data IN Stage callback

Definition at line 264 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data OUT Stage callback

Definition at line 263 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO IN Incomplete callback

Definition at line 266 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO OUT Incomplete callback

Definition at line 265 of file stm32h7xx_hal_pcd.h.

typedef void(* pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

pointer to USB OTG PCD LPM callback

Definition at line 267 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG PCD Callback ID enumeration definition

HAL USB OTG PCD Callback ID enumeration definition.

HAL USB OTG PCD Callback pointer definition

HAL USB OTG PCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 244 of file stm32h7xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), __PCD_HandleTypeDef::MspDeInitCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 123 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::DisconnectCallback, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_MspInit(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_ERROR, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SuspendCallback(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::ISOINIncompleteCallback, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, __PCD_HandleTypeDef::Lock, __PCD_HandleTypeDef::LPMCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::OUT_ep, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, __PCD_HandleTypeDef::SuspendCallback, and __PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 295 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 280 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_BcdCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD BCD Callback function
Return values:
HAL status

Definition at line 826 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID,
 |  | pPCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB PCD Callback To be used instead of the weak predefined callback.

Parameters:
hpcd | USB PCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 324 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_RESUME_CB_ID, HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SOF_CB_ID, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataInStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data IN Stage Callback function
Return values:
HAL status

Definition at line 607 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataOutStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data OUT Stage Callback function
Return values:
HAL status

Definition at line 534 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoInIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso IN incomplete Callback function
Return values:
HAL status

Definition at line 753 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoOutIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso OUT incomplete Callback function
Return values:
HAL status

Definition at line 680 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_LpmCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD LPM Callback function
Return values:
HAL status

Definition at line 899 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 866 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_BCD_Callback(), and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.

Parameters:
hpcd USB PCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 435 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_ConnectCallback(), HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_DisconnectCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MspDeInit(), HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MspInit(), HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_ResetCallback(), HAL_PCD_RESUME_CB_ID, HAL_PCD_ResumeCallback(), HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SetupStageCallback(), HAL_PCD_SOF_CB_ID, HAL_PCD_SOFCallback(), HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, HAL_PCD_SuspendCallback(), __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 647 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataInStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 574 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataOutStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 793 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 720 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 939 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1566 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1442 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterDataInStageCallback().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1425 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_OutXfrComplete_int().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1581 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

Handles PCD interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1038 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, __HAL_PCD_IS_INVALID_INTERRUPT, __PCD_HandleTypeDef::BESL, __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DisconnectCallback, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), HAL_RCC_GetHCLKFreq(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::ISOINIncompleteCallback, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, LPM_L0, LPM_L1, __PCD_HandleTypeDef::LPM_State, __PCD_HandleTypeDef::LPMCallback, __PCD_HandleTypeDef::OUT_ep, PCD_EP_OutSetupPacket_int(), PCD_EP_OutXfrComplete_int(), PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, PCD_WriteEmptyTxFifo(), __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::Setup, __PCD_HandleTypeDef::SOFCallback, and __PCD_HandleTypeDef::SuspendCallback.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1550 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1533 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1487 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1517 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1457 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterCallback(), and PCD_EP_OutSetupPacket_int().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1472 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 990 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_ENABLE, __PCD_HandleTypeDef::Init, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1016 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1502 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1929 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1939 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1615 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Init, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1640 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1714 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1870 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1906 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

uint32_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
Data Size

Definition at line 1781 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_mps | endpoint max packet size
ep_type | endpoint type
Return values:
HAL status

Definition at line 1670 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the reception buffer
len | amount of data to be received
Return values:
HAL status

Definition at line 1745 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1829 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, and __PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the transmission buffer
len | amount of data to be sent
Return values:
HAL status

Definition at line 1793 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd | PCD handle
address | new device address
Return values:
HAL status

Definition at line 1654 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::USB_Address.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD handle state.

Parameters:
hpcd PCD handle
Return values:
HAL state

Definition at line 1968 of file stm32h7xx_hal_pcd.c.

References __PCD_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Typedef Documentation

typedef USB_OTG_EPTypeDef PCD_EPTypeDef

Definition at line 87 of file stm32h7xx_hal_pcd.h.

typedef struct __PCD_HandleTypeDef PCD_HandleTypeDef

PCD Handle Structure definition.

typedef USB_OTG_CfgTypeDef PCD_InitTypeDef

Definition at line 86 of file stm32h7xx_hal_pcd.h.

typedef USB_OTG_GlobalTypeDef PCD_TypeDef

Definition at line 85 of file stm32h7xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 73 of file stm32h7xx_hal_pcd.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 67 of file stm32h7xx_hal_pcd.h.

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 59 of file stm32h7xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 49 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32h7xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [16]
PCD_EPTypeDef | OUT_ep [16]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData
void(* | SOFCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SetupStageCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResetCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SuspendCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResumeCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ConnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DisconnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DataOutStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | DataInStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOOUTIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOINIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | BCDCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
void(* | LPMCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
void(* | MspInitCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | MspDeInitCallback )(struct __PCD_HandleTypeDef *hpcd)

Detailed Description

PCD Handle Structure definition.

Definition at line 94 of file stm32h7xx_hal_pcd.h.

Field Documentation

uint32_t __PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

void(* __PCD_HandleTypeDef::BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

USB OTG PCD BCD callback

Definition at line 132 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t __PCD_HandleTypeDef::BESL

Definition at line 109 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

void(* __PCD_HandleTypeDef::ConnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Connect callback

Definition at line 125 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data IN Stage callback

Definition at line 129 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterDataInStageCallback(), and HAL_PCD_UnRegisterDataInStageCallback().

void(* __PCD_HandleTypeDef::DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data OUT Stage callback

Definition at line 128 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_OutXfrComplete_int().

void(* __PCD_HandleTypeDef::DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Disconnect callback

Definition at line 126 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint32_t __PCD_HandleTypeDef::ErrorCode

PCD Error code

Definition at line 106 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), HAL_PCD_UnRegisterLpmCallback(), and PSSI_Error().

PCD_EPTypeDef __PCD_HandleTypeDef::IN_ep[16]

IN endpoint parameters

Definition at line 102 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_InitTypeDef __PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 100 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_DevConnect(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_Start(), PCD_EP_OutSetupPacket_int(), PCD_EP_OutXfrComplete_int(), and PCD_WriteEmptyTxFifo().

PCD_TypeDef* __PCD_HandleTypeDef::Instance

Register base address

Definition at line 99 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), HAL_PCDEx_SetRxFiFo(), HAL_PCDEx_SetTxFiFo(), PCD_EP_OutSetupPacket_int(), PCD_EP_OutXfrComplete_int(), and PCD_WriteEmptyTxFifo().

void(* __PCD_HandleTypeDef::ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO IN Incomplete callback

Definition at line 131 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterIsoInIncpltCallback(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void(* __PCD_HandleTypeDef::ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO OUT Incomplete callback

Definition at line 130 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

HAL_LockTypeDef __PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 104 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t __PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 112 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef __PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 108 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

void(* __PCD_HandleTypeDef::LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

USB OTG PCD LPM callback

Definition at line 133 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterLpmCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp DeInit callback

Definition at line 136 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::MspInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp Init callback

Definition at line 135 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::OUT_ep[16]

OUT endpoint parameters

Definition at line 103 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_EP_OutXfrComplete_int().

void* __PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 117 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

void(* __PCD_HandleTypeDef::ResetCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Reset callback

Definition at line 122 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::ResumeCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Resume callback

Definition at line 124 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

uint32_t __PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 107 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), HAL_PCD_IRQHandler(), PCD_EP_OutSetupPacket_int(), and PCD_EP_OutXfrComplete_int().

void(* __PCD_HandleTypeDef::SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Setup Stage callback

Definition at line 121 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), HAL_PCD_UnRegisterCallback(), and PCD_EP_OutSetupPacket_int().

void(* __PCD_HandleTypeDef::SOFCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD SOF callback

Definition at line 120 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO PCD_StateTypeDef __PCD_HandleTypeDef::State

PCD communication state

Definition at line 105 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::SuspendCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Suspend callback

Definition at line 123 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint8_t __PCD_HandleTypeDef::USB_Address

USB Address

Definition at line 101 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_SetAddress().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pcd.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define | PCD_SPEED_HIGH USBD_HS_SPEED
#define | PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
#define | PCD_SPEED_FULL USBD_FS_SPEED

Define Documentation

#define PCD_SPEED_FULL USBD_FS_SPEED

Definition at line 157 of file stm32h7xx_hal_pcd.h.

#define PCD_SPEED_HIGH USBD_HS_SPEED

Definition at line 155 of file stm32h7xx_hal_pcd.h.

#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED

Definition at line 156 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 166 of file stm32h7xx_hal_pcd.h.

#define PCD_PHY_ULPI 1U

Definition at line 165 of file stm32h7xx_hal_pcd.h.

#define PCD_PHY_UTMI 3U

Definition at line 167 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Error Code definition

Defines
PCD Error Code definition
PCD Exported Constants

PCD Error Code definition. More...

Defines

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

PCD Error Code definition.

Define Documentation

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 177 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))

Definition at line 198 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 195 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 194 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GATE_PHYCLOCK ( __HANDLE__ ) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK

Definition at line 205 of file stm32h7xx_hal_pcd.h.

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 197 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)

Definition at line 199 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_PHY_SUSPENDED ( __HANDLE__ ) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)

Definition at line 207 of file stm32h7xx_hal_pcd.h.

#define __HAL_PCD_UNGATE_PHYCLOCK ( __HANDLE__ )
Value:
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
                                                          ~(USB_OTG_PCGCCTL_STOPCLK)

Definition at line 202 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 212 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 211 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 210 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 209 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define | USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11)

Define Documentation

#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU

Definition at line 367 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12)

USB FS EXTI Line WakeUp Interrupt

Definition at line 374 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U

Definition at line 366 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U

Definition at line 368 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU

Definition at line 371 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11)

USB HS EXTI Line WakeUp Interrupt

Definition at line 375 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U

Definition at line 370 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U

Definition at line 372 of file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 256 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 125 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::lpm_active, LPM_L0, and __PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 319 of file stm32h7xx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 159 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::BCDCallback, HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_DeActivateBCD(), __PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 279 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

Deactivate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 142 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 302 of file stm32h7xx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterLpmCallback().

HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | size
 | ) |  |

Set Rx FIFO.

Parameters:
hpcd | PCD handle
size | Size of Rx fifo
Return values:
HAL status

Definition at line 113 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | fifo,
 |  | uint16_t | size
 | ) |  |

Set Tx FIFO.

Parameters:
hpcd | PCD handle
fifo | The number of Tx fifo
size | Fifo size
Return values:
HAL status

Definition at line 71 of file stm32h7xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Private Define

PSSI Private Define
PSSI
Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Private Functions

Functions
PSSI Private Functions
PSSI

Functions

void | PSSI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA PSSI slave transmit process complete callback.
void | PSSI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA PSSI master receive process complete callback.
void | PSSI_DMAError (DMA_HandleTypeDef *hdma)
void | PSSI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA PSSI communication abort callback (To be called at end of DMA Abort procedure).
static void | PSSI_Error (PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
PSSI Errors process.
static HAL_StatusTypeDef | PSSI_WaitOnStatusUntilTimeout (PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles PSSI Communication Timeout.

Function Documentation

void PSSI_DMAAbort ( DMA_HandleTypeDef * hdma )

DMA PSSI communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1674 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), and PSSI_Error().

void PSSI_DMAError ( DMA_HandleTypeDef * hdma )

Definition at line 1730 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_DISABLE, HAL_PSSI_DISABLE_IT, HAL_PSSI_ERROR_NONE, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_READY, PSSI_Error(), PSSI_FLAG_OVR_RIS, and __PSSI_HandleTypeDef::State.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

void PSSI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma )

DMA PSSI master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1633 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_DISABLE_IT, HAL_PSSI_ERROR_NONE, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_READY, PSSI_Error(), PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::RxCpltCallback, and __PSSI_HandleTypeDef::State.

Referenced by HAL_PSSI_Receive_DMA().

void PSSI_DMATransmitCplt ( DMA_HandleTypeDef * hdma )

DMA PSSI slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1592 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_DISABLE_IT, HAL_PSSI_ERROR_NONE, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_READY, PSSI_Error(), PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::State, and __PSSI_HandleTypeDef::TxCpltCallback.

Referenced by HAL_PSSI_Transmit_DMA().

static void PSSI_Error | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

PSSI Errors process.

Parameters:
hpssi | PSSI handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 1493 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, __PCD_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_PSSI_DISABLE_IT, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_BUSY_RX, HAL_PSSI_STATE_BUSY_TX, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Instance, PSSI_DMAAbort(), PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __PSSI_HandleTypeDef::XferCount.

Referenced by PSSI_DMAError(), PSSI_DMAReceiveCplt(), and PSSI_DMATransmitCplt().

static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles PSSI Communication Timeout.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Flag | Specifies the PSSI flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 1709 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_PSSI_ERROR_TIMEOUT, HAL_PSSI_GET_STATUS, HAL_PSSI_STATE_READY, and __PSSI_HandleTypeDef::State.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PSSI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PSSI_Init (PSSI_HandleTypeDef *hpssi)
Initializes the PSSI according to the specified parameters in the PSSI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PSSI_DeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI peripheral.
__weak void | HAL_PSSI_MspInit (PSSI_HandleTypeDef *hpssi)
Initialize the PSSI MSP.
__weak void | HAL_PSSI_MspDeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI MSP.
HAL_StatusTypeDef | HAL_PSSI_RegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback)
Register a User PSSI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PSSI_UnRegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
Unregister an PSSI Callback PSSI callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the PSSIx peripheral:

      (+) User must implement HAL_PSSI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_PSSI_Init() to configure the selected device with
          the selected configuration:
        (++) Data Width
        (++) Control Signals
        (++) Input Clock polarity
        (++) Output Clock polarity

      (+) Call the function HAL_PSSI_DeInit() to restore the default configuration
          of the selected PSSIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_PSSI_DeInit ( PSSI_HandleTypeDef * hpssi )

DeInitialize the PSSI peripheral.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
HAL status

Definition at line 298 of file stm32h7xx_hal_pssi.c.

References assert_param, __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_DISABLE, HAL_PSSI_ERROR_NONE, HAL_PSSI_MspDeInit(), HAL_PSSI_STATE_BUSY, HAL_PSSI_STATE_RESET, __PSSI_HandleTypeDef::Instance, __PSSI_HandleTypeDef::MspDeInitCallback, and __PSSI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PSSI_Init ( PSSI_HandleTypeDef * hpssi )

Initializes the PSSI according to the specified parameters in the PSSI_InitTypeDef and initialize the associated handle.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
HAL status

Definition at line 238 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, assert_param, PSSI_InitTypeDef::BusWidth, PSSI_InitTypeDef::ClockPolarity, PSSI_InitTypeDef::ControlSignal, PSSI_InitTypeDef::DataEnablePolarity, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_AbortCpltCallback(), HAL_PSSI_DISABLE, HAL_PSSI_ERROR_NONE, HAL_PSSI_ErrorCallback(), HAL_PSSI_MspInit(), HAL_PSSI_RxCpltCallback(), HAL_PSSI_STATE_BUSY, HAL_PSSI_STATE_READY, HAL_PSSI_STATE_RESET, HAL_PSSI_TxCpltCallback(), __PSSI_HandleTypeDef::Init, __PSSI_HandleTypeDef::Instance, IS_PSSI_BUSWIDTH, IS_PSSI_CLOCK_POLARITY, IS_PSSI_CONTROL_SIGNAL, IS_PSSI_DE_POLARITY, IS_PSSI_RDY_POLARITY, __PSSI_HandleTypeDef::Lock, __PSSI_HandleTypeDef::MspInitCallback, PSSI_InitTypeDef::ReadyPolarity, __PSSI_HandleTypeDef::RxCpltCallback, __PSSI_HandleTypeDef::State, and __PSSI_HandleTypeDef::TxCpltCallback.

void HAL_PSSI_MspDeInit ( PSSI_HandleTypeDef * hpssi )

DeInitialize the PSSI MSP.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 353 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_DeInit(), and HAL_PSSI_UnRegisterCallback().

void HAL_PSSI_MspInit ( PSSI_HandleTypeDef * hpssi )

Initialize the PSSI MSP.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 337 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_Init(), and HAL_PSSI_UnRegisterCallback().

HAL_StatusTypeDef HAL_PSSI_RegisterCallback | ( | PSSI_HandleTypeDef * | hpssi,
 |  | HAL_PSSI_CallbackIDTypeDef | CallbackID,
 |  | pPSSI_CallbackTypeDef | pCallback
 | ) |  |

Register a User PSSI Callback To be used instead of the weak predefined callback.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
  • HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
  • HAL_PSSI_ERROR_CB_ID Error callback ID
  • HAL_PSSI_ABORT_CB_ID Abort callback ID
  • HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
  • HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 379 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_ABORT_CB_ID, HAL_PSSI_ERROR_CB_ID, HAL_PSSI_ERROR_INVALID_CALLBACK, HAL_PSSI_MSPDEINIT_CB_ID, HAL_PSSI_MSPINIT_CB_ID, HAL_PSSI_RX_COMPLETE_CB_ID, HAL_PSSI_STATE_READY, HAL_PSSI_STATE_RESET, HAL_PSSI_TX_COMPLETE_CB_ID, __PSSI_HandleTypeDef::MspDeInitCallback, __PSSI_HandleTypeDef::MspInitCallback, __PSSI_HandleTypeDef::RxCpltCallback, __PSSI_HandleTypeDef::State, and __PSSI_HandleTypeDef::TxCpltCallback.

HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback | ( | PSSI_HandleTypeDef * | hpssi,
 |  | HAL_PSSI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an PSSI Callback PSSI callback is redirected to the weak predefined callback.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
  • HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
  • HAL_PSSI_ERROR_CB_ID Error callback ID
  • HAL_PSSI_ABORT_CB_ID Abort callback ID
  • HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
  • HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 480 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_PSSI_ABORT_CB_ID, HAL_PSSI_AbortCpltCallback(), HAL_PSSI_ERROR_CB_ID, HAL_PSSI_ERROR_INVALID_CALLBACK, HAL_PSSI_ErrorCallback(), HAL_PSSI_MspDeInit(), HAL_PSSI_MSPDEINIT_CB_ID, HAL_PSSI_MspInit(), HAL_PSSI_MSPINIT_CB_ID, HAL_PSSI_RX_COMPLETE_CB_ID, HAL_PSSI_RxCpltCallback(), HAL_PSSI_STATE_READY, HAL_PSSI_STATE_RESET, HAL_PSSI_TX_COMPLETE_CB_ID, HAL_PSSI_TxCpltCallback(), __PSSI_HandleTypeDef::MspDeInitCallback, __PSSI_HandleTypeDef::MspInitCallback, __PSSI_HandleTypeDef::RxCpltCallback, __PSSI_HandleTypeDef::State, and __PSSI_HandleTypeDef::TxCpltCallback.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PSSI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PSSI_Transmit (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Receive (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Transmit_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Receive_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Abort_DMA (PSSI_HandleTypeDef *hpssi)
Abort a DMA process communication with Interrupt.
void | HAL_PSSI_IRQHandler (PSSI_HandleTypeDef *hpssi)
This function handles PSSI event interrupt request.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PSSI data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using DMA.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated  the DMA IRQ .

    (#) Blocking mode functions are :
        (++) HAL_PSSI_Transmit()
        (++) HAL_PSSI_Receive()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_PSSI_Transmit_DMA()
        (++) HAL_PSSI_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_PSSI_TxCpltCallback()
        (++) HAL_PSSI_RxCpltCallback()
        (++) HAL_PSSI_ErrorCallback()
        (++) HAL_PSSI_AbortCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_PSSI_Abort_DMA ( PSSI_HandleTypeDef * hpssi )

Abort a DMA process communication with Interrupt.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
HAL status

Definition at line 1177 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCallback, HAL_DMA_Abort_IT(), HAL_PSSI_DISABLE_IT, HAL_PSSI_ENABLE_IT, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_BUSY_RX, HAL_PSSI_STATE_BUSY_TX, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Instance, PSSI_DMAAbort(), PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_PSSI_IRQHandler ( PSSI_HandleTypeDef * hpssi )

This function handles PSSI event interrupt request.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1266 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_PSSI_DISABLE_IT, HAL_PSSI_ERROR_OVER_RUN, HAL_PSSI_ERROR_UNDER_RUN, HAL_PSSI_GET_FLAG, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_BUSY_RX, HAL_PSSI_STATE_BUSY_TX, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Instance, PSSI_DMAAbort(), PSSI_FLAG_OVR_MIS, PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __PSSI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_PSSI_Receive | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint8_t * | pData,
 |  | uint32_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data in blocking mode.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
pData | Pointer to data buffer
Size | Amount of data to be received (in bytes)
Timeout | Timeout duration
Return values:
HAL status

Definition at line 762 of file stm32h7xx_hal_pssi.c.

References PSSI_InitTypeDef::BusWidth, PSSI_InitTypeDef::ClockPolarity, PSSI_InitTypeDef::DataWidth, __PSSI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_PSSI_16BITS, HAL_PSSI_32BITS, HAL_PSSI_8BITS, HAL_PSSI_8LINES, HAL_PSSI_CLEAR_FLAG, HAL_PSSI_DISABLE, HAL_PSSI_ENABLE, HAL_PSSI_ERROR_NONE, HAL_PSSI_ERROR_NOT_SUPPORTED, HAL_PSSI_ERROR_OVER_RUN, HAL_PSSI_ERROR_TIMEOUT, HAL_PSSI_FALLING_EDGE, HAL_PSSI_GET_FLAG, HAL_PSSI_STATE_BUSY, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::Init, __PSSI_HandleTypeDef::Instance, __PCD_HandleTypeDef::pData, PSSI_CR_DMA_DISABLE, PSSI_CR_OUTEN_INPUT, PSSI_FLAG_OVR_RIS, PSSI_FLAG_RTT1B, PSSI_FLAG_RTT4B, PSSI_WaitOnStatusUntilTimeout(), and __PSSI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PSSI_Receive_DMA | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint32_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
pData | Pointer to data buffer
Size | Amount of data to be received (in bytes)
Return values:
HAL status

Definition at line 1045 of file stm32h7xx_hal_pssi.c.

References PSSI_InitTypeDef::BusWidth, PSSI_InitTypeDef::ClockPolarity, DMA_PDATAALIGN_BYTE, __PSSI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_PSSI_DISABLE, HAL_PSSI_ENABLE, HAL_PSSI_ENABLE_IT, HAL_PSSI_ERROR_DMA, HAL_PSSI_ERROR_NONE, HAL_PSSI_RISING_EDGE, HAL_PSSI_STATE_BUSY_RX, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __PSSI_HandleTypeDef::Instance, __PSSI_HandleTypeDef::pBuffPtr, __PCD_HandleTypeDef::pData, DMA_InitTypeDef::PeriphDataAlignment, PSSI_CR_DMA_ENABLE, PSSI_DMAError(), PSSI_DMAReceiveCplt(), PSSI_FLAG_OVR_RIS, PSSI_MAX_NBYTE_SIZE, __PSSI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __PSSI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __PSSI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_PSSI_Transmit | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint8_t * | pData,
 |  | uint32_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
pData | Pointer to data buffer
Size | Amount of data to be sent (in bytes)
Timeout | Timeout duration
Return values:
HAL status

Definition at line 611 of file stm32h7xx_hal_pssi.c.

References PSSI_InitTypeDef::BusWidth, PSSI_InitTypeDef::ClockPolarity, PSSI_InitTypeDef::DataWidth, __PSSI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_PSSI_16BITS, HAL_PSSI_32BITS, HAL_PSSI_8BITS, HAL_PSSI_8LINES, HAL_PSSI_CLEAR_FLAG, HAL_PSSI_DISABLE, HAL_PSSI_ENABLE, HAL_PSSI_ERROR_NONE, HAL_PSSI_ERROR_NOT_SUPPORTED, HAL_PSSI_ERROR_TIMEOUT, HAL_PSSI_ERROR_UNDER_RUN, HAL_PSSI_GET_FLAG, HAL_PSSI_RISING_EDGE, HAL_PSSI_STATE_BUSY, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::Init, __PSSI_HandleTypeDef::Instance, __PCD_HandleTypeDef::pData, PSSI_CR_DMA_DISABLE, PSSI_CR_OUTEN_OUTPUT, PSSI_FLAG_OVR_RIS, PSSI_FLAG_RTT1B, PSSI_FLAG_RTT4B, PSSI_WaitOnStatusUntilTimeout(), and __PSSI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PSSI_Transmit_DMA | ( | PSSI_HandleTypeDef * | hpssi,
 |  | uint32_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hpssi | Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
pData | Pointer to data buffer
Size | Amount of data to be sent (in bytes)
Return values:
HAL status

Definition at line 907 of file stm32h7xx_hal_pssi.c.

References PSSI_InitTypeDef::BusWidth, PSSI_InitTypeDef::ClockPolarity, DMA_PDATAALIGN_BYTE, __PSSI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_PSSI_DISABLE, HAL_PSSI_ENABLE, HAL_PSSI_ENABLE_IT, HAL_PSSI_ERROR_DMA, HAL_PSSI_ERROR_NONE, HAL_PSSI_RISING_EDGE, HAL_PSSI_STATE_BUSY_TX, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __PSSI_HandleTypeDef::Instance, __PSSI_HandleTypeDef::pBuffPtr, __PCD_HandleTypeDef::pData, DMA_InitTypeDef::PeriphDataAlignment, PSSI_CR_DMA_ENABLE, PSSI_CR_OUTEN_OUTPUT, PSSI_DMAError(), PSSI_DMATransmitCplt(), PSSI_FLAG_OVR_RIS, PSSI_MAX_NBYTE_SIZE, __PSSI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __PSSI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __PSSI_HandleTypeDef::XferSize.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
PSSI Exported Functions

Functions

void | HAL_PSSI_IRQHandler (PSSI_HandleTypeDef *hpssi)
This function handles PSSI event interrupt request.
__weak void | HAL_PSSI_TxCpltCallback (PSSI_HandleTypeDef *hpssi)
Tx Transfer complete callback.
__weak void | HAL_PSSI_RxCpltCallback (PSSI_HandleTypeDef *hpssi)
Rx Transfer complete callback.
__weak void | HAL_PSSI_ErrorCallback (PSSI_HandleTypeDef *hpssi)
PSSI error callback.
__weak void | HAL_PSSI_AbortCpltCallback (PSSI_HandleTypeDef *hpssi)
PSSI abort callback.

Function Documentation

void HAL_PSSI_AbortCpltCallback ( PSSI_HandleTypeDef * hpssi )

PSSI abort callback.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1422 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_Init(), and HAL_PSSI_UnRegisterCallback().

void HAL_PSSI_ErrorCallback ( PSSI_HandleTypeDef * hpssi )

PSSI error callback.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1406 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_Init(), and HAL_PSSI_UnRegisterCallback().

void HAL_PSSI_IRQHandler ( PSSI_HandleTypeDef * hpssi )

This function handles PSSI event interrupt request.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1266 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::AbortCpltCallback, __PSSI_HandleTypeDef::ErrorCallback, __PSSI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_PSSI_DISABLE_IT, HAL_PSSI_ERROR_OVER_RUN, HAL_PSSI_ERROR_UNDER_RUN, HAL_PSSI_GET_FLAG, HAL_PSSI_STATE_ABORT, HAL_PSSI_STATE_BUSY_RX, HAL_PSSI_STATE_BUSY_TX, HAL_PSSI_STATE_READY, __PSSI_HandleTypeDef::hdmarx, __PSSI_HandleTypeDef::hdmatx, __PSSI_HandleTypeDef::Instance, PSSI_DMAAbort(), PSSI_FLAG_OVR_MIS, PSSI_FLAG_OVR_RIS, __PSSI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __PSSI_HandleTypeDef::XferCount.

void HAL_PSSI_RxCpltCallback ( PSSI_HandleTypeDef * hpssi )

Rx Transfer complete callback.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1389 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_Init(), and HAL_PSSI_UnRegisterCallback().

void HAL_PSSI_TxCpltCallback ( PSSI_HandleTypeDef * hpssi )

Tx Transfer complete callback.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
None

Definition at line 1373 of file stm32h7xx_hal_pssi.c.

Referenced by HAL_PSSI_Init(), and HAL_PSSI_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
PSSI Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_PSSI_StateTypeDef | HAL_PSSI_GetState (PSSI_HandleTypeDef *hpssi)
Return the PSSI handle state.
uint32_t | HAL_PSSI_GetError (PSSI_HandleTypeDef *hpssi)
Return the PSSI error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_PSSI_GetError ( PSSI_HandleTypeDef * hpssi )

Return the PSSI error code.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
PSSI Error Code

Definition at line 1470 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::ErrorCode.

HAL_PSSI_StateTypeDef HAL_PSSI_GetState ( PSSI_HandleTypeDef * hpssi )

Return the PSSI handle state.

Parameters:
hpssi Pointer to a PSSI_HandleTypeDef structure that contains the configuration information for the specified PSSI.
Return values:
HAL state

Definition at line 1457 of file stm32h7xx_hal_pssi.c.

References __PSSI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Exported Types

Data Structures | Typedefs | Enumerations
PSSI Exported Types
PSSI

Data Structures

struct | PSSI_InitTypeDef
PSSI Init structure definition. More...
struct | __PSSI_HandleTypeDef
PSSI handle Structure definition. More...

Typedefs

typedef struct __PSSI_HandleTypeDef | PSSI_HandleTypeDef
PSSI handle Structure definition.
typedef void(* | pPSSI_CallbackTypeDef )(PSSI_HandleTypeDef *hpssi)
HAL PSSI Callback pointer definition.

Enumerations

enum HAL_PSSI_StateTypeDef {
HAL_PSSI_STATE_RESET = 0x00U, HAL_PSSI_STATE_READY = 0x01U, HAL_PSSI_STATE_BUSY = 0x02U, HAL_PSSI_STATE_BUSY_TX = 0x03U,
HAL_PSSI_STATE_BUSY_RX = 0x04U, HAL_PSSI_STATE_TIMEOUT = 0x05U, HAL_PSSI_STATE_ERROR = 0x06U, HAL_PSSI_STATE_ABORT = 0x07U
}
HAL PSSI State structures definition. More...

Typedef Documentation

typedef void(* pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi)

HAL PSSI Callback pointer definition.

Pointer to a PSSI common callback function

Definition at line 108 of file stm32h7xx_hal_pssi.h.

typedef struct __PSSI_HandleTypeDef PSSI_HandleTypeDef

PSSI handle Structure definition.

Enumeration Type Documentation

enum HAL_PSSI_StateTypeDef

HAL PSSI State structures definition.

Enumerator:
HAL_PSSI_STATE_RESET
HAL_PSSI_STATE_READY
HAL_PSSI_STATE_BUSY
HAL_PSSI_STATE_BUSY_TX
HAL_PSSI_STATE_BUSY_RX
HAL_PSSI_STATE_TIMEOUT
HAL_PSSI_STATE_ERROR
HAL_PSSI_STATE_ABORT

Definition at line 64 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PSSI_InitTypeDef Struct Reference
PSSI Exported Types

PSSI Init structure definition. More...

#include <stm32h7xx_hal_pssi.h>

Data Fields

uint32_t | DataWidth
uint32_t | BusWidth
uint32_t | ControlSignal
uint32_t | ClockPolarity
uint32_t | DataEnablePolarity
uint32_t | ReadyPolarity

Detailed Description

PSSI Init structure definition.

Definition at line 49 of file stm32h7xx_hal_pssi.h.

Field Documentation

uint32_t PSSI_InitTypeDef::BusWidth

Definition at line 52 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

uint32_t PSSI_InitTypeDef::ClockPolarity

Definition at line 54 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

uint32_t PSSI_InitTypeDef::ControlSignal

Definition at line 53 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

uint32_t PSSI_InitTypeDef::DataEnablePolarity

Definition at line 55 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

uint32_t PSSI_InitTypeDef::DataWidth

Definition at line 51 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

uint32_t PSSI_InitTypeDef::ReadyPolarity

Definition at line 56 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pssi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __PSSI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PSSI_HandleTypeDef Struct Reference
PSSI Exported Types

PSSI handle Structure definition. More...

#include <stm32h7xx_hal_pssi.h>

Data Fields

PSSI_TypeDef * | Instance
PSSI_InitTypeDef Init
uint32_t * | pBuffPtr
uint32_t | XferCount
uint32_t | XferSize
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
void(* | TxCpltCallback )(struct __PSSI_HandleTypeDef *hpssi)
void(* | RxCpltCallback )(struct __PSSI_HandleTypeDef *hpssi)
void(* | ErrorCallback )(struct __PSSI_HandleTypeDef *hpssi)
void(* | AbortCpltCallback )(struct __PSSI_HandleTypeDef *hpssi)
void(* | MspInitCallback )(struct __PSSI_HandleTypeDef *hpssi)
void(* | MspDeInitCallback )(struct __PSSI_HandleTypeDef *hpssi)
HAL_LockTypeDef | Lock
__IO HAL_PSSI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

PSSI handle Structure definition.

Definition at line 80 of file stm32h7xx_hal_pssi.h.

Field Documentation

void(* __PSSI_HandleTypeDef::AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI transfer error callback.

Definition at line 93 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_IRQHandler(), HAL_PSSI_RegisterCallback(), HAL_PSSI_UnRegisterCallback(), PSSI_DMAAbort(), and PSSI_Error().

void(* __PSSI_HandleTypeDef::ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI transfer complete callback.

Definition at line 92 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_Init(), HAL_PSSI_IRQHandler(), HAL_PSSI_RegisterCallback(), HAL_PSSI_UnRegisterCallback(), PSSI_DMAAbort(), PSSI_DMAError(), and PSSI_Error().

__IO uint32_t __PSSI_HandleTypeDef::ErrorCode

PSSI error code.

Definition at line 100 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_DeInit(), HAL_PSSI_GetError(), HAL_PSSI_Init(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_RegisterCallback(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), HAL_PSSI_UnRegisterCallback(), PSSI_DMAError(), PSSI_DMAReceiveCplt(), PSSI_DMATransmitCplt(), PSSI_Error(), and PSSI_WaitOnStatusUntilTimeout().

DMA_HandleTypeDef* __PSSI_HandleTypeDef::hdmarx

PSSI Rx DMA Handle parameters

Definition at line 88 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive_DMA(), PSSI_DMAAbort(), and PSSI_Error().

DMA_HandleTypeDef* __PSSI_HandleTypeDef::hdmatx

PSSI Tx DMA Handle parameters

Definition at line 87 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), PSSI_DMAAbort(), and PSSI_Error().

PSSI_InitTypeDef __PSSI_HandleTypeDef::Init

PSSI Initialization Structure.

Definition at line 83 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

PSSI_TypeDef* __PSSI_HandleTypeDef::Instance

PSSI register base address.

Definition at line 82 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_DeInit(), HAL_PSSI_Init(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), and PSSI_Error().

HAL_LockTypeDef __PSSI_HandleTypeDef::Lock

PSSI lock.

Definition at line 98 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

void(* __PSSI_HandleTypeDef::MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI Msp DeInit callback.

Definition at line 96 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_DeInit(), HAL_PSSI_RegisterCallback(), and HAL_PSSI_UnRegisterCallback().

void(* __PSSI_HandleTypeDef::MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI Msp Init callback.

Definition at line 95 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_RegisterCallback(), and HAL_PSSI_UnRegisterCallback().

uint32_t* __PSSI_HandleTypeDef::pBuffPtr

PSSI Data buffer.

Definition at line 84 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

void(* __PSSI_HandleTypeDef::RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI transfer complete callback.

Definition at line 91 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_RegisterCallback(), HAL_PSSI_UnRegisterCallback(), and PSSI_DMAReceiveCplt().

__IO HAL_PSSI_StateTypeDef __PSSI_HandleTypeDef::State

PSSI transfer state.

Definition at line 99 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_DeInit(), HAL_PSSI_GetState(), HAL_PSSI_Init(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_RegisterCallback(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), HAL_PSSI_UnRegisterCallback(), PSSI_DMAAbort(), PSSI_DMAError(), PSSI_DMAReceiveCplt(), PSSI_DMATransmitCplt(), PSSI_Error(), and PSSI_WaitOnStatusUntilTimeout().

void(* __PSSI_HandleTypeDef::TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi)

PSSI transfer complete callback.

Definition at line 90 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init(), HAL_PSSI_RegisterCallback(), HAL_PSSI_UnRegisterCallback(), and PSSI_DMATransmitCplt().

uint32_t __PSSI_HandleTypeDef::XferCount

PSSI transfer count

Definition at line 85 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_IRQHandler(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit_DMA(), and PSSI_Error().

uint32_t __PSSI_HandleTypeDef::XferSize

PSSI transfer size

Definition at line 86 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pssi.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Error Code

Defines
PSSI Error Code
PSSI Exported Constants

Defines

#define | HAL_PSSI_ERROR_NONE 0x00000000U
#define | HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U
#define | HAL_PSSI_ERROR_UNDER_RUN 0x00000002U
#define | HAL_PSSI_ERROR_OVER_RUN 0x00000004U
#define | HAL_PSSI_ERROR_DMA 0x00000008U
#define | HAL_PSSI_ERROR_TIMEOUT 0x00000010U
#define | HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U

Define Documentation

#define HAL_PSSI_ERROR_DMA 0x00000008U

Dma error

Definition at line 140 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U

Invalid callback error

Definition at line 142 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_RegisterCallback(), and HAL_PSSI_UnRegisterCallback().

#define HAL_PSSI_ERROR_NONE 0x00000000U

No error

Definition at line 136 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_DeInit(), HAL_PSSI_Init(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), PSSI_DMAError(), PSSI_DMAReceiveCplt(), and PSSI_DMATransmitCplt().

#define HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U

Not supported operation

Definition at line 137 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define HAL_PSSI_ERROR_OVER_RUN 0x00000004U

FIFO Over-run error

Definition at line 139 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_IRQHandler(), and HAL_PSSI_Receive().

#define HAL_PSSI_ERROR_TIMEOUT 0x00000010U

Timeout error

Definition at line 141 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), HAL_PSSI_Transmit(), and PSSI_WaitOnStatusUntilTimeout().

#define HAL_PSSI_ERROR_UNDER_RUN 0x00000002U

FIFO Under-run error

Definition at line 138 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_IRQHandler(), and HAL_PSSI_Transmit().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Data Width

Defines
PSSI Data Width
PSSI Exported Constants

Defines

#define | HAL_PSSI_8BITS 0x00000000U
#define | HAL_PSSI_16BITS 0x00000001U
#define | HAL_PSSI_32BITS 0x00000002U

Define Documentation

#define HAL_PSSI_16BITS 0x00000001U

16 Bits

Definition at line 154 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define HAL_PSSI_32BITS 0x00000002U

32 Bits

Definition at line 155 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define HAL_PSSI_8BITS 0x00000000U

8 Bits

Definition at line 153 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Bus Width

Defines
PSSI Bus Width
PSSI Exported Constants

Defines

#define | HAL_PSSI_8LINES 0x00000000U
#define | HAL_PSSI_16LINES PSSI_CR_EDM

Define Documentation

#define HAL_PSSI_16LINES PSSI_CR_EDM

16 data lines

Definition at line 165 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_8LINES 0x00000000U

8 data lines

Definition at line 164 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI mode

Defines
PSSI mode
PSSI Exported Constants

Defines

#define | HAL_PSSI_UNIDIRECTIONAL 0x00000000U
#define | HAL_PSSI_BIDIRECTIONAL 0x00000001U

Define Documentation

#define HAL_PSSI_BIDIRECTIONAL 0x00000001U

Bi-directional mode

Definition at line 173 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_UNIDIRECTIONAL 0x00000000U

Uni-directional mode

Definition at line 172 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Defines
Configuration
PSSI Exported Constants

Defines

#define | HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos)

Define Documentation

#define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos)

Only DE enabled

Definition at line 183 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos)

Only DE enabled, mapped to RDY pin

Definition at line 187 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos)

Both RDY and DE alternate functions enabled

Definition at line 184 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos)

Neither DE nor RDY are enabled

Definition at line 181 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos)

Bi-directional on DE pin

Definition at line 188 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos)

Bi-directional on RDY pin

Definition at line 185 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos)

Only RDY enabled

Definition at line 182 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos)

Only RDY enabled, mapped to DE pin

Definition at line 186 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Enable Polarity

Defines
Data Enable Polarity
PSSI Exported Constants

Defines

#define | HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U
#define | HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL

Define Documentation

#define HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL

Active High

Definition at line 199 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U

Active Low

Definition at line 198 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Reday Polarity

Defines
Reday Polarity
PSSI Exported Constants

Defines

#define | HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U
#define | HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL

Define Documentation

#define HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL

Active High

Definition at line 207 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U

Active Low

Definition at line 206 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Polarity

Defines
Clock Polarity
PSSI Exported Constants

Defines

#define | HAL_PSSI_FALLING_EDGE 0x0U
#define | HAL_PSSI_RISING_EDGE 0x1U

Define Documentation

#define HAL_PSSI_FALLING_EDGE 0x0U

Fallling Edge

Definition at line 215 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive().

#define HAL_PSSI_RISING_EDGE 0x1U

Rising Edge

Definition at line 216 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI definitions

Defines
PSSI definitions
PSSI Exported Constants

Defines

#define | PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */
#define | PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU
#define | PSSI_CR_OUTEN_INPUT 0x00000000U
#define | PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN
#define | PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN
#define | PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN)
#define | PSSI_CR_16BITS PSSI_CR_EDM
#define | PSSI_CR_8BITS (~PSSI_CR_EDM)
#define | PSSI_FLAG_RTT1B PSSI_SR_RTT1B
#define | PSSI_FLAG_RTT4B PSSI_SR_RTT4B

Define Documentation

#define PSSI_CR_16BITS PSSI_CR_EDM

16 Lines Mode

Definition at line 237 of file stm32h7xx_hal_pssi.h.

#define PSSI_CR_8BITS (~PSSI_CR_EDM)

8 Lines Mode

Definition at line 238 of file stm32h7xx_hal_pssi.h.

#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN)

DMA Mode Disble

Definition at line 235 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN

DMA Mode Enable

Definition at line 234 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

#define PSSI_CR_OUTEN_INPUT 0x00000000U

Input Mode

Definition at line 231 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive().

#define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN

Output Mode

Definition at line 232 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B

1 Byte Fifo Flag

Definition at line 240 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B

4 Bytes Fifo Flag

Definition at line 241 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */

Definition at line 228 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

#define PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU

Timeout Value

Definition at line 229 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Interrupts

Defines
PSSI Interrupts
PSSI Exported Constants

Defines

#define | PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS
#define | PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk
#define | PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS

Define Documentation

#define PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk

Overrun, Underrun errors Mask

Definition at line 251 of file stm32h7xx_hal_pssi.h.

#define PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS

Overrun, Underrun masked errors flag

Definition at line 252 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_IRQHandler().

#define PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS

Overrun, Underrun errors flag

Definition at line 250 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), PSSI_DMAError(), PSSI_DMAReceiveCplt(), PSSI_DMATransmitCplt(), and PSSI_Error().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Exported Macros

Defines
PSSI Exported Macros
PSSI

Defines

#define | HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__)
Reset PSSI handle state.
#define | HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
Enable the PSSI.
#define | HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
Disable the PSSI.
#define | HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
Get the PSSI pending flags.
#define | HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
Get the PSSI pending flags.
#define | HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the PSSI pending flags.
#define | HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified PSSI interrupts.
#define | HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified PSSI interrupts.
#define | HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Check whether the specified PSSI interrupt source is enabled or not.
#define | IS_PSSI_CONTROL_SIGNAL(__CONTROL__)
Check whether the PSSI Control signal is valid.
#define | IS_PSSI_BUSWIDTH(__BUSWIDTH__)
Check whether the PSSI Bus Width is valid.
#define | IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__)
Check whether the PSSI Clock Polarity is valid.
#define | IS_PSSI_DE_POLARITY(__DEPOL__)
Check whether the PSSI Data Enable Polarity is valid.
#define | IS_PSSI_RDY_POLARITY(__RDYPOL__)
Check whether the PSSI Ready Polarity is valid.

Define Documentation

#define HAL_PSSI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the PSSI pending flags.

Parameters:
__HANDLE__ PSSI handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
Return values:
None

Definition at line 323 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define HAL_PSSI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))

Disable the PSSI.

Parameters:
__HANDLE__ PSSI handle
Return values:
None.

Definition at line 287 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_DeInit(), HAL_PSSI_Init(), HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), HAL_PSSI_Transmit_DMA(), and PSSI_DMAError().

#define HAL_PSSI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disable the specified PSSI interrupts.

Parameters:
__HANDLE__ PSSI handle
__INTERRUPT__ specifies the PSSI interrupt sources to be disabled. This parameter can be any combination of the following values:
  • PSSI_IT_OVR_IE: Configuration error mask
Return values:
None

Definition at line 343 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_IRQHandler(), PSSI_DMAError(), PSSI_DMAReceiveCplt(), PSSI_DMATransmitCplt(), and PSSI_Error().

#define HAL_PSSI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)

Enable the PSSI.

Parameters:
__HANDLE__ PSSI handle
Return values:
None.

Definition at line 281 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Receive(), HAL_PSSI_Receive_DMA(), HAL_PSSI_Transmit(), and HAL_PSSI_Transmit_DMA().

#define HAL_PSSI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified PSSI interrupts.

Parameters:
__HANDLE__ PSSI handle
__INTERRUPT__ specifies the PSSI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • PSSI_FLAG_OVR_RIS: Configuration error mask
Return values:
None

Definition at line 333 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Abort_DMA(), HAL_PSSI_Receive_DMA(), and HAL_PSSI_Transmit_DMA().

#define HAL_PSSI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->RIS & (__FLAG__))

Get the PSSI pending flags.

Parameters:
__HANDLE__ PSSI handle
__FLAG__ flag to check. This parameter can be any combination of the following values:
  • PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
Return values:
The state of FLAG.

Definition at line 313 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_IRQHandler(), HAL_PSSI_Receive(), and HAL_PSSI_Transmit().

#define HAL_PSSI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Check whether the specified PSSI interrupt source is enabled or not.

Parameters:
__HANDLE__ PSSI handle
__INTERRUPT__ specifies the PSSI interrupt source to check. This parameter can be one of the following values:
  • PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask
Return values:
The state of INTERRUPT source.

Definition at line 353 of file stm32h7xx_hal_pssi.h.

#define HAL_PSSI_GET_STATUS | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR & (__FLAG__))

Get the PSSI pending flags.

Parameters:
__HANDLE__ PSSI handle
__FLAG__ flag to check. This parameter can be any combination of the following values:
  • PSSI_FLAG_RTT1B: FIFO is ready to transfer one byte
  • PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes
Return values:
The state of FLAG.

Definition at line 300 of file stm32h7xx_hal_pssi.h.

Referenced by PSSI_WaitOnStatusUntilTimeout().

#define HAL_PSSI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                      (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;       \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                     }while(0)

Reset PSSI handle state.

Parameters:
__HANDLE__ specifies the PSSI handle.
Return values:
None

Definition at line 269 of file stm32h7xx_hal_pssi.h.

#define IS_PSSI_BUSWIDTH ( __BUSWIDTH__ )
Value:
(((__BUSWIDTH__) == HAL_PSSI_8LINES    ) || \
                                        ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))

Check whether the PSSI Bus Width is valid.

Parameters:
__BUSWIDTH__ PSSI Bush width
Return values:
Valid or not.

Definition at line 375 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

#define IS_PSSI_CLOCK_POLARITY ( __CLOCKPOL__ )
Value:
(((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \
                                              ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))

Check whether the PSSI Clock Polarity is valid.

Parameters:
__CLOCKPOL__ PSSI Clock Polarity
Return values:
Valid or not.

Definition at line 384 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

#define IS_PSSI_CONTROL_SIGNAL ( __CONTROL__ )
Value:
(((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE        ) || \
                                             ((__CONTROL__) == HAL_PSSI_RDY_ENABLE            ) || \
                                             ((__CONTROL__) == HAL_PSSI_DE_ENABLE             ) || \
                                             ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE     ) || \
                                             ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE  ) || \
                                             ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \
                                             ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \
                                             ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))

Check whether the PSSI Control signal is valid.

Parameters:
__CONTROL__ Control signals configuration
Return values:
Valid or not.

Definition at line 361 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

#define IS_PSSI_DE_POLARITY ( __DEPOL__ )
Value:
(((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \
                                        ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))

Check whether the PSSI Data Enable Polarity is valid.

Parameters:
__DEPOL__ PSSI DE Polarity
Return values:
Valid or not.

Definition at line 392 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

#define IS_PSSI_RDY_POLARITY ( __RDYPOL__ )
Value:
(((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \
                                         ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))

Check whether the PSSI Ready Polarity is valid.

Parameters:
__RDYPOL__ PSSI RDY Polarity
Return values:
Valid or not.

Definition at line 400 of file stm32h7xx_hal_pssi.h.

Referenced by HAL_PSSI_Init().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI

Modules | Enumerations
PSSI
STM32H7xx_HAL_Driver

PSSI HAL module driver. More...

Modules

PSSI Private Define
PSSI Private Functions
PSSI Exported Functions
PSSI Exported Types
PSSI Exported Constants
PSSI Exported Macros

Enumerations

enum HAL_PSSI_CallbackIDTypeDef {
HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, HAL_PSSI_ERROR_CB_ID = 0x03U, HAL_PSSI_ABORT_CB_ID = 0x04U,
HAL_PSSI_MSPINIT_CB_ID = 0x05U, HAL_PSSI_MSPDEINIT_CB_ID = 0x06U
}
HAL PSSI Callback ID enumeration definition. More...

Detailed Description

PSSI HAL module driver.

Enumeration Type Documentation

enum HAL_PSSI_CallbackIDTypeDef

HAL PSSI Callback ID enumeration definition.

Enumerator:
HAL_PSSI_TX_COMPLETE_CB_ID

PSSI Tx Transfer completed callback ID

HAL_PSSI_RX_COMPLETE_CB_ID

PSSI Rx Transfer completed callback ID

HAL_PSSI_ERROR_CB_ID

PSSI Error callback ID

HAL_PSSI_ABORT_CB_ID

PSSI Abort callback ID

HAL_PSSI_MSPINIT_CB_ID

PSSI Msp Init callback ID

HAL_PSSI_MSPDEINIT_CB_ID

PSSI Msp DeInit callback ID

Definition at line 116 of file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and De-Initialization Functions

Functions
Initialization and De-Initialization Functions
PWR Exported Functions

Initialization and De-Initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Initialization and De-Initialization functions.

 ===============================================================================
              ##### Initialization and De-Initialization Functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to deinitialize power peripheral.

    [..]
      After system reset, the backup domain (RTC registers, RTC backup data
      registers and backup SRAM) is protected against possible unwanted write
      accesses.
      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
      domain.
      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
      domain.

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Note:
This functionality is not available in this product. The prototype is kept just to maintain compatibility with other products.
Return values:
None.

Definition at line 227 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None.

Definition at line 251 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None.

Definition at line 238 of file stm32h7xx_hal_pwr.c.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control Functions

Functions
Peripheral Control Functions
PWR Exported Functions

Power Control functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the event mode and the voltage threshold detected by the Programmable Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Programmable Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Programmable Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter the current core in SLEEP mode (CSLEEP).
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND feature.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Power Control functions.

 ===============================================================================
                 ##### Peripheral Control Functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to control power peripheral.

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
          register).

      (+) A PVDO flag is available to indicate if VDD is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line 16 to generate an interrupt if enabled.
          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.

      (+) The PVD is stopped in STANDBY mode.

    *** Wake-up pin configuration ***
    =================================
    [..]
      (+) Wake-up pin is used to wake up the system from STANDBY mode.
          The pin pull is configurable through the WKUPEPR register to be in
          No-pull, Pull-up and Pull-down.
          The pin polarity is configurable through the WKUPEPR register to be
          active on rising or falling edges.

      (+) There are up to six Wake-up pin in the STM32H7 devices family.

    *** Low Power modes configuration ***
    =====================================
    [..]
     The device present 3 principles low-power modes features:
      (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
                         active (Powered and Clocked).

      (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
                         regulator is running. The Main regulator or the LP
                         regulator could be selected.

      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
                         supply regulator is powered off.

   *** SLEEP mode ***
   ==================
    [..]
      (+) Entry:
        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
        SLEEPEntry) function.

          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.

      -@@- The Regulator parameter is not used for the STM32H7 family
              and is kept as parameter just to maintain compatibility with the
              lower power families (STM32L).

      (+) Exit:
        Any peripheral interrupt acknowledged by the nested vectored interrupt
        controller (NVIC) can wake up the device from SLEEP mode.

   *** STOP mode ***
   =================
    [..]
      In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
      the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
      register contents are preserved.
      The voltage regulator can be configured either in normal or low-power mode.
      To minimize the consumption in STOP mode, FLASH can be powered off before
      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
      It can be switched on again by software after exiting the STOP mode using
      the HAL_PWREx_DisableFlashPowerDown() function.

      (+) Entry:
         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
         STOPEntry) function with:

         (++) Regulator:
          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.

         (++) STOPEntry:
          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.

      (+) Exit:
         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** STANDBY mode ***
   ====================
    [..]
    (+)
      The system STANDBY mode allows to achieve the lowest power consumption.
      It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
      disabled. The system is consequently powered off. The PLL, the HSI
      oscillator and the HSE oscillator are also switched off. SRAM and register
      contents are lost except for the RTC registers, RTC backup registers,
      backup SRAM and standby circuitry.

    [..]
      The voltage regulator is OFF.

      (++) Entry:
        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
              function.

      (++) Exit:
        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
              RTC wakeup, tamper event, time stamp event, external reset in NRST
              pin, IWDG reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
         RTC Wakeup event, a tamper event or a time-stamp event, without
         depending on an external interrupt (Auto-wakeup mode).

     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes

       (++) To wake up from the STOP mode with an RTC alarm event, it is
            necessary to configure the RTC to generate the RTC alarm using the
            HAL_RTC_SetAlarm_IT() function.

       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
            it is necessary to configure the RTC to detect the tamper or time
            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
            HAL_RTCEx_SetTamper_IT() functions.

       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
            necessary to configure the RTC to generate the RTC WakeUp event
            using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the event mode and the voltage threshold detected by the Programmable Voltage Detector(PVD).

Parameters:
sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
For dual core devices, please ensure to configure the EXTI lines for the different Cortex-Mx through PWR_Exported_Macro provided by this driver. All combination are allowed: wake up only Cortex-M7, wake up only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
Return values:
None.

Definition at line 417 of file stm32h7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disable the Programmable Voltage Detector (PVD).

Return values:
None.

Definition at line 482 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disable CORTEX SEVONPEND feature.

Note:
Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled pending causes exception entry wakes up the Cortex-Mx.
Return values:
None.

Definition at line 770 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 745 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx : Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
Return values:
None.

Definition at line 532 of file stm32h7xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enable the Programmable Voltage Detector (PVD).

Return values:
None.

Definition at line 472 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enable CORTEX SEVONPEND feature.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, any pending event / interrupt even if it's disabled or has insufficient priority to cause exception entry wakes up the Cortex-Mx.
Return values:
None.

Definition at line 758 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicate Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None.

Definition at line 732 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity : Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values, which sets the default (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. or one of the following values where the user can explicitly states the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None.

Definition at line 506 of file stm32h7xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_EWUP_MASK.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter the current core in SLEEP mode (CSLEEP).

Parameters:
Regulator : Specifies the regulator state in SLEEP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
  • PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power regulator ON.
Note:
This parameter is not used for the STM32H7 family and is kept as parameter just to maintain compatibility with the lower power families.
Parameters:
SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE intrinsic instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
  • PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
Note:
Ensure to clear pending events before calling this API through HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
Return values:
None.

Definition at line 560 of file stm32h7xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter STANDBY mode.

Note:
For single core devices, this API will enter the system in STANDBY mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR regiter is cleared. For dual core devices, this API will enter the domain (containing Cortex-Mx that executing this function) in DSTANDBY mode. If all Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register is cleared, all the system will enter in STANDBY mode.
The system enters Standby mode only when all domains are in DSTANDBY.
When the System exit STANDBY mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
Return values:
None.

Definition at line 680 of file stm32h7xx_hal_pwr.c.

References CM7_CPUID, and HAL_GetCurrentCPUID().

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter STOP mode.

Note:
For single core devices, this API will enter the system in STOP mode with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is cleared. For dual core devices, this API will enter the domain (containing Cortex-Mx that executing this function) in DSTOP mode. If all Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is cleared, all the system will enter in STOP mode.
Parameters:
Regulator : Specifies the regulator state in STOP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
  • PWR_LOWPOWERREGULATOR_ON : STOP mode with low power regulator ON.
STOPEntry : Specifies if STOP mode in entered with WFI or WFE intrinsic instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
  • PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
Note:
In System STOP mode, all I/O pins keep the same state as in Run mode.
When exiting System STOP mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as default system wakeup clock.
In System STOP mode, when the voltage regulator operates in low power mode, an additional startup delay is incurred when the system is waking up. By keeping the internal regulator ON during STOP mode, the consumption is higher although the startup time is reduced.
Return values:
None.

Definition at line 611 of file stm32h7xx_hal_pwr.c.

References assert_param, CM7_CPUID, HAL_GetCurrentCPUID(), IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_AVD_IRQHandler().
Return values:
None.

Definition at line 799 of file stm32h7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, CM7_CPUID, HAL_GetCurrentCPUID(), and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None.

Definition at line 844 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

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STM32H7B3xQ HAL User Manual: Interrupt Handling Functions

Functions
Interrupt Handling Functions
PWR Exported Functions

Interrupt Handling functions. More...

Functions

void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Interrupt Handling functions.

 ===============================================================================
                    ##### Interrupt Handling Functions #####
 ===============================================================================
    [..]
    This section provides functions allowing to handle the PVD pending
    interrupts.

Function Documentation

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_AVD_IRQHandler().
Return values:
None.

Definition at line 799 of file stm32h7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, CM7_CPUID, HAL_GetCurrentCPUID(), and HAL_PWR_PVDCallback().

__weak void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None.

Definition at line 844 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

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STM32H7B3xQ HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32h7xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 48 of file stm32h7xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the EXTI operating mode for the PVD event. This parameter can be a value of PWR PVD Mode.

Definition at line 55 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of PWR PVD detection level.

Definition at line 50 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr.h
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STM32H7B3xQ HAL User Manual: PWR PVD detection level

Defines
PWR PVD detection level
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0

Programmable voltage detector level 0 selection : 1V95

Definition at line 73 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1

Programmable voltage detector level 1 selection : 2V1

Definition at line 75 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2

Programmable voltage detector level 2 selection : 2V25

Definition at line 77 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3

Programmable voltage detector level 3 selection : 2V4

Definition at line 79 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4

Programmable voltage detector level 4 selection : 2V55

Definition at line 81 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5

Programmable voltage detector level 5 selection : 2V7

Definition at line 83 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6

Programmable voltage detector level 6 selection : 2V85

Definition at line 85 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7

External input analog voltage (Compare internally to VREF)

Definition at line 87 of file stm32h7xx_hal_pwr.h.

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STM32H7B3xQ HAL User Manual: PWR PVD Mode

Defines
PWR PVD Mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 101 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING (0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 100 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 102 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING (0x00010002U)

Interrupt Mode with Falling edge trigger detection

Definition at line 98 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING (0x00010001U)

Interrupt Mode with Rising edge trigger detection

Definition at line 97 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)

Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 99 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL (0x00000000U)

Basic mode is used

Definition at line 96 of file stm32h7xx_hal_pwr.h.

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STM32H7B3xQ HAL User Manual: PWR Regulator state in SLEEP/STOP mode

Defines
PWR Regulator state in SLEEP/STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON (0U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Definition at line 111 of file stm32h7xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON (0U)

Definition at line 110 of file stm32h7xx_hal_pwr.h.

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STM32H7B3xQ HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI (0x01U)
#define | PWR_SLEEPENTRY_WFE (0x02U)

Define Documentation

#define PWR_SLEEPENTRY_WFE (0x02U)

Definition at line 120 of file stm32h7xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI (0x01U)

Definition at line 119 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI (0x01U)
#define | PWR_STOPENTRY_WFE (0x02U)

Define Documentation

#define PWR_STOPENTRY_WFE (0x02U)

Definition at line 129 of file stm32h7xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI (0x01U)

Definition at line 128 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode(), HAL_PWREx_EnterSTOP2Mode(), and HAL_PWREx_EnterSTOPMode().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Regulator Voltage Scale

Defines
PWR Regulator Voltage Scale
PWR Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
#define | PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE3 (0U)

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)

Definition at line 138 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)

Definition at line 139 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)

Definition at line 140 of file stm32h7xx_hal_pwr.h.

#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U)

Definition at line 141 of file stm32h7xx_hal_pwr.h.

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STM32H7B3xQ HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_STOP (0x01U)
#define | PWR_FLAG_SB (0x04U)
#define | PWR_FLAG_PVDO (0x0BU)
#define | PWR_FLAG_AVDO (0x0CU)
#define | PWR_FLAG_ACTVOSRDY (0x0DU)
#define | PWR_FLAG_ACTVOS (0x0EU)
#define | PWR_FLAG_BRR (0x0FU)
#define | PWR_FLAG_VOSRDY (0x10U)
#define | PWR_FLAG_SMPSEXTRDY (0x11U)
#define | PWR_FLAG_MMCVDO (0x12U)
#define | PWR_FLAG_USB33RDY (0x13U)
#define | PWR_FLAG_TEMPH (0x14U)
#define | PWR_FLAG_TEMPL (0x15U)
#define | PWR_FLAG_VBATH (0x16U)
#define | PWR_FLAG_VBATL (0x17U)
#define | PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
#define | PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
#define | PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
#define | PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
#define | PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
#define | PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6

Define Documentation

#define PWR_FLAG_ACTVOS (0x0EU)

Definition at line 173 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_ACTVOSRDY (0x0DU)

Definition at line 172 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply(), and HAL_PWREx_ControlVoltageScaling().

#define PWR_FLAG_AVDO (0x0CU)

Definition at line 171 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_BRR (0x0FU)

Definition at line 174 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_FLAG_MMCVDO (0x12U)

Definition at line 182 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_PVDO (0x0BU)

Definition at line 170 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SB (0x04U)

Definition at line 161 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SMPSEXTRDY (0x11U)

Definition at line 177 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_FLAG_STOP (0x01U)

Definition at line 156 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_TEMPH (0x14U)

Definition at line 185 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_TEMPL (0x15U)

Definition at line 186 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_USB33RDY (0x13U)

Definition at line 184 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_DisableUSBReg(), and HAL_PWREx_EnableUSBReg().

#define PWR_FLAG_VBATH (0x16U)

Definition at line 187 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_VBATL (0x17U)

Definition at line 188 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_VOSRDY (0x10U)

Definition at line 175 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1

Definition at line 191 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2

Definition at line 192 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3

Definition at line 193 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4

Definition at line 194 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5

Definition at line 195 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6

Definition at line 196 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Enable WUP Mask

Defines
PWR Enable WUP Mask
PWR Exported Constants

Defines

#define PWR_EWUP_MASK (0x0FFF3F3FU)

Define Documentation

#define PWR_EWUP_MASK (0x0FFF3F3FU)

Definition at line 204 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnableWakeUpPin().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Exported Macro

Defines
PWR Exported Macro
PWR

Defines

#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check PWR flags are set or not.
#define | __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
Check PWR wake up flags are set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
Clear CPU PWR flags.
#define | __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
Clear PWR wake up flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
Enable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
Disable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Rising Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Rising Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Rising & Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Rising & Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generates a Software interrupt on PVD EXTI line.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)

Clear CPU PWR flags.

Parameters:
__FLAG__ : Specifies the flag to clear.
Note:
This parameter is not used for the STM32H7 family and is kept as parameter just to maintain compatibility with other families.
This macro clear all CPU flags. For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF. For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
Return values:
None.

Definition at line 482 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_CLEAR_WAKEUPFLAG ( __FLAG__ ) SET_BIT(PWR->WKUPCR, (__FLAG__))

Clear PWR wake up flags.

Parameters:
__FLAG__ : Specifies the wake up flag to be cleared. This parameter can be one of the following values :
  • PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
  • PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
  • PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
  • PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
  • PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
  • PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
Return values:
None.

Definition at line 496 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
 ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

Check PWR flags are set or not.

Parameters:
__FLAG__ : Specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the PVDE bit is set.
  • PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD is enabled by the HAL_PWREx_EnableAVD() function. The AVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the AVDE bit is set.
  • PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator voltage scaling output selection is ready.
  • PWR_FLAG_BRR : Backup regulator ready flag. This bit is not reset when the device wakes up from STANDBY mode or by a system reset or power-on reset.
  • PWR_FLAG_VOSRDY : This flag indicates that the Regulator voltage scaling output selection is ready. mode or by a system reset or power-on reset.
  • PWR_FLAG_USB33RDY : This flag indicates that the USB supply from regulator is ready.
  • PWR_FLAG_TEMPH : This flag indicates that the temperature equal or above high threshold level.
  • PWR_FLAG_TEMPL : This flag indicates that the temperature equal or below low threshold level.
  • PWR_FLAG_VBATH : This flag indicates that VBAT level equal or above high threshold level.
  • PWR_FLAG_VBATL : This flag indicates that VBAT level equal or below low threshold level.
  • PWR_FLAG_STOP : This flag indicates that the system entered in STOP mode.
  • PWR_FLAG_SB : This flag indicates that the system entered in STANDBY mode.
  • PWR_FLAG_SB_D1 : This flag indicates that the D1 domain entered in STANDBY mode.
  • PWR_FLAG_SB_D2 : This flag indicates that the D2 domain entered in STANDBY mode.
  • PWR_FLAG2_STOP : This flag indicates that the system entered in STOP mode.
  • PWR_FLAG2_SB : This flag indicates that the system entered in STANDBY mode.
  • PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain entered in STANDBY mode.
  • PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain entered in STANDBY mode.
  • PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes up with hold.
  • PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes up with hold.
  • PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS External supply is sready.
  • PWR_FLAG_SCUEN : This flag indicates that the supply configuration update is enabled.
  • PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is above or equal to 1.2 V.
Note:
The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags are used for all H7 family lines. The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 dual core lines. The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 family except STM32H7Axxx and STM32H7Bxxx lines. The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and STM32H7Bxxx lines. The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742, STM32H750, STM32H7Axx and STM32H7Bxx lines. The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ, STM32H7BxxQ lines.
Return values:
The (__FLAG__) state (TRUE or FALSE).

Definition at line 408 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), and HAL_PWREx_EnableUSBReg().

#define __HAL_PWR_GET_WAKEUPFLAG ( __FLAG__ ) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)

Check PWR wake up flags are set or not.

Parameters:
__FLAG__,: specifies the wake up flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
  • PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
  • PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
  • PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
  • PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
  • PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
Return values:
The (__FLAG__) state (TRUE or FALSE).

Definition at line 454 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI flag.

Return values:
None.

Definition at line 616 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

Disable event on PVD EXTI Line 16.

Return values:
None.

Definition at line 544 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Falling Interrupt Trigger.

Return values:
None.

Definition at line 576 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD EXTI Line 16.

Return values:
None.

Definition at line 516 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Rising Interrupt Trigger.

Return values:
None.

Definition at line 564 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
} while(0);

Disable the PVD Rising & Falling Interrupt Trigger.

Return values:
None.

Definition at line 592 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

Enable event on PVD EXTI Line 16.

Return values:
None.

Definition at line 530 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Falling Interrupt Trigger.

Return values:
None.

Definition at line 570 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD EXTI Line 16.

Return values:
None.

Definition at line 502 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Rising Interrupt Trigger.

Return values:
None.

Definition at line 558 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
} while(0);

Enable the PVD Rising & Falling Interrupt Trigger.

Return values:
None.

Definition at line 582 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generates a Software interrupt on PVD EXTI line.

Return values:
None.

Definition at line 630 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)

Check whether the specified PVD EXTI interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 602 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                                           \
      __IO uint32_t tmpreg = 0x00;                                             \
      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
      /* Delay after setting the voltage scaling */                            \
      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
      UNUSED(tmpreg);                                                          \
} while(0)

Configure the main internal regulator output voltage.

Parameters:
__REGULATOR__ : Specifies the regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheet for more details). This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output Scale 0 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output Scale 1 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output Scale 2 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output Scale 3 mode.
Note:
For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, configuring Voltage Scale 0 is only possible when Vcore is supplied from LDO (Low DropOut). The SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale 0 using __HAL_PWR_VOLTAGESCALING_CONFIG(). Transition to Voltage Scale 0 is only possible when the system is already in Voltage Scale 1. Transition from Voltage Scale 0 is only possible to Voltage Scale 1 then once in Voltage Scale 1 it is possible to switch to another voltage scale. After each regulator voltage setting, wait on VOSRDY flag to be set using macro __HAL_PWR_GET_FLAG(). To enter low power mode , and if current regulator voltage is Voltage Scale 0 then first switch to Voltage Scale 1 before entering low power mode.
Return values:
None.

Definition at line 249 of file stm32h7xx_hal_pwr.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Constants

Defines

#define | PVD_MODE_IT (0x00010000U)
#define | PVD_MODE_EVT (0x00020000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)
#define | PVD_RISING_FALLING_EDGE (0x00000003U)

Define Documentation

#define PVD_FALLING_EDGE (0x00000002U)

Definition at line 177 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT (0x00020000U)

Definition at line 173 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT (0x00010000U)

Definition at line 172 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE (0x00000001U)

Definition at line 176 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_FALLING_EDGE (0x00000003U)

Definition at line 178 of file stm32h7xx_hal_pwr.c.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR PVD EXTI Line

Defines
PWR PVD EXTI Line
PWR Private Constants

Defines

#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16

Define Documentation

#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 699 of file stm32h7xx_hal_pwr.h.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Private macros to check input parameters

Defines
PWR Private macros to check input parameters
PWR Private Macros

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
                                 ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 717 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
                               ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 727 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 736 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_EnterSTOP2Mode(), and HAL_PWREx_EnterSTOPMode().

#define IS_PWR_REGULATOR_VOLTAGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))

Definition at line 748 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_SLEEP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 740 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_STOPENTRY_WFI) ||\
                                  ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 744 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode(), HAL_PWREx_EnterSTOP2Mode(), and HAL_PWREx_EnterSTOPMode().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Power Supply Control Functions

Functions
Power Supply Control Functions
PWREx Exported Functions

Power supply control functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.

Detailed Description

Power supply control functions.

 ===============================================================================
                  ##### Power supply control functions #####
 ===============================================================================
    [..]
   (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
       above the POR threshold level, the voltage regulator is enabled in the
       default supply configuration:
      (+) The Voltage converter output level is set at 1V0 in accordance with
          the VOS3 level configured in PWR (D3/SRD) domain control register
          (PWR_D3CR/PWR_SRDCR).
      (+) The system is kept in reset mode as long as VCORE is not ok.
      (+) Once VCORE is ok, the system is taken out of reset and the HSI
          oscillator is enabled.
      (+) Once the oscillator is stable, the system is initialized: Flash memory
          and option bytes are loaded and the CPU starts in Run* mode.
      (+) The software shall then initialize the system including supply
          configuration programming using the HAL_PWREx_ConfigSupply().
      (+) Once the supply configuration has been configured, the
          HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
          control status register 1 (PWR_CSR1) to guarantee a valid voltage
          levels:
       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
            system is in limited Run* mode, write accesses to the RAMs are not
            permitted and VOS shall not be changed.
       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
            is in normal Run mode, write accesses to RAMs are allowed and VOS
            can be changed.

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ConfigSupply ( uint32_t SupplySource )

Configure the system Power Supply.

Parameters:
SupplySource : Specifies the Power Supply source to set after a system startup. This parameter can be one of the following values :
  • PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power Domains. The LDO is Bypassed.
  • PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies the LDO. The Vcore Power Domains are supplied from the LDO.
  • PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies the LDO. The Vcore Power Domains are supplied from the LDO.
  • PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output supplies external circuits and the LDO. The Vcore Power Domains are supplied from the LDO.
  • PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output supplies external circuits and the LDO. The Vcore Power Domains are supplied from the LDO.
  • PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies external circuits. The LDO is Bypassed. The Vcore Power Domains are supplied from external source.
  • PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies external circuits. The LDO is Bypassed. The Vcore Power Domains are supplied from external source.
  • PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains. The SMPS regulator is Bypassed.
  • PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are Bypassed. The Vcore Power Domains are supplied from external source.
Note:
The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all H7 lines. The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS regulator.
Return values:
HAL status.

Definition at line 309 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, assert_param, HAL_GetTick(), IS_PWR_SUPPLY, PWR_FLAG_ACTVOSRDY, PWR_FLAG_SETTING_DELAY, PWR_FLAG_SMPSEXTRDY, PWR_SMPS_1V8_SUPPLIES_EXT, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, PWR_SMPS_2V5_SUPPLIES_EXT, PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, and PWR_SUPPLY_CONFIG_MASK.

HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage in STOP mode.

Parameters:
VoltageScaling : Specifies the regulator output voltage when the system enters Stop mode to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range 3 mode.
  • PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range 4 mode.
  • PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range 5 mode.
Note:
The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator in Low-power (LP) mode to further reduce power consumption. When preselecting SVOS3, the use of the voltage regulator low-power mode (LP) can be selected by LPDS register bit.
The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from system Stop mode.
Return values:
HAL Status.

Definition at line 527 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_STOP_MODE_REGULATOR_VOLTAGE.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage.

Note:
For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines, configuring Voltage Scale 0 is only possible when Vcore is supplied from LDO (Low DropOut). The SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale 0.
Parameters:
VoltageScaling : Specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values :
  • PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output Scale 0 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output range 1 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output range 2 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output range 3 mode.
Return values:
HAL Status

Definition at line 407 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, assert_param, HAL_GetTick(), IS_PWR_REGULATOR_VOLTAGE, PWR_FLAG_ACTVOSRDY, PWR_FLAG_SETTING_DELAY, PWR_REGULATOR_VOLTAGE_SCALE0, and PWR_REGULATOR_VOLTAGE_SCALE1.

uint32_t HAL_PWREx_GetStopModeVoltageRange ( void )

Get the main internal regulator output voltage in STOP mode.

Return values:
The actual applied VOS selection.

Definition at line 542 of file stm32h7xx_hal_pwr_ex.c.

uint32_t HAL_PWREx_GetSupplyConfig ( void )

Get the power supply configuration.

Return values:
The supply configuration.

Definition at line 381 of file stm32h7xx_hal_pwr_ex.c.

References PWR_SUPPLY_CONFIG_MASK.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Get the main internal regulator output voltage.

Reflecting the last VOS value applied to the PMU.

Return values:
The current applied VOS selection.

Definition at line 501 of file stm32h7xx_hal_pwr_ex.c.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Low Power Control Functions

Functions
Low Power Control Functions
PWREx Exported Functions

Low power control functions. More...

Functions

void | HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode with main domain in DSTOP2.
void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_ClearPendingEvent (void)
Clear pending event.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3/SRD Domain state when the System in low power mode.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
Enable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
Disable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin pending flags.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin pending flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.

Detailed Description

Low power control functions.

 ===============================================================================
                     ##### Low power control functions #####
 ===============================================================================

    *** Domains Low Power modes configuration ***
    =============================================
    [..]
      This section provides the extended low power mode control APIs.
      The system presents 3 principles domains (D1, D2 and D3) that can be
      operated in low-power modes (DSTOP or DSTANDBY mode):

      (+) DSTOP mode to enters a domain to STOP mode:
       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
            subsystem is in CSTOP mode and has allocated peripheral in the
            domain.
            In DSTOP mode the domain bus matrix clock is stopped.
       (++) The system enters STOP mode using one of the following scenarios:
        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
              enter DSTOP mode.
        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
              enter DSTOP mode.
        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
              enter DSTOP mode.
        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
              enters DSTOP mode.
        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
              enters DSTOP mode.
        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
              enters DSTOP mode.
        (+++) D1, D2 and D3 domains enter DSTOP mode.
       (++) When the system enters STOP mode, the clocks are stopped and the
            regulator is running in main or low power mode.
       (++) D3 domain can be kept in Run mode regardless of the CPU status when
            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.

      (+) DSTANDBY mode to enters a domain to STANDBY mode:
       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
            register (PWR_CPUCR) for the Dn domain selects Standby mode.
       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
            DSTANDBY mode. Consequently the VCORE supply regulator is powered
            off.

   *** DSTOP mode ***
   ==================
    [..]
      In DStop mode the domain bus matrix clock is stopped.
      The Flash memory can enter low-power Stop mode when it is enabled through
      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
      restart time and low power consumption.
    [..]
      In DStop mode domain peripherals using the LSI or LSE clock and
      peripherals having a kernel clock request are still able to operate.
    [..]
      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
      function in order to clean the D-Cache and guarantee the data integrity
      for the SRAM memories.

      (+) Entry:
         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
         STOPEntry, Domain) function with:
         (++) Regulator:
          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
         (++) STOPEntry:
          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
         (++) Domain:
          (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
          (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.

      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** DSTANDBY mode ***
   =====================
    [..]
      In DStandby mode:
        (+) The domain bus matrix clock is stopped.
        (+) The domain is powered down and the domain RAM and register contents
            are lost.
    [..]
      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
      function in order to clean the D-Cache and guarantee the data integrity
      for the SRAM memories.

      (+) Entry:
         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
         (Domain) function with:
       (++) Domain:
        (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
        (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.

      (+) Exit:
        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
        wakeup, tamper event, time stamp event, external reset in NRST pin,
        IWDG reset.

   *** Keep D3/SRD in RUN mode ***
   ===============================
    [..]
      D3/SRD domain can be kept in Run mode regardless of the CPU status when
      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
      with :
       (+) D3State:
        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
                                  mode.
        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
                                 of CPU subsystem mode.

    *** FLASH Power Down configuration ****
    =======================================
    [..]
      By setting the FLPS bit in the PWR_CR1 register using the
      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
      power down mode when the device enters STOP mode. When the Flash memory is
      in power down mode, an additional startup delay is incurred when waking up
      from STOP mode.

    *** Wakeup Pins configuration ****
    ===================================
    [..]
      Wakeup pins allow the system to exit from Standby mode. The configuration
      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
      function with:
       (+) sPinParams: structure to enable and configure a wakeup pin:
        (++) WakeUpPin: Wakeup pin to be enabled.
        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
    [..]
      The wakeup pins are internally connected to the EXTI lines [55-60] to
      generate an interrupt if enabled. The EXTI lines configuration is done by
      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
      file.
    [..]
      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
      cleared and the appropriate user callback will be called. The user can add
      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.

Function Documentation

void HAL_PWREx_ClearPendingEvent ( void )

Clear pending event.

Note:
This API clears the pending event in order to enter a given CPU to CSLEEP or CSTOP. It should be called just before APIs performing enter low power mode using Wait For Event request.
Return values:
None.

Definition at line 908 of file stm32h7xx_hal_pwr_ex.c.

References CM7_CPUID, and HAL_GetCurrentCPUID().

HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag ( uint32_t WakeUpFlag )

Clear the Wake-Up pin pending flag.

Parameters:
WakeUpFlag,: Specifies the Wake-Up PIN flag to clear. This parameter can be one of the following values:
  • PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
  • PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
  • PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PC1.
  • PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
  • PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI8.
  • PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PI11.
  • PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from all wake up pins.
Return values:
HAL status.

Definition at line 1355 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_FLAG.

void HAL_PWREx_ConfigD3Domain ( uint32_t D3State )

Configure the D3/SRD Domain state when the System in low power mode.

Parameters:
D3State : Specifies the D3/SRD state. This parameter can be one of the following values :
  • PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep CPU sub-system low power mode.
  • PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode regardless of the CPU sub-system low power mode.
Return values:
None

Definition at line 1048 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_D3_STATE.

void HAL_PWREx_DisableFlashPowerDown ( void )

Disable the Flash Power Down in Stop mode.

Note:
When Flash Power Down is disabled the Flash memory is kept on normal mode when D1/SRD domain is in DStop mode. This feature allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode.
Return values:
None.

Definition at line 1193 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableMemoryShutOff ( uint32_t MemoryBlock )

Disable memory block shut-off in DStop or DStop2 modes.

Parameters:
MemoryBlock : Specifies the memory block to keep content during DStop or DStop2 mode. This parameter can be one of the following values:
  • PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
  • PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and FDCAN memories.
  • PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
  • PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
  • PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
  • PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
  • PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
  • PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
  • PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
Return values:
None.

Definition at line 1248 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_MEMORY_BLOCK.

void HAL_PWREx_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the Wake-up PINx functionality.

Parameters:
WakeUpPin : Specifies the Wake-Up pin to be disabled. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN.
  • PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN.
  • PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN.
  • PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
  • PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
  • PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN.
Return values:
None

Definition at line 1309 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWREx_EnableFlashPowerDown ( void )

Enable the Flash Power Down in Stop mode.

Note:
When Flash Power Down is enabled the Flash memory enters low-power mode when D1/SRD domain is in DStop mode. This feature allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode.
Return values:
None.

Definition at line 1179 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableMemoryShutOff ( uint32_t MemoryBlock )

Enable memory block shut-off in DStop or DStop2 modes.

Note:
In DStop or DStop2 mode, the content of the memory blocks is maintained. Further power optimization can be obtained by switching off some memory blocks. This optimization implies loss of the memory content. The user can select which memory is discarded during STOP mode by means of xxSO bits.
Parameters:
MemoryBlock : Specifies the memory block to shut-off during DStop or DStop2 mode. This parameter can be one of the following values:
  • PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
  • PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and FDCAN memories.
  • PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
  • PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
  • PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
  • PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
  • PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
  • PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
  • PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
Return values:
None.

Definition at line 1222 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_MEMORY_BLOCK.

void HAL_PWREx_EnableWakeUpPin ( PWREx_WakeupPinTypeDef * sPinParams )

Enable the Wake-up PINx functionality.

Parameters:
sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that contains the configuration information for the wake-up Pin.
Note:
For dual core devices, please ensure to configure the EXTI lines for the different Cortex-Mx. All combination are allowed: wake up only Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
Return values:
None.

Definition at line 1269 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_WAKEUP_PIN, IS_PWR_WAKEUP_PIN_POLARITY, IS_PWR_WAKEUP_PIN_PULL, PWREx_WakeupPinTypeDef::PinPolarity, PWREx_WakeupPinTypeDef::PinPull, PWR_EXTI_WAKEUP_PINS_MASK, PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET, and PWREx_WakeupPinTypeDef::WakeUpPin.

void HAL_PWREx_EnterSTANDBYMode ( uint32_t Domain )

Enter a Domain to DSTANDBY mode.

Note:
This API gives flexibility to manage independently each domain STANDBY mode. For dual core lines, this API should be executed with the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When it is executed by all available Cortex-Mx, the system enter STANDBY mode. For single core lines, calling this API with D1/SRD the selected domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain select Standby mode. When the system enters Standby mode, the voltage regulator is disabled.
When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn bit to select Stop mode, the domain remains in DStandby mode. The domain will only exit DStandby when the CPU allocates a peripheral in the domain.
The system D3/SRD domain enters Standby mode only when the D1 and D2 domain are in DStandby.
Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
Parameters:
Domain : Specifies the Domain to enter to STANDBY mode. This parameter can be one of the following values:
  • PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
  • PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
  • PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
Return values:
None

Definition at line 955 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, CM7_CPUID, HAL_GetCurrentCPUID(), IS_PWR_DOMAIN, and PWR_D1_DOMAIN.

void HAL_PWREx_EnterSTOP2Mode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter the system to STOP mode with main domain in DSTOP2.

Note:
In STOP mode, the domain bus matrix clock is stalled.
In STOP mode, memories and registers are maintained and peripherals in CPU domain are no longer operational.
All clocks in the VCORE domain are stopped, the PLL, the HSI and the HSE oscillators are disabled. Only Peripherals that have wakeup capability can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only to the peripheral requesting it.
When exiting STOP mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set.
Parameters:
Regulator : Specifies the regulator state in STOP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
  • PWR_LOWPOWERREGULATOR_ON : STOP mode with low power regulator ON.
STOPEntry : Specifies if STOP mode in entered with WFI or WFE intrinsic instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
  • PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
Return values:
None.

Definition at line 728 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

void HAL_PWREx_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry,
 |  | uint32_t | Domain
 | ) |  |

Enter a Domain to DSTOP mode.

Note:
This API gives flexibility to manage independently each domain STOP mode. For dual core lines, this API should be executed with the corresponding Cortex-Mx to enter domain to DSTOP mode. When it is executed by all available Cortex-Mx, the system enter to STOP mode. For single core lines, calling this API with domain parameter set to PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the CPUCR_RUN_D3 is cleared.
In DStop mode the domain bus matrix clock is stopped.
The system D3/SRD domain enter Stop mode only when the CPU subsystem is in CStop mode, the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for any domain request Stop.
Before entering DSTOP mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the peripherals that have a kernel clock request to select HSI or CSI as source, are still able to operate.
Parameters:
Regulator : Specifies the regulator state in STOP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
  • PWR_LOWPOWERREGULATOR_ON : STOP mode with low power regulator ON.
STOPEntry : Specifies if STOP mode in entered with WFI or WFE intrinsic instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
  • PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
Domain : Specifies the Domain to enter in DSTOP mode. This parameter can be one of the following values:
  • PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
  • PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
  • PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
Return values:
None.

Definition at line 805 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, CM7_CPUID, HAL_GetCurrentCPUID(), IS_PWR_DOMAIN, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR_D1_DOMAIN, and PWR_STOPENTRY_WFI.

uint32_t HAL_PWREx_GetWakeupFlag ( uint32_t WakeUpFlag )

Get the Wake-Up Pin pending flags.

Parameters:
WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. This parameter can be one of the following values:
  • PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0.
  • PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2.
  • PWR_WAKEUP_FLAG3 : Get wakeup event received from PC1.
  • PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13.
  • PWR_WAKEUP_FLAG5 : Get wakeup event received from PI8.
  • PWR_WAKEUP_FLAG6 : Get wakeup event received from PI11.
  • PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all wake up pins.
Return values:
The Wake-Up pin flag.

Definition at line 1332 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_FLAG.

void HAL_PWREx_WAKEUP_PIN_IRQHandler ( void )

This function handles the PWR WAKEUP PIN interrupt request.

Note:
This API should be called under the WAKEUP_PIN_IRQHandler().
Return values:
None.

Definition at line 1377 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_CLEAR_WAKEUPFLAG, HAL_PWREx_WKUP1_Callback(), HAL_PWREx_WKUP2_Callback(), HAL_PWREx_WKUP3_Callback(), HAL_PWREx_WKUP4_Callback(), HAL_PWREx_WKUP5_Callback(), HAL_PWREx_WKUP6_Callback(), PWR_FLAG_WKUP1, PWR_FLAG_WKUP2, PWR_FLAG_WKUP3, PWR_FLAG_WKUP4, PWR_FLAG_WKUP5, and PWR_FLAG_WKUP6.

void HAL_PWREx_WKUP1_Callback ( void )

PWR WKUP1 interrupt callback.

Return values:
None.

Definition at line 1434 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP2_Callback ( void )

PWR WKUP2 interrupt callback.

Return values:
None.

Definition at line 1445 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP3_Callback ( void )

PWR WKUP3 interrupt callback.

Return values:
None.

Definition at line 1456 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP4_Callback ( void )

PWR WKUP4 interrupt callback.

Return values:
None.

Definition at line 1467 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP5_Callback ( void )

PWR WKUP5 interrupt callback.

Return values:
None.

Definition at line 1478 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP6_Callback ( void )

PWR WKUP6 interrupt callback.

Return values:
None.

Definition at line 1489 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripherals control functions

Functions
Peripherals control functions
PWREx Exported Functions

Peripherals control functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.
void | HAL_PWREx_EnableAnalogBooster (void)
Enable the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2V7.
void | HAL_PWREx_DisableAnalogBooster (void)
Disable the analog booster.

Detailed Description

Peripherals control functions.

 ===============================================================================
                 ##### Peripherals control functions #####
 ===============================================================================

    *** Main and Backup Regulators configuration ***
    ================================================
    [..]
      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
          from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
          content is retained even in Standby or VBAT mode when the low power
          backup regulator is enabled. It can be considered as an internal
          EEPROM when VBAT is always present. You can use the
          HAL_PWREx_EnableBkUpReg() function to enable the low power backup
          regulator.
      (+) When the backup domain is supplied by VDD (analog switch connected to
          VDD) the backup SRAM is powered from VDD which replaces the VBAT power
          supply to save battery life.
      (+) The backup SRAM is not mass erased by a tamper event. It is read
          protected to prevent confidential data, such as cryptographic private
          key, from being accessed. The backup SRAM can be erased only through
          the Flash interface when a protection level change from level 1 to
          level 0 is requested.
      -@- Refer to the description of Read protection (RDP) in the Flash
          programming manual.
      (+) The main internal regulator can be configured to have a tradeoff
          between performance and power consumption when the device does not
          operate at the maximum frequency. This is done through
          HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
          bit in PWR_D3CR register.
      (+) The main internal regulator can be configured to operate in Low Power
          mode when the system enters STOP mode to further reduce power
          consumption.
          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
          function which configure the SVOS bit in PWR_CR1 register.
          The selected SVOS4 and SVOS5 levels add an additional startup delay
          when exiting from system Stop mode.
    -@- Refer to the product datasheets for more details.

    *** USB Regulator configuration ***
    ===================================
    [..]
      (+) The USB transceivers are supplied from a dedicated VDD33USB supply
          that can be provided either by the integrated USB regulator, or by an
          external USB supply.
      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
          VDD33USB is then provided from the USB regulator.
      (+) When the USB regulator is enabled, the VDD33USB supply level detector
          shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
          function.
      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
          function and VDD33USB can be provided from an external supply. In this
          case VDD33USB and VDD50USB shall be connected together.

    *** VBAT battery charging ***
    =============================
    [..]
      (+) When VDD is present, the external battery connected to VBAT can be
          charged through an internal resistance. VBAT charging can be performed
          either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
          (ResistorValue) function with:
       (++) ResistorValue:
        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
          function.

Function Documentation

void HAL_PWREx_DisableAnalogBooster ( void )

Disable the analog booster.

Return values:
None.

Definition at line 1751 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableBatteryCharging ( void )

Disable the Battery charging.

Return values:
None.

Definition at line 1724 of file stm32h7xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg ( void )

Disable the Backup Regulator.

Return values:
HAL status.

Definition at line 1604 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_BRR, and PWR_FLAG_SETTING_DELAY.

HAL_StatusTypeDef HAL_PWREx_DisableUSBReg ( void )

Disable the USB Regulator.

Return values:
HAL status.

Definition at line 1656 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_SETTING_DELAY, and PWR_FLAG_USB33RDY.

void HAL_PWREx_DisableUSBVoltageDetector ( void )

Disable the USB voltage level detector.

Return values:
None.

Definition at line 1692 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableAnalogBooster ( void )

Enable the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2V7.

Note:
The VDD supply voltage can be monitored through the PVD and the PLS field bits.
Return values:
None.

Definition at line 1738 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorValue )

Enable the Battery charging.

Note:
When VDD is present, charge the external battery through an internal resistor.
Parameters:
ResistorValue : Specifies the charging resistor. This parameter can be one of the following values :
  • PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
Return values:
None.

Definition at line 1708 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg ( void )

Enable the Backup Regulator.

Return values:
HAL status.

Definition at line 1578 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_BRR, and PWR_FLAG_SETTING_DELAY.

HAL_StatusTypeDef HAL_PWREx_EnableUSBReg ( void )

Enable the USB Regulator.

Return values:
HAL status.

Definition at line 1630 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_SETTING_DELAY, and PWR_FLAG_USB33RDY.

void HAL_PWREx_EnableUSBVoltageDetector ( void )

Enable the USB voltage level detector.

Return values:
None.

Definition at line 1682 of file stm32h7xx_hal_pwr_ex.c.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Power Monitoring functions

Functions
Power Monitoring functions
PWREx Exported Functions

Power Monitoring functions. More...

Functions

void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the thresholds.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the thresholds.
PWREx_MMC_VoltageLevel | HAL_PWREx_GetMMCVoltage (void)
Get the VDDMMC voltage level.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the event mode and the voltage threshold detected by the Analog Voltage Detector (AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector (AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Power Monitoring functions.

 ===============================================================================
                 ##### Power Monitoring functions #####
 ===============================================================================

    *** VBAT and Temperature supervision ***
    ========================================
    [..]
      (+) The VBAT battery voltage supply can be monitored by comparing it with
          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
          in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
          lower than the threshold.
      (+) The temperature can be monitored by comparing it with two threshold
          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
          control register 2 (PWR_CR2), indicate whether the device temperature
          is higher or lower than the threshold.
      (+) The VBAT and the temperature monitoring is enabled by
          HAL_PWREx_EnableMonitoring() function and disabled by
          HAL_PWREx_DisableMonitoring() function.
      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
          level which can be :
          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.

    *** AVD configuration ***
    =========================
    [..]
      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
          register).
      (+) A AVDO flag is available to indicate if VDDA is higher or lower
          than the AVD threshold. This event is internally connected to the EXTI
          line 16 to generate an interrupt if enabled.
          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
      (+) The AVD is stopped in System Standby mode.

Function Documentation

void HAL_PWREx_AVDCallback ( void )

PWR AVD interrupt callback.

Return values:
None.

Definition at line 2068 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

void HAL_PWREx_ConfigAVD ( PWREx_AVDTypeDef * sConfigAVD )

Configure the event mode and the voltage threshold detected by the Analog Voltage Detector (AVD).

Parameters:
sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains the configuration information for the AVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
For dual core devices, please ensure to configure the EXTI lines for the different Cortex-Mx through PWR_Exported_Macro provided by this driver. All combination are allowed: wake up only Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
Return values:
None.

Definition at line 1929 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_AVD_EXTI_DISABLE_EVENT, __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_AVD_EXTI_DISABLE_IT, __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_AVD_EXTI_ENABLE_EVENT, __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_AVD_EXTI_ENABLE_IT, __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE, assert_param, AVD_FALLING_EDGE, AVD_MODE_EVT, AVD_MODE_IT, AVD_RISING_EDGE, PWREx_AVDTypeDef::AVDLevel, IS_PWR_AVD_LEVEL, IS_PWR_AVD_MODE, and PWREx_AVDTypeDef::Mode.

void HAL_PWREx_DisableAVD ( void )

Disable the Analog Voltage Detector(AVD).

Return values:
None.

Definition at line 1988 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableMonitoring ( void )

Disable the VBAT and temperature monitoring.

Return values:
HAL status.

Definition at line 1824 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableAVD ( void )

Enable the Analog Voltage Detector (AVD).

Return values:
None.

Definition at line 1978 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableMonitoring ( void )

Enable the VBAT and temperature monitoring.

Return values:
HAL status.

Definition at line 1814 of file stm32h7xx_hal_pwr_ex.c.

PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage ( void )

Get the VDDMMC voltage level.

Return values:
The VDDMMC voltage level.

Definition at line 1897 of file stm32h7xx_hal_pwr_ex.c.

References PWR_MMC_VOLTAGE_BELOW_1V2, and PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2.

uint32_t HAL_PWREx_GetTemperatureLevel ( void )

Indicate whether the junction temperature is between, above or below the thresholds.

Return values:
Temperature level.

Definition at line 1835 of file stm32h7xx_hal_pwr_ex.c.

References PWR_TEMP_ABOVE_HIGH_THRESHOLD, PWR_TEMP_BELOW_LOW_THRESHOLD, and PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.

uint32_t HAL_PWREx_GetVBATLevel ( void )

Indicate whether the Battery voltage level is between, above or below the thresholds.

Return values:
VBAT level.

Definition at line 1866 of file stm32h7xx_hal_pwr_ex.c.

References PWR_VBAT_ABOVE_HIGH_THRESHOLD, PWR_VBAT_BELOW_LOW_THRESHOLD, and PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.

void HAL_PWREx_PVD_AVD_IRQHandler ( void )

This function handles the PWR PVD/AVD interrupt request.

Note:
This API should be called under the PVD_AVD_IRQHandler().
Return values:
None

Definition at line 1999 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_AVD_EXTI_CLEAR_FLAG, __HAL_PWR_AVD_EXTI_GET_FLAG, __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, CM7_CPUID, HAL_GetCurrentCPUID(), HAL_PWR_PVDCallback(), and HAL_PWREx_AVDCallback().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Exported Types

Data Structures | Enumerations
PWREx Exported Types
PWREx

Data Structures

struct | PWREx_AVDTypeDef
PWREx AVD configuration structure definition. More...
struct | PWREx_WakeupPinTypeDef
PWREx Wakeup pin configuration structure definition. More...

Enumerations

enum | PWREx_MMC_VoltageLevel { PWR_MMC_VOLTAGE_BELOW_1V2, PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 }
PWR VDDMMC voltage level enum definition. More...

Enumeration Type Documentation

enum PWREx_MMC_VoltageLevel

PWR VDDMMC voltage level enum definition.

Enumerator:
PWR_MMC_VOLTAGE_BELOW_1V2

VDDMMC is below 1V2

PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2

VDDMMC is above or equal 1V2

Definition at line 84 of file stm32h7xx_hal_pwr_ex.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx_AVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWREx_AVDTypeDef Struct Reference
PWREx Exported Types

PWREx AVD configuration structure definition. More...

#include <stm32h7xx_hal_pwr_ex.h>

Data Fields

uint32_t | AVDLevel
uint32_t | Mode

Detailed Description

PWREx AVD configuration structure definition.

Definition at line 46 of file stm32h7xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWREx_AVDTypeDef::AVDLevel

AVDLevel : Specifies the AVD detection level. This parameter can be a value of PWREx AVD detection level

Definition at line 48 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

uint32_t PWREx_AVDTypeDef::Mode

Mode : Specifies the EXTI operating mode for the AVD event. This parameter can be a value of PWREx AVD Mode.

Definition at line 53 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx_WakeupPinTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWREx_WakeupPinTypeDef Struct Reference
PWREx Exported Types

PWREx Wakeup pin configuration structure definition. More...

#include <stm32h7xx_hal_pwr_ex.h>

Data Fields

uint32_t | WakeUpPin
uint32_t | PinPolarity
uint32_t | PinPull

Detailed Description

PWREx Wakeup pin configuration structure definition.

Definition at line 62 of file stm32h7xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWREx_WakeupPinTypeDef::PinPolarity

PinPolarity: Specifies the Wake-Up pin polarity. This parameter can be a value of PWREx Pin Polarity configuration

Definition at line 69 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

uint32_t PWREx_WakeupPinTypeDef::PinPull

PinPull: Specifies the Wake-Up pin pull. This parameter can be a value of PWREx Pin Pull configuration

Definition at line 74 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

uint32_t PWREx_WakeupPinTypeDef::WakeUpPin

WakeUpPin: Specifies the Wake-Up pin to be enabled. This parameter can be a value of PWREx Wake-Up Pins

Definition at line 64 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Wake-Up Pins

Defines
PWREx Wake-Up Pins
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
#define | PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#define | PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#define | PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#define | PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define | PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
#define | PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
#define | PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
#define | PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
#define | PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
#define | PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
#define | PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
#define | PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
#define | PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
#define | PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
#define | PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
#define | PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
#define | PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1

Definition at line 109 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1

Definition at line 117 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)

Definition at line 125 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2

Definition at line 108 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2

Definition at line 116 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)

Definition at line 124 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3

Definition at line 107 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3

Definition at line 115 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)

Definition at line 123 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4

Definition at line 106 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4

Definition at line 114 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)

Definition at line 122 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5

Definition at line 105 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5

Definition at line 113 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)

Definition at line 121 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6

Definition at line 104 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6

Definition at line 112 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)

Definition at line 120 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Pin Polarity configuration

Defines
PWREx Pin Polarity configuration
PWREx Exported Constants

Defines

#define | PWR_PIN_POLARITY_HIGH (0x00000000U)
#define | PWR_PIN_POLARITY_LOW (0x00000001U)

Define Documentation

#define PWR_PIN_POLARITY_HIGH (0x00000000U)

Definition at line 133 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_POLARITY_LOW (0x00000001U)

Definition at line 134 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Pin Pull configuration

Defines
PWREx Pin Pull configuration
PWREx Exported Constants

Defines

#define | PWR_PIN_NO_PULL (0x00000000U)
#define | PWR_PIN_PULL_UP (0x00000001U)
#define | PWR_PIN_PULL_DOWN (0x00000002U)

Define Documentation

#define PWR_PIN_NO_PULL (0x00000000U)

Definition at line 142 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_PULL_DOWN (0x00000002U)

Definition at line 144 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_PULL_UP (0x00000001U)

Definition at line 143 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Wakeup Pins Flags.

Defines
PWREx Wakeup Pins Flags.
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1
#define | PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2
#define | PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3
#define | PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4
#define | PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5
#define | PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6
#define | PWR_WAKEUP_FLAG_ALL

Define Documentation

#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1

Wakeup flag on pin 1

Definition at line 152 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2

Wakeup flag on pin 2

Definition at line 153 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3

Wakeup flag on pin 3

Definition at line 154 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4

Wakeup flag on pin 4

Definition at line 155 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5

Wakeup flag on pin 5

Definition at line 156 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6

Wakeup flag on pin 6

Definition at line 157 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG_ALL
Value:
(PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)

Definition at line 158 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Domains definition

Defines
PWREx Domains definition
PWREx Exported Constants

Defines

#define | PWR_D1_DOMAIN (0x00000000U)
#define | PWR_D3_DOMAIN (0x00000002U)

Define Documentation

#define PWR_D1_DOMAIN (0x00000000U)

Definition at line 179 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterSTANDBYMode(), and HAL_PWREx_EnterSTOPMode().

#define PWR_D3_DOMAIN (0x00000002U)

Definition at line 183 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Domain Flags definition

Defines
PWREx Domain Flags definition
PWREx Exported Constants

Defines

#define PWR_CPU_FLAGS (0x00000000U)

Define Documentation

#define PWR_CPU_FLAGS (0x00000000U)

Definition at line 196 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx D3 Domain State

Defines
PWREx D3 Domain State
PWREx Exported Constants

Defines

#define | PWR_D3_DOMAIN_STOP (0x00000000U)
#define | PWR_D3_DOMAIN_RUN (0x00000800U)

Define Documentation

#define PWR_D3_DOMAIN_RUN (0x00000800U)

Definition at line 206 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_D3_DOMAIN_STOP (0x00000000U)

Definition at line 205 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Supply configuration

Defines
PWREx Supply configuration
PWREx Exported Constants

Defines

#define | PWR_LDO_SUPPLY PWR_CR3_LDOEN
#define | PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN
#define | PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS
#define | PWR_SUPPLY_CONFIG_MASK

Define Documentation

#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN

Core domains are suppplied from the SMPS only

Definition at line 217 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS

The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source

Definition at line 225 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_LDO_SUPPLY PWR_CR3_LDOEN

Core domains are suppplied from the LDO

Definition at line 215 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)

The SMPS 1.8V output supplies an external source which supplies the Core domains

Definition at line 222 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO

Definition at line 220 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 1.8V output supplies the LDO which supplies the Core domains

Definition at line 218 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)

The SMPS 2.5V output supplies an external source which supplies the Core domains

Definition at line 223 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO

Definition at line 221 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 2.5V output supplies the LDO which supplies the Core domains

Definition at line 219 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_SUPPLY_CONFIG_MASK
Value:
(PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)

Definition at line 228 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply(), and HAL_PWREx_GetSupplyConfig().

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STM32H7B3xQ HAL User Manual: PWREx AVD detection level

Defines
PWREx AVD detection level
PWREx Exported Constants

Defines

#define | PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Define Documentation

#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0

Definition at line 241 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1

Definition at line 242 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2

Definition at line 243 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Definition at line 244 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx AVD Mode

Defines
PWREx AVD Mode
PWREx Exported Constants

Defines

#define | PWR_AVD_MODE_NORMAL (0x00000000U)
#define | PWR_AVD_MODE_IT_RISING (0x00010001U)
#define | PWR_AVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_AVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_AVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Define Documentation

#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 257 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_EVENT_RISING (0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 256 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 258 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_FALLING (0x00010002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 254 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_RISING (0x00010001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 253 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 255 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_NORMAL (0x00000000U)

Basic mode is used

Definition at line 252 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Regulator Voltage Scale

Defines
PWREx Regulator Voltage Scale
PWREx Exported Constants

Defines

#define | PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define | PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define | PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Define Documentation

#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Definition at line 268 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)

Definition at line 267 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)

Definition at line 266 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWREx Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 277 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)

VBAT charging through a 5 kOhms resistor

Definition at line 276 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx VBAT Thresholds

Defines
PWREx VBAT Thresholds
PWREx Exported Constants

Defines

#define | PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define | PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define | PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH

Define Documentation

#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH

Definition at line 287 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL

Definition at line 286 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)

Definition at line 285 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

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STM32H7B3xQ HAL User Manual: PWREx Temperature Thresholds

Defines
PWREx Temperature Thresholds
PWREx Exported Constants

Defines

#define | PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define | PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define | PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH

Define Documentation

#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH

Definition at line 297 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL

Definition at line 296 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)

Definition at line 295 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

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STM32H7B3xQ HAL User Manual: PWREx AVD EXTI Line 16

Defines
PWREx AVD EXTI Line 16
PWREx Exported Constants

Defines

#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16

Define Documentation

#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16

External interrupt line 16 Connected to the AVD EXTI Line

Definition at line 304 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: Memory shut-off block selection

Defines
Memory shut-off block selection
PWREx Exported Constants

Defines

#define | PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO
#define | PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO
#define | PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO
#define | PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO
#define | PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO
#define | PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO
#define | PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO
#define | PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO
#define | PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO
#define | PWR_MEMORY_BLOCK_KEEP_ON 0U
#define | PWR_MEMORY_BLOCK_SHUT_OFF 1U

Define Documentation

#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO

GFXMMU and JPEG memories shut-off in DStop/DStop2 mode

Definition at line 316 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_MEMORY_BLOCK_KEEP_ON 0U

Memory content is kept in DStop or DStop2 mode

Definition at line 323 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_MEMORY_BLOCK_SHUT_OFF 1U

Memory content is lost in DStop or DStop2 mode

Definition at line 324 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO

AHB RAM1 shut-off in DStop/DStop2 mode

Definition at line 318 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO

AXI RAM1 shut-off in DStop/DStop2 mode

Definition at line 320 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO

AHB RAM2 shut-off in DStop/DStop2 mode

Definition at line 319 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO

AXI RAM2 shut-off in DStop/DStop2 mode

Definition at line 321 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO

AXI RAM3 shut-off in DStop/DStop2 mode

Definition at line 322 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO

SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode

Definition at line 314 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO

Instruction TCM and ETM memories shut-off in DStop/DStop2 mode

Definition at line 317 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO

High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode

Definition at line 315 of file stm32h7xx_hal_pwr_ex.h.

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STM32H7B3xQ HAL User Manual: PWREx Exported Macro

Defines
PWREx Exported Macro
PWREx

Defines

#define | __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
Enable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
Disable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
Enable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
Disable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the AVD Extended Interrupt Rising and Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the AVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
Check whether the specified AVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
Clear the AVD EXTI flag.
#define | __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
Generates a Software interrupt on AVD EXTI line.

Define Documentation

#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG ( ) SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)

Clear the AVD EXTI flag.

Return values:
None.

Definition at line 457 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)

Disable event on AVD EXTI Line 16.

Return values:
None.

Definition at line 385 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

Disable the AVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 417 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)

Disable the AVD EXTI Line 16.

Return values:
None.

Definition at line 357 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

Disable the AVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 405 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
} while(0);

Disable the AVD Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 433 of file stm32h7xx_hal_pwr_ex.h.

#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)

Enable event on AVD EXTI Line 16.

Return values:
None.

Definition at line 371 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

Enable the AVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 411 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)

Enable the AVD EXTI Line 16.

Return values:
None.

Definition at line 343 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

Enable the AVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 399 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
} while(0);

Enable the AVD Extended Interrupt Rising and Falling Trigger.

Return values:
None.

Definition at line 423 of file stm32h7xx_hal_pwr_ex.h.

#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)

Generates a Software interrupt on AVD EXTI line.

Return values:
None.

Definition at line 471 of file stm32h7xx_hal_pwr_ex.h.

#define __HAL_PWR_AVD_EXTI_GET_FLAG ( ) ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)

Check whether the specified AVD EXTI interrupt flag is set or not.

Return values:
EXTI AVD Line Status.

Definition at line 443 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Private macros to check input parameters

Defines
PWREx Private macros to check input parameters
PWREx Private Macros

Defines

#define | IS_PWR_SUPPLY(PWR_SOURCE)
#define | IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)
#define | IS_PWR_DOMAIN(DOMAIN)
#define | IS_D3_STATE(STATE)
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_WAKEUP_PIN_PULL(PULL)
#define | IS_PWR_WAKEUP_FLAG(FLAG)
#define | IS_PWR_AVD_LEVEL(LEVEL)
#define | IS_PWR_AVD_MODE(MODE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
#define | IS_PWR_MEMORY_BLOCK(BLOCK)

Define Documentation

#define IS_D3_STATE ( STATE )
Value:
(((STATE) == PWR_D3_DOMAIN_STOP) ||\
                            ((STATE) == PWR_D3_DOMAIN_RUN))

Definition at line 631 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigD3Domain().

#define IS_PWR_AVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_AVDLEVEL_0) ||\
                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
                                 ((LEVEL) == PWR_AVDLEVEL_3))

Definition at line 673 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define IS_PWR_AVD_MODE ( MODE )
Value:
(((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))

Definition at line 679 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define IS_PWR_BATTERY_RESISTOR_SELECT ( RESISTOR )
Value:
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 688 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_D1_CPU ( CPU ) ((CPU) == CM7_CPUID)

Definition at line 691 of file stm32h7xx_hal_pwr_ex.h.

#define IS_PWR_DOMAIN ( DOMAIN )
Value:
(((DOMAIN) == PWR_D1_DOMAIN) ||\
                               ((DOMAIN) == PWR_D3_DOMAIN))

Definition at line 626 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterSTANDBYMode(), and HAL_PWREx_EnterSTOPMode().

#define IS_PWR_MEMORY_BLOCK ( BLOCK )
Value:
(((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))

Definition at line 708 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableMemoryShutOff(), and HAL_PWREx_EnableMemoryShutOff().

#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))

Definition at line 616 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlStopModeVoltageScaling().

#define IS_PWR_SUPPLY ( PWR_SOURCE )
Value:
(((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))

Definition at line 600 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define IS_PWR_WAKEUP_FLAG ( FLAG )
Value:
(((FLAG) == PWR_WAKEUP_FLAG1) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))

Definition at line 664 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ClearWakeupFlag(), and HAL_PWREx_GetWakeupFlag().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1)      ||\
                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
                                ((PIN) == PWR_WAKEUP_PIN6_LOW))

Definition at line 635 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWREx_DisableWakeUpPin(), and HAL_PWREx_EnableWakeUpPin().

#define IS_PWR_WAKEUP_PIN_POLARITY ( POLARITY )
Value:
(((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))

Definition at line 655 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

#define IS_PWR_WAKEUP_PIN_PULL ( PULL )
Value:
(((PULL) == PWR_PIN_NO_PULL) ||\
                                      ((PULL) == PWR_PIN_PULL_UP) ||\
                                      ((PULL) == PWR_PIN_PULL_DOWN))

Definition at line 659 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Extended AVD Mode Mask

Defines
PWR Extended AVD Mode Mask
PWREx_Private_Constants

Defines

#define | AVD_MODE_IT (0x00010000U)
#define | AVD_MODE_EVT (0x00020000U)
#define | AVD_RISING_EDGE (0x00000001U)
#define | AVD_FALLING_EDGE (0x00000002U)
#define | AVD_RISING_FALLING_EDGE (0x00000003U)

Define Documentation

#define AVD_FALLING_EDGE (0x00000002U)

Definition at line 180 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_MODE_EVT (0x00020000U)

Definition at line 178 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_MODE_IT (0x00010000U)

Definition at line 177 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_RISING_EDGE (0x00000001U)

Definition at line 179 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_RISING_FALLING_EDGE (0x00000003U)

Definition at line 181 of file stm32h7xx_hal_pwr_ex.c.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Extended Flag Setting Time Out Value

Defines
PWR Extended Flag Setting Time Out Value
PWREx_Private_Constants

Defines

#define PWR_FLAG_SETTING_DELAY (1000U)

Define Documentation

#define PWR_FLAG_SETTING_DELAY (1000U)

Definition at line 189 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), and HAL_PWREx_EnableUSBReg().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Wake-Up Pins masks and offsets

Defines
PWREx Wake-Up Pins masks and offsets
PWREx_Private_Constants

Defines

#define | PWR_EXTI_WAKEUP_PINS_MASK
#define | PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)

Define Documentation

#define PWR_EXTI_WAKEUP_PINS_MASK
Value:
(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
                                    EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
                                    EXTI_IMR2_IM59 | EXTI_IMR2_IM60)

Definition at line 198 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_EnableWakeUpPin().

#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)

Definition at line 203 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_EnableWakeUpPin().

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Exported Types

Data Structures | Typedefs | Enumerations
RAMECC Exported Types
RAMECC

RAMECC Exported Types. More...

Data Structures

struct | __RAMECC_HandleTypeDef
RAMECC handle Structure definition. More...

Typedefs

typedef struct
__RAMECC_HandleTypeDef 		RAMECC_HandleTypeDef
RAMECC handle Structure definition.

Enumerations

enum | HAL_RAMECC_StateTypeDef { HAL_RAMECC_STATE_RESET = 0x00U, HAL_RAMECC_STATE_READY = 0x01U, HAL_RAMECC_STATE_BUSY = 0x02U, HAL_RAMECC_STATE_ERROR = 0x03U }
HAL RAMECC State structures definition. More...

Detailed Description

RAMECC Exported Types.

Typedef Documentation

typedef struct __RAMECC_HandleTypeDef RAMECC_HandleTypeDef

RAMECC handle Structure definition.

Enumeration Type Documentation

enum HAL_RAMECC_StateTypeDef

HAL RAMECC State structures definition.

Enumerator:
HAL_RAMECC_STATE_RESET

RAMECC not yet initialized or disabled

HAL_RAMECC_STATE_READY

RAMECC initialized and ready for use

HAL_RAMECC_STATE_BUSY

RAMECC process is ongoing

HAL_RAMECC_STATE_ERROR

RAMECC error state

Definition at line 49 of file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __RAMECC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RAMECC_HandleTypeDef Struct Reference
RAMECC Exported Types

RAMECC handle Structure definition. More...

#include <stm32h7xx_hal_ramecc.h>

Data Fields

RAMECC_MonitorTypeDef * | Instance
__IO HAL_RAMECC_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | DetectErrorCallback )(struct __RAMECC_HandleTypeDef *hramecc)

Detailed Description

RAMECC handle Structure definition.

Definition at line 62 of file stm32h7xx_hal_ramecc.h.

Field Documentation

void(* __RAMECC_HandleTypeDef::DetectErrorCallback)(struct __RAMECC_HandleTypeDef *hramecc)

RAMECC error detect callback

Definition at line 67 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), HAL_RAMECC_IRQHandler(), HAL_RAMECC_RegisterCallback(), and HAL_RAMECC_UnRegisterCallback().

__IO uint32_t __RAMECC_HandleTypeDef::ErrorCode

RAMECC Error Code

Definition at line 66 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), HAL_RAMECC_DisableNotification(), HAL_RAMECC_EnableNotification(), HAL_RAMECC_GetError(), HAL_RAMECC_Init(), HAL_RAMECC_RegisterCallback(), HAL_RAMECC_StartMonitor(), HAL_RAMECC_StopMonitor(), and HAL_RAMECC_UnRegisterCallback().

RAMECC_MonitorTypeDef* __RAMECC_HandleTypeDef::Instance

Register base address

Definition at line 64 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), HAL_RAMECC_DisableNotification(), HAL_RAMECC_EnableNotification(), HAL_RAMECC_GetFailingAddress(), HAL_RAMECC_GetFailingDataHigh(), HAL_RAMECC_GetFailingDataLow(), HAL_RAMECC_GetHammingErrorCode(), HAL_RAMECC_Init(), HAL_RAMECC_IRQHandler(), HAL_RAMECC_IsECCDoubleErrorDetected(), HAL_RAMECC_IsECCSingleErrorDetected(), HAL_RAMECC_RegisterCallback(), HAL_RAMECC_StartMonitor(), HAL_RAMECC_StopMonitor(), and HAL_RAMECC_UnRegisterCallback().

__IO HAL_RAMECC_StateTypeDef __RAMECC_HandleTypeDef::State

RAMECC state

Definition at line 65 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), HAL_RAMECC_DisableNotification(), HAL_RAMECC_EnableNotification(), HAL_RAMECC_GetState(), HAL_RAMECC_Init(), HAL_RAMECC_RegisterCallback(), HAL_RAMECC_StartMonitor(), HAL_RAMECC_StopMonitor(), and HAL_RAMECC_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ramecc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Error Codes

Defines
RAMECC Error Codes
RAMECC

Defines

#define | HAL_RAMECC_ERROR_NONE 0x00000000U
#define | HAL_RAMECC_ERROR_TIMEOUT 0x00000001U
#define | HAL_RAMECC_ERROR_BUSY 0x00000002U
#define | HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U

Define Documentation

#define HAL_RAMECC_ERROR_BUSY 0x00000002U

RAMECC Busy Error

Definition at line 82 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DisableNotification(), HAL_RAMECC_EnableNotification(), HAL_RAMECC_StartMonitor(), and HAL_RAMECC_StopMonitor().

#define HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U

Invalid Callback error

Definition at line 83 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_RegisterCallback(), and HAL_RAMECC_UnRegisterCallback().

#define HAL_RAMECC_ERROR_NONE 0x00000000U

RAMECC No Error

Definition at line 80 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), and HAL_RAMECC_Init().

#define HAL_RAMECC_ERROR_TIMEOUT 0x00000001U

RAMECC Timeout Error

Definition at line 81 of file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC interrupts

Defines
RAMECC interrupts
RAMECC

Defines

#define | RAMECC_IT_GLOBAL_ID 0x10000000UL
#define | RAMECC_IT_MONITOR_ID 0x20000000UL
#define | RAMECC_IT_GLOBAL_ENABLE (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE)
#define | RAMECC_IT_GLOBAL_SINGLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE)
#define | RAMECC_IT_GLOBAL_DOUBLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE)
#define | RAMECC_IT_GLOBAL_DOUBLEERR_W (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE)
#define | RAMECC_IT_GLOBAL_ALL (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE)
#define | RAMECC_IT_MONITOR_SINGLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE)
#define | RAMECC_IT_MONITOR_DOUBLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE)
#define | RAMECC_IT_MONITOR_DOUBLEERR_W (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE)
#define | RAMECC_IT_MONITOR_ALL (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE)

Define Documentation

#define RAMECC_IT_GLOBAL_ALL (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE)

Definition at line 98 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_IRQHandler().

#define RAMECC_IT_GLOBAL_DOUBLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE)

Definition at line 96 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_GLOBAL_DOUBLEERR_W (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE)

Definition at line 97 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_GLOBAL_ENABLE (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE)

Definition at line 94 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_GLOBAL_ID 0x10000000UL

Definition at line 91 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_GLOBAL_SINGLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE)

Definition at line 95 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_MONITOR_ALL (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE)

Definition at line 104 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_MONITOR_DOUBLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE)

Definition at line 102 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_MONITOR_DOUBLEERR_W (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE)

Definition at line 103 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_MONITOR_ID 0x20000000UL

Definition at line 92 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_IT_MONITOR_SINGLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE)

Definition at line 101 of file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Private Functions

RAMECC Private Functions
RAMECC Monitor flags

RAMECC private functions. More...

RAMECC private functions.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Monitor flags

Modules | Defines
RAMECC Monitor flags
RAMECC

Modules

RAMECC Private Functions

RAMECC private functions.

Defines

#define | RAMECC_FLAG_SINGLEERR_R RAMECC_SR_SEDCF
#define | RAMECC_FLAG_DOUBLEERR_R RAMECC_SR_DEDF
#define | RAMECC_FLAG_DOUBLEERR_W RAMECC_SR_DEBWDF
#define | RAMECC_FLAGS_ALL (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)

Define Documentation

#define RAMECC_FLAG_DOUBLEERR_R RAMECC_SR_DEDF

Definition at line 113 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_FLAG_DOUBLEERR_W RAMECC_SR_DEBWDF

Definition at line 114 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_FLAG_SINGLEERR_R RAMECC_SR_SEDCF

Definition at line 112 of file stm32h7xx_hal_ramecc.h.

#define RAMECC_FLAGS_ALL (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)

Definition at line 115 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), and HAL_RAMECC_Init().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Exported Macros

Defines
RAMECC Exported Macros
RAMECC

Defines

#define | __HAL_RAMECC_ENABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define | __HAL_RAMECC_ENABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
#define | __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified RAMECC interrupts.
#define | __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define | __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
#define | __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified RAMECC interrupts.
#define | __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
#define | __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
#define | __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RAMECC interrupt source is enabled or not.
#define | __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
Get the RAMECC pending flags.
#define | __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
Clear the RAMECC pending flags.
#define | __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)
Reset the RAMECC handle state.

Define Documentation

#define __HAL_RAMECC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR &= ~(__FLAG__))

Clear the RAMECC pending flags.

Parameters:
__HANDLE__ : RAMECC handle.
__FLAG__ : specifies the flag to clear. This parameter can be any combination of the following values:
  • RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
  • RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
  • RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
  • RAMECC_FLAGS_ALL : RAMECC instance all flag.
Return values:
None.

Definition at line 223 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DeInit(), HAL_RAMECC_Init(), and HAL_RAMECC_IRQHandler().

#define __HAL_RAMECC_DISABLE_GLOBAL_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))

Definition at line 150 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
( \
(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_DISABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\
(__HAL_RAMECC_DISABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))

Disable the specified RAMECC interrupts.

Parameters:
__HANDLE__ : RAMECC handle.
__INTERRUPT__,: specifies the RAMECC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
  • RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
  • RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
  • RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
  • RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
  • RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
  • RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
Return values:
None

Definition at line 169 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DisableNotification().

#define __HAL_RAMECC_DISABLE_MONITOR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))

Definition at line 151 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_ENABLE_GLOBAL_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))

Definition at line 126 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
( \
(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_ENABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\
(__HAL_RAMECC_ENABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))

Enable the specified RAMECC interrupts.

Parameters:
__HANDLE__ : RAMECC handle.
__INTERRUPT__,: specifies the RAMECC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
  • RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
  • RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
  • RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
  • RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
  • RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
  • RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
Return values:
None

Definition at line 145 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_EnableNotification().

#define __HAL_RAMECC_ENABLE_MONITOR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))

Definition at line 127 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR &= (__FLAG__))

Get the RAMECC pending flags.

Parameters:
__HANDLE__ : RAMECC handle.
__FLAG__ : specifies the flag to clear. This parameter can be any combination of the following values:
  • RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
  • RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
  • RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
  • RAMECC_FLAGS_ALL : RAMECC instance all flag.
Return values:
The state of __FLAG__ (SET or RESET).

Definition at line 209 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_GET_GLOBAL_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)

Definition at line 174 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(  \
(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_GET_GLOBAL_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
(__HAL_RAMECC_GET_MONITOR_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))

Check whether the specified RAMECC interrupt source is enabled or not.

Parameters:
__HANDLE__ : Specifies the RAMECC Handle.
__INTERRUPT__ : Specifies the RAMECC interrupt source to check. This parameter can be one of the following values:
  • RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
  • RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
  • RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
  • RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
  • RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
  • RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
  • RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
  • RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 193 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_GET_MONITOR_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)

Definition at line 175 of file stm32h7xx_hal_ramecc.h.

#define __HAL_RAMECC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)

Reset the RAMECC handle state.

Parameters:
__HANDLE__ : Specifies the RAMECC Handle.
Return values:
None.

Definition at line 230 of file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RAMECC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
Initialize the RAMECC by clearing flags and disabling interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
DeInitializes the RAMECC peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the RAMECC Monitor.
    [..]
    The HAL_RAMECC_Init() function follows the RAMECC configuration procedures
    as described in reference manual.
    The HAL_RAMECC_DeInit() function allows to deinitialize the RAMECC monitor.

Function Documentation

HAL_StatusTypeDef HAL_RAMECC_DeInit ( RAMECC_HandleTypeDef * hramecc )

DeInitializes the RAMECC peripheral.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
HAL status.

Definition at line 181 of file stm32h7xx_hal_ramecc.c.

References __HAL_RAMECC_CLEAR_FLAG, assert_param, __RAMECC_HandleTypeDef::DetectErrorCallback, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_NONE, HAL_RAMECC_STATE_RESET, __RAMECC_HandleTypeDef::Instance, RAMECC_FLAGS_ALL, and __RAMECC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RAMECC_Init ( RAMECC_HandleTypeDef * hramecc )

Initialize the RAMECC by clearing flags and disabling interrupts.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
HAL status.

Definition at line 135 of file stm32h7xx_hal_ramecc.c.

References __HAL_RAMECC_CLEAR_FLAG, assert_param, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_NONE, HAL_RAMECC_STATE_BUSY, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, RAMECC_FLAGS_ALL, and __RAMECC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Error informations functions

Functions
Error informations functions
RAMECC Exported Functions | monitoring operation functions

Error informations functions. More...

Functions

uint32_t | HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC failing address.
uint32_t | HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data low.
uint32_t | HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data high.
uint32_t | HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC Hamming bits injected.
uint32_t | HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC single error was occured.
uint32_t | HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC double error was occured.
HAL_RAMECC_StateTypeDef | HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral state.
uint32_t | HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral error code.

Detailed Description

Error informations functions.

 ===============================================================================
                   #####  Error informations functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get failing address.
      (+) Get failing data low.
      (+) Get failing data high.
      (+) Get hamming bits injected.
      (+) Check single error flag.
      (+) Check double error flag.

Function Documentation

uint32_t HAL_RAMECC_GetError ( RAMECC_HandleTypeDef * hramecc )

Get the RAMECC peripheral error code.

Parameters:
hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC instance.
Return values:
RAMECC error code.

Definition at line 666 of file stm32h7xx_hal_ramecc.c.

References __RAMECC_HandleTypeDef::ErrorCode.

uint32_t HAL_RAMECC_GetFailingAddress ( RAMECC_HandleTypeDef * hramecc )

Return the RAMECC failing address.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
Failing address offset.

Definition at line 531 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

uint32_t HAL_RAMECC_GetFailingDataHigh ( RAMECC_HandleTypeDef * hramecc )

Return the RAMECC data high.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
Failing data high.

Definition at line 565 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

uint32_t HAL_RAMECC_GetFailingDataLow ( RAMECC_HandleTypeDef * hramecc )

Return the RAMECC data low.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
Failing data low.

Definition at line 548 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

uint32_t HAL_RAMECC_GetHammingErrorCode ( RAMECC_HandleTypeDef * hramecc )

Return the RAMECC Hamming bits injected.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
Hamming bits injected.

Definition at line 582 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState ( RAMECC_HandleTypeDef * hramecc )

Get the RAMECC peripheral state.

Parameters:
hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC instance.
Return values:
RAMECC state.

Definition at line 653 of file stm32h7xx_hal_ramecc.c.

References __RAMECC_HandleTypeDef::State.

uint32_t HAL_RAMECC_IsECCDoubleErrorDetected ( RAMECC_HandleTypeDef * hramecc )

Check if an ECC double error was occured.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
State of bit (1 or 0).

Definition at line 614 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

uint32_t HAL_RAMECC_IsECCSingleErrorDetected ( RAMECC_HandleTypeDef * hramecc )

Check if an ECC single error was occured.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
State of bit (1 or 0).

Definition at line 598 of file stm32h7xx_hal_ramecc.c.

References assert_param, and __RAMECC_HandleTypeDef::Instance.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC_Exported_Functions_Group4

Functions
RAMECC_Exported_Functions_Group4
monitoring operation functions

Functions

HAL_RAMECC_StateTypeDef | HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral state.
uint32_t | HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral error code.

Detailed Description

 ===============================================================================
                    ##### State and Error Functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to check and get the RAMECC state
    and the error code .
    [..]
    The HAL_RAMECC_GetState() function allows to get the RAMECC peripheral
    state.
    The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error
    code.

Function Documentation

uint32_t HAL_RAMECC_GetError ( RAMECC_HandleTypeDef * hramecc )

Get the RAMECC peripheral error code.

Parameters:
hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC instance.
Return values:
RAMECC error code.

Definition at line 666 of file stm32h7xx_hal_ramecc.c.

References __RAMECC_HandleTypeDef::ErrorCode.

HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState ( RAMECC_HandleTypeDef * hramecc )

Get the RAMECC peripheral state.

Parameters:
hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC instance.
Return values:
RAMECC state.

Definition at line 653 of file stm32h7xx_hal_ramecc.c.

References __RAMECC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: monitoring operation functions

Modules | Functions
monitoring operation functions
RAMECC Exported Functions | RAMECC

monitoring operation functions More...

Modules

Error informations functions

Error informations functions.

RAMECC_Exported_Functions_Group4

Functions

HAL_StatusTypeDef | HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
Starts the RAMECC latching error information.
HAL_StatusTypeDef | HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
Stop the RAMECC latching error informations.
HAL_StatusTypeDef | HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Enable the RAMECC error interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Disable the RAMECC error interrupts.
HAL_StatusTypeDef | HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void(*pCallback)(RAMECC_HandleTypeDef *_hramecc))
Register callbacks.
HAL_StatusTypeDef | HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
UnRegister callbacks.
void | HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
Handles RAMECC interrupt request.

Detailed Description

monitoring operation functions

 ===============================================================================
                   #####  Monitoring operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure latching error informations.
      (+) Configure RAMECC Global/Monitor interrupts.
      (+) Register and Unregister RAMECC callbacks
      (+) Handle RAMECC interrupt request

Function Documentation

HAL_StatusTypeDef HAL_RAMECC_DisableNotification | ( | RAMECC_HandleTypeDef * | hramecc,
 |  | uint32_t | Notifications
 | ) |  |

Disable the RAMECC error interrupts.

Parameters:
hramecc | Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Notifications | Select the notification.
Return values:
HAL status.

Definition at line 366 of file stm32h7xx_hal_ramecc.c.

References __HAL_RAMECC_DISABLE_IT, assert_param, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_BUSY, HAL_RAMECC_STATE_BUSY, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, IS_RAMECC_INTERRUPT, and __RAMECC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RAMECC_EnableNotification | ( | RAMECC_HandleTypeDef * | hramecc,
 |  | uint32_t | Notifications
 | ) |  |

Enable the RAMECC error interrupts.

Parameters:
hramecc | Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Notifications | Select the notification.
Return values:
HAL status.

Definition at line 326 of file stm32h7xx_hal_ramecc.c.

References __HAL_RAMECC_ENABLE_IT, assert_param, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_BUSY, HAL_RAMECC_STATE_BUSY, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, IS_RAMECC_INTERRUPT, and __RAMECC_HandleTypeDef::State.

void HAL_RAMECC_IRQHandler ( RAMECC_HandleTypeDef * hramecc )

Handles RAMECC interrupt request.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
None.

Definition at line 482 of file stm32h7xx_hal_ramecc.c.

References __HAL_RAMECC_CLEAR_FLAG, __RAMECC_HandleTypeDef::DetectErrorCallback, __RAMECC_HandleTypeDef::Instance, and RAMECC_IT_GLOBAL_ALL.

HAL_StatusTypeDef HAL_RAMECC_RegisterCallback | ( | RAMECC_HandleTypeDef * | hramecc,
 |  | void(*)(RAMECC_HandleTypeDef *_hramecc) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hramecc | Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
pCallback | pointer to private callbacsk function which has pointer to a RAMECC_HandleTypeDef structure as parameter.
Return values:
HAL status.

Definition at line 407 of file stm32h7xx_hal_ramecc.c.

References assert_param, __RAMECC_HandleTypeDef::DetectErrorCallback, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_INVALID_CALLBACK, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, and __RAMECC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RAMECC_StartMonitor ( RAMECC_HandleTypeDef * hramecc )

Starts the RAMECC latching error information.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
HAL status.

Definition at line 249 of file stm32h7xx_hal_ramecc.c.

References assert_param, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_BUSY, HAL_RAMECC_STATE_BUSY, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, and __RAMECC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RAMECC_StopMonitor ( RAMECC_HandleTypeDef * hramecc )

Stop the RAMECC latching error informations.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
HAL status.

Definition at line 287 of file stm32h7xx_hal_ramecc.c.

References assert_param, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_BUSY, HAL_RAMECC_STATE_BUSY, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, and __RAMECC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback ( RAMECC_HandleTypeDef * hramecc )

UnRegister callbacks.

Parameters:
hramecc Pointer to a RAMECC_HandleTypeDef structure that contains the configuration information for the specified RAMECC Monitor.
Return values:
HAL status.

Definition at line 449 of file stm32h7xx_hal_ramecc.c.

References assert_param, __RAMECC_HandleTypeDef::DetectErrorCallback, __RAMECC_HandleTypeDef::ErrorCode, HAL_RAMECC_ERROR_INVALID_CALLBACK, HAL_RAMECC_STATE_READY, __RAMECC_HandleTypeDef::Instance, and __RAMECC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Private Constants

RAMECC Private Constants
RAMECC

RAMECC private defines and constants. More...

RAMECC private defines and constants.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Private Macros

Defines
RAMECC Private Macros
RAMECC

RAMECC private macros. More...

Defines

#define | IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)
#define | IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)
#define | IS_RAMECC_INTERRUPT(INTERRUPT)

Detailed Description

RAMECC private macros.

Define Documentation

#define IS_RAMECC_GLOBAL_INTERRUPT ( INTERRUPT )
Value:
(((INTERRUPT) == RAMECC_IT_GLOBAL_ENABLE)      || \
                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \
                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \
                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_W) || \
                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_ALL))

Definition at line 309 of file stm32h7xx_hal_ramecc.h.

#define IS_RAMECC_INTERRUPT ( INTERRUPT )
Value:
((IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)) || \
                                        (IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)))

Definition at line 321 of file stm32h7xx_hal_ramecc.h.

Referenced by HAL_RAMECC_DisableNotification(), and HAL_RAMECC_EnableNotification().

#define IS_RAMECC_MONITOR_INTERRUPT ( INTERRUPT )
Value:
(((INTERRUPT) == RAMECC_IT_MONITOR_SINGLEERR_R) || \
                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \
                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \
                                                ((INTERRUPT) == RAMECC_IT_MONITOR_ALL))

Definition at line 316 of file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCC Private Macros

Defines

#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI)
#define | IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
#define | IS_RCC_PLL(PLL)
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
#define | IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLCLOCKOUT_VALUE(VALUE)
#define | IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_SYSCLK(SYSCLK)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CDPCLK1(CDPCLK1)
#define | IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */
#define | IS_RCC_PCLK1(PCLK1)
#define | IS_RCC_PCLK2(PCLK2)
#define | IS_RCC_SRDPCLK1(SRDPCLK1)
#define | IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
#define | IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
#define | IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define | IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Define Documentation

#define IS_RCC_CDPCLK1 ( CDPCLK1 )
Value:
(((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
                                 ((CDPCLK1) == RCC_APB3_DIV16))

Definition at line 7754 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_CLOCKTYPE ( CLK ) ((1U <= (CLK)) && ((CLK) <= 0x3FU))

Definition at line 7734 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_CSI ( CSI ) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))

Definition at line 7711 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CSICALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x3FU)

Definition at line 7874 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */

Definition at line 7758 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/

Definition at line 7772 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_FLAG ( FLAG )
Value:
(((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

Definition at line 7858 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
                           ((HCLK) == RCC_HCLK_DIV512))

Definition at line 7748 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))

Definition at line 7688 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( HSI )
Value:
(((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))

Definition at line 7703 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI48 ( HSI48 ) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))

Definition at line 7707 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSICALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x7FU)

Definition at line 7873 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))

Definition at line 7696 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI ( LSI ) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

Definition at line 7709 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( MCOx ) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

Definition at line 7807 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))

Definition at line 7809 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))

Definition at line 7813 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( DIV )
Value:
(((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
                            ((DIV) == RCC_MCODIV_15))

Definition at line 7817 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( OSCILLATOR )
Value:
(((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))

Definition at line 7679 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK1 ( PCLK1 )
Value:
(((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
                            ((PCLK1) == RCC_APB1_DIV16))

Definition at line 7760 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PCLK2 ( PCLK2 )
Value:
(((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
                             ((PCLK2) == RCC_APB2_DIV16))

Definition at line 7764 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( PLL )
Value:
(((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
                         ((PLL) == RCC_PLL_ON))

Definition at line 7713 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLCLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL1_DIVP) || \
                                         ((VALUE) == RCC_PLL1_DIVQ) || \
                                         ((VALUE) == RCC_PLL1_DIVR))

Definition at line 7730 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_PLLM_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 63U))

Definition at line 7720 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( VALUE ) ((8U <= (VALUE)) && ((VALUE) <= 420U))

Definition at line 7724 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 7726 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 7727 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 7728 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSOURCE_CSI)  || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSE))

Definition at line 7716 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( SOURCE )

Definition at line 7774 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SRDPCLK1 ( SRDPCLK1 )
Value:
(((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
                                  ((SRDPCLK1) == RCC_APB4_DIV16))

Definition at line 7768 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_STOP_KERWAKEUPCLOCK ( SOURCE )
Value:
(((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))

Definition at line 7879 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_KerWakeUpStopCLKConfig().

#define IS_RCC_STOP_WAKEUPCLOCK ( SOURCE )
Value:
(((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))

Definition at line 7876 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define IS_RCC_SYSCLK ( SYSCLK )
Value:
(((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
                               ((SYSCLK) == RCC_SYSCLK_DIV512))

Definition at line 7741 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_SYSCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 7736 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private Macros

Modules | Defines
RCC Private Macros
RCC

Modules

RCC Private macros to check input parameters

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Define Documentation

#define MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 88 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 89 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 90 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOC_CLK_ENABLE()

Definition at line 92 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOC

Definition at line 93 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_9

Definition at line 94 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).

    [..] Internal/external clock and PLL configuration
         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.
         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
             clock, or PLL input.But even with frequency calibration, is less accurate than an
             external crystal oscillator or ceramic resonator.
         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also as RTC clock source.

         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
             featuring three different output clocks and able  to work either in integer or Fractional mode.
           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
                and to some peripherals.
           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.

         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
             exception vector.

         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.

         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.

    [..] System, AHB and APB buses clocks configuration
         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
             HSE and PLL.
             The AHB clock (HCLK) is derived from System core clock through configurable
             pre-scaler and used to clock the CPU, memory and peripherals mapped
             on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
             and used to clock the peripherals mapped on these buses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
             with dual clock domain where kernel source clock could be selected through
             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.

     (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency,: FLASH Latency, this parameter depend on device selected
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_InitTick() function called within this function
The HSI is used (enabled by hardware) as system clock source after start-up from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after start-up delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 881 of file stm32h7xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CDPCLK1, IS_RCC_CLOCKTYPE, IS_RCC_D1PCLK1, IS_RCC_D3PCLK1, IS_RCC_HCLK, IS_RCC_PCLK1, IS_RCC_PCLK2, IS_RCC_SRDPCLK1, IS_RCC_SYSCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_CSIRDY, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_CSI, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKDivider, RCC_ClkInitTypeDef::SYSCLKSource, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL1, PLL2 and PLL3 OFF
  • AHB, APB Bus pre-scaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
HAL status

Definition at line 190 of file stm32h7xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, CLOCKSWITCH_TIMEOUT_VALUE, HAL_GetTick(), HAL_InitTick(), HSE_TIMEOUT_VALUE, HSI_TIMEOUT_VALUE, HSI_VALUE, PLL_TIMEOUT_VALUE, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this function. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this function. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 401 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_CSI_DISABLE, __HAL_RCC_CSI_ENABLE, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI48_DISABLE, __HAL_RCC_HSI48_ENABLE, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_CONFIG, __HAL_RCC_HSI_DISABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLL_VCIRANGE, __HAL_RCC_PLL_VCORANGE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PLLFRACN_CONFIG, __HAL_RCC_PLLFRACN_DISABLE, __HAL_RCC_PLLFRACN_ENABLE, assert_param, CSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CSI, IS_RCC_CSICALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI48, IS_RCC_HSICALIBRATION_VALUE, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLFRACN_VALUE, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLFRACN, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_CSIRDY, RCC_FLAG_HSERDY, RCC_FLAG_HSI48RDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL1_DIVP, RCC_PLL1_DIVQ, RCC_PLL1_DIVR, RCC_PLL_NONE, RCC_PLL_OFF, and RCC_PLL_ON.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

__weak void HAL_RCC_CCSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1721 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 1294 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
Return values:
None

Definition at line 1285 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1648 of file stm32h7xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_ClkInitTypeDef::SYSCLKDivider, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1430 of file stm32h7xx_hal_rcc.c.

References HAL_RCCEx_GetD1SysClockFreq().

Referenced by ADC_ConfigureBoostMode(), HAL_InitTick(), HAL_PCD_IRQHandler(), HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD1PCLK1Freq(), and HAL_RCCEx_GetD3PCLK1Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1482 of file stm32h7xx_hal_rcc.c.

References RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, HAL_GetREVID(), RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLFRACN, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_HSE_BYPASS, RCC_HSE_BYPASS_DIGITAL, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_BYPASS_DIGITAL, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, RCC_PLL_ON, and REV_ID_Y.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1447 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1465 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 64 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1333 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, RCC_FLAG_HSIDIV, RCC_PLLSOURCE_CSI, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), and HAL_RCCEx_GetD1SysClockFreq().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
  • RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx pre-scaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
Return values:
None

Definition at line 1231 of file stm32h7xx_hal_rcc.c.

References GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, MCO2_CLK_ENABLE, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1704 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CCSCallback(), and RCC_IT_CSS.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_Exported_Functions_Group2

Functions
RCC_Exported_Functions_Group2
RCC Exported Functions

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Function Documentation

void HAL_RCC_CCSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1721 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 1294 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
Return values:
None

Definition at line 1285 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1648 of file stm32h7xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_ClkInitTypeDef::SYSCLKDivider, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1430 of file stm32h7xx_hal_rcc.c.

References HAL_RCCEx_GetD1SysClockFreq().

Referenced by ADC_ConfigureBoostMode(), HAL_InitTick(), HAL_PCD_IRQHandler(), HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD1PCLK1Freq(), and HAL_RCCEx_GetD3PCLK1Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1482 of file stm32h7xx_hal_rcc.c.

References RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, HAL_GetREVID(), RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLFRACN, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_HSE_BYPASS, RCC_HSE_BYPASS_DIGITAL, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_BYPASS_DIGITAL, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, RCC_PLL_ON, and REV_ID_Y.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1447 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1465 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 64 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1333 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, RCC_FLAG_HSIDIV, RCC_PLLSOURCE_CSI, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), and HAL_RCCEx_GetD1SysClockFreq().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
  • RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx pre-scaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
Return values:
None

Definition at line 1231 of file stm32h7xx_hal_rcc.c.

References GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, MCO2_CLK_ENABLE, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1704 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CCSCallback(), and RCC_IT_CSS.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR
uint32_t | PLLRGE
uint32_t | PLLVCOSEL
uint32_t | PLLFRACN

Detailed Description

RCC PLL configuration structure definition.

Definition at line 48 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLFRACN

PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191

Definition at line 78 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 56 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 or between Min_Data = 8 and Max_Data = 420(*) (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 59 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 64 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 68 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 71 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLRGE

PLLRGE: PLL1 clock Input range This parameter must be a value of RCC PLL1 VCI Range

Definition at line 73 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of RCC PLL Clock Source

Definition at line 53 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of RCC PLL Config

Definition at line 50 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLVCOSEL

PLLVCOSEL: PLL1 clock Output range This parameter must be a value of RCC PLL1 VCO Range

Definition at line 75 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | HSI48State
uint32_t | CSIState
uint32_t | CSICalibrationValue
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition.

Definition at line 86 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::CSICalibrationValue

The calibration trimming value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above

Definition at line 113 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::CSIState

The new state of the CSI. This parameter can be a value of RCC CSI Config

Definition at line 110 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of RCC HSE Config

Definition at line 91 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48. This parameter can be a value of RCC HSI48 Config

Definition at line 107 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above

Definition at line 100 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of RCC HSI Config

Definition at line 97 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of RCC LSE Config

Definition at line 94 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of RCC LSI Config

Definition at line 104 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of RCC Oscillator Type

Definition at line 88 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 117 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | SYSCLKDivider
uint32_t | AHBCLKDivider
uint32_t | APB3CLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider
uint32_t | APB4CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 124 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of RCC HCLK Clock Source

Definition at line 135 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB1 Clock Source

Definition at line 141 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB2 Clock Source

Definition at line 143 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB3CLKDivider

The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB3 Clock Source

Definition at line 138 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB4CLKDivider

The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB4 Clock Source

Definition at line 145 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of RCC System Clock Type

Definition at line 126 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKDivider

The system clock divider. This parameter can be a value of RCC SYS Clock Source

Definition at line 132 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of RCC System Clock Source

Definition at line 129 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Oscillator Type

Defines
RCC Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI (0x00000008U)
#define | RCC_OSCILLATORTYPE_CSI (0x00000010U)
#define | RCC_OSCILLATORTYPE_HSI48 (0x00000020U)

Define Documentation

#define RCC_OSCILLATORTYPE_CSI (0x00000010U)

Definition at line 167 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSE (0x00000001U)

Definition at line 163 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI (0x00000002U)

Definition at line 164 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)

Definition at line 168 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE (0x00000004U)

Definition at line 165 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI (0x00000008U)

Definition at line 166 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE (0x00000000U)

Definition at line 162 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC HSE Config

Defines
RCC HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF (0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Definition at line 179 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))

Definition at line 181 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF (0x00000000U)

Definition at line 177 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

Definition at line 178 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC LSE Config

Defines
RCC LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF (0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Definition at line 193 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Definition at line 195 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF (0x00000000U)

Definition at line 191 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

Definition at line 192 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC HSI Config

Defines
RCC HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF (0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
#define | RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
#define | RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
#define | RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value, for STM32H7 rev.V and above */

Define Documentation

#define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)

HSI_DIV1 clock activation

Definition at line 208 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)

HSI_DIV2 clock activation

Definition at line 209 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)

HSI_DIV4 clock activation

Definition at line 210 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)

HSI_DIV8 clock activation

Definition at line 211 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_OFF (0x00000000U)

HSI clock deactivation

Definition at line 205 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 206 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value, for STM32H7 rev.V and above */

Definition at line 215 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC HSI48 Config

Defines
RCC HSI48 Config
RCC Exported Constants

Defines

#define | RCC_HSI48_OFF ((uint8_t)0x00)
#define | RCC_HSI48_ON ((uint8_t)0x01)

Define Documentation

#define RCC_HSI48_OFF ((uint8_t)0x00)

Definition at line 226 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI48_ON ((uint8_t)0x01)

Definition at line 227 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC LSI Config

Defines
RCC LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF (0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF (0x00000000U)

Definition at line 236 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

Definition at line 237 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC CSI Config

Defines
RCC CSI Config
RCC Exported Constants

Defines

#define | RCC_CSI_OFF (0x00000000U)
#define | RCC_CSI_ON RCC_CR_CSION
#define | RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value */

Define Documentation

#define RCC_CSI_OFF (0x00000000U)

Definition at line 246 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_CSI_ON RCC_CR_CSION

Definition at line 247 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value */

Definition at line 250 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL Config

Defines
RCC PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE (0x00000000U)
#define | RCC_PLL_OFF (0x00000001U)
#define | RCC_PLL_ON (0x00000002U)

Define Documentation

#define RCC_PLL_NONE (0x00000000U)

Definition at line 261 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF (0x00000001U)

Definition at line 262 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_PLL_ON (0x00000002U)

Definition at line 263 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL Clock Source

Defines
RCC PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI (0x00000000U)
#define | RCC_PLLSOURCE_CSI (0x00000001U)
#define | RCC_PLLSOURCE_HSE (0x00000002U)
#define | RCC_PLLSOURCE_NONE (0x00000003U)

Define Documentation

#define RCC_PLLSOURCE_CSI (0x00000001U)

Definition at line 274 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

#define RCC_PLLSOURCE_HSE (0x00000002U)

Definition at line 275 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

#define RCC_PLLSOURCE_HSI (0x00000000U)

Definition at line 273 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

#define RCC_PLLSOURCE_NONE (0x00000003U)

Definition at line 276 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL Clock Output

Defines
RCC PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
#define | RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
#define | RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN

Define Documentation

#define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN

Definition at line 284 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN

Definition at line 285 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN

Definition at line 286 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL1 VCI Range

Defines
RCC PLL1 VCI Range
RCC Exported Constants

Defines

#define | RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
#define | RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
#define | RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
#define | RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3

Define Documentation

#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0

Definition at line 297 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1

Definition at line 298 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2

Definition at line 299 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3

Definition at line 300 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL1 VCO Range

Defines
RCC PLL1 VCO Range
RCC Exported Constants

Defines

#define | RCC_PLL1VCOWIDE (0x00000000U)
#define | RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL

Define Documentation

#define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL

Definition at line 312 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCOWIDE (0x00000000U)

Definition at line 311 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC System Clock Type

Defines
RCC System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK (0x00000001U)
#define | RCC_CLOCKTYPE_HCLK (0x00000002U)
#define | RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
#define | RCC_CLOCKTYPE_PCLK1 (0x00000008U)
#define | RCC_CLOCKTYPE_PCLK2 (0x00000010U)
#define | RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)

Define Documentation

#define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)

Definition at line 324 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)

Definition at line 327 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_HCLK (0x00000002U)

Definition at line 323 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 (0x00000008U)

Definition at line 325 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 (0x00000010U)

Definition at line 326 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)

Definition at line 322 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC System Clock Source

Defines
RCC System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1

Define Documentation

#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI

Definition at line 336 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

Definition at line 338 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

Definition at line 337 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1

Definition at line 339 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI

CSI used as system clock

Definition at line 348 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 350 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 349 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1

PLL1 used as system clock

Definition at line 351 of file stm32h7xx_hal_rcc.h.

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STM32H7B3xQ HAL User Manual: RCC SYS Clock Source

Defines
RCC SYS Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1

Definition at line 370 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128

Definition at line 376 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16

Definition at line 374 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2

Definition at line 371 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256

Definition at line 377 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4

Definition at line 372 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512

Definition at line 378 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64

Definition at line 375 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8

Definition at line 373 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC HCLK Clock Source

Defines
RCC HCLK Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1
#define | RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2
#define | RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4
#define | RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8
#define | RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16
#define | RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64
#define | RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128
#define | RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256
#define | RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512

Define Documentation

#define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1

Definition at line 399 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128

Definition at line 405 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16

Definition at line 403 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2

Definition at line 400 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256

Definition at line 406 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4

Definition at line 401 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512

Definition at line 407 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64

Definition at line 404 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8

Definition at line 402 of file stm32h7xx_hal_rcc.h.

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STM32H7B3xQ HAL User Manual: RCC APB3 Clock Source

Defines
RCC APB3 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1
#define | RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2
#define | RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4
#define | RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8
#define | RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16

Define Documentation

#define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1

Definition at line 423 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16

Definition at line 427 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2

Definition at line 424 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4

Definition at line 425 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8

Definition at line 426 of file stm32h7xx_hal_rcc.h.

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STM32H7B3xQ HAL User Manual: RCC APB1 Clock Source

Defines
RCC APB1 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1
#define | RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2
#define | RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4
#define | RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8
#define | RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16

Define Documentation

#define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1

Definition at line 443 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16

Definition at line 447 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2

Definition at line 444 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4

Definition at line 445 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8

Definition at line 446 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC APB2 Clock Source

Defines
RCC APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1
#define | RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2
#define | RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4
#define | RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8
#define | RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16

Define Documentation

#define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1

Definition at line 464 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16

Definition at line 468 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2

Definition at line 465 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4

Definition at line 466 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8

Definition at line 467 of file stm32h7xx_hal_rcc.h.

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STM32H7B3xQ HAL User Manual: RCC APB4 Clock Source

Defines
RCC APB4 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1
#define | RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2
#define | RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4
#define | RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8
#define | RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16

Define Documentation

#define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1

Definition at line 484 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16

Definition at line 488 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2

Definition at line 485 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4

Definition at line 486 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8

Definition at line 487 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC RTC Clock Source

Defines
RCC RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
#define | RCC_RTCCLKSOURCE_LSE (0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI (0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)

Definition at line 508 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)

Definition at line 509 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)

Definition at line 510 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)

Definition at line 511 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)

Definition at line 512 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)

Definition at line 513 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)

Definition at line 514 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)

Definition at line 515 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)

Definition at line 516 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)

Definition at line 517 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)

Definition at line 500 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)

Definition at line 518 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)

Definition at line 519 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)

Definition at line 520 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)

Definition at line 521 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)

Definition at line 522 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)

Definition at line 523 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)

Definition at line 524 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)

Definition at line 525 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)

Definition at line 526 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)

Definition at line 527 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)

Definition at line 501 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)

Definition at line 528 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)

Definition at line 529 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)

Definition at line 530 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)

Definition at line 531 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)

Definition at line 532 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)

Definition at line 533 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)

Definition at line 534 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)

Definition at line 535 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)

Definition at line 536 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)

Definition at line 537 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)

Definition at line 502 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)

Definition at line 538 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)

Definition at line 539 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)

Definition at line 540 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)

Definition at line 541 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)

Definition at line 542 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)

Definition at line 543 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)

Definition at line 544 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)

Definition at line 545 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)

Definition at line 546 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)

Definition at line 547 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)

Definition at line 503 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)

Definition at line 548 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)

Definition at line 549 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)

Definition at line 550 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)

Definition at line 551 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)

Definition at line 552 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)

Definition at line 553 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)

Definition at line 554 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)

Definition at line 555 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)

Definition at line 556 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)

Definition at line 557 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)

Definition at line 504 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)

Definition at line 558 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)

Definition at line 559 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)

Definition at line 560 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)

Definition at line 561 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)

Definition at line 505 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)

Definition at line 506 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)

Definition at line 507 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSE (0x00000100U)

Definition at line 498 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RTCCLKSOURCE_LSI (0x00000200U)

Definition at line 499 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)

Definition at line 497 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC MCO Index

Defines
RCC MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 (0x00000000U)
#define | RCC_MCO2 (0x00000001U)

Define Documentation

#define RCC_MCO1 (0x00000000U)

Definition at line 572 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 (0x00000001U)

Definition at line 573 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC MCO1 Clock Source

Defines
RCC MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_HSI (0x00000000U)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

Definition at line 584 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI (0x00000000U)

Definition at line 582 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2

Definition at line 586 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

Definition at line 583 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)

Definition at line 585 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC MCO2 Clock Source

Defines
RCC MCO2 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO2SOURCE_SYSCLK (0x00000000U)
#define | RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
#define | RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
#define | RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

Define Documentation

#define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2

Definition at line 599 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1

Definition at line 597 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

Definition at line 600 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0

Definition at line 596 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)

Definition at line 598 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_SYSCLK (0x00000000U)

Definition at line 595 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC MCOx Clock Prescaler

Defines
RCC MCOx Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
#define | RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_15 RCC_CFGR_MCO1PRE

Define Documentation

#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0

Definition at line 609 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 618 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 619 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 620 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 621 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 622 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE

Definition at line 623 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1

Definition at line 610 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

Definition at line 611 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2

Definition at line 612 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

Definition at line 613 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 614 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 615 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3

Definition at line 616 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

Definition at line 617 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Interrupt

Defines
RCC Interrupt
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY (0x00000001U)
#define | RCC_IT_LSERDY (0x00000002U)
#define | RCC_IT_HSIRDY (0x00000004U)
#define | RCC_IT_HSERDY (0x00000008U)
#define | RCC_IT_CSIRDY (0x00000010U)
#define | RCC_IT_HSI48RDY (0x00000020U)
#define | RCC_IT_PLLRDY (0x00000040U)
#define | RCC_IT_PLL2RDY (0x00000080U)
#define | RCC_IT_PLL3RDY (0x00000100U)
#define | RCC_IT_LSECSS (0x00000200U)
#define | RCC_IT_CSS (0x00000400U)

Define Documentation

#define RCC_IT_CSIRDY (0x00000010U)

Definition at line 637 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_CSS (0x00000400U)

Definition at line 643 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY (0x00000008U)

Definition at line 636 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_HSI48RDY (0x00000020U)

Definition at line 638 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_HSIRDY (0x00000004U)

Definition at line 635 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_LSECSS (0x00000200U)

Definition at line 642 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define RCC_IT_LSERDY (0x00000002U)

Definition at line 634 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_LSIRDY (0x00000001U)

Definition at line 633 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLL2RDY (0x00000080U)

Definition at line 640 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLL3RDY (0x00000100U)

Definition at line 641 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLLRDY (0x00000040U)

Definition at line 639 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Flag

Defines
RCC Flag
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define | RCC_FLAG_HSIDIV ((uint8_t)0x25)
#define | RCC_FLAG_CSIRDY ((uint8_t)0x28)
#define | RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
#define | RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)
#define | RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */
#define | RCC_FLAG_CDCKRDY ((uint8_t)0x2F)
#define | RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_CDRST ((uint8_t)0x93)
#define | RCC_FLAG_BORRST ((uint8_t)0x95)
#define | RCC_FLAG_PINRST ((uint8_t)0x96)
#define | RCC_FLAG_PORRST ((uint8_t)0x97)
#define | RCC_FLAG_SFTRST ((uint8_t)0x98)
#define | RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
#define | RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
#define | RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
#define | RCC_FLAG_LPWR2RST ((uint8_t)0x9F)

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register
    • 100: RSR register

Define Documentation

#define RCC_FLAG_BORRST ((uint8_t)0x95)

Definition at line 698 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CDCKRDY ((uint8_t)0x2F)

Definition at line 672 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CDRST ((uint8_t)0x93)

Definition at line 693 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)

Definition at line 666 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CSIRDY ((uint8_t)0x28)

Definition at line 661 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */

Definition at line 667 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */

Definition at line 673 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((uint8_t)0x31)

Definition at line 675 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)

Definition at line 662 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_HSIDIV ((uint8_t)0x25)

Definition at line 660 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)0x22)

Definition at line 659 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)

Definition at line 702 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)

Definition at line 704 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)

Definition at line 705 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x41)

Definition at line 680 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)0x61)

Definition at line 683 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_PINRST ((uint8_t)0x96)

Definition at line 699 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)

Definition at line 677 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config().

#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)

Definition at line 678 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL3_Config().

#define RCC_FLAG_PLLRDY ((uint8_t)0x39)

Definition at line 676 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PORRST ((uint8_t)0x97)

Definition at line 700 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)0x98)

Definition at line 701 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)

Definition at line 703 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LSE Drive Config

Defines
LSE Drive Config
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW (0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

LSE high drive capability

Definition at line 727 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW (0x00000000U)

LSE low drive capability

Definition at line 724 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

LSE medium high drive capability

Definition at line 726 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

LSE medium low drive capability

Definition at line 725 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Stop WakeUpClock

Defines
RCC Stop WakeUpClock
RCC Exported Constants

Defines

#define | RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
#define | RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK

Define Documentation

#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK

Definition at line 736 of file stm32h7xx_hal_rcc.h.

#define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)

Definition at line 735 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Stop KernelWakeUpClock

Defines
RCC Stop KernelWakeUpClock
RCC Exported Constants

Defines

#define | RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
#define | RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK

Define Documentation

#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK

Definition at line 746 of file stm32h7xx_hal_rcc.h.

#define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)

Definition at line 745 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                               \
                      if((__STATE__) == RCC_LSE_ON)                    \
                      {                                                \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
                      }                                                \
                      else if((__STATE__) == RCC_LSE_OFF)              \
                      {                                                \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
                      }                                                \
                      else if((__STATE__) == RCC_LSE_BYPASS)           \
                      {                                                \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
                      }                                                \
                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
                      {                                                \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
                      }                                                \
                      else                                             \
                      {                                                \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
                      }                                                \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). A duty cycle close to 50% is recommended.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
Parameters:
__STATE__,: specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator.
  • RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
  • RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
(*) Available on some STM32H7 lines only.

Definition at line 7051 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Extended MCOx Clock Config

Defines
RCC Extended MCOx Clock Config
RCC Exported Macros

Defines

#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
Macro to configure the MCO2 clock.

Define Documentation

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO1 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock

Definition at line 7351 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MCO2_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));

Macro to configure the MCO2 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
  • RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock

Definition at line 7367 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__)

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear the RCC's interrupt pending bits.

Parameters:
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: CSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_HSECSS: HSE Clock Security interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 7478 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->RSR |= RCC_RSR_RMVF)

Set RMVF bit to clear the reset flags.

Definition at line 7500 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: HSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 7461 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: HSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 7445 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

Definition at line 7589 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HAL_RCCEx_PeriphCLKConfig(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt source to check. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: CSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_HSECSS: HSE Clock Security interrupt
  • RCC_IT_LSECSS: Clock security system interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 7496 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_FLAG_MASK ((uint8_t)0x1F)

Check RCC flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSIDIV: HSI divider flag
  • RCC_FLAG_CSIRDY: CSI oscillator clock ready
  • RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_D1CKRDY: Domain1 clock ready (*)
  • RCC_FLAG_D2CKRDY: Domain2 clock ready (*)
  • RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
  • RCC_FLAG_CDCKRDY: CPU Domain clock ready (*)
  • RCC_FLAG_PLLRDY: PLL1 clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_CPURST: CPU reset flag
  • RCC_FLAG_D1RST: D1 domain power switch reset flag (*)
  • RCC_FLAG_D2RST: D2 domain power switch reset flag (*)
  • RCC_FLAG_CDRST: CD domain power switch reset flag (*)
  • RCC_FLAG_BORRST: BOR reset flag
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: System reset from CPU reset flag
  • RCC_FLAG_BORRST: D2 domain power switch reset flag
  • RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
  • RCC_FLAG_WWDG1RST: Window Watchdog1 reset
  • RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
  • RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

(*) Available on some STM32H7 lines only.

Definition at line 7588 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Macros

Modules | Defines
RCC Exported Macros
RCC

Modules

LSE Configuration
RCC Extended MCOx Clock Config
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_MDMA_CLK_ENABLE()
Enable or disable the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_JPGDECEN_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_OSPI1_CLK_ENABLE()
#define | __HAL_RCC_OSPI2_CLK_ENABLE()
#define | __HAL_RCC_OCTOSPIM_CLK_ENABLE()
#define | __HAL_RCC_OTFDEC1_CLK_ENABLE()
#define | __HAL_RCC_OTFDEC2_CLK_ENABLE()
#define | __HAL_RCC_GFXMMU_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
#define | __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
#define | __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
#define | __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
#define | __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
#define | __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
#define | __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
#define | __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
Get the enable or disable status of the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
#define | __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
#define | __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
#define | __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
#define | __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
#define | __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
#define | __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
#define | __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
#define | __HAL_RCC_DMA1_CLK_ENABLE()
Enable or disable the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
Get the enable or disable status of the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
#define | __HAL_RCC_DCMI_PSSI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_ENABLE()
#define | __HAL_RCC_HASH_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_SDMMC2_CLK_ENABLE()
#define | __HAL_RCC_AHBSRAM1_CLK_ENABLE()
#define | __HAL_RCC_AHBSRAM2_CLK_ENABLE()
#define | __HAL_RCC_HSEM_CLK_ENABLE()
#define | __HAL_RCC_BDMA1_CLK_ENABLE()
#define | __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
#define | __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#define | __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define | __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
#define | __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
#define | __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
#define | __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U)
Get the enable or disable status of the AHB2 peripheral clock.
#define | __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
#define | __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
#define | __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U)
#define | __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U)
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U)
#define | __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
#define | __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
#define | __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U)
#define | __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
Enable or disable the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_BDMA2_CLK_ENABLE()
#define | __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_CLK_ENABLE()
#define | __HAL_RCC_BKPRAM_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
#define | __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
#define | __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
#define | __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
Get the enable or disable status of the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U)
#define | __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
#define | __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U)
#define | __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U)
#define | __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
#define | __HAL_RCC_LTDC_CLK_ENABLE()
Enable or disable the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_CLK_ENABLE()
#define | __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
#define | __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
#define | __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)
Get the enable or disable status of the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
#define | __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)
#define | __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC12_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_MDIOS_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
#define | __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
#define | __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
Get the enable or disable status of the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
#define | __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
#define | __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
#define | __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
#define | __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
#define | __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
#define | __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_UART9_CLK_ENABLE()
#define | __HAL_RCC_USART10_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
#define | __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
#define | __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
Get the enable or disable status of the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
#define | __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
#define | __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
#define | __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
#define | __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
#define | __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
#define | __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
Enable or disable the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM3_CLK_ENABLE()
#define | __HAL_RCC_DAC2_CLK_ENABLE()
#define | __HAL_RCC_COMP12_CLK_ENABLE()
#define | __HAL_RCC_VREF_CLK_ENABLE()
#define | __HAL_RCC_RTC_CLK_ENABLE()
#define | __HAL_RCC_DTS_CLK_ENABLE()
#define | __HAL_RCC_DFSDM2_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
#define | __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
#define | __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
#define | __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
#define | __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
#define | __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
#define | __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
#define | __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
Get the enable or disable status of the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
#define | __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)
#define | __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)
#define | __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U)
#define | __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)
#define | __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)
#define | __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)
#define | __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
#define | __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)
#define | __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)
#define | __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U)
#define | __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)
#define | __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)
#define | __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)
#define | __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U)
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Enable or disable the AHB3 peripheral reset.
#define | __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
#define | __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
#define | __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
#define | __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
#define | __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
#define | __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
#define | __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
#define | __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
#define | __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Force or release the AHB1 peripheral reset.
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Force or release the AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
#define | __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
#define | __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
#define | __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
#define | __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
#define | __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
#define | __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU)
Force or release the AHB4 peripheral reset.
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
#define | __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
#define | __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU)
Force or release the APB3 peripheral reset.
#define | __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)
#define | __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU)
Force or release the APB1 peripheral reset.
#define | __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
#define | __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Force or release the APB2 peripheral reset.
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
#define | __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
#define | __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU)
Force or release the APB4 peripheral reset.
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
#define | __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
#define | __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
#define | __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
#define | __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
#define | __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
#define | __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
#define | __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
#define | __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
#define | __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
#define | __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
#define | __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
#define | __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
#define | __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
#define | __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
#define | __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
#define | __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
#define | __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
#define | __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
#define | __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
#define | __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
#define | __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
#define | __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)
#define | __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U)
#define | __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U)
#define | __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U)
#define | __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U)
#define | __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)
#define | __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)
#define | __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)
#define | __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
#define | __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)
#define | __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U)
#define | __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U)
#define | __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U)
#define | __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U)
#define | __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)
#define | __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)
#define | __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)
#define | __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
#define | __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
#define | __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
#define | __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
#define | __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
#define | __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
#define | __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U)
Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
#define | __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
#define | __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U)
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
#define | __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
#define | __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN))
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U)
#define | __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)
#define | __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
#define | __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U)
#define | __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)
#define | __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
#define | __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
#define | __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
#define | __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)
Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
#define | __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)
#define | __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
#define | __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
#define | __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
#define | __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
#define | __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
#define | __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
#define | __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
#define | __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
#define | __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
#define | __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
#define | __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)
#define | __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U)
#define | __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)
#define | __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)
#define | __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)
#define | __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)
#define | __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U)
#define | __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)
#define | __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)
#define | __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)
#define | __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
#define | __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
Enable or disable peripheral bus clock when D3 domain is in DRUN.
#define | __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
#define | __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
#define | __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
#define | __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
#define | __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
#define | __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
#define | __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
#define | __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
#define | __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
#define | __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
#define | __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
#define | __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
#define | __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
#define | __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
#define | __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
#define | __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
#define | __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
#define | __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
#define | __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
#define | __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
#define | __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
#define | __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
#define | __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
#define | __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
#define | __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
#define | __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
#define | __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
#define | __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
#define | __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
#define | __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
#define | __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
#define | __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
#define | __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
#define | __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
#define | __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
#define | __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
#define | __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
#define | __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
#define | __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
#define | __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
#define | __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
#define | __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
#define | __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
#define | __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
#define | __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
#define | __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
#define | __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
#define | __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
#define | __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
#define | __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
#define | __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
#define | __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
#define | __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
#define | __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
#define | __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
#define | __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
Macro to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
Macro to get the HSI divider.
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
#define | __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
Macros to enable or disable the Internal oscillator (CSI).
#define | __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
#define | __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)
Macro Adjusts the Internal oscillator (CSI) calibration value.
#define | __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
#define | __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.
#define | __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
Macro to configures the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLLs clock source.
#define | __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
Macro to configure the Kernel wake up from stop clock.
#define | RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

Define Documentation

#define __HAL_RCC_ADC12_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

Definition at line 1086 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 996 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

Definition at line 5155 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

Definition at line 5132 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))

Definition at line 4598 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)

Definition at line 1134 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)

Definition at line 1113 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)

Definition at line 5208 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)

Definition at line 5185 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

Definition at line 4616 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB12_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)

Definition at line 6759 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB12_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)

Definition at line 6736 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB1_FORCE_RESET ( ) (RCC->AHB1RSTR = 0xFFFFFFFFU)

Force or release the AHB1 peripheral reset.

Definition at line 4595 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) (RCC->AHB1RSTR = 0x00U)

Definition at line 4613 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_FORCE_RESET ( ) (RCC->AHB2RSTR = 0xFFFFFFFFU)

Force or release the AHB2 peripheral reset.

Definition at line 4633 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) (RCC->AHB2RSTR = 0x00U)

Definition at line 4651 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB34_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)

Definition at line 6760 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB34_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)

Definition at line 6737 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB3_FORCE_RESET ( ) (RCC->AHB3RSTR = 0xFFFFFFFFU)

Enable or disable the AHB3 peripheral reset.

Definition at line 4531 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) (RCC->AHB3RSTR = 0x00)

Definition at line 4561 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB4_FORCE_RESET ( ) (RCC->AHB4RSTR = 0xFFFFFFFFU)

Force or release the AHB4 peripheral reset.

Definition at line 4673 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB4_RELEASE_RESET ( ) (RCC->AHB4RSTR = 0x00U)

Definition at line 4701 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)

Definition at line 6752 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)

Definition at line 6729 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))

Definition at line 1290 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1220 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))

Definition at line 5280 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))

Definition at line 5253 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)

Definition at line 1356 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)

Definition at line 1326 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)

Definition at line 5341 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)

Definition at line 5314 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))

Definition at line 1295 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1238 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))

Definition at line 5285 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))

Definition at line 5258 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)

Definition at line 1361 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)

Definition at line 1331 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)

Definition at line 5346 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)

Definition at line 5319 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_APB1H_FORCE_RESET ( ) (RCC->APB1HRSTR = 0xFFFFFFFFU)

Definition at line 4750 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1H_RELEASE_RESET ( ) (RCC->APB1HRSTR = 0x00U)

Definition at line 4782 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1L_FORCE_RESET ( ) (RCC->APB1LRSTR = 0xFFFFFFFFU)

Force or release the APB1 peripheral reset.

Definition at line 4749 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1L_RELEASE_RESET ( ) (RCC->APB1LRSTR = 0x00U)

Definition at line 4781 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFFU)

Force or release the APB2 peripheral reset.

Definition at line 4815 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00U)

Definition at line 4842 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB3_FORCE_RESET ( ) (RCC->APB3RSTR = 0xFFFFFFFFU)

Force or release the APB3 peripheral reset.

Definition at line 4731 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB3_RELEASE_RESET ( ) (RCC->APB3RSTR = 0x00U)

Definition at line 4739 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB4_FORCE_RESET ( ) (RCC->APB4RSTR = 0xFFFFFFFFU)

Force or release the APB4 peripheral reset.

Definition at line 4872 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB4_RELEASE_RESET ( ) (RCC->APB4RSTR = 0x00U)

Definition at line 4900 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AXI_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)

Definition at line 6751 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXI_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)

Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).

Note:
Parameters:
@note

Definition at line 6728 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)

Definition at line 6765 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)

Definition at line 6742 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)

Definition at line 6766 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)

Definition at line 6743 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)

Definition at line 6767 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)

Definition at line 6744 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))

Definition at line 5012 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))

Definition at line 4966 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U)

Definition at line 5109 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U)

Definition at line 5065 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))

Definition at line 5015 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))

Definition at line 4969 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U)

Definition at line 5112 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U)

Definition at line 5068 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE

Definition at line 5022 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE

Definition at line 4976 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.
The BKPSRAM is not affected by this reset.

Definition at line 7154 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Definition at line 7155 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BDMA1_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))

Definition at line 1304 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1268 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA1_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))

Definition at line 4648 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA1_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U)

Definition at line 1370 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA1_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U)

Definition at line 1340 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA1_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))

Definition at line 4666 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)

Definition at line 1551 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1478 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)

Definition at line 5406 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)

Definition at line 5375 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)

Definition at line 6673 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)

Enable or disable peripheral bus clock when D3 domain is in DRUN.

Note:
After reset (default config), peripheral clock is disabled when CPU is in CSTOP

Definition at line 6578 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)

Definition at line 4689 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U)

Definition at line 1621 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U)

Definition at line 1589 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U)

Definition at line 5476 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U)

Definition at line 5445 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA2_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)

Definition at line 4717 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_DISABLE ( ) __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/

Definition at line 1552 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_ENABLE ( ) __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/

Definition at line 1486 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/

Definition at line 5407 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/

Definition at line 5376 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_FORCE_RESET ( ) __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/

Definition at line 4690 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_IS_CLK_DISABLED ( ) __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/

Definition at line 1622 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_IS_CLK_ENABLED ( ) __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/

Definition at line 1590 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/

Definition at line 5477 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/

Definition at line 5446 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_RELEASE_RESET ( ) __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/

Definition at line 4718 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

Definition at line 1565 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1527 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

Definition at line 5414 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

Definition at line 5383 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)

Definition at line 6712 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)

Definition at line 6617 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)

Definition at line 1635 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)

Definition at line 1603 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)

Definition at line 5484 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)

Definition at line 5453 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

Definition at line 1976 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1878 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

Definition at line 5609 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

Definition at line 5573 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)

Definition at line 4771 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)

Definition at line 2049 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)

Definition at line 2016 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)

Definition at line 5683 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)

Definition at line 5650 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

Definition at line 4803 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

Definition at line 2447 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2378 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

Definition at line 5863 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

Definition at line 5835 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)

Definition at line 6697 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)

Definition at line 6602 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)

Definition at line 4888 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)

Definition at line 2509 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)

Definition at line 2481 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)

Definition at line 5927 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)

Definition at line 5899 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

Definition at line 4916 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CPU_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)

Definition at line 6753 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CPU_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)

Definition at line 6730 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))

Definition at line 1091 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1015 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))

Definition at line 5157 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))

Definition at line 5134 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))

Definition at line 4603 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U)

Definition at line 1139 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U)

Definition at line 1118 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U)

Definition at line 5210 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U)

Definition at line 5187 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))

Definition at line 4621 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

Definition at line 1980 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1910 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

Definition at line 5613 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

Definition at line 5577 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)

Definition at line 4775 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRS_IS_CLK_DISABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)

Definition at line 2053 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_ENABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)

Definition at line 2020 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)

Definition at line 5687 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)

Definition at line 5654 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

Definition at line 4807 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRYP_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

Definition at line 1283 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1179 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

Definition at line 5270 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

Definition at line 5243 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))

Definition at line 4640 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)

Definition at line 1349 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)

Definition at line 1319 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)

Definition at line 5331 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)

Definition at line 5304 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))

Definition at line 4658 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST ( __CSICalibrationValue__ )
Value:
do {                                                                                                                          \
               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
               } while(0)

Macro Adjusts the Internal oscillator (CSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal CSI RC.
Parameters:
__CSICalibrationValue__,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Definition at line 6916 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_CSION)

Definition at line 6894 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSION)

Macros to enable or disable the Internal oscillator (CSI).

Note:
The CSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
CSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the CSI.
After enabling the CSI, the application software should wait on CSIRDY flag to be set indicating that CSI clock is stable and can be used as system clock source.
When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator clock cycles.

Definition at line 6893 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

Definition at line 6932 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSIKERON)

Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the CSI ON in STOP mode allows to avoid slowing down the communication speed because of the CSI start-up time.
The enable of this function has not effect on the CSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 6931 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

Definition at line 5021 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

Definition at line 4975 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)

Definition at line 5118 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)

Definition at line 5074 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE

Definition at line 5417 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/

Definition at line 5386 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/

Definition at line 5487 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/

Definition at line 5456 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

Definition at line 1977 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1886 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

Definition at line 5610 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

Definition at line 5574 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)

Definition at line 4772 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)

Definition at line 2050 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)

Definition at line 2017 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)

Definition at line 5684 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)

Definition at line 5651 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

Definition at line 4804 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)

Definition at line 2445 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2369 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)

Definition at line 5861 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)

Definition at line 5833 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)

Definition at line 6694 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)

Definition at line 6599 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)

Definition at line 4886 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U)

Definition at line 2507 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U)

Definition at line 2479 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U)

Definition at line 5925 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U)

Definition at line 5897 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC2_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)

Definition at line 4914 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_DISABLE ( ) __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/

Definition at line 1279 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_ENABLE ( ) __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/

Definition at line 1168 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE ( ) __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/

Definition at line 5266 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE ( ) __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/

Definition at line 5239 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_FORCE_RESET ( ) __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/

Definition at line 4636 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_IS_CLK_DISABLED ( ) __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/

Definition at line 1345 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_IS_CLK_ENABLED ( ) __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/

Definition at line 1315 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED ( ) __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/

Definition at line 5327 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED ( ) __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/

Definition at line 5300 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))

Definition at line 1278 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1160 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))

Definition at line 5265 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))

ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5238 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))

Definition at line 4635 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U)

Definition at line 1344 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U)

Get the enable or disable status of the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1314 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U)

Definition at line 5326 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U)

Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5299 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))

Definition at line 4653 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_RELEASE_RESET ( ) __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/

Definition at line 4654 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

Definition at line 2231 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2192 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

Definition at line 5748 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

Definition at line 5722 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)

Definition at line 4837 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)

Definition at line 2289 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)

Definition at line 2263 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)

Definition at line 5808 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)

Definition at line 5782 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

Definition at line 4864 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)

Definition at line 2457 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2423 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)

Definition at line 5873 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)

Definition at line 5845 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)

Definition at line 6709 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)

Definition at line 6614 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)

Definition at line 4897 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U)

Definition at line 2519 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U)

Definition at line 2491 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)

Definition at line 5937 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)

Definition at line 5909 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM2_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)

Definition at line 4925 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))

Definition at line 5275 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))

Definition at line 5248 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)

Definition at line 5335 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)

Definition at line 5309 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

Definition at line 1084 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 980 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

Definition at line 5153 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5130 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

Definition at line 4596 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)

Definition at line 1132 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1111 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)

Definition at line 5206 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)

Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5183 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

Definition at line 4614 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

Definition at line 1085 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 988 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 5154 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 5131 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

Definition at line 4597 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)

Definition at line 1133 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)

Definition at line 1112 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)

Definition at line 5207 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)

Definition at line 5184 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

Definition at line 4615 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

Definition at line 882 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 783 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

Definition at line 4983 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

Definition at line 4937 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)

Definition at line 6756 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)

Definition at line 6733 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))

Definition at line 4533 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)

Definition at line 947 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)

Definition at line 918 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DMA2D_DeInit().

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)

Definition at line 5080 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)

Definition at line 5036 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

Definition at line 4563 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

Definition at line 5017 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

Definition at line 4971 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)

Definition at line 5114 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)

Definition at line 5070 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

Definition at line 5018 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

Definition at line 4972 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)

Definition at line 5115 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)

Definition at line 5071 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)

Definition at line 2454 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2413 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)

Definition at line 5870 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)

Definition at line 5842 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)

Definition at line 6706 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)

Definition at line 6611 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)

Definition at line 4894 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U)

Definition at line 2516 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U)

Definition at line 2488 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U)

Definition at line 5934 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U)

Definition at line 5906 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTS_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)

Definition at line 4922 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ECCRAM_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)

Definition at line 6769 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ECCRAM_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)

Definition at line 6746 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_EXTI_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)

Definition at line 6770 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_EXTI_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)

Definition at line 6747 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

Definition at line 1984 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1942 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

Definition at line 5617 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

Definition at line 5581 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)

Definition at line 4779 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_DISABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)

Definition at line 2057 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_ENABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)

Definition at line 2024 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)

Definition at line 5691 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)

Definition at line 5658 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

Definition at line 4811 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

Definition at line 4987 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

Definition at line 4941 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)

Definition at line 5084 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)

Definition at line 5040 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLIFT_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)

Definition at line 6761 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLIFT_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)

Definition at line 6738 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

Definition at line 886 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 801 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

Definition at line 4988 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

Definition at line 4942 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)

Definition at line 6763 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)

Definition at line 6740 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))

Definition at line 4537 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)

Definition at line 951 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)

Definition at line 922 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)

Definition at line 5085 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)

Definition at line 5041 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

Definition at line 4567 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GET_HSI_DIVIDER ( ) ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))

Macro to get the HSI divider.

Return values:
The HSI divider. The returned value can be one of the following:
  • RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset)
  • RCC_CR_HSIDIV_2 HSI oscillator divided by 2
  • RCC_CR_HSIDIV_4 HSI oscillator divided by 4
  • RCC_CR_HSIDIV_8 HSI oscillator divided by 8

Definition at line 6809 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 7333 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

#define __HAL_RCC_GET_RTC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

Definition at line 7146 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_CFGR_SWS_CSI: CSI used as system clock.
  • RCC_CFGR_SWS_HSI: HSI used as system clock.
  • RCC_CFGR_SWS_HSE: HSE used as system clock.
  • RCC_CFGR_SWS_PLL: PLL used as system clock.

Definition at line 7311 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_GFXMMU_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))

Definition at line 908 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 864 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))

Definition at line 5009 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))

Definition at line 4963 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))

Definition at line 4558 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)

Definition at line 972 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)

Definition at line 943 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U)

Definition at line 5106 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U)

Definition at line 5062 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMU_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))

Definition at line 4588 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)

Definition at line 6758 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)

Definition at line 6735 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)

Definition at line 6768 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)

Definition at line 6745 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIO_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)

Definition at line 6676 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIO_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)

Definition at line 6581 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

Definition at line 1536 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1379 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

Definition at line 5391 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5360 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)

Definition at line 4674 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)

Definition at line 1605 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)

Get the enable or disable status of the AHB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1574 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)

Definition at line 5461 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)

Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5430 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

Definition at line 4702 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

Definition at line 1537 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1387 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

Definition at line 5392 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

Definition at line 5361 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)

Definition at line 4675 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)

Definition at line 1606 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)

Definition at line 1575 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)

Definition at line 5462 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)

Definition at line 5431 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

Definition at line 4703 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

Definition at line 1538 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1395 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

Definition at line 5393 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

Definition at line 5362 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)

Definition at line 4676 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)

Definition at line 1607 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)

Definition at line 1576 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)

Definition at line 5463 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)

Definition at line 5432 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

Definition at line 4704 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

Definition at line 1539 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1403 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

Definition at line 5394 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

Definition at line 5363 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)

Definition at line 4677 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)

Definition at line 1608 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)

Definition at line 1577 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)

Definition at line 5464 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)

Definition at line 5433 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

Definition at line 4705 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

Definition at line 1540 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1411 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

Definition at line 5395 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

Definition at line 5364 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)

Definition at line 4678 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)

Definition at line 1609 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)

Definition at line 1578 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)

Definition at line 5465 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)

Definition at line 5434 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

Definition at line 4706 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

Definition at line 1541 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1419 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

Definition at line 5396 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

Definition at line 5365 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)

Definition at line 4679 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)

Definition at line 1610 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)

Definition at line 1579 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)

Definition at line 5466 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)

Definition at line 5435 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

Definition at line 4707 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

Definition at line 1542 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1427 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

Definition at line 5397 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

Definition at line 5366 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)

Definition at line 4680 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)

Definition at line 1611 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)

Definition at line 1580 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)

Definition at line 5467 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)

Definition at line 5436 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

Definition at line 4708 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

Definition at line 1543 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1435 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

Definition at line 5398 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

Definition at line 5367 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)

Definition at line 4681 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)

Definition at line 1612 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)

Definition at line 1581 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)

Definition at line 5468 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)

Definition at line 5437 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

Definition at line 4709 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

Definition at line 1544 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1443 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

Definition at line 5399 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

Definition at line 5368 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)

Definition at line 4682 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)

Definition at line 1613 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)

Definition at line 1582 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)

Definition at line 5469 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)

Definition at line 5438 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)

Definition at line 4710 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

Definition at line 1545 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1451 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

Definition at line 5400 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

Definition at line 5369 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)

Definition at line 4683 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)

Definition at line 1614 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)

Definition at line 1583 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)

Definition at line 5470 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)

Definition at line 5439 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

Definition at line 4711 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

Definition at line 1546 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1459 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

Definition at line 5401 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

Definition at line 5370 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)

Definition at line 4684 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)

Definition at line 1615 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)

Definition at line 1584 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)

Definition at line 5471 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)

Definition at line 5440 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

Definition at line 4712 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

Definition at line 1284 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1187 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

Definition at line 5271 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

Definition at line 5244 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))

Definition at line 4641 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)

Definition at line 1350 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)

Definition at line 1320 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)

Definition at line 5332 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)

Definition at line 5305 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))

Definition at line 4659 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                               \
                      if ((__STATE__) == RCC_HSE_ON)                   \
                      {                                                \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
                      }                                                \
                      else if ((__STATE__) == RCC_HSE_OFF)             \
                      {                                                \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
                      }                                                \
                      else if ((__STATE__) == RCC_HSE_BYPASS)          \
                      {                                                \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
                      }                                                \
                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
                      {                                                \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
                      }                                                \
                      else                                             \
                      {                                                \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
                      }                                                \
                    } while(0)

Macro to configure the External High Speed oscillator (__HSE__).

Note:
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__,: specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator.
  • RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

Definition at line 6966 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSEM_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))

Definition at line 1301 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1258 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))

Definition at line 4645 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U)

Definition at line 1367 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U)

Definition at line 1337 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))

Definition at line 4663 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSI48_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

Definition at line 6875 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSI48ON);

Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

Note:
After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be used to clock the USB.
The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

Definition at line 6873 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICalibrationValue__ ) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICalibrationValue__,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x7F (3F for Rev Y device).

Definition at line 6850 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CONFIG ( __STATE__ ) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))

Macro to enable or disable the Internal High Speed oscillator (HSI).

Note:
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.
HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.
The HSI is stopped by hardware when entering STOP and STANDBY modes.
Parameters:
__STATE__ specifies the new state of the HSI. This parameter can be one of the following values:
  • RCC_HSI_OFF turn OFF the HSI oscillator
  • RCC_HSI_ON turn ON the HSI oscillator
  • RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
  • RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
  • RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
  • RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 6797 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Definition at line 6827 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 6826 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 6863 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI start-up time.
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 6862 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

Definition at line 1973 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1854 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

Definition at line 5606 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

Definition at line 5570 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)

Definition at line 4768 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)

Definition at line 2046 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)

Definition at line 2013 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)

Definition at line 5680 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)

Definition at line 5647 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

Definition at line 4800 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

Definition at line 1974 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1862 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

Definition at line 5607 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

Definition at line 5571 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)

Definition at line 4769 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)

Definition at line 2047 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)

Definition at line 2014 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)

Definition at line 5681 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)

Definition at line 5648 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

Definition at line 4801 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

Definition at line 1975 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1870 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

Definition at line 5608 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

Definition at line 5572 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)

Definition at line 4770 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)

Definition at line 2048 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)

Definition at line 2015 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)

Definition at line 5682 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)

Definition at line 5649 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

Definition at line 4802 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

Definition at line 2435 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2324 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

Definition at line 5851 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

Definition at line 5823 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)

Definition at line 6685 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)

Definition at line 6590 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)

Definition at line 4876 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)

Definition at line 2497 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)

Definition at line 2469 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)

Definition at line 5915 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)

Definition at line 5887 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

Definition at line 4904 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))

Definition at line 5000 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))

Definition at line 4954 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))

Definition at line 4549 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)

Definition at line 5097 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U)

Definition at line 5053 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_IOMNGR_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))

Definition at line 4579 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

Definition at line 5019 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

Definition at line 4973 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)

Definition at line 5116 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)

Definition at line 5072 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

Definition at line 4985 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

Definition at line 4939 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)

Definition at line 5082 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)

Definition at line 5038 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

Definition at line 884 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 792 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)

Definition at line 949 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)

Definition at line 920 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECRST_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))

Definition at line 4535 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECRST_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))

Definition at line 4565 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JTAG_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)

Definition at line 6771 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JTAG_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)

Definition at line 6748 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG ( __RCC_STOPKERWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))

Macro to configure the Kernel wake up from stop clock.

Parameters:
__RCC_STOPKERWUCLK__,: specifies the Kernel clock source used after wake up from stop This parameter can be one of the following values:
  • RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
  • RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
Return values:
None

Definition at line 7424 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_KerWakeUpStopCLKConfig().

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

Definition at line 1960 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1780 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

Definition at line 5593 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

Definition at line 5557 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)

Definition at line 4760 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)

Definition at line 2035 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)

Definition at line 2002 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)

Definition at line 5669 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)

Definition at line 5636 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

Definition at line 4792 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

Definition at line 2436 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2332 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

Definition at line 5852 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

Definition at line 5824 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)

Definition at line 6688 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)

Definition at line 6593 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)

Definition at line 4877 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)

Definition at line 2498 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)

Definition at line 2470 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)

Definition at line 5916 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)

Definition at line 5888 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

Definition at line 4905 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM3_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

Definition at line 2437 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2340 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

Definition at line 5853 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

Definition at line 5825 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)

Definition at line 6691 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)

Definition at line 6596 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)

Definition at line 4878 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)

Definition at line 2499 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)

Definition at line 2471 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)

Definition at line 5917 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)

Definition at line 5889 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

Definition at line 4906 of file stm32h7xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

Definition at line 2433 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2308 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

Definition at line 5849 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

Definition at line 5821 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)

Definition at line 6679 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)

Definition at line 6584 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)

Definition at line 4874 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)

Definition at line 2495 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)

Definition at line 2467 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)

Definition at line 5913 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)

Definition at line 5885 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

Definition at line 4902 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
Parameters:
__LSEDRIVE__,: specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Return values:
None

Definition at line 7402 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE ( ) CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 6944 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 6943 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LTDC_CLK_DISABLE ( ) (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

Definition at line 1673 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1645 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE ( ) (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

Definition at line 5509 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE ( ) (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5501 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)

Definition at line 6757 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)

Definition at line 6734 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_FORCE_RESET ( ) (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)

Definition at line 4733 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_IS_CLK_DISABLED ( ) ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)

Definition at line 1694 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_IS_CLK_ENABLED ( ) ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)

Get the enable or disable status of the APB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1687 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)

Definition at line 5533 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)

Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5525 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_RELEASE_RESET ( ) (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)

Definition at line 4741 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

Definition at line 1983 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1934 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

Definition at line 5616 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

Definition at line 5580 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)

Definition at line 4778 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_IS_CLK_DISABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)

Definition at line 2056 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_IS_CLK_ENABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)

Definition at line 2023 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)

Definition at line 5690 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)

Definition at line 5657 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

Definition at line 4810 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

Definition at line 881 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 775 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

Definition at line 4982 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 4936 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)

Definition at line 6755 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)

Definition at line 6732 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))

Definition at line 4532 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)

Definition at line 946 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)

Get the enable or disable status of the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 917 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)

Definition at line 5079 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)

Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5035 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

Definition at line 4562 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)

Definition at line 6764 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)

Definition at line 6741 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)

Definition at line 6762 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)

Definition at line 6739 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPIM_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))

Definition at line 899 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPIM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 837 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)

Definition at line 963 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)

Definition at line 934 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

Definition at line 1982 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1926 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

Definition at line 5615 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

Definition at line 5579 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)

Definition at line 4777 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_DISABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)

Definition at line 2055 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_ENABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)

Definition at line 2022 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)

Definition at line 5689 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)

Definition at line 5656 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

Definition at line 4809 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))

Definition at line 892 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 819 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))

Definition at line 4994 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))

Definition at line 4948 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))

Definition at line 4542 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)

Definition at line 957 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)

Definition at line 927 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U)

Definition at line 5091 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U)

Definition at line 5047 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI1_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))

Definition at line 4572 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))

Definition at line 895 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 828 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))

Definition at line 4997 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))

Definition at line 4951 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))

Definition at line 4546 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)

Definition at line 960 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)

Definition at line 930 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U)

Definition at line 5094 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U)

Definition at line 5050 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OSPI2_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))

Definition at line 4576 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))

Definition at line 902 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 846 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))

Definition at line 5003 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))

Definition at line 4957 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))

Definition at line 4552 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)

Definition at line 966 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)

Definition at line 937 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U)

Definition at line 5100 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)

Definition at line 5056 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC1_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))

Definition at line 4582 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))

Definition at line 905 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 855 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))

Definition at line 5006 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))

Definition at line 4960 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))

Definition at line 4555 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)

Definition at line 969 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)

Definition at line 940 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U)

Definition at line 5103 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)

Definition at line 5059 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OTFDEC2_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))

Definition at line 4585 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSOURCE__,
 |  | __PLLM1__,
 |  | __PLLN1__,
 |  | __PLLP1__,
 |  | __PLLQ1__,
 |  | __PLLR1__
 | ) |
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
                    } while(0)

Macro to configures the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__RCC_PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Note:
This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
Parameters:
__PLLM1__,: specifies the division factor for PLL VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLLN1__,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
Parameters:
__PLLP1__,: specifies the division factor for system clock. This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
__PLLQ1__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLLR1__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Note:
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
Return values:
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 7237 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

Definition at line 7165 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL1ON)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 7164 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLLs clock source.

Note:
This function must be used only when all PLLs are disabled.
Parameters:
__PLLSOURCE__,: specifies the PLLs entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Definition at line 7253 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLL_VCIRANGE ( __RCC_PLL1VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))

Macro to select the PLL1 reference frequency range.

Parameters:
__RCC_PLL1VCIRange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 7284 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_VCORANGE ( __RCC_PLL1VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))

Macro to select the PLL1 reference frequency range.

Parameters:
__RCC_PLL1VCORange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
  • RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 7298 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __RCC_PLL1ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

Definition at line 7184 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __RCC_PLL1ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

Note:
Enabling/disabling those Clocks can be done only when the PLL is disabled. This is mainly used to save Power. (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
Parameters:
__RCC_PLL1ClockOut__,: specifies the PLL clock to be outputted This parameter can be one of the following values:
  • RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 7182 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLFRACN_CONFIG ( __RCC_PLL1FRACN__ ) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)

Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
Parameters:
__RCC_PLL1FRACN__,: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191
Note:
Warning: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:
None

Definition at line 7272 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLFRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

Definition at line 7194 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLFRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
Return values:
None

Definition at line 7192 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_RNG_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

Definition at line 1285 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1195 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

Definition at line 5272 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

Definition at line 5245 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))

Definition at line 4642 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)

Definition at line 1351 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)

Definition at line 1321 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)

Definition at line 5333 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)

Definition at line 5306 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

Definition at line 4660 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

Definition at line 2449 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2404 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

Definition at line 5865 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

Definition at line 5837 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)

Definition at line 6703 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)

Definition at line 6608 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKPRESCALER ( __RTCCLKSource__ )
Value:
(((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by a Power On Reset (POR).
Parameters:
__RTCCLKSource__,: specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Definition at line 7139 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CONFIG ( __RTCCLKSource__ )
Value:
do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
                                                   } while (0)

Definition at line 7142 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Definition at line 7116 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 7115 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)

Definition at line 2511 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)

Definition at line 2483 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)

Definition at line 5929 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)

Definition at line 5901 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

Definition at line 2226 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2166 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

Definition at line 5743 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

Definition at line 5717 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)

Definition at line 4832 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)

Definition at line 2284 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)

Definition at line 2258 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)

Definition at line 5803 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)

Definition at line 5777 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

Definition at line 4859 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

Definition at line 2227 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2174 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

Definition at line 5744 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

Definition at line 5718 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)

Definition at line 4833 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)

Definition at line 2285 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)

Definition at line 2259 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)

Definition at line 5804 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)

Definition at line 5778 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)

Definition at line 4860 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

Definition at line 897 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 872 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

Definition at line 4992 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

Definition at line 4946 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))

Definition at line 4544 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)

Definition at line 955 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)

Definition at line 932 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)

Definition at line 5089 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)

Definition at line 5045 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

Definition at line 4574 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

Definition at line 1286 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1203 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

Definition at line 5273 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

Definition at line 5246 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))

Definition at line 4643 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)

Definition at line 1352 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)

Definition at line 1322 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)

Definition at line 5337 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)

Definition at line 5307 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

Definition at line 4661 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC_CLKGA_DISABLE ( ) (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)

Definition at line 6754 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC_CLKGA_ENABLE ( ) (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)

Definition at line 6731 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

Definition at line 1968 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1814 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

Definition at line 5601 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

Definition at line 5565 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)

Definition at line 4763 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)

Definition at line 2041 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)

Definition at line 2008 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)

Definition at line 5675 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)

Definition at line 5642 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

Definition at line 4795 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

Definition at line 2220 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2118 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

Definition at line 5737 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

Definition at line 5711 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)

Definition at line 4826 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)

Definition at line 2278 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)

Definition at line 2252 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)

Definition at line 5797 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)

Definition at line 5771 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

Definition at line 4853 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

Definition at line 1966 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1798 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

Definition at line 5599 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

Definition at line 5563 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)

Definition at line 4761 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)

Definition at line 2039 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)

Definition at line 2006 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)

Definition at line 5673 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)

Definition at line 5640 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

Definition at line 4793 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

Definition at line 1967 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1806 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

Definition at line 5600 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

Definition at line 5564 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)

Definition at line 4762 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)

Definition at line 2040 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)

Definition at line 2007 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)

Definition at line 5674 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)

Definition at line 5641 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

Definition at line 4794 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

Definition at line 2221 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2126 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

Definition at line 5738 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

Definition at line 5712 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)

Definition at line 4827 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)

Definition at line 2279 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)

Definition at line 2253 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)

Definition at line 5798 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)

Definition at line 5772 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

Definition at line 4854 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

Definition at line 2225 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2158 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

Definition at line 5742 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

Definition at line 5716 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)

Definition at line 4831 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)

Definition at line 2283 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)

Definition at line 2257 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)

Definition at line 5802 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)

Definition at line 5776 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

Definition at line 4858 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

Definition at line 2434 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2316 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

Definition at line 5850 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

Definition at line 5822 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)

Definition at line 6682 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)

Definition at line 6587 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)

Definition at line 4875 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)

Definition at line 2496 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)

Definition at line 2468 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)

Definition at line 5914 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)

Definition at line 5886 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

Definition at line 4903 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)

Definition at line 1563 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1518 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))

Definition at line 5416 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN))

Definition at line 5385 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)

Definition at line 6715 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)

Definition at line 6620 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U)

Definition at line 1633 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)

Definition at line 1601 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)

Definition at line 5486 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)

Definition at line 5455 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

Definition at line 1981 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1918 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

Definition at line 5614 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

Definition at line 5578 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)

Definition at line 4776 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)

Definition at line 2054 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED ( ) ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)

Definition at line 2021 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)

Definition at line 5688 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)

Definition at line 5655 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

Definition at line 4808 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

Definition at line 2432 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 2300 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_GPIO_Init(), HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

Definition at line 5848 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5820 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)

Definition at line 4873 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)

Definition at line 2494 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)

Get the enable or disable status of the APB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 2466 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)

Definition at line 5912 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)

Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5884 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

Definition at line 4901 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCLK_CONFIG ( __RCC_SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__RCC_SYSCLKSOURCE__,: specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

Definition at line 7323 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

Definition at line 1957 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1756 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

Definition at line 5590 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

Definition at line 5554 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)

Definition at line 4757 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)

Definition at line 2032 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)

Definition at line 1999 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)

Definition at line 5666 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)

Definition at line 5633 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

Definition at line 4789 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

Definition at line 1958 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1764 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

Definition at line 5591 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

Definition at line 5555 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)

Definition at line 4758 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)

Definition at line 2033 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)

Definition at line 2000 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)

Definition at line 5667 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)

Definition at line 5634 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

Definition at line 4790 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

Definition at line 1959 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1772 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

Definition at line 5592 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

Definition at line 5556 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)

Definition at line 4759 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)

Definition at line 2034 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)

Definition at line 2001 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)

Definition at line 5668 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)

Definition at line 5635 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

Definition at line 4791 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

Definition at line 2222 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2134 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

Definition at line 5739 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

Definition at line 5713 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)

Definition at line 4828 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)

Definition at line 2280 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)

Definition at line 2254 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)

Definition at line 5799 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)

Definition at line 5773 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

Definition at line 4855 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

Definition at line 2223 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2142 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

Definition at line 5740 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

Definition at line 5714 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)

Definition at line 4829 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)

Definition at line 2281 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)

Definition at line 2255 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)

Definition at line 5800 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)

Definition at line 5774 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

Definition at line 4856 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

Definition at line 2224 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2150 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

Definition at line 5741 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

Definition at line 5715 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)

Definition at line 4830 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)

Definition at line 2282 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)

Definition at line 2256 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)

Definition at line 5801 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)

Definition at line 5775 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

Definition at line 4857 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

Definition at line 2210 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 2066 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

Definition at line 5727 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5701 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)

Definition at line 4816 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)

Definition at line 2268 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 2242 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)

Definition at line 5787 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)

Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5761 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

Definition at line 4843 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

Definition at line 1951 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1708 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

Definition at line 5584 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 5548 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)

Definition at line 4751 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)

Definition at line 2026 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1993 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)

Definition at line 5660 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)

Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 5627 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

Definition at line 4783 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

Definition at line 1952 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1716 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

Definition at line 5585 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

Definition at line 5549 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)

Definition at line 4752 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)

Definition at line 2027 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)

Definition at line 1994 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)

Definition at line 5661 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)

Definition at line 5628 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

Definition at line 4784 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

Definition at line 1953 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1724 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

Definition at line 5586 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

Definition at line 5550 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)

Definition at line 4753 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)

Definition at line 2028 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)

Definition at line 1995 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)

Definition at line 5662 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)

Definition at line 5629 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

Definition at line 4785 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

Definition at line 1954 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1732 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

Definition at line 5587 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

Definition at line 5551 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)

Definition at line 4754 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)

Definition at line 2029 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)

Definition at line 1996 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)

Definition at line 5663 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)

Definition at line 5630 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

Definition at line 4786 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

Definition at line 1955 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1740 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

Definition at line 5588 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

Definition at line 5552 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)

Definition at line 4755 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)

Definition at line 2030 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)

Definition at line 1997 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)

Definition at line 5664 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)

Definition at line 5631 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

Definition at line 4787 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

Definition at line 1956 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1748 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

Definition at line 5589 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

Definition at line 5553 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)

Definition at line 4756 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)

Definition at line 2031 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)

Definition at line 1998 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)

Definition at line 5665 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)

Definition at line 5632 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

Definition at line 4788 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

Definition at line 2211 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2074 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

Definition at line 5728 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

Definition at line 5702 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)

Definition at line 4817 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)

Definition at line 2269 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)

Definition at line 2243 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)

Definition at line 5788 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)

Definition at line 5762 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

Definition at line 4844 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

Definition at line 1971 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1838 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

Definition at line 5604 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

Definition at line 5568 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)

Definition at line 4766 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)

Definition at line 2044 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)

Definition at line 2011 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)

Definition at line 5678 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)

Definition at line 5645 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

Definition at line 4798 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

Definition at line 1972 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1846 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

Definition at line 5605 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

Definition at line 5569 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)

Definition at line 4767 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)

Definition at line 2045 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)

Definition at line 2012 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)

Definition at line 5679 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)

Definition at line 5646 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

Definition at line 4799 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

Definition at line 1978 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1894 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

Definition at line 5611 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

Definition at line 5575 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)

Definition at line 4773 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)

Definition at line 2051 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)

Definition at line 2018 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)

Definition at line 5685 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)

Definition at line 5652 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

Definition at line 4805 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

Definition at line 1979 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1902 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

Definition at line 5612 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

Definition at line 5576 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)

Definition at line 4774 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)

Definition at line 2052 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)

Definition at line 2019 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)

Definition at line 5686 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)

Definition at line 5653 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

Definition at line 4806 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)

Definition at line 2215 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2099 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)

Definition at line 5732 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)

Definition at line 5706 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)

Definition at line 4821 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)

Definition at line 2273 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)

Definition at line 2247 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)

Definition at line 5766 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART9_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)

Definition at line 4848 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)

Definition at line 2218 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2109 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)

Definition at line 5735 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)

Definition at line 5709 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)

Definition at line 4824 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)

Definition at line 2276 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)

Definition at line 2250 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)

Definition at line 5795 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)

Definition at line 5769 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART10_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)

Definition at line 4851 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

Definition at line 2212 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2082 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

Definition at line 5729 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

Definition at line 5703 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)

Definition at line 4818 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)

Definition at line 2270 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)

Definition at line 2244 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)

Definition at line 5789 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)

Definition at line 5763 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

Definition at line 4845 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

Definition at line 1969 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1822 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

Definition at line 5602 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

Definition at line 5566 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)

Definition at line 4764 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)

Definition at line 2042 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)

Definition at line 2009 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)

Definition at line 5676 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)

Definition at line 5643 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

Definition at line 4796 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

Definition at line 1970 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1830 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

Definition at line 5603 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

Definition at line 5567 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)

Definition at line 4765 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)

Definition at line 2043 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)

Definition at line 2010 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)

Definition at line 5677 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)

Definition at line 5644 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

Definition at line 4797 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

Definition at line 2213 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2090 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

Definition at line 5730 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

Definition at line 5704 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)

Definition at line 4819 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)

Definition at line 2271 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)

Definition at line 2245 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)

Definition at line 5790 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)

Definition at line 5764 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

Definition at line 4846 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)

Definition at line 5792 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

Definition at line 1098 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1050 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

Definition at line 5169 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

Definition at line 5146 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))

Definition at line 4608 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)

Definition at line 1146 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)

Definition at line 1125 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)

Definition at line 5222 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)

Definition at line 5199 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

Definition at line 4626 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

Definition at line 1099 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1058 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

Definition at line 5170 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

Definition at line 5147 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)

Definition at line 1147 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)

Definition at line 1126 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)

Definition at line 5223 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)

Definition at line 5200 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

Definition at line 2448 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 2386 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

Definition at line 5864 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

Definition at line 5836 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLKAM_DISABLE ( ) (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)

Definition at line 6700 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLKAM_ENABLE ( ) (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)

Definition at line 6605 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)

Definition at line 4889 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_IS_CLK_DISABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)

Definition at line 2510 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)

Definition at line 2482 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)

Definition at line 5928 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)

Definition at line 5900 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

Definition at line 4917 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG ( __RCC_STOPWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))

Macro to configure the wake up from stop clock.

Parameters:
__RCC_STOPWUCLK__,: specifies the clock source used after wake up from stop This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
  • RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
Return values:
None

Definition at line 7413 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define __HAL_RCC_WWDG1_CLK_DISABLE ( ) (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

Definition at line 1678 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1664 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE ( ) (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

Definition at line 5514 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE ( ) (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

Definition at line 5506 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_IS_CLK_DISABLED ( ) ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)

Definition at line 1699 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_IS_CLK_ENABLED ( ) ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)

Definition at line 1692 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)

Definition at line 5538 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)

Definition at line 5530 of file stm32h7xx_hal_rcc.h.

#define RCC_GET_PLL_OSCSOURCE ( ) ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

Definition at line 7597 of file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms */
#define | CSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | RCC_DBP_TIMEOUT_VALUE (100U)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Define Documentation

#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */

Definition at line 7662 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */

Definition at line 7659 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 7656 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */

Definition at line 7658 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */

Definition at line 7657 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */

Definition at line 7660 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */

Definition at line 7661 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define RCC_DBP_TIMEOUT_VALUE (100U)

Definition at line 7663 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 7664 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Private Defines

Defines
Private Defines
RCCEx

Defines

#define | PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define | PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U

Define Documentation

#define DIVIDER_P_UPDATE 0U

Definition at line 46 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig(), RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

#define DIVIDER_Q_UPDATE 1U

Definition at line 47 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig(), RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

#define DIVIDER_R_UPDATE 2U

Definition at line 48 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */

Definition at line 43 of file stm32h7xx_hal_rcc_ex.c.

Referenced by RCCEx_PLL2_Config().

#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */

Definition at line 44 of file stm32h7xx_hal_rcc_ex.c.

Referenced by RCCEx_PLL3_Config().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register are set to their reset values.

Function Documentation

uint32_t HAL_RCCEx_GetD1PCLK1Freq ( void )

Returns the D1PCLK1 frequency.

Note:
Each time D1PCLK1 changes, this function must be called to update the right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
D1PCLK1 frequency

Definition at line 2406 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetHCLKFreq().

uint32_t HAL_RCCEx_GetD1SysClockFreq ( void )

Returns the main Core frequency.

Note:
Each time core clock changes, this function must be called to update the right system core clock value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 2645 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetSysClockFreq().

Referenced by HAL_RCC_GetHCLKFreq().

uint32_t HAL_RCCEx_GetD3PCLK1Freq ( void )

Returns the D3PCLK1 frequency.

Note:
Each time D3PCLK1 changes, this function must be called to update the right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
D3PCLK1 frequency

Definition at line 2423 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_DTS_GetTemperature(), HAL_RCCEx_GetPeriphCLKFreq(), and UART_SetConfig().

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks : (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. SAI4A*, SAI4B*, SPI6, RTC, TIM).
Return values:
None (*) : Available on some STM32H7 lines only.

Definition at line 1545 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_CLKP_SOURCE, __HAL_RCC_GET_DFSDM1_SOURCE, __HAL_RCC_GET_DFSDM2_SOURCE, __HAL_RCC_GET_FDCAN_SOURCE, __HAL_RCC_GET_FMC_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPTIM345_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_OSPI_SOURCE, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2A_SOURCE, __HAL_RCC_GET_SAI2B_SOURCE, __HAL_RCC_GET_SDMMC_SOURCE, __HAL_RCC_GET_SPDIFRX_SOURCE, __HAL_RCC_GET_SPI123_SOURCE, __HAL_RCC_GET_SPI45_SOURCE, __HAL_RCC_GET_SPI6_SOURCE, __HAL_RCC_GET_SWPMI1_SOURCE, __HAL_RCC_GET_USART16_SOURCE, __HAL_RCC_GET_USART234578_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::CkperClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm2ClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::FmcClockSelection, RCC_PeriphCLKInitTypeDef::I2c123ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::OspiClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLL2, RCC_PLL2InitTypeDef::PLL2M, RCC_PLL2InitTypeDef::PLL2N, RCC_PLL2InitTypeDef::PLL2P, RCC_PLL2InitTypeDef::PLL2Q, RCC_PLL2InitTypeDef::PLL2R, RCC_PLL2InitTypeDef::PLL2RGE, RCC_PLL2InitTypeDef::PLL2VCOSEL, RCC_PeriphCLKInitTypeDef::PLL3, RCC_PLL3InitTypeDef::PLL3M, RCC_PLL3InitTypeDef::PLL3N, RCC_PLL3InitTypeDef::PLL3P, RCC_PLL3InitTypeDef::PLL3Q, RCC_PLL3InitTypeDef::PLL3R, RCC_PLL3InitTypeDef::PLL3RGE, RCC_PLL3InitTypeDef::PLL3VCOSEL, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_CKPER, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_DFSDM2, RCC_PERIPHCLK_DSI, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_FMC, RCC_PERIPHCLK_I2C123, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPTIM345, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LTDC, RCC_PERIPHCLK_OSPI, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2A, RCC_PERIPHCLK_SAI2B, RCC_PERIPHCLK_SDMMC, RCC_PERIPHCLK_SPDIFRX, RCC_PERIPHCLK_SPI123, RCC_PERIPHCLK_SPI45, RCC_PERIPHCLK_SPI6, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_TIM, RCC_PERIPHCLK_USART16, RCC_PERIPHCLK_USART234578, RCC_PERIPHCLK_USB, RCC_TIMPRES_ACTIVATED, RCC_TIMPRES_DESACTIVATED, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2AClockSelection, RCC_PeriphCLKInitTypeDef::Sai2BClockSelection, RCC_PeriphCLKInitTypeDef::SdmmcClockSelection, RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection, RCC_PeriphCLKInitTypeDef::Spi123ClockSelection, RCC_PeriphCLKInitTypeDef::Spi45ClockSelection, RCC_PeriphCLKInitTypeDef::Spi6ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Usart16ClockSelection, RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for a given peripheral(SAI..)

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk,: Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
  • RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*)
  • RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
  • RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
  • RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
  • RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
  • RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
  • RCC_PERIPHCLK_ADC : ADC peripheral clock
  • RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
  • RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock
Return values:
Frequency in KHz

(*) : Available on some STM32H7 lines only.

Definition at line 1725 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_CLKP_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2A_SOURCE, __HAL_RCC_GET_SAI2B_SOURCE, __HAL_RCC_GET_SDMMC_SOURCE, __HAL_RCC_GET_SPI123_SOURCE, __HAL_RCC_GET_SPI6_SOURCE, CSI_VALUE, EXTERNAL_CLOCK_VALUE, HAL_RCCEx_GetD3PCLK1Freq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSE_VALUE, HSI_VALUE, PLL1_ClocksTypeDef::PLL1_Q_Frequency, PLL2_ClocksTypeDef::PLL2_P_Frequency, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL2_ClocksTypeDef::PLL2_R_Frequency, PLL3_ClocksTypeDef::PLL3_P_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, PLL3_ClocksTypeDef::PLL3_R_Frequency, RCC_ADCCLKSOURCE_CLKP, RCC_ADCCLKSOURCE_PLL2, RCC_ADCCLKSOURCE_PLL3, RCC_CLKPSOURCE_CSI, RCC_CLKPSOURCE_HSE, RCC_CLKPSOURCE_HSI, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2A, RCC_PERIPHCLK_SAI2B, RCC_PERIPHCLK_SDMMC, RCC_PERIPHCLK_SPI123, RCC_PERIPHCLK_SPI6, RCC_SAI1CLKSOURCE_CLKP, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLL2, RCC_SAI1CLKSOURCE_PLL3, RCC_SAI2ACLKSOURCE_CLKP, RCC_SAI2ACLKSOURCE_PIN, RCC_SAI2ACLKSOURCE_PLL2, RCC_SAI2ACLKSOURCE_PLL3, RCC_SAI2BCLKSOURCE_CLKP, RCC_SAI2BCLKSOURCE_PIN, RCC_SAI2BCLKSOURCE_PLL2, RCC_SAI2BCLKSOURCE_PLL3, RCC_SDMMCCLKSOURCE_PLL, RCC_SDMMCCLKSOURCE_PLL2, RCC_SPI123CLKSOURCE_CLKP, RCC_SPI123CLKSOURCE_PIN, RCC_SPI123CLKSOURCE_PLL, RCC_SPI123CLKSOURCE_PLL2, RCC_SPI123CLKSOURCE_PLL3, RCC_SPI6CLKSOURCE_CSI, RCC_SPI6CLKSOURCE_D3PCLK1, RCC_SPI6CLKSOURCE_HSE, RCC_SPI6CLKSOURCE_HSI, RCC_SPI6CLKSOURCE_PIN, RCC_SPI6CLKSOURCE_PLL2, and RCC_SPI6CLKSOURCE_PLL3.

Referenced by ADC_ConfigureBoostMode(), HAL_I2S_Init(), HAL_SAI_Init(), and HAL_SD_InitCard().

void HAL_RCCEx_GetPLL1ClockFreq ( PLL1_ClocksTypeDef * PLL1_Clocks )

Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.

Note:
The PLL1 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL1CLK changes, this function must be called to update the right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL1_Clocks structure.
Return values:
None

Definition at line 2584 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL1_ClocksTypeDef::PLL1_P_Frequency, PLL1_ClocksTypeDef::PLL1_Q_Frequency, PLL1_ClocksTypeDef::PLL1_R_Frequency, RCC_FLAG_HSIDIV, RCC_PLLSOURCE_CSI, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

void HAL_RCCEx_GetPLL2ClockFreq ( PLL2_ClocksTypeDef * PLL2_Clocks )

Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.

Note:
The PLL2 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL2CLK changes, this function must be called to update the right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL2_Clocks structure.
Return values:
None

Definition at line 2447 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL2_ClocksTypeDef::PLL2_P_Frequency, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL2_ClocksTypeDef::PLL2_R_Frequency, RCC_FLAG_HSIDIV, RCC_PLLSOURCE_CSI, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCCEx_GetPLL3ClockFreq ( PLL3_ClocksTypeDef * PLL3_Clocks )

Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.

Note:
The PLL3 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL3CLK changes, this function must be called to update the right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL3_Clocks structure.
Return values:
None

Definition at line 2516 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL3_ClocksTypeDef::PLL3_P_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, PLL3_ClocksTypeDef::PLL3_R_Frequency, RCC_FLAG_HSIDIV, RCC_PLLSOURCE_CSI, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, SAI4A*, SAI4B*, SPI6, RTC).
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values.

(*) : Available on some STM32H7 lines only.

Return values:
HAL status

Definition at line 98 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_CLKP_CONFIG, __HAL_RCC_DFSDM1_CONFIG, __HAL_RCC_DFSDM2_CONFIG, __HAL_RCC_FDCAN_CONFIG, __HAL_RCC_FMC_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_I2C123_CONFIG, __HAL_RCC_I2C4_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPTIM345_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_OSPI_CONFIG, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_RNG_CONFIG, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_SAI2A_CONFIG, __HAL_RCC_SAI2B_CONFIG, __HAL_RCC_SDMMC_CONFIG, __HAL_RCC_SPDIFRX_CONFIG, __HAL_RCC_SPI123_CONFIG, __HAL_RCC_SPI45_CONFIG, __HAL_RCC_SPI6_CONFIG, __HAL_RCC_SWPMI1_CONFIG, __HAL_RCC_TIMCLKPRESCALER, __HAL_RCC_USART16_CONFIG, __HAL_RCC_USART234578_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::CkperClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm2ClockSelection, DIVIDER_P_UPDATE, DIVIDER_Q_UPDATE, DIVIDER_R_UPDATE, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::FmcClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c123ClockSelection, RCC_PeriphCLKInitTypeDef::I2c4ClockSelection, IS_RCC_CLKPSOURCE, IS_RCC_DFSDM1CLKSOURCE, IS_RCC_DFSDM2CLKSOURCE, IS_RCC_I2C123CLKSOURCE, IS_RCC_I2C4CLKSOURCE, IS_RCC_RTCCLKSOURCE, IS_RCC_SDMMC, IS_RCC_SWPMI1CLKSOURCE, IS_RCC_TIMPRES, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::OspiClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLL2, RCC_PeriphCLKInitTypeDef::PLL3, RCC_ADCCLKSOURCE_CLKP, RCC_ADCCLKSOURCE_PLL2, RCC_ADCCLKSOURCE_PLL3, RCC_DBP_TIMEOUT_VALUE, RCC_FDCANCLKSOURCE_HSE, RCC_FDCANCLKSOURCE_PLL, RCC_FDCANCLKSOURCE_PLL2, RCC_FLAG_LSERDY, RCC_FMCCLKSOURCE_CLKP, RCC_FMCCLKSOURCE_HCLK, RCC_FMCCLKSOURCE_PLL, RCC_FMCCLKSOURCE_PLL2, RCC_I2C123CLKSOURCE_PLL3, RCC_I2C4CLKSOURCE_PLL3, RCC_LPTIM1CLKSOURCE_CLKP, RCC_LPTIM1CLKSOURCE_LSE, RCC_LPTIM1CLKSOURCE_LSI, RCC_LPTIM1CLKSOURCE_PCLK1, RCC_LPTIM1CLKSOURCE_PLL2, RCC_LPTIM1CLKSOURCE_PLL3, RCC_LPTIM2CLKSOURCE_CLKP, RCC_LPTIM2CLKSOURCE_LSE, RCC_LPTIM2CLKSOURCE_LSI, RCC_LPTIM2CLKSOURCE_PCLK4, RCC_LPTIM2CLKSOURCE_PLL2, RCC_LPTIM2CLKSOURCE_PLL3, RCC_LPTIM345CLKSOURCE_CLKP, RCC_LPTIM345CLKSOURCE_LSE, RCC_LPTIM345CLKSOURCE_LSI, RCC_LPTIM345CLKSOURCE_PCLK4, RCC_LPTIM345CLKSOURCE_PLL2, RCC_LPTIM345CLKSOURCE_PLL3, RCC_LPUART1CLKSOURCE_CSI, RCC_LPUART1CLKSOURCE_HSI, RCC_LPUART1CLKSOURCE_LSE, RCC_LPUART1CLKSOURCE_PCLK4, RCC_LPUART1CLKSOURCE_PLL2, RCC_LPUART1CLKSOURCE_PLL3, RCC_LSE_TIMEOUT_VALUE, RCC_OSPICLKSOURCE_CLKP, RCC_OSPICLKSOURCE_HCLK, RCC_OSPICLKSOURCE_PLL, RCC_OSPICLKSOURCE_PLL2, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_CKPER, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_DFSDM2, RCC_PERIPHCLK_DSI, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_FMC, RCC_PERIPHCLK_I2C123, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPTIM345, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LTDC, RCC_PERIPHCLK_OSPI, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2A, RCC_PERIPHCLK_SAI2B, RCC_PERIPHCLK_SDMMC, RCC_PERIPHCLK_SPDIFRX, RCC_PERIPHCLK_SPI123, RCC_PERIPHCLK_SPI45, RCC_PERIPHCLK_SPI6, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_TIM, RCC_PERIPHCLK_USART16, RCC_PERIPHCLK_USART234578, RCC_PERIPHCLK_USB, RCC_PLL1_DIVQ, RCC_RNGCLKSOURCE_HSI48, RCC_RNGCLKSOURCE_LSE, RCC_RNGCLKSOURCE_LSI, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_LSE, RCC_SAI1CLKSOURCE_CLKP, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLL2, RCC_SAI1CLKSOURCE_PLL3, RCC_SAI2ACLKSOURCE_CLKP, RCC_SAI2ACLKSOURCE_PIN, RCC_SAI2ACLKSOURCE_PLL, RCC_SAI2ACLKSOURCE_PLL2, RCC_SAI2ACLKSOURCE_PLL3, RCC_SAI2ACLKSOURCE_SPDIF, RCC_SAI2BCLKSOURCE_CLKP, RCC_SAI2BCLKSOURCE_PIN, RCC_SAI2BCLKSOURCE_PLL, RCC_SAI2BCLKSOURCE_PLL2, RCC_SAI2BCLKSOURCE_PLL3, RCC_SAI2BCLKSOURCE_SPDIF, RCC_SDMMCCLKSOURCE_PLL, RCC_SDMMCCLKSOURCE_PLL2, RCC_SPDIFRXCLKSOURCE_HSI, RCC_SPDIFRXCLKSOURCE_PLL, RCC_SPDIFRXCLKSOURCE_PLL2, RCC_SPDIFRXCLKSOURCE_PLL3, RCC_SPI123CLKSOURCE_CLKP, RCC_SPI123CLKSOURCE_PIN, RCC_SPI123CLKSOURCE_PLL, RCC_SPI123CLKSOURCE_PLL2, RCC_SPI123CLKSOURCE_PLL3, RCC_SPI45CLKSOURCE_CSI, RCC_SPI45CLKSOURCE_HSE, RCC_SPI45CLKSOURCE_HSI, RCC_SPI45CLKSOURCE_PCLK1, RCC_SPI45CLKSOURCE_PLL2, RCC_SPI45CLKSOURCE_PLL3, RCC_SPI6CLKSOURCE_CSI, RCC_SPI6CLKSOURCE_HSE, RCC_SPI6CLKSOURCE_HSI, RCC_SPI6CLKSOURCE_PCLK4, RCC_SPI6CLKSOURCE_PIN, RCC_SPI6CLKSOURCE_PLL2, RCC_SPI6CLKSOURCE_PLL3, RCC_USART16CLKSOURCE_CSI, RCC_USART16CLKSOURCE_HSI, RCC_USART16CLKSOURCE_LSE, RCC_USART16CLKSOURCE_PCLK2, RCC_USART16CLKSOURCE_PLL2, RCC_USART16CLKSOURCE_PLL3, RCC_USART234578CLKSOURCE_CSI, RCC_USART234578CLKSOURCE_HSI, RCC_USART234578CLKSOURCE_LSE, RCC_USART234578CLKSOURCE_PCLK1, RCC_USART234578CLKSOURCE_PLL2, RCC_USART234578CLKSOURCE_PLL3, RCC_USBCLKSOURCE_HSI48, RCC_USBCLKSOURCE_PLL, RCC_USBCLKSOURCE_PLL3, RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2AClockSelection, RCC_PeriphCLKInitTypeDef::Sai2BClockSelection, RCC_PeriphCLKInitTypeDef::SdmmcClockSelection, RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection, RCC_PeriphCLKInitTypeDef::Spi123ClockSelection, RCC_PeriphCLKInitTypeDef::Spi45ClockSelection, RCC_PeriphCLKInitTypeDef::Spi6ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Usart16ClockSelection, RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended System Control functions

Functions
Extended System Control functions
Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.

Detailed Description

Extended Peripheral Control functions.

Function Documentation

void HAL_RCCEx_DisableLSECSS ( void )

Disables the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 2679 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, and RCC_IT_LSECSS.

void HAL_RCCEx_EnableLSECSS ( void )

Enables the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 2669 of file stm32h7xx_hal_rcc_ex.c.

void HAL_RCCEx_KerWakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator Kernel clock source for wakeup from Stop.

Parameters:
WakeUpClk,: Kernel Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
Return values:
None

Definition at line 2711 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_KERWAKEUPCLOCK.

void HAL_RCCEx_WakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator clock source for wakeup from Stop and CSS backup clock.

Parameters:
WakeUpClk,: Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
Note:
This function shall not be called after the Clock Security System on HSE has been enabled.
Return values:
None

Definition at line 2696 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_WAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_WAKEUPCLOCK.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Clock Recovery System Control functions

Functions
Extended Clock Recovery System Control functions
Exported Functions

Extended Clock Recovery System Control functions. More...

Functions

void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended Clock Recovery System Control functions.

 ===============================================================================
                ##### Extended Clock Recovery System Control functions  #####
 ===============================================================================
    [..]
      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:

      (#) In System clock config, HSI48 needs to be enabled

      (#) Enable CRS clock in IP MSP init which will use CRS functions

      (#) Call CRS functions as follows:
          (##) Prepare synchronization configuration necessary for HSI48 calibration
              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
                        and also HSI48 oscillator smooth trimming.
              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
                        directly reload value with target and synchronization frequencies values
          (##) Call function HAL_RCCEx_CRSConfig which
              (+++) Resets CRS registers to their default values.
              (+++) Configures CRS registers with synchronization configuration
              (+++) Enables automatic calibration and frequency error counter feature
           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
           should be used as SYNC signal.

          (##) A polling function is provided to wait for complete synchronization
              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
              (+++) According to CRS status, user can decide to adjust again the calibration or continue
                        application if synchronization is OK

      (#) User can retrieve information related to synchronization in calling function
            HAL_RCCEx_CRSGetSynchronizationInfo()

      (#) Regarding synchronization status and synchronization information, user can try a new calibration
           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
           incremented), while when it is detected during the up-counting phase it means that the actual frequency
           is higher (and that the TRIM value should be decremented).

      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
              (++) Call function HAL_RCCEx_CRSConfig()
              (++) Enable CRS_IRQn (thanks to NVIC functions)
              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
              (++) Implement CRS status management in the following user callbacks called from
                   HAL_RCCEx_CRS_IRQHandler():
                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
                   (+++) HAL_RCCEx_CRS_ErrorCallback()

      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)

Function Documentation

void HAL_RCCEx_CRS_ErrorCallback ( uint32_t Error )

RCCEx Clock Recovery System Error interrupt callback.

Parameters:
Error Combination of Error status. This parameter can be a combination of the following values:
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF
Return values:
none

Definition at line 3125 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_ExpectedSyncCallback ( void )

RCCEx Clock Recovery System Expected SYNC interrupt callback.

Return values:
none

Definition at line 3109 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_IRQHandler ( void )

Handle the Clock Recovery System interrupt request.

Return values:
None

Definition at line 3022 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCCEx_CRS_ErrorCallback(), HAL_RCCEx_CRS_ExpectedSyncCallback(), HAL_RCCEx_CRS_SyncOkCallback(), HAL_RCCEx_CRS_SyncWarnCallback(), RCC_CRS_FLAG_ERR, RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_IT_ERR, RCC_CRS_IT_ESYNC, RCC_CRS_IT_SYNCOK, RCC_CRS_IT_SYNCWARN, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, and RCC_CRS_TRIMOVF.

void HAL_RCCEx_CRS_SyncOkCallback ( void )

RCCEx Clock Recovery System SYNCOK interrupt callback.

Return values:
none

Definition at line 3087 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_SyncWarnCallback ( void )

RCCEx Clock Recovery System SYNCWARN interrupt callback.

Return values:
none

Definition at line 3098 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRSConfig ( RCC_CRSInitTypeDef * pInit )

Start automatic synchronization for polling mode.

Parameters:
pInit Pointer on RCC_CRSInitTypeDef structure
Return values:
None

Definition at line 2846 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_FORCE_RESET, __HAL_RCC_CRS_RELEASE_RESET, assert_param, RCC_CRSInitTypeDef::ErrorLimitValue, HAL_GetREVID(), RCC_CRSInitTypeDef::HSI48CalibrationValue, IS_RCC_CRS_ERRORLIMIT, IS_RCC_CRS_HSI48CALIBRATION, IS_RCC_CRS_RELOADVALUE, IS_RCC_CRS_SYNC_DIV, IS_RCC_CRS_SYNC_POLARITY, IS_RCC_CRS_SYNC_SOURCE, RCC_CRSInitTypeDef::Polarity, RCC_CRSInitTypeDef::Prescaler, RCC_CRS_SYNC_SOURCE_PIN, RCC_CRS_SYNC_SOURCE_USB2, RCC_CRSInitTypeDef::ReloadValue, REV_ID_Y, and RCC_CRSInitTypeDef::Source.

void HAL_RCCEx_CRSGetSynchronizationInfo ( RCC_CRSSynchroInfoTypeDef * pSynchroInfo )

Return synchronization info.

Parameters:
pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
Return values:
None

Definition at line 2906 of file stm32h7xx_hal_rcc_ex.c.

References assert_param, RCC_CRSSynchroInfoTypeDef::FreqErrorCapture, RCC_CRSSynchroInfoTypeDef::FreqErrorDirection, RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue, and RCC_CRSSynchroInfoTypeDef::ReloadValue.

void HAL_RCCEx_CRSSoftwareSynchronizationGenerate ( void )

Generate the software synchronization event.

Return values:
None

Definition at line 2896 of file stm32h7xx_hal_rcc_ex.c.

uint32_t HAL_RCCEx_CRSWaitSynchronization ( uint32_t Timeout )

Wait for CRS Synchronization status.

Parameters:
Timeout Duration of the time-out
Note:
Timeout is based on the maximum time to receive a SYNC event based on synchronization frequency.
If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
Return values:
Combination of Synchronization status This parameter can be a combination of the following values:
  • RCC_CRS_TIMEOUT
  • RCC_CRS_SYNCOK
  • RCC_CRS_SYNCWARN
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF

Definition at line 2939 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_CLEAR_FLAG, __HAL_RCC_CRS_GET_FLAG, HAL_GetTick(), RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, RCC_CRS_SYNCOK, RCC_CRS_SYNCWARN, RCC_CRS_TIMEOUT, and RCC_CRS_TRIMOVF.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Private Functions

Functions
Private Functions
RCCEx

Functions

static HAL_StatusTypeDef | RCCEx_PLL2_Config (RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.
static HAL_StatusTypeDef | RCCEx_PLL3_Config (RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.

Function Documentation

static HAL_StatusTypeDef RCCEx_PLL2_Config | ( | RCC_PLL2InitTypeDef * | pll2,
 |  | uint32_t | Divider
 | ) |  | [static]

Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.

Parameters:
pll2,: Pointer to an RCC_PLL2InitTypeDef structure that contains the configuration parameters as well as VCI, VCO clock ranges.
Divider divider parameter to be updated
Note:
PLL2 is temporary disabled to apply new parameters
Return values:
HAL status

Definition at line 3156 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLL2_CONFIG, __HAL_RCC_PLL2_DISABLE, __HAL_RCC_PLL2_ENABLE, __HAL_RCC_PLL2_VCIRANGE, __HAL_RCC_PLL2_VCORANGE, __HAL_RCC_PLL2CLKOUT_ENABLE, __HAL_RCC_PLL2FRACN_CONFIG, __HAL_RCC_PLL2FRACN_DISABLE, __HAL_RCC_PLL2FRACN_ENABLE, assert_param, DIVIDER_P_UPDATE, DIVIDER_Q_UPDATE, HAL_GetTick(), IS_RCC_PLL2M_VALUE, IS_RCC_PLL2N_VALUE, IS_RCC_PLL2P_VALUE, IS_RCC_PLL2Q_VALUE, IS_RCC_PLL2R_VALUE, IS_RCC_PLL2RGE_VALUE, IS_RCC_PLL2VCO_VALUE, IS_RCC_PLLFRACN_VALUE, PLL2_TIMEOUT_VALUE, RCC_PLL2InitTypeDef::PLL2FRACN, RCC_PLL2InitTypeDef::PLL2M, RCC_PLL2InitTypeDef::PLL2N, RCC_PLL2InitTypeDef::PLL2P, RCC_PLL2InitTypeDef::PLL2Q, RCC_PLL2InitTypeDef::PLL2R, RCC_PLL2InitTypeDef::PLL2RGE, RCC_PLL2InitTypeDef::PLL2VCOSEL, RCC_FLAG_PLL2RDY, RCC_PLL2_DIVP, RCC_PLL2_DIVQ, RCC_PLL2_DIVR, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

static HAL_StatusTypeDef RCCEx_PLL3_Config | ( | RCC_PLL3InitTypeDef * | pll3,
 |  | uint32_t | Divider
 | ) |  | [static]

Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.

Parameters:
pll3,: Pointer to an RCC_PLL3InitTypeDef structure that contains the configuration parameters as well as VCI, VCO clock ranges.
Divider divider parameter to be updated
Note:
PLL3 is temporary disabled to apply new parameters
Return values:
HAL status

Definition at line 3261 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLL3_CONFIG, __HAL_RCC_PLL3_DISABLE, __HAL_RCC_PLL3_ENABLE, __HAL_RCC_PLL3_VCIRANGE, __HAL_RCC_PLL3_VCORANGE, __HAL_RCC_PLL3CLKOUT_ENABLE, __HAL_RCC_PLL3FRACN_CONFIG, __HAL_RCC_PLL3FRACN_DISABLE, __HAL_RCC_PLL3FRACN_ENABLE, assert_param, DIVIDER_P_UPDATE, DIVIDER_Q_UPDATE, HAL_GetTick(), IS_RCC_PLL3M_VALUE, IS_RCC_PLL3N_VALUE, IS_RCC_PLL3P_VALUE, IS_RCC_PLL3Q_VALUE, IS_RCC_PLL3R_VALUE, IS_RCC_PLL3RGE_VALUE, IS_RCC_PLL3VCO_VALUE, IS_RCC_PLLFRACN_VALUE, PLL3_TIMEOUT_VALUE, RCC_PLL3InitTypeDef::PLL3FRACN, RCC_PLL3InitTypeDef::PLL3M, RCC_PLL3InitTypeDef::PLL3N, RCC_PLL3InitTypeDef::PLL3P, RCC_PLL3InitTypeDef::PLL3Q, RCC_PLL3InitTypeDef::PLL3R, RCC_PLL3InitTypeDef::PLL3RGE, RCC_PLL3InitTypeDef::PLL3VCOSEL, RCC_FLAG_PLL3RDY, RCC_PLL3_DIVP, RCC_PLL3_DIVQ, RCC_PLL3_DIVR, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_PLL2InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLL2InitTypeDef Struct Reference
RCCEx Exported Types

PLL2 Clock structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL2M
uint32_t | PLL2N
uint32_t | PLL2P
uint32_t | PLL2Q
uint32_t | PLL2R
uint32_t | PLL2RGE
uint32_t | PLL2VCOSEL
uint32_t | PLL2FRACN

Detailed Description

PLL2 Clock structure definition.

Definition at line 47 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLL2InitTypeDef::PLL2FRACN

PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL2 VCO It should be a value between 0 and 8191

Definition at line 72 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2M

PLL2M: Division factor for PLL2 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 50 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2N

PLL2N: Multiplication factor for PLL2 VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 or between Min_Data = 8 and Max_Data = 420(*) (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 53 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2P

PLL2P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 58 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2Q

PLL2Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 62 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2R

PLL2R: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 65 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2RGE

PLL2RGE: PLL2 clock Input range This parameter must be a value of RCC PLL2 VCI Range

Definition at line 67 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2VCOSEL

PLL2VCOSEL: PLL2 clock Output range This parameter must be a value of RCC PLL2 VCO Range

Definition at line 69 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_PLL3InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLL3InitTypeDef Struct Reference
RCCEx Exported Types

PLL3 Clock structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL3M
uint32_t | PLL3N
uint32_t | PLL3P
uint32_t | PLL3Q
uint32_t | PLL3R
uint32_t | PLL3RGE
uint32_t | PLL3VCOSEL
uint32_t | PLL3FRACN

Detailed Description

PLL3 Clock structure definition.

Definition at line 79 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLL3InitTypeDef::PLL3FRACN

PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191

Definition at line 104 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3M

PLL3M: Division factor for PLL3 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 82 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3N

PLL3N: Multiplication factor for PLL3 VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 or between Min_Data = 8 and Max_Data = 420(*) (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 85 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3P

PLL3P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 90 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3Q

PLL3Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 94 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3R

PLL3R: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 97 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3RGE

PLL3RGE: PLL3 clock Input range This parameter must be a value of RCC PLL3 VCI Range

Definition at line 99 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3VCOSEL

PLL3VCOSEL: PLL3 clock Output range This parameter must be a value of RCC PLL3 VCO Range

Definition at line 101 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PLL1_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL1_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL1 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL1_P_Frequency
uint32_t | PLL1_Q_Frequency
uint32_t | PLL1_R_Frequency

Detailed Description

RCC PLL1 Clocks structure definition.

Definition at line 111 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL1_ClocksTypeDef::PLL1_P_Frequency

Definition at line 113 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL1ClockFreq().

uint32_t PLL1_ClocksTypeDef::PLL1_Q_Frequency

Definition at line 114 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL1ClockFreq().

uint32_t PLL1_ClocksTypeDef::PLL1_R_Frequency

Definition at line 115 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL1ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PLL2_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL2_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL2 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL2_P_Frequency
uint32_t | PLL2_Q_Frequency
uint32_t | PLL2_R_Frequency

Detailed Description

RCC PLL2 Clocks structure definition.

Definition at line 121 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL2_ClocksTypeDef::PLL2_P_Frequency

Definition at line 123 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL2ClockFreq().

uint32_t PLL2_ClocksTypeDef::PLL2_Q_Frequency

Definition at line 124 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL2ClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t PLL2_ClocksTypeDef::PLL2_R_Frequency

Definition at line 125 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL2ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PLL3_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL3_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL3 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL3_P_Frequency
uint32_t | PLL3_Q_Frequency
uint32_t | PLL3_R_Frequency

Detailed Description

RCC PLL3 Clocks structure definition.

Definition at line 131 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL3_ClocksTypeDef::PLL3_P_Frequency

Definition at line 133 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

uint32_t PLL3_ClocksTypeDef::PLL3_Q_Frequency

Definition at line 134 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL3ClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t PLL3_ClocksTypeDef::PLL3_R_Frequency

Definition at line 135 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
RCC_PLL2InitTypeDef PLL2
RCC_PLL3InitTypeDef PLL3
uint32_t | FmcClockSelection
uint32_t | OspiClockSelection
uint32_t | SdmmcClockSelection
uint32_t | CkperClockSelection
uint32_t | Sai1ClockSelection
uint32_t | Sai2AClockSelection
uint32_t | Sai2BClockSelection
uint32_t | Spi123ClockSelection
uint32_t | Spi45ClockSelection
uint32_t | SpdifrxClockSelection
uint32_t | Dfsdm1ClockSelection
uint32_t | Dfsdm2ClockSelection
uint32_t | FdcanClockSelection
uint32_t | Swpmi1ClockSelection
uint32_t | Usart234578ClockSelection
uint32_t | Usart16ClockSelection
uint32_t | RngClockSelection
uint32_t | I2c123ClockSelection
uint32_t | UsbClockSelection
uint32_t | CecClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | I2c4ClockSelection
uint32_t | Lptim2ClockSelection
uint32_t | Lptim345ClockSelection
uint32_t | AdcClockSelection
uint32_t | Spi6ClockSelection
uint32_t | RTCClockSelection
uint32_t | TIMPresSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 142 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

Specifies ADC interface clock source This parameter can be a value of RCCEx ADC Clock Source

Definition at line 254 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CecClockSelection

Specifies CEC clock source This parameter can be a value of RCCEx CEC Clock Source

Definition at line 236 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CkperClockSelection

Specifies CKPER clock source This parameter can be a value of RCCEx CLKP Clock Source

Definition at line 175 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection

Specifies DFSDM1 Clock clock source This parameter can be a value of RCCEx DFSDM1 Clock Source

Definition at line 205 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Dfsdm2ClockSelection

Specifies DFSDM2 Clock clock source This parameter can be a value of RCCEx DFSDM2 Clock Source

Definition at line 209 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FdcanClockSelection

Specifies FDCAN Clock clock source This parameter can be a value of RCCEx FDCAN Clock Source

Definition at line 214 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FmcClockSelection

Specifies FMC clock source This parameter can be a value of RCCEx FMC Clock Source

Definition at line 153 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c123ClockSelection

Specifies I2C1/2/3 clock source This parameter can be a value of RCCEx I2C1/2/3 Clock Source

Definition at line 230 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c4ClockSelection

Specifies I2C4 clock source This parameter can be a value of RCCEx I2C4 Clock Source

Definition at line 245 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source This parameter can be a value of RCCEx LPTIM1 Clock Source

Definition at line 239 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection

Specifies LPTIM2 clock source This parameter can be a value of RCCEx LPTIM2 Clock Source

Definition at line 248 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection

Specifies LPTIM3/4/5 clock source This parameter can be a value of RCCEx LPTIM3/4/5 Clock Source

Definition at line 251 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source This parameter can be a value of RCCEx LPUART1 Clock Source

Definition at line 242 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::OspiClockSelection

Specifies OSPI clock source This parameter can be a value of RCCEx OSPI Clock Source

Definition at line 162 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of RCCEx Periph Clock Selection

Definition at line 144 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLL2InitTypeDef RCC_PeriphCLKInitTypeDef::PLL2

PLL2structure parameters. This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals

Definition at line 147 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLL3InitTypeDef RCC_PeriphCLKInitTypeDef::PLL3

PLL3 structure parameters. This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals

Definition at line 150 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source This parameter can be a value of RCCEx RNG Clock Source

Definition at line 227 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC Clock clock source This parameter can be a value of RCC RTC Clock Source

Definition at line 267 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 clock source This parameter can be a value of SAI1 Clock Source

Definition at line 178 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai2AClockSelection

Specifies SAI2A clock source This parameter can be a value of RCCEx_SAI2A_Clock_Source

Definition at line 187 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai2BClockSelection

Specifies SAI2B clock source This parameter can be a value of RCCEx_SAI2B_Clock_Source

Definition at line 192 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SdmmcClockSelection

Specifies SDMMC clock source This parameter can be a value of RCCEx SDMMC Clock Source

Definition at line 172 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection

Specifies SPDIFRX Clock clock source This parameter can be a value of RCCEx SPDIFRX Clock Source

Definition at line 202 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi123ClockSelection

Specifies SPI1/2/3 clock source This parameter can be a value of SPI1/2/3 Clock Source

Definition at line 196 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi45ClockSelection

Specifies SPI4/5 clock source This parameter can be a value of SPI4/5 Clock Source

Definition at line 199 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi6ClockSelection

Specifies SPI6 clock source This parameter can be a value of SPI6 Clock Source

Definition at line 264 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection

Specifies SWPMI1 Clock clock source This parameter can be a value of RCCEx SWPMI1 Clock Source

Definition at line 218 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::TIMPresSelection

Specifies TIM Clock Prescalers Selection. This parameter can be a value of RCCEx TIM Prescaler Selection

Definition at line 275 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart16ClockSelection

Specifies USART1/6 clock source This parameter can be a value of RCCEx USART1/6 Clock Source

Definition at line 224 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection

Specifies USART2/3/4/5/7/8 clock source This parameter can be a value of RCCEx USART2/3/4/5/7/8 Clock Source

Definition at line 221 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB clock source This parameter can be a value of RCCEx USB Clock Source

Definition at line 233 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_CRSInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSInitTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Init structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | Prescaler
uint32_t | Source
uint32_t | Polarity
uint32_t | ReloadValue
uint32_t | ErrorLimitValue
uint32_t | HSI48CalibrationValue

Detailed Description

RCC_CRS Init structure definition.

Definition at line 283 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSInitTypeDef::ErrorLimitValue

Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of RCCEx CRS ErrorLimitDefault

Definition at line 298 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::HSI48CalibrationValue

Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x3F or a value of RCCEx CRS HSI48CalibrationDefault

Definition at line 301 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Polarity

Specifies the input polarity for the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroPolarity

Definition at line 291 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Prescaler

Specifies the division factor of the SYNC signal. This parameter can be a value of RCCEx CRS SynchroDivider

Definition at line 285 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::ReloadValue

Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of RCCEx CRS ReloadValueDefault .

Definition at line 294 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Source

Specifies the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroSource

Definition at line 288 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC_CRSSynchroInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSSynchroInfoTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Synchronization structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | ReloadValue
uint32_t | HSI48CalibrationValue
uint32_t | FreqErrorCapture
uint32_t | FreqErrorDirection

Detailed Description

RCC_CRS Synchronization structure definition.

Definition at line 309 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorCapture

Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF

Definition at line 317 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorDirection

Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of RCCEx CRS FreqErrorDirection

Definition at line 321 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue

Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F

Definition at line 314 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::ReloadValue

Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF

Definition at line 311 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx Periph Clock Selection

Defines
RCCEx Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART16910 (0x00000001U)
#define | RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART234578 (0x00000002U)
#define | RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_LPUART1 (0x00000004U)
#define | RCC_PERIPHCLK_I2C123 (0x00000008U)
#define | RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C4 (0x00000010U)
#define | RCC_PERIPHCLK_LPTIM1 (0x00000020U)
#define | RCC_PERIPHCLK_LPTIM2 (0x00000040U)
#define | RCC_PERIPHCLK_LPTIM345 (0x00000080U)
#define | RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
#define | RCC_PERIPHCLK_SAI1 (0x00000100U)
#define | RCC_PERIPHCLK_SAI2A (0x00000200U)
#define | RCC_PERIPHCLK_SAI2B (0x00000400U)
#define | RCC_PERIPHCLK_SPI123 (0x00001000U)
#define | RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI45 (0x00002000U)
#define | RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
#define | RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
#define | RCC_PERIPHCLK_SPI6 (0x00004000U)
#define | RCC_PERIPHCLK_FDCAN (0x00008000U)
#define | RCC_PERIPHCLK_SDMMC (0x00010000U)
#define | RCC_PERIPHCLK_RNG (0x00020000U)
#define | RCC_PERIPHCLK_USB (0x00040000U)
#define | RCC_PERIPHCLK_ADC (0x00080000U)
#define | RCC_PERIPHCLK_SWPMI1 (0x00100000U)
#define | RCC_PERIPHCLK_DFSDM1 (0x00200000U)
#define | RCC_PERIPHCLK_DFSDM2 (0x00000800U)
#define | RCC_PERIPHCLK_RTC (0x00400000U)
#define | RCC_PERIPHCLK_CEC (0x00800000U)
#define | RCC_PERIPHCLK_FMC (0x01000000U)
#define | RCC_PERIPHCLK_OSPI (0x02000000U)
#define | RCC_PERIPHCLK_DSI (0x04000000U)
#define | RCC_PERIPHCLK_SPDIFRX (0x08000000U)
#define | RCC_PERIPHCLK_LTDC (0x20000000U)
#define | RCC_PERIPHCLK_TIM (0x40000000U)
#define | RCC_PERIPHCLK_CKPER (0x80000000U)

Define Documentation

#define RCC_PERIPHCLK_ADC (0x00080000U)

Definition at line 408 of file stm32h7xx_hal_rcc_ex.h.

Referenced by ADC_ConfigureBoostMode(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CEC (0x00800000U)

Definition at line 415 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_PERIPHCLK_CKPER (0x80000000U)

Definition at line 432 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_DFSDM1 (0x00200000U)

Definition at line 410 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_DFSDM2 (0x00000800U)

Definition at line 412 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_DSI (0x04000000U)

Definition at line 423 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_FDCAN (0x00008000U)

Definition at line 404 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_FMC (0x01000000U)

Definition at line 416 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123

Definition at line 366 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_I2C123 (0x00000008U)

Definition at line 365 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123

Definition at line 367 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123

Definition at line 368 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_I2C4 (0x00000010U)

Definition at line 369 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)

Definition at line 370 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)

Definition at line 371 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345

Definition at line 373 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)

Definition at line 372 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 (0x00000004U)

Definition at line 364 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LTDC (0x20000000U)

Definition at line 429 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_OSPI (0x02000000U)

Definition at line 421 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG (0x00020000U)

Definition at line 406 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC (0x00400000U)

Definition at line 414 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 (0x00000100U)

Definition at line 380 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI2A (0x00000200U)

Definition at line 387 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI2B (0x00000400U)

Definition at line 390 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SDMMC (0x00010000U)

Definition at line 405 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SD_InitCard().

#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)

Definition at line 424 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123

Definition at line 397 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_SPI123 (0x00001000U)

Definition at line 396 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123

Definition at line 398 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123

Definition at line 399 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45

Definition at line 401 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_SPI45 (0x00002000U)

Definition at line 400 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45

Definition at line 402 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_SPI6 (0x00004000U)

Definition at line 403 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SWPMI1 (0x00100000U)

Definition at line 409 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM (0x40000000U)

Definition at line 431 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578

Definition at line 360 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578

Definition at line 361 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578

Definition at line 362 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578

Definition at line 363 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910

Definition at line 346 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910

Definition at line 344 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910

Definition at line 347 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910

Definition at line 349 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART16910 (0x00000001U)

Definition at line 343 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578

Definition at line 358 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART234578 (0x00000002U)

Definition at line 357 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578

Definition at line 359 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910

Definition at line 345 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_USB (0x00040000U)

Definition at line 407 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL2 Clock Output

Defines
RCC PLL2 Clock Output
RCCEx Exported Constants

Defines

#define | RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
#define | RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
#define | RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN

Define Documentation

#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN

Definition at line 442 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN

Definition at line 443 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN

Definition at line 444 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL3 Clock Output

Defines
RCC PLL3 Clock Output
RCCEx Exported Constants

Defines

#define | RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
#define | RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
#define | RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN

Define Documentation

#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN

Definition at line 453 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN

Definition at line 454 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN

Definition at line 455 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL2 VCI Range

Defines
RCC PLL2 VCI Range
RCCEx Exported Constants

Defines

#define | RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
#define | RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
#define | RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
#define | RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3

Define Documentation

#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0

Definition at line 464 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1

Definition at line 465 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2

Definition at line 466 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3

Definition at line 467 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL2 VCO Range

Defines
RCC PLL2 VCO Range
RCCEx Exported Constants

Defines

#define | RCC_PLL2VCOWIDE (0x00000000U)
#define | RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL

Define Documentation

#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL

Definition at line 478 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCOWIDE (0x00000000U)

Definition at line 477 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL3 VCI Range

Defines
RCC PLL3 VCI Range
RCCEx Exported Constants

Defines

#define | RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
#define | RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
#define | RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
#define | RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3

Define Documentation

#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0

Definition at line 487 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1

Definition at line 488 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2

Definition at line 489 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3

Definition at line 490 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC PLL3 VCO Range

Defines
RCC PLL3 VCO Range
RCCEx Exported Constants

Defines

#define | RCC_PLL3VCOWIDE (0x00000000U)
#define | RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL

Define Documentation

#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL

Definition at line 501 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCOWIDE (0x00000000U)

Definition at line 500 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART1/6 Clock Source

Defines
RCCEx USART1/6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
#define | RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
#define | RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0
#define | RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1
#define | RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
#define | RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2
#define | RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
#define | RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
#define | RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
#define | RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
#define | RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
#define | RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE

Define Documentation

#define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)

Definition at line 521 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2

Definition at line 527 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2

Definition at line 523 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

Definition at line 526 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

Definition at line 528 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0

Definition at line 524 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1

Definition at line 525 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2

Definition at line 531 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI

Definition at line 537 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2

Definition at line 533 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI

Definition at line 536 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE

Definition at line 538 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2

Definition at line 532 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2

Definition at line 534 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3

Definition at line 535 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART1 Clock Source

Defines
RCCEx USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Define Documentation

#define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI

Definition at line 551 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2

Definition at line 547 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI

Definition at line 550 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Definition at line 552 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2

Definition at line 548 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3

Definition at line 549 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART6 Clock Source

Defines
RCCEx USART6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Define Documentation

#define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI

Definition at line 564 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2

Definition at line 560 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI

Definition at line 563 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Definition at line 565 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2

Definition at line 561 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3

Definition at line 562 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx UART9 Clock Source

Defines
RCCEx UART9 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Define Documentation

#define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI

Definition at line 579 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2

Definition at line 575 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI

Definition at line 578 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Definition at line 580 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2

Definition at line 576 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3

Definition at line 577 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART10 Clock Source

Defines
RCCEx USART10 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Define Documentation

#define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI

Definition at line 594 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2

Definition at line 590 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI

Definition at line 593 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE

Definition at line 595 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2

Definition at line 591 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3

Definition at line 592 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART2/3/4/5/7/8 Clock Source

Defines
RCCEx USART2/3/4/5/7/8 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
#define | RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
#define | RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0
#define | RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1
#define | RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
#define | RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2
#define | RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

Define Documentation

#define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 614 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2

Definition at line 621 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1

Definition at line 617 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

Definition at line 620 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

Definition at line 622 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1

Definition at line 616 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0

Definition at line 618 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1

Definition at line 619 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART2 Clock Source

Defines
RCCEx USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 635 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 631 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 634 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 636 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 632 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 633 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx USART3 Clock Source

Defines
RCCEx USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 649 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 645 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 648 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 650 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 646 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 647 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx UART4 Clock Source

Defines
RCCEx UART4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 663 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 659 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 662 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 664 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 660 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 661 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx UART5 Clock Source

Defines
RCCEx UART5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 677 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 673 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 676 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 678 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 674 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 675 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx UART7 Clock Source

Defines
RCCEx UART7 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 691 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 687 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 690 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 692 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 688 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 689 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx UART8 Clock Source

Defines
RCCEx UART8 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Define Documentation

#define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI

Definition at line 705 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1

Definition at line 701 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI

Definition at line 704 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE

Definition at line 706 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2

Definition at line 702 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3

Definition at line 703 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx LPUART1 Clock Source

Defines
RCCEx LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4
#define | RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4
#define | RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
#define | RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)

Define Documentation

#define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2

Definition at line 732 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4

Definition at line 728 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

Definition at line 731 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)

Definition at line 733 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4

Definition at line 727 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0

Definition at line 729 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1

Definition at line 730 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 725 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx I2C1/2/3 Clock Source

Defines
RCCEx I2C1/2/3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
#define | RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
#define | RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
#define | RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

Define Documentation

#define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 748 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

Definition at line 753 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1

Definition at line 750 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1

Definition at line 752 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0

Definition at line 751 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx I2C1 Clock Source

Defines
RCCEx I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Define Documentation

#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Definition at line 765 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1

Definition at line 762 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI

Definition at line 764 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3

Definition at line 763 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx I2C2 Clock Source

Defines
RCCEx I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Define Documentation

#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Definition at line 777 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1

Definition at line 774 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI

Definition at line 776 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3

Definition at line 775 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx I2C3 Clock Source

Defines
RCCEx I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Define Documentation

#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI

Definition at line 789 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1

Definition at line 786 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI

Definition at line 788 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3

Definition at line 787 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx I2C4 Clock Source

Defines
RCCEx I2C4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4
#define | RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1
#define | RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

Define Documentation

#define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

Definition at line 809 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4

Definition at line 806 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1

Definition at line 808 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0

Definition at line 807 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 804 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx RNG Clock Source

Defines
RCCEx RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
#define | RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0
#define | RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1
#define | RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL

Define Documentation

#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)

Definition at line 825 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1

Definition at line 827 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL

Definition at line 828 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0

Definition at line 826 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H7B3xQ HAL User Manual: RCCEx USB Clock Source

Defines
RCCEx USB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL

Define Documentation

#define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL

Definition at line 857 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0

Definition at line 855 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1

Definition at line 856 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H7B3xQ HAL User Manual: SAI1 Clock Source

Defines
SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
#define | RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2

Define Documentation

#define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2

Definition at line 878 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

Definition at line 877 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)

Definition at line 874 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0

Definition at line 875 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1

Definition at line 876 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Source SAI2A Clock Source

Defines
Source SAI2A Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0
#define | RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1
#define | RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
#define | RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
#define | RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

Define Documentation

#define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2

Definition at line 931 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

Definition at line 930 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2ACLKSOURCE_PLL (0x00000000U)

Definition at line 927 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0

Definition at line 928 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1

Definition at line 929 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

Definition at line 932 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H7B3xQ HAL User Manual: Clock_Source SAI2B Clock Source

Defines
Clock_Source SAI2B Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0
#define | RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1
#define | RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
#define | RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2
#define | RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

Define Documentation

#define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2

Definition at line 946 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

Definition at line 945 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2BCLKSOURCE_PLL (0x00000000U)

Definition at line 942 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0

Definition at line 943 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1

Definition at line 944 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

Definition at line 947 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI1/2/3 Clock Source

Defines
SPI1/2/3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI123CLKSOURCE_PLL (0x00000000U)
#define | RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0
#define | RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1
#define | RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
#define | RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2

Define Documentation

#define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2

Definition at line 968 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

Definition at line 967 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)

Definition at line 964 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0

Definition at line 965 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1

Definition at line 966 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI1 Clock Source

Defines
SPI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Define Documentation

#define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Definition at line 981 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN

Definition at line 980 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL

Definition at line 977 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2

Definition at line 978 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3

Definition at line 979 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: SPI2 Clock Source

Defines
SPI2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Define Documentation

#define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Definition at line 994 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN

Definition at line 993 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL

Definition at line 990 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2

Definition at line 991 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3

Definition at line 992 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: SPI3 Clock Source

Defines
SPI3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Define Documentation

#define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP

Definition at line 1007 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN

Definition at line 1006 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL

Definition at line 1003 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2

Definition at line 1004 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3

Definition at line 1005 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: SPI4/5 Clock Source

Defines
SPI4/5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
#define | RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
#define | RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
#define | RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
#define | RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
#define | RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2
#define | RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

Define Documentation

#define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 1025 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2

Definition at line 1032 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

Definition at line 1027 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

Definition at line 1033 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

Definition at line 1031 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1

Definition at line 1028 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0

Definition at line 1029 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1

Definition at line 1030 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI4 Clock Source

Defines
SPI4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
#define | RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
#define | RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
#define | RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
#define | RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
#define | RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE

Define Documentation

#define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI

Definition at line 1046 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1

Definition at line 1042 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE

Definition at line 1047 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI

Definition at line 1045 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2

Definition at line 1043 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3

Definition at line 1044 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI5 Clock Source

Defines
SPI5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
#define | RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
#define | RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
#define | RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
#define | RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
#define | RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE

Define Documentation

#define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI

Definition at line 1060 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1

Definition at line 1056 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE

Definition at line 1061 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI

Definition at line 1059 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2

Definition at line 1057 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3

Definition at line 1058 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI6 Clock Source

Defines
SPI6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
#define | RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4
#define | RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0
#define | RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1
#define | RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
#define | RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2
#define | RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
#define | RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

Define Documentation

#define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2

Definition at line 1086 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

Definition at line 1081 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

Definition at line 1087 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

Definition at line 1085 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4

Definition at line 1082 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

Definition at line 1088 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0

Definition at line 1083 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1

Definition at line 1084 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 1079 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx LPTIM1 Clock Source

Defines
RCCEx LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
#define | RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
#define | RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2
#define | RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

Define Documentation

#define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 1142 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

Definition at line 1150 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1

Definition at line 1145 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

Definition at line 1148 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2

Definition at line 1149 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1

Definition at line 1144 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0

Definition at line 1146 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1

Definition at line 1147 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx LPTIM2 Clock Source

Defines
RCCEx LPTIM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2
#define | RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

Define Documentation

#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

Definition at line 1178 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4

Definition at line 1173 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

Definition at line 1176 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2

Definition at line 1177 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4

Definition at line 1172 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0

Definition at line 1174 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1

Definition at line 1175 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 1170 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx LPTIM3/4/5 Clock Source

Defines
RCCEx LPTIM3/4/5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0
#define | RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1
#define | RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
#define | RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2
#define | RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

Define Documentation

#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

Definition at line 1205 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4

Definition at line 1200 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

Definition at line 1203 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2

Definition at line 1204 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4

Definition at line 1199 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0

Definition at line 1201 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1

Definition at line 1202 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 1197 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx LPTIM3 Clock Source

Defines
RCCEx LPTIM3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
#define | RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
#define | RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
#define | RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
#define | RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
#define | RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP

Define Documentation

#define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP

Definition at line 1219 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1

Definition at line 1214 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE

Definition at line 1217 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI

Definition at line 1218 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2

Definition at line 1215 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3

Definition at line 1216 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx OSPI Clock Source

Defines
RCCEx OSPI Clock Source
RCCEx Exported Constants

Defines

#define | RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
#define | RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
#define | RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK
#define | RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
#define | RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
#define | RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL

Define Documentation

#define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)

Definition at line 1274 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL

Definition at line 1280 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK

Definition at line 1276 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK

Definition at line 1277 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0

Definition at line 1278 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1

Definition at line 1279 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx FMC Clock Source

Defines
RCCEx FMC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)
#define | RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK
#define | RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK
#define | RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0
#define | RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1
#define | RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL

Define Documentation

#define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)

Definition at line 1309 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL

Definition at line 1315 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK

Definition at line 1312 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK

Definition at line 1310 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0

Definition at line 1313 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1

Definition at line 1314 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx FDCAN Clock Source

Defines
RCCEx FDCAN Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FDCANCLKSOURCE_HSE (0x00000000U)
#define | RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1

Define Documentation

#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)

Definition at line 1331 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0

Definition at line 1332 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1

Definition at line 1333 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx SDMMC Clock Source

Defines
RCCEx SDMMC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
#define | RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL

Define Documentation

#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)

Definition at line 1348 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL

Definition at line 1349 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx ADC Clock Source

Defines
RCCEx ADC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
#define | RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1

Define Documentation

#define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1

Definition at line 1366 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)

Definition at line 1364 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0

Definition at line 1365 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx SWPMI1 Clock Source

Defines
RCCEx SWPMI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL

Define Documentation

#define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 1379 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1

Definition at line 1381 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL

Definition at line 1382 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx DFSDM1 Clock Source

Defines
RCCEx DFSDM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1
#define | RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL

Define Documentation

#define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)

Definition at line 1395 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1

Definition at line 1397 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL

Definition at line 1398 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx DFSDM2 Clock Source

Defines
RCCEx DFSDM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4
#define | RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL

Define Documentation

#define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4

Definition at line 1410 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)

Definition at line 1408 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL

Definition at line 1411 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx SPDIFRX Clock Source

Defines
RCCEx SPDIFRX Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
#define | RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0
#define | RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1
#define | RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL

Define Documentation

#define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL

Definition at line 1429 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)

Definition at line 1426 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0

Definition at line 1427 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1

Definition at line 1428 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx CEC Clock Source

Defines
RCCEx CEC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CECCLKSOURCE_LSE (0x00000000U)
#define | RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0
#define | RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1

Define Documentation

#define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1

Definition at line 1445 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CECCLKSOURCE_LSE (0x00000000U)

Definition at line 1443 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0

Definition at line 1444 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CLKP Clock Source

Defines
RCCEx CLKP Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CLKPSOURCE_HSI (0x00000000U)
#define | RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0
#define | RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1

Define Documentation

#define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0

Definition at line 1461 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1

Definition at line 1462 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CLKPSOURCE_HSI (0x00000000U)

Definition at line 1460 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32H7B3xQ HAL User Manual: RCCEx TIM Prescaler Selection

Defines
RCCEx TIM Prescaler Selection
RCCEx Exported Constants

Defines

#define | RCC_TIMPRES_DESACTIVATED (0x00000000U)
#define | RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE

Define Documentation

#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE

Definition at line 1472 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_TIMPRES_DESACTIVATED (0x00000000U)

Definition at line 1471 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

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STM32H7B3xQ HAL User Manual: RCCEx RCC WWDGx

Defines
RCCEx RCC WWDGx
RCCEx Exported Constants

Defines

#define RCC_WWDG1 RCC_GCR_WW1RSC

Define Documentation

#define RCC_WWDG1 RCC_GCR_WW1RSC

Definition at line 1507 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CRS Status

Defines
RCCEx CRS Status
RCCEx Exported Constants

Defines

#define | RCC_CRS_NONE (0x00000000U)
#define | RCC_CRS_TIMEOUT (0x00000001U)
#define | RCC_CRS_SYNCOK (0x00000002U)
#define | RCC_CRS_SYNCWARN (0x00000004U)
#define | RCC_CRS_SYNCERR (0x00000008U)
#define | RCC_CRS_SYNCMISS (0x00000010U)
#define | RCC_CRS_TRIMOVF (0x00000020U)

Define Documentation

#define RCC_CRS_NONE (0x00000000U)

Definition at line 1518 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCERR (0x00000008U)

Definition at line 1522 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCMISS (0x00000010U)

Definition at line 1523 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCOK (0x00000002U)

Definition at line 1520 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCWARN (0x00000004U)

Definition at line 1521 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TIMEOUT (0x00000001U)

Definition at line 1519 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TRIMOVF (0x00000020U)

Definition at line 1524 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

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STM32H7B3xQ HAL User Manual: RCCEx CRS SynchroSource

Defines
RCCEx CRS SynchroSource
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
#define | RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)

Define Documentation

#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 1533 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)

Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only

Definition at line 1532 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1

Synchro Signal source USB1 SOF (default)

Definition at line 1534 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)

Synchro Signal source USB2 SOF

Definition at line 1535 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

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STM32H7B3xQ HAL User Manual: RCCEx CRS SynchroDivider

Defines
RCCEx CRS SynchroDivider
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_DIV1 (0x00000000U)
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Define Documentation

#define RCC_CRS_SYNC_DIV1 (0x00000000U)

Synchro Signal not divided (default)

Definition at line 1543 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 1550 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 1547 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 1544 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 1548 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 1545 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 1549 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 1546 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx CRS SynchroPolarity

Defines
RCCEx CRS SynchroPolarity
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 1559 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)

Synchro Active on rising edge (default)

Definition at line 1558 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx CRS ReloadValueDefault

Defines
RCCEx CRS ReloadValueDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)

Define Documentation

#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)

The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB).

Definition at line 1567 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CRS ErrorLimitDefault

Defines
RCCEx CRS ErrorLimitDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)

Define Documentation

#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)

Default Frequency error limit

Definition at line 1576 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CRS HSI48CalibrationDefault

Defines
RCCEx CRS HSI48CalibrationDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)

Define Documentation

#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)

The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency

Definition at line 1584 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CRS FreqErrorDirection

Defines
RCCEx CRS FreqErrorDirection
RCCEx Exported Constants

Defines

#define | RCC_CRS_FREQERRORDIR_UP (0x00000000U)
#define | RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)

Define Documentation

#define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)

Downcounting direction, the actual frequency is below the target

Definition at line 1595 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_FREQERRORDIR_UP (0x00000000U)

Upcounting direction, the actual frequency is above the target

Definition at line 1594 of file stm32h7xx_hal_rcc_ex.h.

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STM32H7B3xQ HAL User Manual: RCCEx CRS Interrupt Sources

Defines
RCCEx CRS Interrupt Sources
RCCEx Exported Constants

Defines

#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Define Documentation

#define RCC_CRS_IT_ERR CRS_CR_ERRIE

Error

Definition at line 1605 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE

Expected SYNC

Definition at line 1606 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE

SYNC error

Definition at line 1607 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE

SYNC missed

Definition at line 1608 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE

SYNC event OK

Definition at line 1603 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE

SYNC warning

Definition at line 1604 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Trimming overflow or underflow

Definition at line 1609 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx CRS Flags

Defines
RCCEx CRS Flags
RCCEx Exported Constants

Defines

#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Define Documentation

#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF

Error flag

Definition at line 1620 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF

Expected SYNC flag

Definition at line 1621 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR

SYNC error

Definition at line 1622 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS

SYNC missed

Definition at line 1623 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF

SYNC event OK flag

Definition at line 1618 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF

SYNC warning flag

Definition at line 1619 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Trimming overflow or underflow

Definition at line 1624 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCCEx Private Macros

Defines

#define | IS_RCC_PLL2CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_PLL3CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_USART16CLKSOURCE(SOURCE)
#define | IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE
#define | IS_RCC_USART234578CLKSOURCE(SOURCE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_UART9CLKSOURCE(SOURCE)
#define | IS_RCC_USART10CLKSOURCE(SOURCE)
#define | IS_RCC_LPUART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C123CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_RNGCLKSOURCE(SOURCE)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2ACLK(__SOURCE__)
#define | IS_RCC_SAI2BCLK(__SOURCE__)
#define | IS_RCC_SPI123CLK(__SOURCE__)
#define | IS_RCC_SPI1CLK(__SOURCE__)
#define | IS_RCC_SPI2CLK(__SOURCE__)
#define | IS_RCC_SPI3CLK(__SOURCE__)
#define | IS_RCC_SPI45CLK(__SOURCE__)
#define | IS_RCC_SPI4CLK(__SOURCE__)
#define | IS_RCC_SPI5CLK(__SOURCE__)
#define | IS_RCC_SPI6CLK(__SOURCE__)
#define | IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
#define | IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
#define | IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2RGE_VALUE(VALUE)
#define | IS_RCC_PLL3RGE_VALUE(VALUE)
#define | IS_RCC_PLL2VCO_VALUE(VALUE)
#define | IS_RCC_PLL3VCO_VALUE(VALUE)
#define | IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_LPTIM2CLK(SOURCE)
#define | IS_RCC_LPTIM345CLK(SOURCE)
#define | IS_RCC_LPTIM3CLK(SOURCE)
#define | IS_RCC_OSPICLK(__SOURCE__)
#define | IS_RCC_FMCCLK(__SOURCE__)
#define | IS_RCC_FDCANCLK(__SOURCE__)
#define | IS_RCC_SDMMC(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(SOURCE)
#define | IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM2CLKSOURCE(SOURCE)
#define | IS_RCC_SPDIFRXCLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_CLKPSOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Define Documentation

#define IS_RCC_ADCCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))

Definition at line 2117 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CECCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))

Definition at line 2137 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CLKPSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))

Definition at line 2141 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__ ) (((__VALUE__) <= 0xFFU))

Definition at line 2176 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__ )
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

Definition at line 2180 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__ ) (((__VALUE__) <= 0x3FU))

Definition at line 2178 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__ ) (((__VALUE__) <= 0xFFFFU))

Definition at line 2174 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

Definition at line 2166 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

Definition at line 2171 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))

Definition at line 2161 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_DFSDM1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))

Definition at line 2124 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_DFSDM2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))

Definition at line 2128 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_FDCANCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))

Definition at line 2107 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_FMCCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))

Definition at line 2100 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_I2C123CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))

Definition at line 1825 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))

Definition at line 1830 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_I2C2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))

Definition at line 1835 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_I2C3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

Definition at line 1840 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_I2C4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

Definition at line 1845 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))

Definition at line 2032 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM2CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))

Definition at line 2039 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM345CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))

Definition at line 2046 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM3CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))

Definition at line 2053 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPUART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 1818 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_OSPICLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))

Definition at line 2087 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PLL2CLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL2_DIVP) || \
                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
                                         ((VALUE) == RCC_PLL2_DIVR))

Definition at line 1700 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PLL2M_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 63U))

Definition at line 2008 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2N_VALUE ( VALUE ) ((4U <= (VALUE)) && ((VALUE) <= 512U))

Definition at line 2009 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2P_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2010 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2Q_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2011 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2R_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2012 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2RGE_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL2VCIRANGE_0)  || \
                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
                                    ((VALUE) == RCC_PLL2VCIRANGE_3))

Definition at line 2014 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2VCO_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL2VCOWIDE)  || \
                                    ((VALUE) == RCC_PLL2VCOMEDIUM))

Definition at line 2024 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL3CLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL3_DIVP) || \
                                          ((VALUE) == RCC_PLL3_DIVQ) || \
                                          ((VALUE) == RCC_PLL3_DIVR))

Definition at line 1704 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PLL3M_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 63U))

Definition at line 2002 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3N_VALUE ( VALUE ) ((4U <= (VALUE)) && ((VALUE) <= 512U))

Definition at line 2003 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3P_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2004 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3Q_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2005 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3R_VALUE ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 128U))

Definition at line 2006 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3RGE_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL3VCIRANGE_0)  || \
                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
                                    ((VALUE) == RCC_PLL3VCIRANGE_3))

Definition at line 2019 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3VCO_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL3VCOWIDE)  || \
                                    ((VALUE) == RCC_PLL3VCOMEDIUM))

Definition at line 2027 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLLFRACN_VALUE ( VALUE ) ((VALUE) <=8191U)

Definition at line 2030 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig(), RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

#define IS_RCC_RNGCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))

Definition at line 1850 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

Definition at line 1864 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI2ACLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))

Definition at line 1896 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI2BCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))

Definition at line 1906 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SCOPE_WWDG ( WWDG ) ((WWDG) == RCC_WWDG1)

Definition at line 2157 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SDMMC ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))

Definition at line 2113 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SPDIFRXCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))

Definition at line 2132 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI123CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))

Definition at line 1915 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))

Definition at line 1922 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))

Definition at line 1929 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI3CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))

Definition at line 1936 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI45CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))

Definition at line 1943 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI4CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))

Definition at line 1951 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI5CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))

Definition at line 1959 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI6CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))

Definition at line 1976 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SWPMI1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))

Definition at line 2121 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_TIMPRES ( VALUE )
Value:
(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
                ((VALUE) == RCC_TIMPRES_ACTIVATED))

Definition at line 2144 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))

Definition at line 1765 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART5CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))

Definition at line 1772 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART7CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))

Definition at line 1786 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART8CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))

Definition at line 1793 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART9CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))

Definition at line 1801 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART10CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))

Definition at line 1810 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE

Definition at line 1724 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART16CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

Definition at line 1716 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

Definition at line 1744 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART234578CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

Definition at line 1735 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))

Definition at line 1751 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))

Definition at line 1758 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART6CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))

Definition at line 1779 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USBCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))

Definition at line 1860 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx Exported Macros

Defines
RCCEx Exported Macros
RCCEx

Defines

#define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
Macros to enable or disable PLL2.
#define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
#define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
#define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
#define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
#define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
Macros to enable or disable the main PLL3.
#define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
#define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
#define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
#define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
#define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
Macro to Configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
Macro to Configure the SPDIFRX clock source.
#define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
Macro to get the SPDIFRX clock source.
#define | __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
Macro to Configure the SAI2A clock source.
#define | __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
Macro to get the SAI2A clock source.
#define | __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
Macro to Configure the SAI2B clock source.
#define | __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
Macro to get the SAI2B clock source.
#define | __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
macro to configure the I2C1/2/3 clock (I2C123CLK).
#define | __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
macro to get the I2C1/2/3 clock source.
#define | __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
macro to configure the USART1/6/9* /10* clock (USART16CLK).
#define | __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
#define | __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
macro to get the USART1/6/9* /10* clock source.
#define | __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
#define | __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
macro to configure the USART234578 clock (USART234578CLK).
#define | __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
macro to get the USART2/3/4/5/7/8 clock source.
#define | __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART5 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART8 clock source.
#define | __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the UART9 clock (UART9CLK).
#define | __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the UART9 clock source.
#define | __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART10 clock (USART10CLK).
#define | __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART10 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
macro to configure the LPTIM1 clock source.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
macro to configure the LPTIM2 clock source.
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
macro to configure the LPTIM3/4/5 clock source.
#define | __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
macro to get the LPTIM3/4/5 clock source.
#define | __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
macro to configure the LPTIM3 clock source.
#define | __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
macro to configure the OSPI clock source.
#define | __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
macro to get the OSPI clock source.
#define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
macro to configure the FMC clock source.
#define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
macro to get the FMC clock source.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
Macro to configure the ADC clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.
#define | __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
Macro to configure the DFSDM2 clock.
#define | __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
Macro to get the DFSDM2 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
Macro to configure the CLKP : Oscillator clock for peripheral.
#define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
Macro to get the Oscillator clock for peripheral source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
Macro to configure the FDCAN clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
Macro to get the FDCAN clock.
#define | __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
Macro to Configure the SPI1/2/3 clock source.
#define | __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
Macro to get the SPI1/2/3 clock source.
#define | __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI1 clock source.
#define | __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI1 clock source.
#define | __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI2 clock source.
#define | __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI2 clock source.
#define | __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI3 clock source.
#define | __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI3 clock source.
#define | __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
Macro to Configure the SPI4/5 clock source.
#define | __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
Macro to get the SPI4/5 clock source.
#define | __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
Macro to Configure the SPI4 clock source.
#define | __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
Macro to get the SPI4 clock source.
#define | __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
Macro to Configure the SPI5 clock source.
#define | __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
Macro to get the SPI5 clock source.
#define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
Macro to Configure the SPI6 clock source.
#define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
Macro to get the SPI6 clock source.
#define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
Macro to configure the SDMMC clock.
#define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
Macro to get the SDMMC clock.
#define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
macro to configure the RNG clock (RNGCLK).
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
macro to get the RNG clock source.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADCCLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

Macro to configure the ADC clock.

Parameters:
__ADCCLKSource__ specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 3464 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CEC_CONFIG ( __CECCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

macro to configure the CEC clock (CECCLK).

Parameters:
__CECCLKSource__ specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 3560 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CLKP_CONFIG ( __CLKPSource__ ) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

Macro to configure the CLKP : Oscillator clock for peripheral.

Parameters:
__CLKPSource__ specifies Oscillator clock for peripheral This parameter can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 3587 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_DFSDM1_CONFIG ( __DFSDM1CLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

Macro to configure the DFSDM1 clock.

Parameters:
__DFSDM1CLKSource__ specifies the DFSDM1 clock source. This parameter can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 3515 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_DFSDM2_CONFIG ( __DFSDM2CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))

Macro to configure the DFSDM2 clock.

Parameters:
__DFSDM2CLKSource__ specifies the DFSDM2 clock source. This parameter can be one of the following values:
  • RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock
  • RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock

Definition at line 3537 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FDCAN_CONFIG ( __FDCANCLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

Macro to configure the FDCAN clock.

Parameters:
__FDCANCLKSource__ specifies clock source for FDCAN This parameter can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 3615 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FMC_CONFIG ( __FMCCLKSource__ ) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

macro to configure the FMC clock source.

Parameters:
__FMCCLKSource__ specifies the FMC clock source.
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 3409 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 3477 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))

macro to get the CEC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 3573 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_CLKP_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))

Macro to get the Oscillator clock for peripheral source.

Return values:
The clock source can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 3600 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_DFSDM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))

Macro to get the DFSDM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 3527 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_DFSDM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))

Macro to get the DFSDM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
  • RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock

Definition at line 3545 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_FDCAN_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))

Macro to get the FDCAN clock.

Return values:
The clock source can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 3628 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_FMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))

macro to get the FMC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 3423 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C123_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))

macro to get the I2C1/2/3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

Definition at line 2712 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 2733 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 2753 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 2773 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

macro to get the I2C4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 2799 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 3186 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))

macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 3220 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM345_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))

macro to get the LPTIM3/4/5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

Definition at line 3253 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE

macro to get the LPTIM3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 3277 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))

macro to get the LPUART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 3152 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_OSPI_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))

macro to get the OSPI clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock

Definition at line 3374 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_RNG_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))

macro to get the RNG clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 3918 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
  • RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
  • RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

Definition at line 2465 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI2A_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))

Macro to get the SAI2A clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
  • RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
  • RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
  • RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP
  • RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
  • RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock

Definition at line 2598 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI2B_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))

Macro to get the SAI2B clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
  • RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
  • RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
  • RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP
  • RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
  • RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock

Definition at line 2627 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDMMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))

Macro to get the SDMMC clock.

Definition at line 3888 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SPDIFRX_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))

Macro to get the SPDIFRX clock source.

Return values:
None

Definition at line 2494 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI123_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))

Macro to get the SPI1/2/3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
  • RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
  • RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
  • RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
  • RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

Definition at line 3664 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
  • RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

Definition at line 3689 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
  • RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

Definition at line 3713 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
  • RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

Definition at line 3737 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI45_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))

Macro to get the SPI4/5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
  • RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
  • RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
  • RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
  • RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
  • RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE

Definition at line 3772 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE

Definition at line 3799 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE

Definition at line 3825 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI6_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))

Macro to get the SPI6 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
  • RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN

Definition at line 3866 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SWPMI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))

Macro to get the SWPMI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 3502 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2971 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2995 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART7 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 3043 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART8 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 3067 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the UART9 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
  • RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
  • RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
  • RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
  • RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
  • RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

Definition at line 3092 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART10 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
  • RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

Definition at line 3118 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART16910_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))

macro to get the USART1/6/9* /10* clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
(*) : Available on some STM32H7 lines only.

Definition at line 2838 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE

Definition at line 2840 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2899 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART234578_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))

macro to get the USART2/3/4/5/7/8 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

Definition at line 2874 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2923 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2947 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART6 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 3019 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

Definition at line 3450 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C123_CONFIG ( __I2C123CLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))

macro to configure the I2C1/2/3 clock (I2C123CLK).

Parameters:
__I2C123CLKSource__ specifies the I2C1/2/3 clock source. This parameter can be one of the following values:
  • RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
  • RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

Definition at line 2698 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG

macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1CLKSource__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 2724 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG

macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2CLKSource__ specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 2744 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG

macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3CLKSource__ specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 2764 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CONFIG ( __I2C4CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

macro to configure the I2C4 clock (I2C4CLK).

Parameters:
__I2C4CLKSource__ specifies the I2C4 clock source. This parameter can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 2788 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1CLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

macro to configure the LPTIM1 clock source.

Parameters:
__LPTIM1CLKSource__ specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 3170 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

macro to configure the LPTIM2 clock source.

Parameters:
__LPTIM2CLKSource__ specifies the LPTIM2 clock source. This parameter can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 3204 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM345_CONFIG ( __LPTIM3CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))

macro to configure the LPTIM3/4/5 clock source.

Parameters:
__LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
  • RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

Definition at line 3237 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG

macro to configure the LPTIM3 clock source.

Parameters:
__LPTIM3CLKSource__ specifies the LPTIM3 clock source.
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 3266 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:
__LPUART1CLKSource__ specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 3136 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_OSPI_CONFIG ( __OSPICLKSource__ ) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

macro to configure the OSPI clock source.

Parameters:
__OSPICLKSource__ specifies the OSPI clock source.
  • RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
  • RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock

Definition at line 3363 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLL2_CONFIG | ( | __PLL2M__,
 |  | __PLL2N__,
 |  | __PLL2P__,
 |  | __PLL2Q__,
 |  | __PLL2R__
 | ) |
Value:
do{ \
                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
                    } while(0)

Macro to configures the PLL2 multiplication and division factors.

Note:
This function must be used only when PLL2 is disabled.
Parameters:
__PLL2M__ specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLL2N__ specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).
Note:
You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
Parameters:
__PLL2P__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2Q__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2R__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
Note:
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
Return values:
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 2263 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)

Definition at line 2202 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL2ON)

Macros to enable or disable PLL2.

Note:
After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.
PLL2 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 2201 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCIRANGE ( __RCC_PLL2VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

Macro to select the PLL2 reference frequency range.

Parameters:
__RCC_PLL2VCIRange__ specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 2298 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCORANGE ( __RCC_PLL2VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

Macro to select the PLL2 reference frequency range.

Parameters:
__RCC_PLL2VCORange__ Specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
  • RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 2312 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2CLKOUT_DISABLE ( __RCC_PLL2ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Definition at line 2220 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL2CLKOUT_ENABLE ( __RCC_PLL2ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

Note:
Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power.
Parameters:
__RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 2218 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_CONFIG ( __RCC_PLL2FRACN__ ) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))

Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
Parameters:
__RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191
Note:
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:
None

Definition at line 2286 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Definition at line 2229 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
Return values:
None

Definition at line 2227 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL3_CONFIG | ( | __PLL3M__,
 |  | __PLL3N__,
 |  | __PLL3P__,
 |  | __PLL3Q__,
 |  | __PLL3R__
 | ) |
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
                       } while(0)

Macro to configures the PLL3 multiplication and division factors.

Note:
This function must be used only when PLL3 is disabled.
Parameters:
__PLL3M__ specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLL3N__ specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.
Note:
You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
Parameters:
__PLL3P__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLL3Q__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLL3R__ | specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Note:
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
Return values:
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 2383 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)

Definition at line 2322 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL3ON)

Macros to enable or disable the main PLL3.

Note:
After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.
PLL3 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 2321 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCIRANGE ( __RCC_PLL3VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

Macro to select the PLL3 reference frequency range.

Parameters:
__RCC_PLL3VCIRange__ specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 2418 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCORANGE ( __RCC_PLL3VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

Macro to select the PLL3 reference frequency range.

Parameters:
__RCC_PLL3VCORange__ specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
  • RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 2432 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3CLKOUT_DISABLE ( __RCC_PLL3ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Definition at line 2349 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3CLKOUT_ENABLE ( __RCC_PLL3ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

Note:
Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power.
Parameters:
__RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
  • RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values:
None

Definition at line 2347 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_CONFIG ( __RCC_PLL3FRACN__ ) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)

Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
Parameters:
__RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
Note:
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:
None

Definition at line 2407 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Definition at line 2331 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
Return values:
None

Definition at line 2329 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_RNG_CONFIG ( __RNGCLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

macro to configure the RNG clock (RNGCLK).

Parameters:
__RNGCLKSource__ specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 3904 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __RCC_SAI1CLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

Macro to Configure the SAI1 clock source.

Parameters:
__RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
  • RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
  • RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
Return values:
None

Definition at line 2450 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2A_CONFIG ( __RCC_SAI2ACLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))

Macro to Configure the SAI2A clock source.

Parameters:
__RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
  • RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
  • RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
  • RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP
  • RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
  • RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
Return values:
None

Definition at line 2586 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2B_CONFIG ( __RCC_SAI2BCLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))

Macro to Configure the SAI2B clock source.

Parameters:
__RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
  • RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
  • RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
  • RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP
  • RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
  • RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
Return values:
None

Definition at line 2615 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC_CONFIG ( __SDMMCCLKSource__ ) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

Macro to configure the SDMMC clock.

Parameters:
__SDMMCCLKSource__ specifies clock source for SDMMC This parameter can be one of the following values:
  • RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
  • RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

Definition at line 3879 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPDIFRX_CONFIG ( __RCC_SPDIFCLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

Macro to Configure the SPDIFRX clock source.

Parameters:
__RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values:
  • RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
  • RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
  • RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
  • RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
Return values:
None

Definition at line 2483 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI123_CONFIG ( __RCC_SPI123CLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

Macro to Configure the SPI1/2/3 clock source.

Parameters:
__RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
  • RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
  • RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
  • RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
  • RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
Return values:
None

Definition at line 3649 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI1 clock source.

Parameters:
__RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
  • RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
Return values:
None

Definition at line 3679 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI2 clock source.

Parameters:
__RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
  • RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
Return values:
None

Definition at line 3703 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI3 clock source.

Parameters:
__RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
  • RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
Return values:
None

Definition at line 3727 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI45_CONFIG ( __RCC_SPI45CLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

Macro to Configure the SPI4/5 clock source.

Parameters:
__RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
  • RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
  • RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
  • RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
  • RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
  • RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
Return values:
None

Definition at line 3756 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI4 clock source.

Parameters:
__RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
Return values:
None

Definition at line 3788 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI5 clock source.

Parameters:
__RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
Return values:
None

Definition at line 3814 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CONFIG ( __RCC_SPI6CLKSource__ ) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

Macro to Configure the SPI6 clock source.

Parameters:
__RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
  • RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)
Return values:
None (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 3849 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SWPMI1_CONFIG ( __SWPMI1CLKSource__ ) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

Macro to configure the SWPMI1 clock.

Parameters:
__SWPMI1CLKSource__ specifies the SWPMI1 clock source. This parameter can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 3490 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ )
Value:
do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
                                                 RCC->CFGR |= (__PRESC__);       \
                                                }while(0)

Macro to configure the Timers clocks prescalers.

Parameters:
__PRESC__ specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2

Definition at line 3952 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART4 clock (UART4CLK).

Parameters:
__UART4CLKSource__ specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2960 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART5CLK).

Parameters:
__UART5CLKSource__ specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2984 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART7CLK).

Parameters:
__UART7CLKSource__ specifies the UART7 clock source. This parameter can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 3032 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART8 clock (UART8CLK).

Parameters:
__UART8CLKSource__ specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 3056 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the UART9 clock (UART9CLK).

Parameters:
__UART8CLKSource__ specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
  • RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
  • RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
  • RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
  • RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
  • RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

Definition at line 3081 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the USART10 clock (USART10CLK).

Parameters:
__UART8CLKSource__ specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
  • RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
  • RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

Definition at line 3107 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART16910_CONFIG ( __USART16910CLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

macro to configure the USART1/6/9* /10* clock (USART16CLK).

Parameters:
__USART16CLKSource__ specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values:
  • RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
(*) : Available on some STM32H7 lines only.

Definition at line 2818 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG

Definition at line 2821 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1CLKSource__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2888 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART234578_CONFIG ( __USART234578CLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))

macro to configure the USART234578 clock (USART234578CLK).

Parameters:
__USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values:
  • RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

Definition at line 2858 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2CLKSource__ specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2912 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3CLKSource__ specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2936 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the USART6 clock (USART6CLK).

Parameters:
__USART6CLKSource__ specifies the USART6 clock source. This parameter can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 3008 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_CONFIG ( __USBCLKSource__ ) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

Macro to configure the USB clock (USBCLK).

Parameters:
__USBCLKSource__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

Definition at line 3437 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx CRS Extended Features

Defines
RCCEx CRS Extended Features
RCCEx

Defines

#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable or disable the automatic hardware adjustment of TRIM bits.

Return values:
None

Definition at line 4090 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable the automatic hardware adjustment of TRIM bits.

Note:
When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 4084 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_CEN)

Disable the oscillator clock for frequency error counter.

Return values:
None

Definition at line 4077 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_CEN)

Enable the oscillator clock for frequency error counter.

Note:
when the CEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 4071 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after pre-scaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
None

Definition at line 4102 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx

Modules | Defines
RCCEx
STM32H7xx_HAL_Driver

RCC HAL module driver. More...

Modules

Private Defines
Exported Functions
Private Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Private Macros
RCCEx Exported Macros
RCCEx CRS Extended Features

Defines

#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)

Detailed Description

RCC HAL module driver.

Define Documentation

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                 } \
                                               } while(0)

Definition at line 4052 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )
Value:
do { \
                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                 } \
                                               } while(0)

Definition at line 4008 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 3981 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 3969 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Return values:
The new state of _FLAG_ (TRUE or FALSE).

Definition at line 4032 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the CRS interrupt source to check. This parameter can be one of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 3992 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

Clear the CRS specified FLAG.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Note:
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values:
None

Definition at line 4050 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

Clear the CRS interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
  • RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
  • RCC_CRS_IT_SYNCERR SYNC error interrupt
  • RCC_CRS_IT_SYNCMISS SYNC missed interrupt

Definition at line 4006 of file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG_Private_Defines

Defines
RNG_Private_Defines
RNG

Defines

#define | RNG_HTCFG_1 0x17590ABCU
#define | RNG_HTCFG 0x000CAA74U

Define Documentation

#define RNG_HTCFG 0x000CAA74U

for best latency and To be compliant with NIST

Definition at line 119 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init().

#define RNG_HTCFG_1 0x17590ABCU

magic number

Definition at line 117 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 131 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), and HAL_RNG_Init().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_InitTypeDef Struct Reference
RNG Init Structure definition

#include <stm32h7xx_hal_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

Definition at line 51 of file stm32h7xx_hal_rng.h.

Field Documentation

uint32_t RNG_InitTypeDef::ClockErrorDetection

CED Clock error detection

Definition at line 53 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rng.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 63 of file stm32h7xx_hal_rng.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Handle Structure definition

Data Structures | Typedefs | Enumerations
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct | __RNG_HandleTypeDef

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng)

HAL RNG Callback pointer definition.

pointer to a common RNG callback function

Definition at line 124 of file stm32h7xx_hal_rng.h.

typedef void(* pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit)

pointer to an RNG Data Ready specific callback function

Definition at line 125 of file stm32h7xx_hal_rng.h.

typedef struct __RNG_HandleTypeDef RNG_HandleTypeDef

Enumeration Type Documentation

enum HAL_RNG_CallbackIDTypeDef

HAL RNG Callback ID enumeration definition.

Enumerator:
HAL_RNG_ERROR_CB_ID

RNG Error Callback ID

HAL_RNG_MSPINIT_CB_ID

RNG MspInit callback ID

HAL_RNG_MSPDEINIT_CB_ID

RNG MspDeInit callback ID

Definition at line 112 of file stm32h7xx_hal_rng.h.

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STM32H7B3xQ HAL User Manual: __RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32h7xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
RNG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | RandomNumber
void(* | ReadyDataCallback )(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)
void(* | ErrorCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspInitCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspDeInitCallback )(struct __RNG_HandleTypeDef *hrng)

Detailed Description

Definition at line 81 of file stm32h7xx_hal_rng.h.

Field Documentation

void(* __RNG_HandleTypeDef::ErrorCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Error Callback

Definition at line 100 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

__IO uint32_t __RNG_HandleTypeDef::ErrorCode

RNG Error code

Definition at line 94 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetError(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), HAL_RNG_UnRegisterReadyDataCallback(), HAL_RNGEx_GetConfig(), HAL_RNGEx_LockConfig(), and HAL_RNGEx_SetConfig().

RNG_InitTypeDef __RNG_HandleTypeDef::Init

RNG configuration parameters

Definition at line 88 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

RNG_TypeDef* __RNG_HandleTypeDef::Instance

Register base address

Definition at line 86 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNGEx_GetConfig(), HAL_RNGEx_LockConfig(), and HAL_RNGEx_SetConfig().

HAL_LockTypeDef __RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 90 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

void(* __RNG_HandleTypeDef::MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp DeInit callback

Definition at line 103 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

void(* __RNG_HandleTypeDef::MspInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp Init callback

Definition at line 102 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

uint32_t __RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 96 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

void(* __RNG_HandleTypeDef::ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)

RNG Data Ready Callback

Definition at line 99 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterReadyDataCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

__IO HAL_RNG_StateTypeDef __RNG_HandleTypeDef::State

RNG communication state

Definition at line 92 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), HAL_RNG_UnRegisterReadyDataCallback(), HAL_RNGEx_GetConfig(), HAL_RNGEx_LockConfig(), and HAL_RNGEx_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rng.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 146 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 145 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 147 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), and HAL_RNG_IRQHandler().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 156 of file stm32h7xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 155 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 157 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Clock Error Detection

Defines
RNG Clock Error Detection
RNG Exported Constants

Defines

#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define RNG_CED_DISABLE RNG_CR_CED

Clock error detection Disabled

Definition at line 166 of file stm32h7xx_hal_rng.h.

#define RNG_CED_ENABLE 0x00000000U

Clock error detection Enabled

Definition at line 165 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Error Definition

Defines
RNG Error Definition
RNG Exported Constants

Defines

#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U

Define Documentation

#define HAL_RNG_ERROR_BUSY 0x00000004U

Busy error

Definition at line 179 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNGEx_GetConfig(), HAL_RNGEx_LockConfig(), and HAL_RNGEx_SetConfig().

#define HAL_RNG_ERROR_CLOCK 0x00000010U

Clock error

Definition at line 181 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U

Invalid Callback error

Definition at line 176 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

#define HAL_RNG_ERROR_NONE 0x00000000U

No error

Definition at line 174 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_Init().

#define HAL_RNG_ERROR_SEED 0x00000008U

Seed error

Definition at line 180 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_TIMEOUT 0x00000002U

Timeout error

Definition at line 178 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), and HAL_RNGEx_SetConfig().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__ | RNG handle
__FLAG__ | RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 243 of file stm32h7xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 281 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 221 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), and HAL_RNGEx_SetConfig().

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 257 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 214 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), and HAL_RNGEx_SetConfig().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 250 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__ RNG Handle
__FLAG__ RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 233 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), and HAL_RNG_Init().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 269 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init(), and HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0U)

Reset RNG handle state.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 200 of file stm32h7xx_hal_rng.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and configuration functions

Functions
Initialization and configuration functions
RNG Exported Functions

Initialization and configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Detailed Description

Initialization and configuration functions.

 ===============================================================================
          ##### Initialization and configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 284 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_NONE, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_MspDeInit(), HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::MspDeInitCallback, RNG_CED_ENABLE, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

< magic number must be written immediately before to RNG_HTCRG

Definition at line 168 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_DISABLE, __HAL_RNG_ENABLE, __HAL_RNG_GET_FLAG, __HAL_RNG_GET_IT, assert_param, RNG_InitTypeDef::ClockErrorDetection, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_NONE, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_ErrorCallback(), HAL_RNG_MspInit(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Init, __RNG_HandleTypeDef::Instance, IS_RNG_CED, __RNG_HandleTypeDef::Lock, __RNG_HandleTypeDef::MspInitCallback, __RNG_HandleTypeDef::ReadyDataCallback, RNG_FLAG_SECS, RNG_HTCFG, RNG_HTCFG_1, RNG_IT_SEI, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 376 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_UnRegisterCallback().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 361 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_RegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID,
 |  | pRNG_CallbackTypeDef | pCallback
 | ) |  |

Register a User RNG Callback To be used instead of the weak predefined callback.

Parameters:
hrng | RNG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 398 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | pRNG_ReadyDataCallbackTypeDef | pCallback
 | ) |  |

Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng | RNG handle
pCallback | pointer to the Data Ready Callback function
Return values:
HAL status

Definition at line 550 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.

Parameters:
hrng RNG handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 479 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ErrorCallback(), HAL_RNG_MspDeInit(), HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MspInit(), HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback ( RNG_HandleTypeDef * hrng )

UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng RNG handle
Return values:
HAL status

Definition at line 586 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 858 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
This function checks value of RNG_FLAG_DRDY flag to know if valid random number is available in the DR register (RNG_FLAG_DRDY flag set whenever a random number is available through the RNG_DR register). After transitioning from 0 to 1 (random number available), RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading four words from the RNG_DR register, i.e. further function calls will immediately return a new u32 random number (additional words are available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
When no more random number data is available in DR register, RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 650 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 704 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and __RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 753 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CLOCK, HAL_RNG_ERROR_SEED, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, __RNG_HandleTypeDef::ReadyDataCallback, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and __RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 825 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Note:
When RNG_FLAG_DRDY flag value is set, first random number has been read from DR register in IRQ Handler and is provided as callback parameter. Depending on valid data available in the conditioning output buffer, additional words can be read by the application from DR register till DRDY bit remains high.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | generated random number.
Return values:
None

Definition at line 842 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterReadyDataCallback().

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STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_RNG_GetError ( RNG_HandleTypeDef * hrng )

Return the RNG handle error code.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
RNG Error Code

Definition at line 902 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode.

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 892 of file stm32h7xx_hal_rng.c.

References __RNG_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Define Documentation

#define IS_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == RNG_CED_ENABLE) || \
                                ((__MODE__) == RNG_CED_DISABLE))

Verify the RNG Clock Error Detection mode.

Parameters:
__MODE__ RNG Clock Error Detection mode
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 361 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                            ((FLAG) == RNG_FLAG_CECS) || \
                            ((FLAG) == RNG_FLAG_SECS))

Definition at line 352 of file stm32h7xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 349 of file stm32h7xx_hal_rng.h.

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STM32H7B3xQ HAL User Manual: RNGEx_Private_Defines

Defines
RNGEx_Private_Defines
RNGEx

Defines

#define | RNG_HTCFG_1 0x17590ABCU
#define | RNG_HTCFG 0x000CAA74U

Define Documentation

#define RNG_HTCFG 0x000CAA74U

for best latency and To be compliant with NIST

Definition at line 49 of file stm32h7xx_hal_rng_ex.c.

Referenced by HAL_RNGEx_SetConfig().

#define RNG_HTCFG_1 0x17590ABCU

magic number

Definition at line 47 of file stm32h7xx_hal_rng_ex.c.

Referenced by HAL_RNGEx_SetConfig().

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STM32H7B3xQ HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNGEx

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 61 of file stm32h7xx_hal_rng_ex.c.

Referenced by HAL_RNGEx_SetConfig().

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STM32H7B3xQ HAL User Manual: RNG_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_ConfigTypeDef Struct Reference
RNGEx Exported Types

RNGEX Configuration Structure definition. More...

#include <stm32h7xx_hal_rng_ex.h>

Data Fields

uint32_t | Config1
uint32_t | Config2
uint32_t | Config3
uint32_t | ClockDivider
uint32_t | NistCompliance

Detailed Description

RNGEX Configuration Structure definition.

Definition at line 53 of file stm32h7xx_hal_rng_ex.h.

Field Documentation

uint32_t RNG_ConfigTypeDef::ClockDivider

Clock Divider factor.This parameter can be a value of Value used to configure an internal

Definition at line 58 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_GetConfig(), and HAL_RNGEx_SetConfig().

uint32_t RNG_ConfigTypeDef::Config1

Config1 must be a value between 0 and 0x3F

Definition at line 55 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_GetConfig(), and HAL_RNGEx_SetConfig().

uint32_t RNG_ConfigTypeDef::Config2

Config2 must be a value between 0 and 0x7

Definition at line 56 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_GetConfig(), and HAL_RNGEx_SetConfig().

uint32_t RNG_ConfigTypeDef::Config3

Config3 must be a value between 0 and 0xF

Definition at line 57 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_GetConfig(), and HAL_RNGEx_SetConfig().

uint32_t RNG_ConfigTypeDef::NistCompliance

NIST compliance.This parameter can be a value of NIST Compliance configuration

Definition at line 60 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_GetConfig(), and HAL_RNGEx_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rng_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Value used to configure an internal

Defines
Value used to configure an internal
RNGEX Exported Constants

programmable divider acting on the incoming RNG clock More...

Defines

#define | RNG_CLKDIV_BY_1 (0x00000000UL)
#define | RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
#define | RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
#define | RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
#define | RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

Detailed Description

programmable divider acting on the incoming RNG clock

Define Documentation

#define RNG_CLKDIV_BY_1 (0x00000000UL)

No clock division

Definition at line 77 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)

1024 RNG clock cycles per internal RNG clock

Definition at line 96 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

128 RNG clock cycles per internal RNG clock

Definition at line 90 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)

16 RNG clock cycles per internal RNG clock

Definition at line 84 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

16384 RNG clock cycles per internal RNG clock

Definition at line 104 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)

2 RNG clock cycles per internal RNG clock

Definition at line 78 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

2048 RNG clock cycles per internal RNG clock

Definition at line 98 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)

256 RNG clock cycles per internal RNG clock

Definition at line 92 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

32 RNG clock cycles per internal RNG clock

Definition at line 86 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

32768 RNG clock cycles per internal RNG clock

Definition at line 106 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)

4 RNG clock cycles per internal RNG clock

Definition at line 80 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)

4096 RNG clock cycles per internal RNG clock

Definition at line 100 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)

512 RNG clock cycles per internal RNG clock

Definition at line 94 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

64 RNG clock cycles per internal RNG clock

Definition at line 88 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

8 RNG clock cycles per internal RNG clock

Definition at line 82 of file stm32h7xx_hal_rng_ex.h.

#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

8192 RNG clock cycles per internal RNG clock

Definition at line 102 of file stm32h7xx_hal_rng_ex.h.

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STM32H7B3xQ HAL User Manual: NIST Compliance configuration

Defines
NIST Compliance configuration
RNGEX Exported Constants

Defines

#define | RNG_NIST_COMPLIANT (0x00000000UL)
#define | RNG_CUSTOM_NIST (RNG_CR_NISTC)

Define Documentation

#define RNG_CUSTOM_NIST (RNG_CR_NISTC)

Custom NIST configuration

Definition at line 116 of file stm32h7xx_hal_rng_ex.h.

#define RNG_NIST_COMPLIANT (0x00000000UL)

NIST compliant configuration

Definition at line 115 of file stm32h7xx_hal_rng_ex.h.

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STM32H7B3xQ HAL User Manual: RNGEx Private Types

RNGEx Private Types
RNGEx
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STM32H7B3xQ HAL User Manual: RNGEx Private Variables

RNGEx Private Variables
RNGEx
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STM32H7B3xQ HAL User Manual: RNGEx Private Macros

Defines
RNGEx Private Macros
RNGEx

Defines

#define | IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__)
#define | IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__)
#define | IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
#define | IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
#define | IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

Define Documentation

#define IS_RNG_CLOCK_DIVIDER ( __CLOCK_DIV__ )
Value:
(((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))

Definition at line 158 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_SetConfig().

#define IS_RNG_CONFIG1 ( __CONFIG1__ ) ((__CONFIG1__) <= 0x3FUL)

Definition at line 179 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_SetConfig().

#define IS_RNG_CONFIG2 ( __CONFIG2__ ) ((__CONFIG2__) <= 0x07UL)

Definition at line 181 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_SetConfig().

#define IS_RNG_CONFIG3 ( __CONFIG3__ ) ((__CONFIG3__) <= 0xFUL)

Definition at line 183 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_SetConfig().

#define IS_RNG_NIST_COMPLIANCE ( __NIST_COMPLIANCE__ )
Value:
(((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
                                                     ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))

Definition at line 176 of file stm32h7xx_hal_rng_ex.h.

Referenced by HAL_RNGEx_SetConfig().

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STM32H7B3xQ HAL User Manual: RNGEx Private Functions

RNGEx Private Functions
RNGEx
Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNGEx_Exported_Functions_Group1

Functions
RNGEx_Exported_Functions_Group1
RNGEx Exported Functions

Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RNGEx_SetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Configure the RNG with the specified parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_GetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Get the RNG Configuration and fill parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_LockConfig (RNG_HandleTypeDef *hrng)
RNG current configuration lock.

Detailed Description

Configuration functions.

 ===============================================================================
          ##### Configuration and lock functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef
      (+) Lock RNG configuration Allows user to lock a configuration until next reset.

Function Documentation

HAL_StatusTypeDef HAL_RNGEx_GetConfig | ( | RNG_HandleTypeDef * | hrng,
 |  | RNG_ConfigTypeDef * | pConf
 | ) |  |

Get the RNG Configuration and fill parameters in the RNG_ConfigTypeDef.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
pConf,: pointer to a RNG_ConfigTypeDef structure that contains the configuration information for RNG module
Return values:
HAL status

Definition at line 194 of file stm32h7xx_hal_rng_ex.c.

References RNG_ConfigTypeDef::ClockDivider, RNG_ConfigTypeDef::Config1, RNG_ConfigTypeDef::Config2, RNG_ConfigTypeDef::Config3, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, RNG_ConfigTypeDef::NistCompliance, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNGEx_LockConfig ( RNG_HandleTypeDef * hrng )

RNG current configuration lock.

Note:
This function allows to lock RNG peripheral configuration. Once locked, HW RNG reset has to be perfomed prior any further configuration update.
Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 243 of file stm32h7xx_hal_rng_ex.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNGEx_SetConfig | ( | RNG_HandleTypeDef * | hrng,
 |  | RNG_ConfigTypeDef * | pConf
 | ) |  |

Configure the RNG with the specified parameters in the RNG_ConfigTypeDef.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
pConf,: pointer to a RNG_ConfigTypeDef structure that contains the configuration information for RNG module
Return values:
HAL status

< magic number must be written immediately before to RNG_HTCRG

Definition at line 99 of file stm32h7xx_hal_rng_ex.c.

References __HAL_RNG_DISABLE, __HAL_RNG_ENABLE, assert_param, RNG_ConfigTypeDef::ClockDivider, RNG_ConfigTypeDef::Config1, RNG_ConfigTypeDef::Config2, RNG_ConfigTypeDef::Config3, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, IS_RNG_CLOCK_DIVIDER, IS_RNG_CONFIG1, IS_RNG_CONFIG2, IS_RNG_CONFIG3, IS_RNG_NIST_COMPLIANCE, RNG_ConfigTypeDef::NistCompliance, RNG_HTCFG, RNG_HTCFG_1, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Exported Types

Data Structures | Typedefs | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u,
HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12u,
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 13u, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 14u, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 15u, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 16u,
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 17u, HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 19u, HAL_RTC_MSPINIT_CB_ID = 20u, HAL_RTC_MSPDEINIT_CB_ID = 21u
}
HAL RTC Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc)

HAL RTC Callback pointer definition.

pointer to an RTC callback function

Definition at line 277 of file stm32h7xx_hal_rtc.h.

typedef struct __RTC_HandleTypeDef RTC_HandleTypeDef

RTC Handle Structure definition.

Enumeration Type Documentation

enum HAL_RTC_CallbackIDTypeDef

HAL RTC Callback ID enumeration definition.

Enumerator:
HAL_RTC_ALARM_A_EVENT_CB_ID

RTC Alarm A Event Callback ID

HAL_RTC_ALARM_B_EVENT_CB_ID

RTC Alarm B Event Callback ID

HAL_RTC_TIMESTAMP_EVENT_CB_ID

RTC TimeStamp Event Callback ID

HAL_RTC_WAKEUPTIMER_EVENT_CB_ID

RTC WakeUp Timer Event Callback ID

HAL_RTC_TAMPER1_EVENT_CB_ID

RTC Tamper 1 Callback ID

HAL_RTC_TAMPER2_EVENT_CB_ID

RTC Tamper 2 Callback ID

HAL_RTC_TAMPER3_EVENT_CB_ID

RTC Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID

RTC Internal Tamper 1 Callback ID

HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID

RTC Internal Tamper 2 Callback ID

HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID

RTC Internal Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID

RTC Internal Tamper 4 Callback ID

HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID

RTC Internal Tamper 5 Callback ID

HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID

RTC Internal Tamper 6 Callback ID

HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID

RTC Internal Tamper 8 Callback ID

HAL_RTC_MSPINIT_CB_ID

RTC Msp Init callback ID

HAL_RTC_MSPDEINIT_CB_ID

RTC Msp DeInit callback ID

Definition at line 239 of file stm32h7xx_hal_rtc.h.

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 47 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType
uint32_t | OutPutPullUp

Detailed Description

RTC Configuration Structure definition.

Definition at line 60 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 65 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC_Hour_Formats

Definition at line 62 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTCEx_Output_selection_Definitions

Definition at line 71 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 77 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPullUp

Specifies the RTC Output Pull-Up mode. This parameter can be a value of RTC Output Pull-Up ALARM OUT

Definition at line 83 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 74 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 80 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 68 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 91 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLight Saving Definitions

Definition at line 116 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 93 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 97 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 110 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 100 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BKP bit in CR register to store the operation. This parameter can be a value of RTC Store Operation Definitions

Definition at line 119 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 106 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 103 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 127 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 135 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions (in BCD format)

Definition at line 132 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 129 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 138 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 146 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 163 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 159 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC Alarm Date WeekDay Definitions

Definition at line 156 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC Alarm Mask Definitions

Definition at line 150 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 153 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 148 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State
void(* | AlarmAEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | AlarmBEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | TimeStampEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | WakeUpTimerEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper2EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper2EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper4EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper5EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper6EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper8EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspInitCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspDeInitCallback )(struct __RTC_HandleTypeDef *hrtc)

Detailed Description

RTC Handle Structure definition.

Definition at line 171 of file stm32h7xx_hal_rtc.h.

Field Documentation

void(* __RTC_HandleTypeDef::AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm A Event callback

Definition at line 185 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm B Event callback

Definition at line 187 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

RTC_InitTypeDef __RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 178 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* __RTC_HandleTypeDef::Instance

Register base address

Definition at line 176 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), and RTC_EnterInitMode().

void(* __RTC_HandleTypeDef::InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 1 Event callback

Definition at line 200 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 2 Event callback

Definition at line 204 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 3 Event callback

Definition at line 208 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 4 Event callback

Definition at line 212 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 5 Event callback

Definition at line 216 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 6 Event callback

Definition at line 220 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 8 Event callback

Definition at line 224 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

HAL_LockTypeDef __RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 180 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

void(* __RTC_HandleTypeDef::MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp DeInit callback

Definition at line 229 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::MspInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp Init callback

Definition at line 227 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

__IO HAL_RTCStateTypeDef __RTC_HandleTypeDef::State

Time communication state

Definition at line 182 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_RegisterCallback(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_UnRegisterCallback(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetActiveSeed(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void(* __RTC_HandleTypeDef::Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 1 Event callback

Definition at line 193 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 2 Event callback

Definition at line 195 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 3 Event callback

Definition at line 197 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC TimeStamp Event callback

Definition at line 189 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC WakeUpTimer Event callback

Definition at line 191 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Hour Formats Definitions

Defines
RTC Hour Formats Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 0x00000000u
#define | RTC_HOURFORMAT_12 RTC_CR_FMT

Define Documentation

#define RTC_HOURFORMAT_12 RTC_CR_FMT

Definition at line 293 of file stm32h7xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 0x00000000u

Definition at line 292 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Output Selection Definitions

Defines
RTC Output Selection Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE 0x00000000u
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Define Documentation

#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0

Definition at line 302 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1

Definition at line 303 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_DISABLE 0x00000000u

Definition at line 301 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Definition at line 306 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL

Definition at line 304 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000u
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u

Definition at line 315 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Definition at line 316 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | RTC_ALARM_OUTPUT_TYPE RTC_CR_TAMPALRM_TYPE

Define Documentation

#define RTC_ALARM_OUTPUT_TYPE RTC_CR_TAMPALRM_TYPE

Definition at line 327 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

Definition at line 326 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u

Definition at line 325 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Output Pull-Up ALARM OUT

Defines
RTC Output Pull-Up ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_PULLUP_NONE 0x00000000u
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Define Documentation

#define RTC_OUTPUT_PULLUP_NONE 0x00000000u

Definition at line 343 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Definition at line 344 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE 0x00000000u
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Define Documentation

#define RTC_OUTPUT_REMAP_NONE 0x00000000u

Definition at line 354 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Definition at line 355 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x01)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)

Definition at line 369 of file stm32h7xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)

Definition at line 370 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC DayLight Saving Definitions

Defines
RTC DayLight Saving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000u

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H

Definition at line 379 of file stm32h7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE 0x00000000u

Definition at line 380 of file stm32h7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H

Definition at line 378 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Store Operation Definitions

Defines
RTC Store Operation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET 0x00000000u
#define | RTC_STOREOPERATION_SET RTC_CR_BKP

Define Documentation

#define RTC_STOREOPERATION_RESET 0x00000000u

Definition at line 388 of file stm32h7xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET RTC_CR_BKP

Definition at line 389 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN 0x00000000u
#define | RTC_FORMAT_BCD 0x00000001u

Define Documentation

#define RTC_FORMAT_BCD 0x00000001u

Definition at line 398 of file stm32h7xx_hal_rtc.h.

#define RTC_FORMAT_BIN 0x00000000u

Definition at line 397 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Month Date Definitions (in BCD format)

Defines
RTC Month Date Definitions (in BCD format)
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 409 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 413 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 417 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 407 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 406 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 412 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 411 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 408 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 410 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 416 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 415 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 414 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 430 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 426 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 431 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Definition at line 432 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 429 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 427 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 428 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm Date WeekDay Definitions

Defines
RTC Alarm Date WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u

Definition at line 441 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Definition at line 442 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm Mask Definitions

Defines
RTC Alarm Mask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE 0x00000000u
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL

Define Documentation

#define RTC_ALARMMASK_ALL
Value:
(RTC_ALARMMASK_DATEWEEKDAY | \
                                           RTC_ALARMMASK_HOURS       | \
                                           RTC_ALARMMASK_MINUTES     | \
                                           RTC_ALARMMASK_SECONDS)

Definition at line 456 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 452 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 453 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 454 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE 0x00000000u

Definition at line 451 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 455 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 467 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 468 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000u
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u

< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 477 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Definition at line 507 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:0] are compared and must match to activate alarm.

Definition at line 505 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared.

Definition at line 479 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared.

Definition at line 497 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared.

Definition at line 499 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared.

Definition at line 501 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared.

Definition at line 503 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared.

Definition at line 481 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared.

Definition at line 483 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared.

Definition at line 485 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared.

Definition at line 487 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared.

Definition at line 489 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared.

Definition at line 491 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared.

Definition at line 493 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared.

Definition at line 495 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE

Define Documentation

#define RTC_IT_ALRA RTC_CR_ALRAIE

Enable Alarm A Interrupt

Definition at line 518 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB RTC_CR_ALRBIE

Enable Alarm B Interrupt

Definition at line 519 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TS RTC_CR_TSIE

Enable Timestamp Interrupt

Definition at line 516 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define RTC_IT_WUT RTC_CR_WUTIE

Enable Wakeup timer Interrupt

Definition at line 517 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF RTC_ICSR_RECALPF
#define | RTC_FLAG_INITF RTC_ICSR_INITF
#define | RTC_FLAG_RSF RTC_ICSR_RSF
#define | RTC_FLAG_INITS RTC_ICSR_INITS
#define | RTC_FLAG_SHPF RTC_ICSR_SHPF
#define | RTC_FLAG_WUTWF RTC_ICSR_WUTWF
#define | RTC_FLAG_ALRBWF RTC_ICSR_ALRBWF
#define | RTC_FLAG_ALRAWF RTC_ICSR_ALRAWF
#define | RTC_FLAG_ITSF RTC_SR_ITSF
#define | RTC_FLAG_TSOVF RTC_SR_TSOVF
#define | RTC_FLAG_TSF RTC_SR_TSF
#define | RTC_FLAG_WUTF RTC_SR_WUTF
#define | RTC_FLAG_ALRBF RTC_SR_ALRBF
#define | RTC_FLAG_ALRAF RTC_SR_ALRAF

Define Documentation

#define RTC_FLAG_ALRAF RTC_SR_ALRAF

Alarm A flag

Definition at line 567 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF RTC_ICSR_ALRAWF

Alarm A write operation pending flag

Definition at line 549 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF RTC_SR_ALRBF

Alarm B flag

Definition at line 564 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF RTC_ICSR_ALRBWF

Alarm B write operation pending flag

Definition at line 546 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF RTC_ICSR_INITF

Initialization pending flag

Definition at line 531 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_INITS RTC_ICSR_INITS

Initialization status flag

Definition at line 537 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_ITSF RTC_SR_ITSF

Internal Time-stamp flag

Definition at line 552 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define RTC_FLAG_RECALPF RTC_ICSR_RECALPF

Recalibration pending Flag

Definition at line 528 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_RSF RTC_ICSR_RSF

Registers synchronization flag

Definition at line 534 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_SHPF RTC_ICSR_SHPF

Shift operation pending flag

Definition at line 540 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_TSF RTC_SR_TSF

Time-stamp flag

Definition at line 558 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_TSOVF RTC_SR_TSOVF

Time-stamp overflow flag

Definition at line 555 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF RTC_SR_WUTF

Wakeup timer flag

Definition at line 561 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF RTC_ICSR_WUTWF

Wakeup timer write operation pending flag

Definition at line 543 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Clear Flags Definitions

Defines
RTC Clear Flags Definitions
RTC Exported Constants

Defines

#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Define Documentation

#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Clear Alarm A flag

Definition at line 592 of file stm32h7xx_hal_rtc.h.

#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF

Clear Alarm B flag

Definition at line 589 of file stm32h7xx_hal_rtc.h.

#define RTC_CLEAR_ITSF RTC_SCR_CITSF

Clear Internal Time-stamp flag

Definition at line 577 of file stm32h7xx_hal_rtc.h.

#define RTC_CLEAR_TSF RTC_SCR_CTSF

Clear Time-stamp flag

Definition at line 583 of file stm32h7xx_hal_rtc.h.

#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF

Clear Time-stamp overflow flag

Definition at line 580 of file stm32h7xx_hal_rtc.h.

#define RTC_CLEAR_WUTF RTC_SCR_CWUTF

Clear Wakeup timer flag

Definition at line 586 of file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR |= __FLAG__)

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 839 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 773 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 762 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 969 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 881 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 922 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 861 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 934 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                           } while(0u)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 949 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 871 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 916 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 851 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 928 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                           } while(0u)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 940 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None

Definition at line 991 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 959 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 812 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 785 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 800 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 737 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 730 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 751 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 744 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                                \
                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);              \
                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
                        } while(0u);

Add 1 hour (summer time change).

Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 700 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                                \
                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);              \
                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
                        } while(0u);

Subtract 1 hour (winter time change).

Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 717 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                              \
                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;  \
                                                      (__HANDLE__)->MspInitCallback = NULL;       \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                     }while(0u)

Reset RTC handle state.

Parameters:
__HANDLE__ RTC handle.
Return values:
None

Definition at line 661 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                        \
                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
                            (__HANDLE__)->Instance->WPR = 0x53U;   \
                          } while(0u)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 675 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                        \
                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
                          } while(0u)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 686 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Note:
This function doesn't reset the RTC Backup Data registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 394 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::MspDeInitCallback, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, __RTC_HandleTypeDef::State, and TAMP_OFFSET.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC peripheral.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 227 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper1EventCallback(), HAL_RTCEx_InternalTamper2EventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_InternalTamper8EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), RTC_InitTypeDef::HourFormat, __RTC_HandleTypeDef::Init, __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper2EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::InternalTamper8EventCallback, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_PULLUP, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, __RTC_HandleTypeDef::Lock, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutPullUp, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), __RTC_HandleTypeDef::State, RTC_InitTypeDef::SynchPrediv, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 861 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 846 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTC_RegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID,
 |  | pRTC_CallbackTypeDef | pCallback
 | ) |  |

Register a User RTC Callback To be used instead of the weak predefined callback.

Parameters:
hrtc | RTC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 561 of file stm32h7xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID, HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper2EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::InternalTamper8EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

HAL_StatusTypeDef HAL_RTC_UnRegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.

Parameters:
hrtc RTC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
Return values:
HAL status

Definition at line 715 of file stm32h7xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_AlarmAEventCallback(), HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID, HAL_RTC_MspDeInit(), HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MspInit(), HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper1EventCallback(), HAL_RTCEx_InternalTamper2EventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_InternalTamper8EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper2EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::InternalTamper8EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to Date structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 1196 of file stm32h7xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 1038 of file stm32h7xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1082 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, __RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 899 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1903 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1806 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, CM7_CPUID, HAL_GetCurrentCPUID(), HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), __RTC_HandleTypeDef::Instance, RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc RTC handle
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1641 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Date structure
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1745 of file stm32h7xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1919 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1250 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 1444 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1978 of file stm32h7xx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 2032 of file stm32h7xx_hal_rtc.c.

References __RTC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK 0xFFFFFFFFu
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_TIMEOUT_VALUE 1000u
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17

Define Documentation

#define RTC_DR_RESERVED_MASK
Value:
(RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
                                 RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
                                 RTC_DR_DU)

Definition at line 1084 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 1100 of file stm32h7xx_hal_rtc.h.

#define RTC_INIT_MASK 0xFFFFFFFFu

Definition at line 1088 of file stm32h7xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))

Definition at line 1091 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000u

Definition at line 1098 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetActiveSeed(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK
Value:
(RTC_TR_PM  | RTC_TR_HT | RTC_TR_HU | \
                                 RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
                                 RTC_TR_SU)

Definition at line 1080 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Define Documentation

#define IS_RTC_ALARM ( ALARM )
Value:
(((ALARM) == RTC_ALARM_A) || \
                                  ((ALARM) == RTC_ALARM_B))

Definition at line 1187 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) > 0u) && ((DATE) <= 31u))

Definition at line 1172 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 1182 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 1174 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)

Definition at line 1185 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == 0u) || \
                                                    (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))

Definition at line 1192 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= RTC_ALRMASSR_SS)

Definition at line 1190 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))

Definition at line 1195 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1u) && ((DATE) <= 31u))

Definition at line 1162 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 1148 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_FORMAT_BIN) || \
                               ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 1155 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > 0u) && ((HOUR) <= 12u))

Definition at line 1199 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23u)

Definition at line 1201 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 1128 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM )
Value:
(((PM) == RTC_HOURFORMAT12_AM) || \
                                  ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 1145 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59u)

Definition at line 1203 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1u) && ((MONTH) <= 12u))

Definition at line 1160 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP)      || \
                               ((OUTPUT) == RTC_OUTPUT_TAMPER))

Definition at line 1116 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 1131 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_PULLUP ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))

Definition at line 1138 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                        ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 1142 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 1134 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59u)

Definition at line 1205 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 1152 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))

Definition at line 1197 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 1164 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99u)

Definition at line 1158 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 2124 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 2105 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2056 of file stm32h7xx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTC Tamper structure definition

#include <stm32h7xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Interrupt
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 48 of file stm32h7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the TAMP Filter Tamper. This parameter can be a value of RTC Tamper Filter Definitions

Definition at line 65 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Interrupt

Specifies the Tamper Interrupt. This parameter can be a value of RTC Tamper Interrupts Definitions

Definition at line 53 of file stm32h7xx_hal_rtc_ex.h.

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTC Tamper Mask Flag Definitions

Definition at line 62 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTC Tamper EraseBackUp Definitions

Definition at line 59 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTC Tamper Pin Precharge Duration Definitions

Definition at line 71 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTC Tamper Sampling Frequencies Definitions

Definition at line 68 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTC Tamper Pins Definitions

Definition at line 50 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTC Tamper Pull Up Definitions

Definition at line 74 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTC Tamper TimeStamp On Tamper Detection Definitions

Definition at line 77 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTC Tamper Triggers Definitions

Definition at line 56 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_InternalTamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InternalTamperTypeDef Struct Reference
RTCEx Internal Tamper structure definition

#include <stm32h7xx_hal_rtc_ex.h>

Data Fields

uint32_t | IntTamper
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 88 of file stm32h7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_InternalTamperTypeDef::IntTamper

Specifies the Internal Tamper Pin. This parameter can be a value of RTCEx_Internal_Tamper_Pins

Definition at line 90 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

uint32_t RTC_InternalTamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx_Tamper_TimeStampOnTamperDetection

Definition at line 93 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Seed size Definitions

Defines
Seed size Definitions
RTCEx Exported Types

Defines

#define RTC_ATAMP_SEED_NB_UINT32 4U

Define Documentation

#define RTC_ATAMP_SEED_NB_UINT32 4U

Definition at line 105 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveSeed(), and HAL_RTCEx_SetActiveTampers().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Active Tampers number Definitions

Defines
Active Tampers number Definitions
RTCEx Exported Types

Defines

#define RTC_TAMP_NB 3u

Define Documentation

#define RTC_TAMP_NB 3u

Definition at line 113 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_ATampInputTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_ATampInputTypeDef Struct Reference
RTC Active Tamper structures definitions

#include <stm32h7xx_hal_rtc_ex.h>

Data Fields

uint32_t | Enable
uint32_t | Interrupt
uint32_t | Output
uint32_t | NoErase
uint32_t | MaskFlag

Detailed Description

Definition at line 121 of file stm32h7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_ATampInputTypeDef::Enable

Specifies the Tamper input is active. This parameter can be a value of RTCEx_ActiveTamper_Enable Definitions

Definition at line 123 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ATampInputTypeDef::Interrupt

Specifies the interrupt mode This parameter can be a value of RTCEx_ActiveTamper_Interrupt Definitions

Definition at line 126 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ATampInputTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTCEx_Tamper_MaskFlag

Definition at line 136 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ATampInputTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTCEx_Tamper_EraseBackUp

Definition at line 133 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ATampInputTypeDef::Output

Specifies the TAMP output to be compared with. The same output can be used for several tamper inputs. This parameter can be a value of RTC Active Tamper selection Definition

Definition at line 129 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC_ActiveTampersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_ActiveTampersTypeDef Struct Reference
RTC Active Tamper structures definitions

#include <stm32h7xx_hal_rtc_ex.h>

Data Fields

uint32_t | ActiveFilter
uint32_t | ActiveAsyncPrescaler
uint32_t | TimeStampOnTamperDetection
uint32_t | ActiveOutputChangePeriod
uint32_t | Seed [RTC_ATAMP_SEED_NB_UINT32]
RTC_ATampInputTypeDef TampInput [RTC_TAMP_NB]

Detailed Description

Definition at line 142 of file stm32h7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_ActiveTampersTypeDef::ActiveAsyncPrescaler

Specifies the Active Tamper asynchronous Prescaler clock. This parameter can be a value of RTC Active_Tamper_Asynchronous_Prescaler clock Definitions

Definition at line 147 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ActiveTampersTypeDef::ActiveFilter

Specifies the Active tamper filter enable. This parameter can be a value of RTCEx_ActiveTamper_Filter Definitions

Definition at line 144 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ActiveTampersTypeDef::ActiveOutputChangePeriod

Specifies the Active Tamper output change period . This parameter can be a value from 0 to 7.

Definition at line 153 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ActiveTampersTypeDef::Seed[RTC_ATAMP_SEED_NB_UINT32]

Specifies the Active Tamper RNG Seed value . This parameter can be a value from 0 to (2^32-1)

Definition at line 157 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

RTC_ATampInputTypeDef RTC_ActiveTampersTypeDef::TampInput[RTC_TAMP_NB]

Specifies configuration of all active tampers. The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel

Definition at line 161 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

uint32_t RTC_ActiveTampersTypeDef::TimeStampOnTamperDetection

Specifies the timeStamp on tamper detection. This parameter can be a value of RTCEx_Tamper_TimeStampOnTamperDetection

Definition at line 150 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc_ex.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Backup Registers Number Definitions

Defines
RTC Backup Registers Number Definitions
RTCEx Exported Constants

Defines

#define BKP_REG_NUMBER TAMP_BKP_NUMBER

Define Documentation

#define BKP_REG_NUMBER TAMP_BKP_NUMBER

Definition at line 191 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Backup Registers Definitions

Defines
RTC Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 0x00u
#define | RTC_BKP_DR1 0x01u
#define | RTC_BKP_DR2 0x02u
#define | RTC_BKP_DR3 0x03u
#define | RTC_BKP_DR4 0x04u
#define | RTC_BKP_DR5 0x05u
#define | RTC_BKP_DR6 0x06u
#define | RTC_BKP_DR7 0x07u
#define | RTC_BKP_DR8 0x08u
#define | RTC_BKP_DR9 0x09u
#define | RTC_BKP_DR10 0x0Au
#define | RTC_BKP_DR11 0x0Bu
#define | RTC_BKP_DR12 0x0Cu
#define | RTC_BKP_DR13 0x0Du
#define | RTC_BKP_DR14 0x0Eu
#define | RTC_BKP_DR15 0x0Fu
#define | RTC_BKP_DR16 0x10u
#define | RTC_BKP_DR17 0x11u
#define | RTC_BKP_DR18 0x12u
#define | RTC_BKP_DR19 0x13u
#define | RTC_BKP_DR20 0x14u
#define | RTC_BKP_DR21 0x15u
#define | RTC_BKP_DR22 0x16u
#define | RTC_BKP_DR23 0x17u
#define | RTC_BKP_DR24 0x18u
#define | RTC_BKP_DR25 0x19u
#define | RTC_BKP_DR26 0x1Au
#define | RTC_BKP_DR27 0x1Bu
#define | RTC_BKP_DR28 0x1Cu
#define | RTC_BKP_DR29 0x1Du
#define | RTC_BKP_DR30 0x1Eu
#define | RTC_BKP_DR31 0x1Fu

Define Documentation

#define RTC_BKP_DR0 0x00u

Definition at line 200 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 0x01u

Definition at line 201 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 0x0Au

Definition at line 210 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 0x0Bu

Definition at line 211 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 0x0Cu

Definition at line 212 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 0x0Du

Definition at line 213 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 0x0Eu

Definition at line 214 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 0x0Fu

Definition at line 215 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 0x10u

Definition at line 216 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 0x11u

Definition at line 217 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 0x12u

Definition at line 218 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 0x13u

Definition at line 219 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 0x02u

Definition at line 202 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR20 0x14u

Definition at line 220 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR21 0x15u

Definition at line 221 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR22 0x16u

Definition at line 222 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR23 0x17u

Definition at line 223 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR24 0x18u

Definition at line 224 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR25 0x19u

Definition at line 225 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR26 0x1Au

Definition at line 226 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR27 0x1Bu

Definition at line 227 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR28 0x1Cu

Definition at line 228 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR29 0x1Du

Definition at line 229 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 0x03u

Definition at line 203 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR30 0x1Eu

Definition at line 230 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR31 0x1Fu

Definition at line 231 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 0x04u

Definition at line 204 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 0x05u

Definition at line 205 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 0x06u

Definition at line 206 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 0x07u

Definition at line 207 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 0x08u

Definition at line 208 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 0x09u

Definition at line 209 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC TimeStamp Edges Definitions

Defines
RTC TimeStamp Edges Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000u
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Definition at line 245 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING 0x00000000u

Definition at line 244 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC TimeStamp Pin Selection

Defines
RTC TimeStamp Pin Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u

Definition at line 253 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Pins Definitions

Defines
RTC Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define | TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)
#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)

Define Documentation

#define RTC_TAMPER_1 TAMP_CR1_TAMP1E

Definition at line 267 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_2 TAMP_CR1_TAMP2E

Definition at line 270 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_3 TAMP_CR1_TAMP3E

Definition at line 273 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)

Definition at line 286 of file stm32h7xx_hal_rtc_ex.h.

#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)

Definition at line 125 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_DeactivateActiveTampers().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Interrupts Definitions

Defines
RTC Tamper Interrupts Definitions
RTCEx Exported Constants

Defines

#define | RTC_IT_TAMP1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMP 0x00000000u
#define | RTC_IT_TAMPALL (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)

Define Documentation

#define RTC_IT_TAMP 0x00000000u

No such feature in RTC3

Definition at line 318 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_IT_TAMP1 TAMP_IER_TAMP1IE

Enable Tamper 1 Interrupt

Definition at line 295 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_IT_TAMP2 TAMP_IER_TAMP2IE

Enable Tamper 2 Interrupt

Definition at line 298 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_IT_TAMP3 TAMP_IER_TAMP3IE

Enable Tamper 3 Interrupt

Definition at line 301 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_IT_TAMPALL (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)

Definition at line 319 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Internal Tamper Pins Definition

Defines
RTC Internal Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E
#define | RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E
#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E
#define | RTC_INT_TAMPER_ALL

Define Documentation

#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E

Definition at line 329 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E

Definition at line 332 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E

Definition at line 335 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E

Definition at line 338 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E

Definition at line 341 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E

Definition at line 344 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E

Definition at line 347 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_INT_TAMPER_ALL
Value:
(RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
                                             RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
                                             RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
                                             RTC_INT_TAMPER_8)

Definition at line 348 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Internal Tamper Interrupt

Defines
RTC Internal Tamper Interrupt
RTCEx Exported Constants

Defines

#define | RTC_INTERNAL_TAMPER1_INTERRUPT TAMP_IER_ITAMP1IE
#define | RTC_INTERNAL_TAMPER2_INTERRUPT TAMP_IER_ITAMP2IE
#define | RTC_INTERNAL_TAMPER3_INTERRUPT TAMP_IER_ITAMP3IE
#define | RTC_INTERNAL_TAMPER4_INTERRUPT TAMP_IER_ITAMP4IE
#define | RTC_INTERNAL_TAMPER5_INTERRUPT TAMP_IER_ITAMP5IE
#define | RTC_INTERNAL_TAMPER6_INTERRUPT TAMP_IER_ITAMP6IE
#define | RTC_INTERNAL_TAMPER8_INTERRUPT TAMP_IER_ITAMP8IE

Define Documentation

#define RTC_INTERNAL_TAMPER1_INTERRUPT TAMP_IER_ITAMP1IE

Enable Internal Tamper 1 Interrupt

Definition at line 361 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER2_INTERRUPT TAMP_IER_ITAMP2IE

Enable Internal Tamper 2 Interrupt

Definition at line 364 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER3_INTERRUPT TAMP_IER_ITAMP3IE

Enable Internal Tamper 3 Interrupt

Definition at line 367 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER4_INTERRUPT TAMP_IER_ITAMP4IE

Enable Internal Tamper 4 Interrupt

Definition at line 370 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER5_INTERRUPT TAMP_IER_ITAMP5IE

Enable Internal Tamper 5 Interrupt

Definition at line 373 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER6_INTERRUPT TAMP_IER_ITAMP6IE

Enable Internal Tamper 6 Interrupt

Definition at line 376 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_INTERNAL_TAMPER8_INTERRUPT TAMP_IER_ITAMP8IE

Enable Internal Tamper 8 Interrupt

Definition at line 379 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Triggers Definitions

Defines
RTC Tamper Triggers Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x01u
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x02u
#define | RTC_TAMPERTRIGGER_LOWLEVEL 0x04u
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x08u
#define | RTC_TAMPER_1_TRIGGER TAMP_CR2_TAMP1TRG
#define | RTC_TAMPER_2_TRIGGER TAMP_CR2_TAMP2TRG
#define | RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG
#define | RTC_TAMPER_X_TRIGGER

Define Documentation

#define RTC_TAMPER_1_TRIGGER TAMP_CR2_TAMP1TRG

Definition at line 394 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_2_TRIGGER TAMP_CR2_TAMP2TRG

Definition at line 397 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG

Definition at line 400 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_X_TRIGGER
Value:
(RTC_TAMPER_1_TRIGGER |\
                                             RTC_TAMPER_2_TRIGGER |\
                                             RTC_TAMPER_3_TRIGGER)

Definition at line 413 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x02u

Warning : Filter must be RTC_TAMPERFILTER_DISABLE

Definition at line 389 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x08u

Warning : Filter must not be RTC_TAMPERFILTER_DISABLE

Definition at line 391 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERTRIGGER_LOWLEVEL 0x04u

Warning : Filter must not be RTC_TAMPERFILTER_DISABLE

Definition at line 390 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE 0x01u

Warning : Filter must be RTC_TAMPERFILTER_DISABLE

Definition at line 388 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper EraseBackUp Definitions

Defines
RTC Tamper EraseBackUp Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 TAMP_CR2_TAMP1NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK

Define Documentation

#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 TAMP_CR2_TAMP1NOERASE

Definition at line 433 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE

Definition at line 436 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE

Definition at line 439 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK
Value:
(RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\
                                              RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\
                                              RTC_DISABLE_BKP_ERASE_ON_TAMPER_3)

Definition at line 452 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u

Definition at line 425 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u

Definition at line 424 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Mask Flag Definitions

Defines
RTC Tamper Mask Flag Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00u
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01u
#define | RTC_TAMPER_1_MASK_FLAG TAMP_CR2_TAMP1MSK
#define | RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK
#define | RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK
#define | RTC_TAMPER_X_MASK_FLAG

Define Documentation

#define RTC_TAMPER_1_MASK_FLAG TAMP_CR2_TAMP1MSK

Definition at line 472 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK

Definition at line 475 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK

Definition at line 478 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_X_MASK_FLAG
Value:
(RTC_TAMPER_1_MASK_FLAG |\
                                            RTC_TAMPER_2_MASK_FLAG |\
                                            RTC_TAMPER_3_MASK_FLAG)

Definition at line 491 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u

Definition at line 463 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u

Definition at line 464 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Filter Definitions

Defines
RTC Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | RTC_TAMPERFILTER_MASK TAMP_FLTCR_TAMPFLT

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 504 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 506 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level

Definition at line 508 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 502 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_MASK TAMP_FLTCR_TAMPFLT

Masking all bits except those of field TAMPFLT[1:0].

Definition at line 510 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Sampling Frequencies Definitions

Defines
RTC Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 TAMP_FLTCR_TAMPFREQ
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 543 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 535 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 541 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 TAMP_FLTCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 547 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 533 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 539 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 545 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 537 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ

Masking all bits except those of field TAMPFREQ[2:0]

Definition at line 549 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Pin Precharge Duration Definitions

Defines
RTC Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
#define | RTC_TAMPERPRECHARGEDURATION_MASK TAMP_FLTCR_TAMPPRCH

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 580 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 582 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 584 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 586 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_MASK TAMP_FLTCR_TAMPPRCH

Masking all bits except those of field TAMPPRCH[1:0]

Definition at line 588 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper TimeStamp On Tamper Detection Definitions

Defines
RTC Tamper TimeStamp On Tamper Detection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS
#define | RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_CR_TAMPTS

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u

TimeStamp on Tamper Detection event is not saved

Definition at line 611 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS

TimeStamp on Tamper Detection event saved

Definition at line 612 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_CR_TAMPTS

Masking all bits except bit TAMPTS

Definition at line 613 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Pull Up Definitions

Defines
RTC Tamper Pull Up Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000u
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS
#define | RTC_TAMPER_PULLUP_MASK TAMP_FLTCR_TAMPPUDIS

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS

Tamper pins pre-charge is disabled

Definition at line 629 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u

Tamper pins are pre-charged before sampling

Definition at line 628 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_MASK TAMP_FLTCR_TAMPPUDIS

Maskin all bits except bit TAMPPUDIS

Definition at line 630 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Detection Ouput Definitions

Defines
RTC Tamper Detection Ouput Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERDETECTIONOUTPUT_DISABLE 0x00000000u
#define | RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE

Define Documentation

#define RTC_TAMPERDETECTIONOUTPUT_DISABLE 0x00000000u

The tamper flag is not routed on TAMPALRM

Definition at line 645 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE

The tamper flag is routed on TAMPALRM combined with the signal provided by OSEL and with the polarity provided by POL

Definition at line 646 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Tamper Flags Definitions

Defines
RTC Tamper Flags Definitions
RTCEx Exported Constants

Defines

#define | RTC_FLAG_TAMP1F TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP2F TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP3F TAMP_SR_TAMP3F

Define Documentation

#define RTC_FLAG_TAMP1F TAMP_SR_TAMP1F

Definition at line 657 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event().

#define RTC_FLAG_TAMP2F TAMP_SR_TAMP2F

Definition at line 660 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper2Event().

#define RTC_FLAG_TAMP3F TAMP_SR_TAMP3F

Definition at line 663 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper3Event().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx_ActiveTamper_Enable Definitions

Defines
RTCEx_ActiveTamper_Enable Definitions
RTCEx Exported Constants

Defines

#define | RTC_ATAMP_ENABLE 1u
#define | RTC_ATAMP_DISABLE 0u

Define Documentation

#define RTC_ATAMP_DISABLE 0u

Definition at line 683 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

#define RTC_ATAMP_ENABLE 1u

Definition at line 682 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx_ActiveTamper_Interrupt Definitions

Defines
RTCEx_ActiveTamper_Interrupt Definitions
RTCEx Exported Constants

Defines

#define | RTC_ATAMP_INTERRUPT_ENABLE 1u
#define | RTC_ATAMP_INTERRUPT_DISABLE 0u

Define Documentation

#define RTC_ATAMP_INTERRUPT_DISABLE 0u

Definition at line 692 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers().

#define RTC_ATAMP_INTERRUPT_ENABLE 1u

Definition at line 691 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx_ActiveTamper_Filter Definitions

Defines
RTCEx_ActiveTamper_Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN
#define | RTC_ATAMP_FILTER_DISABLE 0u

Define Documentation

#define RTC_ATAMP_FILTER_DISABLE 0u

Definition at line 701 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN

Definition at line 700 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Active_Tamper_Asynchronous_Prescaler clock Definitions

Defines
RTC Active_Tamper_Asynchronous_Prescaler clock Definitions
RTCEx Exported Constants

Defines

#define | RTC_ATAMP_ASYNCPRES_RTCCLK 0u
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

Define Documentation

#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u

RTCCLK

Definition at line 709 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/128

Definition at line 716 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2

RTCCLK/16

Definition at line 713 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0

RTCCLK/2

Definition at line 710 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/32

Definition at line 714 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1

RTCCLK/4

Definition at line 711 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)

RTCCLK/64

Definition at line 715 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/8

Definition at line 712 of file stm32h7xx_hal_rtc_ex.h.

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STM32H7B3xQ HAL User Manual: RTC Active Tamper selection Definition

Defines
RTC Active Tamper selection Definition
RTCEx Exported Constants

Defines

#define | RTC_ATAMP_1 0u
#define | RTC_ATAMP_2 1u
#define | RTC_ATAMP_3 2u
#define | RTC_ATAMP_4 3u
#define | RTC_ATAMP_5 4u
#define | RTC_ATAMP_6 5u
#define | RTC_ATAMP_7 6u
#define | RTC_ATAMP_8 7u

Define Documentation

#define RTC_ATAMP_1 0u

Tamper 1

Definition at line 724 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_2 1u

Tamper 2

Definition at line 725 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_3 2u

Tamper 3

Definition at line 726 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_4 3u

Tamper 4

Definition at line 727 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_5 4u

Tamper 5

Definition at line 728 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_6 5u

Tamper 6

Definition at line 729 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_7 6u

Tamper 7

Definition at line 730 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_ATAMP_8 7u

Tamper 8

Definition at line 731 of file stm32h7xx_hal_rtc_ex.h.

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STM32H7B3xQ HAL User Manual: RTC Tamper Registers Offset

Defines
RTC Tamper Registers Offset
RTCEx Exported Constants

Defines

#define TAMP_OFFSET (TAMP_BASE - RTC_BASE)

Define Documentation

#define TAMP_OFFSET (TAMP_BASE - RTC_BASE)

Definition at line 741 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTC_DeInit(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Wakeup Timer Definitions

Defines
RTC Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2

Definition at line 758 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Definition at line 759 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u

Definition at line 754 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)

Definition at line 757 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1

Definition at line 756 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0

Definition at line 755 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Smooth Calib Period Definitions

Defines
RTC Smooth Calib Period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK pulses

Definition at line 773 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK pulses

Definition at line 771 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK pulses

Definition at line 775 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Smooth Calib Plus pulses Definitions

Defines
RTC Smooth Calib Plus pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 787 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 784 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Calib Output Selection Definitions

Defines
RTC Calib Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ 0x00000000u
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Define Documentation

#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Definition at line 797 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ 0x00000000u

Definition at line 796 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Add 1 Second Parameter Definitions

Defines
RTC Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET 0x00000000u
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Define Documentation

#define RTC_SHIFTADD1S_RESET 0x00000000u

Definition at line 805 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Definition at line 806 of file stm32h7xx_hal_rtc_ex.h.

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STM32H7B3xQ HAL User Manual: RTCEx Exported Macros

Defines
RTCEx Exported Macros
RTCEx

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
Get the frequency at which each of the Tamper inputs are sampled.
#define | __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))
Get the number of consecutive samples at the specified level needed to activate a Tamper event.
#define | __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
Get the pull-up resistors precharge duration.
#define | __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))
Get the pull-up resistors status.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__) ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
Get activation status of the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT() (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG() (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG() (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated D3 Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1384 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1377 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1398 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1391 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR |= __FLAG__)

Clear the RTC Internal Time Stamp's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Note:
This flag must be cleared together with TSF flag.
Return values:
None

Definition at line 1307 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1273 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC Internal Time Stamp's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
Flag status

Definition at line 1291 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
Flag status

Definition at line 1409 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 945 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 933 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 969 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 957 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 993 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 981 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 1098 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_PollForTamper3Event().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 1029 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 1011 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
Flag status

Definition at line 1081 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_PollForTamper3Event().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 interrupt flag
  • RTC_FLAG_TAMP2F: Tamper2 interrupt flag
  • RTC_FLAG_TAMP3F: Tamper3 interrupt flag
Return values:
Flag status

Definition at line 1046 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
Flag status

Definition at line 1064 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION ( __HANDLE__ ) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))

Get the pull-up resistors precharge duration.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
Number of consecutive samples This value can be:
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK

Definition at line 1153 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_PULLUP_STATUS ( __HANDLE__ ) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))

Get the pull-up resistors status.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
Pull-up resistors status This value can be:
  • RTC_TAMPER_PULLUP_ENABLE
  • RTC_TAMPER_PULLUP_DISABLE

Definition at line 1168 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT ( __HANDLE__ ) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))

Get the number of consecutive samples at the specified level needed to activate a Tamper event.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
Number of consecutive samples This value can be:
  • RTC_TAMPERFILTER_DISABLE
  • RTC_TAMPERFILTER_2SAMPLE
  • RTC_TAMPERFILTER_4SAMPLE
  • RTC_TAMPERFILTER_8SAMPLE

Definition at line 1136 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ ( __HANDLE__ ) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))

Get the frequency at which each of the Tamper inputs are sampled.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
Sampling frequency This value can be:
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256

Definition at line 1118 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None

Definition at line 1724 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1633 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1677 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1613 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1689 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
                                                                       } while(0)

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1704 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1623 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1671 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1603 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1683 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
                                                                      } while(0)

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1695 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper_IT(), and HAL_RTCEx_SetTamper_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 1748 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status

Definition at line 1714 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))

Disable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1365 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))

Enable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1358 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))

Disable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1331 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))

Enable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1319 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_GET_STATUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)

Get activation status of the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
Activation status of TimeStamp on Tamper detection This value can be:
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE

Definition at line 1346 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR |= __FLAG__)

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 1262 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1190 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 1210 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1183 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 1200 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
Flag status

Definition at line 1246 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 1221 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 1234 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR |= __FLAG__)

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 917 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 837 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 857 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 830 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 847 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag.

Return values:
None

Definition at line 1555 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1453 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1507 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1433 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1519 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
                                                                  } while(0)

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None

Definition at line 1535 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1443 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1501 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1424 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1513 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
                                                                 } while(0)

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1525 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 1576 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 1545 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG ( ) (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated D3 Exti line flag.

Return values:
None.

Definition at line 1570 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT ( ) (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated D3 Exti line.

Return values:
None

Definition at line 1468 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT ( ) (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated D3 Exti line.

Return values:
None

Definition at line 1462 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG ( ) (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.

Return values:
Line Status

Definition at line 1564 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag sources to check. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
Flag status

Definition at line 893 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. This parameter can be:
  • RTC_FLAG_WUTF WakeUpTimer interrupt flag
Return values:
None

Definition at line 868 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 882 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended RTC TimeStamp functions

Functions
Extended RTC TimeStamp functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 357 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 289 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_IT_TS, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc | RTC handle
sTimeStamp | Pointer to Time structure
sTimeStampDate | Pointer to Date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 392 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_ITSF, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1778 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 327 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 175 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 234 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_IT_TS, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1311 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_InternalTamper1EventCallback(), HAL_RTCEx_InternalTamper2EventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_InternalTamper8EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper2EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::InternalTamper8EventCallback, RTC_INT_TAMPER_1, RTC_INT_TAMPER_2, RTC_INT_TAMPER_3, RTC_INT_TAMPER_4, RTC_INT_TAMPER_5, RTC_INT_TAMPER_6, RTC_INT_TAMPER_8, __RTC_HandleTypeDef::State, TAMP_OFFSET, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, and __RTC_HandleTypeDef::TimeStampEventCallback.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1587 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended RTC Tamper functions

Functions
Extended RTC Tamper functions
RTCEx Exported Functions

Extended RTC Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveTampers (RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper)
Set all active Tampers at the same time.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveSeed (RTC_HandleTypeDef *hrtc, uint32_t *pSeed)
Write a new seed.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateActiveTampers (RTC_HandleTypeDef *hrtc)
Deactivate all Active Tampers at the same time.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper1EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 1 callback.
__weak void | HAL_RTCEx_InternalTamper2EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 2 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
__weak void | HAL_RTCEx_InternalTamper8EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 8 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.

Detailed Description

Extended RTC Tamper functions.

 ==============================================================================
                        ##### Tamper functions #####
 ==============================================================================
 [..]
  (+) Before calling any tamper or internal tamper function, you have to call first
      HAL_RTC_Init() function.
  (+) In that ine you can select to output tamper event on RTC pin.
 [..]
  (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
      or Level according to the Tamper filter (if equal to 0 Edge else Level)
      value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
      Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
      You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
  (+) The default configuration of the Tamper erases the backup registers. To avoid
      erase, enable the NoErase field on the TAMP_TAMPCR register.
 [..]
  (+) Enable Internal Tamper and configure it with interrupt, timestamp using
      the HAL_RTCEx_SetInternalTamper() function.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers ( RTC_HandleTypeDef * hrtc )

Deactivate all Active Tampers at the same time.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1266 of file stm32h7xx_hal_rtc_ex.c.

References TAMP_ALL.

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper
 | ) |  |

Deactivate Internal Tamper.

Parameters:
hrtc | RTC handle
IntTamper | Selected internal tamper event. This parameter can be any combination of existing internal tampers.
Return values:
HAL status

Definition at line 1093 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, and IS_RTC_INTERNAL_TAMPER.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc RTC handle
Tamper Selected tamper pin. This parameter can be a combination of the following values:
  • RTC_TAMPER_1
  • RTC_TAMPER_2
Return values:
HAL status

Definition at line 953 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, and TAMP_OFFSET.

void HAL_RTCEx_InternalTamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1663 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1678 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1693 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper4EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 4 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1708 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper5EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 5 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1723 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper6EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 6 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1738 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_InternalTamper8EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 8 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1753 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper,
 |  | uint32_t | Timeout
 | ) |  |

Internal Tamper event polling.

Parameters:
hrtc | RTC handle
IntTamper | selected tamper. This parameter can be any combination of existing internal tampers.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1932 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, HAL_GetTick(), and IS_RTC_INTERNAL_TAMPER.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper1 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1828 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper2 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1862 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper3 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1896 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t * | pSeed
 | ) |  |

Write a new seed.

Active tamper must be enabled.

Parameters:
hrtc | RTC handle
pSeed | Pointer to active tamper seed values.
Return values:
HAL status

Definition at line 1230 of file stm32h7xx_hal_rtc_ex.c.

References HAL_GetTick(), HAL_RTC_STATE_TIMEOUT, RTC_ATAMP_SEED_NB_UINT32, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_ActiveTampersTypeDef * | sAllTamper
 | ) |  |

Set all active Tampers at the same time.

Parameters:
hrtc | RTC handle
sAllTamper | Pointer to active Tamper Structure.
Return values:
HAL status

Definition at line 1118 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_ActiveTampersTypeDef::ActiveAsyncPrescaler, RTC_ActiveTampersTypeDef::ActiveFilter, RTC_ActiveTampersTypeDef::ActiveOutputChangePeriod, assert_param, RTC_ATampInputTypeDef::Enable, HAL_GetTick(), HAL_RTC_STATE_TIMEOUT, RTC_ATampInputTypeDef::Interrupt, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, RTC_ATampInputTypeDef::MaskFlag, RTC_ATampInputTypeDef::NoErase, RTC_ATampInputTypeDef::Output, RTC_ATAMP_DISABLE, RTC_ATAMP_INTERRUPT_DISABLE, RTC_ATAMP_SEED_NB_UINT32, RTC_TAMP_NB, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TIMEOUT_VALUE, RTC_ActiveTampersTypeDef::Seed, __RTC_HandleTypeDef::State, RTC_ActiveTampersTypeDef::TampInput, and RTC_ActiveTampersTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1034 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper in interrupt mode.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1060 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 476 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_FILTER_CONFIG_CORRECT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_FALLINGEDGE, RTC_TAMPERTRIGGER_HIGHLEVEL, RTC_TamperTypeDef::SamplingFrequency, TAMP_OFFSET, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper with interrupt.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 703 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_FILTER_CONFIG_CORRECT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_FALLINGEDGE, RTC_TAMPERTRIGGER_HIGHLEVEL, RTC_TamperTypeDef::SamplingFrequency, TAMP_OFFSET, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1613 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1630 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1647 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended RTC Wake-up functions

Functions
Extended RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2198 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
Counter value

Definition at line 2255 of file stm32h7xx_hal_rtc_ex.c.

References __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2341 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 1983 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 2085 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 2324 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 2266 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, CM7_CPUID, HAL_GetCurrentCPUID(), HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::Instance, RTC_FLAG_WUTF, __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended RTC Backup register functions

Functions
Extended RTC Backup register functions
RTCEx Exported Functions

Extended RTC Backup register functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.

Detailed Description

Extended RTC Backup register functions.

 ===============================================================================
             ##### Extended RTC Backup register functions #####
 ===============================================================================
  [..]
   (+) Before calling any tamper or internal tamper function, you have to call first
       HAL_RTC_Init() function.
   (+) In that ine you can select to output tamper event on RTC pin.
  [..]
   This subsection provides functions allowing to
   (+) Write a data in a specified RTC Backup data register
   (+) Read a data in a specified RTC Backup data register

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Read data from the specified RTC Backup data Register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to specify the register.
Return values:
Read value

Definition at line 2430 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_BKP, and TAMP_OFFSET.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to specify the register.
Data | Data to be written in the specified Backup data register.
Return values:
None

Definition at line 2400 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_BKP, and TAMP_OFFSET.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterIncrement (RTC_HandleTypeDef *hrtc)
Increment Monotonic counter.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterGet (RTC_HandleTypeDef *hrtc, uint32_t *Counter)
Monotonic counter incrementation.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Smooth calibration parameters.
      (+) Set Low Power calibration parameter (if feature supported).
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2716 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2799 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2887 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2855 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t * | Counter
 | ) |  |

Monotonic counter incrementation.

Parameters:
hrtc | RTC handle
Counter | monotonic counter value
Return values:
HAL status

Definition at line 2934 of file stm32h7xx_hal_rtc_ex.c.

HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement ( RTC_HandleTypeDef * hrtc )

Increment Monotonic counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2918 of file stm32h7xx_hal_rtc_ex.c.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
CalibOutput Select the Calibration output Selection. This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 2678 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 2745 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Parameters:
hrtc | RTC handle
SmoothCalibPeriod Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue | Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 2502 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc | RTC handle
ShiftAdd1S Select to add or not 1 second to the time calendar. This parameter can be one of the following values:
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS | Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 2580 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 2969 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2985 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and __RTC_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR1_IM18
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19
#define | RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))
#define | RTC_TAMPER_X_INTERRUPT ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3))

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR1_IM18

External interrupt line 18 Connected to the RTC Tamper and Time Stamp events

Definition at line 1920 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC Wakeup event

Definition at line 1921 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))

Definition at line 1924 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_X_INTERRUPT ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3))

Definition at line 1925 of file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx Private Macros

Defines
RTCEx Private Macros
RTCEx

Defines

#define | IS_RTC_BKP(__BKP__) ((__BKP__) < BKP_REG_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__)
#define | IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)

Define Documentation

#define IS_RTC_BKP ( __BKP__ ) ((__BKP__) < BKP_REG_NUMBER)

Definition at line 1940 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1986 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_INTERNAL_TAMPER ( __INT_TAMPER__ )
Value:
((((__INT_TAMPER__) &  RTC_INT_TAMPER_ALL) != 0x00U) && \
                                                  (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))

Definition at line 2055 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1981 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= RTC_SHIFTR_SUBFS)

Definition at line 1984 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= RTC_CALR_CALM)

Definition at line 1975 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1968 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1972 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ )
Value:
((((__TAMPER__) &  RTC_TAMPER_X) != 0x00U) &&  \
                                    (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U))

Definition at line 1993 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( __MODE__ )
Value:
(((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 2011 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( __FILTER__ )
Value:
(((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
                                           ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
                                           ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
                                           ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 2017 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT | ( | FILTER,
 |  | TRIGGER
 | ) |
Value:
(  (  ((FILTER) != RTC_TAMPERFILTER_DISABLE)          \
                     && (  ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL)    \
                        || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
                  || (  ((FILTER) == RTC_TAMPERFILTER_DISABLE)          \
                     && (  ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE)  \
                        || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))

Definition at line 2047 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_INTERRUPT ( __INTERRUPT__ )
Value:
((((__INTERRUPT__) &   RTC_TAMPER_X_INTERRUPT ) != 0x00U) &&  \
               (((__INTERRUPT__) & (~RTC_TAMPER_X_INTERRUPT)) == 0x00U))

Definition at line 2001 of file stm32h7xx_hal_rtc_ex.h.

#define IS_RTC_TAMPER_MASKFLAG_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                        ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 2014 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 2031 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
                                               ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 2036 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( __FREQ__ )
Value:
(((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 2022 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT ( __MODE__ )
Value:
(((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
                                                       ((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))

Definition at line 2043 of file stm32h7xx_hal_rtc_ex.h.

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( __DETECTION__ )
Value:
(((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                                  ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 2039 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( __TRIGGER__ )
Value:
(((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \
                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \
                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)      || \
                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 2006 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1949 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1955 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= RTC_WUTR_WUT)

Definition at line 1962 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1946 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 234 of file stm32h7xx_hal_sai.c.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_FIFO_SIZE 8U
#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U

Define Documentation

#define SAI_DEFAULT_TIMEOUT 4U

Definition at line 248 of file stm32h7xx_hal_sai.c.

Referenced by SAI_Disable().

#define SAI_FIFO_SIZE 8U

Definition at line 247 of file stm32h7xx_hal_sai.c.

#define SAI_LONG_TIMEOUT 1000U

Definition at line 249 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Transmit_DMA().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Private Functions

Functions
SAI Private Functions
SAI

Private functions. More...

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.

Detailed Description

Private functions.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

Disable the SAI and wait for the disabling.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2507 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_DEFAULT_TIMEOUT.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Transmit(), SAI_DMAAbort(), and SAI_DMAError().

static void SAI_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI Abort callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2873 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_IRQHandler().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2835 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_FE, HAL_DMA_GetError(), HAL_SAI_ERROR_DMA, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2790 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __SAI_HandleTypeDef::RxCpltCallback, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2818 of file stm32h7xx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback(), and __SAI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2744 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2773 of file stm32h7xx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback(), and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2431 of file stm32h7xx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol.
datasize | one of the supported datasize SAI protocol data size.
nbslot | number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 2266 of file stm32h7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol
datasize | one of the supported datasize SAI protocol data size
nbslot | number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 2361 of file stm32h7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | const SAI_HandleTypeDef * | hsai,
 |  | SAI_ModeTypedef | mode
 | ) |  | [static]

Return the interrupt flag to set according the SAI setup.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode | SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 2474 of file stm32h7xx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2668 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2704 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2637 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2567 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2600 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2538 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
             ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config
        (++) PDM Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI peripheral.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 757 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::MspDeInitCallback, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initialize the SAI according to the specified parameters.

in the SAI_InitTypeDef structure and initialize the associated handle.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 371 of file stm32h7xx_hal_sai.c.

References SAI_PdmInitTypeDef::Activation, SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_PdmInitTypeDef::ClockEnable, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_GetREVID(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_SAI_ERROR_NONE, HAL_SAI_ErrorCallback(), HAL_SAI_MspInit(), HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MCK_OUTPUT, IS_SAI_BLOCK_MCK_OVERSAMPLING, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_PDM_CLOCK_ENABLE, IS_SAI_PDM_MIC_PAIRS_NUMBER, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MckOutput, SAI_InitTypeDef::MckOverSampling, SAI_PdmInitTypeDef::MicPairsNbr, SAI_InitTypeDef::MonoStereoMode, __SAI_HandleTypeDef::MspInitCallback, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::PdmInit, SAI_InitTypeDef::Protocol, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2A, RCC_PERIPHCLK_SAI2B, REV_ID_B, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_FREE_PROTOCOL, SAI_MASTERDIVIDER_DISABLE, SAI_MCK_OVERSAMPLING_ENABLE, SAI_MODEMASTER_RX, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE, SAI_SYNCHRONOUS, SAI_SYNCHRONOUS_EXT_SAI1, SAI_SYNCHRONOUS_EXT_SAI2, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, SAI_InitTypeDef::TriState, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol SAI Supported protocol
datasize | one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot | Number of slot.
Return values:
HAL status

Definition at line 332 of file stm32h7xx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 854 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_DeInit(), and HAL_SAI_UnRegisterCallback().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

Initialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 838 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), and HAL_SAI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SAI_RegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID,
 |  | pSAI_CallbackTypeDef | pCallback
 | ) |  |

Register a user SAI callback to be used instead of the weak predefined callback.

Parameters:
hsai | SAI handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 881 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_SAI_UnRegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user SAI callback.

SAI callback is redirected to the weak predefined callback.

Parameters:
hsai SAI handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 973 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_ErrorCallback(), HAL_SAI_MspDeInit(), HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MspInit(), HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
      (++) Blocking mode : The communication is performed in the polling mode.
           The status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode : The communication is performed using Interrupts
           or DMA. These functions return the status of the transfer startup.
           The end of the data processing will be indicated through the
           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.

    (+) Blocking mode functions are :
      (++) HAL_SAI_Transmit()
      (++) HAL_SAI_Receive()

    (+) Non Blocking mode functions with Interrupt are :
      (++) HAL_SAI_Transmit_IT()
      (++) HAL_SAI_Receive_IT()

    (+) Non Blocking mode functions with DMA are :
      (++) HAL_SAI_Transmit_DMA()
      (++) HAL_SAI_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
      (++) HAL_SAI_TxCpltCallback()
      (++) HAL_SAI_RxCpltCallback()
      (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disable the SAI.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1547 of file stm32h7xx_hal_sai.c.

References __DMA_HandleTypeDef::ErrorCode, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_NO_XFER, HAL_SAI_ERROR_DMA, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Rx mute detection.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1835 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Tx mute mode.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1794 of file stm32h7xx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pause the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1438 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resume the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1458 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stop the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1485 of file stm32h7xx_hal_sai.c.

References __DMA_HandleTypeDef::ErrorCode, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_NO_XFER, HAL_SAI_ERROR_DMA, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the Rx mute detection.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback | function called when the mute is detected.
counter | number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1812 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the Tx mute mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val | value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1775 of file stm32h7xx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2191 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

Handle SAI interrupt request.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1854 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_DMA, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_DMAAbort(), SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __SAI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1208 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1706 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2159 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2175 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1095 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1619 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_FIFOSTATUS_EMPTY, SAI_InterruptFlag(), SAI_LONG_TIMEOUT, SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1318 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2127 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2143 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

  ===============================================================================
                ##### Peripheral State and Errors functions #####
  ===============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 2237 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( SAI_HandleTypeDef * hsai )

Return the SAI handle state.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 2226 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI_PdmInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_PdmInitTypeDef Struct Reference
SAI PDM Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

FunctionalState | Activation
uint32_t | MicPairsNbr
uint32_t | ClockEnable

Detailed Description

Definition at line 65 of file stm32h7xx_hal_sai.h.

Field Documentation

FunctionalState SAI_PdmInitTypeDef::Activation

Enable/disable PDM interface

Definition at line 67 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::ClockEnable

Specifies which clock must be enabled. This parameter can be a values combination of SAI PDM Clock Enable

Definition at line 70 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::MicPairsNbr

Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 68 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Init Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | MckOutput
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MckOverSampling
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
SAI_PdmInitTypeDef PdmInit
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

Definition at line 81 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 115 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 83 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 148 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 128 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 142 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 112 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 145 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice This parameter must be a number between Min_Data = 0 and Max_Data = 63.

Definition at line 118 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOutput

Specifies whether master clock output will be generated or not. This parameter can be a value of SAI Block Master Clock Output

Note:
This feature is only available on STM32H7xx Rev.B and above

Definition at line 95 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOverSampling

Specifies the master clock oversampling. This parameter can be a value of SAI Block Master Clock OverSampling

Definition at line 122 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 125 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values from 8 to 256.
The NODIV bit is the same as NOMCK bit in STM32H7xx rev.Y

Definition at line 104 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
This value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 99 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAI_PdmInitTypeDef SAI_InitTypeDef::PdmInit

Specifies the PDM configuration.

Definition at line 134 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 139 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 86 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of SAI External synchronisation

Note:
If both audio blocks of same SAI are used, this parameter has to be set to the same value for each audio block

Definition at line 89 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 131 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Frame Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

Definition at line 159 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 168 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 162 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 173 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 179 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 176 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Slot Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

Definition at line 191 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 193 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 202 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 199 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 196 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Handle Structure definition

Data Structures | Typedefs
SAI Handle Structure definition
SAI Exported Types

SAI handle Structure definition. More...

Data Structures

struct | __SAI_HandleTypeDef

Typedefs

typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Detailed Description

SAI handle Structure definition.

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Handle Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | RxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | RxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | ErrorCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspInitCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspDeInitCallback )(struct __SAI_HandleTypeDef *hsai)

Detailed Description

Definition at line 213 of file stm32h7xx_hal_sai.h.

Field Documentation

void(* __SAI_HandleTypeDef::ErrorCallback)(struct __SAI_HandleTypeDef *hsai)

SAI error callback

Definition at line 248 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 241 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), SAI_Disable(), SAI_DMAAbort(), and SAI_DMAError().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 219 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 231 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Receive_DMA().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 229 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Transmit_DMA().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 217 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_InitCard(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 215 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_Disable(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 235 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 237 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

void(* __SAI_HandleTypeDef::MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP de-init callback

Definition at line 250 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

void(* __SAI_HandleTypeDef::MspInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP init callback

Definition at line 249 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 233 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 223 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::RxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive complete callback

Definition at line 244 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void(* __SAI_HandleTypeDef::RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive half complete callback

Definition at line 245 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 221 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 239 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit complete callback

Definition at line 246 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit half complete callback

Definition at line 247 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 227 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 225 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Exported Types

Modules | Typedefs | Enumerations
SAI Exported Types
SAI

Modules

SAI PDM Structure definition

SAI PDM Init structure definition.

SAI Init Structure definition

SAI Init Structure definition.

SAI Frame Structure definition

SAI Frame Init structure definition.

SAI Slot Structure definition

SAI Block Slot Init Structure definition.

SAI Handle Structure definition

SAI handle Structure definition.

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai)

SAI callback pointer definition.

Definition at line 275 of file stm32h7xx_hal_sai.h.

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 59 of file stm32h7xx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_CallbackIDTypeDef

SAI callback ID enumeration definition.

Enumerator:
HAL_SAI_RX_COMPLETE_CB_ID

SAI receive complete callback ID

HAL_SAI_RX_HALFCOMPLETE_CB_ID

SAI receive half complete callback ID

HAL_SAI_TX_COMPLETE_CB_ID

SAI transmit complete callback ID

HAL_SAI_TX_HALFCOMPLETE_CB_ID

SAI transmit half complete callback ID

HAL_SAI_ERROR_CB_ID

SAI error callback ID

HAL_SAI_MSPINIT_CB_ID

SAI MSP init callback ID

HAL_SAI_MSPDEINIT_CB_ID

SAI MSP de-init callback ID

Definition at line 261 of file stm32h7xx_hal_sai.h.

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

Definition at line 47 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Define Documentation

#define HAL_SAI_ERROR_AFSDET 0x00000004U

Anticipated Frame synchronisation detection

Definition at line 293 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY 0x00000010U

codec not ready

Definition at line 295 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_DMA 0x00000080U

DMA error

Definition at line 298 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and SAI_DMAError().

#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Invalid callback error

Definition at line 300 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

#define HAL_SAI_ERROR_LFSDET 0x00000008U

Late Frame synchronisation detection

Definition at line 294 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE 0x00000000U

No error

Definition at line 290 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR 0x00000001U

Overrun Error

Definition at line 291 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT 0x00000040U

Timeout error

Definition at line 297 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR 0x00000002U

Underrun error

Definition at line 292 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG 0x00000020U

Wrong clock configuration

Definition at line 296 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAAbort().

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STM32H7B3xQ HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define | SAI_SYNCEXT_DISABLE 0U
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U

Define Documentation

#define SAI_SYNCEXT_DISABLE 0U

Definition at line 309 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U

Definition at line 310 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U

Definition at line 311 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

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STM32H7B3xQ HAL User Manual: SAI Block Master Clock Output

Defines
SAI Block Master Clock Output
SAI Exported Constants

Defines

#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Define Documentation

#define SAI_MCK_OUTPUT_DISABLE 0x00000000U

Definition at line 319 of file stm32h7xx_hal_sai.h.

#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Definition at line 320 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U

Define Documentation

#define SAI_I2S_LSBJUSTIFIED 2U

Definition at line 330 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED 1U

Definition at line 329 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_I2S_STANDARD 0U

Definition at line 328 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG 3U

Definition at line 331 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_PCM_SHORT 4U

Definition at line 332 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

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STM32H7B3xQ HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT 0U

Definition at line 340 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U

Definition at line 341 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT 2U

Definition at line 342 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT 3U

Definition at line 343 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K 11025U

Definition at line 358 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K 16000U

Definition at line 357 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K 192000U

Definition at line 351 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K 22050U

Definition at line 356 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K 32000U

Definition at line 355 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K 44100U

Definition at line 354 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K 48000U

Definition at line 353 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K 8000U

Definition at line 359 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K 96000U

Definition at line 352 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV 0U

Definition at line 360 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

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STM32H7B3xQ HAL User Manual: SAI Block Master Clock OverSampling

Defines
SAI Block Master Clock OverSampling
SAI Exported Constants

Defines

#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Define Documentation

#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U

Definition at line 368 of file stm32h7xx_hal_sai.h.

#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Definition at line 369 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI PDM Clock Enable

Defines
SAI PDM Clock Enable
SAI Exported Constants

Defines

#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Define Documentation

#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1

Definition at line 377 of file stm32h7xx_hal_sai.h.

#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Definition at line 378 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Define Documentation

#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0

Definition at line 387 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_MODEMASTER_TX 0x00000000U

Definition at line 386 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Definition at line 389 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1

Definition at line 388 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

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STM32H7B3xQ HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Define Documentation

#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Definition at line 400 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL 0x00000000U

Definition at line 398 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0

Definition at line 399 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Define Documentation

#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 409 of file stm32h7xx_hal_sai.h.

#define SAI_DATASIZE_16 SAI_xCR1_DS_2

Definition at line 410 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)

Definition at line 411 of file stm32h7xx_hal_sai.h.

#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)

Definition at line 412 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 413 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 SAI_xCR1_DS_1

Definition at line 408 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Define Documentation

#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Definition at line 422 of file stm32h7xx_hal_sai.h.

#define SAI_FIRSTBIT_MSB 0x00000000U

Definition at line 421 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE 0U

Definition at line 430 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE 1U

Definition at line 431 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U
#define | SAI_SYNCHRONOUS_EXT_SAI1 2U
#define | SAI_SYNCHRONOUS_EXT_SAI2 3U

Define Documentation

#define SAI_ASYNCHRONOUS 0U

Asynchronous

Definition at line 439 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS 1U

Synchronous with other block of same SAI

Definition at line 440 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI1 2U

Synchronous with other SAI, SAI1

Definition at line 441 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI2 3U

Synchronous with other SAI, SAI2

Definition at line 443 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

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STM32H7B3xQ HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U

Definition at line 458 of file stm32h7xx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Definition at line 459 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Definition at line 468 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_MASTERDIVIDER_ENABLE 0x00000000U

Definition at line 467 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Definition at line 477 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME 0x00000000U

Definition at line 476 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitPCM().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Define Documentation

#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Definition at line 486 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW 0x00000000U

Definition at line 485 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32H7B3xQ HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Definition at line 495 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT 0x00000000U

Definition at line 494 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32H7B3xQ HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Define Documentation

#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0

Definition at line 504 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Definition at line 505 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE 0x00000000U

Definition at line 503 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU

Define Documentation

#define SAI_SLOT_NOTACTIVE 0x00000000U

Definition at line 513 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_0 0x00000001U

Definition at line 514 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_1 0x00000002U

Definition at line 515 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_10 0x00000400U

Definition at line 524 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_11 0x00000800U

Definition at line 525 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_12 0x00001000U

Definition at line 526 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_13 0x00002000U

Definition at line 527 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_14 0x00004000U

Definition at line 528 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_15 0x00008000U

Definition at line 529 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_2 0x00000004U

Definition at line 516 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_3 0x00000008U

Definition at line 517 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_4 0x00000010U

Definition at line 518 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_5 0x00000020U

Definition at line 519 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_6 0x00000040U

Definition at line 520 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_7 0x00000080U

Definition at line 521 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_8 0x00000100U

Definition at line 522 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_9 0x00000200U

Definition at line 523 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL 0x0000FFFFU

Definition at line 530 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

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STM32H7B3xQ HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO

Define Documentation

#define SAI_MONOMODE SAI_xCR1_MONO

Definition at line 539 of file stm32h7xx_hal_sai.h.

#define SAI_STEREOMODE 0x00000000U

Definition at line 538 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Define Documentation

#define SAI_OUTPUT_NOTRELEASED 0x00000000U

Definition at line 547 of file stm32h7xx_hal_sai.h.

#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Definition at line 548 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0

Definition at line 557 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)

Definition at line 559 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U

Definition at line 556 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Definition at line 560 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1

Definition at line 558 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)

Definition at line 570 of file stm32h7xx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Definition at line 572 of file stm32h7xx_hal_sai.h.

#define SAI_NOCOMPANDING 0x00000000U

Definition at line 568 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1

Definition at line 569 of file stm32h7xx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)

Definition at line 571 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Define Documentation

#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Definition at line 581 of file stm32h7xx_hal_sai.h.

#define SAI_ZERO_VALUE 0x00000000U

Definition at line 580 of file stm32h7xx_hal_sai.h.

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STM32H7B3xQ HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Define Documentation

#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE

Definition at line 594 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE

Definition at line 593 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ SAI_xIMR_FREQIE

Definition at line 592 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Definition at line 595 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE

Definition at line 590 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE

Definition at line 589 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE

Definition at line 591 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET

Define Documentation

#define SAI_FLAG_AFSDET SAI_xSR_AFSDET

Definition at line 608 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY SAI_xSR_CNRDY

Definition at line 607 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ SAI_xSR_FREQ

Definition at line 606 of file stm32h7xx_hal_sai.h.

#define SAI_FLAG_LFSDET SAI_xSR_LFSDET

Definition at line 609 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET

Definition at line 604 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR

Definition at line 603 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG

Definition at line 605 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

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STM32H7B3xQ HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U

Definition at line 619 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U

Definition at line 621 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY 0x00000000U

Definition at line 617 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), and HAL_SAI_Transmit_DMA().

#define SAI_FIFOSTATUS_FULL 0x00050000U

Definition at line 622 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL 0x00030000U

Definition at line 620 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U

Definition at line 618 of file stm32h7xx_hal_sai.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the specified SAI pending flag.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 725 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Disable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 737 of file stm32h7xx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Disable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 679 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Enable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 731 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 664 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 709 of file stm32h7xx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SAI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 694 of file stm32h7xx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
                                                     (__HANDLE__)->MspInitCallback = NULL;      \
                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
                                                   } while(0U)

Reset SAI handle state.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 642 of file stm32h7xx_hal_sai.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI_Private_Macros

Defines
SAI_Private_Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 845 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Definition at line 954 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 878 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 913 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 868 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 919 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 875 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24U)

Definition at line 939 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))

Definition at line 952 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 947 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 941 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 944 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 63U)

Definition at line 950 of file stm32h7xx_hal_sai.h.

#define IS_SAI_BLOCK_MCK_OUTPUT ( VALUE )
Value:
(((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
                                        ((VALUE) == SAI_MCK_OUTPUT_DISABLE))

Definition at line 899 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MCK_OVERSAMPLING ( VALUE )
Value:
(((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))

Definition at line 851 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                  ((MODE) == SAI_MODEMASTER_RX) || \
                                  ((MODE) == SAI_MODESLAVE_TX)  || \
                                  ((MODE) == SAI_MODESLAVE_RX))

Definition at line 859 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63U)

Definition at line 908 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 910 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 905 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 902 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 864 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))

Definition at line 933 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 935 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE )
Value:
(((STATE) == SAI_SYNCEXT_DISABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

Definition at line 830 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

Definition at line 888 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 925 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 928 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_CLOCK_ENABLE ( CLOCK )
Value:
(((CLOCK) != 0U) && \
                                       (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))

Definition at line 856 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_MIC_PAIRS_NUMBER ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 3U))

Definition at line 854 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and HAL_SAIEx_ConfigPdmMicDelay().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 840 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 931 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 834 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SAIEx Extended Exported Functions

SAIEx control functions. More...

Functions

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAIEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Modify PDM microphone delays

Function Documentation

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIEx_PdmMicDelayParamTypeDef * | pdmMicDelay
 | ) |  |

Configure PDM microphone delays.

Parameters:
hsai | SAI handle.
pdmMicDelay | Microphone delays configuration.
Return values:
HAL status

Definition at line 71 of file stm32h7xx_hal_sai_ex.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_PDM_MIC_DELAY, IS_SAI_PDM_MIC_PAIRS_NUMBER, SAIEx_PdmMicDelayParamTypeDef::LeftDelay, SAIEx_PdmMicDelayParamTypeDef::MicPair, SAIEx_PdmMicDelayParamTypeDef::RightDelay, SAI_PDM_DELAY_MASK, SAI_PDM_DELAY_OFFSET, SAI_PDM_RIGHT_DELAY_OFFSET, and __SAI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAIEx_PdmMicDelayParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAIEx_PdmMicDelayParamTypeDef Struct Reference
SAIEx Exported Types

PDM microphone delay structure definition. More...

#include <stm32h7xx_hal_sai_ex.h>

Data Fields

uint32_t | MicPair
uint32_t | LeftDelay
uint32_t | RightDelay

Detailed Description

PDM microphone delay structure definition.

Definition at line 47 of file stm32h7xx_hal_sai_ex.h.

Field Documentation

uint32_t SAIEx_PdmMicDelayParamTypeDef::LeftDelay

Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 52 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::MicPair

Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 49 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::RightDelay

Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 55 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai_ex.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAIEx Extended Private Macros

Defines
SAIEx Extended Private Macros
SAIEx

Defines

#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Define Documentation

#define IS_SAI_PDM_MIC_DELAY ( VALUE ) ((VALUE) <= 7U)

Definition at line 86 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAIEx

Modules | Defines
SAIEx
STM32H7xx_HAL_Driver

SAI Extended HAL module driver. More...

Modules

SAIEx Extended Exported Functions
SAIEx Exported Types
SAIEx Extended Private Macros

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Detailed Description

SAI Extended HAL module driver.

Define Documentation

#define SAI_PDM_DELAY_MASK 0x77U

Definition at line 40 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_DELAY_OFFSET 8U

Definition at line 41 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_RIGHT_DELAY_OFFSET 4U

Definition at line 42 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Private Functions

Functions
SD Private Functions
SD | SD Exported Functions

Functions

static uint32_t | SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the sd card.
static uint32_t | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static uint32_t | SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Send Status info command.
static uint32_t | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static uint32_t | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static uint32_t | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static uint32_t | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static void | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static void | SD_Write_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static void | SD_Read_IT (SD_HandleTypeDef *hsd)
Wrap up reading in non-blocking mode.
static uint32_t | SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
static uint32_t | SD_UltraHighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to Ultra High Speed mode.
static uint32_t | SD_DDR_Mode (SD_HandleTypeDef *hsd)
Switches the SD card to Double Data Rate (DDR) mode.
__weak void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Function Documentation

__weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3910 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

__weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3925 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

__weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3940 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

__weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3955 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

static uint32_t SD_DDR_Mode ( SD_HandleTypeDef * hsd ) [static]

Switches the SD card to Double Data Rate (DDR) mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock less than 50MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 3781 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, CARD_NORMAL_SPEED, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, DelayBlock_Enable(), __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_GENERAL_UNKNOWN_ERR, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, SD_GET_DLYB_INSTANCE, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

Referenced by HAL_SD_ConfigSpeedBusOperation().

static uint32_t SD_FindSCR | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSCR
 | ) |  | [static]

Finds the SD card SCR register value.

Parameters:
hsd,: Pointer to SD handle
pSCR,: pointer to the buffer that will contain the SCR value
Return values:
error state

Definition at line 3370 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, HAL_GetTick(), HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

Referenced by SD_WideBus_Disable(), and SD_WideBus_Enable().

uint32_t SD_HighSpeed ( SD_HandleTypeDef * hsd ) [static]

Switches the SD card to High Speed mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock between 50 and 120 MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 3535 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, CARD_HIGH_SPEED, CARD_NORMAL_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_GENERAL_UNKNOWN_ERR, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

Referenced by HAL_SD_ConfigSpeedBusOperation().

static uint32_t SD_InitCard ( SD_HandleTypeDef * hsd ) [static]

Initializes the sd card.

Parameters:
hsd,: Pointer to SD handle
Return values:
SD Card error state

Definition at line 2873 of file stm32h7xx_hal_sd.c.

References CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::CID, HAL_SD_CardInfoTypeDef::Class, __SD_HandleTypeDef::CSD, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_GetCardCSD(), __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_InitCard().

static void SD_PowerOFF ( SD_HandleTypeDef * hsd ) [static]

Turns the SDMMC output signals off.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 3128 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::Instance.

Referenced by HAL_SD_DeInit().

static uint32_t SD_PowerON ( SD_HandleTypeDef * hsd ) [static]

Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.

Parameters:
hsd,: Pointer to SD handle
Return values:
error state

Definition at line 2962 of file stm32h7xx_hal_sd.c.

References CARD_SDHC_SDXC, CARD_ULTRA_HIGH_SPEED, CARD_V1_X, CARD_V2_X, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, HAL_GetTick(), HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_INVALID_VOLTRANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_TIMEOUT, HAL_SD_ERROR_UNSUPPORTED_FEATURE, __SD_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_InitCard().

static void SD_Read_IT ( SD_HandleTypeDef * hsd ) [static]

Wrap up reading in non-blocking mode.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
None

Definition at line 3465 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::pRxBuffPtr, and __SD_HandleTypeDef::RxXferSize.

Referenced by HAL_SD_IRQHandler().

static uint32_t SD_SendSDStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSDstatus
 | ) |  | [static]

Send Status info command.

Parameters:
hsd,: pointer to SD handle
pSDstatus,: Pointer to the buffer that will contain the SD card status SD Status register)
Return values:
error state

Definition at line 3141 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_GetCardStatus().

static uint32_t SD_SendStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hsd,: Pointer to SD handle
pCardStatus,: pointer to the buffer that will contain the SD card status (Card Status register)
Return values:
error state

Definition at line 3247 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_GetCardState().

static uint32_t SD_UltraHighSpeed ( SD_HandleTypeDef * hsd ) [static]

Switches the SD card to Ultra High Speed mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock between 50 and 120 MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 3651 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, CARD_NORMAL_SPEED, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, DelayBlock_Enable(), __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_GENERAL_UNKNOWN_ERR, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, SD_GET_DLYB_INSTANCE, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

Referenced by HAL_SD_ConfigSpeedBusOperation().

static uint32_t SD_WideBus_Disable ( SD_HandleTypeDef * hsd ) [static]

Disables the SDMMC wide bus mode.

Parameters:
hsd,: Pointer to SD handle
Return values:
error state

Definition at line 3321 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, SD_FindSCR(), and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_ConfigWideBusOperation().

static uint32_t SD_WideBus_Enable ( SD_HandleTypeDef * hsd ) [static]

Enables the SDMMC wide bus mode.

Parameters:
hsd,: pointer to SD handle
Return values:
error state

Definition at line 3274 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, SD_FindSCR(), and __SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_ConfigWideBusOperation().

static void SD_Write_IT ( SD_HandleTypeDef * hsd ) [static]

Wrap up writing in non-blocking mode.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
None

Definition at line 3499 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::pTxBuffPtr, and __SD_HandleTypeDef::TxXferSize.

Referenced by HAL_SD_IRQHandler().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD State enumeration structure

Enumerations
SD State enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_StateTypeDef {
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), HAL_SD_STATE_READY = ((uint32_t)0x00000001U), HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU)
}

Enumeration Type Documentation

enum HAL_SD_StateTypeDef
Enumerator:
HAL_SD_STATE_RESET

SD not yet initialized or disabled

HAL_SD_STATE_READY

SD initialized and ready for use

HAL_SD_STATE_TIMEOUT

SD Timeout state

HAL_SD_STATE_BUSY

SD process ongoing

HAL_SD_STATE_PROGRAMMING

SD Programming State

HAL_SD_STATE_RECEIVING

SD Receiving State

HAL_SD_STATE_TRANSFER

SD Transfert State

HAL_SD_STATE_ERROR

SD is in error state

Definition at line 51 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Card State enumeration structure

Defines | Typedefs
SD Card State enumeration structure
SD Exported Types

Defines

#define | HAL_SD_CARD_READY 0x00000001U
#define | HAL_SD_CARD_IDENTIFICATION 0x00000002U
#define | HAL_SD_CARD_STANDBY 0x00000003U
#define | HAL_SD_CARD_TRANSFER 0x00000004U
#define | HAL_SD_CARD_SENDING 0x00000005U
#define | HAL_SD_CARD_RECEIVING 0x00000006U
#define | HAL_SD_CARD_PROGRAMMING 0x00000007U
#define | HAL_SD_CARD_DISCONNECTED 0x00000008U
#define | HAL_SD_CARD_ERROR 0x000000FFU

Typedefs

typedef uint32_t | HAL_SD_CardStateTypeDef

Define Documentation

#define HAL_SD_CARD_DISCONNECTED 0x00000008U

Card is disconnected

Definition at line 78 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_ERROR 0x000000FFU

Card response Error

Definition at line 79 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_IDENTIFICATION 0x00000002U

Card is in identification state

Definition at line 72 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_PROGRAMMING 0x00000007U

Card is in programming state

Definition at line 77 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_READY 0x00000001U

Card state is ready

Definition at line 71 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_RECEIVING 0x00000006U

Card is receiving operation information

Definition at line 76 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), and HAL_SD_Abort_IT().

#define HAL_SD_CARD_SENDING 0x00000005U

Card is sending an operation

Definition at line 75 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), and HAL_SD_Abort_IT().

#define HAL_SD_CARD_STANDBY 0x00000003U

Card is in standby state

Definition at line 73 of file stm32h7xx_hal_sd.h.

#define HAL_SD_CARD_TRANSFER 0x00000004U

Card is in transfer state

Definition at line 74 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), and HAL_SD_Init().

Typedef Documentation

typedef uint32_t HAL_SD_CardStateTypeDef

Definition at line 69 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Handle Structure definition

Data Structures | Defines | Typedefs
SD Handle Structure definition
SD Exported Types

Data Structures

struct | HAL_SD_CardInfoTypeDef
SD Card Information Structure definition. More...
struct | __SD_HandleTypeDef
SD handle Structure definition. More...

Defines

#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef

Typedefs

typedef struct __SD_HandleTypeDef | SD_HandleTypeDef
SD handle Structure definition.

Define Documentation

#define SD_InitTypeDef SDMMC_InitTypeDef

Definition at line 87 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_InitCard().

#define SD_TypeDef SDMMC_TypeDef

Definition at line 88 of file stm32h7xx_hal_sd.h.

Typedef Documentation

typedef struct __SD_HandleTypeDef SD_HandleTypeDef

SD handle Structure definition.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_SD_CardInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardInfoTypeDef Struct Reference
SD Handle Structure definition

SD Card Information Structure definition. More...

#include <stm32h7xx_hal_sd.h>

Data Fields

uint32_t | CardType
uint32_t | CardVersion
uint32_t | Class
uint32_t | RelCardAdd
uint32_t | BlockNbr
uint32_t | BlockSize
uint32_t | LogBlockNbr
uint32_t | LogBlockSize
uint32_t | CardSpeed

Detailed Description

SD Card Information Structure definition.

Definition at line 93 of file stm32h7xx_hal_sd.h.

Field Documentation

uint32_t HAL_SD_CardInfoTypeDef::BlockNbr

Specifies the Card Capacity in blocks

Definition at line 103 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::BlockSize

Specifies one block size in bytes

Definition at line 105 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::CardSpeed

Specifies the card Speed

Definition at line 111 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Init(), SD_DDR_Mode(), SD_HighSpeed(), SD_PowerON(), and SD_UltraHighSpeed().

uint32_t HAL_SD_CardInfoTypeDef::CardType

Specifies the card Type

Definition at line 95 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_InitCard(), and SD_PowerON().

uint32_t HAL_SD_CardInfoTypeDef::CardVersion

Specifies the card version

Definition at line 97 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardInfo(), and SD_PowerON().

uint32_t HAL_SD_CardInfoTypeDef::Class

Specifies the class of the card class

Definition at line 99 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_GetCardInfo(), and SD_InitCard().

uint32_t HAL_SD_CardInfoTypeDef::LogBlockNbr

Specifies the Card logical Capacity in blocks

Definition at line 107 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

uint32_t HAL_SD_CardInfoTypeDef::LogBlockSize

Specifies logical block size in bytes

Definition at line 109 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::RelCardAdd

Specifies the Relative Card Address

Definition at line 101 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardInfo(), SD_FindSCR(), SD_InitCard(), SD_SendSDStatus(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SD_HandleTypeDef Struct Reference
SD Handle Structure definition

SD handle Structure definition. More...

#include <stm32h7xx_hal_sd.h>

Data Fields

SD_TypeDef * Instance
SD_InitTypeDef Init
HAL_LockTypeDef | Lock
uint8_t * | pTxBuffPtr
uint32_t | TxXferSize
uint8_t * | pRxBuffPtr
uint32_t | RxXferSize
__IO uint32_t | Context
__IO HAL_SD_StateTypeDef | State
__IO uint32_t | ErrorCode
HAL_SD_CardInfoTypeDef SdCard
uint32_t | CSD [4]
uint32_t | CID [4]
void(* | TxCpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | RxCpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | ErrorCallback )(struct __SD_HandleTypeDef *hsd)
void(* | AbortCpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | Read_DMADblBuf0CpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | Read_DMADblBuf1CpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | Write_DMADblBuf0CpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | Write_DMADblBuf1CpltCallback )(struct __SD_HandleTypeDef *hsd)
void(* | DriveTransceiver_1_8V_Callback )(FlagStatus status)
void(* | MspInitCallback )(struct __SD_HandleTypeDef *hsd)
void(* | MspDeInitCallback )(struct __SD_HandleTypeDef *hsd)

Detailed Description

SD handle Structure definition.

Definition at line 119 of file stm32h7xx_hal_sd.h.

Field Documentation

void(* __SD_HandleTypeDef::AbortCpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 154 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort_IT(), HAL_SD_Init(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

uint32_t __SD_HandleTypeDef::CID[4]

SD card identification number table

Definition at line 148 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID(), and SD_InitCard().

__IO uint32_t __SD_HandleTypeDef::Context

SD transfer context

Definition at line 138 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

uint32_t __SD_HandleTypeDef::CSD[4]

SD card specific data table

Definition at line 146 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and SD_InitCard().

void(* __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback)(FlagStatus status)

Definition at line 161 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_DeInit(), HAL_SD_Init(), HAL_SD_RegisterTransceiverCallback(), HAL_SD_UnRegisterTransceiverCallback(), SD_DDR_Mode(), SD_PowerON(), and SD_UltraHighSpeed().

void(* __SD_HandleTypeDef::ErrorCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 153 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

__IO uint32_t __SD_HandleTypeDef::ErrorCode

SD Card Error codes

Definition at line 142 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardState(), HAL_SD_GetCardStatus(), HAL_SD_GetError(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_RegisterCallback(), HAL_SD_RegisterTransceiverCallback(), HAL_SD_UnRegisterCallback(), HAL_SD_UnRegisterTransceiverCallback(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_HighSpeed(), SD_SendSDStatus(), and SD_UltraHighSpeed().

SD_InitTypeDef __SD_HandleTypeDef::Init

SD required parameters

Definition at line 126 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Init(), HAL_SD_InitCard(), and SD_PowerON().

SD_TypeDef* __SD_HandleTypeDef::Instance

SD registers base address

Definition at line 124 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ChangeDMABuffer(), HAL_SDEx_ConfigDMAMultiBuffer(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_InitCard(), SD_PowerOFF(), SD_PowerON(), SD_Read_IT(), SD_SendSDStatus(), SD_SendStatus(), SD_UltraHighSpeed(), SD_WideBus_Disable(), SD_WideBus_Enable(), and SD_Write_IT().

HAL_LockTypeDef __SD_HandleTypeDef::Lock

SD locking object

Definition at line 128 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init().

void(* __SD_HandleTypeDef::MspDeInitCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 165 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_DeInit(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

void(* __SD_HandleTypeDef::MspInitCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 164 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

uint8_t* __SD_HandleTypeDef::pRxBuffPtr

Pointer to SD Rx transfer Buffer

Definition at line 134 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), and SD_Read_IT().

uint8_t* __SD_HandleTypeDef::pTxBuffPtr

Pointer to SD Tx transfer Buffer

Definition at line 130 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and SD_Write_IT().

void(* __SD_HandleTypeDef::Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 155 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

void(* __SD_HandleTypeDef::Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 156 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

void(* __SD_HandleTypeDef::RxCpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 152 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

uint32_t __SD_HandleTypeDef::RxXferSize

SD Rx Transfer size

Definition at line 136 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), and SD_Read_IT().

HAL_SD_CardInfoTypeDef __SD_HandleTypeDef::SdCard

SD Card information

Definition at line 144 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_InitCard(), SD_PowerON(), SD_SendSDStatus(), SD_SendStatus(), SD_UltraHighSpeed(), SD_WideBus_Disable(), and SD_WideBus_Enable().

__IO HAL_SD_StateTypeDef __SD_HandleTypeDef::State

SD card State

Definition at line 140 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardStatus(), HAL_SD_GetState(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_RegisterCallback(), HAL_SD_RegisterTransceiverCallback(), HAL_SD_UnRegisterCallback(), HAL_SD_UnRegisterTransceiverCallback(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ConfigDMAMultiBuffer(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_HighSpeed(), and SD_UltraHighSpeed().

void(* __SD_HandleTypeDef::TxCpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 151 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

uint32_t __SD_HandleTypeDef::TxXferSize

SD Tx Transfer size

Definition at line 132 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and SD_Write_IT().

void(* __SD_HandleTypeDef::Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 157 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

void(* __SD_HandleTypeDef::Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd)

Definition at line 158 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_RegisterCallback(), and HAL_SD_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_SD_CardCSDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardCSDTypeDef Struct Reference
Card Specific Data: CSD Register

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | CSDStruct
__IO uint8_t | SysSpecVersion
__IO uint8_t | Reserved1
__IO uint8_t | TAAC
__IO uint8_t | NSAC
__IO uint8_t | MaxBusClkFrec
__IO uint16_t | CardComdClasses
__IO uint8_t | RdBlockLen
__IO uint8_t | PartBlockRead
__IO uint8_t | WrBlockMisalign
__IO uint8_t | RdBlockMisalign
__IO uint8_t | DSRImpl
__IO uint8_t | Reserved2
__IO uint32_t | DeviceSize
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | DeviceSizeMul
__IO uint8_t | EraseGrSize
__IO uint8_t | EraseGrMul
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | ManDeflECC
__IO uint8_t | WrSpeedFact
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | Reserved3
__IO uint8_t | ContentProtectAppli
__IO uint8_t | FileFormatGroup
__IO uint8_t | CopyFlag
__IO uint8_t | PermWrProtect
__IO uint8_t | TempWrProtect
__IO uint8_t | FileFormat
__IO uint8_t | ECC
__IO uint8_t | CSD_CRC
__IO uint8_t | Reserved4

Detailed Description

Definition at line 176 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint16_t HAL_SD_CardCSDTypeDef::CardComdClasses

Card command classes

Definition at line 184 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::ContentProtectAppli

Content protection application

Definition at line 206 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::CopyFlag

Copy flag (OTP)

Definition at line 208 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::CSD_CRC

CSD CRC

Definition at line 213 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::CSDStruct

CSD structure

Definition at line 178 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint32_t HAL_SD_CardCSDTypeDef::DeviceSize

Device Size

Definition at line 191 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::DeviceSizeMul

Device size multiplier

Definition at line 196 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::DSRImpl

DSR implemented

Definition at line 189 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::ECC

ECC code

Definition at line 212 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::EraseGrMul

Erase group size multiplier

Definition at line 198 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::EraseGrSize

Erase group size

Definition at line 197 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::FileFormat

File format

Definition at line 211 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::FileFormatGroup

File format group

Definition at line 207 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::ManDeflECC

Manufacturer default ECC

Definition at line 201 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxBusClkFrec

Max. bus clock frequency

Definition at line 183 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 193 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 192 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxWrBlockLen

Max. write data block length

Definition at line 203 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 195 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 194 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::NSAC

Data read access time 2 in CLK cycles

Definition at line 182 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::PartBlockRead

Partial blocks for read allowed

Definition at line 186 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::PermWrProtect

Permanent write protection

Definition at line 209 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::RdBlockLen

Max. read data block length

Definition at line 185 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::RdBlockMisalign

Read block misalignment

Definition at line 188 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::Reserved1

Reserved

Definition at line 180 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::Reserved2

Reserved

Definition at line 190 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::Reserved3

Reserved

Definition at line 205 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::Reserved4

Always 1

Definition at line 214 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::SysSpecVersion

System specification version

Definition at line 179 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::TAAC

Data read access time 1

Definition at line 181 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::TempWrProtect

Temporary write protection

Definition at line 210 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::WrBlockMisalign

Write block misalignment

Definition at line 187 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 204 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::WrProtectGrEnable

Write protect group enable

Definition at line 200 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::WrProtectGrSize

Write protect group size

Definition at line 199 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypeDef::WrSpeedFact

Write speed factor

Definition at line 202 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_SD_CardCIDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardCIDTypeDef Struct Reference
Card Identification Data: CID Register

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint16_t | ManufactDate
__IO uint8_t | CID_CRC
__IO uint8_t | Reserved2

Detailed Description

Definition at line 223 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CardCIDTypeDef::CID_CRC

CID CRC

Definition at line 233 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint16_t HAL_SD_CardCIDTypeDef::ManufactDate

Manufacturing Date

Definition at line 232 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypeDef::ManufacturerID

Manufacturer ID

Definition at line 225 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint16_t HAL_SD_CardCIDTypeDef::OEM_AppliID

OEM/Application ID

Definition at line 226 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint32_t HAL_SD_CardCIDTypeDef::ProdName1

Product Name part1

Definition at line 227 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypeDef::ProdName2

Product Name part2

Definition at line 228 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypeDef::ProdRev

Product Revision

Definition at line 229 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint32_t HAL_SD_CardCIDTypeDef::ProdSN

Product Serial Number

Definition at line 230 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypeDef::Reserved1

Reserved1

Definition at line 231 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypeDef::Reserved2

Always 1

Definition at line 234 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL_SD_CardStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardStatusTypeDef Struct Reference
SD Card Status returned by ACMD13

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | DataBusWidth
__IO uint8_t | SecuredMode
__IO uint16_t | CardType
__IO uint32_t | ProtectedAreaSize
__IO uint8_t | SpeedClass
__IO uint8_t | PerformanceMove
__IO uint8_t | AllocationUnitSize
__IO uint16_t | EraseSize
__IO uint8_t | EraseTimeout
__IO uint8_t | EraseOffset
__IO uint8_t | UhsSpeedGrade
__IO uint8_t | UhsAllocationUnitSize
__IO uint8_t | VideoSpeedClass

Detailed Description

Definition at line 244 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CardStatusTypeDef::AllocationUnitSize

Carries information about the card's allocation unit size

Definition at line 252 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypeDef::CardType

Carries information about card type

Definition at line 248 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::DataBusWidth

Shows the currently defined data bus width

Definition at line 246 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::EraseOffset

Carries information about the erase offset

Definition at line 255 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypeDef::EraseSize

Determines the number of AUs to be erased in one operation

Definition at line 253 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::EraseTimeout

Determines the timeout for any number of AU erase

Definition at line 254 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::PerformanceMove

Carries information about the card's performance move

Definition at line 251 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint32_t HAL_SD_CardStatusTypeDef::ProtectedAreaSize

Carries information about the capacity of protected area

Definition at line 249 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::SecuredMode

Card is in secured mode of operation

Definition at line 247 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::SpeedClass

Carries information about the speed class of the card

Definition at line 250 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypeDef::UhsAllocationUnitSize

Carries information about the UHS card's allocation unit size

Definition at line 257 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus(), and HAL_SD_Init().

__IO uint8_t HAL_SD_CardStatusTypeDef::UhsSpeedGrade

Carries information about the speed grade of UHS card

Definition at line 256 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus(), and HAL_SD_Init().

__IO uint8_t HAL_SD_CardStatusTypeDef::VideoSpeedClass

Carries information about the Video Speed Class of UHS card

Definition at line 258 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Callback ID enumeration definition

Enumerations
SD Callback ID enumeration definition
SD Exported Types

Enumerations

enum HAL_SD_CallbackIDTypeDef {
HAL_SD_TX_CPLT_CB_ID = 0x00U, HAL_SD_RX_CPLT_CB_ID = 0x01U, HAL_SD_ERROR_CB_ID = 0x02U, HAL_SD_ABORT_CB_ID = 0x03U,
HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,
HAL_SD_MSP_INIT_CB_ID = 0x10U, HAL_SD_MSP_DEINIT_CB_ID = 0x11U
}

Enumeration Type Documentation

enum HAL_SD_CallbackIDTypeDef
Enumerator:
HAL_SD_TX_CPLT_CB_ID

SD Tx Complete Callback ID

HAL_SD_RX_CPLT_CB_ID

SD Rx Complete Callback ID

HAL_SD_ERROR_CB_ID

SD Error Callback ID

HAL_SD_ABORT_CB_ID

SD Abort Callback ID

HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID

SD Rx DMA Double Buffer 0 Complete Callback ID

HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID

SD Rx DMA Double Buffer 1 Complete Callback ID

HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID

SD Tx DMA Double Buffer 0 Complete Callback ID

HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID

SD Tx DMA Double Buffer 1 Complete Callback ID

HAL_SD_MSP_INIT_CB_ID

SD MspInit Callback ID

HAL_SD_MSP_DEINIT_CB_ID

SD MspDeInit Callback ID

Definition at line 268 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Callback pointer definition

Typedefs
SD Callback pointer definition
SD Exported Types

Typedefs

typedef void(* | pSD_CallbackTypeDef )(SD_HandleTypeDef *hsd)
typedef void(* | pSD_TransceiverCallbackTypeDef )(FlagStatus status)

Typedef Documentation

typedef void(* pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd)

Definition at line 289 of file stm32h7xx_hal_sd.h.

typedef void(* pSD_TransceiverCallbackTypeDef)(FlagStatus status)

Definition at line 291 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Error status enumeration Structure definition

Defines
SD Error status enumeration Structure definition
Exported Constants

Defines

#define | HAL_SD_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_SD_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER

Define Documentation

#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED

Misaligned address

Definition at line 318 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE

Error when addressed block is out of range

Definition at line 340 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR

Error in sequence of authentication

Definition at line 338 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM

An invalid selection for erase groups

Definition at line 322 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

Definition at line 319 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY

Error when transfer process is busy

Definition at line 344 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), and HAL_SD_WriteBlocks().

#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED

Command has been executed without using internal ECC

Definition at line 335 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

Definition at line 328 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR

Internal card controller error

Definition at line 329 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE

CID/CSD overwrite error

Definition at line 333 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL

Command response received (but CRC check failed)

Definition at line 312 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT

Command response timeout

Definition at line 314 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED

CRC check of the previous command failed

Definition at line 326 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL

Data block sent/received (CRC check failed)

Definition at line 313 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT

Data timeout

Definition at line 315 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA

Error while DMA transfer

Definition at line 345 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

Definition at line 336 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR

An error in the sequence of erase command occurs

Definition at line 321 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR

General or unknown error

Definition at line 330 of file stm32h7xx_hal_sd.h.

Referenced by SD_DDR_Mode(), SD_HighSpeed(), and SD_UltraHighSpeed().

#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD

Command is not legal for the card state

Definition at line 327 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER

Invalid callback error

Definition at line 349 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_RegisterCallback(), HAL_SD_RegisterTransceiverCallback(), HAL_SD_UnRegisterCallback(), and HAL_SD_UnRegisterTransceiverCallback().

#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE

Error in case of invalid voltage range

Definition at line 339 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

Definition at line 324 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), SD_SendSDStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE

No error

Definition at line 311 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardState(), HAL_SD_GetCardStatus(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_InitCard(), SD_PowerON(), SD_SendSDStatus(), SD_SendStatus(), SD_UltraHighSpeed(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER

the used parameter is not valid

Definition at line 342 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and SD_SendStatus().

#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE

Error when command request is not applicable

Definition at line 341 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), SD_DDR_Mode(), SD_HighSpeed(), SD_InitCard(), SD_UltraHighSpeed(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN

Receive FIFO overrun

Definition at line 317 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN

The card could not sustain data reading in stream rmode

Definition at line 331 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

Definition at line 332 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Timeout error

Definition at line 346 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_Init(), HAL_SD_ReadBlocks(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_PowerON(), SD_SendSDStatus(), and SD_UltraHighSpeed().

#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN

Transmit FIFO underrun

Definition at line 316 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), and HAL_SD_WriteBlocks().

#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE

Error when feature is not insupported

Definition at line 343 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_GetCardCSD(), SD_InitCard(), and SD_PowerON().

#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP

Only partial address space was erased

Definition at line 334 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION

Attempt to program a write protect block

Definition at line 323 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD context enumeration

Defines
SD context enumeration
Exported Constants

Defines

#define | SD_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | SD_CONTEXT_IT ((uint32_t)0x00000008U)
#define | SD_CONTEXT_DMA ((uint32_t)0x00000080U)

Define Documentation

#define SD_CONTEXT_DMA ((uint32_t)0x00000080U)

Process in DMA mode

Definition at line 364 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define SD_CONTEXT_IT ((uint32_t)0x00000008U)

Process in Interrupt mode

Definition at line 363 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_IT(), and HAL_SD_WriteBlocks_IT().

#define SD_CONTEXT_NONE ((uint32_t)0x00000000U)

None

Definition at line 358 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and HAL_SD_WriteBlocks_IT().

#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)

Read multiple blocks operation

Definition at line 360 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), and HAL_SDEx_ReadBlocksDMAMultiBuffer().

#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)

Read single block operation

Definition at line 359 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_ReadBlocks_IT().

#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)

Write multiple blocks operation

Definition at line 362 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)

Write single block operation

Definition at line 361 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and HAL_SD_WriteBlocks_IT().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Supported Memory Cards

Defines
SD Supported Memory Cards
Exported Constants

Defines

#define | CARD_NORMAL_SPEED ((uint32_t)0x00000000U)
#define | CARD_HIGH_SPEED ((uint32_t)0x00000100U)
#define | CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)
#define | CARD_SDSC ((uint32_t)0x00000000U)
#define | CARD_SDHC_SDXC ((uint32_t)0x00000001U)
#define | CARD_SECURED ((uint32_t)0x00000003U)

Define Documentation

#define CARD_HIGH_SPEED ((uint32_t)0x00000100U)

High Speed Card <25Mo/s , Spec version 2.00

Definition at line 374 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Init(), and SD_HighSpeed().

#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U)

Normal Speed Card <12.5Mo/s , Spec Version 1.01

Definition at line 373 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), SD_DDR_Mode(), SD_HighSpeed(), and SD_UltraHighSpeed().

#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)

SD High Capacity <32Go, SD Extended Capacity <2To

Definition at line 379 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), and SD_PowerON().

#define CARD_SDSC ((uint32_t)0x00000000U)

SD Standard Capacity <2Go

Definition at line 378 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

#define CARD_SECURED ((uint32_t)0x00000003U)

Definition at line 380 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), and SD_InitCard().

#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)

UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01

Definition at line 375 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Init(), SD_DDR_Mode(), SD_PowerON(), and SD_UltraHighSpeed().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Supported Version

Defines
SD Supported Version
Exported Constants

Defines

#define | CARD_V1_X ((uint32_t)0x00000000U)
#define | CARD_V2_X ((uint32_t)0x00000001U)

Define Documentation

#define CARD_V1_X ((uint32_t)0x00000000U)

Definition at line 389 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

#define CARD_V2_X ((uint32_t)0x00000001U)

Definition at line 390 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Exported Constants

Modules | Defines
Exported Constants
SD

Modules

SD Error status enumeration Structure definition
SD context enumeration
SD Supported Memory Cards
SD Supported Version

Defines

#define BLOCKSIZE ((uint32_t)512U)

Define Documentation

#define BLOCKSIZE ((uint32_t)512U)

Block size is 512 bytes

Definition at line 306 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ConfigDMAMultiBuffer(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Exported Macros

Defines
SD Exported Macros
SD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)
Reset SD handle state.
#define | __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_SD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

Clear the SD's pending flags.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to clear. This parameter can be one or a combination of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SDIO interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
None

Definition at line 547 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardStatus(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_SendSDStatus(), and SD_UltraHighSpeed().

#define __HAL_SD_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Clear the SD's interrupt pending bits.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 607 of file stm32h7xx_hal_sd.h.

#define __HAL_SD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Disable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 480 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

#define __HAL_SD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Enable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 448 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define __HAL_SD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

Check whether the specified SD flag is set or not.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_DPSMACT: Data path state machine active
  • SDMMC_FLAG_CPSMACT: Command path state machine active
  • SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDMMC_FLAG_TXFIFOF: Transmit FIFO full
  • SDMMC_FLAG_RXFIFOF: Receive FIFO full
  • SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
  • SDMMC_FLAG_RXFIFOE: Receive FIFO empty
  • SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SDIO interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
The new state of SD FLAG (SET or RESET).

Definition at line 518 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_DDR_Mode(), SD_FindSCR(), SD_HighSpeed(), SD_SendSDStatus(), and SD_UltraHighSpeed().

#define __HAL_SD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Check whether the specified SD interrupt has occurred or not.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt source to check. This parameter can be one of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
The new state of SD IT (SET or RESET).

Definition at line 579 of file stm32h7xx_hal_sd.h.

#define __HAL_SD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                              \
                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                             } while(0)

Reset SD handle state.

Parameters:
__HANDLE__ : SD handle.
Return values:
None

Definition at line 409 of file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SD Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the SD
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_SD_DeInit ( SD_HandleTypeDef * hsd )

De-Initializes the SD card.

Parameters:
hsd,: Pointer to SD handle
Return values:
HAL status

Definition at line 539 of file stm32h7xx_hal_sd.c.

References assert_param, __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCode, HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_NONE, HAL_SD_MspDeInit(), HAL_SD_STATE_BUSY, HAL_SD_STATE_RESET, __SD_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::MspDeInitCallback, SD_PowerOFF(), and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Init ( SD_HandleTypeDef * hsd )

Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.

Parameters:
hsd,: Pointer to the SD handle
Return values:
HAL status

Definition at line 334 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::AbortCpltCallback, assert_param, CARD_HIGH_SPEED, CARD_NORMAL_SPEED, CARD_SDHC_SDXC, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCallback, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_AbortCallback(), HAL_SD_CARD_TRANSFER, HAL_SD_ConfigWideBusOperation(), HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_NONE, HAL_SD_ERROR_TIMEOUT, HAL_SD_ErrorCallback(), HAL_SD_GetCardState(), HAL_SD_GetCardStatus(), HAL_SD_InitCard(), HAL_SD_MspInit(), HAL_SD_RxCpltCallback(), HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, HAL_SD_STATE_RESET, HAL_SD_TxCpltCallback(), HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(), __SD_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::Lock, __SD_HandleTypeDef::MspInitCallback, __SD_HandleTypeDef::Read_DMADblBuf0CpltCallback, __SD_HandleTypeDef::Read_DMADblBuf1CpltCallback, __SD_HandleTypeDef::RxCpltCallback, SD_CONTEXT_NONE, __SD_HandleTypeDef::SdCard, __SD_HandleTypeDef::State, __SD_HandleTypeDef::TxCpltCallback, HAL_SD_CardStatusTypeDef::UhsAllocationUnitSize, HAL_SD_CardStatusTypeDef::UhsSpeedGrade, __SD_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __SD_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_SD_InitCard ( SD_HandleTypeDef * hsd )

Initializes the SD Card.

Parameters:
hsd,: Pointer to SD handle
Note:
This function initializes the SD card. It could be used when a card re-initialization is needed.
Return values:
HAL status

Definition at line 464 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::ErrorCode, HAL_Delay(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, __SD_HandleTypeDef::Init, __SAI_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, RCC_PERIPHCLK_SDMMC, SD_InitCard(), SD_InitTypeDef, SD_PowerON(), and __SD_HandleTypeDef::State.

Referenced by HAL_SD_Init().

void HAL_SD_MspDeInit ( SD_HandleTypeDef * hsd )

De-Initialize SD MSP.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 611 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_DeInit(), and HAL_SD_UnRegisterCallback().

void HAL_SD_MspInit ( SD_HandleTypeDef * hsd )

Initializes the SD MSP.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 596 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), and HAL_SD_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
SD Exported Functions

Data transfer functions. More...

Functions

HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransceiver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transceiver 1.8V Mode Callback.
HAL_StatusTypeDef | HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
Register a User SD Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
Unregister a User SD Callback SD Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
Register a User SD Transceiver Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterTransceiverCallback (SD_HandleTypeDef *hsd)
Unregister a User SD Transceiver Callback SD Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to SD card.

Function Documentation

void HAL_SD_AbortCallback ( SD_HandleTypeDef * hsd )

SD Abort callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1865 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Abort_IT(), HAL_SD_Init(), and HAL_SD_UnRegisterCallback().

void HAL_SD_DriveTransceiver_1_8V_Callback ( FlagStatus status )

Enable/Disable the SD Transceiver 1.8V Mode Callback.

Parameters:
status,: Voltage Switch State
Return values:
None

Definition at line 1881 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_DeInit(), HAL_SD_Init(), HAL_SD_UnRegisterTransceiverCallback(), SD_DDR_Mode(), SD_PowerON(), and SD_UltraHighSpeed().

HAL_StatusTypeDef HAL_SD_Erase | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockStartAdd,
 |  | uint32_t | BlockEndAdd
 | ) |  |

Erases the specified memory area of the given SD card.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
BlockStartAdd,: Start Block address
BlockEndAdd,: End Block address
Return values:
HAL status

Definition at line 1463 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::Class, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

void HAL_SD_ErrorCallback ( SD_HandleTypeDef * hsd )

SD error callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1850 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

uint32_t HAL_SD_GetError ( SD_HandleTypeDef * hsd )

Return the SD error code.

Parameters:
hsd : Pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
SD Error Code

Definition at line 1810 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::ErrorCode.

HAL_SD_StateTypeDef HAL_SD_GetState ( SD_HandleTypeDef * hsd )

return the SD state

Parameters:
hsd,: Pointer to sd handle
Return values:
HAL state

Definition at line 1799 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::State.

void HAL_SD_IRQHandler ( SD_HandleTypeDef * hsd )

This function handles SD card interrupt request.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 1565 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_GET_FLAG, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCallback, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TX_UNDERRUN, HAL_SD_ErrorCallback(), HAL_SD_RxCpltCallback(), HAL_SD_STATE_READY, HAL_SD_TxCpltCallback(), HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(), __SD_HandleTypeDef::Instance, __SD_HandleTypeDef::Read_DMADblBuf0CpltCallback, __SD_HandleTypeDef::Read_DMADblBuf1CpltCallback, __SD_HandleTypeDef::RxCpltCallback, SD_CONTEXT_DMA, SD_CONTEXT_IT, SD_CONTEXT_NONE, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, SD_Read_IT(), SD_Write_IT(), __SD_HandleTypeDef::State, __SD_HandleTypeDef::TxCpltCallback, __SD_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __SD_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_SD_ReadBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
pData,: pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of SD blocks to read
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 652 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, BLOCKSIZE, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_BUSY, HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_NONE, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the DMA transfer process through the SD Rx interrupt event.
Parameters:
hsd,: Pointer SD handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 1249 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, __SD_HandleTypeDef::pRxBuffPtr, __SD_HandleTypeDef::RxXferSize, SD_CONTEXT_DMA, SD_CONTEXT_NONE, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ReadBlocks_IT | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the IT transfer process through the SD Rx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 1039 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, __SD_HandleTypeDef::pRxBuffPtr, __SD_HandleTypeDef::RxXferSize, SD_CONTEXT_IT, SD_CONTEXT_NONE, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_RegisterCallback | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CallbackIDTypeDef | CallbackID,
 |  | pSD_CallbackTypeDef | pCallback
 | ) |  |

Register a User SD Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsd | : SD handle
CallbackID : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
  • HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
  • HAL_SD_ERROR_CB_ID SD Error Callback ID
  • HAL_SD_ABORT_CB_ID SD Abort Callback ID
  • HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Rx Double buffer 0 Callback ID
  • HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID
  • HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
  • HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
  • HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
  • HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1911 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::AbortCpltCallback, __SD_HandleTypeDef::ErrorCallback, __SD_HandleTypeDef::ErrorCode, HAL_SD_ABORT_CB_ID, HAL_SD_ERROR_CB_ID, HAL_SD_ERROR_INVALID_CALLBACK, HAL_SD_MSP_DEINIT_CB_ID, HAL_SD_MSP_INIT_CB_ID, HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID, HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID, HAL_SD_RX_CPLT_CB_ID, HAL_SD_STATE_READY, HAL_SD_STATE_RESET, HAL_SD_TX_CPLT_CB_ID, HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID, HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID, __SD_HandleTypeDef::MspDeInitCallback, __SD_HandleTypeDef::MspInitCallback, __SD_HandleTypeDef::Read_DMADblBuf0CpltCallback, __SD_HandleTypeDef::Read_DMADblBuf1CpltCallback, __SD_HandleTypeDef::RxCpltCallback, __SD_HandleTypeDef::State, __SD_HandleTypeDef::TxCpltCallback, __SD_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __SD_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback | ( | SD_HandleTypeDef * | hsd,
 |  | pSD_TransceiverCallbackTypeDef | pCallback
 | ) |  |

Register a User SD Transceiver Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsd | : SD handle
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 2104 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_INVALID_CALLBACK, HAL_SD_STATE_READY, and __SD_HandleTypeDef::State.

void HAL_SD_RxCpltCallback ( SD_HandleTypeDef * hsd )

Rx Transfer completed callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1835 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

void HAL_SD_TxCpltCallback ( SD_HandleTypeDef * hsd )

Tx Transfer completed callbacks.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 1820 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SD_UnRegisterCallback | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User SD Callback SD Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hsd : SD handle
CallbackID : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
  • HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
  • HAL_SD_ERROR_CB_ID SD Error Callback ID
  • HAL_SD_ABORT_CB_ID SD Abort Callback ID
  • HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Rx Double buffer 0 Callback ID
  • HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID
  • HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
  • HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
  • HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
  • HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
Return values:
status

Definition at line 2016 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::AbortCpltCallback, __SD_HandleTypeDef::ErrorCallback, __SD_HandleTypeDef::ErrorCode, HAL_SD_ABORT_CB_ID, HAL_SD_AbortCallback(), HAL_SD_ERROR_CB_ID, HAL_SD_ERROR_INVALID_CALLBACK, HAL_SD_ErrorCallback(), HAL_SD_MSP_DEINIT_CB_ID, HAL_SD_MSP_INIT_CB_ID, HAL_SD_MspDeInit(), HAL_SD_MspInit(), HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID, HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID, HAL_SD_RX_CPLT_CB_ID, HAL_SD_RxCpltCallback(), HAL_SD_STATE_READY, HAL_SD_STATE_RESET, HAL_SD_TX_CPLT_CB_ID, HAL_SD_TxCpltCallback(), HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID, HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID, HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(), __SD_HandleTypeDef::MspDeInitCallback, __SD_HandleTypeDef::MspInitCallback, __SD_HandleTypeDef::Read_DMADblBuf0CpltCallback, __SD_HandleTypeDef::Read_DMADblBuf1CpltCallback, __SD_HandleTypeDef::RxCpltCallback, __SD_HandleTypeDef::State, __SD_HandleTypeDef::TxCpltCallback, __SD_HandleTypeDef::Write_DMADblBuf0CpltCallback, and __SD_HandleTypeDef::Write_DMADblBuf1CpltCallback.

HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback ( SD_HandleTypeDef * hsd )

Unregister a User SD Transceiver Callback SD Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hsd : SD handle
Return values:
status

Definition at line 2141 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::DriveTransceiver_1_8V_Callback, __SD_HandleTypeDef::ErrorCode, HAL_SD_DriveTransceiver_1_8V_Callback(), HAL_SD_ERROR_INVALID_CALLBACK, HAL_SD_STATE_READY, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_WriteBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of SD blocks to write
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 845 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, BLOCKSIZE, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_BUSY, HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_TX_UNDERRUN, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_NONE, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the DMA transfer process through the SD Tx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1358 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, __SD_HandleTypeDef::pTxBuffPtr, SD_CONTEXT_DMA, SD_CONTEXT_NONE, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, __SD_HandleTypeDef::State, and __SD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SD_WriteBlocks_IT | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the IT transfer process through the SD Tx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1143 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, __SD_HandleTypeDef::pTxBuffPtr, SD_CONTEXT_IT, SD_CONTEXT_NONE, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, __SD_HandleTypeDef::SdCard, __SD_HandleTypeDef::State, and __SD_HandleTypeDef::TxXferSize.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_SD_ConfigSpeedBusOperation (SD_HandleTypeDef *hsd, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_SD_CardStateTypeDef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the SD card
    operations and get the related information

Function Documentation

HAL_StatusTypeDef HAL_SD_Abort ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2779 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, SD_CONTEXT_NONE, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Abort_IT ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD (IT mode).

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2816 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __SD_HandleTypeDef::AbortCpltCallback, __SD_HandleTypeDef::ErrorCode, HAL_SD_AbortCallback(), HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | SpeedMode
 | ) |  |

Configure the speed bus mode.

Parameters:
hsd,: Pointer to the SD handle
SpeedMode,: Specifies the SD card speed bus mode This parameter can be one of the following values:
  • SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
  • SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode
  • SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode
  • SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode
Return values:
HAL status

Definition at line 2516 of file stm32h7xx_hal_sd.c.

References assert_param, CARD_HIGH_SPEED, CARD_SDHC_SDXC, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_CARD_TRANSFER, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_TIMEOUT, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_GetCardState(), HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, SD_DDR_Mode(), SD_HighSpeed(), SD_UltraHighSpeed(), __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hsd,: Pointer to SD handle
WideMode,: Specifies the SD card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
HAL status

Definition at line 2418 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, assert_param, CARD_HIGH_SPEED, CARD_SECURED, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Init, __SAI_HandleTypeDef::Init, __SD_HandleTypeDef::Instance, SD_WideBus_Disable(), SD_WideBus_Enable(), __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

Referenced by HAL_SD_Init().

HAL_StatusTypeDef HAL_SD_GetCardCID | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCIDTypeDef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hsd,: Pointer to SD handle
pCID,: Pointer to a HAL_SD_CardCIDTypeDef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 2194 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::CID, HAL_SD_CardCIDTypeDef::CID_CRC, HAL_SD_CardCIDTypeDef::ManufactDate, HAL_SD_CardCIDTypeDef::ManufacturerID, HAL_SD_CardCIDTypeDef::OEM_AppliID, HAL_SD_CardCIDTypeDef::ProdName1, HAL_SD_CardCIDTypeDef::ProdName2, HAL_SD_CardCIDTypeDef::ProdRev, HAL_SD_CardCIDTypeDef::ProdSN, HAL_SD_CardCIDTypeDef::Reserved1, and HAL_SD_CardCIDTypeDef::Reserved2.

HAL_StatusTypeDef HAL_SD_GetCardCSD | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hsd,: Pointer to SD handle
pCSD,: Pointer to a HAL_SD_CardCSDTypeDef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 2227 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, CARD_SDHC_SDXC, CARD_SDSC, HAL_SD_CardCSDTypeDef::CardComdClasses, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardCSDTypeDef::ContentProtectAppli, HAL_SD_CardCSDTypeDef::CopyFlag, __SD_HandleTypeDef::CSD, HAL_SD_CardCSDTypeDef::CSD_CRC, HAL_SD_CardCSDTypeDef::CSDStruct, HAL_SD_CardCSDTypeDef::DeviceSize, HAL_SD_CardCSDTypeDef::DeviceSizeMul, HAL_SD_CardCSDTypeDef::DSRImpl, HAL_SD_CardCSDTypeDef::ECC, HAL_SD_CardCSDTypeDef::EraseGrMul, HAL_SD_CardCSDTypeDef::EraseGrSize, __SD_HandleTypeDef::ErrorCode, HAL_SD_CardCSDTypeDef::FileFormat, HAL_SD_CardCSDTypeDef::FileFormatGroup, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_READY, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardCSDTypeDef::ManDeflECC, HAL_SD_CardCSDTypeDef::MaxBusClkFrec, HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_SD_CardCSDTypeDef::MaxWrBlockLen, HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMin, HAL_SD_CardCSDTypeDef::NSAC, HAL_SD_CardCSDTypeDef::PartBlockRead, HAL_SD_CardCSDTypeDef::PermWrProtect, HAL_SD_CardCSDTypeDef::RdBlockLen, HAL_SD_CardCSDTypeDef::RdBlockMisalign, HAL_SD_CardCSDTypeDef::Reserved1, HAL_SD_CardCSDTypeDef::Reserved2, HAL_SD_CardCSDTypeDef::Reserved3, HAL_SD_CardCSDTypeDef::Reserved4, __SD_HandleTypeDef::SdCard, __SD_HandleTypeDef::State, HAL_SD_CardCSDTypeDef::SysSpecVersion, HAL_SD_CardCSDTypeDef::TAAC, HAL_SD_CardCSDTypeDef::TempWrProtect, HAL_SD_CardCSDTypeDef::WrBlockMisalign, HAL_SD_CardCSDTypeDef::WriteBlockPaPartial, HAL_SD_CardCSDTypeDef::WrProtectGrEnable, HAL_SD_CardCSDTypeDef::WrProtectGrSize, and HAL_SD_CardCSDTypeDef::WrSpeedFact.

Referenced by SD_InitCard().

HAL_StatusTypeDef HAL_SD_GetCardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the SD card info.

Parameters:
hsd,: Pointer to SD handle
pCardInfo,: Pointer to the HAL_SD_CardInfoTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 2393 of file stm32h7xx_hal_sd.c.

References HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, HAL_SD_CardInfoTypeDef::Class, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

HAL_SD_CardStateTypeDef HAL_SD_GetCardState ( SD_HandleTypeDef * hsd )

Gets the current sd card data state.

Parameters:
hsd,: pointer to SD handle
Return values:
Card state

Definition at line 2756 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, and SD_SendStatus().

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), and HAL_SD_Init().

HAL_StatusTypeDef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypeDef * | pStatus
 | ) |  |

Gets the SD status info.

Parameters:
hsd,: Pointer to SD handle
pStatus,: Pointer to the HAL_SD_CardStatusTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 2341 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardStatusTypeDef::AllocationUnitSize, HAL_SD_CardStatusTypeDef::CardType, HAL_SD_CardStatusTypeDef::DataBusWidth, HAL_SD_CardStatusTypeDef::EraseOffset, HAL_SD_CardStatusTypeDef::EraseSize, HAL_SD_CardStatusTypeDef::EraseTimeout, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, HAL_SD_CardStatusTypeDef::PerformanceMove, HAL_SD_CardStatusTypeDef::ProtectedAreaSize, SD_SendSDStatus(), HAL_SD_CardStatusTypeDef::SecuredMode, HAL_SD_CardStatusTypeDef::SpeedClass, __SD_HandleTypeDef::State, HAL_SD_CardStatusTypeDef::UhsAllocationUnitSize, HAL_SD_CardStatusTypeDef::UhsSpeedGrade, and HAL_SD_CardStatusTypeDef::VideoSpeedClass.

Referenced by HAL_SD_Init().

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STM32H7B3xQ HAL User Manual: SD card related functions

Functions
SD card related functions
SD Exported Functions

Functions

HAL_SD_CardStateTypeDef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.

Function Documentation

HAL_StatusTypeDef HAL_SD_GetCardCID | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCIDTypeDef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hsd,: Pointer to SD handle
pCID,: Pointer to a HAL_SD_CardCIDTypeDef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 2194 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::CID, HAL_SD_CardCIDTypeDef::CID_CRC, HAL_SD_CardCIDTypeDef::ManufactDate, HAL_SD_CardCIDTypeDef::ManufacturerID, HAL_SD_CardCIDTypeDef::OEM_AppliID, HAL_SD_CardCIDTypeDef::ProdName1, HAL_SD_CardCIDTypeDef::ProdName2, HAL_SD_CardCIDTypeDef::ProdRev, HAL_SD_CardCIDTypeDef::ProdSN, HAL_SD_CardCIDTypeDef::Reserved1, and HAL_SD_CardCIDTypeDef::Reserved2.

HAL_StatusTypeDef HAL_SD_GetCardCSD | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hsd,: Pointer to SD handle
pCSD,: Pointer to a HAL_SD_CardCSDTypeDef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 2227 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, CARD_SDHC_SDXC, CARD_SDSC, HAL_SD_CardCSDTypeDef::CardComdClasses, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardCSDTypeDef::ContentProtectAppli, HAL_SD_CardCSDTypeDef::CopyFlag, __SD_HandleTypeDef::CSD, HAL_SD_CardCSDTypeDef::CSD_CRC, HAL_SD_CardCSDTypeDef::CSDStruct, HAL_SD_CardCSDTypeDef::DeviceSize, HAL_SD_CardCSDTypeDef::DeviceSizeMul, HAL_SD_CardCSDTypeDef::DSRImpl, HAL_SD_CardCSDTypeDef::ECC, HAL_SD_CardCSDTypeDef::EraseGrMul, HAL_SD_CardCSDTypeDef::EraseGrSize, __SD_HandleTypeDef::ErrorCode, HAL_SD_CardCSDTypeDef::FileFormat, HAL_SD_CardCSDTypeDef::FileFormatGroup, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_READY, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardCSDTypeDef::ManDeflECC, HAL_SD_CardCSDTypeDef::MaxBusClkFrec, HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_SD_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_SD_CardCSDTypeDef::MaxWrBlockLen, HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_SD_CardCSDTypeDef::MaxWrCurrentVDDMin, HAL_SD_CardCSDTypeDef::NSAC, HAL_SD_CardCSDTypeDef::PartBlockRead, HAL_SD_CardCSDTypeDef::PermWrProtect, HAL_SD_CardCSDTypeDef::RdBlockLen, HAL_SD_CardCSDTypeDef::RdBlockMisalign, HAL_SD_CardCSDTypeDef::Reserved1, HAL_SD_CardCSDTypeDef::Reserved2, HAL_SD_CardCSDTypeDef::Reserved3, HAL_SD_CardCSDTypeDef::Reserved4, __SD_HandleTypeDef::SdCard, __SD_HandleTypeDef::State, HAL_SD_CardCSDTypeDef::SysSpecVersion, HAL_SD_CardCSDTypeDef::TAAC, HAL_SD_CardCSDTypeDef::TempWrProtect, HAL_SD_CardCSDTypeDef::WrBlockMisalign, HAL_SD_CardCSDTypeDef::WriteBlockPaPartial, HAL_SD_CardCSDTypeDef::WrProtectGrEnable, HAL_SD_CardCSDTypeDef::WrProtectGrSize, and HAL_SD_CardCSDTypeDef::WrSpeedFact.

Referenced by SD_InitCard().

HAL_StatusTypeDef HAL_SD_GetCardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the SD card info.

Parameters:
hsd,: Pointer to SD handle
pCardInfo,: Pointer to the HAL_SD_CardInfoTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 2393 of file stm32h7xx_hal_sd.c.

References HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, HAL_SD_CardInfoTypeDef::Class, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardInfoTypeDef::RelCardAdd, and __SD_HandleTypeDef::SdCard.

HAL_SD_CardStateTypeDef HAL_SD_GetCardState ( SD_HandleTypeDef * hsd )

Gets the current sd card data state.

Parameters:
hsd,: pointer to SD handle
Return values:
Card state

Definition at line 2756 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, and SD_SendStatus().

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigSpeedBusOperation(), and HAL_SD_Init().

HAL_StatusTypeDef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypeDef * | pStatus
 | ) |  |

Gets the SD status info.

Parameters:
hsd,: Pointer to SD handle
pStatus,: Pointer to the HAL_SD_CardStatusTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 2341 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardStatusTypeDef::AllocationUnitSize, HAL_SD_CardStatusTypeDef::CardType, HAL_SD_CardStatusTypeDef::DataBusWidth, HAL_SD_CardStatusTypeDef::EraseOffset, HAL_SD_CardStatusTypeDef::EraseSize, HAL_SD_CardStatusTypeDef::EraseTimeout, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, HAL_SD_CardStatusTypeDef::PerformanceMove, HAL_SD_CardStatusTypeDef::ProtectedAreaSize, SD_SendSDStatus(), HAL_SD_CardStatusTypeDef::SecuredMode, HAL_SD_CardStatusTypeDef::SpeedClass, __SD_HandleTypeDef::State, HAL_SD_CardStatusTypeDef::UhsAllocationUnitSize, HAL_SD_CardStatusTypeDef::UhsSpeedGrade, and HAL_SD_CardStatusTypeDef::VideoSpeedClass.

Referenced by HAL_SD_Init().

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STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SD Exported Functions

Functions

HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.

Function Documentation

uint32_t HAL_SD_GetError ( SD_HandleTypeDef * hsd )

Return the SD error code.

Parameters:
hsd : Pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
SD Error Code

Definition at line 1810 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::ErrorCode.

HAL_SD_StateTypeDef HAL_SD_GetState ( SD_HandleTypeDef * hsd )

return the SD state

Parameters:
hsd,: Pointer to sd handle
Return values:
HAL state

Definition at line 1799 of file stm32h7xx_hal_sd.c.

References __SD_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: Perioheral Abort management

Functions
Perioheral Abort management
SD Exported Functions

Functions

HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Function Documentation

HAL_StatusTypeDef HAL_SD_Abort ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2779 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, SD_CONTEXT_NONE, and __SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Abort_IT ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD (IT mode).

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2816 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __SD_HandleTypeDef::AbortCpltCallback, __SD_HandleTypeDef::ErrorCode, HAL_SD_AbortCallback(), HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, and __SD_HandleTypeDef::State.

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STM32H7B3xQ HAL User Manual: SD Private Types

SD Private Types
SD Exported Functions
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STM32H7B3xQ HAL User Manual: SD Private Defines

SD Private Defines
SD Exported Functions | SD
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STM32H7B3xQ HAL User Manual: SD Private Variables

SD Private Variables
SD Exported Functions
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STM32H7B3xQ HAL User Manual: SD Private Constants

SD Private Constants
SD Exported Functions
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STM32H7B3xQ HAL User Manual: SD Private Macros

SD Private Macros
SD Exported Functions
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STM32H7B3xQ HAL User Manual: SD Private Functions Prototypes

SD Private Functions Prototypes
SD Exported Functions
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STM32H7B3xQ HAL User Manual: SD

Modules | Defines
SD
STM32H7xx_HAL_Driver

SD HAL module driver. More...

Modules

SD Private Functions
SD Exported Types
Exported Constants
SD Exported Macros

macros to handle interrupts and specific clock configurations

SD Exported Functions
SD Private Defines

Defines

#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE)

Detailed Description

SD HAL module driver.

Define Documentation

#define SD_GET_DLYB_INSTANCE ( SDMMC_INSTANCE )
Value:
(((SDMMC_INSTANCE) == SDMMC1)?  \
               DLYB_SDMMC1 : DLYB_SDMMC2 )

Definition at line 278 of file stm32h7xx_hal_sd.c.

Referenced by SD_DDR_Mode(), and SD_UltraHighSpeed().

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STM32H7B3xQ HAL User Manual: SD Card Internal DMA Buffer structure

Enumerations
SD Card Internal DMA Buffer structure
SDEx Exported Types

Enumerations

enum HAL_SDEx_DMABuffer_MemoryTypeDef { SD_DMA_BUFFER0 = 0x00U, SD_DMA_BUFFER1 = 0x01U }

Enumeration Type Documentation

enum HAL_SDEx_DMABuffer_MemoryTypeDef
Enumerator:
SD_DMA_BUFFER0

selects SD internal DMA Buffer 0

SD_DMA_BUFFER1

selects SD internal DMA Buffer 1

Definition at line 48 of file stm32h7xx_hal_sd_ex.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MultiBuffer functions

Functions
MultiBuffer functions
SDEx Exported Functions

Multibuffer functions. More...

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Multibuffer functions.

  ==============================================================================
          ##### Multibuffer functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to configure the multibuffer mode and start read and write
    multibuffer mode for SD HAL driver.

Function Documentation

HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SDEx_DMABuffer_MemoryTypeDef | Buffer,
 |  | uint32_t * | pDataBuffer
 | ) |  |

Change the DMA Buffer0 or Buffer1 address on the fly.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure.
Buffer,: the buffer to be changed, This parameter can be one of the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
pDataBuffer,: The new address
Note:
The BUFFER0 address can be changed only when the current transfer use BUFFER1 and the BUFFER1 address can be changed only when the current transfer use BUFFER0.
Return values:
HAL status

Definition at line 292 of file stm32h7xx_hal_sd_ex.c.

References __SD_HandleTypeDef::Instance, and SD_DMA_BUFFER0.

HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pDataBuffer0,
 |  | uint32_t * | pDataBuffer1,
 |  | uint32_t | BufferSize
 | ) |  |

Configure DMA Dual Buffer mode.

The Data transfer is managed by an Internal DMA.

Parameters:
hsd,: SD handle
pDataBuffer0,: Pointer to the buffer0 that will contain/receive the transfered data
pDataBuffer1,: Pointer to the buffer1 that will contain/receive the transfered data
BufferSize,: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
Return values:
HAL status

Definition at line 82 of file stm32h7xx_hal_sd_ex.c.

References BLOCKSIZE, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, and __SD_HandleTypeDef::State.

void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3910 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3925 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The received Data will be stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hsd,: SD handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 106 of file stm32h7xx_hal_sd_ex.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_DMA, SD_CONTEXT_READ_MULTIPLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3940 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 3955 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), and HAL_SD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Write block(s) to a specified address in a card.

The transfered Data are stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hsd,: SD handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 199 of file stm32h7xx_hal_sd_ex.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, __SD_HandleTypeDef::Context, __SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, __SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_DMA, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, __SD_HandleTypeDef::SdCard, and __SD_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SDRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SDRAM Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_DeInit ( SDRAM_HandleTypeDef * hsdram )

Perform the SDRAM device initialization sequence.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 222 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_MspDeInit(), HAL_SDRAM_STATE_RESET, __SDRAM_HandleTypeDef::Init, __SDRAM_HandleTypeDef::Instance, __SDRAM_HandleTypeDef::MspDeInitCallback, and __SDRAM_HandleTypeDef::State.

void HAL_SDRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 326 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init(), and HAL_SDRAM_UnRegisterCallback().

void HAL_SDRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma DMA handle
Return values:
None

Definition at line 341 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init(), and HAL_SDRAM_UnRegisterCallback().

HAL_StatusTypeDef HAL_SDRAM_Init | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_TimingTypeDef * | Timing
 | ) |  |

Performs the SDRAM device initialization sequence.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Timing | Pointer to SDRAM control timing structure
Return values:
HAL status

Definition at line 170 of file stm32h7xx_hal_sdram.c.

References __SDRAM_HandleTypeDef::DmaXferCpltCallback, __SDRAM_HandleTypeDef::DmaXferErrorCallback, HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_MspInit(), HAL_SDRAM_RefreshErrorCallback(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_RESET, __SDRAM_HandleTypeDef::Init, __SDRAM_HandleTypeDef::Instance, __SDRAM_HandleTypeDef::Lock, __SDRAM_HandleTypeDef::MspInitCallback, __SDRAM_HandleTypeDef::RefreshErrorCallback, and __SDRAM_HandleTypeDef::State.

void HAL_SDRAM_IRQHandler ( SDRAM_HandleTypeDef * hsdram )

This function handles SDRAM refresh error interrupt request.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 287 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_RefreshErrorCallback(), __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::RefreshErrorCallback.

void HAL_SDRAM_MspDeInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP DeInit.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 271 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_DeInit(), and HAL_SDRAM_UnRegisterCallback().

void HAL_SDRAM_MspInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP Init.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 255 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init(), and HAL_SDRAM_UnRegisterCallback().

void HAL_SDRAM_RefreshErrorCallback ( SDRAM_HandleTypeDef * hsdram )

SDRAM Refresh error callback.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 310 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init(), HAL_SDRAM_IRQHandler(), and HAL_SDRAM_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output functions

Functions
Input and Output functions
SDRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
Register a User SDRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
Unregister a User SDRAM Callback SDRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_RegisterDmaCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
Register a User SDRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### SDRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_Read_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit data buffer from the SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 479 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit data buffer from the SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 596 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit data buffer from the SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 378 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SDRAM memory using DMA transfer.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 697 of file stm32h7xx_hal_sdram.c.

References HAL_MDMA_Start_IT(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, __SDRAM_HandleTypeDef::hmdma, __SDRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SDRAM_RegisterCallback | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | HAL_SDRAM_CallbackIDTypeDef | CallbackId,
 |  | pSDRAM_CallbackTypeDef | pCallback
 | ) |  |

Register a User SDRAM Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsdram | : SDRAM handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
  • HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
  • HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 797 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_MSP_DEINIT_CB_ID, HAL_SDRAM_MSP_INIT_CB_ID, HAL_SDRAM_REFRESH_ERR_CB_ID, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_RESET, HAL_SDRAM_STATE_WRITE_PROTECTED, __SDRAM_HandleTypeDef::MspDeInitCallback, __SDRAM_HandleTypeDef::MspInitCallback, __SDRAM_HandleTypeDef::RefreshErrorCallback, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | HAL_SDRAM_CallbackIDTypeDef | CallbackId,
 |  | pSDRAM_DmaCallbackTypeDef | pCallback
 | ) |  |

Register a User SDRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsdram | : SDRAM handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
  • HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 942 of file stm32h7xx_hal_sdram.c.

References __SDRAM_HandleTypeDef::DmaXferCpltCallback, __SDRAM_HandleTypeDef::DmaXferErrorCallback, HAL_SDRAM_DMA_XFER_CPLT_CB_ID, HAL_SDRAM_DMA_XFER_ERR_CB_ID, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | HAL_SDRAM_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User SDRAM Callback SDRAM Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hsdram : SDRAM handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
  • HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
  • HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
  • HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
  • HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
Return values:
status

Definition at line 870 of file stm32h7xx_hal_sdram.c.

References __SDRAM_HandleTypeDef::DmaXferCpltCallback, __SDRAM_HandleTypeDef::DmaXferErrorCallback, HAL_SDRAM_DMA_XFER_CPLT_CB_ID, HAL_SDRAM_DMA_XFER_ERR_CB_ID, HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_MSP_DEINIT_CB_ID, HAL_SDRAM_MSP_INIT_CB_ID, HAL_SDRAM_MspDeInit(), HAL_SDRAM_MspInit(), HAL_SDRAM_REFRESH_ERR_CB_ID, HAL_SDRAM_RefreshErrorCallback(), HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_RESET, HAL_SDRAM_STATE_WRITE_PROTECTED, __SDRAM_HandleTypeDef::MspDeInitCallback, __SDRAM_HandleTypeDef::MspInitCallback, __SDRAM_HandleTypeDef::RefreshErrorCallback, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit data buffer to SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 538 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit data buffer to SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 647 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit data buffer to SDRAM memory.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 429 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SDRAM memory using DMA transfer.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 749 of file stm32h7xx_hal_sdram.c.

References HAL_MDMA_Start_IT(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, __SDRAM_HandleTypeDef::hmdma, __SDRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Control functions

Functions
Control functions
SDRAM Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.

Detailed Description

management functions

  ==============================================================================
                         ##### SDRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SDRAM interface.

Function Documentation

uint32_t HAL_SDRAM_GetModeStatus ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM memory current mode.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
The SDRAM memory mode.

Definition at line 1184 of file stm32h7xx_hal_sdram.c.

References __SDRAM_HandleTypeDef::Init, and __SDRAM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | RefreshRate
 | ) |  |

Programs the SDRAM Memory Refresh rate.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
RefreshRate | The SDRAM refresh rate value
Return values:
HAL status

Definition at line 1119 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SendCommand | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_CommandTypeDef * | Command,
 |  | uint32_t | Timeout
 | ) |  |

Sends Command to the SDRAM bank.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Command | SDRAM command structure
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1077 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_READY, __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | AutoRefreshNumber
 | ) |  |

Sets the Number of consecutive SDRAM Memory auto Refresh commands.

Parameters:
hsdram | pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
AutoRefreshNumber | The SDRAM auto Refresh number
Return values:
HAL status

Definition at line 1152 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable ( SDRAM_HandleTypeDef * hsdram )

Disables dynamically SDRAM write protection.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 1041 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, __SDRAM_HandleTypeDef::Init, __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable ( SDRAM_HandleTypeDef * hsdram )

Enables dynamically SDRAM write protection.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 1009 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_WRITE_PROTECTED, __SDRAM_HandleTypeDef::Init, __SDRAM_HandleTypeDef::Instance, and __SDRAM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: State functions

Functions
State functions
SDRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SDRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SDRAM controller
    and the data flow.

Function Documentation

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM state.

Parameters:
hsdram pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL state

Definition at line 1215 of file stm32h7xx_hal_sdram.c.

References __SDRAM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDRAM Exported Types

Data Structures | Typedefs | Enumerations
SDRAM Exported Types
SDRAM

Data Structures

struct | __SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Typedefs

typedef struct
__SDRAM_HandleTypeDef 		SDRAM_HandleTypeDef
SDRAM handle Structure definition.
typedef void(* | pSDRAM_CallbackTypeDef )(SDRAM_HandleTypeDef *hsdram)
HAL SDRAM Callback pointer definition.
typedef void(* | pSDRAM_DmaCallbackTypeDef )(MDMA_HandleTypeDef *hmdma)

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00U, HAL_SDRAM_STATE_READY = 0x01U, HAL_SDRAM_STATE_BUSY = 0x02U, HAL_SDRAM_STATE_ERROR = 0x03U,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, HAL_SDRAM_STATE_PRECHARGED = 0x05U
}
HAL SDRAM State structure definition. More...
enum HAL_SDRAM_CallbackIDTypeDef {
HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U,
HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U
}
HAL SDRAM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram)

HAL SDRAM Callback pointer definition.

Definition at line 103 of file stm32h7xx_hal_sdram.h.

typedef void(* pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma)

Definition at line 104 of file stm32h7xx_hal_sdram.h.

typedef struct __SDRAM_HandleTypeDef SDRAM_HandleTypeDef

SDRAM handle Structure definition.

Enumeration Type Documentation

enum HAL_SDRAM_CallbackIDTypeDef

HAL SDRAM Callback ID enumeration definition.

Enumerator:
HAL_SDRAM_MSP_INIT_CB_ID

SDRAM MspInit Callback ID

HAL_SDRAM_MSP_DEINIT_CB_ID

SDRAM MspDeInit Callback ID

HAL_SDRAM_REFRESH_ERR_CB_ID

SDRAM Refresh Error Callback ID

HAL_SDRAM_DMA_XFER_CPLT_CB_ID

SDRAM DMA Xfer Complete Callback ID

HAL_SDRAM_DMA_XFER_ERR_CB_ID

SDRAM DMA Xfer Error Callback ID

Definition at line 91 of file stm32h7xx_hal_sdram.h.

enum HAL_SDRAM_StateTypeDef

HAL SDRAM State structure definition.

Enumerator:
HAL_SDRAM_STATE_RESET

SDRAM not yet initialized or disabled

HAL_SDRAM_STATE_READY

SDRAM initialized and ready for use

HAL_SDRAM_STATE_BUSY

SDRAM internal process is ongoing

HAL_SDRAM_STATE_ERROR

SDRAM error state

HAL_SDRAM_STATE_WRITE_PROTECTED

SDRAM device write protected

HAL_SDRAM_STATE_PRECHARGED

SDRAM device precharged

Definition at line 48 of file stm32h7xx_hal_sdram.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SDRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SDRAM_HandleTypeDef Struct Reference
SDRAM Exported Types

SDRAM handle Structure definition. More...

#include <stm32h7xx_hal_sdram.h>

Data Fields

FMC_SDRAM_TypeDef * | Instance
FMC_SDRAM_InitTypeDef | Init
__IO HAL_SDRAM_StateTypeDef | State
HAL_LockTypeDef | Lock
MDMA_HandleTypeDef * hmdma
void(* | MspInitCallback )(struct __SDRAM_HandleTypeDef *hsdram)
void(* | MspDeInitCallback )(struct __SDRAM_HandleTypeDef *hsdram)
void(* | RefreshErrorCallback )(struct __SDRAM_HandleTypeDef *hsdram)
void(* | DmaXferCpltCallback )(MDMA_HandleTypeDef *hmdma)
void(* | DmaXferErrorCallback )(MDMA_HandleTypeDef *hmdma)

Detailed Description

SDRAM handle Structure definition.

Definition at line 63 of file stm32h7xx_hal_sdram.h.

Field Documentation

void(* __SDRAM_HandleTypeDef::DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma)

SDRAM DMA Xfer Complete callback

Definition at line 82 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init(), HAL_SDRAM_RegisterDmaCallback(), and HAL_SDRAM_UnRegisterCallback().

void(* __SDRAM_HandleTypeDef::DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma)

SDRAM DMA Xfer Error callback

Definition at line 83 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init(), HAL_SDRAM_RegisterDmaCallback(), and HAL_SDRAM_UnRegisterCallback().

MDMA_HandleTypeDef* __SDRAM_HandleTypeDef::hmdma

Pointer DMA handler

Definition at line 76 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

FMC_SDRAM_InitTypeDef __SDRAM_HandleTypeDef::Init

SDRAM device configuration parameters

Definition at line 70 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

FMC_SDRAM_TypeDef* __SDRAM_HandleTypeDef::Instance

Register base address

Definition at line 68 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_IRQHandler(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

HAL_LockTypeDef __SDRAM_HandleTypeDef::Lock

SDRAM locking object

Definition at line 74 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init().

void(* __SDRAM_HandleTypeDef::MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram)

SDRAM Msp DeInit callback

Definition at line 80 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_RegisterCallback(), and HAL_SDRAM_UnRegisterCallback().

void(* __SDRAM_HandleTypeDef::MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram)

SDRAM Msp Init callback

Definition at line 79 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init(), HAL_SDRAM_RegisterCallback(), and HAL_SDRAM_UnRegisterCallback().

void(* __SDRAM_HandleTypeDef::RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram)

SDRAM Refresh Error callback

Definition at line 81 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init(), HAL_SDRAM_IRQHandler(), HAL_SDRAM_RegisterCallback(), and HAL_SDRAM_UnRegisterCallback().

__IO HAL_SDRAM_StateTypeDef __SDRAM_HandleTypeDef::State

SDRAM access state

Definition at line 72 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetState(), HAL_SDRAM_Init(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_Read_16b(), HAL_SDRAM_Read_32b(), HAL_SDRAM_Read_8b(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_RegisterCallback(), HAL_SDRAM_RegisterDmaCallback(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_UnRegisterCallback(), HAL_SDRAM_Write_16b(), HAL_SDRAM_Write_32b(), HAL_SDRAM_Write_8b(), HAL_SDRAM_Write_DMA(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sdram.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDRAM Exported Macros

Defines
SDRAM Exported Macros
SDRAM

Defines

#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)
Reset SDRAM handle state.

Define Documentation

#define __HAL_SDRAM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                               \
                                                               (__HANDLE__)->State = HAL_SDRAM_STATE_RESET;  \
                                                               (__HANDLE__)->MspInitCallback = NULL;         \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \
                                                             } while(0)

Reset SDRAM handle state.

Parameters:
__HANDLE__ specifies the SDRAM handle.
Return values:
None

Definition at line 122 of file stm32h7xx_hal_sdram.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 201 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 217 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 215 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS   | \
                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
                                          USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 203 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS
Value:
((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
                                          USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 207 of file stm32h7xx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 210 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
                                          USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 212 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 389 of file stm32h7xx_hal_smartcard.c.

References assert_param, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::MspDeInitCallback, and __SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 316 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::Lock, __SMARTCARD_HandleTypeDef::MspInitCallback, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 455 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit(), and HAL_SMARTCARD_UnRegisterCallback().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 439 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init(), and HAL_SMARTCARD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID,
 |  | pSMARTCARD_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMARTCARD Callback To be used instead of the weak predefined callback.

Parameters:
hsmartcard | smartcard handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 485 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Parameters:
hsmartcard smartcard handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 608 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (+) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (+) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (+) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (+) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

  [..]
    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_SMARTCARD_Abort()
        (++) HAL_SMARTCARD_AbortTransmit()
        (++) HAL_SMARTCARD_AbortReceive()
        (++) HAL_SMARTCARD_Abort_IT()
        (++) HAL_SMARTCARD_AbortTransmit_IT()
        (++) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_SMARTCARD_AbortCpltCallback()
        (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (++) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
            and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
            If user wants to abort it, Abort services should be called by user.
       (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
            This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
            Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1277 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1497 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2158 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1430 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1732 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2190 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1367 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1637 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2174 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2142 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1825 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback, __SMARTCARD_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 891 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 1197 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_RDR register can be read, i.e one interrupt per data to receive.
When FIFO mode is enabled, USART interrupt is generated whenever RXFIFO threshold reached. In that case the interrupt rate depends on RXFIFO threshold configuration.
This function sets the hsmartcard->RxIsr function pointer according to the FIFO mode (data reception processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 1044 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2126 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 802 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX_RX, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 1108 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_RXDATA_FLUSH_REQUEST, __SMARTCARD_HandleTypeDef::TxXferCount, __SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_TDR register is empty, i.e one interrupt per data to transmit.
When FIFO mode is enabled, USART interrupt is generated whenever TXFIFO threshold reached. In that case the interrupt rate depends on TXFIFO threshold configuration.
This function sets the hsmartcard->TxIsr function pointer according to the FIFO mode (data transmission processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 959 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2110 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 2246 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 2229 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, and __SMARTCARD_HandleTypeDef::RxState.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2434 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2496 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2707 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxXferCount, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2667 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2636 of file stm32h7xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxState, and __SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2779 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2857 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2617 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2730 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2828 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2600 of file stm32h7xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static void SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2957 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_MODE_TX_RX, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxISR.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2583 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void SMARTCARD_InitCallbacksToDefault ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the callbacks to their default values.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
none

Definition at line 2269 of file stm32h7xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_RxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3003 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_Receive_IT(), and SMARTCARD_RxISR_FIFOEN().

static void SMARTCARD_RxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3056 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_RXDATA_FLUSH_REQUEST, and SMARTCARD_RxISR().

Referenced by HAL_SMARTCARD_Receive_IT().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2290 of file stm32h7xx_hal_smartcard.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::ClockPrescaler, CSI_VALUE, __SMARTCARD_HandleTypeDef::FifoMode, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_CLOCKPRESCALER, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, SMARTCARD_InitTypeDef::Prescaler, RCC_FLAG_HSIDIV, __SMARTCARD_HandleTypeDef::RxISR, SMARTCARD_CLOCKSOURCE_CSI, SMARTCARD_CLOCKSOURCE_D2PCLK1, SMARTCARD_CLOCKSOURCE_D2PCLK2, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PLL2Q, SMARTCARD_CLOCKSOURCE_PLL3Q, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, __SMARTCARD_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_TxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2889 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static void SMARTCARD_TxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2920 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The new Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 2549 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Exported Types

Data Structures | Typedefs | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_D2PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_D2PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x04U, SMARTCARD_CLOCKSOURCE_CSI = 0x08U,
SMARTCARD_CLOCKSOURCE_LSE = 0x20U, SMARTCARD_CLOCKSOURCE_PLL2Q = 0x40U, SMARTCARD_CLOCKSOURCE_PLL3Q = 0x80U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Typedef Documentation

typedef uint32_t HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see SMARTCARD State Code Definition).
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 188 of file stm32h7xx_hal_smartcard.h.

typedef void(* pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard)

HAL SMARTCARD Callback pointer definition.

pointer to an SMARTCARD callback function

Definition at line 286 of file stm32h7xx_hal_smartcard.h.

typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_HandleTypeDef

SMARTCARD handle Structure definition.

Enumeration Type Documentation

enum HAL_SMARTCARD_CallbackIDTypeDef

HAL SMARTCARD Callback ID enumeration definition.

Enumerator:
HAL_SMARTCARD_TX_COMPLETE_CB_ID

SMARTCARD Tx Complete Callback ID

HAL_SMARTCARD_RX_COMPLETE_CB_ID

SMARTCARD Rx Complete Callback ID

HAL_SMARTCARD_ERROR_CB_ID

SMARTCARD Error Callback ID

HAL_SMARTCARD_ABORT_COMPLETE_CB_ID

SMARTCARD Abort Complete Callback ID

HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID

SMARTCARD Abort Transmit Complete Callback ID

HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID

SMARTCARD Abort Receive Complete Callback ID

HAL_SMARTCARD_RX_FIFO_FULL_CB_ID

SMARTCARD Rx Fifo Full Callback ID

HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID

SMARTCARD Tx Fifo Empty Callback ID

HAL_SMARTCARD_MSPINIT_CB_ID

SMARTCARD MspInit callback ID

HAL_SMARTCARD_MSPDEINIT_CB_ID

SMARTCARD MspDeInit callback ID

Definition at line 267 of file stm32h7xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

SMARTCARD_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_CSI

CSI clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_PLL2Q

PLL2Q clock source

SMARTCARD_CLOCKSOURCE_PLL3Q

PLL3Q clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 293 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount
uint32_t | ClockPrescaler

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 47 of file stm32h7xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 103 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) where usart_ker_ckpres is the USART input clock divided by a prescaler

Definition at line 49 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 100 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 75 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 72 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 69 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of SMARTCARD Clock Prescaler.

Definition at line 108 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 87 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 66 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 89 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 79 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 60 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler. This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency

Definition at line 83 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 57 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 93 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 96 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 54 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 116 of file stm32h7xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 118 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 128 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 138 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 141 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 135 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 125 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 132 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 144 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 122 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | FifoMode
void(* | RxISR )(struct __SMARTCARD_HandleTypeDef *huart)
void(* | TxISR )(struct __SMARTCARD_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | ErrorCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortTransmitCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortReceiveCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxFifoFullCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | TxFifoEmptyCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspDeInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 193 of file stm32h7xx_hal_smartcard.h.

Field Documentation

void(* __SMARTCARD_HandleTypeDef::AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Complete Callback

Definition at line 246 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Receive Complete Callback

Definition at line 250 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Transmit Complete Callback

Definition at line 248 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

SMARTCARD_AdvFeatureInitTypeDef __SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 199 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Error Callback

Definition at line 244 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

__IO uint32_t __SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 237 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

uint32_t __SMARTCARD_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of SMARTCARD FIFO mode.

Definition at line 217 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 230 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 226 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 224 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef __SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 197 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* __SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 195 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), SMARTCARD_WaitOnFlagUntilTimeout(), and SMARTCARDEx_SetNbDataToProcess().

HAL_LockTypeDef __SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 228 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

void(* __SMARTCARD_HandleTypeDef::MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp DeInit callback

Definition at line 258 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

void(* __SMARTCARD_HandleTypeDef::MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp Init callback

Definition at line 256 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

uint16_t __SMARTCARD_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 213 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

uint16_t __SMARTCARD_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 215 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARDEx_SetNbDataToProcess().

uint8_t* __SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 207 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint8_t* __SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 201 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Complete Callback

Definition at line 242 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Fifo Full Callback

Definition at line 252 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::RxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 220 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_SetConfig().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 234 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t __SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 211 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 209 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

void(* __SMARTCARD_HandleTypeDef::TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Complete Callback

Definition at line 240 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Fifo Empty Callback

Definition at line 254 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 222 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

__IO uint16_t __SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 205 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 203 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD State Code Definition

Defines
SMARTCARD State Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_SMARTCARD_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 321 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 325 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 323 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 327 of file stm32h7xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 332 of file stm32h7xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 319 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define HAL_SMARTCARD_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 317 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 330 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Error Code Definition

Defines
SMARTCARD Error Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 346 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), and SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)

frame error

Definition at line 344 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 349 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 343 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 341 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 345 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 342 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)

Receiver TimeOut error

Definition at line 347 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

SMARTCARD frame length

Definition at line 358 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

Define Documentation

#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0

SMARTCARD frame with 0.5 stop bit

Definition at line 366 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

SMARTCARD frame with 1.5 stop bits

Definition at line 367 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define SMARTCARD_PARITY_EVEN USART_CR1_PCE

SMARTCARD frame even parity

Definition at line 375 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

SMARTCARD frame odd parity

Definition at line 376 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define SMARTCARD_MODE_RX USART_CR1_RE

SMARTCARD RX mode

Definition at line 384 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX USART_CR1_TE

SMARTCARD TX mode

Definition at line 385 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

SMARTCARD RX and TX mode

Definition at line 386 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

SMARTCARD frame high polarity

Definition at line 395 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW 0x00000000U

SMARTCARD frame low polarity

Definition at line 394 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define SMARTCARD_PHASE_1EDGE 0x00000000U

SMARTCARD frame phase on first clock transition

Definition at line 403 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

SMARTCARD frame phase on second clock transition

Definition at line 404 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE 0x00000000U

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 412 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 413 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U

SMARTCARD frame one-bit sample disabled

Definition at line 421 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

SMARTCARD frame one-bit sample enabled

Definition at line 422 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK

Define Documentation

#define SMARTCARD_NACK_DISABLE 0x00000000U

SMARTCARD NACK transmission disabled

Definition at line 430 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE USART_CR3_NACK

SMARTCARD NACK transmission enabled

Definition at line 431 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U

SMARTCARD receiver timeout disabled

Definition at line 439 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

SMARTCARD receiver timeout enabled

Definition at line 440 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Clock Prescaler

Defines
SMARTCARD Clock Prescaler
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define SMARTCARD_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 448 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 453 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 454 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 458 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 455 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 449 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 459 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 456 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 450 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 451 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 457 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 452 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 467 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 468 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 476 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 477 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 485 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 486 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 494 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 495 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 504 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 503 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 513 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 512 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 521 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 522 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive data flush request

Definition at line 530 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush request

Definition at line 531 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U

Define Documentation

#define SMARTCARD_CR_MASK 0x00E0U

SMARTCARD control register mask

Definition at line 540 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_CR_POS 5U

SMARTCARD control register position

Definition at line 541 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ISR_MASK 0x1F00U

SMARTCARD ISR register mask

Definition at line 542 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ISR_POS 8U

SMARTCARD ISR register position

Definition at line 543 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_IT_MASK 0x001FU

SMARTCARD interruptions flags mask

Definition at line 539 of file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 613 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
Return values:
None

Definition at line 601 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 631 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 777 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 619 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 625 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 607 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 812 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 707 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 806 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 682 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                     \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 579 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
  • SMARTCARD_FLAG_TXFNF TXFIFO not full flag
  • SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
  • SMARTCARD_FLAG_TXFE TXFIFO Empty flag
  • SMARTCARD_FLAG_RXFF RXFIFO Full flag
  • SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
  • SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 659 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                             & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 732 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
                                                                      (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 756 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 799 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 793 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
                                                          } while(0U)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__ SMARTCARD handle.
Return values:
None

Definition at line 562 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 787 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__ SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1233 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1254 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__ SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1206 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__ SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1261 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__ SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1226 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1240 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__ SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1219 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7U)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__ number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 1116 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 6250001U)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__ Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 1095 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFFU)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__ block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 1102 of file stm32h7xx_hal_smartcard.h.

#define IS_SMARTCARD_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))

Ensure that SMARTCARD clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1189 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 1161 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__ SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1142 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__ SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 1175 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__ SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1168 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__ SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1247 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__ SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1135 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__ SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 1155 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ )
Value:
(((__CPOL__) == SMARTCARD_POLARITY_LOW)\
                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__ SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 1148 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__ SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1268 of file stm32h7xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__ SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1128 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__ SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1182 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 1109 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__ SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1122 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__ | specifies the SMARTCARD Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 829 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Extended Private Constants

Defines
SMARTCARD Extended Private Constants
SMARTCARDEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 62 of file stm32h7xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 65 of file stm32h7xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength | SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 104 of file stm32h7xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 157 of file stm32h7xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 127 of file stm32h7xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 116 of file stm32h7xx_hal_smartcard_ex.c.

References assert_param, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral IO operation functions

Functions
Extended Peripheral IO operation functions
SMARTCARD Extended Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (++) HAL_SMARTCARDEx_RxFifoFullCallback()
        (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()

Function Documentation

void HAL_SMARTCARDEx_RxFifoFullCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD RX Fifo full callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 210 of file stm32h7xx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARDEx_TxFifoEmptyCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD TX Fifo empty callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 226 of file stm32h7xx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral FIFO Control functions

Functions
Extended Peripheral FIFO Control functions
SMARTCARD Extended Exported Functions

SMARTCARD control functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD control functions.

 ===============================================================================
                  ##### Peripheral FIFO Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SMARTCARD
    FIFO feature.
     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 304 of file stm32h7xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 263 of file stm32h7xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FIFOMODE_ENABLE, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_RXFIFO_THRESHOLD_1_8
  • SMARTCARD_RXFIFO_THRESHOLD_1_4
  • SMARTCARD_RXFIFO_THRESHOLD_1_2
  • SMARTCARD_RXFIFO_THRESHOLD_3_4
  • SMARTCARD_RXFIFO_THRESHOLD_7_8
  • SMARTCARD_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 399 of file stm32h7xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_RXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_TXFIFO_THRESHOLD_1_8
  • SMARTCARD_TXFIFO_THRESHOLD_1_4
  • SMARTCARD_TXFIFO_THRESHOLD_1_2
  • SMARTCARD_TXFIFO_THRESHOLD_3_4
  • SMARTCARD_TXFIFO_THRESHOLD_7_8
  • SMARTCARD_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 350 of file stm32h7xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Extended Private Functions

Functions
SMARTCARD Extended Private Functions
SMARTCARDEx

Functions

static void SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void SMARTCARDEx_SetNbDataToProcess ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
hsmartcard SMARTCARD handle.
Return values:
None

Definition at line 454 of file stm32h7xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, SMARTCARD_FIFOMODE_DISABLE, and TX_FIFO_DEPTH.

Referenced by HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Define Documentation

#define IS_SMARTCARD_FIFOMODE_STATE ( __STATE__ )
Value:
(((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

Ensure that SMARTCARD FIFO mode is valid.

Parameters:
__STATE__ SMARTCARD FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 240 of file stm32h7xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 258 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetRxFifoThreshold().

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ )
Value:
(((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 233 of file stm32h7xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 247 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetTxFifoThreshold().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))

Return the transmission completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is reported.
Return values:
Transmission completion flag

Definition at line 225 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                                                                       \
    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
    {                                                                                                        \
      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
    }                                                                                                        \
    else                                                                                                     \
    {                                                                                                        \
      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
    }                                                                                                        \
  } while(0U)

Set the Transmission Completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
If TCBGT (Transmission Complete Before Guard Time) flag is not available or if AdvancedInit.TxCompletionIndication is not already filled, the latter is forced to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
Return values:
None

Definition at line 206 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 50 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT

SMARTCARD transmission complete before guard time

Definition at line 49 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 61 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 64 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 65 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 58 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 60 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 63 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 62 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

TX completion indication before of after guard time

Definition at line 66 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 59 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD FIFO mode

Defines
SMARTCARD FIFO mode
SMARTCARD Extended Exported Constants

SMARTCARD FIFO mode. More...

Defines

#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

SMARTCARD FIFO mode.

Define Documentation

#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 75 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 76 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), and HAL_SMARTCARDEx_EnableFifoMode().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD TXFIFO threshold level

Defines
SMARTCARD TXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD TXFIFO level. More...

Defines

#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

SMARTCARD TXFIFO level.

Define Documentation

#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 87 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 86 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 85 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 88 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 89 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 90 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD RXFIFO threshold level

Defines
SMARTCARD RXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD RXFIFO level. More...

Defines

#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

SMARTCARD RXFIFO level.

Define Documentation

#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 101 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 100 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 99 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 102 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 103 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 104 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 117 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 118 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 128 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 125 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 127 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 126 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 129 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 115 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 119 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF

SMARTCARD RXFIFO Full flag

Definition at line 131 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE

SMARTCARD RXFIFO not empty

Definition at line 124 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT

SMARTCARD RXFIFO threshold flag

Definition at line 132 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE

SMARTCARD read data register not empty

Definition at line 123 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 122 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT

SMARTCARD transmission complete before guard time completion

Definition at line 114 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 116 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF

SMARTCARD transmit data register empty

Definition at line 120 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE

SMARTCARD TXFIFO Empty flag

Definition at line 130 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF

SMARTCARD TXFIFO not full

Definition at line 121 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT

SMARTCARD TXFIFO threshold flag

Definition at line 133 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB 0x0C3BU

SMARTCARD end of block interruption

Definition at line 161 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ERR 0x0060U

SMARTCARD error interruption

Definition at line 156 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_FE 0x0100U

SMARTCARD frame error interruption

Definition at line 159 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_IDLE 0x0424U

SMARTCARD idle line detection interruption

Definition at line 154 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE 0x0200U

SMARTCARD noise error interruption

Definition at line 158 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ORE 0x0300U

SMARTCARD overrun error interruption

Definition at line 157 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_PE 0x0028U

SMARTCARD parity error interruption

Definition at line 148 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RTO 0x0B3AU

SMARTCARD receiver timeout interruption

Definition at line 162 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFF 0x183FU

SMARTCARD RXFIFO full interruption

Definition at line 165 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFNE 0x0525U

SMARTCARD RXFIFO not empty interruption

Definition at line 153 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFT 0x1A7CU

SMARTCARD RXFIFO threshold reached interruption

Definition at line 167 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXNE 0x0525U

SMARTCARD read data register not empty interruption

Definition at line 152 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TC 0x0626U

SMARTCARD transmission complete interruption

Definition at line 151 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TCBGT 0x1978U

SMARTCARD transmission complete before guard time completion interruption

Definition at line 163 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE 0x0727U

SMARTCARD transmit data register empty interruption

Definition at line 149 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFE 0x173EU

SMARTCARD TXFIFO empty interruption

Definition at line 166 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFNF 0x0727U

SMARTCARD TX FIFO not full interruption

Definition at line 150 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFT 0x1B77U

SMARTCARD TXFIFO threshold reached interruption

Definition at line 168 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 185 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 177 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 180 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NECF

SMARTCARD noise error detected clear flag

Definition at line 178 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 179 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 176 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 184 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF

SMARTCARD transmission complete before guard time completion clear flag

Definition at line 183 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 182 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty Clear Flag

Definition at line 181 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Define Documentation

#define HAL_TIMEOUT_ADDR (10000U)

10 s

Definition at line 187 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY (25U)

25 ms

Definition at line 188 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR (25U)

25 ms

Definition at line 189 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE (25U)

25 ms

Definition at line 190 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF (25U)

25 ms

Definition at line 191 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TC (25U)

25 ms

Definition at line 192 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR (25U)

25 ms

Definition at line 193 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS (25U)

25 ms

Definition at line 194 of file stm32h7xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255U

Definition at line 195 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK (0xF0FFFFFFUL)

SMBUS TIMING clear register Mask

Definition at line 186 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
          HAL_SMBUS_ConfigDigitalFilter().

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure Analog noise filter.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
AnalogFilter This parameter can be one of the following values:
  • SMBUS_ANALOGFILTER_ENABLE
  • SMBUS_ANALOGFILTER_DISABLE
Return values:
HAL status

Definition at line 474 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ANALOG_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital noise filter.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 518 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_DIGITAL_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 394 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 274 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::AddrCallback, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspInit(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::Lock, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspInitCallback, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, __SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 455 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_UnRegisterCallback().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 439 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | pSMBUS_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 790 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_RegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID,
 |  | pSMBUS_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMBUS Callback To be used instead of the weak predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 582 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback ( SMBUS_HandleTypeDef * hsmbus )

UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 829 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 695 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspDeInit(), HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MspInit(), HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1420 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1399 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1356 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1340 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1103 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1013 of file stm32h7xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 914 of file stm32h7xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1262 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1168 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection | Master request Transfer Direction (Write/Read)
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 1698 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1622 of file stm32h7xx_hal_smbus.c.

References SMBUS_ITErrorHandler().

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1732 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1561 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, SMBUS_CHECK_FLAG, SMBUS_CHECK_IT_SOURCE, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and __SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1716 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1649 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1633 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1680 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1664 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1779 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1767 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1399 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1356 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1340 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1420 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1103 of file stm32h7xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1013 of file stm32h7xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 914 of file stm32h7xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1262 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1168 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static void | SMBUS_Enable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (struct __SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (struct __SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( struct __SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2623 of file stm32h7xx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and __SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Disable_IRQ | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2384 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_Enable_IRQ | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2344 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_ITErrorHandler ( struct __SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS interrupts error handler.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2456 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_IT_ERRI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_ER_IRQHandler(), and SMBUS_Master_ISR().

static HAL_StatusTypeDef SMBUS_Master_ISR | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 1804 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_ITErrorHandler(), SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 2088 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::ListenCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus | SMBUS handle.
DevAddress | specifies the slave address to be programmed.
Size | specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_RELOAD_MODE Enable Reload mode.
  • SMBUS_AUTOEND_MODE Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  • SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
Request New state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 2606 of file stm32h7xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag | Specifies the SMBUS flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2557 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32h7xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 48 of file stm32h7xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 59 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 53 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 62 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 71 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 74 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 56 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 65 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS ownaddress2 masks.

Definition at line 68 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 77 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 80 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 83 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 50 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smbus.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 98 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

#define HAL_SMBUS_STATE_ERROR (0x00000004U)

Reception process is ongoing

Definition at line 104 of file stm32h7xx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 105 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 100 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 99 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 97 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 96 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 102 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 101 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)

Timeout state

Definition at line 103 of file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 117 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 121 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 116 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 115 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 120 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 119 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 124 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 126 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 114 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 118 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 122 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS handle Structure definition

Data Structures | Typedefs | Enumerations
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct | __SMBUS_HandleTypeDef

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Detailed Description

SMBUS handle Structure definition.

Typedef Documentation

typedef void(* pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an SMBUS Address Match callback function

Definition at line 195 of file stm32h7xx_hal_smbus.h.

typedef void(* pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus)

HAL SMBUS Callback pointer definition.

pointer to an SMBUS callback function

Definition at line 194 of file stm32h7xx_hal_smbus.h.

typedef struct __SMBUS_HandleTypeDef SMBUS_HandleTypeDef

Enumeration Type Documentation

enum HAL_SMBUS_CallbackIDTypeDef

HAL SMBUS Callback ID enumeration definition.

Enumerator:
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID

SMBUS Master Tx Transfer completed callback ID

HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID

SMBUS Master Rx Transfer completed callback ID

HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID

SMBUS Slave Tx Transfer completed callback ID

HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID

SMBUS Slave Rx Transfer completed callback ID

HAL_SMBUS_LISTEN_COMPLETE_CB_ID

SMBUS Listen Complete callback ID

HAL_SMBUS_ERROR_CB_ID

SMBUS Error callback ID

HAL_SMBUS_MSPINIT_CB_ID

SMBUS Msp Init callback ID

HAL_SMBUS_MSPDEINIT_CB_ID

SMBUS Msp DeInit callback ID

Definition at line 177 of file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32h7xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
void(* | MasterTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MasterRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ListenCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ErrorCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | AddrCallback )(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MspDeInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)

Detailed Description

Definition at line 135 of file stm32h7xx_hal_smbus.h.

Field Documentation

void(* __SMBUS_HandleTypeDef::AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

SMBUS Slave Address Match callback

Definition at line 165 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Error callback

Definition at line 163 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 155 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

SMBUS_InitTypeDef __SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 139 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* __SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 137 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

void(* __SMBUS_HandleTypeDef::ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Listen Complete callback

Definition at line 162 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

HAL_LockTypeDef __SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 151 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

void(* __SMBUS_HandleTypeDef::MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Rx Transfer completed callback

Definition at line 159 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Tx Transfer completed callback

Definition at line 158 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp DeInit callback

Definition at line 168 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

void(* __SMBUS_HandleTypeDef::MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp Init callback

Definition at line 167 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

uint8_t* __SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 141 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 149 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

void(* __SMBUS_HandleTypeDef::SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Rx Transfer completed callback

Definition at line 161 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Tx Transfer completed callback

Definition at line 160 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 153 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint16_t __SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 145 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 147 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t __SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 143 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smbus.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 215 of file stm32h7xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 214 of file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 224 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 223 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 233 of file stm32h7xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 234 of file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS ownaddress2 masks

Defines
SMBUS ownaddress2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 244 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 245 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 246 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 247 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 248 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 249 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 250 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 243 of file stm32h7xx_hal_smbus.h.

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STM32H7B3xQ HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 259 of file stm32h7xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 260 of file stm32h7xx_hal_smbus.h.

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STM32H7B3xQ HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 268 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 269 of file stm32h7xx_hal_smbus.h.

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STM32H7B3xQ HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 277 of file stm32h7xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 278 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 286 of file stm32h7xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 287 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 288 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 299 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 298 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 300 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 297 of file stm32h7xx_hal_smbus.h.

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STM32H7B3xQ HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 311 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 312 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 310 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 309 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

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STM32H7B3xQ HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 327 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 329 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 325 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 328 of file stm32h7xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 330 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 326 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 337 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 338 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 335 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 336 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

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STM32H7B3xQ HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 359 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 353 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 358 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 349 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_ITErrorHandler().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 352 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

Definition at line 357 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 354 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 351 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 350 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 356 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 355 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

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STM32H7B3xQ HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 374 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 375 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 384 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and SMBUS_ITErrorHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 380 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 379 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 385 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 386 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 381 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 382 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 373 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 376 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 377 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 378 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 383 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 371 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 372 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 504 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 516 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 444 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 510 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 428 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 522 of file stm32h7xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 486 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 460 of file stm32h7xx_hal_smbus.h.

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \
                                                                (__HANDLE__)->MspInitCallback = NULL;            \
                                                                (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                             } while(0)

Reset SMBUS handle state.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 405 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_TXIS Transmit interrupt status
  • SMBUS_FLAG_RXNE Receive data register not empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_TC Transfer complete (master mode)
  • SMBUS_FLAG_TCR Transfer complete reload
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
  • SMBUS_FLAG_BUSY Bus busy
  • SMBUS_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 485 of file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 541 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 536 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), and HAL_SMBUS_Init().

#define IS_SMBUS_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 539 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigDigitalFilter().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 544 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 556 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 559 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 613 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 614 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 547 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                          ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 562 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 565 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

Definition at line 569 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
                                                          ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

Definition at line 585 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 593 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 579 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 610 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 611 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 601 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

Definition at line 604 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 608 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 605 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 607 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 606 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

Definition at line 598 of file stm32h7xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 599 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPDIFRX Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_RegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
Register a User SPDIFRX Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_UnRegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
Unregister a SPDIFRX Callback SPDIFRX callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
  ##### Initialization and de-initialization functions #####
  ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SPDIFRX peripheral:

  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
      all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
      the selected configuration:
  (++) Input Selection (IN0, IN1,...)
  (++) Maximum allowed re-tries during synchronization phase
  (++) Wait for activity on SPDIF selected input
  (++) Channel status selection (from channel A or B)
  (++) Data format (LSB, MSB, ...)
  (++) Stereo mode
  (++) User bits masking (PT,C,U,V,...)

  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
      of the selected SPDIFRXx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPDIFRX_DeInit ( SPDIFRX_HandleTypeDef * hspdif )

DeInitializes the SPDIFRX peripheral.

Parameters:
hspdif SPDIFRX handle
Return values:
HAL status

Definition at line 343 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_MspDeInit(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_RESET, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::MspDeInitCallback, and __SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_Init ( SPDIFRX_HandleTypeDef * hspdif )

Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.

Parameters:
hspdif SPDIFRX handle
Return values:
HAL status

Definition at line 236 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, SPDIFRX_InitTypeDef::BackupSymbolClockGen, SPDIFRX_InitTypeDef::ChannelSelection, SPDIFRX_InitTypeDef::ChannelStatusMask, __SPDIFRX_HandleTypeDef::CxCpltCallback, __SPDIFRX_HandleTypeDef::CxHalfCpltCallback, SPDIFRX_InitTypeDef::DataFormat, __SPDIFRX_HandleTypeDef::ErrorCallback, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_ErrorCallback(), HAL_SPDIFRX_MspInit(), HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_RxHalfCpltCallback(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, HAL_SPDIFRX_STATE_RESET, __SPDIFRX_HandleTypeDef::Init, SPDIFRX_InitTypeDef::InputSelection, __SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_CHANNEL, IS_SPDIFRX_DATA_FORMAT, IS_SPDIFRX_INPUT_SELECT, IS_SPDIFRX_MAX_RETRIES, IS_SPDIFRX_WAIT_FOR_ACTIVITY, IS_STEREO_MODE, IS_SYMBOL_CLOCK_GEN, IS_VALIDITY_MASK, __SPDIFRX_HandleTypeDef::Lock, __SPDIFRX_HandleTypeDef::MspInitCallback, SPDIFRX_InitTypeDef::ParityErrorMask, SPDIFRX_InitTypeDef::PreambleTypeMask, SPDIFRX_InitTypeDef::Retries, __SPDIFRX_HandleTypeDef::RxCpltCallback, __SPDIFRX_HandleTypeDef::RxHalfCpltCallback, __SPDIFRX_HandleTypeDef::State, SPDIFRX_InitTypeDef::StereoMode, SPDIFRX_InitTypeDef::SymbolClockGen, SPDIFRX_InitTypeDef::ValidityBitMask, and SPDIFRX_InitTypeDef::WaitForActivity.

void HAL_SPDIFRX_MspDeInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP DeInit.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 403 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_DeInit(), and HAL_SPDIFRX_UnRegisterCallback().

void HAL_SPDIFRX_MspInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP Init.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 388 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_UnRegisterCallback().

HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | HAL_SPDIFRX_CallbackIDTypeDef | CallbackID,
 |  | pSPDIFRX_CallbackTypeDef | pCallback
 | ) |  |

Register a User SPDIFRX Callback To be used instead of the weak predefined callback.

Parameters:
hspdif | SPDIFRX handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
  • HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
  • HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
  • HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
  • HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
  • HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
  • HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 430 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::CxCpltCallback, __SPDIFRX_HandleTypeDef::CxHalfCpltCallback, __SPDIFRX_HandleTypeDef::ErrorCallback, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_CX_CPLT_CB_ID, HAL_SPDIFRX_CX_HALF_CB_ID, HAL_SPDIFRX_ERROR_CB_ID, HAL_SPDIFRX_ERROR_INVALID_CALLBACK, HAL_SPDIFRX_MSPDEINIT_CB_ID, HAL_SPDIFRX_MSPINIT_CB_ID, HAL_SPDIFRX_RX_CPLT_CB_ID, HAL_SPDIFRX_RX_HALF_CB_ID, HAL_SPDIFRX_STATE_READY, HAL_SPDIFRX_STATE_RESET, __SPDIFRX_HandleTypeDef::MspDeInitCallback, __SPDIFRX_HandleTypeDef::MspInitCallback, __SPDIFRX_HandleTypeDef::RxCpltCallback, __SPDIFRX_HandleTypeDef::RxHalfCpltCallback, and __SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | SPDIFRX_SetDataFormatTypeDef | sDataFormat
 | ) |  |

Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.

Parameters:
hspdif | SPDIFRX handle
sDataFormat | SPDIFRX data format
Return values:
HAL status

Definition at line 611 of file stm32h7xx_hal_spdifrx.c.

References assert_param, SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask, SPDIFRX_SetDataFormatTypeDef::DataFormat, __SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_DATA_FORMAT, IS_STEREO_MODE, IS_VALIDITY_MASK, SPDIFRX_SetDataFormatTypeDef::ParityErrorMask, SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask, SPDIFRX_STATE_RCV, SPDIFRX_SetDataFormatTypeDef::StereoMode, and SPDIFRX_SetDataFormatTypeDef::ValidityBitMask.

HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | HAL_SPDIFRX_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a SPDIFRX Callback SPDIFRX callabck is redirected to the weak predefined callback.

Parameters:
hspdif SPDIFRX handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
  • HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
  • HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
  • HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
  • HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
  • HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
  • HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 531 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::CxCpltCallback, __SPDIFRX_HandleTypeDef::CxHalfCpltCallback, __SPDIFRX_HandleTypeDef::ErrorCallback, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_CX_CPLT_CB_ID, HAL_SPDIFRX_CX_HALF_CB_ID, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(), HAL_SPDIFRX_ERROR_CB_ID, HAL_SPDIFRX_ERROR_INVALID_CALLBACK, HAL_SPDIFRX_ErrorCallback(), HAL_SPDIFRX_MspDeInit(), HAL_SPDIFRX_MSPDEINIT_CB_ID, HAL_SPDIFRX_MspInit(), HAL_SPDIFRX_MSPINIT_CB_ID, HAL_SPDIFRX_RX_CPLT_CB_ID, HAL_SPDIFRX_RX_HALF_CB_ID, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_RxHalfCpltCallback(), HAL_SPDIFRX_STATE_READY, HAL_SPDIFRX_STATE_RESET, __SPDIFRX_HandleTypeDef::MspDeInitCallback, __SPDIFRX_HandleTypeDef::MspInitCallback, __SPDIFRX_HandleTypeDef::RxCpltCallback, __SPDIFRX_HandleTypeDef::RxHalfCpltCallback, and __SPDIFRX_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
SPDIFRX Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.

Detailed Description

Data transfers functions.

===============================================================================
                     ##### IO operation functions #####
===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SPDIFRX data
    transfers.

    (#) There is two mode of transfer:
        (++) Blocking mode : The communication is performed in the polling mode.
             The status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer start-up.
             The end of the data processing will be indicated through the
             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_SPDIFRX_ReceiveDataFlow()
        (++) HAL_SPDIFRX_ReceiveCtrlFlow()
                (+@) Do not use blocking mode to receive both control and data flow at the same time.

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_SPDIFRX_ReceiveCtrlFlow_IT()
        (++) HAL_SPDIFRX_ReceiveDataFlow_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
        (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_SPDIFRX_RxCpltCallback()
        (++) HAL_SPDIFRX_CxCpltCallback()

Function Documentation

void HAL_SPDIFRX_CxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Control flow) completed callbacks.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1347 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_UnRegisterCallback(), SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

void HAL_SPDIFRX_CxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx (Control flow) Transfer half completed callbacks.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1332 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMACxHalfCplt().

HAL_StatusTypeDef HAL_SPDIFRX_DMAStop ( SPDIFRX_HandleTypeDef * hspdif )

stop the audio stream receive from the Media.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1224 of file stm32h7xx_hal_spdifrx.c.

References __HAL_DMA_DISABLE, __HAL_SPDIFRX_IDLE, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::hdmaCsRx, __SPDIFRX_HandleTypeDef::hdmaDrRx, __SPDIFRX_HandleTypeDef::Instance, and __SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_ErrorCallback ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX error callbacks.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1362 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMAError().

void HAL_SPDIFRX_IRQHandler ( SPDIFRX_HandleTypeDef * hspdif )

This function handles SPDIFRX interrupt request.

Parameters:
hspdif SPDIFRX handle
Return values:
HAL status

Definition at line 1253 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_CLEAR_IT, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_OVR, HAL_SPDIFRX_ERROR_PE, HAL_SPDIFRX_ErrorCallback(), __SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_OVR, SPDIFRX_FLAG_PERR, SPDIFRX_FLAG_RXNE, SPDIFRX_IT_CSRNE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Control Flow) in blocking mode.

Parameters:
hspdif | pointer to a SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 783 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_GetTick(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and __SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with DMA.

Parameters:
hspdif | SPDIFRX handle
pData | a 32-bit pointer to the Receive data buffer.
Size | number of data (Control Flow) sample to be received
Return values:
HAL status

Definition at line 1125 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, __SPDIFRX_HandleTypeDef::CsXferCount, __SPDIFRX_HandleTypeDef::CsXferSize, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPDIFRX_ERROR_DMA, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_ERROR, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::hdmaCsRx, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_DMACxCplt(), SPDIFRX_DMACxHalfCplt(), SPDIFRX_DMAError(), SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, SPDIFRX_STATE_RCV, SPDIFRX_TIMEOUT_VALUE, __SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif | SPDIFRX handle
pData | a 32-bit pointer to the Receive data buffer.
Size | number of data sample (Control Flow) to be received
Return values:
HAL status

Definition at line 939 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, __SPDIFRX_HandleTypeDef::CsXferCount, __SPDIFRX_HandleTypeDef::CsXferSize, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, SPDIFRX_STATE_RCV, SPDIFRX_TIMEOUT_VALUE, and __SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Data Flow) in blocking mode.

Parameters:
hspdif | pointer to SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 710 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_GetTick(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_RXNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and __SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) mode with DMA.

Parameters:
hspdif | SPDIFRX handle
pData | a 32-bit pointer to the Receive data buffer.
Size | number of data sample to be received
Return values:
HAL status

Definition at line 1024 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPDIFRX_ERROR_DMA, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_ERROR, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::hdmaDrRx, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::pRxBuffPtr, __SPDIFRX_HandleTypeDef::RxXferCount, __SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_DMARxHalfCplt(), SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, SPDIFRX_STATE_RCV, SPDIFRX_TIMEOUT_VALUE, __SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.

Parameters:
hspdif | SPDIFRX handle
pData | a 32-bit pointer to the Receive data buffer.
Size | number of data sample to be received .
Return values:
HAL status

Definition at line 854 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::pRxBuffPtr, __SPDIFRX_HandleTypeDef::RxXferCount, __SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, SPDIFRX_STATE_RCV, SPDIFRX_TIMEOUT_VALUE, and __SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_RxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) completed callbacks.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1317 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_UnRegisterCallback(), SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

void HAL_SPDIFRX_RxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) half completed callbacks.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1302 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMARxHalfCplt().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPDIFRX Exported Functions

Peripheral State functions. More...

Functions

HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX error code.

Detailed Description

Peripheral State functions.

===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.

Function Documentation

uint32_t HAL_SPDIFRX_GetError ( SPDIFRX_HandleTypeDef const *const hspdif )

Return the SPDIFRX error code.

Parameters:
hspdif SPDIFRX handle
Return values:
SPDIFRX Error Code

Definition at line 1406 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::ErrorCode.

HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState ( SPDIFRX_HandleTypeDef const *const hspdif )

Return the SPDIFRX state.

Parameters:
hspdif SPDIFRX handle
Return values:
HAL state

Definition at line 1396 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Exported Functions

Modules | Functions
SPDIFRX Exported Functions
SPDIFRX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
This function handles SPDIFRX Communication Timeout.

Function Documentation

static void SPDIFRX_DMACxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1460 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::CsXferCount, __SPDIFRX_HandleTypeDef::CxCpltCallback, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA().

static void SPDIFRX_DMACxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) half complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1481 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::CxHalfCpltCallback, and HAL_SPDIFRX_CxHalfCpltCallback().

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA().

static void SPDIFRX_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1497 of file stm32h7xx_hal_spdifrx.c.

References __SPDIFRX_HandleTypeDef::ErrorCallback, __SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_DMA, HAL_SPDIFRX_ErrorCallback(), HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::RxXferCount, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1420 of file stm32h7xx_hal_spdifrx.c.

References DMA_CIRCULAR, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, __DMA_HandleTypeDef::Init, __SPDIFRX_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __SPDIFRX_HandleTypeDef::RxCpltCallback, __SPDIFRX_HandleTypeDef::RxXferCount, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) half complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1443 of file stm32h7xx_hal_spdifrx.c.

References HAL_SPDIFRX_RxHalfCpltCallback(), and __SPDIFRX_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_ReceiveControlFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1554 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __SPDIFRX_HandleTypeDef::CsXferCount, __SPDIFRX_HandleTypeDef::CxCpltCallback, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_IT_CSRNE, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static void SPDIFRX_ReceiveDataFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Data Flow) with Interrupt.

Parameters:
hspdif SPDIFRX handle
Return values:
None

Definition at line 1524 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, __SPDIFRX_HandleTypeDef::Instance, __SPDIFRX_HandleTypeDef::pRxBuffPtr, __SPDIFRX_HandleTypeDef::RxCpltCallback, __SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | tickstart
 | ) |  | [static]

This function handles SPDIFRX Communication Timeout.

Parameters:
hspdif | SPDIFRX handle
Flag | Flag checked
Status | Value of the flag expected
Timeout | Duration of the timeout
tickstart | Tick start value
Return values:
HAL status

Definition at line 1588 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_GET_FLAG, HAL_GetTick(), HAL_SPDIFRX_STATE_READY, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, and __SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow(), and HAL_SPDIFRX_ReceiveDataFlow().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Exported Types

Data Structures | Typedefs | Enumerations
SPDIFRX Exported Types
SPDIFRX

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | __SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Typedefs

typedef struct
__SPDIFRX_HandleTypeDef 		SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition.

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00U, HAL_SPDIFRX_STATE_READY = 0x01U, HAL_SPDIFRX_STATE_BUSY = 0x02U, HAL_SPDIFRX_STATE_BUSY_RX = 0x03U,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, HAL_SPDIFRX_STATE_ERROR = 0x07U
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __SPDIFRX_HandleTypeDef SPDIFRX_HandleTypeDef

SPDIFRX handle Structure definition.

Enumeration Type Documentation

enum HAL_SPDIFRX_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SPDIFRX_STATE_RESET

SPDIFRX not yet initialized or disabled

HAL_SPDIFRX_STATE_READY

SPDIFRX initialized and ready for use

HAL_SPDIFRX_STATE_BUSY

SPDIFRX internal process is ongoing

HAL_SPDIFRX_STATE_BUSY_RX

SPDIFRX internal Data Flow RX process is ongoing

HAL_SPDIFRX_STATE_BUSY_CX

SPDIFRX internal Control Flow RX process is ongoing

HAL_SPDIFRX_STATE_ERROR

SPDIFRX error state

Definition at line 115 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_InitTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX Init structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

uint32_t | InputSelection
uint32_t | Retries
uint32_t | WaitForActivity
uint32_t | ChannelSelection
uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask
FunctionalState | SymbolClockGen
FunctionalState | BackupSymbolClockGen

Detailed Description

SPDIFRX Init structure definition.

Definition at line 49 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

FunctionalState SPDIFRX_InitTypeDef::BackupSymbolClockGen

Enable/Disable the SPDIFRX Backup Symbol Clock generation. This parameter can be set to Enable or Disable

Definition at line 83 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ChannelSelection

Specifies whether the control flow will take the channel status from channel A or B. This parameter can be a value of SPDIFRX Channel Selection

Definition at line 60 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 72 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 63 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::InputSelection

Specifies the SPDIF input selection. This parameter can be a value of SPDIFRX Input Selection

Definition at line 51 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 78 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 69 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::Retries

Specifies the Maximum allowed re-tries during synchronization phase. This parameter can be a value of SPDIFRX Maximum Retries

Definition at line 54 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 66 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

FunctionalState SPDIFRX_InitTypeDef::SymbolClockGen

Enable/Disable the SPDIFRX Symbol Clock generation. This parameter can be set to Enable or Disable

Definition at line 80 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 75 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::WaitForActivity

Specifies the wait for activity on SPDIF selected input. This parameter can be a value of SPDIFRX Wait For Activity.

Definition at line 57 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX_SetDataFormatTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_SetDataFormatTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX SetDataFormat structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask

Detailed Description

SPDIFRX SetDataFormat structure definition.

Definition at line 90 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

uint32_t SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 101 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 92 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 107 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 98 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 95 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 104 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SPDIFRX_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPDIFRX_HandleTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX handle Structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

SPDIFRX_TypeDef * | Instance
SPDIFRX_InitTypeDef Init
uint32_t * | pRxBuffPtr
uint32_t * | pCsBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
__IO uint16_t | CsXferSize
__IO uint16_t | CsXferCount
DMA_HandleTypeDef * hdmaCsRx
DMA_HandleTypeDef * hdmaDrRx
__IO HAL_LockTypeDef | Lock
__IO HAL_SPDIFRX_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | RxHalfCpltCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | RxCpltCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | CxHalfCpltCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | CxCpltCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | ErrorCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | MspInitCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)
void(* | MspDeInitCallback )(struct __SPDIFRX_HandleTypeDef *hspdif)

Detailed Description

SPDIFRX handle Structure definition.

Definition at line 129 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

__IO uint16_t __SPDIFRX_HandleTypeDef::CsXferCount

Definition at line 153 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

__IO uint16_t __SPDIFRX_HandleTypeDef::CsXferSize

Definition at line 151 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), and HAL_SPDIFRX_ReceiveCtrlFlow_IT().

void(* __SPDIFRX_HandleTypeDef::CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Control flow completed callback

Definition at line 174 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

void(* __SPDIFRX_HandleTypeDef::CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Control flow half completed callback

Definition at line 173 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMACxHalfCplt().

void(* __SPDIFRX_HandleTypeDef::ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX error callback

Definition at line 175 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMAError().

__IO uint32_t __SPDIFRX_HandleTypeDef::ErrorCode

Definition at line 168 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_GetError(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMAError().

DMA_HandleTypeDef* __SPDIFRX_HandleTypeDef::hdmaCsRx

Definition at line 160 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveCtrlFlow_DMA().

DMA_HandleTypeDef* __SPDIFRX_HandleTypeDef::hdmaDrRx

Definition at line 162 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

SPDIFRX_InitTypeDef __SPDIFRX_HandleTypeDef::Init

Definition at line 136 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

SPDIFRX_TypeDef* __SPDIFRX_HandleTypeDef::Instance

Definition at line 134 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_SetDataFormat(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_LockTypeDef __SPDIFRX_HandleTypeDef::Lock

Definition at line 164 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

void(* __SPDIFRX_HandleTypeDef::MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Msp DeInit callback

Definition at line 177 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_RegisterCallback(), and HAL_SPDIFRX_UnRegisterCallback().

void(* __SPDIFRX_HandleTypeDef::MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Msp Init callback

Definition at line 176 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), and HAL_SPDIFRX_UnRegisterCallback().

uint32_t* __SPDIFRX_HandleTypeDef::pCsBuffPtr

Definition at line 140 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), and SPDIFRX_ReceiveControlFlow_IT().

uint32_t* __SPDIFRX_HandleTypeDef::pRxBuffPtr

Definition at line 138 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

void(* __SPDIFRX_HandleTypeDef::RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Data flow completed callback

Definition at line 172 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

void(* __SPDIFRX_HandleTypeDef::RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif)

SPDIFRX Data flow half completed callback

Definition at line 171 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), and SPDIFRX_DMARxHalfCplt().

__IO uint16_t __SPDIFRX_HandleTypeDef::RxXferCount

Definition at line 144 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

__IO uint16_t __SPDIFRX_HandleTypeDef::RxXferSize

Definition at line 142 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_SPDIFRX_StateTypeDef __SPDIFRX_HandleTypeDef::State

Definition at line 166 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_GetState(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), HAL_SPDIFRX_RegisterCallback(), HAL_SPDIFRX_UnRegisterCallback(), HAL_SPI_IRQHandler(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Error Code

Defines
SPDIFRX Error Code
SPDIFRX Exported Constants

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)
#define | HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Define Documentation

#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)

DMA transfer error

Definition at line 217 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and SPDIFRX_DMAError().

#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)

Invalid Callback error

Definition at line 220 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_RegisterCallback(), and HAL_SPDIFRX_UnRegisterCallback().

#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 213 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)

OVR error

Definition at line 215 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)

Parity error

Definition at line 216 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 214 of file stm32h7xx_hal_spdifrx.h.

#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)

Unknown Error error

Definition at line 218 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Input Selection

Defines
SPDIFRX Input Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)

Define Documentation

#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)

Definition at line 229 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)

Definition at line 230 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)

Definition at line 231 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)

Definition at line 232 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Maximum Retries

Defines
SPDIFRX Maximum Retries
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)

Define Documentation

#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)

Definition at line 242 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)

Definition at line 241 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)

Definition at line 243 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)

Definition at line 240 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Wait For Activity

Defines
SPDIFRX Wait For Activity
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Define Documentation

#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)

Definition at line 251 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Definition at line 252 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Preamble Type Mask

Defines
SPDIFRX Preamble Type Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Define Documentation

#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)

Definition at line 260 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Definition at line 261 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Channel Status Mask

Defines
SPDIFRX Channel Status Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Define Documentation

#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */

Definition at line 269 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Definition at line 270 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Validity Mask

Defines
SPDIFRX Validity Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Define Documentation

#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)

Definition at line 278 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Definition at line 279 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Parity Error Mask

Defines
SPDIFRX Parity Error Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Define Documentation

#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)

Definition at line 287 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Definition at line 288 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Channel Selection

Defines
SPDIFRX Channel Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Define Documentation

#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)

Definition at line 296 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Definition at line 297 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Data Format

Defines
SPDIFRX Data Format
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)

Define Documentation

#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)

Definition at line 307 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)

Definition at line 305 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)

Definition at line 306 of file stm32h7xx_hal_spdifrx.h.

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STM32H7B3xQ HAL User Manual: SPDIFRX Stereo Mode

Defines
SPDIFRX Stereo Mode
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Define Documentation

#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 315 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Definition at line 316 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX State

Defines
SPDIFRX State
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Define Documentation

#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)

Definition at line 325 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Definition at line 327 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and HAL_SPDIFRX_SetDataFormat().

#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)

Definition at line 326 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Interrupts Definition

Defines
SPDIFRX Interrupts Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Define Documentation

#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)

Definition at line 336 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Definition at line 341 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)

Definition at line 338 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)

Definition at line 337 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)

Definition at line 335 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)

Definition at line 339 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)

Definition at line 340 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Flags Definition

Defines
SPDIFRX Flags Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Define Documentation

#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)

Definition at line 350 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveCtrlFlow().

#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)

Definition at line 355 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)

Definition at line 352 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)

Definition at line 351 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)

Definition at line 349 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveDataFlow().

#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)

Definition at line 353 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)

Definition at line 356 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)

Definition at line 354 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Definition at line 357 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Exported Macros

Defines
SPDIFRX Exported Macros
SPDIFRX

Defines

#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Define Documentation

#define __HAL_SPDIFRX_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))

Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_SR_SBD
  • SPDIFRX_SR_SYNCD
Return values:
None

Definition at line 464 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define __HAL_SPDIFRX_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 419 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SPDIFRX interrupts.

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
None

Definition at line 418 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_IT(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Checks whether the specified SPDIFRX flag is set or not.

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPDIFRX_FLAG_RXNE
  • SPDIFRX_FLAG_CSRNE
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_FLAG_SBD
  • SPDIFRX_FLAG_SYNCD
  • SPDIFRX_FLAG_FERR
  • SPDIFRX_FLAG_SERR
  • SPDIFRX_FLAG_TERR
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 451 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified SPDIFRX interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
__INTERRUPT__ specifies the SPDIFRX interrupt source to check. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 434 of file stm32h7xx_hal_spdifrx.h.

#define __HAL_SPDIFRX_IDLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)

Disable the specified SPDIFRX peripheral (IDLE State).

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
Return values:
None

Definition at line 389 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_Init().

#define __HAL_SPDIFRX_RCV ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)

Enable the specified SPDIFRX peripheral (RCV State).

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
Return values:
None

Definition at line 402 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0)

Reset SPDIFRX handle state.

Parameters:
__HANDLE__ SPDIFRX handle.
Return values:
None

Definition at line 376 of file stm32h7xx_hal_spdifrx.h.

#define __HAL_SPDIFRX_SYNC ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)

Enable the specified SPDIFRX peripheral (SYNC State).

Parameters:
__HANDLE__ specifies the SPDIFRX Handle.
Return values:
None

Definition at line 395 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow(), HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Private Macros

Defines
SPDIFRX Private Macros
SPDIFRX

Defines

#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)
#define | IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE))

Define Documentation

#define IS_CHANNEL_STATUS_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
                                            ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))

Definition at line 574 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PARITY_ERROR_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
                                            ((VAL) == SPDIFRX_PARITYERRORMASK_ON))

Definition at line 561 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PREAMBLE_TYPE_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
                                            ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))

Definition at line 555 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == SPDIFRX_CHANNEL_A) || \
                                            ((CHANNEL) == SPDIFRX_CHANNEL_B))

Definition at line 564 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
                                            ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \
                                            ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))

Definition at line 567 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_INPUT_SELECT ( INPUT )
Value:
(((INPUT) == SPDIFRX_INPUT_IN1) || \
                                            ((INPUT) == SPDIFRX_INPUT_IN2)  || \
                                            ((INPUT) == SPDIFRX_INPUT_IN3)  || \
                                            ((INPUT) == SPDIFRX_INPUT_IN0))

Definition at line 542 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_MAX_RETRIES ( RET )
Value:
(((RET) == SPDIFRX_MAXRETRIES_NONE) || \
                                            ((RET) == SPDIFRX_MAXRETRIES_3)     || \
                                            ((RET) == SPDIFRX_MAXRETRIES_15)    || \
                                            ((RET) == SPDIFRX_MAXRETRIES_63))

Definition at line 547 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_WAIT_FOR_ACTIVITY ( VAL )
Value:
(((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
                                            ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))

Definition at line 552 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_STEREO_MODE ( MODE )
Value:
(((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
                                            ((MODE) == SPDIFRX_STEREOMODE_ENABLE))

Definition at line 571 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SYMBOL_CLOCK_GEN ( VAL ) (((VAL) == ENABLE) || ((VAL) == DISABLE))

Definition at line 577 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_VALIDITY_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
                                            ((VAL) == SPDIFRX_VALIDITYMASK_ON))

Definition at line 558 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Private Functions

SPDIFRX Private Functions
SPDIFRX
Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX

Modules | Defines | Typedefs | Enumerations
SPDIFRX
STM32H7xx_HAL_Driver

SPDIFRX HAL module driver. More...

Modules

SPDIFRX Exported Functions
SPDIFRX Exported Types
SPDIFRX Exported Constants
SPDIFRX Exported Macros
SPDIFRX Private Macros
SPDIFRX Private Functions

Defines

#define | SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Typedefs

typedef void(* | pSPDIFRX_CallbackTypeDef )(SPDIFRX_HandleTypeDef *hspdif)
HAL SPDIFRX Callback pointer definition.

Enumerations

enum HAL_SPDIFRX_CallbackIDTypeDef {
HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U,
HAL_SPDIFRX_ERROR_CB_ID = 0x04U, HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U
}
HAL SPDIFRX Callback ID enumeration definition. More...

Detailed Description

SPDIFRX HAL module driver.

Define Documentation

#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Definition at line 176 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_ReceiveCtrlFlow_DMA(), HAL_SPDIFRX_ReceiveCtrlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Typedef Documentation

typedef void(* pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif)

HAL SPDIFRX Callback pointer definition.

pointer to an SPDIFRX callback function

Definition at line 203 of file stm32h7xx_hal_spdifrx.h.

Enumeration Type Documentation

enum HAL_SPDIFRX_CallbackIDTypeDef

HAL SPDIFRX Callback ID enumeration definition.

Enumerator:
HAL_SPDIFRX_RX_HALF_CB_ID

SPDIFRX Data flow half completed callback ID

HAL_SPDIFRX_RX_CPLT_CB_ID

SPDIFRX Data flow completed callback

HAL_SPDIFRX_CX_HALF_CB_ID

SPDIFRX Control flow half completed callback

HAL_SPDIFRX_CX_CPLT_CB_ID

SPDIFRX Control flow completed callback

HAL_SPDIFRX_ERROR_CB_ID

SPDIFRX error callback

HAL_SPDIFRX_MSPINIT_CB_ID

SPDIFRX Msp Init callback ID

HAL_SPDIFRX_MSPDEINIT_CB_ID

SPDIFRX Msp DeInit callback ID

Definition at line 189 of file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100UL

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100UL

Definition at line 148 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitOnFlagUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_TxISR_32BIT (SPI_HandleTypeDef *hspi)
Handle the data 32-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_32BIT (SPI_HandleTypeDef *hspi)
Manage the 32-bit receive in Interrupt context.
static void | SPI_AbortTransfer (SPI_HandleTypeDef *hspi)
Abort Transfer and clear flags.
static void | SPI_CloseTransfer (SPI_HandleTypeDef *hspi)
Close Transfer and clear flags.
static uint32_t | SPI_GetPacketSize (SPI_HandleTypeDef *hspi)
Compute configured packet size from fifo perspective.

Detailed Description

Private functions.

Function Documentation

static void SPI_AbortTransfer ( SPI_HandleTypeDef * hspi ) [static]

Abort Transfer and clear flags.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3613 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_SUSPFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_IT_DXP, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_RXP, SPI_IT_TXP, SPI_IT_UDR, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

static void SPI_CloseTransfer ( SPI_HandleTypeDef * hspi ) [static]

Close Transfer and clear flags.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL_ERROR,: if any error detected HAL_OK: if nothing detected

Definition at line 3651 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_OVR, HAL_SPI_ERROR_UDR, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRCCALCULATION_ENABLE, SPI_FLAG_CRCERR, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_UDR, SPI_IT_DXP, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_RXP, SPI_IT_TXP, SPI_IT_UDR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), and SPI_DMAError().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3298 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3272 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_FE, HAL_DMA_GetError(), HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, SPI_CloseTransfer(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3238 of file stm32h7xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback(), and __SPI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3221 of file stm32h7xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback(), and __SPI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3255 of file stm32h7xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback(), and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3165 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE_IT, DMA_CIRCULAR, HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::hdmarx, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __SPI_HandleTypeDef::RxCpltCallback, SPI_IT_EOT, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3359 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, HAL_SPI_AbortCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, SPI_AbortTransfer(), __SPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3137 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE_IT, DMA_CIRCULAR, HAL_SPI_STATE_ABORT, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, SPI_IT_EOT, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxCpltCallback.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3193 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE_IT, DMA_CIRCULAR, HAL_SPI_STATE_ABORT, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, SPI_IT_EOT, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3322 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, HAL_SPI_AbortCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, SPI_AbortTransfer(), __SPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static uint32_t SPI_GetPacketSize ( SPI_HandleTypeDef * hspi ) [static]

Compute configured packet size from fifo perspective.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
Packet size occupied in the fifo

Definition at line 3748 of file stm32h7xx_hal_spi.c.

References SPI_InitTypeDef::DataSize, SPI_InitTypeDef::FifoThreshold, and __SPI_HandleTypeDef::Init.

Referenced by HAL_SPI_Init().

static void SPI_RxISR_16BIT ( SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3431 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, and SPI_IT_RXP.

Referenced by HAL_SPI_Receive_IT(), and HAL_SPI_TransmitReceive_IT().

static void SPI_RxISR_32BIT ( SPI_HandleTypeDef * hspi ) [static]

Manage the 32-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3468 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, and SPI_IT_RXP.

Referenced by HAL_SPI_Receive_IT(), and HAL_SPI_TransmitReceive_IT().

static void SPI_RxISR_8BIT ( SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3394 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, and SPI_IT_RXP.

Referenced by HAL_SPI_Receive_IT(), and HAL_SPI_TransmitReceive_IT().

static void SPI_TxISR_16BIT ( SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3541 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_IT_TXP, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

static void SPI_TxISR_32BIT ( SPI_HandleTypeDef * hspi ) [static]

Handle the data 32-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3577 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_IT_TXP, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

static void SPI_TxISR_8BIT ( SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3505 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_IT_TXP, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag,: SPI flag to check
Status,: flag state to check
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 3727 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_GET_FLAG, and HAL_GetTick().

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold
        (++) FIFO transmission threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 446 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::MspDeInitCallback, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 234 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, SPI_InitTypeDef::FirstBit, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_MspInit(), HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::IOSwap, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_INITIALIZATION_PATTERN, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIFOTHRESHOLD, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::MasterInterDataIdleness, SPI_InitTypeDef::MasterKeepIOState, SPI_InitTypeDef::MasterSSIdleness, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::MspInitCallback, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, SPI_InitTypeDef::NSSPolarity, __SPI_HandleTypeDef::RxCpltCallback, SPI_InitTypeDef::RxCRCInitializationPattern, __SPI_HandleTypeDef::RxHalfCpltCallback, SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_32BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_GetPacketSize(), SPI_HIGHEND_FIFO_SIZE, SPI_LOWEND_FIFO_SIZE, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_NSS_POLARITY_LOW, SPI_NSS_SOFT, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, SPI_InitTypeDef::TIMode, __SPI_HandleTypeDef::TxCpltCallback, SPI_InitTypeDef::TxCRCInitializationPattern, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 506 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_DeInit(), and HAL_SPI_UnRegisterCallback().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 490 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), and HAL_SPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SPI_RegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID,
 |  | pSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User SPI Callback To be used instead of the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 526 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_UnRegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 636 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_ErrorCallback(), HAL_SPI_MspDeInit(), HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MspInit(), HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (##) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (##) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode.
This procedure performs following operations : + Disable SPI Interrupts (depending of transfer direction) + Disable the DMA transfer in the peripheral register (if enabled) + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + Set handle State to READY.
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 2434 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, SPI_AbortTransfer(), SPI_DEFAULT_TIMEOUT, __SPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode.
This procedure performs following operations : + Disable SPI Interrupts (depending of transfer direction) + Disable the DMA transfer in the peripheral register (if enabled) + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + Set handle State to READY + At abort completion, call user abort complete callback.
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2543 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_ERROR_NO_XFER, HAL_DMA_GetError(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, SPI_AbortTransfer(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 3065 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

This API is not supported, it is maintained for backward compatibility.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL_ERROR

Definition at line 2664 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, and HAL_SPI_ERROR_NOT_SUPPORTED.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

This API is not supported, it is maintained for backward compatibility.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL_ERROR

Definition at line 2679 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, and HAL_SPI_ERROR_NOT_SUPPORTED.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

This API is not supported, it is maintained for backward compatibility.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL_ERROR

Definition at line 2694 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, and HAL_SPI_ERROR_NOT_SUPPORTED.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3047 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), SPI_DMAAbortOnError(), and SPI_DMAError().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2708 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_SUSPFLAG, __HAL_SPI_CLEAR_TSERFFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::DataSize, DMA_NORMAL, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ERROR_UDR, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseTransfer(), SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DMAAbortOnError(), SPI_FLAG_DXP, SPI_FLAG_EOT, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXP, SPI_FLAG_SUSP, SPI_FLAG_TSERF, SPI_FLAG_TXP, SPI_FLAG_UDR, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_RXP, SPI_IT_TXP, SPI_IT_UDR, __SPDIFRX_HandleTypeDef::State, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxRxCpltCallback, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | : pointer to data buffer
Size | : amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 984 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CloseTransfer(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_FLAG_EOT, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_MODE_MASTER, SPI_RX_FIFO_1PACKET, SPI_WaitOnFlagUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size | : amount of data to be sent
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Return values:
HAL status

Definition at line 2090 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_CIRCULAR, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, DMA_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size | : amount of data to be sent
Return values:
HAL status

Definition at line 1557 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_RXP, SPI_IT_TSERF, SPI_MODE_MASTER, SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2967 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3015 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | : pointer to data buffer
Size | : amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 777 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CloseTransfer(), SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_FIFO_THRESHOLD_01DATA, SPI_FIFO_THRESHOLD_03DATA, SPI_FLAG_EOT, SPI_FLAG_TXP, SPI_MODE_MASTER, SPI_WaitOnFlagUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size | : amount of data to be sent
Return values:
HAL status

Definition at line 1947 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_CIRCULAR, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, DMA_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_IT_FRE, SPI_IT_MODF, SPI_IT_UDR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size | : amount of data to be sent
Return values:
HAL status

Definition at line 1473 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_TSERF, SPI_IT_TXP, SPI_IT_UDR, SPI_MODE_MASTER, SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size | : amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1205 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CloseTransfer(), SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_FIFO_THRESHOLD_01DATA, SPI_FIFO_THRESHOLD_03DATA, SPI_FLAG_EOT, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_FLAG_TXP, SPI_MODE_MASTER, SPI_RX_FIFO_1PACKET, SPI_WaitOnFlagUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size | : amount of data to be sent
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Return values:
HAL status

Definition at line 2240 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_CIRCULAR, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, DMA_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_UDR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | : pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size | : amount of data to be sent and received
Return values:
HAL status

Definition at line 1654 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_DXP, SPI_IT_EOT, SPI_IT_FRE, SPI_IT_MODF, SPI_IT_OVR, SPI_IT_RXP, SPI_IT_TSERF, SPI_IT_TXP, SPI_IT_UDR, SPI_MODE_MASTER, SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2951 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2999 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2983 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3031 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 3112 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 3100 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00UL, HAL_SPI_STATE_READY = 0x01UL, HAL_SPI_STATE_BUSY = 0x02UL, HAL_SPI_STATE_BUSY_TX = 0x03UL,
HAL_SPI_STATE_BUSY_RX = 0x04UL, HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, HAL_SPI_STATE_ERROR = 0x06UL, HAL_SPI_STATE_ABORT = 0x07UL
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, HAL_SPI_ERROR_CB_ID = 0x06UL, HAL_SPI_ABORT_CB_ID = 0x07UL,
HAL_SPI_MSPINIT_CB_ID = 0x08UL, HAL_SPI_MSPDEINIT_CB_ID = 0x09UL
}
HAL SPI Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi)

HAL SPI Callback pointer definition.

pointer to an SPI callback function

Definition at line 242 of file stm32h7xx_hal_spi.h.

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_CallbackIDTypeDef

HAL SPI Callback ID enumeration definition.

Enumerator:
HAL_SPI_TX_COMPLETE_CB_ID

SPI Tx Completed callback ID

HAL_SPI_RX_COMPLETE_CB_ID

SPI Rx Completed callback ID

HAL_SPI_TX_RX_COMPLETE_CB_ID

SPI TxRx Completed callback ID

HAL_SPI_TX_HALF_COMPLETE_CB_ID

SPI Tx Half Completed callback ID

HAL_SPI_RX_HALF_COMPLETE_CB_ID

SPI Rx Half Completed callback ID

HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID

SPI TxRx Half Completed callback ID

HAL_SPI_ERROR_CB_ID

SPI Error callback ID

HAL_SPI_ABORT_CB_ID

SPI Abort callback ID

HAL_SPI_MSPINIT_CB_ID

SPI Msp Init callback ID

HAL_SPI_MSPDEINIT_CB_ID

SPI Msp DeInit callback ID

Definition at line 224 of file stm32h7xx_hal_spi.h.

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 131 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32h7xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode
uint32_t | NSSPolarity
uint32_t | FifoThreshold
uint32_t | TxCRCInitializationPattern
uint32_t | RxCRCInitializationPattern
uint32_t | MasterSSIdleness
uint32_t | MasterInterDataIdleness
uint32_t | MasterReceiverAutoSusp
uint32_t | MasterKeepIOState
uint32_t | IOSwap

Detailed Description

SPI Configuration Structure definition.

Definition at line 47 of file stm32h7xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 68 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 61 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 58 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 80 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and SPI_CloseTransfer().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. This parameter can be a value of SPI CRC Length

Definition at line 86 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535

Definition at line 83 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 55 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_GetPacketSize().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 52 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

uint32_t SPI_InitTypeDef::FifoThreshold

Specifies the FIFO threshold level. This parameter can be a value of SPI Fifo Threshold

Definition at line 99 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), and SPI_GetPacketSize().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 74 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::IOSwap

Invert MISO/MOSI alternate functions This parameter can be a value of Control SPI IO Swap

Definition at line 123 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterInterDataIdleness

Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode This parameter can be a value of SPI Master Inter-Data Idleness

Definition at line 112 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterKeepIOState

Control of Alternate function GPIOs state This parameter can be a value of Keep IO State

Definition at line 120 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterReceiverAutoSusp

Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. This parameter can be a value of SPI Master Receiver AutoSuspend

Definition at line 116 of file stm32h7xx_hal_spi.h.

uint32_t SPI_InitTypeDef::MasterSSIdleness

Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. This parameter can be a value of SPI Master SS Idleness

Definition at line 108 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 49 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and HAL_SPIEx_ConfigureUnderrun().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 64 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the SSOM bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0).

Definition at line 89 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPolarity

Specifies which level of SS input/output external signal (present on SS pin) is considered as active one. This parameter can be a value of SPI NSS Polarity

Definition at line 95 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::RxCRCInitializationPattern

Specifies the receiver CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 105 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 77 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TxCRCInitializationPattern

Specifies the transmitter CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 102 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spi.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32h7xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | ErrorCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | AbortCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspInitCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspDeInitCallback )(struct __SPI_HandleTypeDef *hspi)

Detailed Description

SPI handle Structure definition.

Definition at line 165 of file stm32h7xx_hal_spi.h.

Field Documentation

void(* __SPI_HandleTypeDef::AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Abort callback

Definition at line 213 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 183 of file stm32h7xx_hal_spi.h.

void(* __SPI_HandleTypeDef::ErrorCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Error callback

Definition at line 212 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_DMAAbortOnError(), and SPI_DMAError().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 197 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_CloseTransfer(), and SPI_DMAError().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 191 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 189 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 169 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), SPI_CloseTransfer(), and SPI_GetPacketSize().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 167 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_EnableLockConfiguration(), HAL_SPIEx_FlushRxFifo(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 193 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

void(* __SPI_HandleTypeDef::MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp DeInit callback

Definition at line 215 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

void(* __SPI_HandleTypeDef::MspInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp Init callback

Definition at line 214 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 177 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 171 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Completed callback

Definition at line 207 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAReceiveCplt().

void(* __SPI_HandleTypeDef::RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Half Completed callback

Definition at line 210 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 185 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 181 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_DMAAbortOnError(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 179 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 195 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_EnableLockConfiguration(), SPI_CloseTransfer(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

void(* __SPI_HandleTypeDef::TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Completed callback

Definition at line 206 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMATransmitCplt().

void(* __SPI_HandleTypeDef::TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Half Completed callback

Definition at line 209 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 187 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

void(* __SPI_HandleTypeDef::TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Completed callback

Definition at line 208 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMATransmitReceiveCplt().

void(* __SPI_HandleTypeDef::TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Half Completed callback

Definition at line 211 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 175 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_DMAAbortOnError(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 173 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spi.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI FIFO Type

Defines
SPI FIFO Type
SPI Exported Constants

Defines

#define | SPI_LOWEND_FIFO_SIZE 8UL
#define | SPI_HIGHEND_FIFO_SIZE 16UL

Define Documentation

#define SPI_HIGHEND_FIFO_SIZE 16UL

Definition at line 259 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPIEx_FlushRxFifo().

#define SPI_LOWEND_FIFO_SIZE 8UL

Definition at line 258 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPIEx_FlushRxFifo().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Error Codes

Defines
SPI Error Codes
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000UL)
#define | HAL_SPI_ERROR_MODF (0x00000001UL)
#define | HAL_SPI_ERROR_CRC (0x00000002UL)
#define | HAL_SPI_ERROR_OVR (0x00000004UL)
#define | HAL_SPI_ERROR_FRE (0x00000008UL)
#define | HAL_SPI_ERROR_DMA (0x00000010UL)
#define | HAL_SPI_ERROR_FLAG (0x00000020UL)
#define | HAL_SPI_ERROR_ABORT (0x00000040UL)
#define | HAL_SPI_ERROR_UDR (0x00000080UL)
#define | HAL_SPI_ERROR_TIMEOUT (0x00000100UL)
#define | HAL_SPI_ERROR_UNKNOW (0x00000200UL)
#define | HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040UL)

Error during SPI Abort procedure

Definition at line 274 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), and HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_CRC (0x00000002UL)

CRC error

Definition at line 269 of file stm32h7xx_hal_spi.h.

Referenced by SPI_CloseTransfer().

#define HAL_SPI_ERROR_DMA (0x00000010UL)

DMA transfer error

Definition at line 272 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), and SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020UL)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 273 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define HAL_SPI_ERROR_FRE (0x00000008UL)

FRE error

Definition at line 271 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL)

Invalid Callback error

Definition at line 280 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

#define HAL_SPI_ERROR_MODF (0x00000001UL)

MODF error

Definition at line 268 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define HAL_SPI_ERROR_NONE (0x00000000UL)

No error

Definition at line 267 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL)

Requested operation not supported

Definition at line 278 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), and HAL_SPI_DMAStop().

#define HAL_SPI_ERROR_OVR (0x00000004UL)

OVR error

Definition at line 270 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL)

Timeout error

Definition at line 276 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define HAL_SPI_ERROR_UDR (0x00000080UL)

Underrun error

Definition at line 275 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define HAL_SPI_ERROR_UNKNOW (0x00000200UL)

Unknow error

Definition at line 277 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000UL)
#define | SPI_MODE_MASTER SPI_CFG2_MASTER

Define Documentation

#define SPI_MODE_MASTER SPI_CFG2_MASTER

Definition at line 290 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define SPI_MODE_SLAVE (0x00000000UL)

Definition at line 289 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPIEx_ConfigureUnderrun().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000UL)
#define | SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
#define | SPI_DIRECTION_1LINE SPI_CFG2_COMM

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CFG2_COMM

Definition at line 301 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_DIRECTION_2LINES (0x00000000UL)

Definition at line 298 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1

Definition at line 300 of file stm32h7xx_hal_spi.h.

#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0

Definition at line 299 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000003UL)
#define | SPI_DATASIZE_5BIT (0x00000004UL)
#define | SPI_DATASIZE_6BIT (0x00000005UL)
#define | SPI_DATASIZE_7BIT (0x00000006UL)
#define | SPI_DATASIZE_8BIT (0x00000007UL)
#define | SPI_DATASIZE_9BIT (0x00000008UL)
#define | SPI_DATASIZE_10BIT (0x00000009UL)
#define | SPI_DATASIZE_11BIT (0x0000000AUL)
#define | SPI_DATASIZE_12BIT (0x0000000BUL)
#define | SPI_DATASIZE_13BIT (0x0000000CUL)
#define | SPI_DATASIZE_14BIT (0x0000000DUL)
#define | SPI_DATASIZE_15BIT (0x0000000EUL)
#define | SPI_DATASIZE_16BIT (0x0000000FUL)
#define | SPI_DATASIZE_17BIT (0x00000010UL)
#define | SPI_DATASIZE_18BIT (0x00000011UL)
#define | SPI_DATASIZE_19BIT (0x00000012UL)
#define | SPI_DATASIZE_20BIT (0x00000013UL)
#define | SPI_DATASIZE_21BIT (0x00000014UL)
#define | SPI_DATASIZE_22BIT (0x00000015UL)
#define | SPI_DATASIZE_23BIT (0x00000016UL)
#define | SPI_DATASIZE_24BIT (0x00000017UL)
#define | SPI_DATASIZE_25BIT (0x00000018UL)
#define | SPI_DATASIZE_26BIT (0x00000019UL)
#define | SPI_DATASIZE_27BIT (0x0000001AUL)
#define | SPI_DATASIZE_28BIT (0x0000001BUL)
#define | SPI_DATASIZE_29BIT (0x0000001CUL)
#define | SPI_DATASIZE_30BIT (0x0000001DUL)
#define | SPI_DATASIZE_31BIT (0x0000001EUL)
#define | SPI_DATASIZE_32BIT (0x0000001FUL)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000009UL)

Definition at line 315 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x0000000AUL)

Definition at line 316 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x0000000BUL)

Definition at line 317 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x0000000CUL)

Definition at line 318 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x0000000DUL)

Definition at line 319 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x0000000EUL)

Definition at line 320 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x0000000FUL)

Definition at line 321 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define SPI_DATASIZE_17BIT (0x00000010UL)

Definition at line 322 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_18BIT (0x00000011UL)

Definition at line 323 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_19BIT (0x00000012UL)

Definition at line 324 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_20BIT (0x00000013UL)

Definition at line 325 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_21BIT (0x00000014UL)

Definition at line 326 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_22BIT (0x00000015UL)

Definition at line 327 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_23BIT (0x00000016UL)

Definition at line 328 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_24BIT (0x00000017UL)

Definition at line 329 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_25BIT (0x00000018UL)

Definition at line 330 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_26BIT (0x00000019UL)

Definition at line 331 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_27BIT (0x0000001AUL)

Definition at line 332 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_28BIT (0x0000001BUL)

Definition at line 333 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_29BIT (0x0000001CUL)

Definition at line 334 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_30BIT (0x0000001DUL)

Definition at line 335 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_31BIT (0x0000001EUL)

Definition at line 336 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_32BIT (0x0000001FUL)

Definition at line 337 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_4BIT (0x00000003UL)

Definition at line 309 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000004UL)

Definition at line 310 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000005UL)

Definition at line 311 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000006UL)

Definition at line 312 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000007UL)

Definition at line 313 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define SPI_DATASIZE_9BIT (0x00000008UL)

Definition at line 314 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000UL)
#define | SPI_POLARITY_HIGH SPI_CFG2_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CFG2_CPOL

Definition at line 346 of file stm32h7xx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000UL)

Definition at line 345 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000UL)
#define | SPI_PHASE_2EDGE SPI_CFG2_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000UL)

Definition at line 354 of file stm32h7xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CFG2_CPHA

Definition at line 355 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CFG2_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000UL)
#define | SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000UL)

Definition at line 364 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE

Definition at line 365 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CFG2_SSM

Definition at line 363 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_DISABLE (0x00000000UL)
#define | SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000UL)

Definition at line 373 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM

Definition at line 374 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
#define | SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
#define | SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
#define | SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
#define | SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
#define | SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
#define | SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
#define | SPI_BAUDRATEPRESCALER_256 (0x70000000UL)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)

Definition at line 388 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)

Definition at line 385 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)

Definition at line 382 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)

Definition at line 389 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)

Definition at line 386 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)

Definition at line 383 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)

Definition at line 387 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)

Definition at line 384 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000UL)
#define | SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Definition at line 398 of file stm32h7xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000UL)

Definition at line 397 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000UL)
#define | SPI_TIMODE_ENABLE SPI_CFG2_SP_0

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000UL)

Definition at line 406 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0

Definition at line 407 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000UL)
#define | SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000UL)

Definition at line 415 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN

Definition at line 416 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and SPI_CloseTransfer().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
#define | SPI_CRC_LENGTH_4BIT (0x00030000UL)
#define | SPI_CRC_LENGTH_5BIT (0x00040000UL)
#define | SPI_CRC_LENGTH_6BIT (0x00050000UL)
#define | SPI_CRC_LENGTH_7BIT (0x00060000UL)
#define | SPI_CRC_LENGTH_8BIT (0x00070000UL)
#define | SPI_CRC_LENGTH_9BIT (0x00080000UL)
#define | SPI_CRC_LENGTH_10BIT (0x00090000UL)
#define | SPI_CRC_LENGTH_11BIT (0x000A0000UL)
#define | SPI_CRC_LENGTH_12BIT (0x000B0000UL)
#define | SPI_CRC_LENGTH_13BIT (0x000C0000UL)
#define | SPI_CRC_LENGTH_14BIT (0x000D0000UL)
#define | SPI_CRC_LENGTH_15BIT (0x000E0000UL)
#define | SPI_CRC_LENGTH_16BIT (0x000F0000UL)
#define | SPI_CRC_LENGTH_17BIT (0x00100000UL)
#define | SPI_CRC_LENGTH_18BIT (0x00110000UL)
#define | SPI_CRC_LENGTH_19BIT (0x00120000UL)
#define | SPI_CRC_LENGTH_20BIT (0x00130000UL)
#define | SPI_CRC_LENGTH_21BIT (0x00140000UL)
#define | SPI_CRC_LENGTH_22BIT (0x00150000UL)
#define | SPI_CRC_LENGTH_23BIT (0x00160000UL)
#define | SPI_CRC_LENGTH_24BIT (0x00170000UL)
#define | SPI_CRC_LENGTH_25BIT (0x00180000UL)
#define | SPI_CRC_LENGTH_26BIT (0x00190000UL)
#define | SPI_CRC_LENGTH_27BIT (0x001A0000UL)
#define | SPI_CRC_LENGTH_28BIT (0x001B0000UL)
#define | SPI_CRC_LENGTH_29BIT (0x001C0000UL)
#define | SPI_CRC_LENGTH_30BIT (0x001D0000UL)
#define | SPI_CRC_LENGTH_31BIT (0x001E0000UL)
#define | SPI_CRC_LENGTH_32BIT (0x001F0000UL)

Define Documentation

#define SPI_CRC_LENGTH_10BIT (0x00090000UL)

Definition at line 431 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_11BIT (0x000A0000UL)

Definition at line 432 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_12BIT (0x000B0000UL)

Definition at line 433 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_13BIT (0x000C0000UL)

Definition at line 434 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_14BIT (0x000D0000UL)

Definition at line 435 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_15BIT (0x000E0000UL)

Definition at line 436 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_16BIT (0x000F0000UL)

Definition at line 437 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_LENGTH_17BIT (0x00100000UL)

Definition at line 438 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_18BIT (0x00110000UL)

Definition at line 439 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_19BIT (0x00120000UL)

Definition at line 440 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_20BIT (0x00130000UL)

Definition at line 441 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_21BIT (0x00140000UL)

Definition at line 442 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_22BIT (0x00150000UL)

Definition at line 443 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_23BIT (0x00160000UL)

Definition at line 444 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_24BIT (0x00170000UL)

Definition at line 445 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_25BIT (0x00180000UL)

Definition at line 446 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_26BIT (0x00190000UL)

Definition at line 447 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_27BIT (0x001A0000UL)

Definition at line 448 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_28BIT (0x001B0000UL)

Definition at line 449 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_29BIT (0x001C0000UL)

Definition at line 450 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_30BIT (0x001D0000UL)

Definition at line 451 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_31BIT (0x001E0000UL)

Definition at line 452 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_32BIT (0x001F0000UL)

Definition at line 453 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_LENGTH_4BIT (0x00030000UL)

Definition at line 425 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_5BIT (0x00040000UL)

Definition at line 426 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_6BIT (0x00050000UL)

Definition at line 427 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_7BIT (0x00060000UL)

Definition at line 428 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_8BIT (0x00070000UL)

Definition at line 429 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_9BIT (0x00080000UL)

Definition at line 430 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)

Definition at line 424 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Fifo Threshold

Defines
SPI Fifo Threshold
SPI Exported Constants

Defines

#define | SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
#define | SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
#define | SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
#define | SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
#define | SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
#define | SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
#define | SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
#define | SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
#define | SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
#define | SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
#define | SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
#define | SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
#define | SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
#define | SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
#define | SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
#define | SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)

Define Documentation

#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)

Definition at line 461 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)

Definition at line 462 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)

Definition at line 463 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)

Definition at line 464 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)

Definition at line 465 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)

Definition at line 466 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)

Definition at line 467 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)

Definition at line 468 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)

Definition at line 469 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)

Definition at line 470 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)

Definition at line 471 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)

Definition at line 472 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)

Definition at line 473 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)

Definition at line 474 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)

Definition at line 475 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)

Definition at line 476 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI CRC Calculation Initialization Pattern

Defines
SPI CRC Calculation Initialization Pattern
SPI Exported Constants

Defines

#define | SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
#define | SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)

Define Documentation

#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)

Definition at line 485 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)

Definition at line 484 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI NSS Polarity

Defines
SPI NSS Polarity
SPI Exported Constants

Defines

#define | SPI_NSS_POLARITY_LOW (0x00000000UL)
#define | SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP

Define Documentation

#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP

Definition at line 494 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_POLARITY_LOW (0x00000000UL)

Definition at line 493 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Keep IO State

Defines
Keep IO State
SPI Exported Constants

Defines

#define | SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
#define | SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Define Documentation

#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)

Definition at line 502 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Definition at line 503 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Control SPI IO Swap

Defines
Control SPI IO Swap
SPI Exported Constants

Defines

#define | SPI_IO_SWAP_DISABLE (0x00000000UL)
#define | SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Define Documentation

#define SPI_IO_SWAP_DISABLE (0x00000000UL)

Definition at line 511 of file stm32h7xx_hal_spi.h.

#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Definition at line 512 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Master SS Idleness

Defines
SPI Master SS Idleness
SPI Exported Constants

Defines

#define | SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
#define | SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
#define | SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
#define | SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
#define | SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
#define | SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
#define | SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
#define | SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
#define | SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
#define | SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
#define | SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
#define | SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
#define | SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
#define | SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
#define | SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
#define | SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)

Define Documentation

#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)

Definition at line 520 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)

Definition at line 521 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)

Definition at line 522 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)

Definition at line 523 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)

Definition at line 524 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)

Definition at line 525 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)

Definition at line 526 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)

Definition at line 527 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)

Definition at line 528 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)

Definition at line 529 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)

Definition at line 530 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)

Definition at line 531 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)

Definition at line 532 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)

Definition at line 533 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)

Definition at line 534 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)

Definition at line 535 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Master Inter-Data Idleness

Defines
SPI Master Inter-Data Idleness
SPI Exported Constants

Defines

#define | SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)

Define Documentation

#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)

Definition at line 543 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)

Definition at line 544 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)

Definition at line 545 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)

Definition at line 546 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)

Definition at line 547 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)

Definition at line 548 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)

Definition at line 549 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)

Definition at line 550 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)

Definition at line 551 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)

Definition at line 552 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)

Definition at line 553 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)

Definition at line 554 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)

Definition at line 555 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)

Definition at line 556 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)

Definition at line 557 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)

Definition at line 558 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Master Receiver AutoSuspend

Defines
SPI Master Receiver AutoSuspend
SPI Exported Constants

Defines

#define | SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
#define | SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX

Define Documentation

#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)

Definition at line 566 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX

Definition at line 567 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Underrun Detection

Defines
SPI Underrun Detection
SPI Exported Constants

Defines

#define | SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
#define | SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
#define | SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1

Define Documentation

#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1

Definition at line 577 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)

Definition at line 575 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0

Definition at line 576 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Underrun Behavior

Defines
SPI Underrun Behavior
SPI Exported Constants

Defines

#define | SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
#define | SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
#define | SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1

Define Documentation

#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0

Definition at line 586 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1

Definition at line 587 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)

Definition at line 585 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_RXP SPI_IER_RXPIE
#define | SPI_IT_TXP SPI_IER_TXPIE
#define | SPI_IT_DXP SPI_IER_DXPIE
#define | SPI_IT_EOT SPI_IER_EOTIE
#define | SPI_IT_TXTF SPI_IER_TXTFIE
#define | SPI_IT_UDR SPI_IER_UDRIE
#define | SPI_IT_OVR SPI_IER_OVRIE
#define | SPI_IT_CRCERR SPI_IER_CRCEIE
#define | SPI_IT_FRE SPI_IER_TIFREIE
#define | SPI_IT_MODF SPI_IER_MODFIE
#define | SPI_IT_TSERF SPI_IER_TSERFIE
#define | SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)

Define Documentation

#define SPI_IT_CRCERR SPI_IER_CRCEIE

Definition at line 602 of file stm32h7xx_hal_spi.h.

#define SPI_IT_DXP SPI_IER_DXPIE

Definition at line 597 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define SPI_IT_EOT SPI_IER_EOTIE

Definition at line 598 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)

Definition at line 606 of file stm32h7xx_hal_spi.h.

#define SPI_IT_FRE SPI_IER_TIFREIE

Definition at line 603 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define SPI_IT_MODF SPI_IER_MODFIE

Definition at line 604 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define SPI_IT_OVR SPI_IER_OVRIE

Definition at line 601 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define SPI_IT_RXP SPI_IER_RXPIE

Definition at line 595 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

#define SPI_IT_TSERF SPI_IER_TSERFIE

Definition at line 605 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

#define SPI_IT_TXP SPI_IER_TXPIE

Definition at line 596 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

#define SPI_IT_TXTF SPI_IER_TXTFIE

Definition at line 599 of file stm32h7xx_hal_spi.h.

#define SPI_IT_UDR SPI_IER_UDRIE

Definition at line 600 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortTransfer(), and SPI_CloseTransfer().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
#define | SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
#define | SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
#define | SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
#define | SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
#define | SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
#define | SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
#define | SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
#define | SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
#define | SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
#define | SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
#define | SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */

Define Documentation

#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */

Definition at line 621 of file stm32h7xx_hal_spi.h.

Referenced by SPI_CloseTransfer().

#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */

Definition at line 616 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */

Definition at line 617 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */

Definition at line 622 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */

Definition at line 627 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and HAL_SPIEx_FlushRxFifo().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */

Definition at line 623 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */

Definition at line 620 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */

Definition at line 614 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */

Definition at line 628 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and HAL_SPIEx_FlushRxFifo().

#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */

Definition at line 625 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */

Definition at line 624 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */

Definition at line 626 of file stm32h7xx_hal_spi.h.

#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */

Definition at line 615 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */

Definition at line 618 of file stm32h7xx_hal_spi.h.

#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */

Definition at line 619 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_CloseTransfer().

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
#define | SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
#define | SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
#define | SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Define Documentation

#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */

Definition at line 636 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_FlushRxFifo().

#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)

Definition at line 637 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)

Definition at line 638 of file stm32h7xx_hal_spi.h.

#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Definition at line 639 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
Clear the SPI EOT pending flag.
#define | __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
Clear the SPI SUSP pending flag.
#define | __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
Clear the SPI TSERF pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 759 of file stm32h7xx_hal_spi.h.

Referenced by SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_EOTFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)

Clear the SPI EOT pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 789 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 777 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 765 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 771 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_SUSPFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)

Clear the SPI SUSP pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 801 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), and SPI_AbortTransfer().

#define __HAL_SPI_CLEAR_TSERFFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)

Clear the SPI TSERF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 807 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_TXTFFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)

Clear the SPI UDR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 795 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_CLEAR_UDRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

Clear the SPI UDR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 783 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 819 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_EnableLockConfiguration(), SPI_AbortTransfer(), and SPI_CloseTransfer().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_RXP : Rx-Packet available interrupt
  • SPI_IT_TXP : Tx-Packet space available interrupt
  • SPI_IT_DXP : Duplex Packet interrupt
  • SPI_IT_EOT : End of transfer interrupt
  • SPI_IT_TXTF : Transmission Transfer Filled interrupt
  • SPI_IT_UDR : Underrun interrupt
  • SPI_IT_OVR : Overrun interrupt
  • SPI_IT_CRCERR : CRC error interrupt
  • SPI_IT_FRE : TI mode frame format error interrupt
  • SPI_IT_MODF : Mode fault interrupt
  • SPI_IT_TSERF : Additional number of data reloaded interrupt
  • SPI_IT_ERR : Error interrupt
Return values:
None

Definition at line 708 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_AbortTransfer(), SPI_CloseTransfer(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 813 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), and HAL_SPIEx_EnableLockConfiguration().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_RXP : Rx-Packet available interrupt
  • SPI_IT_TXP : Tx-Packet space available interrupt
  • SPI_IT_DXP : Duplex Packet interrupt
  • SPI_IT_EOT : End of transfer interrupt
  • SPI_IT_TXTF : Transmission Transfer Filled interrupt
  • SPI_IT_UDR : Underrun interrupt
  • SPI_IT_OVR : Overrun interrupt
  • SPI_IT_CRCERR : CRC error interrupt
  • SPI_IT_FRE : TI mode frame format error interrupt
  • SPI_IT_MODF : Mode fault interrupt
  • SPI_IT_TSERF : Additional number of data reloaded interrupt
  • SPI_IT_ERR : Error interrupt
Return values:
None

Definition at line 687 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXP : Rx-Packet available flag
  • SPI_FLAG_TXP : Tx-Packet space available flag
  • SPI_FLAG_DXP : Duplex Packet flag
  • SPI_FLAG_EOT : End of transfer flag
  • SPI_FLAG_TXTF : Transmission Transfer Filled flag
  • SPI_FLAG_UDR : Underrun flag
  • SPI_FLAG_OVR : Overrun flag
  • SPI_FLAG_CRCERR : CRC error flag
  • SPI_FLAG_FRE : TI mode frame format error flag
  • SPI_FLAG_MODF : Mode fault flag
  • SPI_FLAG_TSERF : Additional number of data reloaded flag
  • SPI_FLAG_SUSP : Transfer suspend complete flag
  • SPI_FLAG_TXC : TxFIFO transmission complete flag
  • SPI_FLAG_FRLVL : Fifo reception level flag
  • SPI_FLAG_RXWNE : RxFIFO word not empty flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 753 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), and SPI_WaitOnFlagUntilTimeout().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_RXP : Rx-Packet available interrupt
  • SPI_IT_TXP : Tx-Packet space available interrupt
  • SPI_IT_DXP : Duplex Packet interrupt
  • SPI_IT_EOT : End of transfer interrupt
  • SPI_IT_TXTF : Transmission Transfer Filled interrupt
  • SPI_IT_UDR : Underrun interrupt
  • SPI_IT_OVR : Overrun interrupt
  • SPI_IT_CRCERR : CRC error interrupt
  • SPI_IT_FRE : TI mode frame format error interrupt
  • SPI_IT_MODF : Mode fault interrupt
  • SPI_IT_TSERF : Additional number of data reloaded interrupt
  • SPI_IT_ERR : Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 729 of file stm32h7xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                       (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                     } while(0)

Reset SPI handle state.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
Return values:
None

Definition at line 659 of file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
Set the SPI receive-only mode.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_FIFOTHRESHOLD(THRESHOLD)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
#define | IS_SPI_UNDERRUN_DETECTION(MODE)
#define | IS_SPI_UNDERRUN_BEHAVIOUR(MODE)

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 1010 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                                                    ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 1000 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                                                    ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 997 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                                    ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 1025 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_INITIALIZATION_PATTERN ( PATTERN )
Value:
(((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
                                                    ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))

Definition at line 1028 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( LENGTH )
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_32BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_31BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_30BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_29BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_28BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_27BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_26BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_25BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_24BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_23BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_22BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_21BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_20BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_19BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_18BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_17BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_15BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_14BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_13BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_12BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_11BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_10BIT)    || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_9BIT)     || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)     || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_7BIT)     || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_6BIT)     || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
                                                    ((LENGTH) == SPI_CRC_LENGTH_4BIT))

Definition at line 1031 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) ((POLYNOMIAL) >= 0x1UL)

Definition at line 1062 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_32BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_31BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_30BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_29BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_28BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_27BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_26BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_25BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_24BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_23BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_21BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_20BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_19BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_18BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_17BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
                                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
                                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
                                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
                                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
                                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
                                                    ((DATASIZE) == SPI_DATASIZE_4BIT))

Definition at line 949 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)        || \
                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
                                                    ((MODE) == SPI_DIRECTION_1LINE)         || \
                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

Definition at line 932 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 937 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY ( MODE )
Value:
(                         \
                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \
                                                    ((MODE) == SPI_DIRECTION_1LINE) || \
                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY))

Definition at line 944 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY ( MODE )
Value:
(                         \
                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \
                                                    ((MODE) == SPI_DIRECTION_1LINE) || \
                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

Definition at line 939 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIFOTHRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))

Definition at line 980 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                                                    ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 1019 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                                                    ((MODE) == SPI_MODE_MASTER))

Definition at line 929 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT)       || \
                                                    ((NSS) == SPI_NSS_HARD_INPUT) || \
                                                    ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 1003 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( NSSP )
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                                                    ((NSSP) == SPI_NSS_PULSE_DISABLE))

Definition at line 1007 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                                                    ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 1022 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_UNDERRUN_BEHAVIOUR ( MODE )
Value:
(((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
                                                    ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \
                                                    ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))

Definition at line 1068 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_ConfigureUnderrun().

#define IS_SPI_UNDERRUN_DETECTION ( MODE )
Value:
(((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
                                                    ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \
                                                    ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))

Definition at line 1064 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_ConfigureUnderrun().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)

Set the SPI receive-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 927 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 920 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuration register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) SPIEx function:
        (++) HAL_SPIEx_FlushRxFifo()
        (++) HAL_SPIEx_FlushRxFifo()
        (++) HAL_SPIEx_EnableLockConfiguration()
        (++) HAL_SPIEx_ConfigureUnderrun()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | UnderrunDetection,
 |  | uint32_t | UnderrunBehaviour
 | ) |  |

Configure the UNDERRUN condition and behavior of slave transmitter.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
UnderrunDetection | : Detection of underrun condition at slave transmitter This parameter can be a value of SPI Underrun Detection.
UnderrunBehaviour | : Behavior of slave transmitter at underrun condition This parameter can be a value of SPI Underrun Behavior.
Return values:
None

Definition at line 163 of file stm32h7xx_hal_spi_ex.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, assert_param, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_UNDERRUN_BEHAVIOUR, IS_SPI_UNDERRUN_DETECTION, SPI_InitTypeDef::Mode, SPI_MODE_SLAVE, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration ( SPI_HandleTypeDef * hspi )

Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuration register 2 when SPI is enabled.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 115 of file stm32h7xx_hal_spi_ex.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 76 of file stm32h7xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_HIGHEND_FIFO_SIZE, SPI_LOWEND_FIFO_SIZE, and SPI_RX_FIFO_0PACKET.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SRAM Initialization and de_initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to initialize/de-initialize
          the SRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SRAM_DeInit ( SRAM_HandleTypeDef * hsram )

Performs the SRAM device De-initialization sequence.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 228 of file stm32h7xx_hal_sram.c.

References __SRAM_HandleTypeDef::Extended, HAL_SRAM_MspDeInit(), HAL_SRAM_STATE_RESET, __SRAM_HandleTypeDef::Init, __SRAM_HandleTypeDef::Instance, __SRAM_HandleTypeDef::MspDeInitCallback, and __SRAM_HandleTypeDef::State.

__weak void HAL_SRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 293 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init(), and HAL_SRAM_UnRegisterCallback().

__weak void HAL_SRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 309 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init(), and HAL_SRAM_UnRegisterCallback().

HAL_StatusTypeDef HAL_SRAM_Init | ( | SRAM_HandleTypeDef * | hsram,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Performs the SRAM device initialization sequence.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Timing | Pointer to SRAM control timing structure
ExtTiming | Pointer to SRAM extended mode timing structure
Return values:
HAL status

Definition at line 172 of file stm32h7xx_hal_sram.c.

References __SRAM_HandleTypeDef::DmaXferCpltCallback, __SRAM_HandleTypeDef::DmaXferErrorCallback, __SRAM_HandleTypeDef::Extended, HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_MspInit(), HAL_SRAM_STATE_READY, HAL_SRAM_STATE_RESET, __SRAM_HandleTypeDef::Init, __SRAM_HandleTypeDef::Instance, __SRAM_HandleTypeDef::Lock, __SRAM_HandleTypeDef::MspInitCallback, and __SRAM_HandleTypeDef::State.

void HAL_SRAM_MspDeInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP DeInit.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 277 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_DeInit(), and HAL_SRAM_UnRegisterCallback().

void HAL_SRAM_MspInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP Init.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 261 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init(), and HAL_SRAM_UnRegisterCallback().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input Output and memory control functions

Functions
Input Output and memory control functions
SRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
Register a User SRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
Unregister a User SRAM Callback SRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_RegisterDmaCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
Register a User SRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.
void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                  ##### SRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SRAM memory

Function Documentation

void HAL_SRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 293 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init(), and HAL_SRAM_UnRegisterCallback().

void HAL_SRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 309 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init(), and HAL_SRAM_UnRegisterCallback().

HAL_StatusTypeDef HAL_SRAM_Read_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit buffer from SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 439 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit buffer from SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 556 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit buffer from SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 346 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SRAM memory using DMA transfer.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to read start address
pDstBuffer | Pointer to destination buffer
BufferSize | Size of the buffer to read from memory
Return values:
HAL status

Definition at line 649 of file stm32h7xx_hal_sram.c.

References HAL_MDMA_Start_IT(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, __SRAM_HandleTypeDef::hmdma, __SRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SRAM_RegisterCallback | ( | SRAM_HandleTypeDef * | hsram,
 |  | HAL_SRAM_CallbackIDTypeDef | CallbackId,
 |  | pSRAM_CallbackTypeDef | pCallback
 | ) |  |

Register a User SRAM Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsram | : SRAM handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  • HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 740 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_MSP_DEINIT_CB_ID, HAL_SRAM_MSP_INIT_CB_ID, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, HAL_SRAM_STATE_RESET, __SRAM_HandleTypeDef::MspDeInitCallback, __SRAM_HandleTypeDef::MspInitCallback, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback | ( | SRAM_HandleTypeDef * | hsram,
 |  | HAL_SRAM_CallbackIDTypeDef | CallbackId,
 |  | pSRAM_DmaCallbackTypeDef | pCallback
 | ) |  |

Register a User SRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.

Parameters:
hsram | : SRAM handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  • HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 862 of file stm32h7xx_hal_sram.c.

References __SRAM_HandleTypeDef::DmaXferCpltCallback, __SRAM_HandleTypeDef::DmaXferErrorCallback, HAL_SRAM_DMA_XFER_CPLT_CB_ID, HAL_SRAM_DMA_XFER_ERR_CB_ID, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback | ( | SRAM_HandleTypeDef * | hsram,
 |  | HAL_SRAM_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User SRAM Callback SRAM Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hsram : SRAM handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  • HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
  • HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  • HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
Return values:
status

Definition at line 793 of file stm32h7xx_hal_sram.c.

References __SRAM_HandleTypeDef::DmaXferCpltCallback, __SRAM_HandleTypeDef::DmaXferErrorCallback, HAL_SRAM_DMA_XFER_CPLT_CB_ID, HAL_SRAM_DMA_XFER_ERR_CB_ID, HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_MSP_DEINIT_CB_ID, HAL_SRAM_MSP_INIT_CB_ID, HAL_SRAM_MspDeInit(), HAL_SRAM_MspInit(), HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, HAL_SRAM_STATE_RESET, __SRAM_HandleTypeDef::MspDeInitCallback, __SRAM_HandleTypeDef::MspInitCallback, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit buffer to SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 498 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit buffer to SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 603 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit buffer to SRAM memory.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 393 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SRAM memory using DMA transfer.

Parameters:
hsram | pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress | Pointer to write start address
pSrcBuffer | Pointer to source buffer to write
BufferSize | Size of the buffer to write to memory
Return values:
HAL status

Definition at line 697 of file stm32h7xx_hal_sram.c.

References HAL_MDMA_Start_IT(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, __SRAM_HandleTypeDef::hmdma, __SRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Control functions

Functions
Control functions
SRAM Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.

Detailed Description

Control functions.

  ==============================================================================
                        ##### SRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SRAM interface.

Function Documentation

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable ( SRAM_HandleTypeDef * hsram )

Disables dynamically SRAM write operation.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 963 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, __SRAM_HandleTypeDef::Init, __SRAM_HandleTypeDef::Instance, and __SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable ( SRAM_HandleTypeDef * hsram )

Enables dynamically SRAM write operation.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 929 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, __SRAM_HandleTypeDef::Init, __SRAM_HandleTypeDef::Instance, and __SRAM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SRAM_StateTypeDef HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SRAM controller
    and the data flow.

Function Documentation

HAL_SRAM_StateTypeDef HAL_SRAM_GetState ( SRAM_HandleTypeDef * hsram )

Returns the SRAM controller state.

Parameters:
hsram pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL state

Definition at line 1016 of file stm32h7xx_hal_sram.c.

References __SRAM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SRAM Exported Types

Data Structures | Typedefs | Enumerations
SRAM Exported Types
SRAM

Data Structures

struct | __SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Typedefs

typedef struct __SRAM_HandleTypeDef | SRAM_HandleTypeDef
SRAM handle Structure definition.
typedef void(* | pSRAM_CallbackTypeDef )(SRAM_HandleTypeDef *hsram)
HAL SRAM Callback pointer definition.
typedef void(* | pSRAM_DmaCallbackTypeDef )(MDMA_HandleTypeDef *hmdma)

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00U, HAL_SRAM_STATE_READY = 0x01U, HAL_SRAM_STATE_BUSY = 0x02U, HAL_SRAM_STATE_ERROR = 0x03U,
HAL_SRAM_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_SRAM_CallbackIDTypeDef { HAL_SRAM_MSP_INIT_CB_ID = 0x00U, HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U }
HAL SRAM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram)

HAL SRAM Callback pointer definition.

Definition at line 100 of file stm32h7xx_hal_sram.h.

typedef void(* pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma)

Definition at line 101 of file stm32h7xx_hal_sram.h.

typedef struct __SRAM_HandleTypeDef SRAM_HandleTypeDef

SRAM handle Structure definition.

Enumeration Type Documentation

enum HAL_SRAM_CallbackIDTypeDef

HAL SRAM Callback ID enumeration definition.

Enumerator:
HAL_SRAM_MSP_INIT_CB_ID

SRAM MspInit Callback ID

HAL_SRAM_MSP_DEINIT_CB_ID

SRAM MspDeInit Callback ID

HAL_SRAM_DMA_XFER_CPLT_CB_ID

SRAM DMA Xfer Complete Callback ID

HAL_SRAM_DMA_XFER_ERR_CB_ID

SRAM DMA Xfer Complete Callback ID

Definition at line 89 of file stm32h7xx_hal_sram.h.

enum HAL_SRAM_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_SRAM_STATE_RESET

SRAM not yet initialized or disabled

HAL_SRAM_STATE_READY

SRAM initialized and ready for use

HAL_SRAM_STATE_BUSY

SRAM internal process is ongoing

HAL_SRAM_STATE_ERROR

SRAM error state

HAL_SRAM_STATE_PROTECTED

SRAM peripheral NORSRAM device write protected

Definition at line 46 of file stm32h7xx_hal_sram.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SRAM_HandleTypeDef Struct Reference
SRAM Exported Types

SRAM handle Structure definition. More...

#include <stm32h7xx_hal_sram.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_SRAM_StateTypeDef | State
MDMA_HandleTypeDef * hmdma
void(* | MspInitCallback )(struct __SRAM_HandleTypeDef *hsram)
void(* | MspDeInitCallback )(struct __SRAM_HandleTypeDef *hsram)
void(* | DmaXferCpltCallback )(MDMA_HandleTypeDef *hmdma)
void(* | DmaXferErrorCallback )(MDMA_HandleTypeDef *hmdma)

Detailed Description

SRAM handle Structure definition.

Definition at line 60 of file stm32h7xx_hal_sram.h.

Field Documentation

void(* __SRAM_HandleTypeDef::DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma)

SRAM DMA Xfer Complete callback

Definition at line 80 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Init(), HAL_SRAM_RegisterDmaCallback(), and HAL_SRAM_UnRegisterCallback().

void(* __SRAM_HandleTypeDef::DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma)

SRAM DMA Xfer Error callback

Definition at line 81 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Init(), HAL_SRAM_RegisterDmaCallback(), and HAL_SRAM_UnRegisterCallback().

FMC_NORSRAM_EXTENDED_TypeDef* __SRAM_HandleTypeDef::Extended

Extended mode register base address

Definition at line 67 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), and HAL_SRAM_Init().

MDMA_HandleTypeDef* __SRAM_HandleTypeDef::hmdma

Pointer DMA handler

Definition at line 75 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

FMC_NORSRAM_InitTypeDef __SRAM_HandleTypeDef::Init

SRAM device control configuration parameters

Definition at line 69 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* __SRAM_HandleTypeDef::Instance

Register base address

Definition at line 65 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

HAL_LockTypeDef __SRAM_HandleTypeDef::Lock

SRAM locking object

Definition at line 71 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Init().

void(* __SRAM_HandleTypeDef::MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram)

SRAM Msp DeInit callback

Definition at line 79 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_RegisterCallback(), and HAL_SRAM_UnRegisterCallback().

void(* __SRAM_HandleTypeDef::MspInitCallback)(struct __SRAM_HandleTypeDef *hsram)

SRAM Msp Init callback

Definition at line 78 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Init(), HAL_SRAM_RegisterCallback(), and HAL_SRAM_UnRegisterCallback().

__IO HAL_SRAM_StateTypeDef __SRAM_HandleTypeDef::State

SRAM device access state

Definition at line 73 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_GetState(), HAL_SRAM_Init(), HAL_SRAM_Read_16b(), HAL_SRAM_Read_32b(), HAL_SRAM_Read_8b(), HAL_SRAM_Read_DMA(), HAL_SRAM_RegisterCallback(), HAL_SRAM_RegisterDmaCallback(), HAL_SRAM_UnRegisterCallback(), HAL_SRAM_Write_16b(), HAL_SRAM_Write_32b(), HAL_SRAM_Write_8b(), HAL_SRAM_Write_DMA(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sram.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SRAM Exported Macros

Defines
SRAM Exported Macros
SRAM

Defines

#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)
Reset SRAM handle state.

Define Documentation

#define __HAL_SRAM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                             \
                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                             } while(0)

Reset SRAM handle state.

Parameters:
__HANDLE__ SRAM handle
Return values:
None

Definition at line 119 of file stm32h7xx_hal_sram.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization/de-initialization methods

Functions
Initialization/de-initialization methods
SWPMI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_RegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID, pSWPMI_CallbackTypeDef pCallback)
Register a user SWPMI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SWPMI_UnRegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID)
Unregister a user SWPMI callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the SWPMI peripheral.
      (+) De-initialize the SWPMI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 334 of file stm32h7xx_hal_swpmi.c.

References assert_param, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::MspDeInitCallback, and __SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 240 of file stm32h7xx_hal_swpmi.c.

References assert_param, SWPMI_InitTypeDef::BitRate, __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_MspInit(), HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_RxHalfCpltCallback(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_ERROR, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_TxHalfCpltCallback(), __SWPMI_HandleTypeDef::Init, __SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, __SWPMI_HandleTypeDef::Lock, __SWPMI_HandleTypeDef::MspInitCallback, SWPMI_InitTypeDef::RxBufferingMode, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_RDYF, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), SWPMI_InitTypeDef::TxBufferingMode, __SWPMI_HandleTypeDef::TxCpltCallback, __SWPMI_HandleTypeDef::TxHalfCpltCallback, and SWPMI_InitTypeDef::VoltageClass.

__weak void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 401 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit(), and HAL_SWPMI_UnRegisterCallback().

__weak void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 386 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), and HAL_SWPMI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SWPMI_RegisterCallback | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | HAL_SWPMI_CallbackIDTypeDef | CallbackID,
 |  | pSWPMI_CallbackTypeDef | pCallback
 | ) |  |

Register a user SWPMI callback to be used instead of the weak predefined callback.

Parameters:
hswpmi | SWPMI handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SWPMI_ERROR_CB_ID error callback ID.
  • HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 428 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CB_ID, HAL_SWPMI_ERROR_INVALID_CALLBACK, HAL_SWPMI_MSPDEINIT_CB_ID, HAL_SWPMI_MSPINIT_CB_ID, HAL_SWPMI_RX_COMPLETE_CB_ID, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TX_COMPLETE_CB_ID, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID, __SWPMI_HandleTypeDef::MspDeInitCallback, __SWPMI_HandleTypeDef::MspInitCallback, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, __SWPMI_HandleTypeDef::TxCpltCallback, and __SWPMI_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | HAL_SWPMI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user SWPMI callback.

SWPMI callback is redirected to the weak predefined callback.

Parameters:
hswpmi SWPMI handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SWPMI_ERROR_CB_ID error callback ID.
  • HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 520 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CB_ID, HAL_SWPMI_ERROR_INVALID_CALLBACK, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_MspDeInit(), HAL_SWPMI_MSPDEINIT_CB_ID, HAL_SWPMI_MspInit(), HAL_SWPMI_MSPINIT_CB_ID, HAL_SWPMI_RX_COMPLETE_CB_ID, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID, HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_RxHalfCpltCallback(), HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TX_COMPLETE_CB_ID, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID, HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_TxHalfCpltCallback(), __SWPMI_HandleTypeDef::MspDeInitCallback, __SWPMI_HandleTypeDef::MspInitCallback, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, __SWPMI_HandleTypeDef::TxCpltCallback, and __SWPMI_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation methods

Functions
IO operation methods
SWPMI Exported Functions

SWPMI Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.

Detailed Description

SWPMI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation methods #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SWPMI
     data transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non-Blocking mode: The communication is performed using Interrupts
           or DMA. The end of the data processing will be indicated through the
           dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
           the selected DMA stream interrupt handler when using DMA mode.
           The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or receive process.
           The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.

    (#) Blocking mode API's are:
        (++) HAL_SWPMI_Transmit()
        (++) HAL_SWPMI_Receive()

    (#) Non-Blocking mode API's with Interrupt are:
        (++) HAL_SWPMI_Transmit_IT()
        (++) HAL_SWPMI_Receive_IT()
        (++) HAL_SWPMI_IRQHandler()

    (#) Non-Blocking mode API's with DMA are:
        (++) HAL_SWPMI_Transmit_DMA()
        (++) HAL_SWPMI_Receive_DMA()
        (++) HAL_SWPMI_DMAPause()
        (++) HAL_SWPMI_DMAResume()
        (++) HAL_SWPMI_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
        (++) HAL_SWPMI_TxHalfCpltCallback()
        (++) HAL_SWPMI_TxCpltCallback()
        (++) HAL_SWPMI_RxHalfCpltCallback()
        (++) HAL_SWPMI_RxCpltCallback()
        (++) HAL_SWPMI_ErrorCallback()

    (#) The capability to launch the above IO operations in loopback mode for
        user application verification:
        (++) HAL_SWPMI_EnableLoopback()
        (++) HAL_SWPMI_DisableLoopback()

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 1246 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 1171 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, and __SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 1218 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 766 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1087 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pRxBuffPtr, __SWPMI_HandleTypeDef::RxXferSize, __SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), SWPMI_IT_RXBERIE, SWPMI_IT_RXOVRIE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 937 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pRxBuffPtr, __SWPMI_HandleTypeDef::RxXferCount, __SWPMI_HandleTypeDef::RxXferSize, __SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 655 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_TXBEF_TIMEOUT, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1000 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pTxBuffPtr, __SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_IT_TXUNRIE, __SWPMI_HandleTypeDef::TxXferCount, __SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 870 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pTxBuffPtr, __SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, __SWPMI_HandleTypeDef::TxXferCount, and __SWPMI_HandleTypeDef::TxXferSize.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI IRQ handler and callbacks

Functions
SWPMI IRQ handler and callbacks
SWPMI Exported Functions

SWPMI IRQ handler. More...

Functions

void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.

Detailed Description

SWPMI IRQ handler.

  ==============================================================================
                      ##### SWPMI IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides SWPMI IRQ handler and callback functions called within
      the IRQ handler.

Function Documentation

__weak void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1523 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1291 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_DMAAbortOnError(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

__weak void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1493 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

__weak void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1508 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMARxHalfCplt().

__weak void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1463 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

__weak void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1478 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMATxHalfCplt().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control methods

Functions
Peripheral Control methods
SWPMI Exported Functions

SWPMI control functions. More...

Functions

HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI control functions.

 ===============================================================================
                      ##### Peripheral Control methods #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SWPMI.
     (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
     (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral

Function Documentation

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1569 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi SWPMI handle
Return values:
HAL state

Definition at line 1557 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Exported Functions

Modules | Functions
SWPMI Exported Functions
SWPMI

Modules

Initialization/de-initialization methods

Initialization and Configuration functions.

IO operation methods

SWPMI Transmit/Receive functions.

SWPMI IRQ handler and callbacks

SWPMI IRQ handler.

Peripheral Control methods

SWPMI control functions.

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_RegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID, pSWPMI_CallbackTypeDef pCallback)
Register a user SWPMI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SWPMI_UnRegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID)
Unregister a user SWPMI callback.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 334 of file stm32h7xx_hal_swpmi.c.

References assert_param, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::MspDeInitCallback, and __SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 1246 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 1171 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, and __SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 1218 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::Instance.

void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1523 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1569 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi SWPMI handle
Return values:
HAL state

Definition at line 1557 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi SWPMI handle
Return values:
HAL status

Definition at line 240 of file stm32h7xx_hal_swpmi.c.

References assert_param, SWPMI_InitTypeDef::BitRate, __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_MspInit(), HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_RxHalfCpltCallback(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_ERROR, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_TxHalfCpltCallback(), __SWPMI_HandleTypeDef::Init, __SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, __SWPMI_HandleTypeDef::Lock, __SWPMI_HandleTypeDef::MspInitCallback, SWPMI_InitTypeDef::RxBufferingMode, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_RDYF, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), SWPMI_InitTypeDef::TxBufferingMode, __SWPMI_HandleTypeDef::TxCpltCallback, __SWPMI_HandleTypeDef::TxHalfCpltCallback, and SWPMI_InitTypeDef::VoltageClass.

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1291 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_DMAAbortOnError(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 401 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit(), and HAL_SWPMI_UnRegisterCallback().

void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 386 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), and HAL_SWPMI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 766 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1087 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmarx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pRxBuffPtr, __SWPMI_HandleTypeDef::RxXferSize, __SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), SWPMI_IT_RXBERIE, SWPMI_IT_RXOVRIE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 937 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pRxBuffPtr, __SWPMI_HandleTypeDef::RxXferCount, __SWPMI_HandleTypeDef::RxXferSize, __SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

HAL_StatusTypeDef HAL_SWPMI_RegisterCallback | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | HAL_SWPMI_CallbackIDTypeDef | CallbackID,
 |  | pSWPMI_CallbackTypeDef | pCallback
 | ) |  |

Register a user SWPMI callback to be used instead of the weak predefined callback.

Parameters:
hswpmi | SWPMI handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SWPMI_ERROR_CB_ID error callback ID.
  • HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 428 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CB_ID, HAL_SWPMI_ERROR_INVALID_CALLBACK, HAL_SWPMI_MSPDEINIT_CB_ID, HAL_SWPMI_MSPINIT_CB_ID, HAL_SWPMI_RX_COMPLETE_CB_ID, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TX_COMPLETE_CB_ID, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID, __SWPMI_HandleTypeDef::MspDeInitCallback, __SWPMI_HandleTypeDef::MspInitCallback, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, __SWPMI_HandleTypeDef::TxCpltCallback, and __SWPMI_HandleTypeDef::TxHalfCpltCallback.

void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1493 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1508 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 655 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_TXBEF_TIMEOUT, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi | SWPMI handle
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1000 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::hdmatx, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pTxBuffPtr, __SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_IT_TXUNRIE, __SWPMI_HandleTypeDef::TxXferCount, __SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi | pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 870 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pTxBuffPtr, __SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, __SWPMI_HandleTypeDef::TxXferCount, and __SWPMI_HandleTypeDef::TxXferSize.

void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1463 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1478 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMATxHalfCplt().

HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | HAL_SWPMI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user SWPMI callback.

SWPMI callback is redirected to the weak predefined callback.

Parameters:
hswpmi SWPMI handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SWPMI_ERROR_CB_ID error callback ID.
  • HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 520 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CB_ID, HAL_SWPMI_ERROR_INVALID_CALLBACK, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_MspDeInit(), HAL_SWPMI_MSPDEINIT_CB_ID, HAL_SWPMI_MspInit(), HAL_SWPMI_MSPINIT_CB_ID, HAL_SWPMI_RX_COMPLETE_CB_ID, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID, HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_RxHalfCpltCallback(), HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, HAL_SWPMI_TX_COMPLETE_CB_ID, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID, HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_TxHalfCpltCallback(), __SWPMI_HandleTypeDef::MspDeInitCallback, __SWPMI_HandleTypeDef::MspInitCallback, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxHalfCpltCallback, __SWPMI_HandleTypeDef::State, __SWPMI_HandleTypeDef::TxCpltCallback, and __SWPMI_HandleTypeDef::TxHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Functions

Functions
SWPMI Private Functions
SWPMI

Functions

static void | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static void | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static void | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static void | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static void | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static void | SWPMI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication abort callback.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.

Function Documentation

static void SWPMI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI communication abort callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1889 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::RxXferCount, __SWPMI_HandleTypeDef::State, and __SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1867 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::RxXferCount, __SWPMI_HandleTypeDef::State, and __SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1816 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxXferCount, and __SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process half complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1851 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxHalfCpltCallback(), and __SWPMI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1734 of file stm32h7xx_hal_swpmi.c.

References __SWPMI_HandleTypeDef::ErrorCallback, __SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_TXBEF_TIMEOUT, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), __SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), __SWPMI_HandleTypeDef::TxCpltCallback, and __SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process half complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 1799 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_TxHalfCpltCallback(), and __SWPMI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SWPMI_Transmit_DMA().

static void SWPMI_EndReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up reception in non-blocking mode.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1684 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_EndTransmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1623 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and __SWPMI_HandleTypeDef::TxCpltCallback.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_EndTransmitReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission and reception in non-blocking mode.

Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1707 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, and SWPMI_IT_TCIE.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_Receive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Receive an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1653 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pRxBuffPtr, __SWPMI_HandleTypeDef::RxCpltCallback, __SWPMI_HandleTypeDef::RxXferCount, and __SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_Transmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Transmit an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
Parameters:
hswpmi SWPMI handle
Return values:
None

Definition at line 1594 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, __SWPMI_HandleTypeDef::Instance, __SWPMI_HandleTypeDef::pTxBuffPtr, __SWPMI_HandleTypeDef::State, SWPMI_IT_TIE, SWPMI_IT_TXUNRIE, and __SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t | Flag,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SWPMI Communication Timeout.

Parameters:
hswpmi | SWPMI handle
Flag,: specifies the SWPMI flag to check.
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 1913 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_READY, __SWPMI_HandleTypeDef::Instance, and __SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_Transmit(), and SWPMI_DMATransmitCplt().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Exported Types

Data Structures | Typedefs | Enumerations
SWPMI Exported Types
SWPMI

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | __SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Typedefs

typedef struct
__SWPMI_HandleTypeDef 		SWPMI_HandleTypeDef
SWPMI handle Structure definition.
typedef void(* | pSWPMI_CallbackTypeDef )(SWPMI_HandleTypeDef *hswpmi)
SWPMI callback pointer definition.

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...
enum HAL_SWPMI_CallbackIDTypeDef {
HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SWPMI_ERROR_CB_ID = 0x04U, HAL_SWPMI_MSPINIT_CB_ID = 0x05U, HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U
}
SWPMI callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi)

SWPMI callback pointer definition.

Definition at line 148 of file stm32h7xx_hal_swpmi.h.

typedef struct __SWPMI_HandleTypeDef SWPMI_HandleTypeDef

SWPMI handle Structure definition.

Enumeration Type Documentation

enum HAL_SWPMI_CallbackIDTypeDef

SWPMI callback ID enumeration definition.

Enumerator:
HAL_SWPMI_RX_COMPLETE_CB_ID

SWPMI receive complete callback ID

HAL_SWPMI_RX_HALFCOMPLETE_CB_ID

SWPMI receive half complete callback ID

HAL_SWPMI_TX_COMPLETE_CB_ID

SWPMI transmit complete callback ID

HAL_SWPMI_TX_HALFCOMPLETE_CB_ID

SWPMI transmit half complete callback ID

HAL_SWPMI_ERROR_CB_ID

SWPMI error callback ID

HAL_SWPMI_MSPINIT_CB_ID

SWPMI MSP init callback ID

HAL_SWPMI_MSPDEINIT_CB_ID

SWPMI MSP de-init callback ID

Definition at line 134 of file stm32h7xx_hal_swpmi.h.

enum HAL_SWPMI_StateTypeDef

HAL SWPMI State structures definition.

Enumerator:
HAL_SWPMI_STATE_RESET

Peripheral Reset state

HAL_SWPMI_STATE_READY

Peripheral Initialized and ready for use

HAL_SWPMI_STATE_BUSY

an internal process is ongoing

HAL_SWPMI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SWPMI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SWPMI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SWPMI_STATE_TIMEOUT

Timeout state

HAL_SWPMI_STATE_ERROR

Error

Definition at line 71 of file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SWPMI_InitTypeDef Struct Reference
SWPMI Exported Types

SWPMI Init Structure definition. More...

#include <stm32h7xx_hal_swpmi.h>

Data Fields

uint32_t | VoltageClass
uint32_t | BitRate
uint32_t | TxBufferingMode
uint32_t | RxBufferingMode

Detailed Description

SWPMI Init Structure definition.

Definition at line 48 of file stm32h7xx_hal_swpmi.h.

Field Documentation

uint32_t SWPMI_InitTypeDef::BitRate

Specifies the SWPMI Bitrate. This parameter must be a number between 0 and 255U. The Bitrate is computed using the following formula: SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)

Definition at line 53 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::RxBufferingMode

Specifies the reception buffering mode. This parameter can be a value of SWPMI Rx Buffering Mode

Definition at line 62 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::TxBufferingMode

Specifies the transmission buffering mode. This parameter can be a value of SWPMI Tx Buffering Mode

Definition at line 59 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::VoltageClass

Specifies the SWP Voltage Class. This parameter can be a value of SWPMI Voltage Class

Definition at line 50 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_swpmi.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __SWPMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SWPMI_HandleTypeDef Struct Reference
SWPMI Exported Types

SWPMI handle Structure definition. More...

#include <stm32h7xx_hal_swpmi.h>

Data Fields

SWPMI_TypeDef * | Instance
SWPMI_InitTypeDef Init
uint32_t * | pTxBuffPtr
uint32_t | TxXferSize
uint32_t | TxXferCount
uint32_t * | pRxBuffPtr
uint32_t | RxXferSize
uint32_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SWPMI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | RxCpltCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | RxHalfCpltCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | TxCpltCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | TxHalfCpltCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | ErrorCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | MspInitCallback )(struct __SWPMI_HandleTypeDef *hswpmi)
void(* | MspDeInitCallback )(struct __SWPMI_HandleTypeDef *hswpmi)

Detailed Description

SWPMI handle Structure definition.

Definition at line 87 of file stm32h7xx_hal_swpmi.h.

Field Documentation

void(* __SWPMI_HandleTypeDef::ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI error callback

Definition at line 123 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

__IO uint32_t __SWPMI_HandleTypeDef::ErrorCode

SWPMI Error code

Definition at line 116 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DMAStop(), HAL_SWPMI_GetError(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

DMA_HandleTypeDef* __SWPMI_HandleTypeDef::hdmarx

SWPMI Rx DMA Handle parameters

Definition at line 110 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Receive_DMA().

DMA_HandleTypeDef* __SWPMI_HandleTypeDef::hdmatx

SWPMI Tx DMA Handle parameters

Definition at line 108 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit_DMA().

SWPMI_InitTypeDef __SWPMI_HandleTypeDef::Init

SWPMI communication parameters

Definition at line 94 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

SWPMI_TypeDef* __SWPMI_HandleTypeDef::Instance

SWPMI registers base address

Definition at line 92 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DisableLoopback(), HAL_SWPMI_DMAStop(), HAL_SWPMI_EnableLoopback(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_LockTypeDef __SWPMI_HandleTypeDef::Lock

SWPMI object

Definition at line 112 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

void(* __SWPMI_HandleTypeDef::MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI MSP de-init callback

Definition at line 125 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_RegisterCallback(), and HAL_SWPMI_UnRegisterCallback().

void(* __SWPMI_HandleTypeDef::MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI MSP init callback

Definition at line 124 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_RegisterCallback(), and HAL_SWPMI_UnRegisterCallback().

uint32_t* __SWPMI_HandleTypeDef::pRxBuffPtr

Pointer to SWPMI Rx transfer Buffer

Definition at line 102 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_Receive_IT().

uint32_t* __SWPMI_HandleTypeDef::pTxBuffPtr

Pointer to SWPMI Tx transfer Buffer

Definition at line 96 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), and SWPMI_Transmit_IT().

void(* __SWPMI_HandleTypeDef::RxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI receive complete callback

Definition at line 119 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

void(* __SWPMI_HandleTypeDef::RxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI receive half complete callback

Definition at line 120 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMARxHalfCplt().

uint32_t __SWPMI_HandleTypeDef::RxXferCount

SWPMI Rx Transfer Counter

Definition at line 106 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_IT(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

uint32_t __SWPMI_HandleTypeDef::RxXferSize

SWPMI Rx Transfer size

Definition at line 104 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Receive_IT().

__IO HAL_SWPMI_StateTypeDef __SWPMI_HandleTypeDef::State

SWPMI communication state

Definition at line 114 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DMAStop(), HAL_SWPMI_GetState(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

void(* __SWPMI_HandleTypeDef::TxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI transmit complete callback

Definition at line 121 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_UnRegisterCallback(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

void(* __SWPMI_HandleTypeDef::TxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi)

SWPMI transmit half complete callback

Definition at line 122 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_RegisterCallback(), HAL_SWPMI_UnRegisterCallback(), and SWPMI_DMATxHalfCplt().

uint32_t __SWPMI_HandleTypeDef::TxXferCount

SWPMI Tx Transfer Counter

Definition at line 100 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMATransmitCplt(), and SWPMI_Transmit_IT().

uint32_t __SWPMI_HandleTypeDef::TxXferSize

SWPMI Tx Transfer size

Definition at line 98 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_swpmi.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Error Code Bitmap

Defines
SWPMI Error Code Bitmap
SWPMI Exported Constants

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)
#define | HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040)
#define | HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080)
#define | HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100)

Define Documentation

#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)

frame error

Definition at line 165 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 168 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), and SWPMI_DMAError().

#define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100)

Invalid callback error

Definition at line 173 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_RegisterCallback(), and HAL_SWPMI_UnRegisterCallback().

#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 164 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)

Overrun error

Definition at line 166 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020)

Transfer timeout

Definition at line 169 of file stm32h7xx_hal_swpmi.h.

#define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080)

Transceiver not ready

Definition at line 171 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040)

End Tx buffer timeout

Definition at line 170 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit(), and SWPMI_DMATransmitCplt().

#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)

Underrun error

Definition at line 167 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Voltage Class

Defines
SWPMI Voltage Class
SWPMI Exported Constants

Defines

#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Define Documentation

#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Definition at line 183 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)

Definition at line 182 of file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Tx Buffering Mode

Defines
SWPMI Tx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Define Documentation

#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Definition at line 193 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 191 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 192 of file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Rx Buffering Mode

Defines
SWPMI Rx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Define Documentation

#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Definition at line 203 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 201 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 202 of file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Status Flags

Defines
SWPMI Status Flags
SWPMI Exported Constants

Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define | SWPMI_FLAG_RDYF SWPMI_ISR_RDYF

Detailed Description

Elements values convention: 0xXXXXXXXX.

  • 0xXXXXXXXX : Flag mask in the ISR register

Define Documentation

#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF

Definition at line 223 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_RDYF SWPMI_ISR_RDYF

Definition at line 224 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF

Definition at line 215 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF

Definition at line 213 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), and SWPMI_EndReceive_IT().

#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE

Definition at line 218 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Receive().

#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF

Definition at line 216 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_SRF SWPMI_ISR_SRF

Definition at line 221 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP

Definition at line 222 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_TCF SWPMI_ISR_TCF

Definition at line 220 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF

Definition at line 214 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

#define SWPMI_FLAG_TXE SWPMI_ISR_TXE

Definition at line 219 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF

Definition at line 217 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Interrupts Definition

Defines
SWPMI Interrupts Definition
SWPMI Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SWPMI_IT_RDYIE SWPMI_IER_RDYIE
#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the IER register

Define Documentation

#define SWPMI_IT_RDYIE SWPMI_IER_RDYIE

Definition at line 234 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_IT_RIE SWPMI_IER_RIE

Definition at line 238 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE

Definition at line 241 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Definition at line 243 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE

Definition at line 240 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_SRIE SWPMI_IER_SRIE

Definition at line 235 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive().

#define SWPMI_IT_TCIE SWPMI_IER_TCIE

Definition at line 236 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_IT_TIE SWPMI_IER_TIE

Definition at line 237 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE

Definition at line 242 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmit_IT().

#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE

Definition at line 239 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Exported Macros

Defines
SWPMI Exported Macros
SWPMI

Defines

#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Enable the SWPMI transceiver.
#define | __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Disable the SWPMI transceiver.
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.

Define Documentation

#define __HAL_SWPMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))

Clear the specified SWPMI ISR flag.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF Receive buffer full flag.
  • SWPMI_FLAG_TXBEF Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF Transmit underrun error flag.
  • SWPMI_FLAG_TCF Transfer complete flag.
  • SWPMI_FLAG_SRF Slave resume flag.
  • SWPMI_FLAG_RDYF Transceiver ready flag.
Return values:
None

Definition at line 333 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Disable the SWPMI peripheral.

Parameters:
__HANDLE__ SWPMI handle
Return values:
None

Definition at line 283 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Disable the specified SWPMI interrupt.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__INTERRUPT__ specifies the SWPMI interrupt source to disable. This parameter can be one of the following values:
  • SWPMI_IT_RDYIE Transceiver ready interrupt.
  • SWPMI_IT_SRIE Slave resume interrupt.
  • SWPMI_IT_TCIE Transmit complete interrupt.
  • SWPMI_IT_TIE Transmit interrupt.
  • SWPMI_IT_RIE Receive interrupt.
  • SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE Receive buffer full interrupt.
Return values:
None

Definition at line 369 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Enable the SWPMI peripheral.

Parameters:
__HANDLE__ SWPMI handle
Return values:
None

Definition at line 276 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Enable the specified SWPMI interrupt.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__INTERRUPT__ specifies the SWPMI interrupt source to enable. This parameter can be one of the following values:
  • SWPMI_IT_RDYIE Transceiver ready interrupt.
  • SWPMI_IT_SRIE Slave resume interrupt.
  • SWPMI_IT_TCIE Transmit complete interrupt.
  • SWPMI_IT_TIE Transmit interrupt.
  • SWPMI_IT_RIE Receive interrupt.
  • SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE Receive buffer full interrupt.
Return values:
None

Definition at line 351 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

#define __HAL_SWPMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified SWPMI flag is set or not.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF Receive buffer full flag.
  • SWPMI_FLAG_TXBEF Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF Transmit underrun error flag.
  • SWPMI_FLAG_RXNE Receive data register not empty.
  • SWPMI_FLAG_TXE Transmit data register empty.
  • SWPMI_FLAG_TCF Transfer complete flag.
  • SWPMI_FLAG_SRF Slave resume flag.
  • SWPMI_FLAG_SUSP SUSPEND flag.
  • SWPMI_FLAG_DEACTF DEACTIVATED flag.
  • SWPMI_FLAG_RDYF Transceiver ready flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 317 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))

Check whether the specified SWPMI interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__IT__ specifies the SWPMI interrupt to check. This parameter can be one of the following values:
  • SWPMI_IT_RDYIE Transceiver ready interrupt.
  • SWPMI_IT_SRIE Slave resume interrupt.
  • SWPMI_IT_TCIE Transmit complete interrupt.
  • SWPMI_IT_TIE Transmit interrupt.
  • SWPMI_IT_RIE Receive interrupt.
  • SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 387 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)

Check whether the specified SWPMI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
__IT__ specifies the SWPMI interrupt source to check. This parameter can be one of the following values:
  • SWPMI_IT_RDYIE Transceiver ready interrupt.
  • SWPMI_IT_SRIE Slave resume interrupt.
  • SWPMI_IT_TCIE Transmit complete interrupt.
  • SWPMI_IT_TIE Transmit interrupt.
  • SWPMI_IT_RIE Receive interrupt.
  • SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 405 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                     (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \
                                                     (__HANDLE__)->MspInitCallback = NULL;        \
                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \
                                                   } while(0)

Reset SWPMI handle state.

Parameters:
__HANDLE__ specifies the SWPMI Handle.
Return values:
None

Definition at line 262 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_TRANSCEIVER_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

Disable the SWPMI transceiver.

Parameters:
__HANDLE__ SWPMI handle
Return values:
None

Definition at line 297 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_TRANSCEIVER_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

Enable the SWPMI transceiver.

Parameters:
__HANDLE__ SWPMI handle
Return values:
None

Definition at line 290 of file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Types

SWPMI Private Types
SWPMI
Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Variables

SWPMI Private Variables
SWPMI
Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Constants

Defines
SWPMI Private Constants
SWPMI

Defines

#define | SWPMI_TIMEOUT_VALUE 22000U /* End of transmission timeout */
#define | SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE 2000U /* Transceiver ready timeout */

Define Documentation

#define SWPMI_TIMEOUT_VALUE 22000U /* End of transmission timeout */

Definition at line 191 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt().

#define SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE 2000U /* Transceiver ready timeout */

Definition at line 192 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Macros

Defines
SWPMI Private Macros
SWPMI

Defines

#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Define Documentation

#define IS_SWPMI_BITRATE_VALUE ( __VALUE__ ) (((__VALUE__) <= 255U))

Definition at line 491 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_RX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))

Definition at line 498 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_TX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))

Definition at line 494 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_VOLTAGE_CLASS ( __CLASS__ )
Value:
(((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))

Definition at line 488 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Time Base functions

Functions
TIM Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 320 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Base_MspDeInitCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 268 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, __TIM_HandleTypeDef::Base_MspInitCallback, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 371 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 356 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 387 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | TIM Base handle
pData | The source Buffer address.
Length | The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 486 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 439 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 416 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 545 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 465 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Output Compare functions

Functions
TIM Output Compare functions
TIM Exported Functions

TIM Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

TIM Output Compare functions.

  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 652 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 600 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 703 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 688 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 726 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 938 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 798 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 766 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1080 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 870 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM PWM functions

Functions
TIM PWM functions
TIM Exported Functions

TIM PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

TIM PWM functions.

  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the TIM PWM.
    (+) Stop the TIM PWM.
    (+) Start the TIM PWM and enable interrupt.
    (+) Stop the TIM PWM and disable interrupt.
    (+) Start the TIM PWM and enable DMA transfer.
    (+) Stop the TIM PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1229 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::PWM_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1177 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1265 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1303 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | TIM PWM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1517 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1378 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1343 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1658 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1449 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Input Capture functions

Functions
TIM Input Capture functions
TIM Exported Functions

TIM Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

TIM Input Capture functions.

  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture.
   (+) Stop the TIM Input Capture.
   (+) Start the TIM Input Capture and enable interrupt.
   (+) Stop the TIM Input Capture and disable interrupt.
   (+) Start the TIM Input Capture and enable DMA transfer.
   (+) Stop the TIM Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1807 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1755 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1858 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim TIM Input Capture handle
Return values:
None

Definition at line 1843 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1879 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2064 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1937 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1911 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2199 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2002 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM One Pulse functions

Functions
TIM One Pulse functions
TIM Exported Functions

TIM One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

TIM One Pulse functions.

  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the TIM One Pulse.
    (+) Stop the TIM One Pulse.
    (+) Start the TIM One Pulse and enable interrupt.
    (+) Stop the TIM One Pulse and disable interrupt.
    (+) Start the TIM One Pulse and enable DMA transfer.
    (+) Stop the TIM One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim TIM One Pulse handle
Return values:
HAL status

Definition at line 2353 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
Parameters:
htim TIM One Pulse handle
OnePulseMode Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 2294 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2404 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2389 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2423 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2495 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2459 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2537 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Encoder functions

Functions
TIM Encoder functions
TIM Exported Functions

TIM Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

TIM Encoder functions.

  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the TIM Encoder.
    (+) Stop the TIM Encoder.
    (+) Start the TIM Encoder and enable interrupt.
    (+) Stop the TIM Encoder and disable interrupt.
    (+) Start the TIM Encoder and enable DMA transfer.
    (+) Stop the TIM Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL status

Definition at line 2712 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
Encoder mode and External clock mode 2 are not compatible and must not be selected together Ex: A call for HAL_TIM_Encoder_Init will erase the settings of HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2607 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::Encoder_MspInitCallback, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_ENCODERINPUT_POLARITY, IS_TIM_IC_FILTER, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 2763 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 2748 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2783 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1 | The destination Buffer address for IC1.
pData2 | The destination Buffer address for IC2.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2977 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2873 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2827 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3112 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, and TIM_DMA_ID_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2923 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

TIM IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

TIM IRQ handler management.

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3178 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_CLEAR_FLAG, __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, TIM_IT_UPDATE, and __TIM_HandleTypeDef::TriggerCallback.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Peripheral Control functions

Functions
TIM Peripheral Control functions
TIM Exported Functions

TIM Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

TIM Peripheral Control functions.

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | TIM handle
sClockSourceConfig | pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 4726 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, __TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_ITR4, TIM_CLOCKSOURCE_ITR5, TIM_CLOCKSOURCE_ITR6, TIM_CLOCKSOURCE_ITR7, TIM_CLOCKSOURCE_ITR8, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | TIM handle
sClearInputConfig | pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
HAL status

Definition at line 4574 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTPRESCALER_DIV1, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim TIM handle.
TI1_Selection Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4883 of file stm32h7xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 4283 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, __TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_ReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 3955 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, __TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_WriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4230 of file stm32h7xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 4456 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 3902 of file stm32h7xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiWriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 4127 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim TIM handle
EventSource specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Note:
Basic timers can only generate an update event.
TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant only for timer instances supporting break input(s).
Return values:
HAL status

Definition at line 4535 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | TIM IC handle
sConfig | TIM Input Capture configuration structure
Channel TIM Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3508 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM Output Compare handle
sConfig | TIM Output Compare configuration structure
Channel TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3408 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | TIM One Pulse handle
sConfig | TIM One Pulse configuration structure
OutputChannel TIM output channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel TIM input Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Note:
To output a waveform with a minimum delay user can enable the fast mode by calling the __HAL_TIM_ENABLE_OCxFAST macro. Then CCx output is forced in response to the edge detection on TIx input, without taking in account the comparison.
Return values:
HAL status

Definition at line 3756 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM PWM handle
sConfig | TIM PWM configuration structure
Channel TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3607 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim TIM handle.
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4998 of file stm32h7xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4915 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4955 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5217 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAError(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5127 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureHalfCpltCallback ( TIM_HandleTypeDef * htim )

Input Capture half complete callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5142 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non-blocking mode.

Parameters:
htim TIM OC handle
Return values:
None

Definition at line 5112 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5082 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedHalfCpltCallback ( TIM_HandleTypeDef * htim )

Period elapsed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5097 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5157 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedHalfCpltCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5172 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_RegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID,
 |  | pTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User TIM callback to be used instead of the weak predefined callback.

Parameters:
htim | tim handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 5264 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5187 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void HAL_TIM_TriggerHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5202 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_UnRegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Parameters:
htim tim handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
Return values:
status

Definition at line 5512 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_Base_MspInit(), HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_Encoder_MspInit(), HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_ErrorCallback(), HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_IC_MspDeInit(), HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MspInit(), HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_OC_MspDeInit(), HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MspInit(), HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_OnePulse_MspInit(), HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_MspDeInit(), HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MspInit(), HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_HallSensor_MspDeInit(), HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Peripheral State functions

Functions
TIM Peripheral State functions
TIM Exported Functions

TIM Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.

Detailed Description

TIM Peripheral State functions.

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim TIM Base handle
Return values:
HAL state

Definition at line 5744 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL state

Definition at line 5794 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim TIM IC handle
Return values:
HAL state

Definition at line 5774 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC handle state.

Parameters:
htim TIM Output Compare handle
Return values:
HAL state

Definition at line 5754 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim TIM OPM handle
Return values:
HAL state

Definition at line 5784 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim TIM handle
Return values:
HAL state

Definition at line 5764 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | TIM peripheral
Structure | TIM Base configuration structure
Return values:
None

Definition at line 6071 of file stm32h7xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
ChannelState | specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
Return values:
None

Definition at line 6991 of file stm32h7xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5916 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMACaptureHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5957 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5834 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMADelayPulseHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5875 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5816 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5998 of file stm32h7xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::PeriodElapsedCallback, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMAPeriodElapsedHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6016 of file stm32h7xx_hal_tim.c.

References HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6034 of file stm32h7xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), __TIM_HandleTypeDef::State, and __TIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6052 of file stm32h7xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerHalfCpltCallback(), __TIM_HandleTypeDef::State, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 6959 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
  • TIM_TS_ITR4: Internal Trigger 4 (*)
  • TIM_TS_ITR5: Internal Trigger 5
  • TIM_TS_ITR6: Internal Trigger 6
  • TIM_TS_ITR7: Internal Trigger 7
  • TIM_TS_ITR8: Internal Trigger 8 (*)
  • TIM_TS_ITR9: Internal Trigger 9 (*)
  • TIM_TS_ITR10: Internal Trigger 10 (*)
  • TIM_TS_ITR11: Internal Trigger 11 (*)
  • TIM_TS_ITR12: Internal Trigger 12 (*)
  • TIM_TS_ITR13: Internal Trigger 13 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 6929 of file stm32h7xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6119 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Timer Output Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6194 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6270 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6344 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 5 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6404 of file stm32h7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 6 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6457 of file stm32h7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_ResetCallback ( TIM_HandleTypeDef * htim )

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
htim pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 7015 of file stm32h7xx_hal_tim.c.

References __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Slave Timer configuration function.

Parameters:
htim | TIM handle
sSlaveConfig | Slave timer configuration
Return values:
None

Definition at line 6511 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_SLAVEMODE_GATED, TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR10, TIM_TS_ITR11, TIM_TS_ITR12, TIM_TS_ITR13, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_ITR4, TIM_TS_ITR5, TIM_TS_ITR6, TIM_TS_ITR7, TIM_TS_ITR8, TIM_TS_ITR9, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 6699 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6652 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 6782 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6742 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 6825 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 6873 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Types

Data Structures | Typedefs | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim)

HAL TIM Callback pointer definition.

pointer to the TIM callback function

Definition at line 410 of file stm32h7xx_hal_tim.h.

typedef struct __TIM_HandleTypeDef TIM_HandleTypeDef

TIM Time Base Handle Structure definition.

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 310 of file stm32h7xx_hal_tim.h.

enum HAL_TIM_CallbackIDTypeDef

HAL TIM Callback ID enumeration definition.

Enumerator:
HAL_TIM_BASE_MSPINIT_CB_ID

TIM Base MspInit Callback ID

HAL_TIM_BASE_MSPDEINIT_CB_ID

TIM Base MspDeInit Callback ID

HAL_TIM_IC_MSPINIT_CB_ID

TIM IC MspInit Callback ID

HAL_TIM_IC_MSPDEINIT_CB_ID

TIM IC MspDeInit Callback ID

HAL_TIM_OC_MSPINIT_CB_ID

TIM OC MspInit Callback ID

HAL_TIM_OC_MSPDEINIT_CB_ID

TIM OC MspDeInit Callback ID

HAL_TIM_PWM_MSPINIT_CB_ID

TIM PWM MspInit Callback ID

HAL_TIM_PWM_MSPDEINIT_CB_ID

TIM PWM MspDeInit Callback ID

HAL_TIM_ONE_PULSE_MSPINIT_CB_ID

TIM One Pulse MspInit Callback ID

HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID

TIM One Pulse MspDeInit Callback ID

HAL_TIM_ENCODER_MSPINIT_CB_ID

TIM Encoder MspInit Callback ID

HAL_TIM_ENCODER_MSPDEINIT_CB_ID

TIM Encoder MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_PERIOD_ELAPSED_CB_ID

TIM Period Elapsed Callback ID

HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID

TIM Period Elapsed half complete Callback ID

HAL_TIM_TRIGGER_CB_ID

TIM Trigger Callback ID

HAL_TIM_TRIGGER_HALF_CB_ID

TIM Trigger half complete Callback ID

HAL_TIM_IC_CAPTURE_CB_ID

TIM Input Capture Callback ID

HAL_TIM_IC_CAPTURE_HALF_CB_ID

TIM Input Capture half complete Callback ID

HAL_TIM_OC_DELAY_ELAPSED_CB_ID

TIM Output Compare Delay Elapsed Callback ID

HAL_TIM_PWM_PULSE_FINISHED_CB_ID

TIM PWM Pulse Finished Callback ID

HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID

TIM PWM Pulse Finished half complete Callback ID

HAL_TIM_ERROR_CB_ID

TIM Error Callback ID

HAL_TIM_COMMUTATION_CB_ID

TIM Commutation Callback ID

HAL_TIM_COMMUTATION_HALF_CB_ID

TIM Commutation half complete Callback ID

HAL_TIM_BREAK_CB_ID

TIM Break Callback ID

HAL_TIM_BREAK2_CB_ID

TIM Break2 Callback ID

Definition at line 374 of file stm32h7xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 298 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 47 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 71 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 59 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 52 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 55 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 49 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 62 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 78 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 93 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 98 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 80 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 102 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 89 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 86 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 83 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 110 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 139 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 133 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 136 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 125 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 112 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 129 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 121 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 118 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 115 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 146 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 157 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 148 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 154 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 151 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 164 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 166 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 178 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 169 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 175 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 172 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 190 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 181 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 187 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 184 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 197 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 205 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 201 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 203 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 199 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 212 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 222 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 218 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off

Definition at line 220 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Clear Input Source

Definition at line 216 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 214 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 231 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 233 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 235 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Note:
When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode.

Definition at line 237 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 249 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 253 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 251 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 259 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 255 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 257 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 269 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 291 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 289 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity This parameter can be a value of TIM Break Input 2 Polarity

Definition at line 287 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State This parameter can be a value of TIM Break input 2 Enable

Definition at line 285 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 283 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 281 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable

Definition at line 279 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 277 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock level

Definition at line 275 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 273 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 271 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State
void(* | Base_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Base_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_DelayElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | ErrorCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | BreakCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Break2Callback )(struct __TIM_HandleTypeDef *htim)

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 325 of file stm32h7xx_hal_tim.h.

Field Documentation

void(* __TIM_HandleTypeDef::Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp DeInit Callback

Definition at line 340 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp Init Callback

Definition at line 339 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Break2Callback)(struct __TIM_HandleTypeDef *htim)

TIM Break2 Callback

Definition at line 366 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::BreakCallback)(struct __TIM_HandleTypeDef *htim)

TIM Break Callback

Definition at line 365 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

HAL_TIM_ActiveChannel __TIM_HandleTypeDef::Channel

Active channel

Definition at line 332 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

void(* __TIM_HandleTypeDef::CommutationCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation Callback

Definition at line 363 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void(* __TIM_HandleTypeDef::CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation half complete Callback

Definition at line 364 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp DeInit Callback

Definition at line 350 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp Init Callback

Definition at line 349 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::ErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Error Callback

Definition at line 362 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAError(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp DeInit Callback

Definition at line 352 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void(* __TIM_HandleTypeDef::HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp Init Callback

Definition at line 351 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

DMA_HandleTypeDef* __TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 333 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), and UART_DMARxOnlyAbortCallback().

void(* __TIM_HandleTypeDef::IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture Callback

Definition at line 357 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture half complete Callback

Definition at line 358 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp DeInit Callback

Definition at line 342 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp Init Callback

Definition at line 341 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

TIM_Base_InitTypeDef __TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 331 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* __TIM_HandleTypeDef::Instance

Register base address

Definition at line 330 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef __TIM_HandleTypeDef::Lock

Locking object

Definition at line 335 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Output Compare Delay Elapsed Callback

Definition at line 359 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp DeInit Callback

Definition at line 344 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp Init Callback

Definition at line 343 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp DeInit Callback

Definition at line 348 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp Init Callback

Definition at line 347 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed Callback

Definition at line 353 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed half complete Callback

Definition at line 354 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp DeInit Callback

Definition at line 346 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp Init Callback

Definition at line 345 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished Callback

Definition at line 360 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished half complete Callback

Definition at line 361 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

__IO HAL_TIM_StateTypeDef __TIM_HandleTypeDef::State

TIM operation state

Definition at line 336 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_RegisterCallback(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIM_UnRegisterCallback(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::TriggerCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger Callback

Definition at line 355 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger half complete Callback

Definition at line 356 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U

OCREF_CLR is connected to ETRF input

Definition at line 428 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U

OCREF_CLR is disabled

Definition at line 427 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_TISEL 0x00000020U

Define Documentation

#define TIM_DMABASE_AF1 0x00000018U

Definition at line 460 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_AF2 0x00000019U

Definition at line 461 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_ARR 0x0000000BU

Definition at line 447 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_BDTR 0x00000011U

Definition at line 453 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCER 0x00000008U

Definition at line 444 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 0x00000006U

Definition at line 442 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 0x00000007U

Definition at line 443 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCMR3 0x00000015U

Definition at line 456 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR1 0x0000000DU

Definition at line 449 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR2 0x0000000EU

Definition at line 450 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR3 0x0000000FU

Definition at line 451 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR4 0x00000010U

Definition at line 452 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR5 0x00000016U

Definition at line 457 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CCR6 0x00000017U

Definition at line 458 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CNT 0x00000009U

Definition at line 445 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CR1 0x00000000U

Definition at line 436 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_CR2 0x00000001U

Definition at line 437 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_DCR 0x00000012U

Definition at line 454 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_DIER 0x00000003U

Definition at line 439 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_DMAR 0x00000013U

Definition at line 455 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_EGR 0x00000005U

Definition at line 441 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_PSC 0x0000000AU

Definition at line 446 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_RCR 0x0000000CU

Definition at line 448 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_SMCR 0x00000002U

Definition at line 438 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_SR 0x00000004U

Definition at line 440 of file stm32h7xx_hal_tim.h.

#define TIM_DMABASE_TISEL 0x00000020U

Definition at line 463 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 478 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 479 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 472 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 473 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 474 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 475 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 476 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 477 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 471 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 489 of file stm32h7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P

Polarity for TIx source

Definition at line 488 of file stm32h7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U

Polarity for TIx source

Definition at line 487 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Define Documentation

#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP

Polarity for ETR source

Definition at line 497 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Polarity for ETR source

Definition at line 498 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define TIM_ETRPRESCALER_DIV1 0x00000000U

No prescaler is used

Definition at line 506 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR input source is divided by 2

Definition at line 507 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR input source is divided by 4

Definition at line 508 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

ETR input source is divided by 8

Definition at line 509 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Center-aligned mode 1

Definition at line 519 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Center-aligned mode 2

Definition at line 520 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Center-aligned mode 3

Definition at line 521 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as down-counter

Definition at line 518 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_UP 0x00000000U

Counter used as up-counter

Definition at line 517 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 0x00000000U

Clock division: tDTS=tCK_INT

Definition at line 529 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

Clock division: tDTS=2*tCK_INT

Definition at line 530 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Clock division: tDTS=4*tCK_INT

Definition at line 531 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE 0x00000000U

Capture/Compare 1 output disabled

Definition at line 539 of file stm32h7xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Capture/Compare 1 output enabled

Definition at line 540 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U

TIMx_ARR register is not buffered

Definition at line 548 of file stm32h7xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

TIMx_ARR register is buffered

Definition at line 549 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Define Documentation

#define TIM_OCFAST_DISABLE 0x00000000U

Output Compare fast disable

Definition at line 558 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Output Compare fast enable

Definition at line 559 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U

OCxN is disabled

Definition at line 567 of file stm32h7xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

OCxN is enabled

Definition at line 568 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define TIM_OCPOLARITY_HIGH 0x00000000U

Capture/Compare output polarity

Definition at line 576 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Capture/Compare output polarity

Definition at line 577 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Define Documentation

#define TIM_OCNPOLARITY_HIGH 0x00000000U

Capture/Compare complementary output polarity

Definition at line 585 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Capture/Compare complementary output polarity

Definition at line 586 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCIDLESTATE_RESET 0x00000000U

Output Idle state: OCx=0 when MOE=0

Definition at line 595 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1

Output Idle state: OCx=1 when MOE=0

Definition at line 594 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCNIDLESTATE_RESET 0x00000000U

Complementary output Idle state: OCxN=0 when MOE=0

Definition at line 604 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N

Complementary output Idle state: OCxN=1 when MOE=0

Definition at line 603 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Capture triggered by both rising and falling edges on timer input

Definition at line 614 of file stm32h7xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Capture triggered by falling edge on timer input

Definition at line 613 of file stm32h7xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Capture triggered by rising edge on timer input

Definition at line 612 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Encoder Input Polarity

Defines
TIM Encoder Input Polarity
TIM Exported Constants

Defines

#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Define Documentation

#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Encoder input with falling edge polarity

Definition at line 623 of file stm32h7xx_hal_tim.h.

#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Encoder input with rising edge polarity

Definition at line 622 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

Define Documentation

#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 631 of file stm32h7xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 633 of file stm32h7xx_hal_tim.h.

#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 635 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32H7B3xQ HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Define Documentation

#define TIM_ICPSC_DIV1 0x00000000U

Capture performed each time an edge is detected on the capture input

Definition at line 643 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0

Capture performed once every 2 events

Definition at line 644 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1

Capture performed once every 4 events

Definition at line 645 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Capture performed once every 8 events

Definition at line 646 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U

Define Documentation

#define TIM_OPMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 655 of file stm32h7xx_hal_tim.h.

#define TIM_OPMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 654 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 663 of file stm32h7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

Definition at line 665 of file stm32h7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level.

Definition at line 664 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE

Define Documentation

#define TIM_IT_BREAK TIM_DIER_BIE

Break interrupt

Definition at line 680 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 TIM_DIER_CC1IE

Capture/Compare 1 interrupt

Definition at line 674 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 TIM_DIER_CC2IE

Capture/Compare 2 interrupt

Definition at line 675 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 TIM_DIER_CC3IE

Capture/Compare 3 interrupt

Definition at line 676 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 TIM_DIER_CC4IE

Capture/Compare 4 interrupt

Definition at line 677 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), and HAL_TIM_PWM_Stop_IT().

#define TIM_IT_COM TIM_DIER_COMIE

Commutation interrupt

Definition at line 678 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_IT_TRIGGER TIM_DIER_TIE

Trigger interrupt

Definition at line 679 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_IT_UPDATE TIM_DIER_UIE

Update interrupt

Definition at line 673 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32H7B3xQ HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U

Define Documentation

#define TIM_COMMUTATION_SOFTWARE 0x00000000U

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit

Definition at line 689 of file stm32h7xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input

Definition at line 688 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE

Define Documentation

#define TIM_DMA_CC1 TIM_DIER_CC1DE

DMA request is triggered by the capture/compare macth 1 event

Definition at line 698 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 TIM_DIER_CC2DE

DMA request is triggered by the capture/compare macth 2 event event

Definition at line 699 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 TIM_DIER_CC3DE

DMA request is triggered by the capture/compare macth 3 event event

Definition at line 700 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 TIM_DIER_CC4DE

DMA request is triggered by the capture/compare macth 4 event event

Definition at line 701 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), and HAL_TIM_PWM_Stop_DMA().

#define TIM_DMA_COM TIM_DIER_COMDE

DMA request is triggered by the commutation event

Definition at line 702 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_DMA_TRIGGER TIM_DIER_TDE

DMA request is triggered by the trigger event

Definition at line 703 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_DMA_UPDATE TIM_DIER_UDE

DMA request is triggered by the update event

Definition at line 697 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF

Define Documentation

#define TIM_FLAG_BREAK TIM_SR_BIF

Break interrupt flag

Definition at line 720 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 TIM_SR_B2IF

Break 2 interrupt flag

Definition at line 721 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 TIM_SR_CC1IF

Capture/Compare 1 interrupt flag

Definition at line 712 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF TIM_SR_CC1OF

Capture 1 overcapture flag

Definition at line 723 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC2 TIM_SR_CC2IF

Capture/Compare 2 interrupt flag

Definition at line 713 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF TIM_SR_CC2OF

Capture 2 overcapture flag

Definition at line 724 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC3 TIM_SR_CC3IF

Capture/Compare 3 interrupt flag

Definition at line 714 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF TIM_SR_CC3OF

Capture 3 overcapture flag

Definition at line 725 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC4 TIM_SR_CC4IF

Capture/Compare 4 interrupt flag

Definition at line 715 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF TIM_SR_CC4OF

Capture 4 overcapture flag

Definition at line 726 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC5 TIM_SR_CC5IF

Capture/Compare 5 interrupt flag

Definition at line 716 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC6 TIM_SR_CC6IF

Capture/Compare 6 interrupt flag

Definition at line 717 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_COM TIM_SR_COMIF

Commutation interrupt flag

Definition at line 718 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF

System Break interrupt flag

Definition at line 722 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_TRIGGER TIM_SR_TIF

Trigger interrupt flag

Definition at line 719 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE TIM_SR_UIF

Update interrupt flag

Definition at line 711 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU

Define Documentation

#define TIM_CHANNEL_1 0x00000000U

Capture/compare channel 1 identifier

Definition at line 734 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 0x00000004U

Capture/compare channel 2 identifier

Definition at line 735 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 0x00000008U

Capture/compare channel 3 identifier

Definition at line 736 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 0x0000000CU

Capture/compare channel 4 identifier

Definition at line 737 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), and HAL_TIMEx_TISelection().

#define TIM_CHANNEL_5 0x00000010U

Compare channel 5 identifier

Definition at line 738 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 0x00000014U

Compare channel 6 identifier

Definition at line 739 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL 0x0000003CU

Global Capture/compare channel identifier

Definition at line 740 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

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STM32H7B3xQ HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4
#define | TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
#define | TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
#define | TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF

External clock source mode 1 (ETRF)

Definition at line 757 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1

External clock source mode 2

Definition at line 748 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0

Internal clock source

Definition at line 749 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0

External clock source mode 1 (ITR0)

Definition at line 750 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1

External clock source mode 1 (ITR1)

Definition at line 751 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2

External clock source mode 1 (ITR2)

Definition at line 752 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3

External clock source mode 1 (ITR3)

Definition at line 753 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4

External clock source mode 1 (ITR4)

Definition at line 758 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5

External clock source mode 1 (ITR5)

Definition at line 759 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6

External clock source mode 1 (ITR6)

Definition at line 760 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7

External clock source mode 1 (ITR7)

Definition at line 761 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8

External clock source mode 1 (ITR8)

Definition at line 762 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1

External clock source mode 1 (TTI1FP1)

Definition at line 755 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED

External clock source mode 1 (TTI1FP1 + edge detect.)

Definition at line 754 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2

External clock source mode 1 (TTI2FP2)

Definition at line 756 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

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STM32H7B3xQ HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 774 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 773 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 770 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 771 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 772 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 782 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 783 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 784 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 785 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 793 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 794 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 802 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 803 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 804 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 805 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSR_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 814 of file stm32h7xx_hal_tim.h.

#define TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 813 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSI_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 823 of file stm32h7xx_hal_tim.h.

#define TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 822 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 831 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 832 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 833 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF

Definition at line 830 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U

Define Documentation

#define TIM_BREAK_DISABLE 0x00000000U

Break input BRK is disabled

Definition at line 842 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_ENABLE TIM_BDTR_BKE

Break input BRK is enabled

Definition at line 841 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 851 of file stm32h7xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 850 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Break input 2 Enable

Defines
TIM Break input 2 Enable
TIM Exported Constants

Defines

#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define TIM_BREAK2_DISABLE 0x00000000U

Break input BRK2 is disabled

Definition at line 859 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break input BRK2 is enabled

Definition at line 860 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Break Input 2 Polarity

Defines
TIM Break Input 2 Polarity
TIM Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 869 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK2POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 868 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 877 of file stm32h7xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Definition at line 878 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Group Channel 5 and Channel 1, 2 or 3

Defines
Group Channel 5 and Channel 1, 2 or 3
TIM Exported Constants

Defines

#define | TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Define Documentation

#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

Definition at line 887 of file stm32h7xx_hal_tim.h.

#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */

Definition at line 888 of file stm32h7xx_hal_tim.h.

#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */

Definition at line 889 of file stm32h7xx_hal_tim.h.

#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Definition at line 890 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define TIM_TRGO_ENABLE TIM_CR2_MMS_0

TIMx_CR1.CEN bit is used as trigger output (TRGO)

Definition at line 899 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Capture or a compare match 1 is used as trigger output (TRGO)

Definition at line 901 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output (TRGO)

Definition at line 902 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output(TRGO)

Definition at line 903 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output(TRGO)

Definition at line 904 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output(TRGO)

Definition at line 905 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO)

Definition at line 898 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output (TRGO)

Definition at line 900 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

TIMx_CR1.CEN bit is used as trigger output (TRGO2)

Definition at line 914 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Capture or a compare match 1 is used as trigger output (TRGO2)

Definition at line 916 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2

OC1REF signal is used as trigger output (TRGO2)

Definition at line 917 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output (TRGO2)

Definition at line 918 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output (TRGO2)

Definition at line 919 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output (TRGO2)

Definition at line 920 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges generate pulses on TRGO2

Definition at line 926 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 925 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges generate pulses on TRGO2

Definition at line 923 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3

OC5REF signal is used as trigger output (TRGO2)

Definition at line 921 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 928 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 927 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output (TRGO2)

Definition at line 922 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges generate pulses on TRGO2

Definition at line 924 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO2)

Definition at line 913 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output (TRGO2)

Definition at line 915 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Master/slave mode is selected

Definition at line 937 of file stm32h7xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM

No action

Definition at line 936 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode

Definition at line 950 of file stm32h7xx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE 0x00000000U

Slave mode disabled

Definition at line 945 of file stm32h7xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

External Clock Mode 1

Definition at line 949 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode

Definition at line 947 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode

Definition at line 946 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode

Definition at line 948 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Define Documentation

#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

Set channel to active level on match

Definition at line 959 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 970 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Asymmetric PWM mode 2

Definition at line 971 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 968 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 969 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Force active level

Definition at line 964 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

Force inactive level

Definition at line 965 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

Set channel to inactive level on match

Definition at line 960 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

PWM mode 1

Definition at line 962 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

PWM mode 2

Definition at line 963 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 966 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 967 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_TIMING 0x00000000U

Frozen

Definition at line 958 of file stm32h7xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Toggle

Definition at line 961 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ITR4 (TIM_SMCR_TS_3)
#define | TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR12 (TIM_SMCR_TS_4)
#define | TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)
#define | TIM_TS_NONE 0x0000FFFFU

Define Documentation

#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered External Trigger input (ETRF)

Definition at line 986 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0)

Definition at line 979 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1)

Definition at line 980 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 10 (ITR10)

Definition at line 993 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 11 (ITR11)

Definition at line 994 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR12 (TIM_SMCR_TS_4)

Internal Trigger 12 (ITR12)

Definition at line 995 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)

Internal Trigger 13 (ITR13)

Definition at line 996 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2)

Definition at line 981 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3)

Definition at line 982 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR4 (TIM_SMCR_TS_3)

Internal Trigger 4 (ITR4)

Definition at line 987 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)

Internal Trigger 5 (ITR5)

Definition at line 988 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 6 (ITR6)

Definition at line 989 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 7 (ITR7)

Definition at line 990 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 8 (ITR8)

Definition at line 991 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 9 (ITR9)

Definition at line 992 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE 0x0000FFFFU

No trigger selected

Definition at line 997 of file stm32h7xx_hal_tim.h.

#define TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED)

Definition at line 983 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Filtered Timer Input 1 (TI1FP1)

Definition at line 984 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered Timer Input 2 (TI2FP2)

Definition at line 985 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1009 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1008 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 1005 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 1006 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1007 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 1017 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 1018 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 1019 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 1020 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

Define Documentation

#define TIM_TI1SELECTION_CH1 0x00000000U

The TIMx_CH1 pin is connected to TI1 input

Definition at line 1028 of file stm32h7xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Definition at line 1029 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1046 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1047 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1048 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1049 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1050 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1051 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1052 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1053 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1054 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1037 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1038 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1039 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1040 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1041 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1042 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1043 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1044 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1045 of file stm32h7xx_hal_tim.h.

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STM32H7B3xQ HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 1063 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 1064 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 1065 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 1066 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)

Index of the DMA handle used for Commutation DMA requests

Definition at line 1067 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Index of the DMA handle used for Trigger DMA requests

Definition at line 1068 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)

Index of the DMA handle used for Update DMA requests

Definition at line 1062 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

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STM32H7B3xQ HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U

Define Documentation

#define TIM_CCx_DISABLE 0x00000000U

Input or output channel is disabled

Definition at line 1077 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE 0x00000001U

Input or output channel is enabled

Definition at line 1076 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE 0x00000000U

Complementary output channel is enabled

Definition at line 1079 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE 0x00000004U

Complementary output channel is enabled

Definition at line 1078 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Break System

Defines
TIM Break System
TIM Exported Constants

Defines

#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 1087 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17

Definition at line 1090 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1088 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 1089 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1294 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1328 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
      } \
    } \
  } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1150 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1246 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1216 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchro(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))

Disable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is disabled CCx output behaves normally depending on counter and CCRx values even when the trigger is ON. The minimum delay to activate CCx output when an active edge occurs on the trigger input is 5 clock cycles.
Return values:
None

Definition at line 1579 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))

Reset the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1529 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1136 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1231 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1200 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))

Enable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is enabled an active edge on the trigger input acts like a compare match on CCx output. Delay to sample the trigger input and to activate CCx output is reduced to 3 clock cycles.
Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
Return values:
None

Definition at line 1554 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))

Set the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1508 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1379 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1406 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
   ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1487 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1360 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1270 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1446 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
                                                             == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1311 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__ TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1337 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
      } \
    } \
  } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1167 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled unconditionally

Definition at line 1184 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1143 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
                                                     } while(0)

Reset TIM handle state.

Parameters:
__HANDLE__ TIM handle.
Return values:
None

Definition at line 1110 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
  } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ | TIM handle.
__AUTORELOAD__ | specifies the Counter register new value.
Return values:
None

Definition at line 1368 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__ Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1625 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                   \
    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
  } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ TIM handle.
__CKD__ specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1391 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__ | TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__ | specifies the Capture Compare register new value.
Return values:
None

Definition at line 1466 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ | TIM handle.
__COUNTER__ | specifies the Counter register new value.
Return values:
None

Definition at line 1353 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__ specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1425 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__ | TIM handle.
__PRESC__ | specifies the Prescaler new value.
Return values:
None

Definition at line 1345 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1608 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1595 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1642 of file stm32h7xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1643 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1812 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1694 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 1809 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 1806 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xFUL)

Definition at line 1797 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1803 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1800 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 1940 of file stm32h7xx_hal_tim.h.

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1737 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1784 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1776 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1779 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))

Definition at line 1653 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1690 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1774 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1763 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1769 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1752 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

Definition at line 1748 of file stm32h7xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1684 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFFU)

Definition at line 1938 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
                                   ((__BASE__) == TIM_DMABASE_TISEL))

Definition at line 1656 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_DATA_LENGTH ( LENGTH ) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

Definition at line 1934 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1915 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1735 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1731 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_ENCODERINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

Definition at line 1712 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1682 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1697 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

Definition at line 1815 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1936 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1715 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1723 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1719 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 1886 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1792 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1844 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 1861 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1700 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1706 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1703 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1709 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1745 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1728 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1789 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1786 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 1854 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1847 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED ( __TRIGGER__ )
Value:
(((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1945 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1912 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 1826 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1817 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
                                                 ((__SELECTION__) == TIM_TS_ITR13))

Definition at line 1870 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1910 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1899 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1905 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 1966 of file stm32h7xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

Definition at line 1954 of file stm32h7xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

Definition at line 1960 of file stm32h7xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Definition at line 1948 of file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 223 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Parameters:
htim | TIM Hall Sensor Interface handle
sConfig | TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 131 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspInitCallback, TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, __TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_ResetCallback(), TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 274 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 259 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 289 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | TIM Hall Sensor Interface handle
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 393 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 337 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 316 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 453 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, and TIM_DMA_ID_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 367 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 509 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 705 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 573 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 544 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 823 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 639 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 918 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1113 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 981 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 952 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1230 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1046 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1313 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1367 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1338 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1398 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Select timer input source.
      (+) Enable or disable channel grouping.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | TIM handle
sBreakDeadTimeConfig | pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Note:
Interrupts can be generated when an active level is detected on the break input, the break 2 input or the system break input. Break interrupt can be enabled by calling the __HAL_TIM_ENABLE_IT macro.
Return values:
HAL status

Definition at line 1717 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, __TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim | TIM handle.
BreakInput Break input to configure This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig | Break input source configuration
Return values:
HAL status

Definition at line 1782 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, TIM_BREAKINPUTSOURCE_COMP2, and TIM_BREAKINPUTSOURCE_DFSDM1.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR12: Internal trigger 12 selected (*)
  • TIM_TS_ITR13: Internal trigger 13 selected (*)
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1472 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR12, TIM_TS_ITR13, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR2: Internal trigger 12 selected (*)
  • TIM_TS_ITR3: Internal trigger 13 selected (*)
  • TIM_TS_NONE: No trigger is needed
(*) Value not defined in all devices.
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1594 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_IT, __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR12, TIM_TS_ITR13, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR2: Internal trigger 12 selected (*)
  • TIM_TS_ITR3: Internal trigger 13 selected (*)
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1531 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR12, TIM_TS_ITR13, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim | TIM handle.
Channels | specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 2103 of file stm32h7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | TIM handle.
sMasterConfig | pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1644 of file stm32h7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, TIM_MasterConfigTypeDef::MasterSlaveMode, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim TIM handle.
Remap specifies the TIM remapping source. For TIM1, the parameter is one of the following values:
  • TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO
  • TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
  • TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
  • TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
  • TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  • TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  • TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
For TIM2, the parameter is one of the following values:
  • TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
  • TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
  • TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
  • TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
  • TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
  • TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
For TIM3, the parameter is one of the following values:
  • TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
  • TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
For TIM5, the parameter is one of the following values:
  • TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO
  • TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
  • TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
  • TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
  • TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
For TIM8, the parameter is one of the following values:
  • TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO
  • TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
  • TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
  • TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
  • TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
  • TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
  • TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
  • TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
  • TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
For TIM23, the parameter is one of the following values: (*)
  • TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO
  • TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output
  • TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output
For TIM24, the parameter is one of the following values: (*)
  • TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO
  • TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
  • TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
  • TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
  • TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
(*) Value not defined in all devices.
Return values:
HAL status

Definition at line 1964 of file stm32h7xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_REMAP.

HAL_StatusTypeDef HAL_TIMEx_TISelection | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TISelection,
 |  | uint32_t | Channel
 | ) |  |

Select the timer input source.

Parameters:
htim TIM handle.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TI1 input channel
  • TIM_CHANNEL_2: TI2 input channel
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: For TIM1, the parameter is one of the following values:
  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
For TIM2, the parameter is one of the following values:
  • TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
  • TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
  • TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
  • TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
For TIM3, the parameter is one of the following values:
  • TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
  • TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
For TIM5, the parameter is one of the following values:
  • TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
  • TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP
  • TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP
For TIM8, the parameter is one of the following values:
  • TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
  • TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
For TIM12, the parameter can have the following values: (*)
  • TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
  • TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
For TIM15, the parameter is one of the following values:
  • TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
  • TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
  • TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
  • TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
  • TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
  • TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
  • TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
  • TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
  • TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
  • TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
For TIM16, the parameter can have the following values:
  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
For TIM17, the parameter can have the following values:
  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
  • TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
  • TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
For TIM23, the parameter can have the following values: (*)
  • TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
  • TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
  • TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
  • TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
For TIM24, the parameter can have the following values: (*)
  • TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
  • TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
  • TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
  • TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
(*) Value not defined in all devices.
Return values:
HAL status

Definition at line 2058 of file stm32h7xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_TISEL, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_Break2Callback ( TIM_HandleTypeDef * htim )

Hall Break2 detection callback in non blocking mode.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2197 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2182 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_CommutCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2153 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void HAL_TIMEx_CommutHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2167 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface handle state.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2230 of file stm32h7xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIMEx

Functions

void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
ChannelNState | specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2299 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2253 of file stm32h7xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

void TIMEx_DMACommutationHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2272 of file stm32h7xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationHalfCpltCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32h7xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 48 of file stm32h7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 59 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 56 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 50 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 53 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim_ex.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32h7xx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 67 of file stm32h7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 71 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source

Definition at line 73 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 69 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim_ex.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define | TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define | TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define | TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
#define | TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
#define | TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define | TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define | TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define | TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define | TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define | TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define | TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define | TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define | TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define | TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define | TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

Define Documentation

#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 96 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 97 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 98 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */

Definition at line 99 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

Definition at line 100 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */

Definition at line 101 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */

Definition at line 94 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */

Definition at line 95 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */

Definition at line 93 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */

Definition at line 130 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */

Definition at line 131 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */

Definition at line 129 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */

Definition at line 133 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */

Definition at line 136 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

Definition at line 137 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */

Definition at line 134 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */

Definition at line 135 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */

Definition at line 114 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */

Definition at line 115 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */

Definition at line 113 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */

Definition at line 116 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */

Definition at line 117 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */

Definition at line 118 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */

Definition at line 121 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */

Definition at line 120 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */

Definition at line 123 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */

Definition at line 124 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */

Definition at line 125 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */

Definition at line 126 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */

Definition at line 127 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */

Definition at line 106 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */

Definition at line 107 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */

Definition at line 108 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */

Definition at line 109 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

Definition at line 110 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */

Definition at line 111 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */

Definition at line 104 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */

Definition at line 105 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */

Definition at line 103 of file stm32h7xx_hal_tim_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */

Define Documentation

#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */

Definition at line 146 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */

Definition at line 147 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */

Definition at line 155 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */

Definition at line 156 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */

Definition at line 157 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Definition at line 158 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */

Definition at line 166 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */

Definition at line 167 of file stm32h7xx_hal_tim_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */

Definition at line 176 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */

Definition at line 175 of file stm32h7xx_hal_tim_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Timer input selection

Defines
TIM Extended Timer input selection
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
#define | TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
#define | TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */
#define | TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */
#define | TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define | TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
#define | TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
#define | TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
#define | TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */
#define | TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */
#define | TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */
#define | TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */
#define | TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */
#define | TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */
#define | TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */

Define Documentation

#define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */

Definition at line 205 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */

Definition at line 206 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */

Definition at line 208 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */

Definition at line 213 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */

Definition at line 212 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */

Definition at line 214 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */

Definition at line 209 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */

Definition at line 210 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */

Definition at line 211 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */

Definition at line 216 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */

Definition at line 217 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */

Definition at line 218 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */

Definition at line 219 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */

Definition at line 221 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */

Definition at line 223 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */

Definition at line 222 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */

Definition at line 224 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */

Definition at line 226 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */

Definition at line 228 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */

Definition at line 229 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */

Definition at line 227 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */

Definition at line 186 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */

Definition at line 185 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */

Definition at line 232 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */

Definition at line 234 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */

Definition at line 233 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */

Definition at line 231 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */

Definition at line 238 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */

Definition at line 239 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */

Definition at line 237 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */

Definition at line 236 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */

Definition at line 192 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */

Definition at line 194 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */

Definition at line 193 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */

Definition at line 191 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */

Definition at line 197 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */

Definition at line 199 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */

Definition at line 198 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */

Definition at line 196 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */

Definition at line 203 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */

Definition at line 202 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */

Definition at line 201 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */

Definition at line 189 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */

Definition at line 188 of file stm32h7xx_hal_tim_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Exported Macros

TIM Extended Exported Macros
TIMEx
Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIMEx

Defines

#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__)
#define | IS_TIM_REMAP(__RREMAP__)

Define Documentation

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 263 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))

Definition at line 266 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 274 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 271 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_REMAP ( __RREMAP__ )

Definition at line 322 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_TISEL ( __TISEL__ )

Definition at line 277 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_TISelection().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Define Documentation

#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */

Definition at line 183 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */

Definition at line 182 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Definition at line 186 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */

Definition at line 185 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
                                      USART_CR1_FIFOEN ))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 175 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

UART or USART CR3 fields of parameters set by UART_SetConfig API

Definition at line 179 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 368 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
BreakDetectLength Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 441 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart | UART handle.
Address | UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod Specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 538 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 612 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::MspDeInitCallback, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 295 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, UART_InitCallbacksToDefault(), and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 672 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_DeInit(), and HAL_UART_UnRegisterCallback().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 657 of file stm32h7xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UART_UnRegisterCallback().

HAL_StatusTypeDef HAL_UART_RegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID,
 |  | pUART_CallbackTypeDef | pCallback
 | ) |  |

Register a User UART Callback To be used instead of the weak predefined callback.

Parameters:
huart | uart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 705 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_WAKEUP_CB_ID, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_UnRegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Parameters:
huart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 834 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_ErrorCallback(), HAL_UART_MspDeInit(), HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MspInit(), HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UART_WAKEUP_CB_ID, HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (+) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_UART_Abort()
        (+) HAL_UART_AbortTransmit()
        (+) HAL_UART_AbortReceive()
        (+) HAL_UART_Abort_IT()
        (+) HAL_UART_AbortTransmit_IT()
        (+) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_UART_AbortCpltCallback()
        (+) HAL_UART_AbortTransmitCpltCallback()
        (+) HAL_UART_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1648 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1859 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2484 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1799 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2093 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2514 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1741 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2003 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2499 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1507 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1541 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1573 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2469 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), and UART_InitCallbacksToDefault().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2177 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ERROR_RTO, HAL_UART_ErrorCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxISR, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_RTOF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), __UART_HandleTypeDef::WakeupCallback, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1120 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1436 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1279 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FIFOMODE_ENABLE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2439 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2454 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1031 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1360 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1205 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FIFOMODE_ENABLE, UART_PARITY_NONE, UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2409 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2424 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart UART handle.
Return values:
HAL status.

Definition at line 2725 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2702 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2749 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2672 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2652 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart UART handle.
Return values:
None

Definition at line 2692 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout ( UART_HandleTypeDef * huart )

Disable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2614 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout ( UART_HandleTypeDef * huart )

Enable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2576 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

void HAL_UART_ReceiverTimeout_Config | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | TimeoutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
huart | Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
TimeoutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 2561 of file stm32h7xx_hal_uart.c.

References assert_param, __UART_HandleTypeDef::Instance, and IS_UART_RECEIVER_TIMEOUT_VALUE.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2810 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 2794 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, and __UART_HandleTypeDef::RxState.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart UART handle.
Return values:
None

Definition at line 3142 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, __UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3216 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3501 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3461 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3408 of file stm32h7xx_hal_uart.c.

References DMA_CIRCULAR, HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxState, and __UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3578 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3443 of file stm32h7xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3662 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, __TIM_HandleTypeDef::hdma, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3356 of file stm32h7xx_hal_uart.c.

References DMA_CIRCULAR, HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3524 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3390 of file stm32h7xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3629 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, and UART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3337 of file stm32h7xx_hal_uart.c.

References HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxISR, and __UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static void UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 3836 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxISR.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3321 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

void UART_InitCallbacksToDefault ( UART_HandleTypeDef * huart )

Initialize the callbacks to their default values.

Parameters:
huart UART handle.
Return values:
none

Definition at line 2832 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ErrorCallback(), HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_RxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 9 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 3911 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_Receive_IT(), and UART_RxISR_16BIT_FIFOEN().

static void UART_RxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4035 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_16BIT().

Referenced by HAL_UART_Receive_IT().

static void UART_RxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 7 or 8 bits data word length .

Parameters:
huart UART handle.
Return values:
None

Definition at line 3861 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_Receive_IT(), and UART_RxISR_8BIT_FIFOEN().

static void UART_RxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 3963 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_8BIT().

Referenced by HAL_UART_Receive_IT().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2855 of file stm32h7xx_hal_uart.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, UART_InitTypeDef::BaudRate, UART_InitTypeDef::ClockPrescaler, CSI_VALUE, __UART_HandleTypeDef::FifoMode, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD3PCLK1Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_PRESCALER, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LPUART_BRR_MAX, LPUART_BRR_MIN, LSE_VALUE, UART_InitTypeDef::Mode, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, RCC_FLAG_HSIDIV, __UART_HandleTypeDef::RxISR, UART_InitTypeDef::StopBits, __UART_HandleTypeDef::TxISR, UART_BRR_MAX, UART_BRR_MIN, UART_CLOCKSOURCE_CSI, UART_CLOCKSOURCE_D2PCLK1, UART_CLOCKSOURCE_D2PCLK2, UART_CLOCKSOURCE_D3PCLK1, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PLL2, UART_CLOCKSOURCE_PLL3, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GET_DIV_FACTOR, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_OVERSAMPLING_8, USART_CR1_FIELDS, USART_CR3_FIELDS, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_TxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 9 bits data word length.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3723 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3795 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 7 or 8 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3694 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3755 of file stm32h7xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

Handle UART Communication Timeout.

Parameters:
huart | UART handle.
Flag | Specifies the UART flag to check
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3266 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_RTO, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_CLEAR_RTOF, and UART_FLAG_RTOF.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Exported Types

Data Structures | Typedefs | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_D2PCLK1 = 0x00U, UART_CLOCKSOURCE_D2PCLK2 = 0x01U, UART_CLOCKSOURCE_D3PCLK1 = 0x02U, UART_CLOCKSOURCE_PLL2 = 0x04U,
UART_CLOCKSOURCE_PLL3 = 0x08U, UART_CLOCKSOURCE_HSI = 0x10U, UART_CLOCKSOURCE_CSI = 0x20U, UART_CLOCKSOURCE_LSE = 0x40U,
UART_CLOCKSOURCE_UNDEFINED = 0x80U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_UART_StateTypeDef

HAL UART State definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState (see UART State Code Definition).
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 175 of file stm32h7xx_hal_uart.h.

typedef void(* pUART_CallbackTypeDef)(UART_HandleTypeDef *huart)

HAL UART Callback pointer definition.

pointer to an UART callback function

Definition at line 289 of file stm32h7xx_hal_uart.h.

typedef struct __UART_HandleTypeDef UART_HandleTypeDef

UART handle Structure definition.

Enumeration Type Documentation

enum HAL_UART_CallbackIDTypeDef

HAL UART Callback ID enumeration definition.

Enumerator:
HAL_UART_TX_HALFCOMPLETE_CB_ID

UART Tx Half Complete Callback ID

HAL_UART_TX_COMPLETE_CB_ID

UART Tx Complete Callback ID

HAL_UART_RX_HALFCOMPLETE_CB_ID

UART Rx Half Complete Callback ID

HAL_UART_RX_COMPLETE_CB_ID

UART Rx Complete Callback ID

HAL_UART_ERROR_CB_ID

UART Error Callback ID

HAL_UART_ABORT_COMPLETE_CB_ID

UART Abort Complete Callback ID

HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID

UART Abort Transmit Complete Callback ID

HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID

UART Abort Receive Complete Callback ID

HAL_UART_WAKEUP_CB_ID

UART Wakeup Callback ID

HAL_UART_RX_FIFO_FULL_CB_ID

UART Rx Fifo Full Callback ID

HAL_UART_TX_FIFO_EMPTY_CB_ID

UART Tx Fifo Empty Callback ID

HAL_UART_MSPINIT_CB_ID

UART MspInit callback ID

HAL_UART_MSPDEINIT_CB_ID

UART MspDeInit callback ID

Definition at line 267 of file stm32h7xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

UART_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

UART_CLOCKSOURCE_D3PCLK1

Domain3 PCLK1 clock source

UART_CLOCKSOURCE_PLL2

PLL2Q clock source

UART_CLOCKSOURCE_PLL3

PLL3Q clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_CSI

CSI clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 180 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling
uint32_t | ClockPrescaler

Detailed Description

UART Init Structure definition.

Definition at line 47 of file stm32h7xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula: LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: =====

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock divided by a prescaler

Definition at line 49 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of UART Clock Prescaler.

Definition at line 92 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 81 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 78 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 88 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 85 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 71 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 68 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length.

Definition at line 65 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initialization structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initialization structure definition.

Definition at line 100 of file stm32h7xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 102 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable.

Definition at line 125 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 128 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 112 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 122 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 132 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 119 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 109 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 116 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 106 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint32_t | FifoMode
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
void(* | RxISR )(struct __UART_HandleTypeDef *huart)
void(* | TxISR )(struct __UART_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | ErrorCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortTransmitCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortReceiveCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | WakeupCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxFifoFullCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxFifoEmptyCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspInitCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspDeInitCallback )(struct __UART_HandleTypeDef *huart)

Detailed Description

UART handle Structure definition.

Definition at line 196 of file stm32h7xx_hal_uart.h.

Field Documentation

void(* __UART_HandleTypeDef::AbortCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Complete Callback

Definition at line 250 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Receive Complete Callback

Definition at line 252 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Transmit Complete Callback

Definition at line 251 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

UART_AdvFeatureInitTypeDef __UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 202 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

void(* __UART_HandleTypeDef::ErrorCallback)(struct __UART_HandleTypeDef *huart)

UART Error Callback

Definition at line 249 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), and UART_InitCallbacksToDefault().

__IO uint32_t __UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 242 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DeInit(), HAL_UART_DMAStop(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_WaitOnFlagUntilTimeout().

uint32_t __UART_HandleTypeDef::FifoMode

Specifies if the FIFO mode is being used. This parameter can be a value of UARTEx FIFO mode.

Definition at line 218 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_SetConfig(), and UARTEx_SetNbDataToProcess().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 235 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_Receive_DMA(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 231 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 229 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef __UART_HandleTypeDef::Init

UART communication parameters

Definition at line 200 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

USART_TypeDef* __UART_HandleTypeDef::Instance

UART registers base address

Definition at line 198 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_ReceiverTimeout_Config(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WaitOnFlagUntilTimeout(), UARTEx_SetNbDataToProcess(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef __UART_HandleTypeDef::Lock

Locking object

Definition at line 233 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t __UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 216 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::MspDeInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp DeInit callback

Definition at line 258 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

void(* __UART_HandleTypeDef::MspInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp Init callback

Definition at line 257 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

uint16_t __UART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 221 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UARTEx_SetNbDataToProcess(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 223 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT_FIFOEN(), and UARTEx_SetNbDataToProcess().

uint8_t* __UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 210 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

uint8_t* __UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 204 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Complete Callback

Definition at line 248 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxFifoFullCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Fifo Full Callback

Definition at line 254 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Half Complete Callback

Definition at line 247 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 225 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_SetConfig().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 239 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t __UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 214 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 212 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

void(* __UART_HandleTypeDef::TxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Complete Callback

Definition at line 246 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Fifo Empty Callback

Definition at line 255 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Half Complete Callback

Definition at line 245 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 227 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_EndTransmit_IT(), and UART_SetConfig().

__IO uint16_t __UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 208 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 206 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

void(* __UART_HandleTypeDef::WakeupCallback)(struct __UART_HandleTypeDef *huart)

UART Wakeup Callback

Definition at line 253 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART State Code Definition

Defines
UART State Code Definition
UART Exported Constants

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_UART_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 309 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define HAL_UART_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 313 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_DMAError(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 311 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 315 of file stm32h7xx_hal_uart.h.

#define HAL_UART_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 320 of file stm32h7xx_hal_uart.h.

#define HAL_UART_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 307 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define HAL_UART_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 305 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 318 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Error Definition

Defines
UART Error Definition
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 334 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), and UART_DMAError().

#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 332 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 338 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 331 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 329 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 333 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 330 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)

Receiver Timeout error

Definition at line 335 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 347 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_1 0x00000000U

UART frame with 1 stop bit

Definition at line 348 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 349 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 350 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define UART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 359 of file stm32h7xx_hal_uart.h.

#define UART_PARITY_NONE 0x00000000U

No parity

Definition at line 358 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), and HAL_UART_Transmit_IT().

#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 360 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define UART_HWCONTROL_CTS USART_CR3_CTSE

Clear To Send

Definition at line 370 of file stm32h7xx_hal_uart.h.

#define UART_HWCONTROL_NONE 0x00000000U

No hardware control

Definition at line 368 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS USART_CR3_RTSE

Request To Send

Definition at line 369 of file stm32h7xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Request and Clear To Send

Definition at line 371 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define UART_MODE_RX USART_CR1_RE

RX mode

Definition at line 379 of file stm32h7xx_hal_uart.h.

#define UART_MODE_TX USART_CR1_TE

TX mode

Definition at line 380 of file stm32h7xx_hal_uart.h.

#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 381 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE

Define Documentation

#define UART_STATE_DISABLE 0x00000000U

UART disabled

Definition at line 389 of file stm32h7xx_hal_uart.h.

#define UART_STATE_ENABLE USART_CR1_UE

UART enabled

Definition at line 390 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define UART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 398 of file stm32h7xx_hal_uart.h.

#define UART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 399 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

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STM32H7B3xQ HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disable

Definition at line 407 of file stm32h7xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enable

Definition at line 408 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Clock Prescaler

Defines
UART Clock Prescaler
UART Exported Constants

Defines

#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define UART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 416 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 421 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 422 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 426 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 423 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 417 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 427 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 424 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 418 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 419 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 425 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 420 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Auto Baud rate detection on 0x55 frame detection

Definition at line 438 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1

Auto Baud rate detection on 0x7F frame detection

Definition at line 437 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0

Auto Baud rate detection on falling edge

Definition at line 436 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U

Auto Baud rate detection on start bit

Definition at line 435 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Receiver Timeout

Defines
UART Receiver Timeout
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U

UART Receiver Timeout disable

Definition at line 446 of file stm32h7xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

UART Receiver Timeout enable

Definition at line 447 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN

Define Documentation

#define UART_LIN_DISABLE 0x00000000U

Local Interconnect Network disable

Definition at line 455 of file stm32h7xx_hal_uart.h.

#define UART_LIN_ENABLE USART_CR2_LINEN

Local Interconnect Network enable

Definition at line 456 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U

LIN 10-bit break detection length

Definition at line 464 of file stm32h7xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

LIN 11-bit break detection length

Definition at line 465 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define UART_DMA_TX_DISABLE 0x00000000U

UART DMA TX disabled

Definition at line 473 of file stm32h7xx_hal_uart.h.

#define UART_DMA_TX_ENABLE USART_CR3_DMAT

UART DMA TX enabled

Definition at line 474 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define UART_DMA_RX_DISABLE 0x00000000U

UART DMA RX disabled

Definition at line 482 of file stm32h7xx_hal_uart.h.

#define UART_DMA_RX_ENABLE USART_CR3_DMAR

UART DMA RX enabled

Definition at line 483 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

Define Documentation

#define UART_HALF_DUPLEX_DISABLE 0x00000000U

UART half-duplex disabled

Definition at line 491 of file stm32h7xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

UART half-duplex enabled

Definition at line 492 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

UART wake-up on address mark

Definition at line 501 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U

UART wake-up on idle line

Definition at line 500 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 509 of file stm32h7xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ

Mute Mode Request

Definition at line 511 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 512 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ

Send Break Request

Definition at line 510 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 513 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

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STM32H7B3xQ HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U

Auto Baud rate detection initialization

Definition at line 528 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 524 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 527 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 529 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 521 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 523 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 526 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 525 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 522 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32H7B3xQ HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 537 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 538 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 546 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 547 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 555 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 556 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 564 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 565 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 574 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 573 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U

RX Auto Baud rate detection enable

Definition at line 582 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

RX Auto Baud rate detection disable

Definition at line 583 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32H7B3xQ HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 592 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 591 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 600 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 601 of file stm32h7xx_hal_uart.h.

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STM32H7B3xQ HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U

UART stop mode disable

Definition at line 609 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

UART stop mode enable

Definition at line 610 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U

UART mute mode disable

Definition at line 618 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

UART mute mode enable

Definition at line 619 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS 24U

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS 24U

UART address-matching LSB position in CR2 register

Definition at line 627 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

Define Documentation

#define UART_WAKEUP_ON_ADDRESS 0x00000000U

UART wake-up on address

Definition at line 635 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

UART wake-up on receive data register not empty or RXFIFO is not empty

Definition at line 637 of file stm32h7xx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

UART wake-up on start bit

Definition at line 636 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define UART_DE_POLARITY_HIGH 0x00000000U

Driver enable signal is active high

Definition at line 645 of file stm32h7xx_hal_uart.h.

#define UART_DE_POLARITY_LOW USART_CR3_DEP

Driver enable signal is active low

Definition at line 646 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 654 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 662 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK 0x001FU

Define Documentation

#define UART_IT_MASK 0x001FU

UART interruptions flags mask

Definition at line 670 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

UART polling-based communications time-out value

Definition at line 678 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE USART_ISR_ABRE

UART auto Baud rate error

Definition at line 700 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_ABRF USART_ISR_ABRF

UART auto Baud rate flag

Definition at line 699 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_BUSY USART_ISR_BUSY

UART busy flag

Definition at line 698 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CMF USART_ISR_CMF

UART character match flag

Definition at line 697 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CTS USART_ISR_CTS

UART clear to send flag

Definition at line 702 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CTSIF USART_ISR_CTSIF

UART clear to send interrupt flag

Definition at line 703 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_FE USART_ISR_FE

UART frame error

Definition at line 713 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_IDLE USART_ISR_IDLE

UART idle flag

Definition at line 710 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_LBDF USART_ISR_LBDF

UART LIN break detection flag

Definition at line 704 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_NE USART_ISR_NE

UART noise error

Definition at line 712 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_ORE USART_ISR_ORE

UART overrun error

Definition at line 711 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_PE USART_ISR_PE

UART parity error

Definition at line 714 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_REACK USART_ISR_REACK

UART receive enable acknowledge flag

Definition at line 692 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RTOF USART_ISR_RTOF

UART receiver timeout flag

Definition at line 701 of file stm32h7xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_RWU USART_ISR_RWU

UART receiver wake-up from mute mode flag

Definition at line 695 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFF USART_ISR_RXFF

UART RXFIFO Full flag

Definition at line 690 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

UART RXFIFO not empty

Definition at line 709 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFT USART_ISR_RXFT

UART RXFIFO threshold flag

Definition at line 689 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE

UART read data register not empty

Definition at line 708 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF USART_ISR_SBKF

UART send break flag

Definition at line 696 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TC USART_ISR_TC

UART transmission complete

Definition at line 707 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK USART_ISR_TEACK

UART transmit enable acknowledge flag

Definition at line 693 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXE USART_ISR_TXE_TXFNF

UART transmit data register empty

Definition at line 705 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TXFE USART_ISR_TXFE

UART TXFIFO Empty flag

Definition at line 691 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF

UART TXFIFO not full

Definition at line 706 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXFT USART_ISR_TXFT

UART TXFIFO threshold flag

Definition at line 688 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_WUF USART_ISR_WUF

UART wake-up from stop mode flag

Definition at line 694 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits) Elements values convention: 000000000XXYYYYYb
  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register Elements values convention: 0000ZZZZ00000000b
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define UART_IT_CM 0x112EU

UART character match interruption

Definition at line 746 of file stm32h7xx_hal_uart.h.

#define UART_IT_CTS 0x096AU

UART CTS interruption

Definition at line 745 of file stm32h7xx_hal_uart.h.

#define UART_IT_ERR 0x0060U

UART error interruption

Definition at line 754 of file stm32h7xx_hal_uart.h.

#define UART_IT_FE 0x0100U

UART frame error interruption

Definition at line 758 of file stm32h7xx_hal_uart.h.

#define UART_IT_IDLE 0x0424U

UART idle interruption

Definition at line 743 of file stm32h7xx_hal_uart.h.

#define UART_IT_LBD 0x0846U

UART LIN break detection interruption

Definition at line 744 of file stm32h7xx_hal_uart.h.

#define UART_IT_NE 0x0200U

UART noise error interruption

Definition at line 757 of file stm32h7xx_hal_uart.h.

#define UART_IT_ORE 0x0300U

UART overrun error interruption

Definition at line 756 of file stm32h7xx_hal_uart.h.

#define UART_IT_PE 0x0028U

UART parity error interruption

Definition at line 737 of file stm32h7xx_hal_uart.h.

#define UART_IT_RTO 0x0B3AU

UART receiver timeout interruption

Definition at line 752 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXFF 0x183FU

UART RXFIFO full interruption

Definition at line 748 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXFNE 0x0525U

UART RXFIFO not empty interruption

Definition at line 742 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXFT 0x1A7CU

UART RXFIFO threshold reached interruption

Definition at line 750 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXNE 0x0525U

UART read data register not empty interruption

Definition at line 741 of file stm32h7xx_hal_uart.h.

#define UART_IT_TC 0x0626U

UART transmission complete interruption

Definition at line 740 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXE 0x0727U

UART transmit data register empty interruption

Definition at line 738 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXFE 0x173EU

UART TXFIFO empty interruption

Definition at line 749 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXFNF 0x0727U

UART TX FIFO not full interruption

Definition at line 739 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXFT 0x1B77U

UART TXFIFO threshold reached interruption

Definition at line 751 of file stm32h7xx_hal_uart.h.

#define UART_IT_WUF 0x1476U

UART wake-up from stop mode interruption

Definition at line 747 of file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 775 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 774 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 767 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 770 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 773 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 768 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 769 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 766 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

UART receiver timeout clear flag

Definition at line 777 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 772 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 771 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 776 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 850 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TXFECF TXFIFO empty clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_RTOF Receiver Timeout clear flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 838 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 868 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_RTOF Receiver timeout clear flag
  • UART_CLEAR_TXFECF TXFIFO empty Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 1037 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 856 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 862 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 844 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

Clear the UART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 874 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1074 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 961 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1068 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
Return values:
None

Definition at line 933 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
  }  while(0U)

Flush the UART Data registers.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 814 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_TXFT TXFIFO threshold flag
  • UART_FLAG_RXFT RXFIFO threshold flag
  • UART_FLAG_RXFF RXFIFO Full flag
  • UART_FLAG_TXFE TXFIFO Empty flag
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_CTS CTS Change flag
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TXFNF UART TXFIFO not full flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_RXFNE UART RXFIFO not empty flag
  • UART_FLAG_RTOF Receiver Timeout flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 908 of file stm32h7xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 988 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1014 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0U)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1106 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0U)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1088 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0U)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1142 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0U)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1124 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1062 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1056 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset UART handle states.

Parameters:
__HANDLE__ UART handle.
Return values:
None

Definition at line 797 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 1050 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__ LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1241 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__ UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1439 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__ UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1300 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__ UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1415 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1447 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__ UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1384 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__ UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1455 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__ UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1407 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__ UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1463 of file stm32h7xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1423 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__ UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1399 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__ 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1218 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 12500001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1212 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__ UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1488 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__ 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1224 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__ UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1349 of file stm32h7xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__ UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1341 of file stm32h7xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__ UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1357 of file stm32h7xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__ UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1258 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__ UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1325 of file stm32h7xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__ UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1333 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that UART communication mode is valid.

Parameters:
__MODE__ UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1269 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__ UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1471 of file stm32h7xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__ UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1292 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__ UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1431 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__ UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1284 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__ UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1249 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))

Ensure that UART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ UART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1496 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__ UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1310 of file stm32h7xx_hal_uart.h.

#define IS_UART_RECEIVER_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum UART receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 1318 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_ReceiverTimeout_Config().

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__ UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1373 of file stm32h7xx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__ UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1276 of file stm32h7xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__ UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1231 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__ UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1479 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__ UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1365 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__ | LPUART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1179 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1197 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
(((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1188 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)

Get UART clok division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ UART prescaler value.
Return values:
UART clock division factor

Definition at line 1159 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1204 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Private Constants

Defines
UARTEx Private Constants
UARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 63 of file stm32h7xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 66 of file stm32h7xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void UARTEx_SetNbDataToProcess ( UART_HandleTypeDef * huart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the UART configuration registers.
Parameters:
huart UART handle.
Return values:
None

Definition at line 691 of file stm32h7xx_hal_uart_ex.c.

References __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and UART_FIFOMODE_DISABLE.

Referenced by HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), and HAL_UARTEx_SetTxFifoThreshold().

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart | UART handle.
WakeUpSelection | UART wake up from stop mode parameters.
Return values:
None

Definition at line 673 of file stm32h7xx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart | UART handle.
Polarity Select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime | Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime | Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), and UART_SetConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
UARTEx Exported Functions

Extended functions. More...

Functions

__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.

Detailed Description

Extended functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of Wakeup and FIFO mode related callback functions.

    (#) Wakeup from Stop mode Callback:
        (+) HAL_UARTEx_WakeupCallback()

    (#) TX/RX Fifos Callbacks:
        (+) HAL_UARTEx_RxFifoFullCallback()
        (+) HAL_UARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_UARTEx_RxFifoFullCallback ( UART_HandleTypeDef * huart )

UART RX Fifo full callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 287 of file stm32h7xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_TxFifoEmptyCallback ( UART_HandleTypeDef * huart )

UART TX Fifo empty callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 302 of file stm32h7xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 272 of file stm32h7xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart UART handle.
AddressLength This parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 352 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode ( UART_HandleTypeDef * huart )

Disable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 524 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 464 of file stm32h7xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode ( UART_HandleTypeDef * huart )

Enable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 483 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, UART_FIFOMODE_ENABLE, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 445 of file stm32h7xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
huart UART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • UART_RXFIFO_THRESHOLD_1_8
  • UART_RXFIFO_THRESHOLD_1_4
  • UART_RXFIFO_THRESHOLD_1_2
  • UART_RXFIFO_THRESHOLD_3_4
  • UART_RXFIFO_THRESHOLD_7_8
  • UART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 619 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_RXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
huart UART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • UART_TXFIFO_THRESHOLD_1_8
  • UART_TXFIFO_THRESHOLD_1_4
  • UART_TXFIFO_THRESHOLD_1_2
  • UART_TXFIFO_THRESHOLD_3_4
  • UART_TXFIFO_THRESHOLD_7_8
  • UART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 570 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_TXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Note:
It is the application responsibility to enable the interrupt used as usart_wkup interrupt source before entering low-power mode.
Parameters:
huart UART handle.
WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 390 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32h7xx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 47 of file stm32h7xx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 57 of file stm32h7xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UARTEx WakeUp Address Length.

Definition at line 54 of file stm32h7xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 49 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart_ex.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define UART_WORDLENGTH_7B USART_CR1_M1

7-bit long UART frame

Definition at line 72 of file stm32h7xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B 0x00000000U

8-bit long UART frame

Definition at line 73 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B USART_CR1_M0

9-bit long UART frame

Definition at line 74 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), and HAL_UART_Transmit_IT().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx WakeUp Address Length

Defines
UARTEx WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define UART_ADDRESS_DETECT_4B 0x00000000U

4-bit long wake-up address

Definition at line 82 of file stm32h7xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit long wake-up address

Definition at line 83 of file stm32h7xx_hal_uart_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx FIFO mode

Defines
UARTEx FIFO mode
UARTEx Exported Constants

UART FIFO mode. More...

Defines

#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

UART FIFO mode.

Define Documentation

#define UART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 92 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_DisableFifoMode(), and UARTEx_SetNbDataToProcess().

#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 93 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx TXFIFO threshold level

Defines
UARTEx TXFIFO threshold level
UARTEx Exported Constants

UART TXFIFO threshold level. More...

Defines

#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

UART TXFIFO threshold level.

Define Documentation

#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 104 of file stm32h7xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 103 of file stm32h7xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 102 of file stm32h7xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 105 of file stm32h7xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 106 of file stm32h7xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 107 of file stm32h7xx_hal_uart_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx RXFIFO threshold level

Defines
UARTEx RXFIFO threshold level
UARTEx Exported Constants

UART RXFIFO threshold level. More...

Defines

#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

UART RXFIFO threshold level.

Define Documentation

#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 118 of file stm32h7xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 117 of file stm32h7xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 116 of file stm32h7xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 119 of file stm32h7xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 120 of file stm32h7xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 121 of file stm32h7xx_hal_uart_ex.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__ UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 817 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

Ensure that UART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 837 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetRxFifoThreshold().

#define IS_UART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

Ensure that UART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 825 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetTxFifoThreshold().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__ UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 808 of file stm32h7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__ | specifies the UART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 196 of file stm32h7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 762 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Define Documentation

#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Definition at line 170 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */

Definition at line 169 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
                                              USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 159 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
                                              USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
                                              USART_CR2_DIS_NSS))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 163 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART or USART CR3 fields of parameters set by USART_SetConfig API

Definition at line 167 of file stm32h7xx_hal_usart.c.

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 157 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TEACK_REACK_TIMEOUT 1000U

USART TX or RX enable acknowledge time-out value

Definition at line 158 of file stm32h7xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 336 of file stm32h7xx_hal_usart.c.

References assert_param, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::MspDeInitCallback, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 275 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Lock, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::State, USART_CheckIdleState(), USART_InitCallbacksToDefault(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 394 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_DeInit(), and HAL_USART_UnRegisterCallback().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 379 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Init(), and HAL_USART_UnRegisterCallback().

HAL_StatusTypeDef HAL_USART_RegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID,
 |  | pUSART_CallbackTypeDef | pCallback
 | ) |  |

Register a User USART Callback To be used instead of the weak predefined callback.

Parameters:
husart | usart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status +

Definition at line 425 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

HAL_StatusTypeDef HAL_USART_UnRegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Parameters:
husart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 552 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_ErrorCallback(), HAL_USART_MspDeInit(), HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MspInit(), HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    [..]

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT() in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA() in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_USART_Abort()
        (++) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (++) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1857 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1953 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2404 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1706 of file stm32h7xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1753 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1797 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2389 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2084 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, __HAL_USART_CLEAR_UDRFLAG, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ERROR_UDR, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxISR, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 843 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1472 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_SLAVEMODE_DISABLE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1185 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2344 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2359 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 746 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1387 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1102 of file stm32h7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_IT_TXE, USART_IT_TXFT, USART_PARITY_NONE, USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 955 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_ENABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received/sent.
Return values:
HAL status

Definition at line 1589 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Return values:
HAL status

Definition at line 1289 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2314 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2329 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2374 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 2452 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 2441 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2955 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2688 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, and __USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2662 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2569 of file stm32h7xx_hal_usart.c.

References DMA_CIRCULAR, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2759 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2644 of file stm32h7xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2511 of file stm32h7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, DMA_CIRCULAR, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2711 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2551 of file stm32h7xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 2495 of file stm32h7xx_hal_usart.c.

References HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static void USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 3164 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, __HAL_USART_DISABLE_IT, __HAL_USART_SEND_REQ, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxRxCpltCallback, USART_IT_ERR, USART_IT_TC, and USART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_IRQHandler().

void USART_InitCallbacksToDefault ( USART_HandleTypeDef * husart )

Initialize the callbacks to their default values.

Parameters:
husart USART handle.
Return values:
none

Definition at line 2475 of file stm32h7xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, HAL_USART_AbortCpltCallback(), HAL_USART_ErrorCallback(), HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Init().

static void USART_RxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3312 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_16BIT_FIFOEN().

static void USART_RxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3537 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_16BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_RxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3221 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_8BIT_FIFOEN().

static void USART_RxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3405 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_8BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2835 of file stm32h7xx_hal_usart.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, USART_InitTypeDef::ClockPrescaler, CSI_VALUE, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_PRESCALER, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, USART_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, RCC_FLAG_HSIDIV, __USART_HandleTypeDef::RxISR, USART_InitTypeDef::StopBits, __USART_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_CSI, USART_CLOCKSOURCE_D2PCLK1, USART_CLOCKSOURCE_D2PCLK2, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PLL2, USART_CLOCKSOURCE_PLL3, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_DIV_SAMPLING8, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static void USART_TxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3040 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3121 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3005 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3076 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 2807 of file stm32h7xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Exported Types

Data Structures | Typedefs | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_D2PCLK1 = 0x00U, USART_CLOCKSOURCE_D2PCLK2 = 0x01U, USART_CLOCKSOURCE_PLL2 = 0x02U, USART_CLOCKSOURCE_PLL3 = 0x04U,
USART_CLOCKSOURCE_HSI = 0x08U, USART_CLOCKSOURCE_CSI = 0x10U, USART_CLOCKSOURCE_LSE = 0x20U, USART_CLOCKSOURCE_UNDEFINED = 0x40U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart)

HAL USART Callback pointer definition.

pointer to an USART callback function

Definition at line 205 of file stm32h7xx_hal_usart.h.

typedef struct __USART_HandleTypeDef USART_HandleTypeDef

USART handle Structure definition.

Enumeration Type Documentation

enum HAL_USART_CallbackIDTypeDef

HAL USART Callback ID enumeration definition.

Enumerator:
HAL_USART_TX_HALFCOMPLETE_CB_ID

USART Tx Half Complete Callback ID

HAL_USART_TX_COMPLETE_CB_ID

USART Tx Complete Callback ID

HAL_USART_RX_HALFCOMPLETE_CB_ID

USART Rx Half Complete Callback ID

HAL_USART_RX_COMPLETE_CB_ID

USART Rx Complete Callback ID

HAL_USART_TX_RX_COMPLETE_CB_ID

USART Tx Rx Complete Callback ID

HAL_USART_ERROR_CB_ID

USART Error Callback ID

HAL_USART_ABORT_COMPLETE_CB_ID

USART Abort Complete Callback ID

HAL_USART_RX_FIFO_FULL_CB_ID

USART Rx Fifo Full Callback ID

HAL_USART_TX_FIFO_EMPTY_CB_ID

USART Tx Fifo Empty Callback ID

HAL_USART_MSPINIT_CB_ID

USART MspInit callback ID

HAL_USART_MSPDEINIT_CB_ID

USART MspDeInit callback ID

Definition at line 185 of file stm32h7xx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 90 of file stm32h7xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

USART_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

USART_CLOCKSOURCE_PLL2

PLL2Q clock source

USART_CLOCKSOURCE_PLL3

PLL3Q clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_CSI

CSI clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 105 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32h7xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | ClockPrescaler

Detailed Description

USART Init Structure definition.

Definition at line 47 of file stm32h7xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.

Note:
Oversampling by 8 is systematically applied to achieve high baud rates.

Definition at line 49 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 79 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 76 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 73 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of USART Clock Prescaler.

Definition at line 83 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 70 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 63 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 60 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 57 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_usart.h
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: __USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32h7xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | SlaveMode
uint32_t | FifoMode
void(* | RxISR )(struct __USART_HandleTypeDef *husart)
void(* | TxISR )(struct __USART_HandleTypeDef *husart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxRxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | ErrorCallback )(struct __USART_HandleTypeDef *husart)
void(* | AbortCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxFifoFullCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxFifoEmptyCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspInitCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspDeInitCallback )(struct __USART_HandleTypeDef *husart)

Detailed Description

USART handle Structure definition.

Definition at line 120 of file stm32h7xx_hal_usart.h.

Field Documentation

void(* __USART_HandleTypeDef::AbortCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Abort Complete Callback

Definition at line 171 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort_IT(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::ErrorCallback)(struct __USART_HandleTypeDef *husart)

USART Error Callback

Definition at line 170 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

__IO uint32_t __USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 162 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

uint32_t __USART_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of USARTEx FIFO mode.

Definition at line 147 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_EnableFifoMode(), and USARTEx_SetNbDataToProcess().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 156 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 154 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef __USART_HandleTypeDef::Init

USART communication parameters

Definition at line 124 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

USART_TypeDef* __USART_HandleTypeDef::Instance

USART registers base address

Definition at line 122 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

HAL_LockTypeDef __USART_HandleTypeDef::Lock

Locking object

Definition at line 158 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t __USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 138 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::MspDeInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp DeInit callback

Definition at line 176 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

void(* __USART_HandleTypeDef::MspInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp Init callback

Definition at line 175 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

uint16_t __USART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 140 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), and USARTEx_SetNbDataToProcess().

uint16_t __USART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 142 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

uint8_t* __USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 132 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint8_t* __USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 126 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Complete Callback

Definition at line 168 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxFifoFullCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Fifo Full Callback

Definition at line 172 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Half Complete Callback

Definition at line 167 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Rx IRQ handler

Definition at line 150 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), and USART_SetConfig().

__IO uint16_t __USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 136 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 134 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

uint32_t __USART_HandleTypeDef::SlaveMode

Enable/Disable UART SPI Slave Mode. This parameter can be a value of USARTEx Synchronous Slave mode enable

Definition at line 144 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO HAL_USART_StateTypeDef __USART_HandleTypeDef::State

USART communication state

Definition at line 160 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

void(* __USART_HandleTypeDef::TxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Complete Callback

Definition at line 166 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Fifo Empty Callback

Definition at line 173 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Half Complete Callback

Definition at line 165 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Tx IRQ handler

Definition at line 152 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), and USART_SetConfig().

void(* __USART_HandleTypeDef::TxRxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Rx Complete Callback

Definition at line 169 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO uint16_t __USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 130 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 128 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_usart.h
Generated on Tue Nov 12 2019 18:50:40 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Error Definition

Defines
USART Error Definition
USART Exported Constants

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 226 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and USART_DMAError().

#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 224 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 229 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 223 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 221 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 225 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 222 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)

SPI slave underrun error

Definition at line 227 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define USART_STOPBITS_0_5 USART_CR2_STOP_0

USART frame with 0.5 stop bit

Definition at line 238 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_1 0x00000000U

USART frame with 1 stop bit

Definition at line 239 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

USART frame with 1.5 stop bits

Definition at line 240 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_2 USART_CR2_STOP_1

USART frame with 2 stop bits

Definition at line 241 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define USART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 250 of file stm32h7xx_hal_usart.h.

#define USART_PARITY_NONE 0x00000000U

No parity

Definition at line 249 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 251 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define USART_MODE_RX USART_CR1_RE

RX mode

Definition at line 259 of file stm32h7xx_hal_usart.h.

#define USART_MODE_TX USART_CR1_TE

TX mode

Definition at line 260 of file stm32h7xx_hal_usart.h.

#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 261 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Over Sampling

Defines
USART Over Sampling
USART Exported Constants

Defines

#define | USART_OVERSAMPLING_16 0x00000000U
#define | USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 269 of file stm32h7xx_hal_usart.h.

#define USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 270 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define USART_CLOCK_DISABLE 0x00000000U

USART clock disable

Definition at line 278 of file stm32h7xx_hal_usart.h.

#define USART_CLOCK_ENABLE USART_CR2_CLKEN

USART clock enable

Definition at line 279 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define USART_POLARITY_HIGH USART_CR2_CPOL

Driver enable signal is active low

Definition at line 288 of file stm32h7xx_hal_usart.h.

#define USART_POLARITY_LOW 0x00000000U

Driver enable signal is active high

Definition at line 287 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define USART_PHASE_1EDGE 0x00000000U

USART frame phase on first clock transition

Definition at line 296 of file stm32h7xx_hal_usart.h.

#define USART_PHASE_2EDGE USART_CR2_CPHA

USART frame phase on second clock transition

Definition at line 297 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define USART_LASTBIT_DISABLE 0x00000000U

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 305 of file stm32h7xx_hal_usart.h.

#define USART_LASTBIT_ENABLE USART_CR2_LBCL

USART frame last data bit clock pulse output to SCLK pin

Definition at line 306 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Clock Prescaler

Defines
USART Clock Prescaler
USART Exported Constants

Defines

#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define USART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 314 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 319 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 320 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 324 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 321 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 315 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 325 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 322 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 316 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 317 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 323 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 318 of file stm32h7xx_hal_usart.h.

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STM32H7B3xQ HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 334 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 335 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY USART_ISR_BUSY

USART busy flag

Definition at line 351 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_FE USART_ISR_FE

USART frame error

Definition at line 361 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_IDLE USART_ISR_IDLE

USART idle flag

Definition at line 358 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_NE USART_ISR_NE

USART noise error

Definition at line 360 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_ORE USART_ISR_ORE

USART overrun error

Definition at line 359 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_PE USART_ISR_PE

USART parity error

Definition at line 362 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_REACK USART_ISR_REACK

USART receive enable acknowledge flag

Definition at line 349 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXFF USART_ISR_RXFF

USART RXFIFO Full flag

Definition at line 347 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

USART RXFIFO not empty

Definition at line 357 of file stm32h7xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_FLAG_RXFT USART_ISR_RXFT

USART RXFIFO threshold flag

Definition at line 346 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE

USART read data register not empty

Definition at line 356 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TC USART_ISR_TC

USART transmission complete

Definition at line 355 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit().

#define USART_FLAG_TEACK USART_ISR_TEACK

USART transmit enable acknowledge flag

Definition at line 350 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_TXE USART_ISR_TXE_TXFNF

USART transmit data register empty

Definition at line 353 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TXFE USART_ISR_TXFE

USART TXFIFO Empty flag

Definition at line 348 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF

USART TXFIFO not full

Definition at line 354 of file stm32h7xx_hal_usart.h.

Referenced by USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

#define USART_FLAG_TXFT USART_ISR_TXFT

USART TXFIFO threshold flag

Definition at line 345 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_UDR USART_ISR_UDR

SPI slave underrun error flag

Definition at line 352 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR 0x0060U

USART error interruption

Definition at line 385 of file stm32h7xx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE 0x0100U

USART frame error interruption

Definition at line 388 of file stm32h7xx_hal_usart.h.

#define USART_IT_IDLE 0x0424U

USART idle interruption

Definition at line 384 of file stm32h7xx_hal_usart.h.

#define USART_IT_NE 0x0200U

USART noise error interruption

Definition at line 387 of file stm32h7xx_hal_usart.h.

#define USART_IT_ORE 0x0300U

USART overrun error interruption

Definition at line 386 of file stm32h7xx_hal_usart.h.

#define USART_IT_PE 0x0028U

USART parity error interruption

Definition at line 378 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXFF 0x183FU

USART RXFIFO full interruption

Definition at line 389 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXFNE 0x0525U

USART RXFIFO not empty interruption

Definition at line 383 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXFT 0x1A7CU

USART RXFIFO threshold reached interruption

Definition at line 391 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXNE 0x0525U

USART read data register not empty interruption

Definition at line 382 of file stm32h7xx_hal_usart.h.

#define USART_IT_TC 0x0626U

USART transmission complete interruption

Definition at line 381 of file stm32h7xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define USART_IT_TXE 0x0727U

USART transmit data register empty interruption

Definition at line 379 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT(), and USART_TxISR_8BIT().

#define USART_IT_TXFE 0x173EU

USART TXFIFO empty interruption

Definition at line 390 of file stm32h7xx_hal_usart.h.

#define USART_IT_TXFNF 0x0727U

USART TX FIFO not full interruption

Definition at line 380 of file stm32h7xx_hal_usart.h.

#define USART_IT_TXFT 0x1B77U

USART TXFIFO threshold reached interruption

Definition at line 392 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 402 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 405 of file stm32h7xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 403 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 404 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 401 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 406 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO Empty Clear Flag

Definition at line 408 of file stm32h7xx_hal_usart.h.

#define USART_CLEAR_UDRF USART_ICR_UDRCF

SPI slave underrun error Clear Flag

Definition at line 407 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U

Define Documentation

#define USART_CR_MASK 0x00E0U

USART control register mask

Definition at line 417 of file stm32h7xx_hal_usart.h.

#define USART_CR_POS 5U

USART control register position

Definition at line 418 of file stm32h7xx_hal_usart.h.

#define USART_ISR_MASK 0x1F00U

USART ISR register mask

Definition at line 419 of file stm32h7xx_hal_usart.h.

#define USART_ISR_POS 8U

USART ISR register position

Definition at line 420 of file stm32h7xx_hal_usart.h.

#define USART_IT_MASK 0x001FU

USART interruptions flags mask

Definition at line 416 of file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 500 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
  • USART_CLEAR_UDRF SPI slave underrun error Clear Flag
Return values:
None

Definition at line 488 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 518 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 639 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 506 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 512 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), and USART_EndTransmit_IT().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 494 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)

Clear the USART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 524 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_UDRFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)

Clear SPI slave underrun error flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 530 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 674 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 572 of file stm32h7xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 668 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init(), and HAL_USARTEx_EnableSlaveMode().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 550 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__ specifies the USART Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXFT TXFIFO threshold flag
  • USART_FLAG_RXFT RXFIFO threshold flag
  • USART_FLAG_RXFF RXFIFO Full flag
  • USART_FLAG_TXFE TXFIFO Empty flag
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_UDR SPI slave underrun error flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TXFNF TXFIFO not full flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_RXFNE RXFIFO not empty flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 472 of file stm32h7xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                         & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 597 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != 0U) ? SET : RESET)

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 620 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 662 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 656 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback = NULL;        \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
                                                      } while(0U)

Reset USART handle state.

Parameters:
__HANDLE__ USART handle.
Return values:
None

Definition at line 439 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__REQ__ specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 650 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 12500000U)

Check USART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 983 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__ USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 1024 of file stm32h7xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 1046 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__ USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1009 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == USART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

Ensure that USART oversampling is valid.

Parameters:
__SAMPLING__ USART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1016 of file stm32h7xx_hal_usart.h.

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__ USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1000 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__ USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 1039 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__ USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 1032 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))

Ensure that USART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ USART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1062 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__ USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1054 of file stm32h7xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__ USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 990 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
                                                                        + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | USART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 709 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)

Get USART clock division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ USART prescaler value.
Return values:
USART clock division factor

Definition at line 689 of file stm32h7xx_hal_usart.h.

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__ | specifies the USART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 718 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx Private Constants

Defines
USARTEx Private Constants
USARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 61 of file stm32h7xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 64 of file stm32h7xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx Private Functions

Functions
USARTEx Private Functions
USARTEx

Functions

static void USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void USARTEx_SetNbDataToProcess ( USART_HandleTypeDef * husart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
husart USART handle.
Return values:
None

Definition at line 499 of file stm32h7xx_hal_usart_ex.c.

References __USART_HandleTypeDef::FifoMode, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and USART_FIFOMODE_DISABLE.

Referenced by HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
USARTEx Exported Functions

Extended USART Transmit/Receive functions. More...

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.

Detailed Description

Extended USART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (+) HAL_USARTEx_RxFifoFullCallback()
        (+) HAL_USARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_USARTEx_RxFifoFullCallback ( USART_HandleTypeDef * husart )

USART RX Fifo full callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 109 of file stm32h7xx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void HAL_USARTEx_TxFifoEmptyCallback ( USART_HandleTypeDef * husart )

USART TX Fifo empty callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 124 of file stm32h7xx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
USARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_USARTEx_ConfigNSS | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | NSSConfig
 | ) |  |

Configure the Slave Select input pin (NSS).

Note:
Software NSS management: SPI slave will always be selected and NSS input pin will be ignored.
Hardware NSS management: the SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high.
Parameters:
husart USART handle.
NSSConfig NSS configuration. This parameter can be one of the following values:
  • USART_NSS_HARD
  • USART_NSS_SOFT
Return values:
HAL status

Definition at line 270 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_NSS, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode ( USART_HandleTypeDef * husart )

Disable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 349 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode ( USART_HandleTypeDef * husart )

Disable the SPI slave mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 222 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode ( USART_HandleTypeDef * husart )

Enable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 308 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_FIFOMODE_ENABLE, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode ( USART_HandleTypeDef * husart )

Enable the SPI slave mode.

Note:
When the USART operates in SPI slave mode, it handles data flow using the serial interface clock derived from the external SCLK signal provided by the external master SPI device.
In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it will become desynchronized with the master.
The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave will transmit zeros.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 174 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
husart USART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • USART_RXFIFO_THRESHOLD_1_8
  • USART_RXFIFO_THRESHOLD_1_4
  • USART_RXFIFO_THRESHOLD_1_2
  • USART_RXFIFO_THRESHOLD_3_4
  • USART_RXFIFO_THRESHOLD_7_8
  • USART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 444 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_RXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
husart USART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • USART_TXFIFO_THRESHOLD_1_8
  • USART_TXFIFO_THRESHOLD_1_4
  • USART_TXFIFO_THRESHOLD_1_2
  • USART_TXFIFO_THRESHOLD_3_4
  • USART_TXFIFO_THRESHOLD_7_8
  • USART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 395 of file stm32h7xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_TXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

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STM32H7B3xQ HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long USART frame

Definition at line 48 of file stm32h7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B 0x00000000U

8-bit long USART frame

Definition at line 49 of file stm32h7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long USART frame

Definition at line 50 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx Slave Select Management

Defines
USARTEx Slave Select Management
USARTEx Exported Constants

Defines

#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS

Define Documentation

#define USART_NSS_HARD 0x00000000U

SPI slave selection depends on NSS input pin

Definition at line 58 of file stm32h7xx_hal_usart_ex.h.

#define USART_NSS_SOFT USART_CR2_DIS_NSS

SPI slave is always selected and NSS input pin is ignored

Definition at line 59 of file stm32h7xx_hal_usart_ex.h.

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STM32H7B3xQ HAL User Manual: USARTEx Synchronous Slave mode enable

Defines
USARTEx Synchronous Slave mode enable
USARTEx Exported Constants

USART SLAVE mode. More...

Defines

#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

Detailed Description

USART SLAVE mode.

Define Documentation

#define USART_SLAVEMODE_DISABLE 0x00000000U

USART SPI Slave Mode Enable

Definition at line 69 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

USART SPI Slave Mode Disable

Definition at line 70 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx FIFO mode

Defines
USARTEx FIFO mode
USARTEx Exported Constants

USART FIFO mode. More...

Defines

#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

USART FIFO mode.

Define Documentation

#define USART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 79 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_DisableFifoMode(), and USARTEx_SetNbDataToProcess().

#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 80 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), and HAL_USARTEx_EnableFifoMode().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx TXFIFO threshold level

Defines
USARTEx TXFIFO threshold level
USARTEx Exported Constants

USART TXFIFO level. More...

Defines

#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

USART TXFIFO level.

Define Documentation

#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 91 of file stm32h7xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 90 of file stm32h7xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 89 of file stm32h7xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 92 of file stm32h7xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 93 of file stm32h7xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 94 of file stm32h7xx_hal_usart_ex.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx RXFIFO threshold level

Defines
USARTEx RXFIFO threshold level
USARTEx Exported Constants

USART RXFIFO level. More...

Defines

#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

USART RXFIFO level.

Define Documentation

#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 105 of file stm32h7xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 104 of file stm32h7xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 103 of file stm32h7xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 106 of file stm32h7xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 107 of file stm32h7xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 108 of file stm32h7xx_hal_usart_ex.h.

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STM32H7B3xQ HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Define Documentation

#define IS_USART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == USART_FIFOMODE_DISABLE ) || \
                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

Ensure that USART FIFO mode is valid.

Parameters:
__STATE__ USART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 203 of file stm32h7xx_hal_usart_ex.h.

#define IS_USART_NSS ( __NSS__ )
Value:
(((__NSS__) == USART_NSS_HARD) || \
                               ((__NSS__) == USART_NSS_SOFT))

Ensure that USART Negative Slave Select (NSS) pin management is valid.

Parameters:
__NSS__ USART Negative Slave Select pin management.
Return values:
SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

Definition at line 187 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_ConfigNSS().

#define IS_USART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

Ensure that USART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 223 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetRxFifoThreshold().

#define IS_USART_SLAVEMODE ( __STATE__ )
Value:
(((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

Ensure that USART Slave Mode is valid.

Parameters:
__STATE__ USART Slave Mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 195 of file stm32h7xx_hal_usart_ex.h.

#define IS_USART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

Ensure that USART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 211 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetTxFifoThreshold().

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__ USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 178 of file stm32h7xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 131 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 169 of file stm32h7xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::EwiCallback, WWDG_InitTypeDef::EWIMode, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_MspInit(), __WWDG_HandleTypeDef::Init, __WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, __WWDG_HandleTypeDef::MspInitCallback, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 223 of file stm32h7xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_UnRegisterCallback().

HAL_StatusTypeDef HAL_WWDG_RegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID,
 |  | pWWDG_CallbackTypeDef | pCallback
 | ) |  |

Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hwwdg | WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 246 of file stm32h7xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EWI_CB_ID, HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hwwdg WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
Return values:
status

Definition at line 286 of file stm32h7xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_EWI_CB_ID, HAL_WWDG_MspInit(), HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 387 of file stm32h7xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), and HAL_WWDG_UnRegisterCallback().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 358 of file stm32h7xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 335 of file stm32h7xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::Init, and __WWDG_HandleTypeDef::Instance.

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STM32H7B3xQ HAL User Manual: WWDG Exported Types

Data Structures | Typedefs | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00u, HAL_WWDG_MSPINIT_CB_ID = 0x01u }
HAL WWDG common Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp)

HAL WWDG Callback pointer definition.

pointer to a WWDG common callback functions

Definition at line 97 of file stm32h7xx_hal_wwdg.h.

typedef struct __WWDG_HandleTypeDef WWDG_HandleTypeDef

WWDG handle Structure definition.

Enumeration Type Documentation

enum HAL_WWDG_CallbackIDTypeDef

HAL WWDG common Callback ID enumeration definition.

Enumerator:
HAL_WWDG_EWI_CB_ID

WWDG EWI callback ID

HAL_WWDG_MSPINIT_CB_ID

WWDG MspInit callback ID

Definition at line 88 of file stm32h7xx_hal_wwdg.h.

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STM32H7B3xQ HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32h7xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 48 of file stm32h7xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 56 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 59 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 50 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 53 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_wwdg.h
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STM32H7B3xQ HAL User Manual: __WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32h7xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
void(* | EwiCallback )(struct __WWDG_HandleTypeDef *hwwdg)
void(* | MspInitCallback )(struct __WWDG_HandleTypeDef *hwwdg)

Detailed Description

WWDG handle Structure definition.

Definition at line 68 of file stm32h7xx_hal_wwdg.h.

Field Documentation

void(* __WWDG_HandleTypeDef::EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Early WakeUp Interrupt callback

Definition at line 78 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

WWDG_InitTypeDef __WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 75 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* __WWDG_HandleTypeDef::Instance

Register base address

Definition at line 73 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

void(* __WWDG_HandleTypeDef::MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Msp Init callback

Definition at line 80 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_wwdg.h
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STM32H7B3xQ HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 113 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

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STM32H7B3xQ HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 122 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

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STM32H7B3xQ HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 130 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/128

Definition at line 137 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 134 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 131 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 135 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 132 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 136 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 133 of file stm32h7xx_hal_wwdg.h.

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STM32H7B3xQ HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 145 of file stm32h7xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 146 of file stm32h7xx_hal_wwdg.h.

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STM32H7B3xQ HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 171 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 173 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

Definition at line 160 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 169 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

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STM32H7B3xQ HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 241 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 221 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 191 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 202 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 231 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 212 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CFR\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 250 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

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STM32H7B3xQ HAL User Manual: Initialization de-initialization functions

Functions
Initialization de-initialization functions
Delay Block Low Layer Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | DelayBlock_Enable (DLYB_TypeDef *DLYBx)
Enable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Disable (DLYB_TypeDef *DLYBx)
Disable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Configure (DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units)
Configure the Delay Block instance.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef DelayBlock_Configure | ( | DLYB_TypeDef * | DLYBx,
 |  | uint32_t | PhaseSel,
 |  | uint32_t | Units
 | ) |  |

Configure the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
PhaseSel,: Phase selection [0..11].
Units,: Delay units[0..127].
Return values:
HAL status

Definition at line 180 of file stm32h7xx_ll_delayblock.c.

HAL_StatusTypeDef DelayBlock_Disable ( DLYB_TypeDef * DLYBx )

Disable the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
Return values:
HAL status

Definition at line 166 of file stm32h7xx_ll_delayblock.c.

HAL_StatusTypeDef DelayBlock_Enable ( DLYB_TypeDef * DLYBx )

Enable the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
Return values:
HAL status

Definition at line 96 of file stm32h7xx_ll_delayblock.c.

References DLYB_MAX_SELECT, DLYB_MAX_UNIT, DLYB_TIMEOUT, and HAL_GetTick().

Referenced by SD_DDR_Mode(), and SD_UltraHighSpeed().

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STM32H7B3xQ HAL User Manual: DELAYBLOCK_LL Exported Types

DELAYBLOCK_LL Exported Types
DELAYBLOCK_LL
Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Delay Block Exported Constants

Defines
Delay Block Exported Constants
DELAYBLOCK_LL

Defines

#define | DLYB_MAX_UNIT ((uint32_t)0x00000080U)
#define | DLYB_MAX_SELECT ((uint32_t)0x0000000CU)

Define Documentation

#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU)

Max SELECT value (12)

Definition at line 56 of file stm32h7xx_ll_delayblock.h.

Referenced by DelayBlock_Enable().

#define DLYB_MAX_UNIT ((uint32_t)0x00000080U)

Max UNIT value (128)

Definition at line 55 of file stm32h7xx_ll_delayblock.h.

Referenced by DelayBlock_Enable().

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STM32H7B3xQ HAL User Manual: Delay Block functions

Functions
Delay Block functions
DELAYBLOCK_LL

Functions

HAL_StatusTypeDef | DelayBlock_Enable (DLYB_TypeDef *DLYBx)
Enable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Disable (DLYB_TypeDef *DLYBx)
Disable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Configure (DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units)
Configure the Delay Block instance.

Function Documentation

HAL_StatusTypeDef DelayBlock_Configure | ( | DLYB_TypeDef * | DLYBx,
 |  | uint32_t | PhaseSel,
 |  | uint32_t | Units
 | ) |  |

Configure the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
PhaseSel,: Phase selection [0..11].
Units,: Delay units[0..127].
Return values:
HAL status

Definition at line 180 of file stm32h7xx_ll_delayblock.c.

HAL_StatusTypeDef DelayBlock_Disable ( DLYB_TypeDef * DLYBx )

Disable the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
Return values:
HAL status

Definition at line 166 of file stm32h7xx_ll_delayblock.c.

HAL_StatusTypeDef DelayBlock_Enable ( DLYB_TypeDef * DLYBx )

Enable the Delay Block instance.

Parameters:
DLYBx,: Pointer to DLYB instance.
Return values:
HAL status

Definition at line 96 of file stm32h7xx_ll_delayblock.c.

References DLYB_MAX_SELECT, DLYB_MAX_UNIT, DLYB_TIMEOUT, and HAL_GetTick().

Referenced by SD_DDR_Mode(), and SD_UltraHighSpeed().

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STM32H7B3xQ HAL User Manual: DELAYBLOCK_LL

Modules | Defines
DELAYBLOCK_LL
STM32H7xx_HAL_Driver

Low layer module for Delay Block. More...

Modules

Delay Block Low Layer Exported Functions
DELAYBLOCK_LL Exported Types
Delay Block Exported Constants
Delay Block functions

Defines

#define DLYB_TIMEOUT 0xFFU

Detailed Description

Low layer module for Delay Block.

Define Documentation

#define DLYB_TIMEOUT 0xFFU

Definition at line 67 of file stm32h7xx_ll_delayblock.c.

Referenced by DelayBlock_Enable().

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STM32H7B3xQ HAL User Manual: GPIO Alternate Function Selection

Defines
GPIO Alternate Function Selection
GPIO Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define | GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define | GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define | GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define | GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#define | GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define | GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#define | GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define | GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define | GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define | GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define | GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define | GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define | GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define | GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define | GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define | GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#define | GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */
#define | GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */
#define | GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
#define | GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#define | GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
#define | GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define | GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define | GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
#define | GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define | GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define | GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define | GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define | GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */
#define | GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
#define | GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define | GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */
#define | GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define | GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define | GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#define | GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
#define | GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */
#define | GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)

Define Documentation

#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */

Definition at line 56 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 54 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 53 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 55 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */

Definition at line 57 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */

Definition at line 220 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */

Definition at line 221 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */

Definition at line 225 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */

Definition at line 223 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */

Definition at line 237 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */

Definition at line 233 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */

Definition at line 235 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */

AF 10 selection.

Definition at line 215 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */

Definition at line 216 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */

Definition at line 239 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */

Definition at line 249 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */

Definition at line 250 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */

Definition at line 248 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */

Definition at line 255 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */

Definition at line 253 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */

Definition at line 267 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */

Definition at line 245 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */

Definition at line 270 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */

Definition at line 247 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */

AF 11 selection.

Definition at line 244 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */

Definition at line 251 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */

Definition at line 252 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */

Definition at line 246 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */

Definition at line 261 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */

Definition at line 258 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */

Definition at line 279 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */

Definition at line 280 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */

AF 12 selection.

Definition at line 276 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */

Definition at line 284 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */

Definition at line 278 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */

Definition at line 277 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */

Definition at line 281 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */

Definition at line 282 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */

Definition at line 294 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */

Definition at line 295 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */

AF 13 selection.

Definition at line 293 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */

Definition at line 297 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */

Definition at line 303 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */

Definition at line 305 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */

Definition at line 306 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */

AF 14 selection.

Definition at line 311 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */

Definition at line 312 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 317 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */

Definition at line 76 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */

AF 1 selection.

Definition at line 72 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */

Definition at line 74 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */

Definition at line 75 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */

Definition at line 73 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */

Definition at line 88 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */

Definition at line 87 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */

Definition at line 92 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */

AF 2 selection.

Definition at line 84 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */

Definition at line 85 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */

Definition at line 86 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */

Definition at line 99 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */

Definition at line 98 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */

Definition at line 100 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */

Definition at line 101 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */

Definition at line 102 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */

Definition at line 103 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */

Definition at line 105 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */

Definition at line 106 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */

AF 3 selection.

Definition at line 97 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */

Definition at line 120 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */

Definition at line 123 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */

Definition at line 125 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 115 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */

Definition at line 116 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */

Definition at line 117 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */

Definition at line 118 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */

Definition at line 121 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */

Definition at line 128 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */

Definition at line 119 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */

Definition at line 122 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */

Definition at line 140 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */

AF 5 selection.

Definition at line 134 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */

Definition at line 135 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */

Definition at line 136 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */

Definition at line 137 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */

Definition at line 138 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */

Definition at line 139 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */

Definition at line 149 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */

Definition at line 152 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */

Definition at line 148 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */

Definition at line 158 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */

Definition at line 147 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */

AF 6 selection.

Definition at line 145 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */

Definition at line 146 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */

Definition at line 150 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */

Definition at line 172 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */

Definition at line 173 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */

AF 7 selection.

Definition at line 164 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */

Definition at line 165 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */

Definition at line 166 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */

Definition at line 171 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */

Definition at line 167 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */

Definition at line 168 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */

Definition at line 169 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */

Definition at line 170 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */

Definition at line 184 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */

Definition at line 179 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */

Definition at line 185 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */

Definition at line 183 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */

AF 8 selection.

Definition at line 178 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */

Definition at line 180 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */

Definition at line 181 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */

Definition at line 182 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */

AF 9 selection.

Definition at line 193 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */

Definition at line 194 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */

Definition at line 200 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */

Definition at line 198 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */

Definition at line 208 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */

Definition at line 209 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */

Definition at line 197 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */

Definition at line 199 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */

Definition at line 195 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */

Definition at line 196 of file stm32h7xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0F)

Definition at line 319 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Exported Macros

GPIO Exported Macros
GPIOEx
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Exported Functions

GPIO Exported Functions
GPIOEx
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIOEx

Defines

#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE

Define Documentation

#define GPIOA_PIN_AVAILABLE GPIO_PIN_All

GPIO pin available on the platform.

Definition at line 357 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOB_PIN_AVAILABLE GPIO_PIN_All

Definition at line 358 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOC_PIN_AVAILABLE GPIO_PIN_All

Definition at line 359 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOD_PIN_AVAILABLE GPIO_PIN_All

Definition at line 360 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOE_PIN_AVAILABLE GPIO_PIN_All

Definition at line 361 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOF_PIN_AVAILABLE GPIO_PIN_All

Definition at line 362 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOG_PIN_AVAILABLE GPIO_PIN_All

Definition at line 363 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOH_PIN_AVAILABLE GPIO_PIN_All

Definition at line 366 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOI_PIN_AVAILABLE GPIO_PIN_All

Definition at line 364 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All

Definition at line 365 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOK_PIN_AVAILABLE
Value:
(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)

Definition at line 367 of file stm32h7xx_hal_gpio_ex.h.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Get Port Index

Defines
GPIO Get Port Index
GPIO Private Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0UL :\
                                    ((__GPIOx__) == (GPIOB))? 1UL :\
                                    ((__GPIOx__) == (GPIOC))? 2UL :\
                                    ((__GPIOx__) == (GPIOD))? 3UL :\
                                    ((__GPIOx__) == (GPIOE))? 4UL :\
                                    ((__GPIOx__) == (GPIOF))? 5UL :\
                                    ((__GPIOx__) == (GPIOG))? 6UL :\
                                    ((__GPIOx__) == (GPIOH))? 7UL :\
                                    ((__GPIOx__) == (GPIOI))? 8UL :\
                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)

Definition at line 381 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Check Alternate Function

GPIO Check Alternate Function
GPIO Private Macros
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIOEx
Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMPEx_Exported_Functions_Group1

Functions
OPAMPEx_Exported_Functions_Group1
OPAMPEx Exported Functions

Functions

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2
 | ) |  |

Run the self calibration of 2 OPAMPs in parallel.

Note:
Trimming values (PMOS & NMOS) are updated and user trimming is enabled is calibration is successful.
Calibration is performed in the mode specified in OPAMP init structure (mode normal or low power). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Parameters:
hopamp1 | handle
hopamp2 | handle
Return values:
HAL status

Definition at line 79 of file stm32h7xx_hal_opamp_ex.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, OPAMP_InitTypeDef::PowerMode, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMPEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]
      (+) OPAMP unlock.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_Unlock ( OPAMP_HandleTypeDef * hopamp )

Unlock the selected OPAMP configuration.

Note:
This function must be called only when OPAMP is in state "locked".
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 390 of file stm32h7xx_hal_opamp_ex.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
#define | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
#define | ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
#define | ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
#define | ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
#define | ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
#define | LL_ADC_AWD1_TR LL_ADC_AWD1
#define | LL_ADC_AWD2_TR LL_ADC_AWD2
#define | LL_ADC_AWD3_TR LL_ADC_AWD3
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define | ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
#define | ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
#define | ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
#define | ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
#define | ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
#define | ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
#define | ADC_LINEAR_CALIB_REG_COUNT (6UL)

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 314 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)

Definition at line 315 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 319 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)

Definition at line 308 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 320 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)

Definition at line 309 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)

Definition at line 310 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 321 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 317 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 323 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 334 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)

Definition at line 335 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 326 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 327 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 328 of file stm32h7xx_ll_adc.h.

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 329 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

Definition at line 330 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */

Definition at line 58 of file stm32h7xx_ll_adc.h.

#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */

Definition at line 57 of file stm32h7xx_ll_adc.h.

#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)

Definition at line 59 of file stm32h7xx_ll_adc.h.

#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */

Definition at line 61 of file stm32h7xx_ll_adc.h.

#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)

Definition at line 60 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_StartCalibration().

#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)

Definition at line 354 of file stm32h7xx_ll_adc.h.

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)

Definition at line 353 of file stm32h7xx_ll_adc.h.

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)

Definition at line 355 of file stm32h7xx_ll_adc.h.

#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)

Definition at line 352 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 239 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER (0x00000000UL)

Definition at line 216 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

Definition at line 262 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)

Definition at line 249 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )

Definition at line 226 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

Definition at line 272 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)

Definition at line 250 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 227 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

Definition at line 273 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)

Definition at line 251 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )

Definition at line 228 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

Definition at line 274 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)

Definition at line 252 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 229 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

Definition at line 275 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)

Definition at line 253 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 230 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

Definition at line 276 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)

Definition at line 254 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 231 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

Definition at line 277 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)

Definition at line 255 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )

Definition at line 232 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

Definition at line 278 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)

Definition at line 256 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)

Definition at line 233 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

Definition at line 279 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)

Definition at line 257 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )

Definition at line 234 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

Definition at line 280 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)

Definition at line 258 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 235 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */

Definition at line 281 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 240 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)

Definition at line 217 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

Definition at line 263 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 241 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )

Definition at line 218 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

Definition at line 264 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 242 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 219 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

Definition at line 265 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 243 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )

Definition at line 220 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

Definition at line 266 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 244 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 221 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

Definition at line 267 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)

Definition at line 245 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 222 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

Definition at line 268 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)

Definition at line 246 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 223 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

Definition at line 269 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)

Definition at line 247 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )

Definition at line 224 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

Definition at line 270 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)

Definition at line 248 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)

Definition at line 225 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

Definition at line 271 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 194 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */

Definition at line 201 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)

Definition at line 202 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 196 of file stm32h7xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

Definition at line 195 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)

Definition at line 193 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetOffset().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

Definition at line 198 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 208 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)

Definition at line 211 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

Definition at line 212 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)

Definition at line 66 of file stm32h7xx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 359 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableDeepPowerDown(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_EnableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_StopConversion(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), and LL_ADC_StartCalibration().

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 113 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData14(), LL_ADC_INJ_ReadConversionData16(), LL_ADC_INJ_ReadConversionData32(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)

Definition at line 119 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)

Definition at line 120 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)

Definition at line 121 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)

Definition at line 122 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 114 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_INJ_TRIG_EDGE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 171 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 158 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

Definition at line 178 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

Definition at line 177 of file stm32h7xx_ll_adc.h.

#define ADC_INJ_TRIG_SOURCE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

Definition at line 163 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_JDR1_REGOFFSET (0x00000000UL)

Definition at line 108 of file stm32h7xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET (0x00000100UL)

Definition at line 109 of file stm32h7xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET (0x00000200UL)

Definition at line 110 of file stm32h7xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET (0x00000300UL)

Definition at line 111 of file stm32h7xx_ll_adc.h.

#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

Definition at line 115 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData14(), LL_ADC_INJ_ReadConversionData16(), LL_ADC_INJ_ReadConversionData32(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))

Definition at line 375 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_LinearCalibration_FactorLoad().

#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))

Definition at line 376 of file stm32h7xx_ll_adc.h.

#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))

Definition at line 377 of file stm32h7xx_ll_adc.h.

#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))

Definition at line 378 of file stm32h7xx_ll_adc.h.

#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))

Definition at line 379 of file stm32h7xx_ll_adc.h.

#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))

Definition at line 380 of file stm32h7xx_ll_adc.h.

#define ADC_LINEAR_CALIB_REG_COUNT (6UL)

Definition at line 381 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_LinearCalibration_FactorLoad(), HAL_ADCEx_LinearCalibration_GetValue(), and HAL_ADCEx_LinearCalibration_SetValue().

#define ADC_OFR1_REGOFFSET (0x00000000UL)

Definition at line 344 of file stm32h7xx_ll_adc.h.

#define ADC_OFR2_REGOFFSET (0x00000001UL)

Definition at line 345 of file stm32h7xx_ll_adc.h.

#define ADC_OFR3_REGOFFSET (0x00000002UL)

Definition at line 346 of file stm32h7xx_ll_adc.h.

#define ADC_OFR4_REGOFFSET (0x00000003UL)

Definition at line 347 of file stm32h7xx_ll_adc.h.

#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

Definition at line 348 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

Definition at line 91 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

Definition at line 92 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

Definition at line 93 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

Definition at line 94 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

Definition at line 95 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

Definition at line 96 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

Definition at line 97 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

Definition at line 82 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

Definition at line 83 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

Definition at line 84 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

Definition at line 85 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

Definition at line 86 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

Definition at line 87 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

Definition at line 88 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

Definition at line 89 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

Definition at line 90 of file stm32h7xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 78 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 76 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

Definition at line 143 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 130 of file stm32h7xx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

Definition at line 150 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

Definition at line 149 of file stm32h7xx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

Definition at line 135 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */

Definition at line 294 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationOffsetFactor(), and LL_ADC_SetCalibrationOffsetFactor().

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */

Definition at line 295 of file stm32h7xx_ll_adc.h.

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

Definition at line 296 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationOffsetFactor(), and LL_ADC_SetCalibrationOffsetFactor().

#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

Definition at line 291 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationOffsetFactor(), and LL_ADC_SetCalibrationOffsetFactor().

#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)

Definition at line 290 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_StartCalibration().

#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

Definition at line 292 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSingleDiff(), and LL_ADC_SetChannelSingleDiff().

#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

Definition at line 293 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_SetChannelSingleDiff().

#define ADC_SMPR1_REGOFFSET (0x00000000UL)

Definition at line 206 of file stm32h7xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET (0x02000000UL)

Definition at line 207 of file stm32h7xx_ll_adc.h.

#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

Definition at line 209 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_SQR1_REGOFFSET (0x00000000UL)

Definition at line 71 of file stm32h7xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET (0x00000100UL)

Definition at line 72 of file stm32h7xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET (0x00000200UL)

Definition at line 73 of file stm32h7xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET (0x00000300UL)

Definition at line 74 of file stm32h7xx_ll_adc.h.

#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

Definition at line 77 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 67 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 68 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define LL_ADC_AWD1_TR LL_ADC_AWD1

Definition at line 338 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD2_TR LL_ADC_AWD2

Definition at line 339 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD3_TR LL_ADC_AWD3

Definition at line 340 of file stm32h7xx_ll_adc.h.

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 367 of file stm32h7xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 369 of file stm32h7xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 368 of file stm32h7xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 370 of file stm32h7xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Definition at line 371 of file stm32h7xx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

Definition at line 364 of file stm32h7xx_ll_adc.h.

#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 365 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 400 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_GetOffsetChannel(), LL_ADC_GetOffsetLevel(), LL_ADC_GetOffsetSignedSaturation(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData14(), LL_ADC_INJ_ReadConversionData16(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAnalogWDThresholds(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetOffset(), and LL_ADC_SetOffsetSignedSaturation().

#define IS_LL_ADC_COMMON_CLOCK ( __CLOCK__ )
Value:
(   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
  )

Definition at line 82 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
  )

Definition at line 254 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
  )

Definition at line 247 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
  )

Definition at line 242 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_EXT_EDGE ( __INJ_TRIG_EXT_EDGE__ )
Value:
(   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
  )

Definition at line 236 of file stm32h7xx_ll_adc.c.

#define IS_LL_ADC_INJ_TRIG_SOURCE ( __INJ_TRIG_SOURCE__ )
Value:
(   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)                \
  )

Definition at line 211 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_LEFT_BIT_SHIFT ( __LEFT_BIT_SHIFT__ )
Value:
(   ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE)                     \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9)                        \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10)                       \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11)                       \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12)                       \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13)                       \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14)                       \
   || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15)                       \
  )

Definition at line 110 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_LOW_POWER ( __LOW_POWER__ )
Value:
(   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
  )

Definition at line 129 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_MULTI_DMA_TRANSFER ( __MULTI_DMA_TRANSFER__ )
Value:
(   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B)            \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B)                \
  )

Definition at line 272 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_MASTER_SLAVE ( __MULTI_MASTER_SLAVE__ )
Value:
(   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
  )

Definition at line 293 of file stm32h7xx_ll_adc.c.

#define IS_LL_ADC_MULTI_MODE ( __MULTI_MODE__ )
Value:
(   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
  )

Definition at line 261 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_TWOSMP_DELAY ( __MULTI_TWOSMP_DELAY__ )
Value:
(   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS)  \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)           \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)           \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)           \
  )

Definition at line 277 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 161 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DATA_TRANSFER_MODE ( __REG_DATA_TRANSFER_MODE__ )
Value:
(   ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER)                 \
   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)        \
   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)      \
   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER)              \
  )

Definition at line 166 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR ( __REG_OVR_DATA_BEHAVIOR__ )
Value:
(   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
  )

Definition at line 173 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
  )

Definition at line 197 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
  )

Definition at line 178 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)                \
  )

Definition at line 136 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(   ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
  )

Definition at line 102 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_Init().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32h7xx_ll_adc.h>

Data Fields

uint32_t | CommonClock
uint32_t | Multimode
uint32_t | MultiDMATransfer
uint32_t | MultiTwoSamplingDelay

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 424 of file stm32h7xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::CommonClock

Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of ADC common - Clock source

Note:
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.

This feature can be modified afterwards using unitary function LL_ADC_SetCommonClock().

Definition at line 426 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiDMATransfer

Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution. This parameter can be a value of Multimode - DMA transfer

This feature can be modified afterwards using unitary function LL_ADC_SetMultiDMATransfer().

Definition at line 439 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::Multimode

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of Multimode - Mode

This feature can be modified afterwards using unitary function LL_ADC_SetMultimode().

Definition at line 434 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay

Set ADC multimode delay between 2 sampling phases. This parameter can be a value of Multimode - Delay between two sampling phases

This feature can be modified afterwards using unitary function LL_ADC_SetMultiTwoSamplingDelay().

Definition at line 444 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32h7xx_ll_adc.h>

Data Fields

uint32_t | Resolution
uint32_t | LeftBitShift
uint32_t | LowPowerMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 471 of file stm32h7xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::LeftBitShift

Configures the left shifting applied to the final result with or without oversampling. This parameter can be a value of ADC left Shift.

Definition at line 478 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::LowPowerMode

Set ADC low power mode. This parameter can be a value of ADC instance - Low power mode

This feature can be modified afterwards using unitary function LL_ADC_SetLowPowerMode().

Definition at line 481 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::Resolution

Set ADC resolution. This parameter can be a value of ADC instance - Resolution

This feature can be modified afterwards using unitary function LL_ADC_SetResolution().

Definition at line 473 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32h7xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DataTransferMode
uint32_t | Overrun

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 507 of file stm32h7xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 529 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DataTransferMode

Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM. This parameter can be a value of ADC group regular - Data transfer mode of ADC conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDataTransferMode().

Definition at line 535 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::Overrun

Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of ADC group regular - Overrun behavior on conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetOverrun().

Definition at line 540 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 522 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 517 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 509 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32h7xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 567 of file stm32h7xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 582 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 577 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 589 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 569 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag ADC instance ready

Definition at line 611 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_ADRDY(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_ADRDY().

#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST

ADC flag ADC multimode master instance ready

Definition at line 622 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_ADRDY().

#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV

ADC flag ADC multimode slave instance ready

Definition at line 623 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_ADRDY().

#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag ADC analog watchdog 1

Definition at line 619 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD1().

#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST

ADC flag ADC multimode master analog watchdog 1 of the ADC master

Definition at line 638 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD1().

#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV

ADC flag ADC multimode slave analog watchdog 1 of the ADC slave

Definition at line 639 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD1().

#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag ADC analog watchdog 2

Definition at line 620 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD2(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD2().

#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST

ADC flag ADC multimode master analog watchdog 2 of the ADC master

Definition at line 640 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD2().

#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV

ADC flag ADC multimode slave analog watchdog 2 of the ADC slave

Definition at line 641 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD2().

#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag ADC analog watchdog 3

Definition at line 621 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD3(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD3().

#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST

ADC flag ADC multimode master analog watchdog 3 of the ADC master

Definition at line 642 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD3().

#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

ADC flag ADC multimode slave analog watchdog 3 of the ADC slave

Definition at line 643 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD3().

#define LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag ADC group regular end of unitary conversion

Definition at line 612 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOC(), and LL_ADC_DeInit().

#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST

ADC flag ADC multimode master group regular end of unitary conversion

Definition at line 624 of file stm32h7xx_ll_adc.h.

#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV

ADC flag ADC multimode slave group regular end of unitary conversion

Definition at line 625 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOC(), and LL_ADC_IsActiveFlag_SLV_EOC().

#define LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag ADC group regular end of sequence conversions

Definition at line 613 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST

ADC flag ADC multimode master group regular end of sequence conversions

Definition at line 626 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOS().

#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV

ADC flag ADC multimode slave group regular end of sequence conversions

Definition at line 627 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOS().

#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag ADC group regular end of sampling phase

Definition at line 615 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOSMP(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOSMP().

#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST

ADC flag ADC multimode master group regular end of sampling phase

Definition at line 630 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOSMP().

#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV

ADC flag ADC multimode slave group regular end of sampling phase

Definition at line 631 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOSMP().

#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC

ADC flag ADC group injected end of unitary conversion

Definition at line 616 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOC(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOC().

#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST

ADC flag ADC multimode master group injected end of unitary conversion

Definition at line 632 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOC().

#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV

ADC flag ADC multimode slave group injected end of unitary conversion

Definition at line 633 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOC().

#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS

ADC flag ADC group injected end of sequence conversions

Definition at line 617 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOS().

#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST

ADC flag ADC multimode master group injected end of sequence conversions

Definition at line 634 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOS().

#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV

ADC flag ADC multimode slave group injected end of sequence conversions

Definition at line 635 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOS().

#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC flag ADC group injected contexts queue overflow

Definition at line 618 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JQOVF(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JQOVF().

#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST

ADC flag ADC multimode master group injected contexts queue overflow

Definition at line 636 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JQOVF().

#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV

ADC flag ADC multimode slave group injected contexts queue overflow

Definition at line 637 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JQOVF().

#define LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag ADC group regular overrun

Definition at line 614 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_OVR(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_OVR().

#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST

ADC flag ADC multimode master group regular overrun

Definition at line 628 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_OVR().

#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV

ADC flag ADC multimode slave group regular overrun

Definition at line 629 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_OVR().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption ADC instance ready

Definition at line 652 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_ADRDY(), LL_ADC_EnableIT_ADRDY(), and LL_ADC_IsEnabledIT_ADRDY().

#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption ADC analog watchdog 1

Definition at line 660 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption ADC analog watchdog 2

Definition at line 661 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD2(), LL_ADC_EnableIT_AWD2(), and LL_ADC_IsEnabledIT_AWD2().

#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption ADC analog watchdog 3

Definition at line 662 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD3(), and LL_ADC_IsEnabledIT_AWD3().

#define LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption ADC group regular end of unitary conversion

Definition at line 653 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOC(), LL_ADC_EnableIT_EOC(), and LL_ADC_IsEnabledIT_EOC().

#define LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption ADC group regular end of sequence conversions

Definition at line 654 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOS(), LL_ADC_EnableIT_EOS(), and LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption ADC group regular end of sampling phase

Definition at line 656 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOSMP(), LL_ADC_EnableIT_EOSMP(), and LL_ADC_IsEnabledIT_EOSMP().

#define LL_ADC_IT_JEOC ADC_IER_JEOCIE

ADC interruption ADC group injected end of unitary conversion

Definition at line 657 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOC(), LL_ADC_EnableIT_JEOC(), and LL_ADC_IsEnabledIT_JEOC().

#define LL_ADC_IT_JEOS ADC_IER_JEOSIE

ADC interruption ADC group injected end of sequence conversions

Definition at line 658 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOS(), LL_ADC_EnableIT_JEOS(), and LL_ADC_IsEnabledIT_JEOS().

#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC interruption ADC group injected contexts queue overflow

Definition at line 659 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JQOVF(), LL_ADC_EnableIT_JQOVF(), and LL_ADC_IsEnabledIT_JQOVF().

#define LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption ADC group regular overrun

Definition at line 655 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_OVR(), LL_ADC_EnableIT_OVR(), and LL_ADC_IsEnabledIT_OVR().

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STM32H7B3xQ HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define | LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 673 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DMA_GetRegAddr().

#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Definition at line 674 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

Define Documentation

#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)

ADC asynchronous clock without prescaler

Definition at line 685 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10

Definition at line 690 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 12

Definition at line 691 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128

Definition at line 695 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 16

Definition at line 692 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2

Definition at line 686 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 256

Definition at line 696 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32

Definition at line 693 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 4

Definition at line 687 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6

Definition at line 688 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64

Definition at line 694 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )

ADC asynchronous clock with prescaler division by 8

Definition at line 689 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 682 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 683 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 684 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)

ADC measurement pathes all disabled

Definition at line 709 of file stm32h7xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)

ADC measurement path to internal channel temperature sensor

Definition at line 711 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

ADC measurement path to internal channel Vbat

Definition at line 712 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

Definition at line 710 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32H7B3xQ HAL User Manual: ADC instance - Boost mode

Defines
ADC instance - Boost mode
ADC Exported Constants

Defines

#define | LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL)
#define | LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0)
#define | LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 )
#define | LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 )
#define | LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)

Define Documentation

#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0)

Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz

Definition at line 721 of file stm32h7xx_ll_adc.h.

#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 )

Boost mode is configured for 12.5Mhz < frequency <= 20Mhz

Definition at line 722 of file stm32h7xx_ll_adc.h.

#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 )

Boost mode is configured for 20Mhz < frequency <= 25Mhz

Definition at line 723 of file stm32h7xx_ll_adc.h.

#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)

Boost mode is configured for frequency > 25Mhz

Definition at line 724 of file stm32h7xx_ll_adc.h.

#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL)

Boost mode is configured for frequency <= 6.25Mhz

Definition at line 720 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC instance - Calibration mode for offset and linearity

Defines
ADC instance - Calibration mode for offset and linearity
ADC Exported Constants

Defines

#define | LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)
#define | LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
#define | LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN)

Define Documentation

#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)

Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes.

Definition at line 733 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)

Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes.

Definition at line 732 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN)

Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes.

Definition at line 734 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC instance - Calibration linearity words

Defines
ADC instance - Calibration linearity words
ADC Exported Constants

Defines

#define | LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1)
#define | LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2)
#define | LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3)
#define | LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4)
#define | LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5)
#define | LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6)

Define Documentation

#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1)

ADC calibration linearity word 1

Definition at line 742 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2)

ADC calibration linearity word 2

Definition at line 743 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3)

ADC calibration linearity word 3

Definition at line 744 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4)

ADC calibration linearity word 4

Definition at line 745 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5)

ADC calibration linearity word 5

Definition at line 746 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6)

ADC calibration linearity word 6

Definition at line 747 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | LL_ADC_RESOLUTION_16B (0x00000000UL)
#define | LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

Define Documentation

#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

ADC resolution 10 bits

Definition at line 758 of file stm32h7xx_ll_adc.h.

#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 )

ADC resolution 12 bits

Definition at line 757 of file stm32h7xx_ll_adc.h.

#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0)

ADC resolution 12 bits

Definition at line 756 of file stm32h7xx_ll_adc.h.

#define LL_ADC_RESOLUTION_16B (0x00000000UL)

ADC resolution 16 bits

Definition at line 755 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

ADC resolution 8 bits

Definition at line 760 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetResolution(), and LL_ADC_SetResolution().

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STM32H7B3xQ HAL User Manual: ADC left Shift

Defines
ADC left Shift
ADC Exported Constants

Defines

#define | LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)
#define | LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)
#define | LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)
#define | LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

Define Documentation

#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)

ADC 1 bit shift left applied on the final ADC convesion data

Definition at line 772 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)

ADC 10 bits shift left applied on the final ADC convesion data

Definition at line 781 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

ADC 11 bits shift left applied on the final ADC convesion data

Definition at line 782 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)

ADC 12 bits shift left applied on the final ADC convesion data

Definition at line 783 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)

ADC 13 bits shift left applied on the final ADC convesion data

Definition at line 784 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)

ADC 14 bits shift left applied on the final ADC convesion data

Definition at line 785 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

ADC 15 bits shift left applied on the final ADC convesion data

Definition at line 786 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)

ADC 2 bits shift left applied on the final ADC convesion data

Definition at line 773 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

ADC 3 bits shift left applied on the final ADC convesion data

Definition at line 774 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)

ADC 4 bits shift left applied on the final ADC convesion data

Definition at line 775 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)

ADC 5 bits shift left applied on the final ADC convesion data

Definition at line 776 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)

ADC 6 bits shift left applied on the final ADC convesion data

Definition at line 777 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

ADC 7 bits shift left applied on the final ADC convesion data

Definition at line 778 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)

ADC 8 bits shift left applied on the final ADC convesion data

Definition at line 779 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)

ADC 9 bits shift left applied on the final ADC convesion data

Definition at line 780 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)

ADC no bit shift left applied on the final ADC convesion data

Definition at line 771 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32H7B3xQ HAL User Manual: ADC instance - Low power mode

Defines
ADC instance - Low power mode
ADC Exported Constants

Defines

#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

Define Documentation

#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode().

Definition at line 795 of file stm32h7xx_ll_adc.h.

#define LL_ADC_LP_MODE_NONE (0x00000000UL)

No ADC low power mode activated

Definition at line 794 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32H7B3xQ HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

Define Documentation

#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 803 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 804 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 805 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 806 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Offset signed saturation mode

Defines
ADC instance - Offset signed saturation mode
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE)

Define Documentation

#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)

ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 814 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE)

ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 815 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Offset right shift

Defines
ADC instance - Offset right shift
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1)

Define Documentation

#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL)

ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 823 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1)

ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 824 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

Define Documentation

#define LL_ADC_GROUP_INJECTED (0x00000002UL)

ADC group injected (not available on all STM32 devices)

Definition at line 832 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR (0x00000001UL)

ADC group regular (available on all STM32 devices)

Definition at line 831 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

ADC both groups regular and injected

Definition at line 833 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 841 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 842 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 851 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 852 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 853 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 854 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 855 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 856 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 857 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 858 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 859 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN19 Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX

Definition at line 860 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 843 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 844 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 845 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 846 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 847 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 848 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 849 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 850 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to DAC1 channel 1, channel specific to ADC2

Definition at line 872 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX

Definition at line 873 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to DAC2 channel 1, channel specific to ADC2

Definition at line 876 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2.

Definition at line 869 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2.

Definition at line 870 of file stm32h7xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2.

Definition at line 868 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting).

Definition at line 892 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting).

Definition at line 902 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting).

Definition at line 903 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 904 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 905 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting).

Definition at line 906 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 900 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 886 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 887 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 888 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 895 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 896 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 889 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 897 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 901 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 890 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 891 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 898 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 899 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 893 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 894 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)

ADC group regular conversion trigger internal: SW start.

Definition at line 885 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )

ADC group regular conversion trigger polarity set to falling edge

Definition at line 915 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 914 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 916 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 925 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 924 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group regular - Data transfer mode of ADC conversion data

Defines
ADC group regular - Data transfer mode of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DR_TRANSFER (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0)
#define | LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 )

Define Documentation

#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 )

ADC conversion data are transferred to DFSDM

Definition at line 936 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

Definition at line 934 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 935 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_DR_TRANSFER (0x00000000UL)

ADC conversions are transferred to DR rigister

Definition at line 933 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

Define Documentation

#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 945 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)

ADC group regular behavior in case of overrun: data preserved

Definition at line 944 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 953 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 962 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 963 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 964 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 965 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 966 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 15 ranks in the sequence

Definition at line 967 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 968 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 954 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 955 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 956 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 957 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 958 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 959 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 960 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 961 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 977 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 978 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 979 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 980 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 981 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 982 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 983 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 984 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group regular sequencer discontinuous mode disable

Definition at line 976 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 992 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 1001 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 1002 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 1003 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 1004 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 1005 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 1006 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 1007 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 993 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 994 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 995 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 996 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 997 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 998 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 999 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 1000 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 1022 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting).

Definition at line 1032 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting).

Definition at line 1033 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 1034 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting).

Definition at line 1035 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1036 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1031 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1017 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1016 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 1024 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1019 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1018 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1029 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1027 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1020 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1028 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1021 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1030 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1023 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting).

Definition at line 1025 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting).

Definition at line 1026 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)

ADC group injected conversion trigger internal: SW start.

Definition at line 1015 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_IsTriggerSourceSWStart(), and LL_ADC_INJ_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )

ADC group injected conversion trigger polarity set to falling edge

Definition at line 1045 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to rising edge

Definition at line 1044 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to both rising and falling edges

Definition at line 1046 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 1055 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 1054 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and LL_ADC_INJ_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group injected - Context queue mode

Defines
ADC group injected - Context queue mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Define Documentation

#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

Definition at line 1064 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

Definition at line 1063 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Definition at line 1065 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue().

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STM32H7B3xQ HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 1073 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 1074 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 1075 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 1076 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 1085 of file stm32h7xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group injected sequencer discontinuous mode disable

Definition at line 1084 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32H7B3xQ HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

Define Documentation

#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 1

Definition at line 1093 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 2

Definition at line 1094 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 3

Definition at line 1095 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 4

Definition at line 1096 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

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STM32H7B3xQ HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 16.5 ADC clock cycles

Definition at line 1107 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)

Sampling time 1.5 ADC clock cycles

Definition at line 1104 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0)

Sampling time 2.5 ADC clock cycles

Definition at line 1105 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 )

Sampling time 32.5 ADC clock cycles

Definition at line 1108 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )

Sampling time 387.5 ADC clock cycles

Definition at line 1110 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)

Sampling time 64.5 ADC clock cycles

Definition at line 1109 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 810.5 ADC clock cycles

Definition at line 1111 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 )

Sampling time 8.5 ADC clock cycles

Definition at line 1106 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Exported Constants

Defines

#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to both single ended and differential (literal used only to set calibration factors)

Definition at line 1121 of file stm32h7xx_ll_adc.h.

#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 1120 of file stm32h7xx_ll_adc.h.

#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 1119 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 1129 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and LL_ADC_GetAnalogWDMonitChannels().

#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)

ADC analog watchdog number 2

Definition at line 1130 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

ADC analog watchdog number 3

Definition at line 1131 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 1141 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 1140 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 1142 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only

Definition at line 1213 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only

Definition at line 1212 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected

Definition at line 1214 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only

Definition at line 1216 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only

Definition at line 1215 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected

Definition at line 1217 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only

Definition at line 1207 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 1206 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected

Definition at line 1208 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only

Definition at line 1210 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only

Definition at line 1209 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda

Definition at line 1211 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 1204 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 1203 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 1205 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only

Definition at line 1144 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 1143 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected

Definition at line 1145 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only

Definition at line 1174 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 1173 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected

Definition at line 1175 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only

Definition at line 1177 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 1176 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected

Definition at line 1178 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only

Definition at line 1180 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 1179 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected

Definition at line 1181 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only

Definition at line 1183 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 1182 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected

Definition at line 1184 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only

Definition at line 1186 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 1185 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected

Definition at line 1187 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only

Definition at line 1189 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 1188 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected

Definition at line 1190 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only

Definition at line 1192 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 1191 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected

Definition at line 1193 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only

Definition at line 1195 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 1194 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected

Definition at line 1196 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only

Definition at line 1198 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only

Definition at line 1197 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected

Definition at line 1199 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only

Definition at line 1201 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only

Definition at line 1200 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected

Definition at line 1202 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only

Definition at line 1147 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 1146 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected

Definition at line 1148 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only

Definition at line 1150 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 1149 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected

Definition at line 1151 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only

Definition at line 1153 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 1152 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected

Definition at line 1154 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only

Definition at line 1156 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 1155 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected

Definition at line 1157 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only

Definition at line 1159 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 1158 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected

Definition at line 1160 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only

Definition at line 1162 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 1161 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected

Definition at line 1163 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only

Definition at line 1165 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 1164 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected

Definition at line 1166 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only

Definition at line 1168 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 1167 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected

Definition at line 1169 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only

Definition at line 1171 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 1170 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected

Definition at line 1172 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE (0x00000000UL)

ADC analog watchdog monitoring disabled

Definition at line 1139 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)
#define | LL_ADC_AWD_THRESHOLD_LOW (0x0UL)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)

ADC analog watchdog threshold high

Definition at line 1225 of file stm32h7xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL)

ADC analog watchdog threshold low

Definition at line 1226 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Oversampling - Oversampling scope

Defines
Oversampling - Oversampling scope
ADC Exported Constants

Defines

#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

Define Documentation

#define LL_ADC_OVS_DISABLE (0x00000000UL)

ADC oversampling disabled.

Definition at line 1234 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1238 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )

ADC oversampling on conversions of ADC group injected.

Definition at line 1237 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards.

Definition at line 1235 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1236 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

Define Documentation

#define LL_ADC_OVS_REG_CONT (0x00000000UL)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 1246 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 1247 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define | LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

Define Documentation

#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 1255 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 1256 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data)

Definition at line 1265 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data)

Definition at line 1266 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 1257 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 1258 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 1259 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 1260 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 1261 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 1262 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 1263 of file stm32h7xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data)

Definition at line 1264 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Multimode - Mode

Defines
Multimode - Mode
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

Define Documentation

#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)

Definition at line 1278 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected simultaneous

Definition at line 1277 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Definition at line 1281 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved

Definition at line 1276 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 1280 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 1279 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )

ADC dual mode enabled: group regular simultaneous

Definition at line 1275 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL)

ADC dual mode disabled (ADC independent mode)

Definition at line 1274 of file stm32h7xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Multimode - DMA transfer

Defines
Multimode - DMA transfer
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
#define | LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 )
#define | LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)

Define Documentation

#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)

ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings

Definition at line 1289 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 )

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits

Definition at line 1290 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits

Definition at line 1291 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Multimode - Delay between two sampling phases

Defines
Multimode - Delay between two sampling phases
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )

Define Documentation

#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL)

ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution

Definition at line 1299 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution

Definition at line 1300 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 )

ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution

Definition at line 1301 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution

Definition at line 1302 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution

Definition at line 1303 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 )

ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution

Definition at line 1304 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution

Definition at line 1305 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 )

ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution

Definition at line 1306 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution

Definition at line 1307 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution

Definition at line 1308 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution

Definition at line 1309 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 )

ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution

Definition at line 1310 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )

ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution

Definition at line 1311 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Multimode - ADC master or slave

Defines
Multimode - ADC master or slave
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)

Define Documentation

#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: ADC master

Definition at line 1319 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: both ADC master and ADC slave

Definition at line 1321 of file stm32h7xx_ll_adc.h.

#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )

In multimode, selection among several ADC instances: ADC slave

Definition at line 1320 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US (5UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
#define | ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL)

Detailed Description

Note:
Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL)

ADC linearity set/clear bit delay

Definition at line 1389 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationLinearFactor(), and LL_ADC_SetCalibrationLinearFactor().

#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)

Delay required between ADC end of calibration and ADC enable

Definition at line 1379 of file stm32h7xx_ll_adc.h.

#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)

Delay for ADC stabilization time (ADC voltage regulator start-up time)

Definition at line 1358 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_Init().

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL)

Delay for temperature sensor stabilization time

Definition at line 1370 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_DELAY_VREFINT_STAB_US (5UL)

Delay for internal voltage reference stabilization time

Definition at line 1364 of file stm32h7xx_ll_adc.h.

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STM32H7B3xQ HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1424 of file stm32h7xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1416 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__)
Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
   :                                                                                                      \
   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
   :                                                                                                      \
   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CHANNEL_19_REG (0)
  • LL_ADC_AWD_CHANNEL_19_INJ (0)
  • LL_ADC_AWD_CHANNEL_19_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)(1)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
  • LL_ADC_AWD_CH_VBAT_REG (0)(1)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(1)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (1)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
(0) On STM32H7, parameter available only on analog watchdog number: AWD1.
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.

Definition at line 1855 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_16_BITS__
 | ) | ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 18 bits): < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
__AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
Return values:
Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

Definition at line 1908 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.

Note:
To be used with function LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 18 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
__AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
Return values:
Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

Definition at line 1885 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
  )

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 16 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 2084 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                    (__ADC_RESOLUTION__),          \
                                                    LL_ADC_RESOLUTION_16B)         \
                   * (__VREFANALOG_VOLTAGE__))                                     \
                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
   ) + TEMPSENSOR_CAL1_TEMP                                                        \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 16 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 16 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2170 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((( (                                                                        \
       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
                 * 1000UL)                                                     \
       -                                                                       \
       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
                 * 1000UL)                                                     \
      )                                                                        \
    ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \
   ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 16 bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 16 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32H7, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2229 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
   / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
                                      (__ADC_RESOLUTION__),                    \
                                      LL_ADC_RESOLUTION_16B))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 16 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 16 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
Analog reference voltage (unit: mV)

Definition at line 2117 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF | ( | __CALIB_FACTOR_SINGLE_ENDED__,
 |  | __CALIB_FACTOR_DIFFERENTIAL__
 | ) | (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.

Note:
To be used with function LL_ADC_SetCalibrationOffsetFactor(). Example, to set calibration factors single ended to 0x55 and differential ended to 0x2A: LL_ADC_SetCalibrationOffsetFactor( ADC1, __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
Parameters:
__CALIB_FACTOR_SINGLE_ENDED__ | Value between Min_Data=0x00 and Max_Data=0x7F
__CALIB_FACTOR_DIFFERENTIAL__ | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 1924 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19

Definition at line 1663 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ )
Value:
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \
   ? (                                                                                     \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
     )                                                                                     \
   :                                                                                       \
   (                                                                                       \
       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
   )                                                                                       \
  )

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1475 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADCEx_InjectedConfigChannel(), and LL_ADC_GetAnalogWDMonitChannels().

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC12_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1985 of file stm32h7xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), and LL_ADC_DMA_GetRegAddr().

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
  )

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
ADC conversion data to the requested resolution

Definition at line 2059 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9UL)                                                                            \
   ? (                                                                                                  \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \
       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
     )                                                                                                  \
   :                                                                                                    \
   (                                                                                                    \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \
       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
   )                                                                                                    \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1528 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

Definition at line 2036 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1594 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((__ADC_INSTANCE__) == ADC2)                                               \
    &&(                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \
       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) ||                       \
       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
      )                                                                        \
   )                                                                           \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1710 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 2018 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_MultiModeConfigChannel(), and LL_ADC_CommonInit().

#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled: refer to function LL_ADC_SetMultiDMATransfer(). In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1940 of file stm32h7xx_ll_adc.h.

#define __LL_ADC_MULTI_INSTANCE_MASTER ( __ADCx__ )
Value:
( ( ((__ADCx__) == ADC2)                                                     \
    )?                                                                         \
     (ADC1)                                                                    \
     :                                                                         \
     (__ADCx__)                                                                \
  )

Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).

Note:
In case of device with multimode available and a mix of ADC instances compliant and not compliant with multimode feature, ADC instances not compliant with multimode feature are considered as master instances (do not depend to any other ADC instance).
Parameters:
__ADCx__ ADC instance
Return values:
__ADCx__ ADC instance master of the corresponding ADC common instance

Definition at line 1955 of file stm32h7xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_DMA_GetRegAddr
CDR RDATA_MST LL_ADC_DMA_GetRegAddr
CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
(1) Available on devices with several ADC instances.
Return values:
ADC register address

Definition at line 2295 of file stm32h7xx_ll_adc.h.

References __LL_ADC_COMMON_INSTANCE, and LL_ADC_DMA_REG_REGULAR_DATA.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonClock ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: Clock source and prescaler.

Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_GetCommonClock
CCR PRESC LL_ADC_GetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256

Definition at line 2383 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_GetCommonPathInternalCh
CCR TSEN LL_ADC_GetCommonPathInternalCh
CCR VBATEN LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT

Definition at line 2445 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonClock | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonClock
 | ) |  |

Set parameter common to several ADC: Clock source and prescaler.

Note:
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_SetCommonClock
CCR PRESC LL_ADC_SetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonClock This parameter can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256
Return values:
None

Definition at line 2355 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literal LL_ADC_DELAY_TEMPSENSOR_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalCh
CCR TSEN LL_ADC_SetCommonPathInternalCh
CCR VBATEN LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 2423 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCalibrationOffsetFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationOffsetFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetCalibrationLinearFactor (ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
Set ADC Linear calibration factor in the mode single-ended.
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationLinearFactor (ADC_TypeDef *ADCx, uint32_t LinearityWord)
Get ADC Linear calibration factor in the mode single-ended.
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetDataRightShift (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
Set data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE uint32_t | LL_ADC_GetDataRightShift (ADC_TypeDef *ADCx, uint32_t Offsety)
Get data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE void | LL_ADC_SetOffsetSignedSaturation (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
Set signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSignedSaturation (ADC_TypeDef *ADCx, uint32_t Offsety)
Get signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LinearityWord
 | ) |  |

Get ADC Linear calibration factor in the mode single-ended.

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
Reference Manual to LL API cross reference:
CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
Parameters:
ADCx ADC instance
LinearityWord This parameter can be one of the following values:
  • LL_ADC_CALIB_LINEARITY_WORD1
  • LL_ADC_CALIB_LINEARITY_WORD2
  • LL_ADC_CALIB_LINEARITY_WORD3
  • LL_ADC_CALIB_LINEARITY_WORD4
  • LL_ADC_CALIB_LINEARITY_WORD5
  • LL_ADC_CALIB_LINEARITY_WORD6
Return values:
Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

Definition at line 2575 of file stm32h7xx_ll_adc.h.

References ADC_LINEARITY_BIT_TOGGLE_TIMEOUT.

Referenced by HAL_ADCEx_LinearCalibration_GetValue().

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes Calibration of linearity is common to both single-ended and differential modes
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor
CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
Value between Min_Data=0x00 and Max_Data=0x7F

Definition at line 2517 of file stm32h7xx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK, ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4, and ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

Referenced by HAL_ADCEx_Calibration_GetValue().

__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.

Reference Manual to LL API cross reference:
CFGR2 RSHIFT LL_ADC_GetDataRightShift
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_RSHIFT_ENABLE
  • LL_ADC_OFFSET_RSHIFT_DISABLE

Definition at line 2976 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode ( ADC_TypeDef * ADCx )

Get ADC low power mode:

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_GetLowPowerMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT

Definition at line 2758 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
On STM32H7, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN0..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2908 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Referenced by HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).

Note:
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
OFR1 OFFSET1 LL_ADC_GetOffsetLevel
OFR2 OFFSET2 LL_ADC_GetOffsetLevel
OFR3 OFFSET3 LL_ADC_GetOffsetLevel
OFR4 OFFSET4 LL_ADC_GetOffsetLevel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

Definition at line 2934 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.

Reference Manual to LL API cross reference:
OFR1 SSATE LL_ADC_GetOffsetSignedSaturation
OFR2 SSATE LL_ADC_GetOffsetSignedSaturation
OFR3 SSATE LL_ADC_GetOffsetSignedSaturation
OFR4 SSATE LL_ADC_GetOffsetSignedSaturation
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
  • LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

Definition at line 3022 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetResolution ( ADC_TypeDef * ADCx )

Get ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Reference Manual to LL API cross reference:
CFGR RES LL_ADC_GetResolution
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B

Definition at line 2639 of file stm32h7xx_ll_adc.h.

References LL_ADC_RESOLUTION_8B.

__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LinearityWord,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC Linear calibration factor in the mode single-ended.

Note:
This function is intended to set linear calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
Parameters:
ADCx | ADC instance
LinearityWord This parameter can be one of the following values:
  • LL_ADC_CALIB_LINEARITY_WORD1
  • LL_ADC_CALIB_LINEARITY_WORD2
  • LL_ADC_CALIB_LINEARITY_WORD3
  • LL_ADC_CALIB_LINEARITY_WORD4
  • LL_ADC_CALIB_LINEARITY_WORD5
  • LL_ADC_CALIB_LINEARITY_WORD6
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
Return values:
None

Definition at line 2548 of file stm32h7xx_ll_adc.h.

References ADC_LINEARITY_BIT_TOGGLE_TIMEOUT.

Referenced by HAL_ADCEx_LinearCalibration_SetValue().

__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
This function is intended to set calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration factor must be specified for each of these differential modes, if used afterwards and if the application requires their calibration). Calibration of linearity is common to both single-ended and differential modes (calibration factor can be specified only once).
In case of setting calibration factors of both modes single ended and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): both calibration factors must be concatenated. To perform this processing, use helper macro __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor
CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
Parameters:
ADCx | ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
None

Definition at line 2492 of file stm32h7xx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK, ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4, and ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

Referenced by HAL_ADCEx_Calibration_SetValue().

__STATIC_INLINE void LL_ADC_SetDataRightShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | RigthShift
 | ) |  |

Set data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.

Reference Manual to LL API cross reference:
CFGR2 RSHIFT LL_ADC_SetDataRightShift
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
RigthShift This parameter can be one of the following values:
  • LL_ADC_OFFSET_RSHIFT_ENABLE
  • LL_ADC_OFFSET_RSHIFT_DISABLE
Return values:
Returned None

Definition at line 2957 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetLowPowerMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LowPowerMode
 | ) |  |

Set ADC low power mode.

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_SetLowPowerMode
Parameters:
ADCx ADC instance
LowPowerMode This parameter can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
Return values:
None

Definition at line 2710 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | Channel,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC selected offset number 1, 2, 3 or 4.

Note:
This function set the 2 items of offset configuration:
  • ADC channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
  • Offset level (offset to be subtracted from the raw converted data).
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
This function enables the offset, by default. It can be forced to disable state using function LL_ADC_SetOffsetState().
If a channel is mapped on several offsets numbers, only the offset with the lowest value is considered for the subtraction.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
On STM32H7, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN0..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_SetOffset
OFR1 OFFSET1 LL_ADC_SetOffset
OFR1 OFFSET1_EN LL_ADC_SetOffset
OFR2 OFFSET2_CH LL_ADC_SetOffset
OFR2 OFFSET2 LL_ADC_SetOffset
OFR2 OFFSET2_EN LL_ADC_SetOffset
OFR3 OFFSET3_CH LL_ADC_SetOffset
OFR3 OFFSET3 LL_ADC_SetOffset
OFR3 OFFSET3_EN LL_ADC_SetOffset
OFR4 OFFSET4_CH LL_ADC_SetOffset
OFR4 OFFSET4 LL_ADC_SetOffset
OFR4 OFFSET4_EN LL_ADC_SetOffset
Parameters:
ADCx | ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
Return values:
None

Definition at line 2836 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and ADC_CHANNEL_ID_NUMBER_MASK.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetSignedSaturation
 | ) |  |

Set signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.

Reference Manual to LL API cross reference:
OFR1 SSATE LL_ADC_SetOffsetSignedSaturation
OFR2 SSATE LL_ADC_SetOffsetSignedSaturation
OFR3 SSATE LL_ADC_SetOffsetSignedSaturation
OFR4 SSATE LL_ADC_SetOffsetSignedSaturation
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetSignedSaturation This parameter can be one of the following values:
  • LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
  • LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
Return values:
Returned None

Definition at line 2999 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetResolution | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Resolution
 | ) |  |

Set ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR RES LL_ADC_SetResolution
Parameters:
ADCx ADC instance
Resolution This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_16B
  • LL_ADC_RESOLUTION_14B
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
Return values:
None

Definition at line 2603 of file stm32h7xx_ll_adc.h.

References LL_ADC_RESOLUTION_8B.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDataTransferMode (ADC_TypeDef *ADCx, uint32_t DataTransferMode)
Set ADC data transfer mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDataTransferMode (ADC_TypeDef *ADCx)
Get ADC data transfer mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 3594 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode ( ADC_TypeDef * ADCx )

Get ADC data transfer mode.

Note:
Conversion data can be either:
  • Available in Data Register
  • Transfered by DMA in one shot mode
  • Transfered by DMA in circular mode
  • Transfered to DFSDM data register
Reference Manual to LL API cross reference:
CFGR DMNGT LL_ADC_REG_GetDataTransferMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DR_TRANSFER
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
  • LL_ADC_REG_DFSDM_TRANSFER

Definition at line 3635 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun ( ADC_TypeDef * ADCx )

Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_GetOverrun
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 3675 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 3354 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 3299 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 3548 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 3186 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_GetTriggerSource
CFGR EXTEN LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
  • LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
  • LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
  • LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

Definition at line 3124 of file stm32h7xx_ll_adc.h.

References ADC_REG_TRIG_EDGE_MASK, ADC_REG_TRIG_EXTEN_BITOFFSET_POS, and ADC_REG_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3151 of file stm32h7xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 3577 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataTransferMode
 | ) |  |

Set ADC data transfer mode.

Note:
Conversion data can be either:
  • Available in Data Register
  • Transfered by DMA in one shot mode
  • Transfered by DMA in circular mode
  • Transfered to DFSDM data register
Reference Manual to LL API cross reference:
CFGR DMNGT LL_ADC_REG_SetDataTransferMode
Parameters:
ADCx ADC instance
DataTransferMode This parameter can be one of the following values:
  • LL_ADC_REG_DR_TRANSFER
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
  • LL_ADC_REG_DFSDM_TRANSFER
Return values:
None

Definition at line 3614 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_Start_DMA().

__STATIC_INLINE void LL_ADC_REG_SetOverrun | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Overrun
 | ) |  |

Set ADC group regular behavior in case of overrun: data preserved or overwritten.

Note:
Compatibility with devices without feature overrun: other devices without this feature have a behavior equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_SetOverrun
Parameters:
ADCx ADC instance
Overrun This parameter can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN
Return values:
None

Definition at line 3661 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 3331 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 3245 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
None

Definition at line 3446 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 3171 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_SetTriggerSource
CFGR EXTEN LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
  • LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
  • LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
  • LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
Return values:
None

Definition at line 3080 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.

Function Documentation

__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource,
 |  | uint32_t | ExternalTriggerEdge,
 |  | uint32_t | SequencerNbRanks,
 |  | uint32_t | Rank1_Channel,
 |  | uint32_t | Rank2_Channel,
 |  | uint32_t | Rank3_Channel,
 |  | uint32_t | Rank4_Channel
 | ) |  |

Set one context on ADC group injected that will be checked in contexts queue.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks This function is intended to be used when contexts queue is enabled, because the sequence must be fully configured in one time (functions to set separately injected trigger and sequencer channels cannot be used): Refer to function LL_ADC_INJ_SetQueueMode().
In the contexts queue, only the active context can be read. The parameters of this function can be read using functions:
  • LL_ADC_INJ_GetTriggerSource()
  • LL_ADC_INJ_GetTriggerEdge()
  • LL_ADC_INJ_GetSequencerRanks()
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32H7, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN0..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
JSQR JL LL_ADC_INJ_ConfigQueueContext
JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Note: This parameter is discarded in case of SW start: parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Rank1_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Rank2_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Rank3_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Rank4_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
None

Definition at line 4367 of file stm32h7xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_INJ_RANK_ID_JSQR_MASK, LL_ADC_INJ_RANK_1, LL_ADC_INJ_RANK_2, LL_ADC_INJ_RANK_3, LL_ADC_INJ_RANK_4, and LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode ( ADC_TypeDef * ADCx )

Get ADC group injected context queue mode.

Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_GetQueueMode
CFGR JQDIS LL_ADC_INJ_GetQueueMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Definition at line 4166 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 3918 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 3885 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
(1, 2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 4053 of file stm32h7xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 4105 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Definition at line 3838 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

Definition at line 3776 of file stm32h7xx_ll_adc.h.

References ADC_INJ_TRIG_EDGE_MASK, ADC_INJ_TRIG_EXTEN_BITOFFSET_POS, and ADC_INJ_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3803 of file stm32h7xx_ll_adc.h.

References LL_ADC_INJ_TRIG_SOFTWARE.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_INJ_SetQueueMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | QueueMode
 | ) |  |

Set ADC group injected contexts queue mode.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks If contexts queue is disabled:
  • only 1 sequence can be configured and is active perpetually. If contexts queue is enabled:
  • up to 2 contexts can be queued and are checked in and out as a FIFO stack (first-in, first-out).
  • If a new context is set when queues is full, error is triggered by interruption "Injected Queue Overflow".
  • Two behaviors are possible when all contexts have been processed: the contexts queue can maintain the last context active perpetually or can be empty and injected group triggers are disabled.
  • Triggers can be only external (not internal SW start)
  • Caution: The sequence must be fully configured in one time (one write of register JSQR makes a check-in of a new context into the queue). Therefore functions to set separately injected trigger and sequencer channels cannot be used, register JSQR must be set using function LL_ADC_INJ_ConfigQueueContext().
This parameter can be modified only when no conversion is on going on either groups regular or injected.
A modification of the context mode (bit JQDIS) causes the contexts queue to be flushed and the register JSQR is cleared.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_SetQueueMode
CFGR JQDIS LL_ADC_INJ_SetQueueMode
Parameters:
ADCx ADC instance
QueueMode This parameter can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
Return values:
None

Definition at line 4151 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 3903 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 3864 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32H7, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN0..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
None

Definition at line 3981 of file stm32h7xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 4091 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 3823 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
  • LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
Return values:
None

Definition at line 3732 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_8CYCLES_5
  • LL_ADC_SAMPLINGTIME_16CYCLES_5
  • LL_ADC_SAMPLINGTIME_32CYCLES_5
  • LL_ADC_SAMPLINGTIME_64CYCLES_5
  • LL_ADC_SAMPLINGTIME_387CYCLES_5
  • LL_ADC_SAMPLINGTIME_810CYCLES_5

Definition at line 4582 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get mode single-ended or differential input of the selected ADC channel.

Note:
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Therefore, to ensure a channel is configured in single-ended mode, the configuration of channel itself and the channel 'i-1' must be read back (to ensure that the selected channel channel has not been configured in differential mode by the previous channel).
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32H7, some channels are internally fixed to single-ended inputs configuration:
  • ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
  • ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
  • ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
One or several values can be selected. In this case, the value returned is null if all channels are in single ended-mode. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
Return values:
0,: channel in single-ended mode, else: channel in differential mode

Definition at line 4696 of file stm32h7xx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0 (3)
  • LL_ADC_CHANNEL_1 (3)
  • LL_ADC_CHANNEL_2 (3)
  • LL_ADC_CHANNEL_3 (3)
  • LL_ADC_CHANNEL_4 (3)
  • LL_ADC_CHANNEL_5 (3)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
  • LL_ADC_CHANNEL_VBAT (1)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
(3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). Other channels are slow channels (conversion rate: refer to reference manual).
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_8CYCLES_5
  • LL_ADC_SAMPLINGTIME_16CYCLES_5
  • LL_ADC_SAMPLINGTIME_32CYCLES_5
  • LL_ADC_SAMPLINGTIME_64CYCLES_5
  • LL_ADC_SAMPLINGTIME_387CYCLES_5
  • LL_ADC_SAMPLINGTIME_810CYCLES_5
Return values:
None

Definition at line 4497 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SingleDiff
 | ) |  |

Set mode single-ended or differential input of the selected ADC channel.

Note:
Channel ending is on channel scope: independently of channel mapped on ADC group regular or injected. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32H7, some channels are internally fixed to single-ended inputs configuration:
  • ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
  • ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
  • ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
For ADC channels configured in differential mode, both inputs should be biased at (Vref+)/2 +/-200mV. (Vref+ is the analog voltage reference)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_19
SingleDiff This parameter can be a combination of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 4643 of file stm32h7xx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK, and ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2 (1)
  • LL_ADC_AWD3 (1)
(1) On this AWD number, monitored channel can be retrieved if only 1 channel is programmed (or none or all channels). This function cannot retrieve monitored channel if multiple channels are programmed simultaneously by bitfield.
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CHANNEL_19_REG (0)
  • LL_ADC_AWD_CHANNEL_19_INJ (0)
  • LL_ADC_AWD_CHANNEL_19_REG_INJ
(0) On STM32H7, parameter available only on analog watchdog number: AWD1.

Definition at line 4979 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR23_CHANNEL_MASK, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, ADC_AWD_CRX_REGOFFSET_POS, and LL_ADC_AWD1.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Note:
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_GetAnalogWDThresholds
TR2 HT2 LL_ADC_GetAnalogWDThresholds
TR3 HT3 LL_ADC_GetAnalogWDThresholds
TR1 LT1 LL_ADC_GetAnalogWDThresholds
TR2 LT2 LL_ADC_GetAnalogWDThresholds
TR3 LT3 LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FFFFFF

Definition at line 5126 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TR12_REGOFFSETGAP_MASK, ADC_AWD_TR12_REGOFFSETGAP_VAL, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CHANNEL_19_REG (0)
  • LL_ADC_AWD_CHANNEL_19_INJ (0)
  • LL_ADC_AWD_CHANNEL_19_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)(1)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
  • LL_ADC_AWD_CH_VBAT_REG (0)(1)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(1)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (1)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
(0) On STM32H7, parameter available only on analog watchdog number: AWD1.
(1) On STM32H7, parameter available only on ADC instance: ADC3.
(2) On STM32H7, parameter available only on ADC instance: ADC2.
Return values:
None

Definition at line 4840 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, and ADC_AWD_CRX_REGOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling intermediate computation (after ratio, before shift application): intermediate register bitfield [32:7] (26 most significant bits).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either ADC groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_SetAnalogWDThresholds
TR2 HT2 LL_ADC_SetAnalogWDThresholds
TR3 HT3 LL_ADC_SetAnalogWDThresholds
TR1 LT1 LL_ADC_SetAnalogWDThresholds
TR2 LT2 LL_ADC_SetAnalogWDThresholds
TR3 LT3 LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 5088 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TR12_REGOFFSETGAP_MASK, ADC_AWD_TR12_REGOFFSETGAP_VAL, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC transversal scope: oversampling

Functions
Configuration of ADC transversal scope: oversampling
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Ratio,
 |  | uint32_t | Shift
 | ) |  |

Set ADC oversampling (impacting both ADC groups regular and injected)

Note:
This function set the 2 items of oversampling configuration:
  • ratio
  • shift
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
Parameters:
ADCx | ADC instance
Ratio | This parameter can be in the range from 1 to 1024.
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
  • LL_ADC_OVS_SHIFT_RIGHT_9
  • LL_ADC_OVS_SHIFT_RIGHT_10
  • LL_ADC_OVS_SHIFT_RIGHT_11
Return values:
None

Definition at line 5273 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont ( ADC_TypeDef * ADCx )

Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT

Definition at line 5239 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio ( ADC_TypeDef * ADCx )

Get ADC oversampling ratio (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSR LL_ADC_GetOverSamplingRatio
Parameters:
ADCx ADC instance
Return values:
Ratio This parameter can be in the from 1 to 1024.

Definition at line 5285 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope ( ADC_TypeDef * ADCx )

Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_GetOverSamplingScope
CFGR2 JOVSE LL_ADC_GetOverSamplingScope
CFGR2 ROVSM LL_ADC_GetOverSamplingScope
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED

Definition at line 5193 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift ( ADC_TypeDef * ADCx )

Get ADC oversampling shift (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_GetOverSamplingShift
Parameters:
ADCx ADC instance
Return values:
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
  • LL_ADC_OVS_SHIFT_RIGHT_9
  • LL_ADC_OVS_SHIFT_RIGHT_10
  • LL_ADC_OVS_SHIFT_RIGHT_11

Definition at line 5309 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OverSamplingDiscont
 | ) |  |

Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
On this STM32 serie, oversampling discontinuous mode (triggered mode) can be used only when oversampling is set on group regular only and in resumed mode.
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
Parameters:
ADCx ADC instance
OverSamplingDiscont This parameter can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT
Return values:
None

Definition at line 5220 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingScope | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OvsScope
 | ) |  |

Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_SetOverSamplingScope
CFGR2 JOVSE LL_ADC_SetOverSamplingScope
CFGR2 ROVSM LL_ADC_SetOverSamplingScope
Parameters:
ADCx ADC instance
OvsScope This parameter can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED
Return values:
None

Definition at line 5168 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of ADC hierarchical scope: multimode

Functions
Configuration of ADC hierarchical scope: multimode
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetBoostMode (ADC_TypeDef *ADCx, uint32_t BoostMode)
Set ADC boost mode.
__STATIC_INLINE uint32_t | LL_ADC_GetBoostMode (ADC_TypeDef *ADCx)
Get ADC boost mode.
__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetBoostMode ( ADC_TypeDef * ADCx )

Get ADC boost mode.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC boost must be configured, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CR BOOST LL_ADC_GetBoostMode
Parameters:
ADCx ADC instance
Return values:
0,: Boost disabled 1: Boost enabled

Definition at line 5359 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
Reference Manual to LL API cross reference:
CCR DAMDF LL_ADC_GetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_RES_32_10B
  • LL_ADC_MULTI_REG_DMA_RES_8B

Definition at line 5512 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

__STATIC_INLINE uint32_t LL_ADC_GetMultimode ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_GetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

Definition at line 5421 of file stm32h7xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode delay between 2 sampling phases.

Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
(1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits. (2) Parameter available only if ADC resolution is 16, 14 or 12 bits. (3) Parameter available only if ADC resolution is 10 or 8 bits. (4) Parameter available only if ADC resolution is 16 or 14 bits. (5) Parameter available only if ADC resolution is 16 bits. (6) Parameter available only if ADC resolution is 12 bits. (7) Parameter available only if ADC resolution is 16 or 14 bits.

Definition at line 5590 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetBoostMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | BoostMode
 | ) |  |

Set ADC boost mode.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC boost must be configured, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CR BOOST LL_ADC_SetBoostMode
Parameters:
ADCx ADC instance
BoostMode This parameter can be one of the following values:
  • LL_ADC_BOOST_MODE_6MHZ25
  • LL_ADC_BOOST_MODE_12MHZ5
  • LL_ADC_BOOST_MODE_20MHZ
  • LL_ADC_BOOST_MODE_25MHZ
  • LL_ADC_BOOST_MODE_50MHZ
Return values:
None

Definition at line 5337 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiDMATransfer | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiDMATransfer
 | ) |  |

Set ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CCR DAMDF LL_ADC_GetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiDMATransfer This parameter can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_RES_32_10B
  • LL_ADC_MULTI_REG_DMA_RES_8B
Return values:
None

Definition at line 5469 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultimode | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | Multimode
 | ) |  |

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_SetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Multimode This parameter can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
Return values:
None

Definition at line 5397 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiTwoSamplingDelay
 | ) |  |

Set ADC multimode delay between 2 sampling phases.

Note:
The sampling delay range depends on ADC resolution:
  • ADC resolution 12 bits can have maximum delay of 12 cycles.
  • ADC resolution 10 bits can have maximum delay of 10 cycles.
  • ADC resolution 8 bits can have maximum delay of 8 cycles.
  • ADC resolution 6 bits can have maximum delay of 6 cycles.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiTwoSamplingDelay This parameter can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
(1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits. (2) Parameter available only if ADC resolution is 16, 14 or 12 bits. (3) Parameter available only if ADC resolution is 10 or 8 bits. (4) Parameter available only if ADC resolution is 16 or 14 bits. (5) Parameter available only if ADC resolution is 16 bits. (6) Parameter available only if ADC resolution is 12 bits. (7) Parameter available only if ADC resolution is 16 or 14 bits.
Return values:
None

Definition at line 5557 of file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be not disabled. Must be enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5742 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_DisableDeepPowerDown ( ADC_TypeDef * ADCx )

Disable ADC deep power down mode.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_DisableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5638 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_DisableInternalRegulator ( ADC_TypeDef * ADCx )

Disable ADC internal voltage regulator.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_DisableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5690 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_DisableVoltageRegulator().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 serie, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled and ADC internal voltage regulator enabled.
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5722 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Enable().

__STATIC_INLINE void LL_ADC_EnableDeepPowerDown ( ADC_TypeDef * ADCx )

Put ADC instance in deep power down state.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_EnableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5615 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_EnterADCDeepPowerDownMode().

__STATIC_INLINE void LL_ADC_EnableInternalRegulator ( ADC_TypeDef * ADCx )

Enable ADC instance internal voltage regulator.

Note:
On this STM32 serie, after ADC internal voltage regulator enable, a delay for ADC internal voltage regulator stabilization is required before performing a ADC calibration or ADC enable. Refer to device datasheet, parameter tADCVREG_STUP. Refer to literal LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_EnableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5671 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 5826 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance deep power down state.

Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
Parameters:
ADCx ADC instance
Return values:
0,: deep power down is disabled, 1: deep power down is enabled.

Definition at line 5652 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing ( ADC_TypeDef * ADCx )

Get the selected ADC instance disable state.

Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_IsDisableOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no ADC disable command on going.

Definition at line 5772 of file stm32h7xx_ll_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 5761 of file stm32h7xx_ll_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance internal voltage regulator state.

Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
Parameters:
ADCx ADC instance
Return values:
0,: internal regulator is disabled, 1: internal regulator is enabled.

Definition at line 5701 of file stm32h7xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_StartCalibration | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | CalibrationMode,
 |  | uint32_t | SingleDiff
 | ) |  |

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 serie, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Refer to literal LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
Calibration duration:
  • Calibration of offset: 520 ADC clock cycles
  • Calibration of linearity: 131072 ADC clock cycles
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration run must be performed for each of these differential modes, if used afterwards and if the application requires their calibration). Calibration of linearity is common to both single-ended and differential modes (calibration run can be performed only once).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_StartCalibration
CR ADCALDIF LL_ADC_StartCalibration
CR ADCALLIN LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
CalibrationMode This parameter can be one of the following values:
  • LL_ADC_CALIB_OFFSET
  • LL_ADC_CALIB_OFFSET_LINEARITY
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 5810 of file stm32h7xx_ll_adc.h.

References ADC_CALIB_MODE_MASK, ADC_CR_BITS_PROPERTY_RS, and ADC_SINGLEDIFF_CALIB_START_MASK.

Referenced by HAL_ADCEx_Calibration_Start().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData16 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 16 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData14 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 14 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular conversion state.

Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group regular.

Definition at line 5893 of file stm32h7xx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular command of conversion stop state.

Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group regular.

Definition at line 5904 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData10
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 5978 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 5963 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 14 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData14
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x3FF

Definition at line 5948 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 16 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData16
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 5933 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 5918 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData8
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 5993 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32 | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | ConversionData
 | ) |  |

Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Note:
If raw data with ADC master and slave concatenated is retrieved, a macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). (however this macro is mainly intended for multimode transfer by DMA, because this function can do the same by getting multimode conversion data of ADC master or ADC slave separately).
Reference Manual to LL API cross reference:
CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ConversionData This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
  • LL_ADC_MULTI_MASTER_SLAVE
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 6018 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5857 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), and HAL_ADCEx_MultiModeStart_DMA().

__STATIC_INLINE void LL_ADC_REG_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5877 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), and LL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData16 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 16 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData14 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 14 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected conversion state.

Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group injected.

Definition at line 6088 of file stm32h7xx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected command of conversion stop state.

Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group injected.

Definition at line 6099 of file stm32h7xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData10
JDR2 JDATA LL_ADC_INJ_ReadConversionData10
JDR3 JDATA LL_ADC_INJ_ReadConversionData10
JDR4 JDATA LL_ADC_INJ_ReadConversionData10
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 6229 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 6202 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 14 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData14
JDR2 JDATA LL_ADC_INJ_ReadConversionData14
JDR3 JDATA LL_ADC_INJ_ReadConversionData14
JDR4 JDATA LL_ADC_INJ_ReadConversionData14
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FFF

Definition at line 6175 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 16 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData16
JDR2 JDATA LL_ADC_INJ_ReadConversionData16
JDR3 JDATA LL_ADC_INJ_ReadConversionData16
JDR4 JDATA LL_ADC_INJ_ReadConversionData16
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFFF

Definition at line 6148 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 6121 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData8
JDR2 JDATA LL_ADC_INJ_ReadConversionData8
JDR3 JDATA LL_ADC_INJ_ReadConversionData8
JDR4 JDATA LL_ADC_INJ_ReadConversionData8
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 6256 of file stm32h7xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE void LL_ADC_INJ_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group injected, without conversion stop command on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6052 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE void LL_ADC_INJ_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6072 of file stm32h7xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY ( ADC_TypeDef * ADCx )

Clear flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_ClearFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6406 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6494 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD2 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_ClearFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6505 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD3 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_ClearFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6516 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_EOC ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_ClearFlag_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6417 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOC.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6428 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_ClearFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6450 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOC ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_ClearFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6461 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6472 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF ( ADC_TypeDef * ADCx )

Clear flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_ClearFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6483 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE void LL_ADC_ClearFlag_OVR ( ADC_TypeDef * ADCx )

Clear flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_ClearFlag_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6439 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY ( ADC_TypeDef * ADCx )

Get flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6282 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6370 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_IsActiveFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6381 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_IsActiveFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6392 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_IsActiveFlag_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6293 of file stm32h7xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6304 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6326 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_IsActiveFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6337 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6348 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF ( ADC_TypeDef * ADCx )

Get flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6359 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC master.

Reference Manual to LL API cross reference:
CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6528 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 1 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6720 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6744 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD2_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6768 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD3_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6552 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6576 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC master.

Reference Manual to LL API cross reference:
CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6624 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6648 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6672 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC master.

Reference Manual to LL API cross reference:
CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6696 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC master.

Reference Manual to LL API cross reference:
CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6600 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_OVR_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR ( ADC_TypeDef * ADCx )

Get flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_IsActiveFlag_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6315 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC slave.

Reference Manual to LL API cross reference:
CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6540 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode analog watchdog 1 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6732 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6756 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD2_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6780 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_AWD3_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6564 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6588 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6636 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6660 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6684 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC slave.

Reference Manual to LL API cross reference:
CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6708 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC slave.

Reference Manual to LL API cross reference:
CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6612 of file stm32h7xx_ll_adc.h.

References LL_ADC_FLAG_OVR_SLV.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_ADRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_DisableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6920 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_DisableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7008 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD2 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_DisableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7019 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD3 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_DisableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7030 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_EOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_DisableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6931 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6942 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_DisableIT_EOSMP ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_DisableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6964 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_DisableIT_JEOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_DisableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6975 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_DisableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6986 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_DisableIT_JQOVF ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_DisableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6997 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_DisableIT_OVR ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_DisableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6953 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE void LL_ADC_EnableIT_ADRDY ( ADC_TypeDef * ADCx )

Enable ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_EnableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6799 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6887 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD2 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_EnableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6898 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD3 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_EnableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6909 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_EOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_EnableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6810 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6821 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_EnableIT_EOSMP ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_EnableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6843 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_EnableIT_JEOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_EnableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6854 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6865 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_EnableIT_JQOVF ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_EnableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6876 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_EnableIT_OVR ( ADC_TypeDef * ADCx )

Enable ADC group regular interruption overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_EnableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6832 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY ( ADC_TypeDef * ADCx )

Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7042 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_IsEnabledIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7138 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_IsEnabledIT_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7150 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_IsEnabledIT_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7162 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_IsEnabledIT_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7054 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7066 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7090 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_IsEnabledIT_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7102 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_IsEnabledIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7114 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7126 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_IsEnabledIT_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7078 of file stm32h7xx_ll_adc.h.

References LL_ADC_IT_OVR.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Note:
This function is performing a hard reset, using high level clock source RCC ADC reset. Caution: On this STM32 serie, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. To de-initialize only 1 ADC instance, use function LL_ADC_DeInit().
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 331 of file stm32h7xx_ll_adc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_ADC12, LL_AHB1_GRP1_ReleaseReset(), LL_AHB4_GRP1_ForceReset(), and LL_AHB4_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | LL_ADC_CommonInitTypeDef * | ADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 373 of file stm32h7xx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, LL_ADC_CommonInitTypeDef::CommonClock, IS_LL_ADC_COMMON_CLOCK, IS_LL_ADC_MULTI_DMA_TRANSFER, IS_LL_ADC_MULTI_MODE, IS_LL_ADC_MULTI_TWOSMP_DELAY, LL_ADC_MULTI_INDEPENDENT, LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
ADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 449 of file stm32h7xx_ll_adc.c.

References LL_ADC_CommonInitTypeDef::CommonClock, LL_ADC_CLOCK_SYNC_PCLK_DIV2, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5, LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
If this functions returns error status, it means that ADC instance is in an unknown state. In this case, perform a hard reset using high level clock source RCC ADC reset. Caution: On this STM32 serie, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. Refer to function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 480 of file stm32h7xx_ll_adc.c.

References ADC_TIMEOUT_DISABLE_CPU_CYCLES, ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES, assert_param, LL_ADC_Disable(), LL_ADC_FLAG_ADRDY, LL_ADC_FLAG_AWD1, LL_ADC_FLAG_AWD2, LL_ADC_FLAG_AWD3, LL_ADC_FLAG_EOC, LL_ADC_FLAG_EOS, LL_ADC_FLAG_EOSMP, LL_ADC_FLAG_JEOC, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JQOVF, LL_ADC_FLAG_OVR, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsStopConversionOngoing(), LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY, LL_ADC_INJ_SetQueueMode(), LL_ADC_INJ_SetTriggerSource(), LL_ADC_INJ_StopConversion(), LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), LL_ADC_IT_ADRDY, LL_ADC_IT_AWD1, LL_ADC_IT_AWD2, LL_ADC_IT_AWD3, LL_ADC_IT_EOC, LL_ADC_IT_EOS, LL_ADC_IT_EOSMP, LL_ADC_IT_JEOC, LL_ADC_IT_JEOS, LL_ADC_IT_JQOVF, LL_ADC_IT_OVR, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsStopConversionOngoing(), LL_ADC_REG_SetTriggerSource(), LL_ADC_REG_StopConversion(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 762 of file stm32h7xx_ll_adc.c.

References assert_param, IS_LL_ADC_LEFT_BIT_SHIFT, IS_LL_ADC_LOW_POWER, IS_LL_ADC_RESOLUTION, LL_ADC_InitTypeDef::LeftBitShift, LL_ADC_IsEnabled(), LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_INJ_InitTypeDef * | ADC_INJ_InitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_INJ_InitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 979 of file stm32h7xx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
ADC_INJ_InitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1050 of file stm32h7xx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | ADC_REG_InitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_REG_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 848 of file stm32h7xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DataTransferMode, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DATA_TRANSFER_MODE, IS_LL_ADC_REG_OVR_DATA_BEHAVIOR, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
ADC_REG_InitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 933 of file stm32h7xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DataTransferMode, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DR_TRANSFER, LL_ADC_REG_OVR_DATA_OVERWRITTEN, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * ADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
ADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 806 of file stm32h7xx_ll_adc.c.

References LL_ADC_InitTypeDef::LeftBitShift, LL_ADC_LEFT_BIT_SHIFT_NONE, LL_ADC_LP_MODE_NONE, LL_ADC_RESOLUTION_16B, LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BDMA Private Variables

Variables
BDMA Private Variables
BDMA

Variables

static const uint8_t LL_BDMA_CH_OFFSET_TAB []

Variable Documentation

const uint8_t LL_BDMA_CH_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
  (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
}

Definition at line 48 of file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_BDMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_BDMA_InitTypeDef Struct Reference
BDMA Exported Init structure

#include <stm32h7xx_ll_bdma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority

Detailed Description

Definition at line 74 of file stm32h7xx_ll_bdma.h.

Field Documentation

uint32_t LL_BDMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_BDMA_SetDataTransferDirection().

Definition at line 86 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 81 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_BDMA_SetMemorySize().

Definition at line 117 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_BDMA_SetMemoryIncMode().

Definition at line 105 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_BDMA_SetMode().

Definition at line 92 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_BDMA_SetDataLength().

Definition at line 123 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for BDMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 76 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_BDMA_SetPeriphSize().

Definition at line 111 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_BDMA_SetPeriphIncMode().

Definition at line 99 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of DMAMUX_LL_EC_REQUEST

This feature can be modified afterwards using unitary function LL_BDMA_SetPeriphRequest().

Definition at line 130 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

uint32_t LL_BDMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_BDMA_SetChannelPriorityLevel().

Definition at line 135 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init(), and LL_BDMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_bdma.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
BDMA Exported Constants

Flags defines which can be used with LL_BDMA_WriteReg function. More...

Defines

#define | LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1
#define | LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1
#define | LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1
#define | LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1
#define | LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2
#define | LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2
#define | LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2
#define | LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2
#define | LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3
#define | LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3
#define | LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3
#define | LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3
#define | LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4
#define | LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4
#define | LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4
#define | LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4
#define | LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5
#define | LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5
#define | LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5
#define | LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5
#define | LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6
#define | LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6
#define | LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6
#define | LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6
#define | LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7
#define | LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7
#define | LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7
#define | LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_BDMA_WriteReg function.

Define Documentation

#define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 154 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 158 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 162 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 166 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 170 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 174 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 178 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 156 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 160 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 164 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 168 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 172 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 176 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 180 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 155 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 159 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 163 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 167 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 171 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 175 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 179 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 157 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 161 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 165 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 169 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 173 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 177 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 181 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
BDMA Exported Constants

Flags defines which can be used with LL_BDMA_ReadReg function. More...

Defines

#define | LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0
#define | LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0
#define | LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0
#define | LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0
#define | LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1
#define | LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1
#define | LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1
#define | LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1
#define | LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2
#define | LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2
#define | LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2
#define | LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2
#define | LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3
#define | LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3
#define | LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3
#define | LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3
#define | LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4
#define | LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4
#define | LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4
#define | LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4
#define | LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5
#define | LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5
#define | LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5
#define | LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5
#define | LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6
#define | LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6
#define | LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6
#define | LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6
#define | LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7
#define | LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7
#define | LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7
#define | LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_BDMA_ReadReg function.

Define Documentation

#define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0

Channel 1 global flag

Definition at line 190 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1

Channel 1 global flag

Definition at line 194 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2

Channel 2 global flag

Definition at line 198 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3

Channel 3 global flag

Definition at line 202 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4

Channel 4 global flag

Definition at line 206 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5

Channel 5 global flag

Definition at line 210 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6

Channel 6 global flag

Definition at line 214 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7

Channel 7 global flag

Definition at line 218 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0

Channel 1 half transfer flag

Definition at line 192 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 196 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 200 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 204 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 208 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 212 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 216 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 220 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0

Channel 1 transfer complete flag

Definition at line 191 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 195 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 199 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 203 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 207 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 211 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 215 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 219 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0

Channel 1 transfer error flag

Definition at line 193 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 197 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 201 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 205 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 209 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 213 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 217 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 221 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
BDMA Exported Constants

IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions. More...

Defines

#define | LL_BDMA_CCR_TCIE BDMA_CCR_TCIE
#define | LL_BDMA_CCR_HTIE BDMA_CCR_HTIE
#define | LL_BDMA_CCR_TEIE BDMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions.

Define Documentation

#define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE

Half Transfer interrupt

Definition at line 231 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE

Transfer complete interrupt

Definition at line 230 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE

Transfer error interrupt

Definition at line 232 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: CHANNEL

Defines
CHANNEL
BDMA Exported Constants

Defines

#define | LL_BDMA_CHANNEL_0 0x00000000U
#define | LL_BDMA_CHANNEL_1 0x00000001U
#define | LL_BDMA_CHANNEL_2 0x00000002U
#define | LL_BDMA_CHANNEL_3 0x00000003U
#define | LL_BDMA_CHANNEL_4 0x00000004U
#define | LL_BDMA_CHANNEL_5 0x00000005U
#define | LL_BDMA_CHANNEL_6 0x00000006U
#define | LL_BDMA_CHANNEL_7 0x00000007U
#define | LL_BDMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_BDMA_CHANNEL_0 0x00000000U

DMA Channel 0

Definition at line 240 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_1 0x00000001U

BDMA Channel 1

Definition at line 241 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_2 0x00000002U

BDMA Channel 2

Definition at line 242 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_3 0x00000003U

BDMA Channel 3

Definition at line 243 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_4 0x00000004U

BDMA Channel 4

Definition at line 244 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_5 0x00000005U

BDMA Channel 5

Definition at line 245 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_6 0x00000006U

BDMA Channel 6

Definition at line 246 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_7 0x00000007U

BDMA Channel 7

Definition at line 247 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define LL_BDMA_CHANNEL_ALL 0xFFFF0000U

BDMA Channel all (used only for function LL_BDMA_DeInit().

Definition at line 249 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

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STM32H7B3xQ HAL User Manual: Transfer Direction

Defines
Transfer Direction
BDMA Exported Constants

Defines

#define | LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR
#define | LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM

Define Documentation

#define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 260 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR

Memory to peripheral direction

Definition at line 259 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_ConfigAddresses().

#define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 258 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Transfer mode

Defines
Transfer mode
BDMA Exported Constants

Defines

#define | LL_BDMA_MODE_NORMAL 0x00000000U
#define | LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC

Define Documentation

#define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC

Circular Mode

Definition at line 269 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 268 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

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STM32H7B3xQ HAL User Manual: DOUBLE BUFFER MODE

Defines
DOUBLE BUFFER MODE
BDMA Exported Constants | DMA Exported Constants

Defines

#define | LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
#define | LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM
#define | LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
#define | LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM

Define Documentation

#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U

Disable double buffering mode

Definition at line 277 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM

Enable double buffering mode

Definition at line 278 of file stm32h7xx_ll_bdma.h.

#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U

Disable double buffering mode

Definition at line 226 of file stm32h7xx_ll_dma.h.

#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM

Enable double buffering mode

Definition at line 227 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
BDMA Exported Constants

Defines

#define | LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC
#define | LL_BDMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 286 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 287 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Memory increment mode

Defines
Memory increment mode
BDMA Exported Constants

Defines

#define | LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC
#define | LL_BDMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC

Memory increment mode Enable

Definition at line 295 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 296 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
BDMA Exported Constants

Defines

#define | LL_BDMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0
#define | LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1

Define Documentation

#define LL_BDMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 304 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

#define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 305 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 306 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: Memory data alignment

Defines
Memory data alignment
BDMA Exported Constants

Defines

#define | LL_BDMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0
#define | LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1

Define Documentation

#define LL_BDMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 314 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

#define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 315 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 316 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
BDMA Exported Constants

Defines

#define | LL_BDMA_PRIORITY_LOW 0x00000000U
#define | LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0
#define | LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1
#define | LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL

Define Documentation

#define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1

Priority level : High

Definition at line 326 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 324 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_StructInit().

#define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0

Priority level : Medium

Definition at line 325 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL

Priority level : Very_High

Definition at line 327 of file stm32h7xx_ll_bdma.h.

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STM32H7B3xQ HAL User Manual: CURRENTTARGETMEM

Defines
CURRENTTARGETMEM
BDMA Exported Constants | DMA Exported Constants

Defines

#define | LL_BDMA_CURRENTTARGETMEM0 0x00000000U
#define | LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT
#define | LL_DMA_CURRENTTARGETMEM0 0x00000000U
#define | LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT

Define Documentation

#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U

Set CurrentTarget Memory to Memory 0

Definition at line 335 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT

Set CurrentTarget Memory to Memory 1

Definition at line 336 of file stm32h7xx_ll_bdma.h.

#define LL_DMA_CURRENTTARGETMEM0 0x00000000U

Set CurrentTarget Memory to Memory 0

Definition at line 349 of file stm32h7xx_ll_dma.h.

#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT

Set CurrentTarget Memory to Memory 1

Definition at line 350 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
BDMA Exported Macros

Defines

#define | LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in BDMA register.
#define | LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in BDMA register.

Define Documentation

#define LL_BDMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in BDMA register.

Parameters:
__INSTANCE__ | BDMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 364 of file stm32h7xx_ll_bdma.h.

#define LL_BDMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in BDMA register.

Parameters:
__INSTANCE__ | BDMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 356 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Convert BDMAxChannely

Defines
Convert BDMAxChannely
BDMA Exported Macros

Defines

#define | __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
Convert BDMAx_Channely into BDMAx.
#define | __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert BDMAx_Channely into LL_BDMA_CHANNEL_y.
#define | __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)
Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely.

Define Documentation

#define __LL_BDMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0))  ? LL_BDMA_CHANNEL_0 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1))  ? LL_BDMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2))  ? LL_BDMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3))  ? LL_BDMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4))  ? LL_BDMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5))  ? LL_BDMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6))  ? LL_BDMA_CHANNEL_6 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7))  ? LL_BDMA_CHANNEL_7 : \
LL_BDMA_CHANNEL_7)

Convert BDMAx_Channely into LL_BDMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ BDMAx_Channely
Return values:
LL_BDMA_CHANNEL_y

Definition at line 390 of file stm32h7xx_ll_bdma.h.

#define __LL_BDMA_GET_CHANNEL_INSTANCE | ( | __BDMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6  : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7  : \
 BDMA1_Channel7)

Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely.

Parameters:
__BDMA_INSTANCE__ | BDMAx
__CHANNEL__ | LL_BDMA_CHANNEL_y
Return values:
BDMAx_Channely

Definition at line 426 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

#define __LL_BDMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)

Convert BDMAx_Channely into BDMAx.

Parameters:
__CHANNEL_INSTANCE__ BDMAx_Channely
Return values:
BDMAx

Definition at line 378 of file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
BDMA Exported Functions

Functions

__STATIC_INLINE void | LL_BDMA_EnableChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable BDMA channel.
__STATIC_INLINE void | LL_BDMA_DisableChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable BDMA channel.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if BDMA channel is enabled or disabled.
__STATIC_INLINE void | LL_BDMA_ConfigTransfer (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to BDMA transfer.
__STATIC_INLINE void | LL_BDMA_SetDataTransferDirection (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_BDMA_GetDataTransferDirection (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_BDMA_SetMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
Set BDMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_BDMA_GetMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get BDMA mode circular or normal.
__STATIC_INLINE void | LL_BDMA_SetPeriphIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_BDMA_SetMemoryIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemoryIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_BDMA_SetPeriphSize (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphSize (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_BDMA_SetMemorySize (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemorySize (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_BDMA_SetChannelPriorityLevel (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_BDMA_GetChannelPriorityLevel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_BDMA_SetDataLength (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_BDMA_GetDataLength (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_BDMA_SetCurrentTargetMem (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE uint32_t | LL_BDMA_GetCurrentTargetMem (BDMA_TypeDef *BDMAx, uint32_t Channel)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE void | LL_BDMA_EnableDoubleBufferMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable the double buffer mode.
__STATIC_INLINE void | LL_BDMA_DisableDoubleBufferMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable the double buffer mode.
__STATIC_INLINE void | LL_BDMA_ConfigAddresses (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_BDMA_SetMemoryAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_BDMA_SetPeriphAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemoryAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_BDMA_SetM2MSrcAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_BDMA_SetM2MDstAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_BDMA_GetM2MSrcAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_BDMA_GetM2MDstAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_BDMA_SetMemory1Address (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
Set Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE uint32_t | LL_BDMA_GetMemory1Address (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE void | LL_BDMA_SetPeriphRequest (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
Set BDMA request for BDMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphRequest (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get BDMA request for BDMA Channels on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_BDMA_ConfigAddresses | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the BDMA channel is enabled.
Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_BDMA_ConfigAddresses
CMAR MA LL_BDMA_ConfigAddresses
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 1114 of file stm32h7xx_ll_bdma.h.

References LL_BDMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_BDMA_ConfigTransfer | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to BDMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_BDMA_ConfigTransfer
CCR MEM2MEM LL_BDMA_ConfigTransfer
CCR CIRC LL_BDMA_ConfigTransfer
CCR PINC LL_BDMA_ConfigTransfer
CCR MINC LL_BDMA_ConfigTransfer
CCR PSIZE LL_BDMA_ConfigTransfer
CCR MSIZE LL_BDMA_ConfigTransfer
CCR PL LL_BDMA_ConfigTransfer
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_BDMA_MODE_NORMAL or LL_BDMA_MODE_CIRCULAR
  • LL_BDMA_PERIPH_INCREMENT or LL_BDMA_PERIPH_NOINCREMENT
  • LL_BDMA_MEMORY_INCREMENT or LL_BDMA_MEMORY_NOINCREMENT
  • LL_BDMA_PDATAALIGN_BYTE or LL_BDMA_PDATAALIGN_HALFWORD or LL_BDMA_PDATAALIGN_WORD
  • LL_BDMA_MDATAALIGN_BYTE or LL_BDMA_MDATAALIGN_HALFWORD or LL_BDMA_MDATAALIGN_WORD
  • LL_BDMA_PRIORITY_LOW or LL_BDMA_PRIORITY_MEDIUM or LL_BDMA_PRIORITY_HIGH or LL_BDMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 566 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init().

__STATIC_INLINE void LL_BDMA_DisableChannel | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable BDMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_BDMA_DisableChannel
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 507 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable the double buffer mode.

Reference Manual to LL API cross reference:
CR DBM LL_BDMA_DisableDoubleBufferMode
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 1083 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_EnableChannel | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable BDMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_BDMA_EnableChannel
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 485 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable the double buffer mode.

Reference Manual to LL API cross reference:
CR DBM LL_BDMA_EnableDoubleBufferMode
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 1061 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_BDMA_GetChannelPriorityLevel
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_PRIORITY_LOW
  • LL_BDMA_PRIORITY_MEDIUM
  • LL_BDMA_PRIORITY_HIGH
  • LL_BDMA_PRIORITY_VERYHIGH

Definition at line 938 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

Reference Manual to LL API cross reference:
CR CT LL_BDMA_GetCurrentTargetMem
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_CURRENTTARGETMEM0
  • LL_BDMA_CURRENTTARGETMEM1

Definition at line 1039 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetDataLength | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_BDMA_GetDataLength
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 989 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_BDMA_GetDataTransferDirection
CCR MEM2MEM LL_BDMA_GetDataTransferDirection
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_BDMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 622 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_BDMA_GetM2MDstAddress
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1318 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_BDMA_GetM2MSrcAddress
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1295 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory 1 address (used in case of Double buffer mode).

Reference Manual to LL API cross reference:
M1AR M1A LL_BDMA_GetMemory1Address
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1363 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_BDMA_GetMemoryAddress
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1199 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_BDMA_GetMemoryIncMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_MEMORY_INCREMENT
  • LL_BDMA_MEMORY_NOINCREMENT

Definition at line 777 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_BDMA_GetMemorySize
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_MDATAALIGN_BYTE
  • LL_BDMA_MDATAALIGN_HALFWORD
  • LL_BDMA_MDATAALIGN_WORD

Definition at line 883 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get BDMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_BDMA_GetMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_MODE_NORMAL
  • LL_BDMA_MODE_CIRCULAR

Definition at line 675 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_BDMA_GetPeriphAddress
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1222 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_BDMA_GetPeriphIncMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_PERIPH_INCREMENT
  • LL_BDMA_PERIPH_NOINCREMENT

Definition at line 726 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get BDMA request for BDMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX2_REQ_MEM2MEM
  • LL_DMAMUX2_REQ_GENERATOR0
  • LL_DMAMUX2_REQ_GENERATOR1
  • LL_DMAMUX2_REQ_GENERATOR2
  • LL_DMAMUX2_REQ_GENERATOR3
  • LL_DMAMUX2_REQ_GENERATOR4
  • LL_DMAMUX2_REQ_GENERATOR5
  • LL_DMAMUX2_REQ_GENERATOR6
  • LL_DMAMUX2_REQ_GENERATOR7
  • LL_DMAMUX2_REQ_LPUART1_RX
  • LL_DMAMUX2_REQ_LPUART1_TX
  • LL_DMAMUX2_REQ_SPI6_RX
  • LL_DMAMUX2_REQ_SPI6_TX
  • LL_DMAMUX2_REQ_I2C4_RX
  • LL_DMAMUX2_REQ_I2C4_TX
  • LL_DMAMUX2_REQ_SAI4_A (*)
  • LL_DMAMUX2_REQ_SAI4_B (*)
  • LL_DMAMUX2_REQ_ADC3 (*)
  • LL_DMAMUX2_REQ_DAC3 (*)
  • LL_DMAMUX2_REQ_DFSDM2 (*)
Note:
(*) Availability depends on devices.

Definition at line 1451 of file stm32h7xx_ll_bdma.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_BDMA_GetPeriphSize
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_BDMA_PDATAALIGN_BYTE
  • LL_BDMA_PDATAALIGN_HALFWORD
  • LL_BDMA_PDATAALIGN_WORD

Definition at line 830 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if BDMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_BDMA_IsEnabledChannel
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 529 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_BDMA_SetChannelPriorityLevel
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_BDMA_PRIORITY_LOW
  • LL_BDMA_PRIORITY_MEDIUM
  • LL_BDMA_PRIORITY_HIGH
  • LL_BDMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 911 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | CurrentMemory
 | ) |  |

Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

Reference Manual to LL API cross reference:
CR CT LL_BDMA_SetCurrentTargetMem
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
CurrentMemory This parameter can be one of the following values:
  • LL_BDMA_CURRENTTARGETMEM0
  • LL_BDMA_CURRENTTARGETMEM1
Return values:
None

Definition at line 1015 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetDataLength | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_BDMA_SetDataLength
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 964 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init().

__STATIC_INLINE void LL_BDMA_SetDataTransferDirection | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_BDMA_SetDataTransferDirection
CCR MEM2MEM LL_BDMA_SetDataTransferDirection
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 595 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetM2MDstAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the BDMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_BDMA_SetM2MDstAddress
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1272 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the BDMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_BDMA_SetM2MSrcAddress
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1247 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetMemory1Address | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Address
 | ) |  |

Set Memory 1 address (used in case of Double buffer mode).

Reference Manual to LL API cross reference:
M1AR M1A LL_BDMA_SetMemory1Address
Parameters:
BDMAx | BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Address | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1341 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetMemoryAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the BDMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_BDMA_SetMemoryAddress
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1151 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init().

__STATIC_INLINE void LL_BDMA_SetMemoryIncMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_BDMA_SetMemoryIncMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_BDMA_MEMORY_INCREMENT
  • LL_BDMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 752 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetMemorySize | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_BDMA_SetMemorySize
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_BDMA_MDATAALIGN_BYTE
  • LL_BDMA_MDATAALIGN_HALFWORD
  • LL_BDMA_MDATAALIGN_WORD
Return values:
None

Definition at line 857 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set BDMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_BDMA_SetMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_BDMA_MODE_NORMAL
  • LL_BDMA_MODE_CIRCULAR
Return values:
None

Definition at line 650 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetPeriphAddress | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the BDMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_BDMA_SetPeriphAddress
Parameters:
BDMAx | BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1176 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_Init().

__STATIC_INLINE void LL_BDMA_SetPeriphIncMode | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_BDMA_SetPeriphIncMode
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_BDMA_PERIPH_INCREMENT
  • LL_BDMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 701 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_SetPeriphRequest | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set BDMA request for BDMA Channels on DMAMUX Channel x.

Note:
DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest
Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Request This parameter can be one of the following values:
  • LL_DMAMUX2_REQ_MEM2MEM
  • LL_DMAMUX2_REQ_GENERATOR0
  • LL_DMAMUX2_REQ_GENERATOR1
  • LL_DMAMUX2_REQ_GENERATOR2
  • LL_DMAMUX2_REQ_GENERATOR3
  • LL_DMAMUX2_REQ_GENERATOR4
  • LL_DMAMUX2_REQ_GENERATOR5
  • LL_DMAMUX2_REQ_GENERATOR6
  • LL_DMAMUX2_REQ_GENERATOR7
  • LL_DMAMUX2_REQ_LPUART1_RX
  • LL_DMAMUX2_REQ_LPUART1_TX
  • LL_DMAMUX2_REQ_SPI6_RX
  • LL_DMAMUX2_REQ_SPI6_TX
  • LL_DMAMUX2_REQ_I2C4_RX
  • LL_DMAMUX2_REQ_I2C4_TX
  • LL_DMAMUX2_REQ_SAI4_A (*)
  • LL_DMAMUX2_REQ_SAI4_B (*)
  • LL_DMAMUX2_REQ_ADC3 (*)
  • LL_DMAMUX2_REQ_DAC3 (*)
  • LL_DMAMUX2_REQ_DFSDM2 (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 1408 of file stm32h7xx_ll_bdma.h.

References DMAMUX_CCR_SIZE.

Referenced by LL_BDMA_DeInit(), and LL_BDMA_Init().

__STATIC_INLINE void LL_BDMA_SetPeriphSize | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_BDMA_SetPeriphSize
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_BDMA_PDATAALIGN_BYTE
  • LL_BDMA_PDATAALIGN_HALFWORD
  • LL_BDMA_PDATAALIGN_WORD
Return values:
None

Definition at line 804 of file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
BDMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI0 (BDMA_TypeDef *BDMAx)
Get Channel 0 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI1 (BDMA_TypeDef *BDMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI2 (BDMA_TypeDef *BDMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI3 (BDMA_TypeDef *BDMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI4 (BDMA_TypeDef *BDMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI5 (BDMA_TypeDef *BDMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI6 (BDMA_TypeDef *BDMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI7 (BDMA_TypeDef *BDMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC0 (BDMA_TypeDef *BDMAx)
Get Channel 0 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC1 (BDMA_TypeDef *BDMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC2 (BDMA_TypeDef *BDMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC3 (BDMA_TypeDef *BDMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC4 (BDMA_TypeDef *BDMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC5 (BDMA_TypeDef *BDMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC6 (BDMA_TypeDef *BDMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC7 (BDMA_TypeDef *BDMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT0 (BDMA_TypeDef *BDMAx)
Get Channel 0 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT1 (BDMA_TypeDef *BDMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT2 (BDMA_TypeDef *BDMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT3 (BDMA_TypeDef *BDMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT4 (BDMA_TypeDef *BDMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT5 (BDMA_TypeDef *BDMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT6 (BDMA_TypeDef *BDMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT7 (BDMA_TypeDef *BDMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE0 (BDMA_TypeDef *BDMAx)
Get Channel 0 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE1 (BDMA_TypeDef *BDMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE2 (BDMA_TypeDef *BDMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE3 (BDMA_TypeDef *BDMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE4 (BDMA_TypeDef *BDMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE5 (BDMA_TypeDef *BDMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE6 (BDMA_TypeDef *BDMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE7 (BDMA_TypeDef *BDMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_BDMA_ClearFlag_GI0 ( BDMA_TypeDef * BDMAx )

Clear Channel 0 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF0 LL_BDMA_ClearFlag_GI0
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1822 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI1 ( BDMA_TypeDef * BDMAx )

Clear Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF1 LL_BDMA_ClearFlag_GI1
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1833 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI2 ( BDMA_TypeDef * BDMAx )

Clear Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF2 LL_BDMA_ClearFlag_GI2
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1844 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI3 ( BDMA_TypeDef * BDMAx )

Clear Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF3 LL_BDMA_ClearFlag_GI3
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1855 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI4 ( BDMA_TypeDef * BDMAx )

Clear Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF4 LL_BDMA_ClearFlag_GI4
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1866 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI5 ( BDMA_TypeDef * BDMAx )

Clear Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF5 LL_BDMA_ClearFlag_GI5
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1877 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI6 ( BDMA_TypeDef * BDMAx )

Clear Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF6 LL_BDMA_ClearFlag_GI6
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1888 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_GI7 ( BDMA_TypeDef * BDMAx )

Clear Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF7 LL_BDMA_ClearFlag_GI7
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1899 of file stm32h7xx_ll_bdma.h.

Referenced by LL_BDMA_DeInit().

__STATIC_INLINE void LL_BDMA_ClearFlag_HT0 ( BDMA_TypeDef * BDMAx )

Clear Channel 0 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF0 LL_BDMA_ClearFlag_HT0
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1998 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT1 ( BDMA_TypeDef * BDMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_BDMA_ClearFlag_HT1
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2009 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT2 ( BDMA_TypeDef * BDMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_BDMA_ClearFlag_HT2
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2020 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT3 ( BDMA_TypeDef * BDMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_BDMA_ClearFlag_HT3
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2031 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT4 ( BDMA_TypeDef * BDMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_BDMA_ClearFlag_HT4
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2042 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT5 ( BDMA_TypeDef * BDMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_BDMA_ClearFlag_HT5
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2053 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT6 ( BDMA_TypeDef * BDMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_BDMA_ClearFlag_HT6
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2064 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_HT7 ( BDMA_TypeDef * BDMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_BDMA_ClearFlag_HT7
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2075 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC0 ( BDMA_TypeDef * BDMAx )

Clear Channel 0 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF0 LL_BDMA_ClearFlag_TC0
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1910 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC1 ( BDMA_TypeDef * BDMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_BDMA_ClearFlag_TC1
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1921 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC2 ( BDMA_TypeDef * BDMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_BDMA_ClearFlag_TC2
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1932 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC3 ( BDMA_TypeDef * BDMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_BDMA_ClearFlag_TC3
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1943 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC4 ( BDMA_TypeDef * BDMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_BDMA_ClearFlag_TC4
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1954 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC5 ( BDMA_TypeDef * BDMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_BDMA_ClearFlag_TC5
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1965 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC6 ( BDMA_TypeDef * BDMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_BDMA_ClearFlag_TC6
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1976 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TC7 ( BDMA_TypeDef * BDMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_BDMA_ClearFlag_TC7
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 1987 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE0 ( BDMA_TypeDef * BDMAx )

Clear Channel 0 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF0 LL_BDMA_ClearFlag_TE0
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2086 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE1 ( BDMA_TypeDef * BDMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_BDMA_ClearFlag_TE1
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2097 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE2 ( BDMA_TypeDef * BDMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_BDMA_ClearFlag_TE2
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2108 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE3 ( BDMA_TypeDef * BDMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_BDMA_ClearFlag_TE3
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2119 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE4 ( BDMA_TypeDef * BDMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_BDMA_ClearFlag_TE4
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2130 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE5 ( BDMA_TypeDef * BDMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_BDMA_ClearFlag_TE5
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2141 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE6 ( BDMA_TypeDef * BDMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_BDMA_ClearFlag_TE6
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2152 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_ClearFlag_TE7 ( BDMA_TypeDef * BDMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_BDMA_ClearFlag_TE7
Parameters:
BDMAx BDMA Instance
Return values:
None

Definition at line 2163 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0 ( BDMA_TypeDef * BDMAx )

Get Channel 0 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF0 LL_BDMA_IsActiveFlag_GI0
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1471 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1 ( BDMA_TypeDef * BDMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_BDMA_IsActiveFlag_GI1
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1482 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2 ( BDMA_TypeDef * BDMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_BDMA_IsActiveFlag_GI2
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1493 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3 ( BDMA_TypeDef * BDMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_BDMA_IsActiveFlag_GI3
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1504 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4 ( BDMA_TypeDef * BDMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_BDMA_IsActiveFlag_GI4
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1515 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5 ( BDMA_TypeDef * BDMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_BDMA_IsActiveFlag_GI5
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1526 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6 ( BDMA_TypeDef * BDMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_BDMA_IsActiveFlag_GI6
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1537 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7 ( BDMA_TypeDef * BDMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_BDMA_IsActiveFlag_GI7
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1548 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0 ( BDMA_TypeDef * BDMAx )

Get Channel 0 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF0 LL_BDMA_IsActiveFlag_HT0
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1646 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1 ( BDMA_TypeDef * BDMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_BDMA_IsActiveFlag_HT1
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1657 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2 ( BDMA_TypeDef * BDMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_BDMA_IsActiveFlag_HT2
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1668 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3 ( BDMA_TypeDef * BDMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_BDMA_IsActiveFlag_HT3
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1679 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4 ( BDMA_TypeDef * BDMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_BDMA_IsActiveFlag_HT4
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1690 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5 ( BDMA_TypeDef * BDMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_BDMA_IsActiveFlag_HT5
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1701 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6 ( BDMA_TypeDef * BDMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_BDMA_IsActiveFlag_HT6
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1712 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7 ( BDMA_TypeDef * BDMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_BDMA_IsActiveFlag_HT7
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1723 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0 ( BDMA_TypeDef * BDMAx )

Get Channel 0 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF0 LL_BDMA_IsActiveFlag_TC0
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1559 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1 ( BDMA_TypeDef * BDMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_BDMA_IsActiveFlag_TC1
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1569 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2 ( BDMA_TypeDef * BDMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_BDMA_IsActiveFlag_TC2
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1580 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3 ( BDMA_TypeDef * BDMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_BDMA_IsActiveFlag_TC3
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1591 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4 ( BDMA_TypeDef * BDMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_BDMA_IsActiveFlag_TC4
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5 ( BDMA_TypeDef * BDMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_BDMA_IsActiveFlag_TC5
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1613 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6 ( BDMA_TypeDef * BDMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_BDMA_IsActiveFlag_TC6
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1624 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7 ( BDMA_TypeDef * BDMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_BDMA_IsActiveFlag_TC7
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1635 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0 ( BDMA_TypeDef * BDMAx )

Get Channel 0 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF0 LL_BDMA_IsActiveFlag_TE0
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1734 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1 ( BDMA_TypeDef * BDMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_BDMA_IsActiveFlag_TE1
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1745 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2 ( BDMA_TypeDef * BDMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_BDMA_IsActiveFlag_TE2
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1756 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3 ( BDMA_TypeDef * BDMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_BDMA_IsActiveFlag_TE3
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1767 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4 ( BDMA_TypeDef * BDMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_BDMA_IsActiveFlag_TE4
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1778 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5 ( BDMA_TypeDef * BDMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_BDMA_IsActiveFlag_TE5
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1789 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6 ( BDMA_TypeDef * BDMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_BDMA_IsActiveFlag_TE6
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1800 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7 ( BDMA_TypeDef * BDMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_BDMA_IsActiveFlag_TE7
Parameters:
BDMAx BDMA Instance
Return values:
State of bit (1 or 0).

Definition at line 1811 of file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
BDMA Exported Functions

Functions

__STATIC_INLINE void | LL_BDMA_EnableIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_BDMA_EnableIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_BDMA_EnableIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_BDMA_DisableIT_HT | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_BDMA_DisableIT_HT
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2278 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_DisableIT_TC | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_BDMA_DisableIT_TC
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2256 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_DisableIT_TE | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_BDMA_DisableIT_TE
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2300 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_EnableIT_HT | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_BDMA_EnableIT_HT
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2212 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_EnableIT_TC | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_BDMA_EnableIT_TC
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2190 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE void LL_BDMA_EnableIT_TE | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_BDMA_EnableIT_TE
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
None

Definition at line 2234 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_BDMA_IsEnabledIT_HT
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2344 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_BDMA_IsEnabledIT_TC
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2322 of file stm32h7xx_ll_bdma.h.

__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_BDMA_IsEnabledIT_TE
Parameters:
BDMAx BDMA Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2366 of file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
BDMA Exported Functions

Functions

uint32_t | LL_BDMA_DeInit (BDMA_TypeDef *BDMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_BDMA_Init (BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
void | LL_BDMA_StructInit (LL_BDMA_InitTypeDef *BDMA_InitStruct)
Set each LL_BDMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_BDMA_DeInit | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
BDMAx BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
  • LL_BDMA_CHANNEL_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 124 of file stm32h7xx_ll_bdma.c.

References __LL_BDMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_BDMA_ALL_CHANNEL_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_ReleaseReset(), LL_BDMA_CHANNEL_0, LL_BDMA_CHANNEL_1, LL_BDMA_CHANNEL_2, LL_BDMA_CHANNEL_3, LL_BDMA_CHANNEL_4, LL_BDMA_CHANNEL_5, LL_BDMA_CHANNEL_6, LL_BDMA_CHANNEL_7, LL_BDMA_CHANNEL_ALL, LL_BDMA_ClearFlag_GI0(), LL_BDMA_ClearFlag_GI1(), LL_BDMA_ClearFlag_GI2(), LL_BDMA_ClearFlag_GI3(), LL_BDMA_ClearFlag_GI4(), LL_BDMA_ClearFlag_GI5(), LL_BDMA_ClearFlag_GI6(), LL_BDMA_ClearFlag_GI7(), LL_BDMA_SetPeriphRequest(), LL_BDMA_WriteReg, and LL_DMAMUX2_REQ_MEM2MEM.

uint32_t LL_BDMA_Init | ( | BDMA_TypeDef * | BDMAx,
 |  | uint32_t | Channel,
 |  | LL_BDMA_InitTypeDef * | BDMA_InitStruct
 | ) |  |

Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.

Note:
To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros :
  • __LL_BDMA_GET_INSTANCE
  • __LL_BDMA_GET_CHANNEL
Parameters:
BDMAx | BDMAx Instance
Channel This parameter can be one of the following values:
  • LL_BDMA_CHANNEL_0
  • LL_BDMA_CHANNEL_1
  • LL_BDMA_CHANNEL_2
  • LL_BDMA_CHANNEL_3
  • LL_BDMA_CHANNEL_4
  • LL_BDMA_CHANNEL_5
  • LL_BDMA_CHANNEL_6
  • LL_BDMA_CHANNEL_7
BDMA_InitStruct | pointer to a LL_BDMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 242 of file stm32h7xx_ll_bdma.c.

References assert_param, LL_BDMA_InitTypeDef::Direction, IS_LL_BDMA_ALL_CHANNEL_INSTANCE, IS_LL_BDMA_DIRECTION, IS_LL_BDMA_MEMORYDATASIZE, IS_LL_BDMA_MEMORYINCMODE, IS_LL_BDMA_MODE, IS_LL_BDMA_NBDATA, IS_LL_BDMA_PERIPHDATASIZE, IS_LL_BDMA_PERIPHINCMODE, IS_LL_BDMA_PERIPHREQUEST, IS_LL_BDMA_PRIORITY, LL_BDMA_ConfigTransfer(), LL_BDMA_SetDataLength(), LL_BDMA_SetMemoryAddress(), LL_BDMA_SetPeriphAddress(), LL_BDMA_SetPeriphRequest(), LL_BDMA_InitTypeDef::MemoryOrM2MDstAddress, LL_BDMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_BDMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_BDMA_InitTypeDef::Mode, LL_BDMA_InitTypeDef::NbData, LL_BDMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_BDMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_BDMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_BDMA_InitTypeDef::PeriphRequest, and LL_BDMA_InitTypeDef::Priority.

void LL_BDMA_StructInit ( LL_BDMA_InitTypeDef * BDMA_InitStruct )

Set each LL_BDMA_InitTypeDef field to default value.

Parameters:
BDMA_InitStruct Pointer to a LL_BDMA_InitTypeDef structure.
Return values:
None

Definition at line 310 of file stm32h7xx_ll_bdma.c.

References LL_BDMA_InitTypeDef::Direction, LL_BDMA_DIRECTION_PERIPH_TO_MEMORY, LL_BDMA_MDATAALIGN_BYTE, LL_BDMA_MEMORY_NOINCREMENT, LL_BDMA_MODE_NORMAL, LL_BDMA_PDATAALIGN_BYTE, LL_BDMA_PERIPH_NOINCREMENT, LL_BDMA_PRIORITY_LOW, LL_DMAMUX2_REQ_MEM2MEM, LL_BDMA_InitTypeDef::MemoryOrM2MDstAddress, LL_BDMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_BDMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_BDMA_InitTypeDef::Mode, LL_BDMA_InitTypeDef::NbData, LL_BDMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_BDMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_BDMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_BDMA_InitTypeDef::PeriphRequest, and LL_BDMA_InitTypeDef::Priority.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BDMA_LL_Private_Macros

Defines
BDMA_LL_Private_Macros
BDMA

Defines

#define | IS_LL_BDMA_DIRECTION(__VALUE__)
#define | IS_LL_BDMA_MODE(__VALUE__)
#define | IS_LL_BDMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_BDMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2)
#define | IS_LL_BDMA_PRIORITY(__VALUE__)
#define | IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Define Documentation

#define IS_LL_BDMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == BDMA) && \
                                                             (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_1) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_2) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_3) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_4) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_5) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_6) || \
                                                              ((CHANNEL) == LL_BDMA_CHANNEL_7))))

Definition at line 82 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_DeInit(), and LL_BDMA_Init().

#define IS_LL_BDMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                  ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                  ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 48 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE)      || \
                                                  ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD)  || \
                                                  ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))

Definition at line 65 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
                                                  ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))

Definition at line 58 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
                                                  ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))

Definition at line 52 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 69 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE)      || \
                                                  ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD)  || \
                                                  ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))

Definition at line 61 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
                                                  ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))

Definition at line 55 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_PERIPHREQUEST ( __VALUE__ ) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2)

Definition at line 74 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

#define IS_LL_BDMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_BDMA_PRIORITY_LOW)    || \
                                                  ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
                                                  ((__VALUE__) == LL_BDMA_PRIORITY_HIGH)   || \
                                                  ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))

Definition at line 77 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_Init().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB3 GRP1 PERIPH

Defines
AHB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
#define | LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
#define | LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
#define | LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define | LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
#define | LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
#define | LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
#define | LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
#define | LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
#define | LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN
#define | LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
#define | LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
#define | LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
#define | LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
#define | LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN

Define Documentation

#define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN

Definition at line 107 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN

Definition at line 113 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN

Definition at line 116 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN

Definition at line 77 of file stm32h7xx_ll_bus.h.

Referenced by LL_DMA2D_DeInit().

#define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN

Definition at line 103 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN

Definition at line 104 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN

Definition at line 102 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN

Definition at line 83 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN

Definition at line 99 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN

Definition at line 105 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN

Definition at line 80 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN

Definition at line 76 of file stm32h7xx_ll_bus.h.

Referenced by LL_MDMA_DeInit().

#define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN

Definition at line 92 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN

Definition at line 88 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN

Definition at line 89 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN

Definition at line 95 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN

Definition at line 96 of file stm32h7xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN

Definition at line 101 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
#define | LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN

Definition at line 128 of file stm32h7xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN

Definition at line 133 of file stm32h7xx_ll_bus.h.

Referenced by LL_CRC_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN

Definition at line 126 of file stm32h7xx_ll_bus.h.

Referenced by LL_BDMA_DeInit(), and LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN

Definition at line 127 of file stm32h7xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN

Definition at line 140 of file stm32h7xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN

Definition at line 141 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB2 GRP1 PERIPH

Defines
AHB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
#define | LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
#define | LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
#define | LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define | LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
#define | LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
#define | LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN
#define | LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/
#define | LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN
#define | LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/

Define Documentation

#define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN

Definition at line 172 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN

Definition at line 178 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN

Definition at line 167 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN

Definition at line 159 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/

Definition at line 173 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/

Definition at line 179 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN

Definition at line 154 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN

Definition at line 162 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN

Definition at line 156 of file stm32h7xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN

Definition at line 164 of file stm32h7xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN

Definition at line 165 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB4 GRP1 PERIPH

Defines
AHB4 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
#define | LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
#define | LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
#define | LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
#define | LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
#define | LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
#define | LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
#define | LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
#define | LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
#define | LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
#define | LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
#define | LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN
#define | LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/
#define | LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
#define | LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN
#define | LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
#define | LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/

Define Documentation

#define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/

Definition at line 208 of file stm32h7xx_ll_bus.h.

#define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN

Definition at line 207 of file stm32h7xx_ll_bus.h.

#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN

Definition at line 218 of file stm32h7xx_ll_bus.h.

#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/

Definition at line 225 of file stm32h7xx_ll_bus.h.

#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN

Definition at line 192 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN

Definition at line 193 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN

Definition at line 194 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN

Definition at line 195 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN

Definition at line 196 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN

Definition at line 197 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN

Definition at line 198 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN

Definition at line 199 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN

Definition at line 200 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN

Definition at line 201 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN

Definition at line 202 of file stm32h7xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/

Definition at line 224 of file stm32h7xx_ll_bus.h.

#define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN

Definition at line 223 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB3 GRP1 PERIPH

Defines
APB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
#define | LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
#define | LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/

Define Documentation

#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN

Definition at line 235 of file stm32h7xx_ll_bus.h.

#define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/

Definition at line 241 of file stm32h7xx_ll_bus.h.

#define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN

Definition at line 239 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
#define | LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
#define | LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
#define | LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
#define | LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
#define | LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
#define | LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
#define | LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
#define | LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN

Define Documentation

#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN

Definition at line 274 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN

Definition at line 275 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN

Definition at line 271 of file stm32h7xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN

Definition at line 272 of file stm32h7xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN

Definition at line 273 of file stm32h7xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN

Definition at line 260 of file stm32h7xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN

Definition at line 266 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN

Definition at line 264 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN

Definition at line 265 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN

Definition at line 257 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN

Definition at line 258 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN

Definition at line 259 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN

Definition at line 251 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN

Definition at line 252 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN

Definition at line 253 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN

Definition at line 254 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN

Definition at line 255 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN

Definition at line 256 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN

Definition at line 269 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN

Definition at line 270 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN

Definition at line 276 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN

Definition at line 277 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN

Definition at line 267 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN

Definition at line 268 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB1 GRP2 PERIPH

Defines
APB1 GRP2 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
#define | LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
#define | LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
#define | LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
#define | LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN

Define Documentation

#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN

Definition at line 286 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN

Definition at line 290 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN

Definition at line 289 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN

Definition at line 288 of file stm32h7xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN

Definition at line 287 of file stm32h7xx_ll_bus.h.

Referenced by LL_SWPMI_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
#define | LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
#define | LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define | LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
#define | LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN

Definition at line 320 of file stm32h7xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Definition at line 315 of file stm32h7xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN

Definition at line 316 of file stm32h7xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 309 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN

Definition at line 310 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN

Definition at line 314 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN

Definition at line 299 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN

Definition at line 311 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN

Definition at line 312 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN

Definition at line 313 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN

Definition at line 300 of file stm32h7xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN

Definition at line 304 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 301 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN

Definition at line 307 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN

Definition at line 302 of file stm32h7xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB4 GRP1 PERIPH

Defines
APB4 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
#define | LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
#define | LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
#define | LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
#define | LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
#define | LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
#define | LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN
#define | LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
#define | LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
#define | LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
#define | LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
#define | LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN

Define Documentation

#define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN

Definition at line 347 of file stm32h7xx_ll_bus.h.

#define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN

Definition at line 345 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN

Definition at line 357 of file stm32h7xx_ll_bus.h.

#define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN

Definition at line 354 of file stm32h7xx_ll_bus.h.

#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN

Definition at line 335 of file stm32h7xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN

Definition at line 336 of file stm32h7xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN

Definition at line 337 of file stm32h7xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN

Definition at line 333 of file stm32h7xx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN

Definition at line 349 of file stm32h7xx_ll_bus.h.

#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN

Definition at line 334 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN

Definition at line 332 of file stm32h7xx_ll_bus.h.

#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN

Definition at line 348 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CLKAM PERIPH

Defines
CLKAM PERIPH
BUS Exported Constants

Defines

#define | LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
#define | LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
#define | LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
#define | LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
#define | LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN
#define | LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN
#define | LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN
#define | LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
#define | LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN
#define | LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN
#define | LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN
#define | LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN
#define | LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
#define | LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
#define | LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN
#define | LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN
#define | LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM

Define Documentation

#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/

Definition at line 370 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN

Definition at line 369 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN

Definition at line 442 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN

Definition at line 412 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN

Definition at line 407 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN

Definition at line 437 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN

Definition at line 434 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN

Definition at line 373 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN

Definition at line 388 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN

Definition at line 393 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN

Definition at line 398 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN

Definition at line 378 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN

Definition at line 422 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN

Definition at line 383 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM

Definition at line 448 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN

Definition at line 447 of file stm32h7xx_ll_bus.h.

#define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN

Definition at line 417 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CKGA (AXI Clocks Gating) PERIPH

Defines
CKGA (AXI Clocks Gating) PERIPH
BUS Exported Constants

Defines

#define | LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG
#define | LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG
#define | LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG
#define | LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG
#define | LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG
#define | LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG
#define | LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG
#define | LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG
#define | LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG
#define | LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG
#define | LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG
#define | LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG
#define | LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG
#define | LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG
#define | LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG
#define | LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG
#define | LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG
#define | LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG
#define | LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG
#define | LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG
#define | LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG

Define Documentation

#define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG

Definition at line 459 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG

Definition at line 466 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG

Definition at line 467 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG

Definition at line 458 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG

Definition at line 472 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG

Definition at line 473 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG

Definition at line 474 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG

Definition at line 460 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG

Definition at line 463 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG

Definition at line 476 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG

Definition at line 477 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG

Definition at line 468 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG

Definition at line 470 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG

Definition at line 465 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG

Definition at line 475 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG

Definition at line 478 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG

Definition at line 464 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG

Definition at line 462 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG

Definition at line 471 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG

Definition at line 469 of file stm32h7xx_ll_bus.h.

#define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG

Definition at line 461 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB3

Functions
AHB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB3 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB3_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock
AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock
AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock
AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR GFXMMU LL_AHB3_GRP1_DisableClock
(*) AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock
(*) AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_MDMA
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_IOMNGR (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
  • LL_AHB3_GRP1_PERIPH_FLASH (*)
  • LL_AHB3_GRP1_PERIPH_DTCM1 (*)
  • LL_AHB3_GRP1_PERIPH_DTCM2 (*)
  • LL_AHB3_GRP1_PERIPH_ITCM (*)
  • LL_AHB3_GRP1_PERIPH_AXISRAM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 633 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep
(*) AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep
AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
  • LL_AHB3_GRP1_PERIPH_FLASH
  • LL_AHB3_GRP1_PERIPH_DTCM1
  • LL_AHB3_GRP1_PERIPH_DTCM2
  • LL_AHB3_GRP1_PERIPH_ITCM
  • LL_AHB3_GRP1_PERIPH_AXISRAM
(*) value not defined in all devices.
Return values:
None

Definition at line 799 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock
AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock
AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock
AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR GFXMMU LL_AHB3_GRP1_EnableClock
(*) AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock
AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock
(*) AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_MDMA
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
  • LL_AHB3_GRP1_PERIPH_FLASH (*)
  • LL_AHB3_GRP1_PERIPH_DTCM1 (*)
  • LL_AHB3_GRP1_PERIPH_DTCM2 (*)
  • LL_AHB3_GRP1_PERIPH_ITCM (*)
  • LL_AHB3_GRP1_PERIPH_AXISRAM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 537 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep
(*) AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep
AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
  • LL_AHB3_GRP1_PERIPH_FLASH
  • LL_AHB3_GRP1_PERIPH_DTCM1
  • LL_AHB3_GRP1_PERIPH_DTCM2
  • LL_AHB3_GRP1_PERIPH_ITCM
  • LL_AHB3_GRP1_PERIPH_AXISRAM
(*) value not defined in all devices.
Return values:
None

Definition at line 750 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ForceReset ( uint32_t Periphs )

Force AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset
AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset
AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset
AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset
(*) AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_MDMA
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
(*) value not defined in all devices.
Return values:
None

Definition at line 669 of file stm32h7xx_ll_bus.h.

Referenced by LL_DMA2D_DeInit(), and LL_MDMA_DeInit().

__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR GFXMMU LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock
(*) AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_MDMA
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_IOMNGR (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
  • LL_AHB3_GRP1_PERIPH_FLASH (*)
  • LL_AHB3_GRP1_PERIPH_DTCM1 (*)
  • LL_AHB3_GRP1_PERIPH_DTCM2 (*)
  • LL_AHB3_GRP1_PERIPH_ITCM (*)
  • LL_AHB3_GRP1_PERIPH_AXISRAM (*)
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 587 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset
(*) AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_MDMA
  • LL_AHB3_GRP1_PERIPH_DMA2D
  • LL_AHB3_GRP1_PERIPH_JPGDEC (*)
  • LL_AHB3_GRP1_PERIPH_FMC
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
  • LL_AHB3_GRP1_PERIPH_OSPI1 (*)
  • LL_AHB3_GRP1_PERIPH_OSPI2 (*)
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
  • LL_AHB3_GRP1_PERIPH_GFXMMU (*)
  • LL_AHB3_GRP1_PERIPH_SDMMC1
(*) value not defined in all devices.
Return values:
None

Definition at line 705 of file stm32h7xx_ll_bus.h.

Referenced by LL_DMA2D_DeInit(), and LL_MDMA_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock
AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock
(*) AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock
(*) AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock
(*) AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock
(*) AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock
AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock
AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock
(*) AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1TX (*)
  • LL_AHB1_GRP1_PERIPH_ETH1RX (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 916 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep
AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep
AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep
AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep
AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep
(*) AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1TX (*)
  • LL_AHB1_GRP1_PERIPH_ETH1RX (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1048 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock
AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock
(*) AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock
(*) AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock
(*) AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock
AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock
AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock
(*) AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1TX (*)
  • LL_AHB1_GRP1_PERIPH_ETH1RX (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 841 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep
(*) AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep
(*) AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep
(*) AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep
(*) AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep
AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep
(*) AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1TX (*)
  • LL_AHB1_GRP1_PERIPH_ETH1RX (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1008 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset
AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset
(*) AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
(*) AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset
(*) AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset
AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 944 of file stm32h7xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_BDMA_DeInit(), LL_CRC_DeInit(), and LL_DMA_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock
(*) AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1TX (*)
  • LL_AHB1_GRP1_PERIPH_ETH1RX (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 881 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset
(*) AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
(*) AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset
(*) AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_ADC12
  • LL_AHB1_GRP1_PERIPH_ART (*)
  • LL_AHB1_GRP1_PERIPH_CRC (*)
  • LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS
  • LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 972 of file stm32h7xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_BDMA_DeInit(), LL_CRC_DeInit(), and LL_DMA_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB2

Functions
AHB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock
AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_HSEMEN (*)
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
  • LL_AHB2_GRP1_PERIPH_D2SRAM1
  • LL_AHB2_GRP1_PERIPH_D2SRAM2
  • LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1156 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
  • LL_AHB2_GRP1_PERIPH_D2SRAM1
  • LL_AHB2_GRP1_PERIPH_D2SRAM2
  • LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1271 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock
AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_HSEM (*)
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
  • LL_AHB2_GRP1_PERIPH_D2SRAM1
  • LL_AHB2_GRP1_PERIPH_D2SRAM2
  • LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1088 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
  • LL_AHB2_GRP1_PERIPH_D2SRAM1
  • LL_AHB2_GRP1_PERIPH_D2SRAM2
  • LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1237 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset ( uint32_t Periphs )

Force AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset
AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_HSEM (*)
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1182 of file stm32h7xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_DCMI
  • LL_AHB2_GRP1_PERIPH_HSEMEN (*)
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
  • LL_AHB2_GRP1_PERIPH_D2SRAM1
  • LL_AHB2_GRP1_PERIPH_D2SRAM2
  • LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 1124 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_HSEM (*)
  • LL_AHB2_GRP1_PERIPH_CRYP (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_SDMMC2
  • LL_AHB2_GRP1_PERIPH_BDMA1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1207 of file stm32h7xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB4

Functions
AHB4
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB4_GRP1_EnableClock (uint32_t Periphs)
Enable AHB4 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB4_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB4 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB4_GRP1_DisableClock (uint32_t Periphs)
Disable AHB4 peripherals clock.
__STATIC_INLINE void | LL_AHB4_GRP1_ForceReset (uint32_t Periphs)
Force AHB4 peripherals reset.
__STATIC_INLINE void | LL_AHB4_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB4 peripherals reset.
__STATIC_INLINE void | LL_AHB4_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB4_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB4 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB4_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB4 peripherals clock.

Reference Manual to LL API cross reference:
AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock
AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock
AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock
(*) AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock
AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock
(*) AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock
(*) AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock
AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_HSEM (*)
  • LL_AHB4_GRP1_PERIPH_BKPRAM
  • LL_AHB4_GRP1_PERIPH_SRAM4
(*) value not defined in all devices.
Return values:
None

Definition at line 1421 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB4 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep
(*) AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep
(*) AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep
AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_BKPRAM
  • LL_AHB4_GRP1_PERIPH_SRAM4
Return values:
None

Definition at line 1593 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB4_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB4 peripherals clock.

Reference Manual to LL API cross reference:
AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock
AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock
AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock
(*) AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock
AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock
(*) AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock
(*) AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock
AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_HSEM (*)
  • LL_AHB4_GRP1_PERIPH_BKPRAM
  • LL_AHB4_GRP1_PERIPH_SRAM4
(*) value not defined in all devices.
Return values:
None

Definition at line 1325 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB4 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep
(*) AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep
(*) AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep
AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_BKPRAM
  • LL_AHB4_GRP1_PERIPH_SRAM4
Return values:
None

Definition at line 1547 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB4_GRP1_ForceReset ( uint32_t Periphs )

Force AHB4 peripherals reset.

Reference Manual to LL API cross reference:
AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset
AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset
AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset
(*) AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset
AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset
(*) AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_HSEM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1463 of file stm32h7xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_CRC_DeInit(), and LL_GPIO_DeInit().

__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB4 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock
(*) AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock
(*) AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock
(*) AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock
AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_HSEM (*)
  • LL_AHB4_GRP1_PERIPH_BKPRAM
  • LL_AHB4_GRP1_PERIPH_SRAM4
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 1375 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB4 peripherals reset.

Reference Manual to LL API cross reference:
AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset
(*) AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset
AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset
(*) AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB4_GRP1_PERIPH_GPIOA
  • LL_AHB4_GRP1_PERIPH_GPIOB
  • LL_AHB4_GRP1_PERIPH_GPIOC
  • LL_AHB4_GRP1_PERIPH_GPIOD
  • LL_AHB4_GRP1_PERIPH_GPIOE
  • LL_AHB4_GRP1_PERIPH_GPIOF
  • LL_AHB4_GRP1_PERIPH_GPIOG
  • LL_AHB4_GRP1_PERIPH_GPIOH
  • LL_AHB4_GRP1_PERIPH_GPIOI
  • LL_AHB4_GRP1_PERIPH_GPIOJ
  • LL_AHB4_GRP1_PERIPH_GPIOK
  • LL_AHB4_GRP1_PERIPH_CRC (*)
  • LL_AHB4_GRP1_PERIPH_BDMA
  • LL_AHB4_GRP1_PERIPH_ADC3 (*)
  • LL_AHB4_GRP1_PERIPH_HSEM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1505 of file stm32h7xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_CRC_DeInit(), and LL_GPIO_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB3

Functions
APB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB3_GRP1_EnableClock (uint32_t Periphs)
Enable APB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB3_GRP1_DisableClock (uint32_t Periphs)
Disable APB3 peripherals clock.
__STATIC_INLINE void | LL_APB3_GRP1_ForceReset (uint32_t Periphs)
Force APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_ReleaseReset (uint32_t Periphs)
Release APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB3 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB3_GRP1_DisableClock ( uint32_t Periphs )

Disable APB3 peripherals clock.

Reference Manual to LL API cross reference:
APB3ENR LTDCEN LL_APB3_GRP1_DisableClock
APB3ENR DSIEN LL_APB3_GRP1_DisableClock
APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
  • LL_APB3_GRP1_PERIPH_WWDG1
(*) value not defined in all devices.
Return values:
None

Definition at line 1659 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep
(*) APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep
(*) APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
  • LL_APB3_GRP1_PERIPH_WWDG1
(*) value not defined in all devices.
Return values:
None

Definition at line 1731 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_EnableClock ( uint32_t Periphs )

Enable APB3 peripherals clock.

Reference Manual to LL API cross reference:
APB3ENR LTDCEN LL_APB3_GRP1_EnableClock
(*) APB3ENR DSIEN LL_APB3_GRP1_EnableClock
(*) APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
  • LL_APB3_GRP1_PERIPH_WWDG1
(*) value not defined in all devices.
Return values:
None

Definition at line 1619 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep
(*) APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep
(*) APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
  • LL_APB3_GRP1_PERIPH_WWDG1
(*) value not defined in all devices.
Return values:
None

Definition at line 1709 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_ForceReset ( uint32_t Periphs )

Force APB3 peripherals reset.

Reference Manual to LL API cross reference:
APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset
(*) APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1675 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock
(*) APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock
(*) APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
  • LL_APB3_GRP1_PERIPH_WWDG1
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 1641 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB3 peripherals reset.

Reference Manual to LL API cross reference:
APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset
APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_LTDC (*)
  • LL_APB3_GRP1_PERIPH_DSI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1691 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1LENR TIM2EN LL_APB1_GRP1_DisableClock
APB1LENR TIM3EN LL_APB1_GRP1_DisableClock
APB1LENR TIM4EN LL_APB1_GRP1_DisableClock
APB1LENR TIM5EN LL_APB1_GRP1_DisableClock
APB1LENR TIM6EN LL_APB1_GRP1_DisableClock
APB1LENR TIM7EN LL_APB1_GRP1_DisableClock
APB1LENR TIM12EN LL_APB1_GRP1_DisableClock
APB1LENR TIM13EN LL_APB1_GRP1_DisableClock
APB1LENR TIM14EN LL_APB1_GRP1_DisableClock
APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock
APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_DisableClock
APB1LENR SPI3EN LL_APB1_GRP1_DisableClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock
APB1LENR USART2EN LL_APB1_GRP1_DisableClock
APB1LENR USART3EN LL_APB1_GRP1_DisableClock
APB1LENR UART4EN LL_APB1_GRP1_DisableClock
APB1LENR UART5EN LL_APB1_GRP1_DisableClock
APB1LENR I2C1EN LL_APB1_GRP1_DisableClock
APB1LENR I2C2EN LL_APB1_GRP1_DisableClock
APB1LENR I2C3EN LL_APB1_GRP1_DisableClock
APB1LENR CECEN LL_APB1_GRP1_DisableClock
APB1LENR DAC12EN LL_APB1_GRP1_DisableClock
APB1LENR UART7EN LL_APB1_GRP1_DisableClock
APB1LENR UART8EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_WWDG2 (*)
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
(*) value not defined in all devices.
Return values:
None

Definition at line 1929 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep
(*) APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_WWDG2 (*)
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
(*) value not defined in all devices.
Return values:
None

Definition at line 2173 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1LENR TIM2EN LL_APB1_GRP1_EnableClock
APB1LENR TIM3EN LL_APB1_GRP1_EnableClock
APB1LENR TIM4EN LL_APB1_GRP1_EnableClock
APB1LENR TIM5EN LL_APB1_GRP1_EnableClock
APB1LENR TIM6EN LL_APB1_GRP1_EnableClock
APB1LENR TIM7EN LL_APB1_GRP1_EnableClock
APB1LENR TIM12EN LL_APB1_GRP1_EnableClock
APB1LENR TIM13EN LL_APB1_GRP1_EnableClock
APB1LENR TIM14EN LL_APB1_GRP1_EnableClock
APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock
APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_EnableClock
APB1LENR SPI3EN LL_APB1_GRP1_EnableClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock
APB1LENR USART2EN LL_APB1_GRP1_EnableClock
APB1LENR USART3EN LL_APB1_GRP1_EnableClock
APB1LENR UART4EN LL_APB1_GRP1_EnableClock
APB1LENR UART5EN LL_APB1_GRP1_EnableClock
APB1LENR I2C1EN LL_APB1_GRP1_EnableClock
APB1LENR I2C2EN LL_APB1_GRP1_EnableClock
APB1LENR I2C3EN LL_APB1_GRP1_EnableClock
APB1LENR CECEN LL_APB1_GRP1_EnableClock
APB1LENR DAC12EN LL_APB1_GRP1_EnableClock
APB1LENR UART7EN LL_APB1_GRP1_EnableClock
APB1LENR UART8EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_WWDG2 (*)
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
(*) value not defined in all devices.
Return values:
None

Definition at line 1801 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep
(*) APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_WWDG2 (*)
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
(*) value not defined in all devices.
Return values:
None

Definition at line 2107 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset
APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset
APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset
APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset
APB1LRSTR CECRST LL_APB1_GRP1_ForceReset
APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
Return values:
None

Definition at line 1987 of file stm32h7xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock
APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock
APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock
APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock
APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_WWDG2 (*)
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 1867 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset
APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset
APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_TIM12
  • LL_APB1_GRP1_PERIPH_TIM13
  • LL_APB1_GRP1_PERIPH_TIM14
  • LL_APB1_GRP1_PERIPH_LPTIM1
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_SPDIFRX
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4
  • LL_APB1_GRP1_PERIPH_UART5
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CEC
  • LL_APB1_GRP1_PERIPH_DAC12
  • LL_APB1_GRP1_PERIPH_UART7
  • LL_APB1_GRP1_PERIPH_UART8
Return values:
None

Definition at line 2045 of file stm32h7xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1HENR CRSEN LL_APB1_GRP2_DisableClock
APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock
APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock
APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock
APB1HENR FDCANEN LL_APB1_GRP2_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2237 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep ( uint32_t Periphs )

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2321 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1HENR CRSEN LL_APB1_GRP2_EnableClock
APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock
APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock
APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock
APB1HENR FDCANEN LL_APB1_GRP2_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2193 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep ( uint32_t Periphs )

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2297 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset
APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset
APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset
APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset
APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2257 of file stm32h7xx_ll_bus.h.

Referenced by LL_SWPMI_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock
APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock
APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock
APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock
APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
uint32_t

Definition at line 2217 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_CRS
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_OPAMP
  • LL_APB1_GRP2_PERIPH_MDIOS
  • LL_APB1_GRP2_PERIPH_FDCAN
Return values:
None

Definition at line 2277 of file stm32h7xx_ll_bus.h.

Referenced by LL_SWPMI_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM8EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
APB2ENR USART6EN LL_APB2_GRP1_DisableClock
APB2ENR UART9EN LL_APB2_GRP1_DisableClock
(*) APB2ENR USART10EN LL_APB2_GRP1_DisableClock
(*) APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI4EN LL_APB2_GRP1_DisableClock
APB2ENR TIM15EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR SPI5EN LL_APB2_GRP1_DisableClock
APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
APB2ENR SAI2EN LL_APB2_GRP1_DisableClock
APB2ENR SAI3EN LL_APB2_GRP1_DisableClock
(*) APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2471 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep
APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep
(*) APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep
(*) APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep
(*) APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep
APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
Return values:
None

Definition at line 2655 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM8EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
APB2ENR USART6EN LL_APB2_GRP1_EnableClock
APB2ENR UART9EN LL_APB2_GRP1_EnableClock
(*) APB2ENR USART10EN LL_APB2_GRP1_EnableClock
(*) APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI4EN LL_APB2_GRP1_EnableClock
APB2ENR TIM15EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR SPI5EN LL_APB2_GRP1_EnableClock
APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
APB2ENR SAI2EN LL_APB2_GRP1_EnableClock
APB2ENR SAI3EN LL_APB2_GRP1_EnableClock
(*) APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2375 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep
APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep
(*) APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep
(*) APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep
(*) APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep
APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
Return values:
None

Definition at line 2607 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR USART6RST LL_APB2_GRP1_ForceReset
APB2ENR UART9RST LL_APB2_GRP1_ForceReset
(*) APB2ENR USART10RST LL_APB2_GRP1_ForceReset
(*) APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset
(*) APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2517 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock
APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock
(*) APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock
(*) APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock
APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 2425 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset
APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset
(*) APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset
(*) APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset
(*) APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_USART6
  • LL_APB2_GRP1_PERIPH_UART9 (*)
  • LL_APB2_GRP1_PERIPH_USART10 (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_SPI4
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SPI5
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2
  • LL_APB2_GRP1_PERIPH_SAI3 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1
  • LL_APB2_GRP1_PERIPH_HRTIM (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2563 of file stm32h7xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB4

Functions
APB4
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB4_GRP1_EnableClock (uint32_t Periphs)
Enable APB4 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB4_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB4 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB4_GRP1_DisableClock (uint32_t Periphs)
Disable APB4 peripherals clock.
__STATIC_INLINE void | LL_APB4_GRP1_ForceReset (uint32_t Periphs)
Force APB4 peripherals reset.
__STATIC_INLINE void | LL_APB4_GRP1_ReleaseReset (uint32_t Periphs)
Release APB4 peripherals reset.
__STATIC_INLINE void | LL_APB4_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB4_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB4 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB4_GRP1_DisableClock ( uint32_t Periphs )

Disable APB4 peripherals clock.

Reference Manual to LL API cross reference:
APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock
APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock
APB4ENR SPI6EN LL_APB4_GRP1_DisableClock
APB4ENR I2C4EN LL_APB4_GRP1_DisableClock
APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock
APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock
APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock
(*) APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock
(*) APB4ENR DAC2EN LL_APB4_GRP1_DisableClock
(*) APB4ENR COMP12EN LL_APB4_GRP1_DisableClock
APB4ENR VREFEN LL_APB4_GRP1_DisableClock
APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock
APB4ENR SAI4EN LL_APB4_GRP1_DisableClock
(*) APB4ENR DTSEN LL_APB4_GRP1_DisableClock
(*) APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_RTCAPB
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2793 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB4 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep
(*) APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep
(*) APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep
(*) APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep
APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep
(*) APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep
(*) APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_RTCAPB
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2961 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB4_GRP1_EnableClock ( uint32_t Periphs )

Enable APB4 peripherals clock.

Reference Manual to LL API cross reference:
APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock
APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock
APB4ENR SPI6EN LL_APB4_GRP1_EnableClock
APB4ENR I2C4EN LL_APB4_GRP1_EnableClock
APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock
APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock
APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock
(*) APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock
(*) APB4ENR DAC2EN LL_APB4_GRP1_EnableClock
(*) APB4ENR COMP12EN LL_APB4_GRP1_EnableClock
APB4ENR VREFEN LL_APB4_GRP1_EnableClock
APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock
APB4ENR SAI4EN LL_APB4_GRP1_EnableClock
(*) APB4ENR DTSEN LL_APB4_GRP1_EnableClock
(*) APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_RTCAPB
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2705 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB4 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep
(*) APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep
(*) APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep
(*) APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep
APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep
(*) APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep
(*) APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_RTCAPB
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2915 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB4_GRP1_ForceReset ( uint32_t Periphs )

Force APB4 peripherals reset.

Reference Manual to LL API cross reference:
APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset
APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset
APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset
APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset
APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset
APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset
APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset
(*) APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset
(*) APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset
(*) APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset
APB4RSTR VREFRST LL_APB4_GRP1_ForceReset
APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset
(*) APB4RSTR DTSRST LL_APB4_GRP1_ForceReset
(*) APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2833 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_LPUART_DeInit(), and LL_SPI_DeInit().

__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB4 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock
APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock
APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock
APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock
APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock
APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock
APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock
(*) APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock
(*) APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock
(*) APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock
APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock
APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock
APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock
(*) APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock
(*) APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_RTCAPB
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
uint32_t

Definition at line 2751 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB4 peripherals reset.

Reference Manual to LL API cross reference:
APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset
APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset
APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset
APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset
APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset
APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset
APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset
(*) APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset
(*) APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset
(*) APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset
APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset
APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset
APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset
(*) APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*)
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB4_GRP1_PERIPH_SYSCFG
  • LL_APB4_GRP1_PERIPH_LPUART1
  • LL_APB4_GRP1_PERIPH_SPI6
  • LL_APB4_GRP1_PERIPH_I2C4
  • LL_APB4_GRP1_PERIPH_LPTIM2
  • LL_APB4_GRP1_PERIPH_LPTIM3
  • LL_APB4_GRP1_PERIPH_LPTIM4 (*)
  • LL_APB4_GRP1_PERIPH_LPTIM5 (*)
  • LL_APB4_GRP1_PERIPH_DAC2 (*)
  • LL_APB4_GRP1_PERIPH_COMP12
  • LL_APB4_GRP1_PERIPH_VREF
  • LL_APB4_GRP1_PERIPH_SAI4 (*)
  • LL_APB4_GRP1_PERIPH_DTS (*)
  • LL_APB4_GRP1_PERIPH_DFSDM2 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2873 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_LPUART_DeInit(), and LL_SPI_DeInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BUS_LL_EF_CLKAM

Functions
BUS_LL_EF_CLKAM
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_CLKAM_Enable (uint32_t Periphs)
Enable peripherals clock for CLKAM Mode.
__STATIC_INLINE void | LL_CLKAM_Disable (uint32_t Periphs)
Disable peripherals clock for CLKAM Mode.

Function Documentation

__STATIC_INLINE void LL_CLKAM_Disable ( uint32_t Periphs )

Disable peripherals clock for CLKAM Mode.

Reference Manual to LL API cross reference:
D3AMR / SRDAMR BDMA LL_CLKAM_Disable
D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable
D3AMR / SRDAMR SPI6 LL_CLKAM_Disable
D3AMR / SRDAMR I2C4 LL_CLKAM_Disable
D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable
D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable
D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable
(*) D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable
(*) D3AMR / SRDAMR DAC2 LL_CLKAM_Disable
(*) D3AMR / SRDAMR COMP12 LL_CLKAM_Disable
D3AMR / SRDAMR VREF LL_CLKAM_Disable
D3AMR / SRDAMR RTC LL_CLKAM_Disable
D3AMR / SRDAMR CRC LL_CLKAM_Disable
D3AMR / SRDAMR SAI4 LL_CLKAM_Disable
(*) D3AMR / SRDAMR ADC3 LL_CLKAM_Disable
(*) D3AMR / SRDAMR DTS LL_CLKAM_Disable
(*) D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable
(*) D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable
D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_CLKAM_PERIPH_BDMA
  • LL_CLKAM_PERIPH_LPUART1
  • LL_CLKAM_PERIPH_SPI6
  • LL_CLKAM_PERIPH_I2C4
  • LL_CLKAM_PERIPH_LPTIM2
  • LL_CLKAM_PERIPH_LPTIM3
  • LL_CLKAM_PERIPH_LPTIM4 (*)
  • LL_CLKAM_PERIPH_LPTIM5 (*)
  • LL_CLKAM_PERIPH_DAC2 (*)
  • LL_CLKAM_PERIPH_COMP12
  • LL_CLKAM_PERIPH_VREF
  • LL_CLKAM_PERIPH_RTC
  • LL_CLKAM_PERIPH_CRC
  • LL_CLKAM_PERIPH_SAI4 (*)
  • LL_CLKAM_PERIPH_ADC3 (*)
  • LL_CLKAM_PERIPH_DTS (*)
  • LL_CLKAM_PERIPH_DFSDM2 (*)
  • LL_CLKAM_PERIPH_BKPRAM
  • LL_CLKAM_PERIPH_SRAM4
(*) value not defined in all devices.
Return values:
None

Definition at line 3080 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_CLKAM_Enable ( uint32_t Periphs )

Enable peripherals clock for CLKAM Mode.

Reference Manual to LL API cross reference:
D3AMR / SRDAMR BDMA LL_CLKAM_Enable
D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable
D3AMR / SRDAMR SPI6 LL_CLKAM_Enable
D3AMR / SRDAMR I2C4 LL_CLKAM_Enable
D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable
D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable
D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable
(*) D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable
(*) D3AMR / SRDAMR DAC2 LL_CLKAM_Enable
(*) D3AMR / SRDAMR COMP12 LL_CLKAM_Enable
D3AMR / SRDAMR VREF LL_CLKAM_Enable
D3AMR / SRDAMR RTC LL_CLKAM_Enable
D3AMR / SRDAMR CRC LL_CLKAM_Enable
D3AMR / SRDAMR SAI4 LL_CLKAM_Enable
(*) D3AMR / SRDAMR ADC3 LL_CLKAM_Enable
(*) D3AMR / SRDAMR DTS LL_CLKAM_Enable
(*) D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable
(*) D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable
D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_CLKAM_PERIPH_BDMA
  • LL_CLKAM_PERIPH_LPUART1
  • LL_CLKAM_PERIPH_SPI6
  • LL_CLKAM_PERIPH_I2C4
  • LL_CLKAM_PERIPH_LPTIM2
  • LL_CLKAM_PERIPH_LPTIM3
  • LL_CLKAM_PERIPH_LPTIM4 (*)
  • LL_CLKAM_PERIPH_LPTIM5 (*)
  • LL_CLKAM_PERIPH_DAC2 (*)
  • LL_CLKAM_PERIPH_COMP12
  • LL_CLKAM_PERIPH_VREF
  • LL_CLKAM_PERIPH_RTC
  • LL_CLKAM_PERIPH_CRC
  • LL_CLKAM_PERIPH_SAI4 (*)
  • LL_CLKAM_PERIPH_ADC3 (*)
  • LL_CLKAM_PERIPH_DTS (*)
  • LL_CLKAM_PERIPH_DFSDM2 (*)
  • LL_CLKAM_PERIPH_BKPRAM
  • LL_CLKAM_PERIPH_SRAM4
(*) value not defined in all devices.
Return values:
None

Definition at line 3019 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BUS Exported Functions

Modules | Functions
BUS Exported Functions
BUS Exported Constants

Modules

AHB3
AHB1
AHB2
AHB4
APB3
APB1
APB2
APB4
BUS_LL_EF_CLKAM

Functions

__STATIC_INLINE void LL_CKGA_Enable (uint32_t Periphs)
Enable clock gating for AXI bus peripherals.

Function Documentation

__STATIC_INLINE void LL_CKGA_Enable ( uint32_t Periphs )

Enable clock gating for AXI bus peripherals.

Reference Manual to LL API cross reference:
Parameters:
:
Return values:
None

Definition at line 3100 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BUS

Modules | Functions
BUS
STM32H7xx_LL_Driver

Modules

BUS Exported Constants

Functions

__STATIC_INLINE void LL_CKGA_Disable (uint32_t Periphs)
Disable clock gating for AXI bus peripherals.

Function Documentation

__STATIC_INLINE void LL_CKGA_Disable ( uint32_t Periphs )

Disable clock gating for AXI bus peripherals.

Reference Manual to LL API cross reference:
Parameters:
:
Return values:
None

Definition at line 3124 of file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:28 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Definition at line 49 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32h7xx_ll_comp.h>

Data Fields

uint32_t | PowerMode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputPolarity
uint32_t | OutputBlankingSource

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 65 of file stm32h7xx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis

This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 82 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 77 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 72 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputBlankingSource

Set comparator blanking source. This parameter can be a value of Comparator output - Blanking source

This feature can be modified afterwards using unitary function LL_COMP_SetOutputBlankingSource().

Definition at line 92 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity

This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 87 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::PowerMode

Set comparator operating mode to adjust power and speed. This parameter can be a value of Comparator modes - Power mode

This feature can be modified afterwards using unitary function LL_COMP_SetPowerMode().

Definition at line 67 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_comp.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Comparator common modes - Window mode

Defines
Comparator common modes - Window mode
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Define Documentation

#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 113 of file stm32h7xx_ll_comp.h.

#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)

Window mode disable: Comparators 1 and 2 are independent

Definition at line 112 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Comparator modes - Power mode

Defines
Comparator modes - Power mode
COMP Exported Constants

Defines

#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE_1 | COMP_CFGRx_PWRMODE_0)

Define Documentation

#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)

COMP power mode to high speed

Definition at line 121 of file stm32h7xx_ll_comp.h.

#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)

COMP power mode to medium speed

Definition at line 122 of file stm32h7xx_ll_comp.h.

#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE_1 | COMP_CFGRx_PWRMODE_0)

COMP power mode to ultra-low power

Definition at line 123 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)
#define | LL_COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)

Define Documentation

#define LL_COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)

Comparator input plus 2 connected to (DAC2_CH1 for COMP1)

Definition at line 134 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2)

Definition at line 131 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2)

Definition at line 132 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )
#define | LL_COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )
#define | LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )
#define | LL_COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 144 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 143 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 145 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 147 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 148 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2)

Definition at line 149 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2)

Definition at line 150 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )

Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2)

Definition at line 152 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )

Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2)

Definition at line 153 of file stm32h7xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 146 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32H7B3xQ HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CFGRx_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST_1 | COMP_CFGRx_HYST_0)

Define Documentation

#define LL_COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST_1 | COMP_CFGRx_HYST_0)

Hysteresis level high

Definition at line 165 of file stm32h7xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW ( COMP_CFGRx_HYST_0)

Hysteresis level low

Definition at line 163 of file stm32h7xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1 )

Hysteresis level medium

Definition at line 164 of file stm32h7xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 162 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32H7B3xQ HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 174 of file stm32h7xx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 173 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32H7B3xQ HAL User Manual: Comparator output - Blanking source

Defines
Comparator output - Blanking source
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

Define Documentation

#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 182 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

Comparator output blanking source TIM15 OC1 (common to all COMP instances: COMP1, COMP2)

Definition at line 188 of file stm32h7xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)

Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2)

Definition at line 183 of file stm32h7xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)

Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2)

Definition at line 184 of file stm32h7xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)

Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2)

Definition at line 185 of file stm32h7xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)

Comparator output blanking source TIM3 OC4 (common to all COMP instances: COMP1, COMP2)

Definition at line 186 of file stm32h7xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)

Comparator output blanking source TIM8 OC5 (common to all COMP instances: COMP1, COMP2)

Definition at line 187 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 197 of file stm32h7xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 196 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Comparator output - Output to BKIN timer

Defines
Comparator output - Output to BKIN timer
COMP Exported Constants

Defines

#define | LL_COMP_AF_PA6 COMP_OR_AFOPA6
#define | LL_COMP_AF_PA8 COMP_OR_AFOPA8
#define | LL_COMP_AF_PB12 COMP_OR_AFOPB12
#define | LL_COMP_AF_PE6 COMP_OR_AFOPE6
#define | LL_COMP_AF_PE15 COMP_OR_AFOPE15
#define | LL_COMP_AF_PG2 COMP_OR_AFOPG2
#define | LL_COMP_AF_PG3 COMP_OR_AFOPG3
#define | LL_COMP_AF_PG4 COMP_OR_AFOPG4
#define | LL_COMP_AF_PI1 COMP_OR_AFOPI1
#define | LL_COMP_AF_PI4 COMP_OR_AFOPI4
#define | LL_COMP_AF_PK2 COMP_OR_AFOPK2

Define Documentation

#define LL_COMP_AF_PA6 COMP_OR_AFOPA6

Comparator Alternate Function PA6 source selected to timer BKIN input

Definition at line 204 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PA8 COMP_OR_AFOPA8

Comparator Alternate Function PA8 source selected to timer BKIN input

Definition at line 205 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PB12 COMP_OR_AFOPB12

Comparator Alternate Function PB12 source selected to timer BKIN input

Definition at line 206 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PE15 COMP_OR_AFOPE15

Comparator Alternate Function PE15 source selected to timer BKIN input

Definition at line 208 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PE6 COMP_OR_AFOPE6

Comparator Alternate Function PE6 source selected to timer BKIN input

Definition at line 207 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PG2 COMP_OR_AFOPG2

Comparator Alternate Function PG2 source selected to timer BKIN input

Definition at line 209 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PG3 COMP_OR_AFOPG3

Comparator Alternate Function PG3 source selected to timer BKIN input

Definition at line 210 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PG4 COMP_OR_AFOPG4

Comparator Alternate Function PG4 source selected to timer BKIN input

Definition at line 211 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PI1 COMP_OR_AFOPI1

Comparator Alternate Function PI1 source selected to timer BKIN input

Definition at line 212 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PI4 COMP_OR_AFOPI4

Comparator Alternate Function PI4 source selected to timer BKIN input

Definition at line 213 of file stm32h7xx_ll_comp.h.

#define LL_COMP_AF_PK2 COMP_OR_AFOPK2

Comparator Alternate Function PK2 source selected to timer BKIN input

Definition at line 214 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Detailed Description

Note:
Only COMP IP HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ( 80UL)

Delay for COMP startup time

Definition at line 232 of file stm32h7xx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 240 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 273 of file stm32h7xx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 265 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_DeInit().

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STM32H7B3xQ HAL User Manual: COMP helper macro

Defines
COMP helper macro
COMP Exported Macros

Defines

#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Define Documentation

#define __LL_COMP_COMMON_INSTANCE ( __COMPx__ ) (COMP12_COMMON)

Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Note:
COMP common register instance can be used to set parameters common to several COMP instances. Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
__COMPx__ COMP instance
Return values:
COMP common instance or value "0" if there is no COMP common instance.

Definition at line 291 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Configuration of COMP hierarchical scope: common to several COMP instances

Functions
Configuration of COMP hierarchical scope: common to several COMP instances
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CFGRx WINMODE LL_COMP_GetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

Definition at line 339 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetCommonWindowMode | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowMode
 | ) |  |

Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CFGRx WINMODE LL_COMP_SetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowMode This parameter can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Return values:
None

Definition at line 322 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Configuration of comparator modes

Functions
Configuration of comparator modes
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetPowerMode ( COMP_TypeDef * COMPx )

Get comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CFGRx PWRMODE LL_COMP_GetPowerMode
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER

Definition at line 376 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetPowerMode | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CFGRx PWRMODE LL_COMP_SetPowerMode
Parameters:
COMPx Comparator instance
PowerMode This parameter can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER
Return values:
None

Definition at line 362 of file stm32h7xx_ll_comp.h.

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STM32H7B3xQ HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CFGRx INMSEL LL_COMP_ConfigInputs
CFGRx INPSEL LL_COMP_ConfigInputs
CFGRx BRGEN LL_COMP_ConfigInputs
CFGRx SCALEN LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2 #if defined (COMP_CFGRx_INMSEL_3)
  • LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
  • LL_COMP_INPUT_MINUS_VBAT_VDDAP #endif
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2 #if defined (COMP_CFGRx_INP2SEL)
  • LL_COMP_INPUT_PLUS_DAC2_CH1 #endif
Return values:
None

Definition at line 432 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH

Definition at line 590 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CFGRx INMSEL LL_COMP_GetInputMinus
CFGRx BRGEN LL_COMP_GetInputMinus
CFGRx SCALEN LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2 #if defined (COMP_CFGRx_INMSEL_3)
  • LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
  • LL_COMP_INPUT_MINUS_VBAT_VDDAP #endif

Definition at line 559 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CFGRx INPSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2 #if defined (COMP_CFGRx_INP2SEL)
  • LL_COMP_INPUT_PLUS_DAC2_CH1 #endif

Definition at line 486 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CFGRx HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 575 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CFGRx INMSEL LL_COMP_SetInputMinus
CFGRx BRGEN LL_COMP_SetInputMinus
CFGRx SCALEN LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2 #if defined (COMP_CFGRx_INMSEL_3)
  • LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
  • LL_COMP_INPUT_MINUS_VBAT_VDDAP #endif
Return values:
None

Definition at line 531 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CFGRx INPSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2 #if defined (COMP_CFGRx_INP2SEL)
  • LL_COMP_INPUT_PLUS_DAC2_CH1 #endif
Return values:
None

Definition at line 463 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_SetOutputAlternateFunction (COMP_TypeDef *COMPx, uint32_t CompAFx)
Set the output alternate function in the Option register in order to be used with the alternate function of the timer break input.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputAlternateFunction (COMP_TypeDef *COMPx)
Get the output alternate function from the Option register.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction ( COMP_TypeDef * COMPx )

Get the output alternate function from the Option register.

Reference Manual to LL API cross reference:
OR AFOP COMP_LL_EC_OUTPUT_BKIN_TIMER
Parameters:
COMPx specifies the Comparator instance.
Return values:
Returned value can be one of the following values:
  • LL_COMP_AF_PA6
  • LL_COMP_AF_PA8
  • LL_COMP_AF_PB12
  • LL_COMP_AF_PE6
  • LL_COMP_AF_PE15
  • LL_COMP_AF_PG2
  • LL_COMP_AF_PG3
  • LL_COMP_AF_PG4
  • LL_COMP_AF_PI1
  • LL_COMP_AF_PI4
  • LL_COMP_AF_PK2

Definition at line 716 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource ( COMP_TypeDef * COMPx )

Get comparator instance blanking source.

Note:
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CFGR BLANKING LL_COMP_GetOutputBlankingSource
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5
  • LL_COMP_BLANKINGSRC_TIM2_OC3
  • LL_COMP_BLANKINGSRC_TIM3_OC3
  • LL_COMP_BLANKINGSRC_TIM3_OC4
  • LL_COMP_BLANKINGSRC_TIM8_OC5
  • LL_COMP_BLANKINGSRC_TIM15_OC1

Definition at line 670 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CFGRx POLARITY LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 625 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | CompAFx
 | ) |  |

Set the output alternate function in the Option register in order to be used with the alternate function of the timer break input.

Reference Manual to LL API cross reference:
OR AFOP COMP_LL_EC_OUTPUT_BKIN_TIMER
Parameters:
COMPx specifies the instance.
CompAFx specifies the Alternate Function source selection. This parameter can be one of the following values:
  • LL_COMP_AF_PA6
  • LL_COMP_AF_PA8
  • LL_COMP_AF_PB12
  • LL_COMP_AF_PE6
  • LL_COMP_AF_PE15
  • LL_COMP_AF_PG2
  • LL_COMP_AF_PG3
  • LL_COMP_AF_PG4
  • LL_COMP_AF_PI1
  • LL_COMP_AF_PI4
  • LL_COMP_AF_PK2
Return values:
None

Definition at line 695 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputBlankingSource | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | BlankingSource
 | ) |  |

Set comparator instance blanking source.

Note:
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR BLANKING LL_COMP_SetOutputBlankingSource
Parameters:
COMPx Comparator instance
BlankingSource This parameter can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5
  • LL_COMP_BLANKINGSRC_TIM2_OC3
  • LL_COMP_BLANKINGSRC_TIM3_OC3
  • LL_COMP_BLANKINGSRC_TIM3_OC4
  • LL_COMP_BLANKINGSRC_TIM8_OC5
  • LL_COMP_BLANKINGSRC_TIM15_OC1
Return values:
None

Definition at line 648 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CFGRx POLARITY LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 612 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CFGR EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 749 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CFGR EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 738 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CFGR EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 761 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CFGR LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 788 of file stm32h7xx_ll_comp.h.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CFGR LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 774 of file stm32h7xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
The comparator output level depends on the selected polarity (Refer to function LL_COMP_SetOutputPolarity()). If the comparator polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the comparator polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CFGR VALUE LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 813 of file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 150 of file stm32h7xx_ll_comp.c.

References assert_param, LL_COMP_IsLocked(), and LL_COMP_WriteReg.

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 187 of file stm32h7xx_ll_comp.c.

References assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_BLANKING_SOURCE, IS_LL_COMP_OUTPUT_POLARITY, IS_LL_COMP_POWER_MODE, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct Pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 265 of file stm32h7xx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_BLANKINGSRC_NONE, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_POWERMODE_ULTRALOWPOWER, LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COMP_LL_Private_Macros

Defines
COMP_LL_Private_Macros
COMP

Defines

#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Define Documentation

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
  )

Definition at line 101 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1)                \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VBAT_VDDAP))

Definition at line 78 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC2_CH1))

Definition at line 63 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)          \
  )

Definition at line 113 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 108 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
  )

Definition at line 52 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 71 of file stm32h7xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 70 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 80 of file stm32h7xx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 81 of file stm32h7xx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 79 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 92 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 94 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL

Disable NMI and privileged SW access

Definition at line 91 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 93 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 0x00UL
#define | LL_MPU_REGION_NUMBER1 0x01UL
#define | LL_MPU_REGION_NUMBER2 0x02UL
#define | LL_MPU_REGION_NUMBER3 0x03UL
#define | LL_MPU_REGION_NUMBER4 0x04UL
#define | LL_MPU_REGION_NUMBER5 0x05UL
#define | LL_MPU_REGION_NUMBER6 0x06UL
#define | LL_MPU_REGION_NUMBER7 0x07UL
#define | LL_MPU_REGION_NUMBER8 0x08UL
#define | LL_MPU_REGION_NUMBER9 0x09UL
#define | LL_MPU_REGION_NUMBER10 0x0AUL
#define | LL_MPU_REGION_NUMBER11 0x0BUL
#define | LL_MPU_REGION_NUMBER12 0x0CUL
#define | LL_MPU_REGION_NUMBER13 0x0DUL
#define | LL_MPU_REGION_NUMBER14 0x0EUL
#define | LL_MPU_REGION_NUMBER15 0x0FUL

Define Documentation

#define LL_MPU_REGION_NUMBER0 0x00UL

REGION Number 0

Definition at line 102 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 0x01UL

REGION Number 1

Definition at line 103 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER10 0x0AUL

REGION Number 10

Definition at line 113 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER11 0x0BUL

REGION Number 11

Definition at line 114 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER12 0x0CUL

REGION Number 12

Definition at line 115 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER13 0x0DUL

REGION Number 13

Definition at line 116 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER14 0x0EUL

REGION Number 14

Definition at line 117 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER15 0x0FUL

REGION Number 15

Definition at line 118 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 0x02UL

REGION Number 2

Definition at line 104 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 0x03UL

REGION Number 3

Definition at line 105 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 0x04UL

REGION Number 4

Definition at line 106 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 0x05UL

REGION Number 5

Definition at line 107 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 0x06UL

REGION Number 6

Definition at line 108 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 0x07UL

REGION Number 7

Definition at line 109 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER8 0x08UL

REGION Number 8

Definition at line 111 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER9 0x09UL

REGION Number 9

Definition at line 112 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos)

Define Documentation

#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos)

128B Size of the MPU protection region

Definition at line 129 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos)

128KB Size of the MPU protection region

Definition at line 139 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos)

128MB Size of the MPU protection region

Definition at line 149 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos)

16KB Size of the MPU protection region

Definition at line 136 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos)

16MB Size of the MPU protection region

Definition at line 146 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos)

1GB Size of the MPU protection region

Definition at line 152 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos)

1KB Size of the MPU protection region

Definition at line 132 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos)

1MB Size of the MPU protection region

Definition at line 142 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos)

256B Size of the MPU protection region

Definition at line 130 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos)

256KB Size of the MPU protection region

Definition at line 140 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos)

256MB Size of the MPU protection region

Definition at line 150 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos)

2GB Size of the MPU protection region

Definition at line 153 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos)

2KB Size of the MPU protection region

Definition at line 133 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos)

2MB Size of the MPU protection region

Definition at line 143 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos)

32B Size of the MPU protection region

Definition at line 127 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos)

32KB Size of the MPU protection region

Definition at line 137 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos)

32MB Size of the MPU protection region

Definition at line 147 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos)

4GB Size of the MPU protection region

Definition at line 154 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos)

4KB Size of the MPU protection region

Definition at line 134 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos)

4MB Size of the MPU protection region

Definition at line 144 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos)

512B Size of the MPU protection region

Definition at line 131 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos)

512KB Size of the MPU protection region

Definition at line 141 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos)

512MB Size of the MPU protection region

Definition at line 151 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos)

64B Size of the MPU protection region

Definition at line 128 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos)

64KB Size of the MPU protection region

Definition at line 138 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos)

64MB Size of the MPU protection region

Definition at line 148 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos)

8KB Size of the MPU protection region

Definition at line 135 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos)

8MB Size of the MPU protection region

Definition at line 145 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos)

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos)

RW privileged & user (Full access)

Definition at line 165 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos)

No access

Definition at line 162 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos)

RO privileged (privileged read only)

Definition at line 166 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos)

RO privileged & user (read only)

Definition at line 167 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos)

RW privileged (privileged access only)

Definition at line 163 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos)

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 164 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos)

Define Documentation

#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos)

b000 for TEX bits

Definition at line 175 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos)

b001 for TEX bits

Definition at line 176 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos)

b010 for TEX bits

Definition at line 177 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos)

b100 for TEX bits

Definition at line 178 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 187 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL

Instruction fetches enabled

Definition at line 186 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL

Not Shareable memory attribute

Definition at line 196 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 195 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 204 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL

Not Cacheable memory attribute

Definition at line 205 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 213 of file stm32h7xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL

Not Bufferable memory attribute

Definition at line 214 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 285 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 275 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 265 of file stm32h7xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 240 of file stm32h7xx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 295 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 253 of file stm32h7xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

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STM32H7B3xQ HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 372 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 348 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 324 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 360 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 313 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 337 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 410 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 395 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetConstant ( void )

Get Constant number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Return values:
Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices

Definition at line 449 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 429 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4

Definition at line 459 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 469 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 439 of file stm32h7xx_ll_cortex.h.

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STM32H7B3xQ HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
  • LL_MPU_REGION_NUMBER8
  • LL_MPU_REGION_NUMBER9
  • LL_MPU_REGION_NUMBER10
  • LL_MPU_REGION_NUMBER11
  • LL_MPU_REGION_NUMBER12
  • LL_MPU_REGION_NUMBER13
  • LL_MPU_REGION_NUMBER14
  • LL_MPU_REGION_NUMBER15
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_32B or LL_MPU_REGION_SIZE_64B or LL_MPU_REGION_SIZE_128B or LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Note:
For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
Return values:
None

Definition at line 604 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 508 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
  • LL_MPU_REGION_NUMBER8
  • LL_MPU_REGION_NUMBER9
  • LL_MPU_REGION_NUMBER10
  • LL_MPU_REGION_NUMBER11
  • LL_MPU_REGION_NUMBER12
  • LL_MPU_REGION_NUMBER13
  • LL_MPU_REGION_NUMBER14
  • LL_MPU_REGION_NUMBER15
Note:
For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
Return values:
None

Definition at line 638 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 493 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
  • LL_MPU_REGION_NUMBER8
  • LL_MPU_REGION_NUMBER9
  • LL_MPU_REGION_NUMBER10
  • LL_MPU_REGION_NUMBER11
  • LL_MPU_REGION_NUMBER12
  • LL_MPU_REGION_NUMBER13
  • LL_MPU_REGION_NUMBER14
  • LL_MPU_REGION_NUMBER15
Note:
For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
Return values:
None

Definition at line 549 of file stm32h7xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 521 of file stm32h7xx_ll_cortex.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 56 of file stm32h7xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B 0x00000000U

32 bits Polynomial size

Definition at line 55 of file stm32h7xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 58 of file stm32h7xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 57 of file stm32h7xx_ll_crc.h.

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STM32H7B3xQ HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 67 of file stm32h7xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 68 of file stm32h7xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U

Input Data bit order not affected

Definition at line 66 of file stm32h7xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 69 of file stm32h7xx_ll_crc.h.

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STM32H7B3xQ HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 78 of file stm32h7xx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U

Output Data bit order not affected

Definition at line 77 of file stm32h7xx_ll_crc.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Default CRC generating polynomial value

Definition at line 88 of file stm32h7xx_ll_crc.h.

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STM32H7B3xQ HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 96 of file stm32h7xx_ll_crc.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 129 of file stm32h7xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, __VALUE__)

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 121 of file stm32h7xx_ll_crc.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 274 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 219 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( CRC_TypeDef * CRCx )

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 246 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 305 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 188 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 157 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 261 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 204 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 233 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 291 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 173 of file stm32h7xx_ll_crc.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 337 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 325 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 352 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 32-bit data register).

Definition at line 411 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 375 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 363 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 399 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 387 of file stm32h7xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 424 of file stm32h7xx_ll_crc.h.

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STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 63 of file stm32h7xx_ll_crc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CRC, LL_AHB1_GRP1_ReleaseReset(), LL_AHB4_GRP1_ForceReset(), and LL_AHB4_GRP1_ReleaseReset().

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STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
CRS Exported Constants

Flags defines which can be used with LL_CRS_ReadReg function. More...

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Detailed Description

Flags defines which can be used with LL_CRS_ReadReg function.

Define Documentation

#define LL_CRS_ISR_ERRF CRS_ISR_ERRF

Definition at line 58 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF

Definition at line 59 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR

Definition at line 60 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS

Definition at line 61 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF

Definition at line 56 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF

Definition at line 57 of file stm32h7xx_ll_crs.h.

#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Definition at line 62 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
CRS Exported Constants

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions. More...

Defines

#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Detailed Description

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Define Documentation

#define LL_CRS_CR_ERRIE CRS_CR_ERRIE

Definition at line 73 of file stm32h7xx_ll_crs.h.

#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Definition at line 74 of file stm32h7xx_ll_crs.h.

#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE

Definition at line 71 of file stm32h7xx_ll_crs.h.

#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE

Definition at line 72 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Synchronization Signal Divider

Defines
Synchronization Signal Divider
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Define Documentation

#define LL_CRS_SYNC_DIV_1 0x00000000U

Synchro Signal not divided (default)

Definition at line 82 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 89 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 86 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 83 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 87 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 84 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 88 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 85 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Synchronization Signal Source

Defines
Synchronization Signal Source
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U

Synchro Signal soucre GPIO

Definition at line 97 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 98 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 99 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 108 of file stm32h7xx_ll_crs.h.

#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U

Synchro Active on rising edge (default)

Definition at line 107 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Frequency Error Direction

Defines
Frequency Error Direction
CRS Exported Constants

Defines

#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Define Documentation

#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Downcounting direction, the actual frequency is below the target

Definition at line 117 of file stm32h7xx_ll_crs.h.

#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U

Upcounting direction, the actual frequency is above the target

Definition at line 116 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Default Values

Defines
Default Values
CRS Exported Constants

Defines

#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
Reset value of the HSI48 Calibration field.

Define Documentation

#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Reset value of Frequency error limit.

Definition at line 135 of file stm32h7xx_ll_crs.h.

#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

Reset value of the HSI48 Calibration field.

Note:
The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency.

Definition at line 143 of file stm32h7xx_ll_crs.h.

#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

Reset value of the RELOAD field.

Note:
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB)

Definition at line 130 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRS Exported Macros

Defines

#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.

Define Documentation

#define LL_CRS_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 176 of file stm32h7xx_ll_crs.h.

#define LL_CRS_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 168 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Exported_Macros_Calculate_Reload

Defines
Exported_Macros_Calculate_Reload
CRS Exported Macros

Defines

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
Reload value (in Hz)

Definition at line 196 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.

Function Documentation

__STATIC_INLINE void LL_CRS_ConfigSynchronization | ( | uint32_t | HSI48CalibrationValue,
 |  | uint32_t | ErrorLimitValue,
 |  | uint32_t | ReloadValue,
 |  | uint32_t | Settings
 | ) |  |

Configure CRS for the synchronization.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_ConfigSynchronization
CFGR RELOAD LL_CRS_ConfigSynchronization
CFGR FELIM LL_CRS_ConfigSynchronization
CFGR SYNCDIV LL_CRS_ConfigSynchronization
CFGR SYNCSRC LL_CRS_ConfigSynchronization
CFGR SYNCPOL LL_CRS_ConfigSynchronization
Parameters:
HSI48CalibrationValue | a number between Min_Data = 0 and Max_Data = 63
ErrorLimitValue | a number between Min_Data = 0 and Max_Data = 0xFFFF
ReloadValue | a number between Min_Data = 0 and Max_Data = 255
Settings This parameter can be a combination of the following values:
  • LL_CRS_SYNC_DIV_1 or LL_CRS_SYNC_DIV_2 or LL_CRS_SYNC_DIV_4 or LL_CRS_SYNC_DIV_8 or LL_CRS_SYNC_DIV_16 or LL_CRS_SYNC_DIV_32 or LL_CRS_SYNC_DIV_64 or LL_CRS_SYNC_DIV_128
  • LL_CRS_SYNC_SOURCE_GPIO or LL_CRS_SYNC_SOURCE_LSE or LL_CRS_SYNC_SOURCE_USB
  • LL_CRS_SYNC_POLARITY_RISING or LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 451 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableAutoTrimming ( void )

Disable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
Return values:
None

Definition at line 261 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter ( void )

Disable Frequency error counter.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_DisableFreqErrorCounter
Return values:
None

Definition at line 231 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableAutoTrimming ( void )

Enable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
Return values:
None

Definition at line 251 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter ( void )

Enable Frequency error counter.

Note:
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
Reference Manual to LL API cross reference:
CR CEN LL_CRS_EnableFreqErrorCounter
Return values:
None

Definition at line 221 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit ( void )

Get frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_GetFreqErrorLimit
Return values:
A number between Min_Data = 0 and Max_Data = 255

Definition at line 339 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming ( void )

Get HSI48 oscillator smooth trimming.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_GetHSI48SmoothTrimming
Return values:
a number between Min_Data = 0 and Max_Data = 127

Definition at line 294 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter ( void )

Get counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_GetReloadCounter
Return values:
a number between Min_Data = 0 and Max_Data = 0xFFFF

Definition at line 317 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider ( void )

Get division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_GetSyncDivider
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128

Definition at line 376 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity ( void )

Get input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_GetSyncPolarity
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING

Definition at line 428 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource ( void )

Get SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_GetSyncSignalSource
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB

Definition at line 403 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming ( void )

Check if Automatic trimming is enabled or not.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
Return values:
State of bit (1 or 0).

Definition at line 271 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter ( void )

Check if Frequency error counter is enabled or not.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_IsEnabledFreqErrorCounter
Return values:
State of bit (1 or 0).

Definition at line 241 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetFreqErrorLimit ( uint32_t Value )

Set frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_SetFreqErrorLimit
Parameters:
Value a number between Min_Data = 0 and Max_Data = 255
Note:
Default value can be set thanks to LL_CRS_ERRORLIMIT_DEFAULT
Return values:
None

Definition at line 329 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming ( uint32_t Value )

Set HSI48 oscillator smooth trimming.

Note:
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
Reference Manual to LL API cross reference:
CR TRIM LL_CRS_SetHSI48SmoothTrimming
Parameters:
Value a number between Min_Data = 0 and Max_Data = 127
Note:
Default value can be set thanks to LL_CRS_HSI48CALIBRATION_DEFAULT
Return values:
None

Definition at line 284 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetReloadCounter ( uint32_t Value )

Set counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_SetReloadCounter
Parameters:
Value a number between Min_Data = 0 and Max_Data = 0xFFFF
Note:
Default value can be set thanks to LL_CRS_RELOADVALUE_DEFAULT Otherwise it can be calculated in using macro __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
Return values:
None

Definition at line 307 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncDivider ( uint32_t Divider )

Set division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_SetSyncDivider
Parameters:
Divider This parameter can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128
Return values:
None

Definition at line 358 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncPolarity ( uint32_t Polarity )

Set input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_SetSyncPolarity
Parameters:
Polarity This parameter can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 416 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncSignalSource ( uint32_t Source )

Set SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_SetSyncSignalSource
Parameters:
Source This parameter can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB
Return values:
None

Definition at line 390 of file stm32h7xx_ll_crs.h.

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STM32H7B3xQ HAL User Manual: CRS_Management

Functions
CRS_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.

Function Documentation

__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC ( void )

Generate software SYNC event.

Reference Manual to LL API cross reference:
CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
Return values:
None

Definition at line 472 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture ( void )

Get the frequency error counter value latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FECAP LL_CRS_GetFreqErrorCapture
Return values:
A number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 495 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection ( void )

Get the frequency error direction latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FEDIR LL_CRS_GetFreqErrorDirection
Return values:
Returned value can be one of the following values:
  • LL_CRS_FREQ_ERROR_DIR_UP
  • LL_CRS_FREQ_ERROR_DIR_DOWN

Definition at line 485 of file stm32h7xx_ll_crs.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
CRS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.

Function Documentation

__STATIC_INLINE void LL_CRS_ClearFlag_ERR ( void )

Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.

Reference Manual to LL API cross reference:
ICR ERRC LL_CRS_ClearFlag_ERR
Return values:
None

Definition at line 604 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC ( void )

Clear Expected SYNC flag.

Reference Manual to LL API cross reference:
ICR ESYNCC LL_CRS_ClearFlag_ESYNC
Return values:
None

Definition at line 614 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK ( void )

Clear the SYNC event OK flag.

Reference Manual to LL API cross reference:
ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
Return values:
None

Definition at line 583 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN ( void )

Clear the SYNC warning flag.

Reference Manual to LL API cross reference:
ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
Return values:
None

Definition at line 593 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR ( void )

Check if Synchronization or trimming error signal occurred or not.

Reference Manual to LL API cross reference:
ISR ERRF LL_CRS_IsActiveFlag_ERR
Return values:
State of bit (1 or 0).

Definition at line 533 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC ( void )

Check if Expected SYNC signal occurred or not.

Reference Manual to LL API cross reference:
ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 543 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR ( void )

Check if SYNC error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
Return values:
State of bit (1 or 0).

Definition at line 553 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS ( void )

Check if SYNC missed error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
Return values:
State of bit (1 or 0).

Definition at line 563 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK ( void )

Check if SYNC event OK signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 513 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN ( void )

Check if SYNC warning signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 523 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF ( void )

Check if Trimming overflow or underflow occurred or not.

Reference Manual to LL API cross reference:
ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
Return values:
State of bit (1 or 0).

Definition at line 573 of file stm32h7xx_ll_crs.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_CRS_DisableIT_ERR ( void )

Disable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_DisableIT_ERR
Return values:
None

Definition at line 702 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_ESYNC ( void )

Disable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_DisableIT_ESYNC
Return values:
None

Definition at line 732 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK ( void )

Disable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
Return values:
None

Definition at line 642 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN ( void )

Disable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
Return values:
None

Definition at line 672 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ERR ( void )

Enable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_EnableIT_ERR
Return values:
None

Definition at line 692 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ESYNC ( void )

Enable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_EnableIT_ESYNC
Return values:
None

Definition at line 722 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK ( void )

Enable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
Return values:
None

Definition at line 632 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN ( void )

Enable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
Return values:
None

Definition at line 662 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR ( void )

Check if Synchronization or trimming error interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_IsEnabledIT_ERR
Return values:
State of bit (1 or 0).

Definition at line 712 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC ( void )

Check if Expected SYNC interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 742 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK ( void )

Check if SYNC event OK interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 652 of file stm32h7xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN ( void )

Check if SYNC warning interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 682 of file stm32h7xx_ll_crs.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRS Exported Functions

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_CRS_DeInit ( void )

De-Initializes CRS peripheral registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRS registers are de-initialized
  • ERROR: not applicable

Definition at line 56 of file stm32h7xx_ll_crs.c.

References LL_APB1_GRP1_ForceReset(), and LL_APB1_GRP1_ReleaseReset().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Define Documentation

#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */

Definition at line 56 of file stm32h7xx_ll_dac.h.

#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */

Definition at line 57 of file stm32h7xx_ll_dac.h.

#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

Definition at line 58 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConfigOutput(), LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_Enable(), LL_DAC_EnableDMAReq(), LL_DAC_EnableTrigger(), LL_DAC_GetMode(), LL_DAC_GetOutputBuffer(), LL_DAC_GetOutputConnection(), LL_DAC_GetOutputMode(), LL_DAC_GetSampleAndHoldHoldTime(), LL_DAC_GetSampleAndHoldRefreshTime(), LL_DAC_GetTriggerSource(), LL_DAC_GetTrimmingValue(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetMode(), LL_DAC_SetOutputBuffer(), LL_DAC_SetOutputConnection(), LL_DAC_SetOutputMode(), LL_DAC_SetSampleAndHoldHoldTime(), LL_DAC_SetSampleAndHoldRefreshTime(), LL_DAC_SetTriggerSource(), LL_DAC_SetTrimmingValue(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().

#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos

Definition at line 95 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12LeftAligned().

#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos

Definition at line 94 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12RightAligned().

#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos

Definition at line 96 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData8RightAligned().

#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Definition at line 99 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 65 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 68 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 88 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned().

#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL

Definition at line 71 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */

Definition at line 64 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */

Definition at line 67 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */

Definition at line 87 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12RightAligned().

#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL

Definition at line 70 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 66 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 69 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 89 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertData8RightAligned().

#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL

Definition at line 72 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */

Definition at line 83 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), and LL_DAC_DMA_GetRegAddr().

#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

Definition at line 73 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */

Definition at line 75 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */

Definition at line 76 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */

Definition at line 90 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

Definition at line 77 of file stm32h7xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */

Definition at line 84 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */

Definition at line 78 of file stm32h7xx_ll_dac.h.

#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */

Definition at line 79 of file stm32h7xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */

Definition at line 91 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldSampleTime().

#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)

Definition at line 80 of file stm32h7xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */

Definition at line 85 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldSampleTime().

#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */

Definition at line 60 of file stm32h7xx_ll_dac.h.

#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */

Definition at line 61 of file stm32h7xx_ll_dac.h.

#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)

Definition at line 62 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_TrigSWConversion().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __DAC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 119 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_DMA_GetRegAddr(), LL_DAC_GetSampleAndHoldSampleTime(), LL_DAC_RetrieveOutputData(), and LL_DAC_SetSampleAndHoldSampleTime().

#define IS_LL_DAC_CHANNEL ( __DAC_CHANNEL__ )
Value:
(                                                                            \
      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
  )

Definition at line 49 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_BUFFER ( __OUTPUT_BUFFER__ )
Value:
(   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
  )

Definition at line 144 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_CONNECTION ( __OUTPUT_CONNECTION__ )
Value:
(   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
   || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
  )

Definition at line 149 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_MODE ( __OUTPUT_MODE__ )
Value:
(   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
   || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
  )

Definition at line 154 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE ( __TRIGGER_SOURCE__ )
Value:
(   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_OUT)                     \
  )

Definition at line 73 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG | ( | __WAVE_AUTO_GENERATION_MODE__,
 |  | __WAVE_AUTO_GENERATION_CONFIG__
 | ) |
Value:
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
    && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                            \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                         \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                        \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                       \
    )                                                                                                     \
  ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                            \
    && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                              \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                              \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                              \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                             \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                             \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                             \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                            \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                            \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                            \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                           \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                           \
       || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                          \
    )                                                                                                     \
  )

Definition at line 113 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_MODE ( __WAVE_AUTO_GENERATION_MODE__ )
Value:
(   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
  )

Definition at line 107 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_Init().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_DAC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DAC_InitTypeDef Struct Reference
DAC Exported Init structure

Structure definition of some features of DAC instance. More...

#include <stm32h7xx_ll_dac.h>

Data Fields

uint32_t | TriggerSource
uint32_t | WaveAutoGeneration
uint32_t | WaveAutoGenerationConfig
uint32_t | OutputBuffer
uint32_t | OutputConnection
uint32_t | OutputMode

Detailed Description

Structure definition of some features of DAC instance.

Definition at line 136 of file stm32h7xx_ll_dac.h.

Field Documentation

uint32_t LL_DAC_InitTypeDef::OutputBuffer

Set the output buffer for the selected DAC channel. This parameter can be a value of DAC channel output buffer

This feature can be modified afterwards using unitary function LL_DAC_SetOutputBuffer().

Definition at line 156 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputConnection

Set the output connection for the selected DAC channel. This parameter can be a value of DAC channel output connection

This feature can be modified afterwards using unitary function LL_DAC_SetOutputConnection().

Definition at line 161 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputMode

Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of DAC channel output mode

This feature can be modified afterwards using unitary function LL_DAC_SetOutputMode().

Definition at line 166 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource

Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource().

Definition at line 138 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGeneration

Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of DAC waveform automatic generation mode

This feature can be modified afterwards using unitary function LL_DAC_SetWaveAutoGeneration().

Definition at line 143 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGenerationConfig

Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of DAC wave generation - Noise LFSR unmask bits If waveform automatic generation mode is set to triangle, this parameter can be a value of DAC wave generation - Triangle amplitude

Note:
If waveform automatic generation mode is disabled, this parameter is discarded.

This feature can be modified afterwards using unitary function LL_DAC_SetWaveNoiseLFSR(), LL_DAC_SetWaveTriangleAmplitude() depending on the wave automatic generation selected.

Definition at line 148 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_dac.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC flags

Defines
DAC flags
DAC Exported Constants

Flags defines which can be used with LL_DAC_ReadReg function. More...

Defines

#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

Detailed Description

Flags defines which can be used with LL_DAC_ReadReg function.

Define Documentation

#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)

DAC channel 1 flag busy writing sample time

Definition at line 189 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST1().

#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

DAC channel 2 flag busy writing sample time

Definition at line 194 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST2().

#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)

DAC channel 1 flag offset calibration status

Definition at line 188 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)

DAC channel 2 flag offset calibration status

Definition at line 193 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL2().

#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

DAC channel 1 flag DMA underrun

Definition at line 187 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR1(), and LL_DAC_IsActiveFlag_DMAUDR1().

#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

DAC channel 2 flag DMA underrun

Definition at line 192 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR2(), and LL_DAC_IsActiveFlag_DMAUDR2().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC interruptions

Defines
DAC interruptions
DAC Exported Constants

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions. More...

Defines

#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

Detailed Description

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

Define Documentation

#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)

DAC channel 1 interruption DMA underrun

Definition at line 203 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR1(), LL_DAC_EnableIT_DMAUDR1(), and LL_DAC_IsEnabledIT_DMAUDR1().

#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

DAC channel 2 interruption DMA underrun

Definition at line 204 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR2(), LL_DAC_EnableIT_DMAUDR2(), and LL_DAC_IsEnabledIT_DMAUDR2().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC channels

Defines
DAC channels
DAC Exported Constants

Defines

#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

Define Documentation

#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)

DAC channel 1

Definition at line 212 of file stm32h7xx_ll_dac.h.

#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

DAC channel 2

Definition at line 213 of file stm32h7xx_ll_dac.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC operating mode

Defines
DAC operating mode
DAC Exported Constants

Defines

#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

Define Documentation

#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

DAC channel in mode calibration

Definition at line 222 of file stm32h7xx_ll_dac.h.

#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL

DAC channel in mode normal operation

Definition at line 221 of file stm32h7xx_ll_dac.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC trigger source

Defines
DAC trigger source
DAC Exported Constants

Defines

#define | LL_DAC_TRIG_SOFTWARE 0x00000000U
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

Define Documentation

#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: external interrupt line 9.

Definition at line 245 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: LPTIM1 TRGO.

Definition at line 243 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )

DAC channel conversion trigger from external peripheral: LPTIM2 TRGO.

Definition at line 244 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external peripheral: LPTIM3 TRGO.

Definition at line 253 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )

DAC channel conversion trigger from external peripheral: TIM15 TRGO.

Definition at line 238 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM1 TRGO.

Definition at line 231 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external peripheral: TIM2 TRGO.

Definition at line 232 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM4 TRGO.

Definition at line 233 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 )

DAC channel conversion trigger from external peripheral: TIM5 TRGO.

Definition at line 234 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM6 TRGO.

Definition at line 235 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external peripheral: TIM7 TRGO.

Definition at line 236 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM8 TRGO.

Definition at line 237 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIG_SOFTWARE 0x00000000U

DAC channel conversion trigger internal (SW start)

Definition at line 230 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC waveform automatic generation mode

Defines
DAC waveform automatic generation mode
DAC Exported Constants

Defines

#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )

Define Documentation

#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated noise waveform.

Definition at line 263 of file stm32h7xx_ll_dac.h.

#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL

DAC channel wave auto generation mode disabled.

Definition at line 262 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )

DAC channel wave auto generation mode enabled, set generated triangle waveform.

Definition at line 264 of file stm32h7xx_ll_dac.h.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DAC wave generation - Noise LFSR unmask bits

Defines
DAC wave generation - Noise LFSR unmask bits
DAC Exported Constants

Defines

#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL

Noise wave generation, unmask LFSR bit0, for the selected DAC channel

Definition at line 272 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel

Definition at line 282 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel

Definition at line 283 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel

Definition at line 273 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel

Definition at line 274 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel

Definition at line 275 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel

Definition at line 276 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel

Definition at line 277 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel

Definition at line 278 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel

Definition at line 279 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel

Definition at line 280 of file stm32h7xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel

Definition at line 281 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC wave generation - Triangle amplitude

Defines
DAC wave generation - Triangle amplitude
DAC Exported Constants

Defines

#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL

Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel

Definition at line 291 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel

Definition at line 300 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel

Definition at line 297 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel

Definition at line 294 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel

Definition at line 301 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel

Definition at line 298 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel

Definition at line 292 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel

Definition at line 295 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel

Definition at line 302 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )

Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel

Definition at line 299 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel

Definition at line 296 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel

Definition at line 293 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC channel output mode

Defines
DAC channel output mode
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

Define Documentation

#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL

The selected DAC channel output is on mode normal.

Definition at line 310 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function LL_DAC_ConfigOutput() or LL_DAC_SetOutputMode().

Definition at line 311 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC channel output buffer

Defines
DAC channel output buffer
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption

Definition at line 320 of file stm32h7xx_ll_dac.h.

#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL

The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption

Definition at line 319 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

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STM32H7B3xQ HAL User Manual: DAC channel output connection

Defines
DAC channel output connection
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

Define Documentation

#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL

The selected DAC channel output is connected to external pin

Definition at line 328 of file stm32h7xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function LL_DAC_SetOutputConnection().

Definition at line 329 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC literals legacy naming

Defines
DAC literals legacy naming
DAC Exported Constants

Defines

#define | LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
#define | LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
#define | LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
#define | LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
#define | LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
#define | LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
#define | LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
#define | LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
#define | LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
#define | LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
#define | LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
#define | LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)

Define Documentation

#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)

Definition at line 349 of file stm32h7xx_ll_dac.h.

#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)

Definition at line 350 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)

Definition at line 343 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)

Definition at line 337 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)

Definition at line 338 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)

Definition at line 339 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)

Definition at line 340 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)

Definition at line 341 of file stm32h7xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)

Definition at line 342 of file stm32h7xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)

Definition at line 346 of file stm32h7xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)

Definition at line 345 of file stm32h7xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)

Definition at line 347 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC channel output resolution

Defines
DAC channel output resolution
DAC Exported Constants

Defines

#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL

Define Documentation

#define LL_DAC_RESOLUTION_12B 0x00000000UL

DAC channel resolution 12 bits

Definition at line 357 of file stm32h7xx_ll_dac.h.

#define LL_DAC_RESOLUTION_8B 0x00000002UL

DAC channel resolution 8 bits

Definition at line 358 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC registers compliant with specific purpose

Defines
DAC registers compliant with specific purpose
DAC Exported Constants

Defines

#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

Define Documentation

#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits left aligned

Definition at line 370 of file stm32h7xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits right aligned

Definition at line 369 of file stm32h7xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 8 bits right aligned

Definition at line 371 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: Definitions of DAC hardware constraints delays

Defines
Definitions of DAC hardware constraints delays
DAC Exported Constants

Defines

#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Detailed Description

Note:
Only DAC peripheral HW delays are defined in DAC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 396 of file stm32h7xx_ll_dac.h.

#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Delay for DAC channel voltage settling time

Definition at line 409 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: Common write and read registers macros

Defines
Common write and read registers macros
DAC Exported Macros

Defines

#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.

Define Documentation

#define LL_DAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 443 of file stm32h7xx_ll_dac.h.

#define LL_DAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 435 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: DAC helper macro

Defines
DAC helper macro
DAC Exported Macros

Defines

#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Define Documentation

#define __LL_DAC_CALC_VOLTAGE_TO_DATA | ( | __VREFANALOG_VOLTAGE__,
 |  | __DAC_VOLTAGE__,
 |  | __DAC_RESOLUTION__
 | ) |
Value:
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
   / (__VREFANALOG_VOLTAGE__)                                                  \
  )

Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Note:
This helper macro is intended to provide input data in voltage rather than digital value, to be used with LL DAC functions such as LL_DAC_ConvertData12RightAligned().
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__DAC_VOLTAGE__ | Voltage to be generated by DAC channel (unit: mVolt).
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
DAC conversion data (unit: digital value)

Definition at line 531 of file stm32h7xx_ll_dac.h.

#define __LL_DAC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.

Example: __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) will return decimal number "1".

Note:
The input can be a value from functions where a channel number is returned.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
1...2

Definition at line 466 of file stm32h7xx_ll_dac.h.

#define __LL_DAC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) == 1UL)                                                   \
    ? (                                                                        \
       LL_DAC_CHANNEL_1                                                        \
      )                                                                        \
      :                                                                        \
      (((__DECIMAL_NB__) == 2UL)                                               \
        ? (                                                                    \
           LL_DAC_CHANNEL_2                                                    \
          )                                                                    \
          :                                                                    \
          (                                                                    \
           0UL                                                                 \
          )                                                                    \
      )                                                                        \
  )

Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.

Example: __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) will return a data equivalent to "LL_DAC_CHANNEL_1".

Note:
If the input parameter does not correspond to a DAC channel, this macro returns value '0'.
Parameters:
__DECIMAL_NB__ 1...2
Return values:
Returned value can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2

Definition at line 482 of file stm32h7xx_ll_dac.h.

#define __LL_DAC_DIGITAL_SCALE ( __DAC_RESOLUTION__ ) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))

Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.

Note:
DAC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 510 of file stm32h7xx_ll_dac.h.

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STM32H7B3xQ HAL User Manual: Configuration of DAC channels

Functions
Configuration of DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.

Function Documentation

__STATIC_INLINE void LL_DAC_ConfigOutput | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode,
 |  | uint32_t | OutputBuffer,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output for the selected DAC channel.

Note:
This function set several features:
  • mode normal or sample-and-hold
  • buffer
  • connection to GPIO or internal path. These features can also be set individually using dedicated functions:
  • LL_DAC_SetOutputBuffer()
  • LL_DAC_SetOutputMode()
  • LL_DAC_SetOutputConnection()
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_ConfigOutput
CR MODE2 LL_DAC_ConfigOutput
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 950 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_GetMode
CR CEN2 LL_DAC_GetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION

Definition at line 589 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output buffer state for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputBuffer
CR MODE2 LL_DAC_GetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE

Definition at line 1040 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output connection for the selected DAC channel.

Note:
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputConnection
CR MODE2 LL_DAC_GetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL

Definition at line 1099 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output mode normal or sample-and-hold for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputMode
CR MODE2 LL_DAC_GetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

Definition at line 997 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1179 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1216 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: sample time.

Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1142 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_GetTriggerSource
CR TSEL2 LL_DAC_GetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_TIM5_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM8_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
  • LL_DAC_TRIG_EXT_LPTIM1_OUT
  • LL_DAC_TRIG_EXT_LPTIM2_OUT
  • LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM23_TRGO (3)
  • LL_DAC_TRIG_EXT_TIM24_TRGO (4)
(1) On this STM32 serie, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list) (2) On this STM32 serie, parameter only available on DAC2. (3) On this STM32 serie, parameter not available on all devices. Only available if TIM23 feature is supported (refer to device datasheet for supported features list) (4) On this STM32 serie, parameter not available on all devices. Only available if TIM24 feature is supported (refer to device datasheet for supported features list)

Definition at line 723 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_GetTrimmingValue
CCR OTRIM2 LL_DAC_GetTrimmingValue
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 628 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_GetWaveAutoGeneration
CR WAVE2 LL_DAC_GetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

Definition at line 766 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveNoiseLFSR
CR MAMP2 LL_DAC_GetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

Definition at line 832 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095

Definition at line 899 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | ChannelMode
 | ) |  |

Set the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_SetMode
CR CEN2 LL_DAC_SetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
ChannelMode This parameter can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION
Return values:
None

Definition at line 569 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputBuffer
 | ) |  |

Set the output buffer for the selected DAC channel.

Note:
On this STM32 serie, when buffer is enabled, its offset can be trimmed: factory calibration default values can be replaced by user trimming values, using function LL_DAC_SetTrimmingValue().
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputBuffer
CR MODE2 LL_DAC_SetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
Return values:
None

Definition at line 1021 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output connection for the selected DAC channel.

Note:
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputConnection
CR MODE2 LL_DAC_SetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 1070 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode
 | ) |  |

Set the output mode normal or sample-and-hold for the selected DAC channel.

Note:
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputMode
CR MODE2 LL_DAC_SetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
Return values:
None

Definition at line 978 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | HoldTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
HoldTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1161 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | RefreshTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
RefreshTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1198 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | SampleTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: sample time.

Note:
Sample time must be set when DAC channel is disabled or during DAC operation when DAC channel flag BWSTx is reset, otherwise the setting is ignored. Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
SampleTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1122 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_SetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
To set conversion trigger source, DAC channel must be disabled. Otherwise, the setting is discarded.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_SetTriggerSource
CR TSEL2 LL_DAC_SetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_TIM5_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM8_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
  • LL_DAC_TRIG_EXT_LPTIM1_OUT
  • LL_DAC_TRIG_EXT_LPTIM2_OUT
  • LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM23_TRGO (3)
  • LL_DAC_TRIG_EXT_TIM24_TRGO (4)
(1) On this STM32 serie, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list) (2) On this STM32 serie, parameter only available on DAC2. (3) On this STM32 serie, parameter not available on all devices. Only available if TIM23 feature is supported (refer to device datasheet for supported features list) (4) On this STM32 serie, parameter not available on all devices. Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
Return values:
None

Definition at line 677 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_SetTrimmingValue
CCR OTRIM2 LL_DAC_SetTrimmingValue
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TrimmingValue | Value between Min_Data=0x00 and Max_Data=0x1F
Return values:
None

Definition at line 609 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveAutoGeneration
 | ) |  |

Set the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_SetWaveAutoGeneration
CR WAVE2 LL_DAC_SetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
WaveAutoGeneration This parameter can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
Return values:
None

Definition at line 745 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | NoiseLFSRMask
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveNoiseLFSR
CR MAMP2 LL_DAC_SetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
NoiseLFSRMask This parameter can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
Return values:
None

Definition at line 802 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriangleAmplitude
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriangleAmplitude This parameter can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095
Return values:
None

Definition at line 868 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Management

Functions
DMA Management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_DisableDMAReq
CR DMAEN2 LL_DAC_DisableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1261 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Note:
These DAC registers are data holding registers: when DAC conversion is requested, DAC generates a DMA transfer request to have data available in DAC data holding registers.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, (uint32_t)&< array or variable >, LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Register This parameter can be one of the following values:
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Return values:
DAC register address

Definition at line 1316 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_EnableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_EnableDMAReq
CR DMAEN2 LL_DAC_EnableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1243 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA transfer request state of the selected channel.

(0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_IsDMAReqEnabled
CR DMAEN2 LL_DAC_IsDMAReqEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1278 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on DAC channels

Functions
Operation on DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1504 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1482 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1526 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned
DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1566 of file stm32h7xx_ll_dac.h.

References DAC_DHR12LD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned
DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1547 of file stm32h7xx_ll_dac.h.

References DAC_DHR12RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned
DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x00 and Max_Data=0xFF
DataChannel2 | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1588 of file stm32h7xx_ll_dac.h.

References DAC_DHR8RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_Disable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Disable
CR EN2 LL_DAC_Disable
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1360 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC trigger of the selected channel.

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_DisableTrigger
CR TEN2 LL_DAC_DisableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1418 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_Enable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Enable
CR EN2 LL_DAC_Enable
Note:
After enable from off state, DAC channel requires a delay for output voltage to reach accuracy +/- 1 LSB. Refer to device datasheet, parameter "tWAKEUP".
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1344 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_EnableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC trigger of the selected channel.

Note:
- If DAC trigger is disabled, DAC conversion is performed automatically once the data holding register is updated, using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...
  • If DAC trigger is enabled, DAC conversion is performed only when a hardware of software trigger event is occurring. Select trigger source using function LL_DAC_SetTriggerSource().
Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_EnableTrigger
CR TEN2 LL_DAC_EnableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1402 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC enable state of the selected channel.

(0: DAC channel is disabled, 1: DAC channel is enabled)

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_IsEnabled
CR EN2 LL_DAC_IsEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1377 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_Init().

__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC trigger state of the selected channel.

(0: DAC trigger is disabled, 1: DAC trigger is enabled)

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_IsTriggerEnabled
CR TEN2 LL_DAC_IsTriggerEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1435 of file stm32h7xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Retrieve output data currently generated for the selected DAC channel.

Note:
Whatever alignment and resolution settings (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...), output data format is 12 bits right aligned (LSB aligned on bit 0).
Reference Manual to LL API cross reference:
DOR1 DACC1DOR LL_DAC_RetrieveOutputData
DOR2 DACC2DOR LL_DAC_RetrieveOutputData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1611 of file stm32h7xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DORX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DORX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_TrigSWConversion | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by software for the selected DAC channel.

Note:
Preliminarily, DAC trigger must be set to software trigger using function LL_DAC_Init() LL_DAC_SetTriggerSource() with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1463 of file stm32h7xx_ll_dac.h.

References DAC_SWTR_CHX_MASK.

Generated on Tue Nov 12 2019 18:50:29 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG Management

Functions
FLAG Management
DAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1703 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1715 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR BWST1 LL_DAC_IsActiveFlag_BWST1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1655 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_BWST1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR BWST2 LL_DAC_IsActiveFlag_BWST2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_BWST2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_CAL1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1643 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_CAL2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1679 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1691 of file stm32h7xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT management

Functions
IT management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1759 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1771 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1735 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1747 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1783 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1795 of file stm32h7xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DAC_DeInit ( DAC_TypeDef * DACx )

De-initialize registers of the selected DAC instance to their default reset values.

Parameters:
DACx DAC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are de-initialized
  • ERROR: not applicable

Definition at line 183 of file stm32h7xx_ll_dac.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_DAC12, LL_APB1_GRP1_ReleaseReset(), LL_APB4_GRP1_ForceReset(), LL_APB4_GRP1_PERIPH_DAC2, and LL_APB4_GRP1_ReleaseReset().

ErrorStatus LL_DAC_Init | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | LL_DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initialize some features of DAC channel.

Note:
LL_DAC_Init() aims to ease basic configuration of a DAC channel. Leaving it ready to be enabled and output: a level by calling one of LL_DAC_ConvertData12RightAligned LL_DAC_ConvertData12LeftAligned LL_DAC_ConvertData8RightAligned or one of the supported autogenerated wave.
This function allows configuration of:
  • Output mode
  • Trigger
  • Wave generation
The setting of these parameters by function LL_DAC_Init() is conditioned to DAC state: DAC channel must be disabled.
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
DAC_InitStruct | Pointer to a LL_DAC_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are initialized
  • ERROR: DAC registers are not initialized

Definition at line 236 of file stm32h7xx_ll_dac.c.

References assert_param, DAC_CR_CHX_BITOFFSET_MASK, IS_LL_DAC_CHANNEL, IS_LL_DAC_OUTPUT_BUFFER, IS_LL_DAC_OUTPUT_CONNECTION, IS_LL_DAC_OUTPUT_MODE, IS_LL_DAC_TRIGGER_SOURCE, IS_LL_DAC_WAVE_AUTO_GENER_CONFIG, IS_LL_DAC_WAVE_AUTO_GENER_MODE, LL_DAC_IsEnabled(), LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

void LL_DAC_StructInit ( LL_DAC_InitTypeDef * DAC_InitStruct )

Set each LL_DAC_InitTypeDef field to default value.

Parameters:
DAC_InitStruct pointer to a LL_DAC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 316 of file stm32h7xx_ll_dac.c.

References LL_DAC_NOISE_LFSR_UNMASK_BIT0, LL_DAC_OUTPUT_BUFFER_ENABLE, LL_DAC_OUTPUT_CONNECT_GPIO, LL_DAC_OUTPUT_MODE_NORMAL, LL_DAC_TRIG_SOFTWARE, LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t LL_DMA_STR_OFFSET_TAB []

Variable Documentation

const uint8_t LL_DMA_STR_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
}

Definition at line 48 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32h7xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority
uint32_t | FIFOMode
uint32_t | FIFOThreshold
uint32_t | MemBurst
uint32_t | PeriphBurst

Detailed Description

Definition at line 82 of file stm32h7xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DIRECTION

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 94 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::FIFOMode

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of DMA_LL_FIFOMODE

Note:
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream

This feature can be modified afterwards using unitary functions LL_DMA_EnableFifoMode() or LL_DMA_EnableFifoMode() .

Definition at line 148 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::FIFOThreshold

Specifies the FIFO threshold level. This parameter can be a value of FIFOTHRESHOLD

This feature can be modified afterwards using unitary function LL_DMA_SetFIFOThreshold().

Definition at line 155 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemBurst

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of MBURST

Note:
The burst mode is possible only if the address Increment mode is enabled.

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryBurstxfer().

Definition at line 160 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 89 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of MDATAALIGN

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 125 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of MEMORY

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 113 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of MODE

Note:
The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Stream

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 100 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 131 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphBurst

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of PBURST

Note:
The burst mode is possible only if the address Increment mode is enabled.

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphBurstxfer().

Definition at line 168 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 84 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of PDATAALIGN

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 119 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of PERIPH

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 107 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of DMAMUX_LL_EC_REQUEST

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphRequest().

Definition at line 138 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of PRIORITY

This feature can be modified afterwards using unitary function LL_DMA_SetStreamPriorityLevel().

Definition at line 143 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_dma.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: STREAM

Defines
STREAM
DMA Exported Constants

Defines

#define | LL_DMA_STREAM_0 0x00000000U
#define | LL_DMA_STREAM_1 0x00000001U
#define | LL_DMA_STREAM_2 0x00000002U
#define | LL_DMA_STREAM_3 0x00000003U
#define | LL_DMA_STREAM_4 0x00000004U
#define | LL_DMA_STREAM_5 0x00000005U
#define | LL_DMA_STREAM_6 0x00000006U
#define | LL_DMA_STREAM_7 0x00000007U
#define | LL_DMA_STREAM_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_STREAM_0 0x00000000U

Definition at line 189 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_1 0x00000001U

Definition at line 190 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_2 0x00000002U

Definition at line 191 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_3 0x00000003U

Definition at line 192 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_4 0x00000004U

Definition at line 193 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_5 0x00000005U

Definition at line 194 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_6 0x00000006U

Definition at line 195 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_7 0x00000007U

Definition at line 196 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_STREAM_ALL 0xFFFF0000U

Definition at line 197 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

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STM32H7B3xQ HAL User Manual: DIRECTION

Defines
DIRECTION
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1

Memory to memory direction

Definition at line 208 of file stm32h7xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0

Memory to peripheral direction

Definition at line 207 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 206 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MODE

Defines
MODE
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC
#define | LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC

Circular Mode

Definition at line 217 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 216 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL

Peripheral flow control mode

Definition at line 218 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PERIPH

Defines
PERIPH
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC

Peripheral increment mode Enable

Definition at line 236 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 235 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MEMORY

Defines
MEMORY
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC

Memory increment mode Enable

Definition at line 245 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 244 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32H7B3xQ HAL User Manual: PDATAALIGN

Defines
PDATAALIGN
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 253 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 254 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 255 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: MDATAALIGN

Defines
MDATAALIGN
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 263 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 264 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1

Memory data alignment : Word

Definition at line 265 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: OFFSETSIZE

Defines
OFFSETSIZE
DMA Exported Constants

Defines

#define | LL_DMA_OFFSETSIZE_PSIZE 0x00000000U
#define | LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS

Define Documentation

#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS

Peripheral increment offset size is fixed to 4 (32-bit alignment)

Definition at line 274 of file stm32h7xx_ll_dma.h.

#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U

Peripheral increment offset size is linked to the PSIZE

Definition at line 273 of file stm32h7xx_ll_dma.h.

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STM32H7B3xQ HAL User Manual: PRIORITY

Defines
PRIORITY
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1

Priority level : High

Definition at line 284 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 282 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0

Priority level : Medium

Definition at line 283 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL

Priority level : Very_High

Definition at line 285 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MBURST

Defines
MBURST
DMA Exported Constants

Defines

#define | LL_DMA_MBURST_SINGLE 0x00000000U
#define | LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0
#define | LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1
#define | LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)

Define Documentation

#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)

Memory burst of 16 beats transfer configuration

Definition at line 297 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0

Memory burst of 4 beats transfer configuration

Definition at line 295 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1

Memory burst of 8 beats transfer configuration

Definition at line 296 of file stm32h7xx_ll_dma.h.

#define LL_DMA_MBURST_SINGLE 0x00000000U

Memory burst single transfer configuration

Definition at line 294 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PBURST

Defines
PBURST
DMA Exported Constants

Defines

#define | LL_DMA_PBURST_SINGLE 0x00000000U
#define | LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0
#define | LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1
#define | LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)

Define Documentation

#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)

Peripheral burst of 16 beats transfer configuration

Definition at line 308 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0

Peripheral burst of 4 beats transfer configuration

Definition at line 306 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1

Peripheral burst of 8 beats transfer configuration

Definition at line 307 of file stm32h7xx_ll_dma.h.

#define LL_DMA_PBURST_SINGLE 0x00000000U

Peripheral burst single transfer configuration

Definition at line 305 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_LL_FIFOMODE

Defines
DMA_LL_FIFOMODE
DMA Exported Constants

Defines

#define | LL_DMA_FIFOMODE_DISABLE 0x00000000U
#define | LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS

Define Documentation

#define LL_DMA_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable (direct mode is enabled)

Definition at line 316 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS

FIFO mode enable

Definition at line 317 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FIFOSTATUS 0

Defines
FIFOSTATUS 0
DMA Exported Constants

Defines

#define | LL_DMA_FIFOSTATUS_0_25 0x00000000U
#define | LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0
#define | LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1
#define | LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)
#define | LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2
#define | LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)

Define Documentation

#define LL_DMA_FIFOSTATUS_0_25 0x00000000U

0 < fifo_level < 1/4

Definition at line 325 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0

1/4 < fifo_level < 1/2

Definition at line 326 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1

1/2 < fifo_level < 3/4

Definition at line 327 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)

3/4 < fifo_level < full

Definition at line 328 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2

FIFO is empty

Definition at line 329 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)

FIFO is full

Definition at line 330 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FIFOTHRESHOLD

Defines
FIFOTHRESHOLD
DMA Exported Constants

Defines

#define | LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U
#define | LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0
#define | LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1
#define | LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH

Define Documentation

#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0

FIFO threshold half full configuration

Definition at line 339 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U

FIFO threshold 1 quart full configuration

Definition at line 338 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1

FIFO threshold 3 quarts full configuration

Definition at line 340 of file stm32h7xx_ll_dma.h.

#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH

FIFO threshold full configuration

Definition at line 341 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 382 of file stm32h7xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 374 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Convert DMAxStreamy

Defines
Convert DMAxStreamy
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
Convert DMAx_Streamy into DMAx.
#define | __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)
Convert DMAx_Streamy into LL_DMA_STREAM_y.
#define | __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)
Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy.

Define Documentation

#define __LL_DMA_GET_INSTANCE ( __STREAM_INSTANCE__ ) (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)

Convert DMAx_Streamy into DMAx.

Parameters:
__STREAM_INSTANCE__ DMAx_Streamy
Return values:
DMAx

Definition at line 395 of file stm32h7xx_ll_dma.h.

#define __LL_DMA_GET_STREAM ( __STREAM_INSTANCE__ )
Value:
(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
 LL_DMA_STREAM_7)

Convert DMAx_Streamy into LL_DMA_STREAM_y.

Parameters:
__STREAM_INSTANCE__ DMAx_Streamy
Return values:
LL_DMA_STREAM_y

Definition at line 403 of file stm32h7xx_ll_dma.h.

#define __LL_DMA_GET_STREAM_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __STREAM__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
 DMA2_Stream7)

Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy.

Parameters:
__DMA_INSTANCE__ | DMAx
__STREAM__ | LL_DMA_STREAM_y
Return values:
DMAx_Streamy

Definition at line 426 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableStream (DMA_TypeDef *DMAx, uint32_t Stream)
Enable DMA stream.
__STATIC_INLINE void | LL_DMA_DisableStream (DMA_TypeDef *DMAx, uint32_t Stream)
Disable DMA stream.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledStream (DMA_TypeDef *DMAx, uint32_t Stream)
Check if DMA stream is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
Configure all parameters linked to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Stream)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
Set DMA mode normal, circular or peripheral flow control.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get DMA mode normal, circular or peripheral flow control.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetIncOffsetSize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
Set Peripheral increment offset size.
__STATIC_INLINE uint32_t | LL_DMA_GetIncOffsetSize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral increment offset size.
__STATIC_INLINE void | LL_DMA_SetStreamPriorityLevel (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
Set Stream priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetStreamPriorityLevel (DMA_TypeDef *DMAx, uint32_t Stream)
Get Stream priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Stream)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
Set DMA request for DMA Streams on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Stream)
Get DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMA_SetMemoryBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
Set Memory burst transfer configuration.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory burst transfer configuration.
__STATIC_INLINE void | LL_DMA_SetPeriphBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
Set Peripheral burst transfer configuration.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral burst transfer configuration.
__STATIC_INLINE void | LL_DMA_SetCurrentTargetMem (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE uint32_t | LL_DMA_GetCurrentTargetMem (DMA_TypeDef *DMAx, uint32_t Stream)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE void | LL_DMA_EnableDoubleBufferMode (DMA_TypeDef *DMAx, uint32_t Stream)
Enable the double buffer mode.
__STATIC_INLINE void | LL_DMA_DisableDoubleBufferMode (DMA_TypeDef *DMAx, uint32_t Stream)
Disable the double buffer mode.
__STATIC_INLINE uint32_t | LL_DMA_GetFIFOStatus (DMA_TypeDef *DMAx, uint32_t Stream)
Get FIFO status.
__STATIC_INLINE void | LL_DMA_DisableFifoMode (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Fifo mode.
__STATIC_INLINE void | LL_DMA_EnableFifoMode (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Fifo mode.
__STATIC_INLINE void | LL_DMA_SetFIFOThreshold (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
Select FIFO threshold.
__STATIC_INLINE uint32_t | LL_DMA_GetFIFOThreshold (DMA_TypeDef *DMAx, uint32_t Stream)
Get FIFO threshold.
__STATIC_INLINE void | LL_DMA_ConfigFifo (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
Configure the FIFO .
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetMemory1Address (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
Set Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE uint32_t | LL_DMA_GetMemory1Address (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory 1 address (used in case of Double buffer mode).

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA stream is enabled.
Reference Manual to LL API cross reference:
M0AR M0A LL_DMA_ConfigAddresses
PAR PA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
SrcAddress | Between 0 to 0xFFFFFFFF
DstAddress | Between 0 to 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 1683 of file stm32h7xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigFifo | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | FifoMode,
 |  | uint32_t | FifoThreshold
 | ) |  |

Configure the FIFO .

Reference Manual to LL API cross reference:
FCR FTH LL_DMA_ConfigFifo
FCR DMDIS LL_DMA_ConfigFifo
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
FifoMode This parameter can be one of the following values:
  • LL_DMA_FIFOMODE_ENABLE
  • LL_DMA_FIFOMODE_DISABLE
FifoThreshold This parameter can be one of the following values:
  • LL_DMA_FIFOTHRESHOLD_1_4
  • LL_DMA_FIFOTHRESHOLD_1_2
  • LL_DMA_FIFOTHRESHOLD_3_4
  • LL_DMA_FIFOTHRESHOLD_FULL
Return values:
None

Definition at line 1653 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters linked to DMA transfer.

Reference Manual to LL API cross reference:
CR DIR LL_DMA_ConfigTransfer
CR CIRC LL_DMA_ConfigTransfer
CR PINC LL_DMA_ConfigTransfer
CR MINC LL_DMA_ConfigTransfer
CR PSIZE LL_DMA_ConfigTransfer
CR MSIZE LL_DMA_ConfigTransfer
CR PL LL_DMA_ConfigTransfer
CR PFCTRL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR or LL_DMA_MODE_PFCTRL
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 557 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable the double buffer mode.

Reference Manual to LL API cross reference:
CR DBM LL_DMA_DisableDoubleBufferMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 1497 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableFifoMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable Fifo mode.

Reference Manual to LL API cross reference:
FCR DMDIS LL_DMA_DisableFifoMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 1547 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableStream | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable DMA stream.

Reference Manual to LL API cross reference:
CR EN LL_DMA_DisableStream
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 498 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable the double buffer mode.

Reference Manual to LL API cross reference:
CR DBM LL_DMA_EnableDoubleBufferMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 1475 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableFifoMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable Fifo mode.

Reference Manual to LL API cross reference:
FCR DMDIS LL_DMA_EnableFifoMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 1569 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableStream | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable DMA stream.

Reference Manual to LL API cross reference:
CR EN LL_DMA_EnableStream
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 476 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

Reference Manual to LL API cross reference:
CR CT LL_DMA_GetCurrentTargetMem
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_CURRENTTARGETMEM0
  • LL_DMA_CURRENTTARGETMEM1

Definition at line 1453 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Number of data to transfer.

Reference Manual to LL API cross reference:
NDTR NDT LL_DMA_GetDataLength
Note:
Once the stream is enabled, the return value indicate the remaining bytes to be transmitted.
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1014 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CR DIR LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 610 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get FIFO status.

Reference Manual to LL API cross reference:
FCR FS LL_DMA_GetFIFOStatus
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_FIFOSTATUS_0_25
  • LL_DMA_FIFOSTATUS_25_50
  • LL_DMA_FIFOSTATUS_50_75
  • LL_DMA_FIFOSTATUS_75_100
  • LL_DMA_FIFOSTATUS_EMPTY
  • LL_DMA_FIFOSTATUS_FULL

Definition at line 1525 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get FIFO threshold.

Reference Manual to LL API cross reference:
FCR FTH LL_DMA_GetFIFOThreshold
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_FIFOTHRESHOLD_1_4
  • LL_DMA_FIFOTHRESHOLD_1_2
  • LL_DMA_FIFOTHRESHOLD_3_4
  • LL_DMA_FIFOTHRESHOLD_FULL

Definition at line 1622 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Peripheral increment offset size.

Reference Manual to LL API cross reference:
CR PINCOS LL_DMA_GetIncOffsetSize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_OFFSETSIZE_PSIZE
  • LL_DMA_OFFSETSIZE_FIXEDTO4

Definition at line 912 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get the Memory to Memory Destination address.

Reference Manual to LL API cross reference:
M0AR M0A LL_DMA_GetM2MDstAddress
Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1886 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get the Memory to Memory Source address.

Reference Manual to LL API cross reference:
PAR PA LL_DMA_GetM2MSrcAddress
Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1863 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Memory 1 address (used in case of Double buffer mode).

Reference Manual to LL API cross reference:
M1AR M1A LL_DMA_GetMemory1Address
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1931 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get the Memory address.

Reference Manual to LL API cross reference:
M0AR M0A LL_DMA_GetMemoryAddress
Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1767 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Memory burst transfer configuration.

Reference Manual to LL API cross reference:
CR MBURST LL_DMA_GetMemoryBurstxfer
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MBURST_SINGLE
  • LL_DMA_MBURST_INC4
  • LL_DMA_MBURST_INC8
  • LL_DMA_MBURST_INC16

Definition at line 1351 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT

Definition at line 761 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 863 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get DMA mode normal, circular or peripheral flow control.

Reference Manual to LL API cross reference:
CR CIRC LL_DMA_GetMode
CR PFCTRL LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
  • LL_DMA_MODE_PFCTRL

Definition at line 663 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get the Peripheral address.

Reference Manual to LL API cross reference:
PAR PA LL_DMA_GetPeriphAddress
Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Between 0 to 0xFFFFFFFF

Definition at line 1790 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Peripheral burst transfer configuration.

Reference Manual to LL API cross reference:
CR PBURST LL_DMA_GetPeriphBurstxfer
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PBURST_SINGLE
  • LL_DMA_PBURST_INC4
  • LL_DMA_PBURST_INC8
  • LL_DMA_PBURST_INC16

Definition at line 1404 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_PERIPH_INCREMENT

Definition at line 712 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get DMA request for DMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX1_REQ_MEM2MEM
  • LL_DMAMUX1_REQ_GENERATOR0
  • LL_DMAMUX1_REQ_GENERATOR1
  • LL_DMAMUX1_REQ_GENERATOR2
  • LL_DMAMUX1_REQ_GENERATOR3
  • LL_DMAMUX1_REQ_GENERATOR4
  • LL_DMAMUX1_REQ_GENERATOR5
  • LL_DMAMUX1_REQ_GENERATOR6
  • LL_DMAMUX1_REQ_GENERATOR7
  • LL_DMAMUX1_REQ_ADC1
  • LL_DMAMUX1_REQ_ADC2
  • LL_DMAMUX1_REQ_TIM1_CH1
  • LL_DMAMUX1_REQ_TIM1_CH2
  • LL_DMAMUX1_REQ_TIM1_CH3
  • LL_DMAMUX1_REQ_TIM1_CH4
  • LL_DMAMUX1_REQ_TIM1_UP
  • LL_DMAMUX1_REQ_TIM1_TRIG
  • LL_DMAMUX1_REQ_TIM1_COM
  • LL_DMAMUX1_REQ_TIM2_CH1
  • LL_DMAMUX1_REQ_TIM2_CH2
  • LL_DMAMUX1_REQ_TIM2_CH3
  • LL_DMAMUX1_REQ_TIM2_CH4
  • LL_DMAMUX1_REQ_TIM2_UP
  • LL_DMAMUX1_REQ_TIM3_CH1
  • LL_DMAMUX1_REQ_TIM3_CH2
  • LL_DMAMUX1_REQ_TIM3_CH3
  • LL_DMAMUX1_REQ_TIM3_CH4
  • LL_DMAMUX1_REQ_TIM3_UP
  • LL_DMAMUX1_REQ_TIM3_TRIG
  • LL_DMAMUX1_REQ_TIM4_CH1
  • LL_DMAMUX1_REQ_TIM4_CH2
  • LL_DMAMUX1_REQ_TIM4_CH3
  • LL_DMAMUX1_REQ_TIM4_UP
  • LL_DMAMUX1_REQ_I2C1_RX
  • LL_DMAMUX1_REQ_I2C1_TX
  • LL_DMAMUX1_REQ_I2C2_RX
  • LL_DMAMUX1_REQ_I2C2_TX
  • LL_DMAMUX1_REQ_SPI1_RX
  • LL_DMAMUX1_REQ_SPI1_TX
  • LL_DMAMUX1_REQ_SPI2_RX
  • LL_DMAMUX1_REQ_SPI2_TX
  • LL_DMAMUX1_REQ_USART1_RX
  • LL_DMAMUX1_REQ_USART1_TX
  • LL_DMAMUX1_REQ_USART2_RX
  • LL_DMAMUX1_REQ_USART2_TX
  • LL_DMAMUX1_REQ_USART3_RX
  • LL_DMAMUX1_REQ_USART3_TX
  • LL_DMAMUX1_REQ_TIM8_CH1
  • LL_DMAMUX1_REQ_TIM8_CH2
  • LL_DMAMUX1_REQ_TIM8_CH3
  • LL_DMAMUX1_REQ_TIM8_CH4
  • LL_DMAMUX1_REQ_TIM8_UP
  • LL_DMAMUX1_REQ_TIM8_TRIG
  • LL_DMAMUX1_REQ_TIM8_COM
  • LL_DMAMUX1_REQ_TIM5_CH1
  • LL_DMAMUX1_REQ_TIM5_CH2
  • LL_DMAMUX1_REQ_TIM5_CH3
  • LL_DMAMUX1_REQ_TIM5_CH4
  • LL_DMAMUX1_REQ_TIM5_UP
  • LL_DMAMUX1_REQ_TIM5_TRIG
  • LL_DMAMUX1_REQ_SPI3_RX
  • LL_DMAMUX1_REQ_SPI3_TX
  • LL_DMAMUX1_REQ_UART4_RX
  • LL_DMAMUX1_REQ_UART4_TX
  • LL_DMAMUX1_REQ_UART5_RX
  • LL_DMAMUX1_REQ_UART5_TX
  • LL_DMAMUX1_REQ_DAC1_CH1
  • LL_DMAMUX1_REQ_DAC1_CH2
  • LL_DMAMUX1_REQ_TIM6_UP
  • LL_DMAMUX1_REQ_TIM7_UP
  • LL_DMAMUX1_REQ_USART6_RX
  • LL_DMAMUX1_REQ_USART6_TX
  • LL_DMAMUX1_REQ_I2C3_RX
  • LL_DMAMUX1_REQ_I2C3_TX
  • LL_DMAMUX1_REQ_DCMI_PSSI
  • LL_DMAMUX1_REQ_CRYP_IN
  • LL_DMAMUX1_REQ_CRYP_OUT
  • LL_DMAMUX1_REQ_HASH_IN
  • LL_DMAMUX1_REQ_UART7_RX
  • LL_DMAMUX1_REQ_UART7_TX
  • LL_DMAMUX1_REQ_UART8_RX
  • LL_DMAMUX1_REQ_UART8_TX
  • LL_DMAMUX1_REQ_SPI4_RX
  • LL_DMAMUX1_REQ_SPI4_TX
  • LL_DMAMUX1_REQ_SPI5_RX
  • LL_DMAMUX1_REQ_SPI5_TX
  • LL_DMAMUX1_REQ_SAI1_A
  • LL_DMAMUX1_REQ_SAI1_B
  • LL_DMAMUX1_REQ_SAI2_A
  • LL_DMAMUX1_REQ_SAI2_B
  • LL_DMAMUX1_REQ_SWPMI_RX
  • LL_DMAMUX1_REQ_SWPMI_TX
  • LL_DMAMUX1_REQ_SPDIF_RX_DT
  • LL_DMAMUX1_REQ_SPDIF_RX_CS
  • LL_DMAMUX1_REQ_HRTIM_MASTER (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
  • LL_DMAMUX1_REQ_DFSDM1_FLT0
  • LL_DMAMUX1_REQ_DFSDM1_FLT1
  • LL_DMAMUX1_REQ_DFSDM1_FLT2
  • LL_DMAMUX1_REQ_DFSDM1_FLT3
  • LL_DMAMUX1_REQ_TIM15_CH1
  • LL_DMAMUX1_REQ_TIM15_UP
  • LL_DMAMUX1_REQ_TIM15_TRIG
  • LL_DMAMUX1_REQ_TIM15_COM
  • LL_DMAMUX1_REQ_TIM16_CH1
  • LL_DMAMUX1_REQ_TIM16_UP
  • LL_DMAMUX1_REQ_TIM17_CH1
  • LL_DMAMUX1_REQ_TIM17_UP
  • LL_DMAMUX1_REQ_SAI3_A (*)
  • LL_DMAMUX1_REQ_SAI3_B (*)
  • LL_DMAMUX1_REQ_ADC3 (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
Note:
(*) Availability depends on devices.

Definition at line 1300 of file stm32h7xx_ll_dma.h.

References DMAMUX_CCR_SIZE, and LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 812 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Get Stream priority level.

Reference Manual to LL API cross reference:
CR PL LL_DMA_GetStreamPriorityLevel
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 965 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if DMA stream is enabled or disabled.

Reference Manual to LL API cross reference:
CR EN LL_DMA_IsEnabledStream
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 520 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetCurrentTargetMem | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | CurrentMemory
 | ) |  |

Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

Reference Manual to LL API cross reference:
CR CT LL_DMA_SetCurrentTargetMem
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
CurrentMemory This parameter can be one of the following values:
  • LL_DMA_CURRENTTARGETMEM0
  • LL_DMA_CURRENTTARGETMEM1
Return values:
None

Definition at line 1429 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Reference Manual to LL API cross reference:
NDTR NDT LL_DMA_SetDataLength
Note:
This action has no effect if stream is enabled.
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
NbData | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 990 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CR DIR LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 585 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetFIFOThreshold | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Threshold
 | ) |  |

Select FIFO threshold.

Reference Manual to LL API cross reference:
FCR FTH LL_DMA_SetFIFOThreshold
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Threshold This parameter can be one of the following values:
  • LL_DMA_FIFOTHRESHOLD_1_4
  • LL_DMA_FIFOTHRESHOLD_1_2
  • LL_DMA_FIFOTHRESHOLD_3_4
  • LL_DMA_FIFOTHRESHOLD_FULL
Return values:
None

Definition at line 1596 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetIncOffsetSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | OffsetSize
 | ) |  |

Set Peripheral increment offset size.

Reference Manual to LL API cross reference:
CR PINCOS LL_DMA_SetIncOffsetSize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
OffsetSize This parameter can be one of the following values:
  • LL_DMA_OFFSETSIZE_PSIZE
  • LL_DMA_OFFSETSIZE_FIXEDTO4
Return values:
None

Definition at line 888 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Reference Manual to LL API cross reference:
M0AR M0A LL_DMA_SetM2MDstAddress
Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA stream is enabled.
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
MemoryAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1840 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Reference Manual to LL API cross reference:
PAR PA LL_DMA_SetM2MSrcAddress
Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA stream is enabled.
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
MemoryAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1815 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemory1Address | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Address
 | ) |  |

Set Memory 1 address (used in case of Double buffer mode).

Reference Manual to LL API cross reference:
M1AR M1A LL_DMA_SetMemory1Address
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Address | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1909 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Reference Manual to LL API cross reference:
M0AR M0A LL_DMA_SetMemoryAddress
Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA stream is enabled.
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
MemoryAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1719 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Mburst
 | ) |  |

Set Memory burst transfer configuration.

Reference Manual to LL API cross reference:
CR MBURST LL_DMA_SetMemoryBurstxfer
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Mburst This parameter can be one of the following values:
  • LL_DMA_MBURST_SINGLE
  • LL_DMA_MBURST_INC4
  • LL_DMA_MBURST_INC8
  • LL_DMA_MBURST_INC16
Return values:
None

Definition at line 1325 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | IncrementMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
IncrementMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT
Return values:
None

Definition at line 737 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Size
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Size This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 838 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode normal, circular or peripheral flow control.

Reference Manual to LL API cross reference:
CR CIRC LL_DMA_SetMode
CR PFCTRL LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
  • LL_DMA_MODE_PFCTRL
Return values:
None

Definition at line 637 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Reference Manual to LL API cross reference:
PAR PA LL_DMA_SetPeriphAddress
Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA stream is enabled.
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
PeriphAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 1744 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Pburst
 | ) |  |

Set Peripheral burst transfer configuration.

Reference Manual to LL API cross reference:
CR PBURST LL_DMA_SetPeriphBurstxfer
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Pburst This parameter can be one of the following values:
  • LL_DMA_PBURST_SINGLE
  • LL_DMA_PBURST_INC4
  • LL_DMA_PBURST_INC8
  • LL_DMA_PBURST_INC16
Return values:
None

Definition at line 1378 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | IncrementMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
IncrementMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_PERIPH_INCREMENT
Return values:
None

Definition at line 688 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Request
 | ) |  |

Set DMA request for DMA Streams on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Request This parameter can be one of the following values:
  • LL_DMAMUX1_REQ_MEM2MEM
  • LL_DMAMUX1_REQ_GENERATOR0
  • LL_DMAMUX1_REQ_GENERATOR1
  • LL_DMAMUX1_REQ_GENERATOR2
  • LL_DMAMUX1_REQ_GENERATOR3
  • LL_DMAMUX1_REQ_GENERATOR4
  • LL_DMAMUX1_REQ_GENERATOR5
  • LL_DMAMUX1_REQ_GENERATOR6
  • LL_DMAMUX1_REQ_GENERATOR7
  • LL_DMAMUX1_REQ_ADC1
  • LL_DMAMUX1_REQ_ADC2
  • LL_DMAMUX1_REQ_TIM1_CH1
  • LL_DMAMUX1_REQ_TIM1_CH2
  • LL_DMAMUX1_REQ_TIM1_CH3
  • LL_DMAMUX1_REQ_TIM1_CH4
  • LL_DMAMUX1_REQ_TIM1_UP
  • LL_DMAMUX1_REQ_TIM1_TRIG
  • LL_DMAMUX1_REQ_TIM1_COM
  • LL_DMAMUX1_REQ_TIM2_CH1
  • LL_DMAMUX1_REQ_TIM2_CH2
  • LL_DMAMUX1_REQ_TIM2_CH3
  • LL_DMAMUX1_REQ_TIM2_CH4
  • LL_DMAMUX1_REQ_TIM2_UP
  • LL_DMAMUX1_REQ_TIM3_CH1
  • LL_DMAMUX1_REQ_TIM3_CH2
  • LL_DMAMUX1_REQ_TIM3_CH3
  • LL_DMAMUX1_REQ_TIM3_CH4
  • LL_DMAMUX1_REQ_TIM3_UP
  • LL_DMAMUX1_REQ_TIM3_TRIG
  • LL_DMAMUX1_REQ_TIM4_CH1
  • LL_DMAMUX1_REQ_TIM4_CH2
  • LL_DMAMUX1_REQ_TIM4_CH3
  • LL_DMAMUX1_REQ_TIM4_UP
  • LL_DMAMUX1_REQ_I2C1_RX
  • LL_DMAMUX1_REQ_I2C1_TX
  • LL_DMAMUX1_REQ_I2C2_RX
  • LL_DMAMUX1_REQ_I2C2_TX
  • LL_DMAMUX1_REQ_SPI1_RX
  • LL_DMAMUX1_REQ_SPI1_TX
  • LL_DMAMUX1_REQ_SPI2_RX
  • LL_DMAMUX1_REQ_SPI2_TX
  • LL_DMAMUX1_REQ_USART1_RX
  • LL_DMAMUX1_REQ_USART1_TX
  • LL_DMAMUX1_REQ_USART2_RX
  • LL_DMAMUX1_REQ_USART2_TX
  • LL_DMAMUX1_REQ_USART3_RX
  • LL_DMAMUX1_REQ_USART3_TX
  • LL_DMAMUX1_REQ_TIM8_CH1
  • LL_DMAMUX1_REQ_TIM8_CH2
  • LL_DMAMUX1_REQ_TIM8_CH3
  • LL_DMAMUX1_REQ_TIM8_CH4
  • LL_DMAMUX1_REQ_TIM8_UP
  • LL_DMAMUX1_REQ_TIM8_TRIG
  • LL_DMAMUX1_REQ_TIM8_COM
  • LL_DMAMUX1_REQ_TIM5_CH1
  • LL_DMAMUX1_REQ_TIM5_CH2
  • LL_DMAMUX1_REQ_TIM5_CH3
  • LL_DMAMUX1_REQ_TIM5_CH4
  • LL_DMAMUX1_REQ_TIM5_UP
  • LL_DMAMUX1_REQ_TIM5_TRIG
  • LL_DMAMUX1_REQ_SPI3_RX
  • LL_DMAMUX1_REQ_SPI3_TX
  • LL_DMAMUX1_REQ_UART4_RX
  • LL_DMAMUX1_REQ_UART4_TX
  • LL_DMAMUX1_REQ_UART5_RX
  • LL_DMAMUX1_REQ_UART5_TX
  • LL_DMAMUX1_REQ_DAC1_CH1
  • LL_DMAMUX1_REQ_DAC1_CH2
  • LL_DMAMUX1_REQ_TIM6_UP
  • LL_DMAMUX1_REQ_TIM7_UP
  • LL_DMAMUX1_REQ_USART6_RX
  • LL_DMAMUX1_REQ_USART6_TX
  • LL_DMAMUX1_REQ_I2C3_RX
  • LL_DMAMUX1_REQ_I2C3_TX
  • LL_DMAMUX1_REQ_DCMI_PSSI
  • LL_DMAMUX1_REQ_CRYP_IN
  • LL_DMAMUX1_REQ_CRYP_OUT
  • LL_DMAMUX1_REQ_HASH_IN
  • LL_DMAMUX1_REQ_UART7_RX
  • LL_DMAMUX1_REQ_UART7_TX
  • LL_DMAMUX1_REQ_UART8_RX
  • LL_DMAMUX1_REQ_UART8_TX
  • LL_DMAMUX1_REQ_SPI4_RX
  • LL_DMAMUX1_REQ_SPI4_TX
  • LL_DMAMUX1_REQ_SPI5_RX
  • LL_DMAMUX1_REQ_SPI5_TX
  • LL_DMAMUX1_REQ_SAI1_A
  • LL_DMAMUX1_REQ_SAI1_B
  • LL_DMAMUX1_REQ_SAI2_A
  • LL_DMAMUX1_REQ_SAI2_B
  • LL_DMAMUX1_REQ_SWPMI_RX
  • LL_DMAMUX1_REQ_SWPMI_TX
  • LL_DMAMUX1_REQ_SPDIF_RX_DT
  • LL_DMAMUX1_REQ_SPDIF_RX_CS
  • LL_DMAMUX1_REQ_HRTIM_MASTER (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
  • LL_DMAMUX1_REQ_DFSDM1_FLT0
  • LL_DMAMUX1_REQ_DFSDM1_FLT1
  • LL_DMAMUX1_REQ_DFSDM1_FLT2
  • LL_DMAMUX1_REQ_DFSDM1_FLT3
  • LL_DMAMUX1_REQ_TIM15_CH1
  • LL_DMAMUX1_REQ_TIM15_UP
  • LL_DMAMUX1_REQ_TIM15_TRIG
  • LL_DMAMUX1_REQ_TIM15_COM
  • LL_DMAMUX1_REQ_TIM16_CH1
  • LL_DMAMUX1_REQ_TIM16_UP
  • LL_DMAMUX1_REQ_TIM17_CH1
  • LL_DMAMUX1_REQ_TIM17_UP
  • LL_DMAMUX1_REQ_SAI3_A (*)
  • LL_DMAMUX1_REQ_SAI3_B (*)
  • LL_DMAMUX1_REQ_ADC3 (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 1158 of file stm32h7xx_ll_dma.h.

References DMAMUX_CCR_SIZE, and LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Size
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Size This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 787 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | uint32_t | Priority
 | ) |  |

Set Stream priority level.

Reference Manual to LL API cross reference:
CR PL LL_DMA_SetStreamPriorityLevel
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 939 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT0 (DMA_TypeDef *DMAx)
Get Stream 0 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Stream 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Stream 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Stream 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Stream 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Stream 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Stream 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Stream 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC0 (DMA_TypeDef *DMAx)
Get Stream 0 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Stream 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Stream 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Stream 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Stream 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Stream 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Stream 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Stream 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE0 (DMA_TypeDef *DMAx)
Get Stream 0 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Stream 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Stream 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Stream 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Stream 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Stream 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Stream 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Stream 7 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME0 (DMA_TypeDef *DMAx)
Get Stream 0 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME1 (DMA_TypeDef *DMAx)
Get Stream 1 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME2 (DMA_TypeDef *DMAx)
Get Stream 2 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME3 (DMA_TypeDef *DMAx)
Get Stream 3 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME4 (DMA_TypeDef *DMAx)
Get Stream 4 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME5 (DMA_TypeDef *DMAx)
Get Stream 5 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME6 (DMA_TypeDef *DMAx)
Get Stream 6 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME7 (DMA_TypeDef *DMAx)
Get Stream 7 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE0 (DMA_TypeDef *DMAx)
Get Stream 0 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE1 (DMA_TypeDef *DMAx)
Get Stream 1 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE2 (DMA_TypeDef *DMAx)
Get Stream 2 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE3 (DMA_TypeDef *DMAx)
Get Stream 3 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE4 (DMA_TypeDef *DMAx)
Get Stream 4 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE5 (DMA_TypeDef *DMAx)
Get Stream 5 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE6 (DMA_TypeDef *DMAx)
Get Stream 6 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE7 (DMA_TypeDef *DMAx)
Get Stream 7 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT0 (DMA_TypeDef *DMAx)
Clear Stream 0 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Stream 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Stream 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Stream 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Stream 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Stream 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Stream 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Stream 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC0 (DMA_TypeDef *DMAx)
Clear Stream 0 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Stream 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Stream 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Stream 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Stream 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Stream 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Stream 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Stream 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE0 (DMA_TypeDef *DMAx)
Clear Stream 0 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Stream 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Stream 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Stream 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Stream 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Stream 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Stream 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Stream 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME0 (DMA_TypeDef *DMAx)
Clear Stream 0 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME1 (DMA_TypeDef *DMAx)
Clear Stream 1 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME2 (DMA_TypeDef *DMAx)
Clear Stream 2 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME3 (DMA_TypeDef *DMAx)
Clear Stream 3 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME4 (DMA_TypeDef *DMAx)
Clear Stream 4 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME5 (DMA_TypeDef *DMAx)
Clear Stream 5 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME6 (DMA_TypeDef *DMAx)
Clear Stream 6 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME7 (DMA_TypeDef *DMAx)
Clear Stream 7 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE0 (DMA_TypeDef *DMAx)
Clear Stream 0 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE1 (DMA_TypeDef *DMAx)
Clear Stream 1 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE2 (DMA_TypeDef *DMAx)
Clear Stream 2 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE3 (DMA_TypeDef *DMAx)
Clear Stream 3 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE4 (DMA_TypeDef *DMAx)
Clear Stream 4 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE5 (DMA_TypeDef *DMAx)
Clear Stream 5 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE6 (DMA_TypeDef *DMAx)
Clear Stream 6 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE7 (DMA_TypeDef *DMAx)
Clear Stream 7 FIFO error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_DME0 ( DMA_TypeDef * DMAx )

Clear Stream 0 direct mode error flag.

Reference Manual to LL API cross reference:
LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2656 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME1 ( DMA_TypeDef * DMAx )

Clear Stream 1 direct mode error flag.

Reference Manual to LL API cross reference:
LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2667 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME2 ( DMA_TypeDef * DMAx )

Clear Stream 2 direct mode error flag.

Reference Manual to LL API cross reference:
LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2678 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME3 ( DMA_TypeDef * DMAx )

Clear Stream 3 direct mode error flag.

Reference Manual to LL API cross reference:
LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2689 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME4 ( DMA_TypeDef * DMAx )

Clear Stream 4 direct mode error flag.

Reference Manual to LL API cross reference:
HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2700 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME5 ( DMA_TypeDef * DMAx )

Clear Stream 5 direct mode error flag.

Reference Manual to LL API cross reference:
HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2711 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME6 ( DMA_TypeDef * DMAx )

Clear Stream 6 direct mode error flag.

Reference Manual to LL API cross reference:
HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2722 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_DME7 ( DMA_TypeDef * DMAx )

Clear Stream 7 direct mode error flag.

Reference Manual to LL API cross reference:
HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2733 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE0 ( DMA_TypeDef * DMAx )

Clear Stream 0 FIFO error flag.

Reference Manual to LL API cross reference:
LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2744 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE1 ( DMA_TypeDef * DMAx )

Clear Stream 1 FIFO error flag.

Reference Manual to LL API cross reference:
LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2755 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE2 ( DMA_TypeDef * DMAx )

Clear Stream 2 FIFO error flag.

Reference Manual to LL API cross reference:
LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2766 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE3 ( DMA_TypeDef * DMAx )

Clear Stream 3 FIFO error flag.

Reference Manual to LL API cross reference:
LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2777 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE4 ( DMA_TypeDef * DMAx )

Clear Stream 4 FIFO error flag.

Reference Manual to LL API cross reference:
HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2788 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE5 ( DMA_TypeDef * DMAx )

Clear Stream 5 FIFO error flag.

Reference Manual to LL API cross reference:
HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2799 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE6 ( DMA_TypeDef * DMAx )

Clear Stream 6 FIFO error flag.

Reference Manual to LL API cross reference:
HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2810 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_FE7 ( DMA_TypeDef * DMAx )

Clear Stream 7 FIFO error flag.

Reference Manual to LL API cross reference:
HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2821 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT0 ( DMA_TypeDef * DMAx )

Clear Stream 0 half transfer flag.

Reference Manual to LL API cross reference:
LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2392 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Stream 1 half transfer flag.

Reference Manual to LL API cross reference:
LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2403 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Stream 2 half transfer flag.

Reference Manual to LL API cross reference:
LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2414 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Stream 3 half transfer flag.

Reference Manual to LL API cross reference:
LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2425 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Stream 4 half transfer flag.

Reference Manual to LL API cross reference:
HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2436 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Stream 5 half transfer flag.

Reference Manual to LL API cross reference:
HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2447 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Stream 6 half transfer flag.

Reference Manual to LL API cross reference:
HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2458 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Stream 7 half transfer flag.

Reference Manual to LL API cross reference:
HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2469 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC0 ( DMA_TypeDef * DMAx )

Clear Stream 0 transfer complete flag.

Reference Manual to LL API cross reference:
LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2480 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Stream 1 transfer complete flag.

Reference Manual to LL API cross reference:
LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2491 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Stream 2 transfer complete flag.

Reference Manual to LL API cross reference:
LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2502 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Stream 3 transfer complete flag.

Reference Manual to LL API cross reference:
LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2513 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Stream 4 transfer complete flag.

Reference Manual to LL API cross reference:
HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2524 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Stream 5 transfer complete flag.

Reference Manual to LL API cross reference:
HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2535 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Stream 6 transfer complete flag.

Reference Manual to LL API cross reference:
HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2546 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Stream 7 transfer complete flag.

Reference Manual to LL API cross reference:
HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2557 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE0 ( DMA_TypeDef * DMAx )

Clear Stream 0 transfer error flag.

Reference Manual to LL API cross reference:
LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2568 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Stream 1 transfer error flag.

Reference Manual to LL API cross reference:
LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2579 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Stream 2 transfer error flag.

Reference Manual to LL API cross reference:
LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2590 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Stream 3 transfer error flag.

Reference Manual to LL API cross reference:
LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2601 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Stream 4 transfer error flag.

Reference Manual to LL API cross reference:
HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2612 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Stream 5 transfer error flag.

Reference Manual to LL API cross reference:
HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2623 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Stream 6 transfer error flag.

Reference Manual to LL API cross reference:
HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2634 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Stream 7 transfer error flag.

Reference Manual to LL API cross reference:
HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2645 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0 ( DMA_TypeDef * DMAx )

Get Stream 0 direct mode error flag.

Reference Manual to LL API cross reference:
LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2216 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1 ( DMA_TypeDef * DMAx )

Get Stream 1 direct mode error flag.

Reference Manual to LL API cross reference:
LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2227 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2 ( DMA_TypeDef * DMAx )

Get Stream 2 direct mode error flag.

Reference Manual to LL API cross reference:
LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2238 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3 ( DMA_TypeDef * DMAx )

Get Stream 3 direct mode error flag.

Reference Manual to LL API cross reference:
LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2249 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4 ( DMA_TypeDef * DMAx )

Get Stream 4 direct mode error flag.

Reference Manual to LL API cross reference:
HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2260 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5 ( DMA_TypeDef * DMAx )

Get Stream 5 direct mode error flag.

Reference Manual to LL API cross reference:
HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2271 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6 ( DMA_TypeDef * DMAx )

Get Stream 6 direct mode error flag.

Reference Manual to LL API cross reference:
HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2282 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7 ( DMA_TypeDef * DMAx )

Get Stream 7 direct mode error flag.

Reference Manual to LL API cross reference:
HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2293 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0 ( DMA_TypeDef * DMAx )

Get Stream 0 FIFO error flag.

Reference Manual to LL API cross reference:
LISR FEIF0 LL_DMA_IsActiveFlag_FE0
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2304 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1 ( DMA_TypeDef * DMAx )

Get Stream 1 FIFO error flag.

Reference Manual to LL API cross reference:
LISR FEIF1 LL_DMA_IsActiveFlag_FE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2315 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2 ( DMA_TypeDef * DMAx )

Get Stream 2 FIFO error flag.

Reference Manual to LL API cross reference:
LISR FEIF2 LL_DMA_IsActiveFlag_FE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2326 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3 ( DMA_TypeDef * DMAx )

Get Stream 3 FIFO error flag.

Reference Manual to LL API cross reference:
LISR FEIF3 LL_DMA_IsActiveFlag_FE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2337 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4 ( DMA_TypeDef * DMAx )

Get Stream 4 FIFO error flag.

Reference Manual to LL API cross reference:
HISR FEIF4 LL_DMA_IsActiveFlag_FE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2348 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5 ( DMA_TypeDef * DMAx )

Get Stream 5 FIFO error flag.

Reference Manual to LL API cross reference:
HISR FEIF0 LL_DMA_IsActiveFlag_FE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2359 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6 ( DMA_TypeDef * DMAx )

Get Stream 6 FIFO error flag.

Reference Manual to LL API cross reference:
HISR FEIF6 LL_DMA_IsActiveFlag_FE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2370 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7 ( DMA_TypeDef * DMAx )

Get Stream 7 FIFO error flag.

Reference Manual to LL API cross reference:
HISR FEIF7 LL_DMA_IsActiveFlag_FE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2381 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0 ( DMA_TypeDef * DMAx )

Get Stream 0 half transfer flag.

Reference Manual to LL API cross reference:
LISR HTIF0 LL_DMA_IsActiveFlag_HT0
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1952 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Stream 1 half transfer flag.

Reference Manual to LL API cross reference:
LISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1963 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Stream 2 half transfer flag.

Reference Manual to LL API cross reference:
LISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1974 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Stream 3 half transfer flag.

Reference Manual to LL API cross reference:
LISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1985 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Stream 4 half transfer flag.

Reference Manual to LL API cross reference:
HISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1996 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Stream 5 half transfer flag.

Reference Manual to LL API cross reference:
HISR HTIF0 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2007 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Stream 6 half transfer flag.

Reference Manual to LL API cross reference:
HISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2018 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Stream 7 half transfer flag.

Reference Manual to LL API cross reference:
HISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2029 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0 ( DMA_TypeDef * DMAx )

Get Stream 0 transfer complete flag.

Reference Manual to LL API cross reference:
LISR TCIF0 LL_DMA_IsActiveFlag_TC0
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2040 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Stream 1 transfer complete flag.

Reference Manual to LL API cross reference:
LISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2051 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Stream 2 transfer complete flag.

Reference Manual to LL API cross reference:
LISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2062 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Stream 3 transfer complete flag.

Reference Manual to LL API cross reference:
LISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2073 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Stream 4 transfer complete flag.

Reference Manual to LL API cross reference:
HISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2084 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Stream 5 transfer complete flag.

Reference Manual to LL API cross reference:
HISR TCIF0 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2095 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Stream 6 transfer complete flag.

Reference Manual to LL API cross reference:
HISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2106 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Stream 7 transfer complete flag.

Reference Manual to LL API cross reference:
HISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2117 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0 ( DMA_TypeDef * DMAx )

Get Stream 0 transfer error flag.

Reference Manual to LL API cross reference:
LISR TEIF0 LL_DMA_IsActiveFlag_TE0
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2128 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Stream 1 transfer error flag.

Reference Manual to LL API cross reference:
LISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2139 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Stream 2 transfer error flag.

Reference Manual to LL API cross reference:
LISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2150 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Stream 3 transfer error flag.

Reference Manual to LL API cross reference:
LISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2161 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Stream 4 transfer error flag.

Reference Manual to LL API cross reference:
HISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2172 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Stream 5 transfer error flag.

Reference Manual to LL API cross reference:
HISR TEIF0 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2183 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Stream 6 transfer error flag.

Reference Manual to LL API cross reference:
HISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2194 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Stream 7 transfer error flag.

Reference Manual to LL API cross reference:
HISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 2205 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Direct mode error interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Enable FIFO error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Direct mode error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Disable FIFO error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Half transfer interrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Transfer error nterrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Transfer complete interrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Direct mode error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Check if FIFO error interrup is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_DME | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable Direct mode error interrupt.

Reference Manual to LL API cross reference:
CR DMEIE LL_DMA_DisableIT_DME
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 3025 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_FE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable FIFO error interrupt.

Reference Manual to LL API cross reference:
FCR FEIE LL_DMA_DisableIT_FE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 3047 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2959 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 3003 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2981 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_DME | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable Direct mode error interrupt.

Reference Manual to LL API cross reference:
CR DMEIE LL_DMA_EnableIT_DME
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2915 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_FE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable FIFO error interrupt.

Reference Manual to LL API cross reference:
FCR FEIE LL_DMA_EnableIT_FE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2937 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2849 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2893 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
None

Definition at line 2871 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if Direct mode error interrupt is enabled.

Reference Manual to LL API cross reference:
CR DMEIE LL_DMA_IsEnabledIT_DME
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 3135 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if FIFO error interrup is enabled.

Reference Manual to LL API cross reference:
FCR FEIE LL_DMA_IsEnabledIT_FE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 3157 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if Half transfer interrup is enabled.

Reference Manual to LL API cross reference:
CR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 3069 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if Transfer complete interrup is enabled.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 3113 of file stm32h7xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

Check if Transfer error nterrup is enabled.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
Return values:
State of bit (1 or 0).

Definition at line 3091 of file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Stream)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
  • LL_DMA_STREAM_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 153 of file stm32h7xx_ll_dma.c.

References __LL_DMA_GET_STREAM_INSTANCE, assert_param, IS_LL_DMA_ALL_STREAM_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_PERIPH_DMA2, LL_AHB1_GRP1_ReleaseReset(), LL_DMA_DisableStream(), LL_DMA_SetPeriphRequest(), LL_DMA_STREAM_0, LL_DMA_STREAM_1, LL_DMA_STREAM_2, LL_DMA_STREAM_3, LL_DMA_STREAM_4, LL_DMA_STREAM_5, LL_DMA_STREAM_6, LL_DMA_STREAM_7, LL_DMA_STREAM_ALL, LL_DMA_WriteReg, and LL_DMAMUX1_REQ_MEM2MEM.

uint32_t LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Stream,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_STREAM
Parameters:
DMAx | DMAx Instance
Stream This parameter can be one of the following values:
  • LL_DMA_STREAM_0
  • LL_DMA_STREAM_1
  • LL_DMA_STREAM_2
  • LL_DMA_STREAM_3
  • LL_DMA_STREAM_4
  • LL_DMA_STREAM_5
  • LL_DMA_STREAM_6
  • LL_DMA_STREAM_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 282 of file stm32h7xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, LL_DMA_InitTypeDef::FIFOMode, LL_DMA_InitTypeDef::FIFOThreshold, IS_LL_DMA_ALL_STREAM_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_FIFO_MODE_STATE, IS_LL_DMA_FIFO_THRESHOLD, IS_LL_DMA_MEMORY_BURST, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHERAL_BURST, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PRIORITY, IS_LL_DMA_REQUEST, LL_DMA_ConfigFifo(), LL_DMA_ConfigTransfer(), LL_DMA_FIFOMODE_DISABLE, LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetMemoryBurstxfer(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphBurstxfer(), LL_DMA_SetPeriphRequest(), LL_DMA_InitTypeDef::MemBurst, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphBurst, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 383 of file stm32h7xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_InitTypeDef::FIFOMode, LL_DMA_InitTypeDef::FIFOThreshold, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_FIFOMODE_DISABLE, LL_DMA_FIFOTHRESHOLD_1_4, LL_DMA_MBURST_SINGLE, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PBURST_SINGLE, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMAMUX1_REQ_MEM2MEM, LL_DMA_InitTypeDef::MemBurst, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphBurst, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_LL_Private_Macros

Defines
DMA_LL_Private_Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)
#define | IS_LL_DMA_FIFO_MODE_STATE(STATE)
#define | IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_LL_DMA_MEMORY_BURST(BURST)
#define | IS_LL_DMA_PERIPHERAL_BURST(BURST)

Define Documentation

#define IS_LL_DMA_ALL_STREAM_INSTANCE | ( | INSTANCE,
 |  | STREAM
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
                                                            ((STREAM) == LL_DMA_STREAM_ALL))) || \
                                                           (((INSTANCE) == DMA2) && \
                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
                                                            ((STREAM) == LL_DMA_STREAM_ALL))))

Definition at line 82 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 47 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_FIFO_MODE_STATE ( STATE )
Value:
(((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
                                             ((STATE) == LL_DMA_FIFOMODE_ENABLE))

Definition at line 103 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))

Definition at line 106 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORY_BURST ( BURST )
Value:
(((BURST) == LL_DMA_MBURST_SINGLE) || \
                                             ((BURST) == LL_DMA_MBURST_INC4)   || \
                                             ((BURST) == LL_DMA_MBURST_INC8)   || \
                                             ((BURST) == LL_DMA_MBURST_INC16))

Definition at line 111 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 65 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 58 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))

Definition at line 51 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 69 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 61 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHERAL_BURST ( BURST )
Value:
(((BURST) == LL_DMA_PBURST_SINGLE) || \
                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
                                            ((BURST) == LL_DMA_PBURST_INC16))

Definition at line 116 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 55 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 77 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_REQUEST ( REQUEST ) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))

Definition at line 74 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA

Modules | Defines
DMA
STM32H7xx_LL_Driver

Modules

DMA Private Variables
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions
DMA_LL_Private_Macros

Defines

#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
Helper macro to convert DMA Instance DMAx into DMAMUX channel.

Define Documentation

#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL ( __DMA_INSTANCE__ ) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)

Helper macro to convert DMA Instance DMAx into DMAMUX channel.

Note:
DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
Parameters:
__DMA_INSTANCE__ DMAx
Return values:
Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).

Definition at line 74 of file stm32h7xx_ll_dma.h.

Referenced by LL_DMA_GetPeriphRequest(), and LL_DMA_SetPeriphRequest().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA2D Private Macros

Defines
DMA2D Private Macros
DMA2D

Defines

#define | IS_LL_DMA2D_MODE(MODE)
#define | IS_LL_DMA2D_OCMODE(MODE_ARGB)
#define | IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_OFFSET_MODE(MODE)
#define | IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
#define | IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
#define | IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
#define | IS_LL_DMA2D_SWAP_MODE(MODE)
#define | IS_LL_DMA2D_ALPHAINV(ALPHA)
#define | IS_LL_DMA2D_RBSWAP(RBSWAP)
#define | IS_LL_DMA2D_LCMODE(MODE_ARGB)
#define | IS_LL_DMA2D_CLUTCMODE(CLUTCMODE)
#define | IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
#define | IS_LL_DMA2D_ALPHAMODE(MODE)
#define | IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS)

Define Documentation

#define IS_LL_DMA2D_ALPHA ( ALPHA ) ((ALPHA) <= LL_DMA2D_COLOR)

Definition at line 74 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_ALPHAINV ( ALPHA )
Value:
(((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
                                         ((ALPHA) == LL_DMA2D_ALPHA_INVERTED))

Definition at line 87 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_ALPHAMODE ( MODE )
Value:
(((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
                                         ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE)  || \
                                         ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))

Definition at line 110 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer().

#define IS_LL_DMA2D_BLUE ( BLUE ) ((BLUE) <= LL_DMA2D_COLOR)

Definition at line 73 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_CHROMA_SUB_SAMPLING ( CSS )
Value:
(((CSS) == LL_DMA2D_CSS_444) || \
                                              ((CSS) == LL_DMA2D_CSS_422) || \
                                              ((CSS) == LL_DMA2D_CSS_420))

Definition at line 114 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer().

#define IS_LL_DMA2D_CLUTCMODE ( CLUTCMODE )
Value:
(((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
                                          ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))

Definition at line 105 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer().

#define IS_LL_DMA2D_CLUTSIZE ( SIZE ) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)

Definition at line 108 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer().

#define IS_LL_DMA2D_GREEN ( GREEN ) ((GREEN) <= LL_DMA2D_COLOR)

Definition at line 71 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_LCMODE ( MODE_ARGB )
Value:
(((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888)   || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565)   || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8)       || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44)     || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88)     || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4)       || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8)       || \
                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))

Definition at line 93 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer().

#define IS_LL_DMA2D_LINE ( LINES ) ((LINES) <= LL_DMA2D_NUMBEROFLINES)

Definition at line 81 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

#define IS_LL_DMA2D_MODE ( MODE )
Value:
(((MODE) == LL_DMA2D_MODE_M2M)                      || \
                                         ((MODE) == LL_DMA2D_MODE_M2M_PFC)                  || \
                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND)                || \
                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \
                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \
                                         ((MODE) == LL_DMA2D_MODE_R2M))

Definition at line 58 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

#define IS_LL_DMA2D_OCMODE ( MODE_ARGB )
Value:
(((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888)   || \
                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565)   || \
                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))

Definition at line 65 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigOutputColor(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), LL_DMA2D_GetOutputRedColor(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_OFFSET ( OFFSET ) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)

Definition at line 79 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_OFFSET_MODE ( MODE )
Value:
(((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \
                                         ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES))

Definition at line 76 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

#define IS_LL_DMA2D_PIXEL ( PIXELS ) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)

Definition at line 82 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

#define IS_LL_DMA2D_RBSWAP ( RBSWAP )
Value:
(((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
                                         ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))

Definition at line 90 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_RED ( RED ) ((RED) <= LL_DMA2D_COLOR)

Definition at line 72 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

#define IS_LL_DMA2D_SWAP_MODE ( MODE )
Value:
(((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \
                                         ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO))

Definition at line 84 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_DMA2D_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA2D_InitTypeDef Struct Reference
DMA2D Exported Init structures

LL DMA2D Init Structure Definition. More...

#include <stm32h7xx_ll_dma2d.h>

Data Fields

uint32_t | Mode
uint32_t | ColorMode
uint32_t | OutputBlue
uint32_t | OutputGreen
uint32_t | OutputRed
uint32_t | OutputAlpha
uint32_t | OutputMemoryAddress
uint32_t | OutputSwapMode
uint32_t | LineOffsetMode
uint32_t | LineOffset
uint32_t | NbrOfLines
uint32_t | NbrOfPixelsPerLines
uint32_t | AlphaInversionMode
uint32_t | RBSwapMode

Detailed Description

LL DMA2D Init Structure Definition.

Definition at line 64 of file stm32h7xx_ll_dma2d.h.

Field Documentation

uint32_t LL_DMA2D_InitTypeDef::AlphaInversionMode

Specifies the output alpha inversion mode.

  • This parameter can be one value of Alpha Inversion.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputAlphaInvMode().

Definition at line 145 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::ColorMode

Specifies the color format of the output image.

  • This parameter can be one value of Output Color Mode.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColorMode().

Definition at line 71 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::LineOffset

Specifies the output line offset value.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetLineOffset().

Definition at line 130 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::LineOffsetMode

Specifies the output line offset mode.

  • This parameter can be one value of Line Offset Mode.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetLineOffsetMode().

Definition at line 125 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::Mode

Specifies the DMA2D transfer mode.

  • This parameter can be one value of Mode.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetMode().

Definition at line 66 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::NbrOfLines

Specifies the number of lines of the area to be transferred.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetNbrOfLines().

Definition at line 135 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::NbrOfPixelsPerLines

Specifies the number of pixels per lines of the area to be transfered.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetNbrOfPixelsPerLines().

Definition at line 140 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputAlpha

Specifies the Alpha channel of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
  • This parameter is not considered if RGB888 or RGB565 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 106 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputBlue

Specifies the Blue value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 76 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputGreen

Specifies the Green value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 86 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputMemoryAddress

Specifies the memory address.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputMemAddr().

Definition at line 115 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputRed

Specifies the Red value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 96 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::OutputSwapMode

Specifies the output swap mode color format of the output image.

  • This parameter can be one value of Swap Mode.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputSwapMode().

Definition at line 120 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

uint32_t LL_DMA2D_InitTypeDef::RBSwapMode

Specifies the output Red Blue swap mode.

  • This parameter can be one value of Red Blue Swap.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputRBSwapMode().

Definition at line 150 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init(), and LL_DMA2D_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_dma2d.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_DMA2D_LayerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA2D_LayerCfgTypeDef Struct Reference
DMA2D Exported Init structures

LL DMA2D Layer Configuration Structure Definition. More...

#include <stm32h7xx_ll_dma2d.h>

Data Fields

uint32_t | MemoryAddress
uint32_t | LineOffset
uint32_t | ColorMode
uint32_t | CLUTColorMode
uint32_t | CLUTSize
uint32_t | AlphaMode
uint32_t | Alpha
uint32_t | Blue
uint32_t | Green
uint32_t | Red
uint32_t | CLUTMemoryAddress
uint32_t | AlphaInversionMode
uint32_t | RBSwapMode
uint32_t | ChromaSubSampling

Detailed Description

LL DMA2D Layer Configuration Structure Definition.

Definition at line 160 of file stm32h7xx_ll_dma2d.h.

Field Documentation

uint32_t LL_DMA2D_LayerCfgTypeDef::Alpha

Specifies the foreground or background Alpha value.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetAlpha() for foreground layer,
  • LL_DMA2D_BGND_SetAlpha() for background layer.

Definition at line 204 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::AlphaInversionMode

Specifies the foreground or background alpha inversion mode.

  • This parameter can be one value of Alpha Inversion.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
  • LL_DMA2D_BGND_SetAlphaInvMode() for background layer.

Definition at line 239 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::AlphaMode

Specifies the foreground or background alpha mode.

  • This parameter can be one value of Alpha Mode.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
  • LL_DMA2D_BGND_SetAlphaMode() for background layer.

Definition at line 197 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::Blue

Specifies the foreground or background Blue color value.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetBlueColor() for foreground layer,
  • LL_DMA2D_BGND_SetBlueColor() for background layer.

Definition at line 211 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::ChromaSubSampling

Configure the chroma sub-sampling mode for the YCbCr color mode This parameter is applicable for foreground layer only. This parameter can be one value of Chroma Sub Sampling

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetChrSubSampling() for foreground layer.

Definition at line 253 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::CLUTColorMode

Specifies the foreground or background CLUT color mode.

  • This parameter can be one value of CLUT Color Mode.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
  • LL_DMA2D_BGND_SetCLUTColorMode() for background layer.

Definition at line 183 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::CLUTMemoryAddress

Specifies the foreground or background CLUT memory address.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
  • LL_DMA2D_BGND_SetCLUTMemAddr() for background layer.

Definition at line 232 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::CLUTSize

Specifies the foreground or background CLUT size.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
  • LL_DMA2D_BGND_SetCLUTSize() for background layer.

Definition at line 190 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::ColorMode

Specifies the foreground or background color mode.

  • This parameter can be one value of Input Color Mode.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetColorMode() for foreground layer,
  • LL_DMA2D_BGND_SetColorMode() for background layer.

Definition at line 176 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::Green

Specifies the foreground or background Green color value.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetGreenColor() for foreground layer,
  • LL_DMA2D_BGND_SetGreenColor() for background layer.

Definition at line 218 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::LineOffset

Specifies the foreground or background line offset value.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetLineOffset() for foreground layer,
  • LL_DMA2D_BGND_SetLineOffset() for background layer.

Definition at line 169 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::MemoryAddress

Specifies the foreground or background memory address.

  • This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetMemAddr() for foreground layer,
  • LL_DMA2D_BGND_SetMemAddr() for background layer.

Definition at line 162 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::RBSwapMode

Specifies the foreground or background Red Blue swap mode. This parameter can be one value of Red Blue Swap .

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
  • LL_DMA2D_BGND_SetRBSwapMode() for background layer.

Definition at line 246 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

uint32_t LL_DMA2D_LayerCfgTypeDef::Red

Specifies the foreground or background Red color value.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This parameter can be modified afterwards using unitary functions

  • LL_DMA2D_FGND_SetRedColor() for foreground layer,
  • LL_DMA2D_BGND_SetRedColor() for background layer.

Definition at line 225 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer(), and LL_DMA2D_LayerCfgStructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_dma2d.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_DMA2D_ColorTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA2D_ColorTypeDef Struct Reference
DMA2D Exported Init structures

LL DMA2D Output Color Structure Definition. More...

#include <stm32h7xx_ll_dma2d.h>

Data Fields

uint32_t | ColorMode
uint32_t | OutputBlue
uint32_t | OutputGreen
uint32_t | OutputRed
uint32_t | OutputAlpha

Detailed Description

LL DMA2D Output Color Structure Definition.

Definition at line 265 of file stm32h7xx_ll_dma2d.h.

Field Documentation

uint32_t LL_DMA2D_ColorTypeDef::ColorMode

Specifies the color format of the output image.

  • This parameter can be one value of Output Color Mode.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColorMode().

Definition at line 267 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

uint32_t LL_DMA2D_ColorTypeDef::OutputAlpha

Specifies the Alpha channel of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
  • This parameter is not considered if RGB888 or RGB565 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 302 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

uint32_t LL_DMA2D_ColorTypeDef::OutputBlue

Specifies the Blue value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 272 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

uint32_t LL_DMA2D_ColorTypeDef::OutputGreen

Specifies the Green value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 282 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

uint32_t LL_DMA2D_ColorTypeDef::OutputRed

Specifies the Red value of the output image.

  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
  • This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

This parameter can be modified afterwards using unitary function LL_DMA2D_SetOutputColor() or configuration function LL_DMA2D_ConfigOutputColor().

Definition at line 292 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), and LL_DMA2D_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_dma2d.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA2D Exported Constants

Flags defines which can be used with LL_DMA2D_ReadReg function. More...

Defines

#define | LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF
#define | LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF
#define | LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF
#define | LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF
#define | LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF
#define | LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF

Detailed Description

Flags defines which can be used with LL_DMA2D_ReadReg function.

Define Documentation

#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF

CLUT Access Error Interrupt Flag

Definition at line 329 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF

Configuration Error Interrupt Flag

Definition at line 327 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF

CLUT Transfer Complete Interrupt Flag

Definition at line 328 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF

Transfer Complete Interrupt Flag

Definition at line 331 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF

Transfer Error Interrupt Flag

Definition at line 332 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF

Transfer Watermark Interrupt Flag

Definition at line 330 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
DMA2D Exported Constants

IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions. More...

Defines

#define | LL_DMA2D_IT_CEIE DMA2D_CR_CEIE
#define | LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE
#define | LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE
#define | LL_DMA2D_IT_TWIE DMA2D_CR_TWIE
#define | LL_DMA2D_IT_TCIE DMA2D_CR_TCIE
#define | LL_DMA2D_IT_TEIE DMA2D_CR_TEIE

Detailed Description

IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions.

Define Documentation

#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE

CLUT Access Error Interrupt

Definition at line 343 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE

Configuration Error Interrupt

Definition at line 341 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE

CLUT Transfer Complete Interrupt

Definition at line 342 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE

Transfer Complete Interrupt

Definition at line 345 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE

Transfer Error Interrupt

Definition at line 346 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE

Transfer Watermark Interrupt

Definition at line 344 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Mode

Defines
Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_MODE_M2M 0x00000000U
#define | LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0
#define | LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1
#define | LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1)
#define | LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2
#define | LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2)

Define Documentation

#define LL_DMA2D_MODE_M2M 0x00000000U

DMA2D memory to memory transfer mode

Definition at line 354 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_StructInit().

#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1

DMA2D memory to memory with blending transfer mode

Definition at line 356 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2)

DMA2D memory to memory with blending transfer mode and fixed color background

Definition at line 359 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2

DMA2D memory to memory with blending transfer mode and fixed color foreground

Definition at line 358 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0

DMA2D memory to memory with pixel format conversion transfer mode

Definition at line 355 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1)

DMA2D register to memory transfer mode

Definition at line 357 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Output Color Mode

Defines
Output Color Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0
#define | LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1
#define | LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
#define | LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2

Define Documentation

#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)

ARGB1555

Definition at line 370 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), and LL_DMA2D_GetOutputRedColor().

#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2

ARGB4444

Definition at line 371 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U

ARGB8888

Definition at line 367 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), LL_DMA2D_GetOutputRedColor(), and LL_DMA2D_StructInit().

#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1

RGB565

Definition at line 369 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), and LL_DMA2D_GetOutputRedColor().

#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0

RGB888

Definition at line 368 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), and LL_DMA2D_GetOutputRedColor().

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STM32H7B3xQ HAL User Manual: Input Color Mode

Defines
Input Color Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0
#define | LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1
#define | LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)
#define | LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2
#define | LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3
#define | LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)
#define | LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
#define | LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)

Define Documentation

#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)

A4

Definition at line 389 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)

A8

Definition at line 388 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)

AL44

Definition at line 385 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)

AL88

Definition at line 386 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)

ARGB1555

Definition at line 382 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2

ARGB4444

Definition at line 383 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U

ARGB8888

Definition at line 379 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit().

#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3

L4

Definition at line 387 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)

L8

Definition at line 384 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1

RGB565

Definition at line 381 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0

RGB888

Definition at line 380 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)

YCbCr

Definition at line 390 of file stm32h7xx_ll_dma2d.h.

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STM32H7B3xQ HAL User Manual: Alpha Mode

Defines
Alpha Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U
#define | LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0
#define | LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1

Define Documentation

#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1

Replace original alpha channel value by programmed alpha value with original alpha channel value

Definition at line 400 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U

No modification of the alpha channel value

Definition at line 398 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit().

#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0

Replace original alpha channel value by programmed alpha value

Definition at line 399 of file stm32h7xx_ll_dma2d.h.

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STM32H7B3xQ HAL User Manual: Swap Mode

Defines
Swap Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U
#define | LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB

Define Documentation

#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U

Regular order

Definition at line 409 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_StructInit().

#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB

Bytes swapped two by two

Definition at line 410 of file stm32h7xx_ll_dma2d.h.

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STM32H7B3xQ HAL User Manual: Red Blue Swap

Defines
Red Blue Swap
DMA2D Exported Constants

Defines

#define | LL_DMA2D_RB_MODE_REGULAR 0x00000000U
#define | LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS

Define Documentation

#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U

RGB or ARGB

Definition at line 418 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit(), and LL_DMA2D_StructInit().

#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS

BGR or ABGR

Definition at line 419 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Alpha Inversion

Defines
Alpha Inversion
DMA2D Exported Constants

Defines

#define | LL_DMA2D_ALPHA_REGULAR 0x00000000U
#define | LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI

Define Documentation

#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI

Inverted alpha

Definition at line 428 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_ALPHA_REGULAR 0x00000000U

Regular alpha

Definition at line 427 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit(), and LL_DMA2D_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Line Offset Mode

Defines
Line Offset Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U
#define | LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM

Define Documentation

#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM

Line offsets are expressed in bytes

Definition at line 438 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U

Line offsets are expressed in pixels

Definition at line 437 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_StructInit().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CLUT Color Mode

Defines
CLUT Color Mode
DMA2D Exported Constants

Defines

#define | LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM

Define Documentation

#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U

ARGB8888

Definition at line 446 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit().

#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM

RGB888

Definition at line 447 of file stm32h7xx_ll_dma2d.h.

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STM32H7B3xQ HAL User Manual: Chroma Sub Sampling

Defines
Chroma Sub Sampling
DMA2D Exported Constants

Defines

#define | LL_DMA2D_CSS_444 0x00000000U
#define | LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0
#define | LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1

Define Documentation

#define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1

chroma sub-sampling 4:2:0

Definition at line 457 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0

chroma sub-sampling 4:2:2

Definition at line 456 of file stm32h7xx_ll_dma2d.h.

#define LL_DMA2D_CSS_444 0x00000000U

No chroma sub-sampling 4:4:4

Definition at line 455 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_LayerCfgStructInit().

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
DMA2D Exported Macros

Defines

#define | LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in DMA2D register.
#define | LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in DMA2D register.

Define Documentation

#define LL_DMA2D_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in DMA2D register.

Parameters:
__INSTANCE__ | DMA2D Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 490 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_BGND_GetCLUTMemAddr(), LL_DMA2D_BGND_GetMemAddr(), LL_DMA2D_FGND_GetCLUTMemAddr(), LL_DMA2D_FGND_GetMemAddr(), and LL_DMA2D_GetOutputMemAddr().

#define LL_DMA2D_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in DMA2D register.

Parameters:
__INSTANCE__ | DMA2D Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 482 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_BGND_SetCLUTMemAddr(), LL_DMA2D_BGND_SetMemAddr(), LL_DMA2D_FGND_SetCLUTMemAddr(), LL_DMA2D_FGND_SetMemAddr(), and LL_DMA2D_SetOutputMemAddr().

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STM32H7B3xQ HAL User Manual: Foreground Configuration Functions

Functions
Foreground Configuration Functions
Configuration Functions

Functions

__STATIC_INLINE void | LL_DMA2D_FGND_SetMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_EnableCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D foreground CLUT loading.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_IsEnabledCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D foreground CLUT loading is enabled.
__STATIC_INLINE void | LL_DMA2D_FGND_SetColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D foreground color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground color mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlphaMode (DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D foreground alpha mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlphaMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlpha (DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlpha (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D foreground Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D foreground alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetRedColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetGreenColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetBlueColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTSize (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTSize (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D foreground CLUT color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground CLUT color mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetChrSubSampling (DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetChrSubSampling (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).

Function Documentation

__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad ( DMA2D_TypeDef * DMA2Dx )

Enable DMA2D foreground CLUT loading.

Reference Manual to LL API cross reference:
FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1012 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
Parameters:
DMA2Dx DMA2D Instance
Return values:
Alpha value between Min_Data=0 and Max_Data=0xFF

Definition at line 1120 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground alpha inversion mode.

Reference Manual to LL API cross reference:
FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED

Definition at line 1174 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground alpha mode.

Reference Manual to LL API cross reference:
FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_ALPHA_MODE_NO_MODIF
  • LL_DMA2D_ALPHA_MODE_REPLACE
  • LL_DMA2D_ALPHA_MODE_COMBINE

Definition at line 1097 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Blue color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1283 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).

Reference Manual to LL API cross reference:
FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_CSS_444
  • LL_DMA2D_CSS_422
  • LL_DMA2D_CSS_420

Definition at line 1385 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground CLUT color mode.

Reference Manual to LL API cross reference:
FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888

Definition at line 1356 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
Parameters:
DMA2Dx DMA2D Instance
Return values:
Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 1306 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_ReadReg.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
Parameters:
DMA2Dx DMA2D Instance
Return values:
Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF

Definition at line 1329 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground color mode.

Reference Manual to LL API cross reference:
FGPFCCR CM LL_DMA2D_FGND_GetColorMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_INPUT_MODE_ARGB8888
  • LL_DMA2D_INPUT_MODE_RGB888
  • LL_DMA2D_INPUT_MODE_RGB565
  • LL_DMA2D_INPUT_MODE_ARGB1555
  • LL_DMA2D_INPUT_MODE_ARGB4444
  • LL_DMA2D_INPUT_MODE_L8
  • LL_DMA2D_INPUT_MODE_AL44
  • LL_DMA2D_INPUT_MODE_AL88
  • LL_DMA2D_INPUT_MODE_L4
  • LL_DMA2D_INPUT_MODE_A8
  • LL_DMA2D_INPUT_MODE_A4

Definition at line 1068 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Green color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1260 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
FGOR LO LL_DMA2D_FGND_GetLineOffset
Parameters:
DMA2Dx DMA2D Instance
Return values:
Foreground line offset value between Min_Data=0 and Max_Data=0x3FF

Definition at line 1197 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
FGMAR MA LL_DMA2D_FGND_GetMemAddr
Parameters:
DMA2Dx DMA2D Instance
Return values:
Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 1001 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_ReadReg.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground Red Blue swap mode.

Reference Manual to LL API cross reference:
FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP

Definition at line 1147 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR RED LL_DMA2D_FGND_GetRedColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Red color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1237 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad ( DMA2D_TypeDef * DMA2Dx )

Indicate if DMA2D foreground CLUT loading is enabled.

Reference Manual to LL API cross reference:
FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1023 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init().

__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Alpha
 | ) |  |

Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
Parameters:
DMA2Dx | DMA2D Instance
Alpha | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1109 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | AlphaInversionMode
 | ) |  |

Set DMA2D foreground alpha inversion mode.

Reference Manual to LL API cross reference:
FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
AlphaInversionMode This parameter can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED
Return values:
None

Definition at line 1161 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | AphaMode
 | ) |  |

Set DMA2D foreground alpha mode.

Reference Manual to LL API cross reference:
FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
Parameters:
DMA2Dx DMA2D Instance
AphaMode This parameter can be one of the following values:
  • LL_DMA2D_ALPHA_MODE_NO_MODIF
  • LL_DMA2D_ALPHA_MODE_REPLACE
  • LL_DMA2D_ALPHA_MODE_COMBINE
Return values:
None

Definition at line 1083 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Blue
 | ) |  |

Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
Parameters:
DMA2Dx | DMA2D Instance
Blue | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1272 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ChromaSubSampling
 | ) |  |

Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).

Reference Manual to LL API cross reference:
FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling
Parameters:
DMA2Dx DMA2D Instance
ChromaSubSampling This parameter can be one of the following values:
  • LL_DMA2D_CSS_444
  • LL_DMA2D_CSS_422
  • LL_DMA2D_CSS_420
Return values:
None

Definition at line 1371 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTColorMode
 | ) |  |

Set DMA2D foreground CLUT color mode.

Reference Manual to LL API cross reference:
FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
Parameters:
DMA2Dx DMA2D Instance
CLUTColorMode This parameter can be one of the following values:
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888
Return values:
None

Definition at line 1343 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTMemoryAddress
 | ) |  |

Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
Parameters:
DMA2Dx | DMA2D Instance
CLUTMemoryAddress | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 1295 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_WriteReg.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTSize
 | ) |  |

Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
Parameters:
DMA2Dx | DMA2D Instance
CLUTSize | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1318 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Red,
 |  | uint32_t | Green,
 |  | uint32_t | Blue
 | ) |  |

Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).

Reference Manual to LL API cross reference:
FGCOLR RED LL_DMA2D_FGND_SetColor
Reference Manual to LL API cross reference:
FGCOLR GREEN LL_DMA2D_FGND_SetColor
Reference Manual to LL API cross reference:
FGCOLR BLUE LL_DMA2D_FGND_SetColor
Parameters:
DMA2Dx | DMA2D Instance
Red | Value between Min_Data=0 and Max_Data=0xFF
Green | Value between Min_Data=0 and Max_Data=0xFF
Blue | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1213 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Set DMA2D foreground color mode.

Reference Manual to LL API cross reference:
FGPFCCR CM LL_DMA2D_FGND_SetColorMode
Parameters:
DMA2Dx DMA2D Instance
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_INPUT_MODE_ARGB8888
  • LL_DMA2D_INPUT_MODE_RGB888
  • LL_DMA2D_INPUT_MODE_RGB565
  • LL_DMA2D_INPUT_MODE_ARGB1555
  • LL_DMA2D_INPUT_MODE_ARGB4444
  • LL_DMA2D_INPUT_MODE_L8
  • LL_DMA2D_INPUT_MODE_AL44
  • LL_DMA2D_INPUT_MODE_AL88
  • LL_DMA2D_INPUT_MODE_L4
  • LL_DMA2D_INPUT_MODE_A8
  • LL_DMA2D_INPUT_MODE_A4
Return values:
None

Definition at line 1046 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Green
 | ) |  |

Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
Parameters:
DMA2Dx | DMA2D Instance
Green | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1249 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | LineOffset
 | ) |  |

Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
FGOR LO LL_DMA2D_FGND_SetLineOffset
Parameters:
DMA2Dx | DMA2D Instance
LineOffset | Value between Min_Data=0 and Max_Data=0x3FF
Return values:
None

Definition at line 1186 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
FGMAR MA LL_DMA2D_FGND_SetMemAddr
Parameters:
DMA2Dx | DMA2D Instance
MemoryAddress | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 990 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_WriteReg.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | RBSwapMode
 | ) |  |

Set DMA2D foreground Red Blue swap mode.

Reference Manual to LL API cross reference:
FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
RBSwapMode This parameter can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP
Return values:
None

Definition at line 1134 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Red
 | ) |  |

Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
FGCOLR RED LL_DMA2D_FGND_SetRedColor
Parameters:
DMA2Dx | DMA2D Instance
Red | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1226 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Background Configuration Functions

Functions
Background Configuration Functions
Configuration Functions

Functions

__STATIC_INLINE void | LL_DMA2D_BGND_SetMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_EnableCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D background CLUT loading.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_IsEnabledCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D background CLUT loading is enabled.
__STATIC_INLINE void | LL_DMA2D_BGND_SetColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D background color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background color mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlphaMode (DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D background alpha mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlphaMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlpha (DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlpha (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D background Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D background alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetRedColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetGreenColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetBlueColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTSize (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTSize (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D background CLUT color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background CLUT color mode.

Function Documentation

__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad ( DMA2D_TypeDef * DMA2Dx )

Enable DMA2D background CLUT loading.

Reference Manual to LL API cross reference:
BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1426 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
Parameters:
DMA2Dx DMA2D Instance
Return values:
Alpha value between Min_Data=0 and Max_Data=0xFF

Definition at line 1534 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background alpha inversion mode.

Reference Manual to LL API cross reference:
BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED

Definition at line 1588 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background alpha mode.

Reference Manual to LL API cross reference:
BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_ALPHA_MODE_NO_MODIF
  • LL_DMA2D_ALPHA_MODE_REPLACE
  • LL_DMA2D_ALPHA_MODE_COMBINE

Definition at line 1511 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Blue color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1697 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background CLUT color mode.

Reference Manual to LL API cross reference:
BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888

Definition at line 1770 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
Parameters:
DMA2Dx DMA2D Instance
Return values:
Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 1720 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_ReadReg.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
Parameters:
DMA2Dx DMA2D Instance
Return values:
Background CLUT size value between Min_Data=0 and Max_Data=0xFF

Definition at line 1743 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background color mode.

Reference Manual to LL API cross reference:
BGPFCCR CM LL_DMA2D_BGND_GetColorMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_INPUT_MODE_ARGB8888
  • LL_DMA2D_INPUT_MODE_RGB888
  • LL_DMA2D_INPUT_MODE_RGB565
  • LL_DMA2D_INPUT_MODE_ARGB1555
  • LL_DMA2D_INPUT_MODE_ARGB4444
  • LL_DMA2D_INPUT_MODE_L8
  • LL_DMA2D_INPUT_MODE_AL44
  • LL_DMA2D_INPUT_MODE_AL88
  • LL_DMA2D_INPUT_MODE_L4
  • LL_DMA2D_INPUT_MODE_A8
  • LL_DMA2D_INPUT_MODE_A4

Definition at line 1482 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Green color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1674 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
BGOR LO LL_DMA2D_BGND_GetLineOffset
Parameters:
DMA2Dx DMA2D Instance
Return values:
Background line offset value between Min_Data=0 and Max_Data=0x3FF

Definition at line 1611 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
BGMAR MA LL_DMA2D_BGND_GetMemAddr
Parameters:
DMA2Dx DMA2D Instance
Return values:
Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 1415 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_ReadReg.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background Red Blue swap mode.

Reference Manual to LL API cross reference:
BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP

Definition at line 1561 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR RED LL_DMA2D_BGND_GetRedColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Red color value between Min_Data=0 and Max_Data=0xFF

Definition at line 1651 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad ( DMA2D_TypeDef * DMA2Dx )

Indicate if DMA2D background CLUT loading is enabled.

Reference Manual to LL API cross reference:
BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1437 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init().

__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Alpha
 | ) |  |

Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
Parameters:
DMA2Dx | DMA2D Instance
Alpha | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1523 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | AlphaInversionMode
 | ) |  |

Set DMA2D background alpha inversion mode.

Reference Manual to LL API cross reference:
BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
AlphaInversionMode This parameter can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED
Return values:
None

Definition at line 1575 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | AphaMode
 | ) |  |

Set DMA2D background alpha mode.

Reference Manual to LL API cross reference:
BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
Parameters:
DMA2Dx DMA2D Instance
AphaMode This parameter can be one of the following values:
  • LL_DMA2D_ALPHA_MODE_NO_MODIF
  • LL_DMA2D_ALPHA_MODE_REPLACE
  • LL_DMA2D_ALPHA_MODE_COMBINE
Return values:
None

Definition at line 1497 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Blue
 | ) |  |

Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
Parameters:
DMA2Dx | DMA2D Instance
Blue | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1686 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTColorMode
 | ) |  |

Set DMA2D background CLUT color mode.

Reference Manual to LL API cross reference:
BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
Parameters:
DMA2Dx DMA2D Instance
CLUTColorMode This parameter can be one of the following values:
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888
Return values:
None

Definition at line 1757 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTMemoryAddress
 | ) |  |

Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
Parameters:
DMA2Dx | DMA2D Instance
CLUTMemoryAddress | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 1709 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_WriteReg.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | CLUTSize
 | ) |  |

Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
Parameters:
DMA2Dx | DMA2D Instance
CLUTSize | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1732 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Red,
 |  | uint32_t | Green,
 |  | uint32_t | Blue
 | ) |  |

Set DMA2D background color values, expressed on 24 bits ([23:0] bits).

Reference Manual to LL API cross reference:
BGCOLR RED LL_DMA2D_BGND_SetColor
Reference Manual to LL API cross reference:
BGCOLR GREEN LL_DMA2D_BGND_SetColor
Reference Manual to LL API cross reference:
BGCOLR BLUE LL_DMA2D_BGND_SetColor
Parameters:
DMA2Dx | DMA2D Instance
Red | Value between Min_Data=0 and Max_Data=0xFF
Green | Value between Min_Data=0 and Max_Data=0xFF
Blue | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1627 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Set DMA2D background color mode.

Reference Manual to LL API cross reference:
BGPFCCR CM LL_DMA2D_BGND_SetColorMode
Parameters:
DMA2Dx DMA2D Instance
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_INPUT_MODE_ARGB8888
  • LL_DMA2D_INPUT_MODE_RGB888
  • LL_DMA2D_INPUT_MODE_RGB565
  • LL_DMA2D_INPUT_MODE_ARGB1555
  • LL_DMA2D_INPUT_MODE_ARGB4444
  • LL_DMA2D_INPUT_MODE_L8
  • LL_DMA2D_INPUT_MODE_AL44
  • LL_DMA2D_INPUT_MODE_AL88
  • LL_DMA2D_INPUT_MODE_L4
  • LL_DMA2D_INPUT_MODE_A8
  • LL_DMA2D_INPUT_MODE_A4
Return values:
None

Definition at line 1460 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Green
 | ) |  |

Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
Parameters:
DMA2Dx | DMA2D Instance
Green | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1663 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | LineOffset
 | ) |  |

Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
BGOR LO LL_DMA2D_BGND_SetLineOffset
Parameters:
DMA2Dx | DMA2D Instance
LineOffset | Value between Min_Data=0 and Max_Data=0x3FF
Return values:
None

Definition at line 1600 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
BGMAR MA LL_DMA2D_BGND_SetMemAddr
Parameters:
DMA2Dx | DMA2D Instance
MemoryAddress | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 1404 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_WriteReg.

Referenced by LL_DMA2D_ConfigLayer().

__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | RBSwapMode
 | ) |  |

Set DMA2D background Red Blue swap mode.

Reference Manual to LL API cross reference:
BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
RBSwapMode This parameter can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP
Return values:
None

Definition at line 1548 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Red
 | ) |  |

Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
BGCOLR RED LL_DMA2D_BGND_SetRedColor
Parameters:
DMA2Dx | DMA2D Instance
Red | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 1640 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration Functions

Modules | Functions
Configuration Functions
DMA2D Exported Functions

Modules

Foreground Configuration Functions
Background Configuration Functions

Functions

__STATIC_INLINE void | LL_DMA2D_Start (DMA2D_TypeDef *DMA2Dx)
Start a DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsTransferOngoing (DMA2D_TypeDef *DMA2Dx)
Indicate if a DMA2D transfer is ongoing.
__STATIC_INLINE void | LL_DMA2D_Suspend (DMA2D_TypeDef *DMA2Dx)
Suspend DMA2D transfer.
__STATIC_INLINE void | LL_DMA2D_Resume (DMA2D_TypeDef *DMA2Dx)
Resume DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsSuspended (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is suspended.
__STATIC_INLINE void | LL_DMA2D_Abort (DMA2D_TypeDef *DMA2Dx)
Abort DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsAborted (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is aborted.
__STATIC_INLINE void | LL_DMA2D_SetMode (DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
Set DMA2D mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D output color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output color mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D output Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D output alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
Set DMA2D output swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output swap mode.
__STATIC_INLINE void | LL_DMA2D_SetLineOffsetMode (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
Set DMA2D line offset mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineOffsetMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset mode.
__STATIC_INLINE void | LL_DMA2D_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetNbrOfPixelsPerLines (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetNbrOfPixelsPerLines (DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
__STATIC_INLINE void | LL_DMA2D_SetNbrOfLines (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetNbrOfLines (DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetOutputMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetOutputColor (DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
Set DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputColor (DMA2D_TypeDef *DMA2Dx)
Get DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetLineWatermark (DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineWatermark (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetDeadTime (DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetDeadTime (DMA2D_TypeDef *DMA2Dx)
Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_EnableDeadTime (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D dead time functionality.
__STATIC_INLINE void | LL_DMA2D_DisableDeadTime (DMA2D_TypeDef *DMA2Dx)
Disable DMA2D dead time functionality.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledDeadTime (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D dead time functionality is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA2D_Abort ( DMA2D_TypeDef * DMA2Dx )

Abort DMA2D transfer.

Note:
This API can be used to abort automatic foreground or background CLUT loading.
Reference Manual to LL API cross reference:
CR ABORT LL_DMA2D_Abort
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 574 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableDeadTime ( DMA2D_TypeDef * DMA2Dx )

Disable DMA2D dead time functionality.

Reference Manual to LL API cross reference:
AMTCR EN LL_DMA2D_DisableDeadTime
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 963 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableDeadTime ( DMA2D_TypeDef * DMA2Dx )

Enable DMA2D dead time functionality.

Reference Manual to LL API cross reference:
AMTCR EN LL_DMA2D_EnableDeadTime
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 952 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D dead time, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
AMTCR DT LL_DMA2D_GetDeadTime
Parameters:
DMA2Dx DMA2D Instance
Return values:
Dead time value between Min_Data=0 and Max_Data=0xFF

Definition at line 941 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
OOR LO LL_DMA2D_GetLineOffset
Parameters:
DMA2Dx DMA2D Instance
Return values:
Line offset value between Min_Data=0 and Max_Data=0xFFFF

Definition at line 788 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D line offset mode.

Reference Manual to LL API cross reference:
CR LOM LL_DMA2D_GetLineOffsetMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_LINE_OFFSET_PIXELS
  • LL_DMA2D_LINE_OFFSET_BYTES

Definition at line 764 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).

Reference Manual to LL API cross reference:
LWR LW LL_DMA2D_GetLineWatermark
Parameters:
DMA2Dx DMA2D Instance
Return values:
Line watermark value between Min_Data=0 and Max_Data=0xFFFF

Definition at line 918 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D mode.

Reference Manual to LL API cross reference:
CR MODE LL_DMA2D_GetMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_MODE_M2M
  • LL_DMA2D_MODE_M2M_PFC
  • LL_DMA2D_MODE_M2M_BLEND
  • LL_DMA2D_MODE_R2M
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG

Definition at line 622 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).

Reference Manual to LL API cross reference:
NLR NL LL_DMA2D_GetNbrOfLines
Parameters:
DMA2Dx DMA2D Instance
Return values:
Number of lines value between Min_Data=0 and Max_Data=0xFFFF

Definition at line 834 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)

Reference Manual to LL API cross reference:
NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
Parameters:
DMA2Dx DMA2D Instance
Return values:
Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF

Definition at line 811 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D output alpha inversion mode.

Reference Manual to LL API cross reference:
OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED

Definition at line 709 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D output color, expressed on 32 bits ([31:0] bits).

Note:
Alpha channel and red, green, blue color values must be retrieved from the returned value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) as set by LL_DMA2D_SetOutputColorMode.
Reference Manual to LL API cross reference:
OCOLR BLUE LL_DMA2D_GetOutputColor
OCOLR GREEN LL_DMA2D_GetOutputColor
OCOLR RED LL_DMA2D_GetOutputColor
OCOLR ALPHA LL_DMA2D_GetOutputColor
Parameters:
DMA2Dx DMA2D Instance
Return values:
Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 894 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D output color mode.

Reference Manual to LL API cross reference:
OPFCCR CM LL_DMA2D_GetOutputColorMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444

Definition at line 655 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr ( DMA2D_TypeDef * DMA2Dx )

Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
OMAR MA LL_DMA2D_GetOutputMemAddr
Parameters:
DMA2Dx DMA2D Instance
Return values:
Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 857 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_ReadReg.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D output Red Blue swap mode.

Reference Manual to LL API cross reference:
OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP

Definition at line 682 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode ( DMA2D_TypeDef * DMA2Dx )

Return DMA2D output swap mode.

Reference Manual to LL API cross reference:
OPFCCR SB LL_DMA2D_GetOutputSwapMode
Parameters:
DMA2Dx DMA2D Instance
Return values:
Returned value can be one of the following values:
  • LL_DMA2D_SWAP_MODE_REGULAR
  • LL_DMA2D_SWAP_MODE_TWO_BY_TWO

Definition at line 737 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsAborted ( DMA2D_TypeDef * DMA2Dx )

Indicate if DMA2D transfer is aborted.

Note:
This API can be used to indicate whether or not automatic foreground or background CLUT loading is aborted.
Reference Manual to LL API cross reference:
CR ABORT LL_DMA2D_IsAborted
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 587 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime ( DMA2D_TypeDef * DMA2Dx )

Indicate if DMA2D dead time functionality is enabled.

Reference Manual to LL API cross reference:
AMTCR EN LL_DMA2D_IsEnabledDeadTime
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 974 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended ( DMA2D_TypeDef * DMA2Dx )

Indicate if DMA2D transfer is suspended.

Note:
This API can be used to indicate whether or not automatic foreground or background CLUT loading is suspended.
Reference Manual to LL API cross reference:
CR SUSP LL_DMA2D_IsSuspended
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 562 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing ( DMA2D_TypeDef * DMA2Dx )

Indicate if a DMA2D transfer is ongoing.

Reference Manual to LL API cross reference:
CR START LL_DMA2D_IsTransferOngoing
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 525 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init().

__STATIC_INLINE void LL_DMA2D_Resume ( DMA2D_TypeDef * DMA2Dx )

Resume DMA2D transfer.

Note:
This API can be used to resume automatic foreground or background CLUT loading.
Reference Manual to LL API cross reference:
CR SUSP LL_DMA2D_Resume
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 549 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetDeadTime | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | DeadTime
 | ) |  |

Set DMA2D dead time, expressed on 8 bits ([7:0] bits).

Reference Manual to LL API cross reference:
AMTCR DT LL_DMA2D_SetDeadTime
Parameters:
DMA2Dx | DMA2D Instance
DeadTime | Value between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 930 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetLineOffset | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | LineOffset
 | ) |  |

Set DMA2D line offset, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
OOR LO LL_DMA2D_SetLineOffset
Parameters:
DMA2Dx | DMA2D Instance
LineOffset | Value between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 776 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_Init().

__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | LineOffsetMode
 | ) |  |

Set DMA2D line offset mode.

Reference Manual to LL API cross reference:
CR LOM LL_DMA2D_SetLineOffsetMode
Parameters:
DMA2Dx DMA2D Instance
LineOffsetMode This parameter can be one of the following values:
  • LL_DMA2D_LINE_OFFSET_PIXELS
  • LL_DMA2D_LINE_OFFSET_BYTES
Return values:
None

Definition at line 751 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetLineWatermark | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | LineWatermark
 | ) |  |

Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).

Reference Manual to LL API cross reference:
LWR LW LL_DMA2D_SetLineWatermark
Parameters:
DMA2Dx | DMA2D Instance
LineWatermark | Value between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 907 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | Mode
 | ) |  |

Set DMA2D mode.

Reference Manual to LL API cross reference:
CR MODE LL_DMA2D_SetMode
Parameters:
DMA2Dx DMA2D Instance
Mode This parameter can be one of the following values:
  • LL_DMA2D_MODE_M2M
  • LL_DMA2D_MODE_M2M_PFC
  • LL_DMA2D_MODE_M2M_BLEND
  • LL_DMA2D_MODE_R2M
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
Return values:
None

Definition at line 605 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetNbrOfLines | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | NbrOfLines
 | ) |  |

Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).

Reference Manual to LL API cross reference:
NLR NL LL_DMA2D_SetNbrOfLines
Parameters:
DMA2Dx | DMA2D Instance
NbrOfLines | Value between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 823 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | NbrOfPixelsPerLines
 | ) |  |

Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).

Reference Manual to LL API cross reference:
NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
Parameters:
DMA2Dx | DMA2D Instance
NbrOfPixelsPerLines | Value between Min_Data=0 and Max_Data=0x3FFF
Return values:
None

Definition at line 800 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | AlphaInversionMode
 | ) |  |

Set DMA2D output alpha inversion mode.

Reference Manual to LL API cross reference:
OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
Parameters:
DMA2Dx DMA2D Instance
AlphaInversionMode This parameter can be one of the following values:
  • LL_DMA2D_ALPHA_REGULAR
  • LL_DMA2D_ALPHA_INVERTED
Return values:
None

Definition at line 696 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetOutputColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | OutputColor
 | ) |  |

Set DMA2D output color, expressed on 32 bits ([31:0] bits).

Note:
Output color format depends on output color mode, ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444.
LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting with respect to color mode is not done by the user code.
Reference Manual to LL API cross reference:
OCOLR BLUE LL_DMA2D_SetOutputColor
OCOLR GREEN LL_DMA2D_SetOutputColor
OCOLR RED LL_DMA2D_SetOutputColor
OCOLR ALPHA LL_DMA2D_SetOutputColor
Parameters:
DMA2Dx | DMA2D Instance
OutputColor | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 876 of file stm32h7xx_ll_dma2d.h.

Referenced by LL_DMA2D_ConfigOutputColor().

__STATIC_INLINE void LL_DMA2D_SetOutputColorMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Set DMA2D output color mode.

Reference Manual to LL API cross reference:
OPFCCR CM LL_DMA2D_SetOutputColorMode
Parameters:
DMA2Dx DMA2D Instance
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444
Return values:
None

Definition at line 639 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | OutputMemoryAddress
 | ) |  |

Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).

Reference Manual to LL API cross reference:
OMAR MA LL_DMA2D_SetOutputMemAddr
Parameters:
DMA2Dx | DMA2D Instance
OutputMemoryAddress | Value between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 846 of file stm32h7xx_ll_dma2d.h.

References LL_DMA2D_WriteReg.

Referenced by LL_DMA2D_Init().

__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | RBSwapMode
 | ) |  |

Set DMA2D output Red Blue swap mode.

Reference Manual to LL API cross reference:
OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
Parameters:
DMA2Dx DMA2D Instance
RBSwapMode This parameter can be one of the following values:
  • LL_DMA2D_RB_MODE_REGULAR
  • LL_DMA2D_RB_MODE_SWAP
Return values:
None

Definition at line 669 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | OutputSwapMode
 | ) |  |

Set DMA2D output swap mode.

Reference Manual to LL API cross reference:
OPFCCR SB LL_DMA2D_SetOutputSwapMode
Parameters:
DMA2Dx DMA2D Instance
OutputSwapMode This parameter can be one of the following values:
  • LL_DMA2D_SWAP_MODE_REGULAR
  • LL_DMA2D_SWAP_MODE_TWO_BY_TWO
Return values:
None

Definition at line 724 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_Start ( DMA2D_TypeDef * DMA2Dx )

Start a DMA2D transfer.

Reference Manual to LL API cross reference:
CR START LL_DMA2D_Start
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 514 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_Suspend ( DMA2D_TypeDef * DMA2Dx )

Suspend DMA2D transfer.

Note:
This API can be used to suspend automatic foreground or background CLUT loading.
Reference Manual to LL API cross reference:
CR SUSP LL_DMA2D_Suspend
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 537 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Flag Management

Functions
Flag Management
DMA2D Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CTC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CAE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TW (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error Interrupt Flag is set or not.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Configuration Error Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CTC (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Transfer Complete Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CAE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Access Error Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TW (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Watermark Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TC (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Complete Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Error Interrupt Flag.

Function Documentation

__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D CLUT Access Error Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CAECIF LL_DMA2D_ClearFlag_CAE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1882 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_ClearFlag_CE ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D Configuration Error Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CCEIF LL_DMA2D_ClearFlag_CE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1860 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D CLUT Transfer Complete Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1871 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_ClearFlag_TC ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D Transfer Complete Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CTCIF LL_DMA2D_ClearFlag_TC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1904 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_ClearFlag_TE ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D Transfer Error Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CTEIF LL_DMA2D_ClearFlag_TE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1915 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_ClearFlag_TW ( DMA2D_TypeDef * DMA2Dx )

Clear DMA2D Transfer Watermark Interrupt Flag.

Reference Manual to LL API cross reference:
IFCR CTWIF LL_DMA2D_ClearFlag_TW
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1893 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D CLUT Access Error Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1816 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Configuration Error Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CEIF LL_DMA2D_IsActiveFlag_CE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1794 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1805 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Complete Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR TCIF LL_DMA2D_IsActiveFlag_TC
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1838 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Error Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEIF LL_DMA2D_IsActiveFlag_TE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1849 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Watermark Interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR TWIF LL_DMA2D_IsActiveFlag_TW
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 1827 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Interruption Management

Functions
Interruption Management
DMA2D Exported Functions

Functions

__STATIC_INLINE void | LL_DMA2D_EnableIT_CE (DMA2D_TypeDef *DMA2Dx)
Enable Configuration Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_CTC (DMA2D_TypeDef *DMA2Dx)
Enable CLUT Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_CAE (DMA2D_TypeDef *DMA2Dx)
Enable CLUT Access Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TW (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Watermark Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TC (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TE (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CE (DMA2D_TypeDef *DMA2Dx)
Disable Configuration Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CTC (DMA2D_TypeDef *DMA2Dx)
Disable CLUT Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CAE (DMA2D_TypeDef *DMA2Dx)
Disable CLUT Access Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TW (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Watermark Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TC (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TE (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Error Interrupt.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CTC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CAE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TW (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_DMA2D_DisableIT_CAE ( DMA2D_TypeDef * DMA2Dx )

Disable CLUT Access Error Interrupt.

Reference Manual to LL API cross reference:
CR CAEIE LL_DMA2D_DisableIT_CAE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2022 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableIT_CE ( DMA2D_TypeDef * DMA2Dx )

Disable Configuration Error Interrupt.

Reference Manual to LL API cross reference:
CR CEIE LL_DMA2D_DisableIT_CE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2000 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableIT_CTC ( DMA2D_TypeDef * DMA2Dx )

Disable CLUT Transfer Complete Interrupt.

Reference Manual to LL API cross reference:
CR CTCIE LL_DMA2D_DisableIT_CTC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2011 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableIT_TC ( DMA2D_TypeDef * DMA2Dx )

Disable Transfer Complete Interrupt.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA2D_DisableIT_TC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2044 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableIT_TE ( DMA2D_TypeDef * DMA2Dx )

Disable Transfer Error Interrupt.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA2D_DisableIT_TE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2055 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_DisableIT_TW ( DMA2D_TypeDef * DMA2Dx )

Disable Transfer Watermark Interrupt.

Reference Manual to LL API cross reference:
CR TWIE LL_DMA2D_DisableIT_TW
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 2033 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_CAE ( DMA2D_TypeDef * DMA2Dx )

Enable CLUT Access Error Interrupt.

Reference Manual to LL API cross reference:
CR CAEIE LL_DMA2D_EnableIT_CAE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1956 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_CE ( DMA2D_TypeDef * DMA2Dx )

Enable Configuration Error Interrupt.

Reference Manual to LL API cross reference:
CR CEIE LL_DMA2D_EnableIT_CE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1934 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_CTC ( DMA2D_TypeDef * DMA2Dx )

Enable CLUT Transfer Complete Interrupt.

Reference Manual to LL API cross reference:
CR CTCIE LL_DMA2D_EnableIT_CTC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1945 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_TC ( DMA2D_TypeDef * DMA2Dx )

Enable Transfer Complete Interrupt.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA2D_EnableIT_TC
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1978 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_TE ( DMA2D_TypeDef * DMA2Dx )

Enable Transfer Error Interrupt.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA2D_EnableIT_TE
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1989 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE void LL_DMA2D_EnableIT_TW ( DMA2D_TypeDef * DMA2Dx )

Enable Transfer Watermark Interrupt.

Reference Manual to LL API cross reference:
CR TWIE LL_DMA2D_EnableIT_TW
Parameters:
DMA2Dx DMA2D Instance
Return values:
None

Definition at line 1967 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR CAEIE LL_DMA2D_IsEnabledIT_CAE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2088 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Configuration Error interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR CEIE LL_DMA2D_IsEnabledIT_CE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2066 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR CTCIE LL_DMA2D_IsEnabledIT_CTC
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2077 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR TCIE LL_DMA2D_IsEnabledIT_TC
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2110 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Error interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR TEIE LL_DMA2D_IsEnabledIT_TE
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2121 of file stm32h7xx_ll_dma2d.h.

__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW ( DMA2D_TypeDef * DMA2Dx )

Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR TWIE LL_DMA2D_IsEnabledIT_TW
Parameters:
DMA2Dx DMA2D Instance
Return values:
State of bit (1 or 0).

Definition at line 2099 of file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and De-initialization Functions

Functions
Initialization and De-initialization Functions
DMA2D Exported Functions

Functions

ErrorStatus | LL_DMA2D_DeInit (DMA2D_TypeDef *DMA2Dx)
De-initialize DMA2D registers (registers restored to their default values).
ErrorStatus | LL_DMA2D_Init (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
void | LL_DMA2D_StructInit (LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Set each LL_DMA2D_InitTypeDef field to default value.
void | LL_DMA2D_ConfigLayer (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
Configure the foreground or background according to the specified parameters in the LL_DMA2D_LayerCfgTypeDef structure.
void | LL_DMA2D_LayerCfgStructInit (LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
Set each LL_DMA2D_LayerCfgTypeDef field to default value.
void | LL_DMA2D_ConfigOutputColor (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
Initialize DMA2D output color register according to the specified parameters in DMA2D_ColorStruct.
uint32_t | LL_DMA2D_GetOutputBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Blue color.
uint32_t | LL_DMA2D_GetOutputGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Green color.
uint32_t | LL_DMA2D_GetOutputRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Red color.
uint32_t | LL_DMA2D_GetOutputAlphaColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Alpha color.
void | LL_DMA2D_ConfigSize (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
Configure DMA2D transfer size.

Function Documentation

void LL_DMA2D_ConfigLayer | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | LL_DMA2D_LayerCfgTypeDef * | DMA2D_LayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the foreground or background according to the specified parameters in the LL_DMA2D_LayerCfgTypeDef structure.

Parameters:
DMA2Dx | DMA2D Instance
DMA2D_LayerCfg | pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains the configuration information for the specified layer.
LayerIdx | DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
None

Definition at line 281 of file stm32h7xx_ll_dma2d.c.

References LL_DMA2D_LayerCfgTypeDef::Alpha, LL_DMA2D_LayerCfgTypeDef::AlphaInversionMode, LL_DMA2D_LayerCfgTypeDef::AlphaMode, assert_param, LL_DMA2D_LayerCfgTypeDef::Blue, LL_DMA2D_LayerCfgTypeDef::ChromaSubSampling, LL_DMA2D_LayerCfgTypeDef::CLUTColorMode, LL_DMA2D_LayerCfgTypeDef::CLUTMemoryAddress, LL_DMA2D_LayerCfgTypeDef::CLUTSize, LL_DMA2D_LayerCfgTypeDef::ColorMode, LL_DMA2D_LayerCfgTypeDef::Green, IS_LL_DMA2D_ALPHA, IS_LL_DMA2D_ALPHAINV, IS_LL_DMA2D_ALPHAMODE, IS_LL_DMA2D_BLUE, IS_LL_DMA2D_CHROMA_SUB_SAMPLING, IS_LL_DMA2D_CLUTCMODE, IS_LL_DMA2D_CLUTSIZE, IS_LL_DMA2D_GREEN, IS_LL_DMA2D_LCMODE, IS_LL_DMA2D_OFFSET, IS_LL_DMA2D_RBSWAP, IS_LL_DMA2D_RED, LL_DMA2D_LayerCfgTypeDef::LineOffset, LL_DMA2D_BGND_SetCLUTMemAddr(), LL_DMA2D_BGND_SetColor(), LL_DMA2D_BGND_SetLineOffset(), LL_DMA2D_BGND_SetMemAddr(), LL_DMA2D_FGND_SetCLUTMemAddr(), LL_DMA2D_FGND_SetColor(), LL_DMA2D_FGND_SetLineOffset(), LL_DMA2D_FGND_SetMemAddr(), LL_DMA2D_LayerCfgTypeDef::MemoryAddress, LL_DMA2D_LayerCfgTypeDef::RBSwapMode, and LL_DMA2D_LayerCfgTypeDef::Red.

void LL_DMA2D_ConfigOutputColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | LL_DMA2D_ColorTypeDef * | DMA2D_ColorStruct
 | ) |  |

Initialize DMA2D output color register according to the specified parameters in DMA2D_ColorStruct.

Parameters:
DMA2Dx | DMA2D Instance
DMA2D_ColorStruct | pointer to a LL_DMA2D_ColorTypeDef structure that contains the color configuration information for the specified DMA2D peripheral.
Return values:
None

Definition at line 381 of file stm32h7xx_ll_dma2d.c.

References assert_param, LL_DMA2D_ColorTypeDef::ColorMode, IS_LL_DMA2D_ALPHA, IS_LL_DMA2D_BLUE, IS_LL_DMA2D_GREEN, IS_LL_DMA2D_OCMODE, IS_LL_DMA2D_RED, LL_DMA2D_OUTPUT_MODE_ARGB1555, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_OUTPUT_MODE_RGB565, LL_DMA2D_OUTPUT_MODE_RGB888, LL_DMA2D_SetOutputColor(), LL_DMA2D_ColorTypeDef::OutputAlpha, LL_DMA2D_ColorTypeDef::OutputBlue, LL_DMA2D_ColorTypeDef::OutputGreen, and LL_DMA2D_ColorTypeDef::OutputRed.

Referenced by LL_DMA2D_Init().

void LL_DMA2D_ConfigSize | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | NbrOfLines,
 |  | uint32_t | NbrOfPixelsPerLines
 | ) |  |

Configure DMA2D transfer size.

Parameters:
DMA2Dx | DMA2D Instance
NbrOfLines | Value between Min_Data=0 and Max_Data=0xFFFF
NbrOfPixelsPerLines | Value between Min_Data=0 and Max_Data=0x3FFF
Return values:
None

Definition at line 608 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_Init().

ErrorStatus LL_DMA2D_DeInit ( DMA2D_TypeDef * DMA2Dx )

De-initialize DMA2D registers (registers restored to their default values).

Parameters:
DMA2Dx DMA2D Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA2D registers are de-initialized
  • ERROR: DMA2D registers are not de-initialized

Definition at line 140 of file stm32h7xx_ll_dma2d.c.

References assert_param, LL_AHB3_GRP1_ForceReset(), LL_AHB3_GRP1_PERIPH_DMA2D, and LL_AHB3_GRP1_ReleaseReset().

uint32_t LL_DMA2D_GetOutputAlphaColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Return DMA2D output Alpha color.

Parameters:
DMA2Dx DMA2D Instance.
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444
Return values:
Output Alpha color value between Min_Data=0 and Max_Data=0xFF

Definition at line 572 of file stm32h7xx_ll_dma2d.c.

References assert_param, IS_LL_DMA2D_OCMODE, LL_DMA2D_OUTPUT_MODE_ARGB1555, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_OUTPUT_MODE_RGB565, and LL_DMA2D_OUTPUT_MODE_RGB888.

uint32_t LL_DMA2D_GetOutputBlueColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Return DMA2D output Blue color.

Parameters:
DMA2Dx DMA2D Instance.
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444
Return values:
Output Blue color value between Min_Data=0 and Max_Data=0xFF

Definition at line 440 of file stm32h7xx_ll_dma2d.c.

References assert_param, IS_LL_DMA2D_OCMODE, LL_DMA2D_OUTPUT_MODE_ARGB1555, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_OUTPUT_MODE_RGB565, and LL_DMA2D_OUTPUT_MODE_RGB888.

uint32_t LL_DMA2D_GetOutputGreenColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Return DMA2D output Green color.

Parameters:
DMA2Dx DMA2D Instance.
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444
Return values:
Output Green color value between Min_Data=0 and Max_Data=0xFF

Definition at line 484 of file stm32h7xx_ll_dma2d.c.

References assert_param, IS_LL_DMA2D_OCMODE, LL_DMA2D_OUTPUT_MODE_ARGB1555, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_OUTPUT_MODE_RGB565, and LL_DMA2D_OUTPUT_MODE_RGB888.

uint32_t LL_DMA2D_GetOutputRedColor | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | uint32_t | ColorMode
 | ) |  |

Return DMA2D output Red color.

Parameters:
DMA2Dx DMA2D Instance.
ColorMode This parameter can be one of the following values:
  • LL_DMA2D_OUTPUT_MODE_ARGB8888
  • LL_DMA2D_OUTPUT_MODE_RGB888
  • LL_DMA2D_OUTPUT_MODE_RGB565
  • LL_DMA2D_OUTPUT_MODE_ARGB1555
  • LL_DMA2D_OUTPUT_MODE_ARGB4444
Return values:
Output Red color value between Min_Data=0 and Max_Data=0xFF

Definition at line 528 of file stm32h7xx_ll_dma2d.c.

References assert_param, IS_LL_DMA2D_OCMODE, LL_DMA2D_OUTPUT_MODE_ARGB1555, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_OUTPUT_MODE_RGB565, and LL_DMA2D_OUTPUT_MODE_RGB888.

ErrorStatus LL_DMA2D_Init | ( | DMA2D_TypeDef * | DMA2Dx,
 |  | LL_DMA2D_InitTypeDef * | DMA2D_InitStruct
 | ) |  |

Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.

Note:
DMA2D transfers must be disabled to set initialization bits in configuration registers, otherwise ERROR result is returned.
Parameters:
DMA2Dx | DMA2D Instance
DMA2D_InitStruct | pointer to a LL_DMA2D_InitTypeDef structure that contains the configuration information for the specified DMA2D peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
  • ERROR: Issue occurred during DMA2D registers initialization

Definition at line 175 of file stm32h7xx_ll_dma2d.c.

References LL_DMA2D_InitTypeDef::AlphaInversionMode, assert_param, LL_DMA2D_InitTypeDef::ColorMode, LL_DMA2D_ColorTypeDef::ColorMode, IS_LL_DMA2D_ALPHA, IS_LL_DMA2D_ALPHAINV, IS_LL_DMA2D_BLUE, IS_LL_DMA2D_GREEN, IS_LL_DMA2D_LINE, IS_LL_DMA2D_MODE, IS_LL_DMA2D_OCMODE, IS_LL_DMA2D_OFFSET, IS_LL_DMA2D_OFFSET_MODE, IS_LL_DMA2D_PIXEL, IS_LL_DMA2D_RBSWAP, IS_LL_DMA2D_RED, IS_LL_DMA2D_SWAP_MODE, LL_DMA2D_InitTypeDef::LineOffset, LL_DMA2D_InitTypeDef::LineOffsetMode, LL_DMA2D_BGND_IsEnabledCLUTLoad(), LL_DMA2D_ConfigOutputColor(), LL_DMA2D_ConfigSize(), LL_DMA2D_FGND_IsEnabledCLUTLoad(), LL_DMA2D_IsTransferOngoing(), LL_DMA2D_SetLineOffset(), LL_DMA2D_SetOutputMemAddr(), LL_DMA2D_InitTypeDef::Mode, LL_DMA2D_InitTypeDef::NbrOfLines, LL_DMA2D_InitTypeDef::NbrOfPixelsPerLines, LL_DMA2D_InitTypeDef::OutputAlpha, LL_DMA2D_ColorTypeDef::OutputAlpha, LL_DMA2D_InitTypeDef::OutputBlue, LL_DMA2D_ColorTypeDef::OutputBlue, LL_DMA2D_InitTypeDef::OutputGreen, LL_DMA2D_ColorTypeDef::OutputGreen, LL_DMA2D_InitTypeDef::OutputMemoryAddress, LL_DMA2D_InitTypeDef::OutputRed, LL_DMA2D_ColorTypeDef::OutputRed, LL_DMA2D_InitTypeDef::OutputSwapMode, and LL_DMA2D_InitTypeDef::RBSwapMode.

void LL_DMA2D_LayerCfgStructInit ( LL_DMA2D_LayerCfgTypeDef * DMA2D_LayerCfg )

Set each LL_DMA2D_LayerCfgTypeDef field to default value.

Parameters:
DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 354 of file stm32h7xx_ll_dma2d.c.

References LL_DMA2D_LayerCfgTypeDef::Alpha, LL_DMA2D_LayerCfgTypeDef::AlphaInversionMode, LL_DMA2D_LayerCfgTypeDef::AlphaMode, LL_DMA2D_LayerCfgTypeDef::Blue, LL_DMA2D_LayerCfgTypeDef::ChromaSubSampling, LL_DMA2D_LayerCfgTypeDef::CLUTColorMode, LL_DMA2D_LayerCfgTypeDef::CLUTMemoryAddress, LL_DMA2D_LayerCfgTypeDef::CLUTSize, LL_DMA2D_LayerCfgTypeDef::ColorMode, LL_DMA2D_LayerCfgTypeDef::Green, LL_DMA2D_LayerCfgTypeDef::LineOffset, LL_DMA2D_ALPHA_MODE_NO_MODIF, LL_DMA2D_ALPHA_REGULAR, LL_DMA2D_CLUT_COLOR_MODE_ARGB8888, LL_DMA2D_CSS_444, LL_DMA2D_INPUT_MODE_ARGB8888, LL_DMA2D_RB_MODE_REGULAR, LL_DMA2D_LayerCfgTypeDef::MemoryAddress, LL_DMA2D_LayerCfgTypeDef::RBSwapMode, and LL_DMA2D_LayerCfgTypeDef::Red.

void LL_DMA2D_StructInit ( LL_DMA2D_InitTypeDef * DMA2D_InitStruct )

Set each LL_DMA2D_InitTypeDef field to default value.

Parameters:
DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 251 of file stm32h7xx_ll_dma2d.c.

References LL_DMA2D_InitTypeDef::AlphaInversionMode, LL_DMA2D_InitTypeDef::ColorMode, LL_DMA2D_InitTypeDef::LineOffset, LL_DMA2D_InitTypeDef::LineOffsetMode, LL_DMA2D_ALPHA_REGULAR, LL_DMA2D_LINE_OFFSET_PIXELS, LL_DMA2D_MODE_M2M, LL_DMA2D_OUTPUT_MODE_ARGB8888, LL_DMA2D_RB_MODE_REGULAR, LL_DMA2D_SWAP_MODE_REGULAR, LL_DMA2D_InitTypeDef::Mode, LL_DMA2D_InitTypeDef::NbrOfLines, LL_DMA2D_InitTypeDef::NbrOfPixelsPerLines, LL_DMA2D_InitTypeDef::OutputAlpha, LL_DMA2D_InitTypeDef::OutputBlue, LL_DMA2D_InitTypeDef::OutputGreen, LL_DMA2D_InitTypeDef::OutputMemoryAddress, LL_DMA2D_InitTypeDef::OutputRed, LL_DMA2D_InitTypeDef::OutputSwapMode, and LL_DMA2D_InitTypeDef::RBSwapMode.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA2D Private Constants

Defines
DMA2D Private Constants
DMA2D

Defines

#define | LL_DMA2D_COLOR 0xFFU
#define | LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL
#define | LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)
#define | LL_DMA2D_OFFSET_MAX 0x3FFFU
#define | LL_DMA2D_CLUTSIZE_MAX 0xFFU

Define Documentation

#define LL_DMA2D_CLUTSIZE_MAX 0xFFU

Maximum CLUT size

Definition at line 50 of file stm32h7xx_ll_dma2d.c.

#define LL_DMA2D_COLOR 0xFFU

Maximum output color setting

Definition at line 46 of file stm32h7xx_ll_dma2d.c.

#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL

Maximum number of lines

Definition at line 47 of file stm32h7xx_ll_dma2d.c.

#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)

Maximum number of pixels per lines

Definition at line 48 of file stm32h7xx_ll_dma2d.c.

#define LL_DMA2D_OFFSET_MAX 0x3FFFU

Maximum output line offset expressed in pixels

Definition at line 49 of file stm32h7xx_ll_dma2d.c.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAMUX Private Constants

Defines
DMAMUX Private Constants
DMAMUX

Defines

#define | DMAMUX_CCR_SIZE 0x00000004U
#define | DMAMUX_RGCR_SIZE 0x00000004U
#define | DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
#define | DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
#define | DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)

Define Documentation

#define DMAMUX_CCR_SIZE 0x00000004U

Definition at line 48 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_BDMA_GetPeriphRequest(), LL_BDMA_SetPeriphRequest(), LL_DMA_GetPeriphRequest(), LL_DMA_SetPeriphRequest(), LL_DMAMUX_DisableEventGeneration(), LL_DMAMUX_DisableIT_SO(), LL_DMAMUX_DisableSync(), LL_DMAMUX_EnableEventGeneration(), LL_DMAMUX_EnableIT_SO(), LL_DMAMUX_EnableSync(), LL_DMAMUX_GetRequestID(), LL_DMAMUX_GetSyncID(), LL_DMAMUX_GetSyncPolarity(), LL_DMAMUX_GetSyncRequestNb(), LL_DMAMUX_IsEnabledEventGeneration(), LL_DMAMUX_IsEnabledIT_SO(), LL_DMAMUX_IsEnabledSync(), LL_DMAMUX_SetRequestID(), LL_DMAMUX_SetSyncID(), LL_DMAMUX_SetSyncPolarity(), and LL_DMAMUX_SetSyncRequestNb().

#define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)

Definition at line 56 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_DMAMUX_ClearFlag_SO0(), LL_DMAMUX_ClearFlag_SO1(), LL_DMAMUX_ClearFlag_SO10(), LL_DMAMUX_ClearFlag_SO11(), LL_DMAMUX_ClearFlag_SO12(), LL_DMAMUX_ClearFlag_SO13(), LL_DMAMUX_ClearFlag_SO14(), LL_DMAMUX_ClearFlag_SO15(), LL_DMAMUX_ClearFlag_SO2(), LL_DMAMUX_ClearFlag_SO3(), LL_DMAMUX_ClearFlag_SO4(), LL_DMAMUX_ClearFlag_SO5(), LL_DMAMUX_ClearFlag_SO6(), LL_DMAMUX_ClearFlag_SO7(), LL_DMAMUX_ClearFlag_SO8(), LL_DMAMUX_ClearFlag_SO9(), LL_DMAMUX_IsActiveFlag_SO0(), LL_DMAMUX_IsActiveFlag_SO1(), LL_DMAMUX_IsActiveFlag_SO10(), LL_DMAMUX_IsActiveFlag_SO11(), LL_DMAMUX_IsActiveFlag_SO12(), LL_DMAMUX_IsActiveFlag_SO13(), LL_DMAMUX_IsActiveFlag_SO14(), LL_DMAMUX_IsActiveFlag_SO15(), LL_DMAMUX_IsActiveFlag_SO2(), LL_DMAMUX_IsActiveFlag_SO3(), LL_DMAMUX_IsActiveFlag_SO4(), LL_DMAMUX_IsActiveFlag_SO5(), LL_DMAMUX_IsActiveFlag_SO6(), LL_DMAMUX_IsActiveFlag_SO7(), LL_DMAMUX_IsActiveFlag_SO8(), and LL_DMAMUX_IsActiveFlag_SO9().

#define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)

Definition at line 54 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_DMAMUX_DisableIT_RGO(), LL_DMAMUX_DisableRequestGen(), LL_DMAMUX_EnableIT_RGO(), LL_DMAMUX_EnableRequestGen(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsEnabledIT_RGO(), LL_DMAMUX_IsEnabledRequestGen(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), and LL_DMAMUX_SetRequestSignalID().

#define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)

Definition at line 58 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_DMAMUX_ClearFlag_RGO0(), LL_DMAMUX_ClearFlag_RGO1(), LL_DMAMUX_ClearFlag_RGO2(), LL_DMAMUX_ClearFlag_RGO3(), LL_DMAMUX_ClearFlag_RGO4(), LL_DMAMUX_ClearFlag_RGO5(), LL_DMAMUX_ClearFlag_RGO6(), LL_DMAMUX_ClearFlag_RGO7(), LL_DMAMUX_IsActiveFlag_RGO0(), LL_DMAMUX_IsActiveFlag_RGO1(), LL_DMAMUX_IsActiveFlag_RGO2(), LL_DMAMUX_IsActiveFlag_RGO3(), LL_DMAMUX_IsActiveFlag_RGO4(), LL_DMAMUX_IsActiveFlag_RGO5(), LL_DMAMUX_IsActiveFlag_RGO6(), and LL_DMAMUX_IsActiveFlag_RGO7().

#define DMAMUX_RGCR_SIZE 0x00000004U

Definition at line 51 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_DMAMUX_DisableIT_RGO(), LL_DMAMUX_DisableRequestGen(), LL_DMAMUX_EnableIT_RGO(), LL_DMAMUX_EnableRequestGen(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsEnabledIT_RGO(), LL_DMAMUX_IsEnabledRequestGen(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), and LL_DMAMUX_SetRequestSignalID().

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_WriteReg function. More...

Defines

#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14
#define | LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3
#define | LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4
#define | LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5
#define | LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6
#define | LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7

Detailed Description

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Define Documentation

#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 74 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 75 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 84 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 85 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 86 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 87 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14

Synchronization Event Overrun Flag Channel 14

Definition at line 88 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15

Synchronization Event Overrun Flag Channel 15

Definition at line 89 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 76 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 77 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 78 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 79 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 80 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 81 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 82 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 83 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 90 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 91 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 92 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 93 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4

Request Generator 4 Trigger Event Overrun Flag

Definition at line 94 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5

Request Generator 5 Trigger Event Overrun Flag

Definition at line 95 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6

Request Generator 6 Trigger Event Overrun Flag

Definition at line 96 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7

Request Generator 7 Trigger Event Overrun Flag

Definition at line 97 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_ReadReg function. More...

Defines

#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14
#define | LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3
#define | LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4
#define | LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5
#define | LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6
#define | LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7

Detailed Description

Flags defines which can be used with LL_DMAMUX_ReadReg function.

Define Documentation

#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 106 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 107 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 116 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 117 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 118 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 119 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14

Synchronization Event Overrun Flag Channel 14

Definition at line 120 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15

Synchronization Event Overrun Flag Channel 15

Definition at line 121 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 108 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 109 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 110 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 111 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 112 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 113 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 114 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 115 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 122 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 123 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 124 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 125 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4

Request Generator 4 Trigger Event Overrun Flag

Definition at line 126 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5

Request Generator 5 Trigger Event Overrun Flag

Definition at line 127 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6

Request Generator 6 Trigger Event Overrun Flag

Definition at line 128 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7

Request Generator 7 Trigger Event Overrun Flag

Definition at line 129 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
DMAMUX Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions. More...

Defines

#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Define Documentation

#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE

Synchronization Event Overrun Interrupt

Definition at line 138 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Request Generation Trigger Event Overrun Interrupt

Definition at line 139 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAMUX Request selection

Defines
DMAMUX Request selection
DMAMUX Exported Constants

DMA Request selection. More...

Defines

#define | LL_DMAMUX1_REQ_MEM2MEM 0U
#define | LL_DMAMUX1_REQ_GENERATOR0 1U
#define | LL_DMAMUX1_REQ_GENERATOR1 2U
#define | LL_DMAMUX1_REQ_GENERATOR2 3U
#define | LL_DMAMUX1_REQ_GENERATOR3 4U
#define | LL_DMAMUX1_REQ_GENERATOR4 5U
#define | LL_DMAMUX1_REQ_GENERATOR5 6U
#define | LL_DMAMUX1_REQ_GENERATOR6 7U
#define | LL_DMAMUX1_REQ_GENERATOR7 8U
#define | LL_DMAMUX1_REQ_ADC1 9U
#define | LL_DMAMUX1_REQ_ADC2 10U
#define | LL_DMAMUX1_REQ_TIM1_CH1 11U
#define | LL_DMAMUX1_REQ_TIM1_CH2 12U
#define | LL_DMAMUX1_REQ_TIM1_CH3 13U
#define | LL_DMAMUX1_REQ_TIM1_CH4 14U
#define | LL_DMAMUX1_REQ_TIM1_UP 15U
#define | LL_DMAMUX1_REQ_TIM1_TRIG 16U
#define | LL_DMAMUX1_REQ_TIM1_COM 17U
#define | LL_DMAMUX1_REQ_TIM2_CH1 18U
#define | LL_DMAMUX1_REQ_TIM2_CH2 19U
#define | LL_DMAMUX1_REQ_TIM2_CH3 20U
#define | LL_DMAMUX1_REQ_TIM2_CH4 21U
#define | LL_DMAMUX1_REQ_TIM2_UP 22U
#define | LL_DMAMUX1_REQ_TIM3_CH1 23U
#define | LL_DMAMUX1_REQ_TIM3_CH2 24U
#define | LL_DMAMUX1_REQ_TIM3_CH3 25U
#define | LL_DMAMUX1_REQ_TIM3_CH4 26U
#define | LL_DMAMUX1_REQ_TIM3_UP 27U
#define | LL_DMAMUX1_REQ_TIM3_TRIG 28U
#define | LL_DMAMUX1_REQ_TIM4_CH1 29U
#define | LL_DMAMUX1_REQ_TIM4_CH2 30U
#define | LL_DMAMUX1_REQ_TIM4_CH3 31U
#define | LL_DMAMUX1_REQ_TIM4_UP 32U
#define | LL_DMAMUX1_REQ_I2C1_RX 33U
#define | LL_DMAMUX1_REQ_I2C1_TX 34U
#define | LL_DMAMUX1_REQ_I2C2_RX 35U
#define | LL_DMAMUX1_REQ_I2C2_TX 36U
#define | LL_DMAMUX1_REQ_SPI1_RX 37U
#define | LL_DMAMUX1_REQ_SPI1_TX 38U
#define | LL_DMAMUX1_REQ_SPI2_RX 39U
#define | LL_DMAMUX1_REQ_SPI2_TX 40U
#define | LL_DMAMUX1_REQ_USART1_RX 41U
#define | LL_DMAMUX1_REQ_USART1_TX 42U
#define | LL_DMAMUX1_REQ_USART2_RX 43U
#define | LL_DMAMUX1_REQ_USART2_TX 44U
#define | LL_DMAMUX1_REQ_USART3_RX 45U
#define | LL_DMAMUX1_REQ_USART3_TX 46U
#define | LL_DMAMUX1_REQ_TIM8_CH1 47U
#define | LL_DMAMUX1_REQ_TIM8_CH2 48U
#define | LL_DMAMUX1_REQ_TIM8_CH3 49U
#define | LL_DMAMUX1_REQ_TIM8_CH4 50U
#define | LL_DMAMUX1_REQ_TIM8_UP 51U
#define | LL_DMAMUX1_REQ_TIM8_TRIG 52U
#define | LL_DMAMUX1_REQ_TIM8_COM 53U
#define | LL_DMAMUX1_REQ_TIM5_CH1 55U
#define | LL_DMAMUX1_REQ_TIM5_CH2 56U
#define | LL_DMAMUX1_REQ_TIM5_CH3 57U
#define | LL_DMAMUX1_REQ_TIM5_CH4 58U
#define | LL_DMAMUX1_REQ_TIM5_UP 59U
#define | LL_DMAMUX1_REQ_TIM5_TRIG 60U
#define | LL_DMAMUX1_REQ_SPI3_RX 61U
#define | LL_DMAMUX1_REQ_SPI3_TX 62U
#define | LL_DMAMUX1_REQ_UART4_RX 63U
#define | LL_DMAMUX1_REQ_UART4_TX 64U
#define | LL_DMAMUX1_REQ_UART5_RX 65U
#define | LL_DMAMUX1_REQ_UART5_TX 66U
#define | LL_DMAMUX1_REQ_DAC1_CH1 67U
#define | LL_DMAMUX1_REQ_DAC1_CH2 68U
#define | LL_DMAMUX1_REQ_TIM6_UP 69U
#define | LL_DMAMUX1_REQ_TIM7_UP 70U
#define | LL_DMAMUX1_REQ_USART6_RX 71U
#define | LL_DMAMUX1_REQ_USART6_TX 72U
#define | LL_DMAMUX1_REQ_I2C3_RX 73U
#define | LL_DMAMUX1_REQ_I2C3_TX 74U
#define | LL_DMAMUX1_REQ_DCMI_PSSI 75U
#define | LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
#define | LL_DMAMUX1_REQ_CRYP_IN 76U
#define | LL_DMAMUX1_REQ_CRYP_OUT 77U
#define | LL_DMAMUX1_REQ_HASH_IN 78U
#define | LL_DMAMUX1_REQ_UART7_RX 79U
#define | LL_DMAMUX1_REQ_UART7_TX 80U
#define | LL_DMAMUX1_REQ_UART8_RX 81U
#define | LL_DMAMUX1_REQ_UART8_TX 82U
#define | LL_DMAMUX1_REQ_SPI4_RX 83U
#define | LL_DMAMUX1_REQ_SPI4_TX 84U
#define | LL_DMAMUX1_REQ_SPI5_RX 85U
#define | LL_DMAMUX1_REQ_SPI5_TX 86U
#define | LL_DMAMUX1_REQ_SAI1_A 87U
#define | LL_DMAMUX1_REQ_SAI1_B 88U
#define | LL_DMAMUX1_REQ_SAI2_A 89U
#define | LL_DMAMUX1_REQ_SAI2_B 90U
#define | LL_DMAMUX1_REQ_SWPMI_RX 91U
#define | LL_DMAMUX1_REQ_SWPMI_TX 92U
#define | LL_DMAMUX1_REQ_SPDIF_RX_DT 93U
#define | LL_DMAMUX1_REQ_SPDIF_RX_CS 94U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT0 101U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT1 102U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT2 103U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT3 104U
#define | LL_DMAMUX1_REQ_TIM15_CH1 105U
#define | LL_DMAMUX1_REQ_TIM15_UP 106U
#define | LL_DMAMUX1_REQ_TIM15_TRIG 107U
#define | LL_DMAMUX1_REQ_TIM15_COM 108U
#define | LL_DMAMUX1_REQ_TIM16_CH1 109U
#define | LL_DMAMUX1_REQ_TIM16_UP 110U
#define | LL_DMAMUX1_REQ_TIM17_CH1 111U
#define | LL_DMAMUX1_REQ_TIM17_UP 112U
#define | LL_DMAMUX1_REQ_UART9_RX 116U
#define | LL_DMAMUX1_REQ_UART9_TX 117U
#define | LL_DMAMUX1_REQ_USART10_RX 118U
#define | LL_DMAMUX1_REQ_USART10_TX 119U
#define | LL_DMAMUX2_REQ_MEM2MEM 0U
#define | LL_DMAMUX2_REQ_GENERATOR0 1U
#define | LL_DMAMUX2_REQ_GENERATOR1 2U
#define | LL_DMAMUX2_REQ_GENERATOR2 3U
#define | LL_DMAMUX2_REQ_GENERATOR3 4U
#define | LL_DMAMUX2_REQ_GENERATOR4 5U
#define | LL_DMAMUX2_REQ_GENERATOR5 6U
#define | LL_DMAMUX2_REQ_GENERATOR6 7U
#define | LL_DMAMUX2_REQ_GENERATOR7 8U
#define | LL_DMAMUX2_REQ_LPUART1_RX 9U
#define | LL_DMAMUX2_REQ_LPUART1_TX 10U
#define | LL_DMAMUX2_REQ_SPI6_RX 11U
#define | LL_DMAMUX2_REQ_SPI6_TX 12U
#define | LL_DMAMUX2_REQ_I2C4_RX 13U
#define | LL_DMAMUX2_REQ_I2C4_TX 14U
#define | LL_DMAMUX2_REQ_DAC2_CH1 17U
#define | LL_DMAMUX2_REQ_DFSDM2 18U

Detailed Description

DMA Request selection.

Define Documentation

#define LL_DMAMUX1_REQ_ADC1 9U

DMAMUX1 ADC1 request

Definition at line 158 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_ADC2 10U

DMAMUX1 ADC2 request

Definition at line 159 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_CRYP_IN 76U

DMAMUX1 CRYP IN request

Definition at line 229 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_CRYP_OUT 77U

DMAMUX1 CRYP OUT request

Definition at line 230 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DAC1_CH1 67U

DMAMUX1 DAC1 Channel 1 request

Definition at line 215 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DAC1_CH2 68U

DMAMUX1 DAC1 Channel 2 request

Definition at line 216 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */

Definition at line 225 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DCMI_PSSI 75U

DMAMUX1 DCMI/PSSI request

Definition at line 224 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U

DMAMUX1 DFSDM1 Filter0 request

Definition at line 256 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U

DMAMUX1 DFSDM1 Filter1 request

Definition at line 257 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U

DMAMUX1 DFSDM1 Filter2 request

Definition at line 258 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U

DMAMUX1 DFSDM1 Filter3 request

Definition at line 259 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR0 1U

DMAMUX1 request generator 0

Definition at line 150 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR1 2U

DMAMUX1 request generator 1

Definition at line 151 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR2 3U

DMAMUX1 request generator 2

Definition at line 152 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR3 4U

DMAMUX1 request generator 3

Definition at line 153 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR4 5U

DMAMUX1 request generator 4

Definition at line 154 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR5 6U

DMAMUX1 request generator 5

Definition at line 155 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR6 7U

DMAMUX1 request generator 6

Definition at line 156 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GENERATOR7 8U

DMAMUX1 request generator 7

Definition at line 157 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_HASH_IN 78U

DMAMUX1 HASH IN request

Definition at line 231 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C1_RX 33U

DMAMUX1 I2C1 RX request

Definition at line 182 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C1_TX 34U

DMAMUX1 I2C1 TX request

Definition at line 183 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C2_RX 35U

DMAMUX1 I2C2 RX request

Definition at line 184 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C2_TX 36U

DMAMUX1 I2C2 TX request

Definition at line 185 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C3_RX 73U

DMAMUX1 I2C3 RX request

Definition at line 221 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_I2C3_TX 74U

DMAMUX1 I2C3 TX request

Definition at line 222 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_MEM2MEM 0U

memory to memory transfer

Definition at line 149 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_StructInit().

#define LL_DMAMUX1_REQ_SAI1_A 87U

DMAMUX1 SAI1 A request

Definition at line 240 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SAI1_B 88U

DMAMUX1 SAI1 B request

Definition at line 241 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SAI2_A 89U

DMAMUX1 SAI2 A request

Definition at line 242 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SAI2_B 90U

DMAMUX1 SAI2 B request

Definition at line 243 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U

DMAMUX1 SPDIF RXCS request

Definition at line 247 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U

DMAMUX1 SPDIF RXDT request

Definition at line 246 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI1_RX 37U

DMAMUX1 SPI1 RX request

Definition at line 186 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI1_TX 38U

DMAMUX1 SPI1 TX request

Definition at line 187 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI2_RX 39U

DMAMUX1 SPI2 RX request

Definition at line 188 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI2_TX 40U

DMAMUX1 SPI2 TX request

Definition at line 189 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI3_RX 61U

DMAMUX1 SPI3 RX request

Definition at line 209 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI3_TX 62U

DMAMUX1 SPI3 TX request

Definition at line 210 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI4_RX 83U

DMAMUX1 SPI4 RX request

Definition at line 236 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI4_TX 84U

DMAMUX1 SPI4 TX request

Definition at line 237 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI5_RX 85U

DMAMUX1 SPI5 RX request

Definition at line 238 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SPI5_TX 86U

DMAMUX1 SPI5 TX request

Definition at line 239 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SWPMI_RX 91U

DMAMUX1 SWPMI RX request

Definition at line 244 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_SWPMI_TX 92U

DMAMUX1 SWPMI TX request

Definition at line 245 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM15_CH1 105U

DMAMUX1 TIM15 CH1 request

Definition at line 260 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM15_COM 108U

DMAMUX1 TIM15 COM request

Definition at line 263 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM15_TRIG 107U

DMAMUX1 TIM15 TRIG request

Definition at line 262 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM15_UP 106U

DMAMUX1 TIM15 UP request

Definition at line 261 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM16_CH1 109U

DMAMUX1 TIM16 CH1 request

Definition at line 264 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM16_UP 110U

DMAMUX1 TIM16 UP request

Definition at line 265 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM17_CH1 111U

DMAMUX1 TIM17 CH1 request

Definition at line 266 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM17_UP 112U

DMAMUX1 TIM17 UP request

Definition at line 267 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_CH1 11U

DMAMUX1 TIM1 CH1 request

Definition at line 160 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_CH2 12U

DMAMUX1 TIM1 CH2 request

Definition at line 161 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_CH3 13U

DMAMUX1 TIM1 CH3 request

Definition at line 162 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_CH4 14U

DMAMUX1 TIM1 CH4 request

Definition at line 163 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_COM 17U

DMAMUX1 TIM1 COM request

Definition at line 166 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_TRIG 16U

DMAMUX1 TIM1 TRIG request

Definition at line 165 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM1_UP 15U

DMAMUX1 TIM1 UP request

Definition at line 164 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM2_CH1 18U

DMAMUX1 TIM2 CH1 request

Definition at line 167 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM2_CH2 19U

DMAMUX1 TIM2 CH2 request

Definition at line 168 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM2_CH3 20U

DMAMUX1 TIM2 CH3 request

Definition at line 169 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM2_CH4 21U

DMAMUX1 TIM2 CH4 request

Definition at line 170 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM2_UP 22U

DMAMUX1 TIM2 UP request

Definition at line 171 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_CH1 23U

DMAMUX1 TIM3 CH1 request

Definition at line 172 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_CH2 24U

DMAMUX1 TIM3 CH2 request

Definition at line 173 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_CH3 25U

DMAMUX1 TIM3 CH3 request

Definition at line 174 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_CH4 26U

DMAMUX1 TIM3 CH4 request

Definition at line 175 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_TRIG 28U

DMAMUX1 TIM3 TRIG request

Definition at line 177 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM3_UP 27U

DMAMUX1 TIM3 UP request

Definition at line 176 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM4_CH1 29U

DMAMUX1 TIM4 CH1 request

Definition at line 178 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM4_CH2 30U

DMAMUX1 TIM4 CH2 request

Definition at line 179 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM4_CH3 31U

DMAMUX1 TIM4 CH3 request

Definition at line 180 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM4_UP 32U

DMAMUX1 TIM4 UP request

Definition at line 181 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_CH1 55U

DMAMUX1 TIM5 CH1 request

Definition at line 203 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_CH2 56U

DMAMUX1 TIM5 CH2 request

Definition at line 204 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_CH3 57U

DMAMUX1 TIM5 CH3 request

Definition at line 205 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_CH4 58U

DMAMUX1 TIM5 CH4 request

Definition at line 206 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_TRIG 60U

DMAMUX1 TIM5 TRIG request

Definition at line 208 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM5_UP 59U

DMAMUX1 TIM5 UP request

Definition at line 207 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM6_UP 69U

DMAMUX1 TIM6 UP request

Definition at line 217 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM7_UP 70U

DMAMUX1 TIM7 UP request

Definition at line 218 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_CH1 47U

DMAMUX1 TIM8 CH1 request

Definition at line 196 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_CH2 48U

DMAMUX1 TIM8 CH2 request

Definition at line 197 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_CH3 49U

DMAMUX1 TIM8 CH3 request

Definition at line 198 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_CH4 50U

DMAMUX1 TIM8 CH4 request

Definition at line 199 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_COM 53U

DMAMUX1 TIM8 COM request

Definition at line 202 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_TRIG 52U

DMAMUX1 TIM8 TRIG request

Definition at line 201 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_TIM8_UP 51U

DMAMUX1 TIM8 UP request

Definition at line 200 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART4_RX 63U

DMAMUX1 UART4 RX request

Definition at line 211 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART4_TX 64U

DMAMUX1 UART4 TX request

Definition at line 212 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART5_RX 65U

DMAMUX1 UART5 RX request

Definition at line 213 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART5_TX 66U

DMAMUX1 UART5 TX request

Definition at line 214 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART7_RX 79U

DMAMUX1 UART7 RX request

Definition at line 232 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART7_TX 80U

DMAMUX1 UART7 TX request

Definition at line 233 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART8_RX 81U

DMAMUX1 UART8 RX request

Definition at line 234 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART8_TX 82U

DMAMUX1 UART8 TX request

Definition at line 235 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART9_RX 116U

DMAMUX1 UART9 RX request

Definition at line 276 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_UART9_TX 117U

DMAMUX1 UART9 TX request

Definition at line 277 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART10_RX 118U

DMAMUX1 USART10 RX request

Definition at line 280 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART10_TX 119U

DMAMUX1 USART10 TX request

Definition at line 281 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART1_RX 41U

DMAMUX1 USART1 RX request

Definition at line 190 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART1_TX 42U

DMAMUX1 USART1 TX request

Definition at line 191 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART2_RX 43U

DMAMUX1 USART2 RX request

Definition at line 192 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART2_TX 44U

DMAMUX1 USART2 TX request

Definition at line 193 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART3_RX 45U

DMAMUX1 USART3 RX request

Definition at line 194 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART3_TX 46U

DMAMUX1 USART3 TX request

Definition at line 195 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART6_RX 71U

DMAMUX1 USART6 RX request

Definition at line 219 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_USART6_TX 72U

DMAMUX1 USART6 TX request

Definition at line 220 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_DAC2_CH1 17U

DMAMUX2 DAC2 CH1 request

Definition at line 308 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_DFSDM2 18U

DMAMUX2 DFSDM2 request

Definition at line 311 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR0 1U

DMAMUX2 request generator 0

Definition at line 286 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR1 2U

DMAMUX2 request generator 1

Definition at line 287 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR2 3U

DMAMUX2 request generator 2

Definition at line 288 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR3 4U

DMAMUX2 request generator 3

Definition at line 289 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR4 5U

DMAMUX2 request generator 4

Definition at line 290 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR5 6U

DMAMUX2 request generator 5

Definition at line 291 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR6 7U

DMAMUX2 request generator 6

Definition at line 292 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GENERATOR7 8U

DMAMUX2 request generator 7

Definition at line 293 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_I2C4_RX 13U

DMAMUX2 I2C4 RX request

Definition at line 298 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_I2C4_TX 14U

DMAMUX2 I2C4 TX request

Definition at line 299 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_LPUART1_RX 9U

DMAMUX2 LP_UART1_RX request

Definition at line 294 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_LPUART1_TX 10U

DMAMUX2 LP_UART1_TX request

Definition at line 295 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_MEM2MEM 0U

memory to memory transfer

Definition at line 285 of file stm32h7xx_ll_dmamux.h.

Referenced by LL_BDMA_DeInit(), and LL_BDMA_StructInit().

#define LL_DMAMUX2_REQ_SPI6_RX 11U

DMAMUX2 SPI6 RX request

Definition at line 296 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_SPI6_TX 12U

DMAMUX2 SPI6 TX request

Definition at line 297 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMAMUX Channel

Defines
DMAMUX Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU
#define | LL_DMAMUX_CHANNEL_14 0x0000000EU
#define | LL_DMAMUX_CHANNEL_15 0x0000000FU

Define Documentation

#define LL_DMAMUX_CHANNEL_0 0x00000000U

DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0

Definition at line 321 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_1 0x00000001U

DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1

Definition at line 322 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_10 0x0000000AU

DMAMUX1 Channel 10 connected to DMA2 Channel 2

Definition at line 331 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_11 0x0000000BU

DMAMUX1 Channel 11 connected to DMA2 Channel 3

Definition at line 332 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_12 0x0000000CU

DMAMUX1 Channel 12 connected to DMA2 Channel 4

Definition at line 333 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_13 0x0000000DU

DMAMUX1 Channel 13 connected to DMA2 Channel 5

Definition at line 334 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_14 0x0000000EU

DMAMUX1 Channel 14 connected to DMA2 Channel 6

Definition at line 335 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_15 0x0000000FU

DMAMUX1 Channel 15 connected to DMA2 Channel 7

Definition at line 336 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_2 0x00000002U

DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2

Definition at line 323 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_3 0x00000003U

DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3

Definition at line 324 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_4 0x00000004U

DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4

Definition at line 325 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_5 0x00000005U

DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5

Definition at line 326 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_6 0x00000006U

DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6

Definition at line 327 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_7 0x00000007U

DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7

Definition at line 328 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_8 0x00000008U

DMAMUX1 Channel 8 connected to DMA2 Channel 0

Definition at line 329 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_9 0x00000009U

DMAMUX1 Channel 9 connected to DMA2 Channel 1

Definition at line 330 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Define Documentation

#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U

All requests are blocked

Definition at line 344 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1

Synchronization on event on falling edge

Definition at line 346 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0

Synchronization on event on rising edge

Definition at line 345 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Synchronization on event on rising and falling edge

Definition at line 347 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Synchronization Signal Event

Defines
Synchronization Signal Event
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U
#define | LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U
#define | LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U
#define | LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U
#define | LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U
#define | LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U
#define | LL_DMAMUX1_SYNC_EXTI0 0x06000000U
#define | LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U
#define | LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U
#define | LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U
#define | LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U
#define | LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U
#define | LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U
#define | LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U
#define | LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U
#define | LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U
#define | LL_DMAMUX2_SYNC_EXTI0 0x0E000000U
#define | LL_DMAMUX2_SYNC_EXTI2 0x0F000000U

Define Documentation

#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U

DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event

Definition at line 355 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U

DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event

Definition at line 356 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U

DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event

Definition at line 357 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U

DMAMUX1 synchronization Signal is EXTI0 IT

Definition at line 361 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U

DMAMUX1 synchronization Signal is LPTIM1 OUT

Definition at line 358 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U

DMAMUX1 synchronization Signal is LPTIM2 OUT

Definition at line 359 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U

DMAMUX1 synchronization Signal is LPTIM3 OUT

Definition at line 360 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U

DMAMUX1 synchronization Signal is TIM12 TRGO

Definition at line 362 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U

DMAMUX2 synchronization Signal is Comparator 1 output

Definition at line 376 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event

Definition at line 364 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event

Definition at line 365 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event

Definition at line 366 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event

Definition at line 367 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event

Definition at line 368 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U

DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event

Definition at line 369 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U

DMAMUX2 synchronization Signal is EXTI0 IT

Definition at line 378 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U

DMAMUX2 synchronization Signal is EXTI2 IT

Definition at line 379 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U

DMAMUX2 synchronization Signal is I2C4 Wakeup

Definition at line 374 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U

DMAMUX2 synchronization Signal is LPTIM2 output

Definition at line 372 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U

DMAMUX2 synchronization Signal is LPTIM3 output

Definition at line 373 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U

DMAMUX2 synchronization Signal is LPUART1 RX Wakeup

Definition at line 370 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U

DMAMUX2 synchronization Signal is LPUART1 TX Wakeup

Definition at line 371 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U

DMAMUX2 synchronization Signal is RTC Wakeup

Definition at line 377 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U

DMAMUX2 synchronization Signal is SPI6 Wakeup

Definition at line 375 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Request Generator Channel

Defines
Request Generator Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U
#define | LL_DMAMUX_REQ_GEN_4 0x00000004U
#define | LL_DMAMUX_REQ_GEN_5 0x00000005U
#define | LL_DMAMUX_REQ_GEN_6 0x00000006U
#define | LL_DMAMUX_REQ_GEN_7 0x00000007U

Define Documentation

#define LL_DMAMUX_REQ_GEN_0 0x00000000U

Definition at line 388 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_1 0x00000001U

Definition at line 389 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_2 0x00000002U

Definition at line 390 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_3 0x00000003U

Definition at line 391 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_4 0x00000004U

Definition at line 392 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_5 0x00000005U

Definition at line 393 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_6 0x00000006U

Definition at line 394 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_7 0x00000007U

Definition at line 395 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:30 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: External Request Signal Generation Polarity

Defines
External Request Signal Generation Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

Define Documentation

#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

No external DMA request generation

Definition at line 403 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1

External DMA request generation on event on falling edge

Definition at line 405 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0

External DMA request generation on event on rising edge

Definition at line 404 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

External DMA request generation on rising and falling edge

Definition at line 406 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: External Request Signal Generation

Defines
External Request Signal Generation
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
#define | LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
#define | LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
#define | LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
#define | LL_DMAMUX1_REQ_GEN_EXTI0 6U
#define | LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
#define | LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
#define | LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
#define | LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
#define | LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
#define | LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
#define | LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
#define | LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
#define | LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
#define | LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
#define | LL_DMAMUX2_REQ_GEN_EXTI0 20U
#define | LL_DMAMUX2_REQ_GEN_EXTI2 21U
#define | LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
#define | LL_DMAMUX2_REQ_GEN_SPI6_IT 23U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
#define | LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
#define | LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U

Define Documentation

#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U

DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event

Definition at line 414 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U

DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event

Definition at line 415 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U

DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event

Definition at line 416 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_EXTI0 6U

DMAMUX1 Request generator Signal is EXTI0 IT

Definition at line 420 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U

DMAMUX1 Request generator Signal is LPTIM1 OUT

Definition at line 417 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U

DMAMUX1 Request generator Signal is LPTIM2 OUT

Definition at line 418 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U

DMAMUX1 Request generator Signal is LPTIM3 OUT

Definition at line 419 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U

DMAMUX1 Request generator Signal is TIM12 TRGO

Definition at line 421 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U

DMAMUX2 Request generator Signal is BDMA Channel 0 IT

Definition at line 457 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U

DMAMUX2 Request generator Signal is BDMA Channel 1 IT

Definition at line 458 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U

DMAMUX2 Request generator Signal is Comparator 1 output

Definition at line 444 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U

DMAMUX2 Request generator Signal is Comparator 2 output

Definition at line 445 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U

DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event

Definition at line 423 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U

DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event

Definition at line 424 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U

DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event

Definition at line 425 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U

DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event

Definition at line 426 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U

DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event

Definition at line 427 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U

DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event

Definition at line 428 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U

DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event

Definition at line 429 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_EXTI0 20U

DMAMUX2 Request generator Signal is EXTI0

Definition at line 447 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_EXTI2 21U

DMAMUX2 Request generator Signal is EXTI2

Definition at line 448 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U

DMAMUX2 Request generator Signal is I2C4 IT Event

Definition at line 449 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U

DMAMUX2 Request generator Signal is I2C4 Wakeup

Definition at line 442 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U

DMAMUX2 Request generator Signal is LPTIM2 OUT

Definition at line 433 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U

DMAMUX2 Request generator Signal is LPTIM2 Wakeup

Definition at line 432 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U

DMAMUX2 Request generator Signal is LPTIM3 OUT

Definition at line 435 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U

DMAMUX2 Request generator Signal is LPTIM3 Wakeup

Definition at line 434 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U

DMAMUX2 Request generator Signal is LPUART1 Rx IT

Definition at line 452 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U

DMAMUX2 Request generator Signal is LPUART1 RX Wakeup

Definition at line 430 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U

DMAMUX2 Request generator Signal is LPUART1 Tx IT

Definition at line 451 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U

DMAMUX2 Request generator Signal is LPUART1 TX Wakeup

Definition at line 431 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U

DMAMUX2 Request generator Signal is RTC Wakeup

Definition at line 446 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U

DMAMUX2 Request generator Signal is SPI6 IT

Definition at line 450 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U

DMAMUX2 Request generator Signal is SPI6 Wakeup

Definition at line 443 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMAMUX Exported Macros

Defines

#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Define Documentation

#define LL_DMAMUX_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 490 of file stm32h7xx_ll_dmamux.h.

#define LL_DMAMUX_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 482 of file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_DisableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1038 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_DisableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1307 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_DisableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1128 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_EnableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1008 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_EnableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
None

Definition at line 1289 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_EnableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1098 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the number of DMA request that will be autorized after a generation event.

Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 1428 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Definition at line 1382 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX1_REQ_MEM2MEM
  • LL_DMAMUX1_REQ_GENERATOR0
  • LL_DMAMUX1_REQ_GENERATOR1
  • LL_DMAMUX1_REQ_GENERATOR2
  • LL_DMAMUX1_REQ_GENERATOR3
  • LL_DMAMUX1_REQ_GENERATOR4
  • LL_DMAMUX1_REQ_GENERATOR5
  • LL_DMAMUX1_REQ_GENERATOR6
  • LL_DMAMUX1_REQ_GENERATOR7
  • LL_DMAMUX1_REQ_ADC1
  • LL_DMAMUX1_REQ_ADC2
  • LL_DMAMUX1_REQ_TIM1_CH1
  • LL_DMAMUX1_REQ_TIM1_CH2
  • LL_DMAMUX1_REQ_TIM1_CH3
  • LL_DMAMUX1_REQ_TIM1_CH4
  • LL_DMAMUX1_REQ_TIM1_UP
  • LL_DMAMUX1_REQ_TIM1_TRIG
  • LL_DMAMUX1_REQ_TIM1_COM
  • LL_DMAMUX1_REQ_TIM2_CH1
  • LL_DMAMUX1_REQ_TIM2_CH2
  • LL_DMAMUX1_REQ_TIM2_CH3
  • LL_DMAMUX1_REQ_TIM2_CH4
  • LL_DMAMUX1_REQ_TIM2_UP
  • LL_DMAMUX1_REQ_TIM3_CH1
  • LL_DMAMUX1_REQ_TIM3_CH2
  • LL_DMAMUX1_REQ_TIM3_CH3
  • LL_DMAMUX1_REQ_TIM3_CH4
  • LL_DMAMUX1_REQ_TIM3_UP
  • LL_DMAMUX1_REQ_TIM3_TRIG
  • LL_DMAMUX1_REQ_TIM4_CH1
  • LL_DMAMUX1_REQ_TIM4_CH2
  • LL_DMAMUX1_REQ_TIM4_CH3
  • LL_DMAMUX1_REQ_TIM4_UP
  • LL_DMAMUX1_REQ_I2C1_RX
  • LL_DMAMUX1_REQ_I2C1_TX
  • LL_DMAMUX1_REQ_I2C2_RX
  • LL_DMAMUX1_REQ_I2C2_TX
  • LL_DMAMUX1_REQ_SPI1_RX
  • LL_DMAMUX1_REQ_SPI1_TX
  • LL_DMAMUX1_REQ_SPI2_RX
  • LL_DMAMUX1_REQ_SPI2_TX
  • LL_DMAMUX1_REQ_USART1_RX
  • LL_DMAMUX1_REQ_USART1_TX
  • LL_DMAMUX1_REQ_USART2_RX
  • LL_DMAMUX1_REQ_USART2_TX
  • LL_DMAMUX1_REQ_USART3_RX
  • LL_DMAMUX1_REQ_USART3_TX
  • LL_DMAMUX1_REQ_TIM8_CH1
  • LL_DMAMUX1_REQ_TIM8_CH2
  • LL_DMAMUX1_REQ_TIM8_CH3
  • LL_DMAMUX1_REQ_TIM8_CH4
  • LL_DMAMUX1_REQ_TIM8_UP
  • LL_DMAMUX1_REQ_TIM8_TRIG
  • LL_DMAMUX1_REQ_TIM8_COM
  • LL_DMAMUX1_REQ_TIM5_CH1
  • LL_DMAMUX1_REQ_TIM5_CH2
  • LL_DMAMUX1_REQ_TIM5_CH3
  • LL_DMAMUX1_REQ_TIM5_CH4
  • LL_DMAMUX1_REQ_TIM5_UP
  • LL_DMAMUX1_REQ_TIM5_TRIG
  • LL_DMAMUX1_REQ_SPI3_RX
  • LL_DMAMUX1_REQ_SPI3_TX
  • LL_DMAMUX1_REQ_UART4_RX
  • LL_DMAMUX1_REQ_UART4_TX
  • LL_DMAMUX1_REQ_UART5_RX
  • LL_DMAMUX1_REQ_UART5_TX
  • LL_DMAMUX1_REQ_DAC1_CH1
  • LL_DMAMUX1_REQ_DAC1_CH2
  • LL_DMAMUX1_REQ_TIM6_UP
  • LL_DMAMUX1_REQ_TIM7_UP
  • LL_DMAMUX1_REQ_USART6_RX
  • LL_DMAMUX1_REQ_USART6_TX
  • LL_DMAMUX1_REQ_I2C3_RX
  • LL_DMAMUX1_REQ_I2C3_TX
  • LL_DMAMUX1_REQ_DCMI_PSSI
  • LL_DMAMUX1_REQ_CRYP_IN
  • LL_DMAMUX1_REQ_CRYP_OUT
  • LL_DMAMUX1_REQ_HASH_IN
  • LL_DMAMUX1_REQ_UART7_RX
  • LL_DMAMUX1_REQ_UART7_TX
  • LL_DMAMUX1_REQ_UART8_RX
  • LL_DMAMUX1_REQ_UART8_TX
  • LL_DMAMUX1_REQ_SPI4_RX
  • LL_DMAMUX1_REQ_SPI4_TX
  • LL_DMAMUX1_REQ_SPI5_RX
  • LL_DMAMUX1_REQ_SPI5_TX
  • LL_DMAMUX1_REQ_SAI1_A
  • LL_DMAMUX1_REQ_SAI1_B
  • LL_DMAMUX1_REQ_SAI2_A
  • LL_DMAMUX1_REQ_SAI2_B
  • LL_DMAMUX1_REQ_SWPMI_RX
  • LL_DMAMUX1_REQ_SWPMI_TX
  • LL_DMAMUX1_REQ_SPDIF_RX_DT
  • LL_DMAMUX1_REQ_SPDIF_RX_CS
  • LL_DMAMUX1_REQ_HRTIM_MASTER (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
  • LL_DMAMUX1_REQ_DFSDM1_FLT0
  • LL_DMAMUX1_REQ_DFSDM1_FLT1
  • LL_DMAMUX1_REQ_DFSDM1_FLT2
  • LL_DMAMUX1_REQ_DFSDM1_FLT3
  • LL_DMAMUX1_REQ_TIM15_CH1
  • LL_DMAMUX1_REQ_TIM15_UP
  • LL_DMAMUX1_REQ_TIM15_TRIG
  • LL_DMAMUX1_REQ_TIM15_COM
  • LL_DMAMUX1_REQ_TIM16_CH1
  • LL_DMAMUX1_REQ_TIM16_UP
  • LL_DMAMUX1_REQ_TIM17_CH1
  • LL_DMAMUX1_REQ_TIM17_UP
  • LL_DMAMUX1_REQ_SAI3_A (*)
  • LL_DMAMUX1_REQ_SAI3_B (*)
  • LL_DMAMUX1_REQ_ADC3 (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_UART9_TX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
  • LL_DMAMUX1_REQ_USART10_TX (*)
  • LL_DMAMUX2_REQ_MEM2MEM
  • LL_DMAMUX2_REQ_GENERATOR0
  • LL_DMAMUX2_REQ_GENERATOR1
  • LL_DMAMUX2_REQ_GENERATOR2
  • LL_DMAMUX2_REQ_GENERATOR3
  • LL_DMAMUX2_REQ_GENERATOR4
  • LL_DMAMUX2_REQ_GENERATOR5
  • LL_DMAMUX2_REQ_GENERATOR6
  • LL_DMAMUX2_REQ_GENERATOR7
  • LL_DMAMUX2_REQ_LPUART1_RX
  • LL_DMAMUX2_REQ_LPUART1_TX
  • LL_DMAMUX2_REQ_SPI6_RX
  • LL_DMAMUX2_REQ_SPI6_TX
  • LL_DMAMUX2_REQ_I2C4_RX
  • LL_DMAMUX2_REQ_I2C4_TX
  • LL_DMAMUX2_REQ_SAI4_A (*)
  • LL_DMAMUX2_REQ_SAI4_B (*)
  • LL_DMAMUX2_REQ_ADC3 (*)
  • LL_DMAMUX2_REQ_DAC2_CH1 (*)
  • LL_DMAMUX2_REQ_DFSDM2 (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 848 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
  • LL_DMAMUX1_SYNC_LPTIM1_OUT
  • LL_DMAMUX1_SYNC_LPTIM2_OUT
  • LL_DMAMUX1_SYNC_LPTIM3_OUT
  • LL_DMAMUX1_SYNC_EXTI0
  • LL_DMAMUX1_SYNC_TIM12_TRGO
  • LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
  • LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
  • LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
  • LL_DMAMUX2_SYNC_LPTIM2_OUT
  • LL_DMAMUX2_SYNC_LPTIM3_OUT
  • LL_DMAMUX2_SYNC_I2C4_WKUP
  • LL_DMAMUX2_SYNC_SPI6_WKUP
  • LL_DMAMUX2_SYNC_COMP1_OUT
  • LL_DMAMUX2_SYNC_RTC_WKUP
  • LL_DMAMUX2_SYNC_EXTI0
  • LL_DMAMUX2_SYNC_EXTI2

Definition at line 1536 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_GetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
  • LL_DMAMUX1_SYNC_LPTIM1_OUT
  • LL_DMAMUX1_SYNC_LPTIM2_OUT
  • LL_DMAMUX1_SYNC_LPTIM3_OUT
  • LL_DMAMUX1_SYNC_EXTI0
  • LL_DMAMUX1_SYNC_TIM12_TRGO
  • LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
  • LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
  • LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
  • LL_DMAMUX2_SYNC_LPTIM2_OUT
  • LL_DMAMUX2_SYNC_LPTIM3_OUT
  • LL_DMAMUX2_SYNC_I2C4_WKUP
  • LL_DMAMUX2_SYNC_SPI6_WKUP
  • LL_DMAMUX2_SYNC_COMP1_OUT
  • LL_DMAMUX2_SYNC_RTC_WKUP
  • LL_DMAMUX2_SYNC_EXTI0
  • LL_DMAMUX2_SYNC_EXTI2

Definition at line 1267 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_GetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING

Definition at line 978 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 909 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Event Generation on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1068 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generator is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_IsEnabledRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
State of bit (1 or 0).

Definition at line 1329 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the synchronization mode is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_IsEnabledSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1158 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a generation event.

Note:
This field can only be written when Generator is disabled.
Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 1406 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
Return values:
None

Definition at line 1356 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Request This parameter can be one of the following values:
  • LL_DMAMUX1_REQ_MEM2MEM
  • LL_DMAMUX1_REQ_GENERATOR0
  • LL_DMAMUX1_REQ_GENERATOR1
  • LL_DMAMUX1_REQ_GENERATOR2
  • LL_DMAMUX1_REQ_GENERATOR3
  • LL_DMAMUX1_REQ_GENERATOR4
  • LL_DMAMUX1_REQ_GENERATOR5
  • LL_DMAMUX1_REQ_GENERATOR6
  • LL_DMAMUX1_REQ_GENERATOR7
  • LL_DMAMUX1_REQ_ADC1
  • LL_DMAMUX1_REQ_ADC2
  • LL_DMAMUX1_REQ_TIM1_CH1
  • LL_DMAMUX1_REQ_TIM1_CH2
  • LL_DMAMUX1_REQ_TIM1_CH3
  • LL_DMAMUX1_REQ_TIM1_CH4
  • LL_DMAMUX1_REQ_TIM1_UP
  • LL_DMAMUX1_REQ_TIM1_TRIG
  • LL_DMAMUX1_REQ_TIM1_COM
  • LL_DMAMUX1_REQ_TIM2_CH1
  • LL_DMAMUX1_REQ_TIM2_CH2
  • LL_DMAMUX1_REQ_TIM2_CH3
  • LL_DMAMUX1_REQ_TIM2_CH4
  • LL_DMAMUX1_REQ_TIM2_UP
  • LL_DMAMUX1_REQ_TIM3_CH1
  • LL_DMAMUX1_REQ_TIM3_CH2
  • LL_DMAMUX1_REQ_TIM3_CH3
  • LL_DMAMUX1_REQ_TIM3_CH4
  • LL_DMAMUX1_REQ_TIM3_UP
  • LL_DMAMUX1_REQ_TIM3_TRIG
  • LL_DMAMUX1_REQ_TIM4_CH1
  • LL_DMAMUX1_REQ_TIM4_CH2
  • LL_DMAMUX1_REQ_TIM4_CH3
  • LL_DMAMUX1_REQ_TIM4_UP
  • LL_DMAMUX1_REQ_I2C1_RX
  • LL_DMAMUX1_REQ_I2C1_TX
  • LL_DMAMUX1_REQ_I2C2_RX
  • LL_DMAMUX1_REQ_I2C2_TX
  • LL_DMAMUX1_REQ_SPI1_RX
  • LL_DMAMUX1_REQ_SPI1_TX
  • LL_DMAMUX1_REQ_SPI2_RX
  • LL_DMAMUX1_REQ_SPI2_TX
  • LL_DMAMUX1_REQ_USART1_RX
  • LL_DMAMUX1_REQ_USART1_TX
  • LL_DMAMUX1_REQ_USART2_RX
  • LL_DMAMUX1_REQ_USART2_TX
  • LL_DMAMUX1_REQ_USART3_RX
  • LL_DMAMUX1_REQ_USART3_TX
  • LL_DMAMUX1_REQ_TIM8_CH1
  • LL_DMAMUX1_REQ_TIM8_CH2
  • LL_DMAMUX1_REQ_TIM8_CH3
  • LL_DMAMUX1_REQ_TIM8_CH4
  • LL_DMAMUX1_REQ_TIM8_UP
  • LL_DMAMUX1_REQ_TIM8_TRIG
  • LL_DMAMUX1_REQ_TIM8_COM
  • LL_DMAMUX1_REQ_TIM5_CH1
  • LL_DMAMUX1_REQ_TIM5_CH2
  • LL_DMAMUX1_REQ_TIM5_CH3
  • LL_DMAMUX1_REQ_TIM5_CH4
  • LL_DMAMUX1_REQ_TIM5_UP
  • LL_DMAMUX1_REQ_TIM5_TRIG
  • LL_DMAMUX1_REQ_SPI3_RX
  • LL_DMAMUX1_REQ_SPI3_TX
  • LL_DMAMUX1_REQ_UART4_RX
  • LL_DMAMUX1_REQ_UART4_TX
  • LL_DMAMUX1_REQ_UART5_RX
  • LL_DMAMUX1_REQ_UART5_TX
  • LL_DMAMUX1_REQ_DAC1_CH1
  • LL_DMAMUX1_REQ_DAC1_CH2
  • LL_DMAMUX1_REQ_TIM6_UP
  • LL_DMAMUX1_REQ_TIM7_UP
  • LL_DMAMUX1_REQ_USART6_RX
  • LL_DMAMUX1_REQ_USART6_TX
  • LL_DMAMUX1_REQ_I2C3_RX
  • LL_DMAMUX1_REQ_I2C3_TX
  • LL_DMAMUX1_REQ_DCMI_PSSI
  • LL_DMAMUX1_REQ_CRYP_IN
  • LL_DMAMUX1_REQ_CRYP_OUT
  • LL_DMAMUX1_REQ_HASH_IN
  • LL_DMAMUX1_REQ_UART7_RX
  • LL_DMAMUX1_REQ_UART7_TX
  • LL_DMAMUX1_REQ_UART8_RX
  • LL_DMAMUX1_REQ_UART8_TX
  • LL_DMAMUX1_REQ_SPI4_RX
  • LL_DMAMUX1_REQ_SPI4_TX
  • LL_DMAMUX1_REQ_SPI5_RX
  • LL_DMAMUX1_REQ_SPI5_TX
  • LL_DMAMUX1_REQ_SAI1_A
  • LL_DMAMUX1_REQ_SAI1_B
  • LL_DMAMUX1_REQ_SAI2_A
  • LL_DMAMUX1_REQ_SAI2_B
  • LL_DMAMUX1_REQ_SWPMI_RX
  • LL_DMAMUX1_REQ_SWPMI_TX
  • LL_DMAMUX1_REQ_SPDIF_RX_DT
  • LL_DMAMUX1_REQ_SPDIF_RX_CS
  • LL_DMAMUX1_REQ_HRTIM_MASTER (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
  • LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
  • LL_DMAMUX1_REQ_DFSDM1_FLT0
  • LL_DMAMUX1_REQ_DFSDM1_FLT1
  • LL_DMAMUX1_REQ_DFSDM1_FLT2
  • LL_DMAMUX1_REQ_DFSDM1_FLT3
  • LL_DMAMUX1_REQ_TIM15_CH1
  • LL_DMAMUX1_REQ_TIM15_UP
  • LL_DMAMUX1_REQ_TIM15_TRIG
  • LL_DMAMUX1_REQ_TIM15_COM
  • LL_DMAMUX1_REQ_TIM16_CH1
  • LL_DMAMUX1_REQ_TIM16_UP
  • LL_DMAMUX1_REQ_TIM17_CH1
  • LL_DMAMUX1_REQ_TIM17_UP
  • LL_DMAMUX1_REQ_SAI3_A (*)
  • LL_DMAMUX1_REQ_SAI3_B (*)
  • LL_DMAMUX1_REQ_ADC3 (*)
  • LL_DMAMUX1_REQ_UART9_RX (*)
  • LL_DMAMUX1_REQ_UART9_TX (*)
  • LL_DMAMUX1_REQ_USART10_RX (*)
  • LL_DMAMUX1_REQ_USART10_TX (*)
  • LL_DMAMUX2_REQ_MEM2MEM
  • LL_DMAMUX2_REQ_GENERATOR0
  • LL_DMAMUX2_REQ_GENERATOR1
  • LL_DMAMUX2_REQ_GENERATOR2
  • LL_DMAMUX2_REQ_GENERATOR3
  • LL_DMAMUX2_REQ_GENERATOR4
  • LL_DMAMUX2_REQ_GENERATOR5
  • LL_DMAMUX2_REQ_GENERATOR6
  • LL_DMAMUX2_REQ_GENERATOR7
  • LL_DMAMUX2_REQ_LPUART1_RX
  • LL_DMAMUX2_REQ_LPUART1_TX
  • LL_DMAMUX2_REQ_SPI6_RX
  • LL_DMAMUX2_REQ_SPI6_TX
  • LL_DMAMUX2_REQ_I2C4_RX
  • LL_DMAMUX2_REQ_I2C4_TX
  • LL_DMAMUX2_REQ_SAI4_A (*)
  • LL_DMAMUX2_REQ_SAI4_B (*)
  • LL_DMAMUX2_REQ_ADC3 (*)
  • LL_DMAMUX2_REQ_DAC2_CH1 (*)
  • LL_DMAMUX2_REQ_DFSDM2 (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 674 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestSignalID
 | ) |  |

Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
RequestSignalID This parameter can be one of the following values:
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
  • LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
  • LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
  • LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
  • LL_DMAMUX1_REQ_GEN_EXTI0
  • LL_DMAMUX1_REQ_GEN_TIM12_TRGO
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
  • LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
  • LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
  • LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
  • LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
  • LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
  • LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
  • LL_DMAMUX2_REQ_GEN_I2C4_WKUP
  • LL_DMAMUX2_REQ_GEN_SPI6_WKUP
  • LL_DMAMUX2_REQ_GEN_COMP1_OUT
  • LL_DMAMUX2_REQ_GEN_COMP2_OUT
  • LL_DMAMUX2_REQ_GEN_RTC_WKUP
  • LL_DMAMUX2_REQ_GEN_EXTI0
  • LL_DMAMUX2_REQ_GEN_EXTI2
  • LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
  • LL_DMAMUX2_REQ_GEN_SPI6_IT
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
  • LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
  • LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
  • LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
  • LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 1490 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | SyncID
 | ) |  |

Set DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_SetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
SyncID This parameter can be one of the following values:
  • LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
  • LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
  • LL_DMAMUX1_SYNC_LPTIM1_OUT
  • LL_DMAMUX1_SYNC_LPTIM2_OUT
  • LL_DMAMUX1_SYNC_LPTIM3_OUT
  • LL_DMAMUX1_SYNC_EXTI0
  • LL_DMAMUX1_SYNC_TIM12_TRGO
  • LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
  • LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
  • LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
  • LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
  • LL_DMAMUX2_SYNC_LPTIM2_OUT
  • LL_DMAMUX2_SYNC_LPTIM3_OUT
  • LL_DMAMUX2_SYNC_I2C4_WKUP
  • LL_DMAMUX2_SYNC_SPI6_WKUP
  • LL_DMAMUX2_SYNC_COMP1_OUT
  • LL_DMAMUX2_SYNC_RTC_WKUP
  • LL_DMAMUX2_SYNC_EXTI0
  • LL_DMAMUX2_SYNC_EXTI2
Return values:
None

Definition at line 1213 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_SetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING
Return values:
None

Definition at line 944 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 879 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO14 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 14.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO15 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 15.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 4 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 5 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 6 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 7 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO14 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 14.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO15 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 15.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 4 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 5 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 6 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 7 Trigger Event Overrun Flag.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2077 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2090 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2103 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2116 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 4 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2129 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 5 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2142 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 6 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2155 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 7 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2168 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1869 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1882 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1999 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2012 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 12.

Reference Manual to LL API cross reference:
CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2025 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 13.

Reference Manual to LL API cross reference:
CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2038 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 14.

Reference Manual to LL API cross reference:
CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2051 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 15.

Reference Manual to LL API cross reference:
CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 2064 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1895 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1908 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1921 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1934 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1947 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1960 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1973 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1986 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1765 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1778 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1791 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1804 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 4 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1817 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 5 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1830 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 6 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1843 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 7 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1856 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1557 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1570 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1687 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1700 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 12.

Reference Manual to LL API cross reference:
CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1713 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 13.

Reference Manual to LL API cross reference:
CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1726 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 14.

Reference Manual to LL API cross reference:
CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1739 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 15.

Reference Manual to LL API cross reference:
CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1752 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1583 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1596 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1609 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1622 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1635 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1648 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1661 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1674 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CH_STATUS_OFFSET.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_DisableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
None

Definition at line 2310 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_DisableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 2236 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_EnableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
None

Definition at line 2288 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_EnableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 2206 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
  • LL_DMAMUX_REQ_GEN_4
  • LL_DMAMUX_REQ_GEN_5
  • LL_DMAMUX_REQ_GEN_6
  • LL_DMAMUX_REQ_GEN_7
Return values:
State of bit (1 or 0).

Definition at line 2332 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_REQ_GEN_OFFSET, and DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 2266 of file stm32h7xx_ll_dmamux.h.

References DMAMUX_CCR_SIZE.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 47 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_32_63 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)

Definition at line 48 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_64_95 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)

Definition at line 49 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 51 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 56 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32h7xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
uint32_t | Line_32_63
uint32_t | Line_64_95
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 58 of file stm32h7xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 61 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_32_63

Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of LINE

Definition at line 64 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_64_95

Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 This parameter can be any combination of LINE

Definition at line 67 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 70 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 73 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 76 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_exti.h
Generated on Tue Nov 12 2019 18:50:41 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_42 EXTI_IMR2_IM42
#define | LL_EXTI_LINE_43 EXTI_IMR2_IM43
#define | LL_EXTI_LINE_47 EXTI_IMR2_IM47
#define | LL_EXTI_LINE_48 EXTI_IMR2_IM48
#define | LL_EXTI_LINE_49 EXTI_IMR2_IM49
#define | LL_EXTI_LINE_50 EXTI_IMR2_IM50
#define | LL_EXTI_LINE_51 EXTI_IMR2_IM51
#define | LL_EXTI_LINE_52 EXTI_IMR2_IM52
#define | LL_EXTI_LINE_53 EXTI_IMR2_IM53
#define | LL_EXTI_LINE_54 EXTI_IMR2_IM54
#define | LL_EXTI_LINE_55 EXTI_IMR2_IM55
#define | LL_EXTI_LINE_56 EXTI_IMR2_IM56
#define | LL_EXTI_LINE_57 EXTI_IMR2_IM57
#define | LL_EXTI_LINE_58 EXTI_IMR2_IM58
#define | LL_EXTI_LINE_59 EXTI_IMR2_IM59
#define | LL_EXTI_LINE_60 EXTI_IMR2_IM60
#define | LL_EXTI_LINE_61 EXTI_IMR2_IM61
#define | LL_EXTI_LINE_62 EXTI_IMR2_IM62
#define | LL_EXTI_LINE_63 EXTI_IMR2_IM63
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_64 EXTI_IMR3_IM64
#define | LL_EXTI_LINE_65 EXTI_IMR3_IM65
#define | LL_EXTI_LINE_66 EXTI_IMR3_IM66
#define | LL_EXTI_LINE_67 EXTI_IMR3_IM67
#define | LL_EXTI_LINE_68 EXTI_IMR3_IM68
#define | LL_EXTI_LINE_69 EXTI_IMR3_IM69
#define | LL_EXTI_LINE_70 EXTI_IMR3_IM70
#define | LL_EXTI_LINE_71 EXTI_IMR3_IM71
#define | LL_EXTI_LINE_72 EXTI_IMR3_IM72
#define | LL_EXTI_LINE_73 EXTI_IMR3_IM73
#define | LL_EXTI_LINE_74 EXTI_IMR3_IM74
#define | LL_EXTI_LINE_85 EXTI_IMR3_IM85
#define | LL_EXTI_LINE_87 EXTI_IMR3_IM87
#define | LL_EXTI_LINE_88 EXTI_IMR3_IM88
#define | LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR1_IM0

Extended line 0

Definition at line 93 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR1_IM1

Extended line 1

Definition at line 94 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR1_IM10

Extended line 10

Definition at line 103 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR1_IM11

Extended line 11

Definition at line 104 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR1_IM12

Extended line 12

Definition at line 105 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR1_IM13

Extended line 13

Definition at line 106 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR1_IM14

Extended line 14

Definition at line 107 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR1_IM15

Extended line 15

Definition at line 108 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR1_IM16

Extended line 16

Definition at line 109 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR1_IM17

Extended line 17

Definition at line 110 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR1_IM18

Extended line 18

Definition at line 111 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR1_IM19

Extended line 19

Definition at line 112 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR1_IM2

Extended line 2

Definition at line 95 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR1_IM20

Extended line 20

Definition at line 113 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR1_IM21

Extended line 21

Definition at line 114 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR1_IM22

Extended line 22

Definition at line 115 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR1_IM23

Extended line 23

Definition at line 116 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR1_IM24

Extended line 24

Definition at line 117 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR1_IM25

Extended line 25

Definition at line 118 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_26 EXTI_IMR1_IM26

Extended line 26

Definition at line 119 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_27 EXTI_IMR1_IM27

Extended line 27

Definition at line 120 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR1_IM28

Extended line 28

Definition at line 121 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_29 EXTI_IMR1_IM29

Extended line 29

Definition at line 122 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR1_IM3

Extended line 3

Definition at line 96 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_30 EXTI_IMR1_IM30

Extended line 30

Definition at line 123 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_31 EXTI_IMR1_IM31

Extended line 31

Definition at line 124 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_32 EXTI_IMR2_IM32

Extended line 32

Definition at line 127 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_33 EXTI_IMR2_IM33

Extended line 33

Definition at line 128 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_34 EXTI_IMR2_IM34

Extended line 34

Definition at line 129 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_35 EXTI_IMR2_IM35

Extended line 35

Definition at line 130 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_36 EXTI_IMR2_IM36

Extended line 36

Definition at line 131 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_37 EXTI_IMR2_IM37

Extended line 37

Definition at line 132 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_38 EXTI_IMR2_IM38

Extended line 38

Definition at line 133 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_39 EXTI_IMR2_IM39

Extended line 39

Definition at line 134 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR1_IM4

Extended line 4

Definition at line 97 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_40 EXTI_IMR2_IM40

Extended line 40

Definition at line 135 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_41 EXTI_IMR2_IM41

Extended line 41

Definition at line 136 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_42 EXTI_IMR2_IM42

Extended line 42

Definition at line 137 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_43 EXTI_IMR2_IM43

Extended line 43

Definition at line 138 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_47 EXTI_IMR2_IM47

Extended line 47

Definition at line 145 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_48 EXTI_IMR2_IM48

Extended line 48

Definition at line 146 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_49 EXTI_IMR2_IM49

Extended line 49

Definition at line 147 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR1_IM5

Extended line 5

Definition at line 98 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_50 EXTI_IMR2_IM50

Extended line 50

Definition at line 148 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_51 EXTI_IMR2_IM51

Extended line 51

Definition at line 149 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_52 EXTI_IMR2_IM52

Extended line 52

Definition at line 150 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_53 EXTI_IMR2_IM53

Extended line 53

Definition at line 151 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_54 EXTI_IMR2_IM54

Extended line 54

Definition at line 152 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_55 EXTI_IMR2_IM55

Extended line 55

Definition at line 153 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_56 EXTI_IMR2_IM56

Extended line 56

Definition at line 154 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_57 EXTI_IMR2_IM57

Extended line 57

Definition at line 155 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_58 EXTI_IMR2_IM58

Extended line 58

Definition at line 156 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_59 EXTI_IMR2_IM59

Extended line 59

Definition at line 157 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR1_IM6

Extended line 6

Definition at line 99 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_60 EXTI_IMR2_IM60

Extended line 60

Definition at line 158 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_61 EXTI_IMR2_IM61

Extended line 61

Definition at line 159 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_62 EXTI_IMR2_IM62

Extended line 62

Definition at line 160 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_63 EXTI_IMR2_IM63

Extended line 63

Definition at line 161 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_64 EXTI_IMR3_IM64

Extended line 64

Definition at line 164 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_65 EXTI_IMR3_IM65

Extended line 65

Definition at line 165 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_66 EXTI_IMR3_IM66

Extended line 66

Definition at line 166 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_67 EXTI_IMR3_IM67

Extended line 67

Definition at line 167 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_68 EXTI_IMR3_IM68

Extended line 68

Definition at line 168 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_69 EXTI_IMR3_IM69

Extended line 69

Definition at line 169 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR1_IM7

Extended line 7

Definition at line 100 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_70 EXTI_IMR3_IM70

Extended line 70

Definition at line 170 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_71 EXTI_IMR3_IM71

Extended line 71

Definition at line 171 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_72 EXTI_IMR3_IM72

Extended line 72

Definition at line 172 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_73 EXTI_IMR3_IM73

Extended line 73

Definition at line 173 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_74 EXTI_IMR3_IM74

Extended line 74

Definition at line 174 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR1_IM8

Extended line 8

Definition at line 101 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_85 EXTI_IMR3_IM85

Extended line 85

Definition at line 189 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_87 EXTI_IMR3_IM87

Extended line 87

Definition at line 193 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_88 EXTI_IMR3_IM88

Extended line 87

Definition at line 195 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR1_IM9

Extended line 9

Definition at line 102 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_ALL (0xFFFFFFFFU)

All Extended line

Definition at line 200 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM

All Extended line not reserved

Definition at line 125 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM

All Extended line not reserved

Definition at line 162 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM

All Extended line not reserved

Definition at line 197 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_LINE_NONE (0x00000000U)

None Extended line

Definition at line 203 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U)

Cortex-M7 Event Mode

Definition at line 215 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x01U)

Cortex-M7 Interrupt Mode

Definition at line 214 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U)

Cortex-M7 Interrupt & Event Mode

Definition at line 216 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 237 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 235 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 236 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 238 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: D3 Pend Clear Source

Defines
D3 Pend Clear Source
EXTI Exported Constants

Defines

#define | LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U)
#define | LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U)
#define | LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U)
#define | LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U)

DMA ch6 event selected as D3 domain pendclear source

Definition at line 247 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U)

DMA ch7 event selected as D3 domain pendclear source

Definition at line 248 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U)

LPTIM2 out selected as D3 domain pendclear source

Definition at line 252 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U)

LPTIM3 out selected as D3 domain pendclear source

Definition at line 257 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 293 of file stm32h7xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 286 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableIT_64_95 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_64_95 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_64_95 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 476 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 520 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_64_95 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
IMR3 IMx LL_EXTI_DisableIT_64_95
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
None

Definition at line 554 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 353 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 396 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_64_95 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
IMR3 IMx LL_EXTI_EnableIT_64_95
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
None

Definition at line 431 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
State of bit (1 or 0).

Definition at line 599 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 643 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
IMR3 IMx LL_EXTI_IsEnabledIT_64_95
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
State of bit (1 or 0).

Definition at line 678 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableEvent_64_95 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_64_95 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_64_95 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 1227 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 1270 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_64_95 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
EMR3 EMx LL_EXTI_DisableEvent_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
None

Definition at line 1304 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 1106 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 1149 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_64_95 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
EMR3 EMx LL_EXTI_EnableEvent_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
None

Definition at line 1183 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1349 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_47
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
  • LL_EXTI_LINE_54
  • LL_EXTI_LINE_55
  • LL_EXTI_LINE_56
  • LL_EXTI_LINE_57
  • LL_EXTI_LINE_58
  • LL_EXTI_LINE_59
  • LL_EXTI_LINE_60
  • LL_EXTI_LINE_61
  • LL_EXTI_LINE_62
  • LL_EXTI_LINE_63
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 1392 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
EMR3 EMx LL_EXTI_IsEnabledEvent_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_64
  • LL_EXTI_LINE_65
  • LL_EXTI_LINE_66
  • LL_EXTI_LINE_67
  • LL_EXTI_LINE_68
  • LL_EXTI_LINE_69
  • LL_EXTI_LINE_70
  • LL_EXTI_LINE_71
  • LL_EXTI_LINE_72
  • LL_EXTI_LINE_73
  • LL_EXTI_LINE_74
  • LL_EXTI_LINE_75
  • LL_EXTI_LINE_76
  • LL_EXTI_LINE_77
  • LL_EXTI_LINE_78
  • LL_EXTI_LINE_79
  • LL_EXTI_LINE_80
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_87
  • LL_EXTI_LINE_ALL_64_95
Return values:
State of bit (1 or 0).

Definition at line 1426 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_64_95 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_64_95 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_64_95 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 64 to 95.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Return values:
None

Definition at line 1931 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 1952 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 1974 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Return values:
None

Definition at line 1850 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 1870 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 1891 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Return values:
State of bit (1 or 0).

Definition at line 2007 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
State of bit (1 or 0).

Definition at line 2021 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
State of bit (1 or 0).

Definition at line 2036 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_64_95 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_64_95 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_64_95 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 64 to 95.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 2166 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 2185 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 2206 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 2084 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 2104 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 2126 of file stm32h7xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 2240 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
State of bit (1 or 0).

Definition at line 2253 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 64 to 95.

Reference Manual to LL API cross reference:
FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
State of bit (1 or 0).

Definition at line 2268 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_64_95 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 64 to 95.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR1 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 2315 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 32 to 63.

Note:
If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR2 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 2333 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 64 to 95.

Note:
If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR3 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER3 SWIx LL_EXTI_GenerateSWI_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 2353 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_64_95 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_64_95 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_64_95 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 64 to 95.
__STATIC_INLINE void | LL_D3_EXTI_EnablePendMask_0_31 (uint32_t ExtiLine)
Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31.
__STATIC_INLINE void | LL_D3_EXTI_EnablePendMask_32_63 (uint32_t ExtiLine)
Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63.
__STATIC_INLINE void | LL_D3_EXTI_DisablePendMask_0_31 (uint32_t ExtiLine)
Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31.
__STATIC_INLINE void | LL_D3_EXTI_DisablePendMask_32_63 (uint32_t ExtiLine)
Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_D3_EXTI_IsEnabledPendMask_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_D3_EXTI_IsEnabledPendMask_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_0_15 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_16_31 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_32_47 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_48_63 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_0_15 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_16_31 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_32_47 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_48_63 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.

Function Documentation

__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31 ( uint32_t ExtiLine )

Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
D3PMR1 MRx LL_D3_EXTI_DisablePendMask_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_25
Return values:
None

Definition at line 2859 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63 ( uint32_t ExtiLine )

Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
D3PMR2 MRx LL_D3_EXTI_DisablePendMask_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
Return values:
None

Definition at line 2879 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31 ( uint32_t ExtiLine )

Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
D3PMR1 MRx LL_D3_EXTI_EnablePendMask_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_25
Return values:
None

Definition at line 2808 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63 ( uint32_t ExtiLine )

Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
D3PMR2 MRx LL_D3_EXTI_EnablePendMask_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
Return values:
None

Definition at line 2828 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15 ( uint32_t ExtiLine )

Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.

Reference Manual to LL API cross reference:
D3PCR1L PCSx LL_D3_EXTI_GetPendClearSel_0_15
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
Return values:
Returned value can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5

Definition at line 3055 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31 ( uint32_t ExtiLine )

Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.

Reference Manual to LL API cross reference:
D3PCR1H PCSx LL_D3_EXTI_GetPendClearSel_16_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_25
Return values:
Returned value can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5

Definition at line 3074 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47 ( uint32_t ExtiLine )

Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.

Reference Manual to LL API cross reference:
D3PCR2L PCSx LL_D3_EXTI_GetPendClearSel_32_47
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_41
Return values:
Returned value can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5

Definition at line 3092 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63 ( uint32_t ExtiLine )

Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.

Reference Manual to LL API cross reference:
D3PCR2H PCSx LL_D3_EXTI_GetPendClearSel_48_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
Return values:
Returned value can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5

Definition at line 3113 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
D3PMR1 MRx LL_D3_EXTI_IsEnabledPendMask_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_25
Return values:
State of bit (1 or 0).

Definition at line 2910 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
D3PMR2 MRx LL_D3_EXTI_IsEnabledPendMask_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
Return values:
State of bit (1 or 0).

Definition at line 2930 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15 | ( | uint32_t | ExtiLine,
 |  | uint32_t | ClrSrc
 | ) |  |

Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.

Reference Manual to LL API cross reference:
D3PCR1L PCSx LL_D3_EXTI_SetPendClearSel_0_15
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
ClrSrc This parameter can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5
Return values:
None

Definition at line 2962 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31 | ( | uint32_t | ExtiLine,
 |  | uint32_t | ClrSrc
 | ) |  |

Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.

Reference Manual to LL API cross reference:
D3PCR1H PCSx LL_D3_EXTI_SetPendClearSel_16_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_25
ClrSrc This parameter can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5
Return values:
None

Definition at line 2982 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47 | ( | uint32_t | ExtiLine,
 |  | uint32_t | ClrSrc
 | ) |  |

Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.

Reference Manual to LL API cross reference:
D3PCR2L PCSx LL_D3_EXTI_SetPendClearSel_32_47
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_41
ClrSrc This parameter can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5
Return values:
None

Definition at line 3002 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63 | ( | uint32_t | ExtiLine,
 |  | uint32_t | ClrSrc
 | ) |  |

Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.

Reference Manual to LL API cross reference:
D3PCR2H PCSx LL_D3_EXTI_SetPendClearSel_48_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_50
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_52
  • LL_EXTI_LINE_53
ClrSrc This parameter can be one of the following values:
  • LL_EXTI_D3_PEND_CLR_DMACH6
  • LL_EXTI_D3_PEND_CLR_DMACH7
  • LL_EXTI_D3_PEND_CLR_LPTIM4
  • LL_EXTI_D3_PEND_CLR_LPTIM5
Return values:
None

Definition at line 3024 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Return values:
None

Definition at line 2537 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_ClearFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ClearFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
None

Definition at line 2552 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_ClearFlag_64_95 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 64 to 95.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR3 PIFx LL_EXTI_ClearFlag_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
None

Definition at line 2569 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Return values:
State of bit (1 or 0).

Definition at line 2398 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_IsActiveFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 2414 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 64 to 95.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR3 PIFx LL_EXTI_IsActiveFlag_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
  • LL_EXTI_LINE_ALL_64_95
Return values:
State of bit (1 or 0).

Definition at line 2432 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 2468 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ReadFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_49
  • LL_EXTI_LINE_51
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 2484 of file stm32h7xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 64 to 95.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR3 PIFx LL_EXTI_ReadFlag_64_95
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_82
  • LL_EXTI_LINE_84
  • LL_EXTI_LINE_85
  • LL_EXTI_LINE_86
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 2502 of file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

, More...

Functions

ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

,

Function Documentation

ErrorStatus LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are de-initialized
  • ERROR: not applicable

Definition at line 82 of file stm32h7xx_ll_exti.c.

References LL_EXTI_WriteReg.

ErrorStatus LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are initialized
  • ERROR: not applicable

Definition at line 156 of file stm32h7xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_LINE_32_63, IS_LL_EXTI_LINE_64_95, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::Line_64_95, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableEvent_64_95(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableFallingTrig_32_63(), LL_EXTI_DisableFallingTrig_64_95(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableIT_64_95(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_DisableRisingTrig_32_63(), LL_EXTI_DisableRisingTrig_64_95(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableEvent_64_95(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableFallingTrig_32_63(), LL_EXTI_EnableFallingTrig_64_95(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableIT_64_95(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_EnableRisingTrig_32_63(), LL_EXTI_EnableRisingTrig_64_95(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 428 of file stm32h7xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::Line_64_95, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_15 ))

Definition at line 67 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 50 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 55 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 48 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 63 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 58 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32h7xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 64 of file stm32h7xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 89 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 69 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 79 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 66 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 84 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 74 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_gpio.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS0

Select pin 0

Definition at line 108 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS1

Select pin 1

Definition at line 109 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS10

Select pin 10

Definition at line 118 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS11

Select pin 11

Definition at line 119 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS12

Select pin 12

Definition at line 120 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS13

Select pin 13

Definition at line 121 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS14

Select pin 14

Definition at line 122 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS15

Select pin 15

Definition at line 123 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS2

Select pin 2

Definition at line 110 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS3

Select pin 3

Definition at line 111 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS4

Select pin 4

Definition at line 112 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS5

Select pin 5

Definition at line 113 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS6

Select pin 6

Definition at line 114 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS7

Select pin 7

Definition at line 115 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS8

Select pin 8

Definition at line 116 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_PIN_9 GPIO_BSRR_BS9

Select pin 9

Definition at line 117 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
                                           GPIO_BSRR_BS15)

Select all pins

Definition at line 124 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1

Select alternate function mode

Definition at line 139 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Select analog mode

Definition at line 140 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT (0x00000000U)

Select input mode

Definition at line 137 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0

Select output mode

Definition at line 138 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Select open-drain as output type

Definition at line 149 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)

Select push-pull as output type

Definition at line 148 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1

Select I/O fast output speed

Definition at line 159 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U)

Select I/O low output speed

Definition at line 157 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0

Select I/O medium output speed

Definition at line 158 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Select I/O high output speed

Definition at line 160 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Select I/O pull down

Definition at line 175 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_PULL_NO (0x00000000U)

Select I/O no pull

Definition at line 173 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0

Select I/O pull up

Definition at line 174 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)

Define Documentation

#define LL_GPIO_AF_0 (0x0000000U)

Select alternate function 0

Definition at line 183 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 (0x0000001U)

Select alternate function 1

Definition at line 184 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_10 (0x000000AU)

Select alternate function 10

Definition at line 193 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_11 (0x000000BU)

Select alternate function 11

Definition at line 194 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_12 (0x000000CU)

Select alternate function 12

Definition at line 195 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_13 (0x000000DU)

Select alternate function 13

Definition at line 196 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_14 (0x000000EU)

Select alternate function 14

Definition at line 197 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_15 (0x000000FU)

Select alternate function 15

Definition at line 198 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_2 (0x0000002U)

Select alternate function 2

Definition at line 185 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_3 (0x0000003U)

Select alternate function 3

Definition at line 186 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_4 (0x0000004U)

Select alternate function 4

Definition at line 187 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_5 (0x0000005U)

Select alternate function 5

Definition at line 188 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_6 (0x0000006U)

Select alternate function 6

Definition at line 189 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_7 (0x0000007U)

Select alternate function 7

Definition at line 190 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_8 (0x0000008U)

Select alternate function 8

Definition at line 191 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_AF_9 (0x0000009U)

Select alternate function 9

Definition at line 192 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Exported Constants

Modules | Defines
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function

Defines

#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Define Documentation

#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH

Definition at line 166 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 167 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW

Definition at line 164 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM

Definition at line 165 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 231 of file stm32h7xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 223 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 595 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 673 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 313 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 381 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 519 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 454 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 756 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 745 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 710 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 558 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 635 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 279 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 347 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 487 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH
Return values:
None

Definition at line 418 of file stm32h7xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 804 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 856 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 775 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 827 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 914 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 885 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 943 of file stm32h7xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 816 of file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 105 of file stm32h7xx_ll_gpio.c.

References assert_param, LL_AHB4_GRP1_ForceReset(), LL_AHB4_GRP1_PERIPH_GPIOA, LL_AHB4_GRP1_PERIPH_GPIOB, LL_AHB4_GRP1_PERIPH_GPIOC, LL_AHB4_GRP1_PERIPH_GPIOD, LL_AHB4_GRP1_PERIPH_GPIOE, LL_AHB4_GRP1_PERIPH_GPIOF, LL_AHB4_GRP1_PERIPH_GPIOG, LL_AHB4_GRP1_PERIPH_GPIOH, LL_AHB4_GRP1_PERIPH_GPIOI, LL_AHB4_GRP1_PERIPH_GPIOJ, LL_AHB4_GRP1_PERIPH_GPIOK, and LL_AHB4_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx | GPIO Port
GPIO_InitStruct | pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 201 of file stm32h7xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_PIN_8, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 276 of file stm32h7xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: COREID Defines

Defines
COREID Defines
HSEM Exported Constants

Defines

#define | LL_HSEM_COREID_NONE 0U
#define | LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
#define | LL_HSEM_COREID HSEM_CR_COREID_CURRENT

Define Documentation

#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT

Definition at line 61 of file stm32h7xx_ll_hsem.h.

Referenced by LL_HSEM_1StepLock(), LL_HSEM_2StepLock(), LL_HSEM_ReleaseLock(), and LL_HSEM_SetLock().

#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1

Definition at line 57 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_COREID_NONE 0U

Definition at line 56 of file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
HSEM Exported Constants

Flags defines which can be used with LL_HSEM_ReadReg function. More...

Defines

#define | LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
#define | LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
#define | LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
#define | LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
#define | LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
#define | LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
#define | LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
#define | LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
#define | LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
#define | LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
#define | LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
#define | LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
#define | LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
#define | LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
#define | LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
#define | LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
#define | LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU

Detailed Description

Flags defines which can be used with LL_HSEM_ReadReg function.

Define Documentation

#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0

Definition at line 71 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1

Definition at line 72 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10

Definition at line 81 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11

Definition at line 82 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12

Definition at line 83 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13

Definition at line 84 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14

Definition at line 85 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15

Definition at line 86 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2

Definition at line 73 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3

Definition at line 74 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4

Definition at line 75 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5

Definition at line 76 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6

Definition at line 77 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7

Definition at line 78 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8

Definition at line 79 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9

Definition at line 80 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU

Definition at line 88 of file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
HSEM Exported Macros

Defines

#define | LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in HSEM register.
#define | LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in HSEM register.

Define Documentation

#define LL_HSEM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in HSEM register.

Parameters:
__INSTANCE__ | HSEM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 140 of file stm32h7xx_ll_hsem.h.

#define LL_HSEM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in HSEM register.

Parameters:
__INSTANCE__ | HSEM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 132 of file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
HSEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_HSEM_IsSemaphoreLocked (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Return 1 if the semaphore is locked, else return 0.
__STATIC_INLINE uint32_t | LL_HSEM_GetCoreId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get core id.
__STATIC_INLINE uint32_t | LL_HSEM_GetProcessId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get process id.
__STATIC_INLINE void | LL_HSEM_SetLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock by writing in R register.
__STATIC_INLINE uint32_t | LL_HSEM_2StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock with 2-step lock.
__STATIC_INLINE uint32_t | LL_HSEM_1StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock with 1-step lock.
__STATIC_INLINE void | LL_HSEM_ReleaseLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Release the lock of the semaphore.
__STATIC_INLINE uint32_t | LL_HSEM_GetStatus (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock status of the semaphore.
__STATIC_INLINE void | LL_HSEM_SetKey (HSEM_TypeDef *HSEMx, uint32_t key)
Set the key.
__STATIC_INLINE uint32_t | LL_HSEM_GetKey (HSEM_TypeDef *HSEMx)
Get the key.
__STATIC_INLINE void | LL_HSEM_ResetAllLock (HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
Release all semaphore with the same core id.

Function Documentation

__STATIC_INLINE uint32_t LL_HSEM_1StepLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get the lock with 1-step lock.

Reference Manual to LL API cross reference:
RLR LOCK LL_HSEM_1StepLock
Reference Manual to LL API cross reference:
RLR COREID LL_HSEM_1StepLock
Reference Manual to LL API cross reference:
RLR PROCID LL_HSEM_1StepLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
1 lock fail, 0 lock successful or already locked by same core

Definition at line 239 of file stm32h7xx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE uint32_t LL_HSEM_2StepLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Get the lock with 2-step lock.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_2StepLock
Reference Manual to LL API cross reference:
R COREID LL_HSEM_2StepLock
Reference Manual to LL API cross reference:
R PROCID LL_HSEM_2StepLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process id. Value between Min_Data=0 and Max_Data=255
Return values:
1 lock fail, 0 lock successful or already locked by same process and core

Definition at line 224 of file stm32h7xx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE uint32_t LL_HSEM_GetCoreId | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get core id.

Reference Manual to LL API cross reference:
R COREID LL_HSEM_GetCoreId
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
Returned value can be one of the following values:
  • LL_HSEM_COREID_NONE
  • LL_HSEM_COREID_CPU1
  • LL_HSEM_COREID_CPU2

Definition at line 181 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetKey ( HSEM_TypeDef * HSEMx )

Get the key.

Reference Manual to LL API cross reference:
KEYR KEY LL_HSEM_GetKey
Parameters:
HSEMx HSEM Instance.
Return values:
key to unlock all semaphore from the same core

Definition at line 287 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetProcessId | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get process id.

Reference Manual to LL API cross reference:
R PROCID LL_HSEM_GetProcessId
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
Process number. Value between Min_Data=0 and Max_Data=255

Definition at line 193 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetStatus | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get the lock status of the semaphore.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_GetStatus
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
0 semaphore is free, 1 semaphore is locked

Definition at line 264 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Return 1 if the semaphore is locked, else return 0.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_IsSemaphoreLocked
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
State of bit (1 or 0).

Definition at line 166 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_ReleaseLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Release the lock of the semaphore.

Note:
In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
Reference Manual to LL API cross reference:
R LOCK LL_HSEM_ReleaseLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process number. Value between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 253 of file stm32h7xx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE void LL_HSEM_ResetAllLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | key,
 |  | uint32_t | core
 | ) |  |

Release all semaphore with the same core id.

Reference Manual to LL API cross reference:
CR KEY LL_HSEM_ResetAllLock
Parameters:
HSEMx | HSEM Instance.
key | Key value.
core This parameter can be one of the following values:
  • LL_HSEM_COREID_CPU1
  • LL_HSEM_COREID_CPU2
Return values:
None

Definition at line 302 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_SetKey | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | key
 | ) |  |

Set the key.

Reference Manual to LL API cross reference:
KEYR KEY LL_HSEM_SetKey
Parameters:
HSEMx | HSEM Instance.
key | Key value.
Return values:
None

Definition at line 276 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_SetLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Get the lock by writing in R register.

Note:
The R register has to be read to determined if the lock is taken.
Reference Manual to LL API cross reference:
R LOCK LL_HSEM_SetLock
Reference Manual to LL API cross reference:
R COREID LL_HSEM_SetLock
Reference Manual to LL API cross reference:
R PROCID LL_HSEM_SetLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process id. Value between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 209 of file stm32h7xx_ll_hsem.h.

References LL_HSEM_COREID.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
HSEM Exported Functions

Functions

__STATIC_INLINE void | LL_HSEM_EnableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_HSEM_DisableIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Disable interrupt.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_DisableIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
None

Definition at line 404 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_EnableIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Enable interrupt.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_EnableIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
None

Definition at line 357 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Check if interrupt is enabled.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
State of bit (1 or 0).

Definition at line 451 of file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
HSEM Exported Functions

Functions

__STATIC_INLINE void | LL_HSEM_ClearFlag_C1ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.

Function Documentation

__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Clear interrupt status.

Reference Manual to LL API cross reference:
C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
None

Definition at line 642 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from ISR register.

Reference Manual to LL API cross reference:
C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
State of bit (1 or 0).

Definition at line 689 of file stm32h7xx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from MISR register.

Reference Manual to LL API cross reference:
C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Note:
Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 depends on devices.
Return values:
State of bit (1 or 0).

Definition at line 736 of file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 53 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 56 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 58 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 63 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 48 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 60 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32h7xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 67 of file stm32h7xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 80 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 85 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 90 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 100 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 69 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS()

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 74 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 95 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_i2c.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 119 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 127 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 123 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 122 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 120 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 124 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 125 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 121 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 126 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 139 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 149 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 145 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 144 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 150 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 140 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 146 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 147 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 138 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 141 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 142 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 143 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 148 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 136 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 137 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 161 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 165 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 162 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 160 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 163 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 164 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 159 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 173 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U

SMBus Device default mode (Default address not acknowledge)

Definition at line 175 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 176 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 174 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 185 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

Definition at line 184 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32H7B3xQ HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 194 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

Definition at line 193 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 203 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

Definition at line 202 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 212 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 213 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 214 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 215 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 216 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 217 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 218 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 211 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

Definition at line 226 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 227 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 236 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

Definition at line 235 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 245 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

Definition at line 244 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 254 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 253 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 257 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 259 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 256 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 258 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 260 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 255 of file stm32h7xx_ll_i2c.h.

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STM32H7B3xQ HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don't Generate Stop and Start condition.

Definition at line 268 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 274 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 10Bit address.

Definition at line 275 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 272 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 7Bit address.

Definition at line 273 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 270 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Start for write request.

Definition at line 271 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Generate Stop condition (Size should be set to 0).

Definition at line 269 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 284 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

Definition at line 283 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 293 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 292 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

TimeoutA is used to detect SCL low level timeout.

Definition at line 301 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 302 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 312 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 310 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 311 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 345 of file stm32h7xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 337 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __DATA_SETUP_TIME__,
 |  | __DATA_HOLD_TIME__,
 |  | __CLOCK_HIGH_PERIOD__,
 |  | __CLOCK_LOW_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF.
__DATA_SETUP_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
__DATA_HOLD_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
__CLOCK_HIGH_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
__CLOCK_LOW_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 362 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 436 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Return values:
None

Definition at line 1083 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 405 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 487 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 616 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 553 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 520 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 724 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 801 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 857 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 649 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1010 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1049 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1209 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 687 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 579 of file stm32h7xx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 391 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 475 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 604 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 542 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 509 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 712 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 790 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 846 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 638 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 992 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1036 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1191 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 674 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 915 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 904 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 926 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 937 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 463 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 763 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 974 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1113 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1145 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( I2C_TypeDef * I2Cx )

Get the SMBus Extented Cumulative Clock TimeoutB setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1173 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 893 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 416 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 498 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 627 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 564 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 531 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 735 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 812 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 868 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 660 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1023 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1062 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1227 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 700 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 452 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 750 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 956 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 779 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between Min_Data=0 and Max_Data=0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 835 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1100 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1130 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1160 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 882 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1323 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1479 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1356 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1290 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1389 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1428 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1257 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1312 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1459 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1345 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1279 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1378 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1414 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1246 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1334 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1490 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1367 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1301 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1400 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1439 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1268 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1711 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1767 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1756 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1722 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1778 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1733 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1745 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1817 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1791 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1804 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1550 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1628 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1615 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1700 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1563 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1641 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1537 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1576 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1589 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1511 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1524 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1687 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1671 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1935 of file stm32h7xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1984 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1850 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1885 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1972 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1838 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1873 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2135 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1948 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1959 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2119 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2047 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2161 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2108 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2023 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1920 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between Min_Data=0 and Max_Data=255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2090 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1995 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1861 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1896 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte internal comparison is requested or not.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2148 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2172 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2036 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2010 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1909 of file stm32h7xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2184 of file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 87 of file stm32h7xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, LL_APB1_GRP1_PERIPH_I2C3, LL_APB1_GRP1_ReleaseReset(), LL_APB4_GRP1_ForceReset(), LL_APB4_GRP1_PERIPH_I2C4, and LL_APB4_GRP1_ReleaseReset().

ErrorStatus LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 143 of file stm32h7xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 211 of file stm32h7xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 49 of file stm32h7xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 48 of file stm32h7xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 51 of file stm32h7xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 50 of file stm32h7xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 68 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 69 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 70 of file stm32h7xx_ll_iwdg.h.

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STM32H7B3xQ HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 83 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 80 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 84 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 81 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 78 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 82 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 79 of file stm32h7xx_ll_iwdg.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 117 of file stm32h7xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 109 of file stm32h7xx_ll_iwdg.h.

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STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 175 of file stm32h7xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 142 of file stm32h7xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 164 of file stm32h7xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 212 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 235 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 258 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 153 of file stm32h7xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 194 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 224 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 247 of file stm32h7xx_ll_iwdg.h.

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STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 277 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 288 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 299 of file stm32h7xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 312 of file stm32h7xx_ll_iwdg.h.

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STM32H7B3xQ HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Define Documentation

#define IS_LL_LPTIM_CLOCK_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))

Definition at line 53 of file stm32h7xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_CLOCK_SOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
                                          || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))

Definition at line 50 of file stm32h7xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_OUTPUT_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
                                             || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))

Definition at line 65 of file stm32h7xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_WAVEFORM ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
                                      || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))

Definition at line 62 of file stm32h7xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

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STM32H7B3xQ HAL User Manual: LL_LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPTIM_InitTypeDef Struct Reference
LPTIM Exported Init structure

LPTIM Init structure definition. More...

#include <stm32h7xx_ll_lptim.h>

Data Fields

uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | Waveform
uint32_t | Polarity

Detailed Description

LPTIM Init structure definition.

Definition at line 65 of file stm32h7xx_ll_lptim.h.

Field Documentation

uint32_t LL_LPTIM_InitTypeDef::ClockSource

Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of Clock Source.

This feature can be modified afterwards using unitary function LL_LPTIM_SetClockSource().

Definition at line 67 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Polarity

Specifies waveform polarity. This parameter can be a value of Output Polarity.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 82 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Prescaler

Specifies the prescaler division ratio. This parameter can be a value of Prescaler Value.

This feature can be modified afterwards using using unitary function LL_LPTIM_SetPrescaler().

Definition at line 72 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Waveform

Specifies the waveform shape. This parameter can be a value of Output Waveform Type.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 77 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_lptim.h
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STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPTIM Exported Constants

Flags defines which can be used with LL_LPTIM_ReadReg function. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Detailed Description

Flags defines which can be used with LL_LPTIM_ReadReg function.

Define Documentation

#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

Definition at line 103 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

Definition at line 106 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM

Compare match

Definition at line 102 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK

Compare register update OK

Definition at line 105 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

Definition at line 108 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

Definition at line 104 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

Definition at line 107 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
LPTIM Exported Constants

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions. More...

Defines

#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Detailed Description

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Define Documentation

#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE

Autoreload match Interrupt Enable

Definition at line 118 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE

Autoreload register update OK Interrupt Enable

Definition at line 121 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE

Compare match Interrupt Enable

Definition at line 117 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE

Compare register update OK Interrupt Enable

Definition at line 120 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Direction change to down Interrupt Enable

Definition at line 123 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE

External trigger valid edge Interrupt Enable

Definition at line 119 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE

Direction change to UP Interrupt Enable

Definition at line 122 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Operating Mode

Defines
Operating Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

Define Documentation

#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode

Definition at line 131 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Tilmer starts in single mode

Definition at line 132 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Update Mode

Defines
Update Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

preload is enabled: registers are updated at the end of the current LPTIM period

Definition at line 141 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U

Preload is disabled: registers are updated after each APB bus write access

Definition at line 140 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Counter Mode

Defines
Counter Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1

Definition at line 150 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U

The counter is incremented following each internal clock pulse

Definition at line 149 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Output Waveform Type

Defines
Output Waveform Type
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

Define Documentation

#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U

LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE

Definition at line 158 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a Set Once waveform

Definition at line 159 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Output Polarity

Defines
Output Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

Define Documentation

#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 168 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 167 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32H7B3xQ HAL User Manual: Prescaler Value

Defines
Prescaler Value
LPTIM Exported Constants

Defines

#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LL_LPTIM_PRESCALER_DIV1 0x00000000U

Prescaler division factor is set to 1

Definition at line 176 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128

Definition at line 183 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16

Definition at line 180 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2

Definition at line 177 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32

Definition at line 181 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4

Definition at line 178 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64

Definition at line 182 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8

Definition at line 179 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Trigger Source

Defines
Trigger Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2

Define Documentation

#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

Definition at line 197 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

External input trigger is connected to COMP2 output

Definition at line 198 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U

External input trigger is connected to TIMx_ETR input

Definition at line 191 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U

External input trigger is connected to LPTIM2 output

Definition at line 199 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to LPTIM3 output

Definition at line 200 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to LPTIM4 output

Definition at line 201 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to LPTIM5 output

Definition at line 202 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

Definition at line 192 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

Definition at line 193 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

Definition at line 194 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

Definition at line 195 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 3

Definition at line 196 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to SAI1 FS A output

Definition at line 203 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to SAI1 FS B output

Definition at line 204 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to SAI2 FS A output

Definition at line 205 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to SAI2 FS B output

Definition at line 206 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to SAI4 FS A output

Definition at line 207 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to SAI4 FS B output

Definition at line 208 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Trigger Filter

Defines
Trigger Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Define Documentation

#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger

Definition at line 217 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger

Definition at line 218 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Definition at line 219 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U

Any trigger active level change is considered as a valid trigger

Definition at line 216 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Trigger Polarity

Defines
Trigger Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

Definition at line 228 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

Definition at line 227 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Definition at line 229 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Clock Source

Defines
Clock Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

Define Documentation

#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Definition at line 238 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

Definition at line 237 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32H7B3xQ HAL User Manual: Clock Filter

Defines
Clock Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

Define Documentation

#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

Definition at line 247 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Definition at line 248 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Definition at line 249 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U

Any external clock signal level change is considered as a valid transition

Definition at line 246 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Clock Polarity

Defines
Clock Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 258 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 257 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 259 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Encoder Mode

Defines
Encoder Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 268 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 267 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 269 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Input1 Source

Defines
Input1 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1

Define Documentation

#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0

For LPTIM1 and LPTIM2

Definition at line 278 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

For LPTIM2

Definition at line 280 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1

For LPTIM2

Definition at line 279 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 277 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0

For LPTIM3

Definition at line 281 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1

For LPTIM3

Definition at line 282 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Input2 Source

Defines
Input2 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0

Define Documentation

#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0

For LPTIM1

Definition at line 291 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U

For LPTIM1

Definition at line 290 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPTIM Exported Macros

Defines

#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Define Documentation

#define LL_LPTIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 324 of file stm32h7xx_ll_lptim.h.

#define LL_LPTIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 316 of file stm32h7xx_ll_lptim.h.

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STM32H7B3xQ HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
LPTIM Exported Functions

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Function Documentation

ErrorStatus LL_LPTIM_DeInit ( LPTIM_TypeDef * LPTIMx )

Set LPTIMx registers to their reset values.

Parameters:
LPTIMx LP Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx registers are de-initialized
  • ERROR: invalid LPTIMx instance

Definition at line 96 of file stm32h7xx_ll_lptim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPTIM1, LL_APB1_GRP1_ReleaseReset(), LL_APB4_GRP1_ForceReset(), LL_APB4_GRP1_PERIPH_LPTIM2, LL_APB4_GRP1_PERIPH_LPTIM3, and LL_APB4_GRP1_ReleaseReset().

Referenced by LL_LPTIM_Disable().

void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 210 of file stm32h7xx_ll_lptim.c.

References assert_param, LL_LPTIM_ClearFlag_ARROK(), LL_LPTIM_ClearFlag_CMPOK(), LL_LPTIM_DeInit(), LL_LPTIM_IsActiveFlag_ARROK(), LL_LPTIM_IsActiveFlag_CMPOK(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSystemClocksFreq(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_PCLK4, LL_RCC_LPTIM345_CLKSOURCE, LL_RCC_LPTIM345_CLKSOURCE_PCLK4, LL_RCC_LPTIM3_CLKSOURCE, LL_RCC_LPTIM3_CLKSOURCE_PCLK4, LL_RCC_SetLPTIMClockSource(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

ErrorStatus LL_LPTIM_Init | ( | LPTIM_TypeDef * | LPTIMx,
 |  | LL_LPTIM_InitTypeDef * | LPTIM_InitStruct
 | ) |  |

Configure the LPTIMx peripheral according to the specified parameters.

Note:
LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
LPTIMx can be disabled using unitary function LL_LPTIM_Disable().
Parameters:
LPTIMx | LP Timer Instance
LPTIM_InitStruct | pointer to a LL_LPTIM_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx instance has been initialized
  • ERROR: LPTIMx instance hasn't been initialized

Definition at line 167 of file stm32h7xx_ll_lptim.c.

References assert_param, LL_LPTIM_InitTypeDef::ClockSource, IS_LL_LPTIM_CLOCK_PRESCALER, IS_LL_LPTIM_CLOCK_SOURCE, IS_LL_LPTIM_OUTPUT_POLARITY, IS_LL_LPTIM_WAVEFORM, LL_LPTIM_IsEnabled(), LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

void LL_LPTIM_StructInit ( LL_LPTIM_InitTypeDef * LPTIM_InitStruct )

Set each fields of the LPTIM_InitStruct structure to its default value.

Parameters:
LPTIM_InitStruct pointer to a LL_LPTIM_InitTypeDef structure
Return values:
None

Definition at line 148 of file stm32h7xx_ll_lptim.c.

References LL_LPTIM_InitTypeDef::ClockSource, LL_LPTIM_CLK_SOURCE_INTERNAL, LL_LPTIM_OUTPUT_POLARITY_REGULAR, LL_LPTIM_OUTPUT_WAVEFORM_PWM, LL_LPTIM_PRESCALER_DIV1, LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPTIM Configuration

Functions
LPTIM Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigOutput | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform,
 |  | uint32_t | Polarity
 | ) |  |

Configure the LPTIM instance output (LPTIMx_OUT)

Note:
This function must be called when the LPTIM instance is disabled.
Regarding the LPTIM output polarity the change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_ConfigOutput
CFGR WAVPOL LL_LPTIM_ConfigOutput
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 592 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Disable reset after read.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_DisableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 417 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Enable ( LPTIM_TypeDef * LPTIMx )

Enable the LPTIM instance.

Note:
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM instance is actually enabled.
Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Enable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 364 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Enable reset after read.

Note:
After calling this function any read access to LPTIM_CNT register will asynchronously reset the LPTIM_CNT register content.
Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_EnableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 406 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload ( LPTIM_TypeDef * LPTIMx )

Get actual auto reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_GetAutoReload
Parameters:
LPTIMx Low-Power Timer instance
Return values:
AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 500 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCompare ( LPTIM_TypeDef * LPTIMx )

Get actual compare value.

Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_GetCompare
Parameters:
LPTIMx Low-Power Timer instance
Return values:
CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 527 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounter ( LPTIM_TypeDef * LPTIMx )

Get actual counter value.

Note:
When the LPTIM instance is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Reference Manual to LL API cross reference:
CNT CNT LL_LPTIM_GetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Counter value

Definition at line 542 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode ( LPTIM_TypeDef * LPTIMx )

Get the counter mode.

Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_GetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL

Definition at line 570 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_GetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE

Definition at line 646 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler ( LPTIM_TypeDef * LPTIMx )

Get actual prescaler division ratio.

Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_GetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128

Definition at line 690 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode ( LPTIM_TypeDef * LPTIMx )

Get the LPTIM registers update mode.

Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_GetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

Definition at line 471 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform ( LPTIM_TypeDef * LPTIMx )

Get actual waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_GetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

Definition at line 619 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM instance is enabled.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_IsEnabled
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 375 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Init().

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Indicate whether the reset after read feature is enabled.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 428 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ResetCounter ( LPTIM_TypeDef * LPTIMx )

Reset of the LPTIM_CNT counter register (synchronous).

Note:
Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTIM core clock cycles (LPTIM core clock may be different from APB clock).
COUNTRST is automatically cleared by hardware
Reference Manual to LL API cross reference:
CR COUNTRST LL_LPTIM_ResetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 443 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetAutoReload | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto reload value.

Note:
The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
After a write to the LPTIMx_ARR register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the ARROK flag is set, will lead to unpredictable results.
autoreload value be strictly greater than the compare value.
Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_SetAutoReload
Parameters:
LPTIMx | Low-Power Timer instance
AutoReload | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 489 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCompare | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set the compare value.

Note:
After a write to the LPTIMx_CMP register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the CMPOK flag is set, will lead to unpredictable results.
Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_SetCompare
Parameters:
LPTIMx | Low-Power Timer instance
CompareValue | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 516 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCounterMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the counter mode (selection of the LPTIM counter clock source).

Note:
The counter mode can be set only when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_SetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
CounterMode This parameter can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL
Return values:
None

Definition at line 557 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput1Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 1 source (default GPIO).

Reference Manual to LL API cross reference:
CFGR2 IN1SEL LL_LPTIM_SetInput1Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT1_SRC_GPIO
  • LL_LPTIM_INPUT1_SRC_COMP1
  • LL_LPTIM_INPUT1_SRC_COMP2
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_A
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_B
Return values:
None

Definition at line 708 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput2Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 2 source (default GPIO).

Reference Manual to LL API cross reference:
CFGR2 IN2SEL LL_LPTIM_SetInput2Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT2_SRC_GPIO
  • LL_LPTIM_INPUT2_SRC_COMP2
Return values:
None

Definition at line 722 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPolarity | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Polarity
 | ) |  |

Set output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_SetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 633 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPrescaler | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set actual prescaler division ratio.

Note:
This function must be called when the LPTIM instance is disabled.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled.
Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_SetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Prescaler This parameter can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128
Return values:
None

Definition at line 671 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetUpdateMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | UpdateMode
 | ) |  |

Set the LPTIM registers update mode (enable/disable register preload)

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_SetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
UpdateMode This parameter can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
Return values:
None

Definition at line 458 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetWaveform | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform
 | ) |  |

Set waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_SetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Return values:
None

Definition at line 606 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_StartCounter | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | OperatingMode
 | ) |  |

Starts the LPTIM counter in the desired mode.

Note:
LPTIM instance must be enabled before starting the counter.
It is possible to change on the fly from One Shot mode to Continuous mode.
Reference Manual to LL API cross reference:
CR CNTSTRT LL_LPTIM_StartCounter
CR SNGSTRT LL_LPTIM_StartCounter
Parameters:
LPTIMx Low-Power Timer instance
OperatingMode This parameter can be one of the following values:
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS
  • LL_LPTIM_OPERATING_MODE_ONESHOT
Return values:
None

Definition at line 393 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Trigger Configuration

Functions
Trigger Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigTrigger | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Source,
 |  | uint32_t | Filter,
 |  | uint32_t | Polarity
 | ) |  |

Configure the external trigger used as a trigger event for the LPTIM.

Note:
This function must be called when the LPTIM instance is disabled.
An internal clock source must be present when a digital filter is required for the trigger.
Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_ConfigTrigger
CFGR TRGFLT LL_LPTIM_ConfigTrigger
CFGR TRIGEN LL_LPTIM_ConfigTrigger
Parameters:
LPTIMx Low-Power Timer instance
Source This parameter can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
(*) Value not defined in all devices.
Filter This parameter can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8
Polarity This parameter can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Return values:
None

Definition at line 831 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableTimeout ( LPTIM_TypeDef * LPTIMx )

Disable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
A trigger event arriving when the timer is already started will be ignored.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_DisableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 761 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableTimeout ( LPTIM_TypeDef * LPTIMx )

Enable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_EnableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 747 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger filter.

Reference Manual to LL API cross reference:
CFGR TRGFLT LL_LPTIM_GetTriggerFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8

Definition at line 878 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger polarity.

Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING

Definition at line 892 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger source.

Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_GetTriggerSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
  • LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
(*) Value not defined in all devices.

Definition at line 863 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout ( LPTIM_TypeDef * LPTIMx )

Indicate whether the timeout function is enabled.

Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 772 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_TrigSw ( LPTIM_TypeDef * LPTIMx )

Start the LPTIM counter.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_TrigSw
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 784 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Configuration

Functions
Clock Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigClock | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockFilter,
 |  | uint32_t | ClockPolarity
 | ) |  |

Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

Note:
This function must be called when the LPTIM instance is disabled.
When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.
An internal clock source must be present when a digital filter is required for external clock.
Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_ConfigClock
CFGR CKPOL LL_LPTIM_ConfigClock
Parameters:
LPTIMx Low-Power Timer instance
ClockFilter This parameter can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8
ClockPolarity This parameter can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING
Return values:
None

Definition at line 955 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter ( LPTIM_TypeDef * LPTIMx )

Get actual clock digital filter.

Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_GetClockFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8

Definition at line 984 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual clock polarity.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetClockPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING

Definition at line 969 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource ( LPTIM_TypeDef * LPTIMx )

Get actual LPTIM instance clock source.

Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_GetClockSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL

Definition at line 928 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetClockSource | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the source of the clock used by the LPTIM instance.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_SetClockSource
Parameters:
LPTIMx Low-Power Timer instance
ClockSource This parameter can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL
Return values:
None

Definition at line 915 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Encoder Mode

Functions
Encoder Mode
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Disable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_DisableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1050 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Enable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
In this mode the LPTIM instance must be clocked by an internal clock source. Also, the prescaler division ratio must be equal to 1.
LPTIM instance must be configured in continuous mode prior enabling the encoder mode.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_EnableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1038 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode ( LPTIM_TypeDef * LPTIMx )

Get actual encoder mode.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING

Definition at line 1022 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM operates in encoder mode.

Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_IsEnabledEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1061 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetEncoderMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Configure the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_SetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING
Return values:
None

Definition at line 1008 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG Management

Functions
FLAG Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload match flag (ARRMCF)

Reference Manual to LL API cross reference:
ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1102 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload register update interrupt flag (ARROKCF).

Reference Manual to LL API cross reference:
ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1168 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM ( LPTIM_TypeDef * LPTIMx )

Clear the compare match flag (CMPMCF)

Reference Manual to LL API cross reference:
ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1080 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Clear the compare register update interrupt flag (CMPOKCF).

Reference Manual to LL API cross reference:
ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1146 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to down interrupt flag (DOWNCF).

Reference Manual to LL API cross reference:
ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1212 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Clear the external trigger valid edge flag(EXTTRIGCF).

Reference Manual to LL API cross reference:
ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1124 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_UP ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to up interrupt flag (UPCF).

Reference Manual to LL API cross reference:
ICR UPCF LL_LPTIM_ClearFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1190 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a autoreload match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1113 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1179 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a compare match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1091 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1157 of file stm32h7xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1223 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Inform application whether a valid edge on the selected external trigger input has occurred.

Reference Manual to LL API cross reference:
ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1135 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR UP LL_LPTIM_IsActiveFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1201 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Interrupt Management

Functions
Interrupt Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Disable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_DisableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1286 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Disable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_DisableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1385 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Disable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_DisableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1253 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Disable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1352 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Disable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_DisableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1451 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Disable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1319 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_UP ( LPTIM_TypeDef * LPTIMx )

Disable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_DisableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1418 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Enable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_EnableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1275 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Enable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_EnableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1374 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Enable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_EnableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1242 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Enable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1341 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Enable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_EnableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1440 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Enable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1308 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_UP ( LPTIM_TypeDef * LPTIMx )

Enable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_EnableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1407 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1297 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1396 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare match interrupt (CMPMIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1264 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1363 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1462 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1330 of file stm32h7xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to up interrupt (UPIE) is enabled.

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_IsEnabledIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1429 of file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPUART Private Variables

Variables
LPUART Private Variables
LPUART

Variables

static const uint16_t LPUART_PRESCALER_TAB []

Variable Documentation

const uint16_t LPUART_PRESCALER_TAB[] [static]
Initial value:
{
  (uint16_t)1,
  (uint16_t)2,
  (uint16_t)4,
  (uint16_t)6,
  (uint16_t)8,
  (uint16_t)10,
  (uint16_t)12,
  (uint16_t)16,
  (uint16_t)32,
  (uint16_t)64,
  (uint16_t)128,
  (uint16_t)256
}

Definition at line 47 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPUART Private Constants

Defines
LPUART Private Constants
LPUART

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U

Define Documentation

#define LPUART_BRR_MASK 0x000FFFFFU

Definition at line 72 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_BRR_MIN_VALUE 0x00000300U

Definition at line 73 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_LPUARTDIV_FREQ_MUL 256U

Definition at line 71 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LPUART Private Macros

Defines
LPUART Private Macros
LPUART

Defines

#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_LPUART_BAUDRATE ( __BAUDRATE__ ) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))

Definition at line 79 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x000FFFFFU)

Definition at line 85 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 0x300U)

Definition at line 82 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))

Definition at line 96 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))

Definition at line 87 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))

Definition at line 103 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PARITY_NONE) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))

Definition at line 92 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))

Definition at line 60 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_STOPBITS_1) \
                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))

Definition at line 100 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_LPUART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPUART_InitTypeDef Struct Reference
LPUART Exported Init structures

LL LPUART Init Structure definition. More...

#include <stm32h7xx_ll_lpuart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL LPUART Init Structure definition.

Definition at line 98 of file stm32h7xx_ll_lpuart.h.

Field Documentation

uint32_t LL_LPUART_InitTypeDef::BaudRate

This field defines expected LPUART communication baud rate.

This feature can be modified afterwards using unitary function LL_LPUART_SetBaudRate().

Definition at line 105 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_LPUART_SetDataWidth().

Definition at line 109 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetHWFlowCtrl().

Definition at line 129 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetParity().

Definition at line 119 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_LPUART_SetPrescaler().

Definition at line 100 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_LPUART_SetStopBitsLength().

Definition at line 114 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Direction.

This feature can be modified afterwards using unitary function LL_LPUART_SetTransferDirection().

Definition at line 124 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_lpuart.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_WriteReg function. More...

Defines

#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_LPUART_WriteReg function.

Define Documentation

#define LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 158 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 157 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 151 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 154 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_NCF USART_ICR_NECF

Noise error detected flag

Definition at line 152 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 153 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 150 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 156 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty Clear flag

Definition at line 155 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 159 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_ReadReg function. More...

Defines

#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_LPUART_ReadReg function.

Define Documentation

#define LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 178 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 179 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 177 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 176 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 169 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 172 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 170 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 171 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 168 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 184 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 181 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 186 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 187 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 173 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 180 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 174 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 183 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 175 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 185 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 188 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 182 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
LPUART Exported Constants

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions. More...

Defines

#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Define Documentation

#define LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 202 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 197 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 201 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 204 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 198 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 199 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 200 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 203 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 206 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 205 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 209 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 208 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 207 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
LPUART Exported Constants

Defines

#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 219 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 218 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 217 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 220 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 221 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 222 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Direction

Defines
Direction
LPUART Exported Constants

Defines

#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_LPUART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 230 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 231 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 232 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 233 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

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STM32H7B3xQ HAL User Manual: Parity Control

Defines
Parity Control
LPUART Exported Constants

Defines

#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 242 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 241 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 243 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Wakeup

Defines
Wakeup
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Definition at line 252 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U

LPUART wake up from Mute mode on Idle Line

Definition at line 251 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Datawidth

Defines
Datawidth
LPUART Exported Constants

Defines

#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 260 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 261 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 262 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
LPUART Exported Constants

Defines

#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_LPUART_PRESCALER_DIV1 0x00000000U

Input clock not devided

Definition at line 270 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock devided by 10

Definition at line 275 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock devided by 12

Definition at line 276 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock devided by 128

Definition at line 280 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 16

Definition at line 277 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock devided by 2

Definition at line 271 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 256

Definition at line 281 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock devided by 32

Definition at line 278 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock devided by 4

Definition at line 272 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 6

Definition at line 273 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock devided by 64

Definition at line 279 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock devided by 8

Definition at line 274 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Stop Bits

Defines
Stop Bits
LPUART Exported Constants

Defines

#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_LPUART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 289 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 290 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
LPUART Exported Constants

Defines

#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_LPUART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 298 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 299 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 308 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 307 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 317 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 316 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 326 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 325 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Bit Order

Defines
Bit Order
LPUART Exported Constants

Defines

#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 334 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 335 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Address Length Detection

Defines
Address Length Detection
LPUART Exported Constants

Defines

#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 343 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 344 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Hardware Control

Defines
Hardware Control
LPUART Exported Constants

Defines

#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 354 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 352 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 353 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 355 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 363 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 365 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 364 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
LPUART Exported Constants

Defines

#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 373 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 374 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: DMA Register Data

Defines
DMA Register Data
LPUART Exported Constants

Defines

#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 383 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 382 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_DMA_GetRegAddr().

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPUART Exported Macros

Defines

#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.

Define Documentation

#define LL_LPUART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 416 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 408 of file stm32h7xx_ll_lpuart.h.

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STM32H7B3xQ HAL User Manual: Helper Macros

Defines
Helper Macros
LPUART Exported Macros

Defines

#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Define Documentation

#define __LL_LPUART_DIV | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
                                                                                + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)

Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for LPUART Instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
__BAUDRATE__ | Baud Rate value to achieve
Return values:
LPUARTDIV value to be used for BRR register filling

Definition at line 445 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_SetBaudRate().

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STM32H7B3xQ HAL User Manual: Configuration functions

Functions
Configuration functions
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Function Documentation

__STATIC_INLINE void LL_LPUART_ConfigCharacter | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_LPUART_SetDataWidth() function
  • Parity Control and mode configuration using LL_LPUART_SetParity() function
  • Stop bits configuration using LL_LPUART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_ConfigCharacter
CR1 PCE LL_LPUART_ConfigCharacter
CR1 M LL_LPUART_ConfigCharacter
CR2 STOP LL_LPUART_ConfigCharacter
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 971 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
Parameters:
LPUARTx LPUART Instance
TXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 630 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigNodeAddress | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the LPUART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_ConfigNodeAddress
CR2 ADDM7 LL_LPUART_ConfigNodeAddress
Parameters:
LPUARTx | LPUART Instance
AddressLen This parameter can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the LPUART node.
Return values:
None

Definition at line 1143 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Disable ( USART_TypeDef * LPUARTx )

LPUART Disable.

Note:
When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their default values.
In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Disable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 490 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1216 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_DisableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 689 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_DisableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 711 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Disable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_DisableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 523 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableInStopMode ( USART_TypeDef * LPUARTx )

LPUART disabled in STOP Mode.

Note:
When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_DisableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 655 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableMuteMode ( USART_TypeDef * LPUARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_DisableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 857 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableOverrunDetect ( USART_TypeDef * LPUARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_DisableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1271 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1194 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Enable ( USART_TypeDef * LPUARTx )

LPUART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Enable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 471 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1205 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_EnableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 678 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_EnableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 700 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Enable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_EnableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 512 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableInStopMode ( USART_TypeDef * LPUARTx )

LPUART enabled in STOP Mode.

Note:
When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_EnableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 643 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableMuteMode ( USART_TypeDef * LPUARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_EnableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 846 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableOverrunDetect ( USART_TypeDef * LPUARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_EnableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1260 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1183 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue
 | ) |  |

Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_GetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
Baud Rate

Definition at line 1373 of file stm32h7xx_ll_lpuart.h.

References LPUART_BRR_MASK, LPUART_BRR_MIN_VALUE, and LPUART_LPUARTDIV_FREQ_MUL.

__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic ( USART_TypeDef * LPUARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_GetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE

Definition at line 1084 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth ( USART_TypeDef * LPUARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_GetDataWidth
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B

Definition at line 835 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl ( USART_TypeDef * LPUARTx )

Return HW Flow Control configuration (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_GetHWFlowCtrl
CR3 CTSE LL_LPUART_GetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS

Definition at line 1249 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress ( USART_TypeDef * LPUARTx )

Return 8 bit Address of the LPUART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_GetNodeAddress
Parameters:
LPUARTx LPUART Instance
Return values:
Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1159 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen ( USART_TypeDef * LPUARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_LPUART_GetNodeAddressLen
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B

Definition at line 1172 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetParity ( USART_TypeDef * LPUARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_GetParity
CR1 PCE LL_LPUART_GetParity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD

Definition at line 779 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler ( USART_TypeDef * LPUARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_GetPrescaler
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256

Definition at line 915 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold ( USART_TypeDef * LPUARTx )

Return RX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 604 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_GetRXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED

Definition at line 1027 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength ( USART_TypeDef * LPUARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_GetStopBitsLength
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2

Definition at line 942 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder ( USART_TypeDef * LPUARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST

Definition at line 1115 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection ( USART_TypeDef * LPUARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_GetTransferDirection
CR1 TE LL_LPUART_GetTransferDirection
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX

Definition at line 745 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold ( USART_TypeDef * LPUARTx )

Return TX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 569 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_GetTXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED

Definition at line 1054 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap ( USART_TypeDef * LPUARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_GetTXRXSwap
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED

Definition at line 1000 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod ( USART_TypeDef * LPUARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_GetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK

Definition at line 806 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType ( USART_TypeDef * LPUARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_GetWKUPType
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE

Definition at line 1311 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabled ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_IsEnabled
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 501 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO ( USART_TypeDef * LPUARTx )

Indicate if FIFO Mode is enabled.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_IsEnabledFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 534 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_IsEnabledInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 667 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode ( USART_TypeDef * LPUARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_IsEnabledMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 868 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect ( USART_TypeDef * LPUARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1282 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | BaudRate
 | ) |  |

Configure LPUART BRR register for achieving expected Baud Rate value.

Note:
Compute and set LPUARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock and expected Baud Rate values
Peripheral clock and Baud Rate values provided as function parameters should be valid (Baud rate value != 0).
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baud rates using high PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_SetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
BaudRate | Baud Rate
Return values:
None

Definition at line 1345 of file stm32h7xx_ll_lpuart.h.

References __LL_LPUART_DIV.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_SetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
DataLogic This parameter can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1071 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDataWidth | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_SetDataWidth
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Return values:
None

Definition at line 821 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_SetHWFlowCtrl
CR3 CTSE LL_LPUART_SetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1233 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetParity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled)

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_SetParity
CR1 PCE LL_LPUART_SetParity
Parameters:
LPUARTx LPUART Instance
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
Return values:
None

Definition at line 764 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetPrescaler | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_SetPrescaler
Parameters:
LPUARTx LPUART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
None

Definition at line 892 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 587 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetRXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_SetRXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1014 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetStopBitsLength | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_SetStopBitsLength
Parameters:
LPUARTx LPUART Instance
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 929 of file stm32h7xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetTransferBitOrder | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
BitOrder This parameter can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1100 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTransferDirection | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_SetTransferDirection
CR1 TE LL_LPUART_SetTransferDirection
Parameters:
LPUARTx LPUART Instance
TransferDirection This parameter can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX
Return values:
None

Definition at line 729 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 552 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_SetTXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1041 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXRXSwap | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_SetTXRXSwap
Parameters:
LPUARTx LPUART Instance
SwapConfig This parameter can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED
Return values:
None

Definition at line 987 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWakeUpMethod | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_SetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Method This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 793 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWKUPType | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_SetWKUPType
Parameters:
LPUARTx LPUART Instance
Type This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1297 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableHalfDuplex ( USART_TypeDef * LPUARTx )

Disable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_DisableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1418 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableHalfDuplex ( USART_TypeDef * LPUARTx )

Enable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_EnableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1407 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex ( USART_TypeDef * LPUARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1429 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDEMode ( USART_TypeDef * LPUARTx )

Disable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_DisableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1505 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDEMode ( USART_TypeDef * LPUARTx )

Enable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_EnableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1494 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime ( USART_TypeDef * LPUARTx )

Return DEAT (Driver Enable Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_GetDEAssertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

Definition at line 1483 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime ( USART_TypeDef * LPUARTx )

Return DEDT (Driver Enable De-Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_GetDEDeassertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : c

Definition at line 1460 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity ( USART_TypeDef * LPUARTx )

Return Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_GetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW

Definition at line 1543 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode ( USART_TypeDef * LPUARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_IsEnabledDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1516 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEAssertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_SetDEAssertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1472 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_SetDEDeassertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1449 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDESignalPolarity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_SetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Polarity This parameter can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW
Return values:
None

Definition at line 1530 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TXFE (USART_TypeDef *LPUARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE

Definition at line 1612 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Definition at line 1637 of file stm32h7xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_ClearFlag_CM ( USART_TypeDef * LPUARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_LPUART_ClearFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1887 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_FE ( USART_TypeDef * LPUARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_LPUART_ClearFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1810 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE ( USART_TypeDef * LPUARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_LPUART_ClearFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1843 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS ( USART_TypeDef * LPUARTx )

Clear CTS Interrupt Flag.

Reference Manual to LL API cross reference:
ICR CTSCF LL_LPUART_ClearFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1876 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_NE ( USART_TypeDef * LPUARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_LPUART_ClearFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1821 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_ORE ( USART_TypeDef * LPUARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_LPUART_ClearFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1832 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_PE ( USART_TypeDef * LPUARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_LPUART_ClearFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1799 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TC ( USART_TypeDef * LPUARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_LPUART_ClearFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1865 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE ( USART_TypeDef * LPUARTx )

Clear TX FIFO Empty Flag.

Reference Manual to LL API cross reference:
ICR TXFECF LL_LPUART_ClearFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1854 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP ( USART_TypeDef * LPUARTx )

Clear Wake Up from stop mode Flag.

Reference Manual to LL API cross reference:
ICR WUCF LL_LPUART_ClearFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1898 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY ( USART_TypeDef * LPUARTx )

Check if the LPUART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_LPUART_IsActiveFlag_BUSY
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1678 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_LPUART_IsActiveFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1689 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTS LL_LPUART_IsActiveFlag_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE ( USART_TypeDef * LPUARTx )

Check if the LPUART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_LPUART_IsActiveFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1573 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_LPUART_IsActiveFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1606 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE ( USART_TypeDef * LPUARTx )

Check if the LPUART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_LPUART_IsActiveFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1584 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE ( USART_TypeDef * LPUARTx )

Check if the LPUART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_LPUART_IsActiveFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1595 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_LPUART_IsActiveFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1562 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_LPUART_IsActiveFlag_REACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1744 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_LPUART_IsActiveFlag_RWU
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1711 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFF LL_LPUART_IsActiveFlag_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1766 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFT LL_LPUART_IsActiveFlag_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1788 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1620 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK ( USART_TypeDef * LPUARTx )

Check if the LPUART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_LPUART_IsActiveFlag_SBK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1700 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_LPUART_IsActiveFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_LPUART_IsActiveFlag_TEACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1733 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1645 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFE LL_LPUART_IsActiveFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1755 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFT LL_LPUART_IsActiveFlag_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1777 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from stop mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR WUF LL_LPUART_IsActiveFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1722 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Defines | Functions
IT_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE

Definition at line 2076 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF

Definition at line 2101 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE

Definition at line 1923 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF

Definition at line 1948 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE

Definition at line 2229 of file stm32h7xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Definition at line 2254 of file stm32h7xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableIT_CM ( USART_TypeDef * LPUARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_DisableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2131 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_CTS ( USART_TypeDef * LPUARTx )

Disable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_DisableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2179 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_ERROR ( USART_TypeDef * LPUARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_DisableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2168 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_IDLE ( USART_TypeDef * LPUARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_DisableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2070 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_PE ( USART_TypeDef * LPUARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_DisableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2120 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFF ( USART_TypeDef * LPUARTx )

Disable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_DisableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2153 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFT ( USART_TypeDef * LPUARTx )

Disable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_DisableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2212 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2084 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TC ( USART_TypeDef * LPUARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_DisableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2095 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2109 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFE ( USART_TypeDef * LPUARTx )

Disable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_DisableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2142 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFT ( USART_TypeDef * LPUARTx )

Disable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_DisableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2201 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_WKUP ( USART_TypeDef * LPUARTx )

Disable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_DisableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2190 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CM ( USART_TypeDef * LPUARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_EnableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1978 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CTS ( USART_TypeDef * LPUARTx )

Enable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_EnableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2026 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_ERROR ( USART_TypeDef * LPUARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_EnableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2015 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_IDLE ( USART_TypeDef * LPUARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_EnableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1917 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_PE ( USART_TypeDef * LPUARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_EnableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1967 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFF ( USART_TypeDef * LPUARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_EnableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2000 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFT ( USART_TypeDef * LPUARTx )

Enable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_EnableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2059 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1931 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TC ( USART_TypeDef * LPUARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_EnableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1942 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1956 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFE ( USART_TypeDef * LPUARTx )

Enable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_EnableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1989 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFT ( USART_TypeDef * LPUARTx )

Enable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_EnableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2048 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_WKUP ( USART_TypeDef * LPUARTx )

Enable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_EnableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2037 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_IsEnabledIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2284 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2328 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR ( USART_TypeDef * LPUARTx )

Check if the LPUART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_IsEnabledIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2317 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2223 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_IsEnabledIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2273 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2306 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT ( USART_TypeDef * LPUARTx )

Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2361 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2237 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_IsEnabledIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2248 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2262 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2295 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT ( USART_TypeDef * LPUARTx )

Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2350 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2339 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_Management

Functions
DMA_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2457 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_DisableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2391 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_DisableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2424 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the LPUART data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_DMA_GetRegAddr
Parameters:
LPUARTx LPUART Instance
Direction This parameter can be one of the following values:
  • LL_LPUART_DMA_REG_DATA_TRANSMIT
  • LL_LPUART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 2483 of file stm32h7xx_ll_lpuart.h.

References LL_LPUART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2446 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_EnableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2380 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_EnableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2413 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2468 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2402 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2435 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData8
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2515 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData9
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2526 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData8 | ( | USART_TypeDef * | LPUARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData8
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2538 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData9 | ( | USART_TypeDef * | LPUARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData9
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2550 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Execution

Functions
Execution
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_LPUART_RequestBreakSending ( USART_TypeDef * LPUARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_LPUART_RequestBreakSending
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2569 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode ( USART_TypeDef * LPUARTx )

Put LPUART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_LPUART_RequestEnterMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2580 of file stm32h7xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestRxDataFlush ( USART_TypeDef * LPUARTx )

Request a Receive Data and FIFO flush.

Note:
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_LPUART_RequestRxDataFlush
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2593 of file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
LPUART Exported Functions

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_LPUART_DeInit ( USART_TypeDef * LPUARTx )

De-initialize LPUART registers (Registers restored to their default values).

Parameters:
LPUARTx LPUART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are de-initialized
  • ERROR: not applicable

Definition at line 130 of file stm32h7xx_ll_lpuart.c.

References assert_param, LL_APB4_GRP1_ForceReset(), LL_APB4_GRP1_PERIPH_LPUART1, and LL_APB4_GRP1_ReleaseReset().

ErrorStatus LL_LPUART_Init | ( | USART_TypeDef * | LPUARTx,
 |  | LL_LPUART_InitTypeDef * | LPUART_InitStruct
 | ) |  |

Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.

Note:
As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
LPUARTx | LPUART Instance
LPUART_InitStruct | pointer to a LL_LPUART_InitTypeDef structure that contains the configuration information for the specified LPUART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
  • ERROR: Problem occurred during LPUART Registers initialization

Definition at line 166 of file stm32h7xx_ll_lpuart.c.

References assert_param, LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, IS_LL_LPUART_BAUDRATE, IS_LL_LPUART_BRR_MAX, IS_LL_LPUART_BRR_MIN, IS_LL_LPUART_DATAWIDTH, IS_LL_LPUART_DIRECTION, IS_LL_LPUART_HWCONTROL, IS_LL_LPUART_PARITY, IS_LL_LPUART_PRESCALER, IS_LL_LPUART_STOPBITS, LL_LPUART_IsEnabled(), LL_LPUART_SetBaudRate(), LL_LPUART_SetHWFlowCtrl(), LL_LPUART_SetPrescaler(), LL_LPUART_SetStopBitsLength(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_PERIPH_FREQUENCY_NO, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

void LL_LPUART_StructInit ( LL_LPUART_InitTypeDef * LPUART_InitStruct )

Set each LL_LPUART_InitTypeDef field to default value.

Parameters:
LPUART_InitStruct pointer to a LL_LPUART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 250 of file stm32h7xx_ll_lpuart.c.

References LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, LL_LPUART_DATAWIDTH_8B, LL_LPUART_DIRECTION_TX_RX, LL_LPUART_HWCONTROL_NONE, LL_LPUART_PARITY_NONE, LL_LPUART_PRESCALER_DIV1, LL_LPUART_STOPBITS_1, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Private Variables

Variables
MDMA Private Variables
MDMA

Variables

static const uint32_t LL_MDMA_CH_OFFSET_TAB []

Variable Documentation

const uint32_t LL_MDMA_CH_OFFSET_TAB[] [static]
Initial value:
{
  (uint32_t)(MDMA_Channel0_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel1_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel2_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel3_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel4_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel5_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel6_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel7_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel8_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel9_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel10_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel11_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel12_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel13_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel14_BASE - MDMA_BASE),
  (uint32_t)(MDMA_Channel15_BASE - MDMA_BASE)
}

Definition at line 47 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA Private Constants

MDMA Private Constants
MDMA
Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_MDMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_MDMA_InitTypeDef Struct Reference
MDMA Exported Init structure

#include <stm32h7xx_ll_mdma.h>

Data Fields

uint32_t | SrcAddress
uint32_t | DstAddress
uint32_t | RequestMode
uint32_t | TriggerMode
uint32_t | HWTrigger
uint32_t | BlockDataLength
uint32_t | BlockRepeatCount
uint32_t | BlockRepeatDestAddrUpdateMode
uint32_t | BlockRepeatSrcAddrUpdateMode
uint32_t | BlockRepeatDestAddrUpdateVal
uint32_t | BlockRepeatSrcAddrUpdateVal
uint32_t | LinkAddress
uint32_t | WordEndianess
uint32_t | HalfWordEndianess
uint32_t | ByteEndianess
uint32_t | Priority
uint32_t | BufferableWriteMode
uint32_t | PaddingAlignment
uint32_t | PackMode
uint32_t | BufferTransferLength
uint32_t | DestBurst
uint32_t | SrctBurst
uint32_t | DestIncSize
uint32_t | SrcIncSize
uint32_t | DestDataSize
uint32_t | SrcDataSize
uint32_t | DestIncMode
uint32_t | SrcIncMode
uint32_t | DestBus
uint32_t | SrcBus
uint32_t | MaskAddress
uint32_t | MaskData

Detailed Description

Definition at line 86 of file stm32h7xx_ll_mdma.h.

Field Documentation

uint32_t LL_MDMA_InitTypeDef::BlockDataLength

Specifies the length of a block transfer in bytes This parameter must be a value between Min_Data = 0 and Max_Data = 0x00010000. This feature can be modified afterwards using unitary function LL_MDMA_SetBlkDataLength()

Definition at line 108 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BlockRepeatCount

Specifies the Block Repeat Count This parameter must be a value between Min_Data = 0 and Max_Data = 0x00000FFF. This feature can be modified afterwards using unitary function LL_MDMA_SetBlkRepeatCount()

Definition at line 112 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateMode

Specifies the block repeat destination address update mode. This parameter can be a value of Block Repeat Destination address Update Mode This feature can be modified afterwards using unitary function LL_MDMA_SetBlkRepeatDestAddrUpdate()

Definition at line 116 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateVal

Specifies the block repeat destination address update value. This parameter can be a value Between 0 to 0x0000FFFF This feature can be modified afterwards using unitary function LL_MDMA_SetBlkRptDestAddrUpdateValue()

Definition at line 124 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateMode

Specifies the block repeat source address update mode. This parameter can be a value of Source Block Repeat address Update Mode This feature can be modified afterwards using unitary function LL_MDMA_SetBlkRepeatSrcAddrUpdate()

Definition at line 120 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateVal

Specifies the block repeat source address update value. This parameter can be a value Between 0 to 0x0000FFFF This feature can be modified afterwards using unitary function LL_MDMA_SetBlkRptSrcAddrUpdateValue()

Definition at line 128 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BufferableWriteMode

Specifies the transfer Bufferable Write Mode. This parameter can be a value of Bufferable Write Mode This feature can be modified afterwards using unitary function LL_MDMA_EnableBufferableWrMode() and LL_MDMA_DisableBufferableWrMode

Definition at line 152 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::BufferTransferLength

Specifies the length of a buffer transfer in bytes This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000007F. This feature can be modified afterwards using unitary function LL_MDMA_SetBufferTransferLength()

Definition at line 167 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::ByteEndianess

Specifies the Byte transfer endianness This parameter can be a value of Byte Endianness. This feature can be modified afterwards using unitary function LL_MDMA_SetByteEndianness()

Definition at line 144 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DestBurst

Specifies the destination burst size. This parameter can be a value of Transfer Destination Burst This feature can be modified afterwards using unitary function LL_MDMA_SetDestinationBurstSize()

Definition at line 171 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DestBus

Specifies the destination transfer bus, System AXI or AHB/TCM bus. This parameter can be a value of Destination BUS Selection This feature can be modified afterwards using unitary function LL_MDMA_SetDestBusSelection()

Definition at line 204 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DestDataSize

Specifies the destination data size. This parameter can be a value of Destination Data Size This feature can be modified afterwards using unitary function LL_MDMA_SetDestinationDataSize()

Definition at line 187 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DestIncMode

Specifies the destination increment mode. This parameter can be a value of Destination Increment Mode This feature can be modified afterwards using unitary function LL_MDMA_SetDestinationIncMode()

Definition at line 195 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DestIncSize

Specifies the destination increment size. This parameter can be a value of Destination Increment Offset Size This feature can be modified afterwards using unitary function LL_MDMA_SetDestinationIncSize()

Definition at line 179 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::DstAddress

Specifies the transfer destination address This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. This feature can be modified afterwards using unitary function LL_MDMA_SetDestinationAddress()

Definition at line 92 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::HalfWordEndianess

Specifies the Half Word transfer endianness This parameter can be a value of Half Word Endianness. This feature can be modified afterwards using unitary function LL_MDMA_SetHalfWordEndianness()

Definition at line 140 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::HWTrigger

Specifies the HW transfer trigger used when RequestMode is HW. This parameter can be a value of HW Trigger Selection This feature can be modified afterwards using unitary function LL_MDMA_SetHWTrigger()

Definition at line 104 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::LinkAddress

Specifies the linked list next transfer node address. This parameter can be a value Between 0 to 0xFFFFFFFF This feature can be modified afterwards using unitary function LL_MDMA_SetLinkAddress()

Definition at line 132 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::MaskAddress

Specifies the address to be updated (written) with MaskData after a request is served. MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served This parameter can be a value Between 0 to 0xFFFFFFFF This feature can be modified afterwards using unitary function LL_MDMA_SetMaskAddress()

Definition at line 212 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::MaskData

Specifies the value to be written to MaskAddress after a request is served. MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served This parameter can be a value Between 0 to 0xFFFFFFFF This feature can be modified afterwards using unitary function LL_MDMA_SetMaskData()

Definition at line 217 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::PackMode

Specifies the transfer Packing enabled or disabled. This parameter can be a value of Transfer Packing This feature can be modified afterwards using unitary function LL_MDMA_EnablePacking() and LL_MDMA_DisablePacking()

Definition at line 162 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::PaddingAlignment

Specifies the transfer Padding and Alignment. This parameter can be a value of Padding Alignment Mode This feature can be modified afterwards using unitary function LL_MDMA_SetPaddingAlignment()

Definition at line 158 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level This feature can be modified afterwards using unitary function LL_MDMA_SetChannelPriorityLevel()

Definition at line 148 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::RequestMode

Specifies the request mode Hardware or Software. This parameter can be a value of Request Mode This feature can be modified afterwards using unitary function LL_MDMA_SetRequestMode()

Definition at line 96 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrcAddress

Specifies the transfer source address This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. This feature can be modified afterwards using unitary function LL_MDMA_SetSourceAddress()

Definition at line 88 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrcBus

Specifies the source transfer bus, System AXI or AHB/TCM bus. This parameter can be a value of Source BUS Selection This feature can be modified afterwards using unitary function LL_MDMA_SetSrcBusSelection()

Definition at line 208 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrcDataSize

Specifies the source data size. This parameter can be a value of Source Data Size This feature can be modified afterwards using unitary function LL_MDMA_SetSourceDataSize()

Definition at line 191 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrcIncMode

Specifies the source increment mode. This parameter can be a value of Source Increment Mode This feature can be modified afterwards using unitary function LL_MDMA_SetSourceIncMode()

Definition at line 199 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrcIncSize

Specifies the source increment size. This parameter can be a value of Source Increment Offset Size This feature can be modified afterwards using unitary function LL_MDMA_SetSourceIncSize()

Definition at line 183 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::SrctBurst

Specifies the source burst size. This parameter can be a value of Transfer Source Burst This feature can be modified afterwards using unitary function LL_MDMA_SetSourceBurstSize()

Definition at line 175 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::TriggerMode

Specifies the transfer trigger mode. This parameter can be a value of Trigger Mode This feature can be modified afterwards using unitary function LL_MDMA_SetTriggerMode()

Definition at line 100 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_Init(), and LL_MDMA_StructInit().

uint32_t LL_MDMA_InitTypeDef::WordEndianess

Specifies the Word transfer endianness This parameter can be a value of Word Endianness. This feature can be modified afterwards using unitary function LL_MDMA_SetWordEndianness()

Definition at line 136 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init(), and LL_MDMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_mdma.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_MDMA_LinkNodeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_MDMA_LinkNodeTypeDef Struct Reference
MDMA Exported Init structure

LL MDMA linked list node structure definition. More...

#include <stm32h7xx_ll_mdma.h>

Data Fields

__IO uint32_t | CTCR
__IO uint32_t | CBNDTR
__IO uint32_t | CSAR
__IO uint32_t | CDAR
__IO uint32_t | CBRUR
__IO uint32_t | CLAR
__IO uint32_t | CTBR
__IO uint32_t | Reserved
__IO uint32_t | CMAR
__IO uint32_t | CMDR

Detailed Description

LL MDMA linked list node structure definition.

Note:
The Linked list node allows to define a new MDMA configuration (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). When CLAR register is configured to a non NULL value , each time a transfer ends, a new configuration (linked list node) is automatically loaded from the address given in CLAR register.

Definition at line 231 of file stm32h7xx_ll_mdma.h.

Field Documentation

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CBNDTR

New CBNDTR register configuration for the given MDMA linked list node

Definition at line 234 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CBRUR

New CBRUR register configuration for the given MDMA linked list node

Definition at line 237 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CDAR

New CDAR register configuration for the given MDMA linked list node

Definition at line 236 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CLAR

New CLAR register configuration for the given MDMA linked list node

Definition at line 238 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_ConnectLinkNode(), LL_MDMA_CreateLinkNode(), and LL_MDMA_DisconnectNextLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CMAR

New CMAR register configuration for the given MDMA linked list node

Definition at line 241 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CMDR

New CMDR register configuration for the given MDMA linked list node

Definition at line 242 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CSAR

New CSAR register configuration for the given MDMA linked list node

Definition at line 235 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CTBR

New CTBR register configuration for the given MDMA linked list node

Definition at line 239 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::CTCR

New CTCR register configuration for the given MDMA linked list node

Definition at line 233 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

__IO uint32_t LL_MDMA_LinkNodeTypeDef::Reserved

Reserved register

Definition at line 240 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_CreateLinkNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_mdma.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CHANNEL

Defines
CHANNEL
MDMA Exported Constants

Defines

#define | LL_MDMA_CHANNEL_0 0x00000000U
#define | LL_MDMA_CHANNEL_1 0x00000001U
#define | LL_MDMA_CHANNEL_2 0x00000002U
#define | LL_MDMA_CHANNEL_3 0x00000003U
#define | LL_MDMA_CHANNEL_4 0x00000004U
#define | LL_MDMA_CHANNEL_5 0x00000005U
#define | LL_MDMA_CHANNEL_6 0x00000006U
#define | LL_MDMA_CHANNEL_7 0x00000007U
#define | LL_MDMA_CHANNEL_8 0x00000008U
#define | LL_MDMA_CHANNEL_9 0x00000009U
#define | LL_MDMA_CHANNEL_10 0x0000000AU
#define | LL_MDMA_CHANNEL_11 0x0000000BU
#define | LL_MDMA_CHANNEL_12 0x0000000CU
#define | LL_MDMA_CHANNEL_13 0x0000000DU
#define | LL_MDMA_CHANNEL_14 0x0000000EU
#define | LL_MDMA_CHANNEL_15 0x0000000FU
#define | LL_MDMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_MDMA_CHANNEL_0 0x00000000U

Definition at line 258 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_1 0x00000001U

Definition at line 259 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_10 0x0000000AU

Definition at line 268 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_11 0x0000000BU

Definition at line 269 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_12 0x0000000CU

Definition at line 270 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_13 0x0000000DU

Definition at line 271 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_14 0x0000000EU

Definition at line 272 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_15 0x0000000FU

Definition at line 273 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_2 0x00000002U

Definition at line 260 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_3 0x00000003U

Definition at line 261 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_4 0x00000004U

Definition at line 262 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_5 0x00000005U

Definition at line 263 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_6 0x00000006U

Definition at line 264 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_7 0x00000007U

Definition at line 265 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_8 0x00000008U

Definition at line 266 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_9 0x00000009U

Definition at line 267 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_CHANNEL_ALL 0xFFFF0000U

Definition at line 274 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_DeInit().

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STM32H7B3xQ HAL User Manual: Word Endianness

Defines
Word Endianness
MDMA Exported Constants

Defines

#define | LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX

Define Documentation

#define LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX

word order exchanged when destination data size is double word

Definition at line 283 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U

Little endianess preserved for words

Definition at line 282 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

Generated on Tue Nov 12 2019 18:50:32 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Half Word Endianness

Defines
Half Word Endianness
MDMA Exported Constants

Defines

#define | LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX

Define Documentation

#define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX

half word order exchanged when destination data size is word or double word

Definition at line 293 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U

Little endianess preserved for half words

Definition at line 292 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Byte Endianness

Defines
Byte Endianness
MDMA Exported Constants

Defines

#define | LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX

Define Documentation

#define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX

byte order exchanged when destination data size is half word , word or double word

Definition at line 303 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U

Little endianess preserved for bytes

Definition at line 302 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
MDMA Exported Constants

Defines

#define | LL_MDMA_PRIORITY_LOW 0x00000000U
#define | LL_MDMA_PRIORITY_MEDIUM MDMA_CCR_PL_0
#define | LL_MDMA_PRIORITY_HIGH MDMA_CCR_PL_1
#define | LL_MDMA_PRIORITY_VERYHIGH MDMA_CCR_PL

Define Documentation

#define LL_MDMA_PRIORITY_HIGH MDMA_CCR_PL_1

Priority level : High

Definition at line 314 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 312 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_PRIORITY_MEDIUM MDMA_CCR_PL_0

Priority level : Medium

Definition at line 313 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_PRIORITY_VERYHIGH MDMA_CCR_PL

Priority level : Very_High

Definition at line 315 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Bufferable Write Mode

Defines
Bufferable Write Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_BUFF_WRITE_DISABLE 0x00000000U
#define | LL_MDMA_BUFF_WRITE_ENABLE MDMA_CTCR_BWM

Define Documentation

#define LL_MDMA_BUFF_WRITE_DISABLE 0x00000000U

destination write operation is non-bufferable

Definition at line 323 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_BUFF_WRITE_ENABLE MDMA_CTCR_BWM

destination write operation is bufferable

Definition at line 324 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Request Mode

Defines
Request Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_REQUEST_MODE_HW 0x00000000U
#define | LL_MDMA_REQUEST_MODE_SW MDMA_CTCR_SWRM

Define Documentation

#define LL_MDMA_REQUEST_MODE_HW 0x00000000U

Request mode is Hardware

Definition at line 332 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_REQUEST_MODE_SW MDMA_CTCR_SWRM

Request mode is Software

Definition at line 333 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Trigger Mode

Defines
Trigger Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_BUFFER_TRANSFER 0x00000000U
#define | LL_MDMA_BLOCK_TRANSFER MDMA_CTCR_TRGM_0
#define | LL_MDMA_REPEAT_BLOCK_TRANSFER MDMA_CTCR_TRGM_1
#define | LL_MDMA_FULL_TRANSFER MDMA_CTCR_TRGM

Define Documentation

#define LL_MDMA_BLOCK_TRANSFER MDMA_CTCR_TRGM_0

Each MDMA request (SW or HW) triggers a block transfer

Definition at line 342 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_BUFFER_TRANSFER 0x00000000U

Each MDMA request (SW or HW) triggers a buffer transfer

Definition at line 341 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_FULL_TRANSFER MDMA_CTCR_TRGM

Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any

Definition at line 344 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REPEAT_BLOCK_TRANSFER MDMA_CTCR_TRGM_1

Each MDMA request (SW or HW) triggers a repeated block transfer

Definition at line 343 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Padding Alignment Mode

Defines
Padding Alignment Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_DATAALIGN_RIGHT 0x00000000U
#define | LL_MDMA_DATAALIGN_RIGHT_SIGNED MDMA_CTCR_PAM_0
#define | LL_MDMA_DATAALIGN_LEFT MDMA_CTCR_PAM_1

Define Documentation

#define LL_MDMA_DATAALIGN_LEFT MDMA_CTCR_PAM_1

Left Aligned (padded with 0s)

Definition at line 355 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DATAALIGN_RIGHT 0x00000000U

Right Aligned, padded w/ 0s (default)

Definition at line 352 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_DATAALIGN_RIGHT_SIGNED MDMA_CTCR_PAM_0

Right Aligned, Sign extended , Note : this mode is allowed only if the Source data size smaller than Destination data size

Definition at line 353 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Transfer Packing

Defines
Transfer Packing
MDMA Exported Constants

Defines

#define | LL_MDMA_PACK_DISABLE 0x00000000U
#define | LL_MDMA_PACK_ENABLE MDMA_CTCR_PKE

Define Documentation

#define LL_MDMA_PACK_DISABLE 0x00000000U

Packing disabled

Definition at line 363 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_PACK_ENABLE MDMA_CTCR_PKE

Packing enabled

Definition at line 364 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Transfer Destination Burst

Defines
Transfer Destination Burst
MDMA Exported Constants

Defines

#define | LL_MDMA_DEST_BURST_SINGLE 0x00000000U
#define | LL_MDMA_DEST_BURST_2BEATS MDMA_CTCR_DBURST_0
#define | LL_MDMA_DEST_BURST_4BEATS MDMA_CTCR_DBURST_1
#define | LL_MDMA_DEST_BURST_8BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)
#define | LL_MDMA_DEST_BURST_16BEATS MDMA_CTCR_DBURST_2
#define | LL_MDMA_DEST_BURST_32BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)
#define | LL_MDMA_DEST_BURST_64BEATS (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)
#define | LL_MDMA_DEST_BURST_128BEATS (MDMA_CTCR_DBURST)

Define Documentation

#define LL_MDMA_DEST_BURST_128BEATS (MDMA_CTCR_DBURST)

Burst 128 beats

Definition at line 379 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_16BEATS MDMA_CTCR_DBURST_2

Burst 16 beats

Definition at line 376 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_2BEATS MDMA_CTCR_DBURST_0

Burst 2 beats

Definition at line 373 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_32BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)

Burst 32 beats

Definition at line 377 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_4BEATS MDMA_CTCR_DBURST_1

Burst 4 beats

Definition at line 374 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_64BEATS (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)

Burst 64 beats

Definition at line 378 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_8BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)

Burst 8 beats

Definition at line 375 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BURST_SINGLE 0x00000000U

Single transfer

Definition at line 372 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Transfer Source Burst

Defines
Transfer Source Burst
MDMA Exported Constants

Defines

#define | LL_MDMA_SRC_BURST_SINGLE 0x00000000U
#define | LL_MDMA_SRC_BURST_2BEATS MDMA_CTCR_SBURST_0
#define | LL_MDMA_SRC_BURST_4BEATS MDMA_CTCR_SBURST_1
#define | LL_MDMA_SRC_BURST_8BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)
#define | LL_MDMA_SRC_BURST_16BEATS MDMA_CTCR_SBURST_2
#define | LL_MDMA_SRC_BURST_32BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)
#define | LL_MDMA_SRC_BURST_64BEATS (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)
#define | LL_MDMA_SRC_BURST_128BEATS MDMA_CTCR_SBURST

Define Documentation

#define LL_MDMA_SRC_BURST_128BEATS MDMA_CTCR_SBURST

Burst 128 beats

Definition at line 394 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_16BEATS MDMA_CTCR_SBURST_2

Burst 16 beats

Definition at line 391 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_2BEATS MDMA_CTCR_SBURST_0

Burst 2 beats

Definition at line 388 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_32BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)

Burst 32 beats

Definition at line 392 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_4BEATS MDMA_CTCR_SBURST_1

Burst 4 beats

Definition at line 389 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_64BEATS (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)

Burst 64 beats

Definition at line 393 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_8BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)

Burst 8 beats

Definition at line 390 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BURST_SINGLE 0x00000000U

Single transfer

Definition at line 387 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Destination Increment Offset Size

Defines
Destination Increment Offset Size
MDMA Exported Constants

Defines

#define | LL_MDMA_DEST_INC_OFFSET_BYTE 0x00000000U
#define | LL_MDMA_DEST_INC_OFFSET_HALFWORD MDMA_CTCR_DINCOS_0
#define | LL_MDMA_DEST_INC_OFFSET_WORD MDMA_CTCR_DINCOS_1
#define | LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD MDMA_CTCR_DINCOS

Define Documentation

#define LL_MDMA_DEST_INC_OFFSET_BYTE 0x00000000U

offset is Byte (8-bit)

Definition at line 402 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD MDMA_CTCR_DINCOS

offset is Double Word (64-bit)

Definition at line 405 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_INC_OFFSET_HALFWORD MDMA_CTCR_DINCOS_0

offset is Half Word (16-bit)

Definition at line 403 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_INC_OFFSET_WORD MDMA_CTCR_DINCOS_1

offset is Word (32-bit)

Definition at line 404 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Source Increment Offset Size

Defines
Source Increment Offset Size
MDMA Exported Constants

Defines

#define | LL_MDMA_SRC_INC_OFFSET_BYTE 0x00000000U
#define | LL_MDMA_SRC_INC_OFFSET_HALFWORD MDMA_CTCR_SINCOS_0
#define | LL_MDMA_SRC_INC_OFFSET_WORD MDMA_CTCR_SINCOS_1
#define | LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD MDMA_CTCR_SINCOS

Define Documentation

#define LL_MDMA_SRC_INC_OFFSET_BYTE 0x00000000U

offset is Byte (8-bit)

Definition at line 413 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD MDMA_CTCR_SINCOS

offset is Double Word (64-bit)

Definition at line 416 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_INC_OFFSET_HALFWORD MDMA_CTCR_SINCOS_0

offset is Half Word (16-bit)

Definition at line 414 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_INC_OFFSET_WORD MDMA_CTCR_SINCOS_1

offset is Word (32-bit)

Definition at line 415 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Destination Data Size

Defines
Destination Data Size
MDMA Exported Constants

Defines

#define | LL_MDMA_DEST_DATA_SIZE_BYTE 0x00000000U
#define | LL_MDMA_DEST_DATA_SIZE_HALFWORD MDMA_CTCR_DSIZE_0
#define | LL_MDMA_DEST_DATA_SIZE_WORD MDMA_CTCR_DSIZE_1
#define | LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE

Define Documentation

#define LL_MDMA_DEST_DATA_SIZE_BYTE 0x00000000U

Destination data size is Byte

Definition at line 424 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE

Destination data size is double word

Definition at line 427 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_DATA_SIZE_HALFWORD MDMA_CTCR_DSIZE_0

Destination data size is half word

Definition at line 425 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_DATA_SIZE_WORD MDMA_CTCR_DSIZE_1

Destination data size is word

Definition at line 426 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Source Data Size

Defines
Source Data Size
MDMA Exported Constants

Defines

#define | LL_MDMA_SRC_DATA_SIZE_BYTE 0x00000000U
#define | LL_MDMA_SRC_DATA_SIZE_HALFWORD MDMA_CTCR_SSIZE_0
#define | LL_MDMA_SRC_DATA_SIZE_WORD MDMA_CTCR_SSIZE_1
#define | LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE

Define Documentation

#define LL_MDMA_SRC_DATA_SIZE_BYTE 0x00000000U

Source data size is Byte

Definition at line 435 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE

Source data size is double word

Definition at line 438 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_DATA_SIZE_HALFWORD MDMA_CTCR_SSIZE_0

Source data size is half word

Definition at line 436 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_DATA_SIZE_WORD MDMA_CTCR_SSIZE_1

Source data size is word

Definition at line 437 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Destination Increment Mode

Defines
Destination Increment Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_DEST_FIXED 0x00000000U
#define | LL_MDMA_DEST_INCREMENT MDMA_CTCR_DINC_1
#define | LL_MDMA_DEST_DECREMENT MDMA_CTCR_DINC

Define Documentation

#define LL_MDMA_DEST_DECREMENT MDMA_CTCR_DINC

Destination address pointer is decremented after each data transfer

Definition at line 448 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_FIXED 0x00000000U

Destination address pointer is fixed

Definition at line 446 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_DEST_INCREMENT MDMA_CTCR_DINC_1

Destination address pointer is incremented after each data transfer

Definition at line 447 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Source Increment Mode

Defines
Source Increment Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_SRC_FIXED 0x00000000U
#define | LL_MDMA_SRC_INCREMENT MDMA_CTCR_SINC_1
#define | LL_MDMA_SRC_DECREMENT MDMA_CTCR_SINC

Define Documentation

#define LL_MDMA_SRC_DECREMENT MDMA_CTCR_SINC

Destination address pointer is decremented after each data transfer

Definition at line 458 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_FIXED 0x00000000U

Destination address pointer is fixed

Definition at line 456 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_SRC_INCREMENT MDMA_CTCR_SINC_1

Destination address pointer is incremented after each data transfer

Definition at line 457 of file stm32h7xx_ll_mdma.h.

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STM32H7B3xQ HAL User Manual: Block Repeat Destination address Update Mode

Defines
Block Repeat Destination address Update Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT 0x00000000U
#define | LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT MDMA_CBNDTR_BRDUM

Define Documentation

#define LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT MDMA_CBNDTR_BRDUM

Destination address pointer is decremented after each block transfer by Destination Update Value

Definition at line 467 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT 0x00000000U

Destination address pointer is incremented after each block transfer by Destination Update Value

Definition at line 466 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Source Block Repeat address Update Mode

Defines
Source Block Repeat address Update Mode
MDMA Exported Constants

Defines

#define | LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT 0x00000000U
#define | LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT MDMA_CBNDTR_BRSUM

Define Documentation

#define LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT MDMA_CBNDTR_BRSUM

Source address pointer is decremented after each block transfer by Source Update Value

Definition at line 476 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT 0x00000000U

Source address pointer is incremented after each block transfer by Source Update Value

Definition at line 475 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Destination BUS Selection

Defines
Destination BUS Selection
MDMA Exported Constants

Defines

#define | LL_MDMA_DEST_BUS_SYSTEM_AXI 0x00000000U
#define | LL_MDMA_DEST_BUS_AHB_TCM MDMA_CTBR_DBUS

Define Documentation

#define LL_MDMA_DEST_BUS_AHB_TCM MDMA_CTBR_DBUS

AHB bus/TCM is used as destination

Definition at line 485 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_DEST_BUS_SYSTEM_AXI 0x00000000U

System/AXI bus is used as destination

Definition at line 484 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

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STM32H7B3xQ HAL User Manual: Source BUS Selection

Defines
Source BUS Selection
MDMA Exported Constants

Defines

#define | LL_MDMA_SRC_BUS_SYSTEM_AXI 0x00000000U
#define | LL_MDMA_SRC_BUS_AHB_TCM MDMA_CTBR_SBUS

Define Documentation

#define LL_MDMA_SRC_BUS_AHB_TCM MDMA_CTBR_SBUS

AHB bus/TCM is used as source

Definition at line 494 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_SRC_BUS_SYSTEM_AXI 0x00000000U

System/AXI bus is used as source

Definition at line 493 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HW Trigger Selection

Defines
HW Trigger Selection
MDMA Exported Constants

Defines

#define | LL_MDMA_REQ_DMA1_STREAM0_TC 0x00000000U
#define | LL_MDMA_REQ_DMA1_STREAM1_TC 0x00000001U
#define | LL_MDMA_REQ_DMA1_STREAM2_TC 0x00000002U
#define | LL_MDMA_REQ_DMA1_STREAM3_TC 0x00000003U
#define | LL_MDMA_REQ_DMA1_STREAM4_TC 0x00000004U
#define | LL_MDMA_REQ_DMA1_STREAM5_TC 0x00000005U
#define | LL_MDMA_REQ_DMA1_STREAM6_TC 0x00000006U
#define | LL_MDMA_REQ_DMA1_STREAM7_TC 0x00000007U
#define | LL_MDMA_REQ_DMA2_STREAM0_TC 0x00000008U
#define | LL_MDMA_REQ_DMA2_STREAM1_TC 0x00000009U
#define | LL_MDMA_REQ_DMA2_STREAM2_TC 0x0000000AU
#define | LL_MDMA_REQ_DMA2_STREAM3_TC 0x0000000BU
#define | LL_MDMA_REQ_DMA2_STREAM4_TC 0x0000000CU
#define | LL_MDMA_REQ_DMA2_STREAM5_TC 0x0000000DU
#define | LL_MDMA_REQ_DMA2_STREAM6_TC 0x0000000EU
#define | LL_MDMA_REQ_DMA2_STREAM7_TC 0x0000000FU
#define | LL_MDMA_REQ_LTDC_LINE_IT 0x00000010U
#define | LL_MDMA_REQ_JPEG_INFIFO_TH 0x00000011U
#define | LL_MDMA_REQ_JPEG_INFIFO_NF 0x00000012U
#define | LL_MDMA_REQ_JPEG_OUTFIFO_TH 0x00000013U
#define | LL_MDMA_REQ_JPEG_OUTFIFO_NE 0x00000014U
#define | LL_MDMA_REQ_JPEG_END_CONVERSION 0x00000015U
#define | LL_MDMA_REQ_OCTOSPI1_FIFO_TH 0x00000016U
#define | LL_MDMA_REQ_OCTOSPI1_TC 0x00000017U
#define | LL_MDMA_REQ_DMA2D_CLUT_TC 0x00000018U
#define | LL_MDMA_REQ_DMA2D_TC 0x00000019U
#define | LL_MDMA_REQ_DMA2D_TW 0x0000001AU
#define | LL_MDMA_REQ_SDMMC1_END_DATA 0x0000001DU
#define | LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER 0x0000001EU
#define | LL_MDMA_REQ_SDMMC1_COMMAND_END 0x0000001FU
#define | LL_MDMA_REQ_OCTOSPI2_FIFO_TH 0x00000020U
#define | LL_MDMA_REQ_OCTOSPI2_TC 0x00000021U

Define Documentation

#define LL_MDMA_REQ_DMA1_STREAM0_TC 0x00000000U

MDMA HW Trigger (request) is DMA1 Stream 0 Transfer Complete Flag

Definition at line 502 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_StructInit().

#define LL_MDMA_REQ_DMA1_STREAM1_TC 0x00000001U

MDMA HW Trigger (request) is DMA1 Stream 1 Transfer Complete Flag

Definition at line 503 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM2_TC 0x00000002U

MDMA HW Trigger (request) is DMA1 Stream 2 Transfer Complete Flag

Definition at line 504 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM3_TC 0x00000003U

MDMA HW Trigger (request) is DMA1 Stream 3 Transfer Complete Flag

Definition at line 505 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM4_TC 0x00000004U

MDMA HW Trigger (request) is DMA1 Stream 4 Transfer Complete Flag

Definition at line 506 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM5_TC 0x00000005U

MDMA HW Trigger (request) is DMA1 Stream 5 Transfer Complete Flag

Definition at line 507 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM6_TC 0x00000006U

MDMA HW Trigger (request) is DMA1 Stream 6 Transfer Complete Flag

Definition at line 508 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA1_STREAM7_TC 0x00000007U

MDMA HW Trigger (request) is DMA1 Stream 7 Transfer Complete Flag

Definition at line 509 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM0_TC 0x00000008U

MDMA HW Trigger (request) is DMA2 Stream 0 Transfer Complete Flag

Definition at line 510 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM1_TC 0x00000009U

MDMA HW Trigger (request) is DMA2 Stream 1 Transfer Complete Flag

Definition at line 511 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM2_TC 0x0000000AU

MDMA HW Trigger (request) is DMA2 Stream 2 Transfer Complete Flag

Definition at line 512 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM3_TC 0x0000000BU

MDMA HW Trigger (request) is DMA2 Stream 3 Transfer Complete Flag

Definition at line 513 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM4_TC 0x0000000CU

MDMA HW Trigger (request) is DMA2 Stream 4 Transfer Complete Flag

Definition at line 514 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM5_TC 0x0000000DU

MDMA HW Trigger (request) is DMA2 Stream 5 Transfer Complete Flag

Definition at line 515 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM6_TC 0x0000000EU

MDMA HW Trigger (request) is DMA2 Stream 6 Transfer Complete Flag

Definition at line 516 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2_STREAM7_TC 0x0000000FU

MDMA HW Trigger (request) is DMA2 Stream 7 Transfer Complete Flag

Definition at line 517 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2D_CLUT_TC 0x00000018U

MDMA HW Trigger (request) is DMA2D CLUT Transfer Complete Flag

Definition at line 536 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2D_TC 0x00000019U

MDMA HW Trigger (request) is DMA2D Transfer Complete Flag

Definition at line 537 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_DMA2D_TW 0x0000001AU

MDMA HW Trigger (request) is DMA2D Transfer Watermark Flag

Definition at line 538 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_JPEG_END_CONVERSION 0x00000015U

MDMA HW Trigger (request) is JPEG End of conversion Flag

Definition at line 526 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_JPEG_INFIFO_NF 0x00000012U

MDMA HW Trigger (request) is JPEG Input FIFO not full Flag

Definition at line 523 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_JPEG_INFIFO_TH 0x00000011U

MDMA HW Trigger (request) is JPEG Input FIFO threshold Flag

Definition at line 522 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_JPEG_OUTFIFO_NE 0x00000014U

MDMA HW Trigger (request) is JPEG Output FIFO not empty Flag

Definition at line 525 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_JPEG_OUTFIFO_TH 0x00000013U

MDMA HW Trigger (request) is JPEG Output FIFO threshold Flag

Definition at line 524 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_LTDC_LINE_IT 0x00000010U

MDMA HW Trigger (request) is LTDC Line interrupt Flag

Definition at line 519 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_OCTOSPI1_FIFO_TH 0x00000016U

MDMA HW Trigger (request) is OCTOSPI1 FIFO threshold Flag

Definition at line 533 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_OCTOSPI1_TC 0x00000017U

MDMA HW Trigger (request) is OCTOSPI1 Transfer complete Flag

Definition at line 534 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_OCTOSPI2_FIFO_TH 0x00000020U

MDMA HW Trigger (request) is OCTOSPI2 FIFO threshold Flag

Definition at line 547 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_OCTOSPI2_TC 0x00000021U

MDMA HW Trigger (request) is OCTOSPI2 Transfer complete Flag

Definition at line 548 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_SDMMC1_COMMAND_END 0x0000001FU

MDMA HW Trigger (request) is SDMMC1 Command End Flag : This trigger is available starting from STM32H7 Rev.B devices

Definition at line 545 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER 0x0000001EU

MDMA HW Trigger (request) is SDMMC1 Internal DMA buffer End Flag : This trigger is available starting from STM32H7 Rev.B devices

Definition at line 544 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_REQ_SDMMC1_END_DATA 0x0000001DU

MDMA HW Trigger (request) is SDMMC1 End of Data Flag

Definition at line 543 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Transfer Error Direction

Defines
Transfer Error Direction
MDMA Exported Constants

Defines

#define | LL_MDMA_READ_ERROR 0x00000000U
#define | LL_MDMA_WRITE_ERROR MDMA_CESR_TED

Define Documentation

#define LL_MDMA_READ_ERROR 0x00000000U

Last transfer error on the channel was a related to a read access

Definition at line 557 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_WRITE_ERROR MDMA_CESR_TED

Last transfer error on the channel was a related to a write access

Definition at line 558 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
MDMA Exported Macros

Defines

#define | LL_MDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in MDMA register.
#define | LL_MDMA_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in MDMA register.

Define Documentation

#define LL_MDMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in MDMA register.

Parameters:
__INSTANCE__ | MDMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 590 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in MDMA register.

Parameters:
__INSTANCE__ | MDMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 582 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_DeInit().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Convert MDMAxChannely

Defines
Convert MDMAxChannely
MDMA Exported Macros

Defines

#define | LL_MDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (MDMA)
Convert MDMAx_Channely into MDMAx.
#define | LL_MDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert MDMAx_Channely into LL_MDMA_CHANNEL_y.
#define | LL_MDMA_GET_CHANNEL_INSTANCE(__MDMA_INSTANCE__, __CHANNEL__)
Convert MDMA Instance MDMAx and LL_MDMA_CHANNEL_y into MDMAx_Channely.

Define Documentation

#define LL_MDMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel0 )) ? LL_MDMA_CHANNEL_0  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel1 )) ? LL_MDMA_CHANNEL_1  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel2 )) ? LL_MDMA_CHANNEL_2  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel3 )) ? LL_MDMA_CHANNEL_3  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel4 )) ? LL_MDMA_CHANNEL_4  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel5 )) ? LL_MDMA_CHANNEL_5  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel6 )) ? LL_MDMA_CHANNEL_6  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel7 )) ? LL_MDMA_CHANNEL_7  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel8 )) ? LL_MDMA_CHANNEL_8  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel9 )) ? LL_MDMA_CHANNEL_9  : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel10)) ? LL_MDMA_CHANNEL_10 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel11)) ? LL_MDMA_CHANNEL_11 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel12)) ? LL_MDMA_CHANNEL_12 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel13)) ? LL_MDMA_CHANNEL_13 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel14)) ? LL_MDMA_CHANNEL_14 : \
 LL_MDMA_CHANNEL_15)

Convert MDMAx_Channely into LL_MDMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ MDMAx_Channely
Return values:
LL_MDMA_CHANNEL_y

Definition at line 610 of file stm32h7xx_ll_mdma.h.

#define LL_MDMA_GET_CHANNEL_INSTANCE | ( | __MDMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_0 )) ? MDMA_Channel0  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_1 )) ? MDMA_Channel1  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_2 )) ? MDMA_Channel2  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_3 )) ? MDMA_Channel3  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_4 )) ? MDMA_Channel4  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_5 )) ? MDMA_Channel5  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_6 )) ? MDMA_Channel6  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_7 )) ? MDMA_Channel7  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_8 )) ? MDMA_Channel8  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_9 )) ? MDMA_Channel9  : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_10)) ? MDMA_Channel10 : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_11)) ? MDMA_Channel11 : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_12)) ? MDMA_Channel12 : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_13)) ? MDMA_Channel13 : \
 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_14)) ? MDMA_Channel14 : \
 MDMA_Channel15)

Convert MDMA Instance MDMAx and LL_MDMA_CHANNEL_y into MDMAx_Channely.

Parameters:
__MDMA_INSTANCE__ | MDMAx
__CHANNEL__ | LL_MDMA_CHANNEL_y
Return values:
MDMAx_Channely

Definition at line 634 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_DeInit().

#define LL_MDMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (MDMA)

Convert MDMAx_Channely into MDMAx.

Parameters:
__CHANNEL_INSTANCE__ MDMAx_Channely
Return values:
MDMAx

Definition at line 603 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
MDMA Exported Functions

Functions

__STATIC_INLINE void | LL_MDMA_EnableChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA channel.
__STATIC_INLINE void | LL_MDMA_DisableChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA channel.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA channel is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_GenerateSWRequest (MDMA_TypeDef *MDMAx, uint32_t Channel)
Generate a SW transfer request on the MDMA channel.
__STATIC_INLINE void | LL_MDMA_ConfigXferEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.
__STATIC_INLINE void | LL_MDMA_SetWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Words Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Words Endianess.
__STATIC_INLINE void | LL_MDMA_SetHalfWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Half Words Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetHalfWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Half Words Endianess.
__STATIC_INLINE void | LL_MDMA_SetByteEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Bytes Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetByteEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Bytes Endianess.
__STATIC_INLINE void | LL_MDMA_SetChannelPriorityLevel (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_MDMA_GetChannelPriorityLevel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_MDMA_ConfigTransfer (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)
Configure MDMA transfer parameters.
__STATIC_INLINE void | LL_MDMA_EnableBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable Bufferable Write Mode.
__STATIC_INLINE void | LL_MDMA_DisableBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable Bufferable Write Mode.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if Bufferable Write Mode is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_SetRequestMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)
Set Request Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetRequestMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Request Mode.
__STATIC_INLINE void | LL_MDMA_SetTriggerMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)
Set Trigger Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetTriggerMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Trigger Mode.
__STATIC_INLINE void | LL_MDMA_SetPaddingAlignment (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)
Set Padding Alignment.
__STATIC_INLINE uint32_t | LL_MDMA_GetPaddingAlignment (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Padding Alignment.
__STATIC_INLINE void | LL_MDMA_EnablePacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable Packing.
__STATIC_INLINE void | LL_MDMA_DisablePacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable Packing.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledPacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if packing is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_SetBufferTransferLength (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)
Set Buffer Transfer Length.
__STATIC_INLINE uint32_t | LL_MDMA_GetBufferTransferLength (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Buffer Transfer Length.
__STATIC_INLINE void | LL_MDMA_SetDestinationBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)
Set Destination burst transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination burst transfer.
__STATIC_INLINE void | LL_MDMA_SetSourceBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)
Set Source burst transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source burst transfer.
__STATIC_INLINE void | LL_MDMA_SetDestinationIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
Set Destination Increment Offset Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Increment Offset Size.
__STATIC_INLINE void | LL_MDMA_SetSourceIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
Set Source Increment Offset Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Increment Offset Size.
__STATIC_INLINE void | LL_MDMA_SetDestinationDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)
Set Destination Data Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Data Size.
__STATIC_INLINE void | LL_MDMA_SetSourceDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)
Set Source Data Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Data Size.
__STATIC_INLINE void | LL_MDMA_SetDestinationIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)
Set Destination Increment Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Increment Mode.
__STATIC_INLINE void | LL_MDMA_SetSourceIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)
Set Source Increment Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Increment Mode.
__STATIC_INLINE void | LL_MDMA_ConfigBlkCounters (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)
Configure MDMA Block number of data and repeat Count.
__STATIC_INLINE void | LL_MDMA_SetBlkDataLength (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)
Set Block Number of data bytes to transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkDataLength (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Number of data bytes to transfer.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatCount (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)
Set Block Repeat Count.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatCount (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Count.
__STATIC_INLINE void | LL_MDMA_ConfigBlkRepeatAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure MDMA block repeat address update mode.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatDestAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)
Set Block Repeat Destination address Update Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatDestAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Destination address Update Mode.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatSrcAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)
Set Block Repeat Source address Update Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatSrcAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Source address Update Mode.
__STATIC_INLINE void | LL_MDMA_ConfigAddresses (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_MDMA_SetSourceAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)
Set transfer Source address.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Source address.
__STATIC_INLINE void | LL_MDMA_SetDestinationAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)
Set transfer Destination address.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Destination address.
__STATIC_INLINE void | LL_MDMA_ConfigBlkRptAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)
Configure the Source and Destination Block repeat addresses Update value.
__STATIC_INLINE void | LL_MDMA_SetBlkRptDestAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)
Set transfer Destination address Update Value.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRptDestAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Destination address Update Value.
__STATIC_INLINE void | LL_MDMA_SetBlkRptSrcAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)
Set transfer Source address Update Value.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRptSrcAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Source address Update Value.
__STATIC_INLINE void | LL_MDMA_SetLinkAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)
Set transfer Link Address.
__STATIC_INLINE uint32_t | LL_MDMA_GetLinkAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Link Address.
__STATIC_INLINE void | LL_MDMA_ConfigBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure MDMA source and destination bus selection.
__STATIC_INLINE void | LL_MDMA_SetDestBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)
Set Destination Bus Selection.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Bus Selection.
__STATIC_INLINE void | LL_MDMA_SetSrcBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)
Set Source Bus Selection.
__STATIC_INLINE uint32_t | LL_MDMA_GetSrcBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Bus Selection.
__STATIC_INLINE void | LL_MDMA_SetHWTrigger (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)
Set Transfer hardware trigger (Request).
__STATIC_INLINE uint32_t | LL_MDMA_GetHWTrigger (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer hardware trigger (Request).
__STATIC_INLINE void | LL_MDMA_SetMaskAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)
Set Mask Address.
__STATIC_INLINE uint32_t | LL_MDMA_GetMaskAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Mask Address.
__STATIC_INLINE void | LL_MDMA_SetMaskData (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)
Set Mask Data.
__STATIC_INLINE uint32_t | LL_MDMA_GetMaskData (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Mask Data.
__STATIC_INLINE uint32_t | LL_MDMA_GetXferErrorDirection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer Error Direction.
__STATIC_INLINE uint32_t | LL_MDMA_GetXferErrorLSBAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer Error LSB Address.

Function Documentation

__STATIC_INLINE void LL_MDMA_ConfigAddresses | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the MDMA channel is enabled.
Reference Manual to LL API cross reference:
CSAR SAR LL_MDMA_ConfigAddresses
Reference Manual to LL API cross reference:
CDAR DAR LL_MDMA_ConfigAddresses
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 2530 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_ConfigBlkCounters | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | BlockRepeatCount,
 |  | uint32_t | BlkDataLength
 | ) |  |

Configure MDMA Block number of data and repeat Count.

Reference Manual to LL API cross reference:
CBNDTR BRC LL_MDMA_ConfigBlkCounters
Reference Manual to LL API cross reference:
CBNDTR BNDT LL_MDMA_ConfigBlkCounters
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
BlockRepeatCount | Between 0 to 0x00000FFF
BlkDataLength | Between 0 to 0x00010000
Return values:
None

Definition at line 2201 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure MDMA block repeat address update mode.

Reference Manual to LL API cross reference:
CBNDTR BRDUM LL_MDMA_ConfigBlkRepeatAddrUpdate
Reference Manual to LL API cross reference:
CBNDTR BRSUM LL_MDMA_ConfigBlkRepeatAddrUpdate
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Configuration This parameter must be a combination of all the following values:
  • LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT or LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
  • LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
Return values:
None

Definition at line 2362 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrctAdrUpdateValue,
 |  | uint32_t | DestAdrUpdateValue
 | ) |  |

Configure the Source and Destination Block repeat addresses Update value.

Note:
This API must not be called when the MDMA channel is enabled.
Reference Manual to LL API cross reference:
CBRUR DUV LL_MDMA_ConfigBlkRptAddrUpdateValue
Reference Manual to LL API cross reference:
CBRUR SUV LL_MDMA_ConfigBlkRptAddrUpdateValue
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrctAdrUpdateValue | Min_Data = 0 and Max_Data = 0x0000FFFF
DestAdrUpdateValue | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 2688 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_ConfigBusSelection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure MDMA source and destination bus selection.

Reference Manual to LL API cross reference:
CTBR DBUS LL_MDMA_ConfigBusSelection
Reference Manual to LL API cross reference:
CTBR SBUS LL_MDMA_ConfigBusSelection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Configuration This parameter must be a combination of all the following values:
  • LL_MDMA_DEST_BUS_SYSTEM_AXI or LL_MDMA_DEST_BUS_AHB_TCM
  • LL_MDMA_SRC_BUS_SYSTEM_AXI or LL_MDMA_SRC_BUS_AHB_TCM
Return values:
None

Definition at line 2910 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_ConfigTransfer | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration,
 |  | uint32_t | BufferXferLength
 | ) |  |

Configure MDMA transfer parameters.

Reference Manual to LL API cross reference:
CTCR BWM LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR SWRM LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR TRGM LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR PAM LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR PKE LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR TLEN LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR DBURST LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR SBURST LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR DINCOS LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR SINCOS LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR DSIZE LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR SSIZE LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR DINC LL_MDMA_ConfigTransfer
Reference Manual to LL API cross reference:
CTCR SINC LL_MDMA_ConfigTransfer
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Configuration This parameter must be a combination of all the following values:
  • LL_MDMA_BUFF_WRITE_DISABLE or LL_MDMA_BUFF_WRITE_ENABLE
  • LL_MDMA_REQUEST_MODE_HW or LL_MDMA_REQUEST_MODE_SW
  • LL_MDMA_BUFFER_TRANSFER or LL_MDMA_BLOCK_TRANSFER or LL_MDMA_REPEAT_BLOCK_TRANSFER or LL_MDMA_FULL_TRANSFER
  • LL_MDMA_DATAALIGN_RIGHT or LL_MDMA_DATAALIGN_RIGHT_SIGNED or LL_MDMA_DATAALIGN_LEFT
  • LL_MDMA_PACK_DISABLE or LL_MDMA_PACK_ENABLE
  • LL_MDMA_DEST_BURST_SINGLE or LL_MDMA_DEST_BURST_2BEATS or LL_MDMA_DEST_BURST_4BEATS or LL_MDMA_DEST_BURST_8BEATS or LL_MDMA_DEST_BURST_16BEATS or LL_MDMA_DEST_BURST_32BEATS or LL_MDMA_DEST_BURST_64BEATS or LL_MDMA_DEST_BURST_128BEATS
  • LL_MDMA_SRC_BURST_SINGLE or LL_MDMA_SRC_BURST_2BEATS or LL_MDMA_SRC_BURST_4BEATS or LL_MDMA_SRC_BURST_8BEATS or LL_MDMA_SRC_BURST_16BEATS or LL_MDMA_SRC_BURST_32BEATS or LL_MDMA_SRC_BURST_64BEATS or LL_MDMA_SRC_BURST_128BEATS
  • LL_MDMA_DEST_INC_OFFSET_BYTE or LL_MDMA_DEST_INC_OFFSET_HALFWORD or LL_MDMA_DEST_INC_OFFSET_WORD or LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
  • LL_MDMA_SRC_INC_OFFSET_BYTE or LL_MDMA_SRC_INC_OFFSET_HALFWORD or LL_MDMA_SRC_INC_OFFSET_WORD or LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
  • LL_MDMA_DEST_DATA_SIZE_BYTE or LL_MDMA_DEST_DATA_SIZE_HALFWORD or LL_MDMA_DEST_DATA_SIZE_WORD or LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
  • LL_MDMA_SRC_DATA_SIZE_BYTE or LL_MDMA_SRC_DATA_SIZE_HALFWORD or LL_MDMA_SRC_DATA_SIZE_WORD or LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
  • LL_MDMA_DEST_FIXED or LL_MDMA_DEST_INCREMENT or LL_MDMA_DEST_DECREMENT
  • LL_MDMA_SRC_FIXED or LL_MDMA_SRC_INCREMENT or LL_MDMA_SRC_DECREMENT
BufferXferLength | This parameter can be a value Between 0 to 0x0000007F
Return values:
None

Definition at line 1147 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_ConfigXferEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.

Reference Manual to LL API cross reference:
CCR WEX LL_MDMA_ConfigXferEndianness
Reference Manual to LL API cross reference:
CCR HEX LL_MDMA_ConfigXferEndianness
Reference Manual to LL API cross reference:
CCR BEX LL_MDMA_ConfigXferEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Configuration This parameter must be a combination of all the following values:
  • LL_MDMA_WORD_ENDIANNESS_PRESERVE or LL_MDMA_WORD_ENDIANNESS_EXCHANGE
  • LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE or LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
  • LL_MDMA_BYTE_ENDIANNESS_PRESERVE or LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
Return values:
None

Definition at line 818 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Bufferable Write Mode.

Reference Manual to LL API cross reference:
CTCR BWM LL_MDMA_DisableBufferableWrMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 1208 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_DisableChannel | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_MDMA_DisableChannel
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 722 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_DeInit().

__STATIC_INLINE void LL_MDMA_DisablePacking | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Packing.

Reference Manual to LL API cross reference:
CTCR PKE LL_MDMA_DisablePacking
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 1503 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Bufferable Write Mode.

Reference Manual to LL API cross reference:
CTCR BWM LL_MDMA_EnableBufferableWrMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 1178 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableChannel | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_MDMA_EnableChannel
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 692 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnablePacking | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Packing.

Reference Manual to LL API cross reference:
CTCR PKE LL_MDMA_EnablePacking
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 1473 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_GenerateSWRequest | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Generate a SW transfer request on the MDMA channel.

Reference Manual to LL API cross reference:
CCR SWRQ LL_MDMA_GenerateSWRequest
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 782 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Block Number of data bytes to transfer.

Reference Manual to LL API cross reference:
CBNDTR BNDT LL_MDMA_GetBlkDataLength
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x00010000
None

Definition at line 2265 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Block Repeat Count.

Reference Manual to LL API cross reference:
CBNDTR BRC LL_MDMA_GetBlkRepeatCount
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x00000FFF
None

Definition at line 2328 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Block Repeat Destination address Update Mode.

Reference Manual to LL API cross reference:
CBNDTR BRDUM LL_MDMA_GetBlkRepeatDestAddrUpdate
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT
  • LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
None

Definition at line 2430 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Block Repeat Source address Update Mode.

Reference Manual to LL API cross reference:
CBNDTR BRSUM LL_MDMA_GetBlkRepeatSrcAddrUpdate
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT
  • LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
None

Definition at line 2496 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get transfer Destination address Update Value.

Reference Manual to LL API cross reference:
CBRUR DUV LL_MDMA_GetBlkRptDestAddrUpdateValue
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x0000FFFF
None

Definition at line 2752 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get transfer Source address Update Value.

Reference Manual to LL API cross reference:
CBRUR SUV LL_MDMA_GetBlkRptSrcAddrUpdateValue
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x0000FFFF
None

Definition at line 2814 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Buffer Transfer Length.

Reference Manual to LL API cross reference:
CTCR TLEN LL_MDMA_GetBufferTransferLength
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x0000007F
None

Definition at line 1596 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Bytes Endianess.

Reference Manual to LL API cross reference:
CCR BEX LL_MDMA_GetByteEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_BYTE_ENDIANNESS_PRESERVE
  • LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
None

Definition at line 1017 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_MDMA_GetChannelPriorityLevel
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_PRIORITY_LOW
  • LL_MDMA_PRIORITY_MEDIUM
  • LL_MDMA_PRIORITY_HIGH
  • LL_MDMA_PRIORITY_VERYHIGH
None

Definition at line 1087 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Destination Bus Selection.

Reference Manual to LL API cross reference:
CTBR DBUS LL_MDMA_GetDestBusSelection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DEST_BUS_SYSTEM_AXI
  • LL_MDMA_DEST_BUS_AHB_TCM
None

Definition at line 2978 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get transfer Destination address.

Reference Manual to LL API cross reference:
CDAR DAR LL_MDMA_GetDestinationAddress
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0xFFFFFFFF
None

Definition at line 2654 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Destination burst transfer.

Reference Manual to LL API cross reference:
CTCR DBURST LL_MDMA_GetDestinationBurstSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DEST_BURST_SINGLE
  • LL_MDMA_DEST_BURST_2BEATS
  • LL_MDMA_DEST_BURST_4BEATS
  • LL_MDMA_DEST_BURST_8BEATS
  • LL_MDMA_DEST_BURST_16BEATS
  • LL_MDMA_DEST_BURST_32BEATS
  • LL_MDMA_DEST_BURST_64BEATS
  • LL_MDMA_DEST_BURST_128BEATS
None

Definition at line 1674 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Destination Data Size.

Reference Manual to LL API cross reference:
CTCR DSIZE LL_MDMA_GetDestinationDataSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DEST_DATA_SIZE_BYTE
  • LL_MDMA_DEST_DATA_SIZE_HALFWORD
  • LL_MDMA_DEST_DATA_SIZE_WORD
  • LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
None

Definition at line 1962 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Destination Increment Mode.

Reference Manual to LL API cross reference:
CTCR DINC LL_MDMA_GetDestinationIncMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DEST_FIXED
  • LL_MDMA_DEST_INCREMENT
  • LL_MDMA_DEST_DECREMENT
None

Definition at line 2100 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Destination Increment Offset Size.

Reference Manual to LL API cross reference:
CTCR DINCOS LL_MDMA_GetDestinationIncSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DEST_INC_OFFSET_BYTE
  • LL_MDMA_DEST_INC_OFFSET_HALFWORD
  • LL_MDMA_DEST_INC_OFFSET_WORD
  • LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
None

Definition at line 1822 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Half Words Endianess.

Reference Manual to LL API cross reference:
CCR HEX LL_MDMA_GetHalfWordEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE
  • LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
None

Definition at line 951 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Transfer hardware trigger (Request).

Reference Manual to LL API cross reference:
CTBR TSEL LL_MDMA_GetHWTrigger
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_REQ_DMA1_STREAM0_TC
  • LL_MDMA_REQ_DMA1_STREAM1_TC
  • LL_MDMA_REQ_DMA1_STREAM2_TC
  • LL_MDMA_REQ_DMA1_STREAM3_TC
  • LL_MDMA_REQ_DMA1_STREAM4_TC
  • LL_MDMA_REQ_DMA1_STREAM5_TC
  • LL_MDMA_REQ_DMA1_STREAM6_TC
  • LL_MDMA_REQ_DMA1_STREAM7_TC
  • LL_MDMA_REQ_DMA2_STREAM0_TC
  • LL_MDMA_REQ_DMA2_STREAM1_TC
  • LL_MDMA_REQ_DMA2_STREAM2_TC
  • LL_MDMA_REQ_DMA2_STREAM3_TC
  • LL_MDMA_REQ_DMA2_STREAM4_TC
  • LL_MDMA_REQ_DMA2_STREAM5_TC
  • LL_MDMA_REQ_DMA2_STREAM6_TC
  • LL_MDMA_REQ_DMA2_STREAM7_TC
  • LL_MDMA_REQ_LTDC_LINE_IT (*)
  • LL_MDMA_REQ_JPEG_INFIFO_TH (*)
  • LL_MDMA_REQ_JPEG_INFIFO_NF (*)
  • LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)
  • LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)
  • LL_MDMA_REQ_JPEG_END_CONVERSION (*)
  • LL_MDMA_REQ_QUADSPI_FIFO_TH (*)
  • LL_MDMA_REQ_QUADSPI_TC (*)
  • LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)
  • LL_MDMA_REQ_OCTOSPI1_TC (*)
  • LL_MDMA_REQ_DMA2D_CLUT_TC
  • LL_MDMA_REQ_DMA2D_TC
  • LL_MDMA_REQ_DMA2D_TW
  • LL_MDMA_REQ_DSI_TEARING_EFFECT (*)
  • LL_MDMA_REQ_DSI_END_REFRESH (*)
  • LL_MDMA_REQ_SDMMC1_END_DATA
  • LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)
  • LL_MDMA_REQ_SDMMC1_COMMAND_END (*)
  • LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)
  • LL_MDMA_REQ_OCTOSPI2_TC (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 3180 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get transfer Link Address.

Reference Manual to LL API cross reference:
CLAR LAR LL_MDMA_GetLinkAddress
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0xFFFFFFFF
None

Definition at line 2876 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Mask Address.

Reference Manual to LL API cross reference:
CMAR MAR LL_MDMA_GetMaskAddress
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0xFFFFFFFF
None

Definition at line 3242 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetMaskData | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Mask Data.

Reference Manual to LL API cross reference:
CMDR MDR LL_MDMA_GetMaskData
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0xFFFFFFFF
None

Definition at line 3304 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Padding Alignment.

Reference Manual to LL API cross reference:
CTCR PAM LL_MDMA_GetPaddingAlignment
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_DATAALIGN_RIGHT
  • LL_MDMA_DATAALIGN_RIGHT_SIGNED
  • LL_MDMA_DATAALIGN_LEFT
None

Definition at line 1442 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Request Mode.

Reference Manual to LL API cross reference:
CTCR SWRM LL_MDMA_GetRequestMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_REQUEST_MODE_HW
  • LL_MDMA_REQUEST_MODE_SW
None

Definition at line 1304 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get transfer Source address.

Reference Manual to LL API cross reference:
CSAR SAR LL_MDMA_GetSourceAddress
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0xFFFFFFFF
None

Definition at line 2592 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Source burst transfer.

Reference Manual to LL API cross reference:
CTCR SBURST LL_MDMA_GetSourceBurstSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_SRC_BURST_SINGLE
  • LL_MDMA_SRC_BURST_2BEATS
  • LL_MDMA_SRC_BURST_4BEATS
  • LL_MDMA_SRC_BURST_8BEATS
  • LL_MDMA_SRC_BURST_16BEATS
  • LL_MDMA_SRC_BURST_32BEATS
  • LL_MDMA_SRC_BURST_64BEATS
  • LL_MDMA_SRC_BURST_128BEATS
None

Definition at line 1752 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Source Data Size.

Reference Manual to LL API cross reference:
CTCR SSIZE LL_MDMA_GetSourceDataSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_SRC_DATA_SIZE_BYTE
  • LL_MDMA_SRC_DATA_SIZE_HALFWORD
  • LL_MDMA_SRC_DATA_SIZE_WORD
  • LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
None

Definition at line 2032 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Source Increment Mode.

Reference Manual to LL API cross reference:
CTCR SINC LL_MDMA_GetSourceIncMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_SRC_FIXED
  • LL_MDMA_SRC_INCREMENT
  • LL_MDMA_SRC_DECREMENT
None

Definition at line 2168 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Source Increment Offset Size.

Reference Manual to LL API cross reference:
CTCR SINCOS LL_MDMA_GetSourceIncSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_SRC_INC_OFFSET_BYTE
  • LL_MDMA_SRC_INC_OFFSET_HALFWORD
  • LL_MDMA_SRC_INC_OFFSET_WORD
  • LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
None

Definition at line 1892 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Source Bus Selection.

Reference Manual to LL API cross reference:
CTBR SBUS LL_MDMA_GetSrcBusSelection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_SRC_BUS_SYSTEM_AXI
  • LL_MDMA_SRC_BUS_AHB_TCM
None

Definition at line 3044 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Trigger Mode.

Reference Manual to LL API cross reference:
CTCR TRGM LL_MDMA_GetTriggerMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_BUFFER_TRANSFER
  • LL_MDMA_BLOCK_TRANSFER
  • LL_MDMA_REPEAT_BLOCK_TRANSFER
  • LL_MDMA_FULL_TRANSFER
None

Definition at line 1374 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Words Endianess.

Reference Manual to LL API cross reference:
CCR WEX LL_MDMA_GetWordEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_WORD_ENDIANNESS_PRESERVE
  • LL_MDMA_WORD_ENDIANNESS_EXCHANGE
None

Definition at line 885 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Transfer Error Direction.

Reference Manual to LL API cross reference:
CESR TED LL_MDMA_GetXferErrorDirection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_MDMA_READ_ERROR
  • LL_MDMA_WRITE_ERROR
None

Definition at line 3337 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Transfer Error LSB Address.

Reference Manual to LL API cross reference:
CESR TEA LL_MDMA_GetXferErrorLSBAddress
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
Between 0 to 0x0000007F
None

Definition at line 3368 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Bufferable Write Mode is enabled or disabled.

Reference Manual to LL API cross reference:
CTCR BWM LL_MDMA_IsEnabledBufferableWrMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1238 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_MDMA_IsEnabledChannel
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 752 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if packing is enabled or disabled.

Reference Manual to LL API cross reference:
CTCR PKE LL_MDMA_IsEnabledPacking
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1533 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkDataLength | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | BlkDataLength
 | ) |  |

Set Block Number of data bytes to transfer.

Reference Manual to LL API cross reference:
CBNDTR BNDT LL_MDMA_SetBlkDataLength
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
BlkDataLength | Between 0 to 0x00010000
Return values:
None

Definition at line 2234 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | BlockRepeatCount
 | ) |  |

Set Block Repeat Count.

Reference Manual to LL API cross reference:
CBNDTR BRC LL_MDMA_SetBlkRepeatCount
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
BlockRepeatCount | Between 0 to 0x00000FFF
Return values:
None

Definition at line 2296 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestAdrUpdateMode
 | ) |  |

Set Block Repeat Destination address Update Mode.

Reference Manual to LL API cross reference:
CBNDTR BRDUM LL_MDMA_SetBlkRepeatDestAddrUpdate
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestAdrUpdateMode This parameter can be one of the following values:
  • LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT
  • LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
Return values:
None

Definition at line 2397 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAdrUpdateMode
 | ) |  |

Set Block Repeat Source address Update Mode.

Reference Manual to LL API cross reference:
CBNDTR BRSUM LL_MDMA_SetBlkRepeatSrcAddrUpdate
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcAdrUpdateMode This parameter can be one of the following values:
  • LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT
  • LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
Return values:
None

Definition at line 2463 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestAdrUpdateValue
 | ) |  |

Set transfer Destination address Update Value.

Reference Manual to LL API cross reference:
CBRUR DUV LL_MDMA_SetBlkRptDestAddrUpdateValue
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestAdrUpdateValue | Between 0 to 0x0000FFFF
Return values:
None

Definition at line 2720 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAdrUpdateValue
 | ) |  |

Set transfer Source address Update Value.

Reference Manual to LL API cross reference:
CBRUR SUV LL_MDMA_SetBlkRptSrcAddrUpdateValue
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcAdrUpdateValue | Between 0 to 0x0000FFFF
Return values:
None

Definition at line 2783 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetBufferTransferLength | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Length
 | ) |  |

Set Buffer Transfer Length.

Reference Manual to LL API cross reference:
CTCR TLEN LL_MDMA_SetBufferTransferLength
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Length | Between 0 to 0x0000007F
Return values:
None

Definition at line 1564 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetByteEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Endianness
 | ) |  |

Set Bytes Endianess.

Reference Manual to LL API cross reference:
CCR BEX LL_MDMA_SetByteEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Endianness This parameter can be one of the following values:
  • LL_MDMA_BYTE_ENDIANNESS_PRESERVE
  • LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
Return values:
None

Definition at line 984 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_MDMA_SetChannelPriorityLevel
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Priority This parameter can be one of the following values:
  • LL_MDMA_PRIORITY_LOW
  • LL_MDMA_PRIORITY_MEDIUM
  • LL_MDMA_PRIORITY_HIGH
  • LL_MDMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 1052 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetDestBusSelection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestBus
 | ) |  |

Set Destination Bus Selection.

Reference Manual to LL API cross reference:
CTBR DBUS LL_MDMA_SetDestBusSelection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestBus This parameter can be one of the following values:
  • LL_MDMA_DEST_BUS_SYSTEM_AXI
  • LL_MDMA_DEST_BUS_AHB_TCM
Return values:
None

Definition at line 2945 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetDestinationAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestAddress
 | ) |  |

Set transfer Destination address.

Reference Manual to LL API cross reference:
CDAR DAR LL_MDMA_SetDestinationAddress
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 2623 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Dburst
 | ) |  |

Set Destination burst transfer.

Reference Manual to LL API cross reference:
CTCR DBURST LL_MDMA_SetDestinationBurstSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Dburst This parameter can be one of the following values:
  • LL_MDMA_DEST_BURST_SINGLE
  • LL_MDMA_DEST_BURST_2BEATS
  • LL_MDMA_DEST_BURST_4BEATS
  • LL_MDMA_DEST_BURST_8BEATS
  • LL_MDMA_DEST_BURST_16BEATS
  • LL_MDMA_DEST_BURST_32BEATS
  • LL_MDMA_DEST_BURST_64BEATS
  • LL_MDMA_DEST_BURST_128BEATS
Return values:
None

Definition at line 1635 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetDestinationDataSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestDataSize
 | ) |  |

Set Destination Data Size.

Reference Manual to LL API cross reference:
CTCR DSIZE LL_MDMA_SetDestinationDataSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestDataSize This parameter can be one of the following values:
  • LL_MDMA_DEST_DATA_SIZE_BYTE
  • LL_MDMA_DEST_DATA_SIZE_HALFWORD
  • LL_MDMA_DEST_DATA_SIZE_WORD
  • LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
Return values:
None

Definition at line 1927 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetDestinationIncMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | DestIncMode
 | ) |  |

Set Destination Increment Mode.

Reference Manual to LL API cross reference:
CTCR DINC LL_MDMA_SetDestinationIncMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
DestIncMode This parameter can be one of the following values:
  • LL_MDMA_DEST_FIXED
  • LL_MDMA_DEST_INCREMENT
  • LL_MDMA_DEST_DECREMENT
Return values:
None

Definition at line 2066 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetDestinationIncSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | IncSize
 | ) |  |

Set Destination Increment Offset Size.

Reference Manual to LL API cross reference:
CTCR DINCOS LL_MDMA_SetDestinationIncSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
IncSize This parameter can be one of the following values:
  • LL_MDMA_DEST_INC_OFFSET_BYTE
  • LL_MDMA_DEST_INC_OFFSET_HALFWORD
  • LL_MDMA_DEST_INC_OFFSET_WORD
  • LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
Return values:
None

Definition at line 1787 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Endianness
 | ) |  |

Set Half Words Endianess.

Reference Manual to LL API cross reference:
CCR HEX LL_MDMA_SetHalfWordEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Endianness This parameter can be one of the following values:
  • LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE
  • LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
Return values:
None

Definition at line 918 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetHWTrigger | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | HWRequest
 | ) |  |

Set Transfer hardware trigger (Request).

Reference Manual to LL API cross reference:
CTBR TSEL LL_MDMA_SetHWTrigger
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
HWRequest This parameter can be one of the following values:
  • LL_MDMA_REQ_DMA1_STREAM0_TC
  • LL_MDMA_REQ_DMA1_STREAM1_TC
  • LL_MDMA_REQ_DMA1_STREAM2_TC
  • LL_MDMA_REQ_DMA1_STREAM3_TC
  • LL_MDMA_REQ_DMA1_STREAM4_TC
  • LL_MDMA_REQ_DMA1_STREAM5_TC
  • LL_MDMA_REQ_DMA1_STREAM6_TC
  • LL_MDMA_REQ_DMA1_STREAM7_TC
  • LL_MDMA_REQ_DMA2_STREAM0_TC
  • LL_MDMA_REQ_DMA2_STREAM1_TC
  • LL_MDMA_REQ_DMA2_STREAM2_TC
  • LL_MDMA_REQ_DMA2_STREAM3_TC
  • LL_MDMA_REQ_DMA2_STREAM4_TC
  • LL_MDMA_REQ_DMA2_STREAM5_TC
  • LL_MDMA_REQ_DMA2_STREAM6_TC
  • LL_MDMA_REQ_DMA2_STREAM7_TC
  • LL_MDMA_REQ_LTDC_LINE_IT (*)
  • LL_MDMA_REQ_JPEG_INFIFO_TH (*)
  • LL_MDMA_REQ_JPEG_INFIFO_NF (*)
  • LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)
  • LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)
  • LL_MDMA_REQ_JPEG_END_CONVERSION (*)
  • LL_MDMA_REQ_QUADSPI_FIFO_TH (*)
  • LL_MDMA_REQ_QUADSPI_TC (*)
  • LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)
  • LL_MDMA_REQ_OCTOSPI1_TC (*)
  • LL_MDMA_REQ_DMA2D_CLUT_TC
  • LL_MDMA_REQ_DMA2D_TC
  • LL_MDMA_REQ_DMA2D_TW
  • LL_MDMA_REQ_DSI_TEARING_EFFECT (*)
  • LL_MDMA_REQ_DSI_END_REFRESH (*)
  • LL_MDMA_REQ_SDMMC1_END_DATA
  • LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)
  • LL_MDMA_REQ_SDMMC1_COMMAND_END (*)
  • LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)
  • LL_MDMA_REQ_OCTOSPI2_TC (*)
Note:
(*) Availability depends on devices.
Return values:
None

Definition at line 3112 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetLinkAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | LinkAddress
 | ) |  |

Set transfer Link Address.

Reference Manual to LL API cross reference:
CLAR LAR LL_MDMA_SetLinkAddress
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
LinkAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 2845 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetMaskAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MaskAddress
 | ) |  |

Set Mask Address.

Reference Manual to LL API cross reference:
CMAR MAR LL_MDMA_SetMaskAddress
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
MaskAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 3211 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetMaskData | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MaskData
 | ) |  |

Set Mask Data.

Reference Manual to LL API cross reference:
CMDR MDR LL_MDMA_SetMaskData
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
MaskData | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 3273 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetPaddingAlignment | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PaddingAlignment
 | ) |  |

Set Padding Alignment.

Reference Manual to LL API cross reference:
CTCR PAM LL_MDMA_SetPaddingAlignment
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
PaddingAlignment This parameter can be one of the following values:
  • LL_MDMA_DATAALIGN_RIGHT
  • LL_MDMA_DATAALIGN_RIGHT_SIGNED
  • LL_MDMA_DATAALIGN_LEFT
Return values:
None

Definition at line 1408 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetRequestMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | RequestMode
 | ) |  |

Set Request Mode.

Reference Manual to LL API cross reference:
CTCR SWRM LL_MDMA_SetRequestMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
RequestMode This parameter can be one of the following values:
  • LL_MDMA_REQUEST_MODE_HW
  • LL_MDMA_REQUEST_MODE_SW
Return values:
None

Definition at line 1271 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetSourceAddress | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress
 | ) |  |

Set transfer Source address.

Reference Manual to LL API cross reference:
CSAR SAR LL_MDMA_SetSourceAddress
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcAddress | Between 0 to 0xFFFFFFFF
Return values:
None

Definition at line 2561 of file stm32h7xx_ll_mdma.h.

Referenced by LL_MDMA_Init().

__STATIC_INLINE void LL_MDMA_SetSourceBurstSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Sburst
 | ) |  |

Set Source burst transfer.

Reference Manual to LL API cross reference:
CTCR SBURST LL_MDMA_SetSourceBurstSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Sburst This parameter can be one of the following values:
  • LL_MDMA_SRC_BURST_SINGLE
  • LL_MDMA_SRC_BURST_2BEATS
  • LL_MDMA_SRC_BURST_4BEATS
  • LL_MDMA_SRC_BURST_8BEATS
  • LL_MDMA_SRC_BURST_16BEATS
  • LL_MDMA_SRC_BURST_32BEATS
  • LL_MDMA_SRC_BURST_64BEATS
  • LL_MDMA_SRC_BURST_128BEATS
Return values:
None

Definition at line 1713 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetSourceDataSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcDataSize
 | ) |  |

Set Source Data Size.

Reference Manual to LL API cross reference:
CTCR SSIZE LL_MDMA_SetSourceDataSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcDataSize This parameter can be one of the following values:
  • LL_MDMA_SRC_DATA_SIZE_BYTE
  • LL_MDMA_SRC_DATA_SIZE_HALFWORD
  • LL_MDMA_SRC_DATA_SIZE_WORD
  • LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
Return values:
None

Definition at line 1997 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetSourceIncMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcIncMode
 | ) |  |

Set Source Increment Mode.

Reference Manual to LL API cross reference:
CTCR SINC LL_MDMA_SetSourceIncMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcIncMode This parameter can be one of the following values:
  • LL_MDMA_SRC_FIXED
  • LL_MDMA_SRC_INCREMENT
  • LL_MDMA_SRC_DECREMENT
Return values:
None

Definition at line 2134 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetSourceIncSize | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | IncSize
 | ) |  |

Set Source Increment Offset Size.

Reference Manual to LL API cross reference:
CTCR SINCOS LL_MDMA_SetSourceIncSize
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
IncSize This parameter can be one of the following values:
  • LL_MDMA_SRC_INC_OFFSET_BYTE
  • LL_MDMA_SRC_INC_OFFSET_HALFWORD
  • LL_MDMA_SRC_INC_OFFSET_WORD
  • LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
Return values:
None

Definition at line 1857 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetSrcBusSelection | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcBus
 | ) |  |

Set Source Bus Selection.

Reference Manual to LL API cross reference:
CTBR SBUS LL_MDMA_SetSrcBusSelection
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
SrcBus This parameter can be one of the following values:
  • LL_MDMA_SRC_BUS_SYSTEM_AXI
  • LL_MDMA_SRC_BUS_AHB_TCM
Return values:
None

Definition at line 3011 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetTriggerMode | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | TriggerMode
 | ) |  |

Set Trigger Mode.

Reference Manual to LL API cross reference:
CTCR TRGM LL_MDMA_SetTriggerMode
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
TriggerMode This parameter can be one of the following values:
  • LL_MDMA_BUFFER_TRANSFER
  • LL_MDMA_BLOCK_TRANSFER
  • LL_MDMA_REPEAT_BLOCK_TRANSFER
  • LL_MDMA_FULL_TRANSFER
Return values:
None

Definition at line 1339 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_SetWordEndianness | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Endianness
 | ) |  |

Set Words Endianess.

Reference Manual to LL API cross reference:
CCR WEX LL_MDMA_SetWordEndianness
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Endianness This parameter can be one of the following values:
  • LL_MDMA_WORD_ENDIANNESS_PRESERVE
  • LL_MDMA_WORD_ENDIANNESS_EXCHANGE
Return values:
None

Definition at line 852 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
MDMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_GI (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Global Interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Channel Transfer Complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Repeat Transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x buffer transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_CRQA (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x ReQuest Active flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BSE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Size Error flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_ASE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Address/Size Error flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TEMD (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error Mask Data flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TELD (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error Link Data flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Transfer Error interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Channel Transfer Complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Block Repeat Transfer complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Block Transfer complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x buffer transfer Complete Interrupt Flag.

Function Documentation

__STATIC_INLINE void LL_MDMA_ClearFlag_BRT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Clear MDMA Channel x Block Repeat Transfer complete interrupt flag.

Reference Manual to LL API cross reference:
CIFCR CBRTIF LL_MDMA_ClearFlag_BRT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3794 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_ClearFlag_BT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Clear MDMA Channel x Block Transfer complete interrupt flag.

Reference Manual to LL API cross reference:
CIFCR CBTIF LL_MDMA_ClearFlag_BT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3824 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_ClearFlag_CTC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Clear MDMA Channel x Channel Transfer Complete interrupt flag.

Reference Manual to LL API cross reference:
CIFCR CCTCIF LL_MDMA_ClearFlag_CTC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3764 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_ClearFlag_TC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Clear MDMA Channel x buffer transfer Complete Interrupt Flag.

Reference Manual to LL API cross reference:
CIFCR CLTCIF LL_MDMA_ClearFlag_TC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3854 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_ClearFlag_TE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Clear MDMA Channel x Transfer Error interrupt flag.

Reference Manual to LL API cross reference:
CIFCR CTEIF LL_MDMA_ClearFlag_TE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3734 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Address/Size Error flag.

Reference Manual to LL API cross reference:
CESR ASE LL_MDMA_IsActiveFlag_ASE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3644 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Block Repeat Transfer complete interrupt flag.

Reference Manual to LL API cross reference:
CISR BRTIF LL_MDMA_IsActiveFlag_BRT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3494 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Block Size Error flag.

Reference Manual to LL API cross reference:
CESR BSE LL_MDMA_IsActiveFlag_BSE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3614 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Block Transfer complete interrupt flag.

Reference Manual to LL API cross reference:
CISR BTIF LL_MDMA_IsActiveFlag_BT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3524 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x ReQuest Active flag.

Reference Manual to LL API cross reference:
CISR CRQA LL_MDMA_IsActiveFlag_CRQA
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3584 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Channel Transfer Complete interrupt flag.

Reference Manual to LL API cross reference:
CISR CTCIF LL_MDMA_IsActiveFlag_CTC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3464 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Global Interrupt flag.

Reference Manual to LL API cross reference:
GISR0 GIFx LL_MDMA_IsActiveFlag_GI
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3406 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x buffer transfer complete interrupt flag.

Reference Manual to LL API cross reference:
CISR TCIF LL_MDMA_IsActiveFlag_TC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3554 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Transfer Error interrupt flag.

Reference Manual to LL API cross reference:
CISR TEIF LL_MDMA_IsActiveFlag_TE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3434 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Transfer Error Link Data flag.

Reference Manual to LL API cross reference:
CESR TELD LL_MDMA_IsActiveFlag_TELD
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3704 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Get MDMA Channel x Transfer Error Mask Data flag.

Reference Manual to LL API cross reference:
CESR TEMD LL_MDMA_IsActiveFlag_TEMD
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 3674 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
MDMA Exported Functions

Functions

__STATIC_INLINE void | LL_MDMA_EnableIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Transfer Error interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Channel Transfer Complete interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Block Repeat Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Block Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x buffer transfer complete interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Transfer Error interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Channel Transfer Complete interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Block Repeat Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Block Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x buffer transfer complete interrupt.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Transfer Error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Channel Transfer Complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Block Repeat Transfer complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Block Transfer interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x buffer transfer complete interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_MDMA_DisableIT_BRT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA Channel x Block Repeat Transfer interrupt.

Reference Manual to LL API cross reference:
CCR BRTIE LL_MDMA_DisableIT_BRT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4102 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_DisableIT_BT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA Channel x Block Transfer interrupt.

Reference Manual to LL API cross reference:
CCR BTIE LL_MDMA_DisableIT_BT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4132 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_DisableIT_CTC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA Channel x Channel Transfer Complete interrupt.

Reference Manual to LL API cross reference:
CCR CTCIE LL_MDMA_DisableIT_CTC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4072 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_DisableIT_TC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA Channel x buffer transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_MDMA_DisableIT_TC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4162 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_DisableIT_TE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable MDMA Channel x Transfer Error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_MDMA_DisableIT_TE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4042 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableIT_BRT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA Channel x Block Repeat Transfer interrupt.

Reference Manual to LL API cross reference:
CCR BRTIE LL_MDMA_EnableIT_BRT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3952 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableIT_BT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA Channel x Block Transfer interrupt.

Reference Manual to LL API cross reference:
CCR BTIE LL_MDMA_EnableIT_BT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3982 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableIT_CTC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA Channel x Channel Transfer Complete interrupt.

Reference Manual to LL API cross reference:
CCR CTCIE LL_MDMA_EnableIT_CTC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3922 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableIT_TC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA Channel x buffer transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_MDMA_EnableIT_TC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 4012 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE void LL_MDMA_EnableIT_TE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable MDMA Channel x Transfer Error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_MDMA_EnableIT_TE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
None

Definition at line 3892 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA Channel x Block Repeat Transfer complete interrupt is enabled.

Reference Manual to LL API cross reference:
CCR BRTIE LL_MDMA_IsEnabledIT_BRT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 4252 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA Channel x Block Transfer interrupt is enabled.

Reference Manual to LL API cross reference:
CCR BTIE LL_MDMA_IsEnabledIT_BT
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 4282 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA Channel x Channel Transfer Complete interrupt is enabled.

Reference Manual to LL API cross reference:
CCR CTCIE LL_MDMA_IsEnabledIT_CTC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 4222 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA Channel x buffer transfer complete interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_MDMA_IsEnabledIT_TC
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 4312 of file stm32h7xx_ll_mdma.h.

__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if MDMA Channel x Transfer Error interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_MDMA_IsEnabledIT_TE
Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 4192 of file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
MDMA Exported Functions

Functions

uint32_t | LL_MDMA_DeInit (MDMA_TypeDef *MDMAx, uint32_t Channel)
De-initialize the MDMA registers to their default reset values.
uint32_t | LL_MDMA_Init (MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
void | LL_MDMA_StructInit (LL_MDMA_InitTypeDef *MDMA_InitStruct)
Set each LL_MDMA_InitTypeDef field to default value.
void | LL_MDMA_CreateLinkNode (LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
Initializes MDMA linked list node according to the specified parameters in the MDMA_InitStruct.
void | LL_MDMA_ConnectLinkNode (LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
Connect Linked list Nodes.
void | LL_MDMA_DisconnectNextLinkNode (LL_MDMA_LinkNodeTypeDef *pLinkNode)
Disconnect the next linked list node.

Function Documentation

void LL_MDMA_ConnectLinkNode | ( | LL_MDMA_LinkNodeTypeDef * | pPrevLinkNode,
 |  | LL_MDMA_LinkNodeTypeDef * | pNewLinkNode
 | ) |  |

Connect Linked list Nodes.

Parameters:
pPrevLinkNode | Pointer to previous linked list node to be connected to new Lined list node.
pNewLinkNode | Pointer to new Linked list.
Return values:
None

Definition at line 747 of file stm32h7xx_ll_mdma.c.

References LL_MDMA_LinkNodeTypeDef::CLAR.

void LL_MDMA_CreateLinkNode | ( | LL_MDMA_InitTypeDef * | MDMA_InitStruct,
 |  | LL_MDMA_LinkNodeTypeDef * | pNode
 | ) |  |

Initializes MDMA linked list node according to the specified parameters in the MDMA_InitStruct.

Parameters:
MDMA_InitStruct | Pointer to a LL_MDMA_InitTypeDef structure that contains linked list node registers configurations.
pNode | Pointer to linked list node to fill according to MDMA_InitStruct parameters.
Return values:
None

Definition at line 612 of file stm32h7xx_ll_mdma.c.

References assert_param, LL_MDMA_InitTypeDef::BlockDataLength, LL_MDMA_InitTypeDef::BlockRepeatCount, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateVal, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateVal, LL_MDMA_InitTypeDef::BufferableWriteMode, LL_MDMA_InitTypeDef::BufferTransferLength, LL_MDMA_LinkNodeTypeDef::CBNDTR, LL_MDMA_LinkNodeTypeDef::CBRUR, LL_MDMA_LinkNodeTypeDef::CDAR, LL_MDMA_LinkNodeTypeDef::CLAR, LL_MDMA_LinkNodeTypeDef::CMAR, LL_MDMA_LinkNodeTypeDef::CMDR, LL_MDMA_LinkNodeTypeDef::CSAR, LL_MDMA_LinkNodeTypeDef::CTBR, LL_MDMA_LinkNodeTypeDef::CTCR, LL_MDMA_InitTypeDef::DestBurst, LL_MDMA_InitTypeDef::DestBus, LL_MDMA_InitTypeDef::DestDataSize, LL_MDMA_InitTypeDef::DestIncMode, LL_MDMA_InitTypeDef::DestIncSize, LL_MDMA_InitTypeDef::DstAddress, LL_MDMA_InitTypeDef::HWTrigger, IS_LL_MDMA_BLK_DATALENGTH, IS_LL_MDMA_BLK_REPEATCOUNT, IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE, IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL, IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE, IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL, IS_LL_MDMA_BUFFER_XFERLENGTH, IS_LL_MDMA_BUFFWRITEMODE, IS_LL_MDMA_DEST_BUS, IS_LL_MDMA_DESTBURST, IS_LL_MDMA_DESTDATASIZE, IS_LL_MDMA_DESTINCMODE, IS_LL_MDMA_DESTINCSIZE, IS_LL_MDMA_HWTRIGGER, IS_LL_MDMA_PACKMODE, IS_LL_MDMA_PADDINGALIGNEMENT, IS_LL_MDMA_REQUESTMODE, IS_LL_MDMA_SRC_BUS, IS_LL_MDMA_SRCDATASIZE, IS_LL_MDMA_SRCINCMODE, IS_LL_MDMA_SRCINCSIZE, IS_LL_MDMA_SRCTBURST, IS_LL_MDMA_TRIGGERMODE, LL_MDMA_InitTypeDef::LinkAddress, LL_MDMA_InitTypeDef::MaskAddress, LL_MDMA_InitTypeDef::MaskData, LL_MDMA_InitTypeDef::PackMode, LL_MDMA_InitTypeDef::PaddingAlignment, LL_MDMA_InitTypeDef::RequestMode, LL_MDMA_LinkNodeTypeDef::Reserved, LL_MDMA_InitTypeDef::SrcAddress, LL_MDMA_InitTypeDef::SrcBus, LL_MDMA_InitTypeDef::SrcDataSize, LL_MDMA_InitTypeDef::SrcIncMode, LL_MDMA_InitTypeDef::SrcIncSize, LL_MDMA_InitTypeDef::SrctBurst, and LL_MDMA_InitTypeDef::TriggerMode.

uint32_t LL_MDMA_DeInit | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the MDMA registers to their default reset values.

Parameters:
MDMAx MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
  • LL_MDMA_CHANNEL_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: MDMA registers are de-initialized
  • ERROR: Not applicable

Definition at line 332 of file stm32h7xx_ll_mdma.c.

References assert_param, IS_LL_MDMA_ALL_CHANNEL_INSTANCE, LL_AHB3_GRP1_ForceReset(), LL_AHB3_GRP1_PERIPH_MDMA, LL_AHB3_GRP1_ReleaseReset(), LL_MDMA_CHANNEL_ALL, LL_MDMA_DisableChannel(), LL_MDMA_GET_CHANNEL_INSTANCE, and LL_MDMA_WriteReg.

void LL_MDMA_DisconnectNextLinkNode ( LL_MDMA_LinkNodeTypeDef * pLinkNode )

Disconnect the next linked list node.

Parameters:
pLinkNode Pointer to linked list node to be disconnected from the next one.
Return values:
None

Definition at line 757 of file stm32h7xx_ll_mdma.c.

References LL_MDMA_LinkNodeTypeDef::CLAR.

uint32_t LL_MDMA_Init | ( | MDMA_TypeDef * | MDMAx,
 |  | uint32_t | Channel,
 |  | LL_MDMA_InitTypeDef * | MDMA_InitStruct
 | ) |  |

Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.

Note:
To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
  • LL_MDMA_GET_INSTANCE
  • LL_MDMA_GET_CHANNEL
Parameters:
MDMAx | MDMAx Instance
Channel This parameter can be one of the following values:
  • LL_MDMA_CHANNEL_0
  • LL_MDMA_CHANNEL_1
  • LL_MDMA_CHANNEL_2
  • LL_MDMA_CHANNEL_3
  • LL_MDMA_CHANNEL_4
  • LL_MDMA_CHANNEL_5
  • LL_MDMA_CHANNEL_6
  • LL_MDMA_CHANNEL_7
  • LL_MDMA_CHANNEL_8
  • LL_MDMA_CHANNEL_9
  • LL_MDMA_CHANNEL_10
  • LL_MDMA_CHANNEL_11
  • LL_MDMA_CHANNEL_12
  • LL_MDMA_CHANNEL_13
  • LL_MDMA_CHANNEL_14
  • LL_MDMA_CHANNEL_15
MDMA_InitStruct | pointer to a LL_MDMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: MDMA registers are initialized
  • ERROR: Not applicable

Definition at line 418 of file stm32h7xx_ll_mdma.c.

References assert_param, LL_MDMA_InitTypeDef::BlockDataLength, LL_MDMA_InitTypeDef::BlockRepeatCount, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateVal, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateVal, LL_MDMA_InitTypeDef::BufferableWriteMode, LL_MDMA_InitTypeDef::BufferTransferLength, LL_MDMA_InitTypeDef::ByteEndianess, LL_MDMA_InitTypeDef::DestBurst, LL_MDMA_InitTypeDef::DestBus, LL_MDMA_InitTypeDef::DestDataSize, LL_MDMA_InitTypeDef::DestIncMode, LL_MDMA_InitTypeDef::DestIncSize, LL_MDMA_InitTypeDef::DstAddress, LL_MDMA_InitTypeDef::HalfWordEndianess, LL_MDMA_InitTypeDef::HWTrigger, IS_LL_MDMA_ALL_CHANNEL_INSTANCE, IS_LL_MDMA_BLK_DATALENGTH, IS_LL_MDMA_BLK_REPEATCOUNT, IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE, IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL, IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE, IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL, IS_LL_MDMA_BUFFER_XFERLENGTH, IS_LL_MDMA_BUFFWRITEMODE, IS_LL_MDMA_BYTEENDIANESS, IS_LL_MDMA_DEST_BUS, IS_LL_MDMA_DESTBURST, IS_LL_MDMA_DESTDATASIZE, IS_LL_MDMA_DESTINCMODE, IS_LL_MDMA_DESTINCSIZE, IS_LL_MDMA_HALFWORDENDIANESS, IS_LL_MDMA_HWTRIGGER, IS_LL_MDMA_PACKMODE, IS_LL_MDMA_PADDINGALIGNEMENT, IS_LL_MDMA_PRIORITY, IS_LL_MDMA_REQUESTMODE, IS_LL_MDMA_SRC_BUS, IS_LL_MDMA_SRCDATASIZE, IS_LL_MDMA_SRCINCMODE, IS_LL_MDMA_SRCINCSIZE, IS_LL_MDMA_SRCTBURST, IS_LL_MDMA_TRIGGERMODE, IS_LL_MDMA_WORDENDIANESS, LL_MDMA_InitTypeDef::LinkAddress, LL_MDMA_ConfigBlkCounters(), LL_MDMA_ConfigBlkRepeatAddrUpdate(), LL_MDMA_ConfigBlkRptAddrUpdateValue(), LL_MDMA_ConfigBusSelection(), LL_MDMA_ConfigTransfer(), LL_MDMA_ConfigXferEndianness(), LL_MDMA_SetChannelPriorityLevel(), LL_MDMA_SetDestinationAddress(), LL_MDMA_SetHWTrigger(), LL_MDMA_SetLinkAddress(), LL_MDMA_SetMaskAddress(), LL_MDMA_SetMaskData(), LL_MDMA_SetSourceAddress(), LL_MDMA_InitTypeDef::MaskAddress, LL_MDMA_InitTypeDef::MaskData, LL_MDMA_InitTypeDef::PackMode, LL_MDMA_InitTypeDef::PaddingAlignment, LL_MDMA_InitTypeDef::Priority, LL_MDMA_InitTypeDef::RequestMode, LL_MDMA_InitTypeDef::SrcAddress, LL_MDMA_InitTypeDef::SrcBus, LL_MDMA_InitTypeDef::SrcDataSize, LL_MDMA_InitTypeDef::SrcIncMode, LL_MDMA_InitTypeDef::SrcIncSize, LL_MDMA_InitTypeDef::SrctBurst, LL_MDMA_InitTypeDef::TriggerMode, and LL_MDMA_InitTypeDef::WordEndianess.

void LL_MDMA_StructInit ( LL_MDMA_InitTypeDef * MDMA_InitStruct )

Set each LL_MDMA_InitTypeDef field to default value.

Parameters:
MDMA_InitStruct Pointer to a LL_MDMA_InitTypeDef structure.
Return values:
None

Definition at line 567 of file stm32h7xx_ll_mdma.c.

References LL_MDMA_InitTypeDef::BlockDataLength, LL_MDMA_InitTypeDef::BlockRepeatCount, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatDestAddrUpdateVal, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateMode, LL_MDMA_InitTypeDef::BlockRepeatSrcAddrUpdateVal, LL_MDMA_InitTypeDef::BufferableWriteMode, LL_MDMA_InitTypeDef::BufferTransferLength, LL_MDMA_InitTypeDef::ByteEndianess, LL_MDMA_InitTypeDef::DestBurst, LL_MDMA_InitTypeDef::DestBus, LL_MDMA_InitTypeDef::DestDataSize, LL_MDMA_InitTypeDef::DestIncMode, LL_MDMA_InitTypeDef::DestIncSize, LL_MDMA_InitTypeDef::DstAddress, LL_MDMA_InitTypeDef::HalfWordEndianess, LL_MDMA_InitTypeDef::HWTrigger, LL_MDMA_InitTypeDef::LinkAddress, LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT, LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT, LL_MDMA_BUFF_WRITE_DISABLE, LL_MDMA_BUFFER_TRANSFER, LL_MDMA_BYTE_ENDIANNESS_PRESERVE, LL_MDMA_DATAALIGN_RIGHT, LL_MDMA_DEST_BURST_SINGLE, LL_MDMA_DEST_BUS_SYSTEM_AXI, LL_MDMA_DEST_DATA_SIZE_BYTE, LL_MDMA_DEST_FIXED, LL_MDMA_DEST_INC_OFFSET_BYTE, LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE, LL_MDMA_PACK_DISABLE, LL_MDMA_PRIORITY_LOW, LL_MDMA_REQ_DMA1_STREAM0_TC, LL_MDMA_REQUEST_MODE_HW, LL_MDMA_SRC_BURST_SINGLE, LL_MDMA_SRC_BUS_SYSTEM_AXI, LL_MDMA_SRC_DATA_SIZE_BYTE, LL_MDMA_SRC_FIXED, LL_MDMA_SRC_INC_OFFSET_BYTE, LL_MDMA_WORD_ENDIANNESS_PRESERVE, LL_MDMA_InitTypeDef::MaskAddress, LL_MDMA_InitTypeDef::MaskData, LL_MDMA_InitTypeDef::PackMode, LL_MDMA_InitTypeDef::PaddingAlignment, LL_MDMA_InitTypeDef::Priority, LL_MDMA_InitTypeDef::RequestMode, LL_MDMA_InitTypeDef::SrcAddress, LL_MDMA_InitTypeDef::SrcBus, LL_MDMA_InitTypeDef::SrcDataSize, LL_MDMA_InitTypeDef::SrcIncMode, LL_MDMA_InitTypeDef::SrcIncSize, LL_MDMA_InitTypeDef::SrctBurst, LL_MDMA_InitTypeDef::TriggerMode, and LL_MDMA_InitTypeDef::WordEndianess.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MDMA_LL_Private_Macros

Defines
MDMA_LL_Private_Macros
MDMA

Defines

#define | IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)
#define | IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U)
#define | IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU)
#define | IS_LL_MDMA_WORDENDIANESS(__VALUE__)
#define | IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__)
#define | IS_LL_MDMA_BYTEENDIANESS(__VALUE__)
#define | IS_LL_MDMA_PRIORITY(__VALUE__)
#define | IS_LL_MDMA_BUFFWRITEMODE(__VALUE__)
#define | IS_LL_MDMA_REQUESTMODE(__VALUE__)
#define | IS_LL_MDMA_TRIGGERMODE(__VALUE__)
#define | IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__)
#define | IS_LL_MDMA_PACKMODE(__VALUE__)
#define | IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU)
#define | IS_LL_MDMA_DESTBURST(__VALUE__)
#define | IS_LL_MDMA_SRCTBURST(__VALUE__)
#define | IS_LL_MDMA_DESTINCSIZE(__VALUE__)
#define | IS_LL_MDMA_SRCINCSIZE(__VALUE__)
#define | IS_LL_MDMA_DESTDATASIZE(__VALUE__)
#define | IS_LL_MDMA_SRCDATASIZE(__VALUE__)
#define | IS_LL_MDMA_DESTINCMODE(__VALUE__)
#define | IS_LL_MDMA_SRCINCMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_MDMA_DEST_BUS(__VALUE__)
#define | IS_LL_MDMA_SRC_BUS(__VALUE__)
#define | IS_LL_MDMA_HWTRIGGER(__VALUE__)

Define Documentation

#define IS_LL_MDMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
(((INSTANCE) == MDMA) && \
                                                            (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
                                                             ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))

Definition at line 48 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_DeInit(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLK_DATALENGTH ( __VALUE__ ) ((__VALUE__) <= 0x00010000U)

Definition at line 67 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLK_REPEATCOUNT ( __VALUE__ ) ((__VALUE__) <= 0x00000FFFU)

Definition at line 69 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
                                                           ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))

Definition at line 151 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 158 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
                                                           ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))

Definition at line 155 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 160 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BUFFER_XFERLENGTH ( __VALUE__ ) ((__VALUE__) <= 0x0000007FU)

Definition at line 103 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BUFFWRITEMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
                                                           ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))

Definition at line 85 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_BYTEENDIANESS ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
                                                           ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))

Definition at line 77 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_Init().

#define IS_LL_MDMA_DEST_BUS ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))

Definition at line 162 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_DESTBURST ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))

Definition at line 105 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_DESTDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))

Definition at line 133 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_DESTINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DEST_FIXED) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_DECREMENT))

Definition at line 143 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_DESTINCSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
                                                           ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))

Definition at line 123 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_HALFWORDENDIANESS ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
                                                           ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))

Definition at line 74 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_Init().

#define IS_LL_MDMA_HWTRIGGER ( __VALUE__ )

Definition at line 258 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_PACKMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
                                                           ((__VALUE__) == LL_MDMA_PACK_ENABLE))

Definition at line 100 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_PADDINGALIGNEMENT ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT)        || \
                                                           ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
                                                           ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))

Definition at line 96 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_PRIORITY_LOW)    || \
                                                           ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
                                                           ((__VALUE__) == LL_MDMA_PRIORITY_HIGH)   || \
                                                           ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))

Definition at line 80 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_Init().

#define IS_LL_MDMA_REQUESTMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
                                                           ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))

Definition at line 88 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_SRC_BUS ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))

Definition at line 165 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_SRCDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))

Definition at line 138 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_SRCINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_SRC_FIXED) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_DECREMENT))

Definition at line 147 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_SRCINCSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE)     || \
                                                           ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD)     || \
                                                           ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))

Definition at line 128 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_SRCTBURST ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
                                                           ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))

Definition at line 114 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_TRIGGERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_BUFFER_TRANSFER)       || \
                                                           ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER)        || \
                                                           ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
                                                           ((__VALUE__) == LL_MDMA_FULL_TRANSFER))

Definition at line 91 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), and LL_MDMA_Init().

#define IS_LL_MDMA_WORDENDIANESS ( __VALUE__ )
Value:
(((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
                                                           ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))

Definition at line 71 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_Init().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

Defines

#define | OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U
#define | OPAMP_POWERMODE_HSOTR_REGOFFSET 0x00000001U
#define | OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_HSOTR_REGOFFSET)
#define | OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPAHSM)
#define | OPAMP_TRIMMING_SELECT_MASK 0x00030000U
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)

Define Documentation

#define OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPAHSM)

Definition at line 60 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_SetPowerMode().

#define OPAMP_POWERMODE_HSOTR_REGOFFSET 0x00000001U

Definition at line 56 of file stm32h7xx_ll_opamp.h.

#define OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U

Definition at line 55 of file stm32h7xx_ll_opamp.h.

#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_HSOTR_REGOFFSET)

Definition at line 57 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define OPAMP_TRIMMING_SELECT_MASK 0x00030000U

Definition at line 67 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_SetCalibrationSelection().

#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)

Definition at line 68 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __OPAMP_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Register address

Definition at line 88 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define IS_LL_OPAMP_FUNCTIONAL_MODE ( __FUNCTIONAL_MODE__ )
Value:
(   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0)                         \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_BIAS)                    \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_IO1_BIAS)                \
  )

Definition at line 55 of file stm32h7xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_INVERTING ( __INPUT_INVERTING__ )
Value:
(   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
  )

Definition at line 78 of file stm32h7xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_NONINVERTING ( __INPUT_NONINVERTING__ )
Value:
(   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC2)              \
  )

Definition at line 65 of file stm32h7xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
   || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_HIGHSPEED))

Definition at line 51 of file stm32h7xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

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STM32H7B3xQ HAL User Manual: LL_OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_OPAMP_InitTypeDef Struct Reference
OPAMP Exported Init structure

Structure definition of some features of OPAMP instance. More...

#include <stm32h7xx_ll_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | FunctionalMode
uint32_t | InputNonInverting
uint32_t | InputInverting

Detailed Description

Structure definition of some features of OPAMP instance.

Definition at line 107 of file stm32h7xx_ll_opamp.h.

Field Documentation

uint32_t LL_OPAMP_InitTypeDef::FunctionalMode

Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ... This parameter can be a value of OPAMP functional mode

Note:
If OPAMP is configured in mode PGA, the gain can be configured using function LL_OPAMP_SetPGAGain().

This feature can be modified afterwards using unitary function LL_OPAMP_SetFunctionalMode().

Definition at line 115 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputInverting

Set OPAMP inverting input connection. This parameter can be a value of OPAMP input inverting

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputInverting().

Definition at line 126 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputNonInverting

Set OPAMP input non-inverting connection. This parameter can be a value of OPAMP input non-inverting

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputNonInverting().

Definition at line 121 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::PowerMode

Set OPAMP power mode. This parameter can be a value of OPAMP PowerMode

This feature can be modified afterwards using unitary function LL_OPAMP_SetPowerMode().

Definition at line 109 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_opamp.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP mode calibration or functional.

Defines
OPAMP mode calibration or functional.
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_FUNCTIONAL 0x00000000U
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)

Define Documentation

#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)

OPAMP calibration mode

Definition at line 148 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_MODE_FUNCTIONAL 0x00000000U

OPAMP functional mode

Definition at line 147 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP functional mode

Defines
OPAMP functional mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_STANDALONE 0x00000000U
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)

Define Documentation

#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

OPAMP functional mode, OPAMP operation in follower

Definition at line 157 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)

OPAMP functional mode, OPAMP operation in PGA

Definition at line 158 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0 for filtering

Definition at line 159 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain

Definition at line 160 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain And VINM1 is connected too for filtering

Definition at line 163 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_MODE_STANDALONE 0x00000000U

OPAMP functional mode, OPAMP operation in standalone

Definition at line 156 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)

Defines
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP Exported Constants

Defines

#define | LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U
#define | LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)

Detailed Description

Note:
Gain sign:
  • is positive if the OPAMP functional mode configuration is LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0
  • may be positive or negative if the OPAMP functional mode configuration is LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS see OPAMP functional mode for more details

Define Documentation

#define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 16 or -15

Definition at line 184 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U

OPAMP PGA gain 2 or -1

Definition at line 181 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 4 or -3

Definition at line 182 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )

OPAMP PGA gain 8 or -7

Definition at line 183 of file stm32h7xx_ll_opamp.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OPAMP input non-inverting

Defines
OPAMP input non-inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U
#define | LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_DAC2 OPAMP_CSR_VPSEL_1

Define Documentation

#define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL_0

OPAMP non inverting input connected internally to DAC channel (DAC1_CH1 for OPAMP1, DAC1_CH2 for OPAMP2) Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 195 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_DAC2 OPAMP_CSR_VPSEL_1

OPAMP non inverting input connected internally to DAC2 channel (DAC3 only for OPAMP2)

Definition at line 199 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U

OPAMP non inverting input connected to I/O VINP0 (PB0 for OPAMP1, PE9 for OPAMP2) Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 192 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

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STM32H7B3xQ HAL User Manual: OPAMP input inverting

Defines
OPAMP input inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_INVERT_IO0 0x00000000U
#define | LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1

Detailed Description

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

Define Documentation

#define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1

OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA.

Definition at line 218 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U

OPAMP inverting input connected to I/O VINM0 (PC5 for OPAMP1, PE8 for OPAMP2) Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 212 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0

OPAMP inverting input connected to I/0 VINM1 (PA7 for OPAMP1, PG1 for OPAMP2) Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 215 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)
#define | LL_OPAMP_POWERMODE_HIGHSPEED (OPAMP_POWERMODE_HSOTR_REGOFFSET | OPAMP_CSR_OPAHSM)

Define Documentation

#define LL_OPAMP_POWERMODE_HIGHSPEED (OPAMP_POWERMODE_HSOTR_REGOFFSET | OPAMP_CSR_OPAHSM)

OPAMP output in highspeed mode

Definition at line 230 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)

OPAMP output in normal mode

Definition at line 229 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

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STM32H7B3xQ HAL User Manual: OPAMP trimming mode

Defines
OPAMP trimming mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_FACTORY 0x00000000U
#define | LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

Define Documentation

#define LL_OPAMP_TRIMMING_FACTORY 0x00000000U

OPAMP trimming factors set to factory values

Definition at line 238 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

OPAMP trimming factors set to user values

Definition at line 239 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: OPAMP trimming of transistors differential pair NMOS or PMOS

Defines
OPAMP trimming of transistors differential pair NMOS or PMOS
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_OTR_TRIMOFFSETN | ((OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) << 4))
#define | LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_OTR_TRIMOFFSETN | (OPAMP_CSR_CALSEL_1 << 4))
#define | LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_OTR_TRIMOFFSETP | (OPAMP_CSR_CALSEL_0 << 4))
#define | LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_OTR_TRIMOFFSETP )
#define | LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)
#define | LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)

Define Documentation

#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 251 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_OTR_TRIMOFFSETN | (OPAMP_CSR_CALSEL_1 << 4))

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda).

Definition at line 248 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_OTR_TRIMOFFSETN | ((OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) << 4))

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 247 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 252 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_OTR_TRIMOFFSETP | (OPAMP_CSR_CALSEL_0 << 4))

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 249 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_OTR_TRIMOFFSETP )

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda).

Definition at line 250 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: Definitions of OPAMP hardware constraints delays

Defines
Definitions of OPAMP hardware constraints delays
OPAMP Exported Constants

Defines

#define LL_OPAMP_DELAY_STARTUP_US (3U)

Detailed Description

Note:
Only OPAMP IP HW delays are defined in OPAMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_OPAMP_DELAY_STARTUP_US (3U)

Delay for OPAMP startup time

Definition at line 274 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
OPAMP Exported Macros

Defines

#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in OPAMP LL_OPAMP_GetPowerModeregister.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in OPAMP register.

Define Documentation

#define LL_OPAMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in OPAMP register.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 305 of file stm32h7xx_ll_opamp.h.

#define LL_OPAMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in OPAMP LL_OPAMP_GetPowerModeregister.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 297 of file stm32h7xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit().

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STM32H7B3xQ HAL User Manual: OPAMP helper macro

Defines
OPAMP helper macro
OPAMP Exported Macros

Defines

#define | __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON)
Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.
#define | __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()
Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Define Documentation

#define __LL_OPAMP_COMMON_INSTANCE ( __OPAMPx__ ) (OPAMP12_COMMON)

Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.

Note:
OPAMP common register instance can be used to set parameters common to several OPAMP instances. Refer to functions having argument "OPAMPxy_COMMON" as parameter.
Parameters:
__OPAMPx__ OPAMP instance
Return values:
OPAMP common instance

Definition at line 323 of file stm32h7xx_ll_opamp.h.

#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE ( )
Value:
(LL_OPAMP_IsEnabled(OPAMP1) |                                                \
   LL_OPAMP_IsEnabled(OPAMP2)  )

Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Note:
This check is required by functions with setting conditioned to OPAMP state: All OPAMP instances of the OPAMP common group must be disabled. Refer to functions having argument "OPAMPxy_COMMON" as parameter.
Return values:
0,: All OPAMP instances sharing the same OPAMP common instance are disabled. 1: At least one OPAMP instance sharing the same OPAMP common instance is enabled

Definition at line 340 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: Configuration of OPAMP hierarchical scope: OPAMP instance

Functions
Configuration of OPAMP hierarchical scope: OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.
__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode normal or highspeed.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode normal or highspeed.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP functional mode from setting of internal connections.

OPAMP operation in standalone, follower, ...

Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_GetFunctionalMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA
  • LL_OPAMP_MODE_PGA_IO0
  • LL_OPAMP_MODE_PGA_IO0_BIAS
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS

Definition at line 438 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_GetMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION

Definition at line 396 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain ( OPAMP_TypeDef * OPAMPx )

Get OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_GetPGAGain
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15

Definition at line 473 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP power mode normal or highspeed.

Note:
OPAMP highspeed mode allows output stage to have a better slew rate.
Reference Manual to LL API cross reference:
CSR OPAHSM LL_OPAMP_GetPowerMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_HIGHSPEED

Definition at line 502 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetFunctionalMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | FunctionalMode
 | ) |  |

Set OPAMP functional mode by setting internal connections.

OPAMP operation in standalone, follower, ...

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_SetFunctionalMode
Parameters:
OPAMPx OPAMP instance
FunctionalMode This parameter can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA
  • LL_OPAMP_MODE_PGA_IO0
  • LL_OPAMP_MODE_PGA_IO0_BIAS
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
Return values:
None

Definition at line 419 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | Mode
 | ) |  |

Set OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_SetMode
Parameters:
OPAMPx OPAMP instance
Mode This parameter can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION
Return values:
None

Definition at line 377 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPGAGain | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PGAGain
 | ) |  |

Set OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_SetPGAGain
Parameters:
OPAMPx OPAMP instance
PGAGain This parameter can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
Return values:
None

Definition at line 456 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPowerMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set OPAMP power mode normal or highspeed.

Note:
OPAMP highspeed mode allows output stage to have a better slew rate.
Reference Manual to LL API cross reference:
CSR OPAHSM LL_OPAMP_SetPowerMode
Parameters:
OPAMPx OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_HIGHSPEED
Return values:
None

Definition at line 488 of file stm32h7xx_ll_opamp.h.

References OPAMP_POWERMODE_CSR_BIT_MASK.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration of OPAMP inputs

Functions
Configuration of OPAMP inputs
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP inverting input connection.

Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_GetInputInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO

Definition at line 576 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_GetInputNonInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_DAC
  • LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)

Definition at line 540 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputInverting
 | ) |  |

Set OPAMP inverting input connection.

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_SetInputInverting
Parameters:
OPAMPx OPAMP instance
InputInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO
Return values:
None

Definition at line 559 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputNonInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputNonInverting
 | ) |  |

Set OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_SetInputNonInverting
Parameters:
OPAMPx OPAMP instance
InputNonInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_DAC
  • LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)
Return values:
None

Definition at line 526 of file stm32h7xx_ll_opamp.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration and operation of OPAMP trimming

Functions
Configuration and operation of OPAMP trimming
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection ( OPAMP_TypeDef * OPAMPx )

Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_GetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS (1)
  • LL_OPAMP_TRIMMING_PMOS (1)
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
(1) Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS)

Definition at line 662 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_GetTrimmingMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER

Definition at line 615 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
OTR TRIMOFFSETN LL_OPAMP_GetTrimmingValue
OTR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
HSOTR TRIMHSOFFSETN LL_OPAMP_GetTrimmingValue
HSOTR TRIMHSOFFSETP LL_OPAMP_GetTrimmingValue
Parameters:
OPAMPx OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_HIGHSPEED
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
Return values:
0x0...0x1F

Definition at line 732 of file stm32h7xx_ll_opamp.h.

References __OPAMP_PTR_REG_OFFSET, LL_OPAMP_TRIMMING_NMOS, OPAMP_POWERMODE_OTR_REGOFFSET_MASK, and OPAMP_TRIMMING_VALUE_MASK.

__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet ( OPAMP_TypeDef * OPAMPx )

Get OPAMP calibration result of toggling output.

Note:
This functions returns: 0 if OPAMP calibration output is reset 1 if OPAMP calibration output is set
Reference Manual to LL API cross reference:
CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 679 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_SetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS (1)
  • LL_OPAMP_TRIMMING_PMOS (1)
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
(1) Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS)
Return values:
None

Definition at line 638 of file stm32h7xx_ll_opamp.h.

References OPAMP_TRIMMING_SELECT_MASK.

__STATIC_INLINE void LL_OPAMP_SetTrimmingMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TrimmingMode
 | ) |  |

Set OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_SetTrimmingMode
Parameters:
OPAMPx OPAMP instance
TrimmingMode This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER
Return values:
None

Definition at line 602 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode,
 |  | uint32_t | TransistorsDiffPair,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
HSOTR TRIMHSOFFSETN LL_OPAMP_SetTrimmingValue
HSOTR TRIMHSOFFSETP LL_OPAMP_SetTrimmingValue
Parameters:
OPAMPx | OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_HIGHSPEED
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
TrimmingValue | 0x00...0x1F
Return values:
None

Definition at line 702 of file stm32h7xx_ll_opamp.h.

References __OPAMP_PTR_REG_OFFSET, LL_OPAMP_TRIMMING_NMOS, OPAMP_POWERMODE_OTR_REGOFFSET_MASK, and OPAMP_TRIMMING_VALUE_MASK.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation on OPAMP instance

Functions
Operation on OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)

Function Documentation

__STATIC_INLINE void LL_OPAMP_Disable ( OPAMP_TypeDef * OPAMPx )

Disable OPAMP instance.

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Disable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 771 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_Enable ( OPAMP_TypeDef * OPAMPx )

Enable OPAMP instance.

Note:
After enable from off state, OPAMP requires a delay to fullfill wake up time specification. Refer to device datasheet, parameter "tWAKEUP".
Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Enable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 760 of file stm32h7xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled ( OPAMP_TypeDef * OPAMPx )

Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_IsEnabled
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 783 of file stm32h7xx_ll_opamp.h.

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STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_OPAMP_DeInit ( OPAMP_TypeDef * OPAMPx )

De-initialize registers of the selected OPAMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
OPAMPx OPAMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are de-initialized
  • ERROR: OPAMP registers are not de-initialized

Definition at line 111 of file stm32h7xx_ll_opamp.c.

References assert_param, and LL_OPAMP_WriteReg.

ErrorStatus LL_OPAMP_Init | ( | OPAMP_TypeDef * | OPAMPx,
 |  | LL_OPAMP_InitTypeDef * | OPAMP_InitStruct
 | ) |  |

Initialize some features of OPAMP instance.

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
Parameters:
OPAMPx | OPAMP instance
OPAMP_InitStruct | Pointer to a LL_OPAMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are initialized
  • ERROR: OPAMP registers are not initialized

Definition at line 135 of file stm32h7xx_ll_opamp.c.

References assert_param, LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, IS_LL_OPAMP_FUNCTIONAL_MODE, IS_LL_OPAMP_INPUT_INVERTING, IS_LL_OPAMP_INPUT_NONINVERTING, IS_LL_OPAMP_POWER_MODE, LL_OPAMP_MODE_FOLLOWER, OPAMP_POWERMODE_CSR_BIT_MASK, and LL_OPAMP_InitTypeDef::PowerMode.

void LL_OPAMP_StructInit ( LL_OPAMP_InitTypeDef * OPAMP_InitStruct )

Set each LL_OPAMP_InitTypeDef field to default value.

Parameters:
OPAMP_InitStruct pointer to a LL_OPAMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 199 of file stm32h7xx_ll_opamp.c.

References LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, LL_OPAMP_INPUT_INVERT_CONNECT_NO, LL_OPAMP_INPUT_NONINVERT_IO0, LL_OPAMP_MODE_FOLLOWER, LL_OPAMP_POWERMODE_NORMAL, and LL_OPAMP_InitTypeDef::PowerMode.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Wake-Up Pins register offsets Defines

Defines
Wake-Up Pins register offsets Defines
PWR Private Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
#define | LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU

Definition at line 54 of file stm32h7xx_ll_pwr.h.

Referenced by LL_PWR_GetWakeUpPinPull(), LL_PWR_SetWakeUpPinPullDown(), LL_PWR_SetWakeUpPinPullNone(), and LL_PWR_SetWakeUpPinPullUp().

#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL

Definition at line 53 of file stm32h7xx_ll_pwr.h.

Referenced by LL_PWR_GetWakeUpPinPull(), LL_PWR_SetWakeUpPinPullDown(), LL_PWR_SetWakeUpPinPullNone(), and LL_PWR_SetWakeUpPinPullUp().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF
#define | LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6
#define | LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5
#define | LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4
#define | LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3
#define | LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2
#define | LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF

Clear flags for CPU

Definition at line 72 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1

Clear WKUP pin 1

Definition at line 81 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2

Clear WKUP pin 2

Definition at line 80 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3

Clear WKUP pin 3

Definition at line 79 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4

Clear WKUP pin 4

Definition at line 78 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5

Clear WKUP pin 5

Definition at line 77 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6

Clear WKUP pin 6

Definition at line 76 of file stm32h7xx_ll_pwr.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_FLAG_AVDO PWR_CSR1_AVDO
#define | LL_PWR_FLAG_PVDO PWR_CSR1_PVDO
#define | LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS
#define | LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY
#define | LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO
#define | LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH
#define | LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL
#define | LL_PWR_FLAG_VBATH PWR_CR2_VBATH
#define | LL_PWR_FLAG_VBATL PWR_CR2_VBATL
#define | LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY
#define | LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY
#define | LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY
#define | LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF
#define | LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF
#define | LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY
#define | LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6
#define | LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5
#define | LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4
#define | LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3
#define | LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2
#define | LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS

Current VOS applied for VCORE voltage scaling flag

Definition at line 92 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY

Ready bit for current actual used VOS for VCORE voltage scaling flag

Definition at line 93 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO

Analog voltage detector output on VDDA flag

Definition at line 90 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY

Backup Regulator ready flag

Definition at line 102 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF

System STANDBY Flag

Definition at line 113 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF

STOP Flag

Definition at line 114 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO

Voltage detector output on VDDMMC flag

Definition at line 95 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO

Programmable voltage detect output flag

Definition at line 91 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY

SMPS External supply ready flag

Definition at line 105 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH

Temperature high threshold flag

Definition at line 98 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL

Temperature low threshold flag

Definition at line 99 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY

USB supply ready flag

Definition at line 104 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH

VBAT high threshold flag

Definition at line 100 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL

VBAT low threshold flag

Definition at line 101 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY

Voltage scaling ready flag

Definition at line 130 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1

Wakeup Pin Flag 1

Definition at line 138 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2

Wakeup Pin Flag 2

Definition at line 137 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3

Wakeup Pin Flag 3

Definition at line 136 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4

Wakeup Pin Flag 4

Definition at line 135 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5

Wakeup Pin Flag 5

Definition at line 134 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6

Wakeup Pin Flag 6

Definition at line 133 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Power mode

Defines
Power mode
PWR Exported Constants

Defines

#define | LL_PWR_CPU_MODE_CDSTOP 0x00000000U
#define | LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD
#define | LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD
#define | LL_PWR_CPU_MODE_SRDSTOP 0x00000000U
#define | LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD

Define Documentation

#define LL_PWR_CPU_MODE_CDSTOP 0x00000000U

Enter CD domain to Stop mode when the CPU enters deepsleep

Definition at line 150 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD

Enter CD domain to Stop2 mode when the CPU enters deepsleep

Definition at line 151 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD

Keep system SRD domain in Run mode when the CPU enter deepsleep

Definition at line 164 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD

Enter SRD domain to Standby mode when the CPU enters deepsleep

Definition at line 166 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U

Enter SRD domain to Stop mode when the CPU enters deepsleep

Definition at line 165 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Run mode Regulator Voltage Scaling

Defines
Run mode Regulator Voltage Scaling
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U
#define | LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0
#define | LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1
#define | LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1)

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1)

Select voltage scale 0

Definition at line 194 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1

Select voltage scale 1

Definition at line 193 of file stm32h7xx_ll_pwr.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0

Select voltage scale 2

Definition at line 192 of file stm32h7xx_ll_pwr.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U

Select voltage scale 3

Definition at line 191 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Stop mode Regulator Voltage Scaling

Defines
Stop mode Regulator Voltage Scaling
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0
#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1
#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Select voltage scale 3 when system enters STOP mode

Definition at line 205 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1

Select voltage scale 4 when system enters STOP mode

Definition at line 204 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0

Select voltage scale 5 when system enters STOP mode

Definition at line 203 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Regulator Mode In Deep Sleep Mode

Defines
Regulator Mode In Deep Sleep Mode
PWR Exported Constants

Defines

#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS

Define Documentation

#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS

Voltage Regulator in low-power mode during deepsleep mode

Definition at line 214 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U

Voltage Regulator in main mode during deepsleep mode

Definition at line 213 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Power Digital Voltage Level Detector

Defines
Power Digital Voltage Level Detector
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7

Define Documentation

#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0

Voltage threshold detected by PVD 1.95 V

Definition at line 222 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1

Voltage threshold detected by PVD 2.1 V

Definition at line 223 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2

Voltage threshold detected by PVD 2.25 V

Definition at line 224 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3

Voltage threshold detected by PVD 2.4 V

Definition at line 225 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4

Voltage threshold detected by PVD 2.55 V

Definition at line 226 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5

Voltage threshold detected by PVD 2.7 V

Definition at line 227 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6

Voltage threshold detected by PVD 2.85 V

Definition at line 228 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7

External voltage level on PVD_IN pin, compared to internal VREFINT level.

Definition at line 229 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Power Analog Voltage Level Detector

Defines
Power Analog Voltage Level Detector
PWR Exported Constants

Defines

#define | LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Define Documentation

#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0

Analog Voltage threshold detected by AVD 1.7 V

Definition at line 237 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1

Analog Voltage threshold detected by AVD 2.1 V

Definition at line 238 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2

Analog Voltage threshold detected by AVD 2.5 V

Definition at line 239 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Analog Voltage threshold detected by AVD 2.8 V

Definition at line 240 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Battery Charge Resistor

Defines
Battery Charge Resistor
PWR Exported Constants

Defines

#define | LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS

Define Documentation

#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U

Charge the Battery through a 5 kO resistor

Definition at line 249 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS

Charge the Battery through a 1.5 kO resistor

Definition at line 250 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Wakeup Pins

Defines
Wakeup Pins
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
#define | LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define | LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#define | LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#define | LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#define | LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6

Define Documentation

#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1

Wake-Up pin 1 : PA0

Definition at line 258 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2

Wake-Up pin 2 : PA2

Definition at line 259 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3

Wake-Up pin 3 : PC1

Definition at line 260 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4

Wake-Up pin 4 : PC13

Definition at line 261 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5

Wake-Up pin 5 : PI8

Definition at line 262 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6

Wake-Up pin 6 : PI11

Definition at line 263 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Wakeup Pins pull configuration

Defines
Wakeup Pins pull configuration
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL
#define | LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL
#define | LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL

Define Documentation

#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL

Configure Wake-Up pin in no pull

Definition at line 271 of file stm32h7xx_ll_pwr.h.

Referenced by LL_PWR_SetWakeUpPinPullNone().

#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL

Configure Wake-Up pin in pull Down

Definition at line 273 of file stm32h7xx_ll_pwr.h.

Referenced by LL_PWR_SetWakeUpPinPullDown().

#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL

Configure Wake-Up pin in pull Up

Definition at line 272 of file stm32h7xx_ll_pwr.h.

Referenced by LL_PWR_SetWakeUpPinPullUp().

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STM32H7B3xQ HAL User Manual: Power supply source configuration

Defines
Power supply source configuration
PWR Exported Constants

Defines

#define | LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN
#define | LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN
#define | LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS

Define Documentation

#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN

Core domains are suppplied from the SMPS

Definition at line 283 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS

The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source

Definition at line 291 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN

Core domains are suppplied from the LDO

Definition at line 281 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)

The SMPS 1.8V output supplies an external source which supplies the Core domains

Definition at line 288 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO

Definition at line 286 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 1.8V output supplies the LDO which supplies the Core domains

Definition at line 284 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)

The SMPS 2.5V output supplies an external source which supplies the Core domains

Definition at line 289 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO

Definition at line 287 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)

The SMPS 2.5V output supplies the LDO which supplies the Core domains

Definition at line 285 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 321 of file stm32h7xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 314 of file stm32h7xx_ll_pwr.h.

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STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set the voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get the voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop Mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop Mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledFlashPowerDown (void)
Check if the Flash Power Down in Stop Mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAnalogBooster (void)
Enable the Analog Voltage Booster (VDDA)
__STATIC_INLINE void | LL_PWR_DisableAnalogBooster (void)
Disable the Analog Voltage Booster (VDDA)
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAnalogBooster (void)
Check if the Analog Voltage Booster (VDDA) is enabled.
__STATIC_INLINE void | LL_PWR_EnableAnalogVoltageReady (void)
Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready.
__STATIC_INLINE void | LL_PWR_DisableAnalogVoltageReady (void)
Disable the Analog Voltage Ready (VDDA)
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAnalogVoltageReady (void)
Check if the Analog Voltage Booster (VDDA) is enabled.
__STATIC_INLINE void | LL_PWR_SetStopModeRegulVoltageScaling (uint32_t VoltageScaling)
Set the internal Regulator output voltage in STOP mode.
__STATIC_INLINE uint32_t | LL_PWR_GetStopModeRegulVoltageScaling (void)
Get the internal Regulator output voltage in STOP mode.
__STATIC_INLINE void | LL_PWR_EnableAVD (void)
Enable Analog Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisableAVD (void)
Disable Analog Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAVD (void)
Check if Analog Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_SetAVDLevel (uint32_t AVDLevel)
Configure the voltage threshold to be detected by the Analog Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetAVDLevel (void)
Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM1ShutOff (void)
Enable the AXI RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM1ShutOff (void)
Disable the AXI RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM1ShutOff (void)
Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM2ShutOff (void)
Enable the AXI RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM2ShutOff (void)
Disable the AXI RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM2ShutOff (void)
Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM3ShutOff (void)
Enable the AXI RAM3 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM3ShutOff (void)
Disable the AXI RAM3 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM3ShutOff (void)
Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAHBRAM1ShutOff (void)
Enable the AHB RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAHBRAM1ShutOff (void)
Disable the AHB RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAHBRAM1ShutOff (void)
Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAHBRAM2ShutOff (void)
Enable the AHB RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAHBRAM2ShutOff (void)
Disable the AHB RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAHBRAM2ShutOff (void)
Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableITCMSOShutOff (void)
Enable the ITCM shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableITCMSOShutOff (void)
Disable the ITCM shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledITCMShutOff (void)
Check if the ITCM shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableHSITFShutOff (void)
Enable the USB and FDCAN shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableHSITFShutOff (void)
Disable the USB and FDCAN shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledHSITFShutOff (void)
Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRDRAMShutOff (void)
Enable the SRD AHB RAM shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableSRDRAMShutOff (void)
Disable the SRD AHB RAM shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRDRAMShutOff (void)
Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableBkUpRegulator (void)
Enable Backup Regulator.
__STATIC_INLINE void | LL_PWR_DisableBkUpRegulator (void)
Disable Backup Regulator.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpRegulator (void)
Check if the backup Regulator is enabled.
__STATIC_INLINE void | LL_PWR_EnableMonitoring (void)
Enable VBAT and Temperature monitoring.
__STATIC_INLINE void | LL_PWR_DisableMonitoring (void)
Disable VBAT and Temperature monitoring.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledMonitoring (void)
Check if the VBAT and Temperature monitoring is enabled.
__STATIC_INLINE void | LL_PWR_ConfigSupply (uint32_t SupplySource)
Configure the PWR supply.
__STATIC_INLINE uint32_t | LL_PWR_GetSupply (void)
Get the PWR supply.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the Battery charge resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the Battery charge resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableUSBReg (void)
Enable the USB regulator.
__STATIC_INLINE void | LL_PWR_DisableUSBReg (void)
Disable the USB regulator.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUSBReg (void)
Check if the USB regulator is enabled.
__STATIC_INLINE void | LL_PWR_EnableUSBVoltageDetector (void)
Enable the USB voltage detector.
__STATIC_INLINE void | LL_PWR_DisableUSBVoltageDetector (void)
Disable the USB voltage detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUSBVoltageDetector (void)
Check if the USB voltage detector is enabled.
__STATIC_INLINE void | LL_PWR_CPU_SetCDPowerMode (uint32_t PDMode)
Set the CPU domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_CPU_GetCDPowerMode (void)
Get the CD Domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_CPU_SetSRDPowerMode (uint32_t PDMode)
Set the SRD domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_CPU_GetD3PowerMode (void)
Get the D3 Domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_CPU_EnableSRDRunInLowPowerMode (void)
SRD domain remains in Run mode regardless of CPU subsystem modes.
__STATIC_INLINE void | LL_PWR_CPU_DisableSRDRunInLowPowerMode (void)
SRD domain follows CPU subsystem modes.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode (void)
Check if SRD is kept in Run mode when CPU enters low power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal Regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal Regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullNone (uint32_t WakeUpPin)
Set the Wake-Up pin Pull None.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullUp (uint32_t WakeUpPin)
Set the Wake-Up pin Pull Up.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullDown (uint32_t WakeUpPin)
Set the Wake-Up pin Pull Down.
__STATIC_INLINE uint32_t | LL_PWR_GetWakeUpPinPull (uint32_t WakeUpPin)
Get the Wake-Up pin pull.

Function Documentation

__STATIC_INLINE void LL_PWR_ConfigSupply ( uint32_t SupplySource )

Configure the PWR supply.

Reference Manual to LL API cross reference:
CR3 BYPASS LL_PWR_ConfigSupply
Reference Manual to LL API cross reference:
CR3 LDOEN LL_PWR_ConfigSupply
Reference Manual to LL API cross reference:
CR3 SMPSEN LL_PWR_ConfigSupply
Reference Manual to LL API cross reference:
CR3 SMPSEXTHP LL_PWR_ConfigSupply
Reference Manual to LL API cross reference:
CR3 SMPSLEVEL LL_PWR_ConfigSupply
Parameters:
SupplySource This parameter can be one of the following values:
  • LL_PWR_LDO_SUPPLY
  • LL_PWR_DIRECT_SMPS_SUPPLY
  • LL_PWR_SMPS_1V8_SUPPLIES_LDO
  • LL_PWR_SMPS_2V5_SUPPLIES_LDO
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT
  • LL_PWR_EXTERNAL_SOURCE_SUPPLY
Return values:
None

Definition at line 981 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode ( void )

SRD domain follows CPU subsystem modes.

Reference Manual to LL API cross reference:
CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode
Return values:
None

Definition at line 1496 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode ( void )

SRD domain remains in Run mode regardless of CPU subsystem modes.

Reference Manual to LL API cross reference:
CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode
Return values:
None

Definition at line 1462 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode ( void )

Get the CD Domain Power Down mode when the CPU enters deepsleep.

Reference Manual to LL API cross reference:
CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_CPU_MODE_CDSTOP
  • LL_PWR_CPU_MODE_CDSTOP2

Definition at line 1223 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode ( void )

Get the D3 Domain Power Down mode when the CPU enters deepsleep.

Reference Manual to LL API cross reference:
CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_CPU_MODE_D3STOP
  • LL_PWR_CPU_MODE_D3STANDBY

Definition at line 1352 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode ( void )

Check if SRD is kept in Run mode when CPU enters low power mode.

Reference Manual to LL API cross reference:
CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
Return values:
State of bit (1 or 0).

Definition at line 1530 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode ( uint32_t PDMode )

Set the CPU domain Power Down mode when the CPU enters deepsleep.

Reference Manual to LL API cross reference:
CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode
Parameters:
PDMode This parameter can be one of the following values:
  • LL_PWR_CPU_MODE_CDSTOP
  • LL_PWR_CPU_MODE_CDSTOP2
Return values:
None

Definition at line 1182 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode ( uint32_t PDMode )

Set the SRD domain Power Down mode when the CPU enters deepsleep.

Reference Manual to LL API cross reference:
CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode
Parameters:
PDMode This parameter can be one of the following values:
  • LL_PWR_CPU_MODE_SRDSTOP
  • LL_PWR_CPU_MODE_SRDSTANDBY
Return values:
None

Definition at line 1323 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff ( void )

Disable the AHB RAM1 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff
Return values:
None

Definition at line 752 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff ( void )

Disable the AHB RAM2 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff
Return values:
None

Definition at line 784 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAnalogBooster ( void )

Disable the Analog Voltage Booster (VDDA)

Reference Manual to LL API cross reference:
CR1 BOOSTE LL_PWR_DisableAnalogBooster
Return values:
None

Definition at line 506 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady ( void )

Disable the Analog Voltage Ready (VDDA)

Reference Manual to LL API cross reference:
CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady
Return values:
None

Definition at line 538 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAVD ( void )

Disable Analog Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 AVDEN LL_PWR_DisableAVD
Return values:
None

Definition at line 596 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff ( void )

Disable the AXI RAM1 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff
Return values:
None

Definition at line 656 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff ( void )

Disable the AXI RAM2 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff
Return values:
None

Definition at line 688 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff ( void )

Disable the AXI RAM3 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff
Return values:
None

Definition at line 720 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBatteryCharging ( void )

Disable battery charging.

Reference Manual to LL API cross reference:
CR3 VBE LL_PWR_DisableBatteryCharging
Return values:
None

Definition at line 1060 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 445 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpRegulator ( void )

Disable Backup Regulator.

Reference Manual to LL API cross reference:
CR2 BREN LL_PWR_DisableBkUpRegulator
Return values:
None

Definition at line 916 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableFlashPowerDown ( void )

Disable the Flash Power Down in Stop Mode.

Reference Manual to LL API cross reference:
CR1 FLPS LL_PWR_DisableFlashPowerDown
Return values:
None

Definition at line 475 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableHSITFShutOff ( void )

Disable the USB and FDCAN shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 HSITFSO LL_PWR_DisableHSITFShutOff
Return values:
None

Definition at line 848 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff ( void )

Disable the ITCM shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 ITCMSO LL_PWR_DisableITCMSOShutOff
Return values:
None

Definition at line 816 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableMonitoring ( void )

Disable VBAT and Temperature monitoring.

Reference Manual to LL API cross reference:
CR2 MONEN LL_PWR_DisableMonitoring
Return values:
None

Definition at line 946 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 PVDEN LL_PWR_DisablePVD
Return values:
None

Definition at line 378 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff ( void )

Disable the SRD AHB RAM shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff
Return values:
None

Definition at line 880 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableUSBReg ( void )

Disable the USB regulator.

Reference Manual to LL API cross reference:
CR3 USBREGEN LL_PWR_DisableUSBReg
Return values:
None

Definition at line 1115 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector ( void )

Disable the USB voltage detector.

Reference Manual to LL API cross reference:
CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
Return values:
None

Definition at line 1145 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin
WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin
WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin
WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin
WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin
WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1628 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff ( void )

Enable the AHB RAM1 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff
Return values:
None

Definition at line 742 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff ( void )

Enable the AHB RAM2 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff
Return values:
None

Definition at line 774 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAnalogBooster ( void )

Enable the Analog Voltage Booster (VDDA)

Reference Manual to LL API cross reference:
CR1 BOOSTE LL_PWR_EnableAnalogBooster
Return values:
None

Definition at line 496 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady ( void )

Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready.

Reference Manual to LL API cross reference:
CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady
Return values:
None

Definition at line 528 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAVD ( void )

Enable Analog Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 AVDEN LL_PWR_EnableAVD
Return values:
None

Definition at line 586 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff ( void )

Enable the AXI RAM1 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff
Return values:
None

Definition at line 646 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff ( void )

Enable the AXI RAM2 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff
Return values:
None

Definition at line 678 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff ( void )

Enable the AXI RAM3 shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff
Return values:
None

Definition at line 710 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBatteryCharging ( void )

Enable battery charging.

Reference Manual to LL API cross reference:
CR3 VBE LL_PWR_EnableBatteryCharging
Return values:
None

Definition at line 1050 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 435 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpRegulator ( void )

Enable Backup Regulator.

Reference Manual to LL API cross reference:
CR2 BREN LL_PWR_EnableBkUpRegulator
Note:
When set, the Backup Regulator (used to maintain backup SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the RAM will be maintained in the Standby and VBAT modes.
Return values:
None

Definition at line 906 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableFlashPowerDown ( void )

Enable the Flash Power Down in Stop Mode.

Reference Manual to LL API cross reference:
CR1 FLPS LL_PWR_EnableFlashPowerDown
Return values:
None

Definition at line 465 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableHSITFShutOff ( void )

Enable the USB and FDCAN shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 HSITFSO LL_PWR_EnableHSITFShutOff
Return values:
None

Definition at line 838 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff ( void )

Enable the ITCM shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 ITCMSO LL_PWR_EnableITCMSOShutOff
Return values:
None

Definition at line 806 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableMonitoring ( void )

Enable VBAT and Temperature monitoring.

Reference Manual to LL API cross reference:
CR2 MONEN LL_PWR_EnableMonitoring
Return values:
None

Definition at line 936 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 PVDEN LL_PWR_EnablePVD
Return values:
None

Definition at line 368 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff ( void )

Enable the SRD AHB RAM shut-off in DStop/DStop2 mode.

Reference Manual to LL API cross reference:
CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff
Return values:
None

Definition at line 870 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableUSBReg ( void )

Enable the USB regulator.

Reference Manual to LL API cross reference:
CR3 USBREGEN LL_PWR_EnableUSBReg
Return values:
None

Definition at line 1105 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector ( void )

Enable the USB voltage detector.

Reference Manual to LL API cross reference:
CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
Return values:
None

Definition at line 1135 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin
WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin
WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin
WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin
WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin
WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1606 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel ( void )

Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 ALS LL_PWR_GetAVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_AVDLEVEL_0
  • LL_PWR_AVDLEVEL_1
  • LL_PWR_AVDLEVEL_2
  • LL_PWR_AVDLEVEL_3

Definition at line 635 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor ( void )

Get the Battery charge resistor impedance.

Reference Manual to LL API cross reference:
CR3 VBRS LL_PWR_GetBattChargResistor
Return values:
Returned value can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K

Definition at line 1095 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR1 PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 425 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS ( void )

Get the voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR1 LPDS LL_PWR_GetRegulModeDS
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER

Definition at line 358 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling ( void )

Get the main internal Regulator output voltage.

Reference Manual to LL API cross reference:
D3CR VOS LL_PWR_GetRegulVoltageScaling
Note:
For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE0
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
  • LL_PWR_REGU_VOLTAGE_SCALE3

Definition at line 1580 of file stm32h7xx_ll_pwr.h.

Referenced by UTILS_CalculateFlashLatency().

__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling ( void )

Get the internal Regulator output voltage in STOP mode.

Reference Manual to LL API cross reference:
CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE5

Definition at line 576 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetSupply ( void )

Get the PWR supply.

Reference Manual to LL API cross reference:
CR3 BYPASS LL_PWR_GetSupply
Reference Manual to LL API cross reference:
CR3 LDOEN LL_PWR_GetSupply
Reference Manual to LL API cross reference:
CR3 SMPSEN LL_PWR_GetSupply
Reference Manual to LL API cross reference:
CR3 SMPSEXTHP LL_PWR_GetSupply
Reference Manual to LL API cross reference:
CR3 SMPSLEVEL LL_PWR_GetSupply
Return values:
Returned value can be one of the following values:
  • LL_PWR_LDO_SUPPLY
  • LL_PWR_DIRECT_SMPS_SUPPLY
  • LL_PWR_SMPS_1V8_SUPPLIES_LDO
  • LL_PWR_SMPS_2V5_SUPPLIES_LDO
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT
  • LL_PWR_EXTERNAL_SOURCE_SUPPLY

Definition at line 1023 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull ( uint32_t WakeUpPin )

Get the Wake-Up pin pull.

Reference Manual to LL API cross reference:
WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull
WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull
WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull
WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull
WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull
WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
Returned value can be one of the following values:
  • LL_PWR_WAKEUP_PIN_NOPULL
  • LL_PWR_WAKEUP_PIN_PULLUP
  • LL_PWR_WAKEUP_PIN_PULLDOWN

Definition at line 1813 of file stm32h7xx_ll_pwr.h.

References LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK, and LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff ( void )

Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
Return values:
State of bit (1 or 0).

Definition at line 762 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff ( void )

Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
Return values:
State of bit (1 or 0).

Definition at line 794 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster ( void )

Check if the Analog Voltage Booster (VDDA) is enabled.

Reference Manual to LL API cross reference:
CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster
Return values:
State of bit (1 or 0).

Definition at line 516 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady ( void )

Check if the Analog Voltage Booster (VDDA) is enabled.

Reference Manual to LL API cross reference:
CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
Return values:
State of bit (1 or 0).

Definition at line 548 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD ( void )

Check if Analog Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR1 AVDEN LL_PWR_IsEnabledAVD
Return values:
State of bit (1 or 0).

Definition at line 606 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff ( void )

Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff
Return values:
State of bit (1 or 0).

Definition at line 666 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff ( void )

Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff
Return values:
State of bit (1 or 0).

Definition at line 698 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff ( void )

Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff
Return values:
State of bit (1 or 0).

Definition at line 730 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging ( void )

Check if battery charging is enabled.

Reference Manual to LL API cross reference:
CR3 VBE LL_PWR_IsEnabledBatteryCharging
Return values:
State of bit (1 or 0).

Definition at line 1070 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 455 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator ( void )

Check if the backup Regulator is enabled.

Reference Manual to LL API cross reference:
CR2 BREN LL_PWR_IsEnabledBkUpRegulator
Return values:
State of bit (1 or 0).

Definition at line 926 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown ( void )

Check if the Flash Power Down in Stop Mode is enabled.

Reference Manual to LL API cross reference:
CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
Return values:
State of bit (1 or 0).

Definition at line 485 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff ( void )

Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff
Return values:
State of bit (1 or 0).

Definition at line 858 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff ( void )

Check if the ITCM shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff
Return values:
State of bit (1 or 0).

Definition at line 826 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring ( void )

Check if the VBAT and Temperature monitoring is enabled.

Reference Manual to LL API cross reference:
CR2 MONEN LL_PWR_IsEnabledMonitoring
Return values:
State of bit (1 or 0).

Definition at line 956 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR1 PVDEN LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 388 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff ( void )

Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled.

Reference Manual to LL API cross reference:
CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff
Return values:
State of bit (1 or 0).

Definition at line 890 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg ( void )

Check if the USB regulator is enabled.

Reference Manual to LL API cross reference:
CR3 USBREGEN LL_PWR_IsEnabledUSBReg
Return values:
State of bit (1 or 0).

Definition at line 1125 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector ( void )

Check if the USB voltage detector is enabled.

Reference Manual to LL API cross reference:
CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
Return values:
State of bit (1 or 0).

Definition at line 1155 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin
WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin
WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin
WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin
WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin
WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
State of bit (1 or 0).

Definition at line 1650 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Get the Wake-Up pin polarity for the event detection.

Reference Manual to LL API cross reference:
WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow
WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow
WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow
WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow
WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow
WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
State of bit (1 or 0).

Definition at line 1716 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetAVDLevel ( uint32_t AVDLevel )

Configure the voltage threshold to be detected by the Analog Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 ALS LL_PWR_SetAVDLevel
Parameters:
AVDLevel This parameter can be one of the following values:
  • LL_PWR_AVDLEVEL_0
  • LL_PWR_AVDLEVEL_1
  • LL_PWR_AVDLEVEL_2
  • LL_PWR_AVDLEVEL_3
Return values:
None

Definition at line 621 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBattChargResistor ( uint32_t Resistor )

Set the Battery charge resistor impedance.

Reference Manual to LL API cross reference:
CR3 VBRS LL_PWR_SetBattChargResistor
Parameters:
Resistor This parameter can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K
Return values:
None

Definition at line 1083 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR1 PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 407 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulModeDS ( uint32_t RegulMode )

Set the voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR1 LPDS LL_PWR_SetRegulModeDS
Parameters:
RegulMode This parameter can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER
Return values:
None

Definition at line 346 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling ( uint32_t VoltageScaling )

Set the main internal Regulator output voltage.

Reference Manual to LL API cross reference:
D3CR VOS LL_PWR_SetRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE0
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
  • LL_PWR_REGU_VOLTAGE_SCALE3
Note:
For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1.
Return values:
None

Definition at line 1560 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling ( uint32_t VoltageScaling )

Set the internal Regulator output voltage in STOP mode.

Reference Manual to LL API cross reference:
CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
Return values:
None

Definition at line 563 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity high for the event detection.

Reference Manual to LL API cross reference:
WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh
WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh
WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh
WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh
WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh
WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1694 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity low for the event detection.

Reference Manual to LL API cross reference:
WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow
WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow
WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow
WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow
WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow
WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1672 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown ( uint32_t WakeUpPin )

Set the Wake-Up pin Pull Down.

Reference Manual to LL API cross reference:
WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown
WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown
WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown
WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown
WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown
WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1786 of file stm32h7xx_ll_pwr.h.

References LL_PWR_WAKEUP_PIN_PULLDOWN, LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK, and LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone ( uint32_t WakeUpPin )

Set the Wake-Up pin Pull None.

Reference Manual to LL API cross reference:
WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone
WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone
WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone
WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone
WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone
WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1738 of file stm32h7xx_ll_pwr.h.

References LL_PWR_WAKEUP_PIN_NOPULL, LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK, and LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp ( uint32_t WakeUpPin )

Set the Wake-Up pin Pull Up.

Reference Manual to LL API cross reference:
WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp
WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp
WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp
WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp
WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp
WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
  • LL_PWR_WAKEUP_PIN6
Return values:
None

Definition at line 1762 of file stm32h7xx_ll_pwr.h.

References LL_PWR_WAKEUP_PIN_PULLUP, LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK, and LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: De-initialization function

Functions
De-initialization function
FLAG_Management | PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 56 of file stm32h7xx_ll_pwr.c.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Modules | Functions
FLAG_Management
PWR Exported Functions

Modules

De-initialization function

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_ACTVOS (void)
Indicate whether the voltage level is ready for current actual used VOS.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_AVDO (void)
Indicate whether VDDA voltage is below the selected AVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_MMCVDO (void)
Indicate whether VDDMMC voltage is below 1V2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BRR (void)
Get Backup Regulator ready Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VBATL (void)
Indicate whether the VBAT level is above or below low threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VBATH (void)
Indicate whether the VBAT level is above or below high threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_TEMPL (void)
Indicate whether the CPU temperature level is above or below low threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_TEMPH (void)
Indicate whether the CPU temperature level is above or below high threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SMPSEXT (void)
Indicate whether the SMPS external supply is ready or not.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_USB (void)
Indicate whether the USB supply is ready or not.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsActiveFlag_STOP (void)
Get CPU System Stop Flag.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsActiveFlag_SB (void)
Get CPU System Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU6 (void)
Get Wake-up Flag 6.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_CPU (void)
Clear CPU STANDBY, STOP and HOLD flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU6 (void)
Clear Wake-up Flag 6.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_CPU ( void )

Clear CPU STANDBY, STOP and HOLD flags.

Reference Manual to LL API cross reference:
CPUCR CSSF LL_PWR_ClearFlag_CPU
Return values:
None

Definition at line 2137 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU1 ( void )

Clear Wake-up Flag 1.

Reference Manual to LL API cross reference:
WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
Return values:
None

Definition at line 2209 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU2 ( void )

Clear Wake-up Flag 2.

Reference Manual to LL API cross reference:
WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
Return values:
None

Definition at line 2199 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU3 ( void )

Clear Wake-up Flag 3.

Reference Manual to LL API cross reference:
WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
Return values:
None

Definition at line 2189 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU4 ( void )

Clear Wake-up Flag 4.

Reference Manual to LL API cross reference:
WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
Return values:
None

Definition at line 2179 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU5 ( void )

Clear Wake-up Flag 5.

Reference Manual to LL API cross reference:
WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
Return values:
None

Definition at line 2169 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU6 ( void )

Clear Wake-up Flag 6.

Reference Manual to LL API cross reference:
WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
Return values:
None

Definition at line 2159 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB ( void )

Get CPU System Standby Flag.

Reference Manual to LL API cross reference:
CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 1991 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP ( void )

Get CPU System Stop Flag.

Reference Manual to LL API cross reference:
CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
Return values:
State of bit (1 or 0).

Definition at line 1969 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS ( void )

Indicate whether the voltage level is ready for current actual used VOS.

Reference Manual to LL API cross reference:
CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
Return values:
State of bit (1 or 0).

Definition at line 1843 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO ( void )

Indicate whether VDDA voltage is below the selected AVD threshold.

Reference Manual to LL API cross reference:
CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
Return values:
State of bit (1 or 0).

Definition at line 1853 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR ( void )

Get Backup Regulator ready Flag.

Reference Manual to LL API cross reference:
CR2 BRRDY LL_PWR_IsActiveFlag_BRR
Return values:
State of bit (1 or 0).

Definition at line 1875 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO ( void )

Indicate whether VDDMMC voltage is below 1V2.

Reference Manual to LL API cross reference:
CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO
Return values:
State of bit (1 or 0).

Definition at line 1864 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below the selected PVD threshold.

Reference Manual to LL API cross reference:
CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 1833 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT ( void )

Indicate whether the SMPS external supply is ready or not.

Reference Manual to LL API cross reference:
CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT
Return values:
State of bit (1 or 0).

Definition at line 1926 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH ( void )

Indicate whether the CPU temperature level is above or below high threshold.

Reference Manual to LL API cross reference:
CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
Return values:
State of bit (1 or 0).

Definition at line 1915 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL ( void )

Indicate whether the CPU temperature level is above or below low threshold.

Reference Manual to LL API cross reference:
CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
Return values:
State of bit (1 or 0).

Definition at line 1905 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB ( void )

Indicate whether the USB supply is ready or not.

Reference Manual to LL API cross reference:
CR3 USBRDY LL_PWR_IsActiveFlag_USB
Return values:
State of bit (1 or 0).

Definition at line 1937 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH ( void )

Indicate whether the VBAT level is above or below high threshold.

Reference Manual to LL API cross reference:
CR2 VBATH LL_PWR_IsActiveFlag_VBATH
Return values:
State of bit (1 or 0).

Definition at line 1895 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL ( void )

Indicate whether the VBAT level is above or below low threshold.

Reference Manual to LL API cross reference:
CR2 VBATL LL_PWR_IsActiveFlag_VBATL
Return values:
State of bit (1 or 0).

Definition at line 1885 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS ( void )

Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.

Reference Manual to LL API cross reference:
D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
Return values:
State of bit (1 or 0).

Definition at line 2063 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1 ( void )

Get Wake-up Flag 1.

Reference Manual to LL API cross reference:
WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
Return values:
State of bit (1 or 0).

Definition at line 2127 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2 ( void )

Get Wake-up Flag 2.

Reference Manual to LL API cross reference:
WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
Return values:
State of bit (1 or 0).

Definition at line 2117 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3 ( void )

Get Wake-up Flag 3.

Reference Manual to LL API cross reference:
WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
Return values:
State of bit (1 or 0).

Definition at line 2107 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4 ( void )

Get Wake-up Flag 4.

Reference Manual to LL API cross reference:
WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
Return values:
State of bit (1 or 0).

Definition at line 2097 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5 ( void )

Get Wake-up Flag 5.

Reference Manual to LL API cross reference:
WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
Return values:
State of bit (1 or 0).

Definition at line 2087 of file stm32h7xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6 ( void )

Get Wake-up Flag 6.

Reference Manual to LL API cross reference:
WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
Return values:
State of bit (1 or 0).

Definition at line 2077 of file stm32h7xx_ll_pwr.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_GetPCLK3ClockFreq (uint32_t HCLK_Frequency)
Return PCLK3 clock frequency.
uint32_t | RCC_GetPCLK4ClockFreq (uint32_t HCLK_Frequency)
Return PCLK4 clock frequency.

Function Documentation

uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 1704 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1715 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1726 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK3ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK3 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK3 clock frequency (in Hz)

Definition at line 1737 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_PCLK3_FREQ, and LL_RCC_GetAPB3Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetPCLK4ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK4 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK4 clock frequency (in Hz)

Definition at line 1748 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_PCLK4_FREQ, and LL_RCC_GetAPB4Prescaler().

Referenced by LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSPIClockFreq(), and LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetSystemClockFreq ( void )

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 1665 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSE_VALUE, HSI_VALUE, LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetSysClkSource(), LL_RCC_HSI_GetDivider(), LL_RCC_SYS_CLKSOURCE_STATUS_CSI, LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL1, and LL_PLL_ClocksTypeDef::PLL_P_Frequency.

Referenced by LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private Variables

Variables
RCC Private Variables
RCC

Variables

const uint8_t LL_RCC_PrescTable [16]

Variable Documentation

const uint8_t LL_RCC_PrescTable[16]

Definition at line 42 of file stm32h7xx_ll_rcc.c.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)

Define Documentation

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))

Definition at line 52 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_LPTIM_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
                                            || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))

Definition at line 55 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define IS_LL_RCC_SAI_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))

Definition at line 65 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetSAIClockFreq().

#define IS_LL_RCC_SPI_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))

Definition at line 70 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetSPIClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))

Definition at line 48 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32h7xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | CPUCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency
uint32_t | PCLK3_Frequency
uint32_t | PCLK4_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 119 of file stm32h7xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::CPUCLK_Frequency

Definition at line 122 of file stm32h7xx_ll_rcc.h.

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

Definition at line 123 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

Definition at line 124 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

Definition at line 125 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK3_Frequency

Definition at line 126 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK4_Frequency

Definition at line 127 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

Definition at line 121 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rcc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_PLL_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_PLL_ClocksTypeDef Struct Reference
RCC Exported Types

PLL Clocks Frequency Structure. More...

#include <stm32h7xx_ll_rcc.h>

Data Fields

uint32_t | PLL_P_Frequency
uint32_t | PLL_Q_Frequency
uint32_t | PLL_R_Frequency

Detailed Description

PLL Clocks Frequency Structure.

Definition at line 137 of file stm32h7xx_ll_rcc.h.

Field Documentation

uint32_t LL_PLL_ClocksTypeDef::PLL_P_Frequency

Definition at line 139 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSPIClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_PLL_ClocksTypeDef::PLL_Q_Frequency

Definition at line 140 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

uint32_t LL_PLL_ClocksTypeDef::PLL_R_Frequency

Definition at line 141 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetSPDIFClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rcc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Oscillator Values adaptation

Defines
Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines

#define HSI48_VALUE 48000000U

Detailed Description

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.

Define Documentation

#define HSI48_VALUE 48000000U

Value of the HSI48 oscillator in Hz

Definition at line 190 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSI oscillator divider

Defines
HSI oscillator divider
RCC Exported Constants

Defines

#define | LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
#define | LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
#define | LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
#define | LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8

Define Documentation

#define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1

Definition at line 200 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2

Definition at line 201 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4

Definition at line 202 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8

Definition at line 203 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
#define | LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)

Definition at line 214 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)

Definition at line 211 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)

Definition at line 213 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)

Definition at line 212 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI

Definition at line 223 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE

Definition at line 224 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI

Definition at line 222 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1

Definition at line 225 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI

CSI used as system clock

Definition at line 234 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 235 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 233 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1

PLL1 used as system clock

Definition at line 236 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System wakeup clock source

Defines
System wakeup clock source
RCC Exported Constants

Defines

#define | LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
#define | LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)

Define Documentation

#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)

Definition at line 245 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)

Definition at line 244 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Kernel wakeup clock source

Defines
Kernel wakeup clock source
RCC Exported Constants

Defines

#define | LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
#define | LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)

Define Documentation

#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)

Definition at line 254 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)

Definition at line 253 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System prescaler

Defines
System prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1

Definition at line 273 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128

Definition at line 279 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16

Definition at line 277 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2

Definition at line 274 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256

Definition at line 280 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4

Definition at line 275 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512

Definition at line 281 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64

Definition at line 278 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8

Definition at line 276 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1
#define | LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2
#define | LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4
#define | LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8
#define | LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16
#define | LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64
#define | LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128
#define | LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256
#define | LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512

Define Documentation

#define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1

Definition at line 301 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128

Definition at line 307 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16

Definition at line 305 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2

Definition at line 302 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256

Definition at line 308 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4

Definition at line 303 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512

Definition at line 309 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64

Definition at line 306 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8

Definition at line 304 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16

Define Documentation

#define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1

Definition at line 325 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16

Definition at line 329 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2

Definition at line 326 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4

Definition at line 327 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8

Definition at line 328 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB low-speed prescaler (APB2)

Defines
APB low-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16

Define Documentation

#define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1

Definition at line 345 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16

Definition at line 349 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2

Definition at line 346 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4

Definition at line 347 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8

Definition at line 348 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB low-speed prescaler (APB3)

Defines
APB low-speed prescaler (APB3)
RCC Exported Constants

Defines

#define | LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1
#define | LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2
#define | LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4
#define | LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8
#define | LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16

Define Documentation

#define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1

Definition at line 365 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16

Definition at line 369 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2

Definition at line 366 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4

Definition at line 367 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8

Definition at line 368 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: APB low-speed prescaler (APB4)

Defines
APB low-speed prescaler (APB4)
RCC Exported Constants

Defines

#define | LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1
#define | LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2
#define | LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4
#define | LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8
#define | LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16

Define Documentation

#define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1

Definition at line 385 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16

Definition at line 389 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2

Definition at line 386 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4

Definition at line 387 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8

Definition at line 388 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MCO source selection

Defines
MCO source selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
#define | LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
#define | LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
#define | LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
#define | LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
#define | LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
#define | LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
#define | LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
#define | LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
#define | LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
#define | LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)

Definition at line 400 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)

Definition at line 398 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)

Definition at line 402 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)

Definition at line 399 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)

Definition at line 401 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)

Definition at line 407 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)

Definition at line 405 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)

Definition at line 408 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)

Definition at line 406 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)

Definition at line 404 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)

Definition at line 403 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MCO prescaler

Defines
MCO prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
#define | LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
#define | LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
#define | LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)

Define Documentation

#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)

Definition at line 416 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 425 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 426 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 427 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 428 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 429 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)

Definition at line 430 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)

Definition at line 417 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

Definition at line 418 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)

Definition at line 419 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

Definition at line 420 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 421 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 422 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)

Definition at line 423 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

Definition at line 424 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)

Definition at line 431 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

Definition at line 440 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

Definition at line 441 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

Definition at line 442 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

Definition at line 443 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

Definition at line 444 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)

Definition at line 445 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)

Definition at line 432 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)

Definition at line 433 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)

Definition at line 434 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)

Definition at line 435 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

Definition at line 436 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

Definition at line 437 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)

Definition at line 438 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)

Definition at line 439 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSE prescaler for RTC clock

Defines
HSE prescaler for RTC clock
RCC Exported Constants

Defines

#define | LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
#define | LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
#define | LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
#define | LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
#define | LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Define Documentation

#define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

Definition at line 463 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 464 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

Definition at line 465 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 466 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 467 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 468 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)

Definition at line 469 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

Definition at line 470 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

Definition at line 471 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 472 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)

Definition at line 455 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

Definition at line 473 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 474 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 475 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 476 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

Definition at line 477 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

Definition at line 478 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

Definition at line 479 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 480 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

Definition at line 481 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 482 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 456 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 483 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 484 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)

Definition at line 485 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)

Definition at line 486 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)

Definition at line 487 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 488 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)

Definition at line 489 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 490 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 491 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 492 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)

Definition at line 457 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)

Definition at line 493 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

Definition at line 494 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

Definition at line 495 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 496 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

Definition at line 497 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 498 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 499 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 500 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)

Definition at line 501 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

Definition at line 502 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 458 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

Definition at line 503 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 504 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

Definition at line 505 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 506 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 507 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 508 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

Definition at line 509 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

Definition at line 510 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

Definition at line 511 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 512 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 459 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

Definition at line 513 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

Definition at line 514 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

Definition at line 515 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 516 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

Definition at line 460 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)

Definition at line 461 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

Definition at line 462 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)

Definition at line 454 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral USART clock source selection

Defines
Peripheral USART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
#define | LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
#define | LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
#define | LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
#define | LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
#define | LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
#define | LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
#define | LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
#define | LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
#define | LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
#define | LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
#define | LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
#define | LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
#define | LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
#define | LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
#define | LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
#define | LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
#define | LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
#define | LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
#define | LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
#define | LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

Define Documentation

#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE

Definition at line 1021 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)

Definition at line 536 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

Definition at line 535 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

Definition at line 537 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

Definition at line 532 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)

Definition at line 533 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)

Definition at line 534 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

Definition at line 1019 of file stm32h7xx_ll_rcc.h.

Referenced by LL_USART_Init().

#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI

Definition at line 543 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI

Definition at line 542 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE

Definition at line 544 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2

Definition at line 539 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q

Definition at line 540 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q

Definition at line 541 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

Definition at line 1026 of file stm32h7xx_ll_rcc.h.

Referenced by LL_USART_Init().

#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)

Definition at line 558 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

Definition at line 557 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

Definition at line 559 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

Definition at line 554 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)

Definition at line 555 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)

Definition at line 556 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral LPUART clock source selection

Defines
Peripheral LPUART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
#define | LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)
#define | LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)
#define | LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
#define | LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL

Definition at line 1038 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPUART_Init().

#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)

Definition at line 580 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

Definition at line 579 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)

Definition at line 581 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)

Definition at line 576 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)

Definition at line 577 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)

Definition at line 578 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral I2C clock source selection

Defines
Peripheral I2C clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
#define | LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
#define | LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
#define | LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)
#define | LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)
#define | LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
#define | LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)

Define Documentation

#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

Definition at line 1050 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

Definition at line 599 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)

Definition at line 598 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

Definition at line 596 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)

Definition at line 597 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)

Definition at line 1055 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

Definition at line 610 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)

Definition at line 609 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)

Definition at line 607 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)

Definition at line 608 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral LPTIM clock source selection

Defines
Peripheral LPTIM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)
#define | LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)
#define | LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)
#define | LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)
#define | LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
#define | LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
#define | LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
#define | LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
#define | LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
#define | LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
#define | LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4
#define | LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P
#define | LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R
#define | LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE
#define | LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI
#define | LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP
#define | LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)

Definition at line 1067 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

Definition at line 632 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

Definition at line 630 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)

Definition at line 631 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)

Definition at line 627 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)

Definition at line 628 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)

Definition at line 629 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)

Definition at line 1072 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

Definition at line 647 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

Definition at line 645 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)

Definition at line 646 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)

Definition at line 642 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)

Definition at line 643 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)

Definition at line 644 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)

Definition at line 1077 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

Definition at line 662 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

Definition at line 660 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)

Definition at line 661 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)

Definition at line 657 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)

Definition at line 658 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)

Definition at line 659 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */

Definition at line 1078 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP

Definition at line 669 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE

Definition at line 667 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI

Definition at line 668 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4

Definition at line 664 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P

Definition at line 665 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R

Definition at line 666 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral SAI clock source selection

Defines
Peripheral SAI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
#define | LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)
#define | LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)
#define | LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
#define | LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)
#define | LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
#define | LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)
#define | LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)
#define | LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
#define | LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)
#define | LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
#define | LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)

Definition at line 1090 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)

Definition at line 689 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

Definition at line 688 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)

Definition at line 685 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)

Definition at line 686 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)

Definition at line 687 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)

Definition at line 1096 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)

Definition at line 703 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

Definition at line 702 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)

Definition at line 699 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)

Definition at line 700 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)

Definition at line 701 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

Definition at line 704 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)

Definition at line 1099 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)

Definition at line 711 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

Definition at line 710 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)

Definition at line 707 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)

Definition at line 708 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)

Definition at line 709 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

Definition at line 712 of file stm32h7xx_ll_rcc.h.

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STM32H7B3xQ HAL User Manual: Peripheral SDMMC clock source selection

Defines
Peripheral SDMMC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
#define | LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)
#define | LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL

Define Documentation

#define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL

Definition at line 1117 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)

Definition at line 739 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)

Definition at line 740 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral RNG clock source selection

Defines
Peripheral RNG clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
#define | LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)
#define | LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)
#define | LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
#define | LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL

Definition at line 1129 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)

Definition at line 755 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)

Definition at line 757 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)

Definition at line 758 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)

Definition at line 756 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
#define | LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)
#define | LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)
#define | LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
#define | LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL

Define Documentation

#define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL

Definition at line 1141 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)

Definition at line 773 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)

Definition at line 776 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)

Definition at line 774 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)

Definition at line 775 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral CEC clock source selection

Defines
Peripheral CEC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
#define | LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)
#define | LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)
#define | LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL

Define Documentation

#define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL

Definition at line 1153 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)

Definition at line 792 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)

Definition at line 790 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)

Definition at line 791 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral DFSDM clock source selection

Defines
Peripheral DFSDM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
#define | LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)
#define | LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL

Define Documentation

#define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL

Definition at line 1175 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)

Definition at line 816 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)

Definition at line 817 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral DFSDM2 clock source selection

Defines
Peripheral DFSDM2 clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)
#define | LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)
#define | LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL

Define Documentation

#define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL

Definition at line 1185 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)

Definition at line 827 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDM2ClockFreq().

#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)

Definition at line 828 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDM2ClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral FMC clock source selection

Defines
Peripheral FMC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
#define | LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)
#define | LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)
#define | LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
#define | LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL

Define Documentation

#define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL

Definition at line 1198 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)

Definition at line 846 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFMCClockFreq().

#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)

Definition at line 843 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFMCClockFreq().

#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)

Definition at line 844 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFMCClockFreq().

#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)

Definition at line 845 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFMCClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral OSPI clock source selection

Defines
Peripheral OSPI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
#define | LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
#define | LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
#define | LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
#define | LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL

Define Documentation

#define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL

Definition at line 1218 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)

Definition at line 873 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetOSPIClockFreq().

#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)

Definition at line 870 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetOSPIClockFreq().

#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)

Definition at line 871 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetOSPIClockFreq().

#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)

Definition at line 872 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetOSPIClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral CLKP clock source selection

Defines
Peripheral CLKP clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
#define | LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)
#define | LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)
#define | LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL

Define Documentation

#define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL

Definition at line 1230 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetSPIClockFreq().

#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)

Definition at line 889 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCLKPClockFreq().

#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)

Definition at line 890 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCLKPClockFreq().

#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)

Definition at line 888 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCLKPClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral SPI clock source selection

Defines
Peripheral SPI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
#define | LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
#define | LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
#define | LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
#define | LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)
#define | LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)
#define | LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
#define | LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)
#define | LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)
#define | LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)
#define | LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
#define | LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)

Define Documentation

#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

Definition at line 1242 of file stm32h7xx_ll_rcc.h.

Referenced by LL_I2S_Init().

#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)

Definition at line 910 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

Definition at line 909 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

Definition at line 906 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)

Definition at line 907 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)

Definition at line 908 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)

Definition at line 1247 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)

Definition at line 924 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

Definition at line 925 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

Definition at line 923 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)

Definition at line 920 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)

Definition at line 921 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)

Definition at line 922 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)

Definition at line 1252 of file stm32h7xx_ll_rcc.h.

Referenced by LL_I2S_Init().

#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)

Definition at line 939 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

Definition at line 940 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

Definition at line 938 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

Definition at line 941 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)

Definition at line 935 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)

Definition at line 936 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)

Definition at line 937 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPIClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral SPDIF clock source selection

Defines
Peripheral SPDIF clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
#define | LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)
#define | LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)
#define | LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
#define | LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL

Define Documentation

#define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL

Definition at line 1264 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)

Definition at line 959 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPDIFClockFreq().

#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)

Definition at line 956 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPDIFClockFreq().

#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)

Definition at line 957 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPDIFClockFreq().

#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)

Definition at line 958 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPDIFClockFreq().

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STM32H7B3xQ HAL User Manual: Peripheral FDCAN clock source selection

Defines
Peripheral FDCAN clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
#define | LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)
#define | LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)
#define | LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL

Define Documentation

#define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL

Definition at line 1277 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)

Definition at line 974 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)

Definition at line 975 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)

Definition at line 976 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral SWP clock source selection

Defines
Peripheral SWP clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
#define | LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)
#define | LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL

Define Documentation

#define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL

Definition at line 1290 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)

Definition at line 991 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPClockFreq().

#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)

Definition at line 990 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
#define | LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)
#define | LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)
#define | LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL

Definition at line 1302 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)

Definition at line 1007 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)

Definition at line 1005 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)

Definition at line 1006 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
#define | LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
#define | LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
#define | LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)

Definition at line 1314 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)

Definition at line 1312 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)

Definition at line 1313 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)

Definition at line 1311 of file stm32h7xx_ll_rcc.h.

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STM32H7B3xQ HAL User Manual: Timers clocks prescalers selection

Defines
Timers clocks prescalers selection
RCC Exported Constants

Defines

#define | LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
#define | LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)

Define Documentation

#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)

Definition at line 1323 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)

Definition at line 1322 of file stm32h7xx_ll_rcc.h.

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STM32H7B3xQ HAL User Manual: All PLLs entry clock source

Defines
All PLLs entry clock source
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
#define | LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE

Define Documentation

#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI

Definition at line 1343 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), and LL_RCC_GetPLL3ClockFreq().

#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE

Definition at line 1344 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), and LL_RCC_GetPLL3ClockFreq().

#define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI

Definition at line 1342 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), and LL_RCC_GetPLL3ClockFreq().

#define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE

Definition at line 1345 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), and LL_RCC_GetPLL3ClockFreq().

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STM32H7B3xQ HAL User Manual: All PLLs input range

Defines
All PLLs input range
RCC Exported Constants

Defines

#define | LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
#define | LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
#define | LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
#define | LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)

Define Documentation

#define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)

Definition at line 1353 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)

Definition at line 1354 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)

Definition at line 1355 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)

Definition at line 1356 of file stm32h7xx_ll_rcc.h.

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STM32H7B3xQ HAL User Manual: All PLLs VCO range

Defines
All PLLs VCO range
RCC Exported Constants

Defines

#define | LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */
#define | LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */

Define Documentation

#define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */

Definition at line 1365 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */

Definition at line 1364 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 1397 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1390 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
Helper macro to calculate the SYSCLK frequency.
#define | LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])
Helper macro to calculate the PCLK3 frequency (APB3)
#define | LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])
Helper macro to calculate the PCLK4 frequency (ABP4)

Define Documentation

#define LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __HPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency.
__HPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_AHB_DIV_1
  • LL_RCC_AHB_DIV_2
  • LL_RCC_AHB_DIV_4
  • LL_RCC_AHB_DIV_8
  • LL_RCC_AHB_DIV_16
  • LL_RCC_AHB_DIV_64
  • LL_RCC_AHB_DIV_128
  • LL_RCC_AHB_DIV_256
  • LL_RCC_AHB_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 1445 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1462 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1479 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define LL_RCC_CALC_PCLK3_FREQ | ( | __HCLKFREQ__,
 |  | __APB3PRESCALER__
 | ) | ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])

Helper macro to calculate the PCLK3 frequency (APB3)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB3PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB3_DIV_1
  • LL_RCC_APB3_DIV_2
  • LL_RCC_APB3_DIV_4
  • LL_RCC_APB3_DIV_8
  • LL_RCC_APB3_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1496 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK3ClockFreq().

#define LL_RCC_CALC_PCLK4_FREQ | ( | __HCLKFREQ__,
 |  | __APB4PRESCALER__
 | ) | ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])

Helper macro to calculate the PCLK4 frequency (ABP4)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB4PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB4_DIV_1
  • LL_RCC_APB4_DIV_2
  • LL_RCC_APB4_DIV_4
  • LL_RCC_APB4_DIV_8
  • LL_RCC_APB4_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1513 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK4ClockFreq().

#define LL_RCC_CALC_SYSCLK_FREQ | ( | __SYSINPUTCLKFREQ__,
 |  | __SYSPRESCALER__
 | ) | ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])

Helper macro to calculate the SYSCLK frequency.

Parameters:
__SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
__SYSPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
SYSCLK clock frequency (in Hz)

Definition at line 1424 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), and LL_RCC_GetUSARTClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Macros

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 1525 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 1524 of file stm32h7xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_SelectAnalogClock (void)
Select the Analog HSE external clock type in Bypass mode.
__STATIC_INLINE void | LL_RCC_HSE_SelectDigitalClock (void)
Select the Digital HSE external clock type in Bypass mode.
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 1613 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 1571 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 1603 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 1561 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Note:
Once HSE Clock Security System is enabled it cannot be changed anymore unless a reset occurs or system enter in standby mode.
Reference Manual to LL API cross reference:
CR CSSHSEON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 1551 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1623 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), and LL_RCC_GetSPIClockFreq().

__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock ( void )

Select the Analog HSE external clock type in Bypass mode.

Reference Manual to LL API cross reference:
CR HSEEXT LL_RCC_HSE_SelectAnalogClock
Return values:
None

Definition at line 1582 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock ( void )

Select the Digital HSE external clock type in Bypass mode.

Reference Manual to LL API cross reference:
CR HSEEXT LL_RCC_HSE_SelectDigitalClock
Return values:
None

Definition at line 1592 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsDividerReady (void)
Check if HSI new divider applied and ready.
__STATIC_INLINE void | LL_RCC_HSI_SetDivider (uint32_t Divider)
Set HSI divider.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetDivider (void)
Get HSI divider.
__STATIC_INLINE void | LL_RCC_HSI_EnableStopMode (void)
Enable HSI oscillator in Stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableStopMode (void)
Disable HSI oscillator in Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1651 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableStopMode ( void )

Disable HSI oscillator in Stop mode.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_DisableStopMode
Return values:
None

Definition at line 1720 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1641 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_HSI_EnableStopMode ( void )

Enable HSI oscillator in Stop mode.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_EnableStopMode
Return values:
None

Definition at line 1710 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
HSICFGR HSICAL LL_RCC_HSI_GetCalibration
Return values:
A value between 0 and 4095 (0xFFF)

Definition at line 1732 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
A value between 0 and 127 (63 for Cut1.x)

Definition at line 1769 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider ( void )

Get HSI divider.

Reference Manual to LL API cross reference:
CR HSIDIV LL_RCC_HSI_GetDivider
Return values:
can be one of the following values:
  • LL_RCC_HSI_DIV1
  • LL_RCC_HSI_DIV2
  • LL_RCC_HSI_DIV4
  • LL_RCC_HSI_DIV8

Definition at line 1700 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetUSARTClockFreq(), and RCC_GetSystemClockFreq().

__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady ( void )

Check if HSI new divider applied and ready.

Reference Manual to LL API cross reference:
CR HSIDIVF LL_RCC_HSI_IsDividerReady
Return values:
State of bit (1 or 0).

Definition at line 1671 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1661 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_DeInit(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value, should trim the HSI to 64 MHz +/- 1 %
Reference Manual to LL API cross reference:
HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Parameter can be a value between 0 and 127 (63 for Cut1.x)
Return values:
None

Definition at line 1746 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_SetDivider ( uint32_t Divider )

Set HSI divider.

Reference Manual to LL API cross reference:
CR HSIDIV LL_RCC_HSI_SetDivider
Parameters:
Divider This parameter can be one of the following values:
  • LL_RCC_HSI_DIV1
  • LL_RCC_HSI_DIV2
  • LL_RCC_HSI_DIV4
  • LL_RCC_HSI_DIV8
Return values:
None.

Definition at line 1686 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CSI

Functions
CSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_CSI_Enable (void)
Enable CSI oscillator.
__STATIC_INLINE void | LL_RCC_CSI_Disable (void)
Disable CSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_CSI_IsReady (void)
Check if CSI clock is ready.
__STATIC_INLINE void | LL_RCC_CSI_EnableStopMode (void)
Enable CSI oscillator in Stop mode.
__STATIC_INLINE void | LL_RCC_CSI_DisableStopMode (void)
Disable CSI oscillator in Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibration (void)
Get CSI Calibration value.
__STATIC_INLINE void | LL_RCC_CSI_SetCalibTrimming (uint32_t Value)
Set CSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibTrimming (void)
Get CSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_CSI_Disable ( void )

Disable CSI oscillator.

Reference Manual to LL API cross reference:
CR CSION LL_RCC_CSI_Disable
Return values:
None

Definition at line 1810 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_CSI_DisableStopMode ( void )

Disable CSI oscillator in Stop mode.

Reference Manual to LL API cross reference:
CR CSIKERON LL_RCC_CSI_DisableStopMode
Return values:
None

Definition at line 1840 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_CSI_Enable ( void )

Enable CSI oscillator.

Reference Manual to LL API cross reference:
CR CSION LL_RCC_CSI_Enable
Return values:
None

Definition at line 1800 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_CSI_EnableStopMode ( void )

Enable CSI oscillator in Stop mode.

Reference Manual to LL API cross reference:
CR CSIKERON LL_RCC_CSI_EnableStopMode
Return values:
None

Definition at line 1830 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration ( void )

Get CSI Calibration value.

Note:
When CSITRIM is written, CSICAL is updated with the sum of CSITRIM and the factory trim value
Reference Manual to LL API cross reference:
CSICFGR CSICAL LL_RCC_CSI_GetCalibration
Return values:
A value between 0 and 255 (0xFF)

Definition at line 1852 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming ( void )

Get CSI Calibration trimming.

Reference Manual to LL API cross reference:
CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
Return values:
A value between 0 and 31

Definition at line 1902 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady ( void )

Check if CSI clock is ready.

Reference Manual to LL API cross reference:
CR CSIRDY LL_RCC_CSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1820 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPIClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming ( uint32_t Value )

Set CSI Calibration trimming.

Note:
user-programmable trimming value that is added to the CSICAL
Default value is 16, which, when added to the CSICAL value, should trim the CSI to 4 MHz +/- 1 %
Reference Manual to LL API cross reference:
CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
Parameters:
Value can be a value between 0 and 31
Return values:
None

Definition at line 1879 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSI48

Functions
HSI48
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48 oscillator.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48 oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI48_Disable ( void )

Disable HSI48 oscillator.

Reference Manual to LL API cross reference:
CR HSI48ON LL_RCC_HSI48_Disable
Return values:
None

Definition at line 1943 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI48_Enable ( void )

Enable HSI48 oscillator.

Reference Manual to LL API cross reference:
CR HSI48ON LL_RCC_HSI48_Enable
Return values:
None

Definition at line 1933 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration ( void )

Get HSI48 Calibration value.

Note:
When HSI48TRIM is written, HSI48CAL is updated with the sum of HSI48TRIM and the factory trim value
Reference Manual to LL API cross reference:
CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Return values:
A value between 0 and 1023 (0x3FF)

Definition at line 1965 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady ( void )

Check if HSI48 clock is ready.

Reference Manual to LL API cross reference:
CR HSI48RDY LL_RCC_HSI48_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1953 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CPUCKREADY

Defines | Functions
CPUCKREADY
RCC Exported Functions

Defines

#define | LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady

Functions

__STATIC_INLINE uint32_t | LL_RCC_CPUCK_IsReady (void)
Check if CPU clock is ready.

Define Documentation

#define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady

Definition at line 2008 of file stm32h7xx_ll_rcc.h.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady ( void )

Check if CPU clock is ready.

Reference Manual to LL API cross reference:
CR CPUCKRDY LL_RCC_CPUCK_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2003 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CDCKREADY

Defines | Functions
CDCKREADY
RCC Exported Functions

Defines

#define | LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady

Functions

__STATIC_INLINE uint32_t | LL_RCC_CDCK_IsReady (void)
Check if CD clock is ready.

Define Documentation

#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady

Definition at line 2047 of file stm32h7xx_ll_rcc.h.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady ( void )

Check if CD clock is ready.

Reference Manual to LL API cross reference:
CR CDCKRDY LL_RCC_CDCK_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2043 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RESET

RESET
RCC Exported Functions
Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable the Clock Security System on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsFailureDetected (void)
Check if LSE failure is detected by Clock Security System.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SelectDigitalClock (void)
Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
__STATIC_INLINE void | LL_RCC_LSE_SelectAnalogClock (void)
Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 2195 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 2215 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 2185 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 2205 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableCSS ( void )

Enable the Clock Security System on LSE.

Note:
Once LSE Clock Security System is enabled it cannot be changed anymore unless a clock failure is detected.
Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_EnableCSS
Return values:
None

Definition at line 2165 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 2271 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected ( void )

Check if LSE failure is detected by Clock Security System.

Reference Manual to LL API cross reference:
BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
Return values:
State of bit (1 or 0).

Definition at line 2175 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2281 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock ( void )

Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).

Note:
The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.
Reference Manual to LL API cross reference:
BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock
Return values:
None

Definition at line 2240 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock ( void )

Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).

Note:
The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.
Reference Manual to LL API cross reference:
BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock
Return values:
None

Definition at line 2228 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 2257 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 2309 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 2299 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2319 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), and LL_RCC_GetRNGClockFreq().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetSysWakeUpClkSource (uint32_t Source)
Configure the system wakeup clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysWakeUpClkSource (void)
Get the system wakeup clock source.
__STATIC_INLINE void | LL_RCC_SetKerWakeUpClkSource (uint32_t Source)
Configure the kernel wakeup clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetKerWakeUpClkSource (void)
Get the kernel wakeup clock source.
__STATIC_INLINE void | LL_RCC_SetSysPrescaler (uint32_t Prescaler)
Set System prescaler.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB3Prescaler (uint32_t Prescaler)
Set APB3 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB4Prescaler (uint32_t Prescaler)
Set APB4 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetSysPrescaler (void)
Get System prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB3Prescaler (void)
Get APB3 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB4Prescaler (void)
Get APB4 prescaler.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_AHB_DIV_1
  • LL_RCC_AHB_DIV_2
  • LL_RCC_AHB_DIV_4
  • LL_RCC_AHB_DIV_8
  • LL_RCC_AHB_DIV_16
  • LL_RCC_AHB_DIV_64
  • LL_RCC_AHB_DIV_128
  • LL_RCC_AHB_DIV_256
  • LL_RCC_AHB_DIV_512

Definition at line 2576 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 2595 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 2614 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler ( void )

Get APB3 prescaler.

Reference Manual to LL API cross reference:
D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB3_DIV_1
  • LL_RCC_APB3_DIV_2
  • LL_RCC_APB3_DIV_4
  • LL_RCC_APB3_DIV_8
  • LL_RCC_APB3_DIV_16

Definition at line 2633 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler ( void )

Get APB4 prescaler.

Reference Manual to LL API cross reference:
D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB4_DIV_1
  • LL_RCC_APB4_DIV_2
  • LL_RCC_APB4_DIV_4
  • LL_RCC_APB4_DIV_8
  • LL_RCC_APB4_DIV_16

Definition at line 2652 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetPCLK4ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource ( void )

Get the kernel wakeup clock source.

Reference Manual to LL API cross reference:
CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_KERWAKEUP_CLKSOURCE_HSI
  • LL_RCC_KERWAKEUP_CLKSOURCE_CSI

Definition at line 2406 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_CSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL1

Definition at line 2356 of file stm32h7xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler ( void )

Get System prescaler.

Reference Manual to LL API cross reference:
D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 2553 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDM2ClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource ( void )

Get the system wakeup clock source.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
  • LL_RCC_SYSWAKEUP_CLKSOURCE_CSI

Definition at line 2381 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_AHB_DIV_1
  • LL_RCC_AHB_DIV_2
  • LL_RCC_AHB_DIV_4
  • LL_RCC_AHB_DIV_8
  • LL_RCC_AHB_DIV_16
  • LL_RCC_AHB_DIV_64
  • LL_RCC_AHB_DIV_128
  • LL_RCC_AHB_DIV_256
  • LL_RCC_AHB_DIV_512
Return values:
None

Definition at line 2450 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 2470 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 2490 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB3Prescaler ( uint32_t Prescaler )

Set APB3 prescaler.

Reference Manual to LL API cross reference:
D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB3_DIV_1
  • LL_RCC_APB3_DIV_2
  • LL_RCC_APB3_DIV_4
  • LL_RCC_APB3_DIV_8
  • LL_RCC_APB3_DIV_16
Return values:
None

Definition at line 2510 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB4Prescaler ( uint32_t Prescaler )

Set APB4 prescaler.

Reference Manual to LL API cross reference:
D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB4_DIV_1
  • LL_RCC_APB4_DIV_2
  • LL_RCC_APB4_DIV_4
  • LL_RCC_APB4_DIV_8
  • LL_RCC_APB4_DIV_16
Return values:
None

Definition at line 2530 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource ( uint32_t Source )

Configure the kernel wakeup clock source.

Reference Manual to LL API cross reference:
CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_KERWAKEUP_CLKSOURCE_HSI
  • LL_RCC_KERWAKEUP_CLKSOURCE_CSI
Return values:
None

Definition at line 2394 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_CSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL1
Return values:
None

Definition at line 2342 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetSysPrescaler ( uint32_t Prescaler )

Set System prescaler.

Reference Manual to LL API cross reference:
D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 2426 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource ( uint32_t Source )

Configure the system wakeup clock source.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
  • LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
Return values:
None

Definition at line 2369 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCO1 LL_RCC_ConfigMCO
CFGR MCO1PRE LL_RCC_ConfigMCO
CFGR MCO2 LL_RCC_ConfigMCO
CFGR MCO2PRE LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_LSE
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_PLL1QCLK
  • LL_RCC_MCO1SOURCE_HSI48
  • LL_RCC_MCO2SOURCE_SYSCLK
  • LL_RCC_MCO2SOURCE_PLL2PCLK
  • LL_RCC_MCO2SOURCE_HSE
  • LL_RCC_MCO2SOURCE_PLL1PCLK
  • LL_RCC_MCO2SOURCE_CSI
  • LL_RCC_MCO2SOURCE_LSI
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2
  • LL_RCC_MCO1_DIV_3
  • LL_RCC_MCO1_DIV_4
  • LL_RCC_MCO1_DIV_5
  • LL_RCC_MCO1_DIV_6
  • LL_RCC_MCO1_DIV_7
  • LL_RCC_MCO1_DIV_8
  • LL_RCC_MCO1_DIV_9
  • LL_RCC_MCO1_DIV_10
  • LL_RCC_MCO1_DIV_11
  • LL_RCC_MCO1_DIV_12
  • LL_RCC_MCO1_DIV_13
  • LL_RCC_MCO1_DIV_14
  • LL_RCC_MCO1_DIV_15
  • LL_RCC_MCO2_DIV_1
  • LL_RCC_MCO2_DIV_2
  • LL_RCC_MCO2_DIV_3
  • LL_RCC_MCO2_DIV_4
  • LL_RCC_MCO2_DIV_5
  • LL_RCC_MCO2_DIV_6
  • LL_RCC_MCO2_DIV_7
  • LL_RCC_MCO2_DIV_8
  • LL_RCC_MCO2_DIV_9
  • LL_RCC_MCO2_DIV_10
  • LL_RCC_MCO2_DIV_11
  • LL_RCC_MCO2_DIV_12
  • LL_RCC_MCO2_DIV_13
  • LL_RCC_MCO2_DIV_14
  • LL_RCC_MCO2_DIV_15
Return values:
None

Definition at line 2720 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetClockSource (uint32_t ClkSource)
Configure periph clock source.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t ClkSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t ClkSource)
Configure LPUARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t ClkSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t ClkSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t ClkSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetSDMMCClockSource (uint32_t ClkSource)
Configure SDMMCx clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t ClkSource)
Configure RNGx clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t ClkSource)
Configure USBx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t ClkSource)
Configure CECx clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDMClockSource (uint32_t ClkSource)
Configure DFSDMx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDM2ClockSource (uint32_t ClkSource)
Configure DFSDMx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetFMCClockSource (uint32_t ClkSource)
Configure FMCx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetOSPIClockSource (uint32_t ClkSource)
Configure OSPIx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetCLKPClockSource (uint32_t ClkSource)
Configure CLKP Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSPIClockSource (uint32_t ClkSource)
Configure SPIx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSPDIFClockSource (uint32_t ClkSource)
Configure SPDIFx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t ClkSource)
Configure FDCANx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSWPClockSource (uint32_t ClkSource)
Configure SWPx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ClkSource)
Configure ADCx Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetClockSource (uint32_t Periph)
Get periph clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t Periph)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t Periph)
Get LPUART clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t Periph)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t Periph)
Get LPTIM clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t Periph)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDMMCClockSource (uint32_t Periph)
Get SDMMC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t Periph)
Get RNG clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t Periph)
Get USB clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t Periph)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDMClockSource (uint32_t Periph)
Get DFSDM Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDM2ClockSource (uint32_t Periph)
Get DFSDM2 Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFMCClockSource (uint32_t Periph)
Get FMC Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetOSPIClockSource (uint32_t Periph)
Get OSPI Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCLKPClockSource (uint32_t Periph)
Get CLKP Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSPIClockSource (uint32_t Periph)
Get SPIx Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSPDIFClockSource (uint32_t Periph)
Get SPDIF Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t Periph)
Get FDCAN Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSWPClockSource (uint32_t Periph)
Get SWP Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t Periph)
Get ADC Kernel clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t Periph )

Get ADC Kernel clock source.

Reference Manual to LL API cross reference:
D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_PLL2P
  • LL_RCC_ADC_CLKSOURCE_PLL3R
  • LL_RCC_ADC_CLKSOURCE_CLKP

Definition at line 3882 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource ( uint32_t Periph )

Get CEC clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_LSE
  • LL_RCC_CEC_CLKSOURCE_LSI
  • LL_RCC_CEC_CLKSOURCE_CSI_DIV122

Definition at line 3634 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource ( uint32_t Periph )

Get CLKP Kernel clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_CLKP_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_CLKP_CLKSOURCE_HSI
  • LL_RCC_CLKP_CLKSOURCE_CSI
  • LL_RCC_CLKP_CLKSOURCE_HSE

Definition at line 3766 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetCLKPClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetClockSource ( uint32_t Periph )

Get periph clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR * LL_RCC_GetClockSource
D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource
D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource
D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE
  • LL_RCC_USART234578_CLKSOURCE
  • LL_RCC_I2C123_CLKSOURCE
  • LL_RCC_I2C4_CLKSOURCE
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
  • LL_RCC_LPTIM345_CLKSOURCE
  • LL_RCC_SAI1_CLKSOURCE
  • LL_RCC_SAI23_CLKSOURCE
  • LL_RCC_SAI4A_CLKSOURCE (*)
  • LL_RCC_SAI4B_CLKSOURCE (*)
  • LL_RCC_SAI2A_CLKSOURCE (*)
  • LL_RCC_SAI2B_CLKSOURCE (*)
  • LL_RCC_SPI123_CLKSOURCE (*)
  • LL_RCC_SPI45_CLKSOURCE (*)
  • LL_RCC_SPI6_CLKSOURCE (*)
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE_PCLK2
  • LL_RCC_USART16_CLKSOURCE_PLL2Q
  • LL_RCC_USART16_CLKSOURCE_PLL3Q
  • LL_RCC_USART16_CLKSOURCE_HSI
  • LL_RCC_USART16_CLKSOURCE_CSI
  • LL_RCC_USART16_CLKSOURCE_LSE
  • LL_RCC_USART234578_CLKSOURCE_PCLK1
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q
  • LL_RCC_USART234578_CLKSOURCE_HSI
  • LL_RCC_USART234578_CLKSOURCE_CSI
  • LL_RCC_USART234578_CLKSOURCE_LSE
  • LL_RCC_I2C123_CLKSOURCE_PCLK1
  • LL_RCC_I2C123_CLKSOURCE_PLL3R
  • LL_RCC_I2C123_CLKSOURCE_HSI
  • LL_RCC_I2C123_CLKSOURCE_CSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK4
  • LL_RCC_I2C4_CLKSOURCE_PLL3R
  • LL_RCC_I2C4_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_CSI
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM345_CLKSOURCE_LSE
  • LL_RCC_LPTIM345_CLKSOURCE_LSI
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q
  • LL_RCC_SAI1_CLKSOURCE_PLL2P
  • LL_RCC_SAI1_CLKSOURCE_PLL3P
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI1_CLKSOURCE_CLKP
  • LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI23_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q
  • LL_RCC_SPI123_CLKSOURCE_PLL2P
  • LL_RCC_SPI123_CLKSOURCE_PLL3P
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
  • LL_RCC_SPI123_CLKSOURCE_CLKP
  • LL_RCC_SPI45_CLKSOURCE_PCLK2
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q
  • LL_RCC_SPI45_CLKSOURCE_HSI
  • LL_RCC_SPI45_CLKSOURCE_CSI
  • LL_RCC_SPI45_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_PCLK4
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q
  • LL_RCC_SPI6_CLKSOURCE_HSI
  • LL_RCC_SPI6_CLKSOURCE_CSI
  • LL_RCC_SPI6_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
(*) value not defined in all devices.
None

Definition at line 3395 of file stm32h7xx_ll_rcc.h.

References LL_CLKSOURCE_MASK, LL_CLKSOURCE_REG, LL_CLKSOURCE_SHIFT, and LL_RCC_CONFIG_SHIFT.

Referenced by LL_RCC_GetI2CClockSource(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSAIClockSource(), LL_RCC_GetSPIClockSource(), and LL_RCC_GetUSARTClockSource().

__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource ( uint32_t Periph )

Get DFSDM2 Kernel clock source.

Reference Manual to LL API cross reference:
SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_DFSDM2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_DFSDM2_CLKSOURCE_PCLK4
  • LL_RCC_DFSDM2_CLKSOURCE_SYSCLK

Definition at line 3690 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDM2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource ( uint32_t Periph )

Get DFSDM Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK2
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK

Definition at line 3670 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource ( uint32_t Periph )

Get FDCAN Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_HSE
  • LL_RCC_FDCAN_CLKSOURCE_PLL1Q
  • LL_RCC_FDCAN_CLKSOURCE_PLL2Q

Definition at line 3843 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource ( uint32_t Periph )

Get FMC Kernel clock source.

Reference Manual to LL API cross reference:
D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_FMC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_FMC_CLKSOURCE_HCLK
  • LL_RCC_FMC_CLKSOURCE_PLL1Q
  • LL_RCC_FMC_CLKSOURCE_PLL2R
  • LL_RCC_FMC_CLKSOURCE_CLKP

Definition at line 3708 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetFMCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t Periph )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource
D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_I2C123_CLKSOURCE
  • LL_RCC_I2C4_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C123_CLKSOURCE_PCLK1
  • LL_RCC_I2C123_CLKSOURCE_PLL3R
  • LL_RCC_I2C123_CLKSOURCE_HSI
  • LL_RCC_I2C123_CLKSOURCE_CSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK4
  • LL_RCC_I2C4_CLKSOURCE_PLL3R
  • LL_RCC_I2C4_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_CSI

Definition at line 3471 of file stm32h7xx_ll_rcc.h.

References LL_RCC_GetClockSource().

Referenced by LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource ( uint32_t Periph )

Get LPTIM clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource
D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource
D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
Parameters:
Perihp This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
  • LL_RCC_LPTIM345_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM345_CLKSOURCE_LSE
  • LL_RCC_LPTIM345_CLKSOURCE_LSI
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP
None

Definition at line 3506 of file stm32h7xx_ll_rcc.h.

References LL_RCC_GetClockSource().

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource ( uint32_t Periph )

Get LPUART clock source.

Reference Manual to LL API cross reference:
D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK4
  • LL_RCC_LPUART1_CLKSOURCE_PLL2Q
  • LL_RCC_LPUART1_CLKSOURCE_PLL3Q
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_CSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE

Definition at line 3444 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource ( uint32_t Periph )

Get OSPI Kernel clock source.

Reference Manual to LL API cross reference:
CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_OSPI_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_OSPI_CLKSOURCE_HCLK
  • LL_RCC_OSPI_CLKSOURCE_PLL1Q
  • LL_RCC_OSPI_CLKSOURCE_PLL2R
  • LL_RCC_OSPI_CLKSOURCE_CLKP

Definition at line 3749 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetOSPIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource ( uint32_t Periph )

Get RNG clock source.

Reference Manual to LL API cross reference:
D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_HSI48
  • LL_RCC_RNG_CLKSOURCE_PLL1Q
  • LL_RCC_RNG_CLKSOURCE_LSE
  • LL_RCC_RNG_CLKSOURCE_LSI

Definition at line 3593 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource ( uint32_t Periph )

Get SAIx clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource
D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource
D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
  • LL_RCC_SAI23_CLKSOURCE
  • LL_RCC_SAI4A_CLKSOURCE
  • LL_RCC_SAI4B_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q
  • LL_RCC_SAI1_CLKSOURCE_PLL2P
  • LL_RCC_SAI1_CLKSOURCE_PLL3P
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI1_CLKSOURCE_CLKP
  • LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI23_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
(*) value not defined in all devices.

Definition at line 3558 of file stm32h7xx_ll_rcc.h.

References LL_RCC_GetClockSource().

Referenced by LL_RCC_GetSAIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource ( uint32_t Periph )

Get SDMMC clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_SDMMC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SDMMC_CLKSOURCE_PLL1Q
  • LL_RCC_SDMMC_CLKSOURCE_PLL2R

Definition at line 3572 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource ( uint32_t Periph )

Get SPDIF Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_SPDIF_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SPDIF_CLKSOURCE_PLL1Q
  • LL_RCC_SPDIF_CLKSOURCE_PLL2R
  • LL_RCC_SPDIF_CLKSOURCE_PLL3R
  • LL_RCC_SPDIF_CLKSOURCE_HSI

Definition at line 3823 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSPDIFClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource ( uint32_t Periph )

Get SPIx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource
D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource
D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_SPI123_CLKSOURCE
  • LL_RCC_SPI45_CLKSOURCE
  • LL_RCC_SPI6_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q
  • LL_RCC_SPI123_CLKSOURCE_PLL2P
  • LL_RCC_SPI123_CLKSOURCE_PLL3P
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
  • LL_RCC_SPI123_CLKSOURCE_CLKP
  • LL_RCC_SPI45_CLKSOURCE_PCLK2
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q
  • LL_RCC_SPI45_CLKSOURCE_HSI
  • LL_RCC_SPI45_CLKSOURCE_CSI
  • LL_RCC_SPI45_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_PCLK4
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q
  • LL_RCC_SPI6_CLKSOURCE_HSI
  • LL_RCC_SPI6_CLKSOURCE_CSI
  • LL_RCC_SPI6_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
(*) value not defined in all stm32h7xx lines.

Definition at line 3807 of file stm32h7xx_ll_rcc.h.

References LL_RCC_GetClockSource().

Referenced by LL_RCC_GetSPIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource ( uint32_t Periph )

Get SWP Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_SWP_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SWP_CLKSOURCE_PCLK1
  • LL_RCC_SWP_CLKSOURCE_HSI

Definition at line 3862 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t Periph )

Get USARTx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource
D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE
  • LL_RCC_USART234578_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE_PCLK2
  • LL_RCC_USART16_CLKSOURCE_PLL2Q
  • LL_RCC_USART16_CLKSOURCE_PLL3Q
  • LL_RCC_USART16_CLKSOURCE_HSI
  • LL_RCC_USART16_CLKSOURCE_CSI
  • LL_RCC_USART16_CLKSOURCE_LSE
  • LL_RCC_USART234578_CLKSOURCE_PCLK1
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q
  • LL_RCC_USART234578_CLKSOURCE_HSI
  • LL_RCC_USART234578_CLKSOURCE_CSI
  • LL_RCC_USART234578_CLKSOURCE_LSE

Definition at line 3426 of file stm32h7xx_ll_rcc.h.

References LL_RCC_GetClockSource().

Referenced by LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t Periph )

Get USB clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource
Parameters:
Periph This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_DISABLE
  • LL_RCC_USB_CLKSOURCE_PLL1Q
  • LL_RCC_USB_CLKSOURCE_PLL3Q
  • LL_RCC_USB_CLKSOURCE_HSI48

Definition at line 3614 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ClkSource )

Configure ADCx Kernel clock source.

Reference Manual to LL API cross reference:
D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_PLL2P
  • LL_RCC_ADC_CLKSOURCE_PLL3R
  • LL_RCC_ADC_CLKSOURCE_CLKP
Return values:
None

Definition at line 3270 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetCECClockSource ( uint32_t ClkSource )

Configure CECx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_LSE
  • LL_RCC_CEC_CLKSOURCE_LSI
  • LL_RCC_CEC_CLKSOURCE_CSI_DIV122
Return values:
None

Definition at line 3047 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetCLKPClockSource ( uint32_t ClkSource )

Configure CLKP Kernel clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_CLKP_CLKSOURCE_HSI
  • LL_RCC_CLKP_CLKSOURCE_CSI
  • LL_RCC_CLKP_CLKSOURCE_HSE
Return values:
None

Definition at line 3165 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetClockSource ( uint32_t ClkSource )

Configure periph clock source.

Reference Manual to LL API cross reference:
D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource
D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource
D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE_PCLK2
  • LL_RCC_USART16_CLKSOURCE_PLL2Q
  • LL_RCC_USART16_CLKSOURCE_PLL3Q
  • LL_RCC_USART16_CLKSOURCE_HSI
  • LL_RCC_USART16_CLKSOURCE_CSI
  • LL_RCC_USART16_CLKSOURCE_LSE
  • LL_RCC_USART234578_CLKSOURCE_PCLK1
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q
  • LL_RCC_USART234578_CLKSOURCE_HSI
  • LL_RCC_USART234578_CLKSOURCE_CSI
  • LL_RCC_USART234578_CLKSOURCE_LSE
  • LL_RCC_I2C123_CLKSOURCE_PCLK1
  • LL_RCC_I2C123_CLKSOURCE_PLL3R
  • LL_RCC_I2C123_CLKSOURCE_HSI
  • LL_RCC_I2C123_CLKSOURCE_CSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK4
  • LL_RCC_I2C4_CLKSOURCE_PLL3R
  • LL_RCC_I2C4_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_CSI
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM345_CLKSOURCE_LSE
  • LL_RCC_LPTIM345_CLKSOURCE_LSI
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q
  • LL_RCC_SAI1_CLKSOURCE_PLL2P
  • LL_RCC_SAI1_CLKSOURCE_PLL3P
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI1_CLKSOURCE_CLKP
  • LL_RCC_SAI23_CLKSOURCE_PLL1Q
  • LL_RCC_SAI23_CLKSOURCE_PLL2P
  • LL_RCC_SAI23_CLKSOURCE_PLL3P
  • LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI23_CLKSOURCE_CLKP
  • LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q
  • LL_RCC_SPI123_CLKSOURCE_PLL2P
  • LL_RCC_SPI123_CLKSOURCE_PLL3P
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
  • LL_RCC_SPI123_CLKSOURCE_CLKP
  • LL_RCC_SPI45_CLKSOURCE_PCLK2
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q
  • LL_RCC_SPI45_CLKSOURCE_HSI
  • LL_RCC_SPI45_CLKSOURCE_CSI
  • LL_RCC_SPI45_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_PCLK4
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q
  • LL_RCC_SPI6_CLKSOURCE_HSI
  • LL_RCC_SPI6_CLKSOURCE_CSI
  • LL_RCC_SPI6_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2830 of file stm32h7xx_ll_rcc.h.

References LL_CLKSOURCE_CONFIG, LL_CLKSOURCE_MASK, and LL_CLKSOURCE_REG.

Referenced by LL_RCC_SetI2CClockSource(), LL_RCC_SetLPTIMClockSource(), LL_RCC_SetSAIClockSource(), LL_RCC_SetSPIClockSource(), and LL_RCC_SetUSARTClockSource().

__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource ( uint32_t ClkSource )

Configure DFSDMx Kernel clock source.

Reference Manual to LL API cross reference:
SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_DFSDM2_CLKSOURCE_PCLK2
  • LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
Return values:
None

Definition at line 3097 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetDFSDMClockSource ( uint32_t ClkSource )

Configure DFSDMx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK2
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Return values:
None

Definition at line 3079 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetFDCANClockSource ( uint32_t ClkSource )

Configure FDCANx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_HSE
  • LL_RCC_FDCAN_CLKSOURCE_PLL1Q
  • LL_RCC_FDCAN_CLKSOURCE_PLL2Q
Return values:
None

Definition at line 3235 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetFMCClockSource ( uint32_t ClkSource )

Configure FMCx Kernel clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_FMC_CLKSOURCE_HCLK
  • LL_RCC_FMC_CLKSOURCE_PLL1Q
  • LL_RCC_FMC_CLKSOURCE_PLL2R
  • LL_RCC_FMC_CLKSOURCE_CLKP
Return values:
None

Definition at line 3113 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t ClkSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource
D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_I2C123_CLKSOURCE_PCLK1
  • LL_RCC_I2C123_CLKSOURCE_PLL3R
  • LL_RCC_I2C123_CLKSOURCE_HSI
  • LL_RCC_I2C123_CLKSOURCE_CSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK4
  • LL_RCC_I2C4_CLKSOURCE_PLL3R
  • LL_RCC_I2C4_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_CSI
Return values:
None

Definition at line 2900 of file stm32h7xx_ll_rcc.h.

References LL_RCC_SetClockSource().

__STATIC_INLINE void LL_RCC_SetLPTIMClockSource ( uint32_t ClkSource )

Configure LPTIMx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource
D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R
  • LL_RCC_LPTIM345_CLKSOURCE_LSE
  • LL_RCC_LPTIM345_CLKSOURCE_LSI
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP
Return values:
None

Definition at line 2931 of file stm32h7xx_ll_rcc.h.

References LL_RCC_SetClockSource().

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_RCC_SetLPUARTClockSource ( uint32_t ClkSource )

Configure LPUARTx clock source.

Reference Manual to LL API cross reference:
D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK4
  • LL_RCC_LPUART1_CLKSOURCE_PLL2Q
  • LL_RCC_LPUART1_CLKSOURCE_PLL3Q
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_CSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
Return values:
None

Definition at line 2876 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetOSPIClockSource ( uint32_t ClkSource )

Configure OSPIx Kernel clock source.

Reference Manual to LL API cross reference:
D1CCIPR OPISEL LL_RCC_SetOSPIClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_OSPI_CLKSOURCE_HCLK
  • LL_RCC_OSPI_CLKSOURCE_PLL1Q
  • LL_RCC_OSPI_CLKSOURCE_PLL2R
  • LL_RCC_OSPI_CLKSOURCE_CLKP
Return values:
None

Definition at line 3150 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockSource ( uint32_t ClkSource )

Configure RNGx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_HSI48
  • LL_RCC_RNG_CLKSOURCE_PLL1Q
  • LL_RCC_RNG_CLKSOURCE_LSE
  • LL_RCC_RNG_CLKSOURCE_LSI
Return values:
None

Definition at line 3010 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSAIClockSource ( uint32_t ClkSource )

Configure SAIx clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource
D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource
D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q
  • LL_RCC_SAI1_CLKSOURCE_PLL2P
  • LL_RCC_SAI1_CLKSOURCE_PLL3P
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI1_CLKSOURCE_CLKP
  • LL_RCC_SAI23_CLKSOURCE_PLL1Q
  • LL_RCC_SAI23_CLKSOURCE_PLL2P
  • LL_RCC_SAI23_CLKSOURCE_PLL3P
  • LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
  • LL_RCC_SAI23_CLKSOURCE_CLKP
  • LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
  • LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2978 of file stm32h7xx_ll_rcc.h.

References LL_RCC_SetClockSource().

__STATIC_INLINE void LL_RCC_SetSDMMCClockSource ( uint32_t ClkSource )

Configure SDMMCx clock source.

Reference Manual to LL API cross reference:
D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_SDMMC_CLKSOURCE_PLL1Q
  • LL_RCC_SDMMC_CLKSOURCE_PLL2R
Return values:
None

Definition at line 2991 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSPDIFClockSource ( uint32_t ClkSource )

Configure SPDIFx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_SPDIF_CLKSOURCE_PLL1Q
  • LL_RCC_SPDIF_CLKSOURCE_PLL2R
  • LL_RCC_SPDIF_CLKSOURCE_PLL3R
  • LL_RCC_SPDIF_CLKSOURCE_HSI
Return values:
None

Definition at line 3217 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSPIClockSource ( uint32_t ClkSource )

Configure SPIx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource
D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource
D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q
  • LL_RCC_SPI123_CLKSOURCE_PLL2P
  • LL_RCC_SPI123_CLKSOURCE_PLL3P
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
  • LL_RCC_SPI123_CLKSOURCE_CLKP
  • LL_RCC_SPI45_CLKSOURCE_PCLK2
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q
  • LL_RCC_SPI45_CLKSOURCE_HSI
  • LL_RCC_SPI45_CLKSOURCE_CSI
  • LL_RCC_SPI45_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_PCLK4
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q
  • LL_RCC_SPI6_CLKSOURCE_HSI
  • LL_RCC_SPI6_CLKSOURCE_CSI
  • LL_RCC_SPI6_CLKSOURCE_HSE
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 3202 of file stm32h7xx_ll_rcc.h.

References LL_RCC_SetClockSource().

__STATIC_INLINE void LL_RCC_SetSWPClockSource ( uint32_t ClkSource )

Configure SWPx Kernel clock source.

Reference Manual to LL API cross reference:
D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_SWP_CLKSOURCE_PCLK1
  • LL_RCC_SWP_CLKSOURCE_HSI
Return values:
None

Definition at line 3252 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t ClkSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource
D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE_PCLK2
  • LL_RCC_USART16_CLKSOURCE_PLL2Q
  • LL_RCC_USART16_CLKSOURCE_PLL3Q
  • LL_RCC_USART16_CLKSOURCE_HSI
  • LL_RCC_USART16_CLKSOURCE_CSI
  • LL_RCC_USART16_CLKSOURCE_LSE
  • LL_RCC_USART234578_CLKSOURCE_PCLK1
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q
  • LL_RCC_USART234578_CLKSOURCE_HSI
  • LL_RCC_USART234578_CLKSOURCE_CSI
  • LL_RCC_USART234578_CLKSOURCE_LSE
Return values:
None

Definition at line 2859 of file stm32h7xx_ll_rcc.h.

References LL_RCC_SetClockSource().

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t ClkSource )

Configure USBx clock source.

Reference Manual to LL API cross reference:
D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource
Parameters:
ClkSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_DISABLE
  • LL_RCC_USB_CLKSOURCE_PLL1Q
  • LL_RCC_USB_CLKSOURCE_PLL3Q
  • LL_RCC_USB_CLKSOURCE_HSI48
Return values:
None

Definition at line 3029 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_SetRTC_HSEPrescaler (uint32_t Prescaler)
Set HSE Prescalers for RTC Clock.
__STATIC_INLINE uint32_t | LL_RCC_GetRTC_HSEPrescaler (void)
Get HSE Prescalers for RTC Clock.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 3947 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 3937 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 3967 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler ( void )

Get HSE Prescalers for RTC Clock.

Reference Manual to LL API cross reference:
CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_NOCLOCK
  • LL_RCC_RTC_HSE_DIV_2
  • LL_RCC_RTC_HSE_DIV_3
  • LL_RCC_RTC_HSE_DIV_4
  • LL_RCC_RTC_HSE_DIV_5
  • LL_RCC_RTC_HSE_DIV_6
  • LL_RCC_RTC_HSE_DIV_7
  • LL_RCC_RTC_HSE_DIV_8
  • LL_RCC_RTC_HSE_DIV_9
  • LL_RCC_RTC_HSE_DIV_10
  • LL_RCC_RTC_HSE_DIV_11
  • LL_RCC_RTC_HSE_DIV_12
  • LL_RCC_RTC_HSE_DIV_13
  • LL_RCC_RTC_HSE_DIV_14
  • LL_RCC_RTC_HSE_DIV_15
  • LL_RCC_RTC_HSE_DIV_16
  • LL_RCC_RTC_HSE_DIV_17
  • LL_RCC_RTC_HSE_DIV_18
  • LL_RCC_RTC_HSE_DIV_19
  • LL_RCC_RTC_HSE_DIV_20
  • LL_RCC_RTC_HSE_DIV_21
  • LL_RCC_RTC_HSE_DIV_22
  • LL_RCC_RTC_HSE_DIV_23
  • LL_RCC_RTC_HSE_DIV_24
  • LL_RCC_RTC_HSE_DIV_25
  • LL_RCC_RTC_HSE_DIV_26
  • LL_RCC_RTC_HSE_DIV_27
  • LL_RCC_RTC_HSE_DIV_28
  • LL_RCC_RTC_HSE_DIV_29
  • LL_RCC_RTC_HSE_DIV_30
  • LL_RCC_RTC_HSE_DIV_31
  • LL_RCC_RTC_HSE_DIV_32
  • LL_RCC_RTC_HSE_DIV_33
  • LL_RCC_RTC_HSE_DIV_34
  • LL_RCC_RTC_HSE_DIV_35
  • LL_RCC_RTC_HSE_DIV_36
  • LL_RCC_RTC_HSE_DIV_37
  • LL_RCC_RTC_HSE_DIV_38
  • LL_RCC_RTC_HSE_DIV_39
  • LL_RCC_RTC_HSE_DIV_40
  • LL_RCC_RTC_HSE_DIV_41
  • LL_RCC_RTC_HSE_DIV_42
  • LL_RCC_RTC_HSE_DIV_43
  • LL_RCC_RTC_HSE_DIV_44
  • LL_RCC_RTC_HSE_DIV_45
  • LL_RCC_RTC_HSE_DIV_46
  • LL_RCC_RTC_HSE_DIV_47
  • LL_RCC_RTC_HSE_DIV_48
  • LL_RCC_RTC_HSE_DIV_49
  • LL_RCC_RTC_HSE_DIV_50
  • LL_RCC_RTC_HSE_DIV_51
  • LL_RCC_RTC_HSE_DIV_52
  • LL_RCC_RTC_HSE_DIV_53
  • LL_RCC_RTC_HSE_DIV_54
  • LL_RCC_RTC_HSE_DIV_55
  • LL_RCC_RTC_HSE_DIV_56
  • LL_RCC_RTC_HSE_DIV_57
  • LL_RCC_RTC_HSE_DIV_58
  • LL_RCC_RTC_HSE_DIV_59
  • LL_RCC_RTC_HSE_DIV_60
  • LL_RCC_RTC_HSE_DIV_61
  • LL_RCC_RTC_HSE_DIV_62
  • LL_RCC_RTC_HSE_DIV_63

Definition at line 4128 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE

Definition at line 3927 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 3957 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 3977 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler ( uint32_t Prescaler )

Set HSE Prescalers for RTC Clock.

Reference Manual to LL API cross reference:
CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_RTC_NOCLOCK
  • LL_RCC_RTC_HSE_DIV_2
  • LL_RCC_RTC_HSE_DIV_3
  • LL_RCC_RTC_HSE_DIV_4
  • LL_RCC_RTC_HSE_DIV_5
  • LL_RCC_RTC_HSE_DIV_6
  • LL_RCC_RTC_HSE_DIV_7
  • LL_RCC_RTC_HSE_DIV_8
  • LL_RCC_RTC_HSE_DIV_9
  • LL_RCC_RTC_HSE_DIV_10
  • LL_RCC_RTC_HSE_DIV_11
  • LL_RCC_RTC_HSE_DIV_12
  • LL_RCC_RTC_HSE_DIV_13
  • LL_RCC_RTC_HSE_DIV_14
  • LL_RCC_RTC_HSE_DIV_15
  • LL_RCC_RTC_HSE_DIV_16
  • LL_RCC_RTC_HSE_DIV_17
  • LL_RCC_RTC_HSE_DIV_18
  • LL_RCC_RTC_HSE_DIV_19
  • LL_RCC_RTC_HSE_DIV_20
  • LL_RCC_RTC_HSE_DIV_21
  • LL_RCC_RTC_HSE_DIV_22
  • LL_RCC_RTC_HSE_DIV_23
  • LL_RCC_RTC_HSE_DIV_24
  • LL_RCC_RTC_HSE_DIV_25
  • LL_RCC_RTC_HSE_DIV_26
  • LL_RCC_RTC_HSE_DIV_27
  • LL_RCC_RTC_HSE_DIV_28
  • LL_RCC_RTC_HSE_DIV_29
  • LL_RCC_RTC_HSE_DIV_30
  • LL_RCC_RTC_HSE_DIV_31
  • LL_RCC_RTC_HSE_DIV_32
  • LL_RCC_RTC_HSE_DIV_33
  • LL_RCC_RTC_HSE_DIV_34
  • LL_RCC_RTC_HSE_DIV_35
  • LL_RCC_RTC_HSE_DIV_36
  • LL_RCC_RTC_HSE_DIV_37
  • LL_RCC_RTC_HSE_DIV_38
  • LL_RCC_RTC_HSE_DIV_39
  • LL_RCC_RTC_HSE_DIV_40
  • LL_RCC_RTC_HSE_DIV_41
  • LL_RCC_RTC_HSE_DIV_42
  • LL_RCC_RTC_HSE_DIV_43
  • LL_RCC_RTC_HSE_DIV_44
  • LL_RCC_RTC_HSE_DIV_45
  • LL_RCC_RTC_HSE_DIV_46
  • LL_RCC_RTC_HSE_DIV_47
  • LL_RCC_RTC_HSE_DIV_48
  • LL_RCC_RTC_HSE_DIV_49
  • LL_RCC_RTC_HSE_DIV_50
  • LL_RCC_RTC_HSE_DIV_51
  • LL_RCC_RTC_HSE_DIV_52
  • LL_RCC_RTC_HSE_DIV_53
  • LL_RCC_RTC_HSE_DIV_54
  • LL_RCC_RTC_HSE_DIV_55
  • LL_RCC_RTC_HSE_DIV_56
  • LL_RCC_RTC_HSE_DIV_57
  • LL_RCC_RTC_HSE_DIV_58
  • LL_RCC_RTC_HSE_DIV_59
  • LL_RCC_RTC_HSE_DIV_60
  • LL_RCC_RTC_HSE_DIV_61
  • LL_RCC_RTC_HSE_DIV_62
  • LL_RCC_RTC_HSE_DIV_63
Return values:
None

Definition at line 4055 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE
Return values:
None

Definition at line 3913 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM

Functions
TIM
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetTIMPrescaler (uint32_t Prescaler)
Set Timers Clock Prescalers.
__STATIC_INLINE uint32_t | LL_RCC_GetTIMPrescaler (void)
Get Timers Clock Prescalers.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler ( void )

Get Timers Clock Prescalers.

Reference Manual to LL API cross reference:
CFGR TIMPRE LL_RCC_GetTIMPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_TIM_PRESCALER_TWICE
  • LL_RCC_TIM_PRESCALER_FOUR_TIMES

Definition at line 4161 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetTIMPrescaler ( uint32_t Prescaler )

Set Timers Clock Prescalers.

Reference Manual to LL API cross reference:
CFGR TIMPRE LL_RCC_SetTIMPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_TIM_PRESCALER_TWICE
  • LL_RCC_TIM_PRESCALER_FOUR_TIMES
Return values:
None

Definition at line 4149 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_SetSource (uint32_t PLLSource)
Set the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE void | LL_RCC_PLL1_Enable (void)
Enable PLL1.
__STATIC_INLINE void | LL_RCC_PLL1_Disable (void)
Disable PLL1.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_IsReady (void)
Check if PLL1 Ready.
__STATIC_INLINE void | LL_RCC_PLL1P_Enable (void)
Enable PLL1P.
__STATIC_INLINE void | LL_RCC_PLL1Q_Enable (void)
Enable PLL1Q.
__STATIC_INLINE void | LL_RCC_PLL1R_Enable (void)
Enable PLL1R.
__STATIC_INLINE void | LL_RCC_PLL1FRACN_Enable (void)
Enable PLL1 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL1P_IsEnabled (void)
Check if PLL1 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1Q_IsEnabled (void)
Check if PLL1 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1R_IsEnabled (void)
Check if PLL1 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1FRACN_IsEnabled (void)
Check if PLL1 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL1P_Disable (void)
Disable PLL1P.
__STATIC_INLINE void | LL_RCC_PLL1Q_Disable (void)
Disable PLL1Q.
__STATIC_INLINE void | LL_RCC_PLL1R_Disable (void)
Disable PLL1R.
__STATIC_INLINE void | LL_RCC_PLL1FRACN_Disable (void)
Disable PLL1 FRACN.
__STATIC_INLINE void | LL_RCC_PLL1_SetVCOOutputRange (uint32_t VCORange)
Set PLL1 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL1_SetVCOInputRange (uint32_t InputRange)
Set PLL1 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetN (void)
Get PLL1 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetM (void)
Get PLL1 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetP (void)
Get PLL1 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetQ (void)
Get PLL1 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetR (void)
Get PLL1 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetFRACN (void)
Get PLL1 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetN (uint32_t N)
Set PLL1 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetM (uint32_t M)
Set PLL1 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetP (uint32_t P)
Set PLL1 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetQ (uint32_t Q)
Set PLL1 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetR (uint32_t R)
Set PLL1 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetFRACN (uint32_t FRACN)
Set PLL1 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_Enable (void)
Enable PLL2.
__STATIC_INLINE void | LL_RCC_PLL2_Disable (void)
Disable PLL2.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_IsReady (void)
Check if PLL2 Ready.
__STATIC_INLINE void | LL_RCC_PLL2P_Enable (void)
Enable PLL2P.
__STATIC_INLINE void | LL_RCC_PLL2Q_Enable (void)
Enable PLL2Q.
__STATIC_INLINE void | LL_RCC_PLL2R_Enable (void)
Enable PLL2R.
__STATIC_INLINE void | LL_RCC_PLL2FRACN_Enable (void)
Enable PLL2 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL2P_IsEnabled (void)
Check if PLL2 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2Q_IsEnabled (void)
Check if PLL2 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2R_IsEnabled (void)
Check if PLL2 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2FRACN_IsEnabled (void)
Check if PLL2 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL2P_Disable (void)
Disable PLL2P.
__STATIC_INLINE void | LL_RCC_PLL2Q_Disable (void)
Disable PLL2Q.
__STATIC_INLINE void | LL_RCC_PLL2R_Disable (void)
Disable PLL2R.
__STATIC_INLINE void | LL_RCC_PLL2FRACN_Disable (void)
Disable PLL2 FRACN.
__STATIC_INLINE void | LL_RCC_PLL2_SetVCOOutputRange (uint32_t VCORange)
Set PLL2 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL2_SetVCOInputRange (uint32_t InputRange)
Set PLL2 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetN (void)
Get PLL2 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetM (void)
Get PLL2 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetP (void)
Get PLL2 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetQ (void)
Get PLL2 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetR (void)
Get PLL2 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetFRACN (void)
Get PLL2 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetN (uint32_t N)
Set PLL2 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetM (uint32_t M)
Set PLL2 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetP (uint32_t P)
Set PLL2 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetQ (uint32_t Q)
Set PLL2 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetR (uint32_t R)
Set PLL2 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetFRACN (uint32_t FRACN)
Set PLL2 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_Enable (void)
Enable PLL3.
__STATIC_INLINE void | LL_RCC_PLL3_Disable (void)
Disable PLL3.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_IsReady (void)
Check if PLL3 Ready.
__STATIC_INLINE void | LL_RCC_PLL3P_Enable (void)
Enable PLL3P.
__STATIC_INLINE void | LL_RCC_PLL3Q_Enable (void)
Enable PLL3Q.
__STATIC_INLINE void | LL_RCC_PLL3R_Enable (void)
Enable PLL3R.
__STATIC_INLINE void | LL_RCC_PLL3FRACN_Enable (void)
Enable PLL3 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL3P_IsEnabled (void)
Check if PLL3 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3Q_IsEnabled (void)
Check if PLL3 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3R_IsEnabled (void)
Check if PLL3 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3FRACN_IsEnabled (void)
Check if PLL3 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL3P_Disable (void)
Disable PLL3P.
__STATIC_INLINE void | LL_RCC_PLL3Q_Disable (void)
Disable PLL3Q.
__STATIC_INLINE void | LL_RCC_PLL3R_Disable (void)
Disable PLL3R.
__STATIC_INLINE void | LL_RCC_PLL3FRACN_Disable (void)
Disable PLL3 FRACN.
__STATIC_INLINE void | LL_RCC_PLL3_SetVCOOutputRange (uint32_t VCORange)
Set PLL3 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL3_SetVCOInputRange (uint32_t InputRange)
Set PLL3 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetN (void)
Get PLL3 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetM (void)
Get PLL3 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetP (void)
Get PLL3 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetQ (void)
Get PLL3 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetR (void)
Get PLL3 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetFRACN (void)
Get PLL3 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetN (uint32_t N)
Set PLL3 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetM (uint32_t M)
Set PLL3 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetP (uint32_t P)
Set PLL3 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetQ (uint32_t Q)
Set PLL3 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetR (uint32_t R)
Set PLL3 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetFRACN (uint32_t FRACN)
Set PLL3 FRACN Coefficient.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL1_Disable ( void )

Disable PLL1.

Note:
Cannot be disabled if the PLL1 clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLL1ON LL_RCC_PLL1_Disable
Return values:
None

Definition at line 4256 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1_Enable ( void )

Enable PLL1.

Reference Manual to LL API cross reference:
CR PLL1ON LL_RCC_PLL1_Enable
Return values:
None

Definition at line 4245 of file stm32h7xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN ( void )

Get PLL1 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN
Return values:
A value between 0 and 8191 (0x1FFF)

Definition at line 4482 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM ( void )

Get PLL1 M Coefficient.

Reference Manual to LL API cross reference:
PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
Return values:
A value between 0 and 63

Definition at line 4442 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN ( void )

Get PLL1 N Coefficient.

Reference Manual to LL API cross reference:
PLL1DIVR N1 LL_RCC_PLL1_GetN
Return values:
A value between 4 and 512

Definition at line 4432 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP ( void )

Get PLL1 P Coefficient.

Reference Manual to LL API cross reference:
PLL1DIVR P1 LL_RCC_PLL1_GetP
Return values:
A value between 2 and 128

Definition at line 4452 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ ( void )

Get PLL1 Q Coefficient.

Reference Manual to LL API cross reference:
PLL1DIVR Q1 LL_RCC_PLL1_GetQ
Return values:
A value between 1 and 128

Definition at line 4462 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR ( void )

Get PLL1 R Coefficient.

Reference Manual to LL API cross reference:
PLL1DIVR R1 LL_RCC_PLL1_GetR
Return values:
A value between 1 and 128

Definition at line 4472 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady ( void )

Check if PLL1 Ready.

Reference Manual to LL API cross reference:
CR PLL1RDY LL_RCC_PLL1_IsReady
Return values:
State of bit (1 or 0).

Definition at line 4266 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_IsPLLsReady().

__STATIC_INLINE void LL_RCC_PLL1_SetFRACN ( uint32_t FRACN )

Set PLL1 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN
Parameters:
FRACN parameter can be a value between 0 and 8191 (0x1FFF)

Definition at line 4547 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1_SetM ( uint32_t M )

Set PLL1 M Coefficient.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
Parameters:
M parameter can be a value between 0 and 63

Definition at line 4504 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1_SetN ( uint32_t N )

Set PLL1 N Coefficient.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLL1DIVR N1 LL_RCC_PLL1_SetN
Parameters:
N parameter can be a value between 4 and 512

Definition at line 4493 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1_SetP ( uint32_t P )

Set PLL1 P Coefficient.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLL1DIVR P1 LL_RCC_PLL1_SetP
Parameters:
P parameter can be a value between 2 and 128 (ODD division factor not supportted)

Definition at line 4515 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1_SetQ ( uint32_t Q )

Set PLL1 Q Coefficient.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLL1DIVR Q1 LL_RCC_PLL1_SetQ
Parameters:
Q parameter can be a value between 1 and 128

Definition at line 4526 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1_SetR ( uint32_t R )

Set PLL1 R Coefficient.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLL1DIVR R1 LL_RCC_PLL1_SetR
Parameters:
R parameter can be a value between 1 and 128

Definition at line 4537 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange ( uint32_t InputRange )

Set PLL1 VCO Input Range.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
Parameters:
InputRange This parameter can be one of the following values:
  • LL_RCC_PLLINPUTRANGE_1_2
  • LL_RCC_PLLINPUTRANGE_2_4
  • LL_RCC_PLLINPUTRANGE_4_8
  • LL_RCC_PLLINPUTRANGE_8_16
Return values:
None

Definition at line 4422 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange ( uint32_t VCORange )

Set PLL1 VCO OutputRange.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
Parameters:
VCORange This parameter can be one of the following values:
  • LL_RCC_PLLVCORANGE_WIDE
  • LL_RCC_PLLVCORANGE_MEDIUM
Return values:
None

Definition at line 4406 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable ( void )

Disable PLL1 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
Return values:
None

Definition at line 4392 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable ( void )

Enable PLL1 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
Return values:
None

Definition at line 4309 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled ( void )

Check if PLL1 FRACN is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4349 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE void LL_RCC_PLL1P_Disable ( void )

Disable PLL1P.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable
Return values:
None

Definition at line 4360 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1P_Enable ( void )

Enable PLL1P.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable
Return values:
None

Definition at line 4277 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled ( void )

Check if PLL1 P is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4319 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE void LL_RCC_PLL1Q_Disable ( void )

Disable PLL1Q.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable
Return values:
None

Definition at line 4371 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1Q_Enable ( void )

Enable PLL1Q.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable
Return values:
None

Definition at line 4288 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled ( void )

Check if PLL1 Q is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4329 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE void LL_RCC_PLL1R_Disable ( void )

Disable PLL1R.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable
Return values:
None

Definition at line 4382 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL1R_Enable ( void )

Enable PLL1R.

Note:
This API shall be called only when PLL1 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable
Return values:
None

Definition at line 4299 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled ( void )

Check if PLL1 R is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4339 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq().

__STATIC_INLINE void LL_RCC_PLL2_Disable ( void )

Disable PLL2.

Note:
Cannot be disabled if the PLL2 clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLL2ON LL_RCC_PLL2_Disable
Return values:
None

Definition at line 4568 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_Enable ( void )

Enable PLL2.

Reference Manual to LL API cross reference:
CR PLL2ON LL_RCC_PLL2_Enable
Return values:
None

Definition at line 4557 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN ( void )

Get PLL2 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN
Return values:
A value between 0 and 8191 (0x1FFF)

Definition at line 4794 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM ( void )

Get PLL2 M Coefficient.

Reference Manual to LL API cross reference:
PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
Return values:
A value between 0 and 63

Definition at line 4754 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN ( void )

Get PLL2 N Coefficient.

Reference Manual to LL API cross reference:
PLL2DIVR N2 LL_RCC_PLL2_GetN
Return values:
A value between 4 and 512

Definition at line 4744 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP ( void )

Get PLL2 P Coefficient.

Reference Manual to LL API cross reference:
PLL2DIVR P2 LL_RCC_PLL2_GetP
Return values:
A value between 1 and 128

Definition at line 4764 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ ( void )

Get PLL2 Q Coefficient.

Reference Manual to LL API cross reference:
PLL2DIVR Q2 LL_RCC_PLL2_GetQ
Return values:
A value between 1 and 128

Definition at line 4774 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR ( void )

Get PLL2 R Coefficient.

Reference Manual to LL API cross reference:
PLL2DIVR R2 LL_RCC_PLL2_GetR
Return values:
A value between 1 and 128

Definition at line 4784 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady ( void )

Check if PLL2 Ready.

Reference Manual to LL API cross reference:
CR PLL2RDY LL_RCC_PLL2_IsReady
Return values:
State of bit (1 or 0).

Definition at line 4578 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSARTClockFreq(), and UTILS_IsPLLsReady().

__STATIC_INLINE void LL_RCC_PLL2_SetFRACN ( uint32_t FRACN )

Set PLL2 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN
Parameters:
FRACN parameter can be a value between 0 and 8191 (0x1FFF)

Definition at line 4859 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetM ( uint32_t M )

Set PLL2 M Coefficient.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
Parameters:
M parameter can be a value between 0 and 63

Definition at line 4816 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetN ( uint32_t N )

Set PLL2 N Coefficient.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLL2DIVR N2 LL_RCC_PLL2_SetN
Parameters:
N parameter can be a value between 4 and 512

Definition at line 4805 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetP ( uint32_t P )

Set PLL2 P Coefficient.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLL2DIVR P2 LL_RCC_PLL2_SetP
Parameters:
P parameter can be a value between 1 and 128

Definition at line 4827 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetQ ( uint32_t Q )

Set PLL2 Q Coefficient.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLL2DIVR Q2 LL_RCC_PLL2_SetQ
Parameters:
Q parameter can be a value between 1 and 128

Definition at line 4838 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetR ( uint32_t R )

Set PLL2 R Coefficient.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLL2DIVR R2 LL_RCC_PLL2_SetR
Parameters:
R parameter can be a value between 1 and 128

Definition at line 4849 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange ( uint32_t InputRange )

Set PLL2 VCO Input Range.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
Parameters:
InputRange This parameter can be one of the following values:
  • LL_RCC_PLLINPUTRANGE_1_2
  • LL_RCC_PLLINPUTRANGE_2_4
  • LL_RCC_PLLINPUTRANGE_4_8
  • LL_RCC_PLLINPUTRANGE_8_16
Return values:
None

Definition at line 4734 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange ( uint32_t VCORange )

Set PLL2 VCO OutputRange.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
Parameters:
VCORange This parameter can be one of the following values:
  • LL_RCC_PLLVCORANGE_WIDE
  • LL_RCC_PLLVCORANGE_MEDIUM
Return values:
None

Definition at line 4718 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable ( void )

Disable PLL2 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
Return values:
None

Definition at line 4704 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable ( void )

Enable PLL2 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
Return values:
None

Definition at line 4621 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled ( void )

Check if PLL2 FRACN is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4661 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE void LL_RCC_PLL2P_Disable ( void )

Disable PLL2P.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable
Return values:
None

Definition at line 4672 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2P_Enable ( void )

Enable PLL2P.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable
Return values:
None

Definition at line 4589 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled ( void )

Check if PLL2 P is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4631 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE void LL_RCC_PLL2Q_Disable ( void )

Disable PLL2Q.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable
Return values:
None

Definition at line 4683 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2Q_Enable ( void )

Enable PLL2Q.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable
Return values:
None

Definition at line 4600 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled ( void )

Check if PLL2 Q is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4641 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE void LL_RCC_PLL2R_Disable ( void )

Disable PLL2R.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable
Return values:
None

Definition at line 4694 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL2R_Enable ( void )

Enable PLL2R.

Note:
This API shall be called only when PLL2 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable
Return values:
None

Definition at line 4611 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled ( void )

Check if PLL2 R is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4651 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL2ClockFreq().

__STATIC_INLINE void LL_RCC_PLL3_Disable ( void )

Disable PLL3.

Note:
Cannot be disabled if the PLL3 clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLL3ON LL_RCC_PLL3_Disable
Return values:
None

Definition at line 4880 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_Enable ( void )

Enable PLL3.

Reference Manual to LL API cross reference:
CR PLL3ON LL_RCC_PLL3_Enable
Return values:
None

Definition at line 4869 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN ( void )

Get PLL3 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN
Return values:
A value between 0 and 8191 (0x1FFF)

Definition at line 5106 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM ( void )

Get PLL3 M Coefficient.

Reference Manual to LL API cross reference:
PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
Return values:
A value between 0 and 63

Definition at line 5066 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN ( void )

Get PLL3 N Coefficient.

Reference Manual to LL API cross reference:
PLL3DIVR N3 LL_RCC_PLL3_GetN
Return values:
A value between 4 and 512

Definition at line 5056 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP ( void )

Get PLL3 P Coefficient.

Reference Manual to LL API cross reference:
PLL3DIVR P3 LL_RCC_PLL3_GetP
Return values:
A value between 1 and 128

Definition at line 5076 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ ( void )

Get PLL3 Q Coefficient.

Reference Manual to LL API cross reference:
PLL3DIVR Q3 LL_RCC_PLL3_GetQ
Return values:
A value between 1 and 128

Definition at line 5086 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR ( void )

Get PLL3 R Coefficient.

Reference Manual to LL API cross reference:
PLL3DIVR R3 LL_RCC_PLL3_GetR
Return values:
A value between 1 and 128

Definition at line 5096 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady ( void )

Check if PLL3 Ready.

Reference Manual to LL API cross reference:
CR PLL3RDY LL_RCC_PLL3_IsReady
Return values:
State of bit (1 or 0).

Definition at line 4890 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and UTILS_IsPLLsReady().

__STATIC_INLINE void LL_RCC_PLL3_SetFRACN ( uint32_t FRACN )

Set PLL3 FRACN Coefficient.

Reference Manual to LL API cross reference:
PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN
Parameters:
FRACN parameter can be a value between 0 and 8191 (0x1FFF)

Definition at line 5171 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetM ( uint32_t M )

Set PLL3 M Coefficient.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
Parameters:
M parameter can be a value between 0 and 63

Definition at line 5128 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetN ( uint32_t N )

Set PLL3 N Coefficient.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLL3DIVR N3 LL_RCC_PLL3_SetN
Parameters:
N parameter can be a value between 4 and 512

Definition at line 5117 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetP ( uint32_t P )

Set PLL3 P Coefficient.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLL3DIVR P3 LL_RCC_PLL3_SetP
Parameters:
P parameter can be a value between 1 and 128

Definition at line 5139 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetQ ( uint32_t Q )

Set PLL3 Q Coefficient.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLL3DIVR Q3 LL_RCC_PLL3_SetQ
Parameters:
Q parameter can be a value between 1 and 128

Definition at line 5150 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetR ( uint32_t R )

Set PLL3 R Coefficient.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLL3DIVR R3 LL_RCC_PLL3_SetR
Parameters:
R parameter can be a value between 1 and 128

Definition at line 5161 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange ( uint32_t InputRange )

Set PLL3 VCO Input Range.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
Parameters:
InputRange This parameter can be one of the following values:
  • LL_RCC_PLLINPUTRANGE_1_2
  • LL_RCC_PLLINPUTRANGE_2_4
  • LL_RCC_PLLINPUTRANGE_4_8
  • LL_RCC_PLLINPUTRANGE_8_16
Return values:
None

Definition at line 5046 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange ( uint32_t VCORange )

Set PLL3 VCO OutputRange.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
Parameters:
VCORange This parameter can be one of the following values:
  • LL_RCC_PLLVCORANGE_WIDE
  • LL_RCC_PLLVCORANGE_MEDIUM
Return values:
None

Definition at line 5030 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable ( void )

Disable PLL3 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
Return values:
None

Definition at line 5016 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable ( void )

Enable PLL3 FRACN.

Reference Manual to LL API cross reference:
PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
Return values:
None

Definition at line 4933 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled ( void )

Check if PLL3 FRACN is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4973 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE void LL_RCC_PLL3P_Disable ( void )

Disable PLL3P.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable
Return values:
None

Definition at line 4984 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3P_Enable ( void )

Enable PLL3P.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable
Return values:
None

Definition at line 4901 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled ( void )

Check if PLL3 P is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4943 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE void LL_RCC_PLL3Q_Disable ( void )

Disable PLL3Q.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable
Return values:
None

Definition at line 4995 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3Q_Enable ( void )

Enable PLL3Q.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable
Return values:
None

Definition at line 4912 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled ( void )

Check if PLL3 Q is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4953 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE void LL_RCC_PLL3R_Disable ( void )

Disable PLL3R.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable
Return values:
None

Definition at line 5006 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL3R_Enable ( void )

Enable PLL3R.

Note:
This API shall be called only when PLL3 is disabled.
Reference Manual to LL API cross reference:
PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable
Return values:
None

Definition at line 4923 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled ( void )

Check if PLL3 R is enabled.

Reference Manual to LL API cross reference:
PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 4963 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_CSI
  • LL_RCC_PLLSOURCE_HSE
  • LL_RCC_PLLSOURCE_NONE

Definition at line 4235 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), and LL_RCC_GetPLL3ClockFreq().

__STATIC_INLINE void LL_RCC_PLL_SetSource ( uint32_t PLLSource )

Set the oscillator used as PLL clock source.

Note:
PLLSRC can be written only when All PLLs are disabled.
Reference Manual to LL API cross reference:
PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
Parameters:
PLLSource parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_CSI
  • LL_RCC_PLLSOURCE_HSE
  • LL_RCC_PLLSOURCE_NONE
Return values:
None

Definition at line 4221 of file stm32h7xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_CSIRDY (void)
Clear CSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL1RDY (void)
Clear PLL1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL2RDY (void)
Clear PLL2 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL3RDY (void)
Clear PLL3 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear HSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CSIRDY (void)
Check if CSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL1RDY (void)
Check if PLL1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL2RDY (void)
Check if PLL2 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL3RDY (void)
Check if PLL3 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if HSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power D1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDG1RST (void)
Check if RCC flag Window Watchdog 1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDG1RST (void)
Check if RCC flag Independent Watchdog 1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CDRST (void)
Check if RCC flag CD reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear all reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY ( void )

Clear CSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
Return values:
None

Definition at line 5231 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear HSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR HSECSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 5291 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 5221 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY ( void )

Clear HSI48 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Return values:
None

Definition at line 5241 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 5211 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS ( void )

Clear LSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Return values:
None

Definition at line 5281 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 5201 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 5191 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY ( void )

Clear PLL1 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
Return values:
None

Definition at line 5251 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY ( void )

Clear PLL2 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
Return values:
None

Definition at line 5261 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY ( void )

Clear PLL3 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
Return values:
None

Definition at line 5271 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear all reset flags.

Reference Manual to LL API cross reference:
RSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 5613 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST ( void )

Check if RCC flag BOR reset is set or not.

Reference Manual to LL API cross reference:
RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Return values:
State of bit (1 or 0).

Definition at line 5535 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST ( void )

Check if RCC flag CD reset is set or not.

Reference Manual to LL API cross reference:
RSR CDRSTF LL_RCC_IsActiveFlag_CDRST
Return values:
State of bit (1 or 0).

Definition at line 5558 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY ( void )

Check if CSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
Return values:
State of bit (1 or 0).

Definition at line 5341 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if HSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 5401 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 5331 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY ( void )

Check if HSI48 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 5351 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 5321 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST ( void )

Check if RCC flag Independent Watchdog 1 reset is set or not.

Reference Manual to LL API cross reference:
RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST
Return values:
State of bit (1 or 0).

Definition at line 5463 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power D1 reset is set or not.

Reference Manual to LL API cross reference:
RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)
RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**)

(*) Only available for single core devices (**) Only available for Dual core devices

Return values:
State of bit (1 or 0).

Definition at line 5415 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS ( void )

Check if LSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 5391 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 5311 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 5301 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 5525 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY ( void )

Check if PLL1 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY
Return values:
State of bit (1 or 0).

Definition at line 5361 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY ( void )

Check if PLL2 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
Return values:
State of bit (1 or 0).

Definition at line 5371 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY ( void )

Check if PLL3 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
Return values:
State of bit (1 or 0).

Definition at line 5381 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST ( void )

Check if RCC flag POR/PDR reset is set or not.

Reference Manual to LL API cross reference:
RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
Return values:
State of bit (1 or 0).

Definition at line 5515 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)
RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**)

(*) Only available for single core devices (**) Only available for Dual core devices

Return values:
State of bit (1 or 0).

Definition at line 5489 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST ( void )

Check if RCC flag Window Watchdog 1 reset is set or not.

Reference Manual to LL API cross reference:
RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST
Return values:
State of bit (1 or 0).

Definition at line 5441 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_CSIRDY (void)
Enable CSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL1RDY (void)
Enable PLL1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL2RDY (void)
Enable PLL2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL3RDY (void)
Enable PLL3 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSECSS interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_CSIRDY (void)
Disable CSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL1RDY (void)
Disable PLL1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL2RDY (void)
Disable PLL2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL3RDY (void)
Disable PLL3 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSECSS interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_CSIRDY (void)
Checks if CSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL1RDY (void)
Checks if PLL1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL2RDY (void)
Checks if PLL2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL3RDY (void)
Checks if PLL3 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY ( void )

Disable CSI ready interrupt.

Reference Manual to LL API cross reference:
CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
Return values:
None

Definition at line 6093 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 6083 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY ( void )

Disable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Return values:
None

Definition at line 6103 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 6073 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSECSS ( void )

Disable LSECSS interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Return values:
None

Definition at line 6143 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 6063 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 6053 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY ( void )

Disable PLL1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
Return values:
None

Definition at line 6113 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY ( void )

Disable PLL2 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
Return values:
None

Definition at line 6123 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY ( void )

Disable PLL3 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
Return values:
None

Definition at line 6133 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY ( void )

Enable CSI ready interrupt.

Reference Manual to LL API cross reference:
CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
Return values:
None

Definition at line 5993 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 5983 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY ( void )

Enable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Return values:
None

Definition at line 6003 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 5973 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSECSS ( void )

Enable LSECSS interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Return values:
None

Definition at line 6043 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 5963 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 5953 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY ( void )

Enable PLL1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
Return values:
None

Definition at line 6013 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY ( void )

Enable PLL2 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
Return values:
None

Definition at line 6023 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY ( void )

Enable PLL3 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
Return values:
None

Definition at line 6033 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY ( void )

Checks if CSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
Return values:
State of bit (1 or 0).

Definition at line 6193 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 6183 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY ( void )

Checks if HSI48 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 6203 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 6173 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS ( void )

Checks if LSECSS interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 6243 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 6163 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 6153 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY ( void )

Checks if PLL1 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
Return values:
State of bit (1 or 0).

Definition at line 6213 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY ( void )

Checks if PLL2 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
Return values:
State of bit (1 or 0).

Definition at line 6223 of file stm32h7xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY ( void )

Checks if PLL3 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
Return values:
State of bit (1 or 0).

Definition at line 6233 of file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

void LL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.

Function Documentation

void LL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL1, PLL2 and PLL3 OFF
  • AHB, APB Bus pre-scaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 116 of file stm32h7xx_ll_rcc.c.

References LL_RCC_HSI_IsReady(), LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), and LL_RCC_WriteReg.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
void | LL_RCC_GetPLL1ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL1 clocks frequencies.
void | LL_RCC_GetPLL2ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL2 clocks frequencies.
void | LL_RCC_GetPLL3ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL3 clocks frequencies.
uint32_t | LL_RCC_CalcPLLClockFreq (uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
Helper function to calculate the PLL frequency output.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUART clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADC clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMC clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNG clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USB clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetDFSDM2ClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetSPDIFClockFreq (uint32_t SPDIFxSource)
Return SPDIF clock frequency.
uint32_t | LL_RCC_GetSPIClockFreq (uint32_t SPIxSource)
Return SPIx clock frequency.
uint32_t | LL_RCC_GetSWPClockFreq (uint32_t SWPxSource)
Return SWP clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN clock frequency.
uint32_t | LL_RCC_GetFMCClockFreq (uint32_t FMCxSource)
Return FMC clock frequency.
uint32_t | LL_RCC_GetOSPIClockFreq (uint32_t OSPIxSource)
Return OSPI clock frequency.
uint32_t | LL_RCC_GetCLKPClockFreq (uint32_t CLKPxSource)
Return CLKP clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.

and different peripheral clocks available on the device.

Note:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in header file (default value 64 MHz) divider by HSIDIV, but the real value may vary depending on on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in header file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
(***) CSI_VALUE is a constant defined in header file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_CalcPLLClockFreq | ( | uint32_t | PLLInputFreq,
 |  | uint32_t | M,
 |  | uint32_t | N,
 |  | uint32_t | FRACN,
 |  | uint32_t | PQR
 | ) |  |

Helper function to calculate the PLL frequency output.

Note:
ex: LL_RCC_CalcPLLClockFreq (HSE_VALUE, LL_RCC_PLL1_GetM (), LL_RCC_PLL1_GetN (), LL_RCC_PLL1_GetFRACN (), LL_RCC_PLL1_GetP ());
Parameters:
PLLInputFreq | PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
M | Between 1 and 63
N | Between 4 and 512
FRACN | Between 0 and 0x1FFF
PQR | VCO output divider (P, Q or R) Between 1 and 128, except for PLL1P Odd value not allowed
Return values:
PLL1 clock frequency (in Hz)

Definition at line 496 of file stm32h7xx_ll_rcc.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADC clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
ADC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 911 of file stm32h7xx_ll_rcc.c.

References LL_RCC_ADC_CLKSOURCE_CLKP, LL_RCC_ADC_CLKSOURCE_PLL2P, LL_RCC_ADC_CLKSOURCE_PLL3R, LL_RCC_CLKP_CLKSOURCE, LL_RCC_GetADCClockSource(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LL_PLL_ClocksTypeDef::PLL_P_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

uint32_t LL_RCC_GetCECClockFreq ( uint32_t CECxSource )

Return CEC clock frequency.

Parameters:
CECxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
CEC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1042 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, LL_RCC_CEC_CLKSOURCE_CSI_DIV122, LL_RCC_CEC_CLKSOURCE_LSE, LL_RCC_CEC_CLKSOURCE_LSI, LL_RCC_CSI_IsReady(), LL_RCC_GetCECClockSource(), LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, and LSI_VALUE.

uint32_t LL_RCC_GetCLKPClockFreq ( uint32_t CLKPxSource )

Return CLKP clock frequency.

Parameters:
CLKPxSource This parameter can be one of the following values:
  • LL_RCC_CLKP_CLKSOURCE
Return values:
CLKP clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1614 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSE_VALUE, HSI_VALUE, LL_RCC_CLKP_CLKSOURCE_CSI, LL_RCC_CLKP_CLKSOURCE_HSE, LL_RCC_CLKP_CLKSOURCE_HSI, LL_RCC_CSI_IsReady(), LL_RCC_GetCLKPClockSource(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), and LL_RCC_PERIPH_FREQUENCY_NO.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetSPIClockFreq().

uint32_t LL_RCC_GetDFSDM2ClockFreq ( uint32_t DFSDMxSource )

Return DFSDM clock frequency.

Parameters:
DFSDMxSource This parameter can be one of the following values:
  • LL_RCC_DFSDM2_CLKSOURCE
Return values:
DFSDM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1160 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_DFSDM2_CLKSOURCE_PCLK4, LL_RCC_DFSDM2_CLKSOURCE_SYSCLK, LL_RCC_GetDFSDM2ClockSource(), LL_RCC_GetSysPrescaler(), LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK4ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetDFSDMClockFreq ( uint32_t DFSDMxSource )

Return DFSDM clock frequency.

Parameters:
DFSDMxSource This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE
Return values:
DFSDM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1130 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_DFSDM1_CLKSOURCE_PCLK2, LL_RCC_DFSDM1_CLKSOURCE_SYSCLK, LL_RCC_GetDFSDMClockSource(), LL_RCC_GetSysPrescaler(), LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetFDCANClockFreq ( uint32_t FDCANxSource )

Return FDCAN clock frequency.

Parameters:
FDCANxSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
FDCAN clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1426 of file stm32h7xx_ll_rcc.c.

References HSE_VALUE, LL_RCC_FDCAN_CLKSOURCE_HSE, LL_RCC_FDCAN_CLKSOURCE_PLL1Q, LL_RCC_FDCAN_CLKSOURCE_PLL2Q, LL_RCC_GetFDCANClockSource(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_HSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), and LL_PLL_ClocksTypeDef::PLL_Q_Frequency.

uint32_t LL_RCC_GetFMCClockFreq ( uint32_t FMCxSource )

Return FMC clock frequency.

Parameters:
FMCxSource This parameter can be one of the following values:
  • LL_RCC_FMC_CLKSOURCE
Return values:
FMC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1471 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CLKP_CLKSOURCE, LL_RCC_FMC_CLKSOURCE_CLKP, LL_RCC_FMC_CLKSOURCE_HCLK, LL_RCC_FMC_CLKSOURCE_PLL1Q, LL_RCC_FMC_CLKSOURCE_PLL2R, LL_RCC_GetCLKPClockFreq(), LL_RCC_GetFMCClockSource(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_PLL_ClocksTypeDef::PLL_Q_Frequency, LL_PLL_ClocksTypeDef::PLL_R_Frequency, RCC_GetHCLKClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C123_CLKSOURCE
  • LL_RCC_I2C4_CLKSOURCE
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 654 of file stm32h7xx_ll_rcc.c.

References assert_param, CSI_VALUE, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CSI_IsReady(), LL_RCC_GetI2CClockSource(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_I2C123_CLKSOURCE_CSI, LL_RCC_I2C123_CLKSOURCE_HSI, LL_RCC_I2C123_CLKSOURCE_PCLK1, LL_RCC_I2C123_CLKSOURCE_PLL3R, LL_RCC_I2C4_CLKSOURCE_CSI, LL_RCC_I2C4_CLKSOURCE_HSI, LL_RCC_I2C4_CLKSOURCE_PCLK4, LL_RCC_I2C4_CLKSOURCE_PLL3R, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL3_IsReady(), LL_PLL_ClocksTypeDef::PLL_R_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK4ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPTIMClockFreq ( uint32_t LPTIMxSource )

Return LPTIMx clock frequency.

Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
  • LL_RCC_LPTIM345_CLKSOURCE
Return values:
LPTIM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 714 of file stm32h7xx_ll_rcc.c.

References assert_param, IS_LL_RCC_LPTIM_CLKSOURCE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CLKP_CLKSOURCE, LL_RCC_GetCLKPClockFreq(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_LPTIM1_CLKSOURCE_CLKP, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM1_CLKSOURCE_PLL2P, LL_RCC_LPTIM1_CLKSOURCE_PLL3R, LL_RCC_LPTIM2_CLKSOURCE_CLKP, LL_RCC_LPTIM2_CLKSOURCE_LSE, LL_RCC_LPTIM2_CLKSOURCE_LSI, LL_RCC_LPTIM2_CLKSOURCE_PCLK4, LL_RCC_LPTIM2_CLKSOURCE_PLL2P, LL_RCC_LPTIM2_CLKSOURCE_PLL3R, LL_RCC_LPTIM345_CLKSOURCE_CLKP, LL_RCC_LPTIM345_CLKSOURCE_LSE, LL_RCC_LPTIM345_CLKSOURCE_LSI, LL_RCC_LPTIM345_CLKSOURCE_PCLK4, LL_RCC_LPTIM345_CLKSOURCE_PLL2P, LL_RCC_LPTIM345_CLKSOURCE_PLL3R, LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LSE_VALUE, LSI_VALUE, LL_PLL_ClocksTypeDef::PLL_P_Frequency, LL_PLL_ClocksTypeDef::PLL_R_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK4ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPUARTClockFreq ( uint32_t LPUARTxSource )

Return LPUART clock frequency.

Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
LPUART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 590 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSI_VALUE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CSI_IsReady(), LL_RCC_GetLPUARTClockSource(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_LPUART1_CLKSOURCE_CSI, LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_PCLK4, LL_RCC_LPUART1_CLKSOURCE_PLL2Q, LL_RCC_LPUART1_CLKSOURCE_PLL3Q, LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LSE_VALUE, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK4ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_LPUART_Init().

uint32_t LL_RCC_GetOSPIClockFreq ( uint32_t OSPIxSource )

Return OSPI clock frequency.

Parameters:
QSPIxSource This parameter can be one of the following values:
  • LL_RCC_OSPI_CLKSOURCE
Return values:
OSPI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1567 of file stm32h7xx_ll_rcc.c.

References LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CLKP_CLKSOURCE, LL_RCC_GetCLKPClockFreq(), LL_RCC_GetOSPIClockSource(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_OSPI_CLKSOURCE_CLKP, LL_RCC_OSPI_CLKSOURCE_HCLK, LL_RCC_OSPI_CLKSOURCE_PLL1Q, LL_RCC_OSPI_CLKSOURCE_PLL2R, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_PLL_ClocksTypeDef::PLL_Q_Frequency, LL_PLL_ClocksTypeDef::PLL_R_Frequency, RCC_GetHCLKClockFreq(), and RCC_GetSystemClockFreq().

void LL_RCC_GetPLL1ClockFreq ( LL_PLL_ClocksTypeDef * PLL_Clocks )

Return PLL1 clocks frequencies.

Note:
LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
Return values:
None

Definition at line 267 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSE_VALUE, HSI_VALUE, LL_RCC_CalcPLLClockFreq(), LL_RCC_CSI_IsReady(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_GetFRACN(), LL_RCC_PLL1_GetM(), LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetP(), LL_RCC_PLL1_GetQ(), LL_RCC_PLL1_GetR(), LL_RCC_PLL1FRACN_IsEnabled(), LL_RCC_PLL1P_IsEnabled(), LL_RCC_PLL1Q_IsEnabled(), LL_RCC_PLL1R_IsEnabled(), LL_RCC_PLL_GetSource(), LL_RCC_PLLSOURCE_CSI, LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLSOURCE_NONE, LL_PLL_ClocksTypeDef::PLL_P_Frequency, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSBClockFreq(), and RCC_GetSystemClockFreq().

void LL_RCC_GetPLL2ClockFreq ( LL_PLL_ClocksTypeDef * PLL_Clocks )

Return PLL2 clocks frequencies.

Note:
LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
Return values:
None

Definition at line 341 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSE_VALUE, HSI_VALUE, LL_RCC_CalcPLLClockFreq(), LL_RCC_CSI_IsReady(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL2_GetFRACN(), LL_RCC_PLL2_GetM(), LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetP(), LL_RCC_PLL2_GetQ(), LL_RCC_PLL2_GetR(), LL_RCC_PLL2FRACN_IsEnabled(), LL_RCC_PLL2P_IsEnabled(), LL_RCC_PLL2Q_IsEnabled(), LL_RCC_PLL2R_IsEnabled(), LL_RCC_PLL_GetSource(), LL_RCC_PLLSOURCE_CSI, LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLSOURCE_NONE, LL_PLL_ClocksTypeDef::PLL_P_Frequency, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetFMCClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetOSPIClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), and LL_RCC_GetUSARTClockFreq().

void LL_RCC_GetPLL3ClockFreq ( LL_PLL_ClocksTypeDef * PLL_Clocks )

Return PLL3 clocks frequencies.

Note:
LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
Return values:
None

Definition at line 415 of file stm32h7xx_ll_rcc.c.

References CSI_VALUE, HSE_VALUE, HSI_VALUE, LL_RCC_CalcPLLClockFreq(), LL_RCC_CSI_IsReady(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL3_GetFRACN(), LL_RCC_PLL3_GetM(), LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetP(), LL_RCC_PLL3_GetQ(), LL_RCC_PLL3_GetR(), LL_RCC_PLL3FRACN_IsEnabled(), LL_RCC_PLL3P_IsEnabled(), LL_RCC_PLL3Q_IsEnabled(), LL_RCC_PLL3R_IsEnabled(), LL_RCC_PLL_GetSource(), LL_RCC_PLLSOURCE_CSI, LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLSOURCE_NONE, LL_PLL_ClocksTypeDef::PLL_P_Frequency, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

uint32_t LL_RCC_GetRNGClockFreq ( uint32_t RNGxSource )

Return RNG clock frequency.

Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
RNG clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 991 of file stm32h7xx_ll_rcc.c.

References LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetRNGClockSource(), LL_RCC_HSI48_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_RNG_CLKSOURCE_HSI48, LL_RCC_RNG_CLKSOURCE_LSE, LL_RCC_RNG_CLKSOURCE_LSI, LL_RCC_RNG_CLKSOURCE_PLL1Q, LSE_VALUE, LSI_VALUE, and LL_PLL_ClocksTypeDef::PLL_Q_Frequency.

uint32_t LL_RCC_GetSAIClockFreq ( uint32_t SAIxSource )

Return SAIx clock frequency.

Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
  • LL_RCC_SAI23_CLKSOURCE (*)
  • LL_RCC_SAI2A_CLKSOURCE (*)
  • LL_RCC_SAI2B_CLKSOURCE (*)
  • LL_RCC_SAI4A_CLKSOURCE (*)
  • LL_RCC_SAI4B_CLKSOURCE (*)
Return values:
SAI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

(*) : Available on some STM32H7 lines only.

Definition at line 799 of file stm32h7xx_ll_rcc.c.

References assert_param, EXTERNAL_CLOCK_VALUE, IS_LL_RCC_SAI_CLKSOURCE, LL_RCC_CLKP_CLKSOURCE, LL_RCC_GetCLKPClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSAIClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LL_RCC_SAI1_CLKSOURCE_CLKP, LL_RCC_SAI1_CLKSOURCE_I2S_CKIN, LL_RCC_SAI1_CLKSOURCE_PLL1Q, LL_RCC_SAI1_CLKSOURCE_PLL2P, LL_RCC_SAI1_CLKSOURCE_PLL3P, LL_RCC_SAI2A_CLKSOURCE_CLKP, LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN, LL_RCC_SAI2A_CLKSOURCE_PLL1Q, LL_RCC_SAI2A_CLKSOURCE_PLL2P, LL_RCC_SAI2A_CLKSOURCE_PLL3P, LL_RCC_SAI2B_CLKSOURCE_CLKP, LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN, LL_RCC_SAI2B_CLKSOURCE_PLL1Q, LL_RCC_SAI2B_CLKSOURCE_PLL2P, LL_RCC_SAI2B_CLKSOURCE_PLL3P, LL_PLL_ClocksTypeDef::PLL_P_Frequency, and LL_PLL_ClocksTypeDef::PLL_Q_Frequency.

uint32_t LL_RCC_GetSDMMCClockFreq ( uint32_t SDMMCxSource )

Return SDMMC clock frequency.

Parameters:
SDMMCxSource This parameter can be one of the following values:
  • LL_RCC_SDMMC_CLKSOURCE
Return values:
SDMMC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 953 of file stm32h7xx_ll_rcc.c.

References LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetSDMMCClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_RCC_SDMMC_CLKSOURCE_PLL1Q, LL_RCC_SDMMC_CLKSOURCE_PLL2R, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

uint32_t LL_RCC_GetSPDIFClockFreq ( uint32_t SPDIFxSource )

Return SPDIF clock frequency.

Parameters:
SPDIFxSource This parameter can be one of the following values:
  • LL_RCC_SPDIF_CLKSOURCE
Return values:
SPDIF clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1229 of file stm32h7xx_ll_rcc.c.

References HSI_VALUE, LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPDIFClockSource(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LL_RCC_SPDIF_CLKSOURCE_HSI, LL_RCC_SPDIF_CLKSOURCE_PLL1Q, LL_RCC_SPDIF_CLKSOURCE_PLL2R, LL_RCC_SPDIF_CLKSOURCE_PLL3R, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, and LL_PLL_ClocksTypeDef::PLL_R_Frequency.

uint32_t LL_RCC_GetSPIClockFreq ( uint32_t SPIxSource )

Return SPIx clock frequency.

Parameters:
SPIxSource This parameter can be one of the following values:
  • LL_RCC_SPI123_CLKSOURCE
  • LL_RCC_SPI45_CLKSOURCE
  • LL_RCC_SPI6_CLKSOURCE
Return values:
SPI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1284 of file stm32h7xx_ll_rcc.c.

References assert_param, CSI_VALUE, EXTERNAL_CLOCK_VALUE, HSE_VALUE, HSI_VALUE, IS_LL_RCC_SPI_CLKSOURCE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CLKP_CLKSOURCE, LL_RCC_CSI_IsReady(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPIClockSource(), LL_RCC_GetSysPrescaler(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LL_RCC_SPI123_CLKSOURCE_CLKP, LL_RCC_SPI123_CLKSOURCE_I2S_CKIN, LL_RCC_SPI123_CLKSOURCE_PLL1Q, LL_RCC_SPI123_CLKSOURCE_PLL2P, LL_RCC_SPI123_CLKSOURCE_PLL3P, LL_RCC_SPI45_CLKSOURCE_CSI, LL_RCC_SPI45_CLKSOURCE_HSE, LL_RCC_SPI45_CLKSOURCE_HSI, LL_RCC_SPI45_CLKSOURCE_PCLK2, LL_RCC_SPI45_CLKSOURCE_PLL2Q, LL_RCC_SPI45_CLKSOURCE_PLL3Q, LL_RCC_SPI6_CLKSOURCE_CSI, LL_RCC_SPI6_CLKSOURCE_HSE, LL_RCC_SPI6_CLKSOURCE_HSI, LL_RCC_SPI6_CLKSOURCE_I2S_CKIN, LL_RCC_SPI6_CLKSOURCE_PCLK4, LL_RCC_SPI6_CLKSOURCE_PLL2Q, LL_RCC_SPI6_CLKSOURCE_PLL3Q, LL_PLL_ClocksTypeDef::PLL_P_Frequency, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetPCLK4ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_I2S_Init().

uint32_t LL_RCC_GetSWPClockFreq ( uint32_t SWPxSource )

Return SWP clock frequency.

Parameters:
SWPxSource This parameter can be one of the following values:
  • LL_RCC_SWP_CLKSOURCE
Return values:
SWP clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 1394 of file stm32h7xx_ll_rcc.c.

References HSI_VALUE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_GetSWPClockSource(), LL_RCC_GetSysPrescaler(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_SWP_CLKSOURCE_HSI, LL_RCC_SWP_CLKSOURCE_PCLK1, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 241 of file stm32h7xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, LL_RCC_ClocksTypeDef::PCLK3_Frequency, LL_RCC_ClocksTypeDef::PCLK4_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetPCLK3ClockFreq(), RCC_GetPCLK4ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_LPTIM_Disable().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART16_CLKSOURCE
  • LL_RCC_USART234578_CLKSOURCE
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 515 of file stm32h7xx_ll_rcc.c.

References assert_param, CSI_VALUE, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CSI_IsReady(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSysPrescaler(), LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL2_IsReady(), LL_RCC_PLL3_IsReady(), LL_RCC_USART16_CLKSOURCE_CSI, LL_RCC_USART16_CLKSOURCE_HSI, LL_RCC_USART16_CLKSOURCE_LSE, LL_RCC_USART16_CLKSOURCE_PCLK2, LL_RCC_USART16_CLKSOURCE_PLL2Q, LL_RCC_USART16_CLKSOURCE_PLL3Q, LL_RCC_USART234578_CLKSOURCE_CSI, LL_RCC_USART234578_CLKSOURCE_HSI, LL_RCC_USART234578_CLKSOURCE_LSE, LL_RCC_USART234578_CLKSOURCE_PCLK1, LL_RCC_USART234578_CLKSOURCE_PLL2Q, LL_RCC_USART234578_CLKSOURCE_PLL3Q, LSE_VALUE, LL_PLL_ClocksTypeDef::PLL_Q_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USB clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled

Definition at line 1084 of file stm32h7xx_ll_rcc.c.

References HSI48_VALUE, LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetUSBClockSource(), LL_RCC_HSI48_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL1_IsReady(), LL_RCC_PLL3_IsReady(), LL_RCC_USB_CLKSOURCE_DISABLE, LL_RCC_USB_CLKSOURCE_HSI48, LL_RCC_USB_CLKSOURCE_PLL1Q, LL_RCC_USB_CLKSOURCE_PLL3Q, and LL_PLL_ClocksTypeDef::PLL_Q_Frequency.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC

Modules | Defines | Variables
RCC
STM32H7xx_LL_Driver

Modules

RCC Private functions
RCC Private Variables
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions

Defines

#define | CDCCIP 0x0UL
#define | CDCCIP1 0x4UL
#define | CDCCIP2 0x8UL
#define | SRDCCIP 0xCUL
#define | LL_RCC_REG_SHIFT 0U
#define | LL_RCC_POS_SHIFT 8U
#define | LL_RCC_CONFIG_SHIFT 16U
#define | LL_RCC_MASK_SHIFT 24U
#define | LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
#define | LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define | LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define | LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
#define | LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__)

Variables

const uint8_t | LL_RCC_PrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Define Documentation

#define CDCCIP 0x0UL

Definition at line 68 of file stm32h7xx_ll_rcc.h.

#define CDCCIP1 0x4UL

Definition at line 69 of file stm32h7xx_ll_rcc.h.

#define CDCCIP2 0x8UL

Definition at line 70 of file stm32h7xx_ll_rcc.h.

#define LL_CLKSOURCE | ( | __REG__,
 |  | __MSK__,
 |  | __POS__,
 |  | __CLK__
 | ) |
Value:
((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))

Definition at line 93 of file stm32h7xx_ll_rcc.h.

#define LL_CLKSOURCE_CONFIG ( __CLKSOURCE__ ) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))

Definition at line 89 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_SetClockSource().

#define LL_CLKSOURCE_MASK ( __CLKSOURCE__ ) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))

Definition at line 87 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetClockSource(), and LL_RCC_SetClockSource().

#define LL_CLKSOURCE_REG ( __CLKSOURCE__ ) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)

Definition at line 91 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetClockSource(), and LL_RCC_SetClockSource().

#define LL_CLKSOURCE_SHIFT ( __CLKSOURCE__ ) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)

Definition at line 85 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetClockSource().

#define LL_RCC_CONFIG_SHIFT 16U

Definition at line 82 of file stm32h7xx_ll_rcc.h.

Referenced by LL_RCC_GetClockSource().

#define LL_RCC_MASK_SHIFT 24U

Definition at line 83 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_POS_SHIFT 8U

Definition at line 81 of file stm32h7xx_ll_rcc.h.

#define LL_RCC_REG_SHIFT 0U

Definition at line 80 of file stm32h7xx_ll_rcc.h.

#define SRDCCIP 0xCUL

Definition at line 71 of file stm32h7xx_ll_rcc.h.

Variable Documentation

const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 42 of file stm32h7xx_ll_rcc.c.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RNG_InitTypeDef Struct Reference
RNG Exported Init structures

LL RNG Init Structure Definition. More...

#include <stm32h7xx_ll_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

LL RNG Init Structure Definition.

Definition at line 56 of file stm32h7xx_ll_rng.h.

Field Documentation

uint32_t LL_RNG_InitTypeDef::ClockErrorDetection

Clock error detection. This parameter can be one value of Clock Error Detection.

This parameter can be modified using unitary functions LL_RNG_EnableClkErrorDetect().

Definition at line 58 of file stm32h7xx_ll_rng.h.

Referenced by LL_RNG_Init(), and LL_RNG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rng.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Error Detection

Defines
Clock Error Detection
RNG Exported Constants

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define LL_RNG_CED_DISABLE RNG_CR_CED

Clock error detection disabled

Definition at line 77 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CED_ENABLE 0x00000000U

Clock error detection enabled

Definition at line 76 of file stm32h7xx_ll_rng.h.

Referenced by LL_RNG_StructInit().

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Value used to configure an internal

Defines
Value used to configure an internal
RNG Exported Constants

programmable divider acting on the incoming RNG clock More...

Defines

#define | LL_RNG_CLKDIV_BY_1 (0x00000000UL)
#define | LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
#define | LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
#define | LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
#define | LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

Detailed Description

programmable divider acting on the incoming RNG clock

Define Documentation

#define LL_RNG_CLKDIV_BY_1 (0x00000000UL)

No clock division

Definition at line 87 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)

1024 RNG clock cycles per internal RNG clock

Definition at line 97 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

128 RNG clock cycles per internal RNG clock

Definition at line 94 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)

16 RNG clock cycles per internal RNG clock

Definition at line 91 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

16384 RNG clock cycles per internal RNG clock

Definition at line 101 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)

2 RNG clock cycles per internal RNG clock

Definition at line 88 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

2048 RNG clock cycles per internal RNG clock

Definition at line 98 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)

256 RNG clock cycles per internal RNG clock

Definition at line 95 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

32 RNG clock cycles per internal RNG clock

Definition at line 92 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

32768 RNG clock cycles per internal RNG clock

Definition at line 102 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)

4 RNG clock cycles per internal RNG clock

Definition at line 89 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)

4096 RNG clock cycles per internal RNG clock

Definition at line 99 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)

512 RNG clock cycles per internal RNG clock

Definition at line 96 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

64 RNG clock cycles per internal RNG clock

Definition at line 93 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

8 RNG clock cycles per internal RNG clock

Definition at line 90 of file stm32h7xx_ll_rng.h.

#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

8192 RNG clock cycles per internal RNG clock

Definition at line 100 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NIST Compliance configuration

Defines
NIST Compliance configuration
RNG Exported Constants

Defines

#define | LL_RNG_NIST_COMPLIANT (0x00000000UL)
#define | LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)

Define Documentation

#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)

Custom NIST configuration

Definition at line 111 of file stm32h7xx_ll_rng.h.

#define LL_RNG_NIST_COMPLIANT (0x00000000UL)

Default NIST compliant configuration

Definition at line 110 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RNG Exported Constants

Flags defines which can be used with LL_RNG_ReadReg function. More...

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS

Detailed Description

Flags defines which can be used with LL_RNG_ReadReg function.

Define Documentation

#define LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

Definition at line 123 of file stm32h7xx_ll_rng.h.

#define LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

Definition at line 125 of file stm32h7xx_ll_rng.h.

#define LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

Definition at line 122 of file stm32h7xx_ll_rng.h.

#define LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

Definition at line 124 of file stm32h7xx_ll_rng.h.

#define LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Definition at line 126 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
RNG Exported Constants

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros. More...

Defines

#define LL_RNG_CR_IE RNG_CR_IE

Detailed Description

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Define Documentation

#define LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable

Definition at line 135 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RNG Exported Macros

Defines

#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Define Documentation

#define LL_RNG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 168 of file stm32h7xx_ll_rng.h.

#define LL_RNG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 160 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Configuration functions

Functions
RNG Configuration functions
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.
__STATIC_INLINE void | LL_RNG_EnableCondReset (RNG_TypeDef *RNGx)
Set RNG Conditioning Soft Reset bit.
__STATIC_INLINE void | LL_RNG_DisableCondReset (RNG_TypeDef *RNGx)
Reset RNG Conditioning Soft Reset bit.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledCondReset (RNG_TypeDef *RNGx)
Check if RNG Conditioning Soft Reset bit is set.
__STATIC_INLINE void | LL_RNG_ConfigLock (RNG_TypeDef *RNGx)
Enable RNG Config Lock.
__STATIC_INLINE uint32_t | LL_RNG_IsConfigLocked (RNG_TypeDef *RNGx)
Check if RNG Config Lock is enabled.
__STATIC_INLINE void | LL_RNG_EnableNistCompliance (RNG_TypeDef *RNGx)
Enable NIST Compliance.
__STATIC_INLINE void | LL_RNG_DisableNistCompliance (RNG_TypeDef *RNGx)
Disable NIST Compliance.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledNistCompliance (RNG_TypeDef *RNGx)
Check if NIST Compliance is enabled.
__STATIC_INLINE void | LL_RNG_SetConfig1 (RNG_TypeDef *RNGx, uint32_t Config1)
Set RNG Config1 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig1 (RNG_TypeDef *RNGx)
Get RNG Config1 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetConfig2 (RNG_TypeDef *RNGx, uint32_t Config2)
Set RNG Config2 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig2 (RNG_TypeDef *RNGx)
Get RNG Config2 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetConfig3 (RNG_TypeDef *RNGx, uint32_t Config3)
Set RNG Config3 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig3 (RNG_TypeDef *RNGx)
Get RNG Config3 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetClockDivider (RNG_TypeDef *RNGx, uint32_t Divider)
Set RNG Clock divider factor.
__STATIC_INLINE uint32_t | LL_RNG_GetClockDivider (RNG_TypeDef *RNGx)
Get RNG Clock divider factor.

Function Documentation

__STATIC_INLINE void LL_RNG_ConfigLock ( RNG_TypeDef * RNGx )

Enable RNG Config Lock.

Reference Manual to LL API cross reference:
CR CONFIGLOCK LL_RNG_ConfigLock
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 292 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Disable ( RNG_TypeDef * RNGx )

Disable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Disable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 203 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableClkErrorDetect ( RNG_TypeDef * RNGx )

Disable RNG Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_DisableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 236 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableCondReset ( RNG_TypeDef * RNGx )

Reset RNG Conditioning Soft Reset bit.

Reference Manual to LL API cross reference:
CR CONDRST LL_RNG_DisableCondReset
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 270 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableNistCompliance ( RNG_TypeDef * RNGx )

Disable NIST Compliance.

Reference Manual to LL API cross reference:
CR NISTC LL_RNG_DisableNistCompliance
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 325 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Enable ( RNG_TypeDef * RNGx )

Enable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Enable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 192 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableClkErrorDetect ( RNG_TypeDef * RNGx )

Enable Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_EnableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 225 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableCondReset ( RNG_TypeDef * RNGx )

Set RNG Conditioning Soft Reset bit.

Reference Manual to LL API cross reference:
CR CONDRST LL_RNG_EnableCondReset
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 259 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableNistCompliance ( RNG_TypeDef * RNGx )

Enable NIST Compliance.

Reference Manual to LL API cross reference:
CR NISTC LL_RNG_EnableNistCompliance
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 314 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_GetClockDivider ( RNG_TypeDef * RNGx )

Get RNG Clock divider factor.

Reference Manual to LL API cross reference:
CR CLKDIV LL_RNG_GetClockDivider
Parameters:
RNGx RNG Instance
Return values:
Returned value can be one of the following values:
  • LL_RNG_CLKDIV_BY_1
  • LL_RNG_CLKDIV_BY_2
  • LL_RNG_CLKDIV_BY_4
  • LL_RNG_CLKDIV_BY_8
  • LL_RNG_CLKDIV_BY_16
  • LL_RNG_CLKDIV_BY_32
  • LL_RNG_CLKDIV_BY_64
  • LL_RNG_CLKDIV_BY_128
  • LL_RNG_CLKDIV_BY_256
  • LL_RNG_CLKDIV_BY_512
  • LL_RNG_CLKDIV_BY_1024
  • LL_RNG_CLKDIV_BY_2048
  • LL_RNG_CLKDIV_BY_4096
  • LL_RNG_CLKDIV_BY_8192
  • LL_RNG_CLKDIV_BY_16384
  • LL_RNG_CLKDIV_BY_32768

Definition at line 460 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_GetConfig1 ( RNG_TypeDef * RNGx )

Get RNG Config1 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG1 LL_RNG_GetConfig1
Parameters:
RNGx RNG Instance
Return values:
Returned Value expressed on 6 bits : Value between 0 and 0x3F

Definition at line 359 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_GetConfig2 ( RNG_TypeDef * RNGx )

Get RNG Config2 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG2 LL_RNG_GetConfig2
Parameters:
RNGx RNG Instance
Return values:
Returned Value expressed on 3 bits : Value between 0 and 0x7

Definition at line 382 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_GetConfig3 ( RNG_TypeDef * RNGx )

Get RNG Config3 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG3 LL_RNG_GetConfig3
Parameters:
RNGx RNG Instance
Return values:
Returned Value expressed on 4 bits : Value between 0 and 0xF

Definition at line 405 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked ( RNG_TypeDef * RNGx )

Check if RNG Config Lock is enabled.

Reference Manual to LL API cross reference:
CR CONFIGLOCK LL_RNG_IsConfigLocked
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 303 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabled ( RNG_TypeDef * RNGx )

Check if Random Number Generator is enabled.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_IsEnabled
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 214 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect ( RNG_TypeDef * RNGx )

Check if RNG Clock Error Detection is enabled.

Reference Manual to LL API cross reference:
CR CED LL_RNG_IsEnabledClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 247 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset ( RNG_TypeDef * RNGx )

Check if RNG Conditioning Soft Reset bit is set.

Reference Manual to LL API cross reference:
CR CONDRST LL_RNG_IsEnabledCondReset
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 281 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance ( RNG_TypeDef * RNGx )

Check if NIST Compliance is enabled.

Reference Manual to LL API cross reference:
CR NISTC LL_RNG_IsEnabledNistCompliance
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 336 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_SetClockDivider | ( | RNG_TypeDef * | RNGx,
 |  | uint32_t | Divider
 | ) |  |

Set RNG Clock divider factor.

Reference Manual to LL API cross reference:
CR CLKDIV LL_RNG_SetClockDivider
Parameters:
RNGx RNG Instance
Divider can be one of the following values:
  • LL_RNG_CLKDIV_BY_1
  • LL_RNG_CLKDIV_BY_2
  • LL_RNG_CLKDIV_BY_4
  • LL_RNG_CLKDIV_BY_8
  • LL_RNG_CLKDIV_BY_16
  • LL_RNG_CLKDIV_BY_32
  • LL_RNG_CLKDIV_BY_64
  • LL_RNG_CLKDIV_BY_128
  • LL_RNG_CLKDIV_BY_256
  • LL_RNG_CLKDIV_BY_512
  • LL_RNG_CLKDIV_BY_1024
  • LL_RNG_CLKDIV_BY_2048
  • LL_RNG_CLKDIV_BY_4096
  • LL_RNG_CLKDIV_BY_8192
  • LL_RNG_CLKDIV_BY_16384
  • LL_RNG_CLKDIV_BY_32768
Return values:
None

Definition at line 433 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_SetConfig1 | ( | RNG_TypeDef * | RNGx,
 |  | uint32_t | Config1
 | ) |  |

Set RNG Config1 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG1 LL_RNG_SetConfig1
Parameters:
RNGx | RNG Instance
Config1 | Value between 0 and 0x3F
Return values:
None

Definition at line 348 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_SetConfig2 | ( | RNG_TypeDef * | RNGx,
 |  | uint32_t | Config2
 | ) |  |

Set RNG Config2 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG2 LL_RNG_SetConfig2
Parameters:
RNGx | RNG Instance
Config2 | Value between 0 and 0x7
Return values:
None

Definition at line 371 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_SetConfig3 | ( | RNG_TypeDef * | RNGx,
 |  | uint32_t | Config3
 | ) |  |

Set RNG Config3 Configuration field value.

Reference Manual to LL API cross reference:
CR RNG_CONFIG3 LL_RNG_SetConfig3
Parameters:
RNGx | RNG Instance
Config3 | Value between 0 and 0xF
Return values:
None

Definition at line 394 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG Management

Functions
FLAG Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.

Function Documentation

__STATIC_INLINE void LL_RNG_ClearFlag_CEIS ( RNG_TypeDef * RNGx )

Clear Clock Error interrupt Status (CEIS) Flag.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_ClearFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 534 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_ClearFlag_SEIS ( RNG_TypeDef * RNGx )

Clear Seed Error interrupt Status (SEIS) Flag.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_ClearFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 545 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CECS LL_RNG_IsActiveFlag_CECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 490 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_IsActiveFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 512 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY ( RNG_TypeDef * RNGx )

Indicate if the RNG Data ready Flag is set or not.

Reference Manual to LL API cross reference:
SR DRDY LL_RNG_IsActiveFlag_DRDY
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 479 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SECS LL_RNG_IsActiveFlag_SECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 501 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_IsActiveFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 523 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Management

Functions
IT Management
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Function Documentation

__STATIC_INLINE void LL_RNG_DisableIT ( RNG_TypeDef * RNGx )

Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_DisableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 577 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableIT ( RNG_TypeDef * RNGx )

Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_EnableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 565 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT ( RNG_TypeDef * RNGx )

Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_IsEnabledIT
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 589 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Management

Functions
Data Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 ( RNG_TypeDef * RNGx )

Return32-bit Random Number value.

Reference Manual to LL API cross reference:
DR RNDATA LL_RNG_ReadRandData32
Parameters:
RNGx RNG Instance
Return values:
Generated 32-bit random value

Definition at line 608 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Health Test Control

Functions
Health Test Control
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_SetHealthConfig (RNG_TypeDef *RNGx, uint32_t HTCFG)
Set RNG Health Test Control.
__STATIC_INLINE uint32_t | LL_RNG_GetHealthConfig (RNG_TypeDef *RNGx)
Get RNG Health Test Control.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig ( RNG_TypeDef * RNGx )

Get RNG Health Test Control.

Reference Manual to LL API cross reference:
HTCR HTCFG LL_RNG_GetHealthConfig
Parameters:
RNGx RNG Instance
Return values:
Return 32-bit RNG Health Test configuration

Definition at line 640 of file stm32h7xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_SetHealthConfig | ( | RNG_TypeDef * | RNGx,
 |  | uint32_t | HTCFG
 | ) |  |

Set RNG Health Test Control.

Reference Manual to LL API cross reference:
HTCR HTCFG LL_RNG_SetHealthConfig
Parameters:
RNGx | RNG Instance
HTCFG | can be values of 32 bits
Return values:
None

Definition at line 629 of file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_RNG_DeInit ( RNG_TypeDef * RNGx )

De-initialize RNG registers (Registers restored to their default values).

Parameters:
RNGx RNG Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are de-initialized
  • ERROR: not applicable

Definition at line 85 of file stm32h7xx_ll_rng.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_RNG, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_RNG_Init | ( | RNG_TypeDef * | RNGx,
 |  | LL_RNG_InitTypeDef * | RNG_InitStruct
 | ) |  |

Initialize RNG registers according to the specified parameters in RNG_InitStruct.

Parameters:
RNGx | RNG Instance
RNG_InitStruct | pointer to a LL_RNG_InitTypeDef structure that contains the configuration information for the specified RNG peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are initialized according to RNG_InitStruct content
  • ERROR: not applicable

Definition at line 106 of file stm32h7xx_ll_rng.c.

References assert_param, LL_RNG_InitTypeDef::ClockErrorDetection, and IS_LL_RNG_CED.

void LL_RNG_StructInit ( LL_RNG_InitTypeDef * RNG_InitStruct )

Set each LL_RNG_InitTypeDef field to default value.

Parameters:
RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 131 of file stm32h7xx_ll_rng.c.

References LL_RNG_InitTypeDef::ClockErrorDetection, and LL_RNG_CED_ENABLE.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG_LL_Private_Macros

Defines
RNG_LL_Private_Macros
RNG

Defines

#define | IS_LL_RNG_CED(__MODE__)
#define | IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu)
#define | IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__)
#define | IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
#define | IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
#define | IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

Define Documentation

#define IS_LL_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == LL_RNG_CED_ENABLE) || \
                                 ((__MODE__) == LL_RNG_CED_DISABLE))

Definition at line 48 of file stm32h7xx_ll_rng.c.

Referenced by LL_RNG_Init().

#define IS_LL_RNG_CLOCK_DIVIDER ( __CLOCK_DIV__ ) ((__CLOCK_DIV__) <=0x0Fu)

Definition at line 52 of file stm32h7xx_ll_rng.c.

#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)

Definition at line 58 of file stm32h7xx_ll_rng.c.

#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)

Definition at line 60 of file stm32h7xx_ll_rng.c.

#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

Definition at line 62 of file stm32h7xx_ll_rng.c.

#define IS_LL_RNG_NIST_COMPLIANCE ( __NIST_COMPLIANCE__ )
Value:
(((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
                                                     ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))

Definition at line 55 of file stm32h7xx_ll_rng.c.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE 0xFFU
#define | RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
#define | RTC_WRITE_PROTECTION_ENABLE_2 0x53U
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU

Definition at line 47 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 51 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_LL_INIT_MASK 0xFFFFFFFFU

Definition at line 48 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_EnableInitMode().

#define RTC_LL_RSF_MASK 0xFFFFFF5FU

Definition at line 49 of file stm32h7xx_ll_rtc.h.

#define RTC_OFFSET_DAY 16U

Definition at line 58 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR 16U

Definition at line 60 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE 8U

Definition at line 61 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH 8U

Definition at line 59 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY 24U

Definition at line 57 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU

Definition at line 48 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 52 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE 0xFFU

Definition at line 52 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU

Definition at line 53 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U

Definition at line 54 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 120 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 105 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 123 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 112 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FU)

Definition at line 65 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))

Definition at line 88 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 69 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 75 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 76 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 62 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 77 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))

Definition at line 90 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 78 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FFFU)

Definition at line 67 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 72 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 80 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 103 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32h7xx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 86 of file stm32h7xx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 94 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 88 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 100 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32h7xx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 110 of file stm32h7xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 117 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 123 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 128 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 112 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32h7xx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 137 of file stm32h7xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 149 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 144 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 139 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 154 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32h7xx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 163 of file stm32h7xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 181 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 174 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 167 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 165 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_rtc.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U

Define Documentation

#define LL_RTC_FORMAT_BCD 0x00000001U

BCD data format

Definition at line 209 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN 0x00000000U

Binary data format

Definition at line 208 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm A Date is selected

Definition at line 217 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 218 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm B Date is selected

Definition at line 226 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 227 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_ICSR_INITF RTC_ICSR_INITF

Definition at line 249 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ICSR_INITS RTC_ICSR_INITS

Definition at line 251 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF

Definition at line 248 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ICSR_RSF RTC_ICSR_RSF

Definition at line 250 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF

Definition at line 252 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF

Definition at line 253 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF

Definition at line 244 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF

Definition at line 243 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_ITSF RTC_SCR_CITSF

Definition at line 239 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_TSF RTC_SCR_CTSF

Definition at line 241 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF

Definition at line 240 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF

Definition at line 242 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 285 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 284 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 282 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 283 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
#define | LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
#define | LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
#define | LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
#define | LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
#define | LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
#define | LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05

Friday

Definition at line 309 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01

Monday

Definition at line 305 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06

Saturday

Definition at line 310 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07

Sunday

Definition at line 311 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04

Thrusday

Definition at line 308 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02

Tuesday

Definition at line 306 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03

Wednesday

Definition at line 307 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY (uint8_t)0x01
#define | LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
#define | LL_RTC_MONTH_MARCH (uint8_t)0x03
#define | LL_RTC_MONTH_APRIL (uint8_t)0x04
#define | LL_RTC_MONTH_MAY (uint8_t)0x05
#define | LL_RTC_MONTH_JUNE (uint8_t)0x06
#define | LL_RTC_MONTH_JULY (uint8_t)0x07
#define | LL_RTC_MONTH_AUGUST (uint8_t)0x08
#define | LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
#define | LL_RTC_MONTH_OCTOBER (uint8_t)0x10
#define | LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
#define | LL_RTC_MONTH_DECEMBER (uint8_t)0x12

Define Documentation

#define LL_RTC_MONTH_APRIL (uint8_t)0x04

April

Definition at line 322 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST (uint8_t)0x08

August

Definition at line 326 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12

December

Definition at line 330 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02

February

Definition at line 320 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY (uint8_t)0x01

January

Definition at line 319 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY (uint8_t)0x07

July

Definition at line 325 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE (uint8_t)0x06

June

Definition at line 324 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH (uint8_t)0x03

March

Definition at line 321 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_MAY (uint8_t)0x05

May

Definition at line 323 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11

November

Definition at line 329 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10

October

Definition at line 328 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09

September

Definition at line 327 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U

24 hour/day format

Definition at line 338 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 339 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 348 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 349 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE 0x00000000U

Output disabled

Definition at line 347 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 350 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

RTC_ALARM is open-drain output

Definition at line 359 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

RTC_ALARM is push-pull output

Definition at line 360 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 373 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 374 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U

AM or 24-hour format

Definition at line 382 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 383 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 392 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 391 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 405 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 401 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 402 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 403 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE 0x00000000U

No masks applied on Alarm A

Definition at line 400 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 404 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 413 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 414 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 427 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 423 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 424 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 425 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE 0x00000000U

No masks applied on Alarm B

Definition at line 422 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 426 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 435 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 436 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 445 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 444 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 453 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 454 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E

Tamper 1 input detection

Definition at line 463 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E

Tamper 2 input detection

Definition at line 466 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Tamper 3 input detection

Definition at line 469 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased

Definition at line 479 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 482 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK

Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 485 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 495 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 498 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 501 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 511 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 512 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 513 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 514 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 525 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 526 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 527 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 524 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 542 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 538 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 541 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 544 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 537 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 540 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 543 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 539 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG

Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 554 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG

Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 557 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 560 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ACTIVE TAMPER MODE

Defines
ACTIVE TAMPER MODE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM
#define | LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM
#define | LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM

Define Documentation

#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM

tamper 1 is active

Definition at line 679 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM

tamper 2 is active

Definition at line 682 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM

tamper 3 is active

Definition at line 685 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK

Defines
ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

Define Documentation

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U

RTCCLK

Definition at line 696 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/128

Definition at line 703 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2

RTCCLK/16

Definition at line 700 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0

RTCCLK/2

Definition at line 697 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/32

Definition at line 701 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1

RTCCLK/4

Definition at line 698 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)

RTCCLK/64

Definition at line 702 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)

RTCCLK/8

Definition at line 699 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ACTIVE TAMPER OUTPUT SELECTION

Defines
ACTIVE TAMPER OUTPUT SELECTION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)

Define Documentation

#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)

Definition at line 713 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)

Definition at line 714 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)

Definition at line 715 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)

Definition at line 719 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)

Definition at line 720 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)

Definition at line 721 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)

Definition at line 725 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)

Definition at line 726 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)

Definition at line 727 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2

ck_spre (usually 1 Hz) clock is selected

Definition at line 740 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 741 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U

RTC/16 clock is selected

Definition at line 736 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 739 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1

RTC/4 clock is selected

Definition at line 738 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0

RTC/8 clock is selected

Definition at line 737 of file stm32h7xx_ll_rtc.h.

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STM32H7B3xQ HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U
#define | LL_RTC_BKP_DR20 0x00000014U
#define | LL_RTC_BKP_DR21 0x00000015U
#define | LL_RTC_BKP_DR22 0x00000016U
#define | LL_RTC_BKP_DR23 0x00000017U
#define | LL_RTC_BKP_DR24 0x00000018U
#define | LL_RTC_BKP_DR25 0x00000019U
#define | LL_RTC_BKP_DR26 0x0000001AU
#define | LL_RTC_BKP_DR27 0x0000001BU
#define | LL_RTC_BKP_DR28 0x0000001CU
#define | LL_RTC_BKP_DR29 0x0000001DU
#define | LL_RTC_BKP_DR30 0x0000001EU
#define | LL_RTC_BKP_DR31 0x0000001FU

Define Documentation

#define LL_RTC_BKP_DR0 0x00000000U

Definition at line 749 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR1 0x00000001U

Definition at line 750 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR10 0x0000000AU

Definition at line 759 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR11 0x0000000BU

Definition at line 760 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR12 0x0000000CU

Definition at line 761 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR13 0x0000000DU

Definition at line 762 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR14 0x0000000EU

Definition at line 763 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR15 0x0000000FU

Definition at line 764 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR16 0x00000010U

Definition at line 765 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR17 0x00000011U

Definition at line 766 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR18 0x00000012U

Definition at line 767 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR19 0x00000013U

Definition at line 768 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR2 0x00000002U

Definition at line 751 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR20 0x00000014U

Definition at line 769 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR21 0x00000015U

Definition at line 770 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR22 0x00000016U

Definition at line 771 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR23 0x00000017U

Definition at line 772 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR24 0x00000018U

Definition at line 773 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR25 0x00000019U

Definition at line 774 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR26 0x0000001AU

Definition at line 775 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR27 0x0000001BU

Definition at line 776 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR28 0x0000001CU

Definition at line 777 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR29 0x0000001DU

Definition at line 778 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR3 0x00000003U

Definition at line 752 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR30 0x0000001EU

Definition at line 779 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR31 0x0000001FU

Definition at line 780 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR4 0x00000004U

Definition at line 753 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR5 0x00000005U

Definition at line 754 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR6 0x00000006U

Definition at line 755 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR7 0x00000007U

Definition at line 756 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR8 0x00000008U

Definition at line 757 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_BKP_DR9 0x00000009U

Definition at line 758 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 1 Hz

Definition at line 789 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Calibration output is 512 Hz

Definition at line 790 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U

Calibration output disabled

Definition at line 788 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U

No RTCCLK pulses are added

Definition at line 798 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 799 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 808 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U

Use a 32-second calibration cycle period

Definition at line 807 of file stm32h7xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 809 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RTC Exported Macros

Defines

#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in RTC register.

Define Documentation

#define LL_RTC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 842 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

#define LL_RTC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)

Write a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 834 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 863 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 856 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 918 of file stm32h7xx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 911 of file stm32h7xx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 885 of file stm32h7xx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 892 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 933 of file stm32h7xx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 940 of file stm32h7xx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 947 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableAlarmPullUp ( RTC_TypeDef * RTCx )

Disable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1358 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1078 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisableOutput2 ( RTC_TypeDef * RTCx )

Disable RTC_OUT2 output.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_DisableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1396 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1229 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1192 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableTamperOutput ( RTC_TypeDef * RTCx )

Disable tamper output.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_DisableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1323 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1297 of file stm32h7xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableAlarmPullUp ( RTC_TypeDef * RTCx )

Enable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1347 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1066 of file stm32h7xx_ll_rtc.h.

References RTC_LL_INIT_MASK.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnableOutput2 ( RTC_TypeDef * RTCx )

Enable RTC_OUT2 output.

Note:
RTC_OUT2 mapping depends on both OSEL (LL_RTC_SetAlarmOutEvent) and COE (LL_RTC_CAL_SetOutputFreq) settings.
RTC_OUT2 isn't available ins VBAT mode.
Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_EnableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1385 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1216 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1181 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableTamperOutput ( RTC_TypeDef * RTCx )

Enable tamper output.

Note:
When the tamper output is enabled, all external and internal tamper flags are ORed and routed to the TAMPALRM output.
Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_EnableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1312 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1286 of file stm32h7xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 1022 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 1050 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 1264 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 990 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 1169 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 1275 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled ( RTC_TypeDef * RTCx )

Check if internal pull-up in output mode is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1369 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled ( RTC_TypeDef * RTCx )

Check if RTC_OUT2 output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1407 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1203 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled ( RTC_TypeDef * RTCx )

Check if tamper output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1334 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 1007 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 1037 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 1241 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 977 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 1156 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 1253 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_Config RTC_TR HT LL_RTC_TIME_Config RTC_TR HU LL_RTC_TIME_Config RTC_TR MNT LL_RTC_TIME_Config RTC_TR MNU LL_RTC_TIME_Config RTC_TR ST LL_RTC_TIME_Config RTC_TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1605 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1685 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1662 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1650 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_Get RTC_TR HU LL_RTC_TIME_Get RTC_TR MNT LL_RTC_TIME_Get RTC_TR MNU LL_RTC_TIME_Get RTC_TR ST LL_RTC_TIME_Get RTC_TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1633 of file stm32h7xx_ll_rtc.h.

References RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1474 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_GetHour RTC_TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1509 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_GetMinute RTC_TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1544 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_GetSecond RTC_TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1579 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
RTC_SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1715 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1697 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1673 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1457 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_SetHour RTC_TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1490 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_SetMinute RTC_TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1525 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_SetSecond RTC_TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1560 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1734 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Config RTC_DR MT LL_RTC_DATE_Config RTC_DR MU LL_RTC_DATE_Config RTC_DR DT LL_RTC_DATE_Config RTC_DR DU LL_RTC_DATE_Config RTC_DR YT LL_RTC_DATE_Config RTC_DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1935 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Get RTC_DR MT LL_RTC_DATE_Get RTC_DR MU LL_RTC_DATE_Get RTC_DR DT LL_RTC_DATE_Get RTC_DR DU LL_RTC_DATE_Get RTC_DR YT LL_RTC_DATE_Get RTC_DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1963 of file stm32h7xx_ll_rtc.h.

References RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_GetDay RTC_DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1895 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_GetMonth RTC_DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1865 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1811 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_GetYear RTC_DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1772 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_SetDay RTC_DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1879 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_SetMonth RTC_DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1837 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1791 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_SetYear RTC_DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1756 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2263 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2001 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2064 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1989 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2053 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_GetDay RTC_ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2092 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetHour RTC_ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2184 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 2042 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2212 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_GetSecond RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2240 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2335 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2312 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetTime RTC_ALRMAR HU LL_RTC_ALMA_GetTime RTC_ALRMAR MNT LL_RTC_ALMA_GetTime RTC_ALRMAR MNU LL_RTC_ALMA_GetTime RTC_ALRMAR ST LL_RTC_ALMA_GetTime RTC_ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2287 of file stm32h7xx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 2156 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2129 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_SetDay RTC_ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2078 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_SetHour RTC_ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2170 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 2022 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2198 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_SetSecond RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2226 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2324 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2301 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 2143 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2111 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2629 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2367 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2430 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2355 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2419 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_GetDay RTC_ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2458 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetHour RTC_ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2550 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2408 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2578 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_GetSecond RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2606 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2701 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2678 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetTime RTC_ALRMBR HU LL_RTC_ALMB_GetTime RTC_ALRMBR MNT LL_RTC_ALMB_GetTime RTC_ALRMBR MNU LL_RTC_ALMB_GetTime RTC_ALRMBR ST LL_RTC_ALMB_GetTime RTC_ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2653 of file stm32h7xx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2522 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2495 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_SetDay RTC_ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2444 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_SetHour RTC_ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2536 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2388 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2564 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_SetSecond RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2592 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2690 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2667 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2509 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2477 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2757 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent ( RTC_TypeDef * RTCx )

Disable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2733 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2745 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent ( RTC_TypeDef * RTCx )

Enable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2721 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2787 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetDate RTC_TSDR MT LL_RTC_TS_GetDate RTC_TSDR MU LL_RTC_TS_GetDate RTC_TSDR DT LL_RTC_TS_GetDate RTC_TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2931 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR DT LL_RTC_TS_GetDay RTC_TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2914 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetHour RTC_TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2813 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR MNT LL_RTC_TS_GetMinute RTC_TSTR MNU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2826 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR MT LL_RTC_TS_GetMonth RTC_TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2901 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR ST LL_RTC_TS_GetSecond RTC_TSTR SU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2839 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
RTC_TSSSR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2942 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetTime RTC_TSTR HU LL_RTC_TS_GetTime RTC_TSTR MNT LL_RTC_TS_GetTime RTC_TSTR MNU LL_RTC_TS_GetTime RTC_TSTR ST LL_RTC_TS_GetTime RTC_TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2857 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
RTC_TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2800 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2876 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2773 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Time-stamp on Tamper

Functions
Time-stamp on Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2998 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2987 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (TAMP_TypeDef *TAMPx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (TAMP_TypeDef *TAMPx)
Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (TAMP_TypeDef *TAMPx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (TAMP_TypeDef *TAMPx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (TAMP_TypeDef *TAMPx)
Get Tamper sampling frequency.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Clear TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable TAMP_CR1 TAMP3E LL_RTC_TAMPER_Disable
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3
Return values:
None

Definition at line 3324 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 3435 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Disable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3
Return values:
None

Definition at line 3399 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableMask | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Mask
 | ) |  |

Disable Tamper mask flag.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask TAMP_CR2 TAMP2MF LL_RTC_TAMPER_DisableMask TAMP_CR2 TAMP3MF LL_RTC_TAMPER_DisableMask
Parameters:
TAMPx TAMP Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3
Return values:
None

Definition at line 3363 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( TAMP_TypeDef * TAMPx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3448 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable TAMP_CR1 TAMP3E LL_RTC_TAMPER_Enable
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3
Return values:
None

Definition at line 3306 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 3417 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3
Return values:
None

Definition at line 3381 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableMask | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Mask
 | ) |  |

Enable Tamper mask flag.

Note:
Associated Tamper IT must not enabled when tamper mask is set.
Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask TAMP_CR2 TAMP2MF LL_RTC_TAMPER_EnableMask TAMP_CR2 TAMP3MF LL_RTC_TAMPER_EnableMask
Parameters:
TAMPx TAMP Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3
Return values:
None

Definition at line 3345 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( TAMP_TypeDef * TAMPx )

Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3459 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( TAMP_TypeDef * TAMPx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 3521 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( TAMP_TypeDef * TAMPx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 3490 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( TAMP_TypeDef * TAMPx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 3560 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
TAMPx TAMP Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 3506 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
TAMPx TAMP Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 3475 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
TAMPx TAMP Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 3541 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3593 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3581 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3665 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 3641 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3604 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1 in RTC_ISR
Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3654 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 3624 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Backup_Registers

Backup_Registers
RTC Exported Functions
Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 4006 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_GetOutputFreq RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3921 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_GetPeriod RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3981 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3948 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3995 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_SetOutputFreq RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3906 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_SetPeriod RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3966 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3937 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (TAMP_TypeDef *TAMPx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (TAMP_TypeDef *TAMPx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (TAMP_TypeDef *TAMPx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Clear tamper 3 detection flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4449 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4438 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITS ( RTC_TypeDef * RTCx )

Clear Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CITSF LL_RTC_ClearFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4394 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4495 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( TAMP_TypeDef * TAMPx )

Clear tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4709 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( TAMP_TypeDef * TAMPx )

Clear tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4722 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( TAMP_TypeDef * TAMPx )

Clear tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4735 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4416 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4405 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4427 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4381 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM ( RTC_TypeDef * RTCx )

Get Alarm A masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4563 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4550 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4370 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM ( RTC_TypeDef * RTCx )

Get Alarm B masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4574 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4539 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4473 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4506 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS ( RTC_TypeDef * RTCx )

Get Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4326 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM ( RTC_TypeDef * RTCx )

Get Internal Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4618 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4462 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4484 of file stm32h7xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4517 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( TAMP_TypeDef * TAMPx )

Get tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4631 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M ( TAMP_TypeDef * TAMPx )

Get tamper 1 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4670 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( TAMP_TypeDef * TAMPx )

Get tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4644 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M ( TAMP_TypeDef * TAMPx )

Get tamper 2 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4683 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( TAMP_TypeDef * TAMPx )

Get tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4657 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M ( TAMP_TypeDef * TAMPx )

Get tamper 3 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4696 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4348 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM ( RTC_TypeDef * RTCx )

Get Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4596 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4337 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM ( RTC_TypeDef * RTCx )

Get Time-stamp overflow masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4607 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4359 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM ( RTC_TypeDef * RTCx )

Get Wakeup timer masked flag.

Reference Manual to LL API cross reference:
RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4585 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4528 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Disable tamper 3 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (TAMP_TypeDef *TAMPx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (TAMP_TypeDef *TAMPx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (TAMP_TypeDef *TAMPx)
Check if tamper 3 interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4840 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4816 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Disable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5056 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Disable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5080 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Disable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5104 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4768 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4792 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4828 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4804 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Enable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5045 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Enable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5069 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Enable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 5093 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4756 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4780 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4980 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4969 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Check if tamper 1 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 5117 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Check if tamper 2 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 5130 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Check if tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 5143 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4947 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4958 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Active Tamper

Functions
Active Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableActiveMode (uint32_t Tamper)
Enable tamper active mode.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableActiveMode (uint32_t Tamper)
Disable tamper active mode.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableFilter (void)
Enable active tamper filter.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableFilter (void)
Disable active tamper filter.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod (uint32_t ActiveOutputChangePeriod)
Set Active tamper output change period.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod (void)
Get Active tamper output change period.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler (uint32_t ActiveAsynvPrescaler)
Set Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler (void)
Get Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableOutputSharing (void)
Enable active tamper output sharing.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableOutputSharing (void)
Disable active tamper output sharing.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection (uint32_t OutputSelection)
Set Active tamper output selection.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection (void)
Get Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ATAMP_INITS (void)
Get active tamper initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ATAMP_SEEDF (void)
Get active tamper seed running status flag.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS ( void )

Get active tamper initialization status flag.

Reference Manual to LL API cross reference:
TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
Return values:
State of bit (1 or 0).

Definition at line 5315 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF ( void )

Get active tamper seed running status flag.

Reference Manual to LL API cross reference:
TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
Return values:
State of bit (1 or 0).

Definition at line 5325 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode ( uint32_t Tamper )

Disable tamper active mode.

Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode
Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode
Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode
Parameters:
Tamper to configure as active. This parameter can be a combination of the following values:
  • ACTIVE TAMPER MODE
Return values:
None

Definition at line 5182 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter ( void )

Disable active tamper filter.

Reference Manual to LL API cross reference:
TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter
Return values:
None

Definition at line 5202 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing ( void )

Disable active tamper output sharing.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing
Return values:
None

Definition at line 5266 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode ( uint32_t Tamper )

Enable tamper active mode.

Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode
Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode
Reference Manual to LL API cross reference:
TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode
Parameters:
Tamper to configure as active. This parameter can be a combination of the following values:
  • ACTIVE TAMPER MODE
Return values:
None

Definition at line 5167 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter ( void )

Enable active tamper filter.

Reference Manual to LL API cross reference:
TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter
Return values:
None

Definition at line 5192 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing ( void )

Enable active tamper output sharing.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing
Return values:
None

Definition at line 5256 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler ( void )

Get Active tamper asynchronous prescaler clock selection.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler
Return values:
One of
  • ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK

Definition at line 5246 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod ( void )

Get Active tamper output change period.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod
Return values:
Output change period. This parameter can be a value from 0 to 7.

Definition at line 5223 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection ( void )

Get Active tamper asynchronous prescaler clock selection.

Reference Manual to LL API cross reference:
TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler
Return values:
A combination of
  • ACTIVE TAMPER OUTPUT SELECTION

Definition at line 5290 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler ( uint32_t ActiveAsynvPrescaler )

Set Active tamper asynchronous prescaler clock selection.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler
Parameters:
ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock. This parameter can be a value of the following values:
  • ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
Return values:
None

Definition at line 5236 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod ( uint32_t ActiveOutputChangePeriod )

Set Active tamper output change period.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod
Parameters:
ActiveOutputChangePeriod This parameter can be a value from 0 to 7
Return values:
None

Definition at line 5213 of file stm32h7xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection ( uint32_t OutputSelection )

Set Active tamper output selection.

Reference Manual to LL API cross reference:
TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection
Parameters:
OutputSelection Specifies all the output selection of the Active Tamper. This parameter is a combinasation of the following values: One of
  • ACTIVE TAMPER OUTPUT SELECTION
Return values:
None

Definition at line 5279 of file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 480 of file stm32h7xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 708 of file stm32h7xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 598 of file stm32h7xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 730 of file stm32h7xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 390 of file stm32h7xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 457 of file stm32h7xx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function does not reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 149 of file stm32h7xx_ll_rtc.c.

References assert_param, LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_ReadReg, LL_RTC_WaitForSynchro(), LL_RTC_WriteReg, and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 755 of file stm32h7xx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 799 of file stm32h7xx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 228 of file stm32h7xx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 267 of file stm32h7xx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 287 of file stm32h7xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 369 of file stm32h7xx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 826 of file stm32h7xx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Private Macros

Data Structures | Defines
SPI Private Macros
SPI

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...

Defines

#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_SS_IDLENESS(__VALUE__)
#define | IS_LL_SPI_ID_IDLENESS(__VALUE__)
#define | IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)
#define | IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)
#define | IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)
#define | IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)
#define | IS_LL_SPI_PROTOCOL(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_FIFO_TH(__VALUE__)
#define | IS_LL_SPI_CRC(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_RX_FIFO(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)

Define Documentation

#define IS_LL_SPI_BAUDRATEPRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)      \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)      \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)     \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)     \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)     \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128)    \
                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 112 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST)                   \
                                                  || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 121 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRC_4BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_5BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_6BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_7BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_8BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_9BIT)                    \
                                                  || ((__VALUE__) == LL_SPI_CRC_10BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_11BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_12BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_13BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_14BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_15BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_16BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_17BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_18BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_19BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_20BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_21BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_22BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_23BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_24BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_25BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_26BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_27BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_28BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_29BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_30BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_31BIT)                   \
                                                  || ((__VALUE__) == LL_SPI_CRC_32BIT))

Definition at line 177 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1UL)

Definition at line 219 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE)       \
                                                  || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 216 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)              \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT)             \
                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))

Definition at line 130 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_FIFO_TH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FIFO_TH_01DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA)              \
                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))

Definition at line 160 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_ID_IDLENESS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))

Definition at line 72 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER)                 \
                                                  || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 52 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT)                    \
                                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT)              \
                                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 207 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE)                 \
                                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 106 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW)                \
                                                  || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 109 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PROTOCOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA)           \
                                                  || ((__VALUE__) == LL_SPI_PROTOCOL_TI))

Definition at line 103 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_RX_FIFO ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_RX_FIFO_0PACKET)             \
                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET)             \
                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET)             \
                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))

Definition at line 211 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_RXCRCINIT_PATTERN ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN)  \
                                                  || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))

Definition at line 92 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_SS_IDLENESS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE)         \
                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))

Definition at line 55 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)                 \
                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_TX)                  \
                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)                  \
                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX)              \
                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 124 of file stm32h7xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TXCRCINIT_PATTERN ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN)  \
                                                  || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))

Definition at line 89 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_UDR_CONFIG_REGISTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
                                                  || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED)    \
                                                  || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))

Definition at line 95 of file stm32h7xx_ll_spi.c.

#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
                                                  || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME)   \
                                                  || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))

Definition at line 99 of file stm32h7xx_ll_spi.c.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Private Macros

SPI Init structures definition. More...

#include <stm32h7xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 54 of file stm32h7xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 86 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 92 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 76 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 71 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 97 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 102 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Data Width.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 66 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 61 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of NSS Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 81 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 56 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_spi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXP (SPI_SR_RXP)
#define | LL_SPI_SR_TXP (SPI_SR_TXP)
#define | LL_SPI_SR_DXP (SPI_SR_DXP)
#define | LL_SPI_SR_EOT (SPI_SR_EOT)
#define | LL_SPI_SR_TXTF (SPI_SR_TXTF)
#define | LL_SPI_SR_UDR (SPI_SR_UDR)
#define | LL_SPI_SR_CRCE (SPI_SR_CRCE)
#define | LL_SPI_SR_MODF (SPI_SR_MODF)
#define | LL_SPI_SR_OVR (SPI_SR_OVR)
#define | LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
#define | LL_SPI_SR_TSERF (SPI_SR_TSERF)
#define | LL_SPI_SR_SUSP (SPI_SR_SUSP)
#define | LL_SPI_SR_TXC (SPI_SR_TXC)
#define | LL_SPI_SR_RXWNE (SPI_SR_RXWNE)

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_CRCE (SPI_SR_CRCE)

Definition at line 131 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_DXP (SPI_SR_DXP)

Definition at line 127 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_EOT (SPI_SR_EOT)

Definition at line 128 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_MODF (SPI_SR_MODF)

Definition at line 132 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_OVR (SPI_SR_OVR)

Definition at line 133 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_RXP (SPI_SR_RXP)

Definition at line 125 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)

Definition at line 138 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_SUSP (SPI_SR_SUSP)

Definition at line 136 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)

Definition at line 134 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_TSERF (SPI_SR_TSERF)

Definition at line 135 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_TXC (SPI_SR_TXC)

Definition at line 137 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_TXP (SPI_SR_TXP)

Definition at line 126 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_TXTF (SPI_SR_TXTF)

Definition at line 129 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SR_UDR (SPI_SR_UDR)

Definition at line 130 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
#define | LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
#define | LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
#define | LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
#define | LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
#define | LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
#define | LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
#define | LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
#define | LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
#define | LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
#define | LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)

Definition at line 154 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)

Definition at line 149 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)

Definition at line 150 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)

Definition at line 156 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)

Definition at line 153 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)

Definition at line 147 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)

Definition at line 155 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)

Definition at line 157 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)

Definition at line 148 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)

Definition at line 151 of file stm32h7xx_ll_spi.h.

#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)

Definition at line 152 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Mode

Defines
Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
#define | LL_SPI_MODE_SLAVE (0x00000000UL)

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)

Definition at line 165 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

#define LL_SPI_MODE_SLAVE (0x00000000UL)

Definition at line 166 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SS Level

Defines
SS Level
SPI Exported Constants

Defines

#define | LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
#define | LL_SPI_SS_LEVEL_LOW (0x00000000UL)

Define Documentation

#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)

Definition at line 174 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)

Definition at line 175 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SS Idleness

Defines
SS Idleness
SPI Exported Constants

Defines

#define | LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
#define | LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
#define | LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
#define | LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
#define | LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

Define Documentation

#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)

Definition at line 183 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)

Definition at line 184 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)

Definition at line 185 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)

Definition at line 186 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)

Definition at line 187 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

Definition at line 188 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

Definition at line 189 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

Definition at line 190 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)

Definition at line 191 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)

Definition at line 192 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)

Definition at line 193 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

Definition at line 194 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)

Definition at line 195 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

Definition at line 196 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

Definition at line 197 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

Definition at line 198 of file stm32h7xx_ll_spi.h.

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STM32H7B3xQ HAL User Manual: Master Inter-Data Idleness

Defines
Master Inter-Data Idleness
SPI Exported Constants

Defines

#define | LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
#define | LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
#define | LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
#define | LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
#define | LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

Define Documentation

#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)

Definition at line 206 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)

Definition at line 207 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)

Definition at line 208 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)

Definition at line 209 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)

Definition at line 210 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

Definition at line 211 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

Definition at line 212 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

Definition at line 213 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)

Definition at line 214 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)

Definition at line 215 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)

Definition at line 216 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

Definition at line 217 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)

Definition at line 218 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

Definition at line 219 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

Definition at line 220 of file stm32h7xx_ll_spi.h.

#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

Definition at line 221 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TXCRC Init All

Defines
TXCRC Init All
SPI Exported Constants

Defines

#define | LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define | LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)

Define Documentation

#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)

Definition at line 230 of file stm32h7xx_ll_spi.h.

#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)

Definition at line 229 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RXCRC Init All

Defines
RXCRC Init All
SPI Exported Constants

Defines

#define | LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define | LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)

Define Documentation

#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)

Definition at line 239 of file stm32h7xx_ll_spi.h.

#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)

Definition at line 238 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UDR Config Register

Defines
UDR Config Register
SPI Exported Constants

Defines

#define | LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
#define | LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
#define | LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)

Define Documentation

#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)

Definition at line 248 of file stm32h7xx_ll_spi.h.

#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)

Definition at line 249 of file stm32h7xx_ll_spi.h.

#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)

Definition at line 247 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UDR Detect Begin Data

Defines
UDR Detect Begin Data
SPI Exported Constants

Defines

#define | LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
#define | LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
#define | LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)

Define Documentation

#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)

Definition at line 259 of file stm32h7xx_ll_spi.h.

#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)

Definition at line 257 of file stm32h7xx_ll_spi.h.

#define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)

Definition at line 258 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Protocol

Defines
Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
#define | LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)

Definition at line 267 of file stm32h7xx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)

Definition at line 268 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Phase

Defines
Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE (0x00000000UL)
#define | LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE (0x00000000UL)

Definition at line 276 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)

Definition at line 277 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Polarity

Defines
Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW (0x00000000UL)
#define | LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)

Definition at line 286 of file stm32h7xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW (0x00000000UL)

Definition at line 285 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NSS Polarity

Defines
NSS Polarity
SPI Exported Constants

Defines

#define | LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
#define | LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)

Define Documentation

#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)

Definition at line 295 of file stm32h7xx_ll_spi.h.

#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)

Definition at line 294 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)

Definition at line 309 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

Definition at line 306 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)

Definition at line 303 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

Definition at line 310 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)

Definition at line 307 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)

Definition at line 304 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)

Definition at line 308 of file stm32h7xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)

Definition at line 305 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Bit Order

Defines
Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
#define | LL_SPI_MSB_FIRST (0x00000000UL)

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)

Definition at line 318 of file stm32h7xx_ll_spi.h.

#define LL_SPI_MSB_FIRST (0x00000000UL)

Definition at line 319 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX (0x00000000UL)
#define | LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
#define | LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)

Define Documentation

#define LL_SPI_FULL_DUPLEX (0x00000000UL)

Definition at line 327 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)

Definition at line 330 of file stm32h7xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)

Definition at line 331 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)

Definition at line 329 of file stm32h7xx_ll_spi.h.

#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)

Definition at line 328 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Width

Defines
Data Width
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
#define | LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
#define | LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)

Definition at line 345 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)

Definition at line 346 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 347 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)

Definition at line 348 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

Definition at line 349 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

Definition at line 350 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 351 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)

Definition at line 352 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)

Definition at line 353 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)

Definition at line 354 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)

Definition at line 355 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)

Definition at line 356 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

Definition at line 357 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

Definition at line 358 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 359 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)

Definition at line 360 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)

Definition at line 361 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)

Definition at line 362 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 363 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)

Definition at line 364 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

Definition at line 365 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

Definition at line 366 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 367 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)

Definition at line 339 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)

Definition at line 340 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

Definition at line 341 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

Definition at line 342 of file stm32h7xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

Definition at line 343 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)

Definition at line 344 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_FIFO_TH_01DATA (0x00000000UL)
#define | LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
#define | LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
#define | LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
#define | LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

Define Documentation

#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)

Definition at line 375 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)

Definition at line 376 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)

Definition at line 377 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)

Definition at line 378 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)

Definition at line 379 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)

Definition at line 380 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)

Definition at line 381 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

Definition at line 382 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)

Definition at line 383 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)

Definition at line 384 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)

Definition at line 385 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

Definition at line 386 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)

Definition at line 387 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)

Definition at line 388 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)

Definition at line 389 of file stm32h7xx_ll_spi.h.

#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

Definition at line 390 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL)
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL)

CRC calculation disabled

Definition at line 400 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN)

CRC calculation enabled

Definition at line 401 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CRC

Defines
CRC
SPI Exported Constants

Defines

#define | LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
#define | LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
#define | LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
#define | LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Define Documentation

#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)

Definition at line 416 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)

Definition at line 417 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 418 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)

Definition at line 419 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

Definition at line 420 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

Definition at line 421 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 422 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)

Definition at line 423 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)

Definition at line 424 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)

Definition at line 425 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)

Definition at line 426 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)

Definition at line 427 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

Definition at line 428 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

Definition at line 429 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 430 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)

Definition at line 431 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)

Definition at line 432 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)

Definition at line 433 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 434 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)

Definition at line 435 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

Definition at line 436 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

Definition at line 437 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 438 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)

Definition at line 410 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)

Definition at line 411 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

Definition at line 412 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

Definition at line 413 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

Definition at line 414 of file stm32h7xx_ll_spi.h.

#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)

Definition at line 415 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NSS Mode

Defines
NSS Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
#define | LL_SPI_NSS_HARD_INPUT (0x00000000UL)
#define | LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)

Define Documentation

#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)

Definition at line 447 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)

Definition at line 448 of file stm32h7xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)

Definition at line 446 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RxFIFO Packing LeVel

Defines
RxFIFO Packing LeVel
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
#define | LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
#define | LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
#define | LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */

Definition at line 456 of file stm32h7xx_ll_spi.h.

#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)

Definition at line 457 of file stm32h7xx_ll_spi.h.

#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)

Definition at line 458 of file stm32h7xx_ll_spi.h.

#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Definition at line 459 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 492 of file stm32h7xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 484 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_EnableIOSwap (SPI_TypeDef *SPIx)
Swap the MOSI and MISO pin.
__STATIC_INLINE void | LL_SPI_DisableIOSwap (SPI_TypeDef *SPIx)
Restore default function for MOSI and MISO pin.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOSwap (SPI_TypeDef *SPIx)
Check if MOSI and MISO pin are swapped.
__STATIC_INLINE void | LL_SPI_EnableGPIOControl (SPI_TypeDef *SPIx)
Enable GPIO control.
__STATIC_INLINE void | LL_SPI_DisableGPIOControl (SPI_TypeDef *SPIx)
Disable GPIO control.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledGPIOControl (SPI_TypeDef *SPIx)
Check if GPIO control is active.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI Mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI Mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetMasterSSIdleness (SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
Configure the Idleness applied by master between active edge of SS and first send data.
__STATIC_INLINE uint32_t | LL_SPI_GetMasterSSIdleness (SPI_TypeDef *SPIx)
Get the configured Idleness applied by master.
__STATIC_INLINE void | LL_SPI_SetInterDataIdleness (SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
Configure the idleness applied by master between data frame.
__STATIC_INLINE uint32_t | LL_SPI_GetInterDataIdleness (SPI_TypeDef *SPIx)
Get the configured inter data idleness.
__STATIC_INLINE void | LL_SPI_SetTransferSize (SPI_TypeDef *SPIx, uint32_t Count)
Set transfer size.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferSize (SPI_TypeDef *SPIx)
Get transfer size.
__STATIC_INLINE void | LL_SPI_SetReloadSize (SPI_TypeDef *SPIx, uint32_t Count)
Set reload transfer size.
__STATIC_INLINE uint32_t | LL_SPI_GetReloadSize (SPI_TypeDef *SPIx)
Get reload transfer size.
__STATIC_INLINE void | LL_SPI_EnableIOLock (SPI_TypeDef *SPIx)
Lock the AF configuration of associated IOs.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOLock (SPI_TypeDef *SPIx)
Check if the AF configuration is locked.
__STATIC_INLINE void | LL_SPI_SetTxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
Set Tx CRC Initialization Pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRCInitPattern (SPI_TypeDef *SPIx)
Get Tx CRC Initialization Pattern.
__STATIC_INLINE void | LL_SPI_SetRxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
Set Rx CRC Initialization Pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRCInitPattern (SPI_TypeDef *SPIx)
Get Rx CRC Initialization Pattern.
__STATIC_INLINE void | LL_SPI_SetInternalSSLevel (SPI_TypeDef *SPIx, uint32_t SSLevel)
Set internal SS input level ignoring what comes from PIN.
__STATIC_INLINE uint32_t | LL_SPI_GetInternalSSLevel (SPI_TypeDef *SPIx)
Get internal SS input level.
__STATIC_INLINE void | LL_SPI_EnableFullSizeCRC (SPI_TypeDef *SPIx)
Enable CRC computation on 33/17 bits.
__STATIC_INLINE void | LL_SPI_DisableFullSizeCRC (SPI_TypeDef *SPIx)
Disable CRC computation on 33/17 bits.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledFullSizeCRC (SPI_TypeDef *SPIx)
Check if Enable CRC computation on 33/17 bits is enabled.
__STATIC_INLINE void | LL_SPI_SuspendMasterTransfer (SPI_TypeDef *SPIx)
Suspend an ongoing transfer for Master configuration.
__STATIC_INLINE void | LL_SPI_StartMasterTransfer (SPI_TypeDef *SPIx)
Start effective transfer on wire for Master configuration.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveMasterTransfer (SPI_TypeDef *SPIx)
Check if there is an unfinished master transfer.
__STATIC_INLINE void | LL_SPI_EnableMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Enable Master Rx auto suspend in case of overrun.
__STATIC_INLINE void | LL_SPI_DisableMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Disable Master Rx auto suspend in case of overrun.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Check if Master Rx auto suspend is activated.
__STATIC_INLINE void | LL_SPI_SetUDRConfiguration (SPI_TypeDef *SPIx, uint32_t UDRConfig)
Set Underrun behavior.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRConfiguration (SPI_TypeDef *SPIx)
Get Underrun behavior.
__STATIC_INLINE void | LL_SPI_SetUDRDetection (SPI_TypeDef *SPIx, uint32_t UDRDetection)
Set Underrun Detection method.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRDetection (SPI_TypeDef *SPIx)
Get Underrun Detection method.
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set Serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get Serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set Clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get Clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set Clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get Clock polarity.
__STATIC_INLINE void | LL_SPI_SetNSSPolarity (SPI_TypeDef *SPIx, uint32_t NSSPolarity)
Set NSS polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSPolarity (SPI_TypeDef *SPIx)
Get NSS polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t Baudrate)
Set Baudrate Prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get Baudrate Prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set Transfer Bit Order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get Transfer Bit Order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set Transfer Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get Transfer Mode.
__STATIC_INLINE void | LL_SPI_SetHalfDuplexDirection (SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
Set direction for Half-Duplex Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetHalfDuplexDirection (SPI_TypeDef *SPIx)
Get direction for Half-Duplex Mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set Frame Data Size.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get Frame Data Size.
__STATIC_INLINE void | LL_SPI_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of FIFO that triggers a transfer event.
__STATIC_INLINE uint32_t | LL_SPI_GetFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of FIFO that triggers a transfer event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Set NSS Mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse mgt.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse mgt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 530 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Reference Manual to LL API cross reference:
CFG1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1478 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableFullSizeCRC ( SPI_TypeDef * SPIx )

Disable CRC computation on 33/17 bits.

Reference Manual to LL API cross reference:
CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 927 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableGPIOControl ( SPI_TypeDef * SPIx )

Disable GPIO control.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_SPI_DisableGPIOControl
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 600 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableGPIOControl().

__STATIC_INLINE void LL_SPI_DisableIOSwap ( SPI_TypeDef * SPIx )

Restore default function for MOSI and MISO pin.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 IOSWP LL_SPI_DisableIOSwap
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 565 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIOSwap().

__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend ( SPI_TypeDef * SPIx )

Disable Master Rx auto suspend in case of overrun.

Reference Manual to LL API cross reference:
CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 993 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse mgt.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 SSOM LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1630 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 518 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1467 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableFullSizeCRC ( SPI_TypeDef * SPIx )

Enable CRC computation on 33/17 bits.

Reference Manual to LL API cross reference:
CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 916 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableGPIOControl ( SPI_TypeDef * SPIx )

Enable GPIO control.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_SPI_EnableGPIOControl
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 588 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableGPIOControl().

__STATIC_INLINE void LL_SPI_EnableIOLock ( SPI_TypeDef * SPIx )

Lock the AF configuration of associated IOs.

Note:
Once this bit is set, the AF configuration remains locked until a hardware reset occurs. the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
Reference Manual to LL API cross reference:
CR1 IOLOCK LL_SPI_EnableIOLock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 812 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIOLock().

__STATIC_INLINE void LL_SPI_EnableIOSwap ( SPI_TypeDef * SPIx )

Swap the MOSI and MISO pin.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 IOSWP LL_SPI_EnableIOSwap
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 553 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIOSwap().

__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend ( SPI_TypeDef * SPIx )

Enable Master Rx auto suspend in case of overrun.

Reference Manual to LL API cross reference:
CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 982 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse mgt.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 SSOM LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1617 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get Baudrate Prescaler.

Reference Manual to LL API cross reference:
CFG1 MBR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 1220 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get Clock phase.

Reference Manual to LL API cross reference:
CFG2 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 1121 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get Clock polarity.

Reference Manual to LL API cross reference:
CFG2 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 1150 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CFG1 CRCSIZE LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_4BIT
  • LL_SPI_CRC_5BIT
  • LL_SPI_CRC_6BIT
  • LL_SPI_CRC_7BIT
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_9BIT
  • LL_SPI_CRC_10BIT
  • LL_SPI_CRC_11BIT
  • LL_SPI_CRC_12BIT
  • LL_SPI_CRC_13BIT
  • LL_SPI_CRC_14BIT
  • LL_SPI_CRC_15BIT
  • LL_SPI_CRC_16BIT
  • LL_SPI_CRC_17BIT
  • LL_SPI_CRC_18BIT
  • LL_SPI_CRC_19BIT
  • LL_SPI_CRC_20BIT
  • LL_SPI_CRC_21BIT
  • LL_SPI_CRC_22BIT
  • LL_SPI_CRC_23BIT
  • LL_SPI_CRC_24BIT
  • LL_SPI_CRC_25BIT
  • LL_SPI_CRC_26BIT
  • LL_SPI_CRC_27BIT
  • LL_SPI_CRC_28BIT
  • LL_SPI_CRC_29BIT
  • LL_SPI_CRC_30BIT
  • LL_SPI_CRC_31BIT
  • LL_SPI_CRC_32BIT

Definition at line 1571 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get Frame Data Size.

Reference Manual to LL API cross reference:
CFG1 DSIZE LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
  • LL_SPI_DATAWIDTH_17BIT
  • LL_SPI_DATAWIDTH_18BIT
  • LL_SPI_DATAWIDTH_19BIT
  • LL_SPI_DATAWIDTH_20BIT
  • LL_SPI_DATAWIDTH_21BIT
  • LL_SPI_DATAWIDTH_22BIT
  • LL_SPI_DATAWIDTH_23BIT
  • LL_SPI_DATAWIDTH_24BIT
  • LL_SPI_DATAWIDTH_25BIT
  • LL_SPI_DATAWIDTH_26BIT
  • LL_SPI_DATAWIDTH_27BIT
  • LL_SPI_DATAWIDTH_28BIT
  • LL_SPI_DATAWIDTH_29BIT
  • LL_SPI_DATAWIDTH_30BIT
  • LL_SPI_DATAWIDTH_31BIT
  • LL_SPI_DATAWIDTH_32BIT

Definition at line 1399 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of FIFO that triggers a transfer event.

Reference Manual to LL API cross reference:
CFG1 FTHLV LL_SPI_GetFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FIFO_TH_01DATA
  • LL_SPI_FIFO_TH_02DATA
  • LL_SPI_FIFO_TH_03DATA
  • LL_SPI_FIFO_TH_04DATA
  • LL_SPI_FIFO_TH_05DATA
  • LL_SPI_FIFO_TH_06DATA
  • LL_SPI_FIFO_TH_07DATA
  • LL_SPI_FIFO_TH_08DATA
  • LL_SPI_FIFO_TH_09DATA
  • LL_SPI_FIFO_TH_10DATA
  • LL_SPI_FIFO_TH_11DATA
  • LL_SPI_FIFO_TH_12DATA
  • LL_SPI_FIFO_TH_13DATA
  • LL_SPI_FIFO_TH_14DATA
  • LL_SPI_FIFO_TH_15DATA
  • LL_SPI_FIFO_TH_16DATA

Definition at line 1455 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_GetFIFOThreshold().

__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection ( SPI_TypeDef * SPIx )

Get direction for Half-Duplex Mode.

Note:
In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 HDDIR LL_SPI_GetHalfDuplexDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 1317 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness ( SPI_TypeDef * SPIx )

Get the configured inter data idleness.

Reference Manual to LL API cross reference:
CFG2 MIDI LL_SPI_SetInterDataIdleness
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_ID_IDLENESS_00CYCLE
  • LL_SPI_ID_IDLENESS_01CYCLE
  • LL_SPI_ID_IDLENESS_02CYCLE
  • LL_SPI_ID_IDLENESS_03CYCLE
  • LL_SPI_ID_IDLENESS_04CYCLE
  • LL_SPI_ID_IDLENESS_05CYCLE
  • LL_SPI_ID_IDLENESS_06CYCLE
  • LL_SPI_ID_IDLENESS_07CYCLE
  • LL_SPI_ID_IDLENESS_08CYCLE
  • LL_SPI_ID_IDLENESS_09CYCLE
  • LL_SPI_ID_IDLENESS_10CYCLE
  • LL_SPI_ID_IDLENESS_11CYCLE
  • LL_SPI_ID_IDLENESS_12CYCLE
  • LL_SPI_ID_IDLENESS_13CYCLE
  • LL_SPI_ID_IDLENESS_14CYCLE
  • LL_SPI_ID_IDLENESS_15CYCLE

Definition at line 749 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel ( SPI_TypeDef * SPIx )

Get internal SS input level.

Reference Manual to LL API cross reference:
CR1 SSI LL_SPI_GetInternalSSLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_SS_LEVEL_HIGH
  • LL_SPI_SS_LEVEL_LOW

Definition at line 905 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness ( SPI_TypeDef * SPIx )

Get the configured Idleness applied by master.

Reference Manual to LL API cross reference:
CFG2 MSSI LL_SPI_GetMasterSSIdleness
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_SS_IDLENESS_00CYCLE
  • LL_SPI_SS_IDLENESS_01CYCLE
  • LL_SPI_SS_IDLENESS_02CYCLE
  • LL_SPI_SS_IDLENESS_03CYCLE
  • LL_SPI_SS_IDLENESS_04CYCLE
  • LL_SPI_SS_IDLENESS_05CYCLE
  • LL_SPI_SS_IDLENESS_06CYCLE
  • LL_SPI_SS_IDLENESS_07CYCLE
  • LL_SPI_SS_IDLENESS_08CYCLE
  • LL_SPI_SS_IDLENESS_09CYCLE
  • LL_SPI_SS_IDLENESS_10CYCLE
  • LL_SPI_SS_IDLENESS_11CYCLE
  • LL_SPI_SS_IDLENESS_12CYCLE
  • LL_SPI_SS_IDLENESS_13CYCLE
  • LL_SPI_SS_IDLENESS_14CYCLE
  • LL_SPI_SS_IDLENESS_15CYCLE

Definition at line 694 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI Mode (Master or Slave)

Reference Manual to LL API cross reference:
CFG2 MASTER LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 639 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Set NSS Mode.

Reference Manual to LL API cross reference:
CFG2 SSM LL_SPI_GetNSSMode
CFG2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 1604 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity ( SPI_TypeDef * SPIx )

Get NSS polarity.

Reference Manual to LL API cross reference:
CFG2 SSIOP LL_SPI_GetNSSPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_POLARITY_LOW
  • LL_SPI_NSS_POLARITY_HIGH

Definition at line 1179 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE uint32_t LL_SPI_GetReloadSize ( SPI_TypeDef * SPIx )

Get reload transfer size.

Note:
Count is the number of frame to be transferred
Reference Manual to LL API cross reference:
CR2 TSER LL_SPI_GetReloadSize
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFF

Definition at line 799 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern ( SPI_TypeDef * SPIx )

Get Rx CRC Initialization Pattern.

Reference Manual to LL API cross reference:
CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
  • LL_SPI_RXCRCINIT_ALL_ONES_PATTERN

Definition at line 877 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get Serial protocol used.

Reference Manual to LL API cross reference:
CFG2 SP LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 1092 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get Transfer Bit Order.

Reference Manual to LL API cross reference:
CFG2 LSBFRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 1249 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_GetTransferBitOrder().

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get Transfer Mode.

Reference Manual to LL API cross reference:
CR1 HDDIR LL_SPI_GetTransferDirection
CFG2 COMM LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_TX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 1286 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferSize ( SPI_TypeDef * SPIx )

Get transfer size.

Note:
Count is the number of frame to be transferred
Reference Manual to LL API cross reference:
CR2 TSIZE LL_SPI_GetTransferSize
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFF

Definition at line 774 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern ( SPI_TypeDef * SPIx )

Get Tx CRC Initialization Pattern.

Reference Manual to LL API cross reference:
CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
  • LL_SPI_TXCRCINIT_ALL_ONES_PATTERN

Definition at line 850 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration ( SPI_TypeDef * SPIx )

Get Underrun behavior.

Reference Manual to LL API cross reference:
CFG1 UDRCFG LL_SPI_GetUDRConfiguration
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_UDR_CONFIG_REGISTER_PATTERN
  • LL_SPI_UDR_CONFIG_LAST_RECEIVED
  • LL_SPI_UDR_CONFIG_LAST_TRANSMITTED

Definition at line 1034 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection ( SPI_TypeDef * SPIx )

Get Underrun Detection method.

Reference Manual to LL API cross reference:
CFG1 UDRDET LL_SPI_GetUDRDetection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
  • LL_SPI_UDR_DETECT_END_DATA_FRAME
  • LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS

Definition at line 1064 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer ( SPI_TypeDef * SPIx )

Check if there is an unfinished master transfer.

Reference Manual to LL API cross reference:
CR1 CSTART LL_SPI_IsMasterTransferActive
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 971 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveTransfer().

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 541 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_SPI_Init().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Reference Manual to LL API cross reference:
CFG1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1489 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC ( SPI_TypeDef * SPIx )

Check if Enable CRC computation on 33/17 bits is enabled.

Reference Manual to LL API cross reference:
CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 938 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl ( SPI_TypeDef * SPIx )

Check if GPIO control is active.

Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 611 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledGPIOControl().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock ( SPI_TypeDef * SPIx )

Check if the AF configuration is locked.

Reference Manual to LL API cross reference:
CR1 IOLOCK LL_SPI_IsEnabledIOLock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 823 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIOLock().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap ( SPI_TypeDef * SPIx )

Check if MOSI and MISO pin are swapped.

Reference Manual to LL API cross reference:
CFG2 IOSWP LL_SPI_IsEnabledIOSwap
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 576 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIOSwap().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend ( SPI_TypeDef * SPIx )

Check if Master Rx auto suspend is activated.

Reference Manual to LL API cross reference:
CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1004 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Reference Manual to LL API cross reference:
CFG2 SSOM LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1641 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Baudrate
 | ) |  |

Set Baudrate Prescaler.

Note:
This configuration can not be changed when SPI is enabled. SPI BaudRate = fPCLK/Pescaler.
Reference Manual to LL API cross reference:
CFG1 MBR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Baudrate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 1201 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set Clock phase.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 1108 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set Clock polarity.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 1137 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 CRCSIZE LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_4BIT
  • LL_SPI_CRC_5BIT
  • LL_SPI_CRC_6BIT
  • LL_SPI_CRC_7BIT
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_9BIT
  • LL_SPI_CRC_10BIT
  • LL_SPI_CRC_11BIT
  • LL_SPI_CRC_12BIT
  • LL_SPI_CRC_13BIT
  • LL_SPI_CRC_14BIT
  • LL_SPI_CRC_15BIT
  • LL_SPI_CRC_16BIT
  • LL_SPI_CRC_17BIT
  • LL_SPI_CRC_18BIT
  • LL_SPI_CRC_19BIT
  • LL_SPI_CRC_20BIT
  • LL_SPI_CRC_21BIT
  • LL_SPI_CRC_22BIT
  • LL_SPI_CRC_23BIT
  • LL_SPI_CRC_24BIT
  • LL_SPI_CRC_25BIT
  • LL_SPI_CRC_26BIT
  • LL_SPI_CRC_27BIT
  • LL_SPI_CRC_28BIT
  • LL_SPI_CRC_29BIT
  • LL_SPI_CRC_30BIT
  • LL_SPI_CRC_31BIT
  • LL_SPI_CRC_32BIT
Return values:
None

Definition at line 1531 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Frame Data Size.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 DSIZE LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
  • LL_SPI_DATAWIDTH_17BIT
  • LL_SPI_DATAWIDTH_18BIT
  • LL_SPI_DATAWIDTH_19BIT
  • LL_SPI_DATAWIDTH_20BIT
  • LL_SPI_DATAWIDTH_21BIT
  • LL_SPI_DATAWIDTH_22BIT
  • LL_SPI_DATAWIDTH_23BIT
  • LL_SPI_DATAWIDTH_24BIT
  • LL_SPI_DATAWIDTH_25BIT
  • LL_SPI_DATAWIDTH_26BIT
  • LL_SPI_DATAWIDTH_27BIT
  • LL_SPI_DATAWIDTH_28BIT
  • LL_SPI_DATAWIDTH_29BIT
  • LL_SPI_DATAWIDTH_30BIT
  • LL_SPI_DATAWIDTH_31BIT
  • LL_SPI_DATAWIDTH_32BIT
Return values:
None

Definition at line 1359 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of FIFO that triggers a transfer event.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 FTHLV LL_SPI_SetFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_FIFO_TH_01DATA
  • LL_SPI_FIFO_TH_02DATA
  • LL_SPI_FIFO_TH_03DATA
  • LL_SPI_FIFO_TH_04DATA
  • LL_SPI_FIFO_TH_05DATA
  • LL_SPI_FIFO_TH_06DATA
  • LL_SPI_FIFO_TH_07DATA
  • LL_SPI_FIFO_TH_08DATA
  • LL_SPI_FIFO_TH_09DATA
  • LL_SPI_FIFO_TH_10DATA
  • LL_SPI_FIFO_TH_11DATA
  • LL_SPI_FIFO_TH_12DATA
  • LL_SPI_FIFO_TH_13DATA
  • LL_SPI_FIFO_TH_14DATA
  • LL_SPI_FIFO_TH_15DATA
  • LL_SPI_FIFO_TH_16DATA
Return values:
None

Definition at line 1428 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_SetFIFOThreshold().

__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | HalfDuplexDirection
 | ) |  |

Set direction for Half-Duplex Mode.

Note:
In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 HDDIR LL_SPI_SetHalfDuplexDirection
Parameters:
SPIx SPI Instance
HalfDuplexDirection This parameter can be one of the following values:
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 1303 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetInterDataIdleness | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | MasterInterDataIdleness
 | ) |  |

Configure the idleness applied by master between data frame.

Reference Manual to LL API cross reference:
CFG2 MIDI LL_SPI_SetInterDataIdleness
Parameters:
SPIx SPI Instance
MasterInterDataIdleness This parameter can be one of the following values:
  • LL_SPI_ID_IDLENESS_00CYCLE
  • LL_SPI_ID_IDLENESS_01CYCLE
  • LL_SPI_ID_IDLENESS_02CYCLE
  • LL_SPI_ID_IDLENESS_03CYCLE
  • LL_SPI_ID_IDLENESS_04CYCLE
  • LL_SPI_ID_IDLENESS_05CYCLE
  • LL_SPI_ID_IDLENESS_06CYCLE
  • LL_SPI_ID_IDLENESS_07CYCLE
  • LL_SPI_ID_IDLENESS_08CYCLE
  • LL_SPI_ID_IDLENESS_09CYCLE
  • LL_SPI_ID_IDLENESS_10CYCLE
  • LL_SPI_ID_IDLENESS_11CYCLE
  • LL_SPI_ID_IDLENESS_12CYCLE
  • LL_SPI_ID_IDLENESS_13CYCLE
  • LL_SPI_ID_IDLENESS_14CYCLE
  • LL_SPI_ID_IDLENESS_15CYCLE
Return values:
None

Definition at line 722 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetInternalSSLevel | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | SSLevel
 | ) |  |

Set internal SS input level ignoring what comes from PIN.

Note:
This configuration has effect only with config LL_SPI_NSS_SOFT
Reference Manual to LL API cross reference:
CR1 SSI LL_SPI_SetInternalSSLevel
Parameters:
SPIx SPI Instance
SSLevel This parameter can be one of the following values:
  • LL_SPI_SS_LEVEL_HIGH
  • LL_SPI_SS_LEVEL_LOW
Return values:
None

Definition at line 892 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetMasterSSIdleness | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | MasterSSIdleness
 | ) |  |

Configure the Idleness applied by master between active edge of SS and first send data.

Reference Manual to LL API cross reference:
CFG2 MSSI LL_SPI_SetMasterSSIdleness
Parameters:
SPIx SPI Instance
MasterSSIdleness This parameter can be one of the following values:
  • LL_SPI_SS_IDLENESS_00CYCLE
  • LL_SPI_SS_IDLENESS_01CYCLE
  • LL_SPI_SS_IDLENESS_02CYCLE
  • LL_SPI_SS_IDLENESS_03CYCLE
  • LL_SPI_SS_IDLENESS_04CYCLE
  • LL_SPI_SS_IDLENESS_05CYCLE
  • LL_SPI_SS_IDLENESS_06CYCLE
  • LL_SPI_SS_IDLENESS_07CYCLE
  • LL_SPI_SS_IDLENESS_08CYCLE
  • LL_SPI_SS_IDLENESS_09CYCLE
  • LL_SPI_SS_IDLENESS_10CYCLE
  • LL_SPI_SS_IDLENESS_11CYCLE
  • LL_SPI_SS_IDLENESS_12CYCLE
  • LL_SPI_SS_IDLENESS_13CYCLE
  • LL_SPI_SS_IDLENESS_14CYCLE
  • LL_SPI_SS_IDLENESS_15CYCLE
Return values:
None

Definition at line 667 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI Mode to Master or Slave.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 MASTER LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 626 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS Mode.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 SSM LL_SPI_SetNSSMode
CFG2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 1589 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSSPolarity
 | ) |  |

Set NSS polarity.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 SSIOP LL_SPI_SetNSSPolarity
Parameters:
SPIx SPI Instance
NSSPolarity This parameter can be one of the following values:
  • LL_SPI_NSS_POLARITY_LOW
  • LL_SPI_NSS_POLARITY_HIGH
Return values:
None

Definition at line 1166 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetReloadSize | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Count
 | ) |  |

Set reload transfer size.

Note:
Count is the number of frame to be transferred
Reference Manual to LL API cross reference:
CR2 TSER LL_SPI_SetReloadSize
Parameters:
SPIx | SPI Instance
Count | 0..0xFFFF
Return values:
None

Definition at line 787 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | RXCRCInitAll
 | ) |  |

Set Rx CRC Initialization Pattern.

Reference Manual to LL API cross reference:
CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
Parameters:
SPIx SPI Instance
RXCRCInitAll This parameter can be one of the following values:
  • LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
  • LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
Return values:
None

Definition at line 864 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set Serial protocol used.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG2 SP LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 1079 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set Transfer Bit Order.

Note:
This configuration can not be changed when SPI is enabled. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CFG2 LSBFRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 1236 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_SetTransferBitOrder().

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set Transfer Mode.

Note:
This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
Reference Manual to LL API cross reference:
CR1 HDDIR LL_SPI_SetTransferDirection
CFG2 COMM LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_TX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 1268 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferSize | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Count
 | ) |  |

Set transfer size.

Note:
Count is the number of frame to be transferred
Reference Manual to LL API cross reference:
CR2 TSIZE LL_SPI_SetTransferSize
Parameters:
SPIx | SPI Instance
Count | 0..0xFFFF
Return values:
None

Definition at line 762 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TXCRCInitAll
 | ) |  |

Set Tx CRC Initialization Pattern.

Reference Manual to LL API cross reference:
CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
Parameters:
SPIx SPI Instance
TXCRCInitAll This parameter can be one of the following values:
  • LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
  • LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
Return values:
None

Definition at line 837 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetUDRConfiguration | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | UDRConfig
 | ) |  |

Set Underrun behavior.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 UDRCFG LL_SPI_SetUDRConfiguration
Parameters:
SPIx SPI Instance
UDRConfig This parameter can be one of the following values:
  • LL_SPI_UDR_CONFIG_REGISTER_PATTERN
  • LL_SPI_UDR_CONFIG_LAST_RECEIVED
  • LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
Return values:
None

Definition at line 1020 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetUDRDetection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | UDRDetection
 | ) |  |

Set Underrun Detection method.

Note:
This configuration can not be changed when SPI is enabled.
Reference Manual to LL API cross reference:
CFG1 UDRDET LL_SPI_SetUDRDetection
Parameters:
SPIx SPI Instance
UDRDetection This parameter can be one of the following values:
  • LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
  • LL_SPI_UDR_DETECT_END_DATA_FRAME
  • LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
Return values:
None

Definition at line 1050 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_StartMasterTransfer ( SPI_TypeDef * SPIx )

Start effective transfer on wire for Master configuration.

Reference Manual to LL API cross reference:
CR1 CSTART LL_SPI_StartMasterTransfer
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 960 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_StartTransfer().

__STATIC_INLINE void LL_SPI_SuspendMasterTransfer ( SPI_TypeDef * SPIx )

Suspend an ongoing transfer for Master configuration.

Reference Manual to LL API cross reference:
CR1 CSUSP LL_SPI_SuspendMasterTransfer
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 949 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXP (SPI_TypeDef *SPIx)
Check if there is enough data in FIFO to read a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXP (SPI_TypeDef *SPIx)
Check if there is enough space in FIFO to hold a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_DXP (SPI_TypeDef *SPIx)
Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_EOT (SPI_TypeDef *SPIx)
Check that end of transfer event occured.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXTF (SPI_TypeDef *SPIx)
Check that all required data has been filled in the fifo according to transfer size.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get Underrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get Mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get Overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get TI Frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TSER (SPI_TypeDef *SPIx)
Check if the additional number of data has been reloaded.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_SUSP (SPI_TypeDef *SPIx)
Check if a suspend operation is done.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXC (SPI_TypeDef *SPIx)
Check if last TxFIFO or CRC frame transmission is completed.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXWNE (SPI_TypeDef *SPIx)
Check if at least one 32-bit data is available in RxFIFO.
__STATIC_INLINE uint32_t | LL_SPI_GetRemainingDataFrames (SPI_TypeDef *SPIx)
Get number of data framed remaining in current TSIZE.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOPackingLevel (SPI_TypeDef *SPIx)
Get RxFIFO packing Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_EOT (SPI_TypeDef *SPIx)
Clear End Of Transfer flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_TXTF (SPI_TypeDef *SPIx)
Clear TXTF flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear Underrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear Overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear Mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear Frame format error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_TSER (SPI_TypeDef *SPIx)
Clear TSER flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_SUSP (SPI_TypeDef *SPIx)
Clear SUSP flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
IFCR CRCEC LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1884 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_EOT ( SPI_TypeDef * SPIx )

Clear End Of Transfer flag.

Reference Manual to LL API cross reference:
IFCR EOTC LL_SPI_ClearFlag_EOT
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1840 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear Frame format error flag.

Reference Manual to LL API cross reference:
IFCR TIFREC LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1906 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_FRE().

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear Mode fault error flag.

Reference Manual to LL API cross reference:
IFCR MODFC LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1895 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear Overrun error flag.

Reference Manual to LL API cross reference:
IFCR OVRC LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1873 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_OVR().

__STATIC_INLINE void LL_SPI_ClearFlag_SUSP ( SPI_TypeDef * SPIx )

Clear SUSP flag.

Reference Manual to LL API cross reference:
IFCR SUSPC LL_SPI_ClearFlag_SUSP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1928 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_TSER ( SPI_TypeDef * SPIx )

Clear TSER flag.

Reference Manual to LL API cross reference:
IFCR TSERFC LL_SPI_ClearFlag_TSER
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1917 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_TXTF ( SPI_TypeDef * SPIx )

Clear TXTF flag.

Reference Manual to LL API cross reference:
IFCR TXTFC LL_SPI_ClearFlag_TXTF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1851 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear Underrun error flag.

Reference Manual to LL API cross reference:
IFCR UDRC LL_SPI_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1862 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_UDR().

__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames ( SPI_TypeDef * SPIx )

Get number of data framed remaining in current TSIZE.

Reference Manual to LL API cross reference:
SR CTSIZE LL_SPI_GetRemainingDataFrames
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFF

Definition at line 1814 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel ( SPI_TypeDef * SPIx )

Get RxFIFO packing Level.

Reference Manual to LL API cross reference:
SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_0PACKET
  • LL_SPI_RX_FIFO_1PACKET
  • LL_SPI_RX_FIFO_2PACKET
  • LL_SPI_RX_FIFO_3PACKET

Definition at line 1829 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCE LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1726 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP ( SPI_TypeDef * SPIx )

Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet.

Reference Manual to LL API cross reference:
SR DXP LL_SPI_IsActiveFlag_DXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1682 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT ( SPI_TypeDef * SPIx )

Check that end of transfer event occured.

Reference Manual to LL API cross reference:
SR EOT LL_SPI_IsActiveFlag_EOT
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1693 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get TI Frame format error flag.

Reference Manual to LL API cross reference:
SR TIFRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1759 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get Mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1737 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get Overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1748 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP ( SPI_TypeDef * SPIx )

Check if there is enough data in FIFO to read a full packet.

Reference Manual to LL API cross reference:
SR RXP LL_SPI_IsActiveFlag_RXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1660 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_RXP().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE ( SPI_TypeDef * SPIx )

Check if at least one 32-bit data is available in RxFIFO.

Reference Manual to LL API cross reference:
SR RXWNE LL_SPI_IsActiveFlag_RXWNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1803 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP ( SPI_TypeDef * SPIx )

Check if a suspend operation is done.

Reference Manual to LL API cross reference:
SR SUSP LL_SPI_IsActiveFlag_SUSP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1781 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER ( SPI_TypeDef * SPIx )

Check if the additional number of data has been reloaded.

Reference Manual to LL API cross reference:
SR TSERF LL_SPI_IsActiveFlag_TSER
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1770 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC ( SPI_TypeDef * SPIx )

Check if last TxFIFO or CRC frame transmission is completed.

Reference Manual to LL API cross reference:
SR TXC LL_SPI_IsActiveFlag_TXC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1792 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP ( SPI_TypeDef * SPIx )

Check if there is enough space in FIFO to hold a full packet.

Reference Manual to LL API cross reference:
SR TXP LL_SPI_IsActiveFlag_TXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 1671 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_TXP().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF ( SPI_TypeDef * SPIx )

Check that all required data has been filled in the fifo according to transfer size.

Reference Manual to LL API cross reference:
SR TXTF LL_SPI_IsActiveFlag_TXTF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1704 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get Underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_SPI_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1715 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_UDR().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_RXP (SPI_TypeDef *SPIx)
Enable Rx Packet available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TXP (SPI_TypeDef *SPIx)
Enable Tx Packet space available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_DXP (SPI_TypeDef *SPIx)
Enable Duplex Packet available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_EOT (SPI_TypeDef *SPIx)
Enable End Of Transfer IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TXTF (SPI_TypeDef *SPIx)
Enable TXTF IT.
__STATIC_INLINE void | LL_SPI_EnableIT_UDR (SPI_TypeDef *SPIx)
Enable Underrun IT.
__STATIC_INLINE void | LL_SPI_EnableIT_OVR (SPI_TypeDef *SPIx)
Enable Overrun IT.
__STATIC_INLINE void | LL_SPI_EnableIT_CRCERR (SPI_TypeDef *SPIx)
Enable CRC Error IT.
__STATIC_INLINE void | LL_SPI_EnableIT_FRE (SPI_TypeDef *SPIx)
Enable TI Frame Format Error IT.
__STATIC_INLINE void | LL_SPI_EnableIT_MODF (SPI_TypeDef *SPIx)
Enable MODF IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TSER (SPI_TypeDef *SPIx)
Enable TSER reload IT.
__STATIC_INLINE void | LL_SPI_DisableIT_RXP (SPI_TypeDef *SPIx)
Disable Rx Packet available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TXP (SPI_TypeDef *SPIx)
Disable Tx Packet space available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_DXP (SPI_TypeDef *SPIx)
Disable Duplex Packet available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_EOT (SPI_TypeDef *SPIx)
Disable End Of Transfer IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TXTF (SPI_TypeDef *SPIx)
Disable TXTF IT.
__STATIC_INLINE void | LL_SPI_DisableIT_UDR (SPI_TypeDef *SPIx)
Disable Underrun IT.
__STATIC_INLINE void | LL_SPI_DisableIT_OVR (SPI_TypeDef *SPIx)
Disable Overrun IT.
__STATIC_INLINE void | LL_SPI_DisableIT_CRCERR (SPI_TypeDef *SPIx)
Disable CRC Error IT.
__STATIC_INLINE void | LL_SPI_DisableIT_FRE (SPI_TypeDef *SPIx)
Disable TI Frame Format Error IT.
__STATIC_INLINE void | LL_SPI_DisableIT_MODF (SPI_TypeDef *SPIx)
Disable MODF IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TSER (SPI_TypeDef *SPIx)
Disable TSER reload IT.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXP (SPI_TypeDef *SPIx)
Check if Rx Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXP (SPI_TypeDef *SPIx)
Check if Tx Packet space available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_DXP (SPI_TypeDef *SPIx)
Check if Duplex Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_EOT (SPI_TypeDef *SPIx)
Check if End Of Transfer IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXTF (SPI_TypeDef *SPIx)
Check if TXTF IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_UDR (SPI_TypeDef *SPIx)
Check if Underrun IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_OVR (SPI_TypeDef *SPIx)
Check if Overrun IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_CRCERR (SPI_TypeDef *SPIx)
Check if CRC Error IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_FRE (SPI_TypeDef *SPIx)
Check if TI Frame Format Error IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_MODF (SPI_TypeDef *SPIx)
Check if MODF IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TSER (SPI_TypeDef *SPIx)
Check if TSER reload IT is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_CRCERR ( SPI_TypeDef * SPIx )

Disable CRC Error IT.

Reference Manual to LL API cross reference:
IER CRCEIE LL_SPI_DisableIT_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2145 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_DXP ( SPI_TypeDef * SPIx )

Disable Duplex Packet available IT.

Reference Manual to LL API cross reference:
IER DXPIE LL_SPI_DisableIT_DXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2090 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_EOT ( SPI_TypeDef * SPIx )

Disable End Of Transfer IT.

Reference Manual to LL API cross reference:
IER EOTIE LL_SPI_DisableIT_EOT
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2101 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_FRE ( SPI_TypeDef * SPIx )

Disable TI Frame Format Error IT.

Reference Manual to LL API cross reference:
IER TIFREIE LL_SPI_DisableIT_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2156 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_FRE().

__STATIC_INLINE void LL_SPI_DisableIT_MODF ( SPI_TypeDef * SPIx )

Disable MODF IT.

Reference Manual to LL API cross reference:
IER MODFIE LL_SPI_DisableIT_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2167 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_OVR ( SPI_TypeDef * SPIx )

Disable Overrun IT.

Reference Manual to LL API cross reference:
IER OVRIE LL_SPI_DisableIT_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2134 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_OVR().

__STATIC_INLINE void LL_SPI_DisableIT_RXP ( SPI_TypeDef * SPIx )

Disable Rx Packet available IT.

Reference Manual to LL API cross reference:
IER RXPIE LL_SPI_DisableIT_RXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2068 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_RXP().

__STATIC_INLINE void LL_SPI_DisableIT_TSER ( SPI_TypeDef * SPIx )

Disable TSER reload IT.

Reference Manual to LL API cross reference:
IER TSERFIE LL_SPI_DisableIT_TSER
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2178 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_TXP ( SPI_TypeDef * SPIx )

Disable Tx Packet space available IT.

Reference Manual to LL API cross reference:
IER TXPIE LL_SPI_DisableIT_TXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2079 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_TXP().

__STATIC_INLINE void LL_SPI_DisableIT_TXTF ( SPI_TypeDef * SPIx )

Disable TXTF IT.

Reference Manual to LL API cross reference:
IER TXTFIE LL_SPI_DisableIT_TXTF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2112 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_UDR ( SPI_TypeDef * SPIx )

Disable Underrun IT.

Reference Manual to LL API cross reference:
IER UDRIE LL_SPI_DisableIT_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2123 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_UDR().

__STATIC_INLINE void LL_SPI_EnableIT_CRCERR ( SPI_TypeDef * SPIx )

Enable CRC Error IT.

Reference Manual to LL API cross reference:
IER CRCEIE LL_SPI_EnableIT_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2024 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_DXP ( SPI_TypeDef * SPIx )

Enable Duplex Packet available IT.

Reference Manual to LL API cross reference:
IER DXPIE LL_SPI_EnableIT_DXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1969 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_EOT ( SPI_TypeDef * SPIx )

Enable End Of Transfer IT.

Reference Manual to LL API cross reference:
IER EOTIE LL_SPI_EnableIT_EOT
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1980 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_FRE ( SPI_TypeDef * SPIx )

Enable TI Frame Format Error IT.

Reference Manual to LL API cross reference:
IER TIFREIE LL_SPI_EnableIT_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2035 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_FRE().

__STATIC_INLINE void LL_SPI_EnableIT_MODF ( SPI_TypeDef * SPIx )

Enable MODF IT.

Reference Manual to LL API cross reference:
IER MODFIE LL_SPI_EnableIT_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2046 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_OVR ( SPI_TypeDef * SPIx )

Enable Overrun IT.

Reference Manual to LL API cross reference:
IER OVRIE LL_SPI_EnableIT_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2013 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_OVR().

__STATIC_INLINE void LL_SPI_EnableIT_RXP ( SPI_TypeDef * SPIx )

Enable Rx Packet available IT.

Reference Manual to LL API cross reference:
IER RXPIE LL_SPI_EnableIT_RXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1947 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_RXP().

__STATIC_INLINE void LL_SPI_EnableIT_TSER ( SPI_TypeDef * SPIx )

Enable TSER reload IT.

Reference Manual to LL API cross reference:
IER TSERFIE LL_SPI_EnableIT_TSER
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2057 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_TXP ( SPI_TypeDef * SPIx )

Enable Tx Packet space available IT.

Reference Manual to LL API cross reference:
IER TXPIE LL_SPI_EnableIT_TXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1958 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_TXP().

__STATIC_INLINE void LL_SPI_EnableIT_TXTF ( SPI_TypeDef * SPIx )

Enable TXTF IT.

Reference Manual to LL API cross reference:
IER TXTFIE LL_SPI_EnableIT_TXTF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1991 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_UDR ( SPI_TypeDef * SPIx )

Enable Underrun IT.

Reference Manual to LL API cross reference:
IER UDRIE LL_SPI_EnableIT_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2002 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_UDR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR ( SPI_TypeDef * SPIx )

Check if CRC Error IT is enabled.

Reference Manual to LL API cross reference:
IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2266 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP ( SPI_TypeDef * SPIx )

Check if Duplex Packet available IT is enabled.

Reference Manual to LL API cross reference:
IER DXPIE LL_SPI_IsEnabledIT_DXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2211 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT ( SPI_TypeDef * SPIx )

Check if End Of Transfer IT is enabled.

Reference Manual to LL API cross reference:
IER EOTIE LL_SPI_IsEnabledIT_EOT
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2222 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE ( SPI_TypeDef * SPIx )

Check if TI Frame Format Error IT is enabled.

Reference Manual to LL API cross reference:
IER TIFREIE LL_SPI_IsEnabledIT_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2277 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_FRE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF ( SPI_TypeDef * SPIx )

Check if MODF IT is enabled.

Reference Manual to LL API cross reference:
IER MODFIE LL_SPI_IsEnabledIT_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2288 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR ( SPI_TypeDef * SPIx )

Check if Overrun IT is enabled.

Reference Manual to LL API cross reference:
IER OVRIE LL_SPI_IsEnabledIT_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2255 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP ( SPI_TypeDef * SPIx )

Check if Rx Packet available IT is enabled.

Reference Manual to LL API cross reference:
IER RXPIE LL_SPI_IsEnabledIT_RXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2189 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_RXP().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER ( SPI_TypeDef * SPIx )

Check if TSER reload IT is enabled.

Reference Manual to LL API cross reference:
IER TSERFIE LL_SPI_IsEnabledIT_TSER
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2299 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP ( SPI_TypeDef * SPIx )

Check if Tx Packet space available IT is enabled.

Reference Manual to LL API cross reference:
IER TXPIE LL_SPI_IsEnabledIT_TXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2200 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_TXP().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF ( SPI_TypeDef * SPIx )

Check if TXTF IT is enabled.

Reference Manual to LL API cross reference:
IER TXTFIE LL_SPI_IsEnabledIT_TXTF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2233 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR ( SPI_TypeDef * SPIx )

Check if Underrun IT is enabled.

Reference Manual to LL API cross reference:
IER UDRIE LL_SPI_IsEnabledIT_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2244 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_UDR().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2329 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_RX().

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2362 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_TX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2318 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_RX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2351 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2340 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 2373 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_TX().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DATA_Management

Functions
DATA_Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint32_t | LL_SPI_ReceiveData32 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calcul.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calcul.
__STATIC_INLINE void | LL_SPI_SetUDRPattern (SPI_TypeDef *SPIx, uint32_t Pattern)
Set the underrun pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRPattern (SPI_TypeDef *SPIx)
Get the underrun pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calcul.

Reference Manual to LL API cross reference:
CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 2478 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 2512 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 2523 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern ( SPI_TypeDef * SPIx )

Get the underrun pattern.

Reference Manual to LL API cross reference:
UDRDR UDRDR LL_SPI_GetUDRPattern
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 2501 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read Data Register.

Reference Manual to LL API cross reference:
RXDR . LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFF

Definition at line 2403 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData16().

__STATIC_INLINE uint32_t LL_SPI_ReceiveData32 ( SPI_TypeDef * SPIx )

Read Data Register.

Reference Manual to LL API cross reference:
RXDR . LL_SPI_ReceiveData32
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 2414 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData32().

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read Data Register.

Reference Manual to LL API cross reference:
RXDR . LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
0..0xFF

Definition at line 2392 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calcul.

Reference Manual to LL API cross reference:
CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | 0..0xFFFFFFFF
Return values:
None

Definition at line 2467 of file stm32h7xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetUDRPattern | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Pattern
 | ) |  |

Set the underrun pattern.

Reference Manual to LL API cross reference:
UDRDR UDRDR LL_SPI_SetUDRPattern
Parameters:
SPIx | SPI Instance
Pattern | 0..0xFFFFFFFF
Return values:
None

Definition at line 2490 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write Data Register.

Reference Manual to LL API cross reference:
TXDR . LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | 0..0xFFFF
Return values:
None

Definition at line 2438 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_TransmitData16().

__STATIC_INLINE void LL_SPI_TransmitData32 | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TxData
 | ) |  |

Write Data Register.

Reference Manual to LL API cross reference:
TXDR . LL_SPI_TransmitData32
Parameters:
SPIx | SPI Instance
TxData | 0..0xFFFFFFFF
Return values:
None

Definition at line 2455 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_TransmitData32().

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write Data Register.

Reference Manual to LL API cross reference:
TXDR . LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | 0..0xFF
Return values:
None

Definition at line 2426 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions | I2S Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x00 and Max_Data=0xFF
Note:
PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
Parameters:
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 707 of file stm32h7xx_ll_spi.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 542 of file stm32h7xx_ll_spi.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 558 of file stm32h7xx_ll_spi.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CKPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_ENABLE, LL_I2S_STANDARD_PCM_LONG, LL_I2S_STANDARD_PCM_SHORT, LL_RCC_GetSPIClockFreq(), LL_RCC_SPI123_CLKSOURCE, LL_RCC_SPI6_CLKSOURCE, LL_SPI_IsEnabled(), LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 684 of file stm32h7xx_ll_spi.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 243 of file stm32h7xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_PERIPH_SPI3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, LL_APB2_GRP1_PERIPH_SPI4, LL_APB2_GRP1_PERIPH_SPI5, LL_APB2_GRP1_ReleaseReset(), LL_APB4_GRP1_ForceReset(), LL_APB4_GRP1_PERIPH_SPI6, and LL_APB4_GRP1_ReleaseReset().

Referenced by LL_I2S_DeInit().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 334 of file stm32h7xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATEPRESCALER, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_GetNSSPolarity(), LL_SPI_IsEnabled(), LL_SPI_MODE_MASTER, LL_SPI_NSS_POLARITY_LOW, LL_SPI_NSS_SOFT, LL_SPI_SetCRCPolynomial(), LL_SPI_SetInternalSSLevel(), LL_SPI_SS_LEVEL_HIGH, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 421 of file stm32h7xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Private Constants

Defines
I2S Private Constants
I2S

Defines

#define I2S_I2SCFGR_CLEAR_MASK

Define Documentation

#define I2S_I2SCFGR_CLEAR_MASK
Value:
(SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
                                                      SPI_I2SCFGR_DATFMT  | SPI_I2SCFGR_CKPOL  | \
                                                      SPI_I2SCFGR_I2SSTD  | SPI_I2SCFGR_MCKOE  | \
                                                      SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )

Definition at line 459 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CHANNEL_LENGTH_TYPE
#define | IS_LL_I2S_CKPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)
#define | IS_LL_I2S_FIFO_TH
#define | IS_LL_I2S_BIT_ORDER(__VALUE__)

Define Documentation

#define IS_LL_I2S_AUDIO_FREQ ( __VALUE__ )
Value:
((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)                \
                                                 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K))             \
                                                 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))

Definition at line 500 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_BIT_ORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_LSB_FIRST)                   \
                                                 || ((__VALUE__) == LL_I2S_MSB_FIRST))

Definition at line 518 of file stm32h7xx_ll_spi.c.

#define IS_LL_I2S_CHANNEL_LENGTH_TYPE
Value:
(__VALUE__)  (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH)    \
                                                 || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))

Definition at line 478 of file stm32h7xx_ll_spi.c.

#define IS_LL_I2S_CKPOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_POLARITY_LOW)               \
                                                 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))

Definition at line 481 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_DATAFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_DATAFORMAT_16B)              \
                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED)     \
                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)              \
                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))

Definition at line 472 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_FIFO_TH
Value:
(__VALUE__)              (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA)       \
                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))

Definition at line 509 of file stm32h7xx_ll_spi.c.

#define IS_LL_I2S_MCLK_OUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE)          \
                                                 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))

Definition at line 497 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MODE_SLAVE_TX)               \
                                                 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)               \
                                                 || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX)      \
                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX)              \
                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)              \
                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))

Definition at line 490 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_PRESCALER_LINEAR ( __VALUE__ ) ((__VALUE__) <= 0xFFUL)

Definition at line 504 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_PRESCALER_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN)       \
                                                 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))

Definition at line 506 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_STANDARD ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_STANDARD_PHILIPS)            \
                                                 || ((__VALUE__) == LL_I2S_STANDARD_MSB)                \
                                                 || ((__VALUE__) == LL_I2S_STANDARD_LSB)                \
                                                 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT)          \
                                                 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))

Definition at line 484 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_Init().

Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2S_InitTypeDef Struct Reference
I2S Exported Init structure

I2S Init structure definition. More...

#include <stm32h7xx_ll_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | ClockPolarity

Detailed Description

I2S Init structure definition.

Definition at line 2567 of file stm32h7xx_ll_spi.h.

Field Documentation

uint32_t LL_I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of Audio Frequency

Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity and unitary functions LL_I2S_SetPrescalerLinear() and LL_I2S_SetPrescalerParity() to set it.

Definition at line 2592 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::ClockPolarity

Specifies the idle state of the I2S clock. This parameter can be a value of Clock Polarity

This feature can be modified afterwards using unitary function LL_I2S_SetClockPolarity().

Definition at line 2599 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of Data Format

This feature can be modified afterwards using unitary function LL_I2S_SetDataFormat().

Definition at line 2580 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of MCLK Output

This feature can be modified afterwards using unitary functions LL_I2S_EnableMasterClock() or LL_I2S_DisableMasterClock.

Definition at line 2586 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of Operation Mode

This feature can be modified afterwards using unitary function LL_I2S_SetTransferMode().

Definition at line 2569 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

This feature can be modified afterwards using unitary function LL_I2S_SetStandard().

Definition at line 2574 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_spi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Format

Defines
Data Format
I2S Exported Constants

Defines

#define | LL_I2S_DATAFORMAT_16B (0x00000000UL)
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define LL_I2S_DATAFORMAT_16B (0x00000000UL)

Definition at line 2619 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Definition at line 2620 of file stm32h7xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

Definition at line 2621 of file stm32h7xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)

Definition at line 2622 of file stm32h7xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Definition at line 2623 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Type of Channel Length

Defines
Type of Channel Length
I2S Exported Constants

Defines

#define | LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
#define | LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)

Define Documentation

#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)

Definition at line 2632 of file stm32h7xx_ll_spi.h.

#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)

Definition at line 2631 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Polarity

Defines
Clock Polarity
I2S Exported Constants

Defines

#define | LL_I2S_POLARITY_LOW (0x00000000UL)
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Definition at line 2641 of file stm32h7xx_ll_spi.h.

#define LL_I2S_POLARITY_LOW (0x00000000UL)

Definition at line 2640 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | LL_I2S_STANDARD_PHILIPS (0x00000000UL)
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

Definition at line 2651 of file stm32h7xx_ll_spi.h.

#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

Definition at line 2650 of file stm32h7xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Definition at line 2653 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init().

#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

Definition at line 2652 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init().

#define LL_I2S_STANDARD_PHILIPS (0x00000000UL)

Definition at line 2649 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Operation Mode

Defines
Operation Mode
I2S Exported Constants

Defines

#define | LL_I2S_MODE_SLAVE_TX (0x00000000UL)
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

Define Documentation

#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

Definition at line 2666 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)

Definition at line 2665 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Definition at line 2664 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)

Definition at line 2663 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Definition at line 2662 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_TX (0x00000000UL)

Definition at line 2661 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Prescaler Factor

Defines
Prescaler Factor
I2S Exported Constants

Defines

#define | LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL)
#define | LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL)

Define Documentation

#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL)

Odd factor: Real divider value is = I2SDIV * 2

Definition at line 2674 of file stm32h7xx_ll_spi.h.

#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL)

Odd factor: Real divider value is = (I2SDIV * 2)+1

Definition at line 2675 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FIFO Threshold Level

Defines
FIFO Threshold Level
I2S Exported Constants

Defines

#define | LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
#define | LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
#define | LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
#define | LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
#define | LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
#define | LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
#define | LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
#define | LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)

Define Documentation

#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)

Definition at line 2683 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)

Definition at line 2684 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)

Definition at line 2685 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)

Definition at line 2686 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)

Definition at line 2687 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)

Definition at line 2688 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)

Definition at line 2689 of file stm32h7xx_ll_spi.h.

#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)

Definition at line 2690 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
I2S Exported Constants

Defines

#define | LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
#define | LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)

Define Documentation

#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)

Definition at line 2698 of file stm32h7xx_ll_spi.h.

#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)

Definition at line 2699 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MCLK Output

Defines
MCLK Output
I2S Exported Constants

Defines

#define | LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)

Define Documentation

#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)

Definition at line 2709 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)

Definition at line 2710 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Audio Frequency

Defines
Audio Frequency
I2S Exported Constants

Defines

#define | LL_I2S_AUDIOFREQ_192K 192000UL
#define | LL_I2S_AUDIOFREQ_96K 96000UL
#define | LL_I2S_AUDIOFREQ_48K 48000UL
#define | LL_I2S_AUDIOFREQ_44K 44100UL
#define | LL_I2S_AUDIOFREQ_32K 32000UL
#define | LL_I2S_AUDIOFREQ_22K 22050UL
#define | LL_I2S_AUDIOFREQ_16K 16000UL
#define | LL_I2S_AUDIOFREQ_11K 11025UL
#define | LL_I2S_AUDIOFREQ_8K 8000UL
#define | LL_I2S_AUDIOFREQ_DEFAULT 0UL

Define Documentation

#define LL_I2S_AUDIOFREQ_11K 11025UL

Audio Frequency configuration 11025 Hz

Definition at line 2726 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_16K 16000UL

Audio Frequency configuration 16000 Hz

Definition at line 2725 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_192K 192000UL

Audio Frequency configuration 192000 Hz

Definition at line 2719 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_22K 22050UL

Audio Frequency configuration 22050 Hz

Definition at line 2724 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_32K 32000UL

Audio Frequency configuration 32000 Hz

Definition at line 2723 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_44K 44100UL

Audio Frequency configuration 44100 Hz

Definition at line 2722 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_48K 48000UL

Audio Frequency configuration 48000 Hz

Definition at line 2721 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_8K 8000UL

Audio Frequency configuration 8000 Hz

Definition at line 2727 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_96K 96000UL

Audio Frequency configuration 96000 Hz

Definition at line 2720 of file stm32h7xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_DEFAULT 0UL

Audio Freq not specified. Register I2SDIV = 0

Definition at line 2728 of file stm32h7xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2S Exported Macros

Defines

#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Define Documentation

#define LL_I2S_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 2762 of file stm32h7xx_ll_spi.h.

#define LL_I2S_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 2754 of file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataLength)
Set I2S Data frame format.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S Data frame format.
__STATIC_INLINE void | LL_I2S_SetChannelLengthType (SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
Set I2S Channel Length Type.
__STATIC_INLINE uint32_t | LL_I2S_GetChannelLengthType (SPI_TypeDef *SPIx)
Get I2S Channel Length Type.
__STATIC_INLINE void | LL_I2S_EnableWordSelectInversion (SPI_TypeDef *SPIx)
Invert the default polarity of WS signal.
__STATIC_INLINE void | LL_I2S_DisableWordSelectInversion (SPI_TypeDef *SPIx)
Use the default polarity of WS signal.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledWordSelectInversion (SPI_TypeDef *SPIx)
Check if polarity of WS signal is inverted.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set 2S Clock Polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get 2S Clock Polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S config.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S config.
__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral and disable I2S mode.
__STATIC_INLINE void | LL_I2S_EnableIOSwap (SPI_TypeDef *SPIx)
Swap the SDO and SDI pin.
__STATIC_INLINE void | LL_I2S_DisableIOSwap (SPI_TypeDef *SPIx)
Restore default function for SDO and SDI pin.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOSwap (SPI_TypeDef *SPIx)
Check if SDO and SDI pin are swapped.
__STATIC_INLINE void | LL_I2S_EnableGPIOControl (SPI_TypeDef *SPIx)
Enable GPIO control.
__STATIC_INLINE void | LL_I2S_DisableGPIOControl (SPI_TypeDef *SPIx)
Disable GPIO control.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledGPIOControl (SPI_TypeDef *SPIx)
Check if GPIO control is active.
__STATIC_INLINE void | LL_I2S_EnableIOLock (SPI_TypeDef *SPIx)
Lock the AF configuration of associated IOs.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOLock (SPI_TypeDef *SPIx)
Check if the the SPI_CFG2 register is locked.
__STATIC_INLINE void | LL_I2S_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set Transfer Bit Order.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get Transfer Bit Order.
__STATIC_INLINE void | LL_I2S_StartTransfer (SPI_TypeDef *SPIx)
Start effective transfer on wire.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveTransfer (SPI_TypeDef *SPIx)
Check if there is an unfinished transfer.
__STATIC_INLINE void | LL_I2S_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of FIFO that triggers a transfer event.
__STATIC_INLINE uint32_t | LL_I2S_GetFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of FIFO that triggers a transfer event.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the Master Clock Output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the Master Clock Ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_Disable ( SPI_TypeDef * SPIx )

Disable I2S peripheral and disable I2S mode.

Reference Manual to LL API cross reference:
CR1 SPE LL_I2S_Disable
I2SCFGR I2SMOD LL_I2S_Disable
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 2998 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableGPIOControl ( SPI_TypeDef * SPIx )

Disable GPIO control.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_I2S_DisableGPIOControl
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3058 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableGPIOControl().

__STATIC_INLINE void LL_I2S_DisableIOSwap ( SPI_TypeDef * SPIx )

Restore default function for SDO and SDI pin.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG2 IOSWP LL_I2S_DisableIOSwap
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3023 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIOSwap().

__STATIC_INLINE void LL_I2S_DisableMasterClock ( SPI_TypeDef * SPIx )

Disable the Master Clock Ouput (Pin MCK)

Reference Manual to LL API cross reference:
I2SCFGR MCKOE LL_I2S_DisableMasterClock
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 3255 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableWordSelectInversion ( SPI_TypeDef * SPIx )

Use the default polarity of WS signal.

Reference Manual to LL API cross reference:
I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 2865 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_Enable ( SPI_TypeDef * SPIx )

Select I2S mode and Enable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SMOD LL_I2S_Enable
CR1 SPE LL_I2S_Enable
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 2985 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableGPIOControl ( SPI_TypeDef * SPIx )

Enable GPIO control.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_I2S_EnableGPIOControl
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3046 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableGPIOControl().

__STATIC_INLINE void LL_I2S_EnableIOLock ( SPI_TypeDef * SPIx )

Lock the AF configuration of associated IOs.

Note:
Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs. The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
Reference Manual to LL API cross reference:
CR1 IOLOCK LL_SPI_EnableIOLock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3082 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIOLock().

__STATIC_INLINE void LL_I2S_EnableIOSwap ( SPI_TypeDef * SPIx )

Swap the SDO and SDI pin.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG2 IOSWP LL_I2S_EnableIOSwap
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3011 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIOSwap().

__STATIC_INLINE void LL_I2S_EnableMasterClock ( SPI_TypeDef * SPIx )

Enable the Master Clock Output (Pin MCK)

Reference Manual to LL API cross reference:
I2SCFGR MCKOE LL_I2S_EnableMasterClock
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 3244 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableWordSelectInversion ( SPI_TypeDef * SPIx )

Invert the default polarity of WS signal.

Reference Manual to LL API cross reference:
I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
Parameters:
SPIx SPI Handle
Return values:
None

Definition at line 2854 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType ( SPI_TypeDef * SPIx )

Get I2S Channel Length Type.

Note:
This feature is usefull with SLAVE only
Reference Manual to LL API cross reference:
I2SCFGR FIXCH LL_I2S_GetChannelLengthType
Parameters:
SPIx SPI Handle
Return values:
Return value can be one of the following values:
  • LL_I2S_SLAVE_VARIABLE_CH_LENGTH
  • LL_I2S_SLAVE_FIXED_CH_LENGTH

Definition at line 2843 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity ( SPI_TypeDef * SPIx )

Get 2S Clock Polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_GetClockPolarity
Parameters:
SPIx SPI Handle
Return values:
Return value can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH

Definition at line 2903 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetDataFormat ( SPI_TypeDef * SPIx )

Get I2S Data frame format.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_GetDataFormat
I2SCFGR CHLEN LL_I2S_GetDataFormat
I2SCFGR DATFMT LL_I2S_GetDataFormat
Parameters:
SPIx SPI Handle
Return values:
Return value can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
  • LL_I2S_DATAFORMAT_32B

Definition at line 2814 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of FIFO that triggers a transfer event.

Reference Manual to LL API cross reference:
CFG1 FTHLV LL_I2S_GetFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_FIFO_TH_01DATA
  • LL_I2S_FIFO_TH_02DATA
  • LL_I2S_FIFO_TH_03DATA
  • LL_I2S_FIFO_TH_04DATA
  • LL_I2S_FIFO_TH_05DATA
  • LL_I2S_FIFO_TH_06DATA
  • LL_I2S_FIFO_TH_07DATA
  • LL_I2S_FIFO_TH_08DATA

Definition at line 3182 of file stm32h7xx_ll_spi.h.

References LL_SPI_GetFIFOThreshold().

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear ( SPI_TypeDef * SPIx )

Get I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
Parameters:
SPIx SPI Instance
Return values:
PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 3206 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity ( SPI_TypeDef * SPIx )

Get I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SCFGR ODD LL_I2S_GetPrescalerParity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD

Definition at line 3233 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetStandard ( SPI_TypeDef * SPIx )

Get I2S standard.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_GetStandard
I2SCFGR PCMSYNC LL_I2S_GetStandard
Parameters:
SPIx SPI Handle
Return values:
Return value can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG

Definition at line 2938 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get Transfer Bit Order.

Reference Manual to LL API cross reference:
CFG2 LSBFRST LL_I2S_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_LSB_FIRST
  • LL_I2S_MSB_FIRST

Definition at line 3120 of file stm32h7xx_ll_spi.h.

References LL_SPI_GetTransferBitOrder().

__STATIC_INLINE uint32_t LL_I2S_GetTransferMode ( SPI_TypeDef * SPIx )

Get I2S config.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_GetTransferMode
Parameters:
SPIx SPI Handle
Return values:
Return value can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_SLAVE_FULL_DUPLEX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
  • LL_I2S_MODE_MASTER_FULL_DUPLEX

Definition at line 2973 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer ( SPI_TypeDef * SPIx )

Check if there is an unfinished transfer.

Reference Manual to LL API cross reference:
CR1 CSTART LL_I2S_IsTransferActive
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3142 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveMasterTransfer().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl ( SPI_TypeDef * SPIx )

Check if GPIO control is active.

Reference Manual to LL API cross reference:
CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3069 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledGPIOControl().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock ( SPI_TypeDef * SPIx )

Check if the the SPI_CFG2 register is locked.

Reference Manual to LL API cross reference:
CR1 IOLOCK LL_I2S_IsEnabledIOLock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3093 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIOLock().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap ( SPI_TypeDef * SPIx )

Check if SDO and SDI pin are swapped.

Reference Manual to LL API cross reference:
CFG2 IOSWP LL_I2S_IsEnabledIOSwap
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3034 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIOSwap().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock ( SPI_TypeDef * SPIx )

Check if the master clock output (Pin MCK) is enabled.

Reference Manual to LL API cross reference:
I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3266 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion ( SPI_TypeDef * SPIx )

Check if polarity of WS signal is inverted.

Reference Manual to LL API cross reference:
I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
Parameters:
SPIx SPI Handle
Return values:
State of bit (1 or 0)

Definition at line 2876 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetChannelLengthType | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ChannelLengthType
 | ) |  |

Set I2S Channel Length Type.

Note:
This feature is usefull with SLAVE only
Reference Manual to LL API cross reference:
I2SCFGR FIXCH LL_I2S_SetChannelLengthType
Parameters:
SPIx SPI Handle
ChannelLengthType This parameter can be one of the following values:
  • LL_I2S_SLAVE_VARIABLE_CH_LENGTH
  • LL_I2S_SLAVE_FIXED_CH_LENGTH
Return values:
None

Definition at line 2829 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set 2S Clock Polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_SetClockPolarity
Parameters:
SPIx SPI Handle
ClockPolarity This parameter can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH
Return values:
None

Definition at line 2890 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetDataFormat | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataLength
 | ) |  |

Set I2S Data frame format.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_SetDataFormat
I2SCFGR CHLEN LL_I2S_SetDataFormat
I2SCFGR DATFMT LL_I2S_SetDataFormat
Parameters:
SPIx SPI Handle
DataLength This parameter can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
  • LL_I2S_DATAFORMAT_32B
Return values:
None

Definition at line 2796 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of FIFO that triggers a transfer event.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG1 FTHLV LL_I2S_SetFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_I2S_FIFO_TH_01DATA
  • LL_I2S_FIFO_TH_02DATA
  • LL_I2S_FIFO_TH_03DATA
  • LL_I2S_FIFO_TH_04DATA
  • LL_I2S_FIFO_TH_05DATA
  • LL_I2S_FIFO_TH_06DATA
  • LL_I2S_FIFO_TH_07DATA
  • LL_I2S_FIFO_TH_08DATA
Return values:
None

Definition at line 3163 of file stm32h7xx_ll_spi.h.

References LL_SPI_SetFIFOThreshold().

__STATIC_INLINE void LL_I2S_SetPrescalerLinear | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear
 | ) |  |

Set I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x00 and Max_Data=0xFF
Note:
PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 3195 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerParity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SCFGR ODD LL_I2S_SetPrescalerParity
Parameters:
SPIx SPI Instance
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 3220 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S standard.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_SetStandard
I2SCFGR PCMSYNC LL_I2S_SetStandard
Parameters:
SPIx SPI Handle
Standard This parameter can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG
Return values:
None

Definition at line 2921 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set Transfer Bit Order.

Note:
This configuration can not be changed when I2S is enabled.
Reference Manual to LL API cross reference:
CFG2 LSBFRST LL_I2S_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_I2S_LSB_FIRST
  • LL_I2S_MSB_FIRST
Return values:
None

Definition at line 3108 of file stm32h7xx_ll_spi.h.

References LL_SPI_SetTransferBitOrder().

__STATIC_INLINE void LL_I2S_SetTransferMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S config.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_SetTransferMode
Parameters:
SPIx SPI Handle
Standard This parameter can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_SLAVE_FULL_DUPLEX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
  • LL_I2S_MODE_MASTER_FULL_DUPLEX
Return values:
None

Definition at line 2956 of file stm32h7xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_StartTransfer ( SPI_TypeDef * SPIx )

Start effective transfer on wire.

Reference Manual to LL API cross reference:
CR1 CSTART LL_I2S_StartTransfer
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3131 of file stm32h7xx_ll_spi.h.

References LL_SPI_StartMasterTransfer().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
I2S Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXP (SPI_TypeDef *SPIx)
Check if there enough data in FIFO to read a full packet.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXP (SPI_TypeDef *SPIx)
Check if there enough space in FIFO to hold a full packet.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get Underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get Overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get TI Frame format error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear Underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear Overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear Frame format error flag.

Function Documentation

__STATIC_INLINE void LL_I2S_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear Frame format error flag.

Reference Manual to LL API cross reference:
IFCR TIFREC LL_I2S_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3363 of file stm32h7xx_ll_spi.h.

References LL_SPI_ClearFlag_FRE().

__STATIC_INLINE void LL_I2S_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear Overrun error flag.

Reference Manual to LL API cross reference:
IFCR OVRC LL_I2S_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3352 of file stm32h7xx_ll_spi.h.

References LL_SPI_ClearFlag_OVR().

__STATIC_INLINE void LL_I2S_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear Underrun error flag.

Reference Manual to LL API cross reference:
IFCR UDRC LL_I2S_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3341 of file stm32h7xx_ll_spi.h.

References LL_SPI_ClearFlag_UDR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get TI Frame format error flag.

Reference Manual to LL API cross reference:
SR TIFRE LL_I2S_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 3330 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get Overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 3319 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP ( SPI_TypeDef * SPIx )

Check if there enough data in FIFO to read a full packet.

Reference Manual to LL API cross reference:
SR RXP LL_I2S_IsActiveFlag_RXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3286 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveFlag_RXP().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP ( SPI_TypeDef * SPIx )

Check if there enough space in FIFO to hold a full packet.

Reference Manual to LL API cross reference:
SR TXP LL_I2S_IsActiveFlag_TXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3297 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveFlag_TXP().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get Underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3308 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsActiveFlag_UDR().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableIT_RXP (SPI_TypeDef *SPIx)
Enable Rx Packet available IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXP (SPI_TypeDef *SPIx)
Enable Tx Packet space available IT.
__STATIC_INLINE void | LL_I2S_EnableIT_UDR (SPI_TypeDef *SPIx)
Enable Underrun IT.
__STATIC_INLINE void | LL_I2S_EnableIT_OVR (SPI_TypeDef *SPIx)
Enable Overrun IT.
__STATIC_INLINE void | LL_I2S_EnableIT_FRE (SPI_TypeDef *SPIx)
Enable TI Frame Format Error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXP (SPI_TypeDef *SPIx)
Disable Rx Packet available IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXP (SPI_TypeDef *SPIx)
Disable Tx Packet space available IT.
__STATIC_INLINE void | LL_I2S_DisableIT_UDR (SPI_TypeDef *SPIx)
Disable Underrun IT.
__STATIC_INLINE void | LL_I2S_DisableIT_OVR (SPI_TypeDef *SPIx)
Disable Overrun IT.
__STATIC_INLINE void | LL_I2S_DisableIT_FRE (SPI_TypeDef *SPIx)
Disable TI Frame Format Error IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXP (SPI_TypeDef *SPIx)
Check if Rx Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXP (SPI_TypeDef *SPIx)
Check if Tx Packet space available IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_UDR (SPI_TypeDef *SPIx)
Check if Underrun IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_OVR (SPI_TypeDef *SPIx)
Check if Overrun IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_FRE (SPI_TypeDef *SPIx)
Check if TI Frame Format Error IT is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableIT_FRE ( SPI_TypeDef * SPIx )

Disable TI Frame Format Error IT.

Reference Manual to LL API cross reference:
IER TIFREIE LL_I2S_DisableIT_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3481 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIT_FRE().

__STATIC_INLINE void LL_I2S_DisableIT_OVR ( SPI_TypeDef * SPIx )

Disable Overrun IT.

Reference Manual to LL API cross reference:
IER OVRIE LL_I2S_DisableIT_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3470 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIT_OVR().

__STATIC_INLINE void LL_I2S_DisableIT_RXP ( SPI_TypeDef * SPIx )

Disable Rx Packet available IT.

Reference Manual to LL API cross reference:
IER RXPIE LL_I2S_DisableIT_RXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3437 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIT_RXP().

__STATIC_INLINE void LL_I2S_DisableIT_TXP ( SPI_TypeDef * SPIx )

Disable Tx Packet space available IT.

Reference Manual to LL API cross reference:
IER TXPIE LL_I2S_DisableIT_TXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3448 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIT_TXP().

__STATIC_INLINE void LL_I2S_DisableIT_UDR ( SPI_TypeDef * SPIx )

Disable Underrun IT.

Reference Manual to LL API cross reference:
IER UDRIE LL_I2S_DisableIT_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3459 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableIT_UDR().

__STATIC_INLINE void LL_I2S_EnableIT_FRE ( SPI_TypeDef * SPIx )

Enable TI Frame Format Error IT.

Reference Manual to LL API cross reference:
IER TIFREIE LL_I2S_EnableIT_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3426 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIT_FRE().

__STATIC_INLINE void LL_I2S_EnableIT_OVR ( SPI_TypeDef * SPIx )

Enable Overrun IT.

Reference Manual to LL API cross reference:
IER OVRIE LL_I2S_EnableIT_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3415 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIT_OVR().

__STATIC_INLINE void LL_I2S_EnableIT_RXP ( SPI_TypeDef * SPIx )

Enable Rx Packet available IT.

Reference Manual to LL API cross reference:
IER RXPIE LL_I2S_EnableIT_RXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3382 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIT_RXP().

__STATIC_INLINE void LL_I2S_EnableIT_TXP ( SPI_TypeDef * SPIx )

Enable Tx Packet space available IT.

Reference Manual to LL API cross reference:
IER TXPIE LL_I2S_EnableIT_TXP
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3393 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIT_TXP().

__STATIC_INLINE void LL_I2S_EnableIT_UDR ( SPI_TypeDef * SPIx )

Enable Underrun IT.

Reference Manual to LL API cross reference:
IER UDRIE LL_I2S_EnableIT_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3404 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableIT_UDR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE ( SPI_TypeDef * SPIx )

Check if TI Frame Format Error IT is enabled.

Reference Manual to LL API cross reference:
IER TIFREIE LL_I2S_IsEnabledIT_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3536 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIT_FRE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR ( SPI_TypeDef * SPIx )

Check if Overrun IT is enabled.

Reference Manual to LL API cross reference:
IER OVRIE LL_I2S_IsEnabledIT_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3525 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIT_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP ( SPI_TypeDef * SPIx )

Check if Rx Packet available IT is enabled.

Reference Manual to LL API cross reference:
IER RXPIE LL_I2S_IsEnabledIT_RXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3492 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIT_RXP().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP ( SPI_TypeDef * SPIx )

Check if Tx Packet space available IT is enabled.

Reference Manual to LL API cross reference:
IER TXPIE LL_I2S_IsEnabledIT_TXP
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3503 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIT_TXP().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR ( SPI_TypeDef * SPIx )

Check if Underrun IT is enabled.

Reference Manual to LL API cross reference:
IER UDRIE LL_I2S_IsEnabledIT_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3514 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledIT_UDR().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_Management

Functions
DMA_Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3566 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableDMAReq_RX().

__STATIC_INLINE void LL_I2S_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3599 of file stm32h7xx_ll_spi.h.

References LL_SPI_DisableDMAReq_TX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3555 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableDMAReq_RX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 3588 of file stm32h7xx_ll_spi.h.

References LL_SPI_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3577 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0)

Definition at line 3610 of file stm32h7xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_TX().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DATA_Management

Functions
DATA_Management
I2S Exported Functions

Functions

__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint32_t | LL_I2S_ReceiveData32 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_I2S_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData)
Write Data Register.

Function Documentation

__STATIC_INLINE uint16_t LL_I2S_ReceiveData16 ( SPI_TypeDef * SPIx )

Read Data Register.

Reference Manual to LL API cross reference:
RXDR . LL_I2S_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFF

Definition at line 3629 of file stm32h7xx_ll_spi.h.

References LL_SPI_ReceiveData16().

__STATIC_INLINE uint32_t LL_I2S_ReceiveData32 ( SPI_TypeDef * SPIx )

Read Data Register.

Reference Manual to LL API cross reference:
RXDR . LL_I2S_ReceiveData32
Parameters:
SPIx SPI Instance
Return values:
0..0xFFFFFFFF

Definition at line 3640 of file stm32h7xx_ll_spi.h.

References LL_SPI_ReceiveData32().

__STATIC_INLINE void LL_I2S_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write Data Register.

Reference Manual to LL API cross reference:
TXDR . LL_I2S_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | 0..0xFFFF
Return values:
None

Definition at line 3652 of file stm32h7xx_ll_spi.h.

References LL_SPI_TransmitData16().

__STATIC_INLINE void LL_I2S_TransmitData32 | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TxData
 | ) |  |

Write Data Register.

Reference Manual to LL API cross reference:
TXDR . LL_I2S_TransmitData32
Parameters:
SPIx | SPI Instance
TxData | 0..0xFFFFFFFF
Return values:
None

Definition at line 3664 of file stm32h7xx_ll_spi.h.

References LL_SPI_TransmitData32().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S_LL_EF_Init

Functions
I2S_LL_EF_Init
I2S Exported Functions

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x00 and Max_Data=0xFF
Note:
PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
Parameters:
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 707 of file stm32h7xx_ll_spi.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 542 of file stm32h7xx_ll_spi.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 558 of file stm32h7xx_ll_spi.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CKPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_ENABLE, LL_I2S_STANDARD_PCM_LONG, LL_I2S_STANDARD_PCM_SHORT, LL_RCC_GetSPIClockFreq(), LL_RCC_SPI123_CLKSOURCE, LL_RCC_SPI6_CLKSOURCE, LL_SPI_IsEnabled(), LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 684 of file stm32h7xx_ll_spi.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Private Macros

Defines
SWPMI Private Macros
SWPMI

Defines

#define | IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
#define | IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__)
#define | IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__)
#define | IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__)

Define Documentation

#define IS_LL_SWPMI_BITRATE_VALUE ( __VALUE__ ) (((__VALUE__) <= 255U))

Definition at line 47 of file stm32h7xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_SW_BUFFER_RX ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))

Definition at line 49 of file stm32h7xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_SW_BUFFER_TX ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))

Definition at line 52 of file stm32h7xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_VOLTAGE_CLASS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
                                           || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))

Definition at line 55 of file stm32h7xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

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STM32H7B3xQ HAL User Manual: LL_SWPMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SWPMI_InitTypeDef Struct Reference
SWPMI Exported Init structure

SWPMI Init structures definition. More...

#include <stm32h7xx_ll_swpmi.h>

Data Fields

uint32_t | VoltageClass
uint32_t | BitRatePrescaler
uint32_t | TxBufferingMode
uint32_t | RxBufferingMode

Detailed Description

SWPMI Init structures definition.

Definition at line 62 of file stm32h7xx_ll_swpmi.h.

Field Documentation

uint32_t LL_SWPMI_InitTypeDef::BitRatePrescaler

Specifies the SWPMI bitrate prescaler. This parameter must be a number between Min_Data=0 and Max_Data=255U.

The value can be calculated thanks to helper macro __LL_SWPMI_CALC_BITRATE_PRESCALER

This feature can be modified afterwards using unitary function LL_SWPMI_SetBitRatePrescaler.

Definition at line 69 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::RxBufferingMode

Specifies the reception buffering mode. This parameter can be a value of SW BUFFER RX

This feature can be modified afterwards using unitary function LL_SWPMI_SetReceptionMode.

Definition at line 81 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::TxBufferingMode

Specifies the transmission buffering mode. This parameter can be a value of SW BUFFER TX

This feature can be modified afterwards using unitary function LL_SWPMI_SetTransmissionMode.

Definition at line 76 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::VoltageClass

Specifies the SWP Voltage Class. This parameter can be a value of VOLTAGE CLASS

This feature can be modified afterwards using unitary function LL_SWPMI_SetVoltageClass.

Definition at line 64 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_swpmi.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
SWPMI Exported Constants

Flags defines which can be used with LL_SWPMI_WriteReg function. More...

Defines

#define | LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF
#define | LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF
#define | LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF
#define | LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF
#define | LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF
#define | LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF
#define | LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF

Detailed Description

Flags defines which can be used with LL_SWPMI_WriteReg function.

Define Documentation

#define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF

Clear receive CRC error flag

Definition at line 103 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF

Clear receive buffer full flag

Definition at line 101 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF

Clear receive overrun error flag

Definition at line 104 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF

Clear slave resume flag

Definition at line 107 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF

Clear transfer complete flag

Definition at line 106 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF

Clear transmit buffer empty flag

Definition at line 102 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF

Clear transmit underrun error flag

Definition at line 105 of file stm32h7xx_ll_swpmi.h.

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STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SWPMI Exported Constants

Flags defines which can be used with LL_SWPMI_ReadReg function. More...

Defines

#define | LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF
#define | LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF
#define | LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF
#define | LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF
#define | LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF
#define | LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE
#define | LL_SWPMI_ISR_TXE SWPMI_ISR_TXE
#define | LL_SWPMI_ISR_TCF SWPMI_ISR_TCF
#define | LL_SWPMI_ISR_SRF SWPMI_ISR_SRF
#define | LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP
#define | LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF

Detailed Description

Flags defines which can be used with LL_SWPMI_ReadReg function.

Define Documentation

#define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF

DEACTIVATED flag

Definition at line 126 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF

Receive CRC error flag

Definition at line 118 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF

Receive buffer full flag

Definition at line 116 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE

Receive data register not empty

Definition at line 121 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF

Receive overrun error flag

Definition at line 119 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF

Slave resume flag

Definition at line 124 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP

SUSPEND flag

Definition at line 125 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF

Transfer complete flag

Definition at line 123 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF

Transmit buffer empty flag

Definition at line 117 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE

Transmit data register empty

Definition at line 122 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF

Transmit underrun error flag

Definition at line 120 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
SWPMI Exported Constants

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions. More...

Defines

#define | LL_SWPMI_IER_SRIE SWPMI_IER_SRIE
#define | LL_SWPMI_IER_TCIE SWPMI_IER_TCIE
#define | LL_SWPMI_IER_TIE SWPMI_IER_TIE
#define | LL_SWPMI_IER_RIE SWPMI_IER_RIE
#define | LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE
#define | LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE
#define | LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE
#define | LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE
#define | LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE

Detailed Description

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions.

Define Documentation

#define LL_SWPMI_IER_RIE SWPMI_IER_RIE

Receive interrupt enable

Definition at line 138 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE

Receive CRC error interrupt enable

Definition at line 141 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE

Receive buffer full interrupt enable

Definition at line 143 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE

Receive overrun error interrupt enable

Definition at line 140 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE

Slave resume interrupt enable

Definition at line 135 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE

Transmit complete interrupt enable

Definition at line 136 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_TIE SWPMI_IER_TIE

Transmit interrupt enable

Definition at line 137 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE

Transmit buffer empty interrupt enable

Definition at line 142 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE

Transmit underrun error interrupt enable

Definition at line 139 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SW BUFFER RX

Defines
SW BUFFER RX
SWPMI Exported Constants

Defines

#define | LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE

Define Documentation

#define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE

Multi software buffermode for reception

Definition at line 152 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)

Single software buffer mode for reception

Definition at line 151 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SW BUFFER TX

Defines
SW BUFFER TX
SWPMI Exported Constants

Defines

#define | LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE

Define Documentation

#define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE

Multi software buffermode for transmission

Definition at line 161 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)

Single software buffer mode for transmission

Definition at line 160 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: VOLTAGE CLASS

Defines
VOLTAGE CLASS
SWPMI Exported Constants

Defines

#define | LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Define Documentation

#define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

SWPMI_IO uses an internal voltage regulator to operate in class B

Definition at line 170 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)

SWPMI_IO uses directly VDD voltage to operate in class C

Definition at line 169 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA register data

Defines
DMA register data
SWPMI Exported Constants

Defines

#define | LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0
#define | LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1

Define Documentation

#define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1

Get address of data register used for reception

Definition at line 179 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0

Get address of data register used for transmission

Definition at line 178 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_DMA_GetRegAddr().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SWPMI Exported Macros

Defines

#define | LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SWPMI register.
#define | LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SWPMI register.

Define Documentation

#define LL_SWPMI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SWPMI register.

Parameters:
__INSTANCE__ | SWPMI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 212 of file stm32h7xx_ll_swpmi.h.

#define LL_SWPMI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SWPMI register.

Parameters:
__INSTANCE__ | SWPMI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 204 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Bit rate calculation helper Macros

Defines
Bit rate calculation helper Macros
SWPMI Exported Macros

Defines

#define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Define Documentation

#define __LL_SWPMI_CALC_BITRATE_PRESCALER | ( | __FSWP__,
 |  | __FSWPCLK__
 | ) | ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))

Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Note:
ex: __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
Parameters:
__FSWP__ | Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
__FSWPCLK__ | PCLK or HSI frequency (in Hz)
Return values:
Bitrate prescaler (BRR register)

Definition at line 228 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_SetReceptionMode (SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
Set Reception buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceptionMode (SWPMI_TypeDef *SWPMIx)
Get Reception buffering mode.
__STATIC_INLINE void | LL_SWPMI_SetTransmissionMode (SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
Set Transmission buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetTransmissionMode (SWPMI_TypeDef *SWPMIx)
Get Transmission buffering mode.
__STATIC_INLINE void | LL_SWPMI_EnableLoopback (SWPMI_TypeDef *SWPMIx)
Enable loopback mode.
__STATIC_INLINE void | LL_SWPMI_DisableLoopback (SWPMI_TypeDef *SWPMIx)
Disable loopback mode.
__STATIC_INLINE void | LL_SWPMI_EnableTransceiver (SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver.
__STATIC_INLINE void | LL_SWPMI_DisableTransceiver (SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledTransceiver (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is enabled.
__STATIC_INLINE void | LL_SWPMI_Activate (SWPMI_TypeDef *SWPMIx)
Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActivated (SWPMI_TypeDef *SWPMIx)
Check if Single wire protocol bus is in ACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_Deactivate (SWPMI_TypeDef *SWPMIx)
Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)
__STATIC_INLINE void | LL_SWPMI_RequestDeactivation (SWPMI_TypeDef *SWPMIx)
Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)
__STATIC_INLINE void | LL_SWPMI_SetBitRatePrescaler (SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
__STATIC_INLINE uint32_t | LL_SWPMI_GetBitRatePrescaler (SWPMI_TypeDef *SWPMIx)
Get Bitrate prescaler.
__STATIC_INLINE void | LL_SWPMI_SetVoltageClass (SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
Set SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_GetVoltageClass (SWPMI_TypeDef *SWPMIx)
Get SWP Voltage Class.

Function Documentation

__STATIC_INLINE void LL_SWPMI_Activate ( SWPMI_TypeDef * SWPMIx )

Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)

Note:
SWP bus stays in the ACTIVATED state as long as there is a communication with the slave, either in transmission or in reception. The SWP bus switches back to the SUSPENDED state as soon as there is no more transmission or reception activity, after 7 idle bits.
Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Activate
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 370 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_Deactivate ( SWPMI_TypeDef * SWPMIx )

Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)

Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Deactivate
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 397 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableLoopback ( SWPMI_TypeDef * SWPMIx )

Disable loopback mode.

Reference Manual to LL API cross reference:
CR LPBK LL_SWPMI_DisableLoopback
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 320 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableTransceiver ( SWPMI_TypeDef * SWPMIx )

Disable SWPMI transceiver.

Note:
SWPMI_IO pin is controlled by GPIO controller
Reference Manual to LL API cross reference:
CR SWPEN LL_SWPMI_DisableTransceiver
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 344 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableLoopback ( SWPMI_TypeDef * SWPMIx )

Enable loopback mode.

Reference Manual to LL API cross reference:
CR LPBK LL_SWPMI_EnableLoopback
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 309 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableTransceiver ( SWPMI_TypeDef * SWPMIx )

Enable SWPMI transceiver.

Note:
SWPMI_IO pin is controlled by SWPMI
Reference Manual to LL API cross reference:
CR SWPEN LL_SWPMI_EnableTransceiver
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 332 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler ( SWPMI_TypeDef * SWPMIx )

Get Bitrate prescaler.

Reference Manual to LL API cross reference:
BRR BR LL_SWPMI_GetBitRatePrescaler
Parameters:
SWPMIx SWPMI Instance
Return values:
A number between Min_Data=0 and Max_Data=255U

Definition at line 432 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode ( SWPMI_TypeDef * SWPMIx )

Get Reception buffering mode.

Reference Manual to LL API cross reference:
CR RXMODE LL_SWPMI_GetReceptionMode
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_SW_BUFFER_RX_SINGLE
  • LL_SWPMI_SW_BUFFER_RX_MULTI

Definition at line 270 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode ( SWPMI_TypeDef * SWPMIx )

Get Transmission buffering mode.

Reference Manual to LL API cross reference:
CR TXMODE LL_SWPMI_GetTransmissionMode
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_SW_BUFFER_TX_SINGLE
  • LL_SWPMI_SW_BUFFER_TX_MULTI

Definition at line 298 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass ( SWPMI_TypeDef * SWPMIx )

Get SWP Voltage Class.

Reference Manual to LL API cross reference:
OR CLASS LL_SWPMI_GetVoltageClass
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_VOLTAGE_CLASS_C
  • LL_SWPMI_VOLTAGE_CLASS_B

Definition at line 459 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActivated ( SWPMI_TypeDef * SWPMIx )

Check if Single wire protocol bus is in ACTIVATED state.

Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Activate
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 385 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver ( SWPMI_TypeDef * SWPMIx )

Check if SWPMI transceiver is enabled.

Reference Manual to LL API cross reference:
CR SWPEN LL_SWPMI_IsEnabledTransceiver
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 355 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_RequestDeactivation ( SWPMI_TypeDef * SWPMIx )

Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)

Reference Manual to LL API cross reference:
CR DEACT LL_SWPMI_RequestDeactivation
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 409 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | BitRatePrescaler
 | ) |  |

Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)

Reference Manual to LL API cross reference:
BRR BR LL_SWPMI_SetBitRatePrescaler
Parameters:
SWPMIx | SWPMI Instance
BitRatePrescaler | A number between Min_Data=0 and Max_Data=255U
Return values:
None

Definition at line 421 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

__STATIC_INLINE void LL_SWPMI_SetReceptionMode | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | RxBufferingMode
 | ) |  |

Set Reception buffering mode.

Note:
If Multi software buffer mode is chosen, RXDMA bits must also be set.
Reference Manual to LL API cross reference:
CR RXMODE LL_SWPMI_SetReceptionMode
Parameters:
SWPMIx SWPMI Instance
RxBufferingMode This parameter can be one of the following values:
  • LL_SWPMI_SW_BUFFER_RX_SINGLE
  • LL_SWPMI_SW_BUFFER_RX_MULTI
Return values:
None

Definition at line 257 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetTransmissionMode | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | TxBufferingMode
 | ) |  |

Set Transmission buffering mode.

Note:
If Multi software buffer mode is chosen, TXDMA bits must also be set.
Reference Manual to LL API cross reference:
CR TXMODE LL_SWPMI_SetTransmissionMode
Parameters:
SWPMIx SWPMI Instance
TxBufferingMode This parameter can be one of the following values:
  • LL_SWPMI_SW_BUFFER_TX_SINGLE
  • LL_SWPMI_SW_BUFFER_TX_MULTI
Return values:
None

Definition at line 285 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetVoltageClass | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | VoltageClass
 | ) |  |

Set SWP Voltage Class.

Reference Manual to LL API cross reference:
OR CLASS LL_SWPMI_SetVoltageClass
Parameters:
SWPMIx SWPMI Instance
VoltageClass This parameter can be one of the following values:
  • LL_SWPMI_VOLTAGE_CLASS_C
  • LL_SWPMI_VOLTAGE_CLASS_B
Return values:
None

Definition at line 446 of file stm32h7xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Check if the last word of the frame under reception has arrived in SWPMI_RDR.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Frame transmission buffer has been emptied.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Check if CRC error in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Overrun in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if underrun error in transmission has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXNE (SWPMI_TypeDef *SWPMIx)
Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXE (SWPMI_TypeDef *SWPMIx)
Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TC (SWPMI_TypeDef *SWPMIx)
Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SR (SWPMI_TypeDef *SWPMIx)
Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SUSP (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in SUSPENDED or DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_DEACT (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RDYF (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is ready.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Clear receive buffer full flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Clear transmit buffer empty flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Clear receive CRC error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Clear receive overrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Clear transmit underrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TC (SWPMI_TypeDef *SWPMIx)
Clear transfer complete flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_SR (SWPMI_TypeDef *SWPMIx)
Clear slave resume flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RDY (SWPMI_TypeDef *SWPMIx)
Clear SWPMI transceiver ready flag.

Function Documentation

__STATIC_INLINE void LL_SWPMI_ClearFlag_RDY ( SWPMI_TypeDef * SWPMIx )

Clear SWPMI transceiver ready flag.

Reference Manual to LL API cross reference:
ISR CRDYF LL_SWPMI_ClearFlag_RDY
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 691 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER ( SWPMI_TypeDef * SWPMIx )

Clear receive CRC error flag.

Reference Manual to LL API cross reference:
ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 636 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF ( SWPMI_TypeDef * SWPMIx )

Clear receive buffer full flag.

Reference Manual to LL API cross reference:
ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 614 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR ( SWPMI_TypeDef * SWPMIx )

Clear receive overrun error flag.

Reference Manual to LL API cross reference:
ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 647 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_SR ( SWPMI_TypeDef * SWPMIx )

Clear slave resume flag.

Reference Manual to LL API cross reference:
ICR CSRF LL_SWPMI_ClearFlag_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 680 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TC ( SWPMI_TypeDef * SWPMIx )

Clear transfer complete flag.

Reference Manual to LL API cross reference:
ICR CTCF LL_SWPMI_ClearFlag_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 669 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE ( SWPMI_TypeDef * SWPMIx )

Clear transmit buffer empty flag.

Reference Manual to LL API cross reference:
ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 625 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR ( SWPMI_TypeDef * SWPMIx )

Clear transmit underrun error flag.

Reference Manual to LL API cross reference:
ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 658 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT ( SWPMI_TypeDef * SWPMIx )

Check if SWP bus is in DEACTIVATED state.

Reference Manual to LL API cross reference:
ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 592 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF ( SWPMI_TypeDef * SWPMIx )

Check if SWPMI transceiver is ready.

Reference Manual to LL API cross reference:
ISR RDYF LL_SWPMI_IsActiveFlag_RDYF
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 603 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER ( SWPMI_TypeDef * SWPMIx )

Check if CRC error in reception has been detected.

Reference Manual to LL API cross reference:
ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 500 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF ( SWPMI_TypeDef * SWPMIx )

Check if the last word of the frame under reception has arrived in SWPMI_RDR.

Reference Manual to LL API cross reference:
ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 478 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE ( SWPMI_TypeDef * SWPMIx )

Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)

Reference Manual to LL API cross reference:
ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 534 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR ( SWPMI_TypeDef * SWPMIx )

Check if Overrun in reception has been detected.

Reference Manual to LL API cross reference:
ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 511 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR ( SWPMI_TypeDef * SWPMIx )

Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.

Reference Manual to LL API cross reference:
ISR SRF LL_SWPMI_IsActiveFlag_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 570 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP ( SWPMI_TypeDef * SWPMIx )

Check if SWP bus is in SUSPENDED or DEACTIVATED state.

Reference Manual to LL API cross reference:
ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 581 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC ( SWPMI_TypeDef * SWPMIx )

Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.

Reference Manual to LL API cross reference:
ISR TCF LL_SWPMI_IsActiveFlag_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 558 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE ( SWPMI_TypeDef * SWPMIx )

Check if Frame transmission buffer has been emptied.

Reference Manual to LL API cross reference:
ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 489 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE ( SWPMI_TypeDef * SWPMIx )

Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)

Reference Manual to LL API cross reference:
ISR TXE LL_SWPMI_IsActiveFlag_TXE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 546 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR ( SWPMI_TypeDef * SWPMIx )

Check if underrun error in transmission has been detected.

Reference Manual to LL API cross reference:
ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 522 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_EnableIT_RDY (SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver ready interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_SR (SWPMI_TypeDef *SWPMIx)
Enable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TC (SWPMI_TypeDef *SWPMIx)
Enable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TX (SWPMI_TypeDef *SWPMIx)
Enable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RX (SWPMI_TypeDef *SWPMIx)
Enable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Enable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Enable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Enable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Enable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Enable Receive buffer full interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RDY (SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver ready interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_SR (SWPMI_TypeDef *SWPMIx)
Disable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TC (SWPMI_TypeDef *SWPMIx)
Disable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TX (SWPMI_TypeDef *SWPMIx)
Disable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RX (SWPMI_TypeDef *SWPMIx)
Disable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Disable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Disable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Disable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Disable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Disable Receive buffer full interrupt.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RDY (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver ready interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_SR (SWPMI_TypeDef *SWPMIx)
Check if Slave resume interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TC (SWPMI_TypeDef *SWPMIx)
Check if Transmit complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TX (SWPMI_TypeDef *SWPMIx)
Check if Transmit interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RX (SWPMI_TypeDef *SWPMIx)
Check if Receive interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if Transmit underrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Receive overrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBER (SWPMI_TypeDef *SWPMIx)
Check if Receive CRC error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Transmit buffer empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBF (SWPMI_TypeDef *SWPMIx)
Check if Receive buffer full interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableIT_RDY ( SWPMI_TypeDef * SWPMIx )

Disable SWPMI transceiver ready interrupt.

Reference Manual to LL API cross reference:
IER RDYIE LL_SWPMI_DisableIT_RDY
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 820 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RX ( SWPMI_TypeDef * SWPMIx )

Disable Receive interrupt.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_DisableIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 864 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Disable Receive CRC error interrupt.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_DisableIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 897 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Disable Receive buffer full interrupt.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_DisableIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 919 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Disable Receive overrun error interrupt.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 886 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_SR ( SWPMI_TypeDef * SWPMIx )

Disable Slave resume interrupt.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_DisableIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 831 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TC ( SWPMI_TypeDef * SWPMIx )

Disable Transmit complete interrupt.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_DisableIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 842 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TX ( SWPMI_TypeDef * SWPMIx )

Disable Transmit interrupt.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_DisableIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 853 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Disable Transmit buffer empty interrupt.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_DisableIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 908 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Disable Transmit underrun error interrupt.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 875 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RDY ( SWPMI_TypeDef * SWPMIx )

Enable SWPMI transceiver ready interrupt.

Reference Manual to LL API cross reference:
IER RDYIE LL_SWPMI_EnableIT_RDY
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 710 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RX ( SWPMI_TypeDef * SWPMIx )

Enable Receive interrupt.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_EnableIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 754 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Enable Receive CRC error interrupt.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_EnableIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 787 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Enable Receive buffer full interrupt.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_EnableIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 809 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Enable Receive overrun error interrupt.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 776 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_SR ( SWPMI_TypeDef * SWPMIx )

Enable Slave resume interrupt.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_EnableIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 721 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TC ( SWPMI_TypeDef * SWPMIx )

Enable Transmit complete interrupt.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_EnableIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 732 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TX ( SWPMI_TypeDef * SWPMIx )

Enable Transmit interrupt.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_EnableIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 743 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Enable Transmit buffer empty interrupt.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_EnableIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 798 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Enable Transmit underrun error interrupt.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 765 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY ( SWPMI_TypeDef * SWPMIx )

Check if SWPMI transceiver ready interrupt is enabled.

Reference Manual to LL API cross reference:
IER RDYIE LL_SWPMI_IsEnabledIT_RDY
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 930 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX ( SWPMI_TypeDef * SWPMIx )

Check if Receive interrupt is enabled.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_IsEnabledIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 974 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Check if Receive CRC error interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1007 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Check if Receive buffer full interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1029 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Check if Receive overrun error interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 996 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR ( SWPMI_TypeDef * SWPMIx )

Check if Slave resume interrupt is enabled.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_IsEnabledIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 941 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC ( SWPMI_TypeDef * SWPMIx )

Check if Transmit complete interrupt is enabled.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_IsEnabledIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 952 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX ( SWPMI_TypeDef * SWPMIx )

Check if Transmit interrupt is enabled.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_IsEnabledIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 963 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Check if Transmit buffer empty interrupt is enabled.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1018 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Check if Transmit underrun error interrupt is enabled.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 985 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_Management

Functions
DMA_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for reception.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for reception.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for reception is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for transmission.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for transmission.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for transmission is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_DMA_GetRegAddr (SWPMI_TypeDef *SWPMIx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Disable DMA mode for reception.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_DisableDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1059 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Disable DMA mode for transmission.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_DisableDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1092 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TDR TD LL_SWPMI_DMA_GetRegAddr
RDR RD LL_SWPMI_DMA_GetRegAddr
Parameters:
SWPMIx SWPMI Instance
Direction This parameter can be one of the following values:
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT
  • LL_SWPMI_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 1118 of file stm32h7xx_ll_swpmi.h.

References LL_SWPMI_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Enable DMA mode for reception.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_EnableDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1048 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Enable DMA mode for transmission.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_EnableDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1081 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Check if DMA mode for reception is enabled.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1070 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Check if DMA mode for transmission is enabled.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1103 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SWPMI_GetReceiveFrameLength (SWPMI_TypeDef *SWPMIx)
Retrieve number of data bytes present in payload of received frame.
__STATIC_INLINE void | LL_SWPMI_TransmitData32 (SWPMI_TypeDef *SWPMIx, uint32_t TxData)
Transmit Data Register.
__STATIC_INLINE uint32_t | LL_SWPMI_ReceiveData32 (SWPMI_TypeDef *SWPMIx)
Receive Data Register.
__STATIC_INLINE void | LL_SWPMI_EnableTXBypass (SWPMI_TypeDef *SWPMIx)
Enable SWP Transceiver Bypass.
__STATIC_INLINE void | LL_SWPMI_DisableTXBypass (SWPMI_TypeDef *SWPMIx)
Disable SWP Transceiver Bypass.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableTXBypass ( SWPMI_TypeDef * SWPMIx )

Disable SWP Transceiver Bypass.

Note:
SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate function on GPIOs. This configuration is selected to connect an external transceiver
In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared
Reference Manual to LL API cross reference:
OR TBYP LL_SWPMI_DisableTXBypass
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1200 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableTXBypass ( SWPMI_TypeDef * SWPMIx )

Enable SWP Transceiver Bypass.

Note:
The external interface for SWPMI is SWPMI_IO (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
Reference Manual to LL API cross reference:
OR TBYP LL_SWPMI_EnableTXBypass
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1186 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength ( SWPMI_TypeDef * SWPMIx )

Retrieve number of data bytes present in payload of received frame.

Reference Manual to LL API cross reference:
RFL RFL LL_SWPMI_GetReceiveFrameLength
Parameters:
SWPMIx SWPMI Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 1150 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32 ( SWPMI_TypeDef * SWPMIx )

Receive Data Register.

Reference Manual to LL API cross reference:
RDR RD LL_SWPMI_ReceiveData32
Parameters:
SWPMIx SWPMI Instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 1173 of file stm32h7xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_TransmitData32 | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | TxData
 | ) |  |

Transmit Data Register.

Reference Manual to LL API cross reference:
TDR TD LL_SWPMI_TransmitData32
Parameters:
SWPMIx | SWPMI Instance
TxData | Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 1162 of file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SWPMI Exported Functions

Functions

ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SWPMI_DeInit ( SWPMI_TypeDef * SWPMIx )

De-initialize the SWPMI peripheral registers to their default reset values.

Parameters:
SWPMIx SWPMI Instance
Return values:
An ErrorStatus enumeration value
  • SUCCESS: SWPMI registers are de-initialized
  • ERROR: Not applicable

Definition at line 80 of file stm32h7xx_ll_swpmi.c.

References assert_param, LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_SWPMI1, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_SWPMI_Init | ( | SWPMI_TypeDef * | SWPMIx,
 |  | LL_SWPMI_InitTypeDef * | SWPMI_InitStruct
 | ) |  |

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.

Note:
As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0), SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SWPMIx | SWPMI Instance
SWPMI_InitStruct | pointer to a LL_SWPMI_InitTypeDef structure that contains the configuration information for the SWPMI peripheral.
Return values:
An ErrorStatus enumeration value
  • SUCCESS: SWPMI registers are initialized
  • ERROR: SWPMI registers are not initialized

Definition at line 111 of file stm32h7xx_ll_swpmi.c.

References assert_param, LL_SWPMI_InitTypeDef::BitRatePrescaler, IS_LL_SWPMI_BITRATE_VALUE, IS_LL_SWPMI_SW_BUFFER_RX, IS_LL_SWPMI_SW_BUFFER_TX, IS_LL_SWPMI_VOLTAGE_CLASS, LL_SWPMI_IsActivated(), LL_SWPMI_SetBitRatePrescaler(), LL_SWPMI_SetVoltageClass(), LL_SWPMI_InitTypeDef::RxBufferingMode, LL_SWPMI_InitTypeDef::TxBufferingMode, and LL_SWPMI_InitTypeDef::VoltageClass.

void LL_SWPMI_StructInit ( LL_SWPMI_InitTypeDef * SWPMI_InitStruct )

Set each LL_SWPMI_InitTypeDef field to default value.

Parameters:
SWPMI_InitStruct pointer to a LL_SWPMI_InitTypeDef structure that contains the configuration information for the SWPMI peripheral.
Return values:
None

Definition at line 151 of file stm32h7xx_ll_swpmi.c.

References LL_SWPMI_InitTypeDef::BitRatePrescaler, LL_SWPMI_SW_BUFFER_RX_SINGLE, LL_SWPMI_SW_BUFFER_TX_SINGLE, LL_SWPMI_VOLTAGE_CLASS_C, LL_SWPMI_InitTypeDef::RxBufferingMode, LL_SWPMI_InitTypeDef::TxBufferingMode, and LL_SWPMI_InitTypeDef::VoltageClass.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG Flash Bank1 sectors bits status

Defines
SYSCFG Flash Bank1 sectors bits status
SYSTEM Private Constants

Defines

#define | LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
#define | LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
#define | LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
#define | LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
#define | LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
#define | LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
#define | LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
#define | LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U

Define Documentation

#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U

Definition at line 63 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U

Definition at line 64 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U

Definition at line 65 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U

Definition at line 66 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U

Definition at line 67 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U

Definition at line 68 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U

Definition at line 69 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U

Definition at line 70 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG Flash Bank2 sectors bits status

Defines
SYSCFG Flash Bank2 sectors bits status
SYSTEM Private Constants

Defines

#define | LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
#define | LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
#define | LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
#define | LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
#define | LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
#define | LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
#define | LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
#define | LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U

Define Documentation

#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U

Definition at line 78 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U

Definition at line 79 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U

Definition at line 80 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U

Definition at line 81 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U

Definition at line 82 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U

Definition at line 83 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U

Definition at line 84 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U

Definition at line 85 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP

Enable Fast Mode Plus for I2C1

Definition at line 104 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP

Enable Fast Mode Plus for I2C2

Definition at line 105 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP

Enable Fast Mode Plus for I2C3

Definition at line 106 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP

Enable Fast Mode Plus for I2C4

Definition at line 107 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 108 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 109 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 110 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 111 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Analog Switch control

Defines
Analog Switch control
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN
#define | LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO

Define Documentation

#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN

I/O analog switch voltage booster enable

Definition at line 119 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO

PA0 Switch Open

Definition at line 120 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO

PA1 Switch Open

Definition at line 121 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO

PC2 Switch Open

Definition at line 122 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO

PC3 Switch Open

Definition at line 123 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG EXTI PORT

Defines
SYSCFG EXTI PORT
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTF 5U
#define | LL_SYSCFG_EXTI_PORTG 6U
#define | LL_SYSCFG_EXTI_PORTH 7U
#define | LL_SYSCFG_EXTI_PORTI 8U
#define | LL_SYSCFG_EXTI_PORTJ 9U
#define | LL_SYSCFG_EXTI_PORTK 10U

Define Documentation

#define LL_SYSCFG_EXTI_PORTA 0U

EXTI PORT A

Definition at line 142 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTB 1U

EXTI PORT B

Definition at line 143 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTC 2U

EXTI PORT C

Definition at line 144 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTD 3U

EXTI PORT D

Definition at line 145 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTE 4U

EXTI PORT E

Definition at line 146 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTF 5U

EXTI PORT F

Definition at line 147 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTG 6U

EXTI PORT G

Definition at line 148 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTH 7U

EXTI PORT H

Definition at line 149 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTI 8U

EXTI PORT I

Definition at line 150 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTJ 9U

EXTI PORT J

Definition at line 151 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTK 10U

EXTI PORT k

Definition at line 152 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG EXTI LINE

Defines
SYSCFG EXTI LINE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U)

Define Documentation

#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U)

EXTI_POSITION_0 | EXTICR[0]

Definition at line 160 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U)

EXTI_POSITION_4 | EXTICR[0]

Definition at line 161 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U)

EXTI_POSITION_8 | EXTICR[2]

Definition at line 170 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U)

EXTI_POSITION_12 | EXTICR[2]

Definition at line 171 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U)

EXTI_POSITION_0 | EXTICR[3]

Definition at line 172 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U)

EXTI_POSITION_4 | EXTICR[3]

Definition at line 173 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U)

EXTI_POSITION_8 | EXTICR[3]

Definition at line 174 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U)

EXTI_POSITION_12 | EXTICR[3]

Definition at line 175 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U)

EXTI_POSITION_8 | EXTICR[0]

Definition at line 162 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U)

EXTI_POSITION_12 | EXTICR[0]

Definition at line 163 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U)

EXTI_POSITION_0 | EXTICR[1]

Definition at line 164 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U)

EXTI_POSITION_4 | EXTICR[1]

Definition at line 165 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U)

EXTI_POSITION_8 | EXTICR[1]

Definition at line 166 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U)

EXTI_POSITION_12 | EXTICR[1]

Definition at line 167 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U)

EXTI_POSITION_0 | EXTICR[2]

Definition at line 168 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U)

EXTI_POSITION_4 | EXTICR[2]

Definition at line 169 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML
#define | LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML
#define | LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML
#define | LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L
#define | LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L
#define | LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L
#define | LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L
#define | LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML
#define | LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L
#define | LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL

Define Documentation

#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML

Enables and locks the AXIRAM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 183 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML

Enables and locks the BKRAM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 204 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L

Enables and locks the Cortex-M7 LOCKUP signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 207 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML

Enables and locks the DTCM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 189 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL

Enables and locks the FLASH double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 210 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML

Enables and locks the ITCM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 186 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 and HRTIM Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 213 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L

Enables and locks the SRAM1 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 192 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L

Enables and locks the SRAM2 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 195 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L

Enables and locks the SRAM3 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 198 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L

Enables and locks the SRAM4 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 201 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG I/O compensation cell Code selection

Defines
SYSCFG I/O compensation cell Code selection
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_CELL_CODE 0U
#define | LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS

Define Documentation

#define LL_SYSCFG_CELL_CODE 0U

Definition at line 227 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS

Definition at line 228 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG IWDG1 control modes

Defines
SYSCFG IWDG1 control modes
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
#define | LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M

Define Documentation

#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M

Definition at line 237 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U

Definition at line 236 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG DTCM RAM size configuration

Defines
SYSCFG DTCM RAM size configuration
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
#define | LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
#define | LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
#define | LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U

Define Documentation

#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U

Definition at line 259 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U

Definition at line 256 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U

Definition at line 257 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U

Definition at line 258 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG Brownout Reset Threshold Level

Defines
SYSCFG Brownout Reset Threshold Level
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
#define | LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
#define | LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
#define | LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH

Define Documentation

#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH

Definition at line 282 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0

Definition at line 280 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1

Definition at line 281 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U

Definition at line 279 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU TRACE Pin Assignment

Defines
DBGMCU TRACE Pin Assignment
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

Define Documentation

#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN

TRACE pin assignment for Asynchronous Mode

Definition at line 292 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_TRACE_NONE 0x00000000U

TRACE pins not assigned (default state)

Definition at line 291 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1

Definition at line 293 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2

Definition at line 294 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4

Definition at line 295 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7
#define | LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12
#define | LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13
#define | LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3

Define Documentation

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1

I2C1 SMBUS timeout mode stopped when Core is halted

Definition at line 313 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2

I2C2 SMBUS timeout mode stopped when Core is halted

Definition at line 314 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3

I2C3 SMBUS timeout mode stopped when Core is halted

Definition at line 315 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1

LPTIM1 counter stopped when core is halted

Definition at line 312 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12

TIM12 counter stopped when core is halted

Definition at line 309 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13

TIM13 counter stopped when core is halted

Definition at line 310 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14

TIM14 counter stopped when core is halted

Definition at line 311 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2

TIM2 counter stopped when core is halted

Definition at line 303 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3

TIM3 counter stopped when core is halted

Definition at line 304 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4

TIM4 counter stopped when core is halted

Definition at line 305 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5

TIM5 counter stopped when core is halted

Definition at line 306 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6

TIM6 counter stopped when core is halted

Definition at line 307 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7

TIM7 counter stopped when core is halted

Definition at line 308 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU APB1 GRP2 STOP IP

Defines
DBGMCU APB1 GRP2 STOP IP
SYSTEM Exported Constants

Defines

#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN

Define Documentation

#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN

FDCAN is frozen while the core is in debug mode

Definition at line 323 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17
#define | LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM

Define Documentation

#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM

HRTIM counter stopped when core is halted

Definition at line 336 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15

TIM15 counter stopped when core is halted

Definition at line 333 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16

TIM16 counter stopped when core is halted

Definition at line 334 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17

TIM17 counter stopped when core is halted

Definition at line 335 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1

TIM1 counter stopped when core is halted

Definition at line 331 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8

TIM8 counter stopped when core is halted

Definition at line 332 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU APB3 GRP1 STOP IP

Defines
DBGMCU APB3 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1

Define Documentation

#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1

WWDG1 is frozen while the core is in debug mode

Definition at line 344 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU APB4 GRP1 STOP IP

Defines
DBGMCU APB4 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4
#define | LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2
#define | LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3
#define | LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4
#define | LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5
#define | LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC
#define | LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1

Define Documentation

#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4

I2C4 is frozen while the core is in debug mode

Definition at line 352 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1

IWDG1 is frozen while the core is in debug mode

Definition at line 358 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2

LPTIM2 is frozen while the core is in debug mode

Definition at line 353 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3

LPTIM3 is frozen while the core is in debug mode

Definition at line 354 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4

LPTIM4 is frozen while the core is in debug mode

Definition at line 355 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5

LPTIM5 is frozen while the core is in debug mode

Definition at line 356 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC

RTC is frozen while the core is in debug mode

Definition at line 357 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

Define Documentation

#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 366 of file stm32h7xx_ll_system.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 367 of file stm32h7xx_ll_system.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 368 of file stm32h7xx_ll_system.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 369 of file stm32h7xx_ll_system.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four wait states

Definition at line 370 of file stm32h7xx_ll_system.h.

Referenced by UTILS_CalculateFlashLatency().

#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH five wait state

Definition at line 371 of file stm32h7xx_ll_system.h.

#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH six wait state

Definition at line 372 of file stm32h7xx_ll_system.h.

#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH seven wait states

Definition at line 373 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSCFG

Functions
SYSCFG
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_SYSCFG_OpenAnalogSwitch (uint32_t AnalogSwitch)
Open an Analog Switch.
__STATIC_INLINE void | LL_SYSCFG_CloseAnalogSwitch (uint32_t AnalogSwitch)
Close an Analog Switch.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 and HRTIM Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 and HRTIM Break inputs.
__STATIC_INLINE void | LL_SYSCFG_EnableCompensationCell (void)
Enable the Compensation Cell.
__STATIC_INLINE void | LL_SYSCFG_DisableCompensationCell (void)
Disable the Compensation Cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledCompensationCell (void)
Check if the Compensation Cell is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CMPCR (void)
Get Compensation Cell ready Flag.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization1 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization2 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization3 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization1 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization2 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization3 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization1 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization2 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization3 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE void | LL_SYSCFG_SetCellCompensationCode (uint32_t CompCode)
Set the code selection for the I/O Compensation cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetCellCompensationCode (void)
Get the code selected for the I/O Compensation cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_MMCGetCellCompensationCode (void)
Get the code selected for the I/O Compensation cell on the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationValue (void)
Get I/O compensation cell value for PMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationValue (void)
Get I/O compensation cell value for NMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_SetPMOSCompensationCode (uint32_t PMOSCode)
Set I/O compensation cell code for PMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationCode (void)
Get I/O compensation cell code for PMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_MMCSetPMOSCompensationCode (uint32_t PMOSCode)
Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_MMCGetPMOSCompensationCode (void)
Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.
__STATIC_INLINE void | LL_SYSCFG_SetNMOSCompensationCode (uint32_t NMOSCode)
Set I/O compensation cell code for NMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationCode (void)
Get I/O compensation cell code for NMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_VDMMCSetNMOSCompensationCode (uint32_t NMOSCode)
Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_VDMMCGetNMOSCompensationCode (void)
Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.

Function Documentation

__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch ( uint32_t AnalogSwitch )

Close an Analog Switch.

Reference Manual to LL API cross reference:
PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
Parameters:
AnalogSwitch This parameter can be one of the following values:
  • LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
Return values:
None

Definition at line 451 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell ( void )

Disable the Compensation Cell.

Reference Manual to LL API cross reference:
CCCSR EN LL_SYSCFG_DisableCompensationCell
Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V
Return values:
None

Definition at line 725 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) value not defined in all devices
Return values:
None

Definition at line 521 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization ( void )

To Disable optimize the I/O speed when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 817 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1 ( void )

To Disable optimize the I/O speed when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 835 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2 ( void )

To Disable optimize the I/O speed when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 848 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3 ( void )

To Disable optimize the I/O speed when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 861 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell ( void )

Enable the Compensation Cell.

Reference Manual to LL API cross reference:
CCCSR EN LL_SYSCFG_EnableCompensationCell
Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V
Return values:
None

Definition at line 713 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
(*) value not defined in all devices
Return values:
None

Definition at line 500 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization ( void )

Enable the I/O speed optimization when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 758 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1 ( void )

Enable the I/O speed optimization when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 776 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2 ( void )

Enable the I/O speed optimization when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 789 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3 ( void )

Enable the I/O speed optimization when the product voltage is low.

Reference Manual to LL API cross reference:
CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize
Note:
This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive.
Return values:
None

Definition at line 802 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode ( void )

Get the code selected for the I/O Compensation cell.

Reference Manual to LL API cross reference:
CCCSR CS LL_SYSCFG_GetCellCompensationCode
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
  • LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)

Definition at line 934 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG
  • LL_SYSCFG_EXTI_PORTH
  • LL_SYSCFG_EXTI_PORTI
  • LL_SYSCFG_EXTI_PORTJ
  • LL_SYSCFG_EXTI_PORTK (*) value not defined in all devices

Definition at line 607 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode ( void )

Get I/O compensation cell code for NMOS transistors.

Reference Manual to LL API cross reference:
CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
Return values:
Returned value is the I/O compensation cell code for NMOS transistors

Definition at line 1041 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue ( void )

Get I/O compensation cell value for NMOS transistors.

Reference Manual to LL API cross reference:
CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
Return values:
Returned value is the I/O compensation cell value for NMOS transistors

Definition at line 969 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode ( void )

Get I/O compensation cell code for PMOS transistors.

Reference Manual to LL API cross reference:
CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
Return values:
Returned value is the I/O compensation cell code for PMOS transistors

Definition at line 992 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue ( void )

Get I/O compensation cell value for PMOS transistors.

Reference Manual to LL API cross reference:
CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
Return values:
Returned value is the I/O compensation cell value for PMOS transistors

Definition at line 959 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIM1/8/15/16/17 and HRTIM Break inputs.

Note:
this feature is available on STM32H7 rev.B and above
Reference Manual to LL API cross reference:
SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
  • LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_CM7_LOCKUP
  • LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)

Definition at line 688 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR ( void )

Get Compensation Cell ready Flag.

Reference Manual to LL API cross reference:
CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
Return values:
State of bit (1 or 0).

Definition at line 745 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell ( void )

Check if the Compensation Cell is enabled.

Reference Manual to LL API cross reference:
CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
Return values:
State of bit (1 or 0).

Definition at line 735 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization ( void )

Check if the I/O speed optimization is enabled.

Reference Manual to LL API cross reference:
CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
Return values:
State of bit (1 or 0).

Definition at line 872 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1 ( void )

Check if the I/O speed optimization is enabled.

Reference Manual to LL API cross reference:
CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization
Return values:
State of bit (1 or 0).

Definition at line 887 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2 ( void )

Check if the I/O speed optimization is enabled.

Reference Manual to LL API cross reference:
CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization
Return values:
State of bit (1 or 0).

Definition at line 897 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3 ( void )

Check if the I/O speed optimization is enabled.

Reference Manual to LL API cross reference:
CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization
Return values:
State of bit (1 or 0).

Definition at line 907 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode ( void )

Get the code selected for the I/O Compensation cell on the VDDMMC power rail.

Reference Manual to LL API cross reference:
CCCSR CS LL_SYSCFG_GetCellCompensationCode
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
  • LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)

Definition at line 948 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode ( void )

Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.

Reference Manual to LL API cross reference:
CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
Return values:
Returned value is the I/O compensation cell code for PMOS transistors

Definition at line 1017 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode ( uint32_t PMOSCode )

Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.

Reference Manual to LL API cross reference:
CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
Parameters:
PMOSCode PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 1007 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch ( uint32_t AnalogSwitch )

Open an Analog Switch.

Reference Manual to LL API cross reference:
PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
Reference Manual to LL API cross reference:
PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
Parameters:
AnalogSwitch This parameter can be one of the following values:
  • LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
  • LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
Return values:
None

Definition at line 433 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode ( uint32_t CompCode )

Set the code selection for the I/O Compensation cell.

Reference Manual to LL API cross reference:
CCCSR CS LL_SYSCFG_SetCellCompensationCode
Parameters:
CompCode,: Selects the code to be applied for the I/O compensation cell This parameter can be one of the following values:
  • LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
  • LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
Return values:
None

Definition at line 922 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG
  • LL_SYSCFG_EXTI_PORTH
  • LL_SYSCFG_EXTI_PORTI
  • LL_SYSCFG_EXTI_PORTJ
  • LL_SYSCFG_EXTI_PORTK
(*) value not defined in all devices
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
None

Definition at line 565 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode ( uint32_t NMOSCode )

Set I/O compensation cell code for NMOS transistors.

Reference Manual to LL API cross reference:
CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
Parameters:
NMOSCode NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 1031 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode ( uint32_t PMOSCode )

Set I/O compensation cell code for PMOS transistors.

Reference Manual to LL API cross reference:
CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
Parameters:
PMOSCode PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 982 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIM1/8/15/16/17 and HRTIM Break inputs.

Note:
this feature is available on STM32H7 rev.B and above
Reference Manual to LL API cross reference:
SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
  • LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
  • LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
  • LL_SYSCFG_TIMBREAK_CM7_LOCKUP
  • LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
Return values:
None

Definition at line 642 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode ( void )

Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.

Reference Manual to LL API cross reference:
CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
Return values:
Returned value is the I/O compensation cell code for NMOS transistors

Definition at line 1066 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode ( uint32_t NMOSCode )

Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.

Reference Manual to LL API cross reference:
CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
Parameters:
NMOSCode,: NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 1056 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DBGMCU

Defines | Functions
DBGMCU
SYSTEM Exported Functions

Defines

#define | LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
#define | LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInSleepMode (void)
Enable D1 Domain/CDomain debug during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInSleepMode (void)
Disable D1 Domain/CDomain debug during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStopMode (void)
Enable D1 Domain/CDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStopMode (void)
Disable D1 Domain/CDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStandbyMode (void)
Enable D1 Domain/CDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStandbyMode (void)
Disable D1 Domain/CDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStopMode (void)
Enable D3 Domain/SRDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStopMode (void)
Disable D3 Domain/SRDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStandbyMode (void)
Enable D3 Domain/SRDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStandbyMode (void)
Disable D3 Domain/SRDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableTracePortClock (void)
Enable the trace port clock.
__STATIC_INLINE void | LL_DBGMCU_DisableTracePortClock (void)
Disable the trace port clock.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugClock (void)
Enable the Domain1/CDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugClock (void)
Disable the Domain1/CDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugClock (void)
Enable the Domain3/SRDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugClock (void)
Disable the Domain3/SRDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_SetExternalTriggerPinDirection (uint32_t PinDirection)
Set the direction of the bi-directional trigger pin TRGIO.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetExternalTriggerPinDirection (void)
Get the direction of the bi-directional trigger pin TRGIO.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 group1 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 group2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 group2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB3 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB3 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB4 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB4 peripherals.

Define Documentation

#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U

Definition at line 1904 of file stm32h7xx_ll_system.h.

#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN

Definition at line 1905 of file stm32h7xx_ll_system.h.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 group1 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
Return values:
None

Definition at line 1962 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
Return values:
None

Definition at line 1998 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph ( uint32_t Periphs )

Freeze APB1 group2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_FDCAN_STOP
Return values:
None

Definition at line 2010 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 group2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_FDCAN_STOP
Return values:
None

Definition at line 2022 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_HRTIM_STOP
Return values:
None

Definition at line 2044 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_HRTIM_STOP
Return values:
None

Definition at line 2066 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB3 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB3_GRP1_WWDG1_STOP
Return values:
None

Definition at line 2078 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB3 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB3_GRP1_WWDG1_STOP
Return values:
None

Definition at line 2090 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB4 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB4_GRP1_I2C4_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
  • LL_DBGMCU_APB4_GRP1_RTC_STOP
  • LL_DBGMCU_APB4_GRP1_IWDG1_STOP
Return values:
None

Definition at line 2114 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB4 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph
Reference Manual to LL API cross reference:
DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB4_GRP1_I2C4_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
  • LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
  • LL_DBGMCU_APB4_GRP1_RTC_STOP
  • LL_DBGMCU_APB4_GRP1_IWDG1_STOP
Return values:
None

Definition at line 2138 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock ( void )

Disable the Domain1/CDomain debug clock enable.

Reference Manual to LL API cross reference:
DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock
Return values:
None

Definition at line 1879 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode ( void )

Disable D1 Domain/CDomain debug during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode
Return values:
None

Definition at line 1696 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode ( void )

Disable D1 Domain/CDomain debug during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode
Return values:
None

Definition at line 1736 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode ( void )

Disable D1 Domain/CDomain debug during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode
Return values:
None

Definition at line 1716 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock ( void )

Disable the Domain3/SRDomain debug clock enable.

Reference Manual to LL API cross reference:
DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock
Return values:
None

Definition at line 1899 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode ( void )

Disable D3 Domain/SRDomain debug during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode
Return values:
None

Definition at line 1839 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode ( void )

Disable D3 Domain/SRDomain debug during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode
Return values:
None

Definition at line 1819 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock ( void )

Disable the trace port clock.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
Return values:
None

Definition at line 1859 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock ( void )

Enable the Domain1/CDomain debug clock enable.

Reference Manual to LL API cross reference:
DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock
Return values:
None

Definition at line 1869 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode ( void )

Enable D1 Domain/CDomain debug during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode
Return values:
None

Definition at line 1686 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode ( void )

Enable D1 Domain/CDomain debug during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode
Return values:
None

Definition at line 1726 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode ( void )

Enable D1 Domain/CDomain debug during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode
Return values:
None

Definition at line 1706 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock ( void )

Enable the Domain3/SRDomain debug clock enable.

Reference Manual to LL API cross reference:
DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock
Return values:
None

Definition at line 1889 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode ( void )

Enable D3 Domain/SRDomain debug during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
Return values:
None

Definition at line 1829 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode ( void )

Enable D3 Domain/SRDomain debug during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
Return values:
None

Definition at line 1809 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock ( void )

Enable the trace port clock.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
Return values:
None

Definition at line 1849 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFF

Definition at line 1664 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection ( void )

Get the direction of the bi-directional trigger pin TRGIO.

Reference Manual to LL API cross reference:
DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection
Return values:
Returned value can be one of the following values:
  • LL_DBGMCU_TRGIO_INPUT_DIRECTION
  • LL_DBGMCU_TRGIO_OUTPUT_DIRECTION

Definition at line 1926 of file stm32h7xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device. For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1676 of file stm32h7xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection ( uint32_t PinDirection )

Set the direction of the bi-directional trigger pin TRGIO.

Reference Manual to LL API cross reference:
DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection
Parameters:
PinDirection This parameter can be one of the following values:
  • LL_DBGMCU_TRGIO_INPUT_DIRECTION
  • LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
Return values:
None

Definition at line 1914 of file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.

Function Documentation

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
  • LL_FLASH_LATENCY_5
  • LL_FLASH_LATENCY_6
  • LL_FLASH_LATENCY_7

Definition at line 2182 of file stm32h7xx_ll_system.h.

Referenced by UTILS_EnablePLLAndSwitchSystem(), and UTILS_SetFlashLatency().

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
  • LL_FLASH_LATENCY_5
  • LL_FLASH_LATENCY_6
  • LL_FLASH_LATENCY_7
Return values:
None

Definition at line 2164 of file stm32h7xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1239 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1272 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1305 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1338 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 811 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 890 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 969 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1048 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC5Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 5.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 5 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1118 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH5(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC6Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 6.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 6 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1179 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH6(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U,
  0x3CU,
  0x3CU
}

Definition at line 46 of file stm32h7xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  16U,
  20U
}

Definition at line 85 of file stm32h7xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U
}

Definition at line 72 of file stm32h7xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  8U
}

Definition at line 59 of file stm32h7xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  8U,
  10U
}

Definition at line 98 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINE TIM1_AF1_BKINE
#define | TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E
#define | TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E
#define | TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P
#define | TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | TIMx_AF2_BK2INE TIM1_AF2_BK2INE
#define | TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E
#define | TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E
#define | TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E
#define | TIMx_AF2_BK2INP TIM1_AF2_BK2INP
#define | TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P
#define | TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7F)

Definition at line 145 of file stm32h7xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3F)

Definition at line 146 of file stm32h7xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1F)

Definition at line 147 of file stm32h7xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1F)

Definition at line 148 of file stm32h7xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00)

Definition at line 151 of file stm32h7xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80)

Definition at line 152 of file stm32h7xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0)

Definition at line 153 of file stm32h7xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0)

Definition at line 154 of file stm32h7xx_ll_tim.h.

#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)

Definition at line 121 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E

BRK COMP1 enable

Definition at line 125 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P

BRK COMP1 input polarity

Definition at line 129 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E

BRK COMP2 enable

Definition at line 126 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P

BRK COMP2 input polarity

Definition at line 130 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E

BRK DFSDM1_BREAK[0] enable

Definition at line 127 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKINE TIM1_AF1_BKINE

BRK BKIN input enable

Definition at line 124 of file stm32h7xx_ll_tim.h.

#define TIMx_AF1_BKINP TIM1_AF1_BKINP

BRK BKIN input polarity

Definition at line 128 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

TIMx ETR source selection

Definition at line 131 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E

BRK2 COMP1 enable

Definition at line 135 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P

BRK2 COMP1 input polarity

Definition at line 139 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E

BRK2 COMP2 enable

Definition at line 136 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P

BRK2 COMP2 input polarity

Definition at line 140 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E

BRK2 DFSDM1_BREAK[1] enable

Definition at line 137 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE

BRK2 BKIN2 input enable

Definition at line 134 of file stm32h7xx_ll_tim.h.

#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP

BRK2 BKIN2 input polarity

Definition at line 138 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 82 of file stm32h7xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 176 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))

Definition at line 159 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))

Definition at line 156 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))

Definition at line 153 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))

Definition at line 136 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 133 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 130 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 54 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 48 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 112 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 91 of file stm32h7xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 108 of file stm32h7xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 116 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 86 of file stm32h7xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 125 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 79 of file stm32h7xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 58 of file stm32h7xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 76 of file stm32h7xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 73 of file stm32h7xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 122 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 119 of file stm32h7xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 196 of file stm32h7xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
none

Definition at line 178 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint8_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 214 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 226 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 233 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 221 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 216 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint8_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 238 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 252 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 269 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 285 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 254 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 290 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 279 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 264 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 274 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 259 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 300 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 308 of file stm32h7xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 318 of file stm32h7xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 303 of file stm32h7xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 313 of file stm32h7xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 328 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 330 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 340 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 350 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 335 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 345 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 360 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 370 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 355 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 365 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 380 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 400 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 395 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 383 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 388 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32h7xx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 411 of file stm32h7xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 483 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Filter

Specifies the TIM Break2 Filter. This parameter can be a value of BREAK2 FILTER

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 476 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Polarity

Specifies the TIM Break2 Input pin polarity. This parameter can be a value of BREAK2 POLARITY

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 469 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2State

Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of Break2 Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK2() or LL_TIM_DisableBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 462 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakFilter

Specifies the TIM Break Filter. This parameter can be a value of break filter

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 455 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 448 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 441 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 433 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 427 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 420 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 413 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_tim.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 515 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 514 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 506 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 516 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 507 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 517 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 508 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 518 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 509 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 519 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC5IF TIM_SR_CC5IF

Capture/compare 5 interrupt flag

Definition at line 510 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_CC6IF TIM_SR_CC6IF

Capture/compare 6 interrupt flag

Definition at line 511 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 512 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_SBIF TIM_SR_SBIF

System Break interrupt flag

Definition at line 520 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 513 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 505 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 529 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 530 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Break2 Enable

Defines
Break2 Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define LL_TIM_BREAK2_DISABLE 0x00000000U

Break2 function disabled

Definition at line 538 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break2 function enabled

Definition at line 539 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 547 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 548 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 565 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 559 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 560 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 561 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 562 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 563 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 564 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 558 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 574 of file stm32h7xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 573 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter stops counting at the next update event

Definition at line 583 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter is not stopped at update event

Definition at line 582 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 594 of file stm32h7xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 593 of file stm32h7xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 595 of file stm32h7xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 592 of file stm32h7xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 591 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

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STM32H7B3xQ HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 603 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 604 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 605 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 614 of file stm32h7xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 613 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 623 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 622 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 631 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 632 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 641 of file stm32h7xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 642 of file stm32h7xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 643 of file stm32h7xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 640 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 651 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 652 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 653 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 654 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 655 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 656 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 657 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

Definition at line 658 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

Definition at line 659 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

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STM32H7B3xQ HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 668 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 669 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 679 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 690 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Asymmetric PWM mode 2

Definition at line 691 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 688 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 689 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 683 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 682 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 678 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 680 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 684 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 685 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 686 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 687 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 681 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 699 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 700 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 709 of file stm32h7xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 708 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GROUPCH5

Defines
GROUPCH5
TIM Exported Constants

Defines

#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define LL_TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 717 of file stm32h7xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 718 of file stm32h7xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 719 of file stm32h7xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 720 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 728 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 729 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 730 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

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STM32H7B3xQ HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 738 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 739 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 740 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 741 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 749 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 759 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 760 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 761 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 750 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 751 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 752 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 753 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 754 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 762 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 763 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 764 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 755 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 756 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 757 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 758 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 774 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 773 of file stm32h7xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 772 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected input

Definition at line 783 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 784 of file stm32h7xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 782 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 792 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 793 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

Definition at line 794 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 805 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 803 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 806 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 807 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 808 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 809 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 802 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 804 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Trigger Output 2

Defines
Trigger Output 2
TIM Exported Constants

Defines

#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

CC1 capture or a compare match is used as trigger output 2

Definition at line 820 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

Counter Enable signal (CNT_EN) is used as trigger output 2

Definition at line 818 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2

OC1REF signal is used as trigger output 2

Definition at line 821 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output 2

Definition at line 822 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output 2

Definition at line 823 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output 2

Definition at line 824 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 830 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges are used as trigger output 2

Definition at line 829 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges are used as trigger output 2

Definition at line 827 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3

OC5REF signal is used as trigger output 2

Definition at line 825 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 832 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges are used as trigger output 2

Definition at line 831 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output 2

Definition at line 826 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges are used as trigger output 2

Definition at line 828 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output 2

Definition at line 817 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output 2

Definition at line 819 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

Definition at line 844 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 840 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 842 of file stm32h7xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 841 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 843 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR4 (TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR12 (TIM_SMCR_TS_4)
#define | LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 859 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 852 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 853 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 10 (ITR10) is used as trigger input

Definition at line 866 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 11 (ITR11) is used as trigger input

Definition at line 867 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4)

Internal Trigger 12 (ITR12) is used as trigger input

Definition at line 868 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)

Internal Trigger 13 (ITR13) is used as trigger input

Definition at line 869 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 854 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 855 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3)

Internal Trigger 4 (ITR4) is used as trigger input

Definition at line 860 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)

Internal Trigger 5 (ITR5) is used as trigger input

Definition at line 861 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 6 (ITR6) is used as trigger input

Definition at line 862 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 7 (ITR7) is used as trigger input

Definition at line 863 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 8 (ITR8) is used as trigger input

Definition at line 864 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 9 (ITR9) is used as trigger input

Definition at line 865 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 856 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 857 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 858 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 878 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 877 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 886 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 887 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 888 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 889 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 897 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=6

Definition at line 907 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 908 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=5

Definition at line 909 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 898 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 899 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 900 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 901 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 902 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 910 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 911 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 912 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 903 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 904 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 905 of file stm32h7xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 906 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 967 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 966 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: break filter

Defines
break filter
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

Define Documentation

#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 975 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U

fSAMPLING=fDTS/16, N=5

Definition at line 985 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U

fSAMPLING=fDTS/16, N=6

Definition at line 986 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U

fSAMPLING=fDTS/16, N=8

Definition at line 987 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U

fSAMPLING=fCK_INT, N=2

Definition at line 976 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U

fSAMPLING=fCK_INT, N=4

Definition at line 977 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U

fSAMPLING=fCK_INT, N=8

Definition at line 978 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U

fSAMPLING=fDTS/2, N=6

Definition at line 979 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U

fSAMPLING=fDTS/2, N=8

Definition at line 980 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U

fSAMPLING=fDTS/32, N=5

Definition at line 988 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U

fSAMPLING=fDTS/32, N=6

Definition at line 989 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

fSAMPLING=fDTS/32, N=8

Definition at line 990 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U

fSAMPLING=fDTS/4, N=6

Definition at line 981 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U

fSAMPLING=fDTS/4, N=8

Definition at line 982 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U

fSAMPLING=fDTS/8, N=6

Definition at line 983 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U

fSAMPLING=fDTS/8, N=8

Definition at line 984 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BREAK2 POLARITY

Defines
BREAK2 POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 999 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 998 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BREAK2 FILTER

Defines
BREAK2 FILTER
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

Define Documentation

#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 1007 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U

fSAMPLING=fDTS/16, N=5

Definition at line 1017 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U

fSAMPLING=fDTS/16, N=6

Definition at line 1018 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U

fSAMPLING=fDTS/16, N=8

Definition at line 1019 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U

fSAMPLING=fCK_INT, N=2

Definition at line 1008 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U

fSAMPLING=fCK_INT, N=4

Definition at line 1009 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U

fSAMPLING=fCK_INT, N=8

Definition at line 1010 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U

fSAMPLING=fDTS/2, N=6

Definition at line 1011 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U

fSAMPLING=fDTS/2, N=8

Definition at line 1012 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U

fSAMPLING=fDTS/32, N=5

Definition at line 1020 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U

fSAMPLING=fDTS/32, N=6

Definition at line 1021 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

fSAMPLING=fDTS/32, N=8

Definition at line 1022 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U

fSAMPLING=fDTS/4, N=6

Definition at line 1013 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U

fSAMPLING=fDTS/4, N=8

Definition at line 1014 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U

fSAMPLING=fDTS/8, N=6

Definition at line 1015 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U

fSAMPLING=fDTS/8, N=8

Definition at line 1016 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1030 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 1031 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1039 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 1040 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BREAK INPUT

Defines
BREAK INPUT
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

Define Documentation

#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U

TIMx_BKIN input

Definition at line 1049 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

TIMx_BKIN2 input

Definition at line 1050 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: BKIN SOURCE

Defines
BKIN SOURCE
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E

Define Documentation

#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E

internal signal: COMP1 output

Definition at line 1059 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E

internal signal: COMP2 output

Definition at line 1060 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE

BKIN input from AF controller

Definition at line 1058 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E

internal signal: DFSDM1 break output

Definition at line 1061 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: BKIN POLARITY

Defines
BKIN POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

Define Documentation

#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

BRK BKIN input is active high

Definition at line 1070 of file stm32h7xx_ll_tim.h.

#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP

BRK BKIN input is active low

Definition at line 1069 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 1090 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 1096 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 1087 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 1085 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 1086 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 1097 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 1092 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 1093 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 1094 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 1095 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR5 register is the DMA base address for DMA burst

Definition at line 1098 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR6 register is the DMA base address for DMA burst

Definition at line 1099 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 1088 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 1079 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 1080 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 1082 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 1084 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 1089 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 1091 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 1081 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 1083 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_TISEL register is the DMA base address for DMA burst

Definition at line 1104 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1121 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1122 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1123 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1124 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1125 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1126 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1127 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1128 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1129 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1112 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1113 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1114 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1115 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1116 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1117 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1118 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1119 of file stm32h7xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1120 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM1 Timer Input Ch1 Remap

Defines
TIM1 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
#define | TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */

Define Documentation

#define TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */

Definition at line 1138 of file stm32h7xx_ll_tim.h.

#define TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */

Definition at line 1137 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM8 Timer Input Ch1 Remap

Defines
TIM8 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
#define | TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */

Define Documentation

#define TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */

Definition at line 1147 of file stm32h7xx_ll_tim.h.

#define TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */

Definition at line 1146 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM2 Timer Input Ch4 Remap

Defines
TIM2 Timer Input Ch4 Remap
TIM Exported Constants

Defines

#define | TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
#define | TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */

Define Documentation

#define TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */

Definition at line 1156 of file stm32h7xx_ll_tim.h.

#define TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */

Definition at line 1158 of file stm32h7xx_ll_tim.h.

#define TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */

Definition at line 1157 of file stm32h7xx_ll_tim.h.

#define TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */

Definition at line 1155 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM3 Timer Input Ch1 Remap

Defines
TIM3 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
#define | TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */

Define Documentation

#define TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */

Definition at line 1167 of file stm32h7xx_ll_tim.h.

#define TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */

Definition at line 1169 of file stm32h7xx_ll_tim.h.

#define TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */

Definition at line 1168 of file stm32h7xx_ll_tim.h.

#define TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */

Definition at line 1166 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM5 Timer Input Ch1 Remap

Defines
TIM5 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
#define | TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */

Define Documentation

#define TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */

Definition at line 1179 of file stm32h7xx_ll_tim.h.

#define TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */

Definition at line 1178 of file stm32h7xx_ll_tim.h.

#define TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */

Definition at line 1177 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: TIM12 Timer Input Ch1 Remap

Defines
TIM12 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
#define | TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */

Define Documentation

#define TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */

Definition at line 1187 of file stm32h7xx_ll_tim.h.

#define TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */

Definition at line 1188 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM15 Timer Input Ch1 Remap

Defines
TIM15 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
#define | TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */

Define Documentation

#define TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */

Definition at line 1196 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */

Definition at line 1201 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */

Definition at line 1200 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */

Definition at line 1202 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */

Definition at line 1197 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */

Definition at line 1198 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */

Definition at line 1199 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM15 Timer Input Ch2 Remap

Defines
TIM15 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
#define | TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */

Define Documentation

#define TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */

Definition at line 1210 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */

Definition at line 1211 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */

Definition at line 1212 of file stm32h7xx_ll_tim.h.

#define TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */

Definition at line 1213 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM16 Timer Input Ch1 Remap

Defines
TIM16 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
#define | TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */

Define Documentation

#define TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */

Definition at line 1221 of file stm32h7xx_ll_tim.h.

#define TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */

Definition at line 1223 of file stm32h7xx_ll_tim.h.

#define TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */

Definition at line 1222 of file stm32h7xx_ll_tim.h.

#define TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */

Definition at line 1224 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM17 Timer Input Ch1 Remap

Defines
TIM17 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
#define | TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
#define | TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
#define | TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */

Define Documentation

#define TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */

Definition at line 1232 of file stm32h7xx_ll_tim.h.

#define TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */

Definition at line 1234 of file stm32h7xx_ll_tim.h.

#define TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */

Definition at line 1235 of file stm32h7xx_ll_tim.h.

#define TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */

Definition at line 1233 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM23 Timer Input Ch4 Remap

Defines
TIM23 Timer Input Ch4 Remap
TIM Exported Constants

Defines

#define | TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
#define | TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
#define | TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
#define | TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */

Define Documentation

#define TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */

Definition at line 1244 of file stm32h7xx_ll_tim.h.

#define TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */

Definition at line 1246 of file stm32h7xx_ll_tim.h.

#define TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */

Definition at line 1245 of file stm32h7xx_ll_tim.h.

#define TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */

Definition at line 1243 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM24 Timer Input Ch1 Remap

Defines
TIM24 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
#define | TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
#define | TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
#define | TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */

Define Documentation

#define TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */

Definition at line 1256 of file stm32h7xx_ll_tim.h.

#define TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */

Definition at line 1257 of file stm32h7xx_ll_tim.h.

#define TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */

Definition at line 1255 of file stm32h7xx_ll_tim.h.

#define TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */

Definition at line 1254 of file stm32h7xx_ll_tim.h.

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STM32H7B3xQ HAL User Manual: TIM Exported Constants

Modules | Defines
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Break2 Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
GROUPCH5
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Trigger Output 2
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
break polarity
break filter
BREAK2 POLARITY
BREAK2 FILTER
OSSI
OSSR
BREAK INPUT
BKIN SOURCE
BKIN POLARITY
DMA Burst Base Address
DMA Burst Length
TIM1 Timer Input Ch1 Remap
TIM8 Timer Input Ch1 Remap
TIM2 Timer Input Ch4 Remap
TIM3 Timer Input Ch1 Remap
TIM5 Timer Input Ch1 Remap
TIM12 Timer Input Ch1 Remap
TIM15 Timer Input Ch1 Remap
TIM15 Timer Input Ch2 Remap
TIM16 Timer Input Ch1 Remap
TIM17 Timer Input Ch1 Remap
TIM23 Timer Input Ch4 Remap
TIM24 Timer Input Ch1 Remap

Defines

#define | LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define | LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
#define | LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define | LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define | LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define | LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define | LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define | LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define | LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define | LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define | LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

Define Documentation

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 920 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 921 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 922 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */

Definition at line 923 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

Definition at line 924 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */

Definition at line 925 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */

Definition at line 918 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */

Definition at line 919 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */

Definition at line 917 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */

Definition at line 954 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */

Definition at line 955 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */

Definition at line 953 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */

Definition at line 957 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */

Definition at line 960 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

Definition at line 961 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */

Definition at line 958 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */

Definition at line 959 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */

Definition at line 938 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */

Definition at line 939 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */

Definition at line 937 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */

Definition at line 940 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */

Definition at line 941 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */

Definition at line 942 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */

Definition at line 945 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */

Definition at line 944 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */

Definition at line 947 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */

Definition at line 948 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */

Definition at line 949 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */

Definition at line 950 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */

Definition at line 951 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */

Definition at line 930 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */

Definition at line 931 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */

Definition at line 932 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */

Definition at line 933 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

Definition at line 934 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */

Definition at line 935 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */

Definition at line 928 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */

Definition at line 929 of file stm32h7xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */

Definition at line 927 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1299 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1291 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1355 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
    0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1330 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1366 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1344 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1379 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1393 of file stm32h7xx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1316 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1602 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1431 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUIFRemap ( TIM_TypeDef * TIMx )

Disable update interrupt flag (UIF) remapping.

Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_DisableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1795 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1464 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1591 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1420 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUIFRemap ( TIM_TypeDef * TIMx )

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_EnableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1784 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1453 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1744 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1648 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 1675 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1580 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1688 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1536 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1715 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1772 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1509 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1613 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1442 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
Inverted state of bit (0 or 1).

Definition at line 1475 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1731 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1631 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 1662 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1560 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1523 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1704 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1759 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1496 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1951 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1831 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1922 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1818 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 1874 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 1980 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 1861 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 1893 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 1847 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCMR3 CC5S LL_TIM_OC_ConfigOutput
CCMR3 CC6S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2025 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
CCMR3 OC5CE LL_TIM_OC_DisableClear
CCMR3 OC6CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2453 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
CCMR3 OC5FE LL_TIM_OC_DisableFast
CCMR3 OC6FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2295 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
CCMR3 OC5PE LL_TIM_OC_DisablePreload
CCMR3 OC6PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2372 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
CCMR3 OC5CE LL_TIM_OC_EnableClear
CCMR3 OC6CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2426 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
CCMR3 OC5FE LL_TIM_OC_EnableFast
CCMR3 OC6FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2269 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
CCMR3 OC5PE LL_TIM_OC_EnablePreload
CCMR3 OC6PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2347 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2612 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2628 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2644 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2660 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR5) set for output channel 5.

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_GetCompareCH5
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2673 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR6) set for output channel 6.

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_GetCompareCH6
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2686 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2244 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
CCMR3 OC5M LL_TIM_OC_GetMode
CCMR3 OC6M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2

Definition at line 2109 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2175 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
CCMR3 OC5CE LL_TIM_OC_IsEnabledClear
CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2482 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
CCMR3 OC5FE LL_TIM_OC_IsEnabledFast
CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2321 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2397 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2517 of file stm32h7xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2534 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2551 of file stm32h7xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2568 of file stm32h7xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH5 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 5 (TIMx_CCR5).

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_SetCompareCH5
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2582 of file stm32h7xx_ll_tim.h.

Referenced by OC5Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH6 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 6 (TIMx_CCR6).

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_SetCompareCH6
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2596 of file stm32h7xx_ll_tim.h.

Referenced by OC6Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 2500 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2212 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
CCMR3 OC5M LL_TIM_OC_SetMode
CCMR3 OC6M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
Return values:
None

Definition at line 2070 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 2143 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | GroupCH5
 | ) |  |

Select on which reference signal the OC5REF is combined to.

Note:
Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the combined 3-phase PWM mode.
Reference Manual to LL API cross reference:
CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
Parameters:
TIMx Timer instance
GroupCH5 This parameter can be a combination of the following values:
  • LL_TIM_GROUPCH5_NONE
  • LL_TIM_GROUPCH5_OC1REFC
  • LL_TIM_GROUPCH5_OC2REFC
  • LL_TIM_GROUPCH5_OC3REFC
Return values:
None

Definition at line 2706 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2753 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3016 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3003 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2805 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3045 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3061 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3077 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3093 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 2931 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 2988 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 2856 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3029 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2781 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 2894 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2960 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 2831 of file stm32h7xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3127 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3114 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3140 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3164 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 3181 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 3372 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3319 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3306 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3332 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetETRSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRSource
 | ) |  |

Select the external trigger (ETR) input source.

Note:
Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or not a timer instance supports ETR source selection.
Reference Manual to LL API cross reference:
AF1 ETRSEL LL_TIM_SetETRSource
Parameters:
TIMx Timer instance
ETRSource This parameter can be one of the following values: For TIM1, the parameter is one of the following values:
  • LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO
  • LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output
  • LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
For TIM2, the parameter is one of the following values:
  • LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO
  • LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output
  • LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output
  • LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
For TIM3, the parameter is one of the following values:
  • LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO
  • LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output
For TIM5, the parameter is one of the following values:
  • LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
For TIM8, the parameter is one of the following values:
  • LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO
  • LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output
  • LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
For TIM23, the parameter is one of the following values: (*)
  • LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO
  • LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output
  • LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output
For TIM24, the parameter is one of the following values: (*)
  • LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
(*) Value not defined in all devices.
Return values:
None

Definition at line 3441 of file stm32h7xx_ll_tim.h.

References TIMx_AF1_ETRSEL.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Return values:
None

Definition at line 3259 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
  • LL_TIM_TS_ITR4
  • LL_TIM_TS_ITR5
  • LL_TIM_TS_ITR6
  • LL_TIM_TS_ITR7
  • LL_TIM_TS_ITR8 (*)
  • LL_TIM_TS_ITR9 (*)
  • LL_TIM_TS_ITR10 (*)
  • LL_TIM_TS_ITR11 (*)
  • LL_TIM_TS_ITR12 (*)
  • LL_TIM_TS_ITR13 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 3293 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 3210 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ADCSynchronization
 | ) |  |

Set the trigger output 2 (TRGO2) used for ADC synchronization .

Note:
Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check whether or not a timer instance can be used for ADC synchronization.
Reference Manual to LL API cross reference:
CR2 MMS2 LL_TIM_SetTriggerOutput2
Parameters:
TIMx Timer Instance
ADCSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO2_RESET
  • LL_TIM_TRGO2_ENABLE
  • LL_TIM_TRGO2_UPDATE
  • LL_TIM_TRGO2_CC1F
  • LL_TIM_TRGO2_OC1
  • LL_TIM_TRGO2_OC2
  • LL_TIM_TRGO2_OC3
  • LL_TIM_TRGO2_OC4
  • LL_TIM_TRGO2_OC5
  • LL_TIM_TRGO2_OC6
  • LL_TIM_TRGO2_OC4_RISINGFALLING
  • LL_TIM_TRGO2_OC6_RISINGFALLING
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
Return values:
None

Definition at line 3240 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity,
 |  | uint32_t | BreakFilter
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
BDTR BKF LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
BreakFilter This parameter can be one of the following values:
  • LL_TIM_BREAK_FILTER_FDIV1
  • LL_TIM_BREAK_FILTER_FDIV1_N2
  • LL_TIM_BREAK_FILTER_FDIV1_N4
  • LL_TIM_BREAK_FILTER_FDIV1_N8
  • LL_TIM_BREAK_FILTER_FDIV2_N6
  • LL_TIM_BREAK_FILTER_FDIV2_N8
  • LL_TIM_BREAK_FILTER_FDIV4_N6
  • LL_TIM_BREAK_FILTER_FDIV4_N8
  • LL_TIM_BREAK_FILTER_FDIV8_N6
  • LL_TIM_BREAK_FILTER_FDIV8_N8
  • LL_TIM_BREAK_FILTER_FDIV16_N5
  • LL_TIM_BREAK_FILTER_FDIV16_N6
  • LL_TIM_BREAK_FILTER_FDIV16_N8
  • LL_TIM_BREAK_FILTER_FDIV32_N5
  • LL_TIM_BREAK_FILTER_FDIV32_N6
  • LL_TIM_BREAK_FILTER_FDIV32_N8
Return values:
None

Definition at line 3509 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ConfigBRK2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Break2Polarity,
 |  | uint32_t | Break2Filter
 | ) |  |

Configure the break 2 input.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2P LL_TIM_ConfigBRK2
BDTR BK2F LL_TIM_ConfigBRK2
Parameters:
TIMx Timer instance
Break2Polarity This parameter can be one of the following values:
  • LL_TIM_BREAK2_POLARITY_LOW
  • LL_TIM_BREAK2_POLARITY_HIGH
Break2Filter This parameter can be one of the following values:
  • LL_TIM_BREAK2_FILTER_FDIV1
  • LL_TIM_BREAK2_FILTER_FDIV1_N2
  • LL_TIM_BREAK2_FILTER_FDIV1_N4
  • LL_TIM_BREAK2_FILTER_FDIV1_N8
  • LL_TIM_BREAK2_FILTER_FDIV2_N6
  • LL_TIM_BREAK2_FILTER_FDIV2_N8
  • LL_TIM_BREAK2_FILTER_FDIV4_N6
  • LL_TIM_BREAK2_FILTER_FDIV4_N8
  • LL_TIM_BREAK2_FILTER_FDIV8_N6
  • LL_TIM_BREAK2_FILTER_FDIV8_N8
  • LL_TIM_BREAK2_FILTER_FDIV16_N5
  • LL_TIM_BREAK2_FILTER_FDIV16_N6
  • LL_TIM_BREAK2_FILTER_FDIV16_N8
  • LL_TIM_BREAK2_FILTER_FDIV32_N5
  • LL_TIM_BREAK2_FILTER_FDIV32_N6
  • LL_TIM_BREAK2_FILTER_FDIV32_N8
Return values:
None

Definition at line 3570 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3659 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3616 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Disable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_DisableBreakInputSource
AF1 BKCMP1E LL_TIM_DisableBreakInputSource
AF1 BKCMP2E LL_TIM_DisableBreakInputSource
AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource
AF2 BK2INE LL_TIM_DisableBreakInputSource
AF2 BK2CMP1E LL_TIM_DisableBreakInputSource
AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_DF1BK
Return values:
None

Definition at line 3730 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 3475 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK2 ( TIM_TypeDef * TIMx )

Disable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_DisableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3536 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3644 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3603 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Enable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_EnableBreakInputSource
AF1 BKCMP1E LL_TIM_EnableBreakInputSource
AF1 BKCMP2E LL_TIM_EnableBreakInputSource
AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource
AF2 BK2INE LL_TIM_EnableBreakInputSource
AF2 BK2CMP1E LL_TIM_EnableBreakInputSource
AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_DF1BK
Return values:
None

Definition at line 3701 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3462 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK2 ( TIM_TypeDef * TIMx )

Enable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_EnableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3523 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3672 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3629 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the break signal for the timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINP LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
Polarity This parameter can be one of the following values:
  • LL_TIM_BKIN_POLARITY_LOW
  • LL_TIM_BKIN_POLARITY_HIGH
Return values:
None

Definition at line 3759 of file stm32h7xx_ll_tim.h.

References TIM_POSITION_BRK_SOURCE, and TIMx_AF1_BKINP.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 3590 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_CCMR3
  • LL_TIM_DMABURST_BASEADDR_CCR5
  • LL_TIM_DMABURST_BASEADDR_CCR6
  • LL_TIM_DMABURST_BASEADDR_AF1
  • LL_TIM_DMABURST_BASEADDR_AF2
  • LL_TIM_DMABURST_BASEADDR_TISEL
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 3827 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).

Function Documentation

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped. TIM1: one of the following values:
  • TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
TIM2: one of the following values:
  • TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
  • TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
  • TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
  • TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
TIM3: one of the following values:
  • TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
  • TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
TIM5: one of the following values:
  • TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
  • TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP
  • TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP
TIM8: one of the following values:
  • TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
  • TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
TIM12: one of the following values: (*)
  • TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
  • TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
TIM15: one of the following values:
  • TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1
  • TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1
  • TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1
  • TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
  • TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI
  • TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
  • TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
  • TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2
  • TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2
  • TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2
TIM16: one of the following values:
  • TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
TIM17: one of the following values:
  • TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
  • TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
  • TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
TIM23: one of the following values: (*)
  • TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO
  • TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output
  • TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output
  • TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
TIM24: one of the following values: (*)
  • TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO
  • TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP
  • TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP
  • TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC
(*) Value not defined in all devices.
Return values:
None

Definition at line 3912 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4128 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_BRK2 ( TIM_TypeDef * TIMx )

Clear the break 2 interrupt flag (B2IF).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_ClearFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4150 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3952 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4172 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3974 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4194 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3996 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4216 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4018 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4238 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC5 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 5 interrupt flag (CC5F).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_ClearFlag_CC5
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4040 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC6 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 6 interrupt flag (CC6F).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_ClearFlag_CC6
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4062 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4084 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK ( TIM_TypeDef * TIMx )

Clear the system break interrupt flag (SBIF).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_ClearFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4260 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4106 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3930 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4139 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2 ( TIM_TypeDef * TIMx )

Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_IsActiveFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4161 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3963 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4183 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3985 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4205 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4007 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4227 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4029 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4249 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_IsActiveFlag_CC5
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4051 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_IsActiveFlag_CC6
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4073 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4095 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK ( TIM_TypeDef * TIMx )

Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_IsActiveFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4271 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4117 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3941 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4531 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4333 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4366 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4399 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4432 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4465 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4498 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4300 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4520 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4322 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4355 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4388 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4421 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4454 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4487 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4289 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4542 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4344 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4377 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4410 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4443 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4476 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4509 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4311 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA-Management

Functions
DMA-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4604 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4637 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4670 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4703 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4736 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4769 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4571 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4593 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4626 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4659 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4692 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4725 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4758 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4560 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4615 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4648 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4681 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4714 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4747 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4780 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4582 of file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4875 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2 ( TIM_TypeDef * TIMx )

Generate break 2 event.

Reference Manual to LL API cross reference:
EGR B2G LL_TIM_GenerateEvent_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4886 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4809 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4820 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4831 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4842 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4853 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4864 of file stm32h7xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4798 of file stm32h7xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 743 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK2_FILTER, IS_LL_TIM_BREAK2_POLARITY, IS_LL_TIM_BREAK2_STATE, IS_LL_TIM_BREAK_FILTER, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 711 of file stm32h7xx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK2_DISABLE, LL_TIM_BREAK2_FILTER_FDIV1, LL_TIM_BREAK2_POLARITY_LOW, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_FILTER_FDIV1, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 217 of file stm32h7xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM12, LL_APB1_GRP1_PERIPH_TIM13, LL_APB1_GRP1_PERIPH_TIM14, LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_PERIPH_TIM5, LL_APB1_GRP1_PERIPH_TIM6, LL_APB1_GRP1_PERIPH_TIM7, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, LL_APB2_GRP1_PERIPH_TIM15, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, LL_APB2_GRP1_PERIPH_TIM8, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 542 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 520 of file stm32h7xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used when TIMx operates in Hall sensor interface mode.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 633 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 604 of file stm32h7xx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 490 of file stm32h7xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 468 of file stm32h7xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 352 of file stm32h7xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 431 of file stm32h7xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6, OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 403 of file stm32h7xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 334 of file stm32h7xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Private Variables

Variables
USART Private Variables
USART

Variables

static const uint32_t USART_PRESCALER_TAB []

Variable Documentation

const uint32_t USART_PRESCALER_TAB[] [static]
Initial value:
{
  1UL,
  2UL,
  4UL,
  6UL,
  8UL,
  10UL,
  12UL,
  16UL,
  32UL,
  64UL,
  128UL,
  256UL
}

Definition at line 47 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 12500000U)

Definition at line 64 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 70 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 16U)

Definition at line 67 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 97 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 91 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 94 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_7B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 81 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 72 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 105 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 88 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 85 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                       || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 77 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PRESCALER_DIV1) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))

Definition at line 49 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 100 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32h7xx_ll_usart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 86 of file stm32h7xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 93 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 97 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 117 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 122 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 107 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_USART_SetPrescaler().

Definition at line 88 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 102 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 112 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_usart.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32h7xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 132 of file stm32h7xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 134 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 147 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 141 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 153 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_usart.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 189 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 185 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block flag

Definition at line 187 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 177 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 180 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection flag

Definition at line 184 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_NECF USART_ICR_NECF

Noise error detected flag

Definition at line 178 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 179 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 176 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout flag

Definition at line 186 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF

Transmission completed before guard time flag

Definition at line 183 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 182 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty Clear flag

Definition at line 181 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_UDRCF USART_ICR_UDRCF

SPI Slave Underrun Clear flag

Definition at line 188 of file stm32h7xx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 190 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 213 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 214 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 215 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 216 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 209 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 208 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 211 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 200 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 203 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 207 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 201 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 202 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 199 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 221 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 210 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 218 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 223 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 225 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 204 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 217 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 205 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TCBGT USART_ISR_TCBGT

Transmission complete before guard time completion flag

Definition at line 224 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 220 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 206 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 222 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 226 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_UDR USART_ISR_UDR

SPI Slave underrun error flag

Definition at line 212 of file stm32h7xx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 219 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 240 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 242 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 235 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 239 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 241 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 244 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 236 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 237 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 238 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 243 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 245 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 247 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 246 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 251 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE

Transmission complete before guard time interrupt enable

Definition at line 250 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 249 of file stm32h7xx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 248 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
USART Exported Constants

Defines

#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 261 of file stm32h7xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 260 of file stm32h7xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 259 of file stm32h7xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 262 of file stm32h7xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 263 of file stm32h7xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 264 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 272 of file stm32h7xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 273 of file stm32h7xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 274 of file stm32h7xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 275 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 284 of file stm32h7xx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 283 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 285 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 294 of file stm32h7xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 293 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_USART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 302 of file stm32h7xx_ll_usart.h.

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 303 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 304 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 312 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 313 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 323 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 324 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 333 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 334 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 342 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 343 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 352 of file stm32h7xx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 351 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

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STM32H7B3xQ HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
USART Exported Constants

Defines

#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_USART_PRESCALER_DIV1 0x00000000U

Input clock not devided

Definition at line 360 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock devided by 10

Definition at line 365 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock devided by 12

Definition at line 366 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock devided by 128

Definition at line 370 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 16

Definition at line 367 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock devided by 2

Definition at line 361 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 256

Definition at line 371 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock devided by 32

Definition at line 368 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock devided by 4

Definition at line 362 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 6

Definition at line 363 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock devided by 64

Definition at line 369 of file stm32h7xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock devided by 8

Definition at line 364 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 379 of file stm32h7xx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 380 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 381 of file stm32h7xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 382 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 390 of file stm32h7xx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 391 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 400 of file stm32h7xx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 399 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 409 of file stm32h7xx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 408 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 418 of file stm32h7xx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 417 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 426 of file stm32h7xx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 427 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 438 of file stm32h7xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 437 of file stm32h7xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 436 of file stm32h7xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 435 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 446 of file stm32h7xx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 447 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 457 of file stm32h7xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 455 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 456 of file stm32h7xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 458 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 466 of file stm32h7xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 468 of file stm32h7xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 467 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 477 of file stm32h7xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 476 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 485 of file stm32h7xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 486 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 494 of file stm32h7xx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 495 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 504 of file stm32h7xx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 503 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

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STM32H7B3xQ HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 537 of file stm32h7xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 529 of file stm32h7xx_ll_usart.h.

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STM32H7B3xQ HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
                                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 589 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
                                                                               + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 566 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1333 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1180 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
Parameters:
USARTx USART Instance
TXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 786 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1611 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 630 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1502 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1692 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 850 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 872 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Disable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_DisableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 667 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 815 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1020 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1751 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1784 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1666 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1572 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1257 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit().

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 616 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1489 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1679 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 839 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 861 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Enable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_EnableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 654 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 801 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1009 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1740 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1773 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1653 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1561 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1244 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1550 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1912 of file stm32h7xx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1445 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1984 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 1121 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 1152 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 998 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1729 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 1090 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1627 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1640 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 1058 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 940 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetPrescaler ( USART_TypeDef * USARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_GetPrescaler
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256

Definition at line 1231 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold ( USART_TypeDef * USARTx )

Return RX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 758 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1389 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1961 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1301 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1476 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 906 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold ( USART_TypeDef * USARTx )

Return TX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 719 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1416 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1362 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 967 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1828 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 641 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1515 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO ( USART_TypeDef * USARTx )

Indicate if FIFO Mode is enabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_IsEnabledFIFO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 680 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 828 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1031 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1762 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1795 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1583 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1270 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1533 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1862 of file stm32h7xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, LL_USART_OVERSAMPLING_8, and LL_USART_PRESCALER_DIV256.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1432 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1973 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 1106 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 1137 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 983 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1711 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1074 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 1045 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 925 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_SetPrescaler
Parameters:
USARTx USART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
Return values:
None

Definition at line 1206 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetRXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 739 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1376 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1950 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1286 of file stm32h7xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1461 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 890 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 700 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1403 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1349 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 954 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1812 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2018 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2005 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 2062 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2091 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2031 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 2047 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2077 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2164 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2125 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2151 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2112 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 2209 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2267 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 2238 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2177 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2138 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 2196 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2253 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2224 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2301 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2288 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2314 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to SPI Slave feature

Functions
Configuration functions related to SPI Slave feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.

Function Documentation

__STATIC_INLINE void LL_USART_DisableSPISlave ( USART_TypeDef * USARTx )

Disable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_DisableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2347 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSPISlaveSelect ( USART_TypeDef * USARTx )

Disable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave will be always selected and NSS input pin will be ignored.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2389 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlave ( USART_TypeDef * USARTx )

Enable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_EnableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2334 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlaveSelect ( USART_TypeDef * USARTx )

Enable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave Selection depends on NSS input pin (The slave is selected when NSS is low and deselected when NSS is high).
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2375 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave ( USART_TypeDef * USARTx )

Indicate if SPI Synchronous Slave mode is enabled.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_IsEnabledSPISlave
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2360 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect ( USART_TypeDef * USARTx )

Indicate if SPI Slave Selection depends on NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2402 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2467 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2454 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2441 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2480 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2426 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2568 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2555 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2542 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2515 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2612 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2581 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2529 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2502 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2597 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2650 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2764 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2847 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2726 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2885 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2804 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2686 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
USART Exported Functions

Defines

#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE

Definition at line 2958 of file stm32h7xx_ll_usart.h.

#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Definition at line 2985 of file stm32h7xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3403 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3379 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3261 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3294 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3342 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3355 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise Error detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3272 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3283 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3250 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3366 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3318 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TCBGT ( USART_TypeDef * USARTx )

Clear Smartcard Transmission Complete Before Guard Time Flag.

Reference Manual to LL API cross reference:
ICR TCBGTCF LL_USART_ClearFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3329 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TXFE ( USART_TypeDef * USARTx )

Clear TX FIFO Empty Flag.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR TXFECF LL_USART_ClearFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3307 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_UDR ( USART_TypeDef * USARTx )

Clear SPI Slave Underrun Flag.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR UDRCF LL_USART_ClearFlag_UDR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3392 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3416 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3097 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3084 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3108 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3119 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3034 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3058 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2919 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2952 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3008 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3021 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2930 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2941 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2908 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3176 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3045 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3141 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFF LL_USART_IsActiveFlag_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3202 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFT LL_USART_IsActiveFlag_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3239 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE ( USART_TypeDef * USARTx )

Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2968 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3130 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2979 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT ( USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.

Reference Manual to LL API cross reference:
ISR TCBGT LL_USART_IsActiveFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3213 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3165 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF ( USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2995 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFE LL_USART_IsActiveFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3189 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFT LL_USART_IsActiveFlag_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3226 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR ( USART_TypeDef * USARTx )

Check if the SPI Slave Underrun error flag is set or not.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR UDR LL_USART_IsActiveFlag_UDR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3071 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3154 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:38 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT_Management

Defines | Functions
IT_Management
USART Exported Functions

Defines

#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE

Definition at line 3658 of file stm32h7xx_ll_usart.h.

#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF

Definition at line 3685 of file stm32h7xx_ll_usart.h.

#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE

Definition at line 3441 of file stm32h7xx_ll_usart.h.

#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF

Definition at line 3468 of file stm32h7xx_ll_usart.h.

#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE

Definition at line 3877 of file stm32h7xx_ll_usart.h.

#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Definition at line 3904 of file stm32h7xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3717 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3808 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3741 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3795 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3652 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3780 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3706 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3728 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFF ( USART_TypeDef * USARTx )

Disable RX FIFO Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_DisableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3767 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFT ( USART_TypeDef * USARTx )

Disable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_DisableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3860 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3668 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3679 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TCBGT ( USART_TypeDef * USARTx )

Disable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_DisableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3847 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3695 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFE ( USART_TypeDef * USARTx )

Disable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_DisableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3754 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFT ( USART_TypeDef * USARTx )

Disable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_DisableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3834 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3821 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3500 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3589 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3524 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3576 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3435 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3561 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3489 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3511 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFF ( USART_TypeDef * USARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_EnableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3548 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFT ( USART_TypeDef * USARTx )

Enable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_EnableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3641 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3451 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3462 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TCBGT ( USART_TypeDef * USARTx )

Enable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_EnableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3628 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3478 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFE ( USART_TypeDef * USARTx )

Enable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_EnableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3537 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFT ( USART_TypeDef * USARTx )

Enable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_EnableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3615 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3602 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3936 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4023 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3960 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4010 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3871 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3999 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3925 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3947 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3986 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT ( USART_TypeDef * USARTx )

Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4075 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3887 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3898 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT ( USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4062 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3914 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3973 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT ( USART_TypeDef * USARTx )

Check if USART TX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4049 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4036 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4171 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4105 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4138 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 4197 of file stm32h7xx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4160 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4094 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4127 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4182 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4116 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4149 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 4229 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 4240 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 4252 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 4264 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4285 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4296 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4307 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4322 of file stm32h7xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4335 of file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx | USART Instance
USART_ClockInitStruct | pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 407 of file stm32h7xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_DisableSCLKOutput(), and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 466 of file stm32h7xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 132 of file stm32h7xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_UART4, LL_APB1_GRP1_PERIPH_UART5, LL_APB1_GRP1_PERIPH_UART7, LL_APB1_GRP1_PERIPH_UART8, LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_UART9, LL_APB2_GRP1_PERIPH_USART1, LL_APB2_GRP1_PERIPH_USART10, LL_APB2_GRP1_PERIPH_USART6, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx | USART Instance
USART_InitStruct | pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 244 of file stm32h7xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_BRR_MAX, IS_LL_USART_BRR_MIN, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_PRESCALER, IS_LL_USART_STOPBITS, LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART16_CLKSOURCE, LL_RCC_USART234578_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetPrescaler(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 382 of file stm32h7xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_PRESCALER_DIV1, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_CalculateFlashLatency (uint32_t HCLK_Frequency, uint32_t *latency)
Calculate and check the Flash wait states number according to the new HCLK frequency and current voltage range.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t latency)
Update number of Flash wait states.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_IsPLLsReady (void)
Check that all PLLs are ready therefore configuration can be done.

Function Documentation

static ErrorStatus UTILS_CalculateFlashLatency | ( | uint32_t | HCLK_Frequency,
 |  | uint32_t * | latency
 | ) |  | [static]

Calculate and check the Flash wait states number according to the new HCLK frequency and current voltage range.

Parameters:
HCLK_Frequency HCLK frequency
latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
  • LL_FLASH_LATENCY_5
  • LL_FLASH_LATENCY_6
  • LL_FLASH_LATENCY_7
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 535 of file stm32h7xx_ll_utils.c.

References LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_PWR_GetRegulVoltageScaling(), LL_PWR_REGU_VOLTAGE_SCALE1, LL_PWR_REGU_VOLTAGE_SCALE2, UTILS_SCALE1_LATENCY0_FREQ, UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_FREQ, UTILS_SCALE2_LATENCY0_FREQ, UTILS_SCALE2_LATENCY1_FREQ, UTILS_SCALE2_LATENCY2_FREQ, UTILS_SCALE2_LATENCY3_FREQ, UTILS_SCALE3_LATENCY0_FREQ, UTILS_SCALE3_LATENCY1_FREQ, UTILS_SCALE3_LATENCY2_FREQ, UTILS_SCALE3_LATENCY3_FREQ, and UTILS_SCALE3_LATENCY4_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 720 of file stm32h7xx_ll_utils.c.

References LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, LL_UTILS_ClkInitTypeDef::APB3CLKDivider, LL_UTILS_ClkInitTypeDef::APB4CLKDivider, assert_param, IS_LL_UTILS_AHB_DIV, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_APB3_DIV, IS_LL_UTILS_APB4_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_FLASH_GetLatency(), LL_RCC_APB1_DIV_16, LL_RCC_APB2_DIV_16, LL_RCC_APB3_DIV_16, LL_RCC_APB4_DIV_16, LL_RCC_CALC_HCLK_FREQ, LL_RCC_GetSysClkSource(), LL_RCC_PLL1_Enable(), LL_RCC_PLL1_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetAPB3Prescaler(), LL_RCC_SetAPB4Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SetSysPrescaler(), LL_RCC_SYS_CLKSOURCE_PLL1, LL_RCC_SYS_CLKSOURCE_STATUS_PLL1, LL_SetSystemCoreClock(), LL_UTILS_ClkInitTypeDef::SYSCLKDivider, UTILS_CalculateFlashLatency(), and UTILS_SetFlashLatency().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 662 of file stm32h7xx_ll_utils.c.

References assert_param, LL_UTILS_PLLInitTypeDef::FRACN, IS_LL_UTILS_FRACN_VALUE, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLP_VALUE, LL_RCC_CalcPLLClockFreq(), LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, and LL_UTILS_PLLInitTypeDef::PLLP.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_IsPLLsReady ( void ) [static]

Check that all PLLs are ready therefore configuration can be done.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: All PLLs are ready so configuration can be done
  • ERROR: One PLL at least is busy

Definition at line 683 of file stm32h7xx_ll_utils.c.

References LL_RCC_PLL1_IsReady(), LL_RCC_PLL2_IsReady(), and LL_RCC_PLL3_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_SetFlashLatency ( uint32_t latency ) [static]

Update number of Flash wait states.

Parameters:
latency Flash Latency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 639 of file stm32h7xx_ll_utils.c.

References LL_FLASH_GetLatency(), and LL_FLASH_SetLatency().

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_MAX_FREQUENCY_SCALE1 400000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 300000000U
#define | UTILS_MAX_FREQUENCY_SCALE3 200000000U
#define | UTILS_PLLVCO_INPUT_MIN1 1000000U
#define | UTILS_PLLVCO_INPUT_MAX1 2000000U
#define | UTILS_PLLVCO_INPUT_MIN2 2000000U
#define | UTILS_PLLVCO_INPUT_MAX2 4000000U
#define | UTILS_PLLVCO_INPUT_MIN3 4000000U
#define | UTILS_PLLVCO_INPUT_MAX3 8000000U
#define | UTILS_PLLVCO_INPUT_MIN4 8000000U
#define | UTILS_PLLVCO_INPUT_MAX4 16000000U
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U
#define | UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U
#define | UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY0_FREQ 70000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 140000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 210000000U
#define | UTILS_SCALE2_LATENCY0_FREQ 55000000U
#define | UTILS_SCALE2_LATENCY1_FREQ 110000000U
#define | UTILS_SCALE2_LATENCY2_FREQ 165000000U
#define | UTILS_SCALE2_LATENCY3_FREQ 220000000U
#define | UTILS_SCALE3_LATENCY0_FREQ 45000000U
#define | UTILS_SCALE3_LATENCY1_FREQ 90000000U
#define | UTILS_SCALE3_LATENCY2_FREQ 135000000U
#define | UTILS_SCALE3_LATENCY3_FREQ 180000000U
#define | UTILS_SCALE3_LATENCY4_FREQ 225000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 72 of file stm32h7xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 62 of file stm32h7xx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 77 of file stm32h7xx_ll_utils.h.

Referenced by LL_GetPackageType().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 67 of file stm32h7xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX 48000000U

Frequency max for HSE frequency, in Hz

Definition at line 65 of file stm32h7xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN 4000000U

Frequency min for HSE frequency, in Hz

Definition at line 64 of file stm32h7xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE1 400000000U

Maximum frequency for system clock at power scale1, in Hz

Definition at line 44 of file stm32h7xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE2 300000000U

Maximum frequency for system clock at power scale2, in Hz

Definition at line 45 of file stm32h7xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE3 200000000U

Maximum frequency for system clock at power scale3, in Hz

Definition at line 46 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX1 2000000U

Frequency max for the wide range PLLVCO input, in Hz

Definition at line 50 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX2 4000000U

Frequency max for the wide range PLLVCO input, in Hz

Definition at line 52 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX3 8000000U

Frequency max for the wide range PLLVCO input, in Hz

Definition at line 54 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX4 16000000U

Frequency max for the wide range PLLVCO input, in Hz

Definition at line 56 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN1 1000000U

Frequency min for the low range PLLVCO input, in Hz

Definition at line 49 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN2 2000000U

Frequency min for the low range PLLVCO input, in Hz

Definition at line 51 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN3 4000000U

Frequency min for the low range PLLVCO input, in Hz

Definition at line 53 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN4 8000000U

Frequency min for the low range PLLVCO input, in Hz

Definition at line 55 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U

Frequency max for the wide range PLLVCO output, in Hz

Definition at line 60 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U

Frequency min for the medium range PLLVCO output, in Hz

Definition at line 58 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U

Frequency max for the wide range PLLVCO output, in Hz

Definition at line 61 of file stm32h7xx_ll_utils.c.

#define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U

Frequency min for the wide range PLLVCO output, in Hz

Definition at line 59 of file stm32h7xx_ll_utils.c.

#define UTILS_SCALE1_LATENCY0_FREQ 70000000U

HCLK frequency to set FLASH latency 0 in power scale 1

Definition at line 68 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE1_LATENCY1_FREQ 140000000U

HCLK frequency to set FLASH latency 1 in power scale 1

Definition at line 69 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE1_LATENCY2_FREQ 210000000U

HCLK frequency to set FLASH latency 2 in power scale 1

Definition at line 70 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE2_LATENCY0_FREQ 55000000U

HCLK frequency to set FLASH latency 0 in power scale 2

Definition at line 72 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE2_LATENCY1_FREQ 110000000U

HCLK frequency to set FLASH latency 1 in power scale 2

Definition at line 73 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE2_LATENCY2_FREQ 165000000U

HCLK frequency to set FLASH latency 2 in power scale 2

Definition at line 74 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE2_LATENCY3_FREQ 220000000U

HCLK frequency to set FLASH latency 3 in power scale 2

Definition at line 75 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE3_LATENCY0_FREQ 45000000U

HCLK frequency to set FLASH latency 0 in power scale 3

Definition at line 77 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE3_LATENCY1_FREQ 90000000U

HCLK frequency to set FLASH latency 1 in power scale 3

Definition at line 78 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE3_LATENCY2_FREQ 135000000U

HCLK frequency to set FLASH latency 2 in power scale 3

Definition at line 79 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE3_LATENCY3_FREQ 180000000U

HCLK frequency to set FLASH latency 3 in power scale 3

Definition at line 80 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

#define UTILS_SCALE3_LATENCY4_FREQ 225000000U

HCLK frequency to set FLASH latency 4 in power scale 3

Definition at line 81 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_CalculateFlashLatency().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_AHB_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_APB3_DIV(__VALUE__)
#define | IS_LL_UTILS_APB4_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
#define | IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
#define | IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__)
#define | IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__)
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_AHB_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_AHB_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_AHB_DIV_512))

Definition at line 100 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 110 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 116 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB3_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB3_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB3_DIV_16))

Definition at line 122 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB4_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB4_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB4_DIV_16))

Definition at line 128 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_CHECK_VCO_RANGES | ( | __RANGEIN__,
 |  | __RANGEOUT__
 | ) |
Value:
( \
(((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
(((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))

Definition at line 152 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define IS_LL_UTILS_FRACN_VALUE ( __VALUE__ ) ((__VALUE__) <= 0x1FFFU)

Definition at line 140 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 160 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 163 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ )
Value:
((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))

Definition at line 156 of file stm32h7xx_ll_utils.c.

#define IS_LL_UTILS_PLLM_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))

Definition at line 134 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLN_VALUE ( __VALUE__ ) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))

Definition at line 136 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLP_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))

Definition at line 138 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_INPUT | ( | __VALUE__,
 |  | __RANGE__
 | ) |
Value:
( \
(((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
(((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
(((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
(((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))

Definition at line 142 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define IS_LL_UTILS_PLLVCO_OUTPUT | ( | __VALUE__,
 |  | __RANGE__
 | ) |
Value:
( \
(((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
(((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))

Definition at line 148 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 90 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32h7xx_ll_utils.h>

Data Fields

uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | FRACN
uint32_t | VCO_Input
uint32_t | VCO_Output

Detailed Description

UTILS PLL structure definition.

Definition at line 97 of file stm32h7xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::FRACN

Fractional part of the multiplication factor for PLL VCO. This parameter can be a value between 0 and 8191

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetFRACN().

Definition at line 118 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLM

Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetM().

Definition at line 99 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLN

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetN().

Definition at line 105 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLP

Division for the main system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetP().

Definition at line 111 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::VCO_Input

Fractional part of the multiplication factor for PLL VCO. This parameter can be a value of All PLLs input range

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetVCOInputRange().

Definition at line 124 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

uint32_t LL_UTILS_PLLInitTypeDef::VCO_Output

Fractional part of the multiplication factor for PLL VCO. This parameter can be a value of All PLLs VCO range

This feature can be modified afterwards using unitary function LL_RCC_PLL1_SetVCOOutputRange().

Definition at line 130 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_utils.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32h7xx_ll_utils.h>

Data Fields

uint32_t | SYSCLKDivider
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider
uint32_t | APB3CLKDivider
uint32_t | APB4CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 141 of file stm32h7xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 149 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 155 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 161 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB3CLKDivider

The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB3)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB3Prescaler().

Definition at line 167 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB4CLKDivider

The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB4)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB4Prescaler().

Definition at line 173 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::SYSCLKDivider

The System clock (SYSCLK) divider. This clock is derived from the PLL output. This parameter can be a value of System prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetSysPrescaler().

Definition at line 143 of file stm32h7xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_ll_utils.h
Generated on Tue Nov 12 2019 18:50:42 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 193 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 194 of file stm32h7xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PACKAGE TYPE

Defines
PACKAGE TYPE
UTILS Exported Constants

Defines

#define | LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL
#define | LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL
#define | LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL
#define | LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL
#define | LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL
#define | LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL
#define | LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL
#define | LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL
#define | LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL
#define | LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL
#define | LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL
#define | LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL
#define | LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL

Define Documentation

#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL

LQFP100 with SMPS package type

Definition at line 210 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL

LQFP144 package type

Definition at line 213 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL

LQFP144 with SMPS package type

Definition at line 214 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL

LQFP176 with SMPS package type

Definition at line 217 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL

LQFP64 package type

Definition at line 208 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL

TFBGA100 or LQFP100 package type

Definition at line 209 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL

TFBGA100 with SMPS package type

Definition at line 211 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL

TFBGA216 package type

Definition at line 219 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL

TFBGA225 package type

Definition at line 220 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL

UFBGA169 package type

Definition at line 215 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL

UFBGA176 or LQFP176 package type

Definition at line 216 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL

UFBGA176 with SMPS package type

Definition at line 218 of file stm32h7xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL

WLCSP132 package type

Definition at line 212 of file stm32h7xx_ll_utils.h.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 274 of file stm32h7xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetPackageType ( void )

Get Package type.

Return values:
Returned value can be one of the following values:
  • LL_UTILS_PACKAGETYPE_LQFP100
  • LL_UTILS_PACKAGETYPE_TQFP144
  • LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
  • LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
  • LL_UTILS_PACKAGETYPE_LQFP64 (*)
  • LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*)
  • LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*)
  • LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*)
  • LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*)
  • LL_UTILS_PACKAGETYPE_LQFP144 (*)
  • LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
  • LL_UTILS_PACKAGETYPE_UFBGA169 (*)
  • LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*)
  • LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*)
  • LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*)
  • LL_UTILS_PACKAGETYPE_TFBGA216 (*)
  • LL_UTILS_PACKAGETYPE_TFBGA225 (*)
(*) Packages available on some STM32H7 lines only.
Note:
For some SM32H7 lines, enabling the SYSCFG clock is mandatory. the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock

Definition at line 304 of file stm32h7xx_ll_utils.h.

References PACKAGE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0]

Definition at line 245 of file stm32h7xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32]

Definition at line 254 of file stm32h7xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64]

Definition at line 263 of file stm32h7xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t CPU_Frequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t CPU_Frequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
CPU_Frequency Core frequency in Hz
Note:
CPU_Frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 211 of file stm32h7xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 331 of file stm32h7xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 228 of file stm32h7xx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t CPU_Frequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
  • PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLP: ensure that max frequency at 400000000 Hz is reached (PLLVCO_output / PLLP)
Parameters:
HSEFrequency | Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 424 of file stm32h7xx_ll_utils.c.

References assert_param, LL_UTILS_PLLInitTypeDef::FRACN, IS_LL_UTILS_CHECK_VCO_RANGES, IS_LL_UTILS_FRACN_VALUE, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLP_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_RCC_CalcPLLClockFreq(), LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL1_SetFRACN(), LL_RCC_PLL1_SetM(), LL_RCC_PLL1_SetN(), LL_RCC_PLL1_SetP(), LL_RCC_PLL1_SetVCOInputRange(), LL_RCC_PLL1_SetVCOOutputRange(), LL_RCC_PLL1FRACN_Enable(), LL_RCC_PLL1P_Enable(), LL_RCC_PLL_SetSource(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_IsPLLsReady(), LL_UTILS_PLLInitTypeDef::VCO_Input, and LL_UTILS_PLLInitTypeDef::VCO_Output.

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
  • PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLP: ensure that max frequency at 400000000 Hz is reach (PLLVCO_output / PLLP)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 333 of file stm32h7xx_ll_utils.c.

References assert_param, LL_UTILS_PLLInitTypeDef::FRACN, HSI_VALUE, IS_LL_UTILS_CHECK_VCO_RANGES, IS_LL_UTILS_FRACN_VALUE, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLP_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_RCC_CalcPLLClockFreq(), LL_RCC_HSI_Enable(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PLL1_SetFRACN(), LL_RCC_PLL1_SetM(), LL_RCC_PLL1_SetN(), LL_RCC_PLL1_SetP(), LL_RCC_PLL1_SetVCOInputRange(), LL_RCC_PLL1_SetVCOOutputRange(), LL_RCC_PLL1FRACN_Enable(), LL_RCC_PLL1P_Enable(), LL_RCC_PLL_SetSource(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_IsPLLsReady(), LL_UTILS_PLLInitTypeDef::VCO_Input, and LL_UTILS_PLLInitTypeDef::VCO_Output.

void LL_SetSystemCoreClock ( uint32_t CPU_Frequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
CPU_Frequency Core frequency in Hz
Note:
CPU_Frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 311 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 55 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 63 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/128

Definition at line 70 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 67 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 64 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 68 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 65 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 69 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 66 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 101 of file stm32h7xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 93 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 128 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 166 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128

Definition at line 207 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 239 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 139 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 155 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128
Return values:
None

Definition at line 188 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 228 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 271 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 260 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 291 of file stm32h7xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 302 of file stm32h7xx_ll_wwdg.h.

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STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __OSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __PSSI_HandleTypeDef , __USART_HandleTypeDef , __MMC_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AbortReceiveCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AbortTransmitCpltCallback : __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AccessTime : OSPI_HyperbusCfgTypeDef
  • AccumulatedActiveH : LTDC_InitTypeDef
  • AccumulatedActiveW : LTDC_InitTypeDef
  • AccumulatedHBP : LTDC_InitTypeDef
  • AccumulatedVBP : LTDC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef , GFXMMU_CachePrefetchTypeDef , GFXMMU_InterruptsTypeDef , SAI_PdmInitTypeDef
  • ActiveAsyncPrescaler : RTC_ActiveTampersTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFilter : RTC_ActiveTampersTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • ActiveOutputChangePeriod : RTC_ActiveTampersTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , OSPI_RegularCmdTypeDef , OSPI_HyperbusCmdTypeDef , UART_WakeUpTypeDef
  • AddressDtrMode : OSPI_RegularCmdTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : OSPI_RegularCmdTypeDef
  • AddressSize : OSPI_RegularCmdTypeDef , OSPI_HyperbusCmdTypeDef
  • AddressSpace : OSPI_HyperbusCmdTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • AllocationUnitSize : HAL_SD_CardStatusTypeDef
  • Alpha : LTDC_LayerCfgTypeDef , LL_DMA2D_LayerCfgTypeDef
  • Alpha0 : LTDC_LayerCfgTypeDef
  • AlphaInversionMode : LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • AlphaMode : LL_DMA2D_LayerCfgTypeDef
  • Alternate : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • AlternateBytes : OSPI_RegularCmdTypeDef
  • AlternateBytesDtrMode : OSPI_RegularCmdTypeDef
  • AlternateBytesMode : OSPI_RegularCmdTypeDef
  • AlternateBytesSize : OSPI_RegularCmdTypeDef
  • AnalogFilter : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB3CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB4CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AppWdgEvt : FDCAN_TTOperationStatusTypeDef
  • AppWdgLimit : FDCAN_TT_ConfigTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : OSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AVDLevel : PWREx_AVDTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
  • AwdCallback : __DFSDM_Filter_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • B0 : CRYP_ConfigTypeDef
  • Backcolor : LTDC_InitTypeDef , LTDC_LayerCfgTypeDef
  • BackupSymbolClockGen : SPDIFRX_InitTypeDef
  • Bank : FLASH_CRCInitTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BasicCyclesNbr : FDCAN_TT_ConfigTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRatePrescaler : LL_SWPMI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Bits : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlendingFactor1 : LTDC_LayerCfgTypeDef
  • BlendingFactor2 : LTDC_LayerCfgTypeDef
  • Block : NAND_AddressTypeDef
  • BlockCount : MDMA_LinkNodeConfTypeDef
  • BlockDataLength : MDMA_LinkNodeConfTypeDef , LL_MDMA_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlockRepeatCount : LL_MDMA_InitTypeDef
  • BlockRepeatDestAddrUpdateMode : LL_MDMA_InitTypeDef
  • BlockRepeatDestAddrUpdateVal : LL_MDMA_InitTypeDef
  • BlockRepeatSrcAddrUpdateMode : LL_MDMA_InitTypeDef
  • BlockRepeatSrcAddrUpdateVal : LL_MDMA_InitTypeDef
  • BlockSize : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlocksPerLine : GFXMMU_InitTypeDef
  • Blue : LTDC_ColorTypeDef , LL_DMA2D_LayerCfgTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BootConfig : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • Buf0Address : GFXMMU_BuffersTypeDef
  • Buf1Address : GFXMMU_BuffersTypeDef
  • Buf2Address : GFXMMU_BuffersTypeDef
  • Buf3Address : GFXMMU_BuffersTypeDef
  • BufferableWriteMode : LL_MDMA_InitTypeDef
  • Buffers : GFXMMU_InitTypeDef
  • BufferTransferLength : LL_MDMA_InitTypeDef , MDMA_InitTypeDef
  • BurstSize : FLASH_CRCInitTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
  • BusWidth : PSSI_InitTypeDef
  • ByteEndianess : LL_MDMA_InitTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CacheForce : GFXMMU_CachePrefetchTypeDef
  • CacheLock : GFXMMU_CachePrefetchTypeDef
  • CacheLockBuffer : GFXMMU_CachePrefetchTypeDef
  • CachePrefetch : GFXMMU_InitTypeDef
  • CalFieldLength : FDCAN_ClkCalUnitTypeDef
  • CaptureRate : DCMI_InitTypeDef
  • CardComdClasses : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • CardSpeed : HAL_SD_CardInfoTypeDef
  • CardType : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef , HAL_SD_CardStatusTypeDef
  • CardVersion : HAL_SD_CardInfoTypeDef
  • CBNDTR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CBRUR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CDAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef , __TIM_HandleTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_SetDataFormatTypeDef , SPDIFRX_InitTypeDef
  • ChipSelectBoundary : OSPI_InitTypeDef
  • ChipSelectHighTime : OSPI_InitTypeDef
  • ChromaSubsampling : JPEG_ConfTypeDef
  • ChromaSubSampling : LL_DMA2D_LayerCfgTypeDef
  • CID : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • CID_CRC : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • CkabCallback : __DFSDM_Channel_HandleTypeDef
  • CkperClockSelection : RCC_PeriphCLKInitTypeDef
  • CLAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • Class : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • ClkChipSelectHighTime : OSPI_InitTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • ClkPort : OSPIM_CfgTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockCalibration : FDCAN_TT_ConfigTypeDef , FDCAN_ClkCalUnitTypeDef
  • ClockCalibrationCallback : __FDCAN_HandleTypeDef
  • ClockDivider : FDCAN_ClkCalUnitTypeDef , RNG_ConfigTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : OSPI_InitTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : PSSI_InitTypeDef , TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , OSPI_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockQuality : FDCAN_TTOperationStatusTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : LL_DMA2D_LayerCfgTypeDef
  • CLUTMemoryAddress : LL_DMA2D_LayerCfgTypeDef
  • CLUTSize : LL_DMA2D_LayerCfgTypeDef
  • CMAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CmdCpltCallback : __OSPI_HandleTypeDef
  • CMDR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CodeLength : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • ColorMode : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • ColorSpace : JPEG_ConfTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • Conf : __JPEG_HandleTypeDef
  • Config : __NAND_HandleTypeDef
  • Config1 : RNG_ConfigTypeDef
  • Config2 : RNG_ConfigTypeDef
  • Config3 : RNG_ConfigTypeDef
  • ConnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • ContentProtectAppli : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Context : __MMC_HandleTypeDef , __SD_HandleTypeDef , __JPEG_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ControlSignal : PSSI_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConversionDataManagement : ADC_InitTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • CopyFlag : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CPUCLK_Frequency : LL_RCC_ClocksTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCEndAddr : FLASH_CRCInitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CRCStartAddr : FLASH_CRCInitTypeDef
  • CrypHeaderCount : __CRYP_HandleTypeDef
  • CrypInCount : __CRYP_HandleTypeDef
  • CrypOutCount : __CRYP_HandleTypeDef
  • CSAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CSD : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • CSD_CRC : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • CSDStruct : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • CSICalibrationValue : RCC_OscInitTypeDef
  • CSIState : RCC_OscInitTypeDef
  • CsXferCount : __SPDIFRX_HandleTypeDef
  • CsXferSize : __SPDIFRX_HandleTypeDef
  • CTBR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CTCR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CustomQuanTable : __JPEG_HandleTypeDef
  • CxCpltCallback : __SPDIFRX_HandleTypeDef
  • CxHalfCpltCallback : __SPDIFRX_HandleTypeDef
  • CycleStartSync : FDCAN_TT_ConfigTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • Data24BitAlignment : I2S_InitTypeDef
  • DataAlignment : MDMA_InitTypeDef
  • DataBusWidth : HAL_SD_CardStatusTypeDef
  • DataDtrMode : OSPI_RegularCmdTypeDef
  • DataEnablePolarity : PSSI_InitTypeDef
  • DataFormat : I2S_InitTypeDef , SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataMode : OSPI_RegularCmdTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataReadyCallback : __JPEG_HandleTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataTransferMode : LL_ADC_REG_InitTypeDef
  • DataType : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • DataWidth : PSSI_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • DataWidthUnit : CRYP_ConfigTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DecodeCpltCallback : __JPEG_HandleTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DefaultValue : GFXMMU_InitTypeDef
  • DelayBlockBypass : OSPI_InitTypeDef
  • DelayHoldQuarterCycle : OSPI_InitTypeDef
  • DEPolarity : LTDC_InitTypeDef
  • DestBlockAddressOffset : MDMA_InitTypeDef
  • DestBurst : MDMA_InitTypeDef , LL_MDMA_InitTypeDef
  • DestBus : LL_MDMA_InitTypeDef
  • DestDataSize : MDMA_InitTypeDef , LL_MDMA_InitTypeDef
  • DestinationInc : MDMA_InitTypeDef
  • DestIncMode : LL_MDMA_InitTypeDef
  • DestIncSize : LL_MDMA_InitTypeDef
  • DetectErrorCallback : __RAMECC_HandleTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_MMC_CardCSDTypeDef , OSPI_InitTypeDef , HAL_SD_CardCSDTypeDef
  • DeviceSizeMul : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Dfsdm2ClockSelection : RCC_PeriphCLKInitTypeDef
  • DgstCpltCallback : __HASH_HandleTypeDef
  • DigestCalculationDisable : __HASH_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : DFSDM_Channel_OutputClockTypeDef
  • DMA_Handle : __DCMI_HandleTypeDef , __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DmaMode : DFSDM_Filter_InjectedParamTypeDef , DFSDM_Filter_RegularParamTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DmaXferCpltCallback : __SRAM_HandleTypeDef , __SDRAM_HandleTypeDef
  • DmaXferErrorCallback : __SDRAM_HandleTypeDef , __SRAM_HandleTypeDef
  • DQSMode : OSPI_HyperbusCmdTypeDef , OSPI_RegularCmdTypeDef
  • DQSPort : OSPIM_CfgTypeDef
  • DriveTransceiver_1_8V_Callback : __SD_HandleTypeDef
  • DSRImpl : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • DstAddress : LL_MDMA_InitTypeDef , MDMA_LinkNodeConfTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DualModeData : ADC_MultiModeTypeDef
  • DualQuad : OSPI_InitTypeDef
  • DummyCycles : OSPI_RegularCmdTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ECSPending : FDCAN_TTOperationStatusTypeDef
  • Enable : MPU_Region_InitTypeDef , RTC_ATampInputTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncodeCpltCallback : __JPEG_HandleTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndAddress : FDCAN_MsgRamAddressTypeDef
  • Endianness : MDMA_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • EraseGrMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • EraseGrSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • EraseOffset : HAL_SD_CardStatusTypeDef
  • EraseSize : HAL_SD_CardStatusTypeDef
  • EraseTimeout : HAL_SD_CardStatusTypeDef
  • ErrorCallback : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __JPEG_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPDIFRX_HandleTypeDef , __ADC_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __CEC_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __DCMI_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __FDCAN_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __I2C_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __GFXMMU_HandleTypeDef , __I2S_HandleTypeDef , __FDCAN_HandleTypeDef , __IRDA_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __JPEG_HandleTypeDef , __LTDC_HandleTypeDef , __MDMA_HandleTypeDef , __COMP_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __RAMECC_HandleTypeDef , __RNG_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SAI_HandleTypeDef , __PCD_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __DCMI_HandleTypeDef , __MDIOS_HandleTypeDef , __DMA_HandleTypeDef , FLASH_ProcessTypeDef
  • ErrorLevel : FDCAN_TTOperationStatusTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventTrigSel : FDCAN_TT_ConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EvtTrigPolarity : FDCAN_TT_ConfigTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExpTxTrigNbr : FDCAN_TT_ConfigTypeDef
  • Ext_CSD : __MMC_HandleTypeDef
  • Extended : __SRAM_HandleTypeDef , __NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalClkSync : FDCAN_TT_ConfigTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
  • ExtraCommandEnable : NAND_DeviceConfigTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : __DFSDM_Filter_HandleTypeDef , DFSDM_Filter_InjectedParamTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FastMode : DFSDM_Filter_RegularParamTypeDef
  • FBStartAdress : LTDC_LayerCfgTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • FifoMode : __UART_HandleTypeDef , __USART_HandleTypeDef
  • FIFOMode : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • FifoMode : __SMARTCARD_HandleTypeDef
  • FIFOThreshold : LL_DMA_InitTypeDef
  • FifoThreshold : OSPI_InitTypeDef , SPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef , SAI_InitTypeDef
  • FifoThresholdCallback : __OSPI_HandleTypeDef
  • FileFormat : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • FileFormatGroup : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_TriggerTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterType : FDCAN_FilterTypeDef , FDCAN_TriggerTypeDef
  • FirstBit : I2S_InitTypeDef , SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstLinkedListNodeAddress : __MDMA_HandleTypeDef
  • FirstVisibleBlock : GFXMMU_LutLineTypeDef
  • FlashId : OSPI_RegularCmdTypeDef
  • FmcClockSelection : RCC_PeriphCLKInitTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FRACN : LL_UTILS_PLLInitTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameEventCallback : __DCMI_HandleTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FreeRunningClock : OSPI_InitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GapEnable : FDCAN_TT_ConfigTypeDef
  • GapFinished : FDCAN_TTOperationStatusTypeDef
  • GapStarted : FDCAN_TTOperationStatusTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GetDataCallback : __JPEG_HandleTypeDef
  • GlobalTimeFilter : FDCAN_TT_ConfigTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • Green : LL_DMA2D_LayerCfgTypeDef , LTDC_ColorTypeDef
  • gState : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef
  • GTimeDiscPending : FDCAN_TTOperationStatusTypeDef
  • GTimeQuality : FDCAN_TTOperationStatusTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HalfWordEndianess : LL_MDMA_InitTypeDef
  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • HashBuffSize : __HASH_HandleTypeDef
  • HashInCount : __HASH_HandleTypeDef
  • HashITCounter : __HASH_HandleTypeDef
  • HashKeyCount : __HASH_HandleTypeDef
  • hc : __HCD_HandleTypeDef
  • HC_NotifyURBChangeCallback : __HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmaCsRx : __SPDIFRX_HandleTypeDef
  • hdmaDrRx : __SPDIFRX_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef , __HASH_HandleTypeDef , __JPEG_HandleTypeDef
  • hdmaInj : __DFSDM_Filter_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef , __JPEG_HandleTypeDef
  • hdmaReg : __DFSDM_Filter_HandleTypeDef
  • hdmarx : __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , __SPI_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : DFSDM_Filter_AwdParamTypeDef , ADC_AnalogWDGConfTypeDef
  • hmdma : __SRAM_HandleTypeDef , __OSPI_HandleTypeDef , __SDRAM_HandleTypeDef
  • HorizontalSync : LTDC_InitTypeDef
  • HourFormat : LL_RTC_InitTypeDef , RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
  • HuffmanCode : JPEG_DC_HuffCodeTableTypeDef , JPEG_AC_HuffCodeTableTypeDef
  • HuffVal : JPEG_DCHuffTableTypeDef , JPEG_ACHuffTableTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • HWTrigger : LL_MDMA_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c123ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IFCR : DMA_Base_Registers , BDMA_Base_Registers
  • ImageHeight : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • ImageQuality : JPEG_ConfTypeDef
  • ImageWidth : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef , __HASH_HandleTypeDef
  • InDataLength : __JPEG_HandleTypeDef
  • InfoReadyCallback : __JPEG_HandleTypeDef
  • Init : __DCMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , MDMA_LinkNodeConfTypeDef , __MDMA_HandleTypeDef , __MMC_HandleTypeDef , __NAND_HandleTypeDef , __NOR_HandleTypeDef , __OPAMP_HandleTypeDef , __OSPI_HandleTypeDef , __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SDRAM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , __SRAM_HandleTypeDef , __SWPMI_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef
  • InitRefTrigOffset : FDCAN_TT_ConfigTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvCpltCallback : __DFSDM_Filter_HandleTypeDef
  • InjConvHalfCpltCallback : __DFSDM_Filter_HandleTypeDef
  • InjConvRemaining : __DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : __DFSDM_Filter_HandleTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedLeftBitShift : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetRightShift : ADC_InjectionConfTypeDef
  • InjectedOffsetSignedSaturation : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : __DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : __DFSDM_Filter_HandleTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SDRAM_HandleTypeDef , __GFXMMU_HandleTypeDef , IWDG_HandleTypeDef , __SPI_HandleTypeDef , __MDMA_HandleTypeDef , __IRDA_HandleTypeDef , __DMA_HandleTypeDef , __DCMI_HandleTypeDef , __DAC_HandleTypeDef , __LTDC_HandleTypeDef , __ADC_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __RNG_HandleTypeDef , CRC_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __I2C_HandleTypeDef , __USART_HandleTypeDef , __CRYP_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __HCD_HandleTypeDef , __I2S_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __MDIOS_HandleTypeDef , __MMC_HandleTypeDef , __NOR_HandleTypeDef , __CEC_HandleTypeDef , __PSSI_HandleTypeDef , __COMP_HandleTypeDef , __TIM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SWPMI_HandleTypeDef , __WWDG_HandleTypeDef , __SD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __OSPI_HandleTypeDef , __SAI_HandleTypeDef , __PCD_HandleTypeDef , __OPAMP_HandleTypeDef , __RAMECC_HandleTypeDef , __NAND_HandleTypeDef
  • Instruction : OSPI_RegularCmdTypeDef
  • InstructionDtrMode : OSPI_RegularCmdTypeDef
  • InstructionMode : OSPI_RegularCmdTypeDef
  • InstructionSize : OSPI_RegularCmdTypeDef
  • InternalTamper1EventCallback : __RTC_HandleTypeDef
  • InternalTamper2EventCallback : __RTC_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • InternalTamper8EventCallback : __RTC_HandleTypeDef
  • Interrupt : RTC_ATampInputTypeDef , RTC_TamperTypeDef
  • Interrupts : GFXMMU_InitTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : OSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • InvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • IOHighPort : OSPIM_CfgTypeDef
  • IOLowPort : OSPIM_CfgTypeDef
  • IOSwap : SPI_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsCalibrationMsg : FDCAN_FilterTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • ISR : BDMA_Base_Registers , DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ItCallback : __NAND_HandleTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- j -

  • JpegInCount : __JPEG_HandleTypeDef
  • JPEGMode : DCMI_InitTypeDef
  • JpegOutCount : __JPEG_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KeySize : CRYP_ConfigTypeDef , HASH_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LastLinkedListNodeAddress : __MDMA_HandleTypeDef
  • LastVisibleBlock : GFXMMU_LutLineTypeDef
  • LatencyMode : OSPI_HyperbusCfgTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LayerCfg : __LTDC_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LeftBitShift : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_ConfigTypeDef , EXTI_HandleTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • Line_64_95 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineEventCallback : __DCMI_HandleTypeDef , __LTDC_HandleTypeDef
  • LineNumber : GFXMMU_LutLineTypeDef
  • LineOffset : GFXMMU_LutLineTypeDef , LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • LineOffsetMode : LL_DMA2D_InitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LineStatus : GFXMMU_LutLineTypeDef
  • LinkAddress : LL_MDMA_InitTypeDef
  • LinkedListNodeCounter : __MDMA_HandleTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __NAND_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __LTDC_HandleTypeDef , __LPTIM_HandleTypeDef , __SD_HandleTypeDef , __SDRAM_HandleTypeDef , __I2S_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , FLASH_ProcessTypeDef , __ADC_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef , __DAC_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DCMI_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __SPDIFRX_HandleTypeDef , __OPAMP_HandleTypeDef , __MMC_HandleTypeDef , __MDMA_HandleTypeDef , __IRDA_HandleTypeDef , __JPEG_HandleTypeDef , __TIM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __MDIOS_HandleTypeDef , __NOR_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LogBlockNbr : HAL_SD_CardInfoTypeDef , HAL_MMC_CardInfoTypeDef
  • LogBlockSize : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : DFSDM_Filter_AwdParamTypeDef , ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim345ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ManufactDate : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • Mask : __IRDA_HandleTypeDef , OSPI_AutoPollingTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskAddress : LL_MDMA_InitTypeDef
  • MaskData : LL_MDMA_InitTypeDef
  • MaskFlag : RTC_ATampInputTypeDef , RTC_TamperTypeDef
  • MasterInterDataIdleness : SPI_InitTypeDef
  • MasterKeepIOState : I2S_InitTypeDef , SPI_InitTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterPriority : FDCAN_TTOperationStatusTypeDef
  • MasterReceiverAutoSusp : SPI_InitTypeDef
  • MasterRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterSSIdleness : SPI_InitTypeDef
  • MasterState : FDCAN_TTOperationStatusTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Match : OSPI_AutoPollingTypeDef
  • MatchMode : OSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxRdCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxRdCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxTran : OSPI_InitTypeDef
  • MaxWrBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxWrCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxWrCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • MemBurst : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryAddress : LL_DMA2D_LayerCfgTypeDef
  • MemoryOrM2MDstAddress : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryType : OSPI_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageRAMOffset : FDCAN_InitTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • MinOscClkPeriods : FDCAN_ClkCalUnitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • MmcCard : __MMC_HandleTypeDef
  • Mode : ADC_MultiModeTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef , PWR_PVDTypeDef , PWREx_AVDTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , LL_DMA2D_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __NOR_HandleTypeDef , __OSPI_HandleTypeDef , __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __USART_HandleTypeDef , __RTC_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __MDIOS_HandleTypeDef , __SRAM_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __HASH_HandleTypeDef , __DCMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __COMP_HandleTypeDef , __UART_HandleTypeDef , __SWPMI_HandleTypeDef , __OPAMP_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __RNG_HandleTypeDef , __NAND_HandleTypeDef , __LTDC_HandleTypeDef , __CEC_HandleTypeDef , __SDRAM_HandleTypeDef , __I2C_HandleTypeDef , __GFXMMU_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __FDCAN_HandleTypeDef , __HCD_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __MMC_HandleTypeDef
  • MspInitCallback : __RNG_HandleTypeDef , __JPEG_HandleTypeDef , __CEC_HandleTypeDef , __NOR_HandleTypeDef , __SAI_HandleTypeDef , __OSPI_HandleTypeDef , __DCMI_HandleTypeDef , __MMC_HandleTypeDef , __FDCAN_HandleTypeDef , __SD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __PCD_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __I2C_HandleTypeDef , __COMP_HandleTypeDef , __HASH_HandleTypeDef , __RTC_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef , __SWPMI_HandleTypeDef , __USART_HandleTypeDef , __OPAMP_HandleTypeDef , __SDRAM_HandleTypeDef , __NAND_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __SPDIFRX_HandleTypeDef , __HCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __GFXMMU_HandleTypeDef , __PSSI_HandleTypeDef , __LTDC_HandleTypeDef , __DAC_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __MDIOS_HandleTypeDef , __LPTIM_HandleTypeDef , __WWDG_HandleTypeDef , __SRAM_HandleTypeDef , __CRYP_HandleTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : OSPI_RegularCmdTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , OSPI_HyperbusCmdTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbrOfLines : LL_DMA2D_InitTypeDef
  • NbrOfPixelsPerLines : LL_DMA2D_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbSectors : FLASH_EraseInitTypeDef , FLASH_CRCInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbWordsAlreadyPushed : __HASH_HandleTypeDef
  • NCSPort : OSPIM_CfgTypeDef
  • NistCompliance : RNG_ConfigTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef , RTC_ATampInputTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSAC : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • NSSPolarity : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OEM_AppliID : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetRightShift : ADC_ChannelConfTypeDef
  • OffsetSignedSaturation : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : UART_InitTypeDef , SMARTCARD_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OperationMode : FDCAN_TT_ConfigTypeDef
  • OperationType : OSPI_RegularCmdTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OspiClockSelection : RCC_PeriphCLKInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OTPBlockLock : FLASH_OBProgramInitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutDataLength : __JPEG_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • Output : RTC_ATampInputTypeDef
  • OutputAlpha : LL_DMA2D_InitTypeDef , LL_DMA2D_ColorTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBlue : LL_DMA2D_InitTypeDef , LL_DMA2D_ColorTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputGreen : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef
  • OutputMemoryAddress : LL_DMA2D_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutputRed : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputSwapMode : LL_DMA2D_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutterBufferability : GFXMMU_CachePrefetchTypeDef
  • OutterCachability : GFXMMU_CachePrefetchTypeDef
  • Overrun : LL_ADC_REG_InitTypeDef , ADC_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Oversampling : DFSDM_Filter_FilterParamTypeDef , ADC_InitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef
  • OverSampling : UART_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • PackMode : LL_MDMA_InitTypeDef
  • PaddingAlignment : LL_MDMA_InitTypeDef
  • Page : NAND_AddressTypeDef
  • PageSize : NAND_DeviceConfigTypeDef
  • Parent : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • pBuffPtr : __DCMI_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCLK3_Frequency : LL_RCC_ClocksTypeDef
  • PCLK4_Frequency : LL_RCC_ClocksTypeDef
  • PCPolarity : LTDC_InitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pCsBuffPtr : __SPDIFRX_HandleTypeDef
  • pData : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendClearSource : EXTI_ConfigTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • PerformanceMove : HAL_SD_CardStatusTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphBurst : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphRequest : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PermWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : __CRYP_HandleTypeDef , __HASH_HandleTypeDef
  • PhaseLock : FDCAN_TTOperationStatusTypeDef
  • pHashInBuffPtr : __HASH_HandleTypeDef
  • pHashKeyBuffPtr : __HASH_HandleTypeDef
  • pHashMsgBuffPtr : __HASH_HandleTypeDef
  • pHashOutBuffPtr : __HASH_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • PinPolarity : PWREx_WakeupPinTypeDef
  • PinPull : PWREx_WakeupPinTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • PixelFormat : LTDC_LayerCfgTypeDef
  • pJpegInBuffPtr : __JPEG_HandleTypeDef
  • pJpegOutBuffPtr : __JPEG_HandleTypeDef
  • pKey : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Plane : NAND_AddressTypeDef
  • PlaneNbr : NAND_DeviceConfigTypeDef
  • PlaneSize : NAND_DeviceConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLL1_P_Frequency : PLL1_ClocksTypeDef
  • PLL1_Q_Frequency : PLL1_ClocksTypeDef
  • PLL1_R_Frequency : PLL1_ClocksTypeDef
  • PLL2 : RCC_PeriphCLKInitTypeDef
  • PLL2_P_Frequency : PLL2_ClocksTypeDef
  • PLL2_Q_Frequency : PLL2_ClocksTypeDef
  • PLL2_R_Frequency : PLL2_ClocksTypeDef
  • PLL2FRACN : RCC_PLL2InitTypeDef
  • PLL2M : RCC_PLL2InitTypeDef
  • PLL2N : RCC_PLL2InitTypeDef
  • PLL2P : RCC_PLL2InitTypeDef
  • PLL2Q : RCC_PLL2InitTypeDef
  • PLL2R : RCC_PLL2InitTypeDef
  • PLL2RGE : RCC_PLL2InitTypeDef
  • PLL2VCOSEL : RCC_PLL2InitTypeDef
  • PLL3 : RCC_PeriphCLKInitTypeDef
  • PLL3_P_Frequency : PLL3_ClocksTypeDef
  • PLL3_Q_Frequency : PLL3_ClocksTypeDef
  • PLL3_R_Frequency : PLL3_ClocksTypeDef
  • PLL3FRACN : RCC_PLL3InitTypeDef
  • PLL3M : RCC_PLL3InitTypeDef
  • PLL3N : RCC_PLL3InitTypeDef
  • PLL3P : RCC_PLL3InitTypeDef
  • PLL3Q : RCC_PLL3InitTypeDef
  • PLL3R : RCC_PLL3InitTypeDef
  • PLL3RGE : RCC_PLL3InitTypeDef
  • PLL3VCOSEL : RCC_PLL3InitTypeDef
  • PLL_P_Frequency : LL_PLL_ClocksTypeDef
  • PLL_Q_Frequency : LL_PLL_ClocksTypeDef
  • PLL_R_Frequency : LL_PLL_ClocksTypeDef
  • PLLFRACN : RCC_PLLInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLRGE : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PLLVCOSEL : RCC_PLLInitTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • PortAddress : MDIOS_InitTypeDef
  • PortDisabledCallback : __HCD_HandleTypeDef
  • PortEnabledCallback : __HCD_HandleTypeDef
  • PostRequestMaskAddress : MDMA_LinkNodeConfTypeDef
  • PostRequestMaskData : MDMA_LinkNodeConfTypeDef
  • PowerMode : OPAMP_InitTypeDef , LL_COMP_InitTypeDef , LL_OPAMP_InitTypeDef , IRDA_InitTypeDef
  • PreambleCheck : MDIOS_InitTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prefetch : GFXMMU_CachePrefetchTypeDef
  • Prescaler : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , WWDG_InitTypeDef , LL_TIM_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , TIM_Base_InitTypeDef , LL_LPTIM_InitTypeDef , RCC_CRSInitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • Priority : MDMA_InitTypeDef , DMA_InitTypeDef , LL_DMA_InitTypeDef , LL_MDMA_InitTypeDef , LL_BDMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdName2 : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdRev : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdSN : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProtectedAreaSize : HAL_SD_CardStatusTypeDef
  • Protocol : SAI_InitTypeDef
  • ProtocolException : FDCAN_InitTypeDef , FDCAN_ProtocolStatusTypeDef
  • pRxBuffPtr : __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __MMC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef
  • pTxBuffPtr : __CEC_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- q -

  • QuantTable0 : __JPEG_HandleTypeDef
  • QuantTable1 : __JPEG_HandleTypeDef
  • QuantTable2 : __JPEG_HandleTypeDef
  • QuantTable3 : __JPEG_HandleTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RBSwapMode : LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • RdBlockLen : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • RdBlockMisalign : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Read_DMADblBuf0CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • Read_DMADblBuf1CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • ReadCpltCallback : __MDIOS_HandleTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReadyPolarity : PSSI_InitTypeDef
  • Red : LTDC_ColorTypeDef , LL_DMA2D_LayerCfgTypeDef
  • Refresh : OSPI_InitTypeDef
  • RefreshErrorCallback : __SDRAM_HandleTypeDef
  • RefTrigOffset : FDCAN_TTOperationStatusTypeDef
  • RegConvCpltCallback : __DFSDM_Filter_HandleTypeDef
  • RegConvHalfCpltCallback : __DFSDM_Filter_HandleTypeDef
  • RegularContMode : __DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : __DFSDM_Filter_HandleTypeDef
  • RelCardAdd : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadEventCallback : __LTDC_HandleTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepeatFactor : FDCAN_TriggerTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef , MDMA_InitTypeDef
  • RequestMode : LL_MDMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Reserved : LTDC_ColorTypeDef , MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypeDef , HAL_SD_CardCSDTypeDef , HAL_SD_CardCIDTypeDef
  • Reserved2 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypeDef , HAL_SD_CardCSDTypeDef , HAL_SD_CardCIDTypeDef
  • Reserved3 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Reserved4 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RWRecoveryTime : OSPI_HyperbusCfgTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxBufferIndex : FDCAN_FilterTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • RxBufferNewMessageCallback : __FDCAN_HandleTypeDef
  • RxBufferSA : FDCAN_MsgRamAddressTypeDef
  • RxBufferSize : FDCAN_InitTypeDef
  • RxBuffersNbr : FDCAN_InitTypeDef
  • RxCpltCallback : __SD_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SWPMI_HandleTypeDef
  • RxCRCInitializationPattern : SPI_InitTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFifo0ElmtSize : FDCAN_InitTypeDef
  • RxFifo0ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFifo1ElmtSize : FDCAN_InitTypeDef
  • RxFifo1ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __USART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __UART_HandleTypeDef , __SWPMI_HandleTypeDef , __I2S_HandleTypeDef , __SAI_HandleTypeDef , __OSPI_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef
  • RxISR : __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __IRDA_HandleTypeDef , __CEC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __I2S_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SWPMI_HandleTypeDef
  • RxXferSize : __UART_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __SPI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SWPMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2AClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2BClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : OSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • ScdCallback : __DFSDM_Channel_HandleTypeDef
  • SdCard : __SD_HandleTypeDef
  • SdmmcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef , FLASH_CRCInitTypeDef
  • SecureAreaConfig : FLASH_OBProgramInitTypeDef
  • SecureAreaEndAddr : FLASH_OBProgramInitTypeDef
  • SecureAreaStartAddr : FLASH_OBProgramInitTypeDef
  • SecuredMode : HAL_SD_CardStatusTypeDef
  • Seed : RTC_ActiveTampersTypeDef
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : OSPI_RegularCmdTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • SourceBlockAddressOffset : MDMA_InitTypeDef
  • SourceBurst : MDMA_InitTypeDef
  • SourceDataSize : MDMA_InitTypeDef
  • SourceInc : MDMA_InitTypeDef
  • SpareAreaSize : NAND_DeviceConfigTypeDef
  • SpdifrxClockSelection : RCC_PeriphCLKInitTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • SpeedClass : HAL_SD_CardStatusTypeDef
  • Spi123ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi45ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi6ClockSelection : RCC_PeriphCLKInitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SrcAddress : MDMA_LinkNodeConfTypeDef , LL_MDMA_InitTypeDef
  • SrcBus : LL_MDMA_InitTypeDef
  • SrcDataSize : LL_MDMA_InitTypeDef
  • SrcIncMode : LL_MDMA_InitTypeDef
  • SrcIncSize : LL_MDMA_InitTypeDef
  • SrctBurst : LL_MDMA_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • StartCycle : FDCAN_TriggerTypeDef
  • State : __I2C_HandleTypeDef , __SPI_HandleTypeDef , __DCMI_HandleTypeDef , __HCD_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __SWPMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __USART_HandleTypeDef , __SMBUS_HandleTypeDef , __I2S_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , __MDMA_HandleTypeDef , __SDRAM_HandleTypeDef , __MMC_HandleTypeDef , __RNG_HandleTypeDef , __RAMECC_HandleTypeDef , __RTC_HandleTypeDef , __NOR_HandleTypeDef , __OPAMP_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __NAND_HandleTypeDef , __TIM_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef , __HASH_HandleTypeDef , __OPAMP_HandleTypeDef
  • StatusMatchCallback : __OSPI_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StereoMode : SPDIFRX_SetDataFormatTypeDef , SPDIFRX_InitTypeDef
  • StopBits : USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , LL_USART_InitTypeDef
  • StopWatchTrigSel : FDCAN_TT_ConfigTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • SuspendRequest : __HASH_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SymbolClockGen : SPDIFRX_InitTypeDef
  • SyncDevLimit : FDCAN_TT_ConfigTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SyncState : FDCAN_TTOperationStatusTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TAAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TampInput : RTC_ActiveTampersTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TempWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • TimeMark : FDCAN_TriggerTypeDef
  • TimeMaster : FDCAN_TT_ConfigTypeDef
  • Timeout : __OSPI_HandleTypeDef
  • TimeOutActivation : OSPI_MemoryMappedTypeDef
  • TimeOutCallback : __OSPI_HandleTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutPeriod : OSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeQuantaPerBitTime : FDCAN_ClkCalUnitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef , RTC_ActiveTampersTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : LL_I2C_InitTypeDef , I2C_InitTypeDef , SMBUS_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • TmEventExt : FDCAN_TriggerTypeDef
  • TmEventInt : FDCAN_TriggerTypeDef
  • Tolerance : CEC_InitTypeDef
  • TotalHeigh : LTDC_InitTypeDef
  • TotalWidth : LTDC_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransferTriggerMode : MDMA_InitTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerIndex : FDCAN_TriggerTypeDef
  • TriggerMemoryNbr : FDCAN_TT_ConfigTypeDef
  • TriggerMode : COMP_InitTypeDef , LL_MDMA_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TriggerType : FDCAN_TriggerTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNHighSpeed : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePHighSpeed : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TT_GlobalTimeCallback : __FDCAN_HandleTypeDef
  • TT_ScheduleSyncCallback : __FDCAN_HandleTypeDef
  • TT_StopWatchCallback : __FDCAN_HandleTypeDef
  • TT_TimeMarkCallback : __FDCAN_HandleTypeDef
  • ttcan : __FDCAN_HandleTypeDef
  • TTMemorySA : FDCAN_MsgRamAddressTypeDef
  • TURDenominator : FDCAN_TT_ConfigTypeDef
  • TURNumerator : FDCAN_TT_ConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxBufferIndex : FDCAN_TriggerTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • TxBufferSA : FDCAN_MsgRamAddressTypeDef
  • TxBuffersNbr : FDCAN_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __PSSI_HandleTypeDef , __I2S_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxCRCInitializationPattern : SPI_InitTypeDef
  • TxElmtSize : FDCAN_InitTypeDef
  • TxEnableWindow : FDCAN_TT_ConfigTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxEventsNbr : FDCAN_InitTypeDef
  • TxFifoEmptyCallback : __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueElmtsNbr : FDCAN_InitTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SAI_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __OSPI_HandleTypeDef , __SPI_HandleTypeDef
  • TxISR : __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __UART_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef , __MMC_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeCRC : FLASH_CRCInitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • UhsAllocationUnitSize : HAL_SD_CardStatusTypeDef
  • UhsSpeedGrade : HAL_SD_CardStatusTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart16ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart234578ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • UsedInterrupts : GFXMMU_InterruptsTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VCO_Input : LL_UTILS_PLLInitTypeDef
  • VCO_Output : LL_UTILS_PLLInitTypeDef
  • Version : __CRYP_HandleTypeDef
  • VerticalSync : LTDC_InitTypeDef
  • VideoSpeedClass : HAL_SD_CardStatusTypeDef
  • VoltageClass : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : LTDC_InitTypeDef , DCMI_InitTypeDef
  • VsyncEventCallback : __DCMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WaitForActivity : SPDIFRX_InitTypeDef
  • WaitForEvt : FDCAN_TTOperationStatusTypeDef
  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpCallback : __MDIOS_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpPin : PWREx_WakeupPinTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WatchdogStartValue : FDCAN_ClkCalUnitTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowX0 : LTDC_LayerCfgTypeDef
  • WindowX1 : LTDC_LayerCfgTypeDef
  • WindowY0 : LTDC_LayerCfgTypeDef
  • WindowY1 : LTDC_LayerCfgTypeDef
  • WordEndianess : LL_MDMA_InitTypeDef
  • WordLength : UART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef
  • WrapSize : OSPI_InitTypeDef
  • WrBlockMisalign : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Write_DMADblBuf0CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • Write_DMADblBuf1CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • WriteBlockPaPartial : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • WriteCpltCallback : __MDIOS_HandleTypeDef
  • WriteZeroLatency : OSPI_HyperbusCfgTypeDef
  • WrProtectGrEnable : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • WrProtectGrSize : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • WSInversion : I2S_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferBlockCpltCallback : __MDMA_HandleTypeDef
  • XferBufferCpltCallback : __MDMA_HandleTypeDef
  • XferCount : __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __DCMI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferM1HalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferRepeatBlockCpltCallback : __MDMA_HandleTypeDef
  • XferSize : __SMBUS_HandleTypeDef , __DCMI_HandleTypeDef , __SAI_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef
  • XferTransferNumber : __DCMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __OSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __PSSI_HandleTypeDef , __USART_HandleTypeDef , __MMC_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AbortReceiveCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AbortTransmitCpltCallback : __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AccessTime : OSPI_HyperbusCfgTypeDef
  • AccumulatedActiveH : LTDC_InitTypeDef
  • AccumulatedActiveW : LTDC_InitTypeDef
  • AccumulatedHBP : LTDC_InitTypeDef
  • AccumulatedVBP : LTDC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef , GFXMMU_CachePrefetchTypeDef , GFXMMU_InterruptsTypeDef , SAI_PdmInitTypeDef
  • ActiveAsyncPrescaler : RTC_ActiveTampersTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFilter : RTC_ActiveTampersTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • ActiveOutputChangePeriod : RTC_ActiveTampersTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , OSPI_RegularCmdTypeDef , OSPI_HyperbusCmdTypeDef , UART_WakeUpTypeDef
  • AddressDtrMode : OSPI_RegularCmdTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : OSPI_RegularCmdTypeDef
  • AddressSize : OSPI_RegularCmdTypeDef , OSPI_HyperbusCmdTypeDef
  • AddressSpace : OSPI_HyperbusCmdTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • AllocationUnitSize : HAL_SD_CardStatusTypeDef
  • Alpha : LTDC_LayerCfgTypeDef , LL_DMA2D_LayerCfgTypeDef
  • Alpha0 : LTDC_LayerCfgTypeDef
  • AlphaInversionMode : LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • AlphaMode : LL_DMA2D_LayerCfgTypeDef
  • Alternate : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • AlternateBytes : OSPI_RegularCmdTypeDef
  • AlternateBytesDtrMode : OSPI_RegularCmdTypeDef
  • AlternateBytesMode : OSPI_RegularCmdTypeDef
  • AlternateBytesSize : OSPI_RegularCmdTypeDef
  • AnalogFilter : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB3CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB4CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AppWdgEvt : FDCAN_TTOperationStatusTypeDef
  • AppWdgLimit : FDCAN_TT_ConfigTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : OSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AVDLevel : PWREx_AVDTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
  • AwdCallback : __DFSDM_Filter_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- b -

  • B0 : CRYP_ConfigTypeDef
  • Backcolor : LTDC_InitTypeDef , LTDC_LayerCfgTypeDef
  • BackupSymbolClockGen : SPDIFRX_InitTypeDef
  • Bank : FLASH_CRCInitTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BasicCyclesNbr : FDCAN_TT_ConfigTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRatePrescaler : LL_SWPMI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Bits : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlendingFactor1 : LTDC_LayerCfgTypeDef
  • BlendingFactor2 : LTDC_LayerCfgTypeDef
  • Block : NAND_AddressTypeDef
  • BlockCount : MDMA_LinkNodeConfTypeDef
  • BlockDataLength : MDMA_LinkNodeConfTypeDef , LL_MDMA_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlockRepeatCount : LL_MDMA_InitTypeDef
  • BlockRepeatDestAddrUpdateMode : LL_MDMA_InitTypeDef
  • BlockRepeatDestAddrUpdateVal : LL_MDMA_InitTypeDef
  • BlockRepeatSrcAddrUpdateMode : LL_MDMA_InitTypeDef
  • BlockRepeatSrcAddrUpdateVal : LL_MDMA_InitTypeDef
  • BlockSize : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlocksPerLine : GFXMMU_InitTypeDef
  • Blue : LTDC_ColorTypeDef , LL_DMA2D_LayerCfgTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BootConfig : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • Buf0Address : GFXMMU_BuffersTypeDef
  • Buf1Address : GFXMMU_BuffersTypeDef
  • Buf2Address : GFXMMU_BuffersTypeDef
  • Buf3Address : GFXMMU_BuffersTypeDef
  • BufferableWriteMode : LL_MDMA_InitTypeDef
  • Buffers : GFXMMU_InitTypeDef
  • BufferTransferLength : LL_MDMA_InitTypeDef , MDMA_InitTypeDef
  • BurstSize : FLASH_CRCInitTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
  • BusWidth : PSSI_InitTypeDef
  • ByteEndianess : LL_MDMA_InitTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- c -

  • CacheForce : GFXMMU_CachePrefetchTypeDef
  • CacheLock : GFXMMU_CachePrefetchTypeDef
  • CacheLockBuffer : GFXMMU_CachePrefetchTypeDef
  • CachePrefetch : GFXMMU_InitTypeDef
  • CalFieldLength : FDCAN_ClkCalUnitTypeDef
  • CaptureRate : DCMI_InitTypeDef
  • CardComdClasses : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • CardSpeed : HAL_SD_CardInfoTypeDef
  • CardType : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef , HAL_SD_CardStatusTypeDef
  • CardVersion : HAL_SD_CardInfoTypeDef
  • CBNDTR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CBRUR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CDAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef , __TIM_HandleTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_SetDataFormatTypeDef , SPDIFRX_InitTypeDef
  • ChipSelectBoundary : OSPI_InitTypeDef
  • ChipSelectHighTime : OSPI_InitTypeDef
  • ChromaSubsampling : JPEG_ConfTypeDef
  • ChromaSubSampling : LL_DMA2D_LayerCfgTypeDef
  • CID : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • CID_CRC : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • CkabCallback : __DFSDM_Channel_HandleTypeDef
  • CkperClockSelection : RCC_PeriphCLKInitTypeDef
  • CLAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • Class : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • ClkChipSelectHighTime : OSPI_InitTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • ClkPort : OSPIM_CfgTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockCalibration : FDCAN_TT_ConfigTypeDef , FDCAN_ClkCalUnitTypeDef
  • ClockCalibrationCallback : __FDCAN_HandleTypeDef
  • ClockDivider : FDCAN_ClkCalUnitTypeDef , RNG_ConfigTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : OSPI_InitTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : PSSI_InitTypeDef , TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , OSPI_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockQuality : FDCAN_TTOperationStatusTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : LL_DMA2D_LayerCfgTypeDef
  • CLUTMemoryAddress : LL_DMA2D_LayerCfgTypeDef
  • CLUTSize : LL_DMA2D_LayerCfgTypeDef
  • CMAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CmdCpltCallback : __OSPI_HandleTypeDef
  • CMDR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CodeLength : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • ColorMode : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • ColorSpace : JPEG_ConfTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • Conf : __JPEG_HandleTypeDef
  • Config : __NAND_HandleTypeDef
  • Config1 : RNG_ConfigTypeDef
  • Config2 : RNG_ConfigTypeDef
  • Config3 : RNG_ConfigTypeDef
  • ConnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • ContentProtectAppli : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Context : __MMC_HandleTypeDef , __SD_HandleTypeDef , __JPEG_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ControlSignal : PSSI_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConversionDataManagement : ADC_InitTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • CopyFlag : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CPUCLK_Frequency : LL_RCC_ClocksTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCEndAddr : FLASH_CRCInitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CRCStartAddr : FLASH_CRCInitTypeDef
  • CrypHeaderCount : __CRYP_HandleTypeDef
  • CrypInCount : __CRYP_HandleTypeDef
  • CrypOutCount : __CRYP_HandleTypeDef
  • CSAR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CSD : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • CSD_CRC : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • CSDStruct : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • CSICalibrationValue : RCC_OscInitTypeDef
  • CSIState : RCC_OscInitTypeDef
  • CsXferCount : __SPDIFRX_HandleTypeDef
  • CsXferSize : __SPDIFRX_HandleTypeDef
  • CTBR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CTCR : MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • CustomQuanTable : __JPEG_HandleTypeDef
  • CxCpltCallback : __SPDIFRX_HandleTypeDef
  • CxHalfCpltCallback : __SPDIFRX_HandleTypeDef
  • CycleStartSync : FDCAN_TT_ConfigTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • Data24BitAlignment : I2S_InitTypeDef
  • DataAlignment : MDMA_InitTypeDef
  • DataBusWidth : HAL_SD_CardStatusTypeDef
  • DataDtrMode : OSPI_RegularCmdTypeDef
  • DataEnablePolarity : PSSI_InitTypeDef
  • DataFormat : I2S_InitTypeDef , SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataMode : OSPI_RegularCmdTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataReadyCallback : __JPEG_HandleTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataTransferMode : LL_ADC_REG_InitTypeDef
  • DataType : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • DataWidth : PSSI_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • DataWidthUnit : CRYP_ConfigTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DecodeCpltCallback : __JPEG_HandleTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DefaultValue : GFXMMU_InitTypeDef
  • DelayBlockBypass : OSPI_InitTypeDef
  • DelayHoldQuarterCycle : OSPI_InitTypeDef
  • DEPolarity : LTDC_InitTypeDef
  • DestBlockAddressOffset : MDMA_InitTypeDef
  • DestBurst : MDMA_InitTypeDef , LL_MDMA_InitTypeDef
  • DestBus : LL_MDMA_InitTypeDef
  • DestDataSize : MDMA_InitTypeDef , LL_MDMA_InitTypeDef
  • DestinationInc : MDMA_InitTypeDef
  • DestIncMode : LL_MDMA_InitTypeDef
  • DestIncSize : LL_MDMA_InitTypeDef
  • DetectErrorCallback : __RAMECC_HandleTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_MMC_CardCSDTypeDef , OSPI_InitTypeDef , HAL_SD_CardCSDTypeDef
  • DeviceSizeMul : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Dfsdm2ClockSelection : RCC_PeriphCLKInitTypeDef
  • DgstCpltCallback : __HASH_HandleTypeDef
  • DigestCalculationDisable : __HASH_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : DFSDM_Channel_OutputClockTypeDef
  • DMA_Handle : __DCMI_HandleTypeDef , __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DmaMode : DFSDM_Filter_InjectedParamTypeDef , DFSDM_Filter_RegularParamTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DmaXferCpltCallback : __SRAM_HandleTypeDef , __SDRAM_HandleTypeDef
  • DmaXferErrorCallback : __SDRAM_HandleTypeDef , __SRAM_HandleTypeDef
  • DQSMode : OSPI_HyperbusCmdTypeDef , OSPI_RegularCmdTypeDef
  • DQSPort : OSPIM_CfgTypeDef
  • DriveTransceiver_1_8V_Callback : __SD_HandleTypeDef
  • DSRImpl : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • DstAddress : LL_MDMA_InitTypeDef , MDMA_LinkNodeConfTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DualModeData : ADC_MultiModeTypeDef
  • DualQuad : OSPI_InitTypeDef
  • DummyCycles : OSPI_RegularCmdTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- e -

  • ECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ECSPending : FDCAN_TTOperationStatusTypeDef
  • Enable : MPU_Region_InitTypeDef , RTC_ATampInputTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncodeCpltCallback : __JPEG_HandleTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndAddress : FDCAN_MsgRamAddressTypeDef
  • Endianness : MDMA_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • EraseGrMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • EraseGrSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • EraseOffset : HAL_SD_CardStatusTypeDef
  • EraseSize : HAL_SD_CardStatusTypeDef
  • EraseTimeout : HAL_SD_CardStatusTypeDef
  • ErrorCallback : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __JPEG_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPDIFRX_HandleTypeDef , __ADC_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __CEC_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __DCMI_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __FDCAN_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __I2C_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __GFXMMU_HandleTypeDef , __I2S_HandleTypeDef , __FDCAN_HandleTypeDef , __IRDA_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __JPEG_HandleTypeDef , __LTDC_HandleTypeDef , __MDMA_HandleTypeDef , __COMP_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __RAMECC_HandleTypeDef , __RNG_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SAI_HandleTypeDef , __PCD_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __DCMI_HandleTypeDef , __MDIOS_HandleTypeDef , __DMA_HandleTypeDef , FLASH_ProcessTypeDef
  • ErrorLevel : FDCAN_TTOperationStatusTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventTrigSel : FDCAN_TT_ConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EvtTrigPolarity : FDCAN_TT_ConfigTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExpTxTrigNbr : FDCAN_TT_ConfigTypeDef
  • Ext_CSD : __MMC_HandleTypeDef
  • Extended : __SRAM_HandleTypeDef , __NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalClkSync : FDCAN_TT_ConfigTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
  • ExtraCommandEnable : NAND_DeviceConfigTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : __DFSDM_Filter_HandleTypeDef , DFSDM_Filter_InjectedParamTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- f -

  • FastMode : DFSDM_Filter_RegularParamTypeDef
  • FBStartAdress : LTDC_LayerCfgTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • FifoMode : __UART_HandleTypeDef , __USART_HandleTypeDef
  • FIFOMode : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • FifoMode : __SMARTCARD_HandleTypeDef
  • FIFOThreshold : LL_DMA_InitTypeDef
  • FifoThreshold : OSPI_InitTypeDef , SPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef , SAI_InitTypeDef
  • FifoThresholdCallback : __OSPI_HandleTypeDef
  • FileFormat : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • FileFormatGroup : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_TriggerTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterType : FDCAN_FilterTypeDef , FDCAN_TriggerTypeDef
  • FirstBit : I2S_InitTypeDef , SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstLinkedListNodeAddress : __MDMA_HandleTypeDef
  • FirstVisibleBlock : GFXMMU_LutLineTypeDef
  • FlashId : OSPI_RegularCmdTypeDef
  • FmcClockSelection : RCC_PeriphCLKInitTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FRACN : LL_UTILS_PLLInitTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameEventCallback : __DCMI_HandleTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FreeRunningClock : OSPI_InitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
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- g -

  • GapEnable : FDCAN_TT_ConfigTypeDef
  • GapFinished : FDCAN_TTOperationStatusTypeDef
  • GapStarted : FDCAN_TTOperationStatusTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GetDataCallback : __JPEG_HandleTypeDef
  • GlobalTimeFilter : FDCAN_TT_ConfigTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • Green : LL_DMA2D_LayerCfgTypeDef , LTDC_ColorTypeDef
  • gState : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef
  • GTimeDiscPending : FDCAN_TTOperationStatusTypeDef
  • GTimeQuality : FDCAN_TTOperationStatusTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- h -

  • HalfWordEndianess : LL_MDMA_InitTypeDef
  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • HashBuffSize : __HASH_HandleTypeDef
  • HashInCount : __HASH_HandleTypeDef
  • HashITCounter : __HASH_HandleTypeDef
  • HashKeyCount : __HASH_HandleTypeDef
  • hc : __HCD_HandleTypeDef
  • HC_NotifyURBChangeCallback : __HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmaCsRx : __SPDIFRX_HandleTypeDef
  • hdmaDrRx : __SPDIFRX_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef , __HASH_HandleTypeDef , __JPEG_HandleTypeDef
  • hdmaInj : __DFSDM_Filter_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef , __JPEG_HandleTypeDef
  • hdmaReg : __DFSDM_Filter_HandleTypeDef
  • hdmarx : __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , __SPI_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : DFSDM_Filter_AwdParamTypeDef , ADC_AnalogWDGConfTypeDef
  • hmdma : __SRAM_HandleTypeDef , __OSPI_HandleTypeDef , __SDRAM_HandleTypeDef
  • HorizontalSync : LTDC_InitTypeDef
  • HourFormat : LL_RTC_InitTypeDef , RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
  • HuffmanCode : JPEG_DC_HuffCodeTableTypeDef , JPEG_AC_HuffCodeTableTypeDef
  • HuffVal : JPEG_DCHuffTableTypeDef , JPEG_ACHuffTableTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • HWTrigger : LL_MDMA_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • I2c123ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IFCR : DMA_Base_Registers , BDMA_Base_Registers
  • ImageHeight : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • ImageQuality : JPEG_ConfTypeDef
  • ImageWidth : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef , __HASH_HandleTypeDef
  • InDataLength : __JPEG_HandleTypeDef
  • InfoReadyCallback : __JPEG_HandleTypeDef
  • Init : __DCMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , MDMA_LinkNodeConfTypeDef , __MDMA_HandleTypeDef , __MMC_HandleTypeDef , __NAND_HandleTypeDef , __NOR_HandleTypeDef , __OPAMP_HandleTypeDef , __OSPI_HandleTypeDef , __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SDRAM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , __SRAM_HandleTypeDef , __SWPMI_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef
  • InitRefTrigOffset : FDCAN_TT_ConfigTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvCpltCallback : __DFSDM_Filter_HandleTypeDef
  • InjConvHalfCpltCallback : __DFSDM_Filter_HandleTypeDef
  • InjConvRemaining : __DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : __DFSDM_Filter_HandleTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedLeftBitShift : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetRightShift : ADC_InjectionConfTypeDef
  • InjectedOffsetSignedSaturation : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : __DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : __DFSDM_Filter_HandleTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SDRAM_HandleTypeDef , __GFXMMU_HandleTypeDef , IWDG_HandleTypeDef , __SPI_HandleTypeDef , __MDMA_HandleTypeDef , __IRDA_HandleTypeDef , __DMA_HandleTypeDef , __DCMI_HandleTypeDef , __DAC_HandleTypeDef , __LTDC_HandleTypeDef , __ADC_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __RNG_HandleTypeDef , CRC_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __I2C_HandleTypeDef , __USART_HandleTypeDef , __CRYP_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __HCD_HandleTypeDef , __I2S_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __MDIOS_HandleTypeDef , __MMC_HandleTypeDef , __NOR_HandleTypeDef , __CEC_HandleTypeDef , __PSSI_HandleTypeDef , __COMP_HandleTypeDef , __TIM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SWPMI_HandleTypeDef , __WWDG_HandleTypeDef , __SD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __OSPI_HandleTypeDef , __SAI_HandleTypeDef , __PCD_HandleTypeDef , __OPAMP_HandleTypeDef , __RAMECC_HandleTypeDef , __NAND_HandleTypeDef
  • Instruction : OSPI_RegularCmdTypeDef
  • InstructionDtrMode : OSPI_RegularCmdTypeDef
  • InstructionMode : OSPI_RegularCmdTypeDef
  • InstructionSize : OSPI_RegularCmdTypeDef
  • InternalTamper1EventCallback : __RTC_HandleTypeDef
  • InternalTamper2EventCallback : __RTC_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • InternalTamper8EventCallback : __RTC_HandleTypeDef
  • Interrupt : RTC_ATampInputTypeDef , RTC_TamperTypeDef
  • Interrupts : GFXMMU_InitTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : OSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • InvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • IOHighPort : OSPIM_CfgTypeDef
  • IOLowPort : OSPIM_CfgTypeDef
  • IOSwap : SPI_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsCalibrationMsg : FDCAN_FilterTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • ISR : BDMA_Base_Registers , DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ItCallback : __NAND_HandleTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- j -

  • JpegInCount : __JPEG_HandleTypeDef
  • JPEGMode : DCMI_InitTypeDef
  • JpegOutCount : __JPEG_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- k -

  • KeySize : CRYP_ConfigTypeDef , HASH_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LastLinkedListNodeAddress : __MDMA_HandleTypeDef
  • LastVisibleBlock : GFXMMU_LutLineTypeDef
  • LatencyMode : OSPI_HyperbusCfgTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LayerCfg : __LTDC_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LeftBitShift : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_ConfigTypeDef , EXTI_HandleTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • Line_64_95 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineEventCallback : __DCMI_HandleTypeDef , __LTDC_HandleTypeDef
  • LineNumber : GFXMMU_LutLineTypeDef
  • LineOffset : GFXMMU_LutLineTypeDef , LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • LineOffsetMode : LL_DMA2D_InitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LineStatus : GFXMMU_LutLineTypeDef
  • LinkAddress : LL_MDMA_InitTypeDef
  • LinkedListNodeCounter : __MDMA_HandleTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __NAND_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __LTDC_HandleTypeDef , __LPTIM_HandleTypeDef , __SD_HandleTypeDef , __SDRAM_HandleTypeDef , __I2S_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , FLASH_ProcessTypeDef , __ADC_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef , __DAC_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DCMI_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __HASH_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __SPDIFRX_HandleTypeDef , __OPAMP_HandleTypeDef , __MMC_HandleTypeDef , __MDMA_HandleTypeDef , __IRDA_HandleTypeDef , __JPEG_HandleTypeDef , __TIM_HandleTypeDef , __SMARTCARD_HandleTypeDef , __MDIOS_HandleTypeDef , __NOR_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LogBlockNbr : HAL_SD_CardInfoTypeDef , HAL_MMC_CardInfoTypeDef
  • LogBlockSize : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : DFSDM_Filter_AwdParamTypeDef , ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim345ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ManufactDate : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • Mask : __IRDA_HandleTypeDef , OSPI_AutoPollingTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskAddress : LL_MDMA_InitTypeDef
  • MaskData : LL_MDMA_InitTypeDef
  • MaskFlag : RTC_ATampInputTypeDef , RTC_TamperTypeDef
  • MasterInterDataIdleness : SPI_InitTypeDef
  • MasterKeepIOState : I2S_InitTypeDef , SPI_InitTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterPriority : FDCAN_TTOperationStatusTypeDef
  • MasterReceiverAutoSusp : SPI_InitTypeDef
  • MasterRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterSSIdleness : SPI_InitTypeDef
  • MasterState : FDCAN_TTOperationStatusTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Match : OSPI_AutoPollingTypeDef
  • MatchMode : OSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxRdCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxRdCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxTran : OSPI_InitTypeDef
  • MaxWrBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxWrCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • MaxWrCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • MemBurst : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryAddress : LL_DMA2D_LayerCfgTypeDef
  • MemoryOrM2MDstAddress : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • MemoryType : OSPI_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageRAMOffset : FDCAN_InitTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • MinOscClkPeriods : FDCAN_ClkCalUnitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • MmcCard : __MMC_HandleTypeDef
  • Mode : ADC_MultiModeTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef , PWR_PVDTypeDef , PWREx_AVDTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , LL_DMA2D_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __NOR_HandleTypeDef , __OSPI_HandleTypeDef , __PCD_HandleTypeDef , __PSSI_HandleTypeDef , __USART_HandleTypeDef , __RTC_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __MDIOS_HandleTypeDef , __SRAM_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __HASH_HandleTypeDef , __DCMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __COMP_HandleTypeDef , __UART_HandleTypeDef , __SWPMI_HandleTypeDef , __OPAMP_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __RNG_HandleTypeDef , __NAND_HandleTypeDef , __LTDC_HandleTypeDef , __CEC_HandleTypeDef , __SDRAM_HandleTypeDef , __I2C_HandleTypeDef , __GFXMMU_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __FDCAN_HandleTypeDef , __HCD_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __MMC_HandleTypeDef
  • MspInitCallback : __RNG_HandleTypeDef , __JPEG_HandleTypeDef , __CEC_HandleTypeDef , __NOR_HandleTypeDef , __SAI_HandleTypeDef , __OSPI_HandleTypeDef , __DCMI_HandleTypeDef , __MMC_HandleTypeDef , __FDCAN_HandleTypeDef , __SD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __PCD_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __I2C_HandleTypeDef , __COMP_HandleTypeDef , __HASH_HandleTypeDef , __RTC_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef , __SWPMI_HandleTypeDef , __USART_HandleTypeDef , __OPAMP_HandleTypeDef , __SDRAM_HandleTypeDef , __NAND_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __SPDIFRX_HandleTypeDef , __HCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __GFXMMU_HandleTypeDef , __PSSI_HandleTypeDef , __LTDC_HandleTypeDef , __DAC_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __MDIOS_HandleTypeDef , __LPTIM_HandleTypeDef , __WWDG_HandleTypeDef , __SRAM_HandleTypeDef , __CRYP_HandleTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : OSPI_RegularCmdTypeDef , LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef , OSPI_HyperbusCmdTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbrOfLines : LL_DMA2D_InitTypeDef
  • NbrOfPixelsPerLines : LL_DMA2D_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbSectors : FLASH_EraseInitTypeDef , FLASH_CRCInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbWordsAlreadyPushed : __HASH_HandleTypeDef
  • NCSPort : OSPIM_CfgTypeDef
  • NistCompliance : RNG_ConfigTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef , RTC_ATampInputTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSAC : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • NSSPolarity : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OEM_AppliID : HAL_MMC_CardCIDTypeDef , HAL_SD_CardCIDTypeDef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetRightShift : ADC_ChannelConfTypeDef
  • OffsetSignedSaturation : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : UART_InitTypeDef , SMARTCARD_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OperationMode : FDCAN_TT_ConfigTypeDef
  • OperationType : OSPI_RegularCmdTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OspiClockSelection : RCC_PeriphCLKInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OTPBlockLock : FLASH_OBProgramInitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutDataLength : __JPEG_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • Output : RTC_ATampInputTypeDef
  • OutputAlpha : LL_DMA2D_InitTypeDef , LL_DMA2D_ColorTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBlue : LL_DMA2D_InitTypeDef , LL_DMA2D_ColorTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputGreen : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef
  • OutputMemoryAddress : LL_DMA2D_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutputRed : LL_DMA2D_ColorTypeDef , LL_DMA2D_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputSwapMode : LL_DMA2D_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutterBufferability : GFXMMU_CachePrefetchTypeDef
  • OutterCachability : GFXMMU_CachePrefetchTypeDef
  • Overrun : LL_ADC_REG_InitTypeDef , ADC_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Oversampling : DFSDM_Filter_FilterParamTypeDef , ADC_InitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef
  • OverSampling : UART_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • Variables
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- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • PackMode : LL_MDMA_InitTypeDef
  • PaddingAlignment : LL_MDMA_InitTypeDef
  • Page : NAND_AddressTypeDef
  • PageSize : NAND_DeviceConfigTypeDef
  • Parent : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • pBuffPtr : __DCMI_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCLK3_Frequency : LL_RCC_ClocksTypeDef
  • PCLK4_Frequency : LL_RCC_ClocksTypeDef
  • PCPolarity : LTDC_InitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pCsBuffPtr : __SPDIFRX_HandleTypeDef
  • pData : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendClearSource : EXTI_ConfigTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • PerformanceMove : HAL_SD_CardStatusTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphBurst : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PeriphRequest : LL_BDMA_InitTypeDef , LL_DMA_InitTypeDef
  • PermWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : __CRYP_HandleTypeDef , __HASH_HandleTypeDef
  • PhaseLock : FDCAN_TTOperationStatusTypeDef
  • pHashInBuffPtr : __HASH_HandleTypeDef
  • pHashKeyBuffPtr : __HASH_HandleTypeDef
  • pHashMsgBuffPtr : __HASH_HandleTypeDef
  • pHashOutBuffPtr : __HASH_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • PinPolarity : PWREx_WakeupPinTypeDef
  • PinPull : PWREx_WakeupPinTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • PixelFormat : LTDC_LayerCfgTypeDef
  • pJpegInBuffPtr : __JPEG_HandleTypeDef
  • pJpegOutBuffPtr : __JPEG_HandleTypeDef
  • pKey : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Plane : NAND_AddressTypeDef
  • PlaneNbr : NAND_DeviceConfigTypeDef
  • PlaneSize : NAND_DeviceConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLL1_P_Frequency : PLL1_ClocksTypeDef
  • PLL1_Q_Frequency : PLL1_ClocksTypeDef
  • PLL1_R_Frequency : PLL1_ClocksTypeDef
  • PLL2 : RCC_PeriphCLKInitTypeDef
  • PLL2_P_Frequency : PLL2_ClocksTypeDef
  • PLL2_Q_Frequency : PLL2_ClocksTypeDef
  • PLL2_R_Frequency : PLL2_ClocksTypeDef
  • PLL2FRACN : RCC_PLL2InitTypeDef
  • PLL2M : RCC_PLL2InitTypeDef
  • PLL2N : RCC_PLL2InitTypeDef
  • PLL2P : RCC_PLL2InitTypeDef
  • PLL2Q : RCC_PLL2InitTypeDef
  • PLL2R : RCC_PLL2InitTypeDef
  • PLL2RGE : RCC_PLL2InitTypeDef
  • PLL2VCOSEL : RCC_PLL2InitTypeDef
  • PLL3 : RCC_PeriphCLKInitTypeDef
  • PLL3_P_Frequency : PLL3_ClocksTypeDef
  • PLL3_Q_Frequency : PLL3_ClocksTypeDef
  • PLL3_R_Frequency : PLL3_ClocksTypeDef
  • PLL3FRACN : RCC_PLL3InitTypeDef
  • PLL3M : RCC_PLL3InitTypeDef
  • PLL3N : RCC_PLL3InitTypeDef
  • PLL3P : RCC_PLL3InitTypeDef
  • PLL3Q : RCC_PLL3InitTypeDef
  • PLL3R : RCC_PLL3InitTypeDef
  • PLL3RGE : RCC_PLL3InitTypeDef
  • PLL3VCOSEL : RCC_PLL3InitTypeDef
  • PLL_P_Frequency : LL_PLL_ClocksTypeDef
  • PLL_Q_Frequency : LL_PLL_ClocksTypeDef
  • PLL_R_Frequency : LL_PLL_ClocksTypeDef
  • PLLFRACN : RCC_PLLInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLRGE : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PLLVCOSEL : RCC_PLLInitTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • PortAddress : MDIOS_InitTypeDef
  • PortDisabledCallback : __HCD_HandleTypeDef
  • PortEnabledCallback : __HCD_HandleTypeDef
  • PostRequestMaskAddress : MDMA_LinkNodeConfTypeDef
  • PostRequestMaskData : MDMA_LinkNodeConfTypeDef
  • PowerMode : OPAMP_InitTypeDef , LL_COMP_InitTypeDef , LL_OPAMP_InitTypeDef , IRDA_InitTypeDef
  • PreambleCheck : MDIOS_InitTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prefetch : GFXMMU_CachePrefetchTypeDef
  • Prescaler : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , WWDG_InitTypeDef , LL_TIM_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , TIM_Base_InitTypeDef , LL_LPTIM_InitTypeDef , RCC_CRSInitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • Priority : MDMA_InitTypeDef , DMA_InitTypeDef , LL_DMA_InitTypeDef , LL_MDMA_InitTypeDef , LL_BDMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdName2 : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdRev : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProdSN : HAL_SD_CardCIDTypeDef , HAL_MMC_CardCIDTypeDef
  • ProtectedAreaSize : HAL_SD_CardStatusTypeDef
  • Protocol : SAI_InitTypeDef
  • ProtocolException : FDCAN_InitTypeDef , FDCAN_ProtocolStatusTypeDef
  • pRxBuffPtr : __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __MMC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef
  • pTxBuffPtr : __CEC_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- q -

  • QuantTable0 : __JPEG_HandleTypeDef
  • QuantTable1 : __JPEG_HandleTypeDef
  • QuantTable2 : __JPEG_HandleTypeDef
  • QuantTable3 : __JPEG_HandleTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- r -

  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RBSwapMode : LL_DMA2D_InitTypeDef , LL_DMA2D_LayerCfgTypeDef
  • RdBlockLen : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • RdBlockMisalign : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Read_DMADblBuf0CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • Read_DMADblBuf1CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • ReadCpltCallback : __MDIOS_HandleTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReadyPolarity : PSSI_InitTypeDef
  • Red : LTDC_ColorTypeDef , LL_DMA2D_LayerCfgTypeDef
  • Refresh : OSPI_InitTypeDef
  • RefreshErrorCallback : __SDRAM_HandleTypeDef
  • RefTrigOffset : FDCAN_TTOperationStatusTypeDef
  • RegConvCpltCallback : __DFSDM_Filter_HandleTypeDef
  • RegConvHalfCpltCallback : __DFSDM_Filter_HandleTypeDef
  • RegularContMode : __DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : __DFSDM_Filter_HandleTypeDef
  • RelCardAdd : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadEventCallback : __LTDC_HandleTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepeatFactor : FDCAN_TriggerTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef , MDMA_InitTypeDef
  • RequestMode : LL_MDMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Reserved : LTDC_ColorTypeDef , MDMA_LinkNodeTypeDef , LL_MDMA_LinkNodeTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypeDef , HAL_SD_CardCSDTypeDef , HAL_SD_CardCIDTypeDef
  • Reserved2 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypeDef , HAL_SD_CardCSDTypeDef , HAL_SD_CardCIDTypeDef
  • Reserved3 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Reserved4 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RWRecoveryTime : OSPI_HyperbusCfgTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxBufferIndex : FDCAN_FilterTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • RxBufferNewMessageCallback : __FDCAN_HandleTypeDef
  • RxBufferSA : FDCAN_MsgRamAddressTypeDef
  • RxBufferSize : FDCAN_InitTypeDef
  • RxBuffersNbr : FDCAN_InitTypeDef
  • RxCpltCallback : __SD_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SWPMI_HandleTypeDef
  • RxCRCInitializationPattern : SPI_InitTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFifo0ElmtSize : FDCAN_InitTypeDef
  • RxFifo0ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFifo1ElmtSize : FDCAN_InitTypeDef
  • RxFifo1ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __USART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __UART_HandleTypeDef , __SWPMI_HandleTypeDef , __I2S_HandleTypeDef , __SAI_HandleTypeDef , __OSPI_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef
  • RxISR : __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __IRDA_HandleTypeDef , __CEC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __I2S_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SWPMI_HandleTypeDef
  • RxXferSize : __UART_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __SPI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __SPDIFRX_HandleTypeDef , __SWPMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2AClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2BClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : OSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • ScdCallback : __DFSDM_Channel_HandleTypeDef
  • SdCard : __SD_HandleTypeDef
  • SdmmcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef , FLASH_CRCInitTypeDef
  • SecureAreaConfig : FLASH_OBProgramInitTypeDef
  • SecureAreaEndAddr : FLASH_OBProgramInitTypeDef
  • SecureAreaStartAddr : FLASH_OBProgramInitTypeDef
  • SecuredMode : HAL_SD_CardStatusTypeDef
  • Seed : RTC_ActiveTampersTypeDef
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : OSPI_RegularCmdTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • SourceBlockAddressOffset : MDMA_InitTypeDef
  • SourceBurst : MDMA_InitTypeDef
  • SourceDataSize : MDMA_InitTypeDef
  • SourceInc : MDMA_InitTypeDef
  • SpareAreaSize : NAND_DeviceConfigTypeDef
  • SpdifrxClockSelection : RCC_PeriphCLKInitTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • SpeedClass : HAL_SD_CardStatusTypeDef
  • Spi123ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi45ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi6ClockSelection : RCC_PeriphCLKInitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SrcAddress : MDMA_LinkNodeConfTypeDef , LL_MDMA_InitTypeDef
  • SrcBus : LL_MDMA_InitTypeDef
  • SrcDataSize : LL_MDMA_InitTypeDef
  • SrcIncMode : LL_MDMA_InitTypeDef
  • SrcIncSize : LL_MDMA_InitTypeDef
  • SrctBurst : LL_MDMA_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • StartCycle : FDCAN_TriggerTypeDef
  • State : __I2C_HandleTypeDef , __SPI_HandleTypeDef , __DCMI_HandleTypeDef , __HCD_HandleTypeDef , __FDCAN_HandleTypeDef , __SRAM_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __SWPMI_HandleTypeDef , __DFSDM_Channel_HandleTypeDef , __DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __GFXMMU_HandleTypeDef , __HASH_HandleTypeDef , __USART_HandleTypeDef , __SMBUS_HandleTypeDef , __I2S_HandleTypeDef , __JPEG_HandleTypeDef , __LPTIM_HandleTypeDef , __LTDC_HandleTypeDef , __MDIOS_HandleTypeDef , __MDMA_HandleTypeDef , __SDRAM_HandleTypeDef , __MMC_HandleTypeDef , __RNG_HandleTypeDef , __RAMECC_HandleTypeDef , __RTC_HandleTypeDef , __NOR_HandleTypeDef , __OPAMP_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SPDIFRX_HandleTypeDef , __NAND_HandleTypeDef , __TIM_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef , __HASH_HandleTypeDef , __OPAMP_HandleTypeDef
  • StatusMatchCallback : __OSPI_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StereoMode : SPDIFRX_SetDataFormatTypeDef , SPDIFRX_InitTypeDef
  • StopBits : USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , LL_USART_InitTypeDef
  • StopWatchTrigSel : FDCAN_TT_ConfigTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • SuspendRequest : __HASH_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SymbolClockGen : SPDIFRX_InitTypeDef
  • SyncDevLimit : FDCAN_TT_ConfigTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SyncState : FDCAN_TTOperationStatusTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
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STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • TAAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TampInput : RTC_ActiveTampersTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TempWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • TimeMark : FDCAN_TriggerTypeDef
  • TimeMaster : FDCAN_TT_ConfigTypeDef
  • Timeout : __OSPI_HandleTypeDef
  • TimeOutActivation : OSPI_MemoryMappedTypeDef
  • TimeOutCallback : __OSPI_HandleTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutPeriod : OSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeQuantaPerBitTime : FDCAN_ClkCalUnitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef , RTC_ActiveTampersTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : LL_I2C_InitTypeDef , I2C_InitTypeDef , SMBUS_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • TmEventExt : FDCAN_TriggerTypeDef
  • TmEventInt : FDCAN_TriggerTypeDef
  • Tolerance : CEC_InitTypeDef
  • TotalHeigh : LTDC_InitTypeDef
  • TotalWidth : LTDC_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransferTriggerMode : MDMA_InitTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerIndex : FDCAN_TriggerTypeDef
  • TriggerMemoryNbr : FDCAN_TT_ConfigTypeDef
  • TriggerMode : COMP_InitTypeDef , LL_MDMA_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TriggerType : FDCAN_TriggerTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNHighSpeed : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePHighSpeed : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TT_GlobalTimeCallback : __FDCAN_HandleTypeDef
  • TT_ScheduleSyncCallback : __FDCAN_HandleTypeDef
  • TT_StopWatchCallback : __FDCAN_HandleTypeDef
  • TT_TimeMarkCallback : __FDCAN_HandleTypeDef
  • ttcan : __FDCAN_HandleTypeDef
  • TTMemorySA : FDCAN_MsgRamAddressTypeDef
  • TURDenominator : FDCAN_TT_ConfigTypeDef
  • TURNumerator : FDCAN_TT_ConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxBufferIndex : FDCAN_TriggerTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • TxBufferSA : FDCAN_MsgRamAddressTypeDef
  • TxBuffersNbr : FDCAN_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __PSSI_HandleTypeDef , __I2S_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __MMC_HandleTypeDef , __OSPI_HandleTypeDef , __SAI_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxCRCInitializationPattern : SPI_InitTypeDef
  • TxElmtSize : FDCAN_InitTypeDef
  • TxEnableWindow : FDCAN_TT_ConfigTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxEventsNbr : FDCAN_InitTypeDef
  • TxFifoEmptyCallback : __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueElmtsNbr : FDCAN_InitTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SWPMI_HandleTypeDef , __UART_HandleTypeDef , __SAI_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __OSPI_HandleTypeDef , __SPI_HandleTypeDef
  • TxISR : __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __UART_HandleTypeDef , __SPI_HandleTypeDef , __SWPMI_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SWPMI_HandleTypeDef , __MMC_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeCRC : FLASH_CRCInitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • UhsAllocationUnitSize : HAL_SD_CardStatusTypeDef
  • UhsSpeedGrade : HAL_SD_CardStatusTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart16ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart234578ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • UsedInterrupts : GFXMMU_InterruptsTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VCO_Input : LL_UTILS_PLLInitTypeDef
  • VCO_Output : LL_UTILS_PLLInitTypeDef
  • Version : __CRYP_HandleTypeDef
  • VerticalSync : LTDC_InitTypeDef
  • VideoSpeedClass : HAL_SD_CardStatusTypeDef
  • VoltageClass : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : LTDC_InitTypeDef , DCMI_InitTypeDef
  • VsyncEventCallback : __DCMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • WaitForActivity : SPDIFRX_InitTypeDef
  • WaitForEvt : FDCAN_TTOperationStatusTypeDef
  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpCallback : __MDIOS_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpPin : PWREx_WakeupPinTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WatchdogStartValue : FDCAN_ClkCalUnitTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowX0 : LTDC_LayerCfgTypeDef
  • WindowX1 : LTDC_LayerCfgTypeDef
  • WindowY0 : LTDC_LayerCfgTypeDef
  • WindowY1 : LTDC_LayerCfgTypeDef
  • WordEndianess : LL_MDMA_InitTypeDef
  • WordLength : UART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef
  • WrapSize : OSPI_InitTypeDef
  • WrBlockMisalign : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • Write_DMADblBuf0CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • Write_DMADblBuf1CpltCallback : __MMC_HandleTypeDef , __SD_HandleTypeDef
  • WriteBlockPaPartial : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • WriteCpltCallback : __MDIOS_HandleTypeDef
  • WriteZeroLatency : OSPI_HyperbusCfgTypeDef
  • WrProtectGrEnable : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypeDef
  • WrProtectGrSize : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CardCSDTypeDef , HAL_MMC_CardCSDTypeDef
  • WSInversion : I2S_InitTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • XferAbortCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferBlockCpltCallback : __MDMA_HandleTypeDef
  • XferBufferCpltCallback : __MDMA_HandleTypeDef
  • XferCount : __PSSI_HandleTypeDef , __SAI_HandleTypeDef , __DCMI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferM1HalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferRepeatBlockCpltCallback : __MDMA_HandleTypeDef
  • XferSize : __SMBUS_HandleTypeDef , __DCMI_HandleTypeDef , __SAI_HandleTypeDef , __I2C_HandleTypeDef , __OSPI_HandleTypeDef , __PSSI_HandleTypeDef
  • XferTransferNumber : __DCMI_HandleTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Fields - Variables

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  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32h7xx_hal_conf.h File Reference
#include "stm32h7xx_hal_rcc.h"
#include "stm32h7xx_hal_gpio.h"
#include "stm32h7xx_hal_dma.h"
#include "stm32h7xx_hal_mdma.h"
#include "stm32h7xx_hal_hash.h"
#include "stm32h7xx_hal_dcmi.h"
#include "stm32h7xx_hal_dma2d.h"
#include "stm32h7xx_hal_dsi.h"
#include "stm32h7xx_hal_dfsdm.h"
#include "stm32h7xx_hal_dts.h"
#include "stm32h7xx_hal_eth.h"
#include "stm32h7xx_hal_exti.h"
#include "stm32h7xx_hal_cortex.h"
#include "stm32h7xx_hal_adc.h"
#include "stm32h7xx_hal_fdcan.h"
#include "stm32h7xx_hal_cec.h"
#include "stm32h7xx_hal_comp.h"
#include "stm32h7xx_hal_crc.h"
#include "stm32h7xx_hal_cryp.h"
#include "stm32h7xx_hal_dac.h"
#include "stm32h7xx_hal_flash.h"
#include "stm32h7xx_hal_gfxmmu.h"
#include "stm32h7xx_hal_hrtim.h"
#include "stm32h7xx_hal_hsem.h"
#include "stm32h7xx_hal_sram.h"
#include "stm32h7xx_hal_nor.h"
#include "stm32h7xx_hal_nand.h"
#include "stm32h7xx_hal_i2c.h"
#include "stm32h7xx_hal_i2s.h"
#include "stm32h7xx_hal_iwdg.h"
#include "stm32h7xx_hal_jpeg.h"
#include "stm32h7xx_hal_mdios.h"
#include "stm32h7xx_hal_mmc.h"
#include "stm32h7xx_hal_lptim.h"
#include "stm32h7xx_hal_ltdc.h"
#include "stm32h7xx_hal_opamp.h"
#include "stm32h7xx_hal_ospi.h"
#include "stm32h7xx_hal_otfdec.h"
#include "stm32h7xx_hal_pssi.h"
#include "stm32h7xx_hal_pwr.h"
#include "stm32h7xx_hal_qspi.h"
#include "stm32h7xx_hal_ramecc.h"
#include "stm32h7xx_hal_rng.h"
#include "stm32h7xx_hal_rtc.h"
#include "stm32h7xx_hal_sai.h"
#include "stm32h7xx_hal_sd.h"
#include "stm32h7xx_hal_sdram.h"
#include "stm32h7xx_hal_spi.h"
#include "stm32h7xx_hal_spdifrx.h"
#include "stm32h7xx_hal_swpmi.h"
#include "stm32h7xx_hal_tim.h"
#include "stm32h7xx_hal_uart.h"
#include "stm32h7xx_hal_usart.h"
#include "stm32h7xx_hal_irda.h"
#include "stm32h7xx_hal_smartcard.h"
#include "stm32h7xx_hal_smbus.h"
#include "stm32h7xx_hal_wwdg.h"
#include "stm32h7xx_hal_pcd.h"
#include "stm32h7xx_hal_hcd.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DCMI_MODULE_ENABLED
#define | HAL_DFSDM_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_DMA2D_MODULE_ENABLED
#define | HAL_DTS_MODULE_ENABLED
#define | HAL_DSI_MODULE_ENABLED
#define | HAL_ETH_MODULE_ENABLED
#define | HAL_EXTI_MODULE_ENABLED
#define | HAL_FDCAN_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_GFXMMU_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HASH_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_HRTIM_MODULE_ENABLED
#define | HAL_HSEM_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_JPEG_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_LTDC_MODULE_ENABLED
#define | HAL_MDIOS_MODULE_ENABLED
#define | HAL_MDMA_MODULE_ENABLED
#define | HAL_MMC_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_OPAMP_MODULE_ENABLED
#define | HAL_OSPI_MODULE_ENABLED
#define | HAL_OTFDEC_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_PSSI_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RAMECC_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SDRAM_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPDIFRX_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_SWPMI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HSE_VALUE ((uint32_t)25000000)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT ((uint32_t)5000)
#define | CSI_VALUE ((uint32_t)4000000)
Internal oscillator (CSI) default value.
#define | HSI_VALUE ((uint32_t)64000000)
Internal High Speed oscillator (HSI) value.
#define | LSE_VALUE ((uint32_t)32768)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT ((uint32_t)5000)
#define | LSI_VALUE ((uint32_t)32000)
#define | EXTERNAL_CLOCK_VALUE 12288000U
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE ((uint32_t)3300)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)0x0F)
#define | USE_RTOS 0
#define | USE_SD_TRANSCEIVER 1U
#define | USE_SPI_CRC 1U
#define | USE_HAL_ADC_REGISTER_CALLBACKS 1U /* ADC register callback disabled */
#define | USE_HAL_CEC_REGISTER_CALLBACKS 1U /* CEC register callback disabled */
#define | USE_HAL_COMP_REGISTER_CALLBACKS 1U /* COMP register callback disabled */
#define | USE_HAL_CRYP_REGISTER_CALLBACKS 1U /* CRYP register callback disabled */
#define | USE_HAL_DAC_REGISTER_CALLBACKS 1U /* DAC register callback disabled */
#define | USE_HAL_DCMI_REGISTER_CALLBACKS 1U /* DCMI register callback disabled */
#define | USE_HAL_DFSDM_REGISTER_CALLBACKS 1U /* DFSDM register callback disabled */
#define | USE_HAL_DMA2D_REGISTER_CALLBACKS 1U /* DMA2D register callback disabled */
#define | USE_HAL_DSI_REGISTER_CALLBACKS 1U /* DSI register callback disabled */
#define | USE_HAL_DTS_REGISTER_CALLBACKS 1U /* DTS register callback disabled */
#define | USE_HAL_ETH_REGISTER_CALLBACKS 1U /* ETH register callback disabled */
#define | USE_HAL_FDCAN_REGISTER_CALLBACKS 1U /* FDCAN register callback disabled */
#define | USE_HAL_NAND_REGISTER_CALLBACKS 1U /* NAND register callback disabled */
#define | USE_HAL_NOR_REGISTER_CALLBACKS 1U /* NOR register callback disabled */
#define | USE_HAL_SDRAM_REGISTER_CALLBACKS 1U /* SDRAM register callback disabled */
#define | USE_HAL_SRAM_REGISTER_CALLBACKS 1U /* SRAM register callback disabled */
#define | USE_HAL_HASH_REGISTER_CALLBACKS 1U /* HASH register callback disabled */
#define | USE_HAL_HCD_REGISTER_CALLBACKS 1U /* HCD register callback disabled */
#define | USE_HAL_GFXMMU_REGISTER_CALLBACKS 1U /* GFXMMU register callback disabled */
#define | USE_HAL_HRTIM_REGISTER_CALLBACKS 1U /* HRTIM register callback disabled */
#define | USE_HAL_I2C_REGISTER_CALLBACKS 1U /* I2C register callback disabled */
#define | USE_HAL_I2S_REGISTER_CALLBACKS 1U /* I2S register callback disabled */
#define | USE_HAL_IRDA_REGISTER_CALLBACKS 1U /* IRDA register callback disabled */
#define | USE_HAL_JPEG_REGISTER_CALLBACKS 1U /* JPEG register callback disabled */
#define | USE_HAL_LPTIM_REGISTER_CALLBACKS 1U /* LPTIM register callback disabled */
#define | USE_HAL_LTDC_REGISTER_CALLBACKS 1U /* LTDC register callback disabled */
#define | USE_HAL_MDIOS_REGISTER_CALLBACKS 1U /* MDIO register callback disabled */
#define | USE_HAL_MMC_REGISTER_CALLBACKS 1U /* MMC register callback disabled */
#define | USE_HAL_OPAMP_REGISTER_CALLBACKS 1U /* MDIO register callback disabled */
#define | USE_HAL_OSPI_REGISTER_CALLBACKS 1U /* OSPI register callback disabled */
#define | USE_HAL_OTFDEC_REGISTER_CALLBACKS 1U /* OTFDEC register callback disabled */
#define | USE_HAL_PCD_REGISTER_CALLBACKS 1U /* PCD register callback disabled */
#define | USE_HAL_QSPI_REGISTER_CALLBACKS 1U /* QSPI register callback disabled */
#define | USE_HAL_RNG_REGISTER_CALLBACKS 1U /* RNG register callback disabled */
#define | USE_HAL_RTC_REGISTER_CALLBACKS 1U /* RTC register callback disabled */
#define | USE_HAL_SAI_REGISTER_CALLBACKS 1U /* SAI register callback disabled */
#define | USE_HAL_SD_REGISTER_CALLBACKS 1U /* SD register callback disabled */
#define | USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U /* SMARTCARD register callback disabled */
#define | USE_HAL_SPDIFRX_REGISTER_CALLBACKS 1U /* SPDIFRX register callback disabled */
#define | USE_HAL_SMBUS_REGISTER_CALLBACKS 1U /* SMBUS register callback disabled */
#define | USE_HAL_SPI_REGISTER_CALLBACKS 1U /* SPI register callback disabled */
#define | USE_HAL_SWPMI_REGISTER_CALLBACKS 1U /* SWPMI register callback disabled */
#define | USE_HAL_TIM_REGISTER_CALLBACKS 1U /* TIM register callback disabled */
#define | USE_HAL_UART_REGISTER_CALLBACKS 1U /* UART register callback disabled */
#define | USE_HAL_USART_REGISTER_CALLBACKS 1U /* USART register callback disabled */
#define | USE_HAL_WWDG_REGISTER_CALLBACKS 1U /* WWDG register callback disabled */
#define | ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define | ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
#define | ETH_MAC_ADDR0 ((uint8_t)0x02)
#define | ETH_MAC_ADDR1 ((uint8_t)0x00)
#define | ETH_MAC_ADDR2 ((uint8_t)0x00)
#define | ETH_MAC_ADDR3 ((uint8_t)0x00)
#define | ETH_MAC_ADDR4 ((uint8_t)0x00)
#define | ETH_MAC_ADDR5 ((uint8_t)0x00)
#define | assert_param(expr) ((void)0U)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Include module's header file

Definition at line 491 of file stm32h7xx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_CRC_AddSector(), FLASH_CRC_SelectAddress(), FLASH_CRC_WaitForLastOperation(), FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_OTP_LockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), FLASH_WaitForLastOperation(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), HAL_DACEx_TriangleWaveGenerate(), HAL_DCMI_ConfigCrop(), HAL_DCMI_Init(), HAL_DCMI_Start_DMA(), HAL_DFDSMEx_ChannelSetPulsesSkipping(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), HAL_DFSDM_ChannelScdStop_IT(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_Init(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Start(), HAL_DMA2D_Start_IT(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_DTS_DeInit(), HAL_DTS_Init(), HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_D1_ClearFlag(), HAL_EXTI_D1_EventInputConfig(), HAL_EXTI_D3_EventInputConfig(), HAL_EXTI_EdgeConfig(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GenerateSWInterrupt(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_SetConfigLine(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_GetClockCalibrationCounter(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), HAL_FDCAN_TT_SetNextIsGap(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_ComputeCRC(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_GFXMMU_ConfigForceCache(), HAL_GFXMMU_ConfigLut(), HAL_GFXMMU_ConfigLutLine(), HAL_GFXMMU_DeInit(), HAL_GFXMMU_DisableLutLines(), HAL_GFXMMU_Init(), HAL_GFXMMU_ModifyBuffers(), HAL_GFXMMU_ModifyCachePrefetch(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_HASH_Init(), HAL_HCD_Init(), HAL_HSEM_FastTake(), HAL_HSEM_Release(), HAL_HSEM_ReleaseAll(), HAL_HSEM_SetClearKey(), HAL_HSEM_Take(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_Init(), HAL_LTDC_ProgramLineEvent(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_DeInit(), HAL_MDIOS_Init(), HAL_MDIOS_ReadReg(), HAL_MDIOS_WriteReg(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MMC_ConfigSpeedBusOperation(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Init(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_OPAMPEx_Unlock(), HAL_OSPI_AutoPolling(), HAL_OSPI_AutoPolling_IT(), HAL_OSPI_Command(), HAL_OSPI_Command_IT(), HAL_OSPI_HyperbusCfg(), HAL_OSPI_HyperbusCmd(), HAL_OSPI_Init(), HAL_OSPI_MemoryMapped(), HAL_OSPIM_Config(), HAL_OTFDEC_DeInit(), HAL_OTFDEC_Init(), HAL_OTFDEC_RegionConfig(), HAL_OTFDEC_RegionDisable(), HAL_OTFDEC_RegionEnable(), HAL_OTFDEC_RegionGetConfig(), HAL_OTFDEC_RegionGetKeyCRC(), HAL_OTFDEC_RegionKeyLock(), HAL_OTFDEC_RegionSetKey(), HAL_OTFDEC_RegionSetMode(), HAL_PCD_Init(), HAL_PSSI_DeInit(), HAL_PSSI_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ClearWakeupFlag(), HAL_PWREx_ConfigAVD(), HAL_PWREx_ConfigD3Domain(), HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlStopModeVoltageScaling(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableMemoryShutOff(), HAL_PWREx_DisableWakeUpPin(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableMemoryShutOff(), HAL_PWREx_EnableWakeUpPin(), HAL_PWREx_EnterSTANDBYMode(), HAL_PWREx_EnterSTOP2Mode(), HAL_PWREx_EnterSTOPMode(), HAL_PWREx_GetWakeupFlag(), HAL_RAMECC_DeInit(), HAL_RAMECC_DisableNotification(), HAL_RAMECC_EnableNotification(), HAL_RAMECC_GetFailingAddress(), HAL_RAMECC_GetFailingDataHigh(), HAL_RAMECC_GetFailingDataLow(), HAL_RAMECC_GetHammingErrorCode(), HAL_RAMECC_Init(), HAL_RAMECC_IsECCDoubleErrorDetected(), HAL_RAMECC_IsECCSingleErrorDetected(), HAL_RAMECC_RegisterCallback(), HAL_RAMECC_StartMonitor(), HAL_RAMECC_StopMonitor(), HAL_RAMECC_UnRegisterCallback(), HAL_RCC_ClockConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSConfig(), HAL_RCCEx_CRSGetSynchronizationInfo(), HAL_RCCEx_KerWakeUpStopCLKConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RCCEx_WakeUpStopCLKConfig(), HAL_RNG_Init(), HAL_RNGEx_SetConfig(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_SetActiveTampers(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SAIEx_ConfigPdmMicDelay(), HAL_SD_ConfigSpeedBusOperation(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Init(), HAL_SetFMCMemorySwappingConfig(), HAL_SetTickFreq(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_SetDataFormat(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SYSCFG_AnalogSwitchConfig(), HAL_SYSCFG_CompensationCodeConfig(), HAL_SYSCFG_CompensationCodeSelect(), HAL_SYSCFG_VDDMMC_CompensationCodeConfig(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_ReceiverTimeout_Config(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), HAL_WWDG_Init(), HASH_Accumulate(), HASH_Start_DMA(), HMAC_Start_DMA(), I2C_TransferConfig(), IRDA_SetConfig(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define CSI_VALUE ((uint32_t)4000000)

Internal oscillator (CSI) default value.

This value is the default CSI value after Reset. Value of the Internal oscillator in Hz

Definition at line 117 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), IRDA_SetConfig(), LL_RCC_GetCECClockFreq(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetSystemClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define ETH_MAC_ADDR0 ((uint8_t)0x02)

Definition at line 221 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR1 ((uint8_t)0x00)

Definition at line 222 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR2 ((uint8_t)0x00)

Definition at line 223 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR3 ((uint8_t)0x00)

Definition at line 224 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR4 ((uint8_t)0x00)

Definition at line 225 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR5 ((uint8_t)0x00)

Definition at line 226 of file stm32h7xx_hal_conf.h.

#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */

Definition at line 219 of file stm32h7xx_hal_conf.h.

#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */

Definition at line 218 of file stm32h7xx_hal_conf.h.

#define EXTERNAL_CLOCK_VALUE 12288000U

External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. Value of the External clock in Hz

Definition at line 154 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetSPIClockFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 38 of file stm32h7xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 39 of file stm32h7xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 40 of file stm32h7xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 41 of file stm32h7xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 42 of file stm32h7xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 43 of file stm32h7xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 44 of file stm32h7xx_hal_conf.h.

#define HAL_DCMI_MODULE_ENABLED

Definition at line 45 of file stm32h7xx_hal_conf.h.

#define HAL_DFSDM_MODULE_ENABLED

Definition at line 46 of file stm32h7xx_hal_conf.h.

#define HAL_DMA2D_MODULE_ENABLED

Definition at line 48 of file stm32h7xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 47 of file stm32h7xx_hal_conf.h.

#define HAL_DSI_MODULE_ENABLED

Definition at line 50 of file stm32h7xx_hal_conf.h.

#define HAL_DTS_MODULE_ENABLED

Definition at line 49 of file stm32h7xx_hal_conf.h.

#define HAL_ETH_MODULE_ENABLED

Definition at line 51 of file stm32h7xx_hal_conf.h.

#define HAL_EXTI_MODULE_ENABLED

Definition at line 52 of file stm32h7xx_hal_conf.h.

#define HAL_FDCAN_MODULE_ENABLED

Definition at line 53 of file stm32h7xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 54 of file stm32h7xx_hal_conf.h.

#define HAL_GFXMMU_MODULE_ENABLED

Definition at line 55 of file stm32h7xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 56 of file stm32h7xx_hal_conf.h.

#define HAL_HASH_MODULE_ENABLED

Definition at line 57 of file stm32h7xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 58 of file stm32h7xx_hal_conf.h.

#define HAL_HRTIM_MODULE_ENABLED

Definition at line 59 of file stm32h7xx_hal_conf.h.

#define HAL_HSEM_MODULE_ENABLED

Definition at line 60 of file stm32h7xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 61 of file stm32h7xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 62 of file stm32h7xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 63 of file stm32h7xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 64 of file stm32h7xx_hal_conf.h.

#define HAL_JPEG_MODULE_ENABLED

Definition at line 65 of file stm32h7xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 66 of file stm32h7xx_hal_conf.h.

#define HAL_LTDC_MODULE_ENABLED

Definition at line 67 of file stm32h7xx_hal_conf.h.

#define HAL_MDIOS_MODULE_ENABLED

Definition at line 68 of file stm32h7xx_hal_conf.h.

#define HAL_MDMA_MODULE_ENABLED

Definition at line 69 of file stm32h7xx_hal_conf.h.

#define HAL_MMC_MODULE_ENABLED

Definition at line 70 of file stm32h7xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 37 of file stm32h7xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 71 of file stm32h7xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 72 of file stm32h7xx_hal_conf.h.

#define HAL_OPAMP_MODULE_ENABLED

Definition at line 73 of file stm32h7xx_hal_conf.h.

#define HAL_OSPI_MODULE_ENABLED

Definition at line 74 of file stm32h7xx_hal_conf.h.

#define HAL_OTFDEC_MODULE_ENABLED

Definition at line 75 of file stm32h7xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 76 of file stm32h7xx_hal_conf.h.

#define HAL_PSSI_MODULE_ENABLED

Definition at line 78 of file stm32h7xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 77 of file stm32h7xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 79 of file stm32h7xx_hal_conf.h.

#define HAL_RAMECC_MODULE_ENABLED

Definition at line 80 of file stm32h7xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 81 of file stm32h7xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 82 of file stm32h7xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 83 of file stm32h7xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 84 of file stm32h7xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 85 of file stm32h7xx_hal_conf.h.

#define HAL_SDRAM_MODULE_ENABLED

Definition at line 86 of file stm32h7xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 87 of file stm32h7xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 88 of file stm32h7xx_hal_conf.h.

#define HAL_SPDIFRX_MODULE_ENABLED

Definition at line 89 of file stm32h7xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 90 of file stm32h7xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 91 of file stm32h7xx_hal_conf.h.

#define HAL_SWPMI_MODULE_ENABLED

Definition at line 92 of file stm32h7xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 93 of file stm32h7xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 94 of file stm32h7xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 95 of file stm32h7xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 96 of file stm32h7xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT ((uint32_t)5000)

Time out for HSE start up, in ms

Definition at line 109 of file stm32h7xx_hal_conf.h.

#define HSE_VALUE ((uint32_t)25000000)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 105 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPIClockFreq(), and RCC_GetSystemClockFreq().

#define HSI_VALUE ((uint32_t)64000000)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 126 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_DeInit(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetCLKPClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetPLL1ClockFreq(), LL_RCC_GetPLL2ClockFreq(), LL_RCC_GetPLL3ClockFreq(), LL_RCC_GetSPDIFClockFreq(), LL_RCC_GetSPIClockFreq(), LL_RCC_GetSWPClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetSystemClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSE_STARTUP_TIMEOUT ((uint32_t)5000)

Time out for LSE start up, in ms

Definition at line 139 of file stm32h7xx_hal_conf.h.

#define LSE_VALUE ((uint32_t)32768)

External Low Speed oscillator (LSE) value.

This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 134 of file stm32h7xx_hal_conf.h.

Referenced by HAL_DTS_GetTemperature(), IRDA_SetConfig(), LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE ((uint32_t)32000)

LSI Typical Value in Hz

Definition at line 143 of file stm32h7xx_hal_conf.h.

Referenced by LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), and LL_RCC_GetRNGClockFreq().

#define TICK_INT_PRIORITY ((uint32_t)0x0F)

tick interrupt priority

Definition at line 165 of file stm32h7xx_hal_conf.h.

Referenced by HAL_Init().

#define USE_HAL_ADC_REGISTER_CALLBACKS 1U /* ADC register callback disabled */

Definition at line 170 of file stm32h7xx_hal_conf.h.

#define USE_HAL_CEC_REGISTER_CALLBACKS 1U /* CEC register callback disabled */

Definition at line 171 of file stm32h7xx_hal_conf.h.

#define USE_HAL_COMP_REGISTER_CALLBACKS 1U /* COMP register callback disabled */

Definition at line 172 of file stm32h7xx_hal_conf.h.

#define USE_HAL_CRYP_REGISTER_CALLBACKS 1U /* CRYP register callback disabled */

Definition at line 173 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DAC_REGISTER_CALLBACKS 1U /* DAC register callback disabled */

Definition at line 174 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DCMI_REGISTER_CALLBACKS 1U /* DCMI register callback disabled */

Definition at line 175 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DFSDM_REGISTER_CALLBACKS 1U /* DFSDM register callback disabled */

Definition at line 176 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DMA2D_REGISTER_CALLBACKS 1U /* DMA2D register callback disabled */

Definition at line 177 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DSI_REGISTER_CALLBACKS 1U /* DSI register callback disabled */

Definition at line 178 of file stm32h7xx_hal_conf.h.

#define USE_HAL_DTS_REGISTER_CALLBACKS 1U /* DTS register callback disabled */

Definition at line 179 of file stm32h7xx_hal_conf.h.

#define USE_HAL_ETH_REGISTER_CALLBACKS 1U /* ETH register callback disabled */

Definition at line 180 of file stm32h7xx_hal_conf.h.

#define USE_HAL_FDCAN_REGISTER_CALLBACKS 1U /* FDCAN register callback disabled */

Definition at line 181 of file stm32h7xx_hal_conf.h.

#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 1U /* GFXMMU register callback disabled */

Definition at line 188 of file stm32h7xx_hal_conf.h.

#define USE_HAL_HASH_REGISTER_CALLBACKS 1U /* HASH register callback disabled */

Definition at line 186 of file stm32h7xx_hal_conf.h.

#define USE_HAL_HCD_REGISTER_CALLBACKS 1U /* HCD register callback disabled */

Definition at line 187 of file stm32h7xx_hal_conf.h.

#define USE_HAL_HRTIM_REGISTER_CALLBACKS 1U /* HRTIM register callback disabled */

Definition at line 189 of file stm32h7xx_hal_conf.h.

#define USE_HAL_I2C_REGISTER_CALLBACKS 1U /* I2C register callback disabled */

Definition at line 190 of file stm32h7xx_hal_conf.h.

#define USE_HAL_I2S_REGISTER_CALLBACKS 1U /* I2S register callback disabled */

Definition at line 191 of file stm32h7xx_hal_conf.h.

#define USE_HAL_IRDA_REGISTER_CALLBACKS 1U /* IRDA register callback disabled */

Definition at line 192 of file stm32h7xx_hal_conf.h.

#define USE_HAL_JPEG_REGISTER_CALLBACKS 1U /* JPEG register callback disabled */

Definition at line 193 of file stm32h7xx_hal_conf.h.

#define USE_HAL_LPTIM_REGISTER_CALLBACKS 1U /* LPTIM register callback disabled */

Definition at line 194 of file stm32h7xx_hal_conf.h.

#define USE_HAL_LTDC_REGISTER_CALLBACKS 1U /* LTDC register callback disabled */

Definition at line 195 of file stm32h7xx_hal_conf.h.

#define USE_HAL_MDIOS_REGISTER_CALLBACKS 1U /* MDIO register callback disabled */

Definition at line 196 of file stm32h7xx_hal_conf.h.

#define USE_HAL_MMC_REGISTER_CALLBACKS 1U /* MMC register callback disabled */

Definition at line 197 of file stm32h7xx_hal_conf.h.

#define USE_HAL_NAND_REGISTER_CALLBACKS 1U /* NAND register callback disabled */

Definition at line 182 of file stm32h7xx_hal_conf.h.

#define USE_HAL_NOR_REGISTER_CALLBACKS 1U /* NOR register callback disabled */

Definition at line 183 of file stm32h7xx_hal_conf.h.

#define USE_HAL_OPAMP_REGISTER_CALLBACKS 1U /* MDIO register callback disabled */

Definition at line 198 of file stm32h7xx_hal_conf.h.

#define USE_HAL_OSPI_REGISTER_CALLBACKS 1U /* OSPI register callback disabled */

Definition at line 199 of file stm32h7xx_hal_conf.h.

#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 1U /* OTFDEC register callback disabled */

Definition at line 200 of file stm32h7xx_hal_conf.h.

#define USE_HAL_PCD_REGISTER_CALLBACKS 1U /* PCD register callback disabled */

Definition at line 201 of file stm32h7xx_hal_conf.h.

#define USE_HAL_QSPI_REGISTER_CALLBACKS 1U /* QSPI register callback disabled */

Definition at line 202 of file stm32h7xx_hal_conf.h.

#define USE_HAL_RNG_REGISTER_CALLBACKS 1U /* RNG register callback disabled */

Definition at line 203 of file stm32h7xx_hal_conf.h.

#define USE_HAL_RTC_REGISTER_CALLBACKS 1U /* RTC register callback disabled */

Definition at line 204 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SAI_REGISTER_CALLBACKS 1U /* SAI register callback disabled */

Definition at line 205 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SD_REGISTER_CALLBACKS 1U /* SD register callback disabled */

Definition at line 206 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SDRAM_REGISTER_CALLBACKS 1U /* SDRAM register callback disabled */

Definition at line 184 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U /* SMARTCARD register callback disabled */

Definition at line 207 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SMBUS_REGISTER_CALLBACKS 1U /* SMBUS register callback disabled */

Definition at line 209 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 1U /* SPDIFRX register callback disabled */

Definition at line 208 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SPI_REGISTER_CALLBACKS 1U /* SPI register callback disabled */

Definition at line 210 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SRAM_REGISTER_CALLBACKS 1U /* SRAM register callback disabled */

Definition at line 185 of file stm32h7xx_hal_conf.h.

#define USE_HAL_SWPMI_REGISTER_CALLBACKS 1U /* SWPMI register callback disabled */

Definition at line 211 of file stm32h7xx_hal_conf.h.

#define USE_HAL_TIM_REGISTER_CALLBACKS 1U /* TIM register callback disabled */

Definition at line 212 of file stm32h7xx_hal_conf.h.

#define USE_HAL_UART_REGISTER_CALLBACKS 1U /* UART register callback disabled */

Definition at line 213 of file stm32h7xx_hal_conf.h.

#define USE_HAL_USART_REGISTER_CALLBACKS 1U /* USART register callback disabled */

Definition at line 214 of file stm32h7xx_hal_conf.h.

#define USE_HAL_WWDG_REGISTER_CALLBACKS 1U /* WWDG register callback disabled */

Definition at line 215 of file stm32h7xx_hal_conf.h.

#define USE_RTOS 0

Definition at line 166 of file stm32h7xx_hal_conf.h.

#define USE_SD_TRANSCEIVER 1U

use uSD Transceiver

Definition at line 167 of file stm32h7xx_hal_conf.h.

#define USE_SPI_CRC 1U

use CRC in SPI

Definition at line 168 of file stm32h7xx_hal_conf.h.

#define VDD_VALUE ((uint32_t)3300)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 164 of file stm32h7xx_hal_conf.h.

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STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma2d.h File Reference

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stm32h7xx_hal_dma2d.h File Reference

Header file of DMA2D HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DMA2D HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma2d.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dsi.c File Reference

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stm32h7xx_hal_dsi.c File Reference

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
        PLL parameters, number of lanes and TX Escape clock divider.
    (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
        command mode.
    (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
    (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
    (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
    (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
        Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
        to write DSI short packets, long packets and to read DSI packets.

    (#) The DSI Host Offers two Low power modes :
        (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
            It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
            and @ref HAL_DSI_ExitULPMData()

        (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
            It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
            and @ref HAL_DSI_ExitULPM()

    (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
        When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
        the error code by calling function @ref HAL_DSI_GetError()

    (#) To control DSI state you can use the following function: HAL_DSI_GetState()

     *** DSI HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DSI HAL driver.

      (+) __HAL_DSI_ENABLE: Enable the DSI Host.
      (+) __HAL_DSI_DISABLE: Disable the DSI Host.
      (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
      (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
      (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
      (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
      (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
      (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
      (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
      (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
      (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
      (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
      (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_DSI_RegisterCallback() to register a callback.

  Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
    (+) TearingEffectCallback : DSI Tearing Effect Callback.
    (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
    (+) ErrorCallback         : DSI Error Callback
    (+) MspInitCallback       : DSI MspInit.
    (+) MspDeInitCallback     : DSI MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TearingEffectCallback : DSI Tearing Effect Callback.
    (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
    (+) ErrorCallback         : DSI Error Callback
    (+) MspInitCallback       : DSI MspInit.
    (+) MspDeInitCallback     : DSI MspDeInit.

  By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
  all callbacks are set to the corresponding weak functions:
  examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
  or HAL_DSI_Init function.

  When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

     [..]
       (@) You can refer to the DSI HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dsi.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dsi.h File Reference

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stm32h7xx_hal_dsi.h File Reference

Header file of DSI HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DSI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dsi.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dts.h File Reference

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stm32h7xx_hal_dts.h File Reference

Header file of DTS HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DTS HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dts.h.

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STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth.c File Reference

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stm32h7xx_hal_eth.c File Reference

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
     [..]
     The ETH HAL driver can be used as follows:

      (#)Declare a ETH_HandleTypeDef handle structure, for example:
         ETH_HandleTypeDef  heth;

      (#)Fill parameters of Init structure in heth handle

      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)

      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
          (##) Enable the Ethernet interface clock using
                (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
                (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
                (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()

          (##) Initialize the related GPIO clocks
          (##) Configure Ethernet pinout
          (##) Configure Ethernet NVIC interrupt (in Interrupt mode)

      (#) Ethernet data reception is asynchronous, so call the following API
          to start the listening mode:
          (##) HAL_ETH_Start():
               This API starts the MAC and DMA transmission and reception process,
               without enabling end of transfer interrupts, in this mode user
               has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
          (##) HAL_ETH_Start_IT():
               This API starts the MAC and DMA transmission and reception process,
               end of transfer interrupts are enabled in this mode,
               HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received

      (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
          occurred), user can call the following APIs to get received data:
          (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
          (##) HAL_ETH_GetRxDataLength(): Get received frame length
          (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
               please refer to ETH_RxPacketInfo typedef structure

      (#) For transmission path, two APIs are available:
         (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
         (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
              HAL_ETH_TxCpltCallback() will be executed when end of transfer occur

      (#) Communication with an external PHY device:
         (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
         (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register

      (#) Configure the Ethernet MAC after ETH peripheral initialization
          (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
          (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef

      (#) Configure the Ethernet DMA after ETH peripheral initialization
          (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
          (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef

      -@- The PTP protocol offload APIs are not supported in this driver.

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.

  Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback   : Tx Complete Callback.
    (+) RxCpltCallback   : Rx Complete Callback.
    (+) DMAErrorCallback : DMA Error Callback.
    (+) MACErrorCallback : MAC Error Callback.
    (+) PMTCallback      : Power Management Callback
    (+) EEECallback      : EEE Callback.
    (+) WakeUpCallback   : Wake UP Callback
    (+) MspInitCallback  : MspInit Callback.
    (+) MspDeInitCallback: MspDeInit Callback.

  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxCpltCallback   : Tx Complete Callback.
    (+) RxCpltCallback   : Rx Complete Callback.
    (+) DMAErrorCallback : DMA Error Callback.
    (+) MACErrorCallback : MAC Error Callback.
    (+) PMTCallback      : Power Management Callback
    (+) EEECallback      : EEE Callback.
    (+) WakeUpCallback   : Wake UP Callback
    (+) MspInitCallback  : MspInit Callback.
    (+) MspDeInitCallback: MspDeInit Callback.

  By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
  all callbacks are set to the corresponding weak functions:
  examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
  or HAL_ETH_Init function.

  When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_eth.c.

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STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth.h File Reference

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stm32h7xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of ETH HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_eth.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth_ex.c File Reference

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stm32h7xx_hal_eth_ex.c File Reference

ETH HAL Extended module driver. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

ETH HAL Extended module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_eth_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth_ex.h File Reference

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stm32h7xx_hal_eth_ex.h File Reference

Header file of ETH HAL Extended module. More...

Go to the source code of this file.

Detailed Description

Header file of ETH HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_eth_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hrtim.c File Reference

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stm32h7xx_hal_hrtim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

Author:
MCD Application Team
==============================================================================
                      ##### Simple mode v.s. waveform mode #####
==============================================================================
  [..] The HRTIM HAL API is split into 2 categories:
    (#)Simple functions: these functions allow for using a HRTIM timer as a
       general purpose timer with high resolution capabilities.
       HRTIM simple modes are managed through the set of functions named
       HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
       to the one defined for the TIM peripheral. When a HRTIM timer operates in
       simple mode, only a very limited set of HRTIM features are used.
       Following simple modes are proposed:
         (++)Output compare mode,
         (++)PWM output mode,
         (++)Input capture mode,
         (++)One pulse mode.
    (#)Waveform functions: These functions allow taking advantage of the HRTIM
       flexibility to produce numerous types of control signal. When a HRTIM timer
       operates in waveform mode, all the HRTIM features are accessible without
       any restriction. HRTIM waveform modes are managed through the set of
       functions named HAL_HRTIM_Waveform<Function>
                      ##### How to use this driver #####
==============================================================================
    [..]
     (#)Initialize the HRTIM low level resources by implementing the
        HAL_HRTIM_MspInit() function:
        (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
        (##)Connect HRTIM pins to MCU I/Os
            (+++) Enable the clock for the HRTIM GPIOs using the following
                  function: __HAL_RCC_GPIOx_CLK_ENABLE()
            (+++) Configure these GPIO pins in Alternate Function mode using
                  HAL_GPIO_Init()
        (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
            (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++)Initialize the DMA handle
            (+++)Associate the initialized DMA handle to the appropriate DMA
                 handle of the HRTIM handle using __HAL_LINKDMA()
            (+++)Initialize the DMA channel using HAL_DMA_Init()
            (+++)Configure the priority and enable the NVIC for the transfer
                 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
                 and HAL_NVIC_EnableIRQ()
        (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
            (+++)Configure the priority and enable the NVIC for the concerned
                 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

    (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
       structure (field of the HRTIM handle) specifies which global interrupt of
       whole HRTIM must be enabled (Burst mode period, System fault, Faults).
       It also contains the HRTIM external synchronization configuration. HRTIM
       can act as a master (generating a synchronization signal) or as a slave
       (waiting for a trigger to be synchronized).

     (#) Configure HRTIM resources shared by all HRTIM timers
        (##)Burst Mode Controller:
                (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
                     controller: operating mode (continuous or one-shot mode), clock
                     (source, prescaler) , trigger(s), period, idle duration.
        (##)External Events Conditioning:
                (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
                     external event channel: source, polarity, edge-sensitivity.
                     External event can be used as triggers (timer reset, input
                     capture, burst mode, ADC triggers, delayed protection)
                     They can also be used to set or reset timer outputs. Up to
                     10 event channels are available.
                (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
                     event sampling clock (used for digital filtering).
        (##)Fault Conditioning:
                (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
                     fault channel: source, polarity, edge-sensitivity. Fault
                     channels are used to disable the outputs in case of an
                     abnormal operation. Up to 5 fault channels are available.
                (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
                     sampling clock (used for digital filtering).
                (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
                     circuitry. By default all fault inputs are disabled.
        (##)ADC trigger:
                (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
                     the update of the ADC trigger register and the ADC trigger.
                     4 independent triggers are available to start both the regular
                     and the injected sequencers of the 2 ADCs

     (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
         function must be called whatever the HRTIM timer operating mode is
         (simple v.s. waveform). It configures mainly:
        (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
        (##)The HRTIM  timer clock prescaler
        (##)The HRTIM  timer period
        (##)The HRTIM  timer repetition counter

     *** If the HRTIM timer operates in simple mode ***
     ===================================================
     [..]
     (#) Start or Stop simple timers
              (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
                  HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
                  HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
              (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
                  HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
                  HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
                  HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
              (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
                  HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
                  HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
                  HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
              (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
                  HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
                  HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
                  HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
              (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
                  HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
                  HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().

     *** If the HRTIM timer operates in waveform mode ***
     ====================================================
     [..]
     (#) Completes waveform timer configuration
              (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
                  operating in wave form mode mainly consists in:
                (+++)Enabling the HRTIM timer interrupts and DMA requests.
                (+++)Enabling the half mode for the HRTIM timer.
                (+++)Defining how the HRTIM timer reacts to external synchronization input.
                (+++)Enabling the push-pull mode for the HRTIM timer.
                (+++)Enabling the fault channels for the HRTIM timer.
                (+++)Enabling the dead-time insertion for the HRTIM timer.
                (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
                     on which the delayed protection are applied).
                (+++)Specifying the HRTIM timer update and reset triggers.
                (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
              (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
                  event blanking and windowing circuitry of a HRTIM timer:
                (+++)Blanking:  to mask external events during a defined  time period a defined time period
                (+++)Windowing, to enable external events only during a defined time period
              (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
                  unit for a HRTIM timer. Allows to generate a couple of
                  complementary signals from a single reference waveform,
                  with programmable delays between active state.
              (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
                  the high-frequency carrier signal added on top of the timing
                  unit output. Chopper mode can be enabled or disabled for each
                   timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
              (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
                  controller. Allows having multiple HRTIM registers updated
                  with a single DMA request. The burst DMA operation is started
                  by calling HAL_HRTIM_BurstDMATransfer().
              (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
                  of a HRTIM timer. This operation consists in setting the
                  compare value and possibly specifying the auto delayed mode
                  for compare units 2 and 4 (allows to have compare events
                  generated relatively to capture events). Note that when auto
                  delayed mode is needed, the capture unit associated to the
                  compare unit must be configured separately.
              (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
                  of a HRTIM timer. This operation consists in specifying the
                  source(s)  triggering the capture (timer register update event,
                  external event, timer output set/reset event, other HRTIM
                  timer related events).
              (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
                  output mainly consists in:
                (+++)Setting the output polarity (active high or active low),
                (+++)Defining the set/reset crossbar for the output,
                (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,

     (#) Set waveform timer output(s) level
              (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
                  active or inactive level. For example, when deadtime insertion
                  is enabled it is necessary to force the output level by software
                  to have the outputs in a complementary state as soon as the RUN mode is entered.

     (#) Enable or Disable waveform timer output(s)
              (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().

     (#) Start or Stop waveform HRTIM timer(s).
              (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
              (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
              (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
     (#) Burst mode controller enabling:
              (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
                  burst mode controller.

     (#) Some HRTIM operations can be triggered by software:
              (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
                  trigs the burst operation.
              (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
                  capture of the HRTIM timer counter.
              (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
                  update of the pre-loadable registers of the HRTIM timer
              (++)HAL_HRTIM_SoftwareReset():calling this function resets the
                  HRTIM timer counter.

     (#) Some functions can be used any time to retrieve HRTIM timer related
            information
              (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
                  capture register of the designated capture unit.
              (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
                 (ACTIVE/INACTIVE) of the designated timer output.
              (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
                 (IDLE/RUN/FAULT) of the designated timer output.
              (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
                 (ACTIVE/INACTIVE) of the designated output when the delayed
                  protection was triggered.
              (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
                 (ACTIVE/INACTIVE) of the burst mode controller.
              (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the push-pull status indicates on which output the signal is currently
                 active (e.g signal applied on output 1 and output 2 forced
                 inactive or vice versa).
             (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the idle push-pull status indicates during which period the
                 delayed protection request occurred (e.g. protection occurred
                 when the output 1 was active and output 2 forced inactive or
                 vice versa).

     (#) Some functions can be used any time to retrieve actual HRTIM status
             (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.

     *** Callback registration ***
     =============================
     [..]
     The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
     to register an interrupt callback.

     [..]
     Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
       (+) Fault1Callback               : Fault 1 interrupt callback function
       (+) Fault2Callback               : Fault 2 interrupt callback function
       (+) Fault3Callback               : Fault 3 interrupt callback function
       (+) Fault4Callback               : Fault 4 interrupt callback function
       (+) Fault5Callback               : Fault 5 interrupt callback function
       (+) SystemFaultCallback          : System fault interrupt callback function
       (+) BurstModePeriodCallback      : Burst mode period interrupt callback function
       (+) SynchronizationEventCallback : Sync Input interrupt callback function
       (+) ErrorCallback                : DMA error callback function
       (+) MspInitCallback              : HRTIM MspInit callback function
       (+) MspDeInitCallback            : HRTIM MspInit callback function

     [..]
     Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
       (+) RegistersUpdateCallback   : Timer x Update interrupt callback function
       (+) RepetitionEventCallback   : Timer x Repetition interrupt callback function
       (+) Compare1EventCallback     : Timer x Compare 1 match interrupt callback function
       (+) Compare2EventCallback     : Timer x Compare 2 match interrupt callback function
       (+) Compare3EventCallback     : Timer x Compare 3 match interrupt callback function
       (+) Compare4EventCallback     : Timer x Compare 4 match interrupt callback function
       (+) Capture1EventCallback     : Timer x Capture 1 interrupts callback function
       (+) Capture2EventCallback     : Timer x Capture 2 interrupts callback function
       (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
       (+) CounterResetCallback      : Timer x counter reset/roll-over interrupt callback function
       (+) Output1SetCallback        : Timer x output 1 set interrupt callback function
       (+) Output1ResetCallback      : Timer x output 1 reset interrupt callback function
       (+) Output2SetCallback        : Timer x output 2 set interrupt callback function
       (+) Output2ResetCallback      : Timer x output 2 reset interrupt callback function
       (+) BurstDMATransferCallback  : Timer x Burst DMA completed interrupt callback function

     [..]
     Both functions take as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.

     [..]
     Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
     to reset a callback to the default weak function. Both functions take  as parameters
     the HAL peripheral handle and the Callback ID.

     [..]
     By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
     all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
     Exception done for MspInit and MspDeInit functions that are reset to the legacy
     weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
     callbacks are null (not registered beforehand). If MspInit or MspDeInit are
     not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
     MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

     [..]
     Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
     (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
     or HAL_HRTIM_Init() function.

     [..]
     When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all
     callbacks are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hrtim.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hrtim.h File Reference

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stm32h7xx_hal_hrtim.h File Reference

Header file of HRTIM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of HRTIM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hrtim.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s_ex.c File Reference

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stm32h7xx_hal_i2s_ex.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### I2S Extension features #####
  ==============================================================================
  [..]
     (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
         data simultaneously using two data lines. Each SPI peripheral has an extended block
         called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
     (#) The extension block is not a full SPI IP, it is used only as I2S slave to
         implement full duplex mode. The extension block uses the same clock sources
         as its master.

     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.

     [..]
       (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
         I2Sx can be I2S2 or I2S3.

                  ##### How to use this driver #####
 ===============================================================================
 [..]
   Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
     (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
     (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

Additional Figure: The Extended block uses the same clock sources as its master.

+-----------------------+ I2Sx_SCK | | ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) +--|-->| | | | +-----------------------+ | | I2S_WS | | ------>| | | | +-----------------------+ | +-->| | | | I2Sx_ext |------------------->I2Sx_extSD(in/out) +----->| | +-----------------------+

Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2s_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s_ex.h File Reference

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stm32h7xx_hal_i2s_ex.h File Reference

Header file of I2S HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2s_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc_ex.c File Reference

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stm32h7xx_hal_ltdc_ex.c File Reference

LTDC Extension HAL module driver. More...

#include "stm32h7xx_hal.h"

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Detailed Description

LTDC Extension HAL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ltdc_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc_ex.h File Reference

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stm32h7xx_hal_ltdc_ex.h File Reference

Header file of LTDC HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of LTDC HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ltdc_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_otfdec.h File Reference

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stm32h7xx_hal_otfdec.h File Reference

Header file of OTFDEC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of OTFDEC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_otfdec.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_qspi.c File Reference

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stm32h7xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
            with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** MDMA functional mode ***
    ====================================
    [..]
      (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
         (++) MDMA settings for write operation :
          (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
          (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
              aligned with @ref MDMA_Source_increment_mode .
          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
         (++) MDMA settings for read operation :
          (+) The SourceInc should be MDMA_SRC_INC_DISABLE
          (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
              aligned with @ref MDMA_Destination_increment_mode.
         (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
      (#)In case of wrong MDMA setting
        (++) For write operation :
         (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
        (++) For read operation :
         (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
              the transfer complete bi is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
      and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
      or @ref HAL_QSPI_Init function.

      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_qspi.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_qspi.h File Reference

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stm32h7xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_qspi.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_adc.c File Reference

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Defines | Functions
stm32h7xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32h7xx_ll_adc.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bdma.c File Reference

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Defines | Functions
stm32h7xx_ll_bdma.c File Reference

BDMA LL module driver. More...

#include "stm32h7xx_ll_bdma.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_BDMA_DIRECTION(__VALUE__)
#define | IS_LL_BDMA_MODE(__VALUE__)
#define | IS_LL_BDMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_BDMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2)
#define | IS_LL_BDMA_PRIORITY(__VALUE__)
#define | IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

uint32_t | LL_BDMA_DeInit (BDMA_TypeDef *BDMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_BDMA_Init (BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
void | LL_BDMA_StructInit (LL_BDMA_InitTypeDef *BDMA_InitStruct)
Set each LL_BDMA_InitTypeDef field to default value.

Detailed Description

BDMA LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_bdma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_bdma.c.

Referenced by LL_BDMA_DeInit(), and LL_BDMA_Init().

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_comp.c File Reference

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stm32h7xx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32h7xx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crc.c File Reference

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Defines | Functions
stm32h7xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32h7xx_ll_crc.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dac.c File Reference

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Defines | Functions
stm32h7xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32h7xx_ll_dac.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_dac.c.

Referenced by LL_DAC_DeInit(), and LL_DAC_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma.c File Reference

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Defines | Functions
stm32h7xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32h7xx_ll_dma.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)
#define | IS_LL_DMA_FIFO_MODE_STATE(STATE)
#define | IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_LL_DMA_MEMORY_BURST(BURST)
#define | IS_LL_DMA_PERIPHERAL_BURST(BURST)

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Stream)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma2d.c File Reference

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Defines | Functions
stm32h7xx_ll_dma2d.c File Reference

DMA2D LL module driver. More...

#include "stm32h7xx_ll_dma2d.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | LL_DMA2D_COLOR 0xFFU
#define | LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL
#define | LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)
#define | LL_DMA2D_OFFSET_MAX 0x3FFFU
#define | LL_DMA2D_CLUTSIZE_MAX 0xFFU
#define | IS_LL_DMA2D_MODE(MODE)
#define | IS_LL_DMA2D_OCMODE(MODE_ARGB)
#define | IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
#define | IS_LL_DMA2D_OFFSET_MODE(MODE)
#define | IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
#define | IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
#define | IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
#define | IS_LL_DMA2D_SWAP_MODE(MODE)
#define | IS_LL_DMA2D_ALPHAINV(ALPHA)
#define | IS_LL_DMA2D_RBSWAP(RBSWAP)
#define | IS_LL_DMA2D_LCMODE(MODE_ARGB)
#define | IS_LL_DMA2D_CLUTCMODE(CLUTCMODE)
#define | IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
#define | IS_LL_DMA2D_ALPHAMODE(MODE)
#define | IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS)

Functions

ErrorStatus | LL_DMA2D_DeInit (DMA2D_TypeDef *DMA2Dx)
De-initialize DMA2D registers (registers restored to their default values).
ErrorStatus | LL_DMA2D_Init (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
void | LL_DMA2D_StructInit (LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Set each LL_DMA2D_InitTypeDef field to default value.
void | LL_DMA2D_ConfigLayer (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
Configure the foreground or background according to the specified parameters in the LL_DMA2D_LayerCfgTypeDef structure.
void | LL_DMA2D_LayerCfgStructInit (LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
Set each LL_DMA2D_LayerCfgTypeDef field to default value.
void | LL_DMA2D_ConfigOutputColor (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
Initialize DMA2D output color register according to the specified parameters in DMA2D_ColorStruct.
uint32_t | LL_DMA2D_GetOutputBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Blue color.
uint32_t | LL_DMA2D_GetOutputGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Green color.
uint32_t | LL_DMA2D_GetOutputRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Red color.
uint32_t | LL_DMA2D_GetOutputAlphaColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Alpha color.
void | LL_DMA2D_ConfigSize (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
Configure DMA2D transfer size.

Detailed Description

DMA2D LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dma2d.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_dma2d.c.

Referenced by LL_DMA2D_ConfigLayer(), LL_DMA2D_ConfigOutputColor(), LL_DMA2D_DeInit(), LL_DMA2D_GetOutputAlphaColor(), LL_DMA2D_GetOutputBlueColor(), LL_DMA2D_GetOutputGreenColor(), LL_DMA2D_GetOutputRedColor(), and LL_DMA2D_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_exti.c File Reference

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Defines | Functions
stm32h7xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32h7xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32h7xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_gpio.c File Reference

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Defines | Functions
stm32h7xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32h7xx_ll_gpio.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hrtim.c File Reference

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Defines
stm32h7xx_ll_hrtim.c File Reference

HRTIM LL module driver. More...

#include "stm32h7xx_ll_hrtim.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0U)

Detailed Description

HRTIM LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_hrtim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_hrtim.c.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hrtim.h File Reference

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stm32h7xx_ll_hrtim.h File Reference

Header file of HRTIM LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Detailed Description

Header file of HRTIM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_hrtim.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_i2c.c File Reference

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Defines | Functions
stm32h7xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32h7xx_ll_i2c.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lptim.c File Reference

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Defines | Functions
stm32h7xx_ll_lptim.c File Reference

LPTIM LL module driver. More...

#include "stm32h7xx_ll_lptim.h"
#include "stm32h7xx_ll_bus.h"
#include "stm32h7xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Detailed Description

LPTIM LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_lptim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 30 of file stm32h7xx_ll_lptim.c.

Referenced by LL_LPTIM_DeInit(), LL_LPTIM_Disable(), and LL_LPTIM_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lpuart.c File Reference

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Defines | Functions
stm32h7xx_ll_lpuart.c File Reference

LPUART LL module driver. More...

#include "stm32h7xx_ll_lpuart.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

LPUART LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_lpuart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_lpuart.c.

Referenced by LL_LPUART_DeInit(), and LL_LPUART_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_mdma.c File Reference

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Defines | Functions
stm32h7xx_ll_mdma.c File Reference

MDMA LL module driver. More...

#include "stm32h7xx_ll_mdma.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)
#define | IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U)
#define | IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU)
#define | IS_LL_MDMA_WORDENDIANESS(__VALUE__)
#define | IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__)
#define | IS_LL_MDMA_BYTEENDIANESS(__VALUE__)
#define | IS_LL_MDMA_PRIORITY(__VALUE__)
#define | IS_LL_MDMA_BUFFWRITEMODE(__VALUE__)
#define | IS_LL_MDMA_REQUESTMODE(__VALUE__)
#define | IS_LL_MDMA_TRIGGERMODE(__VALUE__)
#define | IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__)
#define | IS_LL_MDMA_PACKMODE(__VALUE__)
#define | IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU)
#define | IS_LL_MDMA_DESTBURST(__VALUE__)
#define | IS_LL_MDMA_SRCTBURST(__VALUE__)
#define | IS_LL_MDMA_DESTINCSIZE(__VALUE__)
#define | IS_LL_MDMA_SRCINCSIZE(__VALUE__)
#define | IS_LL_MDMA_DESTDATASIZE(__VALUE__)
#define | IS_LL_MDMA_SRCDATASIZE(__VALUE__)
#define | IS_LL_MDMA_DESTINCMODE(__VALUE__)
#define | IS_LL_MDMA_SRCINCMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__)
#define | IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_MDMA_DEST_BUS(__VALUE__)
#define | IS_LL_MDMA_SRC_BUS(__VALUE__)
#define | IS_LL_MDMA_HWTRIGGER(__VALUE__)

Functions

uint32_t | LL_MDMA_DeInit (MDMA_TypeDef *MDMAx, uint32_t Channel)
De-initialize the MDMA registers to their default reset values.
uint32_t | LL_MDMA_Init (MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
void | LL_MDMA_StructInit (LL_MDMA_InitTypeDef *MDMA_InitStruct)
Set each LL_MDMA_InitTypeDef field to default value.
void | LL_MDMA_CreateLinkNode (LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
Initializes MDMA linked list node according to the specified parameters in the MDMA_InitStruct.
void | LL_MDMA_ConnectLinkNode (LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
Connect Linked list Nodes.
void | LL_MDMA_DisconnectNextLinkNode (LL_MDMA_LinkNodeTypeDef *pLinkNode)
Disconnect the next linked list node.

Detailed Description

MDMA LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_mdma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_mdma.c.

Referenced by LL_MDMA_CreateLinkNode(), LL_MDMA_DeInit(), and LL_MDMA_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_opamp.c File Reference

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Defines | Functions
stm32h7xx_ll_opamp.c File Reference

OPAMP LL module driver. More...

#include "stm32h7xx_ll_opamp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

OPAMP LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_opamp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_opamp.c.

Referenced by LL_OPAMP_DeInit(), and LL_OPAMP_Init().

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rcc.c File Reference

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Defines | Functions | Variables
stm32h7xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_GetPCLK3ClockFreq (uint32_t HCLK_Frequency)
Return PCLK3 clock frequency.
uint32_t | RCC_GetPCLK4ClockFreq (uint32_t HCLK_Frequency)
Return PCLK4 clock frequency.
void | LL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
void | LL_RCC_GetPLL1ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL1 clocks frequencies.
void | LL_RCC_GetPLL2ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL2 clocks frequencies.
void | LL_RCC_GetPLL3ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL3 clocks frequencies.
uint32_t | LL_RCC_CalcPLLClockFreq (uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
Helper function to calculate the PLL frequency output.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUART clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADC clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMC clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNG clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USB clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetDFSDM2ClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetSPDIFClockFreq (uint32_t SPDIFxSource)
Return SPDIF clock frequency.
uint32_t | LL_RCC_GetSPIClockFreq (uint32_t SPIxSource)
Return SPIx clock frequency.
uint32_t | LL_RCC_GetSWPClockFreq (uint32_t SWPxSource)
Return SWP clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN clock frequency.
uint32_t | LL_RCC_GetFMCClockFreq (uint32_t FMCxSource)
Return FMC clock frequency.
uint32_t | LL_RCC_GetOSPIClockFreq (uint32_t OSPIxSource)
Return OSPI clock frequency.
uint32_t | LL_RCC_GetCLKPClockFreq (uint32_t CLKPxSource)
Return CLKP clock frequency.

Variables

const uint8_t | LL_RCC_PrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSPIClockFreq(), and LL_RCC_GetUSARTClockFreq().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rng.c File Reference

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Defines | Functions
stm32h7xx_ll_rng.c File Reference

RNG LL module driver. More...

#include "stm32h7xx_ll_rng.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RNG_CED(__MODE__)
#define | IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu)
#define | IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__)
#define | IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
#define | IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
#define | IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Detailed Description

RNG LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rng.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_rng.c.

Referenced by LL_RNG_DeInit(), and LL_RNG_Init().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rtc.c File Reference

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Defines | Functions
stm32h7xx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32h7xx_ll_rtc.h"
#include "stm32h7xx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_spi.c File Reference

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Defines | Functions
stm32h7xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32h7xx_ll_spi.h"
#include "stm32h7xx_ll_bus.h"
#include "stm32h7xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_SS_IDLENESS(__VALUE__)
#define | IS_LL_SPI_ID_IDLENESS(__VALUE__)
#define | IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)
#define | IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)
#define | IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)
#define | IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)
#define | IS_LL_SPI_PROTOCOL(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_FIFO_TH(__VALUE__)
#define | IS_LL_SPI_CRC(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_RX_FIFO(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
#define | I2S_I2SCFGR_CLEAR_MASK
#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CHANNEL_LENGTH_TYPE
#define | IS_LL_I2S_CKPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)
#define | IS_LL_I2S_FIFO_TH
#define | IS_LL_I2S_BIT_ORDER(__VALUE__)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 31 of file stm32h7xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler(), LL_I2S_Init(), LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_swpmi.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_ll_swpmi.c File Reference

SWPMI LL module driver. More...

#include "stm32h7xx_ll_swpmi.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
#define | IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__)
#define | IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__)
#define | IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__)

Functions

ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Detailed Description

SWPMI LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_swpmi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_swpmi.c.

Referenced by LL_SWPMI_DeInit(), and LL_SWPMI_Init().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_tim.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32h7xx_ll_tim.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_usart.c File Reference

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Defines | Functions
stm32h7xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32h7xx_ll_usart.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32h7xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_utils.c File Reference

  • File List
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Defines | Functions
stm32h7xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32h7xx_ll_utils.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_MAX_FREQUENCY_SCALE1 400000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 300000000U
#define | UTILS_MAX_FREQUENCY_SCALE3 200000000U
#define | UTILS_PLLVCO_INPUT_MIN1 1000000U
#define | UTILS_PLLVCO_INPUT_MAX1 2000000U
#define | UTILS_PLLVCO_INPUT_MIN2 2000000U
#define | UTILS_PLLVCO_INPUT_MAX2 4000000U
#define | UTILS_PLLVCO_INPUT_MIN3 4000000U
#define | UTILS_PLLVCO_INPUT_MAX3 8000000U
#define | UTILS_PLLVCO_INPUT_MIN4 8000000U
#define | UTILS_PLLVCO_INPUT_MAX4 16000000U
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U
#define | UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U
#define | UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY0_FREQ 70000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 140000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 210000000U
#define | UTILS_SCALE2_LATENCY0_FREQ 55000000U
#define | UTILS_SCALE2_LATENCY1_FREQ 110000000U
#define | UTILS_SCALE2_LATENCY2_FREQ 165000000U
#define | UTILS_SCALE2_LATENCY3_FREQ 220000000U
#define | UTILS_SCALE3_LATENCY0_FREQ 45000000U
#define | UTILS_SCALE3_LATENCY1_FREQ 90000000U
#define | UTILS_SCALE3_LATENCY2_FREQ 135000000U
#define | UTILS_SCALE3_LATENCY3_FREQ 180000000U
#define | UTILS_SCALE3_LATENCY4_FREQ 225000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_AHB_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_APB3_DIV(__VALUE__)
#define | IS_LL_UTILS_APB4_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
#define | IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
#define | IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__)
#define | IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__)
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_CalculateFlashLatency (uint32_t HCLK_Frequency, uint32_t *latency)
Calculate and check the Flash wait states number according to the new HCLK frequency and current voltage range.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t latency)
Update number of Flash wait states.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_IsPLLsReady (void)
Check that all PLLs are ready therefore configuration can be done.
void | LL_Init1msTick (uint32_t CPU_Frequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t CPU_Frequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32h7xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_PTR_REG_OFFSET : stm32h7xx_ll_adc.h
  • __DAC_PTR_REG_OFFSET : stm32h7xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32h7xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32h7xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32h7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32h7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32h7xx_hal_adc.h
  • __HAL_BDMA_CHANNEL_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_BDMA_CHANNEL_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_BDMA_CHANNEL_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_BDMA_GET_GI_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_CEC_CLEAR_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32h7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32h7xx_hal_cec.h
  • __HAL_COMP_CLEAR_C1IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_C2IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_IT_SOURCE : stm32h7xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32h7xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32h7xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32h7xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32h7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32h7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32h7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRYP_DISABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32h7xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32h7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32h7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_WWDG1 : stm32h7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32h7xx_hal_dcmi.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DMA_CLEAR_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32h7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FLASH_CALC_BOOT_BASE_ADR : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_CLEAR_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_PROGRAM_DELAY : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_SET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_SET_PROGRAM_DELAY : stm32h7xx_hal_flash_ex.h
  • __HAL_GFXMMU_RESET_HANDLE_STATE : stm32h7xx_hal_gfxmmu.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32h7xx_hal_gpio.h
  • __HAL_HASH_CLEAR_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_DISABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_ENABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_GET_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_INIT : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATE : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATUS : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_NBVALIDBITS : stm32h7xx_hal_hash.h
  • __HAL_HASH_START_DIGEST : stm32h7xx_hal_hash.h
  • __HAL_HCD_CLEAR_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HSEM_CLEAR_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32h7xx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32h7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_TIFREFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32h7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32h7xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32h7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32h7xx_hal_iwdg.h
  • __HAL_JPEG_CLEAR_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_IT_SOURCE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_RESET_HANDLE_STATE : stm32h7xx_hal_jpeg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32h7xx_hal_lptim.h
  • __HAL_LTDC_CLEAR_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_IT_SOURCE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RESET_HANDLE_STATE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_MDIOS_CLEAR_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_IT_SOURCE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_READ_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_WRITE_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_RESET_HANDLE_STATE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDMA_CLEAR_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_IT_SOURCE : stm32h7xx_hal_mdma.h
  • __HAL_MMC_CLEAR_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_CLEAR_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_DISABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_ENABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_RESET_HANDLE_STATE : stm32h7xx_hal_mmc.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32h7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32h7xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32h7xx_hal_opamp.h
  • __HAL_OSPI_CLEAR_FLAG : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_DISABLE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_DISABLE_IT : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_ENABLE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_ENABLE_IT : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_GET_FLAG : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_GET_IT_SOURCE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_RESET_HANDLE_STATE : stm32h7xx_hal_ospi.h
  • __HAL_PCD_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32h7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PWR_AVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_CLEAR_WAKEUPFLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_WAKEUPFLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32h7xx_hal_pwr.h
  • __HAL_RAMECC_CLEAR_FLAG : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_GLOBAL_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_MONITOR_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_GLOBAL_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_MONITOR_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_FLAG : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_GLOBAL_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_MONITOR_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_RESET_HANDLE_STATE : stm32h7xx_hal_ramecc.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB12_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB12_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB34_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB34_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM1_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM1_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM2_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM2_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM3_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM3_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLKP_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_COMP12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRYP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ECCRAM_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ECCRAM_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_EXTI_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_EXTI_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLIFT_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLIFT_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLKP_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_FMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HSI_DIVIDER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C123_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM345_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_OSPI_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2A_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2B_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPDIFRX_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI123_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI45_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART9_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART10_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART16910_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART16_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART234578_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GFXMMU_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUM_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUM_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUS_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUS_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIO_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIO_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C123_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JTAG_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JTAG_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM345_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI1_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI1_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI2_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI2_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_OTFDEC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCIRANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCORANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2A_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2B_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI123_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI45_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART9_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART10_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART16910_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART16_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART234578_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_VREF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32h7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32h7xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32h7xx_hal_rtc.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_PRCHRG_DURATION : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_PULLUP_STATUS : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_SAMPLES_COUNT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_GET_STATUS : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32h7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32h7xx_hal_sai.h
  • __HAL_SD_CLEAR_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_CLEAR_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_DISABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_ENABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_RESET_HANDLE_STATE : stm32h7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32h7xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32h7xx_hal_smbus.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32h7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_EOTFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_SUSPFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TSERFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TXTFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_UDRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32h7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32h7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32h7xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32h7xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32h7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32h7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32h7xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32h7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32h7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32h7xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32h7xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32h7xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32h7xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32h7xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32h7xx_ll_adc.h
  • __LL_ADC_MULTI_INSTANCE_MASTER : stm32h7xx_ll_adc.h
  • __LL_BDMA_GET_CHANNEL : stm32h7xx_ll_bdma.h
  • __LL_BDMA_GET_CHANNEL_INSTANCE : stm32h7xx_ll_bdma.h
  • __LL_BDMA_GET_INSTANCE : stm32h7xx_ll_bdma.h
  • __LL_COMP_COMMON_INSTANCE : stm32h7xx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32h7xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32h7xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32h7xx_ll_dac.h
  • __LL_DMA_GET_INSTANCE : stm32h7xx_ll_dma.h
  • __LL_DMA_GET_STREAM : stm32h7xx_ll_dma.h
  • __LL_DMA_GET_STREAM_INSTANCE : stm32h7xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32h7xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32h7xx_ll_lpuart.h
  • __LL_OPAMP_COMMON_INSTANCE : stm32h7xx_ll_opamp.h
  • __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_ll_opamp.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32h7xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32h7xx_ll_rtc.h
  • __LL_SWPMI_CALC_BITRATE_PRESCALER : stm32h7xx_ll_swpmi.h
  • __LL_TIM_CALC_ARR : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32h7xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32h7xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32h7xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32h7xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32h7xx_ll_usart.h
  • __OPAMP_PTR_REG_OFFSET : stm32h7xx_ll_opamp.h
  • __STM32H7xx_HAL_VERSION : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_MAIN : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_RC : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB1 : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB2 : stm32h7xx_hal.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • a_dfsdm1ChannelHandle : stm32h7xx_hal_dfsdm.c
  • a_dfsdm2ChannelHandle : stm32h7xx_hal_dfsdm.c
  • ADC12_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC12_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_1 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32h7xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32h7xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_AWD_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD_TR12_REGOFFSETGAP_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_TR12_REGOFFSETGAP_VAL : stm32h7xx_ll_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_FACTOR_LINEARITY_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_CALIB_FACTOR_OFFSET_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_CALIB_FACTOR_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_MODE_BINARY_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_MODE_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_OFFSET : stm32h7xx_hal_adc.h
  • ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_hal_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32h7xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CFGR_AUTOWAIT : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32h7xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_19_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC2CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32h7xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32h7xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_ConfigureBoostMode() : stm32h7xx_hal_adc.c
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32h7xx_hal_adc.c
  • ADC_CONVERSIONDATA_DFSDM : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_CIRCULAR : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_ONESHOT : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DR : stm32h7xx_hal_adc.h
  • ADC_ConversionStop() : stm32h7xx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32h7xx_ll_adc.h
  • ADC_DFSDM_MODE_DISABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DFSDM_MODE_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DIFFERENTIAL_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_Disable() : stm32h7xx_hal_adc.c
  • ADC_DISABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DMAError() : stm32h7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_32_10_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_8_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_DISABLED : stm32h7xx_hal_adc_ex.h
  • ADC_Enable() : stm32h7xx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32h7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32h7xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM1_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM2_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM3_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM1_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM2_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM3_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32h7xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32h7xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOC : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOS : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32h7xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32h7xx_hal_adc.h
  • ADC_FLAG_JEOS : stm32h7xx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32h7xx_hal_adc.h
  • ADC_FLAG_OVR : stm32h7xx_hal_adc.h
  • ADC_FLAG_RDY : stm32h7xx_hal_adc.h
  • ADC_FORCE_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32h7xx_hal_adc.h
  • ADC_HandleTypeDef : stm32h7xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32h7xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32h7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SYNCHRONOUS_CLOCK_MODE : stm32h7xx_hal_adc.h
  • ADC_IT_AWD : stm32h7xx_hal_adc.h
  • ADC_IT_AWD1 : stm32h7xx_hal_adc.h
  • ADC_IT_AWD2 : stm32h7xx_hal_adc.h
  • ADC_IT_AWD3 : stm32h7xx_hal_adc.h
  • ADC_IT_EOC : stm32h7xx_hal_adc.h
  • ADC_IT_EOS : stm32h7xx_hal_adc.h
  • ADC_IT_EOSMP : stm32h7xx_hal_adc.h
  • ADC_IT_JEOC : stm32h7xx_hal_adc.h
  • ADC_IT_JEOS : stm32h7xx_hal_adc.h
  • ADC_IT_JQOVF : stm32h7xx_hal_adc.h
  • ADC_IT_OVR : stm32h7xx_hal_adc.h
  • ADC_IT_RDY : stm32h7xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32h7xx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_1 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_10 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_11 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_12 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_13 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_14 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_15 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_2 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_3 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_4 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_5 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_6 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_7 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_8 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_9 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_NONE : stm32h7xx_hal_adc.h
  • ADC_LINEAR_CALIB_REG_1_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_2_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_3_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_4_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_5_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_6_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_COUNT : stm32h7xx_ll_adc.h
  • ADC_LINEARITY_BIT_TOGGLE_TIMEOUT : stm32h7xx_ll_adc.h
  • ADC_MASTER_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_OFRx_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32h7xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32h7xx_hal_adc.h
  • ADC_OVR_EVENT : stm32h7xx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32h7xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32h7xx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32h7xx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_14B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_16B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_10 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_11 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_9 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_16CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_32CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_387CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_64CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_810CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_8CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32h7xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32h7xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32h7xx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32h7xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32h7xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32h7xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32h7xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32h7xx_ll_adc.c
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32h7xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32h7xx_hal_adc.h
  • ADC_TRX_HIGHTHRESHOLD : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_AREA : stm32h7xx_hal_nand.h
  • ANALOG_MODE : stm32h7xx_hal_gpio.c
  • ARRAY_ADDRESS : stm32h7xx_hal_nand.h
  • assert_param : stm32h7xx_ll_comp.c , stm32h7xx_ll_lptim.c , stm32h7xx_ll_rng.c , stm32h7xx_ll_rcc.c , stm32h7xx_ll_crc.c , stm32h7xx_ll_exti.c , stm32h7xx_ll_dac.c , stm32h7xx_ll_spi.c , stm32h7xx_ll_lpuart.c , stm32h7xx_ll_mdma.c , stm32h7xx_ll_adc.c , stm32h7xx_ll_opamp.c , stm32h7xx_ll_tim.c , stm32h7xx_ll_rtc.c , stm32h7xx_ll_dma2d.c , stm32h7xx_ll_bdma.c , stm32h7xx_ll_gpio.c , stm32h7xx_ll_hrtim.c , stm32h7xx_ll_usart.c , stm32h7xx_ll_swpmi.c , stm32h7xx_ll_i2c.c , stm32h7xx_ll_utils.c , stm32h7xx_hal_conf.h , stm32h7xx_ll_dma.c
  • AVD_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_EVT : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_IT : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDMA_CH6_CLEAR : stm32h7xx_hal.h
  • BDMA_CH7_CLEAR : stm32h7xx_hal.h
  • BDMA_FLAG_GL0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE7 : stm32h7xx_hal_dma.h
  • BDMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.c
  • BDMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_REQUEST_DAC2_CH1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_DFSDM2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LPUART1_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LPUART1_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_TX : stm32h7xx_hal_dma.h
  • BKP_REG_NUMBER : stm32h7xx_hal_rtc_ex.h
  • BLOCKSIZE : stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CARD_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_NORMAL_SPEED : stm32h7xx_hal_sd.h
  • CARD_SDHC_SDXC : stm32h7xx_hal_sd.h
  • CARD_SDSC : stm32h7xx_hal_sd.h
  • CARD_SECURED : stm32h7xx_hal_sd.h
  • CARD_ULTRA_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_V1_X : stm32h7xx_hal_sd.h
  • CARD_V2_X : stm32h7xx_hal_sd.h
  • CCU_IR_MASK : stm32h7xx_hal_fdcan.h
  • CDCCIP : stm32h7xx_ll_rcc.h
  • CDCCIP1 : stm32h7xx_ll_rcc.h
  • CDCCIP2 : stm32h7xx_ll_rcc.h
  • CEC_0_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32h7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32h7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32h7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32h7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32h7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32h7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_HandleTypeDef : stm32h7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32h7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32h7xx_hal_cec.h
  • CEC_IT_BRE : stm32h7xx_hal_cec.h
  • CEC_IT_LBPE : stm32h7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_RXBR : stm32h7xx_hal_cec.h
  • CEC_IT_RXEND : stm32h7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32h7xx_hal_cec.h
  • CEC_IT_SBPE : stm32h7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_TXBR : stm32h7xx_hal_cec.h
  • CEC_IT_TXEND : stm32h7xx_hal_cec.h
  • CEC_IT_TXERR : stm32h7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32h7xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32h7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32h7xx_hal_cec.h
  • CFI1_ADDRESS : stm32h7xx_hal_nor.h
  • CFI2_ADDRESS : stm32h7xx_hal_nor.h
  • CFI3_ADDRESS : stm32h7xx_hal_nor.h
  • CFI4_ADDRESS : stm32h7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CM7_CPUID : stm32h7xx_hal_cortex.h
  • CMD_AREA : stm32h7xx_hal_nand.h
  • COLUMN_1ST_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_2ND_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_ADDRESS : stm32h7xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C1IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C2IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32h7xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32h7xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32h7xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32h7xx_hal_comp.h
  • COMP_EXTI_IT : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32h7xx_hal_comp.h
  • COMP_EXTI_RISING : stm32h7xx_hal_comp.h
  • COMP_FLAG_C1I : stm32h7xx_hal_comp.h
  • COMP_FLAG_C2I : stm32h7xx_hal_comp.h
  • COMP_FLAG_LOCK : stm32h7xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32h7xx_hal_comp.h
  • COMP_HandleTypeDef : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_TPSENS_DAC2CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VBAT_VDDAP : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_DAC2_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_IT_EN : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32h7xx_hal_comp.h
  • CRC_Handle_16() : stm32h7xx_hal_crc.c
  • CRC_Handle_8() : stm32h7xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32h7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32h7xx_hal_crc.h
  • CRYP_AES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_AES_CCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_CTR : stm32h7xx_hal_cryp.h
  • CRYP_AES_Decrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_AES_Encrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_GCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR0_0 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32h7xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32h7xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32h7xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32h7xx_hal_cryp.h
  • CRYP_DES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_DES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_DMAError() : stm32h7xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32h7xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32h7xx_hal_cryp.c
  • CRYP_FLAG_BUSY : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFEM : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFNF : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_INRIS : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFFU : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFNE : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OUTRIS : stm32h7xx_hal_cryp.h
  • CRYP_GCMCCM_SetHeaderPhase() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_HandleTypeDef : stm32h7xx_hal_cryp.h
  • CRYP_IT_INI : stm32h7xx_hal_cryp.h
  • CRYP_IT_OUTI : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_192B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32h7xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_FINAL : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_HEADER : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_INIT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_PAYLOAD : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_PROCESS : stm32h7xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32h7xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32h7xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32h7xx_hal_cryp.c
  • CRYP_SetKey() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_TDES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_TDES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_Process() : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnBUSYFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnIFEMFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnOFNEFlag() : stm32h7xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32h7xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32h7xx_hal_cryp_ex.c
  • CSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CSI_VALUE : stm32h7xx_hal_conf.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32h7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32h7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_BOTH : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_EXTERNAL : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_INTERNAL : stm32h7xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32h7xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32h7xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32h7xx_ll_dac.h
  • DAC_DMAConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_FLAG_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_HandleTypeDef : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32h7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32h7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32h7xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32h7xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32h7xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32h7xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32h7xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM1_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM2_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM3_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32h7xx_hal_dac.h
  • DCMI_BSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_4 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_OTHER : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALL_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_DMAError() : stm32h7xx_hal_dcmi.c
  • DCMI_DMAXferCplt() : stm32h7xx_hal_dcmi.c
  • DCMI_EXTEND_DATA_10B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32h7xx_hal_dcmi.h
  • DCMI_HandleTypeDef : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32h7xx_hal_dcmi.h
  • DCMI_IT_OVR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_MIS_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_CONTINUOUS : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_FALLING : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32h7xx_hal_dcmi.h
  • DCMI_SR_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32h7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32h7xx_hal_crc.h
  • DelayBlock_Configure() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DelayBlock_Disable() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DelayBlock_Enable() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DEVICE_CODE1_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32h7xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM2_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_ADC_OUTPUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_Channel_HandleTypeDef : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CKAB_TIMEOUT : stm32h7xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32h7xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32h7xx_hal_dfsdm.h
  • DFSDM_DMAError() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_COMP1_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_COMP2_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_Filter_HandleTypeDef : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32h7xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_RegConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32h7xx_hal_dfsdm.c
  • DIVIDER_P_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DLCtoBytes : stm32h7xx_hal_fdcan.c
  • DLYB_MAX_SELECT : stm32h7xx_ll_delayblock.h
  • DLYB_MAX_UNIT : stm32h7xx_ll_delayblock.h
  • DLYB_TIMEOUT : stm32h7xx_ll_delayblock.c
  • DMA2D_SetConfig() : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_ABORT : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_SUSPEND : stm32h7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CheckFifoParam() : stm32h7xx_hal_dma.c
  • DMA_CIRCULAR : stm32h7xx_hal_dma.h
  • DMA_DOUBLE_BUFFER_M0 : stm32h7xx_hal_dma.h
  • DMA_DOUBLE_BUFFER_M1 : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_HandleTypeDef : stm32h7xx_hal_dma.h
  • DMA_IT_DME : stm32h7xx_hal_dma.h
  • DMA_IT_FE : stm32h7xx_hal_dma.h
  • DMA_IT_HT : stm32h7xx_hal_dma.h
  • DMA_IT_TC : stm32h7xx_hal_dma.h
  • DMA_IT_TE : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_MultiBufferSetConfig() : stm32h7xx_hal_dma_ex.c
  • DMA_NORMAL : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_PFCTRL : stm32h7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_OUT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI_PSSI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HASH_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_CS : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_DT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART9_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART9_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART10_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART10_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32h7xx_hal_dma.h
  • DMA_SetConfig() : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_DIRECTION : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_IT : stm32h7xx_hal_dma.h
  • DMA_TO_BDMA_MDATA_SIZE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_MEMORY_INC : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_MODE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PDATA_SIZE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PERIPHERAL_INC : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PRIORITY : stm32h7xx_hal_dma.c
  • DMAMUX_CCR_SIZE : stm32h7xx_ll_dmamux.h
  • DMAMUX_CH_STATUS_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_REQ_GEN_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_REQ_GEN_STATUS_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32h7xx_ll_dmamux.h
  • DT_DELAY_1 : stm32h7xx_ll_tim.h
  • DT_DELAY_2 : stm32h7xx_ll_tim.h
  • DT_DELAY_3 : stm32h7xx_ll_tim.h
  • DT_DELAY_4 : stm32h7xx_ll_tim.h
  • DT_RANGE_1 : stm32h7xx_ll_tim.h
  • DT_RANGE_2 : stm32h7xx_ll_tim.h
  • DT_RANGE_3 : stm32h7xx_ll_tim.h
  • DT_RANGE_4 : stm32h7xx_ll_tim.h
  • DTS_DELAY_STARTUP : stm32h7xx_hal_dts.c
  • DTS_ResetCallback() : stm32h7xx_hal_dts.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • eMMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • eMMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • ETH_MAC_ADDR0 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR1 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR2 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR3 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR4 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR5 : stm32h7xx_hal_conf.h
  • ETH_RX_DESC_CNT : stm32h7xx_hal_conf.h
  • ETH_TX_DESC_CNT : stm32h7xx_hal_conf.h
  • EXTERNAL_CLOCK_VALUE : stm32h7xx_hal_conf.h
  • EXTI_CallbackIDTypeDef : stm32h7xx_hal_exti.h
  • EXTI_CONFIG : stm32h7xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32h7xx_hal_exti.c
  • EXTI_D3_PENDCLR_SRC_DMACH6 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_DMACH7 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_LPTIM2 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_LPTIM3 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_NONE : stm32h7xx_hal_exti.h
  • EXTI_DIRECT : stm32h7xx_hal_exti.h
  • EXTI_EVENT : stm32h7xx_hal_exti.h
  • EXTI_EVENT_PRESENCE_MASK : stm32h7xx_hal_exti.h
  • EXTI_EVENT_PRESENCE_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_FALLING_EDGE : stm32h7xx_hal.h
  • EXTI_GPIO : stm32h7xx_hal_exti.h
  • EXTI_GPIOA : stm32h7xx_hal_exti.h
  • EXTI_GPIOB : stm32h7xx_hal_exti.h
  • EXTI_GPIOC : stm32h7xx_hal_exti.h
  • EXTI_GPIOD : stm32h7xx_hal_exti.h
  • EXTI_GPIOE : stm32h7xx_hal_exti.h
  • EXTI_GPIOF : stm32h7xx_hal_exti.h
  • EXTI_GPIOG : stm32h7xx_hal_exti.h
  • EXTI_GPIOH : stm32h7xx_hal_exti.h
  • EXTI_GPIOI : stm32h7xx_hal_exti.h
  • EXTI_GPIOJ : stm32h7xx_hal_exti.h
  • EXTI_GPIOK : stm32h7xx_hal_exti.h
  • EXTI_LINE0 : stm32h7xx_hal.h
  • EXTI_LINE1 : stm32h7xx_hal.h
  • EXTI_LINE10 : stm32h7xx_hal.h
  • EXTI_LINE11 : stm32h7xx_hal.h
  • EXTI_LINE12 : stm32h7xx_hal.h
  • EXTI_LINE13 : stm32h7xx_hal.h
  • EXTI_LINE14 : stm32h7xx_hal.h
  • EXTI_LINE15 : stm32h7xx_hal.h
  • EXTI_LINE16 : stm32h7xx_hal.h
  • EXTI_LINE17 : stm32h7xx_hal.h
  • EXTI_LINE18 : stm32h7xx_hal.h
  • EXTI_LINE19 : stm32h7xx_hal.h
  • EXTI_LINE2 : stm32h7xx_hal.h
  • EXTI_LINE20 : stm32h7xx_hal.h
  • EXTI_LINE21 : stm32h7xx_hal.h
  • EXTI_LINE22 : stm32h7xx_hal.h
  • EXTI_LINE23 : stm32h7xx_hal.h
  • EXTI_LINE24 : stm32h7xx_hal.h
  • EXTI_LINE25 : stm32h7xx_hal.h
  • EXTI_LINE26 : stm32h7xx_hal.h
  • EXTI_LINE27 : stm32h7xx_hal.h
  • EXTI_LINE28 : stm32h7xx_hal.h
  • EXTI_LINE29 : stm32h7xx_hal.h
  • EXTI_LINE3 : stm32h7xx_hal.h
  • EXTI_LINE30 : stm32h7xx_hal.h
  • EXTI_LINE31 : stm32h7xx_hal.h
  • EXTI_LINE32 : stm32h7xx_hal.h
  • EXTI_LINE33 : stm32h7xx_hal.h
  • EXTI_LINE34 : stm32h7xx_hal.h
  • EXTI_LINE35 : stm32h7xx_hal.h
  • EXTI_LINE36 : stm32h7xx_hal.h
  • EXTI_LINE37 : stm32h7xx_hal.h
  • EXTI_LINE38 : stm32h7xx_hal.h
  • EXTI_LINE39 : stm32h7xx_hal.h
  • EXTI_LINE4 : stm32h7xx_hal.h
  • EXTI_LINE40 : stm32h7xx_hal.h
  • EXTI_LINE41 : stm32h7xx_hal.h
  • EXTI_LINE42 : stm32h7xx_hal.h
  • EXTI_LINE43 : stm32h7xx_hal.h
  • EXTI_LINE44 : stm32h7xx_hal.h
  • EXTI_LINE47 : stm32h7xx_hal.h
  • EXTI_LINE48 : stm32h7xx_hal.h
  • EXTI_LINE49 : stm32h7xx_hal.h
  • EXTI_LINE5 : stm32h7xx_hal.h
  • EXTI_LINE50 : stm32h7xx_hal.h
  • EXTI_LINE51 : stm32h7xx_hal.h
  • EXTI_LINE52 : stm32h7xx_hal.h
  • EXTI_LINE53 : stm32h7xx_hal.h
  • EXTI_LINE54 : stm32h7xx_hal.h
  • EXTI_LINE55 : stm32h7xx_hal.h
  • EXTI_LINE56 : stm32h7xx_hal.h
  • EXTI_LINE57 : stm32h7xx_hal.h
  • EXTI_LINE58 : stm32h7xx_hal.h
  • EXTI_LINE59 : stm32h7xx_hal.h
  • EXTI_LINE6 : stm32h7xx_hal.h
  • EXTI_LINE60 : stm32h7xx_hal.h
  • EXTI_LINE61 : stm32h7xx_hal.h
  • EXTI_LINE62 : stm32h7xx_hal.h
  • EXTI_LINE63 : stm32h7xx_hal.h
  • EXTI_LINE64 : stm32h7xx_hal.h
  • EXTI_LINE65 : stm32h7xx_hal.h
  • EXTI_LINE66 : stm32h7xx_hal.h
  • EXTI_LINE67 : stm32h7xx_hal.h
  • EXTI_LINE68 : stm32h7xx_hal.h
  • EXTI_LINE69 : stm32h7xx_hal.h
  • EXTI_LINE7 : stm32h7xx_hal.h
  • EXTI_LINE70 : stm32h7xx_hal.h
  • EXTI_LINE71 : stm32h7xx_hal.h
  • EXTI_LINE72 : stm32h7xx_hal.h
  • EXTI_LINE73 : stm32h7xx_hal.h
  • EXTI_LINE74 : stm32h7xx_hal.h
  • EXTI_LINE75 : stm32h7xx_hal.h
  • EXTI_LINE76 : stm32h7xx_hal.h
  • EXTI_LINE8 : stm32h7xx_hal.h
  • EXTI_LINE85 : stm32h7xx_hal.h
  • EXTI_LINE86 : stm32h7xx_hal.h
  • EXTI_LINE87 : stm32h7xx_hal.h
  • EXTI_LINE88 : stm32h7xx_hal.h
  • EXTI_LINE9 : stm32h7xx_hal.h
  • EXTI_LINE_0 : stm32h7xx_hal_exti.h
  • EXTI_LINE_1 : stm32h7xx_hal_exti.h
  • EXTI_LINE_10 : stm32h7xx_hal_exti.h
  • EXTI_LINE_11 : stm32h7xx_hal_exti.h
  • EXTI_LINE_12 : stm32h7xx_hal_exti.h
  • EXTI_LINE_13 : stm32h7xx_hal_exti.h
  • EXTI_LINE_14 : stm32h7xx_hal_exti.h
  • EXTI_LINE_15 : stm32h7xx_hal_exti.h
  • EXTI_LINE_16 : stm32h7xx_hal_exti.h
  • EXTI_LINE_17 : stm32h7xx_hal_exti.h
  • EXTI_LINE_18 : stm32h7xx_hal_exti.h
  • EXTI_LINE_19 : stm32h7xx_hal_exti.h
  • EXTI_LINE_2 : stm32h7xx_hal_exti.h
  • EXTI_LINE_20 : stm32h7xx_hal_exti.h
  • EXTI_LINE_21 : stm32h7xx_hal_exti.h
  • EXTI_LINE_22 : stm32h7xx_hal_exti.h
  • EXTI_LINE_23 : stm32h7xx_hal_exti.h
  • EXTI_LINE_24 : stm32h7xx_hal_exti.h
  • EXTI_LINE_25 : stm32h7xx_hal_exti.h
  • EXTI_LINE_26 : stm32h7xx_hal_exti.h
  • EXTI_LINE_27 : stm32h7xx_hal_exti.h
  • EXTI_LINE_28 : stm32h7xx_hal_exti.h
  • EXTI_LINE_29 : stm32h7xx_hal_exti.h
  • EXTI_LINE_3 : stm32h7xx_hal_exti.h
  • EXTI_LINE_30 : stm32h7xx_hal_exti.h
  • EXTI_LINE_31 : stm32h7xx_hal_exti.h
  • EXTI_LINE_32 : stm32h7xx_hal_exti.h
  • EXTI_LINE_33 : stm32h7xx_hal_exti.h
  • EXTI_LINE_34 : stm32h7xx_hal_exti.h
  • EXTI_LINE_35 : stm32h7xx_hal_exti.h
  • EXTI_LINE_36 : stm32h7xx_hal_exti.h
  • EXTI_LINE_37 : stm32h7xx_hal_exti.h
  • EXTI_LINE_38 : stm32h7xx_hal_exti.h
  • EXTI_LINE_39 : stm32h7xx_hal_exti.h
  • EXTI_LINE_4 : stm32h7xx_hal_exti.h
  • EXTI_LINE_40 : stm32h7xx_hal_exti.h
  • EXTI_LINE_41 : stm32h7xx_hal_exti.h
  • EXTI_LINE_42 : stm32h7xx_hal_exti.h
  • EXTI_LINE_43 : stm32h7xx_hal_exti.h
  • EXTI_LINE_44 : stm32h7xx_hal_exti.h
  • EXTI_LINE_45 : stm32h7xx_hal_exti.h
  • EXTI_LINE_46 : stm32h7xx_hal_exti.h
  • EXTI_LINE_47 : stm32h7xx_hal_exti.h
  • EXTI_LINE_48 : stm32h7xx_hal_exti.h
  • EXTI_LINE_49 : stm32h7xx_hal_exti.h
  • EXTI_LINE_5 : stm32h7xx_hal_exti.h
  • EXTI_LINE_50 : stm32h7xx_hal_exti.h
  • EXTI_LINE_51 : stm32h7xx_hal_exti.h
  • EXTI_LINE_52 : stm32h7xx_hal_exti.h
  • EXTI_LINE_53 : stm32h7xx_hal_exti.h
  • EXTI_LINE_54 : stm32h7xx_hal_exti.h
  • EXTI_LINE_55 : stm32h7xx_hal_exti.h
  • EXTI_LINE_56 : stm32h7xx_hal_exti.h
  • EXTI_LINE_57 : stm32h7xx_hal_exti.h
  • EXTI_LINE_58 : stm32h7xx_hal_exti.h
  • EXTI_LINE_59 : stm32h7xx_hal_exti.h
  • EXTI_LINE_6 : stm32h7xx_hal_exti.h
  • EXTI_LINE_60 : stm32h7xx_hal_exti.h
  • EXTI_LINE_61 : stm32h7xx_hal_exti.h
  • EXTI_LINE_62 : stm32h7xx_hal_exti.h
  • EXTI_LINE_63 : stm32h7xx_hal_exti.h
  • EXTI_LINE_64 : stm32h7xx_hal_exti.h
  • EXTI_LINE_65 : stm32h7xx_hal_exti.h
  • EXTI_LINE_66 : stm32h7xx_hal_exti.h
  • EXTI_LINE_67 : stm32h7xx_hal_exti.h
  • EXTI_LINE_68 : stm32h7xx_hal_exti.h
  • EXTI_LINE_69 : stm32h7xx_hal_exti.h
  • EXTI_LINE_7 : stm32h7xx_hal_exti.h
  • EXTI_LINE_70 : stm32h7xx_hal_exti.h
  • EXTI_LINE_71 : stm32h7xx_hal_exti.h
  • EXTI_LINE_72 : stm32h7xx_hal_exti.h
  • EXTI_LINE_73 : stm32h7xx_hal_exti.h
  • EXTI_LINE_74 : stm32h7xx_hal_exti.h
  • EXTI_LINE_75 : stm32h7xx_hal_exti.h
  • EXTI_LINE_76 : stm32h7xx_hal_exti.h
  • EXTI_LINE_77 : stm32h7xx_hal_exti.h
  • EXTI_LINE_78 : stm32h7xx_hal_exti.h
  • EXTI_LINE_79 : stm32h7xx_hal_exti.h
  • EXTI_LINE_8 : stm32h7xx_hal_exti.h
  • EXTI_LINE_80 : stm32h7xx_hal_exti.h
  • EXTI_LINE_81 : stm32h7xx_hal_exti.h
  • EXTI_LINE_82 : stm32h7xx_hal_exti.h
  • EXTI_LINE_83 : stm32h7xx_hal_exti.h
  • EXTI_LINE_84 : stm32h7xx_hal_exti.h
  • EXTI_LINE_85 : stm32h7xx_hal_exti.h
  • EXTI_LINE_86 : stm32h7xx_hal_exti.h
  • EXTI_LINE_87 : stm32h7xx_hal_exti.h
  • EXTI_LINE_88 : stm32h7xx_hal_exti.h
  • EXTI_LINE_9 : stm32h7xx_hal_exti.h
  • EXTI_LINE_NB : stm32h7xx_hal_exti.h
  • EXTI_MODE : stm32h7xx_hal_gpio.c
  • EXTI_MODE_EVENT : stm32h7xx_hal_exti.h
  • EXTI_MODE_EVT : stm32h7xx_hal.h
  • EXTI_MODE_INTERRUPT : stm32h7xx_hal_exti.h
  • EXTI_MODE_IT : stm32h7xx_hal.h
  • EXTI_MODE_MASK : stm32h7xx_hal_exti.h
  • EXTI_MODE_NONE : stm32h7xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32h7xx_hal_exti.c
  • EXTI_PIN_MASK : stm32h7xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32h7xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_REG1 : stm32h7xx_hal_exti.h
  • EXTI_REG2 : stm32h7xx_hal_exti.h
  • EXTI_REG3 : stm32h7xx_hal_exti.h
  • EXTI_REG_MASK : stm32h7xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_RESERVED : stm32h7xx_hal_exti.h
  • EXTI_RISING_EDGE : stm32h7xx_hal.h
  • EXTI_TARGET_MASK : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_ALL : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_ALL_CPU : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_CPU1 : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_D3SRD : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_NONE : stm32h7xx_hal_exti.h
  • EXTI_TARGET_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32h7xx_hal_exti.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32h7xx_hal_gpio.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32h7xx_hal_fdcan.h
  • FDCAN_CalcultateRamBlockAddresses() : stm32h7xx_hal_fdcan.c
  • FDCAN_CALIB_CLOCK_PERIOD_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_TIME_QUANTA_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_WATCHDOG_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_BASIC_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_CALIBRATION_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_CALIBRATION_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_NOT_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_PRECISION_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32h7xx_hal_fdcan.h
  • FDCAN_CopyMessageToRAM() : stm32h7xx_hal_fdcan.c
  • FDCAN_DATA_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_EXT_EVT_SYNC_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXBUFFER : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_HandleTypeDef : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32h7xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_MESSAGE_RAM_END_ADDRESS : stm32h7xx_hal_fdcan.c
  • FDCAN_MESSAGE_RAM_SIZE : stm32h7xx_hal_fdcan.c
  • FDCAN_MODE_BUS_MONITORING : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32h7xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER32 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER33 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER34 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER35 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER36 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER37 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER38 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER39 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER40 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER41 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER42 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER43 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER44 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER45 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER46 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER47 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER48 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER49 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER50 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER51 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER52 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER53 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER54 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER55 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER56 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER57 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER58 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER59 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER60 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER61 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER62 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER63 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32h7xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_STRICTLY_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32h7xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_BACKUP_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CURRENT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_DISTURBING_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_END_OF_LIST : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FATAL_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_FLAG_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOBAL_TIME_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_IN_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IN_SCHEDULE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_MASTER_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_SYNC_PULSE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_OUT_OF_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_POTENTIAL_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_NO_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_CYC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_DIABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_GLO_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_LOC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_16TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_2ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_32ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_4TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_64TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_8TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_RX_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SCHEDULE_SYNC_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_SEVERE_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_CYCLE_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_DISABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_LOCAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_MATRIX_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNCHRONIZING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_BASE_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_MARK_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_TIME_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_ARBITRATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_MERGED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_SINGLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32h7xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_BOTH : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_ADDR : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_AddSector() : stm32h7xx_hal_flash_ex.c
  • FLASH_CRC_BANK : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_16 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_256 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_64 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_SelectAddress() : stm32h7xx_hal_flash_ex.c
  • FLASH_CRC_WaitForLastOperation() : stm32h7xx_hal_flash.c
  • FLASH_Erase_Sector() : stm32h7xx_hal_flash_ex.c
  • FLASH_FLAG_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCRDERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCRDERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_10 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_11 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_12 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_13 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_14 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_15 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_8 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_9 : stm32h7xx_hal_flash_ex.h
  • FLASH_MassErase() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BootAddConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAdd() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetSecureArea() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_OTP_GetLock() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_OTP_LockConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_SecureAreaConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_WaitForLastOperation() : stm32h7xx_hal_flash.c
  • FLASH_OPT_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_OTP_BLOCK_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_10 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_11 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_12 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_13 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_14 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_15 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_8 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_9 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_ALL : stm32h7xx_hal_flash_ex.h
  • FLASH_PROC_ALLBANK_MASSERASE : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32h7xx_hal_flash.h
  • FLASH_PROGRAMMING_DELAY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_SECTOR_0 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_1 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_10 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_100 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_101 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_102 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_103 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_104 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_105 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_106 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_107 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_108 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_109 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_11 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_110 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_111 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_112 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_113 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_114 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_115 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_116 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_117 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_118 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_119 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_12 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_120 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_121 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_122 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_123 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_124 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_125 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_126 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_127 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_13 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_14 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_15 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_16 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_17 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_18 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_19 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_2 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_20 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_21 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_22 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_23 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_24 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_25 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_26 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_27 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_28 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_29 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_3 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_30 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_31 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_32 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_33 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_34 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_35 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_36 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_37 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_38 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_39 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_4 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_40 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_41 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_42 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_43 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_44 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_45 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_46 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_47 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_48 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_49 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_5 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_50 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_51 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_52 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_53 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_54 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_55 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_56 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_57 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_58 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_59 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_6 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_60 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_61 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_62 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_63 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_64 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_65 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_66 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_67 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_68 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_69 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_7 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_70 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_71 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_72 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_73 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_74 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_75 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_76 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_77 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_78 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_79 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_8 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_80 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_81 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_82 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_83 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_84 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_85 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_86 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_87 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_88 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_89 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_9 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_90 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_91 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_92 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_93 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_94 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_95 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_96 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_97 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_98 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_99 : stm32h7xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_FLASHWORD : stm32h7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_OTPWORD : stm32h7xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32h7xx_hal_flash.c
  • FLASHSIZE_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • FMC_SWAPBMAP_DISABLE : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAM_SRAM : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAMB2 : stm32h7xx_hal.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GFXMMU_192BLOCKS : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_256BLOCKS : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_AHB_MASTER_ERROR_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER0_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER1_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER2_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER3_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_FLUSH : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_INVALIDATE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER0 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER1 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER2 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER3 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CR_ITS_MASK : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_ERROR_AHB_MASTER : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER0_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER1_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER2_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER3_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_INVALID_CALLBACK : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_NONE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_HandleTypeDef : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUT_LINE_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUT_LINE_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUTXL_FVB_OFFSET : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_LUTXL_LVB_OFFSET : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_OUTTER_BUFFERABILITY_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_BUFFERABILITY_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_CACHABILITY_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_CACHABILITY_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_PREFETCH_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_PREFETCH_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GPIO_AF0_LCDBIAS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_CRS_SYNC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SWP : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART9 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_USART10 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_PSSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM12 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_OCTOSPIM_P2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_PSSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_OCTOSPIM_P2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32h7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32h7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32h7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32h7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32h7xx_hal_gpio.h
  • GPIO_NOPULL : stm32h7xx_hal_gpio.h
  • GPIO_NUMBER : stm32h7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32h7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_All : stm32h7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32h7xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32h7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32h7xx_hal_gpio.h
  • GPIO_PinState : stm32h7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32h7xx_hal_gpio.h
  • GPIO_PULLUP : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32h7xx_hal_adc.c
  • HAL_ADC_CallbackIDTypeDef : stm32h7xx_hal_adc.h
  • HAL_ADC_ConfigChannel() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_ConvHalfCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32h7xx_hal_adc.c
  • HAL_ADC_Init() : stm32h7xx_hal_adc.c
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_IRQHandler() : stm32h7xx_hal_adc.c
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LevelOutOfWindowCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_MSPDEINIT_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_MspInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_MSPINIT_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_PollForConversion() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32h7xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32h7xx_hal_adc.h
  • HAL_ADC_Stop() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32h7xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_FactorLoad() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_CEC_CallbackIDTypeDef : stm32h7xx_hal_cec.h
  • HAL_CEC_ChangeRxBuffer() : stm32h7xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_ERROR_ARBLST : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32h7xx_hal_cec.h
  • HAL_CEC_ErrorCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32h7xx_hal_cec.c
  • HAL_CEC_Init() : stm32h7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32h7xx_hal_cec.c
  • HAL_CEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CEC_MspDeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_MSPDEINIT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_MspInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_MSPINIT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_RegisterCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_RegisterRxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_RX_CPLT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_RxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32h7xx_hal_cec.c
  • HAL_CEC_STATE_BUSY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32h7xx_hal_cec.h
  • HAL_CEC_StateTypeDef : stm32h7xx_hal_cec.h
  • HAL_CEC_Transmit_IT() : stm32h7xx_hal_cec.c
  • HAL_CEC_TX_CPLT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_TxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_UnRegisterCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_UnRegisterRxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_COMP_CallbackIDTypeDef : stm32h7xx_hal_comp.h
  • HAL_COMP_DeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32h7xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32h7xx_hal_comp.h
  • HAL_COMP_GetError() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetState() : stm32h7xx_hal_comp.c
  • HAL_COMP_Init() : stm32h7xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32h7xx_hal_comp.c
  • HAL_COMP_Lock() : stm32h7xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_MSPDEINIT_CB_ID : stm32h7xx_hal_comp.h
  • HAL_COMP_MspInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_MSPINIT_CB_ID : stm32h7xx_hal_comp.h
  • HAL_COMP_RegisterCallback() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32h7xx_hal_comp.h
  • HAL_COMP_Stop() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_TRIGGER_CB_ID : stm32h7xx_hal_comp.h
  • HAL_COMP_TriggerCallback() : stm32h7xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32h7xx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32h7xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32h7xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32h7xx_hal_crc.c
  • HAL_CRC_GetState() : stm32h7xx_hal_crc.c
  • HAL_CRC_Init() : stm32h7xx_hal_crc.c
  • HAL_CRC_Input_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32h7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32h7xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32h7xx_hal_crc.c
  • HAL_CRC_Output_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32h7xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32h7xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32h7xx_hal_crc_ex.c
  • HAL_CRYP_CallbackIDTypeDef : stm32h7xx_hal_cryp.h
  • HAL_CRYP_Decrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ErrorCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_FIFO_FLUSH : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_IRQHandler() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRYP_MspDeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_MspInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MSPINIT_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_OutCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_RegisterCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_STATE_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32h7xx_hal_cryp.h
  • HAL_CRYP_UnRegisterCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_DAC_ALL_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CallbackIDTypeDef : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_ConfigChannel() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetError() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Init() : stm32h7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32h7xx_hal_dac.c
  • HAL_DAC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_MSPDEINIT_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_MspInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_MSPINIT_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_RegisterCallback() : stm32h7xx_hal_dac.c , stm32h7xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32h7xx_hal_dac.h
  • HAL_DAC_Stop() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32h7xx_hal_dac.c , stm32h7xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStart_DMA() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStop_DMA() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DCMI_CallbackIDTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ConfigCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DisableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_EnableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_ERROR_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_DMA : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_NONE : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ErrorCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_FRAME_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_FrameEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_IRQHandler() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_LINE_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_LineEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DCMI_MspDeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MSPDEINIT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_MspInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MSPINIT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_RegisterCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Resume() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_STATE_BUSY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_SUSPENDED : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_StateTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_Stop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Suspend() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_UnRegisterCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_VSYNC_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_VsyncEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DeInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_Delay() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DFDSMEx_ChannelGetPulsesSkipping() : stm32h7xx_hal_dfsdm_ex.c
  • HAL_DFDSMEx_ChannelSetPulsesSkipping() : stm32h7xx_hal_dfsdm_ex.c
  • HAL_DFSDM_Channel_CallbackIDTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_CKAB_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_RegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_CHANNEL_SCD_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_UnRegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_CallbackIDTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_ERROR_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_MSPINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_RegisterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_RegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_UnRegisterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_UnRegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DisableCompensationCell() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDBGSleepMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDomain3DBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDomain3DBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DMA2D_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoadingCpltCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigLayer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DisableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetError() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetState() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Init() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_IRQHandler() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_LineEventCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA2D_MspDeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_PollForTransfer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ProgramLineEvent() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_RegisterCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_UnRegisterCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA_Abort() : stm32h7xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32h7xx_hal_dma.c
  • HAL_DMA_ERROR_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_DME : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32h7xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_GetError() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32h7xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_Init() : stm32h7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32h7xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32h7xx_hal_dma_ex.h
  • HAL_DMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32h7xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_STATE_ABORT : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32h7xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMAEx_ChangeMemory() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_COMP2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_SPI6_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DSI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DTS_AsyncEndCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_AsyncHighCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_AsyncLowCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_DeInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_EndCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_GetState() : stm32h7xx_hal_dts.c
  • HAL_DTS_GetTemperature() : stm32h7xx_hal_dts.c
  • HAL_DTS_HighCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_Init() : stm32h7xx_hal_dts.c
  • HAL_DTS_IRQHandler() : stm32h7xx_hal_dts.c
  • HAL_DTS_LowCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DTS_MspDeInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_MspInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_Start() : stm32h7xx_hal_dts.c
  • HAL_DTS_Start_IT() : stm32h7xx_hal_dts.c
  • HAL_DTS_Stop() : stm32h7xx_hal_dts.c
  • HAL_DTS_Stop_IT() : stm32h7xx_hal_dts.c
  • HAL_EnableCompensationCell() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGSleepMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDomain3DBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDomain3DBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_ETH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_EXTI_ClearConfigLine() : stm32h7xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32h7xx_hal_exti.c
  • HAL_EXTI_COMMON_CB_ID : stm32h7xx_hal_exti.h
  • HAL_EXTI_D1_ClearFlag() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_D1_EventInputConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_D3_EventInputConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_EdgeConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_GenerateSWI() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GenerateSWInterrupt() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_GetConfigLine() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32h7xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32h7xx_hal_exti.c
  • HAL_EXTI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_EXTI_RegisterCallback() : stm32h7xx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32h7xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_CallbackIDTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigClockCalibration() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFifoWatermark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxBufferRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_APPL_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_CONFIG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_INIT_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE1 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE2 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ErrorCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRxBufferMessageAvailable() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FDCAN_MspDeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_MspInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MSPINIT_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_RegisterCallback() : stm32h7xx_hal_fdcan.c , stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_RegisterClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTGlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTStopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTTimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_RxBufferNewMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_STATE_BUSY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_Stop() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigExternalSyncPhase() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigOperation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigReferenceMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigRegisterTimeMark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigStopWatch() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigTrigger() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GetOperationStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetClockSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetEndOfGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetGlobalTime() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetNextIsGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_StopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_TimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTGlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTStopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTTimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32h7xx_hal_flash.c
  • HAL_FLASH_ERROR_CRCRD : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_CRCRD_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_CRCRD_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OB_CHANGE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32h7xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Program() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32h7xx_hal_flash.c
  • HAL_FLASHEx_ComputeCRC() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Lock_Bank1() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Lock_Bank2() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Unlock_Bank1() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Unlock_Bank2() : stm32h7xx_hal_flash_ex.c
  • HAL_GetCurrentCPUID() : stm32h7xx_hal_cortex.c
  • HAL_GetDEVID() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetFMCMemorySwappingConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetHalVersion() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetREVID() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTickFreq() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTickPrio() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw0() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw1() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw2() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GFXMMU_CallbackIDTypeDef : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_ConfigForceCache() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ConfigLut() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ConfigLutLine() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_DeInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_DisableLutLines() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ERROR_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_ErrorCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_GetError() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_GetState() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_Init() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_IRQHandler() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ModifyBuffers() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ModifyCachePrefetch() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GFXMMU_MspDeInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_MSPDEINIT_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_MspInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_MSPINIT_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_RegisterCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_STATE_READY : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_STATE_RESET : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_StateTypeDef : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_UnRegisterCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GPIO_DeInit() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32h7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32h7xx_hal_uart.c
  • HAL_HASH_CallbackIDTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_ContextRestoring() : stm32h7xx_hal_hash.c
  • HAL_HASH_ContextSaving() : stm32h7xx_hal_hash.c
  • HAL_HASH_DeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_DGSTCPLT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_DgstCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_DMAFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_ERROR_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_DMA : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_INVALID_CALLBACK : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_IT : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_NONE : stm32h7xx_hal_hash.h
  • HAL_HASH_ErrorCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetError() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetState() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetStatus() : stm32h7xx_hal_hash.c
  • HAL_HASH_InCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_Init() : stm32h7xx_hal_hash.c
  • HAL_HASH_INPUTCPLT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_IRQHandler() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASH_MspDeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_MSPDEINIT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_MspInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_MSPINIT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_1 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_2 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_3 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_PROCESS : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_PhaseTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_RegisterCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_STATE_BUSY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_ERROR : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_RESET : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_SUSPENDED : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_TIMEOUT : stm32h7xx_hal_hash.h
  • HAL_HASH_StateTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND_NONE : stm32h7xx_hal_hash.h
  • HAL_HASH_SuspendTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SwFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_UnRegisterCallback() : stm32h7xx_hal_hash.c
  • HAL_HASHEx_IRQHandler : stm32h7xx_hal_hash.h
  • HAL_HASHEx_SHA224_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HCD_CallbackIDTypeDef : stm32h7xx_hal_hcd.h
  • HAL_HCD_Connect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_CONNECT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_DeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_DISCONNECT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_hcd.h
  • HAL_HCD_GetCurrentFrame() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HCD_MspDeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MSPDEINIT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_MspInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MSPINIT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_PORT_DISABLED_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_PORT_ENABLED_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_PortDisabled_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_PortEnabled_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_RegisterCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_RegisterHC_NotifyURBChangeCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_ResetPort() : stm32h7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_SOF_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_Start() : stm32h7xx_hal_hcd.c
  • HAL_HCD_STATE_BUSY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32h7xx_hal_hcd.h
  • HAL_HCD_Stop() : stm32h7xx_hal_hcd.c
  • HAL_HCD_UnRegisterCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_UnRegisterHC_NotifyURBChangeCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HMAC_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMACEx_MD5_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HRTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HSEM_ActivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HSEM_Release() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Take() : stm32h7xx_hal_hsem.c
  • HAL_I2C_ABORT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_AbortCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_CallbackIDTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_DeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32h7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32h7xx_hal_i2c.c
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_ListenCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MasterRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_Mem_Write() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MSPDEINIT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MspInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MSPINIT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_RegisterAddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_SlaveRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_UnRegisterAddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2S_CallbackIDTypeDef : stm32h7xx_hal_i2s.h
  • HAL_I2S_DeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32h7xx_hal_i2s.c
  • HAL_I2S_ERROR_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_DMA : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NO_OGT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NOT_SUPPORTED : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32h7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MSPDEINIT_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_MspInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MSPINIT_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_Receive() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_RxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32h7xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_TxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32h7xx_hal_i2s.c
  • HAL_IncTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_Init() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_InitTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_IRDA_Abort() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_Abort_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_AbortCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_CallbackIDTypeDef : stm32h7xx_hal_irda.h
  • HAL_IRDA_DeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32h7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_MspInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MSPINIT_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_Receive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_RxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32h7xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32h7xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_TxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32h7xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32h7xx_hal_iwdg.c
  • HAL_JPEG_Abort() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_CallbackIDTypeDef : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ConfigEncoding() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigInputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigOutputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DECODE_CPLT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_Decode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DecodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DisableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EnableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ENCODE_CPLT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_Encode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EncodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ERROR_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_DMA : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_HUFF_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_INVALID_CALLBACK : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_NONE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_QUANT_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ErrorCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetError() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetInfo() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetState() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_InfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Init() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_IRQHandler() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_JPEG_MspDeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MSPDEINIT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_MspInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MSPINIT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_Pause() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterDataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterGetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterInfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Resume() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_SetUserQuantTables() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_STATE_BUSY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_DECODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_ENCODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_ERROR : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_READY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_RESET : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATETypeDef : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_UnRegisterCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterDataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterGetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterInfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_LIN_Init() : stm32h7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32h7xx_hal_uart.c
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_CallbackIDTypeDef : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_MSPINIT_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_STATE_BUSY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TRIGGER_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32h7xx_hal_lptim.c
  • HAL_LTDC_CallbackIDTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ConfigCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ERROR_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_FU : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_NONE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ErrorCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_GetError() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_GetState() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Init() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_IRQHandler() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_LINE_EVENT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_LineEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LTDC_MspDeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_MSPDEINIT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MspInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_MSPINIT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ProgramLineEvent() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_RegisterCallback() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Reload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_RELOAD_EVENT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ReloadEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_SetAddress() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAddress_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_STATE_BUSY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_ERROR : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_READY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_RESET : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_StateTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_UnRegisterCallback() : stm32h7xx_hal_ltdc.c
  • HAL_MDIOS_CallbackIDTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ClearReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ClearWriteRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_DeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_EnableEvents() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ERROR_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_DATA : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_INVALID_CALLBACK : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_NONE : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_PARAM : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_TIMEOUT : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ErrorCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetError() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetState() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetWrittenRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_Init() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_IRQHandler() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDIOS_MspDeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MSPDEINIT_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_MspInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MSPINIT_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_READ_COMPLETE_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ReadCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadReg() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_RegisterCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_STATE_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_ERROR : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_READY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_RESET : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_StateTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_UnRegisterCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WAKEUP_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_WakeUpCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WRITE_COMPLETE_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_WriteCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteReg() : stm32h7xx_hal_mdios.c
  • HAL_MDMA_Abort() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Abort_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_CallbackIDTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_CHANNEL_SIZE : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ConfigPostRequestMask() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_DeInit() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ERROR_ALIGNMENT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BLOCK_SIZE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_LINKED_LIST : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_MASK_DATA : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NO_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NONE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_READ_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_TIMEOUT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_WRITE_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_GenerateSWRequest() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetError() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetState() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Init() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_IRQHandler() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LevelCompleteTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_LinkedList_AddNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_CreateNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_DisableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_EnableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_RemoveNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDMA_PollForTransfer() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_RegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_Start() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_STATE_ABORT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ERROR : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_READY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_RESET : stm32h7xx_hal_mdma.h
  • HAL_MDMA_StateTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_UnRegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_XFER_ABORT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ALL_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BUFFERCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_CPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ERROR_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MMC_Abort() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_ABORT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_Abort_IT() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_AbortCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_CallbackIDTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_DISCONNECTED : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_IDENTIFICATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_SENDING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_STANDBY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_CardStateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMC_ConfigSpeedBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ConfigWideBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_DeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_Erase() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CC_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_COM_CRC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DMA : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ILLEGAL_CMD : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_NONE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_RX_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TX_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_ErrorCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_GetCardCID() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardCSD() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardInfo() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetError() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Init() : stm32h7xx_hal_mmc.c
  • HAL_MMC_InitCard() : stm32h7xx_hal_mmc.c
  • HAL_MMC_IRQHandler() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MMC_MSP_DEINIT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_MSP_INIT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_MspDeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_ReadBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RegisterCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RX_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_RxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_STATE_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_StateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMC_TX_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_TxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_UnRegisterCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_WriteBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMCEx_ChangeDMABuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32h7xx_hal_cortex.c
  • HAL_MspDeInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_MspInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_MultiProcessor_DisableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32h7xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32h7xx_hal_nand.c
  • HAL_NAND_CallbackIDTypeDef : stm32h7xx_hal_nand.h
  • HAL_NAND_ConfigDevice() : stm32h7xx_hal_nand.c , stm32h7xx_hal_nand.h
  • HAL_NAND_DeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32h7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32h7xx_hal_nand.c
  • HAL_NAND_Init() : stm32h7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32h7xx_hal_nand.c
  • HAL_NAND_IT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_ITCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NAND_MSP_DEINIT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_MSP_INIT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_MspDeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32h7xx_hal_nand.c , stm32h7xx_hal_nand.h
  • HAL_NAND_Read_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32h7xx_hal_nand.c
  • HAL_NAND_RegisterCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_Reset() : stm32h7xx_hal_nand.c
  • HAL_NAND_STATE_BUSY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32h7xx_hal_nand.h
  • HAL_NAND_StateTypeDef : stm32h7xx_hal_nand.h
  • HAL_NAND_UnRegisterCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NOR_CallbackIDTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_DeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32h7xx_hal_nor.c
  • HAL_NOR_Init() : stm32h7xx_hal_nor.c
  • HAL_NOR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NOR_MSP_DEINIT_CB_ID : stm32h7xx_hal_nor.h
  • HAL_NOR_MSP_INIT_CB_ID : stm32h7xx_hal_nor.h
  • HAL_NOR_MspDeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32h7xx_hal_nor.c
  • HAL_NOR_Program() : stm32h7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_RegisterCallback() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32h7xx_hal_nor.c
  • HAL_NOR_STATE_BUSY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32h7xx_hal_nor.h
  • HAL_NOR_StateTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32h7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_UnRegisterCallback() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Disable() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32h7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32h7xx_hal_cortex.c
  • HAL_OPAMP_ALL_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_CallbackIDTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_DeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OPAMP_MspDeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MSPDEINIT_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_MspInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MSPINIT_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_RegisterCallback() : stm32h7xx_hal_opamp.c , stm32h7xx_hal_opamp.h
  • HAL_OPAMP_SelfCalibrate() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_STATE_BUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_Stop() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_TrimmingValueTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_UnRegisterCallback() : stm32h7xx_hal_opamp.c , stm32h7xx_hal_opamp.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32h7xx_hal_opamp_ex.c , stm32h7xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32h7xx_hal_opamp_ex.c
  • HAL_OSPI_Abort() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_ABORT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_Abort_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_AbortCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_ADDRESS_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_AUTOMATIC_STOP_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_AUTOMATIC_STOP_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_AutoPolling() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_AutoPolling_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_CallbackIDTypeDef : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CLOCK_MODE_0 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CLOCK_MODE_3 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CMD_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CmdCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Command() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Command_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_DATA_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DeInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_DELAY_BLOCK_BYPASSED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DELAY_BLOCK_USED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DHQC_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DHQC_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DQS_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DQS_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DUALQUAD_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DUALQUAD_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_DMA : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_PARAM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_SEQUENCE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_TIMEOUT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_TRANSFER : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ErrorCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_FIFO_THRESHOLD_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FifoThresholdCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_FIXED_LATENCY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_BUSY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_FT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_SM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TC : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TO : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLASH_ID_1 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLASH_ID_2 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FREERUNCLK_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FREERUNCLK_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_GetError() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_GetFifoThreshold() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_GetState() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_HyperbusCfg() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_HyperbusCmd() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Init() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_INSTRUCTION_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IRQHandler() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_IT_FT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_SM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TC : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TO : stm32h7xx_hal_ospi.h
  • HAL_OSPI_LATENCY_ON_WRITE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MATCH_MODE_AND : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MATCH_MODE_OR : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMORY_ADDRESS_SPACE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MemoryMapped() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_MEMTYPE_APMEMORY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_HYPERBUS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MACRONIX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MACRONIX_RAM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MICRON : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OSPI_MSP_DEINIT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MSP_INIT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MspDeInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_MspInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_NO_LATENCY_ON_WRITE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_COMMON_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_READ_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_WRAP_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_WRITE_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_Receive() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Receive_DMA() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Receive_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_REGISTER_ADDRESS_SPACE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_RegisterCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_RX_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_RX_HALF_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_RxCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_RxHalfCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SAMPLE_SHIFTING_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SetFifoThreshold() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_SetTimeout() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_SIOO_INST_EVERY_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_ABORT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_AUTO_POLLING : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_MEM_MAPPED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_RX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_TX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_ERROR : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_HYPERBUS_INIT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_READ_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_READY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_RESET : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_WRITE_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATUS_MATCH_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_StatusMatchCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TIMEOUT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_COUNTER_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_COUNTER_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_DEFAULT_VALUE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TimeOutCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit_DMA() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TX_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TX_HALF_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TxCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TxHalfCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_UnRegisterCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_VARIABLE_LATENCY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_128_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_16_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_32_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_64_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_NOT_SUPPORTED : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_Config() : stm32h7xx_hal_ospi.c
  • HAL_OSPIM_IOPORT_1_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_1_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_2_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_2_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_3_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_3_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_4_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_4_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_5_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_5_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_6_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_6_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_7_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_7_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_8_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_8_LOW : stm32h7xx_hal_ospi.h
  • HAL_OTFDEC_DeInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_ErrorCallback() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_GetState() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_Init() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_IRQHandler() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_KeyCRCComputation() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OTFDEC_MspDeInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_MspInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionConfig() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionDisable() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionEnable() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionGetConfig() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionGetKeyCRC() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionKeyLock() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionSetKey() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionSetMode() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegisterCallback() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_UnRegisterCallback() : stm32h7xx_hal_otfdec.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_CallbackIDTypeDef : stm32h7xx_hal_pcd.h
  • HAL_PCD_CONNECT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DISCONNECT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_DisconnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_pcd.h
  • HAL_PCD_GetState() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32h7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MSPDEINIT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_MspInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MSPINIT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_RegisterBcdCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RESET_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_ResetCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RESUME_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_ResumeCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_SetupStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SOF_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_SOFCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32h7xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32h7xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SUSPEND_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_SuspendCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PSSI_16BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_16LINES : stm32h7xx_hal_pssi.h
  • HAL_PSSI_32BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_8BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_8LINES : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ABORT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_Abort_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_AbortCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_BIDIRECTIONAL : stm32h7xx_hal_pssi.h
  • HAL_PSSI_CallbackIDTypeDef : stm32h7xx_hal_pssi.h
  • HAL_PSSI_CLEAR_FLAG : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_MAP_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_RDY_ALT_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_RDY_DISABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DeInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_DEPOL_ACTIVE_HIGH : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DEPOL_ACTIVE_LOW : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DISABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DISABLE_IT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ENABLE_IT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_DMA : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_NONE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_NOT_SUPPORTED : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_OVER_RUN : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_TIMEOUT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_UNDER_RUN : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ErrorCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_FALLING_EDGE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_FLAG : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_IT_SOURCE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_STATUS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GetError() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_GetState() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Init() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_IRQHandler() : stm32h7xx_hal_pssi.c , stm32h7xx_hal_pssi.h
  • HAL_PSSI_MAP_DE_BIDIR_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MAP_RDY_BIDIR_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PSSI_MspDeInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_MSPDEINIT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MspInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_MSPINIT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDY_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDY_MAP_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDYPOL_ACTIVE_HIGH : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDYPOL_ACTIVE_LOW : stm32h7xx_hal_pssi.h
  • HAL_PSSI_Receive() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Receive_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_RegisterCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_RESET_HANDLE_STATE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RISING_EDGE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RX_COMPLETE_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RxCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_STATE_ABORT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY_RX : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY_TX : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_ERROR : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_READY : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_RESET : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_TIMEOUT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_StateTypeDef : stm32h7xx_hal_pssi.h
  • HAL_PSSI_Transmit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Transmit_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_TX_COMPLETE_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_TxCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_UNIDIRECTIONAL : stm32h7xx_hal_pssi.h
  • HAL_PSSI_UnRegisterCallback() : stm32h7xx_hal_pssi.c
  • HAL_PWR_ConfigPVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32h7xx_hal_pwr.c , stm32h7xx_hal_pwr.h
  • HAL_PWR_PVDCallback() : stm32h7xx_hal_pwr.c , stm32h7xx_hal_pwr.h
  • HAL_PWREx_AVDCallback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearPendingEvent() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigD3Domain() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSupply() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlStopModeVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAnalogBooster() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMemoryShutOff() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAnalogBooster() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMemoryShutOff() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTANDBYMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOPMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetMMCVoltage() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetStopModeVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetSupplyConfig() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetTemperatureLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVBATLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_AVD_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WAKEUP_PIN_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP1_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP2_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP3_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP4_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP5_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP6_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_QSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RAMECC_DeInit() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_DisableNotification() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_EnableNotification() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_ERROR_BUSY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_NONE : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_TIMEOUT : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_GetError() : stm32h7xx_hal_ramecc.c , stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_GetFailingAddress() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetFailingDataHigh() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetFailingDataLow() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetHammingErrorCode() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetState() : stm32h7xx_hal_ramecc.c , stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_Init() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IRQHandler() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IsECCDoubleErrorDetected() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IsECCSingleErrorDetected() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RAMECC_RegisterCallback() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_StartMonitor() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_STATE_BUSY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_ERROR : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_READY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_RESET : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_StateTypeDef : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_StopMonitor() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_UnRegisterCallback() : stm32h7xx_hal_ramecc.c
  • HAL_RCC_CCSCallback() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_ClockConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_EnableCSS() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetClockConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetHCLKFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetOscConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK1Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK2Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetSysClockFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MCOConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1SysClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD3PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL1ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL2ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL3ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_KerWakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_RNG_CallbackIDTypeDef : stm32h7xx_hal_rng.h
  • HAL_RNG_DeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ERROR_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RNG_ErrorCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetError() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32h7xx_hal_rng.c
  • HAL_RNG_Init() : stm32h7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32h7xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_MSPDEINIT_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_MspInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_MSPINIT_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_ReadLastRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32h7xx_hal_rng.h
  • HAL_RNG_UnRegisterCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNGEx_GetConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RNGEx_LockConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RNGEx_SetConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RS485Ex_Init() : stm32h7xx_hal_uart_ex.c
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_AlarmAEventCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32h7xx_hal_rtc.c
  • HAL_RTC_CallbackIDTypeDef : stm32h7xx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_Init() : stm32h7xx_hal_rtc.c
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MSPDEINIT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MSPINIT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_PollForAlarmAEvent() : stm32h7xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_UnRegisterCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32h7xx_hal_rtc.c
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateActiveTampers() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper8EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_MonotonicCounterGet() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_MonotonicCounterIncrement() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetActiveSeed() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetActiveTampers() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32h7xx_hal_rtc.h
  • HAL_SAI_Abort() : stm32h7xx_hal_sai.c
  • HAL_SAI_CallbackIDTypeDef : stm32h7xx_hal_sai.h
  • HAL_SAI_DeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32h7xx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32h7xx_hal_sai.c
  • HAL_SAI_Init() : stm32h7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32h7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32h7xx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_MSPDEINIT_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_MspInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_MSPINIT_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_Receive() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_RxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32h7xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32h7xx_hal_sai.h
  • HAL_SAI_Transmit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_TxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32h7xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32h7xx_hal_sai_ex.c
  • HAL_SD_Abort() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_ABORT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_Abort_IT() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_AbortCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_CallbackIDTypeDef : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_DISCONNECTED : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_IDENTIFICATION : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_READY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_SENDING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_STANDBY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_CardStateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SD_ConfigSpeedBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_ConfigWideBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_DriveTransceiver_1_8V_Callback() : stm32h7xx_hal_sd.c
  • HAL_SD_Erase() : stm32h7xx_hal_sd.c
  • HAL_SD_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CC_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_COM_CRC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DMA : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ILLEGAL_CMD : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_NONE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_RX_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TX_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_sd.h
  • HAL_SD_ErrorCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCID() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardCSD() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardInfo() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardState() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardStatus() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetError() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetState() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Init() : stm32h7xx_hal_sd.c
  • HAL_SD_InitCard() : stm32h7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32h7xx_hal_sd.c
  • HAL_SD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SD_MSP_DEINIT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_MSP_INIT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_MspDeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32h7xx_hal_sd.c
  • HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_ReadBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SD_RegisterCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_RegisterTransceiverCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_RX_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_RxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_STATE_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_READY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_StateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SD_TX_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_TxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_UnRegisterCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_UnRegisterTransceiverCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_WriteBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SDEx_ChangeDMABuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDRAM_CallbackIDTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_DeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_DMA_XFER_ERR_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SDRAM_MSP_DEINIT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_MSP_INIT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_MspDeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_REFRESH_ERR_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_RefreshErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RegisterCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RegisterDmaCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_STATE_BUSY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_StateTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_UnRegisterCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32h7xx_hal_sdram.c
  • HAL_SetFMCMemorySwappingConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SetTickFreq() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SMARTCARD_Abort() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_Abort_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_AbortCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_DeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_DMA : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_MspInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_Receive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_TxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_CallbackIDTypeDef : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ConfigAnalogFilter() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MspInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MSPINIT_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_RegisterAddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32h7xx_hal_smbus.c
  • HAL_SPDIFRX_CallbackIDTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_CX_CPLT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_CX_HALF_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_CxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ERROR_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_DMA : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_INVALID_CALLBACK : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ErrorCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPDIFRX_MspDeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MSPDEINIT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MspInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MSPINIT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ReceiveCtrlFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveCtrlFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveCtrlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RegisterCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RX_CPLT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_RX_HALF_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_RxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_STATE_BUSY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_StateTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_UnRegisterCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPI_Abort() : stm32h7xx_hal_spi.c
  • HAL_SPI_ABORT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_Abort_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_CallbackIDTypeDef : stm32h7xx_hal_spi.h
  • HAL_SPI_DeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32h7xx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NOT_SUPPORTED : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_TIMEOUT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UDR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32h7xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32h7xx_hal_spi.c
  • HAL_SPI_Init() : stm32h7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32h7xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_MSPDEINIT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_MspInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_MSPINIT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_Receive() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_RxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32h7xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32h7xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32h7xx_hal_spi.c
  • HAL_SPIEx_ConfigureUnderrun() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_EnableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_FlushRxFifo() : stm32h7xx_hal_spi_ex.c
  • HAL_SRAM_CallbackIDTypeDef : stm32h7xx_hal_sram.h
  • HAL_SRAM_DeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_DMA_XFER_ERR_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sram.h , stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sram.h , stm32h7xx_hal_sram.c
  • HAL_SRAM_GetState() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SRAM_MSP_DEINIT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_MSP_INIT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_MspDeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_RegisterCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_RegisterDmaCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_STATE_BUSY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32h7xx_hal_sram.h
  • HAL_SRAM_StateTypeDef : stm32h7xx_hal_sram.h
  • HAL_SRAM_UnRegisterCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32h7xx_hal_sram.c
  • HAL_SuspendTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SWPMI_CallbackIDTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_DeInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_DisableLoopback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_DMAStop() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_EnableLoopback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_CRC : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TXBEF_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ErrorCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_GetError() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_GetState() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Init() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_IRQHandler() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SWPMI_MspDeInit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MSPDEINIT_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MspInit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MSPINIT_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive_DMA() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RegisterCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_RX_COMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RxCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_RxHalfCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_STATE_BUSY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_StateTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Transmit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_DMA() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_TX_COMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TxCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_TxHalfCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_UnRegisterCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SYSCFG_AnalogSwitchConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_CompensationCodeConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_CompensationCodeSelect() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_DisableIOSpeedOptimize() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_EnableIOSpeedOptimize() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_VDDMMC_CompensationCodeConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSTICK_Callback() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32h7xx_hal_cortex.c
  • HAL_TICK_FREQ_100HZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32h7xx_hal.h
  • HAL_TickFreqTypeDef : stm32h7xx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32h7xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32h7xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_Base_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_Base_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_BREAK2_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32h7xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ConfigClockSource() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_Encoder_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_Encoder_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ERROR_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ErrorCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32h7xx_hal_tim.c
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_CaptureCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32h7xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_DelayElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OnePulse_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PeriodElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32h7xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32h7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32h7xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32h7xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DCMI_STOP : stm32h7xx_hal_dcmi.c
  • HAL_TIMEOUT_DIR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DMA_ABORT : stm32h7xx_hal_dma.c
  • HAL_TIMEOUT_MDMA_ABORT : stm32h7xx_hal_mdma.c
  • HAL_TIMEOUT_RXNE : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32h7xx_hal_smbus.c
  • HAL_TIMEx_Break2Callback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32h7xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32h7xx_hal_uart.c
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_Abort_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_AbortCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_CallbackIDTypeDef : stm32h7xx_hal_uart.h
  • HAL_UART_DeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32h7xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32h7xx_hal_uart.c
  • HAL_UART_ERROR_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32h7xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_GetError() : stm32h7xx_hal_uart.c
  • HAL_UART_GetState() : stm32h7xx_hal_uart.c
  • HAL_UART_Init() : stm32h7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32h7xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_MSPDEINIT_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_MspInit() : stm32h7xx_hal_uart.c
  • HAL_UART_MSPINIT_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_Receive() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32h7xx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RX_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32h7xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32h7xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • HAL_UART_Transmit() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_TX_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_WAKEUP_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UARTEx_DisableFifoMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32h7xx_hal_usart.c
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_Abort_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_CallbackIDTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_DeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32h7xx_hal_usart.c
  • HAL_USART_ERROR_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_DMA : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32h7xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_GetError() : stm32h7xx_hal_usart.c
  • HAL_USART_GetState() : stm32h7xx_hal_usart.c
  • HAL_USART_Init() : stm32h7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32h7xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_MSPDEINIT_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_MspInit() : stm32h7xx_hal_usart.c
  • HAL_USART_MSPINIT_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_Receive() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32h7xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_Transmit() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32h7xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32h7xx_hal_usart_ex.c
  • HAL_WWDG_CallbackIDTypeDef : stm32h7xx_hal_wwdg.h
  • HAL_WWDG_EarlyWakeupCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_EWI_CB_ID : stm32h7xx_hal_wwdg.h
  • HAL_WWDG_Init() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_MSPINIT_CB_ID : stm32h7xx_hal_wwdg.h
  • HAL_WWDG_Refresh() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32h7xx_hal_wwdg.c
  • HASH_Accumulate() : stm32h7xx_hal_hash.c
  • HASH_ALGOMODE_HASH : stm32h7xx_hal_hash.h
  • HASH_ALGOMODE_HMAC : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_MD5 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA1 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA224 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA256 : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_16B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_1B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_32B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_8B : stm32h7xx_hal_hash.h
  • HASH_DIGEST_CALCULATION_NOT_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_CALCULATION_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_LENGTH : stm32h7xx_hal_hash.h
  • HASH_DMA_SUSPENSION_WORDS_LIMIT : stm32h7xx_hal_hash.c
  • HASH_DMAError() : stm32h7xx_hal_hash.c
  • HASH_DMAXferCplt() : stm32h7xx_hal_hash.c
  • HASH_Finish() : stm32h7xx_hal_hash.c
  • HASH_FLAG_BUSY : stm32h7xx_hal_hash.h
  • HASH_FLAG_DCIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINNE : stm32h7xx_hal_hash.h
  • HASH_FLAG_DMAS : stm32h7xx_hal_hash.h
  • HASH_GetDigest() : stm32h7xx_hal_hash.c
  • HASH_HandleTypeDef : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_LONGKEY : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_SHORTKEY : stm32h7xx_hal_hash.h
  • HASH_IT() : stm32h7xx_hal_hash.c
  • HASH_IT_DCI : stm32h7xx_hal_hash.h
  • HASH_IT_DINI : stm32h7xx_hal_hash.h
  • HASH_NBW_PUSHED : stm32h7xx_hal_hash.h
  • HASH_NUMBER_OF_CSR_REGISTERS : stm32h7xx_hal_hash.c
  • HASH_Start() : stm32h7xx_hal_hash.c
  • HASH_Start_DMA() : stm32h7xx_hal_hash.c
  • HASH_Start_IT() : stm32h7xx_hal_hash.c
  • HASH_TIMEOUTVALUE : stm32h7xx_hal_hash.c
  • HASH_WaitOnFlagUntilTimeout() : stm32h7xx_hal_hash.c
  • HASH_Write_Block_Data() : stm32h7xx_hal_hash.c
  • HASH_WriteData() : stm32h7xx_hal_hash.c
  • HCD_HandleTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HC_IN_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HCStateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32h7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32h7xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32h7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32h7xx_hal_hcd.h
  • HCD_Port_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_SPEED_FULL : stm32h7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32h7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32h7xx_hal_hcd.h
  • HCD_StateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_TypeDef : stm32h7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32h7xx_hal_hcd.h
  • HMAC_Processing() : stm32h7xx_hal_hash.c
  • HMAC_Start() : stm32h7xx_hal_hash.c
  • HMAC_Start_DMA() : stm32h7xx_hal_hash.c
  • HMAC_Start_IT() : stm32h7xx_hal_hash.c
  • HSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSE_VALUE : stm32h7xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI48_VALUE : stm32h7xx_ll_rcc.h
  • HSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_VALUE : stm32h7xx_hal_conf.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32h7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32h7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32h7xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32h7xx_hal_i2c.h
  • I2C_ConvertOtherXferOptions() : stm32h7xx_hal_i2c.c
  • I2C_DIRECTION_RECEIVE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32h7xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_DMAAbort() : stm32h7xx_hal_i2c.c
  • I2C_DMAError() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32h7xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32h7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32h7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32h7xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32h7xx_hal_i2c.c
  • I2C_GENERALCALL_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32h7xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32h7xx_hal_i2c.h
  • I2C_GET_DIR : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32h7xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32h7xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32h7xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32h7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32h7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32h7xx_hal_i2c.h
  • I2C_IT_RXI : stm32h7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32h7xx_hal_i2c.h
  • I2C_IT_TCI : stm32h7xx_hal_i2c.h
  • I2C_IT_TXI : stm32h7xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITError() : stm32h7xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32h7xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32h7xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32h7xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32h7xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32h7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32h7xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32h7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32h7xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32h7xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32h7xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MSK : stm32h7xx_hal_i2c.c
  • I2C_STATE_NONE : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32h7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32h7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32h7xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32h7xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32h7xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32h7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_LEFT : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_RIGHT : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32h7xx_hal_i2s.h
  • I2S_DMAError() : stm32h7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_FIRSTBIT_LSB : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_MSB : stm32h7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32h7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXP : stm32h7xx_hal_i2s.h
  • I2S_FLAG_TXP : stm32h7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32h7xx_hal_i2s.h
  • I2S_HandleTypeDef : stm32h7xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32h7xx_ll_spi.c
  • I2S_IT_ERR : stm32h7xx_hal_i2s.h
  • I2S_IT_FRE : stm32h7xx_hal_i2s.h
  • I2S_IT_OVR : stm32h7xx_hal_i2s.h
  • I2S_IT_RXP : stm32h7xx_hal_i2s.h
  • I2S_IT_TXP : stm32h7xx_hal_i2s.h
  • I2S_IT_UDR : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_FULLDUPLEX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_FULLDUPLEX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32h7xx_hal_i2s.h
  • I2S_Receive_16Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_Receive_32Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_STANDARD_LSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32h7xx_hal_i2s.h
  • I2S_TIMEOUT : stm32h7xx_hal_i2s.c
  • I2S_Transmit_16Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_Transmit_32Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s.c
  • I2S_WS_INVERSION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_WS_INVERSION_ENABLE : stm32h7xx_hal_i2s.h
  • IC1Config() : stm32h7xx_ll_tim.c
  • IC2Config() : stm32h7xx_ll_tim.c
  • IC3Config() : stm32h7xx_ll_tim.c
  • IC4Config() : stm32h7xx_ll_tim.c
  • IDCODE_DEVID_MASK : stm32h7xx_hal.c
  • IRDA_AUTOBAUD_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32h7xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_CSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32h7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32h7xx_hal_irda.c
  • IRDA_CR_MASK : stm32h7xx_hal_irda.h
  • IRDA_CR_POS : stm32h7xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32h7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32h7xx_hal_irda.c
  • IRDA_DMAError() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32h7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32h7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32h7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32h7xx_hal_irda_ex.h
  • IRDA_HandleTypeDef : stm32h7xx_hal_irda.h
  • IRDA_InitCallbacksToDefault() : stm32h7xx_hal_irda.c
  • IRDA_ISR_MASK : stm32h7xx_hal_irda.h
  • IRDA_ISR_POS : stm32h7xx_hal_irda.h
  • IRDA_IT_ERR : stm32h7xx_hal_irda.h
  • IRDA_IT_FE : stm32h7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32h7xx_hal_irda.h
  • IRDA_IT_MASK : stm32h7xx_hal_irda.h
  • IRDA_IT_NE : stm32h7xx_hal_irda.h
  • IRDA_IT_ORE : stm32h7xx_hal_irda.h
  • IRDA_IT_PE : stm32h7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32h7xx_hal_irda.h
  • IRDA_IT_TC : stm32h7xx_hal_irda.h
  • IRDA_IT_TXE : stm32h7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32h7xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_RX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32h7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32h7xx_hal_irda.h
  • IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_SetConfig() : stm32h7xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32h7xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32h7xx_hal_irda.c
  • IRDA_WORDLENGTH_7B : stm32h7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32h7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32h7xx_hal_irda_ex.h
  • IS_ADC1_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC2_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC3_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32h7xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CONVERSIONDATAMGT : stm32h7xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_DUAL_DATA_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32h7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32h7xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32h7xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32h7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32h7xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_BITS : stm32h7xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32h7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32h7xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_BDMA_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_BDMA_REQUEST : stm32h7xx_hal_dma.h
  • IS_BOOT_ADDRESS : stm32h7xx_hal_flash.h
  • IS_CEC_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32h7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32h7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32h7xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32h7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32h7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32h7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32h7xx_hal_spdifrx.h
  • IS_COMP_BLANKINGSRCE : stm32h7xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32h7xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32h7xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32h7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32h7xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32h7xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32h7xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32h7xx_hal_cryp.h
  • IS_D3_STATE : stm32h7xx_hal_pwr_ex.h
  • IS_DAC_ALIGN : stm32h7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32h7xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32h7xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32h7xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32h7xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32h7xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32h7xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_BYTE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32h7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_MODE_JPEG : stm32h7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32h7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32h7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32h7xx_hal_crc.h
  • IS_DFSDM1_CHANNEL_INSTANCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM1_FILTER_INSTANCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_BREAK_SIGNALS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SKIPPING_VALUE : stm32h7xx_hal_dfsdm_ex.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DMA_BUFFER_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32h7xx_hal_dma.h
  • IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_DMA_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_DMA_FIFO_MODE_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_MODE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32h7xx_hal_dma.h
  • IS_DMA_REQUEST : stm32h7xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32h7xx_hal_dma_ex.h
  • IS_EXTI_ALL_LINE : stm32h7xx_hal.h
  • IS_EXTI_CONFIG_LINE : stm32h7xx_hal_exti.h
  • IS_EXTI_D1_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_CLEAR : stm32h7xx_hal.h
  • IS_EXTI_D3_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_PENDCLR_SRC : stm32h7xx_hal_exti.h
  • IS_EXTI_EDGE_LINE : stm32h7xx_hal.h
  • IS_EXTI_GPIO_PIN : stm32h7xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32h7xx_hal_exti.h
  • IS_EXTI_LINE : stm32h7xx_hal_exti.h
  • IS_EXTI_MODE : stm32h7xx_hal_exti.h
  • IS_EXTI_MODE_LINE : stm32h7xx_hal.h
  • IS_EXTI_PENDING_EDGE : stm32h7xx_hal_exti.h
  • IS_EXTI_PROPERTY : stm32h7xx_hal_exti.h
  • IS_EXTI_TARGET : stm32h7xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32h7xx_hal_exti.h
  • IS_FDCAN_BRS : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_COUNTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_FIELD_LENGTH : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CLOCK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SIZE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_OPERATION_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_AUTO_CLK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_BASIC_CYCLES_NUMBER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_CYCLE_START_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EXTERNAL_CLK_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_GLOBAL_TIME_FILTERING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REPEAT_FACTOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_PRESET : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_EXTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_INTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TRIGGER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_DENOMINATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_0_2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_NUMERATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TX_ENABLE_WINDOW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32h7xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32h7xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_OTP : stm32h7xx_hal_flash.h
  • IS_FLASH_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPECRC : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32h7xx_hal_flash.h
  • IS_FMC_SWAPBMAP_MODE : stm32h7xx_hal.h
  • IS_GFXMMU_BLOCKS_PER_LINE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_BUFFER_ADDRESS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_FORCE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_FORCE_ACTION : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_LOCK : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_LOCK_BUFFER : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_INTERRUPTS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_BLOCK : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE_OFFSET : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE_STATUS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINES_NUMBER : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_OUTTER_BUFFERABILITY : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_OUTTER_CACHABILITY : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_PREFETCH : stm32h7xx_hal_gfxmmu.h
  • IS_GPIO_AF : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32h7xx_hal_gpio.h
  • IS_GPIO_PULL : stm32h7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32h7xx_hal_gpio.h
  • IS_HAL_EXTI_CONFIG_LINE : stm32h7xx_hal.h
  • IS_HASH_DATATYPE : stm32h7xx_hal_hash.h
  • IS_HASH_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_POLLING_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HMAC_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HMAC_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HSEM_COREID : stm32h7xx_hal_hsem.h
  • IS_HSEM_KEY : stm32h7xx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32h7xx_hal_hsem.h
  • IS_HSEM_SEMID : stm32h7xx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32h7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32h7xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32h7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32h7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32h7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_24BIT_ALIGNMENT : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32h7xx_hal_i2s.h
  • IS_I2S_FIRST_BIT : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER_KEEP_IO_STATE : stm32h7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32h7xx_hal_i2s.h
  • IS_I2S_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_SLAVE : stm32h7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32h7xx_hal_i2s.h
  • IS_I2S_WS_INVERSION : stm32h7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32h7xx_hal_irda.h
  • IS_IRDA_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32h7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32h7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32h7xx_hal_irda.h
  • IS_IRDA_STATE : stm32h7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32h7xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32h7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32h7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32h7xx_hal_iwdg.h
  • IS_JPEG_CHROMASUBSAMPLING : stm32h7xx_hal_jpeg.h
  • IS_JPEG_COLORSPACE : stm32h7xx_hal_jpeg.h
  • IS_JPEG_IMAGE_QUALITY : stm32h7xx_hal_jpeg.h
  • IS_JPEG_PAUSE_RESUME_STATE : stm32h7xx_hal_jpeg.h
  • IS_LL_ADC_COMMON_CLOCK : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_LEFT_BIT_SHIFT : stm32h7xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_DATA_TRANSFER_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32h7xx_ll_adc.c
  • IS_LL_BDMA_ALL_CHANNEL_INSTANCE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_DIRECTION : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MEMORYDATASIZE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MEMORYINCMODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_NBDATA : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHDATASIZE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHINCMODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHREQUEST : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PRIORITY : stm32h7xx_ll_bdma.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32h7xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32h7xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32h7xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32h7xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32h7xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32h7xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32h7xx_ll_dac.c
  • IS_LL_DMA2D_ALPHA : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_ALPHAINV : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_ALPHAMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_BLUE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CHROMA_SUB_SAMPLING : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CLUTCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CLUTSIZE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_GREEN : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_LCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_LINE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OFFSET : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OFFSET_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_PIXEL : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_RBSWAP : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_RED : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_SWAP_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA_ALL_STREAM_INSTANCE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32h7xx_ll_dma.c
  • IS_LL_DMA_FIFO_MODE_STATE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_FIFO_THRESHOLD : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORY_BURST : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHERAL_BURST : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32h7xx_ll_dma.c
  • IS_LL_DMA_REQUEST : stm32h7xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_LINE_64_95 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32h7xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32h7xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32h7xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32h7xx_ll_spi.c
  • IS_LL_I2S_BIT_ORDER : stm32h7xx_ll_spi.c
  • IS_LL_I2S_CHANNEL_LENGTH_TYPE : stm32h7xx_ll_spi.c
  • IS_LL_I2S_CKPOL : stm32h7xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32h7xx_ll_spi.c
  • IS_LL_I2S_FIFO_TH : stm32h7xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32h7xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32h7xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32h7xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32h7xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32h7xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32h7xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32h7xx_ll_lpuart.c
  • IS_LL_MDMA_ALL_CHANNEL_INSTANCE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLK_DATALENGTH : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLK_REPEATCOUNT : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BUFFER_XFERLENGTH : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BUFFWRITEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BYTEENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DEST_BUS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTBURST : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTDATASIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTINCMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTINCSIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_HALFWORDENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_HWTRIGGER : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PACKMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PADDINGALIGNEMENT : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PRIORITY : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_REQUESTMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRC_BUS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCDATASIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCINCMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCINCSIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCTBURST : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_TRIGGERMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_WORDENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32h7xx_ll_opamp.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_SPI_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CLOCK_DIVIDER : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG1 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG2 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG3 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_NIST_COMPLIANCE : stm32h7xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32h7xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATEPRESCALER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRC : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32h7xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32h7xx_ll_spi.c
  • IS_LL_SPI_FIFO_TH : stm32h7xx_ll_spi.c
  • IS_LL_SPI_ID_IDLENESS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32h7xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32h7xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32h7xx_ll_spi.c
  • IS_LL_SPI_PROTOCOL : stm32h7xx_ll_spi.c
  • IS_LL_SPI_RX_FIFO : stm32h7xx_ll_spi.c
  • IS_LL_SPI_RXCRCINIT_PATTERN : stm32h7xx_ll_spi.c
  • IS_LL_SPI_SS_IDLENESS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32h7xx_ll_spi.c
  • IS_LL_SPI_TXCRCINIT_PATTERN : stm32h7xx_ll_spi.c
  • IS_LL_SPI_UDR_CONFIG_REGISTER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_UDR_DETECT_BEGIN_DATA : stm32h7xx_ll_spi.c
  • IS_LL_SWPMI_BITRATE_VALUE : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_RX : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_TX : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_VOLTAGE_CLASS : stm32h7xx_ll_swpmi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32h7xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32h7xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32h7xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32h7xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32h7xx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32h7xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32h7xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32h7xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32h7xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32h7xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32h7xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32h7xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32h7xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32h7xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32h7xx_ll_usart.c
  • IS_LL_UTILS_AHB_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB1_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB3_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB4_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_CHECK_VCO_RANGES : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_FRACN_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLP_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32h7xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32h7xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_LTDC_AAH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AAW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AHBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AVBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR1 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR2 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLUEVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLNBR : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_DEPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_GREENVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSYNC : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LIPOS : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PCPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PIXEL_FORMAT : stm32h7xx_hal_ltdc.h
  • IS_LTDC_REDVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_RELOAD : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSYNC : stm32h7xx_hal_ltdc.h
  • IS_MDIOS_PORTADDRESS : stm32h7xx_hal_mdios.h
  • IS_MDIOS_PREAMBLECHECK : stm32h7xx_hal_mdios.h
  • IS_MDIOS_REGISTER : stm32h7xx_hal_mdios.h
  • IS_MDMA_BLOCK_ADDR_OFFSET : stm32h7xx_hal_mdma.h
  • IS_MDMA_BLOCK_COUNT : stm32h7xx_hal_mdma.h
  • IS_MDMA_BUFFER_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_DATA_ALIGNMENT : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_ENDIANNESS_MODE : stm32h7xx_hal_mdma.h
  • IS_MDMA_LEVEL_COMPLETE : stm32h7xx_hal_mdma.h
  • IS_MDMA_PRIORITY : stm32h7xx_hal_mdma.h
  • IS_MDMA_REQUEST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_TRIGGER_MODE : stm32h7xx_hal_mdma.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32h7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32h7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32h7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32h7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_OB_BOOT_ADD_OPTION : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOOT_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG1_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_PCROP_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_SECURE_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_TYPE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_VDDMMC_HSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OPAMP_FACTORYTRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32h7xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32h7xx_hal_flash_ex.h
  • IS_OTP_BLOCK : stm32h7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PREAMBLE_TYPE_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PSSI_BUSWIDTH : stm32h7xx_hal_pssi.h
  • IS_PSSI_CLOCK_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PSSI_CONTROL_SIGNAL : stm32h7xx_hal_pssi.h
  • IS_PSSI_DE_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PSSI_RDY_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PWR_AVD_LEVEL : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_AVD_MODE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_D1_CPU : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32h7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_MODE_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_FLAG : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_PULL : stm32h7xx_hal_pwr_ex.h
  • IS_RAMECC_GLOBAL_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RAMECC_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RAMECC_MONITOR_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RCC_ADCCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CDPCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLKPSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CSI : stm32h7xx_hal_rcc.h
  • IS_RCC_CSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_D1PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_D3PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_DFSDM2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FLAG : stm32h7xx_hal_rcc.h
  • IS_RCC_FMCCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_HSE : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32h7xx_hal_rcc.h
  • IS_RCC_HSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_I2C123CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM345CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32h7xx_hal_rcc.h
  • IS_RCC_LSI : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32h7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_OSPICLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK2 : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL2CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2RGE_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2VCO_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3RGE_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3VCO_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLCLOCKOUT_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLFRACN_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2ACLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2BCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SCOPE_WWDG : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPDIFRXCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI123CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI45CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI6CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SRDPCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_KERWAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART9CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART10CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART16910CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART16CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART234578CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32h7xx_hal_rng.h
  • IS_RNG_CLOCK_DIVIDER : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG1 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG2 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG3 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_FLAG : stm32h7xx_hal_rng.h
  • IS_RNG_IT : stm32h7xx_hal_rng.h
  • IS_RNG_NIST_COMPLIANCE : stm32h7xx_hal_rng_ex.h
  • IS_RTC_ALARM : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32h7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_BKP : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32h7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32h7xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32h7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32h7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32h7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER_CONFIG_CORRECT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32h7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32h7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32h7xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32h7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32h7xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32h7xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SPDIFRX_CHANNEL : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32h7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32h7xx_hal_spi.h
  • IS_SPI_CPHA : stm32h7xx_hal_spi.h
  • IS_SPI_CPOL : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_INITIALIZATION_PATTERN : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32h7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_FIFOTHRESHOLD : stm32h7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32h7xx_hal_spi.h
  • IS_SPI_MODE : stm32h7xx_hal_spi.h
  • IS_SPI_NSS : stm32h7xx_hal_spi.h
  • IS_SPI_NSSP : stm32h7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_BEHAVIOUR : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_DETECTION : stm32h7xx_hal_spi.h
  • IS_STEREO_MODE : stm32h7xx_hal_spdifrx.h
  • IS_SWPMI_BITRATE_VALUE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32h7xx_hal_swpmi.h
  • IS_SYMBOL_CLOCK_GEN : stm32h7xx_hal_spdifrx.h
  • IS_SYSCFG_ANALOG_SWITCH : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_ADDRESS : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_REGISTER : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_SELECT : stm32h7xx_hal.h
  • IS_SYSCFG_ETHERNET_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32h7xx_hal.h
  • IS_SYSCFG_SWITCH_STATE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32h7xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32h7xx_hal_cortex.h
  • IS_TICKFREQ : stm32h7xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32h7xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32h7xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32h7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32h7xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TISEL : stm32h7xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32h7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32h7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32h7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32h7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32h7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32h7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32h7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32h7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32h7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32h7xx_hal_uart.h
  • IS_UART_LIN : stm32h7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32h7xx_hal_uart.h
  • IS_UART_MODE : stm32h7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32h7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32h7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32h7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32h7xx_hal_uart.h
  • IS_UART_PARITY : stm32h7xx_hal_uart.h
  • IS_UART_PRESCALER : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32h7xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32h7xx_hal_uart_ex.h
  • IS_UART_STATE : stm32h7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32h7xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32h7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32h7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32h7xx_hal_usart.h
  • IS_USART_CLOCK : stm32h7xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32h7xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32h7xx_hal_usart.h
  • IS_USART_MODE : stm32h7xx_hal_usart.h
  • IS_USART_NSS : stm32h7xx_hal_usart_ex.h
  • IS_USART_OVERSAMPLING : stm32h7xx_hal_usart.h
  • IS_USART_PARITY : stm32h7xx_hal_usart.h
  • IS_USART_PHASE : stm32h7xx_hal_usart.h
  • IS_USART_POLARITY : stm32h7xx_hal_usart.h
  • IS_USART_PRESCALER : stm32h7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32h7xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32h7xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32h7xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32h7xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32h7xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32h7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32h7xx_hal_spdifrx.h
  • IS_WRPSTATE : stm32h7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32h7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32h7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32h7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32h7xx_hal_iwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
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  • e
  • f
  • g
  • h
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  • j
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- j -

  • JPEG_420_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_422_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_444_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_AC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_ACCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_ACHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_ACLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_Bits_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_CMYK_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_CONTEXT_CONF_ENCODING : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_CUSTOM_TABLES : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DECODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENCODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENDING_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_IT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_METHOD_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_OPERATION_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_INPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_OUTPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_POLLING : stm32h7xx_hal_jpeg.c
  • JPEG_DC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_DCCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DCLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_ContinueProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_EndProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_PollResidualData() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_StartProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_TH_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FLAG_ALL : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_COF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_EOCF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_HPDF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFNFF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFTF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFNEF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFTF : stm32h7xx_hal_jpeg.h
  • JPEG_GetQuality() : stm32h7xx_hal_jpeg.c
  • JPEG_GRAYSCALE_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_HandleTypeDef : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MAX : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MIN : stm32h7xx_hal_jpeg.h
  • JPEG_Init_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_INTERRUPT_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_IT_EOC : stm32h7xx_hal_jpeg.h
  • JPEG_IT_HPD : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFNF : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFT : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFNE : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFT : stm32h7xx_hal_jpeg.h
  • JPEG_MDMAErrorCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAInCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutAbortCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_PAUSE_RESUME_INPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_DONE : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_ONGOING : stm32h7xx_hal_jpeg.c
  • JPEG_QUANT_TABLE_SIZE : stm32h7xx_hal_jpeg.h
  • JPEG_ReadInputData() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Huff_DHTMem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffAC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffDC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffEnc_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Quantization_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorCMYK() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorGrayScale() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorYCBCR() : stm32h7xx_hal_jpeg.c
  • JPEG_StoreOutputData() : stm32h7xx_hal_jpeg.c
  • JPEG_TIMEOUT_VALUE : stm32h7xx_hal_jpeg.c
  • JPEG_YCBCR_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_ZIGZAG_ORDER : stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LL_ADC_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD1_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD2_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD3_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_12MHZ5 : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_20MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_25MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_50MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_6MHZ25 : stm32h7xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD1 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD2 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD3 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD4 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD5 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD6 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_OFFSET : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_19 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC2CH1_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32h7xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32h7xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32h7xx_ll_adc.h
  • LL_ADC_DeInit() : stm32h7xx_ll_adc.c
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_Disable() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32h7xx_ll_adc.h
  • LL_ADC_Enable() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32h7xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32h7xx_ll_adc.h
  • LL_ADC_GetBoostMode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCalibrationLinearFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCalibrationOffsetFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32h7xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32h7xx_ll_adc.h
  • LL_ADC_GetDataRightShift() : stm32h7xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetSignedSaturation() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32h7xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData14() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData16() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32h7xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32h7xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_1 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_10 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_11 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_12 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_13 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_14 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_15 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_2 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_3 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_4 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_5 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_6 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_7 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_8 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_9 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32h7xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_RES_32_10B : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_RES_8B : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_RSHIFT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_RSHIFT_ENABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_10 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_11 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_9 : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32h7xx_ll_adc.h
  • LL_ADC_ReadReg : stm32h7xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DFSDM_TRANSFER : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DR_TRANSFER : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetDataTransferMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32h7xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData14() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData16() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetDataTransferMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_14B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_16B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_16CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_32CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_387CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_64CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_810CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_8CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32h7xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32h7xx_ll_adc.h
  • LL_ADC_SetBoostMode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCalibrationLinearFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCalibrationOffsetFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32h7xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32h7xx_ll_adc.h
  • LL_ADC_SetDataRightShift() : stm32h7xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOffsetSignedSaturation() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32h7xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32h7xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32h7xx_ll_adc.h
  • LL_ADC_StructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_WriteReg : stm32h7xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ADC12 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AHBSRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AHBSRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_BDMA1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_CRYP : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_D2SRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_D2SRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DCMI : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_HASH : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_HSEM : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SDMMC2 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM3 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DMA2D : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DTCM1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DTCM2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FLASH : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FMC : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_GFXMMU : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ITCM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_JPGDEC : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_MDMA : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OSPI1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OSPI2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_SDMMC1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BDMA : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BDMA2 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BKPRAM : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_D3SRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOA : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOB : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOC : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOD : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOE : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOF : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOG : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOH : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOI : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOJ : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOK : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_SRAM4 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_SRDSRAM : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC12 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPDIFRX : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM12 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM13 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM14 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART5 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART7 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART8 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_CRS : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_FDCAN : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_MDIOS : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_OPAMP : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_SWPMI1 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_DFSDM1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI2 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI4 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI5 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_UART9 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART10 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART6 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_LTDC : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_WWDG : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_WWDG1 : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_COMP12 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DAC2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DFSDM2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DTS : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_I2C4 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPTIM2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPTIM3 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPUART1 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_RTCAPB : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_SPI6 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_SYSCFG : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_VREF : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_BDMA_CCR_HTIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CCR_TCIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CCR_TEIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CH_OFFSET_TAB : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_ALL : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ConfigAddresses() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ConfigTransfer() : stm32h7xx_ll_bdma.h
  • LL_BDMA_CURRENTTARGETMEM0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CURRENTTARGETMEM1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_DeInit() : stm32h7xx_ll_bdma.c
  • LL_BDMA_DIRECTION_MEMORY_TO_MEMORY : stm32h7xx_ll_bdma.h
  • LL_BDMA_DIRECTION_MEMORY_TO_PERIPH : stm32h7xx_ll_bdma.h
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableDoubleBufferMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DOUBLEBUFFER_MODE_DISABLE : stm32h7xx_ll_bdma.h
  • LL_BDMA_DOUBLEBUFFER_MODE_ENABLE : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableDoubleBufferMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetChannelPriorityLevel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetCurrentTargetMem() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetDataLength() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetDataTransferDirection() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetM2MDstAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetM2MSrcAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemory1Address() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemoryAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemoryIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemorySize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphRequest() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphSize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_Init() : stm32h7xx_ll_bdma.c
  • LL_BDMA_IsActiveFlag_GI0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_BYTE : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_HALFWORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_WORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_MEMORY_INCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_MEMORY_NOINCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_MODE_CIRCULAR : stm32h7xx_ll_bdma.h
  • LL_BDMA_MODE_NORMAL : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_BYTE : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_HALFWORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_WORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_PERIPH_INCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_PERIPH_NOINCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_HIGH : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_LOW : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_MEDIUM : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_VERYHIGH : stm32h7xx_ll_bdma.h
  • LL_BDMA_ReadReg : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetChannelPriorityLevel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetCurrentTargetMem() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetDataLength() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetDataTransferDirection() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetM2MDstAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetM2MSrcAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemory1Address() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemoryAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemoryIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemorySize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphRequest() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphSize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_StructInit() : stm32h7xx_ll_bdma.c
  • LL_BDMA_WriteReg : stm32h7xx_ll_bdma.h
  • LL_CKGA_Disable() : stm32h7xx_ll_bus.h
  • LL_CKGA_Enable() : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AHB : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AHB12 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AHB34 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXI : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM1 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM2 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM3 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_CPU : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_DMA2D : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_ECCRAM : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_EXTI : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_FLIFT : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_FMC : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_GFXMMUM : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_GFXMMUS : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_JTAG : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_LTDC : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_MDMA : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_OCTOSPI1 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_OCTOSPI2 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_SDMMC : stm32h7xx_ll_bus.h
  • LL_CLKAM_Disable() : stm32h7xx_ll_bus.h
  • LL_CLKAM_Enable() : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BDMA : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BDMA2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BKPRAM : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_COMP12 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DAC2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DFSDM2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DTS : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_GPIO : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_I2C4 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPTIM2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPTIM3 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPUART1 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_RTC : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SPI6 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SRAM4 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SRDSRAM : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_VREF : stm32h7xx_ll_bus.h
  • LL_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_CONFIG : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_MASK : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_REG : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_SHIFT : stm32h7xx_ll_rcc.h
  • LL_COMP_AF_PA6 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PA8 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PB12 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PE15 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PE6 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG2 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG3 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG4 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PI1 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PI4 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PK2 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_NONE : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_ll_comp.h
  • LL_COMP_ConfigInputs() : stm32h7xx_ll_comp.h
  • LL_COMP_DeInit() : stm32h7xx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32h7xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_ll_comp.h
  • LL_COMP_Disable() : stm32h7xx_ll_comp.h
  • LL_COMP_Enable() : stm32h7xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputAlternateFunction() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32h7xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32h7xx_ll_comp.h
  • LL_COMP_Init() : stm32h7xx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VBAT_VDDAP : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_DAC2_CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32h7xx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32h7xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32h7xx_ll_comp.h
  • LL_COMP_Lock() : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32h7xx_ll_comp.h
  • LL_COMP_ReadReg : stm32h7xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputAlternateFunction() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32h7xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32h7xx_ll_comp.h
  • LL_COMP_StructInit() : stm32h7xx_ll_comp.c
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32h7xx_ll_comp.h
  • LL_COMP_WriteReg : stm32h7xx_ll_comp.h
  • LL_CPUID_GetConstant() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32h7xx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32h7xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32h7xx_ll_crc.h
  • LL_CRC_DeInit() : stm32h7xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32h7xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32h7xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32h7xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32h7xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32h7xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32h7xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32h7xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32h7xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadReg : stm32h7xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32h7xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32h7xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32h7xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32h7xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32h7xx_ll_crc.h
  • LL_CRC_WriteReg : stm32h7xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32h7xx_ll_crs.h
  • LL_CRS_CR_ERRIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32h7xx_ll_crs.h
  • LL_CRS_DeInit() : stm32h7xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32h7xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32h7xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32h7xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32h7xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32h7xx_ll_crs.h
  • LL_CRS_ReadReg : stm32h7xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32h7xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32h7xx_ll_crs.h
  • LL_CRS_WriteReg : stm32h7xx_ll_crs.h
  • LL_D3_EXTI_DisablePendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_DisablePendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_EnablePendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_EnablePendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_0_15() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_16_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_32_47() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_48_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_IsEnabledPendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_IsEnabledPendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_0_15() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_16_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_32_47() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_48_63() : stm32h7xx_ll_exti.h
  • LL_DAC_CHANNEL_1 : stm32h7xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32h7xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32h7xx_ll_dac.h
  • LL_DAC_CONNECT_GPIO : stm32h7xx_ll_dac.h
  • LL_DAC_CONNECT_INTERNAL : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_DeInit() : stm32h7xx_ll_dac.c
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32h7xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32h7xx_ll_dac.h
  • LL_DAC_Disable() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_Enable() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32h7xx_ll_dac.h
  • LL_DAC_GetMode() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32h7xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32h7xx_ll_dac.h
  • LL_DAC_Init() : stm32h7xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32h7xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32h7xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32h7xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32h7xx_ll_dac.h
  • LL_DAC_ReadReg : stm32h7xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32h7xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32h7xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32h7xx_ll_dac.h
  • LL_DAC_SetMode() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32h7xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32h7xx_ll_dac.h
  • LL_DAC_StructInit() : stm32h7xx_ll_dac.c
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_EXT_IT9 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_SOFTWARE : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM2_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM4_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM6_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM7_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM8_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TrigSWConversion() : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NOISE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NONE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_TRIANGLE : stm32h7xx_ll_dac.h
  • LL_DAC_WriteReg : stm32h7xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FDCAN_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_HRTIM_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_WWDG1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_I2C4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_IWDG1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM5_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_RTC_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInSleepMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableTracePortClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInSleepMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableTracePortClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetExternalTriggerPinDirection() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32h7xx_ll_system.h
  • LL_DBGMCU_SetExternalTriggerPinDirection() : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRGIO_INPUT_DIRECTION : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRGIO_OUTPUT_DIRECTION : stm32h7xx_ll_system.h
  • LL_DMA2D_Abort() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_INVERTED : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_COMBINE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_NO_MODIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_REPLACE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_EnableCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_IsEnabledCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUTSIZE_MAX : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_COLOR : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_ConfigLayer() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_ConfigOutputColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_ConfigSize() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_CSS_420 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CSS_422 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CSS_444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DeInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_DisableDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_EnableCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetChrSubSampling() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_IsEnabledCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetChrSubSampling() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CAEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CTCIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TCIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TWIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineOffsetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineWatermark() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetNbrOfLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetNbrOfPixelsPerLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputAlphaColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputBlueColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputGreenColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputRedColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_Init() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_INPUT_MODE_A4 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_A8 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_AL44 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_AL88 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB1555 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB4444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_L4 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_L8 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_RGB565 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_YCBCR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsAborted() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsSuspended() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsTransferOngoing() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CAEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CTCIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TCIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TWIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_LayerCfgStructInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_LINE_OFFSET_BYTES : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_LINE_OFFSET_PIXELS : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_PFC : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_R2M : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_NUMBEROFLINES : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_NUMBEROFPIXELS : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_OFFSET_MAX : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_OUTPUT_MODE_ARGB1555 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_ARGB4444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_RGB565 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_RB_MODE_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_RB_MODE_SWAP : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ReadReg : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_Resume() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineOffsetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineWatermark() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetNbrOfLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetNbrOfPixelsPerLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_Start() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_StructInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_Suspend() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SWAP_MODE_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SWAP_MODE_TWO_BY_TWO : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_WriteReg : stm32h7xx_ll_dma2d.h
  • LL_DMA_ClearFlag_DME0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigFifo() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32h7xx_ll_dma.h
  • LL_DMA_CURRENTTARGETMEM0 : stm32h7xx_ll_dma.h
  • LL_DMA_CURRENTTARGETMEM1 : stm32h7xx_ll_dma.h
  • LL_DMA_DeInit() : stm32h7xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32h7xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32h7xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32h7xx_ll_dma.h
  • LL_DMA_DisableDoubleBufferMode() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableFifoMode() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableStream() : stm32h7xx_ll_dma.h
  • LL_DMA_DOUBLEBUFFER_MODE_DISABLE : stm32h7xx_ll_dma.h
  • LL_DMA_DOUBLEBUFFER_MODE_ENABLE : stm32h7xx_ll_dma.h
  • LL_DMA_EnableDoubleBufferMode() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableFifoMode() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableStream() : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOMODE_DISABLE : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOMODE_ENABLE : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_0_25 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_25_50 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_50_75 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_75_100 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_EMPTY : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_FULL : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_FULL : stm32h7xx_ll_dma.h
  • LL_DMA_GetCurrentTargetMem() : stm32h7xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32h7xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32h7xx_ll_dma.h
  • LL_DMA_GetFIFOStatus() : stm32h7xx_ll_dma.h
  • LL_DMA_GetFIFOThreshold() : stm32h7xx_ll_dma.h
  • LL_DMA_GetIncOffsetSize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemory1Address() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetStreamPriorityLevel() : stm32h7xx_ll_dma.h
  • LL_DMA_Init() : stm32h7xx_ll_dma.c
  • LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledStream() : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC16 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC4 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC8 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_SINGLE : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32h7xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_PFCTRL : stm32h7xx_ll_dma.h
  • LL_DMA_OFFSETSIZE_FIXEDTO4 : stm32h7xx_ll_dma.h
  • LL_DMA_OFFSETSIZE_PSIZE : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC16 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC4 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC8 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_SINGLE : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32h7xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32h7xx_ll_dma.h
  • LL_DMA_ReadReg : stm32h7xx_ll_dma.h
  • LL_DMA_SetCurrentTargetMem() : stm32h7xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32h7xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32h7xx_ll_dma.h
  • LL_DMA_SetFIFOThreshold() : stm32h7xx_ll_dma.h
  • LL_DMA_SetIncOffsetSize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemory1Address() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetStreamPriorityLevel() : stm32h7xx_ll_dma.h
  • LL_DMA_STR_OFFSET_TAB : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_0 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_1 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_2 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_3 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_4 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_5 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_6 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_7 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_ALL : stm32h7xx_ll_dma.h
  • LL_DMA_StructInit() : stm32h7xx_ll_dma.c
  • LL_DMA_WriteReg : stm32h7xx_ll_dma.h
  • LL_DMAMUX1_REQ_ADC1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_ADC2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_CRYP_IN : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_CRYP_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DAC1_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DAC1_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DCMI : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DCMI_PSSI : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_TIM12_TRGO : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_HASH_IN : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_MEM2MEM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI1_A : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI1_B : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI2_A : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI2_B : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPDIF_RX_CS : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPDIF_RX_DT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI5_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI5_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SWPMI_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SWPMI_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM16_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM16_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM17_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM17_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM6_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM7_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART5_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART5_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART7_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART7_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART8_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART8_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART9_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART9_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART10_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART10_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART6_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART6_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_DAC2_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_DFSDM2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_COMP1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_COMP2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_EXTI2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_I2C4_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_RTC_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_SPI6_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_SPI6_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_I2C4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_I2C4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_LPUART1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_LPUART1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_MEM2MEM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_SPI6_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_SPI6_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CCR_SOIE : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO12() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO13() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO14() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO15() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO12() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO13() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO14() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO15() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32h7xx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_ClearFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_DMACH6 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_DMACH7 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_LPTIM2 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_LPTIM3 : stm32h7xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32h7xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_Init() : stm32h7xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_42 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_43 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_47 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_48 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_49 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_50 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_51 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_52 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_53 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_54 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_55 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_56 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_57 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_58 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_59 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_60 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_61 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_62 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_63 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_64 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_65 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_66 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_67 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_68 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_69 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_70 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_71 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_72 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_73 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_74 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_85 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_87 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_88 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_64_95 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32h7xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32h7xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32h7xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32h7xx_ll_exti.h
  • LL_FLASH_GetLatency() : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_5 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_6 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_7 : stm32h7xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32h7xx_ll_system.h
  • LL_GetFlashSize() : stm32h7xx_ll_utils.h
  • LL_GetPackageType() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word0() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word1() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word2() : stm32h7xx_ll_utils.h
  • LL_GPIO_AF_0 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32h7xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32h7xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32h7xx_ll_gpio.h
  • LL_GPIO_Init() : stm32h7xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32h7xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32h7xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32h7xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32h7xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32h7xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32h7xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32h7xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32h7xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32h7xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32h7xx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32h7xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32h7xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32h7xx_ll_cortex.h
  • LL_HSEM_1StepLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_2StepLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ClearFlag_C1ICR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_COREID : stm32h7xx_ll_hsem.h
  • LL_HSEM_COREID_CPU1 : stm32h7xx_ll_hsem.h
  • LL_HSEM_COREID_NONE : stm32h7xx_ll_hsem.h
  • LL_HSEM_DisableIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_EnableIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetCoreId() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetKey() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetProcessId() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetStatus() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1ISR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1MISR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsSemaphoreLocked() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ReadReg : stm32h7xx_ll_hsem.h
  • LL_HSEM_ReleaseLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ResetAllLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_0 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_1 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_10 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_11 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_12 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_13 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_14 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_15 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_2 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_3 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_4 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_5 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_6 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_7 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_8 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_9 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_ALL : stm32h7xx_ll_hsem.h
  • LL_HSEM_SetKey() : stm32h7xx_ll_hsem.h
  • LL_HSEM_SetLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_WriteReg : stm32h7xx_ll_hsem.h
  • LL_I2C_ACK : stm32h7xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32h7xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32h7xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32h7xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32h7xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32h7xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_Disable() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_i2c.h
  • LL_I2C_Enable() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32h7xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32h7xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32h7xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32h7xx_ll_i2c.h
  • LL_I2C_Init() : stm32h7xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32h7xx_ll_i2c.h
  • LL_I2C_NACK : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32h7xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32h7xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32h7xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32h7xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32h7xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32h7xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32h7xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32h7xx_ll_spi.h
  • LL_I2S_ClearFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32h7xx_ll_spi.h
  • LL_I2S_DeInit() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_Disable() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_Enable() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIOLock() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_01DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_02DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_03DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_04DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_05DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_06DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_07DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_08DATA : stm32h7xx_ll_spi.h
  • LL_I2S_GetChannelLengthType() : stm32h7xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32h7xx_ll_spi.h
  • LL_I2S_GetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32h7xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32h7xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32h7xx_ll_spi.h
  • LL_I2S_GetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32h7xx_ll_spi.h
  • LL_I2S_Init() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveTransfer() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIOLock() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_LSB_FIRST : stm32h7xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32h7xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32h7xx_ll_spi.h
  • LL_I2S_MSB_FIRST : stm32h7xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32h7xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32h7xx_ll_spi.h
  • LL_I2S_ReadReg : stm32h7xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32h7xx_ll_spi.h
  • LL_I2S_ReceiveData32() : stm32h7xx_ll_spi.h
  • LL_I2S_SetChannelLengthType() : stm32h7xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32h7xx_ll_spi.h
  • LL_I2S_SetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32h7xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32h7xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32h7xx_ll_spi.h
  • LL_I2S_SetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32h7xx_ll_spi.h
  • LL_I2S_SLAVE_FIXED_CH_LENGTH : stm32h7xx_ll_spi.h
  • LL_I2S_SLAVE_VARIABLE_CH_LENGTH : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32h7xx_ll_spi.h
  • LL_I2S_StartTransfer() : stm32h7xx_ll_spi.h
  • LL_I2S_StructInit() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_TransmitData16() : stm32h7xx_ll_spi.h
  • LL_I2S_TransmitData32() : stm32h7xx_ll_spi.h
  • LL_I2S_WriteReg : stm32h7xx_ll_spi.h
  • LL_Init1msTick() : stm32h7xx_ll_utils.c
  • LL_InitTick() : stm32h7xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32h7xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32h7xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32h7xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32h7xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_TRIG_FILTER_2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM3 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM5 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TrigSw() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32h7xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32h7xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_DIRECTION_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_Disable() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_TXFECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32h7xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32h7xx_ll_utils.h
  • LL_mDelay() : stm32h7xx_ll_utils.c
  • LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLOCK_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFF_WRITE_DISABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFF_WRITE_ENABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFFER_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BYTE_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_CH_OFFSET_TAB : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_0 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_1 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_10 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_11 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_12 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_13 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_14 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_15 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_2 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_3 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_4 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_5 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_6 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_7 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_8 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_9 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_ALL : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigAddresses() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkCounters() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkRepeatAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkRptAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigTransfer() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigXferEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConnectLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_CreateLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_DATAALIGN_LEFT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DATAALIGN_RIGHT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_ll_mdma.h
  • LL_MDMA_DeInit() : stm32h7xx_ll_mdma.c
  • LL_MDMA_DEST_BURST_128BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_16BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_2BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_32BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_4BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_64BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_8BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_SINGLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BUS_AHB_TCM : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BUS_SYSTEM_AXI : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_FIXED : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisablePacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisconnectNextLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_EnableBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnablePacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_FULL_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_GenerateSWRequest() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_CHANNEL : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_CHANNEL_INSTANCE : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_INSTANCE : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkDataLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatCount() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatDestAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatSrcAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRptDestAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRptSrcAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBufferTransferLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetByteEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetChannelPriorityLevel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetHalfWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetHWTrigger() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetLinkAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetMaskAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetMaskData() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetPaddingAlignment() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetRequestMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSrcBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetTriggerMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetXferErrorDirection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetXferErrorLSBAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_Init() : stm32h7xx_ll_mdma.c
  • LL_MDMA_IsActiveFlag_ASE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BSE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_CRQA() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_GI() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TELD() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TEMD() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledPacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_PACK_DISABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_PACK_ENABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_HIGH : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_LOW : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_MEDIUM : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_VERYHIGH : stm32h7xx_ll_mdma.h
  • LL_MDMA_READ_ERROR : stm32h7xx_ll_mdma.h
  • LL_MDMA_ReadReg : stm32h7xx_ll_mdma.h
  • LL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM0_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM3_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM4_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM5_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM6_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM7_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM0_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM3_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM4_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM5_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM6_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM7_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_CLUT_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_TW : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_END_CONVERSION : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_INFIFO_NF : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_INFIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_OUTFIFO_NE : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_OUTFIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_LTDC_LINE_IT : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI1_FIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI2_FIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_COMMAND_END : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_END_DATA : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQUEST_MODE_HW : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQUEST_MODE_SW : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkDataLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatCount() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatDestAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatSrcAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRptDestAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRptSrcAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBufferTransferLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetByteEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetChannelPriorityLevel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetHalfWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetHWTrigger() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetLinkAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetMaskAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetMaskData() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetPaddingAlignment() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetRequestMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSrcBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetTriggerMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_128BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_16BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_2BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_32BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_4BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_64BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_8BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_SINGLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BUS_AHB_TCM : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BUS_SYSTEM_AXI : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_FIXED : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_StructInit() : stm32h7xx_ll_mdma.c
  • LL_MDMA_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_WORD_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_WRITE_ERROR : stm32h7xx_ll_mdma.h
  • LL_MDMA_WriteReg : stm32h7xx_ll_mdma.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32h7xx_ll_cortex.h
  • LL_MPU_Disable() : stm32h7xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_Enable() : stm32h7xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER10 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER11 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER12 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER13 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER14 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER15 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER8 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER9 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32h7xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32h7xx_ll_opamp.c
  • LL_OPAMP_DELAY_STARTUP_US : stm32h7xx_ll_opamp.h
  • LL_OPAMP_Disable() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32h7xx_ll_opamp.c
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC2 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_IsCalibrationOutputSet() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_BIAS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32h7xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32h7xx_ll_opamp.c
  • LL_OPAMP_TRIMMING_FACTORY : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32h7xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32h7xx_ll_opamp.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32h7xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32h7xx_ll_utils.c
  • LL_PWR_AVDLEVEL_0 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_1 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_2 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_3 : stm32h7xx_ll_pwr.h
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32h7xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_CPU() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU6() : stm32h7xx_ll_pwr.h
  • LL_PWR_ConfigSupply() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_DisableSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_EnableSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_GetCDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_GetD3PowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsActiveFlag_SB() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsActiveFlag_STOP() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_CDSTOP : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_CDSTOP2 : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDRUN : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDSTANDBY : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDSTOP : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_SetCDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_SetSRDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32h7xx_ll_pwr.c
  • LL_PWR_DIRECT_SMPS_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableITCMSOShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableITCMSOShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_ACTVOS : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_ACTVOSRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_AVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_BRRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_CSSF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_SBF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_STOPF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_MMCVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_PVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_SMPSEXTRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_TEMPH : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_TEMPL : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_USBRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_VBATH : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_VBATL : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC1 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC2 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC3 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC4 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC5 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC6 : stm32h7xx_ll_pwr.h
  • LL_PWR_GetAVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetStopModeRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetSupply() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetWakeUpPinPull() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_ACTVOS() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_AVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BRR() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_MMCVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SMPSEXT() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_TEMPH() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_TEMPL() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_USB() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VBATH() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VBATL() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU6() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledITCMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32h7xx_ll_pwr.h
  • LL_PWR_LDO_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32h7xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE0 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE3 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 : stm32h7xx_ll_pwr.h
  • LL_PWR_SetAVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetStopModeRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullNone() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullUp() : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SRDCR_VOSRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN6 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_NOPULL : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_PULLDOWN : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_PULLUP : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF1 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF2 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF3 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF4 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF5 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF6 : stm32h7xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32h7xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_128 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_256 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_512 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_64 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_HCLK_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK1_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK2_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK3_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK4_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_SYSCLK_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CalcPLLClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_CDCK_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_CSI_DIV122 : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_CONFIG_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32h7xx_ll_rcc.h
  • LL_RCC_CPUCK_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_DisableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_EnableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_GetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_SetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_D1CK_IsReady : stm32h7xx_ll_rcc.h
  • LL_RCC_D2CK_IsReady : stm32h7xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32h7xx_ll_rcc.c
  • LL_RCC_DFSDM1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_HCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB3Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB4Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetCLKPClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetCLKPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetDFSDM2ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetDFSDM2ClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetDFSDMClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetDFSDMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetFMCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetFMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetKerWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetOSPIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetOSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetPLL1ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetPLL2ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetPLL3ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetRNGClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetRTC_HSEPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSDMMCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSDMMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSPDIFClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSPDIFClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSPIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSWPClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSWPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSysPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSysWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetTIMPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_SelectAnalogClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_SelectDigitalClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DisableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV1 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV2 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV4 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV8 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_EnableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetDivider() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_IsDividerReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_SetDivider() : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_CDRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDG1RST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDG1RST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_KERWAKEUP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_KERWAKEUP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_IsFailureDetected() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SelectAnalogClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SelectDigitalClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_MASK_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLL1PCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_HCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32h7xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL_GetSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL_SetSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_1_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_2_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_4_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_8_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLVCORANGE_MEDIUM : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLVCORANGE_WIDE : stm32h7xx_ll_rcc.h
  • LL_RCC_POS_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_PrescTable : stm32h7xx_ll_rcc.c , stm32h7xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32h7xx_ll_rcc.h
  • LL_RCC_REG_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_17 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_18 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_19 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_20 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_21 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_22 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_23 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_24 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_25 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_26 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_27 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_28 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_29 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_30 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_31 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_32 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_33 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_34 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_35 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_36 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_37 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_38 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_39 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_40 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_41 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_42 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_43 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_44 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_45 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_46 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_47 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_48 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_49 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_50 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_51 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_52 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_53 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_54 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_55 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_56 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_57 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_58 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_59 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_60 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_61 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_62 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_63 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_NOCLOCK : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_SPDIF : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB3Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB4Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetCLKPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetDFSDM2ClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetDFSDMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetFMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetKerWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetOSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRTC_HSEPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSDMMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSPDIFClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSWPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetTIMPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSWAKEUP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSWAKEUP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_TIM_PRESCALER_FOUR_TIMES : stm32h7xx_ll_rcc.h
  • LL_RCC_TIM_PRESCALER_TWICE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_DISABLE : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32h7xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32h7xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32h7xx_ll_rng.h
  • LL_RNG_ClearFlag_CEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_1 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_1024 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_128 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_16 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_16384 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_2 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_2048 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_256 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_32 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_32768 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_4 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_4096 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_512 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_64 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_8 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_8192 : stm32h7xx_ll_rng.h
  • LL_RNG_ConfigLock() : stm32h7xx_ll_rng.h
  • LL_RNG_CR_IE : stm32h7xx_ll_rng.h
  • LL_RNG_CUSTOM_NIST : stm32h7xx_ll_rng.h
  • LL_RNG_DeInit() : stm32h7xx_ll_rng.c
  • LL_RNG_Disable() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_Enable() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_GetClockDivider() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig1() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig2() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig3() : stm32h7xx_ll_rng.h
  • LL_RNG_GetHealthConfig() : stm32h7xx_ll_rng.h
  • LL_RNG_Init() : stm32h7xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsConfigLocked() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_NIST_COMPLIANT : stm32h7xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32h7xx_ll_rng.h
  • LL_RNG_ReadReg : stm32h7xx_ll_rng.h
  • LL_RNG_SetClockDivider() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig1() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig2() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig3() : stm32h7xx_ll_rng.h
  • LL_RNG_SetHealthConfig() : stm32h7xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32h7xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32h7xx_ll_rng.h
  • LL_RNG_StructInit() : stm32h7xx_ll_rng.c
  • LL_RNG_WriteReg : stm32h7xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32h7xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32h7xx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32h7xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32h7xx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32h7xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32h7xx_ll_rtc.h
  • LL_RTC_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ATAMP_INITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ATAMP_SEEDF() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32h7xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32h7xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ALRAF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32h7xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32h7xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_TAMPER_1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_DisableActiveMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_DisableFilter() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_DisableOutputSharing() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableActiveMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableFilter() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableOutputSharing() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP1AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP2AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP3AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32h7xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32h7xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32h7xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32h7xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_SUSP() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_10BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_11BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_12BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_13BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_14BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_15BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_17BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_18BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_19BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_20BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_21BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_22BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_23BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_24BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_25BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_26BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_27BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_28BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_29BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_30BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_31BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_32BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_4BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_5BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_6BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_7BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_9BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32h7xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_17BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_18BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_19BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_20BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_21BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_22BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_23BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_24BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_25BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_26BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_27BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_28BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_29BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_30BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_31BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_32BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DeInit() : stm32h7xx_ll_spi.c
  • LL_SPI_Disable() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32h7xx_ll_spi.h
  • LL_SPI_Enable() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIOLock() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_01DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_02DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_03DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_04DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_05DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_06DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_07DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_08DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_09DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_10DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_11DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_12DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_13DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_14DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_15DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_16DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32h7xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32h7xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32h7xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_GetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_SPI_GetHalfDuplexDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetInterDataIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_GetInternalSSLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_GetMasterSSIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_GetMode() : stm32h7xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32h7xx_ll_spi.h
  • LL_SPI_GetNSSPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_GetReloadSize() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRemainingDataFrames() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxFIFOPackingLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferSize() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRConfiguration() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRDetection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32h7xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_00CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_01CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_02CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_03CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_04CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_05CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_06CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_07CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_08CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_09CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_10CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_11CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_12CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_13CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_14CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_15CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_CRCEIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_DXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_EOTIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_MODFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_OVRIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_RXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TIFREIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TSERFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TXTFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_UDRIE : stm32h7xx_ll_spi.h
  • LL_SPI_Init() : stm32h7xx_ll_spi.c
  • LL_SPI_IsActiveFlag_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXWNE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_SUSP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIOLock() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32h7xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32h7xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32h7xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32h7xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32h7xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32h7xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32h7xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32h7xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32h7xx_ll_spi.h
  • LL_SPI_ReadReg : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData32() : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_0PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_1PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_2PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_3PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RXCRCINIT_ALL_ONES_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32h7xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32h7xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32h7xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_SetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_SPI_SetHalfDuplexDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetInterDataIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_SetInternalSSLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_SetMasterSSIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_SetMode() : stm32h7xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32h7xx_ll_spi.h
  • LL_SPI_SetNSSPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_SetReloadSize() : stm32h7xx_ll_spi.h
  • LL_SPI_SetRxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferSize() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRConfiguration() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRDetection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32h7xx_ll_spi.h
  • LL_SPI_SIMPLEX_TX : stm32h7xx_ll_spi.h
  • LL_SPI_SR_CRCE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_DXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_EOT : stm32h7xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32h7xx_ll_spi.h
  • LL_SPI_SR_RXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_RXWNE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_SUSP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TIFRE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TSERF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXC : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXTF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_UDR : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_00CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_01CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_02CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_03CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_04CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_05CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_06CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_07CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_08CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_09CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_10CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_11CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_12CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_13CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_14CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_15CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_LEVEL_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_SS_LEVEL_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_StartMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_StructInit() : stm32h7xx_ll_spi.c
  • LL_SPI_SuspendMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData16() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData32() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32h7xx_ll_spi.h
  • LL_SPI_TXCRCINIT_ALL_ONES_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_LAST_RECEIVED : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_LAST_TRANSMITTED : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_REGISTER_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_END_DATA_FRAME : stm32h7xx_ll_spi.h
  • LL_SPI_WriteReg : stm32h7xx_ll_spi.h
  • LL_SWPMI_Activate() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_Deactivate() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DeInit() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_DisableDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableLoopback() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableTXBypass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DMA_GetRegAddr() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableLoopback() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableTXBypass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetBitRatePrescaler() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetReceiveFrameLength() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetReceptionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetTransmissionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetVoltageClass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBERF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBFF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXOVRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CSRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTCF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXBEF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXUNRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBERIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBFIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXOVRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_SRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TCIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TXBEIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TXUNRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_Init() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_IsActivated() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_DEACT() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RDYF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXNE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SUSP() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_DEACTF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBERF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBFF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXNE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXOVRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_SRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_SUSP : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TCF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXBEF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXUNRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ReadReg : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ReceiveData32() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_RequestDeactivation() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetBitRatePrescaler() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetReceptionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetTransmissionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetVoltageClass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_StructInit() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_SW_BUFFER_RX_MULTI : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_SINGLE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_MULTI : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_SINGLE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_TransmitData32() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_B : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_C : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_WriteReg : stm32h7xx_ll_swpmi.h
  • LL_SYSCFG_ANALOG_SWITCH_BOOSTEN : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PA0 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PA1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PC2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PC3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_HIGH_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_LOW_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_OFF_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_CELL_CODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_CloseAnalogSwitch() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_16KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_2KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_4KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_8KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTI : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTJ : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTK : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetNMOSCompensationValue() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetPMOSCompensationValue() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CMPCR() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IWDG1_HW_CONTROL_MODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_IWDG1_SW_CONTROL_MODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCGetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCGetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCSetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_OpenAnalogSwitch() : stm32h7xx_ll_system.h
  • LL_SYSCFG_REGISTER_CODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_CM7_LOCKUP : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_VDMMCGetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_VDMMCSetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32h7xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32h7xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32h7xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32h7xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_BKIN_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_DF1BK : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32h7xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32h7xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32h7xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32h7xx_ll_tim.h
  • LL_TIM_DeInit() : stm32h7xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32h7xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32h7xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32h7xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32h7xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32h7xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32h7xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32h7xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32h7xx_ll_tim.h
  • LL_TIM_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32h7xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32h7xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32h7xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_ReadReg : stm32h7xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32h7xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32h7xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32h7xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32h7xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32h7xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32h7xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32h7xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32h7xx_ll_tim.h
  • LL_TIM_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_RCC_LSE : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR10 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR11 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR12 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR13 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR4 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR5 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR6 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR8 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR9 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32h7xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32h7xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32h7xx_ll_tim.h
  • LL_TIM_WriteReg : stm32h7xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32h7xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32h7xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32h7xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32h7xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32h7xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32h7xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32h7xx_ll_usart.h
  • LL_USART_ClockInit() : stm32h7xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32h7xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32h7xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32h7xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32h7xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32h7xx_ll_usart.h
  • LL_USART_DeInit() : stm32h7xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32h7xx_ll_usart.h
  • LL_USART_Disable() : stm32h7xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32h7xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32h7xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_usart.h
  • LL_USART_Enable() : stm32h7xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32h7xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32h7xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32h7xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32h7xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32h7xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32h7xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32h7xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32h7xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32h7xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32h7xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32h7xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32h7xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32h7xx_ll_usart.h
  • LL_USART_GetParity() : stm32h7xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32h7xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32h7xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32h7xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32h7xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32h7xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32h7xx_ll_usart.h
  • LL_USART_Init() : stm32h7xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32h7xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_FE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_NE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_PE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TC : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32h7xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32h7xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32h7xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32h7xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32h7xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32h7xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32h7xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32h7xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32h7xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32h7xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32h7xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32h7xx_ll_usart.h
  • LL_USART_ReadReg : stm32h7xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32h7xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32h7xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32h7xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32h7xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32h7xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32h7xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32h7xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32h7xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32h7xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32h7xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32h7xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32h7xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32h7xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32h7xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32h7xx_ll_usart.h
  • LL_USART_SetParity() : stm32h7xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32h7xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32h7xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32h7xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32h7xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32h7xx_ll_usart.h
  • LL_USART_StructInit() : stm32h7xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32h7xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32h7xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32h7xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32h7xx_ll_usart.h
  • LL_USART_WriteReg : stm32h7xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32h7xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP176_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA216 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA225 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA169 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA176_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP132_SMPS : stm32h7xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32h7xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32h7xx_ll_wwdg.h
  • LPM_L0 : stm32h7xx_hal_pcd.h
  • LPM_L1 : stm32h7xx_hal_pcd.h
  • LPM_L2 : stm32h7xx_hal_pcd.h
  • LPM_L3 : stm32h7xx_hal_pcd.h
  • LPTIM2_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM3_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_Disable() : stm32h7xx_hal_lptim.c
  • LPTIM_FLAG_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32h7xx_hal_lptim.h
  • LPTIM_HandleTypeDef : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_NOT_CONNECTED : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI4_FSA : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI4_FSB : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32h7xx_hal_lptim.h
  • LPTIM_ResetCallback() : stm32h7xx_hal_lptim.c
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32h7xx_hal_lptim.h
  • LPTIM_WaitForFlag() : stm32h7xx_hal_lptim.c
  • LPUART_BRR_MASK : stm32h7xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32h7xx_hal_uart.c
  • LPUART_BRR_MIN : stm32h7xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32h7xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32h7xx_ll_lpuart.h
  • LPUART_PRESCALER_TAB : stm32h7xx_ll_lpuart.h
  • LSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • LSE_VALUE : stm32h7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • LSI_VALUE : stm32h7xx_hal_conf.h
  • LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR_FRAME_BUFFER : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_FU : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_LI : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_RR : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_TE : stm32h7xx_hal_ltdc.h
  • LTDC_HandleTypeDef : stm32h7xx_hal_ltdc.h
  • LTDC_HORIZONTALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_IT_FU : stm32h7xx_hal_ltdc.h
  • LTDC_IT_LI : stm32h7xx_hal_ltdc.h
  • LTDC_IT_RR : stm32h7xx_hal_ltdc.h
  • LTDC_IT_TE : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_1 : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_2 : stm32h7xx_hal_ltdc.h
  • LTDC_LINE_NUMBER : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IIPC : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IPC : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL44 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL88 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB1555 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB4444 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB8888 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_L8 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB565 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB888 : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_IMMEDIATE : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_VERTICAL_BLANKING : stm32h7xx_hal_ltdc.h
  • LTDC_SetConfig() : stm32h7xx_hal_ltdc.c
  • LTDC_STARTPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_STOPPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_VERTICALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AL : stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_LAYER : stm32h7xx_hal_ltdc.h
  • MAX_NBYTE_SIZE : stm32h7xx_hal_i2c.c , stm32h7xx_hal_smbus.c
  • MC_ADDRESS : stm32h7xx_hal_nor.h
  • MCO1_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO1_PIN : stm32h7xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO2_PIN : stm32h7xx_hal_rcc.c
  • MDIOS_ALL_ERRORS_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALL_REG_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALLREG_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_DIN_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_DOUT_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_HandleTypeDef : stm32h7xx_hal_mdios.h
  • MDIOS_InitCallbacksToDefault() : stm32h7xx_hal_mdios.c
  • MDIOS_IT_ERROR : stm32h7xx_hal_mdios.h
  • MDIOS_IT_READ : stm32h7xx_hal_mdios.h
  • MDIOS_IT_WRITE : stm32h7xx_hal_mdios.h
  • MDIOS_PORT_ADDRESS_SHIFT : stm32h7xx_hal_mdios.c
  • MDIOS_PREAMBLE_CHECK_DISABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_CHECK_ENABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG0 : stm32h7xx_hal_mdios.h
  • MDIOS_REG0_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG11 : stm32h7xx_hal_mdios.h
  • MDIOS_REG11_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG12 : stm32h7xx_hal_mdios.h
  • MDIOS_REG12_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG13 : stm32h7xx_hal_mdios.h
  • MDIOS_REG13_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG14 : stm32h7xx_hal_mdios.h
  • MDIOS_REG14_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG15 : stm32h7xx_hal_mdios.h
  • MDIOS_REG15_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG16 : stm32h7xx_hal_mdios.h
  • MDIOS_REG16_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG17 : stm32h7xx_hal_mdios.h
  • MDIOS_REG17_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG18 : stm32h7xx_hal_mdios.h
  • MDIOS_REG18_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG19 : stm32h7xx_hal_mdios.h
  • MDIOS_REG19_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG21 : stm32h7xx_hal_mdios.h
  • MDIOS_REG21_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG22 : stm32h7xx_hal_mdios.h
  • MDIOS_REG22_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG23 : stm32h7xx_hal_mdios.h
  • MDIOS_REG23_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG24 : stm32h7xx_hal_mdios.h
  • MDIOS_REG24_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG25 : stm32h7xx_hal_mdios.h
  • MDIOS_REG25_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG26 : stm32h7xx_hal_mdios.h
  • MDIOS_REG26_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG27 : stm32h7xx_hal_mdios.h
  • MDIOS_REG27_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG28 : stm32h7xx_hal_mdios.h
  • MDIOS_REG28_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG29 : stm32h7xx_hal_mdios.h
  • MDIOS_REG29_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG31 : stm32h7xx_hal_mdios.h
  • MDIOS_REG31_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG4 : stm32h7xx_hal_mdios.h
  • MDIOS_REG4_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG5 : stm32h7xx_hal_mdios.h
  • MDIOS_REG5_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG6 : stm32h7xx_hal_mdios.h
  • MDIOS_REG6_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG7 : stm32h7xx_hal_mdios.h
  • MDIOS_REG7_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG8 : stm32h7xx_hal_mdios.h
  • MDIOS_REG8_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG9 : stm32h7xx_hal_mdios.h
  • MDIOS_REG9_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_START_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_TURNAROUND_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_WAKEUP_EXTI_LINE : stm32h7xx_hal_mdios.h
  • MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_LEFT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_PACKENABLE : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BRT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CRQA : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_TE : stm32h7xx_hal_mdma.h
  • MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_HandleTypeDef : stm32h7xx_hal_mdma.h
  • MDMA_Init() : stm32h7xx_hal_mdma.c
  • MDMA_IT_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_BRT : stm32h7xx_hal_mdma.h
  • MDMA_IT_BT : stm32h7xx_hal_mdma.h
  • MDMA_IT_CTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_TE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_ENDIANNESS_PRESERVE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_LOW : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_MEDIUM : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_CLUT_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TW : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_END_CONVERSION : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_NF : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_NE : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_LTDC_LINE_IT : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI1_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI2_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_COMMAND_END : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_END_DATA : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SW : stm32h7xx_hal_mdma.h
  • MDMA_SetConfig() : stm32h7xx_hal_mdma.c
  • MDMA_SOURCE_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_WORD : stm32h7xx_hal_mdma.h
  • MEMORY0 : stm32h7xx_hal_dma_ex.h
  • MEMORY1 : stm32h7xx_hal_dma_ex.h
  • MMC_BLOCKSIZE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_DMA : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_IT : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_NONE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_DDR_Mode() : stm32h7xx_hal_mmc.c
  • MMC_DMA_BUFFER0 : stm32h7xx_hal_mmc_ex.h
  • MMC_DMA_BUFFER1 : stm32h7xx_hal_mmc_ex.h
  • MMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_HandleTypeDef : stm32h7xx_hal_mmc.h
  • MMC_HIGH_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_HighSpeed() : stm32h7xx_hal_mmc.c
  • MMC_InitCard() : stm32h7xx_hal_mmc.c
  • MMC_InitTypeDef : stm32h7xx_hal_mmc.h
  • MMC_INVALID_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_LOW_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_PowerOFF() : stm32h7xx_hal_mmc.c
  • MMC_PowerON() : stm32h7xx_hal_mmc.c
  • MMC_Read_IT() : stm32h7xx_hal_mmc.c
  • MMC_ReadExtCSD() : stm32h7xx_hal_mmc.c
  • MMC_SendStatus() : stm32h7xx_hal_mmc.c
  • MMC_TypeDef : stm32h7xx_hal_mmc.h
  • MMC_Write_IT() : stm32h7xx_hal_mmc.c
  • MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32h7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER10 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER11 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER12 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER13 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER14 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER15 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER8 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER9 : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_BUSY : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_READID : stm32h7xx_hal_nand.h
  • NAND_CMD_RESET : stm32h7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_DEVICE : stm32h7xx_hal_nand.h
  • NAND_ERROR : stm32h7xx_hal_nand.h
  • NAND_HandleTypeDef : stm32h7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_READY : stm32h7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32h7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32h7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32h7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32h7xx_hal_nor.c
  • NOR_HandleTypeDef : stm32h7xx_hal_nor.h
  • NOR_MASK_STATUS_DQ5 : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32h7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32h7xx_hal_nor.h
  • NOR_TMEOUT : stm32h7xx_hal_nor.h
  • NOR_WRITE : stm32h7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOT_ADD0 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD_BOTH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_AXIM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL0 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_16KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_2KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_4KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_8KB : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STDBY_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STOP_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • OB_USER_VDDMMC_HSLV : stm32h7xx_hal_flash_ex.h
  • OB_VDDMMC_HSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_VDDMMC_HSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0TO3 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_100TO103 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_104TO107 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_108TO111 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_112TO115 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_116TO119 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_120TO123 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_124TO127 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_12TO15 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_16TO19 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_20TO23 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_24TO27 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_28TO31 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_32TO35 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_36TO39 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_40TO43 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_44TO47 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_48TO51 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4TO7 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_52TO55 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_56TO59 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_60TO63 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_64TO67 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_68TO71 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_72TO75 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_76TO79 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_80TO83 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_84TO87 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_88TO91 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_8TO11 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_92TO95 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_96TO99 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_ALL : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32h7xx_hal_flash_ex.h
  • OC1Config() : stm32h7xx_ll_tim.c
  • OC2Config() : stm32h7xx_ll_tim.c
  • OC3Config() : stm32h7xx_ll_tim.c
  • OC4Config() : stm32h7xx_ll_tim.c
  • OC5Config() : stm32h7xx_ll_tim.c
  • OC6Config() : stm32h7xx_ll_tim.c
  • OFFSET_TAB_CCMRx : stm32h7xx_ll_tim.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32h7xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32h7xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_HandleTypeDef : stm32h7xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC2_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_CSR_BIT_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_HSOTR_REGOFFSET : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_STANDALONE_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_VREF_10VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32h7xx_hal_opamp.h
  • OPTIONBYTE_BOOTADD : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_OTP_LOCK : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_SECURE_AREA : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32h7xx_hal_flash_ex.h
  • OSPI_HandleTypeDef : stm32h7xx_hal_ospi.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • pADC_CallbackTypeDef : stm32h7xx_hal_adc.h
  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32h7xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32h7xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32h7xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32h7xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32h7xx_hal_pcd.h
  • PCD_BCD_MsgTypeDef : stm32h7xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32h7xx_hal_pcd.h
  • PCD_EP_OutSetupPacket_int() : stm32h7xx_hal_pcd.c
  • PCD_EP_OutXfrComplete_int() : stm32h7xx_hal_pcd.c
  • PCD_EPTypeDef : stm32h7xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32h7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32h7xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32h7xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32h7xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32h7xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_MAX : stm32h7xx_hal_pcd.c
  • PCD_MIN : stm32h7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32h7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32h7xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32h7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32h7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_TypeDef : stm32h7xx_hal_pcd.h
  • PCD_WriteEmptyTxFifo() : stm32h7xx_hal_pcd.c
  • pCEC_CallbackTypeDef : stm32h7xx_hal_cec.h
  • pCEC_RxCallbackTypeDef : stm32h7xx_hal_cec.h
  • pCOMP_CallbackTypeDef : stm32h7xx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32h7xx_hal_cryp.h
  • pDAC_CallbackTypeDef : stm32h7xx_hal_dac.h
  • pDCMI_CallbackTypeDef : stm32h7xx_hal_dcmi.h
  • pDFSDM_Channel_CallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pDFSDM_Filter_AwdCallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pDFSDM_Filter_CallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pFDCAN_CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_ClockCalibrationCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_GlobalTimeCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_ScheduleSyncCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_StopWatchCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_TimeMarkCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFlash : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • pGFXMMU_CallbackTypeDef : stm32h7xx_hal_gfxmmu.h
  • pHASH_CallbackTypeDef : stm32h7xx_hal_hash.h
  • pHCD_CallbackTypeDef : stm32h7xx_hal_hcd.h
  • pHCD_HC_NotifyURBChangeCallbackTypeDef : stm32h7xx_hal_hcd.h
  • pI2C_AddrCallbackTypeDef : stm32h7xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32h7xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32h7xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32h7xx_hal_irda.h
  • pJPEG_CallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_DataReadyCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_GetDataCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_InfoReadyCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • PLL2_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL3_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • pLPTIM_CallbackTypeDef : stm32h7xx_hal_lptim.h
  • pLTDC_CallbackTypeDef : stm32h7xx_hal_ltdc.h
  • pMDIOS_CallbackTypeDef : stm32h7xx_hal_mdios.h
  • pMMC_CallbackTypeDef : stm32h7xx_hal_mmc.h
  • pNAND_CallbackTypeDef : stm32h7xx_hal_nand.h
  • pNOR_CallbackTypeDef : stm32h7xx_hal_nor.h
  • pOPAMP_CallbackTypeDef : stm32h7xx_hal_opamp.h
  • pOSPI_CallbackTypeDef : stm32h7xx_hal_ospi.h
  • pPCD_BcdCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPSSI_CallbackTypeDef : stm32h7xx_hal_pssi.h
  • pRNG_CallbackTypeDef : stm32h7xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32h7xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32h7xx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32h7xx_hal_sai.h
  • pSD_CallbackTypeDef : stm32h7xx_hal_sd.h
  • pSD_TransceiverCallbackTypeDef : stm32h7xx_hal_sd.h
  • pSDRAM_CallbackTypeDef : stm32h7xx_hal_sdram.h
  • pSDRAM_DmaCallbackTypeDef : stm32h7xx_hal_sdram.h
  • pSMARTCARD_CallbackTypeDef : stm32h7xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32h7xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32h7xx_hal_smbus.h
  • pSPDIFRX_CallbackTypeDef : stm32h7xx_hal_spdifrx.h
  • pSPI_CallbackTypeDef : stm32h7xx_hal_spi.h
  • pSRAM_CallbackTypeDef : stm32h7xx_hal_sram.h
  • pSRAM_DmaCallbackTypeDef : stm32h7xx_hal_sram.h
  • PSSI_CR_16BITS : stm32h7xx_hal_pssi.h
  • PSSI_CR_8BITS : stm32h7xx_hal_pssi.h
  • PSSI_CR_DMA_DISABLE : stm32h7xx_hal_pssi.h
  • PSSI_CR_DMA_ENABLE : stm32h7xx_hal_pssi.h
  • PSSI_CR_OUTEN_INPUT : stm32h7xx_hal_pssi.h
  • PSSI_CR_OUTEN_OUTPUT : stm32h7xx_hal_pssi.h
  • PSSI_DMAAbort() : stm32h7xx_hal_pssi.c
  • PSSI_DMAError() : stm32h7xx_hal_pssi.c
  • PSSI_DMAReceiveCplt() : stm32h7xx_hal_pssi.c
  • PSSI_DMATransmitCplt() : stm32h7xx_hal_pssi.c
  • PSSI_Error() : stm32h7xx_hal_pssi.c
  • PSSI_FLAG_MASK : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_OVR_MIS : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_OVR_RIS : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_RTT1B : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_RTT4B : stm32h7xx_hal_pssi.h
  • PSSI_HandleTypeDef : stm32h7xx_hal_pssi.h
  • PSSI_MAX_NBYTE_SIZE : stm32h7xx_hal_pssi.h
  • PSSI_TIMEOUT_TRANSMIT : stm32h7xx_hal_pssi.h
  • PSSI_WaitOnStatusUntilTimeout() : stm32h7xx_hal_pssi.c
  • pSWPMI_CallbackTypeDef : stm32h7xx_hal_swpmi.h
  • pTIM_CallbackTypeDef : stm32h7xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32h7xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32h7xx_hal_usart.h
  • PVD_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32h7xx_hal_pwr.c
  • PVD_MODE_IT : stm32h7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PWR_AVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_NORMAL : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_0 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_1 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_2 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_3 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_CPU_FLAGS : stm32h7xx_hal_pwr_ex.h
  • PWR_D1_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_RUN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_STOP : stm32h7xx_hal_pwr_ex.h
  • PWR_DIRECT_SMPS_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EWUP_MASK : stm32h7xx_hal_pwr.h
  • PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_AVD : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32h7xx_hal_pwr.h
  • PWR_EXTI_WAKEUP_PINS_MASK : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_ACTVOS : stm32h7xx_hal_pwr.h
  • PWR_FLAG_ACTVOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_AVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32h7xx_hal_pwr.h
  • PWR_FLAG_MMCVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SETTING_DELAY : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_SMPSEXTRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_STOP : stm32h7xx_hal_pwr.h
  • PWR_FLAG_TEMPH : stm32h7xx_hal_pwr.h
  • PWR_FLAG_TEMPL : stm32h7xx_hal_pwr.h
  • PWR_FLAG_USB33RDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VBATH : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VBATL : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP1 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP2 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP3 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP4 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP5 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP6 : stm32h7xx_hal_pwr.h
  • PWR_GFXMMU_JPEG_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_LDO_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MEMORY_BLOCK_KEEP_ON : stm32h7xx_hal_pwr_ex.h
  • PWR_MEMORY_BLOCK_SHUT_OFF : stm32h7xx_hal_pwr_ex.h
  • PWR_MMC_VOLTAGE_BELOW_1V2 : stm32h7xx_hal_pwr_ex.h
  • PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_NO_PULL : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_DOWN : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_UP : stm32h7xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32h7xx_hal_pwr.h
  • PWR_RAM1_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM1_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM2_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM2_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM3_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE3 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE4 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE5 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE0 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SMPS_1V8_SUPPLIES_EXT : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_1V8_SUPPLIES_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_EXT : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SRD_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_STOPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SUPPLY_CONFIG_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_TCM_ECM_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_USB_FDCAN_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG_ALL : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET : stm32h7xx_hal_pwr_ex.c
  • PWREx_MMC_VoltageLevel : stm32h7xx_hal_pwr_ex.h
  • pWWDG_CallbackTypeDef : stm32h7xx_hal_wwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RAMECC_FLAG_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAG_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAG_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAGS_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_HandleTypeDef : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ENABLE : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ID : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_ID : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RCC_ADCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_APB1_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_CECCLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_D1PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_D3PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_CSI_ON : stm32h7xx_hal_rcc.h
  • RCC_CSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SRDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CDCKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CDRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CPUCKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIDIV : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_IWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_WWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FMCCLKSOURCE_CDHCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • RCC_GetHCLKClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK3ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK4ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_HSE_BYPASS_DIGITAL : stm32h7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSE_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI48_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI_ON : stm32h7xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_I2C123CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_IT_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_CSS : stm32h7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32h7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_LSE_BYPASS_DIGITAL : stm32h7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSE_ON : stm32h7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSI_ON : stm32h7xx_hal_rcc.h
  • RCC_MCO1 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2 : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_CSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_10 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_11 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_12 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_13 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_14 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_15 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_6 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_7 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_9 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_CSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32h7xx_hal_rcc.h
  • RCC_OSPICLKSOURCE_CDHCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_ADC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CKPER : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DSI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C123 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM345 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LTDC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_OSPI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2A : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2B : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI123 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI45 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART9 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART10 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART16 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART16910 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART234578 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL1_DIVP : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVQ : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVR : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_0 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_1 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_2 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_3 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOMEDIUM : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOWIDE : stm32h7xx_hal_rcc.h
  • RCC_PLL2_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32h7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32h7xx_hal_rcc.h
  • RCC_PLL_ON : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32h7xx_hal_rcc.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV33 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV34 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV35 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV36 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV37 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV38 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV39 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV40 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV41 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV42 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV43 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV44 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV45 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV46 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV47 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV48 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV49 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV50 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV51 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV52 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV53 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV54 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV55 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV56 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV57 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV58 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV59 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV60 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV61 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV62 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV63 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32h7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_SPDIF : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_SPDIF : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_STOP_KERWAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_KERWAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_CDPCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_CDPCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_WWDG1 : stm32h7xx_hal_rcc_ex.h
  • RCCEx_PLL2_Config() : stm32h7xx_hal_rcc_ex.c
  • RCCEx_PLL3_Config() : stm32h7xx_hal_rcc_ex.c
  • REV_ID_B : stm32h7xx_hal.h
  • REV_ID_V : stm32h7xx_hal.h
  • REV_ID_X : stm32h7xx_hal.h
  • REV_ID_Y : stm32h7xx_hal.h
  • RISING_EDGE : stm32h7xx_hal_gpio.c
  • RNG_CED_DISABLE : stm32h7xx_hal_rng.h
  • RNG_CED_ENABLE : stm32h7xx_hal_rng.h
  • RNG_CLKDIV_BY_1 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_1024 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_128 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_16 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_16384 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_2 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_2048 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_256 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_32 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_32768 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_4 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_4096 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_512 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_64 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_8 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_8192 : stm32h7xx_hal_rng_ex.h
  • RNG_CUSTOM_NIST : stm32h7xx_hal_rng_ex.h
  • RNG_FLAG_CECS : stm32h7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32h7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32h7xx_hal_rng.h
  • RNG_HandleTypeDef : stm32h7xx_hal_rng.h
  • RNG_HTCFG : stm32h7xx_hal_rng.c , stm32h7xx_hal_rng_ex.c
  • RNG_HTCFG_1 : stm32h7xx_hal_rng.c , stm32h7xx_hal_rng_ex.c
  • RNG_IT_CEI : stm32h7xx_hal_rng.h
  • RNG_IT_DRDY : stm32h7xx_hal_rng.h
  • RNG_IT_SEI : stm32h7xx_hal_rng.h
  • RNG_NIST_COMPLIANT : stm32h7xx_hal_rng_ex.h
  • RNG_TIMEOUT_VALUE : stm32h7xx_hal_rng_ex.c , stm32h7xx_hal_rng.c
  • RTC_ALARM_A : stm32h7xx_hal_rtc.h
  • RTC_ALARM_B : stm32h7xx_hal_rtc.h
  • RTC_ALARM_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32h7xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32h7xx_ll_rtc.c
  • RTC_ATAMP_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_5 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_6 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_7 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_128 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_16 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_32 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_64 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_FILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_FILTER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_INTERRUPT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_INTERRUPT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_SEED_NB_UINT32 : stm32h7xx_hal_rtc_ex.h
  • RTC_Bcd2ToByte() : stm32h7xx_hal_rtc.c
  • RTC_BKP_DR0 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32h7xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32h7xx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32h7xx_hal_rtc.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_DR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32h7xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP2F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP3F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32h7xx_hal_rtc.h
  • RTC_HandleTypeDef : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32h7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32h7xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32h7xx_ll_rtc.c
  • RTC_INT_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER1_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER2_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER3_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER4_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER5_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER6_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER8_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP1 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP2 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP3 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMPALL : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32h7xx_hal_rtc.h
  • RTC_IT_WUT : stm32h7xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32h7xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32h7xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32h7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32h7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32h7xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32h7xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32h7xx_hal_rtc.h
  • RTC_RSF_MASK : stm32h7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32h7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32h7xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32h7xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32h7xx_ll_rtc.c
  • RTC_TAMP_NB : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERDETECTIONOUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERDETECTIONOUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32h7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32h7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32h7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32h7xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32h7xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32h7xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32h7xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32h7xx_hal_uart_ex.c , stm32h7xx_hal_usart_ex.c , stm32h7xx_hal_smartcard_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32h7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_Disable() : stm32h7xx_hal_sai.c
  • SAI_DMAAbort() : stm32h7xx_hal_sai.c
  • SAI_DMAError() : stm32h7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32h7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32h7xx_hal_sai.h
  • SAI_FillFifo() : stm32h7xx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32h7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32h7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32h7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32h7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32h7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32h7xx_hal_sai.h
  • SAI_HandleTypeDef : stm32h7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32h7xx_hal_sai.h
  • SAI_InitI2S() : stm32h7xx_hal_sai.c
  • SAI_InitPCM() : stm32h7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32h7xx_hal_sai.c
  • SAI_IT_AFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32h7xx_hal_sai.h
  • SAI_IT_FREQ : stm32h7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32h7xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MODE_DMA : stm32h7xx_hal_sai.c
  • SAI_MODE_IT : stm32h7xx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32h7xx_hal_sai.h
  • SAI_ModeTypedef : stm32h7xx_hal_sai.c
  • SAI_MONOMODE : stm32h7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PCM_LONG : stm32h7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32h7xx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32h7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_STEREOMODE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32h7xx_hal_sai.h
  • SAI_Transmit_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ZERO_VALUE : stm32h7xx_hal_sai.h
  • SAIcallback : stm32h7xx_hal_sai.h
  • SD_CONTEXT_DMA : stm32h7xx_hal_sd.h
  • SD_CONTEXT_IT : stm32h7xx_hal_sd.h
  • SD_CONTEXT_NONE : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_DDR_Mode() : stm32h7xx_hal_sd.c
  • SD_DMA_BUFFER0 : stm32h7xx_hal_sd_ex.h
  • SD_DMA_BUFFER1 : stm32h7xx_hal_sd_ex.h
  • SD_FindSCR() : stm32h7xx_hal_sd.c
  • SD_GET_DLYB_INSTANCE : stm32h7xx_hal_sd.c
  • SD_HandleTypeDef : stm32h7xx_hal_sd.h
  • SD_HighSpeed() : stm32h7xx_hal_sd.c
  • SD_InitCard() : stm32h7xx_hal_sd.c
  • SD_InitTypeDef : stm32h7xx_hal_sd.h
  • SD_PowerOFF() : stm32h7xx_hal_sd.c
  • SD_PowerON() : stm32h7xx_hal_sd.c
  • SD_Read_IT() : stm32h7xx_hal_sd.c
  • SD_SendSDStatus() : stm32h7xx_hal_sd.c
  • SD_SendStatus() : stm32h7xx_hal_sd.c
  • SD_TypeDef : stm32h7xx_hal_sd.h
  • SD_UltraHighSpeed() : stm32h7xx_hal_sd.c
  • SD_WideBus_Disable() : stm32h7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32h7xx_hal_sd.c
  • SD_Write_IT() : stm32h7xx_hal_sd.c
  • SDRAM_HandleTypeDef : stm32h7xx_hal_sdram.h
  • SHIFT_TAB_CCxP : stm32h7xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32h7xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32h7xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32h7xx_ll_tim.h
  • SlaveAddr_MSK : stm32h7xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32h7xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_CSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CR_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_FIFOMODE_DISABLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_HandleTypeDef : stm32h7xx_hal_smartcard.h
  • SMARTCARD_InitCallbacksToDefault() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_ISR_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RxISR() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TxISR() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32h7xx_hal_smartcard.h
  • SMARTCARDEx_SetNbDataToProcess() : stm32h7xx_hal_smartcard_ex.c
  • SMBUS_ADDRESSINGMODE_10BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32h7xx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32h7xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32h7xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_HandleTypeDef : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32h7xx_hal_smbus.h
  • SMBUS_ITErrorHandler() : stm32h7xx_hal_smbus.c
  • SMBUS_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32h7xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32h7xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32h7xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smbus.c
  • SPDIFRX_CHANNEL_A : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DMACxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_FLAG_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_HandleTypeDef : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_STATE_IDLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spdifrx.c
  • SPI_1LINE_RX : stm32h7xx_hal_spi.h
  • SPI_1LINE_TX : stm32h7xx_hal_spi.h
  • SPI_AbortTransfer() : stm32h7xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32h7xx_hal_spi.h
  • SPI_CloseTransfer() : stm32h7xx_hal_spi.c
  • SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_10BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_11BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_12BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_13BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_14BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_15BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_16BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_17BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_18BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_19BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_20BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_21BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_22BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_23BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_24BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_25BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_26BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_27BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_28BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_29BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_30BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_31BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_32BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_4BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_5BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_6BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_7BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_9BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_17BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_18BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_19BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_20BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_21BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_22BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_23BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_24BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_25BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_26BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_27BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_28BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_29BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_30BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_31BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_32BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32h7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32h7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32h7xx_hal_spi.c
  • SPI_DMAError() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_09DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_10DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_11DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_12DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_13DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_14DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_15DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_16DATA : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32h7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32h7xx_hal_spi.h
  • SPI_FLAG_DXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_EOT : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32h7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32h7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXWNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_SUSP : stm32h7xx_hal_spi.h
  • SPI_FLAG_TSERF : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXC : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXTF : stm32h7xx_hal_spi.h
  • SPI_FLAG_UDR : stm32h7xx_hal_spi.h
  • SPI_GetPacketSize() : stm32h7xx_hal_spi.c
  • SPI_HandleTypeDef : stm32h7xx_hal_spi.h
  • SPI_HIGHEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_IT_CRCERR : stm32h7xx_hal_spi.h
  • SPI_IT_DXP : stm32h7xx_hal_spi.h
  • SPI_IT_EOT : stm32h7xx_hal_spi.h
  • SPI_IT_ERR : stm32h7xx_hal_spi.h
  • SPI_IT_FRE : stm32h7xx_hal_spi.h
  • SPI_IT_MODF : stm32h7xx_hal_spi.h
  • SPI_IT_OVR : stm32h7xx_hal_spi.h
  • SPI_IT_RXP : stm32h7xx_hal_spi.h
  • SPI_IT_TSERF : stm32h7xx_hal_spi.h
  • SPI_IT_TXP : stm32h7xx_hal_spi.h
  • SPI_IT_TXTF : stm32h7xx_hal_spi.h
  • SPI_IT_UDR : stm32h7xx_hal_spi.h
  • SPI_LOWEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32h7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32h7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32h7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32h7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_0PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_1PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_2PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_3PACKET : stm32h7xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_UNDERRUN_BEHAV_LAST_RECEIVED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_REGISTER_PATTERN : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_END_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spi.c
  • SRAM_HandleTypeDef : stm32h7xx_hal_sram.h
  • SRDCCIP : stm32h7xx_ll_rcc.h
  • SWPMI_DMAAbortOnError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_FLAG_DEACTF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RDYF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32h7xx_hal_swpmi.h
  • SWPMI_HandleTypeDef : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RDYIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32h7xx_hal_swpmi.h
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32h7xx_hal_swpmi.c
  • SYSCFG_BOOT_ADDR0 : stm32h7xx_hal.h
  • SYSCFG_BOOT_ADDR1 : stm32h7xx_hal.h
  • SYSCFG_CELL_CODE : stm32h7xx_hal.h
  • SYSCFG_ETH_MII : stm32h7xx_hal.h
  • SYSCFG_ETH_RMII : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32h7xx_hal.h
  • SYSCFG_REGISTER_CODE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_OPEN : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3 : stm32h7xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32h7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TAMP_ALL : stm32h7xx_hal_rtc_ex.c
  • TAMP_OFFSET : stm32h7xx_hal_rtc_ex.h
  • TEMPSENSOR_CAL1_ADDR : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32h7xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32h7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32h7xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_BREAK2_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32h7xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_CALC_DTS : stm32h7xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32h7xx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32h7xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR5 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR6 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32h7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_COM : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32h7xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_SR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32h7xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32h7xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMAError() : stm32h7xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32h7xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32h7xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32h7xx_hal_tim.h
  • TIM_FLAG_COM : stm32h7xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32h7xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32h7xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32h7xx_hal_tim.h
  • TIM_HandleTypeDef : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_IT_BREAK : stm32h7xx_hal_tim.h
  • TIM_IT_CC1 : stm32h7xx_hal_tim.h
  • TIM_IT_CC2 : stm32h7xx_hal_tim.h
  • TIM_IT_CC3 : stm32h7xx_hal_tim.h
  • TIM_IT_CC4 : stm32h7xx_hal_tim.h
  • TIM_IT_COM : stm32h7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32h7xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32h7xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32h7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32h7xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_ResetCallback() : stm32h7xx_hal_tim.c
  • TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32h7xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TIM12_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM12_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM12_TI1_RMP_SPDIF_FS : stm32h7xx_ll_tim.h
  • TIM_TIM12_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_CSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_MCO2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_CSI : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_LSE : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_MCO2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM2_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM3_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM4_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM4_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM2_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM3_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM4_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM4_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_RCC_LSE : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_RCC_LSI : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_WKUP_IT : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_WKUP_IT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_HSE1MHZ : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_MCO1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_RCC_HSE1MHZ : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_RCC_MCO1 : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_SPDIF_FS : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM1_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM23_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM24_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI4_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI4_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_SOC : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_RMP_CAN_RTP : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_CAN_SOC : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_CAN_TMP : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM2_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM3_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM5_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI4_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI4_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_RMP_CAN_RTP : stm32h7xx_ll_tim.h
  • TIM_TIM5_TI1_RMP_CAN_TMP : stm32h7xx_ll_tim.h
  • TIM_TIM5_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM8_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TRGO2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_TS_ETRF : stm32h7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR10 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR11 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR12 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR13 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR4 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR5 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR6 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR7 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR8 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR9 : stm32h7xx_hal_tim.h
  • TIM_TS_NONE : stm32h7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32h7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32h7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32h7xx_hal_tim.h
  • TIMEOUT : stm32h7xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32h7xx_hal_dac.c
  • TIMEx_DMACommutationCplt() : stm32h7xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32h7xx_hal_tim_ex.c
  • TIMING_CLEAR_MASK : stm32h7xx_hal_smbus.c , stm32h7xx_hal_i2c.c
  • TIMx_AF1_BKCOMP1E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP1P : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP2E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP2P : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKDF1BK0E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKINE : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKINP : stm32h7xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP1E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP1P : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP2E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP2P : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2DF1BK1E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2INE : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2INP : stm32h7xx_ll_tim.h
  • TS_TIMEOUT_MS : stm32h7xx_hal_dts.c
  • TX_FIFO_DEPTH : stm32h7xx_hal_usart_ex.c , stm32h7xx_hal_uart_ex.c , stm32h7xx_hal_smartcard_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32h7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32h7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32h7xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32h7xx_hal_uart.h
  • UART_BRR_MAX : stm32h7xx_hal_uart.c
  • UART_BRR_MIN : stm32h7xx_hal_uart.c
  • UART_CheckIdleState() : stm32h7xx_hal_uart.c
  • UART_CLEAR_CMF : stm32h7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32h7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32h7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32h7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • UART_CLEAR_WUF : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_CSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32h7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32h7xx_hal_uart.h
  • UART_DIV_LPUART : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32h7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32h7xx_hal_uart.c
  • UART_DMAError() : stm32h7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_EndRxTransfer() : stm32h7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32h7xx_hal_uart.c
  • UART_EndTxTransfer() : stm32h7xx_hal_uart.c
  • UART_FIFOMODE_DISABLE : stm32h7xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32h7xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32h7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32h7xx_hal_uart.h
  • UART_FLAG_CMF : stm32h7xx_hal_uart.h
  • UART_FLAG_CTS : stm32h7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32h7xx_hal_uart.h
  • UART_FLAG_FE : stm32h7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32h7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32h7xx_hal_uart.h
  • UART_FLAG_NE : stm32h7xx_hal_uart.h
  • UART_FLAG_ORE : stm32h7xx_hal_uart.h
  • UART_FLAG_PE : stm32h7xx_hal_uart.h
  • UART_FLAG_REACK : stm32h7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32h7xx_hal_uart.h
  • UART_FLAG_RWU : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFF : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32h7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32h7xx_hal_uart.h
  • UART_FLAG_TC : stm32h7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32h7xx_hal_uart.h
  • UART_FLAG_TXE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_WUF : stm32h7xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32h7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32h7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32h7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32h7xx_hal_uart.h
  • UART_HandleTypeDef : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32h7xx_hal_uart.h
  • UART_InitCallbacksToDefault() : stm32h7xx_hal_uart.c
  • UART_INSTANCE_LOWPOWER : stm32h7xx_hal_uart.h
  • UART_IT_CM : stm32h7xx_hal_uart.h
  • UART_IT_CTS : stm32h7xx_hal_uart.h
  • UART_IT_ERR : stm32h7xx_hal_uart.h
  • UART_IT_FE : stm32h7xx_hal_uart.h
  • UART_IT_IDLE : stm32h7xx_hal_uart.h
  • UART_IT_LBD : stm32h7xx_hal_uart.h
  • UART_IT_MASK : stm32h7xx_hal_uart.h
  • UART_IT_NE : stm32h7xx_hal_uart.h
  • UART_IT_ORE : stm32h7xx_hal_uart.h
  • UART_IT_PE : stm32h7xx_hal_uart.h
  • UART_IT_RTO : stm32h7xx_hal_uart.h
  • UART_IT_RXFF : stm32h7xx_hal_uart.h
  • UART_IT_RXFNE : stm32h7xx_hal_uart.h
  • UART_IT_RXFT : stm32h7xx_hal_uart.h
  • UART_IT_RXNE : stm32h7xx_hal_uart.h
  • UART_IT_TC : stm32h7xx_hal_uart.h
  • UART_IT_TXE : stm32h7xx_hal_uart.h
  • UART_IT_TXFE : stm32h7xx_hal_uart.h
  • UART_IT_TXFNF : stm32h7xx_hal_uart.h
  • UART_IT_TXFT : stm32h7xx_hal_uart.h
  • UART_IT_WUF : stm32h7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32h7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32h7xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32h7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32h7xx_hal_uart.h
  • UART_MODE_TX : stm32h7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32h7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32h7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32h7xx_hal_uart.h
  • UART_PARITY_NONE : stm32h7xx_hal_uart.h
  • UART_PARITY_ODD : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32h7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart_ex.h
  • UART_RxISR_16BIT() : stm32h7xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32h7xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_SENDBREAK_REQUEST : stm32h7xx_hal_uart.h
  • UART_SetConfig() : stm32h7xx_hal_uart.c
  • UART_STATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32h7xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart_ex.h
  • UART_TxISR_16BIT() : stm32h7xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32h7xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32h7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32h7xx_hal_uart_ex.h
  • UARTEx_SetNbDataToProcess() : stm32h7xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32h7xx_hal_uart_ex.c
  • UID_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • USART_BRR_MAX : stm32h7xx_hal_irda.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_BRR_MIN : stm32h7xx_hal_irda.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CheckIdleState() : stm32h7xx_hal_usart.c
  • USART_CLEAR_FEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32h7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32h7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32h7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_CSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32h7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_uart.c , stm32h7xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32h7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CR3_FIELDS : stm32h7xx_hal_usart.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_uart.c
  • USART_CR_MASK : stm32h7xx_hal_usart.h
  • USART_CR_POS : stm32h7xx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32h7xx_hal_usart.h
  • USART_DMAAbortOnError() : stm32h7xx_hal_usart.c
  • USART_DMAError() : stm32h7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32h7xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32h7xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DUMMY_DATA : stm32h7xx_hal_usart.c
  • USART_EndTransfer() : stm32h7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32h7xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32h7xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32h7xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32h7xx_hal_usart.h
  • USART_FLAG_FE : stm32h7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32h7xx_hal_usart.h
  • USART_FLAG_NE : stm32h7xx_hal_usart.h
  • USART_FLAG_ORE : stm32h7xx_hal_usart.h
  • USART_FLAG_PE : stm32h7xx_hal_usart.h
  • USART_FLAG_REACK : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFF : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32h7xx_hal_usart.h
  • USART_FLAG_TC : stm32h7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32h7xx_hal_usart.h
  • USART_FLAG_TXE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_UDR : stm32h7xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32h7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32h7xx_hal_usart.h
  • USART_HandleTypeDef : stm32h7xx_hal_usart.h
  • USART_InitCallbacksToDefault() : stm32h7xx_hal_usart.c
  • USART_ISR_MASK : stm32h7xx_hal_usart.h
  • USART_ISR_POS : stm32h7xx_hal_usart.h
  • USART_IT_ERR : stm32h7xx_hal_usart.h
  • USART_IT_FE : stm32h7xx_hal_usart.h
  • USART_IT_IDLE : stm32h7xx_hal_usart.h
  • USART_IT_MASK : stm32h7xx_hal_usart.h
  • USART_IT_NE : stm32h7xx_hal_usart.h
  • USART_IT_ORE : stm32h7xx_hal_usart.h
  • USART_IT_PE : stm32h7xx_hal_usart.h
  • USART_IT_RXFF : stm32h7xx_hal_usart.h
  • USART_IT_RXFNE : stm32h7xx_hal_usart.h
  • USART_IT_RXFT : stm32h7xx_hal_usart.h
  • USART_IT_RXNE : stm32h7xx_hal_usart.h
  • USART_IT_TC : stm32h7xx_hal_usart.h
  • USART_IT_TXE : stm32h7xx_hal_usart.h
  • USART_IT_TXFE : stm32h7xx_hal_usart.h
  • USART_IT_TXFNF : stm32h7xx_hal_usart.h
  • USART_IT_TXFT : stm32h7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32h7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32h7xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32h7xx_hal_usart_ex.h
  • USART_MODE_RX : stm32h7xx_hal_usart.h
  • USART_MODE_TX : stm32h7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32h7xx_hal_usart.h
  • USART_NSS_HARD : stm32h7xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32h7xx_hal_usart_ex.h
  • USART_OVERSAMPLING_16 : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32h7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32h7xx_hal_usart.h
  • USART_PARITY_NONE : stm32h7xx_hal_usart.h
  • USART_PARITY_ODD : stm32h7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32h7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32h7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32h7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_TAB : stm32h7xx_ll_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart_ex.h
  • USART_RxISR_16BIT() : stm32h7xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32h7xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_SetConfig() : stm32h7xx_hal_usart.c
  • USART_SLAVEMODE_DISABLE : stm32h7xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32h7xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32h7xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32h7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart_ex.h
  • USART_TxISR_16BIT() : stm32h7xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32h7xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32h7xx_hal_usart_ex.h
  • USARTEx_SetNbDataToProcess() : stm32h7xx_hal_usart_ex.c
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_CEC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DCMI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DFSDM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DMA2D_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DSI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DTS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_ETH_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_GFXMMU_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HASH_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HCD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HRTIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_JPEG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_LTDC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_MDIOS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_MMC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_NAND_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_NOR_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OPAMP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OSPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OTFDEC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SDRAM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SPDIFRX_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SRAM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SWPMI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_RTOS : stm32h7xx_hal_conf.h
  • USE_SD_TRANSCEIVER : stm32h7xx_hal_conf.h
  • USE_SPI_CRC : stm32h7xx_hal_conf.h
  • UTILS_CalculateFlashLatency() : stm32h7xx_ll_utils.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32h7xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32h7xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32h7xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32h7xx_ll_utils.c
  • UTILS_IsPLLsReady() : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX1 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX2 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX4 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN1 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN2 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN4 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_MEDIUM_OUTPUT_MAX : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_MEDIUM_OUTPUT_MIN : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_WIDE_OUTPUT_MAX : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_WIDE_OUTPUT_MIN : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY3_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY4_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32h7xx_ll_utils.c
  • uwNORMemoryDataWidth : stm32h7xx_hal_nor.c
  • uwTick : stm32h7xx_hal.c , stm32h7xx_hal.h
  • uwTickFreq : stm32h7xx_hal.h , stm32h7xx_hal.c
  • uwTickPrio : stm32h7xx_hal.c , stm32h7xx_hal.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • v_dfsdm1ChannelCounter : stm32h7xx_hal_dfsdm.c
  • v_dfsdm2ChannelCounter : stm32h7xx_hal_dfsdm.c
  • VDD_VALUE : stm32h7xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32h7xx_hal.c
  • VREFINT_CAL_ADDR : stm32h7xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32h7xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32h7xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32h7xx_hal_wwdg.h
  • WWDG_HandleTypeDef : stm32h7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32h7xx_hal_wwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- a -

  • ADC_ConfigureBoostMode() : stm32h7xx_hal_adc.c
  • ADC_ConversionStop() : stm32h7xx_hal_adc.c
  • ADC_Disable() : stm32h7xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DMAError() : stm32h7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32h7xx_hal_adc.c
  • ADC_Enable() : stm32h7xx_hal_adc.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- c -

  • CRC_Handle_16() : stm32h7xx_hal_crc.c
  • CRC_Handle_8() : stm32h7xx_hal_crc.c
  • CRYP_AES_Decrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_DMAError() : stm32h7xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32h7xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32h7xx_hal_cryp.c
  • CRYP_SetKey() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_Process() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnBUSYFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnIFEMFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnOFNEFlag() : stm32h7xx_hal_cryp.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- d -

  • DAC_DMAConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DCMI_DMAError() : stm32h7xx_hal_dcmi.c
  • DCMI_DMAXferCplt() : stm32h7xx_hal_dcmi.c
  • DelayBlock_Configure() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DelayBlock_Disable() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DelayBlock_Enable() : stm32h7xx_ll_delayblock.c , stm32h7xx_ll_delayblock.h
  • DFSDM_DMAError() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32h7xx_hal_dfsdm.c
  • DMA2D_SetConfig() : stm32h7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CheckFifoParam() : stm32h7xx_hal_dma.c
  • DMA_MultiBufferSetConfig() : stm32h7xx_hal_dma_ex.c
  • DMA_SetConfig() : stm32h7xx_hal_dma.c
  • DTS_ResetCallback() : stm32h7xx_hal_dts.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- f -

  • FDCAN_CalcultateRamBlockAddresses() : stm32h7xx_hal_fdcan.c
  • FDCAN_CopyMessageToRAM() : stm32h7xx_hal_fdcan.c
  • FLASH_CRC_AddSector() : stm32h7xx_hal_flash_ex.c
  • FLASH_CRC_SelectAddress() : stm32h7xx_hal_flash_ex.c
  • FLASH_CRC_WaitForLastOperation() : stm32h7xx_hal_flash.c
  • FLASH_Erase_Sector() : stm32h7xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BootAddConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAdd() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetSecureArea() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_OTP_GetLock() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_OTP_LockConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_SecureAreaConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_WaitForLastOperation() : stm32h7xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32h7xx_hal_flash.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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  • u

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32h7xx_hal_adc.c
  • HAL_ADC_Init() : stm32h7xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32h7xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32h7xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32h7xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_FactorLoad() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_CEC_ChangeRxBuffer() : stm32h7xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_ErrorCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32h7xx_hal_cec.c
  • HAL_CEC_Init() : stm32h7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32h7xx_hal_cec.c
  • HAL_CEC_MspDeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_RegisterCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_RegisterRxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32h7xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32h7xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_UnRegisterCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_UnRegisterRxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetError() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetState() : stm32h7xx_hal_comp.c
  • HAL_COMP_Init() : stm32h7xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32h7xx_hal_comp.c
  • HAL_COMP_Lock() : stm32h7xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_RegisterCallback() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32h7xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32h7xx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32h7xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32h7xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32h7xx_hal_crc.c
  • HAL_CRC_GetState() : stm32h7xx_hal_crc.c
  • HAL_CRC_Init() : stm32h7xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32h7xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32h7xx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32h7xx_hal_crc_ex.c
  • HAL_CRYP_Decrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_ErrorCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MspDeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_RegisterCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_UnRegisterCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetError() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Init() : stm32h7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32h7xx_hal_dac.c
  • HAL_DAC_MspDeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_RegisterCallback() : stm32h7xx_hal_dac.c , stm32h7xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32h7xx_hal_dac.c , stm32h7xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStart_DMA() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualStop_DMA() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DCMI_ConfigCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DisableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_EnableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_ErrorCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_FrameEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_IRQHandler() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_LineEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MspDeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MspInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_RegisterCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Resume() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Stop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Suspend() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_UnRegisterCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_VsyncEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DeInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_Delay() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DFDSMEx_ChannelGetPulsesSkipping() : stm32h7xx_hal_dfsdm_ex.c
  • HAL_DFDSMEx_ChannelSetPulsesSkipping() : stm32h7xx_hal_dfsdm_ex.c
  • HAL_DFSDM_Channel_RegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Channel_UnRegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_RegisterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_RegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_UnRegisterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_Filter_UnRegisterCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32h7xx_hal_dfsdm.c
  • HAL_DisableCompensationCell() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDBGSleepMode() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_DisableDBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDomain3DBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DisableDomain3DBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_DMA2D_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoadingCpltCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigLayer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DisableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetError() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetState() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Init() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_IRQHandler() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_LineEventCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspDeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_PollForTransfer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ProgramLineEvent() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_RegisterCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_UnRegisterCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA_Abort() : stm32h7xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetError() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32h7xx_hal_dma.c
  • HAL_DMA_Init() : stm32h7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32h7xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32h7xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMAEx_ChangeMemory() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32h7xx_hal_dma_ex.c
  • HAL_DTS_AsyncEndCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_AsyncHighCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_AsyncLowCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_DeInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_EndCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_GetState() : stm32h7xx_hal_dts.c
  • HAL_DTS_GetTemperature() : stm32h7xx_hal_dts.c
  • HAL_DTS_HighCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_Init() : stm32h7xx_hal_dts.c
  • HAL_DTS_IRQHandler() : stm32h7xx_hal_dts.c
  • HAL_DTS_LowCallback() : stm32h7xx_hal_dts.c
  • HAL_DTS_MspDeInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_MspInit() : stm32h7xx_hal_dts.c
  • HAL_DTS_Start() : stm32h7xx_hal_dts.c
  • HAL_DTS_Start_IT() : stm32h7xx_hal_dts.c
  • HAL_DTS_Stop() : stm32h7xx_hal_dts.c
  • HAL_DTS_Stop_IT() : stm32h7xx_hal_dts.c
  • HAL_EnableCompensationCell() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGSleepMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDomain3DBGStandbyMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EnableDomain3DBGStopMode() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_ClearConfigLine() : stm32h7xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32h7xx_hal_exti.c
  • HAL_EXTI_D1_ClearFlag() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_D1_EventInputConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_D3_EventInputConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_EdgeConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_GenerateSWI() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GenerateSWInterrupt() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_EXTI_GetConfigLine() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32h7xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32h7xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32h7xx_hal_exti.c
  • HAL_EXTI_RegisterCallback() : stm32h7xx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32h7xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigClockCalibration() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFifoWatermark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxBufferRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ErrorCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRxBufferMessageAvailable() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MspDeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MspInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterCallback() : stm32h7xx_hal_fdcan.c , stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_RegisterClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTGlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTStopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTTTimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxBufferNewMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Stop() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigExternalSyncPhase() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigOperation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigReferenceMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigRegisterTimeMark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigStopWatch() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigTrigger() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GetOperationStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetClockSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetEndOfGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetGlobalTime() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetNextIsGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_StopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_TimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTGlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTStopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTTTimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32h7xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32h7xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32h7xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Program() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32h7xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32h7xx_hal_flash.c
  • HAL_FLASHEx_ComputeCRC() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Lock_Bank1() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Lock_Bank2() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Unlock_Bank1() : stm32h7xx_hal_flash_ex.c
  • HAL_FLASHEx_Unlock_Bank2() : stm32h7xx_hal_flash_ex.c
  • HAL_GetCurrentCPUID() : stm32h7xx_hal_cortex.c
  • HAL_GetDEVID() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetFMCMemorySwappingConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetHalVersion() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetREVID() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTickFreq() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetTickPrio() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw0() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw1() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GetUIDw2() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_GFXMMU_ConfigForceCache() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ConfigLut() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ConfigLutLine() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_DeInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_DisableLutLines() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ErrorCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_GetError() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_GetState() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_Init() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_IRQHandler() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ModifyBuffers() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_ModifyCachePrefetch() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_MspDeInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_MspInit() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_RegisterCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GFXMMU_UnRegisterCallback() : stm32h7xx_hal_gfxmmu.c
  • HAL_GPIO_DeInit() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32h7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32h7xx_hal_uart.c
  • HAL_HASH_ContextRestoring() : stm32h7xx_hal_hash.c
  • HAL_HASH_ContextSaving() : stm32h7xx_hal_hash.c
  • HAL_HASH_DeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_DgstCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_DMAFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_ErrorCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetError() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetState() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetStatus() : stm32h7xx_hal_hash.c
  • HAL_HASH_InCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_Init() : stm32h7xx_hal_hash.c
  • HAL_HASH_IRQHandler() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_MspDeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_MspInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_RegisterCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_SwFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_UnRegisterCallback() : stm32h7xx_hal_hash.c
  • HAL_HASHEx_SHA224_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HCD_Connect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MspDeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_PortDisabled_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_PortEnabled_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_RegisterCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_RegisterHC_NotifyURBChangeCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_ResetPort() : stm32h7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Start() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Stop() : stm32h7xx_hal_hcd.c
  • HAL_HCD_UnRegisterCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HCD_UnRegisterHC_NotifyURBChangeCallback() : stm32h7xx_hal_hcd.c , stm32h7xx_hal_hcd.h
  • HAL_HMAC_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMACEx_MD5_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HSEM_ActivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Release() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Take() : stm32h7xx_hal_hsem.c
  • HAL_I2C_AbortCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32h7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_RegisterAddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_UnRegisterAddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32h7xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32h7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32h7xx_hal_i2s.c
  • HAL_IncTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_Init() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_InitTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_IRDA_Abort() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32h7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32h7xx_hal_irda.c
  • HAL_IWDG_Init() : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32h7xx_hal_iwdg.c
  • HAL_JPEG_Abort() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigEncoding() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigInputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigOutputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DecodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DisableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EnableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EncodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ErrorCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetError() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetInfo() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetState() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_InfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Init() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_IRQHandler() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MspDeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MspInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Pause() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterDataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterGetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_RegisterInfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Resume() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_SetUserQuantTables() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterDataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterGetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_UnRegisterInfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_LIN_Init() : stm32h7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32h7xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_CompareMatchCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DirectionDownCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_MspDeInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_MspInit() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_TriggerCallback() : stm32h7xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32h7xx_hal_lptim.c
  • HAL_LTDC_ConfigCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ErrorCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_GetError() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_GetState() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Init() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_IRQHandler() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_LineEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MspDeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_MspInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ProgramLineEvent() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_RegisterCallback() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Reload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ReloadEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_SetAddress() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAddress_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_UnRegisterCallback() : stm32h7xx_hal_ltdc.c
  • HAL_MDIOS_ClearReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ClearWriteRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_DeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_EnableEvents() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ErrorCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetError() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetState() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetWrittenRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_Init() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_IRQHandler() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MspDeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MspInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadReg() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_RegisterCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_UnRegisterCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WakeUpCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteReg() : stm32h7xx_hal_mdios.c
  • HAL_MDMA_Abort() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Abort_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ConfigPostRequestMask() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_DeInit() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GenerateSWRequest() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetError() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetState() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Init() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_IRQHandler() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_AddNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_CreateNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_DisableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_EnableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_RemoveNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_PollForTransfer() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_RegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_UnRegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MMC_Abort() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Abort_IT() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_AbortCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ConfigSpeedBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ConfigWideBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_DeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_Erase() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ErrorCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_GetCardCID() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardCSD() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardInfo() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetError() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Init() : stm32h7xx_hal_mmc.c
  • HAL_MMC_InitCard() : stm32h7xx_hal_mmc.c
  • HAL_MMC_IRQHandler() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspDeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RegisterCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_TxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_UnRegisterCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMCEx_ChangeDMABuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MPU_ConfigRegion() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32h7xx_hal_cortex.c
  • HAL_MspDeInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_MspInit() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_MultiProcessor_DisableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32h7xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32h7xx_hal_nand.c
  • HAL_NAND_ConfigDevice() : stm32h7xx_hal_nand.c , stm32h7xx_hal_nand.h
  • HAL_NAND_DeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32h7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32h7xx_hal_nand.c
  • HAL_NAND_Init() : stm32h7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32h7xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspDeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32h7xx_hal_nand.c , stm32h7xx_hal_nand.h
  • HAL_NAND_Read_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32h7xx_hal_nand.c
  • HAL_NAND_RegisterCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_Reset() : stm32h7xx_hal_nand.c
  • HAL_NAND_UnRegisterCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32h7xx_hal_nor.c
  • HAL_NOR_Init() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspDeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32h7xx_hal_nor.c
  • HAL_NOR_Program() : stm32h7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_RegisterCallback() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32h7xx_hal_nor.c
  • HAL_NOR_UnRegisterCallback() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Disable() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32h7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32h7xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MspDeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_RegisterCallback() : stm32h7xx_hal_opamp.h , stm32h7xx_hal_opamp.c
  • HAL_OPAMP_SelfCalibrate() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Stop() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_UnRegisterCallback() : stm32h7xx_hal_opamp.c , stm32h7xx_hal_opamp.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32h7xx_hal_opamp_ex.c , stm32h7xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32h7xx_hal_opamp_ex.c
  • HAL_OSPI_Abort() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Abort_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_AbortCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_AutoPolling() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_AutoPolling_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_CmdCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Command() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Command_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_DeInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_ErrorCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_FifoThresholdCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_GetError() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_GetFifoThreshold() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_GetState() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_HyperbusCfg() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_HyperbusCmd() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Init() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_IRQHandler() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_MemoryMapped() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_MspDeInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_MspInit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Receive() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Receive_DMA() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Receive_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_RegisterCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_RxCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_RxHalfCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_SetFifoThreshold() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_SetTimeout() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_StatusMatchCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TimeOutCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit_DMA() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_Transmit_IT() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TxCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_TxHalfCpltCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPI_UnRegisterCallback() : stm32h7xx_hal_ospi.c
  • HAL_OSPIM_Config() : stm32h7xx_hal_ospi.c
  • HAL_OTFDEC_DeInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_ErrorCallback() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_GetState() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_Init() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_IRQHandler() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_KeyCRCComputation() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_MspDeInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_MspInit() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionConfig() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionDisable() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionEnable() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionGetConfig() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionGetKeyCRC() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionKeyLock() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionSetKey() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegionSetMode() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_RegisterCallback() : stm32h7xx_hal_otfdec.c
  • HAL_OTFDEC_UnRegisterCallback() : stm32h7xx_hal_otfdec.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32h7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterBcdCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PSSI_Abort_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_AbortCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_DeInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_ErrorCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_GetError() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_GetState() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Init() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_IRQHandler() : stm32h7xx_hal_pssi.h , stm32h7xx_hal_pssi.c
  • HAL_PSSI_MspDeInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_MspInit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Receive() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Receive_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_RegisterCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_RxCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Transmit() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_Transmit_DMA() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_TxCpltCallback() : stm32h7xx_hal_pssi.c
  • HAL_PSSI_UnRegisterCallback() : stm32h7xx_hal_pssi.c
  • HAL_PWR_ConfigPVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32h7xx_hal_pwr.c , stm32h7xx_hal_pwr.h
  • HAL_PWR_PVDCallback() : stm32h7xx_hal_pwr.c , stm32h7xx_hal_pwr.h
  • HAL_PWREx_AVDCallback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearPendingEvent() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigD3Domain() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSupply() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlStopModeVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAnalogBooster() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMemoryShutOff() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAnalogBooster() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMemoryShutOff() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTANDBYMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOPMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetMMCVoltage() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetStopModeVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetSupplyConfig() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetTemperatureLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVBATLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_AVD_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WAKEUP_PIN_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP1_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP2_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP3_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP4_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP5_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP6_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_RAMECC_DeInit() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_DisableNotification() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_EnableNotification() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetError() : stm32h7xx_hal_ramecc.h , stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetFailingAddress() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetFailingDataHigh() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetFailingDataLow() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetHammingErrorCode() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_GetState() : stm32h7xx_hal_ramecc.c , stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_Init() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IRQHandler() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IsECCDoubleErrorDetected() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_IsECCSingleErrorDetected() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_RegisterCallback() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_StartMonitor() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_StopMonitor() : stm32h7xx_hal_ramecc.c
  • HAL_RAMECC_UnRegisterCallback() : stm32h7xx_hal_ramecc.c
  • HAL_RCC_CCSCallback() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_ClockConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_EnableCSS() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetClockConfig() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetOscConfig() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK2Freq() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MCOConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_NMI_IRQHandler() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_OscConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1SysClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD3PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL1ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL2ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL3ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_KerWakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_RNG_DeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetError() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32h7xx_hal_rng.c
  • HAL_RNG_Init() : stm32h7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32h7xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_UnRegisterCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNGEx_GetConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RNGEx_LockConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RNGEx_SetConfig() : stm32h7xx_hal_rng_ex.c
  • HAL_RS485Ex_Init() : stm32h7xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_Init() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32h7xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_UnRegisterCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32h7xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateActiveTampers() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper8EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_MonotonicCounterGet() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_MonotonicCounterIncrement() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetActiveSeed() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetActiveTampers() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_SAI_Abort() : stm32h7xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32h7xx_hal_sai.c
  • HAL_SAI_Init() : stm32h7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32h7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32h7xx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32h7xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32h7xx_hal_sai_ex.c
  • HAL_SD_Abort() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Abort_IT() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_AbortCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_ConfigSpeedBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_ConfigWideBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_DriveTransceiver_1_8V_Callback() : stm32h7xx_hal_sd.c
  • HAL_SD_Erase() : stm32h7xx_hal_sd.c
  • HAL_SD_ErrorCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCID() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardCSD() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardInfo() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardState() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetError() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetState() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Init() : stm32h7xx_hal_sd.c
  • HAL_SD_InitCard() : stm32h7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32h7xx_hal_sd.c
  • HAL_SD_MspDeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SD_RegisterCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_RegisterTransceiverCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_RxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_TxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_UnRegisterCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_UnRegisterTransceiverCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SDEx_ChangeDMABuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDRAM_DeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspDeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RefreshErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RegisterCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RegisterDmaCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_UnRegisterCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32h7xx_hal_sdram.c
  • HAL_SetFMCMemorySwappingConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SetTickFreq() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SMARTCARD_Abort() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_RegisterAddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32h7xx_hal_smbus.c
  • HAL_SPDIFRX_CxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ErrorCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspDeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveCtrlFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveCtrlFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveCtrlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RegisterCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_UnRegisterCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPI_Abort() : stm32h7xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32h7xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32h7xx_hal_spi.c
  • HAL_SPI_Init() : stm32h7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32h7xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32h7xx_hal_spi.c
  • HAL_SPIEx_ConfigureUnderrun() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_EnableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_FlushRxFifo() : stm32h7xx_hal_spi_ex.c
  • HAL_SRAM_DeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sram.c , stm32h7xx_hal_sram.h
  • HAL_SRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sram.c , stm32h7xx_hal_sram.h
  • HAL_SRAM_GetState() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspDeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_RegisterCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_RegisterDmaCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_UnRegisterCallback() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32h7xx_hal_sram.c
  • HAL_SuspendTick() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SWPMI_DeInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_DisableLoopback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_DMAStop() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_EnableLoopback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_ErrorCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_GetError() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_GetState() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Init() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_IRQHandler() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MspDeInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_MspInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive_DMA() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RegisterCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_RxCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RxHalfCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_DMA() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TxCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TxHalfCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_UnRegisterCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SYSCFG_AnalogSwitchConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_CompensationCodeConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_CompensationCodeSelect() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_DisableIOSpeedOptimize() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_EnableIOSpeedOptimize() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_EnableVREFBUF() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_VDDMMC_CompensationCodeConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32h7xx_hal.h , stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32h7xx_hal.c , stm32h7xx_hal.h
  • HAL_SYSTICK_Callback() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32h7xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32h7xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32h7xx_hal_tim.c
  • HAL_TIMEx_Break2Callback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32h7xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32h7xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_DeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32h7xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32h7xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_GetError() : stm32h7xx_hal_uart.c
  • HAL_UART_GetState() : stm32h7xx_hal_uart.c
  • HAL_UART_Init() : stm32h7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32h7xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_MspInit() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32h7xx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32h7xx_hal_uart.c
  • HAL_UARTEx_DisableFifoMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32h7xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_DeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32h7xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_GetError() : stm32h7xx_hal_usart.c
  • HAL_USART_GetState() : stm32h7xx_hal_usart.c
  • HAL_USART_Init() : stm32h7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32h7xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_MspInit() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32h7xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32h7xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32h7xx_hal_usart_ex.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32h7xx_hal_wwdg.c
  • HASH_Accumulate() : stm32h7xx_hal_hash.c
  • HASH_DMAError() : stm32h7xx_hal_hash.c
  • HASH_DMAXferCplt() : stm32h7xx_hal_hash.c
  • HASH_Finish() : stm32h7xx_hal_hash.c
  • HASH_GetDigest() : stm32h7xx_hal_hash.c
  • HASH_IT() : stm32h7xx_hal_hash.c
  • HASH_Start() : stm32h7xx_hal_hash.c
  • HASH_Start_DMA() : stm32h7xx_hal_hash.c
  • HASH_Start_IT() : stm32h7xx_hal_hash.c
  • HASH_WaitOnFlagUntilTimeout() : stm32h7xx_hal_hash.c
  • HASH_Write_Block_Data() : stm32h7xx_hal_hash.c
  • HASH_WriteData() : stm32h7xx_hal_hash.c
  • HCD_HC_IN_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_Port_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32h7xx_hal_hcd.c
  • HMAC_Processing() : stm32h7xx_hal_hash.c
  • HMAC_Start() : stm32h7xx_hal_hash.c
  • HMAC_Start_DMA() : stm32h7xx_hal_hash.c
  • HMAC_Start_IT() : stm32h7xx_hal_hash.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- i -

  • I2C_ConvertOtherXferOptions() : stm32h7xx_hal_i2c.c
  • I2C_Disable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_DMAAbort() : stm32h7xx_hal_i2c.c
  • I2C_DMAError() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32h7xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32h7xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITError() : stm32h7xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2S_DMAError() : stm32h7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_Receive_16Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_Receive_32Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_Transmit_16Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_Transmit_32Bit_IT() : stm32h7xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s.c
  • IC1Config() : stm32h7xx_ll_tim.c
  • IC2Config() : stm32h7xx_ll_tim.c
  • IC3Config() : stm32h7xx_ll_tim.c
  • IC4Config() : stm32h7xx_ll_tim.c
  • IRDA_CheckIdleState() : stm32h7xx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32h7xx_hal_irda.c
  • IRDA_DMAError() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_InitCallbacksToDefault() : stm32h7xx_hal_irda.c
  • IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • IRDA_SetConfig() : stm32h7xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32h7xx_hal_irda.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- j -

  • JPEG_ACHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_Bits_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DCHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_ContinueProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_EndProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_PollResidualData() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_StartProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_GetQuality() : stm32h7xx_hal_jpeg.c
  • JPEG_Init_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAErrorCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAInCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutAbortCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_ReadInputData() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Huff_DHTMem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffAC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffDC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffEnc_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Quantization_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorCMYK() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorGrayScale() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorYCBCR() : stm32h7xx_hal_jpeg.c
  • JPEG_StoreOutputData() : stm32h7xx_hal_jpeg.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- l -

  • LL_ADC_ClearFlag_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32h7xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32h7xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32h7xx_ll_adc.h
  • LL_ADC_DeInit() : stm32h7xx_ll_adc.c
  • LL_ADC_Disable() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32h7xx_ll_adc.h
  • LL_ADC_Enable() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32h7xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32h7xx_ll_adc.h
  • LL_ADC_GetBoostMode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCalibrationLinearFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCalibrationOffsetFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32h7xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32h7xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32h7xx_ll_adc.h
  • LL_ADC_GetDataRightShift() : stm32h7xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32h7xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOffsetSignedSaturation() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32h7xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32h7xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32h7xx_ll_adc.h
  • LL_ADC_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData14() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData16() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32h7xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32h7xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32h7xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetDataTransferMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32h7xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData14() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData16() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetDataTransferMode() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32h7xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32h7xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32h7xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32h7xx_ll_adc.h
  • LL_ADC_SetBoostMode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCalibrationLinearFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCalibrationOffsetFactor() : stm32h7xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32h7xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32h7xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32h7xx_ll_adc.h
  • LL_ADC_SetDataRightShift() : stm32h7xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32h7xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOffsetSignedSaturation() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32h7xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32h7xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32h7xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32h7xx_ll_adc.h
  • LL_ADC_StructInit() : stm32h7xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_DisableClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_DisableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_EnableClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_EnableClockSleep() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_ForceReset() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_IsEnabledClock() : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_ReleaseReset() : stm32h7xx_ll_bus.h
  • LL_BDMA_ClearFlag_GI0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_GI7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_HT7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TC7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ClearFlag_TE7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ConfigAddresses() : stm32h7xx_ll_bdma.h
  • LL_BDMA_ConfigTransfer() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DeInit() : stm32h7xx_ll_bdma.c
  • LL_BDMA_DisableChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableDoubleBufferMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_DisableIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableDoubleBufferMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_EnableIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetChannelPriorityLevel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetCurrentTargetMem() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetDataLength() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetDataTransferDirection() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetM2MDstAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetM2MSrcAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemory1Address() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemoryAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemoryIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMemorySize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphRequest() : stm32h7xx_ll_bdma.h
  • LL_BDMA_GetPeriphSize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_Init() : stm32h7xx_ll_bdma.c
  • LL_BDMA_IsActiveFlag_GI0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_GI7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_HT7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TC7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE0() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE1() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE2() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE3() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE4() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE5() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE6() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsActiveFlag_TE7() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledChannel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_HT() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_TC() : stm32h7xx_ll_bdma.h
  • LL_BDMA_IsEnabledIT_TE() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetChannelPriorityLevel() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetCurrentTargetMem() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetDataLength() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetDataTransferDirection() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetM2MDstAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetM2MSrcAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemory1Address() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemoryAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemoryIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMemorySize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphAddress() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphIncMode() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphRequest() : stm32h7xx_ll_bdma.h
  • LL_BDMA_SetPeriphSize() : stm32h7xx_ll_bdma.h
  • LL_BDMA_StructInit() : stm32h7xx_ll_bdma.c
  • LL_CKGA_Disable() : stm32h7xx_ll_bus.h
  • LL_CKGA_Enable() : stm32h7xx_ll_bus.h
  • LL_CLKAM_Disable() : stm32h7xx_ll_bus.h
  • LL_CLKAM_Enable() : stm32h7xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32h7xx_ll_comp.h
  • LL_COMP_DeInit() : stm32h7xx_ll_comp.c
  • LL_COMP_Disable() : stm32h7xx_ll_comp.h
  • LL_COMP_Enable() : stm32h7xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32h7xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputAlternateFunction() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32h7xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32h7xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32h7xx_ll_comp.h
  • LL_COMP_Init() : stm32h7xx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32h7xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32h7xx_ll_comp.h
  • LL_COMP_Lock() : stm32h7xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32h7xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32h7xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputAlternateFunction() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32h7xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32h7xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32h7xx_ll_comp.h
  • LL_COMP_StructInit() : stm32h7xx_ll_comp.c
  • LL_CPUID_GetConstant() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32h7xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32h7xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32h7xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32h7xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32h7xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32h7xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32h7xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32h7xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32h7xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32h7xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32h7xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32h7xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32h7xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32h7xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32h7xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32h7xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32h7xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32h7xx_ll_crs.h
  • LL_CRS_DeInit() : stm32h7xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32h7xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32h7xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32h7xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32h7xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32h7xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32h7xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32h7xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32h7xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32h7xx_ll_crs.h
  • LL_D3_EXTI_DisablePendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_DisablePendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_EnablePendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_EnablePendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_0_15() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_16_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_32_47() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_GetPendClearSel_48_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_IsEnabledPendMask_0_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_IsEnabledPendMask_32_63() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_0_15() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_16_31() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_32_47() : stm32h7xx_ll_exti.h
  • LL_D3_EXTI_SetPendClearSel_48_63() : stm32h7xx_ll_exti.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32h7xx_ll_dac.h
  • LL_DAC_DeInit() : stm32h7xx_ll_dac.c
  • LL_DAC_Disable() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32h7xx_ll_dac.h
  • LL_DAC_Enable() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32h7xx_ll_dac.h
  • LL_DAC_GetMode() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32h7xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32h7xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32h7xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32h7xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32h7xx_ll_dac.h
  • LL_DAC_Init() : stm32h7xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32h7xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32h7xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32h7xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32h7xx_ll_dac.h
  • LL_DAC_SetMode() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32h7xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32h7xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32h7xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32h7xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32h7xx_ll_dac.h
  • LL_DAC_StructInit() : stm32h7xx_ll_dac.c
  • LL_DAC_TrigSWConversion() : stm32h7xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_FreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_UnFreezePeriph() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInSleepMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD1DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableD3DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_DisableTracePortClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInSleepMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD1DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugInStandbyMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableD3DebugInStopMode() : stm32h7xx_ll_system.h
  • LL_DBGMCU_EnableTracePortClock() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetExternalTriggerPinDirection() : stm32h7xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32h7xx_ll_system.h
  • LL_DBGMCU_SetExternalTriggerPinDirection() : stm32h7xx_ll_system.h
  • LL_DMA2D_Abort() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_EnableCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_GetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_IsEnabledCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_BGND_SetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ClearFlag_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ConfigLayer() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_ConfigOutputColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_ConfigSize() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_DeInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_DisableDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_DisableIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_EnableIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_EnableCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetChrSubSampling() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_GetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_IsEnabledCLUTLoad() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlpha() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetAlphaMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetBlueColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetChrSubSampling() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetCLUTSize() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetGreenColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FGND_SetRedColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineOffsetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetLineWatermark() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetNbrOfLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetNbrOfPixelsPerLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputAlphaColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputBlueColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputGreenColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_GetOutputRedColor() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_GetOutputSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_Init() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_IsAborted() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsActiveFlag_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CAE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_CTC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TC() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TE() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsEnabledIT_TW() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsSuspended() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IsTransferOngoing() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_LayerCfgStructInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_Resume() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetDeadTime() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineOffset() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineOffsetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetLineWatermark() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetNbrOfLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetNbrOfPixelsPerLines() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputAlphaInvMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputColor() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputColorMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputMemAddr() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputRBSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SetOutputSwapMode() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_Start() : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_StructInit() : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_Suspend() : stm32h7xx_ll_dma2d.h
  • LL_DMA_ClearFlag_DME0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_DME7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_FE7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE0() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32h7xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigFifo() : stm32h7xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32h7xx_ll_dma.h
  • LL_DMA_DeInit() : stm32h7xx_ll_dma.c
  • LL_DMA_DisableDoubleBufferMode() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableFifoMode() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_DisableStream() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableDoubleBufferMode() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableFifoMode() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_EnableStream() : stm32h7xx_ll_dma.h
  • LL_DMA_GetCurrentTargetMem() : stm32h7xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32h7xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32h7xx_ll_dma.h
  • LL_DMA_GetFIFOStatus() : stm32h7xx_ll_dma.h
  • LL_DMA_GetFIFOThreshold() : stm32h7xx_ll_dma.h
  • LL_DMA_GetIncOffsetSize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemory1Address() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32h7xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32h7xx_ll_dma.h
  • LL_DMA_GetStreamPriorityLevel() : stm32h7xx_ll_dma.h
  • LL_DMA_Init() : stm32h7xx_ll_dma.c
  • LL_DMA_IsActiveFlag_DME0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_DME7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_FE7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE0() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32h7xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_DME() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_FE() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32h7xx_ll_dma.h
  • LL_DMA_IsEnabledStream() : stm32h7xx_ll_dma.h
  • LL_DMA_SetCurrentTargetMem() : stm32h7xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32h7xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32h7xx_ll_dma.h
  • LL_DMA_SetFIFOThreshold() : stm32h7xx_ll_dma.h
  • LL_DMA_SetIncOffsetSize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemory1Address() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphBurstxfer() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32h7xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32h7xx_ll_dma.h
  • LL_DMA_SetStreamPriorityLevel() : stm32h7xx_ll_dma.h
  • LL_DMA_StructInit() : stm32h7xx_ll_dma.c
  • LL_DMAMUX_ClearFlag_RGO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO12() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO13() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO14() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO15() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO12() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO13() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO14() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO15() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32h7xx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_ClearFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32h7xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_GenerateSWI_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_Init() : stm32h7xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadFlag_64_95() : stm32h7xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32h7xx_ll_exti.c
  • LL_FLASH_GetLatency() : stm32h7xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32h7xx_ll_system.h
  • LL_GetFlashSize() : stm32h7xx_ll_utils.h
  • LL_GetPackageType() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word0() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word1() : stm32h7xx_ll_utils.h
  • LL_GetUID_Word2() : stm32h7xx_ll_utils.h
  • LL_GPIO_DeInit() : stm32h7xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32h7xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32h7xx_ll_gpio.h
  • LL_GPIO_Init() : stm32h7xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32h7xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32h7xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32h7xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32h7xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32h7xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32h7xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32h7xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32h7xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32h7xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32h7xx_ll_cortex.h
  • LL_HSEM_1StepLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_2StepLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ClearFlag_C1ICR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_DisableIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_EnableIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetCoreId() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetKey() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetProcessId() : stm32h7xx_ll_hsem.h
  • LL_HSEM_GetStatus() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1ISR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1MISR() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C1IER() : stm32h7xx_ll_hsem.h
  • LL_HSEM_IsSemaphoreLocked() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ReleaseLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_ResetAllLock() : stm32h7xx_ll_hsem.h
  • LL_HSEM_SetKey() : stm32h7xx_ll_hsem.h
  • LL_HSEM_SetLock() : stm32h7xx_ll_hsem.h
  • LL_I2C_AcknowledgeNextData() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32h7xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32h7xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32h7xx_ll_i2c.c
  • LL_I2C_Disable() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_Enable() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32h7xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32h7xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32h7xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32h7xx_ll_i2c.h
  • LL_I2C_Init() : stm32h7xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32h7xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32h7xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32h7xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32h7xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32h7xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32h7xx_ll_i2c.h
  • LL_I2S_ClearFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_DeInit() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_Disable() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_DisableWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_Enable() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIOLock() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_EnableWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_GetChannelLengthType() : stm32h7xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32h7xx_ll_spi.h
  • LL_I2S_GetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32h7xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32h7xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32h7xx_ll_spi.h
  • LL_I2S_GetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32h7xx_ll_spi.h
  • LL_I2S_Init() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsActiveTransfer() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledGPIOControl() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIOLock() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIOSwap() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_FRE() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_OVR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXP() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledIT_UDR() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32h7xx_ll_spi.h
  • LL_I2S_IsEnabledWordSelectInversion() : stm32h7xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32h7xx_ll_spi.h
  • LL_I2S_ReceiveData32() : stm32h7xx_ll_spi.h
  • LL_I2S_SetChannelLengthType() : stm32h7xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32h7xx_ll_spi.h
  • LL_I2S_SetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32h7xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32h7xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32h7xx_ll_spi.h
  • LL_I2S_SetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32h7xx_ll_spi.h
  • LL_I2S_StartTransfer() : stm32h7xx_ll_spi.h
  • LL_I2S_StructInit() : stm32h7xx_ll_spi.c , stm32h7xx_ll_spi.h
  • LL_I2S_TransmitData16() : stm32h7xx_ll_spi.h
  • LL_I2S_TransmitData32() : stm32h7xx_ll_spi.h
  • LL_Init1msTick() : stm32h7xx_ll_utils.c
  • LL_InitTick() : stm32h7xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32h7xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32h7xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32h7xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32h7xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32h7xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32h7xx_ll_lptim.c
  • LL_LPTIM_TrigSw() : stm32h7xx_ll_lptim.h
  • LL_LPUART_ClearFlag_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_Disable() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32h7xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32h7xx_ll_lpuart.h
  • LL_mDelay() : stm32h7xx_ll_utils.c
  • LL_MDMA_ClearFlag_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ClearFlag_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigAddresses() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkCounters() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkRepeatAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBlkRptAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigTransfer() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConfigXferEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_ConnectLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_CreateLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_DeInit() : stm32h7xx_ll_mdma.c
  • LL_MDMA_DisableBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisableIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisablePacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_DisconnectNextLinkNode() : stm32h7xx_ll_mdma.c
  • LL_MDMA_EnableBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnableIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_EnablePacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GenerateSWRequest() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkDataLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatCount() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatDestAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRepeatSrcAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRptDestAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBlkRptSrcAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetBufferTransferLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetByteEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetChannelPriorityLevel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetDestinationIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetHalfWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetHWTrigger() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetLinkAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetMaskAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetMaskData() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetPaddingAlignment() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetRequestMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSourceIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetSrcBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetTriggerMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetXferErrorDirection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_GetXferErrorLSBAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_Init() : stm32h7xx_ll_mdma.c
  • LL_MDMA_IsActiveFlag_ASE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BSE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_CRQA() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_GI() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TELD() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsActiveFlag_TEMD() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledBufferableWrMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledChannel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_BRT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_BT() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_CTC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_TC() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledIT_TE() : stm32h7xx_ll_mdma.h
  • LL_MDMA_IsEnabledPacking() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkDataLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatCount() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatDestAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRepeatSrcAddrUpdate() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRptDestAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBlkRptSrcAddrUpdateValue() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetBufferTransferLength() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetByteEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetChannelPriorityLevel() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetDestinationIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetHalfWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetHWTrigger() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetLinkAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetMaskAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetMaskData() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetPaddingAlignment() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetRequestMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceAddress() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceBurstSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceDataSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceIncMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSourceIncSize() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetSrcBusSelection() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetTriggerMode() : stm32h7xx_ll_mdma.h
  • LL_MDMA_SetWordEndianness() : stm32h7xx_ll_mdma.h
  • LL_MDMA_StructInit() : stm32h7xx_ll_mdma.c
  • LL_MPU_ConfigRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_Disable() : stm32h7xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_Enable() : stm32h7xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32h7xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32h7xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32h7xx_ll_opamp.c
  • LL_OPAMP_Disable() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32h7xx_ll_opamp.c
  • LL_OPAMP_IsCalibrationOutputSet() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32h7xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32h7xx_ll_opamp.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32h7xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32h7xx_ll_utils.c
  • LL_PWR_ClearFlag_CPU() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32h7xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU6() : stm32h7xx_ll_pwr.h
  • LL_PWR_ConfigSupply() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_DisableSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_EnableSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_GetCDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_GetD3PowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsActiveFlag_SB() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsActiveFlag_STOP() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_SetCDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_SetSRDPowerMode() : stm32h7xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32h7xx_ll_pwr.c
  • LL_PWR_DisableAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableITCMSOShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableITCMSOShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetAVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetStopModeRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetSupply() : stm32h7xx_ll_pwr.h
  • LL_PWR_GetWakeUpPinPull() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_ACTVOS() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_AVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BRR() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_MMCVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SMPSEXT() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_TEMPH() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_TEMPL() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_USB() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VBATH() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VBATL() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU6() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAHBRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAHBRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAnalogBooster() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAnalogVoltageReady() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM1ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM2ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledAXIRAM3ShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpRegulator() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledFlashPowerDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledHSITFShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledITCMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledMonitoring() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledSRDRAMShutOff() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBReg() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBVoltageDetector() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32h7xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetAVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetStopModeRegulVoltageScaling() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullDown() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullNone() : stm32h7xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPullUp() : stm32h7xx_ll_pwr.h
  • LL_RCC_CalcPLLClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_CDCK_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32h7xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32h7xx_ll_rcc.h
  • LL_RCC_CPUCK_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_DisableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_EnableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_GetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_CSI_SetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32h7xx_ll_rcc.c
  • LL_RCC_DisableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB3Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetAPB4Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetCLKPClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetCLKPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetDFSDM2ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetDFSDM2ClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetDFSDMClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetDFSDMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetFMCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetFMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetKerWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetOSPIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetOSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetPLL1ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetPLL2ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetPLL3ClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetRNGClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetRTC_HSEPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSDMMCClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSDMMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSPDIFClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSPDIFClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSPIClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSWPClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSWPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSysPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetSysWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetTIMPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32h7xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_SelectAnalogClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSE_SelectDigitalClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DisableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_EnableStopMode() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_GetDivider() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_IsDividerReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_SetDivider() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_CDRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDG1RST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDG1RST() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_CSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSI48RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_HSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSECSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSERDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_LSIRDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL1RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL2RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_IsEnableIT_PLL3RDY() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_IsFailureDetected() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SelectAnalogClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SelectDigitalClock() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL1R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL2R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_GetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_IsReady() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetFRACN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetM() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetN() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetP() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetQ() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetR() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetVCOInputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3_SetVCOOutputRange() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3FRACN_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3P_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3Q_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_Disable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_Enable() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL3R_IsEnabled() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL_GetSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_PLL_SetSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB3Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetAPB4Prescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetCLKPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetDFSDM2ClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetDFSDMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetFMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetKerWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetOSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRTC_HSEPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSDMMCClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSPDIFClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSPIClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSWPClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetSysWakeUpClkSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetTIMPrescaler() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32h7xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32h7xx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_ConfigLock() : stm32h7xx_ll_rng.h
  • LL_RNG_DeInit() : stm32h7xx_ll_rng.c
  • LL_RNG_Disable() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32h7xx_ll_rng.h
  • LL_RNG_DisableNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_Enable() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32h7xx_ll_rng.h
  • LL_RNG_EnableNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_GetClockDivider() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig1() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig2() : stm32h7xx_ll_rng.h
  • LL_RNG_GetConfig3() : stm32h7xx_ll_rng.h
  • LL_RNG_GetHealthConfig() : stm32h7xx_ll_rng.h
  • LL_RNG_Init() : stm32h7xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32h7xx_ll_rng.h
  • LL_RNG_IsConfigLocked() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledCondReset() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32h7xx_ll_rng.h
  • LL_RNG_IsEnabledNistCompliance() : stm32h7xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32h7xx_ll_rng.h
  • LL_RNG_SetClockDivider() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig1() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig2() : stm32h7xx_ll_rng.h
  • LL_RNG_SetConfig3() : stm32h7xx_ll_rng.h
  • LL_RNG_SetHealthConfig() : stm32h7xx_ll_rng.h
  • LL_RNG_StructInit() : stm32h7xx_ll_rng.c
  • LL_RTC_ALMA_ConfigTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_CAL_GetMinus() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32h7xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32h7xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32h7xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32h7xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32h7xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32h7xx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32h7xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ATAMP_INITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ATAMP_SEEDF() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32h7xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_TAMPER_ATAMP_DisableActiveMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_DisableFilter() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_DisableOutputSharing() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableActiveMode() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableFilter() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_EnableOutputSharing() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32h7xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32h7xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32h7xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32h7xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32h7xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32h7xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_SUSP() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_ClearFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_DeInit() : stm32h7xx_ll_spi.c
  • LL_SPI_Disable() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32h7xx_ll_spi.h
  • LL_SPI_Enable() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIOLock() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32h7xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32h7xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32h7xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32h7xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_GetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_SPI_GetHalfDuplexDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetInterDataIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_GetInternalSSLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_GetMasterSSIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_GetMode() : stm32h7xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32h7xx_ll_spi.h
  • LL_SPI_GetNSSPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_GetReloadSize() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRemainingDataFrames() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_GetRxFIFOPackingLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTransferSize() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_GetTxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRConfiguration() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRDetection() : stm32h7xx_ll_spi.h
  • LL_SPI_GetUDRPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_Init() : stm32h7xx_ll_spi.c
  • LL_SPI_IsActiveFlag_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXWNE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_SUSP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveFlag_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsActiveMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledFullSizeCRC() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledGPIOControl() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIOLock() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIOSwap() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_CRCERR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_DXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_EOT() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_FRE() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_MODF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_OVR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TSER() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXP() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXTF() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledIT_UDR() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledMasterRxAutoSuspend() : stm32h7xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData32() : stm32h7xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32h7xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32h7xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32h7xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32h7xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32h7xx_ll_spi.h
  • LL_SPI_SetFIFOThreshold() : stm32h7xx_ll_spi.h
  • LL_SPI_SetHalfDuplexDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetInterDataIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_SetInternalSSLevel() : stm32h7xx_ll_spi.h
  • LL_SPI_SetMasterSSIdleness() : stm32h7xx_ll_spi.h
  • LL_SPI_SetMode() : stm32h7xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32h7xx_ll_spi.h
  • LL_SPI_SetNSSPolarity() : stm32h7xx_ll_spi.h
  • LL_SPI_SetReloadSize() : stm32h7xx_ll_spi.h
  • LL_SPI_SetRxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTransferSize() : stm32h7xx_ll_spi.h
  • LL_SPI_SetTxCRCInitPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRConfiguration() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRDetection() : stm32h7xx_ll_spi.h
  • LL_SPI_SetUDRPattern() : stm32h7xx_ll_spi.h
  • LL_SPI_StartMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_StructInit() : stm32h7xx_ll_spi.c
  • LL_SPI_SuspendMasterTransfer() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData16() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData32() : stm32h7xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32h7xx_ll_spi.h
  • LL_SWPMI_Activate() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_Deactivate() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DeInit() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_DisableDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableLoopback() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DisableTXBypass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DMA_GetRegAddr() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableLoopback() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_EnableTXBypass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetBitRatePrescaler() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetReceiveFrameLength() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetReceptionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetTransmissionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_GetVoltageClass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_Init() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_IsActivated() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_DEACT() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RDYF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXNE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SUSP() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RDY() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBER() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBF() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXOVR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_SR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TC() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TX() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXBE() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXUNR() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledTransceiver() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ReceiveData32() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_RequestDeactivation() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetBitRatePrescaler() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetReceptionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetTransmissionMode() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SetVoltageClass() : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_StructInit() : stm32h7xx_ll_swpmi.c
  • LL_SWPMI_TransmitData32() : stm32h7xx_ll_swpmi.h
  • LL_SYSCFG_CloseAnalogSwitch() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_DisableIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_EnableIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetNMOSCompensationValue() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetPMOSCompensationValue() : stm32h7xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CMPCR() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledCompensationCell() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization1() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization2() : stm32h7xx_ll_system.h
  • LL_SYSCFG_IsEnabledIOSpeedOptimization3() : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCGetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCGetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_MMCSetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_OpenAnalogSwitch() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetCellCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetPMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32h7xx_ll_system.h
  • LL_SYSCFG_VDMMCGetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSCFG_VDMMCSetNMOSCompensationCode() : stm32h7xx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32h7xx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32h7xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32h7xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32h7xx_ll_tim.h
  • LL_TIM_DeInit() : stm32h7xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32h7xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32h7xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32h7xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32h7xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32h7xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32h7xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32h7xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32h7xx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32h7xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32h7xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32h7xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32h7xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32h7xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32h7xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32h7xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32h7xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32h7xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32h7xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32h7xx_ll_tim.h
  • LL_TIM_StructInit() : stm32h7xx_ll_tim.c
  • LL_USART_ClearFlag_CM() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32h7xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_ClockInit() : stm32h7xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32h7xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32h7xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32h7xx_ll_usart.h
  • LL_USART_DeInit() : stm32h7xx_ll_usart.c
  • LL_USART_Disable() : stm32h7xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32h7xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32h7xx_ll_usart.h
  • LL_USART_Enable() : stm32h7xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32h7xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32h7xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32h7xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32h7xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32h7xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32h7xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32h7xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32h7xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32h7xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32h7xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32h7xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32h7xx_ll_usart.h
  • LL_USART_GetParity() : stm32h7xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32h7xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32h7xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32h7xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32h7xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32h7xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32h7xx_ll_usart.h
  • LL_USART_Init() : stm32h7xx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32h7xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32h7xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32h7xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32h7xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32h7xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32h7xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32h7xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32h7xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32h7xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32h7xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32h7xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32h7xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32h7xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32h7xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32h7xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32h7xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32h7xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32h7xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32h7xx_ll_usart.h
  • LL_USART_SetParity() : stm32h7xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32h7xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32h7xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32h7xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32h7xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32h7xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32h7xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32h7xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32h7xx_ll_usart.h
  • LL_USART_StructInit() : stm32h7xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32h7xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32h7xx_ll_usart.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32h7xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32h7xx_ll_wwdg.h
  • LPTIM_Disable() : stm32h7xx_hal_lptim.c
  • LPTIM_ResetCallback() : stm32h7xx_hal_lptim.c
  • LPTIM_WaitForFlag() : stm32h7xx_hal_lptim.c
  • LTDC_SetConfig() : stm32h7xx_hal_ltdc.c
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STM32H7B3xQ HAL User Manual: Globals

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- m -

  • MDIOS_InitCallbacksToDefault() : stm32h7xx_hal_mdios.c
  • MDMA_Init() : stm32h7xx_hal_mdma.c
  • MDMA_SetConfig() : stm32h7xx_hal_mdma.c
  • MMC_DDR_Mode() : stm32h7xx_hal_mmc.c
  • MMC_HighSpeed() : stm32h7xx_hal_mmc.c
  • MMC_InitCard() : stm32h7xx_hal_mmc.c
  • MMC_PowerOFF() : stm32h7xx_hal_mmc.c
  • MMC_PowerON() : stm32h7xx_hal_mmc.c
  • MMC_Read_IT() : stm32h7xx_hal_mmc.c
  • MMC_ReadExtCSD() : stm32h7xx_hal_mmc.c
  • MMC_SendStatus() : stm32h7xx_hal_mmc.c
  • MMC_Write_IT() : stm32h7xx_hal_mmc.c
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STM32H7B3xQ HAL User Manual: Globals

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- o -

  • OC1Config() : stm32h7xx_ll_tim.c
  • OC2Config() : stm32h7xx_ll_tim.c
  • OC3Config() : stm32h7xx_ll_tim.c
  • OC4Config() : stm32h7xx_ll_tim.c
  • OC5Config() : stm32h7xx_ll_tim.c
  • OC6Config() : stm32h7xx_ll_tim.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- p -

  • PCD_EP_OutSetupPacket_int() : stm32h7xx_hal_pcd.c
  • PCD_EP_OutXfrComplete_int() : stm32h7xx_hal_pcd.c
  • PCD_WriteEmptyTxFifo() : stm32h7xx_hal_pcd.c
  • PSSI_DMAAbort() : stm32h7xx_hal_pssi.c
  • PSSI_DMAError() : stm32h7xx_hal_pssi.c
  • PSSI_DMAReceiveCplt() : stm32h7xx_hal_pssi.c
  • PSSI_DMATransmitCplt() : stm32h7xx_hal_pssi.c
  • PSSI_Error() : stm32h7xx_hal_pssi.c
  • PSSI_WaitOnStatusUntilTimeout() : stm32h7xx_hal_pssi.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- r -

  • RCC_GetHCLKClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK3ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetPCLK4ClockFreq() : stm32h7xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32h7xx_ll_rcc.c
  • RCCEx_PLL2_Config() : stm32h7xx_hal_rcc_ex.c
  • RCCEx_PLL3_Config() : stm32h7xx_hal_rcc_ex.c
  • RTC_Bcd2ToByte() : stm32h7xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32h7xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32h7xx_hal_rtc.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- s -

  • SAI_Disable() : stm32h7xx_hal_sai.c
  • SAI_DMAAbort() : stm32h7xx_hal_sai.c
  • SAI_DMAError() : stm32h7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_FillFifo() : stm32h7xx_hal_sai.c
  • SAI_InitI2S() : stm32h7xx_hal_sai.c
  • SAI_InitPCM() : stm32h7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32h7xx_hal_sai.c
  • SD_DDR_Mode() : stm32h7xx_hal_sd.c
  • SD_FindSCR() : stm32h7xx_hal_sd.c
  • SD_HighSpeed() : stm32h7xx_hal_sd.c
  • SD_InitCard() : stm32h7xx_hal_sd.c
  • SD_PowerOFF() : stm32h7xx_hal_sd.c
  • SD_PowerON() : stm32h7xx_hal_sd.c
  • SD_Read_IT() : stm32h7xx_hal_sd.c
  • SD_SendSDStatus() : stm32h7xx_hal_sd.c
  • SD_SendStatus() : stm32h7xx_hal_sd.c
  • SD_UltraHighSpeed() : stm32h7xx_hal_sd.c
  • SD_WideBus_Disable() : stm32h7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32h7xx_hal_sd.c
  • SD_Write_IT() : stm32h7xx_hal_sd.c
  • SMARTCARD_AdvFeatureConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_InitCallbacksToDefault() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_RxISR() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TxISR() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smartcard.c
  • SMARTCARDEx_SetNbDataToProcess() : stm32h7xx_hal_smartcard_ex.c
  • SMBUS_ConvertOtherXferOptions() : stm32h7xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_ITErrorHandler() : stm32h7xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32h7xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smbus.c
  • SPDIFRX_DMACxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spdifrx.c
  • SPI_AbortTransfer() : stm32h7xx_hal_spi.c
  • SPI_CloseTransfer() : stm32h7xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32h7xx_hal_spi.c
  • SPI_DMAError() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_GetPacketSize() : stm32h7xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spi.c
  • SWPMI_DMAAbortOnError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32h7xx_hal_swpmi.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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  • m
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  • r
  • s
  • t
  • u

- t -

  • TIM_Base_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32h7xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32h7xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32h7xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32h7xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMAError() : stm32h7xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32h7xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32h7xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_ResetCallback() : stm32h7xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32h7xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32h7xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32h7xx_hal_tim_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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  • c
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  • m
  • o
  • p
  • r
  • s
  • t
  • u

- u -

  • UART_AdvFeatureConfig() : stm32h7xx_hal_uart.c
  • UART_CheckIdleState() : stm32h7xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32h7xx_hal_uart.c
  • UART_DMAError() : stm32h7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_EndRxTransfer() : stm32h7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32h7xx_hal_uart.c
  • UART_EndTxTransfer() : stm32h7xx_hal_uart.c
  • UART_InitCallbacksToDefault() : stm32h7xx_hal_uart.c
  • UART_RxISR_16BIT() : stm32h7xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32h7xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_SetConfig() : stm32h7xx_hal_uart.c
  • UART_TxISR_16BIT() : stm32h7xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32h7xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32h7xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_uart.c
  • UARTEx_SetNbDataToProcess() : stm32h7xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32h7xx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32h7xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32h7xx_hal_usart.c
  • USART_DMAError() : stm32h7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32h7xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32h7xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_EndTransfer() : stm32h7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32h7xx_hal_usart.c
  • USART_InitCallbacksToDefault() : stm32h7xx_hal_usart.c
  • USART_RxISR_16BIT() : stm32h7xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32h7xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_SetConfig() : stm32h7xx_hal_usart.c
  • USART_TxISR_16BIT() : stm32h7xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32h7xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32h7xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_usart.c
  • USARTEx_SetNbDataToProcess() : stm32h7xx_hal_usart_ex.c
  • UTILS_CalculateFlashLatency() : stm32h7xx_ll_utils.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32h7xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32h7xx_ll_utils.c
  • UTILS_IsPLLsReady() : stm32h7xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32h7xx_ll_utils.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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  • Typedefs
  • Enumerations
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  • a
  • d
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  • o
  • p
  • s
  • u
  • v

- a -

  • a_dfsdm1ChannelHandle : stm32h7xx_hal_dfsdm.c
  • a_dfsdm2ChannelHandle : stm32h7xx_hal_dfsdm.c

- d -

  • DLCtoBytes : stm32h7xx_hal_fdcan.c

- j -

  • JPEG_ACCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_ACLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_ZIGZAG_ORDER : stm32h7xx_hal_jpeg.c

- l -

  • LL_BDMA_CH_OFFSET_TAB : stm32h7xx_ll_bdma.h
  • LL_DMA_STR_OFFSET_TAB : stm32h7xx_ll_dma.h
  • LL_MDMA_CH_OFFSET_TAB : stm32h7xx_ll_mdma.h
  • LL_RCC_PrescTable : stm32h7xx_ll_rcc.c , stm32h7xx_ll_rcc.h
  • LPUART_PRESCALER_TAB : stm32h7xx_ll_lpuart.h

- o -

  • OFFSET_TAB_CCMRx : stm32h7xx_ll_tim.h

- p -

  • pFlash : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h

- s -

  • SHIFT_TAB_CCxP : stm32h7xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32h7xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32h7xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32h7xx_ll_tim.h

- u -

  • USART_PRESCALER_TAB : stm32h7xx_ll_usart.h
  • uwNORMemoryDataWidth : stm32h7xx_hal_nor.c
  • uwTick : stm32h7xx_hal.h , stm32h7xx_hal.c
  • uwTickFreq : stm32h7xx_hal.c , stm32h7xx_hal.h
  • uwTickPrio : stm32h7xx_hal.h , stm32h7xx_hal.c

- v -

  • v_dfsdm1ChannelCounter : stm32h7xx_hal_dfsdm.c
  • v_dfsdm2ChannelCounter : stm32h7xx_hal_dfsdm.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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  • s
  • t
  • u
  • w

- a -

  • ADC_HandleTypeDef : stm32h7xx_hal_adc.h

- c -

  • CEC_HandleTypeDef : stm32h7xx_hal_cec.h
  • COMP_HandleTypeDef : stm32h7xx_hal_comp.h
  • CRYP_HandleTypeDef : stm32h7xx_hal_cryp.h

- d -

  • DAC_HandleTypeDef : stm32h7xx_hal_dac.h
  • DCMI_HandleTypeDef : stm32h7xx_hal_dcmi.h
  • DFSDM_Channel_HandleTypeDef : stm32h7xx_hal_dfsdm.h
  • DFSDM_Filter_HandleTypeDef : stm32h7xx_hal_dfsdm.h
  • DMA_HandleTypeDef : stm32h7xx_hal_dma.h

- f -

  • FDCAN_HandleTypeDef : stm32h7xx_hal_fdcan.h

- g -

  • GFXMMU_HandleTypeDef : stm32h7xx_hal_gfxmmu.h

- h -

  • HAL_CEC_StateTypeDef : stm32h7xx_hal_cec.h
  • HAL_IRDA_StateTypeDef : stm32h7xx_hal_irda.h
  • HAL_MMC_CardStateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_OPAMP_TrimmingValueTypeDef : stm32h7xx_hal_opamp.h
  • HAL_SD_CardStateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SMARTCARD_StateTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_UART_StateTypeDef : stm32h7xx_hal_uart.h
  • HASH_HandleTypeDef : stm32h7xx_hal_hash.h
  • HCD_HandleTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HCStateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32h7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32h7xx_hal_hcd.h
  • HCD_TypeDef : stm32h7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32h7xx_hal_hcd.h

- i -

  • I2C_HandleTypeDef : stm32h7xx_hal_i2c.h
  • I2S_HandleTypeDef : stm32h7xx_hal_i2s.h
  • IRDA_HandleTypeDef : stm32h7xx_hal_irda.h

- j -

  • JPEG_HandleTypeDef : stm32h7xx_hal_jpeg.h

- l -

  • LPTIM_HandleTypeDef : stm32h7xx_hal_lptim.h
  • LTDC_HandleTypeDef : stm32h7xx_hal_ltdc.h

- m -

  • MDIOS_HandleTypeDef : stm32h7xx_hal_mdios.h
  • MDMA_HandleTypeDef : stm32h7xx_hal_mdma.h
  • MMC_HandleTypeDef : stm32h7xx_hal_mmc.h

- n -

  • NAND_HandleTypeDef : stm32h7xx_hal_nand.h
  • NOR_HandleTypeDef : stm32h7xx_hal_nor.h

- o -

  • OPAMP_HandleTypeDef : stm32h7xx_hal_opamp.h
  • OSPI_HandleTypeDef : stm32h7xx_hal_ospi.h

- p -

  • pADC_CallbackTypeDef : stm32h7xx_hal_adc.h
  • PCD_EPTypeDef : stm32h7xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32h7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32h7xx_hal_pcd.h
  • PCD_TypeDef : stm32h7xx_hal_pcd.h
  • pCEC_CallbackTypeDef : stm32h7xx_hal_cec.h
  • pCEC_RxCallbackTypeDef : stm32h7xx_hal_cec.h
  • pCOMP_CallbackTypeDef : stm32h7xx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32h7xx_hal_cryp.h
  • pDAC_CallbackTypeDef : stm32h7xx_hal_dac.h
  • pDCMI_CallbackTypeDef : stm32h7xx_hal_dcmi.h
  • pDFSDM_Channel_CallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pDFSDM_Filter_AwdCallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pDFSDM_Filter_CallbackTypeDef : stm32h7xx_hal_dfsdm.h
  • pFDCAN_CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_ClockCalibrationCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_GlobalTimeCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_ScheduleSyncCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_StopWatchCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TT_TimeMarkCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32h7xx_hal_fdcan.h
  • pGFXMMU_CallbackTypeDef : stm32h7xx_hal_gfxmmu.h
  • pHASH_CallbackTypeDef : stm32h7xx_hal_hash.h
  • pHCD_CallbackTypeDef : stm32h7xx_hal_hcd.h
  • pHCD_HC_NotifyURBChangeCallbackTypeDef : stm32h7xx_hal_hcd.h
  • pI2C_AddrCallbackTypeDef : stm32h7xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32h7xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32h7xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32h7xx_hal_irda.h
  • pJPEG_CallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_DataReadyCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_GetDataCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pJPEG_InfoReadyCallbackTypeDef : stm32h7xx_hal_jpeg.h
  • pLPTIM_CallbackTypeDef : stm32h7xx_hal_lptim.h
  • pLTDC_CallbackTypeDef : stm32h7xx_hal_ltdc.h
  • pMDIOS_CallbackTypeDef : stm32h7xx_hal_mdios.h
  • pMMC_CallbackTypeDef : stm32h7xx_hal_mmc.h
  • pNAND_CallbackTypeDef : stm32h7xx_hal_nand.h
  • pNOR_CallbackTypeDef : stm32h7xx_hal_nor.h
  • pOPAMP_CallbackTypeDef : stm32h7xx_hal_opamp.h
  • pOSPI_CallbackTypeDef : stm32h7xx_hal_ospi.h
  • pPCD_BcdCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32h7xx_hal_pcd.h
  • pPSSI_CallbackTypeDef : stm32h7xx_hal_pssi.h
  • pRNG_CallbackTypeDef : stm32h7xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32h7xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32h7xx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32h7xx_hal_sai.h
  • pSD_CallbackTypeDef : stm32h7xx_hal_sd.h
  • pSD_TransceiverCallbackTypeDef : stm32h7xx_hal_sd.h
  • pSDRAM_CallbackTypeDef : stm32h7xx_hal_sdram.h
  • pSDRAM_DmaCallbackTypeDef : stm32h7xx_hal_sdram.h
  • pSMARTCARD_CallbackTypeDef : stm32h7xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32h7xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32h7xx_hal_smbus.h
  • pSPDIFRX_CallbackTypeDef : stm32h7xx_hal_spdifrx.h
  • pSPI_CallbackTypeDef : stm32h7xx_hal_spi.h
  • pSRAM_CallbackTypeDef : stm32h7xx_hal_sram.h
  • pSRAM_DmaCallbackTypeDef : stm32h7xx_hal_sram.h
  • PSSI_HandleTypeDef : stm32h7xx_hal_pssi.h
  • pSWPMI_CallbackTypeDef : stm32h7xx_hal_swpmi.h
  • pTIM_CallbackTypeDef : stm32h7xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32h7xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32h7xx_hal_usart.h
  • pWWDG_CallbackTypeDef : stm32h7xx_hal_wwdg.h

- r -

  • RAMECC_HandleTypeDef : stm32h7xx_hal_ramecc.h
  • RNG_HandleTypeDef : stm32h7xx_hal_rng.h
  • RTC_HandleTypeDef : stm32h7xx_hal_rtc.h

- s -

  • SAI_HandleTypeDef : stm32h7xx_hal_sai.h
  • SAIcallback : stm32h7xx_hal_sai.h
  • SD_HandleTypeDef : stm32h7xx_hal_sd.h
  • SDRAM_HandleTypeDef : stm32h7xx_hal_sdram.h
  • SMARTCARD_HandleTypeDef : stm32h7xx_hal_smartcard.h
  • SMBUS_HandleTypeDef : stm32h7xx_hal_smbus.h
  • SPDIFRX_HandleTypeDef : stm32h7xx_hal_spdifrx.h
  • SPI_HandleTypeDef : stm32h7xx_hal_spi.h
  • SRAM_HandleTypeDef : stm32h7xx_hal_sram.h
  • SWPMI_HandleTypeDef : stm32h7xx_hal_swpmi.h

- t -

  • TIM_HandleTypeDef : stm32h7xx_hal_tim.h

- u -

  • UART_HandleTypeDef : stm32h7xx_hal_uart.h
  • USART_HandleTypeDef : stm32h7xx_hal_usart.h

- w -

  • WWDG_HandleTypeDef : stm32h7xx_hal_wwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • e
  • f
  • g
  • h
  • i
  • p
  • s
  • u

- e -

  • EXTI_CallbackIDTypeDef : stm32h7xx_hal_exti.h

- f -

  • FLASH_ProcedureTypeDef : stm32h7xx_hal_flash.h

- g -

  • GPIO_PinState : stm32h7xx_hal_gpio.h

- h -

  • HAL_ADC_CallbackIDTypeDef : stm32h7xx_hal_adc.h
  • HAL_CEC_CallbackIDTypeDef : stm32h7xx_hal_cec.h
  • HAL_COMP_CallbackIDTypeDef : stm32h7xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32h7xx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32h7xx_hal_crc.h
  • HAL_CRYP_CallbackIDTypeDef : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32h7xx_hal_cryp.h
  • HAL_DAC_CallbackIDTypeDef : stm32h7xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32h7xx_hal_dac.h
  • HAL_DCMI_CallbackIDTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_StateTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DFSDM_Channel_CallbackIDTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_CallbackIDTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DMA_CallbackIDTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32h7xx_hal_dma_ex.h
  • HAL_DMA_StateTypeDef : stm32h7xx_hal_dma.h
  • HAL_FDCAN_CallbackIDTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_GFXMMU_CallbackIDTypeDef : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_StateTypeDef : stm32h7xx_hal_gfxmmu.h
  • HAL_HASH_CallbackIDTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_PhaseTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_StateTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SuspendTypeDef : stm32h7xx_hal_hash.h
  • HAL_HCD_CallbackIDTypeDef : stm32h7xx_hal_hcd.h
  • HAL_I2C_CallbackIDTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2S_CallbackIDTypeDef : stm32h7xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32h7xx_hal_i2s.h
  • HAL_IRDA_CallbackIDTypeDef : stm32h7xx_hal_irda.h
  • HAL_JPEG_CallbackIDTypeDef : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATETypeDef : stm32h7xx_hal_jpeg.h
  • HAL_LPTIM_CallbackIDTypeDef : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h
  • HAL_LTDC_CallbackIDTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_StateTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_MDIOS_CallbackIDTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_StateTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDMA_CallbackIDTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_LevelCompleteTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_StateTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MMC_CallbackIDTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMC_StateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMCEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_mmc_ex.h
  • HAL_NAND_CallbackIDTypeDef : stm32h7xx_hal_nand.h
  • HAL_NAND_StateTypeDef : stm32h7xx_hal_nand.h
  • HAL_NOR_CallbackIDTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_StateTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32h7xx_hal_nor.h
  • HAL_OPAMP_CallbackIDTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OSPI_CallbackIDTypeDef : stm32h7xx_hal_ospi.h
  • HAL_PCD_CallbackIDTypeDef : stm32h7xx_hal_pcd.h
  • HAL_PSSI_CallbackIDTypeDef : stm32h7xx_hal_pssi.h
  • HAL_PSSI_StateTypeDef : stm32h7xx_hal_pssi.h
  • HAL_RAMECC_StateTypeDef : stm32h7xx_hal_ramecc.h
  • HAL_RNG_CallbackIDTypeDef : stm32h7xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32h7xx_hal_rng.h
  • HAL_RTC_CallbackIDTypeDef : stm32h7xx_hal_rtc.h
  • HAL_RTCStateTypeDef : stm32h7xx_hal_rtc.h
  • HAL_SAI_CallbackIDTypeDef : stm32h7xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32h7xx_hal_sai.h
  • HAL_SD_CallbackIDTypeDef : stm32h7xx_hal_sd.h
  • HAL_SD_StateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SDEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_sd_ex.h
  • HAL_SDRAM_CallbackIDTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_StateTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMBUS_CallbackIDTypeDef : stm32h7xx_hal_smbus.h
  • HAL_SPDIFRX_CallbackIDTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_StateTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPI_CallbackIDTypeDef : stm32h7xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32h7xx_hal_spi.h
  • HAL_SRAM_CallbackIDTypeDef : stm32h7xx_hal_sram.h
  • HAL_SRAM_StateTypeDef : stm32h7xx_hal_sram.h
  • HAL_SWPMI_CallbackIDTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_StateTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_TickFreqTypeDef : stm32h7xx_hal.h
  • HAL_TIM_ActiveChannel : stm32h7xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32h7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32h7xx_hal_tim.h
  • HAL_UART_CallbackIDTypeDef : stm32h7xx_hal_uart.h
  • HAL_USART_CallbackIDTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32h7xx_hal_usart.h
  • HAL_WWDG_CallbackIDTypeDef : stm32h7xx_hal_wwdg.h
  • HCD_StateTypeDef : stm32h7xx_hal_hcd.h

- i -

  • IRDA_ClockSourceTypeDef : stm32h7xx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32h7xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32h7xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32h7xx_hal_pcd.h
  • PWREx_MMC_VoltageLevel : stm32h7xx_hal_pwr_ex.h

- s -

  • SAI_ModeTypedef : stm32h7xx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32h7xx_hal_smartcard.h

- u -

  • UART_ClockSourceTypeDef : stm32h7xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32h7xx_hal_usart.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- f -

  • FLASH_PROC_ALLBANK_MASSERASE : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK2 : stm32h7xx_hal_flash.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- g -

  • GPIO_PIN_RESET : stm32h7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32h7xx_hal_gpio.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- h -

  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_MSPDEINIT_CB_ID : stm32h7xx_hal_adc.h
  • HAL_ADC_MSPINIT_CB_ID : stm32h7xx_hal_adc.h
  • HAL_CEC_ERROR_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_MSPDEINIT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_MSPINIT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_RX_CPLT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_CEC_TX_CPLT_CB_ID : stm32h7xx_hal_cec.h
  • HAL_COMP_MSPDEINIT_CB_ID : stm32h7xx_hal_comp.h
  • HAL_COMP_MSPINIT_CB_ID : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_BUSY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_TRIGGER_CB_ID : stm32h7xx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32h7xx_hal_crc.h
  • HAL_CRYP_ERROR_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_MSPINIT_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32h7xx_hal_cryp.h
  • HAL_DAC_ALL_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_MSPDEINIT_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_MSPINIT_CB_ID : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_BUSY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DCMI_ERROR_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_FRAME_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_LINE_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_MSPDEINIT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_MSPINIT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_BUSY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_SUSPENDED : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_VSYNC_EVENT_CB_ID : stm32h7xx_hal_dcmi.h
  • HAL_DFSDM_CHANNEL_CKAB_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_SCD_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_ERROR_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_MSPINIT_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DMA_FULL_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ABORT : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_EXTI_COMMON_CB_ID : stm32h7xx_hal_exti.h
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_MSPINIT_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_BUSY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_fdcan.h
  • HAL_GFXMMU_ERROR_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_MSPDEINIT_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_MSPINIT_CB_ID : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_STATE_READY : stm32h7xx_hal_gfxmmu.h
  • HAL_GFXMMU_STATE_RESET : stm32h7xx_hal_gfxmmu.h
  • HAL_HASH_DGSTCPLT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_INPUTCPLT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_MSPDEINIT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_MSPINIT_CB_ID : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_1 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_2 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_3 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_PROCESS : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_BUSY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_ERROR : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_RESET : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_SUSPENDED : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_TIMEOUT : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND_NONE : stm32h7xx_hal_hash.h
  • HAL_HCD_CONNECT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_DISCONNECT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_MSPDEINIT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_MSPINIT_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_PORT_DISABLED_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_PORT_ENABLED_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_SOF_CB_ID : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_BUSY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32h7xx_hal_hcd.h
  • HAL_I2C_ABORT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_MASTER : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32h7xx_hal_i2c.h
  • HAL_I2C_MSPDEINIT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_MSPINIT_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2S_ERROR_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_MSPDEINIT_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_MSPINIT_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_i2s.h
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_MSPINIT_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_irda.h
  • HAL_JPEG_DECODE_CPLT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ENCODE_CPLT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_MSPDEINIT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_MSPINIT_CB_ID : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_DECODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_ENCODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_ERROR : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_READY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_RESET : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MSPINIT_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TRIGGER_CB_ID : stm32h7xx_hal_lptim.h
  • HAL_LTDC_ERROR_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_LINE_EVENT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MSPDEINIT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MSPINIT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_RELOAD_EVENT_CB_ID : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_BUSY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_ERROR : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_READY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_RESET : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_MDIOS_ERROR_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_MSPDEINIT_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_MSPINIT_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_READ_COMPLETE_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_ERROR : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_READY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_RESET : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_WAKEUP_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_WRITE_COMPLETE_CB_ID : stm32h7xx_hal_mdios.h
  • HAL_MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ABORT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ERROR : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_READY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_RESET : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ABORT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ALL_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BUFFERCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_CPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ERROR_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MMC_ABORT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_MSP_DEINIT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_MSP_INIT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_RX_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_TX_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_mmc.h
  • HAL_NAND_IT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_MSP_DEINIT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_MSP_INIT_CB_ID : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_BUSY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32h7xx_hal_nand.h
  • HAL_NOR_MSP_DEINIT_CB_ID : stm32h7xx_hal_nor.h
  • HAL_NOR_MSP_INIT_CB_ID : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_BUSY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32h7xx_hal_nor.h
  • HAL_OPAMP_ALL_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_MSPDEINIT_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_MSPINIT_CB_ID : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32h7xx_hal_opamp.h
  • HAL_OSPI_ABORT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CMD_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FIFO_THRESHOLD_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MSP_DEINIT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MSP_INIT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_RX_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_RX_HALF_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATUS_MATCH_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TX_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TX_HALF_CPLT_CB_ID : stm32h7xx_hal_ospi.h
  • HAL_PCD_CONNECT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_DISCONNECT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_MSPDEINIT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_MSPINIT_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_RESET_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_RESUME_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_SOF_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_BUSY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32h7xx_hal_pcd.h
  • HAL_PCD_SUSPEND_CB_ID : stm32h7xx_hal_pcd.h
  • HAL_PSSI_ABORT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MSPDEINIT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MSPINIT_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RX_COMPLETE_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_ABORT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY_RX : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_BUSY_TX : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_ERROR : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_READY : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_RESET : stm32h7xx_hal_pssi.h
  • HAL_PSSI_STATE_TIMEOUT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_TX_COMPLETE_CB_ID : stm32h7xx_hal_pssi.h
  • HAL_RAMECC_STATE_BUSY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_ERROR : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_READY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_STATE_RESET : stm32h7xx_hal_ramecc.h
  • HAL_RNG_ERROR_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_MSPDEINIT_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_MSPINIT_CB_ID : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_MSPDEINIT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_MSPINIT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_BUSY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32h7xx_hal_rtc.h
  • HAL_SAI_ERROR_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_MSPDEINIT_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_MSPINIT_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32h7xx_hal_sai.h
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_sai.h
  • HAL_SD_ABORT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_MSP_DEINIT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_MSP_INIT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_RX_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_READY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_TX_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : stm32h7xx_hal_sd.h
  • HAL_SDRAM_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_DMA_XFER_ERR_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_MSP_DEINIT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_MSP_INIT_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_REFRESH_ERR_CB_ID : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_BUSY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32h7xx_hal_sdram.h
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MSPINIT_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32h7xx_hal_smbus.h
  • HAL_SPDIFRX_CX_CPLT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_CX_HALF_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MSPDEINIT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MSPINIT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_RX_CPLT_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_RX_HALF_CB_ID : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32h7xx_hal_spdifrx.h
  • HAL_SPI_ABORT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_MSPDEINIT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_MSPINIT_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32h7xx_hal_spi.h
  • HAL_SRAM_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_DMA_XFER_ERR_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_MSP_DEINIT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_MSP_INIT_CB_ID : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_BUSY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32h7xx_hal_sram.h
  • HAL_SWPMI_ERROR_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MSPDEINIT_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MSPINIT_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RX_COMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TX_COMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_swpmi.h
  • HAL_TICK_FREQ_100HZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32h7xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32h7xx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32h7xx_hal_tim.h
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_BREAK2_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ERROR_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32h7xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32h7xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32h7xx_hal_tim.h
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_MSPDEINIT_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_MSPINIT_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RX_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TX_COMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_uart.h
  • HAL_UART_WAKEUP_CB_ID : stm32h7xx_hal_uart.h
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_MSPDEINIT_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_MSPINIT_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32h7xx_hal_usart.h
  • HAL_USART_TX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32h7xx_hal_usart.h
  • HAL_WWDG_EWI_CB_ID : stm32h7xx_hal_wwdg.h
  • HAL_WWDG_MSPINIT_CB_ID : stm32h7xx_hal_wwdg.h
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STM32H7B3xQ HAL User Manual: Globals

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- i -

  • IRDA_CLOCKSOURCE_CSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_irda.h
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STM32H7B3xQ HAL User Manual: Globals

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- l -

  • LPM_L0 : stm32h7xx_hal_pcd.h
  • LPM_L1 : stm32h7xx_hal_pcd.h
  • LPM_L2 : stm32h7xx_hal_pcd.h
  • LPM_L3 : stm32h7xx_hal_pcd.h
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STM32H7B3xQ HAL User Manual: Globals

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- m -

  • MEMORY0 : stm32h7xx_hal_dma_ex.h
  • MEMORY1 : stm32h7xx_hal_dma_ex.h
  • MMC_DMA_BUFFER0 : stm32h7xx_hal_mmc_ex.h
  • MMC_DMA_BUFFER1 : stm32h7xx_hal_mmc_ex.h
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STM32H7B3xQ HAL User Manual: Globals

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- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32h7xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32h7xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32h7xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32h7xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32h7xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32h7xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32h7xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32h7xx_hal_pcd.h
  • PWR_MMC_VOLTAGE_BELOW_1V2 : stm32h7xx_hal_pwr_ex.h
  • PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 : stm32h7xx_hal_pwr_ex.h
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STM32H7B3xQ HAL User Manual: Globals

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- s -

  • SAI_MODE_DMA : stm32h7xx_hal_sai.c
  • SAI_MODE_IT : stm32h7xx_hal_sai.c
  • SD_DMA_BUFFER0 : stm32h7xx_hal_sd_ex.h
  • SD_DMA_BUFFER1 : stm32h7xx_hal_sd_ex.h
  • SMARTCARD_CLOCKSOURCE_CSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_smartcard.h
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STM32H7B3xQ HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_CSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_uart.h
  • USART_CLOCKSOURCE_CSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_usart.h
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STM32H7B3xQ HAL User Manual: Globals

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- _ -

  • __ADC_PTR_REG_OFFSET : stm32h7xx_ll_adc.h
  • __DAC_PTR_REG_OFFSET : stm32h7xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32h7xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32h7xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32h7xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32h7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32h7xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32h7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32h7xx_hal_adc.h
  • __HAL_BDMA_CHANNEL_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_BDMA_CHANNEL_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_BDMA_CHANNEL_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_BDMA_GET_GI_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_CEC_CLEAR_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32h7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32h7xx_hal_cec.h
  • __HAL_COMP_CLEAR_C1IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_C2IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_IT_SOURCE : stm32h7xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32h7xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32h7xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32h7xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32h7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32h7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32h7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRYP_DISABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32h7xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32h7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32h7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_WWDG1 : stm32h7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32h7xx_hal_dcmi.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DMA_CLEAR_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32h7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_STREAM_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FLASH_CALC_BOOT_BASE_ADR : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_CLEAR_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_PROGRAM_DELAY : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_SET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_SET_PROGRAM_DELAY : stm32h7xx_hal_flash_ex.h
  • __HAL_GFXMMU_RESET_HANDLE_STATE : stm32h7xx_hal_gfxmmu.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32h7xx_hal_gpio.h
  • __HAL_HASH_CLEAR_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_DISABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_ENABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_GET_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_INIT : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATE : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATUS : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_NBVALIDBITS : stm32h7xx_hal_hash.h
  • __HAL_HASH_START_DIGEST : stm32h7xx_hal_hash.h
  • __HAL_HCD_CLEAR_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HSEM_CLEAR_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32h7xx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32h7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_TIFREFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32h7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32h7xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32h7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32h7xx_hal_iwdg.h
  • __HAL_JPEG_CLEAR_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_IT_SOURCE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_RESET_HANDLE_STATE : stm32h7xx_hal_jpeg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32h7xx_hal_lptim.h
  • __HAL_LTDC_CLEAR_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_IT_SOURCE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RESET_HANDLE_STATE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_MDIOS_CLEAR_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_IT_SOURCE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_READ_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_WRITE_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_RESET_HANDLE_STATE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDMA_CLEAR_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_IT_SOURCE : stm32h7xx_hal_mdma.h
  • __HAL_MMC_CLEAR_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_CLEAR_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_DISABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_ENABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_RESET_HANDLE_STATE : stm32h7xx_hal_mmc.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32h7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32h7xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32h7xx_hal_opamp.h
  • __HAL_OSPI_CLEAR_FLAG : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_DISABLE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_DISABLE_IT : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_ENABLE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_ENABLE_IT : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_GET_FLAG : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_GET_IT_SOURCE : stm32h7xx_hal_ospi.h
  • __HAL_OSPI_RESET_HANDLE_STATE : stm32h7xx_hal_ospi.h
  • __HAL_PCD_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32h7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PWR_AVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_CLEAR_WAKEUPFLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_WAKEUPFLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32h7xx_hal_pwr.h
  • __HAL_RAMECC_CLEAR_FLAG : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_GLOBAL_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_DISABLE_MONITOR_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_GLOBAL_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_ENABLE_MONITOR_IT : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_FLAG : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_GLOBAL_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_GET_MONITOR_IT_SOURCE : stm32h7xx_hal_ramecc.h
  • __HAL_RAMECC_RESET_HANDLE_STATE : stm32h7xx_hal_ramecc.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB12_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB12_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB34_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB34_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM1_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM1_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM2_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM2_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM3_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXIRAM3_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLKP_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_COMP12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRYP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_PSSI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ECCRAM_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ECCRAM_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_EXTI_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_EXTI_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLIFT_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLIFT_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLKP_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_FMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HSI_DIVIDER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C123_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM345_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_OSPI_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2A_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2B_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPDIFRX_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI123_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI45_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART9_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART10_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART16910_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART16_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART234578_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GFXMMU_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMU_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUM_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUM_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUS_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GFXMMUS_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIO_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIO_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C123_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_IOMNGR_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JTAG_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JTAG_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM345_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI1_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI1_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI2_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPI2_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OSPI_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_OTFDEC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OTFDEC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCIRANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCORANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2A_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2B_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CLKGA_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CLKGA_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI123_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI45_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART9_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART9_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART10_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART10_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART16910_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART16_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART234578_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_VREF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED : stm32h7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32h7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32h7xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32h7xx_hal_rtc.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_PRCHRG_DURATION : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_PULLUP_STATUS : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_SAMPLES_COUNT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_GET_STATUS : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32h7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32h7xx_hal_sai.h
  • __HAL_SD_CLEAR_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_CLEAR_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_DISABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_ENABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_RESET_HANDLE_STATE : stm32h7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32h7xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32h7xx_hal_smbus.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32h7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_EOTFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_SUSPFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TSERFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TXTFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_UDRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32h7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32h7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK : stm32h7xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32h7xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32h7xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32h7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32h7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32h7xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32h7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32h7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32h7xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32h7xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32h7xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32h7xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32h7xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32h7xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32h7xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32h7xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32h7xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32h7xx_ll_adc.h
  • __LL_ADC_MULTI_INSTANCE_MASTER : stm32h7xx_ll_adc.h
  • __LL_BDMA_GET_CHANNEL : stm32h7xx_ll_bdma.h
  • __LL_BDMA_GET_CHANNEL_INSTANCE : stm32h7xx_ll_bdma.h
  • __LL_BDMA_GET_INSTANCE : stm32h7xx_ll_bdma.h
  • __LL_COMP_COMMON_INSTANCE : stm32h7xx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32h7xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32h7xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32h7xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32h7xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32h7xx_ll_dac.h
  • __LL_DMA_GET_INSTANCE : stm32h7xx_ll_dma.h
  • __LL_DMA_GET_STREAM : stm32h7xx_ll_dma.h
  • __LL_DMA_GET_STREAM_INSTANCE : stm32h7xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32h7xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32h7xx_ll_lpuart.h
  • __LL_OPAMP_COMMON_INSTANCE : stm32h7xx_ll_opamp.h
  • __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE : stm32h7xx_ll_opamp.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32h7xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32h7xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32h7xx_ll_rtc.h
  • __LL_SWPMI_CALC_BITRATE_PRESCALER : stm32h7xx_ll_swpmi.h
  • __LL_TIM_CALC_ARR : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32h7xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32h7xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32h7xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32h7xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32h7xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32h7xx_ll_usart.h
  • __OPAMP_PTR_REG_OFFSET : stm32h7xx_ll_opamp.h
  • __STM32H7xx_HAL_VERSION : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_MAIN : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_RC : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB1 : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB2 : stm32h7xx_hal.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- a -

  • ADC12_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC12_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_1 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32h7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32h7xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32h7xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_AWD_EVENT : stm32h7xx_hal_adc.h
  • ADC_AWD_TR12_REGOFFSETGAP_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_TR12_REGOFFSETGAP_VAL : stm32h7xx_ll_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_FACTOR_LINEARITY_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_CALIB_FACTOR_OFFSET_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_CALIB_FACTOR_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_MODE_BINARY_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_MODE_MASK : stm32h7xx_ll_adc.h
  • ADC_CALIB_OFFSET : stm32h7xx_hal_adc.h
  • ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_hal_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32h7xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CFGR_AUTOWAIT : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32h7xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_19_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_19_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC2CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32h7xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32h7xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32h7xx_hal_adc.c
  • ADC_CONVERSIONDATA_DFSDM : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_CIRCULAR : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_ONESHOT : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DR : stm32h7xx_hal_adc.h
  • ADC_CR_BITS_PROPERTY_RS : stm32h7xx_ll_adc.h
  • ADC_DFSDM_MODE_DISABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DFSDM_MODE_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DIFFERENTIAL_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_32_10_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_8_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_DISABLED : stm32h7xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32h7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32h7xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM1_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM2_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM3_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM1_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM2_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM3_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32h7xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32h7xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOC : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOS : stm32h7xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32h7xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32h7xx_hal_adc.h
  • ADC_FLAG_JEOS : stm32h7xx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32h7xx_hal_adc.h
  • ADC_FLAG_OVR : stm32h7xx_hal_adc.h
  • ADC_FLAG_RDY : stm32h7xx_hal_adc.h
  • ADC_FORCE_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32h7xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32h7xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32h7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SYNCHRONOUS_CLOCK_MODE : stm32h7xx_hal_adc.h
  • ADC_IT_AWD : stm32h7xx_hal_adc.h
  • ADC_IT_AWD1 : stm32h7xx_hal_adc.h
  • ADC_IT_AWD2 : stm32h7xx_hal_adc.h
  • ADC_IT_AWD3 : stm32h7xx_hal_adc.h
  • ADC_IT_EOC : stm32h7xx_hal_adc.h
  • ADC_IT_EOS : stm32h7xx_hal_adc.h
  • ADC_IT_EOSMP : stm32h7xx_hal_adc.h
  • ADC_IT_JEOC : stm32h7xx_hal_adc.h
  • ADC_IT_JEOS : stm32h7xx_hal_adc.h
  • ADC_IT_JQOVF : stm32h7xx_hal_adc.h
  • ADC_IT_OVR : stm32h7xx_hal_adc.h
  • ADC_IT_RDY : stm32h7xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32h7xx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_1 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_10 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_11 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_12 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_13 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_14 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_15 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_2 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_3 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_4 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_5 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_6 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_7 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_8 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_9 : stm32h7xx_hal_adc.h
  • ADC_LEFTBITSHIFT_NONE : stm32h7xx_hal_adc.h
  • ADC_LINEAR_CALIB_REG_1_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_2_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_3_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_4_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_5_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_6_ADDR : stm32h7xx_ll_adc.h
  • ADC_LINEAR_CALIB_REG_COUNT : stm32h7xx_ll_adc.h
  • ADC_LINEARITY_BIT_TOGGLE_TIMEOUT : stm32h7xx_ll_adc.h
  • ADC_MASTER_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_OFR_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_OFRx_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32h7xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32h7xx_hal_adc.h
  • ADC_OVR_EVENT : stm32h7xx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32h7xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32h7xx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32h7xx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_14B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_16B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_10 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_11 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_9 : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_16CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_32CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_387CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_64CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_810CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SAMPLETIME_8CYCLES_5 : stm32h7xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32h7xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32h7xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32h7xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32h7xx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32h7xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32h7xx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32h7xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32h7xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32h7xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32h7xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32h7xx_ll_adc.c
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32h7xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32h7xx_hal_adc.h
  • ADC_TRX_HIGHTHRESHOLD : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32h7xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_AREA : stm32h7xx_hal_nand.h
  • ANALOG_MODE : stm32h7xx_hal_gpio.c
  • ARRAY_ADDRESS : stm32h7xx_hal_nand.h
  • assert_param : stm32h7xx_ll_rtc.c , stm32h7xx_hal_conf.h , stm32h7xx_ll_hrtim.c , stm32h7xx_ll_gpio.c , stm32h7xx_ll_dac.c , stm32h7xx_ll_opamp.c , stm32h7xx_ll_adc.c , stm32h7xx_ll_mdma.c , stm32h7xx_ll_rcc.c , stm32h7xx_ll_swpmi.c , stm32h7xx_ll_comp.c , stm32h7xx_ll_dma2d.c , stm32h7xx_ll_i2c.c , stm32h7xx_ll_lptim.c , stm32h7xx_ll_utils.c , stm32h7xx_ll_spi.c , stm32h7xx_ll_lpuart.c , stm32h7xx_ll_bdma.c , stm32h7xx_ll_exti.c , stm32h7xx_ll_crc.c , stm32h7xx_ll_dma.c , stm32h7xx_ll_tim.c , stm32h7xx_ll_rng.c , stm32h7xx_ll_usart.c
  • AVD_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_EVT : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_IT : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- b -

  • BDMA_CH6_CLEAR : stm32h7xx_hal.h
  • BDMA_CH7_CLEAR : stm32h7xx_hal.h
  • BDMA_FLAG_GL0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE7 : stm32h7xx_hal_dma.h
  • BDMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.c
  • BDMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_REQUEST_DAC2_CH1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_DFSDM2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LPUART1_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LPUART1_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_TX : stm32h7xx_hal_dma.h
  • BKP_REG_NUMBER : stm32h7xx_hal_rtc_ex.h
  • BLOCKSIZE : stm32h7xx_hal_sd.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
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  • Typedefs
  • Enumerations
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  • _
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- c -

  • CARD_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_NORMAL_SPEED : stm32h7xx_hal_sd.h
  • CARD_SDHC_SDXC : stm32h7xx_hal_sd.h
  • CARD_SDSC : stm32h7xx_hal_sd.h
  • CARD_SECURED : stm32h7xx_hal_sd.h
  • CARD_ULTRA_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_V1_X : stm32h7xx_hal_sd.h
  • CARD_V2_X : stm32h7xx_hal_sd.h
  • CCU_IR_MASK : stm32h7xx_hal_fdcan.h
  • CDCCIP : stm32h7xx_ll_rcc.h
  • CDCCIP1 : stm32h7xx_ll_rcc.h
  • CDCCIP2 : stm32h7xx_ll_rcc.h
  • CEC_0_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32h7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32h7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32h7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32h7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32h7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32h7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32h7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32h7xx_hal_cec.h
  • CEC_IT_BRE : stm32h7xx_hal_cec.h
  • CEC_IT_LBPE : stm32h7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_RXBR : stm32h7xx_hal_cec.h
  • CEC_IT_RXEND : stm32h7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32h7xx_hal_cec.h
  • CEC_IT_SBPE : stm32h7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_TXBR : stm32h7xx_hal_cec.h
  • CEC_IT_TXEND : stm32h7xx_hal_cec.h
  • CEC_IT_TXERR : stm32h7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32h7xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32h7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32h7xx_hal_cec.h
  • CFI1_ADDRESS : stm32h7xx_hal_nor.h
  • CFI2_ADDRESS : stm32h7xx_hal_nor.h
  • CFI3_ADDRESS : stm32h7xx_hal_nor.h
  • CFI4_ADDRESS : stm32h7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CM7_CPUID : stm32h7xx_hal_cortex.h
  • CMD_AREA : stm32h7xx_hal_nand.h
  • COLUMN_1ST_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_2ND_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_ADDRESS : stm32h7xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C1IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C2IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32h7xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32h7xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32h7xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32h7xx_hal_comp.h
  • COMP_EXTI_IT : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32h7xx_hal_comp.h
  • COMP_EXTI_RISING : stm32h7xx_hal_comp.h
  • COMP_FLAG_C1I : stm32h7xx_hal_comp.h
  • COMP_FLAG_C2I : stm32h7xx_hal_comp.h
  • COMP_FLAG_LOCK : stm32h7xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_TPSENS_DAC2CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VBAT_VDDAP : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_DAC2_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_IT_EN : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32h7xx_hal_comp.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32h7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32h7xx_hal_crc.h
  • CRYP_AES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_AES_CCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_CTR : stm32h7xx_hal_cryp.h
  • CRYP_AES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_AES_GCM : stm32h7xx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32h7xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32h7xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32h7xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32h7xx_hal_cryp.h
  • CRYP_DES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_DES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFEM : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFNF : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_INRIS : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFFU : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFNE : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OUTRIS : stm32h7xx_hal_cryp.h
  • CRYP_IT_INI : stm32h7xx_hal_cryp.h
  • CRYP_IT_OUTI : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_192B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32h7xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_FINAL : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_PAYLOAD : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_PROCESS : stm32h7xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32h7xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32h7xx_hal_cryp.c
  • CRYP_TDES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_TDES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32h7xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32h7xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32h7xx_hal_cryp_ex.c
  • CSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CSI_VALUE : stm32h7xx_hal_conf.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • d
  • e
  • f
  • g
  • h
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- d -

  • DAC_ALIGN_12B_L : stm32h7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32h7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_BOTH : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_EXTERNAL : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_INTERNAL : stm32h7xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32h7xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32h7xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32h7xx_ll_dac.h
  • DAC_FLAG_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32h7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32h7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32h7xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32h7xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32h7xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32h7xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32h7xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32h7xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32h7xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM1_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM2_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LPTIM3_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32h7xx_hal_dac.h
  • DCMI_BSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_4 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_OTHER : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALL_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_10B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32h7xx_hal_dcmi.h
  • DCMI_IT_OVR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_MIS_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_CONTINUOUS : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_FALLING : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32h7xx_hal_dcmi.h
  • DCMI_SR_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32h7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32h7xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32h7xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM2_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_ADC_OUTPUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CKAB_TIMEOUT : stm32h7xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32h7xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_COMP1_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_COMP2_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32h7xx_hal_dfsdm.h
  • DIVIDER_P_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32h7xx_hal_rcc_ex.c
  • DLYB_MAX_SELECT : stm32h7xx_ll_delayblock.h
  • DLYB_MAX_UNIT : stm32h7xx_ll_delayblock.h
  • DLYB_TIMEOUT : stm32h7xx_ll_delayblock.c
  • DMA2D_TIMEOUT_ABORT : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_SUSPEND : stm32h7xx_hal_dma2d.c
  • DMA_CIRCULAR : stm32h7xx_hal_dma.h
  • DMA_DOUBLE_BUFFER_M0 : stm32h7xx_hal_dma.h
  • DMA_DOUBLE_BUFFER_M1 : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_IT_DME : stm32h7xx_hal_dma.h
  • DMA_IT_FE : stm32h7xx_hal_dma.h
  • DMA_IT_HT : stm32h7xx_hal_dma.h
  • DMA_IT_TC : stm32h7xx_hal_dma.h
  • DMA_IT_TE : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_NORMAL : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_PFCTRL : stm32h7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_OUT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI_PSSI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HASH_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_CS : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_DT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART9_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART9_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART10_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART10_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32h7xx_hal_dma.h
  • DMA_TO_BDMA_DIRECTION : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_IT : stm32h7xx_hal_dma.h
  • DMA_TO_BDMA_MDATA_SIZE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_MEMORY_INC : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_MODE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PDATA_SIZE : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PERIPHERAL_INC : stm32h7xx_hal_dma.c
  • DMA_TO_BDMA_PRIORITY : stm32h7xx_hal_dma.c
  • DMAMUX_CCR_SIZE : stm32h7xx_ll_dmamux.h
  • DMAMUX_CH_STATUS_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_REQ_GEN_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_REQ_GEN_STATUS_OFFSET : stm32h7xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32h7xx_ll_dmamux.h
  • DT_DELAY_1 : stm32h7xx_ll_tim.h
  • DT_DELAY_2 : stm32h7xx_ll_tim.h
  • DT_DELAY_3 : stm32h7xx_ll_tim.h
  • DT_DELAY_4 : stm32h7xx_ll_tim.h
  • DT_RANGE_1 : stm32h7xx_ll_tim.h
  • DT_RANGE_2 : stm32h7xx_ll_tim.h
  • DT_RANGE_3 : stm32h7xx_ll_tim.h
  • DT_RANGE_4 : stm32h7xx_ll_tim.h
  • DTS_DELAY_STARTUP : stm32h7xx_hal_dts.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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- e -

  • eMMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • eMMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • ETH_MAC_ADDR0 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR1 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR2 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR3 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR4 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR5 : stm32h7xx_hal_conf.h
  • ETH_RX_DESC_CNT : stm32h7xx_hal_conf.h
  • ETH_TX_DESC_CNT : stm32h7xx_hal_conf.h
  • EXTERNAL_CLOCK_VALUE : stm32h7xx_hal_conf.h
  • EXTI_CONFIG : stm32h7xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32h7xx_hal_exti.c
  • EXTI_D3_PENDCLR_SRC_DMACH6 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_DMACH7 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_LPTIM2 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_LPTIM3 : stm32h7xx_hal_exti.h
  • EXTI_D3_PENDCLR_SRC_NONE : stm32h7xx_hal_exti.h
  • EXTI_DIRECT : stm32h7xx_hal_exti.h
  • EXTI_EVENT : stm32h7xx_hal_exti.h
  • EXTI_EVENT_PRESENCE_MASK : stm32h7xx_hal_exti.h
  • EXTI_EVENT_PRESENCE_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_FALLING_EDGE : stm32h7xx_hal.h
  • EXTI_GPIO : stm32h7xx_hal_exti.h
  • EXTI_GPIOA : stm32h7xx_hal_exti.h
  • EXTI_GPIOB : stm32h7xx_hal_exti.h
  • EXTI_GPIOC : stm32h7xx_hal_exti.h
  • EXTI_GPIOD : stm32h7xx_hal_exti.h
  • EXTI_GPIOE : stm32h7xx_hal_exti.h
  • EXTI_GPIOF : stm32h7xx_hal_exti.h
  • EXTI_GPIOG : stm32h7xx_hal_exti.h
  • EXTI_GPIOH : stm32h7xx_hal_exti.h
  • EXTI_GPIOI : stm32h7xx_hal_exti.h
  • EXTI_GPIOJ : stm32h7xx_hal_exti.h
  • EXTI_GPIOK : stm32h7xx_hal_exti.h
  • EXTI_LINE0 : stm32h7xx_hal.h
  • EXTI_LINE1 : stm32h7xx_hal.h
  • EXTI_LINE10 : stm32h7xx_hal.h
  • EXTI_LINE11 : stm32h7xx_hal.h
  • EXTI_LINE12 : stm32h7xx_hal.h
  • EXTI_LINE13 : stm32h7xx_hal.h
  • EXTI_LINE14 : stm32h7xx_hal.h
  • EXTI_LINE15 : stm32h7xx_hal.h
  • EXTI_LINE16 : stm32h7xx_hal.h
  • EXTI_LINE17 : stm32h7xx_hal.h
  • EXTI_LINE18 : stm32h7xx_hal.h
  • EXTI_LINE19 : stm32h7xx_hal.h
  • EXTI_LINE2 : stm32h7xx_hal.h
  • EXTI_LINE20 : stm32h7xx_hal.h
  • EXTI_LINE21 : stm32h7xx_hal.h
  • EXTI_LINE22 : stm32h7xx_hal.h
  • EXTI_LINE23 : stm32h7xx_hal.h
  • EXTI_LINE24 : stm32h7xx_hal.h
  • EXTI_LINE25 : stm32h7xx_hal.h
  • EXTI_LINE26 : stm32h7xx_hal.h
  • EXTI_LINE27 : stm32h7xx_hal.h
  • EXTI_LINE28 : stm32h7xx_hal.h
  • EXTI_LINE29 : stm32h7xx_hal.h
  • EXTI_LINE3 : stm32h7xx_hal.h
  • EXTI_LINE30 : stm32h7xx_hal.h
  • EXTI_LINE31 : stm32h7xx_hal.h
  • EXTI_LINE32 : stm32h7xx_hal.h
  • EXTI_LINE33 : stm32h7xx_hal.h
  • EXTI_LINE34 : stm32h7xx_hal.h
  • EXTI_LINE35 : stm32h7xx_hal.h
  • EXTI_LINE36 : stm32h7xx_hal.h
  • EXTI_LINE37 : stm32h7xx_hal.h
  • EXTI_LINE38 : stm32h7xx_hal.h
  • EXTI_LINE39 : stm32h7xx_hal.h
  • EXTI_LINE4 : stm32h7xx_hal.h
  • EXTI_LINE40 : stm32h7xx_hal.h
  • EXTI_LINE41 : stm32h7xx_hal.h
  • EXTI_LINE42 : stm32h7xx_hal.h
  • EXTI_LINE43 : stm32h7xx_hal.h
  • EXTI_LINE44 : stm32h7xx_hal.h
  • EXTI_LINE47 : stm32h7xx_hal.h
  • EXTI_LINE48 : stm32h7xx_hal.h
  • EXTI_LINE49 : stm32h7xx_hal.h
  • EXTI_LINE5 : stm32h7xx_hal.h
  • EXTI_LINE50 : stm32h7xx_hal.h
  • EXTI_LINE51 : stm32h7xx_hal.h
  • EXTI_LINE52 : stm32h7xx_hal.h
  • EXTI_LINE53 : stm32h7xx_hal.h
  • EXTI_LINE54 : stm32h7xx_hal.h
  • EXTI_LINE55 : stm32h7xx_hal.h
  • EXTI_LINE56 : stm32h7xx_hal.h
  • EXTI_LINE57 : stm32h7xx_hal.h
  • EXTI_LINE58 : stm32h7xx_hal.h
  • EXTI_LINE59 : stm32h7xx_hal.h
  • EXTI_LINE6 : stm32h7xx_hal.h
  • EXTI_LINE60 : stm32h7xx_hal.h
  • EXTI_LINE61 : stm32h7xx_hal.h
  • EXTI_LINE62 : stm32h7xx_hal.h
  • EXTI_LINE63 : stm32h7xx_hal.h
  • EXTI_LINE64 : stm32h7xx_hal.h
  • EXTI_LINE65 : stm32h7xx_hal.h
  • EXTI_LINE66 : stm32h7xx_hal.h
  • EXTI_LINE67 : stm32h7xx_hal.h
  • EXTI_LINE68 : stm32h7xx_hal.h
  • EXTI_LINE69 : stm32h7xx_hal.h
  • EXTI_LINE7 : stm32h7xx_hal.h
  • EXTI_LINE70 : stm32h7xx_hal.h
  • EXTI_LINE71 : stm32h7xx_hal.h
  • EXTI_LINE72 : stm32h7xx_hal.h
  • EXTI_LINE73 : stm32h7xx_hal.h
  • EXTI_LINE74 : stm32h7xx_hal.h
  • EXTI_LINE75 : stm32h7xx_hal.h
  • EXTI_LINE76 : stm32h7xx_hal.h
  • EXTI_LINE8 : stm32h7xx_hal.h
  • EXTI_LINE85 : stm32h7xx_hal.h
  • EXTI_LINE86 : stm32h7xx_hal.h
  • EXTI_LINE87 : stm32h7xx_hal.h
  • EXTI_LINE88 : stm32h7xx_hal.h
  • EXTI_LINE9 : stm32h7xx_hal.h
  • EXTI_LINE_0 : stm32h7xx_hal_exti.h
  • EXTI_LINE_1 : stm32h7xx_hal_exti.h
  • EXTI_LINE_10 : stm32h7xx_hal_exti.h
  • EXTI_LINE_11 : stm32h7xx_hal_exti.h
  • EXTI_LINE_12 : stm32h7xx_hal_exti.h
  • EXTI_LINE_13 : stm32h7xx_hal_exti.h
  • EXTI_LINE_14 : stm32h7xx_hal_exti.h
  • EXTI_LINE_15 : stm32h7xx_hal_exti.h
  • EXTI_LINE_16 : stm32h7xx_hal_exti.h
  • EXTI_LINE_17 : stm32h7xx_hal_exti.h
  • EXTI_LINE_18 : stm32h7xx_hal_exti.h
  • EXTI_LINE_19 : stm32h7xx_hal_exti.h
  • EXTI_LINE_2 : stm32h7xx_hal_exti.h
  • EXTI_LINE_20 : stm32h7xx_hal_exti.h
  • EXTI_LINE_21 : stm32h7xx_hal_exti.h
  • EXTI_LINE_22 : stm32h7xx_hal_exti.h
  • EXTI_LINE_23 : stm32h7xx_hal_exti.h
  • EXTI_LINE_24 : stm32h7xx_hal_exti.h
  • EXTI_LINE_25 : stm32h7xx_hal_exti.h
  • EXTI_LINE_26 : stm32h7xx_hal_exti.h
  • EXTI_LINE_27 : stm32h7xx_hal_exti.h
  • EXTI_LINE_28 : stm32h7xx_hal_exti.h
  • EXTI_LINE_29 : stm32h7xx_hal_exti.h
  • EXTI_LINE_3 : stm32h7xx_hal_exti.h
  • EXTI_LINE_30 : stm32h7xx_hal_exti.h
  • EXTI_LINE_31 : stm32h7xx_hal_exti.h
  • EXTI_LINE_32 : stm32h7xx_hal_exti.h
  • EXTI_LINE_33 : stm32h7xx_hal_exti.h
  • EXTI_LINE_34 : stm32h7xx_hal_exti.h
  • EXTI_LINE_35 : stm32h7xx_hal_exti.h
  • EXTI_LINE_36 : stm32h7xx_hal_exti.h
  • EXTI_LINE_37 : stm32h7xx_hal_exti.h
  • EXTI_LINE_38 : stm32h7xx_hal_exti.h
  • EXTI_LINE_39 : stm32h7xx_hal_exti.h
  • EXTI_LINE_4 : stm32h7xx_hal_exti.h
  • EXTI_LINE_40 : stm32h7xx_hal_exti.h
  • EXTI_LINE_41 : stm32h7xx_hal_exti.h
  • EXTI_LINE_42 : stm32h7xx_hal_exti.h
  • EXTI_LINE_43 : stm32h7xx_hal_exti.h
  • EXTI_LINE_44 : stm32h7xx_hal_exti.h
  • EXTI_LINE_45 : stm32h7xx_hal_exti.h
  • EXTI_LINE_46 : stm32h7xx_hal_exti.h
  • EXTI_LINE_47 : stm32h7xx_hal_exti.h
  • EXTI_LINE_48 : stm32h7xx_hal_exti.h
  • EXTI_LINE_49 : stm32h7xx_hal_exti.h
  • EXTI_LINE_5 : stm32h7xx_hal_exti.h
  • EXTI_LINE_50 : stm32h7xx_hal_exti.h
  • EXTI_LINE_51 : stm32h7xx_hal_exti.h
  • EXTI_LINE_52 : stm32h7xx_hal_exti.h
  • EXTI_LINE_53 : stm32h7xx_hal_exti.h
  • EXTI_LINE_54 : stm32h7xx_hal_exti.h
  • EXTI_LINE_55 : stm32h7xx_hal_exti.h
  • EXTI_LINE_56 : stm32h7xx_hal_exti.h
  • EXTI_LINE_57 : stm32h7xx_hal_exti.h
  • EXTI_LINE_58 : stm32h7xx_hal_exti.h
  • EXTI_LINE_59 : stm32h7xx_hal_exti.h
  • EXTI_LINE_6 : stm32h7xx_hal_exti.h
  • EXTI_LINE_60 : stm32h7xx_hal_exti.h
  • EXTI_LINE_61 : stm32h7xx_hal_exti.h
  • EXTI_LINE_62 : stm32h7xx_hal_exti.h
  • EXTI_LINE_63 : stm32h7xx_hal_exti.h
  • EXTI_LINE_64 : stm32h7xx_hal_exti.h
  • EXTI_LINE_65 : stm32h7xx_hal_exti.h
  • EXTI_LINE_66 : stm32h7xx_hal_exti.h
  • EXTI_LINE_67 : stm32h7xx_hal_exti.h
  • EXTI_LINE_68 : stm32h7xx_hal_exti.h
  • EXTI_LINE_69 : stm32h7xx_hal_exti.h
  • EXTI_LINE_7 : stm32h7xx_hal_exti.h
  • EXTI_LINE_70 : stm32h7xx_hal_exti.h
  • EXTI_LINE_71 : stm32h7xx_hal_exti.h
  • EXTI_LINE_72 : stm32h7xx_hal_exti.h
  • EXTI_LINE_73 : stm32h7xx_hal_exti.h
  • EXTI_LINE_74 : stm32h7xx_hal_exti.h
  • EXTI_LINE_75 : stm32h7xx_hal_exti.h
  • EXTI_LINE_76 : stm32h7xx_hal_exti.h
  • EXTI_LINE_77 : stm32h7xx_hal_exti.h
  • EXTI_LINE_78 : stm32h7xx_hal_exti.h
  • EXTI_LINE_79 : stm32h7xx_hal_exti.h
  • EXTI_LINE_8 : stm32h7xx_hal_exti.h
  • EXTI_LINE_80 : stm32h7xx_hal_exti.h
  • EXTI_LINE_81 : stm32h7xx_hal_exti.h
  • EXTI_LINE_82 : stm32h7xx_hal_exti.h
  • EXTI_LINE_83 : stm32h7xx_hal_exti.h
  • EXTI_LINE_84 : stm32h7xx_hal_exti.h
  • EXTI_LINE_85 : stm32h7xx_hal_exti.h
  • EXTI_LINE_86 : stm32h7xx_hal_exti.h
  • EXTI_LINE_87 : stm32h7xx_hal_exti.h
  • EXTI_LINE_88 : stm32h7xx_hal_exti.h
  • EXTI_LINE_9 : stm32h7xx_hal_exti.h
  • EXTI_LINE_NB : stm32h7xx_hal_exti.h
  • EXTI_MODE : stm32h7xx_hal_gpio.c
  • EXTI_MODE_EVENT : stm32h7xx_hal_exti.h
  • EXTI_MODE_EVT : stm32h7xx_hal.h
  • EXTI_MODE_INTERRUPT : stm32h7xx_hal_exti.h
  • EXTI_MODE_IT : stm32h7xx_hal.h
  • EXTI_MODE_MASK : stm32h7xx_hal_exti.h
  • EXTI_MODE_NONE : stm32h7xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32h7xx_hal_exti.c
  • EXTI_PIN_MASK : stm32h7xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32h7xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_REG1 : stm32h7xx_hal_exti.h
  • EXTI_REG2 : stm32h7xx_hal_exti.h
  • EXTI_REG3 : stm32h7xx_hal_exti.h
  • EXTI_REG_MASK : stm32h7xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_RESERVED : stm32h7xx_hal_exti.h
  • EXTI_RISING_EDGE : stm32h7xx_hal.h
  • EXTI_TARGET_MASK : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_ALL : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_ALL_CPU : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_CPU1 : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_D3SRD : stm32h7xx_hal_exti.h
  • EXTI_TARGET_MSK_NONE : stm32h7xx_hal_exti.h
  • EXTI_TARGET_SHIFT : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32h7xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32h7xx_hal_exti.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
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- f -

  • FALLING_EDGE : stm32h7xx_hal_gpio.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_CLOCK_PERIOD_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_TIME_QUANTA_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_WATCHDOG_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_BASIC_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_CALIBRATION_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_CALIBRATION_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_NOT_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_PRECISION_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_EXT_EVT_SYNC_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXBUFFER : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32h7xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_MESSAGE_RAM_END_ADDRESS : stm32h7xx_hal_fdcan.c
  • FDCAN_MESSAGE_RAM_SIZE : stm32h7xx_hal_fdcan.c
  • FDCAN_MODE_BUS_MONITORING : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32h7xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER32 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER33 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER34 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER35 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER36 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER37 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER38 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER39 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER40 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER41 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER42 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER43 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER44 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER45 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER46 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER47 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER48 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER49 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER50 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER51 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER52 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER53 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER54 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER55 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER56 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER57 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER58 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER59 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER60 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER61 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER62 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER63 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32h7xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_STRICTLY_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32h7xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_BACKUP_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CURRENT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_DISTURBING_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_END_OF_LIST : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FATAL_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_FLAG_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOBAL_TIME_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_IN_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IN_SCHEDULE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_MASTER_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_SYNC_PULSE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_OUT_OF_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_POTENTIAL_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_NO_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_CYC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_DIABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_GLO_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_LOC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_16TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_2ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_32ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_4TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_64TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_8TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_RX_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SCHEDULE_SYNC_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_SEVERE_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_CYCLE_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_DISABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_LOCAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_MATRIX_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNCHRONIZING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_BASE_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_MARK_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_TIME_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_ARBITRATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_MERGED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_SINGLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32h7xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_BOTH : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_ADDR : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BANK : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_16 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_256 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_BURST_SIZE_64 : stm32h7xx_hal_flash_ex.h
  • FLASH_CRC_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_FLAG_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCRDERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCRDERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCRDERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_10 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_11 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_12 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_13 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_14 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_15 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_8 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_9 : stm32h7xx_hal_flash_ex.h
  • FLASH_OPT_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_OTP_BLOCK_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_10 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_11 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_12 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_13 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_14 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_15 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_8 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_9 : stm32h7xx_hal_flash_ex.h
  • FLASH_OTP_BLOCK_ALL : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_PROGRAMMING_DELAY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_SECTOR_0 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_1 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_10 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_100 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_101 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_102 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_103 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_104 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_105 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_106 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_107 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_108 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_109 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_11 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_110 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_111 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_112 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_113 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_114 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_115 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_116 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_117 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_118 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_119 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_12 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_120 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_121 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_122 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_123 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_124 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_125 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_126 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_127 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_13 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_14 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_15 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_16 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_17 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_18 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_19 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_2 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_20 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_21 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_22 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_23 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_24 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_25 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_26 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_27 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_28 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_29 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_3 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_30 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_31 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_32 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_33 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_34 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_35 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_36 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_37 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_38 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_39 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_4 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_40 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_41 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_42 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_43 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_44 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_45 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_46 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_47 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_48 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_49 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_5 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_50 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_51 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_52 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_53 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_54 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_55 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_56 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_57 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_58 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_59 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_6 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_60 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_61 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_62 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_63 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_64 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_65 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_66 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_67 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_68 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_69 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_7 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_70 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_71 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_72 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_73 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_74 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_75 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_76 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_77 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_78 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_79 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_8 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_80 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_81 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_82 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_83 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_84 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_85 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_86 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_87 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_88 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_89 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_9 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_90 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_91 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_92 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_93 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_94 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_95 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_96 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_97 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_98 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_99 : stm32h7xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash.c
  • FLASH_TYPEERASE_MASSERASE : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_FLASHWORD : stm32h7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_OTPWORD : stm32h7xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • FMC_SWAPBMAP_DISABLE : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAM_SRAM : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAMB2 : stm32h7xx_hal.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
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- g -

  • GFXMMU_192BLOCKS : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_256BLOCKS : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_AHB_MASTER_ERROR_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER0_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER1_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER2_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_BUFFER3_OVERFLOW_IT : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_FLUSH : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_FORCE_INVALIDATE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER0 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER1 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER2 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_BUFFER3 : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CACHE_LOCK_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_CR_ITS_MASK : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_ERROR_AHB_MASTER : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER0_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER1_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER2_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_BUFFER3_OVERFLOW : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_INVALID_CALLBACK : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_ERROR_NONE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUT_LINE_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUT_LINE_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_LUTXL_FVB_OFFSET : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_LUTXL_LVB_OFFSET : stm32h7xx_hal_gfxmmu.c
  • GFXMMU_OUTTER_BUFFERABILITY_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_BUFFERABILITY_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_CACHABILITY_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_OUTTER_CACHABILITY_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_PREFETCH_DISABLE : stm32h7xx_hal_gfxmmu.h
  • GFXMMU_PREFETCH_ENABLE : stm32h7xx_hal_gfxmmu.h
  • GPIO_AF0_LCDBIAS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_CRS_SYNC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SWP : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART9 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_USART10 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_PSSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM12 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_OCTOSPIM_P2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_PSSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SDMMC1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_OCTOSPIM_P1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_OCTOSPIM_P2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SDMMC2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32h7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32h7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32h7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32h7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32h7xx_hal_gpio.h
  • GPIO_NOPULL : stm32h7xx_hal_gpio.h
  • GPIO_NUMBER : stm32h7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32h7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_All : stm32h7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32h7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32h7xx_hal_gpio.h
  • GPIO_PULLUP : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- h -

  • HAL_ADC_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32h7xx_hal_adc.h
  • HAL_CEC_ERROR_ARBLST : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32h7xx_hal_cec.h
  • HAL_CEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CEC_STATE_BUSY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32h7xx_hal_cec.h
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32h7xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32h7xx_hal_comp.h
  • HAL_COMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32h7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_FIFO_FLUSH : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DCMI_ERROR_DMA : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_NONE : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DFSDM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA2D_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA_ERROR_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_DME : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32h7xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_COMP2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_SPI6_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQ_GEN_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DSI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DTS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ETH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_EXTI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_APPL_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_CONFIG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_INIT_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE1 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE2 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FLASH_ERROR_CRCRD : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_CRCRD_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_CRCRD_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OB_CHANGE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GFXMMU_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASH_ERROR_DMA : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_INVALID_CALLBACK : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_IT : stm32h7xx_hal_hash.h
  • HAL_HASH_ERROR_NONE : stm32h7xx_hal_hash.h
  • HAL_HASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASHEx_IRQHandler : stm32h7xx_hal_hash.h
  • HAL_HCD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_hcd.h
  • HAL_HCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HRTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HSEM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2S_ERROR_DMA : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NO_OGT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NOT_SUPPORTED : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32h7xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IRDA_ERROR_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32h7xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IRDA_STATE_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32h7xx_hal_irda.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_JPEG_ERROR_DMA : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_HUFF_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_INVALID_CALLBACK : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_NONE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_QUANT_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LTDC_ERROR_FU : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_NONE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDIOS_ERROR_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_DATA : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_INVALID_CALLBACK : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_NONE : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_PARAM : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_ERROR_TIMEOUT : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDMA_CHANNEL_SIZE : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ERROR_ALIGNMENT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BLOCK_SIZE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_LINKED_LIST : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_MASK_DATA : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NO_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NONE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_READ_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_TIMEOUT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_WRITE_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MMC_CARD_DISCONNECTED : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_IDENTIFICATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_SENDING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_STANDBY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CC_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_COM_CRC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DMA : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ILLEGAL_CMD : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_NONE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_RX_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TX_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OPAMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OSPI_ADDRESS_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ADDRESS_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ALTERNATE_BYTES_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_AUTOMATIC_STOP_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_AUTOMATIC_STOP_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CLOCK_MODE_0 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_CLOCK_MODE_3 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DATA_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DELAY_BLOCK_BYPASSED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DELAY_BLOCK_USED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DHQC_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DHQC_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DQS_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DQS_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DUALQUAD_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_DUALQUAD_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_DMA : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_PARAM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_INVALID_SEQUENCE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_TIMEOUT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_ERROR_TRANSFER : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FIXED_LATENCY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_BUSY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_FT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_SM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TC : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLAG_TO : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLASH_ID_1 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FLASH_ID_2 : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FREERUNCLK_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_FREERUNCLK_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_16_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_1_LINE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_24_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_2_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_32_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_4_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_8_BITS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_8_LINES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_DTR_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_DTR_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_INSTRUCTION_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_FT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_SM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TC : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_IT_TO : stm32h7xx_hal_ospi.h
  • HAL_OSPI_LATENCY_ON_WRITE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MATCH_MODE_AND : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MATCH_MODE_OR : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMORY_ADDRESS_SPACE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_APMEMORY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_HYPERBUS : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MACRONIX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MACRONIX_RAM : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MEMTYPE_MICRON : stm32h7xx_hal_ospi.h
  • HAL_OSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OSPI_NO_LATENCY_ON_WRITE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_COMMON_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_READ_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_WRAP_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_OPTYPE_WRITE_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_REGISTER_ADDRESS_SPACE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SAMPLE_SHIFTING_NONE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SIOO_INST_EVERY_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_ABORT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_AUTO_POLLING : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_CMD : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_MEM_MAPPED : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_RX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_BUSY_TX : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_ERROR : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_HYPERBUS_INIT : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_READ_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_READY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_RESET : stm32h7xx_hal_ospi.h
  • HAL_OSPI_STATE_WRITE_CMD_CFG : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_COUNTER_DISABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_COUNTER_ENABLE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_TIMEOUT_DEFAULT_VALUE : stm32h7xx_hal_ospi.h
  • HAL_OSPI_VARIABLE_LATENCY : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_128_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_16_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_32_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_64_BYTES : stm32h7xx_hal_ospi.h
  • HAL_OSPI_WRAP_NOT_SUPPORTED : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_1_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_1_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_2_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_2_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_3_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_3_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_4_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_4_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_5_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_5_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_6_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_6_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_7_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_7_LOW : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_8_HIGH : stm32h7xx_hal_ospi.h
  • HAL_OSPIM_IOPORT_8_LOW : stm32h7xx_hal_ospi.h
  • HAL_OTFDEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_pcd.h
  • HAL_PCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PSSI_16BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_16LINES : stm32h7xx_hal_pssi.h
  • HAL_PSSI_32BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_8BITS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_8LINES : stm32h7xx_hal_pssi.h
  • HAL_PSSI_BIDIRECTIONAL : stm32h7xx_hal_pssi.h
  • HAL_PSSI_CLEAR_FLAG : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_MAP_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_RDY_ALT_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DE_RDY_DISABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DEPOL_ACTIVE_HIGH : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DEPOL_ACTIVE_LOW : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DISABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_DISABLE_IT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ENABLE_IT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_DMA : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_NONE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_NOT_SUPPORTED : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_OVER_RUN : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_TIMEOUT : stm32h7xx_hal_pssi.h
  • HAL_PSSI_ERROR_UNDER_RUN : stm32h7xx_hal_pssi.h
  • HAL_PSSI_FALLING_EDGE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_FLAG : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_IT_SOURCE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_GET_STATUS : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MAP_DE_BIDIR_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MAP_RDY_BIDIR_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PSSI_RDY_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDY_MAP_ENABLE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDYPOL_ACTIVE_HIGH : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RDYPOL_ACTIVE_LOW : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RESET_HANDLE_STATE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_RISING_EDGE : stm32h7xx_hal_pssi.h
  • HAL_PSSI_UNIDIRECTIONAL : stm32h7xx_hal_pssi.h
  • HAL_PWR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_QSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RAMECC_ERROR_BUSY : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_INVALID_CALLBACK : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_NONE : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_ERROR_TIMEOUT : stm32h7xx_hal_ramecc.h
  • HAL_RAMECC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RNG_ERROR_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32h7xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RNG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32h7xx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SD_CARD_DISCONNECTED : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_IDENTIFICATION : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_READY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_SENDING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_STANDBY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CC_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_COM_CRC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DMA : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ILLEGAL_CMD : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_NONE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_RX_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TX_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_sd.h
  • HAL_SD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SDRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMARTCARD_STATE_BUSY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32h7xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_ACKF : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SPDIFRX_ERROR_DMA : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_INVALID_CALLBACK : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPI_ERROR_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NOT_SUPPORTED : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_TIMEOUT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UDR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32h7xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SWPMI_ERROR_CRC : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_INVALID_CALLBACK : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_TXBEF_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DCMI_STOP : stm32h7xx_hal_dcmi.c
  • HAL_TIMEOUT_DIR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DMA_ABORT : stm32h7xx_hal_dma.c
  • HAL_TIMEOUT_MDMA_ABORT : stm32h7xx_hal_mdma.c
  • HAL_TIMEOUT_RXNE : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32h7xx_hal_smbus.c
  • HAL_UART_ERROR_DMA : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32h7xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_UART_STATE_BUSY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32h7xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32h7xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HASH_ALGOMODE_HASH : stm32h7xx_hal_hash.h
  • HASH_ALGOMODE_HMAC : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_MD5 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA1 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA224 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA256 : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_16B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_1B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_32B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_8B : stm32h7xx_hal_hash.h
  • HASH_DIGEST_CALCULATION_NOT_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_CALCULATION_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_LENGTH : stm32h7xx_hal_hash.h
  • HASH_DMA_SUSPENSION_WORDS_LIMIT : stm32h7xx_hal_hash.c
  • HASH_FLAG_BUSY : stm32h7xx_hal_hash.h
  • HASH_FLAG_DCIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINNE : stm32h7xx_hal_hash.h
  • HASH_FLAG_DMAS : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_LONGKEY : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_SHORTKEY : stm32h7xx_hal_hash.h
  • HASH_IT_DCI : stm32h7xx_hal_hash.h
  • HASH_IT_DINI : stm32h7xx_hal_hash.h
  • HASH_NBW_PUSHED : stm32h7xx_hal_hash.h
  • HASH_NUMBER_OF_CSR_REGISTERS : stm32h7xx_hal_hash.c
  • HASH_TIMEOUTVALUE : stm32h7xx_hal_hash.c
  • HCD_PHY_EMBEDDED : stm32h7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32h7xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32h7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32h7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32h7xx_hal_hcd.h
  • HSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSE_VALUE : stm32h7xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI48_VALUE : stm32h7xx_ll_rcc.h
  • HSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_VALUE : stm32h7xx_hal_conf.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32h7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32h7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32h7xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32h7xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32h7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32h7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32h7xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32h7xx_hal_i2c.h
  • I2C_GET_DIR : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32h7xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32h7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32h7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32h7xx_hal_i2c.h
  • I2C_IT_RXI : stm32h7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32h7xx_hal_i2c.h
  • I2C_IT_TCI : stm32h7xx_hal_i2c.h
  • I2C_IT_TXI : stm32h7xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32h7xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32h7xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32h7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32h7xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32h7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32h7xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32h7xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MSK : stm32h7xx_hal_i2c.c
  • I2C_STATE_NONE : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32h7xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32h7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32h7xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32h7xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32h7xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32h7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_LEFT : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_RIGHT : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_LSB : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_MSB : stm32h7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32h7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXP : stm32h7xx_hal_i2s.h
  • I2S_FLAG_TXP : stm32h7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32h7xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32h7xx_ll_spi.c
  • I2S_IT_ERR : stm32h7xx_hal_i2s.h
  • I2S_IT_FRE : stm32h7xx_hal_i2s.h
  • I2S_IT_OVR : stm32h7xx_hal_i2s.h
  • I2S_IT_RXP : stm32h7xx_hal_i2s.h
  • I2S_IT_TXP : stm32h7xx_hal_i2s.h
  • I2S_IT_UDR : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_FULLDUPLEX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_FULLDUPLEX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32h7xx_hal_i2s.h
  • I2S_TIMEOUT : stm32h7xx_hal_i2s.c
  • I2S_WS_INVERSION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_WS_INVERSION_ENABLE : stm32h7xx_hal_i2s.h
  • IDCODE_DEVID_MASK : stm32h7xx_hal.c
  • IRDA_AUTOBAUD_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32h7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32h7xx_hal_irda.c
  • IRDA_CR_MASK : stm32h7xx_hal_irda.h
  • IRDA_CR_POS : stm32h7xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32h7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32h7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32h7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32h7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32h7xx_hal_irda_ex.h
  • IRDA_ISR_MASK : stm32h7xx_hal_irda.h
  • IRDA_ISR_POS : stm32h7xx_hal_irda.h
  • IRDA_IT_ERR : stm32h7xx_hal_irda.h
  • IRDA_IT_FE : stm32h7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32h7xx_hal_irda.h
  • IRDA_IT_MASK : stm32h7xx_hal_irda.h
  • IRDA_IT_NE : stm32h7xx_hal_irda.h
  • IRDA_IT_ORE : stm32h7xx_hal_irda.h
  • IRDA_IT_PE : stm32h7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32h7xx_hal_irda.h
  • IRDA_IT_TC : stm32h7xx_hal_irda.h
  • IRDA_IT_TXE : stm32h7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32h7xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_RX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32h7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32h7xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32h7xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32h7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32h7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32h7xx_hal_irda_ex.h
  • IS_ADC1_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC2_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC3_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32h7xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CONVERSIONDATAMGT : stm32h7xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_DUAL_DATA_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32h7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32h7xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32h7xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32h7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32h7xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_BITS : stm32h7xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32h7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32h7xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_BDMA_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_BDMA_REQUEST : stm32h7xx_hal_dma.h
  • IS_BOOT_ADDRESS : stm32h7xx_hal_flash.h
  • IS_CEC_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32h7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32h7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32h7xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32h7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32h7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32h7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32h7xx_hal_spdifrx.h
  • IS_COMP_BLANKINGSRCE : stm32h7xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32h7xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32h7xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32h7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32h7xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32h7xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32h7xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32h7xx_hal_cryp.h
  • IS_D3_STATE : stm32h7xx_hal_pwr_ex.h
  • IS_DAC_ALIGN : stm32h7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32h7xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32h7xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32h7xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32h7xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32h7xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32h7xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_BYTE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32h7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_MODE_JPEG : stm32h7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32h7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32h7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32h7xx_hal_crc.h
  • IS_DFSDM1_CHANNEL_INSTANCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM1_FILTER_INSTANCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_BREAK_SIGNALS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SKIPPING_VALUE : stm32h7xx_hal_dfsdm_ex.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DMA_BUFFER_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32h7xx_hal_dma.h
  • IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_DMA_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_DMA_FIFO_MODE_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_MODE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32h7xx_hal_dma.h
  • IS_DMA_REQUEST : stm32h7xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32h7xx_hal_dma_ex.h
  • IS_EXTI_ALL_LINE : stm32h7xx_hal.h
  • IS_EXTI_CONFIG_LINE : stm32h7xx_hal_exti.h
  • IS_EXTI_D1_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_CLEAR : stm32h7xx_hal.h
  • IS_EXTI_D3_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_PENDCLR_SRC : stm32h7xx_hal_exti.h
  • IS_EXTI_EDGE_LINE : stm32h7xx_hal.h
  • IS_EXTI_GPIO_PIN : stm32h7xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32h7xx_hal_exti.h
  • IS_EXTI_LINE : stm32h7xx_hal_exti.h
  • IS_EXTI_MODE : stm32h7xx_hal_exti.h
  • IS_EXTI_MODE_LINE : stm32h7xx_hal.h
  • IS_EXTI_PENDING_EDGE : stm32h7xx_hal_exti.h
  • IS_EXTI_PROPERTY : stm32h7xx_hal_exti.h
  • IS_EXTI_TARGET : stm32h7xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32h7xx_hal_exti.h
  • IS_FDCAN_BRS : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_COUNTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_FIELD_LENGTH : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CLOCK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SIZE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_OPERATION_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_AUTO_CLK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_BASIC_CYCLES_NUMBER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_CYCLE_START_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EXTERNAL_CLK_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_GLOBAL_TIME_FILTERING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REPEAT_FACTOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_PRESET : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_EXTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_INTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TRIGGER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_DENOMINATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_0_2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_NUMERATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TX_ENABLE_WINDOW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32h7xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32h7xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_OTP : stm32h7xx_hal_flash.h
  • IS_FLASH_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPECRC : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32h7xx_hal_flash.h
  • IS_FMC_SWAPBMAP_MODE : stm32h7xx_hal.h
  • IS_GFXMMU_BLOCKS_PER_LINE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_BUFFER_ADDRESS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_FORCE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_FORCE_ACTION : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_LOCK : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_CACHE_LOCK_BUFFER : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_INTERRUPTS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_BLOCK : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE_OFFSET : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINE_STATUS : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_LUT_LINES_NUMBER : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_OUTTER_BUFFERABILITY : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_OUTTER_CACHABILITY : stm32h7xx_hal_gfxmmu.h
  • IS_GFXMMU_PREFETCH : stm32h7xx_hal_gfxmmu.h
  • IS_GPIO_AF : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32h7xx_hal_gpio.h
  • IS_GPIO_PULL : stm32h7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32h7xx_hal_gpio.h
  • IS_HAL_EXTI_CONFIG_LINE : stm32h7xx_hal.h
  • IS_HASH_DATATYPE : stm32h7xx_hal_hash.h
  • IS_HASH_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_POLLING_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HMAC_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HMAC_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HSEM_COREID : stm32h7xx_hal_hsem.h
  • IS_HSEM_KEY : stm32h7xx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32h7xx_hal_hsem.h
  • IS_HSEM_SEMID : stm32h7xx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32h7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32h7xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32h7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32h7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32h7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_24BIT_ALIGNMENT : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32h7xx_hal_i2s.h
  • IS_I2S_FIRST_BIT : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER_KEEP_IO_STATE : stm32h7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32h7xx_hal_i2s.h
  • IS_I2S_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_SLAVE : stm32h7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32h7xx_hal_i2s.h
  • IS_I2S_WS_INVERSION : stm32h7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32h7xx_hal_irda.h
  • IS_IRDA_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32h7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32h7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32h7xx_hal_irda.h
  • IS_IRDA_STATE : stm32h7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32h7xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32h7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32h7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32h7xx_hal_iwdg.h
  • IS_JPEG_CHROMASUBSAMPLING : stm32h7xx_hal_jpeg.h
  • IS_JPEG_COLORSPACE : stm32h7xx_hal_jpeg.h
  • IS_JPEG_IMAGE_QUALITY : stm32h7xx_hal_jpeg.h
  • IS_JPEG_PAUSE_RESUME_STATE : stm32h7xx_hal_jpeg.h
  • IS_LL_ADC_COMMON_CLOCK : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_LEFT_BIT_SHIFT : stm32h7xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_DATA_TRANSFER_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32h7xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32h7xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32h7xx_ll_adc.c
  • IS_LL_BDMA_ALL_CHANNEL_INSTANCE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_DIRECTION : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MEMORYDATASIZE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MEMORYINCMODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_MODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_NBDATA : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHDATASIZE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHINCMODE : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PERIPHREQUEST : stm32h7xx_ll_bdma.c
  • IS_LL_BDMA_PRIORITY : stm32h7xx_ll_bdma.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32h7xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32h7xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32h7xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32h7xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32h7xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32h7xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32h7xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32h7xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32h7xx_ll_dac.c
  • IS_LL_DMA2D_ALPHA : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_ALPHAINV : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_ALPHAMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_BLUE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CHROMA_SUB_SAMPLING : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CLUTCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_CLUTSIZE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_GREEN : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_LCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_LINE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OCMODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OFFSET : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_OFFSET_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_PIXEL : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_RBSWAP : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_RED : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA2D_SWAP_MODE : stm32h7xx_ll_dma2d.c
  • IS_LL_DMA_ALL_STREAM_INSTANCE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32h7xx_ll_dma.c
  • IS_LL_DMA_FIFO_MODE_STATE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_FIFO_THRESHOLD : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORY_BURST : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHERAL_BURST : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32h7xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32h7xx_ll_dma.c
  • IS_LL_DMA_REQUEST : stm32h7xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_LINE_64_95 : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32h7xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32h7xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32h7xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32h7xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32h7xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32h7xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32h7xx_ll_spi.c
  • IS_LL_I2S_BIT_ORDER : stm32h7xx_ll_spi.c
  • IS_LL_I2S_CHANNEL_LENGTH_TYPE : stm32h7xx_ll_spi.c
  • IS_LL_I2S_CKPOL : stm32h7xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32h7xx_ll_spi.c
  • IS_LL_I2S_FIFO_TH : stm32h7xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32h7xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32h7xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32h7xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32h7xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32h7xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32h7xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32h7xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32h7xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32h7xx_ll_lpuart.c
  • IS_LL_MDMA_ALL_CHANNEL_INSTANCE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLK_DATALENGTH : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLK_REPEATCOUNT : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BUFFER_XFERLENGTH : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BUFFWRITEMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_BYTEENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DEST_BUS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTBURST : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTDATASIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTINCMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_DESTINCSIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_HALFWORDENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_HWTRIGGER : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PACKMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PADDINGALIGNEMENT : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_PRIORITY : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_REQUESTMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRC_BUS : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCDATASIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCINCMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCINCSIZE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_SRCTBURST : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_TRIGGERMODE : stm32h7xx_ll_mdma.c
  • IS_LL_MDMA_WORDENDIANESS : stm32h7xx_ll_mdma.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32h7xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32h7xx_ll_opamp.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_SPI_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32h7xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CLOCK_DIVIDER : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG1 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG2 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_CONFIG3 : stm32h7xx_ll_rng.c
  • IS_LL_RNG_NIST_COMPLIANCE : stm32h7xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32h7xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32h7xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATEPRESCALER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRC : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32h7xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32h7xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32h7xx_ll_spi.c
  • IS_LL_SPI_FIFO_TH : stm32h7xx_ll_spi.c
  • IS_LL_SPI_ID_IDLENESS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32h7xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32h7xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32h7xx_ll_spi.c
  • IS_LL_SPI_PROTOCOL : stm32h7xx_ll_spi.c
  • IS_LL_SPI_RX_FIFO : stm32h7xx_ll_spi.c
  • IS_LL_SPI_RXCRCINIT_PATTERN : stm32h7xx_ll_spi.c
  • IS_LL_SPI_SS_IDLENESS : stm32h7xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32h7xx_ll_spi.c
  • IS_LL_SPI_TXCRCINIT_PATTERN : stm32h7xx_ll_spi.c
  • IS_LL_SPI_UDR_CONFIG_REGISTER : stm32h7xx_ll_spi.c
  • IS_LL_SPI_UDR_DETECT_BEGIN_DATA : stm32h7xx_ll_spi.c
  • IS_LL_SWPMI_BITRATE_VALUE : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_RX : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_TX : stm32h7xx_ll_swpmi.c
  • IS_LL_SWPMI_VOLTAGE_CLASS : stm32h7xx_ll_swpmi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32h7xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32h7xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32h7xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32h7xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32h7xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32h7xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32h7xx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32h7xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32h7xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32h7xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32h7xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32h7xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32h7xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32h7xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32h7xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32h7xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32h7xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32h7xx_ll_usart.c
  • IS_LL_UTILS_AHB_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB1_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB3_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_APB4_DIV : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_CHECK_VCO_RANGES : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_FRACN_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLP_VALUE : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32h7xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32h7xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32h7xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_LTDC_AAH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AAW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AHBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AVBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR1 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR2 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLUEVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLNBR : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_DEPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_GREENVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSYNC : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LIPOS : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PCPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PIXEL_FORMAT : stm32h7xx_hal_ltdc.h
  • IS_LTDC_REDVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_RELOAD : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSYNC : stm32h7xx_hal_ltdc.h
  • IS_MDIOS_PORTADDRESS : stm32h7xx_hal_mdios.h
  • IS_MDIOS_PREAMBLECHECK : stm32h7xx_hal_mdios.h
  • IS_MDIOS_REGISTER : stm32h7xx_hal_mdios.h
  • IS_MDMA_BLOCK_ADDR_OFFSET : stm32h7xx_hal_mdma.h
  • IS_MDMA_BLOCK_COUNT : stm32h7xx_hal_mdma.h
  • IS_MDMA_BUFFER_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_DATA_ALIGNMENT : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_ENDIANNESS_MODE : stm32h7xx_hal_mdma.h
  • IS_MDMA_LEVEL_COMPLETE : stm32h7xx_hal_mdma.h
  • IS_MDMA_PRIORITY : stm32h7xx_hal_mdma.h
  • IS_MDMA_REQUEST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_TRIGGER_MODE : stm32h7xx_hal_mdma.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32h7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32h7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32h7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32h7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_OB_BOOT_ADD_OPTION : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOOT_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG1_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_PCROP_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_SECURE_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_TYPE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_VDDMMC_HSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OPAMP_FACTORYTRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32h7xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32h7xx_hal_flash_ex.h
  • IS_OTP_BLOCK : stm32h7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PREAMBLE_TYPE_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PSSI_BUSWIDTH : stm32h7xx_hal_pssi.h
  • IS_PSSI_CLOCK_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PSSI_CONTROL_SIGNAL : stm32h7xx_hal_pssi.h
  • IS_PSSI_DE_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PSSI_RDY_POLARITY : stm32h7xx_hal_pssi.h
  • IS_PWR_AVD_LEVEL : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_AVD_MODE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_D1_CPU : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32h7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_MODE_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_FLAG : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_PULL : stm32h7xx_hal_pwr_ex.h
  • IS_RAMECC_GLOBAL_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RAMECC_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RAMECC_MONITOR_INTERRUPT : stm32h7xx_hal_ramecc.h
  • IS_RCC_ADCCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CDPCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLKPSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CSI : stm32h7xx_hal_rcc.h
  • IS_RCC_CSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_D1PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_D3PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_DFSDM2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FLAG : stm32h7xx_hal_rcc.h
  • IS_RCC_FMCCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_HSE : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32h7xx_hal_rcc.h
  • IS_RCC_HSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_I2C123CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM345CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32h7xx_hal_rcc.h
  • IS_RCC_LSI : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32h7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_OSPICLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK2 : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL2CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2RGE_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2VCO_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3RGE_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3VCO_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLCLOCKOUT_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLFRACN_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2ACLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2BCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SCOPE_WWDG : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPDIFRXCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI123CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI45CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI6CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SRDPCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_KERWAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART9CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART10CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART16910CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART16CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART234578CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32h7xx_hal_rng.h
  • IS_RNG_CLOCK_DIVIDER : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG1 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG2 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_CONFIG3 : stm32h7xx_hal_rng_ex.h
  • IS_RNG_FLAG : stm32h7xx_hal_rng.h
  • IS_RNG_IT : stm32h7xx_hal_rng.h
  • IS_RNG_NIST_COMPLIANCE : stm32h7xx_hal_rng_ex.h
  • IS_RTC_ALARM : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32h7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_BKP : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32h7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32h7xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32h7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32h7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32h7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER_CONFIG_CORRECT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32h7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32h7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32h7xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32h7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32h7xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32h7xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SPDIFRX_CHANNEL : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32h7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32h7xx_hal_spi.h
  • IS_SPI_CPHA : stm32h7xx_hal_spi.h
  • IS_SPI_CPOL : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_INITIALIZATION_PATTERN : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32h7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_FIFOTHRESHOLD : stm32h7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32h7xx_hal_spi.h
  • IS_SPI_MODE : stm32h7xx_hal_spi.h
  • IS_SPI_NSS : stm32h7xx_hal_spi.h
  • IS_SPI_NSSP : stm32h7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_BEHAVIOUR : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_DETECTION : stm32h7xx_hal_spi.h
  • IS_STEREO_MODE : stm32h7xx_hal_spdifrx.h
  • IS_SWPMI_BITRATE_VALUE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32h7xx_hal_swpmi.h
  • IS_SYMBOL_CLOCK_GEN : stm32h7xx_hal_spdifrx.h
  • IS_SYSCFG_ANALOG_SWITCH : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_ADDRESS : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_REGISTER : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_SELECT : stm32h7xx_hal.h
  • IS_SYSCFG_ETHERNET_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32h7xx_hal.h
  • IS_SYSCFG_SWITCH_STATE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32h7xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32h7xx_hal_cortex.h
  • IS_TICKFREQ : stm32h7xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32h7xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32h7xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32h7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32h7xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TISEL : stm32h7xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32h7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32h7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32h7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32h7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32h7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32h7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32h7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32h7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32h7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32h7xx_hal_uart.h
  • IS_UART_LIN : stm32h7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32h7xx_hal_uart.h
  • IS_UART_MODE : stm32h7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32h7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32h7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32h7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32h7xx_hal_uart.h
  • IS_UART_PARITY : stm32h7xx_hal_uart.h
  • IS_UART_PRESCALER : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32h7xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32h7xx_hal_uart_ex.h
  • IS_UART_STATE : stm32h7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32h7xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32h7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32h7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32h7xx_hal_usart.h
  • IS_USART_CLOCK : stm32h7xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32h7xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32h7xx_hal_usart.h
  • IS_USART_MODE : stm32h7xx_hal_usart.h
  • IS_USART_NSS : stm32h7xx_hal_usart_ex.h
  • IS_USART_OVERSAMPLING : stm32h7xx_hal_usart.h
  • IS_USART_PARITY : stm32h7xx_hal_usart.h
  • IS_USART_PHASE : stm32h7xx_hal_usart.h
  • IS_USART_POLARITY : stm32h7xx_hal_usart.h
  • IS_USART_PRESCALER : stm32h7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32h7xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32h7xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32h7xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32h7xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32h7xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32h7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32h7xx_hal_spdifrx.h
  • IS_WRPSTATE : stm32h7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32h7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32h7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32h7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32h7xx_hal_iwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- j -

  • JPEG_420_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_422_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_444_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_AC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_CMYK_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_CONTEXT_CONF_ENCODING : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_CUSTOM_TABLES : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DECODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENCODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENDING_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_IT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_METHOD_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_OPERATION_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_INPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_OUTPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_POLLING : stm32h7xx_hal_jpeg.c
  • JPEG_DC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_TH_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FLAG_ALL : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_COF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_EOCF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_HPDF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFNFF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFTF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFNEF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFTF : stm32h7xx_hal_jpeg.h
  • JPEG_GRAYSCALE_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MAX : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MIN : stm32h7xx_hal_jpeg.h
  • JPEG_INTERRUPT_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_IT_EOC : stm32h7xx_hal_jpeg.h
  • JPEG_IT_HPD : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFNF : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFT : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFNE : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PROCESS_DONE : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_ONGOING : stm32h7xx_hal_jpeg.c
  • JPEG_QUANT_TABLE_SIZE : stm32h7xx_hal_jpeg.h
  • JPEG_TIMEOUT_VALUE : stm32h7xx_hal_jpeg.c
  • JPEG_YCBCR_COLORSPACE : stm32h7xx_hal_jpeg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
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- l -

  • LL_ADC_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD1_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD2_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_AWD3_TR : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_19_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32h7xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_12MHZ5 : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_20MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_25MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_50MHZ : stm32h7xx_ll_adc.h
  • LL_ADC_BOOST_MODE_6MHZ25 : stm32h7xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD1 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD2 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD3 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD4 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD5 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_LINEARITY_WORD6 : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_OFFSET : stm32h7xx_ll_adc.h
  • LL_ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_19 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC2CH1_ADC2 : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32h7xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32h7xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32h7xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32h7xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32h7xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32h7xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32h7xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32h7xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32h7xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32h7xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_1 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_10 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_11 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_12 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_13 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_14 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_15 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_2 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_3 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_4 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_5 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_6 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_7 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_8 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_9 : stm32h7xx_ll_adc.h
  • LL_ADC_LEFT_BIT_SHIFT_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32h7xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_RES_32_10B : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_RES_8B : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_RSHIFT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_RSHIFT_ENABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_10 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_11 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32h7xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_9 : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32h7xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32h7xx_ll_adc.h
  • LL_ADC_ReadReg : stm32h7xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DFSDM_TRANSFER : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_DR_TRANSFER : stm32h7xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32h7xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32h7xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_14B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_16B : stm32h7xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_16CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_32CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_387CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_64CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_810CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_8CYCLES_5 : stm32h7xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32h7xx_ll_adc.h
  • LL_ADC_WriteReg : stm32h7xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ADC12 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_USB1OTGHS : stm32h7xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AHBSRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AHBSRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_BDMA1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_CRYP : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_D2SRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_D2SRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DCMI : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_HASH : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_HSEM : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32h7xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SDMMC2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AXISRAM3 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DMA2D : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DTCM1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_DTCM2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FLASH : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FMC : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_GFXMMU : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ITCM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_JPGDEC : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_MDMA : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OCTOSPIM : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OSPI1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OSPI2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OTFDEC1 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_OTFDEC2 : stm32h7xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_SDMMC1 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BDMA : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BDMA2 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_BKPRAM : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_D3SRAM1 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOA : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOB : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOC : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOD : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOE : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOF : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOG : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOH : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOI : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOJ : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_GPIOK : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_SRAM4 : stm32h7xx_ll_bus.h
  • LL_AHB4_GRP1_PERIPH_SRDSRAM : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC12 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPDIFRX : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM12 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM13 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM14 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART5 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART7 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART8 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_CRS : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_FDCAN : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_MDIOS : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_OPAMP : stm32h7xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_SWPMI1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_DFSDM1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI2 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI4 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI5 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_UART9 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART10 : stm32h7xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART6 : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_LTDC : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_WWDG : stm32h7xx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_WWDG1 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_COMP12 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DAC2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DFSDM2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_DTS : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_I2C4 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPTIM2 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPTIM3 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_LPUART1 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_RTCAPB : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_SPI6 : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_SYSCFG : stm32h7xx_ll_bus.h
  • LL_APB4_GRP1_PERIPH_VREF : stm32h7xx_ll_bus.h
  • LL_BDMA_CCR_HTIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CCR_TCIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CCR_TEIE : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CHANNEL_ALL : stm32h7xx_ll_bdma.h
  • LL_BDMA_CURRENTTARGETMEM0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_CURRENTTARGETMEM1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_DIRECTION_MEMORY_TO_MEMORY : stm32h7xx_ll_bdma.h
  • LL_BDMA_DIRECTION_MEMORY_TO_PERIPH : stm32h7xx_ll_bdma.h
  • LL_BDMA_DIRECTION_PERIPH_TO_MEMORY : stm32h7xx_ll_bdma.h
  • LL_BDMA_DOUBLEBUFFER_MODE_DISABLE : stm32h7xx_ll_bdma.h
  • LL_BDMA_DOUBLEBUFFER_MODE_ENABLE : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CGIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CHTIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTCIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_IFCR_CTEIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_GIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_HTIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TCIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF0 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF1 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF2 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF3 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF4 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF5 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF6 : stm32h7xx_ll_bdma.h
  • LL_BDMA_ISR_TEIF7 : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_BYTE : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_HALFWORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_MDATAALIGN_WORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_MEMORY_INCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_MEMORY_NOINCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_MODE_CIRCULAR : stm32h7xx_ll_bdma.h
  • LL_BDMA_MODE_NORMAL : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_BYTE : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_HALFWORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_PDATAALIGN_WORD : stm32h7xx_ll_bdma.h
  • LL_BDMA_PERIPH_INCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_PERIPH_NOINCREMENT : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_HIGH : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_LOW : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_MEDIUM : stm32h7xx_ll_bdma.h
  • LL_BDMA_PRIORITY_VERYHIGH : stm32h7xx_ll_bdma.h
  • LL_BDMA_ReadReg : stm32h7xx_ll_bdma.h
  • LL_BDMA_WriteReg : stm32h7xx_ll_bdma.h
  • LL_CKGA_PERIPH_AHB : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AHB12 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AHB34 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXI : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM1 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM2 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_AXIRAM3 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_CPU : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_DMA2D : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_ECCRAM : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_EXTI : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_FLIFT : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_FMC : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_GFXMMUM : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_GFXMMUS : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_JTAG : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_LTDC : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_MDMA : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_OCTOSPI1 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_OCTOSPI2 : stm32h7xx_ll_bus.h
  • LL_CKGA_PERIPH_SDMMC : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BDMA : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BDMA2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_BKPRAM : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_COMP12 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DAC2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DFSDM2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_DTS : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_GPIO : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_I2C4 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPTIM2 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPTIM3 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_LPUART1 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_RTC : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SPI6 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SRAM4 : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_SRDSRAM : stm32h7xx_ll_bus.h
  • LL_CLKAM_PERIPH_VREF : stm32h7xx_ll_bus.h
  • LL_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_CONFIG : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_MASK : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_REG : stm32h7xx_ll_rcc.h
  • LL_CLKSOURCE_SHIFT : stm32h7xx_ll_rcc.h
  • LL_COMP_AF_PA6 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PA8 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PB12 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PE15 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PE6 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG2 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG3 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PG4 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PI1 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PI4 : stm32h7xx_ll_comp.h
  • LL_COMP_AF_PK2 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_NONE : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_ll_comp.h
  • LL_COMP_DELAY_STARTUP_US : stm32h7xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32h7xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VBAT_VDDAP : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_DAC2_CH1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32h7xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32h7xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_ll_comp.h
  • LL_COMP_ReadReg : stm32h7xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32h7xx_ll_comp.h
  • LL_COMP_WriteReg : stm32h7xx_ll_comp.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32h7xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32h7xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32h7xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32h7xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32h7xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32h7xx_ll_crc.h
  • LL_CRC_ReadReg : stm32h7xx_ll_crc.h
  • LL_CRC_WriteReg : stm32h7xx_ll_crc.h
  • LL_CRS_CR_ERRIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32h7xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32h7xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32h7xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32h7xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32h7xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32h7xx_ll_crs.h
  • LL_CRS_ReadReg : stm32h7xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32h7xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32h7xx_ll_crs.h
  • LL_CRS_WriteReg : stm32h7xx_ll_crs.h
  • LL_DAC_CHANNEL_1 : stm32h7xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32h7xx_ll_dac.h
  • LL_DAC_CONNECT_GPIO : stm32h7xx_ll_dac.h
  • LL_DAC_CONNECT_INTERNAL : stm32h7xx_ll_dac.h
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32h7xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32h7xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32h7xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32h7xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32h7xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32h7xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32h7xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32h7xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32h7xx_ll_dac.h
  • LL_DAC_ReadReg : stm32h7xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32h7xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM1_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM2_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM3_OUT : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_EXT_IT9 : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_SOFTWARE : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM2_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM4_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM6_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM7_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM8_TRGO : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NOISE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NONE : stm32h7xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_TRIANGLE : stm32h7xx_ll_dac.h
  • LL_DAC_WriteReg : stm32h7xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FDCAN_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_HRTIM_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB3_GRP1_WWDG1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_I2C4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_IWDG1_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM2_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM3_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM4_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_LPTIM5_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_APB4_GRP1_RTC_STOP : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRGIO_INPUT_DIRECTION : stm32h7xx_ll_system.h
  • LL_DBGMCU_TRGIO_OUTPUT_DIRECTION : stm32h7xx_ll_system.h
  • LL_DMA2D_ALPHA_INVERTED : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_COMBINE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_NO_MODIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_MODE_REPLACE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ALPHA_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUT_COLOR_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CLUTSIZE_MAX : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_COLOR : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_CSS_420 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CSS_422 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_CSS_444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CAEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_CTCIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TCIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TEIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_FLAG_TWIF : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_A4 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_A8 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_AL44 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_AL88 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB1555 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB4444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_L4 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_L8 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_RGB565 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_INPUT_MODE_YCBCR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CAEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_CTCIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TCIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TEIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_IT_TWIE : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_LINE_OFFSET_BYTES : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_LINE_OFFSET_PIXELS : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_M2M_PFC : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_MODE_R2M : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_NUMBEROFLINES : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_NUMBEROFPIXELS : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_OFFSET_MAX : stm32h7xx_ll_dma2d.c
  • LL_DMA2D_OUTPUT_MODE_ARGB1555 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_ARGB4444 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_ARGB8888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_RGB565 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_OUTPUT_MODE_RGB888 : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_RB_MODE_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_RB_MODE_SWAP : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_ReadReg : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SWAP_MODE_REGULAR : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_SWAP_MODE_TWO_BY_TWO : stm32h7xx_ll_dma2d.h
  • LL_DMA2D_WriteReg : stm32h7xx_ll_dma2d.h
  • LL_DMA_CURRENTTARGETMEM0 : stm32h7xx_ll_dma.h
  • LL_DMA_CURRENTTARGETMEM1 : stm32h7xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32h7xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32h7xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32h7xx_ll_dma.h
  • LL_DMA_DOUBLEBUFFER_MODE_DISABLE : stm32h7xx_ll_dma.h
  • LL_DMA_DOUBLEBUFFER_MODE_ENABLE : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOMODE_DISABLE : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOMODE_ENABLE : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_0_25 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_25_50 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_50_75 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_75_100 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_EMPTY : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOSTATUS_FULL : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_dma.h
  • LL_DMA_FIFOTHRESHOLD_FULL : stm32h7xx_ll_dma.h
  • LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC16 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC4 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_INC8 : stm32h7xx_ll_dma.h
  • LL_DMA_MBURST_SINGLE : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32h7xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32h7xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32h7xx_ll_dma.h
  • LL_DMA_MODE_PFCTRL : stm32h7xx_ll_dma.h
  • LL_DMA_OFFSETSIZE_FIXEDTO4 : stm32h7xx_ll_dma.h
  • LL_DMA_OFFSETSIZE_PSIZE : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC16 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC4 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_INC8 : stm32h7xx_ll_dma.h
  • LL_DMA_PBURST_SINGLE : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32h7xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32h7xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32h7xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32h7xx_ll_dma.h
  • LL_DMA_ReadReg : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_0 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_1 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_2 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_3 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_4 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_5 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_6 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_7 : stm32h7xx_ll_dma.h
  • LL_DMA_STREAM_ALL : stm32h7xx_ll_dma.h
  • LL_DMA_WriteReg : stm32h7xx_ll_dma.h
  • LL_DMAMUX1_REQ_ADC1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_ADC2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_CRYP_IN : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_CRYP_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DAC1_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DAC1_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DCMI : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DCMI_PSSI : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_DFSDM1_FLT3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GEN_TIM12_TRGO : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_GENERATOR7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_HASH_IN : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_I2C3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_MEM2MEM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI1_A : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI1_B : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI2_A : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SAI2_B : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPDIF_RX_CS : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPDIF_RX_DT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI5_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SPI5_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SWPMI_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_SWPMI_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM15_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM16_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM16_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM17_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM17_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM1_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM2_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM3_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM4_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM5_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM6_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM7_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_CH4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_COM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_TRIG : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_TIM8_UP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART5_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART5_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART7_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART7_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART8_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART8_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART9_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_UART9_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART10_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART10_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART2_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART2_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART3_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART3_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART6_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_REQ_USART6_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_DAC2_CH1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_DFSDM2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_COMP1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_COMP2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_EXTI2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_I2C4_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_RTC_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_SPI6_IT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GEN_SPI6_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_GENERATOR7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_I2C4_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_I2C4_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_LPUART1_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_LPUART1_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_MEM2MEM : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_SPI6_RX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_REQ_SPI6_TX : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CCR_SOIE : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF14 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF15 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF4 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF5 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF6 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF7 : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32h7xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32h7xx_ll_dmamux.h
  • LL_EXTI_D3_PEND_CLR_DMACH6 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_DMACH7 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_LPTIM2 : stm32h7xx_ll_exti.h
  • LL_EXTI_D3_PEND_CLR_LPTIM3 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_42 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_43 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_47 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_48 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_49 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_50 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_51 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_52 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_53 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_54 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_55 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_56 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_57 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_58 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_59 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_60 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_61 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_62 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_63 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_64 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_65 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_66 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_67 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_68 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_69 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_70 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_71 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_72 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_73 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_74 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_85 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_87 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_88 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_ALL_64_95 : stm32h7xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32h7xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32h7xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32h7xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32h7xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32h7xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_5 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_6 : stm32h7xx_ll_system.h
  • LL_FLASH_LATENCY_7 : stm32h7xx_ll_system.h
  • LL_GPIO_AF_0 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32h7xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32h7xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32h7xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32h7xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32h7xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32h7xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32h7xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32h7xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32h7xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32h7xx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32h7xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32h7xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32h7xx_ll_cortex.h
  • LL_HSEM_COREID : stm32h7xx_ll_hsem.h
  • LL_HSEM_COREID_CPU1 : stm32h7xx_ll_hsem.h
  • LL_HSEM_COREID_NONE : stm32h7xx_ll_hsem.h
  • LL_HSEM_ReadReg : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_0 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_1 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_10 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_11 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_12 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_13 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_14 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_15 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_2 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_3 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_4 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_5 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_6 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_7 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_8 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_9 : stm32h7xx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_ALL : stm32h7xx_ll_hsem.h
  • LL_HSEM_WriteReg : stm32h7xx_ll_hsem.h
  • LL_I2C_ACK : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32h7xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32h7xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32h7xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32h7xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32h7xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32h7xx_ll_i2c.h
  • LL_I2C_NACK : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32h7xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32h7xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32h7xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32h7xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32h7xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32h7xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32h7xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32h7xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED : stm32h7xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_01DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_02DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_03DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_04DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_05DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_06DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_07DATA : stm32h7xx_ll_spi.h
  • LL_I2S_FIFO_TH_08DATA : stm32h7xx_ll_spi.h
  • LL_I2S_LSB_FIRST : stm32h7xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32h7xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32h7xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32h7xx_ll_spi.h
  • LL_I2S_MSB_FIRST : stm32h7xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32h7xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32h7xx_ll_spi.h
  • LL_I2S_ReadReg : stm32h7xx_ll_spi.h
  • LL_I2S_SLAVE_FIXED_CH_LENGTH : stm32h7xx_ll_spi.h
  • LL_I2S_SLAVE_VARIABLE_CH_LENGTH : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32h7xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32h7xx_ll_spi.h
  • LL_I2S_WriteReg : stm32h7xx_ll_spi.h
  • LL_IWDG_KEY_ENABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32h7xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32h7xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32h7xx_ll_iwdg.h
  • LL_LPTIM_CLK_FILTER_2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_SAI4_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32h7xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM3 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM4 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_LPTIM5 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI1_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI2_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_A : stm32h7xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_SAI4_FS_B : stm32h7xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32h7xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32h7xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32h7xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32h7xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_TXFECF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32h7xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32h7xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32h7xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32h7xx_ll_utils.h
  • LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_BLOCK_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFF_WRITE_DISABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFF_WRITE_ENABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BUFFER_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_BYTE_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_0 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_1 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_10 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_11 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_12 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_13 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_14 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_15 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_2 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_3 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_4 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_5 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_6 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_7 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_8 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_9 : stm32h7xx_ll_mdma.h
  • LL_MDMA_CHANNEL_ALL : stm32h7xx_ll_mdma.h
  • LL_MDMA_DATAALIGN_LEFT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DATAALIGN_RIGHT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_128BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_16BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_2BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_32BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_4BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_64BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_8BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BURST_SINGLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BUS_AHB_TCM : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_BUS_SYSTEM_AXI : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DATA_SIZE_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_FIXED : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INC_OFFSET_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_DEST_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_FULL_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_CHANNEL : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_CHANNEL_INSTANCE : stm32h7xx_ll_mdma.h
  • LL_MDMA_GET_INSTANCE : stm32h7xx_ll_mdma.h
  • LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_PACK_DISABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_PACK_ENABLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_HIGH : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_LOW : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_MEDIUM : stm32h7xx_ll_mdma.h
  • LL_MDMA_PRIORITY_VERYHIGH : stm32h7xx_ll_mdma.h
  • LL_MDMA_READ_ERROR : stm32h7xx_ll_mdma.h
  • LL_MDMA_ReadReg : stm32h7xx_ll_mdma.h
  • LL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM0_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM3_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM4_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM5_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM6_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA1_STREAM7_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM0_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM3_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM4_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM5_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM6_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2_STREAM7_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_CLUT_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_DMA2D_TW : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_END_CONVERSION : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_INFIFO_NF : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_INFIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_OUTFIFO_NE : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_JPEG_OUTFIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_LTDC_LINE_IT : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI1_FIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI1_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI2_FIFO_TH : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_OCTOSPI2_TC : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_COMMAND_END : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQ_SDMMC1_END_DATA : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQUEST_MODE_HW : stm32h7xx_ll_mdma.h
  • LL_MDMA_REQUEST_MODE_SW : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_128BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_16BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_2BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_32BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_4BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_64BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_8BEATS : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BURST_SINGLE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BUS_AHB_TCM : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_BUS_SYSTEM_AXI : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DATA_SIZE_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_DECREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_FIXED : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_BYTE : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_HALFWORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INC_OFFSET_WORD : stm32h7xx_ll_mdma.h
  • LL_MDMA_SRC_INCREMENT : stm32h7xx_ll_mdma.h
  • LL_MDMA_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_ll_mdma.h
  • LL_MDMA_WORD_ENDIANNESS_PRESERVE : stm32h7xx_ll_mdma.h
  • LL_MDMA_WRITE_ERROR : stm32h7xx_ll_mdma.h
  • LL_MDMA_WriteReg : stm32h7xx_ll_mdma.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32h7xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32h7xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER10 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER11 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER12 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER13 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER14 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER15 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER8 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER9 : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32h7xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32h7xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32h7xx_ll_cortex.h
  • LL_OPAMP_DELAY_STARTUP_US : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC2 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_BIAS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32h7xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_FACTORY : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA : stm32h7xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32h7xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32h7xx_ll_opamp.h
  • LL_PWR_AVDLEVEL_0 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_1 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_2 : stm32h7xx_ll_pwr.h
  • LL_PWR_AVDLEVEL_3 : stm32h7xx_ll_pwr.h
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32h7xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_CDSTOP : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_CDSTOP2 : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDRUN : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDSTANDBY : stm32h7xx_ll_pwr.h
  • LL_PWR_CPU_MODE_SRDSTOP : stm32h7xx_ll_pwr.h
  • LL_PWR_DIRECT_SMPS_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_ACTVOS : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_ACTVOSRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_AVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_BRRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_CSSF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_SBF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_CPU_STOPF : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_MMCVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_PVDO : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_SMPSEXTRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_TEMPH : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_TEMPL : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_USBRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_VBATH : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_VBATL : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC1 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC2 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC3 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC4 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC5 : stm32h7xx_ll_pwr.h
  • LL_PWR_FLAG_WKUPCR_WKUPC6 : stm32h7xx_ll_pwr.h
  • LL_PWR_LDO_SUPPLY : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32h7xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32h7xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE0 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE3 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 : stm32h7xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_1V8_SUPPLIES_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SMPS_2V5_SUPPLIES_LDO : stm32h7xx_ll_pwr.h
  • LL_PWR_SRDCR_VOSRDY : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN6 : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_NOPULL : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_PULLDOWN : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN_PULLUP : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK : stm32h7xx_ll_pwr.h
  • LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF1 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF2 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF3 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF4 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF5 : stm32h7xx_ll_pwr.h
  • LL_PWR_WKUPFR_WKUPF6 : stm32h7xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32h7xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_128 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_256 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_512 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_64 : stm32h7xx_ll_rcc.h
  • LL_RCC_AHB_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB3_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_APB4_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_HCLK_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK1_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK2_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK3_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_PCLK4_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CALC_SYSCLK_FREQ : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_CSI_DIV122 : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_CLKP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_CONFIG_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_D1CK_IsReady : stm32h7xx_ll_rcc.h
  • LL_RCC_D2CK_IsReady : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_DFSDM2_CLKSOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_HCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_FMC_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV1 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV2 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV4 : stm32h7xx_ll_rcc.h
  • LL_RCC_HSI_DIV8 : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C123_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_I2C4_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_KERWAKEUP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_KERWAKEUP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM345_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_LPTIM3_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_ll_rcc.h
  • LL_RCC_MASK_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLL1PCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_SYSCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_HCLK : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_OSPI_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32h7xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_1_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_2_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_4_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLINPUTRANGE_8_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLVCORANGE_MEDIUM : stm32h7xx_ll_rcc.h
  • LL_RCC_PLLVCORANGE_WIDE : stm32h7xx_ll_rcc.h
  • LL_RCC_POS_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32h7xx_ll_rcc.h
  • LL_RCC_REG_SHIFT : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_10 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_11 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_12 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_13 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_14 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_15 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_17 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_18 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_19 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_20 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_21 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_22 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_23 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_24 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_25 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_26 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_27 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_28 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_29 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_3 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_30 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_31 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_32 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_33 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_34 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_35 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_36 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_37 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_38 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_39 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_40 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_41 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_42 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_43 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_44 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_45 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_46 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_47 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_48 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_49 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_5 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_50 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_51 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_52 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_53 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_54 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_55 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_56 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_57 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_58 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_59 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_6 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_60 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_61 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_62 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_63 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_7 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_HSE_DIV_9 : stm32h7xx_ll_rcc.h
  • LL_RCC_RTC_NOCLOCK : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2A_CLKSOURCE_SPDIF : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SAI2B_CLKSOURCE_SPDIF : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SDMMC_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL2R : stm32h7xx_ll_rcc.h
  • LL_RCC_SPDIF_CLKSOURCE_PLL3R : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_CLKP : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL2P : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI123_CLKSOURCE_PLL3P : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI45_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_I2S_CKIN : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PCLK4 : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SPI6_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SWP_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSWAKEUP_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_SYSWAKEUP_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_TIM_PRESCALER_FOUR_TIMES : stm32h7xx_ll_rcc.h
  • LL_RCC_TIM_PRESCALER_TWICE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16910_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PCLK2 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART16_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_CSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_HSI : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_LSE : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PCLK1 : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PLL2Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USART234578_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_DISABLE : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL1Q : stm32h7xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL3Q : stm32h7xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32h7xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32h7xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_1 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_1024 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_128 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_16 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_16384 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_2 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_2048 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_256 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_32 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_32768 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_4 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_4096 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_512 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_64 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_8 : stm32h7xx_ll_rng.h
  • LL_RNG_CLKDIV_BY_8192 : stm32h7xx_ll_rng.h
  • LL_RNG_CR_IE : stm32h7xx_ll_rng.h
  • LL_RNG_CUSTOM_NIST : stm32h7xx_ll_rng.h
  • LL_RNG_NIST_COMPLIANT : stm32h7xx_ll_rng.h
  • LL_RNG_ReadReg : stm32h7xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32h7xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32h7xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32h7xx_ll_rng.h
  • LL_RNG_WriteReg : stm32h7xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32h7xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32h7xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32h7xx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32h7xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32h7xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32h7xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32h7xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32h7xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32h7xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32h7xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32h7xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ALRAF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32h7xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32h7xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32h7xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP1AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP2AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_ATAMP_TAMP3AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32h7xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32h7xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32h7xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32h7xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32h7xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32h7xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32h7xx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32h7xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_10BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_11BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_12BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_13BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_14BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_15BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_17BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_18BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_19BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_20BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_21BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_22BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_23BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_24BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_25BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_26BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_27BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_28BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_29BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_30BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_31BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_32BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_4BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_5BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_6BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_7BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRC_9BIT : stm32h7xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32h7xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_17BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_18BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_19BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_20BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_21BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_22BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_23BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_24BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_25BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_26BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_27BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_28BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_29BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_30BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_31BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_32BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32h7xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_01DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_02DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_03DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_04DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_05DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_06DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_07DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_08DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_09DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_10DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_11DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_12DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_13DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_14DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_15DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FIFO_TH_16DATA : stm32h7xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32h7xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32h7xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_00CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_01CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_02CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_03CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_04CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_05CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_06CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_07CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_08CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_09CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_10CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_11CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_12CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_13CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_14CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_ID_IDLENESS_15CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_CRCEIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_DXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_EOTIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_MODFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_OVRIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_RXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TIFREIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TSERFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TXPIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_TXTFIE : stm32h7xx_ll_spi.h
  • LL_SPI_IER_UDRIE : stm32h7xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32h7xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32h7xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32h7xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32h7xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32h7xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32h7xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32h7xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32h7xx_ll_spi.h
  • LL_SPI_ReadReg : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_0PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_1PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_2PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RX_FIFO_3PACKET : stm32h7xx_ll_spi.h
  • LL_SPI_RXCRCINIT_ALL_ONES_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32h7xx_ll_spi.h
  • LL_SPI_SIMPLEX_TX : stm32h7xx_ll_spi.h
  • LL_SPI_SR_CRCE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_DXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_EOT : stm32h7xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32h7xx_ll_spi.h
  • LL_SPI_SR_RXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_RXWNE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_SUSP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TIFRE : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TSERF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXC : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXP : stm32h7xx_ll_spi.h
  • LL_SPI_SR_TXTF : stm32h7xx_ll_spi.h
  • LL_SPI_SR_UDR : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_00CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_01CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_02CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_03CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_04CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_05CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_06CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_07CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_08CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_09CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_10CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_11CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_12CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_13CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_14CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_IDLENESS_15CYCLE : stm32h7xx_ll_spi.h
  • LL_SPI_SS_LEVEL_HIGH : stm32h7xx_ll_spi.h
  • LL_SPI_SS_LEVEL_LOW : stm32h7xx_ll_spi.h
  • LL_SPI_TXCRCINIT_ALL_ONES_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_LAST_RECEIVED : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_LAST_TRANSMITTED : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_CONFIG_REGISTER_PATTERN : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME : stm32h7xx_ll_spi.h
  • LL_SPI_UDR_DETECT_END_DATA_FRAME : stm32h7xx_ll_spi.h
  • LL_SPI_WriteReg : stm32h7xx_ll_spi.h
  • LL_SWPMI_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBERF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBFF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXOVRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CSRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTCF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXBEF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXUNRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBERIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBFIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_RXOVRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_SRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TCIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TXBEIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_IER_TXUNRIE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_DEACTF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBERF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBFF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXNE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXOVRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_SRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_SUSP : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TCF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXBEF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXUNRF : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_ReadReg : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_MULTI : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_SINGLE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_MULTI : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_SINGLE : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_B : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_C : stm32h7xx_ll_swpmi.h
  • LL_SWPMI_WriteReg : stm32h7xx_ll_swpmi.h
  • LL_SYSCFG_ANALOG_SWITCH_BOOSTEN : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PA0 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PA1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PC2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_ANALOG_SWITCH_PC3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_HIGH_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_LOW_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_BOR_OFF_RESET_LEVEL : stm32h7xx_ll_system.h
  • LL_SYSCFG_CELL_CODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_16KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_2KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_4KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_DTCM_RAM_SIZE_8KB : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTI : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTJ : stm32h7xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTK : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32h7xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32h7xx_ll_system.h
  • LL_SYSCFG_IWDG1_HW_CONTROL_MODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_IWDG1_SW_CONTROL_MODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_REGISTER_CODE : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_CM7_LOCKUP : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC : stm32h7xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32h7xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32h7xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32h7xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32h7xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32h7xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_DF1BK : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32h7xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32h7xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32h7xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32h7xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32h7xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32h7xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32h7xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32h7xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32h7xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32h7xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32h7xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32h7xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32h7xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32h7xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32h7xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32h7xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32h7xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_ReadReg : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32h7xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32h7xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM23_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI1_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM24_ETRSOURCE_SAI4_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_RCC_LSE : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_SAI1_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI2_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSA : stm32h7xx_ll_tim.h
  • LL_TIM_TIM5_ETRSOURCE_SAI4_FSB : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP2 : stm32h7xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_GPIO : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32h7xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR10 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR11 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR12 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR13 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR4 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR5 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR6 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR8 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_ITR9 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32h7xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32h7xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32h7xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32h7xx_ll_tim.h
  • LL_TIM_WriteReg : stm32h7xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32h7xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32h7xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32h7xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32h7xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32h7xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32h7xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32h7xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32h7xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32h7xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32h7xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32h7xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32h7xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32h7xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32h7xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32h7xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32h7xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32h7xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32h7xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32h7xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32h7xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32h7xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32h7xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32h7xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_FE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_NE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_PE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TC : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32h7xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32h7xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32h7xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32h7xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32h7xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32h7xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32h7xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32h7xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32h7xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32h7xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32h7xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32h7xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32h7xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32h7xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32h7xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32h7xx_ll_usart.h
  • LL_USART_ReadReg : stm32h7xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32h7xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32h7xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32h7xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32h7xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32h7xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32h7xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32h7xx_ll_usart.h
  • LL_USART_WriteReg : stm32h7xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32h7xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP176_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA216 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA225 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA169 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA176_SMPS : stm32h7xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP132_SMPS : stm32h7xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32h7xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32h7xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32h7xx_ll_wwdg.h
  • LPTIM2_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM3_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_NOT_CONNECTED : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI4_FSA : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI4_FSB : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32h7xx_hal_lptim.h
  • LPUART_BRR_MASK : stm32h7xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32h7xx_hal_uart.c
  • LPUART_BRR_MIN : stm32h7xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32h7xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32h7xx_ll_lpuart.h
  • LSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • LSE_VALUE : stm32h7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • LSI_VALUE : stm32h7xx_hal_conf.h
  • LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR_FRAME_BUFFER : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_FU : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_LI : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_RR : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_TE : stm32h7xx_hal_ltdc.h
  • LTDC_HORIZONTALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_IT_FU : stm32h7xx_hal_ltdc.h
  • LTDC_IT_LI : stm32h7xx_hal_ltdc.h
  • LTDC_IT_RR : stm32h7xx_hal_ltdc.h
  • LTDC_IT_TE : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_1 : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_2 : stm32h7xx_hal_ltdc.h
  • LTDC_LINE_NUMBER : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IIPC : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IPC : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL44 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL88 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB1555 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB4444 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB8888 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_L8 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB565 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB888 : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_IMMEDIATE : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_VERTICAL_BLANKING : stm32h7xx_hal_ltdc.h
  • LTDC_STARTPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_STOPPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_VERTICALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AL : stm32h7xx_hal_ltdc.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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  • MAX_LAYER : stm32h7xx_hal_ltdc.h
  • MAX_NBYTE_SIZE : stm32h7xx_hal_i2c.c , stm32h7xx_hal_smbus.c
  • MC_ADDRESS : stm32h7xx_hal_nor.h
  • MCO1_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO1_PIN : stm32h7xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO2_PIN : stm32h7xx_hal_rcc.c
  • MDIOS_ALL_ERRORS_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALL_REG_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALLREG_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_DIN_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_DOUT_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_IT_ERROR : stm32h7xx_hal_mdios.h
  • MDIOS_IT_READ : stm32h7xx_hal_mdios.h
  • MDIOS_IT_WRITE : stm32h7xx_hal_mdios.h
  • MDIOS_PORT_ADDRESS_SHIFT : stm32h7xx_hal_mdios.c
  • MDIOS_PREAMBLE_CHECK_DISABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_CHECK_ENABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG0 : stm32h7xx_hal_mdios.h
  • MDIOS_REG0_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG11 : stm32h7xx_hal_mdios.h
  • MDIOS_REG11_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG12 : stm32h7xx_hal_mdios.h
  • MDIOS_REG12_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG13 : stm32h7xx_hal_mdios.h
  • MDIOS_REG13_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG14 : stm32h7xx_hal_mdios.h
  • MDIOS_REG14_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG15 : stm32h7xx_hal_mdios.h
  • MDIOS_REG15_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG16 : stm32h7xx_hal_mdios.h
  • MDIOS_REG16_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG17 : stm32h7xx_hal_mdios.h
  • MDIOS_REG17_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG18 : stm32h7xx_hal_mdios.h
  • MDIOS_REG18_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG19 : stm32h7xx_hal_mdios.h
  • MDIOS_REG19_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG21 : stm32h7xx_hal_mdios.h
  • MDIOS_REG21_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG22 : stm32h7xx_hal_mdios.h
  • MDIOS_REG22_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG23 : stm32h7xx_hal_mdios.h
  • MDIOS_REG23_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG24 : stm32h7xx_hal_mdios.h
  • MDIOS_REG24_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG25 : stm32h7xx_hal_mdios.h
  • MDIOS_REG25_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG26 : stm32h7xx_hal_mdios.h
  • MDIOS_REG26_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG27 : stm32h7xx_hal_mdios.h
  • MDIOS_REG27_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG28 : stm32h7xx_hal_mdios.h
  • MDIOS_REG28_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG29 : stm32h7xx_hal_mdios.h
  • MDIOS_REG29_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG31 : stm32h7xx_hal_mdios.h
  • MDIOS_REG31_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG4 : stm32h7xx_hal_mdios.h
  • MDIOS_REG4_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG5 : stm32h7xx_hal_mdios.h
  • MDIOS_REG5_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG6 : stm32h7xx_hal_mdios.h
  • MDIOS_REG6_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG7 : stm32h7xx_hal_mdios.h
  • MDIOS_REG7_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG8 : stm32h7xx_hal_mdios.h
  • MDIOS_REG8_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG9 : stm32h7xx_hal_mdios.h
  • MDIOS_REG9_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_START_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_TURNAROUND_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_WAKEUP_EXTI_LINE : stm32h7xx_hal_mdios.h
  • MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_LEFT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_PACKENABLE : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BRT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CRQA : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_TE : stm32h7xx_hal_mdma.h
  • MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_IT_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_BRT : stm32h7xx_hal_mdma.h
  • MDMA_IT_BT : stm32h7xx_hal_mdma.h
  • MDMA_IT_CTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_TE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_ENDIANNESS_PRESERVE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_LOW : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_MEDIUM : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_CLUT_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TW : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_END_CONVERSION : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_NF : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_NE : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_LTDC_LINE_IT : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI1_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI2_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_OCTOSPI2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_COMMAND_END : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_END_DATA : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SW : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_WORD : stm32h7xx_hal_mdma.h
  • MMC_BLOCKSIZE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_DMA : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_IT : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_NONE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_HIGH_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_InitTypeDef : stm32h7xx_hal_mmc.h
  • MMC_INVALID_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_LOW_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_TypeDef : stm32h7xx_hal_mmc.h
  • MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32h7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER10 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER11 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER12 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER13 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER14 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER15 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER8 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER9 : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
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- n -

  • NAND_BUSY : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_READID : stm32h7xx_hal_nand.h
  • NAND_CMD_RESET : stm32h7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_DEVICE : stm32h7xx_hal_nand.h
  • NAND_ERROR : stm32h7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_READY : stm32h7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32h7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32h7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32h7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32h7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32h7xx_hal_nor.h
  • NOR_TMEOUT : stm32h7xx_hal_nor.h
  • NOR_WRITE : stm32h7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • c
  • d
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  • f
  • g
  • h
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- o -

  • OB_BOOT_ADD0 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD_BOTH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_AXIM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL0 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_16KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_2KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_4KB : stm32h7xx_hal_flash_ex.h
  • OB_ST_RAM_SIZE_8KB : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STDBY_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STOP_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • OB_USER_VDDMMC_HSLV : stm32h7xx_hal_flash_ex.h
  • OB_VDDMMC_HSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_VDDMMC_HSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0TO3 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_100TO103 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_104TO107 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_108TO111 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_112TO115 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_116TO119 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_120TO123 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_124TO127 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_12TO15 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_16TO19 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_20TO23 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_24TO27 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_28TO31 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_32TO35 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_36TO39 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_40TO43 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_44TO47 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_48TO51 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4TO7 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_52TO55 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_56TO59 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_60TO63 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_64TO67 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_68TO71 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_72TO75 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_76TO79 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_80TO83 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_84TO87 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_88TO91 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_8TO11 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_92TO95 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_96TO99 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_ALL : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32h7xx_hal_flash_ex.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32h7xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32h7xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC2_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_CSR_BIT_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_HSOTR_REGOFFSET : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET : stm32h7xx_ll_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_STANDALONE_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32h7xx_ll_opamp.h
  • OPAMP_VREF_10VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32h7xx_hal_opamp.h
  • OPTIONBYTE_BOOTADD : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_OTP_LOCK : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_SECURE_AREA : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32h7xx_hal_flash_ex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • c
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  • f
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  • h
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- p -

  • PACKAGE_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • PCD_MAX : stm32h7xx_hal_pcd.c
  • PCD_MIN : stm32h7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32h7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32h7xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32h7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32h7xx_hal_pcd.h
  • PLL2_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL3_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • PSSI_CR_16BITS : stm32h7xx_hal_pssi.h
  • PSSI_CR_8BITS : stm32h7xx_hal_pssi.h
  • PSSI_CR_DMA_DISABLE : stm32h7xx_hal_pssi.h
  • PSSI_CR_DMA_ENABLE : stm32h7xx_hal_pssi.h
  • PSSI_CR_OUTEN_INPUT : stm32h7xx_hal_pssi.h
  • PSSI_CR_OUTEN_OUTPUT : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_MASK : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_OVR_MIS : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_OVR_RIS : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_RTT1B : stm32h7xx_hal_pssi.h
  • PSSI_FLAG_RTT4B : stm32h7xx_hal_pssi.h
  • PSSI_MAX_NBYTE_SIZE : stm32h7xx_hal_pssi.h
  • PSSI_TIMEOUT_TRANSMIT : stm32h7xx_hal_pssi.h
  • PVD_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32h7xx_hal_pwr.c
  • PVD_MODE_IT : stm32h7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PWR_AVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_NORMAL : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_0 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_1 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_2 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_3 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_CPU_FLAGS : stm32h7xx_hal_pwr_ex.h
  • PWR_D1_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_RUN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_STOP : stm32h7xx_hal_pwr_ex.h
  • PWR_DIRECT_SMPS_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EWUP_MASK : stm32h7xx_hal_pwr.h
  • PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_AVD : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32h7xx_hal_pwr.h
  • PWR_EXTI_WAKEUP_PINS_MASK : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_ACTVOS : stm32h7xx_hal_pwr.h
  • PWR_FLAG_ACTVOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_AVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32h7xx_hal_pwr.h
  • PWR_FLAG_MMCVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SETTING_DELAY : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_SMPSEXTRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_STOP : stm32h7xx_hal_pwr.h
  • PWR_FLAG_TEMPH : stm32h7xx_hal_pwr.h
  • PWR_FLAG_TEMPL : stm32h7xx_hal_pwr.h
  • PWR_FLAG_USB33RDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VBATH : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VBATL : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP1 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP2 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP3 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP4 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP5 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_WKUP6 : stm32h7xx_hal_pwr.h
  • PWR_GFXMMU_JPEG_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_LDO_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MEMORY_BLOCK_KEEP_ON : stm32h7xx_hal_pwr_ex.h
  • PWR_MEMORY_BLOCK_SHUT_OFF : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_NO_PULL : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_DOWN : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_UP : stm32h7xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32h7xx_hal_pwr.h
  • PWR_RAM1_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM1_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM2_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM2_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_RAM3_AXI_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE3 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE4 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE5 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE0 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SMPS_1V8_SUPPLIES_EXT : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_1V8_SUPPLIES_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_EXT : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SMPS_2V5_SUPPLIES_LDO : stm32h7xx_hal_pwr_ex.h
  • PWR_SRD_AHB_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_STOPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SUPPLY_CONFIG_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_TCM_ECM_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_USB_FDCAN_MEMORY_BLOCK : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG_ALL : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET : stm32h7xx_hal_pwr_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- r -

  • RAMECC_FLAG_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAG_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAG_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_FLAGS_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ENABLE : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_ID : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_GLOBAL_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_ALL : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_DOUBLEERR_R : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_DOUBLEERR_W : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_ID : stm32h7xx_hal_ramecc.h
  • RAMECC_IT_MONITOR_SINGLEERR_R : stm32h7xx_hal_ramecc.h
  • RCC_ADCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_APB1_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_CECCLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_D1PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_D3PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_CSI_ON : stm32h7xx_hal_rcc.h
  • RCC_CSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SRDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM2CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CDCKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CDRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CPUCKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIDIV : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_IWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_WWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FMCCLKSOURCE_CDHCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_HSE_BYPASS_DIGITAL : stm32h7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSE_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI48_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI_ON : stm32h7xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_I2C123CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C123CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_IT_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_CSS : stm32h7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32h7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM345CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_LSE_BYPASS_DIGITAL : stm32h7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSE_ON : stm32h7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSI_ON : stm32h7xx_hal_rcc.h
  • RCC_MCO1 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2 : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_CSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_10 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_11 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_12 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_13 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_14 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_15 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_6 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_7 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_9 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_CSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32h7xx_hal_rcc.h
  • RCC_OSPICLKSOURCE_CDHCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_OSPICLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_ADC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CKPER : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DSI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C123 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM345 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LTDC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_OSPI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2A : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2B : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI123 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI45 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART9 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART10 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART16 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART16910 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART234578 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL1_DIVP : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVQ : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVR : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_0 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_1 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_2 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_3 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOMEDIUM : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOWIDE : stm32h7xx_hal_rcc.h
  • RCC_PLL2_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32h7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32h7xx_hal_rcc.h
  • RCC_PLL_ON : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32h7xx_hal_rcc.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV33 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV34 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV35 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV36 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV37 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV38 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV39 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV40 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV41 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV42 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV43 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV44 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV45 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV46 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV47 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV48 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV49 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV50 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV51 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV52 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV53 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV54 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV55 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV56 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV57 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV58 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV59 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV60 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV61 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV62 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV63 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32h7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2ACLKSOURCE_SPDIF : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2BCLKSOURCE_SPDIF : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI123CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI45CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_SRDPCLK4 : stm32h7xx_hal_rcc_ex.h
  • RCC_STOP_KERWAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_KERWAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART9CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART10CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_CDPCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16910CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_CDPCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART16CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_CDPCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART234578CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_WWDG1 : stm32h7xx_hal_rcc_ex.h
  • REV_ID_B : stm32h7xx_hal.h
  • REV_ID_V : stm32h7xx_hal.h
  • REV_ID_X : stm32h7xx_hal.h
  • REV_ID_Y : stm32h7xx_hal.h
  • RISING_EDGE : stm32h7xx_hal_gpio.c
  • RNG_CED_DISABLE : stm32h7xx_hal_rng.h
  • RNG_CED_ENABLE : stm32h7xx_hal_rng.h
  • RNG_CLKDIV_BY_1 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_1024 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_128 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_16 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_16384 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_2 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_2048 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_256 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_32 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_32768 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_4 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_4096 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_512 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_64 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_8 : stm32h7xx_hal_rng_ex.h
  • RNG_CLKDIV_BY_8192 : stm32h7xx_hal_rng_ex.h
  • RNG_CUSTOM_NIST : stm32h7xx_hal_rng_ex.h
  • RNG_FLAG_CECS : stm32h7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32h7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32h7xx_hal_rng.h
  • RNG_HTCFG : stm32h7xx_hal_rng_ex.c , stm32h7xx_hal_rng.c
  • RNG_HTCFG_1 : stm32h7xx_hal_rng.c , stm32h7xx_hal_rng_ex.c
  • RNG_IT_CEI : stm32h7xx_hal_rng.h
  • RNG_IT_DRDY : stm32h7xx_hal_rng.h
  • RNG_IT_SEI : stm32h7xx_hal_rng.h
  • RNG_NIST_COMPLIANT : stm32h7xx_hal_rng_ex.h
  • RNG_TIMEOUT_VALUE : stm32h7xx_hal_rng.c , stm32h7xx_hal_rng_ex.c
  • RTC_ALARM_A : stm32h7xx_hal_rtc.h
  • RTC_ALARM_B : stm32h7xx_hal_rtc.h
  • RTC_ALARM_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32h7xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32h7xx_ll_rtc.c
  • RTC_ATAMP_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_5 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_6 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_7 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_128 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_16 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_32 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_64 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ASYNCPRES_RTCCLK_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_FILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_FILTER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_INTERRUPT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_INTERRUPT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_ATAMP_SEED_NB_UINT32 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR0 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32h7xx_hal_rtc.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_DR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP2F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP3F : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32h7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32h7xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32h7xx_ll_rtc.c
  • RTC_INT_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_8 : stm32h7xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER1_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER2_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER3_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER4_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER5_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER6_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_INTERNAL_TAMPER8_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP1 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP2 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMP3 : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TAMPALL : stm32h7xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32h7xx_hal_rtc.h
  • RTC_IT_WUT : stm32h7xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32h7xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32h7xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32h7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32h7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32h7xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32h7xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32h7xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32h7xx_hal_rtc.h
  • RTC_RSF_MASK : stm32h7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32h7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32h7xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32h7xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32h7xx_ll_rtc.c
  • RTC_TAMP_NB : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_MASK_FLAG : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_X_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERDETECTIONOUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERDETECTIONOUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32h7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_MASK : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32h7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32h7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32h7xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32h7xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32h7xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32h7xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32h7xx_hal_uart_ex.c , stm32h7xx_hal_usart_ex.c , stm32h7xx_hal_smartcard_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- s -

  • SAI_AC97_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32h7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32h7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32h7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32h7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32h7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32h7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32h7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32h7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32h7xx_hal_sai.h
  • SAI_IT_AFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32h7xx_hal_sai.h
  • SAI_IT_FREQ : stm32h7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32h7xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32h7xx_hal_sai.h
  • SAI_MONOMODE : stm32h7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PCM_LONG : stm32h7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32h7xx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32h7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_STEREOMODE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32h7xx_hal_sai.h
  • SAI_ULAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ZERO_VALUE : stm32h7xx_hal_sai.h
  • SD_CONTEXT_DMA : stm32h7xx_hal_sd.h
  • SD_CONTEXT_IT : stm32h7xx_hal_sd.h
  • SD_CONTEXT_NONE : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_GET_DLYB_INSTANCE : stm32h7xx_hal_sd.c
  • SD_InitTypeDef : stm32h7xx_hal_sd.h
  • SD_TypeDef : stm32h7xx_hal_sd.h
  • SlaveAddr_MSK : stm32h7xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32h7xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CR_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_DISABLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ISR_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_STOPBITS_0_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_WORDLENGTH_9B : stm32h7xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32h7xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32h7xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32h7xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32h7xx_hal_smbus.h
  • SPDIFRX_CHANNEL_A : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_IDLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32h7xx_hal_spdifrx.h
  • SPI_1LINE_RX : stm32h7xx_hal_spi.h
  • SPI_1LINE_TX : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_10BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_11BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_12BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_13BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_14BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_15BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_16BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_17BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_18BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_19BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_20BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_21BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_22BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_23BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_24BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_25BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_26BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_27BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_28BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_29BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_30BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_31BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_32BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_4BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_5BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_6BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_7BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_9BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_17BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_18BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_19BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_20BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_21BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_22BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_23BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_24BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_25BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_26BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_27BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_28BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_29BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_30BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_31BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_32BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32h7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32h7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_09DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_10DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_11DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_12DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_13DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_14DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_15DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_16DATA : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32h7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32h7xx_hal_spi.h
  • SPI_FLAG_DXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_EOT : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32h7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32h7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXWNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_SUSP : stm32h7xx_hal_spi.h
  • SPI_FLAG_TSERF : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXC : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXP : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXTF : stm32h7xx_hal_spi.h
  • SPI_FLAG_UDR : stm32h7xx_hal_spi.h
  • SPI_HIGHEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_IT_CRCERR : stm32h7xx_hal_spi.h
  • SPI_IT_DXP : stm32h7xx_hal_spi.h
  • SPI_IT_EOT : stm32h7xx_hal_spi.h
  • SPI_IT_ERR : stm32h7xx_hal_spi.h
  • SPI_IT_FRE : stm32h7xx_hal_spi.h
  • SPI_IT_MODF : stm32h7xx_hal_spi.h
  • SPI_IT_OVR : stm32h7xx_hal_spi.h
  • SPI_IT_RXP : stm32h7xx_hal_spi.h
  • SPI_IT_TSERF : stm32h7xx_hal_spi.h
  • SPI_IT_TXP : stm32h7xx_hal_spi.h
  • SPI_IT_TXTF : stm32h7xx_hal_spi.h
  • SPI_IT_UDR : stm32h7xx_hal_spi.h
  • SPI_LOWEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32h7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32h7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32h7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32h7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_0PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_1PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_2PACKET : stm32h7xx_hal_spi.h
  • SPI_RX_FIFO_3PACKET : stm32h7xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_RECEIVED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_REGISTER_PATTERN : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_END_DATA_FRAME : stm32h7xx_hal_spi.h
  • SRDCCIP : stm32h7xx_ll_rcc.h
  • SWPMI_FLAG_DEACTF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RDYF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RDYIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32h7xx_hal_swpmi.h
  • SYSCFG_BOOT_ADDR0 : stm32h7xx_hal.h
  • SYSCFG_BOOT_ADDR1 : stm32h7xx_hal.h
  • SYSCFG_CELL_CODE : stm32h7xx_hal.h
  • SYSCFG_ETH_MII : stm32h7xx_hal.h
  • SYSCFG_ETH_RMII : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32h7xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32h7xx_hal.h
  • SYSCFG_REGISTER_CODE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_OPEN : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3 : stm32h7xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32h7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_hal_cortex.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- t -

  • TAMP_ALL : stm32h7xx_hal_rtc_ex.c
  • TAMP_OFFSET : stm32h7xx_hal_rtc_ex.h
  • TEMPSENSOR_CAL1_ADDR : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32h7xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32h7xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32h7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32h7xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32h7xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_CALC_DTS : stm32h7xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR5 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR6 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32h7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_COM : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32h7xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32h7xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_SR : stm32h7xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32h7xx_hal_tim.h
  • TIM_FLAG_COM : stm32h7xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32h7xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32h7xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_IT_BREAK : stm32h7xx_hal_tim.h
  • TIM_IT_CC1 : stm32h7xx_hal_tim.h
  • TIM_IT_CC2 : stm32h7xx_hal_tim.h
  • TIM_IT_CC3 : stm32h7xx_hal_tim.h
  • TIM_IT_CC4 : stm32h7xx_hal_tim.h
  • TIM_IT_COM : stm32h7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32h7xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32h7xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32h7xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32h7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32h7xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32h7xx_hal_tim.h
  • TIM_TIM12_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM12_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM12_TI1_RMP_SPDIF_FS : stm32h7xx_ll_tim.h
  • TIM_TIM12_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_CSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_MCO2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_CSI : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_LSE : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_RCC_MCO2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM2_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM3_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_RMP_TIM4_CH1 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM4_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM2_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM3_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_RMP_TIM4_CH2 : stm32h7xx_ll_tim.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM4_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_RCC_LSE : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_RCC_LSI : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_RMP_WKUP_IT : stm32h7xx_ll_tim.h
  • TIM_TIM16_TI1_WKUP_IT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_HSE1MHZ : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_MCO1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_RCC_HSE1MHZ : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_RCC_MCO1 : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_RMP_SPDIF_FS : stm32h7xx_ll_tim.h
  • TIM_TIM17_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM1_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM23_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM23_TI4_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM23_TI4_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM24_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI4_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_ETR_SAI4_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_SOC : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM24_TI1_RMP_CAN_RTP : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_CAN_SOC : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_CAN_TMP : stm32h7xx_ll_tim.h
  • TIM_TIM24_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM2_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM2_TI4_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM3_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_RMP_COMP1 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_COMP1_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM3_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM5_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI4_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI4_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_RMP_CAN_RTP : stm32h7xx_ll_tim.h
  • TIM_TIM5_TI1_RMP_CAN_TMP : stm32h7xx_ll_tim.h
  • TIM_TIM5_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_RMP_COMP2 : stm32h7xx_ll_tim.h
  • TIM_TIM8_TI1_RMP_GPIO : stm32h7xx_ll_tim.h
  • TIM_TRGO2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_TS_ETRF : stm32h7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR10 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR11 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR12 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR13 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR4 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR5 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR6 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR7 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR8 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR9 : stm32h7xx_hal_tim.h
  • TIM_TS_NONE : stm32h7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32h7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32h7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32h7xx_hal_tim.h
  • TIMEOUT : stm32h7xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32h7xx_hal_dac.c
  • TIMING_CLEAR_MASK : stm32h7xx_hal_i2c.c , stm32h7xx_hal_smbus.c
  • TIMx_AF1_BKCOMP1E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP1P : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP2E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKCOMP2P : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKDF1BK0E : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKINE : stm32h7xx_ll_tim.h
  • TIMx_AF1_BKINP : stm32h7xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP1E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP1P : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP2E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2COMP2P : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2DF1BK1E : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2INE : stm32h7xx_ll_tim.h
  • TIMx_AF2_BK2INP : stm32h7xx_ll_tim.h
  • TS_TIMEOUT_MS : stm32h7xx_hal_dts.c
  • TX_FIFO_DEPTH : stm32h7xx_hal_usart_ex.c , stm32h7xx_hal_smartcard_ex.c , stm32h7xx_hal_uart_ex.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32h7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32h7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32h7xx_hal_uart.h
  • UART_BRR_MAX : stm32h7xx_hal_uart.c
  • UART_BRR_MIN : stm32h7xx_hal_uart.c
  • UART_CLEAR_CMF : stm32h7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32h7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32h7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32h7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • UART_CLEAR_WUF : stm32h7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32h7xx_hal_uart.h
  • UART_DIV_LPUART : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32h7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32h7xx_hal_uart.h
  • UART_FIFOMODE_DISABLE : stm32h7xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32h7xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32h7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32h7xx_hal_uart.h
  • UART_FLAG_CMF : stm32h7xx_hal_uart.h
  • UART_FLAG_CTS : stm32h7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32h7xx_hal_uart.h
  • UART_FLAG_FE : stm32h7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32h7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32h7xx_hal_uart.h
  • UART_FLAG_NE : stm32h7xx_hal_uart.h
  • UART_FLAG_ORE : stm32h7xx_hal_uart.h
  • UART_FLAG_PE : stm32h7xx_hal_uart.h
  • UART_FLAG_REACK : stm32h7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32h7xx_hal_uart.h
  • UART_FLAG_RWU : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFF : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32h7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32h7xx_hal_uart.h
  • UART_FLAG_TC : stm32h7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32h7xx_hal_uart.h
  • UART_FLAG_TXE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_WUF : stm32h7xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32h7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32h7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32h7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32h7xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32h7xx_hal_uart.h
  • UART_IT_CM : stm32h7xx_hal_uart.h
  • UART_IT_CTS : stm32h7xx_hal_uart.h
  • UART_IT_ERR : stm32h7xx_hal_uart.h
  • UART_IT_FE : stm32h7xx_hal_uart.h
  • UART_IT_IDLE : stm32h7xx_hal_uart.h
  • UART_IT_LBD : stm32h7xx_hal_uart.h
  • UART_IT_MASK : stm32h7xx_hal_uart.h
  • UART_IT_NE : stm32h7xx_hal_uart.h
  • UART_IT_ORE : stm32h7xx_hal_uart.h
  • UART_IT_PE : stm32h7xx_hal_uart.h
  • UART_IT_RTO : stm32h7xx_hal_uart.h
  • UART_IT_RXFF : stm32h7xx_hal_uart.h
  • UART_IT_RXFNE : stm32h7xx_hal_uart.h
  • UART_IT_RXFT : stm32h7xx_hal_uart.h
  • UART_IT_RXNE : stm32h7xx_hal_uart.h
  • UART_IT_TC : stm32h7xx_hal_uart.h
  • UART_IT_TXE : stm32h7xx_hal_uart.h
  • UART_IT_TXFE : stm32h7xx_hal_uart.h
  • UART_IT_TXFNF : stm32h7xx_hal_uart.h
  • UART_IT_TXFT : stm32h7xx_hal_uart.h
  • UART_IT_WUF : stm32h7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32h7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32h7xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32h7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32h7xx_hal_uart.h
  • UART_MODE_TX : stm32h7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32h7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32h7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32h7xx_hal_uart.h
  • UART_PARITY_NONE : stm32h7xx_hal_uart.h
  • UART_PARITY_ODD : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32h7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart_ex.h
  • UART_SENDBREAK_REQUEST : stm32h7xx_hal_uart.h
  • UART_STATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32h7xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart_ex.h
  • UART_WAKEUP_ON_ADDRESS : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32h7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32h7xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32h7xx_ll_utils.h
  • USART_BRR_MAX : stm32h7xx_hal_irda.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_BRR_MIN : stm32h7xx_hal_irda.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CLEAR_FEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32h7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32h7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32h7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32h7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32h7xx_hal_uart.c , stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32h7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32h7xx_hal_usart.c , stm32h7xx_hal_smartcard.c
  • USART_CR3_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_uart.c , stm32h7xx_hal_usart.c
  • USART_CR_MASK : stm32h7xx_hal_usart.h
  • USART_CR_POS : stm32h7xx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32h7xx_hal_usart.h
  • USART_DUMMY_DATA : stm32h7xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32h7xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32h7xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32h7xx_hal_usart.h
  • USART_FLAG_FE : stm32h7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32h7xx_hal_usart.h
  • USART_FLAG_NE : stm32h7xx_hal_usart.h
  • USART_FLAG_ORE : stm32h7xx_hal_usart.h
  • USART_FLAG_PE : stm32h7xx_hal_usart.h
  • USART_FLAG_REACK : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFF : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32h7xx_hal_usart.h
  • USART_FLAG_TC : stm32h7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32h7xx_hal_usart.h
  • USART_FLAG_TXE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_UDR : stm32h7xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32h7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32h7xx_hal_usart.h
  • USART_ISR_MASK : stm32h7xx_hal_usart.h
  • USART_ISR_POS : stm32h7xx_hal_usart.h
  • USART_IT_ERR : stm32h7xx_hal_usart.h
  • USART_IT_FE : stm32h7xx_hal_usart.h
  • USART_IT_IDLE : stm32h7xx_hal_usart.h
  • USART_IT_MASK : stm32h7xx_hal_usart.h
  • USART_IT_NE : stm32h7xx_hal_usart.h
  • USART_IT_ORE : stm32h7xx_hal_usart.h
  • USART_IT_PE : stm32h7xx_hal_usart.h
  • USART_IT_RXFF : stm32h7xx_hal_usart.h
  • USART_IT_RXFNE : stm32h7xx_hal_usart.h
  • USART_IT_RXFT : stm32h7xx_hal_usart.h
  • USART_IT_RXNE : stm32h7xx_hal_usart.h
  • USART_IT_TC : stm32h7xx_hal_usart.h
  • USART_IT_TXE : stm32h7xx_hal_usart.h
  • USART_IT_TXFE : stm32h7xx_hal_usart.h
  • USART_IT_TXFNF : stm32h7xx_hal_usart.h
  • USART_IT_TXFT : stm32h7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32h7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32h7xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32h7xx_hal_usart_ex.h
  • USART_MODE_RX : stm32h7xx_hal_usart.h
  • USART_MODE_TX : stm32h7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32h7xx_hal_usart.h
  • USART_NSS_HARD : stm32h7xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32h7xx_hal_usart_ex.h
  • USART_OVERSAMPLING_16 : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32h7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32h7xx_hal_usart.h
  • USART_PARITY_NONE : stm32h7xx_hal_usart.h
  • USART_PARITY_ODD : stm32h7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32h7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32h7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32h7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32h7xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart_ex.h
  • USART_SLAVEMODE_DISABLE : stm32h7xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32h7xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32h7xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32h7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_7B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32h7xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_CEC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DCMI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DFSDM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DMA2D_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DSI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_DTS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_ETH_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_GFXMMU_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HASH_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HCD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_HRTIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_JPEG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_LTDC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_MDIOS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_MMC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_NAND_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_NOR_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OPAMP_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OSPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_OTFDEC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SDRAM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SPDIFRX_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SRAM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_SWPMI_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32h7xx_hal_conf.h
  • USE_RTOS : stm32h7xx_hal_conf.h
  • USE_SD_TRANSCEIVER : stm32h7xx_hal_conf.h
  • USE_SPI_CRC : stm32h7xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32h7xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32h7xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX1 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX2 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX4 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN1 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN2 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN3 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN4 : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_MEDIUM_OUTPUT_MAX : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_MEDIUM_OUTPUT_MIN : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_WIDE_OUTPUT_MAX : stm32h7xx_ll_utils.c
  • UTILS_PLLVCO_WIDE_OUTPUT_MIN : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY0_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY1_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY2_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY3_FREQ : stm32h7xx_ll_utils.c
  • UTILS_SCALE3_LATENCY4_FREQ : stm32h7xx_ll_utils.c
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32h7xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32h7xx_hal.c
  • VREFINT_CAL_ADDR : stm32h7xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32h7xx_ll_adc.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Globals

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- w -

  • WWDG_EWI_DISABLE : stm32h7xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32h7xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32h7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32h7xx_hal_wwdg.h
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal.h File Reference

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stm32h7xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32h7xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | REV_ID_Y ((uint32_t)0x1003)
#define | REV_ID_B ((uint32_t)0x2000)
#define | REV_ID_X ((uint32_t)0x2001)
#define | REV_ID_V ((uint32_t)0x2003)
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | SYSCFG_ETH_MII ((uint32_t)0x00000000)
#define | SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2
#define | IS_SYSCFG_ETHERNET_CONFIG(CONFIG)
#define | SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
#define | IS_SYSCFG_ANALOG_SWITCH(SWITCH)
#define | SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)
#define | IS_SYSCFG_SWITCH_STATE(STATE)
#define | SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)
#define | IS_SYSCFG_BOOT_REGISTER(REGISTER)
#define | IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
#define | SYSCFG_CELL_CODE ((uint32_t)0x00000000)
#define | SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
#define | IS_SYSCFG_CODE_SELECT(SELECT)
#define | IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
#define | EXTI_MODE_IT ((uint32_t)0x00010000)
#define | EXTI_MODE_EVT ((uint32_t)0x00020000)
#define | EXTI_RISING_EDGE ((uint32_t)0x00100000)
#define | EXTI_FALLING_EDGE ((uint32_t)0x00200000)
#define | IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
#define | IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
#define | EXTI_LINE0 ((uint32_t)0x00)
#define | EXTI_LINE1 ((uint32_t)0x01)
#define | EXTI_LINE2 ((uint32_t)0x02)
#define | EXTI_LINE3 ((uint32_t)0x03)
#define | EXTI_LINE4 ((uint32_t)0x04)
#define | EXTI_LINE5 ((uint32_t)0x05)
#define | EXTI_LINE6 ((uint32_t)0x06)
#define | EXTI_LINE7 ((uint32_t)0x07)
#define | EXTI_LINE8 ((uint32_t)0x08)
#define | EXTI_LINE9 ((uint32_t)0x09)
#define | EXTI_LINE10 ((uint32_t)0x0A)
#define | EXTI_LINE11 ((uint32_t)0x0B)
#define | EXTI_LINE12 ((uint32_t)0x0C)
#define | EXTI_LINE13 ((uint32_t)0x0D)
#define | EXTI_LINE14 ((uint32_t)0x0E)
#define | EXTI_LINE15 ((uint32_t)0x0F)
#define | EXTI_LINE16 ((uint32_t)0x10)
#define | EXTI_LINE17 ((uint32_t)0x11)
#define | EXTI_LINE18 ((uint32_t)0x12)
#define | EXTI_LINE19 ((uint32_t)0x13)
#define | EXTI_LINE20 ((uint32_t)0x14)
#define | EXTI_LINE21 ((uint32_t)0x15)
#define | EXTI_LINE22 ((uint32_t)0x16)
#define | EXTI_LINE23 ((uint32_t)0x17)
#define | EXTI_LINE24 ((uint32_t)0x18)
#define | EXTI_LINE25 ((uint32_t)0x19)
#define | EXTI_LINE26 ((uint32_t)0x1A)
#define | EXTI_LINE27 ((uint32_t)0x1B)
#define | EXTI_LINE28 ((uint32_t)0x1C)
#define | EXTI_LINE29 ((uint32_t)0x1D)
#define | EXTI_LINE30 ((uint32_t)0x1E)
#define | EXTI_LINE31 ((uint32_t)0x1F)
#define | EXTI_LINE32 ((uint32_t)0x20)
#define | EXTI_LINE33 ((uint32_t)0x21)
#define | EXTI_LINE34 ((uint32_t)0x22)
#define | EXTI_LINE35 ((uint32_t)0x23)
#define | EXTI_LINE36 ((uint32_t)0x24)
#define | EXTI_LINE37 ((uint32_t)0x25)
#define | EXTI_LINE38 ((uint32_t)0x26)
#define | EXTI_LINE39 ((uint32_t)0x27)
#define | EXTI_LINE40 ((uint32_t)0x28)
#define | EXTI_LINE41 ((uint32_t)0x29)
#define | EXTI_LINE42 ((uint32_t)0x2A)
#define | EXTI_LINE43 ((uint32_t)0x2B)
#define | EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */
#define | EXTI_LINE47 ((uint32_t)0x2F)
#define | EXTI_LINE48 ((uint32_t)0x30)
#define | EXTI_LINE49 ((uint32_t)0x31)
#define | EXTI_LINE50 ((uint32_t)0x32)
#define | EXTI_LINE51 ((uint32_t)0x33)
#define | EXTI_LINE52 ((uint32_t)0x34)
#define | EXTI_LINE53 ((uint32_t)0x35)
#define | EXTI_LINE54 ((uint32_t)0x36)
#define | EXTI_LINE55 ((uint32_t)0x37)
#define | EXTI_LINE56 ((uint32_t)0x38)
#define | EXTI_LINE57 ((uint32_t)0x39)
#define | EXTI_LINE58 ((uint32_t)0x3A)
#define | EXTI_LINE59 ((uint32_t)0x3B)
#define | EXTI_LINE60 ((uint32_t)0x3C)
#define | EXTI_LINE61 ((uint32_t)0x3D)
#define | EXTI_LINE62 ((uint32_t)0x3E)
#define | EXTI_LINE63 ((uint32_t)0x3F)
#define | EXTI_LINE64 ((uint32_t)0x40)
#define | EXTI_LINE65 ((uint32_t)0x41)
#define | EXTI_LINE66 ((uint32_t)0x42)
#define | EXTI_LINE67 ((uint32_t)0x43)
#define | EXTI_LINE68 ((uint32_t)0x44)
#define | EXTI_LINE69 ((uint32_t)0x45)
#define | EXTI_LINE70 ((uint32_t)0x46)
#define | EXTI_LINE71 ((uint32_t)0x47)
#define | EXTI_LINE72 ((uint32_t)0x48)
#define | EXTI_LINE73 ((uint32_t)0x49)
#define | EXTI_LINE74 ((uint32_t)0x4A)
#define | EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */
#define | EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */
#define | EXTI_LINE85 ((uint32_t)0x55)
#define | EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */
#define | EXTI_LINE87 ((uint32_t)0x57)
#define | EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */
#define | IS_HAL_EXTI_CONFIG_LINE(LINE)
#define | IS_EXTI_ALL_LINE(LINE)
#define | IS_EXTI_D1_LINE(LINE)
#define | IS_EXTI_D3_LINE(LINE)
#define | BDMA_CH6_CLEAR ((uint32_t)0x00000000)
#define | BDMA_CH7_CLEAR ((uint32_t)0x00000001)
#define | LPTIM2_OUT_CLEAR ((uint32_t)0x00000002)
#define | LPTIM3_OUT_CLEAR ((uint32_t)0x00000003)
#define | IS_EXTI_D3_CLEAR(SOURCE)
#define | FMC_SWAPBMAP_DISABLE (0x00000000U)
#define | FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
#define | FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
#define | IS_FMC_SWAPBMAP_MODE(__MODE__)
#define | __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
SYSCFG Break AXIRAM double ECC lock.
#define | __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
SYSCFG Break ITCM double ECC lock.
#define | __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
SYSCFG Break DTCM double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
SYSCFG Break SRAM1 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
SYSCFG Break SRAM2 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
SYSCFG Break SRAM3 double ECC lock.
#define | __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
SYSCFG Break SRAM4 double ECC lock.
#define | __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
SYSCFG Break Backup SRAM double ECC lock.
#define | __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
SYSCFG Break Cortex-M7 Lockup lock.
#define | __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
SYSCFG Break FLASH double ECC lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
#define | __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
#define | __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
#define | IS_TICKFREQ(FREQ)

Enumerations

enum | HAL_TickFreqTypeDef { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ }

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
void | HAL_MspInit (void)
Initializes the MSP.
void | HAL_MspDeInit (void)
DeInitializes the MSP.
HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
Return tick frequency.
void | HAL_SuspendTick (void)
Suspend Tick increment.
void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_VDDMMC_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio
HAL_TickFreqTypeDef uwTickFreq

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc.h File Reference

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stm32h7xx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_ll_adc.h"
#include "stm32h7xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
#define | ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B)
#define | ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B)
#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)
#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)
#define | ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)
#define | ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)
#define | ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)
#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5)
#define | ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5)
#define | ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5)
#define | ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5)
#define | ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5)
#define | ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5)
#define | ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
#define | ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)
#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_19 (LL_ADC_CHANNEL_19)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2)
#define | ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2)
#define | ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2)
#define | ADC_CONVERSIONDATA_DR (0x00000000UL)
#define | ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1)
#define | ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0)
#define | ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)
#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9)
#define | ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)
#define | ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)
#define | ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE)
#define | ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1)
#define | ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2)
#define | ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3)
#define | ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4)
#define | ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5)
#define | ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6)
#define | ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7)
#define | ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8)
#define | ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9)
#define | ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10)
#define | ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11)
#define | ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12)
#define | ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13)
#define | ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14)
#define | ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15)
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)
#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | ADC_IT_AWD ADC_IT_AWD1
#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | IS_ADC_CONVERSIONDATAMGT(DATA)
Verify the ADC data conversion setting.
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
Check if conversion is on going on regular group.
#define | ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
Check if ADC clock mode is synchronous.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
Verify the ADC resolution setting when limited to 8 bits.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.
#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
void | ADC_ConfigureBoostMode (ADC_HandleTypeDef *hadc)
Configure boost mode of selected ADC.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_adc.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions
stm32h7xx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)
#define | ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)
#define | ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)
#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)
#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)
#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)
#define | ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
#define | ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
#define | ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
#define | ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
#define | ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)
#define | ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL)
#define | ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1)
#define | ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))
#define | ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)
#define | ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
#define | ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)
#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)
#define | ADC_CFGR_FIELDS
#define | ADC_SMPR1_FIELDS
#define | ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
#define | ADC_DFSDM_MODE_DISABLE (0x00000000UL)
#define | ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE)
#define | ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
Force ADC instance in multimode mode independent (multimode disable).
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if conversion is on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
Check if conversion is on going on injected group.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
Check whether or not ADC is independent.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
Enable the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
Configure calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)
Shift the offset in function of the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD1 threshold in function of the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
#define | ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
Clear Common Control Register.
#define | ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
Report Master Instance.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC1_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC1.
#define | IS_ADC2_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC2.
#define | IS_ADC3_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC3.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DUAL_DATA_MODE(MODE)
Verify the ADC dual data mode setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
Return the DFSDM configuration mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_FactorLoad (ADC_HandleTypeDef *hadc)
Load the calibration factor from engi bytes.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_adc_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cec.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | __CEC_HandleTypeDef
CEC handle Structure definition. More...

Defines

#define | HAL_CEC_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_CEC_STATE_READY ((uint32_t)0x00000020)
#define | HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)
#define | HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)
#define | HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)
#define | HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)
#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)
#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
#define | CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
#define | CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE
#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR
#define | CEC_ISR_ALL_ERROR
#define | CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define | CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
Check CEC initiator or destination logical address setting.

Typedefs

typedef uint32_t | HAL_CEC_StateTypeDef
HAL CEC State definition.
typedef struct __CEC_HandleTypeDef | CEC_HandleTypeDef
CEC handle Structure definition.
typedef void(* | pCEC_CallbackTypeDef )(CEC_HandleTypeDef *hcec)
HAL CEC Callback pointer definition.
typedef void(* | pCEC_RxCallbackTypeDef )(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

Enumerations

enum HAL_CEC_CallbackIDTypeDef {
HAL_CEC_TX_CPLT_CB_ID = 0x00U, HAL_CEC_RX_CPLT_CB_ID = 0x01U, HAL_CEC_ERROR_CB_ID = 0x02U, HAL_CEC_MSPINIT_CB_ID = 0x03U,
HAL_CEC_MSPDEINIT_CB_ID = 0x04U
}
HAL CEC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cec.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_comp.h File Reference

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stm32h7xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.
#define | HAL_COMP_ERROR_NONE (0x00U)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)
#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)
#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)
#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)
#define | COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)
#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )
#define | COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )
#define | COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )
#define | COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )
#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)
#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)
#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)
#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)
#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_FLAG_C1I COMP_SR_C1IF
#define | COMP_FLAG_C2I COMP_SR_C2IF
#define | COMP_FLAG_LOCK COMP_CFGRx_LOCK
#define | COMP_CLEAR_C1IF COMP_ICFR_C1IF
#define | COMP_CLEAR_C2IF COMP_ICFR_C2IF
#define | COMP_IT_EN COMP_CFGRx_ITEN
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Clear the the COMP2 EXTI flag.
#define | __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified COMP interrupt source is enabled or disabled.
#define | __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified COMP flag is set or not.
#define | __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
Clears the specified COMP pending flag.
#define | __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
Clear the COMP C1I flag.
#define | __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
Clear the COMP C2I flag.
#define | __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
Enable the specified COMP interrupt.
#define | __HAL_COMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
Disable the specified COMP interrupt.
#define | __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
Enable the specified bit in the Option register.
#define | __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
Disable the specified bit in the Option register.
#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_comp.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cortex.h File Reference

  • File List
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stm32h7xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | MPU_REGION_NUMBER8 ((uint8_t)0x08)
#define | MPU_REGION_NUMBER9 ((uint8_t)0x09)
#define | MPU_REGION_NUMBER10 ((uint8_t)0x0A)
#define | MPU_REGION_NUMBER11 ((uint8_t)0x0B)
#define | MPU_REGION_NUMBER12 ((uint8_t)0x0C)
#define | MPU_REGION_NUMBER13 ((uint8_t)0x0D)
#define | MPU_REGION_NUMBER14 ((uint8_t)0x0E)
#define | MPU_REGION_NUMBER15 ((uint8_t)0x0F)
#define | CM7_CPUID ((uint32_t)0x00000003)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
#define | IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.
void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cortex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc.h File Reference

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stm32h7xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7U
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE
#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U
#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_crc.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc_ex.h File Reference

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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_crc_ex.h File Reference

Header file of CRC HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN
#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_crc_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_cryp_ex.h"

Go to the source code of this file.

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)
#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U
#define | CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define | CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define | CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
#define | CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define | CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define | CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define | CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#define | CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define | CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define | CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B CRYP_CR_DATATYPE
#define | CRYP_IT_INI CRYP_IMSCR_INIM
#define | CRYP_IT_OUTI CRYP_IMSCR_OUTIM
#define | CRYP_FLAG_IFEM CRYP_SR_IFEM
#define | CRYP_FLAG_IFNF CRYP_SR_IFNF
#define | CRYP_FLAG_OFNE CRYP_SR_OFNE
#define | CRYP_FLAG_OFFU CRYP_SR_OFFU
#define | CRYP_FLAG_BUSY CRYP_SR_BUSY
#define | CRYP_FLAG_OUTRIS 0x01000002U
#define | CRYP_FLAG_INRIS 0x01000001U
#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.
#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.
typedef void(* | pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...
enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_ERROR_CB_ID = 0x03U, HAL_CRYP_MSPINIT_CB_ID = 0x04U,
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U
}

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cryp.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp_ex.h File Reference

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Functions
stm32h7xx_hal_cryp_ex.h File Reference

Header file of CRYP HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Header file of CRYP HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cryp_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac.h File Reference

  • File List
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U
#define | DAC_TRIGGER_NONE 0x00000000U
#define | DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U
#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U
#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define | DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define | DAC_CHIPCONNECT_BOTH (1UL << 2)
#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)
#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dac.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac_ex.h File Reference

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Defines | Functions
stm32h7xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dac_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dcmi.h File Reference

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stm32h7xx_hal_dcmi.h File Reference

Header file of DCMI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DCMI_CodesInitTypeDef
DCMI Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...
struct | __DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Defines

#define | HAL_DCMI_ERROR_NONE (0x00000000U)
#define | HAL_DCMI_ERROR_OVR (0x00000001U)
#define | HAL_DCMI_ERROR_SYNC (0x00000002U)
#define | HAL_DCMI_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DCMI_ERROR_DMA (0x00000040U)
#define | HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)
#define | DCMI_MODE_CONTINUOUS (0x00000000U)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)
#define | DCMI_SYNCHRO_HARDWARE (0x00000000U)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)
#define | DCMI_PCKPOLARITY_FALLING (0x00000000U)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)
#define | DCMI_VSPOLARITY_LOW (0x00000000U)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)
#define | DCMI_HSPOLARITY_LOW (0x00000000U)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)
#define | DCMI_JPEG_DISABLE (0x00000000U)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)
#define | DCMI_CR_ALL_FRAME (0x00000000U)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)
#define | DCMI_EXTEND_DATA_8B (0x00000000U)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))
#define | DCMI_WINDOW_COORDINATE (0x3FFFU)
#define | DCMI_WINDOW_HEIGHT (0x1FFFU)
#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
#define | DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)
#define | DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)
DCMI RIS register.
#define | DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)
DCMI MIS register.
#define | DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )
#define | DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )
#define | DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)
#define | DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )
#define | DCMI_BSM_ALL (0x00000000U)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))
#define | DCMI_OEBS_ODD (0x00000000U)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)
#define | DCMI_LSM_ALL (0x00000000U)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)
#define | DCMI_OELS_ODD (0x00000000U)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)
#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flag.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.
#define | DCMI_MIS_INDEX (0x1000)
#define | DCMI_SR_INDEX (0x2000)
#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Typedefs

typedef struct __DCMI_HandleTypeDef | DCMI_HandleTypeDef
DCMI handle Structure definition.
typedef void(* | pDCMI_CallbackTypeDef )(DCMI_HandleTypeDef *hdcmi)
HAL DCMI Callback pointer definition.

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00U, HAL_DCMI_STATE_READY = 0x01U, HAL_DCMI_STATE_BUSY = 0x02U, HAL_DCMI_STATE_TIMEOUT = 0x03U,
HAL_DCMI_STATE_ERROR = 0x04U, HAL_DCMI_STATE_SUSPENDED = 0x05U
}
HAL DCMI State structures definition. More...
enum HAL_DCMI_CallbackIDTypeDef {
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, HAL_DCMI_ERROR_CB_ID = 0x03U,
HAL_DCMI_MSPINIT_CB_ID = 0x04U, HAL_DCMI_MSPDEINIT_CB_ID = 0x05U
}
HAL DCMI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_RegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
Register a User DCMI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DCMI_UnRegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
Unregister a DCMI Callback DCMI callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Header file of DCMI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dcmi.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_dfsdm.h File Reference

Header file of DFSDM HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dfsdm_ex.h"

Go to the source code of this file.

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | __DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | __DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
#define | DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U
#define | DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
#define | DFSDM_CHANNEL_STANDARD_MODE 0x00000000U
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
#define | DFSDM_CHANNEL_SPI_RISING 0x00000000U
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
#define | DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
#define | DFSDM_FILTER_SW_TRIGGER 0x00000000U
#define | DFSDM_FILTER_SYNC_TRIGGER 0x00000001U
#define | DFSDM_FILTER_EXT_TRIGGER 0x00000002U
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_COMP1_OUT
#define | DFSDM_FILTER_EXT_TRIG_COMP2_OUT
#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
#define | DFSDM_FILTER_FASTSINC_ORDER 0x00000000U
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
#define | DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
#define | DFSDM_FILTER_ERROR_NONE 0x00000000U
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U
#define | DFSDM_FILTER_ERROR_DMA 0x00000003U
#define | DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U
#define | DFSDM_NO_BREAK_SIGNAL 0x00000000U
#define | DFSDM_BREAK_SIGNAL_0 0x00000001U
#define | DFSDM_BREAK_SIGNAL_1 0x00000002U
#define | DFSDM_BREAK_SIGNAL_2 0x00000004U
#define | DFSDM_BREAK_SIGNAL_3 0x00000008U
#define | DFSDM_CHANNEL_0 0x00000001U
#define | DFSDM_CHANNEL_1 0x00010002U
#define | DFSDM_CHANNEL_2 0x00020004U
#define | DFSDM_CHANNEL_3 0x00030008U
#define | DFSDM_CHANNEL_4 0x00040010U
#define | DFSDM_CHANNEL_5 0x00050020U
#define | DFSDM_CHANNEL_6 0x00060040U
#define | DFSDM_CHANNEL_7 0x00070080U
#define | DFSDM_CONTINUOUS_CONV_OFF 0x00000000U
#define | DFSDM_CONTINUOUS_CONV_ON 0x00000001U
#define | DFSDM_AWD_HIGH_THRESHOLD 0x00000000U
#define | DFSDM_AWD_LOW_THRESHOLD 0x00000001U
#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__)
Reset DFSDM filter handle state.
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)
#define | IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)
#define | IS_DFSDM1_FILTER_INSTANCE(INSTANCE)

Typedefs

typedef struct
__DFSDM_Channel_HandleTypeDef 		DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition.
typedef void(* | pDFSDM_Channel_CallbackTypeDef )(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
DFSDM channel callback pointer definition.
typedef struct
__DFSDM_Filter_HandleTypeDef 		DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition.
typedef void(* | pDFSDM_Filter_CallbackTypeDef )(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
DFSDM filter callback pointer definition.
typedef void(* | pDFSDM_Filter_AwdCallbackTypeDef )(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU }
HAL DFSDM Channel states definition. More...
enum | HAL_DFSDM_Channel_CallbackIDTypeDef { HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U }
DFSDM channel callback ID enumeration definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, HAL_DFSDM_FILTER_STATE_READY = 0x01U, HAL_DFSDM_FILTER_STATE_REG = 0x02U, HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
}
HAL DFSDM Filter states definition. More...
enum HAL_DFSDM_Filter_CallbackIDTypeDef {
HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U,
HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U
}
DFSDM filter callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_Channel_RegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback)
Register a user DFSDM channel callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Channel_UnRegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM channel callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback)
Register a user DFSDM filter callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM filter callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback)
Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Unregister a user DFSDM filter analog watchdog callback.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Header file of DFSDM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dfsdm.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm_ex.h File Reference

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stm32h7xx_hal_dfsdm_ex.h File Reference

Header file of DFSDM HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U)

Functions

HAL_StatusTypeDef | HAL_DFDSMEx_ChannelSetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
Set value of pulses skipping.
HAL_StatusTypeDef | HAL_DFDSMEx_ChannelGetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
Get value of pulses skipping.

Detailed Description

Header file of DFSDM HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dfsdm_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE (0x00000000U)
#define | HAL_DMA_ERROR_TE (0x00000001U)
#define | HAL_DMA_ERROR_FE (0x00000002U)
#define | HAL_DMA_ERROR_DME (0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DMA_ERROR_PARAM (0x00000040U)
#define | HAL_DMA_ERROR_NO_XFER (0x00000080U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
#define | HAL_DMA_ERROR_SYNC (0x00000200U)
#define | HAL_DMA_ERROR_REQGEN (0x00000400U)
#define | HAL_DMA_ERROR_BUSY (0x00000800U)
#define | DMA_REQUEST_MEM2MEM 0U
#define | DMA_REQUEST_GENERATOR0 1U
#define | DMA_REQUEST_GENERATOR1 2U
#define | DMA_REQUEST_GENERATOR2 3U
#define | DMA_REQUEST_GENERATOR3 4U
#define | DMA_REQUEST_GENERATOR4 5U
#define | DMA_REQUEST_GENERATOR5 6U
#define | DMA_REQUEST_GENERATOR6 7U
#define | DMA_REQUEST_GENERATOR7 8U
#define | DMA_REQUEST_ADC1 9U
#define | DMA_REQUEST_ADC2 10U
#define | DMA_REQUEST_TIM1_CH1 11U
#define | DMA_REQUEST_TIM1_CH2 12U
#define | DMA_REQUEST_TIM1_CH3 13U
#define | DMA_REQUEST_TIM1_CH4 14U
#define | DMA_REQUEST_TIM1_UP 15U
#define | DMA_REQUEST_TIM1_TRIG 16U
#define | DMA_REQUEST_TIM1_COM 17U
#define | DMA_REQUEST_TIM2_CH1 18U
#define | DMA_REQUEST_TIM2_CH2 19U
#define | DMA_REQUEST_TIM2_CH3 20U
#define | DMA_REQUEST_TIM2_CH4 21U
#define | DMA_REQUEST_TIM2_UP 22U
#define | DMA_REQUEST_TIM3_CH1 23U
#define | DMA_REQUEST_TIM3_CH2 24U
#define | DMA_REQUEST_TIM3_CH3 25U
#define | DMA_REQUEST_TIM3_CH4 26U
#define | DMA_REQUEST_TIM3_UP 27U
#define | DMA_REQUEST_TIM3_TRIG 28U
#define | DMA_REQUEST_TIM4_CH1 29U
#define | DMA_REQUEST_TIM4_CH2 30U
#define | DMA_REQUEST_TIM4_CH3 31U
#define | DMA_REQUEST_TIM4_UP 32U
#define | DMA_REQUEST_I2C1_RX 33U
#define | DMA_REQUEST_I2C1_TX 34U
#define | DMA_REQUEST_I2C2_RX 35U
#define | DMA_REQUEST_I2C2_TX 36U
#define | DMA_REQUEST_SPI1_RX 37U
#define | DMA_REQUEST_SPI1_TX 38U
#define | DMA_REQUEST_SPI2_RX 39U
#define | DMA_REQUEST_SPI2_TX 40U
#define | DMA_REQUEST_USART1_RX 41U
#define | DMA_REQUEST_USART1_TX 42U
#define | DMA_REQUEST_USART2_RX 43U
#define | DMA_REQUEST_USART2_TX 44U
#define | DMA_REQUEST_USART3_RX 45U
#define | DMA_REQUEST_USART3_TX 46U
#define | DMA_REQUEST_TIM8_CH1 47U
#define | DMA_REQUEST_TIM8_CH2 48U
#define | DMA_REQUEST_TIM8_CH3 49U
#define | DMA_REQUEST_TIM8_CH4 50U
#define | DMA_REQUEST_TIM8_UP 51U
#define | DMA_REQUEST_TIM8_TRIG 52U
#define | DMA_REQUEST_TIM8_COM 53U
#define | DMA_REQUEST_TIM5_CH1 55U
#define | DMA_REQUEST_TIM5_CH2 56U
#define | DMA_REQUEST_TIM5_CH3 57U
#define | DMA_REQUEST_TIM5_CH4 58U
#define | DMA_REQUEST_TIM5_UP 59U
#define | DMA_REQUEST_TIM5_TRIG 60U
#define | DMA_REQUEST_SPI3_RX 61U
#define | DMA_REQUEST_SPI3_TX 62U
#define | DMA_REQUEST_UART4_RX 63U
#define | DMA_REQUEST_UART4_TX 64U
#define | DMA_REQUEST_UART5_RX 65U
#define | DMA_REQUEST_UART5_TX 66U
#define | DMA_REQUEST_DAC1_CH1 67U
#define | DMA_REQUEST_DAC1_CH2 68U
#define | DMA_REQUEST_TIM6_UP 69U
#define | DMA_REQUEST_TIM7_UP 70U
#define | DMA_REQUEST_USART6_RX 71U
#define | DMA_REQUEST_USART6_TX 72U
#define | DMA_REQUEST_I2C3_RX 73U
#define | DMA_REQUEST_I2C3_TX 74U
#define | DMA_REQUEST_DCMI_PSSI 75U
#define | DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
#define | DMA_REQUEST_CRYP_IN 76U
#define | DMA_REQUEST_CRYP_OUT 77U
#define | DMA_REQUEST_HASH_IN 78U
#define | DMA_REQUEST_UART7_RX 79U
#define | DMA_REQUEST_UART7_TX 80U
#define | DMA_REQUEST_UART8_RX 81U
#define | DMA_REQUEST_UART8_TX 82U
#define | DMA_REQUEST_SPI4_RX 83U
#define | DMA_REQUEST_SPI4_TX 84U
#define | DMA_REQUEST_SPI5_RX 85U
#define | DMA_REQUEST_SPI5_TX 86U
#define | DMA_REQUEST_SAI1_A 87U
#define | DMA_REQUEST_SAI1_B 88U
#define | DMA_REQUEST_SAI2_A 89U
#define | DMA_REQUEST_SAI2_B 90U
#define | DMA_REQUEST_SWPMI_RX 91U
#define | DMA_REQUEST_SWPMI_TX 92U
#define | DMA_REQUEST_SPDIF_RX_DT 93U
#define | DMA_REQUEST_SPDIF_RX_CS 94U
#define | DMA_REQUEST_DFSDM1_FLT0 101U
#define | DMA_REQUEST_DFSDM1_FLT1 102U
#define | DMA_REQUEST_DFSDM1_FLT2 103U
#define | DMA_REQUEST_DFSDM1_FLT3 104U
#define | DMA_REQUEST_TIM15_CH1 105U
#define | DMA_REQUEST_TIM15_UP 106U
#define | DMA_REQUEST_TIM15_TRIG 107U
#define | DMA_REQUEST_TIM15_COM 108U
#define | DMA_REQUEST_TIM16_CH1 109U
#define | DMA_REQUEST_TIM16_UP 110U
#define | DMA_REQUEST_TIM17_CH1 111U
#define | DMA_REQUEST_TIM17_UP 112U
#define | DMA_REQUEST_UART9_RX 116U
#define | DMA_REQUEST_UART9_TX 117U
#define | DMA_REQUEST_USART10_RX 118U
#define | DMA_REQUEST_USART10_TX 119U
#define | BDMA_REQUEST_MEM2MEM 0U
#define | BDMA_REQUEST_GENERATOR0 1U
#define | BDMA_REQUEST_GENERATOR1 2U
#define | BDMA_REQUEST_GENERATOR2 3U
#define | BDMA_REQUEST_GENERATOR3 4U
#define | BDMA_REQUEST_GENERATOR4 5U
#define | BDMA_REQUEST_GENERATOR5 6U
#define | BDMA_REQUEST_GENERATOR6 7U
#define | BDMA_REQUEST_GENERATOR7 8U
#define | BDMA_REQUEST_LPUART1_RX 9U
#define | BDMA_REQUEST_LPUART1_TX 10U
#define | BDMA_REQUEST_SPI6_RX 11U
#define | BDMA_REQUEST_SPI6_TX 12U
#define | BDMA_REQUEST_I2C4_RX 13U
#define | BDMA_REQUEST_I2C4_TX 14U
#define | BDMA_REQUEST_DAC2_CH1 17U
#define | BDMA_REQUEST_DFSDM2 18U
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
#define | DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)
#define | DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)
#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
#define | BDMA_FLAG_GL0 ((uint32_t)0x00000001)
#define | BDMA_FLAG_TC0 ((uint32_t)0x00000002)
#define | BDMA_FLAG_HT0 ((uint32_t)0x00000004)
#define | BDMA_FLAG_TE0 ((uint32_t)0x00000008)
#define | BDMA_FLAG_GL1 ((uint32_t)0x00000010)
#define | BDMA_FLAG_TC1 ((uint32_t)0x00000020)
#define | BDMA_FLAG_HT1 ((uint32_t)0x00000040)
#define | BDMA_FLAG_TE1 ((uint32_t)0x00000080)
#define | BDMA_FLAG_GL2 ((uint32_t)0x00000100)
#define | BDMA_FLAG_TC2 ((uint32_t)0x00000200)
#define | BDMA_FLAG_HT2 ((uint32_t)0x00000400)
#define | BDMA_FLAG_TE2 ((uint32_t)0x00000800)
#define | BDMA_FLAG_GL3 ((uint32_t)0x00001000)
#define | BDMA_FLAG_TC3 ((uint32_t)0x00002000)
#define | BDMA_FLAG_HT3 ((uint32_t)0x00004000)
#define | BDMA_FLAG_TE3 ((uint32_t)0x00008000)
#define | BDMA_FLAG_GL4 ((uint32_t)0x00010000)
#define | BDMA_FLAG_TC4 ((uint32_t)0x00020000)
#define | BDMA_FLAG_HT4 ((uint32_t)0x00040000)
#define | BDMA_FLAG_TE4 ((uint32_t)0x00080000)
#define | BDMA_FLAG_GL5 ((uint32_t)0x00100000)
#define | BDMA_FLAG_TC5 ((uint32_t)0x00200000)
#define | BDMA_FLAG_HT5 ((uint32_t)0x00400000)
#define | BDMA_FLAG_TE5 ((uint32_t)0x00800000)
#define | BDMA_FLAG_GL6 ((uint32_t)0x01000000)
#define | BDMA_FLAG_TC6 ((uint32_t)0x02000000)
#define | BDMA_FLAG_HT6 ((uint32_t)0x04000000)
#define | BDMA_FLAG_TE6 ((uint32_t)0x08000000)
#define | BDMA_FLAG_GL7 ((uint32_t)0x10000000)
#define | BDMA_FLAG_TC7 ((uint32_t)0x20000000)
#define | BDMA_FLAG_HT7 ((uint32_t)0x40000000)
#define | BDMA_FLAG_TE7 ((uint32_t)0x80000000)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)
Returns the current BDMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | DMA_TO_BDMA_IT(__DMA_IT__)
#define | __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
#define | __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__)
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__)
Returns the number of remaining data units in the current DMAy Streamx transfer.
#define | IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
#define | IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Transfer complete level structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U
}
HAL DMA Callbacks IDs structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma_ex.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Defines

#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U
#define | HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U
#define | HAL_DMAMUX1_SYNC_EXTI0 6U
#define | HAL_DMAMUX1_SYNC_TIM12_TRGO 7U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U
#define | HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U
#define | HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U
#define | HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U
#define | HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U
#define | HAL_DMAMUX2_SYNC_I2C4_WKUP 10U
#define | HAL_DMAMUX2_SYNC_SPI6_WKUP 11U
#define | HAL_DMAMUX2_SYNC_COMP1_OUT 12U
#define | HAL_DMAMUX2_SYNC_RTC_WKUP 13U
#define | HAL_DMAMUX2_SYNC_EXTI0 14U
#define | HAL_DMAMUX2_SYNC_EXTI2 15U
#define | HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0
#define | HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1
#define | HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
#define | HAL_DMAMUX1_REQ_GEN_EXTI0 6U
#define | HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
#define | HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
#define | HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
#define | HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
#define | HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
#define | HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
#define | HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
#define | HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
#define | HAL_DMAMUX2_REQ_GEN_EXTI0 20U
#define | HAL_DMAMUX2_REQ_GEN_EXTI2 21U
#define | HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
#define | HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
#define | HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
#define | HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
#define | HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U
#define | HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
#define | HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL
#define | IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
#define | IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
#define | IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_exti.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_exti.h File Reference

Header file of EXTI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
#define | EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
#define | EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
#define | EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
#define | EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
#define | EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
#define | EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
#define | EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define | EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#define | EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU)
#define | EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU)
#define | EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU)
#define | EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
#define | EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U)
#define | EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)
#define | EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)
#define | EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)
#define | EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
#define | EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#define | EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define | EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
#define | EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
#define | EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#define | EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#define | EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define | EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define | EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
#define | EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
#define | EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
#define | EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
#define | EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
#define | EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
#define | EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
#define | EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
#define | EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
#define | EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
#define | EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define | EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
#define | EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define | EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU)
#define | EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU)
#define | EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
#define | EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#define | EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
#define | EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#define | EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
#define | EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
#define | EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#define | EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
#define | EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#define | EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
#define | EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define | EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
#define | EXTI_MODE_NONE 0x00000000U
#define | EXTI_MODE_INTERRUPT 0x00000001U
#define | EXTI_MODE_EVENT 0x00000002U
#define | EXTI_TRIGGER_NONE 0x00000000U
#define | EXTI_TRIGGER_RISING 0x00000001U
#define | EXTI_TRIGGER_FALLING 0x00000002U
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
#define | EXTI_GPIOA 0x00000000U
#define | EXTI_GPIOB 0x00000001U
#define | EXTI_GPIOC 0x00000002U
#define | EXTI_GPIOD 0x00000003U
#define | EXTI_GPIOE 0x00000004U
#define | EXTI_GPIOF 0x00000005U
#define | EXTI_GPIOG 0x00000006U
#define | EXTI_GPIOH 0x00000007U
#define | EXTI_GPIOI 0x00000008U
#define | EXTI_GPIOJ 0x00000009U
#define | EXTI_GPIOK 0x0000000AU
#define | EXTI_D3_PENDCLR_SRC_NONE 0x00000000U
#define | EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U
#define | EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U
#define | EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U
#define | EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U
#define | EXTI_PROPERTY_SHIFT 24U
EXTI Line property definition.
#define | EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_EVENT_PRESENCE_SHIFT 28U
EXTI Event presence definition.
#define | EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
#define | EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
#define | EXTI_REG_SHIFT 16U
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00UL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01UL << EXTI_REG_SHIFT)
#define | EXTI_REG3 (0x02UL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
#define | EXTI_PIN_MASK 0x0000001FUL
#define | EXTI_TARGET_SHIFT 20U
EXTI Target and bit usage.
#define | EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT)
#define | EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
#define | EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1
#define | EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 89UL
EXTI Line number.
#define | IS_EXTI_PROPERTY(__LINE__)
#define | IS_EXTI_TARGET(__LINE__)
#define | IS_EXTI_LINE(__LINE__)
#define | IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
#define | IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
#define | IS_EXTI_PENDING_EDGE(__LINE__)
#define | IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL)
#define | IS_EXTI_D3_PENDCLR_SRC(__SRC__)

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U }

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

Header file of EXTI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_exti.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_fdcan.h File Reference

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stm32h7xx_hal_fdcan.h File Reference

Header file of FDCAN HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_ClkCalUnitTypeDef
FDCAN clock calibration unit structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_TT_ConfigTypeDef
FDCAN TT Init structure definition. More...
struct | FDCAN_TriggerTypeDef
FDCAN Trigger structure definition. More...
struct | FDCAN_TTOperationStatusTypeDef
FDCAN TT Operation Status structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE
#define | HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU
#define | HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO
#define | HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1
#define | HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2
#define | HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT
#define | HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT
#define | HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW
#define | HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)
#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))
#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U)
#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)
#define | FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)
#define | FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)
#define | FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)
#define | FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)
#define | FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)
#define | FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)
#define | FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)
#define | FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)
#define | FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)
#define | FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)
#define | FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)
#define | FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)
#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)
#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)
#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)
#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)
#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)
#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)
#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)
#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)
#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)
#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)
#define | FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)
#define | FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)
#define | FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)
#define | FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)
#define | FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)
#define | FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)
#define | FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)
#define | FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)
#define | FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)
#define | FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)
#define | FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)
#define | FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)
#define | FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)
#define | FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)
#define | FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)
#define | FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)
#define | FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)
#define | FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)
#define | FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)
#define | FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)
#define | FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)
#define | FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)
#define | FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)
#define | FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)
#define | FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)
#define | FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)
#define | FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)
#define | FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)
#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)
#define | FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)
#define | FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)
#define | FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)
#define | FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)
#define | FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)
#define | FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)
#define | FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)
#define | FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)
#define | FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)
#define | FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)
#define | FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)
#define | FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)
#define | FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)
#define | FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)
#define | FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)
#define | FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)
#define | FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)
#define | FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)
#define | FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)
#define | FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)
#define | FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)
#define | FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)
#define | FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)
#define | FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)
#define | FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)
#define | FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)
#define | FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)
#define | FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)
#define | FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)
#define | FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)
#define | FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)
#define | FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)
#define | FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)
#define | FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)
#define | FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)
#define | FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)
#define | FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)
#define | FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)
#define | FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)
#define | FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)
#define | FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)
#define | FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)
#define | FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)
#define | FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)
#define | FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)
#define | FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)
#define | FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)
#define | FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)
#define | FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)
#define | FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)
#define | FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)
#define | FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)
#define | FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)
#define | FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)
#define | FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)
#define | FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)
#define | FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)
#define | FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)
#define | FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)
#define | FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)
#define | FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)
#define | FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)
#define | FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)
#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)
#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)
#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)
#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)
#define | FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)
#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)
#define | FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)
#define | FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)
#define | FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)
#define | FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)
#define | FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)
#define | FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)
#define | FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)
#define | FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)
#define | FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)
#define | FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)
#define | FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)
#define | FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)
#define | FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)
#define | FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)
#define | FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)
#define | FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)
#define | FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)
#define | FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)
#define | FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)
#define | FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)
#define | FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)
#define | FDCAN_TT_SLAVE ((uint32_t)0x00000000U)
#define | FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)
#define | FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)
#define | FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)
#define | FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)
#define | FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)
#define | FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)
#define | FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)
#define | FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)
#define | FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)
#define | FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)
#define | FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)
#define | FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)
#define | FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)
#define | FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)
#define | FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)
#define | FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)
#define | FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)
#define | FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)
#define | FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)
#define | FDCAN_TT_WARNING ((uint32_t)0x00000001U)
#define | FDCAN_TT_ERROR ((uint32_t)0x00000002U)
#define | FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)
#define | FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)
#define | FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)
#define | FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)
#define | FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)
#define | FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)
#define | FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)
#define | FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)
#define | FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)
#define | CCU_IR_MASK ((uint32_t)0xC0000000U)
#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)
#define | FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)
#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE
#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE
#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE
#define | FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)
#define | FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)
#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE
#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE
#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE
#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE
#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE
#define | FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC
#define | FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC
#define | FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM
#define | FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG
#define | FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI
#define | FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI
#define | FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE
#define | FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW
#define | FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD
#define | FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE
#define | FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU
#define | FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2
#define | FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC
#define | FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT
#define | FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT
#define | FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW
#define | FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER
#define | FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE
#define | FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE
#define | FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME
#define | FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE
#define | FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE
#define | FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE
#define | FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE
#define | FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE
#define | FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE
#define | FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE
#define | FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE
#define | FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE
#define | FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E
#define | FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E
#define | FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE
#define | FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE
#define | FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE
#define | FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE
#define | FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE
#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
Enable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
Disable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
Check whether the specified FDCAN TT interrupt is set or not.
#define | __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
Clear the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
Check whether the specified FDCAN TT flag is set or not.
#define | __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
Clear the specified FDCAN TT flags.
#define | __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
Check if the specified FDCAN TT interrupt source is enabled or disabled.
#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
#define | IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
#define | IS_FDCAN_DATA_SIZE(SIZE)
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
#define | IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
#define | IS_FDCAN_FIFO_WATERMARK(FIFO)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH)
#define | IS_FDCAN_CALIBRATION_COUNTER(COUNTER)
#define | IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD)
#define | IS_FDCAN_TT_REPEAT_FACTOR(FACTOR)
#define | IS_FDCAN_TT_TRIGGER_TYPE(TYPE)
#define | IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT)
#define | IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT)
#define | IS_FDCAN_OPERATION_MODE(MODE)
#define | IS_FDCAN_TT_OPERATION(OPERATION)
#define | IS_FDCAN_TT_TIME_MASTER(FUNCTION)
#define | IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC)
#define | IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING)
#define | IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY)
#define | IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER)
#define | IS_FDCAN_TT_CYCLE_START_SYNC(SYNC)
#define | IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
#define | IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
#define | IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
#define | IS_FDCAN_TT_TUR_LEVEL_1(NC, DC) ((NC) >= (4U * (DC)))
#define | IS_FDCAN_TT_TUR_LEVEL_0_2(NC, DC) ((NC) >= (8U * (DC)))
#define | IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
#define | IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE)
#define | IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY)
#define | IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE)

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_ClockCalibrationCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
typedef void(* | pFDCAN_TT_ScheduleSyncCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
typedef void(* | pFDCAN_TT_TimeMarkCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
typedef void(* | pFDCAN_TT_StopWatchCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
typedef void(* | pFDCAN_TT_GlobalTimeCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U,
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, HAL_FDCAN_MSPINIT_CB_ID = 0x06U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U
}
HAL FDCAN common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
Register Clock Calibration FDCAN Callback To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Clock Calibration FDCAN Callback Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
Register TT Schedule Synchronization FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Schedule Synchronization FDCAN Callback TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
Register TT Time Mark FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Time Mark FDCAN Callback TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
Register TT Stop Watch FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Stop Watch FDCAN Callback TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
Register TT Global Time FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Global Time FDCAN Callback TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.

Detailed Description

Header file of FDCAN HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_fdcan.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions | Variables
stm32h7xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR
#define | HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR
#define | HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR
#define | HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR
#define | HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR
#define | HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR
#define | HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR
#define | HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1
#define | HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1
#define | HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1
#define | HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1
#define | HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1
#define | HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1
#define | HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1
#define | HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1
#define | HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1
#define | HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2
#define | HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2
#define | HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2
#define | HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2
#define | HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2
#define | HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2
#define | HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2
#define | HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2
#define | HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2
#define | HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR
#define | FLASH_TYPEPROGRAM_FLASHWORD 0x01U
#define | FLASH_TYPEPROGRAM_OTPWORD 0x02U
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_WBNE FLASH_SR_WBNE
#define | FLASH_FLAG_QW FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR FLASH_SR_INCERR
#define | FLASH_FLAG_RDPERR FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND FLASH_SR_CRCEND
#define | FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR
#define | FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY
#define | FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE
#define | FLASH_FLAG_QW_BANK1 FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR
#define | FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND
#define | FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR
#define | FLASH_FLAG_ALL_ERRORS_BANK1
#define | FLASH_FLAG_ALL_BANK1
#define | FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)
#define | FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)
#define | FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)
#define | FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)
#define | FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)
#define | FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)
#define | FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)
#define | FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U)
#define | FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)
#define | FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)
#define | FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)
#define | FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U)
#define | FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U)
#define | FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)
#define | FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U)
#define | FLASH_FLAG_ALL_ERRORS_BANK2
#define | FLASH_FLAG_ALL_BANK2
#define | FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE
#define | FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE
#define | FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE
#define | FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE
#define | FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE
#define | FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE
#define | FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE
#define | FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE
#define | FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE
#define | FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE
#define | FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE
#define | FLASH_IT_ALL_BANK1
#define | FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)
#define | FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)
#define | FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)
#define | FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)
#define | FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)
#define | FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)
#define | FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)
#define | FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)
#define | FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)
#define | FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)
#define | FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U)
#define | FLASH_IT_ALL_BANK2
#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPT_KEY1 0x08192A3BU
#define | FLASH_OPT_KEY2 0x4C5D6E7FU
#define | FLASH_SECTOR_0 0U
#define | FLASH_SECTOR_1 1U
#define | FLASH_SECTOR_2 2U
#define | FLASH_SECTOR_3 3U
#define | FLASH_SECTOR_4 4U
#define | FLASH_SECTOR_5 5U
#define | FLASH_SECTOR_6 6U
#define | FLASH_SECTOR_7 7U
#define | FLASH_SECTOR_8 8U
#define | FLASH_SECTOR_9 9U
#define | FLASH_SECTOR_10 10U
#define | FLASH_SECTOR_11 11U
#define | FLASH_SECTOR_12 12U
#define | FLASH_SECTOR_13 13U
#define | FLASH_SECTOR_14 14U
#define | FLASH_SECTOR_15 15U
#define | FLASH_SECTOR_16 16U
#define | FLASH_SECTOR_17 17U
#define | FLASH_SECTOR_18 18U
#define | FLASH_SECTOR_19 19U
#define | FLASH_SECTOR_20 20U
#define | FLASH_SECTOR_21 21U
#define | FLASH_SECTOR_22 22U
#define | FLASH_SECTOR_23 23U
#define | FLASH_SECTOR_24 24U
#define | FLASH_SECTOR_25 25U
#define | FLASH_SECTOR_26 26U
#define | FLASH_SECTOR_27 27U
#define | FLASH_SECTOR_28 28U
#define | FLASH_SECTOR_29 29U
#define | FLASH_SECTOR_30 30U
#define | FLASH_SECTOR_31 31U
#define | FLASH_SECTOR_32 32U
#define | FLASH_SECTOR_33 33U
#define | FLASH_SECTOR_34 34U
#define | FLASH_SECTOR_35 35U
#define | FLASH_SECTOR_36 36U
#define | FLASH_SECTOR_37 37U
#define | FLASH_SECTOR_38 38U
#define | FLASH_SECTOR_39 39U
#define | FLASH_SECTOR_40 40U
#define | FLASH_SECTOR_41 41U
#define | FLASH_SECTOR_42 42U
#define | FLASH_SECTOR_43 43U
#define | FLASH_SECTOR_44 44U
#define | FLASH_SECTOR_45 45U
#define | FLASH_SECTOR_46 46U
#define | FLASH_SECTOR_47 47U
#define | FLASH_SECTOR_48 48U
#define | FLASH_SECTOR_49 49U
#define | FLASH_SECTOR_50 50U
#define | FLASH_SECTOR_51 51U
#define | FLASH_SECTOR_52 52U
#define | FLASH_SECTOR_53 53U
#define | FLASH_SECTOR_54 54U
#define | FLASH_SECTOR_55 55U
#define | FLASH_SECTOR_56 56U
#define | FLASH_SECTOR_57 57U
#define | FLASH_SECTOR_58 58U
#define | FLASH_SECTOR_59 59U
#define | FLASH_SECTOR_60 60U
#define | FLASH_SECTOR_61 61U
#define | FLASH_SECTOR_62 62U
#define | FLASH_SECTOR_63 63U
#define | FLASH_SECTOR_64 64U
#define | FLASH_SECTOR_65 65U
#define | FLASH_SECTOR_66 66U
#define | FLASH_SECTOR_67 67U
#define | FLASH_SECTOR_68 68U
#define | FLASH_SECTOR_69 69U
#define | FLASH_SECTOR_70 70U
#define | FLASH_SECTOR_71 71U
#define | FLASH_SECTOR_72 72U
#define | FLASH_SECTOR_73 73U
#define | FLASH_SECTOR_74 74U
#define | FLASH_SECTOR_75 75U
#define | FLASH_SECTOR_76 76U
#define | FLASH_SECTOR_77 77U
#define | FLASH_SECTOR_78 78U
#define | FLASH_SECTOR_79 79U
#define | FLASH_SECTOR_80 80U
#define | FLASH_SECTOR_81 81U
#define | FLASH_SECTOR_82 82U
#define | FLASH_SECTOR_83 83U
#define | FLASH_SECTOR_84 84U
#define | FLASH_SECTOR_85 85U
#define | FLASH_SECTOR_86 86U
#define | FLASH_SECTOR_87 87U
#define | FLASH_SECTOR_88 88U
#define | FLASH_SECTOR_89 89U
#define | FLASH_SECTOR_90 90U
#define | FLASH_SECTOR_91 91U
#define | FLASH_SECTOR_92 92U
#define | FLASH_SECTOR_93 93U
#define | FLASH_SECTOR_94 94U
#define | FLASH_SECTOR_95 95U
#define | FLASH_SECTOR_96 96U
#define | FLASH_SECTOR_97 97U
#define | FLASH_SECTOR_98 98U
#define | FLASH_SECTOR_99 99U
#define | FLASH_SECTOR_100 100U
#define | FLASH_SECTOR_101 101U
#define | FLASH_SECTOR_102 102U
#define | FLASH_SECTOR_103 103U
#define | FLASH_SECTOR_104 104U
#define | FLASH_SECTOR_105 105U
#define | FLASH_SECTOR_106 106U
#define | FLASH_SECTOR_107 107U
#define | FLASH_SECTOR_108 108U
#define | FLASH_SECTOR_109 109U
#define | FLASH_SECTOR_110 110U
#define | FLASH_SECTOR_111 111U
#define | FLASH_SECTOR_112 112U
#define | FLASH_SECTOR_113 113U
#define | FLASH_SECTOR_114 114U
#define | FLASH_SECTOR_115 115U
#define | FLASH_SECTOR_116 116U
#define | FLASH_SECTOR_117 117U
#define | FLASH_SECTOR_118 118U
#define | FLASH_SECTOR_119 119U
#define | FLASH_SECTOR_120 120U
#define | FLASH_SECTOR_121 121U
#define | FLASH_SECTOR_122 122U
#define | FLASH_SECTOR_123 123U
#define | FLASH_SECTOR_124 124U
#define | FLASH_SECTOR_125 125U
#define | FLASH_SECTOR_126 126U
#define | FLASH_SECTOR_127 127U
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
Checks whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
#define | __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
Clear the specified FLASH flag.
#define | __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define | IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
#define | IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define | IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)
#define | IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_PROGRAM_BANK1,
FLASH_PROC_SECTERASE_BANK2, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_ALLBANK_MASSERASE
}
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option bytes loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.
HAL_StatusTypeDef | FLASH_CRC_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH CRC computation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_flash.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32h7xx_hal_flash_ex.h File Reference

Header file of FLASH HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_CRCInitTypeDef
FLASH Erase structure definition. More...

Defines

#define | FLASH_TYPEERASE_SECTORS 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x01U
#define | OB_WRPSTATE_DISABLE 0x00000000U
#define | OB_WRPSTATE_ENABLE 0x00000001U
#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_PCROP 0x08U
#define | OPTIONBYTE_BOR 0x10U
#define | OPTIONBYTE_SECURE_AREA 0x20U
#define | OPTIONBYTE_BOOTADD 0x40U
#define | OPTIONBYTE_OTP_LOCK 0x80U
#define | OB_RDP_LEVEL_0 0xAA00U
#define | OB_RDP_LEVEL_1 0x5500U
#define | OB_RDP_LEVEL_2 0xCC00U
#define | OB_WWDG_SW 0x10U
#define | OB_WWDG_HW 0x00U
#define | OB_IWDG_SW 0x20U
#define | OB_IWDG_HW 0x00U
#define | OB_STOP_NO_RST 0x40U
#define | OB_STOP_RST 0x00U
#define | OB_STDBY_NO_RST 0x80U
#define | OB_STDBY_RST 0x00U
#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
#define | OB_BOR_LEVEL0 0x00000000U
#define | OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
#define | OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
#define | OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)
#define | OB_BOOTADDR_ITCM_RAM 0x0000U
#define | OB_BOOTADDR_SYSTEM 0x0040U
#define | OB_BOOTADDR_ITCM_FLASH 0x0080U
#define | OB_BOOTADDR_AXIM_FLASH 0x2000U
#define | OB_BOOTADDR_DTCM_RAM 0x8000U
#define | OB_BOOTADDR_SRAM1 0x8004U
#define | OB_BOOTADDR_SRAM2 0x8013U
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
#define | FLASH_BANK_1 0x01U
#define | FLASH_BANK_2 0x02U
#define | FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)
#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
#define | OB_WRP_SECTOR_0TO3 0x00000001U
#define | OB_WRP_SECTOR_4TO7 0x00000002U
#define | OB_WRP_SECTOR_8TO11 0x00000004U
#define | OB_WRP_SECTOR_12TO15 0x00000008U
#define | OB_WRP_SECTOR_16TO19 0x00000010U
#define | OB_WRP_SECTOR_20TO23 0x00000020U
#define | OB_WRP_SECTOR_24TO27 0x00000040U
#define | OB_WRP_SECTOR_28TO31 0x00000080U
#define | OB_WRP_SECTOR_32TO35 0x00000100U
#define | OB_WRP_SECTOR_36TO39 0x00000200U
#define | OB_WRP_SECTOR_40TO43 0x00000400U
#define | OB_WRP_SECTOR_44TO47 0x00000800U
#define | OB_WRP_SECTOR_48TO51 0x00001000U
#define | OB_WRP_SECTOR_52TO55 0x00002000U
#define | OB_WRP_SECTOR_56TO59 0x00004000U
#define | OB_WRP_SECTOR_60TO63 0x00008000U
#define | OB_WRP_SECTOR_64TO67 0x00010000U
#define | OB_WRP_SECTOR_68TO71 0x00020000U
#define | OB_WRP_SECTOR_72TO75 0x00040000U
#define | OB_WRP_SECTOR_76TO79 0x00080000U
#define | OB_WRP_SECTOR_80TO83 0x00100000U
#define | OB_WRP_SECTOR_84TO87 0x00200000U
#define | OB_WRP_SECTOR_88TO91 0x00400000U
#define | OB_WRP_SECTOR_92TO95 0x00800000U
#define | OB_WRP_SECTOR_96TO99 0x01000000U
#define | OB_WRP_SECTOR_100TO103 0x02000000U
#define | OB_WRP_SECTOR_104TO107 0x04000000U
#define | OB_WRP_SECTOR_108TO111 0x08000000U
#define | OB_WRP_SECTOR_112TO115 0x10000000U
#define | OB_WRP_SECTOR_116TO119 0x20000000U
#define | OB_WRP_SECTOR_120TO123 0x40000000U
#define | OB_WRP_SECTOR_124TO127 0x80000000U
#define | OB_WRP_SECTOR_ALL 0xFFFFFFFFU
#define | OB_SECURITY_DISABLE 0x00000000U
#define | OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
#define | OB_ST_RAM_SIZE_2KB 0x00000000U
#define | OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
#define | OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
#define | OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
#define | OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
#define | OB_IWDG1_HW 0x00000000U
#define | OB_STOP_RST_D1 0x00000000U
#define | OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
#define | OB_STDBY_RST_D1 0x00000000U
#define | OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
#define | OB_SWAP_BANK_DISABLE 0x00000000U
#define | OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT
#define | OB_IOHSLV_DISABLE 0x00000000U
#define | OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
#define | OB_VDDMMC_HSLV_DISABLE 0x00000000U
#define | OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV
#define | OB_BOOT_ADD0 0x01U
#define | OB_BOOT_ADD1 0x02U
#define | OB_BOOT_ADD_BOTH 0x03U
#define | OB_USER_IWDG1_SW 0x0001U
#define | OB_USER_NRST_STOP_D1 0x0002U
#define | OB_USER_NRST_STDBY_D1 0x0004U
#define | OB_USER_IWDG_STOP 0x0008U
#define | OB_USER_IWDG_STDBY 0x0010U
#define | OB_USER_ST_RAM_SIZE 0x0020U
#define | OB_USER_SECURITY 0x0040U
#define | OB_USER_IOHSLV 0x0080U
#define | OB_USER_SWAP_BANK 0x0100U
#define | OB_USER_VDDMMC_HSLV 0x0200U
#define | OB_SECURE_RDP_NOT_ERASE 0x00000000U
#define | OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
#define | FLASH_CRC_ADDR 0x00000000U
#define | FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
#define | FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)
#define | FLASH_CRC_BURST_SIZE_4 0x00000000U
#define | FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
#define | FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
#define | FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
#define | FLASH_PROGRAMMING_DELAY_0 0x00000000U
#define | FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
#define | FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
#define | FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
#define | FLASH_OTP_BLOCK_0 0x00000001U
#define | FLASH_OTP_BLOCK_1 0x00000002U
#define | FLASH_OTP_BLOCK_2 0x00000004U
#define | FLASH_OTP_BLOCK_3 0x00000008U
#define | FLASH_OTP_BLOCK_4 0x00000010U
#define | FLASH_OTP_BLOCK_5 0x00000020U
#define | FLASH_OTP_BLOCK_6 0x00000040U
#define | FLASH_OTP_BLOCK_7 0x00000080U
#define | FLASH_OTP_BLOCK_8 0x00000100U
#define | FLASH_OTP_BLOCK_9 0x00000200U
#define | FLASH_OTP_BLOCK_10 0x00000400U
#define | FLASH_OTP_BLOCK_11 0x00000800U
#define | FLASH_OTP_BLOCK_12 0x00001000U
#define | FLASH_OTP_BLOCK_13 0x00002000U
#define | FLASH_OTP_BLOCK_14 0x00004000U
#define | FLASH_OTP_BLOCK_15 0x00008000U
#define | FLASH_OTP_BLOCK_ALL 0x0000FFFFU
#define | __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
#define | __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
Set the FLASH Programming Delay.
#define | __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
Get the FLASH Programming Delay.
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
#define | IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define | IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
#define | IS_OB_PCROP_RDP(CONFIG)
#define | IS_OB_SECURE_RDP(CONFIG)
#define | IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
#define | IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define | IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
#define | IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#define | IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define | IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_USER_ST_RAM_SIZE(VALUE)
#define | IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
#define | IS_OB_BOOT_ADD_OPTION(VALUE)
#define | IS_FLASH_TYPECRC(VALUE)
#define | IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_ComputeCRC (FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
Erase the specified FLASH memory sector.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_flash_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gfxmmu.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_gfxmmu.h File Reference

Header file of GFXMMU HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | GFXMMU_BuffersTypeDef
GFXMMU buffers structure definition. More...
struct | GFXMMU_CachePrefetchTypeDef
GFXMMU cache and pre-fetch structure definition. More...
struct | GFXMMU_InterruptsTypeDef
GFXMMU interrupts structure definition. More...
struct | GFXMMU_InitTypeDef
GFXMMU init structure definition. More...
struct | __GFXMMU_HandleTypeDef
GFXMMU handle structure definition. More...
struct | GFXMMU_LutLineTypeDef
GFXMMU LUT line structure definition. More...

Defines

#define | GFXMMU_256BLOCKS 0x00000000U
#define | GFXMMU_192BLOCKS GFXMMU_CR_192BM
#define | GFXMMU_CACHE_LOCK_DISABLE 0x00000000U
#define | GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL
#define | GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U
#define | GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0
#define | GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1
#define | GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB
#define | GFXMMU_CACHE_FORCE_DISABLE 0x00000000U
#define | GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC
#define | GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U
#define | GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB
#define | GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U
#define | GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC
#define | GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD
#define | GFXMMU_PREFETCH_ENABLE 0x00000000U
#define | GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE
#define | GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE
#define | GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE
#define | GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE
#define | GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE
#define | GFXMMU_ERROR_NONE 0x00000000U
#define | GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF
#define | GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF
#define | GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF
#define | GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF
#define | GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF
#define | GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U
#define | GFXMMU_LUT_LINE_DISABLE 0x00000000U
#define | GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN
#define | GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF
#define | GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI
#define | __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__)
Reset GFXMMU handle state.
#define | IS_GFXMMU_BLOCKS_PER_LINE(VALUE)
#define | IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
#define | IS_GFXMMU_CACHE_LOCK(VALUE)
#define | IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE)
#define | IS_GFXMMU_CACHE_FORCE(VALUE)
#define | IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE)
#define | IS_GFXMMU_OUTTER_CACHABILITY(VALUE)
#define | IS_GFXMMU_PREFETCH(VALUE)
#define | IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
#define | IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
#define | IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
#define | IS_GFXMMU_LUT_LINE_STATUS(VALUE)
#define | IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
#define | IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
#define | IS_GFXMMU_CACHE_FORCE_ACTION(VALUE)

Typedefs

typedef struct
__GFXMMU_HandleTypeDef 		GFXMMU_HandleTypeDef
GFXMMU handle structure definition.
typedef void(* | pGFXMMU_CallbackTypeDef )(GFXMMU_HandleTypeDef *hgfxmmu)
GFXMMU callback pointer definition.

Enumerations

enum | HAL_GFXMMU_StateTypeDef { HAL_GFXMMU_STATE_RESET = 0x00U, HAL_GFXMMU_STATE_READY = 0x01U }
HAL GFXMMU states definition. More...
enum | HAL_GFXMMU_CallbackIDTypeDef { HAL_GFXMMU_ERROR_CB_ID = 0x00U, HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U }
GFXMMU callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_GFXMMU_Init (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU according to the specified parameters in the GFXMMU_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_GFXMMU_DeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU.
__weak void | HAL_GFXMMU_MspInit (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU MSP.
__weak void | HAL_GFXMMU_MspDeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU MSP.
HAL_StatusTypeDef | HAL_GFXMMU_RegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID, pGFXMMU_CallbackTypeDef pCallback)
Register a user GFXMMU callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_GFXMMU_UnRegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID)
Unregister a user GFXMMU callback.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigLut (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address)
This function allows to copy LUT from flash to look up RAM.
HAL_StatusTypeDef | HAL_GFXMMU_DisableLutLines (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber)
This function allows to disable a range of LUT lines.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigLutLine (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
This function allows to configure one line of LUT.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigForceCache (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
This function allows to force flush and/or invalidate of cache.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyBuffers (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
This function allows to modify physical buffer addresses.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyCachePrefetch (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_CachePrefetchTypeDef *CachePrefetch)
This function allows to modify cache and pre-fetch parameters.
void | HAL_GFXMMU_IRQHandler (GFXMMU_HandleTypeDef *hgfxmmu)
This function handles the GFXMMU interrupts.
__weak void | HAL_GFXMMU_ErrorCallback (GFXMMU_HandleTypeDef *hgfxmmu)
Error callback.
HAL_GFXMMU_StateTypeDef | HAL_GFXMMU_GetState (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU handle state.
uint32_t | HAL_GFXMMU_GetError (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU error code.

Detailed Description

Header file of GFXMMU HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_gfxmmu.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT (0x00000000U)
#define | GPIO_MODE_OUTPUT_PP (0x00000001U)
#define | GPIO_MODE_OUTPUT_OD (0x00000011U)
#define | GPIO_MODE_AF_PP (0x00000002U)
#define | GPIO_MODE_AF_OD (0x00000012U)
#define | GPIO_MODE_ANALOG (0x00000003U)
#define | GPIO_MODE_IT_RISING (0x11110000U)
#define | GPIO_MODE_IT_FALLING (0x11210000U)
#define | GPIO_MODE_IT_RISING_FALLING (0x11310000U)
#define | GPIO_MODE_EVT_RISING (0x11120000U)
#define | GPIO_MODE_EVT_FALLING (0x11220000U)
#define | GPIO_MODE_EVT_RISING_FALLING (0x11320000U)
#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)
#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_gpio.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio_ex.h File Reference

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  • STM32H7xx_HAL_Driver
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Defines
stm32h7xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define | GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define | GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define | GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define | GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#define | GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define | GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#define | GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define | GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define | GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define | GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define | GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define | GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define | GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define | GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define | GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define | GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#define | GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */
#define | GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */
#define | GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
#define | GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#define | GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
#define | GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define | GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define | GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define | GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
#define | GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define | GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define | GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define | GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define | GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */
#define | GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */
#define | GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
#define | GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#define | GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define | GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define | GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */
#define | GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define | GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define | GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#define | GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
#define | GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */
#define | GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_gpio_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_hash.h File Reference

Header file of HASH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_hash_ex.h"

Go to the source code of this file.

Data Structures

struct | HASH_InitTypeDef
HASH Configuration Structure definition. More...
struct | __HASH_HandleTypeDef
HASH Handle Structure definition. More...

Defines

#define | HASH_ALGOSELECTION_SHA1 0x00000000U
#define | HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0
#define | HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1
#define | HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO
#define | HASH_ALGOMODE_HASH 0x00000000U
#define | HASH_ALGOMODE_HMAC HASH_CR_MODE
#define | HASH_DATATYPE_32B 0x00000000U
#define | HASH_DATATYPE_16B HASH_CR_DATATYPE_0
#define | HASH_DATATYPE_8B HASH_CR_DATATYPE_1
#define | HASH_DATATYPE_1B HASH_CR_DATATYPE
#define | HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U
#define | HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY
#define | HASH_FLAG_DINIS HASH_SR_DINIS
#define | HASH_FLAG_DCIS HASH_SR_DCIS
#define | HASH_FLAG_DMAS HASH_SR_DMAS
#define | HASH_FLAG_BUSY HASH_SR_BUSY
#define | HASH_FLAG_DINNE HASH_CR_DINNE
#define | HASH_IT_DINI HASH_IMR_DINIE
#define | HASH_IT_DCI HASH_IMR_DCIE
#define | HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler
#define | HAL_HASH_ERROR_NONE 0x00000000U
#define | HAL_HASH_ERROR_IT 0x00000001U
#define | HAL_HASH_ERROR_DMA 0x00000002U
#define | HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U
#define | __HAL_HASH_GET_FLAG(__FLAG__)
Check whether or not the specified HASH flag is set.
#define | __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
Clear the specified HASH flag.
#define | __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
Enable the specified HASH interrupt.
#define | __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
Disable the specified HASH interrupt.
#define | __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__)
Reset HASH handle state.
#define | __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
Reset HASH handle status.
#define | __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
Enable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
Disable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
Start the digest computation.
#define | __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
Set the number of valid bits in the last word written in data register DIN.
#define | __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
Reset the HASH core.
#define | HASH_DIGEST_LENGTH()
Return digest length in bytes.
#define | HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
Return number of words already pushed in the FIFO.
#define | IS_HASH_DATATYPE(__DATATYPE__)
Ensure that HASH input data type is valid.
#define | IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.
#define | IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.
#define | IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__, __SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.
#define | IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
Ensure that handle phase is set to HASH processing.
#define | IS_HMAC_PROCESSING(__HANDLE__)
Ensure that handle phase is set to HMAC processing.

Typedefs

typedef struct __HASH_HandleTypeDef | HASH_HandleTypeDef
HASH Handle Structure definition.
typedef void(* | pHASH_CallbackTypeDef )(HASH_HandleTypeDef *hhash)
HAL HASH Callback pointer definition.

Enumerations

enum HAL_HASH_StateTypeDef {
HAL_HASH_STATE_RESET = 0x00U, HAL_HASH_STATE_READY = 0x01U, HAL_HASH_STATE_BUSY = 0x02U, HAL_HASH_STATE_TIMEOUT = 0x06U,
HAL_HASH_STATE_ERROR = 0x07U, HAL_HASH_STATE_SUSPENDED = 0x08U
}
HAL State structures definition. More...
enum HAL_HASH_PhaseTypeDef {
HAL_HASH_PHASE_READY = 0x01U, HAL_HASH_PHASE_PROCESS = 0x02U, HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U,
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U
}
HAL phase structures definition. More...
enum | HAL_HASH_SuspendTypeDef { HAL_HASH_SUSPEND_NONE = 0x00U, HAL_HASH_SUSPEND = 0x01U }
HAL HASH mode suspend definitions. More...
enum HAL_HASH_CallbackIDTypeDef {
HAL_HASH_MSPINIT_CB_ID = 0x00U, HAL_HASH_MSPDEINIT_CB_ID = 0x01U, HAL_HASH_INPUTCPLT_CB_ID = 0x02U, HAL_HASH_DGSTCPLT_CB_ID = 0x03U,
HAL_HASH_ERROR_CB_ID = 0x04U
}
HAL HASH common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.
HAL_StatusTypeDef | HAL_HASH_RegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
Register a User HASH Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_HASH_UnRegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
Unregister a HASH Callback HASH Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.
uint32_t | HAL_HASH_GetError (HASH_HandleTypeDef *hhash)
Return the HASH handle error code.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hash.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash_ex.h File Reference

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Functions
stm32h7xx_hal_hash_ex.h File Reference

Header file of HASH HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hash_ex.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hcd.h File Reference

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stm32h7xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

#include "stm32h7xx_ll_usb.h"

Go to the source code of this file.

Data Structures

struct | __HCD_HandleTypeDef

Defines

#define | HCD_SPEED_HIGH USBH_HS_SPEED
#define | HCD_SPEED_FULL USBH_FS_SPEED
#define | HCD_SPEED_LOW USBH_LS_SPEED
#define | HCD_PHY_ULPI 1U
#define | HCD_PHY_EMBEDDED 2U
#define | HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef
typedef struct __HCD_HandleTypeDef | HCD_HandleTypeDef
typedef void(* | pHCD_CallbackTypeDef )(HCD_HandleTypeDef *hhcd)
typedef void(* | pHCD_HC_NotifyURBChangeCallbackTypeDef )(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}
enum HAL_HCD_CallbackIDTypeDef {
HAL_HCD_SOF_CB_ID = 0x01, HAL_HCD_CONNECT_CB_ID = 0x02, HAL_HCD_DISCONNECT_CB_ID = 0x03, HAL_HCD_PORT_ENABLED_CB_ID = 0x04,
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, HAL_HCD_MSPINIT_CB_ID = 0x06, HAL_HCD_MSPDEINIT_CB_ID = 0x07
}

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hcd.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hsem.h File Reference

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Defines | Functions
stm32h7xx_hal_hsem.h File Reference

Header file of HSEM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.
#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.

Detailed Description

Header file of HSEM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hsem.h.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c.h File Reference

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stm32h7xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define | I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2c.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c_ex.h File Reference

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Defines | Functions
stm32h7xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2c_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s.h File Reference

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stm32h7xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000UL)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001UL)
#define | HAL_I2S_ERROR_OVR (0x00000002UL)
#define | HAL_I2S_ERROR_UDR (0x00000004UL)
#define | HAL_I2S_ERROR_DMA (0x00000008UL)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010UL)
#define | HAL_I2S_ERROR_FRE (0x00000020UL)
#define | HAL_I2S_ERROR_NO_OGT (0x00000040UL)
#define | HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL)
#define | I2S_MODE_SLAVE_TX (0x00000000UL)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define | I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
#define | I2S_STANDARD_PHILIPS (0x00000000UL)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | I2S_DATAFORMAT_16B (0x00000000UL)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
#define | I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
#define | I2S_AUDIOFREQ_192K (192000UL)
#define | I2S_AUDIOFREQ_96K (96000UL)
#define | I2S_AUDIOFREQ_48K (48000UL)
#define | I2S_AUDIOFREQ_44K (44100UL)
#define | I2S_AUDIOFREQ_32K (32000UL)
#define | I2S_AUDIOFREQ_22K (22050UL)
#define | I2S_AUDIOFREQ_16K (16000UL)
#define | I2S_AUDIOFREQ_11K (11025UL)
#define | I2S_AUDIOFREQ_8K (8000UL)
#define | I2S_AUDIOFREQ_DEFAULT (2UL)
#define | I2S_CPOL_LOW (0x00000000UL)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
#define | I2S_FIRSTBIT_MSB (0x00000000UL)
#define | I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
#define | I2S_WS_INVERSION_DISABLE (0x00000000UL)
#define | I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
#define | I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
#define | I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
#define | I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
#define | I2S_IT_RXP SPI_IER_RXPIE
#define | I2S_IT_TXP SPI_IER_TXPIE
#define | I2S_IT_UDR SPI_IER_UDRIE
#define | I2S_IT_OVR SPI_IER_OVRIE
#define | I2S_IT_FRE SPI_IER_TIFREIE
#define | I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
#define | I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
#define | I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
#define | I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
#define | I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
#define | I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
#define | I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the I2S UDR pending flag.
#define | __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the I2S FRE pending flag.
#define | I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_MASTER(__MODE__)
#define | IS_I2S_SLAVE(__MODE__)
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
#define | IS_I2S_FIRST_BIT(__BIT__)
#define | IS_I2S_WS_INVERSION(__WSINV__)
#define | IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__)
#define | IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__)

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00UL, HAL_I2S_STATE_READY = 0x01UL, HAL_I2S_STATE_BUSY = 0x02UL, HAL_I2S_STATE_BUSY_TX = 0x03UL,
HAL_I2S_STATE_BUSY_RX = 0x04UL, HAL_I2S_STATE_TIMEOUT = 0x06UL, HAL_I2S_STATE_ERROR = 0x07UL
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL,
HAL_I2S_ERROR_CB_ID = 0x06UL, HAL_I2S_MSPINIT_CB_ID = 0x07UL, HAL_I2S_MSPDEINIT_CB_ID = 0x08UL
}
HAL I2S Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2s.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda.h File Reference

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stm32h7xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U
#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP
#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU
#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE
#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN
#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT
#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR
#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE
#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_D2PCLK1 = 0x11U, IRDA_CLOCKSOURCE_D2PCLK2 = 0x12U, IRDA_CLOCKSOURCE_PLL2Q = 0x14U, IRDA_CLOCKSOURCE_PLL3Q = 0x18U,
IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_CSI = 0x08U, IRDA_CLOCKSOURCE_LSE = 0x10U, IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_irda.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda_ex.h File Reference

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Defines
stm32h7xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0
#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_irda_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_iwdg.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_iwdg.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_jpeg.h File Reference

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stm32h7xx_hal_jpeg.h File Reference

Header file of JPEG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | JPEG_ConfTypeDef
struct | __JPEG_HandleTypeDef

Defines

#define | HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)
#define | HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)
#define | HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)
#define | HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)
#define | JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)
#define | JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define | JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define | JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
#define | JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)
#define | JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)
#define | JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)
#define | JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)
#define | JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)
#define | JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)
#define | JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)
#define | JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)
#define | JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)
#define | JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)
#define | JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)
#define | JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)
#define | JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)
#define | JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)
#define | JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)
#define | JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)
#define | JPEG_FLAG_ALL ((uint32_t)0x000000FEU)
#define | JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)
#define | JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)
#define | JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)
#define | __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__)
Reset JPEG handle state.
#define | __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
Enable the JPEG peripheral.
#define | __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
Disable the JPEG peripheral.
#define | __HAL_JPEG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
Check the specified JPEG status flag.
#define | __HAL_JPEG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
Clear the specified JPEG status flag.
#define | __HAL_JPEG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
Enable Interrupt.
#define | __HAL_JPEG_DISABLE_IT(__HANDLE__, __INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
Disable Interrupt.
#define | __HAL_JPEG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Get Interrupt state.
#define | IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING)
#define | IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define | IS_JPEG_COLORSPACE(COLORSPACE)
#define | IS_JPEG_PAUSE_RESUME_STATE(VALUE)

Typedefs

typedef struct __JPEG_HandleTypeDef | JPEG_HandleTypeDef
typedef void(* | pJPEG_CallbackTypeDef )(JPEG_HandleTypeDef *hjpeg)
typedef void(* | pJPEG_InfoReadyCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
typedef void(* | pJPEG_GetDataCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
typedef void(* | pJPEG_DataReadyCallbackTypeDef )(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)

Enumerations

enum HAL_JPEG_STATETypeDef {
HAL_JPEG_STATE_RESET = 0x00U, HAL_JPEG_STATE_READY = 0x01U, HAL_JPEG_STATE_BUSY = 0x02U, HAL_JPEG_STATE_BUSY_ENCODING = 0x03U,
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, HAL_JPEG_STATE_TIMEOUT = 0x05U, HAL_JPEG_STATE_ERROR = 0x06U
}
enum HAL_JPEG_CallbackIDTypeDef {
HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, HAL_JPEG_ERROR_CB_ID = 0x03U, HAL_JPEG_MSPINIT_CB_ID = 0x04U,
HAL_JPEG_MSPDEINIT_CB_ID = 0x05U
}

Functions

HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.
HAL_StatusTypeDef | HAL_JPEG_RegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, pJPEG_CallbackTypeDef pCallback)
Register a User JPEG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
Unregister a JPEG Callback JPEG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_InfoReadyCallbackTypeDef pCallback)
Register Info Ready JPEG Callback To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Info Ready JPEG Callback Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
Register Get Data JPEG Callback To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Get Data JPEG Callback Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_DataReadyCallbackTypeDef pCallback)
Register Data Ready JPEG Callback To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Data Ready JPEG Callback Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.
HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.
__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.
void | HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.
HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Detailed Description

Header file of JPEG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_jpeg.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_lptim.h File Reference

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stm32h7xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U
#define | LPTIM_INPUT1SOURCE_SAI4_FSA LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_SAI4_FSB LPTIM_CFGR2_IN1SEL_1
#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_lptim.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_ltdc.h File Reference

Header file of LTDC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_ltdc_ex.h"

Go to the source code of this file.

Data Structures

struct | LTDC_ColorTypeDef
LTDC color structure definition. More...
struct | LTDC_InitTypeDef
LTDC Init structure definition. More...
struct | LTDC_LayerCfgTypeDef
LTDC Layer structure definition. More...
struct | __LTDC_HandleTypeDef
LTDC handle Structure definition. More...

Defines

#define | MAX_LAYER 2U
#define | HAL_LTDC_ERROR_NONE 0x00000000U
#define | HAL_LTDC_ERROR_TE 0x00000001U
#define | HAL_LTDC_ERROR_FU 0x00000002U
#define | HAL_LTDC_ERROR_TIMEOUT 0x00000020U
#define | HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U
#define | LTDC_LAYER_1 0x00000000U
#define | LTDC_LAYER_2 0x00000001U
#define | LTDC_HSPOLARITY_AL 0x00000000U
#define | LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL
#define | LTDC_VSPOLARITY_AL 0x00000000U
#define | LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL
#define | LTDC_DEPOLARITY_AL 0x00000000U
#define | LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL
#define | LTDC_PCPOLARITY_IPC 0x00000000U
#define | LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL
#define | LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U)
#define | LTDC_VERTICALSYNC LTDC_SSCR_VSH
#define | LTDC_COLOR 0x000000FFU
#define | LTDC_BLENDING_FACTOR1_CA 0x00000400U
#define | LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U
#define | LTDC_BLENDING_FACTOR2_CA 0x00000005U
#define | LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U
#define | LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U
#define | LTDC_PIXEL_FORMAT_RGB888 0x00000001U
#define | LTDC_PIXEL_FORMAT_RGB565 0x00000002U
#define | LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U
#define | LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U
#define | LTDC_PIXEL_FORMAT_L8 0x00000005U
#define | LTDC_PIXEL_FORMAT_AL44 0x00000006U
#define | LTDC_PIXEL_FORMAT_AL88 0x00000007U
#define | LTDC_ALPHA LTDC_LxCACR_CONSTA
#define | LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U)
#define | LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS
#define | LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL
#define | LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR
#define | LTDC_IT_LI LTDC_IER_LIE
#define | LTDC_IT_FU LTDC_IER_FUIE
#define | LTDC_IT_TE LTDC_IER_TERRIE
#define | LTDC_IT_RR LTDC_IER_RRIE
#define | LTDC_FLAG_LI LTDC_ISR_LIF
#define | LTDC_FLAG_FU LTDC_ISR_FUIF
#define | LTDC_FLAG_TE LTDC_ISR_TERRIF
#define | LTDC_FLAG_RR LTDC_ISR_RRIF
#define | LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR
#define | LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR
#define | __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__)
Reset LTDC handle state.
#define | __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
Enable the LTDC.
#define | __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
Disable the LTDC.
#define | __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
Enable the LTDC Layer.
#define | __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
Disable the LTDC Layer.
#define | __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
Reload immediately all LTDC Layers.
#define | __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
Reload during vertical blanking period all LTDC Layers.
#define | __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the LTDC pending flags.
#define | __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the LTDC pending flags.
#define | __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified LTDC interrupts.
#define | __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disables the specified LTDC interrupts.
#define | __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Check whether the specified LTDC interrupt has occurred or not.
#define | LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
#define | IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define | IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define | IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define | IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define | IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define | IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define | IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define | IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define | IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__)
#define | IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__)
#define | IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)
#define | IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define | IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define | IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define | IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Typedefs

typedef struct __LTDC_HandleTypeDef | LTDC_HandleTypeDef
LTDC handle Structure definition.
typedef void(* | pLTDC_CallbackTypeDef )(LTDC_HandleTypeDef *hltdc)
HAL LTDC Callback pointer definition.

Enumerations

enum HAL_LTDC_StateTypeDef {
HAL_LTDC_STATE_RESET = 0x00U, HAL_LTDC_STATE_READY = 0x01U, HAL_LTDC_STATE_BUSY = 0x02U, HAL_LTDC_STATE_TIMEOUT = 0x03U,
HAL_LTDC_STATE_ERROR = 0x04U
}
HAL LTDC State structures definition. More...
enum HAL_LTDC_CallbackIDTypeDef {
HAL_LTDC_MSPINIT_CB_ID = 0x00U, HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U,
HAL_LTDC_ERROR_CB_ID = 0x04U
}
HAL LTDC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.
HAL_StatusTypeDef | HAL_LTDC_RegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
Register a User LTDC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LTDC_UnRegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
Unregister an LTDC Callback LTDC callabck is redirected to the weak predefined callback.
void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.
HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

Header file of LTDC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ltdc.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdios.h File Reference

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stm32h7xx_hal_mdios.h File Reference

Header file of MDIOS HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MDIOS_InitTypeDef
struct | __MDIOS_HandleTypeDef

Defines

#define | MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define | MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
#define | MDIOS_REG0 ((uint32_t)0x00000000U)
#define | MDIOS_REG1 ((uint32_t)0x00000001U)
#define | MDIOS_REG2 ((uint32_t)0x00000002U)
#define | MDIOS_REG3 ((uint32_t)0x00000003U)
#define | MDIOS_REG4 ((uint32_t)0x00000004U)
#define | MDIOS_REG5 ((uint32_t)0x00000005U)
#define | MDIOS_REG6 ((uint32_t)0x00000006U)
#define | MDIOS_REG7 ((uint32_t)0x00000007U)
#define | MDIOS_REG8 ((uint32_t)0x00000008U)
#define | MDIOS_REG9 ((uint32_t)0x00000009U)
#define | MDIOS_REG10 ((uint32_t)0x0000000AU)
#define | MDIOS_REG11 ((uint32_t)0x0000000BU)
#define | MDIOS_REG12 ((uint32_t)0x0000000CU)
#define | MDIOS_REG13 ((uint32_t)0x0000000DU)
#define | MDIOS_REG14 ((uint32_t)0x0000000EU)
#define | MDIOS_REG15 ((uint32_t)0x0000000FU)
#define | MDIOS_REG16 ((uint32_t)0x00000010U)
#define | MDIOS_REG17 ((uint32_t)0x00000011U)
#define | MDIOS_REG18 ((uint32_t)0x00000012U)
#define | MDIOS_REG19 ((uint32_t)0x00000013U)
#define | MDIOS_REG20 ((uint32_t)0x00000014U)
#define | MDIOS_REG21 ((uint32_t)0x00000015U)
#define | MDIOS_REG22 ((uint32_t)0x00000016U)
#define | MDIOS_REG23 ((uint32_t)0x00000017U)
#define | MDIOS_REG24 ((uint32_t)0x00000018U)
#define | MDIOS_REG25 ((uint32_t)0x00000019U)
#define | MDIOS_REG26 ((uint32_t)0x0000001AU)
#define | MDIOS_REG27 ((uint32_t)0x0000001BU)
#define | MDIOS_REG28 ((uint32_t)0x0000001CU)
#define | MDIOS_REG29 ((uint32_t)0x0000001DU)
#define | MDIOS_REG30 ((uint32_t)0x0000001EU)
#define | MDIOS_REG31 ((uint32_t)0x0000001FU)
#define | MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define | MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define | MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define | MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define | MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define | MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define | MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define | MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define | MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define | MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define | MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define | MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define | MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define | MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define | MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define | MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define | MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define | MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define | MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define | MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define | MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define | MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define | MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define | MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define | MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define | MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define | MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define | MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define | MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define | MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define | MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define | MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define | MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_IT_WRITE MDIOS_CR_WRIE
#define | MDIOS_IT_READ MDIOS_CR_RDIE
#define | MDIOS_IT_ERROR MDIOS_CR_EIE
#define | MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define | MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define | MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
#define | HAL_MDIOS_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDIOS_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_MDIOS_ERROR_BUSY ((uint32_t)0x00000002U)
#define | HAL_MDIOS_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_MDIOS_ERROR_DATA ((uint32_t)0x00000010U)
#define | HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
#define | MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */
#define | __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__)
Reset MDIOS handle state.
#define | __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
Enable/Disable the MDIOS peripheral.
#define | __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
#define | __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the MDIOS device interrupt.
#define | __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the MDIOS device interrupt.
#define | __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
Set MDIOS slave get write register flag.
#define | __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
MDIOS slave get read register flag.
#define | __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
MDIOS slave get interrupt.
#define | __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
MDIOS slave clear interrupt.
#define | __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified MDIOS interrupt is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR2 |= (__EXTI_LINE__))
Enable the MDIOS WAKEUP Exti Line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR2 & (__EXTI_LINE__))
checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__))
Clear the MDIOS WAKEUP Exti flag.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U)
#define | IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U)
#define | IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__)

Typedefs

typedef struct
__MDIOS_HandleTypeDef 		MDIOS_HandleTypeDef
typedef void(* | pMDIOS_CallbackTypeDef )(MDIOS_HandleTypeDef *hmdios)
HAL MDIOS Callback pointer definition.

Enumerations

enum | HAL_MDIOS_StateTypeDef { HAL_MDIOS_STATE_RESET = 0x00U, HAL_MDIOS_STATE_READY = 0x01U, HAL_MDIOS_STATE_BUSY = 0x02U, HAL_MDIOS_STATE_ERROR = 0x04U }
enum HAL_MDIOS_CallbackIDTypeDef {
HAL_MDIOS_MSPINIT_CB_ID = 0x00U, HAL_MDIOS_MSPDEINIT_CB_ID = 0x01U, HAL_MDIOS_WRITE_COMPLETE_CB_ID = 0x02U, HAL_MDIOS_READ_COMPLETE_CB_ID = 0x03U,
HAL_MDIOS_ERROR_CB_ID = 0x04U, HAL_MDIOS_WAKEUP_CB_ID = 0x05U
}
HAL MDIOS Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.
HAL_StatusTypeDef | HAL_MDIOS_RegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
Register a User MDIOS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_MDIOS_UnRegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
Unregister an MDIOS Callback MDIOS callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.
uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error code.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

Header file of MDIOS HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mdios.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdma.h File Reference

  • File List
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stm32h7xx_hal_mdma.h File Reference

Header file of DMA HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MDMA_InitTypeDef
MDMA Configuration Structure definition. More...
struct | MDMA_LinkNodeTypeDef
HAL MDMA linked list node structure definition. More...
struct | MDMA_LinkNodeConfTypeDef
HAL MDMA linked list node configuration structure definition. More...
struct | __MDMA_HandleTypeDef
MDMA handle Structure definition. More...

Defines

#define | HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)
#define | HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)
#define | HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)
#define | HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)
#define | HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)
#define | HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)
#define | HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)
#define | MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)
#define | MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)
#define | MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)
#define | MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)
#define | MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)
#define | MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)
#define | MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)
#define | MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)
#define | MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)
#define | MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)
#define | MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)
#define | MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)
#define | MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)
#define | MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)
#define | MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)
#define | MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)
#define | MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)
#define | MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)
#define | MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)
#define | MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)
#define | MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U)
#define | MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U)
#define | MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)
#define | MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)
#define | MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)
#define | MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)
#define | MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)
#define | MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU)
#define | MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U)
#define | MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U)
#define | MDMA_REQUEST_SW ((uint32_t)0x40000000U)
#define | MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)
#define | MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)
#define | MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)
#define | MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)
#define | MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)
#define | MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)
#define | MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)
#define | MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)
#define | MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)
#define | MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)
#define | MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)
#define | MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)
#define | MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)
#define | MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)
#define | MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)
#define | MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)
#define | MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)
#define | MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)
#define | MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)
#define | MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)
#define | MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)
#define | MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)
#define | MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)
#define | MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)
#define | MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)
#define | MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)
#define | MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)
#define | MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)
#define | MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)
#define | MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)
#define | MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)
#define | MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)
#define | MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)
#define | MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)
#define | MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)
#define | MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)
#define | MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)
#define | MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)
#define | MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)
#define | __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
Enable the specified MDMA Channel.
#define | __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
Disable the specified MDMA Channel.
#define | __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
Get the MDMA Channel pending flags.
#define | __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
Clear the MDMA Stream pending flags.
#define | __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified MDMA Channel interrupt is enabled or not.
#define | IS_MDMA_LEVEL_COMPLETE(__LEVEL__)
#define | IS_MDMA_PRIORITY(__PRIORITY__)
#define | IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__)
#define | IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
#define | IS_MDMA_SOURCE_INC(__INC__)
#define | IS_MDMA_DESTINATION_INC(__INC__)
#define | IS_MDMA_SOURCE_DATASIZE(__SIZE__)
#define | IS_MDMA_DESTINATION_DATASIZE(__SIZE__)
#define | IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__)
#define | IS_MDMA_SOURCE_BURST(__BURST__)
#define | IS_MDMA_DESTINATION_BURST(__BURST__)
#define | IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__)
#define | IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
#define | IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
#define | IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
#define | IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Typedefs

typedef struct __MDMA_HandleTypeDef | MDMA_HandleTypeDef
MDMA handle Structure definition.

Enumerations

enum HAL_MDMA_StateTypeDef {
HAL_MDMA_STATE_RESET = 0x00U, HAL_MDMA_STATE_READY = 0x01U, HAL_MDMA_STATE_BUSY = 0x02U, HAL_MDMA_STATE_ERROR = 0x03U,
HAL_MDMA_STATE_ABORT = 0x04U
}
HAL MDMA State structure definition. More...
enum | HAL_MDMA_LevelCompleteTypeDef { HAL_MDMA_FULL_TRANSFER = 0x00U, HAL_MDMA_BUFFER_TRANSFER = 0x01U, HAL_MDMA_BLOCK_TRANSFER = 0x02U, HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U }
HAL MDMA Level Complete structure definition. More...
enum HAL_MDMA_CallbackIDTypeDef {
HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U,
HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, HAL_MDMA_XFER_ALL_CB_ID = 0x06U
}
HAL MDMA Callbacks IDs structure definition. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.
HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.
HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mdma.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_mmc.h File Reference

Header file of MMC HAL module. More...

#include "stm32h7xx_ll_sdmmc.h"
#include "stm32h7xx_hal_mmc_ex.h"

Go to the source code of this file.

Data Structures

struct | HAL_MMC_CardInfoTypeDef
MMC Card Information Structure definition. More...
struct | __MMC_HandleTypeDef
MMC handle Structure definition. More...
struct | HAL_MMC_CardCSDTypeDef
struct | HAL_MMC_CardCIDTypeDef

Defines

#define | HAL_MMC_CARD_READY 0x00000001U
#define | HAL_MMC_CARD_IDENTIFICATION 0x00000002U
#define | HAL_MMC_CARD_STANDBY 0x00000003U
#define | HAL_MMC_CARD_TRANSFER 0x00000004U
#define | HAL_MMC_CARD_SENDING 0x00000005U
#define | HAL_MMC_CARD_RECEIVING 0x00000006U
#define | HAL_MMC_CARD_PROGRAMMING 0x00000007U
#define | HAL_MMC_CARD_DISCONNECTED 0x00000008U
#define | HAL_MMC_CARD_ERROR 0x000000FFU
#define | MMC_InitTypeDef SDMMC_InitTypeDef
#define | MMC_TypeDef SDMMC_TypeDef
#define | MMC_BLOCKSIZE ((uint32_t)512U)
#define | HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER
#define | MMC_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | MMC_CONTEXT_IT ((uint32_t)0x00000008U)
#define | MMC_CONTEXT_DMA ((uint32_t)0x00000080U)
#define | MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U
#define | MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U
#define | eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U
#define | eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U
#define | MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
#define | MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)
#define | MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)
#define | __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)
Reset MMC handle state.
#define | __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the MMC device interrupt.
#define | __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the MMC device interrupt.
#define | __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified MMC flag is set or not.
#define | __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the MMC's pending flags.
#define | __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified MMC interrupt has occurred or not.
#define | __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the MMC's interrupt pending bits.

Typedefs

typedef uint32_t | HAL_MMC_CardStateTypeDef
typedef struct __MMC_HandleTypeDef | MMC_HandleTypeDef
MMC handle Structure definition.
typedef void(* | pMMC_CallbackTypeDef )(MMC_HandleTypeDef *hmmc)

Enumerations

enum HAL_MMC_StateTypeDef {
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU)
}
enum HAL_MMC_CallbackIDTypeDef {
HAL_MMC_TX_CPLT_CB_ID = 0x00U, HAL_MMC_RX_CPLT_CB_ID = 0x01U, HAL_MMC_ERROR_CB_ID = 0x02U, HAL_MMC_ABORT_CB_ID = 0x03U,
HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,
HAL_MMC_MSP_INIT_CB_ID = 0x10U, HAL_MMC_MSP_DEINIT_CB_ID = 0x11U
}

Functions

HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.
HAL_StatusTypeDef | HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
Register a User MMC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_MMC_UnRegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
Unregister a User MMC Callback MMC Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_MMC_ConfigSpeedBusOperation (MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_MMC_CardStateTypeDef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Detailed Description

Header file of MMC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mmc.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Enumerations | Functions
stm32h7xx_hal_mmc_ex.h File Reference

Header file of SD HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_MMCEx_DMABuffer_MemoryTypeDef { MMC_DMA_BUFFER0 = 0x00U, MMC_DMA_BUFFER1 = 0x01U }

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Header file of SD HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mmc_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nand.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_DeviceConfigTypeDef
NAND Memory info Structure definition. More...
struct | __NAND_HandleTypeDef
NAND handle Structure definition. More...

Defines

#define | __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)
Reset NAND handle state.
#define | NAND_DEVICE ((uint32_t)0x80000000U)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define | CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define | NAND_BUSY ((uint32_t)0x00000000U)
#define | NAND_ERROR ((uint32_t)0x00000001U)
#define | NAND_READY ((uint32_t)0x00000040U)
#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | COLUMN_ADDRESS(__HANDLE__) ((__HANDLE__)->Config.PageSize)
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
NAND memory Columns cycling.
#define | COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Typedefs

typedef struct __NAND_HandleTypeDef | NAND_HandleTypeDef
NAND handle Structure definition.
typedef void(* | pNAND_CallbackTypeDef )(NAND_HandleTypeDef *hnand)
HAL NAND Callback pointer definition.

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00U, HAL_NAND_STATE_READY = 0x01U, HAL_NAND_STATE_BUSY = 0x02U, HAL_NAND_STATE_ERROR = 0x03U }
HAL NAND State structures definition. More...
enum | HAL_NAND_CallbackIDTypeDef { HAL_NAND_MSP_INIT_CB_ID = 0x00U, HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, HAL_NAND_IT_CB_ID = 0x02U }
HAL NAND Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
Register a User NAND Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
Unregister a User NAND Callback NAND Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_nand.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nor.h File Reference

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stm32h7xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | __NOR_HandleTypeDef
NOR handle Structure definition. More...

Defines

#define | __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)
Reset NOR handle state.
#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x61U)
#define | CFI2_ADDRESS ((uint16_t)0x62U)
#define | CFI3_ADDRESS ((uint16_t)0x63U)
#define | CFI4_ADDRESS ((uint16_t)0x64U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Typedefs

typedef struct __NOR_HandleTypeDef | NOR_HandleTypeDef
NOR handle Structure definition.
typedef void(* | pNOR_CallbackTypeDef )(NOR_HandleTypeDef *hnor)
HAL NOR Callback pointer definition.

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00U, HAL_NOR_STATE_READY = 0x01U, HAL_NOR_STATE_BUSY = 0x02U, HAL_NOR_STATE_ERROR = 0x03U,
HAL_NOR_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...
enum | HAL_NOR_CallbackIDTypeDef { HAL_NOR_MSP_INIT_CB_ID = 0x00U, HAL_NOR_MSP_DEINIT_CB_ID = 0x01U }
HAL NOR Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
Register a User NOR Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
Unregister a User NOR Callback NOR Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_nor.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp.h File Reference

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stm32h7xx_hal_opamp.h File Reference

Header file of OPAMP HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_opamp_ex.h"

Go to the source code of this file.

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | __OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Defines

#define | OPAMP_STANDALONE_MODE 0x00000000U
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | OPAMP_NONINVERTINGINPUT_IO0 0x00000000U
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0
#define | OPAMP_NONINVERTINGINPUT_DAC2_CH OPAMP_CSR_VPSEL_1
#define | OPAMP_INVERTINGINPUT_IO0 0x00000000U
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 0x00000000U
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)
#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)
#define | OPAMP_POWERMODE_NORMAL 0x00000000U
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM
#define | OPAMP_VREF_3VDDA 0x00000000U
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL
#define | OPAMP_TRIMMING_FACTORY 0x00000000U
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU
#define | OPAMP_FACTORYTRIMMING_N 0x00000000U
#define | OPAMP_FACTORYTRIMMING_P 0x00000001U
#define | OPAMP_INPUT_NONINVERTING (8U)
#define | OPAMP_TRIMMING_DELAY (2U)
#define | __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.
#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_VREF(VREF)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Typedefs

typedef struct
__OPAMP_HandleTypeDef 		OPAMP_HandleTypeDef
OPAMP Handle Structure definition.
typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.
typedef void(* | pOPAMP_CallbackTypeDef )(OPAMP_HandleTypeDef *hopamp)
HAL OPAMP Callback pointer definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000U, HAL_OPAMP_STATE_READY = 0x00000001U, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, HAL_OPAMP_STATE_BUSY = 0x00000004U,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U
}
HAL State structures definition. More...
enum | HAL_OPAMP_CallbackIDTypeDef { HAL_OPAMP_MSPINIT_CB_ID = 0x01U, HAL_OPAMP_MSPDEINIT_CB_ID = 0x02U, HAL_OPAMP_ALL_CB_ID = 0x03U }
HAL OPAMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Header file of OPAMP HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_opamp.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp_ex.h File Reference

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Functions
stm32h7xx_hal_opamp_ex.h File Reference

Header file of OPAMP HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.
HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Header file of OPAMP HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_opamp_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ospi.h File Reference

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stm32h7xx_hal_ospi.h File Reference

Header file of OSPI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | OSPI_InitTypeDef
OSPI Init structure definition. More...
struct | __OSPI_HandleTypeDef
HAL OSPI Handle Structure definition. More...
struct | OSPI_RegularCmdTypeDef
HAL OSPI Regular Command Structure definition. More...
struct | OSPI_HyperbusCfgTypeDef
HAL OSPI Hyperbus Configuration Structure definition. More...
struct | OSPI_HyperbusCmdTypeDef
HAL OSPI Hyperbus Command Structure definition. More...
struct | OSPI_AutoPollingTypeDef
HAL OSPI Auto Polling mode configuration structure definition. More...
struct | OSPI_MemoryMappedTypeDef
HAL OSPI Memory Mapped mode configuration structure definition. More...
struct | OSPIM_CfgTypeDef
HAL OSPI IO Manager Configuration structure definition. More...

Defines

#define | HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U)
#define | HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U)
#define | HAL_OSPI_STATE_READY ((uint32_t)0x00000002U)
#define | HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U)
#define | HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U)
#define | HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U)
#define | HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U)
#define | HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U)
#define | HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U)
#define | HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U)
#define | HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U)
#define | HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U)
#define | HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U)
#define | HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
#define | HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
#define | HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U)
#define | HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
#define | HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM)
#define | HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U)
#define | HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0)
#define | HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1)
#define | HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))
#define | HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2)
#define | HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK)
#define | HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)
#define | HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE)
#define | HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U)
#define | HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)
#define | HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1))
#define | HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)
#define | HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2))
#define | HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT)
#define | HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC)
#define | HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U)
#define | HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP)
#define | HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U)
#define | HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U)
#define | HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U)
#define | HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U)
#define | HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
#define | HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL)
#define | HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0)
#define | HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1)
#define | HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))
#define | HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2)
#define | HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0)
#define | HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1)
#define | HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE)
#define | HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR)
#define | HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0)
#define | HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1)
#define | HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))
#define | HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2)
#define | HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0)
#define | HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1)
#define | HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE)
#define | HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR)
#define | HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0)
#define | HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1)
#define | HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))
#define | HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2)
#define | HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0)
#define | HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1)
#define | HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE)
#define | HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR)
#define | HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0)
#define | HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1)
#define | HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))
#define | HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2)
#define | HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR)
#define | HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE)
#define | HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)
#define | HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO)
#define | HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U)
#define | HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL)
#define | HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U)
#define | HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM)
#define | HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U)
#define | HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0)
#define | HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)
#define | HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM)
#define | HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS)
#define | HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)
#define | HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN)
#define | HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY
#define | HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF
#define | HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF
#define | HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF
#define | HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF
#define | HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF
#define | HAL_OSPI_IT_TO OCTOSPI_CR_TOIE
#define | HAL_OSPI_IT_SM OCTOSPI_CR_SMIE
#define | HAL_OSPI_IT_FT OCTOSPI_CR_FTIE
#define | HAL_OSPI_IT_TC OCTOSPI_CR_TCIE
#define | HAL_OSPI_IT_TE OCTOSPI_CR_TEIE
#define | HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
#define | HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))
#define | HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))
#define | HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))
#define | HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))
#define | HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))
#define | HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))
#define | HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))
#define | HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))
#define | HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))
#define | HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))
#define | HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))
#define | HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))
#define | HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))
#define | HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))
#define | HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))
#define | HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))
#define | __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)
Reset OSPI handle state.
#define | __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
Enable the OSPI peripheral.
#define | __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
Disable the OSPI peripheral.
#define | __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified OSPI interrupt.
#define | __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified OSPI interrupt.
#define | __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified OSPI interrupt source is enabled or not.
#define | __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
Check whether the selected OSPI flag is set or not.
#define | __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified OSPI's flag status.

Typedefs

typedef struct __OSPI_HandleTypeDef | OSPI_HandleTypeDef
HAL OSPI Handle Structure definition.
typedef void(* | pOSPI_CallbackTypeDef )(OSPI_HandleTypeDef *hospi)
HAL OSPI Callback pointer definition.

Enumerations

enum HAL_OSPI_CallbackIDTypeDef {
HAL_OSPI_ERROR_CB_ID = 0x00U, HAL_OSPI_ABORT_CB_ID = 0x01U, HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, HAL_OSPI_CMD_CPLT_CB_ID = 0x03U,
HAL_OSPI_RX_CPLT_CB_ID = 0x04U, HAL_OSPI_TX_CPLT_CB_ID = 0x05U, HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U,
HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, HAL_OSPI_TIMEOUT_CB_ID = 0x09U, HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU
}
HAL OSPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
Initialize the OSPI mode according to the specified parameters in the OSPI_InitTypeDef and initialize the associated handle.
__weak void | HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi)
Initialize the OSPI MSP.
HAL_StatusTypeDef | HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi)
De-Initialize the OSPI peripheral.
__weak void | HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi)
DeInitialize the OSPI MSP.
void | HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi)
Handle OSPI interrupt request.
HAL_StatusTypeDef | HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
Configure the Hyperbus parameters.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
Set the Hyperbus command configuration.
HAL_StatusTypeDef | HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the OSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
Configure the OSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi)
Transfer Error callback.
__weak void | HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi)
Abort completed callback.
__weak void | HAL_OSPI_FifoThresholdCallback (OSPI_HandleTypeDef *hospi)
FIFO Threshold callback.
__weak void | HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi)
Command completed callback.
__weak void | HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Transfer completed callback.
__weak void | HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Transfer completed callback.
__weak void | HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Half Transfer completed callback.
__weak void | HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Half Transfer completed callback.
__weak void | HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi)
Status Match callback.
__weak void | HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi)
Timeout callback.
HAL_StatusTypeDef | HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
Register a User OSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
Unregister a User OSPI Callback OSPI Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi)
Abort the current transmission (non-blocking function)
HAL_StatusTypeDef | HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold)
Set OSPI Fifo threshold.
uint32_t | HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi)
Get OSPI Fifo threshold.
HAL_StatusTypeDef | HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout)
Set OSPI timeout.
uint32_t | HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi)
Return the OSPI error code.
uint32_t | HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi)
Return the OSPI handle state.
HAL_StatusTypeDef | HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
Configure the OctoSPI IO manager.

Detailed Description

Header file of OSPI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ospi.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32h7xx_ll_usb.h"
#include "stm32h7xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_HIGH USBD_HS_SPEED
#define | PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
#define | PCD_SPEED_FULL USBD_FS_SPEED
#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U
#define | HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define | USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11)

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.
typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}
enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pcd.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd_ex.h File Reference

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Functions
stm32h7xx_hal_pcd_ex.h File Reference

Header file of PCD HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pcd_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pssi.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_pssi.h File Reference

Header file of PSSI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PSSI_InitTypeDef
PSSI Init structure definition. More...
struct | __PSSI_HandleTypeDef
PSSI handle Structure definition. More...

Defines

#define | HAL_PSSI_ERROR_NONE 0x00000000U
#define | HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U
#define | HAL_PSSI_ERROR_UNDER_RUN 0x00000002U
#define | HAL_PSSI_ERROR_OVER_RUN 0x00000004U
#define | HAL_PSSI_ERROR_DMA 0x00000008U
#define | HAL_PSSI_ERROR_TIMEOUT 0x00000010U
#define | HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U
#define | HAL_PSSI_8BITS 0x00000000U
#define | HAL_PSSI_16BITS 0x00000001U
#define | HAL_PSSI_32BITS 0x00000002U
#define | HAL_PSSI_8LINES 0x00000000U
#define | HAL_PSSI_16LINES PSSI_CR_EDM
#define | HAL_PSSI_UNIDIRECTIONAL 0x00000000U
#define | HAL_PSSI_BIDIRECTIONAL 0x00000001U
#define | HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos)
#define | HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U
#define | HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL
#define | HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U
#define | HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL
#define | HAL_PSSI_FALLING_EDGE 0x0U
#define | HAL_PSSI_RISING_EDGE 0x1U
#define | PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */
#define | PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU
#define | PSSI_CR_OUTEN_INPUT 0x00000000U
#define | PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN
#define | PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN
#define | PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN)
#define | PSSI_CR_16BITS PSSI_CR_EDM
#define | PSSI_CR_8BITS (~PSSI_CR_EDM)
#define | PSSI_FLAG_RTT1B PSSI_SR_RTT1B
#define | PSSI_FLAG_RTT4B PSSI_SR_RTT4B
#define | PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS
#define | PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk
#define | PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS
#define | HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__)
Reset PSSI handle state.
#define | HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
Enable the PSSI.
#define | HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
Disable the PSSI.
#define | HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
Get the PSSI pending flags.
#define | HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
Get the PSSI pending flags.
#define | HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the PSSI pending flags.
#define | HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified PSSI interrupts.
#define | HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified PSSI interrupts.
#define | HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Check whether the specified PSSI interrupt source is enabled or not.
#define | IS_PSSI_CONTROL_SIGNAL(__CONTROL__)
Check whether the PSSI Control signal is valid.
#define | IS_PSSI_BUSWIDTH(__BUSWIDTH__)
Check whether the PSSI Bus Width is valid.
#define | IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__)
Check whether the PSSI Clock Polarity is valid.
#define | IS_PSSI_DE_POLARITY(__DEPOL__)
Check whether the PSSI Data Enable Polarity is valid.
#define | IS_PSSI_RDY_POLARITY(__RDYPOL__)
Check whether the PSSI Ready Polarity is valid.

Typedefs

typedef struct __PSSI_HandleTypeDef | PSSI_HandleTypeDef
PSSI handle Structure definition.
typedef void(* | pPSSI_CallbackTypeDef )(PSSI_HandleTypeDef *hpssi)
HAL PSSI Callback pointer definition.

Enumerations

enum HAL_PSSI_StateTypeDef {
HAL_PSSI_STATE_RESET = 0x00U, HAL_PSSI_STATE_READY = 0x01U, HAL_PSSI_STATE_BUSY = 0x02U, HAL_PSSI_STATE_BUSY_TX = 0x03U,
HAL_PSSI_STATE_BUSY_RX = 0x04U, HAL_PSSI_STATE_TIMEOUT = 0x05U, HAL_PSSI_STATE_ERROR = 0x06U, HAL_PSSI_STATE_ABORT = 0x07U
}
HAL PSSI State structures definition. More...
enum HAL_PSSI_CallbackIDTypeDef {
HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, HAL_PSSI_ERROR_CB_ID = 0x03U, HAL_PSSI_ABORT_CB_ID = 0x04U,
HAL_PSSI_MSPINIT_CB_ID = 0x05U, HAL_PSSI_MSPDEINIT_CB_ID = 0x06U
}
HAL PSSI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_PSSI_Init (PSSI_HandleTypeDef *hpssi)
Initializes the PSSI according to the specified parameters in the PSSI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PSSI_DeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI peripheral.
__weak void | HAL_PSSI_MspInit (PSSI_HandleTypeDef *hpssi)
Initialize the PSSI MSP.
__weak void | HAL_PSSI_MspDeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI MSP.
HAL_StatusTypeDef | HAL_PSSI_RegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback)
Register a User PSSI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PSSI_UnRegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
Unregister an PSSI Callback PSSI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PSSI_Transmit (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Receive (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Transmit_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Receive_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Abort_DMA (PSSI_HandleTypeDef *hpssi)
Abort a DMA process communication with Interrupt.
void | HAL_PSSI_IRQHandler (PSSI_HandleTypeDef *hpssi)
This function handles PSSI event interrupt request.
__weak void | HAL_PSSI_TxCpltCallback (PSSI_HandleTypeDef *hpssi)
Tx Transfer complete callback.
__weak void | HAL_PSSI_RxCpltCallback (PSSI_HandleTypeDef *hpssi)
Rx Transfer complete callback.
__weak void | HAL_PSSI_ErrorCallback (PSSI_HandleTypeDef *hpssi)
PSSI error callback.
__weak void | HAL_PSSI_AbortCpltCallback (PSSI_HandleTypeDef *hpssi)
PSSI abort callback.
HAL_PSSI_StateTypeDef | HAL_PSSI_GetState (PSSI_HandleTypeDef *hpssi)
Return the PSSI handle state.
uint32_t | HAL_PSSI_GetError (PSSI_HandleTypeDef *hpssi)
Return the PSSI error code.

Detailed Description

Header file of PSSI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pssi.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr.h File Reference

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stm32h7xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7
#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
#define | PWR_MAINREGULATOR_ON (0U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
#define | PWR_SLEEPENTRY_WFI (0x01U)
#define | PWR_SLEEPENTRY_WFE (0x02U)
#define | PWR_STOPENTRY_WFI (0x01U)
#define | PWR_STOPENTRY_WFE (0x02U)
#define | PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
#define | PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE3 (0U)
#define | PWR_FLAG_STOP (0x01U)
#define | PWR_FLAG_SB (0x04U)
#define | PWR_FLAG_PVDO (0x0BU)
#define | PWR_FLAG_AVDO (0x0CU)
#define | PWR_FLAG_ACTVOSRDY (0x0DU)
#define | PWR_FLAG_ACTVOS (0x0EU)
#define | PWR_FLAG_BRR (0x0FU)
#define | PWR_FLAG_VOSRDY (0x10U)
#define | PWR_FLAG_SMPSEXTRDY (0x11U)
#define | PWR_FLAG_MMCVDO (0x12U)
#define | PWR_FLAG_USB33RDY (0x13U)
#define | PWR_FLAG_TEMPH (0x14U)
#define | PWR_FLAG_TEMPL (0x15U)
#define | PWR_FLAG_VBATH (0x16U)
#define | PWR_FLAG_VBATL (0x17U)
#define | PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
#define | PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
#define | PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
#define | PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
#define | PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
#define | PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
#define | PWR_EWUP_MASK (0x0FFF3F3FU)
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check PWR flags are set or not.
#define | __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
Check PWR wake up flags are set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
Clear CPU PWR flags.
#define | __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
Clear PWR wake up flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
Enable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
Disable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Rising Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Rising Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Rising & Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Rising & Falling Interrupt Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generates a Software interrupt on PVD EXTI line.
#define | PWR_EXTI_LINE_PVD EXTI_IMR1_IM16
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the event mode and the voltage threshold detected by the Programmable Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Programmable Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Programmable Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter STOP mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter the current core in SLEEP mode (CSLEEP).
void | HAL_PWR_EnterSTANDBYMode (void)
Enter STANDBY mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND feature.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pwr.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr_ex.h File Reference

  • File List
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stm32h7xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWREx_AVDTypeDef
PWREx AVD configuration structure definition. More...
struct | PWREx_WakeupPinTypeDef
PWREx Wakeup pin configuration structure definition. More...

Defines

#define | PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
#define | PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#define | PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#define | PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#define | PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define | PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
#define | PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
#define | PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
#define | PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
#define | PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
#define | PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
#define | PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
#define | PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
#define | PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
#define | PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
#define | PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
#define | PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
#define | PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
#define | PWR_PIN_POLARITY_HIGH (0x00000000U)
#define | PWR_PIN_POLARITY_LOW (0x00000001U)
#define | PWR_PIN_NO_PULL (0x00000000U)
#define | PWR_PIN_PULL_UP (0x00000001U)
#define | PWR_PIN_PULL_DOWN (0x00000002U)
#define | PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1
#define | PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2
#define | PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3
#define | PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4
#define | PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5
#define | PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6
#define | PWR_WAKEUP_FLAG_ALL
#define | PWR_D1_DOMAIN (0x00000000U)
#define | PWR_D3_DOMAIN (0x00000002U)
#define | PWR_CPU_FLAGS (0x00000000U)
#define | PWR_D3_DOMAIN_STOP (0x00000000U)
#define | PWR_D3_DOMAIN_RUN (0x00000800U)
#define | PWR_LDO_SUPPLY PWR_CR3_LDOEN
#define | PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN
#define | PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS
#define | PWR_SUPPLY_CONFIG_MASK
#define | PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
#define | PWR_AVD_MODE_NORMAL (0x00000000U)
#define | PWR_AVD_MODE_IT_RISING (0x00010001U)
#define | PWR_AVD_MODE_IT_FALLING (0x00010002U)
#define | PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)
#define | PWR_AVD_MODE_EVENT_RISING (0x00020001U)
#define | PWR_AVD_MODE_EVENT_FALLING (0x00020002U)
#define | PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)
#define | PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define | PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define | PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS
#define | PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define | PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define | PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
#define | PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define | PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define | PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
#define | PWR_EXTI_LINE_AVD EXTI_IMR1_IM16
#define | PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO
#define | PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO
#define | PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO
#define | PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO
#define | PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO
#define | PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO
#define | PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO
#define | PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO
#define | PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO
#define | PWR_MEMORY_BLOCK_KEEP_ON 0U
#define | PWR_MEMORY_BLOCK_SHUT_OFF 1U
#define | __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
Enable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
Disable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
Enable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
Disable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the AVD Extended Interrupt Rising and Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the AVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
Check whether the specified AVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
Clear the AVD EXTI flag.
#define | __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
Generates a Software interrupt on AVD EXTI line.
#define | IS_PWR_SUPPLY(PWR_SOURCE)
#define | IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)
#define | IS_PWR_DOMAIN(DOMAIN)
#define | IS_D3_STATE(STATE)
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_WAKEUP_PIN_PULL(PULL)
#define | IS_PWR_WAKEUP_FLAG(FLAG)
#define | IS_PWR_AVD_LEVEL(LEVEL)
#define | IS_PWR_AVD_MODE(MODE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
#define | IS_PWR_MEMORY_BLOCK(BLOCK)

Enumerations

enum | PWREx_MMC_VoltageLevel { PWR_MMC_VOLTAGE_BELOW_1V2, PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 }
PWR VDDMMC voltage level enum definition. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.
void | HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode with main domain in DSTOP2.
void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3/SRD Domain state when the System in low power mode.
void | HAL_PWREx_ClearPendingEvent (void)
Clear pending event.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
Enable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
Disable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin pending flags.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin pending flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.
void | HAL_PWREx_EnableAnalogBooster (void)
Enable the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2V7.
void | HAL_PWREx_DisableAnalogBooster (void)
Disable the analog booster.
void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the thresholds.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the thresholds.
PWREx_MMC_VoltageLevel | HAL_PWREx_GetMMCVoltage (void)
Get the VDDMMC voltage level.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the event mode and the voltage threshold detected by the Analog Voltage Detector (AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector (AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Header file of PWR HAL Extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pwr_ex.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ramecc.h File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_ramecc.h File Reference

Header file of RAMECC HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | __RAMECC_HandleTypeDef
RAMECC handle Structure definition. More...

Defines

#define | HAL_RAMECC_ERROR_NONE 0x00000000U
#define | HAL_RAMECC_ERROR_TIMEOUT 0x00000001U
#define | HAL_RAMECC_ERROR_BUSY 0x00000002U
#define | HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U
#define | RAMECC_IT_GLOBAL_ID 0x10000000UL
#define | RAMECC_IT_MONITOR_ID 0x20000000UL
#define | RAMECC_IT_GLOBAL_ENABLE (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE)
#define | RAMECC_IT_GLOBAL_SINGLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE)
#define | RAMECC_IT_GLOBAL_DOUBLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE)
#define | RAMECC_IT_GLOBAL_DOUBLEERR_W (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE)
#define | RAMECC_IT_GLOBAL_ALL (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE)
#define | RAMECC_IT_MONITOR_SINGLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE)
#define | RAMECC_IT_MONITOR_DOUBLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE)
#define | RAMECC_IT_MONITOR_DOUBLEERR_W (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE)
#define | RAMECC_IT_MONITOR_ALL (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE)
#define | RAMECC_FLAG_SINGLEERR_R RAMECC_SR_SEDCF
#define | RAMECC_FLAG_DOUBLEERR_R RAMECC_SR_DEDF
#define | RAMECC_FLAG_DOUBLEERR_W RAMECC_SR_DEBWDF
#define | RAMECC_FLAGS_ALL (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)
#define | __HAL_RAMECC_ENABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define | __HAL_RAMECC_ENABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
#define | __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified RAMECC interrupts.
#define | __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define | __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
#define | __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified RAMECC interrupts.
#define | __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
#define | __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
#define | __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RAMECC interrupt source is enabled or not.
#define | __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
Get the RAMECC pending flags.
#define | __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
Clear the RAMECC pending flags.
#define | __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)
Reset the RAMECC handle state.
#define | IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)
#define | IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)
#define | IS_RAMECC_INTERRUPT(INTERRUPT)

Typedefs

typedef struct
__RAMECC_HandleTypeDef 		RAMECC_HandleTypeDef
RAMECC handle Structure definition.

Enumerations

enum | HAL_RAMECC_StateTypeDef { HAL_RAMECC_STATE_RESET = 0x00U, HAL_RAMECC_STATE_READY = 0x01U, HAL_RAMECC_STATE_BUSY = 0x02U, HAL_RAMECC_STATE_ERROR = 0x03U }
HAL RAMECC State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
Initialize the RAMECC by clearing flags and disabling interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
DeInitializes the RAMECC peripheral.
HAL_StatusTypeDef | HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
Starts the RAMECC latching error information.
HAL_StatusTypeDef | HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
Stop the RAMECC latching error informations.
HAL_StatusTypeDef | HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Enable the RAMECC error interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Disable the RAMECC error interrupts.
void | HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
Handles RAMECC interrupt request.
HAL_StatusTypeDef | HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void(*pCallback)(RAMECC_HandleTypeDef *_hramecc))
Register callbacks.
HAL_StatusTypeDef | HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
UnRegister callbacks.
uint32_t | HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC failing address.
uint32_t | HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data low.
uint32_t | HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data high.
uint32_t | HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC Hamming bits injected.
uint32_t | HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC single error was occured.
uint32_t | HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC double error was occured.
HAL_RAMECC_StateTypeDef | HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral state.
uint32_t | HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral error code.

Detailed Description

Header file of RAMECC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ramecc.h.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI (0x00000008U)
#define | RCC_OSCILLATORTYPE_CSI (0x00000010U)
#define | RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
#define | RCC_HSE_OFF (0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF (0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF (0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
#define | RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
#define | RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
#define | RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value, for STM32H7 rev.V and above */
#define | RCC_HSI48_OFF ((uint8_t)0x00)
#define | RCC_HSI48_ON ((uint8_t)0x01)
#define | RCC_LSI_OFF (0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_CSI_OFF (0x00000000U)
#define | RCC_CSI_ON RCC_CR_CSION
#define | RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value */
#define | RCC_PLL_NONE (0x00000000U)
#define | RCC_PLL_OFF (0x00000001U)
#define | RCC_PLL_ON (0x00000002U)
#define | RCC_PLLSOURCE_HSI (0x00000000U)
#define | RCC_PLLSOURCE_CSI (0x00000001U)
#define | RCC_PLLSOURCE_HSE (0x00000002U)
#define | RCC_PLLSOURCE_NONE (0x00000003U)
#define | RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
#define | RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
#define | RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
#define | RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
#define | RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
#define | RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
#define | RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
#define | RCC_PLL1VCOWIDE (0x00000000U)
#define | RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
#define | RCC_CLOCKTYPE_SYSCLK (0x00000001U)
#define | RCC_CLOCKTYPE_HCLK (0x00000002U)
#define | RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
#define | RCC_CLOCKTYPE_PCLK1 (0x00000008U)
#define | RCC_CLOCKTYPE_PCLK2 (0x00000010U)
#define | RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)
#define | RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
#define | RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1
#define | RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1
#define | RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2
#define | RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4
#define | RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8
#define | RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16
#define | RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64
#define | RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128
#define | RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256
#define | RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512
#define | RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1
#define | RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2
#define | RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4
#define | RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8
#define | RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16
#define | RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1
#define | RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2
#define | RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4
#define | RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8
#define | RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16
#define | RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1
#define | RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2
#define | RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4
#define | RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8
#define | RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16
#define | RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1
#define | RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2
#define | RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4
#define | RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8
#define | RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16
#define | RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
#define | RCC_RTCCLKSOURCE_LSE (0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI (0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)
#define | RCC_MCO1 (0x00000000U)
#define | RCC_MCO2 (0x00000001U)
#define | RCC_MCO1SOURCE_HSI (0x00000000U)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
#define | RCC_MCO2SOURCE_SYSCLK (0x00000000U)
#define | RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
#define | RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
#define | RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
#define | RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
#define | RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_15 RCC_CFGR_MCO1PRE
#define | RCC_IT_LSIRDY (0x00000001U)
#define | RCC_IT_LSERDY (0x00000002U)
#define | RCC_IT_HSIRDY (0x00000004U)
#define | RCC_IT_HSERDY (0x00000008U)
#define | RCC_IT_CSIRDY (0x00000010U)
#define | RCC_IT_HSI48RDY (0x00000020U)
#define | RCC_IT_PLLRDY (0x00000040U)
#define | RCC_IT_PLL2RDY (0x00000080U)
#define | RCC_IT_PLL3RDY (0x00000100U)
#define | RCC_IT_LSECSS (0x00000200U)
#define | RCC_IT_CSS (0x00000400U)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define | RCC_FLAG_HSIDIV ((uint8_t)0x25)
#define | RCC_FLAG_CSIRDY ((uint8_t)0x28)
#define | RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
#define | RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)
#define | RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */
#define | RCC_FLAG_CDCKRDY ((uint8_t)0x2F)
#define | RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_CDRST ((uint8_t)0x93)
#define | RCC_FLAG_BORRST ((uint8_t)0x95)
#define | RCC_FLAG_PINRST ((uint8_t)0x96)
#define | RCC_FLAG_PORRST ((uint8_t)0x97)
#define | RCC_FLAG_SFTRST ((uint8_t)0x98)
#define | RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
#define | RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
#define | RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
#define | RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
#define | RCC_LSEDRIVE_LOW (0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
#define | RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
#define | RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
#define | RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
#define | __HAL_RCC_MDMA_CLK_ENABLE()
Enable or disable the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_JPGDECEN_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_OSPI1_CLK_ENABLE()
#define | __HAL_RCC_OSPI2_CLK_ENABLE()
#define | __HAL_RCC_OCTOSPIM_CLK_ENABLE()
#define | __HAL_RCC_OTFDEC1_CLK_ENABLE()
#define | __HAL_RCC_OTFDEC2_CLK_ENABLE()
#define | __HAL_RCC_GFXMMU_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
#define | __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
#define | __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
#define | __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
#define | __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
#define | __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
#define | __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
#define | __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
Get the enable or disable status of the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
#define | __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
#define | __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
#define | __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
#define | __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
#define | __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
#define | __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
#define | __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
#define | __HAL_RCC_DMA1_CLK_ENABLE()
Enable or disable the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
Get the enable or disable status of the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
#define | __HAL_RCC_DCMI_PSSI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_ENABLE()
#define | __HAL_RCC_HASH_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_SDMMC2_CLK_ENABLE()
#define | __HAL_RCC_AHBSRAM1_CLK_ENABLE()
#define | __HAL_RCC_AHBSRAM2_CLK_ENABLE()
#define | __HAL_RCC_HSEM_CLK_ENABLE()
#define | __HAL_RCC_BDMA1_CLK_ENABLE()
#define | __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
#define | __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#define | __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define | __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
#define | __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
#define | __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
#define | __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U)
Get the enable or disable status of the AHB2 peripheral clock.
#define | __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
#define | __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
#define | __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U)
#define | __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U)
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U)
#define | __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
#define | __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
#define | __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U)
#define | __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
Enable or disable the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_BDMA2_CLK_ENABLE()
#define | __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_CLK_ENABLE()
#define | __HAL_RCC_BKPRAM_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
#define | __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
#define | __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
#define | __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
Get the enable or disable status of the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U)
#define | __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
#define | __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U)
#define | __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U)
#define | __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
#define | __HAL_RCC_LTDC_CLK_ENABLE()
Enable or disable the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_CLK_ENABLE()
#define | __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
#define | __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
#define | __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)
Get the enable or disable status of the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
#define | __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)
#define | __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC12_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_MDIOS_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
#define | __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
#define | __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
Get the enable or disable status of the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
#define | __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
#define | __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
#define | __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
#define | __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
#define | __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
#define | __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_UART9_CLK_ENABLE()
#define | __HAL_RCC_USART10_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
#define | __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
#define | __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
Get the enable or disable status of the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
#define | __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
#define | __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
#define | __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
#define | __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
#define | __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
#define | __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
Enable or disable the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM3_CLK_ENABLE()
#define | __HAL_RCC_DAC2_CLK_ENABLE()
#define | __HAL_RCC_COMP12_CLK_ENABLE()
#define | __HAL_RCC_VREF_CLK_ENABLE()
#define | __HAL_RCC_RTC_CLK_ENABLE()
#define | __HAL_RCC_DTS_CLK_ENABLE()
#define | __HAL_RCC_DFSDM2_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
#define | __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
#define | __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
#define | __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
#define | __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
#define | __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
#define | __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
#define | __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
Get the enable or disable status of the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
#define | __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)
#define | __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)
#define | __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U)
#define | __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)
#define | __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)
#define | __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)
#define | __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
#define | __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)
#define | __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)
#define | __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U)
#define | __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)
#define | __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)
#define | __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)
#define | __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U)
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Enable or disable the AHB3 peripheral reset.
#define | __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
#define | __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
#define | __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
#define | __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
#define | __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
#define | __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
#define | __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
#define | __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
#define | __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Force or release the AHB1 peripheral reset.
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Force or release the AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
#define | __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
#define | __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
#define | __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
#define | __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
#define | __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
#define | __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU)
Force or release the AHB4 peripheral reset.
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
#define | __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
#define | __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/
#define | __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU)
Force or release the APB3 peripheral reset.
#define | __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)
#define | __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU)
Force or release the APB1 peripheral reset.
#define | __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
#define | __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Force or release the APB2 peripheral reset.
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
#define | __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
#define | __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU)
Force or release the APB4 peripheral reset.
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
#define | __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
#define | __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
#define | __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
#define | __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
#define | __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
#define | __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
#define | __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
#define | __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
#define | __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
#define | __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
#define | __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
#define | __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
#define | __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
#define | __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
#define | __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
#define | __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
#define | __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
#define | __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
#define | __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
#define | __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
#define | __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
#define | __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)
#define | __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U)
#define | __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U)
#define | __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U)
#define | __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U)
#define | __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)
#define | __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)
#define | __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)
#define | __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
#define | __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)
#define | __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)
#define | __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U)
#define | __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U)
#define | __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
#define | __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U)
#define | __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U)
#define | __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U)
#define | __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U)
#define | __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U)
#define | __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)
#define | __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)
#define | __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)
#define | __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)
#define | __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
#define | __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
#define | __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
#define | __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
#define | __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
#define | __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
#define | __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U)
Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
#define | __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
#define | __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
#define | __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U)
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/
#define | __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
#define | __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
#define | __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
#define | __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
#define | __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
#define | __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN))
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U)
#define | __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)
#define | __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
#define | __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
#define | __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U)
#define | __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
#define | __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)
#define | __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
#define | __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
#define | __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
#define | __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)
Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
#define | __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)
#define | __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
#define | __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
#define | __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
#define | __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
#define | __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
#define | __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
#define | __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
#define | __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
#define | __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
#define | __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
#define | __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
#define | __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)
#define | __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U)
#define | __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)
#define | __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)
#define | __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)
#define | __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)
#define | __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)
#define | __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U)
#define | __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)
#define | __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)
#define | __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)
#define | __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U)
#define | __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
#define | __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
Enable or disable peripheral bus clock when D3 domain is in DRUN.
#define | __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
#define | __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
#define | __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
#define | __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
#define | __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
#define | __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
#define | __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
#define | __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
#define | __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
#define | __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
#define | __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
#define | __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
#define | __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
#define | __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
#define | __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
#define | __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
#define | __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
#define | __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
#define | __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
#define | __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
#define | __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
#define | __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
#define | __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
#define | __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
#define | __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
#define | __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
#define | __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
#define | __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
#define | __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
#define | __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
#define | __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
#define | __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
#define | __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
#define | __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
#define | __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
#define | __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
#define | __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
#define | __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
#define | __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
#define | __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
#define | __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
#define | __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
#define | __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
#define | __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
#define | __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
#define | __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
#define | __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
#define | __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
#define | __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
#define | __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
#define | __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
#define | __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
#define | __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
#define | __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
#define | __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
#define | __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
Macro to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
Macro to get the HSI divider.
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
#define | __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
Macros to enable or disable the Internal oscillator (CSI).
#define | __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
#define | __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)
Macro Adjusts the Internal oscillator (CSI) calibration value.
#define | __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
#define | __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.
#define | __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
Macro to configures the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLLs clock source.
#define | __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
Macro to configure the MCO2 clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
Macro to configure the Kernel wake up from stop clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
#define | RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms */
#define | CSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | RCC_DBP_TIMEOUT_VALUE (100U)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI)
#define | IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
#define | IS_RCC_PLL(PLL)
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
#define | IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLLCLOCKOUT_VALUE(VALUE)
#define | IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_SYSCLK(SYSCLK)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CDPCLK1(CDPCLK1)
#define | IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */
#define | IS_RCC_PCLK1(PCLK1)
#define | IS_RCC_PCLK2(PCLK2)
#define | IS_RCC_SRDPCLK1(SRDPCLK1)
#define | IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
#define | IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
#define | IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define | IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rcc.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLL2InitTypeDef
PLL2 Clock structure definition. More...
struct | RCC_PLL3InitTypeDef
PLL3 Clock structure definition. More...
struct | PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition. More...
struct | PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition. More...
struct | PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...

Defines

#define | RCC_PERIPHCLK_USART16910 (0x00000001U)
#define | RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
#define | RCC_PERIPHCLK_USART234578 (0x00000002U)
#define | RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
#define | RCC_PERIPHCLK_LPUART1 (0x00000004U)
#define | RCC_PERIPHCLK_I2C123 (0x00000008U)
#define | RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
#define | RCC_PERIPHCLK_I2C4 (0x00000010U)
#define | RCC_PERIPHCLK_LPTIM1 (0x00000020U)
#define | RCC_PERIPHCLK_LPTIM2 (0x00000040U)
#define | RCC_PERIPHCLK_LPTIM345 (0x00000080U)
#define | RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
#define | RCC_PERIPHCLK_SAI1 (0x00000100U)
#define | RCC_PERIPHCLK_SAI2A (0x00000200U)
#define | RCC_PERIPHCLK_SAI2B (0x00000400U)
#define | RCC_PERIPHCLK_SPI123 (0x00001000U)
#define | RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
#define | RCC_PERIPHCLK_SPI45 (0x00002000U)
#define | RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
#define | RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
#define | RCC_PERIPHCLK_SPI6 (0x00004000U)
#define | RCC_PERIPHCLK_FDCAN (0x00008000U)
#define | RCC_PERIPHCLK_SDMMC (0x00010000U)
#define | RCC_PERIPHCLK_RNG (0x00020000U)
#define | RCC_PERIPHCLK_USB (0x00040000U)
#define | RCC_PERIPHCLK_ADC (0x00080000U)
#define | RCC_PERIPHCLK_SWPMI1 (0x00100000U)
#define | RCC_PERIPHCLK_DFSDM1 (0x00200000U)
#define | RCC_PERIPHCLK_DFSDM2 (0x00000800U)
#define | RCC_PERIPHCLK_RTC (0x00400000U)
#define | RCC_PERIPHCLK_CEC (0x00800000U)
#define | RCC_PERIPHCLK_FMC (0x01000000U)
#define | RCC_PERIPHCLK_OSPI (0x02000000U)
#define | RCC_PERIPHCLK_DSI (0x04000000U)
#define | RCC_PERIPHCLK_SPDIFRX (0x08000000U)
#define | RCC_PERIPHCLK_LTDC (0x20000000U)
#define | RCC_PERIPHCLK_TIM (0x40000000U)
#define | RCC_PERIPHCLK_CKPER (0x80000000U)
#define | RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
#define | RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
#define | RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
#define | RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
#define | RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
#define | RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
#define | RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
#define | RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
#define | RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
#define | RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
#define | RCC_PLL2VCOWIDE (0x00000000U)
#define | RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
#define | RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
#define | RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
#define | RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
#define | RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
#define | RCC_PLL3VCOWIDE (0x00000000U)
#define | RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
#define | RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
#define | RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
#define | RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0
#define | RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1
#define | RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
#define | RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2
#define | RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
#define | RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
#define | RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
#define | RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
#define | RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
#define | RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
#define | RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
#define | RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
#define | RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
#define | RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
#define | RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
#define | RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
#define | RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
#define | RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
#define | RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
#define | RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
#define | RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
#define | RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
#define | RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0
#define | RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1
#define | RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
#define | RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2
#define | RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
#define | RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
#define | RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
#define | RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
#define | RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
#define | RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
#define | RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
#define | RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4
#define | RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4
#define | RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
#define | RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
#define | RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
#define | RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
#define | RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
#define | RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
#define | RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
#define | RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
#define | RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define | RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define | RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define | RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
#define | RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4
#define | RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1
#define | RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
#define | RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
#define | RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0
#define | RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1
#define | RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL
#define | RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL
#define | RCC_SAI1CLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
#define | RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2
#define | RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0
#define | RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1
#define | RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
#define | RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
#define | RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
#define | RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
#define | RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0
#define | RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1
#define | RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
#define | RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2
#define | RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
#define | RCC_SPI123CLKSOURCE_PLL (0x00000000U)
#define | RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0
#define | RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1
#define | RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
#define | RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2
#define | RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
#define | RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
#define | RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
#define | RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
#define | RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
#define | RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
#define | RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
#define | RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
#define | RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
#define | RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
#define | RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
#define | RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
#define | RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2
#define | RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
#define | RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
#define | RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
#define | RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
#define | RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
#define | RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
#define | RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
#define | RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
#define | RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
#define | RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
#define | RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
#define | RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
#define | RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
#define | RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
#define | RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4
#define | RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0
#define | RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1
#define | RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
#define | RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2
#define | RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
#define | RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
#define | RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
#define | RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
#define | RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2
#define | RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
#define | RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2
#define | RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
#define | RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define | RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0
#define | RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1
#define | RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
#define | RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2
#define | RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
#define | RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
#define | RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
#define | RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
#define | RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
#define | RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
#define | RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
#define | RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
#define | RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
#define | RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK
#define | RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
#define | RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
#define | RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL
#define | RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)
#define | RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK
#define | RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK
#define | RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0
#define | RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1
#define | RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL
#define | RCC_FDCANCLKSOURCE_HSE (0x00000000U)
#define | RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1
#define | RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
#define | RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL
#define | RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
#define | RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1
#define | RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL
#define | RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)
#define | RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1
#define | RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL
#define | RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)
#define | RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4
#define | RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL
#define | RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
#define | RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0
#define | RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1
#define | RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL
#define | RCC_CECCLKSOURCE_LSE (0x00000000U)
#define | RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0
#define | RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1
#define | RCC_CLKPSOURCE_HSI (0x00000000U)
#define | RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0
#define | RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1
#define | RCC_TIMPRES_DESACTIVATED (0x00000000U)
#define | RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
#define | RCC_WWDG1 RCC_GCR_WW1RSC
#define | RCC_CRS_NONE (0x00000000U)
#define | RCC_CRS_TIMEOUT (0x00000001U)
#define | RCC_CRS_SYNCOK (0x00000002U)
#define | RCC_CRS_SYNCWARN (0x00000004U)
#define | RCC_CRS_SYNCERR (0x00000008U)
#define | RCC_CRS_SYNCMISS (0x00000010U)
#define | RCC_CRS_TRIMOVF (0x00000020U)
#define | RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
#define | RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)
#define | RCC_CRS_SYNC_DIV1 (0x00000000U)
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
#define | RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)
#define | RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)
#define | RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)
#define | RCC_CRS_FREQERRORDIR_UP (0x00000000U)
#define | RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)
#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
#define | IS_RCC_PLL2CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_PLL3CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_USART16CLKSOURCE(SOURCE)
#define | IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE
#define | IS_RCC_USART234578CLKSOURCE(SOURCE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_UART9CLKSOURCE(SOURCE)
#define | IS_RCC_USART10CLKSOURCE(SOURCE)
#define | IS_RCC_LPUART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C123CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_RNGCLKSOURCE(SOURCE)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2ACLK(__SOURCE__)
#define | IS_RCC_SAI2BCLK(__SOURCE__)
#define | IS_RCC_SPI123CLK(__SOURCE__)
#define | IS_RCC_SPI1CLK(__SOURCE__)
#define | IS_RCC_SPI2CLK(__SOURCE__)
#define | IS_RCC_SPI3CLK(__SOURCE__)
#define | IS_RCC_SPI45CLK(__SOURCE__)
#define | IS_RCC_SPI4CLK(__SOURCE__)
#define | IS_RCC_SPI5CLK(__SOURCE__)
#define | IS_RCC_SPI6CLK(__SOURCE__)
#define | IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
#define | IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#define | IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
#define | IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
#define | IS_RCC_PLL2RGE_VALUE(VALUE)
#define | IS_RCC_PLL3RGE_VALUE(VALUE)
#define | IS_RCC_PLL2VCO_VALUE(VALUE)
#define | IS_RCC_PLL3VCO_VALUE(VALUE)
#define | IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_LPTIM2CLK(SOURCE)
#define | IS_RCC_LPTIM345CLK(SOURCE)
#define | IS_RCC_LPTIM3CLK(SOURCE)
#define | IS_RCC_OSPICLK(__SOURCE__)
#define | IS_RCC_FMCCLK(__SOURCE__)
#define | IS_RCC_FDCANCLK(__SOURCE__)
#define | IS_RCC_SDMMC(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(SOURCE)
#define | IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM2CLKSOURCE(SOURCE)
#define | IS_RCC_SPDIFRXCLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_CLKPSOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)
#define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
Macros to enable or disable PLL2.
#define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
#define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
#define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
#define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
#define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
Macros to enable or disable the main PLL3.
#define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
#define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
#define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
#define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
#define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
Macro to Configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
Macro to Configure the SPDIFRX clock source.
#define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
Macro to get the SPDIFRX clock source.
#define | __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
Macro to Configure the SAI2A clock source.
#define | __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
Macro to get the SAI2A clock source.
#define | __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
Macro to Configure the SAI2B clock source.
#define | __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
Macro to get the SAI2B clock source.
#define | __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
macro to configure the I2C1/2/3 clock (I2C123CLK).
#define | __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
macro to get the I2C1/2/3 clock source.
#define | __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
macro to configure the USART1/6/9* /10* clock (USART16CLK).
#define | __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
#define | __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
macro to get the USART1/6/9* /10* clock source.
#define | __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
#define | __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
macro to configure the USART234578 clock (USART234578CLK).
#define | __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
macro to get the USART2/3/4/5/7/8 clock source.
#define | __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART5 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
macro to get the UART8 clock source.
#define | __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the UART9 clock (UART9CLK).
#define | __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the UART9 clock source.
#define | __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
macro to configure the USART10 clock (USART10CLK).
#define | __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
macro to get the USART10 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
macro to configure the LPTIM1 clock source.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
macro to configure the LPTIM2 clock source.
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
macro to configure the LPTIM3/4/5 clock source.
#define | __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
macro to get the LPTIM3/4/5 clock source.
#define | __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
macro to configure the LPTIM3 clock source.
#define | __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
macro to configure the OSPI clock source.
#define | __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
macro to get the OSPI clock source.
#define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
macro to configure the FMC clock source.
#define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
macro to get the FMC clock source.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
Macro to configure the ADC clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.
#define | __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
Macro to configure the DFSDM2 clock.
#define | __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
Macro to get the DFSDM2 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
Macro to configure the CLKP : Oscillator clock for peripheral.
#define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
Macro to get the Oscillator clock for peripheral source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
Macro to configure the FDCAN clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
Macro to get the FDCAN clock.
#define | __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
Macro to Configure the SPI1/2/3 clock source.
#define | __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
Macro to get the SPI1/2/3 clock source.
#define | __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI1 clock source.
#define | __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI1 clock source.
#define | __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI2 clock source.
#define | __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI2 clock source.
#define | __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
Macro to Configure the SPI3 clock source.
#define | __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
Macro to get the SPI3 clock source.
#define | __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
Macro to Configure the SPI4/5 clock source.
#define | __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
Macro to get the SPI4/5 clock source.
#define | __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
Macro to Configure the SPI4 clock source.
#define | __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
Macro to get the SPI4 clock source.
#define | __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
Macro to Configure the SPI5 clock source.
#define | __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
Macro to get the SPI5 clock source.
#define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
Macro to Configure the SPI6 clock source.
#define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
Macro to get the SPI6 clock source.
#define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
Macro to configure the SDMMC clock.
#define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
Macro to get the SDMMC clock.
#define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
macro to configure the RNG clock (RNGCLK).
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
macro to get the RNG clock source.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rcc_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng.h File Reference

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stm32h7xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rng_ex.h"

Go to the source code of this file.

Data Structures

struct | RNG_InitTypeDef
struct | __RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED
#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}
enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rng.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng_ex.h File Reference

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stm32h7xx_hal_rng_ex.h File Reference

Header file of RNG HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_ConfigTypeDef
RNGEX Configuration Structure definition. More...

Defines

#define | RNG_CLKDIV_BY_1 (0x00000000UL)
#define | RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
#define | RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
#define | RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
#define | RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | RNG_NIST_COMPLIANT (0x00000000UL)
#define | RNG_CUSTOM_NIST (RNG_CR_NISTC)
#define | IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__)
#define | IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__)
#define | IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
#define | IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
#define | IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

Functions

HAL_StatusTypeDef | HAL_RNGEx_SetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Configure the RNG with the specified parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_GetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Get the RNG Configuration and fill parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_LockConfig (RNG_HandleTypeDef *hrng)
RNG current configuration lock.

Detailed Description

Header file of RNG HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rng_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc.h File Reference

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stm32h7xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 0x00000000u
#define | RTC_HOURFORMAT_12 RTC_CR_FMT
#define | RTC_OUTPUT_DISABLE 0x00000000u
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000u
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | RTC_ALARM_OUTPUT_TYPE RTC_CR_TAMPALRM_TYPE
#define | RTC_OUTPUT_PULLUP_NONE 0x00000000u
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
#define | RTC_OUTPUT_REMAP_NONE 0x00000000u
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x01)
#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000u
#define | RTC_STOREOPERATION_RESET 0x00000000u
#define | RTC_STOREOPERATION_SET RTC_CR_BKP
#define | RTC_FORMAT_BIN 0x00000000u
#define | RTC_FORMAT_BCD 0x00000001u
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | RTC_ALARMMASK_NONE 0x00000000u
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000u
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE
#define | RTC_FLAG_RECALPF RTC_ICSR_RECALPF
#define | RTC_FLAG_INITF RTC_ICSR_INITF
#define | RTC_FLAG_RSF RTC_ICSR_RSF
#define | RTC_FLAG_INITS RTC_ICSR_INITS
#define | RTC_FLAG_SHPF RTC_ICSR_SHPF
#define | RTC_FLAG_WUTWF RTC_ICSR_WUTWF
#define | RTC_FLAG_ALRBWF RTC_ICSR_ALRBWF
#define | RTC_FLAG_ALRAWF RTC_ICSR_ALRAWF
#define | RTC_FLAG_ITSF RTC_SR_ITSF
#define | RTC_FLAG_TSOVF RTC_SR_TSOVF
#define | RTC_FLAG_TSF RTC_SR_TSF
#define | RTC_FLAG_WUTF RTC_SR_WUTF
#define | RTC_FLAG_ALRBF RTC_SR_ALRBF
#define | RTC_FLAG_ALRAF RTC_SR_ALRAF
#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK 0xFFFFFFFFu
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_TIMEOUT_VALUE 1000u
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u,
HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12u,
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 13u, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 14u, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 15u, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 16u,
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 17u, HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 19u, HAL_RTC_MSPINIT_CB_ID = 20u, HAL_RTC_MSPDEINIT_CB_ID = 21u
}
HAL RTC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rtc.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
struct | RTC_InternalTamperTypeDef
struct | RTC_ATampInputTypeDef
struct | RTC_ActiveTampersTypeDef

Defines

#define | RTC_ATAMP_SEED_NB_UINT32 4U
#define | RTC_TAMP_NB 3u
#define | BKP_REG_NUMBER TAMP_BKP_NUMBER
#define | RTC_BKP_DR0 0x00u
#define | RTC_BKP_DR1 0x01u
#define | RTC_BKP_DR2 0x02u
#define | RTC_BKP_DR3 0x03u
#define | RTC_BKP_DR4 0x04u
#define | RTC_BKP_DR5 0x05u
#define | RTC_BKP_DR6 0x06u
#define | RTC_BKP_DR7 0x07u
#define | RTC_BKP_DR8 0x08u
#define | RTC_BKP_DR9 0x09u
#define | RTC_BKP_DR10 0x0Au
#define | RTC_BKP_DR11 0x0Bu
#define | RTC_BKP_DR12 0x0Cu
#define | RTC_BKP_DR13 0x0Du
#define | RTC_BKP_DR14 0x0Eu
#define | RTC_BKP_DR15 0x0Fu
#define | RTC_BKP_DR16 0x10u
#define | RTC_BKP_DR17 0x11u
#define | RTC_BKP_DR18 0x12u
#define | RTC_BKP_DR19 0x13u
#define | RTC_BKP_DR20 0x14u
#define | RTC_BKP_DR21 0x15u
#define | RTC_BKP_DR22 0x16u
#define | RTC_BKP_DR23 0x17u
#define | RTC_BKP_DR24 0x18u
#define | RTC_BKP_DR25 0x19u
#define | RTC_BKP_DR26 0x1Au
#define | RTC_BKP_DR27 0x1Bu
#define | RTC_BKP_DR28 0x1Cu
#define | RTC_BKP_DR29 0x1Du
#define | RTC_BKP_DR30 0x1Eu
#define | RTC_BKP_DR31 0x1Fu
#define | RTC_TIMESTAMPEDGE_RISING 0x00000000u
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
#define | RTC_TIMESTAMPPIN_DEFAULT 0x00000000u
#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)
#define | RTC_IT_TAMP1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMP 0x00000000u
#define | RTC_IT_TAMPALL (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)
#define | RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E
#define | RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E
#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E
#define | RTC_INT_TAMPER_ALL
#define | RTC_INTERNAL_TAMPER1_INTERRUPT TAMP_IER_ITAMP1IE
#define | RTC_INTERNAL_TAMPER2_INTERRUPT TAMP_IER_ITAMP2IE
#define | RTC_INTERNAL_TAMPER3_INTERRUPT TAMP_IER_ITAMP3IE
#define | RTC_INTERNAL_TAMPER4_INTERRUPT TAMP_IER_ITAMP4IE
#define | RTC_INTERNAL_TAMPER5_INTERRUPT TAMP_IER_ITAMP5IE
#define | RTC_INTERNAL_TAMPER6_INTERRUPT TAMP_IER_ITAMP6IE
#define | RTC_INTERNAL_TAMPER8_INTERRUPT TAMP_IER_ITAMP8IE
#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x01u
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x02u
#define | RTC_TAMPERTRIGGER_LOWLEVEL 0x04u
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x08u
#define | RTC_TAMPER_1_TRIGGER TAMP_CR2_TAMP1TRG
#define | RTC_TAMPER_2_TRIGGER TAMP_CR2_TAMP2TRG
#define | RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG
#define | RTC_TAMPER_X_TRIGGER
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 TAMP_CR2_TAMP1NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE
#define | RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK
#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00u
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01u
#define | RTC_TAMPER_1_MASK_FLAG TAMP_CR2_TAMP1MSK
#define | RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK
#define | RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK
#define | RTC_TAMPER_X_MASK_FLAG
#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | RTC_TAMPERFILTER_MASK TAMP_FLTCR_TAMPFLT
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 TAMP_FLTCR_TAMPFREQ
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
#define | RTC_TAMPERPRECHARGEDURATION_MASK TAMP_FLTCR_TAMPPRCH
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS
#define | RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_CR_TAMPTS
#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000u
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS
#define | RTC_TAMPER_PULLUP_MASK TAMP_FLTCR_TAMPPUDIS
#define | RTC_TAMPERDETECTIONOUTPUT_DISABLE 0x00000000u
#define | RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE
#define | RTC_FLAG_TAMP1F TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP2F TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP3F TAMP_SR_TAMP3F
#define | RTC_ATAMP_ENABLE 1u
#define | RTC_ATAMP_DISABLE 0u
#define | RTC_ATAMP_INTERRUPT_ENABLE 1u
#define | RTC_ATAMP_INTERRUPT_DISABLE 0u
#define | RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN
#define | RTC_ATAMP_FILTER_DISABLE 0u
#define | RTC_ATAMP_ASYNCPRES_RTCCLK 0u
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
#define | RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | RTC_ATAMP_1 0u
#define | RTC_ATAMP_2 1u
#define | RTC_ATAMP_3 2u
#define | RTC_ATAMP_4 3u
#define | RTC_ATAMP_5 4u
#define | RTC_ATAMP_6 5u
#define | RTC_ATAMP_7 6u
#define | RTC_ATAMP_8 7u
#define | TAMP_OFFSET (TAMP_BASE - RTC_BASE)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u
#define | RTC_CALIBOUTPUT_512HZ 0x00000000u
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
#define | RTC_SHIFTADD1S_RESET 0x00000000u
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
Get the frequency at which each of the Tamper inputs are sampled.
#define | __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))
Get the number of consecutive samples at the specified level needed to activate a Tamper event.
#define | __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
Get the pull-up resistors precharge duration.
#define | __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))
Get the pull-up resistors status.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__) ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
Get activation status of the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT() (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG() (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG() (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated D3 Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR1_IM18
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19
#define | RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))
#define | RTC_TAMPER_X_INTERRUPT ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3))
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < BKP_REG_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__)
#define | IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
__weak void | HAL_RTCEx_InternalTamper1EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 1 callback.
__weak void | HAL_RTCEx_InternalTamper2EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 2 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
__weak void | HAL_RTCEx_InternalTamper8EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 8 callback.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveTampers (RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper)
Set all active Tampers at the same time.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveSeed (RTC_HandleTypeDef *hrtc, uint32_t *pSeed)
Write a new seed.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateActiveTampers (RTC_HandleTypeDef *hrtc)
Deactivate all Active Tampers at the same time.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterIncrement (RTC_HandleTypeDef *hrtc)
Increment Monotonic counter.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterGet (RTC_HandleTypeDef *hrtc, uint32_t *Counter)
Monotonic counter incrementation.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Header file of RTC HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rtc_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_sai_ex.h"

Go to the source code of this file.

Data Structures

struct | SAI_PdmInitTypeDef
struct | SAI_InitTypeDef
struct | SAI_FrameInitTypeDef
struct | SAI_SlotInitTypeDef
struct | __SAI_HandleTypeDef

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U
#define | SAI_SYNCEXT_DISABLE 0U
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U
#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U
#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U
#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U
#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U
#define | SAI_SYNCHRONOUS_EXT_SAI1 2U
#define | SAI_SYNCHRONOUS_EXT_SAI2 3U
#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU
#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO
#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE
#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET
#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.
#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sai.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai_ex.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions
stm32h7xx_hal_sai_ex.h File Reference

Header file of SAI HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...

Defines

#define | IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

Header file of SAI HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sai_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd.h File Reference

  • File List
  • Globals
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  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_sd.h File Reference

Header file of SD HAL module. More...

#include "stm32h7xx_ll_sdmmc.h"
#include "stm32h7xx_ll_delayblock.h"
#include "stm32h7xx_hal_sd_ex.h"

Go to the source code of this file.

Data Structures

struct | HAL_SD_CardInfoTypeDef
SD Card Information Structure definition. More...
struct | __SD_HandleTypeDef
SD handle Structure definition. More...
struct | HAL_SD_CardCSDTypeDef
struct | HAL_SD_CardCIDTypeDef
struct | HAL_SD_CardStatusTypeDef

Defines

#define | HAL_SD_CARD_READY 0x00000001U
#define | HAL_SD_CARD_IDENTIFICATION 0x00000002U
#define | HAL_SD_CARD_STANDBY 0x00000003U
#define | HAL_SD_CARD_TRANSFER 0x00000004U
#define | HAL_SD_CARD_SENDING 0x00000005U
#define | HAL_SD_CARD_RECEIVING 0x00000006U
#define | HAL_SD_CARD_PROGRAMMING 0x00000007U
#define | HAL_SD_CARD_DISCONNECTED 0x00000008U
#define | HAL_SD_CARD_ERROR 0x000000FFU
#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef
#define | BLOCKSIZE ((uint32_t)512U)
#define | HAL_SD_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_SD_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER
#define | SD_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | SD_CONTEXT_IT ((uint32_t)0x00000008U)
#define | SD_CONTEXT_DMA ((uint32_t)0x00000080U)
#define | CARD_NORMAL_SPEED ((uint32_t)0x00000000U)
#define | CARD_HIGH_SPEED ((uint32_t)0x00000100U)
#define | CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)
#define | CARD_SDSC ((uint32_t)0x00000000U)
#define | CARD_SDHC_SDXC ((uint32_t)0x00000001U)
#define | CARD_SECURED ((uint32_t)0x00000003U)
#define | CARD_V1_X ((uint32_t)0x00000000U)
#define | CARD_V2_X ((uint32_t)0x00000001U)
#define | __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)
Reset SD handle state.
#define | __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Typedefs

typedef uint32_t | HAL_SD_CardStateTypeDef
typedef struct __SD_HandleTypeDef | SD_HandleTypeDef
SD handle Structure definition.
typedef void(* | pSD_CallbackTypeDef )(SD_HandleTypeDef *hsd)
typedef void(* | pSD_TransceiverCallbackTypeDef )(FlagStatus status)

Enumerations

enum HAL_SD_StateTypeDef {
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), HAL_SD_STATE_READY = ((uint32_t)0x00000001U), HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU)
}
enum HAL_SD_CallbackIDTypeDef {
HAL_SD_TX_CPLT_CB_ID = 0x00U, HAL_SD_RX_CPLT_CB_ID = 0x01U, HAL_SD_ERROR_CB_ID = 0x02U, HAL_SD_ABORT_CB_ID = 0x03U,
HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,
HAL_SD_MSP_INIT_CB_ID = 0x10U, HAL_SD_MSP_DEINIT_CB_ID = 0x11U
}

Functions

HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransceiver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transceiver 1.8V Mode Callback.
HAL_StatusTypeDef | HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
Register a User SD Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
Unregister a User SD Callback SD Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
Register a User SD Transceiver Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterTransceiverCallback (SD_HandleTypeDef *hsd)
Unregister a User SD Transceiver Callback SD Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_SD_ConfigSpeedBusOperation (SD_HandleTypeDef *hsd, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_SD_CardStateTypeDef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sd.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd_ex.h File Reference

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stm32h7xx_hal_sd_ex.h File Reference

Header file of SD HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_SDEx_DMABuffer_MemoryTypeDef { SD_DMA_BUFFER0 = 0x00U, SD_DMA_BUFFER1 = 0x01U }

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Header file of SD HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sd_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sdram.h File Reference

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stm32h7xx_hal_sdram.h File Reference

Header file of SDRAM HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | __SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Defines

#define | __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)
Reset SDRAM handle state.

Typedefs

typedef struct
__SDRAM_HandleTypeDef 		SDRAM_HandleTypeDef
SDRAM handle Structure definition.
typedef void(* | pSDRAM_CallbackTypeDef )(SDRAM_HandleTypeDef *hsdram)
HAL SDRAM Callback pointer definition.
typedef void(* | pSDRAM_DmaCallbackTypeDef )(MDMA_HandleTypeDef *hmdma)

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00U, HAL_SDRAM_STATE_READY = 0x01U, HAL_SDRAM_STATE_BUSY = 0x02U, HAL_SDRAM_STATE_ERROR = 0x03U,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, HAL_SDRAM_STATE_PRECHARGED = 0x05U
}
HAL SDRAM State structure definition. More...
enum HAL_SDRAM_CallbackIDTypeDef {
HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U,
HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U
}
HAL SDRAM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
Register a User SDRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
Unregister a User SDRAM Callback SDRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_RegisterDmaCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
Register a User SDRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Header file of SDRAM HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sdram.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard.h File Reference

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stm32h7xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U
#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | SMARTCARD_WORDLENGTH_9B USART_CR1_M0
#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP
#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL
#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA
#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK
#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_D2PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_D2PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x04U, SMARTCARD_CLOCKSOURCE_CSI = 0x08U,
SMARTCARD_CLOCKSOURCE_LSE = 0x20U, SMARTCARD_CLOCKSOURCE_PLL2Q = 0x40U, SMARTCARD_CLOCKSOURCE_PLL3Q = 0x80U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smartcard.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard_ex.h File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U
#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smartcard_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smbus.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | __SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smbus.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spdifrx.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_spdifrx.h File Reference

Header file of SPDIFRX HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | __SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)
#define | HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)
#define | IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE))

Typedefs

typedef struct
__SPDIFRX_HandleTypeDef 		SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition.
typedef void(* | pSPDIFRX_CallbackTypeDef )(SPDIFRX_HandleTypeDef *hspdif)
HAL SPDIFRX Callback pointer definition.

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00U, HAL_SPDIFRX_STATE_READY = 0x01U, HAL_SPDIFRX_STATE_BUSY = 0x02U, HAL_SPDIFRX_STATE_BUSY_RX = 0x03U,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, HAL_SPDIFRX_STATE_ERROR = 0x07U
}
HAL State structures definition. More...
enum HAL_SPDIFRX_CallbackIDTypeDef {
HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U,
HAL_SPDIFRX_ERROR_CB_ID = 0x04U, HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U
}
HAL SPDIFRX Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_RegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
Register a User SPDIFRX Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_UnRegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
Unregister a SPDIFRX Callback SPDIFRX callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX error code.

Detailed Description

Header file of SPDIFRX HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spdifrx.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | SPI_LOWEND_FIFO_SIZE 8UL
#define | SPI_HIGHEND_FIFO_SIZE 16UL
#define | HAL_SPI_ERROR_NONE (0x00000000UL)
#define | HAL_SPI_ERROR_MODF (0x00000001UL)
#define | HAL_SPI_ERROR_CRC (0x00000002UL)
#define | HAL_SPI_ERROR_OVR (0x00000004UL)
#define | HAL_SPI_ERROR_FRE (0x00000008UL)
#define | HAL_SPI_ERROR_DMA (0x00000010UL)
#define | HAL_SPI_ERROR_FLAG (0x00000020UL)
#define | HAL_SPI_ERROR_ABORT (0x00000040UL)
#define | HAL_SPI_ERROR_UDR (0x00000080UL)
#define | HAL_SPI_ERROR_TIMEOUT (0x00000100UL)
#define | HAL_SPI_ERROR_UNKNOW (0x00000200UL)
#define | HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL)
#define | SPI_MODE_SLAVE (0x00000000UL)
#define | SPI_MODE_MASTER SPI_CFG2_MASTER
#define | SPI_DIRECTION_2LINES (0x00000000UL)
#define | SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
#define | SPI_DIRECTION_1LINE SPI_CFG2_COMM
#define | SPI_DATASIZE_4BIT (0x00000003UL)
#define | SPI_DATASIZE_5BIT (0x00000004UL)
#define | SPI_DATASIZE_6BIT (0x00000005UL)
#define | SPI_DATASIZE_7BIT (0x00000006UL)
#define | SPI_DATASIZE_8BIT (0x00000007UL)
#define | SPI_DATASIZE_9BIT (0x00000008UL)
#define | SPI_DATASIZE_10BIT (0x00000009UL)
#define | SPI_DATASIZE_11BIT (0x0000000AUL)
#define | SPI_DATASIZE_12BIT (0x0000000BUL)
#define | SPI_DATASIZE_13BIT (0x0000000CUL)
#define | SPI_DATASIZE_14BIT (0x0000000DUL)
#define | SPI_DATASIZE_15BIT (0x0000000EUL)
#define | SPI_DATASIZE_16BIT (0x0000000FUL)
#define | SPI_DATASIZE_17BIT (0x00000010UL)
#define | SPI_DATASIZE_18BIT (0x00000011UL)
#define | SPI_DATASIZE_19BIT (0x00000012UL)
#define | SPI_DATASIZE_20BIT (0x00000013UL)
#define | SPI_DATASIZE_21BIT (0x00000014UL)
#define | SPI_DATASIZE_22BIT (0x00000015UL)
#define | SPI_DATASIZE_23BIT (0x00000016UL)
#define | SPI_DATASIZE_24BIT (0x00000017UL)
#define | SPI_DATASIZE_25BIT (0x00000018UL)
#define | SPI_DATASIZE_26BIT (0x00000019UL)
#define | SPI_DATASIZE_27BIT (0x0000001AUL)
#define | SPI_DATASIZE_28BIT (0x0000001BUL)
#define | SPI_DATASIZE_29BIT (0x0000001CUL)
#define | SPI_DATASIZE_30BIT (0x0000001DUL)
#define | SPI_DATASIZE_31BIT (0x0000001EUL)
#define | SPI_DATASIZE_32BIT (0x0000001FUL)
#define | SPI_POLARITY_LOW (0x00000000UL)
#define | SPI_POLARITY_HIGH SPI_CFG2_CPOL
#define | SPI_PHASE_1EDGE (0x00000000UL)
#define | SPI_PHASE_2EDGE SPI_CFG2_CPHA
#define | SPI_NSS_SOFT SPI_CFG2_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000UL)
#define | SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
#define | SPI_NSS_PULSE_DISABLE (0x00000000UL)
#define | SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
#define | SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
#define | SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
#define | SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
#define | SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
#define | SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
#define | SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
#define | SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
#define | SPI_FIRSTBIT_MSB (0x00000000UL)
#define | SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
#define | SPI_TIMODE_DISABLE (0x00000000UL)
#define | SPI_TIMODE_ENABLE SPI_CFG2_SP_0
#define | SPI_CRCCALCULATION_DISABLE (0x00000000UL)
#define | SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
#define | SPI_CRC_LENGTH_4BIT (0x00030000UL)
#define | SPI_CRC_LENGTH_5BIT (0x00040000UL)
#define | SPI_CRC_LENGTH_6BIT (0x00050000UL)
#define | SPI_CRC_LENGTH_7BIT (0x00060000UL)
#define | SPI_CRC_LENGTH_8BIT (0x00070000UL)
#define | SPI_CRC_LENGTH_9BIT (0x00080000UL)
#define | SPI_CRC_LENGTH_10BIT (0x00090000UL)
#define | SPI_CRC_LENGTH_11BIT (0x000A0000UL)
#define | SPI_CRC_LENGTH_12BIT (0x000B0000UL)
#define | SPI_CRC_LENGTH_13BIT (0x000C0000UL)
#define | SPI_CRC_LENGTH_14BIT (0x000D0000UL)
#define | SPI_CRC_LENGTH_15BIT (0x000E0000UL)
#define | SPI_CRC_LENGTH_16BIT (0x000F0000UL)
#define | SPI_CRC_LENGTH_17BIT (0x00100000UL)
#define | SPI_CRC_LENGTH_18BIT (0x00110000UL)
#define | SPI_CRC_LENGTH_19BIT (0x00120000UL)
#define | SPI_CRC_LENGTH_20BIT (0x00130000UL)
#define | SPI_CRC_LENGTH_21BIT (0x00140000UL)
#define | SPI_CRC_LENGTH_22BIT (0x00150000UL)
#define | SPI_CRC_LENGTH_23BIT (0x00160000UL)
#define | SPI_CRC_LENGTH_24BIT (0x00170000UL)
#define | SPI_CRC_LENGTH_25BIT (0x00180000UL)
#define | SPI_CRC_LENGTH_26BIT (0x00190000UL)
#define | SPI_CRC_LENGTH_27BIT (0x001A0000UL)
#define | SPI_CRC_LENGTH_28BIT (0x001B0000UL)
#define | SPI_CRC_LENGTH_29BIT (0x001C0000UL)
#define | SPI_CRC_LENGTH_30BIT (0x001D0000UL)
#define | SPI_CRC_LENGTH_31BIT (0x001E0000UL)
#define | SPI_CRC_LENGTH_32BIT (0x001F0000UL)
#define | SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
#define | SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
#define | SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
#define | SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
#define | SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
#define | SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
#define | SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
#define | SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
#define | SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
#define | SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
#define | SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
#define | SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
#define | SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
#define | SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
#define | SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
#define | SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
#define | SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
#define | SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
#define | SPI_NSS_POLARITY_LOW (0x00000000UL)
#define | SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
#define | SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
#define | SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
#define | SPI_IO_SWAP_DISABLE (0x00000000UL)
#define | SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
#define | SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
#define | SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
#define | SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
#define | SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
#define | SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
#define | SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
#define | SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
#define | SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
#define | SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
#define | SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
#define | SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
#define | SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
#define | SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
#define | SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
#define | SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
#define | SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
#define | SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
#define | SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
#define | SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
#define | SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
#define | SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
#define | SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
#define | SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
#define | SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
#define | SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
#define | SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
#define | SPI_IT_RXP SPI_IER_RXPIE
#define | SPI_IT_TXP SPI_IER_TXPIE
#define | SPI_IT_DXP SPI_IER_DXPIE
#define | SPI_IT_EOT SPI_IER_EOTIE
#define | SPI_IT_TXTF SPI_IER_TXTFIE
#define | SPI_IT_UDR SPI_IER_UDRIE
#define | SPI_IT_OVR SPI_IER_OVRIE
#define | SPI_IT_CRCERR SPI_IER_CRCEIE
#define | SPI_IT_FRE SPI_IER_TIFREIE
#define | SPI_IT_MODF SPI_IER_MODFIE
#define | SPI_IT_TSERF SPI_IER_TSERFIE
#define | SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
#define | SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
#define | SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
#define | SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
#define | SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
#define | SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
#define | SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
#define | SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
#define | SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
#define | SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
#define | SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
#define | SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
#define | SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
#define | SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
#define | SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
#define | SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
#define | SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
Clear the SPI EOT pending flag.
#define | __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
Clear the SPI SUSP pending flag.
#define | __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
Clear the SPI TSERF pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
Set the SPI receive-only mode.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_FIFOTHRESHOLD(THRESHOLD)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
#define | IS_SPI_UNDERRUN_DETECTION(MODE)
#define | IS_SPI_UNDERRUN_BEHAVIOUR(MODE)

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00UL, HAL_SPI_STATE_READY = 0x01UL, HAL_SPI_STATE_BUSY = 0x02UL, HAL_SPI_STATE_BUSY_TX = 0x03UL,
HAL_SPI_STATE_BUSY_RX = 0x04UL, HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, HAL_SPI_STATE_ERROR = 0x06UL, HAL_SPI_STATE_ABORT = 0x07UL
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, HAL_SPI_ERROR_CB_ID = 0x06UL, HAL_SPI_ABORT_CB_ID = 0x07UL,
HAL_SPI_MSPINIT_CB_ID = 0x08UL, HAL_SPI_MSPDEINIT_CB_ID = 0x09UL
}
HAL SPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spi.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi_ex.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuration register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spi_ex.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sram.h File Reference

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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | __SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Defines

#define | __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)
Reset SRAM handle state.

Typedefs

typedef struct __SRAM_HandleTypeDef | SRAM_HandleTypeDef
SRAM handle Structure definition.
typedef void(* | pSRAM_CallbackTypeDef )(SRAM_HandleTypeDef *hsram)
HAL SRAM Callback pointer definition.
typedef void(* | pSRAM_DmaCallbackTypeDef )(MDMA_HandleTypeDef *hmdma)

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00U, HAL_SRAM_STATE_READY = 0x01U, HAL_SRAM_STATE_BUSY = 0x02U, HAL_SRAM_STATE_ERROR = 0x03U,
HAL_SRAM_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_SRAM_CallbackIDTypeDef { HAL_SRAM_MSP_INIT_CB_ID = 0x00U, HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U }
HAL SRAM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
Register a User SRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
Unregister a User SRAM Callback SRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_RegisterDmaCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
Register a User SRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sram.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_swpmi.h File Reference

  • File List
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_swpmi.h File Reference

Header file of SWPMI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | __SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)
#define | HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040)
#define | HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080)
#define | HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100)
#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define | SWPMI_FLAG_RDYF SWPMI_ISR_RDYF
#define | SWPMI_IT_RDYIE SWPMI_IER_RDYIE
#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Enable the SWPMI transceiver.
#define | __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Disable the SWPMI transceiver.
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.
#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Typedefs

typedef struct
__SWPMI_HandleTypeDef 		SWPMI_HandleTypeDef
SWPMI handle Structure definition.
typedef void(* | pSWPMI_CallbackTypeDef )(SWPMI_HandleTypeDef *hswpmi)
SWPMI callback pointer definition.

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...
enum HAL_SWPMI_CallbackIDTypeDef {
HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U, HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U, HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SWPMI_ERROR_CB_ID = 0x04U, HAL_SWPMI_MSPINIT_CB_ID = 0x05U, HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U
}
SWPMI callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_RegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID, pSWPMI_CallbackTypeDef pCallback)
Register a user SWPMI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SWPMI_UnRegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID)
Unregister a user SWPMI callback.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

Header file of SWPMI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_swpmi.h.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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stm32h7xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_TISEL 0x00000020U
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U
#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U
#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U
#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE
#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U
#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE
#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF
#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4
#define | TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
#define | TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
#define | TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U
#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U
#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U
#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ITR4 (TIM_SMCR_TS_3)
#define | TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR12 (TIM_SMCR_TS_4)
#define | TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)
#define | TIM_TS_NONE 0x0000FFFFU
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U
#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_tim.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define | TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define | TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define | TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
#define | TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
#define | TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define | TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define | TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define | TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define | TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define | TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define | TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define | TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define | TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define | TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define | TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
#define | TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
#define | TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
#define | TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */
#define | TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */
#define | TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define | TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
#define | TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
#define | TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
#define | TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */
#define | TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */
#define | TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */
#define | TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */
#define | TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */
#define | TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */
#define | TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__)
#define | IS_TIM_REMAP(__RREMAP__)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_tim_ex.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart.h File Reference

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stm32h7xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U
#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE
#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8
#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE
#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN
#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL
#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT
#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR
#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL
#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE
#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM
#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME
#define | UART_CR2_ADDRESS_LSB_POS 24U
#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS
#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP
#define | UART_CR1_DEAT_ADDRESS_LSB_POS 21U
#define | UART_CR1_DEDT_ADDRESS_LSB_POS 16U
#define | UART_IT_MASK 0x001FU
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE
#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_D2PCLK1 = 0x00U, UART_CLOCKSOURCE_D2PCLK2 = 0x01U, UART_CLOCKSOURCE_D3PCLK1 = 0x02U, UART_CLOCKSOURCE_PLL2 = 0x04U,
UART_CLOCKSOURCE_PLL3 = 0x08U, UART_CLOCKSOURCE_HSI = 0x10U, UART_CLOCKSOURCE_CSI = 0x20U, UART_CLOCKSOURCE_LSE = 0x40U,
UART_CLOCKSOURCE_UNDEFINED = 0x80U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_uart.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart_ex.h File Reference

  • File List
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  • Firmware
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions
stm32h7xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0
#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_uart_ex.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1
#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | USART_OVERSAMPLING_16 0x00000000U
#define | USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL
#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA
#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL
#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU
#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE
#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_D2PCLK1 = 0x00U, USART_CLOCKSOURCE_D2PCLK2 = 0x01U, USART_CLOCKSOURCE_PLL2 = 0x02U, USART_CLOCKSOURCE_PLL3 = 0x04U,
USART_CLOCKSOURCE_HSI = 0x08U, USART_CLOCKSOURCE_CSI = 0x10U, USART_CLOCKSOURCE_LSE = 0x20U, USART_CLOCKSOURCE_UNDEFINED = 0x40U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_usart.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart_ex.h File Reference

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stm32h7xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS
#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN
#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_usart_ex.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_wwdg.h File Reference

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stm32h7xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00u, HAL_WWDG_MSPINIT_CB_ID = 0x01u }
HAL WWDG common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_wwdg.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_adc.h File Reference

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stm32h7xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
#define | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
#define | ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
#define | ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
#define | ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
#define | ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
#define | LL_ADC_AWD1_TR LL_ADC_AWD1
#define | LL_ADC_AWD2_TR LL_ADC_AWD2
#define | LL_ADC_AWD3_TR LL_ADC_AWD3
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define | ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
#define | ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
#define | ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
#define | ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
#define | ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
#define | ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
#define | ADC_LINEAR_CALIB_REG_COUNT (6UL)
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
#define | LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL)
#define | LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0)
#define | LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 )
#define | LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 )
#define | LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)
#define | LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)
#define | LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
#define | LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN)
#define | LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1)
#define | LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2)
#define | LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3)
#define | LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4)
#define | LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5)
#define | LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6)
#define | LL_ADC_RESOLUTION_16B (0x00000000UL)
#define | LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)
#define | LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)
#define | LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)
#define | LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
#define | LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
#define | LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE)
#define | LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1)
#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
#define | LL_ADC_REG_DR_TRANSFER (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0)
#define | LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 )
#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)
#define | LL_ADC_AWD_THRESHOLD_LOW (0x0UL)
#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define | LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
#define | LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 )
#define | LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US (5UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
#define | ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 16 bits.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__)
Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCalibrationOffsetFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationOffsetFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetCalibrationLinearFactor (ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
Set ADC Linear calibration factor in the mode single-ended.
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationLinearFactor (ADC_TypeDef *ADCx, uint32_t LinearityWord)
Get ADC Linear calibration factor in the mode single-ended.
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetDataRightShift (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
Set data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE uint32_t | LL_ADC_GetDataRightShift (ADC_TypeDef *ADCx, uint32_t Offsety)
Get data right shift for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE void | LL_ADC_SetOffsetSignedSaturation (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
Set signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSignedSaturation (ADC_TypeDef *ADCx, uint32_t Offsety)
Get signed saturation for the ADC selected offset number 1, 2, 3 or 4: signed offset saturation if enabled or disabled.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDataTransferMode (ADC_TypeDef *ADCx, uint32_t DataTransferMode)
Set ADC data transfer mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDataTransferMode (ADC_TypeDef *ADCx)
Get ADC data transfer mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)
__STATIC_INLINE void | LL_ADC_SetBoostMode (ADC_TypeDef *ADCx, uint32_t BoostMode)
Set ADC boost mode.
__STATIC_INLINE uint32_t | LL_ADC_GetBoostMode (ADC_TypeDef *ADCx)
Get ADC boost mode.
__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.
__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData16 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 16 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData14 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 14 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData16 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 16 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData14 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 14 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.
__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_adc.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bdma.h File Reference

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stm32h7xx_ll_bdma.h File Reference

Header file of BDMA LL module. More...

#include "stm32h7xx.h"
#include "stm32h7xx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | LL_BDMA_InitTypeDef

Defines

#define | LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1
#define | LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1
#define | LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1
#define | LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1
#define | LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2
#define | LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2
#define | LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2
#define | LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2
#define | LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3
#define | LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3
#define | LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3
#define | LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3
#define | LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4
#define | LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4
#define | LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4
#define | LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4
#define | LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5
#define | LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5
#define | LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5
#define | LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5
#define | LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6
#define | LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6
#define | LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6
#define | LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6
#define | LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7
#define | LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7
#define | LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7
#define | LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7
#define | LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0
#define | LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0
#define | LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0
#define | LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0
#define | LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1
#define | LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1
#define | LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1
#define | LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1
#define | LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2
#define | LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2
#define | LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2
#define | LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2
#define | LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3
#define | LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3
#define | LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3
#define | LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3
#define | LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4
#define | LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4
#define | LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4
#define | LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4
#define | LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5
#define | LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5
#define | LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5
#define | LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5
#define | LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6
#define | LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6
#define | LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6
#define | LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6
#define | LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7
#define | LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7
#define | LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7
#define | LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7
#define | LL_BDMA_CCR_TCIE BDMA_CCR_TCIE
#define | LL_BDMA_CCR_HTIE BDMA_CCR_HTIE
#define | LL_BDMA_CCR_TEIE BDMA_CCR_TEIE
#define | LL_BDMA_CHANNEL_0 0x00000000U
#define | LL_BDMA_CHANNEL_1 0x00000001U
#define | LL_BDMA_CHANNEL_2 0x00000002U
#define | LL_BDMA_CHANNEL_3 0x00000003U
#define | LL_BDMA_CHANNEL_4 0x00000004U
#define | LL_BDMA_CHANNEL_5 0x00000005U
#define | LL_BDMA_CHANNEL_6 0x00000006U
#define | LL_BDMA_CHANNEL_7 0x00000007U
#define | LL_BDMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR
#define | LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM
#define | LL_BDMA_MODE_NORMAL 0x00000000U
#define | LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC
#define | LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
#define | LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM
#define | LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC
#define | LL_BDMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC
#define | LL_BDMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_BDMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0
#define | LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1
#define | LL_BDMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0
#define | LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1
#define | LL_BDMA_PRIORITY_LOW 0x00000000U
#define | LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0
#define | LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1
#define | LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL
#define | LL_BDMA_CURRENTTARGETMEM0 0x00000000U
#define | LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT
#define | LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in BDMA register.
#define | LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in BDMA register.
#define | __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
Convert BDMAx_Channely into BDMAx.
#define | __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert BDMAx_Channely into LL_BDMA_CHANNEL_y.
#define | __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)
Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely.

Functions

__STATIC_INLINE void | LL_BDMA_EnableChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable BDMA channel.
__STATIC_INLINE void | LL_BDMA_DisableChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable BDMA channel.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledChannel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if BDMA channel is enabled or disabled.
__STATIC_INLINE void | LL_BDMA_ConfigTransfer (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to BDMA transfer.
__STATIC_INLINE void | LL_BDMA_SetDataTransferDirection (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_BDMA_GetDataTransferDirection (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_BDMA_SetMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
Set BDMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_BDMA_GetMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get BDMA mode circular or normal.
__STATIC_INLINE void | LL_BDMA_SetPeriphIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_BDMA_SetMemoryIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemoryIncMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_BDMA_SetPeriphSize (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphSize (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_BDMA_SetMemorySize (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemorySize (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_BDMA_SetChannelPriorityLevel (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_BDMA_GetChannelPriorityLevel (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_BDMA_SetDataLength (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_BDMA_GetDataLength (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_BDMA_SetCurrentTargetMem (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE uint32_t | LL_BDMA_GetCurrentTargetMem (BDMA_TypeDef *BDMAx, uint32_t Channel)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE void | LL_BDMA_EnableDoubleBufferMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable the double buffer mode.
__STATIC_INLINE void | LL_BDMA_DisableDoubleBufferMode (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable the double buffer mode.
__STATIC_INLINE void | LL_BDMA_ConfigAddresses (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_BDMA_SetMemoryAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_BDMA_SetPeriphAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_BDMA_GetMemoryAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_BDMA_SetM2MSrcAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_BDMA_SetM2MDstAddress (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_BDMA_GetM2MSrcAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_BDMA_GetM2MDstAddress (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_BDMA_SetMemory1Address (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
Set Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE uint32_t | LL_BDMA_GetMemory1Address (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE void | LL_BDMA_SetPeriphRequest (BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
Set BDMA request for BDMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_BDMA_GetPeriphRequest (BDMA_TypeDef *BDMAx, uint32_t Channel)
Get BDMA request for BDMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI0 (BDMA_TypeDef *BDMAx)
Get Channel 0 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI1 (BDMA_TypeDef *BDMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI2 (BDMA_TypeDef *BDMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI3 (BDMA_TypeDef *BDMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI4 (BDMA_TypeDef *BDMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI5 (BDMA_TypeDef *BDMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI6 (BDMA_TypeDef *BDMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_GI7 (BDMA_TypeDef *BDMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC0 (BDMA_TypeDef *BDMAx)
Get Channel 0 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC1 (BDMA_TypeDef *BDMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC2 (BDMA_TypeDef *BDMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC3 (BDMA_TypeDef *BDMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC4 (BDMA_TypeDef *BDMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC5 (BDMA_TypeDef *BDMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC6 (BDMA_TypeDef *BDMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TC7 (BDMA_TypeDef *BDMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT0 (BDMA_TypeDef *BDMAx)
Get Channel 0 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT1 (BDMA_TypeDef *BDMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT2 (BDMA_TypeDef *BDMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT3 (BDMA_TypeDef *BDMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT4 (BDMA_TypeDef *BDMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT5 (BDMA_TypeDef *BDMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT6 (BDMA_TypeDef *BDMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_HT7 (BDMA_TypeDef *BDMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE0 (BDMA_TypeDef *BDMAx)
Get Channel 0 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE1 (BDMA_TypeDef *BDMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE2 (BDMA_TypeDef *BDMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE3 (BDMA_TypeDef *BDMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE4 (BDMA_TypeDef *BDMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE5 (BDMA_TypeDef *BDMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE6 (BDMA_TypeDef *BDMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_BDMA_IsActiveFlag_TE7 (BDMA_TypeDef *BDMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_GI7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TC7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_HT7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE0 (BDMA_TypeDef *BDMAx)
Clear Channel 0 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE1 (BDMA_TypeDef *BDMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE2 (BDMA_TypeDef *BDMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE3 (BDMA_TypeDef *BDMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE4 (BDMA_TypeDef *BDMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE5 (BDMA_TypeDef *BDMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE6 (BDMA_TypeDef *BDMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_BDMA_ClearFlag_TE7 (BDMA_TypeDef *BDMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_BDMA_EnableIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_BDMA_EnableIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_BDMA_EnableIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_BDMA_DisableIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_TC (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_HT (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_BDMA_IsEnabledIT_TE (BDMA_TypeDef *BDMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
uint32_t | LL_BDMA_Init (BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
uint32_t | LL_BDMA_DeInit (BDMA_TypeDef *BDMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_BDMA_StructInit (LL_BDMA_InitTypeDef *BDMA_InitStruct)
Set each LL_BDMA_InitTypeDef field to default value.

Variables

static const uint8_t | LL_BDMA_CH_OFFSET_TAB []

Detailed Description

Header file of BDMA LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_bdma.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bus.h File Reference

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Defines | Functions
stm32h7xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
#define | LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
#define | LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
#define | LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define | LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
#define | LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
#define | LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
#define | LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
#define | LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
#define | LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN
#define | LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
#define | LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
#define | LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
#define | LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
#define | LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN
#define | LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
#define | LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
#define | LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
#define | LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
#define | LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
#define | LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define | LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
#define | LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
#define | LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN
#define | LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/
#define | LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN
#define | LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/
#define | LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
#define | LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
#define | LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
#define | LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
#define | LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
#define | LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
#define | LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
#define | LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
#define | LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
#define | LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
#define | LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
#define | LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN
#define | LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/
#define | LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
#define | LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN
#define | LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
#define | LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
#define | LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
#define | LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
#define | LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
#define | LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
#define | LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
#define | LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
#define | LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
#define | LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
#define | LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
#define | LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
#define | LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
#define | LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
#define | LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
#define | LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
#define | LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
#define | LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
#define | LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
#define | LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define | LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
#define | LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
#define | LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
#define | LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
#define | LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
#define | LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
#define | LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
#define | LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
#define | LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN
#define | LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
#define | LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
#define | LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
#define | LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
#define | LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN
#define | LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
#define | LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
#define | LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
#define | LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
#define | LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN
#define | LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN
#define | LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN
#define | LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
#define | LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN
#define | LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN
#define | LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN
#define | LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN
#define | LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
#define | LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
#define | LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN
#define | LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN
#define | LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM
#define | LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG
#define | LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG
#define | LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG
#define | LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG
#define | LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG
#define | LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG
#define | LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG
#define | LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG
#define | LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG
#define | LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG
#define | LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG
#define | LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG
#define | LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG
#define | LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG
#define | LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG
#define | LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG
#define | LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG
#define | LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG
#define | LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG
#define | LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG
#define | LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG

Functions

__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB4_GRP1_EnableClock (uint32_t Periphs)
Enable AHB4 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB4_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB4 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB4_GRP1_DisableClock (uint32_t Periphs)
Disable AHB4 peripherals clock.
__STATIC_INLINE void | LL_AHB4_GRP1_ForceReset (uint32_t Periphs)
Force AHB4 peripherals reset.
__STATIC_INLINE void | LL_AHB4_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB4 peripherals reset.
__STATIC_INLINE void | LL_AHB4_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB4_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB3_GRP1_EnableClock (uint32_t Periphs)
Enable APB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB3_GRP1_DisableClock (uint32_t Periphs)
Disable APB3 peripherals clock.
__STATIC_INLINE void | LL_APB3_GRP1_ForceReset (uint32_t Periphs)
Force APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_ReleaseReset (uint32_t Periphs)
Release APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB4_GRP1_EnableClock (uint32_t Periphs)
Enable APB4 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB4_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB4 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB4_GRP1_DisableClock (uint32_t Periphs)
Disable APB4 peripherals clock.
__STATIC_INLINE void | LL_APB4_GRP1_ForceReset (uint32_t Periphs)
Force APB4 peripherals reset.
__STATIC_INLINE void | LL_APB4_GRP1_ReleaseReset (uint32_t Periphs)
Release APB4 peripherals reset.
__STATIC_INLINE void | LL_APB4_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB4_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_CLKAM_Enable (uint32_t Periphs)
Enable peripherals clock for CLKAM Mode.
__STATIC_INLINE void | LL_CLKAM_Disable (uint32_t Periphs)
Disable peripherals clock for CLKAM Mode.
__STATIC_INLINE void | LL_CKGA_Enable (uint32_t Periphs)
Enable clock gating for AXI bus peripherals.
__STATIC_INLINE void | LL_CKGA_Disable (uint32_t Periphs)
Disable clock gating for AXI bus peripherals.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_bus.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_comp.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)
#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE_1 | COMP_CFGRx_PWRMODE_0)
#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)
#define | LL_COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 )
#define | LL_COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 )
#define | LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 )
#define | LL_COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 )
#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CFGRx_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST_1 | COMP_CFGRx_HYST_0)
#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)
#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)
#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | LL_COMP_AF_PA6 COMP_OR_AFOPA6
#define | LL_COMP_AF_PA8 COMP_OR_AFOPA8
#define | LL_COMP_AF_PB12 COMP_OR_AFOPB12
#define | LL_COMP_AF_PE6 COMP_OR_AFOPE6
#define | LL_COMP_AF_PE15 COMP_OR_AFOPE15
#define | LL_COMP_AF_PG2 COMP_OR_AFOPG2
#define | LL_COMP_AF_PG3 COMP_OR_AFOPG3
#define | LL_COMP_AF_PG4 COMP_OR_AFOPG4
#define | LL_COMP_AF_PI1 COMP_OR_AFOPI1
#define | LL_COMP_AF_PI4 COMP_OR_AFOPI4
#define | LL_COMP_AF_PK2 COMP_OR_AFOPK2
#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.
#define | __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.
__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_SetOutputAlternateFunction (COMP_TypeDef *COMPx, uint32_t CompAFx)
Set the output alternate function in the Option register in order to be used with the alternate function of the timer break input.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputAlternateFunction (COMP_TypeDef *COMPx)
Get the output alternate function from the Option register.
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_comp.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_cortex.h File Reference

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Defines | Functions
stm32h7xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 0x00UL
#define | LL_MPU_REGION_NUMBER1 0x01UL
#define | LL_MPU_REGION_NUMBER2 0x02UL
#define | LL_MPU_REGION_NUMBER3 0x03UL
#define | LL_MPU_REGION_NUMBER4 0x04UL
#define | LL_MPU_REGION_NUMBER5 0x05UL
#define | LL_MPU_REGION_NUMBER6 0x06UL
#define | LL_MPU_REGION_NUMBER7 0x07UL
#define | LL_MPU_REGION_NUMBER8 0x08UL
#define | LL_MPU_REGION_NUMBER9 0x09UL
#define | LL_MPU_REGION_NUMBER10 0x0AUL
#define | LL_MPU_REGION_NUMBER11 0x0BUL
#define | LL_MPU_REGION_NUMBER12 0x0CUL
#define | LL_MPU_REGION_NUMBER13 0x0DUL
#define | LL_MPU_REGION_NUMBER14 0x0EUL
#define | LL_MPU_REGION_NUMBER15 0x0FUL
#define | LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos)
#define | LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos)
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_cortex.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crc.h File Reference

  • File List
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Defines | Functions
stm32h7xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_crc.h.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crs.h File Reference

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Defines | Functions
stm32h7xx_ll_crs.h File Reference

CRS LL module driver. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV
#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR
#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
Reset value of the HSI48 Calibration field.
#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.
#define | __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.
__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.
ErrorStatus | LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Detailed Description

CRS LL module driver.

Header file of CRS LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_crs.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dac.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...

Defines

#define | DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
#define | LL_DAC_TRIG_SOFTWARE 0x00000000U
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
#define | LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
#define | LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
#define | LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
#define | LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
#define | LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
#define | LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
#define | LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
#define | LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
#define | LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
#define | LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
#define | LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
#define | LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL
#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL
#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.
#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.
ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dac.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_delayblock.h File Reference

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stm32h7xx_ll_delayblock.h File Reference

Header file of Delay Block module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DLYB_MAX_UNIT ((uint32_t)0x00000080U)
#define | DLYB_MAX_SELECT ((uint32_t)0x0000000CU)

Functions

HAL_StatusTypeDef | DelayBlock_Enable (DLYB_TypeDef *DLYBx)
Enable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Disable (DLYB_TypeDef *DLYBx)
Disable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Configure (DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units)
Configure the Delay Block instance.

Detailed Description

Header file of Delay Block module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_delayblock.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma.h File Reference

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Data Structures | Defines | Functions | Variables
stm32h7xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32h7xx.h"
#include "stm32h7xx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
Helper macro to convert DMA Instance DMAx into DMAMUX channel.
#define | LL_DMA_STREAM_0 0x00000000U
#define | LL_DMA_STREAM_1 0x00000001U
#define | LL_DMA_STREAM_2 0x00000002U
#define | LL_DMA_STREAM_3 0x00000003U
#define | LL_DMA_STREAM_4 0x00000004U
#define | LL_DMA_STREAM_5 0x00000005U
#define | LL_DMA_STREAM_6 0x00000006U
#define | LL_DMA_STREAM_7 0x00000007U
#define | LL_DMA_STREAM_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC
#define | LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL
#define | LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
#define | LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1
#define | LL_DMA_OFFSETSIZE_PSIZE 0x00000000U
#define | LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL
#define | LL_DMA_MBURST_SINGLE 0x00000000U
#define | LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0
#define | LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1
#define | LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
#define | LL_DMA_PBURST_SINGLE 0x00000000U
#define | LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0
#define | LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1
#define | LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
#define | LL_DMA_FIFOMODE_DISABLE 0x00000000U
#define | LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS
#define | LL_DMA_FIFOSTATUS_0_25 0x00000000U
#define | LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0
#define | LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1
#define | LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)
#define | LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2
#define | LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)
#define | LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U
#define | LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0
#define | LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1
#define | LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH
#define | LL_DMA_CURRENTTARGETMEM0 0x00000000U
#define | LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
Convert DMAx_Streamy into DMAx.
#define | __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)
Convert DMAx_Streamy into LL_DMA_STREAM_y.
#define | __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)
Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy.

Functions

__STATIC_INLINE void | LL_DMA_EnableStream (DMA_TypeDef *DMAx, uint32_t Stream)
Enable DMA stream.
__STATIC_INLINE void | LL_DMA_DisableStream (DMA_TypeDef *DMAx, uint32_t Stream)
Disable DMA stream.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledStream (DMA_TypeDef *DMAx, uint32_t Stream)
Check if DMA stream is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
Configure all parameters linked to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Stream)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
Set DMA mode normal, circular or peripheral flow control.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get DMA mode normal, circular or peripheral flow control.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetIncOffsetSize (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
Set Peripheral increment offset size.
__STATIC_INLINE uint32_t | LL_DMA_GetIncOffsetSize (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral increment offset size.
__STATIC_INLINE void | LL_DMA_SetStreamPriorityLevel (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
Set Stream priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetStreamPriorityLevel (DMA_TypeDef *DMAx, uint32_t Stream)
Get Stream priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Stream)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
Set DMA request for DMA Streams on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Stream)
Get DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMA_SetMemoryBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
Set Memory burst transfer configuration.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory burst transfer configuration.
__STATIC_INLINE void | LL_DMA_SetPeriphBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
Set Peripheral burst transfer configuration.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphBurstxfer (DMA_TypeDef *DMAx, uint32_t Stream)
Get Peripheral burst transfer configuration.
__STATIC_INLINE void | LL_DMA_SetCurrentTargetMem (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE uint32_t | LL_DMA_GetCurrentTargetMem (DMA_TypeDef *DMAx, uint32_t Stream)
Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
__STATIC_INLINE void | LL_DMA_EnableDoubleBufferMode (DMA_TypeDef *DMAx, uint32_t Stream)
Enable the double buffer mode.
__STATIC_INLINE void | LL_DMA_DisableDoubleBufferMode (DMA_TypeDef *DMAx, uint32_t Stream)
Disable the double buffer mode.
__STATIC_INLINE uint32_t | LL_DMA_GetFIFOStatus (DMA_TypeDef *DMAx, uint32_t Stream)
Get FIFO status.
__STATIC_INLINE void | LL_DMA_DisableFifoMode (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Fifo mode.
__STATIC_INLINE void | LL_DMA_EnableFifoMode (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Fifo mode.
__STATIC_INLINE void | LL_DMA_SetFIFOThreshold (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
Select FIFO threshold.
__STATIC_INLINE uint32_t | LL_DMA_GetFIFOThreshold (DMA_TypeDef *DMAx, uint32_t Stream)
Get FIFO threshold.
__STATIC_INLINE void | LL_DMA_ConfigFifo (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
Configure the FIFO .
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Stream)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetMemory1Address (DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
Set Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE uint32_t | LL_DMA_GetMemory1Address (DMA_TypeDef *DMAx, uint32_t Stream)
Get Memory 1 address (used in case of Double buffer mode).
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT0 (DMA_TypeDef *DMAx)
Get Stream 0 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Stream 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Stream 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Stream 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Stream 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Stream 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Stream 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Stream 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC0 (DMA_TypeDef *DMAx)
Get Stream 0 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Stream 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Stream 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Stream 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Stream 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Stream 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Stream 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Stream 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE0 (DMA_TypeDef *DMAx)
Get Stream 0 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Stream 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Stream 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Stream 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Stream 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Stream 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Stream 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Stream 7 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME0 (DMA_TypeDef *DMAx)
Get Stream 0 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME1 (DMA_TypeDef *DMAx)
Get Stream 1 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME2 (DMA_TypeDef *DMAx)
Get Stream 2 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME3 (DMA_TypeDef *DMAx)
Get Stream 3 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME4 (DMA_TypeDef *DMAx)
Get Stream 4 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME5 (DMA_TypeDef *DMAx)
Get Stream 5 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME6 (DMA_TypeDef *DMAx)
Get Stream 6 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_DME7 (DMA_TypeDef *DMAx)
Get Stream 7 direct mode error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE0 (DMA_TypeDef *DMAx)
Get Stream 0 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE1 (DMA_TypeDef *DMAx)
Get Stream 1 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE2 (DMA_TypeDef *DMAx)
Get Stream 2 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE3 (DMA_TypeDef *DMAx)
Get Stream 3 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE4 (DMA_TypeDef *DMAx)
Get Stream 4 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE5 (DMA_TypeDef *DMAx)
Get Stream 5 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE6 (DMA_TypeDef *DMAx)
Get Stream 6 FIFO error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_FE7 (DMA_TypeDef *DMAx)
Get Stream 7 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT0 (DMA_TypeDef *DMAx)
Clear Stream 0 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Stream 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Stream 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Stream 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Stream 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Stream 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Stream 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Stream 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC0 (DMA_TypeDef *DMAx)
Clear Stream 0 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Stream 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Stream 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Stream 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Stream 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Stream 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Stream 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Stream 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE0 (DMA_TypeDef *DMAx)
Clear Stream 0 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Stream 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Stream 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Stream 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Stream 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Stream 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Stream 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Stream 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME0 (DMA_TypeDef *DMAx)
Clear Stream 0 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME1 (DMA_TypeDef *DMAx)
Clear Stream 1 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME2 (DMA_TypeDef *DMAx)
Clear Stream 2 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME3 (DMA_TypeDef *DMAx)
Clear Stream 3 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME4 (DMA_TypeDef *DMAx)
Clear Stream 4 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME5 (DMA_TypeDef *DMAx)
Clear Stream 5 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME6 (DMA_TypeDef *DMAx)
Clear Stream 6 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_DME7 (DMA_TypeDef *DMAx)
Clear Stream 7 direct mode error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE0 (DMA_TypeDef *DMAx)
Clear Stream 0 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE1 (DMA_TypeDef *DMAx)
Clear Stream 1 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE2 (DMA_TypeDef *DMAx)
Clear Stream 2 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE3 (DMA_TypeDef *DMAx)
Clear Stream 3 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE4 (DMA_TypeDef *DMAx)
Clear Stream 4 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE5 (DMA_TypeDef *DMAx)
Clear Stream 5 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE6 (DMA_TypeDef *DMAx)
Clear Stream 6 FIFO error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_FE7 (DMA_TypeDef *DMAx)
Clear Stream 7 FIFO error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Enable Direct mode error interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Enable FIFO error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Disable Direct mode error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Disable FIFO error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Half transfer interrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Transfer error nterrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Transfer complete interrup is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_DME (DMA_TypeDef *DMAx, uint32_t Stream)
Check if Direct mode error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_FE (DMA_TypeDef *DMAx, uint32_t Stream)
Check if FIFO error interrup is enabled.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Stream)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | LL_DMA_STR_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dma.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma2d.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_dma2d.h File Reference

Header file of DMA2D LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA2D_InitTypeDef
LL DMA2D Init Structure Definition. More...
struct | LL_DMA2D_LayerCfgTypeDef
LL DMA2D Layer Configuration Structure Definition. More...
struct | LL_DMA2D_ColorTypeDef
LL DMA2D Output Color Structure Definition. More...

Defines

#define | LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF
#define | LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF
#define | LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF
#define | LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF
#define | LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF
#define | LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF
#define | LL_DMA2D_IT_CEIE DMA2D_CR_CEIE
#define | LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE
#define | LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE
#define | LL_DMA2D_IT_TWIE DMA2D_CR_TWIE
#define | LL_DMA2D_IT_TCIE DMA2D_CR_TCIE
#define | LL_DMA2D_IT_TEIE DMA2D_CR_TEIE
#define | LL_DMA2D_MODE_M2M 0x00000000U
#define | LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0
#define | LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1
#define | LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1)
#define | LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2
#define | LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2)
#define | LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0
#define | LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1
#define | LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
#define | LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2
#define | LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0
#define | LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1
#define | LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)
#define | LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2
#define | LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
#define | LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3
#define | LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)
#define | LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
#define | LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
#define | LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U
#define | LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0
#define | LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1
#define | LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U
#define | LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB
#define | LL_DMA2D_RB_MODE_REGULAR 0x00000000U
#define | LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS
#define | LL_DMA2D_ALPHA_REGULAR 0x00000000U
#define | LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI
#define | LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U
#define | LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM
#define | LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U
#define | LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM
#define | LL_DMA2D_CSS_444 0x00000000U
#define | LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0
#define | LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1
#define | LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in DMA2D register.
#define | LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in DMA2D register.

Functions

__STATIC_INLINE void | LL_DMA2D_Start (DMA2D_TypeDef *DMA2Dx)
Start a DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsTransferOngoing (DMA2D_TypeDef *DMA2Dx)
Indicate if a DMA2D transfer is ongoing.
__STATIC_INLINE void | LL_DMA2D_Suspend (DMA2D_TypeDef *DMA2Dx)
Suspend DMA2D transfer.
__STATIC_INLINE void | LL_DMA2D_Resume (DMA2D_TypeDef *DMA2Dx)
Resume DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsSuspended (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is suspended.
__STATIC_INLINE void | LL_DMA2D_Abort (DMA2D_TypeDef *DMA2Dx)
Abort DMA2D transfer.
__STATIC_INLINE uint32_t | LL_DMA2D_IsAborted (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is aborted.
__STATIC_INLINE void | LL_DMA2D_SetMode (DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
Set DMA2D mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D output color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output color mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D output Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D output alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_SetOutputSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
Set DMA2D output swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D output swap mode.
__STATIC_INLINE void | LL_DMA2D_SetLineOffsetMode (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
Set DMA2D line offset mode.
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineOffsetMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset mode.
__STATIC_INLINE void | LL_DMA2D_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetNbrOfPixelsPerLines (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetNbrOfPixelsPerLines (DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
__STATIC_INLINE void | LL_DMA2D_SetNbrOfLines (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetNbrOfLines (DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetOutputMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetOutputColor (DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
Set DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetOutputColor (DMA2D_TypeDef *DMA2Dx)
Get DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetLineWatermark (DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetLineWatermark (DMA2D_TypeDef *DMA2Dx)
Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
__STATIC_INLINE void | LL_DMA2D_SetDeadTime (DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_GetDeadTime (DMA2D_TypeDef *DMA2Dx)
Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_EnableDeadTime (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D dead time functionality.
__STATIC_INLINE void | LL_DMA2D_DisableDeadTime (DMA2D_TypeDef *DMA2Dx)
Disable DMA2D dead time functionality.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledDeadTime (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D dead time functionality is enabled.
__STATIC_INLINE void | LL_DMA2D_FGND_SetMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_EnableCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D foreground CLUT loading.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_IsEnabledCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D foreground CLUT loading is enabled.
__STATIC_INLINE void | LL_DMA2D_FGND_SetColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D foreground color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground color mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlphaMode (DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D foreground alpha mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlphaMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlpha (DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlpha (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D foreground Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D foreground alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetRedColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetGreenColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetBlueColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTSize (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTSize (DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_FGND_SetCLUTColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D foreground CLUT color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetCLUTColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground CLUT color mode.
__STATIC_INLINE void | LL_DMA2D_FGND_SetChrSubSampling (DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
__STATIC_INLINE uint32_t | LL_DMA2D_FGND_GetChrSubSampling (DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
__STATIC_INLINE void | LL_DMA2D_BGND_SetMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_EnableCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Enable DMA2D background CLUT loading.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_IsEnabledCLUTLoad (DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D background CLUT loading is enabled.
__STATIC_INLINE void | LL_DMA2D_BGND_SetColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D background color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background color mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlphaMode (DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D background alpha mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlphaMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlpha (DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlpha (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetRBSwapMode (DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D background Red Blue swap mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetRBSwapMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background Red Blue swap mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetAlphaInvMode (DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D background alpha inversion mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetAlphaInvMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha inversion mode.
__STATIC_INLINE void | LL_DMA2D_BGND_SetLineOffset (DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetLineOffset (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetRedColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetGreenColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetBlueColor (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTMemAddr (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTSize (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTSize (DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
__STATIC_INLINE void | LL_DMA2D_BGND_SetCLUTColorMode (DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D background CLUT color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_BGND_GetCLUTColorMode (DMA2D_TypeDef *DMA2Dx)
Return DMA2D background CLUT color mode.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CTC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_CAE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TW (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete Interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_DMA2D_IsActiveFlag_TE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error Interrupt Flag is set or not.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Configuration Error Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CTC (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Transfer Complete Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_CAE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Access Error Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TW (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Watermark Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TC (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Complete Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_ClearFlag_TE (DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Error Interrupt Flag.
__STATIC_INLINE void | LL_DMA2D_EnableIT_CE (DMA2D_TypeDef *DMA2Dx)
Enable Configuration Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_CTC (DMA2D_TypeDef *DMA2Dx)
Enable CLUT Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_CAE (DMA2D_TypeDef *DMA2Dx)
Enable CLUT Access Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TW (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Watermark Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TC (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_EnableIT_TE (DMA2D_TypeDef *DMA2Dx)
Enable Transfer Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CE (DMA2D_TypeDef *DMA2Dx)
Disable Configuration Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CTC (DMA2D_TypeDef *DMA2Dx)
Disable CLUT Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_CAE (DMA2D_TypeDef *DMA2Dx)
Disable CLUT Access Error Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TW (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Watermark Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TC (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Complete Interrupt.
__STATIC_INLINE void | LL_DMA2D_DisableIT_TE (DMA2D_TypeDef *DMA2Dx)
Disable Transfer Error Interrupt.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CTC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_CAE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TW (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TC (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_DMA2D_IsEnabledIT_TE (DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
ErrorStatus | LL_DMA2D_DeInit (DMA2D_TypeDef *DMA2Dx)
De-initialize DMA2D registers (registers restored to their default values).
ErrorStatus | LL_DMA2D_Init (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
void | LL_DMA2D_StructInit (LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Set each LL_DMA2D_InitTypeDef field to default value.
void | LL_DMA2D_ConfigLayer (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
Configure the foreground or background according to the specified parameters in the LL_DMA2D_LayerCfgTypeDef structure.
void | LL_DMA2D_LayerCfgStructInit (LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
Set each LL_DMA2D_LayerCfgTypeDef field to default value.
void | LL_DMA2D_ConfigOutputColor (DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
Initialize DMA2D output color register according to the specified parameters in DMA2D_ColorStruct.
uint32_t | LL_DMA2D_GetOutputBlueColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Blue color.
uint32_t | LL_DMA2D_GetOutputGreenColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Green color.
uint32_t | LL_DMA2D_GetOutputRedColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Red color.
uint32_t | LL_DMA2D_GetOutputAlphaColor (DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Alpha color.
void | LL_DMA2D_ConfigSize (DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
Configure DMA2D transfer size.

Detailed Description

Header file of DMA2D LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dma2d.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dmamux.h File Reference

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Defines | Functions
stm32h7xx_ll_dmamux.h File Reference

Header file of DMAMUX LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | DMAMUX_CCR_SIZE 0x00000004U
#define | DMAMUX_RGCR_SIZE 0x00000004U
#define | DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
#define | DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
#define | DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14
#define | LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3
#define | LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4
#define | LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5
#define | LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6
#define | LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7
#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14
#define | LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3
#define | LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4
#define | LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5
#define | LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6
#define | LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7
#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE
#define | LL_DMAMUX1_REQ_MEM2MEM 0U
#define | LL_DMAMUX1_REQ_GENERATOR0 1U
#define | LL_DMAMUX1_REQ_GENERATOR1 2U
#define | LL_DMAMUX1_REQ_GENERATOR2 3U
#define | LL_DMAMUX1_REQ_GENERATOR3 4U
#define | LL_DMAMUX1_REQ_GENERATOR4 5U
#define | LL_DMAMUX1_REQ_GENERATOR5 6U
#define | LL_DMAMUX1_REQ_GENERATOR6 7U
#define | LL_DMAMUX1_REQ_GENERATOR7 8U
#define | LL_DMAMUX1_REQ_ADC1 9U
#define | LL_DMAMUX1_REQ_ADC2 10U
#define | LL_DMAMUX1_REQ_TIM1_CH1 11U
#define | LL_DMAMUX1_REQ_TIM1_CH2 12U
#define | LL_DMAMUX1_REQ_TIM1_CH3 13U
#define | LL_DMAMUX1_REQ_TIM1_CH4 14U
#define | LL_DMAMUX1_REQ_TIM1_UP 15U
#define | LL_DMAMUX1_REQ_TIM1_TRIG 16U
#define | LL_DMAMUX1_REQ_TIM1_COM 17U
#define | LL_DMAMUX1_REQ_TIM2_CH1 18U
#define | LL_DMAMUX1_REQ_TIM2_CH2 19U
#define | LL_DMAMUX1_REQ_TIM2_CH3 20U
#define | LL_DMAMUX1_REQ_TIM2_CH4 21U
#define | LL_DMAMUX1_REQ_TIM2_UP 22U
#define | LL_DMAMUX1_REQ_TIM3_CH1 23U
#define | LL_DMAMUX1_REQ_TIM3_CH2 24U
#define | LL_DMAMUX1_REQ_TIM3_CH3 25U
#define | LL_DMAMUX1_REQ_TIM3_CH4 26U
#define | LL_DMAMUX1_REQ_TIM3_UP 27U
#define | LL_DMAMUX1_REQ_TIM3_TRIG 28U
#define | LL_DMAMUX1_REQ_TIM4_CH1 29U
#define | LL_DMAMUX1_REQ_TIM4_CH2 30U
#define | LL_DMAMUX1_REQ_TIM4_CH3 31U
#define | LL_DMAMUX1_REQ_TIM4_UP 32U
#define | LL_DMAMUX1_REQ_I2C1_RX 33U
#define | LL_DMAMUX1_REQ_I2C1_TX 34U
#define | LL_DMAMUX1_REQ_I2C2_RX 35U
#define | LL_DMAMUX1_REQ_I2C2_TX 36U
#define | LL_DMAMUX1_REQ_SPI1_RX 37U
#define | LL_DMAMUX1_REQ_SPI1_TX 38U
#define | LL_DMAMUX1_REQ_SPI2_RX 39U
#define | LL_DMAMUX1_REQ_SPI2_TX 40U
#define | LL_DMAMUX1_REQ_USART1_RX 41U
#define | LL_DMAMUX1_REQ_USART1_TX 42U
#define | LL_DMAMUX1_REQ_USART2_RX 43U
#define | LL_DMAMUX1_REQ_USART2_TX 44U
#define | LL_DMAMUX1_REQ_USART3_RX 45U
#define | LL_DMAMUX1_REQ_USART3_TX 46U
#define | LL_DMAMUX1_REQ_TIM8_CH1 47U
#define | LL_DMAMUX1_REQ_TIM8_CH2 48U
#define | LL_DMAMUX1_REQ_TIM8_CH3 49U
#define | LL_DMAMUX1_REQ_TIM8_CH4 50U
#define | LL_DMAMUX1_REQ_TIM8_UP 51U
#define | LL_DMAMUX1_REQ_TIM8_TRIG 52U
#define | LL_DMAMUX1_REQ_TIM8_COM 53U
#define | LL_DMAMUX1_REQ_TIM5_CH1 55U
#define | LL_DMAMUX1_REQ_TIM5_CH2 56U
#define | LL_DMAMUX1_REQ_TIM5_CH3 57U
#define | LL_DMAMUX1_REQ_TIM5_CH4 58U
#define | LL_DMAMUX1_REQ_TIM5_UP 59U
#define | LL_DMAMUX1_REQ_TIM5_TRIG 60U
#define | LL_DMAMUX1_REQ_SPI3_RX 61U
#define | LL_DMAMUX1_REQ_SPI3_TX 62U
#define | LL_DMAMUX1_REQ_UART4_RX 63U
#define | LL_DMAMUX1_REQ_UART4_TX 64U
#define | LL_DMAMUX1_REQ_UART5_RX 65U
#define | LL_DMAMUX1_REQ_UART5_TX 66U
#define | LL_DMAMUX1_REQ_DAC1_CH1 67U
#define | LL_DMAMUX1_REQ_DAC1_CH2 68U
#define | LL_DMAMUX1_REQ_TIM6_UP 69U
#define | LL_DMAMUX1_REQ_TIM7_UP 70U
#define | LL_DMAMUX1_REQ_USART6_RX 71U
#define | LL_DMAMUX1_REQ_USART6_TX 72U
#define | LL_DMAMUX1_REQ_I2C3_RX 73U
#define | LL_DMAMUX1_REQ_I2C3_TX 74U
#define | LL_DMAMUX1_REQ_DCMI_PSSI 75U
#define | LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
#define | LL_DMAMUX1_REQ_CRYP_IN 76U
#define | LL_DMAMUX1_REQ_CRYP_OUT 77U
#define | LL_DMAMUX1_REQ_HASH_IN 78U
#define | LL_DMAMUX1_REQ_UART7_RX 79U
#define | LL_DMAMUX1_REQ_UART7_TX 80U
#define | LL_DMAMUX1_REQ_UART8_RX 81U
#define | LL_DMAMUX1_REQ_UART8_TX 82U
#define | LL_DMAMUX1_REQ_SPI4_RX 83U
#define | LL_DMAMUX1_REQ_SPI4_TX 84U
#define | LL_DMAMUX1_REQ_SPI5_RX 85U
#define | LL_DMAMUX1_REQ_SPI5_TX 86U
#define | LL_DMAMUX1_REQ_SAI1_A 87U
#define | LL_DMAMUX1_REQ_SAI1_B 88U
#define | LL_DMAMUX1_REQ_SAI2_A 89U
#define | LL_DMAMUX1_REQ_SAI2_B 90U
#define | LL_DMAMUX1_REQ_SWPMI_RX 91U
#define | LL_DMAMUX1_REQ_SWPMI_TX 92U
#define | LL_DMAMUX1_REQ_SPDIF_RX_DT 93U
#define | LL_DMAMUX1_REQ_SPDIF_RX_CS 94U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT0 101U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT1 102U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT2 103U
#define | LL_DMAMUX1_REQ_DFSDM1_FLT3 104U
#define | LL_DMAMUX1_REQ_TIM15_CH1 105U
#define | LL_DMAMUX1_REQ_TIM15_UP 106U
#define | LL_DMAMUX1_REQ_TIM15_TRIG 107U
#define | LL_DMAMUX1_REQ_TIM15_COM 108U
#define | LL_DMAMUX1_REQ_TIM16_CH1 109U
#define | LL_DMAMUX1_REQ_TIM16_UP 110U
#define | LL_DMAMUX1_REQ_TIM17_CH1 111U
#define | LL_DMAMUX1_REQ_TIM17_UP 112U
#define | LL_DMAMUX1_REQ_UART9_RX 116U
#define | LL_DMAMUX1_REQ_UART9_TX 117U
#define | LL_DMAMUX1_REQ_USART10_RX 118U
#define | LL_DMAMUX1_REQ_USART10_TX 119U
#define | LL_DMAMUX2_REQ_MEM2MEM 0U
#define | LL_DMAMUX2_REQ_GENERATOR0 1U
#define | LL_DMAMUX2_REQ_GENERATOR1 2U
#define | LL_DMAMUX2_REQ_GENERATOR2 3U
#define | LL_DMAMUX2_REQ_GENERATOR3 4U
#define | LL_DMAMUX2_REQ_GENERATOR4 5U
#define | LL_DMAMUX2_REQ_GENERATOR5 6U
#define | LL_DMAMUX2_REQ_GENERATOR6 7U
#define | LL_DMAMUX2_REQ_GENERATOR7 8U
#define | LL_DMAMUX2_REQ_LPUART1_RX 9U
#define | LL_DMAMUX2_REQ_LPUART1_TX 10U
#define | LL_DMAMUX2_REQ_SPI6_RX 11U
#define | LL_DMAMUX2_REQ_SPI6_TX 12U
#define | LL_DMAMUX2_REQ_I2C4_RX 13U
#define | LL_DMAMUX2_REQ_I2C4_TX 14U
#define | LL_DMAMUX2_REQ_DAC2_CH1 17U
#define | LL_DMAMUX2_REQ_DFSDM2 18U
#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU
#define | LL_DMAMUX_CHANNEL_14 0x0000000EU
#define | LL_DMAMUX_CHANNEL_15 0x0000000FU
#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)
#define | LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U
#define | LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U
#define | LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U
#define | LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U
#define | LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U
#define | LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U
#define | LL_DMAMUX1_SYNC_EXTI0 0x06000000U
#define | LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U
#define | LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U
#define | LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U
#define | LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U
#define | LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U
#define | LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U
#define | LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U
#define | LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U
#define | LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U
#define | LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U
#define | LL_DMAMUX2_SYNC_EXTI0 0x0E000000U
#define | LL_DMAMUX2_SYNC_EXTI2 0x0F000000U
#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U
#define | LL_DMAMUX_REQ_GEN_4 0x00000004U
#define | LL_DMAMUX_REQ_GEN_5 0x00000005U
#define | LL_DMAMUX_REQ_GEN_6 0x00000006U
#define | LL_DMAMUX_REQ_GEN_7 0x00000007U
#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)
#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
#define | LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
#define | LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
#define | LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
#define | LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
#define | LL_DMAMUX1_REQ_GEN_EXTI0 6U
#define | LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
#define | LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
#define | LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
#define | LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
#define | LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
#define | LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
#define | LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
#define | LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
#define | LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
#define | LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
#define | LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
#define | LL_DMAMUX2_REQ_GEN_EXTI0 20U
#define | LL_DMAMUX2_REQ_GEN_EXTI2 21U
#define | LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
#define | LL_DMAMUX2_REQ_GEN_SPI6_IT 23U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
#define | LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
#define | LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
#define | LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U
#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO14 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 14.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO15 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 15.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 4 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 5 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 6 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 7 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO14 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 14.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO15 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 15.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 4 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 5 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 6 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 7 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Detailed Description

Header file of DMAMUX LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_dmamux.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_exti.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_42 EXTI_IMR2_IM42
#define | LL_EXTI_LINE_43 EXTI_IMR2_IM43
#define | LL_EXTI_LINE_47 EXTI_IMR2_IM47
#define | LL_EXTI_LINE_48 EXTI_IMR2_IM48
#define | LL_EXTI_LINE_49 EXTI_IMR2_IM49
#define | LL_EXTI_LINE_50 EXTI_IMR2_IM50
#define | LL_EXTI_LINE_51 EXTI_IMR2_IM51
#define | LL_EXTI_LINE_52 EXTI_IMR2_IM52
#define | LL_EXTI_LINE_53 EXTI_IMR2_IM53
#define | LL_EXTI_LINE_54 EXTI_IMR2_IM54
#define | LL_EXTI_LINE_55 EXTI_IMR2_IM55
#define | LL_EXTI_LINE_56 EXTI_IMR2_IM56
#define | LL_EXTI_LINE_57 EXTI_IMR2_IM57
#define | LL_EXTI_LINE_58 EXTI_IMR2_IM58
#define | LL_EXTI_LINE_59 EXTI_IMR2_IM59
#define | LL_EXTI_LINE_60 EXTI_IMR2_IM60
#define | LL_EXTI_LINE_61 EXTI_IMR2_IM61
#define | LL_EXTI_LINE_62 EXTI_IMR2_IM62
#define | LL_EXTI_LINE_63 EXTI_IMR2_IM63
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_64 EXTI_IMR3_IM64
#define | LL_EXTI_LINE_65 EXTI_IMR3_IM65
#define | LL_EXTI_LINE_66 EXTI_IMR3_IM66
#define | LL_EXTI_LINE_67 EXTI_IMR3_IM67
#define | LL_EXTI_LINE_68 EXTI_IMR3_IM68
#define | LL_EXTI_LINE_69 EXTI_IMR3_IM69
#define | LL_EXTI_LINE_70 EXTI_IMR3_IM70
#define | LL_EXTI_LINE_71 EXTI_IMR3_IM71
#define | LL_EXTI_LINE_72 EXTI_IMR3_IM72
#define | LL_EXTI_LINE_73 EXTI_IMR3_IM73
#define | LL_EXTI_LINE_74 EXTI_IMR3_IM74
#define | LL_EXTI_LINE_85 EXTI_IMR3_IM85
#define | LL_EXTI_LINE_87 EXTI_IMR3_IM87
#define | LL_EXTI_LINE_88 EXTI_IMR3_IM88
#define | LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U)
#define | LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U)
#define | LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U)
#define | LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableIT_64_95 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_64_95 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_64_95 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableEvent_64_95 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_64_95 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_64_95 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_64_95 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_64_95 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_64_95 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_64_95 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_64_95 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_64_95 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_64_95 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_64_95 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 64 to 95.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_64_95 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 64 to 95.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_64_95 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 64 to 95.
__STATIC_INLINE void | LL_D3_EXTI_EnablePendMask_0_31 (uint32_t ExtiLine)
Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31.
__STATIC_INLINE void | LL_D3_EXTI_EnablePendMask_32_63 (uint32_t ExtiLine)
Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63.
__STATIC_INLINE void | LL_D3_EXTI_DisablePendMask_0_31 (uint32_t ExtiLine)
Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31.
__STATIC_INLINE void | LL_D3_EXTI_DisablePendMask_32_63 (uint32_t ExtiLine)
Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_D3_EXTI_IsEnabledPendMask_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_D3_EXTI_IsEnabledPendMask_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_0_15 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_16_31 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_32_47 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.
__STATIC_INLINE void | LL_D3_EXTI_SetPendClearSel_48_63 (uint32_t ExtiLine, uint32_t ClrSrc)
Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_0_15 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_16_31 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_32_47 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47.
__STATIC_INLINE uint32_t | LL_D3_EXTI_GetPendClearSel_48_63 (uint32_t ExtiLine)
Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_exti.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_gpio.h File Reference

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stm32h7xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0
#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0
#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0
#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1
#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_gpio.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hsem.h File Reference

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Defines | Functions
stm32h7xx_ll_hsem.h File Reference

Header file of HSEM LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_HSEM_COREID_NONE 0U
#define | LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
#define | LL_HSEM_COREID HSEM_CR_COREID_CURRENT
#define | LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
#define | LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
#define | LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
#define | LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
#define | LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
#define | LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
#define | LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
#define | LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
#define | LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
#define | LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
#define | LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
#define | LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
#define | LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
#define | LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
#define | LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
#define | LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
#define | LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU
#define | LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in HSEM register.
#define | LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in HSEM register.

Functions

__STATIC_INLINE uint32_t | LL_HSEM_IsSemaphoreLocked (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Return 1 if the semaphore is locked, else return 0.
__STATIC_INLINE uint32_t | LL_HSEM_GetCoreId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get core id.
__STATIC_INLINE uint32_t | LL_HSEM_GetProcessId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get process id.
__STATIC_INLINE void | LL_HSEM_SetLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock by writing in R register.
__STATIC_INLINE uint32_t | LL_HSEM_2StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock with 2-step lock.
__STATIC_INLINE uint32_t | LL_HSEM_1StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock with 1-step lock.
__STATIC_INLINE void | LL_HSEM_ReleaseLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Release the lock of the semaphore.
__STATIC_INLINE uint32_t | LL_HSEM_GetStatus (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock status of the semaphore.
__STATIC_INLINE void | LL_HSEM_SetKey (HSEM_TypeDef *HSEMx, uint32_t key)
Set the key.
__STATIC_INLINE uint32_t | LL_HSEM_GetKey (HSEM_TypeDef *HSEMx)
Get the key.
__STATIC_INLINE void | LL_HSEM_ResetAllLock (HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
Release all semaphore with the same core id.
__STATIC_INLINE void | LL_HSEM_EnableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.
__STATIC_INLINE void | LL_HSEM_ClearFlag_C1ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.

Detailed Description

Header file of HSEM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_hsem.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_i2c.h File Reference

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stm32h7xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_i2c.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_iwdg.h File Reference

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stm32h7xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_iwdg.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lptim.h File Reference

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stm32h7xx_ll_lptim.h File Reference

Header file of LPTIM LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN
#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE
#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT
#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE
#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL
#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT
#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL
#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT
#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1
#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0
#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.
__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.
__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Detailed Description

Header file of LPTIM LL module.

Author:
MCD Application Team
Attention:

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Definition in file stm32h7xx_ll_lptim.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lpuart.h File Reference

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stm32h7xx_ll_lpuart.h File Reference

Header file of LPUART LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U
#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF
#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT
#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0
#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.
#define | __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)
#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.
__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TXFE (USART_TypeDef *LPUARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.
ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Variables

static const uint16_t | LPUART_PRESCALER_TAB []

Detailed Description

Header file of LPUART LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_lpuart.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_mdma.h File Reference

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Data Structures | Defines | Functions | Variables
stm32h7xx_ll_mdma.h File Reference

Header file of MDMA LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_MDMA_InitTypeDef
struct | LL_MDMA_LinkNodeTypeDef
LL MDMA linked list node structure definition. More...

Defines

#define | LL_MDMA_CHANNEL_0 0x00000000U
#define | LL_MDMA_CHANNEL_1 0x00000001U
#define | LL_MDMA_CHANNEL_2 0x00000002U
#define | LL_MDMA_CHANNEL_3 0x00000003U
#define | LL_MDMA_CHANNEL_4 0x00000004U
#define | LL_MDMA_CHANNEL_5 0x00000005U
#define | LL_MDMA_CHANNEL_6 0x00000006U
#define | LL_MDMA_CHANNEL_7 0x00000007U
#define | LL_MDMA_CHANNEL_8 0x00000008U
#define | LL_MDMA_CHANNEL_9 0x00000009U
#define | LL_MDMA_CHANNEL_10 0x0000000AU
#define | LL_MDMA_CHANNEL_11 0x0000000BU
#define | LL_MDMA_CHANNEL_12 0x0000000CU
#define | LL_MDMA_CHANNEL_13 0x0000000DU
#define | LL_MDMA_CHANNEL_14 0x0000000EU
#define | LL_MDMA_CHANNEL_15 0x0000000FU
#define | LL_MDMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX
#define | LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX
#define | LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U
#define | LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX
#define | LL_MDMA_PRIORITY_LOW 0x00000000U
#define | LL_MDMA_PRIORITY_MEDIUM MDMA_CCR_PL_0
#define | LL_MDMA_PRIORITY_HIGH MDMA_CCR_PL_1
#define | LL_MDMA_PRIORITY_VERYHIGH MDMA_CCR_PL
#define | LL_MDMA_BUFF_WRITE_DISABLE 0x00000000U
#define | LL_MDMA_BUFF_WRITE_ENABLE MDMA_CTCR_BWM
#define | LL_MDMA_REQUEST_MODE_HW 0x00000000U
#define | LL_MDMA_REQUEST_MODE_SW MDMA_CTCR_SWRM
#define | LL_MDMA_BUFFER_TRANSFER 0x00000000U
#define | LL_MDMA_BLOCK_TRANSFER MDMA_CTCR_TRGM_0
#define | LL_MDMA_REPEAT_BLOCK_TRANSFER MDMA_CTCR_TRGM_1
#define | LL_MDMA_FULL_TRANSFER MDMA_CTCR_TRGM
#define | LL_MDMA_DATAALIGN_RIGHT 0x00000000U
#define | LL_MDMA_DATAALIGN_RIGHT_SIGNED MDMA_CTCR_PAM_0
#define | LL_MDMA_DATAALIGN_LEFT MDMA_CTCR_PAM_1
#define | LL_MDMA_PACK_DISABLE 0x00000000U
#define | LL_MDMA_PACK_ENABLE MDMA_CTCR_PKE
#define | LL_MDMA_DEST_BURST_SINGLE 0x00000000U
#define | LL_MDMA_DEST_BURST_2BEATS MDMA_CTCR_DBURST_0
#define | LL_MDMA_DEST_BURST_4BEATS MDMA_CTCR_DBURST_1
#define | LL_MDMA_DEST_BURST_8BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)
#define | LL_MDMA_DEST_BURST_16BEATS MDMA_CTCR_DBURST_2
#define | LL_MDMA_DEST_BURST_32BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)
#define | LL_MDMA_DEST_BURST_64BEATS (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)
#define | LL_MDMA_DEST_BURST_128BEATS (MDMA_CTCR_DBURST)
#define | LL_MDMA_SRC_BURST_SINGLE 0x00000000U
#define | LL_MDMA_SRC_BURST_2BEATS MDMA_CTCR_SBURST_0
#define | LL_MDMA_SRC_BURST_4BEATS MDMA_CTCR_SBURST_1
#define | LL_MDMA_SRC_BURST_8BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)
#define | LL_MDMA_SRC_BURST_16BEATS MDMA_CTCR_SBURST_2
#define | LL_MDMA_SRC_BURST_32BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)
#define | LL_MDMA_SRC_BURST_64BEATS (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)
#define | LL_MDMA_SRC_BURST_128BEATS MDMA_CTCR_SBURST
#define | LL_MDMA_DEST_INC_OFFSET_BYTE 0x00000000U
#define | LL_MDMA_DEST_INC_OFFSET_HALFWORD MDMA_CTCR_DINCOS_0
#define | LL_MDMA_DEST_INC_OFFSET_WORD MDMA_CTCR_DINCOS_1
#define | LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD MDMA_CTCR_DINCOS
#define | LL_MDMA_SRC_INC_OFFSET_BYTE 0x00000000U
#define | LL_MDMA_SRC_INC_OFFSET_HALFWORD MDMA_CTCR_SINCOS_0
#define | LL_MDMA_SRC_INC_OFFSET_WORD MDMA_CTCR_SINCOS_1
#define | LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD MDMA_CTCR_SINCOS
#define | LL_MDMA_DEST_DATA_SIZE_BYTE 0x00000000U
#define | LL_MDMA_DEST_DATA_SIZE_HALFWORD MDMA_CTCR_DSIZE_0
#define | LL_MDMA_DEST_DATA_SIZE_WORD MDMA_CTCR_DSIZE_1
#define | LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE
#define | LL_MDMA_SRC_DATA_SIZE_BYTE 0x00000000U
#define | LL_MDMA_SRC_DATA_SIZE_HALFWORD MDMA_CTCR_SSIZE_0
#define | LL_MDMA_SRC_DATA_SIZE_WORD MDMA_CTCR_SSIZE_1
#define | LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE
#define | LL_MDMA_DEST_FIXED 0x00000000U
#define | LL_MDMA_DEST_INCREMENT MDMA_CTCR_DINC_1
#define | LL_MDMA_DEST_DECREMENT MDMA_CTCR_DINC
#define | LL_MDMA_SRC_FIXED 0x00000000U
#define | LL_MDMA_SRC_INCREMENT MDMA_CTCR_SINC_1
#define | LL_MDMA_SRC_DECREMENT MDMA_CTCR_SINC
#define | LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT 0x00000000U
#define | LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT MDMA_CBNDTR_BRDUM
#define | LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT 0x00000000U
#define | LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT MDMA_CBNDTR_BRSUM
#define | LL_MDMA_DEST_BUS_SYSTEM_AXI 0x00000000U
#define | LL_MDMA_DEST_BUS_AHB_TCM MDMA_CTBR_DBUS
#define | LL_MDMA_SRC_BUS_SYSTEM_AXI 0x00000000U
#define | LL_MDMA_SRC_BUS_AHB_TCM MDMA_CTBR_SBUS
#define | LL_MDMA_REQ_DMA1_STREAM0_TC 0x00000000U
#define | LL_MDMA_REQ_DMA1_STREAM1_TC 0x00000001U
#define | LL_MDMA_REQ_DMA1_STREAM2_TC 0x00000002U
#define | LL_MDMA_REQ_DMA1_STREAM3_TC 0x00000003U
#define | LL_MDMA_REQ_DMA1_STREAM4_TC 0x00000004U
#define | LL_MDMA_REQ_DMA1_STREAM5_TC 0x00000005U
#define | LL_MDMA_REQ_DMA1_STREAM6_TC 0x00000006U
#define | LL_MDMA_REQ_DMA1_STREAM7_TC 0x00000007U
#define | LL_MDMA_REQ_DMA2_STREAM0_TC 0x00000008U
#define | LL_MDMA_REQ_DMA2_STREAM1_TC 0x00000009U
#define | LL_MDMA_REQ_DMA2_STREAM2_TC 0x0000000AU
#define | LL_MDMA_REQ_DMA2_STREAM3_TC 0x0000000BU
#define | LL_MDMA_REQ_DMA2_STREAM4_TC 0x0000000CU
#define | LL_MDMA_REQ_DMA2_STREAM5_TC 0x0000000DU
#define | LL_MDMA_REQ_DMA2_STREAM6_TC 0x0000000EU
#define | LL_MDMA_REQ_DMA2_STREAM7_TC 0x0000000FU
#define | LL_MDMA_REQ_LTDC_LINE_IT 0x00000010U
#define | LL_MDMA_REQ_JPEG_INFIFO_TH 0x00000011U
#define | LL_MDMA_REQ_JPEG_INFIFO_NF 0x00000012U
#define | LL_MDMA_REQ_JPEG_OUTFIFO_TH 0x00000013U
#define | LL_MDMA_REQ_JPEG_OUTFIFO_NE 0x00000014U
#define | LL_MDMA_REQ_JPEG_END_CONVERSION 0x00000015U
#define | LL_MDMA_REQ_OCTOSPI1_FIFO_TH 0x00000016U
#define | LL_MDMA_REQ_OCTOSPI1_TC 0x00000017U
#define | LL_MDMA_REQ_DMA2D_CLUT_TC 0x00000018U
#define | LL_MDMA_REQ_DMA2D_TC 0x00000019U
#define | LL_MDMA_REQ_DMA2D_TW 0x0000001AU
#define | LL_MDMA_REQ_SDMMC1_END_DATA 0x0000001DU
#define | LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER 0x0000001EU
#define | LL_MDMA_REQ_SDMMC1_COMMAND_END 0x0000001FU
#define | LL_MDMA_REQ_OCTOSPI2_FIFO_TH 0x00000020U
#define | LL_MDMA_REQ_OCTOSPI2_TC 0x00000021U
#define | LL_MDMA_READ_ERROR 0x00000000U
#define | LL_MDMA_WRITE_ERROR MDMA_CESR_TED
#define | LL_MDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in MDMA register.
#define | LL_MDMA_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in MDMA register.
#define | LL_MDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (MDMA)
Convert MDMAx_Channely into MDMAx.
#define | LL_MDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert MDMAx_Channely into LL_MDMA_CHANNEL_y.
#define | LL_MDMA_GET_CHANNEL_INSTANCE(__MDMA_INSTANCE__, __CHANNEL__)
Convert MDMA Instance MDMAx and LL_MDMA_CHANNEL_y into MDMAx_Channely.

Functions

__STATIC_INLINE void | LL_MDMA_EnableChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA channel.
__STATIC_INLINE void | LL_MDMA_DisableChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA channel.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledChannel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA channel is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_GenerateSWRequest (MDMA_TypeDef *MDMAx, uint32_t Channel)
Generate a SW transfer request on the MDMA channel.
__STATIC_INLINE void | LL_MDMA_ConfigXferEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.
__STATIC_INLINE void | LL_MDMA_SetWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Words Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Words Endianess.
__STATIC_INLINE void | LL_MDMA_SetHalfWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Half Words Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetHalfWordEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Half Words Endianess.
__STATIC_INLINE void | LL_MDMA_SetByteEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
Set Bytes Endianess.
__STATIC_INLINE uint32_t | LL_MDMA_GetByteEndianness (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Bytes Endianess.
__STATIC_INLINE void | LL_MDMA_SetChannelPriorityLevel (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_MDMA_GetChannelPriorityLevel (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_MDMA_ConfigTransfer (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)
Configure MDMA transfer parameters.
__STATIC_INLINE void | LL_MDMA_EnableBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable Bufferable Write Mode.
__STATIC_INLINE void | LL_MDMA_DisableBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable Bufferable Write Mode.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledBufferableWrMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if Bufferable Write Mode is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_SetRequestMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)
Set Request Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetRequestMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Request Mode.
__STATIC_INLINE void | LL_MDMA_SetTriggerMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)
Set Trigger Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetTriggerMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Trigger Mode.
__STATIC_INLINE void | LL_MDMA_SetPaddingAlignment (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)
Set Padding Alignment.
__STATIC_INLINE uint32_t | LL_MDMA_GetPaddingAlignment (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Padding Alignment.
__STATIC_INLINE void | LL_MDMA_EnablePacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable Packing.
__STATIC_INLINE void | LL_MDMA_DisablePacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable Packing.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledPacking (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if packing is enabled or disabled.
__STATIC_INLINE void | LL_MDMA_SetBufferTransferLength (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)
Set Buffer Transfer Length.
__STATIC_INLINE uint32_t | LL_MDMA_GetBufferTransferLength (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Buffer Transfer Length.
__STATIC_INLINE void | LL_MDMA_SetDestinationBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)
Set Destination burst transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination burst transfer.
__STATIC_INLINE void | LL_MDMA_SetSourceBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)
Set Source burst transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceBurstSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source burst transfer.
__STATIC_INLINE void | LL_MDMA_SetDestinationIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
Set Destination Increment Offset Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Increment Offset Size.
__STATIC_INLINE void | LL_MDMA_SetSourceIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
Set Source Increment Offset Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceIncSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Increment Offset Size.
__STATIC_INLINE void | LL_MDMA_SetDestinationDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)
Set Destination Data Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Data Size.
__STATIC_INLINE void | LL_MDMA_SetSourceDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)
Set Source Data Size.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceDataSize (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Data Size.
__STATIC_INLINE void | LL_MDMA_SetDestinationIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)
Set Destination Increment Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Increment Mode.
__STATIC_INLINE void | LL_MDMA_SetSourceIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)
Set Source Increment Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceIncMode (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Increment Mode.
__STATIC_INLINE void | LL_MDMA_ConfigBlkCounters (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)
Configure MDMA Block number of data and repeat Count.
__STATIC_INLINE void | LL_MDMA_SetBlkDataLength (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)
Set Block Number of data bytes to transfer.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkDataLength (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Number of data bytes to transfer.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatCount (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)
Set Block Repeat Count.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatCount (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Count.
__STATIC_INLINE void | LL_MDMA_ConfigBlkRepeatAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure MDMA block repeat address update mode.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatDestAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)
Set Block Repeat Destination address Update Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatDestAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Destination address Update Mode.
__STATIC_INLINE void | LL_MDMA_SetBlkRepeatSrcAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)
Set Block Repeat Source address Update Mode.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRepeatSrcAddrUpdate (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Block Repeat Source address Update Mode.
__STATIC_INLINE void | LL_MDMA_ConfigAddresses (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_MDMA_SetSourceAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)
Set transfer Source address.
__STATIC_INLINE uint32_t | LL_MDMA_GetSourceAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Source address.
__STATIC_INLINE void | LL_MDMA_SetDestinationAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)
Set transfer Destination address.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestinationAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Destination address.
__STATIC_INLINE void | LL_MDMA_ConfigBlkRptAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)
Configure the Source and Destination Block repeat addresses Update value.
__STATIC_INLINE void | LL_MDMA_SetBlkRptDestAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)
Set transfer Destination address Update Value.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRptDestAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Destination address Update Value.
__STATIC_INLINE void | LL_MDMA_SetBlkRptSrcAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)
Set transfer Source address Update Value.
__STATIC_INLINE uint32_t | LL_MDMA_GetBlkRptSrcAddrUpdateValue (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Source address Update Value.
__STATIC_INLINE void | LL_MDMA_SetLinkAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)
Set transfer Link Address.
__STATIC_INLINE uint32_t | LL_MDMA_GetLinkAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get transfer Link Address.
__STATIC_INLINE void | LL_MDMA_ConfigBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
Configure MDMA source and destination bus selection.
__STATIC_INLINE void | LL_MDMA_SetDestBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)
Set Destination Bus Selection.
__STATIC_INLINE uint32_t | LL_MDMA_GetDestBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Destination Bus Selection.
__STATIC_INLINE void | LL_MDMA_SetSrcBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)
Set Source Bus Selection.
__STATIC_INLINE uint32_t | LL_MDMA_GetSrcBusSelection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Source Bus Selection.
__STATIC_INLINE void | LL_MDMA_SetHWTrigger (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)
Set Transfer hardware trigger (Request).
__STATIC_INLINE uint32_t | LL_MDMA_GetHWTrigger (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer hardware trigger (Request).
__STATIC_INLINE void | LL_MDMA_SetMaskAddress (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)
Set Mask Address.
__STATIC_INLINE uint32_t | LL_MDMA_GetMaskAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Mask Address.
__STATIC_INLINE void | LL_MDMA_SetMaskData (MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)
Set Mask Data.
__STATIC_INLINE uint32_t | LL_MDMA_GetMaskData (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Mask Data.
__STATIC_INLINE uint32_t | LL_MDMA_GetXferErrorDirection (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer Error Direction.
__STATIC_INLINE uint32_t | LL_MDMA_GetXferErrorLSBAddress (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get Transfer Error LSB Address.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_GI (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Global Interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Channel Transfer Complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Repeat Transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x buffer transfer complete interrupt flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_CRQA (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x ReQuest Active flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_BSE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Block Size Error flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_ASE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Address/Size Error flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TEMD (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error Mask Data flag.
__STATIC_INLINE uint32_t | LL_MDMA_IsActiveFlag_TELD (MDMA_TypeDef *MDMAx, uint32_t Channel)
Get MDMA Channel x Transfer Error Link Data flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Transfer Error interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Channel Transfer Complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Block Repeat Transfer complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x Block Transfer complete interrupt flag.
__STATIC_INLINE void | LL_MDMA_ClearFlag_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Clear MDMA Channel x buffer transfer Complete Interrupt Flag.
__STATIC_INLINE void | LL_MDMA_EnableIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Transfer Error interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Channel Transfer Complete interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Block Repeat Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x Block Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_EnableIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Enable MDMA Channel x buffer transfer complete interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Transfer Error interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Channel Transfer Complete interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Block Repeat Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x Block Transfer interrupt.
__STATIC_INLINE void | LL_MDMA_DisableIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Disable MDMA Channel x buffer transfer complete interrupt.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_TE (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Transfer Error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_CTC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Channel Transfer Complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_BRT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Block Repeat Transfer complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_BT (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x Block Transfer interrupt is enabled.
__STATIC_INLINE uint32_t | LL_MDMA_IsEnabledIT_TC (MDMA_TypeDef *MDMAx, uint32_t Channel)
Check if MDMA Channel x buffer transfer complete interrupt is enabled.
uint32_t | LL_MDMA_Init (MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
uint32_t | LL_MDMA_DeInit (MDMA_TypeDef *MDMAx, uint32_t Channel)
De-initialize the MDMA registers to their default reset values.
void | LL_MDMA_StructInit (LL_MDMA_InitTypeDef *MDMA_InitStruct)
Set each LL_MDMA_InitTypeDef field to default value.
void | LL_MDMA_CreateLinkNode (LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
Initializes MDMA linked list node according to the specified parameters in the MDMA_InitStruct.
void | LL_MDMA_ConnectLinkNode (LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
Connect Linked list Nodes.
void | LL_MDMA_DisconnectNextLinkNode (LL_MDMA_LinkNodeTypeDef *pLinkNode)
Disconnect the next linked list node.

Variables

static const uint32_t | LL_MDMA_CH_OFFSET_TAB []

Detailed Description

Header file of MDMA LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_mdma.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_opamp.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_opamp.h File Reference

Header file of OPAMP LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...

Defines

#define | OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U
#define | OPAMP_POWERMODE_HSOTR_REGOFFSET 0x00000001U
#define | OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_HSOTR_REGOFFSET)
#define | OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPAHSM)
#define | OPAMP_TRIMMING_SELECT_MASK 0x00030000U
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_OPAMP_MODE_FUNCTIONAL 0x00000000U
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)
#define | LL_OPAMP_MODE_STANDALONE 0x00000000U
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 0x00000000U
#define | LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U
#define | LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_DAC2 OPAMP_CSR_VPSEL_1
#define | LL_OPAMP_INPUT_INVERT_IO0 0x00000000U
#define | LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1
#define | LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)
#define | LL_OPAMP_POWERMODE_HIGHSPEED (OPAMP_POWERMODE_HSOTR_REGOFFSET | OPAMP_CSR_OPAHSM)
#define | LL_OPAMP_TRIMMING_FACTORY 0x00000000U
#define | LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_OTR_TRIMOFFSETN | ((OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) << 4))
#define | LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_OTR_TRIMOFFSETN | (OPAMP_CSR_CALSEL_1 << 4))
#define | LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_OTR_TRIMOFFSETP | (OPAMP_CSR_CALSEL_0 << 4))
#define | LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_OTR_TRIMOFFSETP )
#define | LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)
#define | LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)
#define | LL_OPAMP_DELAY_STARTUP_US (3U)
#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in OPAMP LL_OPAMP_GetPowerModeregister.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in OPAMP register.
#define | __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON)
Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.
#define | __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()
Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Functions

__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.
__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode normal or highspeed.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode normal or highspeed.
__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)
ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

Header file of OPAMP LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_opamp.h.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_pwr.h File Reference

  • File List
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stm32h7xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
#define | LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
#define | LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF
#define | LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6
#define | LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5
#define | LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4
#define | LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3
#define | LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2
#define | LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1
#define | LL_PWR_FLAG_AVDO PWR_CSR1_AVDO
#define | LL_PWR_FLAG_PVDO PWR_CSR1_PVDO
#define | LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS
#define | LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY
#define | LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO
#define | LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH
#define | LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL
#define | LL_PWR_FLAG_VBATH PWR_CR2_VBATH
#define | LL_PWR_FLAG_VBATL PWR_CR2_VBATL
#define | LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY
#define | LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY
#define | LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY
#define | LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF
#define | LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF
#define | LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY
#define | LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6
#define | LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5
#define | LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4
#define | LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3
#define | LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2
#define | LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1
#define | LL_PWR_CPU_MODE_CDSTOP 0x00000000U
#define | LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD
#define | LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD
#define | LL_PWR_CPU_MODE_SRDSTOP 0x00000000U
#define | LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD
#define | LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U
#define | LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0
#define | LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1
#define | LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1)
#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0
#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1
#define | LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS
#define | LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7
#define | LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
#define | LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS
#define | LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
#define | LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define | LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#define | LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#define | LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#define | LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
#define | LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL
#define | LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL
#define | LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL
#define | LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN
#define | LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN
#define | LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
#define | LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
#define | LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set the voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get the voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop Mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop Mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledFlashPowerDown (void)
Check if the Flash Power Down in Stop Mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAnalogBooster (void)
Enable the Analog Voltage Booster (VDDA)
__STATIC_INLINE void | LL_PWR_DisableAnalogBooster (void)
Disable the Analog Voltage Booster (VDDA)
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAnalogBooster (void)
Check if the Analog Voltage Booster (VDDA) is enabled.
__STATIC_INLINE void | LL_PWR_EnableAnalogVoltageReady (void)
Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready.
__STATIC_INLINE void | LL_PWR_DisableAnalogVoltageReady (void)
Disable the Analog Voltage Ready (VDDA)
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAnalogVoltageReady (void)
Check if the Analog Voltage Booster (VDDA) is enabled.
__STATIC_INLINE void | LL_PWR_SetStopModeRegulVoltageScaling (uint32_t VoltageScaling)
Set the internal Regulator output voltage in STOP mode.
__STATIC_INLINE uint32_t | LL_PWR_GetStopModeRegulVoltageScaling (void)
Get the internal Regulator output voltage in STOP mode.
__STATIC_INLINE void | LL_PWR_EnableAVD (void)
Enable Analog Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisableAVD (void)
Disable Analog Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAVD (void)
Check if Analog Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_SetAVDLevel (uint32_t AVDLevel)
Configure the voltage threshold to be detected by the Analog Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetAVDLevel (void)
Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM1ShutOff (void)
Enable the AXI RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM1ShutOff (void)
Disable the AXI RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM1ShutOff (void)
Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM2ShutOff (void)
Enable the AXI RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM2ShutOff (void)
Disable the AXI RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM2ShutOff (void)
Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAXIRAM3ShutOff (void)
Enable the AXI RAM3 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAXIRAM3ShutOff (void)
Disable the AXI RAM3 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAXIRAM3ShutOff (void)
Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAHBRAM1ShutOff (void)
Enable the AHB RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAHBRAM1ShutOff (void)
Disable the AHB RAM1 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAHBRAM1ShutOff (void)
Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableAHBRAM2ShutOff (void)
Enable the AHB RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableAHBRAM2ShutOff (void)
Disable the AHB RAM2 shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledAHBRAM2ShutOff (void)
Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableITCMSOShutOff (void)
Enable the ITCM shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableITCMSOShutOff (void)
Disable the ITCM shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledITCMShutOff (void)
Check if the ITCM shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableHSITFShutOff (void)
Enable the USB and FDCAN shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableHSITFShutOff (void)
Disable the USB and FDCAN shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledHSITFShutOff (void)
Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRDRAMShutOff (void)
Enable the SRD AHB RAM shut-off in DStop/DStop2 mode.
__STATIC_INLINE void | LL_PWR_DisableSRDRAMShutOff (void)
Disable the SRD AHB RAM shut-off in DStop/DStop2 mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRDRAMShutOff (void)
Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableBkUpRegulator (void)
Enable Backup Regulator.
__STATIC_INLINE void | LL_PWR_DisableBkUpRegulator (void)
Disable Backup Regulator.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpRegulator (void)
Check if the backup Regulator is enabled.
__STATIC_INLINE void | LL_PWR_EnableMonitoring (void)
Enable VBAT and Temperature monitoring.
__STATIC_INLINE void | LL_PWR_DisableMonitoring (void)
Disable VBAT and Temperature monitoring.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledMonitoring (void)
Check if the VBAT and Temperature monitoring is enabled.
__STATIC_INLINE void | LL_PWR_ConfigSupply (uint32_t SupplySource)
Configure the PWR supply.
__STATIC_INLINE uint32_t | LL_PWR_GetSupply (void)
Get the PWR supply.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the Battery charge resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the Battery charge resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableUSBReg (void)
Enable the USB regulator.
__STATIC_INLINE void | LL_PWR_DisableUSBReg (void)
Disable the USB regulator.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUSBReg (void)
Check if the USB regulator is enabled.
__STATIC_INLINE void | LL_PWR_EnableUSBVoltageDetector (void)
Enable the USB voltage detector.
__STATIC_INLINE void | LL_PWR_DisableUSBVoltageDetector (void)
Disable the USB voltage detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUSBVoltageDetector (void)
Check if the USB voltage detector is enabled.
__STATIC_INLINE void | LL_PWR_CPU_SetCDPowerMode (uint32_t PDMode)
Set the CPU domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_CPU_GetCDPowerMode (void)
Get the CD Domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_CPU_SetSRDPowerMode (uint32_t PDMode)
Set the SRD domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_CPU_GetD3PowerMode (void)
Get the D3 Domain Power Down mode when the CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_CPU_EnableSRDRunInLowPowerMode (void)
SRD domain remains in Run mode regardless of CPU subsystem modes.
__STATIC_INLINE void | LL_PWR_CPU_DisableSRDRunInLowPowerMode (void)
SRD domain follows CPU subsystem modes.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode (void)
Check if SRD is kept in Run mode when CPU enters low power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal Regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal Regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullNone (uint32_t WakeUpPin)
Set the Wake-Up pin Pull None.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullUp (uint32_t WakeUpPin)
Set the Wake-Up pin Pull Up.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPullDown (uint32_t WakeUpPin)
Set the Wake-Up pin Pull Down.
__STATIC_INLINE uint32_t | LL_PWR_GetWakeUpPinPull (uint32_t WakeUpPin)
Get the Wake-Up pin pull.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_ACTVOS (void)
Indicate whether the voltage level is ready for current actual used VOS.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_AVDO (void)
Indicate whether VDDA voltage is below the selected AVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_MMCVDO (void)
Indicate whether VDDMMC voltage is below 1V2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BRR (void)
Get Backup Regulator ready Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VBATL (void)
Indicate whether the VBAT level is above or below low threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VBATH (void)
Indicate whether the VBAT level is above or below high threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_TEMPL (void)
Indicate whether the CPU temperature level is above or below low threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_TEMPH (void)
Indicate whether the CPU temperature level is above or below high threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SMPSEXT (void)
Indicate whether the SMPS external supply is ready or not.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_USB (void)
Indicate whether the USB supply is ready or not.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsActiveFlag_STOP (void)
Get CPU System Stop Flag.
__STATIC_INLINE uint32_t | LL_PWR_CPU_IsActiveFlag_SB (void)
Get CPU System Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU6 (void)
Get Wake-up Flag 6.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_CPU (void)
Clear CPU STANDBY, STOP and HOLD flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU6 (void)
Clear Wake-up Flag 6.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_pwr.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rcc.h File Reference

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Data Structures | Defines | Functions | Variables
stm32h7xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32h7xx.h"
#include <math.h>

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
struct | LL_PLL_ClocksTypeDef
PLL Clocks Frequency Structure. More...

Defines

#define | CDCCIP 0x0UL
#define | CDCCIP1 0x4UL
#define | CDCCIP2 0x8UL
#define | SRDCCIP 0xCUL
#define | LL_RCC_REG_SHIFT 0U
#define | LL_RCC_POS_SHIFT 8U
#define | LL_RCC_CONFIG_SHIFT 16U
#define | LL_RCC_MASK_SHIFT 24U
#define | LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
#define | LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define | LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define | LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
#define | LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__)
#define | HSI48_VALUE 48000000U
#define | LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
#define | LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
#define | LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
#define | LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8
#define | LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
#define | LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1
#define | LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
#define | LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)
#define | LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
#define | LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)
#define | LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512
#define | LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1
#define | LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2
#define | LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4
#define | LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8
#define | LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16
#define | LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64
#define | LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128
#define | LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256
#define | LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512
#define | LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16
#define | LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16
#define | LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1
#define | LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2
#define | LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4
#define | LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8
#define | LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16
#define | LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1
#define | LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2
#define | LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4
#define | LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8
#define | LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16
#define | LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
#define | LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
#define | LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
#define | LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
#define | LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
#define | LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
#define | LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
#define | LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
#define | LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
#define | LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
#define | LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
#define | LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
#define | LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
#define | LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
#define | LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
#define | LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
#define | LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
#define | LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
#define | LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
#define | LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
#define | LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
#define | LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
#define | LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
#define | LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
#define | LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
#define | LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
#define | LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
#define | LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
#define | LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
#define | LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
#define | LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
#define | LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
#define | LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
#define | LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
#define | LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
#define | LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
#define | LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
#define | LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
#define | LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
#define | LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
#define | LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
#define | LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
#define | LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
#define | LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)
#define | LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)
#define | LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
#define | LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
#define | LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
#define | LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
#define | LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)
#define | LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)
#define | LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)
#define | LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)
#define | LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)
#define | LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)
#define | LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
#define | LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
#define | LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
#define | LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
#define | LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
#define | LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
#define | LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4
#define | LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P
#define | LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R
#define | LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE
#define | LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI
#define | LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP
#define | LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
#define | LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)
#define | LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)
#define | LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
#define | LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)
#define | LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)
#define | LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
#define | LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)
#define | LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)
#define | LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)
#define | LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
#define | LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)
#define | LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
#define | LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
#define | LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)
#define | LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
#define | LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)
#define | LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)
#define | LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
#define | LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
#define | LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)
#define | LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)
#define | LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
#define | LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
#define | LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)
#define | LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)
#define | LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
#define | LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)
#define | LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)
#define | LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)
#define | LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
#define | LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)
#define | LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)
#define | LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
#define | LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
#define | LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
#define | LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
#define | LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
#define | LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
#define | LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)
#define | LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)
#define | LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
#define | LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
#define | LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
#define | LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
#define | LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)
#define | LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)
#define | LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
#define | LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)
#define | LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)
#define | LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)
#define | LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
#define | LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
#define | LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
#define | LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)
#define | LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)
#define | LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
#define | LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
#define | LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)
#define | LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)
#define | LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
#define | LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)
#define | LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
#define | LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)
#define | LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)
#define | LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
#define | LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
#define | LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
#define | LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL
#define | LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
#define | LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
#define | LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */
#define | LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
#define | LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
#define | LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL
#define | LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL
#define | LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL
#define | LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL
#define | LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL
#define | LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL
#define | LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL
#define | LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL
#define | LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL
#define | LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
#define | LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
#define | LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL
#define | LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL
#define | LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL
#define | LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL
#define | LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
#define | LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
#define | LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
#define | LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
#define | LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
#define | LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
#define | LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE
#define | LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
#define | LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
#define | LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
#define | LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)
#define | LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */
#define | LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
Helper macro to calculate the SYSCLK frequency.
#define | LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])
Helper macro to calculate the PCLK3 frequency (APB3)
#define | LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])
Helper macro to calculate the PCLK4 frequency (ABP4)
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady
#define | LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_SelectAnalogClock (void)
Select the Analog HSE external clock type in Bypass mode.
__STATIC_INLINE void | LL_RCC_HSE_SelectDigitalClock (void)
Select the Digital HSE external clock type in Bypass mode.
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsDividerReady (void)
Check if HSI new divider applied and ready.
__STATIC_INLINE void | LL_RCC_HSI_SetDivider (uint32_t Divider)
Set HSI divider.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetDivider (void)
Get HSI divider.
__STATIC_INLINE void | LL_RCC_HSI_EnableStopMode (void)
Enable HSI oscillator in Stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableStopMode (void)
Disable HSI oscillator in Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_CSI_Enable (void)
Enable CSI oscillator.
__STATIC_INLINE void | LL_RCC_CSI_Disable (void)
Disable CSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_CSI_IsReady (void)
Check if CSI clock is ready.
__STATIC_INLINE void | LL_RCC_CSI_EnableStopMode (void)
Enable CSI oscillator in Stop mode.
__STATIC_INLINE void | LL_RCC_CSI_DisableStopMode (void)
Disable CSI oscillator in Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibration (void)
Get CSI Calibration value.
__STATIC_INLINE void | LL_RCC_CSI_SetCalibTrimming (uint32_t Value)
Set CSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibTrimming (void)
Get CSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48 oscillator.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48 oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.
__STATIC_INLINE uint32_t | LL_RCC_CPUCK_IsReady (void)
Check if CPU clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_CDCK_IsReady (void)
Check if CD clock is ready.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable the Clock Security System on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsFailureDetected (void)
Check if LSE failure is detected by Clock Security System.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SelectDigitalClock (void)
Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
__STATIC_INLINE void | LL_RCC_LSE_SelectAnalogClock (void)
Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetSysWakeUpClkSource (uint32_t Source)
Configure the system wakeup clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysWakeUpClkSource (void)
Get the system wakeup clock source.
__STATIC_INLINE void | LL_RCC_SetKerWakeUpClkSource (uint32_t Source)
Configure the kernel wakeup clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetKerWakeUpClkSource (void)
Get the kernel wakeup clock source.
__STATIC_INLINE void | LL_RCC_SetSysPrescaler (uint32_t Prescaler)
Set System prescaler.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB3Prescaler (uint32_t Prescaler)
Set APB3 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB4Prescaler (uint32_t Prescaler)
Set APB4 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetSysPrescaler (void)
Get System prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB3Prescaler (void)
Get APB3 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB4Prescaler (void)
Get APB4 prescaler.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetClockSource (uint32_t ClkSource)
Configure periph clock source.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t ClkSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t ClkSource)
Configure LPUARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t ClkSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t ClkSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t ClkSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetSDMMCClockSource (uint32_t ClkSource)
Configure SDMMCx clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t ClkSource)
Configure RNGx clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t ClkSource)
Configure USBx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t ClkSource)
Configure CECx clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDMClockSource (uint32_t ClkSource)
Configure DFSDMx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDM2ClockSource (uint32_t ClkSource)
Configure DFSDMx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetFMCClockSource (uint32_t ClkSource)
Configure FMCx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetOSPIClockSource (uint32_t ClkSource)
Configure OSPIx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetCLKPClockSource (uint32_t ClkSource)
Configure CLKP Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSPIClockSource (uint32_t ClkSource)
Configure SPIx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSPDIFClockSource (uint32_t ClkSource)
Configure SPDIFx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t ClkSource)
Configure FDCANx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetSWPClockSource (uint32_t ClkSource)
Configure SWPx Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ClkSource)
Configure ADCx Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetClockSource (uint32_t Periph)
Get periph clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t Periph)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t Periph)
Get LPUART clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t Periph)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t Periph)
Get LPTIM clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t Periph)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDMMCClockSource (uint32_t Periph)
Get SDMMC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t Periph)
Get RNG clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t Periph)
Get USB clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t Periph)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDMClockSource (uint32_t Periph)
Get DFSDM Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDM2ClockSource (uint32_t Periph)
Get DFSDM2 Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFMCClockSource (uint32_t Periph)
Get FMC Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetOSPIClockSource (uint32_t Periph)
Get OSPI Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCLKPClockSource (uint32_t Periph)
Get CLKP Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSPIClockSource (uint32_t Periph)
Get SPIx Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSPDIFClockSource (uint32_t Periph)
Get SPDIF Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t Periph)
Get FDCAN Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSWPClockSource (uint32_t Periph)
Get SWP Kernel clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t Periph)
Get ADC Kernel clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_SetRTC_HSEPrescaler (uint32_t Prescaler)
Set HSE Prescalers for RTC Clock.
__STATIC_INLINE uint32_t | LL_RCC_GetRTC_HSEPrescaler (void)
Get HSE Prescalers for RTC Clock.
__STATIC_INLINE void | LL_RCC_SetTIMPrescaler (uint32_t Prescaler)
Set Timers Clock Prescalers.
__STATIC_INLINE uint32_t | LL_RCC_GetTIMPrescaler (void)
Get Timers Clock Prescalers.
__STATIC_INLINE void | LL_RCC_PLL_SetSource (uint32_t PLLSource)
Set the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE void | LL_RCC_PLL1_Enable (void)
Enable PLL1.
__STATIC_INLINE void | LL_RCC_PLL1_Disable (void)
Disable PLL1.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_IsReady (void)
Check if PLL1 Ready.
__STATIC_INLINE void | LL_RCC_PLL1P_Enable (void)
Enable PLL1P.
__STATIC_INLINE void | LL_RCC_PLL1Q_Enable (void)
Enable PLL1Q.
__STATIC_INLINE void | LL_RCC_PLL1R_Enable (void)
Enable PLL1R.
__STATIC_INLINE void | LL_RCC_PLL1FRACN_Enable (void)
Enable PLL1 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL1P_IsEnabled (void)
Check if PLL1 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1Q_IsEnabled (void)
Check if PLL1 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1R_IsEnabled (void)
Check if PLL1 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL1FRACN_IsEnabled (void)
Check if PLL1 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL1P_Disable (void)
Disable PLL1P.
__STATIC_INLINE void | LL_RCC_PLL1Q_Disable (void)
Disable PLL1Q.
__STATIC_INLINE void | LL_RCC_PLL1R_Disable (void)
Disable PLL1R.
__STATIC_INLINE void | LL_RCC_PLL1FRACN_Disable (void)
Disable PLL1 FRACN.
__STATIC_INLINE void | LL_RCC_PLL1_SetVCOOutputRange (uint32_t VCORange)
Set PLL1 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL1_SetVCOInputRange (uint32_t InputRange)
Set PLL1 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetN (void)
Get PLL1 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetM (void)
Get PLL1 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetP (void)
Get PLL1 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetQ (void)
Get PLL1 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetR (void)
Get PLL1 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL1_GetFRACN (void)
Get PLL1 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetN (uint32_t N)
Set PLL1 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetM (uint32_t M)
Set PLL1 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetP (uint32_t P)
Set PLL1 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetQ (uint32_t Q)
Set PLL1 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetR (uint32_t R)
Set PLL1 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL1_SetFRACN (uint32_t FRACN)
Set PLL1 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_Enable (void)
Enable PLL2.
__STATIC_INLINE void | LL_RCC_PLL2_Disable (void)
Disable PLL2.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_IsReady (void)
Check if PLL2 Ready.
__STATIC_INLINE void | LL_RCC_PLL2P_Enable (void)
Enable PLL2P.
__STATIC_INLINE void | LL_RCC_PLL2Q_Enable (void)
Enable PLL2Q.
__STATIC_INLINE void | LL_RCC_PLL2R_Enable (void)
Enable PLL2R.
__STATIC_INLINE void | LL_RCC_PLL2FRACN_Enable (void)
Enable PLL2 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL2P_IsEnabled (void)
Check if PLL2 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2Q_IsEnabled (void)
Check if PLL2 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2R_IsEnabled (void)
Check if PLL2 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL2FRACN_IsEnabled (void)
Check if PLL2 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL2P_Disable (void)
Disable PLL2P.
__STATIC_INLINE void | LL_RCC_PLL2Q_Disable (void)
Disable PLL2Q.
__STATIC_INLINE void | LL_RCC_PLL2R_Disable (void)
Disable PLL2R.
__STATIC_INLINE void | LL_RCC_PLL2FRACN_Disable (void)
Disable PLL2 FRACN.
__STATIC_INLINE void | LL_RCC_PLL2_SetVCOOutputRange (uint32_t VCORange)
Set PLL2 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL2_SetVCOInputRange (uint32_t InputRange)
Set PLL2 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetN (void)
Get PLL2 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetM (void)
Get PLL2 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetP (void)
Get PLL2 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetQ (void)
Get PLL2 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetR (void)
Get PLL2 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL2_GetFRACN (void)
Get PLL2 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetN (uint32_t N)
Set PLL2 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetM (uint32_t M)
Set PLL2 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetP (uint32_t P)
Set PLL2 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetQ (uint32_t Q)
Set PLL2 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetR (uint32_t R)
Set PLL2 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL2_SetFRACN (uint32_t FRACN)
Set PLL2 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_Enable (void)
Enable PLL3.
__STATIC_INLINE void | LL_RCC_PLL3_Disable (void)
Disable PLL3.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_IsReady (void)
Check if PLL3 Ready.
__STATIC_INLINE void | LL_RCC_PLL3P_Enable (void)
Enable PLL3P.
__STATIC_INLINE void | LL_RCC_PLL3Q_Enable (void)
Enable PLL3Q.
__STATIC_INLINE void | LL_RCC_PLL3R_Enable (void)
Enable PLL3R.
__STATIC_INLINE void | LL_RCC_PLL3FRACN_Enable (void)
Enable PLL3 FRACN.
__STATIC_INLINE uint32_t | LL_RCC_PLL3P_IsEnabled (void)
Check if PLL3 P is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3Q_IsEnabled (void)
Check if PLL3 Q is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3R_IsEnabled (void)
Check if PLL3 R is enabled.
__STATIC_INLINE uint32_t | LL_RCC_PLL3FRACN_IsEnabled (void)
Check if PLL3 FRACN is enabled.
__STATIC_INLINE void | LL_RCC_PLL3P_Disable (void)
Disable PLL3P.
__STATIC_INLINE void | LL_RCC_PLL3Q_Disable (void)
Disable PLL3Q.
__STATIC_INLINE void | LL_RCC_PLL3R_Disable (void)
Disable PLL3R.
__STATIC_INLINE void | LL_RCC_PLL3FRACN_Disable (void)
Disable PLL3 FRACN.
__STATIC_INLINE void | LL_RCC_PLL3_SetVCOOutputRange (uint32_t VCORange)
Set PLL3 VCO OutputRange.
__STATIC_INLINE void | LL_RCC_PLL3_SetVCOInputRange (uint32_t InputRange)
Set PLL3 VCO Input Range.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetN (void)
Get PLL3 N Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetM (void)
Get PLL3 M Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetP (void)
Get PLL3 P Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetQ (void)
Get PLL3 Q Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetR (void)
Get PLL3 R Coefficient.
__STATIC_INLINE uint32_t | LL_RCC_PLL3_GetFRACN (void)
Get PLL3 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetN (uint32_t N)
Set PLL3 N Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetM (uint32_t M)
Set PLL3 M Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetP (uint32_t P)
Set PLL3 P Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetQ (uint32_t Q)
Set PLL3 Q Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetR (uint32_t R)
Set PLL3 R Coefficient.
__STATIC_INLINE void | LL_RCC_PLL3_SetFRACN (uint32_t FRACN)
Set PLL3 FRACN Coefficient.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_CSIRDY (void)
Clear CSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL1RDY (void)
Clear PLL1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL2RDY (void)
Clear PLL2 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLL3RDY (void)
Clear PLL3 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear HSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CSIRDY (void)
Check if CSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL1RDY (void)
Check if PLL1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL2RDY (void)
Check if PLL2 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL3RDY (void)
Check if PLL3 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if HSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power D1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDG1RST (void)
Check if RCC flag Window Watchdog 1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDG1RST (void)
Check if RCC flag Independent Watchdog 1 reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CDRST (void)
Check if RCC flag CD reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear all reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_CSIRDY (void)
Enable CSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL1RDY (void)
Enable PLL1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL2RDY (void)
Enable PLL2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLL3RDY (void)
Enable PLL3 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSECSS interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_CSIRDY (void)
Disable CSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL1RDY (void)
Disable PLL1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL2RDY (void)
Disable PLL2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLL3RDY (void)
Disable PLL3 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSECSS interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_CSIRDY (void)
Checks if CSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL1RDY (void)
Checks if PLL1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL2RDY (void)
Checks if PLL2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL3RDY (void)
Checks if PLL3 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.
void | LL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
uint32_t | LL_RCC_CalcPLLClockFreq (uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
Helper function to calculate the PLL frequency output.
void | LL_RCC_GetPLL1ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL1 clocks frequencies.
void | LL_RCC_GetPLL2ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL2 clocks frequencies.
void | LL_RCC_GetPLL3ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks)
Return PLL3 clocks frequencies.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUART clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADC clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMC clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNG clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USB clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetDFSDM2ClockFreq (uint32_t DFSDMxSource)
Return DFSDM clock frequency.
uint32_t | LL_RCC_GetSPDIFClockFreq (uint32_t SPDIFxSource)
Return SPDIF clock frequency.
uint32_t | LL_RCC_GetSPIClockFreq (uint32_t SPIxSource)
Return SPIx clock frequency.
uint32_t | LL_RCC_GetSWPClockFreq (uint32_t SWPxSource)
Return SWP clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN clock frequency.
uint32_t | LL_RCC_GetFMCClockFreq (uint32_t FMCxSource)
Return FMC clock frequency.
uint32_t | LL_RCC_GetOSPIClockFreq (uint32_t OSPIxSource)
Return OSPI clock frequency.
uint32_t | LL_RCC_GetCLKPClockFreq (uint32_t CLKPxSource)
Return CLKP clock frequency.

Variables

const uint8_t | LL_RCC_PrescTable [16]

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rcc.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rng.h File Reference

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stm32h7xx_ll_rng.h File Reference

Header file of RNG LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED
#define | LL_RNG_CLKDIV_BY_1 (0x00000000UL)
#define | LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
#define | LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
#define | LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
#define | LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
#define | LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
#define | LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
#define | LL_RNG_NIST_COMPLIANT (0x00000000UL)
#define | LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)
#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS
#define | LL_RNG_CR_IE RNG_CR_IE
#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.
__STATIC_INLINE void | LL_RNG_EnableCondReset (RNG_TypeDef *RNGx)
Set RNG Conditioning Soft Reset bit.
__STATIC_INLINE void | LL_RNG_DisableCondReset (RNG_TypeDef *RNGx)
Reset RNG Conditioning Soft Reset bit.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledCondReset (RNG_TypeDef *RNGx)
Check if RNG Conditioning Soft Reset bit is set.
__STATIC_INLINE void | LL_RNG_ConfigLock (RNG_TypeDef *RNGx)
Enable RNG Config Lock.
__STATIC_INLINE uint32_t | LL_RNG_IsConfigLocked (RNG_TypeDef *RNGx)
Check if RNG Config Lock is enabled.
__STATIC_INLINE void | LL_RNG_EnableNistCompliance (RNG_TypeDef *RNGx)
Enable NIST Compliance.
__STATIC_INLINE void | LL_RNG_DisableNistCompliance (RNG_TypeDef *RNGx)
Disable NIST Compliance.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledNistCompliance (RNG_TypeDef *RNGx)
Check if NIST Compliance is enabled.
__STATIC_INLINE void | LL_RNG_SetConfig1 (RNG_TypeDef *RNGx, uint32_t Config1)
Set RNG Config1 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig1 (RNG_TypeDef *RNGx)
Get RNG Config1 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetConfig2 (RNG_TypeDef *RNGx, uint32_t Config2)
Set RNG Config2 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig2 (RNG_TypeDef *RNGx)
Get RNG Config2 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetConfig3 (RNG_TypeDef *RNGx, uint32_t Config3)
Set RNG Config3 Configuration field value.
__STATIC_INLINE uint32_t | LL_RNG_GetConfig3 (RNG_TypeDef *RNGx)
Get RNG Config3 Configuration field value.
__STATIC_INLINE void | LL_RNG_SetClockDivider (RNG_TypeDef *RNGx, uint32_t Divider)
Set RNG Clock divider factor.
__STATIC_INLINE uint32_t | LL_RNG_GetClockDivider (RNG_TypeDef *RNGx)
Get RNG Clock divider factor.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.
__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.
__STATIC_INLINE void | LL_RNG_SetHealthConfig (RNG_TypeDef *RNGx, uint32_t HTCFG)
Set RNG Health Test Control.
__STATIC_INLINE uint32_t | LL_RNG_GetHealthConfig (RNG_TypeDef *RNGx)
Get RNG Health Test Control.
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.
ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

Header file of RNG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rng.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rtc.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE 0xFFU
#define | RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
#define | RTC_WRITE_PROTECTION_ENABLE_2 0x53U
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U
#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
#define | LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
#define | LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
#define | LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
#define | LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
#define | LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
#define | LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07
#define | LL_RTC_MONTH_JANUARY (uint8_t)0x01
#define | LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
#define | LL_RTC_MONTH_MARCH (uint8_t)0x03
#define | LL_RTC_MONTH_APRIL (uint8_t)0x04
#define | LL_RTC_MONTH_MAY (uint8_t)0x05
#define | LL_RTC_MONTH_JUNE (uint8_t)0x06
#define | LL_RTC_MONTH_JULY (uint8_t)0x07
#define | LL_RTC_MONTH_AUGUST (uint8_t)0x08
#define | LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
#define | LL_RTC_MONTH_OCTOBER (uint8_t)0x10
#define | LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
#define | LL_RTC_MONTH_DECEMBER (uint8_t)0x12
#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
#define | LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM
#define | LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM
#define | LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
#define | LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)
#define | LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)
#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U
#define | LL_RTC_BKP_DR20 0x00000014U
#define | LL_RTC_BKP_DR21 0x00000015U
#define | LL_RTC_BKP_DR22 0x00000016U
#define | LL_RTC_BKP_DR23 0x00000017U
#define | LL_RTC_BKP_DR24 0x00000018U
#define | LL_RTC_BKP_DR25 0x00000019U
#define | LL_RTC_BKP_DR26 0x0000001AU
#define | LL_RTC_BKP_DR27 0x0000001BU
#define | LL_RTC_BKP_DR28 0x0000001CU
#define | LL_RTC_BKP_DR29 0x0000001DU
#define | LL_RTC_BKP_DR30 0x0000001EU
#define | LL_RTC_BKP_DR31 0x0000001FU
#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in RTC register.
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (TAMP_TypeDef *TAMPx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (TAMP_TypeDef *TAMPx)
Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (TAMP_TypeDef *TAMPx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (TAMP_TypeDef *TAMPx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (TAMP_TypeDef *TAMPx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (TAMP_TypeDef *TAMPx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (TAMP_TypeDef *TAMPx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (TAMP_TypeDef *TAMPx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Clear tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Disable tamper 3 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (TAMP_TypeDef *TAMPx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (TAMP_TypeDef *TAMPx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (TAMP_TypeDef *TAMPx)
Check if tamper 3 interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableActiveMode (uint32_t Tamper)
Enable tamper active mode.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableActiveMode (uint32_t Tamper)
Disable tamper active mode.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableFilter (void)
Enable active tamper filter.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableFilter (void)
Disable active tamper filter.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod (uint32_t ActiveOutputChangePeriod)
Set Active tamper output change period.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod (void)
Get Active tamper output change period.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler (uint32_t ActiveAsynvPrescaler)
Set Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler (void)
Get Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_EnableOutputSharing (void)
Enable active tamper output sharing.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_DisableOutputSharing (void)
Disable active tamper output sharing.
__STATIC_INLINE void | LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection (uint32_t OutputSelection)
Set Active tamper output selection.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection (void)
Get Active tamper asynchronous prescaler clock selection.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ATAMP_INITS (void)
Get active tamper initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ATAMP_SEEDF (void)
Get active tamper seed running status flag.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_rtc.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_spi.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...
struct | LL_I2S_InitTypeDef
I2S Init structure definition. More...

Defines

#define | LL_SPI_SR_RXP (SPI_SR_RXP)
#define | LL_SPI_SR_TXP (SPI_SR_TXP)
#define | LL_SPI_SR_DXP (SPI_SR_DXP)
#define | LL_SPI_SR_EOT (SPI_SR_EOT)
#define | LL_SPI_SR_TXTF (SPI_SR_TXTF)
#define | LL_SPI_SR_UDR (SPI_SR_UDR)
#define | LL_SPI_SR_CRCE (SPI_SR_CRCE)
#define | LL_SPI_SR_MODF (SPI_SR_MODF)
#define | LL_SPI_SR_OVR (SPI_SR_OVR)
#define | LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
#define | LL_SPI_SR_TSERF (SPI_SR_TSERF)
#define | LL_SPI_SR_SUSP (SPI_SR_SUSP)
#define | LL_SPI_SR_TXC (SPI_SR_TXC)
#define | LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
#define | LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
#define | LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
#define | LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
#define | LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
#define | LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
#define | LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
#define | LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
#define | LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
#define | LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
#define | LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
#define | LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
#define | LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
#define | LL_SPI_MODE_SLAVE (0x00000000UL)
#define | LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
#define | LL_SPI_SS_LEVEL_LOW (0x00000000UL)
#define | LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
#define | LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
#define | LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
#define | LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
#define | LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define | LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define | LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define | LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
#define | LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
#define | LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
#define | LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
#define | LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define | LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define | LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define | LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define | LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
#define | LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define | LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
#define | LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
#define | LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
#define | LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
#define | LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
#define | LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
#define | LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
#define | LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
#define | LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
#define | LL_SPI_PHASE_1EDGE (0x00000000UL)
#define | LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
#define | LL_SPI_POLARITY_LOW (0x00000000UL)
#define | LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
#define | LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
#define | LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
#define | LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
#define | LL_SPI_MSB_FIRST (0x00000000UL)
#define | LL_SPI_FULL_DUPLEX (0x00000000UL)
#define | LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
#define | LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
#define | LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
#define | LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define | LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define | LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define | LL_SPI_FIFO_TH_01DATA (0x00000000UL)
#define | LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
#define | LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
#define | LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
#define | LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define | LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define | LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL)
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN)
#define | LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
#define | LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
#define | LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
#define | LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define | LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define | LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define | LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
#define | LL_SPI_NSS_HARD_INPUT (0x00000000UL)
#define | LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
#define | LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
#define | LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
#define | LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
#define | LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.
#define | LL_I2S_DATAFORMAT_16B (0x00000000UL)
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
#define | LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
#define | LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
#define | LL_I2S_POLARITY_LOW (0x00000000UL)
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
#define | LL_I2S_STANDARD_PHILIPS (0x00000000UL)
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | LL_I2S_MODE_SLAVE_TX (0x00000000UL)
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL)
#define | LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL)
#define | LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
#define | LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
#define | LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
#define | LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
#define | LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
#define | LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
#define | LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
#define | LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
#define | LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
#define | LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
#define | LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
#define | LL_I2S_AUDIOFREQ_192K 192000UL
#define | LL_I2S_AUDIOFREQ_96K 96000UL
#define | LL_I2S_AUDIOFREQ_48K 48000UL
#define | LL_I2S_AUDIOFREQ_44K 44100UL
#define | LL_I2S_AUDIOFREQ_32K 32000UL
#define | LL_I2S_AUDIOFREQ_22K 22050UL
#define | LL_I2S_AUDIOFREQ_16K 16000UL
#define | LL_I2S_AUDIOFREQ_11K 11025UL
#define | LL_I2S_AUDIOFREQ_8K 8000UL
#define | LL_I2S_AUDIOFREQ_DEFAULT 0UL
#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_EnableIOSwap (SPI_TypeDef *SPIx)
Swap the MOSI and MISO pin.
__STATIC_INLINE void | LL_SPI_DisableIOSwap (SPI_TypeDef *SPIx)
Restore default function for MOSI and MISO pin.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOSwap (SPI_TypeDef *SPIx)
Check if MOSI and MISO pin are swapped.
__STATIC_INLINE void | LL_SPI_EnableGPIOControl (SPI_TypeDef *SPIx)
Enable GPIO control.
__STATIC_INLINE void | LL_SPI_DisableGPIOControl (SPI_TypeDef *SPIx)
Disable GPIO control.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledGPIOControl (SPI_TypeDef *SPIx)
Check if GPIO control is active.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI Mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI Mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetMasterSSIdleness (SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
Configure the Idleness applied by master between active edge of SS and first send data.
__STATIC_INLINE uint32_t | LL_SPI_GetMasterSSIdleness (SPI_TypeDef *SPIx)
Get the configured Idleness applied by master.
__STATIC_INLINE void | LL_SPI_SetInterDataIdleness (SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
Configure the idleness applied by master between data frame.
__STATIC_INLINE uint32_t | LL_SPI_GetInterDataIdleness (SPI_TypeDef *SPIx)
Get the configured inter data idleness.
__STATIC_INLINE void | LL_SPI_SetTransferSize (SPI_TypeDef *SPIx, uint32_t Count)
Set transfer size.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferSize (SPI_TypeDef *SPIx)
Get transfer size.
__STATIC_INLINE void | LL_SPI_SetReloadSize (SPI_TypeDef *SPIx, uint32_t Count)
Set reload transfer size.
__STATIC_INLINE uint32_t | LL_SPI_GetReloadSize (SPI_TypeDef *SPIx)
Get reload transfer size.
__STATIC_INLINE void | LL_SPI_EnableIOLock (SPI_TypeDef *SPIx)
Lock the AF configuration of associated IOs.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOLock (SPI_TypeDef *SPIx)
Check if the AF configuration is locked.
__STATIC_INLINE void | LL_SPI_SetTxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
Set Tx CRC Initialization Pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRCInitPattern (SPI_TypeDef *SPIx)
Get Tx CRC Initialization Pattern.
__STATIC_INLINE void | LL_SPI_SetRxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
Set Rx CRC Initialization Pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRCInitPattern (SPI_TypeDef *SPIx)
Get Rx CRC Initialization Pattern.
__STATIC_INLINE void | LL_SPI_SetInternalSSLevel (SPI_TypeDef *SPIx, uint32_t SSLevel)
Set internal SS input level ignoring what comes from PIN.
__STATIC_INLINE uint32_t | LL_SPI_GetInternalSSLevel (SPI_TypeDef *SPIx)
Get internal SS input level.
__STATIC_INLINE void | LL_SPI_EnableFullSizeCRC (SPI_TypeDef *SPIx)
Enable CRC computation on 33/17 bits.
__STATIC_INLINE void | LL_SPI_DisableFullSizeCRC (SPI_TypeDef *SPIx)
Disable CRC computation on 33/17 bits.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledFullSizeCRC (SPI_TypeDef *SPIx)
Check if Enable CRC computation on 33/17 bits is enabled.
__STATIC_INLINE void | LL_SPI_SuspendMasterTransfer (SPI_TypeDef *SPIx)
Suspend an ongoing transfer for Master configuration.
__STATIC_INLINE void | LL_SPI_StartMasterTransfer (SPI_TypeDef *SPIx)
Start effective transfer on wire for Master configuration.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveMasterTransfer (SPI_TypeDef *SPIx)
Check if there is an unfinished master transfer.
__STATIC_INLINE void | LL_SPI_EnableMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Enable Master Rx auto suspend in case of overrun.
__STATIC_INLINE void | LL_SPI_DisableMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Disable Master Rx auto suspend in case of overrun.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledMasterRxAutoSuspend (SPI_TypeDef *SPIx)
Check if Master Rx auto suspend is activated.
__STATIC_INLINE void | LL_SPI_SetUDRConfiguration (SPI_TypeDef *SPIx, uint32_t UDRConfig)
Set Underrun behavior.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRConfiguration (SPI_TypeDef *SPIx)
Get Underrun behavior.
__STATIC_INLINE void | LL_SPI_SetUDRDetection (SPI_TypeDef *SPIx, uint32_t UDRDetection)
Set Underrun Detection method.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRDetection (SPI_TypeDef *SPIx)
Get Underrun Detection method.
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set Serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get Serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set Clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get Clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set Clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get Clock polarity.
__STATIC_INLINE void | LL_SPI_SetNSSPolarity (SPI_TypeDef *SPIx, uint32_t NSSPolarity)
Set NSS polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSPolarity (SPI_TypeDef *SPIx)
Get NSS polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t Baudrate)
Set Baudrate Prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get Baudrate Prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set Transfer Bit Order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get Transfer Bit Order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set Transfer Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get Transfer Mode.
__STATIC_INLINE void | LL_SPI_SetHalfDuplexDirection (SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
Set direction for Half-Duplex Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetHalfDuplexDirection (SPI_TypeDef *SPIx)
Get direction for Half-Duplex Mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set Frame Data Size.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get Frame Data Size.
__STATIC_INLINE void | LL_SPI_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of FIFO that triggers a transfer event.
__STATIC_INLINE uint32_t | LL_SPI_GetFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of FIFO that triggers a transfer event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS Mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Set NSS Mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse mgt.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse mgt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXP (SPI_TypeDef *SPIx)
Check if there is enough data in FIFO to read a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXP (SPI_TypeDef *SPIx)
Check if there is enough space in FIFO to hold a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_DXP (SPI_TypeDef *SPIx)
Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_EOT (SPI_TypeDef *SPIx)
Check that end of transfer event occured.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXTF (SPI_TypeDef *SPIx)
Check that all required data has been filled in the fifo according to transfer size.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get Underrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get Mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get Overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get TI Frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TSER (SPI_TypeDef *SPIx)
Check if the additional number of data has been reloaded.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_SUSP (SPI_TypeDef *SPIx)
Check if a suspend operation is done.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXC (SPI_TypeDef *SPIx)
Check if last TxFIFO or CRC frame transmission is completed.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXWNE (SPI_TypeDef *SPIx)
Check if at least one 32-bit data is available in RxFIFO.
__STATIC_INLINE uint32_t | LL_SPI_GetRemainingDataFrames (SPI_TypeDef *SPIx)
Get number of data framed remaining in current TSIZE.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOPackingLevel (SPI_TypeDef *SPIx)
Get RxFIFO packing Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_EOT (SPI_TypeDef *SPIx)
Clear End Of Transfer flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_TXTF (SPI_TypeDef *SPIx)
Clear TXTF flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear Underrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear Overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear Mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear Frame format error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_TSER (SPI_TypeDef *SPIx)
Clear TSER flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_SUSP (SPI_TypeDef *SPIx)
Clear SUSP flag.
__STATIC_INLINE void | LL_SPI_EnableIT_RXP (SPI_TypeDef *SPIx)
Enable Rx Packet available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TXP (SPI_TypeDef *SPIx)
Enable Tx Packet space available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_DXP (SPI_TypeDef *SPIx)
Enable Duplex Packet available IT.
__STATIC_INLINE void | LL_SPI_EnableIT_EOT (SPI_TypeDef *SPIx)
Enable End Of Transfer IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TXTF (SPI_TypeDef *SPIx)
Enable TXTF IT.
__STATIC_INLINE void | LL_SPI_EnableIT_UDR (SPI_TypeDef *SPIx)
Enable Underrun IT.
__STATIC_INLINE void | LL_SPI_EnableIT_OVR (SPI_TypeDef *SPIx)
Enable Overrun IT.
__STATIC_INLINE void | LL_SPI_EnableIT_CRCERR (SPI_TypeDef *SPIx)
Enable CRC Error IT.
__STATIC_INLINE void | LL_SPI_EnableIT_FRE (SPI_TypeDef *SPIx)
Enable TI Frame Format Error IT.
__STATIC_INLINE void | LL_SPI_EnableIT_MODF (SPI_TypeDef *SPIx)
Enable MODF IT.
__STATIC_INLINE void | LL_SPI_EnableIT_TSER (SPI_TypeDef *SPIx)
Enable TSER reload IT.
__STATIC_INLINE void | LL_SPI_DisableIT_RXP (SPI_TypeDef *SPIx)
Disable Rx Packet available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TXP (SPI_TypeDef *SPIx)
Disable Tx Packet space available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_DXP (SPI_TypeDef *SPIx)
Disable Duplex Packet available IT.
__STATIC_INLINE void | LL_SPI_DisableIT_EOT (SPI_TypeDef *SPIx)
Disable End Of Transfer IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TXTF (SPI_TypeDef *SPIx)
Disable TXTF IT.
__STATIC_INLINE void | LL_SPI_DisableIT_UDR (SPI_TypeDef *SPIx)
Disable Underrun IT.
__STATIC_INLINE void | LL_SPI_DisableIT_OVR (SPI_TypeDef *SPIx)
Disable Overrun IT.
__STATIC_INLINE void | LL_SPI_DisableIT_CRCERR (SPI_TypeDef *SPIx)
Disable CRC Error IT.
__STATIC_INLINE void | LL_SPI_DisableIT_FRE (SPI_TypeDef *SPIx)
Disable TI Frame Format Error IT.
__STATIC_INLINE void | LL_SPI_DisableIT_MODF (SPI_TypeDef *SPIx)
Disable MODF IT.
__STATIC_INLINE void | LL_SPI_DisableIT_TSER (SPI_TypeDef *SPIx)
Disable TSER reload IT.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXP (SPI_TypeDef *SPIx)
Check if Rx Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXP (SPI_TypeDef *SPIx)
Check if Tx Packet space available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_DXP (SPI_TypeDef *SPIx)
Check if Duplex Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_EOT (SPI_TypeDef *SPIx)
Check if End Of Transfer IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXTF (SPI_TypeDef *SPIx)
Check if TXTF IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_UDR (SPI_TypeDef *SPIx)
Check if Underrun IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_OVR (SPI_TypeDef *SPIx)
Check if Overrun IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_CRCERR (SPI_TypeDef *SPIx)
Check if CRC Error IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_FRE (SPI_TypeDef *SPIx)
Check if TI Frame Format Error IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_MODF (SPI_TypeDef *SPIx)
Check if MODF IT is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TSER (SPI_TypeDef *SPIx)
Check if TSER reload IT is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint32_t | LL_SPI_ReceiveData32 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calcul.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calcul.
__STATIC_INLINE void | LL_SPI_SetUDRPattern (SPI_TypeDef *SPIx, uint32_t Pattern)
Set the underrun pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetUDRPattern (SPI_TypeDef *SPIx)
Get the underrun pattern.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataLength)
Set I2S Data frame format.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S Data frame format.
__STATIC_INLINE void | LL_I2S_SetChannelLengthType (SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
Set I2S Channel Length Type.
__STATIC_INLINE uint32_t | LL_I2S_GetChannelLengthType (SPI_TypeDef *SPIx)
Get I2S Channel Length Type.
__STATIC_INLINE void | LL_I2S_EnableWordSelectInversion (SPI_TypeDef *SPIx)
Invert the default polarity of WS signal.
__STATIC_INLINE void | LL_I2S_DisableWordSelectInversion (SPI_TypeDef *SPIx)
Use the default polarity of WS signal.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledWordSelectInversion (SPI_TypeDef *SPIx)
Check if polarity of WS signal is inverted.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set 2S Clock Polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get 2S Clock Polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S config.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S config.
__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral and disable I2S mode.
__STATIC_INLINE void | LL_I2S_EnableIOSwap (SPI_TypeDef *SPIx)
Swap the SDO and SDI pin.
__STATIC_INLINE void | LL_I2S_DisableIOSwap (SPI_TypeDef *SPIx)
Restore default function for SDO and SDI pin.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOSwap (SPI_TypeDef *SPIx)
Check if SDO and SDI pin are swapped.
__STATIC_INLINE void | LL_I2S_EnableGPIOControl (SPI_TypeDef *SPIx)
Enable GPIO control.
__STATIC_INLINE void | LL_I2S_DisableGPIOControl (SPI_TypeDef *SPIx)
Disable GPIO control.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledGPIOControl (SPI_TypeDef *SPIx)
Check if GPIO control is active.
__STATIC_INLINE void | LL_I2S_EnableIOLock (SPI_TypeDef *SPIx)
Lock the AF configuration of associated IOs.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOLock (SPI_TypeDef *SPIx)
Check if the the SPI_CFG2 register is locked.
__STATIC_INLINE void | LL_I2S_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set Transfer Bit Order.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get Transfer Bit Order.
__STATIC_INLINE void | LL_I2S_StartTransfer (SPI_TypeDef *SPIx)
Start effective transfer on wire.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveTransfer (SPI_TypeDef *SPIx)
Check if there is an unfinished transfer.
__STATIC_INLINE void | LL_I2S_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of FIFO that triggers a transfer event.
__STATIC_INLINE uint32_t | LL_I2S_GetFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of FIFO that triggers a transfer event.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the Master Clock Output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the Master Clock Ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXP (SPI_TypeDef *SPIx)
Check if there enough data in FIFO to read a full packet.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXP (SPI_TypeDef *SPIx)
Check if there enough space in FIFO to hold a full packet.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get Underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get Overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get TI Frame format error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear Underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear Overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear Frame format error flag.
__STATIC_INLINE void | LL_I2S_EnableIT_RXP (SPI_TypeDef *SPIx)
Enable Rx Packet available IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXP (SPI_TypeDef *SPIx)
Enable Tx Packet space available IT.
__STATIC_INLINE void | LL_I2S_EnableIT_UDR (SPI_TypeDef *SPIx)
Enable Underrun IT.
__STATIC_INLINE void | LL_I2S_EnableIT_OVR (SPI_TypeDef *SPIx)
Enable Overrun IT.
__STATIC_INLINE void | LL_I2S_EnableIT_FRE (SPI_TypeDef *SPIx)
Enable TI Frame Format Error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXP (SPI_TypeDef *SPIx)
Disable Rx Packet available IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXP (SPI_TypeDef *SPIx)
Disable Tx Packet space available IT.
__STATIC_INLINE void | LL_I2S_DisableIT_UDR (SPI_TypeDef *SPIx)
Disable Underrun IT.
__STATIC_INLINE void | LL_I2S_DisableIT_OVR (SPI_TypeDef *SPIx)
Disable Overrun IT.
__STATIC_INLINE void | LL_I2S_DisableIT_FRE (SPI_TypeDef *SPIx)
Disable TI Frame Format Error IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXP (SPI_TypeDef *SPIx)
Check if Rx Packet available IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXP (SPI_TypeDef *SPIx)
Check if Tx Packet space available IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_UDR (SPI_TypeDef *SPIx)
Check if Underrun IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_OVR (SPI_TypeDef *SPIx)
Check if Overrun IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_FRE (SPI_TypeDef *SPIx)
Check if TI Frame Format Error IT is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE uint32_t | LL_I2S_ReceiveData32 (SPI_TypeDef *SPIx)
Read Data Register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write Data Register.
__STATIC_INLINE void | LL_I2S_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData)
Write Data Register.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_spi.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_swpmi.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_swpmi.h File Reference

Header file of SWPMI LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SWPMI_InitTypeDef
SWPMI Init structures definition. More...

Defines

#define | LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF
#define | LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF
#define | LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF
#define | LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF
#define | LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF
#define | LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF
#define | LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF
#define | LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF
#define | LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF
#define | LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF
#define | LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF
#define | LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF
#define | LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE
#define | LL_SWPMI_ISR_TXE SWPMI_ISR_TXE
#define | LL_SWPMI_ISR_TCF SWPMI_ISR_TCF
#define | LL_SWPMI_ISR_SRF SWPMI_ISR_SRF
#define | LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP
#define | LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF
#define | LL_SWPMI_IER_SRIE SWPMI_IER_SRIE
#define | LL_SWPMI_IER_TCIE SWPMI_IER_TCIE
#define | LL_SWPMI_IER_TIE SWPMI_IER_TIE
#define | LL_SWPMI_IER_RIE SWPMI_IER_RIE
#define | LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE
#define | LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE
#define | LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE
#define | LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE
#define | LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE
#define | LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE
#define | LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE
#define | LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
#define | LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0
#define | LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1
#define | LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SWPMI register.
#define | LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SWPMI register.
#define | __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Functions

__STATIC_INLINE void | LL_SWPMI_SetReceptionMode (SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
Set Reception buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceptionMode (SWPMI_TypeDef *SWPMIx)
Get Reception buffering mode.
__STATIC_INLINE void | LL_SWPMI_SetTransmissionMode (SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
Set Transmission buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetTransmissionMode (SWPMI_TypeDef *SWPMIx)
Get Transmission buffering mode.
__STATIC_INLINE void | LL_SWPMI_EnableLoopback (SWPMI_TypeDef *SWPMIx)
Enable loopback mode.
__STATIC_INLINE void | LL_SWPMI_DisableLoopback (SWPMI_TypeDef *SWPMIx)
Disable loopback mode.
__STATIC_INLINE void | LL_SWPMI_EnableTransceiver (SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver.
__STATIC_INLINE void | LL_SWPMI_DisableTransceiver (SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledTransceiver (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is enabled.
__STATIC_INLINE void | LL_SWPMI_Activate (SWPMI_TypeDef *SWPMIx)
Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActivated (SWPMI_TypeDef *SWPMIx)
Check if Single wire protocol bus is in ACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_Deactivate (SWPMI_TypeDef *SWPMIx)
Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)
__STATIC_INLINE void | LL_SWPMI_RequestDeactivation (SWPMI_TypeDef *SWPMIx)
Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)
__STATIC_INLINE void | LL_SWPMI_SetBitRatePrescaler (SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
__STATIC_INLINE uint32_t | LL_SWPMI_GetBitRatePrescaler (SWPMI_TypeDef *SWPMIx)
Get Bitrate prescaler.
__STATIC_INLINE void | LL_SWPMI_SetVoltageClass (SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
Set SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_GetVoltageClass (SWPMI_TypeDef *SWPMIx)
Get SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Check if the last word of the frame under reception has arrived in SWPMI_RDR.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Frame transmission buffer has been emptied.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Check if CRC error in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Overrun in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if underrun error in transmission has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXNE (SWPMI_TypeDef *SWPMIx)
Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXE (SWPMI_TypeDef *SWPMIx)
Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TC (SWPMI_TypeDef *SWPMIx)
Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SR (SWPMI_TypeDef *SWPMIx)
Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SUSP (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in SUSPENDED or DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_DEACT (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RDYF (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is ready.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Clear receive buffer full flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Clear transmit buffer empty flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Clear receive CRC error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Clear receive overrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Clear transmit underrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TC (SWPMI_TypeDef *SWPMIx)
Clear transfer complete flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_SR (SWPMI_TypeDef *SWPMIx)
Clear slave resume flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RDY (SWPMI_TypeDef *SWPMIx)
Clear SWPMI transceiver ready flag.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RDY (SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver ready interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_SR (SWPMI_TypeDef *SWPMIx)
Enable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TC (SWPMI_TypeDef *SWPMIx)
Enable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TX (SWPMI_TypeDef *SWPMIx)
Enable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RX (SWPMI_TypeDef *SWPMIx)
Enable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Enable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Enable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Enable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Enable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Enable Receive buffer full interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RDY (SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver ready interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_SR (SWPMI_TypeDef *SWPMIx)
Disable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TC (SWPMI_TypeDef *SWPMIx)
Disable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TX (SWPMI_TypeDef *SWPMIx)
Disable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RX (SWPMI_TypeDef *SWPMIx)
Disable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Disable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Disable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Disable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Disable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Disable Receive buffer full interrupt.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RDY (SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver ready interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_SR (SWPMI_TypeDef *SWPMIx)
Check if Slave resume interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TC (SWPMI_TypeDef *SWPMIx)
Check if Transmit complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TX (SWPMI_TypeDef *SWPMIx)
Check if Transmit interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RX (SWPMI_TypeDef *SWPMIx)
Check if Receive interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if Transmit underrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Receive overrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBER (SWPMI_TypeDef *SWPMIx)
Check if Receive CRC error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Transmit buffer empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBF (SWPMI_TypeDef *SWPMIx)
Check if Receive buffer full interrupt is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for reception.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for reception.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for reception is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for transmission.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for transmission.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for transmission is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_DMA_GetRegAddr (SWPMI_TypeDef *SWPMIx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceiveFrameLength (SWPMI_TypeDef *SWPMIx)
Retrieve number of data bytes present in payload of received frame.
__STATIC_INLINE void | LL_SWPMI_TransmitData32 (SWPMI_TypeDef *SWPMIx, uint32_t TxData)
Transmit Data Register.
__STATIC_INLINE uint32_t | LL_SWPMI_ReceiveData32 (SWPMI_TypeDef *SWPMIx)
Receive Data Register.
__STATIC_INLINE void | LL_SWPMI_EnableTXBypass (SWPMI_TypeDef *SWPMIx)
Enable SWP Transceiver Bypass.
__STATIC_INLINE void | LL_SWPMI_DisableTXBypass (SWPMI_TypeDef *SWPMIx)
Disable SWP Transceiver Bypass.
ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Detailed Description

Header file of SWPMI LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_swpmi.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_system.h File Reference

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Defines | Functions
stm32h7xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
#define | LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
#define | LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
#define | LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
#define | LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
#define | LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
#define | LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
#define | LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
#define | LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
#define | LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
#define | LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
#define | LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
#define | LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
#define | LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
#define | LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
#define | LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN
#define | LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTF 5U
#define | LL_SYSCFG_EXTI_PORTG 6U
#define | LL_SYSCFG_EXTI_PORTH 7U
#define | LL_SYSCFG_EXTI_PORTI 8U
#define | LL_SYSCFG_EXTI_PORTJ 9U
#define | LL_SYSCFG_EXTI_PORTK 10U
#define | LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U)
#define | LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML
#define | LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML
#define | LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML
#define | LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L
#define | LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L
#define | LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L
#define | LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L
#define | LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML
#define | LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L
#define | LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL
#define | LL_SYSCFG_CELL_CODE 0U
#define | LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
#define | LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
#define | LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
#define | LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
#define | LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
#define | LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
#define | LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
#define | LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
#define | LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
#define | LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
#define | LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7
#define | LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12
#define | LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13
#define | LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3
#define | LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17
#define | LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM
#define | LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1
#define | LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4
#define | LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2
#define | LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3
#define | LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4
#define | LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5
#define | LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC
#define | LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1
#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
#define | LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN

Functions

__STATIC_INLINE void | LL_SYSCFG_OpenAnalogSwitch (uint32_t AnalogSwitch)
Open an Analog Switch.
__STATIC_INLINE void | LL_SYSCFG_CloseAnalogSwitch (uint32_t AnalogSwitch)
Close an Analog Switch.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 and HRTIM Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 and HRTIM Break inputs.
__STATIC_INLINE void | LL_SYSCFG_EnableCompensationCell (void)
Enable the Compensation Cell.
__STATIC_INLINE void | LL_SYSCFG_DisableCompensationCell (void)
Disable the Compensation Cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledCompensationCell (void)
Check if the Compensation Cell is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CMPCR (void)
Get Compensation Cell ready Flag.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization1 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization2 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization3 (void)
Enable the I/O speed optimization when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization1 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization2 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization3 (void)
To Disable optimize the I/O speed when the product voltage is low.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization1 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization2 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization3 (void)
Check if the I/O speed optimization is enabled.
__STATIC_INLINE void | LL_SYSCFG_SetCellCompensationCode (uint32_t CompCode)
Set the code selection for the I/O Compensation cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetCellCompensationCode (void)
Get the code selected for the I/O Compensation cell.
__STATIC_INLINE uint32_t | LL_SYSCFG_MMCGetCellCompensationCode (void)
Get the code selected for the I/O Compensation cell on the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationValue (void)
Get I/O compensation cell value for PMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationValue (void)
Get I/O compensation cell value for NMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_SetPMOSCompensationCode (uint32_t PMOSCode)
Set I/O compensation cell code for PMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationCode (void)
Get I/O compensation cell code for PMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_MMCSetPMOSCompensationCode (uint32_t PMOSCode)
Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_MMCGetPMOSCompensationCode (void)
Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail.
__STATIC_INLINE void | LL_SYSCFG_SetNMOSCompensationCode (uint32_t NMOSCode)
Set I/O compensation cell code for NMOS transistors.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationCode (void)
Get I/O compensation cell code for NMOS transistors.
__STATIC_INLINE void | LL_SYSCFG_VDMMCSetNMOSCompensationCode (uint32_t NMOSCode)
Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_SYSCFG_VDMMCGetNMOSCompensationCode (void)
Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInSleepMode (void)
Enable D1 Domain/CDomain debug during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInSleepMode (void)
Disable D1 Domain/CDomain debug during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStopMode (void)
Enable D1 Domain/CDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStopMode (void)
Disable D1 Domain/CDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStandbyMode (void)
Enable D1 Domain/CDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStandbyMode (void)
Disable D1 Domain/CDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStopMode (void)
Enable D3 Domain/SRDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStopMode (void)
Disable D3 Domain/SRDomain debug during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStandbyMode (void)
Enable D3 Domain/SRDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStandbyMode (void)
Disable D3 Domain/SRDomain debug during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableTracePortClock (void)
Enable the trace port clock.
__STATIC_INLINE void | LL_DBGMCU_DisableTracePortClock (void)
Disable the trace port clock.
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugClock (void)
Enable the Domain1/CDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugClock (void)
Disable the Domain1/CDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugClock (void)
Enable the Domain3/SRDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugClock (void)
Disable the Domain3/SRDomain debug clock enable.
__STATIC_INLINE void | LL_DBGMCU_SetExternalTriggerPinDirection (uint32_t PinDirection)
Set the direction of the bi-directional trigger pin TRGIO.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetExternalTriggerPinDirection (void)
Get the direction of the bi-directional trigger pin TRGIO.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 group1 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 group2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 group2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB3 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB3 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB4 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB4 peripherals.
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_system.h.

Generated on Tue Nov 12 2019 18:50:10 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32h7xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINE TIM1_AF1_BKINE
#define | TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E
#define | TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E
#define | TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P
#define | TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | TIMx_AF2_BK2INE TIM1_AF2_BK2INE
#define | TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E
#define | TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E
#define | TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E
#define | TIMx_AF2_BK2INP TIM1_AF2_BK2INP
#define | TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P
#define | TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR4 (TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | LL_TIM_TS_ITR12 (TIM_SMCR_TS_4)
#define | LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define | LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
#define | LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define | LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define | LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define | LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define | LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define | LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define | LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define | LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define | LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define | LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define | LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U
#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P
#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U
#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E
#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
#define | TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */
#define | TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
#define | TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
#define | TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
#define | TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
#define | TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */
#define | TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
#define | TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */
#define | TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
#define | TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
#define | TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
#define | TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
#define | TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
#define | TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
#define | TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
#define | TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
#define | TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
#define | TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
#define | TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
#define | TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
#define | TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
#define | TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
#define | TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
#define | TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
#define | TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
#define | TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_tim.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_usart.h File Reference

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Data Structures | Defines | Functions | Variables
stm32h7xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0
#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.
ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Variables

static const uint32_t | USART_PRESCALER_TAB []

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_usart.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_utils.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32h7xx.h"
#include "stm32h7xx_ll_system.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL
#define | LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL
#define | LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL
#define | LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL
#define | LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL
#define | LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL
#define | LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL
#define | LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL
#define | LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL
#define | LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL
#define | LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL
#define | LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL
#define | LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t CPU_Frequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t CPU_Frequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_utils.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_wwdg.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32h7xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_wwdg.h.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal.c File Reference

  • File List
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Defines | Functions | Variables
stm32h7xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32H7xx_HAL_VERSION_MAIN (0x01UL)
STM32H7xx HAL Driver version number V1.7.0RC2.
#define | __STM32H7xx_HAL_VERSION_SUB1 (0x07UL)
#define | __STM32H7xx_HAL_VERSION_SUB2 (0x00UL)
#define | __STM32H7xx_HAL_VERSION_RC (0x02UL)
#define | __STM32H7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
Return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_VDDMMC_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1/CDomain SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1/CDomain STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1/CDomain STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3/SRDomain STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3/SRDomain STANDBY mode.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c". More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR2_FIELDS
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
void | ADC_ConfigureBoostMode (ADC_HandleTypeDef *hadc)
Configure boost mode of selected ADC.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c".

Author:
MCD Application Team
  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.

  (+) Interrupt generation at the end of regular conversion and in case of
      analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) External trigger (timer or EXTI) with configurable polarity

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Configurable delay between conversions in Dual interleaved mode.

  (+) ADC channels selectable single/differential input.

  (+) ADC offset shared on 4 offset instances.
  (+) ADC calibration

  (+) ADC conversion of regular group.

  (+) ADC supply requirements: 1.62 V to 3.6 V.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
        (++) As prerequisite, ADC clock must be configured at RCC top level.

        (++) Two clock settings are mandatory:
             (+++) ADC clock (core clock, also possibly conversion clock).

             (+++) ADC clock (conversions clock).
                   Two possible clock sources: synchronous clock derived from AHB clock
                   or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.

             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)

               RCC_ADCCLKSOURCE_PLL2 enable:                   (optional: if asynchronous clock selected)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL2;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

        (++) ADC clock source and clock prescaler are configured at ADC level with
             parameter "ClockPrescaler" using function HAL_ADC_Init().

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, group regular, channels parameters ***
     ================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_DISABLE();                  (if not used anymore)
               RCC_ADCCLKSOURCE_CLKP restore:                      (optional)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_ADC_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     [..]

     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
     or @ref HAL_ADC_Init() function.
     [..]

     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_adc.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc_ex.c File Reference

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Defines | Functions
stm32h7xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c". More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (633600000U)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_FactorLoad (ADC_HandleTypeDef *hadc)
Load the calibration factor from engi bytes.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c".

Author:
MCD Application Team
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32h7xx_hal_adc.c".
  [..]
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_adc_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cec.c File Reference

  • File List
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Functions
stm32h7xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+++) Enable the clock for the CEC GPIOs.
            (+++) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+++) Configure the CEC interrupt priority.
            (+++) Enable the NVIC CEC IRQ handle.
            (+++) The specific CEC interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                  and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

  [..]
    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
  to register an interrupt callback.

  Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback     : Tx Transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CEC MspInit.
    (+) MspDeInitCallback  : CEC MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
  @ref HAL_CEC_RegisterRxCpltCallback().

  Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxCpltCallback     : Tx Transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CEC MspInit.
    (+) MspDeInitCallback  : CEC MspDeInit.

  For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
  @ref HAL_CEC_UnRegisterRxCpltCallback().

  By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
  or @ref HAL_CEC_Init() function.

  When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cec.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_comp.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
  ================================================================================
                   ##### COMP Peripheral features #####
  ================================================================================

  [..]
      The STM32H7xx device family integrates two analog comparators instances
      COMP1 and COMP2:
      (#) The COMP input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) Pairs of comparators instances can be combined in window mode
          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes:
          (++) COMP1 is internally connected to EXTI Line 20
          (++) COMP2 is internally connected to EXTI Line 21

  [..]
          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().

            ##### How to use this driver #####
  ================================================================================
  [..]
      This driver provides functions to configure and program the comparator instances of
      STM32H7xx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity
      (++) Select the power mode
      (++) Select the window mode
      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy.
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
          In STM32H7,COMP clock enable  __HAL_RCC_COMP12_CLK_ENABLE() must
          be implemented by user in "HAL_COMP_MspInit()".
      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
          with the interrupt through NVIC of the CPU.
      Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
      mode will stay disabled.

      (#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
          functions to manage comparator outputs(output level or events)

      (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
          to disable the interrupt too.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_COMP_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     [..]

     By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     example @ref HAL_COMP_TriggerCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
     or @ref HAL_COMP_Init() function.
     [..]

     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Table 1. COMP inputs and output for STM32H7xx devices +---------------------------------------------------------+ | | | COMP1 | COMP2 | |----------------|----------------|-----------|-----------| | | IO1 | PB0 | PE9 | | Input plus | IO2 | PB2 | PE11 | | | | | | |----------------|----------------|-----------------------| | | 1/4 VrefInt | Available | Available | | | 1/2 VrefInt | Available | Available | | | 3/4 VrefInt | Available | Available | | Input minus | VrefInt | Available | Available | | | DAC1 channel 1 | Available | Available | | | DAC1 channel 2 | Available | Available | | | IO1 | PB1 | PE10 | | | IO2 | PC4 | PE7 | | | | | | | | | | | | | | | | +---------------------------------------------------------+ | Output | | PC5 (1) | PE8 (1) | | | | PE12 (1) | PE13 (1) | | | | TIM (2) | TIM (2) | +---------------------------------------------------------+ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances.

Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_comp.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cortex.c File Reference

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Functions
stm32h7xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programming manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
       inside the stm32h7xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cortex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc.c File Reference

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stm32h7xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++) specify generating polynomial (peripheral default or non-default one)
             (++) specify initialization value (peripheral default or non-default one)
             (++) specify input data format
             (++) specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_crc.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc_ex.c File Reference

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Functions
stm32h7xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_crc_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp.c File Reference

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Defines | Functions
stm32h7xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U
#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__)
#define | HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in iterrupt mode.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static void | CRYP_TDES_IT (CRYP_HandleTypeDef *hcryp)
CRYP block input/output data handling under interruption with DES/TDES standard.
static HAL_StatusTypeDef | CRYP_WaitOnIFEMFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBUSYFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnOFNEFlag (const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
static HAL_StatusTypeDef | CRYP_TDES_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC Algorithm with DES/TDES standard.
HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used in CRYP IP as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP according to the specified parameters :
         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
         (##) The key size: 128, 192 or 256.
         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
         (##) The initialization vector (counter). It is not used in ECB mode.
         (##) The key buffer used for encryption/decryption.
         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
         (##) The HeaderSize The size of header buffer in word.
         (##) The B0 block is the first authentication block used only  in AES CCM mode.

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is configured and processes the buffer in input.
         At second call, no need to Initialize the CRYP, user have to get current configuration via
         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
         new parametres, finally user can  start encryption/decryption.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.

    [..]
      The cryptographic processor supports following standards:
      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
         (##)64-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
         (##) keys length supported :64-bit, 128-bit and 192-bit.
      (#) The advanced encryption standard (AES) supported  by CRYP1:
         (##)128-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
             (+++)  Counter mode (CTR)
             (+++)  Galois/counter mode (GCM/GMAC)
             (+++)  Counter with Cipher Block Chaining-Message(CCM)
         (##) keys length Supported :
             (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.

    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
      (#)  Algorithm supported :
         (##) Galois/counter mode (GCM)
         (##) Galois message authentication code (GMAC) :is exactly the same as
              GCM algorithm composed only by an header.
      (#)  Four phases are performed in GCM :
         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
      (#)  structure of message construction in GCM is defined as below  :
         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
          this part of the message is only authenticated, not encrypted.
         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
          GCM standard specifies that ciphertext has same bit length as the plaintext.
         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
          (on 64 bits)

    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
          Authentication Code (CCM) supported by both CRYP1 IP:
      (#)  Specific parameters for CCM  :

         (##) B0 block  : According to NIST Special Publication 800-38C,
            The first block B0 is formatted as follows, where l(m) is encoded in
            most-significant-byte first order(see below table 3)

              (+++)  Q: a bit string representation of the octet length of P (plaintext)
              (+++)  q The octet length of the binary representation of the octet length of the payload
              (+++)  A nonce (N), n The octet length of the where n+q=15.
              (+++)  Flags: most significant octet containing four flags for control information,
              (+++)  t The octet length of the MAC.
         (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
              the associated data length expressed in bytes (a) defined as below:
            (+++)  If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
            (+++)  If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
            (+++)  If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
         (##) CTRx block  : control blocks
            (+++) Generation of CTR1 from first block B0 information :
              equal to B0 with first 5 bits zeroed and most significant bits storing octet
              length of P also zeroed, then incremented by one ( see below Table 4)
            (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.

      (#)  Four phases are performed in CCM for CRYP1 IP:
         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.

  *** Callback registration ***
  =============================

  [..]
  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
  to register an interrupt callback.

  [..]
  Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.

  [..]
  By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
  or @ref HAL_CRYP_Init() function.

  [..]
  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Table 1. Initial Counter Block (ICB) +-------------------------------------------------------+ | Initialization vector (IV) | Counter | |----------------|----------------|-----------|---------| 127 95 63 31 0

Bit Number Register Contents ---------- --------------- ----------- 127 ...96 CRYP_IV1R[31:0] ICB[127:96] 95 ...64 CRYP_IV1L[31:0] B0[95:64] 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2

Table 2. GCM last block definition

+-------------------------------------------------------------------+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] | |-----------|--------------------|-----------|----------------------| | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | |-----------|--------------------|-----------|----------------------|

Table 3. B0 block Octet Number Contents ------------ --------- 0 Flags 1 ... 15-q Nonce N 16-q ... 15 Q

the Flags field is formatted as follows:

Bit Number Contents ---------- ---------------------- 7 Reserved (always zero) 6 Adata 5 ... 3 (t-2)/2 2 ... 0 [q-1]3

Table 4. CTRx block Bit Number Register Contents ---------- --------------- ----------- 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for bit 0 that is set to 1 95 ...64 CRYP_IV1L[31:0] B0[95:64] 63 ... 32 CRYP_IV0R[31:0] B0[63:32] 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0

Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cryp.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_cryp_ex.c File Reference

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
    Encryption/Decryption to get the authentication messages.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_cryp_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    STM32H7 devices integrate two 12-bit Digital Analog Converters

    The 2 converters (i.e. channel1 & channel2)
    can be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).
      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM1, TIM2, TIM4, TIM5, TIM6, TIM7, TIM8, TIM15, TIM23 and TIM24
          (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)

      (#) Low Power Timers TRGO: LPTIM1, LPTIM2 and LPTIM3
          (DAC_TRIGGER_LPTIM1_OUT, DAC_TRIGGER_LPTIM2_OUT)

      (#) High Resolution Timer TRGO: HRTIM1
          (DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2)

      (#) Software using DAC_TRIGGER_SOFTWARE
      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** DAC connect feature ***
      ===============================
      [..]
      Each DAC channel can be connected internally.
      To connect, use
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
      or
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

      *** DAC Sample and Hold feature ***
      ========================
      [..]
      For each converter, 2 modes are supported: normal mode and
      "sample and hold" mode (i.e. low power mode).
      In the sample and hold mode, the DAC core converts data, then holds the
      converted voltage on a capacitor. When not converting, the DAC cores and
      buffer are completely turned off between samples and the DAC output is
      tri-stated, therefore  reducing the overall power consumption. A new
      stabilization period is needed before each new conversion.

      The sample and hold allow setting internal or external voltage @
      low power consumption cost (output value can be at any given rate either
      by CPU or DMA).

      The Sample and hold block and registers uses either LSI & run in
      several power modes: run mode, sleep mode, low power run, low power sleep
      mode & stop1 mode.

      Low power stop1 mode allows only static conversion.

      To enable Sample and Hold mode
      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
      RCC_LSI_ON parameters.

      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
           DAC_HoldTime & DAC_RefreshTime;

       *** DAC calibration feature ***
       ===================================
      [..]
       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
       (++) Calibration aims at correcting some offset of output buffer.
       (++) The DAC uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_DACEx_SelfCalibrate.
       (++) HAL_DACEx_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates a structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave
         (#) Triangle wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VREF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests ***
       =====================
       [..]
       A DMA request can be generated when an external trigger (but not a software trigger)
       occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
       DMA requests are mapped as following:
      (#) DAC channel1: mapped on DMA_REQUEST_DAC1_CH1
      (#) DAC channel2: mapped on DMA_REQUEST_DAC1_CH2

     [..]
    (@) For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.

     *** Calibration mode IO operation ***
     ======================================
     [..]
       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

    Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

    Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      (+) All Callbacks
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
      and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
      or @ref HAL_DAC_Init function.

      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dac.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_dac_ex.c File Reference

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

Author:
MCD Application Team
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
     *** Dual mode IO operation ***
     ==============================
      (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
          for dual mode operation.
          If software trigger is selected, using HAL_DACEx_DualStart() will start
          the conversion of the value previously set by HAL_DACEx_DualSetValue().
      (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
          for dual mode operation.
      (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
          for dual mode operation using DMA to feed DAC converters.
          First issued trigger will start the conversion of the value previously
          set by HAL_DACEx_DualSetValue().
          The same callbacks that are used in single mode are called in dual mode to notify
          transfer completion (half complete or complete), errors or underrun.
      (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
          for dual mode operation using DMA to feed DAC converters.
      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
          Channel 1 and Channel 2.

     *** Signal generation operation ***
     ===================================
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.

      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
          at least one time after reset).
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dac_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dcmi.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_dcmi.c File Reference

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */

Functions

static void | DCMI_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
HAL_StatusTypeDef | HAL_DCMI_RegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
Register a User DCMI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DCMI_UnRegisterCallback (DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
Unregister a DCMI Callback DCMI callabck is redirected to the weak predefined callback.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
      The sequence below describes how to use this driver to capture image
      from a camera module connected to the DCMI Interface.
      This sequence does not take into account the configuration of the
      camera module, which should be made before to configure and enable
      the DCMI to capture images.

    (#) Program the required configuration through following parameters:
        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
        Synchronization Mode, code of the frame delimiter and data width
        using HAL_DCMI_Init() function.

    (#) Configure the selected DMA stream to transfer Data from DCMI DR
        register to the destination memory buffer.

    (#) Program the required configuration through following parameters:
        DCMI mode, destination memory Buffer address and the data length
        and enable capture using HAL_DCMI_Start_DMA() function.

    (#) Optionally, configure and Enable the CROP feature to select a rectangular
        window from the received image using HAL_DCMI_ConfigCrop()
        and HAL_DCMI_EnableCrop() functions

    (#) The capture can be stopped using HAL_DCMI_Stop() function.

    (#) To control DCMI state you can use the function HAL_DCMI_GetState().

     *** Callback registration ***
     =============================================

     The compilation flag USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_DCMI_RegisterCallback() to register an interrupt callback.

     Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
       (+) LineEventCallback    : callback for DCMI line event.
       (+) FrameEventCallback   : callback for DCMI Frame event.
       (+) VsyncEventCallback   : callback for DCMI Vsync event.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.

     Use function HAL_DCMI_UnRegisterCallback to reset a callback to the default weak function.
     HAL_DCMI_UnRegisterCallback takes as parameters the HAL peripheral handle and the Callback ID.
     This function allows to reset following callbacks:
       (+) LineEventCallback    : callback for DCMI line event.
       (+) FrameEventCallback   : callback for DCMI Frame event.
       (+) VsyncEventCallback   : callback for DCMI Vsync event.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.

     By default, after the HAL_DCMI_Init() and when the state is HAL_DCMI_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_DCMI_LineEventCallback(), HAL_DCMI_FrameEventCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_DCMI_Init()/ HAL_DCMI_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the HAL_DCMI_Init()/ HAL_DCMI_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

     Callbacks can be registered/unregistered in HAL_DCMI_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_DCMI_STATE_READY or HAL_DCMI_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
     using HAL_DCMI_RegisterCallback() before calling HAL_DCMI_DeInit() or HAL_DCMI_Init() function.

     When the compilation flag USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     *** DCMI HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DCMI HAL driver.

      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.

     [..]
       (@) You can refer to the DCMI HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dcmi.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm.c File Reference

  • File List
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Defines | Functions | Variables
stm32h7xx_hal_dfsdm.c File Reference

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_MSB_MASK 0xFFFF0000U
#define | DFSDM_LSB_MASK 0x0000FFFFU
#define | DFSDM_CKAB_TIMEOUT 5000U
#define | DFSDM1_CHANNEL_NUMBER 8U
#define | DFSDM2_CHANNEL_NUMBER 2U

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (const DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_Channel_RegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback)
Register a user DFSDM channel callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Channel_UnRegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM channel callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback)
Register a user DFSDM filter callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM filter callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_RegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback)
Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_DFSDM_Filter_UnRegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Unregister a user DFSDM filter analog watchdog callback.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Variables

static __IO uint32_t | v_dfsdm1ChannelCounter = 0
static
DFSDM_Channel_HandleTypeDef * 		a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}
static __IO uint32_t | v_dfsdm2ChannelCounter = 0
static
DFSDM_Channel_HandleTypeDef * 		a_dfsdm2ChannelHandle [DFSDM2_CHANNEL_NUMBER] = {NULL}

Detailed Description

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
    *** Channel initialization ***
    ==============================
    [..]
      (#) User has first to initialize channels (before filters initialization).
      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the output clock, input, serial interface, analog watchdog,
          offset and data right bit shift parameters for this channel using the
          HAL_DFSDM_ChannelInit() function.

    *** Channel clock absence detector ***
    ======================================
    [..]
      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
          HAL_DFSDM_ChannelCkabStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
          absence.
      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
          clock absence is detected.
      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
          HAL_DFSDM_ChannelCkabStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if clock absence detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel short circuit detector ***
    ======================================
    [..]
      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
          or HAL_DFSDM_ChannelScdStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
          circuit.
      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
          short circuit is detected.
      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
          or HAL_DFSDM_ChannelScdStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if short circuit detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel analog watchdog value ***
    =====================================
    [..]
      (#) Get analog watchdog filter value of a channel using
          HAL_DFSDM_ChannelGetAwdValue().

    *** Channel offset value ***
    =====================================
    [..]
      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().

    *** Filter initialization ***
    =============================
    [..]
      (#) After channel initialization, user has to init filters.
      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
            Please note that DFSDMz_FLT0 global interrupt could be already
            enabled if interrupt is used for channel.
        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
            with DFSDMz filter handle using __HAL_LINKDMA().
      (#) Configure the regular conversion, injected conversion and filter
          parameters for this filter using the HAL_DFSDM_FilterInit() function.

    *** Filter regular channel conversion ***
    =========================================
    [..]
      (#) Select regular channel and enable/disable continuous mode using
          HAL_DFSDM_FilterConfigRegChannel().
      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
          HAL_DFSDM_FilterRegularMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
          the end of regular conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
          at the end of regular conversion.
      (#) Get value of regular conversion and corresponding channel using
          HAL_DFSDM_FilterGetRegularValue().
      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().

    *** Filter injected channels conversion ***
    ===========================================
    [..]
      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
          HAL_DFSDM_FilterInjectedMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
          the end of injected conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
          at the end of injected conversion.
      (#) Get value of injected conversion and corresponding channel using
          HAL_DFSDM_FilterGetInjectedValue().
      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().

    *** Filter analog watchdog ***
    ==============================
    [..]
      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().

    *** Filter extreme detector ***
    ===============================
    [..]
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().

    *** Filter conversion time ***
    ==============================
    [..]
      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().

    *** Callback registration ***
    =============================
    [..]
    The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.
    Use functions HAL_DFSDM_Channel_RegisterCallback(),
    HAL_DFSDM_Filter_RegisterCallback() or
    HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.

    [..]
    Function HAL_DFSDM_Channel_RegisterCallback() allows to register
    following callbacks:
      (+) CkabCallback      : DFSDM channel clock absence detection callback.
      (+) ScdCallback       : DFSDM channel short circuit detection callback.
      (+) MspInitCallback   : DFSDM channel MSP init callback.
      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
    [..]
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Function HAL_DFSDM_Filter_RegisterCallback() allows to register
    following callbacks:
      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.
      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
      (+) ErrorCallback           : DFSDM filter error callback.
      (+) MspInitCallback         : DFSDM filter MSP init callback.
      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.
    [..]
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    For specific DFSDM filter analog watchdog callback use dedicated register callback:
    HAL_DFSDM_Filter_RegisterAwdCallback().

    [..]
    Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
    HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
    weak function.

    [..]
    HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) CkabCallback      : DFSDM channel clock absence detection callback.
      (+) ScdCallback       : DFSDM channel short circuit detection callback.
      (+) MspInitCallback   : DFSDM channel MSP init callback.
      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.

    [..]
    HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.
      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
      (+) ErrorCallback           : DFSDM filter error callback.
      (+) MspInitCallback         : DFSDM filter MSP init callback.
      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.

    [..]
    For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
    HAL_DFSDM_Filter_UnRegisterAwdCallback().

    [..]
    By default, after the call of init function and if the state is RESET
    all callbacks are reset to the corresponding legacy weak functions:
    examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak functions in the init and de-init only when these
    callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the init and de-init keep and use
    the user MspInit/MspDeInit callbacks (registered beforehand)

    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the init/de-init.
    In that case first register the MspInit/MspDeInit user callbacks using
    HAL_DFSDM_Channel_RegisterCallback() or
    HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.

    [..]
    When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dfsdm.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm_ex.c File Reference

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Functions
stm32h7xx_hal_dfsdm_ex.c File Reference

DFSDM Extended HAL module driver. This file provides firmware functions to manage the following functionality of the DFSDM Peripheral Controller: + Set and get pulses skipping on channel. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DFDSMEx_ChannelSetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
Set value of pulses skipping.
HAL_StatusTypeDef | HAL_DFDSMEx_ChannelGetPulsesSkipping (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
Get value of pulses skipping.

Detailed Description

DFSDM Extended HAL module driver. This file provides firmware functions to manage the following functionality of the DFSDM Peripheral Controller: + Set and get pulses skipping on channel.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dfsdm_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma.c File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Data Structures

struct | DMA_Base_Registers
struct | BDMA_Base_Registers

Defines

#define | HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
#define | BDMA_PERIPH_TO_MEMORY (0x00000000U)
#define | BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)
#define | BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)
#define | DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__)
#define | DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
#define | DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
#define | DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
#define | DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
#define | DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
#define | DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
static HAL_StatusTypeDef | DMA_CheckFifoParam (DMA_HandleTypeDef *hdma)
Check compatibility between FIFO threshold level and size of the memory burst.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Stream
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and DMA requests .

   (#) For a given Stream, program the required configuration through the following parameters:
       Transfer Direction, Source and Destination data formats,
       Circular, Normal or peripheral flow control mode, Stream Priority level,
       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of DMA handle structure).
    [..]
     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
         detection.

     (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
           Half-Word data size for the peripheral to access its data register and set Word data size
           for the Memory to gain in access time. Each two half words will be packed and written in
           a single access to a Word in the Memory).

     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
           and Destination. In this case the Peripheral Data Size will be applied to both Source
           and Destination.

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA HAL driver.

      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma2d.c File Reference

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Defines | Functions
stm32h7xx_hal_dma2d.c File Reference

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DMA2D_TIMEOUT_ABORT (1000U)
#define | DMA2D_TIMEOUT_SUSPEND (1000U)

Functions

static void | DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D transfer parameters.
HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_RegisterCallback (DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
Register a User DMA2D Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DMA2D_UnRegisterCallback (DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
Unregister a DMA2D Callback DMA2D Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad_IT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Abort (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Suspend (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Resume (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
__weak void | HAL_DMA2D_LineEventCallback (DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
__weak void | HAL_DMA2D_CLUTLoadingCpltCallback (DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_HandleTypeDef.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
HAL_StatusTypeDef | HAL_DMA2D_EnableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_DisableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_ConfigDeadTime (DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Program the required configuration through the following parameters:
          the transfer mode, the output color mode and the output offset using
          HAL_DMA2D_Init() function.

      (#) Program the required configuration through the following parameters:
          the input color mode, the input color, the input alpha value, the alpha mode,
          the red/blue swap mode, the inverted alpha mode and the input offset using
          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.

     *** Polling mode IO operation ***
     =================================
    [..]
       (#) Configure pdata parameter (explained hereafter), destination and data length
           and enable the transfer using HAL_DMA2D_Start().
       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
           user can specify the value of timeout according to his end application.

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (#) Configure pdata parameter, destination and data length and enable
           the transfer using HAL_DMA2D_Start_IT().
       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
           add his own function by customization of function pointer XferCpltCallback (member
           of DMA2D handle structure).
       (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
           XferErrorCallback.

         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
               color, in Memory-to-memory or Memory-to-Memory with pixel format
               conversion pdata is the source address.

         -@-   Configure the foreground source address, the background source address,
               the destination and data length then Enable the transfer using
               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
               in interrupt mode.

         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
               are used if the memory to memory with blending transfer mode is selected.

      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.

      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().

      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
          HAL_DMA2D_DisableDeadTime().

      (#) The transfer can be suspended, resumed and aborted using the following
          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().

      (#) The CLUT loading can be suspended, resumed and aborted using the following
          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
          HAL_DMA2D_CLUTLoading_Abort().

      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().

      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().

     *** DMA2D HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA2D HAL driver :

      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.

     *** Callback registration ***
     ===================================
     [..]
      (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
          allows the user to configure dynamically the driver callbacks.
          Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.

      (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
            (+) XferCpltCallback : callback for transfer complete.
            (+) XferErrorCallback : callback for transfer error.
            (+) LineEventCallback : callback for line event.
            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
            (+) MspInitCallback    : DMA2D MspInit.
            (+) MspDeInitCallback  : DMA2D MspDeInit.
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
          weak (surcharged) function.
          @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (+) XferCpltCallback : callback for transfer complete.
            (+) XferErrorCallback : callback for transfer error.
            (+) LineEventCallback : callback for line event.
            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
            (+) MspInitCallback    : DMA2D MspInit.
            (+) MspDeInitCallback  : DMA2D MspDeInit.

      (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
          examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
          Exception done for MspInit and MspDeInit callbacks that are respectively
          reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
          and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
          If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

          Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
          as weak (surcharged) functions. They must be defined by the user to be resorted to.

          Callbacks can be registered/unregistered in READY state only.
          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
          during the Init/DeInit.
          In that case first register the MspInit/MspDeInit user callbacks
          using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
          or @ref HAL_DMA2D_Init function.

          When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
          not defined, the callback registering feature is not available
          and weak (surcharged) callbacks are used.

     [..]
      (@) You can refer to the DMA2D HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma2d.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma_ex.c File Reference

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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:
   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.

   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)

     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
     -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dma_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dts.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_dts.c File Reference

DTS HAL module driver. This file provides firmware functions to manage the following functionalities of the DTS peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DTS_DELAY_STARTUP (1UL)
#define | TS_TIMEOUT_MS (5UL)

Functions

static void | DTS_ResetCallback (DTS_HandleTypeDef *hdts)
Reset interrupt callbacks to the legacy weak callbacks.
HAL_StatusTypeDef | HAL_DTS_Init (DTS_HandleTypeDef *hdts)
Initialize the DTS according to the specified parameters in the DTS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DTS_DeInit (DTS_HandleTypeDef *hdts)
DeInitialize the DTS peripheral.
__weak void | HAL_DTS_MspInit (DTS_HandleTypeDef *hdts)
Initialize the DTS MSP.
__weak void | HAL_DTS_MspDeInit (DTS_HandleTypeDef *hdts)
DeInitialize the DTS MSP.
HAL_StatusTypeDef | HAL_DTS_Start (DTS_HandleTypeDef *hdts)
Start the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_Stop (DTS_HandleTypeDef *hdts)
Stop the DTS Sensor.
HAL_StatusTypeDef | HAL_DTS_Start_IT (DTS_HandleTypeDef *hdts)
Enable the interrupt(s) and start the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_Stop_IT (DTS_HandleTypeDef *hdts)
Disable the interrupt(s) and stop the DTS sensor.
HAL_StatusTypeDef | HAL_DTS_GetTemperature (DTS_HandleTypeDef *hdts, int32_t *Temperature)
Get temperature from DTS.
void | HAL_DTS_IRQHandler (DTS_HandleTypeDef *hdts)
DTS sensor IRQ Handler.
__weak void | HAL_DTS_EndCallback (DTS_HandleTypeDef *hdts)
DTS Sensor End measure callback.
__weak void | HAL_DTS_LowCallback (DTS_HandleTypeDef *hdts)
DTS Sensor low threshold measure callback.
__weak void | HAL_DTS_HighCallback (DTS_HandleTypeDef *hdts)
DTS Sensor high threshold measure callback.
__weak void | HAL_DTS_AsyncEndCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous end measure callback.
__weak void | HAL_DTS_AsyncLowCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous low threshold measure callback.
__weak void | HAL_DTS_AsyncHighCallback (DTS_HandleTypeDef *hdts)
DTS Sensor asynchronous high threshold measure callback.
HAL_DTS_StateTypeDef | HAL_DTS_GetState (DTS_HandleTypeDef *hdts)
Return the DTS handle state.

Detailed Description

DTS HAL module driver. This file provides firmware functions to manage the following functionalities of the DTS peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
================================================================================
          ##### DTS Peripheral features #####
================================================================================

  [..]
      The STM32h7xx device family integrate one DTS sensor interface :

            ##### How to use this driver #####
================================================================================
  [..]
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_dts.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_exti.c File Reference

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Defines | Functions
stm32h7xx_hal_exti.c File Reference

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### EXTI Peripheral features #####
  ==============================================================================
  [..]
    (+) Each Exti line can be configured within this driver.

    (+) Exti line can be configured in 3 different modes
        (++) Interrupt (CORE1 or CORE2 in case of dual core line )
        (++) Event (CORE1 or CORE2 in case of dual core line )
        (++) a combination of the previous

    (+) Configurable Exti lines can be configured with 3 different triggers
        (++) Rising
        (++) Falling
        (++) Both of them

    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
        interrupt pending registers which allow to distinguish which transition
        occurs:
        (++) Rising edge pending interrupt
        (++) Falling

    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
        be selected throught multiplexer.

    (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
        It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
        Value can be one of the following:
        (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
              In this case corresponding bit of D2PMRx register is set to 0
                (+++) On a configurable Line : the D3 domain wakeup signal is
                      automatically cleared after after the Delay + Rising Edge detect
                (+++) On a direct Line : the D3 domain wakeup signal is
                      cleared after the direct event input signal is cleared

        (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
              In this case corresponding bit of D2PMRx register is set to 1
              and corresponding bits(2) of D3PCRxL/H is set to b00 :
                DMA ch6 event selected as D3 domain pendclear source

        (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
              In this case corresponding bit of D2PMRx register is set to 1
              and corresponding bits(2) of D3PCRxL/H is set to b01 :
                DMA ch7 event selected as D3 domain pendclear source

        (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
              In this case corresponding bit of D2PMRx register is set to 1
              and corresponding bits(2) of D3PCRxL/H is set to b10 :
                LPTIM4 out selected as D3 domain pendclear source

        (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
              In this case corresponding bit of D2PMRx register is set to 1
              and corresponding bits(2) of D3PCRxL/H is set to b11 :
                LPTIM5 out selected as D3 domain pendclear source

                     ##### How to use this driver #####
  ==============================================================================
  [..]

    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
        (++) Choose the interrupt line number by setting "Line" member from
             EXTI_ConfigTypeDef structure.
        (++) Configure the interrupt and/or event mode using "Mode" member from
             EXTI_ConfigTypeDef structure.
        (++) For configurable lines, configure rising and/or falling trigger
             "Trigger" member from EXTI_ConfigTypeDef structure.
        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
             member from GPIO_InitTypeDef structure.
        (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
             choose gpio D3 PendClearSource using PendClearSource
             member from EXTI_PendClear_Source structure.

    (#) Get current Exti configuration of a dedicated line using
        HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.
        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.

    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.

    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
        (++) Provide exiting handle as first parameter.
        (++) Provide which callback will be registered using one value from
             EXTI_CallbackIDTypeDef.
        (++) Provide callback function pointer.

    (#) Get interrupt pending bit using HAL_EXTI_GetPending().

    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().

    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_exti.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_fdcan.c File Reference

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stm32h7xx_hal_fdcan.c File Reference

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
#define | FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
#define | FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
#define | FDCAN_TT_DISTURBING_ERROR_MASK
#define | FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | FDCAN_MESSAGE_RAM_SIZE 0x2800U
#define | FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */

Functions

static HAL_StatusTypeDef | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
Register Clock Calibration FDCAN Callback To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Clock Calibration FDCAN Callback Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
Register TT Schedule Synchronization FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Schedule Synchronization FDCAN Callback TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
Register TT Time Mark FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTTimeMarkCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Time Mark FDCAN Callback TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
Register TT Stop Watch FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTStopWatchCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Stop Watch FDCAN Callback TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
Register TT Global Time FDCAN Callback To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTTGlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the TT Global Time FDCAN Callback TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Variables

static const uint8_t | DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Detailed Description

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.

      (#) If needed , configure the reception filters and optional features using
          the following configuration functions:
            (++) HAL_FDCAN_ConfigClockCalibration
            (++) HAL_FDCAN_ConfigFilter
            (++) HAL_FDCAN_ConfigGlobalFilter
            (++) HAL_FDCAN_ConfigExtendedIdMask
            (++) HAL_FDCAN_ConfigRxFifoOverwrite
            (++) HAL_FDCAN_ConfigFifoWatermark
            (++) HAL_FDCAN_ConfigRamWatchdog
            (++) HAL_FDCAN_ConfigTimestampCounter
            (++) HAL_FDCAN_EnableTimestampCounter
            (++) HAL_FDCAN_DisableTimestampCounter
            (++) HAL_FDCAN_ConfigTimeoutCounter
            (++) HAL_FDCAN_EnableTimeoutCounter
            (++) HAL_FDCAN_DisableTimeoutCounter
            (++) HAL_FDCAN_ConfigTxDelayCompensation
            (++) HAL_FDCAN_EnableTxDelayCompensation
            (++) HAL_FDCAN_DisableTxDelayCompensation
            (++) HAL_FDCAN_EnableISOMode
            (++) HAL_FDCAN_DisableISOMode
            (++) HAL_FDCAN_EnableEdgeFiltering
            (++) HAL_FDCAN_DisableEdgeFiltering
            (++) HAL_FDCAN_TT_ConfigOperation
            (++) HAL_FDCAN_TT_ConfigReferenceMessage
            (++) HAL_FDCAN_TT_ConfigTrigger

      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
          the node is active on the bus: it can send and receive messages.

      (#) The following Tx control functions can only be called when the FDCAN
          module is started:
            (++) HAL_FDCAN_AddMessageToTxFifoQ
            (++) HAL_FDCAN_EnableTxBufferRequest
            (++) HAL_FDCAN_AbortTxRequest

      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
          get Tx buffer location used to place the Tx request thanks to
          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
          It is then possible to abort later on the corresponding Tx Request using
          HAL_FDCAN_AbortTxRequest API.

      (#) When a message is received into the FDCAN message RAM, it can be
          retrieved using the HAL_FDCAN_GetRxMessage function.

      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
          it to initialization mode and re-enabling access to configuration
          registers through the configuration functions listed here above.

      (#) All other control functions can be called any time after initialization
          phase, no matter if the FDCAN module is started or stoped.

      *** Polling mode operation ***
      ==============================

    [..]
        (#) Reception and transmission states can be monitored via the following
            functions:
              (++) HAL_FDCAN_IsRxBufferMessageAvailable
              (++) HAL_FDCAN_IsTxBufferMessagePending
              (++) HAL_FDCAN_GetRxFifoFillLevel
              (++) HAL_FDCAN_GetTxFifoFreeLevel

      *** Interrupt mode operation ***
      ================================
      [..]
        (#) There are two interrupt lines: line 0 and 1.
            By default, all interrupts are assigned to line 0. Interrupt lines
            can be configured using HAL_FDCAN_ConfigInterruptLines function.

        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
            function. Then, the process can be controlled through one of the
            available user callbacks: HAL_FDCAN_xxxCallback.

  *** Callback registration ***
  =============================================

  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
  to register an interrupt callback.

  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().

  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.

  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().

  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
  all callbacks are set to the corresponding weak functions:
  examples @ref HAL_FDCAN_ErrorCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
  or @ref HAL_FDCAN_Init() function.

  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_fdcan.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash.c File Reference

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Defines | Functions | Variables
stm32h7xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option bytes loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.
HAL_StatusTypeDef | FLASH_CRC_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH CRC computation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Option bytes programming
      (+) Error code correction (ECC) : Data in flash are 266-bits word
          (10 bits added per flash word)

                        ##### How to use this driver #####
 ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32H7xx devices.

      (#) FLASH Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: 256-bit word only
           (++) There Two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions :
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_FLASH_GetError()

      (#) Option bytes management functions :
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
                In this case, a reset is generated
    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the FLASH interrupts
       (+) Monitor the FLASH flags status
     [..]
    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
        (HCLK) must be at least 1MHz.
    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
        a Flash memory operation.
    (@) The application can simultaneously request a read and a write operation through each AXI
        interface.
        As the Flash memory is divided into two independent banks, the embedded Flash
        memory interface can drive different operations at the same time on each bank. For
        example a read, write or erase operation can be executed on bank 1 while another read,
        write or erase operation is executed on bank 2.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_flash.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Functions

static void | FLASH_MassErase (uint32_t VoltageRange, uint32_t Banks)
Mass erase of FLASH memory.
static void | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_GetWRP (uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
Get the write protection of the given bank 1 or bank 2 sectors.
static void | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static uint32_t | FLASH_OB_GetRDP (void)
Get the read protection level.
static void | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
Get the Proprietary code readout protection configuration on a given Bank.
static void | FLASH_OB_BOR_LevelConfig (uint32_t Level)
Set the BOR Level.
static uint32_t | FLASH_OB_GetBOR (void)
Get the BOR Level.
static void | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_BootAddConfig (uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
Set Boot address.
static void | FLASH_OB_GetBootAdd (uint32_t *BootAddress0, uint32_t *BootAddress1)
Get Boot address.
static void | FLASH_OB_SecureAreaConfig (uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
Set secure area configuration.
static void | FLASH_OB_GetSecureArea (uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
Get secure area configuration.
static void | FLASH_CRC_AddSector (uint32_t Sector, uint32_t Bank)
Add a CRC sector to the list of sectors on which the CRC will be calculated.
static void | FLASH_CRC_SelectAddress (uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
Select CRC start and end memory addresses on which the CRC will be calculated.
static void | FLASH_OB_OTP_LockConfig (uint32_t OTP_Block)
Configure the OTP Block Lock.
static uint32_t | FLASH_OB_OTP_GetLock (void)
Get the OTP Block Lock.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_ComputeCRC (FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
Erase the specified FLASH memory sector.

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

Author:
MCD Application Team
 ==============================================================================
                   ##### Flash Extension features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
       devices contains the following additional features

       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank memory organization
       (+) PCROP protection for all banks
       (+) Global readout protection (RDP)
       (+) Write protection
       (+) Secure access only protection
       (+) Bank / register swapping
       (+) Cyclic Redundancy Check (CRC)

                        ##### How to use this driver #####
 ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32H7xx devices. It includes
      (#) FLASH Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Sector erase, bank erase and dual-bank mass erase
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
        (++) Set/Reset the write protection per bank
        (++) Set the Read protection Level
        (++) Set the BOR level
        (++) Program the user Option Bytes
        (++) PCROP protection configuration and control per bank
        (++) Secure area configuration and control per bank
        (++) Core Boot address configuration

      (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
          HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions

      (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
          (++) Enable CRC feature
          (++) Program the desired burst size
          (++) Define the user Flash Area on which the CRC has be computed
          (++) Perform the CRC computation
          (++) Disable CRC feature
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_flash_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gfxmmu.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_gfxmmu.c File Reference

This file provides firmware functions to manage the following functionalities of the Graphic MMU (GFXMMU) peripheral: + Initialization and De-initialization. + LUT configuration. + Force flush and/or invalidate of cache. + Modify physical buffer adresses. + Modify cache and pre-fetch parameters. + Error management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | GFXMMU_LUTXL_FVB_OFFSET 8U
#define | GFXMMU_LUTXL_LVB_OFFSET 16U
#define | GFXMMU_CR_ITS_MASK 0x1FU

Functions

HAL_StatusTypeDef | HAL_GFXMMU_Init (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU according to the specified parameters in the GFXMMU_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_GFXMMU_DeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU.
__weak void | HAL_GFXMMU_MspInit (GFXMMU_HandleTypeDef *hgfxmmu)
Initialize the GFXMMU MSP.
__weak void | HAL_GFXMMU_MspDeInit (GFXMMU_HandleTypeDef *hgfxmmu)
De-initialize the GFXMMU MSP.
HAL_StatusTypeDef | HAL_GFXMMU_RegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID, pGFXMMU_CallbackTypeDef pCallback)
Register a user GFXMMU callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_GFXMMU_UnRegisterCallback (GFXMMU_HandleTypeDef *hgfxmmu, HAL_GFXMMU_CallbackIDTypeDef CallbackID)
Unregister a user GFXMMU callback.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigLut (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address)
This function allows to copy LUT from flash to look up RAM.
HAL_StatusTypeDef | HAL_GFXMMU_DisableLutLines (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber)
This function allows to disable a range of LUT lines.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigLutLine (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
This function allows to configure one line of LUT.
HAL_StatusTypeDef | HAL_GFXMMU_ConfigForceCache (GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
This function allows to force flush and/or invalidate of cache.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyBuffers (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
This function allows to modify physical buffer addresses.
HAL_StatusTypeDef | HAL_GFXMMU_ModifyCachePrefetch (GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_CachePrefetchTypeDef *CachePrefetch)
This function allows to modify cache and pre-fetch parameters.
void | HAL_GFXMMU_IRQHandler (GFXMMU_HandleTypeDef *hgfxmmu)
This function handles the GFXMMU interrupts.
__weak void | HAL_GFXMMU_ErrorCallback (GFXMMU_HandleTypeDef *hgfxmmu)
Error callback.
HAL_GFXMMU_StateTypeDef | HAL_GFXMMU_GetState (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU handle state.
uint32_t | HAL_GFXMMU_GetError (GFXMMU_HandleTypeDef *hgfxmmu)
This function allows to get the current GFXMMU error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Graphic MMU (GFXMMU) peripheral: + Initialization and De-initialization. + LUT configuration. + Force flush and/or invalidate of cache. + Modify physical buffer adresses. + Modify cache and pre-fetch parameters. + Error management.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
        (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
        (++) If interrupts are used, enable and configure GFXMMU global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the number of blocks per line, default value, physical
          buffer addresses, cache and pre-fetch parameters and interrupts
          using the HAL_GFXMMU_Init() function.

    *** LUT configuration ***
    =========================
    [..]
      (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
          range of lines).
      (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
      (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.

    *** Force flush and/or invalidate of cache ***
    ==============================================
    [..]
      (#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.

    *** Modify physical buffer adresses ***
    =======================================
    [..]
      (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.

    *** Modify cache and pre-fetch parameters ***
    =============================================
    [..]
      (#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
          parameters.

    *** Error management ***
    ========================
    [..]
      (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
          an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
          Use HAL_GFXMMU_GetError() to get the error code.

    *** De-initialization ***
    =========================
    [..]
      (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
        (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
        (++) If interrupts has been used, disable GFXMMU global interrupt with
             HAL_NVIC_DisableIRQ().
      (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.

    *** Callback registration ***
    =============================

    [..]
    The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.
    Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.

    [..]
    Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
      (+) ErrorCallback      : GFXMMU error.
      (+) MspInitCallback    : GFXMMU MspInit.
      (+) MspDeInitCallback  : GFXMMU MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) ErrorCallback      : GFXMMU error.
      (+) MspInitCallback    : GFXMMU MspInit.
      (+) MspDeInitCallback  : GFXMMU MspDeInit.

    [..]
    By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
    examples HAL_GFXMMU_ErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
    and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
    or HAL_GFXMMU_Init function.

    [..]
    When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_gfxmmu.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE (0x00000003U)
#define | ANALOG_MODE (0x00000008U)
#define | EXTI_MODE (0x10000000U)
#define | GPIO_MODE_IT (0x00010000U)
#define | GPIO_MODE_EVT (0x00020000U)
#define | RISING_EDGE (0x00100000U)
#define | FALLING_EDGE (0x00200000U)
#define | GPIO_OUTPUT_TYPE (0x00000010U)
#define | GPIO_NUMBER (16U)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  The external interrupt/event controller consists of up to 23 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_gpio.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash.c File Reference

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Defines | Functions
stm32h7xx_hal_hash.c File Reference

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U)
#define | HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U)
#define | HASH_NUMBER_OF_CSR_REGISTERS 54U
#define | HASH_TIMEOUTVALUE 1000U
#define | HASH_DMA_SUSPENSION_WORDS_LIMIT 20U

Functions

static void | HASH_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA HASH Input Data transfer completion callback.
static void | HASH_DMAError (DMA_HandleTypeDef *hdma)
DMA HASH communication error callback.
static void | HASH_GetDigest (uint8_t *pMsgDigest, uint8_t Size)
Retrieve the message digest.
static HAL_StatusTypeDef | HASH_WaitOnFlagUntilTimeout (HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle HASH processing Timeout.
static HAL_StatusTypeDef | HASH_WriteData (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Feed the input buffer to the HASH IP.
static HAL_StatusTypeDef | HASH_IT (HASH_HandleTypeDef *hhash)
HASH processing in interruption mode.
static uint32_t | HASH_Write_Block_Data (HASH_HandleTypeDef *hhash)
Write a block of data in HASH IP in interruption mode.
static HAL_StatusTypeDef | HMAC_Processing (HASH_HandleTypeDef *hhash, uint32_t Timeout)
HMAC processing in polling mode.
HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.
HAL_StatusTypeDef | HAL_HASH_RegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
Register a User HASH Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_HASH_UnRegisterCallback (HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
Unregister a HASH Callback HASH Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.
uint32_t | HAL_HASH_GetError (HASH_HandleTypeDef *hhash)
Return the HASH handle error code.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption.

Author:
MCD Application Team
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
    The HASH HAL driver can be used as follows:

    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
            (+++) Enable the DMAx interface clock using
                   __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream to manage data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU.
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream: use
                 HAL_NVIC_SetPriority() and
                 HAL_NVIC_EnableIRQ()

    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
        (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.

    (#)Three processing schemes are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished,
             e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
        (##) Interrupt mode: processing APIs are not blocking functions
                i.e. they process the data under interrupt,
                e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA,
                e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
                for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
                is then required to retrieve the digest.

    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
       initialized and processes the buffer fed in input. When the input data have all been
       fed to the IP, the digest computation can start.

    (#)Multi-buffer processing is possible in polling and DMA mode.
        (##) In polling mode, only multi-buffer HASH processing is possible.
             API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
             User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
             well the computed digest.

        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
             From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
             macro then wrap-up the HASH processing in feeding the last input buffer thru the
             same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
             API HAL_HASH_xxx_Finish().
             (+++) HMAC processing (requires to resort to extended functions):
             after initialization, the key and the first input buffer are entered
             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
             starts step 2.
             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
             point, the HMAC processing is still carrying out step 2.
             Then, step 2 for the last input buffer and step 3 are carried out by a single call
             to HAL_HMACEx_xxx_Step2_3_DMA().

             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().

    (#)Context swapping.
        (##) Two APIs are available to suspend HASH or HMAC processing:
             (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
             (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.

        (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
            to save in memory the IP context. This context can be restored afterwards
            to resume the HASH processing thanks to HAL_HASH_ContextRestoring().

        (##) Once the HASH IP has been restored to the same configuration as that at suspension
             time, processing can be restarted with the same API call (same API, same handle,
             same parameters) as done before the suspension. Relevant parameters to restart at
             the proper location are internally saved in the HASH handle.

    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.

     *** Callback registration ***
     ===================================
     [..]
      (#) The compilation define  USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
          allows the user to configure dynamically the driver callbacks.
          Use function @ref HAL_HASH_RegisterCallback() to register a user callback.

      (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
            (+) InCpltCallback    : callback for input completion.
            (+) DgstCpltCallback  : callback for digest computation completion.
            (+) ErrorCallback     : callback for error.
            (+) MspInitCallback   : HASH MspInit.
            (+) MspDeInitCallback : HASH MspDeInit.
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
          weak (surcharged) function.
          @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (+) InCpltCallback    : callback for input completion.
            (+) DgstCpltCallback  : callback for digest computation completion.
            (+) ErrorCallback     : callback for error.
            (+) MspInitCallback   : HASH MspInit.
            (+) MspDeInitCallback : HASH MspDeInit.

      (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
          examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
          Exception done for MspInit and MspDeInit callbacks that are respectively
          reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
          and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
          If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

          Callbacks can be registered/unregistered in READY state only.
          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
          during the Init/DeInit.
          In that case first register the MspInit/MspDeInit user callbacks
          using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
          or @ref HAL_HASH_Init function.

          When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
          not defined, the callback registering feature is not available
          and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hash.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash_ex.c File Reference

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Functions
stm32h7xx_hal_hash_ex.c File Reference

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256.

Author:
MCD Application Team
 ===============================================================================
                     ##### HASH peripheral extended features  #####
 ===============================================================================
    [..]
    The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
    the same way as for SHA-1 or MD-5 algorithms.
    (#) Three modes are available.
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished,
             e.g. HAL_HASHEx_xxx_Start()
        (##) Interrupt mode: processing APIs are not blocking functions
                i.e. they process the data under interrupt,
                e.g. HAL_HASHEx_xxx_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA,
                e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
                HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.

   (#)Multi-buffer processing is possible in polling and DMA mode.
        (##) In polling mode, only multi-buffer HASH processing is possible.
             API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
             User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
             well the computed digest.

        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.

              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
             From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
             macro then wrap-up the HASH processing in feeding the last input buffer thru the
             same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
             API HAL_HASHEx_xxx_Finish().

             (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
             extended functions): after initialization, the key and the first input buffer are entered
             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
             starts step 2.
             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
             point, the HMAC processing is still carrying out step 2.
             Then, step 2 for the last input buffer and step 3 are carried out by a single call
             to HAL_HMACEx_xxx_Step2_3_DMA().

             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
             MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hash_ex.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hcd.c File Reference

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Functions
stm32h7xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.
HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
UnRegister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macros
             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hcd.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hsem.c File Reference

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Functions
stm32h7xx_hal_hsem.c File Reference

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255
      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
          (++) the semaphore ID from 0_ID to 31
          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255:
           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
         semaphore remains taken (locked)

      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
          This function takes as parameters :
           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
           (++) the Master ID:
           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
           Key or the MasterID doesn't match, semaphores remains taken (locked)

      (#)Semaphores Release all key functions:
         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
         (++)  HAL_HSEM_GetClearKey() to get release all Key
      (#)Semaphores notification functions :
         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
               semaphores (bitfield).

         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
                Used by the notification functions
     *** HSEM HAL driver macros list ***
     =============================================
     [..] Below the list of most used macros in HSEM HAL driver.

      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
      [..] Example of use :
      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_hsem.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c.c File Reference

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Defines | Functions
stm32h7xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx stream or channel depends on Instance

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode or DMA mode IO sequential operation ***
    ==========================================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases
      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
                              without stopping the communication and so generate a restart condition.
      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
                            interface.
                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          @ref HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          @ref HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          @ref HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          @ref HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
    [..]
     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
    [..]
     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
     or @ref HAL_I2C_Init() function.
    [..]
     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2c.c.

Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c_ex.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32H7xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2c_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | I2S_TIMEOUT 0xFFFFUL

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_16Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the transmission 16-bit in Interrupt context.
static void | I2S_Transmit_32Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the transmission 32-bit in Interrupt context.
static void | I2S_Receive_16Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the reception 16-bit in Interrupt context.
static void | I2S_Receive_32Bit_IT (I2S_HandleTypeDef *hi2s)
Manage the reception 32-bit in Interrupt context.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream/Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                  DMA Tx/Rx Stream/Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.

        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.

    (#) Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   ===================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros

   *** I2S HAL driver macros list ***
   ===================================
   [..]
       Callback registration:

      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.

          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
            (+) TxCpltCallback        : I2S Tx Completed callback
            (+) RxCpltCallback        : I2S Rx Completed callback
            (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (+) ErrorCallback         : I2S Error callback
            (+) MspInitCallback       : I2S Msp Init callback
            (+) MspDeInitCallback     : I2S Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (+) TxCpltCallback        : I2S Tx Completed callback
            (+) RxCpltCallback        : I2S Rx Completed callback
            (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (+) ErrorCallback         : I2S Error callback
            (+) MspInitCallback       : I2S Msp Init callback
            (+) MspDeInitCallback     : I2S Msp DeInit callback

       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
       or HAL_I2S_Init() function.

       When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_i2s.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU
#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
    Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.

    [..]
    By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
    and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
    or @ref HAL_IRDA_Init() function.

    [..]
    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_irda.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_iwdg.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48u

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
        __HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts counting down.
      (++) Enable write access to configuration registers:
          IWDG_PR, IWDG_RLR and IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) Wait for status flags to be reset.
      (++) Depending on window parameter:
        (+++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function with exact time base.
        (+++) Else modify Window register. This will automatically reload
             watchdog counter.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_iwdg.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_jpeg.c File Reference

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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions | Variables
stm32h7xx_hal_jpeg.c File Reference

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Data Structures

struct | JPEG_ACHuffTableTypeDef
struct | JPEG_DCHuffTableTypeDef
struct | JPEG_AC_HuffCodeTableTypeDef
struct | JPEG_DC_HuffCodeTableTypeDef

Defines

#define | JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
#define | JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/
#define | JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/
#define | JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
#define | JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/
#define | JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
#define | JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/
#define | JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/
#define | JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */
#define | JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */
#define | JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */
#define | JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */
#define | JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */
#define | JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */
#define | JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */
#define | JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */
#define | JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */
#define | JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */
#define | JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */
#define | JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */

Functions

static HAL_StatusTypeDef | JPEG_Bits_To_SizeCodes (uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
Generates Huffman sizes/Codes Table from Bits/vals Table.
static HAL_StatusTypeDef | JPEG_DCHuff_BitsVals_To_SizeCodes (JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_ACHuff_BitsVals_To_SizeCodes (JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_Set_HuffDC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, const __IO uint32_t *DCTableAddress)
Set the JPEG register with an DC huffman table at the given DC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffAC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, const __IO uint32_t *ACTableAddress)
Set the JPEG register with an AC huffman table at the given AC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffEnc_Mem (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG encoder register huffman tables to used during the encdoing operation.
static void | JPEG_Set_Huff_DHTMem (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)
static uint32_t | JPEG_Set_Quantization_Mem (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
Configure the JPEG registers with a given quantization table.
static void | JPEG_SetColorYCBCR (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for YCbCr color space.
static void | JPEG_SetColorGrayScale (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for GrayScale color space.
static void | JPEG_SetColorCMYK (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for CMYK color space.
static void | JPEG_Init_Process (JPEG_HandleTypeDef *hjpeg)
Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.
static uint32_t | JPEG_Process (JPEG_HandleTypeDef *hjpeg)
JPEG encoding/decoding process in case of Polling or Interrupt.
static void | JPEG_ReadInputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
Read some input Data from the input buffer.
static void | JPEG_StoreOutputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
Store some output data from the JPEG peripheral to the output buffer.
static uint32_t | JPEG_GetQuality (JPEG_HandleTypeDef *hjpeg)
Calculate the decoded image quality (from 1 to 100)
static HAL_StatusTypeDef | JPEG_DMA_StartProcess (JPEG_HandleTypeDef *hjpeg)
Start the JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_ContinueProcess (JPEG_HandleTypeDef *hjpeg)
Continue the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_EndProcess (JPEG_HandleTypeDef *hjpeg)
Finalize the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_PollResidualData (JPEG_HandleTypeDef *hjpeg)
Poll residual output data when DMA process (encoding/decoding)
static void | JPEG_MDMAOutCpltCallback (MDMA_HandleTypeDef *hmdma)
MDMA output transfer complete callback.
static void | JPEG_MDMAInCpltCallback (MDMA_HandleTypeDef *hmdma)
MDMA input transfer complete callback.
static void | JPEG_MDMAErrorCallback (MDMA_HandleTypeDef *hmdma)
MDMA Transfer error callback.
static void | JPEG_MDMAOutAbortCallback (MDMA_HandleTypeDef *hmdma)
MDMA output Abort callback.
HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.
HAL_StatusTypeDef | HAL_JPEG_RegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, pJPEG_CallbackTypeDef pCallback)
Register a User JPEG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterCallback (JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
Unregister a JPEG Callback JPEG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_InfoReadyCallbackTypeDef pCallback)
Register Info Ready JPEG Callback To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterInfoReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Info Ready JPEG Callback Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
Register Get Data JPEG Callback To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterGetDataCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Get Data JPEG Callback Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_RegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg, pJPEG_DataReadyCallbackTypeDef pCallback)
Register Data Ready JPEG Callback To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_UnRegisterDataReadyCallback (JPEG_HandleTypeDef *hjpeg)
UnRegister the Data Ready JPEG Callback Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback.
HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.
HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.
__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.
void | HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.
HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Variables

static const
JPEG_DCHuffTableTypeDef 		JPEG_DCLUM_HuffTable
static const
JPEG_DCHuffTableTypeDef 		JPEG_DCCHROM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACLUM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACCHROM_HuffTable
static const uint8_t | JPEG_ZIGZAG_ORDER [JPEG_QUANT_TABLE_SIZE]

Detailed Description

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
         Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.

     (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
         the encoding parameters (mandatory before calling the encoding function).
         the application can change the encoding parameter ImageQuality from
         1 to 100 to obtain a more or less quality (visual quality vs the original row image),
         and inversely more or less jpg file size.

     (#) Note that for decoding operation the JPEG peripheral output data are organized in
         YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
         ISO/IEC 10918-1 standard.
         It is up to the application to transform these YCbCr blocks to RGB data that can be display.

         Respectively, for Encoding operation the JPEG peripheral input should be organized
         in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
         MCU blocks transformation before feeding the JPEG peripheral with data.

     (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
         a JPEG encoding/decoding operation in polling method (blocking).

     (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
         a JPEG encoding/decoding operation with Interrupt method (not blocking).

     (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
         a JPEG encoding/decoding operation with DMA method (not blocking).

     (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
         is a JPEG decoding to provide the application with JPEG image  parameters.
         This callback is asserted when the JPEG peripheral successfully parse the
         JPEG header.

     (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
         operations to inform the application that the input buffer has been
         consumed by the peripheral and to ask for a new data chunk if the operation
         (encoding/decoding) has not been complete yet.

        (++) This CallBack should be implemented in the application side. It should
             call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
             or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
             to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
             application to provide a new input data chunk.
             Once the application succeed getting new data and if the input has been paused,
             the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
             input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
             If the application has ended feeding the HAL JPEG with input data (no more input data), the application
             Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
             with the parameter InDataLength set to zero.

         (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
              to the application to provide the input data (for encoding or decoding) by chunks.
              If the new input data chunk is not available (because data should be read from an input file
              for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
              Once the new input data chunk is available ( read from a file for example), the application
              can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
              then resume the JPEG HAL input by calling function HAL_JPEG_Resume.

         (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
              any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.
              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
              (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
              Transferring the previous chunk buffer to the JPEG peripheral.

     (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
         has filled the given output buffer with the given size.

         (++) This CallBack should be implemented in the application side. It should
              call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
              with the new output buffer location and size to be used  to store next data chunk.
              if the application is not ready to provide the output chunk location then it can
              call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT
              to inform the JPEG HAL driver that it shall pause output data. Once the application
              is ready to receive the new data chunk (output buffer location free or available) it should call
              the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
              with the new output chunk buffer location and size, then call HAL_JPEG_Resume
              to inform the HAL that it shall resume outputting data in the given output buffer.

         (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
              the application to receive data from the JPEG peripheral by chunks. when a chunk
              is received, the application can pause the HAL JPEG output data to be able to process
              these received data (YCbCr to RGB conversion in case of decoding or data storage in case
              of encoding).

         (++) The application can call  functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
              any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
              (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
              Transferring the previous chunk buffer from the JPEG peripheral to the application.

     (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
         ended the current JPEG encoding operation, and all output data has been transmitted
         to the application.

     (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
         ended the current JPEG decoding operation. and all output data has been transmitted
         to the application.

     (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
         the current operation. the application can call the function HAL_JPEG_GetError()
         to retrieve the error codes.

     (#) By default the HAL JPEG driver uses the default quantization tables
         as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
         User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
         Note that for decoding the quantization tables are automatically extracted from
         the JPEG header.

      (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()

     *** JPEG HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in JPEG HAL driver.

      (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
      (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.
      (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.
      (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.
      (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.
      (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.
      (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.
      (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback()
  to register an interrupt callback.

  Function HAL_JPEG_RegisterCallback() allows to register following callbacks:
    (+) EncodeCpltCallback : callback for end of encoding operation.
    (+) DecodeCpltCallback : callback for end of decoding operation.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : JPEG MspInit.
    (+) MspDeInitCallback  : JPEG MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
  register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(),
  HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback().

  Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) EncodeCpltCallback : callback for end of encoding operation.
    (+) DecodeCpltCallback : callback for end of decoding operation.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : JPEG MspInit.
    (+) MspDeInitCallback  : JPEG MspDeInit.

  For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
  unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(),
  HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback().

  By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit()
  or HAL_JPEG_Init() function.

  When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_jpeg.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_lptim.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT 1000UL /* Timeout is 1s */

Functions

static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.
HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1 or LPTIM2.
         (++) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
             (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possible.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().

    *** Callback registration ***
  =============================================
  [..]
  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  [..]
  Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
  @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.
  [..]
  Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
  default weak function.
  @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  [..]
  These functions allow to register/unregister following callbacks:

    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
    (+) CompareMatchCallback    : Compare match Callback.
    (+) AutoReloadMatchCallback : Auto-reload match Callback.
    (+) TriggerCallback         : External trigger event detection Callback.
    (+) CompareWriteCallback    : Compare register write complete Callback.
    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
    (+) DirectionUpCallback     : Up-counting direction change Callback.
    (+) DirectionDownCallback   : Down-counting direction change Callback.

  [..]
  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
  all interrupt callbacks are set to the corresponding weak functions:
  examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init/DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.

  [..]
  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_lptim.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc.c File Reference

  • File List
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Functions
stm32h7xx_hal_ltdc.c File Reference

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | LTDC_SetConfig (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC peripheral.
HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
HAL_StatusTypeDef | HAL_LTDC_RegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
Register a User LTDC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LTDC_UnRegisterCallback (LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
Unregister an LTDC Callback LTDC callabck is redirected to the weak predefined callback.
void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
__weak void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
__weak void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
__weak void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.
HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
     [..]
     The LTDC HAL driver can be used as follows:

     (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef  hltdc;

     (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
         (##) Enable the LTDC interface clock
         (##) NVIC configuration if you need to use interrupt process
             (+++) Configure the LTDC interrupt priority
             (+++) Enable the NVIC LTDC IRQ Channel

     (#) Initialize the required configuration through the following parameters:
         the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
         Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function

     *** Configuration ***
     =========================
     [..]
     (#) Program the required configuration through the following parameters:
         the pixel format, the blending factors, input alpha value, the window size
         and the image size using HAL_LTDC_ConfigLayer() function for foreground
         or/and background layer.

     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
         HAL_LTDC_EnableCLUT functions.

     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().

     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
         and HAL_LTDC_EnableColorKeying functions.

     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
         function

     (#) If needed, reconfigure and change the pixel format value, the alpha value
         value, the window size, the window position and the layer start address
         for foreground or/and background layer using respectively the following
         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
         HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().

     (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
         then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().

         After calling the _NoReload functions to set different color/format/layer settings,
         the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
         an immediate reload is required.
         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
         the reload should be done in the next vertical blanking period,
         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.

     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()

     *** LTDC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in LTDC HAL driver.

      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
      (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
      (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
      (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.

     [..]
       (@) You can refer to the LTDC HAL driver header file for more useful macros

     *** Callback registration ***
     =============================================
     [..]
     The compilation define  USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use function HAL_LTDC_RegisterCallback() to register a callback.

    [..]
    Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
      (+) LineEventCallback   : LTDC Line Event Callback.
      (+) ReloadEventCallback : LTDC Reload Event Callback.
      (+) ErrorCallback       : LTDC Error Callback
      (+) MspInitCallback     : LTDC MspInit.
      (+) MspDeInitCallback   : LTDC MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
    and the callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) LineEventCallback   : LTDC Line Event Callback
      (+) ReloadEventCallback : LTDC Reload Event Callback
      (+) ErrorCallback       : LTDC Error Callback
      (+) MspInitCallback     : LTDC MspInit
      (+) MspDeInitCallback   : LTDC MspDeInit.

    [..]
    By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
    all callbacks are set to the corresponding weak functions:
    examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
    Exception done for MspInit and MspDeInit functions that are
    reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
    only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
    thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
    or HAL_LTDC_Init() function.

    [..]
    When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available and all callbacks
    are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ltdc.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdios.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_mdios.c File Reference

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define | MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define | MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U)
#define | MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U)

Functions

static void | MDIOS_InitCallbacksToDefault (MDIOS_HandleTypeDef *hmdios)
HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.
HAL_StatusTypeDef | HAL_MDIOS_RegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
Register a User MDIOS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_MDIOS_UnRegisterCallback (MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
Unregister an MDIOS Callback MDIOS callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.
uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error code.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The MDIOS HAL driver can be used as follow:

    (#) Declare a MDIOS_HandleTypeDef handle structure.

    (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
        (##) Enable the MDIOS interface clock.
        (##) MDIOS pins configuration:
            (+++) Enable clocks for the MDIOS GPIOs.
            (+++) Configure the MDIOS pins as alternate function.
        (##) NVIC configuration if you need to use interrupt process:
            (+++) Configure the MDIOS interrupt priority.
            (+++) Enable the NVIC MDIOS IRQ handle.

    (#) Program the Port Address and the Preamble Check in the Init structure.

    (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.

    (#) Perform direct slave read/write operations using the following APIs:
        (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
        (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()

    (#) Get the Master read/write operations flags using the following APIs:
        (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
        (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()

    (#) Clear the read/write flags using the following APIs:
        (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
        (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()

    (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
        the MDIOS will generate an interrupt in the following cases:
        (##) a DINn register written by the Master
        (##) a DOUTn register read by the Master
        (##) an error occur

        (@) A callback is executed for each genereted interrupt, so the driver provide the following
            HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
        (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
            and execute the previous callbacks

    (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
        (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
            (GPIO, Clocks, NVIC configuration ...)

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback.

  Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks:
    (+) WriteCpltCallback  : Write Complete Callback.
    (+) ReadCpltCallback   : Read Complete Callback.
    (+) ErrorCallback      : Error Callback.
    (+) WakeUpCallback     : Wake UP Callback
    (+) MspInitCallback    : MspInit Callback.
    (+) MspDeInitCallback  : MspDeInit Callback.

  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) WriteCpltCallback  : Write Complete Callback.
    (+) ReadCpltCallback   : Read Complete Callback.
    (+) ErrorCallback      : Error Callback.
    (+) WakeUpCallback     : Wake UP Callback
    (+) MspInitCallback    : MspInit Callback.
    (+) MspDeInitCallback  : MspDeInit Callback.

  By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET
  all callbacks are set to the corresponding weak functions:
  examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit
  or HAL_MDIOS_Init function.

  When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mdios.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdma.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_mdma.c File Reference

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */
#define | HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */

Functions

static void | MDMA_SetConfig (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Sets the MDMA Transfer parameter.
static void | MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA handle according to the specified parameters in the MDMA_InitTypeDef.
HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.
HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.
HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the MDMA Channel
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and MDMA requests.

   (#)
       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
       transfer request , channel priority, data endianness, Source increment, destination increment ,
       source data size, destination data size, data alignment, source Burst, destination Burst ,
       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
       or full transfer) source and destination block address offset, mask address and data.

       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
       last node of the list to the first one in order to make the list circular.
       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init

      -@-   The initial transfer itself (node 0 corresponding to the Init).
            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
            the connection between last node and first one.

       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
       the linked list remains circular and node 2 becomes the first one.
       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).

    [..]
       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
           transfer upon a request :
             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
               with BufferTransferLength defined within the HAL_MDMA_Init.
             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
               or within the current linked list node parameters.
             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
               or within the current linked list node parameters.
             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred.
          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
             In this case a fixed Timeout can be configured by User depending from his application.
          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
              when the abort ends or timeout (should not be called from an interrupt service routine).

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the MDMA interrupt is configured.
          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of MDMA handle structure).

          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
              (could be called from an interrupt service routine).

          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
              from the following list :
              (++) XferCpltCallback            : transfer complete callback.
              (++) XferBufferCpltCallback      : buffer transfer complete callback.
              (++) XferBlockCpltCallback       : block transfer complete callback.
              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
              (++) XferErrorCallback           : transfer error callback.
              (++) XferAbortCallback           : transfer abort complete callback.

    [..]
         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
              (++) This function returns an error if used while the Transfer has ended or not started.
              (++) If used while the current request has not been served yet (current request transfer on going)
                this function returns an error and the new request is ignored.

              Generally this function should be used in conjunctions with the MDMA callbacks:
              (++) example 1:
                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
                 (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
                   request using HAL_MDMA_GenerateSWRequest.

              (++) example 2:
                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
                 (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.

    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.

     *** MDMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in MDMA HAL driver.

      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.

     [..]
      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.

    [..]
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mdma.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc.c File Reference

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Functions
stm32h7xx_hal_mmc.c File Reference

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the mmc card.
static uint32_t | MMC_PowerON (MMC_HandleTypeDef *hmmc)
Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.
static uint32_t | MMC_SendStatus (MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
Returns the current card's status.
static void | MMC_PowerOFF (MMC_HandleTypeDef *hmmc)
Turns the SDMMC output signals off.
static void | MMC_Write_IT (MMC_HandleTypeDef *hmmc)
Wrap up writing in non-blocking mode.
static void | MMC_Read_IT (MMC_HandleTypeDef *hmmc)
Wrap up reading in non-blocking mode.
static uint32_t | MMC_HighSpeed (MMC_HandleTypeDef *hmmc, FunctionalState state)
Switches the MMC card to high speed mode.
static uint32_t | MMC_DDR_Mode (MMC_HandleTypeDef *hmmc, FunctionalState state)
Switches the MMC card to Double Data Rate (DDR) mode.
HAL_StatusTypeDef | MMC_ReadExtCSD (MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
Reads extended CSD register to get the sectors number of the device.
HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.
HAL_StatusTypeDef | HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
Register a User MMC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_MMC_UnRegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
Unregister a User MMC Callback MMC Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_MMC_ConfigSpeedBusOperation (MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_MMC_CardStateTypeDef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).
__weak void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
    the user in HAL_MMC_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with MMC and eMMC cards devices.
    It is used as follows:

    (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
        (##) SDMMC pins configuration for MMC card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
             and HAL_MMC_WriteBlocks_IT() APIs).
            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
                  and __HAL_MMC_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
                  and __HAL_MMC_CLEAR_IT()
        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.

    (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization

  *** MMC Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
    SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Initialize the SDMMC peripheral interface with defaullt configuration.
        The initialization process is done at 400KHz. You can change or adapt
        this frequency by adjusting the "ClockDiv" field.
        The MMC Card frequency (SDMMC_CK) is computed as follows:

           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)

        In initialization mode and according to the MMC Card standard,
        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

        This phase of initialization is done through SDMMC_Init() and
        SDMMC_PowerState_ON() SDMMC low level APIs.

    (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
        This phase allows the card initialization and identification
        and check the MMC Card type (Standard Capacity or High Capacity)
        The initialization flow is compatible with MMC standard.

        This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
        of plug-off plug-in.

    (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
        frequency by adjusting the "ClockDiv" field.
        In transfer mode and according to the MMC Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.

    (#) Select the corresponding MMC Card according to the address read with the step 2.

    (#) Configure the MMC Card in wide bus mode: 4-bits data.

  *** MMC Card Read operation ***
  ==============================
  [..]
    (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.

    (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.
        You could also check the DMA transfer process through the MMC Rx interrupt event.

    (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.
        You could also check the IT transfer process through the MMC Rx interrupt event.

  *** MMC Card Write operation ***
  ===============================
  [..]
    (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.

    (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.
        You could also check the DMA transfer process through the MMC Tx interrupt event.

    (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.
        You could also check the IT transfer process through the MMC Tx interrupt event.

  *** MMC card information ***
  ===========================
  [..]
    (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
        It returns useful information about the MMC card such as block size, card type,
        block number ...

  *** MMC card CSD register ***
  ============================
  [..]
    (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
        Some of the CSD parameters are useful for card initialization and identification.

  *** MMC card CID register ***
  ============================
  [..]
    (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
        Some of the CID parameters are useful for card initialization and identification.

  *** MMC HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in MMC HAL driver.

    (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
    (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
    (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
    (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags

  [..]
    (@) You can refer to the MMC HAL driver header file for more useful macros

  *** Callback registration ***
  =============================================
  [..]
    The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
    it allows to register following callbacks:
      (+) TxCpltCallback : callback when a transmission transfer is completed.
      (+) RxCpltCallback : callback when a reception transfer is completed.
      (+) ErrorCallback : callback when error occurs.
      (+) AbortCpltCallback : callback when abort is completed.
      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
      (+) MspInitCallback    : MMC MspInit.
      (+) MspDeInitCallback  : MMC MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function. It allows to reset following callbacks:
      (+) TxCpltCallback : callback when a transmission transfer is completed.
      (+) RxCpltCallback : callback when a reception transfer is completed.
      (+) ErrorCallback : callback when error occurs.
      (+) AbortCpltCallback : callback when abort is completed.
      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
      (+) MspInitCallback    : MMC MspInit.
      (+) MspDeInitCallback  : MMC MspDeInit.
    This function) takes as parameters the HAL peripheral handle and the Callback ID.

    By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
    and @ref  HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
    or @ref HAL_MMC_Init function.

    When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mmc.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc_ex.c File Reference

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stm32h7xx_hal_mmc_ex.c File Reference

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.

Detailed Description

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   The MMC Extension HAL driver can be used as follows:
   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.

   (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_mmc_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nand.c File Reference

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stm32h7xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
Register a User NAND Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
Unregister a User NAND Callback NAND Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : NAND MspInit.
        (+) MspDeInitCallback  : NAND MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) MspInitCallback    : NAND MspInit.
        (+) MspDeInitCallback  : NAND MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
      and @ref  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
      or @ref HAL_NAND_Init function.

      When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_nand.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nor.c File Reference

  • File List
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Defines | Functions | Variables
stm32h7xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
Register a User NOR Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
Unregister a User NOR Callback NOR Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Variables

static uint32_t | uwNORMemoryDataWidth = NOR_MEMORY_8B

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : NOR MspInit.
        (+) MspDeInitCallback  : NOR MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) MspInitCallback    : NOR MspInit.
        (+) MspDeInitCallback  : NOR MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
      and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
      or @ref HAL_NOR_Init function.

      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_nor.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_opamp.c File Reference

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | OPAMP_CSR_RESET_VALUE 0x00000000U
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
================================================================================
          ##### OPAMP Peripheral Features #####
================================================================================

  [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2

       (#) The OPAMP(s) provides several exclusive running modes.
       (++) Standalone mode
       (++) Programmable Gain Amplifier (PGA) modes
       (++) Follower mode

       (#) Each OPAMP(s) can be configured in normal and high speed mode.

       (#) The OPAMP(s) provide(s) calibration capabilities.
       (++) Calibration aims at correcting some offset for running mode.
       (++) The OPAMP uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
       (++) HAL_OPAMP_SelfCalibrate:
       (+++) Runs automatically the calibration in 2 steps.
            (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
             appropriate and enough in most cases).
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates the init structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)
       (+++) HAL_OPAMPEx_SelfCalibrateAll
            runs calibration of all OPAMPs in parallel to save search time.

       (#) Running mode: Standalone mode
       (++) Gain is set externally (gain depends on external loads).
       (++) Follower mode also possible externally by connecting the inverting input to
           the output.

       (#) Running mode: Follower mode
       (++) No Inverting Input is connected.

       (#) Running mode: Programmable Gain Amplifier (PGA) mode
           (Resistor feedback output)
       (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
           output.
       (#) OPAMP gain can be selected as :

      (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
      (+++) VREF- referenced.
      (+++) Filtering on VINM0, VREF- referenced.
      (+++) VINM0 node for bias voltage and VINP0 for input signal.
      (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.

      (##) Gain of x-1, x-3, x-7 or x-15 for inverting mode with:
      (+++) VINM0 node for input signal and VINP0 for bias.
      (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.

       (#) The OPAMPs inverting input can be selected according to the Reference Manual
           "OPAMP functional description" chapter.

       (#) The OPAMPs non inverting input can be selected according to the Reference Manual
           "OPAMP functional description" chapter.

            ##### How to use this driver #####
================================================================================
  [..]

    *** High speed / normal power mode ***
    ============================================
    [..]  To run in high speed mode:

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select OPAMP_POWERMODE_HIGHSPEED
      (++) Otherwise select OPAMP_POWERMODE_NORMAL

    *** Calibration ***
    ============================================
    [..]  To run the OPAMP calibration self calibration:

      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
           Store the calibration results.

    *** Running mode ***
    ============================================

    [..]  To use the OPAMP, perform the following steps:

      (#) Fill in the HAL_OPAMP_MspInit() to
      (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
      (++) Configure the OPAMP input AND output in analog mode using
           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.

      (#) Registrate Callbacks
      (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
           allows the user to configure dynamically the driver callbacks.

      (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
           it allows to register following callbacks:
      (+++) MspInitCallback         : OPAMP MspInit.
      (+++) MspDeInitCallback       : OPAMP MspDeInit.
           This function takes as parameters the HAL peripheral handle, the Callback ID
           and a pointer to the user callback function.

      (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
           weak (surcharged) function. It allows to reset following callbacks:
      (+++) MspInitCallback         : OPAMP MspInit.
      (+++) MspDeInitCallback       : OPAMP MspDeInit.
      (+++) All Callbacks
      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select the mode
      (++) Select the inverting input
      (++) Select the non-inverting input
      (++) If PGA mode is enabled, Select if inverting input is connected.
      (++) Select either factory or user defined trimming mode.
      (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
          (typically values set by HAL_OPAMP_SelfCalibrate function).

      (#) Enable the OPAMP using HAL_OPAMP_Start() function.

      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.

      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
          Caution: On STM32H7, HAL OPAMP lock is software lock only (not
          hardware lock as on some other STM32 devices)

      (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.

    *** Running mode: change of configuration while OPAMP ON  ***
    ============================================
    [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
      (#) If needed, fill in the HAL_OPAMP_MspInit()
      (++) This is the case for instance if you wish to use new OPAMP I/O

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) As in configure case, select first the parameters you wish to modify.

      (#) Change from high speed mode to normal power mode (& vice versa) requires
          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
          alone.

Table 1. OPAMPs inverting/non-inverting inputs for the STM32H7 devices:

+------------------------------------------------------------------------| | | | OPAMP1 | OPAMP2 | |-----------------|---------|----------------------|---------------------| | Inverting Input | VM_SEL | VINM0-> PC5 | VINM0-> PE8 | | | | VINM1-> PA7 | VINM1-> PG1 | | | | Internal: | Internal: | | | | ADC1_IN9 | OPAMP2_OUT | | | | ADC2_IN9 | PGA mode | | | | OPAMP1_OUT | | | | | PGA mode | | |-----------------|---------|----------------------|---------------------| | Non Inverting | VP_SEL | | | | | | VP0 -> PB0 (GPIO) | VP0 -> PE9 (GPIO) | | | | Internal: | Internal: | | Input | | DAC1_CH1_int | DAC1_CH2_int | | | | ADC1_IN8 | DAC2_CH1_int | | | | ADC2_IN8 | COMP2_INP | | | | COMP1_INP | | +------------------------------------------------------------------------|

[..] Table 2. OPAMPs outputs for the STM32H7 devices:

+------------------------------------------------------------------------- | | | OPAMP1 | OPAMP2 | |-----------------|--------|-----------------------|---------------------| | Output | VOUT | PC4 | PE7 | | | | & ADC1_IN4| | & COMP2_INN7 if | | | | ADC2_IN4 |connected internally | | | | COMP1_INN7 if | | | | | connected internally | | |-----------------|--------|-----------------------|---------------------|

Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_opamp.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp_ex.c File Reference

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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_opamp_ex.c File Reference

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.
HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.

Detailed Description

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"

/** @addtogroup STM32H7xx_HAL_Driver
  * @{
  */

/** @defgroup OPAMPEx OPAMPEx
  * @brief OPAMP Extended HAL module driver
  * @{
  */

#ifdef HAL_OPAMP_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
  * @{
  */

/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
  * @brief    Extended operation functions
  *
@verbatim
 ===============================================================================
              ##### Extended IO operation functions #####
 ===============================================================================
  [..]
      (+) OPAMP Self calibration.

Definition in file stm32h7xx_hal_opamp_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ospi.c File Reference

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Functions
stm32h7xx_hal_ospi.c File Reference

OSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
Initialize the OSPI mode according to the specified parameters in the OSPI_InitTypeDef and initialize the associated handle.
__weak void | HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi)
Initialize the OSPI MSP.
HAL_StatusTypeDef | HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi)
De-Initialize the OSPI peripheral.
__weak void | HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi)
DeInitialize the OSPI MSP.
void | HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi)
Handle OSPI interrupt request.
HAL_StatusTypeDef | HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
Configure the Hyperbus parameters.
HAL_StatusTypeDef | HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
Set the Hyperbus command configuration.
HAL_StatusTypeDef | HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the OSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
Configure the OSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi)
Transfer Error callback.
__weak void | HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi)
Abort completed callback.
__weak void | HAL_OSPI_FifoThresholdCallback (OSPI_HandleTypeDef *hospi)
FIFO Threshold callback.
__weak void | HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi)
Command completed callback.
__weak void | HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Transfer completed callback.
__weak void | HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Transfer completed callback.
__weak void | HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Rx Half Transfer completed callback.
__weak void | HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi)
Tx Half Transfer completed callback.
__weak void | HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi)
Status Match callback.
__weak void | HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi)
Timeout callback.
HAL_StatusTypeDef | HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
Register a User OSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
Unregister a User OSPI Callback OSPI Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi)
Abort the current transmission (non-blocking function)
HAL_StatusTypeDef | HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold)
Set OSPI Fifo threshold.
uint32_t | HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi)
Get OSPI Fifo threshold.
HAL_StatusTypeDef | HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout)
Set OSPI timeout.
uint32_t | HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi)
Return the OSPI error code.
uint32_t | HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi)
Return the OSPI handle state.
HAL_StatusTypeDef | HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
Configure the OctoSPI IO manager.

Detailed Description

OSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_OSPI_MspInit() :
        (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
        (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
        (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt or DMA mode is used, enable and configure OctoSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the fifo threshold, the dual-quad mode, the memory type, the
          device size, the CS high time, the free running clock, the clock mode,
          the wrap size, the clock prescaler, the sample shifting, the hold delay
          and the CS boundary using the HAL_OSPI_Init() function.
      (#) When using Hyperbus, configure the RW recovery time, the access time,
          the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
          function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) In regular mode, configure the command sequence using the HAL_OSPI_Command()
          or HAL_OSPI_Command_IT() functions :
         (++) Instruction phase : the mode used and if present the size, the instruction
              opcode and the DTR mode.
         (++) Address phase : the mode used and if present the size, the address
              value and the DTR mode.
         (++) Alternate-bytes phase : the mode used and if present the size, the
              alternate bytes values and the DTR mode.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes and the DTR mode.
         (++) Data strobe (DQS) mode : the activation (or not) of this mode
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) Flash identifier : in dual-quad mode, indicates which flash is concerned
         (++) Operation type : always common configuration
      (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
          function :
         (++) Address space : indicate if the access will be done in register or memory
         (++) Address size
         (++) Number of data
         (++) Data strobe (DQS) mode : the activation (or not) of this mode
      (#) If no data is required for the command (only for regular mode, not for
          Hyperbus mode), it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
          HAL_OSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
          HAL_OSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence by the same way than the indirect mode
      (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
          or HAL_OSPI_AutoPolling_IT() functions :
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
    *** MDMA functional mode ***
    ====================================
    [..]
      (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_OSPI_MspInit() function :
         (++) MDMA settings for write operation :
          (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
          (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
              aligned with @ref MDMA_Source_increment_mode .
          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
         (++) MDMA settings for read operation :
          (+) The SourceInc should be MDMA_SRC_INC_DISABLE
          (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
              aligned with @ref MDMA_Destination_increment_mode.
         (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
      (#)In case of wrong MDMA setting
        (++) For write operation :
         (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
        (++) For read operation :
         (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence by the same way than the indirect mode except
          for the operation type in regular mode :
         (++) Operation type equals to read configuration : the command configuration
              applies to read access in memory-mapped mode
         (++) Operation type equals to write configuration : the command configuration
              applies to write access in memory-mapped mode
         (++) Both read and write configuration should be performed before activating
              memory-mapped mode
      (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
          functions :
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_OSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
              the transfer complete bit is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
      (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
      (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold

    *** IO manager configuration functions ***
    ==========================================
    [..]
      (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : OSPI MspInit.
        (+) MspDeInitCallback  : OSPI MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : OSPI MspInit.
        (+) MspDeInitCallback  : OSPI MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init
      and @ref  HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit
      or @ref HAL_OSPI_Init function.

      When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ospi.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_otfdec.c File Reference

  • File List
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stm32h7xx_hal_otfdec.c File Reference

OTFDEC HAL module driver. This file provides firmware functions to manage the following functionalities of the On-The-Fly Decryption (OTFDEC) peripheral: + Initialization and de-initialization functions + Region setting/enable functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OTFDEC_Init (OTFDEC_HandleTypeDef *hotfdec)
Initialize the OTFDEC peripheral and create the associated handle.
HAL_StatusTypeDef | HAL_OTFDEC_DeInit (OTFDEC_HandleTypeDef *hotfdec)
DeInitialize the OTFDEC peripheral.
__weak void | HAL_OTFDEC_MspInit (OTFDEC_HandleTypeDef *hotfdec)
Initialize the OTFDEC MSP.
__weak void | HAL_OTFDEC_MspDeInit (OTFDEC_HandleTypeDef *hotfdec)
DeInitialize OTFDEC MSP.
HAL_StatusTypeDef | HAL_OTFDEC_RegisterCallback (OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback)
Register a User OTFDEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_OTFDEC_UnRegisterCallback (OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
Unregister a OTFDEC Callback OTFDEC callback is redirected to the weak predefined callback.
void | HAL_OTFDEC_IRQHandler (OTFDEC_HandleTypeDef *hotfdec)
Handle OTFDEC interrupt request.
__weak void | HAL_OTFDEC_ErrorCallback (OTFDEC_HandleTypeDef *hotfdec)
OTFDEC error callback.
HAL_StatusTypeDef | HAL_OTFDEC_RegionKeyLock (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Lock region keys.
HAL_StatusTypeDef | HAL_OTFDEC_RegionSetKey (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
Set region keys.
HAL_StatusTypeDef | HAL_OTFDEC_RegionSetMode (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
Set region mode.
HAL_StatusTypeDef | HAL_OTFDEC_RegionConfig (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
Set region configuration.
uint32_t | HAL_OTFDEC_KeyCRCComputation (uint32_t *pKey)
Compute Key CRC.
HAL_StatusTypeDef | HAL_OTFDEC_RegionEnable (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Enable region deciphering.
HAL_StatusTypeDef | HAL_OTFDEC_RegionDisable (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Disable region deciphering.
HAL_OTFDEC_StateTypeDef | HAL_OTFDEC_GetState (OTFDEC_HandleTypeDef *hotfdec)
Return the OTFDEC state.
uint32_t | HAL_OTFDEC_RegionGetKeyCRC (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
Return region keys CRC.
HAL_StatusTypeDef | HAL_OTFDEC_RegionGetConfig (OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config)
Return region configuration parameters.

Detailed Description

OTFDEC HAL module driver. This file provides firmware functions to manage the following functionalities of the On-The-Fly Decryption (OTFDEC) peripheral: + Initialization and de-initialization functions + Region setting/enable functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
 [..]
    The OTFDEC HAL driver can be used as follows:

    (#) Declare an OTFDEC_HandleTypeDef handle structure (eg. OTFDEC_HandleTypeDef hotfdec).

    (#) Initialize the OTFDEC low level resources by implementing the HAL_OTFDEC_MspInit() API:
        (++) Enable the OTFDEC interface clock.
        (++) NVIC configuration if interrupts are used
            (+++) Configure the OTFDEC interrupt priority.
            (+++) Enable the NVIC OTFDEC IRQ handle.

    (#) Initialize the OTFDEC peripheral by calling the HAL_OTFDEC_Init() API.

    (#) For each region,

        (++) Configure the region deciphering mode by calling the HAL_OTFDEC_RegionSetMode() API.

        (++) Write the region Key by calling the HAL_OTFDEC_RegionSetKey() API. If desired,
        read the key CRC by calling HAL_OTFDEC_RegionGetKeyCRC() API and compare the
        result with the theoretically expected CRC.

        (++) Initialize the OTFDEC region config structure with the Nonce, protected
        region start and end addresses and firmware version, and wrap-up the region
        configuration by calling HAL_OTFDEC_RegionConfig() API.

    (#) At this point, the OTFDEC region configuration is done and the deciphering
        is enabled. The region can be deciphered on the fly after having made sure
        the OctoSPI is configured in memory-mapped mode.

    [..]
    (@) Warning: the OTFDEC deciphering is based on a different endianness compared
        to the AES-CTR as implemented in the AES peripheral. E.g., if the OTFEC
        resorts to the Key (B0, B1, B2, B3) where Bi are 32-bit longwords and B0
        is the Least Significant Word, the AES has to be configured with the Key
        (B3, B2, B1, B0) to report the same result (with the same swapping applied
        to the Initialization Vector).

    [..]

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_OTFDEC_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
       (+) ErrorCallback                  : OTFDEC error callback
       (+) MspInitCallback                : OTFDEC Msp Init callback
       (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) ErrorCallback                  : OTFDEC error callback
       (+) MspInitCallback                : OTFDEC Msp Init callback
       (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
     [..]

     By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     example @ref HAL_OTFDEC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
     or @ref HAL_OTFDEC_Init() function.
     [..]

     When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.
Attention:

© Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_otfdec.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.
static HAL_StatusTypeDef | PCD_EP_OutXfrComplete_int (PCD_HandleTypeDef *hpcd, uint32_t epnum)
process EP OUT transfer complete interrupt.
static HAL_StatusTypeDef | PCD_EP_OutSetupPacket_int (PCD_HandleTypeDef *hpcd, uint32_t epnum)
process EP OUT setup packet received interrupt.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pcd.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd_ex.c File Reference

  • File List
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Functions
stm32h7xx_hal_pcd_ex.c File Reference

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pcd_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pssi.c File Reference

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Functions
stm32h7xx_hal_pssi.c File Reference

PSSI HAL module driver. This file provides firmware functions to manage the following functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

void | PSSI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA PSSI slave transmit process complete callback.
void | PSSI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA PSSI master receive process complete callback.
void | PSSI_DMAError (DMA_HandleTypeDef *hdma)
void | PSSI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA PSSI communication abort callback (To be called at end of DMA Abort procedure).
static void | PSSI_Error (PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
PSSI Errors process.
static HAL_StatusTypeDef | PSSI_WaitOnStatusUntilTimeout (PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles PSSI Communication Timeout.
HAL_StatusTypeDef | HAL_PSSI_Init (PSSI_HandleTypeDef *hpssi)
Initializes the PSSI according to the specified parameters in the PSSI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PSSI_DeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI peripheral.
__weak void | HAL_PSSI_MspInit (PSSI_HandleTypeDef *hpssi)
Initialize the PSSI MSP.
__weak void | HAL_PSSI_MspDeInit (PSSI_HandleTypeDef *hpssi)
DeInitialize the PSSI MSP.
HAL_StatusTypeDef | HAL_PSSI_RegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback)
Register a User PSSI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PSSI_UnRegisterCallback (PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
Unregister an PSSI Callback PSSI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PSSI_Transmit (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Receive (PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_PSSI_Transmit_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Receive_DMA (PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_PSSI_Abort_DMA (PSSI_HandleTypeDef *hpssi)
Abort a DMA process communication with Interrupt.
void | HAL_PSSI_IRQHandler (PSSI_HandleTypeDef *hpssi)
This function handles PSSI event interrupt request.
__weak void | HAL_PSSI_TxCpltCallback (PSSI_HandleTypeDef *hpssi)
Tx Transfer complete callback.
__weak void | HAL_PSSI_RxCpltCallback (PSSI_HandleTypeDef *hpssi)
Rx Transfer complete callback.
__weak void | HAL_PSSI_ErrorCallback (PSSI_HandleTypeDef *hpssi)
PSSI error callback.
__weak void | HAL_PSSI_AbortCpltCallback (PSSI_HandleTypeDef *hpssi)
PSSI abort callback.
HAL_PSSI_StateTypeDef | HAL_PSSI_GetState (PSSI_HandleTypeDef *hpssi)
Return the PSSI handle state.
uint32_t | HAL_PSSI_GetError (PSSI_HandleTypeDef *hpssi)
Return the PSSI error code.

Detailed Description

PSSI HAL module driver. This file provides firmware functions to manage the following functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The PSSI HAL driver can be used as follows:

    (#) Declare a PSSI_HandleTypeDef handle structure, for example:
        PSSI_HandleTypeDef  hpssi;

    (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
        (##) Enable the PSSIx interface clock
        (##) PSSI pins configuration
            (+++) Enable the clock for the PSSI GPIOs
            (+++) Configure PSSI pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the PSSIx interrupt priority
            (+++) Enable the NVIC PSSI IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare  DMA_HandleTypeDef handles structure for the transmit and receive
            (+++) Enable the DMAx interface clock
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx and Rx
            (+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx and Rx

    (#) Configure the Communication Bus Width,  Control Signals, Input Polarity and Output Polarity
         in the hpssi Init structure.

    (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.

    (#) For PSSI IO operations, two operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
      (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit an amount of data in non-blocking mode (DMA) using
          @ref HAL_PSSI_Transmit_DMA()
      (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using
          @ref HAL_PSSI_Receive_DMA()
      (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
      (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
      (+) Abort a  PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
      (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()

     *** PSSI HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in PSSI HAL driver.

      (+) @ref HAL_PSSI_ENABLE     : Enable the PSSI peripheral
      (+) @ref HAL_PSSI_DISABLE    : Disable the PSSI peripheral
      (+) @ref HAL_PSSI_GET_FLAG   : Check whether the specified PSSI flag is set or not
      (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
      (+) @ref HAL_PSSI_ENABLE_IT  : Enable the specified PSSI interrupt
      (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt

     *** Callback registration ***
     =============================================
     Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
     to register an interrupt callback.

     Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
       (+) TxCpltCallback       : callback for transmission end of transfer.
       (+) RxCpltCallback       : callback for reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.

     Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) TxCpltCallback       : callback for transmission end of transfer.
       (+) RxCpltCallback       : callback for reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.

     By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

     Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
     or @ref HAL_PSSI_Init() function.

     [..]
       (@) You can refer to the PSSI HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pssi.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr.c File Reference

  • File List
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  • Src
Defines | Functions
stm32h7xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions. + Peripheral Control functions. + Interrupt Handling functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT (0x00010000U)
#define | PVD_MODE_EVT (0x00020000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)
#define | PVD_RISING_FALLING_EDGE (0x00000003U)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the event mode and the voltage threshold detected by the Programmable Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Programmable Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Programmable Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter the current core in SLEEP mode (CSLEEP).
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND feature.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions. + Peripheral Control functions. + Interrupt Handling functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### PWR peripheral overview #####
  ==============================================================================
  [..]
   (#) The Power control (PWR) provides an overview of the supply architecture
       for the different power domains and of the supply configuration
       controller.
       In the H7 family, the number of power domains is different between
       device lines. This difference is due to characteristics of each device.

   (#) Domain architecture overview for the different H7 lines:
      (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
          These devices have 3 power domains (D1, D2 and D3).
          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
          peripherals. The D2 domain contains peripherals and a CPU
          (Cortex-M4). The D3 domain contains the system control, I/O logic
          and low-power peripherals.
      (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
          domains (D1, D2 and D3).
          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
          peripherals. The D2 domain contains peripherals. The D3 domains
          contains the system control, I/O logic and low-power peripherals.
      (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
          power domains (CD and SRD).
          The core domain (CD) contains a CPU (Cortex-M7), a Flash
          memory and peripherals. The SmartRun domain contains the system
          control, I/O logic and low-power peripherals.

   (#) Every entity have low power mode as decribed below :
   (#) The CPU low power modes are :
      (+) CPU CRUN.
      (+) CPU CSLEEP.
      (+) CPU CSTOP.
   (#) The domain low power modes are :
      (+) DRUN.
      (+) DSTOP.
      (+) DSTANDBY.
   (#) The SYSTEM low power modes are :
      (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
                 Standby. In Run* mode, the performance is limited and the
                 system supply configuration shall be programmed. The system
                 enters Run mode only when the ACTVOSRDY bit in PWR control
                 status register 1 (PWR_CSR1) is set to 1.
      (+) RUN.
      (+) STOP.
      (+) STANDBY.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Power management peripheral is active by default at startup level in
       STM32h7xx lines.

   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
       to enable/disable access to the backup domain (RTC registers, RTC backup
       data registers and backup SRAM).

   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
       mode and voltage threshold) in order to set up the Power Voltage Detector,
       then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
       and stop the PVD detection.
       (+) PVD level could be one of the following values :
             (++) 1V95
             (++) 2V1
             (++) 2V25
             (++) 2V4
             (++) 2V55
             (++) 2V7
             (++) 2V85
             (++) External voltage level

   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
       with the right parameter to configure the wake up pin polarity (Low or
       High) and to enable and disable it.

   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
       mode. Wake-up from SLEEP mode could be following to an event or an
       interrupt according to low power mode intrinsic request called (__WFI()
       or __WFE()).
       Please ensure to clear all CPU pending events by calling
       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
       in SLEEP mode with __WFE() entry.

   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
       mode for single core devices. For dual core devices, this API will enter
       the domain (containing Cortex-Mx that executing this function) in DSTOP
       mode. According to the used parameter, user could select the regulator to
       be kept actif in low power mode and wake-up event type.
       Please ensure to clear all CPU pending events by calling
       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
       in CSTOP mode with __WFE() entry.

   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
       STANDBY mode for single core devices. For dual core devices, this API
       will enter the domain (containing Cortex-Mx that executing this function)
       in DSTANDBY mode.

   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
       enable and disable the Cortex-Mx re-entring in SLEEP mode after an
       interruption handling is over.

   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
       to configure the Cortex-Mx to wake-up after any pending event / interrupt
       even if it's disabled or has insufficient priority to cause exception
       entry.

   (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
       request.

     *** PWR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in PWR HAL driver.

      (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
                                              regulator output voltage.
      (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
      (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pwr.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr_ex.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | AVD_MODE_IT (0x00010000U)
#define | AVD_MODE_EVT (0x00020000U)
#define | AVD_RISING_EDGE (0x00000001U)
#define | AVD_FALLING_EDGE (0x00000002U)
#define | AVD_RISING_FALLING_EDGE (0x00000003U)
#define | PWR_FLAG_SETTING_DELAY (1000U)
#define | PWR_EXTI_WAKEUP_PINS_MASK
#define | PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.
void | HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode with main domain in DSTOP2.
void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_ClearPendingEvent (void)
Clear pending event.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3/SRD Domain state when the System in low power mode.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
Enable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
Disable memory block shut-off in DStop or DStop2 modes.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin pending flags.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin pending flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.
void | HAL_PWREx_EnableAnalogBooster (void)
Enable the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2V7.
void | HAL_PWREx_DisableAnalogBooster (void)
Disable the analog booster.
void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the thresholds.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the thresholds.
PWREx_MMC_VoltageLevel | HAL_PWREx_GetMMCVoltage (void)
Get the VDDMMC voltage level.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the event mode and the voltage threshold detected by the Analog Voltage Detector (AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector (AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
       with the following different setups according to hardware (support SMPS):
       (+) PWR_DIRECT_SMPS_SUPPLY
       (+) PWR_SMPS_1V8_SUPPLIES_LDO
       (+) PWR_SMPS_2V5_SUPPLIES_LDO
       (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
       (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
       (+) PWR_SMPS_1V8_SUPPLIES_EXT
       (+) PWR_SMPS_2V5_SUPPLIES_EXT
       (+) PWR_LDO_SUPPLY
       (+) PWR_EXTERNAL_SOURCE_SUPPLY

   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.

   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
       internal regulator output voltage. The voltage scaling could be one of
       the following scales :
       (+) PWR_REGULATOR_VOLTAGE_SCALE0
       (+) PWR_REGULATOR_VOLTAGE_SCALE1
       (+) PWR_REGULATOR_VOLTAGE_SCALE2
       (+) PWR_REGULATOR_VOLTAGE_SCALE3

   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
       voltage applied to the main regulator.

   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
       main internal regulator output voltage in STOP mode. The voltage scaling
       in STOP mode could be one of the following scales :
       (+) PWR_REGULATOR_SVOS_SCALE3
       (+) PWR_REGULATOR_SVOS_SCALE4
       (+) PWR_REGULATOR_SVOS_SCALE5

   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
       output voltage applied to the main regulator in STOP mode.

   (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
       with core domain in D2STOP mode. This API is used only for STM32H7Axxx
       and STM32H7Bxxx devices.
       Please ensure to clear all CPU pending events by calling
       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
       in DEEP-SLEEP mode with __WFE() entry.

   (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
       DSTOP mode. Call this API with all available power domains to enter the
       system in STOP mode.
       Please ensure to clear all CPU pending events by calling
       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
       in DEEP-SLEEP mode with __WFE() entry.

   (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
       Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.

   (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
       in DSTANDBY mode. Call this API with all available power domains to enter
       the system in STANDBY mode.

   (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
       (RUN/STOP) when the system enter to low power mode.

   (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
       selected power domain. This API is used only for dual core devices.

   (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
       and release the selected CPU and and their domain peripherals when
       exiting STOP mode. These APIs are used only for dual core devices.

   (#) Call HAL_PWREx_EnableFlashPowerDown() and
       HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
       Flash Power Down in STOP mode.

   (#) Call HAL_PWREx_EnableMemoryShutOff() and
       HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
       memory block shut-off in DStop or DStop2. These APIs are used only for
       STM32H7Axxx and STM32H7Bxxx lines.

   (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
       functions to enable and disable the Wake-up pin functionality for
       the selected pin.

   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
       functions to manage wake-up flag for the selected pin.

   (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
       pins interrupts.

   (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
       to enable and disable the backup domain regulator.

   (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
       HAL_PWREx_EnableUSBVoltageDetector() and
       HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
       regulation functionnalities.

   (#) Call HAL_PWREx_EnableBatteryCharging() and
       HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
       battery charging feature with the selected resistor.

   (#) Call HAL_PWREx_EnableAnalogBooster() and
       HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
       AVD boost feature when the VDD supply voltage is below 2V7.

   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
       functions to enable and disable the VBAT and Temperature monitoring.
       When VBAT and Temperature monitoring feature is enables, use
       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
       respectively the Temperature level and VBAT level.

   (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
       function to get VDDMMC voltage level. This API is used only for
       STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines

   (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
       (event mode and voltage threshold) in order to set up the Analog Voltage
       Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
       functions to start and stop the AVD detection.
       (+) AVD level could be one of the following values :
             (++) 1V7
             (++) 2V1
             (++) 2V5
             (++) 2V8

   (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
       AVD interrupt request.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_pwr_ex.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ramecc.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_ramecc.c File Reference

RAMECC HAL module driver. This file provides firmware functions to manage the following functionalities of the RAM ECC monitoring (RAMECC) peripheral: + Initialization and de-initialization functions + Monitoring operation functions + Error informations functions + State and error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
Initialize the RAMECC by clearing flags and disabling interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
DeInitializes the RAMECC peripheral.
HAL_StatusTypeDef | HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
Starts the RAMECC latching error information.
HAL_StatusTypeDef | HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
Stop the RAMECC latching error informations.
HAL_StatusTypeDef | HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Enable the RAMECC error interrupts.
HAL_StatusTypeDef | HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
Disable the RAMECC error interrupts.
HAL_StatusTypeDef | HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void(*pCallback)(RAMECC_HandleTypeDef *_hramecc))
Register callbacks.
HAL_StatusTypeDef | HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
UnRegister callbacks.
void | HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
Handles RAMECC interrupt request.
uint32_t | HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC failing address.
uint32_t | HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data low.
uint32_t | HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC data high.
uint32_t | HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
Return the RAMECC Hamming bits injected.
uint32_t | HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC single error was occured.
uint32_t | HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
Check if an ECC double error was occured.
HAL_RAMECC_StateTypeDef | HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral state.
uint32_t | HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
Get the RAMECC peripheral error code.

Detailed Description

RAMECC HAL module driver. This file provides firmware functions to manage the following functionalities of the RAM ECC monitoring (RAMECC) peripheral: + Initialization and de-initialization functions + Monitoring operation functions + Error informations functions + State and error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and latch error informations through HAL_RAMECC_Init().

   (#) For a given Monitor, enable and disable interrupt through
       HAL_RAMECC_EnableNotifiaction().
       To enable a notification for a given RAMECC instance, use global
       interrupts.
       To enable a notification for only RAMECC monitor, use monitor interrupts.
       All possible notifications are defined in the driver header file under
       RAMECC_Interrupt group.

     *** Silent mode ***
     ===================
    [..]
          (+) Use HAL_RAMECC_StartMonitor() to start RAMECC latch failing
              information without enabling any notification.

     *** Interrupt mode ***
     ======================
    [..]
          (+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a
              given error.
          (+) Configure the RAMECC interrupt priority using
              HAL_NVIC_SetPriority().
          (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().

     *** Failing informations ***
     ======================
    [..]
     (#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC
         failing address.
     (#) Use HAL_RAMECC_GetFailingDataLow() function to return the RAMECC
         failing data low.
     (#) Use HAL_RAMECC_GetFailingDataHigh() function to return the RAMECC
         failing data high.
     (#) Use HAL_RAMECC_GetHammingErrorCode() function to return the RAMECC
         Hamming bits injected.
     (#) Use HAL_RAMECC_IsECCSingleErrorDetected() function to check if a single
         error was detected and corrected.
     (#) Use HAL_RAMECC_IsECCDoubleErrorDetected() function to check if a double
         error was dedetected.

     *** RAMECC HAL driver macros list ***
     =============================================
     [..]
       Below the list of used macros in RAMECC HAL driver.

      (+) __HAL_RAMECC_ENABLE_IT  : Enable the specified ECCRAM Monitor
                                    interrupts.
      (+) __HAL_RAMECC_DISABLE_IT : Disable the specified ECCRAM Monitor
                                    interrupts.
      (+) __HAL_RAMECC_GET_FLAG   : Return the current RAMECC Monitor selected
                                    flag.
      (+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
                                    flag.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_ramecc.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc.c File Reference

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Defines | Functions
stm32h7xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
      internal SRAM, Flash, JTAG and PWR
      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analogue mode , except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses pre-scalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock kernel source(s) for peripherals which clocks are not
          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
          and RCC_D3CCIPR registers

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
          after the clock enable bit is set on the hardware register
      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
          after the clock enable bit is set on the hardware register

    [..]
      Implemented Workaround:
      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rcc.c.

Generated on Tue Nov 12 2019 18:50:06 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define | PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U

Functions

static HAL_StatusTypeDef | RCCEx_PLL2_Config (RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.
static HAL_StatusTypeDef | RCCEx_PLL3_Config (RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rcc_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng.c File Reference

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Defines | Functions
stm32h7xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_HTCFG_1 0x17590ABCU
#define | RNG_HTCFG 0x000CAA74U
#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
    Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.

    [..]
    For specific callback ReadyDataCallback, use dedicated register callbacks:
    respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().

    [..]
    By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    example @ref HAL_RNG_ErrorCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
    and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
    or @ref HAL_RNG_Init() function.

    [..]
    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rng.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_rng_ex.c File Reference

Extended RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Lock configuration functions + Reset the RNG. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_HTCFG_1 0x17590ABCU
#define | RNG_HTCFG 0x000CAA74U
#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNGEx_SetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Configure the RNG with the specified parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_GetConfig (RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
Get the RNG Configuration and fill parameters in the RNG_ConfigTypeDef.
HAL_StatusTypeDef | HAL_RNGEx_LockConfig (RNG_HandleTypeDef *hrng)
RNG current configuration lock.

Detailed Description

Extended RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Lock configuration functions + Reset the RNG.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rng_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc.c File Reference

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Functions
stm32h7xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.
    (#) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
 ===================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
 ===================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.

  *** Callback registration ***
  =============================================
  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions. This is the recommended configuration
  in order to optimize memory/code consumption footprint/performances.

  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.

  Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.

  By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
  all callbacks are set to the corresponding weak functions :
  examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
  in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
  (not registered beforehand).
  If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
  or @ref HAL_RTC_Init() function.

  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rtc.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveTampers (RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper)
Set all active Tampers at the same time.
HAL_StatusTypeDef | HAL_RTCEx_SetActiveSeed (RTC_HandleTypeDef *hrtc, uint32_t *pSeed)
Write a new seed.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateActiveTampers (RTC_HandleTypeDef *hrtc)
Deactivate all Active Tampers at the same time.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper1EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 1 callback.
__weak void | HAL_RTCEx_InternalTamper2EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 2 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
__weak void | HAL_RTCEx_InternalTamper8EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 8 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterIncrement (RTC_HandleTypeDef *hrtc)
Increment Monotonic counter.
HAL_StatusTypeDef | HAL_RTCEx_MonotonicCounterGet (RTC_HandleTypeDef *hrtc, uint32_t *Counter)
Monotonic counter incrementation.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The default configuration of the Tamper erases the backup registers. To avoid
        erase, enable the NoErase field on the RTC_TAMPCR register.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_rtc_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai.c File Reference

  • File List
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Defines | Enumerations | Functions
stm32h7xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_FIFO_SIZE 8U
#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

    (#) The initialization can be done by two ways
        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().

  [..]
    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
        inside the transmit and receive process.
  [..]
    (@) Make sure that either:
        (+@) PLLSAI1CLK output is configured or
        (+@) PLLSAI2CLK output is configured or
        (+@) PLLSAI3CLK output is configured or
        (+@) PLLSAI4ACLK output is configured or
        (+@) PLLSAI4BCLK output is configured or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@) First bit Offset <= (SLOT size - Data size)
        (+@) Data size <= SLOT size
        (+@) Number of SLOT x SLOT size = Frame length
        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
    (@) PDM interface can be activated through HAL_SAI_Init function.
        Please note that PDM interface is only available for SAI1 or SAI4 sub-block A.
        PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

    *** SAI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SAI HAL driver :

      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
      (+) HAL_SAI_Abort(): Abort the current transfer

    *** SAI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SAI HAL driver :

      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not

    *** Callback registration ***
    =============================
    [..]
    The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.
    Use functions HAL_SAI_RegisterCallback() to register a user callback.

    [..]
    Function HAL_SAI_RegisterCallback() allows to register following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.

    [..]
    By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
    examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
    and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
    or HAL_SAI_Init function.

    [..]
    When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sai.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai_ex.c File Reference

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Defines | Functions
stm32h7xx_hal_sai_ex.c File Reference

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sai_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd.c File Reference

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Defines | Functions
stm32h7xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE)

Functions

static uint32_t | SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the sd card.
static uint32_t | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static uint32_t | SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Send Status info command.
static uint32_t | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static uint32_t | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static uint32_t | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static uint32_t | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static void | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static void | SD_Write_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static void | SD_Read_IT (SD_HandleTypeDef *hsd)
Wrap up reading in non-blocking mode.
static uint32_t | SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
static uint32_t | SD_UltraHighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to Ultra High Speed mode.
static uint32_t | SD_DDR_Mode (SD_HandleTypeDef *hsd)
Switches the SD card to Double Data Rate (DDR) mode.
HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransceiver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transceiver 1.8V Mode Callback.
HAL_StatusTypeDef | HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
Register a User SD Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
Unregister a User SD Callback SD Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
Register a User SD Transceiver Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_UnRegisterTransceiverCallback (SD_HandleTypeDef *hsd)
Unregister a User SD Transceiver Callback SD Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_SD_ConfigSpeedBusOperation (SD_HandleTypeDef *hsd, uint32_t SpeedMode)
Configure the speed bus mode.
HAL_SD_CardStateTypeDef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).
__weak void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
        (##) SDMMC pins configuration for SD card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
             and HAL_SD_WriteBlocks_IT() APIs).
            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
                  and __HAL_SD_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
                  and __HAL_SD_CLEAR_IT()
        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.

    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
    SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
        type (Standard Capacity or High Capacity). You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDMMC_CK) is computed as follows:

           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)

        In initialization mode and according to the SD Card standard,
        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

        This phase of initialization is done through SDMMC_Init() and
        SDMMC_PowerState_ON() SDMMC low level APIs.

    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
        This phase allows the card initialization and identification
        and check the SD Card type (Standard Capacity or High Capacity)
        The initialization flow is compatible with SD standard.

        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
        of plug-off plug-in.

    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the DMA transfer process through the SD Rx interrupt event.

    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the IT transfer process through the SD Rx interrupt event.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the DMA transfer process through the SD Tx interrupt event.

    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the IT transfer process through the SD Tx interrupt event.

  *** SD card status ***
  ======================
  [..]
    (+) The SD Status contains status bits that are related to the SD Memory
        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().

  *** SD card information ***
  ===========================
  [..]
    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
        It returns useful information about the SD card such as block size, card type,
        block number ...

  *** SD card CSD register ***
  ============================
    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
        Some of the CSD parameters are useful for card initialization and identification.

  *** SD card CID register ***
  ============================
    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
        Some of the CSD parameters are useful for card initialization and identification.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags

    (@) You can refer to the SD HAL driver header file for more useful macros

  *** Callback registration ***
  =============================================
  [..]
    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
    it allows to register following callbacks:
      (+) TxCpltCallback : callback when a transmission transfer is completed.
      (+) RxCpltCallback : callback when a reception transfer is completed.
      (+) ErrorCallback : callback when error occurs.
      (+) AbortCpltCallback : callback when abort is completed.
      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
      (+) MspInitCallback    : SD MspInit.
      (+) MspDeInitCallback  : SD MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.
    For specific callbacks TransceiverCallback use dedicated register callbacks:
    respectively @ref HAL_SD_RegisterTransceiverCallback().

    Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function. It allows to reset following callbacks:
      (+) TxCpltCallback : callback when a transmission transfer is completed.
      (+) RxCpltCallback : callback when a reception transfer is completed.
      (+) ErrorCallback : callback when error occurs.
      (+) AbortCpltCallback : callback when abort is completed.
      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
      (+) MspInitCallback    : SD MspInit.
      (+) MspDeInitCallback  : SD MspDeInit.
    This function) takes as parameters the HAL peripheral handle and the Callback ID.
    For specific callbacks TransceiverCallback use dedicated unregister callbacks:
    respectively @ref HAL_SD_UnRegisterTransceiverCallback().

    By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
    and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
    or @ref HAL_SD_Init function.

    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sd.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd_ex.c File Reference

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stm32h7xx_hal_sd_ex.c File Reference

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.

Detailed Description

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   The SD Extension HAL driver can be used as follows:
   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
   (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sd_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sdram.c File Reference

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Functions
stm32h7xx_hal_sdram.c File Reference

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
Register a User SDRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
Unregister a User SDRAM Callback SDRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_RegisterDmaCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
Register a User SDRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                       ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SDRAM memories. It uses the FMC layer functions to interface
    with SDRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SDRAM memories:

   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
          SDRAM_HandleTypeDef  hsdram

       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SDRAM device

   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
          FMC_SDRAM_TimingTypeDef  Timing;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
       (##) Control register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Init()
       (##) Timing register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Timing_Init()
       (##) Program the SDRAM external device by applying its initialization sequence
            according to the device plugged in your hardware. This step is mandatory
            for accessing the SDRAM device.

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the SDRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
       structure.

   (#) You can continuously monitor the SDRAM device HAL state by calling the function
       HAL_SDRAM_GetState()

   *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : SDRAM MspInit.
        (+) MspDeInitCallback  : SDRAM MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) MspInitCallback    : SDRAM MspInit.
        (+) MspDeInitCallback  : SDRAM MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
      and @ref  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
      or @ref HAL_SDRAM_Init function.

      When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sdram.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard.c File Reference

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Defines | Functions
stm32h7xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
    Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.

    [..]
    By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
    and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
    or @ref HAL_SMARTCARD_Init() function.

    [..]
    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smartcard.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard_ex.c File Reference

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Defines | Functions
stm32h7xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.
void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smartcard_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smbus.c File Reference

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Defines | Functions
stm32h7xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static void | SMBUS_Enable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (struct __SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (struct __SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
        (##) Enable the SMBUSx interface clock
        (##) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
      (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
      (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
           to check the Error Code using function @ref HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) @ref __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
      (+) @ref __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
      (+) @ref __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
      (+) @ref __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
      (+) @ref __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
      (+) @ref __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
    [..]
     Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
    [..]
     By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
     or @ref HAL_SMBUS_Init() function.
    [..]
     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_smbus.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spdifrx.c File Reference

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Defines | Functions
stm32h7xx_hal_spdifrx.c File Reference

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
This function handles SPDIFRX Communication Timeout.
HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_RegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
Register a User SPDIFRX Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_UnRegisterCallback (SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
Unregister a SPDIFRX Callback SPDIFRX callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveCtrlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef const *const hspdif)
Return the SPDIFRX error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The SPDIFRX HAL driver can be used as follow:

    (#) Declare SPDIFRX_HandleTypeDef handle structure.
    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
        (##) Enable the SPDIFRX interface clock.
        (##) SPDIFRX pins configuration:
            (+++) Enable the clock for the SPDIFRX GPIOs.
            (+++) Configure these SPDIFRX pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
            (+++) Configure the SPDIFRX interrupt priority.
            (+++) Enable the NVIC SPDIFRX IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
            (+++) Configure the DMA Channel.
            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA CtrlRx/DataRx channel.

   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
       using HAL_SPDIFRX_Init() function.

   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
   -@- Make sure that ck_spdif clock is configured.

   (#) Three operation modes are available within this driver :

   *** Polling mode for reception operation (for debug purpose) ***
   ================================================================
   [..]
     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
     (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow()

   *** Interrupt mode for reception operation ***
   =========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
     (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow_IT()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback

   *** DMA mode for reception operation ***
   ========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
     (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()

   *** SPDIFRX HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in SPDIFRX HAL driver.
      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.

   [..]
      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.

  The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
    (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
    (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
    (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
    (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
    (+) ErrorCallback       : SPDIFRX error callback.
    (+) MspInitCallback     : SPDIFRX MspInit.
    (+) MspDeInitCallback   : SPDIFRX MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default
  weak function.
  The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset the following callbacks:
    (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
    (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
    (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
    (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
    (+) ErrorCallback       : SPDIFRX error callback.
    (+) MspInitCallback     : SPDIFRX MspInit.
    (+) MspDeInitCallback   : SPDIFRX MspDeInit.

  By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(),
  HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback()
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when
  these callbacks pointers are NULL (not registered beforehand).
  If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit()
  or HAL_SPDIFRX_Init() function.

  When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spdifrx.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100UL

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitOnFlagUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_TxISR_32BIT (SPI_HandleTypeDef *hspi)
Handle the data 32-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_32BIT (SPI_HandleTypeDef *hspi)
Manage the 32-bit receive in Interrupt context.
static void | SPI_AbortTransfer (SPI_HandleTypeDef *hspi)
Abort Transfer and clear flags.
static void | SPI_CloseTransfer (SPI_HandleTypeDef *hspi)
Close Transfer and clear flags.
static uint32_t | SPI_GetPacketSize (SPI_HandleTypeDef *hspi)
Compute configured packet size from fifo perspective.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process or DMA process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Callback registration:

      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.

          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
            (+) TxCpltCallback        : SPI Tx Completed callback
            (+) RxCpltCallback        : SPI Rx Completed callback
            (+) TxRxCpltCallback      : SPI TxRx Completed callback
            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (+) ErrorCallback         : SPI Error callback
            (+) AbortCpltCallback     : SPI Abort callback
            (+) MspInitCallback       : SPI Msp Init callback
            (+) MspDeInitCallback     : SPI Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (+) TxCpltCallback        : SPI Tx Completed callback
            (+) RxCpltCallback        : SPI Rx Completed callback
            (+) TxRxCpltCallback      : SPI TxRx Completed callback
            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (+) ErrorCallback         : SPI Error callback
            (+) AbortCpltCallback     : SPI Abort callback
            (+) MspInitCallback       : SPI Msp Init callback
            (+) MspDeInitCallback     : SPI Msp DeInit callback

       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
       or HAL_SPI_Init() function.

       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

    [..]
      Circular mode restriction:
      (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (++) Master 2Lines RxOnly
          (++) Master 1Line Rx
      (+) The CRC feature is not managed when the DMA circular mode is enabled
      (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
          HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
          Those functions are maintained for backward compatibility reasons.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spi.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi_ex.c File Reference

  • File List
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  • Firmware
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuration register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_spi_ex.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sram.c File Reference

  • File List
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  • Firmware
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
Register a User SRAM Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
Unregister a User SRAM Callback SRAM Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_RegisterDmaCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
Register a User SRAM Callback for DMA transfers To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()

       *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : SRAM MspInit.
        (+) MspDeInitCallback  : SRAM MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) MspInitCallback    : SRAM MspInit.
        (+) MspDeInitCallback  : SRAM MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
      and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
      or @ref HAL_SRAM_Init function.

      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_sram.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_swpmi.c File Reference

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Defines | Functions
stm32h7xx_hal_swpmi.c File Reference

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SWPMI_TIMEOUT_VALUE 22000U /* End of transmission timeout */
#define | SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE 2000U /* Transceiver ready timeout */

Functions

static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static void | SWPMI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication abort callback.
static void | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static void | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static void | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static void | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static void | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.
HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_RegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID, pSWPMI_CallbackTypeDef pCallback)
Register a user SWPMI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SWPMI_UnRegisterCallback (SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID)
Unregister a user SWPMI callback.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
     The SWPMI HAL driver can be used as follows:

    (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).

    (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
        (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
        (##) SWPMI IO configuration:
            (+++) Enable the clock for the SWPMI GPIO.
            (+++) Configure these SWPMI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
             and HAL_SWPMI_Receive_IT() APIs):
            (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
            (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().

        (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
             and HAL_SWPMI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx streams.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx streams and requests.
            (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx streams.

    (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.

    (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SWPMI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SWPMI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SWPMI_Transmit_IT()
      (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SWPMI_Receive_IT()
      (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback()
      (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Receive_DMA()
      (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback()
      (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SWPMI_ErrorCallback()
      (+) Stop the DMA Transfer using HAL_SWPMI_DMAStop()

    *** SWPMI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SWPMI HAL driver :

      (+) HAL_SWPMI_EnableLoopback(): Enable the loopback mode for test purpose only
      (+) HAL_SWPMI_DisableLoopback(): Disable the loopback mode

    *** SWPMI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SWPMI HAL driver :

      (+) __HAL_SWPMI_ENABLE(): Enable the SWPMI peripheral
      (+) __HAL_SWPMI_DISABLE(): Disable the SWPMI peripheral
      (+) __HAL_SWPMI_TRANSCEIVER_ENABLE(): Enable the SWPMI peripheral transceiver
      (+) __HAL_SWPMI_TRANSCEIVER_DISABLE(): Disable the SWPMI peripheral transceiver
      (+) __HAL_SWPMI_ENABLE_IT(): Enable the specified SWPMI interrupts
      (+) __HAL_SWPMI_DISABLE_IT(): Disable the specified SWPMI interrupts
      (+) __HAL_SWPMI_GET_IT_SOURCE(): Check if the specified SWPMI interrupt source is
          enabled or disabled
      (+) __HAL_SWPMI_GET_FLAG(): Check whether the specified SWPMI flag is set or not

    *** Callback registration ***
    =============================
    [..]
      The compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.
    [..]
      Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows
      to register the following callbacks:
      (+) RxCpltCallback     : SWPMI receive complete.
      (+) RxHalfCpltCallback : SWPMI receive half complete.
      (+) TxCpltCallback     : SWPMI transmit complete.
      (+) TxHalfCpltCallback : SWPMI transmit half complete.
      (+) ErrorCallback      : SWPMI error.
      (+) MspInitCallback    : SWPMI MspInit.
      (+) MspDeInitCallback  : SWPMI MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.
    [..]
    Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the callback ID.
    This function allows to reset following callbacks:
      (+) RxCpltCallback     : SWPMI receive complete.
      (+) RxHalfCpltCallback : SWPMI receive half complete.
      (+) TxCpltCallback     : SWPMI transmit complete.
      (+) TxHalfCpltCallback : SWPMI transmit half complete.
      (+) ErrorCallback      : SWPMI error.
      (+) MspInitCallback    : SWPMI MspInit.
      (+) MspDeInitCallback  : SWPMI MspDeInit.
    [..]
    By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
    examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init
    and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit
    or HAL_SWPMI_Init function.
    [..]
    When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_swpmi.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim.c File Reference

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Functions
stm32h7xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output
       (#) Synchronization circuit to control the timer with external signals and to interconnect
            several timers together.
       (#) Supports incremental encoder for positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
            in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()

    *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.

  [..]
  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.

  [..]
  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.

  [..]
  These functions allow to register/unregister following callbacks:
    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
    (+) TriggerCallback                   : TIM Trigger Callback.
    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
    (+) IC_CaptureCallback                : TIM Input Capture Callback.
    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
    (+) ErrorCallback                     : TIM Error Callback.
    (+) CommutationCallback               : TIM Commutation Callback.
    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
    (+) BreakCallback                     : TIM Break Callback.
    (+) Break2Callback                    : TIM Break2 Callback.

  [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init / DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)

  [..]
    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
    Exception done MspInit / MspDeInit that can be registered / unregistered
    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.

  [..]
      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_tim.c.

Generated on Tue Nov 12 2019 18:50:07 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim_ex.c File Reference

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stm32h7xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Timer remapping capabilities configuration. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Timer remapping capabilities configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
               Timer Hall Sensor Interface and the commutation event with the corresponding
               Interrupt and DMA request if needed (Note that One Timer is used to interface
               with the Hall sensor Interface and another Timer should be used to use
               the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_tim_ex.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart.c File Reference

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Defines | Functions
stm32h7xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
                inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.

    [..]
    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
    or @ref HAL_UART_Init() function.

    [..]
    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_uart.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_uart_ex.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart.c File Reference

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Defines | Functions
stm32h7xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
          (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
    Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.

    [..]
    By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
    and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
    or @ref HAL_USART_Init() function.

    [..]
    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_usart.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_usart_ex.c File Reference

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.
__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
               ##### USART peripheral extended features  #####
  ==============================================================================

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

    (#) Slave mode enabling/disabling and NSS pin configuration.

        -@- When USART operates in Slave mode, Slave mode must be enabled prior
            starting RX/TX transfers.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_usart_ex.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_wwdg.c File Reference

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Functions
stm32h7xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### WWDG Specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls down from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
        where T[5;0] are the lowest 6 bits of Counter.
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
    (+) Typical values:
        (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
             max timeout before reset: approximately 73.14µs
        (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
             max timeout before reset: approximately 599.18ms

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================

    *** Common driver usage ***
    ===========================

  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Set the WWDG prescaler, refresh window and counter value
        using HAL_WWDG_Init() function.
    (+) Start the WWDG using HAL_WWDG_Start() function.
        When the WWDG is enabled the counter value should be configured to
        a value greater than 0x40 to prevent generating an immediate reset.
    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
        generated when the counter reaches 0x40, and then start the WWDG using
        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
        add his own code by customization of callback HAL_WWDG_WakeupCallback.
        Once enabled, EWI interrupt cannot be disabled except by a system reset.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

    *** Callback registration ***
    =============================

  [..]
    The compilation define  USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
    the user to configure dynamically the driver callbacks. Use Functions
    @ref HAL_WWDG_RegisterCallback() to register a user callback.

    (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
        callbacks:
        (++) EwiCallback : callback for Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
    the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
    takes as parameters the HAL peripheral handle and the Callback ID.
    This function allows to reset following callbacks:
        (++) EwiCallback : callback for  Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.

    [..]
    When calling @ref HAL_WWDG_Init function, callbacks are reset to the
    corresponding legacy weak (surcharged) functions:
    @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
    not been registered before.

    [..]
    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.

    *** WWDG HAL driver macros list ***
    ===================================
    [..]
      Below the list of most used macros in WWDG HAL driver.
      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_hal_wwdg.c.

Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crs.c File Reference

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Functions
stm32h7xx_ll_crs.c File Reference
#include "stm32h7xx_ll_crs.h"
#include "stm32h7xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.
Generated on Tue Nov 12 2019 18:50:08 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_delayblock.c File Reference

  • File List
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Defines | Functions
stm32h7xx_ll_delayblock.c File Reference

DelayBlock Low Layer HAL module driver. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DLYB_TIMEOUT 0xFFU

Functions

HAL_StatusTypeDef | DelayBlock_Enable (DLYB_TypeDef *DLYBx)
Enable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Disable (DLYB_TypeDef *DLYBx)
Disable the Delay Block instance.
HAL_StatusTypeDef | DelayBlock_Configure (DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units)
Configure the Delay Block instance.

Detailed Description

DelayBlock Low Layer HAL module driver.

Author:
MCD Application Team This file provides firmware functions to manage the following functionalities of the Delay Block peripheral: + input clock frequency range 25MHz to 208MHz + up to 12 oversampling phases
  ==============================================================================
                       ##### DelayBlock peripheral features #####
  ==============================================================================
    [..] The Delay block is used to generate an Output clock which is de-phased from the Input
          clock. The phase of the Output clock is programmed by FW. The Output clock is then used
          to clock the receive data in i.e. a SDMMC or QSPI interface.
         The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
          and recenter the Output clock phase to the receive data.

    [..] The Delay Block features include the following:
         (+) Input clock frequency range 25MHz to 208MHz.
         (+) Up to 12 oversampling phases.

                           ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a considered as a driver of service for external devices drivers
      that interfaces with the DELAY peripheral.
      The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
      and configure the Output clock phase.
      The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
Attention:

© Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_delayblock.c.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_pwr.c File Reference

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Functions
stm32h7xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32h7xx_ll_pwr.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32h7xx_ll_pwr.c.

Generated on Tue Nov 12 2019 18:50:09 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__ADC_HandleTypeDef | ADC handle Structure definition
__CEC_HandleTypeDef | CEC handle Structure definition
__COMP_HandleTypeDef | COMP Handle Structure definition
__CRYP_HandleTypeDef | CRYP handle Structure definition
__DAC_HandleTypeDef | DAC handle Structure definition
__DCMI_HandleTypeDef | DCMI handle Structure definition
__DFSDM_Channel_HandleTypeDef | DFSDM channel handle structure definition
__DFSDM_Filter_HandleTypeDef | DFSDM filter handle structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__FDCAN_HandleTypeDef | FDCAN handle structure definition
__GFXMMU_HandleTypeDef | GFXMMU handle structure definition
__HASH_HandleTypeDef | HASH Handle Structure definition
__HCD_HandleTypeDef |
__I2C_HandleTypeDef |
__I2S_HandleTypeDef | I2S handle Structure definition
__IRDA_HandleTypeDef | IRDA handle Structure definition
__JPEG_HandleTypeDef |
__LPTIM_HandleTypeDef | LPTIM handle Structure definition
__LTDC_HandleTypeDef | LTDC handle Structure definition
__MDIOS_HandleTypeDef |
__MDMA_HandleTypeDef | MDMA handle Structure definition
__MMC_HandleTypeDef | MMC handle Structure definition
__NAND_HandleTypeDef | NAND handle Structure definition
__NOR_HandleTypeDef | NOR handle Structure definition
__OPAMP_HandleTypeDef | OPAMP Handle Structure definition
__OSPI_HandleTypeDef | HAL OSPI Handle Structure definition
__PCD_HandleTypeDef | PCD Handle Structure definition
__PSSI_HandleTypeDef | PSSI handle Structure definition
__RAMECC_HandleTypeDef | RAMECC handle Structure definition
__RNG_HandleTypeDef |
__RTC_HandleTypeDef | RTC Handle Structure definition
__SAI_HandleTypeDef |
__SD_HandleTypeDef | SD handle Structure definition
__SDRAM_HandleTypeDef | SDRAM handle Structure definition
__SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
__SMBUS_HandleTypeDef |
__SPDIFRX_HandleTypeDef | SPDIFRX handle Structure definition
__SPI_HandleTypeDef | SPI handle Structure definition
__SRAM_HandleTypeDef | SRAM handle Structure definition
__SWPMI_HandleTypeDef | SWPMI handle Structure definition
__TIM_HandleTypeDef | TIM Time Base Handle Structure definition
__UART_HandleTypeDef | UART handle Structure definition
__USART_HandleTypeDef | USART handle Structure definition
__WWDG_HandleTypeDef | WWDG handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_InitTypeDef | Structure definition of ADC instance and ADC group regular
ADC_InjectionConfigTypeDef | ADC group injected contexts queue configuration
ADC_InjectionConfTypeDef | Structure definition of ADC group injected and ADC channel affected to ADC group injected
ADC_InjOversamplingTypeDef | ADC Injected Conversion Oversampling structure definition
ADC_MultiModeTypeDef | Structure definition of ADC multimode
ADC_OversamplingTypeDef | ADC group regular oversampling structure definition
BDMA_Base_Registers |
CEC_InitTypeDef | CEC Init Structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
CRYP_ConfigTypeDef | CRYP Init Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_SampleAndHoldConfTypeDef | DAC Configuration sample and hold Channel structure definition
DCMI_CodesInitTypeDef | DCMI Embedded Synchronisation CODE Init structure definition
DCMI_InitTypeDef | DCMI Init structure definition
DFSDM_Channel_AwdTypeDef | DFSDM channel analog watchdog structure definition
DFSDM_Channel_InitTypeDef | DFSDM channel init structure definition
DFSDM_Channel_InputTypeDef | DFSDM channel input structure definition
DFSDM_Channel_OutputClockTypeDef | DFSDM channel output clock structure definition
DFSDM_Channel_SerialInterfaceTypeDef | DFSDM channel serial interface structure definition
DFSDM_Filter_AwdParamTypeDef | DFSDM filter analog watchdog parameters structure definition
DFSDM_Filter_FilterParamTypeDef | DFSDM filter parameters structure definition
DFSDM_Filter_InitTypeDef | DFSDM filter init structure definition
DFSDM_Filter_InjectedParamTypeDef | DFSDM filter injected conversion parameters structure definition
DFSDM_Filter_RegularParamTypeDef | DFSDM filter regular conversion parameters structure definition
DMA_Base_Registers |
DMA_InitTypeDef | DMA Configuration Structure definition
EXTI_ConfigTypeDef | EXTI Configuration structure definition
EXTI_HandleTypeDef | EXTI Handle structure definition
FDCAN_ClkCalUnitTypeDef | FDCAN clock calibration unit structure definition
FDCAN_ErrorCountersTypeDef | FDCAN Error Counters structure definition
FDCAN_FilterTypeDef | FDCAN filter structure definition
FDCAN_HpMsgStatusTypeDef | FDCAN High Priority Message Status structure definition
FDCAN_InitTypeDef | FDCAN Init structure definition
FDCAN_MsgRamAddressTypeDef | FDCAN Message RAM blocks
FDCAN_ProtocolStatusTypeDef | FDCAN Protocol Status structure definition
FDCAN_RxHeaderTypeDef | FDCAN Rx header structure definition
FDCAN_TriggerTypeDef | FDCAN Trigger structure definition
FDCAN_TT_ConfigTypeDef | FDCAN TT Init structure definition
FDCAN_TTOperationStatusTypeDef | FDCAN TT Operation Status structure definition
FDCAN_TxEventFifoTypeDef | FDCAN Tx event FIFO structure definition
FDCAN_TxHeaderTypeDef | FDCAN Tx header structure definition
FLASH_CRCInitTypeDef | FLASH Erase structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GFXMMU_BuffersTypeDef | GFXMMU buffers structure definition
GFXMMU_CachePrefetchTypeDef | GFXMMU cache and pre-fetch structure definition
GFXMMU_InitTypeDef | GFXMMU init structure definition
GFXMMU_InterruptsTypeDef | GFXMMU interrupts structure definition
GFXMMU_LutLineTypeDef | GFXMMU LUT line structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_DMA_MuxRequestGeneratorConfigTypeDef | HAL DMAMUX request generator parameters structure definition
HAL_DMA_MuxSyncConfigTypeDef | HAL DMAMUX Synchronization configuration structure definition
HAL_MMC_CardCIDTypeDef |
HAL_MMC_CardCSDTypeDef |
HAL_MMC_CardInfoTypeDef | MMC Card Information Structure definition
HAL_SD_CardCIDTypeDef |
HAL_SD_CardCSDTypeDef |
HAL_SD_CardInfoTypeDef | SD Card Information Structure definition
HAL_SD_CardStatusTypeDef |
HASH_InitTypeDef | HASH Configuration Structure definition
I2C_InitTypeDef |
I2S_InitTypeDef | I2S Init structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
JPEG_AC_HuffCodeTableTypeDef |
JPEG_ACHuffTableTypeDef |
JPEG_ConfTypeDef |
JPEG_DC_HuffCodeTableTypeDef |
JPEG_DCHuffTableTypeDef |
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_BDMA_InitTypeDef |
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DAC_InitTypeDef | Structure definition of some features of DAC instance
LL_DMA2D_ColorTypeDef | LL DMA2D Output Color Structure Definition
LL_DMA2D_InitTypeDef | LL DMA2D Init Structure Definition
LL_DMA2D_LayerCfgTypeDef | LL DMA2D Layer Configuration Structure Definition
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_I2S_InitTypeDef | I2S Init structure definition
LL_LPTIM_InitTypeDef | LPTIM Init structure definition
LL_LPUART_InitTypeDef | LL LPUART Init Structure definition
LL_MDMA_InitTypeDef |
LL_MDMA_LinkNodeTypeDef | LL MDMA linked list node structure definition
LL_OPAMP_InitTypeDef | Structure definition of some features of OPAMP instance
LL_PLL_ClocksTypeDef | PLL Clocks Frequency Structure
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RNG_InitTypeDef | LL RNG Init Structure Definition
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_SWPMI_InitTypeDef | SWPMI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
LTDC_ColorTypeDef | LTDC color structure definition
LTDC_InitTypeDef | LTDC Init structure definition
LTDC_LayerCfgTypeDef | LTDC Layer structure definition
MDIOS_InitTypeDef |
MDMA_InitTypeDef | MDMA Configuration Structure definition
MDMA_LinkNodeConfTypeDef | HAL MDMA linked list node configuration structure definition
MDMA_LinkNodeTypeDef | HAL MDMA linked list node structure definition
MPU_Region_InitTypeDef |
NAND_AddressTypeDef | NAND Memory address Structure definition
NAND_DeviceConfigTypeDef | NAND Memory info Structure definition
NAND_IDTypeDef | NAND Memory electronic signature Structure definition
NOR_CFITypeDef | FMC NOR CFI typedef
NOR_IDTypeDef | FMC NOR ID typedef
OPAMP_InitTypeDef | OPAMP Init structure definition
OSPI_AutoPollingTypeDef | HAL OSPI Auto Polling mode configuration structure definition
OSPI_HyperbusCfgTypeDef | HAL OSPI Hyperbus Configuration Structure definition
OSPI_HyperbusCmdTypeDef | HAL OSPI Hyperbus Command Structure definition
OSPI_InitTypeDef | OSPI Init structure definition
OSPI_MemoryMappedTypeDef | HAL OSPI Memory Mapped mode configuration structure definition
OSPI_RegularCmdTypeDef | HAL OSPI Regular Command Structure definition
OSPIM_CfgTypeDef | HAL OSPI IO Manager Configuration structure definition
PLL1_ClocksTypeDef | RCC PLL1 Clocks structure definition
PLL2_ClocksTypeDef | RCC PLL2 Clocks structure definition
PLL3_ClocksTypeDef | RCC PLL3 Clocks structure definition
PSSI_InitTypeDef | PSSI Init structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWREx_AVDTypeDef | PWREx AVD configuration structure definition
PWREx_WakeupPinTypeDef | PWREx Wakeup pin configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_CRSInitTypeDef | RCC_CRS Init structure definition
RCC_CRSSynchroInfoTypeDef | RCC_CRS Synchronization structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLL2InitTypeDef | PLL2 Clock structure definition
RCC_PLL3InitTypeDef | PLL3 Clock structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RNG_ConfigTypeDef | RNGEX Configuration Structure definition
RNG_InitTypeDef |
RTC_ActiveTampersTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_ATampInputTypeDef |
RTC_DateTypeDef | RTC Date structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_InternalTamperTypeDef |
RTC_TamperTypeDef |
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef |
SAI_InitTypeDef |
SAI_PdmInitTypeDef |
SAI_SlotInitTypeDef |
SAIEx_PdmMicDelayParamTypeDef | PDM microphone delay structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_InitTypeDef |
SPDIFRX_InitTypeDef | SPDIFRX Init structure definition
SPDIFRX_SetDataFormatTypeDef | SPDIFRX SetDataFormat structure definition
SPI_InitTypeDef | SPI Configuration Structure definition
SWPMI_InitTypeDef | SWPMI Init Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
UART_AdvFeatureInitTypeDef | UART Advanced Features initialization structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_InitTypeDef | USART Init Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | B | C | D | E | F | G | H | I | J | L | M | N | O | P | R | S | T | U | W | _
A
FDCAN_TxHeaderTypeDef LL_LPTIM_InitTypeDef PLL2_ClocksTypeDef UART_InitTypeDef
FLASH_CRCInitTypeDef LL_LPUART_InitTypeDef PLL3_ClocksTypeDef UART_WakeUpTypeDef
ADC_AnalogWDGConfTypeDef FLASH_EraseInitTypeDef LL_MDMA_InitTypeDef PSSI_InitTypeDef USART_InitTypeDef
ADC_ChannelConfTypeDef FLASH_OBProgramInitTypeDef LL_MDMA_LinkNodeTypeDef PWR_PVDTypeDef
W
ADC_InitTypeDef FLASH_ProcessTypeDef LL_OPAMP_InitTypeDef PWREx_AVDTypeDef
ADC_InjectionConfigTypeDef
G
LL_PLL_ClocksTypeDef PWREx_WakeupPinTypeDef WWDG_InitTypeDef
ADC_InjectionConfTypeDef LL_RCC_ClocksTypeDef
R
_
ADC_InjOversamplingTypeDef GFXMMU_BuffersTypeDef LL_RNG_InitTypeDef
ADC_MultiModeTypeDef GFXMMU_CachePrefetchTypeDef LL_RTC_AlarmTypeDef RCC_ClkInitTypeDef __ADC_HandleTypeDef
ADC_OversamplingTypeDef GFXMMU_InitTypeDef LL_RTC_DateTypeDef RCC_CRSInitTypeDef __CEC_HandleTypeDef
B
GFXMMU_InterruptsTypeDef LL_RTC_InitTypeDef RCC_CRSSynchroInfoTypeDef __COMP_HandleTypeDef
GFXMMU_LutLineTypeDef LL_RTC_TimeTypeDef RCC_OscInitTypeDef __CRYP_HandleTypeDef
BDMA_Base_Registers GPIO_InitTypeDef LL_SPI_InitTypeDef RCC_PeriphCLKInitTypeDef __DAC_HandleTypeDef
C
H
LL_SWPMI_InitTypeDef RCC_PLL2InitTypeDef __DCMI_HandleTypeDef
LL_TIM_BDTR_InitTypeDef RCC_PLL3InitTypeDef __DFSDM_Channel_HandleTypeDef
CEC_InitTypeDef HAL_DMA_MuxRequestGeneratorConfigTypeDef LL_TIM_ENCODER_InitTypeDef RCC_PLLInitTypeDef __DFSDM_Filter_HandleTypeDef
COMP_InitTypeDef HAL_DMA_MuxSyncConfigTypeDef LL_TIM_HALLSENSOR_InitTypeDef RNG_ConfigTypeDef __DMA_HandleTypeDef
CRC_HandleTypeDef HAL_MMC_CardCIDTypeDef LL_TIM_IC_InitTypeDef RNG_InitTypeDef __FDCAN_HandleTypeDef
CRC_InitTypeDef HAL_MMC_CardCSDTypeDef LL_TIM_InitTypeDef RTC_ActiveTampersTypeDef __GFXMMU_HandleTypeDef
CRYP_ConfigTypeDef HAL_MMC_CardInfoTypeDef LL_TIM_OC_InitTypeDef RTC_AlarmTypeDef __HASH_HandleTypeDef
D
HAL_SD_CardCIDTypeDef LL_USART_ClockInitTypeDef RTC_ATampInputTypeDef __HCD_HandleTypeDef
HAL_SD_CardCSDTypeDef LL_USART_InitTypeDef RTC_DateTypeDef __I2C_HandleTypeDef
DAC_ChannelConfTypeDef HAL_SD_CardInfoTypeDef LL_UTILS_ClkInitTypeDef RTC_InitTypeDef __I2S_HandleTypeDef
DAC_SampleAndHoldConfTypeDef HAL_SD_CardStatusTypeDef LL_UTILS_PLLInitTypeDef RTC_InternalTamperTypeDef __IRDA_HandleTypeDef
DCMI_CodesInitTypeDef HASH_InitTypeDef LPTIM_ClockConfigTypeDef RTC_TamperTypeDef __JPEG_HandleTypeDef
DCMI_InitTypeDef
I
LPTIM_InitTypeDef RTC_TimeTypeDef __LPTIM_HandleTypeDef
DFSDM_Channel_AwdTypeDef LPTIM_TriggerConfigTypeDef
S
__LTDC_HandleTypeDef
DFSDM_Channel_InitTypeDef I2C_InitTypeDef LPTIM_ULPClockConfigTypeDef __MDIOS_HandleTypeDef
DFSDM_Channel_InputTypeDef I2S_InitTypeDef LTDC_ColorTypeDef SAI_FrameInitTypeDef __MDMA_HandleTypeDef
DFSDM_Channel_OutputClockTypeDef IRDA_InitTypeDef LTDC_InitTypeDef SAI_InitTypeDef __MMC_HandleTypeDef
DFSDM_Channel_SerialInterfaceTypeDef IWDG_HandleTypeDef LTDC_LayerCfgTypeDef SAI_PdmInitTypeDef __NAND_HandleTypeDef
DFSDM_Filter_AwdParamTypeDef IWDG_InitTypeDef
M
SAI_SlotInitTypeDef __NOR_HandleTypeDef
DFSDM_Filter_FilterParamTypeDef
J
SAIEx_PdmMicDelayParamTypeDef __OPAMP_HandleTypeDef
DFSDM_Filter_InitTypeDef MDIOS_InitTypeDef SMARTCARD_AdvFeatureInitTypeDef __OSPI_HandleTypeDef
DFSDM_Filter_InjectedParamTypeDef JPEG_AC_HuffCodeTableTypeDef MDMA_InitTypeDef SMARTCARD_InitTypeDef __PCD_HandleTypeDef
DFSDM_Filter_RegularParamTypeDef JPEG_ACHuffTableTypeDef MDMA_LinkNodeConfTypeDef SMBUS_InitTypeDef __PSSI_HandleTypeDef
DMA_Base_Registers JPEG_ConfTypeDef MDMA_LinkNodeTypeDef SPDIFRX_InitTypeDef __RAMECC_HandleTypeDef
DMA_InitTypeDef JPEG_DC_HuffCodeTableTypeDef MPU_Region_InitTypeDef SPDIFRX_SetDataFormatTypeDef __RNG_HandleTypeDef
E
JPEG_DCHuffTableTypeDef
N
SPI_InitTypeDef __RTC_HandleTypeDef
L
SWPMI_InitTypeDef __SAI_HandleTypeDef
EXTI_ConfigTypeDef NAND_AddressTypeDef
T
__SD_HandleTypeDef
EXTI_HandleTypeDef LL_ADC_CommonInitTypeDef NAND_DeviceConfigTypeDef __SDRAM_HandleTypeDef
F
LL_ADC_InitTypeDef NAND_IDTypeDef TIM_Base_InitTypeDef __SMARTCARD_HandleTypeDef
LL_ADC_INJ_InitTypeDef NOR_CFITypeDef TIM_BreakDeadTimeConfigTypeDef __SMBUS_HandleTypeDef
FDCAN_ClkCalUnitTypeDef LL_ADC_REG_InitTypeDef NOR_IDTypeDef TIM_ClearInputConfigTypeDef __SPDIFRX_HandleTypeDef
FDCAN_ErrorCountersTypeDef LL_BDMA_InitTypeDef
O
TIM_ClockConfigTypeDef __SPI_HandleTypeDef
FDCAN_FilterTypeDef LL_COMP_InitTypeDef TIM_Encoder_InitTypeDef __SRAM_HandleTypeDef
FDCAN_HpMsgStatusTypeDef LL_DAC_InitTypeDef OPAMP_InitTypeDef TIM_HallSensor_InitTypeDef __SWPMI_HandleTypeDef
FDCAN_InitTypeDef LL_DMA2D_ColorTypeDef OSPI_AutoPollingTypeDef TIM_IC_InitTypeDef __TIM_HandleTypeDef
FDCAN_MsgRamAddressTypeDef LL_DMA2D_InitTypeDef OSPI_HyperbusCfgTypeDef TIM_MasterConfigTypeDef __UART_HandleTypeDef
FDCAN_ProtocolStatusTypeDef LL_DMA2D_LayerCfgTypeDef OSPI_HyperbusCmdTypeDef TIM_OC_InitTypeDef __USART_HandleTypeDef
FDCAN_RxHeaderTypeDef LL_DMA_InitTypeDef OSPI_InitTypeDef TIM_OnePulse_InitTypeDef __WWDG_HandleTypeDef
FDCAN_TriggerTypeDef LL_EXTI_InitTypeDef OSPI_MemoryMappedTypeDef TIM_SlaveConfigTypeDef
FDCAN_TT_ConfigTypeDef LL_GPIO_InitTypeDef OSPI_RegularCmdTypeDef TIMEx_BreakInputConfigTypeDef
FDCAN_TTOperationStatusTypeDef LL_I2C_InitTypeDef OSPIM_CfgTypeDef
U
FDCAN_TxEventFifoTypeDef LL_I2S_InitTypeDef
P
UART_AdvFeatureInitTypeDef
PLL1_ClocksTypeDef
A | B | C | D | E | F | G | H | I | J | L | M | N | O | P | R | S | T | U | W | _
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: C:/git/h7_topic_tinyshark_w43/Firmware/Drivers/ Directory Reference

  • Firmware
  • Drivers
Drivers Directory Reference

Directories

directory STM32H7xx_HAL_Driver
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: C:/git/h7_topic_tinyshark_w43/Firmware/Drivers/STM32H7xx_HAL_Driver/Inc/ Directory Reference

  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32h7xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32h7xx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32h7xx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32h7xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32h7xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32h7xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32h7xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32h7xx_hal_crc_ex.h [code]

Header file of CRC HAL extended module.

file | stm32h7xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32h7xx_hal_cryp_ex.h [code]

Header file of CRYP HAL Extension module.

file | stm32h7xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32h7xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32h7xx_hal_dcmi.h [code]

Header file of DCMI HAL module.

file | stm32h7xx_hal_dfsdm.h [code]

Header file of DFSDM HAL module.

file | stm32h7xx_hal_dfsdm_ex.h [code]

Header file of DFSDM HAL extended module.

file | stm32h7xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32h7xx_hal_dma2d.h [code]

Header file of DMA2D HAL module.

file | stm32h7xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32h7xx_hal_dsi.h [code]

Header file of DSI HAL module.

file | stm32h7xx_hal_dts.h [code]

Header file of DTS HAL module.

file | stm32h7xx_hal_eth.h [code]

Header file of ETH HAL module.

file | stm32h7xx_hal_eth_ex.h [code]

Header file of ETH HAL Extended module.

file | stm32h7xx_hal_exti.h [code]

Header file of EXTI HAL module.

file | stm32h7xx_hal_fdcan.h [code]

Header file of FDCAN HAL module.

file | stm32h7xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32h7xx_hal_flash_ex.h [code]

Header file of FLASH HAL module.

file | stm32h7xx_hal_gfxmmu.h [code]

Header file of GFXMMU HAL module.

file | stm32h7xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32h7xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extension module.

file | stm32h7xx_hal_hash.h [code]

Header file of HASH HAL module.

file | stm32h7xx_hal_hash_ex.h [code]

Header file of HASH HAL module.

file | stm32h7xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32h7xx_hal_hrtim.h [code]

Header file of HRTIM HAL module.

file | stm32h7xx_hal_hsem.h [code]

Header file of HSEM HAL module.

file | stm32h7xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32h7xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32h7xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32h7xx_hal_i2s_ex.h [code]

Header file of I2S HAL module.

file | stm32h7xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32h7xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32h7xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32h7xx_hal_jpeg.h [code]

Header file of JPEG HAL module.

file | stm32h7xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32h7xx_hal_ltdc.h [code]

Header file of LTDC HAL module.

file | stm32h7xx_hal_ltdc_ex.h [code]

Header file of LTDC HAL Extension module.

file | stm32h7xx_hal_mdios.h [code]

Header file of MDIOS HAL module.

file | stm32h7xx_hal_mdma.h [code]

Header file of DMA HAL module.

file | stm32h7xx_hal_mmc.h [code]

Header file of MMC HAL module.

file | stm32h7xx_hal_mmc_ex.h [code]

Header file of SD HAL extended module.

file | stm32h7xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32h7xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32h7xx_hal_opamp.h [code]

Header file of OPAMP HAL module.

file | stm32h7xx_hal_opamp_ex.h [code]

Header file of OPAMP HAL Extended module.

file | stm32h7xx_hal_ospi.h [code]

Header file of OSPI HAL module.

file | stm32h7xx_hal_otfdec.h [code]

Header file of OTFDEC HAL module.

file | stm32h7xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32h7xx_hal_pcd_ex.h [code]

Header file of PCD HAL Extension module.

file | stm32h7xx_hal_pssi.h [code]

Header file of PSSI HAL module.

file | stm32h7xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32h7xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extension module.

file | stm32h7xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32h7xx_hal_ramecc.h [code]

Header file of RAMECC HAL module.

file | stm32h7xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32h7xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32h7xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32h7xx_hal_rng_ex.h [code]

Header file of RNG HAL Extension module.

file | stm32h7xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32h7xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extension module.

file | stm32h7xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32h7xx_hal_sai_ex.h [code]

Header file of SAI HAL extended module.

file | stm32h7xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32h7xx_hal_sd_ex.h [code]

Header file of SD HAL extended module.

file | stm32h7xx_hal_sdram.h [code]

Header file of SDRAM HAL module.

file | stm32h7xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32h7xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32h7xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32h7xx_hal_spdifrx.h [code]

Header file of SPDIFRX HAL module.

file | stm32h7xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32h7xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32h7xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32h7xx_hal_swpmi.h [code]

Header file of SWPMI HAL module.

file | stm32h7xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32h7xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32h7xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32h7xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32h7xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32h7xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32h7xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32h7xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32h7xx_ll_bdma.h [code]

Header file of BDMA LL module.

file | stm32h7xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32h7xx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32h7xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32h7xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32h7xx_ll_crs.h [code]

CRS LL module driver.

file | stm32h7xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32h7xx_ll_delayblock.h [code]

Header file of Delay Block module.

file | stm32h7xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32h7xx_ll_dma2d.h [code]

Header file of DMA2D LL module.

file | stm32h7xx_ll_dmamux.h [code]

Header file of DMAMUX LL module.

file | stm32h7xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32h7xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32h7xx_ll_hrtim.h [code]

Header file of HRTIM LL module.

file | stm32h7xx_ll_hsem.h [code]

Header file of HSEM LL module.

file | stm32h7xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32h7xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32h7xx_ll_lptim.h [code]

Header file of LPTIM LL module.

file | stm32h7xx_ll_lpuart.h [code]

Header file of LPUART LL module.

file | stm32h7xx_ll_mdma.h [code]

Header file of MDMA LL module.

file | stm32h7xx_ll_opamp.h [code]

Header file of OPAMP LL module.

file | stm32h7xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32h7xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32h7xx_ll_rng.h [code]

Header file of RNG LL module.

file | stm32h7xx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32h7xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32h7xx_ll_swpmi.h [code]

Header file of SWPMI LL module.

file | stm32h7xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32h7xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32h7xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32h7xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32h7xx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: C:/git/h7_topic_tinyshark_w43/Firmware/ Directory Reference

  • Firmware
Firmware Directory Reference

Directories

directory Drivers
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: C:/git/h7_topic_tinyshark_w43/Firmware/Drivers/STM32H7xx_HAL_Driver/ Directory Reference

  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
STM32H7xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: C:/git/h7_topic_tinyshark_w43/Firmware/Drivers/STM32H7xx_HAL_Driver/Src/ Directory Reference

  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32h7xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32h7xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c".

file | stm32h7xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c".

file | stm32h7xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

file | stm32h7xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions.

file | stm32h7xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32h7xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32h7xx_hal_cryp_ex.c [code]

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

file | stm32h7xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_dac_ex.c [code]

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

file | stm32h7xx_hal_dcmi.c [code]

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_dfsdm.c [code]

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

file | stm32h7xx_hal_dfsdm_ex.c [code]

DFSDM Extended HAL module driver. This file provides firmware functions to manage the following functionality of the DFSDM Peripheral Controller: + Set and get pulses skipping on channel.

file | stm32h7xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32h7xx_hal_dma2d.c [code]

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32h7xx_hal_dsi.c [code]

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_dts.c [code]

DTS HAL module driver. This file provides firmware functions to manage the following functionalities of the DTS peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_eth.c [code]

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_eth_ex.c [code]

ETH HAL Extended module driver.

file | stm32h7xx_hal_exti.c [code]

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32h7xx_hal_fdcan.c [code]

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32h7xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

file | stm32h7xx_hal_gfxmmu.c [code]

This file provides firmware functions to manage the following functionalities of the Graphic MMU (GFXMMU) peripheral: + Initialization and De-initialization. + LUT configuration. + Force flush and/or invalidate of cache. + Modify physical buffer adresses. + Modify cache and pre-fetch parameters. + Error management.

file | stm32h7xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32h7xx_hal_hash.c [code]

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption.

file | stm32h7xx_hal_hash_ex.c [code]

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256.

file | stm32h7xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_hrtim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

file | stm32h7xx_hal_hsem.c [code]

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

file | stm32h7xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32h7xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_i2s_ex.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions.

file | stm32h7xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32h7xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32h7xx_hal_jpeg.c [code]

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions.

file | stm32h7xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32h7xx_hal_ltdc.c [code]

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_ltdc_ex.c [code]

LTDC Extension HAL module driver.

file | stm32h7xx_hal_mdios.c [code]

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_mdma.c [code]

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions.

file | stm32h7xx_hal_mmc.c [code]

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions.

file | stm32h7xx_hal_mmc_ex.c [code]

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions.

file | stm32h7xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32h7xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32h7xx_hal_opamp.c [code]

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_opamp_ex.c [code]

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32h7xx_hal_ospi.c [code]

OSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration.

file | stm32h7xx_hal_otfdec.c [code]

OTFDEC HAL module driver. This file provides firmware functions to manage the following functionalities of the On-The-Fly Decryption (OTFDEC) peripheral: + Initialization and de-initialization functions + Region setting/enable functions + Peripheral State functions.

file | stm32h7xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_pcd_ex.c [code]

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32h7xx_hal_pssi.c [code]

PSSI HAL module driver. This file provides firmware functions to manage the following functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions. + Peripheral Control functions. + Interrupt Handling functions.

file | stm32h7xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

file | stm32h7xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32h7xx_hal_ramecc.c [code]

RAMECC HAL module driver. This file provides firmware functions to manage the following functionalities of the RAM ECC monitoring (RAMECC) peripheral: + Initialization and de-initialization functions + Monitoring operation functions + Error informations functions + State and error functions.

file | stm32h7xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32h7xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_rng_ex.c [code]

Extended RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Lock configuration functions + Reset the RNG.

file | stm32h7xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32h7xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32h7xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_sai_ex.c [code]

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

file | stm32h7xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_sd_ex.c [code]

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions.

file | stm32h7xx_hal_sdram.c [code]

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

file | stm32h7xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_spdifrx.c [code]

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32h7xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32h7xx_hal_swpmi.c [code]

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32h7xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

file | stm32h7xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Timer remapping capabilities configuration.

file | stm32h7xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_usart_ex.c [code]

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

file | stm32h7xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

file | stm32h7xx_ll_adc.c [code]

ADC LL module driver.

file | stm32h7xx_ll_bdma.c [code]

BDMA LL module driver.

file | stm32h7xx_ll_comp.c [code]

COMP LL module driver.

file | stm32h7xx_ll_crc.c [code]

CRC LL module driver.

file | stm32h7xx_ll_crs.c [code]
file | stm32h7xx_ll_dac.c [code]

DAC LL module driver.

file | stm32h7xx_ll_delayblock.c [code]

DelayBlock Low Layer HAL module driver.

file | stm32h7xx_ll_dma.c [code]

DMA LL module driver.

file | stm32h7xx_ll_dma2d.c [code]

DMA2D LL module driver.

file | stm32h7xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32h7xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32h7xx_ll_hrtim.c [code]

HRTIM LL module driver.

file | stm32h7xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32h7xx_ll_lptim.c [code]

LPTIM LL module driver.

file | stm32h7xx_ll_lpuart.c [code]

LPUART LL module driver.

file | stm32h7xx_ll_mdma.c [code]

MDMA LL module driver.

file | stm32h7xx_ll_opamp.c [code]

OPAMP LL module driver.

file | stm32h7xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32h7xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32h7xx_ll_rng.c [code]

RNG LL module driver.

file | stm32h7xx_ll_rtc.c [code]

RTC LL module driver.

file | stm32h7xx_ll_spi.c [code]

SPI LL module driver.

file | stm32h7xx_ll_swpmi.c [code]

SWPMI LL module driver.

file | stm32h7xx_ll_tim.c [code]

TIM LL module driver.

file | stm32h7xx_ll_usart.c [code]

USART LL module driver.

file | stm32h7xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Firmware
    • Drivers
      • STM32H7xx_HAL_Driver
        • Inc
        • Src
Generated on Tue Nov 12 2019 18:50:44 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32h7xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32h7xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32h7xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c"
stm32h7xx_hal_adc.h [code] | Header file of ADC HAL module
stm32h7xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c"
stm32h7xx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32h7xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function
stm32h7xx_hal_cec.h [code] | Header file of CEC HAL module
stm32h7xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions
stm32h7xx_hal_comp.h [code] | Header file of COMP HAL module
stm32h7xx_hal_conf.h [code]
stm32h7xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32h7xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_crc.h [code] | Header file of CRC HAL module
stm32h7xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32h7xx_hal_crc_ex.h [code] | Header file of CRC HAL extended module
stm32h7xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32h7xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32h7xx_hal_cryp_ex.c [code] | Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions
stm32h7xx_hal_cryp_ex.h [code] | Header file of CRYP HAL Extension module
stm32h7xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_dac.h [code] | Header file of DAC HAL module
stm32h7xx_hal_dac_ex.c [code] | Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral
stm32h7xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32h7xx_hal_dcmi.c [code] | DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_dcmi.h [code] | Header file of DCMI HAL module
stm32h7xx_hal_dfsdm.c [code] | This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event
stm32h7xx_hal_dfsdm.h [code] | Header file of DFSDM HAL module
stm32h7xx_hal_dfsdm_ex.c [code] | DFSDM Extended HAL module driver. This file provides firmware functions to manage the following functionality of the DFSDM Peripheral Controller: + Set and get pulses skipping on channel
stm32h7xx_hal_dfsdm_ex.h [code] | Header file of DFSDM HAL extended module
stm32h7xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32h7xx_hal_dma.h [code] | Header file of DMA HAL module
stm32h7xx_hal_dma2d.c [code] | DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_dma2d.h [code] | Header file of DMA2D HAL module
stm32h7xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32h7xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32h7xx_hal_dsi.c [code] | DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_dsi.h [code] | Header file of DSI HAL module
stm32h7xx_hal_dts.c [code] | DTS HAL module driver. This file provides firmware functions to manage the following functionalities of the DTS peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_dts.h [code] | Header file of DTS HAL module
stm32h7xx_hal_eth.c [code] | ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_eth.h [code] | Header file of ETH HAL module
stm32h7xx_hal_eth_ex.c [code] | ETH HAL Extended module driver
stm32h7xx_hal_eth_ex.h [code] | Header file of ETH HAL Extended module
stm32h7xx_hal_exti.c [code] | EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32h7xx_hal_exti.h [code] | Header file of EXTI HAL module
stm32h7xx_hal_fdcan.c [code] | FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions
stm32h7xx_hal_fdcan.h [code] | Header file of FDCAN HAL module
stm32h7xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32h7xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32h7xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions
stm32h7xx_hal_flash_ex.h [code] | Header file of FLASH HAL module
stm32h7xx_hal_gfxmmu.c [code] | This file provides firmware functions to manage the following functionalities of the Graphic MMU (GFXMMU) peripheral: + Initialization and De-initialization. + LUT configuration. + Force flush and/or invalidate of cache. + Modify physical buffer adresses. + Modify cache and pre-fetch parameters. + Error management
stm32h7xx_hal_gfxmmu.h [code] | Header file of GFXMMU HAL module
stm32h7xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32h7xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32h7xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extension module
stm32h7xx_hal_hash.c [code] | HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption
stm32h7xx_hal_hash.h [code] | Header file of HASH HAL module
stm32h7xx_hal_hash_ex.c [code] | Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256
stm32h7xx_hal_hash_ex.h [code] | Header file of HASH HAL module
stm32h7xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32h7xx_hal_hrtim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get
stm32h7xx_hal_hrtim.h [code] | Header file of HRTIM HAL module
stm32h7xx_hal_hsem.c [code] | HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management
stm32h7xx_hal_hsem.h [code] | Header file of HSEM HAL module
stm32h7xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32h7xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32h7xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32h7xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32h7xx_hal_i2s_ex.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions
stm32h7xx_hal_i2s_ex.h [code] | Header file of I2S HAL module
stm32h7xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32h7xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32h7xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32h7xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32h7xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32h7xx_hal_jpeg.c [code] | JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions
stm32h7xx_hal_jpeg.h [code] | Header file of JPEG HAL module
stm32h7xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32h7xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32h7xx_hal_ltdc.c [code] | LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_ltdc.h [code] | Header file of LTDC HAL module
stm32h7xx_hal_ltdc_ex.c [code] | LTDC Extension HAL module driver
stm32h7xx_hal_ltdc_ex.h [code] | Header file of LTDC HAL Extension module
stm32h7xx_hal_mdios.c [code] | MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32h7xx_hal_mdios.h [code] | Header file of MDIOS HAL module
stm32h7xx_hal_mdma.c [code] | This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions
stm32h7xx_hal_mdma.h [code] | Header file of DMA HAL module
stm32h7xx_hal_mmc.c [code] | MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions
stm32h7xx_hal_mmc.h [code] | Header file of MMC HAL module
stm32h7xx_hal_mmc_ex.c [code] | MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions
stm32h7xx_hal_mmc_ex.h [code] | Header file of SD HAL extended module
stm32h7xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32h7xx_hal_nand.h [code] | Header file of NAND HAL module
stm32h7xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32h7xx_hal_nor.h [code] | Header file of NOR HAL module
stm32h7xx_hal_opamp.c [code] | OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_opamp.h [code] | Header file of OPAMP HAL module
stm32h7xx_hal_opamp_ex.c [code] | Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32h7xx_hal_opamp_ex.h [code] | Header file of OPAMP HAL Extended module
stm32h7xx_hal_ospi.c [code] | OSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration
stm32h7xx_hal_ospi.h [code] | Header file of OSPI HAL module
stm32h7xx_hal_otfdec.c [code] | OTFDEC HAL module driver. This file provides firmware functions to manage the following functionalities of the On-The-Fly Decryption (OTFDEC) peripheral: + Initialization and de-initialization functions + Region setting/enable functions + Peripheral State functions
stm32h7xx_hal_otfdec.h [code] | Header file of OTFDEC HAL module
stm32h7xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32h7xx_hal_pcd_ex.c [code] | PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32h7xx_hal_pcd_ex.h [code] | Header file of PCD HAL Extension module
stm32h7xx_hal_pssi.c [code] | PSSI HAL module driver. This file provides firmware functions to manage the following functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_pssi.h [code] | Header file of PSSI HAL module
stm32h7xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions. + Peripheral Control functions. + Interrupt Handling functions
stm32h7xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32h7xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions
stm32h7xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extension module
stm32h7xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32h7xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32h7xx_hal_ramecc.c [code] | RAMECC HAL module driver. This file provides firmware functions to manage the following functionalities of the RAM ECC monitoring (RAMECC) peripheral: + Initialization and de-initialization functions + Monitoring operation functions + Error informations functions + State and error functions
stm32h7xx_hal_ramecc.h [code] | Header file of RAMECC HAL module
stm32h7xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32h7xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32h7xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32h7xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_rng.h [code] | Header file of RNG HAL module
stm32h7xx_hal_rng_ex.c [code] | Extended RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Lock configuration functions + Reset the RNG
stm32h7xx_hal_rng_ex.h [code] | Header file of RNG HAL Extension module
stm32h7xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32h7xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32h7xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32h7xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extension module
stm32h7xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_sai.h [code] | Header file of SAI HAL module
stm32h7xx_hal_sai_ex.c [code] | SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays
stm32h7xx_hal_sai_ex.h [code] | Header file of SAI HAL extended module
stm32h7xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_sd.h [code] | Header file of SD HAL module
stm32h7xx_hal_sd_ex.c [code] | SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions
stm32h7xx_hal_sd_ex.h [code] | Header file of SD HAL extended module
stm32h7xx_hal_sdram.c [code] | SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device
stm32h7xx_hal_sdram.h [code] | Header file of SDRAM HAL module
stm32h7xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32h7xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32h7xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32h7xx_hal_spdifrx.c [code] | This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32h7xx_hal_spdifrx.h [code] | Header file of SPDIFRX HAL module
stm32h7xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_spi.h [code] | Header file of SPI HAL module
stm32h7xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions
stm32h7xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32h7xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32h7xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32h7xx_hal_swpmi.c [code] | SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32h7xx_hal_swpmi.h [code] | Header file of SWPMI HAL module
stm32h7xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration
stm32h7xx_hal_tim.h [code] | Header file of TIM HAL module
stm32h7xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Timer remapping capabilities configuration
stm32h7xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32h7xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32h7xx_hal_uart.h [code] | Header file of UART HAL module
stm32h7xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32h7xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_usart.h [code] | Header file of USART HAL module
stm32h7xx_hal_usart_ex.c [code] | Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions
stm32h7xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32h7xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions
stm32h7xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32h7xx_ll_adc.c [code] | ADC LL module driver
stm32h7xx_ll_adc.h [code] | Header file of ADC LL module
stm32h7xx_ll_bdma.c [code] | BDMA LL module driver
stm32h7xx_ll_bdma.h [code] | Header file of BDMA LL module
stm32h7xx_ll_bus.h [code] | Header file of BUS LL module
stm32h7xx_ll_comp.c [code] | COMP LL module driver
stm32h7xx_ll_comp.h [code] | Header file of COMP LL module
stm32h7xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32h7xx_ll_crc.c [code] | CRC LL module driver
stm32h7xx_ll_crc.h [code] | Header file of CRC LL module
stm32h7xx_ll_crs.c [code]
stm32h7xx_ll_crs.h [code] | CRS LL module driver
stm32h7xx_ll_dac.c [code] | DAC LL module driver
stm32h7xx_ll_dac.h [code] | Header file of DAC LL module
stm32h7xx_ll_delayblock.c [code] | DelayBlock Low Layer HAL module driver
stm32h7xx_ll_delayblock.h [code] | Header file of Delay Block module
stm32h7xx_ll_dma.c [code] | DMA LL module driver
stm32h7xx_ll_dma.h [code] | Header file of DMA LL module
stm32h7xx_ll_dma2d.c [code] | DMA2D LL module driver
stm32h7xx_ll_dma2d.h [code] | Header file of DMA2D LL module
stm32h7xx_ll_dmamux.h [code] | Header file of DMAMUX LL module
stm32h7xx_ll_exti.c [code] | EXTI LL module driver
stm32h7xx_ll_exti.h [code] | Header file of EXTI LL module
stm32h7xx_ll_gpio.c [code] | GPIO LL module driver
stm32h7xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32h7xx_ll_hrtim.c [code] | HRTIM LL module driver
stm32h7xx_ll_hrtim.h [code] | Header file of HRTIM LL module
stm32h7xx_ll_hsem.h [code] | Header file of HSEM LL module
stm32h7xx_ll_i2c.c [code] | I2C LL module driver
stm32h7xx_ll_i2c.h [code] | Header file of I2C LL module
stm32h7xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32h7xx_ll_lptim.c [code] | LPTIM LL module driver
stm32h7xx_ll_lptim.h [code] | Header file of LPTIM LL module
stm32h7xx_ll_lpuart.c [code] | LPUART LL module driver
stm32h7xx_ll_lpuart.h [code] | Header file of LPUART LL module
stm32h7xx_ll_mdma.c [code] | MDMA LL module driver
stm32h7xx_ll_mdma.h [code] | Header file of MDMA LL module
stm32h7xx_ll_opamp.c [code] | OPAMP LL module driver
stm32h7xx_ll_opamp.h [code] | Header file of OPAMP LL module
stm32h7xx_ll_pwr.c [code] | PWR LL module driver
stm32h7xx_ll_pwr.h [code] | Header file of PWR LL module
stm32h7xx_ll_rcc.c [code] | RCC LL module driver
stm32h7xx_ll_rcc.h [code] | Header file of RCC LL module
stm32h7xx_ll_rng.c [code] | RNG LL module driver
stm32h7xx_ll_rng.h [code] | Header file of RNG LL module
stm32h7xx_ll_rtc.c [code] | RTC LL module driver
stm32h7xx_ll_rtc.h [code] | Header file of RTC LL module
stm32h7xx_ll_spi.c [code] | SPI LL module driver
stm32h7xx_ll_spi.h [code] | Header file of SPI LL module
stm32h7xx_ll_swpmi.c [code] | SWPMI LL module driver
stm32h7xx_ll_swpmi.h [code] | Header file of SWPMI LL module
stm32h7xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32h7xx_ll_tim.c [code] | TIM LL module driver
stm32h7xx_ll_tim.h [code] | Header file of TIM LL module
stm32h7xx_ll_usart.c [code] | USART LL module driver
stm32h7xx_ll_usart.h [code] | Header file of USART LL module
stm32h7xx_ll_utils.c [code] | UTILS LL module driver
stm32h7xx_ll_utils.h [code] | Header file of UTILS LL module
stm32h7xx_ll_wwdg.h [code] | Header file of WWDG LL module
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STM32H7B3xQ HAL User Manual: ADC

Modules
ADC
STM32H7xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros
ADC Exported Macros

Detailed Description

ADC HAL module driver.

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STM32H7B3xQ HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

ADC Initialization and Configuration functions.

ADC Input and Output operation functions

ADC IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

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STM32H7B3xQ HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

HAL ADC macro to manage HAL ADC handle, IT and flags.
HAL ADC helper macro
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STM32H7B3xQ HAL User Manual: ADC

Modules
ADC
STM32H7xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions
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STM32H7B3xQ HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
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STM32H7B3xQ HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Clock source
ADC common - Measurement path to internal channels
ADC instance - Boost mode
ADC instance - Calibration mode for offset and linearity
ADC instance - Calibration linearity words
ADC instance - Resolution
ADC left Shift
ADC instance - Low power mode
ADC instance - Offset number
ADC instance - Offset signed saturation mode
ADC instance - Offset right shift
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - Data transfer mode of ADC conversion data
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Context queue mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Channel - Single or differential ending
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Oversampling - Oversampling scope
Oversampling - Discontinuous mode
Oversampling - Data shift
Multimode - Mode
Multimode - DMA transfer
Multimode - Delay between two sampling phases
Multimode - ADC master or slave
Definitions of ADC hardware constraints delays
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STM32H7B3xQ HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC transversal scope: oversampling
Configuration of ADC hierarchical scope: multimode
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32H7B3xQ HAL User Manual: ADCEx

Modules
ADCEx
STM32H7xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Exported Macros
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: ADC Extended Exported Constants

Modules
ADC Extended Exported Constants
ADCEx

Modules

ADC group injected trigger source
ADC group injected trigger edge (when external trigger is selected)
Channel - Single or differential ending
ADC instance - Offset number
ADC group injected - Sequencer ranks
Multimode - Mode
ADC instance - Groups
ADCx CFGR fields
ADCx SMPR1 fields
ADCx CFGR sub fields
ADC group regular - DFSDM transfer of ADC conversion data
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STM32H7B3xQ HAL User Manual: ADC Extended Exported Functions

Modules
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

ADC Extended Peripheral Control functions

ADC Extended Peripheral Control functions.

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STM32H7B3xQ HAL User Manual: ADC Extended Exported Types

Data Structures
ADC Extended Exported Types
ADCEx

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...
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STM32H7B3xQ HAL User Manual: BDMA

Modules
BDMA
STM32H7xx_LL_Driver

Modules

BDMA Private Variables
BDMA Exported Init structure
BDMA Exported Constants
BDMA_LL_Private_Macros
BDMA Exported Functions
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STM32H7B3xQ HAL User Manual: BDMA Exported Init structure

Data Structures
BDMA Exported Init structure
BDMA

Data Structures

struct LL_BDMA_InitTypeDef
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STM32H7B3xQ HAL User Manual: BDMA Exported Constants

Modules
BDMA Exported Constants
BDMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_BDMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_BDMA_ReadReg function.

IT Defines

IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
DOUBLE BUFFER MODE
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
CURRENTTARGETMEM
BDMA Exported Macros
BDMA Exported Functions
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STM32H7B3xQ HAL User Manual: BDMA Exported Functions

Modules
BDMA Exported Functions
BDMA Exported Constants | BDMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: BDMA Exported Macros

Modules
BDMA Exported Macros
BDMA Exported Constants

Modules

Common Write and read registers macros
Convert BDMAxChannely
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STM32H7B3xQ HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB3 GRP1 PERIPH
AHB1 GRP1 PERIPH
AHB2 GRP1 PERIPH
AHB4 GRP1 PERIPH
APB3 GRP1 PERIPH
APB1 GRP1 PERIPH
APB1 GRP2 PERIPH
APB2 GRP1 PERIPH
APB4 GRP1 PERIPH
CLKAM PERIPH
CKGA (AXI Clocks Gating) PERIPH
BUS Exported Functions
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STM32H7B3xQ HAL User Manual: CEC

Modules
CEC
STM32H7xx_HAL_Driver

HAL CEC module driver. More...

Modules

CEC Private Constants
CEC Private Functions
CEC Exported Functions
CEC Exported Types
CEC Exported Constants
CEC Exported Macros
CEC Private Types
CEC Private Variables
CEC Private Macros

Detailed Description

HAL CEC module driver.

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STM32H7B3xQ HAL User Manual: CEC Exported Constants

Modules
CEC Exported Constants
CEC

Modules

CEC State Code Definition
CEC Error Code
CEC Signal Free Time setting parameter
CEC Receiver Tolerance
CEC Reception Stop on Error
CEC Error Bit Generation if Bit Rise Error reported
CEC Error Bit Generation if Long Bit Period Error reported
CEC Error Bit Generation on Broadcast message
CEC Signal Free Time start option
CEC Listening mode option
CEC Device Own Address position in CEC CFGR register
CEC Initiator logical address position in message header
CEC Own Address
CEC Interrupts definition
CEC Flags definition
CEC all RX or TX errors flags
CEC all RX errors interrupts enabling flag
CEC all TX errors interrupts enabling flag
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STM32H7B3xQ HAL User Manual: CEC Exported Functions

Modules
CEC Exported Functions
CEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

CEC Transmit/Receive functions.

Peripheral Control function

CEC control functions.

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STM32H7B3xQ HAL User Manual: COMP

Modules
COMP
STM32H7xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

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STM32H7B3xQ HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Error Code
COMP Window Mode
COMP power mode
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP Output Polarity
COMP Blanking Source
COMP Output Level
COMP output to EXTI
COMP Flag
COMP Interruption Clear Flags
COMP Interrupts Definitions
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STM32H7B3xQ HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: COMP

Modules
COMP
STM32H7xx_LL_Driver

Modules

COMP Private Constants
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions
COMP_LL_Private_Macros
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STM32H7B3xQ HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
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STM32H7B3xQ HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator common modes - Window mode
Comparator modes - Power mode
Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator input - Hysteresis
Comparator output - Output polarity
Comparator output - Blanking source
Comparator output - Output level
Comparator output - Output to BKIN timer
Definitions of COMP hardware constraints delays
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STM32H7B3xQ HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of COMP hierarchical scope: common to several COMP instances
Configuration of comparator modes
Configuration of comparator inputs
Configuration of comparator output
Operation on comparator instance
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
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STM32H7B3xQ HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP Private macros to get EXTI line associated with Comparators
COMP private macros to check input parameters
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STM32H7B3xQ HAL User Manual: CORTEX

Modules
CORTEX
STM32H7xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
Cortex Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX_CPU_Identifier
CORTEX Private Macros

Detailed Description

CORTEX HAL module driver.

Generated on Tue Nov 12 2019 18:50:12 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX _SysTick clock source
MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
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STM32H7B3xQ HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

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STM32H7B3xQ HAL User Manual: Cortex Exported Types

Modules
Cortex Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

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STM32H7B3xQ HAL User Manual: CORTEX

Modules
CORTEX
STM32H7xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions
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STM32H7B3xQ HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
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STM32H7B3xQ HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
MPU
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STM32H7B3xQ HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
Cortex Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

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STM32H7B3xQ HAL User Manual: CRC

Modules
CRC
STM32H7xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC Private Macros

Detailed Description

CRC HAL module driver.

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STM32H7B3xQ HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the peripheral
CRC polynomial possible sizes actual definitions
Input Buffer Format
CRC API aliases
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STM32H7B3xQ HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: CRC

Modules
CRC
STM32H7xx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions
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STM32H7B3xQ HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
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STM32H7B3xQ HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: CRCEx

Modules
CRCEx
STM32H7xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRC Extended Exported Constants
CRC Extended Exported Macros
CRC Extended Private Macros

Detailed Description

CRC Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: CRC Extended Exported Constants

Modules
CRC Extended Exported Constants
CRCEx

Modules

Input Data Inversion Modes
Output Data Inversion Modes
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STM32H7B3xQ HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended Initialization/de-initialization functions

Extended Initialization and Configuration functions.

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STM32H7B3xQ HAL User Manual: CRS

Modules
CRS
STM32H7xx_LL_Driver

Modules

CRS Exported Constants
CRS Exported Macros
CRS Exported Functions
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STM32H7B3xQ HAL User Manual: CRS Exported Constants

Modules
CRS Exported Constants
CRS

Modules

Get Flags Defines

Flags defines which can be used with LL_CRS_ReadReg function.

IT Defines

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Synchronization Signal Divider
Synchronization Signal Source
Synchronization Signal Polarity
Frequency Error Direction
Default Values
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STM32H7B3xQ HAL User Manual: CRS Exported Functions

Modules
CRS Exported Functions
CRS

Modules

Configuration
CRS_Management
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: CRS Exported Macros

Modules
CRS Exported Macros
CRS

Modules

Common Write and read registers Macros
Exported_Macros_Calculate_Reload
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STM32H7B3xQ HAL User Manual: CRYP

Modules
CRYP
STM32H7xx_HAL_Driver

CRYP HAL module driver. More...

Modules

CRYP Exported Functions
CRYP Exported Types
HAL CRYP Callback ID enumeration definition

HAL CRYP Callback ID enumeration definition.

HAL CRYP Callback pointer definition

HAL CRYP Callback pointer definition.

CRYP Exported Constants
CRYP Exported Macros
CRYP Private Macros
CRYP Private Constants
CRYP Private Defines
CRYP Private Variables
CRYP Private Functions Prototypes
CRYP Private Functions
CRYP_Private_Functions_prototypes

Detailed Description

CRYP HAL module driver.

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STM32H7B3xQ HAL User Manual: CRYP Exported Constants

Modules
CRYP Exported Constants
CRYP

Modules

CRYP Error Definition
CRYP Data Width Unit
CRYP Algorithm Mode
CRYP Key Size
CRYP Data Type
CRYP Interrupt
CRYP Flags
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STM32H7B3xQ HAL User Manual: CRYP Exported Functions

Modules
CRYP Exported Functions
CRYP

Modules

Initialization and de-initialization functions

CRYP Initialization and Configuration functions.

Encrypt Decrypt functions

CRYP processing functions.

CRYP IRQ handler management

CRYP IRQ handler.

CRYP Private Functions
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STM32H7B3xQ HAL User Manual: CRYPEx

Modules
CRYPEx
STM32H7xx_HAL_Driver

CRYP Extension HAL module driver. More...

Modules

CRYPEx Private Types
CRYPEx Private Variables
CRYPEx Private Constants
CRYPEx Private Macros
CRYPEx Private Functions
CRYPEx Exported Functions
CRYPEx_Private_Defines

Detailed Description

CRYP Extension HAL module driver.

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STM32H7B3xQ HAL User Manual: CRYPEx Exported Functions

Modules
CRYPEx Exported Functions
CRYPEx

Modules

Extended AES processing functions

CRYPEx Extended processing functions.

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STM32H7B3xQ HAL User Manual: DAC

Modules
DAC
STM32H7xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Macros
DAC Private Functions
DAC Private Constants

Detailed Description

DAC driver modules.

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STM32H7B3xQ HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC trigger selection
DAC output buffer
DAC Channel selection
DAC data alignment
DAC flags definition
DAC IT definition
DAC ConnectOnChipPeripheral
DAC User Trimming
DAC power mode
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STM32H7B3xQ HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32H7B3xQ HAL User Manual: DAC

Modules
DAC
STM32H7xx_LL_Driver

Modules

DAC Private Constants
DAC Private Macros
DAC Exported Init structure
DAC Exported Constants
DAC Exported Macros
DAC Exported Functions
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STM32H7B3xQ HAL User Manual: DAC Exported Init structure

Data Structures
DAC Exported Init structure
DAC

Data Structures

struct LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...
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STM32H7B3xQ HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC flags

Flags defines which can be used with LL_DAC_ReadReg function.

DAC interruptions

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

DAC channels
DAC operating mode
DAC trigger source
DAC waveform automatic generation mode
DAC wave generation - Noise LFSR unmask bits
DAC wave generation - Triangle amplitude
DAC channel output mode
DAC channel output buffer
DAC channel output connection
DAC literals legacy naming
DAC channel output resolution
DAC registers compliant with specific purpose
Definitions of DAC hardware constraints delays
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STM32H7B3xQ HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Configuration of DAC channels
DMA Management
Operation on DAC channels
FLAG Management
IT management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: DAC Exported Macros

Modules
DAC Exported Macros
DAC

Modules

Common write and read registers macros
DAC helper macro
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STM32H7B3xQ HAL User Manual: DACEx

Modules
DACEx
STM32H7xx_HAL_Driver

DAC Extended HAL module driver. More...

Modules

DACEx Exported Functions
DACEx private functions

Extended private functions.

DACEx Exported Constants

HAL State structures definition.

DACEx Private Macros

Detailed Description

DAC Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

HAL State structures definition. More...

Modules

DACEx lfsrunmask triangle amplitude

Detailed Description

HAL State structures definition.

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STM32H7B3xQ HAL User Manual: DACEx Exported Functions

Modules
DACEx Exported Functions
DACEx

Modules

IO operation functions

Extended IO operation functions.

Peripheral Control functions

Extended Peripheral Control functions.

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STM32H7B3xQ HAL User Manual: DCMI Exported Constants

Modules
DCMI Exported Constants
DCMI

Modules

DCMI Error Code
DCMI Capture Mode
DCMI Synchronization Mode
DCMI PIXCK Polarity
DCMI VSYNC Polarity
DCMI HSYNC Polarity
DCMI MODE JPEG
DCMI Capture Rate
DCMI Extended Data Mode
DCMI Window Coordinate
DCMI Window Height
DCMI interrupt sources
DCMI Flags
DCMI Byte Select Mode
DCMI Byte Select Start
DCMI Line Select Mode
DCMI Line Select Start
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STM32H7B3xQ HAL User Manual: DCMI Exported Functions

Modules
DCMI Exported Functions
DCMI

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

DCMI Private Functions
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STM32H7B3xQ HAL User Manual: Delay Block Low Layer Exported Functions

Modules
Delay Block Low Layer Exported Functions
DELAYBLOCK_LL

Modules

Initialization de-initialization functions

Initialization and Configuration functions.

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STM32H7B3xQ HAL User Manual: DFSDM

Modules
DFSDM
STM32H7xx_HAL_Driver

DFSDM HAL driver module. More...

Modules

DFSDM Private Define
DFSDM Private Variables
DFSDM Private Functions
DFSDM Exported Functions
DFSDM Exported Types
DFSDM Exported Constants
DFSDM Exported Macros
DFSDM Private Macros

Detailed Description

DFSDM HAL driver module.

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STM32H7B3xQ HAL User Manual: DFSDM Exported Constants

Modules
DFSDM Exported Constants
DFSDM

Modules

DFSDM channel output clock selection
DFSDM channel input multiplexer
DFSDM channel input data packing
DFSDM channel input pins
DFSDM channel serial interface type
DFSDM channel SPI clock selection
DFSDM channel analog watchdog filter order
DFSDM filter conversion trigger
DFSDM filter external trigger
DFSDM filter external trigger edge
DFSDM filter sinc order
DFSDM filter analog watchdog data source
DFSDM filter error code
DFSDM break signals
DFSDM Channel Selection
DFSDM Continuous Mode
DFSDM analog watchdog threshold
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STM32H7B3xQ HAL User Manual: DFSDM Exported Functions

Modules
DFSDM Exported Functions
DFSDM

Modules

Channel initialization and de-initialization functions

Channel initialization and de-initialization functions.

Channel operation functions

Channel operation functions.

Channel state function

Channel state function.

Filter initialization and de-initialization functions

Filter initialization and de-initialization functions.

Filter control functions

Filter control functions.

Filter operation functions

Filter operation functions.

Filter state functions

Filter state functions.

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STM32H7B3xQ HAL User Manual: DFSDMEx

Modules
DFSDMEx
STM32H7xx_HAL_Driver

DFSDM Extended HAL module driver. More...

Modules

DFSDM Extended Exported Functions
DFSDM Extended Private Macros

Detailed Description

DFSDM Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: DFSDM Extended Exported Functions

Modules
DFSDM Extended Exported Functions
DFSDMEx

Modules

Extended channel operation functions

DFSDM extended channel operation functions.

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STM32H7B3xQ HAL User Manual: DMA

Data Structures | Modules
DMA
STM32H7xx_HAL_Driver

DMA HAL module driver. More...

Data Structures

struct | DMA_Base_Registers
struct | BDMA_Base_Registers

Modules

DMA Exported Types

DMA Exported Types.

DMA Exported Constants

DMA Exported constants.

DMA Exported Macros
DMA Exported Functions

DMA Exported functions.

DMA Private Constants

DMA private defines and constants.

DMA Private Macros

DMA private macros.

DMA Private Functions

DMA private functions.

Detailed Description

DMA HAL module driver.

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STM32H7B3xQ HAL User Manual: DMA2D

Modules
DMA2D
STM32H7xx_HAL_Driver

DMA2D HAL module driver. More...

Modules

DMA2D Private Constants
DMA2D Exported Functions
DMA2D Private Functions

Detailed Description

DMA2D HAL module driver.

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STM32H7B3xQ HAL User Manual: DMA2D Exported Functions

Modules
DMA2D Exported Functions
DMA2D

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Error functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: DMA2D

Modules
DMA2D
STM32H7xx_LL_Driver

Modules

DMA2D Private Macros
DMA2D Exported Init structures
DMA2D Exported Constants
DMA2D Exported Macros
DMA2D Exported Functions
DMA2D Private Constants
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STM32H7B3xQ HAL User Manual: DMA2D Exported Init structures

Data Structures
DMA2D Exported Init structures
DMA2D

Data Structures

struct | LL_DMA2D_InitTypeDef
LL DMA2D Init Structure Definition. More...
struct | LL_DMA2D_LayerCfgTypeDef
LL DMA2D Layer Configuration Structure Definition. More...
struct | LL_DMA2D_ColorTypeDef
LL DMA2D Output Color Structure Definition. More...
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STM32H7B3xQ HAL User Manual: DMA2D Exported Constants

Modules
DMA2D Exported Constants
DMA2D

Modules

Get Flags Defines

Flags defines which can be used with LL_DMA2D_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions.

Mode
Output Color Mode
Input Color Mode
Alpha Mode
Swap Mode
Red Blue Swap
Alpha Inversion
Line Offset Mode
CLUT Color Mode
Chroma Sub Sampling
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STM32H7B3xQ HAL User Manual: DMA2D Exported Functions

Modules
DMA2D Exported Functions
DMA2D

Modules

Configuration Functions
Flag Management
Interruption Management
Initialization and De-initialization Functions
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STM32H7B3xQ HAL User Manual: DMA2D Exported Macros

Modules
DMA2D Exported Macros
DMA2D

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: DMA2D Private Constants

Modules
DMA2D Private Constants
DMA2D

Modules

DMA2D Time Out
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STM32H7B3xQ HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

DMA Exported constants. More...

Modules

DMA Error Code

DMA Error Code.

DMA Request selection

DMA Request selection.

DMA Data transfer direction

DMA data transfer direction.

DMA Peripheral incremented mode

DMA peripheral incremented mode.

DMA Memory incremented mode

DMA memory incremented mode.

DMA Peripheral data size

DMA peripheral data size.

DMA Memory data size

DMA memory data size.

DMA mode

DMA mode.

DMA Priority level

DMA priority levels.

DMA FIFO direct mode

DMA FIFO direct mode.

DMA FIFO threshold level

DMA FIFO level.

DMA Memory burst

DMA memory burst.

DMA Peripheral burst

DMA peripheral burst.

DMA interrupt enable definitions

DMA interrupts definition.

DMA flag definitions

DMA flag definitions.

BDMA flag definitions

BDMA flag definitions.

Detailed Description

DMA Exported constants.

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STM32H7B3xQ HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

DMA Exported functions. More...

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

Detailed Description

DMA Exported functions.

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STM32H7B3xQ HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
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STM32H7B3xQ HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

STREAM
DIRECTION
MODE
DOUBLE BUFFER MODE
PERIPH
MEMORY
PDATAALIGN
MDATAALIGN
OFFSETSIZE
PRIORITY
MBURST
PBURST
DMA_LL_FIFOMODE
FIFOSTATUS 0
FIFOTHRESHOLD
CURRENTTARGETMEM
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STM32H7B3xQ HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxStreamy
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STM32H7B3xQ HAL User Manual: DMAEx

Modules
DMAEx
STM32H7xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Types

DMAEx Exported types.

DMA Exported Constants

DMAEx Exported constants.

DMAEx Exported Functions

DMAEx Exported functions.

DMA Private Macros

DMAEx private macros.

DMAEx Private Functions

DMAEx Private functions.

Detailed Description

DMA Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMAEx

DMAEx Exported constants. More...

Modules

DMAEx MUX SyncSignalID selection

DMAEx MUX SyncSignalID selection.

DMAEx MUX SyncPolarity selection

DMAEx MUX SyncPolarity selection.

DMAEx MUX SignalGeneratorID selection

DMAEx MUX SignalGeneratorID selection.

DMAEx MUX RequestGeneneratorPolarity selection

DMAEx MUX RequestGeneneratorPolarity selection.

Detailed Description

DMAEx Exported constants.

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STM32H7B3xQ HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

DMAEx Exported functions. More...

Modules

Extended features functions

Extended features functions.

Detailed Description

DMAEx Exported functions.

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STM32H7B3xQ HAL User Manual: DMAMUX

Modules
DMAMUX
STM32H7xx_LL_Driver

Modules

DMAMUX Private Constants
DMAMUX Exported Constants
DMAMUX Exported Macros
DMAMUX Exported Functions
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STM32H7B3xQ HAL User Manual: DMAMUX Exported Constants

Modules
DMAMUX Exported Constants
DMAMUX

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMAMUX_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

DMAMUX Request selection

DMA Request selection.

DMAMUX Channel
Synchronization Signal Polarity
Synchronization Signal Event
Request Generator Channel
External Request Signal Generation Polarity
External Request Signal Generation
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STM32H7B3xQ HAL User Manual: DMAMUX Exported Functions

Modules
DMAMUX Exported Functions
DMAMUX

Modules

Configuration
FLAG_Management
IT_Management
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STM32H7B3xQ HAL User Manual: DMAMUX Exported Macros

Modules
DMAMUX Exported Macros
DMAMUX

Modules

Common Write and read registers macros
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STM32H7B3xQ HAL User Manual: DTS

Modules
DTS
STM32H7xx_HAL_Driver

DTS HAL module driver. More...

Modules

DTS_Private_Constants

Detailed Description

DTS HAL module driver.

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STM32H7B3xQ HAL User Manual: DTS Exported Functions

Modules
DTS Exported Functions
DTS_Private_Constants

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: EXTI

Modules
EXTI
STM32H7xx_HAL_Driver

EXTI HAL module driver. More...

Modules

EXTI Private Constants
EXTI Exported Types
EXTI Exported Constants
EXTI Exported Macros
EXTI Private Macros
EXTI Exported Functions

EXTI Exported Functions.

Detailed Description

EXTI HAL module driver.

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STM32H7B3xQ HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

EXTI Line
EXTI Mode
EXTI Trigger
EXTI GPIOSel
EXTI PendClear Source
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STM32H7B3xQ HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

EXTI Exported Functions. More...

Modules

Configuration functions

Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

EXTI Exported Functions.

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STM32H7B3xQ HAL User Manual: EXTI

Modules
EXTI
STM32H7xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions
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STM32H7B3xQ HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
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STM32H7B3xQ HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
D3 Pend Clear Source
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STM32H7B3xQ HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions

,

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STM32H7B3xQ HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: FDCAN Exported Constants

Modules
FDCAN Exported Constants
FDCAN

Modules

HAL FDCAN Error Code
FDCAN Frame Format
FDCAN Operating Mode
FDCAN Clock Calibration
FDCAN Clock Divider
FDCAN Calibration Field Length
FDCAN Calibration State
FDCAN Calibration Counter
FDCAN Data Field Size
FDCAN Tx FIFO/Queue Mode
FDCAN ID Type
FDCAN Frame Type
FDCAN Data Length Code
FDCAN Error State Indicator
FDCAN Bit Rate Switching
FDCAN format
FDCAN Event FIFO control
FDCAN Filter Type
FDCAN Filter Configuration
FDCAN Tx Location
FDCAN Rx Location
FDCAN Event Type
FDCAN High Priority Message Storage
FDCAN protocol error code
FDCAN communication state
FDCAN FIFO watermark
FDCAN FIFO operation mode
FDCAN non-matching frames
FDCAN reject remote frames
FDCAN interrupt line
FDCAN timestamp
FDCAN timestamp prescaler
FDCAN timeout operation
FDCAN TT reference message payload
FDCAN TT repeat factor
FDCAN TT trigger type
FDCAN TT time mark event internal
FDCAN TT time mark event external
FDCAN Operation Mode
FDCAN TT Operation
FDCAN TT Time Master
FDCAN TT External Clock Synchronization
FDCAN TT Global Time Filtering
FDCAN TT Automatic Clock Calibration
FDCAN TT Event Trigger Polarity
FDCAN TT Basic Cycle Number
FDCAN TT Cycle Start Sync
FDCAN TT Stop Watch Trigger Selection
FDCAN TT Event Trigger Selection
FDCAN TT Stop Watch Source
FDCAN TT Stop Watch Polarity
FDCAN TT Time Mark Source
FDCAN TT Error Level
FDCAN TT Master State
FDCAN TT Synchronization State
Interrupt masks
FDCAN Flags
FDCAN Interrupts
FDCAN TT Flags
FDCAN TT Interrupts
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STM32H7B3xQ HAL User Manual: FDCAN Exported Functions

Modules
FDCAN Exported Functions
FDCAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Configuration functions

FDCAN Configuration functions.

Control functions

Control functions.

TT Configuration and control functions

TT Configuration and control functions.

Interrupts management

Interrupts management.

Callback functions

FDCAN Callback functions.

Peripheral State functions

FDCAN Peripheral State functions.

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STM32H7B3xQ HAL User Manual: FDCAN Interrupts

Modules
FDCAN Interrupts
FDCAN Exported Constants

Modules

FDCAN Tx Interrupts
FDCAN Rx Interrupts
FDCAN Counter Interrupts
Clock Calibration Interrupts
FDCAN Tx Event FIFO Interrupts
FDCAN Rx FIFO 0 Interrupts
FDCAN Rx FIFO 1 Interrupts
FDCAN Error Interrupts
FDCAN Error Status Interrupts
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STM32H7B3xQ HAL User Manual: FDCAN TT Interrupts

Modules
FDCAN TT Interrupts
FDCAN Exported Constants

Modules

FDCAN TT Schedule Synchronization Interrupts
FDCAN TT Time Mark Interrupts
FDCAN TT Stop Watch Interrupt
FDCAN TT Global Time Interrupts
FDCAN TT Disturbing Error Interrupts
FDCAN TT Fatal Error Interrupts
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STM32H7B3xQ HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Code

FLASH Error Code.

FLASH Type Program
FLASH Flag definition

Flag definition.

FLASH Interrupt definition

FLASH Interrupt definition.

FLASH Keys
FLASH Sectors
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STM32H7B3xQ HAL User Manual: FLASH Exported functions

Modules
FLASH Exported functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

Management functions.

Peripheral State and Errors functions

Peripheral Errors functions.

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STM32H7B3xQ HAL User Manual: FLASHEx Exported Functions

Modules
FLASHEx Exported Functions
FLASHEx | FLASH Exported Constants

Modules

Extended IO operation functions

Extended IO operation functions.

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STM32H7B3xQ HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_CRCInitTypeDef
FLASH Erase structure definition. More...
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STM32H7B3xQ HAL User Manual: FLASHEx Private Macros

Modules
FLASHEx Private Macros
FLASH Exported Constants

Modules

FLASHEx Private macros to check input parameters
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STM32H7B3xQ HAL User Manual: GFXMMU Exported Constants

Modules
GFXMMU Exported Constants
GFXMMU

Modules

GFXMMU blocks per line
GFXMMU cache lock
GFXMMU cache lock buffer
GFXMMU cache force
GFXMMU outter bufferability
GFXMMU outter cachability
GFXMMU pre-fetch
GFXMMU interrupts
GFXMMU Error Code
GFXMMU LUT line status
GFXMMU cache force parameter
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STM32H7B3xQ HAL User Manual: GFXMMU Exported Functions

Modules
GFXMMU Exported Functions
GFXMMU

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Operations functions

GFXMMU operation functions.

State functions

GFXMMU state functions.

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STM32H7B3xQ HAL User Manual: GPIO

Modules
GPIO
STM32H7xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions

Detailed Description

GPIO HAL module driver.

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STM32H7B3xQ HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins define
GPIO mode define

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed define

GPIO Output Maximum frequency.

GPIO pull define

GPIO Pull-Up or Pull-Down Activation.

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STM32H7B3xQ HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read, Write, Toggle, Lock and EXTI management functions.

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STM32H7B3xQ HAL User Manual: GPIO

Modules
GPIO
STM32H7xx_LL_Driver

Modules

GPIO Private Macros
GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
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STM32H7B3xQ HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32H7B3xQ HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: GPIOEx

Modules
GPIOEx
STM32H7xx_HAL_Driver

Modules

GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIOEx

Modules

GPIO Alternate Function Selection
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STM32H7B3xQ HAL User Manual: GPIO Private Macros

Modules
GPIO Private Macros
GPIOEx

Modules

GPIO Get Port Index
GPIO Check Alternate Function
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STM32H7B3xQ HAL User Manual: HAL Private Functions

Modules
HAL Private Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HASH

Modules
HASH
STM32H7xx_HAL_Driver

HASH HAL module driver. More...

Modules

HASH Private Constants
HASH Private Functions
HASH Exported Functions
HASH Exported Types
HASH Exported Constants
HASH Exported Macros
HASH Private Macros

Detailed Description

HASH HAL module driver.

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STM32H7B3xQ HAL User Manual: HASH Exported Constants

Modules
HASH Exported Constants
HASH

Modules

HASH algorithm selection
HASH algorithm mode
HASH input data type
HMAC key length type
HASH flags definitions
HASH interrupts definitions
HASH API alias
HASH Error Definition
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STM32H7B3xQ HAL User Manual: HASH Exported Functions

Modules
HASH Exported Functions
HASH

Modules

Initialization and de-initialization functions

Initialization, configuration and call-back functions.

HASH processing functions in polling mode

HASH processing functions using polling mode.

HASH processing functions in interrupt mode

HASH processing functions using interrupt mode.

HASH processing functions in DMA mode

HASH processing functions using DMA mode.

HMAC processing functions in polling mode

HMAC processing functions using polling mode.

HMAC processing functions in interrupt mode

HMAC processing functions using interrupt mode.

HMAC processing functions in DMA mode

HMAC processing functions using DMA modes.

Peripheral states functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: HASH Private Constants

Modules
HASH Private Constants
HASH

Modules

HASH Digest Calculation Status
HASH Number of Context Swap Registers
HASH TimeOut Value
HASH DMA suspension words limit
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STM32H7B3xQ HAL User Manual: HASHEx

Modules
HASHEx
STM32H7xx_HAL_Driver

HASH HAL extended module driver. More...

Modules

HASH Extended Exported Functions

Detailed Description

HASH HAL extended module driver.

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STM32H7B3xQ HAL User Manual: HASH Extended Exported Functions

Modules
HASH Extended Exported Functions
HASHEx

Modules

HASH extended processing functions in polling mode

HASH extended processing functions using polling mode.

HASH extended processing functions in interrupt mode

HASH extended processing functions using interrupt mode.

HASH extended processing functions in DMA mode

HASH extended processing functions using DMA mode.

HMAC extended processing functions in polling mode

HMAC extended processing functions using polling mode.

HMAC extended processing functions in interrupt mode

HMAC extended processing functions using interruption mode.

HMAC extended processing functions in DMA mode

HMAC extended processing functions using DMA mode.

Multi-buffer HMAC extended processing functions in DMA mode

HMAC extended processing functions in multi-buffer DMA mode.

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STM32H7B3xQ HAL User Manual: HCD

Modules
HCD
STM32H7xx_HAL_Driver

HCD HAL module driver. More...

Modules

HCD Private Functions
HCD Exported Functions
HCD Exported Types
HCD Exported Constants
HCD Exported Macros

macros to handle interrupts and specific clock configurations

HCD Private Macros
HCD Private Functions Prototypes

Detailed Description

HCD HAL module driver.

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STM32H7B3xQ HAL User Manual: HCD Exported Constants

Modules
HCD Exported Constants
HCD

Modules

HCD Speed
HCD PHY Module
HCD Error Code definition

HCD Error Code definition.

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STM32H7B3xQ HAL User Manual: HCD Exported Functions

Modules
HCD Exported Functions
HCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

HCD IO operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: HCD Exported Types

Modules
HCD Exported Types
HCD

Modules

HCD State Structure definition
HCD Handle Structure definition
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STM32H7B3xQ HAL User Manual: HSEM

Modules
HSEM
STM32H7xx_HAL_Driver

HSEM HAL module driver. More...

Modules

HSEM Exported Functions
HSEM Exported Macros
HSEM Private Macros

Detailed Description

HSEM HAL module driver.

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STM32H7B3xQ HAL User Manual: HSEM Exported Functions

Modules
HSEM Exported Functions
HSEM

Modules

Take and Release functions

HSEM Take and Release functions.

HSEM Set and Get Key functions

HSEM Set and Get Key functions.

HSEM IRQ handler management

HSEM Notification functions.

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STM32H7B3xQ HAL User Manual: HSEM

Modules
HSEM
STM32H7xx_LL_Driver

Modules

HSEM Exported Constants
HSEM Exported Macros
HSEM Exported Functions
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STM32H7B3xQ HAL User Manual: HSEM Exported Constants

Modules
HSEM Exported Constants
HSEM

Modules

COREID Defines
Get Flags Defines

Flags defines which can be used with LL_HSEM_ReadReg function.

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STM32H7B3xQ HAL User Manual: HSEM Exported Functions

Modules
HSEM Exported Functions
HSEM

Modules

Data_Management
IT_Management
FLAG_Management
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STM32H7B3xQ HAL User Manual: HSEM Exported Macros

Modules
HSEM Exported Macros
HSEM

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: I2C

Modules
I2C
STM32H7xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Detailed Description

I2C HAL module driver.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction Master Point of View
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32H7B3xQ HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

Generated on Tue Nov 12 2019 18:50:16 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C

Modules
I2C
STM32H7xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions
Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
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STM32H7B3xQ HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
Generated on Tue Nov 12 2019 18:50:31 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
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STM32H7B3xQ HAL User Manual: I2CEx

Modules
I2CEx
STM32H7xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants

Detailed Description

I2C Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Extended features functions

Extended features functions.

Generated on Tue Nov 12 2019 18:50:17 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error
I2S Mode
I2S Standard
I2S Data Format
I2S MCLK Output
I2S Audio Frequency
I2S FullDuplex Mode
I2S MSB LSB Transmission
I2S Word Select Inversion
Data Padding 24Bit
Keep IO State
I2S Interrupts Definition
I2S Flags Definition
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STM32H7B3xQ HAL User Manual: I2S

Modules
I2S
SPI | STM32H7xx_LL_Driver

Modules

I2S Private Constants
I2S Private Macros
I2S Exported Init structure
I2S Exported Constants
I2S Exported Macros
I2S Exported Functions
Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: I2S Exported Init structure

Data Structures
I2S Exported Init structure
I2S

Data Structures

struct LL_I2S_InitTypeDef
I2S Init structure definition. More...
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STM32H7B3xQ HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

Data Format
Type of Channel Length
Clock Polarity
I2S Standard
Operation Mode
Prescaler Factor
FIFO Threshold Level
Transmission Bit Order
MCLK Output
Audio Frequency
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STM32H7B3xQ HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Configuration
FLAG_Management
IT_Management
DMA_Management
DATA_Management
Initialization and de-initialization functions
I2S_LL_EF_Init
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STM32H7B3xQ HAL User Manual: I2S Exported Macros

Modules
I2S Exported Macros
I2S

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: IRDA

Modules
IRDA
STM32H7xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Private Macros
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros

Detailed Description

HAL IRDA module driver.

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STM32H7B3xQ HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA State Code Definition
IRDA Error Code Definition
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA Clock Prescaler
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32H7B3xQ HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

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STM32H7B3xQ HAL User Manual: IRDAEx

Modules
IRDAEx
STM32H7xx_HAL_Driver

IRDA Extended HAL module driver. More...

Modules

IRDAEx Extended Exported Constants
IRDAEx Private Macros

Detailed Description

IRDA Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: IRDAEx Extended Exported Constants

Modules
IRDAEx Extended Exported Constants
IRDAEx

Modules

IRDAEx Word Length
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STM32H7B3xQ HAL User Manual: IWDG

Modules
IWDG
STM32H7xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

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STM32H7B3xQ HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32H7B3xQ HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

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STM32H7B3xQ HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32H7B3xQ HAL User Manual: IWDG

Modules
IWDG
STM32H7xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
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STM32H7B3xQ HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
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STM32H7B3xQ HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
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STM32H7B3xQ HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: JPEG

Modules
JPEG
STM32H7xx_HAL_Driver

JPEG HAL module driver. More...

Modules

JPEG Exported Functions
JPEG Exported Types
JPEG Exported Constants
JPEG Exported Macros
JPEG Private Types
JPEG Private Defines
JPEG Private Variables
JPEG Private Constants
JPEG Private Macros
JPEG Private Functions Prototypes
JPEG Private Functions

Detailed Description

JPEG HAL module driver.

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STM32H7B3xQ HAL User Manual: JPEG Configuration for encoding Structure definition

Data Structures
JPEG Configuration for encoding Structure definition
JPEG Exported Types

JPEG encoding configuration Structure definition. More...

Data Structures

struct JPEG_ConfTypeDef

Detailed Description

JPEG encoding configuration Structure definition.

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STM32H7B3xQ HAL User Manual: JPEG Exported Constants

Modules
JPEG Exported Constants
JPEG

Modules

JPEG Error Code definition

JPEG Error Code definition.

JPEG Quantization Table Size

JPEG Quantization Table Size.

JPEG ColorSpace

JPEG Color Space.

JPEG Chrominance Sampling

JPEG Chrominance Sampling.

JPEG Image Quality

JPEG Min and Max Image Quality.

JPEG Interrupt configuration definition

JPEG Interrupt definition.

JPEG Flag definition

JPEG Flags definition.

JPEG Process Pause Resume definition

JPEG process pause, resume definition.

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STM32H7B3xQ HAL User Manual: JPEG Exported Functions

Modules
JPEG Exported Functions
JPEG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Configuration functions

JPEG Configuration functions.

encoding/decoding processing functions

processing functions.

JPEG Decode/Encode callback functions

JPEG process callback functions.

JPEG IRQ handler management

JPEG IRQ handler.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: JPEG Exported Types

Modules
JPEG Exported Types
JPEG

Modules

JPEG Configuration for encoding Structure definition

JPEG encoding configuration Structure definition.

HAL JPEG state structure definition

HAL JPEG State structure definition.

JPEG handle Structure definition

JPEG handle Structure definition.

HAL JPEG Callback ID enumeration definition

HAL JPEG Callback ID enumeration definition.

HAL JPEG Callback pointer definition

HAL JPEG Callback pointer definition.

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STM32H7B3xQ HAL User Manual: JPEG Private Types

Data Structures
JPEG Private Types
JPEG

Data Structures

struct | JPEG_ACHuffTableTypeDef
struct | JPEG_DCHuffTableTypeDef
struct | JPEG_AC_HuffCodeTableTypeDef
struct | JPEG_DC_HuffCodeTableTypeDef
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STM32H7B3xQ HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
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STM32H7B3xQ HAL User Manual: LPTIM

Modules
LPTIM
STM32H7xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Private Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros

Detailed Description

LPTIM HAL module driver.

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STM32H7B3xQ HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
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STM32H7B3xQ HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: LPTIM

Modules
LPTIM
STM32H7xx_LL_Driver

Modules

LPTIM Private Functions
LPTIM Private Macros
LPTIM Exported Init structure
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Exported Functions
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STM32H7B3xQ HAL User Manual: LPTIM Exported Init structure

Data Structures
LPTIM Exported Init structure
LPTIM

Data Structures

struct LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...
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STM32H7B3xQ HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

Get Flags Defines

Flags defines which can be used with LL_LPTIM_ReadReg function.

IT Defines

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Operating Mode
Update Mode
Counter Mode
Output Waveform Type
Output Polarity
Prescaler Value
Trigger Source
Trigger Filter
Trigger Polarity
Clock Source
Clock Filter
Clock Polarity
Encoder Mode
Input1 Source
Input2 Source
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STM32H7B3xQ HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialisation and deinitialisation functions
LPTIM Configuration
Trigger Configuration
Clock Configuration
Encoder Mode
FLAG Management
Interrupt Management
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STM32H7B3xQ HAL User Manual: LPTIM Exported Macros

Modules
LPTIM Exported Macros
LPTIM

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: LPUART

Modules
LPUART
STM32H7xx_LL_Driver

Modules

LPUART Private Variables
LPUART Private Constants
LPUART Private Macros
LPUART Exported Init structures
LPUART Exported Constants
LPUART Exported Macros
LPUART Exported Functions
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STM32H7B3xQ HAL User Manual: LPUART Exported Init structures

Data Structures
LPUART Exported Init structures
LPUART

Data Structures

struct LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...
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STM32H7B3xQ HAL User Manual: LPUART Exported Constants

Modules
LPUART Exported Constants
LPUART

Modules

Clear Flags Defines

Flags defines which can be used with LL_LPUART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_LPUART_ReadReg function.

IT Defines

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

FIFO Threshold
Direction
Parity Control
Wakeup
Datawidth
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Address Length Detection
Hardware Control
Wakeup Activation
Driver Enable Polarity
DMA Register Data
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STM32H7B3xQ HAL User Manual: LPUART Exported Functions

Modules
LPUART Exported Functions
LPUART

Modules

Configuration functions
Configuration functions related to Half Duplex feature
Configuration functions related to Driver Enable feature
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: LPUART Exported Macros

Modules
LPUART Exported Macros
LPUART

Modules

Common Write and read registers Macros
Helper Macros
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STM32H7B3xQ HAL User Manual: LTDC

Modules
LTDC
STM32H7xx_HAL_Driver

LTDC HAL module driver. More...

Modules

LTDC Exported Functions
LTDC Private Functions
LTDC Exported Types
LTDC Exported Constants
LTDC Exported Macros
LTDC Private Macros

Detailed Description

LTDC HAL module driver.

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STM32H7B3xQ HAL User Manual: LTDC Exported Constants

Modules
LTDC Exported Constants
LTDC

Modules

LTDC Error Code
LTDC Layer
LTDC HS POLARITY
LTDC VS POLARITY
LTDC DE POLARITY
LTDC PC POLARITY
LTDC SYNC
LTDC BACK COLOR
LTDC Blending Factor1
LTDC Blending Factor2
LTDC Pixel format
LTDC Alpha
LTDC LAYER Config
LTDC Interrupts
LTDC Flags
LTDC Reload Type
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STM32H7B3xQ HAL User Manual: LTDC Exported Functions

Modules
LTDC Exported Functions
LTDC

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32H7B3xQ HAL User Manual: MDIOS Exported Constants

Modules
MDIOS Exported Constants
MDIOS

Modules

MDIOS Preamble Check
MDIOS Input Output Registers Definitions
MDIOS Registers Flags
Interrupt Sources
MDIOS Interrupt Flags
MDIOS Error Code
MDIOS Wakeup Line
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STM32H7B3xQ HAL User Manual: MDIOS Exported Functions

Modules
MDIOS Exported Functions
MDIOS

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

MDIOS Read/Write functions.

Peripheral Control functions

MDIOS control functions.

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STM32H7B3xQ HAL User Manual: MDIOS Init Structure definition

Data Structures
MDIOS Init Structure definition
MDIOS Exported Types

Data Structures

struct MDIOS_InitTypeDef
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STM32H7B3xQ HAL User Manual: MDMA

Modules
MDMA
STM32H7xx_HAL_Driver

MDMA HAL module driver. More...

Modules

MDMA Exported Types

MDMA Exported Types.

MDMA Exported Constants

MDMA Exported constants.

MDMA Exported Macros
MDMA Exported Functions
MDMA Private Types
MDMA Private Defines
MDMA Private Variables
MDMA Private Constants
MDMA Private Macros
MDMA Private Functions Prototypes
MDMA Private Functions

Detailed Description

MDMA HAL module driver.

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STM32H7B3xQ HAL User Manual: MDMA Exported Constants

Modules
MDMA Exported Constants
MDMA

MDMA Exported constants. More...

Modules

MDMA Error Codes

MDMA Error Codes.

MDMA Request selection

MDMA_Request_selection.

MDMA Transfer Trigger Mode

MDMA Transfer Trigger Mode.

MDMA Priority level

MDMA Priority level.

MDMA Endianness

MDMA Endianness.

MDMA Source increment mode

MDMA Source increment mode.

MDMA Destination increment mode

MDMA Destination increment mode.

MDMA Source data size

MDMA Source data size.

MDMA Destination data size

MDMA Destination data size.

MDMA data alignment

MDMA data alignment.

MDMA Source burst

MDMA Source burst.

MDMA Destination burst

MDMA Destination burst.

MDMA interrupt enable definitions

MDMA interrupt enable definitions.

MDMA flag definitions

MDMA flag definitions.

Detailed Description

MDMA Exported constants.

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STM32H7B3xQ HAL User Manual: MDMA Exported Functions

Modules
MDMA Exported Functions
MDMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Linked List operation functions

Linked list operation functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: MDMA

Modules
MDMA
STM32H7xx_LL_Driver

Modules

MDMA Private Variables
MDMA Private Constants
MDMA Exported Init structure
MDMA Exported Constants
MDMA Exported Macros
MDMA Exported Functions
MDMA_LL_Private_Macros
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STM32H7B3xQ HAL User Manual: MDMA Exported Init structure

Data Structures
MDMA Exported Init structure
MDMA

Data Structures

struct | LL_MDMA_InitTypeDef
struct | LL_MDMA_LinkNodeTypeDef
LL MDMA linked list node structure definition. More...
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STM32H7B3xQ HAL User Manual: MDMA Exported Constants

Modules
MDMA Exported Constants
MDMA

Modules

CHANNEL
Word Endianness
Half Word Endianness
Byte Endianness
Transfer Priority level
Bufferable Write Mode
Request Mode
Trigger Mode
Padding Alignment Mode
Transfer Packing
Transfer Destination Burst
Transfer Source Burst
Destination Increment Offset Size
Source Increment Offset Size
Destination Data Size
Source Data Size
Destination Increment Mode
Source Increment Mode
Block Repeat Destination address Update Mode
Source Block Repeat address Update Mode
Destination BUS Selection
Source BUS Selection
HW Trigger Selection
Transfer Error Direction
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STM32H7B3xQ HAL User Manual: MDMA Exported Functions

Modules
MDMA Exported Functions
MDMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: MDMA Exported Macros

Modules
MDMA Exported Macros
MDMA

Modules

Common Write and read registers macros
Convert MDMAxChannely
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STM32H7B3xQ HAL User Manual: MMC

Modules
MMC
STM32H7xx_HAL_Driver

MMC HAL module driver. More...

Modules

MMC Private Functions
MMC Exported Types
Exported Constants
MMC Exported Macros

macros to handle interrupts and specific clock configurations

MMC Exported Functions
MMC Private Defines

Detailed Description

MMC HAL module driver.

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STM32H7B3xQ HAL User Manual: MMC Exported Functions

Modules
MMC Exported Functions
MMC

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Data transfer functions.

Peripheral Control functions

management functions

MMC card related functions
Peripheral State and Errors functions
Perioheral Abort management
MMC Private Types
MMC Private Defines
MMC Private Variables
MMC Private Constants
MMC Private Macros
MMC Private Functions Prototypes
MMC Private Functions
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STM32H7B3xQ HAL User Manual: MMC Exported Types

Modules
MMC Exported Types
MMC

Modules

MMC State enumeration structure
MMC Card State enumeration structure
MMC Handle Structure definition
Card Specific Data: CSD Register
Card Identification Data: CID Register
MMC Callback ID enumeration definition
MMC Callback pointer definition
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STM32H7B3xQ HAL User Manual: Card Specific Data: CSD Register

Data Structures
Card Specific Data: CSD Register
MMC Exported Types

Data Structures

struct HAL_MMC_CardCSDTypeDef
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STM32H7B3xQ HAL User Manual: Card Identification Data: CID Register

Data Structures
Card Identification Data: CID Register
MMC Exported Types

Data Structures

struct HAL_MMC_CardCIDTypeDef
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STM32H7B3xQ HAL User Manual: MMCEx

Modules
MMCEx
STM32H7xx_HAL_Driver

MMC Extended HAL module driver. More...

Modules

MMCEx Exported Types
MMCEx Exported Functions

Detailed Description

MMC Extended HAL module driver.

SD HAL extended module driver.

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STM32H7B3xQ HAL User Manual: MMCEx Exported Functions

Modules
MMCEx Exported Functions
MMCEx

Modules

MultiBuffer functions

Multibuffer functions.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: MMCEx Exported Types

Modules
MMCEx Exported Types
MMCEx

Modules

MMC Internal DMA Buffer structure
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STM32H7B3xQ HAL User Manual: NAND

Modules
NAND
STM32H7xx_HAL_Driver

NAND HAL module driver. More...

Modules

NAND Exported Functions
NAND Exported Types
NAND Exported Macros
NAND Private Constants
NAND Private Macros

Detailed Description

NAND HAL module driver.

Generated on Tue Nov 12 2019 18:50:18 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: NAND Exported Functions

Modules
NAND Exported Functions
NAND

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: NOR

Modules
NOR
STM32H7xx_HAL_Driver

NOR driver modules. More...

Modules

NOR Private Defines
NOR Private Variables
NOR Exported Functions
NOR Exported Types
NOR Exported Macros
NOR Private Constants
NOR Private Macros

Detailed Description

NOR driver modules.

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STM32H7B3xQ HAL User Manual: NOR Exported Functions

Modules
NOR Exported Functions
NOR

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

NOR Control functions

management functions

NOR State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP Mode
OPAMP Non Inverting Input
OPAMP Inverting Input
OPAMP Pga Connect
OPAMP Pga Gain
OPAMP PowerMode
OPAMP VREF
OPAMP User Trimming
OPAMP Factory Trimming
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STM32H7B3xQ HAL User Manual: OPAMP

Modules
OPAMP
STM32H7xx_LL_Driver

Modules

OPAMP Private Constants
OPAMP Private Macros
OPAMP Exported Init structure
OPAMP Exported Constants
OPAMP Exported Macros
OPAMP Exported Functions
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STM32H7B3xQ HAL User Manual: OPAMP Exported Init structure

Data Structures
OPAMP Exported Init structure
OPAMP

Data Structures

struct LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...
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STM32H7B3xQ HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP mode calibration or functional.
OPAMP functional mode
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP input non-inverting
OPAMP input inverting
OPAMP PowerMode
OPAMP trimming mode
OPAMP trimming of transistors differential pair NMOS or PMOS
Definitions of OPAMP hardware constraints delays
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STM32H7B3xQ HAL User Manual: OPAMP Exported Functions

Modules
OPAMP Exported Functions
OPAMP

Modules

Configuration of OPAMP hierarchical scope: OPAMP instance
Configuration of OPAMP inputs
Configuration and operation of OPAMP trimming
Operation on OPAMP instance
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: OPAMP Exported Macros

Modules
OPAMP Exported Macros
OPAMP

Modules

Common write and read registers macro
OPAMP helper macro
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STM32H7B3xQ HAL User Manual: OPAMPEx

Modules
OPAMPEx
STM32H7xx_HAL_Driver

Modules

OPAMPEx Exported Functions
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STM32H7B3xQ HAL User Manual: OPAMPEx Exported Functions

Modules
OPAMPEx Exported Functions
OPAMPEx

Modules

OPAMPEx_Exported_Functions_Group1
Peripheral Control functions

Peripheral Control functions.

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STM32H7B3xQ HAL User Manual: OSPI

Modules
OSPI
STM32H7xx_HAL_Driver

OSPI HAL module driver. More...

Modules

OSPI Exported Functions
OSPI Exported Types
OSPI Exported Constants
OSPI Exported Macros

Detailed Description

OSPI HAL module driver.

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STM32H7B3xQ HAL User Manual: OSPI Exported Constants

Modules
OSPI Exported Constants
OSPI

Modules

OSPI State
OSPI Error Code
OSPI Dual-Quad
OSPI Memory Type
OSPI Free Running Clock
OSPI Clock Mode
OSPI Wrap-Size
OSPI Sample Shifting
OSPI Delay Hold Quarter Cycle
OSPI Delay Block Bypaas
OSPI Operation Type
OSPI Flash Id
OSPI Instruction Mode
OSPI Instruction Size
OSPI Instruction DTR Mode
OSPI Address Mode
OSPI Address Size
OSPI Address DTR Mode
OSPI Alternate Bytes Mode
OSPI Alternate Bytes Size
OSPI Alternate Bytes DTR Mode
OSPI Data Mode
OSPI Data DTR Mode
OSPI DQS Mode
OSPI SIOO Mode
OSPI Hyperbus Write Zero Latency Activation
OSPI Hyperbus Latency Mode
OSPI Hyperbus Address Space
OSPI Match Mode
OSPI Automatic Stop
OSPI Timeout Activation
OSPI Flags
OSPI Interrupts
OSPI Timeout definition
OSPI IO Manager IO Port
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STM32H7B3xQ HAL User Manual: OSPI Exported Functions

Modules
OSPI Exported Functions
OSPI

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

OSPI Transmit/Receive functions.

Peripheral Control and State functions

OSPI control and State functions.

IO Manager configuration function

OSPI IO Manager configuration function.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OTFDEC

Modules
OTFDEC
STM32H7xx_HAL_Driver

OTFDEC HAL module driver. More...

Modules

OTFDEC_Exported_Functions

Detailed Description

OTFDEC HAL module driver.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: OTFDEC_Exported_Functions

Modules
OTFDEC_Exported_Functions
OTFDEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

OTFDEC IRQ handler management

OTFDEC IRQ handler.

Peripheral Control functions

Peripheral control functions.

Peripheral State and Status functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: PCD

Modules
PCD
STM32H7xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

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STM32H7B3xQ HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
PCD Error Code definition

PCD Error Code definition.

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STM32H7B3xQ HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
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STM32H7B3xQ HAL User Manual: PCDEx

Modules
PCDEx
STM32H7xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Detailed Description

PCD Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Exported Constants

Modules
PSSI Exported Constants
PSSI

Modules

PSSI Error Code
PSSI Data Width
PSSI Bus Width
PSSI mode
Configuration
Data Enable Polarity
Reday Polarity
Clock Polarity
PSSI definitions
PSSI Interrupts
Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PSSI Exported Functions

Modules
PSSI Exported Functions
PSSI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

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STM32H7B3xQ HAL User Manual: PWR

Modules
PWR
STM32H7xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macro
PWR Private Constants
PWR Private Macros

Detailed Description

PWR HAL module driver.

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STM32H7B3xQ HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR PVD detection level
PWR PVD Mode
PWR Regulator state in SLEEP/STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Regulator Voltage Scale
PWR Flag
PWR Enable WUP Mask
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STM32H7B3xQ HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and De-Initialization Functions

Initialization and De-Initialization functions.

Peripheral Control Functions

Power Control functions.

Interrupt Handling Functions

Interrupt Handling functions.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32H7B3xQ HAL User Manual: PWR

Modules
PWR
STM32H7xx_LL_Driver

Modules

PWR Private Constants
PWR Exported Constants
PWR Exported Macros
PWR Exported Functions
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

Power mode
Run mode Regulator Voltage Scaling
Stop mode Regulator Voltage Scaling
Regulator Mode In Deep Sleep Mode
Power Digital Voltage Level Detector
Power Analog Voltage Level Detector
Battery Charge Resistor
Wakeup Pins
Wakeup Pins pull configuration
Power supply source configuration
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common write and read registers Macros
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Private Constants

Modules
PWR Private Constants
PWR

Modules

Wake-Up Pins register offsets Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWR Private Constants

Modules
PWR Private Constants
PWR

Modules

PWR PVD Mode Mask
PWR PVD EXTI Line
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STM32H7B3xQ HAL User Manual: PWR Private Macros

Modules
PWR Private Macros
PWR

Modules

PWR Private macros to check input parameters
Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx

Modules
PWREx
STM32H7xx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWREx Exported Functions
PWREx Exported Types
PWREx Exported Constants
PWREx Exported Macro
PWREx Private Macros
PWREx_Private_Constants

Detailed Description

PWR Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Exported Constants

Modules
PWREx Exported Constants
PWREx

Modules

PWREx Wake-Up Pins
PWREx Pin Polarity configuration
PWREx Pin Pull configuration
PWREx Wakeup Pins Flags.
PWREx Domains definition
PWREx Domain Flags definition
PWREx D3 Domain State
PWREx Supply configuration
PWREx AVD detection level
PWREx AVD Mode
PWREx Regulator Voltage Scale
PWR battery charging resistor selection
PWREx VBAT Thresholds
PWREx Temperature Thresholds
PWREx AVD EXTI Line 16
Memory shut-off block selection
Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Exported Functions

Modules
PWREx Exported Functions
PWREx

Modules

Power Supply Control Functions

Power supply control functions.

Low Power Control Functions

Low power control functions.

Peripherals control functions

Peripherals control functions.

Power Monitoring functions

Power Monitoring functions.

Generated on Tue Nov 12 2019 18:50:19 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx_Private_Constants

Modules
PWREx_Private_Constants
PWREx

Modules

PWR Extended AVD Mode Mask
PWR Extended Flag Setting Time Out Value
PWREx Wake-Up Pins masks and offsets
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: PWREx Private Macros

Modules
PWREx Private Macros
PWREx

Modules

PWREx Private macros to check input parameters
Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC

Modules
RAMECC
STM32H7xx_HAL_Driver

RAMECC HAL module driver. More...

Modules

RAMECC Exported Types

RAMECC Exported Types.

RAMECC Error Codes
RAMECC interrupts
RAMECC Monitor flags
RAMECC Exported Macros
RAMECC Exported Functions

RAMECC Exported functions.

RAMECC Private Constants

RAMECC private defines and constants.

RAMECC Private Macros

RAMECC private macros.

monitoring operation functions

monitoring operation functions

Detailed Description

RAMECC HAL module driver.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RAMECC Exported Functions

Modules
RAMECC Exported Functions
RAMECC

RAMECC Exported functions. More...

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

monitoring operation functions

monitoring operation functions

Error informations functions

Error informations functions.

Detailed Description

RAMECC Exported functions.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC

Modules
RCC
STM32H7xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Private Constants

Detailed Description

RCC HAL module driver.

Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

RCC Oscillator Type
RCC HSE Config
RCC LSE Config
RCC HSI Config
RCC HSI48 Config
RCC LSI Config
RCC CSI Config
RCC PLL Config
RCC PLL Clock Source
RCC PLL Clock Output
RCC PLL1 VCI Range
RCC PLL1 VCO Range
RCC System Clock Type
RCC System Clock Source
System Clock Source Status
RCC SYS Clock Source
RCC HCLK Clock Source
RCC APB3 Clock Source
RCC APB1 Clock Source
RCC APB2 Clock Source
RCC APB4 Clock Source
RCC RTC Clock Source
RCC MCO Index
RCC MCO1 Clock Source
RCC MCO2 Clock Source
RCC MCOx Clock Prescaler
RCC Interrupt
RCC Flag

Elements values convention: XXXYYYYYb.

LSE Drive Config
RCC Stop WakeUpClock
RCC Stop KernelWakeUpClock
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STM32H7B3xQ HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

RCC_Exported_Functions_Group2
Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
Generated on Tue Nov 12 2019 18:50:20 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

HSI oscillator divider
LSE oscillator drive capability
System clock switch
System clock switch status
System wakeup clock source
Kernel wakeup clock source
System prescaler
AHB prescaler
APB low-speed prescaler (APB1)
APB low-speed prescaler (APB2)
APB low-speed prescaler (APB3)
APB low-speed prescaler (APB4)
MCO source selection
MCO prescaler
HSE prescaler for RTC clock
Peripheral USART clock source selection
Peripheral LPUART clock source selection
Peripheral I2C clock source selection
Peripheral LPTIM clock source selection
Peripheral SAI clock source selection
Peripheral SDMMC clock source selection
Peripheral RNG clock source selection
Peripheral USB clock source selection
Peripheral CEC clock source selection
Peripheral DFSDM clock source selection
Peripheral DFSDM2 clock source selection
Peripheral FMC clock source selection
Peripheral OSPI clock source selection
Peripheral CLKP clock source selection
Peripheral SPI clock source selection
Peripheral SPDIF clock source selection
Peripheral FDCAN clock source selection
Peripheral SWP clock source selection
Peripheral ADC clock source selection
RTC clock source selection
Timers clocks prescalers selection
All PLLs entry clock source
All PLLs input range
All PLLs VCO range
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
CSI
HSI48
CPUCKREADY
CDCKREADY
RESET
LSE
LSI
System
MCO
Peripheral Clock Source
RTC
TIM
PLL
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
Peripheral clock frequency
Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCC Exported Types

Data Structures | Modules
RCC Exported Types
RCC

Data Structures

struct LL_PLL_ClocksTypeDef
PLL Clocks Frequency Structure. More...

Modules

Clocks Frequency Structure
Generated on Tue Nov 12 2019 18:50:33 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

RCCEx Periph Clock Selection
RCC PLL2 Clock Output
RCC PLL3 Clock Output
RCC PLL2 VCI Range
RCC PLL2 VCO Range
RCC PLL3 VCI Range
RCC PLL3 VCO Range
RCCEx USART1/6 Clock Source
RCCEx USART1 Clock Source
RCCEx USART6 Clock Source
RCCEx UART9 Clock Source
RCCEx USART10 Clock Source
RCCEx USART2/3/4/5/7/8 Clock Source
RCCEx USART2 Clock Source
RCCEx USART3 Clock Source
RCCEx UART4 Clock Source
RCCEx UART5 Clock Source
RCCEx UART7 Clock Source
RCCEx UART8 Clock Source
RCCEx LPUART1 Clock Source
RCCEx I2C1/2/3 Clock Source
RCCEx I2C1 Clock Source
RCCEx I2C2 Clock Source
RCCEx I2C3 Clock Source
RCCEx I2C4 Clock Source
RCCEx RNG Clock Source
RCCEx USB Clock Source
SAI1 Clock Source
Source SAI2A Clock Source
Clock_Source SAI2B Clock Source
SPI1/2/3 Clock Source
SPI1 Clock Source
SPI2 Clock Source
SPI3 Clock Source
SPI4/5 Clock Source
SPI4 Clock Source
SPI5 Clock Source
SPI6 Clock Source
RCCEx LPTIM1 Clock Source
RCCEx LPTIM2 Clock Source
RCCEx LPTIM3/4/5 Clock Source
RCCEx LPTIM3 Clock Source
RCCEx OSPI Clock Source
RCCEx FMC Clock Source
RCCEx FDCAN Clock Source
RCCEx SDMMC Clock Source
RCCEx ADC Clock Source
RCCEx SWPMI1 Clock Source
RCCEx DFSDM1 Clock Source
RCCEx DFSDM2 Clock Source
RCCEx SPDIFRX Clock Source
RCCEx CEC Clock Source
RCCEx CLKP Clock Source
RCCEx TIM Prescaler Selection
RCCEx RCC WWDGx
RCCEx CRS Status
RCCEx CRS SynchroSource
RCCEx CRS SynchroDivider
RCCEx CRS SynchroPolarity
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCCEx CRS Interrupt Sources
RCCEx CRS Flags
Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Exported Functions

Modules
Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended System Control functions

Extended Peripheral Control functions.

Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLL2InitTypeDef
PLL2 Clock structure definition. More...
struct | RCC_PLL3InitTypeDef
PLL3 Clock structure definition. More...
struct | PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition. More...
struct | PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition. More...
struct | PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...
Generated on Tue Nov 12 2019 18:50:21 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RCCEx Private Macros

Modules
RCCEx Private Macros
RCCEx

Modules

RCC Private macros to check input parameters
Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG

Modules
RNG
STM32H7xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG_Private_Defines
RNG Private Constants
RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Macros

Detailed Description

RNG HAL module driver.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
RNG Clock Error Detection
RNG Error Definition
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STM32H7B3xQ HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and configuration functions

Initialization and configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG Init Structure definition
RNG State Structure definition
RNG Handle Structure definition
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STM32H7B3xQ HAL User Manual: RNG Init Structure definition

Data Structures
RNG Init Structure definition
RNG Exported Types

Data Structures

struct RNG_InitTypeDef
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STM32H7B3xQ HAL User Manual: RNG

Modules
RNG
STM32H7xx_LL_Driver

Modules

RNG Exported Init structures
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG_LL_Private_Macros
Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Init structures

Data Structures
RNG Exported Init structures
RNG

Data Structures

struct LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...
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STM32H7B3xQ HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

Clock Error Detection
Value used to configure an internal

programmable divider acting on the incoming RNG clock

NIST Compliance configuration
Get Flags Defines

Flags defines which can be used with LL_RNG_ReadReg function.

IT Defines

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

RNG Configuration functions
FLAG Management
IT Management
Data Management
Health Test Control
Initialization and de-initialization functions
Generated on Tue Nov 12 2019 18:50:34 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNG Exported Macros

Modules
RNG Exported Macros
RNG

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: RNGEx

Modules
RNGEx
STM32H7xx_HAL_Driver

RNG Extension HAL module driver. More...

Modules

RNGEx_Private_Defines
RNG Private Constants
RNGEx Exported Types

RNGEx Exported types.

RNGEX Exported Constants
RNGEx Private Types
RNGEx Private Variables
RNGEx Private Macros
RNGEx Private Functions
RNGEx Exported Functions

Detailed Description

RNG Extension HAL module driver.

RNG Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNGEX Exported Constants

Modules
RNGEX Exported Constants
RNGEx

Modules

Value used to configure an internal

programmable divider acting on the incoming RNG clock

NIST Compliance configuration
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STM32H7B3xQ HAL User Manual: RNGEx Exported Functions

Modules
RNGEx Exported Functions
RNGEx

Modules

RNGEx_Exported_Functions_Group1

Configuration functions.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RNGEx Exported Types

Data Structures
RNGEx Exported Types
RNGEx

RNGEx Exported types. More...

Data Structures

struct RNG_ConfigTypeDef
RNGEX Configuration Structure definition. More...

Detailed Description

RNGEx Exported types.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC

Modules
RTC
STM32H7xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats Definitions
RTC Output Selection Definitions
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output Pull-Up ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLight Saving Definitions
RTC Store Operation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions (in BCD format)
RTC WeekDay Definitions
RTC Alarm Date WeekDay Definitions
RTC Alarm Mask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
RTC Clear Flags Definitions
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STM32H7B3xQ HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC

Modules
RTC
STM32H7xx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
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STM32H7B3xQ HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
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STM32H7B3xQ HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
ACTIVE TAMPER MODE
ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
ACTIVE TAMPER OUTPUT SELECTION
WAKEUP CLOCK DIV
BACKUP
Calibration output
Calibration pulse insertion
Calibration period
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STM32H7B3xQ HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Time-stamp on Tamper
Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Active Tamper
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: RTC Exported Macros

Modules
RTC Exported Macros
RTC

Modules

Common Write and read registers Macros
Convert helper Macros
Date helper Macros
Time helper Macros
Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32H7B3xQ HAL User Manual: RTCEx

Modules
RTCEx
STM32H7xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Exported Functions
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

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STM32H7B3xQ HAL User Manual: RTC Active Tamper structures definitions

Data Structures
RTC Active Tamper structures definitions
RTCEx Exported Types

Data Structures

struct | RTC_ATampInputTypeDef
struct | RTC_ActiveTampersTypeDef
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STM32H7B3xQ HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTC Backup Registers Number Definitions
RTC Backup Registers Definitions
RTC TimeStamp Edges Definitions
RTC TimeStamp Pin Selection
RTC Tamper Pins Definitions
RTC Tamper Interrupts Definitions
RTC Internal Tamper Pins Definition
RTC Internal Tamper Interrupt
RTC Tamper Triggers Definitions
RTC Tamper EraseBackUp Definitions
RTC Tamper Mask Flag Definitions
RTC Tamper Filter Definitions
RTC Tamper Sampling Frequencies Definitions
RTC Tamper Pin Precharge Duration Definitions
RTC Tamper TimeStamp On Tamper Detection Definitions
RTC Tamper Pull Up Definitions
RTC Tamper Detection Ouput Definitions
RTC Tamper Flags Definitions
RTCEx_ActiveTamper_Enable Definitions
RTCEx_ActiveTamper_Interrupt Definitions
RTCEx_ActiveTamper_Filter Definitions
RTC Active_Tamper_Asynchronous_Prescaler clock Definitions
RTC Active Tamper selection Definition
RTC Tamper Registers Offset
RTC Wakeup Timer Definitions
RTC Smooth Calib Period Definitions
RTC Smooth Calib Plus pulses Definitions
RTC Calib Output Selection Definitions
RTC Add 1 Second Parameter Definitions
Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

Extended RTC TimeStamp functions

RTC TimeStamp and Tamper functions.

Extended RTC Tamper functions

Extended RTC Tamper functions.

Extended RTC Wake-up functions

RTC Wake-up functions.

Extended RTC Backup register functions

Extended RTC Backup register functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx Exported Types

Modules
RTCEx Exported Types
RTCEx

Modules

RTC Tamper structure definition
RTCEx Internal Tamper structure definition
Seed size Definitions
Active Tampers number Definitions
RTC Active Tamper structures definitions
Generated on Tue Nov 12 2019 18:50:22 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: RTCEx Internal Tamper structure definition

Data Structures
RTCEx Internal Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_InternalTamperTypeDef
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STM32H7B3xQ HAL User Manual: RTC Tamper structure definition

Data Structures
RTC Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_TamperTypeDef
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STM32H7B3xQ HAL User Manual: SAI

Modules
SAI
STM32H7xx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Private Functions

Private functions.

SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI_Private_Macros

Detailed Description

SAI HAL module driver.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Block Master Clock Output
SAI Supported protocol
SAI protocol data size
SAI Audio Frequency
SAI Block Master Clock OverSampling
SAI PDM Clock Enable
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
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STM32H7B3xQ HAL User Manual: SAI Exported Functions

Modules
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Frame Structure definition

Data Structures
SAI Frame Structure definition
SAI Exported Types

SAI Frame Init structure definition. More...

Data Structures

struct SAI_FrameInitTypeDef

Detailed Description

SAI Frame Init structure definition.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Init Structure definition

Data Structures
SAI Init Structure definition
SAI Exported Types

SAI Init Structure definition. More...

Data Structures

struct SAI_InitTypeDef

Detailed Description

SAI Init Structure definition.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI PDM Structure definition

Data Structures
SAI PDM Structure definition
SAI Exported Types

SAI PDM Init structure definition. More...

Data Structures

struct SAI_PdmInitTypeDef

Detailed Description

SAI PDM Init structure definition.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAI Slot Structure definition

Data Structures
SAI Slot Structure definition
SAI Exported Types

SAI Block Slot Init Structure definition. More...

Data Structures

struct SAI_SlotInitTypeDef

Detailed Description

SAI Block Slot Init Structure definition.

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STM32H7B3xQ HAL User Manual: SAIEx Extended Exported Functions

Modules
SAIEx Extended Exported Functions
SAIEx

Modules

Peripheral Control functions

SAIEx control functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SAIEx Exported Types

Data Structures
SAIEx Exported Types
SAIEx

Data Structures

struct SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...
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STM32H7B3xQ HAL User Manual: SD Exported Functions

Modules
SD Exported Functions
SD

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Data transfer functions.

Peripheral Control functions

management functions

SD card related functions
Peripheral State and Errors functions
Perioheral Abort management
SD Private Types
SD Private Defines
SD Private Variables
SD Private Constants
SD Private Macros
SD Private Functions Prototypes
SD Private Functions
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Exported Types

Modules
SD Exported Types
SD

Modules

SD State enumeration structure
SD Card State enumeration structure
SD Handle Structure definition
Card Specific Data: CSD Register
Card Identification Data: CID Register
SD Card Status returned by ACMD13
SD Callback ID enumeration definition
SD Callback pointer definition
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Card Specific Data: CSD Register

Data Structures
Card Specific Data: CSD Register
SD Exported Types

Data Structures

struct HAL_SD_CardCSDTypeDef
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: Card Identification Data: CID Register

Data Structures
Card Identification Data: CID Register
SD Exported Types

Data Structures

struct HAL_SD_CardCIDTypeDef
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SD Card Status returned by ACMD13

Data Structures
SD Card Status returned by ACMD13
SD Exported Types

Data Structures

struct HAL_SD_CardStatusTypeDef
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDEx

Modules
SDEx
STM32H7xx_HAL_Driver

SD Extended HAL module driver. More...

Modules

SDEx Exported Types
SDEx Exported Functions

Detailed Description

SD Extended HAL module driver.

SD HAL extended module driver.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDEx Exported Functions

Modules
SDEx Exported Functions
SDEx

Modules

MultiBuffer functions

Multibuffer functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDEx Exported Types

Modules
SDEx Exported Types
SDEx

Modules

SD Card Internal DMA Buffer structure
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDRAM

Modules
SDRAM
STM32H7xx_HAL_Driver

SDRAM driver modules. More...

Modules

SDRAM Exported Functions
SDRAM Exported Types
SDRAM Exported Macros

Detailed Description

SDRAM driver modules.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SDRAM Exported Functions

Modules
SDRAM Exported Functions
SDRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Control functions

management functions

State functions

Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32H7xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD State Code Definition
SMARTCARD Error Code Definition
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD Clock Prescaler
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD interruptions flags mask
Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Generated on Tue Nov 12 2019 18:50:23 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32H7xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Private Constants
SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Detailed Description

SMARTCARD Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARD FIFO mode

SMARTCARD FIFO mode.

SMARTCARD TXFIFO threshold level

SMARTCARD TXFIFO level.

SMARTCARD RXFIFO threshold level

SMARTCARD RXFIFO level.

SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Extended Peripheral IO operation functions

SMARTCARD Transmit and Receive functions.

Extended Peripheral FIFO Control functions

SMARTCARD control functions.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS

Modules
SMBUS
STM32H7xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS ownaddress2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPDIFRX Exported Constants

Modules
SPDIFRX Exported Constants
SPDIFRX

Modules

SPDIFRX Error Code
SPDIFRX Input Selection
SPDIFRX Maximum Retries
SPDIFRX Wait For Activity
SPDIFRX Preamble Type Mask
SPDIFRX Channel Status Mask
SPDIFRX Validity Mask
SPDIFRX Parity Error Mask
SPDIFRX Channel Selection
SPDIFRX Data Format
SPDIFRX Stereo Mode
SPDIFRX State
SPDIFRX Interrupts Definition
SPDIFRX Flags Definition
Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI

Modules
SPI
STM32H7xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Tue Nov 12 2019 18:50:24 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI FIFO Type
SPI Error Codes
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length
SPI Fifo Threshold
SPI CRC Calculation Initialization Pattern
SPI NSS Polarity
Keep IO State
Control SPI IO Swap
SPI Master SS Idleness
SPI Master Inter-Data Idleness
SPI Master Receiver AutoSuspend
SPI Underrun Detection
SPI Underrun Behavior
SPI Interrupt Definition
SPI Flags Definition
SPI Reception FIFO Status Level
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STM32H7B3xQ HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

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STM32H7B3xQ HAL User Manual: SPI

Modules
SPI
STM32H7xx_LL_Driver

Modules

SPI Private Macros
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions
I2S
Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Mode
SS Level
SS Idleness
Master Inter-Data Idleness
TXCRC Init All
RXCRC Init All
UDR Config Register
UDR Detect Begin Data
Protocol
Phase
Polarity
NSS Polarity
Baud Rate Prescaler
Bit Order
Transfer Mode
Data Width
FIFO Threshold
CRC Calculation
CRC
NSS Mode
RxFIFO Packing LeVel
Generated on Tue Nov 12 2019 18:50:35 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
FLAG_Management
IT_Management
DMA Management
DATA_Management
Initialization and de-initialization functions
Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
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STM32H7B3xQ HAL User Manual: SPIEx

Modules
SPIEx
STM32H7xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

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STM32H7B3xQ HAL User Manual: SRAM

Modules
SRAM
STM32H7xx_HAL_Driver

SRAM driver modules. More...

Modules

SRAM Exported Functions
SRAM Exported Types
SRAM Exported Macros

Detailed Description

SRAM driver modules.

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STM32H7B3xQ HAL User Manual: SRAM Exported Functions

Modules
SRAM Exported Functions
SRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input Output and memory control functions

Input Output and memory control functions.

Control functions

Control functions.

Peripheral State functions

Peripheral State functions.

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STM32H7B3xQ HAL User Manual: STM32H7xx_HAL_Driver

Modules
STM32H7xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

CEC

HAL CEC module driver.

COMP

COMP HAL module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extension HAL module driver.

DAC

DAC driver modules.

DACEx

DAC Extended HAL module driver.

DCMI

DCMI HAL module driver.

DFSDM

DFSDM HAL driver module.

DFSDMEx

DFSDM Extended HAL module driver.

DMA

DMA HAL module driver.

DMA2D

DMA2D HAL module driver.

DMAEx

DMA Extended HAL module driver.

DTS

DTS HAL module driver.

EXTI

EXTI HAL module driver.

FDCAN

FDCAN HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

GFXMMU

GFXMMU HAL driver module.

GPIO

GPIO HAL module driver.

HASH

HASH HAL module driver.

HASHEx

HASH HAL extended module driver.

HCD

HCD HAL module driver.

HSEM

HSEM HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

I2S

I2S HAL module driver.

I2SEx

I2S Extended HAL module driver.

IRDA

HAL IRDA module driver.

IRDAEx

IRDA Extended HAL module driver.

IWDG

IWDG HAL module driver.

JPEG

JPEG HAL module driver.

LPTIM

LPTIM HAL module driver.

LTDC

LTDC HAL module driver.

MDIOS

HAL MDIOS module driver.

MDMA

MDMA HAL module driver.

MMC

MMC HAL module driver.

MMCEx

MMC Extended HAL module driver.

NAND

NAND HAL module driver.

NOR

NOR driver modules.

OPAMP

OPAMP module driver.

OSPI

OSPI HAL module driver.

OTFDEC

OTFDEC HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PSSI

PSSI HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

RAMECC

RAMECC HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC HAL module driver.

RNG

RNG HAL module driver.

RNGEx

RNG Extension HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extended HAL module driver.

SD

SD HAL module driver.

SDEx

SD Extended HAL module driver.

SDRAM

SDRAM driver modules.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SPDIFRX

SPDIFRX HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

SRAM

SRAM driver modules.

SWPMI

HAL SWPMI module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

USARTEx

USART Extended HAL module driver.

WWDG

WWDG HAL module driver.

DELAYBLOCK_LL

Low layer module for Delay Block.

GPIOEx
OPAMPEx
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STM32H7B3xQ HAL User Manual: STM32H7xx_LL_Driver

Modules
STM32H7xx_LL_Driver

Modules

ADC
BDMA
BUS
COMP
CORTEX
CRC
CRS
DAC
DMA
DMA2D
DMAMUX
EXTI
GPIO
HSEM
I2C
IWDG
LPTIM
LPUART
MDMA
OPAMP
PWR
RCC
RNG
RTC
SPI
SWPMI
SYSTEM
TIM
USART
UTILS
WWDG
I2S
Generated on Tue Nov 12 2019 18:50:39 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI

Modules
SWPMI
STM32H7xx_HAL_Driver

HAL SWPMI module driver. More...

Modules

SWPMI Exported Functions
SWPMI Private Functions
SWPMI Exported Types
SWPMI Exported Constants
SWPMI Exported Macros
SWPMI Private Types
SWPMI Private Variables
SWPMI Private Constants
SWPMI Private Macros

Detailed Description

HAL SWPMI module driver.

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STM32H7B3xQ HAL User Manual: SWPMI Exported Constants

Modules
SWPMI Exported Constants
SWPMI

Modules

SWPMI Error Code Bitmap
SWPMI Voltage Class
SWPMI Tx Buffering Mode
SWPMI Rx Buffering Mode
SWPMI Status Flags

Elements values convention: 0xXXXXXXXX.

SWPMI Interrupts Definition

Elements values convention: 0xXXXX.

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STM32H7B3xQ HAL User Manual: SWPMI

Modules
SWPMI
STM32H7xx_LL_Driver

Modules

SWPMI Private Macros
SWPMI Exported Init structure
SWPMI Exported Constants
SWPMI Exported Macros
SWPMI Exported Functions
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STM32H7B3xQ HAL User Manual: SWPMI Exported Init structure

Data Structures
SWPMI Exported Init structure
SWPMI

Data Structures

struct LL_SWPMI_InitTypeDef
SWPMI Init structures definition. More...
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STM32H7B3xQ HAL User Manual: SWPMI Exported Constants

Modules
SWPMI Exported Constants
SWPMI

Modules

Clear Flags Defines

Flags defines which can be used with LL_SWPMI_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_SWPMI_ReadReg function.

IT Defines

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions.

SW BUFFER RX
SW BUFFER TX
VOLTAGE CLASS
DMA register data
Generated on Tue Nov 12 2019 18:50:36 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: SWPMI Exported Functions

Modules
SWPMI Exported Functions
SWPMI

Modules

Configuration
FLAG_Management
IT_Management
DMA_Management
Data_Management
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: SWPMI Exported Macros

Modules
SWPMI Exported Macros
SWPMI

Modules

Common Write and read registers Macros
Bit rate calculation helper Macros
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STM32H7B3xQ HAL User Manual: SYSTEM

Modules
SYSTEM
STM32H7xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions
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STM32H7B3xQ HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG I2C FASTMODEPLUS
Analog Switch control
SYSCFG EXTI PORT
SYSCFG EXTI LINE
SYSCFG TIMER BREAK
SYSCFG I/O compensation cell Code selection
SYSCFG IWDG1 control modes
SYSCFG DTCM RAM size configuration
SYSCFG Brownout Reset Threshold Level
DBGMCU TRACE Pin Assignment
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB1 GRP2 STOP IP
DBGMCU APB2 GRP1 STOP IP
DBGMCU APB3 GRP1 STOP IP
DBGMCU APB4 GRP1 STOP IP
FLASH LATENCY
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STM32H7B3xQ HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
FLASH
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STM32H7B3xQ HAL User Manual: SYSTEM Private Constants

Modules
SYSTEM Private Constants
SYSTEM

Modules

SYSCFG Flash Bank1 sectors bits status
SYSCFG Flash Bank2 sectors bits status
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STM32H7B3xQ HAL User Manual: TIM

Modules
TIM
STM32H7xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Private Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros

Detailed Description

TIM HAL module driver.

Generated on Tue Nov 12 2019 18:50:25 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Clear Input Source
TIM DMA Base Address
TIM Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare State
TIM Auto-Reload Preload
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Encoder Input Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Flag Definition
TIM Channel
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input Enable
TIM Break Input Polarity
TIM Break input 2 Enable
TIM Break Input 2 Polarity
TIM Automatic Output Enable
Group Channel 5 and Channel 1, 2 or 3
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Output Compare and PWM Modes
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
TIM Break System
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STM32H7B3xQ HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

TIM Time Base functions

Time Base functions.

TIM Output Compare functions

TIM Output Compare functions.

TIM PWM functions

TIM PWM functions.

TIM Input Capture functions

TIM Input Capture functions.

TIM One Pulse functions

TIM One Pulse functions.

TIM Encoder functions

TIM Encoder functions.

TIM IRQ handler management

TIM IRQ handler management.

TIM Peripheral Control functions

TIM Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

TIM Peripheral State functions

TIM Peripheral State functions.

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STM32H7B3xQ HAL User Manual: TIM

Modules
TIM
STM32H7xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions
Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Timer input remapping
FLAG-Management
IT-Management
DMA-Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Tue Nov 12 2019 18:50:37 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
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STM32H7B3xQ HAL User Manual: TIMEx

Modules
TIMEx
STM32H7xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Exported Functions
TIMEx Private Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros
TIM Extended Private Macros

Detailed Description

TIM Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Remapping
TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity
TIM Extended Timer input selection
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STM32H7B3xQ HAL User Manual: TIM Extended Exported Functions

Modules
TIM Extended Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART

Modules
UART
STM32H7xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros

Detailed Description

HAL UART module driver.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART State Code Definition
UART Error Definition
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Clock Prescaler
UART Advanced Feature AutoBaud Rate Mode
UART Receiver Timeout
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx

Modules
UARTEx
STM32H7xx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Constants
UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
UARTEx WakeUp Address Length
UARTEx FIFO mode

UART FIFO mode.

UARTEx TXFIFO threshold level

UART TXFIFO threshold level.

UARTEx RXFIFO threshold level

UART RXFIFO threshold level.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

IO operation functions

Extended functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART

Modules
USART
STM32H7xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Definition
USART Number of Stop Bits
USART Parity
USART Mode
USART Over Sampling
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Clock Prescaler
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Tue Nov 12 2019 18:50:26 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USART

Modules
USART
STM32H7xx_LL_Driver

Modules

USART Private Variables
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions
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STM32H7B3xQ HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
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STM32H7B3xQ HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

FIFO Threshold
Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
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STM32H7B3xQ HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to SPI Slave feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
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STM32H7B3xQ HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
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STM32H7B3xQ HAL User Manual: USARTEx

Modules
USARTEx
STM32H7xx_HAL_Driver

USART Extended HAL module driver. More...

Modules

USARTEx Private Constants
USARTEx Private Functions
USARTEx Exported Functions
USARTEx Exported Constants
USARTEx Private Macros

Detailed Description

USART Extended HAL module driver.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
USARTEx Slave Select Management
USARTEx Synchronous Slave mode enable

USART SLAVE mode.

USARTEx FIFO mode

USART FIFO mode.

USARTEx TXFIFO threshold level

USART TXFIFO level.

USARTEx RXFIFO threshold level

USART RXFIFO level.

Generated on Tue Nov 12 2019 18:50:27 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: USARTEx Exported Functions

Modules
USARTEx Exported Functions
USARTEx

Modules

IO operation functions

Extended USART Transmit/Receive functions.

Peripheral Control functions

Extended Peripheral Control functions.

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STM32H7B3xQ HAL User Manual: UTILS

Modules
UTILS
STM32H7xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
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STM32H7B3xQ HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
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STM32H7B3xQ HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
PACKAGE TYPE
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STM32H7B3xQ HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

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STM32H7B3xQ HAL User Manual: WWDG

Modules
WWDG
STM32H7xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

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STM32H7B3xQ HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32H7B3xQ HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

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STM32H7B3xQ HAL User Manual: WWDG

Modules
WWDG
STM32H7xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions
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STM32H7B3xQ HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
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STM32H7B3xQ HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
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STM32H7B3xQ HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
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STM32H7B3xQ HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32H7xx_HAL_Driver
    • HAL
      • HAL Exported Variables
      • HAL Private Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • Tick Frequency
      • device revision ID
      • VREFBUF Voltage Scale
      • VREFBUF High Impedance
      • Fast-mode Plus on GPIO
      • Ethernet Config
      • Analog Switch Config
      • Boot Config
      • IOCompenstionCell Config
      • Event Input Config
      • SwapBankMapping Config
      • ART Exported Macros
      • SYSCFG Exported Macros
      • HAL Private Macros
    • ADC
      • ADC Private Constants
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • ADC Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Private Functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC common - Clock source
        • ADC instance - Resolution
        • ADC sequencer scan mode
        • ADC group regular trigger source
        • ADC group regular trigger edge (when external trigger is selected)
        • ADC sequencer end of unitary conversion or sequence conversions
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer ranks
        • Channel - Sampling time
        • ADC Extended Calibration mode offset mode or linear mode
        • ADC instance - Channel number
        • ADC Conversion Data Management
        • Analog watchdog - Analog watchdog number
        • ADC Analog Watchdog Mode
        • Oversampling - Data shift
        • ADC Extended Oversampling left Shift
        • Oversampling - Discontinuous mode
        • Oversampling - Oversampling scope for ADC group regular
        • ADC Event type
        • ADC interrupts definition
        • ADC flags definition
      • ADC Private Macros
      • ADC Exported Macros
        • HAL ADC macro to manage HAL ADC handle, IT and flags.
        • HAL ADC helper macro
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • ADC Extended Peripheral Control functions
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC group injected trigger source
        • ADC group injected trigger edge (when external trigger is selected)
        • Channel - Single or differential ending
        • ADC instance - Offset number
        • ADC group injected - Sequencer ranks
        • Multimode - Mode
          • ADC Extended Dual Mode Data Formatting
          • Multimode - Delay between two sampling phases
        • ADC instance - Groups
        • ADCx CFGR fields
        • ADCx SMPR1 fields
        • ADCx CFGR sub fields
        • ADC group regular - DFSDM transfer of ADC conversion data
      • ADC Extended Exported Macros
      • ADC Extended Private Macros
    • CEC
      • CEC Private Constants
      • CEC Private Functions
      • CEC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control function
      • CEC Exported Types
      • CEC Exported Constants
        • CEC State Code Definition
        • CEC Error Code
        • CEC Signal Free Time setting parameter
        • CEC Receiver Tolerance
        • CEC Reception Stop on Error
        • CEC Error Bit Generation if Bit Rise Error reported
        • CEC Error Bit Generation if Long Bit Period Error reported
        • CEC Error Bit Generation on Broadcast message
        • CEC Signal Free Time start option
        • CEC Listening mode option
        • CEC Device Own Address position in CEC CFGR register
        • CEC Initiator logical address position in message header
        • CEC Own Address
        • CEC Interrupts definition
        • CEC Flags definition
        • CEC all RX or TX errors flags
        • CEC all RX errors interrupts enabling flag
        • CEC all TX errors interrupts enabling flag
      • CEC Exported Macros
      • CEC Private Types
      • CEC Private Variables
      • CEC Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Error Code
        • COMP Window Mode
        • COMP power mode
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP Output Polarity
        • COMP Blanking Source
        • COMP Output Level
        • COMP output to EXTI
        • COMP Flag
        • COMP Interruption Clear Flags
        • COMP Interrupts Definitions
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP Private macros to get EXTI line associated with Comparators
        • COMP private macros to check input parameters
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • Cortex Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX _SysTick clock source
        • MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX_CPU_Identifier
      • CORTEX Private Macros
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the peripheral
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
        • CRC API aliases
      • CRC Exported Macros
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • Extended Initialization/de-initialization functions
      • CRC Extended Exported Constants
        • Input Data Inversion Modes
        • Output Data Inversion Modes
      • CRC Extended Exported Macros
      • CRC Extended Private Macros
    • CRYP
      • CRYP Exported Functions
        • Initialization and de-initialization functions
        • Encrypt Decrypt functions
        • CRYP IRQ handler management
        • CRYP Private Functions
      • CRYP Exported Types
      • HAL CRYP Callback ID enumeration definition
      • HAL CRYP Callback pointer definition
      • CRYP Exported Constants
        • CRYP Error Definition
        • CRYP Data Width Unit
        • CRYP Algorithm Mode
        • CRYP Key Size
        • CRYP Data Type
        • CRYP Interrupt
        • CRYP Flags
      • CRYP Exported Macros
      • CRYP Private Macros
        • CRYP Private macros to check input parameters
      • CRYP Private Constants
      • CRYP Private Defines
      • CRYP Private Variables
      • CRYP Private Functions Prototypes
      • CRYP Private Functions
      • CRYP_Private_Functions_prototypes
    • CRYPEx
      • CRYPEx Private Types
      • CRYPEx Private Variables
      • CRYPEx Private Constants
      • CRYPEx Private Macros
      • CRYPEx Private Functions
      • CRYPEx Exported Functions
        • Extended AES processing functions
      • CRYPEx_Private_Defines
    • DAC
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC trigger selection
        • DAC output buffer
        • DAC Channel selection
        • DAC data alignment
        • DAC flags definition
        • DAC IT definition
        • DAC ConnectOnChipPeripheral
        • DAC User Trimming
        • DAC power mode
      • DAC Exported Macros
      • DAC Private Macros
      • DAC Private Functions
      • DAC Private Constants
    • DACEx
      • DACEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • DACEx private functions
      • DACEx Exported Constants
        • DACEx lfsrunmask triangle amplitude
      • DACEx Private Macros
    • DCMI
      • DCMI Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
        • DCMI Private Functions
      • DCMI Exported Types
      • DCMI Exported Constants
        • DCMI Error Code
        • DCMI Capture Mode
        • DCMI Synchronization Mode
        • DCMI PIXCK Polarity
        • DCMI VSYNC Polarity
        • DCMI HSYNC Polarity
        • DCMI MODE JPEG
        • DCMI Capture Rate
        • DCMI Extended Data Mode
        • DCMI Window Coordinate
        • DCMI Window Height
        • DCMI interrupt sources
        • DCMI Flags
        • DCMI Byte Select Mode
        • DCMI Byte Select Start
        • DCMI Line Select Mode
        • DCMI Line Select Start
      • DCMI Exported Macros
      • DCMI Private Constants
      • DCMI Private Macros
      • DCMI Private Functions
    • DFSDM
      • DFSDM Private Define
      • DFSDM Private Variables
      • DFSDM Private Functions
      • DFSDM Exported Functions
        • Channel initialization and de-initialization functions
        • Channel operation functions
        • Channel state function
        • Filter initialization and de-initialization functions
        • Filter control functions
        • Filter operation functions
        • Filter state functions
      • DFSDM Exported Types
      • DFSDM Exported Constants
        • DFSDM channel output clock selection
        • DFSDM channel input multiplexer
        • DFSDM channel input data packing
        • DFSDM channel input pins
        • DFSDM channel serial interface type
        • DFSDM channel SPI clock selection
        • DFSDM channel analog watchdog filter order
        • DFSDM filter conversion trigger
        • DFSDM filter external trigger
        • DFSDM filter external trigger edge
        • DFSDM filter sinc order
        • DFSDM filter analog watchdog data source
        • DFSDM filter error code
        • DFSDM break signals
        • DFSDM Channel Selection
        • DFSDM Continuous Mode
        • DFSDM analog watchdog threshold
      • DFSDM Exported Macros
      • DFSDM Private Macros
    • DFSDMEx
      • DFSDM Extended Exported Functions
        • Extended channel operation functions
      • DFSDM Extended Private Macros
    • DMA
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Request selection
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA FIFO direct mode
        • DMA FIFO threshold level
        • DMA Memory burst
        • DMA Peripheral burst
        • DMA interrupt enable definitions
        • DMA flag definitions
        • BDMA flag definitions
      • DMA Exported Macros
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • I/O operation functions
        • Peripheral State functions
      • DMA Private Constants
      • DMA Private Macros
      • DMA Private Functions
    • DMA2D
      • DMA2D Private Constants
        • DMA2D Time Out
      • DMA2D Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • DMA2D Private Functions
    • DMAEx
      • DMAEx Exported Types
      • DMA Exported Constants
        • DMAEx MUX SyncSignalID selection
        • DMAEx MUX SyncPolarity selection
        • DMAEx MUX SignalGeneratorID selection
        • DMAEx MUX RequestGeneneratorPolarity selection
      • DMAEx Exported Functions
        • Extended features functions
      • DMA Private Macros
      • DMAEx Private Functions
    • DTS
      • DTS_Private_Constants
        • DTS Exported Functions
          • Initialization/de-initialization functions
          • Start-Stop operation functions
          • Peripheral State functions
        • DTS Private Functions
    • EXTI
      • EXTI Private Constants
      • EXTI Exported Types
      • EXTI Exported Constants
        • EXTI Line
        • EXTI Mode
        • EXTI Trigger
        • EXTI GPIOSel
        • EXTI PendClear Source
      • EXTI Exported Macros
      • EXTI Private Macros
      • EXTI Exported Functions
        • Configuration functions
        • IO operation functions
    • FDCAN
      • FDCAN Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • Control functions
        • TT Configuration and control functions
        • Interrupts management
        • Callback functions
        • Peripheral State functions
      • FDCAN Exported Types
      • FDCAN Exported Constants
        • HAL FDCAN Error Code
        • FDCAN Frame Format
        • FDCAN Operating Mode
        • FDCAN Clock Calibration
        • FDCAN Clock Divider
        • FDCAN Calibration Field Length
        • FDCAN Calibration State
        • FDCAN Calibration Counter
        • FDCAN Data Field Size
        • FDCAN Tx FIFO/Queue Mode
        • FDCAN ID Type
        • FDCAN Frame Type
        • FDCAN Data Length Code
        • FDCAN Error State Indicator
        • FDCAN Bit Rate Switching
        • FDCAN format
        • FDCAN Event FIFO control
        • FDCAN Filter Type
        • FDCAN Filter Configuration
        • FDCAN Tx Location
        • FDCAN Rx Location
        • FDCAN Event Type
        • FDCAN High Priority Message Storage
        • FDCAN protocol error code
        • FDCAN communication state
        • FDCAN FIFO watermark
        • FDCAN FIFO operation mode
        • FDCAN non-matching frames
        • FDCAN reject remote frames
        • FDCAN interrupt line
        • FDCAN timestamp
        • FDCAN timestamp prescaler
        • FDCAN timeout operation
        • FDCAN TT reference message payload
        • FDCAN TT repeat factor
        • FDCAN TT trigger type
        • FDCAN TT time mark event internal
        • FDCAN TT time mark event external
        • FDCAN Operation Mode
        • FDCAN TT Operation
        • FDCAN TT Time Master
        • FDCAN TT External Clock Synchronization
        • FDCAN TT Global Time Filtering
        • FDCAN TT Automatic Clock Calibration
        • FDCAN TT Event Trigger Polarity
        • FDCAN TT Basic Cycle Number
        • FDCAN TT Cycle Start Sync
        • FDCAN TT Stop Watch Trigger Selection
        • FDCAN TT Event Trigger Selection
        • FDCAN TT Stop Watch Source
        • FDCAN TT Stop Watch Polarity
        • FDCAN TT Time Mark Source
        • FDCAN TT Error Level
        • FDCAN TT Master State
        • FDCAN TT Synchronization State
        • Interrupt masks
        • FDCAN Flags
        • FDCAN Interrupts
          • FDCAN Tx Interrupts
          • FDCAN Rx Interrupts
          • FDCAN Counter Interrupts
          • Clock Calibration Interrupts
          • FDCAN Tx Event FIFO Interrupts
          • FDCAN Rx FIFO 0 Interrupts
          • FDCAN Rx FIFO 1 Interrupts
          • FDCAN Error Interrupts
          • FDCAN Error Status Interrupts
        • FDCAN TT Flags
        • FDCAN TT Interrupts
          • FDCAN TT Schedule Synchronization Interrupts
          • FDCAN TT Time Mark Interrupts
          • FDCAN TT Stop Watch Interrupt
          • FDCAN TT Global Time Interrupts
          • FDCAN TT Disturbing Error Interrupts
          • FDCAN TT Fatal Error Interrupts
      • FDCAN Exported Macros
      • FDCAN Private Types
      • FDCAN Private Variables
      • FDCAN Private Constants
      • FDCAN Private Macros
      • FDCAN Private Functions Prototypes
      • FDCAN Private Functions
    • FLASH
      • FLASH Exported functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Code
        • FLASH Type Program
        • FLASH Flag definition
        • FLASH Interrupt definition
        • FLASH Keys
        • FLASH Sectors
      • FLASH Exported Macros
      • FLASH Private Variables
      • FLASH Private Constants
      • FLASH Private Macros
      • FLASH Private functions
    • FLASHEx
      • FLASHEx Private Functions
      • FLASHEx Exported Functions
        • Extended IO operation functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Type Erase
        • FLASH WRP State
        • FLASH Option Type
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes WWatchdog
        • FLASH Option Bytes IWatchdog
        • FLASH Option Bytes nRST_STOP
        • FLASH Option Bytes nRST_STDBY
        • FLASH IWDG Counter Freeze in STOP
        • FLASH IWDG Counter Freeze in STANDBY
        • FLASH BOR Reset Level
        • FLASH Boot Address
        • FLASH Latency
        • FLASH Banks
        • FLASHEx OB PCROP RDP
        • FLASH Option Bytes Write Protection
        • FLASHEx OB SECURITY
        • FLASHEx OB ST RAM SIZE
        • FLASHEx OB IWDG1 SW
        • FLASHEx OB NRST STOP D1
        • FLASHEx OB NRST STDBY D1
        • FLASHEx OB SWAP BANK
        • FLASHEx OB IOHSLV
        • FLASHEx OB VDDMMC HSLV
        • FLASHEx OB BOOT OPTION
        • FLASHEx OB USER Type
        • FLASHEx OB SECURE RDP
        • FLASH CRC Selection Type
        • FLASH CRC Burst Size
        • FLASH Programming Delay
        • FLASH OTP blocks
        • FLASH Exported Macros
        • FLASHEx Private Macros
          • FLASHEx Private macros to check input parameters
        • FLASHEx Private Functions
        • FLASHEx Exported Functions
          • Extended IO operation functions
      • FLASHEx_Private_Constants
    • GFXMMU
      • GFXMMU Exported Functions
        • Initialization and de-initialization functions
        • Operations functions
        • State functions
      • GFXMMU Exported Types
      • GFXMMU Exported Constants
        • GFXMMU blocks per line
        • GFXMMU cache lock
        • GFXMMU cache lock buffer
        • GFXMMU cache force
        • GFXMMU outter bufferability
        • GFXMMU outter cachability
        • GFXMMU pre-fetch
        • GFXMMU interrupts
        • GFXMMU Error Code
        • GFXMMU LUT line status
        • GFXMMU cache force parameter
      • GFXMMU Exported Macros
      • GFXMMU Private Macros
    • GPIO
      • GPIO Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins define
        • GPIO mode define
        • GPIO speed define
        • GPIO pull define
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Private Functions
    • HASH
      • HASH Private Constants
        • HASH Digest Calculation Status
        • HASH Number of Context Swap Registers
        • HASH TimeOut Value
        • HASH DMA suspension words limit
      • HASH Private Functions
      • HASH Exported Functions
        • Initialization and de-initialization functions
        • HASH processing functions in polling mode
        • HASH processing functions in interrupt mode
        • HASH processing functions in DMA mode
        • HMAC processing functions in polling mode
        • HMAC processing functions in interrupt mode
        • HMAC processing functions in DMA mode
        • Peripheral states functions
      • HASH Exported Types
      • HASH Exported Constants
        • HASH algorithm selection
        • HASH algorithm mode
        • HASH input data type
        • HMAC key length type
        • HASH flags definitions
        • HASH interrupts definitions
        • HASH API alias
        • HASH Error Definition
      • HASH Exported Macros
      • HASH Private Macros
    • HASHEx
      • HASH Extended Exported Functions
        • HASH extended processing functions in polling mode
        • HASH extended processing functions in interrupt mode
        • HASH extended processing functions in DMA mode
        • HMAC extended processing functions in polling mode
        • HMAC extended processing functions in interrupt mode
        • HMAC extended processing functions in DMA mode
        • Multi-buffer HMAC extended processing functions in DMA mode
    • HCD
      • HCD Private Functions
      • HCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG HCD Callback ID enumeration definition
          • HAL USB OTG HCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • HCD Exported Types
        • HCD State Structure definition
        • HCD Handle Structure definition
      • HCD Exported Constants
        • HCD Speed
        • HCD PHY Module
        • HCD Error Code definition
      • HCD Exported Macros
      • HCD Private Macros
      • HCD Private Functions Prototypes
    • HSEM
      • HSEM Exported Functions
        • Take and Release functions
        • HSEM Set and Get Key functions
        • HSEM IRQ handler management
      • HSEM Exported Macros
      • HSEM Private Macros
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction Master Point of View
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Extended features functions
          • I2C Extended Private Constants
          • I2C Extended Private Macros
          • I2C Extended Private Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
    • I2S
      • I2S Private Functions
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S MCLK Output
        • I2S Audio Frequency
        • I2S FullDuplex Mode
        • I2S MSB LSB Transmission
        • I2S Word Select Inversion
        • Data Padding 24Bit
        • Keep IO State
        • I2S Interrupts Definition
        • I2S Flags Definition
      • I2S Exported Macros
      • I2S Private Constants
      • I2S Private Macros
    • I2SEx
    • IRDA
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA State Code Definition
        • IRDA Error Code Definition
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA Clock Prescaler
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
    • IRDAEx
      • IRDAEx Extended Exported Constants
        • IRDAEx Word Length
      • IRDAEx Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • JPEG
      • JPEG Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • encoding/decoding processing functions
        • JPEG Decode/Encode callback functions
        • JPEG IRQ handler management
        • Peripheral State functions
      • JPEG Exported Types
        • JPEG Configuration for encoding Structure definition
        • HAL JPEG state structure definition
        • JPEG handle Structure definition
        • HAL JPEG Callback ID enumeration definition
        • HAL JPEG Callback pointer definition
      • JPEG Exported Constants
        • JPEG Error Code definition
        • JPEG Quantization Table Size
        • JPEG ColorSpace
        • JPEG Chrominance Sampling
        • JPEG Image Quality
        • JPEG Interrupt configuration definition
        • JPEG Flag definition
        • JPEG Process Pause Resume definition
      • JPEG Exported Macros
      • JPEG Private Types
      • JPEG Private Defines
      • JPEG Private Variables
      • JPEG Private Constants
      • JPEG Private Macros
      • JPEG Private Functions Prototypes
      • JPEG Private Functions
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Private Functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Types
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
    • LTDC
      • LTDC Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • LTDC Private Functions
      • LTDC Exported Types
      • LTDC Exported Constants
        • LTDC Error Code
        • LTDC Layer
        • LTDC HS POLARITY
        • LTDC VS POLARITY
        • LTDC DE POLARITY
        • LTDC PC POLARITY
        • LTDC SYNC
        • LTDC BACK COLOR
        • LTDC Blending Factor1
        • LTDC Blending Factor2
        • LTDC Pixel format
        • LTDC Alpha
        • LTDC LAYER Config
        • LTDC Interrupts
        • LTDC Flags
        • LTDC Reload Type
      • LTDC Exported Macros
      • LTDC Private Macros
    • MDIOS
      • MDIOS Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • MDIOS Exported Types
        • MDIOS State structures definition
        • MDIOS Init Structure definition
        • MDIOS handle Structure definition
      • MDIOS Exported Constants
        • MDIOS Preamble Check
        • MDIOS Input Output Registers Definitions
        • MDIOS Registers Flags
        • Interrupt Sources
        • MDIOS Interrupt Flags
        • MDIOS Error Code
        • MDIOS Wakeup Line
      • MDIOS Exported Macros
      • MDIOS Private Types
      • MDIOS Private Variables
      • MDIOS Private Constants
      • MDIOS Private Macros
      • MDIOS Private Functions
    • MDMA
      • MDMA Exported Types
      • MDMA Exported Constants
        • MDMA Error Codes
        • MDMA Request selection
        • MDMA Transfer Trigger Mode
        • MDMA Priority level
        • MDMA Endianness
        • MDMA Source increment mode
        • MDMA Destination increment mode
        • MDMA Source data size
        • MDMA Destination data size
        • MDMA data alignment
        • MDMA Source burst
        • MDMA Destination burst
        • MDMA interrupt enable definitions
        • MDMA flag definitions
      • MDMA Exported Macros
      • MDMA Exported Functions
        • Initialization and de-initialization functions
        • Linked List operation functions
        • I/O operation functions
        • Peripheral State functions
      • MDMA Private Types
      • MDMA Private Defines
      • MDMA Private Variables
      • MDMA Private Constants
      • MDMA Private Macros
      • MDMA Private Functions Prototypes
      • MDMA Private Functions
    • MMC
      • MMC Private Functions
      • MMC Exported Types
        • MMC State enumeration structure
        • MMC Card State enumeration structure
        • MMC Handle Structure definition
        • Card Specific Data: CSD Register
        • Card Identification Data: CID Register
        • MMC Callback ID enumeration definition
        • MMC Callback pointer definition
      • Exported Constants
        • MMC Error status enumeration Structure definition
        • MMC context enumeration
        • MMC Voltage mode
        • MMC Memory Cards
      • MMC Exported Macros
      • MMC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • MMC card related functions
        • Peripheral State and Errors functions
        • Perioheral Abort management
        • MMC Private Types
        • MMC Private Defines
        • MMC Private Variables
        • MMC Private Constants
        • MMC Private Macros
        • MMC Private Functions Prototypes
        • MMC Private Functions
      • MMC Private Defines
    • MMCEx
      • MMCEx Exported Types
        • MMC Internal DMA Buffer structure
      • MMCEx Exported Functions
        • MultiBuffer functions
    • NAND
      • NAND Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Peripheral Control functions
        • Peripheral State functions
      • NAND Exported Types
      • NAND Exported Macros
      • NAND Private Constants
      • NAND Private Macros
    • NOR
      • NOR Private Defines
      • NOR Private Variables
      • NOR Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • NOR Control functions
        • NOR State functions
      • NOR Exported Types
      • NOR Exported Macros
      • NOR Private Constants
      • NOR Private Macros
    • OPAMP
      • OPAMP Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • OPAMP Exported Types
      • OPAMP Exported Constants
        • OPAMP Mode
        • OPAMP Non Inverting Input
        • OPAMP Inverting Input
        • OPAMP Pga Connect
        • OPAMP Pga Gain
        • OPAMP PowerMode
        • OPAMP VREF
        • OPAMP User Trimming
        • OPAMP Factory Trimming
      • OPAMP Private Constants
      • OPAMP Exported Macros
      • OPAMP Private Macros
    • OSPI
      • OSPI Exported Functions
        • Initialization/de-initialization functions
        • Input and Output operation functions
        • Peripheral Control and State functions
        • IO Manager configuration function
      • OSPI Exported Types
      • OSPI Exported Constants
        • OSPI State
        • OSPI Error Code
        • OSPI Dual-Quad
        • OSPI Memory Type
        • OSPI Free Running Clock
        • OSPI Clock Mode
        • OSPI Wrap-Size
        • OSPI Sample Shifting
        • OSPI Delay Hold Quarter Cycle
        • OSPI Delay Block Bypaas
        • OSPI Operation Type
        • OSPI Flash Id
        • OSPI Instruction Mode
        • OSPI Instruction Size
        • OSPI Instruction DTR Mode
        • OSPI Address Mode
        • OSPI Address Size
        • OSPI Address DTR Mode
        • OSPI Alternate Bytes Mode
        • OSPI Alternate Bytes Size
        • OSPI Alternate Bytes DTR Mode
        • OSPI Data Mode
        • OSPI Data DTR Mode
        • OSPI DQS Mode
        • OSPI SIOO Mode
        • OSPI Hyperbus Write Zero Latency Activation
        • OSPI Hyperbus Latency Mode
        • OSPI Hyperbus Address Space
        • OSPI Match Mode
        • OSPI Automatic Stop
        • OSPI Timeout Activation
        • OSPI Flags
        • OSPI Interrupts
        • OSPI Timeout definition
        • OSPI IO Manager IO Port
      • OSPI Exported Macros
    • OTFDEC
      • OTFDEC_Exported_Functions
        • Initialization and de-initialization functions
        • OTFDEC IRQ handler management
        • Peripheral Control functions
        • Peripheral State and Status functions
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG PCD Callback ID enumeration definition
          • HAL USB OTG PCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • PCD Error Code definition
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PSSI
      • PSSI Private Define
      • PSSI Private Functions
      • PSSI Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • PSSI Exported Types
      • PSSI Exported Constants
        • PSSI Error Code
        • PSSI Data Width
        • PSSI Bus Width
        • PSSI mode
        • Configuration
        • Data Enable Polarity
        • Reday Polarity
        • Clock Polarity
        • PSSI definitions
        • PSSI Interrupts
      • PSSI Exported Macros
    • PWR
      • PWR Exported Functions
        • Initialization and De-Initialization Functions
        • Peripheral Control Functions
        • Interrupt Handling Functions
      • PWR Exported Types
      • PWR Exported Constants
        • PWR PVD detection level
        • PWR PVD Mode
        • PWR Regulator state in SLEEP/STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Regulator Voltage Scale
        • PWR Flag
        • PWR Enable WUP Mask
      • PWR Exported Macro
      • PWR Private Constants
        • PWR PVD Mode Mask
        • PWR PVD EXTI Line
      • PWR Private Macros
        • PWR Private macros to check input parameters
    • PWREx
      • PWREx Exported Functions
        • Power Supply Control Functions
        • Low Power Control Functions
        • Peripherals control functions
        • Power Monitoring functions
      • PWREx Exported Types
      • PWREx Exported Constants
        • PWREx Wake-Up Pins
        • PWREx Pin Polarity configuration
        • PWREx Pin Pull configuration
        • PWREx Wakeup Pins Flags.
        • PWREx Domains definition
        • PWREx Domain Flags definition
        • PWREx D3 Domain State
        • PWREx Supply configuration
        • PWREx AVD detection level
        • PWREx AVD Mode
        • PWREx Regulator Voltage Scale
        • PWR battery charging resistor selection
        • PWREx VBAT Thresholds
        • PWREx Temperature Thresholds
        • PWREx AVD EXTI Line 16
        • Memory shut-off block selection
      • PWREx Exported Macro
      • PWREx Private Macros
        • PWREx Private macros to check input parameters
      • PWREx_Private_Constants
        • PWR Extended AVD Mode Mask
        • PWR Extended Flag Setting Time Out Value
        • PWREx Wake-Up Pins masks and offsets
    • RAMECC
      • RAMECC Exported Types
      • RAMECC Error Codes
      • RAMECC interrupts
      • RAMECC Monitor flags
        • RAMECC Private Functions
      • RAMECC Exported Macros
      • RAMECC Exported Functions
        • Initialization and de-initialization functions
        • monitoring operation functions
          • Error informations functions
          • RAMECC_Exported_Functions_Group4
        • Error informations functions
      • RAMECC Private Constants
      • RAMECC Private Macros
      • monitoring operation functions
        • Error informations functions
        • RAMECC_Exported_Functions_Group4
    • RCC
      • RCC Private Macros
        • RCC Private macros to check input parameters
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • RCC_Exported_Functions_Group2
      • RCC Exported Types
      • RCC Exported Constants
        • RCC Oscillator Type
        • RCC HSE Config
        • RCC LSE Config
        • RCC HSI Config
        • RCC HSI48 Config
        • RCC LSI Config
        • RCC CSI Config
        • RCC PLL Config
        • RCC PLL Clock Source
        • RCC PLL Clock Output
        • RCC PLL1 VCI Range
        • RCC PLL1 VCO Range
        • RCC System Clock Type
        • RCC System Clock Source
        • System Clock Source Status
        • RCC SYS Clock Source
        • RCC HCLK Clock Source
        • RCC APB3 Clock Source
        • RCC APB1 Clock Source
        • RCC APB2 Clock Source
        • RCC APB4 Clock Source
        • RCC RTC Clock Source
        • RCC MCO Index
        • RCC MCO1 Clock Source
        • RCC MCO2 Clock Source
        • RCC MCOx Clock Prescaler
        • RCC Interrupt
        • RCC Flag
        • LSE Drive Config
        • RCC Stop WakeUpClock
        • RCC Stop KernelWakeUpClock
      • RCC Exported Macros
        • LSE Configuration
        • RCC Extended MCOx Clock Config
        • Flags Interrupts Management
      • RCC Private Constants
    • RCCEx
      • Private Defines
      • Exported Functions
        • Extended Peripheral Control functions
        • Extended System Control functions
        • Extended Clock Recovery System Control functions
      • Private Functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • RCCEx Periph Clock Selection
        • RCC PLL2 Clock Output
        • RCC PLL3 Clock Output
        • RCC PLL2 VCI Range
        • RCC PLL2 VCO Range
        • RCC PLL3 VCI Range
        • RCC PLL3 VCO Range
        • RCCEx USART1/6 Clock Source
        • RCCEx USART1 Clock Source
        • RCCEx USART6 Clock Source
        • RCCEx UART9 Clock Source
        • RCCEx USART10 Clock Source
        • RCCEx USART2/3/4/5/7/8 Clock Source
        • RCCEx USART2 Clock Source
        • RCCEx USART3 Clock Source
        • RCCEx UART4 Clock Source
        • RCCEx UART5 Clock Source
        • RCCEx UART7 Clock Source
        • RCCEx UART8 Clock Source
        • RCCEx LPUART1 Clock Source
        • RCCEx I2C1/2/3 Clock Source
        • RCCEx I2C1 Clock Source
        • RCCEx I2C2 Clock Source
        • RCCEx I2C3 Clock Source
        • RCCEx I2C4 Clock Source
        • RCCEx RNG Clock Source
        • RCCEx USB Clock Source
        • SAI1 Clock Source
        • Source SAI2A Clock Source
        • Clock_Source SAI2B Clock Source
        • SPI1/2/3 Clock Source
        • SPI1 Clock Source
        • SPI2 Clock Source
        • SPI3 Clock Source
        • SPI4/5 Clock Source
        • SPI4 Clock Source
        • SPI5 Clock Source
        • SPI6 Clock Source
        • RCCEx LPTIM1 Clock Source
        • RCCEx LPTIM2 Clock Source
        • RCCEx LPTIM3/4/5 Clock Source
        • RCCEx LPTIM3 Clock Source
        • RCCEx OSPI Clock Source
        • RCCEx FMC Clock Source
        • RCCEx FDCAN Clock Source
        • RCCEx SDMMC Clock Source
        • RCCEx ADC Clock Source
        • RCCEx SWPMI1 Clock Source
        • RCCEx DFSDM1 Clock Source
        • RCCEx DFSDM2 Clock Source
        • RCCEx SPDIFRX Clock Source
        • RCCEx CEC Clock Source
        • RCCEx CLKP Clock Source
        • RCCEx TIM Prescaler Selection
        • RCCEx RCC WWDGx
        • RCCEx CRS Status
        • RCCEx CRS SynchroSource
        • RCCEx CRS SynchroDivider
        • RCCEx CRS SynchroPolarity
        • RCCEx CRS ReloadValueDefault
        • RCCEx CRS ErrorLimitDefault
        • RCCEx CRS HSI48CalibrationDefault
        • RCCEx CRS FreqErrorDirection
        • RCCEx CRS Interrupt Sources
        • RCCEx CRS Flags
      • RCCEx Private Macros
        • RCC Private macros to check input parameters
      • RCCEx Exported Macros
      • RCCEx CRS Extended Features
    • RNG
      • RNG_Private_Defines
      • RNG Private Constants
      • RNG Exported Types
        • RNG Init Structure definition
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
        • RNG Clock Error Detection
        • RNG Error Definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and configuration functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Macros
    • RNGEx
      • RNGEx_Private_Defines
      • RNG Private Constants
      • RNGEx Exported Types
      • RNGEX Exported Constants
        • Value used to configure an internal
        • NIST Compliance configuration
      • RNGEx Private Types
      • RNGEx Private Variables
      • RNGEx Private Macros
      • RNGEx Private Functions
      • RNGEx Exported Functions
        • RNGEx_Exported_Functions_Group1
    • RTC
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats Definitions
        • RTC Output Selection Definitions
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output Pull-Up ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLight Saving Definitions
        • RTC Store Operation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions (in BCD format)
        • RTC WeekDay Definitions
        • RTC Alarm Date WeekDay Definitions
        • RTC Alarm Mask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
        • RTC Clear Flags Definitions
      • RTC Exported Macros
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Exported Types
        • RTC Tamper structure definition
        • RTCEx Internal Tamper structure definition
        • Seed size Definitions
        • Active Tampers number Definitions
        • RTC Active Tamper structures definitions
      • RTCEx Exported Constants
        • RTC Backup Registers Number Definitions
        • RTC Backup Registers Definitions
        • RTC TimeStamp Edges Definitions
        • RTC TimeStamp Pin Selection
        • RTC Tamper Pins Definitions
        • RTC Tamper Interrupts Definitions
        • RTC Internal Tamper Pins Definition
        • RTC Internal Tamper Interrupt
        • RTC Tamper Triggers Definitions
        • RTC Tamper EraseBackUp Definitions
        • RTC Tamper Mask Flag Definitions
        • RTC Tamper Filter Definitions
        • RTC Tamper Sampling Frequencies Definitions
        • RTC Tamper Pin Precharge Duration Definitions
        • RTC Tamper TimeStamp On Tamper Detection Definitions
        • RTC Tamper Pull Up Definitions
        • RTC Tamper Detection Ouput Definitions
        • RTC Tamper Flags Definitions
        • RTCEx_ActiveTamper_Enable Definitions
        • RTCEx_ActiveTamper_Interrupt Definitions
        • RTCEx_ActiveTamper_Filter Definitions
        • RTC Active_Tamper_Asynchronous_Prescaler clock Definitions
        • RTC Active Tamper selection Definition
        • RTC Tamper Registers Offset
        • RTC Wakeup Timer Definitions
        • RTC Smooth Calib Period Definitions
        • RTC Smooth Calib Plus pulses Definitions
        • RTC Calib Output Selection Definitions
        • RTC Add 1 Second Parameter Definitions
      • RTCEx Exported Macros
      • RTCEx Exported Functions
        • Extended RTC TimeStamp functions
        • Extended RTC Tamper functions
        • Extended RTC Wake-up functions
        • Extended RTC Backup register functions
        • Extended Peripheral Control functions
        • Extended features functions
      • RTCEx Private Constants
      • RTCEx Private Macros
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Private Functions
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
        • SAI PDM Structure definition
        • SAI Init Structure definition
        • SAI Frame Structure definition
        • SAI Slot Structure definition
        • SAI Handle Structure definition
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Block Master Clock Output
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Audio Frequency
        • SAI Block Master Clock OverSampling
        • SAI PDM Clock Enable
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI_Private_Macros
    • SAIEx
      • SAIEx Extended Exported Functions
        • Peripheral Control functions
      • SAIEx Exported Types
      • SAIEx Extended Private Macros
    • SD
      • SD Private Functions
      • SD Exported Types
        • SD State enumeration structure
        • SD Card State enumeration structure
        • SD Handle Structure definition
        • Card Specific Data: CSD Register
        • Card Identification Data: CID Register
        • SD Card Status returned by ACMD13
        • SD Callback ID enumeration definition
        • SD Callback pointer definition
      • Exported Constants
        • SD Error status enumeration Structure definition
        • SD context enumeration
        • SD Supported Memory Cards
        • SD Supported Version
      • SD Exported Macros
      • SD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • SD card related functions
        • Peripheral State and Errors functions
        • Perioheral Abort management
        • SD Private Types
        • SD Private Defines
        • SD Private Variables
        • SD Private Constants
        • SD Private Macros
        • SD Private Functions Prototypes
        • SD Private Functions
      • SD Private Defines
    • SDEx
      • SDEx Exported Types
        • SD Card Internal DMA Buffer structure
      • SDEx Exported Functions
        • MultiBuffer functions
    • SDRAM
      • SDRAM Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Control functions
        • State functions
      • SDRAM Exported Types
      • SDRAM Exported Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD State Code Definition
        • SMARTCARD Error Code Definition
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD Clock Prescaler
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Private Constants
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
        • Extended Peripheral IO operation functions
        • Extended Peripheral FIFO Control functions
      • SMARTCARD Extended Private Functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARD FIFO mode
        • SMARTCARD TXFIFO threshold level
        • SMARTCARD RXFIFO threshold level
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS ownaddress2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SPDIFRX
      • SPDIFRX Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPDIFRX Exported Types
      • SPDIFRX Exported Constants
        • SPDIFRX Error Code
        • SPDIFRX Input Selection
        • SPDIFRX Maximum Retries
        • SPDIFRX Wait For Activity
        • SPDIFRX Preamble Type Mask
        • SPDIFRX Channel Status Mask
        • SPDIFRX Validity Mask
        • SPDIFRX Parity Error Mask
        • SPDIFRX Channel Selection
        • SPDIFRX Data Format
        • SPDIFRX Stereo Mode
        • SPDIFRX State
        • SPDIFRX Interrupts Definition
        • SPDIFRX Flags Definition
      • SPDIFRX Exported Macros
      • SPDIFRX Private Macros
      • SPDIFRX Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI FIFO Type
        • SPI Error Codes
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI Fifo Threshold
        • SPI CRC Calculation Initialization Pattern
        • SPI NSS Polarity
        • Keep IO State
        • Control SPI IO Swap
        • SPI Master SS Idleness
        • SPI Master Inter-Data Idleness
        • SPI Master Receiver AutoSuspend
        • SPI Underrun Detection
        • SPI Underrun Behavior
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Exported Functions
        • IO operation functions
    • SRAM
      • SRAM Exported Functions
        • Initialization and de-initialization functions
        • Input Output and memory control functions
        • Control functions
        • Peripheral State functions
      • SRAM Exported Types
      • SRAM Exported Macros
    • SWPMI
      • SWPMI Exported Functions
        • Initialization/de-initialization methods
        • IO operation methods
        • SWPMI IRQ handler and callbacks
        • Peripheral Control methods
      • SWPMI Private Functions
      • SWPMI Exported Types
      • SWPMI Exported Constants
        • SWPMI Error Code Bitmap
        • SWPMI Voltage Class
        • SWPMI Tx Buffering Mode
        • SWPMI Rx Buffering Mode
        • SWPMI Status Flags
        • SWPMI Interrupts Definition
      • SWPMI Exported Macros
      • SWPMI Private Types
      • SWPMI Private Variables
      • SWPMI Private Constants
      • SWPMI Private Macros
    • TIM
      • TIM Exported Functions
        • TIM Time Base functions
        • TIM Output Compare functions
        • TIM PWM functions
        • TIM Input Capture functions
        • TIM One Pulse functions
        • TIM Encoder functions
        • TIM IRQ handler management
        • TIM Peripheral Control functions
        • TIM Callbacks functions
        • TIM Peripheral State functions
      • TIM Private Functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Clear Input Source
        • TIM DMA Base Address
        • TIM Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Encoder Input Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Flag Definition
        • TIM Channel
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Break input 2 Enable
        • TIM Break Input 2 Polarity
        • TIM Automatic Output Enable
        • Group Channel 5 and Channel 1, 2 or 3
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Output Compare and PWM Modes
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
        • TIM Break System
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
    • TIMEx
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIMEx Private Functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Remapping
        • TIM Extended Break input
        • TIM Extended Break input source
        • TIM Extended Break input source enabling
        • TIM Extended Break input polarity
        • TIM Extended Timer input selection
      • TIM Extended Exported Macros
      • TIM Extended Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART State Code Definition
        • UART Error Definition
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Clock Prescaler
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver Timeout
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
      • UART Exported Macros
      • UART Private Macros
    • UARTEx
      • UARTEx Private Constants
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UARTEx Word Length
        • UARTEx WakeUp Address Length
        • UARTEx FIFO mode
        • UARTEx TXFIFO threshold level
        • UARTEx RXFIFO threshold level
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Definition
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Over Sampling
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Clock Prescaler
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • USARTEx
      • USARTEx Private Constants
      • USARTEx Private Functions
      • USARTEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • USARTEx Exported Constants
        • USARTEx Word Length
        • USARTEx Slave Select Management
        • USARTEx Synchronous Slave mode enable
        • USARTEx FIFO mode
        • USARTEx TXFIFO threshold level
        • USARTEx RXFIFO threshold level
      • USARTEx Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
    • DELAYBLOCK_LL
      • Delay Block Low Layer Exported Functions
        • Initialization de-initialization functions
      • DELAYBLOCK_LL Exported Types
      • Delay Block Exported Constants
      • Delay Block functions
    • GPIOEx
      • GPIO Exported Constants
        • GPIO Alternate Function Selection
      • GPIO Exported Macros
      • GPIO Exported Functions
      • GPIO Private Constants
      • GPIO Private Macros
        • GPIO Get Port Index
        • GPIO Check Alternate Function
      • GPIO Private Functions
    • OPAMPEx
      • OPAMPEx Exported Functions
        • OPAMPEx_Exported_Functions_Group1
        • Peripheral Control functions
  • STM32H7xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Clock source
        • ADC common - Measurement path to internal channels
        • ADC instance - Boost mode
        • ADC instance - Calibration mode for offset and linearity
        • ADC instance - Calibration linearity words
        • ADC instance - Resolution
        • ADC left Shift
        • ADC instance - Low power mode
        • ADC instance - Offset number
        • ADC instance - Offset signed saturation mode
        • ADC instance - Offset right shift
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - Data transfer mode of ADC conversion data
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Context queue mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Channel - Single or differential ending
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Oversampling - Oversampling scope
        • Oversampling - Discontinuous mode
        • Oversampling - Data shift
        • Multimode - Mode
        • Multimode - DMA transfer
        • Multimode - Delay between two sampling phases
        • Multimode - ADC master or slave
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC transversal scope: oversampling
        • Configuration of ADC hierarchical scope: multimode
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BDMA
      • BDMA Private Variables
      • BDMA Exported Init structure
      • BDMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • DOUBLE BUFFER MODE
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
        • CURRENTTARGETMEM
        • BDMA Exported Macros
          • Common Write and read registers macros
          • Convert BDMAxChannely
        • BDMA Exported Functions
          • Configuration
          • FLAG_Management
          • IT_Management
          • Initialization and de-initialization functions
      • BDMA_LL_Private_Macros
      • BDMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB3 GRP1 PERIPH
        • AHB1 GRP1 PERIPH
        • AHB2 GRP1 PERIPH
        • AHB4 GRP1 PERIPH
        • APB3 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB1 GRP2 PERIPH
        • APB2 GRP1 PERIPH
        • APB4 GRP1 PERIPH
        • CLKAM PERIPH
        • CKGA (AXI Clocks Gating) PERIPH
        • BUS Exported Functions
          • AHB3
          • AHB1
          • AHB2
          • AHB4
          • APB3
          • APB1
          • APB2
          • APB4
          • BUS_LL_EF_CLKAM
    • COMP
      • COMP Private Constants
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator common modes - Window mode
        • Comparator modes - Power mode
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator input - Hysteresis
        • Comparator output - Output polarity
        • Comparator output - Blanking source
        • Comparator output - Output level
        • Comparator output - Output to BKIN timer
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of COMP hierarchical scope: common to several COMP instances
        • Configuration of comparator modes
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Operation on comparator instance
        • Initialization and de-initialization functions
      • COMP_LL_Private_Macros
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • CRS
      • CRS Exported Constants
        • Get Flags Defines
        • IT Defines
        • Synchronization Signal Divider
        • Synchronization Signal Source
        • Synchronization Signal Polarity
        • Frequency Error Direction
        • Default Values
      • CRS Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Calculate_Reload
      • CRS Exported Functions
        • Configuration
        • CRS_Management
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DAC
      • DAC Private Constants
      • DAC Private Macros
      • DAC Exported Init structure
      • DAC Exported Constants
        • DAC flags
        • DAC interruptions
        • DAC channels
        • DAC operating mode
        • DAC trigger source
        • DAC waveform automatic generation mode
        • DAC wave generation - Noise LFSR unmask bits
        • DAC wave generation - Triangle amplitude
        • DAC channel output mode
        • DAC channel output buffer
        • DAC channel output connection
        • DAC literals legacy naming
        • DAC channel output resolution
        • DAC registers compliant with specific purpose
        • Definitions of DAC hardware constraints delays
      • DAC Exported Macros
        • Common write and read registers macros
        • DAC helper macro
      • DAC Exported Functions
        • Configuration of DAC channels
        • DMA Management
        • Operation on DAC channels
        • FLAG Management
        • IT management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Exported Init structure
      • DMA Exported Constants
        • STREAM
        • DIRECTION
        • MODE
        • DOUBLE BUFFER MODE
        • PERIPH
        • MEMORY
        • PDATAALIGN
        • MDATAALIGN
        • OFFSETSIZE
        • PRIORITY
        • MBURST
        • PBURST
        • DMA_LL_FIFOMODE
        • FIFOSTATUS 0
        • FIFOTHRESHOLD
        • CURRENTTARGETMEM
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxStreamy
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
      • DMA_LL_Private_Macros
    • DMA2D
      • DMA2D Private Macros
      • DMA2D Exported Init structures
      • DMA2D Exported Constants
        • Get Flags Defines
        • IT Defines
        • Mode
        • Output Color Mode
        • Input Color Mode
        • Alpha Mode
        • Swap Mode
        • Red Blue Swap
        • Alpha Inversion
        • Line Offset Mode
        • CLUT Color Mode
        • Chroma Sub Sampling
      • DMA2D Exported Macros
        • Common Write and read registers Macros
      • DMA2D Exported Functions
        • Configuration Functions
          • Foreground Configuration Functions
          • Background Configuration Functions
        • Flag Management
        • Interruption Management
        • Initialization and De-initialization Functions
      • DMA2D Private Constants
    • DMAMUX
      • DMAMUX Private Constants
      • DMAMUX Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • DMAMUX Request selection
        • DMAMUX Channel
        • Synchronization Signal Polarity
        • Synchronization Signal Event
        • Request Generator Channel
        • External Request Signal Generation Polarity
        • External Request Signal Generation
      • DMAMUX Exported Macros
        • Common Write and read registers macros
      • DMAMUX Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
        • D3 Pend Clear Source
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • HSEM
      • HSEM Exported Constants
        • COREID Defines
        • Get Flags Defines
      • HSEM Exported Macros
        • Common Write and read registers Macros
      • HSEM Exported Functions
        • Data_Management
        • IT_Management
        • FLAG_Management
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • LPTIM
      • LPTIM Private Functions
      • LPTIM Private Macros
      • LPTIM Exported Init structure
      • LPTIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operating Mode
        • Update Mode
        • Counter Mode
        • Output Waveform Type
        • Output Polarity
        • Prescaler Value
        • Trigger Source
        • Trigger Filter
        • Trigger Polarity
        • Clock Source
        • Clock Filter
        • Clock Polarity
        • Encoder Mode
        • Input1 Source
        • Input2 Source
      • LPTIM Exported Macros
        • Common Write and read registers Macros
      • LPTIM Exported Functions
        • Initialisation and deinitialisation functions
        • LPTIM Configuration
        • Trigger Configuration
        • Clock Configuration
        • Encoder Mode
        • FLAG Management
        • Interrupt Management
    • LPUART
      • LPUART Private Variables
      • LPUART Private Constants
      • LPUART Private Macros
      • LPUART Exported Init structures
      • LPUART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • Driver Enable Polarity
        • DMA Register Data
      • LPUART Exported Macros
        • Common Write and read registers Macros
        • Helper Macros
      • LPUART Exported Functions
        • Configuration functions
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to Driver Enable feature
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • MDMA
      • MDMA Private Variables
      • MDMA Private Constants
      • MDMA Exported Init structure
      • MDMA Exported Constants
        • CHANNEL
        • Word Endianness
        • Half Word Endianness
        • Byte Endianness
        • Transfer Priority level
        • Bufferable Write Mode
        • Request Mode
        • Trigger Mode
        • Padding Alignment Mode
        • Transfer Packing
        • Transfer Destination Burst
        • Transfer Source Burst
        • Destination Increment Offset Size
        • Source Increment Offset Size
        • Destination Data Size
        • Source Data Size
        • Destination Increment Mode
        • Source Increment Mode
        • Block Repeat Destination address Update Mode
        • Source Block Repeat address Update Mode
        • Destination BUS Selection
        • Source BUS Selection
        • HW Trigger Selection
        • Transfer Error Direction
      • MDMA Exported Macros
        • Common Write and read registers macros
        • Convert MDMAxChannely
      • MDMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
      • MDMA_LL_Private_Macros
    • OPAMP
      • OPAMP Private Constants
      • OPAMP Private Macros
      • OPAMP Exported Init structure
      • OPAMP Exported Constants
        • OPAMP mode calibration or functional.
        • OPAMP functional mode
        • OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
        • OPAMP input non-inverting
        • OPAMP input inverting
        • OPAMP PowerMode
        • OPAMP trimming mode
        • OPAMP trimming of transistors differential pair NMOS or PMOS
        • Definitions of OPAMP hardware constraints delays
      • OPAMP Exported Macros
        • Common write and read registers macro
        • OPAMP helper macro
      • OPAMP Exported Functions
        • Configuration of OPAMP hierarchical scope: OPAMP instance
        • Configuration of OPAMP inputs
        • Configuration and operation of OPAMP trimming
        • Operation on OPAMP instance
        • Initialization and de-initialization functions
    • PWR
      • PWR Private Constants
        • Wake-Up Pins register offsets Defines
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • Power mode
        • Run mode Regulator Voltage Scaling
        • Stop mode Regulator Voltage Scaling
        • Regulator Mode In Deep Sleep Mode
        • Power Digital Voltage Level Detector
        • Power Analog Voltage Level Detector
        • Battery Charge Resistor
        • Wakeup Pins
        • Wakeup Pins pull configuration
        • Power supply source configuration
      • PWR Exported Macros
        • Common write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
          • De-initialization function
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Variables
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • HSI oscillator divider
        • LSE oscillator drive capability
        • System clock switch
        • System clock switch status
        • System wakeup clock source
        • Kernel wakeup clock source
        • System prescaler
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB low-speed prescaler (APB2)
        • APB low-speed prescaler (APB3)
        • APB low-speed prescaler (APB4)
        • MCO source selection
        • MCO prescaler
        • HSE prescaler for RTC clock
        • Peripheral USART clock source selection
        • Peripheral LPUART clock source selection
        • Peripheral I2C clock source selection
        • Peripheral LPTIM clock source selection
        • Peripheral SAI clock source selection
        • Peripheral SDMMC clock source selection
        • Peripheral RNG clock source selection
        • Peripheral USB clock source selection
        • Peripheral CEC clock source selection
        • Peripheral DFSDM clock source selection
        • Peripheral DFSDM2 clock source selection
        • Peripheral FMC clock source selection
        • Peripheral OSPI clock source selection
        • Peripheral CLKP clock source selection
        • Peripheral SPI clock source selection
        • Peripheral SPDIF clock source selection
        • Peripheral FDCAN clock source selection
        • Peripheral SWP clock source selection
        • Peripheral ADC clock source selection
        • RTC clock source selection
        • Timers clocks prescalers selection
        • All PLLs entry clock source
        • All PLLs input range
        • All PLLs VCO range
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
        • Peripheral clock frequency
      • RCC Exported Functions
        • HSE
        • HSI
        • CSI
        • HSI48
        • CPUCKREADY
        • CDCKREADY
        • RESET
        • LSE
        • LSI
        • System
        • MCO
        • Peripheral Clock Source
        • RTC
        • TIM
        • PLL
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • RNG
      • RNG Exported Init structures
      • RNG Exported Constants
        • Clock Error Detection
        • Value used to configure an internal
        • NIST Compliance configuration
        • Get Flags Defines
        • IT Defines
      • RNG Exported Macros
        • Common Write and read registers Macros
      • RNG Exported Functions
        • RNG Configuration functions
        • FLAG Management
        • IT Management
        • Data Management
        • Health Test Control
        • Initialization and de-initialization functions
      • RNG_LL_Private_Macros
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • ACTIVE TAMPER MODE
        • ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
        • ACTIVE TAMPER OUTPUT SELECTION
        • WAKEUP CLOCK DIV
        • BACKUP
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • RTC Exported Macros
        • Common Write and read registers Macros
        • Convert helper Macros
        • Date helper Macros
        • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Time-stamp on Tamper
        • Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Active Tamper
        • Initialization and de-initialization functions
    • SPI
      • SPI Private Macros
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Mode
        • SS Level
        • SS Idleness
        • Master Inter-Data Idleness
        • TXCRC Init All
        • RXCRC Init All
        • UDR Config Register
        • UDR Detect Begin Data
        • Protocol
        • Phase
        • Polarity
        • NSS Polarity
        • Baud Rate Prescaler
        • Bit Order
        • Transfer Mode
        • Data Width
        • FIFO Threshold
        • CRC Calculation
        • CRC
        • NSS Mode
        • RxFIFO Packing LeVel
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • DMA Management
        • DATA_Management
        • Initialization and de-initialization functions
      • I2S
        • I2S Private Constants
        • I2S Private Macros
        • I2S Exported Init structure
        • I2S Exported Constants
          • Data Format
          • Type of Channel Length
          • Clock Polarity
          • I2S Standard
          • Operation Mode
          • Prescaler Factor
          • FIFO Threshold Level
          • Transmission Bit Order
          • MCLK Output
          • Audio Frequency
        • I2S Exported Macros
          • Common Write and read registers Macros
        • I2S Exported Functions
          • Configuration
          • FLAG_Management
          • IT_Management
          • DMA_Management
          • DATA_Management
          • Initialization and de-initialization functions
          • I2S_LL_EF_Init
    • SWPMI
      • SWPMI Private Macros
      • SWPMI Exported Init structure
      • SWPMI Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • SW BUFFER RX
        • SW BUFFER TX
        • VOLTAGE CLASS
        • DMA register data
      • SWPMI Exported Macros
        • Common Write and read registers Macros
        • Bit rate calculation helper Macros
      • SWPMI Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
        • SYSCFG Flash Bank1 sectors bits status
        • SYSCFG Flash Bank2 sectors bits status
      • SYSTEM Exported Constants
        • SYSCFG I2C FASTMODEPLUS
        • Analog Switch control
        • SYSCFG EXTI PORT
        • SYSCFG EXTI LINE
        • SYSCFG TIMER BREAK
        • SYSCFG I/O compensation cell Code selection
        • SYSCFG IWDG1 control modes
        • SYSCFG DTCM RAM size configuration
        • SYSCFG Brownout Reset Threshold Level
        • DBGMCU TRACE Pin Assignment
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB1 GRP2 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • DBGMCU APB3 GRP1 STOP IP
        • DBGMCU APB4 GRP1 STOP IP
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Break2 Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • GROUPCH5
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Trigger Output 2
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • break polarity
        • break filter
        • BREAK2 POLARITY
        • BREAK2 FILTER
        • OSSI
        • OSSR
        • BREAK INPUT
        • BKIN SOURCE
        • BKIN POLARITY
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM1 Timer Input Ch1 Remap
        • TIM8 Timer Input Ch1 Remap
        • TIM2 Timer Input Ch4 Remap
        • TIM3 Timer Input Ch1 Remap
        • TIM5 Timer Input Ch1 Remap
        • TIM12 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch2 Remap
        • TIM16 Timer Input Ch1 Remap
        • TIM17 Timer Input Ch1 Remap
        • TIM23 Timer Input Ch4 Remap
        • TIM24 Timer Input Ch1 Remap
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Timer input remapping
        • FLAG-Management
        • IT-Management
        • DMA-Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • USART
      • USART Private Variables
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to SPI Slave feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
        • PACKAGE TYPE
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
    • I2S
      • I2S Private Constants
      • I2S Private Macros
      • I2S Exported Init structure
      • I2S Exported Constants
        • Data Format
        • Type of Channel Length
        • Clock Polarity
        • I2S Standard
        • Operation Mode
        • Prescaler Factor
        • FIFO Threshold Level
        • Transmission Bit Order
        • MCLK Output
        • Audio Frequency
      • I2S Exported Macros
        • Common Write and read registers Macros
      • I2S Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • DATA_Management
        • Initialization and de-initialization functions
        • I2S_LL_EF_Init
Generated on Tue Nov 12 2019 18:50:43 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal.c
00004   * @author  MCD Application Team
00005   * @brief   HAL module driver.
00006   *          This is the common part of the HAL initialization
00007   *
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The common HAL driver contains a set of generic and common APIs that can be
00014     used by the PPP peripheral drivers and the user to start using the HAL.
00015     [..]
00016     The HAL contains two APIs' categories:
00017          (+) Common HAL APIs
00018          (+) Services HAL APIs
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00025   * All rights reserved.</center></h2>
00026   *
00027   * This software component is licensed by ST under BSD 3-Clause license,
00028   * the "License"; You may not use this file except in compliance with the
00029   * License. You may obtain a copy of the License at:
00030   *                        opensource.org/licenses/BSD-3-Clause
00031   *
00032   ******************************************************************************
00033   */
00034
00035 /* Includes ------------------------------------------------------------------*/
00036 #include "stm32h7xx_hal.h"
00037
00038 /** @addtogroup STM32H7xx_HAL_Driver
00039   * @{
00040   */
00041
00042 /** @defgroup HAL  HAL
00043   * @brief HAL module driver.
00044   * @{
00045   */
00046
00047 /* Private typedef -----------------------------------------------------------*/
00048 /* Private define ------------------------------------------------------------*/
00049 /**
00050  * @brief STM32H7xx HAL Driver version number V1.7.0RC2
00051    */
00052 #define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
00053 #define __STM32H7xx_HAL_VERSION_SUB1   (0x07UL) /*!< [23:16] sub1 version */
00054 #define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
00055 #define __STM32H7xx_HAL_VERSION_RC     (0x02UL) /*!< [7:0]  release candidate */
00056 #define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
00057                                         |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
00058                                         |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
00059                                         |(__STM32H7xx_HAL_VERSION_RC))
00060
00061 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
00062 #define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
00063
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Exported variables --------------------------------------------------------*/
00067
00068 /** @defgroup HAL_Exported_Variables HAL Exported Variables
00069   * @{
00070   */
00071 __IO uint32_t uwTick;
00072 uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
00073 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
00074 /**
00075   * @}
00076   */
00077
00078 /* Private function prototypes -----------------------------------------------*/
00079 /* Private functions ---------------------------------------------------------*/
00080
00081 /** @defgroup HAL_Private_Functions  HAL Private Functions
00082   * @{
00083   */
00084
00085 /** @defgroup HAL_Group1 Initialization and de-initialization Functions
00086  *  @brief    Initialization and de-initialization functions
00087  *
00088 @verbatim
00089  ===============================================================================
00090               ##### Initialization and de-initialization functions #####
00091  ===============================================================================
00092     [..]  This section provides functions allowing to:
00093       (+) Initializes the Flash interface the NVIC allocation and initial clock
00094           configuration. It initializes the systick also when timeout is needed
00095           and the backup domain when enabled.
00096       (+) De-Initializes common part of the HAL.
00097       (+) Configure The time base source to have 1ms time base with a dedicated
00098           Tick interrupt priority.
00099         (++) SysTick timer is used by default as source of time base, but user
00100              can eventually implement his proper time base source (a general purpose
00101              timer for example or other time source), keeping in mind that Time base
00102              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00103              handled in milliseconds basis.
00104         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00105              at the beginning of the program after reset by HAL_Init() or at any time
00106              when clock is configured, by HAL_RCC_ClockConfig().
00107         (++) Source of time base is configured  to generate interrupts at regular
00108              time intervals. Care must be taken if HAL_Delay() is called from a
00109              peripheral ISR process, the Tick interrupt line must have higher priority
00110             (numerically lower) than the peripheral interrupt. Otherwise the caller
00111             ISR process will be blocked.
00112        (++) functions affecting time base configurations are declared as __weak
00113              to make  override possible  in case of other  implementations in user file.
00114 @endverbatim
00115   * @{
00116   */
00117
00118 /**
00119   * @brief  This function is used to initialize the HAL Library; it must be the first
00120   *         instruction to be executed in the main program (before to call any other
00121   *         HAL function), it performs the following:
00122   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00123   *           which is clocked by the HSI (at this stage, the clock is not yet
00124   *           configured and thus the system is running from the internal HSI at 16 MHz).
00125   *           Set NVIC Group Priority to 4.
00126   *           Calls the HAL_MspInit() callback function defined in user file
00127   *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
00128   *
00129   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00130   *         need to ensure that the SysTick time base is always set to 1 millisecond
00131   *         to have correct HAL operation.
00132   * @retval HAL status
00133   */
00134 HAL_StatusTypeDef HAL_Init(void)
00135 {
00136
00137 #if defined(DUAL_CORE) && defined(CORE_CM4)
00138    /* Configure Cortex-M4 Instruction cache through ART accelerator */
00139    __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
00140    __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
00141    __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
00142 #endif /* DUAL_CORE &&  CORE_CM4 */
00143
00144   /* Set Interrupt Group Priority */
00145   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00146
00147   /* Update the SystemCoreClock global variable */
00148 #if defined(RCC_D1CFGR_D1CPRE)
00149   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
00150 #else
00151   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
00152 #endif
00153
00154   /* Update the SystemD2Clock global variable */
00155 #if defined(RCC_D1CFGR_HPRE)
00156   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
00157 #else
00158   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
00159 #endif
00160
00161   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00162   if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
00163   {
00164     return HAL_ERROR;
00165   }
00166
00167   /* Init the low level hardware */
00168   HAL_MspInit();
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  This function de-Initializes common part of the HAL and stops the systick.
00176   *         This function is optional.
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_DeInit(void)
00180 {
00181   /* Reset of all peripherals */
00182   __HAL_RCC_AHB3_FORCE_RESET();
00183   __HAL_RCC_AHB3_RELEASE_RESET();
00184
00185   __HAL_RCC_AHB1_FORCE_RESET();
00186   __HAL_RCC_AHB1_RELEASE_RESET();
00187
00188   __HAL_RCC_AHB2_FORCE_RESET();
00189   __HAL_RCC_AHB2_RELEASE_RESET();
00190
00191   __HAL_RCC_AHB4_FORCE_RESET();
00192  __HAL_RCC_AHB4_RELEASE_RESET();
00193
00194   __HAL_RCC_APB3_FORCE_RESET();
00195   __HAL_RCC_APB3_RELEASE_RESET();
00196
00197   __HAL_RCC_APB1L_FORCE_RESET();
00198   __HAL_RCC_APB1L_RELEASE_RESET();
00199
00200   __HAL_RCC_APB1H_FORCE_RESET();
00201   __HAL_RCC_APB1H_RELEASE_RESET();
00202
00203    __HAL_RCC_APB2_FORCE_RESET();
00204    __HAL_RCC_APB2_RELEASE_RESET();
00205
00206   __HAL_RCC_APB4_FORCE_RESET();
00207   __HAL_RCC_APB4_RELEASE_RESET();
00208
00209   /* De-Init the low level hardware */
00210   HAL_MspDeInit();
00211
00212   /* Return function status */
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  Initializes the MSP.
00218   * @retval None
00219   */
00220 __weak void HAL_MspInit(void)
00221 {
00222   /* NOTE : This function Should not be modified, when the callback is needed,
00223             the HAL_MspInit could be implemented in the user file
00224    */
00225 }
00226
00227 /**
00228   * @brief  DeInitializes the MSP.
00229   * @retval None
00230   */
00231 __weak void HAL_MspDeInit(void)
00232 {
00233   /* NOTE : This function Should not be modified, when the callback is needed,
00234             the HAL_MspDeInit could be implemented in the user file
00235    */
00236 }
00237
00238 /**
00239   * @brief This function configures the source of the time base.
00240   *        The time source is configured  to have 1ms time base with a dedicated
00241   *        Tick interrupt priority.
00242   * @note This function is called  automatically at the beginning of program after
00243   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00244   * @note In the default implementation, SysTick timer is the source of time base.
00245   *       It is used to generate interrupts at regular time intervals.
00246   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00247   *       The the SysTick interrupt must have higher priority (numerically lower)
00248   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00249   *       The function is declared as __weak  to be overwritten  in case of other
00250   *       implementation  in user file.
00251   * @param TickPriority: Tick interrupt priority.
00252   * @retval HAL status
00253   */
00254 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00255 {
00256   /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
00257   if((uint32_t)uwTickFreq == 0UL)
00258   {
00259     return HAL_ERROR;
00260   }
00261
00262 #if defined(DUAL_CORE)
00263   if (HAL_GetCurrentCPUID() == CM7_CPUID)
00264   {
00265     /* Cortex-M7 detected */
00266     /* Configure the SysTick to have interrupt in 1ms time basis*/
00267     if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
00268     {
00269       return HAL_ERROR;
00270     }
00271   }
00272   else
00273   {
00274     /* Cortex-M4 detected */
00275     /* Configure the SysTick to have interrupt in 1ms time basis*/
00276     if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
00277     {
00278       return HAL_ERROR;
00279     }
00280   }
00281 #else
00282   /* Configure the SysTick to have interrupt in 1ms time basis*/
00283   if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
00284   {
00285     return HAL_ERROR;
00286   }
00287 #endif
00288
00289   /* Configure the SysTick IRQ priority */
00290   if (TickPriority < (1UL << __NVIC_PRIO_BITS))
00291   {
00292     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
00293     uwTickPrio = TickPriority;
00294   }
00295   else
00296   {
00297     return HAL_ERROR;
00298   }
00299
00300   /* Return function status */
00301   return HAL_OK;
00302 }
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup HAL_Group2 HAL Control functions
00309  *  @brief    HAL Control functions
00310  *
00311 @verbatim
00312  ===============================================================================
00313                       ##### HAL Control functions #####
00314  ===============================================================================
00315     [..]  This section provides functions allowing to:
00316       (+) Provide a tick value in millisecond
00317       (+) Provide a blocking delay in millisecond
00318       (+) Suspend the time base source interrupt
00319       (+) Resume the time base source interrupt
00320       (+) Get the HAL API driver version
00321       (+) Get the device identifier
00322       (+) Get the device revision identifier
00323       (+) Enable/Disable Debug module during SLEEP mode
00324       (+) Enable/Disable Debug module during STOP mode
00325       (+) Enable/Disable Debug module during STANDBY mode
00326
00327 @endverbatim
00328   * @{
00329   */
00330
00331 /**
00332   * @brief This function is called to increment  a global variable "uwTick"
00333   *        used as application time base.
00334   * @note In the default implementation, this variable is incremented each 1ms
00335   *       in Systick ISR.
00336  * @note This function is declared as __weak to be overwritten in case of other
00337   *      implementations in user file.
00338   * @retval None
00339   */
00340 __weak void HAL_IncTick(void)
00341 {
00342   uwTick += (uint32_t)uwTickFreq;
00343 }
00344
00345 /**
00346   * @brief Provides a tick value in millisecond.
00347   * @note This function is declared as __weak to be overwritten in case of other
00348   *       implementations in user file.
00349   * @retval tick value
00350   */
00351 __weak uint32_t HAL_GetTick(void)
00352 {
00353   return uwTick;
00354 }
00355
00356 /**
00357   * @brief This function returns a tick priority.
00358   * @retval tick priority
00359   */
00360 uint32_t HAL_GetTickPrio(void)
00361 {
00362   return uwTickPrio;
00363 }
00364
00365 /**
00366   * @brief Set new tick Freq.
00367   * @retval Status
00368   */
00369 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
00370 {
00371   HAL_StatusTypeDef status  = HAL_OK;
00372   HAL_TickFreqTypeDef prevTickFreq;
00373
00374   assert_param(IS_TICKFREQ(Freq));
00375
00376   if (uwTickFreq != Freq)
00377   {
00378
00379     /* Back up uwTickFreq frequency */
00380     prevTickFreq = uwTickFreq;
00381
00382     /* Update uwTickFreq global variable used by HAL_InitTick() */
00383     uwTickFreq = Freq;
00384
00385     /* Apply the new tick Freq  */
00386     status = HAL_InitTick(uwTickPrio);
00387     if (status != HAL_OK)
00388     {
00389       /* Restore previous tick frequency */
00390       uwTickFreq = prevTickFreq;
00391     }
00392   }
00393
00394   return status;
00395 }
00396
00397 /**
00398   * @brief Return tick frequency.
00399   * @retval tick period in Hz
00400   */
00401 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
00402 {
00403   return uwTickFreq;
00404 }
00405
00406 /**
00407   * @brief This function provides minimum delay (in milliseconds) based
00408   *        on variable incremented.
00409   * @note In the default implementation , SysTick timer is the source of time base.
00410   *       It is used to generate interrupts at regular time intervals where uwTick
00411   *       is incremented.
00412   * @note This function is declared as __weak to be overwritten in case of other
00413   *       implementations in user file.
00414   * @param Delay  specifies the delay time length, in milliseconds.
00415   * @retval None
00416   */
00417 __weak void HAL_Delay(uint32_t Delay)
00418 {
00419   uint32_t tickstart = HAL_GetTick();
00420   uint32_t wait = Delay;
00421
00422   /* Add a freq to guarantee minimum wait */
00423   if (wait < HAL_MAX_DELAY)
00424   {
00425     wait += (uint32_t)(uwTickFreq);
00426   }
00427
00428   while ((HAL_GetTick() - tickstart) < wait)
00429   {
00430   }
00431 }
00432
00433 /**
00434   * @brief Suspend Tick increment.
00435   * @note In the default implementation , SysTick timer is the source of time base. It is
00436   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00437   *       is called, the the SysTick interrupt will be disabled and so Tick increment
00438   *       is suspended.
00439   * @note This function is declared as __weak to be overwritten in case of other
00440   *       implementations in user file.
00441   * @retval None
00442   */
00443 __weak void HAL_SuspendTick(void)
00444 {
00445   /* Disable SysTick Interrupt */
00446   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00447 }
00448
00449 /**
00450   * @brief Resume Tick increment.
00451   * @note In the default implementation , SysTick timer is the source of time base. It is
00452   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00453   *       is called, the the SysTick interrupt will be enabled and so Tick increment
00454   *       is resumed.
00455   * @note This function is declared as __weak to be overwritten in case of other
00456   *       implementations in user file.
00457   * @retval None
00458   */
00459 __weak void HAL_ResumeTick(void)
00460 {
00461   /* Enable SysTick Interrupt */
00462   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00463 }
00464
00465 /**
00466   * @brief  Returns the HAL revision
00467   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00468   */
00469 uint32_t HAL_GetHalVersion(void)
00470 {
00471  return __STM32H7xx_HAL_VERSION;
00472 }
00473
00474 /**
00475   * @brief  Returns the device revision identifier.
00476   * @retval Device revision identifier
00477   */
00478 uint32_t HAL_GetREVID(void)
00479 {
00480    return((DBGMCU->IDCODE) >> 16);
00481 }
00482
00483 /**
00484   * @brief  Returns the device identifier.
00485   * @retval Device identifier
00486   */
00487 uint32_t HAL_GetDEVID(void)
00488 {
00489    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00490 }
00491
00492 /**
00493   * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
00494   * @retval Device identifier
00495   */
00496 uint32_t HAL_GetUIDw0(void)
00497 {
00498   return(READ_REG(*((uint32_t *)UID_BASE)));
00499 }
00500
00501 /**
00502   * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
00503   * @retval Device identifier
00504   */
00505 uint32_t HAL_GetUIDw1(void)
00506 {
00507   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00508 }
00509
00510 /**
00511   * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
00512   * @retval Device identifier
00513   */
00514 uint32_t HAL_GetUIDw2(void)
00515 {
00516   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00517 }
00518
00519 /**
00520   * @brief Configure the internal voltage reference buffer voltage scale.
00521   * @param VoltageScaling  specifies the output voltage to achieve
00522   *          This parameter can be one of the following values:
00523   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
00524   *                                                This requires VDDA equal to or higher than 2.4 V.
00525   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
00526   *                                                This requires VDDA equal to or higher than 2.8 V.
00527   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
00528   *                                                This requires VDDA equal to or higher than 1.8 V.
00529   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
00530   *                                                This requires VDDA equal to or higher than 2.1 V.
00531   * @retval None
00532   */
00533 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00534 {
00535   /* Check the parameters */
00536   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00537
00538   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
00539 }
00540
00541 /**
00542   * @brief Configure the internal voltage reference buffer high impedance mode.
00543   * @param Mode  specifies the high impedance mode
00544   *          This parameter can be one of the following values:
00545   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
00546   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
00547   * @retval None
00548   */
00549 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00550 {
00551   /* Check the parameters */
00552   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00553
00554   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00555 }
00556
00557 /**
00558   * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
00559   * @retval None
00560   */
00561 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00562 {
00563   /* Check the parameters */
00564   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00565
00566   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
00567 }
00568
00569 /**
00570   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00571   * @retval HAL_OK/HAL_TIMEOUT
00572   */
00573 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00574 {
00575   uint32_t  tickstart;
00576
00577   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00578
00579   /* Get Start Tick*/
00580   tickstart = HAL_GetTick();
00581
00582   /* Wait for VRR bit  */
00583   while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
00584   {
00585     if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00586     {
00587       return HAL_TIMEOUT;
00588     }
00589   }
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00596   *
00597   * @retval None
00598   */
00599 void HAL_SYSCFG_DisableVREFBUF(void)
00600 {
00601   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00602 }
00603
00604 #if defined(SYSCFG_PMCR_EPIS_SEL)
00605 /**
00606   * @brief  Ethernet PHY Interface Selection either MII or RMII
00607   * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
00608   *   This parameter can be one of the following values:
00609   *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
00610   *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
00611   * @retval None
00612   */
00613 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
00614 {
00615   /* Check the parameter */
00616   assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
00617
00618   MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
00619 }
00620 #endif /* SYSCFG_PMCR_EPIS_SEL */
00621
00622 /**
00623   * @brief  Analog Switch control for dual analog pads.
00624   * @param  SYSCFG_AnalogSwitch: Selects the analog pad
00625   *   This parameter can be one or a combination of the following values:
00626   *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
00627   *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
00628   *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
00629   *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
00630   * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
00631   *   This parameter can be one or a combination of the following values:
00632   *   @arg SYSCFG_SWITCH_PA0_OPEN
00633   *   @arg SYSCFG_SWITCH_PA0_CLOSE
00634   *   @arg SYSCFG_SWITCH_PA1_OPEN
00635   *   @arg SYSCFG_SWITCH_PA1_CLOSE
00636   *   @arg SYSCFG_SWITCH_PC2_OPEN
00637   *   @arg SYSCFG_SWITCH_PC2_CLOSE
00638   *   @arg SYSCFG_SWITCH_PC3_OPEN
00639   *   @arg SYSCFG_SWITCH_PC3_CLOSE
00640   * @retval None
00641   */
00642
00643 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
00644 {
00645   /* Check the parameter */
00646   assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
00647   assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
00648
00649   MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
00650 }
00651
00652 #if defined(SYSCFG_PMCR_BOOSTEN)
00653 /**
00654   * @brief  Enables the booster to reduce the total harmonic distortion of the analog
00655   *         switch when the supply voltage is lower than 2.7 V.
00656   * @note   Activating the booster allows to guaranty the analog switch AC performance
00657   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00658   *         performance is the same on the full voltage range
00659   * @retval None
00660   */
00661 void HAL_SYSCFG_EnableBOOST(void)
00662 {
00663  SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00664 }
00665
00666 /**
00667   * @brief  Disables the booster
00668   * @note   Activating the booster allows to guaranty the analog switch AC performance
00669   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00670   *         performance is the same on the full voltage range
00671   * @retval None
00672   */
00673 void HAL_SYSCFG_DisableBOOST(void)
00674 {
00675  CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00676 }
00677 #endif /* SYSCFG_PMCR_BOOSTEN */
00678
00679 #if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
00680 /**
00681   * @brief  BootCM7 address 0 configuration
00682   * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
00683   *   This parameter can be one of the following values:
00684   *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
00685   *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
00686   * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
00687   * @retval None
00688   */
00689 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
00693   assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
00694   if ( BootRegister == SYSCFG_BOOT_ADDR0 )
00695   {
00696     /* Configure CM7 BOOT ADD0 */
00697 #if defined(DUAL_CORE)
00698     MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
00699 #else
00700     MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
00701 #endif /*DUAL_CORE*/
00702   }
00703   else
00704   {
00705     /* Configure CM7 BOOT ADD1 */
00706 #if defined(DUAL_CORE)
00707     MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
00708 #else
00709     MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
00710 #endif /*DUAL_CORE*/
00711   }
00712 }
00713 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
00714
00715 #if defined(DUAL_CORE)
00716 /**
00717   * @brief  BootCM4 address 0 configuration
00718   * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
00719   *   This parameter can be one of the following values:
00720   *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
00721   *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
00722   * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
00723   * @retval None
00724   */
00725 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
00726 {
00727   /* Check the parameters */
00728   assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
00729   assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
00730
00731   if ( BootRegister == SYSCFG_BOOT_ADDR0 )
00732   {
00733     /* Configure CM4 BOOT ADD0 */
00734     MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
00735   }
00736
00737   else
00738   {
00739     /* Configure CM4 BOOT ADD1 */
00740     MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
00741   }
00742 }
00743
00744 /**
00745   * @brief  Enables the Cortex-M7 boot
00746   * @retval None
00747   */
00748 void HAL_SYSCFG_EnableCM7BOOT(void)
00749 {
00750  SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
00751 }
00752
00753 /**
00754   * @brief  Disables the Cortex-M7 boot
00755   * @note   Disabling the boot will gate the CPU clock
00756   * @retval None
00757   */
00758 void HAL_SYSCFG_DisableCM7BOOT(void)
00759 {
00760  CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
00761 }
00762
00763 /**
00764   * @brief  Enables the Cortex-M4 boot
00765   * @retval None
00766   */
00767 void HAL_SYSCFG_EnableCM4BOOT(void)
00768 {
00769  SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
00770 }
00771
00772 /**
00773   * @brief  Disables the Cortex-M4 boot
00774   * @note   Disabling the boot will gate the CPU clock
00775   * @retval None
00776   */
00777 void HAL_SYSCFG_DisableCM4BOOT(void)
00778 {
00779   CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
00780 }
00781 #endif /*DUAL_CORE*/
00782 /**
00783   * @brief  Enables the I/O Compensation Cell.
00784   * @note   The I/O compensation cell can be used only when the device supply
00785   *         voltage ranges from 2.4 to 3.6 V.
00786   * @retval None
00787   */
00788 void HAL_EnableCompensationCell(void)
00789 {
00790   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
00791 }
00792
00793 /**
00794   * @brief  Power-down the I/O Compensation Cell.
00795   * @note   The I/O compensation cell can be used only when the device supply
00796   *         voltage ranges from 2.4 to 3.6 V.
00797   * @retval None
00798   */
00799 void HAL_DisableCompensationCell(void)
00800 {
00801   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
00802 }
00803
00804
00805 /**
00806   * @brief  To Enable optimize the I/O speed when the product voltage is low.
00807   * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
00808   *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
00809   *         higher than 2.5 V might be destructive.
00810   * @retval None
00811   */
00812 void HAL_SYSCFG_EnableIOSpeedOptimize(void)
00813 {
00814 #if defined(SYSCFG_CCCSR_HSLV)
00815   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
00816 #else
00817   SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
00818 #endif   /* SYSCFG_CCCSR_HSLV */
00819 }
00820
00821 /**
00822   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00823   * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
00824   *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
00825   *         higher than 2.5 V might be destructive.
00826   * @retval None
00827   */
00828 void HAL_SYSCFG_DisableIOSpeedOptimize(void)
00829 {
00830 #if defined(SYSCFG_CCCSR_HSLV)
00831   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
00832 #else
00833   CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
00834 #endif   /* SYSCFG_CCCSR_HSLV */
00835 }
00836
00837 /**
00838   * @brief  Code selection for the I/O Compensation cell
00839   * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
00840   *   This parameter can be one of the following values:
00841   *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
00842   *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
00843   * @retval None
00844   */
00845 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
00846 {
00847   /* Check the parameter */
00848   assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
00849   MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
00850 }
00851
00852 /**
00853   * @brief  Code selection for the I/O Compensation cell
00854   * @param  SYSCFG_PMOSCode: PMOS compensation code
00855   *         This code is applied to the I/O compensation cell when the CS bit of the
00856   *          SYSCFG_CMPCR is set
00857   * @param  SYSCFG_NMOSCode: NMOS compensation code
00858   *         This code is applied to the I/O compensation cell when the CS bit of the
00859   *          SYSCFG_CMPCR is set
00860   * @retval None
00861   */
00862 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
00863 {
00864   /* Check the parameter */
00865   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
00866   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
00867   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
00868 }
00869
00870 #if defined(SYSCFG_CCCR_NCC_MMC)
00871 /**
00872   * @brief  Code selection for the I/O Compensation cell
00873   * @param  SYSCFG_PMOSCode: VDDMMC PMOS compensation code
00874   *         This code is applied to the I/O compensation cell when the CS bit of the
00875   *          SYSCFG_CMPCR is set
00876   * @param  SYSCFG_NMOSCode: VDDMMC NMOS compensation code
00877   *         This code is applied to the I/O compensation cell when the CS bit of the
00878   *          SYSCFG_CMPCR is set
00879   * @retval None
00880   */
00881 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
00882 {
00883   /* Check the parameter */
00884   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
00885   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
00886   MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
00887 }
00888 #endif /* SYSCFG_CCCR_NCC_MMC */
00889
00890 /**
00891   * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
00892   * @retval None
00893   */
00894 void HAL_EnableDBGSleepMode(void)
00895 {
00896   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
00897 }
00898
00899 /**
00900   * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
00901   * @retval None
00902   */
00903 void HAL_DisableDBGSleepMode(void)
00904 {
00905   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
00906 }
00907
00908
00909 /**
00910   * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
00911   * @retval None
00912   */
00913 void HAL_EnableDBGStopMode(void)
00914 {
00915   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
00916 }
00917
00918 /**
00919   * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
00920   * @retval None
00921   */
00922 void HAL_DisableDBGStopMode(void)
00923 {
00924   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
00925 }
00926
00927 /**
00928   * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
00929   * @retval None
00930   */
00931 void HAL_EnableDBGStandbyMode(void)
00932 {
00933   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
00934 }
00935
00936 /**
00937   * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
00938   * @retval None
00939   */
00940 void HAL_DisableDBGStandbyMode(void)
00941 {
00942   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
00943 }
00944
00945 #if defined(DUAL_CORE)
00946 /**
00947   * @brief  Enable the Debug Module during Domain1 SLEEP mode
00948   * @retval None
00949   */
00950 void HAL_EnableDomain2DBGSleepMode(void)
00951 {
00952   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
00953 }
00954
00955 /**
00956   * @brief  Disable the Debug Module during Domain2 SLEEP mode
00957   * @retval None
00958   */
00959 void HAL_DisableDomain2DBGSleepMode(void)
00960 {
00961   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
00962 }
00963
00964 /**
00965   * @brief  Enable the Debug Module during Domain2 STOP mode
00966   * @retval None
00967   */
00968 void HAL_EnableDomain2DBGStopMode(void)
00969 {
00970   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
00971 }
00972
00973 /**
00974   * @brief  Disable the Debug Module during Domain2 STOP mode
00975   * @retval None
00976   */
00977 void HAL_DisableDomain2DBGStopMode(void)
00978 {
00979   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
00980 }
00981
00982 /**
00983   * @brief  Enable the Debug Module during Domain2 STANDBY mode
00984   * @retval None
00985   */
00986 void HAL_EnableDomain2DBGStandbyMode(void)
00987 {
00988   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
00989 }
00990
00991 /**
00992   * @brief  Disable the Debug Module during Domain2 STANDBY mode
00993   * @retval None
00994   */
00995 void HAL_DisableDomain2DBGStandbyMode(void)
00996 {
00997   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
00998 }
00999 #endif /*DUAL_CORE*/
01000
01001 /**
01002   * @brief  Enable the Debug Module during Domain3/SRDomain STOP mode
01003   * @retval None
01004   */
01005 void HAL_EnableDomain3DBGStopMode(void)
01006 {
01007   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
01008 }
01009 /**
01010   * @brief  Disable the Debug Module during Domain3/SRDomain STOP mode
01011   * @retval None
01012   */
01013 void HAL_DisableDomain3DBGStopMode(void)
01014 {
01015   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
01016 }
01017
01018 /**
01019   * @brief  Enable the Debug Module during Domain3/SRDomain STANDBY mode
01020   * @retval None
01021   */
01022 void HAL_EnableDomain3DBGStandbyMode(void)
01023 {
01024   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
01025 }
01026
01027 /**
01028   * @brief  Disable the Debug Module during Domain3/SRDomain STANDBY mode
01029   * @retval None
01030   */
01031 void HAL_DisableDomain3DBGStandbyMode(void)
01032 {
01033   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
01034 }
01035
01036 /**
01037   * @brief  Set the FMC Memory Mapping Swapping config.
01038   * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
01039             FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
01040   * @retval HAL state
01041   */
01042 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
01043 {
01044   /* Check the parameter */
01045   assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
01046   MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
01047 }
01048
01049 /**
01050   * @brief  Get FMC Bank mapping mode.
01051   * @retval The FMC Bank mapping mode. This parameter can be
01052             FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
01053 */
01054 uint32_t HAL_GetFMCMemorySwappingConfig(void)
01055 {
01056   return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
01057 }
01058
01059 /**
01060   * @brief  Configure the EXTI input event line edge
01061   * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
01062   *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
01063   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01064   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
01065   * @param   EXTI_Edge: Specifies  EXTI line Edge used.
01066   *          This parameter can be one of the following values :
01067   *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
01068   *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
01069   * @retval None
01070   */
01071 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
01072 {
01073   /* Check the parameter */
01074   assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
01075   assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
01076
01077   /* Clear Rising Falling edge configuration */
01078   CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01079   CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01080
01081   if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
01082   {
01083    SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01084   }
01085   if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
01086   {
01087    SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01088   }
01089 }
01090
01091 /**
01092   * @brief  Generates a Software interrupt on selected EXTI line.
01093   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01094   *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
01095   * @retval None
01096   */
01097 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
01098 {
01099   /* Check the parameters */
01100   assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
01101
01102   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01103 }
01104
01105
01106 /**
01107   * @brief  Clears the EXTI's line pending flags for Domain D1
01108   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01109   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
01110   * @retval None
01111   */
01112 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
01113 {
01114   /* Check the parameters */
01115  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
01116  WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01117
01118 }
01119
01120 #if defined(DUAL_CORE)
01121 /**
01122   * @brief  Clears the EXTI's line pending flags for Domain D2
01123   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01124   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
01125   * @retval None
01126   */
01127 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
01128 {
01129   /* Check the parameters */
01130  assert_param(IS_EXTI_D2_LINE(EXTI_Line));
01131  WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01132 }
01133
01134 #endif /*DUAL_CORE*/
01135 /**
01136   * @brief  Configure the EXTI input event line for Domain D1
01137   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01138   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
01139   * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
01140   *          This parameter can be one or a combination of the following values :
01141   *   @arg EXTI_MODE_IT :  Interrupt Mode selected
01142   *   @arg EXTI_MODE_EVT : Event Mode selected
01143   * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
01144
01145   * @retval None
01146   */
01147 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
01148 {
01149   /* Check the parameter */
01150   assert_param(IS_EXTI_D1_LINE(EXTI_Line));
01151   assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
01152
01153   if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
01154   {
01155      if( EXTI_LineCmd == 0UL)
01156      {
01157        /* Clear EXTI line configuration */
01158         CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
01159      }
01160      else
01161      {
01162         SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01163      }
01164   }
01165
01166   if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
01167   {
01168     if( EXTI_LineCmd == 0UL)
01169     {
01170       /* Clear EXTI line configuration */
01171       CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01172     }
01173     else
01174     {
01175       SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01176     }
01177   }
01178 }
01179
01180 #if defined(DUAL_CORE)
01181 /**
01182   * @brief  Configure the EXTI input event line for Domain D2
01183   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01184   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
01185   * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
01186   *          This parameter can be one or a combination of the following values :
01187   *   @arg EXTI_MODE_IT :  Interrupt Mode selected
01188   *   @arg EXTI_MODE_EVT : Event Mode selected
01189   * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
01190
01191   * @retval None
01192   */
01193 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
01194 {
01195   /* Check the parameter */
01196   assert_param(IS_EXTI_D2_LINE(EXTI_Line));
01197   assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
01198
01199   if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
01200   {
01201     if( EXTI_LineCmd == 0UL)
01202     {
01203     /* Clear EXTI line configuration */
01204      CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
01205     }
01206     else
01207     {
01208      SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01209     }
01210   }
01211
01212   if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
01213   {
01214     if( EXTI_LineCmd == 0UL)
01215     {
01216       /* Clear EXTI line configuration */
01217       CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01218     }
01219     else
01220     {
01221       SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01222     }
01223   }
01224 }
01225 #endif /*DUAL_CORE*/
01226
01227 /**
01228   * @brief  Configure the EXTI input event line for Domain D3
01229   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
01230   *         (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
01231   *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
01232   * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
01233   * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
01234   *          This parameter can be one of the following values :
01235   *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
01236   *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
01237   *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
01238   *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
01239   * @retval None
01240   */
01241 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
01242 {
01243   __IO uint32_t *pRegv;
01244
01245   /* Check the parameter */
01246   assert_param(IS_EXTI_D3_LINE(EXTI_Line));
01247   assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
01248
01249   if( EXTI_LineCmd == 0UL)
01250   {
01251     /* Clear EXTI line configuration */
01252     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
01253   }
01254   else
01255   {
01256     SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
01257   }
01258
01259   if(((EXTI_Line>>4)%2UL) == 0UL)
01260   {
01261     pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
01262   }
01263   else
01264   {
01265     pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
01266   }
01267   MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
01268
01269 }
01270
01271
01272
01273 /**
01274   * @}
01275   */
01276
01277 /**
01278   * @}
01279   */
01280
01281 /**
01282   * @}
01283   */
01284
01285 /**
01286   * @}
01287   */
01288
01289 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:56 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal.h Source File

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stm32h7xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the HAL
00006   *          module driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00011   * All rights reserved.</center></h2>
00012   *
00013   * This software component is licensed by ST under BSD 3-Clause license,
00014   * the "License"; You may not use this file except in compliance with the
00015   * License. You may obtain a copy of the License at:
00016   *                        opensource.org/licenses/BSD-3-Clause
00017   *
00018   ******************************************************************************
00019   */
00020
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef STM32H7xx_HAL_H
00023 #define STM32H7xx_HAL_H
00024
00025 #ifdef __cplusplus
00026  extern "C" {
00027 #endif
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_conf.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup HAL
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup HAL_TICK_FREQ Tick Frequency
00042   * @{
00043   */
00044 typedef enum
00045 {
00046   HAL_TICK_FREQ_10HZ         = 100U,
00047   HAL_TICK_FREQ_100HZ        = 10U,
00048   HAL_TICK_FREQ_1KHZ         = 1U,
00049   HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
00050 } HAL_TickFreqTypeDef;
00051 /**
00052   * @}
00053   */
00054
00055 /* Exported constants --------------------------------------------------------*/
00056
00057 /** @defgroup REV_ID device revision ID
00058   * @{
00059   */
00060 #define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
00061 #define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
00062 #define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
00063 #define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00070   * @{
00071   */
00072 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
00073 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
00074 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
00075 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
00076
00077
00078 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00079                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
00080                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
00081                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
00082
00083
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00089   * @{
00090   */
00091 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00092 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
00093
00094 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00095                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00096
00097 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00098
00099 /**
00100   * @}
00101   */
00102
00103 #if !defined(SYSCFG_PMCR_BOOSTEN)
00104 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00105   * @{
00106   */
00107
00108 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00109   */
00110 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
00111 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
00112 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
00113 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
00114
00115 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00116                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00117                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
00118                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00119
00120 #endif /* ! SYSCFG_PMCR_BOOSTEN */
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup SYSCFG_Ethernet_Config  Ethernet Config
00126   * @{
00127   */
00128 #define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
00129 #define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
00130
00131 #define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
00132                                           ((CONFIG) == SYSCFG_ETH_RMII))
00133
00134 /**
00135   * @}
00136   */
00137
00138
00139 /** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config
00140   * @{
00141   */
00142 #define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
00143 #define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
00144 #define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
00145 #define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
00146
00147
00148 #define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
00149                                            (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
00150                                            (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
00151                                            (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
00152
00153
00154 #define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
00155 #define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
00156 #define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
00157 #define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
00158 #define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
00159 #define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
00160 #define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
00161 #define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
00162
00163 #define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
00164                                            (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
00165                                            (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
00166                                            (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
00167                                            (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
00168                                            (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
00169                                            (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
00170                                            (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup SYSCFG_Boot_Config  Boot Config
00176   * @{
00177   */
00178 #define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
00179 #define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
00180
00181 #define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
00182                                           ((REGISTER) == SYSCFG_BOOT_ADDR1))
00183
00184 #define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
00185
00186 /**
00187   * @}
00188   */
00189
00190
00191 /** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
00192   * @{
00193   */
00194 #define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
00195 #define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
00196
00197 #define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
00198                                         ((SELECT) == SYSCFG_REGISTER_CODE))
00199
00200 #define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
00201
00202 /**
00203   * @}
00204   */
00205
00206
00207
00208
00209 /** @defgroup EXTI_Event_Input_Config  Event Input Config
00210   * @{
00211   */
00212
00213 #define EXTI_MODE_IT          ((uint32_t)0x00010000)
00214 #define EXTI_MODE_EVT         ((uint32_t)0x00020000)
00215 #define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
00216 #define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
00217
00218 #define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
00219 #define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
00220
00221 #define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
00222 #define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
00223 #define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
00224 #define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
00225 #define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
00226 #define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
00227 #define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
00228 #define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
00229 #define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
00230 #define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
00231 #define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
00232 #define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
00233 #define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
00234 #define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
00235 #define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
00236 #define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
00237 #define EXTI_LINE16      ((uint32_t)0x10)
00238 #define EXTI_LINE17      ((uint32_t)0x11)
00239 #define EXTI_LINE18      ((uint32_t)0x12)
00240 #define EXTI_LINE19      ((uint32_t)0x13)
00241 #define EXTI_LINE20      ((uint32_t)0x14)
00242 #define EXTI_LINE21      ((uint32_t)0x15)
00243 #define EXTI_LINE22      ((uint32_t)0x16)
00244 #define EXTI_LINE23      ((uint32_t)0x17)
00245 #define EXTI_LINE24      ((uint32_t)0x18)
00246 #define EXTI_LINE25      ((uint32_t)0x19)
00247 #define EXTI_LINE26      ((uint32_t)0x1A)
00248 #define EXTI_LINE27      ((uint32_t)0x1B)
00249 #define EXTI_LINE28      ((uint32_t)0x1C)
00250 #define EXTI_LINE29      ((uint32_t)0x1D)
00251 #define EXTI_LINE30      ((uint32_t)0x1E)
00252 #define EXTI_LINE31      ((uint32_t)0x1F)
00253 #define EXTI_LINE32      ((uint32_t)0x20)
00254 #define EXTI_LINE33      ((uint32_t)0x21)
00255 #define EXTI_LINE34      ((uint32_t)0x22)
00256 #define EXTI_LINE35      ((uint32_t)0x23)
00257 #define EXTI_LINE36      ((uint32_t)0x24)
00258 #define EXTI_LINE37      ((uint32_t)0x25)
00259 #define EXTI_LINE38      ((uint32_t)0x26)
00260 #define EXTI_LINE39      ((uint32_t)0x27)
00261
00262 #define EXTI_LINE40      ((uint32_t)0x28)
00263 #define EXTI_LINE41      ((uint32_t)0x29)
00264 #define EXTI_LINE42      ((uint32_t)0x2A)
00265 #define EXTI_LINE43      ((uint32_t)0x2B)
00266 #define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
00267 /* EXTI_LINE45 Reserved */
00268 #if defined(DUAL_CORE)
00269 #define EXTI_LINE46      ((uint32_t)0x2E)
00270 #else
00271 /* EXTI_LINE46 Reserved */
00272 #endif /* DUAL_CORE */
00273 #define EXTI_LINE47      ((uint32_t)0x2F)
00274 #define EXTI_LINE48      ((uint32_t)0x30)
00275 #define EXTI_LINE49      ((uint32_t)0x31)
00276 #define EXTI_LINE50      ((uint32_t)0x32)
00277 #define EXTI_LINE51      ((uint32_t)0x33)
00278 #define EXTI_LINE52      ((uint32_t)0x34)
00279 #define EXTI_LINE53      ((uint32_t)0x35)
00280 #define EXTI_LINE54      ((uint32_t)0x36)
00281 #define EXTI_LINE55      ((uint32_t)0x37)
00282 #define EXTI_LINE56      ((uint32_t)0x38)
00283 #define EXTI_LINE57      ((uint32_t)0x39)
00284 #define EXTI_LINE58      ((uint32_t)0x3A)
00285 #define EXTI_LINE59      ((uint32_t)0x3B)
00286 #define EXTI_LINE60      ((uint32_t)0x3C)
00287 #define EXTI_LINE61      ((uint32_t)0x3D)
00288 #define EXTI_LINE62      ((uint32_t)0x3E)
00289 #define EXTI_LINE63      ((uint32_t)0x3F)
00290 #define EXTI_LINE64      ((uint32_t)0x40)
00291 #define EXTI_LINE65      ((uint32_t)0x41)
00292 #define EXTI_LINE66      ((uint32_t)0x42)
00293 #define EXTI_LINE67      ((uint32_t)0x43)
00294 #define EXTI_LINE68      ((uint32_t)0x44)
00295 #define EXTI_LINE69      ((uint32_t)0x45)
00296 #define EXTI_LINE70      ((uint32_t)0x46)
00297 #define EXTI_LINE71      ((uint32_t)0x47)
00298 #define EXTI_LINE72      ((uint32_t)0x48)
00299 #define EXTI_LINE73      ((uint32_t)0x49)
00300 #define EXTI_LINE74      ((uint32_t)0x4A)
00301 #define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
00302 #define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
00303 #if defined(DUAL_CORE)
00304 #define EXTI_LINE77      ((uint32_t)0x4D)
00305 #define EXTI_LINE78      ((uint32_t)0x4E)
00306 #define EXTI_LINE79      ((uint32_t)0x4F)
00307 #define EXTI_LINE80      ((uint32_t)0x50)
00308 #else
00309 /* EXTI_LINE77 Reserved */
00310 /* EXTI_LINE78 Reserved */
00311 /* EXTI_LINE79 Reserved */
00312 /* EXTI_LINE80 Reserved */
00313 #endif /* DUAL_CORE */
00314 /* EXTI_LINE81   Reserved */
00315 #if defined(DUAL_CORE)
00316 #define EXTI_LINE82      ((uint32_t)0x52)
00317 #else
00318 /* EXTI_LINE82 Reserved */
00319 #endif /* DUAL_CORE */
00320 /* EXTI_LINE83   Reserved */
00321 #if defined(DUAL_CORE)
00322 #define EXTI_LINE84      ((uint32_t)0x54)
00323 #else
00324 /* EXTI_LINE84 Reserved */
00325 #endif /* DUAL_CORE */
00326 #define EXTI_LINE85      ((uint32_t)0x55)
00327 #define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
00328 #define EXTI_LINE87      ((uint32_t)0x57)
00329 #define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
00330
00331 #if defined(DUAL_CORE)
00332 #define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
00333                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
00334                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
00335                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
00336                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
00337                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \
00338                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \
00339                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \
00340                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \
00341                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \
00342                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \
00343                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \
00344                                 ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \
00345                                 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
00346 #else
00347 #define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
00348                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
00349                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
00350                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
00351                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
00352                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00353                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00354                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00355                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00356                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00357                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00358                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
00359                                 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
00360 #endif /* DUAL_CORE */
00361
00362 #if defined(DUAL_CORE)
00363 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00364                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00365                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00366                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00367                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00368                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00369                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00370                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00371                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00372                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00373                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00374                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00375                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00376                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00377                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00378                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00379                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00380                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00381                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00382                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00383                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00384                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00385                                 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
00386                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00387                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00388                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00389                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00390                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00391                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00392                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00393                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00394                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00395                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00396                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00397                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00398                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00399                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00400                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00401                                 ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
00402                                 ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
00403                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
00404                                 ((LINE) == EXTI_LINE78) || \
00405                                 ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
00406 #else
00407 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00408                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00409                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00410                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00411                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00412                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00413                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00414                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00415                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00416                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00417                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00418                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00419                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00420                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00421                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00422                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00423                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00424                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00425                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00426                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00427                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00428                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00429                                 ((LINE) == EXTI_LINE44) || \
00430                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00431                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00432                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00433                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00434                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00435                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00436                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00437                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00438                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00439                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00440                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00441                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00442                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00443                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00444                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00445                                 ((LINE) == EXTI_LINE85) || \
00446                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
00447                                 ((LINE) == EXTI_LINE88))
00448 #endif /*DUAL_CORE*/
00449
00450 #if defined(DUAL_CORE)
00451 #define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00452                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00453                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00454                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00455                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00456                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00457                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00458                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00459                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00460                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00461                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00462                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00463                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00464                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00465                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00466                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00467                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00468                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00469                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00470                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00471                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00472                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00473                                 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
00474                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00475                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00476                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00477                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00478                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00479                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00480                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00481                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00482                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00483                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00484                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00485                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00486                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00487                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00488                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00489                                 ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
00490                                 ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
00491                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
00492 #else
00493 #define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00494                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00495                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00496                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00497                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00498                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00499                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00500                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00501                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00502                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00503                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00504                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00505                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00506                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00507                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00508                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00509                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00510                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00511                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00512                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00513                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00514                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00515                                 ((LINE) == EXTI_LINE44) || \
00516                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00517                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00518                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00519                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00520                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00521                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00522                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00523                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00524                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00525                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00526                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00527                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00528                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00529                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00530                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00531                                 ((LINE) == EXTI_LINE85) || \
00532                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
00533                                 ((LINE) == EXTI_LINE88))
00534 #endif /*DUAL_CORE*/
00535
00536 #if defined(DUAL_CORE)
00537 #define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \
00538                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
00539                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
00540                                 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
00541                                 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
00542                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00543                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00544                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00545                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00546                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00547                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00548                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00549                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00550                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00551                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00552                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00553                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00554                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00555                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00556                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00557                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00558                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00559                                 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
00560                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00561                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00562                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00563                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00564                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00565                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00566                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00567                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00568                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00569                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00570                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00571                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00572                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00573                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00574                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00575                                 ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
00576                                 ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
00577                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
00578 #endif /*DUAL_CORE*/
00579
00580 #if defined(DUAL_CORE)
00581 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
00582                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
00583                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
00584                                 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
00585                                 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
00586                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00587                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00588                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00589                                 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
00590                                 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
00591                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00592                                 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
00593                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00594                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00595                                 ((LINE) == EXTI_LINE53))
00596 #elif (POWER_DOMAINS_NUMBER == 3U)
00597 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
00598                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
00599                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
00600                                 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
00601                                 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
00602                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00603                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00604                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00605                                 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
00606                                 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
00607                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00608                                 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
00609                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00610                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00611                                 ((LINE) == EXTI_LINE53))
00612 #else
00613 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
00614                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
00615                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
00616                                 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
00617                                 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
00618                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00619                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00620                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00621                                 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
00622                                 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
00623                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00624                                 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
00625                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00626                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
00627 #endif /*DUAL_CORE*/
00628
00629
00630 #define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
00631 #define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
00632 #if defined (LPTIM4)
00633 #define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
00634 #else
00635 #define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
00636 #endif /* LPTIM4 */
00637 #if defined (LPTIM5)
00638 #define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
00639 #else
00640 #define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
00641 #endif /* LPTIM5 */
00642 #if defined (LPTIM4) && defined (LPTIM5)
00643 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
00644                                  ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
00645 #else
00646 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
00647                                  ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
00648 #endif /* LPTIM4 LPTIM5 */
00649 /**
00650   * @}
00651   */
00652
00653
00654 /** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config
00655   * @{
00656   */
00657 #define FMC_SWAPBMAP_DISABLE             (0x00000000U)
00658 #define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
00659 #define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
00660
00661 #define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
00662                                         ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
00663                                         ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
00664 /**
00665   * @}
00666   */
00667
00668
00669 /* Exported macro ------------------------------------------------------------*/
00670 /** @defgroup ART_Exported_Macros ART Exported Macros
00671   * @{
00672   */
00673 #if defined(DUAL_CORE)
00674
00675 /** @brief  ART Enable Macro.
00676   *         Enable the Cortex-M4 ART cache.
00677   */
00678 #define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
00679
00680 /** @brief  ART Disable Macro.
00681   *         Disable the Cortex-M4 ART cache.
00682   */
00683 #define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
00684
00685 /** @brief  ART Cache BaseAddress Config.
00686   *         Configure the Cortex-M4 ART cache Base Address.
00687   */
00688 #define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
00689
00690 #endif /* DUAL_CORE */
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00696   * @{
00697   */
00698
00699 /** @brief  SYSCFG Break AXIRAM double ECC lock.
00700   *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00701   * @note   The selected configuration is locked and can be unlocked only by system reset.
00702             This feature is available on STM32H7 rev.B and above.
00703   */
00704 #define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
00705
00706 /** @brief  SYSCFG Break ITCM double ECC lock.
00707   *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00708   * @note   The selected configuration is locked and can be unlocked only by system reset.
00709             This feature is available on STM32H7 rev.B and above.
00710   */
00711 #define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
00712
00713 /** @brief  SYSCFG Break DTCM double ECC lock.
00714   *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00715   * @note   The selected configuration is locked and can be unlocked only by system reset.
00716             This feature is available on STM32H7 rev.B and above.
00717   */
00718 #define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
00719
00720 /** @brief  SYSCFG Break SRAM1 double ECC lock.
00721   *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00722   * @note   The selected configuration is locked and can be unlocked only by system reset.
00723             This feature is available on STM32H7 rev.B and above.
00724   */
00725 #define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
00726
00727 /** @brief  SYSCFG Break SRAM2 double ECC lock.
00728   *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00729   * @note   The selected configuration is locked and can be unlocked only by system reset.
00730             This feature is available on STM32H7 rev.B and above.
00731   */
00732 #define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
00733
00734 /** @brief  SYSCFG Break SRAM3 double ECC lock.
00735   *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00736   * @note   The selected configuration is locked and can be unlocked only by system reset.
00737             This feature is available on STM32H7 rev.B and above.
00738   */
00739 #define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
00740
00741 /** @brief  SYSCFG Break SRAM4 double ECC lock.
00742   *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00743   * @note   The selected configuration is locked and can be unlocked only by system reset.
00744             This feature is available on STM32H7 rev.B and above.
00745   */
00746 #define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
00747
00748 /** @brief  SYSCFG Break Backup SRAM double ECC lock.
00749   *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
00750   * @note   The selected configuration is locked and can be unlocked only by system reset.
00751             This feature is available on STM32H7 rev.B and above.
00752   */
00753 #define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
00754
00755 /** @brief  SYSCFG Break Cortex-M7 Lockup lock.
00756   *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
00757   * @note   The selected configuration is locked and can be unlocked only by system reset.
00758             This feature is available on STM32H7 rev.B and above.
00759   */
00760 #define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
00761
00762 /** @brief  SYSCFG Break FLASH double ECC lock.
00763   *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
00764   * @note   The selected configuration is locked and can be unlocked only by system reset.
00765             This feature is available on STM32H7 rev.B and above.
00766   */
00767 #define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
00768
00769 /** @brief  SYSCFG Break PVD lock.
00770   *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
00771   * @note   The selected configuration is locked and can be unlocked only by system reset.
00772             This feature is available on STM32H7 rev.B and above.
00773   */
00774 #define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
00775
00776 #if defined(DUAL_CORE)
00777 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
00778   *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
00779   * @note   The selected configuration is locked and can be unlocked only by system reset.
00780             This feature is available on STM32H7 rev.B and above.
00781   */
00782 #define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
00783 #endif /* DUAL_CORE */
00784
00785 #if !defined(SYSCFG_PMCR_BOOSTEN)
00786 /** @brief  Fast-mode Plus driving capability enable/disable macros
00787   * @param __FASTMODEPLUS__  This parameter can be a value of :
00788   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
00789   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
00790   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
00791   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
00792   */
00793 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00794                                                                 SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
00795                                                                }while(0)
00796
00797 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00798                                                                 CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
00799                                                                }while(0)
00800
00801 #endif /* !SYSCFG_PMCR_BOOSTEN */
00802 /**
00803   * @}
00804   */
00805
00806 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00807   */
00808 #define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
00809
00810 #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
00811 #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
00812 #define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
00813 #define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
00814 #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
00815 #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
00816 #define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
00817 #define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
00818 #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
00819 #define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
00820 #define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
00821 #define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
00822 #define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
00823 #define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
00824
00825
00826 #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
00827 #define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
00828 #define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
00829 #define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
00830 #define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
00831 #define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
00832
00833 #define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
00834 #define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
00835 #define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
00836 #define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
00837 #define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
00838 #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
00839 #define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
00840
00841
00842 #define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
00843
00844 #define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
00845 #define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
00846 #define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
00847 #define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
00848 #define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
00849 #define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
00850 #define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
00851 #define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
00852 #define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
00853 #define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
00854 #define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
00855 #define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
00856 #define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
00857 #define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
00858
00859
00860 #define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
00861 #define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
00862 #define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
00863 #define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
00864 #define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
00865 #define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
00866
00867 #define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
00868 #define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
00869 #define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
00870 #define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
00871 #define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
00872 #define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
00873 #define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
00874
00875
00876 #if defined(DUAL_CORE)
00877 #define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))
00878 #define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
00879
00880 #define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
00881 #define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
00882
00883
00884 #define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
00885
00886 #define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
00887 #define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
00888 #define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
00889 #define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
00890 #define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
00891 #define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
00892 #define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
00893 #define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
00894 #define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
00895 #define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
00896 #define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
00897 #define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
00898 #define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
00899 #define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
00900
00901
00902 #define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
00903 #define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
00904 #define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
00905 #define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
00906 #define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
00907 #define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
00908
00909 #define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
00910 #define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
00911 #define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
00912 #define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
00913 #define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
00914 #define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
00915 #define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
00916
00917 #define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
00918
00919 #define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
00920 #define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
00921 #define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
00922 #define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
00923 #define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
00924 #define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
00925 #define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
00926 #define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
00927 #define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
00928 #define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
00929 #define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
00930 #define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
00931 #define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
00932 #define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
00933
00934
00935 #define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
00936 #define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
00937 #define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
00938 #define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
00939 #define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
00940 #define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
00941
00942 #define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
00943 #define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
00944 #define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
00945 #define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
00946 #define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
00947 #define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
00948 #define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
00949
00950 #endif /*DUAL_CORE*/
00951
00952 /** @defgroup HAL_Private_Macros HAL Private Macros
00953   * @{
00954   */
00955 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
00956                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
00957                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
00958 /**
00959   * @}
00960   */
00961
00962 /* Exported variables --------------------------------------------------------*/
00963
00964 /** @addtogroup HAL_Exported_Variables
00965   * @{
00966   */
00967 extern __IO uint32_t uwTick;
00968 extern uint32_t uwTickPrio;
00969 extern HAL_TickFreqTypeDef uwTickFreq;
00970 /**
00971   * @}
00972   */
00973
00974 /* Exported functions --------------------------------------------------------*/
00975
00976 /* Initialization and de-initialization functions  ******************************/
00977 HAL_StatusTypeDef HAL_Init(void);
00978 HAL_StatusTypeDef HAL_DeInit(void);
00979 void HAL_MspInit(void);
00980 void HAL_MspDeInit(void);
00981 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00982
00983 /* Peripheral Control functions  ************************************************/
00984 void HAL_IncTick(void);
00985 void HAL_Delay(uint32_t Delay);
00986 uint32_t HAL_GetTick(void);
00987 uint32_t HAL_GetTickPrio(void);
00988 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
00989 HAL_TickFreqTypeDef HAL_GetTickFreq(void);
00990 void HAL_SuspendTick(void);
00991 void HAL_ResumeTick(void);
00992 uint32_t HAL_GetHalVersion(void);
00993 uint32_t HAL_GetREVID(void);
00994 uint32_t HAL_GetDEVID(void);
00995 uint32_t HAL_GetUIDw0(void);
00996 uint32_t HAL_GetUIDw1(void);
00997 uint32_t HAL_GetUIDw2(void);
00998 #if defined(SYSCFG_PMCR_EPIS_SEL)
00999 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
01000 #endif /* SYSCFG_PMCR_EPIS_SEL */
01001 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
01002 #if defined(SYSCFG_PMCR_BOOSTEN)
01003 void HAL_SYSCFG_EnableBOOST(void);
01004 void HAL_SYSCFG_DisableBOOST(void);
01005 #endif /* SYSCFG_PMCR_BOOSTEN */
01006
01007 #if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
01008 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
01009 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
01010
01011 #if defined(DUAL_CORE)
01012 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
01013 void HAL_SYSCFG_EnableCM7BOOT(void);
01014 void HAL_SYSCFG_DisableCM7BOOT(void);
01015 void HAL_SYSCFG_EnableCM4BOOT(void);
01016 void HAL_SYSCFG_DisableCM4BOOT(void);
01017 #endif /*DUAL_CORE*/
01018 void HAL_EnableCompensationCell(void);
01019 void HAL_DisableCompensationCell(void);
01020 void HAL_SYSCFG_EnableIOSpeedOptimize(void);
01021 void HAL_SYSCFG_DisableIOSpeedOptimize(void);
01022 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
01023 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
01024 #if defined(SYSCFG_CCCR_NCC_MMC)
01025 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
01026 #endif /* SYSCFG_CCCR_NCC_MMC */
01027 void HAL_EnableDBGSleepMode(void);
01028 void HAL_DisableDBGSleepMode(void);
01029 void HAL_EnableDBGStopMode(void);
01030 void HAL_DisableDBGStopMode(void);
01031 void HAL_EnableDBGStandbyMode(void);
01032 void HAL_DisableDBGStandbyMode(void);
01033 #if defined(DUAL_CORE)
01034 void HAL_EnableDomain2DBGSleepMode(void);
01035 void HAL_DisableDomain2DBGSleepMode(void);
01036 void HAL_EnableDomain2DBGStopMode(void);
01037 void HAL_DisableDomain2DBGStopMode(void);
01038 void HAL_EnableDomain2DBGStandbyMode(void);
01039 void HAL_DisableDomain2DBGStandbyMode(void);
01040 #endif /*DUAL_CORE*/
01041 void HAL_EnableDomain3DBGStopMode(void);
01042 void HAL_DisableDomain3DBGStopMode(void);
01043 void HAL_EnableDomain3DBGStandbyMode(void);
01044 void HAL_DisableDomain3DBGStandbyMode(void);
01045 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
01046 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
01047 #if defined(DUAL_CORE)
01048 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
01049 #endif /*DUAL_CORE*/
01050 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
01051 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
01052 #if defined(DUAL_CORE)
01053 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
01054 #endif /*DUAL_CORE*/
01055 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
01056 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
01057 uint32_t HAL_GetFMCMemorySwappingConfig(void);
01058 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
01059 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
01060 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
01061 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
01062 void HAL_SYSCFG_DisableVREFBUF(void);
01063
01064 /**
01065   * @}
01066   */
01067
01068 /**
01069   * @}
01070   */
01071
01072 #ifdef __cplusplus
01073 }
01074 #endif
01075
01076 #endif /* STM32H7xx_HAL_H */
01077
01078 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:56 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc.c Source File

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stm32h7xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Initialization and de-initialization functions
00009   *             ++ Initialization and Configuration of ADC
00010   *           + Operation functions
00011   *             ++ Start, stop, get result of conversions of regular
00012   *                group, using 3 possible modes: polling, interruption or DMA.
00013   *           + Control functions
00014   *             ++ Channels configuration on regular group
00015   *             ++ Analog Watchdog configuration
00016   *           + State functions
00017   *             ++ ADC state machine management
00018   *             ++ Interrupts and flags management
00019   *          Other functions (extended functions) are available in file
00020   *          "stm32h7xx_hal_adc_ex.c".
00021   *
00022   @verbatim
00023   ==============================================================================
00024                      ##### ADC peripheral features #####
00025   ==============================================================================
00026   [..]
00027   (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
00028
00029   (+) Interrupt generation at the end of regular conversion and in case of
00030       analog watchdog or overrun events.
00031
00032   (+) Single and continuous conversion modes.
00033
00034   (+) Scan mode for conversion of several channels sequentially.
00035
00036   (+) Data alignment with in-built data coherency.
00037
00038   (+) Programmable sampling time (channel wise)
00039
00040   (+) External trigger (timer or EXTI) with configurable polarity
00041
00042   (+) DMA request generation for transfer of conversions data of regular group.
00043
00044   (+) Configurable delay between conversions in Dual interleaved mode.
00045
00046   (+) ADC channels selectable single/differential input.
00047
00048   (+) ADC offset shared on 4 offset instances.
00049   (+) ADC calibration
00050
00051   (+) ADC conversion of regular group.
00052
00053   (+) ADC supply requirements: 1.62 V to 3.6 V.
00054
00055   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00056       Vdda or to an external voltage reference).
00057
00058
00059                      ##### How to use this driver #####
00060   ==============================================================================
00061     [..]
00062
00063      *** Configuration of top level parameters related to ADC ***
00064      ============================================================
00065      [..]
00066
00067     (#) Enable the ADC interface
00068         (++) As prerequisite, ADC clock must be configured at RCC top level.
00069
00070         (++) Two clock settings are mandatory:
00071              (+++) ADC clock (core clock, also possibly conversion clock).
00072
00073              (+++) ADC clock (conversions clock).
00074                    Two possible clock sources: synchronous clock derived from AHB clock
00075                    or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.
00076
00077              (+++) Example:
00078                    Into HAL_ADC_MspInit() (recommended code location) or with
00079                    other device clock parameters configuration:
00080                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
00081
00082                RCC_ADCCLKSOURCE_PLL2 enable:                   (optional: if asynchronous clock selected)
00083                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00084                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00085                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL2;
00086                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00087
00088         (++) ADC clock source and clock prescaler are configured at ADC level with
00089              parameter "ClockPrescaler" using function HAL_ADC_Init().
00090
00091     (#) ADC pins configuration
00092          (++) Enable the clock for the ADC GPIOs
00093               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00094          (++) Configure these ADC pins in analog mode
00095               using function HAL_GPIO_Init()
00096
00097     (#) Optionally, in case of usage of ADC with interruptions:
00098          (++) Configure the NVIC for ADC
00099               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00100          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00101               into the function of corresponding ADC interruption vector
00102               ADCx_IRQHandler().
00103
00104     (#) Optionally, in case of usage of DMA:
00105          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00106               using function HAL_DMA_Init().
00107          (++) Configure the NVIC for DMA
00108               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00109          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00110               into the function of corresponding DMA interruption vector
00111               DMAx_Channelx_IRQHandler().
00112
00113      *** Configuration of ADC, group regular, channels parameters ***
00114      ================================================================
00115      [..]
00116
00117     (#) Configure the ADC parameters (resolution, data alignment, ...)
00118         and regular group parameters (conversion trigger, sequencer, ...)
00119         using function HAL_ADC_Init().
00120
00121     (#) Configure the channels for regular group parameters (channel number,
00122         channel rank into sequencer, ..., into regular group)
00123         using function HAL_ADC_ConfigChannel().
00124
00125     (#) Optionally, configure the analog watchdog parameters (channels
00126         monitored, thresholds, ...)
00127         using function HAL_ADC_AnalogWDGConfig().
00128
00129      *** Execution of ADC conversions ***
00130      ====================================
00131      [..]
00132
00133     (#) Optionally, perform an automatic ADC calibration to improve the
00134         conversion accuracy
00135         using function HAL_ADCEx_Calibration_Start().
00136
00137     (#) ADC driver can be used among three modes: polling, interruption,
00138         transfer by DMA.
00139
00140         (++) ADC conversion by polling:
00141           (+++) Activate the ADC peripheral and start conversions
00142                 using function HAL_ADC_Start()
00143           (+++) Wait for ADC conversion completion
00144                 using function HAL_ADC_PollForConversion()
00145           (+++) Retrieve conversion results
00146                 using function HAL_ADC_GetValue()
00147           (+++) Stop conversion and disable the ADC peripheral
00148                 using function HAL_ADC_Stop()
00149
00150         (++) ADC conversion by interruption:
00151           (+++) Activate the ADC peripheral and start conversions
00152                 using function HAL_ADC_Start_IT()
00153           (+++) Wait for ADC conversion completion by call of function
00154                 HAL_ADC_ConvCpltCallback()
00155                 (this function must be implemented in user program)
00156           (+++) Retrieve conversion results
00157                 using function HAL_ADC_GetValue()
00158           (+++) Stop conversion and disable the ADC peripheral
00159                 using function HAL_ADC_Stop_IT()
00160
00161         (++) ADC conversion with transfer by DMA:
00162           (+++) Activate the ADC peripheral and start conversions
00163                 using function HAL_ADC_Start_DMA()
00164           (+++) Wait for ADC conversion completion by call of function
00165                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00166                 (these functions must be implemented in user program)
00167           (+++) Conversion results are automatically transferred by DMA into
00168                 destination variable address.
00169           (+++) Stop conversion and disable the ADC peripheral
00170                 using function HAL_ADC_Stop_DMA()
00171
00172      [..]
00173
00174     (@) Callback functions must be implemented in user program:
00175       (+@) HAL_ADC_ErrorCallback()
00176       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00177       (+@) HAL_ADC_ConvCpltCallback()
00178       (+@) HAL_ADC_ConvHalfCpltCallback
00179
00180      *** Deinitialization of ADC ***
00181      ============================================================
00182      [..]
00183
00184     (#) Disable the ADC interface
00185       (++) ADC clock can be hard reset and disabled at RCC top level.
00186         (++) Hard reset of ADC peripherals
00187              using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
00188         (++) ADC clock disable
00189              using the equivalent macro/functions as configuration step.
00190              (+++) Example:
00191                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00192                    other device clock parameters configuration:
00193                (+++) __HAL_RCC_ADC_CLK_DISABLE();                  (if not used anymore)
00194                RCC_ADCCLKSOURCE_CLKP restore:                      (optional)
00195                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00196                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00197                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
00198                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00199
00200     (#) ADC pins configuration
00201          (++) Disable the clock for the ADC GPIOs
00202               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00203
00204     (#) Optionally, in case of usage of ADC with interruptions:
00205          (++) Disable the NVIC for ADC
00206               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00207
00208     (#) Optionally, in case of usage of DMA:
00209          (++) Deinitialize the DMA
00210               using function HAL_DMA_Init().
00211          (++) Disable the NVIC for DMA
00212               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00213
00214     [..]
00215
00216     *** Callback registration ***
00217     =============================================
00218     [..]
00219
00220      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
00221      allows the user to configure dynamically the driver callbacks.
00222      Use Functions @ref HAL_ADC_RegisterCallback()
00223      to register an interrupt callback.
00224     [..]
00225
00226      Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
00227        (+) ConvCpltCallback               : ADC conversion complete callback
00228        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00229        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00230        (+) ErrorCallback                  : ADC error callback
00231        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00232        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00233        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00234        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00235        (+) EndOfSamplingCallback          : ADC end of sampling callback
00236        (+) MspInitCallback                : ADC Msp Init callback
00237        (+) MspDeInitCallback              : ADC Msp DeInit callback
00238      This function takes as parameters the HAL peripheral handle, the Callback ID
00239      and a pointer to the user callback function.
00240     [..]
00241
00242      Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
00243      weak function.
00244     [..]
00245
00246      @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00247      and the Callback ID.
00248      This function allows to reset following callbacks:
00249        (+) ConvCpltCallback               : ADC conversion complete callback
00250        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00251        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00252        (+) ErrorCallback                  : ADC error callback
00253        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00254        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00255        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00256        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00257        (+) EndOfSamplingCallback          : ADC end of sampling callback
00258        (+) MspInitCallback                : ADC Msp Init callback
00259        (+) MspDeInitCallback              : ADC Msp DeInit callback
00260      [..]
00261
00262      By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
00263      all callbacks are set to the corresponding weak functions:
00264      examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
00265      Exception done for MspInit and MspDeInit functions that are
00266      reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
00267      these callbacks are null (not registered beforehand).
00268     [..]
00269
00270      If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
00271      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00272      [..]
00273
00274      Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
00275      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00276      in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
00277      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00278     [..]
00279
00280      Then, the user first registers the MspInit/MspDeInit user callbacks
00281      using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
00282      or @ref HAL_ADC_Init() function.
00283      [..]
00284
00285      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
00286      not defined, the callback registration feature is not available and all callbacks
00287      are set to the corresponding weak functions.
00288
00289   @endverbatim
00290   ******************************************************************************
00291   * @attention
00292   *
00293   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00294   * All rights reserved.</center></h2>
00295   *
00296   * This software component is licensed by ST under BSD 3-Clause license,
00297   * the "License"; You may not use this file except in compliance with the
00298   * License. You may obtain a copy of the License at:
00299   *                        opensource.org/licenses/BSD-3-Clause
00300   *
00301   ******************************************************************************
00302   */
00303
00304 /* Includes ------------------------------------------------------------------*/
00305 #include "stm32h7xx_hal.h"
00306
00307 /** @addtogroup STM32H7xx_HAL_Driver
00308   * @{
00309   */
00310
00311 /** @defgroup ADC ADC
00312   * @brief ADC HAL module driver
00313   * @{
00314   */
00315
00316 #ifdef HAL_ADC_MODULE_ENABLED
00317
00318 /* Private typedef -----------------------------------------------------------*/
00319 /* Private define ------------------------------------------------------------*/
00320
00321 /** @defgroup ADC_Private_Constants ADC Private Constants
00322   * @{
00323   */
00324 #define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    |\
00325                                        ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00326                                        ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00327                                        ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
00328                                                                                   when no regular conversion is on-going */
00329
00330 #define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
00331                                        ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
00332                                        ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
00333                                                                                  (neither regular nor injected) is on-going  */
00334
00335 /* Timeout values for ADC operations (enable settling time,                   */
00336 /*   disable settling time, ...).                                             */
00337 /*   Values defined to be higher than worst cases: low clock frequency,       */
00338 /*   maximum prescalers.                                                      */
00339 #define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
00340 #define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
00341
00342 /* Timeout to wait for current conversion on going to be completed.           */
00343 /* Timeout fixed to worst case, for 1 channel.                                */
00344 /*   - maximum sampling time (830.5 adc_clk)                                  */
00345 /*   - ADC resolution (Tsar 16 bits= 16.5 adc_clk)                            */
00346 /*   - ADC clock with prescaler 256                                           */
00347 /*     823 * 256 = 210688 clock cycles max                                    */
00348 /* Unit: cycles of CPU clock.                                                 */
00349 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)  /*!< ADC conversion completion time-out value */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /* Private macro -------------------------------------------------------------*/
00356 /* Private variables ---------------------------------------------------------*/
00357 /* Private function prototypes -----------------------------------------------*/
00358 /* Exported functions --------------------------------------------------------*/
00359
00360 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00361   * @{
00362   */
00363
00364 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00365   * @brief    ADC Initialization and Configuration functions
00366   *
00367 @verbatim
00368  ===============================================================================
00369               ##### Initialization and de-initialization functions #####
00370  ===============================================================================
00371     [..]  This section provides functions allowing to:
00372       (+) Initialize and configure the ADC.
00373       (+) De-initialize the ADC.
00374 @endverbatim
00375   * @{
00376   */
00377
00378 /**
00379   * @brief  Initialize the ADC peripheral and regular group according to
00380   *         parameters specified in structure "ADC_InitTypeDef".
00381   * @note   As prerequisite, ADC clock must be configured at RCC top level
00382   *         (refer to description of RCC configuration for ADC
00383   *         in header of this file).
00384   * @note   Possibility to update parameters on the fly:
00385   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00386   *         coming from ADC state reset. Following calls to this function can
00387   *         be used to reconfigure some parameters of ADC_InitTypeDef
00388   *         structure on the fly, without modifying MSP configuration. If ADC
00389   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00390   *         before HAL_ADC_Init().
00391   *         The setting of these parameters is conditioned to ADC state.
00392   *         For parameters constraints, see comments of structure
00393   *         "ADC_InitTypeDef".
00394   * @note   This function configures the ADC within 2 scopes: scope of entire
00395   *         ADC and scope of regular group. For parameters details, see comments
00396   *         of structure "ADC_InitTypeDef".
00397   * @note   Parameters related to common ADC registers (ADC clock mode) are set
00398   *         only if all ADCs are disabled.
00399   *         If this is not the case, these common parameters setting are
00400   *         bypassed without error reporting: it can be the intended behaviour in
00401   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00402   *         without  disabling the other ADCs.
00403   * @param hadc ADC handle
00404   * @retval HAL status
00405   */
00406 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
00407 {
00408   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00409   uint32_t tmpCFGR;
00410   uint32_t tmp_adc_reg_is_conversion_on_going;
00411   __IO uint32_t wait_loop_index = 0UL;
00412   uint32_t tmp_adc_is_conversion_on_going_regular;
00413   uint32_t tmp_adc_is_conversion_on_going_injected;
00414
00415   /* Check ADC handle */
00416   if (hadc == NULL)
00417   {
00418     return HAL_ERROR;
00419   }
00420
00421   /* Check the parameters */
00422   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00423   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00424   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00425   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00426   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00427   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00428   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00429   assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
00430   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00431   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00432   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00433   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00434
00435   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00436   {
00437     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00438     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00439
00440     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00441     {
00442       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00443     }
00444   }
00445
00446   /* DISCEN and CONT bits cannot be set at the same time */
00447   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00448
00449   /* Actions performed only if ADC is coming from state reset:                */
00450   /* - Initialization of ADC MSP                                              */
00451   if (hadc->State == HAL_ADC_STATE_RESET)
00452   {
00453 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00454     /* Init the ADC Callback settings */
00455     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
00456     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
00457     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
00458     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
00459     hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
00460     hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak callback */
00461     hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
00462     hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
00463     hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
00464
00465     if (hadc->MspInitCallback == NULL)
00466     {
00467       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
00468     }
00469
00470     /* Init the low level hardware */
00471     hadc->MspInitCallback(hadc);
00472 #else
00473     /* Init the low level hardware */
00474     HAL_ADC_MspInit(hadc);
00475 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00476
00477     /* Set ADC error code to none */
00478     ADC_CLEAR_ERRORCODE(hadc);
00479
00480     /* Initialize Lock */
00481     hadc->Lock = HAL_UNLOCKED;
00482   }
00483
00484   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00485   if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
00486   {
00487     /* Disable ADC deep power down mode */
00488     LL_ADC_DisableDeepPowerDown(hadc->Instance);
00489
00490     /* System was in deep power down mode, calibration must
00491      be relaunched or a previously saved calibration factor
00492      re-applied once the ADC voltage regulator is enabled */
00493   }
00494
00495   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00496   {
00497     /* Enable ADC internal voltage regulator */
00498     LL_ADC_EnableInternalRegulator(hadc->Instance);
00499
00500     /* Note: Variable divided by 2 to compensate partially              */
00501     /*       CPU processing cycles, scaling in us split to not          */
00502     /*       exceed 32 bits register capacity and handle low frequency. */
00503     wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
00504     while (wait_loop_index != 0UL)
00505     {
00506       wait_loop_index--;
00507     }
00508   }
00509
00510   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00511   /* or not ADC is coming from state reset (if any potential problem of       */
00512   /* clocking, voltage regulator would not be enabled).                       */
00513   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00514   {
00515     /* Update ADC state machine to error */
00516     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00517
00518     /* Set ADC error code to ADC peripheral internal error */
00519     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00520
00521     tmp_hal_status = HAL_ERROR;
00522   }
00523
00524   /* Configuration of ADC parameters if previous preliminary actions are      */
00525   /* correctly completed and if there is no conversion on going on regular    */
00526   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00527   /* called to update a parameter on the fly).                                */
00528   tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00529
00530   if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
00531       && (tmp_adc_reg_is_conversion_on_going == 0UL)
00532      )
00533   {
00534     /* Set ADC state */
00535     ADC_STATE_CLR_SET(hadc->State,
00536                       HAL_ADC_STATE_REG_BUSY,
00537                       HAL_ADC_STATE_BUSY_INTERNAL);
00538
00539     /* Configuration of common ADC parameters                                 */
00540
00541     /* Parameters update conditioned to ADC state:                            */
00542     /* Parameters that can be updated only when ADC is disabled:              */
00543     /*  - clock configuration                                                 */
00544     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00545     {
00546       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00547       {
00548         /* Reset configuration of ADC common register CCR:                      */
00549         /*                                                                      */
00550         /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00551         /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00552         /*    source and sets the clock division factor.                        */
00553         /*                                                                      */
00554         /* Some parameters of this register are not reset, since they are set   */
00555         /* by other functions and must be kept in case of usage of this         */
00556         /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00557         /* without needing to reconfigure all other ADC groups/channels         */
00558         /* parameters):                                                         */
00559         /*   - when multimode feature is available, multimode-related           */
00560         /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
00561         /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
00562         /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00563         /*     (set into HAL_ADC_ConfigChannel() or                             */
00564         /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00565         LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
00566       }
00567     }
00568
00569     /* Configuration of ADC:                                                  */
00570     /*  - resolution                               Init.Resolution            */
00571     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00572     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00573     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00574     /*  - overrun                                  Init.Overrun               */
00575     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00576     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
00577 #if defined(ADC_VER_V5_3)
00578       tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
00579                   hadc->Init.Overrun                                                    |
00580                   hadc->Init.Resolution                                                 |
00581                   ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
00582
00583 #else
00584     if((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
00585     {
00586       /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
00587       tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
00588                   hadc->Init.Overrun                                                    |
00589                   hadc->Init.Resolution |(ADC_CFGR_RES_1|ADC_CFGR_RES_0)                |
00590                   ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
00591     }
00592     else
00593     {
00594       tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
00595                   hadc->Init.Overrun                                                    |
00596                   hadc->Init.Resolution                                                 |
00597                   ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
00598     }
00599
00600 #endif /* ADC_VER_V5_3 */
00601
00602     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00603     {
00604       tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
00605     }
00606
00607     /* Enable external trigger if trigger selection is different of software  */
00608     /* start.                                                                 */
00609     /* Note: This configuration keeps the hardware feature of parameter       */
00610     /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00611     /*       software start.                                                  */
00612     if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00613     {
00614       tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
00615                   | hadc->Init.ExternalTrigConvEdge
00616                  );
00617     }
00618
00619     /* Update Configuration Register CFGR */
00620     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
00621
00622     /* Parameters update conditioned to ADC state:                            */
00623     /* Parameters that can be updated when ADC is disabled or enabled without */
00624     /* conversion on going on regular and injected groups:                    */
00625     /*  - Conversion data management      Init.ConversionDataManagement       */
00626     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00627     /*  - Oversampling parameters         Init.Oversampling                   */
00628     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00629     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00630     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
00631         && (tmp_adc_is_conversion_on_going_injected == 0UL)
00632        )
00633     {
00634       tmpCFGR = (
00635                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
00636                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
00637
00638       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
00639
00640       if (hadc->Init.OversamplingMode == ENABLE)
00641       {
00642         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00643         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00644         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00645         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00646
00647       if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
00648             || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
00649         {
00650           /* Multi trigger is not applicable to software-triggered conversions */
00651           assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
00652         }
00653
00654        /* Configuration of Oversampler:                                       */
00655        /*  - Oversampling Ratio                                               */
00656        /*  - Right bit shift                                                  */
00657        /*  - Left bit shift                                                   */
00658        /*  - Triggered mode                                                   */
00659        /*  - Oversampling mode (continued/resumed)                            */
00660        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
00661                                          ADC_CFGR2_ROVSE                       |
00662                                          ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
00663                                          hadc->Init.Oversampling.RightBitShift |
00664                                          hadc->Init.Oversampling.TriggeredMode |
00665                                          hadc->Init.Oversampling.OversamplingStopReset);
00666
00667       }
00668       else
00669       {
00670         /* Disable ADC oversampling scope on ADC group regular */
00671         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00672       }
00673
00674       /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
00675       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
00676
00677       /* Configure the BOOST Mode */
00678       ADC_ConfigureBoostMode(hadc);
00679     }
00680
00681     /* Configuration of regular group sequencer:                              */
00682     /* - if scan mode is disabled, regular channels sequence length is set to */
00683     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00684     /*   Parameter "NbrOfConversion" is discarded.                            */
00685     /*   Note: Scan mode is not present by hardware on this device, but       */
00686     /*   emulated by software for alignment over all STM32 devices.           */
00687     /* - if scan mode is enabled, regular channels sequence length is set to  */
00688     /*   parameter "NbrOfConversion".                                         */
00689
00690     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00691     {
00692       /* Set number of ranks in regular group sequencer */
00693       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
00694     }
00695     else
00696     {
00697       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00698     }
00699
00700     /* Initialize the ADC state */
00701     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00702     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00703   }
00704   else
00705   {
00706     /* Update ADC state machine to error */
00707     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00708
00709     tmp_hal_status = HAL_ERROR;
00710   }
00711
00712   /* Return function status */
00713   return tmp_hal_status;
00714 }
00715
00716 /**
00717   * @brief  Deinitialize the ADC peripheral registers to their default reset
00718   *         values, with deinitialization of the ADC MSP.
00719   * @note   For devices with several ADCs: reset of ADC common registers is done
00720   *         only if all ADCs sharing the same common group are disabled.
00721   *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
00722   *         all ADC instances use the same core clock at RCC level, disabling
00723   *         the core clock reset all ADC instances).
00724   *         If this is not the case, reset of these common parameters reset is
00725   *         bypassed without error reporting: it can be the intended behavior in
00726   *         case of reset of a single ADC while the other ADCs sharing the same
00727   *         common group is still running.
00728   * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
00729   *         this saves more power by reducing leakage currents
00730   *         and is particularly interesting before entering MCU low-power modes.
00731   * @param hadc ADC handle
00732   * @retval HAL status
00733   */
00734 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
00735 {
00736   HAL_StatusTypeDef tmp_hal_status;
00737
00738   /* Check ADC handle */
00739   if (hadc == NULL)
00740   {
00741     return HAL_ERROR;
00742   }
00743
00744   /* Check the parameters */
00745   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00746
00747   /* Set ADC state */
00748   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00749
00750   /* Stop potential conversion on going */
00751   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00752
00753   /* Disable ADC peripheral if conversions are effectively stopped            */
00754   /* Flush register JSQR: reset the queue sequencer when injected             */
00755   /* queue sequencer is enabled and ADC disabled.                             */
00756   /* The software and hardware triggers of the injected sequence are both     */
00757   /* internally disabled just after the completion of the last valid          */
00758   /* injected sequence.                                                       */
00759   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00760
00761   /* Disable ADC peripheral if conversions are effectively stopped */
00762   if (tmp_hal_status == HAL_OK)
00763   {
00764     /* Disable the ADC peripheral */
00765     tmp_hal_status = ADC_Disable(hadc);
00766
00767     /* Check if ADC is effectively disabled */
00768     if (tmp_hal_status == HAL_OK)
00769     {
00770       /* Change ADC state */
00771       hadc->State = HAL_ADC_STATE_READY;
00772     }
00773   }
00774
00775   /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
00776   /*       and disable return status. In case of status fail, attempt to      */
00777   /*       perform deinitialization anyway and it is up user code in          */
00778   /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
00779   /*       system RCC hard reset.                                             */
00780
00781   /* ========== Reset ADC registers ========== */
00782   /* Reset register IER */
00783   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00784                               ADC_IT_JQOVF | ADC_IT_OVR  |
00785                               ADC_IT_JEOS  | ADC_IT_JEOC |
00786                               ADC_IT_EOS   | ADC_IT_EOC  |
00787                               ADC_IT_EOSMP | ADC_IT_RDY));
00788
00789   /* Reset register ISR */
00790   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00791                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00792                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00793                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00794                               ADC_FLAG_EOSMP | ADC_FLAG_RDY));
00795
00796   /* Reset register CR */
00797   /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
00798      ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
00799      no direct reset applicable.
00800      Update CR register to reset value where doable by software */
00801   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00802   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00803
00804   /* Reset register CFGR */
00805   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |
00806                                   ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |
00807                                   ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |
00808                                   ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |
00809                                   ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  |
00810                                   ADC_CFGR_RES     | ADC_CFGR_DMNGT);
00811   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00812
00813   /* Reset register CFGR2 */
00814   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
00815             ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
00816
00817   /* Reset register SMPR1 */
00818   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
00819
00820   /* Reset register SMPR2 */
00821   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00822             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00823             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
00824
00825   /* Reset register LTR1 and HTR1 */
00826   CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT);
00827   CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT);
00828
00829   /* Reset register LTR2 and HTR2*/
00830   CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR_LT);
00831   CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR_HT);
00832
00833   /* Reset register LTR3 and HTR3 */
00834   CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT);
00835   CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT);
00836
00837   /* Reset register SQR1 */
00838   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00839             ADC_SQR1_SQ1 | ADC_SQR1_L);
00840
00841   /* Reset register SQR2 */
00842   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00843             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00844
00845   /* Reset register SQR3 */
00846   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00847             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00848
00849   /* Reset register SQR4 */
00850   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00851
00852   /* Register JSQR was reset when the ADC was disabled */
00853
00854   /* Reset register DR */
00855   /* bits in access mode read only, no direct reset applicable*/
00856
00857   /* Reset register OFR1 */
00858   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00859   /* Reset register OFR2 */
00860   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00861   /* Reset register OFR3 */
00862   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00863   /* Reset register OFR4 */
00864   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00865
00866   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00867   /* bits in access mode read only, no direct reset applicable*/
00868
00869   /* Reset register AWD2CR */
00870   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00871
00872   /* Reset register AWD3CR */
00873   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00874
00875   /* Reset register DIFSEL */
00876   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00877
00878   /* Reset register CALFACT */
00879   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00880
00881
00882   /* ========== Reset common ADC registers ========== */
00883
00884   /* Software is allowed to change common parameters only when all the other
00885      ADCs are disabled.   */
00886   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00887   {
00888     /* Reset configuration of ADC common register CCR:
00889       - clock mode: CKMODE, PRESCEN
00890       - multimode related parameters(when this feature is available): DELAY, DUAL
00891        (set into  HAL_ADCEx_MultiModeConfigChannel() API)
00892       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00893         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00894     */
00895     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
00896   }
00897
00898   /* DeInit the low level hardware.
00899
00900      For example:
00901     __HAL_RCC_ADC_FORCE_RESET();
00902     __HAL_RCC_ADC_RELEASE_RESET();
00903     __HAL_RCC_ADC_CLK_DISABLE();
00904
00905     Keep in mind that all ADCs use the same clock: disabling
00906     the clock will reset all ADCs.
00907
00908   */
00909 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00910   if (hadc->MspDeInitCallback == NULL)
00911   {
00912     hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
00913   }
00914
00915   /* DeInit the low level hardware: RCC clock, NVIC */
00916   hadc->MspDeInitCallback(hadc);
00917 #else
00918   /* DeInit the low level hardware: RCC clock, NVIC */
00919   HAL_ADC_MspDeInit(hadc);
00920 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00921
00922   /* Set ADC error code to none */
00923   ADC_CLEAR_ERRORCODE(hadc);
00924
00925   /* Reset injected channel configuration parameters */
00926   hadc->InjectionConfig.ContextQueue = 0;
00927   hadc->InjectionConfig.ChannelCount = 0;
00928
00929   /* Set ADC state */
00930   hadc->State = HAL_ADC_STATE_RESET;
00931
00932   /* Process unlocked */
00933   __HAL_UNLOCK(hadc);
00934
00935   /* Return function status */
00936   return tmp_hal_status;
00937 }
00938
00939 /**
00940   * @brief  Initialize the ADC MSP.
00941   * @param hadc ADC handle
00942   * @retval None
00943   */
00944 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
00945 {
00946   /* Prevent unused argument(s) compilation warning */
00947   UNUSED(hadc);
00948
00949   /* NOTE : This function should not be modified. When the callback is needed,
00950             function HAL_ADC_MspInit must be implemented in the user file.
00951    */
00952 }
00953
00954 /**
00955   * @brief  DeInitialize the ADC MSP.
00956   * @param hadc ADC handle
00957   * @note   All ADC instances use the same core clock at RCC level, disabling
00958   *         the core clock reset all ADC instances).
00959   * @retval None
00960   */
00961 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
00962 {
00963   /* Prevent unused argument(s) compilation warning */
00964   UNUSED(hadc);
00965
00966   /* NOTE : This function should not be modified. When the callback is needed,
00967             function HAL_ADC_MspDeInit must be implemented in the user file.
00968    */
00969 }
00970
00971 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00972 /**
00973   * @brief  Register a User ADC Callback
00974   *         To be used instead of the weak predefined callback
00975   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
00976   *                the configuration information for the specified ADC.
00977   * @param  CallbackID ID of the callback to be registered
00978   *         This parameter can be one of the following values:
00979   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
00980   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
00981   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
00982   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
00983   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
00984   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
00985   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
00986   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
00987   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
00988   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
00989   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
00990   * @param  pCallback pointer to the Callback function
00991   * @retval HAL status
00992   */
00993 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
00994 {
00995   HAL_StatusTypeDef status = HAL_OK;
00996
00997   if (pCallback == NULL)
00998   {
00999     /* Update the error code */
01000     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01001
01002     return HAL_ERROR;
01003   }
01004
01005   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
01006   {
01007     switch (CallbackID)
01008     {
01009       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
01010         hadc->ConvCpltCallback = pCallback;
01011         break;
01012
01013       case HAL_ADC_CONVERSION_HALF_CB_ID :
01014         hadc->ConvHalfCpltCallback = pCallback;
01015         break;
01016
01017       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
01018         hadc->LevelOutOfWindowCallback = pCallback;
01019         break;
01020
01021       case HAL_ADC_ERROR_CB_ID :
01022         hadc->ErrorCallback = pCallback;
01023         break;
01024
01025       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
01026         hadc->InjectedConvCpltCallback = pCallback;
01027         break;
01028
01029       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
01030         hadc->InjectedQueueOverflowCallback = pCallback;
01031         break;
01032
01033       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01034         hadc->LevelOutOfWindow2Callback = pCallback;
01035         break;
01036
01037       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01038         hadc->LevelOutOfWindow3Callback = pCallback;
01039         break;
01040
01041       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01042         hadc->EndOfSamplingCallback = pCallback;
01043         break;
01044
01045       case HAL_ADC_MSPINIT_CB_ID :
01046         hadc->MspInitCallback = pCallback;
01047         break;
01048
01049       case HAL_ADC_MSPDEINIT_CB_ID :
01050         hadc->MspDeInitCallback = pCallback;
01051         break;
01052
01053       default :
01054         /* Update the error code */
01055         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01056
01057         /* Return error status */
01058         status = HAL_ERROR;
01059         break;
01060     }
01061   }
01062   else if (HAL_ADC_STATE_RESET == hadc->State)
01063   {
01064     switch (CallbackID)
01065     {
01066       case HAL_ADC_MSPINIT_CB_ID :
01067         hadc->MspInitCallback = pCallback;
01068         break;
01069
01070       case HAL_ADC_MSPDEINIT_CB_ID :
01071         hadc->MspDeInitCallback = pCallback;
01072         break;
01073
01074       default :
01075         /* Update the error code */
01076         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01077
01078         /* Return error status */
01079         status = HAL_ERROR;
01080         break;
01081     }
01082   }
01083   else
01084   {
01085     /* Update the error code */
01086     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01087
01088     /* Return error status */
01089     status =  HAL_ERROR;
01090   }
01091
01092   return status;
01093 }
01094
01095 /**
01096   * @brief  Unregister a ADC Callback
01097   *         ADC callback is redirected to the weak predefined callback
01098   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
01099   *                the configuration information for the specified ADC.
01100   * @param  CallbackID ID of the callback to be unregistered
01101   *         This parameter can be one of the following values:
01102   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
01103   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
01104   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
01105   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
01106   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
01107   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
01108   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
01109   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
01110   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
01111   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
01112   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
01113   * @retval HAL status
01114   */
01115 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
01116 {
01117   HAL_StatusTypeDef status = HAL_OK;
01118
01119   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
01120   {
01121     switch (CallbackID)
01122     {
01123       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
01124         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
01125         break;
01126
01127       case HAL_ADC_CONVERSION_HALF_CB_ID :
01128         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
01129         break;
01130
01131       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
01132         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
01133         break;
01134
01135       case HAL_ADC_ERROR_CB_ID :
01136         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
01137         break;
01138
01139       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
01140         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
01141         break;
01142
01143       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
01144         hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
01145         break;
01146
01147       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01148         hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
01149         break;
01150
01151       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01152         hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
01153         break;
01154
01155       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01156         hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
01157         break;
01158
01159       case HAL_ADC_MSPINIT_CB_ID :
01160         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
01161         break;
01162
01163       case HAL_ADC_MSPDEINIT_CB_ID :
01164         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
01165         break;
01166
01167       default :
01168         /* Update the error code */
01169         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01170
01171         /* Return error status */
01172         status =  HAL_ERROR;
01173         break;
01174     }
01175   }
01176   else if (HAL_ADC_STATE_RESET == hadc->State)
01177   {
01178     switch (CallbackID)
01179     {
01180       case HAL_ADC_MSPINIT_CB_ID :
01181         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
01182         break;
01183
01184       case HAL_ADC_MSPDEINIT_CB_ID :
01185         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
01186         break;
01187
01188       default :
01189         /* Update the error code */
01190         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01191
01192         /* Return error status */
01193         status =  HAL_ERROR;
01194         break;
01195     }
01196   }
01197   else
01198   {
01199     /* Update the error code */
01200     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01201
01202     /* Return error status */
01203     status =  HAL_ERROR;
01204   }
01205
01206   return status;
01207 }
01208
01209 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01210
01211 /**
01212   * @}
01213   */
01214
01215 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
01216   * @brief    ADC IO operation functions
01217   *
01218 @verbatim
01219  ===============================================================================
01220                       ##### IO operation functions #####
01221  ===============================================================================
01222     [..]  This section provides functions allowing to:
01223       (+) Start conversion of regular group.
01224       (+) Stop conversion of regular group.
01225       (+) Poll for conversion complete on regular group.
01226       (+) Poll for conversion event.
01227       (+) Get result of regular channel conversion.
01228       (+) Start conversion of regular group and enable interruptions.
01229       (+) Stop conversion of regular group and disable interruptions.
01230       (+) Handle ADC interrupt request
01231       (+) Start conversion of regular group and enable DMA transfer.
01232       (+) Stop conversion of regular group and disable ADC DMA transfer.
01233 @endverbatim
01234   * @{
01235   */
01236
01237 /**
01238   * @brief  Enable ADC, start conversion of regular group.
01239   * @note   Interruptions enabled in this function: None.
01240   * @note   Case of multimode enabled (when multimode feature is available):
01241   *           if ADC is Slave, ADC is enabled but conversion is not started,
01242   *           if ADC is master, ADC is enabled and multimode conversion is started.
01243   * @param hadc ADC handle
01244   * @retval HAL status
01245   */
01246 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
01247 {
01248   HAL_StatusTypeDef tmp_hal_status;
01249   const ADC_TypeDef *tmpADC_Master;
01250   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01251
01252   /* Check the parameters */
01253   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01254
01255   /* Perform ADC enable and conversion start if no conversion is on going */
01256   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01257   {
01258     /* Process locked */
01259     __HAL_LOCK(hadc);
01260
01261     /* Enable the ADC peripheral */
01262     tmp_hal_status = ADC_Enable(hadc);
01263
01264     /* Start conversion if ADC is effectively enabled */
01265     if (tmp_hal_status == HAL_OK)
01266     {
01267       /* Set ADC state                                                        */
01268       /* - Clear state bitfield related to regular group conversion results   */
01269       /* - Set state bitfield related to regular operation                    */
01270       ADC_STATE_CLR_SET(hadc->State,
01271                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01272                         HAL_ADC_STATE_REG_BUSY);
01273
01274       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01275         - if ADC instance is master or if multimode feature is not available
01276         - if multimode setting is disabled (ADC instance slave in independent mode) */
01277       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01278           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01279          )
01280       {
01281         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01282       }
01283
01284       /* Set ADC error code */
01285       /* Check if a conversion is on going on ADC group injected */
01286       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01287       {
01288         /* Reset ADC error code fields related to regular conversions only */
01289         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01290       }
01291       else
01292       {
01293         /* Reset all ADC error code fields */
01294         ADC_CLEAR_ERRORCODE(hadc);
01295       }
01296
01297       /* Clear ADC group regular conversion flag and overrun flag               */
01298       /* (To ensure of no unknown state from potential previous ADC operations) */
01299       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01300
01301       /* Process unlocked */
01302       /* Unlock before starting ADC conversions: in case of potential         */
01303       /* interruption, to let the process to ADC IRQ Handler.                 */
01304       __HAL_UNLOCK(hadc);
01305
01306       /* Enable conversion of regular group.                                  */
01307       /* If software start has been selected, conversion starts immediately.  */
01308       /* If external trigger has been selected, conversion will start at next */
01309       /* trigger event.                                                       */
01310       /* Case of multimode enabled (when multimode feature is available):     */
01311       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01312       /*    enabled only (conversion is not started),                         */
01313       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01314       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01315           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01316           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01317           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01318          )
01319       {
01320         /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
01321         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01322         {
01323           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01324         }
01325
01326         /* Start ADC group regular conversion */
01327         LL_ADC_REG_StartConversion(hadc->Instance);
01328       }
01329       else
01330       {
01331         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
01332         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01333         /* if Master ADC JAUTO bit is set, update Slave State in setting
01334            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
01335         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01336         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
01337         {
01338           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01339         }
01340
01341       }
01342     }
01343     else
01344     {
01345       /* Process unlocked */
01346       __HAL_UNLOCK(hadc);
01347     }
01348   }
01349   else
01350   {
01351     tmp_hal_status = HAL_BUSY;
01352   }
01353
01354   /* Return function status */
01355   return tmp_hal_status;
01356 }
01357
01358 /**
01359   * @brief  Stop ADC conversion of regular group (and injected channels in
01360   *         case of auto_injection mode), disable ADC peripheral.
01361   * @note:  ADC peripheral disable is forcing stop of potential
01362   *         conversion on injected group. If injected group is under use, it
01363   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01364   * @param hadc ADC handle
01365   * @retval HAL status.
01366   */
01367 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
01368 {
01369   HAL_StatusTypeDef tmp_hal_status;
01370
01371   /* Check the parameters */
01372   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01373
01374   /* Process locked */
01375   __HAL_LOCK(hadc);
01376
01377   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01378   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01379
01380   /* Disable ADC peripheral if conversions are effectively stopped */
01381   if (tmp_hal_status == HAL_OK)
01382   {
01383     /* 2. Disable the ADC peripheral */
01384     tmp_hal_status = ADC_Disable(hadc);
01385
01386     /* Check if ADC is effectively disabled */
01387     if (tmp_hal_status == HAL_OK)
01388     {
01389       /* Set ADC state */
01390       ADC_STATE_CLR_SET(hadc->State,
01391                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01392                         HAL_ADC_STATE_READY);
01393     }
01394   }
01395
01396   /* Process unlocked */
01397   __HAL_UNLOCK(hadc);
01398
01399   /* Return function status */
01400   return tmp_hal_status;
01401 }
01402
01403 /**
01404   * @brief  Wait for regular group conversion to be completed.
01405   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
01406   *         conversion) are cleared by this function, with an exception:
01407   *         if low power feature "LowPowerAutoWait" is enabled, flags are
01408   *         not cleared to not interfere with this feature until data register
01409   *         is read using function HAL_ADC_GetValue().
01410   * @note   This function cannot be used in a particular setup: ADC configured
01411   *         in DMA mode and polling for end of each conversion (ADC init
01412   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
01413   *         In this case, DMA resets the flag EOC and polling cannot be
01414   *         performed on each conversion. Nevertheless, polling can still
01415   *         be performed on the complete sequence (ADC init
01416   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
01417   * @param hadc ADC handle
01418   * @param Timeout Timeout value in millisecond.
01419   * @retval HAL status
01420   */
01421 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
01422 {
01423   uint32_t tickstart;
01424   uint32_t tmp_Flag_End;
01425   uint32_t tmp_cfgr;
01426   const ADC_TypeDef *tmpADC_Master;
01427   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01428
01429   /* Check the parameters */
01430   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01431
01432   /* If end of conversion selected to end of sequence conversions */
01433   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01434   {
01435     tmp_Flag_End = ADC_FLAG_EOS;
01436   }
01437   /* If end of conversion selected to end of unitary conversion */
01438   else /* ADC_EOC_SINGLE_CONV */
01439   {
01440     /* Verification that ADC configuration is compliant with polling for      */
01441     /* each conversion:                                                       */
01442     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
01443     /* several ranks and polling for end of each conversion.                  */
01444     /* For code simplicity sake, this particular case is generalized to       */
01445     /* ADC configured in DMA mode and and polling for end of each conversion. */
01446     if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01447         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01448         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01449        )
01450     {
01451       /* Check DMNGT bit in handle ADC CFGR register */
01452       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
01453       {
01454         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01455         return HAL_ERROR;
01456       }
01457       else
01458       {
01459         tmp_Flag_End = (ADC_FLAG_EOC);
01460       }
01461     }
01462     else
01463     {
01464       /* Check ADC DMA mode in multimode on ADC group regular */
01465       if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
01466       {
01467         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01468         return HAL_ERROR;
01469       }
01470       else
01471       {
01472         tmp_Flag_End = (ADC_FLAG_EOC);
01473       }
01474     }
01475   }
01476
01477   /* Get tick count */
01478   tickstart = HAL_GetTick();
01479
01480   /* Wait until End of unitary conversion or sequence conversions flag is raised */
01481   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
01482   {
01483     /* Check if timeout is disabled (set to infinite wait) */
01484     if (Timeout != HAL_MAX_DELAY)
01485     {
01486       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01487       {
01488         /* Update ADC state machine to timeout */
01489         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01490
01491         /* Process unlocked */
01492         __HAL_UNLOCK(hadc);
01493
01494         return HAL_TIMEOUT;
01495       }
01496     }
01497   }
01498
01499   /* Update ADC state machine */
01500   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01501
01502   /* Determine whether any further conversion upcoming on group regular       */
01503   /* by external trigger, continuous mode or scan sequence on going.          */
01504   if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
01505       && (hadc->Init.ContinuousConvMode == DISABLE)
01506      )
01507   {
01508     /* Check whether end of sequence is reached */
01509     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
01510     {
01511       /* Set ADC state */
01512       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01513
01514       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
01515       {
01516         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01517       }
01518     }
01519   }
01520
01521   /* Get relevant register CFGR in ADC instance of ADC master or slave        */
01522   /* in function of multimode state (for devices with multimode               */
01523   /* available).                                                              */
01524   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01525       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01526       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01527       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01528      )
01529   {
01530     /* Retrieve handle ADC CFGR register */
01531     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01532   }
01533   else
01534   {
01535     /* Retrieve Master ADC CFGR register */
01536     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01537     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01538   }
01539
01540   /* Clear polled flag */
01541   if (tmp_Flag_End == ADC_FLAG_EOS)
01542   {
01543     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
01544   }
01545   else
01546   {
01547     /* Clear end of conversion EOC flag of regular group if low power feature */
01548     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01549     /* until data register is read using function HAL_ADC_GetValue().         */
01550     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
01551     {
01552       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
01553     }
01554   }
01555
01556   /* Return function status */
01557   return HAL_OK;
01558 }
01559
01560 /**
01561   * @brief  Poll for ADC event.
01562   * @param hadc ADC handle
01563   * @param EventType the ADC event type.
01564   *          This parameter can be one of the following values:
01565   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01566   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
01567   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
01568   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
01569   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01570   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01571   * @param Timeout Timeout value in millisecond.
01572   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01573   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01574   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
01575   *         by a new converted data as soon as OVR is cleared.
01576   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01577   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01578   * @retval HAL status
01579   */
01580 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
01581 {
01582   uint32_t tickstart;
01583
01584   /* Check the parameters */
01585   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01586   assert_param(IS_ADC_EVENT_TYPE(EventType));
01587
01588   /* Get tick count */
01589   tickstart = HAL_GetTick();
01590
01591   /* Check selected event flag */
01592   while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01593   {
01594     /* Check if timeout is disabled (set to infinite wait) */
01595     if (Timeout != HAL_MAX_DELAY)
01596     {
01597       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01598       {
01599         /* Update ADC state machine to timeout */
01600         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01601
01602         /* Process unlocked */
01603         __HAL_UNLOCK(hadc);
01604
01605         return HAL_TIMEOUT;
01606       }
01607     }
01608   }
01609
01610   switch (EventType)
01611   {
01612     /* End Of Sampling event */
01613     case ADC_EOSMP_EVENT:
01614       /* Set ADC state */
01615       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01616
01617       /* Clear the End Of Sampling flag */
01618       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01619
01620       break;
01621
01622     /* Analog watchdog (level out of window) event */
01623     /* Note: In case of several analog watchdog enabled, if needed to know      */
01624     /* which one triggered and on which ADCx, test ADC state of analog watchdog */
01625     /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
01626     /* For example:                                                             */
01627     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
01628     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
01629     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
01630
01631     /* Check analog watchdog 1 flag */
01632     case ADC_AWD_EVENT:
01633       /* Set ADC state */
01634       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01635
01636       /* Clear ADC analog watchdog flag */
01637       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01638
01639       break;
01640
01641     /* Check analog watchdog 2 flag */
01642     case ADC_AWD2_EVENT:
01643       /* Set ADC state */
01644       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01645
01646       /* Clear ADC analog watchdog flag */
01647       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01648
01649       break;
01650
01651     /* Check analog watchdog 3 flag */
01652     case ADC_AWD3_EVENT:
01653       /* Set ADC state */
01654       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01655
01656       /* Clear ADC analog watchdog flag */
01657       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01658
01659       break;
01660
01661     /* Injected context queue overflow event */
01662     case ADC_JQOVF_EVENT:
01663       /* Set ADC state */
01664       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01665
01666       /* Set ADC error code to Injected context queue overflow */
01667       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01668
01669       /* Clear ADC Injected context queue overflow flag */
01670       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01671
01672       break;
01673
01674     /* Overrun event */
01675     default: /* Case ADC_OVR_EVENT */
01676       /* If overrun is set to overwrite previous data, overrun event is not     */
01677       /* considered as an error.                                                */
01678       /* (cf ref manual "Managing conversions without using the DMA and without */
01679       /* overrun ")                                                             */
01680       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01681       {
01682         /* Set ADC state */
01683         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01684
01685         /* Set ADC error code to overrun */
01686         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01687       }
01688       else
01689       {
01690         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01691            otherwise, data register is potentially overwritten by new converted data as soon
01692            as OVR is cleared. */
01693         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01694       }
01695       break;
01696   }
01697
01698   /* Return function status */
01699   return HAL_OK;
01700 }
01701
01702 /**
01703   * @brief  Enable ADC, start conversion of regular group with interruption.
01704   * @note   Interruptions enabled in this function according to initialization
01705   *         setting : EOC (end of conversion), EOS (end of sequence),
01706   *         OVR overrun.
01707   *         Each of these interruptions has its dedicated callback function.
01708   * @note   Case of multimode enabled (when multimode feature is available):
01709   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
01710   *         ADC Master.
01711   *         For ADC Slave, ADC is enabled only (conversion is not started).
01712   *         For ADC Master, ADC is enabled and multimode conversion is started.
01713   * @note   To guarantee a proper reset of all interruptions once all the needed
01714   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01715   *         a correct stop of the IT-based conversions.
01716   * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
01717   *         interruption. If required (e.g. in case of oversampling with trigger
01718   *         mode), the user must:
01719   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
01720   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
01721   *          before calling HAL_ADC_Start_IT().
01722   * @param hadc ADC handle
01723   * @retval HAL status
01724   */
01725 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
01726 {
01727   HAL_StatusTypeDef tmp_hal_status;
01728   const ADC_TypeDef *tmpADC_Master;
01729   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01730
01731   /* Check the parameters */
01732   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01733
01734   /* Perform ADC enable and conversion start if no conversion is on going */
01735   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01736   {
01737     /* Process locked */
01738     __HAL_LOCK(hadc);
01739
01740     /* Enable the ADC peripheral */
01741     tmp_hal_status = ADC_Enable(hadc);
01742
01743     /* Start conversion if ADC is effectively enabled */
01744     if (tmp_hal_status == HAL_OK)
01745     {
01746       /* Set ADC state                                                        */
01747       /* - Clear state bitfield related to regular group conversion results   */
01748       /* - Set state bitfield related to regular operation                    */
01749       ADC_STATE_CLR_SET(hadc->State,
01750                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01751                         HAL_ADC_STATE_REG_BUSY);
01752
01753       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01754         - if ADC instance is master or if multimode feature is not available
01755         - if multimode setting is disabled (ADC instance slave in independent mode) */
01756       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01757           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01758          )
01759       {
01760         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01761       }
01762
01763       /* Set ADC error code */
01764       /* Check if a conversion is on going on ADC group injected */
01765       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
01766       {
01767         /* Reset ADC error code fields related to regular conversions only */
01768         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01769       }
01770       else
01771       {
01772         /* Reset all ADC error code fields */
01773         ADC_CLEAR_ERRORCODE(hadc);
01774       }
01775
01776       /* Clear ADC group regular conversion flag and overrun flag               */
01777       /* (To ensure of no unknown state from potential previous ADC operations) */
01778       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01779
01780       /* Process unlocked */
01781       /* Unlock before starting ADC conversions: in case of potential         */
01782       /* interruption, to let the process to ADC IRQ Handler.                 */
01783       __HAL_UNLOCK(hadc);
01784
01785       /* Disable all interruptions before enabling the desired ones */
01786       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01787
01788       /* Enable ADC end of conversion interrupt */
01789       switch (hadc->Init.EOCSelection)
01790       {
01791         case ADC_EOC_SEQ_CONV:
01792           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01793           break;
01794         /* case ADC_EOC_SINGLE_CONV */
01795         default:
01796           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01797           break;
01798       }
01799
01800       /* Enable ADC overrun interrupt */
01801       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01802          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01803          behavior and no CPU time is lost for a non-processed interruption */
01804       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01805       {
01806         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01807       }
01808
01809       /* Enable conversion of regular group.                                  */
01810       /* If software start has been selected, conversion starts immediately.  */
01811       /* If external trigger has been selected, conversion will start at next */
01812       /* trigger event.                                                       */
01813       /* Case of multimode enabled (when multimode feature is available):     */
01814       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01815       /*    enabled only (conversion is not started),                         */
01816       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01817       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01818           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01819           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01820           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01821          )
01822       {
01823         /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
01824         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01825         {
01826           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01827
01828           /* Enable as well injected interruptions in case
01829            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01830            allows to start regular and injected conversions when JAUTO is
01831            set with a single call to HAL_ADC_Start_IT() */
01832           switch (hadc->Init.EOCSelection)
01833           {
01834             case ADC_EOC_SEQ_CONV:
01835               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01836               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01837               break;
01838             /* case ADC_EOC_SINGLE_CONV */
01839             default:
01840               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01841               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01842               break;
01843           }
01844         }
01845
01846         /* Start ADC group regular conversion */
01847         LL_ADC_REG_StartConversion(hadc->Instance);
01848       }
01849       else
01850       {
01851         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
01852         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01853         /* if Master ADC JAUTO bit is set, Slave injected interruptions
01854            are enabled nevertheless (for same reason as above) */
01855         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01856         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
01857         {
01858           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
01859              and in resetting HAL_ADC_STATE_INJ_EOC bit */
01860           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01861           /* Next, set Slave injected interruptions */
01862           switch (hadc->Init.EOCSelection)
01863           {
01864             case ADC_EOC_SEQ_CONV:
01865               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01866               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01867               break;
01868             /* case ADC_EOC_SINGLE_CONV */
01869             default:
01870               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01871               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01872               break;
01873           }
01874         }
01875       }
01876     }
01877     else
01878     {
01879       /* Process unlocked */
01880       __HAL_UNLOCK(hadc);
01881     }
01882
01883   }
01884   else
01885   {
01886     tmp_hal_status = HAL_BUSY;
01887   }
01888
01889   /* Return function status */
01890   return tmp_hal_status;
01891 }
01892
01893 /**
01894   * @brief  Stop ADC conversion of regular group (and injected group in
01895   *         case of auto_injection mode), disable interrution of
01896   *         end-of-conversion, disable ADC peripheral.
01897   * @param hadc ADC handle
01898   * @retval HAL status.
01899   */
01900 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
01901 {
01902   HAL_StatusTypeDef tmp_hal_status;
01903
01904   /* Check the parameters */
01905   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01906
01907   /* Process locked */
01908   __HAL_LOCK(hadc);
01909
01910   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01911   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01912
01913   /* Disable ADC peripheral if conversions are effectively stopped */
01914   if (tmp_hal_status == HAL_OK)
01915   {
01916     /* Disable ADC end of conversion interrupt for regular group */
01917     /* Disable ADC overrun interrupt */
01918     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01919
01920     /* 2. Disable the ADC peripheral */
01921     tmp_hal_status = ADC_Disable(hadc);
01922
01923     /* Check if ADC is effectively disabled */
01924     if (tmp_hal_status == HAL_OK)
01925     {
01926       /* Set ADC state */
01927       ADC_STATE_CLR_SET(hadc->State,
01928                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01929                         HAL_ADC_STATE_READY);
01930     }
01931   }
01932
01933   /* Process unlocked */
01934   __HAL_UNLOCK(hadc);
01935
01936   /* Return function status */
01937   return tmp_hal_status;
01938 }
01939
01940 /**
01941   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01942   * @note   Interruptions enabled in this function:
01943   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01944   *         Each of these interruptions has its dedicated callback function.
01945   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
01946   *         is designed for single-ADC mode only. For multimode, the dedicated
01947   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
01948   * @param hadc ADC handle
01949   * @param pData Destination Buffer address.
01950   * @param Length Number of data to be transferred from ADC peripheral to memory
01951   * @retval HAL status.
01952   */
01953 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
01954 {
01955   HAL_StatusTypeDef tmp_hal_status;
01956   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01957
01958   /* Check the parameters */
01959   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01960
01961   /* Perform ADC enable and conversion start if no conversion is on going */
01962   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01963   {
01964     /* Process locked */
01965     __HAL_LOCK(hadc);
01966
01967     /* Ensure that multimode regular conversions are not enabled.   */
01968     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
01969     if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01970         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01971         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01972        )
01973     {
01974       /* Enable the ADC peripheral */
01975       tmp_hal_status = ADC_Enable(hadc);
01976
01977       /* Start conversion if ADC is effectively enabled */
01978       if (tmp_hal_status == HAL_OK)
01979       {
01980         /* Set ADC state                                                        */
01981         /* - Clear state bitfield related to regular group conversion results   */
01982         /* - Set state bitfield related to regular operation                    */
01983         ADC_STATE_CLR_SET(hadc->State,
01984                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01985                           HAL_ADC_STATE_REG_BUSY);
01986
01987         /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01988           - if ADC instance is master or if multimode feature is not available
01989           - if multimode setting is disabled (ADC instance slave in independent mode) */
01990         if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01991             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01992            )
01993         {
01994           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01995         }
01996
01997         /* Check if a conversion is on going on ADC group injected */
01998         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
01999         {
02000           /* Reset ADC error code fields related to regular conversions only */
02001           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02002         }
02003         else
02004         {
02005           /* Reset all ADC error code fields */
02006           ADC_CLEAR_ERRORCODE(hadc);
02007         }
02008
02009         /* Set the DMA transfer complete callback */
02010         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
02011
02012         /* Set the DMA half transfer complete callback */
02013         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
02014
02015         /* Set the DMA error callback */
02016         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
02017
02018
02019         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
02020         /* ADC start (in case of SW start):                                   */
02021
02022         /* Clear regular group conversion flag and overrun flag               */
02023         /* (To ensure of no unknown state from potential previous ADC         */
02024         /* operations)                                                        */
02025         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
02026
02027         /* Process unlocked */
02028         /* Unlock before starting ADC conversions: in case of potential         */
02029         /* interruption, to let the process to ADC IRQ Handler.                 */
02030         __HAL_UNLOCK(hadc);
02031
02032         /* With DMA, overrun event is always considered as an error even if
02033            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
02034            ADC_IT_OVR is enabled. */
02035         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
02036
02037         /* Enable ADC DMA  mode*/
02038         LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
02039
02040         /* Start the DMA channel */
02041         tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
02042
02043         /* Enable conversion of regular group.                                  */
02044         /* If software start has been selected, conversion starts immediately.  */
02045         /* If external trigger has been selected, conversion will start at next */
02046         /* trigger event.                                                       */
02047         /* Start ADC group regular conversion */
02048         LL_ADC_REG_StartConversion(hadc->Instance);
02049       }
02050       else
02051       {
02052         /* Process unlocked */
02053         __HAL_UNLOCK(hadc);
02054       }
02055
02056     }
02057     else
02058     {
02059       tmp_hal_status = HAL_ERROR;
02060       /* Process unlocked */
02061       __HAL_UNLOCK(hadc);
02062     }
02063   }
02064   else
02065   {
02066     tmp_hal_status = HAL_BUSY;
02067   }
02068
02069   /* Return function status */
02070   return tmp_hal_status;
02071 }
02072
02073 /**
02074   * @brief  Stop ADC conversion of regular group (and injected group in
02075   *         case of auto_injection mode), disable ADC DMA transfer, disable
02076   *         ADC peripheral.
02077   * @note:  ADC peripheral disable is forcing stop of potential
02078   *         conversion on ADC group injected. If ADC group injected is under use, it
02079   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
02080   * @note   Case of multimode enabled (when multimode feature is available):
02081   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
02082   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
02083   * @param hadc ADC handle
02084   * @retval HAL status.
02085   */
02086 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
02087 {
02088   HAL_StatusTypeDef tmp_hal_status;
02089
02090   /* Check the parameters */
02091   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02092
02093   /* Process locked */
02094   __HAL_LOCK(hadc);
02095
02096   /* 1. Stop potential ADC group regular conversion on going */
02097   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
02098
02099   /* Disable ADC peripheral if conversions are effectively stopped */
02100   if (tmp_hal_status == HAL_OK)
02101   {
02102     /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
02103     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
02104
02105     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
02106     /* while DMA transfer is on going)                                        */
02107     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
02108     {
02109       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
02110
02111       /* Check if DMA channel effectively disabled */
02112       if (tmp_hal_status != HAL_OK)
02113       {
02114         /* Update ADC state machine to error */
02115         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02116       }
02117     }
02118
02119     /* Disable ADC overrun interrupt */
02120     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
02121
02122     /* 2. Disable the ADC peripheral */
02123     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
02124     /* to keep in memory a potential failing status.                          */
02125     if (tmp_hal_status == HAL_OK)
02126     {
02127       tmp_hal_status = ADC_Disable(hadc);
02128     }
02129     else
02130     {
02131       (void)ADC_Disable(hadc);
02132     }
02133
02134     /* Check if ADC is effectively disabled */
02135     if (tmp_hal_status == HAL_OK)
02136     {
02137       /* Set ADC state */
02138       ADC_STATE_CLR_SET(hadc->State,
02139                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02140                         HAL_ADC_STATE_READY);
02141     }
02142
02143   }
02144
02145   /* Process unlocked */
02146   __HAL_UNLOCK(hadc);
02147
02148   /* Return function status */
02149   return tmp_hal_status;
02150 }
02151
02152 /**
02153   * @brief  Get ADC regular group conversion result.
02154   * @note   Reading register DR automatically clears ADC flag EOC
02155   *         (ADC group regular end of unitary conversion).
02156   * @note   This function does not clear ADC flag EOS
02157   *         (ADC group regular end of sequence conversion).
02158   *         Occurrence of flag EOS rising:
02159   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
02160   *            to flag EOC.
02161   *          - If sequencer is composed of several ranks, during the scan
02162   *            sequence flag EOC only is raised, at the end of the scan sequence
02163   *            both flags EOC and EOS are raised.
02164   *         To clear this flag, either use function:
02165   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
02166   *         model polling: @ref HAL_ADC_PollForConversion()
02167   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
02168   * @param hadc ADC handle
02169   * @retval ADC group regular conversion data
02170   */
02171 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
02172 {
02173   /* Check the parameters */
02174   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02175
02176   /* Note: EOC flag is not cleared here by software because automatically     */
02177   /*       cleared by hardware when reading register DR.                      */
02178
02179   /* Return ADC converted value */
02180   return hadc->Instance->DR;
02181 }
02182
02183 /**
02184   * @brief  Handle ADC interrupt request.
02185   * @param hadc ADC handle
02186   * @retval None
02187   */
02188 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
02189 {
02190   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
02191   uint32_t tmp_isr = hadc->Instance->ISR;
02192   uint32_t tmp_ier = hadc->Instance->IER;
02193   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
02194   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
02195   uint32_t tmp_cfgr;
02196   const ADC_TypeDef *tmpADC_Master;
02197   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02198
02199   /* Check the parameters */
02200   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02201   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
02202
02203   /* ========== Check End of Sampling flag for ADC group regular ========== */
02204   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
02205   {
02206     /* Update state machine on end of sampling status if not in error state */
02207     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02208     {
02209       /* Set ADC state */
02210       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
02211     }
02212
02213     /* End Of Sampling callback */
02214 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02215     hadc->EndOfSamplingCallback(hadc);
02216 #else
02217     HAL_ADCEx_EndOfSamplingCallback(hadc);
02218 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02219
02220     /* Clear regular group conversion flag */
02221     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
02222   }
02223
02224   /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
02225   if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
02226       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
02227   {
02228     /* Update state machine on conversion status if not in error state */
02229     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02230     {
02231       /* Set ADC state */
02232       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02233     }
02234
02235     /* Determine whether any further conversion upcoming on group regular     */
02236     /* by external trigger, continuous mode or scan sequence on going         */
02237     /* to disable interruption.                                               */
02238     if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
02239     {
02240       /* Get relevant register CFGR in ADC instance of ADC master or slave    */
02241       /* in function of multimode state (for devices with multimode           */
02242       /* available).                                                          */
02243       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
02244           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02245           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
02246           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
02247          )
02248       {
02249         /* check CONT bit directly in handle ADC CFGR register */
02250         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02251       }
02252       else
02253       {
02254         /* else need to check Master ADC CONT bit */
02255         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
02256         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
02257       }
02258
02259       /* Carry on if continuous mode is disabled */
02260       if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
02261       {
02262         /* If End of Sequence is reached, disable interrupts */
02263         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
02264         {
02265           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
02266           /* ADSTART==0 (no conversion on going)                              */
02267           if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02268           {
02269             /* Disable ADC end of sequence conversion interrupt */
02270             /* Note: Overrun interrupt was enabled with EOC interrupt in      */
02271             /* HAL_Start_IT(), but is not disabled here because can be used   */
02272             /* by overrun IRQ process below.                                  */
02273             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
02274
02275             /* Set ADC state */
02276             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02277
02278             if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
02279             {
02280               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02281             }
02282           }
02283           else
02284           {
02285             /* Change ADC state to error state */
02286             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02287
02288             /* Set ADC error code to ADC peripheral internal error */
02289             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02290           }
02291         }
02292       }
02293     }
02294
02295     /* Conversion complete callback */
02296     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
02297     /*       to determine if conversion has been triggered from EOC or EOS,   */
02298     /*       possibility to use:                                              */
02299     /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
02300 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02301     hadc->ConvCpltCallback(hadc);
02302 #else
02303     HAL_ADC_ConvCpltCallback(hadc);
02304 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02305
02306     /* Clear regular group conversion flag */
02307     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
02308     /*       conversion flags clear induces the release of the preserved data.*/
02309     /*       Therefore, if the preserved data value is needed, it must be     */
02310     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
02311     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
02312   }
02313
02314   /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
02315   if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
02316       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
02317   {
02318     /* Update state machine on conversion status if not in error state */
02319     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02320     {
02321       /* Set ADC state */
02322       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
02323     }
02324
02325     /* Retrieve ADC configuration */
02326     tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
02327     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
02328     /* Get relevant register CFGR in ADC instance of ADC master or slave  */
02329     /* in function of multimode state (for devices with multimode         */
02330     /* available).                                                        */
02331     if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
02332         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02333         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
02334         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
02335        )
02336     {
02337       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02338     }
02339     else
02340     {
02341       tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
02342       tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
02343     }
02344
02345     /* Disable interruption if no further conversion upcoming by injected     */
02346     /* external trigger or by automatic injected conversion with regular      */
02347     /* group having no further conversion upcoming (same conditions as        */
02348     /* regular group interruption disabling above),                           */
02349     /* and if injected scan sequence is completed.                            */
02350     if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
02351         ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
02352          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
02353           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
02354     {
02355       /* If End of Sequence is reached, disable interrupts */
02356       if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
02357       {
02358         /* Particular case if injected contexts queue is enabled:             */
02359         /* when the last context has been fully processed, JSQR is reset      */
02360         /* by the hardware. Even if no injected conversion is planned to come */
02361         /* (queue empty, triggers are ignored), it can start again            */
02362         /* immediately after setting a new context (JADSTART is still set).   */
02363         /* Therefore, state of HAL ADC injected group is kept to busy.        */
02364         if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
02365         {
02366           /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
02367           /* JADSTART==0 (no conversion on going)                             */
02368           if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
02369           {
02370             /* Disable ADC end of sequence conversion interrupt  */
02371             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
02372
02373             /* Set ADC state */
02374             CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
02375
02376             if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
02377             {
02378               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02379             }
02380           }
02381           else
02382           {
02383             /* Update ADC state machine to error */
02384             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02385
02386             /* Set ADC error code to ADC peripheral internal error */
02387             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02388           }
02389         }
02390       }
02391     }
02392
02393     /* Injected Conversion complete callback */
02394     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
02395               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
02396               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
02397               interruption has been triggered by end of conversion or end of
02398               sequence.    */
02399 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02400     hadc->InjectedConvCpltCallback(hadc);
02401 #else
02402     HAL_ADCEx_InjectedConvCpltCallback(hadc);
02403 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02404
02405     /* Clear injected group conversion flag */
02406     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
02407   }
02408
02409   /* ========== Check Analog watchdog 1 flag ========== */
02410   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
02411   {
02412     /* Set ADC state */
02413     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02414
02415     /* Level out of window 1 callback */
02416 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02417     hadc->LevelOutOfWindowCallback(hadc);
02418 #else
02419     HAL_ADC_LevelOutOfWindowCallback(hadc);
02420 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02421
02422     /* Clear ADC analog watchdog flag */
02423     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
02424   }
02425
02426   /* ========== Check analog watchdog 2 flag ========== */
02427   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
02428   {
02429     /* Set ADC state */
02430     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02431
02432     /* Level out of window 2 callback */
02433 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02434     hadc->LevelOutOfWindow2Callback(hadc);
02435 #else
02436     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
02437 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02438
02439     /* Clear ADC analog watchdog flag */
02440     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
02441   }
02442
02443   /* ========== Check analog watchdog 3 flag ========== */
02444   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
02445   {
02446     /* Set ADC state */
02447     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02448
02449     /* Level out of window 3 callback */
02450 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02451     hadc->LevelOutOfWindow3Callback(hadc);
02452 #else
02453     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
02454 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02455
02456     /* Clear ADC analog watchdog flag */
02457     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
02458   }
02459
02460   /* ========== Check Overrun flag ========== */
02461   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
02462   {
02463     /* If overrun is set to overwrite previous data (default setting),        */
02464     /* overrun event is not considered as an error.                           */
02465     /* (cf ref manual "Managing conversions without using the DMA and without */
02466     /* overrun ")                                                             */
02467     /* Exception for usage with DMA overrun event always considered as an     */
02468     /* error.                                                                 */
02469     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02470     {
02471       overrun_error = 1UL;
02472     }
02473     else
02474     {
02475       /* Check DMA configuration */
02476       if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
02477       {
02478         /* Multimode (when feature is available) is enabled,
02479            Common Control Register MDMA bits must be checked. */
02480         if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
02481         {
02482           overrun_error = 1UL;
02483         }
02484       }
02485       else
02486       {
02487         /* Multimode not set or feature not available or ADC independent */
02488       if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
02489       {
02490         overrun_error = 1UL;
02491       }
02492       }
02493     }
02494
02495     if (overrun_error == 1UL)
02496     {
02497       /* Change ADC state to error state */
02498       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
02499
02500       /* Set ADC error code to overrun */
02501       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
02502
02503       /* Error callback */
02504       /* Note: In case of overrun, ADC conversion data is preserved until     */
02505       /*       flag OVR is reset.                                             */
02506       /*       Therefore, old ADC conversion data can be retrieved in         */
02507       /*       function "HAL_ADC_ErrorCallback()".                            */
02508 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02509       hadc->ErrorCallback(hadc);
02510 #else
02511       HAL_ADC_ErrorCallback(hadc);
02512 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02513     }
02514
02515     /* Clear ADC overrun flag */
02516     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
02517   }
02518
02519   /* ========== Check Injected context queue overflow flag ========== */
02520   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
02521   {
02522     /* Change ADC state to overrun state */
02523     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02524
02525     /* Set ADC error code to Injected context queue overflow */
02526     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
02527
02528     /* Clear the Injected context queue overflow flag */
02529     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
02530
02531     /* Injected context queue overflow callback */
02532 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02533     hadc->InjectedQueueOverflowCallback(hadc);
02534 #else
02535     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
02536 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02537   }
02538
02539 }
02540
02541 /**
02542   * @brief  Conversion complete callback in non-blocking mode.
02543   * @param hadc ADC handle
02544   * @retval None
02545   */
02546 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
02547 {
02548   /* Prevent unused argument(s) compilation warning */
02549   UNUSED(hadc);
02550
02551   /* NOTE : This function should not be modified. When the callback is needed,
02552             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02553    */
02554 }
02555
02556 /**
02557   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02558   * @param hadc ADC handle
02559   * @retval None
02560   */
02561 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
02562 {
02563   /* Prevent unused argument(s) compilation warning */
02564   UNUSED(hadc);
02565
02566   /* NOTE : This function should not be modified. When the callback is needed,
02567             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02568   */
02569 }
02570
02571 /**
02572   * @brief  Analog watchdog 1 callback in non-blocking mode.
02573   * @param hadc ADC handle
02574   * @retval None
02575   */
02576 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
02577 {
02578   /* Prevent unused argument(s) compilation warning */
02579   UNUSED(hadc);
02580
02581   /* NOTE : This function should not be modified. When the callback is needed,
02582             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02583   */
02584 }
02585
02586 /**
02587   * @brief  ADC error callback in non-blocking mode
02588   *         (ADC conversion with interruption or transfer by DMA).
02589   * @note   In case of error due to overrun when using ADC with DMA transfer
02590   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
02591   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
02592   *         - If needed, restart a new ADC conversion using function
02593   *           "HAL_ADC_Start_DMA()"
02594   *           (this function is also clearing overrun flag)
02595   * @param hadc ADC handle
02596   * @retval None
02597   */
02598 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02599 {
02600   /* Prevent unused argument(s) compilation warning */
02601   UNUSED(hadc);
02602
02603   /* NOTE : This function should not be modified. When the callback is needed,
02604             function HAL_ADC_ErrorCallback must be implemented in the user file.
02605   */
02606 }
02607
02608 /**
02609   * @}
02610   */
02611
02612 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02613   * @brief    Peripheral Control functions
02614   *
02615 @verbatim
02616  ===============================================================================
02617              ##### Peripheral Control functions #####
02618  ===============================================================================
02619     [..]  This section provides functions allowing to:
02620       (+) Configure channels on regular group
02621       (+) Configure the analog watchdog
02622
02623 @endverbatim
02624   * @{
02625   */
02626
02627 /**
02628   * @brief  Configure a channel to be assigned to ADC group regular.
02629   * @note   In case of usage of internal measurement channels:
02630   *         Vbat/VrefInt/TempSensor.
02631   *         These internal paths can be disabled using function
02632   *         HAL_ADC_DeInit().
02633   * @note   Possibility to update parameters on the fly:
02634   *         This function initializes channel into ADC group regular,
02635   *         following calls to this function can be used to reconfigure
02636   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
02637   *         without resetting the ADC.
02638   *         The setting of these parameters is conditioned to ADC state:
02639   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
02640   * @param hadc ADC handle
02641   * @param sConfig Structure of ADC channel assigned to ADC group regular.
02642   * @retval HAL status
02643   */
02644 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
02645 {
02646   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02647   uint32_t tmpOffsetShifted;
02648   uint32_t tmp_config_internal_channel;
02649   __IO uint32_t wait_loop_index = 0;
02650   uint32_t tmp_adc_is_conversion_on_going_regular;
02651   uint32_t tmp_adc_is_conversion_on_going_injected;
02652
02653   /* Check the parameters */
02654   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02655   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
02656   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
02657   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
02658   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
02659   /* Check offset range according to oversampling setting */
02660   if (hadc->Init.OversamplingMode == ENABLE)
02661   {
02662     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
02663   }
02664   else
02665   {
02666     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
02667   }
02668
02669   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
02670      ignored (considered as reset) */
02671   assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
02672
02673   /* Verification of channel number */
02674   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02675   {
02676     assert_param(IS_ADC_CHANNEL(sConfig->Channel));
02677   }
02678   else
02679   {
02680     if (hadc->Instance == ADC1)
02681     {
02682       assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
02683     }
02684     if (hadc->Instance == ADC2)
02685     {
02686       assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
02687     }
02688 #if defined(ADC3)
02689     /* ADC3 is not available on some STM32H7 products */
02690     if (hadc->Instance == ADC3)
02691     {
02692       assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
02693     }
02694 #endif
02695   }
02696
02697   /* Process locked */
02698   __HAL_LOCK(hadc);
02699
02700   /* Parameters update conditioned to ADC state:                              */
02701   /* Parameters that can be updated when ADC is disabled or enabled without   */
02702   /* conversion on going on regular group:                                    */
02703   /*  - Channel number                                                        */
02704   /*  - Channel rank                                                          */
02705   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02706   {
02707     /* ADC channels preselection */
02708     hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
02709
02710     /* Set ADC group regular sequence: channel on the selected scan sequence rank */
02711     LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
02712
02713     /* Parameters update conditioned to ADC state:                              */
02714     /* Parameters that can be updated when ADC is disabled or enabled without   */
02715     /* conversion on going on regular group:                                    */
02716     /*  - Channel sampling time                                                 */
02717     /*  - Channel offset                                                        */
02718     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02719     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02720     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02721         && (tmp_adc_is_conversion_on_going_injected == 0UL)
02722        )
02723     {
02724       /* Set sampling time of the selected ADC channel */
02725       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
02726
02727       /* Configure the offset: offset enable/disable, channel, offset value */
02728
02729       /* Shift the offset with respect to the selected ADC resolution. */
02730       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02731       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
02732
02733       if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
02734       {
02735         /* Set ADC selected offset number */
02736         LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
02737
02738         assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
02739         /* Set ADC selected offset signed saturation */
02740         LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02741
02742         assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
02743         /* Set ADC selected offset right shift */
02744         LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
02745
02746       }
02747       else
02748       {
02749          /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
02750            If this is the case, offset OFRx is disabled since
02751            sConfig->OffsetNumber = ADC_OFFSET_NONE. */
02752           if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02753           {
02754             CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02755           }
02756           if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02757           {
02758             CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02759           }
02760           if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02761           {
02762             CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02763           }
02764           if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02765           {
02766             CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02767           }
02768       }
02769     }
02770
02771     /* Parameters update conditioned to ADC state:                              */
02772     /* Parameters that can be updated only when ADC is disabled:                */
02773     /*  - Single or differential mode                                           */
02774     /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02775     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02776     {
02777       /* Set mode single-ended or differential input of the selected ADC channel */
02778       LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
02779
02780       /* Configuration of differential mode */
02781       if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
02782       {
02783         /* Set sampling time of the selected ADC channel */
02784         /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
02785         LL_ADC_SetChannelSamplingTime(hadc->Instance,
02786                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
02787                                       sConfig->SamplingTime);
02788       }
02789
02790       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02791       /* If internal channel selected, enable dedicated internal buffers and    */
02792       /* paths.                                                                 */
02793       /* Note: these internal measurement paths can be disabled using           */
02794       /* HAL_ADC_DeInit().                                                      */
02795
02796       if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
02797       {
02798         /* Configuration of common ADC parameters                                 */
02799
02800         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02801
02802         /* Software is allowed to change common parameters only when all ADCs   */
02803         /* of the common group are disabled.                                    */
02804         if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02805         {
02806           /* If the requested internal measurement path has already been enabled, */
02807           /* bypass the configuration processing.                                 */
02808           if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02809           {
02810             if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02811             {
02812               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02813
02814               /* Delay for temperature sensor stabilization time */
02815               /* Wait loop initialization and execution */
02816               /* Note: Variable divided by 2 to compensate partially              */
02817               /*       CPU processing cycles, scaling in us split to not          */
02818               /*       exceed 32 bits register capacity and handle low frequency. */
02819               wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
02820               while(wait_loop_index != 0UL)
02821               {
02822                 wait_loop_index--;
02823               }
02824             }
02825           }
02826           else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02827           {
02828             if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02829             {
02830               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02831             }
02832           }
02833           else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02834           {
02835             if (ADC_VREFINT_INSTANCE(hadc))
02836             {
02837               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02838             }
02839           }
02840           else
02841           {
02842             /* nothing to do */
02843           }
02844         }
02845         /* If the requested internal measurement path has already been          */
02846         /* enabled and other ADC of the common group are enabled, internal      */
02847         /* measurement paths cannot be enabled.                                 */
02848         else
02849         {
02850           /* Update ADC state machine to error */
02851           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02852
02853           tmp_hal_status = HAL_ERROR;
02854         }
02855       }
02856     }
02857   }
02858
02859   /* If a conversion is on going on regular group, no update on regular       */
02860   /* channel could be done on neither of the channel configuration structure  */
02861   /* parameters.                                                              */
02862   else
02863   {
02864     /* Update ADC state machine to error */
02865     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02866
02867     tmp_hal_status = HAL_ERROR;
02868   }
02869
02870   /* Process unlocked */
02871   __HAL_UNLOCK(hadc);
02872
02873   /* Return function status */
02874   return tmp_hal_status;
02875 }
02876
02877 /**
02878   * @brief  Configure the analog watchdog.
02879   * @note   Possibility to update parameters on the fly:
02880   *         This function initializes the selected analog watchdog, successive
02881   *         calls to this function can be used to reconfigure some parameters
02882   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02883   *         the ADC.
02884   *         The setting of these parameters is conditioned to ADC state.
02885   *         For parameters constraints, see comments of structure
02886   *         "ADC_AnalogWDGConfTypeDef".
02887   * @note   On this STM32 serie, analog watchdog thresholds cannot be modified
02888   *         while ADC conversion is on going.
02889   * @param hadc ADC handle
02890   * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
02891   * @retval HAL status
02892   */
02893 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
02894 {
02895   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02896   uint32_t tmpAWDHighThresholdShifted;
02897   uint32_t tmpAWDLowThresholdShifted;
02898   uint32_t tmp_adc_is_conversion_on_going_regular;
02899   uint32_t tmp_adc_is_conversion_on_going_injected;
02900
02901   /* Check the parameters */
02902   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02903   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
02904   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
02905   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
02906
02907   if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
02908       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
02909       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
02910   {
02911     assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
02912   }
02913
02914   /* Verify thresholds range */
02915   if (hadc->Init.OversamplingMode == ENABLE)
02916   {
02917     /* Case of oversampling enabled: thresholds are compared to oversampling
02918        intermediate computation (after ratio, before shift application) */
02919     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
02920     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
02921   }
02922   else
02923   {
02924     /* Verify if thresholds are within the selected ADC resolution */
02925     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
02926     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
02927   }
02928
02929   /* Process locked */
02930   __HAL_LOCK(hadc);
02931
02932   /* Parameters update conditioned to ADC state:                              */
02933   /* Parameters that can be updated when ADC is disabled or enabled without   */
02934   /* conversion on going on ADC groups regular and injected:                  */
02935   /*  - Analog watchdog channels                                              */
02936   /*  - Analog watchdog thresholds                                            */
02937   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02938   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02939   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02940       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02941      )
02942   {
02943     /* Analog watchdog configuration */
02944     if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02945     {
02946       /* Configuration of analog watchdog:                                    */
02947       /*  - Set the analog watchdog enable mode: one or overall group of      */
02948       /*    channels, on groups regular and-or injected.                      */
02949       switch (AnalogWDGConfig->WatchdogMode)
02950       {
02951         case ADC_ANALOGWATCHDOG_SINGLE_REG:
02952           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02953                                           LL_ADC_GROUP_REGULAR));
02954           break;
02955
02956         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
02957           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02958                                           LL_ADC_GROUP_INJECTED));
02959           break;
02960
02961         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
02962           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02963                                           LL_ADC_GROUP_REGULAR_INJECTED));
02964           break;
02965
02966         case ADC_ANALOGWATCHDOG_ALL_REG:
02967           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
02968           break;
02969
02970         case ADC_ANALOGWATCHDOG_ALL_INJEC:
02971           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
02972           break;
02973
02974         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
02975           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
02976           break;
02977
02978         default: /* ADC_ANALOGWATCHDOG_NONE */
02979           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
02980           break;
02981       }
02982
02983       /* Shift the offset in function of the selected ADC resolution:         */
02984       /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02985       /* are set to 0                                                         */
02986       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02987       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02988
02989       /* Set the high and low thresholds */
02990       MODIFY_REG(hadc->Instance->LTR1,  ADC_LTR_LT , tmpAWDLowThresholdShifted);
02991       MODIFY_REG(hadc->Instance->HTR1,  ADC_HTR_HT , tmpAWDHighThresholdShifted);
02992
02993       /* Update state, clear previous result related to AWD1 */
02994       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02995
02996       /* Clear flag ADC analog watchdog */
02997       /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02998       /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02999       /* (in case left enabled by previous ADC operations).                 */
03000       LL_ADC_ClearFlag_AWD1(hadc->Instance);
03001
03002       /* Configure ADC analog watchdog interrupt */
03003       if (AnalogWDGConfig->ITMode == ENABLE)
03004       {
03005         LL_ADC_EnableIT_AWD1(hadc->Instance);
03006       }
03007       else
03008       {
03009         LL_ADC_DisableIT_AWD1(hadc->Instance);
03010       }
03011     }
03012     /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
03013     else
03014     {
03015       switch (AnalogWDGConfig->WatchdogMode)
03016       {
03017         case ADC_ANALOGWATCHDOG_SINGLE_REG:
03018         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
03019         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
03020           /* Update AWD by bitfield to keep the possibility to monitor        */
03021           /* several channels by successive calls of this function.           */
03022           if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03023           {
03024             SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
03025           }
03026           else
03027           {
03028             SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
03029           }
03030           break;
03031
03032         case ADC_ANALOGWATCHDOG_ALL_REG:
03033         case ADC_ANALOGWATCHDOG_ALL_INJEC:
03034         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
03035           /* Update AWD by bitfield to keep the possibility to monitor        */
03036           /* several channels by successive calls of this function.           */
03037           if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03038           {
03039             SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
03040           }
03041           else
03042           {
03043             SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
03044           }
03045           break;
03046
03047         default: /* ADC_ANALOGWATCHDOG_NONE */
03048           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
03049           break;
03050       }
03051
03052       /* Shift the thresholds in function of the selected ADC resolution      */
03053       /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
03054       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
03055       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
03056
03057      if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03058       {
03059        /* Set ADC analog watchdog thresholds value of both thresholds high and low */
03060         MODIFY_REG(hadc->Instance->LTR2,  ADC_LTR_LT , tmpAWDLowThresholdShifted);
03061         MODIFY_REG(hadc->Instance->HTR2,  ADC_HTR_HT , tmpAWDHighThresholdShifted);
03062       }
03063       else
03064       {
03065         /* Set ADC analog watchdog thresholds value of both thresholds high and low */
03066         MODIFY_REG(hadc->Instance->LTR3,  ADC_LTR_LT , tmpAWDLowThresholdShifted);
03067         MODIFY_REG(hadc->Instance->HTR3,  ADC_HTR_HT , tmpAWDHighThresholdShifted);
03068       }
03069
03070       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03071       {
03072         /* Update state, clear previous result related to AWD2 */
03073         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
03074
03075         /* Clear flag ADC analog watchdog */
03076         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
03077         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
03078         /* (in case left enabled by previous ADC operations).                 */
03079         LL_ADC_ClearFlag_AWD2(hadc->Instance);
03080
03081         /* Configure ADC analog watchdog interrupt */
03082         if (AnalogWDGConfig->ITMode == ENABLE)
03083         {
03084           LL_ADC_EnableIT_AWD2(hadc->Instance);
03085         }
03086         else
03087         {
03088           LL_ADC_DisableIT_AWD2(hadc->Instance);
03089         }
03090       }
03091       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
03092       else
03093       {
03094         /* Update state, clear previous result related to AWD3 */
03095         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
03096
03097         /* Clear flag ADC analog watchdog */
03098         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
03099         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
03100         /* (in case left enabled by previous ADC operations).                 */
03101         LL_ADC_ClearFlag_AWD3(hadc->Instance);
03102
03103         /* Configure ADC analog watchdog interrupt */
03104         if (AnalogWDGConfig->ITMode == ENABLE)
03105         {
03106           LL_ADC_EnableIT_AWD3(hadc->Instance);
03107         }
03108         else
03109         {
03110           LL_ADC_DisableIT_AWD3(hadc->Instance);
03111         }
03112       }
03113     }
03114
03115   }
03116   /* If a conversion is on going on ADC group regular or injected, no update  */
03117   /* could be done on neither of the AWD configuration structure parameters.  */
03118   else
03119   {
03120     /* Update ADC state machine to error */
03121     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
03122
03123     tmp_hal_status = HAL_ERROR;
03124   }
03125   /* Process unlocked */
03126   __HAL_UNLOCK(hadc);
03127
03128   /* Return function status */
03129   return tmp_hal_status;
03130 }
03131
03132
03133 /**
03134   * @}
03135   */
03136
03137 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
03138   *  @brief    ADC Peripheral State functions
03139   *
03140 @verbatim
03141  ===============================================================================
03142             ##### Peripheral state and errors functions #####
03143  ===============================================================================
03144     [..]
03145     This subsection provides functions to get in run-time the status of the
03146     peripheral.
03147       (+) Check the ADC state
03148       (+) Check the ADC error code
03149
03150 @endverbatim
03151   * @{
03152   */
03153
03154 /**
03155   * @brief  Return the ADC handle state.
03156   * @note   ADC state machine is managed by bitfields, ADC status must be
03157   *         compared with states bits.
03158   *         For example:
03159   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
03160   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
03161   * @param hadc ADC handle
03162   * @retval ADC handle state (bitfield on 32 bits)
03163   */
03164 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
03165 {
03166   /* Check the parameters */
03167   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03168
03169   /* Return ADC handle state */
03170   return hadc->State;
03171 }
03172
03173 /**
03174   * @brief  Return the ADC error code.
03175   * @param hadc ADC handle
03176   * @retval ADC error code (bitfield on 32 bits)
03177   */
03178 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
03179 {
03180   /* Check the parameters */
03181   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03182
03183   return hadc->ErrorCode;
03184 }
03185
03186 /**
03187   * @}
03188   */
03189
03190 /**
03191   * @}
03192   */
03193
03194 /** @defgroup ADC_Private_Functions ADC Private Functions
03195   * @{
03196   */
03197
03198 /**
03199   * @brief  Stop ADC conversion.
03200   * @param hadc ADC handle
03201   * @param ConversionGroup ADC group regular and/or injected.
03202   *          This parameter can be one of the following values:
03203   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
03204   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
03205   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
03206   * @retval HAL status.
03207   */
03208 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
03209 {
03210   uint32_t tickstart;
03211   uint32_t Conversion_Timeout_CPU_cycles = 0UL;
03212   uint32_t conversion_group_reassigned = ConversionGroup;
03213   uint32_t tmp_ADC_CR_ADSTART_JADSTART;
03214   uint32_t tmp_adc_is_conversion_on_going_regular;
03215   uint32_t tmp_adc_is_conversion_on_going_injected;
03216
03217   /* Check the parameters */
03218   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03219   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
03220
03221   /* Verification if ADC is not already stopped (on regular and injected      */
03222   /* groups) to bypass this function if not needed.                           */
03223   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
03224   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
03225   if ((tmp_adc_is_conversion_on_going_regular != 0UL)
03226       || (tmp_adc_is_conversion_on_going_injected != 0UL)
03227      )
03228   {
03229     /* Particular case of continuous auto-injection mode combined with        */
03230     /* auto-delay mode.                                                       */
03231     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
03232     /* injected group stop ADC_CR_JADSTP).                                    */
03233     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
03234     /* (see reference manual).                                                */
03235     if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
03236         && (hadc->Init.ContinuousConvMode == ENABLE)
03237         && (hadc->Init.LowPowerAutoWait == ENABLE)
03238        )
03239     {
03240       /* Use stop of regular group */
03241       conversion_group_reassigned = ADC_REGULAR_GROUP;
03242
03243       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
03244       while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
03245       {
03246         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
03247         {
03248           /* Update ADC state machine to error */
03249           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03250
03251           /* Set ADC error code to ADC peripheral internal error */
03252           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03253
03254           return HAL_ERROR;
03255         }
03256         Conversion_Timeout_CPU_cycles ++;
03257       }
03258
03259       /* Clear JEOS */
03260       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
03261     }
03262
03263     /* Stop potential conversion on going on ADC group regular */
03264     if (conversion_group_reassigned != ADC_INJECTED_GROUP)
03265     {
03266       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
03267       if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
03268       {
03269         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
03270         {
03271           /* Stop ADC group regular conversion */
03272           LL_ADC_REG_StopConversion(hadc->Instance);
03273         }
03274       }
03275     }
03276
03277     /* Stop potential conversion on going on ADC group injected */
03278     if (conversion_group_reassigned != ADC_REGULAR_GROUP)
03279     {
03280       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
03281       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
03282       {
03283         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
03284         {
03285           /* Stop ADC group injected conversion */
03286           LL_ADC_INJ_StopConversion(hadc->Instance);
03287         }
03288       }
03289     }
03290
03291     /* Selection of start and stop bits with respect to the regular or injected group */
03292     switch (conversion_group_reassigned)
03293     {
03294       case ADC_REGULAR_INJECTED_GROUP:
03295         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
03296         break;
03297       case ADC_INJECTED_GROUP:
03298         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
03299         break;
03300       /* Case ADC_REGULAR_GROUP only*/
03301       default:
03302         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
03303         break;
03304     }
03305
03306     /* Wait for conversion effectively stopped */
03307     tickstart = HAL_GetTick();
03308
03309     while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
03310     {
03311       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
03312       {
03313         /* Update ADC state machine to error */
03314         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03315
03316         /* Set ADC error code to ADC peripheral internal error */
03317         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03318
03319         return HAL_ERROR;
03320       }
03321     }
03322
03323   }
03324
03325   /* Return HAL status */
03326   return HAL_OK;
03327 }
03328
03329
03330
03331 /**
03332   * @brief  Enable the selected ADC.
03333   * @note   Prerequisite condition to use this function: ADC must be disabled
03334   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
03335   * @param hadc ADC handle
03336   * @retval HAL status.
03337   */
03338 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
03339 {
03340   uint32_t tickstart;
03341
03342   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
03343   /* enabling phase not yet completed: flag ADC ready not yet set).           */
03344   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
03345   /* causes: ADC clock not running, ...).                                     */
03346   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03347   {
03348     /* Check if conditions to enable the ADC are fulfilled */
03349     if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
03350     {
03351       /* Update ADC state machine to error */
03352       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03353
03354       /* Set ADC error code to ADC peripheral internal error */
03355       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03356
03357       return HAL_ERROR;
03358     }
03359
03360     /* Enable the ADC peripheral */
03361     LL_ADC_Enable(hadc->Instance);
03362
03363     /* Wait for ADC effectively enabled */
03364     tickstart = HAL_GetTick();
03365
03366     /* Poll for ADC ready flag raised except case of multimode enabled
03367        and ADC slave selected. */
03368     uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
03369     if (    (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
03370          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
03371        )
03372     {
03373       while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
03374       {
03375         /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
03376             has been cleared (after a calibration), ADEN bit is reset by the
03377             calibration logic.
03378             The workaround is to continue setting ADEN until ADRDY is becomes 1.
03379             Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
03380             4 ADC clock cycle duration */
03381         /* Note: Test of ADC enabled required due to hardware constraint to     */
03382         /*       not enable ADC if already enabled.                             */
03383         if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03384         {
03385           LL_ADC_Enable(hadc->Instance);
03386         }
03387
03388         if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
03389         {
03390           /* Update ADC state machine to error */
03391           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03392
03393           /* Set ADC error code to ADC peripheral internal error */
03394           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03395
03396           return HAL_ERROR;
03397         }
03398       }
03399     }
03400   }
03401
03402   /* Return HAL status */
03403   return HAL_OK;
03404 }
03405
03406 /**
03407   * @brief  Disable the selected ADC.
03408   * @note   Prerequisite condition to use this function: ADC conversions must be
03409   *         stopped.
03410   * @param hadc ADC handle
03411   * @retval HAL status.
03412   */
03413 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
03414 {
03415   uint32_t tickstart;
03416   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
03417
03418   /* Verification if ADC is not already disabled:                             */
03419   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
03420   /*       disabled.                                                          */
03421   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
03422       && (tmp_adc_is_disable_on_going == 0UL)
03423      )
03424   {
03425     /* Check if conditions to disable the ADC are fulfilled */
03426     if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
03427     {
03428       /* Disable the ADC peripheral */
03429       LL_ADC_Disable(hadc->Instance);
03430       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
03431     }
03432     else
03433     {
03434       /* Update ADC state machine to error */
03435       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03436
03437       /* Set ADC error code to ADC peripheral internal error */
03438       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03439
03440       return HAL_ERROR;
03441     }
03442
03443     /* Wait for ADC effectively disabled */
03444     /* Get tick count */
03445     tickstart = HAL_GetTick();
03446
03447     while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
03448     {
03449       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
03450       {
03451         /* Update ADC state machine to error */
03452         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03453
03454         /* Set ADC error code to ADC peripheral internal error */
03455         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03456
03457         return HAL_ERROR;
03458       }
03459     }
03460   }
03461
03462   /* Return HAL status */
03463   return HAL_OK;
03464 }
03465
03466 /**
03467   * @brief  DMA transfer complete callback.
03468   * @param hdma pointer to DMA handle.
03469   * @retval None
03470   */
03471 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
03472 {
03473   /* Retrieve ADC handle corresponding to current DMA handle */
03474   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03475
03476   /* Update state machine on conversion status if not in error state */
03477   if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
03478   {
03479     /* Set ADC state */
03480     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
03481
03482     /* Determine whether any further conversion upcoming on group regular     */
03483     /* by external trigger, continuous mode or scan sequence on going         */
03484     /* to disable interruption.                                               */
03485     /* Is it the end of the regular sequence ? */
03486     if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
03487     {
03488       /* Are conversions software-triggered ? */
03489       if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
03490       {
03491         /* Is CONT bit set ? */
03492         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
03493         {
03494           /* CONT bit is not set, no more conversions expected */
03495           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03496           if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03497           {
03498             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03499           }
03500         }
03501       }
03502     }
03503     else
03504     {
03505       /* DMA End of Transfer interrupt was triggered but conversions sequence
03506          is not over. If DMACFG is set to 0, conversions are stopped. */
03507       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
03508       {
03509         /* DMACFG bit is not set, conversions are stopped. */
03510         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03511         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03512         {
03513           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03514         }
03515       }
03516     }
03517
03518     /* Conversion complete callback */
03519 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03520     hadc->ConvCpltCallback(hadc);
03521 #else
03522     HAL_ADC_ConvCpltCallback(hadc);
03523 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03524   }
03525   else /* DMA and-or internal error occurred */
03526   {
03527     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
03528     {
03529       /* Call HAL ADC Error Callback function */
03530 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03531       hadc->ErrorCallback(hadc);
03532 #else
03533       HAL_ADC_ErrorCallback(hadc);
03534 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03535     }
03536     else
03537     {
03538       /* Call ADC DMA error callback */
03539       hadc->DMA_Handle->XferErrorCallback(hdma);
03540     }
03541   }
03542 }
03543
03544 /**
03545   * @brief  DMA half transfer complete callback.
03546   * @param hdma pointer to DMA handle.
03547   * @retval None
03548   */
03549 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
03550 {
03551   /* Retrieve ADC handle corresponding to current DMA handle */
03552   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03553
03554   /* Half conversion callback */
03555 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03556   hadc->ConvHalfCpltCallback(hadc);
03557 #else
03558   HAL_ADC_ConvHalfCpltCallback(hadc);
03559 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03560 }
03561
03562 /**
03563   * @brief  DMA error callback.
03564   * @param hdma pointer to DMA handle.
03565   * @retval None
03566   */
03567 void ADC_DMAError(DMA_HandleTypeDef *hdma)
03568 {
03569   /* Retrieve ADC handle corresponding to current DMA handle */
03570   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03571
03572   /* Set ADC state */
03573   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
03574
03575   /* Set ADC error code to DMA error */
03576   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
03577
03578   /* Error callback */
03579 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03580   hadc->ErrorCallback(hadc);
03581 #else
03582   HAL_ADC_ErrorCallback(hadc);
03583 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03584 }
03585
03586 /**
03587   * @brief  Configure boost mode of selected ADC.
03588   * @note   Prerequisite condition to use this function: ADC conversions must be
03589   *         stopped.
03590   * @param  hadc ADC handle
03591   * @retval None.
03592   */
03593 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
03594 {
03595   uint32_t freq;
03596   if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
03597   {
03598     freq = HAL_RCC_GetHCLKFreq();
03599     switch(hadc->Init.ClockPrescaler)
03600     {
03601       case ADC_CLOCK_SYNC_PCLK_DIV1:
03602       case ADC_CLOCK_SYNC_PCLK_DIV2:
03603         freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
03604         break;
03605       case ADC_CLOCK_SYNC_PCLK_DIV4:
03606         freq /= 4UL;
03607         break;
03608       default:
03609         break;
03610     }
03611   }
03612   else
03613   {
03614     freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
03615     switch(hadc->Init.ClockPrescaler)
03616     {
03617       case ADC_CLOCK_ASYNC_DIV2:
03618       case ADC_CLOCK_ASYNC_DIV4:
03619       case ADC_CLOCK_ASYNC_DIV6:
03620       case ADC_CLOCK_ASYNC_DIV8:
03621       case ADC_CLOCK_ASYNC_DIV10:
03622       case ADC_CLOCK_ASYNC_DIV12:
03623         freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
03624         break;
03625       case ADC_CLOCK_ASYNC_DIV16:
03626         freq /= 16UL;
03627       break;
03628         case ADC_CLOCK_ASYNC_DIV32:
03629         freq /= 32UL;
03630         break;
03631       case ADC_CLOCK_ASYNC_DIV64:
03632         freq /= 64UL;
03633         break;
03634       case ADC_CLOCK_ASYNC_DIV128:
03635         freq /= 128UL;
03636         break;
03637       case ADC_CLOCK_ASYNC_DIV256:
03638         freq /= 256UL;
03639         break;
03640       default:
03641         break;
03642     }
03643   }
03644
03645 #if defined(ADC_VER_V5_3)
03646   if (freq <= 6250000UL)
03647   {
03648     MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
03649   }
03650   else if((freq > 6250000UL) && (freq <= 12500000UL))
03651   {
03652     MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
03653   }
03654   else if((freq > 12500000UL) && (freq <= 25000000UL))
03655   {
03656     MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
03657   }
03658   else /* if(freq > 25000000UL) */
03659   {
03660     MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
03661   }
03662 #else
03663   if(HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
03664   {
03665     if(freq > 20000000UL)
03666     {
03667       SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
03668     }
03669     else
03670     {
03671       CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
03672     }
03673   }
03674   else /* STM32H7 silicon Rev.V */
03675   {
03676     freq /= 2U; /* divider by 2 for Rev.V */
03677
03678     if (freq <= 6250000UL)
03679     {
03680       MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
03681     }
03682     else if((freq > 6250000UL) && (freq <= 12500000UL))
03683     {
03684       MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
03685     }
03686     else if((freq > 12500000UL) && (freq <= 25000000UL))
03687     {
03688       MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
03689     }
03690     else /* if(freq > 25000000UL) */
03691     {
03692       MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
03693     }
03694   }
03695 #endif /* ADC_VER_V5_3 */
03696 }
03697
03698 /**
03699   * @}
03700   */
03701
03702 #endif /* HAL_ADC_MODULE_ENABLED */
03703 /**
03704   * @}
03705   */
03706
03707 /**
03708   * @}
03709   */
03710
03711 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:56 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc.h Source File

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stm32h7xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_ADC_H
00022 #define STM32H7xx_HAL_ADC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /* Include low level driver */
00032 #include "stm32h7xx_ll_adc.h"
00033
00034 /** @addtogroup STM32H7xx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup ADC
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup ADC_Exported_Types ADC Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  ADC group regular oversampling structure definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00053                                                This parameter can be a value between 1 and 1024 */
00054
00055   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00056                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00057
00058   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00059                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
00060
00061   uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
00062                                                The oversampling is either temporary stopped or reset upon an injected
00063                                                sequence interruption.
00064                                                If oversampling is enabled on both regular and injected groups, this parameter
00065                                                is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
00066                                                (the oversampling buffer is zeroed during injection sequence).
00067                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
00068
00069 } ADC_OversamplingTypeDef;
00070
00071 /**
00072   * @brief  Structure definition of ADC instance and ADC group regular.
00073   * @note   Parameters of this structure are shared within 2 scopes:
00074   *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
00075   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00076   *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
00077   *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
00078   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
00079   *         ADC state can be either:
00080   *          - For all parameters: ADC disabled
00081   *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
00082   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
00083   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00084   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
00085   *         (which fulfills the ADC state condition) on the fly).
00086   */
00087 typedef struct
00088 {
00089   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
00090                                        This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
00091                                        Note: The ADC clock configuration is common to all ADC instances.
00092                                        Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
00093                                              AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
00094                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
00095                                              if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
00096                                              must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
00097                                        Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
00098                                        Note: This parameter can be modified only if all ADC instances are disabled. */
00099
00100   uint32_t Resolution;            /*!< Configure the ADC resolution.
00101                                        This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
00102
00103   uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
00104                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00105                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00106                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00107                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
00108                                                     Scan direction is upward: from rank 1 to rank 'n'.
00109                                        This parameter can be a value of @ref ADC_Scan_mode */
00110
00111   uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
00112                                        This parameter can be a value of @ref ADC_EOCSelection. */
00113
00114   FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
00115                                        conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
00116                                        using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
00117                                        This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
00118                                        for low frequency applications.
00119                                        This parameter can be set to ENABLE or DISABLE.
00120                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
00121                                              to free the IRQ vector sequencer.
00122                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
00123                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
00124                                              (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
00125
00126   FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
00127                                        after the first ADC conversion start trigger occurred (software start or external trigger).
00128                                        This parameter can be set to ENABLE or DISABLE. */
00129
00130   uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
00131                                        To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00132                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16.
00133                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
00134                                        continuous mode or external trigger that could launch a conversion). */
00135
00136   FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
00137                                        (main sequence subdivided in successive parts).
00138                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00139                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00140                                        This parameter can be set to ENABLE or DISABLE. */
00141
00142   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
00143                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00144                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00145
00146   uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
00147                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00148                                        This parameter can be a value of @ref ADC_regular_external_trigger_source.
00149                                        Caution: external trigger source is common to all ADC instances. */
00150
00151   uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
00152                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
00153                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
00154
00155   uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
00156                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00157                                        This parameter can be a value of @ref ADC_ConversionDataManagement.
00158                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups
00159                                        (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00160
00161   uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
00162                                        This parameter applies to ADC group regular only.
00163                                        This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
00164                                        Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
00165                                        end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
00166                                        HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
00167                                        Note: Error reporting with respect to the conversion mode:
00168                                              - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
00169                                                overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
00170                                              - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
00171
00172   uint32_t LeftBitShift;             /*!< Configures the left shifting applied to the final result with or without oversampling.
00173                                           This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
00174   FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
00175                                                This parameter can be set to ENABLE or DISABLE.
00176                                                Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
00177
00178   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
00179                                                Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
00180
00181 } ADC_InitTypeDef;
00182
00183 /**
00184   * @brief  Structure definition of ADC channel for regular group
00185   * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00186   *         ADC state can be either:
00187   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00188   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
00189   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
00190   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00191   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
00192   *         on the fly).
00193   */
00194 typedef struct
00195 {
00196   uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
00197                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00198                                         Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00199
00200   uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
00201                                         This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
00202                                         Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00203                                         the new channel setting (or parameter number of conversions adjusted) */
00204
00205   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00206                                         Unit: ADC clock cycles
00207                                         Conversion time is the addition of sampling time and processing time
00208                                         (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00209                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
00210                                         Caution: This parameter applies to a channel that can be used into regular and/or injected group.
00211                                                  It overwrites the last setting.
00212                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00213                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00214                                               Refer to device datasheet for timings values. */
00215
00216   uint32_t SingleDiff;             /*!< Select single-ended or differential input.
00217                                         In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00218                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00219                                         This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
00220                                         Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00221                                                  It overwrites the last setting.
00222                                         Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00223                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00224                                         Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00225                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00226                                         of another parameter update on the fly) */
00227
00228   uint32_t OffsetNumber;           /*!< Select the offset number
00229                                         This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
00230                                         Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00231
00232   uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
00233                                         Offset value must be a positive number.
00234                                         Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
00235                                         0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
00236                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00237                                               without continuous mode or external trigger that could launch a conversion). */
00238
00239   FunctionalState OffsetRightShift;   /*!< Define the Right-shift data after Offset correction.
00240                                         This parameter is applied only for 16-bit or 8-bit resolution.
00241                                         This parameter can be set to ENABLE or DISABLE.*/
00242
00243   FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
00244                                              This parameter is applied only for 16-bit or 8-bit resolution.
00245                                              This parameter can be set to ENABLE or DISABLE. */
00246
00247 } ADC_ChannelConfTypeDef;
00248
00249 /**
00250   * @brief  Structure definition of ADC analog watchdog
00251   * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00252   *         ADC state can be either:
00253   *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
00254   */
00255 typedef struct
00256 {
00257   uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
00258                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00259                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00260                                    This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
00261
00262   uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
00263                                    For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
00264                                    For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
00265                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
00266
00267   uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
00268                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
00269                                    For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
00270                                    This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
00271
00272   FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
00273                                    This parameter can be set to ENABLE or DISABLE */
00274
00275   uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
00276                                    Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
00277                                    between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
00278                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00279                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00280                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00281                                          impacted: the comparison of analog watchdog thresholds is done
00282                                          on oversampling intermediate computation (after ratio, before shift
00283                                          application): intermediate register bitfield [32:7] (26 most significant bits). */
00284
00285   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00286                                    Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
00287                                    between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
00288                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00289                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00290                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00291                                          impacted: the comparison of analog watchdog thresholds is done
00292                                          on oversampling intermediate computation (after ratio, before shift
00293                                          application): intermediate register bitfield [32:7] (26 most significant bits). */
00294 } ADC_AnalogWDGConfTypeDef;
00295
00296 /**
00297   * @brief  ADC group injected contexts queue configuration
00298   * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"
00299   */
00300 typedef struct
00301 {
00302   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00303                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00304                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00305
00306   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00307 } ADC_InjectionConfigTypeDef;
00308
00309 /** @defgroup ADC_States ADC States
00310   * @{
00311   */
00312
00313 /**
00314   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00315   * @note   ADC state machine is managed by bitfields, state must be compared
00316   *         with bit by bit.
00317   *         For example:
00318   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
00319   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
00320   */
00321 /* States of ADC global scope */
00322 #define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
00323 #define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
00324 #define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */
00325 #define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
00326
00327 /* States of ADC errors */
00328 #define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
00329 #define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
00330 #define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
00331
00332 /* States of ADC group regular */
00333 #define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
00334                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00335 #define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
00336 #define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
00337 #define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
00338
00339 /* States of ADC group injected */
00340 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
00341                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00342 #define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
00343 #define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */
00344
00345 /* States of ADC analog watchdogs */
00346 #define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
00347 #define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
00348 #define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
00349
00350 /* States of ADC multi-mode */
00351 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @brief  ADC handle Structure definition
00359   */
00360 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00361 typedef struct __ADC_HandleTypeDef
00362 #else
00363 typedef struct
00364 #endif
00365 {
00366   ADC_TypeDef                   *Instance;              /*!< Register base address */
00367   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
00368   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00369   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00370   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
00371   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00372   ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
00373 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00374   void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
00375   void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
00376   void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
00377   void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
00378   void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
00379   void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
00380   void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
00381   void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
00382   void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
00383   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
00384   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
00385 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00386 } ADC_HandleTypeDef;
00387
00388 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00389 /**
00390   * @brief  HAL ADC Callback ID enumeration definition
00391   */
00392 typedef enum
00393 {
00394   HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
00395   HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
00396   HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
00397   HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
00398   HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
00399   HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */
00400   HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
00401   HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
00402   HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
00403   HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
00404   HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
00405 } HAL_ADC_CallbackIDTypeDef;
00406
00407 /**
00408   * @brief  HAL ADC Callback pointer definition
00409   */
00410 typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
00411
00412 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00413
00414 /**
00415   * @}
00416   */
00417
00418
00419 /* Exported constants --------------------------------------------------------*/
00420
00421 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00422   * @{
00423   */
00424
00425 /** @defgroup ADC_Error_Code ADC Error Code
00426   * @{
00427   */
00428 #define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
00429 #define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
00430                                                        enable/disable, erroneous state, ...)       */
00431 #define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
00432 #define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
00433 #define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */
00434 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00435 #define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
00436 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00442   * @{
00443   */
00444 #define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler */
00445 #define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00446 #define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00447
00448 #define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */
00449 #define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */
00450 #define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */
00451 #define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */
00452 #define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */
00453 #define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */
00454 #define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */
00455 #define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */
00456 #define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */
00457 #define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */
00458 #define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */
00459 #define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
00465   * @{
00466   */
00467 #define ADC_RESOLUTION_16B                 (LL_ADC_RESOLUTION_16B)  /*!< ADC resolution 16 bits */
00468 #define ADC_RESOLUTION_14B                 (LL_ADC_RESOLUTION_14B)  /*!< ADC resolution 14 bits */
00469 #define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
00470 #define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
00471 #define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
00477   * @{
00478   */
00479 #define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
00480 #define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
00486   * @{
00487   */
00488 /* ADC group regular trigger sources for all ADC instances */
00489 #define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */
00490 #define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00491 #define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00492 #define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00493 #define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00494 #define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
00495 #define ADC_EXTERNALTRIG_T4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00496 #define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
00497 #define ADC_EXTERNALTRIG_T8_TRGO      (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
00498 #define ADC_EXTERNALTRIG_T8_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
00499 #define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
00500 #define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
00501 #define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
00502 #define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
00503 #define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
00504 #define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)           /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
00505 #define ADC_EXTERNALTRIG_T3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00506 #define ADC_EXTERNALTRIG_HR1_ADCTRG1  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
00507 #define ADC_EXTERNALTRIG_HR1_ADCTRG3  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */
00508 #define ADC_EXTERNALTRIG_LPTIM1_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
00509 #define ADC_EXTERNALTRIG_LPTIM2_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
00510 #define ADC_EXTERNALTRIG_LPTIM3_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
00511 /**
00512   * @}
00513   */
00514
00515 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
00516   * @{
00517   */
00518 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */
00519 #define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */
00520 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */
00521 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
00527   * @{
00528   */
00529 #define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
00530 #define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00536   * @{
00537   */
00538 #define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */
00539 #define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00545   * @{
00546   */
00547 #define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
00548 #define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
00549 #define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
00550 #define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
00551 #define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
00552 #define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
00553 #define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
00554 #define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
00555 #define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
00556 #define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
00557 #define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
00558 #define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
00559 #define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
00560 #define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
00561 #define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
00562 #define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00568   * @{
00569   */
00570 #define ADC_SAMPLETIME_1CYCLE_5          (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycles */
00571 #define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
00572 #define ADC_SAMPLETIME_8CYCLES_5         (LL_ADC_SAMPLINGTIME_8CYCLES_5)    /*!< Sampling time 8.5 ADC clock cycles */
00573 #define ADC_SAMPLETIME_16CYCLES_5        (LL_ADC_SAMPLINGTIME_16CYCLES_5)   /*!< Sampling time 16.5 ADC clock cycles */
00574 #define ADC_SAMPLETIME_32CYCLES_5        (LL_ADC_SAMPLINGTIME_32CYCLES_5)   /*!< Sampling time 32.5 ADC clock cycles */
00575 #define ADC_SAMPLETIME_64CYCLES_5        (LL_ADC_SAMPLINGTIME_64CYCLES_5)   /*!< Sampling time 64.5 ADC clock cycles */
00576 #define ADC_SAMPLETIME_387CYCLES_5       (LL_ADC_SAMPLINGTIME_387CYCLES_5)  /*!< Sampling time 387.5 ADC clock cycles */
00577 #define ADC_SAMPLETIME_810CYCLES_5       (LL_ADC_SAMPLINGTIME_810CYCLES_5)  /*!< Sampling time 810.5 ADC clock cycles */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADCEx_Calibration_Mode   ADC Extended Calibration mode offset mode or linear mode
00583   * @{
00584   */
00585 #define ADC_CALIB_OFFSET                   (LL_ADC_CALIB_OFFSET)
00586 #define ADC_CALIB_OFFSET_LINEARITY         (LL_ADC_CALIB_OFFSET_LINEARITY)
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
00592   * @{
00593   */
00594 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
00595 /*        all ADC instances (refer to Reference Manual).                      */
00596 #define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00597 #define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00598 #define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00599 #define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00600 #define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00601 #define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00602 #define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00603 #define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00604 #define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00605 #define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00606 #define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00607 #define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00608 #define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00609 #define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00610 #define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00611 #define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00612 #define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00613 #define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00614 #define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00615 #define ADC_CHANNEL_19                     (LL_ADC_CHANNEL_19)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
00616 #define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */
00617 #define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)      /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */
00618 #define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */
00619 #define ADC_CHANNEL_DAC1CH1_ADC2           (LL_ADC_CHANNEL_DAC1CH1_ADC2)    /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
00620 #define ADC_CHANNEL_DAC1CH2_ADC2           (LL_ADC_CHANNEL_DAC1CH2_ADC2)    /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
00621 #if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2)
00622 #define ADC_CHANNEL_DAC2CH1_ADC2           (LL_ADC_CHANNEL_DAC2CH1_ADC2)    /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
00623 #endif
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
00629   * @{
00630   */
00631 #define ADC_CONVERSIONDATA_DR                  (0x00000000UL)                          /*!< Regular Conversion data stored in DR register only  */
00632 #define ADC_CONVERSIONDATA_DFSDM               (ADC_CFGR_DMNGT_1)                      /*!< DFSDM mode selected */
00633 #define ADC_CONVERSIONDATA_DMA_ONESHOT         (ADC_CFGR_DMNGT_0)                      /*!< DMA one shot mode selected */
00634 #define ADC_CONVERSIONDATA_DMA_CIRCULAR        (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)   /*!< DMA circular mode selected */
00635 /**
00636   * @}
00637   */
00638 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00639   * @{
00640   */
00641 #define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
00642 #define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
00643 #define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
00649   * @{
00650   */
00651 #define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */
00652 #define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)                    /*!< Analog watchdog applied to a regular group single channel               */
00653 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)                   /*!< Analog watchdog applied to an injected group single channel             */
00654 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
00655 #define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                                       /*!< Analog watchdog applied to regular group all channels                   */
00656 #define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                                      /*!< Analog watchdog applied to injected group all channels                  */
00657 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)                    /*!< Analog watchdog applied to regular and injected groups all channels     */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
00663   * @{
00664   */
00665 #define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
00666 #define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
00667 #define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
00668 #define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
00669 #define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
00670 #define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
00671 #define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
00672 #define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
00673 #define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
00674 #define ADC_RIGHTBITSHIFT_9                (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
00675 #define ADC_RIGHTBITSHIFT_10               (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
00676 #define ADC_RIGHTBITSHIFT_11               (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
00677 /**
00678   * @}
00679   */
00680
00681 /** @defgroup ADCEx_Left_Bit_Shift   ADC Extended Oversampling left Shift
00682   * @{
00683   */
00684 #define ADC_LEFTBITSHIFT_NONE  (LL_ADC_LEFT_BIT_SHIFT_NONE)   /*!<  ADC No bit shift */
00685 #define ADC_LEFTBITSHIFT_1     (LL_ADC_LEFT_BIT_SHIFT_1)      /*!<  ADC 1 bit shift  */
00686 #define ADC_LEFTBITSHIFT_2     (LL_ADC_LEFT_BIT_SHIFT_2)      /*!<  ADC 2 bits shift */
00687 #define ADC_LEFTBITSHIFT_3     (LL_ADC_LEFT_BIT_SHIFT_3)      /*!<  ADC 3 bits shift */
00688 #define ADC_LEFTBITSHIFT_4     (LL_ADC_LEFT_BIT_SHIFT_4)      /*!<  ADC 4 bits shift */
00689 #define ADC_LEFTBITSHIFT_5     (LL_ADC_LEFT_BIT_SHIFT_5)      /*!<  ADC 5 bits shift */
00690 #define ADC_LEFTBITSHIFT_6     (LL_ADC_LEFT_BIT_SHIFT_6)      /*!<  ADC 6 bits shift */
00691 #define ADC_LEFTBITSHIFT_7     (LL_ADC_LEFT_BIT_SHIFT_7)      /*!<  ADC 7 bits shift */
00692 #define ADC_LEFTBITSHIFT_8     (LL_ADC_LEFT_BIT_SHIFT_8)      /*!<  ADC 8 bits shift */
00693 #define ADC_LEFTBITSHIFT_9     (LL_ADC_LEFT_BIT_SHIFT_9)      /*!<  ADC 9 bits shift */
00694 #define ADC_LEFTBITSHIFT_10    (LL_ADC_LEFT_BIT_SHIFT_10)     /*!<  ADC 10 bits shift */
00695 #define ADC_LEFTBITSHIFT_11    (LL_ADC_LEFT_BIT_SHIFT_11)     /*!<  ADC 11 bits shift */
00696 #define ADC_LEFTBITSHIFT_12    (LL_ADC_LEFT_BIT_SHIFT_12)     /*!<  ADC 12 bits shift */
00697 #define ADC_LEFTBITSHIFT_13    (LL_ADC_LEFT_BIT_SHIFT_13)     /*!<  ADC 13 bits shift */
00698 #define ADC_LEFTBITSHIFT_14    (LL_ADC_LEFT_BIT_SHIFT_14)     /*!<  ADC 14 bits shift */
00699 #define ADC_LEFTBITSHIFT_15    (LL_ADC_LEFT_BIT_SHIFT_15)     /*!<  ADC 15 bits shift */
00700 /**
00701   * @}
00702   */
00703
00704 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
00705   * @{
00706   */
00707 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
00708 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
00714   * @{
00715   */
00716 #define ADC_REGOVERSAMPLING_CONTINUED_MODE    (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
00717 #define ADC_REGOVERSAMPLING_RESUMED_MODE      (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during injection sequence     */
00718 /**
00719   * @}
00720   */
00721
00722
00723 /** @defgroup ADC_Event_type ADC Event type
00724   * @{
00725   */
00726 #define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
00727 #define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
00728 #define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
00729 #define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
00730 #define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
00731 #define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
00732 /**
00733   * @}
00734   */
00735 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
00736
00737 /** @defgroup ADC_interrupts_definition ADC interrupts definition
00738   * @{
00739   */
00740 #define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
00741 #define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
00742 #define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
00743 #define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
00744 #define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
00745 #define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
00746 #define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
00747 #define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
00748 #define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
00749 #define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
00750 #define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */
00751
00752 #define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
00753
00754 /**
00755   * @}
00756   */
00757
00758 /** @defgroup ADC_flags_definition ADC flags definition
00759   * @{
00760   */
00761 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
00762 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
00763 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
00764 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
00765 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
00766 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
00767 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
00768 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
00769 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
00770 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
00771 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780
00781 /* Private macro -------------------------------------------------------------*/
00782
00783 /** @defgroup ADC_Private_Macros ADC Private Macros
00784   * @{
00785   */
00786 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00787 /* code of final user.                                                        */
00788
00789 /**
00790   * @brief Verify the ADC data conversion setting.
00791   * @param DATA : programmed DATA conversion mode.
00792   * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
00793   */
00794 #define IS_ADC_CONVERSIONDATAMGT(DATA)                                         \
00795    ((((DATA) == ADC_CONVERSIONDATA_DR))          || \
00796     (((DATA) == ADC_CONVERSIONDATA_DFSDM))       || \
00797     (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
00798     (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
00799
00800 /**
00801   * @brief Return resolution bits in CFGR register RES[1:0] field.
00802   * @param __HANDLE__ ADC handle
00803   * @retval Value of bitfield RES in CFGR register.
00804   */
00805 #define ADC_GET_RESOLUTION(__HANDLE__)                                         \
00806   (LL_ADC_GetResolution((__HANDLE__)->Instance))
00807
00808 /**
00809   * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
00810   * @param __HANDLE__ ADC handle
00811   * @retval None
00812   */
00813 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00814
00815 /**
00816   * @brief Verification of ADC state: enabled or disabled.
00817   * @param __HANDLE__ ADC handle
00818   * @retval SET (ADC enabled) or RESET (ADC disabled)
00819   */
00820 #define ADC_IS_ENABLE(__HANDLE__)                                                    \
00821        (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
00822           ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
00823         ) ? SET : RESET)
00824
00825 /**
00826   * @brief Check if conversion is on going on regular group.
00827   * @param __HANDLE__ ADC handle
00828   * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
00829   */
00830 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
00831   (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
00832
00833 /**
00834   * @brief Check if ADC clock mode is synchronous
00835   * @param __HANDLE__: ADC handle
00836   * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)
00837   */
00838 #if defined (ADC3)
00839 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)                                   \
00840        (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \
00841      ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)                              \
00842      :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))
00843 #else
00844 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)     ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
00845
00846 #endif
00847
00848 /**
00849   * @brief Simultaneously clear and set specific bits of the handle State.
00850   * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00851   *        the first parameter is the ADC handle State, the second parameter is the
00852   *        bit field to clear, the third and last parameter is the bit field to set.
00853   * @retval None
00854   */
00855 #define ADC_STATE_CLR_SET MODIFY_REG
00856
00857 /**
00858   * @brief Verify that a given value is aligned with the ADC resolution range.
00859   * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).
00860   * @param __ADC_VALUE__ value checked against the resolution.
00861   * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
00862   */
00863 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
00864   ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
00865
00866 /**
00867   * @brief Verify the length of the scheduled regular conversions group.
00868   * @param __LENGTH__ number of programmed conversions.
00869   * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
00870   */
00871 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
00872
00873
00874 /**
00875   * @brief Verify the number of scheduled regular conversions in discontinuous mode.
00876   * @param NUMBER number of scheduled regular conversions in discontinuous mode.
00877   * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
00878   */
00879 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
00880
00881
00882 /**
00883   * @brief Verify the ADC clock setting.
00884   * @param __ADC_CLOCK__ programmed ADC clock.
00885   * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
00886   */
00887 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
00888                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00889                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00890                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
00891                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
00892                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
00893                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
00894                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
00895                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
00896                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
00897                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
00898                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
00899                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
00900                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
00901                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
00902
00903 /**
00904   * @brief Verify the ADC resolution setting.
00905   * @param __RESOLUTION__ programmed ADC resolution.
00906   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00907   */
00908 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
00909                                            ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
00910                                            ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
00911                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
00912                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)    )
00913 /**
00914   * @brief Verify the ADC resolution setting when limited to 8 bits.
00915   * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.
00916   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00917   */
00918 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
00919
00920 /**
00921   * @brief Verify the ADC scan mode.
00922   * @param __SCAN_MODE__ programmed ADC scan mode.
00923   * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
00924   */
00925 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
00926                                          ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
00927
00928 /**
00929   * @brief Verify the ADC edge trigger setting for regular group.
00930   * @param __EDGE__ programmed ADC edge trigger setting.
00931   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
00932   */
00933 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
00934                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
00935                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
00936                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
00937
00938 /**
00939   * @brief Verify the ADC regular conversions external trigger.
00940   * @param __REGTRIG__ programmed ADC regular conversions external trigger.
00941   * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
00942   */
00943 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
00944                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
00945                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)        || \
00946                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
00947                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)       || \
00948                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
00949                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)      || \
00950                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)       || \
00951                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)      || \
00952                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)       || \
00953                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)      || \
00954                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)       || \
00955                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)       || \
00956                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)       || \
00957                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)      || \
00958                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
00959                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1)   || \
00960                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3)   || \
00961                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT)    || \
00962                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT)    || \
00963                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT)    || \
00964                                      ((__REGTRIG__) == ADC_SOFTWARE_START)           )
00965
00966 /**
00967   * @brief Verify the ADC regular conversions check for converted data availability.
00968   * @param __EOC_SELECTION__ converted data availability check.
00969   * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
00970   */
00971 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
00972                                                  ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
00973
00974 /**
00975   * @brief Verify the ADC regular conversions overrun handling.
00976   * @param __OVR__ ADC regular conversions overrun handling.
00977   * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
00978   */
00979 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
00980                                  ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
00981
00982 /**
00983   * @brief Verify the ADC conversions sampling time.
00984   * @param __TIME__ ADC conversions sampling time.
00985   * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
00986   */
00987 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5)    || \
00988                                       ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
00989                                       ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5)   || \
00990                                       ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5)  || \
00991                                       ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5)  || \
00992                                       ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5)  || \
00993                                       ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
00994                                       ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5)   )
00995
00996 /**
00997   * @brief Verify the ADC regular channel setting.
00998   * @param  __CHANNEL__ programmed ADC regular channel.
00999   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01000   */
01001 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
01002                                           ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
01003                                           ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
01004                                           ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
01005                                           ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
01006                                           ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
01007                                           ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
01008                                           ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
01009                                           ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
01010                                           ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
01011                                           ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
01012                                           ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
01013                                           ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
01014                                           ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
01015                                           ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
01016                                           ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
01017
01018 /**
01019   * @}
01020   */
01021
01022
01023 /* Private constants ---------------------------------------------------------*/
01024
01025 /** @defgroup ADC_Private_Constants ADC Private Constants
01026   * @{
01027   */
01028
01029 /* Fixed timeout values for ADC conversion (including sampling time)        */
01030 /* Maximum sampling time is 810.5 ADC clock cycle        */
01031 /* Maximum conversion time is 16.5 + Maximum sampling time                  */
01032 /*                       or 16.5  + 810.5 = 827 ADC clock cycles            */
01033 /* Minimum ADC Clock frequency is 0.35 MHz                                  */
01034 /* Maximum conversion time is                                               */
01035 /*              827 / 0.35 MHz = 2.36 ms                                    */
01036
01037 #define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */
01038
01039 /* Delay for temperature sensor stabilization time.                         */
01040 /* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
01041 /* Unit: us                                                                 */
01042 #define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
01043
01044 /* Delay for ADC voltage regulator startup time                               */
01045 /*  Maximum delay is 10 microseconds                                          */
01046 /* (refer device RM, parameter Tadcvreg_stup).                                */
01047 #define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
01048
01049 /**
01050   * @}
01051   */
01052
01053 /* Exported macro ------------------------------------------------------------*/
01054
01055 /** @defgroup ADC_Exported_Macros ADC Exported Macros
01056   * @{
01057   */
01058 /* Macro for internal HAL driver usage, and possibly can be used into code of */
01059 /* final user.                                                                */
01060
01061 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
01062   * @{
01063   */
01064
01065 /** @brief  Reset ADC handle state.
01066   * @param __HANDLE__ ADC handle
01067   * @retval None
01068   */
01069 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01070 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01071   do{                                                                          \
01072     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
01073     (__HANDLE__)->MspInitCallback = NULL;                                      \
01074     (__HANDLE__)->MspDeInitCallback = NULL;                                    \
01075   } while(0)
01076 #else
01077 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01078   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
01079 #endif
01080
01081 /**
01082   * @brief Enable ADC interrupt.
01083   * @param __HANDLE__ ADC handle
01084   * @param __INTERRUPT__ ADC Interrupt
01085   *        This parameter can be one of the following values:
01086   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01087   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01088   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01089   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01090   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01091   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01092   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01093   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01094   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01095   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01096   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01097   * @retval None
01098   */
01099 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
01100   (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
01101
01102 /**
01103   * @brief Disable ADC interrupt.
01104   * @param __HANDLE__ ADC handle
01105   * @param __INTERRUPT__ ADC Interrupt
01106   *        This parameter can be one of the following values:
01107   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01108   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01109   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01110   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01111   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01112   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01113   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01114   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01115   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01116   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01117   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01118   * @retval None
01119   */
01120 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
01121   (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
01122
01123 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
01124   * @param __HANDLE__ ADC handle
01125   * @param __INTERRUPT__ ADC interrupt source to check
01126   *          This parameter can be one of the following values:
01127   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01128   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01129   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01130   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01131   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01132   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01133   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01134   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01135   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01136   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01137   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01138   * @retval State of interruption (SET or RESET)
01139   */
01140 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
01141   (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
01142
01143 /**
01144   * @brief Check whether the specified ADC flag is set or not.
01145   * @param __HANDLE__ ADC handle
01146   * @param __FLAG__ ADC flag
01147   *        This parameter can be one of the following values:
01148   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01149   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01150   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01151   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01152   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01153   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01154   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01155   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01156   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01157   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01158   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01159   * @retval State of flag (TRUE or FALSE).
01160   */
01161 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
01162   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
01163
01164 /**
01165   * @brief Clear the specified ADC flag.
01166   * @param __HANDLE__ ADC handle
01167   * @param __FLAG__ ADC flag
01168   *        This parameter can be one of the following values:
01169   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01170   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01171   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01172   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01173   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01174   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01175   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01176   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01177   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01178   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01179   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01180   * @retval None
01181   */
01182 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
01183 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
01184   (((__HANDLE__)->Instance->ISR) = (__FLAG__))
01185
01186 /**
01187   * @}
01188   */
01189
01190 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
01191   * @{
01192   */
01193
01194 /**
01195   * @brief  Helper macro to get ADC channel number in decimal format
01196   *         from literals ADC_CHANNEL_x.
01197   * @note   Example:
01198   *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
01199   *           will return decimal number "4".
01200   * @note   The input can be a value from functions where a channel
01201   *         number is returned, either defined with number
01202   *         or with bitfield (only one bit must be set).
01203   * @param  __CHANNEL__ This parameter can be one of the following values:
01204   *         @arg @ref ADC_CHANNEL_0           (3)
01205   *         @arg @ref ADC_CHANNEL_1           (3)
01206   *         @arg @ref ADC_CHANNEL_2           (3)
01207   *         @arg @ref ADC_CHANNEL_3           (3)
01208   *         @arg @ref ADC_CHANNEL_4           (3)
01209   *         @arg @ref ADC_CHANNEL_5           (3)
01210   *         @arg @ref ADC_CHANNEL_6
01211   *         @arg @ref ADC_CHANNEL_7
01212   *         @arg @ref ADC_CHANNEL_8
01213   *         @arg @ref ADC_CHANNEL_9
01214   *         @arg @ref ADC_CHANNEL_10
01215   *         @arg @ref ADC_CHANNEL_11
01216   *         @arg @ref ADC_CHANNEL_12
01217   *         @arg @ref ADC_CHANNEL_13
01218   *         @arg @ref ADC_CHANNEL_14
01219   *         @arg @ref ADC_CHANNEL_15
01220   *         @arg @ref ADC_CHANNEL_16
01221   *         @arg @ref ADC_CHANNEL_17
01222   *         @arg @ref ADC_CHANNEL_18
01223   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01224   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)
01225   *         @arg @ref ADC_CHANNEL_VBAT         (1)
01226   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
01227   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
01228   *
01229   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01230   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01231   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01232   *             Other channels are slow channels (conversion rate: refer to reference manual).
01233   * @retval Value between Min_Data=0 and Max_Data=18
01234   */
01235 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
01236   __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
01237
01238 /**
01239   * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
01240   *         from number in decimal format.
01241   * @note   Example:
01242   *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01243   *           will return a data equivalent to "ADC_CHANNEL_4".
01244   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01245   * @retval Returned value can be one of the following values:
01246   *         @arg @ref ADC_CHANNEL_0           (3)
01247   *         @arg @ref ADC_CHANNEL_1           (3)
01248   *         @arg @ref ADC_CHANNEL_2           (3)
01249   *         @arg @ref ADC_CHANNEL_3           (3)
01250   *         @arg @ref ADC_CHANNEL_4           (3)
01251   *         @arg @ref ADC_CHANNEL_5           (3)
01252   *         @arg @ref ADC_CHANNEL_6
01253   *         @arg @ref ADC_CHANNEL_7
01254   *         @arg @ref ADC_CHANNEL_8
01255   *         @arg @ref ADC_CHANNEL_9
01256   *         @arg @ref ADC_CHANNEL_10
01257   *         @arg @ref ADC_CHANNEL_11
01258   *         @arg @ref ADC_CHANNEL_12
01259   *         @arg @ref ADC_CHANNEL_13
01260   *         @arg @ref ADC_CHANNEL_14
01261   *         @arg @ref ADC_CHANNEL_15
01262   *         @arg @ref ADC_CHANNEL_16
01263   *         @arg @ref ADC_CHANNEL_17
01264   *         @arg @ref ADC_CHANNEL_18
01265   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01266   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)
01267   *         @arg @ref ADC_CHANNEL_VBAT         (1)
01268   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
01269   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
01270   *
01271   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01272   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01273   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01274   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
01275   *         (1, 2) For ADC channel read back from ADC register,
01276   *                comparison with internal channel parameter to be done
01277   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01278   */
01279 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
01280   __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
01281
01282 /**
01283   * @brief  Helper macro to determine whether the selected channel
01284   *         corresponds to literal definitions of driver.
01285   * @note   The different literal definitions of ADC channels are:
01286   *         - ADC internal channel:
01287   *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
01288   *         - ADC external channel (channel connected to a GPIO pin):
01289   *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
01290   * @note   The channel parameter must be a value defined from literal
01291   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01292   *         ADC_CHANNEL_TEMPSENSOR, ...),
01293   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
01294   *         must not be a value from functions where a channel number is
01295   *         returned from ADC registers,
01296   *         because internal and external channels share the same channel
01297   *         number in ADC registers. The differentiation is made only with
01298   *         parameters definitions of driver.
01299   * @param  __CHANNEL__ This parameter can be one of the following values:
01300   *         @arg @ref ADC_CHANNEL_0           (3)
01301   *         @arg @ref ADC_CHANNEL_1           (3)
01302   *         @arg @ref ADC_CHANNEL_2           (3)
01303   *         @arg @ref ADC_CHANNEL_3           (3)
01304   *         @arg @ref ADC_CHANNEL_4           (3)
01305   *         @arg @ref ADC_CHANNEL_5           (3)
01306   *         @arg @ref ADC_CHANNEL_6
01307   *         @arg @ref ADC_CHANNEL_7
01308   *         @arg @ref ADC_CHANNEL_8
01309   *         @arg @ref ADC_CHANNEL_9
01310   *         @arg @ref ADC_CHANNEL_10
01311   *         @arg @ref ADC_CHANNEL_11
01312   *         @arg @ref ADC_CHANNEL_12
01313   *         @arg @ref ADC_CHANNEL_13
01314   *         @arg @ref ADC_CHANNEL_14
01315   *         @arg @ref ADC_CHANNEL_15
01316   *         @arg @ref ADC_CHANNEL_16
01317   *         @arg @ref ADC_CHANNEL_17
01318   *         @arg @ref ADC_CHANNEL_18
01319   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01320   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)
01321   *         @arg @ref ADC_CHANNEL_VBAT         (1)
01322   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
01323   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
01324   *
01325   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01326   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01327   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01328   *             Other channels are slow channels (conversion rate: refer to reference manual).
01329   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01330   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01331   */
01332 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
01333   __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
01334
01335 /**
01336   * @brief  Helper macro to convert a channel defined from parameter
01337   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01338   *         ADC_CHANNEL_TEMPSENSOR, ...),
01339   *         to its equivalent parameter definition of a ADC external channel
01340   *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
01341   * @note   The channel parameter can be, additionally to a value
01342   *         defined from parameter definition of a ADC internal channel
01343   *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
01344   *         a value defined from parameter definition of
01345   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01346   *         or a value from functions where a channel number is returned
01347   *         from ADC registers.
01348   * @param  __CHANNEL__ This parameter can be one of the following values:
01349   *         @arg @ref ADC_CHANNEL_0           (3)
01350   *         @arg @ref ADC_CHANNEL_1           (3)
01351   *         @arg @ref ADC_CHANNEL_2           (3)
01352   *         @arg @ref ADC_CHANNEL_3           (3)
01353   *         @arg @ref ADC_CHANNEL_4           (3)
01354   *         @arg @ref ADC_CHANNEL_5           (3)
01355   *         @arg @ref ADC_CHANNEL_6
01356   *         @arg @ref ADC_CHANNEL_7
01357   *         @arg @ref ADC_CHANNEL_8
01358   *         @arg @ref ADC_CHANNEL_9
01359   *         @arg @ref ADC_CHANNEL_10
01360   *         @arg @ref ADC_CHANNEL_11
01361   *         @arg @ref ADC_CHANNEL_12
01362   *         @arg @ref ADC_CHANNEL_13
01363   *         @arg @ref ADC_CHANNEL_14
01364   *         @arg @ref ADC_CHANNEL_15
01365   *         @arg @ref ADC_CHANNEL_16
01366   *         @arg @ref ADC_CHANNEL_17
01367   *         @arg @ref ADC_CHANNEL_18
01368   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01369   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)
01370   *         @arg @ref ADC_CHANNEL_VBAT         (1)
01371   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
01372   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
01373   *
01374   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01375   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01376   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01377   *             Other channels are slow channels (conversion rate: refer to reference manual).
01378   * @retval Returned value can be one of the following values:
01379   *         @arg @ref ADC_CHANNEL_0
01380   *         @arg @ref ADC_CHANNEL_1
01381   *         @arg @ref ADC_CHANNEL_2
01382   *         @arg @ref ADC_CHANNEL_3
01383   *         @arg @ref ADC_CHANNEL_4
01384   *         @arg @ref ADC_CHANNEL_5
01385   *         @arg @ref ADC_CHANNEL_6
01386   *         @arg @ref ADC_CHANNEL_7
01387   *         @arg @ref ADC_CHANNEL_8
01388   *         @arg @ref ADC_CHANNEL_9
01389   *         @arg @ref ADC_CHANNEL_10
01390   *         @arg @ref ADC_CHANNEL_11
01391   *         @arg @ref ADC_CHANNEL_12
01392   *         @arg @ref ADC_CHANNEL_13
01393   *         @arg @ref ADC_CHANNEL_14
01394   *         @arg @ref ADC_CHANNEL_15
01395   *         @arg @ref ADC_CHANNEL_16
01396   *         @arg @ref ADC_CHANNEL_17
01397   *         @arg @ref ADC_CHANNEL_18
01398   */
01399 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
01400   __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
01401
01402 /**
01403   * @brief  Helper macro to determine whether the internal channel
01404   *         selected is available on the ADC instance selected.
01405   * @note   The channel parameter must be a value defined from parameter
01406   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01407   *         ADC_CHANNEL_TEMPSENSOR, ...),
01408   *         must not be a value defined from parameter definition of
01409   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01410   *         or a value from functions where a channel number is
01411   *         returned from ADC registers,
01412   *         because internal and external channels share the same channel
01413   *         number in ADC registers. The differentiation is made only with
01414   *         parameters definitions of driver.
01415   * @param  __ADC_INSTANCE__ ADC instance
01416   * @param  __CHANNEL__ This parameter can be one of the following values:
01417   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01418   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)
01419   *         @arg @ref ADC_CHANNEL_VBAT         (1)
01420   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
01421   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
01422   *
01423   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01424   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.
01425   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01426   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01427   */
01428 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01429   __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
01430
01431 /**
01432   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01433   *         or ADC slave from raw value with both ADC conversion data concatenated.
01434   * @note   This macro is intended to be used when multimode transfer by DMA
01435   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
01436   *         In this case the transferred data need to processed with this macro
01437   *         to separate the conversion data of ADC master and ADC slave.
01438   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
01439   *         @arg @ref LL_ADC_MULTI_MASTER
01440   *         @arg @ref LL_ADC_MULTI_SLAVE
01441   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
01442   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01443   */
01444 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
01445   __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
01446
01447 /**
01448   * @brief  Helper macro to select the ADC common instance
01449   *         to which is belonging the selected ADC instance.
01450   * @note   ADC common register instance can be used for:
01451   *         - Set parameters common to several ADC instances
01452   *         - Multimode (for devices with several ADC instances)
01453   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01454   * @param  __ADCx__ ADC instance
01455   * @retval ADC common register instance
01456   */
01457 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
01458   __LL_ADC_COMMON_INSTANCE((__ADCx__))
01459
01460 /**
01461   * @brief  Helper macro to check if all ADC instances sharing the same
01462   *         ADC common instance are disabled.
01463   * @note   This check is required by functions with setting conditioned to
01464   *         ADC state:
01465   *         All ADC instances of the ADC common group must be disabled.
01466   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01467   * @note   On devices with only 1 ADC common instance, parameter of this macro
01468   *         is useless and can be ignored (parameter kept for compatibility
01469   *         with devices featuring several ADC common instances).
01470   * @param  __ADCXY_COMMON__ ADC common instance
01471   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01472   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01473   *         are disabled.
01474   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01475   *         is enabled.
01476   */
01477 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01478   __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
01479
01480 /**
01481   * @brief  Helper macro to define the ADC conversion data full-scale digital
01482   *         value corresponding to the selected ADC resolution.
01483   * @note   ADC conversion data full-scale corresponds to voltage range
01484   *         determined by analog voltage references Vref+ and Vref-
01485   *         (refer to reference manual).
01486   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01487   *         @arg @ref ADC_RESOLUTION_16B
01488   *         @arg @ref ADC_RESOLUTION_14B
01489   *         @arg @ref ADC_RESOLUTION_12B
01490   *         @arg @ref ADC_RESOLUTION_10B
01491   *         @arg @ref ADC_RESOLUTION_8B
01492   * @retval ADC conversion data full-scale digital value
01493   */
01494 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01495   __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
01496
01497 /**
01498   * @brief  Helper macro to convert the ADC conversion data from
01499   *         a resolution to another resolution.
01500   * @param  __DATA__ ADC conversion data to be converted
01501   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
01502   *         This parameter can be one of the following values:
01503   *         @arg @ref ADC_RESOLUTION_16B
01504   *         @arg @ref ADC_RESOLUTION_14B
01505   *         @arg @ref ADC_RESOLUTION_12B
01506   *         @arg @ref ADC_RESOLUTION_10B
01507   *         @arg @ref ADC_RESOLUTION_8B
01508   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01509   *         This parameter can be one of the following values:
01510   *         @arg @ref ADC_RESOLUTION_16B
01511   *         @arg @ref ADC_RESOLUTION_14B
01512   *         @arg @ref ADC_RESOLUTION_12B
01513   *         @arg @ref ADC_RESOLUTION_10B
01514   *         @arg @ref ADC_RESOLUTION_8B
01515   * @retval ADC conversion data to the requested resolution
01516   */
01517 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01518                                           __ADC_RESOLUTION_CURRENT__,\
01519                                           __ADC_RESOLUTION_TARGET__)            \
01520   __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
01521                                    (__ADC_RESOLUTION_CURRENT__),                \
01522                                    (__ADC_RESOLUTION_TARGET__))
01523
01524 /**
01525   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01526   *         corresponding to a ADC conversion data (unit: digital value).
01527   * @note   Analog reference voltage (Vref+) must be either known from
01528   *         user board environment or can be calculated using ADC measurement
01529   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01530   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01531   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01532   *                       (unit: digital value).
01533   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01534   *         @arg @ref ADC_RESOLUTION_16B
01535   *         @arg @ref ADC_RESOLUTION_14B
01536   *         @arg @ref ADC_RESOLUTION_12B
01537   *         @arg @ref ADC_RESOLUTION_10B
01538   *         @arg @ref ADC_RESOLUTION_8B
01539   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01540   */
01541 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01542                                        __ADC_DATA__,\
01543                                        __ADC_RESOLUTION__)                     \
01544   __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
01545                                 (__ADC_DATA__),                                \
01546                                 (__ADC_RESOLUTION__))
01547
01548 /**
01549   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01550   *         (unit: mVolt) from ADC conversion data of internal voltage
01551   *         reference VrefInt.
01552   * @note   Computation is using VrefInt calibration value
01553   *         stored in system memory for each device during production.
01554   * @note   This voltage depends on user board environment: voltage level
01555   *         connected to pin Vref+.
01556   *         On devices with small package, the pin Vref+ is not present
01557   *         and internally bonded to pin Vdda.
01558   * @note   On this STM32 serie, calibration data of internal voltage reference
01559   *         VrefInt corresponds to a resolution of 12 bits,
01560   *         this is the recommended ADC resolution to convert voltage of
01561   *         internal voltage reference VrefInt.
01562   *         Otherwise, this macro performs the processing to scale
01563   *         ADC conversion data to 12 bits.
01564   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
01565   *         of internal voltage reference VrefInt (unit: digital value).
01566   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01567   *         @arg @ref ADC_RESOLUTION_16B
01568   *         @arg @ref ADC_RESOLUTION_14B
01569   *         @arg @ref ADC_RESOLUTION_12B
01570   *         @arg @ref ADC_RESOLUTION_10B
01571   *         @arg @ref ADC_RESOLUTION_8B
01572   * @retval Analog reference voltage (unit: mV)
01573   */
01574 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
01575                                           __ADC_RESOLUTION__)                  \
01576   __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
01577                                   (__ADC_RESOLUTION__))
01578
01579 /**
01580   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01581   *         from ADC conversion data of internal temperature sensor.
01582   * @note   Computation is using temperature sensor calibration values
01583   *         stored in system memory for each device during production.
01584   * @note   Calculation formula:
01585   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01586   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01587   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01588   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01589   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01590   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01591   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01592   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01593   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01594   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01595   *         Caution: Calculation relevancy under reserve that calibration
01596   *                  parameters are correct (address and data).
01597   *                  To calculate temperature using temperature sensor
01598   *                  datasheet typical values (generic values less, therefore
01599   *                  less accurate than calibrated values),
01600   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01601   * @note   As calculation input, the analog reference voltage (Vref+) must be
01602   *         defined as it impacts the ADC LSB equivalent voltage.
01603   * @note   Analog reference voltage (Vref+) must be either known from
01604   *         user board environment or can be calculated using ADC measurement
01605   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01606   * @note   On this STM32 serie, calibration data of temperature sensor
01607   *         corresponds to a resolution of 12 bits,
01608   *         this is the recommended ADC resolution to convert voltage of
01609   *         temperature sensor.
01610   *         Otherwise, this macro performs the processing to scale
01611   *         ADC conversion data to 12 bits.
01612   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
01613   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
01614   *                                 temperature sensor (unit: digital value).
01615   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
01616   *                                 sensor voltage has been measured.
01617   *         This parameter can be one of the following values:
01618   *         @arg @ref ADC_RESOLUTION_16B
01619   *         @arg @ref ADC_RESOLUTION_14B
01620   *         @arg @ref ADC_RESOLUTION_12B
01621   *         @arg @ref ADC_RESOLUTION_10B
01622   *         @arg @ref ADC_RESOLUTION_8B
01623   * @retval Temperature (unit: degree Celsius)
01624   */
01625 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
01626                                    __TEMPSENSOR_ADC_DATA__,\
01627                                    __ADC_RESOLUTION__)                         \
01628   __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
01629                             (__TEMPSENSOR_ADC_DATA__),                         \
01630                             (__ADC_RESOLUTION__))
01631
01632 /**
01633   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01634   *         from ADC conversion data of internal temperature sensor.
01635   * @note   Computation is using temperature sensor typical values
01636   *         (refer to device datasheet).
01637   * @note   Calculation formula:
01638   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01639   *                         / Avg_Slope + CALx_TEMP
01640   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01641   *                                   (unit: digital value)
01642   *                Avg_Slope        = temperature sensor slope
01643   *                                   (unit: uV/Degree Celsius)
01644   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01645   *                                   temperature CALx_TEMP (unit: mV)
01646   *         Caution: Calculation relevancy under reserve the temperature sensor
01647   *                  of the current device has characteristics in line with
01648   *                  datasheet typical values.
01649   *                  If temperature sensor calibration values are available on
01650   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01651   *                  temperature calculation will be more accurate using
01652   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01653   * @note   As calculation input, the analog reference voltage (Vref+) must be
01654   *         defined as it impacts the ADC LSB equivalent voltage.
01655   * @note   Analog reference voltage (Vref+) must be either known from
01656   *         user board environment or can be calculated using ADC measurement
01657   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01658   * @note   ADC measurement data must correspond to a resolution of 12bits
01659   *         (full scale digital value 4095). If not the case, the data must be
01660   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01661   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01662   *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".
01663   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01664   *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
01665   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01666   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01667   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01668   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01669   *         This parameter can be one of the following values:
01670   *         @arg @ref ADC_RESOLUTION_16B
01671   *         @arg @ref ADC_RESOLUTION_14B
01672   *         @arg @ref ADC_RESOLUTION_12B
01673   *         @arg @ref ADC_RESOLUTION_10B
01674   *         @arg @ref ADC_RESOLUTION_8B
01675   * @retval Temperature (unit: degree Celsius)
01676   */
01677 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01678                                               __TEMPSENSOR_TYP_CALX_V__,\
01679                                               __TEMPSENSOR_CALX_TEMP__,\
01680                                               __VREFANALOG_VOLTAGE__,\
01681                                               __TEMPSENSOR_ADC_DATA__,\
01682                                               __ADC_RESOLUTION__)              \
01683   __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
01684                                       (__TEMPSENSOR_TYP_CALX_V__),             \
01685                                       (__TEMPSENSOR_CALX_TEMP__),              \
01686                                       (__VREFANALOG_VOLTAGE__),                \
01687                                       (__TEMPSENSOR_ADC_DATA__),               \
01688                                       (__ADC_RESOLUTION__))
01689
01690 /**
01691   * @}
01692   */
01693
01694 /**
01695   * @}
01696   */
01697
01698 /* Include ADC HAL Extended module */
01699 #include "stm32h7xx_hal_adc_ex.h"
01700
01701 /* Exported functions --------------------------------------------------------*/
01702 /** @addtogroup ADC_Exported_Functions
01703   * @{
01704   */
01705
01706 /** @addtogroup ADC_Exported_Functions_Group1
01707   * @brief    Initialization and Configuration functions
01708   * @{
01709   */
01710 /* Initialization and de-initialization functions  ****************************/
01711 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
01712 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
01713 void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
01714 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
01715
01716 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01717 /* Callbacks Register/UnRegister functions  ***********************************/
01718 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
01719                                            pADC_CallbackTypeDef pCallback);
01720 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
01721 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01722 /**
01723   * @}
01724   */
01725
01726 /** @addtogroup ADC_Exported_Functions_Group2
01727   * @brief    IO operation functions
01728   * @{
01729   */
01730 /* IO operation functions  *****************************************************/
01731
01732 /* Blocking mode: Polling */
01733 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
01734 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
01735 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
01736 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
01737
01738 /* Non-blocking mode: Interruption */
01739 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
01740 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
01741
01742 /* Non-blocking mode: DMA */
01743 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01744 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
01745
01746 /* ADC retrieve conversion value intended to be used with polling or interruption */
01747 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
01748
01749 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
01750 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
01751 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
01752 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
01753 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
01754 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
01755 /**
01756   * @}
01757   */
01758
01759 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
01760   *  @brief    Peripheral Control functions
01761   * @{
01762   */
01763 /* Peripheral Control functions ***********************************************/
01764 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
01765 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
01766
01767 /**
01768   * @}
01769   */
01770
01771 /* Peripheral State functions *************************************************/
01772 /** @addtogroup ADC_Exported_Functions_Group4
01773   * @{
01774   */
01775 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
01776 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
01777
01778 /**
01779   * @}
01780   */
01781
01782 /**
01783   * @}
01784   */
01785
01786 /* Private functions -----------------------------------------------------------*/
01787 /** @addtogroup ADC_Private_Functions ADC Private Functions
01788   * @{
01789   */
01790 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
01791 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
01792 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
01793 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
01794 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
01795 void ADC_DMAError(DMA_HandleTypeDef *hdma);
01796 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
01797
01798 /**
01799   * @}
01800   */
01801
01802 /**
01803   * @}
01804   */
01805
01806 /**
01807   * @}
01808   */
01809
01810 #ifdef __cplusplus
01811 }
01812 #endif
01813
01814
01815 #endif /* STM32H7xx_HAL_ADC_H */
01816
01817 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:56 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc_ex.c Source File

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stm32h7xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Operation functions
00009   *             ++ Start, stop, get result of conversions of ADC group injected,
00010   *                using 2 possible modes: polling, interruption.
00011   *             ++ Calibration
00012   *               +++ ADC automatic self-calibration
00013   *               +++ Calibration factors get or set
00014   *             ++ Multimode feature when available
00015   *           + Control functions
00016   *             ++ Channels configuration on ADC group injected
00017   *           + State functions
00018   *             ++ ADC group injected contexts queue management
00019   *          Other functions (generic functions) are available in file
00020   *          "stm32h7xx_hal_adc.c".
00021   *
00022   @verbatim
00023   [..]
00024   (@) Sections "ADC peripheral features" and "How to use this driver" are
00025       available in file of generic functions "stm32h7xx_hal_adc.c".
00026   [..]
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00032   * All rights reserved.</center></h2>
00033   *
00034   * This software component is licensed by ST under BSD 3-Clause license,
00035   * the "License"; You may not use this file except in compliance with the
00036   * License. You may obtain a copy of the License at:
00037   *                        opensource.org/licenses/BSD-3-Clause
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup ADCEx ADCEx
00050   * @brief ADC Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_ADC_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058
00059 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00060   * @{
00061   */
00062
00063 #define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00064                            ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
00065                            ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
00066                                                                   once the ADC is enabled */
00067
00068 /* Fixed timeout value for ADC calibration.                                   */
00069 /* Fixed timeout value for ADC calibration.                                     */
00070 /* Values defined to be higher than worst cases: low clock frequency,           */
00071 /* maximum prescalers.                                                          */
00072 /* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value              */
00073 /* according to Data sheet), calibration_time MAX = 165010 / f_ADC              */
00074 /*           165010 / 125000 = 1.32s                                            */
00075 /* At maximum CPU speed (480 MHz), this means                                   */
00076 /*    1.32 * 480 MHz = 633600000 CPU cycles                                     */
00077 #define ADC_CALIBRATION_TIMEOUT         (633600000U)   /*!< ADC calibration time-out value */
00078
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Private macro -------------------------------------------------------------*/
00085 /* Private variables ---------------------------------------------------------*/
00086 /* Private function prototypes -----------------------------------------------*/
00087 /* Exported functions --------------------------------------------------------*/
00088
00089 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00090   * @{
00091   */
00092
00093 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00094   * @brief    Extended IO operation functions
00095   *
00096 @verbatim
00097  ===============================================================================
00098                       ##### IO operation functions #####
00099  ===============================================================================
00100     [..]  This section provides functions allowing to:
00101
00102       (+) Perform the ADC self-calibration for single or differential ending.
00103       (+) Get calibration factors for single or differential ending.
00104       (+) Set calibration factors for single or differential ending.
00105
00106       (+) Start conversion of ADC group injected.
00107       (+) Stop conversion of ADC group injected.
00108       (+) Poll for conversion complete on ADC group injected.
00109       (+) Get result of ADC group injected channel conversion.
00110       (+) Start conversion of ADC group injected and enable interruptions.
00111       (+) Stop conversion of ADC group injected and disable interruptions.
00112
00113       (+) When multimode feature is available, start multimode and enable DMA transfer.
00114       (+) Stop multimode and disable ADC DMA transfer.
00115       (+) Get result of multimode conversion.
00116
00117 @endverbatim
00118   * @{
00119   */
00120
00121 /**
00122   * @brief  Perform an ADC automatic self-calibration
00123   *         Calibration prerequisite: ADC must be disabled (execute this
00124   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00125   * @param  hadc       ADC handle
00126 * @param  CalibrationMode       Selection of calibration offset or
00127   *         linear calibration offset.
00128   *           @arg ADC_CALIB_OFFSET       Channel in mode calibration offset
00129   *           @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
00130   * @param  SingleDiff Selection of single-ended or differential input
00131   *         This parameter can be one of the following values:
00132   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00133   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00134   * @retval HAL status
00135   */
00136 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
00137 {
00138   HAL_StatusTypeDef tmp_hal_status;
00139   __IO uint32_t wait_loop_index = 0UL;
00140
00141   /* Check the parameters */
00142   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00143   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00144
00145   /* Process locked */
00146   __HAL_LOCK(hadc);
00147
00148   /* Calibration prerequisite: ADC must be disabled. */
00149
00150   /* Disable the ADC (if not already disabled) */
00151   tmp_hal_status = ADC_Disable(hadc);
00152
00153   /* Check if ADC is effectively disabled */
00154   if (tmp_hal_status == HAL_OK)
00155   {
00156     /* Set ADC state */
00157     ADC_STATE_CLR_SET(hadc->State,
00158                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00159                       HAL_ADC_STATE_BUSY_INTERNAL);
00160
00161     /* Start ADC calibration in mode single-ended or differential */
00162     LL_ADC_StartCalibration(hadc->Instance , CalibrationMode, SingleDiff );
00163
00164     /* Wait for calibration completion */
00165     while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
00166     {
00167       wait_loop_index++;
00168       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
00169       {
00170         /* Update ADC state machine to error */
00171         ADC_STATE_CLR_SET(hadc->State,
00172                           HAL_ADC_STATE_BUSY_INTERNAL,
00173                           HAL_ADC_STATE_ERROR_INTERNAL);
00174
00175         /* Process unlocked */
00176         __HAL_UNLOCK(hadc);
00177
00178         return HAL_ERROR;
00179       }
00180     }
00181
00182     /* Set ADC state */
00183     ADC_STATE_CLR_SET(hadc->State,
00184                       HAL_ADC_STATE_BUSY_INTERNAL,
00185                       HAL_ADC_STATE_READY);
00186   }
00187   else
00188   {
00189     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00190
00191     /* Note: No need to update variable "tmp_hal_status" here: already set    */
00192     /*       to state "HAL_ERROR" by function disabling the ADC.              */
00193   }
00194
00195   /* Process unlocked */
00196   __HAL_UNLOCK(hadc);
00197
00198   /* Return function status */
00199   return tmp_hal_status;
00200 }
00201
00202 /**
00203   * @brief  Get the calibration factor.
00204   * @param hadc ADC handle.
00205   * @param SingleDiff This parameter can be only:
00206   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00207   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00208   * @retval Calibration value.
00209   */
00210 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
00211 {
00212   /* Check the parameters */
00213   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00214   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00215
00216   /* Return the selected ADC calibration value */
00217   return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
00218 }
00219
00220 /**
00221   * @brief  Get the calibration factor from automatic conversion result
00222   * @param  hadc ADC handle
00223   * @param  LinearCalib_Buffer: Linear calibration factor
00224   * @retval HAL state
00225   */
00226 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
00227 {
00228   uint32_t cnt;
00229   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00230   uint32_t temp_REG_IsConversionOngoing = 0UL;
00231
00232   /* Check the parameters */
00233   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00234
00235   /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
00236   if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00237   {
00238     tmp_hal_status = ADC_Enable(hadc);
00239   }
00240
00241   if (tmp_hal_status == HAL_OK)
00242   {
00243     if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
00244     {
00245       LL_ADC_REG_StopConversion(hadc->Instance);
00246       temp_REG_IsConversionOngoing = 1UL;
00247     }
00248     for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
00249     {
00250       LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
00251     }
00252     if(temp_REG_IsConversionOngoing != 0UL)
00253     {
00254       LL_ADC_REG_StartConversion(hadc->Instance);
00255     }
00256   }
00257
00258   return tmp_hal_status;
00259 }
00260
00261 /**
00262   * @brief  Set the calibration factor to overwrite automatic conversion result.
00263   *         ADC must be enabled and no conversion is ongoing.
00264   * @param hadc ADC handle
00265   * @param SingleDiff This parameter can be only:
00266   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00267   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00268   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
00269   * @retval HAL state
00270   */
00271 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
00272 {
00273   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00274   uint32_t tmp_adc_is_conversion_on_going_regular;
00275   uint32_t tmp_adc_is_conversion_on_going_injected;
00276
00277   /* Check the parameters */
00278   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00279   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00280   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00281
00282   /* Process locked */
00283   __HAL_LOCK(hadc);
00284
00285   /* Verification of hardware constraints before modifying the calibration    */
00286   /* factors register: ADC must be enabled, no conversion on going.           */
00287   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00288   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00289
00290   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00291       && (tmp_adc_is_conversion_on_going_regular == 0UL)
00292       && (tmp_adc_is_conversion_on_going_injected == 0UL)
00293      )
00294   {
00295     /* Set the selected ADC calibration value */
00296     LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
00297   }
00298   else
00299   {
00300     /* Update ADC state machine */
00301     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00302     /* Update ADC error code */
00303     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00304
00305     /* Update ADC state machine to error */
00306     tmp_hal_status = HAL_ERROR;
00307   }
00308
00309   /* Process unlocked */
00310   __HAL_UNLOCK(hadc);
00311
00312   /* Return function status */
00313   return tmp_hal_status;
00314 }
00315
00316 /**
00317   * @brief  Set the linear calibration factor
00318   * @param  hadc ADC handle
00319   * @param  LinearCalib_Buffer: Linear calibration factor
00320   * @retval HAL state
00321   */
00322 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer)
00323 {
00324   uint32_t cnt;
00325   __IO uint32_t wait_loop_index = 0;
00326   uint32_t temp_REG_IsConversionOngoing = 0UL;
00327
00328   /* Check the parameters */
00329   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00330
00331   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00332   /*  Exit deep power down mode if still in that state                        */
00333   if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
00334   {
00335     /* Exit deep power down mode */
00336     CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00337
00338     /* System was in deep power down mode, calibration must
00339        be relaunched or a previously saved calibration factor
00340        re-applied once the ADC voltage regulator is enabled */
00341   }
00342
00343
00344   if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00345   {
00346     /* Enable ADC internal voltage regulator                                  */
00347     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
00348     /* Delay for ADC stabilization time                                       */
00349     /* Wait loop initialization and execution                                 */
00350     /* Note: Variable divided by 2 to compensate partially                    */
00351     /*       CPU processing cycles.                                           */
00352     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
00353     while(wait_loop_index != 0UL)
00354     {
00355       wait_loop_index--;
00356     }
00357   }
00358
00359
00360   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00361   /* or not ADC is coming from state reset (if any potential problem of       */
00362   /* clocking, voltage regulator would not be enabled).                       */
00363   if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00364   {
00365     /* Update ADC state machine to error */
00366     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00367
00368     /* Set ADC error code to ADC peripheral internal error */
00369     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00370
00371     return  HAL_ERROR;
00372   }
00373 /* Enable the ADC peripheral */
00374    if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)  /* Enable the ADC if it is disabled */
00375     {
00376     if (ADC_Enable(hadc) != HAL_OK)
00377     {
00378       return  HAL_ERROR;
00379     }
00380     else
00381     {
00382       for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
00383       {
00384         LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
00385       }
00386       (void)ADC_Disable(hadc);
00387     }
00388     }else /* ADC is already enabled, so no need to enable it but need to stop conversion */
00389     {
00390        if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
00391         {
00392           LL_ADC_REG_StopConversion(hadc->Instance);
00393           temp_REG_IsConversionOngoing = 1UL;
00394          }
00395        for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
00396          {
00397            LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
00398          }
00399        if(temp_REG_IsConversionOngoing != 0UL)
00400          {
00401            LL_ADC_REG_StartConversion(hadc->Instance);
00402          }
00403     }
00404   return HAL_OK;
00405 }
00406
00407 /**
00408   * @brief  Load the calibration factor from engi bytes
00409   * @param  hadc ADC handle
00410   * @retval HAL state
00411   */
00412 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc)
00413 {
00414   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00415   uint32_t cnt, FactorOffset;
00416   uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
00417
00418   /* Linearity calibration is retrieved from engi bytes
00419      read values from registers and put them to the CALFACT2 register */
00420   /* If needed linearity calibration can be done in runtime using
00421      LL_ADC_GetCalibrationLinearFactor()                             */
00422    if(hadc->Instance == ADC1)
00423    {
00424     FactorOffset = 0UL;
00425    }else if(hadc->Instance == ADC2)
00426    {
00427     FactorOffset = 8UL;
00428    }else  /*Case ADC3*/
00429     {
00430      FactorOffset = 16UL;
00431     }
00432
00433   for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
00434   {
00435     LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
00436   }
00437   if (HAL_ADCEx_LinearCalibration_SetValue(hadc,(uint32_t*)LinearCalib_Buffer) != HAL_OK)
00438   {
00439     tmp_hal_status = HAL_ERROR;
00440   }
00441
00442    return tmp_hal_status;
00443 }
00444
00445 /**
00446   * @brief  Enable ADC, start conversion of injected group.
00447   * @note   Interruptions enabled in this function: None.
00448   * @note   Case of multimode enabled when multimode feature is available:
00449   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
00450   *         then for ADC master.
00451   *         For ADC slave, ADC is enabled only (conversion is not started).
00452   *         For ADC master, ADC is enabled and multimode conversion is started.
00453   * @param hadc ADC handle.
00454   * @retval HAL status
00455   */
00456 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
00457 {
00458   HAL_StatusTypeDef tmp_hal_status;
00459   uint32_t tmp_config_injected_queue;
00460   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00461
00462   /* Check the parameters */
00463   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00464
00465   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00466   {
00467     return HAL_BUSY;
00468   }
00469   else
00470   {
00471     /* In case of software trigger detection enabled, JQDIS must be set
00472       (which can be done only if ADSTART and JADSTART are both cleared).
00473        If JQDIS is not set at that point, returns an error
00474        - since software trigger detection is disabled. User needs to
00475        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00476        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00477          the queue is empty */
00478     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00479
00480     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00481         && (tmp_config_injected_queue == 0UL)
00482        )
00483     {
00484       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00485       return HAL_ERROR;
00486     }
00487
00488     /* Process locked */
00489     __HAL_LOCK(hadc);
00490
00491     /* Enable the ADC peripheral */
00492     tmp_hal_status = ADC_Enable(hadc);
00493
00494     /* Start conversion if ADC is effectively enabled */
00495     if (tmp_hal_status == HAL_OK)
00496     {
00497       /* Check if a regular conversion is ongoing */
00498       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00499       {
00500         /* Reset ADC error code field related to injected conversions only */
00501         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00502       }
00503       else
00504       {
00505         /* Set ADC error code to none */
00506         ADC_CLEAR_ERRORCODE(hadc);
00507       }
00508
00509       /* Set ADC state                                                        */
00510       /* - Clear state bitfield related to injected group conversion results  */
00511       /* - Set state bitfield related to injected operation                   */
00512       ADC_STATE_CLR_SET(hadc->State,
00513                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00514                         HAL_ADC_STATE_INJ_BUSY);
00515
00516       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00517         - if ADC instance is master or if multimode feature is not available
00518         - if multimode setting is disabled (ADC instance slave in independent mode) */
00519       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00520           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00521          )
00522       {
00523         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00524       }
00525
00526       /* Clear ADC group injected group conversion flag */
00527       /* (To ensure of no unknown state from potential previous ADC operations) */
00528       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00529
00530       /* Process unlocked */
00531       /* Unlock before starting ADC conversions: in case of potential         */
00532       /* interruption, to let the process to ADC IRQ Handler.                 */
00533       __HAL_UNLOCK(hadc);
00534
00535       /* Enable conversion of injected group, if automatic injected conversion  */
00536       /* is disabled.                                                           */
00537       /* If software start has been selected, conversion starts immediately.    */
00538       /* If external trigger has been selected, conversion will start at next   */
00539       /* trigger event.                                                         */
00540       /* Case of multimode enabled (when multimode feature is available):       */
00541       /* if ADC is slave,                                                       */
00542       /*    - ADC is enabled only (conversion is not started),                  */
00543       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00544       /*     and conversion is started.                                         */
00545       /* If ADC is master or independent,                                       */
00546       /*    - ADC is enabled and conversion is started.                         */
00547       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00548           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00549           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00550           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00551          )
00552       {
00553         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00554         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00555         {
00556           LL_ADC_INJ_StartConversion(hadc->Instance);
00557         }
00558       }
00559       else
00560       {
00561         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00562         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00563       }
00564
00565     }
00566     else
00567     {
00568       /* Process unlocked */
00569       __HAL_UNLOCK(hadc);
00570     }
00571
00572     /* Return function status */
00573     return tmp_hal_status;
00574   }
00575 }
00576
00577 /**
00578   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00579   *         no regular conversion is on going.
00580   * @note   If ADC must be disabled and if conversion is on going on
00581   *         regular group, function HAL_ADC_Stop must be used to stop both
00582   *         injected and regular groups, and disable the ADC.
00583   * @note   If injected group mode auto-injection is enabled,
00584   *         function HAL_ADC_Stop must be used.
00585   * @note   In case of multimode enabled (when multimode feature is available),
00586   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
00587   *         For ADC master, conversion is stopped and ADC is disabled.
00588   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00589   *         has already stopped conversion of ADC slave).
00590   * @param hadc ADC handle.
00591   * @retval HAL status
00592   */
00593 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
00594 {
00595   HAL_StatusTypeDef tmp_hal_status;
00596
00597   /* Check the parameters */
00598   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00599
00600   /* Process locked */
00601   __HAL_LOCK(hadc);
00602
00603   /* 1. Stop potential conversion on going on injected group only. */
00604   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00605
00606   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00607   /* and if no conversion on regular group is on-going                       */
00608   if (tmp_hal_status == HAL_OK)
00609   {
00610     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00611     {
00612       /* 2. Disable the ADC peripheral */
00613       tmp_hal_status = ADC_Disable(hadc);
00614
00615       /* Check if ADC is effectively disabled */
00616       if (tmp_hal_status == HAL_OK)
00617       {
00618         /* Set ADC state */
00619         ADC_STATE_CLR_SET(hadc->State,
00620                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00621                           HAL_ADC_STATE_READY);
00622       }
00623     }
00624     /* Conversion on injected group is stopped, but ADC not disabled since    */
00625     /* conversion on regular group is still running.                          */
00626     else
00627     {
00628       /* Set ADC state */
00629       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00630     }
00631   }
00632
00633   /* Process unlocked */
00634   __HAL_UNLOCK(hadc);
00635
00636   /* Return function status */
00637   return tmp_hal_status;
00638 }
00639
00640 /**
00641   * @brief  Wait for injected group conversion to be completed.
00642   * @param hadc ADC handle
00643   * @param Timeout Timeout value in millisecond.
00644   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
00645   *         checked and cleared depending on AUTDLY bit status.
00646   * @retval HAL status
00647   */
00648 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
00649 {
00650   uint32_t tickstart;
00651   uint32_t tmp_Flag_End;
00652   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
00653   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
00654   uint32_t tmp_cfgr;
00655   const ADC_TypeDef *tmpADC_Master;
00656   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00657
00658   /* Check the parameters */
00659   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00660
00661   /* If end of sequence selected */
00662   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00663   {
00664     tmp_Flag_End = ADC_FLAG_JEOS;
00665   }
00666   else /* end of conversion selected */
00667   {
00668     tmp_Flag_End = ADC_FLAG_JEOC;
00669   }
00670
00671   /* Get timeout */
00672   tickstart = HAL_GetTick();
00673
00674   /* Wait until End of Conversion or Sequence flag is raised */
00675   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
00676   {
00677     /* Check if timeout is disabled (set to infinite wait) */
00678     if (Timeout != HAL_MAX_DELAY)
00679     {
00680       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
00681       {
00682         /* Update ADC state machine to timeout */
00683         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00684
00685         /* Process unlocked */
00686         __HAL_UNLOCK(hadc);
00687
00688         return HAL_TIMEOUT;
00689       }
00690     }
00691   }
00692
00693   /* Retrieve ADC configuration */
00694   tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
00695   tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
00696   /* Get relevant register CFGR in ADC instance of ADC master or slave  */
00697   /* in function of multimode state (for devices with multimode         */
00698   /* available).                                                        */
00699   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00700       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00701       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00702       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00703      )
00704   {
00705     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00706   }
00707   else
00708   {
00709     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
00710     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
00711   }
00712
00713   /* Update ADC state machine */
00714   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00715
00716   /* Determine whether any further conversion upcoming on group injected      */
00717   /* by external trigger or by automatic injected conversion                  */
00718   /* from group regular.                                                      */
00719   if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
00720       ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
00721        ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
00722         (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
00723   {
00724     /* Check whether end of sequence is reached */
00725     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
00726     {
00727       /* Particular case if injected contexts queue is enabled:             */
00728       /* when the last context has been fully processed, JSQR is reset      */
00729       /* by the hardware. Even if no injected conversion is planned to come */
00730       /* (queue empty, triggers are ignored), it can start again            */
00731       /* immediately after setting a new context (JADSTART is still set).   */
00732       /* Therefore, state of HAL ADC injected group is kept to busy.        */
00733       if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
00734       {
00735         /* Set ADC state */
00736         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00737
00738         if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
00739         {
00740           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00741         }
00742       }
00743     }
00744   }
00745
00746   /* Clear polled flag */
00747   if (tmp_Flag_End == ADC_FLAG_JEOS)
00748   {
00749     /* Clear end of sequence JEOS flag of injected group if low power feature */
00750     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00751     /* For injected groups, no new conversion will start before JEOS is       */
00752     /* cleared.                                                               */
00753     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
00754     {
00755       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00756     }
00757   }
00758   else
00759   {
00760     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00761   }
00762
00763   /* Return API HAL status */
00764   return HAL_OK;
00765 }
00766
00767 /**
00768   * @brief  Enable ADC, start conversion of injected group with interruption.
00769   * @note   Interruptions enabled in this function according to initialization
00770   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
00771   * @note   Case of multimode enabled (when multimode feature is enabled):
00772   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
00773   *         then for ADC master.
00774   *         For ADC slave, ADC is enabled only (conversion is not started).
00775   *         For ADC master, ADC is enabled and multimode conversion is started.
00776   * @param hadc ADC handle.
00777   * @retval HAL status.
00778   */
00779 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
00780 {
00781   HAL_StatusTypeDef tmp_hal_status;
00782   uint32_t tmp_config_injected_queue;
00783   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00784
00785   /* Check the parameters */
00786   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00787
00788   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00789   {
00790     return HAL_BUSY;
00791   }
00792   else
00793   {
00794     /* In case of software trigger detection enabled, JQDIS must be set
00795       (which can be done only if ADSTART and JADSTART are both cleared).
00796        If JQDIS is not set at that point, returns an error
00797        - since software trigger detection is disabled. User needs to
00798        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00799        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00800          the queue is empty */
00801     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00802
00803     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00804         && (tmp_config_injected_queue == 0UL)
00805        )
00806     {
00807       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00808       return HAL_ERROR;
00809     }
00810
00811     /* Process locked */
00812     __HAL_LOCK(hadc);
00813
00814     /* Enable the ADC peripheral */
00815     tmp_hal_status = ADC_Enable(hadc);
00816
00817     /* Start conversion if ADC is effectively enabled */
00818     if (tmp_hal_status == HAL_OK)
00819     {
00820       /* Check if a regular conversion is ongoing */
00821       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00822       {
00823         /* Reset ADC error code field related to injected conversions only */
00824         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00825       }
00826       else
00827       {
00828         /* Set ADC error code to none */
00829         ADC_CLEAR_ERRORCODE(hadc);
00830       }
00831
00832       /* Set ADC state                                                        */
00833       /* - Clear state bitfield related to injected group conversion results  */
00834       /* - Set state bitfield related to injected operation                   */
00835       ADC_STATE_CLR_SET(hadc->State,
00836                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00837                         HAL_ADC_STATE_INJ_BUSY);
00838
00839       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00840         - if ADC instance is master or if multimode feature is not available
00841         - if multimode setting is disabled (ADC instance slave in independent mode) */
00842       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00843           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00844          )
00845       {
00846         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00847       }
00848
00849       /* Clear ADC group injected group conversion flag */
00850       /* (To ensure of no unknown state from potential previous ADC operations) */
00851       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00852
00853       /* Process unlocked */
00854       /* Unlock before starting ADC conversions: in case of potential         */
00855       /* interruption, to let the process to ADC IRQ Handler.                 */
00856       __HAL_UNLOCK(hadc);
00857
00858       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00859       /* is enabled.                                                            */
00860       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
00861       {
00862         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00863       }
00864
00865       /* Enable ADC end of conversion interrupt */
00866       switch (hadc->Init.EOCSelection)
00867       {
00868         case ADC_EOC_SEQ_CONV:
00869           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00870           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00871           break;
00872         /* case ADC_EOC_SINGLE_CONV */
00873         default:
00874           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
00875           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00876           break;
00877       }
00878
00879       /* Enable conversion of injected group, if automatic injected conversion  */
00880       /* is disabled.                                                           */
00881       /* If software start has been selected, conversion starts immediately.    */
00882       /* If external trigger has been selected, conversion will start at next   */
00883       /* trigger event.                                                         */
00884       /* Case of multimode enabled (when multimode feature is available):       */
00885       /* if ADC is slave,                                                       */
00886       /*    - ADC is enabled only (conversion is not started),                  */
00887       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00888       /*     and conversion is started.                                         */
00889       /* If ADC is master or independent,                                       */
00890       /*    - ADC is enabled and conversion is started.                         */
00891       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00892           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00893           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00894           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00895          )
00896       {
00897         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00898         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00899         {
00900           LL_ADC_INJ_StartConversion(hadc->Instance);
00901         }
00902       }
00903       else
00904       {
00905         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00906         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00907       }
00908
00909     }
00910     else
00911     {
00912       /* Process unlocked */
00913       __HAL_UNLOCK(hadc);
00914     }
00915
00916     /* Return function status */
00917     return tmp_hal_status;
00918   }
00919 }
00920
00921 /**
00922   * @brief  Stop conversion of injected channels, disable interruption of
00923   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00924   *         is on going.
00925   * @note   If ADC must be disabled and if conversion is on going on
00926   *         regular group, function HAL_ADC_Stop must be used to stop both
00927   *         injected and regular groups, and disable the ADC.
00928   * @note   If injected group mode auto-injection is enabled,
00929   *         function HAL_ADC_Stop must be used.
00930   * @note   Case of multimode enabled (when multimode feature is available):
00931   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
00932   *         then for ADC slave.
00933   *         For ADC master, conversion is stopped and ADC is disabled.
00934   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00935   *         has already stopped conversion of ADC slave).
00936   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00937   * @param hadc ADC handle
00938   * @retval HAL status
00939   */
00940 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
00941 {
00942   HAL_StatusTypeDef tmp_hal_status;
00943
00944   /* Check the parameters */
00945   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00946
00947   /* Process locked */
00948   __HAL_LOCK(hadc);
00949
00950   /* 1. Stop potential conversion on going on injected group only. */
00951   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00952
00953   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00954   /* and if no conversion on the other group (regular group) is intended to   */
00955   /* continue.                                                                */
00956   if (tmp_hal_status == HAL_OK)
00957   {
00958     /* Disable ADC end of conversion interrupt for injected channels */
00959     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00960
00961     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00962     {
00963       /* 2. Disable the ADC peripheral */
00964       tmp_hal_status = ADC_Disable(hadc);
00965
00966       /* Check if ADC is effectively disabled */
00967       if (tmp_hal_status == HAL_OK)
00968       {
00969         /* Set ADC state */
00970         ADC_STATE_CLR_SET(hadc->State,
00971                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00972                           HAL_ADC_STATE_READY);
00973       }
00974     }
00975     /* Conversion on injected group is stopped, but ADC not disabled since    */
00976     /* conversion on regular group is still running.                          */
00977     else
00978     {
00979       /* Set ADC state */
00980       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00981     }
00982   }
00983
00984   /* Process unlocked */
00985   __HAL_UNLOCK(hadc);
00986
00987   /* Return function status */
00988   return tmp_hal_status;
00989 }
00990
00991 /**
00992   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
00993   * @note   Multimode must have been previously configured using
00994   *         HAL_ADCEx_MultiModeConfigChannel() function.
00995   *         Interruptions enabled in this function:
00996   *          overrun, DMA half transfer, DMA transfer complete.
00997   *         Each of these interruptions has its dedicated callback function.
00998   * @note   State field of Slave ADC handle is not updated in this configuration:
00999   *          user should not rely on it for information related to Slave regular
01000   *         conversions.
01001   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
01002   * @param pData Destination Buffer address.
01003   * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
01004   * @retval HAL status
01005   */
01006 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
01007 {
01008   HAL_StatusTypeDef tmp_hal_status;
01009   ADC_HandleTypeDef tmphadcSlave;
01010   ADC_Common_TypeDef *tmpADC_Common;
01011
01012   /* Check the parameters */
01013   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01014   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
01015   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
01016
01017   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
01018   {
01019     return HAL_BUSY;
01020   }
01021   else
01022   {
01023     /* Process locked */
01024     __HAL_LOCK(hadc);
01025
01026     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01027     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01028
01029     if (tmphadcSlave.Instance == NULL)
01030     {
01031       /* Set ADC state */
01032       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01033
01034       /* Process unlocked */
01035       __HAL_UNLOCK(hadc);
01036
01037       return HAL_ERROR;
01038     }
01039
01040     /* Enable the ADC peripherals: master and slave (in case if not already   */
01041     /* enabled previously)                                                    */
01042     tmp_hal_status = ADC_Enable(hadc);
01043     if (tmp_hal_status == HAL_OK)
01044     {
01045       tmp_hal_status = ADC_Enable(&tmphadcSlave);
01046     }
01047
01048     /* Start multimode conversion of ADCs pair */
01049     if (tmp_hal_status == HAL_OK)
01050     {
01051       /* Set ADC state */
01052       ADC_STATE_CLR_SET(hadc->State,
01053                         (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
01054                         HAL_ADC_STATE_REG_BUSY);
01055
01056       /* Set ADC error code to none */
01057       ADC_CLEAR_ERRORCODE(hadc);
01058
01059       /* Set the DMA transfer complete callback */
01060       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01061
01062       /* Set the DMA half transfer complete callback */
01063       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01064
01065       /* Set the DMA error callback */
01066       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
01067
01068       /* Pointer to the common control register  */
01069       tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
01070
01071       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01072       /* start (in case of SW start):                                           */
01073
01074       /* Clear regular group conversion flag and overrun flag */
01075       /* (To ensure of no unknown state from potential previous ADC operations) */
01076       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01077
01078       /* Process unlocked */
01079       /* Unlock before starting ADC conversions: in case of potential         */
01080       /* interruption, to let the process to ADC IRQ Handler.                 */
01081       __HAL_UNLOCK(hadc);
01082
01083       /* Enable ADC overrun interrupt */
01084       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01085
01086       /* Start the DMA channel */
01087       tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
01088
01089       /* Enable conversion of regular group.                                    */
01090       /* If software start has been selected, conversion starts immediately.    */
01091       /* If external trigger has been selected, conversion will start at next   */
01092       /* trigger event.                                                         */
01093       /* Start ADC group regular conversion */
01094       LL_ADC_REG_StartConversion(hadc->Instance);
01095     }
01096     else
01097     {
01098       /* Process unlocked */
01099       __HAL_UNLOCK(hadc);
01100     }
01101
01102     /* Return function status */
01103     return tmp_hal_status;
01104   }
01105 }
01106
01107 /**
01108   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
01109   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
01110   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01111   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01112   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01113   *         resort to HAL_ADCEx_DisableMultiMode() API.
01114   * @note   In case of DMA configured in circular mode, function
01115   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
01116   *         ADC slave, to properly disable the DMA channel.
01117   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
01118   * @retval HAL status
01119   */
01120 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
01121 {
01122   HAL_StatusTypeDef tmp_hal_status;
01123   uint32_t tickstart;
01124   ADC_HandleTypeDef tmphadcSlave;
01125   uint32_t tmphadcSlave_conversion_on_going;
01126   HAL_StatusTypeDef tmphadcSlave_disable_status;
01127
01128   /* Check the parameters */
01129   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01130
01131   /* Process locked */
01132   __HAL_LOCK(hadc);
01133
01134
01135   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
01136   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01137
01138   /* Disable ADC peripheral if conversions are effectively stopped */
01139   if (tmp_hal_status == HAL_OK)
01140   {
01141     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01142     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01143
01144     if (tmphadcSlave.Instance == NULL)
01145     {
01146       /* Update ADC state machine to error */
01147       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01148
01149       /* Process unlocked */
01150       __HAL_UNLOCK(hadc);
01151
01152       return HAL_ERROR;
01153     }
01154
01155     /* Procedure to disable the ADC peripheral: wait for conversions          */
01156     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01157
01158     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
01159     tickstart = HAL_GetTick();
01160
01161     tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
01162     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01163            || (tmphadcSlave_conversion_on_going == 1UL)
01164           )
01165     {
01166       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01167       {
01168         /* Update ADC state machine to error */
01169         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01170
01171         /* Process unlocked */
01172         __HAL_UNLOCK(hadc);
01173
01174         return HAL_ERROR;
01175       }
01176
01177       tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
01178     }
01179
01180     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01181     /* while DMA transfer is on going)                                        */
01182     /* Note: DMA channel of ADC slave should be stopped after this function   */
01183     /*       with HAL_ADC_Stop_DMA() API.                                     */
01184     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01185
01186     /* Check if DMA channel effectively disabled */
01187     if (tmp_hal_status == HAL_ERROR)
01188     {
01189       /* Update ADC state machine to error */
01190       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01191     }
01192
01193     /* Disable ADC overrun interrupt */
01194     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01195
01196     /* 2. Disable the ADC peripherals: master and slave */
01197     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
01198     /* memory a potential failing status.                                     */
01199     if (tmp_hal_status == HAL_OK)
01200     {
01201       tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
01202       if ((ADC_Disable(hadc) == HAL_OK)           &&
01203           (tmphadcSlave_disable_status == HAL_OK))
01204       {
01205         tmp_hal_status = HAL_OK;
01206       }
01207     }
01208     else
01209     {
01210       /* In case of error, attempt to disable ADC master and slave without status assert */
01211       (void) ADC_Disable(hadc);
01212       (void) ADC_Disable(&tmphadcSlave);
01213     }
01214
01215     /* Set ADC state (ADC master) */
01216     ADC_STATE_CLR_SET(hadc->State,
01217                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01218                       HAL_ADC_STATE_READY);
01219   }
01220
01221   /* Process unlocked */
01222   __HAL_UNLOCK(hadc);
01223
01224   /* Return function status */
01225   return tmp_hal_status;
01226 }
01227
01228 /**
01229   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
01230   * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
01231   * @retval The converted data values.
01232   */
01233 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
01234 {
01235   const ADC_Common_TypeDef *tmpADC_Common;
01236
01237   /* Check the parameters */
01238   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01239
01240   /* Prevent unused argument(s) compilation warning if no assert_param check */
01241   /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
01242   UNUSED(hadc);
01243
01244   /* Pointer to the common control register  */
01245   tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
01246
01247   /* Return the multi mode conversion value */
01248   return tmpADC_Common->CDR;
01249 }
01250
01251 /**
01252   * @brief  Get ADC injected group conversion result.
01253   * @note   Reading register JDRx automatically clears ADC flag JEOC
01254   *         (ADC group injected end of unitary conversion).
01255   * @note   This function does not clear ADC flag JEOS
01256   *         (ADC group injected end of sequence conversion)
01257   *         Occurrence of flag JEOS rising:
01258   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
01259   *            to flag JEOC.
01260   *          - If sequencer is composed of several ranks, during the scan
01261   *            sequence flag JEOC only is raised, at the end of the scan sequence
01262   *            both flags JEOC and EOS are raised.
01263   *         Flag JEOS must not be cleared by this function because
01264   *         it would not be compliant with low power features
01265   *         (feature low power auto-wait, not available on all STM32 families).
01266   *         To clear this flag, either use function:
01267   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01268   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
01269   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
01270   * @param hadc ADC handle
01271   * @param InjectedRank the converted ADC injected rank.
01272   *          This parameter can be one of the following values:
01273   *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
01274   *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
01275   *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
01276   *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
01277   * @retval ADC group injected conversion data
01278   */
01279 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
01280 {
01281   uint32_t tmp_jdr;
01282
01283   /* Check the parameters */
01284   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01285   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
01286
01287   /* Get ADC converted value */
01288   switch (InjectedRank)
01289   {
01290     case ADC_INJECTED_RANK_4:
01291       tmp_jdr = hadc->Instance->JDR4;
01292       break;
01293     case ADC_INJECTED_RANK_3:
01294       tmp_jdr = hadc->Instance->JDR3;
01295       break;
01296     case ADC_INJECTED_RANK_2:
01297       tmp_jdr = hadc->Instance->JDR2;
01298       break;
01299     case ADC_INJECTED_RANK_1:
01300     default:
01301       tmp_jdr = hadc->Instance->JDR1;
01302       break;
01303   }
01304
01305   /* Return ADC converted value */
01306   return tmp_jdr;
01307 }
01308
01309 /**
01310   * @brief  Injected conversion complete callback in non-blocking mode.
01311   * @param hadc ADC handle
01312   * @retval None
01313   */
01314 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
01315 {
01316   /* Prevent unused argument(s) compilation warning */
01317   UNUSED(hadc);
01318
01319   /* NOTE : This function should not be modified. When the callback is needed,
01320             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
01321   */
01322 }
01323
01324 /**
01325   * @brief  Injected context queue overflow callback.
01326   * @note   This callback is called if injected context queue is enabled
01327             (parameter "QueueInjectedContext" in injected channel configuration)
01328             and if a new injected context is set when queue is full (maximum 2
01329             contexts).
01330   * @param hadc ADC handle
01331   * @retval None
01332   */
01333 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
01334 {
01335   /* Prevent unused argument(s) compilation warning */
01336   UNUSED(hadc);
01337
01338   /* NOTE : This function should not be modified. When the callback is needed,
01339             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
01340   */
01341 }
01342
01343 /**
01344   * @brief  Analog watchdog 2 callback in non-blocking mode.
01345   * @param hadc ADC handle
01346   * @retval None
01347   */
01348 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
01349 {
01350   /* Prevent unused argument(s) compilation warning */
01351   UNUSED(hadc);
01352
01353   /* NOTE : This function should not be modified. When the callback is needed,
01354             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
01355   */
01356 }
01357
01358 /**
01359   * @brief  Analog watchdog 3 callback in non-blocking mode.
01360   * @param hadc ADC handle
01361   * @retval None
01362   */
01363 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
01364 {
01365   /* Prevent unused argument(s) compilation warning */
01366   UNUSED(hadc);
01367
01368   /* NOTE : This function should not be modified. When the callback is needed,
01369             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
01370   */
01371 }
01372
01373
01374 /**
01375   * @brief  End Of Sampling callback in non-blocking mode.
01376   * @param hadc ADC handle
01377   * @retval None
01378   */
01379 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
01380 {
01381   /* Prevent unused argument(s) compilation warning */
01382   UNUSED(hadc);
01383
01384   /* NOTE : This function should not be modified. When the callback is needed,
01385             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
01386   */
01387 }
01388
01389 /**
01390   * @brief  Stop ADC conversion of regular group (and injected channels in
01391   *         case of auto_injection mode), disable ADC peripheral if no
01392   *         conversion is on going on injected group.
01393   * @param hadc ADC handle
01394   * @retval HAL status.
01395   */
01396 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
01397 {
01398   HAL_StatusTypeDef tmp_hal_status;
01399
01400   /* Check the parameters */
01401   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01402
01403   /* Process locked */
01404   __HAL_LOCK(hadc);
01405
01406   /* 1. Stop potential regular conversion on going */
01407   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01408
01409   /* Disable ADC peripheral if regular conversions are effectively stopped
01410      and if no injected conversions are on-going */
01411   if (tmp_hal_status == HAL_OK)
01412   {
01413     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01414     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01415
01416     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01417     {
01418       /* 2. Disable the ADC peripheral */
01419       tmp_hal_status = ADC_Disable(hadc);
01420
01421       /* Check if ADC is effectively disabled */
01422       if (tmp_hal_status == HAL_OK)
01423       {
01424         /* Set ADC state */
01425         ADC_STATE_CLR_SET(hadc->State,
01426                           HAL_ADC_STATE_INJ_BUSY,
01427                           HAL_ADC_STATE_READY);
01428       }
01429     }
01430     /* Conversion on injected group is stopped, but ADC not disabled since    */
01431     /* conversion on regular group is still running.                          */
01432     else
01433     {
01434       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01435     }
01436   }
01437
01438   /* Process unlocked */
01439   __HAL_UNLOCK(hadc);
01440
01441   /* Return function status */
01442   return tmp_hal_status;
01443 }
01444
01445
01446 /**
01447   * @brief  Stop ADC conversion of ADC groups regular and injected,
01448   *         disable interrution of end-of-conversion,
01449   *         disable ADC peripheral if no conversion is on going
01450   *         on injected group.
01451   * @param hadc ADC handle
01452   * @retval HAL status.
01453   */
01454 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
01455 {
01456   HAL_StatusTypeDef tmp_hal_status;
01457
01458   /* Check the parameters */
01459   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01460
01461   /* Process locked */
01462   __HAL_LOCK(hadc);
01463
01464   /* 1. Stop potential regular conversion on going */
01465   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01466
01467   /* Disable ADC peripheral if conversions are effectively stopped
01468     and if no injected conversion is on-going */
01469   if (tmp_hal_status == HAL_OK)
01470   {
01471     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01472     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01473
01474     /* Disable all regular-related interrupts */
01475     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01476
01477     /* 2. Disable ADC peripheral if no injected conversions are on-going */
01478     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01479     {
01480       tmp_hal_status = ADC_Disable(hadc);
01481       /* if no issue reported */
01482       if (tmp_hal_status == HAL_OK)
01483       {
01484         /* Set ADC state */
01485         ADC_STATE_CLR_SET(hadc->State,
01486                           HAL_ADC_STATE_INJ_BUSY,
01487                           HAL_ADC_STATE_READY);
01488       }
01489     }
01490     else
01491     {
01492       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01493     }
01494   }
01495
01496   /* Process unlocked */
01497   __HAL_UNLOCK(hadc);
01498
01499   /* Return function status */
01500   return tmp_hal_status;
01501 }
01502
01503 /**
01504   * @brief  Stop ADC conversion of regular group (and injected group in
01505   *         case of auto_injection mode), disable ADC DMA transfer, disable
01506   *         ADC peripheral if no conversion is on going
01507   *         on injected group.
01508   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
01509   *         For multimode (when multimode feature is available),
01510   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
01511   * @param hadc ADC handle
01512   * @retval HAL status.
01513   */
01514 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
01515 {
01516   HAL_StatusTypeDef tmp_hal_status;
01517
01518   /* Check the parameters */
01519   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01520
01521   /* Process locked */
01522   __HAL_LOCK(hadc);
01523
01524   /* 1. Stop potential regular conversion on going */
01525   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01526
01527   /* Disable ADC peripheral if conversions are effectively stopped
01528      and if no injected conversion is on-going */
01529   if (tmp_hal_status == HAL_OK)
01530   {
01531     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01532     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01533
01534   /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01535     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
01536
01537     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01538     /* while DMA transfer is on going)                                        */
01539     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01540
01541     /* Check if DMA channel effectively disabled */
01542     if (tmp_hal_status != HAL_OK)
01543     {
01544       /* Update ADC state machine to error */
01545       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01546     }
01547
01548     /* Disable ADC overrun interrupt */
01549     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01550
01551     /* 2. Disable the ADC peripheral */
01552     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
01553     /* to keep in memory a potential failing status.                          */
01554     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01555     {
01556       if (tmp_hal_status == HAL_OK)
01557       {
01558         tmp_hal_status = ADC_Disable(hadc);
01559       }
01560       else
01561       {
01562         (void)ADC_Disable(hadc);
01563       }
01564
01565       /* Check if ADC is effectively disabled */
01566       if (tmp_hal_status == HAL_OK)
01567       {
01568         /* Set ADC state */
01569         ADC_STATE_CLR_SET(hadc->State,
01570                           HAL_ADC_STATE_INJ_BUSY,
01571                           HAL_ADC_STATE_READY);
01572       }
01573     }
01574     else
01575     {
01576       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01577     }
01578   }
01579
01580   /* Process unlocked */
01581   __HAL_UNLOCK(hadc);
01582
01583   /* Return function status */
01584   return tmp_hal_status;
01585 }
01586
01587 /**
01588   * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01589   * @note   Multimode is kept enabled after this function. Multimode DMA bits
01590   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01591   *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01592   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01593   *         resort to HAL_ADCEx_DisableMultiMode() API.
01594   * @note   In case of DMA configured in circular mode, function
01595   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
01596   *         ADC slave, to properly disable the DMA channel.
01597   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
01598   * @retval HAL status
01599   */
01600 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
01601 {
01602   HAL_StatusTypeDef tmp_hal_status;
01603   uint32_t tickstart;
01604   ADC_HandleTypeDef tmphadcSlave;
01605   uint32_t tmphadcSlave_conversion_on_going;
01606
01607   /* Check the parameters */
01608   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01609
01610   /* Process locked */
01611   __HAL_LOCK(hadc);
01612
01613
01614   /* 1. Stop potential multimode conversion on going, on regular groups */
01615   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01616
01617   /* Disable ADC peripheral if conversions are effectively stopped */
01618   if (tmp_hal_status == HAL_OK)
01619   {
01620     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01621     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01622
01623     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01624     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01625
01626     if (tmphadcSlave.Instance == NULL)
01627     {
01628       /* Update ADC state machine to error */
01629       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01630
01631       /* Process unlocked */
01632       __HAL_UNLOCK(hadc);
01633
01634       return HAL_ERROR;
01635     }
01636
01637     /* Procedure to disable the ADC peripheral: wait for conversions          */
01638     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01639
01640     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
01641     tickstart = HAL_GetTick();
01642
01643     tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
01644     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01645            || (tmphadcSlave_conversion_on_going == 1UL)
01646           )
01647     {
01648       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01649       {
01650         /* Update ADC state machine to error */
01651         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01652
01653         /* Process unlocked */
01654         __HAL_UNLOCK(hadc);
01655
01656         return HAL_ERROR;
01657       }
01658
01659       tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
01660     }
01661
01662     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01663     /* while DMA transfer is on going)                                        */
01664     /* Note: DMA channel of ADC slave should be stopped after this function   */
01665     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
01666     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01667
01668     /* Check if DMA channel effectively disabled */
01669     if (tmp_hal_status != HAL_OK)
01670     {
01671       /* Update ADC state machine to error */
01672       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01673     }
01674
01675     /* Disable ADC overrun interrupt */
01676     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01677
01678     /* 2. Disable the ADC peripherals: master and slave if no injected        */
01679     /*   conversion is on-going.                                              */
01680     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
01681     /* memory a potential failing status.                                     */
01682     if (tmp_hal_status == HAL_OK)
01683     {
01684       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01685       {
01686         tmp_hal_status =  ADC_Disable(hadc);
01687         if (tmp_hal_status == HAL_OK)
01688         {
01689           if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
01690           {
01691             tmp_hal_status =  ADC_Disable(&tmphadcSlave);
01692           }
01693         }
01694       }
01695
01696       if (tmp_hal_status == HAL_OK)
01697       {
01698         /* Both Master and Slave ADC's could be disabled. Update Master State */
01699         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01700         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01701       }
01702       else
01703       {
01704         /* injected (Master or Slave) conversions are still on-going,
01705            no Master State change */
01706       }
01707     }
01708   }
01709
01710   /* Process unlocked */
01711   __HAL_UNLOCK(hadc);
01712
01713   /* Return function status */
01714   return tmp_hal_status;
01715 }
01716
01717 /**
01718   * @}
01719   */
01720
01721 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
01722   * @brief    ADC Extended Peripheral Control functions
01723   *
01724 @verbatim
01725  ===============================================================================
01726              ##### Peripheral Control functions #####
01727  ===============================================================================
01728     [..]  This section provides functions allowing to:
01729       (+) Configure channels on injected group
01730       (+) Configure multimode when multimode feature is available
01731       (+) Enable or Disable Injected Queue
01732       (+) Disable ADC voltage regulator
01733       (+) Enter ADC deep-power-down mode
01734
01735 @endverbatim
01736   * @{
01737   */
01738
01739 /**
01740   * @brief  Configure a channel to be assigned to ADC group injected.
01741   * @note   Possibility to update parameters on the fly:
01742   *         This function initializes injected group, following calls to this
01743   *         function can be used to reconfigure some parameters of structure
01744   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01745   *         The setting of these parameters is conditioned to ADC state:
01746   *         Refer to comments of structure "ADC_InjectionConfTypeDef".
01747   * @note   In case of usage of internal measurement channels:
01748   *         Vbat/VrefInt/TempSensor.
01749   *         These internal paths can be disabled using function
01750   *         HAL_ADC_DeInit().
01751   * @note   Caution: For Injected Context Queue use, a context must be fully
01752   *         defined before start of injected conversion. All channels are configured
01753   *         consecutively for the same ADC instance. Therefore, the number of calls to
01754   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
01755   *         InjectedNbrOfConversion for each context.
01756   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
01757   *    Injected Queue Context feature) and if the context contains 3 injected ranks
01758   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
01759   *    called once for each channel (i.e. 3 times) before starting a conversion.
01760   *    This function must not be called to configure a 4th injected channel:
01761   *    it would start a new context into context queue.
01762   *  - Example 2: If 2 contexts are intended to be used and each of them contains
01763   *    3 injected ranks (InjectedNbrOfConversion = 3),
01764   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
01765   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
01766   *    start once the 1st context is set, that is after the first three
01767   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01768   * @param hadc ADC handle
01769   * @param sConfigInjected Structure of ADC injected group and ADC channel for
01770   *         injected group.
01771   * @retval HAL status
01772   */
01773 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
01774 {
01775   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01776   uint32_t tmpOffsetShifted;
01777   uint32_t tmp_config_internal_channel;
01778   uint32_t tmp_adc_is_conversion_on_going_regular;
01779   uint32_t tmp_adc_is_conversion_on_going_injected;
01780   __IO uint32_t wait_loop_index = 0;
01781
01782   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
01783
01784   /* Check the parameters */
01785   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01786   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01787   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
01788   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01789   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
01790   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
01791   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
01792   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
01793   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01794   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
01795
01796   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01797   {
01798     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01799     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01800     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01801   }
01802
01803   /* Check offset range according to oversampling setting */
01804   if (hadc->Init.OversamplingMode == ENABLE)
01805   {
01806     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U)));
01807   }
01808   else
01809   {
01810     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01811   }
01812
01813   /* JDISCEN and JAUTO bits can't be set at the same time  */
01814   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01815
01816   /*  DISCEN and JAUTO bits can't be set at the same time */
01817   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01818
01819   /* Verification of channel number */
01820   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01821   {
01822     assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
01823   }
01824   else
01825   {
01826     if (hadc->Instance == ADC1)
01827     {
01828       assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01829     }
01830     if (hadc->Instance == ADC2)
01831     {
01832       assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01833     }
01834 #if defined (ADC3)
01835     if (hadc->Instance == ADC3)
01836     {
01837       assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01838     }
01839 #endif
01840   }
01841
01842   /* Process locked */
01843   __HAL_LOCK(hadc);
01844
01845   /* Configuration of injected group sequencer:                               */
01846   /* Hardware constraint: Must fully define injected context register JSQR    */
01847   /* before make it entering into injected sequencer queue.                   */
01848   /*                                                                          */
01849   /* - if scan mode is disabled:                                              */
01850   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01851   /*      converted (channel on injected rank 1)                              */
01852   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01853   /*    * Injected context register JSQR setting is simple: register is fully */
01854   /*      defined on one call of this function (for injected rank 1) and can  */
01855   /*      be entered into queue directly.                                     */
01856   /* - if scan mode is enabled:                                               */
01857   /*    * Injected channels sequence length is set to parameter               */
01858   /*      "InjectedNbrOfConversion".                                          */
01859   /*    * Injected context register JSQR setting more complex: register is    */
01860   /*      fully defined over successive calls of this function, for each      */
01861   /*      injected channel rank. It is entered into queue only when all       */
01862   /*      injected ranks have been set.                                       */
01863   /*   Note: Scan mode is not present by hardware on this device, but used    */
01864   /*   by software for alignment over all STM32 devices.                      */
01865
01866   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01867       (sConfigInjected->InjectedNbrOfConversion == 1U))
01868   {
01869     /* Configuration of context register JSQR:                                */
01870     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01871     /*    (scan mode disabled, only rank 1 used)                              */
01872     /*  - external trigger to start conversion                                */
01873     /*  - external trigger polarity                                           */
01874     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01875
01876     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01877     {
01878       /* Enable external trigger if trigger selection is different of         */
01879       /* software start.                                                      */
01880       /* Note: This configuration keeps the hardware feature of parameter     */
01881       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01882       /*       software start.                                                */
01883       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01884       {
01885         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
01886                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01887                                            | sConfigInjected->ExternalTrigInjecConvEdge
01888                                           );
01889       }
01890       else
01891       {
01892         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
01893       }
01894
01895       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
01896       /* For debug and informative reasons, hadc handle saves JSQR setting */
01897       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
01898
01899     }
01900   }
01901   else
01902   {
01903     /* Case of scan mode enabled, several channels to set into injected group */
01904     /* sequencer.                                                             */
01905     /*                                                                        */
01906     /* Procedure to define injected context register JSQR over successive     */
01907     /* calls of this function, for each injected channel rank:                */
01908     /* 1. Start new context and set parameters related to all injected        */
01909     /*    channels: injected sequence length and trigger.                     */
01910
01911     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01912     /*   call of the context under setting                                    */
01913     if (hadc->InjectionConfig.ChannelCount == 0U)
01914     {
01915       /* Initialize number of channels that will be configured on the context */
01916       /*  being built                                                         */
01917       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
01918       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01919          call, this context will be written in JSQR register at the last call.
01920          At this point, the context is merely reset  */
01921       hadc->InjectionConfig.ContextQueue = 0x00000000U;
01922
01923       /* Configuration of context register JSQR:                              */
01924       /*  - number of ranks in injected group sequencer                       */
01925       /*  - external trigger to start conversion                              */
01926       /*  - external trigger polarity                                         */
01927
01928       /* Enable external trigger if trigger selection is different of         */
01929       /* software start.                                                      */
01930       /* Note: This configuration keeps the hardware feature of parameter     */
01931       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01932       /*       software start.                                                */
01933       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01934       {
01935         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
01936                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01937                                            | sConfigInjected->ExternalTrigInjecConvEdge
01938                                           );
01939       }
01940       else
01941       {
01942         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
01943       }
01944
01945     }
01946
01947     /* 2. Continue setting of context under definition with parameter       */
01948     /*    related to each channel: channel rank sequence                    */
01949     /* Clear the old JSQx bits for the selected rank */
01950     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
01951
01952     /* Set the JSQx bits for the selected rank */
01953     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
01954
01955     /* Decrease channel count  */
01956     hadc->InjectionConfig.ChannelCount--;
01957
01958     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
01959           call, aggregate the setting to those already built during the previous
01960           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01961     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
01962
01963     /* 4. End of context setting: if this is the last channel set, then write context
01964         into register JSQR and make it enter into queue                   */
01965     if (hadc->InjectionConfig.ChannelCount == 0U)
01966     {
01967       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
01968     }
01969   }
01970
01971   /* Parameters update conditioned to ADC state:                              */
01972   /* Parameters that can be updated when ADC is disabled or enabled without   */
01973   /* conversion on going on injected group:                                   */
01974   /*  - Injected context queue: Queue disable (active context is kept) or     */
01975   /*    enable (context decremented, up to 2 contexts queued)                 */
01976   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01977   /*    mode is disabled.                                                     */
01978   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01979   {
01980   /* ADC channels preselection */
01981     hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
01982
01983     /* If auto-injected mode is disabled: no constraint                       */
01984     if (sConfigInjected->AutoInjectedConv == DISABLE)
01985     {
01986       MODIFY_REG(hadc->Instance->CFGR,
01987                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01988                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)           |
01989                  ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
01990     }
01991     /* If auto-injected mode is enabled: Injected discontinuous setting is    */
01992     /* discarded.                                                             */
01993     else
01994     {
01995       MODIFY_REG(hadc->Instance->CFGR,
01996                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01997                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
01998     }
01999
02000   }
02001
02002   /* Parameters update conditioned to ADC state:                              */
02003   /* Parameters that can be updated when ADC is disabled or enabled without   */
02004   /* conversion on going on regular and injected groups:                      */
02005   /*  - Automatic injected conversion: can be enabled if injected group       */
02006   /*    external triggers are disabled.                                       */
02007   /*  - Channel sampling time                                                 */
02008   /*  - Channel offset                                                        */
02009   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02010   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02011
02012   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02013       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02014      )
02015   {
02016     /* If injected group external triggers are disabled (set to injected      */
02017     /* software start): no constraint                                         */
02018     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
02019         || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
02020     {
02021       if (sConfigInjected->AutoInjectedConv == ENABLE)
02022       {
02023         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02024       }
02025       else
02026       {
02027         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02028       }
02029     }
02030     /* If Automatic injected conversion was intended to be set and could not  */
02031     /* due to injected group external triggers enabled, error is reported.    */
02032     else
02033     {
02034       if (sConfigInjected->AutoInjectedConv == ENABLE)
02035       {
02036         /* Update ADC state machine to error */
02037         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02038
02039         tmp_hal_status = HAL_ERROR;
02040       }
02041       else
02042       {
02043         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02044       }
02045     }
02046
02047     if (sConfigInjected->InjecOversamplingMode == ENABLE)
02048     {
02049       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
02050       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
02051
02052       /*  JOVSE must be reset in case of triggered regular mode  */
02053       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
02054
02055       /* Configuration of Injected Oversampler:                                 */
02056       /*  - Oversampling Ratio                                                  */
02057       /*  - Right bit shift                                                     */
02058
02059       /* Enable OverSampling mode */
02060       MODIFY_REG(hadc->Instance->CFGR2,
02061                  ADC_CFGR2_JOVSE |
02062                  ADC_CFGR2_OVSR  |
02063                  ADC_CFGR2_OVSS,
02064                  ADC_CFGR2_JOVSE                                                          |
02065                  ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
02066                  sConfigInjected->InjecOversampling.RightBitShift
02067                 );
02068     }
02069     else
02070     {
02071       /* Disable Regular OverSampling */
02072       CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
02073     }
02074
02075       /* Set sampling time of the selected ADC channel */
02076       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
02077
02078     /* Configure the offset: offset enable/disable, channel, offset value */
02079
02080     /* Shift the offset with respect to the selected ADC resolution. */
02081     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02082     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
02083
02084     if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
02085     {
02086       /* Set ADC selected offset number */
02087       LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
02088                        tmpOffsetShifted);
02089
02090       /* Set ADC selected offset signed saturation */
02091       LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02092
02093       /* Set ADC selected offset right shift */
02094       LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
02095
02096     }
02097     else
02098     {
02099       /* Scan each offset register to check if the selected channel is targeted. */
02100       /* If this is the case, the corresponding offset number is disabled.       */
02101       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
02102       {
02103         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02104       }
02105       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
02106       {
02107         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02108       }
02109       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
02110       {
02111         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02112       }
02113       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
02114       {
02115         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
02116       }
02117     }
02118
02119   }
02120
02121   /* Parameters update conditioned to ADC state:                              */
02122   /* Parameters that can be updated only when ADC is disabled:                */
02123   /*  - Single or differential mode                                           */
02124   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02125   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02126   {
02127     /* Set mode single-ended or differential input of the selected ADC channel */
02128     LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
02129
02130     /* Configuration of differential mode */
02131     /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
02132     if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
02133     {
02134       /* Set sampling time of the selected ADC channel */
02135       LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
02136     }
02137
02138     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
02139     /* internal measurement paths enable: If internal channel selected,       */
02140     /* enable dedicated internal buffers and path.                            */
02141     /* Note: these internal measurement paths can be disabled using           */
02142     /* HAL_ADC_DeInit().                                                      */
02143
02144     if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
02145     {
02146       /* Configuration of common ADC parameters (continuation)                */
02147       /* Software is allowed to change common parameters only when all ADCs   */
02148       /* of the common group are disabled.                                    */
02149       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02150       {
02151         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02152
02153         /* If the requested internal measurement path has already been enabled, */
02154         /* bypass the configuration processing.                                 */
02155         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02156         {
02157           if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02158           {
02159             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02160
02161             /* Delay for temperature sensor stabilization time */
02162             /* Wait loop initialization and execution */
02163             /* Note: Variable divided by 2 to compensate partially              */
02164             /*       CPU processing cycles, scaling in us split to not          */
02165             /*       exceed 32 bits register capacity and handle low frequency. */
02166             wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
02167             while(wait_loop_index != 0UL)
02168             {
02169               wait_loop_index--;
02170             }
02171           }
02172         }
02173         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02174         {
02175           if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02176           {
02177             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02178           }
02179         }
02180         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02181         {
02182           if (ADC_VREFINT_INSTANCE(hadc))
02183           {
02184             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02185           }
02186         }
02187         else
02188         {
02189           /* nothing to do */
02190         }
02191       }
02192       /* If the requested internal measurement path has already been enabled  */
02193       /* and other ADC of the common group are enabled, internal              */
02194       /* measurement paths cannot be enabled.                                 */
02195       else
02196       {
02197         /* Update ADC state machine to error */
02198         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02199
02200         tmp_hal_status = HAL_ERROR;
02201       }
02202     }
02203
02204   }
02205
02206   /* Process unlocked */
02207   __HAL_UNLOCK(hadc);
02208
02209   /* Return function status */
02210   return tmp_hal_status;
02211 }
02212
02213 /**
02214   * @brief  Enable ADC multimode and configure multimode parameters
02215   * @note   Possibility to update parameters on the fly:
02216   *         This function initializes multimode parameters, following
02217   *         calls to this function can be used to reconfigure some parameters
02218   *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
02219   *         the ADCs.
02220   *         The setting of these parameters is conditioned to ADC state.
02221   *         For parameters constraints, see comments of structure
02222   *         "ADC_MultiModeTypeDef".
02223   * @note   To move back configuration from multimode to single mode, ADC must
02224   *         be reset (using function HAL_ADC_Init() ).
02225   * @param hadc Master ADC handle
02226   * @param multimode Structure of ADC multimode configuration
02227   * @retval HAL status
02228   */
02229 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
02230 {
02231   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02232   ADC_Common_TypeDef *tmpADC_Common;
02233   ADC_HandleTypeDef  tmphadcSlave;
02234   uint32_t tmphadcSlave_conversion_on_going;
02235
02236   /* Check the parameters */
02237   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
02238   assert_param(IS_ADC_MULTIMODE(multimode->Mode));
02239   if (multimode->Mode != ADC_MODE_INDEPENDENT)
02240   {
02241     assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
02242     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
02243   }
02244
02245   /* Process locked */
02246   __HAL_LOCK(hadc);
02247
02248   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
02249
02250   if (tmphadcSlave.Instance == NULL)
02251   {
02252     /* Update ADC state machine to error */
02253     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02254
02255     /* Process unlocked */
02256     __HAL_UNLOCK(hadc);
02257
02258     return HAL_ERROR;
02259   }
02260
02261   /* Parameters update conditioned to ADC state:                              */
02262   /* Parameters that can be updated when ADC is disabled or enabled without   */
02263   /* conversion on going on regular group:                                    */
02264   /*  - Multimode DATA Format configuration                                   */
02265   tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
02266   if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02267       && (tmphadcSlave_conversion_on_going == 0UL))
02268   {
02269     /* Pointer to the common control register */
02270     tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
02271
02272     /* If multimode is selected, configure all multimode parameters.          */
02273     /* Otherwise, reset multimode parameters (can be used in case of          */
02274     /* transition from multimode to independent mode).                        */
02275     if (multimode->Mode != ADC_MODE_INDEPENDENT)
02276     {
02277     MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
02278
02279       /* Parameters that can be updated only when ADC is disabled:              */
02280       /*  - Multimode mode selection                                            */
02281       /*  - Multimode delay                                                     */
02282       /*    Note: Delay range depends on selected resolution:                   */
02283       /*      from 1 to 9 clock cycles for 16 bits                              */
02284       /*      from 1 to 9 clock cycles for 14 bits,                             */
02285       /*      from 1 to 8 clock cycles for 12 bits                              */
02286       /*      from 1 to 6 clock cycles for 10 and 8 bits                        */
02287       /*    If a higher delay is selected, it will be clipped to maximum delay  */
02288       /*    range                                                               */
02289
02290       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02291       {
02292         MODIFY_REG(tmpADC_Common->CCR,
02293                    ADC_CCR_DUAL |
02294                    ADC_CCR_DELAY,
02295                    multimode->Mode |
02296                    multimode->TwoSamplingDelay
02297                   );
02298       }
02299     }
02300     else /* ADC_MODE_INDEPENDENT */
02301     {
02302       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
02303
02304       /* Parameters that can be updated only when ADC is disabled:                */
02305       /*  - Multimode mode selection                                              */
02306       /*  - Multimode delay                                                       */
02307       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02308       {
02309         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
02310       }
02311     }
02312   }
02313   /* If one of the ADC sharing the same common group is enabled, no update    */
02314   /* could be done on neither of the multimode structure parameters.          */
02315   else
02316   {
02317     /* Update ADC state machine to error */
02318     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02319
02320     tmp_hal_status = HAL_ERROR;
02321   }
02322
02323   /* Process unlocked */
02324   __HAL_UNLOCK(hadc);
02325
02326   /* Return function status */
02327   return tmp_hal_status;
02328 }
02329
02330 /**
02331   * @brief  Enable Injected Queue
02332   * @note   This function resets CFGR register JQDIS bit in order to enable the
02333   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02334   *         are both equal to 0 to ensure that no regular nor injected
02335   *         conversion is ongoing.
02336   * @param hadc ADC handle
02337   * @retval HAL status
02338   */
02339 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
02340 {
02341   HAL_StatusTypeDef tmp_hal_status;
02342   uint32_t tmp_adc_is_conversion_on_going_regular;
02343   uint32_t tmp_adc_is_conversion_on_going_injected;
02344
02345   /* Check the parameters */
02346   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02347
02348   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02349   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02350
02351   /* Parameter can be set only if no conversion is on-going */
02352   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02353       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02354      )
02355   {
02356     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02357
02358     /* Update state, clear previous result related to injected queue overflow */
02359     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02360
02361     tmp_hal_status = HAL_OK;
02362   }
02363   else
02364   {
02365     tmp_hal_status = HAL_ERROR;
02366   }
02367
02368   return tmp_hal_status;
02369 }
02370
02371 /**
02372   * @brief  Disable Injected Queue
02373   * @note   This function sets CFGR register JQDIS bit in order to disable the
02374   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02375   *         are both equal to 0 to ensure that no regular nor injected
02376   *         conversion is ongoing.
02377   * @param hadc ADC handle
02378   * @retval HAL status
02379   */
02380 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
02381 {
02382   HAL_StatusTypeDef tmp_hal_status;
02383   uint32_t tmp_adc_is_conversion_on_going_regular;
02384   uint32_t tmp_adc_is_conversion_on_going_injected;
02385
02386   /* Check the parameters */
02387   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02388
02389   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02390   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02391
02392   /* Parameter can be set only if no conversion is on-going */
02393   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02394       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02395      )
02396   {
02397     LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
02398     tmp_hal_status = HAL_OK;
02399   }
02400   else
02401   {
02402     tmp_hal_status = HAL_ERROR;
02403   }
02404
02405   return tmp_hal_status;
02406 }
02407
02408 /**
02409   * @brief  Disable ADC voltage regulator.
02410   * @note   Disabling voltage regulator allows to save power. This operation can
02411   *         be carried out only when ADC is disabled.
02412   * @note   To enable again the voltage regulator, the user is expected to
02413   *         resort to HAL_ADC_Init() API.
02414   * @param hadc ADC handle
02415   * @retval HAL status
02416   */
02417 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
02418 {
02419   HAL_StatusTypeDef tmp_hal_status;
02420
02421   /* Check the parameters */
02422   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02423
02424   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
02425   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02426   {
02427     LL_ADC_DisableInternalRegulator(hadc->Instance);
02428     tmp_hal_status = HAL_OK;
02429   }
02430   else
02431   {
02432     tmp_hal_status = HAL_ERROR;
02433   }
02434
02435   return tmp_hal_status;
02436 }
02437
02438 /**
02439   * @brief  Enter ADC deep-power-down mode
02440   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
02441   *         in reducing leakage currents. It is particularly interesting before
02442   *         entering stop modes.
02443   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
02444   *         ADC voltage regulator. This means that this API encompasses
02445   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
02446   *         calibration is lost.
02447   * @note   To exit the ADC deep-power-down mode, the user is expected to
02448   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
02449   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
02450   *         saved calibration factor.
02451   * @param hadc ADC handle
02452   * @retval HAL status
02453   */
02454 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
02455 {
02456   HAL_StatusTypeDef tmp_hal_status;
02457
02458   /* Check the parameters */
02459   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02460
02461   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
02462   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02463   {
02464     LL_ADC_EnableDeepPowerDown(hadc->Instance);
02465     tmp_hal_status = HAL_OK;
02466   }
02467   else
02468   {
02469     tmp_hal_status = HAL_ERROR;
02470   }
02471
02472   return tmp_hal_status;
02473 }
02474
02475 /**
02476   * @}
02477   */
02478
02479 /**
02480   * @}
02481   */
02482
02483 #endif /* HAL_ADC_MODULE_ENABLED */
02484 /**
02485   * @}
02486   */
02487
02488 /**
02489   * @}
02490   */
02491
02492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_adc_ex.h Source File

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stm32h7xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_ADC_EX_H
00022 #define STM32H7xx_HAL_ADC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup ADCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  ADC Injected Conversion Oversampling structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00050                                                This parameter can be a value between 1 and 1024 */
00051
00052   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00053                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00054 } ADC_InjOversamplingTypeDef;
00055
00056 /**
00057   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
00058   * @note   Parameters of this structure are shared within 2 scopes:
00059   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
00060   *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00061   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
00062   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00063   *         ADC state can be either:
00064   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
00065   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
00066   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
00067   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
00068   *            on ADC groups regular and injected.
00069   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00070   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00071   */
00072 typedef struct
00073 {
00074   uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
00075                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00076                                                Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00077
00078   uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
00079                                                This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
00080                                                Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00081                                                the new channel setting (or parameter number of conversions adjusted) */
00082
00083   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00084                                                Unit: ADC clock cycles.
00085                                                Conversion time is the addition of sampling time and processing time
00086                                                (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00087                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
00088                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00089                                                         It overwrites the last setting.
00090                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00091                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00092                                                      Refer to device datasheet for timings values. */
00093
00094   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00095                                                In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00096                                                Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00097                                                This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
00098                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00099                                                         It overwrites the last setting.
00100                                                Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00101                                                Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00102                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00103                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00104                                                of another parameter update on the fly) */
00105
00106   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
00107                                                This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
00108                                                Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00109
00110   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
00111                                                Offset value must be a positive number.
00112                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00113                                                between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.
00114                                                Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00115                                                without continuous mode or external trigger that could launch a conversion). */
00116
00117   uint32_t InjectedOffsetRightShift;       /*!< Specifies whether the 1 bit Right-shift feature is used or not.
00118                                                 This parameter is applied only for 16-bit or 8-bit resolution.
00119                                                 This parameter can be set to ENABLE or DISABLE. */
00120
00121   FunctionalState InjectedOffsetSignedSaturation;      /*!< Specifies whether the Signed saturation feature is used or not.
00122                                                This parameter is applied only for 16-bit or 8-bit resolution.
00123                                                This parameter can be set to ENABLE or DISABLE. */
00124   uint32_t InjectedLeftBitShift;          /*!< Configures the left shifting applied to the final result with or without oversampling.
00125                                                This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
00126
00127   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
00128                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00129                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00130                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00131                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00132
00133   FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
00134                                                (main sequence subdivided in successive parts).
00135                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00136                                                Discontinuous mode can be enabled only if continuous mode is disabled.
00137                                                This parameter can be set to ENABLE or DISABLE.
00138                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00139                                                Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
00140                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00141                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00142
00143   FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
00144                                                This parameter can be set to ENABLE or DISABLE.
00145                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00146                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
00147                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00148                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00149                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00150                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00151
00152   FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
00153                                                This parameter can be set to ENABLE or DISABLE.
00154                                                If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
00155                                                new injected context is set when queue is full, error is triggered by interruption and through function
00156                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
00157                                                Caution: This feature request that the sequence is fully configured before injected conversion start.
00158                                                         Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
00159                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00160                                                         configure a channel on injected group can impact the configuration of other channels previously set.
00161                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
00162
00163   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00164                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00165                                                This parameter can be a value of @ref ADC_injected_external_trigger_source.
00166                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00167                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00168
00169   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00170                                                This parameter can be a value of @ref ADC_injected_external_trigger_edge.
00171                                                If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00172                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00173                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00174
00175   FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
00176                                                       This parameter can be set to ENABLE or DISABLE.
00177                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00178
00179   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
00180                                                       Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
00181                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00182 } ADC_InjectionConfTypeDef;
00183
00184 /**
00185   * @brief  Structure definition of ADC multimode
00186   * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
00187   *         Both Master and Slave ADCs must be disabled.
00188   */
00189 typedef struct
00190 {
00191   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
00192                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
00193
00194   uint32_t DualModeData;      /*!< Configures the Dual ADC Mode Data Format:
00195                                    This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
00196
00197   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00198                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
00199                                    Delay range depends on selected resolution:
00200                                    from 1 to 9 clock cycles for 16 bits,
00201                                    from 1 to 9 clock cycles for 14 bits
00202                                    from 1 to 8 clock cycles for 12 bits
00203                                    from 1 to 6 clock cycles for 10 bits
00204                                    from 1 to 6 clock cycles for 8 bits     */
00205 } ADC_MultiModeTypeDef;
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported constants --------------------------------------------------------*/
00212
00213 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00214   * @{
00215   */
00216
00217 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
00218   * @{
00219   */
00220 /* ADC group regular trigger sources for all ADC instances */
00221 #define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< Software triggers injected group conversion start */
00222 #define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
00223 #define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00224 #define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
00225 #define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00226 #define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00227 #define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
00228 #define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
00229 #define ADC_EXTERNALTRIGINJEC_T8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00230 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
00231 #define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
00232 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
00233 #define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00234 #define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
00235 #define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00236 #define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
00237 #define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
00238 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
00239 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
00240 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
00241 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
00242 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
00248   * @{
00249   */
00250 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions hardware trigger detection disabled                             */
00251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */
00252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */
00253 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
00259   * @{
00260   */
00261 #define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
00262 #define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
00268   * @{
00269   */
00270 #define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
00271 #define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00272 #define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00273 #define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00274 #define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
00280   * @{
00281   */
00282 #define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
00283 #define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
00284 #define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
00285 #define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
00291   * @{
00292   */
00293 #define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)                                          /*!< ADC dual mode disabled (ADC independent mode) */
00294 #define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
00295 #define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
00296 #define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
00297 #define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
00298 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
00299 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
00300 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
00301
00302 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
00303   * @{
00304   */
00305 #define ADC_DUALMODEDATAFORMAT_DISABLED      (0x00000000UL)                       /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
00306 #define ADC_DUALMODEDATAFORMAT_32_10_BITS    (ADC_CCR_DAMDF_1)                    /*!< Data formatting mode for 32 down to 10-bit resolution */
00307 #define ADC_DUALMODEDATAFORMAT_8_BITS        ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
00313   * @{
00314   */
00315 #define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)   /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
00316 #define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
00317 #define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
00318 #define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
00319 #define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
00320 #define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
00321 #define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
00322 #define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
00323 #define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
00333   * @{
00334   */
00335 #define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
00336 #define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)          /*!< ADC group injected (not available on all STM32 devices)*/
00337 #define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED)  /*!< ADC both groups regular and injected */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
00343   * @{
00344   */
00345 #define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
00346                             ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
00347                             ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
00348                             ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
00349                             ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
00350                             ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
00356   * @{
00357   */
00358 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
00359                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
00360                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
00361                              ADC_SMPR1_SMP0)
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
00367   * @{
00368   */
00369 /* ADC_CFGR fields of parameters that can be updated when no conversion
00370    (neither regular nor injected) is on-going  */
00371 #define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
00372 /**
00373   * @}
00374   */
00375
00376 #if defined(DFSDM1_Channel0)
00377 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
00378   * @{
00379   */
00380 #define ADC_DFSDM_MODE_DISABLE     (0x00000000UL)                     /*!< ADC conversions are not transferred by DFSDM. */
00381 #define ADC_DFSDM_MODE_ENABLE      (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
00382 /**
00383   * @}
00384   */
00385 #endif
00386
00387 /**
00388   * @}
00389   */
00390
00391 /* Exported macros -----------------------------------------------------------*/
00392
00393 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
00394   * @{
00395   */
00396
00397 /** @brief  Force ADC instance in multimode mode independent (multimode disable).
00398   * @note   This macro must be used only in case of transition from multimode
00399   *         to mode independent and in case of unknown previous state,
00400   *         to ensure ADC configuration is in mode independent.
00401   * @note   Standard way of multimode configuration change is done from
00402   *         HAL ADC handle of ADC master using function
00403   *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
00404   *         Usage of this macro is not the Standard way of multimode
00405   *         configuration and can lead to have HAL ADC handles status
00406   *         misaligned. Usage of this macro must be limited to cases
00407   *         mentionned above.
00408   * @param __HANDLE__ ADC handle.
00409   * @retval None
00410   */
00411 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
00412   LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
00413
00414 /**
00415   * @}
00416   */
00417
00418 /* Private macros ------------------------------------------------------------*/
00419
00420 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00421   * @{
00422   */
00423 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00424 /* code of final user.                                                        */
00425
00426 /**
00427   * @brief Test if conversion trigger of injected group is software start
00428   *        or external trigger.
00429   * @param __HANDLE__ ADC handle.
00430   * @retval SET (software start) or RESET (external trigger).
00431   */
00432 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00433   (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
00434
00435 /**
00436   * @brief Check if conversion is on going on regular or injected groups.
00437   * @param __HANDLE__ ADC handle.
00438   * @retval SET (conversion is on going) or RESET (no conversion is on going).
00439   */
00440 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                       \
00441        (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
00442         ) ? RESET : SET)
00443
00444 /**
00445   * @brief Check if conversion is on going on injected group.
00446   * @param __HANDLE__ ADC handle.
00447   * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
00448   */
00449 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                         \
00450   (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
00451
00452 /**
00453   * @brief Check whether or not ADC is independent.
00454   * @param __HANDLE__ ADC handle.
00455   * @note  When multimode feature is not available, the macro always returns SET.
00456   * @retval SET (ADC is independent) or RESET (ADC is not).
00457   */
00458 #if defined (ADC3)
00459 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
00460   ( ( ( ((__HANDLE__)->Instance) == ADC3) \
00461     )?                                    \
00462      SET                                  \
00463      :                                    \
00464      RESET                                \
00465   )
00466 #endif
00467
00468 /**
00469   * @brief Set the selected injected Channel rank.
00470   * @param __CHANNELNB__ Channel number.
00471   * @param __RANKNB__ Rank number.
00472   * @retval None
00473   */
00474 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
00475
00476 /**
00477   * @brief Configure ADC injected context queue
00478   * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
00479   * @retval None
00480   */
00481 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
00482
00483 /**
00484   * @brief Configure ADC discontinuous conversion mode for injected group
00485   * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
00486   * @retval None
00487   */
00488 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
00489
00490 /**
00491   * @brief Configure ADC discontinuous conversion mode for regular group
00492   * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
00493   * @retval None
00494   */
00495 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
00496
00497 /**
00498   * @brief Configure the number of discontinuous conversions for regular group.
00499   * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
00500   * @retval None
00501   */
00502 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
00503
00504 /**
00505   * @brief Configure the ADC auto delay mode.
00506   * @param __AUTOWAIT__ Auto delay bit enable or disable.
00507   * @retval None
00508   */
00509 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
00510
00511 /**
00512   * @brief Configure ADC continuous conversion mode.
00513   * @param __CONTINUOUS_MODE__ Continuous mode.
00514   * @retval None
00515   */
00516 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
00517
00518 /**
00519   * @brief Enable the ADC DMA continuous request.
00520   * @param __DMACONTREQ_MODE__: DMA continuous request mode.
00521   * @retval None
00522   */
00523 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
00524
00525 /**
00526   * @brief Configure the channel number into offset OFRx register.
00527   * @param __CHANNEL__ ADC Channel.
00528   * @retval None
00529   */
00530 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
00531
00532 /**
00533   * @brief Configure the channel number into differential mode selection register.
00534   * @param __CHANNEL__ ADC Channel.
00535   * @retval None
00536   */
00537 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
00538
00539 /**
00540   * @brief Configure calibration factor in differential mode to be set into calibration register.
00541   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00542   * @retval None
00543   */
00544 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
00545
00546 /**
00547   * @brief Calibration factor in differential mode to be retrieved from calibration register.
00548   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00549   * @retval None
00550   */
00551 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
00552
00553 /**
00554   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
00555   * @param __THRESHOLD__ Threshold value.
00556   * @retval None
00557   */
00558 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
00559
00560 /**
00561   * @brief Configure the ADC DMA continuous request for ADC multimode.
00562   * @param __DMACONTREQ_MODE__ DMA continuous request mode.
00563   * @retval None
00564   */
00565 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
00566
00567 /**
00568   * @brief Shift the offset in function of the selected ADC resolution.
00569   * @note  Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0
00570   *        If resolution 16 bits, no shift.
00571   *        If resolution 14 bits, shift of 2 ranks on the left.
00572   *        If resolution 12 bits, shift of 4 ranks on the left.
00573   *        If resolution 10 bits, shift of 6 ranks on the left.
00574   *        If resolution 8 bits, shift of 8 ranks on the left.
00575   *        therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
00576   * @param __HANDLE__: ADC handle
00577   * @param __OFFSET__: Value to be shifted
00578   * @retval None
00579   */
00580 #if defined(ADC_VER_V5_3)
00581 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \
00582         (                                                                                                       \
00583            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                           \
00584               ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \
00585                :                                                                                                \
00586                ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00587         )
00588 #else
00589 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \
00590         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                      \
00591           ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \
00592              :                                                                                                  \
00593             ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                          \
00594               ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \
00595                :                                                                                                \
00596                ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00597         )
00598 #endif /* ADC_VER_V5_3 */
00599
00600 /**
00601   * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
00602   * @note  Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
00603   *        If resolution 16 bits, no shift.
00604   *        If resolution 14 bits, shift of 2 ranks on the left.
00605   *        If resolution 12 bits, shift of 4 ranks on the left.
00606   *        If resolution 10 bits, shift of 6 ranks on the left.
00607   *        If resolution 8 bits, shift of 8 ranks on the left.
00608   *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
00609   * @param __HANDLE__: ADC handle
00610   * @param __THRESHOLD__: Value to be shifted
00611   * @retval None
00612   */
00613 #if defined(ADC_VER_V5_3)
00614 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \
00615         (                                                                                                         \
00616            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \
00617             ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
00618               :                                                                                                   \
00619               ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00620         )
00621 #else
00622 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \
00623         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                        \
00624          ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \
00625             :                                                                                                     \
00626            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \
00627             ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
00628               :                                                                                                   \
00629               ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00630         )
00631 #endif /* ADC_VER_V5_3 */
00632
00633 /**
00634   * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
00635   * @note  Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
00636   *        If resolution 16 bits, no shift.
00637   *        If resolution 14 bits, shift of 2 ranks on the left.
00638   *        If resolution 12 bits, shift of 4 ranks on the left.
00639   *        If resolution 10 bits, shift of 6 ranks on the left.
00640   *        If resolution 8 bits, shift of 8 ranks on the left.
00641   *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
00642   * @param __HANDLE__: ADC handle
00643   * @param __THRESHOLD__: Value to be shifted
00644   * @retval None
00645   */
00646 #if defined(ADC_VER_V5_3)
00647 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \
00648         (                                                                                                           \
00649             ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \
00650               ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
00651                 :                                                                                                   \
00652                 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00653         )
00654 #else
00655 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \
00656         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                          \
00657           ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                        \
00658             :                                                                                                       \
00659             ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \
00660               ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
00661                 :                                                                                                   \
00662                 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
00663         )
00664 #endif /* ADC_VER_V5_3 */
00665 /**
00666   * @brief Clear Common Control Register.
00667   * @param __HANDLE__ ADC handle.
00668   * @retval None
00669   */
00670 /**
00671   * @brief Report common register to ADC1 and ADC2
00672   * @param __HANDLE__: ADC handle
00673   * @retval Common control register
00674   */
00675 #define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)
00676 #if defined (ADC3)
00677 /**
00678   * @brief Report common register to ADC3
00679   * @param __HANDLE__: ADC handle
00680   * @retval Common control register
00681   */
00682 #define ADC3_COMMON_REGISTER(__HANDLE__)   (ADC3_COMMON)
00683 #endif
00684 /**
00685   * @brief Report Master Instance
00686   * @param __HANDLE__: ADC handle
00687   * @note return same instance if ADC of input handle is independent ADC
00688   * @retval Master Instance
00689   */
00690 #if defined (ADC3)
00691 #define ADC_MASTER_REGISTER(__HANDLE__)                                          \
00692   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
00693     )?                                                                           \
00694      ((__HANDLE__)->Instance)                                                    \
00695      :                                                                           \
00696      (ADC1)                                                                      \
00697   )
00698 #else
00699 #define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
00700 #endif
00701
00702 /**
00703   * @brief Check whether or not dual regular conversions are enabled
00704   * @param __HANDLE__: ADC handle
00705   * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
00706   */
00707 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
00708   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
00709     )?                                                                           \
00710      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
00711        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
00712        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
00713      :                                                                           \
00714      RESET                                                                       \
00715   )
00716
00717 /**
00718   * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
00719   * @param __HANDLE__: ADC handle
00720   * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
00721   */
00722 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
00723   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \
00724     )?                                                                         \
00725      SET                                                                       \
00726      :                                                                         \
00727      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
00728   )
00729 #if defined (ADC3)
00730 /**
00731   * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
00732   * @param __HANDLE__: ADC handle
00733   * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
00734   */
00735 #define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
00736   ( ( ((__HANDLE__)->Instance == ADC3)                                          \
00737     )?                                                                         \
00738      SET                                                                       \
00739      :                                                                         \
00740      ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
00741   )
00742 #endif
00743 /**
00744   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
00745   * @param __HANDLE__: ADC handle
00746   * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
00747   */
00748 #if defined (ADC3)
00749 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
00750   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
00751     )?                                                                      \
00752      SET                                                                    \
00753      :                                                                      \
00754      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
00755        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
00756        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
00757 #else
00758 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
00759   ( ( ((__HANDLE__)->Instance == ADC1)                                      \
00760     )?                                                                      \
00761      SET                                                                    \
00762      :                                                                      \
00763      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
00764        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
00765        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
00766 #endif
00767
00768 /**
00769   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
00770   * @param __HANDLE__: ADC handle
00771   * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
00772   */
00773 #if defined (ADC3)
00774 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \
00775   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
00776     )?                                                                     \
00777      SET                                                                   \
00778      :                                                                     \
00779      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
00780        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
00781        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
00782 #else
00783 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \
00784   ( ( ((__HANDLE__)->Instance == ADC1)                                    \
00785     )?                                                                     \
00786      SET                                                                   \
00787      :                                                                     \
00788      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
00789        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
00790        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
00791 #endif
00792
00793 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE    | \
00794                                                                                                       ADC_CCR_PRESC     | \
00795                                                                                                       ADC_CCR_VBATEN    | \
00796                                                                                                       ADC_CCR_TSEN      | \
00797                                                                                                       ADC_CCR_VREFEN    | \
00798                                                                                                       ADC_CCR_DAMDF     | \
00799                                                                                                       ADC_CCR_DELAY     | \
00800                                                                                                       ADC_CCR_DUAL  )
00801
00802 /**
00803   * @brief Set handle instance of the ADC slave associated to the ADC master.
00804   * @param __HANDLE_MASTER__ ADC master handle.
00805   * @param __HANDLE_SLAVE__ ADC slave handle.
00806   * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
00807   * @retval None
00808   */
00809 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
00810   ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
00811
00812
00813 /**
00814   * @brief Verify the ADC instance connected to the temperature sensor.
00815   * @param __HANDLE__ ADC handle.
00816   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00817   */
00818 #if defined(ADC3)
00819 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
00820 #else
00821 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
00822 #endif
00823
00824 /**
00825   * @brief Verify the ADC instance connected to the battery voltage VBAT.
00826   * @param __HANDLE__ ADC handle.
00827   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00828   */
00829 #if defined(ADC3)
00830 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
00831 #else
00832 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
00833 #endif
00834
00835 /**
00836   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
00837   * @param __HANDLE__ ADC handle.
00838   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00839   */
00840 #if defined(ADC3)
00841 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
00842 #else
00843 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
00844 #endif
00845
00846 /**
00847   * @brief Verify the length of scheduled injected conversions group.
00848   * @param __LENGTH__ number of programmed conversions.
00849   * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
00850   */
00851 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
00852
00853 /**
00854   * @brief Calibration factor size verification (7 bits maximum).
00855   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00856   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
00857   */
00858 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
00859
00860
00861 /**
00862   * @brief Verify the ADC channel setting.
00863   * @param __CHANNEL__ programmed ADC channel.
00864   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00865   */
00866 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0)           || \
00867                                      ((__CHANNEL__) == ADC_CHANNEL_1)           || \
00868                                      ((__CHANNEL__) == ADC_CHANNEL_2)           || \
00869                                      ((__CHANNEL__) == ADC_CHANNEL_3)           || \
00870                                      ((__CHANNEL__) == ADC_CHANNEL_4)           || \
00871                                      ((__CHANNEL__) == ADC_CHANNEL_5)           || \
00872                                      ((__CHANNEL__) == ADC_CHANNEL_6)           || \
00873                                      ((__CHANNEL__) == ADC_CHANNEL_7)           || \
00874                                      ((__CHANNEL__) == ADC_CHANNEL_8)           || \
00875                                      ((__CHANNEL__) == ADC_CHANNEL_9)           || \
00876                                      ((__CHANNEL__) == ADC_CHANNEL_10)          || \
00877                                      ((__CHANNEL__) == ADC_CHANNEL_11)          || \
00878                                      ((__CHANNEL__) == ADC_CHANNEL_12)          || \
00879                                      ((__CHANNEL__) == ADC_CHANNEL_13)          || \
00880                                      ((__CHANNEL__) == ADC_CHANNEL_14)          || \
00881                                      ((__CHANNEL__) == ADC_CHANNEL_15)          || \
00882                                      ((__CHANNEL__) == ADC_CHANNEL_16)          || \
00883                                      ((__CHANNEL__) == ADC_CHANNEL_17)          || \
00884                                      ((__CHANNEL__) == ADC_CHANNEL_18)          || \
00885                                      ((__CHANNEL__) == ADC_CHANNEL_19)          || \
00886                                      ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
00887                                      ((__CHANNEL__) == ADC_CHANNEL_VBAT)        || \
00888                                      ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
00889                                      ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
00890                                      ((__CHANNEL__) == ADC_CHANNEL_VREFINT)       )
00891
00892 /**
00893   * @brief Verify the ADC channel setting in differential mode for ADC1.
00894   * @param __CHANNEL__: programmed ADC channel.
00895   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00896   */
00897 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
00898                                            ((__CHANNEL__) == ADC_CHANNEL_2)      ||\
00899                                            ((__CHANNEL__) == ADC_CHANNEL_3)      ||\
00900                                            ((__CHANNEL__) == ADC_CHANNEL_4)      ||\
00901                                            ((__CHANNEL__) == ADC_CHANNEL_5)      ||\
00902                                            ((__CHANNEL__) == ADC_CHANNEL_10)     ||\
00903                                            ((__CHANNEL__) == ADC_CHANNEL_11)     ||\
00904                                            ((__CHANNEL__) == ADC_CHANNEL_12)     ||\
00905                                            ((__CHANNEL__) == ADC_CHANNEL_16)     ||\
00906                                            ((__CHANNEL__) == ADC_CHANNEL_18)      )
00907
00908 /**
00909   * @brief Verify the ADC channel setting in differential mode for ADC2.
00910   * @param __CHANNEL__: programmed ADC channel.
00911   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00912   */
00913 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
00914                                            ((__CHANNEL__) == ADC_CHANNEL_2)      || \
00915                                            ((__CHANNEL__) == ADC_CHANNEL_3)      || \
00916                                            ((__CHANNEL__) == ADC_CHANNEL_4)      || \
00917                                            ((__CHANNEL__) == ADC_CHANNEL_5)      || \
00918                                            ((__CHANNEL__) == ADC_CHANNEL_10)     || \
00919                                            ((__CHANNEL__) == ADC_CHANNEL_11)     || \
00920                                            ((__CHANNEL__) == ADC_CHANNEL_12)     || \
00921                                            ((__CHANNEL__) == ADC_CHANNEL_18)      )
00922
00923 /**
00924   * @brief Verify the ADC channel setting in differential mode for ADC3.
00925   * @param __CHANNEL__: programmed ADC channel.
00926   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00927   */
00928 #define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
00929                                            ((__CHANNEL__) == ADC_CHANNEL_2)      || \
00930                                            ((__CHANNEL__) == ADC_CHANNEL_3)      || \
00931                                            ((__CHANNEL__) == ADC_CHANNEL_4)      || \
00932                                            ((__CHANNEL__) == ADC_CHANNEL_5)      || \
00933                                            ((__CHANNEL__) == ADC_CHANNEL_10)     || \
00934                                            ((__CHANNEL__) == ADC_CHANNEL_11)     || \
00935                                            ((__CHANNEL__) == ADC_CHANNEL_13)     || \
00936                                            ((__CHANNEL__) == ADC_CHANNEL_14)     || \
00937                                            ((__CHANNEL__) == ADC_CHANNEL_15)       )
00938
00939 /**
00940   * @brief Verify the ADC single-ended input or differential mode setting.
00941   * @param __SING_DIFF__ programmed channel setting.
00942   * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
00943   */
00944 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
00945                                                    ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
00946
00947 /**
00948   * @brief Verify the ADC offset management setting.
00949   * @param __OFFSET_NUMBER__ ADC offset management.
00950   * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
00951   */
00952 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
00953                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
00954                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
00955                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
00956                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
00957
00958 /**
00959   * @brief Verify the ADC injected channel setting.
00960   * @param __CHANNEL__ programmed ADC injected channel.
00961   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00962   */
00963 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
00964                                            ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
00965                                            ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
00966                                            ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
00967
00968 /**
00969   * @brief Verify the ADC injected conversions external trigger.
00970   * @param __INJTRIG__ programmed ADC injected conversions external trigger.
00971   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
00972   */
00973 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
00974                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
00975                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
00976                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
00977                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
00978                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
00979                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
00980                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
00981                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
00982                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
00983                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
00984                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
00985                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
00986                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
00987                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
00988                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
00989                                                                                           \
00990                                            ((__INJTRIG__) == ADC_SOFTWARE_START)                   )
00991
00992 /**
00993   * @brief Verify the ADC edge trigger setting for injected group.
00994   * @param __EDGE__ programmed ADC edge trigger setting.
00995   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
00996   */
00997 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
00998                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
00999                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
01000                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
01001
01002 /**
01003   * @brief Verify the ADC multimode setting.
01004   * @param __MODE__ programmed ADC multimode setting.
01005   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01006   */
01007 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
01008                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
01009                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
01010                                     ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
01011                                     ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
01012                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
01013                                     ((__MODE__) == ADC_DUALMODE_INTERL)                || \
01014                                     ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
01015
01016 /**
01017   * @brief Verify the ADC dual data mode setting.
01018   * @param MODE: programmed ADC dual mode setting.
01019   * @retval SET (MODE is valid) or RESET (MODE is invalid)
01020   */
01021 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED)   || \
01022                                      ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
01023                                      ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS)     )
01024
01025 /**
01026   * @brief Verify the ADC multimode delay setting.
01027   * @param __DELAY__ programmed ADC multimode delay setting.
01028   * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
01029   */
01030 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
01031                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
01032                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
01033                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
01034                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
01035                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
01036                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
01037                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
01038                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)    )
01039
01040 /**
01041   * @brief Verify the ADC analog watchdog setting.
01042   * @param __WATCHDOG__ programmed ADC analog watchdog setting.
01043   * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
01044   */
01045 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
01046                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
01047                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
01048
01049 /**
01050   * @brief Verify the ADC analog watchdog mode setting.
01051   * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
01052   * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
01053   */
01054 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
01055                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
01056                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
01057                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
01058                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
01059                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
01060                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
01061
01062 /**
01063   * @brief Verify the ADC conversion (regular or injected or both).
01064   * @param __CONVERSION__ ADC conversion group.
01065   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
01066   */
01067 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
01068                                                  ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
01069                                                  ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
01070
01071 /**
01072   * @brief Verify the ADC event type.
01073   * @param __EVENT__ ADC event.
01074   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
01075   */
01076 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
01077                                       ((__EVENT__) == ADC_AWD_EVENT)    || \
01078                                       ((__EVENT__) == ADC_AWD2_EVENT)   || \
01079                                       ((__EVENT__) == ADC_AWD3_EVENT)   || \
01080                                       ((__EVENT__) == ADC_OVR_EVENT)    || \
01081                                       ((__EVENT__) == ADC_JQOVF_EVENT)  )
01082
01083 /**
01084   * @brief Verify the ADC oversampling ratio.
01085   * @param RATIO: programmed ADC oversampling ratio.
01086   * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
01087   */
01088 #define IS_ADC_OVERSAMPLING_RATIO(RATIO)  (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
01089
01090 /**
01091   * @brief Verify the ADC oversampling shift.
01092   * @param __SHIFT__ programmed ADC oversampling shift.
01093   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
01094   */
01095 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
01096                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
01097                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
01098                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
01099                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
01100                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
01101                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
01102                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
01103                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
01104
01105 /**
01106   * @brief Verify the ADC oversampling triggered mode.
01107   * @param __MODE__ programmed ADC oversampling triggered mode.
01108   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01109   */
01110 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
01111                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
01112
01113 /**
01114   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
01115   * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
01116   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01117   */
01118 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
01119                                                ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
01120
01121 /**
01122   * @brief Verify the DFSDM mode configuration.
01123   * @param __HANDLE__ ADC handle.
01124   * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
01125   *      this reason, the input parameter is the ADC handle and not the configuration parameter
01126   *      directly.
01127   * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
01128   */
01129 #if defined(DFSDM1_Channel0)
01130 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
01131                                           ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
01132 #else
01133 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
01134 #endif
01135
01136 /**
01137   * @brief Return the DFSDM configuration mode.
01138   * @param __HANDLE__ ADC handle.
01139   * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
01140   *       For this reason, the input parameter is the ADC handle and not the configuration parameter
01141   *       directly.
01142   * @retval DFSDM configuration mode
01143   */
01144 #if defined(DFSDM1_Channel0)
01145 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
01146 #else
01147 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
01148 #endif
01149
01150 /**
01151   * @}
01152   */
01153
01154
01155 /* Exported functions --------------------------------------------------------*/
01156 /** @addtogroup ADCEx_Exported_Functions
01157   * @{
01158   */
01159
01160 /** @addtogroup ADCEx_Exported_Functions_Group1
01161   * @{
01162   */
01163 /* IO operation functions *****************************************************/
01164
01165 /* ADC calibration */
01166 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
01167 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
01168 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
01169 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
01170 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
01171 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);
01172
01173
01174 /* Blocking mode: Polling */
01175 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
01176 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
01177 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
01178
01179 /* Non-blocking mode: Interruption */
01180 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
01181 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
01182
01183 /* ADC multimode */
01184 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01185 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01186 uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
01187
01188 /* ADC retrieve conversion value intended to be used with polling or interruption */
01189 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
01190
01191 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
01192 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
01193 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
01194 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
01195 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
01196 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
01197
01198 /* ADC group regular conversions stop */
01199 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
01200 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
01201 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
01202 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01203
01204 /**
01205   * @}
01206   */
01207
01208 /** @addtogroup ADCEx_Exported_Functions_Group2
01209   * @{
01210   */
01211 /* Peripheral Control functions ***********************************************/
01212 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
01213 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
01214 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
01215 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
01216 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
01217 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
01218
01219 /**
01220   * @}
01221   */
01222
01223 /**
01224   * @}
01225   */
01226
01227 /**
01228   * @}
01229   */
01230
01231 /**
01232   * @}
01233   */
01234
01235 #ifdef __cplusplus
01236 }
01237 #endif
01238
01239 #endif /* STM32H7xx_HAL_ADC_EX_H */
01240
01241
01242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cec.c Source File

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stm32h7xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @brief   CEC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Definition Multimedia Interface
00008   *          Consumer Electronics Control Peripheral (CEC).
00009   *           + Initialization and de-initialization function
00010   *           + IO operation function
00011   *           + Peripheral Control function
00012   *
00013   *
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019     The CEC HAL driver can be used as follow:
00020
00021     (#) Declare a CEC_HandleTypeDef handle structure.
00022     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00023         (##) Enable the CEC interface clock.
00024         (##) CEC pins configuration:
00025             (+++) Enable the clock for the CEC GPIOs.
00026             (+++) Configure these CEC pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00028              and HAL_CEC_Receive_IT() APIs):
00029             (+++) Configure the CEC interrupt priority.
00030             (+++) Enable the NVIC CEC IRQ handle.
00031             (+++) The specific CEC interrupts (Transmission complete interrupt,
00032                   RXNE interrupt and Error Interrupts) will be managed using the macros
00033                   __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00034                   and receive process.
00035
00036     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00037         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00038         address and Listen mode in the hcec Init structure.
00039
00040     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00041
00042   [..]
00043     (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00044         by calling the customed HAL_CEC_MspInit() API.
00045   *** Callback registration ***
00046   =============================================
00047
00048   The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
00049   allows the user to configure dynamically the driver callbacks.
00050   Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
00051   to register an interrupt callback.
00052
00053   Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
00054     (+) TxCpltCallback     : Tx Transfer completed callback.
00055     (+) ErrorCallback      : callback for error detection.
00056     (+) MspInitCallback    : CEC MspInit.
00057     (+) MspDeInitCallback  : CEC MspDeInit.
00058   This function takes as parameters the HAL peripheral handle, the Callback ID
00059   and a pointer to the user callback function.
00060
00061   For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
00062   @ref HAL_CEC_RegisterRxCpltCallback().
00063
00064   Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
00065   weak function.
00066   @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00067   and the Callback ID.
00068   This function allows to reset following callbacks:
00069     (+) TxCpltCallback     : Tx Transfer completed callback.
00070     (+) ErrorCallback      : callback for error detection.
00071     (+) MspInitCallback    : CEC MspInit.
00072     (+) MspDeInitCallback  : CEC MspDeInit.
00073
00074   For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
00075   @ref HAL_CEC_UnRegisterRxCpltCallback().
00076
00077   By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
00078   all callbacks are set to the corresponding weak functions :
00079   examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
00080   Exception done for MspInit and MspDeInit functions that are
00081   reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
00082   these callbacks are null (not registered beforehand).
00083   if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
00084   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00085
00086   Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
00087   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00088   in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
00089   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00090   In that case first register the MspInit/MspDeInit user callbacks
00091   using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
00092   or @ref HAL_CEC_Init() function.
00093
00094   When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
00095   not defined, the callback registration feature is not available and all callbacks
00096   are set to the corresponding weak functions.
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00102   * All rights reserved.</center></h2>
00103   *
00104   * This software component is licensed by ST under BSD 3-Clause license,
00105   * the "License"; You may not use this file except in compliance with the
00106   * License. You may obtain a copy of the License at:
00107   *                        opensource.org/licenses/BSD-3-Clause
00108   *
00109   ******************************************************************************
00110   */
00111
00112 /* Includes ------------------------------------------------------------------*/
00113 #include "stm32h7xx_hal.h"
00114
00115 /** @addtogroup STM32H7xx_HAL_Driver
00116   * @{
00117   */
00118
00119 /** @defgroup CEC CEC
00120   * @brief HAL CEC module driver
00121   * @{
00122   */
00123 #ifdef HAL_CEC_MODULE_ENABLED
00124 #if defined (CEC)
00125
00126 /* Private typedef -----------------------------------------------------------*/
00127 /* Private define ------------------------------------------------------------*/
00128 /** @defgroup CEC_Private_Constants CEC Private Constants
00129   * @{
00130   */
00131 /**
00132   * @}
00133   */
00134
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /** @defgroup CEC_Private_Functions CEC Private Functions
00139   * @{
00140   */
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions ---------------------------------------------------------*/
00146
00147 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00152   *  @brief    Initialization and Configuration functions
00153   *
00154 @verbatim
00155 ===============================================================================
00156             ##### Initialization and Configuration functions #####
00157  ===============================================================================
00158     [..]
00159     This subsection provides a set of functions allowing to initialize the CEC
00160       (+) The following parameters need to be configured:
00161         (++) SignalFreeTime
00162         (++) Tolerance
00163         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00164         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00165         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00166         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00167         (++) SignalFreeTimeOption      (SFT Timer start definition)
00168         (++) OwnAddress                (CEC device address)
00169         (++) ListenMode
00170
00171 @endverbatim
00172   * @{
00173   */
00174
00175 /**
00176   * @brief Initializes the CEC mode according to the specified
00177   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00178   * @param hcec CEC handle
00179   * @retval HAL status
00180   */
00181 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00182 {
00183   /* Check the CEC handle allocation */
00184   if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
00185   {
00186     return HAL_ERROR;
00187   }
00188
00189   /* Check the parameters */
00190   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00191   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00192   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00193   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00194   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00195   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00196   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00197   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00198   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00199   assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
00200
00201 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00202   if (hcec->gState == HAL_CEC_STATE_RESET)
00203   {
00204     /* Allocate lock resource and initialize it */
00205     hcec->Lock = HAL_UNLOCKED;
00206
00207     hcec->TxCpltCallback  = HAL_CEC_TxCpltCallback;  /* Legacy weak TxCpltCallback  */
00208     hcec->RxCpltCallback = HAL_CEC_RxCpltCallback;   /* Legacy weak RxCpltCallback */
00209     hcec->ErrorCallback = HAL_CEC_ErrorCallback;     /* Legacy weak ErrorCallback */
00210
00211     if (hcec->MspInitCallback == NULL)
00212     {
00213       hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit  */
00214     }
00215
00216     /* Init the low level hardware */
00217     hcec->MspInitCallback(hcec);
00218   }
00219 #else
00220   if (hcec->gState == HAL_CEC_STATE_RESET)
00221   {
00222     /* Allocate lock resource and initialize it */
00223     hcec->Lock = HAL_UNLOCKED;
00224     /* Init the low level hardware : GPIO, CLOCK */
00225     HAL_CEC_MspInit(hcec);
00226   }
00227 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00228
00229   hcec->gState = HAL_CEC_STATE_BUSY;
00230
00231   /* Disable the Peripheral */
00232   __HAL_CEC_DISABLE(hcec);
00233
00234   /* Write to CEC Control Register */
00235   hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
00236                          hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
00237                          hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
00238                          hcec->Init.ListenMode;
00239
00240   /* Enable the following CEC Transmission/Reception interrupts as
00241     * well as the following CEC Transmission/Reception Errors interrupts
00242     * Rx Byte Received IT
00243     * End of Reception IT
00244     * Rx overrun
00245     * Rx bit rising error
00246     * Rx short bit period error
00247     * Rx long bit period error
00248     * Rx missing acknowledge
00249     * Tx Byte Request IT
00250     * End of Transmission IT
00251     * Tx Missing Acknowledge IT
00252     * Tx-Error IT
00253     * Tx-Buffer Underrun IT
00254     * Tx arbitration lost   */
00255   __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
00256                       CEC_IER_TX_ALL_ERR);
00257
00258   /* Enable the CEC Peripheral */
00259   __HAL_CEC_ENABLE(hcec);
00260
00261   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00262   hcec->gState = HAL_CEC_STATE_READY;
00263   hcec->RxState = HAL_CEC_STATE_READY;
00264
00265   return HAL_OK;
00266 }
00267
00268 /**
00269   * @brief DeInitializes the CEC peripheral
00270   * @param hcec CEC handle
00271   * @retval HAL status
00272   */
00273 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00274 {
00275   /* Check the CEC handle allocation */
00276   if (hcec == NULL)
00277   {
00278     return HAL_ERROR;
00279   }
00280
00281   /* Check the parameters */
00282   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00283
00284   hcec->gState = HAL_CEC_STATE_BUSY;
00285
00286 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00287   if (hcec->MspDeInitCallback == NULL)
00288   {
00289     hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit  */
00290   }
00291
00292   /* DeInit the low level hardware */
00293   hcec->MspDeInitCallback(hcec);
00294
00295 #else
00296   /* DeInit the low level hardware */
00297   HAL_CEC_MspDeInit(hcec);
00298 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00299
00300   /* Disable the Peripheral */
00301   __HAL_CEC_DISABLE(hcec);
00302
00303   /* Clear Flags */
00304   __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
00305
00306   /* Disable the following CEC Transmission/Reception interrupts as
00307     * well as the following CEC Transmission/Reception Errors interrupts
00308     * Rx Byte Received IT
00309     * End of Reception IT
00310     * Rx overrun
00311     * Rx bit rising error
00312     * Rx short bit period error
00313     * Rx long bit period error
00314     * Rx missing acknowledge
00315     * Tx Byte Request IT
00316     * End of Transmission IT
00317     * Tx Missing Acknowledge IT
00318     * Tx-Error IT
00319     * Tx-Buffer Underrun IT
00320     * Tx arbitration lost   */
00321   __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
00322                        CEC_IER_TX_ALL_ERR);
00323
00324   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00325   hcec->gState = HAL_CEC_STATE_RESET;
00326   hcec->RxState = HAL_CEC_STATE_RESET;
00327
00328   /* Process Unlock */
00329   __HAL_UNLOCK(hcec);
00330
00331   return HAL_OK;
00332 }
00333
00334 /**
00335   * @brief Initializes the Own Address of the CEC device
00336   * @param hcec CEC handle
00337   * @param  CEC_OwnAddress The CEC own address.
00338   * @retval HAL status
00339   */
00340 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
00341 {
00342   /* Check the parameters */
00343   assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
00344
00345   if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
00346   {
00347     /* Process Locked */
00348     __HAL_LOCK(hcec);
00349
00350     hcec->gState = HAL_CEC_STATE_BUSY;
00351
00352     /* Disable the Peripheral */
00353     __HAL_CEC_DISABLE(hcec);
00354
00355     if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
00356     {
00357       hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
00358     }
00359     else
00360     {
00361       hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
00362     }
00363
00364     hcec->gState = HAL_CEC_STATE_READY;
00365     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00366
00367     /* Process Unlocked */
00368     __HAL_UNLOCK(hcec);
00369
00370     /* Enable the Peripheral */
00371     __HAL_CEC_ENABLE(hcec);
00372
00373     return  HAL_OK;
00374   }
00375   else
00376   {
00377     return HAL_BUSY;
00378   }
00379 }
00380
00381 /**
00382   * @brief CEC MSP Init
00383   * @param hcec CEC handle
00384   * @retval None
00385   */
00386 __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00387 {
00388   /* Prevent unused argument(s) compilation warning */
00389   UNUSED(hcec);
00390   /* NOTE : This function should not be modified, when the callback is needed,
00391             the HAL_CEC_MspInit can be implemented in the user file
00392    */
00393 }
00394
00395 /**
00396   * @brief CEC MSP DeInit
00397   * @param hcec CEC handle
00398   * @retval None
00399   */
00400 __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00401 {
00402   /* Prevent unused argument(s) compilation warning */
00403   UNUSED(hcec);
00404   /* NOTE : This function should not be modified, when the callback is needed,
00405             the HAL_CEC_MspDeInit can be implemented in the user file
00406    */
00407 }
00408 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00409 /**
00410   * @brief  Register a User CEC Callback
00411   *         To be used instead of the weak predefined callback
00412   * @param  hcec CEC handle
00413   * @param  CallbackID ID of the callback to be registered
00414   *         This parameter can be one of the following values:
00415   *          @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
00416   *          @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
00417   *          @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
00418   *          @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
00419   * @param  pCallback pointer to the Callback function
00420   * @retval HAL status
00421   */
00422 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
00423                                            pCEC_CallbackTypeDef pCallback)
00424 {
00425   HAL_StatusTypeDef status = HAL_OK;
00426
00427   if (pCallback == NULL)
00428   {
00429     /* Update the error code */
00430     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00431     return HAL_ERROR;
00432   }
00433   /* Process locked */
00434   __HAL_LOCK(hcec);
00435
00436   if (hcec->gState == HAL_CEC_STATE_READY)
00437   {
00438     switch (CallbackID)
00439     {
00440       case HAL_CEC_TX_CPLT_CB_ID :
00441         hcec->TxCpltCallback = pCallback;
00442         break;
00443
00444       case HAL_CEC_ERROR_CB_ID :
00445         hcec->ErrorCallback = pCallback;
00446         break;
00447
00448       case HAL_CEC_MSPINIT_CB_ID :
00449         hcec->MspInitCallback = pCallback;
00450         break;
00451
00452       case HAL_CEC_MSPDEINIT_CB_ID :
00453         hcec->MspDeInitCallback = pCallback;
00454         break;
00455
00456       default :
00457         /* Update the error code */
00458         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00459         /* Return error status */
00460         status =  HAL_ERROR;
00461         break;
00462     }
00463   }
00464   else if (hcec->gState == HAL_CEC_STATE_RESET)
00465   {
00466     switch (CallbackID)
00467     {
00468       case HAL_CEC_MSPINIT_CB_ID :
00469         hcec->MspInitCallback = pCallback;
00470         break;
00471
00472       case HAL_CEC_MSPDEINIT_CB_ID :
00473         hcec->MspDeInitCallback = pCallback;
00474         break;
00475
00476       default :
00477         /* Update the error code */
00478         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00479         /* Return error status */
00480         status =  HAL_ERROR;
00481         break;
00482     }
00483   }
00484   else
00485   {
00486     /* Update the error code */
00487     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00488     /* Return error status */
00489     status =  HAL_ERROR;
00490   }
00491
00492   /* Release Lock */
00493   __HAL_UNLOCK(hcec);
00494
00495   return status;
00496 }
00497
00498 /**
00499   * @brief  Unregister an CEC Callback
00500   *         CEC callabck is redirected to the weak predefined callback
00501   * @param hcec uart handle
00502   * @param CallbackID ID of the callback to be unregistered
00503   *         This parameter can be one of the following values:
00504   *          @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
00505   *          @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
00506   *          @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
00507   *          @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
00508   * @retval status
00509   */
00510 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
00511 {
00512   HAL_StatusTypeDef status = HAL_OK;
00513
00514   /* Process locked */
00515   __HAL_LOCK(hcec);
00516
00517   if (hcec->gState == HAL_CEC_STATE_READY)
00518   {
00519     switch (CallbackID)
00520     {
00521       case HAL_CEC_TX_CPLT_CB_ID :
00522         hcec->TxCpltCallback = HAL_CEC_TxCpltCallback;  /* Legacy weak  TxCpltCallback */
00523         break;
00524
00525       case HAL_CEC_ERROR_CB_ID :
00526         hcec->ErrorCallback = HAL_CEC_ErrorCallback;  /* Legacy weak ErrorCallback   */
00527         break;
00528
00529       case HAL_CEC_MSPINIT_CB_ID :
00530         hcec->MspInitCallback = HAL_CEC_MspInit;
00531         break;
00532
00533       case HAL_CEC_MSPDEINIT_CB_ID :
00534         hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
00535         break;
00536
00537       default :
00538         /* Update the error code */
00539         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00540         /* Return error status */
00541         status =  HAL_ERROR;
00542         break;
00543     }
00544   }
00545   else if (hcec->gState == HAL_CEC_STATE_RESET)
00546   {
00547     switch (CallbackID)
00548     {
00549       case HAL_CEC_MSPINIT_CB_ID :
00550         hcec->MspInitCallback = HAL_CEC_MspInit;
00551         break;
00552
00553       case HAL_CEC_MSPDEINIT_CB_ID :
00554         hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
00555         break;
00556
00557       default :
00558         /* Update the error code */
00559         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00560         /* Return error status */
00561         status =  HAL_ERROR;
00562         break;
00563     }
00564   }
00565   else
00566   {
00567     /* Update the error code */
00568     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00569     /* Return error status */
00570     status =  HAL_ERROR;
00571   }
00572
00573   /* Release Lock */
00574   __HAL_UNLOCK(hcec);
00575
00576   return status;
00577 }
00578
00579 /**
00580   * @brief  Register CEC RX complete Callback
00581   *         To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
00582   * @param  hcec CEC handle
00583   * @param  pCallback pointer to the Rx transfer compelete Callback function
00584   * @retval HAL status
00585   */
00586 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
00587 {
00588   HAL_StatusTypeDef status = HAL_OK;
00589
00590   if (pCallback == NULL)
00591   {
00592     /* Update the error code */
00593     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00594     return HAL_ERROR;
00595   }
00596   /* Process locked */
00597   __HAL_LOCK(hcec);
00598
00599   if (HAL_CEC_STATE_READY == hcec->RxState)
00600   {
00601     hcec->RxCpltCallback = pCallback;
00602   }
00603   else
00604   {
00605     /* Update the error code */
00606     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00607     /* Return error status */
00608     status =  HAL_ERROR;
00609   }
00610
00611   /* Release Lock */
00612   __HAL_UNLOCK(hcec);
00613   return status;
00614 }
00615
00616 /**
00617   * @brief  UnRegister CEC RX complete Callback
00618   *         CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
00619   * @param  hcec CEC handle
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
00623 {
00624   HAL_StatusTypeDef status = HAL_OK;
00625
00626   /* Process locked */
00627   __HAL_LOCK(hcec);
00628
00629   if (HAL_CEC_STATE_READY == hcec->RxState)
00630   {
00631     hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak  CEC RxCpltCallback  */
00632   }
00633   else
00634   {
00635     /* Update the error code */
00636     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00637     /* Return error status */
00638     status =  HAL_ERROR;
00639   }
00640
00641   /* Release Lock */
00642   __HAL_UNLOCK(hcec);
00643   return status;
00644 }
00645 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00646
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00652   *  @brief CEC Transmit/Receive functions
00653   *
00654 @verbatim
00655  ===============================================================================
00656                       ##### IO operation functions #####
00657  ===============================================================================
00658     This subsection provides a set of functions allowing to manage the CEC data transfers.
00659
00660     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00661         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00662
00663     (#) The communication is performed using Interrupts.
00664            These API's return the HAL status.
00665            The end of the data processing will be indicated through the
00666            dedicated CEC IRQ when using Interrupt mode.
00667            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00668            will be executed respectively at the end of the transmit or Receive process
00669            The HAL_CEC_ErrorCallback() user callback will be executed when a communication
00670            error is detected
00671
00672     (#) API's with Interrupt are :
00673          (+) HAL_CEC_Transmit_IT()
00674          (+) HAL_CEC_IRQHandler()
00675
00676     (#) A set of User Callbacks are provided:
00677          (+) HAL_CEC_TxCpltCallback()
00678          (+) HAL_CEC_RxCpltCallback()
00679          (+) HAL_CEC_ErrorCallback()
00680
00681 @endverbatim
00682   * @{
00683   */
00684
00685 /**
00686   * @brief Send data in interrupt mode
00687   * @param hcec CEC handle
00688   * @param InitiatorAddress Initiator address
00689   * @param DestinationAddress destination logical address
00690   * @param pData pointer to input byte data buffer
00691   * @param Size amount of data to be sent in bytes (without counting the header).
00692   *              0 means only the header is sent (ping operation).
00693   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00694   * @retval HAL status
00695   */
00696 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
00697                                       uint8_t *pData, uint32_t Size)
00698 {
00699   /* if the IP isn't already busy and if there is no previous transmission
00700      already pending due to arbitration lost */
00701   if (hcec->gState == HAL_CEC_STATE_READY)
00702   {
00703     if ((pData == NULL) && (Size > 0U))
00704     {
00705       return  HAL_ERROR;
00706     }
00707
00708     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00709     assert_param(IS_CEC_ADDRESS(InitiatorAddress));
00710     assert_param(IS_CEC_MSGSIZE(Size));
00711
00712     /* Process Locked */
00713     __HAL_LOCK(hcec);
00714     hcec->pTxBuffPtr = pData;
00715     hcec->gState = HAL_CEC_STATE_BUSY_TX;
00716     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00717
00718     /* initialize the number of bytes to send,
00719       * 0 means only one header is sent (ping operation) */
00720     hcec->TxXferCount = (uint16_t)Size;
00721
00722     /* in case of no payload (Size = 0), sender is only pinging the system;
00723        Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00724     if (Size == 0U)
00725     {
00726       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00727     }
00728
00729     /* send header block */
00730     hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
00731
00732     /* Set TX Start of Message  (TXSOM) bit */
00733     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00734
00735     /* Process Unlocked */
00736     __HAL_UNLOCK(hcec);
00737
00738     return HAL_OK;
00739
00740   }
00741   else
00742   {
00743     return HAL_BUSY;
00744   }
00745 }
00746
00747 /**
00748   * @brief Get size of the received frame.
00749   * @param hcec CEC handle
00750   * @retval Frame size
00751   */
00752 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
00753 {
00754   return hcec->RxXferSize;
00755 }
00756
00757 /**
00758   * @brief Change Rx Buffer.
00759   * @param hcec CEC handle
00760   * @param Rxbuffer Rx Buffer
00761   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
00762   * @retval Frame size
00763   */
00764 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
00765 {
00766   hcec->Init.RxBuffer = Rxbuffer;
00767 }
00768
00769 /**
00770   * @brief This function handles CEC interrupt requests.
00771   * @param hcec CEC handle
00772   * @retval None
00773   */
00774 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00775 {
00776
00777   /* save interrupts register for further error or interrupts handling purposes */
00778   uint32_t reg;
00779   reg = hcec->Instance->ISR;
00780
00781
00782   /* ----------------------------Arbitration Lost Management----------------------------------*/
00783   /* CEC TX arbitration error interrupt occurred --------------------------------------*/
00784   if ((reg & CEC_FLAG_ARBLST) != 0U)
00785   {
00786     hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
00787     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00788   }
00789
00790   /* ----------------------------Rx Management----------------------------------*/
00791   /* CEC RX byte received interrupt  ---------------------------------------------------*/
00792   if ((reg & CEC_FLAG_RXBR) != 0U)
00793   {
00794     /* reception is starting */
00795     hcec->RxState = HAL_CEC_STATE_BUSY_RX;
00796     hcec->RxXferSize++;
00797     /* read received byte */
00798     *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
00799     hcec->Init.RxBuffer++;
00800     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
00801   }
00802
00803   /* CEC RX end received interrupt  ---------------------------------------------------*/
00804   if ((reg & CEC_FLAG_RXEND) != 0U)
00805   {
00806     /* clear IT */
00807     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00808
00809     /* Rx process is completed, restore hcec->RxState to Ready */
00810     hcec->RxState = HAL_CEC_STATE_READY;
00811     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00812     hcec->Init.RxBuffer -= hcec->RxXferSize;
00813 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00814     hcec->RxCpltCallback(hcec, hcec->RxXferSize);
00815 #else
00816     HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
00817 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00818     hcec->RxXferSize = 0U;
00819   }
00820
00821   /* ----------------------------Tx Management----------------------------------*/
00822   /* CEC TX byte request interrupt ------------------------------------------------*/
00823   if ((reg & CEC_FLAG_TXBR) != 0U)
00824   {
00825     if (hcec->TxXferCount == 0U)
00826     {
00827       /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00828       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00829       hcec->Instance->TXDR = *hcec->pTxBuffPtr;
00830       hcec->pTxBuffPtr++;
00831     }
00832     else
00833     {
00834       hcec->Instance->TXDR = *hcec->pTxBuffPtr;
00835       hcec->pTxBuffPtr++;
00836       hcec->TxXferCount--;
00837     }
00838     /* clear Tx-Byte request flag */
00839     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00840   }
00841
00842   /* CEC TX end interrupt ------------------------------------------------*/
00843   if ((reg & CEC_FLAG_TXEND) != 0U)
00844   {
00845     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
00846
00847     /* Tx process is ended, restore hcec->gState to Ready */
00848     hcec->gState = HAL_CEC_STATE_READY;
00849     /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00850     start again the Transmission under the Tx call back API */
00851     __HAL_UNLOCK(hcec);
00852     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00853 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00854     hcec->TxCpltCallback(hcec);
00855 #else
00856     HAL_CEC_TxCpltCallback(hcec);
00857 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00858   }
00859
00860   /* ----------------------------Rx/Tx Error Management----------------------------------*/
00861   if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
00862               CEC_ISR_TXACKE)) != 0U)
00863   {
00864     hcec->ErrorCode = reg;
00865     __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
00866                          HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
00867
00868
00869     if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
00870     {
00871       hcec->Init.RxBuffer -= hcec->RxXferSize;
00872       hcec->RxXferSize = 0U;
00873       hcec->RxState = HAL_CEC_STATE_READY;
00874     }
00875     else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
00876     {
00877       /* Set the CEC state ready to be able to start again the process */
00878       hcec->gState = HAL_CEC_STATE_READY;
00879     }
00880     else
00881     {
00882       /* Nothing todo*/
00883     }
00884 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00885     hcec->ErrorCallback(hcec);
00886 #else
00887     /* Error  Call Back */
00888     HAL_CEC_ErrorCallback(hcec);
00889 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00890   }
00891   else
00892   {
00893     /* Nothing todo*/
00894   }
00895 }
00896
00897 /**
00898   * @brief Tx Transfer completed callback
00899   * @param hcec CEC handle
00900   * @retval None
00901   */
00902 __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00903 {
00904   /* Prevent unused argument(s) compilation warning */
00905   UNUSED(hcec);
00906   /* NOTE : This function should not be modified, when the callback is needed,
00907             the HAL_CEC_TxCpltCallback can be implemented in the user file
00908    */
00909 }
00910
00911 /**
00912   * @brief Rx Transfer completed callback
00913   * @param hcec CEC handle
00914   * @param RxFrameSize Size of frame
00915   * @retval None
00916   */
00917 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
00918 {
00919   /* Prevent unused argument(s) compilation warning */
00920   UNUSED(hcec);
00921   UNUSED(RxFrameSize);
00922   /* NOTE : This function should not be modified, when the callback is needed,
00923             the HAL_CEC_RxCpltCallback can be implemented in the user file
00924    */
00925 }
00926
00927 /**
00928   * @brief CEC error callbacks
00929   * @param hcec CEC handle
00930   * @retval None
00931   */
00932 __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00933 {
00934   /* Prevent unused argument(s) compilation warning */
00935   UNUSED(hcec);
00936   /* NOTE : This function should not be modified, when the callback is needed,
00937             the HAL_CEC_ErrorCallback can be implemented in the user file
00938    */
00939 }
00940 /**
00941   * @}
00942   */
00943
00944 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00945   *  @brief   CEC control functions
00946   *
00947 @verbatim
00948  ===============================================================================
00949                       ##### Peripheral Control function #####
00950  ===============================================================================
00951     [..]
00952     This subsection provides a set of functions allowing to control the CEC.
00953      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00954      (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
00955 @endverbatim
00956   * @{
00957   */
00958 /**
00959   * @brief return the CEC state
00960   * @param hcec pointer to a CEC_HandleTypeDef structure that contains
00961   *              the configuration information for the specified CEC module.
00962   * @retval HAL state
00963   */
00964 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00965 {
00966   uint32_t temp1, temp2;
00967   temp1 = hcec->gState;
00968   temp2 = hcec->RxState;
00969
00970   return (HAL_CEC_StateTypeDef)(temp1 | temp2);
00971 }
00972
00973 /**
00974   * @brief  Return the CEC error code
00975   * @param  hcec  pointer to a CEC_HandleTypeDef structure that contains
00976   *              the configuration information for the specified CEC.
00977   * @retval CEC Error Code
00978   */
00979 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00980 {
00981   return hcec->ErrorCode;
00982 }
00983
00984 /**
00985   * @}
00986   */
00987
00988 /**
00989   * @}
00990   */
00991 #endif /* CEC */
00992 #endif /* HAL_CEC_MODULE_ENABLED */
00993 /**
00994   * @}
00995   */
00996
00997 /**
00998   * @}
00999   */
01000
01001 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cec.h Source File

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stm32h7xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CEC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CEC_H
00022 #define STM32H7xx_HAL_CEC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (CEC)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup CEC
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup CEC_Exported_Types CEC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief CEC Init Structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00052                                               It can be one of @ref CEC_Signal_Free_Time
00053                                               and belongs to the set {0,...,7} where
00054                                               0x0 is the default configuration
00055                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
00056
00057   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00058                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
00059                                               or CEC_EXTENDED_TOLERANCE */
00060
00061   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
00062                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00063                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
00064
00065   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
00066                                               CEC line upon Bit Rising Error detection.
00067                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00068                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
00069
00070   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
00071                                               CEC line upon Long Bit Period Error detection.
00072                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
00073                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
00074
00075   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
00076                                               upon an error detected on a broadcast message.
00077
00078                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
00079
00080                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00081                                                  a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
00082                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00083                                                  b) LBPE detection: error-bit generation on the CEC line
00084                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00085
00086                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00087                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
00088                                                  there is no error-bit generation in case of Short Bit Period Error detection in
00089                                                  a broadcast message while LSTN bit is set. */
00090
00091   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
00092                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00093                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
00094
00095   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
00096
00097                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
00098                                                 own address (OAR). Messages addressed to different destination are ignored.
00099                                                 Broadcast messages are always received.
00100
00101                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
00102                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
00103                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
00104
00105   uint16_t  OwnAddress;                 /*!< Own addresses configuration
00106                                              This parameter can be a value of @ref CEC_OWN_ADDRESS */
00107
00108   uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */
00109
00110
00111 } CEC_InitTypeDef;
00112
00113 /**
00114   * @brief HAL CEC State definition
00115   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
00116   *        - gState contains CEC state information related to global Handle management
00117   *          and also information related to Tx operations.
00118   *          gState value coding follow below described bitmap :
00119   *          b7 (not used)
00120   *             x  : Should be set to 0
00121   *          b6  Error information
00122   *             0  : No Error
00123   *             1  : Error
00124   *          b5     IP initilisation status
00125   *             0  : Reset (IP not initialized)
00126   *             1  : Init done (IP initialized. HAL CEC Init function already called)
00127   *          b4-b3  (not used)
00128   *             xx : Should be set to 00
00129   *          b2     Intrinsic process state
00130   *             0  : Ready
00131   *             1  : Busy (IP busy with some configuration or internal operations)
00132   *          b1     (not used)
00133   *             x  : Should be set to 0
00134   *          b0     Tx state
00135   *             0  : Ready (no Tx operation ongoing)
00136   *             1  : Busy (Tx operation ongoing)
00137   *        - RxState contains information related to Rx operations.
00138   *          RxState value coding follow below described bitmap :
00139   *          b7-b6  (not used)
00140   *             xx : Should be set to 00
00141   *          b5     IP initilisation status
00142   *             0  : Reset (IP not initialized)
00143   *             1  : Init done (IP initialized)
00144   *          b4-b2  (not used)
00145   *            xxx : Should be set to 000
00146   *          b1     Rx state
00147   *             0  : Ready (no Rx operation ongoing)
00148   *             1  : Busy (Rx operation ongoing)
00149   *          b0     (not used)
00150   *             x  : Should be set to 0.
00151   */
00152 typedef uint32_t HAL_CEC_StateTypeDef;
00153
00154 /**
00155   * @brief  CEC handle Structure definition
00156   */
00157 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00158 typedef struct __CEC_HandleTypeDef
00159 #else
00160 typedef struct
00161 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00162 {
00163   CEC_TypeDef             *Instance;      /*!< CEC registers base address */
00164
00165   CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
00166
00167   uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
00168
00169   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
00170
00171   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
00172
00173   HAL_LockTypeDef         Lock;           /*!< Locking object */
00174
00175   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
00176                                                and also related to Tx operations.
00177                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00178
00179   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
00180                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00181
00182   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
00183                                                in case error is reported */
00184
00185 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00186   void (* TxCpltCallback)(struct __CEC_HandleTypeDef
00187                           *hcec);                                /*!< CEC Tx Transfer completed callback */
00188   void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
00189                           uint32_t RxFrameSize);          /*!< CEC Rx Transfer completed callback */
00190   void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec);                                 /*!< CEC error callback */
00191
00192   void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec);               /*!< CEC Msp Init callback              */
00193   void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec);             /*!< CEC Msp DeInit callback            */
00194
00195 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
00196 } CEC_HandleTypeDef;
00197
00198 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00199 /**
00200   * @brief  HAL CEC Callback ID enumeration definition
00201   */
00202 typedef enum
00203 {
00204   HAL_CEC_TX_CPLT_CB_ID      = 0x00U,    /*!< CEC Tx Transfer completed callback ID  */
00205   HAL_CEC_RX_CPLT_CB_ID      = 0x01U,    /*!< CEC Rx Transfer completed callback ID  */
00206   HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback ID                 */
00207   HAL_CEC_MSPINIT_CB_ID      = 0x03U,    /*!< CEC Msp Init callback ID               */
00208   HAL_CEC_MSPDEINIT_CB_ID    = 0x04U     /*!< CEC Msp DeInit callback ID             */
00209 } HAL_CEC_CallbackIDTypeDef;
00210
00211 /**
00212   * @brief  HAL CEC Callback pointer definition
00213   */
00214 typedef  void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec);  /*!< pointer to an CEC callback function */
00215 typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
00216                                         uint32_t RxFrameSize);  /*!< pointer to an Rx Transfer completed callback function */
00217 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00218 /**
00219   * @}
00220   */
00221
00222 /* Exported constants --------------------------------------------------------*/
00223 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00224   * @{
00225   */
00226 /** @defgroup CEC_State_Definition CEC State Code Definition
00227   * @{
00228   */
00229 #define   HAL_CEC_STATE_RESET      ((uint32_t)0x00000000)   /*!< Peripheral is not yet Initialized
00230                                                                  Value is allowed for gState and RxState  */
00231 #define   HAL_CEC_STATE_READY      ((uint32_t)0x00000020)   /*!< Peripheral Initialized and ready for use
00232                                                                  Value is allowed for gState and RxState  */
00233 #define   HAL_CEC_STATE_BUSY       ((uint32_t)0x00000024)   /*!< an internal process is ongoing
00234                                                                  Value is allowed for gState only         */
00235 #define   HAL_CEC_STATE_BUSY_RX    ((uint32_t)0x00000022)   /*!< Data Reception process is ongoing
00236                                                                  Value is allowed for RxState only        */
00237 #define   HAL_CEC_STATE_BUSY_TX    ((uint32_t)0x00000021)   /*!< Data Transmission process is ongoing
00238                                                                  Value is allowed for gState only         */
00239 #define   HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)   /*!< an internal process is ongoing
00240                                                                  Value is allowed for gState only         */
00241 #define   HAL_CEC_STATE_ERROR      ((uint32_t)0x00000050)   /*!< Error Value is allowed for gState only   */
00242 /**
00243   * @}
00244   */
00245 /** @defgroup CEC_Error_Code CEC Error Code
00246   * @{
00247   */
00248 #define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */
00249 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
00250 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
00251 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
00252 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
00253 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
00254 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
00255 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
00256 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
00257 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
00258 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00259 #define  HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error  */
00260 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00266   * @{
00267   */
00268 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)
00269 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)
00270 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)
00271 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)
00272 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)
00273 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)
00274 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)
00275 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00281   * @{
00282   */
00283 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)
00284 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00290   * @{
00291   */
00292 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)
00293 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00299   * @{
00300   */
00301 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00302 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00308   * @{
00309   */
00310 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00311 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00317   * @{
00318   */
00319 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)
00320 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00326   * @{
00327   */
00328 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)
00329 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00335   * @{
00336   */
00337 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)
00338 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00344   * @{
00345   */
00346 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00352   * @{
00353   */
00354 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
00360   * @{
00361   */
00362 #define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */
00363 #define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */
00364 #define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */
00365 #define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */
00366 #define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */
00367 #define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */
00368 #define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */
00369 #define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */
00370 #define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */
00371 #define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */
00372 #define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */
00373 #define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */
00374 #define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */
00375 #define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */
00376 #define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */
00377 #define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00383   * @{
00384   */
00385 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00386 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00387 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00388 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00389 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00390 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00391 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00392 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00393 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00394 #define CEC_IT_BRE                      CEC_IER_BREIE
00395 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00396 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00397 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00403   * @{
00404   */
00405 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00406 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00407 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00408 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00409 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00410 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00411 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00412 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00413 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00414 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00415 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00416 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00417 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00423   * @{
00424   */
00425 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00426                                         CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00432   * @{
00433   */
00434 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00440   * @{
00441   */
00442 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 /* Exported macros -----------------------------------------------------------*/
00452 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00453   * @{
00454   */
00455
00456 /** @brief  Reset CEC handle gstate & RxState
00457   * @param  __HANDLE__ CEC handle.
00458   * @retval None
00459   */
00460 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00461 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00462                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00463                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00464                                                        (__HANDLE__)->MspInitCallback = NULL;           \
00465                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
00466                                                      } while(0)
00467 #else
00468 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00469                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00470                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00471                                                      } while(0)
00472 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00473 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00474   * @param  __HANDLE__ specifies the CEC Handle.
00475   * @param  __FLAG__ specifies the flag to check.
00476   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00477   *            @arg CEC_FLAG_TXERR: Tx Error.
00478   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00479   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00480   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00481   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00482   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00483   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00484   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00485   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00486   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00487   *            @arg CEC_FLAG_RXEND: End Of Reception.
00488   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00489   * @retval ITStatus
00490   */
00491 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00492
00493 /** @brief  Clears the interrupt or status flag when raised (write at 1)
00494   * @param  __HANDLE__ specifies the CEC Handle.
00495   * @param  __FLAG__ specifies the interrupt/status flag to clear.
00496   *        This parameter can be one of the following values:
00497   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00498   *            @arg CEC_FLAG_TXERR: Tx Error.
00499   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00500   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00501   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00502   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00503   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00504   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00505   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00506   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00507   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00508   *            @arg CEC_FLAG_RXEND: End Of Reception.
00509   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00510   * @retval none
00511   */
00512 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00513
00514 /** @brief  Enables the specified CEC interrupt.
00515   * @param  __HANDLE__ specifies the CEC Handle.
00516   * @param  __INTERRUPT__ specifies the CEC interrupt to enable.
00517   *          This parameter can be one of the following values:
00518   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00519   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00520   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00521   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00522   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00523   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00524   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00525   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00526   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00527   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00528   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00529   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00530   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00531   * @retval none
00532   */
00533 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00534
00535 /** @brief  Disables the specified CEC interrupt.
00536   * @param  __HANDLE__ specifies the CEC Handle.
00537   * @param  __INTERRUPT__ specifies the CEC interrupt to disable.
00538   *          This parameter can be one of the following values:
00539   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00540   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00541   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00542   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00543   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00544   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00545   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00546   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00547   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00548   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00549   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00550   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00551   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00552   * @retval none
00553   */
00554 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00555
00556 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00557   * @param  __HANDLE__ specifies the CEC Handle.
00558   * @param  __INTERRUPT__ specifies the CEC interrupt to check.
00559   *          This parameter can be one of the following values:
00560   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00561   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00562   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00563   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00564   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00565   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00566   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00567   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00568   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00569   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00570   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00571   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00572   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00573   * @retval FlagStatus
00574   */
00575 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00576
00577 /** @brief  Enables the CEC device
00578   * @param  __HANDLE__ specifies the CEC Handle.
00579   * @retval none
00580   */
00581 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00582
00583 /** @brief  Disables the CEC device
00584   * @param  __HANDLE__ specifies the CEC Handle.
00585   * @retval none
00586   */
00587 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00588
00589 /** @brief  Set Transmission Start flag
00590   * @param  __HANDLE__ specifies the CEC Handle.
00591   * @retval none
00592   */
00593 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00594
00595 /** @brief  Set Transmission End flag
00596   * @param  __HANDLE__ specifies the CEC Handle.
00597   * @retval none
00598   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00599   */
00600 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00601
00602 /** @brief  Get Transmission Start flag
00603   * @param  __HANDLE__ specifies the CEC Handle.
00604   * @retval FlagStatus
00605   */
00606 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00607
00608 /** @brief  Get Transmission End flag
00609   * @param  __HANDLE__ specifies the CEC Handle.
00610   * @retval FlagStatus
00611   */
00612 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00613
00614 /** @brief  Clear OAR register
00615   * @param  __HANDLE__ specifies the CEC Handle.
00616   * @retval none
00617   */
00618 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00619
00620 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00621   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00622   * @param  __HANDLE__ specifies the CEC Handle.
00623   * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
00624   * @retval none
00625   */
00626 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
00627
00628 /**
00629   * @}
00630   */
00631
00632 /* Exported functions --------------------------------------------------------*/
00633 /** @addtogroup CEC_Exported_Functions
00634   * @{
00635   */
00636
00637 /** @addtogroup CEC_Exported_Functions_Group1
00638   * @{
00639   */
00640 /* Initialization and de-initialization functions  ****************************/
00641 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00642 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00643 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
00644 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00645 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00646
00647 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00648 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
00649                                            pCEC_CallbackTypeDef pCallback);
00650 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
00651
00652 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
00653 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
00654 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00655 /**
00656   * @}
00657   */
00658
00659 /** @addtogroup CEC_Exported_Functions_Group2
00660   * @{
00661   */
00662 /* I/O operation functions  ***************************************************/
00663 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
00664                                       uint8_t *pData, uint32_t Size);
00665 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
00666 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
00667 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00668 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00669 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
00670 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00671 /**
00672   * @}
00673   */
00674
00675 /** @addtogroup CEC_Exported_Functions_Group3
00676   * @{
00677   */
00678 /* Peripheral State functions  ************************************************/
00679 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00680 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00681 /**
00682   * @}
00683   */
00684
00685 /**
00686   * @}
00687   */
00688
00689 /* Private types -------------------------------------------------------------*/
00690 /** @defgroup CEC_Private_Types CEC Private Types
00691   * @{
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 /* Private variables ---------------------------------------------------------*/
00699 /** @defgroup CEC_Private_Variables CEC Private Variables
00700   * @{
00701   */
00702
00703 /**
00704   * @}
00705   */
00706
00707 /* Private constants ---------------------------------------------------------*/
00708 /** @defgroup CEC_Private_Constants CEC Private Constants
00709   * @{
00710   */
00711
00712 /**
00713   * @}
00714   */
00715
00716 /* Private macros ------------------------------------------------------------*/
00717 /** @defgroup CEC_Private_Macros CEC Private Macros
00718   * @{
00719   */
00720
00721 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00722
00723 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00724                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00725
00726 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00727                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00728
00729 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00730                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00731
00732 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00733                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00734
00735 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00736                                                                        ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00737
00738 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00739                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00740
00741 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00742                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00743
00744 /** @brief Check CEC message size.
00745   *       The message size is the payload size: without counting the header,
00746   *       it varies from 0 byte (ping operation, one header only, no payload) to
00747   *       15 bytes (1 opcode and up to 14 operands following the header).
00748   * @param  __SIZE__ CEC message size.
00749   * @retval Test result (TRUE or FALSE).
00750   */
00751 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
00752
00753 /** @brief Check CEC device Own Address Register (OAR) setting.
00754   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00755   * @param  __ADDRESS__ CEC own address.
00756   * @retval Test result (TRUE or FALSE).
00757   */
00758 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
00759
00760 /** @brief Check CEC initiator or destination logical address setting.
00761   *        Initiator and destination addresses are coded over 4 bits.
00762   * @param  __ADDRESS__ CEC initiator or logical address.
00763   * @retval Test result (TRUE or FALSE).
00764   */
00765 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
00766 /**
00767   * @}
00768   */
00769 /* Private functions ---------------------------------------------------------*/
00770 /** @defgroup CEC_Private_Functions CEC Private Functions
00771   * @{
00772   */
00773
00774 /**
00775   * @}
00776   */
00777
00778 /**
00779   * @}
00780   */
00781
00782 /**
00783   * @}
00784   */
00785
00786 #endif /* CEC */
00787
00788 #ifdef __cplusplus
00789 }
00790 #endif
00791
00792 #endif /* STM32H7xxHAL_CEC_H */
00793
00794 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_comp.c Source File

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stm32h7xx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the COMP peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Start/Stop operation functions in polling mode
00010   *           + Start/Stop operation functions in interrupt mode
00011   *           + Peripheral control functions
00012   *           + Peripheral state functions
00013   @verbatim
00014   ================================================================================
00015                    ##### COMP Peripheral features #####
00016   ================================================================================
00017
00018   [..]
00019       The STM32H7xx device family integrates two analog comparators instances
00020       COMP1 and COMP2:
00021       (#) The COMP input minus (inverting input) and input plus (non inverting input)
00022           can be set to internal references or to GPIO pins
00023           (refer to GPIO list in reference manual).
00024
00025       (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
00026           and can be redirected to other peripherals: GPIO pins (in mode
00027           alternate functions for comparator), timers.
00028           (refer to GPIO list in reference manual).
00029
00030       (#) Pairs of comparators instances can be combined in window mode
00031           (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00032
00033       (#) The comparators have interrupt capability through the EXTI controller
00034           with wake-up from sleep and stop modes:
00035           (++) COMP1 is internally connected to EXTI Line 20
00036           (++) COMP2 is internally connected to EXTI Line 21
00037
00038   [..]
00039           From the corresponding IRQ handler, the right interrupt source can be retrieved
00040           using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
00041
00042
00043
00044             ##### How to use this driver #####
00045   ================================================================================
00046   [..]
00047       This driver provides functions to configure and program the comparator instances of
00048       STM32H7xx devices.
00049
00050       To use the comparator, perform the following steps:
00051
00052       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00053       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00054            using HAL_GPIO_Init().
00055       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00056            using HAL_GPIO_Init().
00057       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00058            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00059            interrupt vector using HAL_NVIC_EnableIRQ() function.
00060
00061       (#) Configure the comparator using HAL_COMP_Init() function:
00062       (++) Select the input minus (inverting input)
00063       (++) Select the input plus (non-inverting input)
00064       (++) Select the hysteresis
00065       (++) Select the blanking source
00066       (++) Select the output polarity
00067       (++) Select the power mode
00068       (++) Select the window mode
00069       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00070           to enable internal control clock of the comparators.
00071           However, this is a legacy strategy.
00072           Therefore, for compatibility anticipation, it is recommended to
00073           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00074           In STM32H7,COMP clock enable  __HAL_RCC_COMP12_CLK_ENABLE() must
00075           be implemented by user in "HAL_COMP_MspInit()".
00076       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00077           function HAL_COMP_Init() with new input structure parameters values.
00078
00079       (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
00080           with the interrupt through NVIC of the CPU.
00081       Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
00082       mode will stay disabled.
00083
00084       (#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
00085           functions to manage comparator outputs(output level or events)
00086
00087       (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
00088           to disable the interrupt too.
00089
00090       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00091
00092       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00093           The only way to unlock the comparator is a device hardware reset.
00094
00095     *** Callback registration ***
00096     =============================================
00097     [..]
00098
00099      The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
00100      allows the user to configure dynamically the driver callbacks.
00101      Use Functions @ref HAL_COMP_RegisterCallback()
00102      to register an interrupt callback.
00103     [..]
00104
00105      Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
00106        (+) TriggerCallback       : callback for COMP trigger.
00107        (+) MspInitCallback       : callback for Msp Init.
00108        (+) MspDeInitCallback     : callback for Msp DeInit.
00109      This function takes as parameters the HAL peripheral handle, the Callback ID
00110      and a pointer to the user callback function.
00111     [..]
00112
00113      Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
00114      weak function.
00115     [..]
00116
00117      @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
00118      and the Callback ID.
00119      This function allows to reset following callbacks:
00120        (+) TriggerCallback       : callback for COMP trigger.
00121        (+) MspInitCallback       : callback for Msp Init.
00122        (+) MspDeInitCallback     : callback for Msp DeInit.
00123      [..]
00124
00125      By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
00126      all callbacks are set to the corresponding weak functions:
00127      example @ref HAL_COMP_TriggerCallback().
00128      Exception done for MspInit and MspDeInit functions that are
00129      reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
00130      these callbacks are null (not registered beforehand).
00131     [..]
00132
00133      If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
00134      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00135      [..]
00136
00137      Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
00138      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00139      in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
00140      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00141     [..]
00142
00143      Then, the user first registers the MspInit/MspDeInit user callbacks
00144      using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
00145      or @ref HAL_COMP_Init() function.
00146      [..]
00147
00148      When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
00149      not defined, the callback registration feature is not available and all callbacks
00150      are set to the corresponding weak functions.
00151
00152   @endverbatim
00153   ******************************************************************************
00154
00155   Table 1. COMP inputs and output for STM32H7xx devices
00156   +---------------------------------------------------------+
00157   |                |                |   COMP1   |   COMP2   |
00158   |----------------|----------------|-----------|-----------|
00159   |                | IO1            |    PB0    |    PE9    |
00160   | Input plus     | IO2            |    PB2    |    PE11   |
00161   |                |                |           |           |
00162   |----------------|----------------|-----------------------|
00163   |                | 1/4 VrefInt    | Available | Available |
00164   |                | 1/2 VrefInt    | Available | Available |
00165   |                | 3/4 VrefInt    | Available | Available |
00166   | Input minus    | VrefInt        | Available | Available |
00167   |                | DAC1 channel 1 | Available | Available |
00168   |                | DAC1 channel 2 | Available | Available |
00169   |                | IO1            |    PB1    |    PE10   |
00170   |                | IO2            |    PC4    |    PE7    |
00171   |                |                |           |           |
00172   |                |                |           |           |
00173   |                |                |           |           |
00174   +---------------------------------------------------------+
00175   | Output         |                |  PC5  (1) |  PE8  (1) |
00176   |                |                |  PE12 (1) |  PE13 (1) |
00177   |                |                |  TIM  (2) |  TIM  (2) |
00178   +---------------------------------------------------------+
00179   (1) GPIO must be set to alternate function for comparator
00180   (2) Comparators output to timers is set in timers instances.
00181
00182   ******************************************************************************
00183   * @attention
00184   *
00185   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00186   * All rights reserved.</center></h2>
00187   *
00188   * This software component is licensed by ST under BSD 3-Clause license,
00189   * the "License"; You may not use this file except in compliance with the
00190   * License. You may obtain a copy of the License at:
00191   *                        opensource.org/licenses/BSD-3-Clause
00192   *
00193   ******************************************************************************
00194   */
00195
00196 /* Includes ------------------------------------------------------------------*/
00197 #include "stm32h7xx_hal.h"
00198
00199 /** @addtogroup STM32H7xx_HAL_Driver
00200   * @{
00201   */
00202
00203 /** @defgroup COMP COMP
00204   * @brief COMP HAL module driver
00205   * @{
00206   */
00207
00208 #ifdef HAL_COMP_MODULE_ENABLED
00209
00210 /* Private typedef -----------------------------------------------------------*/
00211 /* Private define ------------------------------------------------------------*/
00212 /** @addtogroup COMP_Private_Constants
00213   * @{
00214   */
00215
00216 /* Delay for COMP startup time.                                               */
00217 /* Note: Delay required to reach propagation delay specification.             */
00218 /* Literal set to maximum value (refer to device datasheet,                   */
00219 /* parameter "tSTART").                                                       */
00220 /* Unit: us                                                                   */
00221 #define COMP_DELAY_STARTUP_US             (80UL)  /*!< Delay for COMP startup time */
00222
00223 /* Delay for COMP voltage scaler stabilization time.                          */
00224 /* Literal set to maximum value (refer to device datasheet,                   */
00225 /* parameter "tSTART_SCALER").                                                */
00226 /* Unit: us                                                                   */
00227 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)  /*!< Delay for COMP voltage scaler stabilization time */
00228
00229
00230 /**
00231   * @}
00232   */
00233
00234 /* Private macro -------------------------------------------------------------*/
00235 /* Private variables ---------------------------------------------------------*/
00236 /* Private function prototypes -----------------------------------------------*/
00237 /* Exported functions --------------------------------------------------------*/
00238
00239 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00240   * @{
00241   */
00242
00243 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00244  *  @brief    Initialization and de-initialization functions.
00245  *
00246 @verbatim
00247  ===============================================================================
00248               ##### Initialization and de-initialization functions #####
00249  ===============================================================================
00250     [..]  This section provides functions to initialize and de-initialize comparators
00251
00252 @endverbatim
00253   * @{
00254   */
00255
00256 /**
00257   * @brief  Initialize the COMP according to the specified
00258   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00259   * @note   If the selected comparator is locked, initialization can't be performed.
00260   *         To unlock the configuration, perform a system reset.
00261   * @param  hcomp COMP handle
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00265 {
00266   uint32_t tmp_csr ;
00267   uint32_t exti_line ;
00268   uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */
00269   __IO uint32_t wait_loop_index = 0UL;
00270
00271   HAL_StatusTypeDef status = HAL_OK;
00272
00273   /* Check the COMP handle allocation and lock status */
00274   if(hcomp == NULL)
00275   {
00276     status = HAL_ERROR;
00277   }
00278   else if(__HAL_COMP_IS_LOCKED(hcomp))
00279   {
00280     status = HAL_ERROR;
00281   }
00282   else
00283   {
00284     /* Check the parameters */
00285     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00286     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
00287     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
00288     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00289     assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
00290     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00291     assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
00292     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00293     assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
00294
00295     if(hcomp->State == HAL_COMP_STATE_RESET)
00296     {
00297       /* Allocate lock resource and initialize it */
00298       hcomp->Lock = HAL_UNLOCKED;
00299
00300           /* Set COMP error code to none */
00301       COMP_CLEAR_ERRORCODE(hcomp);
00302
00303 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00304      /* Init the COMP Callback settings */
00305       hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
00306
00307       if (hcomp->MspInitCallback == NULL)
00308       {
00309         hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
00310       }
00311
00312       /* Init the low level hardware */
00313       hcomp->MspInitCallback(hcomp);
00314 #else
00315          /* Init the low level hardware */
00316       HAL_COMP_MspInit(hcomp);
00317 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00318     }
00319     /* Memorize voltage scaler state before initialization */
00320     comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN);
00321
00322     /* Set COMP parameters */
00323     /*     Set INMSEL bits according to hcomp->Init.InvertingInput value       */
00324     /*     Set INPSEL bits according to hcomp->Init.NonInvertingInput value    */
00325     /*     Set BLANKING bits according to hcomp->Init.BlankingSrce value       */
00326     /*     Set HYST bits according to hcomp->Init.Hysteresis value             */
00327     /*     Set POLARITY bit according to hcomp->Init.OutputPol value           */
00328     /*     Set POWERMODE bits according to hcomp->Init.Mode value              */
00329
00330     tmp_csr = (hcomp->Init.InvertingInput    |  \
00331               hcomp->Init.NonInvertingInput  |  \
00332               hcomp->Init.BlankingSrce       |  \
00333               hcomp->Init.Hysteresis         |  \
00334               hcomp->Init.OutputPol          |  \
00335               hcomp->Init.Mode                );
00336
00337     /* Set parameters in COMP register */
00338     /* Note: Update all bits except read-only, lock and enable bits */
00339 #if defined (COMP_CFGRx_INP2SEL)
00340     MODIFY_REG(hcomp->Instance->CFGR,
00341                COMP_CFGRx_PWRMODE  | COMP_CFGRx_INMSEL   | COMP_CFGRx_INPSEL  |
00342                COMP_CFGRx_INP2SEL  | COMP_CFGRx_WINMODE  | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST    |
00343                COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN    | COMP_CFGRx_SCALEN,
00344                tmp_csr
00345               );
00346 #else
00347     MODIFY_REG(hcomp->Instance->CFGR,
00348                COMP_CFGRx_PWRMODE  | COMP_CFGRx_INMSEL   | COMP_CFGRx_INPSEL  |
00349                COMP_CFGRx_WINMODE  | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST    |
00350                COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN    | COMP_CFGRx_SCALEN,
00351                tmp_csr
00352               );
00353 #endif
00354     /* Set window mode */
00355     /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
00356     /*       instances. Therefore, this function can update another COMP      */
00357     /*       instance that the one currently selected.                        */
00358     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00359     {
00360       SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
00361     }
00362     else
00363     {
00364       CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
00365     }
00366     /* Delay for COMP scaler bridge voltage stabilization */
00367     /* Apply the delay if voltage scaler bridge is enabled for the first time */
00368     if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) &&
00369         (comp_voltage_scaler_initialized != 0UL)               )
00370     {
00371       /* Wait loop initialization and execution */
00372       /* Note: Variable divided by 2 to compensate partially                  */
00373       /*       CPU processing cycles.*/
00374
00375      wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL)));
00376
00377      while(wait_loop_index != 0UL)
00378      {
00379        wait_loop_index --;
00380      }
00381     }
00382
00383     /* Get the EXTI line corresponding to the selected COMP instance */
00384     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00385
00386     /* Manage EXTI settings */
00387     if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
00388     {
00389       /* Configure EXTI rising edge */
00390       if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
00391       {
00392         SET_BIT(EXTI->RTSR1, exti_line);
00393       }
00394       else
00395       {
00396         CLEAR_BIT(EXTI->RTSR1, exti_line);
00397       }
00398
00399       /* Configure EXTI falling edge */
00400       if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
00401       {
00402         SET_BIT(EXTI->FTSR1, exti_line);
00403       }
00404       else
00405       {
00406         CLEAR_BIT(EXTI->FTSR1, exti_line);
00407       }
00408
00409 #if !defined (DUAL_CORE)
00410       /* Clear COMP EXTI pending bit (if any) */
00411       WRITE_REG(EXTI->PR1, exti_line);
00412
00413
00414       /* Configure EXTI event mode */
00415       if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
00416       {
00417         SET_BIT(EXTI->EMR1, exti_line);
00418       }
00419       else
00420       {
00421         CLEAR_BIT(EXTI->EMR1, exti_line);
00422       }
00423
00424        /* Configure EXTI interrupt mode */
00425       if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
00426       {
00427         SET_BIT(EXTI->IMR1, exti_line);
00428       }
00429       else
00430       {
00431         CLEAR_BIT(EXTI->IMR1, exti_line);
00432       }
00433     }
00434     else
00435     {
00436       /* Disable EXTI event mode */
00437       CLEAR_BIT(EXTI->EMR1, exti_line);
00438
00439       /* Disable EXTI interrupt mode */
00440       CLEAR_BIT(EXTI->IMR1, exti_line);
00441 #endif
00442     }
00443     /* Set HAL COMP handle state */
00444     /* Note: Transition from state reset to state ready,                      */
00445     /*       otherwise (coming from state ready or busy) no state update.     */
00446     if (hcomp->State == HAL_COMP_STATE_RESET)
00447     {
00448
00449       hcomp->State = HAL_COMP_STATE_READY;
00450     }
00451
00452   }
00453
00454   return status;
00455 }
00456
00457 /**
00458   * @brief  DeInitialize the COMP peripheral.
00459   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00460   *         To unlock the configuration, perform a system reset.
00461   * @param  hcomp  COMP handle
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00465 {
00466   HAL_StatusTypeDef status = HAL_OK;
00467
00468   /* Check the COMP handle allocation and lock status */
00469   if(hcomp == NULL)
00470   {
00471     status = HAL_ERROR;
00472   }
00473   else if(__HAL_COMP_IS_LOCKED(hcomp))
00474   {
00475     status = HAL_ERROR;
00476   }
00477   else
00478   {
00479     /* Check the parameter */
00480     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00481
00482     /* Set COMP_CFGR register to reset value */
00483     WRITE_REG(hcomp->Instance->CFGR, 0x00000000UL);
00484
00485 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00486     if (hcomp->MspDeInitCallback == NULL)
00487     {
00488       hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
00489     }
00490
00491     /* DeInit the low level hardware */
00492     hcomp->MspDeInitCallback(hcomp);
00493 #else
00494     /* DeInit the low level hardware */
00495     HAL_COMP_MspDeInit(hcomp);
00496 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00497
00498     /* Set HAL COMP handle state */
00499     hcomp->State = HAL_COMP_STATE_RESET;
00500
00501     /* Release Lock */
00502     __HAL_UNLOCK(hcomp);
00503   }
00504
00505   return status;
00506 }
00507
00508 /**
00509   * @brief  Initialize the COMP MSP.
00510   * @param  hcomp COMP handle
00511   * @retval None
00512   */
00513 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00514 {
00515   /* Prevent unused argument(s) compilation warning */
00516   UNUSED(hcomp);
00517   /* NOTE : This function should not be modified, when the callback is needed,
00518             the HAL_COMP_MspInit could be implemented in the user file
00519    */
00520 }
00521
00522 /**
00523   * @brief  DeInitialize the COMP MSP.
00524   * @param  hcomp COMP handle
00525   * @retval None
00526   */
00527 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00528 {
00529   /* Prevent unused argument(s) compilation warning */
00530    UNUSED(hcomp);
00531   /* NOTE : This function should not be modified, when the callback is needed,
00532             the HAL_COMP_MspDeInit could be implemented in the user file
00533    */
00534 }
00535
00536 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00537 /**
00538   * @brief  Register a User COMP Callback
00539   *         To be used instead of the weak predefined callback
00540   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00541   *                the configuration information for the specified COMP.
00542   * @param  CallbackID ID of the callback to be registered
00543   *         This parameter can be one of the following values:
00544   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00545   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00546   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00547   * @param  pCallback pointer to the Callback function
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
00551 {
00552   HAL_StatusTypeDef status = HAL_OK;
00553
00554   if (pCallback == NULL)
00555   {
00556     /* Update the error code */
00557     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00558
00559     return HAL_ERROR;
00560   }
00561
00562   if (HAL_COMP_STATE_READY == hcomp->State)
00563   {
00564     switch (CallbackID)
00565     {
00566       case HAL_COMP_TRIGGER_CB_ID :
00567         hcomp->TriggerCallback = pCallback;
00568         break;
00569
00570       case HAL_COMP_MSPINIT_CB_ID :
00571         hcomp->MspInitCallback = pCallback;
00572         break;
00573
00574       case HAL_COMP_MSPDEINIT_CB_ID :
00575         hcomp->MspDeInitCallback = pCallback;
00576         break;
00577
00578       default :
00579         /* Update the error code */
00580         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00581
00582         /* Return error status */
00583         status = HAL_ERROR;
00584         break;
00585     }
00586   }
00587   else if (HAL_COMP_STATE_RESET == hcomp->State)
00588   {
00589     switch (CallbackID)
00590     {
00591       case HAL_COMP_MSPINIT_CB_ID :
00592         hcomp->MspInitCallback = pCallback;
00593         break;
00594
00595       case HAL_COMP_MSPDEINIT_CB_ID :
00596         hcomp->MspDeInitCallback = pCallback;
00597         break;
00598
00599       default :
00600         /* Update the error code */
00601         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00602
00603         /* Return error status */
00604         status = HAL_ERROR;
00605         break;
00606     }
00607   }
00608   else
00609   {
00610     /* Update the error code */
00611     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00612
00613     /* Return error status */
00614     status =  HAL_ERROR;
00615   }
00616
00617   return status;
00618 }
00619
00620 /**
00621   * @brief  Unregister a COMP Callback
00622   *         COMP callback is redirected to the weak predefined callback
00623   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00624   *                the configuration information for the specified COMP.
00625   * @param  CallbackID ID of the callback to be unregistered
00626   *         This parameter can be one of the following values:
00627   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00628   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00629   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00630   * @retval HAL status
00631   */
00632 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
00633 {
00634   HAL_StatusTypeDef status = HAL_OK;
00635
00636   if (HAL_COMP_STATE_READY == hcomp->State)
00637   {
00638     switch (CallbackID)
00639     {
00640       case HAL_COMP_TRIGGER_CB_ID :
00641         hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
00642         break;
00643
00644       case HAL_COMP_MSPINIT_CB_ID :
00645         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00646         break;
00647
00648       case HAL_COMP_MSPDEINIT_CB_ID :
00649         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00650         break;
00651
00652       default :
00653         /* Update the error code */
00654         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00655
00656         /* Return error status */
00657         status =  HAL_ERROR;
00658         break;
00659     }
00660   }
00661   else if (HAL_COMP_STATE_RESET == hcomp->State)
00662   {
00663     switch (CallbackID)
00664     {
00665       case HAL_COMP_MSPINIT_CB_ID :
00666         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00667         break;
00668
00669       case HAL_COMP_MSPDEINIT_CB_ID :
00670         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00671         break;
00672
00673       default :
00674         /* Update the error code */
00675         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00676
00677         /* Return error status */
00678         status =  HAL_ERROR;
00679         break;
00680     }
00681   }
00682   else
00683   {
00684     /* Update the error code */
00685     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00686
00687     /* Return error status */
00688     status =  HAL_ERROR;
00689   }
00690
00691   return status;
00692 }
00693
00694 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00695 /**
00696   * @}
00697   */
00698
00699 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00700  *  @brief   Start-Stop operation functions.
00701  *
00702 @verbatim
00703  ===============================================================================
00704                       ##### IO operation functions #####
00705  ===============================================================================
00706     [..]  This section provides functions allowing to:
00707       (+) Start a Comparator instance without interrupt.
00708       (+) Stop a Comparator instance without interrupt.
00709       (+) Start a Comparator instance with interrupt generation.
00710       (+) Stop a Comparator instance with interrupt generation.
00711
00712 @endverbatim
00713   * @{
00714   */
00715
00716 /**
00717   * @brief  Start the comparator.
00718   * @param  hcomp COMP handle
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00722 {
00723   __IO uint32_t wait_loop_index = 0UL;
00724
00725   HAL_StatusTypeDef status = HAL_OK;
00726
00727   /* Check the COMP handle allocation and lock status */
00728   if(hcomp == NULL)
00729   {
00730     status = HAL_ERROR;
00731   }
00732   else if(__HAL_COMP_IS_LOCKED(hcomp))
00733   {
00734     status = HAL_ERROR;
00735   }
00736   else
00737   {
00738     /* Check the parameter */
00739     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00740
00741     if(hcomp->State == HAL_COMP_STATE_READY)
00742     {
00743       /* Enable the selected comparator */
00744       SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00745
00746       /* Set HAL COMP handle state */
00747       hcomp->State = HAL_COMP_STATE_BUSY;
00748
00749      /* Delay for COMP startup time */
00750      /* Wait loop initialization and execution */
00751      /* Note: Variable divided by 2 to compensate partially    */
00752      /*       CPU processing cycles.                           */
00753
00754      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
00755      while(wait_loop_index != 0UL)
00756      {
00757        wait_loop_index--;
00758      }
00759     }
00760     else
00761     {
00762       status = HAL_ERROR;
00763     }
00764   }
00765
00766   return status;
00767 }
00768
00769 /**
00770   * @brief  Stop the comparator.
00771   * @param  hcomp COMP handle
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00775 {
00776   HAL_StatusTypeDef status = HAL_OK;
00777
00778   /* Check the COMP handle allocation and lock status */
00779   if(hcomp == NULL)
00780   {
00781     status = HAL_ERROR;
00782   }
00783   else if(__HAL_COMP_IS_LOCKED(hcomp))
00784   {
00785     status = HAL_ERROR;
00786   }
00787   else
00788   {
00789     /* Check the parameter */
00790     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00791
00792     /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY    */
00793     /* (all states except HAL_COMP_STATE_RESET and except locked status.      */
00794     if(hcomp->State != HAL_COMP_STATE_RESET)
00795     {
00796
00797       /* Disable the selected comparator */
00798       CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00799
00800       /* Set HAL COMP handle state */
00801       hcomp->State = HAL_COMP_STATE_READY;
00802     }
00803     else
00804     {
00805       status = HAL_ERROR;
00806     }
00807   }
00808
00809   return status;
00810 }
00811
00812 /**
00813   * @brief  Enable the interrupt and start the comparator.
00814   * @param  hcomp COMP handle
00815   * @retval HAL status
00816   */
00817 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
00818 {
00819
00820  __IO uint32_t wait_loop_index = 0UL;
00821  HAL_StatusTypeDef status = HAL_OK;
00822
00823   /* Check the COMP handle allocation and lock status */
00824   if(hcomp == NULL)
00825   {
00826     status = HAL_ERROR;
00827   }
00828   else if(__HAL_COMP_IS_LOCKED(hcomp))
00829   {
00830     status = HAL_ERROR;
00831   }
00832   else
00833   {
00834     /* Check the parameter */
00835     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00836     /* Set HAL COMP handle state */
00837     if(hcomp->State == HAL_COMP_STATE_READY)
00838     {
00839
00840     /* Enable the selected comparator */
00841     SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00842     /* Enable the Interrupt comparator */
00843     SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
00844
00845     hcomp->State = HAL_COMP_STATE_BUSY;
00846       /* Delay for COMP startup time */
00847       /* Wait loop initialization and execution */
00848       /* Note: Variable divided by 2 to compensate partially                  */
00849       /*       CPU processing cycles.                                         */
00850
00851      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
00852      while(wait_loop_index != 0UL)
00853      {
00854        wait_loop_index--;
00855      }
00856
00857     }
00858     else
00859     {
00860        status = HAL_ERROR;
00861     }
00862    }
00863
00864   return status;
00865 }
00866
00867 /**
00868   * @brief  Disable the interrupt and Stop the comparator.
00869   * @param  hcomp COMP handle
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
00873 {
00874   HAL_StatusTypeDef status;
00875 #if !defined (DUAL_CORE)
00876   /* Disable the EXTI Line interrupt mode */
00877    CLEAR_BIT(EXTI->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
00878 #endif
00879   /* Disable the Interrupt comparator */
00880    CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
00881
00882   status = HAL_COMP_Stop(hcomp);
00883
00884   return status;
00885
00886 }
00887
00888 /**
00889   * @brief  Comparator IRQ Handler.
00890   * @param  hcomp COMP handle
00891   * @retval HAL status
00892   */
00893 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00894 {
00895   /* Get the EXTI line corresponding to the selected COMP instance */
00896   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00897
00898
00899 #if defined(DUAL_CORE)
00900   /* EXTI line interrupt detected */
00901  if (HAL_GetCurrentCPUID() == CM7_CPUID)
00902  {
00903     /* Check COMP EXTI flag */
00904     if(READ_BIT(EXTI->PR1, exti_line) != 0UL)
00905     {
00906        /* Check whether comparator is in independent or window mode */
00907         if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
00908         {
00909           /* Clear COMP EXTI line pending bit of the pair of comparators          */
00910           /* in window mode.                                                      */
00911           /* Note: Pair of comparators in window mode can both trig IRQ when      */
00912           /*       input voltage is changing from "out of window" area            */
00913           /*       (low or high ) to the other "out of window" area (high or low).*/
00914           /*       Both flags must be cleared to call comparator trigger          */
00915           /*       callback is called once.                                       */
00916           WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00917         }
00918         else
00919         {
00920           /* Clear COMP EXTI line pending bit */
00921           WRITE_REG(EXTI->PR1, exti_line);
00922         }
00923
00924     /* COMP trigger user callback */
00925 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00926     hcomp->TriggerCallback(hcomp);
00927 #else
00928     HAL_COMP_TriggerCallback(hcomp);
00929 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00930     }
00931
00932
00933  }
00934  else
00935  {
00936     /* Check COMP EXTI flag */
00937     if(READ_BIT(EXTI_D2->PR1, exti_line) != 0UL)
00938     {
00939        /* Check whether comparator is in independent or window mode */
00940         if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
00941         {
00942           /* Clear COMP EXTI line pending bit of the pair of comparators          */
00943           /* in window mode.                                                      */
00944           /* Note: Pair of comparators in window mode can both trig IRQ when      */
00945           /*       input voltage is changing from "out of window" area            */
00946           /*       (low or high ) to the other "out of window" area (high or low).*/
00947           /*       Both flags must be cleared to call comparator trigger          */
00948           /*       callback is called once.                                       */
00949           WRITE_REG(EXTI_D2->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00950         }
00951         else
00952         {
00953           /* Clear COMP EXTI line pending bit */
00954           WRITE_REG(EXTI_D2->PR1, exti_line);
00955         }
00956
00957     /* COMP trigger user callback */
00958 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00959     hcomp->TriggerCallback(hcomp);
00960 #else
00961     HAL_COMP_TriggerCallback(hcomp);
00962 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00963     }
00964
00965
00966  }
00967 #else
00968     /* Check COMP EXTI flag */
00969     if(READ_BIT(EXTI->PR1, exti_line) != 0UL)
00970     {
00971        /* Check whether comparator is in independent or window mode */
00972         if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
00973         {
00974           /* Clear COMP EXTI line pending bit of the pair of comparators          */
00975           /* in window mode.                                                      */
00976           /* Note: Pair of comparators in window mode can both trig IRQ when      */
00977           /*       input voltage is changing from "out of window" area            */
00978           /*       (low or high ) to the other "out of window" area (high or low).*/
00979           /*       Both flags must be cleared to call comparator trigger          */
00980           /*       callback is called once.                                       */
00981           WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00982         }
00983         else
00984         {
00985           /* Clear COMP EXTI line pending bit */
00986           WRITE_REG(EXTI->PR1, exti_line);
00987         }
00988
00989     /* COMP trigger user callback */
00990 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00991     hcomp->TriggerCallback(hcomp);
00992 #else
00993     HAL_COMP_TriggerCallback(hcomp);
00994 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00995     }
00996 #endif /*DUAL_CORE*/
00997
00998    /* Get COMP interrupt source */
00999   if (__HAL_COMP_GET_IT_SOURCE(hcomp, COMP_IT_EN) != RESET)
01000   {
01001
01002     if((__HAL_COMP_GET_FLAG( COMP_FLAG_C1I)) != 0UL)
01003     {
01004       /* Clear the COMP channel 1 interrupt flag */
01005          __HAL_COMP_CLEAR_C1IFLAG();
01006
01007       /* Disable COMP interrupt */
01008        __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
01009
01010     }
01011     if((__HAL_COMP_GET_FLAG( COMP_FLAG_C2I)) != 0UL)
01012     {
01013      /* Clear the COMP channel 2 interrupt flag */
01014        __HAL_COMP_CLEAR_C2IFLAG();
01015
01016      /* Disable COMP interrupt */
01017      __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
01018
01019     }
01020
01021     /* Change COMP state */
01022     hcomp->State = HAL_COMP_STATE_READY;
01023
01024     /* COMP trigger user callback */
01025 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
01026     hcomp->TriggerCallback(hcomp);
01027 #else
01028     HAL_COMP_TriggerCallback(hcomp);
01029 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
01030   }
01031
01032
01033 }
01034
01035 /**
01036   * @}
01037   */
01038
01039 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
01040  *  @brief   Management functions.
01041  *
01042 @verbatim
01043  ===============================================================================
01044                       ##### Peripheral Control functions #####
01045  ===============================================================================
01046     [..]
01047     This subsection provides a set of functions allowing to control the comparators.
01048
01049 @endverbatim
01050   * @{
01051   */
01052
01053 /**
01054   * @brief  Lock the selected comparator configuration.
01055   * @note   A system reset is required to unlock the comparator configuration.
01056   * @param  hcomp COMP handle
01057   * @retval HAL status
01058   */
01059 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
01060 {
01061  HAL_StatusTypeDef status = HAL_OK;
01062
01063   /* Check the COMP handle allocation and lock status */
01064   if(hcomp == NULL)
01065   {
01066     status = HAL_ERROR;
01067   }
01068   else if(__HAL_COMP_IS_LOCKED(hcomp))
01069   {
01070     status = HAL_ERROR;
01071   }
01072   else
01073   {
01074     /* Check the parameter */
01075     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01076
01077     /* Set HAL COMP handle state */
01078     switch(hcomp->State)
01079     {
01080       case HAL_COMP_STATE_RESET:
01081         hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
01082         break;
01083       case HAL_COMP_STATE_READY:
01084         hcomp->State = HAL_COMP_STATE_READY_LOCKED;
01085         break;
01086       default: /* HAL_COMP_STATE_BUSY */
01087         hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
01088         break;
01089     }
01090   }
01091
01092   if(status == HAL_OK)
01093   {
01094     /* Set the lock bit corresponding to selected comparator */
01095     __HAL_COMP_LOCK(hcomp);
01096   }
01097
01098   return status;
01099 }
01100
01101 /**
01102   * @brief  Return the output level (high or low) of the selected comparator.
01103   * @note   The output level depends on the selected polarity.
01104   *         If the polarity is not inverted:
01105   *           - Comparator output is low when the input plus is at a lower
01106   *             voltage than the input minus
01107   *           - Comparator output is high when the input plus is at a higher
01108   *             voltage than the input minus
01109   *         If the polarity is inverted:
01110   *           - Comparator output is high when the input plus is at a lower
01111   *             voltage than the input minus
01112   *           - Comparator output is low when the input plus is at a higher
01113   *             voltage than the input minus
01114   * @param  hcomp  COMP handle
01115   * @retval Returns the selected comparator output level:
01116   *         @arg @ref COMP_OUTPUT_LEVEL_LOW
01117   *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
01118   *
01119   */
01120 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
01121 {
01122   /* Check the parameter */
01123   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01124
01125   if (hcomp->Instance == COMP1)
01126   {
01127     return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
01128   }
01129   else
01130   {
01131     return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL);
01132   }
01133 }
01134
01135 /**
01136   * @brief  Comparator trigger callback.
01137   * @param  hcomp COMP handle
01138   * @retval None
01139   */
01140 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
01141 {
01142    /* Prevent unused argument(s) compilation warning */
01143    UNUSED(hcomp);
01144   /* NOTE : This function should not be modified, when the callback is needed,
01145             the HAL_COMP_TriggerCallback should be implemented in the user file
01146    */
01147 }
01148
01149
01150 /**
01151   * @}
01152   */
01153
01154 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
01155  *  @brief   Peripheral State functions.
01156  *
01157 @verbatim
01158  ===============================================================================
01159                       ##### Peripheral State functions #####
01160  ===============================================================================
01161     [..]
01162     This subsection permit to get in run-time the status of the peripheral.
01163
01164 @endverbatim
01165   * @{
01166   */
01167
01168 /**
01169   * @brief  Return the COMP handle state.
01170   * @param  hcomp  COMP handle
01171   * @retval HAL state
01172   */
01173 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
01174 {
01175   /* Check the COMP handle allocation */
01176   if(hcomp == NULL)
01177   {
01178     return HAL_COMP_STATE_RESET;
01179   }
01180
01181   /* Check the parameter */
01182   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01183
01184   /* Return HAL COMP handle state */
01185   return hcomp->State;
01186 }
01187
01188 /**
01189   * @brief  Return the COMP error code.
01190   * @param hcomp COMP handle
01191   * @retval COMP error code
01192   */
01193 uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
01194 {
01195   /* Check the parameters */
01196   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01197
01198   return hcomp->ErrorCode;
01199 }
01200 /**
01201   * @}
01202   */
01203
01204 /**
01205   * @}
01206   */
01207
01208 #endif /* HAL_COMP_MODULE_ENABLED */
01209 /**
01210   * @}
01211   */
01212
01213 /**
01214   * @}
01215   */
01216
01217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_comp.h Source File

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stm32h7xx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_COMP_H
00022 #define STM32H7xx_HAL_COMP_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup COMP
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup COMP_Exported_Types COMP Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  COMP Init structure definition
00046   */
00047 typedef struct
00048 {
00049
00050   uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
00051                                     (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00052                                     Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
00053                                     This parameter can be a value of @ref COMP_WindowMode */
00054
00055   uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
00056                                     Note: For the characteritics of comparator power modes
00057                                           (propagation delay and power consumption), refer to device datasheet.
00058                                     This parameter can be a value of @ref COMP_PowerMode */
00059
00060   uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
00061                                     This parameter can be a value of @ref COMP_InputPlus */
00062
00063   uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
00064                                     This parameter can be a value of @ref COMP_InputMinus */
00065
00066   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00067                                     This parameter can be a value of @ref COMP_Hysteresis */
00068
00069   uint32_t OutputPol;          /*!< Set comparator output polarity.
00070                                     This parameter can be a value of @ref COMP_OutputPolarity */
00071
00072   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00073                                     This parameter can be a value of @ref COMP_BlankingSrce */
00074
00075   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00076                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00077
00078 }COMP_InitTypeDef;
00079
00080 /**
00081   * @brief  HAL COMP state machine: HAL COMP states definition
00082   */
00083 #define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
00084 typedef enum
00085 {
00086   HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */
00087   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00088   HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */
00089   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00090   HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */
00091   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00092 }HAL_COMP_StateTypeDef;
00093
00094 /**
00095   * @brief  COMP Handle Structure definition
00096   */
00097 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00098 typedef struct __COMP_HandleTypeDef
00099 #else
00100 typedef struct
00101 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00102 {
00103   COMP_TypeDef       *Instance;       /*!< Register base address    */
00104   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00105   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00106   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00107   __IO uint32_t      ErrorCode;       /*!< COMP error code */
00108 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00109   void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
00110   void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
00111   void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
00112 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00113
00114 } COMP_HandleTypeDef;
00115
00116 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00117 /**
00118   * @brief  HAL COMP Callback ID enumeration definition
00119   */
00120 typedef enum
00121 {
00122   HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
00123   HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
00124   HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
00125 } HAL_COMP_CallbackIDTypeDef;
00126
00127 /**
00128   * @brief  HAL COMP Callback pointer definition
00129   */
00130 typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
00131
00132 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup COMP_Error_Code COMP Error Code
00143   * @{
00144   */
00145 #define HAL_COMP_ERROR_NONE             (0x00U)   /*!< No error */
00146 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00147 #define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)   /*!< Invalid Callback error */
00148 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup COMP_WindowMode COMP Window Mode
00154   * @{
00155   */
00156 #define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000)   /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
00157 #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup COMP_PowerMode COMP power mode
00164   * @{
00165   */
00166 /* Note: For the characteritics of comparator power modes                     */
00167 /*       (propagation delay and power consumption),                           */
00168 /*       refer to device datasheet.                                           */
00169 #define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000)   /*!< High Speed */
00170 #define COMP_POWERMODE_MEDIUMSPEED     (COMP_CFGRx_PWRMODE_0)   /*!< Medium Speed */
00171 #define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CFGRx_PWRMODE)     /*!< Ultra-low power mode */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00177   * @{
00178   */
00179 #define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
00180 #define COMP_INPUT_PLUS_IO2            (COMP_CFGRx_INPSEL)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
00181 #if defined (COMP_CFGRx_INP2SEL)
00182 #define COMP_INPUT_PLUS_DAC2_CH1       (COMP_CFGRx_INP2SEL)   /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1) */
00183 #endif
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00189   * @{
00190   */
00191 #define COMP_INPUT_MINUS_1_4VREFINT     (                                                                                        COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/4 VrefInt */
00192 #define COMP_INPUT_MINUS_1_2VREFINT     (                                                                  COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/2 VrefInt */
00193 #define COMP_INPUT_MINUS_3_4VREFINT     (                                            COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 3/4 VrefInt */
00194 #define COMP_INPUT_MINUS_VREFINT        (                                            COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                   )    /*!< Comparator input minus connected to VrefInt */
00195 #define COMP_INPUT_MINUS_DAC1_CH1       (                      COMP_CFGRx_INMSEL_2                                                                                   )    /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
00196 #define COMP_INPUT_MINUS_DAC1_CH2       (                      COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
00197 #define COMP_INPUT_MINUS_IO1            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                                                             )    /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
00198 #define COMP_INPUT_MINUS_IO2            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
00199 #if defined (COMP_CFGRx_INMSEL_3)
00200 #define COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3                                                                                                         )    /*!< Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */
00201 #define COMP_INPUT_MINUS_VBAT_VDDAP     (COMP_CFGRx_INMSEL_3                                             | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2) */
00202 #endif
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup COMP_Hysteresis COMP hysteresis
00208   * @{
00209   */
00210 #define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000)   /*!< No hysteresis */
00211 #define COMP_HYSTERESIS_LOW            (COMP_CFGRx_HYST_0)      /*!< Hysteresis level low */
00212 #define COMP_HYSTERESIS_MEDIUM         (COMP_CFGRx_HYST_1)      /*!< Hysteresis level medium */
00213 #define COMP_HYSTERESIS_HIGH           (COMP_CFGRx_HYST)        /*!< Hysteresis level high */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup COMP_OutputPolarity COMP Output Polarity
00219   * @{
00220   */
00221 #define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000)  /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00222 #define COMP_OUTPUTPOL_INVERTED        (COMP_CFGRx_POLARITY)   /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00223 /**
00224   * @}
00225   */
00226
00227
00228 /** @defgroup COMP_BlankingSrce  COMP Blanking Source
00229   * @{
00230   */
00231 /* Any blanking source can be selected for all comparators */
00232 #define COMP_BLANKINGSRC_NONE             ((uint32_t)0x00000000)                           /*!< No blanking source */
00233 #define COMP_BLANKINGSRC_TIM1_OC5         (COMP_CFGRx_BLANKING_0)                          /*!< TIM1 OC5 selected as blanking source for comparator */
00234 #define COMP_BLANKINGSRC_TIM2_OC3         (COMP_CFGRx_BLANKING_1)                          /*!< TIM2 OC3 selected as blanking source for comparator */
00235 #define COMP_BLANKINGSRC_TIM3_OC3         (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)   /*!< TIM3 OC3 selected as blanking source for compartor */
00236 #define COMP_BLANKINGSRC_TIM3_OC4         (COMP_CFGRx_BLANKING_2)                          /*!< TIM3 OC4 selected as blanking source for comparator */
00237 #define COMP_BLANKINGSRC_TIM8_OC5         (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)    /*!< TIM8 OC5 selected as blanking source for comparator */
00238 #define COMP_BLANKINGSRC_TIM15_OC1        (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)    /*!< TIM15 OC1 selected as blanking source for comparator */
00239 /**
00240   * @}
00241   */
00242
00243
00244
00245
00246 /** @defgroup COMP_OutputLevel COMP Output Level
00247   * @{
00248   */
00249
00250 /* Note: Comparator output level values are fixed to "0" and "1",             */
00251 /* corresponding COMP register bit is managed by HAL function to match        */
00252 /* with these values (independently of bit position in register).             */
00253
00254 /* When output polarity is not inverted, comparator output is low when
00255    the input plus is at a lower voltage than the input minus */
00256 #define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)
00257 /* When output polarity is not inverted, comparator output is high when
00258    the input plus is at a higher voltage than the input minus */
00259 #define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00266   * @{
00267   */
00268 #define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */
00269 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00270 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00271 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00272 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00273 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00274 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup COMP_Flag COMP Flag
00281   * @{
00282   */
00283 #define COMP_FLAG_C1I           COMP_SR_C1IF           /*!< Comparator 1 Interrupt Flag */
00284 #define COMP_FLAG_C2I           COMP_SR_C2IF           /*!< Comparator 2 Interrupt Flag */
00285 #define COMP_FLAG_LOCK          COMP_CFGRx_LOCK        /*!< Lock flag */
00286 /**
00287   * @}
00288   */
00289 /** @defgroup COMP_IT_CLEAR_Flags  COMP Interruption Clear Flags
00290   * @{
00291   */
00292 #define COMP_CLEAR_C1IF          COMP_ICFR_C1IF     /*!< Clear Comparator 1 Interrupt Flag */
00293 #define COMP_CLEAR_C2IF          COMP_ICFR_C2IF     /*!< Clear Comparator 2 Interrupt Flag */
00294 /**
00295   * @}
00296   */
00297 /** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
00298   * @{
00299   */
00300 #define COMP_IT_EN               COMP_CFGRx_ITEN
00301
00302 /**
00303   * @}
00304   */
00305
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Exported macros -----------------------------------------------------------*/
00312 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00313   * @{
00314   */
00315 /** @defgroup COMP_Handle_Management  COMP Handle Management
00316  * @{
00317   */
00318
00319 /** @brief  Reset COMP handle state.
00320   * @param  __HANDLE__  COMP handle
00321   * @retval None
00322   */
00323 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00324 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
00325                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
00326                                                      (__HANDLE__)->MspInitCallback = NULL;            \
00327                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
00328                                                     } while(0)
00329 #else
00330 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00331 #endif
00332
00333 /**
00334   * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
00335   * @param __HANDLE__ COMP handle
00336   * @retval None
00337   */
00338 #define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
00339
00340 /**
00341   * @brief  Enable the specified comparator.
00342   * @param  __HANDLE__ COMP handle
00343   * @retval None
00344   */
00345 #define __HAL_COMP_ENABLE(__HANDLE__)                 SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
00346
00347 /**
00348   * @brief  Disable the specified comparator.
00349   * @param  __HANDLE__ COMP handle
00350   * @retval None
00351   */
00352 #define __HAL_COMP_DISABLE(__HANDLE__)                CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
00353
00354 /**
00355   * @brief  Lock the specified comparator configuration.
00356   * @note   Using this macro induce HAL COMP handle state machine being no
00357   *         more in line with COMP instance state.
00358   *         To keep HAL COMP handle state machine updated, it is recommended
00359   *         to use function "HAL_COMP_Lock')".
00360   * @param  __HANDLE__ COMP handle
00361   * @retval None
00362   */
00363 #define __HAL_COMP_LOCK(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
00364
00365 /**
00366   * @brief  Check whether the specified comparator is locked.
00367   * @param  __HANDLE__  COMP handle
00368   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00369   */
00370 #define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00377   * @{
00378   */
00379
00380 /**
00381   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00382   * @retval None
00383   */
00384 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00385
00386
00387 /**
00388   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00389   * @retval None
00390   */
00391 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()    CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00392
00393 /**
00394   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00395   * @retval None
00396   */
00397 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()    SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00398
00399 /**
00400   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00401   * @retval None
00402   */
00403 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()    CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00404
00405
00406 /**
00407   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00408   * @retval None
00409   */
00410 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \
00411                                                                __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();  \
00412                                                                __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
00413                                                              } while(0)
00414
00415
00416 /**
00417   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00418   * @retval None
00419   */
00420 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do {                                            \
00421                                                                __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();  \
00422                                                                __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
00423                                                              } while(0)
00424
00425
00426 /**
00427   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00428   * @retval None
00429   */
00430 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
00431
00432 /**
00433   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00434   * @retval None
00435   */
00436 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
00437
00438 /**
00439   * @brief  Enable the COMP1 EXTI Line in event mode.
00440   * @retval None
00441   */
00442 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
00443
00444 /**
00445   * @brief  Disable the COMP1 EXTI Line in event mode.
00446   * @retval None
00447   */
00448 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
00449
00450 /**
00451   * @brief  Check whether the COMP1 EXTI line flag is set or not.
00452   * @retval RESET or SET
00453   */
00454 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
00455 /**
00456   * @brief  Clear the COMP1 EXTI flag.
00457   * @retval None
00458   */
00459 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
00460
00461 /**
00462   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00463   * @retval None
00464   */
00465 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
00466
00467 /**
00468   * @brief  Enable the COMP1 D3 EXTI Line in event mode.
00469   * @retval None
00470   */
00471 #define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
00472
00473 /**
00474   * @brief  Disable the COMP1 D3 EXTI Line in event mode.
00475   * @retval None
00476   */
00477 #define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT()        CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
00478
00479 #if defined(DUAL_CORE)
00480 /**
00481   * @brief  Enable the COMP1 D2 EXTI line in interrupt mode.
00482   * @retval None
00483   */
00484 #define __HAL_COMP_COMP1_EXTID2_ENABLE_IT()           SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)
00485
00486 /**
00487   * @brief  Disable the COMP1 D2 EXTI line in interrupt mode.
00488   * @retval None
00489   */
00490 #define __HAL_COMP_COMP1_EXTID2_DISABLE_IT()          CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)
00491
00492 /**
00493   * @brief  Enable the COMP1 D2 EXTI Line in event mode.
00494   * @retval None
00495   */
00496 #define __HAL_COMP_COMP1_EXTID2_ENABLE_EVENT()         SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)
00497
00498 /**
00499   * @brief  Disable the COMP1 D2 EXTI Line in event mode.
00500   * @retval None
00501   */
00502 #define __HAL_COMP_COMP1_EXTID2_DISABLE_EVENT()        CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)
00503
00504 /**
00505   * @brief  Check whether the COMP1 D2 EXTI line flag is set or not.
00506   * @retval RESET or SET
00507   */
00508 #define __HAL_COMP_COMP1_EXTID2_GET_FLAG()              READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)
00509
00510 /**
00511   * @brief  Clear the COMP1 D2 EXTI flag.
00512   * @retval None
00513   */
00514 #define __HAL_COMP_COMP1_EXTID2_CLEAR_FLAG()            WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)
00515
00516 #endif
00517
00518 /**
00519   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00520   * @retval None
00521   */
00522 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00523
00524 /**
00525   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00526   * @retval None
00527   */
00528 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00529
00530 /**
00531   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00532   * @retval None
00533   */
00534 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00535
00536 /**
00537   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00538   * @retval None
00539   */
00540 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00541
00542 /**
00543   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00544   * @retval None
00545   */
00546 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \
00547                                                                __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();  \
00548                                                                __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
00549                                                              } while(0)
00550
00551 /**
00552   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00553   * @retval None
00554   */
00555 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do {                                           \
00556                                                                __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();  \
00557                                                                __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
00558                                                              } while(0)
00559 /**
00560   * @brief  Enable the COMP2 EXTI line.
00561   * @retval None
00562   */
00563 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
00564
00565 /**
00566   * @brief  Disable the COMP2 EXTI line.
00567   * @retval None
00568   */
00569 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
00570
00571 /**
00572   * @brief  Enable the COMP2 EXTI Line in event mode.
00573   * @retval None
00574   */
00575 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
00576
00577 /**
00578   * @brief  Disable the COMP2 EXTI Line in event mode.
00579   * @retval None
00580   */
00581 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
00582
00583 /**
00584   * @brief  Check whether the COMP2 EXTI line flag is set or not.
00585   * @retval RESET or SET
00586   */
00587 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
00588
00589 /**
00590   * @brief  Clear the the COMP2 EXTI flag.
00591   * @retval None
00592   */
00593 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
00594
00595 /**
00596   * @brief  Enable the COMP2 D3 EXTI Line in event mode.
00597   * @retval None
00598   */
00599 #define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
00600
00601 /**
00602   * @brief  Disable the COMP2 D3 EXTI Line in event mode.
00603   * @retval None
00604   */
00605 #define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT()       CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
00606
00607 /**
00608   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00609   * @retval None
00610   */
00611 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
00612
00613 #if defined(DUAL_CORE)
00614 /**
00615   * @brief  Enable the COMP2 D2 EXTI line
00616   * @retval None
00617   */
00618 #define __HAL_COMP_COMP2_EXTID2_ENABLE_IT()           SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)
00619
00620
00621 /**
00622   * @brief  Disable the COMP2 D2 EXTI line.
00623   * @retval None
00624   */
00625 #define __HAL_COMP_COMP2_EXTID2_DISABLE_IT()          CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)
00626
00627
00628
00629 /**
00630   * @brief  Enable the COMP2 D2 EXTI Line in event mode.
00631   * @retval None
00632   */
00633 #define __HAL_COMP_COMP2_EXTID2_ENABLE_EVENT()         SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)
00634
00635
00636
00637 /**
00638   * @brief  Disable the COMP2 D2 EXTI Line in event mode.
00639   * @retval None
00640   */
00641 #define __HAL_COMP_COMP2_EXTID2_DISABLE_EVENT()        CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)
00642
00643
00644 /**
00645   * @brief  Check whether the COMP2 D2 EXTI line flag is set or not.
00646   * @retval RESET or SET
00647   */
00648 #define __HAL_COMP_COMP2_EXTID2_GET_FLAG()            READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)
00649
00650 /**
00651   * @brief  Clear the the COMP2 D2 EXTI flag.
00652   * @retval None
00653   */
00654 #define __HAL_COMP_COMP2_EXTID2_CLEAR_FLAG()          WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)
00655
00656 #endif
00657 /** @brief  Checks if the specified COMP interrupt source is enabled or disabled.
00658   * @param  __HANDLE__: specifies the COMP Handle.
00659   *         This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
00660   * @param  __INTERRUPT__: specifies the COMP interrupt source to check.
00661   *          This parameter can be one of the following values:
00662   *            @arg COMP_IT_EN: Comparator interrupt enable
00663   *
00664   * @retval The new state of __IT__ (TRUE or FALSE)
00665   */
00666 #define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00667
00668 /** @brief  Checks whether the specified COMP flag is set or not.
00669   * @param  __FLAG__: specifies the flag to check.
00670   *        This parameter can be one of the following values:
00671   *            @arg COMP_FLAG_C1I:  Comparator 1 Interrupt Flag
00672   *            @arg COMP_FLAG_C2I:  Comparator 2 Interrupt Flag
00673   *            @retval The new state of __FLAG__ (TRUE or FALSE)
00674   */
00675 #define __HAL_COMP_GET_FLAG(__FLAG__)     ((COMP12->SR & (__FLAG__)) == (__FLAG__))
00676
00677 /** @brief  Clears the specified COMP pending flag.
00678   * @param  __FLAG__: specifies the flag to check.
00679   *          This parameter can be any combination of the following values:
00680   *            @arg COMP_CLEAR_C1IF  : Clear Comparator 1 Interrupt Flag
00681   *            @arg COMP_CLEAR_C2IF  : Clear Comparator 2 Interrupt Flag
00682   * @retval None
00683   */
00684 #define __HAL_COMP_CLEAR_FLAG(__FLAG__)   (COMP12->ICFR = (__FLAG__))
00685
00686 /** @brief  Clear the COMP C1I  flag.
00687   * @retval None
00688   */
00689 #define __HAL_COMP_CLEAR_C1IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
00690
00691 /** @brief  Clear the COMP C2I  flag.
00692   * @retval None
00693   */
00694 #define __HAL_COMP_CLEAR_C2IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
00695
00696 /** @brief  Enable the specified COMP interrupt.
00697   * @param  __HANDLE__: specifies the COMP Handle.
00698   * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.
00699   *          This parameter can be one of the following values:
00700   *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt
00701   * @retval None
00702   */
00703 #define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
00704
00705 /** @brief  Disable the specified COMP interrupt.
00706   * @param  __HANDLE__: specifies the COMP Handle.
00707   * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.
00708   *          This parameter can be one of the following values:
00709   *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt
00710   * @retval None
00711   */
00712 #define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
00713
00714 /**
00715   * @}
00716   */
00717 /** @brief  Enable the specified bit in the Option register.
00718   * @param  __AF__: specifies the Alternate Function source selection .
00719   *          This parameter can be one of the following values:
00720   *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection
00721   *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection
00722   *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection
00723   *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection
00724   *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection
00725   *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection
00726   *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection
00727   *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection
00728   *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection
00729   *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection
00730   *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection
00731   * @retval None
00732   */
00733 #define __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
00734
00735 /** @brief  Disable the specified bit in the Option register.
00736   * @param  __AF__: specifies the Alternate Function source selection .
00737   *          This parameter can be one of the following values:
00738   *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection
00739   *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection
00740   *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection
00741   *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection
00742   *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection
00743   *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection
00744   *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection
00745   *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection
00746   *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection
00747   *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection
00748   *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection
00749   * @retval None
00750   */
00751 #define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
00752 /**
00753   * @}
00754   */
00755
00756 /* Private types -------------------------------------------------------------*/
00757 /* Private constants ---------------------------------------------------------*/
00758 /** @defgroup COMP_Private_Constants COMP Private Constants
00759   * @{
00760   */
00761 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00762   * @{
00763   */
00764 #define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM20)  /*!< EXTI line 20 connected to COMP1 output */
00765 #define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP2 output */
00766 /**
00767   * @}
00768   */
00769 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00770   * @{
00771   */
00772 #define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */
00773 #define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */
00774 #define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */
00775 #define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */
00776 /**
00777   * @}
00778   */
00779 /**
00780   * @}
00781   */
00782
00783 /* Private macros ------------------------------------------------------------*/
00784 /** @defgroup COMP_Private_Macros COMP Private Macros
00785   * @{
00786   */
00787 /** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
00788   * @{
00789   */
00790 /**
00791   * @brief  Get the specified EXTI line for a comparator instance.
00792   * @param  __INSTANCE__: specifies the COMP instance.
00793   * @retval value of @ref COMP_ExtiLine
00794   */
00795 #define COMP_GET_EXTI_LINE(__INSTANCE__)             (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
00796                                                       COMP_EXTI_LINE_COMP2)
00797 /**
00798   * @}
00799   */
00800 /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
00801   * @{
00802   */
00803 #define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
00804                                              ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
00805
00806 #define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
00807                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
00808                                              ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
00809
00810 #if defined (COMP_CFGRx_INP2SEL)
00811 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00812                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
00813                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC2_CH1))
00814 #else
00815 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00816                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
00817 #endif
00818
00819
00820 #if defined (COMP_CFGRx_INMSEL_3)
00821 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)     || \
00822                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)     || \
00823                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)     || \
00824                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)        || \
00825                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)       || \
00826                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)       || \
00827                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)            || \
00828                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)            || \
00829                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_TPSENS_DAC2CH1) || \
00830                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT_VDDAP))
00831 #else
00832 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00833                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00834                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00835                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00836                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
00837                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
00838                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00839                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
00840 #endif
00841
00842 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
00843                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
00844                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
00845                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
00846
00847 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
00848                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00849
00850 #define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)      || \
00851                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \
00852                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \
00853                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \
00854                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4)  || \
00855                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5)  || \
00856                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
00857
00858
00859 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00860                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00861                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00862                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00863                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00864                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00865                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00866
00867 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
00868                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
00869
00870 /**
00871   * @}
00872   */
00873
00874 /**
00875   * @}
00876   */
00877
00878 /* Exported functions --------------------------------------------------------*/
00879 /** @addtogroup COMP_Exported_Functions
00880   * @{
00881   */
00882
00883 /** @addtogroup COMP_Exported_Functions_Group1
00884   * @{
00885   */
00886 /* Initialization and de-initialization functions  **********************************/
00887 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00888 HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
00889 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00890 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00891 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00892 /* Callbacks Register/UnRegister functions  ***********************************/
00893 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
00894 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
00895 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00896 /**
00897   * @}
00898   */
00899
00900 /* IO operation functions  *****************************************************/
00901 /** @addtogroup COMP_Exported_Functions_Group2
00902   * @{
00903   */
00904 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00905 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00906 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
00907 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
00908 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00909
00910 /**
00911   * @}
00912   */
00913
00914 /* Peripheral Control functions  ************************************************/
00915 /** @addtogroup COMP_Exported_Functions_Group3
00916   * @{
00917   */
00918 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00919 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00920 /* Callback in Interrupt mode */
00921 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00922 /**
00923   * @}
00924   */
00925
00926 /* Peripheral State functions  **************************************************/
00927 /** @addtogroup COMP_Exported_Functions_Group4
00928   * @{
00929   */
00930 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00931 uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
00932 /**
00933   * @}
00934   */
00935
00936 /**
00937   * @}
00938   */
00939
00940
00941 /**
00942   * @}
00943   */
00944
00945 /**
00946   * @}
00947   */
00948 #ifdef __cplusplus
00949 }
00950 #endif
00951
00952 #endif /* STM32H7xx_HAL_COMP_H */
00953
00954 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_conf.h Source File

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stm32h7xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_conf_template.h
00004   * @author  MCD Application Team
00005   * @brief   HAL configuration template file.
00006   *          This file should be copied to the application folder and renamed
00007   *          to stm32h7xx_hal_conf.h.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00012   * All rights reserved.</center></h2>
00013   *
00014   * This software component is licensed by ST under BSD 3-Clause license,
00015   * the "License"; You may not use this file except in compliance with the
00016   * License. You may obtain a copy of the License at:
00017   *                        opensource.org/licenses/BSD-3-Clause
00018   *
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef STM32H7xx_HAL_CONF_H
00024 #define STM32H7xx_HAL_CONF_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032
00033 /* ########################## Module Selection ############################## */
00034 /**
00035   * @brief This is the list of modules to be used in the HAL driver
00036   */
00037 #define HAL_MODULE_ENABLED
00038 #define HAL_ADC_MODULE_ENABLED
00039 #define HAL_CEC_MODULE_ENABLED
00040 #define HAL_COMP_MODULE_ENABLED
00041 #define HAL_CORTEX_MODULE_ENABLED
00042 #define HAL_CRC_MODULE_ENABLED
00043 #define HAL_CRYP_MODULE_ENABLED
00044 #define HAL_DAC_MODULE_ENABLED
00045 #define HAL_DCMI_MODULE_ENABLED
00046 #define HAL_DFSDM_MODULE_ENABLED
00047 #define HAL_DMA_MODULE_ENABLED
00048 #define HAL_DMA2D_MODULE_ENABLED
00049 #define HAL_DTS_MODULE_ENABLED
00050 #define HAL_DSI_MODULE_ENABLED
00051 #define HAL_ETH_MODULE_ENABLED
00052 #define HAL_EXTI_MODULE_ENABLED
00053 #define HAL_FDCAN_MODULE_ENABLED
00054 #define HAL_FLASH_MODULE_ENABLED
00055 #define HAL_GFXMMU_MODULE_ENABLED
00056 #define HAL_GPIO_MODULE_ENABLED
00057 #define HAL_HASH_MODULE_ENABLED
00058 #define HAL_HCD_MODULE_ENABLED
00059 #define HAL_HRTIM_MODULE_ENABLED
00060 #define HAL_HSEM_MODULE_ENABLED
00061 #define HAL_I2C_MODULE_ENABLED
00062 #define HAL_I2S_MODULE_ENABLED
00063 #define HAL_IRDA_MODULE_ENABLED
00064 #define HAL_IWDG_MODULE_ENABLED
00065 #define HAL_JPEG_MODULE_ENABLED
00066 #define HAL_LPTIM_MODULE_ENABLED
00067 #define HAL_LTDC_MODULE_ENABLED
00068 #define HAL_MDIOS_MODULE_ENABLED
00069 #define HAL_MDMA_MODULE_ENABLED
00070 #define HAL_MMC_MODULE_ENABLED
00071 #define HAL_NAND_MODULE_ENABLED
00072 #define HAL_NOR_MODULE_ENABLED
00073 #define HAL_OPAMP_MODULE_ENABLED
00074 #define HAL_OSPI_MODULE_ENABLED
00075 #define HAL_OTFDEC_MODULE_ENABLED
00076 #define HAL_PCD_MODULE_ENABLED
00077 #define HAL_PWR_MODULE_ENABLED
00078 #define HAL_PSSI_MODULE_ENABLED
00079 #define HAL_QSPI_MODULE_ENABLED
00080 #define HAL_RAMECC_MODULE_ENABLED
00081 #define HAL_RCC_MODULE_ENABLED
00082 #define HAL_RNG_MODULE_ENABLED
00083 #define HAL_RTC_MODULE_ENABLED
00084 #define HAL_SAI_MODULE_ENABLED
00085 #define HAL_SD_MODULE_ENABLED
00086 #define HAL_SDRAM_MODULE_ENABLED
00087 #define HAL_SMARTCARD_MODULE_ENABLED
00088 #define HAL_SMBUS_MODULE_ENABLED
00089 #define HAL_SPDIFRX_MODULE_ENABLED
00090 #define HAL_SPI_MODULE_ENABLED
00091 #define HAL_SRAM_MODULE_ENABLED
00092 #define HAL_SWPMI_MODULE_ENABLED
00093 #define HAL_TIM_MODULE_ENABLED
00094 #define HAL_UART_MODULE_ENABLED
00095 #define HAL_USART_MODULE_ENABLED
00096 #define HAL_WWDG_MODULE_ENABLED
00097
00098 /* ########################## Oscillator Values adaptation ####################*/
00099 /**
00100   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00101   *        This value is used by the RCC HAL module to compute the system frequency
00102   *        (when HSE is used as system clock source, directly or through the PLL).
00103   */
00104 #if !defined  (HSE_VALUE)
00105 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
00106 #endif /* HSE_VALUE */
00107
00108 #if !defined  (HSE_STARTUP_TIMEOUT)
00109   #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
00110 #endif /* HSE_STARTUP_TIMEOUT */
00111
00112 /**
00113   * @brief Internal  oscillator (CSI) default value.
00114   *        This value is the default CSI value after Reset.
00115   */
00116 #if !defined  (CSI_VALUE)
00117   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
00118 #endif /* CSI_VALUE */
00119
00120 /**
00121   * @brief Internal High Speed oscillator (HSI) value.
00122   *        This value is used by the RCC HAL module to compute the system frequency
00123   *        (when HSI is used as system clock source, directly or through the PLL).
00124   */
00125 #if !defined  (HSI_VALUE)
00126   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
00127 #endif /* HSI_VALUE */
00128
00129 /**
00130   * @brief External Low Speed oscillator (LSE) value.
00131   *        This value is used by the UART, RTC HAL module to compute the system frequency
00132   */
00133 #if !defined  (LSE_VALUE)
00134   #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
00135 #endif /* LSE_VALUE */
00136
00137
00138 #if !defined  (LSE_STARTUP_TIMEOUT)
00139   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
00140 #endif /* LSE_STARTUP_TIMEOUT */
00141
00142 #if !defined  (LSI_VALUE)
00143   #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/
00144 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00145                                               The real value may vary depending on the variations
00146                                               in voltage and temperature.*/
00147
00148 /**
00149   * @brief External clock source for I2S peripheral
00150   *        This value is used by the I2S HAL module to compute the I2S clock source
00151   *        frequency, this source is inserted directly through I2S_CKIN pad.
00152   */
00153 #if !defined  (EXTERNAL_CLOCK_VALUE)
00154   #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
00155 #endif /* EXTERNAL_CLOCK_VALUE */
00156
00157 /* Tip: To avoid modifying this file each time you need to use different HSE,
00158    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00159
00160 /* ########################### System Configuration ######################### */
00161 /**
00162   * @brief This is the HAL system configuration section
00163   */
00164 #define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
00165 #define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
00166 #define  USE_RTOS                     0
00167 #define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
00168 #define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
00169
00170 #define  USE_HAL_ADC_REGISTER_CALLBACKS 1U /* ADC register callback disabled     */
00171 #define  USE_HAL_CEC_REGISTER_CALLBACKS 1U /* CEC register callback disabled     */
00172 #define  USE_HAL_COMP_REGISTER_CALLBACKS 1U /* COMP register callback disabled    */
00173 #define  USE_HAL_CRYP_REGISTER_CALLBACKS 1U /* CRYP register callback disabled    */
00174 #define  USE_HAL_DAC_REGISTER_CALLBACKS 1U /* DAC register callback disabled     */
00175 #define  USE_HAL_DCMI_REGISTER_CALLBACKS 1U /* DCMI register callback disabled    */
00176 #define  USE_HAL_DFSDM_REGISTER_CALLBACKS 1U /* DFSDM register callback disabled   */
00177 #define  USE_HAL_DMA2D_REGISTER_CALLBACKS 1U /* DMA2D register callback disabled   */
00178 #define  USE_HAL_DSI_REGISTER_CALLBACKS 1U /* DSI register callback disabled     */
00179 #define  USE_HAL_DTS_REGISTER_CALLBACKS 1U /* DTS register callback disabled     */
00180 #define  USE_HAL_ETH_REGISTER_CALLBACKS 1U /* ETH register callback disabled     */
00181 #define  USE_HAL_FDCAN_REGISTER_CALLBACKS 1U /* FDCAN register callback disabled   */
00182 #define  USE_HAL_NAND_REGISTER_CALLBACKS 1U /* NAND register callback disabled    */
00183 #define  USE_HAL_NOR_REGISTER_CALLBACKS 1U /* NOR register callback disabled     */
00184 #define  USE_HAL_SDRAM_REGISTER_CALLBACKS 1U /* SDRAM register callback disabled   */
00185 #define  USE_HAL_SRAM_REGISTER_CALLBACKS 1U /* SRAM register callback disabled    */
00186 #define  USE_HAL_HASH_REGISTER_CALLBACKS 1U /* HASH register callback disabled    */
00187 #define  USE_HAL_HCD_REGISTER_CALLBACKS 1U /* HCD register callback disabled     */
00188 #define  USE_HAL_GFXMMU_REGISTER_CALLBACKS 1U /* GFXMMU register callback disabled  */
00189 #define  USE_HAL_HRTIM_REGISTER_CALLBACKS 1U /* HRTIM register callback disabled   */
00190 #define  USE_HAL_I2C_REGISTER_CALLBACKS 1U /* I2C register callback disabled     */
00191 #define  USE_HAL_I2S_REGISTER_CALLBACKS 1U /* I2S register callback disabled     */
00192 #define  USE_HAL_IRDA_REGISTER_CALLBACKS 1U /* IRDA register callback disabled    */
00193 #define  USE_HAL_JPEG_REGISTER_CALLBACKS 1U /* JPEG register callback disabled    */
00194 #define  USE_HAL_LPTIM_REGISTER_CALLBACKS 1U /* LPTIM register callback disabled   */
00195 #define  USE_HAL_LTDC_REGISTER_CALLBACKS 1U /* LTDC register callback disabled    */
00196 #define  USE_HAL_MDIOS_REGISTER_CALLBACKS 1U /* MDIO register callback disabled    */
00197 #define  USE_HAL_MMC_REGISTER_CALLBACKS 1U /* MMC register callback disabled     */
00198 #define  USE_HAL_OPAMP_REGISTER_CALLBACKS 1U /* MDIO register callback disabled    */
00199 #define  USE_HAL_OSPI_REGISTER_CALLBACKS 1U /* OSPI register callback disabled    */
00200 #define  USE_HAL_OTFDEC_REGISTER_CALLBACKS 1U /* OTFDEC register callback disabled  */
00201 #define  USE_HAL_PCD_REGISTER_CALLBACKS 1U /* PCD register callback disabled     */
00202 #define  USE_HAL_QSPI_REGISTER_CALLBACKS 1U /* QSPI register callback disabled    */
00203 #define  USE_HAL_RNG_REGISTER_CALLBACKS 1U /* RNG register callback disabled     */
00204 #define  USE_HAL_RTC_REGISTER_CALLBACKS 1U /* RTC register callback disabled     */
00205 #define  USE_HAL_SAI_REGISTER_CALLBACKS 1U /* SAI register callback disabled     */
00206 #define  USE_HAL_SD_REGISTER_CALLBACKS 1U /* SD register callback disabled      */
00207 #define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U /* SMARTCARD register callback disabled */
00208 #define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 1U /* SPDIFRX register callback disabled */
00209 #define  USE_HAL_SMBUS_REGISTER_CALLBACKS 1U /* SMBUS register callback disabled   */
00210 #define  USE_HAL_SPI_REGISTER_CALLBACKS 1U /* SPI register callback disabled     */
00211 #define  USE_HAL_SWPMI_REGISTER_CALLBACKS 1U /* SWPMI register callback disabled   */
00212 #define  USE_HAL_TIM_REGISTER_CALLBACKS 1U /* TIM register callback disabled     */
00213 #define  USE_HAL_UART_REGISTER_CALLBACKS 1U /* UART register callback disabled    */
00214 #define  USE_HAL_USART_REGISTER_CALLBACKS 1U /* USART register callback disabled   */
00215 #define  USE_HAL_WWDG_REGISTER_CALLBACKS 1U /* WWDG register callback disabled    */
00216
00217 /* ########################### Ethernet Configuration ######################### */
00218 #define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
00219 #define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
00220
00221 #define ETH_MAC_ADDR0    ((uint8_t)0x02)
00222 #define ETH_MAC_ADDR1    ((uint8_t)0x00)
00223 #define ETH_MAC_ADDR2    ((uint8_t)0x00)
00224 #define ETH_MAC_ADDR3    ((uint8_t)0x00)
00225 #define ETH_MAC_ADDR4    ((uint8_t)0x00)
00226 #define ETH_MAC_ADDR5    ((uint8_t)0x00)
00227
00228 /* ########################## Assert Selection ############################## */
00229 /**
00230   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00231   *        HAL drivers code
00232   */
00233 /* #define USE_FULL_ASSERT    1 */
00234
00235
00236 /* Includes ------------------------------------------------------------------*/
00237 /**
00238   * @brief Include module's header file
00239   */
00240
00241 #ifdef HAL_RCC_MODULE_ENABLED
00242   #include "stm32h7xx_hal_rcc.h"
00243 #endif /* HAL_RCC_MODULE_ENABLED */
00244
00245 #ifdef HAL_GPIO_MODULE_ENABLED
00246   #include "stm32h7xx_hal_gpio.h"
00247 #endif /* HAL_GPIO_MODULE_ENABLED */
00248
00249 #ifdef HAL_DMA_MODULE_ENABLED
00250   #include "stm32h7xx_hal_dma.h"
00251 #endif /* HAL_DMA_MODULE_ENABLED */
00252
00253 #ifdef HAL_MDMA_MODULE_ENABLED
00254  #include "stm32h7xx_hal_mdma.h"
00255 #endif /* HAL_MDMA_MODULE_ENABLED */
00256
00257 #ifdef HAL_HASH_MODULE_ENABLED
00258   #include "stm32h7xx_hal_hash.h"
00259 #endif /* HAL_HASH_MODULE_ENABLED */
00260
00261 #ifdef HAL_DCMI_MODULE_ENABLED
00262   #include "stm32h7xx_hal_dcmi.h"
00263 #endif /* HAL_DCMI_MODULE_ENABLED */
00264
00265 #ifdef HAL_DMA2D_MODULE_ENABLED
00266   #include "stm32h7xx_hal_dma2d.h"
00267 #endif /* HAL_DMA2D_MODULE_ENABLED */
00268
00269 #ifdef HAL_DSI_MODULE_ENABLED
00270   #include "stm32h7xx_hal_dsi.h"
00271 #endif /* HAL_DSI_MODULE_ENABLED */
00272
00273 #ifdef HAL_DFSDM_MODULE_ENABLED
00274   #include "stm32h7xx_hal_dfsdm.h"
00275 #endif /* HAL_DFSDM_MODULE_ENABLED */
00276
00277 #ifdef HAL_DTS_MODULE_ENABLED
00278  #include "stm32h7xx_hal_dts.h"
00279 #endif /* HAL_DTS_MODULE_ENABLED */
00280
00281 #ifdef HAL_ETH_MODULE_ENABLED
00282   #include "stm32h7xx_hal_eth.h"
00283 #endif /* HAL_ETH_MODULE_ENABLED */
00284
00285 #ifdef HAL_EXTI_MODULE_ENABLED
00286   #include "stm32h7xx_hal_exti.h"
00287 #endif /* HAL_EXTI_MODULE_ENABLED */
00288
00289 #ifdef HAL_CORTEX_MODULE_ENABLED
00290   #include "stm32h7xx_hal_cortex.h"
00291 #endif /* HAL_CORTEX_MODULE_ENABLED */
00292
00293 #ifdef HAL_ADC_MODULE_ENABLED
00294   #include "stm32h7xx_hal_adc.h"
00295 #endif /* HAL_ADC_MODULE_ENABLED */
00296
00297 #ifdef HAL_FDCAN_MODULE_ENABLED
00298   #include "stm32h7xx_hal_fdcan.h"
00299 #endif /* HAL_FDCAN_MODULE_ENABLED */
00300
00301 #ifdef HAL_CEC_MODULE_ENABLED
00302   #include "stm32h7xx_hal_cec.h"
00303 #endif /* HAL_CEC_MODULE_ENABLED */
00304
00305 #ifdef HAL_COMP_MODULE_ENABLED
00306   #include "stm32h7xx_hal_comp.h"
00307 #endif /* HAL_COMP_MODULE_ENABLED */
00308
00309 #ifdef HAL_CRC_MODULE_ENABLED
00310   #include "stm32h7xx_hal_crc.h"
00311 #endif /* HAL_CRC_MODULE_ENABLED */
00312
00313 #ifdef HAL_CRYP_MODULE_ENABLED
00314   #include "stm32h7xx_hal_cryp.h"
00315 #endif /* HAL_CRYP_MODULE_ENABLED */
00316
00317 #ifdef HAL_DAC_MODULE_ENABLED
00318   #include "stm32h7xx_hal_dac.h"
00319 #endif /* HAL_DAC_MODULE_ENABLED */
00320
00321 #ifdef HAL_FLASH_MODULE_ENABLED
00322   #include "stm32h7xx_hal_flash.h"
00323 #endif /* HAL_FLASH_MODULE_ENABLED */
00324
00325 #ifdef HAL_GFXMMU_MODULE_ENABLED
00326   #include "stm32h7xx_hal_gfxmmu.h"
00327 #endif /* HAL_GFXMMU_MODULE_ENABLED */
00328
00329 #ifdef HAL_HRTIM_MODULE_ENABLED
00330   #include "stm32h7xx_hal_hrtim.h"
00331 #endif /* HAL_HRTIM_MODULE_ENABLED */
00332
00333 #ifdef HAL_HSEM_MODULE_ENABLED
00334   #include "stm32h7xx_hal_hsem.h"
00335 #endif /* HAL_HSEM_MODULE_ENABLED */
00336
00337 #ifdef HAL_SRAM_MODULE_ENABLED
00338   #include "stm32h7xx_hal_sram.h"
00339 #endif /* HAL_SRAM_MODULE_ENABLED */
00340
00341 #ifdef HAL_NOR_MODULE_ENABLED
00342   #include "stm32h7xx_hal_nor.h"
00343 #endif /* HAL_NOR_MODULE_ENABLED */
00344
00345 #ifdef HAL_NAND_MODULE_ENABLED
00346   #include "stm32h7xx_hal_nand.h"
00347 #endif /* HAL_NAND_MODULE_ENABLED */
00348
00349 #ifdef HAL_I2C_MODULE_ENABLED
00350  #include "stm32h7xx_hal_i2c.h"
00351 #endif /* HAL_I2C_MODULE_ENABLED */
00352
00353 #ifdef HAL_I2S_MODULE_ENABLED
00354  #include "stm32h7xx_hal_i2s.h"
00355 #endif /* HAL_I2S_MODULE_ENABLED */
00356
00357 #ifdef HAL_IWDG_MODULE_ENABLED
00358  #include "stm32h7xx_hal_iwdg.h"
00359 #endif /* HAL_IWDG_MODULE_ENABLED */
00360
00361 #ifdef HAL_JPEG_MODULE_ENABLED
00362  #include "stm32h7xx_hal_jpeg.h"
00363 #endif /* HAL_JPEG_MODULE_ENABLED */
00364
00365 #ifdef HAL_MDIOS_MODULE_ENABLED
00366  #include "stm32h7xx_hal_mdios.h"
00367 #endif /* HAL_MDIOS_MODULE_ENABLED */
00368
00369 #ifdef HAL_MMC_MODULE_ENABLED
00370  #include "stm32h7xx_hal_mmc.h"
00371 #endif /* HAL_MMC_MODULE_ENABLED */
00372
00373 #ifdef HAL_LPTIM_MODULE_ENABLED
00374 #include "stm32h7xx_hal_lptim.h"
00375 #endif /* HAL_LPTIM_MODULE_ENABLED */
00376
00377 #ifdef HAL_LTDC_MODULE_ENABLED
00378 #include "stm32h7xx_hal_ltdc.h"
00379 #endif /* HAL_LTDC_MODULE_ENABLED */
00380
00381 #ifdef HAL_OPAMP_MODULE_ENABLED
00382 #include "stm32h7xx_hal_opamp.h"
00383 #endif /* HAL_OPAMP_MODULE_ENABLED */
00384
00385 #ifdef HAL_OSPI_MODULE_ENABLED
00386  #include "stm32h7xx_hal_ospi.h"
00387 #endif /* HAL_OSPI_MODULE_ENABLED */
00388
00389 #ifdef HAL_OTFDEC_MODULE_ENABLED
00390 #include "stm32h7xx_hal_otfdec.h"
00391 #endif /* HAL_OTFDEC_MODULE_ENABLED */
00392
00393 #ifdef HAL_PSSI_MODULE_ENABLED
00394  #include "stm32h7xx_hal_pssi.h"
00395 #endif /* HAL_PSSI_MODULE_ENABLED */
00396
00397 #ifdef HAL_PWR_MODULE_ENABLED
00398  #include "stm32h7xx_hal_pwr.h"
00399 #endif /* HAL_PWR_MODULE_ENABLED */
00400
00401 #ifdef HAL_QSPI_MODULE_ENABLED
00402  #include "stm32h7xx_hal_qspi.h"
00403 #endif /* HAL_QSPI_MODULE_ENABLED */
00404
00405 #ifdef HAL_RAMECC_MODULE_ENABLED
00406  #include "stm32h7xx_hal_ramecc.h"
00407 #endif /* HAL_RAMECC_MODULE_ENABLED */
00408
00409 #ifdef HAL_RNG_MODULE_ENABLED
00410  #include "stm32h7xx_hal_rng.h"
00411 #endif /* HAL_RNG_MODULE_ENABLED */
00412
00413 #ifdef HAL_RTC_MODULE_ENABLED
00414  #include "stm32h7xx_hal_rtc.h"
00415 #endif /* HAL_RTC_MODULE_ENABLED */
00416
00417 #ifdef HAL_SAI_MODULE_ENABLED
00418  #include "stm32h7xx_hal_sai.h"
00419 #endif /* HAL_SAI_MODULE_ENABLED */
00420
00421 #ifdef HAL_SD_MODULE_ENABLED
00422  #include "stm32h7xx_hal_sd.h"
00423 #endif /* HAL_SD_MODULE_ENABLED */
00424
00425 #ifdef HAL_SDRAM_MODULE_ENABLED
00426  #include "stm32h7xx_hal_sdram.h"
00427 #endif /* HAL_SDRAM_MODULE_ENABLED */
00428
00429 #ifdef HAL_SPI_MODULE_ENABLED
00430  #include "stm32h7xx_hal_spi.h"
00431 #endif /* HAL_SPI_MODULE_ENABLED */
00432
00433 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00434  #include "stm32h7xx_hal_spdifrx.h"
00435 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
00436
00437 #ifdef HAL_SWPMI_MODULE_ENABLED
00438  #include "stm32h7xx_hal_swpmi.h"
00439 #endif /* HAL_SWPMI_MODULE_ENABLED */
00440
00441 #ifdef HAL_TIM_MODULE_ENABLED
00442  #include "stm32h7xx_hal_tim.h"
00443 #endif /* HAL_TIM_MODULE_ENABLED */
00444
00445 #ifdef HAL_UART_MODULE_ENABLED
00446  #include "stm32h7xx_hal_uart.h"
00447 #endif /* HAL_UART_MODULE_ENABLED */
00448
00449 #ifdef HAL_USART_MODULE_ENABLED
00450  #include "stm32h7xx_hal_usart.h"
00451 #endif /* HAL_USART_MODULE_ENABLED */
00452
00453 #ifdef HAL_IRDA_MODULE_ENABLED
00454  #include "stm32h7xx_hal_irda.h"
00455 #endif /* HAL_IRDA_MODULE_ENABLED */
00456
00457 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00458  #include "stm32h7xx_hal_smartcard.h"
00459 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00460
00461 #ifdef HAL_SMBUS_MODULE_ENABLED
00462  #include "stm32h7xx_hal_smbus.h"
00463 #endif /* HAL_SMBUS_MODULE_ENABLED */
00464
00465 #ifdef HAL_WWDG_MODULE_ENABLED
00466  #include "stm32h7xx_hal_wwdg.h"
00467 #endif /* HAL_WWDG_MODULE_ENABLED */
00468
00469 #ifdef HAL_PCD_MODULE_ENABLED
00470  #include "stm32h7xx_hal_pcd.h"
00471 #endif /* HAL_PCD_MODULE_ENABLED */
00472
00473 #ifdef HAL_HCD_MODULE_ENABLED
00474  #include "stm32h7xx_hal_hcd.h"
00475 #endif /* HAL_HCD_MODULE_ENABLED */
00476
00477 /* Exported macro ------------------------------------------------------------*/
00478 #ifdef  USE_FULL_ASSERT
00479 /**
00480   * @brief  The assert_param macro is used for function's parameters check.
00481   * @param  expr: If expr is false, it calls assert_failed function
00482   *         which reports the name of the source file and the source
00483   *         line number of the call that failed.
00484   *         If expr is true, it returns no value.
00485   * @retval None
00486   */
00487   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00488 /* Exported functions ------------------------------------------------------- */
00489   void assert_failed(uint8_t *file, uint32_t line);
00490 #else
00491   #define assert_param(expr) ((void)0U)
00492 #endif /* USE_FULL_ASSERT */
00493
00494 #ifdef __cplusplus
00495 }
00496 #endif
00497
00498 #endif /* STM32H7xx_HAL_CONF_H */
00499
00500
00501 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cortex.c Source File

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stm32h7xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @brief   CORTEX HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORTEX:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015
00016     [..]
00017     *** How to configure Interrupts using CORTEX HAL driver ***
00018     ===========================================================
00019     [..]
00020     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00021     The Cortex-M exceptions are managed by CMSIS functions.
00022
00023     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
00024         function according to the following table.
00025     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00026     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00027     (#) please refer to programming manual for details in how to configure priority.
00028
00029      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
00030          The pending IRQ priority will be managed only by the sub priority.
00031
00032      -@- IRQ priority order (sorted by highest to lowest priority):
00033         (+@) Lowest preemption priority
00034         (+@) Lowest sub priority
00035         (+@) Lowest hardware priority (IRQ number)
00036
00037     [..]
00038     *** How to configure Systick using CORTEX HAL driver ***
00039     ========================================================
00040     [..]
00041     Setup SysTick Timer for time base.
00042
00043    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00044        is a CMSIS function that:
00045         (++) Configures the SysTick Reload register with value passed as function parameter.
00046         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
00047         (++) Resets the SysTick Counter register.
00048         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00049         (++) Enables the SysTick Interrupt.
00050         (++) Starts the SysTick Counter.
00051
00052    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00053        HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00054        HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
00055        inside the stm32h7xx_hal_cortex.h file.
00056
00057    (+) You can change the SysTick IRQ priority by calling the
00058        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00059        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00060
00061    (+) To adjust the SysTick time base, use the following formula:
00062
00063        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00064        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00065        (++) Reload Value should not exceed 0xFFFFFF
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00072   * All rights reserved.</center></h2>
00073   *
00074   * This software component is licensed by ST under BSD 3-Clause license,
00075   * the "License"; You may not use this file except in compliance with the
00076   * License. You may obtain a copy of the License at:
00077   *                        opensource.org/licenses/BSD-3-Clause
00078   *
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32h7xx_hal.h"
00084
00085 /** @addtogroup STM32H7xx_HAL_Driver
00086   * @{
00087   */
00088
00089 /** @defgroup CORTEX CORTEX
00090   * @brief CORTEX HAL module driver
00091   * @{
00092   */
00093
00094 #ifdef HAL_CORTEX_MODULE_ENABLED
00095
00096 /* Private types -------------------------------------------------------------*/
00097 /* Private variables ---------------------------------------------------------*/
00098 /* Private constants ---------------------------------------------------------*/
00099 /* Private macros ------------------------------------------------------------*/
00100 /* Private functions ---------------------------------------------------------*/
00101 /* Exported functions --------------------------------------------------------*/
00102
00103 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00104   * @{
00105   */
00106
00107
00108 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00109  *  @brief    Initialization and Configuration functions
00110  *
00111 @verbatim
00112   ==============================================================================
00113               ##### Initialization and de-initialization functions #####
00114   ==============================================================================
00115     [..]
00116       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00117       Systick functionalities
00118
00119 @endverbatim
00120   * @{
00121   */
00122
00123
00124 /**
00125   * @brief  Sets the priority grouping field (preemption priority and subpriority)
00126   *         using the required unlock sequence.
00127   * @param  PriorityGroup The priority grouping bits length.
00128   *         This parameter can be one of the following values:
00129   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00130   *                                    4 bits for subpriority
00131   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00132   *                                    3 bits for subpriority
00133   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00134   *                                    2 bits for subpriority
00135   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00136   *                                    1 bits for subpriority
00137   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00138   *                                    0 bits for subpriority
00139   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
00140   *         The pending IRQ priority will be managed only by the subpriority.
00141   * @retval None
00142   */
00143 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00144 {
00145   /* Check the parameters */
00146   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00147
00148   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00149   NVIC_SetPriorityGrouping(PriorityGroup);
00150 }
00151
00152 /**
00153   * @brief  Sets the priority of an interrupt.
00154   * @param  IRQn External interrupt number.
00155   *         This parameter can be an enumerator of IRQn_Type enumeration
00156   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00157   * @param  PreemptPriority The preemption priority for the IRQn channel.
00158   *         This parameter can be a value between 0 and 15
00159   *         A lower priority value indicates a higher priority
00160   * @param  SubPriority the subpriority level for the IRQ channel.
00161   *         This parameter can be a value between 0 and 15
00162   *         A lower priority value indicates a higher priority.
00163   * @retval None
00164   */
00165 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00166 {
00167   uint32_t prioritygroup;
00168
00169   /* Check the parameters */
00170   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00171   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00172
00173   prioritygroup = NVIC_GetPriorityGrouping();
00174
00175   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00176 }
00177
00178 /**
00179   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00180   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00181   *         function should be called before.
00182   * @param  IRQn External interrupt number.
00183   *         This parameter can be an enumerator of IRQn_Type enumeration
00184   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00185   * @retval None
00186   */
00187 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00188 {
00189   /* Check the parameters */
00190   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00191
00192   /* Enable interrupt */
00193   NVIC_EnableIRQ(IRQn);
00194 }
00195
00196 /**
00197   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00198   * @param  IRQn External interrupt number.
00199   *         This parameter can be an enumerator of IRQn_Type enumeration
00200   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00201   * @retval None
00202   */
00203 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00204 {
00205   /* Check the parameters */
00206   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00207
00208   /* Disable interrupt */
00209   NVIC_DisableIRQ(IRQn);
00210 }
00211
00212 /**
00213   * @brief  Initiates a system reset request to reset the MCU.
00214   * @retval None
00215   */
00216 void HAL_NVIC_SystemReset(void)
00217 {
00218   /* System Reset */
00219   NVIC_SystemReset();
00220 }
00221
00222 /**
00223   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00224   *         Counter is in free running mode to generate periodic interrupts.
00225   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
00226   * @retval status   - 0  Function succeeded.
00227   *                  - 1  Function failed.
00228   */
00229 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00230 {
00231    return SysTick_Config(TicksNumb);
00232 }
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00238  *  @brief   Cortex control functions
00239  *
00240 @verbatim
00241   ==============================================================================
00242                       ##### Peripheral Control functions #####
00243   ==============================================================================
00244     [..]
00245       This subsection provides a set of functions allowing to control the CORTEX
00246       (NVIC, SYSTICK, MPU) functionalities.
00247
00248
00249 @endverbatim
00250   * @{
00251   */
00252 #if (__MPU_PRESENT == 1)
00253 /**
00254   * @brief  Disables the MPU
00255   * @retval None
00256   */
00257 void HAL_MPU_Disable(void)
00258 {
00259   /* Make sure outstanding transfers are done */
00260   __DMB();
00261
00262   /* Disable fault exceptions */
00263   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00264
00265   /* Disable the MPU and clear the control register*/
00266   MPU->CTRL = 0;
00267 }
00268
00269 /**
00270   * @brief  Enables the MPU
00271   * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
00272   *         NMI, FAULTMASK and privileged access to the default memory
00273   *         This parameter can be one of the following values:
00274   *            @arg MPU_HFNMI_PRIVDEF_NONE
00275   *            @arg MPU_HARDFAULT_NMI
00276   *            @arg MPU_PRIVILEGED_DEFAULT
00277   *            @arg MPU_HFNMI_PRIVDEF
00278   * @retval None
00279   */
00280 void HAL_MPU_Enable(uint32_t MPU_Control)
00281 {
00282   /* Enable the MPU */
00283   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00284
00285   /* Enable fault exceptions */
00286   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00287
00288   /* Ensure MPU setting take effects */
00289   __DSB();
00290   __ISB();
00291 }
00292 /**
00293   * @brief  Initializes and configures the Region and the memory to be protected.
00294   * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
00295   *                  the initialization and configuration information.
00296   * @retval None
00297   */
00298 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00299 {
00300   /* Check the parameters */
00301   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00302   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00303
00304   /* Set the Region number */
00305   MPU->RNR = MPU_Init->Number;
00306
00307   if ((MPU_Init->Enable) != 0UL)
00308   {
00309     /* Check the parameters */
00310     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00311     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00312     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00313     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00314     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00315     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00316     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00317     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00318
00319     MPU->RBAR = MPU_Init->BaseAddress;
00320     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00321                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00322                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00323                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00324                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00325                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00326                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00327                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00328                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00329   }
00330   else
00331   {
00332     MPU->RBAR = 0x00;
00333     MPU->RASR = 0x00;
00334   }
00335 }
00336 #endif /* __MPU_PRESENT */
00337
00338 /**
00339   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00340   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00341   */
00342 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00343 {
00344   /* Get the PRIGROUP[10:8] field value */
00345   return NVIC_GetPriorityGrouping();
00346 }
00347
00348 /**
00349   * @brief  Gets the priority of an interrupt.
00350   * @param  IRQn External interrupt number.
00351   *         This parameter can be an enumerator of IRQn_Type enumeration
00352   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00353   * @param   PriorityGroup the priority grouping bits length.
00354   *         This parameter can be one of the following values:
00355   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00356   *                                      4 bits for subpriority
00357   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00358   *                                      3 bits for subpriority
00359   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00360   *                                      2 bits for subpriority
00361   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00362   *                                      1 bits for subpriority
00363   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00364   *                                      0 bits for subpriority
00365   * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
00366   * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
00367   * @retval None
00368   */
00369 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00370 {
00371   /* Check the parameters */
00372   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00373  /* Get priority for Cortex-M system or device specific interrupts */
00374   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00375 }
00376
00377 /**
00378   * @brief  Sets Pending bit of an external interrupt.
00379   * @param  IRQn External interrupt number
00380   *         This parameter can be an enumerator of IRQn_Type enumeration
00381   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00382   * @retval None
00383   */
00384 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00385 {
00386   /* Check the parameters */
00387   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00388
00389   /* Set interrupt pending */
00390   NVIC_SetPendingIRQ(IRQn);
00391 }
00392
00393 /**
00394   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00395   *         and returns the pending bit for the specified interrupt).
00396   * @param  IRQn External interrupt number.
00397   *          This parameter can be an enumerator of IRQn_Type enumeration
00398   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00399   * @retval status  - 0  Interrupt status is not pending.
00400   *                 - 1  Interrupt status is pending.
00401   */
00402 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00403 {
00404   /* Check the parameters */
00405   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00406
00407   /* Return 1 if pending else 0 */
00408   return NVIC_GetPendingIRQ(IRQn);
00409 }
00410
00411 /**
00412   * @brief  Clears the pending bit of an external interrupt.
00413   * @param  IRQn External interrupt number.
00414   *         This parameter can be an enumerator of IRQn_Type enumeration
00415   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00416   * @retval None
00417   */
00418 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00419 {
00420   /* Check the parameters */
00421   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00422
00423   /* Clear pending interrupt */
00424   NVIC_ClearPendingIRQ(IRQn);
00425 }
00426
00427 /**
00428   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00429   * @param IRQn External interrupt number
00430   *         This parameter can be an enumerator of IRQn_Type enumeration
00431   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00432   * @retval status  - 0  Interrupt status is not pending.
00433   *                 - 1  Interrupt status is pending.
00434   */
00435 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00436 {
00437   /* Check the parameters */
00438   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00439
00440   /* Return 1 if active else 0 */
00441   return NVIC_GetActive(IRQn);
00442 }
00443
00444 /**
00445   * @brief  Configures the SysTick clock source.
00446   * @param  CLKSource specifies the SysTick clock source.
00447   *         This parameter can be one of the following values:
00448   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00449   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00450   * @retval None
00451   */
00452 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00453 {
00454   /* Check the parameters */
00455   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00456   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00457   {
00458     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00459   }
00460   else
00461   {
00462     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00463   }
00464 }
00465
00466 /**
00467   * @brief  This function handles SYSTICK interrupt request.
00468   * @retval None
00469   */
00470 void HAL_SYSTICK_IRQHandler(void)
00471 {
00472   HAL_SYSTICK_Callback();
00473 }
00474
00475 /**
00476   * @brief  SYSTICK callback.
00477   * @retval None
00478   */
00479 __weak void HAL_SYSTICK_Callback(void)
00480 {
00481   /* NOTE : This function Should not be modified, when the callback is needed,
00482             the HAL_SYSTICK_Callback could be implemented in the user file
00483    */
00484 }
00485
00486 #if defined(DUAL_CORE)
00487
00488 /**
00489   * @brief  Returns the current CPU ID.
00490   * @retval CPU identifier
00491   */
00492 uint32_t HAL_GetCurrentCPUID(void)
00493 {
00494   if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
00495   {
00496     return  CM7_CPUID;
00497   }
00498   else
00499   {
00500     return CM4_CPUID;
00501   }
00502 }
00503
00504 #else
00505
00506 /**
00507 * @brief  Returns the current CPU ID.
00508 * @retval CPU identifier
00509 */
00510 uint32_t HAL_GetCurrentCPUID(void)
00511 {
00512   return  CM7_CPUID;
00513 }
00514
00515 #endif /*DUAL_CORE*/
00516 /**
00517   * @}
00518   */
00519
00520 /**
00521   * @}
00522   */
00523
00524 #endif /* HAL_CORTEX_MODULE_ENABLED */
00525 /**
00526   * @}
00527   */
00528
00529 /**
00530   * @}
00531   */
00532
00533 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cortex.h Source File

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stm32h7xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CORTEX_H
00022 #define STM32H7xx_HAL_CORTEX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup CORTEX
00036   * @{
00037   */
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00040   * @{
00041   */
00042
00043 #if (__MPU_PRESENT == 1)
00044 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00045   * @brief  MPU Region initialization structure
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint8_t                Enable;                /*!< Specifies the status of the region.
00051                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00052   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00053                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00054   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00055   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00056                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00057   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00058                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00059   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00060                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00061   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00062                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00063   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00064                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00065   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00066                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00067   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00068                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00069   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00070                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00071 }MPU_Region_InitTypeDef;
00072 /**
00073   * @}
00074   */
00075 #endif /* __MPU_PRESENT */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported constants --------------------------------------------------------*/
00082
00083 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00088   * @{
00089   */
00090 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
00091                                                                  4 bits for subpriority */
00092 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
00093                                                                  3 bits for subpriority */
00094 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
00095                                                                  2 bits for subpriority */
00096 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
00097                                                                  1 bits for subpriority */
00098 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
00099                                                                  0 bits for subpriority */
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
00105   * @{
00106   */
00107 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
00108 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
00109
00110 /**
00111   * @}
00112   */
00113
00114 #if (__MPU_PRESENT == 1)
00115 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00116   * @{
00117   */
00118 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
00119 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
00120 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
00121 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00127   * @{
00128   */
00129 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
00130 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00136   * @{
00137   */
00138 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00139 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00145   * @{
00146   */
00147 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00148 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00154   * @{
00155   */
00156 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
00157 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00163   * @{
00164   */
00165 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
00166 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00172   * @{
00173   */
00174 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
00175 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
00176 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00182   * @{
00183   */
00184 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
00185 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
00186 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
00187 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
00188 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
00189 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
00190 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
00191 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
00192 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
00193 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
00194 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
00195 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
00196 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
00197 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
00198 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
00199 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
00200 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
00201 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
00202 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
00203 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
00204 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
00205 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
00206 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
00207 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
00208 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
00209 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
00210 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
00211 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00217   * @{
00218   */
00219 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
00220 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
00221 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
00222 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
00223 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
00224 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00230   * @{
00231   */
00232 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
00233 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
00234 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
00235 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
00236 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
00237 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
00238 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
00239 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
00240 #if !defined(CORE_CM4)
00241 #define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
00242 #define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
00243 #define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
00244 #define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
00245 #define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
00246 #define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
00247 #define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
00248 #define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
00249 #endif /* !defined(CORE_CM4) */
00250
00251 /**
00252   * @}
00253   */
00254 #endif /* __MPU_PRESENT */
00255
00256 /**
00257   * @}
00258   */
00259
00260
00261 /* Exported Macros -----------------------------------------------------------*/
00262 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00263   * @{
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270
00271
00272 /** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
00273   * @{
00274   */
00275 #define CM7_CPUID        ((uint32_t)0x00000003)
00276
00277 #if defined(DUAL_CORE)
00278 #define CM4_CPUID        ((uint32_t)0x00000001)
00279 #endif /*DUAL_CORE*/
00280 /**
00281   * @}
00282   */
00283
00284
00285 /* Exported functions --------------------------------------------------------*/
00286 /** @addtogroup CORTEX_Exported_Functions
00287   * @{
00288   */
00289
00290 /** @addtogroup CORTEX_Exported_Functions_Group1
00291  * @{
00292  */
00293 /* Initialization and de-initialization functions *****************************/
00294 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00295 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00296 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00297 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00298 void HAL_NVIC_SystemReset(void);
00299 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00300 /**
00301   * @}
00302   */
00303
00304 /** @addtogroup CORTEX_Exported_Functions_Group2
00305  * @{
00306  */
00307 /* Peripheral Control functions ***********************************************/
00308 #if (__MPU_PRESENT == 1)
00309 void HAL_MPU_Enable(uint32_t MPU_Control);
00310 void HAL_MPU_Disable(void);
00311 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00312 #endif /* __MPU_PRESENT */
00313 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00314 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00315 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00316 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00317 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00318 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00319 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00320 void HAL_SYSTICK_IRQHandler(void);
00321 void HAL_SYSTICK_Callback(void);
00322 uint32_t HAL_GetCurrentCPUID(void);
00323
00324
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /* Private types -------------------------------------------------------------*/
00334 /* Private variables ---------------------------------------------------------*/
00335 /* Private constants ---------------------------------------------------------*/
00336 /* Private macros ------------------------------------------------------------*/
00337 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00338   * @{
00339   */
00340 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00341                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00342                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00343                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00344                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00345
00346 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
00347
00348 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
00349
00350 #define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
00351
00352 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00353                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00354
00355 #if (__MPU_PRESENT == 1)
00356 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00357                                      ((STATE) == MPU_REGION_DISABLE))
00358
00359 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00360                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00361
00362 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00363                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00364
00365 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00366                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00367
00368 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00369                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00370
00371 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00372                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00373                                 ((TYPE) == MPU_TEX_LEVEL2))
00374
00375 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00376                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00377                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00378                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00379                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00380                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00381
00382 #if !defined(CORE_CM4)
00383 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
00384                                          ((NUMBER) == MPU_REGION_NUMBER1)  || \
00385                                          ((NUMBER) == MPU_REGION_NUMBER2)  || \
00386                                          ((NUMBER) == MPU_REGION_NUMBER3)  || \
00387                                          ((NUMBER) == MPU_REGION_NUMBER4)  || \
00388                                          ((NUMBER) == MPU_REGION_NUMBER5)  || \
00389                                          ((NUMBER) == MPU_REGION_NUMBER6)  || \
00390                                          ((NUMBER) == MPU_REGION_NUMBER7)  || \
00391                                          ((NUMBER) == MPU_REGION_NUMBER8)  || \
00392                                          ((NUMBER) == MPU_REGION_NUMBER9)  || \
00393                                          ((NUMBER) == MPU_REGION_NUMBER10) || \
00394                                          ((NUMBER) == MPU_REGION_NUMBER11) || \
00395                                          ((NUMBER) == MPU_REGION_NUMBER12) || \
00396                                          ((NUMBER) == MPU_REGION_NUMBER13) || \
00397                                          ((NUMBER) == MPU_REGION_NUMBER14) || \
00398                                          ((NUMBER) == MPU_REGION_NUMBER15))
00399 #else
00400 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
00401                                          ((NUMBER) == MPU_REGION_NUMBER1)  || \
00402                                          ((NUMBER) == MPU_REGION_NUMBER2)  || \
00403                                          ((NUMBER) == MPU_REGION_NUMBER3)  || \
00404                                          ((NUMBER) == MPU_REGION_NUMBER4)  || \
00405                                          ((NUMBER) == MPU_REGION_NUMBER5)  || \
00406                                          ((NUMBER) == MPU_REGION_NUMBER6)  || \
00407                                          ((NUMBER) == MPU_REGION_NUMBER7))
00408 #endif /* !defined(CORE_CM4) */
00409
00410 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00411                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00412                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00413                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00414                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00415                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00416                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00417                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00418                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00419                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00420                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00421                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00422                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00423                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00424                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00425                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00426                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00427                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00428                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00429                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00430                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00431                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00432                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00433                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00434                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00435                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00436                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00437                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00438
00439 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00440 #endif /* __MPU_PRESENT */
00441
00442 /**
00443   * @}
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453
00454 #ifdef __cplusplus
00455 }
00456 #endif
00457
00458 #endif /* STM32H7xx_HAL_CORTEX_H */
00459
00460
00461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc.c Source File

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stm32h7xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013  ===============================================================================
00014                      ##### How to use this driver #####
00015  ===============================================================================
00016     [..]
00017          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00018          (+) Initialize CRC calculator
00019              (++) specify generating polynomial (peripheral default or non-default one)
00020              (++) specify initialization value (peripheral default or non-default one)
00021              (++) specify input data format
00022              (++) specify input or output data inversion mode if any
00023          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00024              input data buffer starting with the previously computed CRC as
00025              initialization value
00026          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00027              input data buffer starting with the defined initialization value
00028              (default or non-default) to initiate CRC calculation
00029
00030   @endverbatim
00031   ******************************************************************************
00032   * @attention
00033   *
00034   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00035   * All rights reserved.</center></h2>
00036   *
00037   * This software component is licensed by ST under BSD 3-Clause license,
00038   * the "License"; You may not use this file except in compliance with the
00039   * License. You may obtain a copy of the License at:
00040   *                        opensource.org/licenses/BSD-3-Clause
00041   *
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32h7xx_hal.h"
00047
00048 /** @addtogroup STM32H7xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup CRC CRC
00053   * @brief CRC HAL module driver.
00054   * @{
00055   */
00056
00057 #ifdef HAL_CRC_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /** @defgroup CRC_Private_Functions CRC Private Functions
00065  * @{
00066  */
00067 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00068 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00069 /**
00070   * @}
00071   */
00072
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00080  *  @brief    Initialization and Configuration functions.
00081  *
00082 @verbatim
00083  ===============================================================================
00084             ##### Initialization and de-initialization functions #####
00085  ===============================================================================
00086     [..]  This section provides functions allowing to:
00087       (+) Initialize the CRC according to the specified parameters
00088           in the CRC_InitTypeDef and create the associated handle
00089       (+) DeInitialize the CRC peripheral
00090       (+) Initialize the CRC MSP (MCU Specific Package)
00091       (+) DeInitialize the CRC MSP
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Initialize the CRC according to the specified
00099   *         parameters in the CRC_InitTypeDef and create the associated handle.
00100   * @param  hcrc CRC handle
00101   * @retval HAL status
00102   */
00103 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00104 {
00105   /* Check the CRC handle allocation */
00106   if (hcrc == NULL)
00107   {
00108     return HAL_ERROR;
00109   }
00110
00111   /* Check the parameters */
00112   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00113
00114   if (hcrc->State == HAL_CRC_STATE_RESET)
00115   {
00116     /* Allocate lock resource and initialize it */
00117     hcrc->Lock = HAL_UNLOCKED;
00118     /* Init the low level hardware */
00119     HAL_CRC_MspInit(hcrc);
00120   }
00121
00122   hcrc->State = HAL_CRC_STATE_BUSY;
00123
00124   /* check whether or not non-default generating polynomial has been
00125    * picked up by user */
00126   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00127   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00128   {
00129     /* initialize peripheral with default generating polynomial */
00130     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00131     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00132   }
00133   else
00134   {
00135     /* initialize CRC peripheral with generating polynomial defined by user */
00136     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00137     {
00138       return HAL_ERROR;
00139     }
00140   }
00141
00142   /* check whether or not non-default CRC initial value has been
00143    * picked up by user */
00144   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00145   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00146   {
00147     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00148   }
00149   else
00150   {
00151     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00152   }
00153
00154
00155   /* set input data inversion mode */
00156   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00157   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00158
00159   /* set output data inversion mode */
00160   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00161   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00162
00163   /* makes sure the input data format (bytes, halfwords or words stream)
00164    * is properly specified by user */
00165   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00166
00167   /* Change CRC peripheral state */
00168   hcrc->State = HAL_CRC_STATE_READY;
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  DeInitialize the CRC peripheral.
00176   * @param  hcrc CRC handle
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00180 {
00181   /* Check the CRC handle allocation */
00182   if (hcrc == NULL)
00183   {
00184     return HAL_ERROR;
00185   }
00186
00187   /* Check the parameters */
00188   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00189
00190   /* Check the CRC peripheral state */
00191   if (hcrc->State == HAL_CRC_STATE_BUSY)
00192   {
00193     return HAL_BUSY;
00194   }
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_BUSY;
00198
00199   /* Reset CRC calculation unit */
00200   __HAL_CRC_DR_RESET(hcrc);
00201
00202   /* Reset IDR register content */
00203   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00204
00205   /* DeInit the low level hardware */
00206   HAL_CRC_MspDeInit(hcrc);
00207
00208   /* Change CRC peripheral state */
00209   hcrc->State = HAL_CRC_STATE_RESET;
00210
00211   /* Process unlocked */
00212   __HAL_UNLOCK(hcrc);
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Initializes the CRC MSP.
00220   * @param  hcrc CRC handle
00221   * @retval None
00222   */
00223 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hcrc);
00227
00228   /* NOTE : This function should not be modified, when the callback is needed,
00229             the HAL_CRC_MspInit can be implemented in the user file
00230    */
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the CRC MSP.
00235   * @param  hcrc CRC handle
00236   * @retval None
00237   */
00238 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00239 {
00240   /* Prevent unused argument(s) compilation warning */
00241   UNUSED(hcrc);
00242
00243   /* NOTE : This function should not be modified, when the callback is needed,
00244             the HAL_CRC_MspDeInit can be implemented in the user file
00245    */
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00253  *  @brief    management functions.
00254  *
00255 @verbatim
00256  ===============================================================================
00257                       ##### Peripheral Control functions #####
00258  ===============================================================================
00259     [..]  This section provides functions allowing to:
00260       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00261           using combination of the previous CRC value and the new one.
00262
00263        [..]  or
00264
00265       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00266           independently of the previous CRC value.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00274   *         starting with the previously computed CRC as initialization value.
00275   * @param  hcrc CRC handle
00276   * @param  pBuffer pointer to the input data buffer, exact input data format is
00277   *         provided by hcrc->InputDataFormat.
00278   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00279   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00280   *         number of words if pBuffer type is * uint32_t).
00281   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00282   *        Input buffer pointers with other types simply need to be cast in uint32_t
00283   *        and the API will internally adjust its input data processing based on the
00284   *        handle field hcrc->InputDataFormat.
00285   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00286   */
00287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00288 {
00289   uint32_t index;      /* CRC input data buffer index */
00290   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00291
00292   /* Change CRC peripheral state */
00293   hcrc->State = HAL_CRC_STATE_BUSY;
00294
00295   switch (hcrc->InputDataFormat)
00296   {
00297     case CRC_INPUTDATA_FORMAT_WORDS:
00298       /* Enter Data to the CRC calculator */
00299       for (index = 0U; index < BufferLength; index++)
00300       {
00301         hcrc->Instance->DR = pBuffer[index];
00302       }
00303       temp = hcrc->Instance->DR;
00304       break;
00305
00306     case CRC_INPUTDATA_FORMAT_BYTES:
00307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00308       break;
00309
00310     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00312       break;
00313     default:
00314       break;
00315   }
00316
00317   /* Change CRC peripheral state */
00318   hcrc->State = HAL_CRC_STATE_READY;
00319
00320   /* Return the CRC computed value */
00321   return temp;
00322 }
00323
00324 /**
00325   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00326   *         starting with hcrc->Instance->INIT as initialization value.
00327   * @param  hcrc CRC handle
00328   * @param  pBuffer pointer to the input data buffer, exact input data format is
00329   *         provided by hcrc->InputDataFormat.
00330   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00331   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00332   *         number of words if pBuffer type is * uint32_t).
00333   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00334   *        Input buffer pointers with other types simply need to be cast in uint32_t
00335   *        and the API will internally adjust its input data processing based on the
00336   *        handle field hcrc->InputDataFormat.
00337   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00338   */
00339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00340 {
00341   uint32_t index;      /* CRC input data buffer index */
00342   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00343
00344   /* Change CRC peripheral state */
00345   hcrc->State = HAL_CRC_STATE_BUSY;
00346
00347   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00348   *  written in hcrc->Instance->DR) */
00349   __HAL_CRC_DR_RESET(hcrc);
00350
00351   switch (hcrc->InputDataFormat)
00352   {
00353     case CRC_INPUTDATA_FORMAT_WORDS:
00354       /* Enter 32-bit input data to the CRC calculator */
00355       for (index = 0U; index < BufferLength; index++)
00356       {
00357         hcrc->Instance->DR = pBuffer[index];
00358       }
00359       temp = hcrc->Instance->DR;
00360       break;
00361
00362     case CRC_INPUTDATA_FORMAT_BYTES:
00363       /* Specific 8-bit input data handling  */
00364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00365       break;
00366
00367     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00368       /* Specific 16-bit input data handling  */
00369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00370       break;
00371
00372     default:
00373       break;
00374   }
00375
00376   /* Change CRC peripheral state */
00377   hcrc->State = HAL_CRC_STATE_READY;
00378
00379   /* Return the CRC computed value */
00380   return temp;
00381 }
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00388  *  @brief    Peripheral State functions.
00389  *
00390 @verbatim
00391  ===============================================================================
00392                       ##### Peripheral State functions #####
00393  ===============================================================================
00394     [..]
00395     This subsection permits to get in run-time the status of the peripheral.
00396
00397 @endverbatim
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Return the CRC handle state.
00403   * @param  hcrc CRC handle
00404   * @retval HAL state
00405   */
00406 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00407 {
00408   /* Return CRC handle state */
00409   return hcrc->State;
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup CRC_Private_Functions
00421  * @{
00422  */
00423
00424 /**
00425   * @brief  Enter 8-bit input data to the CRC calculator.
00426   *         Specific data handling to optimize processing time.
00427   * @param  hcrc CRC handle
00428   * @param  pBuffer pointer to the input data buffer
00429   * @param  BufferLength input data buffer length
00430   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00431   */
00432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00433 {
00434   uint32_t i; /* input data buffer index */
00435   uint16_t data;
00436   __IO uint16_t *pReg;
00437
00438   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00439    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00440    * handling by the peripheral */
00441   for (i = 0U; i < (BufferLength / 4U); i++)
00442   {
00443     hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
00444                          ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
00445                          ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
00446                          (uint32_t)pBuffer[(4U * i) + 3U];
00447   }
00448   /* last bytes specific handling */
00449   if ((BufferLength % 4U) != 0U)
00450   {
00451     if ((BufferLength % 4U) == 1U)
00452     {
00453       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
00454     }
00455     if ((BufferLength % 4U) == 2U)
00456     {
00457       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00458       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00459       *pReg = data;
00460     }
00461     if ((BufferLength % 4U) == 3U)
00462     {
00463       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00464       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00465       *pReg = data;
00466
00467       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
00468     }
00469   }
00470
00471   /* Return the CRC computed value */
00472   return hcrc->Instance->DR;
00473 }
00474
00475 /**
00476   * @brief  Enter 16-bit input data to the CRC calculator.
00477   *         Specific data handling to optimize processing time.
00478   * @param  hcrc CRC handle
00479   * @param  pBuffer pointer to the input data buffer
00480   * @param  BufferLength input data buffer length
00481   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00482   */
00483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00484 {
00485   uint32_t i;  /* input data buffer index */
00486   __IO uint16_t *pReg;
00487
00488   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00489    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00490    * a correct type handling by the peripheral */
00491   for (i = 0U; i < (BufferLength / 2U); i++)
00492   {
00493     hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
00494   }
00495   if ((BufferLength % 2U) != 0U)
00496   {
00497     pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
00498     *pReg = pBuffer[2U * i];
00499   }
00500
00501   /* Return the CRC computed value */
00502   return hcrc->Instance->DR;
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 #endif /* HAL_CRC_MODULE_ENABLED */
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc.h Source File

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stm32h7xx_hal_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CRC_H
00022 #define STM32H7xx_HAL_CRC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup CRC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup CRC_Exported_Types CRC Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  CRC HAL State Structure definition
00046   */
00047 typedef enum
00048 {
00049   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00050   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00051   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00052   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00053   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00054 } HAL_CRC_StateTypeDef;
00055
00056 /**
00057   * @brief CRC Init Structure definition
00058   */
00059 typedef struct
00060 {
00061   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00062                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00063                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
00064                                             In that case, there is no need to set GeneratingPolynomial field.
00065                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
00066
00067   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00068                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00069                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00070                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
00071
00072   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
00073                                            respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
00074                                            e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
00075                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
00076
00077   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00078                                            Value can be either one of
00079                                            @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
00080                                            @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
00081                                            @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
00082                                            @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
00083
00084   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00085                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00086
00087   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00088                                            Can be either one of the following values
00089                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
00090                                            @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00091                                            @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00092                                            @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
00093
00094   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00095                                             Can be either
00096                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
00097                                             @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
00098 } CRC_InitTypeDef;
00099
00100 /**
00101   * @brief  CRC Handle Structure definition
00102   */
00103 typedef struct
00104 {
00105   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00106
00107   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00108
00109   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00110
00111   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00112
00113   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00114                                             Can be either
00115                                             @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
00116                                             @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
00117                                             @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
00118
00119                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00120                                            must occur if InputBufferFormat is not one of the three values listed above  */
00121 } CRC_HandleTypeDef;
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00132   * @{
00133   */
00134 #define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00140   * @{
00141   */
00142 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00148   * @{
00149   */
00150 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
00151 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00157   * @{
00158   */
00159 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
00160 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
00166   * @{
00167   */
00168 #define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
00169 #define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
00170 #define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
00171 #define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00177   * @{
00178   */
00179 #define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
00180 #define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
00181 #define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
00182 #define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00188   * @{
00189   */
00190 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00191  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00192  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00193  * the CRC APIs to provide a correct result */
00194 #define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
00195 #define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
00196 #define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
00197 #define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup CRC_Aliases CRC API aliases
00203   * @{
00204   */
00205 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
00206 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported macros -----------------------------------------------------------*/
00216 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00217   * @{
00218   */
00219
00220 /** @brief Reset CRC handle state.
00221   * @param  __HANDLE__ CRC handle.
00222   * @retval None
00223   */
00224 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00225
00226 /**
00227   * @brief  Reset CRC Data Register.
00228   * @param  __HANDLE__ CRC handle
00229   * @retval None
00230   */
00231 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00232
00233 /**
00234   * @brief  Set CRC INIT non-default value
00235   * @param  __HANDLE__ CRC handle
00236   * @param  __INIT__ 32-bit initial value
00237   * @retval None
00238   */
00239 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00240
00241 /**
00242   * @brief Store data in the Independent Data (ID) register.
00243   * @param __HANDLE__ CRC handle
00244   * @param __VALUE__  Value to be stored in the ID register
00245   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00246   * @retval None
00247   */
00248 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00249
00250 /**
00251   * @brief Return the data stored in the Independent Data (ID) register.
00252   * @param __HANDLE__ CRC handle
00253   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00254   * @retval Value of the ID register
00255   */
00256 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00257 /**
00258   * @}
00259   */
00260
00261
00262 /* Private macros --------------------------------------------------------*/
00263 /** @defgroup  CRC_Private_Macros CRC Private Macros
00264   * @{
00265   */
00266
00267 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00268                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00269
00270 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00271                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00272
00273 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00274                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00275                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00276                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00277
00278 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
00279                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00280                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00281
00282 /**
00283   * @}
00284   */
00285
00286 /* Include CRC HAL Extended module */
00287 #include "stm32h7xx_hal_crc_ex.h"
00288
00289 /* Exported functions --------------------------------------------------------*/
00290 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00291   * @{
00292   */
00293
00294 /* Initialization and de-initialization functions  ****************************/
00295 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00296   * @{
00297   */
00298 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00299 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
00300 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00301 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00302 /**
00303   * @}
00304   */
00305
00306 /* Peripheral Control functions ***********************************************/
00307 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00308   * @{
00309   */
00310 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00311 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00312 /**
00313   * @}
00314   */
00315
00316 /* Peripheral State and Error functions ***************************************/
00317 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00318   * @{
00319   */
00320 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 #ifdef __cplusplus
00338 }
00339 #endif
00340
00341 #endif /* STM32H7xx_HAL_CRC_H */
00342
00343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc_ex.c Source File

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stm32h7xx_hal_crc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the CRC peripheral.
00008   *
00009   @verbatim
00010 ================================================================================
00011             ##### How to use this driver #####
00012 ================================================================================
00013     [..]
00014          (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
00015          (+) Configure Input or Output data inversion
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32h7xx_hal.h"
00034
00035 /** @addtogroup STM32H7xx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup CRCEx CRCEx
00040   * @brief CRC Extended HAL module driver
00041   * @{
00042   */
00043
00044 #ifdef HAL_CRC_MODULE_ENABLED
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 /* Private define ------------------------------------------------------------*/
00048 /* Private macro -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private function prototypes -----------------------------------------------*/
00051 /* Exported functions --------------------------------------------------------*/
00052
00053 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00054   * @{
00055   */
00056
00057 /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00058   * @brief    Extended Initialization and Configuration functions.
00059   *
00060 @verbatim
00061  ===============================================================================
00062             ##### Extended configuration functions #####
00063  ===============================================================================
00064     [..]  This section provides functions allowing to:
00065       (+) Configure the generating polynomial
00066       (+) Configure the input data inversion
00067       (+) Configure the output data inversion
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073
00074 /**
00075   * @brief  Initialize the CRC polynomial if different from default one.
00076   * @param  hcrc CRC handle
00077   * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
00078   *         This parameter is written in normal representation, e.g.
00079   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00080   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00081   * @param  PolyLength CRC polynomial length.
00082   *         This parameter can be one of the following values:
00083   *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
00084   *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
00085   *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
00086   *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
00087   * @retval HAL status
00088   */
00089 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00090 {
00091   HAL_StatusTypeDef status = HAL_OK;
00092   uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
00093
00094   /* Check the parameters */
00095   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00096
00097   /* check polynomial definition vs polynomial size:
00098    * polynomial length must be aligned with polynomial
00099    * definition. HAL_ERROR is reported if Pol degree is
00100    * larger than that indicated by PolyLength.
00101    * Look for MSB position: msb will contain the degree of
00102    *  the second to the largest polynomial member. E.g., for
00103    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00104   while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
00105   {
00106   }
00107
00108   switch (PolyLength)
00109   {
00110     case CRC_POLYLENGTH_7B:
00111       if (msb >= HAL_CRC_LENGTH_7B)
00112       {
00113         status =   HAL_ERROR;
00114       }
00115       break;
00116     case CRC_POLYLENGTH_8B:
00117       if (msb >= HAL_CRC_LENGTH_8B)
00118       {
00119         status =   HAL_ERROR;
00120       }
00121       break;
00122     case CRC_POLYLENGTH_16B:
00123       if (msb >= HAL_CRC_LENGTH_16B)
00124       {
00125         status =   HAL_ERROR;
00126       }
00127       break;
00128
00129     case CRC_POLYLENGTH_32B:
00130       /* no polynomial definition vs. polynomial length issue possible */
00131       break;
00132     default:
00133       status =  HAL_ERROR;
00134       break;
00135   }
00136   if (status == HAL_OK)
00137   {
00138     /* set generating polynomial */
00139     WRITE_REG(hcrc->Instance->POL, Pol);
00140
00141     /* set generating polynomial size */
00142     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00143   }
00144   /* Return function status */
00145   return status;
00146 }
00147
00148 /**
00149   * @brief  Set the Reverse Input data mode.
00150   * @param  hcrc CRC handle
00151   * @param  InputReverseMode Input Data inversion mode.
00152   *         This parameter can be one of the following values:
00153   *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
00154   *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
00155   *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
00156   *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00160 {
00161   /* Check the parameters */
00162   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00163
00164   /* Change CRC peripheral state */
00165   hcrc->State = HAL_CRC_STATE_BUSY;
00166
00167   /* set input data inversion mode */
00168   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00169   /* Change CRC peripheral state */
00170   hcrc->State = HAL_CRC_STATE_READY;
00171
00172   /* Return function status */
00173   return HAL_OK;
00174 }
00175
00176 /**
00177   * @brief  Set the Reverse Output data mode.
00178   * @param  hcrc CRC handle
00179   * @param  OutputReverseMode Output Data inversion mode.
00180   *         This parameter can be one of the following values:
00181   *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
00182   *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00183   * @retval HAL status
00184   */
00185 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00189
00190   /* Change CRC peripheral state */
00191   hcrc->State = HAL_CRC_STATE_BUSY;
00192
00193   /* set output data inversion mode */
00194   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_READY;
00198
00199   /* Return function status */
00200   return HAL_OK;
00201 }
00202
00203
00204
00205
00206 /**
00207   * @}
00208   */
00209
00210
00211 /**
00212   * @}
00213   */
00214
00215
00216 #endif /* HAL_CRC_MODULE_ENABLED */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_crc_ex.h Source File

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stm32h7xx_hal_crc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CRC_EX_H
00022 #define STM32H7xx_HAL_CRC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup CRCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
00046   * @{
00047   */
00048 #define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
00049 #define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
00050 #define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
00051 #define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
00052 /**
00053   * @}
00054   */
00055
00056 /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
00057   * @{
00058   */
00059 #define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
00060 #define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
00061 /**
00062   * @}
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Exported macro ------------------------------------------------------------*/
00070 /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Set CRC output reversal
00076   * @param  __HANDLE__ CRC handle
00077   * @retval None
00078   */
00079 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00080
00081 /**
00082   * @brief  Unset CRC output reversal
00083   * @param  __HANDLE__ CRC handle
00084   * @retval None
00085   */
00086 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00087
00088 /**
00089   * @brief  Set CRC non-default polynomial
00090   * @param  __HANDLE__ CRC handle
00091   * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
00092   * @retval None
00093   */
00094 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Private macros --------------------------------------------------------*/
00101 /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
00102   * @{
00103   */
00104
00105 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
00106                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
00107                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00108                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00109
00110 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00111                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions --------------------------------------------------------*/
00118
00119 /** @addtogroup CRCEx_Exported_Functions
00120   * @{
00121   */
00122
00123 /** @addtogroup CRCEx_Exported_Functions_Group1
00124   * @{
00125   */
00126 /* Initialization and de-initialization functions  ****************************/
00127 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00128 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00129 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00130
00131 /**
00132   * @}
00133   */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /**
00144   * @}
00145   */
00146
00147 #ifdef __cplusplus
00148 }
00149 #endif
00150
00151 #endif /* STM32H7xx_HAL_CRC_EX_H */
00152
00153 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp.c Source File

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stm32h7xx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @brief   CRYP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cryptography (CRYP) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + AES processing functions
00010   *           + DES processing functions
00011   *           + TDES processing functions
00012   *           + DMA callback functions
00013   *           + CRYP IRQ handler management
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       The CRYP HAL driver can be used in CRYP IP as follows:
00022
00023       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00024          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00025          (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
00026              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00027              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00028              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00029          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
00030              (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
00031              (+++) Configure and enable two DMA streams one for managing data transfer from
00032                  memory to peripheral (input stream) and another stream for managing data
00033                  transfer from peripheral to memory (output stream)
00034              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00035                  using  __HAL_LINKDMA()
00036              (+++) Configure the priority and enable the NVIC for the transfer complete
00037                  interrupt on the two DMA Streams. The output stream should have higher
00038                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00039
00040       (#)Initialize the CRYP according to the specified parameters :
00041          (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
00042          (##) The key size: 128, 192 or 256.
00043          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
00044          (##) The initialization vector (counter). It is not used in ECB mode.
00045          (##) The key buffer used for encryption/decryption.
00046          (##) The Header used only in AES GCM and CCM Algorithm for authentication.
00047          (##) The HeaderSize The size of header buffer in word.
00048          (##) The B0 block is the first authentication block used only  in AES CCM mode.
00049
00050       (#)Three processing (encryption/decryption) functions are available:
00051          (##) Polling mode: encryption and decryption APIs are blocking functions
00052               i.e. they process the data and wait till the processing is finished,
00053               e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00054          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00055               i.e. they process the data under interrupt,
00056               e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00057          (##) DMA mode: encryption and decryption APIs are not blocking functions
00058               i.e. the data transfer is ensured by DMA,
00059               e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00060
00061       (#)When the processing function is called at first time after HAL_CRYP_Init()
00062          the CRYP peripheral is configured and processes the buffer in input.
00063          At second call, no need to Initialize the CRYP, user have to get current configuration via
00064          HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
00065          new parametres, finally user can  start encryption/decryption.
00066
00067        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00068
00069     [..]
00070       The cryptographic processor supports following standards:
00071       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
00072          (##)64-bit data block processing
00073          (##) chaining modes supported :
00074              (+++)  Electronic Code Book(ECB)
00075              (+++)  Cipher Block Chaining (CBC)
00076          (##) keys length supported :64-bit, 128-bit and 192-bit.
00077       (#) The advanced encryption standard (AES) supported  by CRYP1:
00078          (##)128-bit data block processing
00079          (##) chaining modes supported :
00080              (+++)  Electronic Code Book(ECB)
00081              (+++)  Cipher Block Chaining (CBC)
00082              (+++)  Counter mode (CTR)
00083              (+++)  Galois/counter mode (GCM/GMAC)
00084              (+++)  Counter with Cipher Block Chaining-Message(CCM)
00085          (##) keys length Supported :
00086              (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
00087
00088     [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
00089       (#)  Algorithm supported :
00090          (##) Galois/counter mode (GCM)
00091          (##) Galois message authentication code (GMAC) :is exactly the same as
00092               GCM algorithm composed only by an header.
00093       (#)  Four phases are performed in GCM :
00094          (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
00095          (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
00096           computation only.
00097          (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
00098           encryption + data XORing. It works in a similar way for ciphertext (C).
00099          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
00100       (#)  structure of message construction in GCM is defined as below  :
00101          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
00102          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
00103           this part of the message is only authenticated, not encrypted.
00104          (##) The plaintext message P is both authenticated and encrypted as ciphertext.
00105           GCM standard specifies that ciphertext has same bit length as the plaintext.
00106          (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
00107           (on 64 bits)
00108
00109     [..]  This section describe The AES Counter with Cipher Block Chaining-Message
00110           Authentication Code (CCM) supported by both CRYP1 IP:
00111       (#)  Specific parameters for CCM  :
00112
00113          (##) B0 block  : According to NIST Special Publication 800-38C,
00114             The first block B0 is formatted as follows, where l(m) is encoded in
00115             most-significant-byte first order(see below table 3)
00116
00117               (+++)  Q: a bit string representation of the octet length of P (plaintext)
00118               (+++)  q The octet length of the binary representation of the octet length of the payload
00119               (+++)  A nonce (N), n The octet length of the where n+q=15.
00120               (+++)  Flags: most significant octet containing four flags for control information,
00121               (+++)  t The octet length of the MAC.
00122          (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
00123               the associated data length expressed in bytes (a) defined as below:
00124             (+++)  If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
00125             (+++)  If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
00126             (+++)  If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
00127          (##) CTRx block  : control blocks
00128             (+++) Generation of CTR1 from first block B0 information :
00129               equal to B0 with first 5 bits zeroed and most significant bits storing octet
00130               length of P also zeroed, then incremented by one ( see below Table 4)
00131             (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
00132
00133       (#)  Four phases are performed in CCM for CRYP1 IP:
00134          (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
00135          (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
00136           computation only.
00137          (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
00138           encryption + data XORing. It works in a similar way for ciphertext (C).
00139          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
00140
00141   *** Callback registration ***
00142   =============================
00143
00144   [..]
00145   The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
00146   allows the user to configure dynamically the driver callbacks.
00147   Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
00148   to register an interrupt callback.
00149
00150   [..]
00151   Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
00152     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00153     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00154     (+) ErrorCallback      : callback for error detection.
00155     (+) MspInitCallback    : CRYP MspInit.
00156     (+) MspDeInitCallback  : CRYP MspDeInit.
00157   This function takes as parameters the HAL peripheral handle, the Callback ID
00158   and a pointer to the user callback function.
00159
00160   [..]
00161   Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
00162   weak function.
00163   @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00164   and the Callback ID.
00165   This function allows to reset following callbacks:
00166     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00167     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00168     (+) ErrorCallback      : callback for error detection.
00169     (+) MspInitCallback    : CRYP MspInit.
00170     (+) MspDeInitCallback  : CRYP MspDeInit.
00171
00172   [..]
00173   By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
00174   all callbacks are set to the corresponding weak functions :
00175   examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
00176   Exception done for MspInit and MspDeInit functions that are
00177   reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
00178   these callbacks are null (not registered beforehand).
00179   if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
00180   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00181
00182   [..]
00183   Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
00184   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00185   in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
00186   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00187   In that case first register the MspInit/MspDeInit user callbacks
00188   using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
00189   or @ref HAL_CRYP_Init() function.
00190
00191   [..]
00192   When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
00193   not defined, the callback registration feature is not available and all callbacks
00194   are set to the corresponding weak functions.
00195
00196   @endverbatim
00197
00198   Table 1. Initial Counter Block (ICB)
00199           +-------------------------------------------------------+
00200           |       Initialization vector (IV)      |  Counter      |
00201           |----------------|----------------|-----------|---------|
00202          127              95                63            31       0
00203
00204
00205               Bit Number    Register           Contents
00206               ----------   ---------------       -----------
00207               127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
00208               95  ...64    CRYP_IV1L[31:0]     B0[95:64]
00209               63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
00210               31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
00211
00212   Table 2.  GCM last block definition
00213
00214           +-------------------------------------------------------------------+
00215           |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
00216           |-----------|--------------------|-----------|----------------------|
00217           |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
00218           |-----------|--------------------|-----------|----------------------|
00219
00220   Table 3. B0 block
00221                 Octet Number   Contents
00222                 ------------   ---------
00223                 0              Flags
00224                 1 ... 15-q     Nonce N
00225                 16-q ... 15    Q
00226
00227             the Flags field is formatted as follows:
00228
00229                 Bit Number   Contents
00230                 ----------   ----------------------
00231                 7            Reserved (always zero)
00232                 6            Adata
00233                 5 ... 3      (t-2)/2
00234                 2 ... 0      [q-1]3
00235
00236  Table 4. CTRx block
00237                 Bit Number    Register           Contents
00238                 ----------   ---------------       -----------
00239                 127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
00240                                                  bit 0 that is set to 1
00241                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
00242                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
00243                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
00244
00245
00246   ******************************************************************************
00247   * @attention
00248   *
00249   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00250   * All rights reserved.</center></h2>
00251   *
00252   * This software component is licensed by ST under BSD 3-Clause license,
00253   * the "License"; You may not use this file except in compliance with the
00254   * License. You may obtain a copy of the License at:
00255   *                        opensource.org/licenses/BSD-3-Clause
00256   *
00257   ******************************************************************************
00258   */
00259
00260 /* Includes ------------------------------------------------------------------*/
00261 #include "stm32h7xx_hal.h"
00262
00263 /** @addtogroup STM32H7xx_HAL_Driver
00264   * @{
00265   */
00266
00267 #if defined (CRYP)
00268
00269 /** @defgroup CRYP CRYP
00270   * @brief CRYP HAL module driver.
00271   * @{
00272   */
00273
00274
00275 #ifdef HAL_CRYP_MODULE_ENABLED
00276
00277 /* Private typedef -----------------------------------------------------------*/
00278 /* Private define ------------------------------------------------------------*/
00279 /** @addtogroup CRYP_Private_Defines
00280   * @{
00281   */
00282 #define CRYP_TIMEOUT_KEYPREPARATION      82U         /*The latency of key preparation operation is 82 clock cycles.*/
00283 #define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /*  The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
00284 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /*  The latency of  GCM/CCM header phase is 290 clock cycles.*/
00285
00286 #define  CRYP_PHASE_READY                0x00000001U /*!< CRYP peripheral is ready for initialization. */
00287 #define  CRYP_PHASE_PROCESS              0x00000002U /*!< CRYP peripheral is in processing phase */
00288
00289 #define CRYP_PHASE_INIT                  0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
00290 #define CRYP_PHASE_HEADER                CRYP_CR_GCM_CCMPH_0     /*!< GCM/GMAC or CCM header phase */
00291 #define CRYP_PHASE_PAYLOAD               CRYP_CR_GCM_CCMPH_1     /*!< GCM(/CCM) payload phase      */
00292 #define CRYP_PHASE_FINAL                 CRYP_CR_GCM_CCMPH       /*!< GCM/GMAC or CCM  final phase */
00293 #define CRYP_OPERATINGMODE_ENCRYPT       0x00000000U             /*!< Encryption mode   */
00294 #define CRYP_OPERATINGMODE_DECRYPT       CRYP_CR_ALGODIR         /*!< Decryption        */
00295
00296
00297 /*  CTR1 information to use in CCM algorithm */
00298 #define CRYP_CCM_CTR1_0                  0x07FFFFFFU
00299 #define CRYP_CCM_CTR1_1                  0xFFFFFF00U
00300 #define CRYP_CCM_CTR1_2                  0x00000001U
00301
00302 /**
00303   * @}
00304   */
00305
00306
00307 /* Private macro -------------------------------------------------------------*/
00308 /** @addtogroup CRYP_Private_Macros
00309   * @{
00310   */
00311
00312 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
00313                                                         (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
00314                                                        }while(0)
00315
00316 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
00317
00318
00319 /**
00320   * @}
00321   */
00322
00323 /* Private struct -------------------------------------------------------------*/
00324 /* Private variables ---------------------------------------------------------*/
00325 /* Private function prototypes -----------------------------------------------*/
00326 /** @addtogroup CRYP_Private_Functions_prototypes
00327   * @{
00328   */
00329
00330 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00331 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00332 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00333 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00334 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
00335 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00336 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00337 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
00338 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
00339 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
00340 #if !defined (CRYP_VER_2_2)
00341 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00342 #endif /*End of not defined CRYP_VER_2_2*/
00343 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00344 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00345 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00346 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00347 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00348 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00349 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
00350 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00351 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00352 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
00353 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
00354 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
00355 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
00356 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00357 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00358 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00359 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported functions ---------------------------------------------------------*/
00366
00367 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00368   * @{
00369   */
00370
00371
00372 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00373   *  @brief    CRYP  Initialization and Configuration functions.
00374   *
00375 @verbatim
00376   ========================================================================================
00377      ##### Initialization, de-initialization and Set and Get configuration functions #####
00378   ========================================================================================
00379     [..]  This section provides functions allowing to:
00380       (+) Initialize the CRYP
00381       (+) DeInitialize the CRYP
00382       (+) Initialize the CRYP MSP
00383       (+) DeInitialize the CRYP MSP
00384       (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
00385           Parameters which are configured in This section are :
00386           (++) Key size
00387           (++) Data Type : 32,16, 8 or 1bit
00388           (++) AlgoMode : for CRYP1 IP
00389                  ECB and CBC in DES/TDES Standard
00390                  ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
00391       (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
00392
00393
00394 @endverbatim
00395   * @{
00396   */
00397
00398
00399 /**
00400   * @brief  Initializes the CRYP according to the specified
00401   *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
00402   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00403   *         the configuration information for CRYP module
00404   * @retval HAL status
00405   */
00406 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00407 {
00408   /* Check the CRYP handle allocation */
00409   if (hcryp == NULL)
00410   {
00411     return HAL_ERROR;
00412   }
00413
00414   /* Check parameters */
00415   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00416   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00417   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
00418
00419 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00420   if (hcryp->State == HAL_CRYP_STATE_RESET)
00421   {
00422     /* Allocate lock resource and initialize it */
00423     hcryp->Lock = HAL_UNLOCKED;
00424
00425     hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
00426     hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback  */
00427     hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy weak ErrorCallback    */
00428
00429     if (hcryp->MspInitCallback == NULL)
00430     {
00431       hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit  */
00432     }
00433
00434     /* Init the low level hardware */
00435     hcryp->MspInitCallback(hcryp);
00436   }
00437 #else
00438   if (hcryp->State == HAL_CRYP_STATE_RESET)
00439   {
00440     /* Allocate lock resource and initialize it */
00441     hcryp->Lock = HAL_UNLOCKED;
00442
00443     /* Init the low level hardware */
00444     HAL_CRYP_MspInit(hcryp);
00445   }
00446 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00447
00448   /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
00449   MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
00450              hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00451 #if !defined (CRYP_VER_2_2)
00452   /* Read Device ID to indicate CRYP1 IP Version */
00453   hcryp->Version = HAL_GetREVID();
00454 #endif /*End of not defined CRYP_VER_2_2*/
00455   /* Reset Error Code field */
00456   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00457
00458   /* Change the CRYP state */
00459   hcryp->State = HAL_CRYP_STATE_READY;
00460
00461   /* Set the default CRYP phase */
00462   hcryp->Phase = CRYP_PHASE_READY;
00463
00464   /* Return function status */
00465   return HAL_OK;
00466 }
00467
00468 /**
00469   * @brief  De-Initializes the CRYP peripheral.
00470   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00471   *         the configuration information for CRYP module
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00475 {
00476   /* Check the CRYP handle allocation */
00477   if (hcryp == NULL)
00478   {
00479     return HAL_ERROR;
00480   }
00481
00482   /* Set the default CRYP phase */
00483   hcryp->Phase = CRYP_PHASE_READY;
00484
00485   /* Reset CrypInCount and CrypOutCount */
00486   hcryp->CrypInCount = 0;
00487   hcryp->CrypOutCount = 0;
00488   hcryp->CrypHeaderCount = 0;
00489
00490   /* Disable the CRYP peripheral clock */
00491   __HAL_CRYP_DISABLE(hcryp);
00492
00493 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00494   if (hcryp->MspDeInitCallback == NULL)
00495   {
00496     hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit  */
00497   }
00498   /* DeInit the low level hardware */
00499   hcryp->MspDeInitCallback(hcryp);
00500
00501 #else
00502   /* DeInit the low level hardware: CLOCK, NVIC.*/
00503   HAL_CRYP_MspDeInit(hcryp);
00504 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00505
00506   /* Change the CRYP state */
00507   hcryp->State = HAL_CRYP_STATE_RESET;
00508
00509   /* Release Lock */
00510   __HAL_UNLOCK(hcryp);
00511
00512   /* Return function status */
00513   return HAL_OK;
00514 }
00515
00516 /**
00517   * @brief  Configure the CRYP according to the specified
00518   *         parameters in the CRYP_ConfigTypeDef
00519   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
00520   * @param  pConf: pointer to a CRYP_ConfigTypeDef structure that contains
00521   *         the configuration information for CRYP module
00522   * @retval HAL status
00523   */
00524 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00525 {
00526   /* Check the CRYP handle allocation */
00527   if ((hcryp == NULL) || (pConf == NULL))
00528   {
00529     return HAL_ERROR;
00530   }
00531
00532   /* Check parameters */
00533   assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
00534   assert_param(IS_CRYP_DATATYPE(pConf->DataType));
00535   assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
00536
00537   if (hcryp->State == HAL_CRYP_STATE_READY)
00538   {
00539     /* Change the CRYP state */
00540     hcryp->State = HAL_CRYP_STATE_BUSY;
00541
00542     /* Process locked */
00543     __HAL_LOCK(hcryp);
00544
00545     /* Set  CRYP parameters  */
00546     hcryp->Init.DataType     = pConf->DataType;
00547     hcryp->Init.pKey         = pConf->pKey;
00548     hcryp->Init.Algorithm    = pConf->Algorithm;
00549     hcryp->Init.KeySize      = pConf->KeySize;
00550     hcryp->Init.pInitVect    = pConf->pInitVect;
00551     hcryp->Init.Header       = pConf->Header;
00552     hcryp->Init.HeaderSize   = pConf->HeaderSize;
00553     hcryp->Init.B0           = pConf->B0;
00554     hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
00555
00556     /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type, AlgoMode and operating mode*/
00557     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
00558                hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00559
00560     /* Process Unlocked */
00561     __HAL_UNLOCK(hcryp);
00562
00563     /* Reset Error Code field */
00564     hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00565
00566     /* Change the CRYP state */
00567     hcryp->State = HAL_CRYP_STATE_READY;
00568
00569     /* Set the default CRYP phase */
00570     hcryp->Phase = CRYP_PHASE_READY;
00571
00572     /* Return function status */
00573     return HAL_OK;
00574   }
00575   else
00576   {
00577     /* Process Unlocked */
00578     __HAL_UNLOCK(hcryp);
00579
00580     /* Busy error code field */
00581     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00582     return HAL_ERROR;
00583   }
00584 }
00585
00586 /**
00587   * @brief  Get CRYP Configuration parameters in associated handle.
00588   * @param  pConf: pointer to a CRYP_ConfigTypeDef structure
00589   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00590   *         the configuration information for CRYP module
00591   * @retval HAL status
00592   */
00593 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00594 {
00595   /* Check the CRYP handle allocation */
00596   if ((hcryp == NULL) || (pConf == NULL))
00597   {
00598     return HAL_ERROR;
00599   }
00600
00601   if (hcryp->State == HAL_CRYP_STATE_READY)
00602   {
00603     /* Change the CRYP state */
00604     hcryp->State = HAL_CRYP_STATE_BUSY;
00605
00606     /* Process locked */
00607     __HAL_LOCK(hcryp);
00608
00609     /* Get  CRYP parameters  */
00610     pConf->DataType        = hcryp->Init.DataType;
00611     pConf->pKey            = hcryp->Init.pKey;
00612     pConf->Algorithm       = hcryp->Init.Algorithm;
00613     pConf->KeySize         = hcryp->Init.KeySize ;
00614     pConf->pInitVect       = hcryp->Init.pInitVect;
00615     pConf->Header          = hcryp->Init.Header ;
00616     pConf->HeaderSize      = hcryp->Init.HeaderSize;
00617     pConf->B0              = hcryp->Init.B0;
00618     pConf->DataWidthUnit    = hcryp->Init.DataWidthUnit;
00619
00620     /* Process Unlocked */
00621     __HAL_UNLOCK(hcryp);
00622
00623     /* Change the CRYP state */
00624     hcryp->State = HAL_CRYP_STATE_READY;
00625
00626     /* Return function status */
00627     return HAL_OK;
00628   }
00629   else
00630   {
00631     /* Process Unlocked */
00632     __HAL_UNLOCK(hcryp);
00633
00634     /* Busy error code field */
00635     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00636     return HAL_ERROR;
00637   }
00638 }
00639 /**
00640   * @brief  Initializes the CRYP MSP.
00641   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00642   *         the configuration information for CRYP module
00643   * @retval None
00644   */
00645 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00646 {
00647   /* Prevent unused argument(s) compilation warning */
00648   UNUSED(hcryp);
00649
00650   /* NOTE : This function Should not be modified, when the callback is needed,
00651             the HAL_CRYP_MspInit could be implemented in the user file
00652    */
00653 }
00654
00655 /**
00656   * @brief  DeInitializes CRYP MSP.
00657   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00658   *         the configuration information for CRYP module
00659   * @retval None
00660   */
00661 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00662 {
00663   /* Prevent unused argument(s) compilation warning */
00664   UNUSED(hcryp);
00665
00666   /* NOTE : This function Should not be modified, when the callback is needed,
00667             the HAL_CRYP_MspDeInit could be implemented in the user file
00668    */
00669 }
00670
00671 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00672 /**
00673   * @brief  Register a User CRYP Callback
00674   *         To be used instead of the weak predefined callback
00675   * @param hcryp cryp handle
00676   * @param CallbackID ID of the callback to be registered
00677   *        This parameter can be one of the following values:
00678   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00679   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00680   *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
00681   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00682   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00683   * @param pCallback pointer to the Callback function
00684   * @retval status
00685   */
00686 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
00687                                             pCRYP_CallbackTypeDef pCallback)
00688 {
00689   HAL_StatusTypeDef status = HAL_OK;
00690
00691   if (pCallback == NULL)
00692   {
00693     /* Update the error code */
00694     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00695
00696     return HAL_ERROR;
00697   }
00698   /* Process locked */
00699   __HAL_LOCK(hcryp);
00700
00701   if (hcryp->State == HAL_CRYP_STATE_READY)
00702   {
00703     switch (CallbackID)
00704     {
00705       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00706         hcryp->InCpltCallback = pCallback;
00707         break;
00708
00709       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00710         hcryp->OutCpltCallback = pCallback;
00711         break;
00712
00713       case HAL_CRYP_ERROR_CB_ID :
00714         hcryp->ErrorCallback = pCallback;
00715         break;
00716
00717       case HAL_CRYP_MSPINIT_CB_ID :
00718         hcryp->MspInitCallback = pCallback;
00719         break;
00720
00721       case HAL_CRYP_MSPDEINIT_CB_ID :
00722         hcryp->MspDeInitCallback = pCallback;
00723         break;
00724
00725       default :
00726         /* Update the error code */
00727         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00728         /* Return error status */
00729         status =  HAL_ERROR;
00730         break;
00731     }
00732   }
00733   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00734   {
00735     switch (CallbackID)
00736     {
00737       case HAL_CRYP_MSPINIT_CB_ID :
00738         hcryp->MspInitCallback = pCallback;
00739         break;
00740
00741       case HAL_CRYP_MSPDEINIT_CB_ID :
00742         hcryp->MspDeInitCallback = pCallback;
00743         break;
00744
00745       default :
00746         /* Update the error code */
00747         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00748         /* Return error status */
00749         status =  HAL_ERROR;
00750         break;
00751     }
00752   }
00753   else
00754   {
00755     /* Update the error code */
00756     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00757     /* Return error status */
00758     status =  HAL_ERROR;
00759   }
00760
00761   /* Release Lock */
00762   __HAL_UNLOCK(hcryp);
00763
00764   return status;
00765 }
00766
00767 /**
00768   * @brief  Unregister an CRYP Callback
00769   *         CRYP callabck is redirected to the weak predefined callback
00770   * @param hcryp cryp handle
00771   * @param CallbackID ID of the callback to be unregistered
00772   *        This parameter can be one of the following values:
00773   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00774   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00775   *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
00776   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00777   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00778   * @retval status
00779   */
00780 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
00781 {
00782   HAL_StatusTypeDef status = HAL_OK;
00783
00784   /* Process locked */
00785   __HAL_LOCK(hcryp);
00786
00787   if (hcryp->State == HAL_CRYP_STATE_READY)
00788   {
00789     switch (CallbackID)
00790     {
00791       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00792         hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
00793         break;
00794
00795       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00796         hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;         /* Legacy weak OutCpltCallback       */
00797         break;
00798
00799       case HAL_CRYP_ERROR_CB_ID :
00800         hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;           /* Legacy weak ErrorCallback        */
00801         break;
00802
00803       case HAL_CRYP_MSPINIT_CB_ID :
00804         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00805         break;
00806
00807       case HAL_CRYP_MSPDEINIT_CB_ID :
00808         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00809         break;
00810
00811       default :
00812         /* Update the error code */
00813         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00814         /* Return error status */
00815         status =  HAL_ERROR;
00816         break;
00817     }
00818   }
00819   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00820   {
00821     switch (CallbackID)
00822     {
00823       case HAL_CRYP_MSPINIT_CB_ID :
00824         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00825         break;
00826
00827       case HAL_CRYP_MSPDEINIT_CB_ID :
00828         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00829         break;
00830
00831       default :
00832         /* Update the error code */
00833         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00834         /* Return error status */
00835         status =  HAL_ERROR;
00836         break;
00837     }
00838   }
00839   else
00840   {
00841     /* Update the error code */
00842     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
00843     /* Return error status */
00844     status =  HAL_ERROR;
00845   }
00846
00847   /* Release Lock */
00848   __HAL_UNLOCK(hcryp);
00849
00850   return status;
00851 }
00852 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00853
00854 /**
00855   * @}
00856   */
00857
00858 /** @defgroup CRYP_Exported_Functions_Group2  Encrypt Decrypt functions
00859   *  @brief   CRYP processing functions.
00860   *
00861 @verbatim
00862   ==============================================================================
00863                       ##### Encrypt Decrypt  functions #####
00864   ==============================================================================
00865     [..]  This section provides API allowing to Encrypt/Decrypt Data following
00866           Standard DES/TDES or AES, and Algorithm configured by the user:
00867       (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
00868            (++)  Electronic Code Book(ECB)
00869            (++) Cipher Block Chaining (CBC)
00870       (+) Standard AES  supported by CRYP1 IP , list of Algorithm supported:
00871            (++) Electronic Code Book(ECB)
00872            (++) Cipher Block Chaining (CBC)
00873            (++) Counter mode (CTR)
00874            (++) Cipher Block Chaining (CBC)
00875            (++) Counter mode (CTR)
00876            (++) Galois/counter mode (GCM)
00877            (++) Counter with Cipher Block Chaining-Message(CCM)
00878     [..]  Three processing functions are available:
00879       (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00880       (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00881       (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00882
00883 @endverbatim
00884   * @{
00885   */
00886
00887
00888 /**
00889   * @brief  Encryption mode.
00890   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00891   *         the configuration information for CRYP module
00892   * @param  Input: Pointer to the input buffer (plaintext)
00893   * @param  Size: Length of the plaintext buffer in word.
00894   * @param  Output: Pointer to the output buffer(ciphertext)
00895   * @param  Timeout: Specify Timeout value
00896   * @retval HAL status
00897   */
00898 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
00899                                    uint32_t Timeout)
00900 {
00901   uint32_t algo;
00902   HAL_StatusTypeDef status;
00903
00904   if (hcryp->State == HAL_CRYP_STATE_READY)
00905   {
00906     /* Change state Busy */
00907     hcryp->State = HAL_CRYP_STATE_BUSY;
00908
00909     /* Process locked */
00910     __HAL_LOCK(hcryp);
00911
00912     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
00913     hcryp->CrypInCount = 0U;
00914     hcryp->CrypOutCount = 0U;
00915     hcryp->pCrypInBuffPtr = Input;
00916     hcryp->pCrypOutBuffPtr = Output;
00917
00918     /*  Calculate Size parameter in Byte*/
00919     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
00920     {
00921       hcryp->Size = Size * 4U;
00922     }
00923     else
00924     {
00925       hcryp->Size = Size;
00926     }
00927
00928     /* Set Encryption operating mode*/
00929     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
00930
00931     /* algo get algorithm selected */
00932     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
00933
00934     switch (algo)
00935     {
00936       case CRYP_DES_ECB:
00937       case CRYP_DES_CBC:
00938       case CRYP_TDES_ECB:
00939       case CRYP_TDES_CBC:
00940
00941         /*Set Key */
00942         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
00943         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
00944         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00945         {
00946           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
00947           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
00948           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
00949           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
00950         }
00951
00952         /*Set Initialization Vector (IV)*/
00953         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00954         {
00955           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
00956           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
00957         }
00958
00959         /* Flush FIFO */
00960         HAL_CRYP_FIFO_FLUSH(hcryp);
00961
00962         /* Set the phase */
00963         hcryp->Phase = CRYP_PHASE_PROCESS;
00964
00965         /* Statrt DES/TDES encryption process */
00966         status = CRYP_TDES_Process(hcryp, Timeout);
00967         break;
00968
00969       case CRYP_AES_ECB:
00970       case CRYP_AES_CBC:
00971       case CRYP_AES_CTR:
00972
00973         /* AES encryption */
00974         status = CRYP_AES_Encrypt(hcryp, Timeout);
00975         break;
00976
00977       case CRYP_AES_GCM:
00978
00979         /* AES GCM encryption */
00980         status = CRYP_AESGCM_Process(hcryp, Timeout);
00981         break;
00982
00983       case CRYP_AES_CCM:
00984
00985         /* AES CCM encryption */
00986         status = CRYP_AESCCM_Process(hcryp, Timeout);
00987         break;
00988
00989       default:
00990         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
00991         status = HAL_ERROR;
00992         break;
00993     }
00994
00995     if (status == HAL_OK)
00996     {
00997       /* Change the CRYP peripheral state */
00998       hcryp->State = HAL_CRYP_STATE_READY;
00999
01000       /* Process unlocked */
01001       __HAL_UNLOCK(hcryp);
01002     }
01003   }
01004   else
01005   {
01006     /* Process unlocked */
01007     __HAL_UNLOCK(hcryp);
01008
01009     /* Busy error code field */
01010     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01011     status = HAL_ERROR;
01012   }
01013
01014   /* Return function status */
01015   return status ;
01016 }
01017
01018 /**
01019   * @brief  Decryption mode.
01020   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01021   *         the configuration information for CRYP module
01022   * @param  Input: Pointer to the input buffer (ciphertext )
01023   * @param  Size: Length of the plaintext buffer in word.
01024   * @param  Output: Pointer to the output buffer(plaintext)
01025   * @param  Timeout: Specify Timeout value
01026   * @retval HAL status
01027   */
01028 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
01029                                    uint32_t Timeout)
01030 {
01031   HAL_StatusTypeDef status;
01032   uint32_t algo;
01033
01034   if (hcryp->State == HAL_CRYP_STATE_READY)
01035   {
01036     /* Change state Busy */
01037     hcryp->State = HAL_CRYP_STATE_BUSY;
01038
01039     /* Process locked */
01040     __HAL_LOCK(hcryp);
01041
01042     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01043     hcryp->CrypInCount = 0U;
01044     hcryp->CrypOutCount = 0U;
01045     hcryp->pCrypInBuffPtr = Input;
01046     hcryp->pCrypOutBuffPtr = Output;
01047
01048     /*  Calculate Size parameter in Byte*/
01049     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01050     {
01051       hcryp->Size = Size * 4U;
01052     }
01053     else
01054     {
01055       hcryp->Size = Size;
01056     }
01057
01058     /* Set Decryption operating mode*/
01059     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
01060
01061     /* algo get algorithm selected */
01062     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01063
01064     switch (algo)
01065     {
01066       case CRYP_DES_ECB:
01067       case CRYP_DES_CBC:
01068       case CRYP_TDES_ECB:
01069       case CRYP_TDES_CBC:
01070
01071         /*Set Key */
01072         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
01073         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
01074         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01075         {
01076           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
01077           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
01078           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
01079           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
01080         }
01081
01082         /*Set Initialization Vector (IV)*/
01083         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01084         {
01085           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01086           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01087         }
01088
01089         /* Flush FIFO */
01090         HAL_CRYP_FIFO_FLUSH(hcryp);
01091
01092         /* Set the phase */
01093         hcryp->Phase = CRYP_PHASE_PROCESS;
01094
01095         /* Start DES/TDES decryption process */
01096         status = CRYP_TDES_Process(hcryp, Timeout);
01097
01098         break;
01099
01100       case CRYP_AES_ECB:
01101       case CRYP_AES_CBC:
01102       case CRYP_AES_CTR:
01103
01104         /* AES decryption */
01105         status = CRYP_AES_Decrypt(hcryp, Timeout);
01106         break;
01107
01108       case CRYP_AES_GCM:
01109
01110         /* AES GCM decryption */
01111         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01112         break;
01113
01114       case CRYP_AES_CCM:
01115
01116         /* AES CCM decryption */
01117         status = CRYP_AESCCM_Process(hcryp, Timeout);
01118         break;
01119
01120       default:
01121         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01122         status = HAL_ERROR;
01123         break;
01124     }
01125
01126     if (status == HAL_OK)
01127     {
01128       /* Change the CRYP peripheral state */
01129       hcryp->State = HAL_CRYP_STATE_READY;
01130
01131       /* Process unlocked */
01132       __HAL_UNLOCK(hcryp);
01133     }
01134   }
01135   else
01136   {
01137     /* Process unlocked */
01138     __HAL_UNLOCK(hcryp);
01139
01140     /* Busy error code field */
01141     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01142     status = HAL_ERROR;
01143   }
01144
01145   /* Return function status */
01146   return status;
01147 }
01148
01149 /**
01150   * @brief  Encryption in interrupt mode.
01151   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01152   *         the configuration information for CRYP module
01153   * @param  Input: Pointer to the input buffer (plaintext)
01154   * @param  Size: Length of the plaintext buffer in word
01155   * @param  Output: Pointer to the output buffer(ciphertext)
01156   * @retval HAL status
01157   */
01158 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01159 {
01160   uint32_t algo;
01161   HAL_StatusTypeDef status;
01162
01163   if (hcryp->State == HAL_CRYP_STATE_READY)
01164   {
01165     /* Change state Busy */
01166     hcryp->State = HAL_CRYP_STATE_BUSY;
01167
01168     /* Process locked */
01169     __HAL_LOCK(hcryp);
01170
01171     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01172     hcryp->CrypInCount = 0U;
01173     hcryp->CrypOutCount = 0U;
01174     hcryp->pCrypInBuffPtr = Input;
01175     hcryp->pCrypOutBuffPtr = Output;
01176
01177     /*  Calculate Size parameter in Byte*/
01178     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01179     {
01180       hcryp->Size = Size * 4U;
01181     }
01182     else
01183     {
01184       hcryp->Size = Size;
01185     }
01186
01187     /* Set encryption operating mode*/
01188     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
01189
01190     /* algo get algorithm selected */
01191     algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
01192
01193     switch (algo)
01194     {
01195       case CRYP_DES_ECB:
01196       case CRYP_DES_CBC:
01197       case CRYP_TDES_ECB:
01198       case CRYP_TDES_CBC:
01199
01200         /*Set Key */
01201         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
01202         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
01203         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01204         {
01205           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
01206           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
01207           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
01208           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
01209         }
01210         /* Set the Initialization Vector*/
01211         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01212         {
01213           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01214           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01215         }
01216
01217         /* Flush FIFO */
01218         HAL_CRYP_FIFO_FLUSH(hcryp);
01219
01220         /* Set the phase */
01221         hcryp->Phase = CRYP_PHASE_PROCESS;
01222
01223         /* Enable interrupts */
01224         __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01225
01226         /* Enable CRYP to start DES/TDES process*/
01227         __HAL_CRYP_ENABLE(hcryp);
01228
01229         status = HAL_OK;
01230         break;
01231
01232       case CRYP_AES_ECB:
01233       case CRYP_AES_CBC:
01234       case CRYP_AES_CTR:
01235
01236         status = CRYP_AES_Encrypt_IT(hcryp);
01237         break;
01238
01239       case CRYP_AES_GCM:
01240
01241         status = CRYP_AESGCM_Process_IT(hcryp) ;
01242         break;
01243
01244       case CRYP_AES_CCM:
01245
01246         status = CRYP_AESCCM_Process_IT(hcryp);
01247         break;
01248
01249       default:
01250         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01251         status =  HAL_ERROR;
01252         break;
01253     }
01254   }
01255   else
01256   {
01257     /* Busy error code field */
01258     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01259     status =  HAL_ERROR;
01260   }
01261
01262   /* Return function status */
01263   return status ;
01264 }
01265
01266 /**
01267   * @brief  Decryption in itnterrupt mode.
01268   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01269   *         the configuration information for CRYP module
01270   * @param  Input: Pointer to the input buffer (ciphertext )
01271   * @param  Size: Length of the plaintext buffer in word.
01272   * @param  Output: Pointer to the output buffer(plaintext)
01273   * @retval HAL status
01274   */
01275 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01276 {
01277   uint32_t algo;
01278   HAL_StatusTypeDef status = HAL_OK;
01279
01280   if (hcryp->State == HAL_CRYP_STATE_READY)
01281   {
01282     /* Change state Busy */
01283     hcryp->State = HAL_CRYP_STATE_BUSY;
01284
01285     /* Process locked */
01286     __HAL_LOCK(hcryp);
01287
01288     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01289     hcryp->CrypInCount = 0U;
01290     hcryp->CrypOutCount = 0U;
01291     hcryp->pCrypInBuffPtr = Input;
01292     hcryp->pCrypOutBuffPtr = Output;
01293
01294     /*  Calculate Size parameter in Byte*/
01295     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01296     {
01297       hcryp->Size = Size * 4U;
01298     }
01299     else
01300     {
01301       hcryp->Size = Size;
01302     }
01303
01304     /* Set decryption operating mode*/
01305     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
01306
01307     /* algo get algorithm selected */
01308     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01309
01310     switch (algo)
01311     {
01312       case CRYP_DES_ECB:
01313       case CRYP_DES_CBC:
01314       case CRYP_TDES_ECB:
01315       case CRYP_TDES_CBC:
01316
01317         /*Set Key */
01318         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
01319         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
01320         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01321         {
01322           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
01323           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
01324           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
01325           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
01326         }
01327
01328         /* Set the Initialization Vector*/
01329         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01330         {
01331           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01332           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01333         }
01334         /* Flush FIFO */
01335         HAL_CRYP_FIFO_FLUSH(hcryp);
01336
01337         /* Set the phase */
01338         hcryp->Phase = CRYP_PHASE_PROCESS;
01339
01340         /* Enable interrupts */
01341         __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01342
01343         /* Enable CRYP and start DES/TDES process*/
01344         __HAL_CRYP_ENABLE(hcryp);
01345
01346         break;
01347
01348       case CRYP_AES_ECB:
01349       case CRYP_AES_CBC:
01350       case CRYP_AES_CTR:
01351
01352         /* AES decryption */
01353         status = CRYP_AES_Decrypt_IT(hcryp);
01354         break;
01355
01356       case CRYP_AES_GCM:
01357
01358         /* AES GCM decryption */
01359         status = CRYP_AESGCM_Process_IT(hcryp) ;
01360         break;
01361
01362       case CRYP_AES_CCM:
01363
01364         /* AES CCMdecryption */
01365         status = CRYP_AESCCM_Process_IT(hcryp);
01366         break;
01367
01368       default:
01369         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01370         status = HAL_ERROR;
01371         break;
01372     }
01373   }
01374   else
01375   {
01376     /* Busy error code field */
01377     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01378     status = HAL_ERROR;
01379   }
01380
01381   /* Return function status */
01382   return status;
01383 }
01384
01385 /**
01386   * @brief  Encryption in DMA mode.
01387   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01388   *         the configuration information for CRYP module
01389   * @param  Input: Pointer to the input buffer (plaintext)
01390   * @param  Size: Length of the plaintext buffer in word.
01391   * @param  Output: Pointer to the output buffer(ciphertext)
01392   * @retval HAL status
01393   */
01394 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01395 {
01396   uint32_t algo;
01397   HAL_StatusTypeDef status = HAL_OK;
01398
01399   if (hcryp->State == HAL_CRYP_STATE_READY)
01400   {
01401     /* Change state Busy */
01402     hcryp->State = HAL_CRYP_STATE_BUSY;
01403
01404     /* Process locked */
01405     __HAL_LOCK(hcryp);
01406
01407     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01408     hcryp->CrypInCount = 0U;
01409     hcryp->CrypOutCount = 0U;
01410     hcryp->pCrypInBuffPtr = Input;
01411     hcryp->pCrypOutBuffPtr = Output;
01412
01413     /*  Calculate Size parameter in Byte*/
01414     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01415     {
01416       hcryp->Size = Size * 4U;
01417     }
01418     else
01419     {
01420       hcryp->Size = Size;
01421     }
01422
01423     /* Set encryption operating mode*/
01424     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
01425
01426     /* algo get algorithm selected */
01427     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01428
01429     switch (algo)
01430     {
01431       case CRYP_DES_ECB:
01432       case CRYP_DES_CBC:
01433       case CRYP_TDES_ECB:
01434       case CRYP_TDES_CBC:
01435
01436         /*Set Key */
01437         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
01438         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
01439         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01440         {
01441           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
01442           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
01443           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
01444           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
01445         }
01446
01447         /* Set the Initialization Vector*/
01448         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01449         {
01450           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01451           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01452         }
01453
01454         /* Flush FIFO */
01455         HAL_CRYP_FIFO_FLUSH(hcryp);
01456
01457         /* Set the phase */
01458         hcryp->Phase = CRYP_PHASE_PROCESS;
01459
01460         /* Start DMA process transfer for DES/TDES */
01461         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
01462
01463         break;
01464
01465       case CRYP_AES_ECB:
01466       case CRYP_AES_CBC:
01467       case CRYP_AES_CTR:
01468
01469         /*  Set the Key*/
01470         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
01471
01472         /* Set the Initialization Vector IV */
01473         if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01474         {
01475           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01476           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01477           hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
01478           hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
01479         }
01480
01481         /* Set the phase */
01482         hcryp->Phase = CRYP_PHASE_PROCESS;
01483
01484         /* Start DMA process transfer for AES */
01485         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
01486         break;
01487
01488       case CRYP_AES_GCM:
01489
01490         /* AES GCM encryption */
01491         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01492         break;
01493
01494       case CRYP_AES_CCM:
01495
01496         /* AES CCM encryption */
01497         status = CRYP_AESCCM_Process_DMA(hcryp);
01498         break;
01499
01500       default:
01501         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01502         status =  HAL_ERROR;
01503         break;
01504     }
01505   }
01506   else
01507   {
01508     /* Busy error code field */
01509     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01510     status =  HAL_ERROR;
01511   }
01512
01513   /* Return function status */
01514   return status;
01515 }
01516
01517 /**
01518   * @brief  Decryption in DMA mode.
01519   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01520   *         the configuration information for CRYP module
01521   * @param  Input: Pointer to the input buffer (ciphertext )
01522   * @param  Size: Length of the plaintext buffer in word
01523   * @param  Output: Pointer to the output buffer(plaintext)
01524   * @retval HAL status
01525   */
01526 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01527 {
01528   uint32_t algo;
01529   HAL_StatusTypeDef status = HAL_OK;
01530
01531   if (hcryp->State == HAL_CRYP_STATE_READY)
01532   {
01533     /* Change state Busy */
01534     hcryp->State = HAL_CRYP_STATE_BUSY;
01535
01536     /* Process locked */
01537     __HAL_LOCK(hcryp);
01538
01539     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01540     hcryp->CrypInCount = 0U;
01541     hcryp->CrypOutCount = 0U;
01542     hcryp->pCrypInBuffPtr = Input;
01543     hcryp->pCrypOutBuffPtr = Output;
01544
01545     /*  Calculate Size parameter in Byte*/
01546     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01547     {
01548       hcryp->Size = Size * 4U;
01549     }
01550     else
01551     {
01552       hcryp->Size = Size;
01553     }
01554
01555     /* Set decryption operating mode*/
01556     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
01557
01558     /* algo get algorithm selected */
01559     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01560
01561     switch (algo)
01562     {
01563       case CRYP_DES_ECB:
01564       case CRYP_DES_CBC:
01565       case CRYP_TDES_ECB:
01566       case CRYP_TDES_CBC:
01567
01568         /*Set Key */
01569         hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
01570         hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
01571         if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01572         {
01573           hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
01574           hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
01575           hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
01576           hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
01577         }
01578
01579         /* Set the Initialization Vector*/
01580         if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01581         {
01582           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01583           hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01584         }
01585
01586         /* Flush FIFO */
01587         HAL_CRYP_FIFO_FLUSH(hcryp);
01588
01589         /* Set the phase */
01590         hcryp->Phase = CRYP_PHASE_PROCESS;
01591
01592         /* Start DMA process transfer for DES/TDES */
01593         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
01594         break;
01595
01596       case CRYP_AES_ECB:
01597       case CRYP_AES_CBC:
01598       case CRYP_AES_CTR:
01599
01600         /* AES decryption */
01601         status = CRYP_AES_Decrypt_DMA(hcryp);
01602         break;
01603
01604       case CRYP_AES_GCM:
01605
01606         /* AES GCM decryption */
01607         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01608
01609         break;
01610
01611       case CRYP_AES_CCM:
01612
01613         /* AES CCM decryption */
01614         status = CRYP_AESCCM_Process_DMA(hcryp);
01615         break;
01616
01617       default:
01618         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01619         status =  HAL_ERROR;
01620         break;
01621     }
01622   }
01623   else
01624   {
01625     /* Busy error code field */
01626     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01627     status = HAL_ERROR;
01628   }
01629
01630   /* Return function status */
01631   return status;
01632 }
01633
01634 /**
01635   * @}
01636   */
01637
01638 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
01639   *  @brief    CRYP IRQ handler.
01640   *
01641 @verbatim
01642   ==============================================================================
01643                 ##### CRYP IRQ handler management #####
01644   ==============================================================================
01645 [..]  This section provides CRYP IRQ handler and callback functions.
01646       (+) HAL_CRYP_IRQHandler CRYP interrupt request
01647       (+) HAL_CRYP_InCpltCallback input data transfer complete callback
01648       (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
01649       (+) HAL_CRYP_ErrorCallback  CRYP error callback
01650       (+) HAL_CRYP_GetState return the CRYP state
01651       (+) HAL_CRYP_GetError return the CRYP error code
01652 @endverbatim
01653   * @{
01654   */
01655
01656 /**
01657   * @brief  This function handles cryptographic interrupt request.
01658   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01659   *         the configuration information for CRYP module
01660   * @retval None
01661   */
01662 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01663 {
01664   uint32_t itstatus = hcryp->Instance->MISR;
01665
01666   if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
01667   {
01668     if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01669     {
01670       CRYP_TDES_IT(hcryp); /* DES or TDES*/
01671     }
01672     else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
01673     {
01674       CRYP_AES_IT(hcryp); /*AES*/
01675     }
01676
01677     else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
01678     {
01679       /* if header phase */
01680       if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
01681       {
01682         CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01683       }
01684       else  /* if payload phase */
01685       {
01686         CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01687       }
01688     }
01689     else
01690     {
01691       /* Nothing to do */
01692     }
01693   }
01694 }
01695
01696 /**
01697   * @brief  Return the CRYP error code.
01698   * @param  hcryp : pointer to a CRYP_HandleTypeDef structure that contains
01699   *                 the configuration information for the  CRYP IP
01700   * @retval CRYP error code
01701   */
01702 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01703 {
01704   return hcryp->ErrorCode;
01705 }
01706
01707 /**
01708   * @brief  Returns the CRYP state.
01709   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01710   *         the configuration information for CRYP module.
01711   * @retval HAL state
01712   */
01713 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01714 {
01715   return hcryp->State;
01716 }
01717
01718 /**
01719   * @brief  Input FIFO transfer completed callback.
01720   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01721   *         the configuration information for CRYP module.
01722   * @retval None
01723   */
01724 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01725 {
01726   /* Prevent unused argument(s) compilation warning */
01727   UNUSED(hcryp);
01728
01729   /* NOTE : This function Should not be modified, when the callback is needed,
01730             the HAL_CRYP_InCpltCallback could be implemented in the user file
01731    */
01732 }
01733
01734 /**
01735   * @brief  Output FIFO transfer completed callback.
01736   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01737   *         the configuration information for CRYP module.
01738   * @retval None
01739   */
01740 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01741 {
01742   /* Prevent unused argument(s) compilation warning */
01743   UNUSED(hcryp);
01744
01745   /* NOTE : This function Should not be modified, when the callback is needed,
01746             the HAL_CRYP_OutCpltCallback could be implemented in the user file
01747    */
01748 }
01749
01750 /**
01751   * @brief  CRYP error callback.
01752   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01753   *         the configuration information for CRYP module.
01754   * @retval None
01755   */
01756 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01757 {
01758   /* Prevent unused argument(s) compilation warning */
01759   UNUSED(hcryp);
01760
01761   /* NOTE : This function Should not be modified, when the callback is needed,
01762             the HAL_CRYP_ErrorCallback could be implemented in the user file
01763    */
01764 }
01765 /**
01766   * @}
01767   */
01768
01769 /* Private functions ---------------------------------------------------------*/
01770 /** @addtogroup CRYP_Private_Functions
01771   * @{
01772   */
01773
01774 /**
01775   * @brief  Encryption in ECB/CBC Algorithm with DES/TDES standard.
01776   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01777   *         the configuration information for CRYP module
01778   * @param  Timeout: Timeout value
01779   * @retval HAL status
01780   */
01781 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01782 {
01783
01784   uint32_t temp;  /* Temporary CrypOutBuff */
01785   uint16_t incount; /* Temporary CrypInCount Value */
01786   uint16_t outcount;  /* Temporary CrypOutCount Value */
01787
01788   /* Enable CRYP */
01789   __HAL_CRYP_ENABLE(hcryp);
01790   /*Temporary CrypOutCount Value*/
01791   outcount = hcryp->CrypOutCount;
01792
01793   /*Start processing*/
01794   while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
01795   {
01796     /* Temporary CrypInCount Value */
01797     incount = hcryp->CrypInCount;
01798     /* Write plain data and get cipher data */
01799     if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
01800     {
01801       /* Write the input block in the IN FIFO */
01802       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
01803       hcryp->CrypInCount++;
01804       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
01805       hcryp->CrypInCount++;
01806     }
01807
01808     /* Wait for OFNE flag to be raised */
01809     if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
01810     {
01811       /* Disable the CRYP peripheral clock */
01812       __HAL_CRYP_DISABLE(hcryp);
01813
01814       /* Change state & errorCode*/
01815       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
01816       hcryp->State = HAL_CRYP_STATE_READY;
01817
01818       /* Process unlocked */
01819       __HAL_UNLOCK(hcryp);
01820 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
01821       /*Call registered error callback*/
01822       hcryp->ErrorCallback(hcryp);
01823 #else
01824       /*Call legacy weak error callback*/
01825       HAL_CRYP_ErrorCallback(hcryp);
01826 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
01827     }
01828
01829     /*Temporary CrypOutCount Value*/
01830     outcount = hcryp->CrypOutCount;
01831
01832     if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
01833     {
01834       /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
01835       temp = hcryp->Instance->DOUT;
01836       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01837       hcryp->CrypOutCount++;
01838       temp = hcryp->Instance->DOUT;
01839       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01840       hcryp->CrypOutCount++;
01841     }
01842     /*Temporary CrypOutCount Value*/
01843     outcount = hcryp->CrypOutCount;
01844   }
01845   /* Disable CRYP */
01846   __HAL_CRYP_DISABLE(hcryp);
01847   /* Change the CRYP state */
01848   hcryp->State = HAL_CRYP_STATE_READY;
01849
01850   /* Return function status */
01851   return HAL_OK;
01852 }
01853
01854 /**
01855   * @brief  CRYP block input/output data handling under interruption with DES/TDES standard.
01856   * @note   The function is called under interruption only, once
01857   *         interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
01858   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01859   *         the configuration information for CRYP module.
01860   * @retval HAL status
01861   */
01862 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
01863 {
01864   uint32_t temp;  /* Temporary CrypOutBuff */
01865
01866   if (hcryp->State == HAL_CRYP_STATE_BUSY)
01867   {
01868     if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
01869     {
01870       if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
01871       {
01872         /* Write input block in the IN FIFO */
01873         hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
01874         hcryp->CrypInCount++;
01875         hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
01876         hcryp->CrypInCount++;
01877
01878         if (hcryp->CrypInCount == (hcryp->Size / 4U))
01879         {
01880           /* Disable interruption */
01881           __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01882
01883           /* Call the input data transfer complete callback */
01884 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
01885           /*Call registered Input complete callback*/
01886           hcryp->InCpltCallback(hcryp);
01887 #else
01888           /*Call legacy weak Input complete callback*/
01889           HAL_CRYP_InCpltCallback(hcryp);
01890 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
01891         }
01892       }
01893     }
01894
01895     if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
01896     {
01897       if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
01898       {
01899         /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
01900         temp = hcryp->Instance->DOUT;
01901         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01902         hcryp->CrypOutCount++;
01903         temp = hcryp->Instance->DOUT;
01904         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01905         hcryp->CrypOutCount++;
01906         if (hcryp->CrypOutCount == (hcryp->Size / 4U))
01907         {
01908           /* Disable interruption */
01909           __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01910
01911           /* Disable CRYP */
01912           __HAL_CRYP_DISABLE(hcryp);
01913
01914           /* Process unlocked */
01915           __HAL_UNLOCK(hcryp);
01916
01917           /* Change the CRYP state */
01918           hcryp->State = HAL_CRYP_STATE_READY;
01919
01920           /* Call output transfer complete callback */
01921 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
01922           /*Call registered Output complete callback*/
01923           hcryp->OutCpltCallback(hcryp);
01924 #else
01925           /*Call legacy weak Output complete callback*/
01926           HAL_CRYP_OutCpltCallback(hcryp);
01927 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
01928
01929         }
01930       }
01931     }
01932   }
01933   else
01934   {
01935     /* Process unlocked */
01936     __HAL_UNLOCK(hcryp);
01937     /* Busy error code field */
01938     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01939 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
01940     /*Call registered error callback*/
01941     hcryp->ErrorCallback(hcryp);
01942 #else
01943     /*Call legacy weak error callback*/
01944     HAL_CRYP_ErrorCallback(hcryp);
01945 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
01946   }
01947 }
01948
01949 /**
01950   * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
01951   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
01952   * @param  Timeout: specify Timeout value
01953   * @retval HAL status
01954   */
01955 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01956 {
01957   uint16_t outcount;  /* Temporary CrypOutCount Value */
01958
01959   /*  Set the Key*/
01960   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
01961
01962   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01963   {
01964     /* Set the Initialization Vector*/
01965     hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
01966     hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
01967     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
01968     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
01969   }
01970
01971   /* Set the phase */
01972   hcryp->Phase = CRYP_PHASE_PROCESS;
01973
01974   /* Enable CRYP */
01975   __HAL_CRYP_ENABLE(hcryp);
01976   /*Temporary CrypOutCount Value*/
01977   outcount = hcryp->CrypOutCount;
01978
01979   while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
01980   {
01981     /* Write plain Ddta and get cipher data */
01982     CRYP_AES_ProcessData(hcryp, Timeout);
01983     /*Temporary CrypOutCount Value*/
01984     outcount = hcryp->CrypOutCount;
01985   }
01986
01987   /* Disable CRYP */
01988   __HAL_CRYP_DISABLE(hcryp);
01989
01990   /* Change the CRYP state */
01991   hcryp->State = HAL_CRYP_STATE_READY;
01992
01993   /* Return function status */
01994   return HAL_OK;
01995 }
01996
01997 /**
01998   * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
01999   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02000   *         the configuration information for CRYP module
02001   * @retval HAL status
02002   */
02003 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
02004 {
02005
02006   /*  Set the Key*/
02007   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02008
02009   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02010   {
02011     /* Set the Initialization Vector*/
02012     hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02013     hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02014     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02015     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02016   }
02017   /* Set the phase */
02018   hcryp->Phase = CRYP_PHASE_PROCESS;
02019
02020   if (hcryp->Size != 0U)
02021   {
02022     /* Enable interrupts */
02023     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02024
02025     /* Enable CRYP */
02026     __HAL_CRYP_ENABLE(hcryp);
02027   }
02028   else
02029   {
02030     /* Change the CRYP state */
02031     hcryp->State = HAL_CRYP_STATE_READY;
02032
02033     /* Process unlocked */
02034     __HAL_UNLOCK(hcryp);
02035   }
02036
02037   /* Return function status */
02038   return HAL_OK;
02039 }
02040
02041 /**
02042   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
02043   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
02044   * @param  Timeout: Specify Timeout value
02045   * @retval HAL status
02046   */
02047 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02048 {
02049   uint16_t outcount;  /* Temporary CrypOutCount Value */
02050
02051   /*  Key preparation for ECB/CBC */
02052   if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
02053   {
02054     /* change ALGOMODE to key preparation for decryption*/
02055     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
02056
02057     /*  Set the Key*/
02058     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02059
02060     /* Enable CRYP */
02061     __HAL_CRYP_ENABLE(hcryp);
02062
02063     /* Wait for BUSY flag to be raised */
02064     if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
02065     {
02066       /* Disable the CRYP peripheral clock */
02067       __HAL_CRYP_DISABLE(hcryp);
02068
02069       /* Change state */
02070       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02071       hcryp->State = HAL_CRYP_STATE_READY;
02072
02073       /* Process unlocked */
02074       __HAL_UNLOCK(hcryp);
02075       return HAL_ERROR;
02076     }
02077     /* Turn back to ALGOMODE of the configuration */
02078     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
02079   }
02080   else  /*Algorithm CTR */
02081   {
02082     /*  Set the Key*/
02083     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02084   }
02085
02086   /* Set IV */
02087   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02088   {
02089     /* Set the Initialization Vector*/
02090     hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02091     hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02092     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02093     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02094   }
02095   /* Set the phase */
02096   hcryp->Phase = CRYP_PHASE_PROCESS;
02097
02098   /* Enable CRYP */
02099   __HAL_CRYP_ENABLE(hcryp);
02100
02101   /*Temporary CrypOutCount Value*/
02102   outcount = hcryp->CrypOutCount;
02103
02104   while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02105   {
02106     /* Write plain data and get cipher data */
02107     CRYP_AES_ProcessData(hcryp, Timeout);
02108     /*Temporary CrypOutCount Value*/
02109     outcount = hcryp->CrypOutCount;
02110   }
02111
02112   /* Disable CRYP */
02113   __HAL_CRYP_DISABLE(hcryp);
02114
02115   /* Change the CRYP state */
02116   hcryp->State = HAL_CRYP_STATE_READY;
02117
02118   /* Return function status */
02119   return HAL_OK;
02120 }
02121 /**
02122   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02123   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02124   *         the configuration information for CRYP module
02125   * @retval HAL status
02126   */
02127 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
02128 {
02129   __IO uint32_t count = 0U;
02130
02131   /*  Key preparation for ECB/CBC */
02132   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02133   {
02134     /* change ALGOMODE to key preparation for decryption*/
02135     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
02136
02137     /*  Set the Key*/
02138     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02139
02140     /* Enable CRYP */
02141     __HAL_CRYP_ENABLE(hcryp);
02142
02143     /* Wait for BUSY flag to be raised */
02144     count = CRYP_TIMEOUT_KEYPREPARATION;
02145     do
02146     {
02147       count-- ;
02148       if (count == 0U)
02149       {
02150         /* Change state */
02151         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02152         hcryp->State = HAL_CRYP_STATE_READY;
02153
02154         /* Process unlocked */
02155         __HAL_UNLOCK(hcryp);
02156         return HAL_ERROR;
02157       }
02158     } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
02159
02160     /* Turn back to ALGOMODE of the configuration */
02161     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
02162   }
02163   else  /*Algorithm CTR */
02164   {
02165     /*  Set the Key*/
02166     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02167   }
02168
02169   /* Set IV */
02170   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02171   {
02172     /* Set the Initialization Vector*/
02173     hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02174     hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02175     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02176     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02177   }
02178   /* Set the phase */
02179   hcryp->Phase = CRYP_PHASE_PROCESS;
02180   if (hcryp->Size != 0U)
02181   {
02182     /* Enable interrupts */
02183     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02184
02185     /* Enable CRYP */
02186     __HAL_CRYP_ENABLE(hcryp);
02187   }
02188   else
02189   {
02190     /* Process locked */
02191     __HAL_UNLOCK(hcryp);
02192
02193     /* Change the CRYP state */
02194     hcryp->State = HAL_CRYP_STATE_READY;
02195   }
02196   /* Return function status */
02197   return HAL_OK;
02198 }
02199 /**
02200   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
02201   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02202   *         the configuration information for CRYP module
02203   * @retval HAL status
02204   */
02205 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
02206 {
02207   __IO uint32_t count = 0U;
02208
02209   /*  Key preparation for ECB/CBC */
02210   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02211   {
02212     /* change ALGOMODE to key preparation for decryption*/
02213     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
02214
02215     /*  Set the Key*/
02216     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02217
02218     /* Enable CRYP */
02219     __HAL_CRYP_ENABLE(hcryp);
02220
02221     /* Wait for BUSY flag to be raised */
02222     count = CRYP_TIMEOUT_KEYPREPARATION;
02223     do
02224     {
02225       count-- ;
02226       if (count == 0U)
02227       {
02228         /* Disable the CRYP peripheral clock */
02229         __HAL_CRYP_DISABLE(hcryp);
02230
02231         /* Change state */
02232         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02233         hcryp->State = HAL_CRYP_STATE_READY;
02234
02235         /* Process unlocked */
02236         __HAL_UNLOCK(hcryp);
02237         return HAL_ERROR;
02238       }
02239     } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
02240
02241     /* Turn back to ALGOMODE of the configuration */
02242     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
02243   }
02244   else  /*Algorithm CTR */
02245   {
02246     /*  Set the Key*/
02247     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02248   }
02249
02250   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02251   {
02252     /* Set the Initialization Vector*/
02253     hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02254     hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02255     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02256     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02257   }
02258   /* Set the phase */
02259   hcryp->Phase = CRYP_PHASE_PROCESS;
02260
02261   if (hcryp->Size != 0U)
02262   {
02263     /* Set the input and output addresses and start DMA transfer */
02264     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
02265   }
02266   else
02267   {
02268     /* Process unlocked */
02269     __HAL_UNLOCK(hcryp);
02270
02271     /* Change the CRYP state */
02272     hcryp->State = HAL_CRYP_STATE_READY;
02273   }
02274
02275   /* Return function status */
02276   return HAL_OK;
02277 }
02278
02279
02280 /**
02281   * @brief  DMA CRYP input data process complete callback.
02282   * @param  hdma: DMA handle
02283   * @retval None
02284   */
02285 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
02286 {
02287   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02288
02289   /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
02290   in the DMACR register */
02291   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
02292
02293   /* Call input data transfer complete callback */
02294 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02295   /*Call registered Input complete callback*/
02296   hcryp->InCpltCallback(hcryp);
02297 #else
02298   /*Call legacy weak Input complete callback*/
02299   HAL_CRYP_InCpltCallback(hcryp);
02300 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02301 }
02302
02303 /**
02304   * @brief  DMA CRYP output data process complete callback.
02305   * @param  hdma: DMA handle
02306   * @retval None
02307   */
02308 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
02309 {
02310   uint32_t count;
02311   uint32_t npblb;
02312   uint32_t lastwordsize;
02313   uint32_t temp;  /* Temporary CrypOutBuff */
02314   uint32_t temp_cr_algodir;
02315   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02316
02317
02318   /* Disable the DMA transfer for output FIFO */
02319   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
02320
02321   /* Last block transfer in case of GCM or CCM with Size not %16*/
02322   if (((hcryp->Size) % 16U) != 0U)
02323   {
02324     /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
02325     hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
02326     hcryp->CrypOutCount = hcryp->CrypInCount;
02327
02328     /* Compute the number of padding bytes in last block of payload */
02329     npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
02330
02331 #if !defined (CRYP_VER_2_2)
02332     if (hcryp->Version >= REV_ID_B)
02333 #endif /*End of not defined CRYP_VER_2_2*/
02334     {
02335           /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
02336       temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
02337       if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
02338           ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
02339       {
02340         /* Disable the CRYP */
02341         __HAL_CRYP_DISABLE(hcryp);
02342
02343         /* Specify the number of non-valid bytes using NPBLB register*/
02344         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
02345
02346         /* Enable CRYP to start the final phase */
02347         __HAL_CRYP_ENABLE(hcryp);
02348       }
02349     }
02350
02351     /* Number of valid words (lastwordsize) in last block */
02352     if ((npblb % 4U) == 0U)
02353     {
02354       lastwordsize = (16U - npblb) / 4U;
02355     }
02356     else
02357     {
02358       lastwordsize = ((16U - npblb) / 4U) + 1U;
02359     }
02360     /* Write the last input block in the IN FIFO */
02361     for (count = 0U; count < lastwordsize; count ++)
02362     {
02363       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02364       hcryp->CrypInCount++;
02365     }
02366     /* Pad the data with zeros to have a complete block */
02367     while (count < 4U)
02368     {
02369       hcryp->Instance->DIN  = 0U;
02370       count++;
02371     }
02372     /* Wait for OFNE flag to be raised */
02373     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
02374     do
02375     {
02376       count-- ;
02377       if (count == 0U)
02378       {
02379         /* Disable the CRYP peripheral clock */
02380         __HAL_CRYP_DISABLE(hcryp);
02381
02382         /* Change state */
02383         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02384         hcryp->State = HAL_CRYP_STATE_READY;
02385
02386         /* Process unlocked */
02387         __HAL_UNLOCK(hcryp);
02388 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02389         /*Call registered error callback*/
02390         hcryp->ErrorCallback(hcryp);
02391 #else
02392         /*Call legacy weak error callback*/
02393         HAL_CRYP_ErrorCallback(hcryp);
02394 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02395       }
02396     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
02397
02398     /*Read the output block from the output FIFO */
02399     for (count = 0U; count < 4U; count++)
02400     {
02401       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
02402       temp = hcryp->Instance->DOUT;
02403
02404       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02405       hcryp->CrypOutCount++;
02406     }
02407   } /*End of last block transfer in case of GCM or CCM */
02408
02409   if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
02410   {
02411     /* Disable CRYP  (not allowed in  GCM)*/
02412     __HAL_CRYP_DISABLE(hcryp);
02413   }
02414
02415   /* Change the CRYP state to ready */
02416   hcryp->State = HAL_CRYP_STATE_READY;
02417
02418   /* Process unlocked */
02419   __HAL_UNLOCK(hcryp);
02420
02421   /* Call output data transfer complete callback */
02422 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02423   /*Call registered Output complete callback*/
02424   hcryp->OutCpltCallback(hcryp);
02425 #else
02426   /*Call legacy weak Output complete callback*/
02427   HAL_CRYP_OutCpltCallback(hcryp);
02428 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02429 }
02430
02431 /**
02432   * @brief  DMA CRYP communication error callback.
02433   * @param  hdma: DMA handle
02434   * @retval None
02435   */
02436 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
02437 {
02438   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02439
02440   /* Change the CRYP peripheral state */
02441   hcryp->State = HAL_CRYP_STATE_READY;
02442
02443   /* DMA error code field */
02444   hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02445
02446   /* Call error callback */
02447 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02448   /*Call registered error callback*/
02449   hcryp->ErrorCallback(hcryp);
02450 #else
02451   /*Call legacy weak error callback*/
02452   HAL_CRYP_ErrorCallback(hcryp);
02453 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02454 }
02455
02456 /**
02457   * @brief  Set the DMA configuration and start the DMA transfer
02458   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02459   *         the configuration information for CRYP module
02460   * @param  inputaddr: address of the input buffer
02461   * @param  Size: size of the input buffer, must be a multiple of 16.
02462   * @param  outputaddr: address of the output buffer
02463   * @retval None
02464   */
02465 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02466 {
02467   /* Set the CRYP DMA transfer complete callback */
02468   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02469
02470   /* Set the DMA input error callback */
02471   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02472
02473   /* Set the CRYP DMA transfer complete callback */
02474   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
02475
02476   /* Set the DMA output error callback */
02477   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
02478
02479   /* Enable CRYP */
02480   __HAL_CRYP_ENABLE(hcryp);
02481
02482   /* Enable the input DMA Stream */
02483   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
02484   {
02485     /* DMA error code field */
02486     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02487
02488     /* Call error callback */
02489 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02490     /*Call registered error callback*/
02491     hcryp->ErrorCallback(hcryp);
02492 #else
02493     /*Call legacy weak error callback*/
02494     HAL_CRYP_ErrorCallback(hcryp);
02495 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02496   }
02497
02498   /* Enable the output DMA Stream */
02499   if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
02500   {
02501     /* DMA error code field */
02502     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02503
02504     /* Call error callback */
02505 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02506     /*Call registered error callback*/
02507     hcryp->ErrorCallback(hcryp);
02508 #else
02509     /*Call legacy weak error callback*/
02510     HAL_CRYP_ErrorCallback(hcryp);
02511 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02512   }
02513   /* Enable In/Out DMA request */
02514   hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
02515 }
02516
02517 /**
02518   * @brief  Process Data: Write Input data in polling mode and used in AES functions.
02519   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02520   *         the configuration information for CRYP module
02521   * @param  Timeout: Specify Timeout value
02522   * @retval None
02523   */
02524 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02525 {
02526
02527   uint32_t temp;  /* Temporary CrypOutBuff */
02528   uint16_t incount;  /* Temporary CrypInCount Value */
02529   uint16_t outcount;  /* Temporary CrypOutCount Value */
02530
02531   /*Temporary CrypOutCount Value*/
02532   incount = hcryp->CrypInCount;
02533
02534   if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U)))
02535   {
02536     /* Write the input block in the IN FIFO */
02537     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02538     hcryp->CrypInCount++;
02539     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02540     hcryp->CrypInCount++;
02541     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02542     hcryp->CrypInCount++;
02543     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02544     hcryp->CrypInCount++;
02545   }
02546
02547   /* Wait for OFNE flag to be raised */
02548   if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
02549   {
02550     /* Disable the CRYP peripheral clock */
02551     __HAL_CRYP_DISABLE(hcryp);
02552
02553     /* Change state & error code*/
02554     hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02555     hcryp->State = HAL_CRYP_STATE_READY;
02556
02557     /* Process unlocked */
02558     __HAL_UNLOCK(hcryp);
02559 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02560     /*Call registered error callback*/
02561     hcryp->ErrorCallback(hcryp);
02562 #else
02563     /*Call legacy weak error callback*/
02564     HAL_CRYP_ErrorCallback(hcryp);
02565 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02566   }
02567   /*Temporary CrypOutCount Value*/
02568   outcount = hcryp->CrypOutCount;
02569
02570   if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
02571   {
02572     /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
02573     temp  = hcryp->Instance->DOUT;
02574     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02575     hcryp->CrypOutCount++;
02576     temp  = hcryp->Instance->DOUT;
02577     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02578     hcryp->CrypOutCount++;
02579     temp  = hcryp->Instance->DOUT;
02580     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02581     hcryp->CrypOutCount++;
02582     temp  = hcryp->Instance->DOUT;
02583     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02584     hcryp->CrypOutCount++;
02585   }
02586 }
02587
02588 /**
02589   * @brief  Handle CRYP block input/output data handling under interruption.
02590   * @note   The function is called under interruption only, once
02591   *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
02592   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02593   *         the configuration information for CRYP module.
02594   * @retval HAL status
02595   */
02596 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
02597 {
02598   uint32_t temp;  /* Temporary CrypOutBuff */
02599   uint16_t incount; /* Temporary CrypInCount Value */
02600   uint16_t outcount;  /* Temporary CrypOutCount Value */
02601
02602   if (hcryp->State == HAL_CRYP_STATE_BUSY)
02603   {
02604     /*Temporary CrypOutCount Value*/
02605     incount = hcryp->CrypInCount;
02606
02607     if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
02608     {
02609       /* Write the input block in the IN FIFO */
02610       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02611       hcryp->CrypInCount++;
02612       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02613       hcryp->CrypInCount++;
02614       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02615       hcryp->CrypInCount++;
02616       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02617       hcryp->CrypInCount++;
02618       if (hcryp->CrypInCount == (hcryp->Size / 4U))
02619       {
02620         /* Disable interrupts */
02621         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02622
02623         /* Call the input data transfer complete callback */
02624 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02625         /*Call registered Input complete callback*/
02626         hcryp->InCpltCallback(hcryp);
02627 #else
02628         /*Call legacy weak Input complete callback*/
02629         HAL_CRYP_InCpltCallback(hcryp);
02630 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02631       }
02632     }
02633
02634     /*Temporary CrypOutCount Value*/
02635     outcount = hcryp->CrypOutCount;
02636
02637     if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
02638     {
02639       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
02640       temp  = hcryp->Instance->DOUT;
02641       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02642       hcryp->CrypOutCount++;
02643       temp  = hcryp->Instance->DOUT;
02644       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02645       hcryp->CrypOutCount++;
02646       temp  = hcryp->Instance->DOUT;
02647       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02648       hcryp->CrypOutCount++;
02649       temp  = hcryp->Instance->DOUT;
02650       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02651       hcryp->CrypOutCount++;
02652       if (hcryp->CrypOutCount == (hcryp->Size / 4U))
02653       {
02654         /* Disable interrupts */
02655         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02656
02657         /* Change the CRYP state */
02658         hcryp->State = HAL_CRYP_STATE_READY;
02659
02660         /* Disable CRYP */
02661         __HAL_CRYP_DISABLE(hcryp);
02662
02663         /* Process unlocked */
02664         __HAL_UNLOCK(hcryp);
02665
02666         /* Call output transfer complete callback */
02667 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02668         /*Call registered Output complete callback*/
02669         hcryp->OutCpltCallback(hcryp);
02670 #else
02671         /*Call legacy weak Output complete callback*/
02672         HAL_CRYP_OutCpltCallback(hcryp);
02673 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02674       }
02675     }
02676   }
02677   else
02678   {
02679     /* Process unlocked */
02680     __HAL_UNLOCK(hcryp);
02681     /* Busy error code field */
02682     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
02683 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02684     /*Call registered error callback*/
02685     hcryp->ErrorCallback(hcryp);
02686 #else
02687     /*Call legacy weak error callback*/
02688     HAL_CRYP_ErrorCallback(hcryp);
02689 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02690   }
02691 }
02692
02693 /**
02694   * @brief  Writes Key in Key registers.
02695   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02696   *         the configuration information for CRYP module
02697   * @param  KeySize: Size of Key
02698   * @retval None
02699   */
02700 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
02701 {
02702   switch (KeySize)
02703   {
02704     case CRYP_KEYSIZE_256B:
02705       hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
02706       hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
02707       hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
02708       hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
02709       hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
02710       hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
02711       hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
02712       hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
02713       break;
02714     case CRYP_KEYSIZE_192B:
02715       hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
02716       hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
02717       hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
02718       hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
02719       hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
02720       hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
02721       break;
02722     case CRYP_KEYSIZE_128B:
02723       hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
02724       hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
02725       hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
02726       hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
02727
02728       break;
02729     default:
02730       break;
02731   }
02732 }
02733
02734 /**
02735   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
02736   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02737   *         the configuration information for CRYP module
02738   * @param  Timeout: Timeout duration
02739   * @retval HAL status
02740   */
02741 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02742 {
02743   uint32_t tickstart;
02744   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
02745   uint32_t npblb ;
02746   uint32_t temp ;  /* Temporary CrypOutBuff */
02747   uint32_t index ;
02748   uint32_t lastwordsize ;
02749   uint16_t outcount;  /* Temporary CrypOutCount Value */
02750
02751   /*  Reset CrypHeaderCount */
02752   hcryp->CrypHeaderCount = 0U;
02753
02754   /****************************** Init phase **********************************/
02755
02756   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02757
02758   /* Set the key */
02759   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02760
02761   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
02762   hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02763   hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02764   hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02765   hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02766
02767   /* Enable the CRYP peripheral */
02768   __HAL_CRYP_ENABLE(hcryp);
02769
02770   /* Get tick */
02771   tickstart = HAL_GetTick();
02772
02773   /*Wait for the CRYPEN bit to be cleared*/
02774   while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02775   {
02776     /* Check for the Timeout */
02777     if (Timeout != HAL_MAX_DELAY)
02778     {
02779       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02780       {
02781         /* Disable the CRYP peripheral clock */
02782         __HAL_CRYP_DISABLE(hcryp);
02783
02784         /* Change state */
02785         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02786         hcryp->State = HAL_CRYP_STATE_READY;
02787
02788         /* Process unlocked */
02789         __HAL_UNLOCK(hcryp);
02790         return HAL_ERROR;
02791       }
02792     }
02793   }
02794
02795   /************************ Header phase *************************************/
02796
02797   if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
02798   {
02799     return HAL_ERROR;
02800   }
02801
02802   /*************************Payload phase ************************************/
02803
02804   /* Set the phase */
02805   hcryp->Phase = CRYP_PHASE_PROCESS;
02806
02807   /* Disable the CRYP peripheral */
02808   __HAL_CRYP_DISABLE(hcryp);
02809
02810 #if !defined (CRYP_VER_2_2)
02811   if (hcryp->Version >= REV_ID_B)
02812 #endif /*End of not defined CRYP_VER_2_2*/
02813   {
02814     /* Set to 0 the number of non-valid bytes using NPBLB register*/
02815     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
02816   }
02817
02818   /* Select payload phase once the header phase is performed */
02819   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02820
02821   /* Enable the CRYP peripheral */
02822   __HAL_CRYP_ENABLE(hcryp);
02823
02824   if ((hcryp->Size % 16U) != 0U)
02825   {
02826     /* recalculate  wordsize */
02827     wordsize = ((wordsize / 4U) * 4U) ;
02828   }
02829
02830   /* Get tick */
02831   tickstart = HAL_GetTick();
02832   /*Temporary CrypOutCount Value*/
02833   outcount = hcryp->CrypOutCount;
02834
02835   /* Write input data and get output Data */
02836   while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
02837   {
02838     /* Write plain data and get cipher data */
02839     CRYP_AES_ProcessData(hcryp, Timeout);
02840
02841     /*Temporary CrypOutCount Value*/
02842     outcount = hcryp->CrypOutCount;
02843
02844     /* Check for the Timeout */
02845     if (Timeout != HAL_MAX_DELAY)
02846     {
02847       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02848       {
02849         /* Disable the CRYP peripheral clock */
02850         __HAL_CRYP_DISABLE(hcryp);
02851
02852         /* Change state & error code */
02853         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02854         hcryp->State = HAL_CRYP_STATE_READY;
02855
02856         /* Process unlocked */
02857         __HAL_UNLOCK(hcryp);
02858         return HAL_ERROR;
02859       }
02860     }
02861   }
02862
02863   if ((hcryp->Size % 16U) != 0U)
02864   {
02865
02866 #if !defined (CRYP_VER_2_2)
02867     if (hcryp->Version >= REV_ID_B)
02868 #endif /*End of not defined CRYP_VER_2_2*/
02869     {
02870       /* Compute the number of padding bytes in last block of payload */
02871       npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
02872
02873       /*  Set Npblb in case of AES GCM payload encryption to get right tag*/
02874       if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
02875       {
02876         /* Disable the CRYP */
02877         __HAL_CRYP_DISABLE(hcryp);
02878
02879         /* Specify the number of non-valid bytes using NPBLB register*/
02880         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
02881
02882         /* Enable CRYP to start the final phase */
02883         __HAL_CRYP_ENABLE(hcryp);
02884       }
02885       /* Number of valid words (lastwordsize) in last block */
02886       if ((npblb % 4U) == 0U)
02887       {
02888         lastwordsize = (16U - npblb) / 4U;
02889       }
02890       else
02891       {
02892         lastwordsize = ((16U - npblb) / 4U) + 1U;
02893       }
02894
02895       /* Write the last input block in the IN FIFO */
02896       for (index = 0U; index < lastwordsize; index ++)
02897       {
02898         hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02899         hcryp->CrypInCount++;
02900       }
02901
02902       /* Pad the data with zeros to have a complete block */
02903       while (index < 4U)
02904       {
02905         hcryp->Instance->DIN  = 0U;
02906         index++;
02907       }
02908
02909       /* Wait for OFNE flag to be raised */
02910       if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
02911       {
02912         /* Disable the CRYP peripheral clock */
02913         __HAL_CRYP_DISABLE(hcryp);
02914
02915         /* Change state */
02916         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02917         hcryp->State = HAL_CRYP_STATE_READY;
02918
02919         /* Process Unlocked */
02920         __HAL_UNLOCK(hcryp);
02921 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
02922         /*Call registered error callback*/
02923         hcryp->ErrorCallback(hcryp);
02924 #else
02925         /*Call legacy weak error callback*/
02926         HAL_CRYP_ErrorCallback(hcryp);
02927 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02928       }
02929
02930       /*Read the output block from the output FIFO */
02931       if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
02932       {
02933         for (index = 0U; index < 4U; index++)
02934         {
02935           /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
02936           temp = hcryp->Instance->DOUT;
02937
02938           *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02939           hcryp->CrypOutCount++;
02940         }
02941       }
02942     }
02943 #if !defined (CRYP_VER_2_2)
02944     else /*  Workaround to be used */
02945     {
02946       /*  Workaround 2 for STM32H7 below rev.B To generate correct TAG only when size of the last block of
02947       payload is inferior to 128 bits, in case of GCM encryption or CCM decryption*/
02948       CRYP_Workaround(hcryp, Timeout);
02949     } /* end of NPBLB or Workaround*/
02950 #endif /*End of not defined CRYP_VER_2_2*/
02951   }
02952
02953
02954   /* Return function status */
02955   return HAL_OK;
02956 }
02957
02958 /**
02959   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
02960   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02961   *         the configuration information for CRYP module
02962   * @retval HAL status
02963   */
02964 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
02965 {
02966   __IO uint32_t count = 0U;
02967
02968   /*  Reset CrypHeaderCount */
02969   hcryp->CrypHeaderCount = 0U;
02970
02971   /******************************* Init phase *********************************/
02972
02973   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02974
02975   /* Set the key */
02976   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02977
02978   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
02979   hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
02980   hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
02981   hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
02982   hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
02983
02984   /* Enable the CRYP peripheral */
02985   __HAL_CRYP_ENABLE(hcryp);
02986
02987   /*Wait for the CRYPEN bit to be cleared*/
02988   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
02989   do
02990   {
02991     count-- ;
02992     if (count == 0U)
02993     {
02994       /* Disable the CRYP peripheral clock */
02995       __HAL_CRYP_DISABLE(hcryp);
02996
02997       /* Change state */
02998       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02999       hcryp->State = HAL_CRYP_STATE_READY;
03000
03001       /* Process unlocked */
03002       __HAL_UNLOCK(hcryp);
03003       return HAL_ERROR;
03004     }
03005   } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
03006
03007   /***************************** Header phase *********************************/
03008
03009   /* Select header phase */
03010   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03011
03012   /* Enable interrupts */
03013   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
03014
03015   /* Enable CRYP */
03016   __HAL_CRYP_ENABLE(hcryp);
03017
03018   /* Return function status */
03019   return HAL_OK;
03020 }
03021
03022
03023 /**
03024   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
03025   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03026   *         the configuration information for CRYP module
03027   * @retval HAL status
03028   */
03029 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
03030 {
03031   __IO uint32_t count = 0U;
03032   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
03033   uint32_t index;
03034   uint32_t npblb;
03035   uint32_t lastwordsize;
03036   uint32_t temp;  /* Temporary CrypOutBuff */
03037   /*  Reset CrypHeaderCount */
03038   hcryp->CrypHeaderCount = 0U;
03039
03040   /*************************** Init phase ************************************/
03041
03042   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03043
03044   /* Set the key */
03045   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03046
03047   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03048   hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
03049   hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
03050   hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
03051   hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
03052
03053   /* Enable the CRYP peripheral */
03054   __HAL_CRYP_ENABLE(hcryp);
03055
03056   /*Wait for the CRYPEN bit to be cleared*/
03057   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03058   do
03059   {
03060     count-- ;
03061     if (count == 0U)
03062     {
03063       /* Disable the CRYP peripheral clock */
03064       __HAL_CRYP_DISABLE(hcryp);
03065
03066       /* Change state */
03067       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03068       hcryp->State = HAL_CRYP_STATE_READY;
03069
03070       /* Process unlocked */
03071       __HAL_UNLOCK(hcryp);
03072       return HAL_ERROR;
03073     }
03074   } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
03075
03076   /************************ Header phase *************************************/
03077
03078   if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
03079   {
03080     return HAL_ERROR;
03081   }
03082
03083   /************************ Payload phase ************************************/
03084
03085   /* Set the phase */
03086   hcryp->Phase = CRYP_PHASE_PROCESS;
03087
03088   /* Disable the CRYP peripheral */
03089   __HAL_CRYP_DISABLE(hcryp);
03090
03091 #if !defined (CRYP_VER_2_2)
03092   if (hcryp->Version >= REV_ID_B)
03093 #endif /*End of not defined CRYP_VER_2_2*/
03094   {
03095     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03096     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
03097   }
03098
03099   /* Select payload phase once the header phase is performed */
03100   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03101
03102   if (hcryp->Size == 0U)
03103   {
03104     /* Process unLocked */
03105     __HAL_UNLOCK(hcryp);
03106
03107     /* Change the CRYP state and phase */
03108     hcryp->State = HAL_CRYP_STATE_READY;
03109   }
03110   else if (hcryp->Size >= 16U)
03111   {
03112     /* for STM32H7 below rev.B : Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03113     Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise TAG is incorrectly generated */
03114
03115     /*DMA transfer must not include the last block in case of Size is not %16 */
03116     wordsize = wordsize - (wordsize % 4U);
03117
03118     /*DMA transfer */
03119     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
03120   }
03121   else /* length of input data is < 16 */
03122   {
03123     /* Compute the number of padding bytes in last block of payload */
03124     npblb = 16U - (uint32_t)hcryp->Size;
03125
03126 #if !defined (CRYP_VER_2_2)
03127     if (hcryp->Version >= REV_ID_B)
03128 #endif /*End of not defined CRYP_VER_2_2*/
03129     {
03130       /* Set Npblb in case of AES GCM payload encryption to get right tag*/
03131       if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
03132       {
03133         /* Specify the number of non-valid bytes using NPBLB register*/
03134         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
03135       }
03136     }
03137     /* Enable CRYP to start the final phase */
03138     __HAL_CRYP_ENABLE(hcryp);
03139
03140     /* Number of valid words (lastwordsize) in last block */
03141     if ((npblb % 4U) == 0U)
03142     {
03143       lastwordsize = (16U - npblb) / 4U;
03144     }
03145     else
03146     {
03147       lastwordsize = ((16U - npblb) / 4U) + 1U;
03148     }
03149
03150     /* Write the last input block in the IN FIFO */
03151     for (index = 0; index < lastwordsize; index ++)
03152     {
03153       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03154       hcryp->CrypInCount++;
03155     }
03156
03157     /* Pad the data with zeros to have a complete block */
03158     while (index < 4U)
03159     {
03160       hcryp->Instance->DIN  = 0U;
03161       index++;
03162     }
03163
03164     /* Wait for OFNE flag to be raised */
03165     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03166     do
03167     {
03168       count-- ;
03169       if (count == 0U)
03170       {
03171         /* Disable the CRYP peripheral clock */
03172         __HAL_CRYP_DISABLE(hcryp);
03173
03174         /* Change state */
03175         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03176         hcryp->State = HAL_CRYP_STATE_READY;
03177
03178         /* Process unlocked */
03179         __HAL_UNLOCK(hcryp);
03180 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
03181         /*Call registered error callback*/
03182         hcryp->ErrorCallback(hcryp);
03183 #else
03184         /*Call legacy weak error callback*/
03185         HAL_CRYP_ErrorCallback(hcryp);
03186 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03187       }
03188     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
03189
03190     /*Read the output block from the output FIFO */
03191     for (index = 0U; index < 4U; index++)
03192     {
03193       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03194       temp = hcryp->Instance->DOUT;
03195
03196       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03197       hcryp->CrypOutCount++;
03198     }
03199     /* Change the CRYP state to ready */
03200     hcryp->State = HAL_CRYP_STATE_READY;
03201
03202     /* Process unlocked */
03203     __HAL_UNLOCK(hcryp);
03204   }
03205
03206   /* Return function status */
03207   return HAL_OK;
03208 }
03209
03210
03211 /**
03212   * @brief  AES CCM encryption/decryption processing in polling mode
03213   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03214   *         the configuration information for CRYP module
03215   * @param  Timeout: Timeout duration
03216   * @retval HAL status
03217   */
03218 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03219 {
03220   uint32_t tickstart;
03221   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
03222   uint32_t npblb ;
03223   uint32_t lastwordsize ;
03224   uint32_t temp ;  /* Temporary CrypOutBuff */
03225   uint32_t index ;
03226   uint16_t outcount;  /* Temporary CrypOutCount Value */
03227
03228   /*  Reset CrypHeaderCount */
03229   hcryp->CrypHeaderCount = 0U;
03230
03231   /********************** Init phase ******************************************/
03232
03233   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03234
03235   /* Set the key */
03236   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03237
03238   /* Set the initialization vector (IV) with CTR1 information */
03239   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
03240   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
03241   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
03242   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
03243
03244   /* Enable the CRYP peripheral */
03245   __HAL_CRYP_ENABLE(hcryp);
03246
03247 #if defined (CRYP_VER_2_2)
03248   {
03249     /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
03250     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03251     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03252     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03253     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03254   }
03255 #else
03256   if (hcryp->Version >= REV_ID_B)
03257   {
03258     /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
03259     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03260     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03261     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03262     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03263   }
03264   else /* data has to be swapped according to the DATATYPE */
03265   {
03266     if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
03267     {
03268       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
03269       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
03270       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
03271       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
03272     }
03273     else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
03274     {
03275       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
03276       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
03277       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
03278       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
03279     }
03280     else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
03281     {
03282       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
03283       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
03284       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
03285       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
03286     }
03287     else
03288     {
03289       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03290       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03291       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03292       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03293     }
03294   }
03295 #endif
03296   /* Get tick */
03297   tickstart = HAL_GetTick();
03298
03299   /*Wait for the CRYPEN bit to be cleared*/
03300   while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
03301   {
03302     /* Check for the Timeout */
03303     if (Timeout != HAL_MAX_DELAY)
03304     {
03305       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03306       {
03307         /* Disable the CRYP peripheral clock */
03308         __HAL_CRYP_DISABLE(hcryp);
03309
03310         /* Change state */
03311         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03312         hcryp->State = HAL_CRYP_STATE_READY;
03313
03314         /* Process unlocked */
03315         __HAL_UNLOCK(hcryp);
03316         return HAL_ERROR;
03317       }
03318     }
03319   }
03320
03321   /************************* Header phase *************************************/
03322   /* Header block(B1) : associated data length expressed in bytes concatenated
03323   with Associated Data (A)*/
03324
03325   if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
03326   {
03327     return HAL_ERROR;
03328   }
03329   /********************** Payload phase ***************************************/
03330
03331   /* Set the phase */
03332   hcryp->Phase = CRYP_PHASE_PROCESS;
03333
03334   /* Disable the CRYP peripheral */
03335   __HAL_CRYP_DISABLE(hcryp);
03336 #if !defined (CRYP_VER_2_2)
03337   if (hcryp->Version >= REV_ID_B)
03338 #endif /*End of not defined CRYP_VER_2_2*/
03339   {
03340     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03341     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
03342   }
03343
03344   /* Select payload phase once the header phase is performed */
03345   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03346
03347   /* Enable the CRYP peripheral */
03348   __HAL_CRYP_ENABLE(hcryp);
03349
03350   if ((hcryp->Size % 16U) != 0U)
03351   {
03352     /* recalculate  wordsize */
03353     wordsize = ((wordsize / 4U) * 4U) ;
03354   }
03355   /* Get tick */
03356   tickstart = HAL_GetTick();
03357
03358   /*Temporary CrypOutCount Value*/
03359   outcount = hcryp->CrypOutCount;
03360
03361   /* Write input data and get output data */
03362   while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
03363   {
03364     /* Write plain data and get cipher data */
03365     CRYP_AES_ProcessData(hcryp, Timeout);
03366
03367     /*Temporary CrypOutCount Value*/
03368     outcount = hcryp->CrypOutCount;
03369
03370     /* Check for the Timeout */
03371     if (Timeout != HAL_MAX_DELAY)
03372     {
03373       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03374       {
03375         /* Disable the CRYP peripheral clock */
03376         __HAL_CRYP_DISABLE(hcryp);
03377
03378         /* Change state */
03379         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03380         hcryp->State = HAL_CRYP_STATE_READY;
03381
03382         /* Process unlocked */
03383         __HAL_UNLOCK(hcryp);
03384         return HAL_ERROR;
03385       }
03386     }
03387   }
03388
03389   if ((hcryp->Size % 16U) != 0U)
03390   {
03391 #if !defined (CRYP_VER_2_2)
03392     if (hcryp->Version >= REV_ID_B)
03393 #endif /*End of not defined CRYP_VER_2_2*/
03394     {
03395       /* Compute the number of padding bytes in last block of payload */
03396       npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
03397
03398       if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
03399       {
03400         /* Disable the CRYP */
03401         __HAL_CRYP_DISABLE(hcryp);
03402
03403         /* Set Npblb in case of AES CCM payload decryption to get right tag  */
03404         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
03405
03406         /* Enable CRYP to start the final phase */
03407         __HAL_CRYP_ENABLE(hcryp);
03408       }
03409
03410       /* Number of valid words (lastwordsize) in last block */
03411       if ((npblb % 4U) == 0U)
03412       {
03413         lastwordsize = (16U - npblb) / 4U;
03414       }
03415       else
03416       {
03417         lastwordsize = ((16U - npblb) / 4U) + 1U;
03418       }
03419
03420       /* Write the last input block in the IN FIFO */
03421       for (index = 0U; index < lastwordsize; index ++)
03422       {
03423         hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03424         hcryp->CrypInCount++;
03425       }
03426
03427       /* Pad the data with zeros to have a complete block */
03428       while (index < 4U)
03429       {
03430         hcryp->Instance->DIN  = 0U;
03431         index++;
03432       }
03433
03434       /* Wait for OFNE flag to be raised */
03435       if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
03436       {
03437         /* Disable the CRYP peripheral clock */
03438         __HAL_CRYP_DISABLE(hcryp);
03439
03440         /* Change state */
03441         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03442         hcryp->State = HAL_CRYP_STATE_READY;
03443
03444         /* Process Unlocked */
03445         __HAL_UNLOCK(hcryp);
03446 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
03447         /*Call registered error callback*/
03448         hcryp->ErrorCallback(hcryp);
03449 #else
03450         /*Call legacy weak error callback*/
03451         HAL_CRYP_ErrorCallback(hcryp);
03452 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03453       }
03454
03455       /*Read the output block from the output FIFO */
03456       if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
03457       {
03458         for (index = 0U; index < 4U; index++)
03459         {
03460           /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03461           temp = hcryp->Instance->DOUT;
03462
03463           *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03464           hcryp->CrypOutCount++;
03465         }
03466       }
03467     }
03468 #if !defined (CRYP_VER_2_2)
03469     else /* No NPBLB, Workaround to be used */
03470     {
03471       /* CRYP Workaround :  CRYP1 generates correct TAG  during CCM decryption only when ciphertext blocks size is multiple of
03472       128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
03473       is selected, then the TAG message will be wrong.*/
03474       CRYP_Workaround(hcryp, Timeout);
03475     }
03476 #endif /*End of not defined CRYP_VER_2_2*/
03477   }
03478
03479   /* Return function status */
03480   return HAL_OK;
03481 }
03482
03483 /**
03484   * @brief  AES CCM encryption/decryption process in interrupt mode
03485   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03486   *         the configuration information for CRYP module
03487   * @retval HAL status
03488   */
03489 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03490 {
03491   __IO uint32_t count = 0U;
03492
03493   /*  Reset CrypHeaderCount */
03494   hcryp->CrypHeaderCount = 0U;
03495
03496   /************ Init phase ************/
03497
03498   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03499
03500   /* Set the key */
03501   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03502
03503   /* Set the initialization vector (IV) with CTR1 information */
03504   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
03505   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
03506   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
03507   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
03508
03509   /* Enable the CRYP peripheral */
03510   __HAL_CRYP_ENABLE(hcryp);
03511
03512   /*Write the B0 packet into CRYP_DR*/
03513 #if !defined (CRYP_VER_2_2)
03514   if (hcryp->Version >= REV_ID_B)
03515 #endif /*End of not defined CRYP_VER_2_2*/
03516   {
03517     /* for STM32H7 rev.B and above data has not to be swapped */
03518     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03519     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03520     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03521     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03522   }
03523 #if !defined (CRYP_VER_2_2)
03524   else /* data has to be swapped according to the DATATYPE */
03525   {
03526     if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
03527     {
03528       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
03529       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
03530       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
03531       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
03532     }
03533     else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
03534     {
03535       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
03536       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
03537       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
03538       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
03539     }
03540     else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
03541     {
03542       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
03543       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
03544       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
03545       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
03546     }
03547     else
03548     {
03549       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03550       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03551       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03552       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03553     }
03554   }
03555 #endif /*End of not defined CRYP_VER_2_2*/
03556   /*Wait for the CRYPEN bit to be cleared*/
03557   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03558   do
03559   {
03560     count-- ;
03561     if (count == 0U)
03562     {
03563       /* Disable the CRYP peripheral clock */
03564       __HAL_CRYP_DISABLE(hcryp);
03565
03566       /* Change state */
03567       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03568       hcryp->State = HAL_CRYP_STATE_READY;
03569
03570       /* Process unlocked */
03571       __HAL_UNLOCK(hcryp);
03572       return HAL_ERROR;
03573     }
03574   } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
03575
03576   /* Select header phase */
03577   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03578
03579   /* Enable interrupts */
03580   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
03581
03582   /* Enable CRYP */
03583   __HAL_CRYP_ENABLE(hcryp);
03584
03585   /* Return function status */
03586   return HAL_OK;
03587 }
03588 /**
03589   * @brief  AES CCM encryption/decryption process in DMA mode
03590   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03591   *         the configuration information for CRYP module
03592   * @retval HAL status
03593   */
03594 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
03595 {
03596   __IO uint32_t count    = 0U;
03597   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
03598   uint32_t index;
03599   uint32_t npblb;
03600   uint32_t lastwordsize;
03601   uint32_t temp;  /* Temporary CrypOutBuff */
03602
03603   /*  Reset CrypHeaderCount */
03604   hcryp->CrypHeaderCount = 0U;
03605
03606   /************************** Init phase **************************************/
03607
03608   CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03609
03610   /* Set the key */
03611   CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03612
03613   /* Set the initialization vector (IV) with CTR1 information */
03614   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
03615   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
03616   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
03617   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
03618
03619   /* Enable the CRYP peripheral */
03620   __HAL_CRYP_ENABLE(hcryp);
03621
03622   /*Write the B0 packet into CRYP_DR*/
03623 #if !defined (CRYP_VER_2_2)
03624   if (hcryp->Version >= REV_ID_B)
03625 #endif /*End of not defined CRYP_VER_2_2*/
03626   {
03627     /* for STM32H7 rev.B and above data has not to be swapped */
03628     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03629     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03630     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03631     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03632   }
03633 #if !defined (CRYP_VER_2_2)
03634   else /* data has to be swapped according to the DATATYPE */
03635   {
03636     if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
03637     {
03638       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
03639       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
03640       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
03641       hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
03642     }
03643     else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
03644     {
03645       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
03646       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
03647       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
03648       hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
03649     }
03650     else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
03651     {
03652       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
03653       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
03654       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
03655       hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
03656     }
03657     else
03658     {
03659       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
03660       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
03661       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
03662       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
03663     }
03664   }
03665 #endif /*End of not defined CRYP_VER_2_2*/
03666   /*Wait for the CRYPEN bit to be cleared*/
03667   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03668   do
03669   {
03670     count-- ;
03671     if (count == 0U)
03672     {
03673       /* Disable the CRYP peripheral clock */
03674       __HAL_CRYP_DISABLE(hcryp);
03675
03676       /* Change state */
03677       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03678       hcryp->State = HAL_CRYP_STATE_READY;
03679
03680       /* Process unlocked */
03681       __HAL_UNLOCK(hcryp);
03682       return HAL_ERROR;
03683     }
03684   } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
03685
03686   /********************* Header phase *****************************************/
03687
03688   if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
03689   {
03690     return HAL_ERROR;
03691   }
03692
03693   /******************** Payload phase *****************************************/
03694
03695   /* Set the phase */
03696   hcryp->Phase = CRYP_PHASE_PROCESS;
03697
03698   /* Disable the CRYP peripheral */
03699   __HAL_CRYP_DISABLE(hcryp);
03700 #if !defined (CRYP_VER_2_2)
03701   if (hcryp->Version >= REV_ID_B)
03702 #endif /*End of not defined CRYP_VER_2_2*/
03703   {
03704     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03705     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
03706   }
03707
03708   /* Select payload phase once the header phase is performed */
03709   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03710
03711   if (hcryp->Size == 0U)
03712   {
03713     /* Process unLocked */
03714     __HAL_UNLOCK(hcryp);
03715
03716     /* Change the CRYP state and phase */
03717     hcryp->State = HAL_CRYP_STATE_READY;
03718   }
03719   else if (hcryp->Size >= 16U)
03720   {
03721     /* for STM32H7 below rev.B ::  Size should be %4  otherwise Tag will  be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/
03722     /*DMA transfer must not include the last block in case of Size is not %16 */
03723     wordsize = wordsize - (wordsize % 4U);
03724
03725     /*DMA transfer */
03726     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
03727   }
03728   else /* length of input data is  < 16U */
03729   {
03730     /* Compute the number of padding bytes in last block of payload */
03731     npblb = 16U - (uint32_t)(hcryp->Size);
03732
03733 #if !defined (CRYP_VER_2_2)
03734     if (hcryp->Version >= REV_ID_B)
03735 #endif /*End of not defined CRYP_VER_2_2*/
03736     {
03737       /* Set Npblb in case of AES CCM payload decryption to get right tag*/
03738       if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
03739       {
03740         /* Specify the number of non-valid bytes using NPBLB register*/
03741         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
03742       }
03743     }
03744     /* Enable CRYP to start the final phase */
03745     __HAL_CRYP_ENABLE(hcryp);
03746
03747     /* Number of valid words (lastwordsize) in last block */
03748     if ((npblb % 4U) == 0U)
03749     {
03750       lastwordsize = (16U - npblb) / 4U;
03751     }
03752     else
03753     {
03754       lastwordsize = ((16U - npblb) / 4U) + 1U;
03755     }
03756
03757     /* Write the last input block in the IN FIFO */
03758     for (index = 0U; index < lastwordsize; index ++)
03759     {
03760       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03761       hcryp->CrypInCount++;
03762     }
03763
03764     /* Pad the data with zeros to have a complete block */
03765     while (index < 4U)
03766     {
03767       hcryp->Instance->DIN  = 0U;
03768       index++;
03769     }
03770
03771     /* Wait for OFNE flag to be raised */
03772     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03773     do
03774     {
03775       count-- ;
03776       if (count == 0U)
03777       {
03778         /* Disable the CRYP peripheral clock */
03779         __HAL_CRYP_DISABLE(hcryp);
03780
03781         /* Change state */
03782         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03783         hcryp->State = HAL_CRYP_STATE_READY;
03784
03785         /* Process unlocked */
03786         __HAL_UNLOCK(hcryp);
03787 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
03788         /*Call registered error callback*/
03789         hcryp->ErrorCallback(hcryp);
03790 #else
03791         /*Call legacy weak error callback*/
03792         HAL_CRYP_ErrorCallback(hcryp);
03793 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03794       }
03795     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
03796
03797     /*Read the output block from the output FIFO */
03798     for (index = 0U; index < 4U; index++)
03799     {
03800       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03801       temp = hcryp->Instance->DOUT;
03802
03803       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03804       hcryp->CrypOutCount++;
03805     }
03806     /* Change the CRYP state to ready */
03807     hcryp->State = HAL_CRYP_STATE_READY;
03808
03809     /* Process unlocked */
03810     __HAL_UNLOCK(hcryp);
03811   }
03812
03813   /* Return function status */
03814   return HAL_OK;
03815 }
03816
03817 /**
03818   * @brief  Sets the payload phase in iterrupt mode
03819   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03820   *         the configuration information for CRYP module
03821   * @retval state
03822   */
03823 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
03824 {
03825   uint32_t loopcounter;
03826   uint32_t temp;  /* Temporary CrypOutBuff */
03827   uint32_t lastwordsize;
03828   uint32_t npblb;
03829   uint32_t temp_cr_algodir;
03830   uint8_t negative = 0U;
03831
03832   /***************************** Payload phase *******************************/
03833
03834   if ((hcryp->Size / 4U) < hcryp->CrypInCount)
03835   {
03836     negative = 1U;
03837   }
03838
03839   if (hcryp->Size == 0U)
03840   {
03841     /* Disable interrupts */
03842     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03843
03844     /* Process unlocked */
03845     __HAL_UNLOCK(hcryp);
03846
03847     /* Change the CRYP state */
03848     hcryp->State = HAL_CRYP_STATE_READY;
03849   }
03850
03851   else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
03852            (negative == 0U))
03853   {
03854     if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
03855     {
03856       /* Write the input block in the IN FIFO */
03857       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03858       hcryp->CrypInCount++;
03859       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03860       hcryp->CrypInCount++;
03861       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03862       hcryp->CrypInCount++;
03863       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03864       hcryp->CrypInCount++;
03865       if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
03866       {
03867         /* Disable interrupts */
03868         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03869
03870         /* Call the input data transfer complete callback */
03871 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03872         /*Call registered Input complete callback*/
03873         hcryp->InCpltCallback(hcryp);
03874 #else
03875         /*Call legacy weak Input complete callback*/
03876         HAL_CRYP_InCpltCallback(hcryp);
03877 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03878       }
03879
03880       if (hcryp->CrypOutCount < (hcryp->Size / 4U))
03881       {
03882         if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
03883         {
03884           /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
03885           temp  = hcryp->Instance->DOUT;
03886           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
03887           hcryp->CrypOutCount++;
03888           temp  = hcryp->Instance->DOUT;
03889           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
03890           hcryp->CrypOutCount++;
03891           temp  = hcryp->Instance->DOUT;
03892           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
03893           hcryp->CrypOutCount++;
03894           temp  = hcryp->Instance->DOUT;
03895           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
03896           hcryp->CrypOutCount++;
03897           if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
03898           {
03899             /* Disable interrupts */
03900             __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03901
03902             /* Change the CRYP state */
03903             hcryp->State = HAL_CRYP_STATE_READY;
03904
03905             /* Disable CRYP */
03906             __HAL_CRYP_DISABLE(hcryp);
03907
03908             /* Process unlocked */
03909             __HAL_UNLOCK(hcryp);
03910
03911             /* Call output transfer complete callback */
03912 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03913         /*Call registered Output complete callback*/
03914         hcryp->OutCpltCallback(hcryp);
03915 #else
03916         /*Call legacy weak Output complete callback*/
03917         HAL_CRYP_OutCpltCallback(hcryp);
03918 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03919           }
03920         }
03921       }
03922     }
03923   }
03924   else if ((hcryp->Size % 16U) != 0U)
03925   {
03926         /* Set padding only in case of input fifo interrupt */
03927         if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
03928  {
03929     /* Compute the number of padding bytes in last block of payload */
03930     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
03931
03932 #if !defined (CRYP_VER_2_2)
03933     if (hcryp->Version >= REV_ID_B)
03934 #endif /*End of not defined CRYP_VER_2_2*/
03935     {
03936       /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
03937       temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
03938
03939       if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
03940           ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
03941       {
03942         /* Disable the CRYP */
03943         __HAL_CRYP_DISABLE(hcryp);
03944
03945         /* Specify the number of non-valid bytes using NPBLB register*/
03946         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
03947
03948         /* Enable CRYP to start the final phase */
03949         __HAL_CRYP_ENABLE(hcryp);
03950       }
03951     }
03952
03953     /* Number of valid words (lastwordsize) in last block */
03954     if ((npblb % 4U) == 0U)
03955     {
03956       lastwordsize = (16U - npblb) / 4U;
03957     }
03958     else
03959     {
03960       lastwordsize = ((16U - npblb) / 4U) + 1U;
03961     }
03962
03963     /* Write the last input block in the IN FIFO */
03964     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
03965     {
03966       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03967       hcryp->CrypInCount++;
03968     }
03969     /* Pad the data with zeros to have a complete block */
03970     while (loopcounter < 4U)
03971     {
03972       hcryp->Instance->DIN  = 0U;
03973       loopcounter++;
03974     }
03975
03976     /* Disable the input FIFO Interrupt */
03977     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03978         }
03979
03980     /*Read the output block from the output FIFO */
03981     if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
03982     {
03983       for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
03984       {
03985         /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03986         temp = hcryp->Instance->DOUT;
03987
03988         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03989         hcryp->CrypOutCount++;
03990       }
03991     }
03992
03993     /* Disable the output FIFO Interrupt */
03994     if (hcryp->CrypOutCount > ((hcryp->Size) / 4U))
03995     {
03996       /* Disable interrupts */
03997       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
03998
03999       /* Change the CRYP peripheral state */
04000       hcryp->State = HAL_CRYP_STATE_READY;
04001
04002       /* Process unlocked */
04003       __HAL_UNLOCK(hcryp);
04004
04005       /* Call output transfer complete callback */
04006 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04007       /*Call registered Output complete callback*/
04008       hcryp->OutCpltCallback(hcryp);
04009 #else
04010       /*Call legacy weak Output complete callback*/
04011       HAL_CRYP_OutCpltCallback(hcryp);
04012 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04013     }
04014   }
04015   else
04016   {
04017     /* Nothing to do */
04018   }
04019 }
04020
04021
04022 /**
04023   * @brief  Sets the header phase in polling mode
04024   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04025   *         the configuration information for CRYP module(Header & HeaderSize)
04026   * @param  Timeout: Timeout value
04027   * @retval state
04028   */
04029 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04030 {
04031   uint32_t loopcounter;
04032
04033   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04034
04035   if ((hcryp->Init.HeaderSize != 0U))
04036   {
04037     /* Select header phase */
04038     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04039
04040     /* Enable the CRYP peripheral */
04041     __HAL_CRYP_ENABLE(hcryp);
04042
04043     if ((hcryp->Init.HeaderSize % 4U) == 0U)
04044     {
04045       /* HeaderSize %4, no padding */
04046       for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
04047       {
04048         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04049         hcryp->CrypHeaderCount++ ;
04050         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04051         hcryp->CrypHeaderCount++ ;
04052         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04053         hcryp->CrypHeaderCount++ ;
04054         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04055         hcryp->CrypHeaderCount++ ;
04056
04057         /* Wait for IFEM to be raised */
04058         if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
04059         {
04060           /* Disable the CRYP peripheral clock */
04061           __HAL_CRYP_DISABLE(hcryp);
04062
04063           /* Change state */
04064           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04065           hcryp->State = HAL_CRYP_STATE_READY;
04066
04067           /* Process unlocked */
04068           __HAL_UNLOCK(hcryp);
04069           return HAL_ERROR;
04070         }
04071       }
04072     }
04073     else
04074     {
04075       /*Write header block in the IN FIFO without last block */
04076       for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
04077       {
04078         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04079         hcryp->CrypHeaderCount++ ;
04080         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04081         hcryp->CrypHeaderCount++ ;
04082         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04083         hcryp->CrypHeaderCount++ ;
04084         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04085         hcryp->CrypHeaderCount++ ;
04086
04087         /* Wait for IFEM to be raised */
04088         if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
04089         {
04090           /* Disable the CRYP peripheral clock */
04091           __HAL_CRYP_DISABLE(hcryp);
04092
04093           /* Change state */
04094           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04095           hcryp->State = HAL_CRYP_STATE_READY;
04096
04097           /* Process unlocked */
04098           __HAL_UNLOCK(hcryp);
04099           return HAL_ERROR;
04100         }
04101       }
04102       /*  Last block optionally pad the data with zeros*/
04103       for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
04104       {
04105         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04106         hcryp->CrypHeaderCount++ ;
04107       }
04108       while (loopcounter < 4U)
04109       {
04110         /* pad the data with zeros to have a complete block */
04111         hcryp->Instance->DIN = 0x0U;
04112         loopcounter++;
04113       }
04114       /* Wait for CCF IFEM to be raised */
04115       if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
04116       {
04117         /* Disable the CRYP peripheral clock */
04118         __HAL_CRYP_DISABLE(hcryp);
04119
04120         /* Change state */
04121         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04122         hcryp->State = HAL_CRYP_STATE_READY;
04123
04124         /* Process unlocked */
04125         __HAL_UNLOCK(hcryp);
04126         return HAL_ERROR;
04127       }
04128     }
04129     /* Wait until the complete message has been processed */
04130     if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
04131     {
04132       /* Disable the CRYP peripheral clock */
04133       __HAL_CRYP_DISABLE(hcryp);
04134
04135       /* Change state */
04136       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04137       hcryp->State = HAL_CRYP_STATE_READY;
04138
04139       /* Process unlocked & return error */
04140       __HAL_UNLOCK(hcryp);
04141       return HAL_ERROR;
04142     }
04143   }
04144   /* Return function status */
04145   return HAL_OK;
04146 }
04147
04148 /**
04149   * @brief  Sets the header phase when using DMA in process
04150   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04151   *         the configuration information for CRYP module(Header & HeaderSize)
04152   * @retval None
04153   */
04154 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
04155 {
04156   __IO uint32_t count  = 0U;
04157   uint32_t loopcounter;
04158
04159   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04160   if ((hcryp->Init.HeaderSize != 0U))
04161   {
04162     /* Select header phase */
04163     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04164
04165     /* Enable the CRYP peripheral */
04166     __HAL_CRYP_ENABLE(hcryp);
04167
04168     if ((hcryp->Init.HeaderSize % 4U) == 0U)
04169     {
04170       /* HeaderSize %4, no padding */
04171       for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
04172       {
04173         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04174         hcryp->CrypHeaderCount++ ;
04175         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04176         hcryp->CrypHeaderCount++ ;
04177         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04178         hcryp->CrypHeaderCount++ ;
04179         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04180         hcryp->CrypHeaderCount++ ;
04181
04182         /* Wait for IFEM to be raised */
04183         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04184         do
04185         {
04186           count-- ;
04187           if (count == 0U)
04188           {
04189             /* Disable the CRYP peripheral clock */
04190             __HAL_CRYP_DISABLE(hcryp);
04191
04192             /* Change state */
04193             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04194             hcryp->State = HAL_CRYP_STATE_READY;
04195
04196             /* Process unlocked */
04197             __HAL_UNLOCK(hcryp);
04198             return HAL_ERROR;
04199           }
04200         } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
04201       }
04202     }
04203     else
04204     {
04205       /*Write header block in the IN FIFO without last block */
04206       for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
04207       {
04208         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04209         hcryp->CrypHeaderCount++ ;
04210         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04211         hcryp->CrypHeaderCount++ ;
04212         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04213         hcryp->CrypHeaderCount++ ;
04214         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04215         hcryp->CrypHeaderCount++ ;
04216
04217         /* Wait for IFEM to be raised */
04218         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04219         do
04220         {
04221           count-- ;
04222           if (count == 0U)
04223           {
04224             /* Disable the CRYP peripheral clock */
04225             __HAL_CRYP_DISABLE(hcryp);
04226
04227             /* Change state */
04228             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04229             hcryp->State = HAL_CRYP_STATE_READY;
04230
04231             /* Process unlocked */
04232             __HAL_UNLOCK(hcryp);
04233             return HAL_ERROR;
04234           }
04235         } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
04236       }
04237       /*  Last block optionally pad the data with zeros*/
04238       for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
04239       {
04240         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04241         hcryp->CrypHeaderCount++ ;
04242       }
04243       while (loopcounter < 4U)
04244       {
04245         /* Pad the data with zeros to have a complete block */
04246         hcryp->Instance->DIN = 0x0U;
04247         loopcounter++;
04248       }
04249       /* Wait for IFEM to be raised */
04250       count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04251       do
04252       {
04253         count-- ;
04254         if (count == 0U)
04255         {
04256           /* Disable the CRYP peripheral clock */
04257           __HAL_CRYP_DISABLE(hcryp);
04258           /* Change state */
04259           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04260           hcryp->State = HAL_CRYP_STATE_READY;
04261           /* Process unlocked */
04262           __HAL_UNLOCK(hcryp);
04263           return HAL_ERROR;
04264         }
04265       } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
04266     }
04267     /* Wait until the complete message has been processed */
04268     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04269     do
04270     {
04271       count-- ;
04272       if (count == 0U)
04273       {
04274         /* Disable the CRYP peripheral clock */
04275         __HAL_CRYP_DISABLE(hcryp);
04276         /* Change state */
04277         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04278         hcryp->State = HAL_CRYP_STATE_READY;
04279         /* Process unlocked */
04280         __HAL_UNLOCK(hcryp);
04281         return HAL_ERROR;
04282       }
04283     } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
04284   }
04285
04286   /* Return function status */
04287   return HAL_OK;
04288 }
04289
04290 /**
04291   * @brief  Sets the header phase in interrupt mode
04292   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04293   *         the configuration information for CRYP module(Header & HeaderSize)
04294   * @retval None
04295   */
04296 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
04297 {
04298   uint32_t loopcounter;
04299
04300   /***************************** Header phase *********************************/
04301
04302   if (hcryp->Init.HeaderSize ==  hcryp->CrypHeaderCount)
04303   {
04304     /* Disable interrupts */
04305     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
04306
04307     /* Disable the CRYP peripheral */
04308     __HAL_CRYP_DISABLE(hcryp);
04309
04310 #if !defined (CRYP_VER_2_2)
04311     if (hcryp->Version >= REV_ID_B)
04312 #endif /*End of not defined CRYP_VER_2_2*/
04313     {
04314       /* Set to 0 the number of non-valid bytes using NPBLB register*/
04315       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
04316     }
04317
04318     /* Set the phase */
04319     hcryp->Phase = CRYP_PHASE_PROCESS;
04320
04321     /* Select payload phase once the header phase is performed */
04322     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
04323
04324     /* Enable Interrupts */
04325     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
04326
04327     /* Enable the CRYP peripheral */
04328     __HAL_CRYP_ENABLE(hcryp);
04329   }
04330   else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
04331
04332   {
04333     /* HeaderSize %4, no padding */
04334     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04335     hcryp->CrypHeaderCount++ ;
04336     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04337     hcryp->CrypHeaderCount++  ;
04338     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04339     hcryp->CrypHeaderCount++ ;
04340     hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04341     hcryp->CrypHeaderCount++ ;
04342   }
04343   else
04344   {
04345     /*  Last block optionally pad the data with zeros*/
04346     for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
04347     {
04348       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04349       hcryp->CrypHeaderCount++ ;
04350     }
04351     while (loopcounter < 4U)
04352     {
04353       /* Pad the data with zeros to have a complete block */
04354       hcryp->Instance->DIN = 0x0U;
04355       loopcounter++;
04356     }
04357   }
04358 }
04359
04360 #if !defined (CRYP_VER_2_2)
04361 /**
04362   * @brief  Workaround used for GCM/CCM mode.
04363   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04364   *         the configuration information for CRYP module
04365   * @param  Timeout: Timeout value
04366   * @retval None
04367   */
04368 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04369 {
04370   uint32_t  iv1temp;
04371   uint32_t  temp[4] = {0};
04372   uint32_t  temp2[4] = {0};
04373   uint32_t intermediate_data[4] = {0};
04374   uint32_t index;
04375   uint32_t lastwordsize;
04376   uint32_t npblb;
04377
04378   /* Compute the number of padding bytes in last block of payload */
04379   npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
04380
04381   /* Number of valid words (lastwordsize) in last block */
04382   if ((npblb % 4U) == 0U)
04383   {
04384     lastwordsize = (16U - npblb) / 4U;
04385   }
04386   else
04387   {
04388     lastwordsize = ((16U - npblb) / 4U) + 1U;
04389   }
04390
04391   /* Workaround 2, case GCM encryption */
04392   if (hcryp->Init.Algorithm == CRYP_AES_GCM)
04393   {
04394     if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
04395     {
04396       /*Workaround in order to properly compute authentication tags while doing
04397        a GCM encryption with the last block of payload size inferior to 128 bits*/
04398       /* Disable CRYP to start the final phase */
04399       __HAL_CRYP_DISABLE(hcryp);
04400
04401       /*Update CRYP_IV1R register and ALGOMODE*/
04402       hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1U);
04403       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
04404
04405       /* Enable CRYP to start the final phase */
04406       __HAL_CRYP_ENABLE(hcryp);
04407     }
04408
04409     for (index = 0; index < lastwordsize ; index ++)
04410     {
04411       /* Write the last input block in the IN FIFO */
04412       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04413       hcryp->CrypInCount++;
04414     }
04415     while (index < 4U)
04416     {
04417       /* Pad the data with zeros to have a complete block */
04418       hcryp->Instance->DIN  = 0U;
04419       index++;
04420     }
04421     /* Wait for OFNE flag to be raised */
04422     if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
04423     {
04424       /* Disable the CRYP peripheral clock */
04425       __HAL_CRYP_DISABLE(hcryp);
04426
04427       /* Change state */
04428       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04429       hcryp->State = HAL_CRYP_STATE_READY;
04430
04431       /* Process Unlocked */
04432       __HAL_UNLOCK(hcryp);
04433 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
04434       /*Call registered error callback*/
04435       hcryp->ErrorCallback(hcryp);
04436 #else
04437       /*Call legacy weak error callback*/
04438       HAL_CRYP_ErrorCallback(hcryp);
04439 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04440     }
04441     if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
04442     {
04443       for (index = 0U; index < 4U; index++)
04444       {
04445         /* Read the output block from the output FIFO */
04446         intermediate_data[index] = hcryp->Instance->DOUT;
04447
04448         /* Intermediate data buffer to be used in for the workaround*/
04449         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
04450         hcryp->CrypOutCount++;
04451       }
04452     }
04453
04454     if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
04455     {
04456       /*workaround in order to properly compute authentication tags while doing
04457       a GCM encryption with the last block of payload size inferior to 128 bits*/
04458       /* Change the AES mode to GCM mode and Select Final phase */
04459       /* configured  CHMOD GCM   */
04460       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
04461
04462       /* configured  final phase  */
04463       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
04464
04465       if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
04466       {
04467         if ((npblb %4U)==1U)
04468         {
04469           intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
04470         }
04471         if ((npblb %4U)==2U)
04472         {
04473           intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
04474         }
04475         if ((npblb %4U)==3U)
04476         {
04477           intermediate_data[lastwordsize-1U] &= 0xFF000000U;
04478         }
04479       }
04480       else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
04481       {
04482         if ((npblb %4U)==1U)
04483         {
04484           intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
04485         }
04486         if ((npblb %4U)==2U)
04487         {
04488           intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
04489         }
04490         if ((npblb %4U)==3U)
04491         {
04492           intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
04493         }
04494       }
04495       else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
04496       {
04497         if ((npblb %4U)==1U)
04498         {
04499           intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
04500         }
04501         if ((npblb %4U)==2U)
04502         {
04503           intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
04504         }
04505         if ((npblb %4U)==3U)
04506         {
04507           intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
04508         }
04509       }
04510       else /*CRYP_DATATYPE_1B*/
04511       {
04512         if ((npblb %4U)==1U)
04513         {
04514           intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
04515         }
04516         if ((npblb %4U)==2U)
04517         {
04518           intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
04519         }
04520         if ((npblb %4U)==3U)
04521         {
04522           intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
04523         }
04524       }
04525
04526       for (index = 0U; index < lastwordsize ; index ++)
04527       {
04528         /*Write the intermediate_data in the IN FIFO */
04529         hcryp->Instance->DIN = intermediate_data[index];
04530       }
04531       while (index < 4U)
04532       {
04533         /* Pad the data with zeros to have a complete block */
04534         hcryp->Instance->DIN  = 0x0U;
04535         index++;
04536       }
04537       /* Wait for OFNE flag to be raised */
04538       if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
04539       {
04540         /* Disable the CRYP peripheral clock */
04541         __HAL_CRYP_DISABLE(hcryp);
04542
04543         /* Change state */
04544         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04545         hcryp->State = HAL_CRYP_STATE_READY;
04546
04547         /* Process unlocked */
04548         __HAL_UNLOCK(hcryp);
04549 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04550         /*Call registered error callback*/
04551         hcryp->ErrorCallback(hcryp);
04552 #else
04553         /*Call legacy weak error callback*/
04554         HAL_CRYP_ErrorCallback(hcryp);
04555 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04556       }
04557
04558       if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
04559       {
04560         for (index = 0U; index < 4U; index++)
04561         {
04562           intermediate_data[index] = hcryp->Instance->DOUT;
04563         }
04564       }
04565     }
04566   } /* End of GCM encryption */
04567   else
04568   {
04569     /* Workaround 2, case CCM decryption, in order to properly compute
04570       authentication tags while doing a CCM decryption with the last block
04571       of payload size inferior to 128 bits*/
04572
04573     if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
04574     {
04575       iv1temp = hcryp->Instance->CSGCMCCM7R;
04576
04577       /* Disable CRYP to start the final phase */
04578       __HAL_CRYP_DISABLE(hcryp);
04579
04580       temp[0] =  hcryp->Instance->CSGCMCCM0R;
04581       temp[1] =  hcryp->Instance->CSGCMCCM1R;
04582       temp[2] =  hcryp->Instance->CSGCMCCM2R;
04583       temp[3] =  hcryp->Instance->CSGCMCCM3R;
04584
04585       hcryp->Instance->IV1RR = iv1temp;
04586
04587       /* Configured  CHMOD CTR   */
04588       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
04589
04590       /* Enable CRYP to start the final phase */
04591       __HAL_CRYP_ENABLE(hcryp);
04592     }
04593     /*  Last block optionally pad the data with zeros*/
04594     for (index = 0; index < lastwordsize; index ++)
04595     {
04596       /* Write the last Input block in the IN FIFO */
04597       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04598       hcryp->CrypInCount++;
04599     }
04600     while (index < 4U)
04601     {
04602       /* Pad the data with zeros to have a complete block */
04603       hcryp->Instance->DIN  = 0U;
04604       index++;
04605     }
04606     /* Wait for OFNE flag to be raised */
04607     if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
04608     {
04609       /* Disable the CRYP peripheral clock */
04610       __HAL_CRYP_DISABLE(hcryp);
04611
04612       /* Change state */
04613       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04614       hcryp->State = HAL_CRYP_STATE_READY;
04615
04616       /* Process Unlocked */
04617       __HAL_UNLOCK(hcryp);
04618 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
04619       /*Call registered error callback*/
04620       hcryp->ErrorCallback(hcryp);
04621 #else
04622       /*Call legacy weak error callback*/
04623       HAL_CRYP_ErrorCallback(hcryp);
04624 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04625     }
04626
04627     if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
04628     {
04629       for (index = 0U; index < 4U; index++)
04630       {
04631         /* Read the Output block from the Output FIFO */
04632         intermediate_data[index] = hcryp->Instance->DOUT;
04633
04634         /*intermediate data buffer to be used in for the workaround*/
04635         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
04636         hcryp->CrypOutCount++;
04637       }
04638     }
04639
04640     if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
04641     {
04642       temp2[0] =  hcryp->Instance->CSGCMCCM0R;
04643       temp2[1] =  hcryp->Instance->CSGCMCCM1R;
04644       temp2[2] =  hcryp->Instance->CSGCMCCM2R;
04645       temp2[3] =  hcryp->Instance->CSGCMCCM3R;
04646
04647       /* configured  CHMOD CCM   */
04648       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
04649
04650       /* configured  Header phase  */
04651       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
04652
04653       /*set to zero the bits corresponding to the padded bits*/
04654       for (index = lastwordsize; index < 4U; index ++)
04655       {
04656         intermediate_data[index] = 0U;
04657       }
04658
04659       if ((npblb % 4U) == 1U)
04660       {
04661         intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
04662       }
04663       if ((npblb % 4U) == 2U)
04664       {
04665         intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
04666       }
04667       if ((npblb % 4U) == 3U)
04668       {
04669         intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
04670       }
04671
04672       for (index = 0U; index < 4U ; index ++)
04673       {
04674         intermediate_data[index] ^=  temp[index];
04675         intermediate_data[index] ^=  temp2[index];
04676       }
04677       for (index = 0U; index < 4U; index ++)
04678       {
04679         /* Write the last Input block in the IN FIFO */
04680         hcryp->Instance->DIN  = intermediate_data[index] ;
04681       }
04682
04683       /* Wait for BUSY flag to be raised */
04684       if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
04685       {
04686         /* Disable the CRYP peripheral clock */
04687         __HAL_CRYP_DISABLE(hcryp);
04688
04689         /* Change state */
04690         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04691         hcryp->State = HAL_CRYP_STATE_READY;
04692
04693         /* Process Unlocked */
04694         __HAL_UNLOCK(hcryp);
04695 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
04696         /*Call registered error callback*/
04697         hcryp->ErrorCallback(hcryp);
04698 #else
04699         /*Call legacy weak error callback*/
04700         HAL_CRYP_ErrorCallback(hcryp);
04701 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04702       }
04703     }
04704   } /* End of CCM WKA*/
04705
04706   /* Process Unlocked */
04707   __HAL_UNLOCK(hcryp);
04708 }
04709 #endif /*End of not defined CRYP_VER_2_2*/
04710
04711 /**
04712   * @brief  Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
04713   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04714   *         the configuration information for CRYP module.
04715   * @param  Timeout: Timeout duration.
04716   * @retval HAL status
04717   */
04718 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04719 {
04720   uint32_t tickstart;
04721
04722   /* Get timeout */
04723   tickstart = HAL_GetTick();
04724
04725   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
04726   {
04727     /* Check for the Timeout */
04728     if (Timeout != HAL_MAX_DELAY)
04729     {
04730       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
04731       {
04732         return HAL_ERROR;
04733       }
04734     }
04735   }
04736   return HAL_OK;
04737 }
04738 /**
04739   * @brief  Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
04740   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04741   *         the configuration information for CRYP module.
04742   * @param  Timeout: Timeout duration.
04743   * @retval HAL status
04744   */
04745 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04746 {
04747   uint32_t tickstart;
04748
04749   /* Get timeout */
04750   tickstart = HAL_GetTick();
04751
04752   while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
04753   {
04754     /* Check for the Timeout */
04755     if (Timeout != HAL_MAX_DELAY)
04756     {
04757       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
04758       {
04759         return HAL_ERROR;
04760       }
04761     }
04762   }
04763   return HAL_OK;
04764 }
04765
04766
04767 /**
04768   * @brief  Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
04769   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
04770   *         the configuration information for CRYP module.
04771   * @param  Timeout: Timeout duration.
04772   * @retval HAL status
04773   */
04774 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef  *hcryp, uint32_t Timeout)
04775 {
04776   uint32_t tickstart;
04777
04778   /* Get timeout */
04779   tickstart = HAL_GetTick();
04780
04781   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
04782   {
04783     /* Check for the Timeout */
04784     if (Timeout != HAL_MAX_DELAY)
04785     {
04786       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
04787       {
04788         return HAL_ERROR;
04789       }
04790     }
04791   }
04792   return HAL_OK;
04793 }
04794
04795
04796 /**
04797   * @}
04798   */
04799
04800
04801
04802 /**
04803   * @}
04804   */
04805
04806 /**
04807   * @}
04808   */
04809
04810 #endif /* HAL_CRYP_MODULE_ENABLED */
04811
04812
04813 /**
04814   * @}
04815   */
04816 #endif /* CRYP */
04817 /**
04818   * @}
04819   */
04820
04821 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp.h Source File

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stm32h7xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CRYP_H
00022 #define STM32H7xx_HAL_CRYP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035 #if defined (CRYP)
00036 /** @addtogroup CRYP
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief CRYP Init Structure definition
00047   */
00048
00049 typedef struct
00050 {
00051   uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00052                                         This parameter can be a value of @ref CRYP_Data_Type */
00053   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
00054                                             This parameter can be a value of @ref CRYP_Key_Size */
00055   uint32_t *pKey;                      /*!< The key used for encryption/decryption */
00056   uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
00057                                          counter in CTR mode */
00058   uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
00059                                         AES Algorithm ECB/CBC/CTR/GCM or CCM
00060                                         This parameter can be a value of @ref CRYP_Algorithm_Mode */
00061   uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
00062                                         GCM : also known as Additional Authentication Data
00063                                         CCM : named B1 composed of the associated data length and Associated Data. */
00064   uint32_t HeaderSize;                /*!< The size of header buffer in word  */
00065   uint32_t *B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */
00066   uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
00067
00068 } CRYP_ConfigTypeDef;
00069
00070
00071 /**
00072   * @brief  CRYP State Structure definition
00073   */
00074
00075 typedef enum
00076 {
00077   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00078   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00079   HAL_CRYP_STATE_BUSY              = 0x02U  /*!< CRYP BUSY, internal processing is ongoing  */
00080 } HAL_CRYP_STATETypeDef;
00081
00082
00083 /**
00084   * @brief  CRYP handle Structure definition
00085   */
00086
00087 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00088 typedef struct __CRYP_HandleTypeDef
00089 #else
00090 typedef struct
00091 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00092 {
00093
00094   CRYP_TypeDef                      *Instance;            /*!< CRYP registers base address */
00095
00096   CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
00097
00098   uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00099
00100   uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00101
00102   __IO uint16_t                     CrypHeaderCount;   /*!< Counter of header data */
00103
00104   __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
00105
00106   __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
00107
00108   uint16_t                          Size;           /*!< length of input data in word */
00109
00110   uint32_t                          Phase;            /*!< CRYP peripheral phase */
00111
00112   DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
00113
00114   DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
00115
00116   HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
00117
00118   __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
00119
00120   __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
00121
00122   uint32_t                          Version;          /*!< CRYP1 IP version*/
00123
00124 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00125   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
00126   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
00127   void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
00128
00129   void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
00130   void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
00131
00132 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00133
00134 } CRYP_HandleTypeDef;
00135
00136
00137 /**
00138   * @}
00139   */
00140
00141 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00142 /** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
00143   * @brief  HAL CRYP Callback ID enumeration definition
00144   * @{
00145   */
00146 typedef enum
00147 {
00148   HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x01U,    /*!< CRYP Input FIFO transfer completed callback ID */
00149   HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x02U,    /*!< CRYP Output FIFO transfer completed callback ID */
00150   HAL_CRYP_ERROR_CB_ID             = 0x03U,    /*!< CRYP Error callback ID           */
00151
00152   HAL_CRYP_MSPINIT_CB_ID        = 0x04U,    /*!< CRYP MspInit callback ID         */
00153   HAL_CRYP_MSPDEINIT_CB_ID      = 0x05U     /*!< CRYP MspDeInit callback ID       */
00154
00155 } HAL_CRYP_CallbackIDTypeDef;
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
00161   * @brief  HAL CRYP Callback pointer definition
00162   * @{
00163   */
00164
00165 typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
00166
00167 /**
00168   * @}
00169   */
00170
00171 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00172
00173 /* Exported constants --------------------------------------------------------*/
00174 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00175   * @{
00176   */
00177
00178 /** @defgroup CRYP_Error_Definition   CRYP Error Definition
00179   * @{
00180   */
00181 #define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
00182 #define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
00183 #define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
00184 #define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
00185 #define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
00186 #define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
00187 #define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
00188 #define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
00189 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00190 #define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
00191 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00192
00193 /**
00194   * @}
00195   */
00196
00197
00198 /** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
00199   * @{
00200   */
00201
00202 #define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
00203 #define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is word */
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
00210   * @{
00211   */
00212
00213 #define CRYP_DES_ECB     CRYP_CR_ALGOMODE_DES_ECB
00214 #define CRYP_DES_CBC     CRYP_CR_ALGOMODE_DES_CBC
00215 #define CRYP_TDES_ECB    CRYP_CR_ALGOMODE_TDES_ECB
00216 #define CRYP_TDES_CBC    CRYP_CR_ALGOMODE_TDES_CBC
00217 #define CRYP_AES_ECB     CRYP_CR_ALGOMODE_AES_ECB
00218 #define CRYP_AES_CBC     CRYP_CR_ALGOMODE_AES_CBC
00219 #define CRYP_AES_CTR     CRYP_CR_ALGOMODE_AES_CTR
00220 #define CRYP_AES_GCM     CRYP_CR_ALGOMODE_AES_GCM
00221 #define CRYP_AES_CCM     CRYP_CR_ALGOMODE_AES_CCM
00222
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup CRYP_Key_Size CRYP Key Size
00228   * @{
00229   */
00230
00231 #define CRYP_KEYSIZE_128B         0x00000000U
00232 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
00233 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup CRYP_Data_Type CRYP Data Type
00240   * @{
00241   */
00242
00243 #define CRYP_DATATYPE_32B         0x00000000U
00244 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
00245 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
00246 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CRYP_Interrupt  CRYP Interrupt
00253   * @{
00254   */
00255
00256 #define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< Input FIFO Interrupt */
00257 #define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< Output FIFO Interrupt */
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup CRYP_Flags CRYP Flags
00264   * @{
00265   */
00266
00267 /* Flags in the SR register */
00268 #define CRYP_FLAG_IFEM    CRYP_SR_IFEM  /*!< Input FIFO is empty */
00269 #define CRYP_FLAG_IFNF    CRYP_SR_IFNF  /*!< Input FIFO is not Full */
00270 #define CRYP_FLAG_OFNE    CRYP_SR_OFNE  /*!< Output FIFO is not empty */
00271 #define CRYP_FLAG_OFFU    CRYP_SR_OFFU  /*!< Output FIFO is Full */
00272 #define CRYP_FLAG_BUSY    CRYP_SR_BUSY  /*!< The CRYP core is currently processing a block of data
00273                                              or a key preparation (for AES decryption). */
00274 /* Flags in the RISR register */
00275 #define CRYP_FLAG_OUTRIS  0x01000002U  /*!< Output FIFO service raw interrupt status */
00276 #define CRYP_FLAG_INRIS   0x01000001U  /*!< Input FIFO service raw interrupt status*/
00277
00278 /**
00279   * @}
00280   */
00281
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Exported macros -----------------------------------------------------------*/
00288 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00289   * @{
00290   */
00291
00292 /** @brief Reset CRYP handle state
00293   * @param  __HANDLE__ specifies the CRYP handle.
00294   * @retval None
00295   */
00296 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00297 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
00298                                                       (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
00299                                                       (__HANDLE__)->MspInitCallback = NULL;\
00300                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00301                                                      }while(0)
00302 #else
00303 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00304 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00305
00306 /**
00307   * @brief  Enable/Disable the CRYP peripheral.
00308   * @param  __HANDLE__: specifies the CRYP handle.
00309   * @retval None
00310   */
00311
00312 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
00313 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
00314
00315 /** @brief  Check whether the specified CRYP status flag is set or not.
00316   * @param  __FLAG__: specifies the flag to check.
00317   *         This parameter can be one of the following values for CRYP:
00318   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00319   *                                 or a key preparation (for AES decryption).
00320   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00321   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00322   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00323   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00324   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00325   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00326   * @retval The state of __FLAG__ (TRUE or FALSE).
00327   */
00328 #define CRYP_FLAG_MASK  0x0000001FU
00329
00330 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
00331                                                    ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
00332
00333 /** @brief  Check whether the specified CRYP interrupt is set or not.
00334   * @param  __HANDLE__: specifies the CRYP handle.
00335   * @param  __INTERRUPT__: specifies the interrupt to check.
00336   *         This parameter can be one of the following values for CRYP:
00337   *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
00338   *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
00339   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00340   */
00341
00342 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
00343
00344 /**
00345   * @brief  Enable the CRYP interrupt.
00346   * @param  __HANDLE__: specifies the CRYP handle.
00347   * @param  __INTERRUPT__: CRYP Interrupt.
00348   *         This parameter can be one of the following values for CRYP:
00349   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00350   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00351   * @retval None
00352   */
00353
00354 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
00355
00356 /**
00357   * @brief  Disable the CRYP interrupt.
00358   * @param  __HANDLE__: specifies the CRYP handle.
00359   * @param  __INTERRUPT__: CRYP Interrupt.
00360   *         This parameter can be one of the following values for CRYP:
00361   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00362   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00363   * @retval None
00364   */
00365
00366 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
00367
00368 /**
00369   * @}
00370   */
00371
00372 /* Include CRYP HAL Extended module */
00373 #include "stm32h7xx_hal_cryp_ex.h"
00374
00375 /* Exported functions --------------------------------------------------------*/
00376 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00377   * @{
00378   */
00379
00380 /** @addtogroup CRYP_Exported_Functions_Group1
00381   * @{
00382   */
00383 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00384 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00385 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00386 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00387 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00388 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00389 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00390 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
00391                                             pCRYP_CallbackTypeDef pCallback);
00392 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
00393 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00394 /**
00395   * @}
00396   */
00397
00398 /** @addtogroup CRYP_Exported_Functions_Group2
00399   * @{
00400   */
00401
00402 /* encryption/decryption ***********************************/
00403 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
00404                                    uint32_t Timeout);
00405 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
00406                                    uint32_t Timeout);
00407 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00408 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00409 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00410 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00411
00412 /**
00413   * @}
00414   */
00415
00416
00417 /** @addtogroup CRYP_Exported_Functions_Group3
00418   * @{
00419   */
00420 /* Interrupt Handler functions  **********************************************/
00421 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00422 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00423 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00424 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00425 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00426 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00427
00428 /**
00429   * @}
00430   */
00431
00432 /**
00433   * @}
00434   */
00435
00436 /* Private macros --------------------------------------------------------*/
00437 /** @defgroup CRYP_Private_Macros   CRYP Private Macros
00438   * @{
00439   */
00440
00441 /** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
00442   * @{
00443   */
00444
00445 #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB)   || \
00446                                       ((ALGORITHM)  == CRYP_DES_CBC)   || \
00447                                       ((ALGORITHM)  == CRYP_TDES_ECB)  || \
00448                                       ((ALGORITHM)  == CRYP_TDES_CBC)  || \
00449                                       ((ALGORITHM)  == CRYP_AES_ECB)   || \
00450                                       ((ALGORITHM)  == CRYP_AES_CBC)   || \
00451                                       ((ALGORITHM)  == CRYP_AES_CTR)   || \
00452                                       ((ALGORITHM)  == CRYP_AES_GCM)   || \
00453                                       ((ALGORITHM)  == CRYP_AES_CCM))
00454
00455 #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
00456                                  ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
00457                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
00458
00459 #define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \
00460                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
00461                                    ((DATATYPE) == CRYP_DATATYPE_8B) || \
00462                                    ((DATATYPE) == CRYP_DATATYPE_1B))
00463
00464 /**
00465   * @}
00466   */
00467
00468 /**
00469   * @}
00470   */
00471
00472
00473 /* Private constants ---------------------------------------------------------*/
00474 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00475   * @{
00476   */
00477
00478 /**
00479   * @}
00480   */
00481 /* Private defines -----------------------------------------------------------*/
00482 /** @defgroup CRYP_Private_Defines CRYP Private Defines
00483   * @{
00484   */
00485
00486 /**
00487   * @}
00488   */
00489
00490 /* Private variables ---------------------------------------------------------*/
00491 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00492   * @{
00493   */
00494
00495 /**
00496   * @}
00497   */
00498 /* Private functions prototypes ----------------------------------------------*/
00499 /** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
00500   * @{
00501   */
00502
00503 /**
00504   * @}
00505   */
00506
00507 /* Private functions ---------------------------------------------------------*/
00508 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00509   * @{
00510   */
00511
00512 /**
00513   * @}
00514   */
00515
00516
00517 /**
00518   * @}
00519   */
00520
00521
00522 #endif /* CRYP */
00523 /**
00524   * @}
00525   */
00526
00527 #ifdef __cplusplus
00528 }
00529 #endif
00530
00531 #endif /* STM32H7xx_HAL_CRYP_H */
00532
00533 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp_ex.c Source File

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stm32h7xx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRYP HAL module driver
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of CRYP extension peripheral:
00008   *           + Extended AES processing functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
00016     Encryption/Decryption to get the authentication messages.
00017
00018   @endverbatim
00019   ******************************************************************************
00020   * @attention
00021   *
00022   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00023   * All rights reserved.</center></h2>
00024   *
00025   * This software component is licensed by ST under BSD 3-Clause license,
00026   * the "License"; You may not use this file except in compliance with the
00027   * License. You may obtain a copy of the License at:
00028   *                        opensource.org/licenses/BSD-3-Clause
00029   *
00030   ******************************************************************************
00031   */
00032
00033 /* Includes ------------------------------------------------------------------*/
00034 #include "stm32h7xx_hal.h"
00035
00036 /** @addtogroup STM32H7xx_HAL_Driver
00037   * @{
00038   */
00039 #if defined (CRYP)
00040 /** @defgroup CRYPEx CRYPEx
00041   * @brief CRYP Extension HAL module driver.
00042   * @{
00043   */
00044
00045 #ifdef HAL_CRYP_MODULE_ENABLED
00046
00047 /* Private typedef -----------------------------------------------------------*/
00048 /* Private define ------------------------------------------------------------*/
00049 /** @addtogroup CRYPEx_Private_Defines
00050   * @{
00051   */
00052
00053 #define CRYP_PHASE_INIT                 0x00000000U
00054 #define CRYP_PHASE_HEADER               CRYP_CR_GCM_CCMPH_0
00055 #define CRYP_PHASE_PAYLOAD              CRYP_CR_GCM_CCMPH_1
00056 #define CRYP_PHASE_FINAL                CRYP_CR_GCM_CCMPH
00057
00058 #define CRYP_OPERATINGMODE_ENCRYPT      0x00000000U
00059 #define CRYP_OPERATINGMODE_DECRYPT      CRYP_CR_ALGODIR
00060
00061 #define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
00062 #define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
00063
00064 /*  CTR0 information to use in CCM algorithm */
00065 #define CRYP_CCM_CTR0_0            0x07FFFFFFU
00066 #define CRYP_CCM_CTR0_3            0xFFFFFF00U
00067
00068 /**
00069   * @}
00070   */
00071
00072 /* Private macro -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075
00076
00077
00078 /* Exported functions---------------------------------------------------------*/
00079 /** @addtogroup CRYPEx_Exported_Functions
00080   * @{
00081   */
00082
00083 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00084   *  @brief    CRYPEx Extended processing functions.
00085   *
00086 @verbatim
00087   ==============================================================================
00088               ##### Extended AES processing functions #####
00089   ==============================================================================
00090     [..]  This section provides functions allowing to generate the authentication
00091           TAG in Polling mode
00092       (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
00093       (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
00094          they should be used after Encrypt/Decrypt operation.
00095
00096 @endverbatim
00097   * @{
00098   */
00099
00100
00101 /**
00102   * @brief  generate the GCM authentication TAG.
00103   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00104   *         the configuration information for CRYP module
00105   * @param  AuthTag: Pointer to the authentication buffer
00106   * @param  Timeout: Timeout duration
00107   * @retval HAL status
00108   */
00109 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00110 {
00111   uint32_t tickstart;
00112   uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
00113   uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
00114   uint32_t tagaddr = (uint32_t)AuthTag;
00115
00116   if (hcryp->State == HAL_CRYP_STATE_READY)
00117   {
00118     /* Process locked */
00119     __HAL_LOCK(hcryp);
00120
00121     /* Change the CRYP peripheral state */
00122     hcryp->State = HAL_CRYP_STATE_BUSY;
00123
00124     /* Check if initialization phase has already been performed */
00125     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00126     {
00127       /* Change the CRYP phase */
00128       hcryp->Phase = CRYPEx_PHASE_FINAL;
00129     }
00130     else /* Initialization phase has not been performed*/
00131     {
00132       /* Disable the Peripheral */
00133       __HAL_CRYP_DISABLE(hcryp);
00134
00135       /* Sequence error code field */
00136       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00137
00138       /* Change the CRYP peripheral state */
00139       hcryp->State = HAL_CRYP_STATE_READY;
00140
00141       /* Process unlocked */
00142       __HAL_UNLOCK(hcryp);
00143       return HAL_ERROR;
00144     }
00145
00146     /* Disable CRYP to start the final phase */
00147     __HAL_CRYP_DISABLE(hcryp);
00148
00149     /* Select final phase */
00150     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
00151
00152     /*ALGODIR bit must be set to ‘0’.*/
00153     hcryp->Instance->CR &=  ~CRYP_CR_ALGODIR;
00154
00155     /* Enable the CRYP peripheral */
00156     __HAL_CRYP_ENABLE(hcryp);
00157
00158     /* Write the number of bits in header (64 bits) followed by the number of bits
00159     in the payload */
00160 #if !defined (CRYP_VER_2_2)
00161     /* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
00162     if (hcryp->Version >= REV_ID_B)
00163 #endif /*End of not defined CRYP_VER_2_2*/
00164     {
00165       hcryp->Instance->DIN = 0U;
00166       hcryp->Instance->DIN = (uint32_t)(headerlength);
00167       hcryp->Instance->DIN = 0U;
00168       hcryp->Instance->DIN = (uint32_t)(inputlength);
00169     }
00170 #if !defined (CRYP_VER_2_2)
00171     else/* data has to be swapped according to the DATATYPE */
00172     {
00173       if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
00174       {
00175         hcryp->Instance->DIN = 0U;
00176         hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
00177         hcryp->Instance->DIN = 0U;
00178         hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
00179       }
00180       else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
00181       {
00182         hcryp->Instance->DIN = 0U;
00183         hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
00184         hcryp->Instance->DIN = 0U;
00185         hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
00186       }
00187       else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
00188       {
00189         hcryp->Instance->DIN = 0U;
00190         hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
00191         hcryp->Instance->DIN = 0U;
00192         hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
00193       }
00194       else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
00195       {
00196         hcryp->Instance->DIN = 0U;
00197         hcryp->Instance->DIN = (uint32_t)(headerlength);
00198         hcryp->Instance->DIN = 0U;
00199         hcryp->Instance->DIN = (uint32_t)(inputlength);
00200       }
00201       else
00202       {
00203         /* Nothing to do */
00204       }
00205     }
00206 #endif /*End of not defined CRYP_VER_2_2*/
00207     /* Wait for OFNE flag to be raised */
00208     tickstart = HAL_GetTick();
00209     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00210     {
00211       /* Check for the Timeout */
00212       if (Timeout != HAL_MAX_DELAY)
00213       {
00214         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00215         {
00216           /* Disable the CRYP Peripheral Clock */
00217           __HAL_CRYP_DISABLE(hcryp);
00218
00219           /* Change state */
00220           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00221           hcryp->State = HAL_CRYP_STATE_READY;
00222
00223           /* Process unlocked */
00224           __HAL_UNLOCK(hcryp);
00225           return HAL_ERROR;
00226         }
00227       }
00228     }
00229
00230     /* Read the authentication TAG in the output FIFO */
00231     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00232     tagaddr += 4U;
00233     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00234     tagaddr += 4U;
00235     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00236     tagaddr += 4U;
00237     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00238
00239     /* Disable the peripheral */
00240     __HAL_CRYP_DISABLE(hcryp);
00241
00242     /* Change the CRYP peripheral state */
00243     hcryp->State = HAL_CRYP_STATE_READY;
00244
00245     /* Process unlocked */
00246     __HAL_UNLOCK(hcryp);
00247   }
00248   else
00249   {
00250     /* Busy error code field */
00251     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00252     return HAL_ERROR;
00253   }
00254   /* Return function status */
00255   return HAL_OK;
00256 }
00257
00258 /**
00259   * @brief  AES CCM Authentication TAG generation.
00260   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00261   *         the configuration information for CRYP module
00262   * @param  AuthTag: Pointer to the authentication buffer
00263   * @param  Timeout: Timeout duration
00264   * @retval HAL status
00265   */
00266 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00267 {
00268   uint32_t tagaddr = (uint32_t)AuthTag;
00269   uint32_t ctr0 [4] = {0};
00270   uint32_t ctr0addr = (uint32_t)ctr0;
00271   uint32_t tickstart;
00272
00273   if (hcryp->State == HAL_CRYP_STATE_READY)
00274   {
00275     /* Process locked */
00276     __HAL_LOCK(hcryp);
00277
00278     /* Change the CRYP peripheral state */
00279     hcryp->State = HAL_CRYP_STATE_BUSY;
00280
00281     /* Check if initialization phase has already been performed */
00282     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00283     {
00284       /* Change the CRYP phase */
00285       hcryp->Phase = CRYPEx_PHASE_FINAL;
00286     }
00287     else /* Initialization phase has not been performed*/
00288     {
00289       /* Disable the peripheral */
00290       __HAL_CRYP_DISABLE(hcryp);
00291
00292       /* Sequence error code field */
00293       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00294
00295       /* Change the CRYP peripheral state */
00296       hcryp->State = HAL_CRYP_STATE_READY;
00297
00298       /* Process unlocked */
00299       __HAL_UNLOCK(hcryp);
00300       return HAL_ERROR;
00301     }
00302
00303     /* Disable CRYP to start the final phase */
00304     __HAL_CRYP_DISABLE(hcryp);
00305
00306     /* Select final phase & ALGODIR bit must be set to ‘0’. */
00307     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
00308
00309     /* Enable the CRYP peripheral */
00310     __HAL_CRYP_ENABLE(hcryp);
00311
00312     /* Write the counter block in the IN FIFO, CTR0 information from B0
00313     data has to be swapped according to the DATATYPE*/
00314     ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
00315     ctr0[1] = hcryp->Init.B0[1];
00316     ctr0[2] = hcryp->Init.B0[2];
00317     ctr0[3] = hcryp->Init.B0[3] &  CRYP_CCM_CTR0_3;
00318
00319 #if !defined (CRYP_VER_2_2)
00320     /*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
00321     if (hcryp->Version >= REV_ID_B)
00322 #endif /*End of not defined CRYP_VER_2_2*/
00323     {
00324       hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00325       ctr0addr += 4U;
00326       hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00327       ctr0addr += 4U;
00328       hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00329       ctr0addr += 4U;
00330       hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00331     }
00332 #if !defined (CRYP_VER_2_2)
00333     else /* data has to be swapped according to the DATATYPE */
00334     {
00335       if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
00336       {
00337         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
00338         ctr0addr += 4U;
00339         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
00340         ctr0addr += 4U;
00341         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
00342         ctr0addr += 4U;
00343         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
00344       }
00345       else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
00346       {
00347         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
00348         ctr0addr += 4U;
00349         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
00350         ctr0addr += 4U;
00351         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
00352         ctr0addr += 4U;
00353         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
00354       }
00355       else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
00356       {
00357         hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
00358         ctr0addr += 4U;
00359         hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
00360         ctr0addr += 4U;
00361         hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
00362         ctr0addr += 4U;
00363         hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
00364       }
00365       else
00366       {
00367         hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00368         ctr0addr += 4U;
00369         hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00370         ctr0addr += 4U;
00371         hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00372         ctr0addr += 4U;
00373         hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
00374       }
00375     }
00376 #endif /*End of not defined CRYP_VER_2_2*/
00377     /* Wait for OFNE flag to be raised */
00378     tickstart = HAL_GetTick();
00379     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00380     {
00381       /* Check for the Timeout */
00382       if (Timeout != HAL_MAX_DELAY)
00383       {
00384         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00385         {
00386           /* Disable the CRYP peripheral Clock */
00387           __HAL_CRYP_DISABLE(hcryp);
00388
00389           /* Change state */
00390           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00391           hcryp->State = HAL_CRYP_STATE_READY;
00392
00393           /* Process unlocked */
00394           __HAL_UNLOCK(hcryp);
00395           return HAL_ERROR;
00396         }
00397       }
00398     }
00399
00400     /* Read the Auth TAG in the IN FIFO */
00401     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00402     tagaddr += 4U;
00403     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00404     tagaddr += 4U;
00405     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00406     tagaddr += 4U;
00407     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
00408
00409     /* Change the CRYP peripheral state */
00410     hcryp->State = HAL_CRYP_STATE_READY;
00411
00412     /* Process unlocked */
00413     __HAL_UNLOCK(hcryp);
00414
00415     /* Disable CRYP  */
00416     __HAL_CRYP_DISABLE(hcryp);
00417   }
00418   else
00419   {
00420     /* Busy error code field */
00421     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00422     return HAL_ERROR;
00423   }
00424   /* Return function status */
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @}
00430   */
00431
00432
00433 #endif /* HAL_CRYP_MODULE_ENABLED */
00434
00435 /**
00436   * @}
00437   */
00438 #endif /* CRYP */
00439 /**
00440   * @}
00441   */
00442
00443 /**
00444   * @}
00445   */
00446 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_cryp_ex.h Source File

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stm32h7xx_hal_cryp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYP HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_CRYP_EX_H
00022 #define STM32H7xx_HAL_CRYP_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined (CRYP)
00035 /** @addtogroup CRYPEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /* Private variables ---------------------------------------------------------*/
00052 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00053   * @{
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00062   * @{
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Private macros ------------------------------------------------------------*/
00070 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @}
00076  */
00077
00078 /* Private functions ---------------------------------------------------------*/
00079 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00080   * @{
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Exported functions --------------------------------------------------------*/
00088 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00089   * @{
00090   */
00091
00092 /** @addtogroup CRYPEx_Exported_Functions_Group1
00093   * @{
00094   */
00095 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00096 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00097
00098
00099 /**
00100   * @}
00101   */
00102
00103
00104 /**
00105   * @}
00106   */
00107
00108 /**
00109   * @}
00110   */
00111 #endif /* CRYP */
00112 /**
00113   * @}
00114   */
00115
00116
00117 #ifdef __cplusplus
00118 }
00119 #endif
00120
00121 #endif /* STM32H7xx_HAL_CRYP_EX_H */
00122
00123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac.c Source File

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stm32h7xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   *
00014   @verbatim
00015   ==============================================================================
00016                       ##### DAC Peripheral features #####
00017   ==============================================================================
00018     [..]
00019       *** DAC Channels ***
00020       ====================
00021     [..]
00022     STM32H7 devices integrate two 12-bit Digital Analog Converters
00023
00024     The 2 converters (i.e. channel1 & channel2)
00025     can be used independently or simultaneously (dual mode):
00026       (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
00027           peripherals (ex. OPAMPs, comparators).
00028       (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
00029           peripherals (ex. OPAMPs, comparators).
00030
00031       *** DAC Triggers ***
00032       ====================
00033     [..]
00034     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00035     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00036     [..]
00037     Digital to Analog conversion can be triggered by:
00038       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00039           The used pin (GPIOx_PIN_9) must be configured in input mode.
00040
00041       (#) Timers TRGO: TIM1, TIM2, TIM4, TIM5, TIM6, TIM7, TIM8, TIM15, TIM23 and TIM24
00042           (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
00043
00044       (#) Low Power Timers TRGO: LPTIM1, LPTIM2 and LPTIM3
00045           (DAC_TRIGGER_LPTIM1_OUT, DAC_TRIGGER_LPTIM2_OUT)
00046
00047       (#) High Resolution Timer TRGO: HRTIM1
00048           (DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2)
00049
00050       (#) Software using DAC_TRIGGER_SOFTWARE
00051       *** DAC Buffer mode feature ***
00052       ===============================
00053       [..]
00054       Each DAC channel integrates an output buffer that can be used to
00055       reduce the output impedance, and to drive external loads directly
00056       without having to add an external operational amplifier.
00057       To enable, the output buffer use
00058       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00059       [..]
00060       (@) Refer to the device datasheet for more details about output
00061           impedance value with and without output buffer.
00062
00063       *** DAC connect feature ***
00064       ===============================
00065       [..]
00066       Each DAC channel can be connected internally.
00067       To connect, use
00068       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
00069       or
00070       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
00071
00072       *** GPIO configurations guidelines ***
00073       =====================
00074       [..]
00075       When a DAC channel is used (ex channel1 on PA4) and the other is not
00076       (ex channel2 on PA5 is configured in Analog and disabled).
00077       Channel1 may disturb channel2 as coupling effect.
00078       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00079       Coupling on adjacent channel could be avoided as follows:
00080       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00081       PA5 is configured in ANALOG just before it is turned on.
00082
00083       *** DAC Sample and Hold feature ***
00084       ========================
00085       [..]
00086       For each converter, 2 modes are supported: normal mode and
00087       "sample and hold" mode (i.e. low power mode).
00088       In the sample and hold mode, the DAC core converts data, then holds the
00089       converted voltage on a capacitor. When not converting, the DAC cores and
00090       buffer are completely turned off between samples and the DAC output is
00091       tri-stated, therefore  reducing the overall power consumption. A new
00092       stabilization period is needed before each new conversion.
00093
00094       The sample and hold allow setting internal or external voltage @
00095       low power consumption cost (output value can be at any given rate either
00096       by CPU or DMA).
00097
00098       The Sample and hold block and registers uses either LSI & run in
00099       several power modes: run mode, sleep mode, low power run, low power sleep
00100       mode & stop1 mode.
00101
00102       Low power stop1 mode allows only static conversion.
00103
00104       To enable Sample and Hold mode
00105       Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
00106       RCC_LSI_ON parameters.
00107
00108       Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
00109          & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
00110            DAC_HoldTime & DAC_RefreshTime;
00111
00112        *** DAC calibration feature ***
00113        ===================================
00114       [..]
00115        (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
00116        (++) Calibration aims at correcting some offset of output buffer.
00117        (++) The DAC uses either factory calibration settings OR user defined
00118            calibration (trimming) settings (i.e. trimming mode).
00119        (++) The user defined settings can be figured out using self calibration
00120            handled by HAL_DACEx_SelfCalibrate.
00121        (++) HAL_DACEx_SelfCalibrate:
00122        (+++) Runs automatically the calibration.
00123        (+++) Enables the user trimming mode
00124        (+++) Updates a structure with trimming values with fresh calibration
00125             results.
00126             The user may store the calibration results for larger
00127             (ex monitoring the trimming as a function of temperature
00128             for instance)
00129
00130        *** DAC wave generation feature ***
00131        ===================================
00132        [..]
00133        Both DAC channels can be used to generate
00134          (#) Noise wave
00135          (#) Triangle wave
00136
00137        *** DAC data format ***
00138        =======================
00139        [..]
00140        The DAC data format can be:
00141          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00142          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00143          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00144
00145        *** DAC data value to voltage correspondence ***
00146        ================================================
00147        [..]
00148        The analog output voltage on each DAC channel pin is determined
00149        by the following equation:
00150        [..]
00151        DAC_OUTx = VREF+ * DOR / 4095
00152        (+) with  DOR is the Data Output Register
00153        [..]
00154           VREF+ is the input voltage reference (refer to the device datasheet)
00155        [..]
00156         e.g. To set DAC_OUT1 to 0.7V, use
00157        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00158
00159        *** DMA requests ***
00160        =====================
00161        [..]
00162        A DMA request can be generated when an external trigger (but not a software trigger)
00163        occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
00164        DMA requests are mapped as following:
00165       (#) DAC channel1: mapped on DMA_REQUEST_DAC1_CH1
00166       (#) DAC channel2: mapped on DMA_REQUEST_DAC1_CH2
00167
00168      [..]
00169     (@) For Dual mode and specific signal (Triangle and noise) generation please
00170         refer to Extended Features Driver description
00171
00172                       ##### How to use this driver #####
00173   ==============================================================================
00174     [..]
00175       (+) DAC APB clock must be enabled to get write access to DAC
00176           registers using HAL_DAC_Init()
00177       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00178       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00179       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
00180
00181      *** Calibration mode IO operation ***
00182      ======================================
00183      [..]
00184        (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
00185        (+) Run the calibration using HAL_DACEx_SelfCalibrate()
00186        (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
00187
00188      *** Polling mode IO operation ***
00189      =================================
00190      [..]
00191        (+) Start the DAC peripheral using HAL_DAC_Start()
00192        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00193        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00194
00195      *** DMA mode IO operation ***
00196      ==============================
00197      [..]
00198        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00199            of data to be transferred at each end of conversion
00200            First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
00201        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00202            function is executed and user can add his own code by customization of function pointer
00203            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00204        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00205            function is executed and user can add his own code by customization of function pointer
00206            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00207        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00208             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00209        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00210            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
00211            function is executed and user can add his own code by customization of function pointer
00212            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
00213            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
00214        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00215
00216     *** Callback registration ***
00217     =============================================
00218     [..]
00219       The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
00220       allows the user to configure dynamically the driver callbacks.
00221
00222     Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
00223       it allows to register following callbacks:
00224       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00225       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00226       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00227       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00228       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00229       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00230       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00231       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00232       (+) MspInitCallback         : DAC MspInit.
00233       (+) MspDeInitCallback       : DAC MspdeInit.
00234       This function takes as parameters the HAL peripheral handle, the Callback ID
00235       and a pointer to the user callback function.
00236
00237     Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
00238       weak (surcharged) function. It allows to reset following callbacks:
00239       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00240       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00241       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00242       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00243       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00244       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00245       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00246       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00247       (+) MspInitCallback         : DAC MspInit.
00248       (+) MspDeInitCallback       : DAC MspdeInit.
00249       (+) All Callbacks
00250       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00251
00252       By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
00253       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00254       Exception done for MspInit and MspDeInit callbacks that are respectively
00255       reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
00256       and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
00257       If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
00258       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00259
00260       Callbacks can be registered/unregistered in READY state only.
00261       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00262       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00263       during the Init/DeInit.
00264       In that case first register the MspInit/MspDeInit user callbacks
00265       using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
00266       or @ref HAL_DAC_Init function.
00267
00268       When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
00269       not defined, the callback registering feature is not available
00270       and weak (surcharged) callbacks are used.
00271
00272      *** DAC HAL driver macros list ***
00273      =============================================
00274      [..]
00275        Below the list of most used macros in DAC HAL driver.
00276
00277       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00278       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00279       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00280       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00281
00282      [..]
00283       (@) You can refer to the DAC HAL driver header file for more useful macros
00284
00285 @endverbatim
00286   ******************************************************************************
00287   * @attention
00288   *
00289   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00290   * All rights reserved.</center></h2>
00291   *
00292   * This software component is licensed by ST under BSD 3-Clause license,
00293   * the "License"; You may not use this file except in compliance with the
00294   * License. You may obtain a copy of the License at:
00295   *                        opensource.org/licenses/BSD-3-Clause
00296   *
00297   ******************************************************************************
00298   */
00299
00300 /* Includes ------------------------------------------------------------------*/
00301 #include "stm32h7xx_hal.h"
00302
00303 /** @addtogroup STM32H7xx_HAL_Driver
00304   * @{
00305   */
00306
00307 #ifdef HAL_DAC_MODULE_ENABLED
00308 #if defined(DAC1) || defined(DAC2)
00309
00310 /** @defgroup DAC DAC
00311   * @brief DAC driver modules
00312   * @{
00313   */
00314
00315 /* Private typedef -----------------------------------------------------------*/
00316 /* Private define ------------------------------------------------------------*/
00317 /* Private constants ---------------------------------------------------------*/
00318 /** @addtogroup DAC_Private_Constants DAC Private Constants
00319   * @{
00320   */
00321 #define TIMEOUT_DAC_CALIBCONFIG        1U         /* 1   ms        */
00322
00323 /**
00324   * @}
00325   */
00326
00327 /* Private macro -------------------------------------------------------------*/
00328 /* Private variables ---------------------------------------------------------*/
00329 /* Private function prototypes -----------------------------------------------*/
00330 /* Exported functions -------------------------------------------------------*/
00331
00332 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00333   * @{
00334   */
00335
00336 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00337   *  @brief    Initialization and Configuration functions
00338   *
00339 @verbatim
00340   ==============================================================================
00341               ##### Initialization and de-initialization functions #####
00342   ==============================================================================
00343     [..]  This section provides functions allowing to:
00344       (+) Initialize and configure the DAC.
00345       (+) De-initialize the DAC.
00346
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Initialize the DAC peripheral according to the specified parameters
00353   *         in the DAC_InitStruct and initialize the associated handle.
00354   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00355   *         the configuration information for the specified DAC.
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
00359 {
00360   /* Check DAC handle */
00361   if (hdac == NULL)
00362   {
00363     return HAL_ERROR;
00364   }
00365   /* Check the parameters */
00366   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00367
00368   if (hdac->State == HAL_DAC_STATE_RESET)
00369   {
00370 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00371     /* Init the DAC Callback settings */
00372     hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
00373     hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
00374     hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
00375     hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
00376
00377     hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
00378     hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
00379     hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
00380     hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
00381
00382     if (hdac->MspInitCallback == NULL)
00383     {
00384       hdac->MspInitCallback             = HAL_DAC_MspInit;
00385     }
00386 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00387
00388     /* Allocate lock resource and initialize it */
00389     hdac->Lock = HAL_UNLOCKED;
00390
00391 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00392     /* Init the low level hardware */
00393     hdac->MspInitCallback(hdac);
00394 #else
00395     /* Init the low level hardware */
00396     HAL_DAC_MspInit(hdac);
00397 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00398   }
00399
00400   /* Initialize the DAC state*/
00401   hdac->State = HAL_DAC_STATE_BUSY;
00402
00403   /* Set DAC error code to none */
00404   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00405
00406   /* Initialize the DAC state*/
00407   hdac->State = HAL_DAC_STATE_READY;
00408
00409   /* Return function status */
00410   return HAL_OK;
00411 }
00412
00413 /**
00414   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00415   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00416   *         the configuration information for the specified DAC.
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
00420 {
00421   /* Check DAC handle */
00422   if (hdac == NULL)
00423   {
00424     return HAL_ERROR;
00425   }
00426
00427   /* Check the parameters */
00428   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00429
00430   /* Change DAC state */
00431   hdac->State = HAL_DAC_STATE_BUSY;
00432
00433 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00434   if (hdac->MspDeInitCallback == NULL)
00435   {
00436     hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
00437   }
00438   /* DeInit the low level hardware */
00439   hdac->MspDeInitCallback(hdac);
00440 #else
00441   /* DeInit the low level hardware */
00442   HAL_DAC_MspDeInit(hdac);
00443 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00444
00445   /* Set DAC error code to none */
00446   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00447
00448   /* Change DAC state */
00449   hdac->State = HAL_DAC_STATE_RESET;
00450
00451   /* Release Lock */
00452   __HAL_UNLOCK(hdac);
00453
00454   /* Return function status */
00455   return HAL_OK;
00456 }
00457
00458 /**
00459   * @brief  Initialize the DAC MSP.
00460   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00461   *         the configuration information for the specified DAC.
00462   * @retval None
00463   */
00464 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
00465 {
00466   /* Prevent unused argument(s) compilation warning */
00467   UNUSED(hdac);
00468
00469   /* NOTE : This function should not be modified, when the callback is needed,
00470             the HAL_DAC_MspInit could be implemented in the user file
00471    */
00472 }
00473
00474 /**
00475   * @brief  DeInitialize the DAC MSP.
00476   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00477   *         the configuration information for the specified DAC.
00478   * @retval None
00479   */
00480 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
00481 {
00482   /* Prevent unused argument(s) compilation warning */
00483   UNUSED(hdac);
00484
00485   /* NOTE : This function should not be modified, when the callback is needed,
00486             the HAL_DAC_MspDeInit could be implemented in the user file
00487    */
00488 }
00489
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00495   *  @brief    IO operation functions
00496   *
00497 @verbatim
00498   ==============================================================================
00499              ##### IO operation functions #####
00500   ==============================================================================
00501     [..]  This section provides functions allowing to:
00502       (+) Start conversion.
00503       (+) Stop conversion.
00504       (+) Start conversion and enable DMA transfer.
00505       (+) Stop conversion and disable DMA transfer.
00506       (+) Get result of conversion.
00507
00508 @endverbatim
00509   * @{
00510   */
00511
00512 /**
00513   * @brief  Enables DAC and starts conversion of channel.
00514   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00515   *         the configuration information for the specified DAC.
00516   * @param  Channel The selected DAC channel.
00517   *          This parameter can be one of the following values:
00518   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00519   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00520   * @retval HAL status
00521   */
00522 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
00523 {
00524   /* Check the parameters */
00525   assert_param(IS_DAC_CHANNEL(Channel));
00526
00527   /* Process locked */
00528   __HAL_LOCK(hdac);
00529
00530   /* Change DAC state */
00531   hdac->State = HAL_DAC_STATE_BUSY;
00532
00533   /* Enable the Peripheral */
00534   __HAL_DAC_ENABLE(hdac, Channel);
00535
00536   if (Channel == DAC_CHANNEL_1)
00537   {
00538     /* Check if software trigger enabled */
00539     if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
00540     {
00541       /* Enable the selected DAC software conversion */
00542       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00543     }
00544   }
00545   else
00546   {
00547     /* Check if software trigger enabled */
00548     if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
00549     {
00550       /* Enable the selected DAC software conversion*/
00551       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00552     }
00553   }
00554
00555   /* Change DAC state */
00556   hdac->State = HAL_DAC_STATE_READY;
00557
00558   /* Process unlocked */
00559   __HAL_UNLOCK(hdac);
00560
00561   /* Return function status */
00562   return HAL_OK;
00563 }
00564
00565 /**
00566   * @brief  Disables DAC and stop conversion of channel.
00567   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00568   *         the configuration information for the specified DAC.
00569   * @param  Channel The selected DAC channel.
00570   *          This parameter can be one of the following values:
00571   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00572   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00573   * @retval HAL status
00574   */
00575 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
00576 {
00577   /* Check the parameters */
00578   assert_param(IS_DAC_CHANNEL(Channel));
00579
00580   /* Disable the Peripheral */
00581   __HAL_DAC_DISABLE(hdac, Channel);
00582
00583   /* Change DAC state */
00584   hdac->State = HAL_DAC_STATE_READY;
00585
00586   /* Return function status */
00587   return HAL_OK;
00588 }
00589
00590 /**
00591   * @brief  Enables DAC and starts conversion of channel.
00592   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00593   *         the configuration information for the specified DAC.
00594   * @param  Channel The selected DAC channel.
00595   *          This parameter can be one of the following values:
00596   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00597   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00598   * @param  pData The destination peripheral Buffer address.
00599   * @param  Length The length of data to be transferred from memory to DAC peripheral
00600   * @param  Alignment Specifies the data alignment for DAC channel.
00601   *          This parameter can be one of the following values:
00602   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00603   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00604   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00605   * @retval HAL status
00606   */
00607 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00608                                     uint32_t Alignment)
00609 {
00610   HAL_StatusTypeDef status;
00611   uint32_t tmpreg = 0U;
00612
00613   /* Check the parameters */
00614   assert_param(IS_DAC_CHANNEL(Channel));
00615   assert_param(IS_DAC_ALIGN(Alignment));
00616
00617   /* Process locked */
00618   __HAL_LOCK(hdac);
00619
00620   /* Change DAC state */
00621   hdac->State = HAL_DAC_STATE_BUSY;
00622
00623   if (Channel == DAC_CHANNEL_1)
00624   {
00625     /* Set the DMA transfer complete callback for channel1 */
00626     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00627
00628     /* Set the DMA half transfer complete callback for channel1 */
00629     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00630
00631     /* Set the DMA error callback for channel1 */
00632     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00633
00634     /* Enable the selected DAC channel1 DMA request */
00635     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00636
00637     /* Case of use of channel 1 */
00638     switch (Alignment)
00639     {
00640       case DAC_ALIGN_12B_R:
00641         /* Get DHR12R1 address */
00642         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00643         break;
00644       case DAC_ALIGN_12B_L:
00645         /* Get DHR12L1 address */
00646         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00647         break;
00648       case DAC_ALIGN_8B_R:
00649         /* Get DHR8R1 address */
00650         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00651         break;
00652       default:
00653         break;
00654     }
00655   }
00656   else
00657   {
00658     /* Set the DMA transfer complete callback for channel2 */
00659     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00660
00661     /* Set the DMA half transfer complete callback for channel2 */
00662     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00663
00664     /* Set the DMA error callback for channel2 */
00665     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00666
00667     /* Enable the selected DAC channel2 DMA request */
00668     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00669
00670     /* Case of use of channel 2 */
00671     switch (Alignment)
00672     {
00673       case DAC_ALIGN_12B_R:
00674         /* Get DHR12R2 address */
00675         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00676         break;
00677       case DAC_ALIGN_12B_L:
00678         /* Get DHR12L2 address */
00679         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00680         break;
00681       case DAC_ALIGN_8B_R:
00682         /* Get DHR8R2 address */
00683         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00684         break;
00685       default:
00686         break;
00687     }
00688   }
00689
00690   /* Enable the DMA Stream */
00691   if (Channel == DAC_CHANNEL_1)
00692   {
00693     /* Enable the DAC DMA underrun interrupt */
00694     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00695
00696    /* Enable the DMA Stream */
00697     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00698   }
00699   else
00700   {
00701     /* Enable the DAC DMA underrun interrupt */
00702     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00703
00704     /* Enable the DMA Stream */
00705     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00706   }
00707
00708   /* Process Unlocked */
00709   __HAL_UNLOCK(hdac);
00710
00711   if (status == HAL_OK)
00712   {
00713     /* Enable the Peripheral */
00714     __HAL_DAC_ENABLE(hdac, Channel);
00715   }
00716   else
00717   {
00718     hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00719   }
00720
00721   /* Return function status */
00722   return status;
00723 }
00724
00725 /**
00726   * @brief  Disables DAC and stop conversion of channel.
00727   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00728   *         the configuration information for the specified DAC.
00729   * @param  Channel The selected DAC channel.
00730   *          This parameter can be one of the following values:
00731   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00732   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00733   * @retval HAL status
00734   */
00735 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
00736 {
00737   HAL_StatusTypeDef status;
00738
00739   /* Check the parameters */
00740   assert_param(IS_DAC_CHANNEL(Channel));
00741
00742   /* Disable the selected DAC channel DMA request */
00743   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
00744
00745   /* Disable the Peripheral */
00746   __HAL_DAC_DISABLE(hdac, Channel);
00747
00748   /* Disable the DMA Stream */
00749
00750   /* Channel1 is used */
00751   if (Channel == DAC_CHANNEL_1)
00752   {
00753     /* Disable the DMA Stream */
00754     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00755
00756     /* Disable the DAC DMA underrun interrupt */
00757     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00758   }
00759   else /* Channel2 is used for */
00760   {
00761     /* Disable the DMA Stream */
00762     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00763
00764     /* Disable the DAC DMA underrun interrupt */
00765     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00766   }
00767
00768   /* Check if DMA Stream effectively disabled */
00769   if (status != HAL_OK)
00770   {
00771     /* Update DAC state machine to error */
00772     hdac->State = HAL_DAC_STATE_ERROR;
00773   }
00774   else
00775   {
00776     /* Change DAC state */
00777     hdac->State = HAL_DAC_STATE_READY;
00778   }
00779
00780   /* Return function status */
00781   return status;
00782 }
00783
00784 /**
00785   * @brief  Handles DAC interrupt request
00786   *         This function uses the interruption of DMA
00787   *         underrun.
00788   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00789   *         the configuration information for the specified DAC.
00790   * @retval None
00791   */
00792 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
00793 {
00794   if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00795   {
00796     /* Check underrun flag of DAC channel 1 */
00797     if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00798     {
00799       /* Change DAC state to error state */
00800       hdac->State = HAL_DAC_STATE_ERROR;
00801
00802       /* Set DAC error code to chanel1 DMA underrun error */
00803       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00804
00805       /* Clear the underrun flag */
00806       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
00807
00808       /* Disable the selected DAC channel1 DMA request */
00809       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00810
00811       /* Error callback */
00812 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00813       hdac->DMAUnderrunCallbackCh1(hdac);
00814 #else
00815       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00816 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00817     }
00818   }
00819
00820   if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00821   {
00822     /* Check underrun flag of DAC channel 2 */
00823     if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00824     {
00825       /* Change DAC state to error state */
00826       hdac->State = HAL_DAC_STATE_ERROR;
00827
00828       /* Set DAC error code to channel2 DMA underrun error */
00829       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00830
00831       /* Clear the underrun flag */
00832       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
00833
00834       /* Disable the selected DAC channel2 DMA request */
00835       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00836
00837       /* Error callback */
00838 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00839       hdac->DMAUnderrunCallbackCh2(hdac);
00840 #else
00841       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00842 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00843     }
00844   }
00845 }
00846
00847 /**
00848   * @brief  Set the specified data holding register value for DAC channel.
00849   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00850   *         the configuration information for the specified DAC.
00851   * @param  Channel The selected DAC channel.
00852   *          This parameter can be one of the following values:
00853   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00854   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00855   * @param  Alignment Specifies the data alignment.
00856   *          This parameter can be one of the following values:
00857   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00858   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00859   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00860   * @param  Data Data to be loaded in the selected data holding register.
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00864 {
00865   __IO uint32_t tmp = 0;
00866
00867   /* Check the parameters */
00868   assert_param(IS_DAC_CHANNEL(Channel));
00869   assert_param(IS_DAC_ALIGN(Alignment));
00870   assert_param(IS_DAC_DATA(Data));
00871
00872   tmp = (uint32_t)hdac->Instance;
00873   if (Channel == DAC_CHANNEL_1)
00874   {
00875     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00876   }
00877   else
00878   {
00879     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00880   }
00881
00882   /* Set the DAC channel selected data holding register */
00883   *(__IO uint32_t *) tmp = Data;
00884
00885   /* Return function status */
00886   return HAL_OK;
00887 }
00888
00889 /**
00890   * @brief  Conversion complete callback in non-blocking mode for Channel1
00891   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00892   *         the configuration information for the specified DAC.
00893   * @retval None
00894   */
00895 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
00896 {
00897   /* Prevent unused argument(s) compilation warning */
00898   UNUSED(hdac);
00899
00900   /* NOTE : This function should not be modified, when the callback is needed,
00901             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
00902    */
00903 }
00904
00905 /**
00906   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
00907   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00908   *         the configuration information for the specified DAC.
00909   * @retval None
00910   */
00911 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
00912 {
00913   /* Prevent unused argument(s) compilation warning */
00914   UNUSED(hdac);
00915
00916   /* NOTE : This function should not be modified, when the callback is needed,
00917             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00918    */
00919 }
00920
00921 /**
00922   * @brief  Error DAC callback for Channel1.
00923   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00924   *         the configuration information for the specified DAC.
00925   * @retval None
00926   */
00927 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00928 {
00929   /* Prevent unused argument(s) compilation warning */
00930   UNUSED(hdac);
00931
00932   /* NOTE : This function should not be modified, when the callback is needed,
00933             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00934    */
00935 }
00936
00937 /**
00938   * @brief  DMA underrun DAC callback for channel1.
00939   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00940   *         the configuration information for the specified DAC.
00941   * @retval None
00942   */
00943 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00944 {
00945   /* Prevent unused argument(s) compilation warning */
00946   UNUSED(hdac);
00947
00948   /* NOTE : This function should not be modified, when the callback is needed,
00949             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00950    */
00951 }
00952
00953 /**
00954   * @}
00955   */
00956
00957 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00958   *  @brief    Peripheral Control functions
00959   *
00960 @verbatim
00961   ==============================================================================
00962              ##### Peripheral Control functions #####
00963   ==============================================================================
00964     [..]  This section provides functions allowing to:
00965       (+) Configure channels.
00966       (+) Set the specified data holding register value for DAC channel.
00967
00968 @endverbatim
00969   * @{
00970   */
00971
00972 /**
00973   * @brief  Returns the last data output value of the selected DAC channel.
00974   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00975   *         the configuration information for the specified DAC.
00976   * @param  Channel The selected DAC channel.
00977   *          This parameter can be one of the following values:
00978   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00979   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00980   * @retval The selected DAC channel data output value.
00981   */
00982 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
00983 {
00984   /* Check the parameters */
00985   assert_param(IS_DAC_CHANNEL(Channel));
00986
00987   /* Returns the DAC channel data output register value */
00988   if (Channel == DAC_CHANNEL_1)
00989   {
00990     return hdac->Instance->DOR1;
00991   }
00992   else
00993   {
00994     return hdac->Instance->DOR2;
00995   }
00996 }
00997
00998 /**
00999   * @brief  Configures the selected DAC channel.
01000   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01001   *         the configuration information for the specified DAC.
01002   * @param  sConfig DAC configuration structure.
01003   * @param  Channel The selected DAC channel.
01004   *          This parameter can be one of the following values:
01005   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
01006   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
01007   * @retval HAL status
01008   */
01009 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
01010 {
01011   uint32_t tmpreg1;
01012   uint32_t tmpreg2;
01013   uint32_t tickstart;
01014   uint32_t connectOnChip;
01015
01016   /* Check the DAC parameters */
01017   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
01018   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
01019   assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
01020   assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
01021   if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
01022   {
01023     assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
01024   }
01025   assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
01026   if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
01027   {
01028     assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
01029     assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
01030     assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
01031   }
01032   assert_param(IS_DAC_CHANNEL(Channel));
01033
01034   /* Process locked */
01035   __HAL_LOCK(hdac);
01036
01037   /* Change DAC state */
01038   hdac->State = HAL_DAC_STATE_BUSY;
01039
01040   /* Sample and hold configuration */
01041   if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
01042   {
01043     /* Get timeout */
01044     tickstart = HAL_GetTick();
01045
01046     if (Channel == DAC_CHANNEL_1)
01047     {
01048       /* SHSR1 can be written when BWST1 is cleared */
01049       while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
01050       {
01051         /* Check for the Timeout */
01052         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01053         {
01054           /* Update error code */
01055           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01056
01057           /* Change the DMA state */
01058           hdac->State = HAL_DAC_STATE_TIMEOUT;
01059
01060           return HAL_TIMEOUT;
01061         }
01062       }
01063       HAL_Delay(1);
01064       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01065     }
01066     else /* Channel 2 */
01067     {
01068       /* SHSR2 can be written when BWST2 is cleared */
01069       while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
01070       {
01071         /* Check for the Timeout */
01072         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01073         {
01074           /* Update error code */
01075           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01076
01077           /* Change the DMA state */
01078           hdac->State = HAL_DAC_STATE_TIMEOUT;
01079
01080           return HAL_TIMEOUT;
01081         }
01082       }
01083       HAL_Delay(1U);
01084       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01085     }
01086
01087     /* HoldTime */
01088     MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
01089     /* RefreshTime */
01090     MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
01091   }
01092
01093   if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
01094     /* USER TRIMMING */
01095   {
01096     /* Get the DAC CCR value */
01097     tmpreg1 = hdac->Instance->CCR;
01098     /* Clear trimming value */
01099     tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
01100     /* Configure for the selected trimming offset */
01101     tmpreg2 = sConfig->DAC_TrimmingValue;
01102     /* Calculate CCR register value depending on DAC_Channel */
01103     tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01104     /* Write to DAC CCR */
01105     hdac->Instance->CCR = tmpreg1;
01106   }
01107   /* else factory trimming is used (factory setting are available at reset)*/
01108   /* SW Nothing has nothing to do */
01109
01110   /* Get the DAC MCR value */
01111   tmpreg1 = hdac->Instance->MCR;
01112   /* Clear DAC_MCR_MODEx bits */
01113   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
01114   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
01115   if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL)
01116   {
01117     connectOnChip = 0x00000000UL;
01118   }
01119   else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL)
01120   {
01121     connectOnChip = DAC_MCR_MODE1_0;
01122   }
01123   else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */
01124   {
01125     if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
01126     {
01127       connectOnChip = DAC_MCR_MODE1_0;
01128     }
01129     else
01130     {
01131       connectOnChip = 0x00000000UL;
01132     }
01133   }
01134   tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
01135   /* Calculate MCR register value depending on DAC_Channel */
01136   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01137   /* Write to DAC MCR */
01138   hdac->Instance->MCR = tmpreg1;
01139
01140   /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
01141   CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
01142
01143   /* Get the DAC CR value */
01144   tmpreg1 = hdac->Instance->CR;
01145   /* Clear TENx, TSELx, WAVEx and MAMPx bits */
01146   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
01147   /* Configure for the selected DAC channel: trigger */
01148   /* Set TSELx and TENx bits according to DAC_Trigger value */
01149   tmpreg2 = sConfig->DAC_Trigger;
01150   /* Calculate CR register value depending on DAC_Channel */
01151   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01152   /* Write to DAC CR */
01153   hdac->Instance->CR = tmpreg1;
01154   /* Disable wave generation */
01155   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
01156
01157   /* Change DAC state */
01158   hdac->State = HAL_DAC_STATE_READY;
01159
01160   /* Process unlocked */
01161   __HAL_UNLOCK(hdac);
01162
01163   /* Return function status */
01164   return HAL_OK;
01165 }
01166
01167 /**
01168   * @}
01169   */
01170
01171 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
01172   *  @brief   Peripheral State and Errors functions
01173   *
01174 @verbatim
01175   ==============================================================================
01176             ##### Peripheral State and Errors functions #####
01177   ==============================================================================
01178     [..]
01179     This subsection provides functions allowing to
01180       (+) Check the DAC state.
01181       (+) Check the DAC Errors.
01182
01183 @endverbatim
01184   * @{
01185   */
01186
01187 /**
01188   * @brief  return the DAC handle state
01189   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01190   *         the configuration information for the specified DAC.
01191   * @retval HAL state
01192   */
01193 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
01194 {
01195   /* Return DAC handle state */
01196   return hdac->State;
01197 }
01198
01199
01200 /**
01201   * @brief  Return the DAC error code
01202   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01203   *         the configuration information for the specified DAC.
01204   * @retval DAC Error Code
01205   */
01206 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
01207 {
01208   return hdac->ErrorCode;
01209 }
01210
01211 /**
01212   * @}
01213   */
01214
01215 /**
01216   * @}
01217   */
01218
01219 /** @addtogroup DAC_Exported_Functions
01220   * @{
01221   */
01222
01223 /** @addtogroup DAC_Exported_Functions_Group1
01224   * @{
01225   */
01226 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01227 /**
01228   * @brief  Register a User DAC Callback
01229   *         To be used instead of the weak (surcharged) predefined callback
01230   * @param  hdac DAC handle
01231   * @param  CallbackID ID of the callback to be registered
01232   *         This parameter can be one of the following values:
01233   *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
01234   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
01235   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
01236   *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
01237   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
01238   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
01239   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
01240   *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
01241   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
01242   *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
01243   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
01244   *
01245   * @param  pCallback pointer to the Callback function
01246   * @retval status
01247   */
01248 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
01249                                            pDAC_CallbackTypeDef pCallback)
01250 {
01251   HAL_StatusTypeDef status = HAL_OK;
01252
01253   if (pCallback == NULL)
01254   {
01255     /* Update the error code */
01256     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01257     return HAL_ERROR;
01258   }
01259
01260   /* Process locked */
01261   __HAL_LOCK(hdac);
01262
01263   if (hdac->State == HAL_DAC_STATE_READY)
01264   {
01265     switch (CallbackID)
01266     {
01267       case HAL_DAC_CH1_COMPLETE_CB_ID :
01268         hdac->ConvCpltCallbackCh1 = pCallback;
01269         break;
01270       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01271         hdac->ConvHalfCpltCallbackCh1 = pCallback;
01272         break;
01273       case HAL_DAC_CH1_ERROR_ID :
01274         hdac->ErrorCallbackCh1 = pCallback;
01275         break;
01276       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01277         hdac->DMAUnderrunCallbackCh1 = pCallback;
01278         break;
01279       case HAL_DAC_CH2_COMPLETE_CB_ID :
01280         hdac->ConvCpltCallbackCh2 = pCallback;
01281         break;
01282       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01283         hdac->ConvHalfCpltCallbackCh2 = pCallback;
01284         break;
01285       case HAL_DAC_CH2_ERROR_ID :
01286         hdac->ErrorCallbackCh2 = pCallback;
01287         break;
01288       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01289         hdac->DMAUnderrunCallbackCh2 = pCallback;
01290         break;
01291       case HAL_DAC_MSPINIT_CB_ID :
01292         hdac->MspInitCallback = pCallback;
01293         break;
01294       case HAL_DAC_MSPDEINIT_CB_ID :
01295         hdac->MspDeInitCallback = pCallback;
01296         break;
01297       default :
01298         /* Update the error code */
01299         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01300         /* update return status */
01301         status =  HAL_ERROR;
01302         break;
01303     }
01304   }
01305   else if (hdac->State == HAL_DAC_STATE_RESET)
01306   {
01307     switch (CallbackID)
01308     {
01309       case HAL_DAC_MSPINIT_CB_ID :
01310         hdac->MspInitCallback = pCallback;
01311         break;
01312       case HAL_DAC_MSPDEINIT_CB_ID :
01313         hdac->MspDeInitCallback = pCallback;
01314         break;
01315       default :
01316         /* Update the error code */
01317         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01318         /* update return status */
01319         status =  HAL_ERROR;
01320         break;
01321     }
01322   }
01323   else
01324   {
01325     /* Update the error code */
01326     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01327     /* update return status */
01328     status =  HAL_ERROR;
01329   }
01330
01331   /* Release Lock */
01332   __HAL_UNLOCK(hdac);
01333   return status;
01334 }
01335
01336 /**
01337   * @brief  Unregister a User DAC Callback
01338   *         DAC Callback is redirected to the weak (surcharged) predefined callback
01339   * @param  hdac DAC handle
01340   * @param  CallbackID ID of the callback to be unregistered
01341   *         This parameter can be one of the following values:
01342   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 tranfer Complete Callback ID
01343   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
01344   *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
01345   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
01346   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
01347   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
01348   *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
01349   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
01350   *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
01351   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
01352   *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
01353   * @retval status
01354   */
01355 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
01356 {
01357   HAL_StatusTypeDef status = HAL_OK;
01358
01359   /* Process locked */
01360   __HAL_LOCK(hdac);
01361
01362   if (hdac->State == HAL_DAC_STATE_READY)
01363   {
01364     switch (CallbackID)
01365     {
01366       case HAL_DAC_CH1_COMPLETE_CB_ID :
01367         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01368         break;
01369       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01370         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01371         break;
01372       case HAL_DAC_CH1_ERROR_ID :
01373         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01374         break;
01375       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01376         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01377         break;
01378       case HAL_DAC_CH2_COMPLETE_CB_ID :
01379         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01380         break;
01381       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01382         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01383         break;
01384       case HAL_DAC_CH2_ERROR_ID :
01385         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01386         break;
01387       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01388         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01389         break;
01390       case HAL_DAC_MSPINIT_CB_ID :
01391         hdac->MspInitCallback = HAL_DAC_MspInit;
01392         break;
01393       case HAL_DAC_MSPDEINIT_CB_ID :
01394         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01395         break;
01396       case HAL_DAC_ALL_CB_ID :
01397         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01398         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01399         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01400         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01401         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01402         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01403         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01404         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01405         hdac->MspInitCallback = HAL_DAC_MspInit;
01406         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01407         break;
01408       default :
01409         /* Update the error code */
01410         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01411         /* update return status */
01412         status =  HAL_ERROR;
01413         break;
01414     }
01415   }
01416   else if (hdac->State == HAL_DAC_STATE_RESET)
01417   {
01418     switch (CallbackID)
01419     {
01420       case HAL_DAC_MSPINIT_CB_ID :
01421         hdac->MspInitCallback = HAL_DAC_MspInit;
01422         break;
01423       case HAL_DAC_MSPDEINIT_CB_ID :
01424         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01425         break;
01426       default :
01427         /* Update the error code */
01428         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01429         /* update return status */
01430         status =  HAL_ERROR;
01431         break;
01432     }
01433   }
01434   else
01435   {
01436     /* Update the error code */
01437     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01438     /* update return status */
01439     status =  HAL_ERROR;
01440   }
01441
01442   /* Release Lock */
01443   __HAL_UNLOCK(hdac);
01444   return status;
01445 }
01446 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01447
01448 /**
01449   * @}
01450   */
01451
01452 /**
01453   * @}
01454   */
01455
01456 /** @addtogroup DAC_Private_Functions
01457   * @{
01458   */
01459
01460 /**
01461   * @brief  DMA conversion complete callback.
01462   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01463   *                the configuration information for the specified DMA module.
01464   * @retval None
01465   */
01466 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01467 {
01468   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01469
01470 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01471   hdac->ConvCpltCallbackCh1(hdac);
01472 #else
01473   HAL_DAC_ConvCpltCallbackCh1(hdac);
01474 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01475
01476   hdac->State = HAL_DAC_STATE_READY;
01477 }
01478
01479 /**
01480   * @brief  DMA half transfer complete callback.
01481   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01482   *                the configuration information for the specified DMA module.
01483   * @retval None
01484   */
01485 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01486 {
01487   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01488   /* Conversion complete callback */
01489 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01490   hdac->ConvHalfCpltCallbackCh1(hdac);
01491 #else
01492   HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01493 #endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
01494 }
01495
01496 /**
01497   * @brief  DMA error callback
01498   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01499   *                the configuration information for the specified DMA module.
01500   * @retval None
01501   */
01502 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01503 {
01504   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01505
01506   /* Set DAC error code to DMA error */
01507   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01508
01509 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01510   hdac->ErrorCallbackCh1(hdac);
01511 #else
01512   HAL_DAC_ErrorCallbackCh1(hdac);
01513 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01514
01515   hdac->State = HAL_DAC_STATE_READY;
01516 }
01517
01518 /**
01519   * @}
01520   */
01521
01522 /**
01523   * @}
01524   */
01525
01526 #endif /* DAC1 || DAC2 */
01527
01528 #endif /* HAL_DAC_MODULE_ENABLED */
01529
01530 /**
01531   * @}
01532   */
01533
01534 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac.h Source File

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stm32h7xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DAC_H
00022 #define STM32H7xx_HAL_DAC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /** @addtogroup STM32H7xx_HAL_Driver
00029   * @{
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32h7xx_hal_def.h"
00034
00035 #if defined(DAC1) || defined(DAC2)
00036
00037 /** @addtogroup DAC
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup DAC_Exported_Types DAC Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  HAL State structures definition
00049   */
00050 typedef enum
00051 {
00052   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00053   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00054   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00055   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00056   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
00057
00058 } HAL_DAC_StateTypeDef;
00059
00060 /**
00061   * @brief  DAC handle Structure definition
00062   */
00063 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00064 typedef struct __DAC_HandleTypeDef
00065 #else
00066 typedef struct
00067 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00068 {
00069   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00070
00071   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00072
00073   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00074
00075   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00076
00077   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00078
00079   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00080
00081 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00082   void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
00083   void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
00084   void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
00085   void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
00086   void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
00087   void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
00088   void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
00089   void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
00090
00091   void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
00092   void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
00093 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00094
00095 } DAC_HandleTypeDef;
00096
00097 /**
00098   * @brief   DAC Configuration sample and hold Channel structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
00103                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00104                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00105
00106   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
00107                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00108                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00109
00110   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
00111                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00112                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
00113 } DAC_SampleAndHoldConfTypeDef;
00114
00115 /**
00116   * @brief   DAC Configuration regular Channel structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
00121                                               This parameter can be a value of @ref DAC_SampleAndHold */
00122
00123   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
00124                                               This parameter can be a value of @ref DAC_trigger_selection */
00125
00126   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00127                                                This parameter can be a value of @ref DAC_output_buffer */
00128
00129   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
00130                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
00131
00132   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
00133                                               This parameter must be a value of @ref DAC_UserTrimming
00134                                               DAC_UserTrimming is either factory or user trimming */
00135
00136   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
00137                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
00138                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00139
00140   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
00141
00142 } DAC_ChannelConfTypeDef;
00143
00144 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00145 /**
00146   * @brief  HAL DAC Callback ID enumeration definition
00147   */
00148 typedef enum
00149 {
00150   HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
00151   HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
00152   HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
00153   HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
00154   HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
00155   HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
00156   HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
00157   HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
00158   HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
00159   HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
00160   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
00161 } HAL_DAC_CallbackIDTypeDef;
00162
00163 /**
00164   * @brief  HAL DAC Callback pointer definition
00165   */
00166 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
00167 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Exported constants --------------------------------------------------------*/
00174
00175 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup DAC_Error_Code DAC Error Code
00180   * @{
00181   */
00182 #define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
00183 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
00184 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
00185 #define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
00186 #define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
00187 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00188 #define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
00189 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup DAC_trigger_selection DAC trigger selection
00196   * @{
00197   */
00198 #define DAC_TRIGGER_NONE                0x00000000U                                                                       /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
00199 #define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
00200 #define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
00201 #define DAC_TRIGGER_T2_TRGO             (                                  DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00202 #define DAC_TRIGGER_T4_TRGO             (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00203 #define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00204 #define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00205 #define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00206 #define DAC_TRIGGER_T8_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00207 #define DAC_TRIGGER_T15_TRGO            (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
00208 #if defined(HRTIM1)
00209 #define DAC_TRIGGER_HR1_TRGO1           (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
00210 #define DAC_TRIGGER_HR1_TRGO2           (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
00211 #endif
00212 #define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
00213 #define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
00214 #define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00215 #if defined(TIM23)
00216 #define DAC_TRIGGER_T23_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
00217 #endif
00218 #if defined(TIM24)
00219 #define DAC_TRIGGER_T24_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
00220 #endif
00221 #if defined(DAC2)
00222 #define DAC_TRIGGER_LPTIM3_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
00223 #endif
00224
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup DAC_output_buffer DAC output buffer
00230   * @{
00231   */
00232 #define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
00233 #define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup DAC_Channel_selection DAC Channel selection
00240   * @{
00241   */
00242 #define DAC_CHANNEL_1                      0x00000000U
00243 #define DAC_CHANNEL_2                      0x00000010U
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup DAC_data_alignment DAC data alignment
00249   * @{
00250   */
00251 #define DAC_ALIGN_12B_R                    0x00000000U
00252 #define DAC_ALIGN_12B_L                    0x00000004U
00253 #define DAC_ALIGN_8B_R                     0x00000008U
00254
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup DAC_flags_definition DAC flags definition
00260   * @{
00261   */
00262 #define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
00263 #define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup DAC_IT_definition  DAC IT definition
00270   * @{
00271   */
00272 #define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
00273 #define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
00280   * @{
00281   */
00282 #define DAC_CHIPCONNECT_EXTERNAL       (1UL << 0)
00283 #define DAC_CHIPCONNECT_INTERNAL       (1UL << 1)
00284 #define DAC_CHIPCONNECT_BOTH           (1UL << 2)
00285
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup DAC_UserTrimming DAC User Trimming
00291   * @{
00292   */
00293 #define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
00294 #define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup DAC_SampleAndHold DAC power mode
00300   * @{
00301   */
00302 #define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
00303 #define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
00304
00305 /**
00306   * @}
00307   */
00308 /**
00309   * @}
00310   */
00311
00312 /* Exported macro ------------------------------------------------------------*/
00313
00314 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00315   * @{
00316   */
00317
00318 /** @brief Reset DAC handle state.
00319   * @param  __HANDLE__ specifies the DAC handle.
00320   * @retval None
00321   */
00322 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00323 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00324                                                       (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
00325                                                       (__HANDLE__)->MspInitCallback   = NULL;                \
00326                                                       (__HANDLE__)->MspDeInitCallback = NULL;                \
00327                                                      } while(0)
00328 #else
00329 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00330 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00331
00332 /** @brief Enable the DAC channel.
00333   * @param  __HANDLE__ specifies the DAC handle.
00334   * @param  __DAC_Channel__ specifies the DAC channel
00335   * @retval None
00336   */
00337 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00338   ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00339
00340 /** @brief Disable the DAC channel.
00341   * @param  __HANDLE__ specifies the DAC handle
00342   * @param  __DAC_Channel__ specifies the DAC channel.
00343   * @retval None
00344   */
00345 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00346   ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00347
00348 /** @brief Set DHR12R1 alignment.
00349   * @param  __ALIGNMENT__ specifies the DAC alignment
00350   * @retval None
00351   */
00352 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
00353
00354 /** @brief  Set DHR12R2 alignment.
00355   * @param  __ALIGNMENT__ specifies the DAC alignment
00356   * @retval None
00357   */
00358 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
00359
00360 /** @brief  Set DHR12RD alignment.
00361   * @param  __ALIGNMENT__ specifies the DAC alignment
00362   * @retval None
00363   */
00364 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
00365
00366 /** @brief Enable the DAC interrupt.
00367   * @param  __HANDLE__ specifies the DAC handle
00368   * @param  __INTERRUPT__ specifies the DAC interrupt.
00369   *          This parameter can be any combination of the following values:
00370   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00371   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00372   * @retval None
00373   */
00374 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00375
00376 /** @brief Disable the DAC interrupt.
00377   * @param  __HANDLE__ specifies the DAC handle
00378   * @param  __INTERRUPT__ specifies the DAC interrupt.
00379   *          This parameter can be any combination of the following values:
00380   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00381   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00382   * @retval None
00383   */
00384 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00385
00386 /** @brief  Check whether the specified DAC interrupt source is enabled or not.
00387   * @param __HANDLE__ DAC handle
00388   * @param __INTERRUPT__ DAC interrupt source to check
00389   *          This parameter can be any combination of the following values:
00390   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00391   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00392   * @retval State of interruption (SET or RESET)
00393   */
00394 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00395
00396 /** @brief  Get the selected DAC's flag status.
00397   * @param  __HANDLE__ specifies the DAC handle.
00398   * @param  __FLAG__ specifies the DAC flag to get.
00399   *          This parameter can be any combination of the following values:
00400   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00401   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
00402   * @retval None
00403   */
00404 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00405
00406 /** @brief  Clear the DAC's flag.
00407   * @param  __HANDLE__ specifies the DAC handle.
00408   * @param  __FLAG__ specifies the DAC flag to clear.
00409   *          This parameter can be any combination of the following values:
00410   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00411   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
00412   * @retval None
00413   */
00414 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00415
00416 /**
00417   * @}
00418   */
00419
00420 /* Private macro -------------------------------------------------------------*/
00421
00422 /** @defgroup DAC_Private_Macros DAC Private Macros
00423   * @{
00424   */
00425 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00426                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00427
00428 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00429                                  ((CHANNEL) == DAC_CHANNEL_2))
00430
00431 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00432                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00433                              ((ALIGN) == DAC_ALIGN_8B_R))
00434
00435 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
00436
00437 #define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
00438
00439 /**
00440   * @}
00441   */
00442
00443 /* Include DAC HAL Extended module */
00444 #include "stm32h7xx_hal_dac_ex.h"
00445
00446 /* Exported functions --------------------------------------------------------*/
00447
00448 /** @addtogroup DAC_Exported_Functions
00449   * @{
00450   */
00451
00452 /** @addtogroup DAC_Exported_Functions_Group1
00453   * @{
00454   */
00455 /* Initialization and de-initialization functions *****************************/
00456 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
00457 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
00458 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
00459 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
00460
00461 /**
00462   * @}
00463   */
00464
00465 /** @addtogroup DAC_Exported_Functions_Group2
00466   * @{
00467   */
00468 /* IO operation functions *****************************************************/
00469 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
00470 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
00471 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00472                                     uint32_t Alignment);
00473 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
00474 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
00475 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00476
00477 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00478 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00479 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00480 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00481
00482 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00483 /* DAC callback registering/unregistering */
00484 HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
00485                                                pDAC_CallbackTypeDef pCallback);
00486 HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
00487 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00488
00489 /**
00490   * @}
00491   */
00492
00493 /** @addtogroup DAC_Exported_Functions_Group3
00494   * @{
00495   */
00496 /* Peripheral Control functions ***********************************************/
00497 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
00498 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00499 /**
00500   * @}
00501   */
00502
00503 /** @addtogroup DAC_Exported_Functions_Group4
00504   * @{
00505   */
00506 /* Peripheral State and Error functions ***************************************/
00507 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
00508 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00509
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup DAC_Private_Functions DAC Private Functions
00519   * @{
00520   */
00521 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00522 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00523 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00524 /**
00525   * @}
00526   */
00527
00528 /**
00529   * @}
00530   */
00531
00532 #endif /* DAC1 || DAC2 */
00533
00534 /**
00535   * @}
00536   */
00537
00538 #ifdef __cplusplus
00539 }
00540 #endif
00541
00542
00543 #endif /*STM32H7xx_HAL_DAC_H */
00544
00545 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00546
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac_ex.c Source File

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stm32h7xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended DAC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the DAC peripheral.
00008   *
00009   *
00010   @verbatim
00011   ==============================================================================
00012                       ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015      *** Dual mode IO operation ***
00016      ==============================
00017       (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
00018           for dual mode operation.
00019           If software trigger is selected, using HAL_DACEx_DualStart() will start
00020           the conversion of the value previously set by HAL_DACEx_DualSetValue().
00021       (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
00022           for dual mode operation.
00023       (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
00024           for dual mode operation using DMA to feed DAC converters.
00025           First issued trigger will start the conversion of the value previously
00026           set by HAL_DACEx_DualSetValue().
00027           The same callbacks that are used in single mode are called in dual mode to notify
00028           transfer completion (half complete or complete), errors or underrun.
00029       (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
00030           for dual mode operation using DMA to feed DAC converters.
00031       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
00032           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00033           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
00034           Channel 1 and Channel 2.
00035
00036      *** Signal generation operation ***
00037      ===================================
00038       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00039       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00040
00041       (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
00042       (+) HAL_DACEx_SetUserTrimming to set user trimming value.
00043       (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
00044           after reset, user setting if HAL_DACEx_SetUserTrimming have been used
00045           at least one time after reset).
00046
00047  @endverbatim
00048   ******************************************************************************
00049   * @attention
00050   *
00051   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00052   * All rights reserved.</center></h2>
00053   *
00054   * This software component is licensed by ST under BSD 3-Clause license,
00055   * the "License"; You may not use this file except in compliance with the
00056   * License. You may obtain a copy of the License at:
00057   *                        opensource.org/licenses/BSD-3-Clause
00058   *
00059   ******************************************************************************
00060   */
00061
00062
00063 /* Includes ------------------------------------------------------------------*/
00064 #include "stm32h7xx_hal.h"
00065
00066 /** @addtogroup STM32H7xx_HAL_Driver
00067   * @{
00068   */
00069
00070 #ifdef HAL_DAC_MODULE_ENABLED
00071
00072 #if defined(DAC1) || defined(DAC2)
00073
00074 /** @defgroup DACEx DACEx
00075   * @brief DAC Extended HAL module driver
00076   * @{
00077   */
00078
00079 /* Private typedef -----------------------------------------------------------*/
00080 /* Private define ------------------------------------------------------------*/
00081 /* Private macro -------------------------------------------------------------*/
00082 /* Private variables ---------------------------------------------------------*/
00083 /* Private function prototypes -----------------------------------------------*/
00084 /* Exported functions --------------------------------------------------------*/
00085
00086 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00087   * @{
00088   */
00089
00090 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
00091   *  @brief    Extended IO operation functions
00092   *
00093 @verbatim
00094   ==============================================================================
00095                  ##### Extended features functions #####
00096   ==============================================================================
00097     [..]  This section provides functions allowing to:
00098       (+) Start conversion.
00099       (+) Stop conversion.
00100       (+) Start conversion and enable DMA transfer.
00101       (+) Stop conversion and disable DMA transfer.
00102       (+) Get result of conversion.
00103       (+) Get result of dual mode conversion.
00104
00105 @endverbatim
00106   * @{
00107   */
00108
00109 /**
00110   * @brief  Enables DAC and starts conversion of both channels.
00111   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00112   *         the configuration information for the specified DAC.
00113   * @retval HAL status
00114   */
00115 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
00116 {
00117   uint32_t tmp_swtrig = 0UL;
00118
00119
00120   /* Process locked */
00121   __HAL_LOCK(hdac);
00122
00123   /* Change DAC state */
00124   hdac->State = HAL_DAC_STATE_BUSY;
00125
00126   /* Enable the Peripheral */
00127   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
00128   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
00129
00130   /* Check if software trigger enabled */
00131   if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
00132   {
00133     tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
00134   }
00135   if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
00136   {
00137     tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
00138   }
00139   /* Enable the selected DAC software conversion*/
00140   SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
00141
00142   /* Change DAC state */
00143   hdac->State = HAL_DAC_STATE_READY;
00144
00145   /* Process unlocked */
00146   __HAL_UNLOCK(hdac);
00147
00148   /* Return function status */
00149   return HAL_OK;
00150 }
00151
00152 /**
00153   * @brief  Disables DAC and stop conversion of both channels.
00154   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00155   *         the configuration information for the specified DAC.
00156   * @retval HAL status
00157   */
00158 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
00159 {
00160
00161   /* Disable the Peripheral */
00162   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
00163   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
00164
00165   /* Change DAC state */
00166   hdac->State = HAL_DAC_STATE_READY;
00167
00168   /* Return function status */
00169   return HAL_OK;
00170 }
00171
00172 /**
00173   * @brief  Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
00174   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00175   *         the configuration information for the specified DAC.
00176   * @param  Channel The DAC channel that will request data from DMA.
00177   *          This parameter can be one of the following values:
00178   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00179   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00180   * @param  pData The destination peripheral Buffer address.
00181   * @param  Length The length of data to be transferred from memory to DAC peripheral
00182   * @param  Alignment Specifies the data alignment for DAC channel.
00183   *          This parameter can be one of the following values:
00184   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00185   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00186   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00190                                           uint32_t Alignment)
00191 {
00192   HAL_StatusTypeDef status;
00193   uint32_t tmpreg = 0UL;
00194
00195   /* Check the parameters */
00196   assert_param(IS_DAC_CHANNEL(Channel));
00197   assert_param(IS_DAC_ALIGN(Alignment));
00198
00199   /* Process locked */
00200   __HAL_LOCK(hdac);
00201
00202   /* Change DAC state */
00203   hdac->State = HAL_DAC_STATE_BUSY;
00204
00205   if (Channel == DAC_CHANNEL_1)
00206   {
00207     /* Set the DMA transfer complete callback for channel1 */
00208     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00209
00210     /* Set the DMA half transfer complete callback for channel1 */
00211     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00212
00213     /* Set the DMA error callback for channel1 */
00214     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00215
00216     /* Enable the selected DAC channel1 DMA request */
00217     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00218   }
00219   else
00220   {
00221     /* Set the DMA transfer complete callback for channel2 */
00222     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00223
00224     /* Set the DMA half transfer complete callback for channel2 */
00225     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00226
00227     /* Set the DMA error callback for channel2 */
00228     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00229
00230     /* Enable the selected DAC channel2 DMA request */
00231     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00232   }
00233
00234   switch (Alignment)
00235   {
00236     case DAC_ALIGN_12B_R:
00237       /* Get DHR12R1 address */
00238       tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
00239       break;
00240     case DAC_ALIGN_12B_L:
00241       /* Get DHR12L1 address */
00242       tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
00243       break;
00244     case DAC_ALIGN_8B_R:
00245       /* Get DHR8R1 address */
00246       tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
00247       break;
00248     default:
00249       break;
00250   }
00251
00252   /* Enable the DMA channel */
00253   if (Channel == DAC_CHANNEL_1)
00254   {
00255     /* Enable the DAC DMA underrun interrupt */
00256     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00257
00258     /* Enable the DMA channel */
00259     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00260   }
00261   else
00262   {
00263     /* Enable the DAC DMA underrun interrupt */
00264     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00265
00266     /* Enable the DMA channel */
00267     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00268   }
00269
00270   /* Process Unlocked */
00271   __HAL_UNLOCK(hdac);
00272
00273   if (status == HAL_OK)
00274   {
00275     /* Enable the Peripheral */
00276     __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
00277     __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
00278   }
00279   else
00280   {
00281     hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00282   }
00283
00284   /* Return function status */
00285   return status;
00286 }
00287
00288 /**
00289   * @brief  Disables DAC and stop conversion both channel.
00290   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00291   *         the configuration information for the specified DAC.
00292   * @param  Channel The DAC channel that requests data from DMA.
00293   *          This parameter can be one of the following values:
00294   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00295   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
00299 {
00300   HAL_StatusTypeDef status;
00301
00302
00303   /* Disable the selected DAC channel DMA request */
00304   CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
00305
00306   /* Disable the Peripheral */
00307   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
00308   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
00309
00310   /* Disable the DMA channel */
00311
00312   /* Channel1 is used */
00313   if (Channel == DAC_CHANNEL_1)
00314   {
00315     /* Disable the DMA channel */
00316     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00317
00318     /* Disable the DAC DMA underrun interrupt */
00319     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00320   }
00321   else
00322   {
00323     /* Disable the DMA channel */
00324     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00325
00326     /* Disable the DAC DMA underrun interrupt */
00327     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00328   }
00329
00330   /* Check if DMA Channel effectively disabled */
00331   if (status != HAL_OK)
00332   {
00333     /* Update DAC state machine to error */
00334     hdac->State = HAL_DAC_STATE_ERROR;
00335   }
00336   else
00337   {
00338     /* Change DAC state */
00339     hdac->State = HAL_DAC_STATE_READY;
00340   }
00341
00342   /* Return function status */
00343   return status;
00344 }
00345
00346 /**
00347   * @brief  Enable or disable the selected DAC channel wave generation.
00348   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00349   *         the configuration information for the specified DAC.
00350   * @param  Channel The selected DAC channel.
00351   *          This parameter can be one of the following values:
00352   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00353   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00354   * @param  Amplitude Select max triangle amplitude.
00355   *          This parameter can be one of the following values:
00356   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00357   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00358   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00359   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00360   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00361   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00362   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00363   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00364   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00365   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00366   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00367   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00368   * @retval HAL status
00369   */
00370 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00371 {
00372   /* Check the parameters */
00373   assert_param(IS_DAC_CHANNEL(Channel));
00374   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00375
00376   /* Process locked */
00377   __HAL_LOCK(hdac);
00378
00379   /* Change DAC state */
00380   hdac->State = HAL_DAC_STATE_BUSY;
00381
00382   /* Enable the triangle wave generation for the selected DAC channel */
00383   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
00384
00385   /* Change DAC state */
00386   hdac->State = HAL_DAC_STATE_READY;
00387
00388   /* Process unlocked */
00389   __HAL_UNLOCK(hdac);
00390
00391   /* Return function status */
00392   return HAL_OK;
00393 }
00394
00395 /**
00396   * @brief  Enable or disable the selected DAC channel wave generation.
00397   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00398   *         the configuration information for the specified DAC.
00399   * @param  Channel The selected DAC channel.
00400   *          This parameter can be one of the following values:
00401   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00402   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00403   * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
00404   *          This parameter can be one of the following values:
00405   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00406   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00407   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00408   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00409   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00410   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00411   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00412   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00413   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00414   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00415   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00416   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00420 {
00421   /* Check the parameters */
00422   assert_param(IS_DAC_CHANNEL(Channel));
00423   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00424
00425   /* Process locked */
00426   __HAL_LOCK(hdac);
00427
00428   /* Change DAC state */
00429   hdac->State = HAL_DAC_STATE_BUSY;
00430
00431   /* Enable the noise wave generation for the selected DAC channel */
00432   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
00433
00434   /* Change DAC state */
00435   hdac->State = HAL_DAC_STATE_READY;
00436
00437   /* Process unlocked */
00438   __HAL_UNLOCK(hdac);
00439
00440   /* Return function status */
00441   return HAL_OK;
00442 }
00443
00444 /**
00445   * @brief  Set the specified data holding register value for dual DAC channel.
00446   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00447   *               the configuration information for the specified DAC.
00448   * @param  Alignment Specifies the data alignment for dual channel DAC.
00449   *          This parameter can be one of the following values:
00450   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00451   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00452   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00453   * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
00454   * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
00455   * @note   In dual mode, a unique register access is required to write in both
00456   *          DAC channels at the same time.
00457   * @retval HAL status
00458   */
00459 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00460 {
00461   uint32_t data;
00462   uint32_t tmp;
00463
00464   /* Check the parameters */
00465   assert_param(IS_DAC_ALIGN(Alignment));
00466   assert_param(IS_DAC_DATA(Data1));
00467   assert_param(IS_DAC_DATA(Data2));
00468
00469   /* Calculate and set dual DAC data holding register value */
00470   if (Alignment == DAC_ALIGN_8B_R)
00471   {
00472     data = ((uint32_t)Data2 << 8U) | Data1;
00473   }
00474   else
00475   {
00476     data = ((uint32_t)Data2 << 16U) | Data1;
00477   }
00478
00479   tmp = (uint32_t)hdac->Instance;
00480   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00481
00482   /* Set the dual DAC selected data holding register */
00483   *(__IO uint32_t *)tmp = data;
00484
00485   /* Return function status */
00486   return HAL_OK;
00487 }
00488
00489 /**
00490   * @brief  Conversion complete callback in non-blocking mode for Channel2.
00491   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00492   *         the configuration information for the specified DAC.
00493   * @retval None
00494   */
00495 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00496 {
00497   /* Prevent unused argument(s) compilation warning */
00498   UNUSED(hdac);
00499
00500   /* NOTE : This function should not be modified, when the callback is needed,
00501             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00502    */
00503 }
00504
00505 /**
00506   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
00507   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00508   *         the configuration information for the specified DAC.
00509   * @retval None
00510   */
00511 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00512 {
00513   /* Prevent unused argument(s) compilation warning */
00514   UNUSED(hdac);
00515
00516   /* NOTE : This function should not be modified, when the callback is needed,
00517             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00518    */
00519 }
00520
00521 /**
00522   * @brief  Error DAC callback for Channel2.
00523   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00524   *         the configuration information for the specified DAC.
00525   * @retval None
00526   */
00527 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00528 {
00529   /* Prevent unused argument(s) compilation warning */
00530   UNUSED(hdac);
00531
00532   /* NOTE : This function should not be modified, when the callback is needed,
00533             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00534    */
00535 }
00536
00537 /**
00538   * @brief  DMA underrun DAC callback for Channel2.
00539   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00540   *         the configuration information for the specified DAC.
00541   * @retval None
00542   */
00543 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00544 {
00545   /* Prevent unused argument(s) compilation warning */
00546   UNUSED(hdac);
00547
00548   /* NOTE : This function should not be modified, when the callback is needed,
00549             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00550    */
00551 }
00552
00553 /**
00554   * @brief  Run the self calibration of one DAC channel.
00555   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00556   *         the configuration information for the specified DAC.
00557   * @param  sConfig DAC channel configuration structure.
00558   * @param  Channel The selected DAC channel.
00559   *          This parameter can be one of the following values:
00560   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00561   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00562   * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
00563   * @retval HAL status
00564   * @note   Calibration runs about 7 ms.
00565   */
00566 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
00567 {
00568   HAL_StatusTypeDef status = HAL_OK;
00569
00570   __IO uint32_t tmp;
00571   uint32_t trimmingvalue;
00572   uint32_t delta;
00573
00574   /* store/restore channel configuration structure purpose */
00575   uint32_t oldmodeconfiguration;
00576
00577   /* Check the parameters */
00578   assert_param(IS_DAC_CHANNEL(Channel));
00579
00580   /* Check the DAC handle allocation */
00581   /* Check if DAC running */
00582   if (hdac == NULL)
00583   {
00584     status = HAL_ERROR;
00585   }
00586   else if (hdac->State == HAL_DAC_STATE_BUSY)
00587   {
00588     status = HAL_ERROR;
00589   }
00590   else
00591   {
00592     /* Process locked */
00593     __HAL_LOCK(hdac);
00594
00595     /* Store configuration */
00596     oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
00597
00598     /* Disable the selected DAC channel */
00599     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
00600
00601     /* Set mode in MCR  for calibration */
00602     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
00603
00604     /* Set DAC Channel1 DHR register to the middle value */
00605     tmp = (uint32_t)hdac->Instance;
00606
00607     if (Channel == DAC_CHANNEL_1)
00608     {
00609       tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
00610     }
00611     else
00612     {
00613       tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
00614     }
00615
00616     *(__IO uint32_t *) tmp = 0x0800UL;
00617
00618     /* Enable the selected DAC channel calibration */
00619     /* i.e. set DAC_CR_CENx bit */
00620     SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00621
00622     /* Init trimming counter */
00623     /* Medium value */
00624     trimmingvalue = 16UL;
00625     delta = 8UL;
00626     while (delta != 0UL)
00627     {
00628       /* Set candidate trimming */
00629       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00630
00631       /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00632       /* i.e. minimum time needed between two calibration steps */
00633       HAL_Delay(1);
00634
00635       if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
00636       {
00637         /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
00638         trimmingvalue -= delta;
00639       }
00640       else
00641       {
00642         /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
00643         trimmingvalue += delta;
00644       }
00645       delta >>= 1UL;
00646     }
00647
00648     /* Still need to check if right calibration is current value or one step below */
00649     /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
00650     /* Set candidate trimming */
00651     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00652
00653     /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00654     /* i.e. minimum time needed between two calibration steps */
00655     HAL_Delay(1U);
00656
00657     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
00658     {
00659       /* Trimming is actually one value more */
00660       trimmingvalue++;
00661       /* Set right trimming */
00662       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00663     }
00664
00665     /* Disable the selected DAC channel calibration */
00666     /* i.e. clear DAC_CR_CENx bit */
00667     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00668
00669     sConfig->DAC_TrimmingValue = trimmingvalue;
00670     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00671
00672     /* Restore configuration */
00673     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
00674
00675     /* Process unlocked */
00676     __HAL_UNLOCK(hdac);
00677   }
00678
00679   return status;
00680 }
00681
00682 /**
00683   * @brief  Set the trimming mode and trimming value (user trimming mode applied).
00684   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00685   *         the configuration information for the specified DAC.
00686   * @param  sConfig DAC configuration structure updated with new DAC trimming value.
00687   * @param  Channel The selected DAC channel.
00688   *          This parameter can be one of the following values:
00689   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00690   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00691   * @param  NewTrimmingValue DAC new trimming value
00692   * @retval HAL status
00693   */
00694 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
00695                                             uint32_t NewTrimmingValue)
00696 {
00697   HAL_StatusTypeDef status = HAL_OK;
00698
00699   /* Check the parameters */
00700   assert_param(IS_DAC_CHANNEL(Channel));
00701   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
00702
00703   /* Check the DAC handle allocation */
00704   if (hdac == NULL)
00705   {
00706     status = HAL_ERROR;
00707   }
00708   else
00709   {
00710     /* Process locked */
00711     __HAL_LOCK(hdac);
00712
00713     /* Set new trimming */
00714     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
00715
00716     /* Update trimming mode */
00717     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00718     sConfig->DAC_TrimmingValue = NewTrimmingValue;
00719
00720     /* Process unlocked */
00721     __HAL_UNLOCK(hdac);
00722   }
00723   return status;
00724 }
00725
00726 /**
00727   * @brief  Return the DAC trimming value.
00728   * @param  hdac DAC handle
00729   * @param  Channel The selected DAC channel.
00730   *          This parameter can be one of the following values:
00731   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00732   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00733   * @retval Trimming value : range: 0->31
00734   *
00735  */
00736 uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
00737 {
00738   /* Check the parameter */
00739   assert_param(IS_DAC_CHANNEL(Channel));
00740
00741   /* Retrieve trimming */
00742   return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
00743 }
00744
00745 /**
00746   * @}
00747   */
00748
00749 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
00750   *  @brief    Extended Peripheral Control functions
00751   *
00752 @verbatim
00753   ==============================================================================
00754              ##### Peripheral Control functions #####
00755   ==============================================================================
00756     [..]  This section provides functions allowing to:
00757       (+) Set the specified data holding register value for DAC channel.
00758
00759 @endverbatim
00760   * @{
00761   */
00762
00763 /**
00764   * @brief  Return the last data output value of the selected DAC channel.
00765   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00766   *         the configuration information for the specified DAC.
00767   * @retval The selected DAC channel data output value.
00768   */
00769 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
00770 {
00771   uint32_t tmp = 0UL;
00772
00773   tmp |= hdac->Instance->DOR1;
00774
00775   tmp |= hdac->Instance->DOR2 << 16UL;
00776
00777   /* Returns the DAC channel data output register value */
00778   return tmp;
00779 }
00780
00781 /**
00782   * @}
00783   */
00784
00785 /**
00786   * @}
00787   */
00788
00789 /* Private functions ---------------------------------------------------------*/
00790 /** @defgroup DACEx_Private_Functions DACEx private functions
00791   *  @brief    Extended private functions
00792   * @{
00793   */
00794
00795 /**
00796   * @brief  DMA conversion complete callback.
00797   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00798   *                the configuration information for the specified DMA module.
00799   * @retval None
00800   */
00801 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00802 {
00803   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00804
00805 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00806   hdac->ConvCpltCallbackCh2(hdac);
00807 #else
00808   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00809 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00810
00811   hdac->State = HAL_DAC_STATE_READY;
00812 }
00813
00814 /**
00815   * @brief  DMA half transfer complete callback.
00816   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00817   *                the configuration information for the specified DMA module.
00818   * @retval None
00819   */
00820 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00821 {
00822   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00823   /* Conversion complete callback */
00824 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00825   hdac->ConvHalfCpltCallbackCh2(hdac);
00826 #else
00827   HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00828 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00829 }
00830
00831 /**
00832   * @brief  DMA error callback.
00833   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00834   *                the configuration information for the specified DMA module.
00835   * @retval None
00836   */
00837 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00838 {
00839   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00840
00841   /* Set DAC error code to DMA error */
00842   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00843
00844 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00845   hdac->ErrorCallbackCh2(hdac);
00846 #else
00847   HAL_DACEx_ErrorCallbackCh2(hdac);
00848 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00849
00850   hdac->State = HAL_DAC_STATE_READY;
00851 }
00852
00853 /**
00854   * @}
00855   */
00856
00857 /**
00858   * @}
00859   */
00860
00861 #endif /* DAC1 || DAC2 */
00862
00863 #endif /* HAL_DAC_MODULE_ENABLED */
00864
00865 /**
00866   * @}
00867   */
00868
00869 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:57 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dac_ex.h Source File

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stm32h7xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DAC_EX_H
00022 #define STM32H7xx_HAL_DAC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /** @addtogroup STM32H7xx_HAL_Driver
00029   * @{
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32h7xx_hal_def.h"
00034
00035 #if defined(DAC1) || defined(DAC2)
00036
00037 /** @addtogroup DACEx
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /**
00044   * @brief  HAL State structures definition
00045   */
00046
00047 /* Exported constants --------------------------------------------------------*/
00048
00049 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
00054   * @{
00055   */
00056 #define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00057 #define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00058 #define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00059 #define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00060 #define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00061 #define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00062 #define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00063 #define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00064 #define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00065 #define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00066 #define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00067 #define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00068 #define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
00069 #define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00070 #define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
00071 #define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00072 #define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
00073 #define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00074 #define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
00075 #define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00076 #define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
00077 #define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00078 #define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
00079 #define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00080
00081 /**
00082   * @}
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /* Exported macro ------------------------------------------------------------*/
00090
00091
00092 /* Private macro -------------------------------------------------------------*/
00093
00094 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00095   * @{
00096   */
00097 #if defined(HRTIM1)
00098 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
00099                                  ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
00100                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
00101                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
00102                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
00103                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
00104                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
00105                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
00106                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
00107                                  ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1)  || \
00108                                  ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2)  || \
00109                                  ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
00110                                  ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
00111                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
00112                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00113 #elif defined(DAC2)
00114 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
00115                                  ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
00116                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
00117                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
00118                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
00119                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
00120                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
00121                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
00122                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
00123                                  ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
00124                                  ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
00125                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
00126                                  ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
00127                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00128 #else
00129 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
00130                                  ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
00131                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
00132                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
00133                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
00134                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
00135                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
00136                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
00137                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
00138                                  ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
00139                                  ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
00140                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
00141                                  ((TRIGGER) == DAC_TRIGGER_T23_TRGO)   || \
00142                                  ((TRIGGER) == DAC_TRIGGER_T24_TRGO)   || \
00143                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00144 #endif
00145
00146 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
00147
00148 #define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
00149
00150 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
00151                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
00152
00153 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00154
00155 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00156
00157 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
00158                                          ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
00159                                          ((CONNECT) == DAC_CHIPCONNECT_BOTH))
00160
00161 #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
00162                                    ((TRIMMING) == DAC_TRIMMING_USER))
00163
00164 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00165                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00166                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00167                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00168                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00169                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00170                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00171                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00172                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00173                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00174                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00175                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00176                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00177                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00178                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00179                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00180                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00181                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00182                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00183                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00184                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00185                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00186                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00187                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00188 /**
00189   * @}
00190   */
00191
00192 /* Exported functions --------------------------------------------------------*/
00193 /* Extended features functions ***********************************************/
00194
00195 /** @addtogroup DACEx_Exported_Functions
00196   * @{
00197   */
00198
00199 /** @addtogroup DACEx_Exported_Functions_Group2
00200   * @{
00201   */
00202 /* IO operation functions *****************************************************/
00203
00204 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00205 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00206
00207 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
00208 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
00209 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00210                                           uint32_t Alignment);
00211 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
00212 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00213 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
00214
00215 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00216 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00217 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
00218 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
00219
00220
00221 /**
00222   * @}
00223   */
00224
00225 /** @addtogroup DACEx_Exported_Functions_Group3
00226   * @{
00227   */
00228 /* Peripheral Control functions ***********************************************/
00229
00230 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00231 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
00232                                             uint32_t NewTrimmingValue);
00233 uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 /** @addtogroup DACEx_Private_Functions
00244   * @{
00245   */
00246
00247 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
00248 /* are called by HAL_DAC_Start_DMA */
00249 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00250 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00251 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00252
00253 /**
00254   * @}
00255   */
00256
00257 /**
00258   * @}
00259   */
00260
00261 #endif /* DAC1 || DAC2 */
00262
00263 /**
00264   * @}
00265   */
00266
00267 #ifdef __cplusplus
00268 }
00269 #endif
00270
00271 #endif /*STM32H7xx_HAL_DAC_EX_H */
00272
00273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dcmi.c Source File

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stm32h7xx_hal_dcmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dcmi.c
00004   * @author  MCD Application Team
00005   * @brief   DCMI HAL module driver
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018       The sequence below describes how to use this driver to capture image
00019       from a camera module connected to the DCMI Interface.
00020       This sequence does not take into account the configuration of the
00021       camera module, which should be made before to configure and enable
00022       the DCMI to capture images.
00023
00024     (#) Program the required configuration through following parameters:
00025         horizontal and vertical polarity, pixel clock polarity, Capture Rate,
00026         Synchronization Mode, code of the frame delimiter and data width
00027         using HAL_DCMI_Init() function.
00028
00029     (#) Configure the selected DMA stream to transfer Data from DCMI DR
00030         register to the destination memory buffer.
00031
00032     (#) Program the required configuration through following parameters:
00033         DCMI mode, destination memory Buffer address and the data length
00034         and enable capture using HAL_DCMI_Start_DMA() function.
00035
00036     (#) Optionally, configure and Enable the CROP feature to select a rectangular
00037         window from the received image using HAL_DCMI_ConfigCrop()
00038         and HAL_DCMI_EnableCrop() functions
00039
00040     (#) The capture can be stopped using HAL_DCMI_Stop() function.
00041
00042     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
00043
00044      *** Callback registration ***
00045      =============================================
00046
00047      The compilation flag USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
00048      allows the user to configure dynamically the driver callbacks.
00049      Use Functions HAL_DCMI_RegisterCallback() to register an interrupt callback.
00050
00051      Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
00052        (+) LineEventCallback    : callback for DCMI line event.
00053        (+) FrameEventCallback   : callback for DCMI Frame event.
00054        (+) VsyncEventCallback   : callback for DCMI Vsync event.
00055        (+) ErrorCallback        : callback for error detection.
00056        (+) MspInitCallback      : callback for Msp Init.
00057        (+) MspDeInitCallback    : callback for Msp DeInit.
00058      This function takes as parameters the HAL peripheral handle, the Callback ID
00059      and a pointer to the user callback function.
00060
00061      Use function HAL_DCMI_UnRegisterCallback to reset a callback to the default weak function.
00062      HAL_DCMI_UnRegisterCallback takes as parameters the HAL peripheral handle and the Callback ID.
00063      This function allows to reset following callbacks:
00064        (+) LineEventCallback    : callback for DCMI line event.
00065        (+) FrameEventCallback   : callback for DCMI Frame event.
00066        (+) VsyncEventCallback   : callback for DCMI Vsync event.
00067        (+) ErrorCallback        : callback for error detection.
00068        (+) MspInitCallback      : callback for Msp Init.
00069        (+) MspDeInitCallback    : callback for Msp DeInit.
00070
00071      By default, after the HAL_DCMI_Init() and when the state is HAL_DCMI_STATE_RESET
00072      all callbacks are set to the corresponding weak functions:
00073      examples HAL_DCMI_LineEventCallback(), HAL_DCMI_FrameEventCallback().
00074      Exception done for MspInit and MspDeInit functions that are
00075      reset to the legacy weak functions in the HAL_DCMI_Init()/ HAL_DCMI_DeInit() only when
00076      these callbacks are null (not registered beforehand).
00077      If MspInit or MspDeInit are not null, the HAL_DCMI_Init()/ HAL_DCMI_DeInit()
00078      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00079
00080      Callbacks can be registered/unregistered in HAL_DCMI_STATE_READY state only.
00081      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00082      in HAL_DCMI_STATE_READY or HAL_DCMI_STATE_RESET state,
00083      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00084      In that case first register the MspInit/MspDeInit user callbacks
00085      using HAL_DCMI_RegisterCallback() before calling HAL_DCMI_DeInit() or HAL_DCMI_Init() function.
00086
00087      When the compilation flag USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
00088      not defined, the callback registration feature is not available and all callbacks
00089      are set to the corresponding weak functions.
00090
00091      *** DCMI HAL driver macros list ***
00092      =============================================
00093      [..]
00094        Below the list of most used macros in DCMI HAL driver.
00095
00096       (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
00097       (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
00098       (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
00099       (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
00100       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
00101       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
00102       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
00103
00104      [..]
00105        (@) You can refer to the DCMI HAL driver header file for more useful macros
00106
00107   @endverbatim
00108   ******************************************************************************
00109   * @attention
00110   *
00111   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00112   * All rights reserved.</center></h2>
00113   *
00114   * This software component is licensed by ST under BSD 3-Clause license,
00115   * the "License"; You may not use this file except in compliance with the
00116   * License. You may obtain a copy of the License at:
00117   *                        opensource.org/licenses/BSD-3-Clause
00118   *
00119   ******************************************************************************
00120   */
00121
00122 /* Includes ------------------------------------------------------------------*/
00123 #include "stm32h7xx_hal.h"
00124
00125 /** @addtogroup STM32H7xx_HAL_Driver
00126   * @{
00127   */
00128 /** @defgroup DCMI DCMI
00129   * @brief DCMI HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_DCMI_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private define ------------------------------------------------------------*/
00137 #define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */
00138
00139 /* Private macro -------------------------------------------------------------*/
00140 /* Private variables ---------------------------------------------------------*/
00141 /* Private function prototypes -----------------------------------------------*/
00142 static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
00143 static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
00144
00145 /* Exported functions --------------------------------------------------------*/
00146
00147 /** @defgroup DCMI_Exported_Functions DCMI Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00152  *  @brief   Initialization and Configuration functions
00153  *
00154 @verbatim
00155  ===============================================================================
00156                 ##### Initialization and Configuration functions #####
00157  ===============================================================================
00158     [..]  This section provides functions allowing to:
00159       (+) Initialize and configure the DCMI
00160       (+) De-initialize the DCMI
00161
00162 @endverbatim
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Initializes the DCMI according to the specified
00168   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00169   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00170   *               the configuration information for DCMI.
00171   * @retval HAL status
00172   */
00173 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00174 {
00175   /* Check the DCMI peripheral state */
00176   if(hdcmi == NULL)
00177   {
00178      return HAL_ERROR;
00179   }
00180
00181   /* Check function parameters */
00182   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00183   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00184   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00185   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00186   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00187   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00188   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00189   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00190
00191   assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
00192   assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
00193   assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
00194   assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
00195
00196 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00197   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00198   {
00199     /* Reset callback pointers to the weak predefined callbacks */
00200     hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;
00201     hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;
00202     hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;
00203     hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;
00204
00205     if(hdcmi->MspInitCallback == NULL)
00206     {
00207       hdcmi->MspInitCallback = HAL_DCMI_MspInit;
00208     }
00209     /* Init the low level hardware */
00210     hdcmi->MspInitCallback(hdcmi);
00211   }
00212
00213 #else
00214   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00215   {
00216     /* Init the low level hardware */
00217     HAL_DCMI_MspInit(hdcmi);
00218   }
00219 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00220
00221   /* Change the DCMI state */
00222   hdcmi->State = HAL_DCMI_STATE_BUSY;
00223                           /* Configures the HS, VS, DE and PC polarity */
00224   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
00225                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
00226                            DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
00227                            DCMI_CR_LSM | DCMI_CR_OELS);
00228
00229   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
00230                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\
00231                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
00232                                      hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
00233                                      hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
00234                                      hdcmi->Init.LineSelectStart);
00235
00236   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00237   {
00238     hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |\
00239                              ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
00240                              ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
00241                              ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
00242
00243   }
00244
00245   /* Enable the Line, Vsync, Error and Overrun interrupts */
00246   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
00247
00248   /* Update error code */
00249   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00250
00251   /* Initialize the DCMI state*/
00252   hdcmi->State  = HAL_DCMI_STATE_READY;
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Deinitializes the DCMI peripheral registers to their default reset
00259   *         values.
00260   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00261   *               the configuration information for DCMI.
00262   * @retval HAL status
00263   */
00264
00265 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
00266 {
00267 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00268   if(hdcmi->MspDeInitCallback == NULL)
00269   {
00270     hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
00271   }
00272
00273   /* DeInit the low level hardware */
00274   hdcmi->MspDeInitCallback(hdcmi);
00275 #else
00276   /* DeInit the low level hardware */
00277   HAL_DCMI_MspDeInit(hdcmi);
00278 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00279
00280   /* Update error code */
00281   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00282
00283   /* Initialize the DCMI state*/
00284   hdcmi->State = HAL_DCMI_STATE_RESET;
00285
00286   /* Release Lock */
00287   __HAL_UNLOCK(hdcmi);
00288
00289   return HAL_OK;
00290 }
00291
00292 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00293 /**
00294   * @brief  Register a User DCMI Callback
00295   *         To be used instead of the weak predefined callback
00296   * @param  hdcmi DCMI handle
00297   * @param  CallbackID ID of the callback to be registered
00298   *         This parameter can be one of the following values:
00299   *          @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
00300   *          @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
00301   *          @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
00302   *          @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
00303   *          @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
00304   *          @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
00305   * @param  pCallback pointer to the Callback function
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
00309 {
00310   HAL_StatusTypeDef status = HAL_OK;
00311
00312   if(pCallback == NULL)
00313   {
00314     /* Update the error code */
00315     hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00316     return HAL_ERROR;
00317   }
00318   /* Process locked */
00319   __HAL_LOCK(hdcmi);
00320
00321   if(HAL_DCMI_STATE_READY == hdcmi->State)
00322   {
00323     switch (CallbackID)
00324     {
00325     case HAL_DCMI_LINE_EVENT_CB_ID :
00326       hdcmi->LineEventCallback = pCallback;
00327       break;
00328
00329     case HAL_DCMI_FRAME_EVENT_CB_ID :
00330       hdcmi->FrameEventCallback = pCallback;
00331       break;
00332
00333     case HAL_DCMI_VSYNC_EVENT_CB_ID :
00334       hdcmi->VsyncEventCallback = pCallback;
00335       break;
00336
00337     case HAL_DCMI_ERROR_CB_ID :
00338       hdcmi->ErrorCallback = pCallback;
00339       break;
00340
00341     case HAL_DCMI_MSPINIT_CB_ID :
00342       hdcmi->MspInitCallback = pCallback;
00343       break;
00344
00345     case HAL_DCMI_MSPDEINIT_CB_ID :
00346       hdcmi->MspDeInitCallback = pCallback;
00347       break;
00348
00349     default :
00350       /* Update the error code */
00351       hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00352      /* Return error status */
00353       status =  HAL_ERROR;
00354       break;
00355     }
00356   }
00357   else if(HAL_DCMI_STATE_RESET == hdcmi->State)
00358   {
00359     switch (CallbackID)
00360     {
00361     case HAL_DCMI_MSPINIT_CB_ID :
00362       hdcmi->MspInitCallback = pCallback;
00363       break;
00364
00365     case HAL_DCMI_MSPDEINIT_CB_ID :
00366       hdcmi->MspDeInitCallback = pCallback;
00367       break;
00368
00369     default :
00370       /* Update the error code */
00371       hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00372      /* Return error status */
00373       status =  HAL_ERROR;
00374       break;
00375     }
00376   }
00377   else
00378   {
00379     /* Update the error code */
00380     hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00381     /* Return error status */
00382     status =  HAL_ERROR;
00383   }
00384
00385   /* Release Lock */
00386   __HAL_UNLOCK(hdcmi);
00387   return status;
00388 }
00389
00390 /**
00391   * @brief  Unregister a DCMI Callback
00392   *         DCMI callabck is redirected to the weak predefined callback
00393   * @param  hdcmi DCMI handle
00394   * @param  CallbackID ID of the callback to be registered
00395   *         This parameter can be one of the following values:
00396   *          @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
00397   *          @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
00398   *          @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
00399   *          @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
00400   *          @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
00401   *          @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
00402   * @retval HAL status
00403   */
00404 HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
00405 {
00406   HAL_StatusTypeDef status = HAL_OK;
00407
00408   /* Process locked */
00409   __HAL_LOCK(hdcmi);
00410
00411   if(HAL_DCMI_STATE_READY == hdcmi->State)
00412   {
00413     switch (CallbackID)
00414     {
00415     case HAL_DCMI_LINE_EVENT_CB_ID :
00416       hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;
00417       break;
00418
00419     case HAL_DCMI_FRAME_EVENT_CB_ID :
00420       hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;
00421       break;
00422
00423     case HAL_DCMI_VSYNC_EVENT_CB_ID :
00424       hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;
00425       break;
00426
00427     case HAL_DCMI_ERROR_CB_ID :
00428       hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;
00429       break;
00430
00431     case HAL_DCMI_MSPINIT_CB_ID :
00432       hdcmi->MspInitCallback = HAL_DCMI_MspInit;
00433       break;
00434
00435     case HAL_DCMI_MSPDEINIT_CB_ID :
00436       hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
00437       break;
00438
00439     default :
00440       /* Update the error code */
00441       hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00442      /* Return error status */
00443       status =  HAL_ERROR;
00444       break;
00445     }
00446   }
00447   else if(HAL_DCMI_STATE_RESET == hdcmi->State)
00448   {
00449     switch (CallbackID)
00450     {
00451     case HAL_DCMI_MSPINIT_CB_ID :
00452       hdcmi->MspInitCallback = HAL_DCMI_MspInit;
00453       break;
00454
00455     case HAL_DCMI_MSPDEINIT_CB_ID :
00456       hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
00457       break;
00458
00459     default :
00460       /* Update the error code */
00461       hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00462      /* Return error status */
00463       status =  HAL_ERROR;
00464       break;
00465     }
00466   }
00467   else
00468   {
00469     /* Update the error code */
00470     hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
00471     /* Return error status */
00472     status =  HAL_ERROR;
00473   }
00474
00475   /* Release Lock */
00476   __HAL_UNLOCK(hdcmi);
00477   return status;
00478 }
00479 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00480 /**
00481   * @brief  Initializes the DCMI MSP.
00482   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00483   *               the configuration information for DCMI.
00484   * @retval None
00485   */
00486 __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
00487 {
00488   /* Prevent unused argument(s) compilation warning */
00489   UNUSED(hdcmi);
00490
00491   /* NOTE : This function Should not be modified, when the callback is needed,
00492             the HAL_DCMI_MspInit could be implemented in the user file
00493    */
00494 }
00495
00496 /**
00497   * @brief  DeInitializes the DCMI MSP.
00498   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00499   *               the configuration information for DCMI.
00500   * @retval None
00501   */
00502 __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
00503 {
00504   /* Prevent unused argument(s) compilation warning */
00505   UNUSED(hdcmi);
00506
00507   /* NOTE : This function Should not be modified, when the callback is needed,
00508             the HAL_DCMI_MspDeInit could be implemented in the user file
00509    */
00510 }
00511
00512 /**
00513   * @}
00514   */
00515 /** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
00516  *  @brief   IO operation functions
00517  *
00518 @verbatim
00519  ===============================================================================
00520                       #####  IO operation functions  #####
00521  ===============================================================================
00522     [..]  This section provides functions allowing to:
00523       (+) Configure destination address and data length and
00524           Enables DCMI DMA request and enables DCMI capture
00525       (+) Stop the DCMI capture.
00526       (+) Handles DCMI interrupt request.
00527
00528 @endverbatim
00529   * @{
00530   */
00531
00532 /**
00533   * @brief  Enables DCMI DMA request and enables DCMI capture
00534   * @param  hdcmi     pointer to a DCMI_HandleTypeDef structure that contains
00535   *                   the configuration information for DCMI.
00536   * @param  DCMI_Mode DCMI capture mode snapshot or continuous grab.
00537   * @param  pData     The destination memory Buffer address (LCD Frame buffer).
00538   * @param  Length    The length of capture to be transferred.
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
00542 {
00543   /* Initialize the second memory address */
00544   uint32_t SecondMemAddress;
00545
00546   /* Check function parameters */
00547   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00548
00549   /* Process Locked */
00550   __HAL_LOCK(hdcmi);
00551
00552   /* Lock the DCMI peripheral state */
00553   hdcmi->State = HAL_DCMI_STATE_BUSY;
00554
00555   /* Enable DCMI by setting DCMIEN bit */
00556   __HAL_DCMI_ENABLE(hdcmi);
00557
00558   /* Configure the DCMI Mode */
00559   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
00560   hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
00561
00562   /* Set the DMA memory0 conversion complete callback */
00563   hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
00564
00565   /* Set the DMA error callback */
00566   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
00567
00568   /* Set the dma abort callback */
00569   hdcmi->DMA_Handle->XferAbortCallback = NULL;
00570
00571   /* Reset transfer counters value */
00572   hdcmi->XferCount = 0;
00573   hdcmi->XferTransferNumber = 0;
00574
00575   if(Length <= 0xFFFFU)
00576   {
00577     /* Enable the DMA Stream */
00578     if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
00579     {
00580       /* Set Error Code */
00581       hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
00582       /* Change DCMI state */
00583       hdcmi->State = HAL_DCMI_STATE_READY;
00584       /* Release Lock */
00585       __HAL_UNLOCK(hdcmi);
00586       /* Return function status */
00587       return HAL_ERROR;
00588     }
00589   }
00590   else /* DCMI_DOUBLE_BUFFER Mode */
00591   {
00592     /* Set the DMA memory1 conversion complete callback */
00593     hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
00594
00595     /* Initialize transfer parameters */
00596     hdcmi->XferCount = 1;
00597     hdcmi->XferSize = Length;
00598     hdcmi->pBuffPtr = pData;
00599
00600     /* Get the number of buffer */
00601     while(hdcmi->XferSize > 0xFFFFU)
00602     {
00603       hdcmi->XferSize = (hdcmi->XferSize/2U);
00604       hdcmi->XferCount = hdcmi->XferCount*2U;
00605     }
00606
00607     /* Update DCMI counter  and transfer number*/
00608     hdcmi->XferCount = (hdcmi->XferCount - 2U);
00609     hdcmi->XferTransferNumber = hdcmi->XferCount;
00610
00611     /* Update second memory address */
00612     SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
00613
00614     /* Start DMA multi buffer transfer */
00615     if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
00616     {
00617       /* Set Error Code */
00618       hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
00619       /* Change DCMI state */
00620       hdcmi->State = HAL_DCMI_STATE_READY;
00621       /* Release Lock */
00622       __HAL_UNLOCK(hdcmi);
00623       /* Return function status */
00624       return HAL_ERROR;
00625     }
00626   }
00627
00628   /* Enable Capture */
00629   hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
00630
00631   /* Release Lock */
00632   __HAL_UNLOCK(hdcmi);
00633
00634   /* Return function status */
00635   return HAL_OK;
00636 }
00637
00638 /**
00639   * @brief  Disable DCMI DMA request and Disable DCMI capture
00640   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00641   *               the configuration information for DCMI.
00642   * @retval HAL status
00643   */
00644 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
00645 {
00646   register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U);
00647   HAL_StatusTypeDef status = HAL_OK;
00648
00649   /* Process locked */
00650   __HAL_LOCK(hdcmi);
00651
00652   /* Lock the DCMI peripheral state */
00653   hdcmi->State = HAL_DCMI_STATE_BUSY;
00654
00655   /* Disable Capture */
00656   hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
00657
00658   /* Check if the DCMI capture effectively disabled */
00659   do
00660   {
00661     count--;
00662     if (count == 0U)
00663     {
00664       /* Update error code */
00665       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00666
00667       status = HAL_TIMEOUT;
00668       break;
00669     }
00670   }
00671   while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
00672
00673   /* Disable the DCMI */
00674   __HAL_DCMI_DISABLE(hdcmi);
00675
00676   /* Disable the DMA */
00677   (void)HAL_DMA_Abort(hdcmi->DMA_Handle);
00678
00679   /* Update error code */
00680   hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
00681
00682   /* Change DCMI state */
00683   hdcmi->State = HAL_DCMI_STATE_READY;
00684
00685   /* Process Unlocked */
00686   __HAL_UNLOCK(hdcmi);
00687
00688   /* Return function status */
00689   return status;
00690 }
00691
00692 /**
00693   * @brief  Suspend DCMI capture
00694   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00695   *               the configuration information for DCMI.
00696   * @retval HAL status
00697   */
00698 HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
00699 {
00700   register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U);
00701   HAL_StatusTypeDef status = HAL_OK;
00702
00703   /* Process locked */
00704   __HAL_LOCK(hdcmi);
00705
00706   if(hdcmi->State == HAL_DCMI_STATE_BUSY)
00707   {
00708     /* Change DCMI state */
00709     hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
00710
00711     /* Disable Capture */
00712     hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
00713
00714     /* Check if the DCMI capture effectively disabled */
00715     do
00716     {
00717       count--;
00718       if (count == 0U)
00719       {
00720         /* Update error code */
00721         hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00722
00723         /* Change DCMI state */
00724         hdcmi->State = HAL_DCMI_STATE_READY;
00725
00726         status = HAL_TIMEOUT;
00727         break;
00728       }
00729     }
00730     while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
00731   }
00732   /* Process Unlocked */
00733   __HAL_UNLOCK(hdcmi);
00734
00735   /* Return function status */
00736   return status;
00737 }
00738
00739 /**
00740   * @brief  Resume DCMI capture
00741   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00742   *               the configuration information for DCMI.
00743   * @retval HAL status
00744   */
00745 HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
00746 {
00747   /* Process locked */
00748   __HAL_LOCK(hdcmi);
00749
00750   if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
00751   {
00752     /* Change DCMI state */
00753     hdcmi->State = HAL_DCMI_STATE_BUSY;
00754
00755     /* Disable Capture */
00756     hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
00757   }
00758   /* Process Unlocked */
00759   __HAL_UNLOCK(hdcmi);
00760
00761   /* Return function status */
00762   return HAL_OK;
00763 }
00764
00765 /**
00766   * @brief  Handles DCMI interrupt request.
00767   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00768   *               the configuration information for the DCMI.
00769   * @retval None
00770   */
00771 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
00772 {
00773   uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
00774
00775   /* Synchronization error interrupt management *******************************/
00776   if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
00777   {
00778     /* Clear the Synchronization error flag */
00779     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
00780
00781     /* Update error code */
00782     hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
00783
00784     /* Change DCMI state */
00785     hdcmi->State = HAL_DCMI_STATE_ERROR;
00786
00787     /* Set the synchronization error callback */
00788     hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
00789
00790     /* Abort the DMA Transfer */
00791     (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
00792   }
00793   /* Overflow interrupt management ********************************************/
00794   if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
00795   {
00796     /* Clear the Overflow flag */
00797     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
00798
00799     /* Update error code */
00800     hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
00801
00802     /* Change DCMI state */
00803     hdcmi->State = HAL_DCMI_STATE_ERROR;
00804
00805     /* Set the overflow callback */
00806     hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
00807
00808     /* Abort the DMA Transfer */
00809     (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
00810   }
00811   /* Line Interrupt management ************************************************/
00812   if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
00813   {
00814     /* Clear the Line interrupt flag */
00815     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
00816
00817     /* Line interrupt Callback */
00818 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00819     hdcmi->LineEventCallback(hdcmi);
00820 #else
00821     HAL_DCMI_LineEventCallback(hdcmi);
00822 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00823
00824   }
00825   /* VSYNC interrupt management ***********************************************/
00826   if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
00827   {
00828     /* Clear the VSYNC flag */
00829     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
00830
00831     /* VSYNC Callback */
00832 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00833     hdcmi->VsyncEventCallback(hdcmi);
00834 #else
00835     HAL_DCMI_VsyncEventCallback(hdcmi);
00836 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00837   }
00838   /* FRAME interrupt management ***********************************************/
00839   if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
00840   {
00841     /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
00842     if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
00843     {
00844       /* Disable the Line, Vsync, Error and Overrun interrupts */
00845       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
00846     }
00847
00848     /* Disable the Frame interrupt */
00849     __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
00850
00851     /* Clear the End of Frame flag */
00852     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
00853
00854     /* Frame Callback */
00855 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00856     hdcmi->FrameEventCallback(hdcmi);
00857 #else
00858     HAL_DCMI_FrameEventCallback(hdcmi);
00859 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00860
00861   }
00862 }
00863
00864 /**
00865   * @brief  Error DCMI callback.
00866   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00867   *               the configuration information for DCMI.
00868   * @retval None
00869   */
00870 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
00871 {
00872   /* Prevent unused argument(s) compilation warning */
00873   UNUSED(hdcmi);
00874
00875   /* NOTE : This function Should not be modified, when the callback is needed,
00876             the HAL_DCMI_ErrorCallback could be implemented in the user file
00877    */
00878 }
00879
00880 /**
00881   * @brief  Line Event callback.
00882   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00883   *               the configuration information for DCMI.
00884   * @retval None
00885   */
00886 __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
00887 {
00888   /* Prevent unused argument(s) compilation warning */
00889   UNUSED(hdcmi);
00890   /* NOTE : This function Should not be modified, when the callback is needed,
00891             the HAL_DCMI_LineEventCallback could be implemented in the user file
00892    */
00893 }
00894
00895 /**
00896   * @brief  VSYNC Event callback.
00897   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00898   *               the configuration information for DCMI.
00899   * @retval None
00900   */
00901 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
00902 {
00903   /* Prevent unused argument(s) compilation warning */
00904   UNUSED(hdcmi);
00905
00906   /* NOTE : This function Should not be modified, when the callback is needed,
00907             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
00908    */
00909 }
00910
00911 /**
00912   * @brief  Frame Event callback.
00913   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00914   *               the configuration information for DCMI.
00915   * @retval None
00916   */
00917 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
00918 {
00919   /* Prevent unused argument(s) compilation warning */
00920   UNUSED(hdcmi);
00921
00922   /* NOTE : This function Should not be modified, when the callback is needed,
00923             the HAL_DCMI_FrameEventCallback could be implemented in the user file
00924    */
00925 }
00926
00927 /**
00928   * @}
00929   */
00930
00931 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00932  *  @brief    Peripheral Control functions
00933  *
00934 @verbatim
00935  ===============================================================================
00936                     ##### Peripheral Control functions #####
00937  ===============================================================================
00938 [..]  This section provides functions allowing to:
00939       (+) Configure the CROP feature.
00940       (+) Enable/Disable the CROP feature.
00941
00942 @endverbatim
00943   * @{
00944   */
00945
00946 /**
00947   * @brief  Configure the DCMI CROP coordinate.
00948   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00949   *               the configuration information for DCMI.
00950   * @param  YSize DCMI Line number
00951   * @param  XSize DCMI Pixel per line
00952   * @param  X0    DCMI window X offset
00953   * @param  Y0    DCMI window Y offset
00954   * @retval HAL status
00955   */
00956 HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
00957 {
00958   /* Process Locked */
00959   __HAL_LOCK(hdcmi);
00960
00961   /* Lock the DCMI peripheral state */
00962   hdcmi->State = HAL_DCMI_STATE_BUSY;
00963
00964   /* Check the parameters */
00965   assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
00966   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
00967   assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
00968   assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
00969
00970   /* Configure CROP */
00971   hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
00972   hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
00973
00974   /* Initialize the DCMI state*/
00975   hdcmi->State  = HAL_DCMI_STATE_READY;
00976
00977   /* Process Unlocked */
00978   __HAL_UNLOCK(hdcmi);
00979
00980   return HAL_OK;
00981 }
00982
00983 /**
00984   * @brief  Disable the Crop feature.
00985   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
00986   *               the configuration information for DCMI.
00987   * @retval HAL status
00988   */
00989 HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
00990 {
00991   /* Process Locked */
00992   __HAL_LOCK(hdcmi);
00993
00994   /* Lock the DCMI peripheral state */
00995   hdcmi->State = HAL_DCMI_STATE_BUSY;
00996
00997   /* Disable DCMI Crop feature */
00998   hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
00999
01000   /* Change the DCMI state*/
01001   hdcmi->State = HAL_DCMI_STATE_READY;
01002
01003   /* Process Unlocked */
01004   __HAL_UNLOCK(hdcmi);
01005
01006   return HAL_OK;
01007 }
01008
01009 /**
01010   * @brief  Enable the Crop feature.
01011   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
01012   *               the configuration information for DCMI.
01013   * @retval HAL status
01014   */
01015 HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
01016 {
01017   /* Process Locked */
01018   __HAL_LOCK(hdcmi);
01019
01020   /* Lock the DCMI peripheral state */
01021   hdcmi->State = HAL_DCMI_STATE_BUSY;
01022
01023   /* Enable DCMI Crop feature */
01024   hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
01025
01026   /* Change the DCMI state*/
01027   hdcmi->State = HAL_DCMI_STATE_READY;
01028
01029   /* Process Unlocked */
01030   __HAL_UNLOCK(hdcmi);
01031
01032   return HAL_OK;
01033 }
01034
01035 /**
01036   * @}
01037   */
01038
01039 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
01040  *  @brief    Peripheral State functions
01041  *
01042 @verbatim
01043  ===============================================================================
01044                ##### Peripheral State and Errors functions #####
01045  ===============================================================================
01046     [..]
01047     This subsection provides functions allowing to
01048       (+) Check the DCMI state.
01049       (+) Get the specific DCMI error flag.
01050
01051 @endverbatim
01052   * @{
01053   */
01054
01055 /**
01056   * @brief  Return the DCMI state
01057   * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
01058   *               the configuration information for DCMI.
01059   * @retval HAL state
01060   */
01061 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
01062 {
01063   return hdcmi->State;
01064 }
01065
01066 /**
01067 * @brief  Return the DCMI error code
01068 * @param  hdcmi  pointer to a DCMI_HandleTypeDef structure that contains
01069   *              the configuration information for DCMI.
01070 * @retval DCMI Error Code
01071 */
01072 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
01073 {
01074   return hdcmi->ErrorCode;
01075 }
01076
01077 /**
01078   * @}
01079   */
01080 /* Private functions ---------------------------------------------------------*/
01081 /** @defgroup DCMI_Private_Functions DCMI Private Functions
01082   * @{
01083   */
01084   /**
01085   * @brief  DMA conversion complete callback.
01086   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01087   *              the configuration information for the specified DMA module.
01088   * @retval None
01089   */
01090 static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
01091 {
01092   uint32_t tmp;
01093
01094   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01095
01096   if(hdcmi->XferCount != 0U)
01097   {
01098     /* Update memory 0 address location */
01099     tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT);
01100     if(((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
01101     {
01102       tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR;
01103       (void) HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY0);
01104       hdcmi->XferCount--;
01105     }
01106     /* Update memory 1 address location */
01107     else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
01108     {
01109       tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR;
01110       (void) HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY1);
01111       hdcmi->XferCount--;
01112     }
01113     else
01114     {
01115       /* Nothing to do */
01116     }
01117   }
01118   /* Update memory 0 address location */
01119   else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U)
01120   {
01121     ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr;
01122   }
01123   /* Update memory 1 address location */
01124   else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
01125   {
01126     tmp = hdcmi->pBuffPtr;
01127     ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U*hdcmi->XferSize));
01128     hdcmi->XferCount = hdcmi->XferTransferNumber;
01129   }
01130   else
01131   {
01132     /* Nothing to do */
01133   }
01134
01135   /* Check if the frame is transferred */
01136   if(hdcmi->XferCount == hdcmi->XferTransferNumber)
01137   {
01138     /* Enable the Frame interrupt */
01139     __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
01140
01141     /* When snapshot mode, set dcmi state to ready */
01142     if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
01143     {
01144       hdcmi->State= HAL_DCMI_STATE_READY;
01145     }
01146   }
01147 }
01148
01149 /**
01150   * @brief  DMA error callback
01151   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01152   *              the configuration information for the specified DMA module.
01153   * @retval None
01154   */
01155 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
01156 {
01157   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01158
01159   if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
01160   {
01161     /* Initialize the DCMI state*/
01162     hdcmi->State = HAL_DCMI_STATE_READY;
01163
01164     /* Set DCMI Error Code */
01165     hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
01166   }
01167
01168   /* DCMI error Callback */
01169 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
01170   hdcmi->ErrorCallback(hdcmi);
01171 #else
01172   HAL_DCMI_ErrorCallback(hdcmi);
01173 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
01174 }
01175
01176 /**
01177   * @}
01178   */
01179
01180 /**
01181   * @}
01182   */
01183 #endif /* HAL_DCMI_MODULE_ENABLED */
01184 /**
01185   * @}
01186   */
01187
01188 /**
01189   * @}
01190   */
01191
01192 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dcmi.h Source File

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stm32h7xx_hal_dcmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dcmi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DCMI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DCMI_H
00022 #define STM32H7xx_HAL_DCMI_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (DCMI)
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup DCMI DCMI
00037   * @brief DCMI HAL module driver
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup DCMI_Exported_Types DCMI Exported Types
00043   * @{
00044   */
00045 /**
00046   * @brief  HAL DCMI State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
00051   HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
00052   HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
00053   HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
00054   HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
00055   HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
00056 }HAL_DCMI_StateTypeDef;
00057
00058 /**
00059   * @brief   DCMI Embedded Synchronisation CODE Init structure definition
00060   */
00061 typedef struct
00062 {
00063   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
00064   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
00065   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
00066   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
00067 }DCMI_CodesInitTypeDef;
00068
00069 /**
00070   * @brief   DCMI Init structure definition
00071   */
00072 typedef struct
00073 {
00074   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
00075                                              This parameter can be a value of @ref DCMI_Synchronization_Mode */
00076
00077   uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
00078                                              This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
00079
00080   uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
00081                                              This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
00082
00083   uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
00084                                              This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
00085
00086   uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
00087                                              This parameter can be a value of @ref DCMI_Capture_Rate         */
00088
00089   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
00090                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
00091
00092   DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the
00093                                              line/frame end delimiter */
00094
00095   uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
00096                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
00097
00098   uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface
00099                                             This parameter can be a value of @ref DCMI_Byte_Select_Mode      */
00100
00101   uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd
00102                                             This parameter can be a value of @ref DCMI_Byte_Select_Start     */
00103
00104   uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface
00105                                             This parameter can be a value of @ref DCMI_Line_Select_Mode      */
00106
00107   uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
00108                                             This parameter can be a value of @ref DCMI_Line_Select_Start     */
00109 }DCMI_InitTypeDef;
00110
00111 /**
00112   * @brief  DCMI handle Structure definition
00113   */
00114 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00115 typedef struct  __DCMI_HandleTypeDef
00116 #else
00117 typedef struct
00118 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00119 {
00120   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
00121
00122   DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
00123
00124   HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
00125
00126   __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
00127
00128   __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
00129
00130   __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
00131
00132   uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
00133
00134   uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
00135
00136   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
00137
00138   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
00139
00140 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00141   void    (* LineEventCallback)  ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Line Event callback  */
00142   void    (* FrameEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Frame Event callback */
00143   void    (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Vsync Event callback */
00144   void    (* ErrorCallback)      ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Error callback       */
00145
00146   void    (* MspInitCallback)    ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Msp Init callback    */
00147   void    (* MspDeInitCallback)  ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Msp DeInit callback  */
00148
00149 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00150
00151 }DCMI_HandleTypeDef;
00152
00153 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00154 /**
00155   * @brief  HAL DCMI Callback ID enumeration definition
00156   */
00157 typedef enum
00158 {
00159   HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U,    /*!< DCMI Frame event Callback ID   */
00160   HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U,    /*!< DCMI Vsync event Callback ID   */
00161   HAL_DCMI_LINE_EVENT_CB_ID  = 0x02U,    /*!< DCMI Line event Callback ID    */
00162   HAL_DCMI_ERROR_CB_ID       = 0x03U,    /*!< DCMI Error Callback ID         */
00163   HAL_DCMI_MSPINIT_CB_ID     = 0x04U,    /*!< DCMI MspInit callback ID       */
00164   HAL_DCMI_MSPDEINIT_CB_ID   = 0x05U     /*!< DCMI MspDeInit callback ID     */
00165
00166 }HAL_DCMI_CallbackIDTypeDef;
00167
00168 /**
00169   * @brief  HAL DCMI Callback pointer definition
00170   */
00171 typedef  void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef * hdcmi); /*!< pointer to a DCMI callback function */
00172
00173 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00174 /**
00175   * @}
00176   */
00177 /* Exported constants --------------------------------------------------------*/
00178
00179 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
00180   * @{
00181   */
00182
00183 /** @defgroup DCMI_Error_Code DCMI Error Code
00184   * @{
00185   */
00186 #define HAL_DCMI_ERROR_NONE      (0x00000000U)    /*!< No error              */
00187 #define HAL_DCMI_ERROR_OVR       (0x00000001U)    /*!< Overrun error         */
00188 #define HAL_DCMI_ERROR_SYNC      (0x00000002U)    /*!< Synchronization error */
00189 #define HAL_DCMI_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00190 #define HAL_DCMI_ERROR_DMA       (0x00000040U)    /*!< DMA error             */
00191 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00192 #define  HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
00193 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
00199   * @{
00200   */
00201 #define DCMI_MODE_CONTINUOUS           (0x00000000U)  /*!< The received data are transferred continuously
00202                                                                     into the destination memory through the DMA             */
00203 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
00204                                                                     frame and then transfers a single frame through the DMA */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
00210   * @{
00211   */
00212 #define DCMI_SYNCHRO_HARDWARE        (0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
00213                                                                    is synchronized with the HSYNC/VSYNC signals                  */
00214 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
00215                                                                    synchronization codes embedded in the data flow               */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
00222   * @{
00223   */
00224 #define DCMI_PCKPOLARITY_FALLING    (0x00000000U)      /*!< Pixel clock active on Falling edge */
00225 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
00232   * @{
00233   */
00234 #define DCMI_VSPOLARITY_LOW     (0x00000000U)     /*!< Vertical synchronization active Low  */
00235 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
00242   * @{
00243   */
00244 #define DCMI_HSPOLARITY_LOW     (0x00000000U)     /*!< Horizontal synchronization active Low  */
00245 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
00246
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
00252   * @{
00253   */
00254 #define DCMI_JPEG_DISABLE   (0x00000000U)    /*!< Mode JPEG Disabled  */
00255 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
00256
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
00262   * @{
00263   */
00264 #define DCMI_CR_ALL_FRAME            (0x00000000U)      /*!< All frames are captured        */
00265 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
00266 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
00267
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
00273   * @{
00274   */
00275 #define DCMI_EXTEND_DATA_8B     (0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
00276 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
00277 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
00278 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
00285   * @{
00286   */
00287 #define DCMI_WINDOW_COORDINATE    (0x3FFFU)  /*!< Window coordinate */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DCMI_Window_Height DCMI Window Height
00294   * @{
00295   */
00296 #define DCMI_WINDOW_HEIGHT    (0x1FFFU)  /*!< Window Height */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
00303   * @{
00304   */
00305 #define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
00306 #define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
00307 #define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
00308 #define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
00309 #define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup DCMI_Flags DCMI Flags
00315   * @{
00316   */
00317
00318 /**
00319   * @brief   DCMI SR register
00320   */
00321 #define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
00322 #define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
00323 #define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
00324 /**
00325   * @brief   DCMI RIS register
00326   */
00327 #define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
00328 #define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */
00329 #define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */
00330 #define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
00331 #define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */
00332 /**
00333   * @brief   DCMI MIS register
00334   */
00335 #define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */
00336 #define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
00337 #define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
00338 #define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
00339 #define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
00345   * @{
00346   */
00347 #define DCMI_BSM_ALL                 (0x00000000U) /*!< Interface captures all received data */
00348 #define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
00349 #define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
00350 #define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
00357   * @{
00358   */
00359 #define DCMI_OEBS_ODD               (0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
00360 #define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
00361
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
00367   * @{
00368   */
00369 #define DCMI_LSM_ALL                 (0x00000000U) /*!< Interface captures all received lines */
00370 #define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
00377   * @{
00378   */
00379 #define DCMI_OELS_ODD               (0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
00380 #define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /**
00387   * @}
00388   */
00389
00390 /* Exported macro ------------------------------------------------------------*/
00391 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
00392   * @{
00393   */
00394
00395 /** @brief Reset DCMI handle state
00396   * @param  __HANDLE__ specifies the DCMI handle.
00397   * @retval None
00398   */
00399 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00400 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__)  do{                                             \
00401                                                        (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
00402                                                        (__HANDLE__)->MspInitCallback = NULL;       \
00403                                                        (__HANDLE__)->MspDeInitCallback = NULL;     \
00404                                                      } while(0)
00405 #else
00406 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
00407 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00408
00409 /**
00410   * @brief  Enable the DCMI.
00411   * @param  __HANDLE__ DCMI handle
00412   * @retval None
00413   */
00414 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
00415
00416 /**
00417   * @brief  Disable the DCMI.
00418   * @param  __HANDLE__ DCMI handle
00419   * @retval None
00420   */
00421 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
00422
00423 /* Interrupt & Flag management */
00424 /**
00425   * @brief  Get the DCMI pending flag.
00426   * @param  __HANDLE__ DCMI handle
00427   * @param  __FLAG__ Get the specified flag.
00428   *         This parameter can be one of the following values (no combination allowed)
00429   *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
00430   *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
00431   *            @arg DCMI_FLAG_FNE: FIFO empty flag
00432   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00433   *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
00434   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00435   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00436   *            @arg DCMI_FLAG_LINERI: Line flag mask
00437   *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
00438   *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
00439   *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
00440   *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
00441   *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
00442   * @retval The state of FLAG.
00443   */
00444 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
00445 ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
00446  (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
00447
00448 /**
00449   * @brief  Clear the DCMI pending flags.
00450   * @param  __HANDLE__ DCMI handle
00451   * @param  __FLAG__ specifies the flag to clear.
00452   *         This parameter can be any combination of the following values:
00453   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00454   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
00455   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00456   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00457   *            @arg DCMI_FLAG_LINERI: Line flag mask
00458   * @retval None
00459   */
00460 #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00461
00462 /**
00463   * @brief  Enable the specified DCMI interrupts.
00464   * @param  __HANDLE__    DCMI handle
00465   * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
00466   *         This parameter can be any combination of the following values:
00467   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00468   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00469   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00470   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00471   *            @arg DCMI_IT_LINE: Line interrupt mask
00472   * @retval None
00473   */
00474 #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00475
00476 /**
00477   * @brief  Disable the specified DCMI interrupts.
00478   * @param  __HANDLE__ DCMI handle
00479   * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
00480   *         This parameter can be any combination of the following values:
00481   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00482   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00483   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00484   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00485   *            @arg DCMI_IT_LINE: Line interrupt mask
00486   * @retval None
00487   */
00488 #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00489
00490 /**
00491   * @brief  Check whether the specified DCMI interrupt has occurred or not.
00492   * @param  __HANDLE__ DCMI handle
00493   * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.
00494   *         This parameter can be one of the following values:
00495   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00496   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00497   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00498   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00499   *            @arg DCMI_IT_LINE: Line interrupt mask
00500   * @retval The state of INTERRUPT.
00501   */
00502 #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
00503
00504 /**
00505   * @}
00506   */
00507
00508 /* Exported functions --------------------------------------------------------*/
00509 /** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
00510   * @{
00511   */
00512
00513 /** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00514  * @{
00515  */
00516 /* Initialization and de-initialization functions *****************************/
00517 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
00518 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
00519 void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
00520 void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
00521
00522 /* Callbacks Register/UnRegister functions  ***********************************/
00523 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
00524 HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
00525 HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
00526 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
00533  * @{
00534  */
00535 /* IO operation functions *****************************************************/
00536 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
00537 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
00538 HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
00539 HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
00540 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
00541 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
00542 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
00543 void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
00544 void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
00545 /**
00546   * @}
00547   */
00548
00549 /** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00550  * @{
00551  */
00552 /* Peripheral Control functions ***********************************************/
00553 HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
00554 HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
00555 HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
00556
00557 /**
00558   * @}
00559   */
00560
00561 /** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
00562  * @{
00563  */
00564 /* Peripheral State functions *************************************************/
00565 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
00566 uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
00567 /**
00568   * @}
00569   */
00570
00571 /**
00572   * @}
00573   */
00574
00575 /* Private types -------------------------------------------------------------*/
00576 /* Private variables ---------------------------------------------------------*/
00577 /* Private constants ---------------------------------------------------------*/
00578 /** @defgroup DCMI_Private_Constants DCMI Private Constants
00579   * @{
00580   */
00581 #define DCMI_MIS_INDEX        (0x1000) /*!< DCMI MIS register index */
00582 #define DCMI_SR_INDEX         (0x2000) /*!< DCMI SR register index  */
00583 /**
00584   * @}
00585   */
00586 /* Private macro -------------------------------------------------------------*/
00587 /** @defgroup DCMI_Private_Macros DCMI Private Macros
00588   * @{
00589   */
00590 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
00591                                    ((MODE) == DCMI_MODE_SNAPSHOT))
00592
00593 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
00594                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
00595
00596 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
00597                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
00598
00599 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
00600                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
00601
00602 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
00603                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
00604
00605 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
00606                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
00607
00608 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
00609                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
00610                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
00611
00612 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
00613                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
00614                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
00615                                     ((DATA) == DCMI_EXTEND_DATA_14B))
00616
00617 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
00618
00619 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
00620
00621 #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
00622                                        ((MODE) == DCMI_BSM_OTHER) || \
00623                                        ((MODE) == DCMI_BSM_ALTERNATE_4) || \
00624                                        ((MODE) == DCMI_BSM_ALTERNATE_2))
00625
00626 #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
00627                                             ((POLARITY) == DCMI_OEBS_EVEN))
00628
00629 #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
00630                                        ((MODE) == DCMI_LSM_ALTERNATE_2))
00631
00632 #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
00633                                             ((POLARITY) == DCMI_OELS_EVEN))
00634
00635 /**
00636   * @}
00637   */
00638
00639 /* Private functions ---------------------------------------------------------*/
00640 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
00641   * @{
00642   */
00643
00644 /**
00645   * @}
00646   */
00647
00648 /**
00649   * @}
00650   */
00651 /**
00652   * @}
00653   */
00654
00655 #endif /* DCMI */
00656
00657 #ifdef __cplusplus
00658 }
00659 #endif
00660
00661 #endif /* STM32H7xx_HAL_DCMI_H */
00662
00663 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm.c Source File

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stm32h7xx_hal_dfsdm.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Digital Filter for Sigma-Delta Modulators
00007   *          (DFSDM) peripherals:
00008   *           + Initialization and configuration of channels and filters
00009   *           + Regular channels configuration
00010   *           + Injected channels configuration
00011   *           + Regular/Injected Channels DMA Configuration
00012   *           + Interrupts and flags management
00013   *           + Analog watchdog feature
00014   *           + Short-circuit detector feature
00015   *           + Extremes detector feature
00016   *           + Clock absence detector feature
00017   *           + Break generation on analog watchdog or short-circuit event
00018   *
00019   @verbatim
00020   ==============================================================================
00021                      ##### How to use this driver #####
00022   ==============================================================================
00023   [..]
00024     *** Channel initialization ***
00025     ==============================
00026     [..]
00027       (#) User has first to initialize channels (before filters initialization).
00028       (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
00029         (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
00030         (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00031         (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
00032         (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
00033             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00034       (#) Configure the output clock, input, serial interface, analog watchdog,
00035           offset and data right bit shift parameters for this channel using the
00036           HAL_DFSDM_ChannelInit() function.
00037
00038     *** Channel clock absence detector ***
00039     ======================================
00040     [..]
00041       (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
00042           HAL_DFSDM_ChannelCkabStart_IT().
00043       (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
00044           absence.
00045       (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
00046           clock absence is detected.
00047       (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
00048           HAL_DFSDM_ChannelCkabStop_IT().
00049       (#) Please note that the same mode (polling or interrupt) has to be used
00050           for all channels because the channels are sharing the same interrupt.
00051       (#) Please note also that in interrupt mode, if clock absence detector is
00052           stopped for one channel, interrupt will be disabled for all channels.
00053
00054     *** Channel short circuit detector ***
00055     ======================================
00056     [..]
00057       (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
00058           or HAL_DFSDM_ChannelScdStart_IT().
00059       (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
00060           circuit.
00061       (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
00062           short circuit is detected.
00063       (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
00064           or HAL_DFSDM_ChannelScdStop_IT().
00065       (#) Please note that the same mode (polling or interrupt) has to be used
00066           for all channels because the channels are sharing the same interrupt.
00067       (#) Please note also that in interrupt mode, if short circuit detector is
00068           stopped for one channel, interrupt will be disabled for all channels.
00069
00070     *** Channel analog watchdog value ***
00071     =====================================
00072     [..]
00073       (#) Get analog watchdog filter value of a channel using
00074           HAL_DFSDM_ChannelGetAwdValue().
00075
00076     *** Channel offset value ***
00077     =====================================
00078     [..]
00079       (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
00080
00081     *** Filter initialization ***
00082     =============================
00083     [..]
00084       (#) After channel initialization, user has to init filters.
00085       (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
00086         (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
00087             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00088             Please note that DFSDMz_FLT0 global interrupt could be already
00089             enabled if interrupt is used for channel.
00090         (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
00091             with DFSDMz filter handle using __HAL_LINKDMA().
00092       (#) Configure the regular conversion, injected conversion and filter
00093           parameters for this filter using the HAL_DFSDM_FilterInit() function.
00094
00095     *** Filter regular channel conversion ***
00096     =========================================
00097     [..]
00098       (#) Select regular channel and enable/disable continuous mode using
00099           HAL_DFSDM_FilterConfigRegChannel().
00100       (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
00101           HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
00102           HAL_DFSDM_FilterRegularMsbStart_DMA().
00103       (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
00104           the end of regular conversion.
00105       (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
00106           at the end of regular conversion.
00107       (#) Get value of regular conversion and corresponding channel using
00108           HAL_DFSDM_FilterGetRegularValue().
00109       (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
00110           HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
00111           half transfer and at the transfer complete. Please note that
00112           HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
00113           circular mode.
00114       (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
00115           HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
00116
00117     *** Filter injected channels conversion ***
00118     ===========================================
00119     [..]
00120       (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
00121       (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
00122           HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
00123           HAL_DFSDM_FilterInjectedMsbStart_DMA().
00124       (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
00125           the end of injected conversion.
00126       (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
00127           at the end of injected conversion.
00128       (#) Get value of injected conversion and corresponding channel using
00129           HAL_DFSDM_FilterGetInjectedValue().
00130       (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
00131           HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
00132           half transfer and at the transfer complete. Please note that
00133           HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
00134           circular mode.
00135       (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
00136           HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
00137
00138     *** Filter analog watchdog ***
00139     ==============================
00140     [..]
00141       (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
00142       (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
00143       (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
00144
00145     *** Filter extreme detector ***
00146     ===============================
00147     [..]
00148       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
00149       (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
00150       (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
00151       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
00152
00153     *** Filter conversion time ***
00154     ==============================
00155     [..]
00156       (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
00157
00158     *** Callback registration ***
00159     =============================
00160     [..]
00161     The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
00162     allows the user to configure dynamically the driver callbacks.
00163     Use functions HAL_DFSDM_Channel_RegisterCallback(),
00164     HAL_DFSDM_Filter_RegisterCallback() or
00165     HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
00166
00167     [..]
00168     Function HAL_DFSDM_Channel_RegisterCallback() allows to register
00169     following callbacks:
00170       (+) CkabCallback      : DFSDM channel clock absence detection callback.
00171       (+) ScdCallback       : DFSDM channel short circuit detection callback.
00172       (+) MspInitCallback   : DFSDM channel MSP init callback.
00173       (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
00174     [..]
00175     This function takes as parameters the HAL peripheral handle, the Callback ID
00176     and a pointer to the user callback function.
00177
00178     [..]
00179     Function HAL_DFSDM_Filter_RegisterCallback() allows to register
00180     following callbacks:
00181       (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
00182       (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
00183       (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.
00184       (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
00185       (+) ErrorCallback           : DFSDM filter error callback.
00186       (+) MspInitCallback         : DFSDM filter MSP init callback.
00187       (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.
00188     [..]
00189     This function takes as parameters the HAL peripheral handle, the Callback ID
00190     and a pointer to the user callback function.
00191
00192     [..]
00193     For specific DFSDM filter analog watchdog callback use dedicated register callback:
00194     HAL_DFSDM_Filter_RegisterAwdCallback().
00195
00196     [..]
00197     Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
00198     HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
00199     weak function.
00200
00201     [..]
00202     HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00203     and the Callback ID.
00204     [..]
00205     This function allows to reset following callbacks:
00206       (+) CkabCallback      : DFSDM channel clock absence detection callback.
00207       (+) ScdCallback       : DFSDM channel short circuit detection callback.
00208       (+) MspInitCallback   : DFSDM channel MSP init callback.
00209       (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
00210
00211     [..]
00212     HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00213     and the Callback ID.
00214     [..]
00215     This function allows to reset following callbacks:
00216       (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
00217       (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
00218       (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.
00219       (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
00220       (+) ErrorCallback           : DFSDM filter error callback.
00221       (+) MspInitCallback         : DFSDM filter MSP init callback.
00222       (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.
00223
00224     [..]
00225     For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
00226     HAL_DFSDM_Filter_UnRegisterAwdCallback().
00227
00228     [..]
00229     By default, after the call of init function and if the state is RESET
00230     all callbacks are reset to the corresponding legacy weak functions:
00231     examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
00232     Exception done for MspInit and MspDeInit callbacks that are respectively
00233     reset to the legacy weak functions in the init and de-init only when these
00234     callbacks are null (not registered beforehand).
00235     If not, MspInit or MspDeInit are not null, the init and de-init keep and use
00236     the user MspInit/MspDeInit callbacks (registered beforehand)
00237
00238     [..]
00239     Callbacks can be registered/unregistered in READY state only.
00240     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00241     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00242     during the init/de-init.
00243     In that case first register the MspInit/MspDeInit user callbacks using
00244     HAL_DFSDM_Channel_RegisterCallback() or
00245     HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
00246
00247     [..]
00248     When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
00249     not defined, the callback registering feature is not available
00250     and weak callbacks are used.
00251
00252     @endverbatim
00253   ******************************************************************************
00254   * @attention
00255   *
00256   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00257   * All rights reserved.</center></h2>
00258   *
00259   * This software component is licensed by ST under BSD 3-Clause license,
00260   * the "License"; You may not use this file except in compliance with the
00261   * License. You may obtain a copy of the License at:
00262   *                        opensource.org/licenses/BSD-3-Clause
00263   *
00264   ******************************************************************************
00265   */
00266
00267 /* Includes ------------------------------------------------------------------*/
00268 #include "stm32h7xx_hal.h"
00269
00270 /** @addtogroup STM32H7xx_HAL_Driver
00271   * @{
00272   */
00273 #ifdef HAL_DFSDM_MODULE_ENABLED
00274
00275 /** @defgroup DFSDM DFSDM
00276   * @brief DFSDM HAL driver module
00277   * @{
00278   */
00279
00280 /* Private typedef -----------------------------------------------------------*/
00281 /* Private define ------------------------------------------------------------*/
00282 /** @defgroup DFSDM_Private_Define DFSDM Private Define
00283  * @{
00284  */
00285 #define DFSDM_FLTCR1_MSB_RCH_OFFSET     8
00286 #define DFSDM_MSB_MASK                  0xFFFF0000U
00287 #define DFSDM_LSB_MASK                  0x0000FFFFU
00288 #define DFSDM_CKAB_TIMEOUT              5000U
00289 #define DFSDM1_CHANNEL_NUMBER           8U
00290 #if defined(DFSDM2_Channel0)
00291 #define DFSDM2_CHANNEL_NUMBER           2U
00292 #endif /* DFSDM2_Channel0 */
00293 /**
00294   * @}
00295   */
00296
00297 /* Private macro -------------------------------------------------------------*/
00298 /* Private variables ---------------------------------------------------------*/
00299 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
00300   * @{
00301   */
00302 static __IO uint32_t                v_dfsdm1ChannelCounter = 0;
00303 static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
00304 #if defined(DFSDM2_Channel0)
00305 static __IO uint32_t                v_dfsdm2ChannelCounter = 0;
00306 static DFSDM_Channel_HandleTypeDef *a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};
00307 #endif /* DFSDM2_Channel0 */
00308 /**
00309   * @}
00310   */
00311
00312 /* Private function prototypes -----------------------------------------------*/
00313 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
00314   * @{
00315   */
00316 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
00317 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);
00318 static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00319 static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00320 static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00321 static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00322 static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
00323 static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
00324 static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
00325 static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
00326 static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);
00327 /**
00328   * @}
00329   */
00330
00331 /* Exported functions --------------------------------------------------------*/
00332 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
00333   * @{
00334   */
00335
00336 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00337  *  @brief    Channel initialization and de-initialization functions
00338  *
00339 @verbatim
00340   ==============================================================================
00341         ##### Channel initialization and de-initialization functions #####
00342   ==============================================================================
00343     [..]  This section provides functions allowing to:
00344       (+) Initialize the DFSDM channel.
00345       (+) De-initialize the DFSDM channel.
00346 @endverbatim
00347   * @{
00348   */
00349
00350 /**
00351   * @brief  Initialize the DFSDM channel according to the specified parameters
00352   *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
00353   * @param  hdfsdm_channel DFSDM channel handle.
00354   * @retval HAL status.
00355   */
00356 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00357 {
00358   __IO uint32_t               *channelCounterPtr;
00359   DFSDM_Channel_HandleTypeDef **channelHandleTable;
00360   DFSDM_Channel_TypeDef       *channel0Instance;
00361
00362   /* Check DFSDM Channel handle */
00363   if(hdfsdm_channel == NULL)
00364   {
00365     return HAL_ERROR;
00366   }
00367
00368   /* Check parameters */
00369   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00370   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
00371   assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
00372   assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
00373   assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
00374   assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
00375   assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
00376   assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
00377   assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
00378   assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
00379   assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
00380
00381 #if defined(DFSDM2_Channel0)
00382   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00383   {
00384     channelCounterPtr  = &v_dfsdm1ChannelCounter;
00385     channelHandleTable = a_dfsdm1ChannelHandle;
00386     channel0Instance   = DFSDM1_Channel0;
00387   }
00388   else
00389   {
00390     channelCounterPtr  = &v_dfsdm2ChannelCounter;
00391     channelHandleTable = a_dfsdm2ChannelHandle;
00392     channel0Instance   = DFSDM2_Channel0;
00393   }
00394 #else /* DFSDM2_Channel0 */
00395   channelCounterPtr  = &v_dfsdm1ChannelCounter;
00396   channelHandleTable = a_dfsdm1ChannelHandle;
00397   channel0Instance   = DFSDM1_Channel0;
00398 #endif /* DFSDM2_Channel0 */
00399
00400   /* Check that channel has not been already initialized */
00401   if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
00402   {
00403     return HAL_ERROR;
00404   }
00405
00406 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00407   /* Reset callback pointers to the weak predefined callbacks */
00408   hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
00409   hdfsdm_channel->ScdCallback  = HAL_DFSDM_ChannelScdCallback;
00410
00411   /* Call MSP init function */
00412   if(hdfsdm_channel->MspInitCallback == NULL)
00413   {
00414     hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
00415   }
00416   hdfsdm_channel->MspInitCallback(hdfsdm_channel);
00417 #else
00418   /* Call MSP init function */
00419   HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
00420 #endif
00421
00422   /* Update the channel counter */
00423   (*channelCounterPtr)++;
00424
00425   /* Configure output serial clock and enable global DFSDM interface only for first channel */
00426   if(*channelCounterPtr == 1U)
00427   {
00428     assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
00429     /* Set the output serial clock source */
00430     channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
00431     channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
00432
00433     /* Reset clock divider */
00434     channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
00435     if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
00436     {
00437       assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
00438       /* Set the output clock divider */
00439       channel0Instance->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
00440                                               DFSDM_CHCFGR1_CKOUTDIV_Pos);
00441     }
00442
00443     /* enable the DFSDM global interface */
00444     channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
00445   }
00446
00447   /* Set channel input parameters */
00448   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
00449                                          DFSDM_CHCFGR1_CHINSEL);
00450   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
00451                                         hdfsdm_channel->Init.Input.DataPacking |
00452                                         hdfsdm_channel->Init.Input.Pins);
00453
00454   /* Set serial interface parameters */
00455   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
00456   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
00457                                         hdfsdm_channel->Init.SerialInterface.SpiClock);
00458
00459   /* Set analog watchdog parameters */
00460   hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
00461   hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
00462                                        ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
00463
00464   /* Set channel offset and right bit shift */
00465   hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
00466   hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
00467                                         (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
00468
00469   /* Enable DFSDM channel */
00470   hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
00471
00472   /* Set DFSDM Channel to ready state */
00473   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
00474
00475   /* Store channel handle in DFSDM channel handle table */
00476   channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
00477
00478   return HAL_OK;
00479 }
00480
00481 /**
00482   * @brief  De-initialize the DFSDM channel.
00483   * @param  hdfsdm_channel DFSDM channel handle.
00484   * @retval HAL status.
00485   */
00486 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00487 {
00488   __IO uint32_t               *channelCounterPtr;
00489   DFSDM_Channel_HandleTypeDef **channelHandleTable;
00490   DFSDM_Channel_TypeDef       *channel0Instance;
00491
00492   /* Check DFSDM Channel handle */
00493   if(hdfsdm_channel == NULL)
00494   {
00495     return HAL_ERROR;
00496   }
00497
00498   /* Check parameters */
00499   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00500
00501 #if defined(DFSDM2_Channel0)
00502   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00503   {
00504     channelCounterPtr  = &v_dfsdm1ChannelCounter;
00505     channelHandleTable = a_dfsdm1ChannelHandle;
00506     channel0Instance   = DFSDM1_Channel0;
00507   }
00508   else
00509   {
00510     channelCounterPtr  = &v_dfsdm2ChannelCounter;
00511     channelHandleTable = a_dfsdm2ChannelHandle;
00512     channel0Instance   = DFSDM2_Channel0;
00513   }
00514 #else /* DFSDM2_Channel0 */
00515   channelCounterPtr  = &v_dfsdm1ChannelCounter;
00516   channelHandleTable = a_dfsdm1ChannelHandle;
00517   channel0Instance   = DFSDM1_Channel0;
00518 #endif /* DFSDM2_Channel0 */
00519
00520   /* Check that channel has not been already deinitialized */
00521   if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
00522   {
00523     return HAL_ERROR;
00524   }
00525
00526   /* Disable the DFSDM channel */
00527   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
00528
00529   /* Update the channel counter */
00530   (*channelCounterPtr)--;
00531
00532   /* Disable global DFSDM at deinit of last channel */
00533   if (*channelCounterPtr == 0U)
00534   {
00535     channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
00536   }
00537
00538   /* Call MSP deinit function */
00539 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00540   if(hdfsdm_channel->MspDeInitCallback == NULL)
00541   {
00542     hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
00543   }
00544   hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
00545 #else
00546   HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
00547 #endif
00548
00549   /* Set DFSDM Channel in reset state */
00550   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
00551
00552   /* Reset channel handle in DFSDM channel handle table */
00553   channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
00554
00555   return HAL_OK;
00556 }
00557
00558 /**
00559   * @brief  Initialize the DFSDM channel MSP.
00560   * @param  hdfsdm_channel DFSDM channel handle.
00561   * @retval None
00562   */
00563 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00564 {
00565   /* Prevent unused argument(s) compilation warning */
00566   UNUSED(hdfsdm_channel);
00567
00568   /* NOTE : This function should not be modified, when the function is needed,
00569             the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
00570    */
00571 }
00572
00573 /**
00574   * @brief  De-initialize the DFSDM channel MSP.
00575   * @param  hdfsdm_channel DFSDM channel handle.
00576   * @retval None
00577   */
00578 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00579 {
00580   /* Prevent unused argument(s) compilation warning */
00581   UNUSED(hdfsdm_channel);
00582
00583   /* NOTE : This function should not be modified, when the function is needed,
00584             the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
00585    */
00586 }
00587
00588 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00589 /**
00590   * @brief  Register a user DFSDM channel callback
00591   *         to be used instead of the weak predefined callback.
00592   * @param  hdfsdm_channel DFSDM channel handle.
00593   * @param  CallbackID ID of the callback to be registered.
00594   *         This parameter can be one of the following values:
00595   *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
00596   *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
00597   *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
00598   *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
00599   * @param  pCallback pointer to the callback function.
00600   * @retval HAL status.
00601   */
00602 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
00603                                                      HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
00604                                                      pDFSDM_Channel_CallbackTypeDef      pCallback)
00605 {
00606   HAL_StatusTypeDef status = HAL_OK;
00607
00608   if(pCallback == NULL)
00609   {
00610     /* update return status */
00611     status = HAL_ERROR;
00612   }
00613   else
00614   {
00615     if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
00616     {
00617       switch (CallbackID)
00618       {
00619         case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
00620           hdfsdm_channel->CkabCallback = pCallback;
00621           break;
00622         case HAL_DFSDM_CHANNEL_SCD_CB_ID :
00623           hdfsdm_channel->ScdCallback = pCallback;
00624           break;
00625         case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
00626           hdfsdm_channel->MspInitCallback = pCallback;
00627           break;
00628         case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
00629           hdfsdm_channel->MspDeInitCallback = pCallback;
00630           break;
00631         default :
00632           /* update return status */
00633           status = HAL_ERROR;
00634           break;
00635       }
00636     }
00637     else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
00638     {
00639       switch (CallbackID)
00640       {
00641         case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
00642           hdfsdm_channel->MspInitCallback = pCallback;
00643           break;
00644         case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
00645           hdfsdm_channel->MspDeInitCallback = pCallback;
00646           break;
00647         default :
00648           /* update return status */
00649           status = HAL_ERROR;
00650           break;
00651       }
00652     }
00653     else
00654     {
00655       /* update return status */
00656       status = HAL_ERROR;
00657     }
00658   }
00659   return status;
00660 }
00661
00662 /**
00663   * @brief  Unregister a user DFSDM channel callback.
00664   *         DFSDM channel callback is redirected to the weak predefined callback.
00665   * @param  hdfsdm_channel DFSDM channel handle.
00666   * @param  CallbackID ID of the callback to be unregistered.
00667   *         This parameter can be one of the following values:
00668   *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
00669   *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
00670   *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
00671   *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
00672   * @retval HAL status.
00673   */
00674 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
00675                                                        HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
00676 {
00677   HAL_StatusTypeDef status = HAL_OK;
00678
00679   if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
00680   {
00681     switch (CallbackID)
00682     {
00683     case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
00684       hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
00685       break;
00686     case HAL_DFSDM_CHANNEL_SCD_CB_ID :
00687       hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
00688       break;
00689     case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
00690       hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
00691       break;
00692     case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
00693       hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
00694       break;
00695     default :
00696       /* update return status */
00697       status = HAL_ERROR;
00698       break;
00699     }
00700   }
00701   else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
00702   {
00703     switch (CallbackID)
00704     {
00705     case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
00706       hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
00707       break;
00708     case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
00709       hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
00710       break;
00711     default :
00712       /* update return status */
00713       status = HAL_ERROR;
00714       break;
00715     }
00716   }
00717   else
00718   {
00719     /* update return status */
00720     status = HAL_ERROR;
00721   }
00722   return status;
00723 }
00724 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00731  *  @brief    Channel operation functions
00732  *
00733 @verbatim
00734   ==============================================================================
00735                    ##### Channel operation functions #####
00736   ==============================================================================
00737     [..]  This section provides functions allowing to:
00738       (+) Manage clock absence detector feature.
00739       (+) Manage short circuit detector feature.
00740       (+) Get analog watchdog value.
00741       (+) Modify offset value.
00742 @endverbatim
00743   * @{
00744   */
00745
00746 /**
00747   * @brief  This function allows to start clock absence detection in polling mode.
00748   * @note   Same mode has to be used for all channels.
00749   * @note   If clock is not available on this channel during 5 seconds,
00750   *         clock absence detection will not be activated and function
00751   *         will return HAL_TIMEOUT error.
00752   * @param  hdfsdm_channel DFSDM channel handle.
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00756 {
00757   HAL_StatusTypeDef status = HAL_OK;
00758   uint32_t channel;
00759   uint32_t tickstart;
00760   DFSDM_Filter_TypeDef *filter0Instance;
00761
00762   /* Check parameters */
00763   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00764
00765 #if defined(DFSDM2_Channel0)
00766   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00767   {
00768     filter0Instance = DFSDM1_Filter0;
00769   }
00770   else
00771   {
00772     filter0Instance = DFSDM2_Filter0;
00773   }
00774 #else /* DFSDM2_Channel0 */
00775   filter0Instance = DFSDM1_Filter0;
00776 #endif /* DFSDM2_Channel0 */
00777
00778   /* Check DFSDM channel state */
00779   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00780   {
00781     /* Return error status */
00782     status = HAL_ERROR;
00783   }
00784   else
00785   {
00786     /* Get channel number from channel instance */
00787     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00788
00789     /* Get timeout */
00790     tickstart = HAL_GetTick();
00791
00792     /* Clear clock absence flag */
00793     while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
00794     {
00795       filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
00796
00797       /* Check the Timeout */
00798       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00799       {
00800         /* Set timeout status */
00801         status = HAL_TIMEOUT;
00802         break;
00803       }
00804     }
00805
00806     if(status == HAL_OK)
00807     {
00808       /* Start clock absence detection */
00809       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00810     }
00811   }
00812   /* Return function status */
00813   return status;
00814 }
00815
00816 /**
00817   * @brief  This function allows to poll for the clock absence detection.
00818   * @param  hdfsdm_channel DFSDM channel handle.
00819   * @param  Timeout Timeout value in milliseconds.
00820   * @retval HAL status
00821   */
00822 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00823                                                uint32_t Timeout)
00824 {
00825   uint32_t tickstart;
00826   uint32_t channel;
00827   DFSDM_Filter_TypeDef *filter0Instance;
00828
00829   /* Check parameters */
00830   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00831
00832 #if defined(DFSDM2_Channel0)
00833   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00834   {
00835     filter0Instance = DFSDM1_Filter0;
00836   }
00837   else
00838   {
00839     filter0Instance = DFSDM2_Filter0;
00840   }
00841 #else /* DFSDM2_Channel0 */
00842   filter0Instance = DFSDM1_Filter0;
00843 #endif /* DFSDM2_Channel0 */
00844
00845   /* Check DFSDM channel state */
00846   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00847   {
00848     /* Return error status */
00849     return HAL_ERROR;
00850   }
00851   else
00852   {
00853     /* Get channel number from channel instance */
00854     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00855
00856     /* Get timeout */
00857     tickstart = HAL_GetTick();
00858
00859     /* Wait clock absence detection */
00860     while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
00861     {
00862       /* Check the Timeout */
00863       if(Timeout != HAL_MAX_DELAY)
00864       {
00865         if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
00866         {
00867           /* Return timeout status */
00868           return HAL_TIMEOUT;
00869         }
00870       }
00871     }
00872
00873     /* Clear clock absence detection flag */
00874     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
00875
00876     /* Return function status */
00877     return HAL_OK;
00878   }
00879 }
00880
00881 /**
00882   * @brief  This function allows to stop clock absence detection in polling mode.
00883   * @param  hdfsdm_channel DFSDM channel handle.
00884   * @retval HAL status
00885   */
00886 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00887 {
00888   HAL_StatusTypeDef status = HAL_OK;
00889   uint32_t channel;
00890   DFSDM_Filter_TypeDef *filter0Instance;
00891
00892   /* Check parameters */
00893   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00894
00895 #if defined(DFSDM2_Channel0)
00896   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00897   {
00898     filter0Instance = DFSDM1_Filter0;
00899   }
00900   else
00901   {
00902     filter0Instance = DFSDM2_Filter0;
00903   }
00904 #else /* DFSDM2_Channel0 */
00905   filter0Instance = DFSDM1_Filter0;
00906 #endif /* DFSDM2_Channel0 */
00907
00908   /* Check DFSDM channel state */
00909   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00910   {
00911     /* Return error status */
00912     status = HAL_ERROR;
00913   }
00914   else
00915   {
00916     /* Stop clock absence detection */
00917     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
00918
00919     /* Clear clock absence flag */
00920     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00921     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
00922   }
00923   /* Return function status */
00924   return status;
00925 }
00926
00927 /**
00928   * @brief  This function allows to start clock absence detection in interrupt mode.
00929   * @note   Same mode has to be used for all channels.
00930   * @note   If clock is not available on this channel during 5 seconds,
00931   *         clock absence detection will not be activated and function
00932   *         will return HAL_TIMEOUT error.
00933   * @param  hdfsdm_channel DFSDM channel handle.
00934   * @retval HAL status
00935   */
00936 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00937 {
00938   HAL_StatusTypeDef status = HAL_OK;
00939   uint32_t channel;
00940   uint32_t tickstart;
00941   DFSDM_Filter_TypeDef *filter0Instance;
00942
00943   /* Check parameters */
00944   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00945
00946 #if defined(DFSDM2_Channel0)
00947   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
00948   {
00949     filter0Instance = DFSDM1_Filter0;
00950   }
00951   else
00952   {
00953     filter0Instance = DFSDM2_Filter0;
00954   }
00955 #else /* DFSDM2_Channel0 */
00956   filter0Instance = DFSDM1_Filter0;
00957 #endif /* DFSDM2_Channel0 */
00958
00959   /* Check DFSDM channel state */
00960   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00961   {
00962     /* Return error status */
00963     status = HAL_ERROR;
00964   }
00965   else
00966   {
00967     /* Get channel number from channel instance */
00968     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00969
00970     /* Get timeout */
00971     tickstart = HAL_GetTick();
00972
00973     /* Clear clock absence flag */
00974     while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
00975     {
00976       filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
00977
00978       /* Check the Timeout */
00979       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00980       {
00981         /* Set timeout status */
00982         status = HAL_TIMEOUT;
00983         break;
00984       }
00985     }
00986
00987     if(status == HAL_OK)
00988     {
00989       /* Activate clock absence detection interrupt */
00990       filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
00991
00992       /* Start clock absence detection */
00993       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00994     }
00995   }
00996   /* Return function status */
00997   return status;
00998 }
00999
01000 /**
01001   * @brief  Clock absence detection callback.
01002   * @param  hdfsdm_channel DFSDM channel handle.
01003   * @retval None
01004   */
01005 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01006 {
01007   /* Prevent unused argument(s) compilation warning */
01008   UNUSED(hdfsdm_channel);
01009
01010   /* NOTE : This function should not be modified, when the callback is needed,
01011             the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
01012    */
01013 }
01014
01015 /**
01016   * @brief  This function allows to stop clock absence detection in interrupt mode.
01017   * @note   Interrupt will be disabled for all channels
01018   * @param  hdfsdm_channel DFSDM channel handle.
01019   * @retval HAL status
01020   */
01021 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01022 {
01023   HAL_StatusTypeDef status = HAL_OK;
01024   uint32_t channel;
01025   DFSDM_Filter_TypeDef *filter0Instance;
01026
01027   /* Check parameters */
01028   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01029
01030 #if defined(DFSDM2_Channel0)
01031   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
01032   {
01033     filter0Instance = DFSDM1_Filter0;
01034   }
01035   else
01036   {
01037     filter0Instance = DFSDM2_Filter0;
01038   }
01039 #else /* DFSDM2_Channel0 */
01040   filter0Instance = DFSDM1_Filter0;
01041 #endif /* DFSDM2_Channel0 */
01042
01043   /* Check DFSDM channel state */
01044   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01045   {
01046     /* Return error status */
01047     status = HAL_ERROR;
01048   }
01049   else
01050   {
01051     /* Stop clock absence detection */
01052     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
01053
01054     /* Clear clock absence flag */
01055     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
01056     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
01057
01058     /* Disable clock absence detection interrupt */
01059     filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
01060   }
01061   /* Return function status */
01062   return status;
01063 }
01064
01065 /**
01066   * @brief  This function allows to start short circuit detection in polling mode.
01067   * @note   Same mode has to be used for all channels
01068   * @param  hdfsdm_channel DFSDM channel handle.
01069   * @param  Threshold Short circuit detector threshold.
01070   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
01071   * @param  BreakSignal Break signals assigned to short circuit event.
01072   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
01073   * @retval HAL status
01074   */
01075 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
01076                                             uint32_t Threshold,
01077                                             uint32_t BreakSignal)
01078 {
01079   HAL_StatusTypeDef status = HAL_OK;
01080
01081   /* Check parameters */
01082   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01083   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
01084   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
01085
01086   /* Check DFSDM channel state */
01087   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01088   {
01089     /* Return error status */
01090     status = HAL_ERROR;
01091   }
01092   else
01093   {
01094     /* Configure threshold and break signals */
01095     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
01096     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
01097                                          Threshold);
01098
01099     /* Start short circuit detection */
01100     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
01101   }
01102   /* Return function status */
01103   return status;
01104 }
01105
01106 /**
01107   * @brief  This function allows to poll for the short circuit detection.
01108   * @param  hdfsdm_channel DFSDM channel handle.
01109   * @param  Timeout Timeout value in milliseconds.
01110   * @retval HAL status
01111   */
01112 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
01113                                               uint32_t Timeout)
01114 {
01115   uint32_t tickstart;
01116   uint32_t channel;
01117   DFSDM_Filter_TypeDef *filter0Instance;
01118
01119   /* Check parameters */
01120   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01121
01122 #if defined(DFSDM2_Channel0)
01123   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
01124   {
01125     filter0Instance = DFSDM1_Filter0;
01126   }
01127   else
01128   {
01129     filter0Instance = DFSDM2_Filter0;
01130   }
01131 #else /* DFSDM2_Channel0 */
01132   filter0Instance = DFSDM1_Filter0;
01133 #endif /* DFSDM2_Channel0 */
01134
01135   /* Check DFSDM channel state */
01136   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01137   {
01138     /* Return error status */
01139     return HAL_ERROR;
01140   }
01141   else
01142   {
01143     /* Get channel number from channel instance */
01144     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
01145
01146     /* Get timeout */
01147     tickstart = HAL_GetTick();
01148
01149     /* Wait short circuit detection */
01150     while (((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
01151     {
01152       /* Check the Timeout */
01153       if(Timeout != HAL_MAX_DELAY)
01154       {
01155         if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
01156         {
01157           /* Return timeout status */
01158           return HAL_TIMEOUT;
01159         }
01160       }
01161     }
01162
01163     /* Clear short circuit detection flag */
01164     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
01165
01166     /* Return function status */
01167     return HAL_OK;
01168   }
01169 }
01170
01171 /**
01172   * @brief  This function allows to stop short circuit detection in polling mode.
01173   * @param  hdfsdm_channel DFSDM channel handle.
01174   * @retval HAL status
01175   */
01176 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01177 {
01178   HAL_StatusTypeDef status = HAL_OK;
01179   uint32_t channel;
01180   DFSDM_Filter_TypeDef *filter0Instance;
01181
01182   /* Check parameters */
01183   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01184
01185 #if defined(DFSDM2_Channel0)
01186   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
01187   {
01188     filter0Instance = DFSDM1_Filter0;
01189   }
01190   else
01191   {
01192     filter0Instance = DFSDM2_Filter0;
01193   }
01194 #else /* DFSDM2_Channel0 */
01195   filter0Instance = DFSDM1_Filter0;
01196 #endif /* DFSDM2_Channel0 */
01197
01198   /* Check DFSDM channel state */
01199   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01200   {
01201     /* Return error status */
01202     status = HAL_ERROR;
01203   }
01204   else
01205   {
01206     /* Stop short circuit detection */
01207     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
01208
01209     /* Clear short circuit detection flag */
01210     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
01211     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
01212   }
01213   /* Return function status */
01214   return status;
01215 }
01216
01217 /**
01218   * @brief  This function allows to start short circuit detection in interrupt mode.
01219   * @note   Same mode has to be used for all channels
01220   * @param  hdfsdm_channel DFSDM channel handle.
01221   * @param  Threshold Short circuit detector threshold.
01222   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
01223   * @param  BreakSignal Break signals assigned to short circuit event.
01224   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
01225   * @retval HAL status
01226   */
01227 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
01228                                                uint32_t Threshold,
01229                                                uint32_t BreakSignal)
01230 {
01231   HAL_StatusTypeDef status = HAL_OK;
01232   DFSDM_Filter_TypeDef *filter0Instance;
01233
01234   /* Check parameters */
01235   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01236   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
01237   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
01238
01239 #if defined(DFSDM2_Channel0)
01240   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
01241   {
01242     filter0Instance = DFSDM1_Filter0;
01243   }
01244   else
01245   {
01246     filter0Instance = DFSDM2_Filter0;
01247   }
01248 #else /* DFSDM2_Channel0 */
01249   filter0Instance = DFSDM1_Filter0;
01250 #endif /* DFSDM2_Channel0 */
01251
01252   /* Check DFSDM channel state */
01253   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01254   {
01255     /* Return error status */
01256     status = HAL_ERROR;
01257   }
01258   else
01259   {
01260     /* Activate short circuit detection interrupt */
01261     filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
01262
01263     /* Configure threshold and break signals */
01264     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
01265     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
01266                                          Threshold);
01267
01268     /* Start short circuit detection */
01269     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
01270   }
01271   /* Return function status */
01272   return status;
01273 }
01274
01275 /**
01276   * @brief  Short circuit detection callback.
01277   * @param  hdfsdm_channel DFSDM channel handle.
01278   * @retval None
01279   */
01280 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01281 {
01282   /* Prevent unused argument(s) compilation warning */
01283   UNUSED(hdfsdm_channel);
01284
01285   /* NOTE : This function should not be modified, when the callback is needed,
01286             the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
01287    */
01288 }
01289
01290 /**
01291   * @brief  This function allows to stop short circuit detection in interrupt mode.
01292   * @note   Interrupt will be disabled for all channels
01293   * @param  hdfsdm_channel DFSDM channel handle.
01294   * @retval HAL status
01295   */
01296 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01297 {
01298   HAL_StatusTypeDef status = HAL_OK;
01299   uint32_t channel;
01300   DFSDM_Filter_TypeDef *filter0Instance;
01301
01302   /* Check parameters */
01303   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01304
01305 #if defined(DFSDM2_Channel0)
01306   if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
01307   {
01308     filter0Instance = DFSDM1_Filter0;
01309   }
01310   else
01311   {
01312     filter0Instance = DFSDM2_Filter0;
01313   }
01314 #else /* DFSDM2_Channel0 */
01315   filter0Instance = DFSDM1_Filter0;
01316 #endif /* DFSDM2_Channel0 */
01317
01318   /* Check DFSDM channel state */
01319   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01320   {
01321     /* Return error status */
01322     status = HAL_ERROR;
01323   }
01324   else
01325   {
01326     /* Stop short circuit detection */
01327     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
01328
01329     /* Clear short circuit detection flag */
01330     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
01331     filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
01332
01333     /* Disable short circuit detection interrupt */
01334     filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
01335   }
01336   /* Return function status */
01337   return status;
01338 }
01339
01340 /**
01341   * @brief  This function allows to get channel analog watchdog value.
01342   * @param  hdfsdm_channel DFSDM channel handle.
01343   * @retval Channel analog watchdog value.
01344   */
01345 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01346 {
01347   return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
01348 }
01349
01350 /**
01351   * @brief  This function allows to modify channel offset value.
01352   * @param  hdfsdm_channel DFSDM channel handle.
01353   * @param  Offset DFSDM channel offset.
01354   *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
01355   * @retval HAL status.
01356   */
01357 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
01358                                                 int32_t Offset)
01359 {
01360   HAL_StatusTypeDef status = HAL_OK;
01361
01362   /* Check parameters */
01363   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
01364   assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
01365
01366   /* Check DFSDM channel state */
01367   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
01368   {
01369     /* Return error status */
01370     status = HAL_ERROR;
01371   }
01372   else
01373   {
01374     /* Modify channel offset */
01375     hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
01376     hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
01377   }
01378   /* Return function status */
01379   return status;
01380 }
01381
01382 /**
01383   * @}
01384   */
01385
01386 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
01387  *  @brief    Channel state function
01388  *
01389 @verbatim
01390   ==============================================================================
01391                    ##### Channel state function #####
01392   ==============================================================================
01393     [..]  This section provides function allowing to:
01394       (+) Get channel handle state.
01395 @endverbatim
01396   * @{
01397   */
01398
01399 /**
01400   * @brief  This function allows to get the current DFSDM channel handle state.
01401   * @param  hdfsdm_channel DFSDM channel handle.
01402   * @retval DFSDM channel state.
01403   */
01404 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01405 {
01406   /* Return DFSDM channel handle state */
01407   return hdfsdm_channel->State;
01408 }
01409
01410 /**
01411   * @}
01412   */
01413
01414 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
01415  *  @brief    Filter initialization and de-initialization functions
01416  *
01417 @verbatim
01418   ==============================================================================
01419         ##### Filter initialization and de-initialization functions #####
01420   ==============================================================================
01421     [..]  This section provides functions allowing to:
01422       (+) Initialize the DFSDM filter.
01423       (+) De-initialize the DFSDM filter.
01424 @endverbatim
01425   * @{
01426   */
01427
01428 /**
01429   * @brief  Initialize the DFSDM filter according to the specified parameters
01430   *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
01431   * @param  hdfsdm_filter DFSDM filter handle.
01432   * @retval HAL status.
01433   */
01434 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01435 {
01436   const DFSDM_Filter_TypeDef *filter0Instance;
01437
01438   /* Check DFSDM Channel handle */
01439   if(hdfsdm_filter == NULL)
01440   {
01441     return HAL_ERROR;
01442   }
01443
01444   /* Check parameters */
01445   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01446   assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
01447   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
01448   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
01449   assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
01450   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
01451   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
01452   assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
01453   assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
01454   assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
01455
01456 #if defined(DFSDM2_Channel0)
01457   if (IS_DFSDM1_FILTER_INSTANCE(hdfsdm_filter->Instance))
01458   {
01459     filter0Instance = DFSDM1_Filter0;
01460   }
01461   else
01462   {
01463     filter0Instance = DFSDM2_Filter0;
01464   }
01465 #else /* DFSDM2_Channel0 */
01466   filter0Instance = DFSDM1_Filter0;
01467 #endif /* DFSDM2_Channel0 */
01468
01469   /* Check parameters compatibility */
01470   if ((hdfsdm_filter->Instance == filter0Instance) &&
01471       ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) ||
01472        (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
01473   {
01474     return HAL_ERROR;
01475   }
01476
01477   /* Initialize DFSDM filter variables with default values */
01478   hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;
01479   hdfsdm_filter->InjectedChannelsNbr = 1;
01480   hdfsdm_filter->InjConvRemaining    = 1;
01481   hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
01482
01483 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
01484   /* Reset callback pointers to the weak predefined callbacks */
01485   hdfsdm_filter->AwdCallback             = HAL_DFSDM_FilterAwdCallback;
01486   hdfsdm_filter->RegConvCpltCallback     = HAL_DFSDM_FilterRegConvCpltCallback;
01487   hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
01488   hdfsdm_filter->InjConvCpltCallback     = HAL_DFSDM_FilterInjConvCpltCallback;
01489   hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
01490   hdfsdm_filter->ErrorCallback           = HAL_DFSDM_FilterErrorCallback;
01491
01492   /* Call MSP init function */
01493   if(hdfsdm_filter->MspInitCallback == NULL)
01494   {
01495     hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
01496   }
01497   hdfsdm_filter->MspInitCallback(hdfsdm_filter);
01498 #else
01499   /* Call MSP init function */
01500   HAL_DFSDM_FilterMspInit(hdfsdm_filter);
01501 #endif
01502
01503   /* Set regular parameters */
01504   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
01505   if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
01506   {
01507     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
01508   }
01509   else
01510   {
01511     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
01512   }
01513
01514   if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
01515   {
01516     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
01517   }
01518   else
01519   {
01520     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
01521   }
01522
01523   /* Set injected parameters */
01524   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
01525   if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
01526   {
01527     assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
01528     assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
01529     hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
01530   }
01531
01532   if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
01533   {
01534     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
01535   }
01536   else
01537   {
01538     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
01539   }
01540
01541   if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
01542   {
01543     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
01544   }
01545   else
01546   {
01547     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
01548   }
01549
01550   /* Set filter parameters */
01551   hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
01552   hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
01553                                       ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
01554                                       (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
01555
01556   /* Store regular and injected triggers and injected scan mode*/
01557   hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;
01558   hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;
01559   hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
01560   hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
01561
01562   /* Enable DFSDM filter */
01563   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
01564
01565   /* Set DFSDM filter to ready state */
01566   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
01567
01568   return HAL_OK;
01569 }
01570
01571 /**
01572   * @brief  De-initializes the DFSDM filter.
01573   * @param  hdfsdm_filter DFSDM filter handle.
01574   * @retval HAL status.
01575   */
01576 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01577 {
01578   /* Check DFSDM filter handle */
01579   if(hdfsdm_filter == NULL)
01580   {
01581     return HAL_ERROR;
01582   }
01583
01584   /* Check parameters */
01585   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01586
01587   /* Disable the DFSDM filter */
01588   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
01589
01590   /* Call MSP deinit function */
01591 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
01592   if(hdfsdm_filter->MspDeInitCallback == NULL)
01593   {
01594     hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
01595   }
01596   hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);
01597 #else
01598   HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
01599 #endif
01600
01601   /* Set DFSDM filter in reset state */
01602   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
01603
01604   return HAL_OK;
01605 }
01606
01607 /**
01608   * @brief  Initializes the DFSDM filter MSP.
01609   * @param  hdfsdm_filter DFSDM filter handle.
01610   * @retval None
01611   */
01612 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01613 {
01614   /* Prevent unused argument(s) compilation warning */
01615   UNUSED(hdfsdm_filter);
01616
01617   /* NOTE : This function should not be modified, when the function is needed,
01618             the HAL_DFSDM_FilterMspInit could be implemented in the user file.
01619    */
01620 }
01621
01622 /**
01623   * @brief  De-initializes the DFSDM filter MSP.
01624   * @param  hdfsdm_filter DFSDM filter handle.
01625   * @retval None
01626   */
01627 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01628 {
01629   /* Prevent unused argument(s) compilation warning */
01630   UNUSED(hdfsdm_filter);
01631
01632   /* NOTE : This function should not be modified, when the function is needed,
01633             the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
01634    */
01635 }
01636
01637 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
01638 /**
01639   * @brief  Register a user DFSDM filter callback
01640   *         to be used instead of the weak predefined callback.
01641   * @param  hdfsdm_filter DFSDM filter handle.
01642   * @param  CallbackID ID of the callback to be registered.
01643   *         This parameter can be one of the following values:
01644   *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
01645   *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
01646   *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
01647   *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
01648   *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
01649   *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
01650   *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
01651   * @param  pCallback pointer to the callback function.
01652   * @retval HAL status.
01653   */
01654 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
01655                                                     HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
01656                                                     pDFSDM_Filter_CallbackTypeDef      pCallback)
01657 {
01658   HAL_StatusTypeDef status = HAL_OK;
01659
01660   if(pCallback == NULL)
01661   {
01662     /* update the error code */
01663     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01664     /* update return status */
01665     status = HAL_ERROR;
01666   }
01667   else
01668   {
01669     if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
01670     {
01671       switch (CallbackID)
01672       {
01673         case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
01674           hdfsdm_filter->RegConvCpltCallback = pCallback;
01675           break;
01676         case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
01677           hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
01678           break;
01679         case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
01680           hdfsdm_filter->InjConvCpltCallback = pCallback;
01681           break;
01682         case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
01683           hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
01684           break;
01685         case HAL_DFSDM_FILTER_ERROR_CB_ID :
01686           hdfsdm_filter->ErrorCallback = pCallback;
01687           break;
01688         case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
01689           hdfsdm_filter->MspInitCallback = pCallback;
01690           break;
01691         case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
01692           hdfsdm_filter->MspDeInitCallback = pCallback;
01693           break;
01694         default :
01695           /* update the error code */
01696           hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01697           /* update return status */
01698           status = HAL_ERROR;
01699           break;
01700       }
01701     }
01702     else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
01703     {
01704       switch (CallbackID)
01705       {
01706         case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
01707           hdfsdm_filter->MspInitCallback = pCallback;
01708           break;
01709         case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
01710           hdfsdm_filter->MspDeInitCallback = pCallback;
01711           break;
01712         default :
01713           /* update the error code */
01714           hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01715           /* update return status */
01716           status = HAL_ERROR;
01717           break;
01718       }
01719     }
01720     else
01721     {
01722       /* update the error code */
01723       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01724       /* update return status */
01725       status = HAL_ERROR;
01726     }
01727   }
01728   return status;
01729 }
01730
01731 /**
01732   * @brief  Unregister a user DFSDM filter callback.
01733   *         DFSDM filter callback is redirected to the weak predefined callback.
01734   * @param  hdfsdm_filter DFSDM filter handle.
01735   * @param  CallbackID ID of the callback to be unregistered.
01736   *         This parameter can be one of the following values:
01737   *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
01738   *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
01739   *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
01740   *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
01741   *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
01742   *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
01743   *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
01744   * @retval HAL status.
01745   */
01746 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
01747                                                       HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
01748 {
01749   HAL_StatusTypeDef status = HAL_OK;
01750
01751   if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
01752   {
01753     switch (CallbackID)
01754     {
01755       case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
01756         hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
01757         break;
01758       case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
01759         hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
01760         break;
01761       case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
01762         hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
01763         break;
01764       case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
01765         hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
01766         break;
01767       case HAL_DFSDM_FILTER_ERROR_CB_ID :
01768         hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
01769         break;
01770       case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
01771         hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
01772         break;
01773       case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
01774         hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
01775         break;
01776       default :
01777         /* update the error code */
01778         hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01779         /* update return status */
01780         status = HAL_ERROR;
01781         break;
01782     }
01783   }
01784   else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
01785   {
01786     switch (CallbackID)
01787     {
01788       case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
01789         hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
01790         break;
01791       case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
01792         hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
01793         break;
01794       default :
01795         /* update the error code */
01796         hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01797         /* update return status */
01798         status = HAL_ERROR;
01799         break;
01800     }
01801   }
01802   else
01803   {
01804     /* update the error code */
01805     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01806     /* update return status */
01807     status = HAL_ERROR;
01808   }
01809   return status;
01810 }
01811
01812 /**
01813   * @brief  Register a user DFSDM filter analog watchdog callback
01814   *         to be used instead of the weak predefined callback.
01815   * @param  hdfsdm_filter DFSDM filter handle.
01816   * @param  pCallback pointer to the DFSDM filter analog watchdog callback function.
01817   * @retval HAL status.
01818   */
01819 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,
01820                                                        pDFSDM_Filter_AwdCallbackTypeDef pCallback)
01821 {
01822   HAL_StatusTypeDef status = HAL_OK;
01823
01824   if(pCallback == NULL)
01825   {
01826     /* update the error code */
01827     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01828     /* update return status */
01829     status = HAL_ERROR;
01830   }
01831   else
01832   {
01833     if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
01834     {
01835       hdfsdm_filter->AwdCallback = pCallback;
01836     }
01837     else
01838     {
01839       /* update the error code */
01840       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01841       /* update return status */
01842       status = HAL_ERROR;
01843     }
01844   }
01845   return status;
01846 }
01847
01848 /**
01849   * @brief  Unregister a user DFSDM filter analog watchdog callback.
01850   *         DFSDM filter AWD callback is redirected to the weak predefined callback.
01851   * @param  hdfsdm_filter DFSDM filter handle.
01852   * @retval HAL status.
01853   */
01854 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01855 {
01856   HAL_StatusTypeDef status = HAL_OK;
01857
01858   if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
01859   {
01860     hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
01861   }
01862   else
01863   {
01864     /* update the error code */
01865     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
01866     /* update return status */
01867     status = HAL_ERROR;
01868   }
01869   return status;
01870 }
01871 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
01872
01873 /**
01874   * @}
01875   */
01876
01877 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
01878  *  @brief    Filter control functions
01879  *
01880 @verbatim
01881   ==============================================================================
01882                     ##### Filter control functions #####
01883   ==============================================================================
01884     [..]  This section provides functions allowing to:
01885       (+) Select channel and enable/disable continuous mode for regular conversion.
01886       (+) Select channels for injected conversion.
01887 @endverbatim
01888   * @{
01889   */
01890
01891 /**
01892   * @brief  This function allows to select channel and to enable/disable
01893   *         continuous mode for regular conversion.
01894   * @param  hdfsdm_filter DFSDM filter handle.
01895   * @param  Channel Channel for regular conversion.
01896   *         This parameter can be a value of @ref DFSDM_Channel_Selection.
01897   * @param  ContinuousMode Enable/disable continuous mode for regular conversion.
01898   *         This parameter can be a value of @ref DFSDM_ContinuousMode.
01899   * @retval HAL status
01900   */
01901 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01902                                                    uint32_t                    Channel,
01903                                                    uint32_t                    ContinuousMode)
01904 {
01905   HAL_StatusTypeDef status = HAL_OK;
01906
01907   /* Check parameters */
01908   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01909   assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
01910   assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
01911
01912   /* Check DFSDM filter state */
01913   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01914      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01915   {
01916     /* Configure channel and continuous mode for regular conversion */
01917     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
01918     if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
01919     {
01920       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
01921                                                      DFSDM_FLTCR1_RCONT);
01922     }
01923     else
01924     {
01925       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
01926     }
01927     /* Store continuous mode information */
01928     hdfsdm_filter->RegularContMode = ContinuousMode;
01929   }
01930   else
01931   {
01932     status = HAL_ERROR;
01933   }
01934
01935   /* Return function status */
01936   return status;
01937 }
01938
01939 /**
01940   * @brief  This function allows to select channels for injected conversion.
01941   * @param  hdfsdm_filter DFSDM filter handle.
01942   * @param  Channel Channels for injected conversion.
01943   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
01944   * @retval HAL status
01945   */
01946 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01947                                                    uint32_t                    Channel)
01948 {
01949   HAL_StatusTypeDef status = HAL_OK;
01950
01951   /* Check parameters */
01952   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01953   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
01954
01955   /* Check DFSDM filter state */
01956   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01957      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01958   {
01959     /* Configure channel for injected conversion */
01960     hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
01961     /* Store number of injected channels */
01962     hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
01963     /* Update number of injected channels remaining */
01964     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
01965                                        hdfsdm_filter->InjectedChannelsNbr : 1U;
01966   }
01967   else
01968   {
01969     status = HAL_ERROR;
01970   }
01971   /* Return function status */
01972   return status;
01973 }
01974
01975 /**
01976   * @}
01977   */
01978
01979 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
01980  *  @brief    Filter operation functions
01981  *
01982 @verbatim
01983   ==============================================================================
01984                     ##### Filter operation functions #####
01985   ==============================================================================
01986     [..]  This section provides functions allowing to:
01987       (+) Start conversion of regular/injected channel.
01988       (+) Poll for the end of regular/injected conversion.
01989       (+) Stop conversion of regular/injected channel.
01990       (+) Start conversion of regular/injected channel and enable interrupt.
01991       (+) Call the callback functions at the end of regular/injected conversions.
01992       (+) Stop conversion of regular/injected channel and disable interrupt.
01993       (+) Start conversion of regular/injected channel and enable DMA transfer.
01994       (+) Stop conversion of regular/injected channel and disable DMA transfer.
01995       (+) Start analog watchdog and enable interrupt.
01996       (+) Call the callback function when analog watchdog occurs.
01997       (+) Stop analog watchdog and disable interrupt.
01998       (+) Start extreme detector.
01999       (+) Stop extreme detector.
02000       (+) Get result of regular channel conversion.
02001       (+) Get result of injected channel conversion.
02002       (+) Get extreme detector maximum and minimum values.
02003       (+) Get conversion time.
02004       (+) Handle DFSDM interrupt request.
02005 @endverbatim
02006   * @{
02007   */
02008
02009 /**
02010   * @brief  This function allows to start regular conversion in polling mode.
02011   * @note   This function should be called only when DFSDM filter instance is
02012   *         in idle state or if injected conversion is ongoing.
02013   * @param  hdfsdm_filter DFSDM filter handle.
02014   * @retval HAL status
02015   */
02016 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02017 {
02018   HAL_StatusTypeDef status = HAL_OK;
02019
02020   /* Check parameters */
02021   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02022
02023   /* Check DFSDM filter state */
02024   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02025      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
02026   {
02027     /* Start regular conversion */
02028     DFSDM_RegConvStart(hdfsdm_filter);
02029   }
02030   else
02031   {
02032     status = HAL_ERROR;
02033   }
02034   /* Return function status */
02035   return status;
02036 }
02037
02038 /**
02039   * @brief  This function allows to poll for the end of regular conversion.
02040   * @note   This function should be called only if regular conversion is ongoing.
02041   * @param  hdfsdm_filter DFSDM filter handle.
02042   * @param  Timeout Timeout value in milliseconds.
02043   * @retval HAL status
02044   */
02045 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02046                                                        uint32_t                    Timeout)
02047 {
02048   uint32_t tickstart;
02049
02050   /* Check parameters */
02051   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02052
02053   /* Check DFSDM filter state */
02054   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
02055      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02056   {
02057     /* Return error status */
02058     return HAL_ERROR;
02059   }
02060   else
02061   {
02062     /* Get timeout */
02063     tickstart = HAL_GetTick();
02064
02065     /* Wait end of regular conversion */
02066     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
02067     {
02068       /* Check the Timeout */
02069       if(Timeout != HAL_MAX_DELAY)
02070       {
02071         if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02072         {
02073           /* Return timeout status */
02074           return HAL_TIMEOUT;
02075         }
02076       }
02077     }
02078     /* Check if overrun occurs */
02079     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
02080     {
02081       /* Update error code and call error callback */
02082       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
02083 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
02084       hdfsdm_filter->ErrorCallback(hdfsdm_filter);
02085 #else
02086       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02087 #endif
02088
02089       /* Clear regular overrun flag */
02090       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
02091     }
02092     /* Update DFSDM filter state only if not continuous conversion and SW trigger */
02093     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02094        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02095     {
02096       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
02097                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
02098     }
02099     /* Return function status */
02100     return HAL_OK;
02101   }
02102 }
02103
02104 /**
02105   * @brief  This function allows to stop regular conversion in polling mode.
02106   * @note   This function should be called only if regular conversion is ongoing.
02107   * @param  hdfsdm_filter DFSDM filter handle.
02108   * @retval HAL status
02109   */
02110 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02111 {
02112   HAL_StatusTypeDef status = HAL_OK;
02113
02114   /* Check parameters */
02115   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02116
02117   /* Check DFSDM filter state */
02118   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
02119      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02120   {
02121     /* Return error status */
02122     status = HAL_ERROR;
02123   }
02124   else
02125   {
02126     /* Stop regular conversion */
02127     DFSDM_RegConvStop(hdfsdm_filter);
02128   }
02129   /* Return function status */
02130   return status;
02131 }
02132
02133 /**
02134   * @brief  This function allows to start regular conversion in interrupt mode.
02135   * @note   This function should be called only when DFSDM filter instance is
02136   *         in idle state or if injected conversion is ongoing.
02137   * @param  hdfsdm_filter DFSDM filter handle.
02138   * @retval HAL status
02139   */
02140 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02141 {
02142   HAL_StatusTypeDef status = HAL_OK;
02143
02144   /* Check parameters */
02145   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02146
02147   /* Check DFSDM filter state */
02148   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02149      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
02150   {
02151     /* Enable interrupts for regular conversions */
02152     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
02153
02154     /* Start regular conversion */
02155     DFSDM_RegConvStart(hdfsdm_filter);
02156   }
02157   else
02158   {
02159     status = HAL_ERROR;
02160   }
02161   /* Return function status */
02162   return status;
02163 }
02164
02165 /**
02166   * @brief  This function allows to stop regular conversion in interrupt mode.
02167   * @note   This function should be called only if regular conversion is ongoing.
02168   * @param  hdfsdm_filter DFSDM filter handle.
02169   * @retval HAL status
02170   */
02171 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02172 {
02173   HAL_StatusTypeDef status = HAL_OK;
02174
02175   /* Check parameters */
02176   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02177
02178   /* Check DFSDM filter state */
02179   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
02180      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02181   {
02182     /* Return error status */
02183     status = HAL_ERROR;
02184   }
02185   else
02186   {
02187     /* Disable interrupts for regular conversions */
02188     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
02189
02190     /* Stop regular conversion */
02191     DFSDM_RegConvStop(hdfsdm_filter);
02192   }
02193   /* Return function status */
02194   return status;
02195 }
02196
02197 /**
02198   * @brief  This function allows to start regular conversion in DMA mode.
02199   * @note   This function should be called only when DFSDM filter instance is
02200   *         in idle state or if injected conversion is ongoing.
02201   *         Please note that data on buffer will contain signed regular conversion
02202   *         value on 24 most significant bits and corresponding channel on 3 least
02203   *         significant bits.
02204   * @param  hdfsdm_filter DFSDM filter handle.
02205   * @param  pData The destination buffer address.
02206   * @param  Length The length of data to be transferred from DFSDM filter to memory.
02207   * @retval HAL status
02208   */
02209 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02210                                                    int32_t                    *pData,
02211                                                    uint32_t                    Length)
02212 {
02213   HAL_StatusTypeDef status = HAL_OK;
02214
02215   /* Check parameters */
02216   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02217
02218   /* Check destination address and length */
02219   if((pData == NULL) || (Length == 0U))
02220   {
02221     status = HAL_ERROR;
02222   }
02223   /* Check that DMA is enabled for regular conversion */
02224   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
02225   {
02226     status = HAL_ERROR;
02227   }
02228   /* Check parameters compatibility */
02229   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02230           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02231           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
02232           (Length != 1U))
02233   {
02234     status = HAL_ERROR;
02235   }
02236   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02237           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02238           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
02239   {
02240     status = HAL_ERROR;
02241   }
02242   /* Check DFSDM filter state */
02243   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02244           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
02245   {
02246     /* Set callbacks on DMA handler */
02247     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
02248     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
02249     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
02250                                                    DFSDM_DMARegularHalfConvCplt : NULL;
02251
02252     /* Start DMA in interrupt mode */
02253     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
02254                         (uint32_t) pData, Length) != HAL_OK)
02255     {
02256       /* Set DFSDM filter in error state */
02257       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02258       status = HAL_ERROR;
02259     }
02260     else
02261     {
02262       /* Start regular conversion */
02263       DFSDM_RegConvStart(hdfsdm_filter);
02264     }
02265   }
02266   else
02267   {
02268     status = HAL_ERROR;
02269   }
02270   /* Return function status */
02271   return status;
02272 }
02273
02274 /**
02275   * @brief  This function allows to start regular conversion in DMA mode and to get
02276   *         only the 16 most significant bits of conversion.
02277   * @note   This function should be called only when DFSDM filter instance is
02278   *         in idle state or if injected conversion is ongoing.
02279   *         Please note that data on buffer will contain signed 16 most significant
02280   *         bits of regular conversion.
02281   * @param  hdfsdm_filter DFSDM filter handle.
02282   * @param  pData The destination buffer address.
02283   * @param  Length The length of data to be transferred from DFSDM filter to memory.
02284   * @retval HAL status
02285   */
02286 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02287                                                       int16_t                    *pData,
02288                                                       uint32_t                    Length)
02289 {
02290   HAL_StatusTypeDef status = HAL_OK;
02291
02292   /* Check parameters */
02293   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02294
02295   /* Check destination address and length */
02296   if((pData == NULL) || (Length == 0U))
02297   {
02298     status = HAL_ERROR;
02299   }
02300   /* Check that DMA is enabled for regular conversion */
02301   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
02302   {
02303     status = HAL_ERROR;
02304   }
02305   /* Check parameters compatibility */
02306   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02307           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02308           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
02309           (Length != 1U))
02310   {
02311     status = HAL_ERROR;
02312   }
02313   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02314           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02315           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
02316   {
02317     status = HAL_ERROR;
02318   }
02319   /* Check DFSDM filter state */
02320   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02321           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
02322   {
02323     /* Set callbacks on DMA handler */
02324     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
02325     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
02326     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
02327                                                    DFSDM_DMARegularHalfConvCplt : NULL;
02328
02329     /* Start DMA in interrupt mode */
02330     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
02331                         (uint32_t) pData, Length) != HAL_OK)
02332     {
02333       /* Set DFSDM filter in error state */
02334       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02335       status = HAL_ERROR;
02336     }
02337     else
02338     {
02339       /* Start regular conversion */
02340       DFSDM_RegConvStart(hdfsdm_filter);
02341     }
02342   }
02343   else
02344   {
02345     status = HAL_ERROR;
02346   }
02347   /* Return function status */
02348   return status;
02349 }
02350
02351 /**
02352   * @brief  This function allows to stop regular conversion in DMA mode.
02353   * @note   This function should be called only if regular conversion is ongoing.
02354   * @param  hdfsdm_filter DFSDM filter handle.
02355   * @retval HAL status
02356   */
02357 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02358 {
02359   HAL_StatusTypeDef status = HAL_OK;
02360
02361   /* Check parameters */
02362   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02363
02364   /* Check DFSDM filter state */
02365   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
02366      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02367   {
02368     /* Return error status */
02369     status = HAL_ERROR;
02370   }
02371   else
02372   {
02373     /* Stop current DMA transfer */
02374     if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
02375     {
02376       /* Set DFSDM filter in error state */
02377       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02378       status = HAL_ERROR;
02379     }
02380     else
02381     {
02382       /* Stop regular conversion */
02383       DFSDM_RegConvStop(hdfsdm_filter);
02384     }
02385   }
02386   /* Return function status */
02387   return status;
02388 }
02389
02390 /**
02391   * @brief  This function allows to get regular conversion value.
02392   * @param  hdfsdm_filter DFSDM filter handle.
02393   * @param  Channel Corresponding channel of regular conversion.
02394   * @retval Regular conversion value
02395   */
02396 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02397                                         uint32_t                   *Channel)
02398 {
02399   uint32_t reg;
02400   int32_t  value;
02401
02402   /* Check parameters */
02403   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02404   assert_param(Channel != (void *)0);
02405
02406   /* Get value of data register for regular channel */
02407   reg = hdfsdm_filter->Instance->FLTRDATAR;
02408
02409   /* Extract channel and regular conversion value */
02410   *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
02411   /* Regular conversion value is a signed value located on 24 MSB of register */
02412   /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */
02413   reg &= DFSDM_FLTRDATAR_RDATA;
02414   value = ((int32_t)reg) / 256;
02415
02416   /* return regular conversion value */
02417   return value;
02418 }
02419
02420 /**
02421   * @brief  This function allows to start injected conversion in polling mode.
02422   * @note   This function should be called only when DFSDM filter instance is
02423   *         in idle state or if regular conversion is ongoing.
02424   * @param  hdfsdm_filter DFSDM filter handle.
02425   * @retval HAL status
02426   */
02427 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02428 {
02429   HAL_StatusTypeDef status = HAL_OK;
02430
02431   /* Check parameters */
02432   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02433
02434   /* Check DFSDM filter state */
02435   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02436      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02437   {
02438     /* Start injected conversion */
02439     DFSDM_InjConvStart(hdfsdm_filter);
02440   }
02441   else
02442   {
02443     status = HAL_ERROR;
02444   }
02445   /* Return function status */
02446   return status;
02447 }
02448
02449 /**
02450   * @brief  This function allows to poll for the end of injected conversion.
02451   * @note   This function should be called only if injected conversion is ongoing.
02452   * @param  hdfsdm_filter DFSDM filter handle.
02453   * @param  Timeout Timeout value in milliseconds.
02454   * @retval HAL status
02455   */
02456 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02457                                                        uint32_t                    Timeout)
02458 {
02459   uint32_t tickstart;
02460
02461   /* Check parameters */
02462   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02463
02464   /* Check DFSDM filter state */
02465   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02466      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02467   {
02468     /* Return error status */
02469     return HAL_ERROR;
02470   }
02471   else
02472   {
02473     /* Get timeout */
02474     tickstart = HAL_GetTick();
02475
02476     /* Wait end of injected conversions */
02477     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
02478     {
02479       /* Check the Timeout */
02480       if(Timeout != HAL_MAX_DELAY)
02481       {
02482         if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02483         {
02484           /* Return timeout status */
02485           return HAL_TIMEOUT;
02486         }
02487       }
02488     }
02489     /* Check if overrun occurs */
02490     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
02491     {
02492       /* Update error code and call error callback */
02493       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
02494 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
02495       hdfsdm_filter->ErrorCallback(hdfsdm_filter);
02496 #else
02497       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02498 #endif
02499
02500       /* Clear injected overrun flag */
02501       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
02502     }
02503
02504     /* Update remaining injected conversions */
02505     hdfsdm_filter->InjConvRemaining--;
02506     if(hdfsdm_filter->InjConvRemaining == 0U)
02507     {
02508       /* Update DFSDM filter state only if trigger is software */
02509       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02510       {
02511         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
02512                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
02513       }
02514
02515       /* end of injected sequence, reset the value */
02516       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02517                                          hdfsdm_filter->InjectedChannelsNbr : 1U;
02518     }
02519
02520     /* Return function status */
02521     return HAL_OK;
02522   }
02523 }
02524
02525 /**
02526   * @brief  This function allows to stop injected conversion in polling mode.
02527   * @note   This function should be called only if injected conversion is ongoing.
02528   * @param  hdfsdm_filter DFSDM filter handle.
02529   * @retval HAL status
02530   */
02531 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02532 {
02533   HAL_StatusTypeDef status = HAL_OK;
02534
02535   /* Check parameters */
02536   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02537
02538   /* Check DFSDM filter state */
02539   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02540      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02541   {
02542     /* Return error status */
02543     status = HAL_ERROR;
02544   }
02545   else
02546   {
02547     /* Stop injected conversion */
02548     DFSDM_InjConvStop(hdfsdm_filter);
02549   }
02550   /* Return function status */
02551   return status;
02552 }
02553
02554 /**
02555   * @brief  This function allows to start injected conversion in interrupt mode.
02556   * @note   This function should be called only when DFSDM filter instance is
02557   *         in idle state or if regular conversion is ongoing.
02558   * @param  hdfsdm_filter DFSDM filter handle.
02559   * @retval HAL status
02560   */
02561 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02562 {
02563   HAL_StatusTypeDef status = HAL_OK;
02564
02565   /* Check parameters */
02566   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02567
02568   /* Check DFSDM filter state */
02569   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02570      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02571   {
02572     /* Enable interrupts for injected conversions */
02573     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
02574
02575     /* Start injected conversion */
02576     DFSDM_InjConvStart(hdfsdm_filter);
02577   }
02578   else
02579   {
02580     status = HAL_ERROR;
02581   }
02582   /* Return function status */
02583   return status;
02584 }
02585
02586 /**
02587   * @brief  This function allows to stop injected conversion in interrupt mode.
02588   * @note   This function should be called only if injected conversion is ongoing.
02589   * @param  hdfsdm_filter DFSDM filter handle.
02590   * @retval HAL status
02591   */
02592 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02593 {
02594   HAL_StatusTypeDef status = HAL_OK;
02595
02596   /* Check parameters */
02597   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02598
02599   /* Check DFSDM filter state */
02600   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02601      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02602   {
02603     /* Return error status */
02604     status = HAL_ERROR;
02605   }
02606   else
02607   {
02608     /* Disable interrupts for injected conversions */
02609     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
02610
02611     /* Stop injected conversion */
02612     DFSDM_InjConvStop(hdfsdm_filter);
02613   }
02614   /* Return function status */
02615   return status;
02616 }
02617
02618 /**
02619   * @brief  This function allows to start injected conversion in DMA mode.
02620   * @note   This function should be called only when DFSDM filter instance is
02621   *         in idle state or if regular conversion is ongoing.
02622   *         Please note that data on buffer will contain signed injected conversion
02623   *         value on 24 most significant bits and corresponding channel on 3 least
02624   *         significant bits.
02625   * @param  hdfsdm_filter DFSDM filter handle.
02626   * @param  pData The destination buffer address.
02627   * @param  Length The length of data to be transferred from DFSDM filter to memory.
02628   * @retval HAL status
02629   */
02630 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02631                                                     int32_t                    *pData,
02632                                                     uint32_t                    Length)
02633 {
02634   HAL_StatusTypeDef status = HAL_OK;
02635
02636   /* Check parameters */
02637   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02638
02639   /* Check destination address and length */
02640   if((pData == NULL) || (Length == 0U))
02641   {
02642     status = HAL_ERROR;
02643   }
02644   /* Check that DMA is enabled for injected conversion */
02645   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
02646   {
02647     status = HAL_ERROR;
02648   }
02649   /* Check parameters compatibility */
02650   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02651           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
02652           (Length > hdfsdm_filter->InjConvRemaining))
02653   {
02654     status = HAL_ERROR;
02655   }
02656   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02657           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
02658   {
02659     status = HAL_ERROR;
02660   }
02661   /* Check DFSDM filter state */
02662   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02663           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02664   {
02665     /* Set callbacks on DMA handler */
02666     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
02667     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
02668     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
02669                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
02670
02671     /* Start DMA in interrupt mode */
02672     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
02673                         (uint32_t) pData, Length) != HAL_OK)
02674     {
02675       /* Set DFSDM filter in error state */
02676       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02677       status = HAL_ERROR;
02678     }
02679     else
02680     {
02681       /* Start injected conversion */
02682       DFSDM_InjConvStart(hdfsdm_filter);
02683     }
02684   }
02685   else
02686   {
02687     status = HAL_ERROR;
02688   }
02689   /* Return function status */
02690   return status;
02691 }
02692
02693 /**
02694   * @brief  This function allows to start injected conversion in DMA mode and to get
02695   *         only the 16 most significant bits of conversion.
02696   * @note   This function should be called only when DFSDM filter instance is
02697   *         in idle state or if regular conversion is ongoing.
02698   *         Please note that data on buffer will contain signed 16 most significant
02699   *         bits of injected conversion.
02700   * @param  hdfsdm_filter DFSDM filter handle.
02701   * @param  pData The destination buffer address.
02702   * @param  Length The length of data to be transferred from DFSDM filter to memory.
02703   * @retval HAL status
02704   */
02705 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02706                                                        int16_t                    *pData,
02707                                                        uint32_t                    Length)
02708 {
02709   HAL_StatusTypeDef status = HAL_OK;
02710
02711   /* Check parameters */
02712   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02713
02714   /* Check destination address and length */
02715   if((pData == NULL) || (Length == 0U))
02716   {
02717     status = HAL_ERROR;
02718   }
02719   /* Check that DMA is enabled for injected conversion */
02720   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
02721   {
02722     status = HAL_ERROR;
02723   }
02724   /* Check parameters compatibility */
02725   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02726           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
02727           (Length > hdfsdm_filter->InjConvRemaining))
02728   {
02729     status = HAL_ERROR;
02730   }
02731   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02732           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
02733   {
02734     status = HAL_ERROR;
02735   }
02736   /* Check DFSDM filter state */
02737   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02738           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02739   {
02740     /* Set callbacks on DMA handler */
02741     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
02742     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
02743     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
02744                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
02745
02746     /* Start DMA in interrupt mode */
02747     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
02748                         (uint32_t) pData, Length) != HAL_OK)
02749     {
02750       /* Set DFSDM filter in error state */
02751       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02752       status = HAL_ERROR;
02753     }
02754     else
02755     {
02756       /* Start injected conversion */
02757       DFSDM_InjConvStart(hdfsdm_filter);
02758     }
02759   }
02760   else
02761   {
02762     status = HAL_ERROR;
02763   }
02764   /* Return function status */
02765   return status;
02766 }
02767
02768 /**
02769   * @brief  This function allows to stop injected conversion in DMA mode.
02770   * @note   This function should be called only if injected conversion is ongoing.
02771   * @param  hdfsdm_filter DFSDM filter handle.
02772   * @retval HAL status
02773   */
02774 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02775 {
02776   HAL_StatusTypeDef status = HAL_OK;
02777
02778   /* Check parameters */
02779   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02780
02781   /* Check DFSDM filter state */
02782   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02783      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02784   {
02785     /* Return error status */
02786     status = HAL_ERROR;
02787   }
02788   else
02789   {
02790     /* Stop current DMA transfer */
02791     if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
02792     {
02793       /* Set DFSDM filter in error state */
02794       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02795       status = HAL_ERROR;
02796     }
02797     else
02798     {
02799       /* Stop regular conversion */
02800       DFSDM_InjConvStop(hdfsdm_filter);
02801     }
02802   }
02803   /* Return function status */
02804   return status;
02805 }
02806
02807 /**
02808   * @brief  This function allows to get injected conversion value.
02809   * @param  hdfsdm_filter DFSDM filter handle.
02810   * @param  Channel Corresponding channel of injected conversion.
02811   * @retval Injected conversion value
02812   */
02813 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02814                                          uint32_t                   *Channel)
02815 {
02816   uint32_t reg;
02817   int32_t  value;
02818
02819   /* Check parameters */
02820   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02821   assert_param(Channel != (void *)0);
02822
02823   /* Get value of data register for injected channel */
02824   reg = hdfsdm_filter->Instance->FLTJDATAR;
02825
02826   /* Extract channel and injected conversion value */
02827   *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
02828   /* Injected conversion value is a signed value located on 24 MSB of register */
02829   /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */
02830   reg &= DFSDM_FLTJDATAR_JDATA;
02831   value = ((int32_t)reg) / 256;
02832
02833   /* return regular conversion value */
02834   return value;
02835 }
02836
02837 /**
02838   * @brief  This function allows to start filter analog watchdog in interrupt mode.
02839   * @param  hdfsdm_filter DFSDM filter handle.
02840   * @param  awdParam DFSDM filter analog watchdog parameters.
02841   * @retval HAL status
02842   */
02843 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
02844                                               DFSDM_Filter_AwdParamTypeDef *awdParam)
02845 {
02846   HAL_StatusTypeDef status = HAL_OK;
02847
02848   /* Check parameters */
02849   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02850   assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
02851   assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
02852   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
02853   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
02854   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
02855   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
02856
02857   /* Check DFSDM filter state */
02858   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02859      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02860   {
02861     /* Return error status */
02862     status = HAL_ERROR;
02863   }
02864   else
02865   {
02866     /* Set analog watchdog data source */
02867     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02868     hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
02869
02870     /* Set thresholds and break signals */
02871     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02872     hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
02873                                           awdParam->HighBreakSignal);
02874     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02875     hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
02876                                           awdParam->LowBreakSignal);
02877
02878     /* Set channels and interrupt for analog watchdog */
02879     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
02880     hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
02881                                         DFSDM_FLTCR2_AWDIE);
02882   }
02883   /* Return function status */
02884   return status;
02885 }
02886
02887 /**
02888   * @brief  This function allows to stop filter analog watchdog in interrupt mode.
02889   * @param  hdfsdm_filter DFSDM filter handle.
02890   * @retval HAL status
02891   */
02892 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02893 {
02894   HAL_StatusTypeDef status = HAL_OK;
02895
02896   /* Check parameters */
02897   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02898
02899   /* Check DFSDM filter state */
02900   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02901      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02902   {
02903     /* Return error status */
02904     status = HAL_ERROR;
02905   }
02906   else
02907   {
02908     /* Reset channels for analog watchdog and deactivate interrupt */
02909     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
02910
02911     /* Clear all analog watchdog flags */
02912     hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
02913
02914     /* Reset thresholds and break signals */
02915     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02916     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02917
02918     /* Reset analog watchdog data source */
02919     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02920   }
02921   /* Return function status */
02922   return status;
02923 }
02924
02925 /**
02926   * @brief  This function allows to start extreme detector feature.
02927   * @param  hdfsdm_filter DFSDM filter handle.
02928   * @param  Channel Channels where extreme detector is enabled.
02929   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
02930   * @retval HAL status
02931   */
02932 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02933                                            uint32_t                    Channel)
02934 {
02935   HAL_StatusTypeDef status = HAL_OK;
02936
02937   /* Check parameters */
02938   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02939   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
02940
02941   /* Check DFSDM filter state */
02942   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02943      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02944   {
02945     /* Return error status */
02946     status = HAL_ERROR;
02947   }
02948   else
02949   {
02950     /* Set channels for extreme detector */
02951     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02952     hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
02953   }
02954   /* Return function status */
02955   return status;
02956 }
02957
02958 /**
02959   * @brief  This function allows to stop extreme detector feature.
02960   * @param  hdfsdm_filter DFSDM filter handle.
02961   * @retval HAL status
02962   */
02963 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02964 {
02965   HAL_StatusTypeDef status = HAL_OK;
02966   __IO uint32_t     reg1;
02967   __IO uint32_t     reg2;
02968
02969   /* Check parameters */
02970   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02971
02972   /* Check DFSDM filter state */
02973   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02974      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02975   {
02976     /* Return error status */
02977     status = HAL_ERROR;
02978   }
02979   else
02980   {
02981     /* Reset channels for extreme detector */
02982     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02983
02984     /* Clear extreme detector values */
02985     reg1 = hdfsdm_filter->Instance->FLTEXMAX;
02986     reg2 = hdfsdm_filter->Instance->FLTEXMIN;
02987     UNUSED(reg1); /* To avoid GCC warning */
02988     UNUSED(reg2); /* To avoid GCC warning */
02989   }
02990   /* Return function status */
02991   return status;
02992 }
02993
02994 /**
02995   * @brief  This function allows to get extreme detector maximum value.
02996   * @param  hdfsdm_filter DFSDM filter handle.
02997   * @param  Channel Corresponding channel.
02998   * @retval Extreme detector maximum value
02999   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
03000   */
03001 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
03002                                        uint32_t                   *Channel)
03003 {
03004   uint32_t reg;
03005   int32_t  value;
03006
03007   /* Check parameters */
03008   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
03009   assert_param(Channel != (void *)0);
03010
03011   /* Get value of extreme detector maximum register */
03012   reg = hdfsdm_filter->Instance->FLTEXMAX;
03013
03014   /* Extract channel and extreme detector maximum value */
03015   *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
03016   /* Extreme detector maximum value is a signed value located on 24 MSB of register */
03017   /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */
03018   reg &= DFSDM_FLTEXMAX_EXMAX;
03019   value = ((int32_t)reg) / 256;
03020
03021   /* return extreme detector maximum value */
03022   return value;
03023 }
03024
03025 /**
03026   * @brief  This function allows to get extreme detector minimum value.
03027   * @param  hdfsdm_filter DFSDM filter handle.
03028   * @param  Channel Corresponding channel.
03029   * @retval Extreme detector minimum value
03030   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
03031   */
03032 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
03033                                        uint32_t                   *Channel)
03034 {
03035   uint32_t reg;
03036   int32_t  value;
03037
03038   /* Check parameters */
03039   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
03040   assert_param(Channel != (void *)0);
03041
03042   /* Get value of extreme detector minimum register */
03043   reg = hdfsdm_filter->Instance->FLTEXMIN;
03044
03045   /* Extract channel and extreme detector minimum value */
03046   *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
03047   /* Extreme detector minimum value is a signed value located on 24 MSB of register */
03048   /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */
03049   reg &= DFSDM_FLTEXMIN_EXMIN;
03050   value = ((int32_t)reg) / 256;
03051
03052   /* return extreme detector minimum value */
03053   return value;
03054 }
03055
03056 /**
03057   * @brief  This function allows to get conversion time value.
03058   * @param  hdfsdm_filter DFSDM filter handle.
03059   * @retval Conversion time value
03060   * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
03061   */
03062 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03063 {
03064   uint32_t reg;
03065   uint32_t value;
03066
03067   /* Check parameters */
03068   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
03069
03070   /* Get value of conversion timer register */
03071   reg = hdfsdm_filter->Instance->FLTCNVTIMR;
03072
03073   /* Extract conversion time value */
03074   value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
03075
03076   /* return extreme detector minimum value */
03077   return value;
03078 }
03079
03080 /**
03081   * @brief  This function handles the DFSDM interrupts.
03082   * @param  hdfsdm_filter DFSDM filter handle.
03083   * @retval None
03084   */
03085 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03086 {
03087   DFSDM_Channel_HandleTypeDef **channelHandleTable;
03088   const DFSDM_Filter_TypeDef   *filter0Instance;
03089   uint32_t channelNumber;
03090
03091   /* Get FTLISR and FLTCR2 register values */
03092   const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR;
03093   const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2;
03094
03095 #if defined(DFSDM2_Channel0)
03096   if (IS_DFSDM1_FILTER_INSTANCE(hdfsdm_filter->Instance))
03097   {
03098     channelHandleTable = a_dfsdm1ChannelHandle;
03099     filter0Instance    = DFSDM1_Filter0;
03100     channelNumber      = DFSDM1_CHANNEL_NUMBER;
03101   }
03102   else
03103   {
03104     channelHandleTable = a_dfsdm2ChannelHandle;
03105     filter0Instance    = DFSDM2_Filter0;
03106     channelNumber      = DFSDM2_CHANNEL_NUMBER;
03107   }
03108 #else /* DFSDM2_Channel0 */
03109   channelHandleTable = a_dfsdm1ChannelHandle;
03110   filter0Instance    = DFSDM1_Filter0;
03111   channelNumber      = DFSDM1_CHANNEL_NUMBER;
03112 #endif /* DFSDM2_Channel0 */
03113
03114   /* Check if overrun occurs during regular conversion */
03115   if(((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \
03116      ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))
03117   {
03118     /* Clear regular overrun flag */
03119     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
03120
03121     /* Update error code */
03122     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
03123
03124     /* Call error callback */
03125 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03126     hdfsdm_filter->ErrorCallback(hdfsdm_filter);
03127 #else
03128     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
03129 #endif
03130   }
03131   /* Check if overrun occurs during injected conversion */
03132   else if(((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \
03133           ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))
03134   {
03135     /* Clear injected overrun flag */
03136     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
03137
03138     /* Update error code */
03139     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
03140
03141     /* Call error callback */
03142 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03143     hdfsdm_filter->ErrorCallback(hdfsdm_filter);
03144 #else
03145     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
03146 #endif
03147   }
03148   /* Check if end of regular conversion */
03149   else if(((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \
03150           ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
03151   {
03152     /* Call regular conversion complete callback */
03153 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03154     hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
03155 #else
03156     HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
03157 #endif
03158
03159     /* End of conversion if mode is not continuous and software trigger */
03160     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
03161        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
03162     {
03163       /* Disable interrupts for regular conversions */
03164       hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
03165
03166       /* Update DFSDM filter state */
03167       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
03168                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
03169     }
03170   }
03171   /* Check if end of injected conversion */
03172   else if(((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \
03173           ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
03174   {
03175     /* Call injected conversion complete callback */
03176 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03177     hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
03178 #else
03179     HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
03180 #endif
03181
03182     /* Update remaining injected conversions */
03183     hdfsdm_filter->InjConvRemaining--;
03184     if(hdfsdm_filter->InjConvRemaining == 0U)
03185     {
03186       /* End of conversion if trigger is software */
03187       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
03188       {
03189         /* Disable interrupts for injected conversions */
03190         hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
03191
03192         /* Update DFSDM filter state */
03193         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
03194                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
03195       }
03196       /* end of injected sequence, reset the value */
03197       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
03198                                          hdfsdm_filter->InjectedChannelsNbr : 1U;
03199     }
03200   }
03201   /* Check if analog watchdog occurs */
03202   else if(((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \
03203           ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))
03204   {
03205     uint32_t reg;
03206     uint32_t threshold;
03207     uint32_t channel = 0;
03208
03209     /* Get channel and threshold */
03210     reg = hdfsdm_filter->Instance->FLTAWSR;
03211     threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
03212     if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
03213     {
03214       reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
03215     }
03216     while (((reg & 1U) == 0U) && (channel < (channelNumber - 1U)))
03217     {
03218       channel++;
03219       reg = reg >> 1;
03220     }
03221     /* Clear analog watchdog flag */
03222     hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
03223                                         (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
03224                                         (1UL << channel);
03225
03226     /* Call analog watchdog callback */
03227 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03228     hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
03229 #else
03230     HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
03231 #endif
03232   }
03233   /* Check if clock absence occurs */
03234   else if((hdfsdm_filter->Instance == filter0Instance) && \
03235          ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \
03236          ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))
03237   {
03238     uint32_t reg;
03239     uint32_t channel = 0;
03240
03241     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
03242
03243     while (channel < channelNumber)
03244     {
03245       /* Check if flag is set and corresponding channel is enabled */
03246       if (((reg & 1U) != 0U) && (channelHandleTable[channel] != NULL))
03247       {
03248         /* Check clock absence has been enabled for this channel */
03249         if ((channelHandleTable[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
03250         {
03251           /* Clear clock absence flag */
03252           hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
03253
03254           /* Call clock absence callback */
03255 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03256           channelHandleTable[channel]->CkabCallback(channelHandleTable[channel]);
03257 #else
03258           HAL_DFSDM_ChannelCkabCallback(channelHandleTable[channel]);
03259 #endif
03260         }
03261       }
03262       channel++;
03263       reg = reg >> 1;
03264     }
03265   }
03266   /* Check if short circuit detection occurs */
03267   else if((hdfsdm_filter->Instance == filter0Instance) && \
03268          ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \
03269          ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))
03270   {
03271     uint32_t reg;
03272     uint32_t channel = 0;
03273
03274     /* Get channel */
03275     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
03276     while (((reg & 1U) == 0U) && (channel < (channelNumber - 1U)))
03277     {
03278       channel++;
03279       reg = reg >> 1;
03280     }
03281
03282     /* Clear short circuit detection flag */
03283     hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
03284
03285     /* Call short circuit detection callback */
03286 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03287     channelHandleTable[channel]->ScdCallback(channelHandleTable[channel]);
03288 #else
03289     HAL_DFSDM_ChannelScdCallback(channelHandleTable[channel]);
03290 #endif
03291   }
03292 }
03293
03294 /**
03295   * @brief  Regular conversion complete callback.
03296   * @note   In interrupt mode, user has to read conversion value in this function
03297   *         using HAL_DFSDM_FilterGetRegularValue.
03298   * @param  hdfsdm_filter DFSDM filter handle.
03299   * @retval None
03300   */
03301 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03302 {
03303   /* Prevent unused argument(s) compilation warning */
03304   UNUSED(hdfsdm_filter);
03305
03306   /* NOTE : This function should not be modified, when the callback is needed,
03307             the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
03308    */
03309 }
03310
03311 /**
03312   * @brief  Half regular conversion complete callback.
03313   * @param  hdfsdm_filter DFSDM filter handle.
03314   * @retval None
03315   */
03316 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03317 {
03318   /* Prevent unused argument(s) compilation warning */
03319   UNUSED(hdfsdm_filter);
03320
03321   /* NOTE : This function should not be modified, when the callback is needed,
03322             the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
03323    */
03324 }
03325
03326 /**
03327   * @brief  Injected conversion complete callback.
03328   * @note   In interrupt mode, user has to read conversion value in this function
03329   *         using HAL_DFSDM_FilterGetInjectedValue.
03330   * @param  hdfsdm_filter DFSDM filter handle.
03331   * @retval None
03332   */
03333 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03334 {
03335   /* Prevent unused argument(s) compilation warning */
03336   UNUSED(hdfsdm_filter);
03337
03338   /* NOTE : This function should not be modified, when the callback is needed,
03339             the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
03340    */
03341 }
03342
03343 /**
03344   * @brief  Half injected conversion complete callback.
03345   * @param  hdfsdm_filter DFSDM filter handle.
03346   * @retval None
03347   */
03348 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03349 {
03350   /* Prevent unused argument(s) compilation warning */
03351   UNUSED(hdfsdm_filter);
03352
03353   /* NOTE : This function should not be modified, when the callback is needed,
03354             the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
03355    */
03356 }
03357
03358 /**
03359   * @brief  Filter analog watchdog callback.
03360   * @param  hdfsdm_filter DFSDM filter handle.
03361   * @param  Channel Corresponding channel.
03362   * @param  Threshold Low or high threshold has been reached.
03363   * @retval None
03364   */
03365 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
03366                                         uint32_t Channel, uint32_t Threshold)
03367 {
03368   /* Prevent unused argument(s) compilation warning */
03369   UNUSED(hdfsdm_filter);
03370   UNUSED(Channel);
03371   UNUSED(Threshold);
03372
03373   /* NOTE : This function should not be modified, when the callback is needed,
03374             the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
03375    */
03376 }
03377
03378 /**
03379   * @brief  Error callback.
03380   * @param  hdfsdm_filter DFSDM filter handle.
03381   * @retval None
03382   */
03383 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03384 {
03385   /* Prevent unused argument(s) compilation warning */
03386   UNUSED(hdfsdm_filter);
03387
03388   /* NOTE : This function should not be modified, when the callback is needed,
03389             the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
03390    */
03391 }
03392
03393 /**
03394   * @}
03395   */
03396
03397 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
03398  *  @brief    Filter state functions
03399  *
03400 @verbatim
03401   ==============================================================================
03402                      ##### Filter state functions #####
03403   ==============================================================================
03404     [..]  This section provides functions allowing to:
03405       (+) Get the DFSDM filter state.
03406       (+) Get the DFSDM filter error.
03407 @endverbatim
03408   * @{
03409   */
03410
03411 /**
03412   * @brief  This function allows to get the current DFSDM filter handle state.
03413   * @param  hdfsdm_filter DFSDM filter handle.
03414   * @retval DFSDM filter state.
03415   */
03416 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03417 {
03418   /* Return DFSDM filter handle state */
03419   return hdfsdm_filter->State;
03420 }
03421
03422 /**
03423   * @brief  This function allows to get the current DFSDM filter error.
03424   * @param  hdfsdm_filter DFSDM filter handle.
03425   * @retval DFSDM filter error code.
03426   */
03427 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03428 {
03429   return hdfsdm_filter->ErrorCode;
03430 }
03431
03432 /**
03433   * @}
03434   */
03435
03436 /**
03437   * @}
03438   */
03439 /* End of exported functions -------------------------------------------------*/
03440
03441 /* Private functions ---------------------------------------------------------*/
03442 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
03443   * @{
03444   */
03445
03446 /**
03447   * @brief  DMA half transfer complete callback for regular conversion.
03448   * @param  hdma DMA handle.
03449   * @retval None
03450   */
03451 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
03452 {
03453   /* Get DFSDM filter handle */
03454   DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
03455
03456   /* Call regular half conversion complete callback */
03457 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03458   hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
03459 #else
03460   HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
03461 #endif
03462 }
03463
03464 /**
03465   * @brief  DMA transfer complete callback for regular conversion.
03466   * @param  hdma DMA handle.
03467   * @retval None
03468   */
03469 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
03470 {
03471   /* Get DFSDM filter handle */
03472   DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
03473
03474   /* Call regular conversion complete callback */
03475 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03476   hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
03477 #else
03478   HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
03479 #endif
03480 }
03481
03482 /**
03483   * @brief  DMA half transfer complete callback for injected conversion.
03484   * @param  hdma DMA handle.
03485   * @retval None
03486   */
03487 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
03488 {
03489   /* Get DFSDM filter handle */
03490   DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
03491
03492   /* Call injected half conversion complete callback */
03493 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03494   hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
03495 #else
03496   HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
03497 #endif
03498 }
03499
03500 /**
03501   * @brief  DMA transfer complete callback for injected conversion.
03502   * @param  hdma DMA handle.
03503   * @retval None
03504   */
03505 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
03506 {
03507   /* Get DFSDM filter handle */
03508   DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
03509
03510   /* Call injected conversion complete callback */
03511 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03512   hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
03513 #else
03514   HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
03515 #endif
03516 }
03517
03518 /**
03519   * @brief  DMA error callback.
03520   * @param  hdma DMA handle.
03521   * @retval None
03522   */
03523 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
03524 {
03525   /* Get DFSDM filter handle */
03526   DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
03527
03528   /* Update error code */
03529   hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
03530
03531   /* Call error callback */
03532 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
03533   hdfsdm_filter->ErrorCallback(hdfsdm_filter);
03534 #else
03535   HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
03536 #endif
03537 }
03538
03539 /**
03540   * @brief  This function allows to get the number of injected channels.
03541   * @param  Channels bitfield of injected channels.
03542   * @retval Number of injected channels.
03543   */
03544 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
03545 {
03546   uint32_t nbChannels = 0;
03547   uint32_t tmp;
03548
03549   /* Get the number of channels from bitfield */
03550   tmp = (uint32_t)(Channels & DFSDM_LSB_MASK);
03551   while(tmp != 0U)
03552   {
03553     if((tmp & 1U) != 0U)
03554     {
03555       nbChannels++;
03556     }
03557     tmp = (uint32_t)(tmp >> 1);
03558   }
03559   return nbChannels;
03560 }
03561
03562 /**
03563   * @brief  This function allows to get the channel number from channel instance.
03564   * @param  Instance DFSDM channel instance.
03565   * @retval Channel number.
03566   */
03567 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef* Instance)
03568 {
03569   uint32_t channel;
03570
03571   /* Get channel from instance */
03572   if(Instance == DFSDM1_Channel0)
03573   {
03574     channel = 0;
03575   }
03576 #if defined(DFSDM2_Channel0)
03577   else if (Instance == DFSDM2_Channel0)
03578   {
03579     channel = 0;
03580   }
03581   else if (Instance == DFSDM2_Channel1)
03582   {
03583     channel = 1;
03584   }
03585 #endif /* DFSDM2_Channel0 */
03586   else if(Instance == DFSDM1_Channel1)
03587   {
03588     channel = 1;
03589   }
03590   else if(Instance == DFSDM1_Channel2)
03591   {
03592     channel = 2;
03593   }
03594   else if(Instance == DFSDM1_Channel3)
03595   {
03596     channel = 3;
03597   }
03598   else if(Instance == DFSDM1_Channel4)
03599   {
03600     channel = 4;
03601   }
03602   else if(Instance == DFSDM1_Channel5)
03603   {
03604     channel = 5;
03605   }
03606   else if(Instance == DFSDM1_Channel6)
03607   {
03608     channel = 6;
03609   }
03610   else /* DFSDM1_Channel7 */
03611   {
03612       channel = 7;
03613   }
03614
03615   return channel;
03616 }
03617
03618 /**
03619   * @brief  This function allows to really start regular conversion.
03620   * @param  hdfsdm_filter DFSDM filter handle.
03621   * @retval None
03622   */
03623 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03624 {
03625   /* Check regular trigger */
03626   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
03627   {
03628     /* Software start of regular conversion */
03629     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
03630   }
03631   else /* synchronous trigger */
03632   {
03633     /* Disable DFSDM filter */
03634     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
03635
03636     /* Set RSYNC bit in DFSDM_FLTCR1 register */
03637     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
03638
03639     /* Enable DFSDM  filter */
03640     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
03641
03642     /* If injected conversion was in progress, restart it */
03643     if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
03644     {
03645       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
03646       {
03647         hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
03648       }
03649       /* Update remaining injected conversions */
03650       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
03651                                          hdfsdm_filter->InjectedChannelsNbr : 1U;
03652     }
03653   }
03654   /* Update DFSDM filter state */
03655   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
03656                           HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
03657 }
03658
03659 /**
03660   * @brief  This function allows to really stop regular conversion.
03661   * @param  hdfsdm_filter DFSDM filter handle.
03662   * @retval None
03663   */
03664 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03665 {
03666   /* Disable DFSDM filter */
03667   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
03668
03669   /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
03670   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
03671   {
03672     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
03673   }
03674
03675   /* Enable DFSDM filter */
03676   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
03677
03678   /* If injected conversion was in progress, restart it */
03679   if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
03680   {
03681     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
03682     {
03683       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
03684     }
03685     /* Update remaining injected conversions */
03686     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
03687                                        hdfsdm_filter->InjectedChannelsNbr : 1U;
03688   }
03689
03690   /* Update DFSDM filter state */
03691   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
03692                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
03693 }
03694
03695 /**
03696   * @brief  This function allows to really start injected conversion.
03697   * @param  hdfsdm_filter DFSDM filter handle.
03698   * @retval None
03699   */
03700 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03701 {
03702   /* Check injected trigger */
03703   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
03704   {
03705     /* Software start of injected conversion */
03706     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
03707   }
03708   else /* external or synchronous trigger */
03709   {
03710     /* Disable DFSDM filter */
03711     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
03712
03713     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
03714     {
03715       /* Set JSYNC bit in DFSDM_FLTCR1 register */
03716       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
03717     }
03718     else /* external trigger */
03719     {
03720       /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
03721       hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
03722     }
03723
03724     /* Enable DFSDM filter */
03725     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
03726
03727     /* If regular conversion was in progress, restart it */
03728     if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
03729        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
03730     {
03731       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
03732     }
03733   }
03734   /* Update DFSDM filter state */
03735   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
03736                          HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
03737 }
03738
03739 /**
03740   * @brief  This function allows to really stop injected conversion.
03741   * @param  hdfsdm_filter DFSDM filter handle.
03742   * @retval None
03743   */
03744 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
03745 {
03746   /* Disable DFSDM filter */
03747   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
03748
03749   /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
03750   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
03751   {
03752     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
03753   }
03754   else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
03755   {
03756     /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
03757     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
03758   }
03759   else
03760   {
03761     /* Nothing to do */
03762   }
03763
03764   /* Enable DFSDM filter */
03765   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
03766
03767   /* If regular conversion was in progress, restart it */
03768   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
03769      (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
03770   {
03771     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
03772   }
03773
03774   /* Update remaining injected conversions */
03775   hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
03776                                      hdfsdm_filter->InjectedChannelsNbr : 1U;
03777
03778   /* Update DFSDM filter state */
03779   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
03780                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
03781 }
03782
03783 /**
03784   * @}
03785   */
03786 /* End of private functions --------------------------------------------------*/
03787
03788 /**
03789   * @}
03790   */
03791
03792 #endif /* HAL_DFSDM_MODULE_ENABLED */
03793
03794 /**
03795   * @}
03796   */
03797
03798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm.h Source File

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stm32h7xx_hal_dfsdm.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DFSDM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DFSDM_H
00022 #define STM32H7xx_HAL_DFSDM_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DFSDM
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  HAL DFSDM Channel states definition
00046   */
00047 typedef enum
00048 {
00049   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
00050   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
00051   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
00052 } HAL_DFSDM_Channel_StateTypeDef;
00053
00054 /**
00055   * @brief  DFSDM channel output clock structure definition
00056   */
00057 typedef struct
00058 {
00059   FunctionalState Activation; /*!< Output clock enable/disable */
00060   uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
00061                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */
00062   uint32_t        Divider;    /*!< Output clock divider.
00063                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
00064 } DFSDM_Channel_OutputClockTypeDef;
00065
00066 /**
00067   * @brief  DFSDM channel input structure definition
00068   */
00069 typedef struct
00070 {
00071   uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
00072                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
00073   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
00074                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */
00075   uint32_t Pins;        /*!< Input pins are taken from same or following channel.
00076                              This parameter can be a value of @ref DFSDM_Channel_InputPins */
00077 } DFSDM_Channel_InputTypeDef;
00078
00079 /**
00080   * @brief  DFSDM channel serial interface structure definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t Type;     /*!< SPI or Manchester modes.
00085                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
00086   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
00087                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */
00088 } DFSDM_Channel_SerialInterfaceTypeDef;
00089
00090 /**
00091   * @brief  DFSDM channel analog watchdog structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
00096                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
00097   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
00098                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00099 } DFSDM_Channel_AwdTypeDef;
00100
00101 /**
00102   * @brief  DFSDM channel init structure definition
00103   */
00104 typedef struct
00105 {
00106   DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
00107   DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
00108   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
00109   DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
00110   int32_t                              Offset;          /*!< DFSDM channel offset.
00111                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00112   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
00113                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00114 } DFSDM_Channel_InitTypeDef;
00115
00116 /**
00117   * @brief  DFSDM channel handle structure definition
00118   */
00119 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00120 typedef struct __DFSDM_Channel_HandleTypeDef
00121 #else
00122 typedef struct
00123 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
00124 {
00125   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
00126   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
00127   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
00128 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00129   void (*CkabCallback)      (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
00130   void (*ScdCallback)       (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
00131   void (*MspInitCallback)   (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
00132   void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
00133 #endif
00134 } DFSDM_Channel_HandleTypeDef;
00135
00136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00137 /**
00138   * @brief  DFSDM channel callback ID enumeration definition
00139   */
00140 typedef enum
00141 {
00142   HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
00143   HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
00144   HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */
00145   HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */
00146 } HAL_DFSDM_Channel_CallbackIDTypeDef;
00147
00148 /**
00149   * @brief  DFSDM channel callback pointer definition
00150   */
00151 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00152 #endif
00153
00154 /**
00155   * @brief  HAL DFSDM Filter states definition
00156   */
00157 typedef enum
00158 {
00159   HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
00160   HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
00161   HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
00162   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
00163   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
00164   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
00165 } HAL_DFSDM_Filter_StateTypeDef;
00166
00167 /**
00168   * @brief  DFSDM filter regular conversion parameters structure definition
00169   */
00170 typedef struct
00171 {
00172   uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
00173                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */
00174   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
00175   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
00176 } DFSDM_Filter_RegularParamTypeDef;
00177
00178 /**
00179   * @brief  DFSDM filter injected conversion parameters structure definition
00180   */
00181 typedef struct
00182 {
00183   uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
00184                                        This parameter can be a value of @ref DFSDM_Filter_Trigger */
00185   FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
00186   FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
00187   uint32_t        ExtTrigger;     /*!< External trigger.
00188                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
00189   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
00190                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
00191 } DFSDM_Filter_InjectedParamTypeDef;
00192
00193 /**
00194   * @brief  DFSDM filter parameters structure definition
00195   */
00196 typedef struct
00197 {
00198   uint32_t SincOrder;       /*!< Sinc filter order.
00199                                  This parameter can be a value of @ref DFSDM_Filter_SincOrder */
00200   uint32_t Oversampling;    /*!< Filter oversampling ratio.
00201                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00202   uint32_t IntOversampling; /*!< Integrator oversampling ratio.
00203                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
00204 } DFSDM_Filter_FilterParamTypeDef;
00205
00206 /**
00207   * @brief  DFSDM filter init structure definition
00208   */
00209 typedef struct
00210 {
00211   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
00212   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
00213   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
00214 } DFSDM_Filter_InitTypeDef;
00215
00216 /**
00217   * @brief  DFSDM filter handle structure definition
00218   */
00219 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00220 typedef struct __DFSDM_Filter_HandleTypeDef
00221 #else
00222 typedef struct
00223 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
00224 {
00225   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
00226   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
00227   DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
00228   DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
00229   uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
00230   uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
00231   uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
00232   uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
00233   FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
00234   uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
00235   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
00236   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
00237   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */
00238 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00239   void (*AwdCallback)             (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00240                                    uint32_t Channel, uint32_t Threshold);               /*!< DFSDM filter analog watchdog callback */
00241   void (*RegConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
00242   void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
00243   void (*InjConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
00244   void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */
00245   void (*ErrorCallback)           (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */
00246   void (*MspInitCallback)         (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */
00247   void (*MspDeInitCallback)       (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */
00248 #endif
00249 }DFSDM_Filter_HandleTypeDef;
00250
00251 /**
00252   * @brief  DFSDM filter analog watchdog parameters structure definition
00253   */
00254 typedef struct
00255 {
00256   uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
00257                                  This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
00258   uint32_t Channel;         /*!< Analog watchdog channel selection.
00259                                  This parameter can be a values combination of @ref DFSDM_Channel_Selection */
00260   int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
00261                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00262   int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
00263                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00264   uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
00265                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00266   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
00267                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00268 } DFSDM_Filter_AwdParamTypeDef;
00269
00270 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00271 /**
00272   * @brief  DFSDM filter callback ID enumeration definition
00273   */
00274 typedef enum
00275 {
00276   HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
00277   HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
00278   HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
00279   HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
00280   HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */
00281   HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */
00282   HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */
00283 } HAL_DFSDM_Filter_CallbackIDTypeDef;
00284
00285 /**
00286   * @brief  DFSDM filter callback pointer definition
00287   */
00288 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00289 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
00290 #endif
00291
00292 /**
00293   * @}
00294   */
00295 /* End of exported types -----------------------------------------------------*/
00296
00297 /* Exported constants --------------------------------------------------------*/
00298 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
00299   * @{
00300   */
00301
00302 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
00303   * @{
00304   */
00305 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U            /*!< Source for ouput clock is system clock */
00306 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
00312   * @{
00313   */
00314 #define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */
00315 #define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */
00316 #define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
00322   * @{
00323   */
00324 #define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */
00325 #define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
00326 #define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
00332   * @{
00333   */
00334 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U            /*!< Input from pins on same channel */
00335 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL  /*!< Input from pins on following channel */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
00341   * @{
00342   */
00343 #define DFSDM_CHANNEL_SPI_RISING         0x00000000U            /*!< SPI with rising edge */
00344 #define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0   /*!< SPI with falling edge */
00345 #define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1   /*!< Manchester with rising edge */
00346 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP     /*!< Manchester with falling edge */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
00352   * @{
00353   */
00354 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */
00355 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
00356 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
00357 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
00363   * @{
00364   */
00365 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */
00366 #define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
00367 #define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
00368 #define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
00374   * @{
00375   */
00376 #define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */
00377 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
00378 #define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
00384   * @{
00385   */
00386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO       0x00000000U                                       /*!< For all DFSDM filters */
00387 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2      DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */
00388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO       DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */
00389 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2      (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
00390 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO       DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */
00391 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)                         /*!< For all DFSDM filters */
00392 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1       (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)                        /*!< For all DFSDM filters */
00393 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
00394 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO       DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
00395 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
00396 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
00397 #define DFSDM_FILTER_EXT_TRIG_EXTI11          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For all DFSDM filters */
00398 #define DFSDM_FILTER_EXT_TRIG_EXTI15          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)                           /*!< For all DFSDM filters */
00399 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)                           /*!< For all DFSDM filters */
00400 #define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)  /*!< For all DFSDM filters */
00401 #define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For all DFSDM filters */
00402 #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
00403 #define DFSDM_FILTER_EXT_TRIG_COMP1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
00404                                               DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
00405 #define DFSDM_FILTER_EXT_TRIG_COMP2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
00406                                               DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
00407 #endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
00413   * @{
00414   */
00415 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
00416 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
00417 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
00423   * @{
00424   */
00425 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */
00426 #define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
00427 #define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
00428 #define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
00429 #define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
00430 #define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
00436   * @{
00437   */
00438 #define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */
00439 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
00445   * @{
00446   */
00447 #define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */
00448 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */
00449 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
00450 #define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */
00451 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00452 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
00453 #endif
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup DFSDM_BreakSignals DFSDM break signals
00459   * @{
00460   */
00461 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
00462 #define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */
00463 #define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */
00464 #define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */
00465 #define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
00471   * @{
00472   */
00473 /* DFSDM Channels ------------------------------------------------------------*/
00474 /* The DFSDM channels are defined as follows:
00475    - in 16-bit LSB the channel mask is set
00476    - in 16-bit MSB the channel number is set
00477    e.g. for channel 5 definition:
00478         - the channel mask is 0x00000020 (bit 5 is set)
00479         - the channel number 5 is 0x00050000
00480         --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
00481 #define DFSDM_CHANNEL_0                              0x00000001U
00482 #define DFSDM_CHANNEL_1                              0x00010002U
00483 #define DFSDM_CHANNEL_2                              0x00020004U
00484 #define DFSDM_CHANNEL_3                              0x00030008U
00485 #define DFSDM_CHANNEL_4                              0x00040010U
00486 #define DFSDM_CHANNEL_5                              0x00050020U
00487 #define DFSDM_CHANNEL_6                              0x00060040U
00488 #define DFSDM_CHANNEL_7                              0x00070080U
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
00494   * @{
00495   */
00496 #define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */
00497 #define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */
00498 /**
00499   * @}
00500   */
00501
00502 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
00503   * @{
00504   */
00505 #define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */
00506 #define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */
00507 /**
00508   * @}
00509   */
00510
00511 /**
00512   * @}
00513   */
00514 /* End of exported constants -------------------------------------------------*/
00515
00516 /* Exported macros -----------------------------------------------------------*/
00517 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
00518  * @{
00519  */
00520
00521 /** @brief  Reset DFSDM channel handle state.
00522   * @param  __HANDLE__ DFSDM channel handle.
00523   * @retval None
00524   */
00525 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00526 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \
00527                                                                (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
00528                                                                (__HANDLE__)->MspInitCallback = NULL;                \
00529                                                                (__HANDLE__)->MspDeInitCallback = NULL;              \
00530                                                              } while(0)
00531 #else
00532 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
00533 #endif
00534
00535 /** @brief  Reset DFSDM filter handle state.
00536   * @param  __HANDLE__ DFSDM filter handle.
00537   * @retval None
00538   */
00539 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00540 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \
00541                                                               (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
00542                                                               (__HANDLE__)->MspInitCallback = NULL;               \
00543                                                               (__HANDLE__)->MspDeInitCallback = NULL;             \
00544                                                             } while(0)
00545 #else
00546 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
00547 #endif
00548
00549 /**
00550   * @}
00551   */
00552 /* End of exported macros ----------------------------------------------------*/
00553
00554 #if defined(DFSDM_CHDLYR_PLSSKP)
00555 /* Include DFSDM HAL Extension module */
00556 #include "stm32h7xx_hal_dfsdm_ex.h"
00557 #endif /* DFSDM_CHDLYR_PLSSKP */
00558
00559 /* Exported functions --------------------------------------------------------*/
00560 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
00561   * @{
00562   */
00563
00564 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00565   * @{
00566   */
00567 /* Channel initialization and de-initialization functions *********************/
00568 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00569 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00570 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00571 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00572
00573 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00574 /* Channel callbacks register/unregister functions ****************************/
00575 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
00576                                                      HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
00577                                                      pDFSDM_Channel_CallbackTypeDef      pCallback);
00578 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
00579                                                        HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
00580 #endif
00581 /**
00582   * @}
00583   */
00584
00585 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00586   * @{
00587   */
00588 /* Channel operation functions ************************************************/
00589 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00590 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00591 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00592 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00593
00594 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00595 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00596 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00597 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00598
00599 int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00600 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
00601
00602 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00603 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00604
00605 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00606 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00612   * @{
00613   */
00614 /* Channel state function *****************************************************/
00615 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00616 /**
00617   * @}
00618   */
00619
00620 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
00621   * @{
00622   */
00623 /* Filter initialization and de-initialization functions *********************/
00624 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00625 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00626 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00627 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00628
00629 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
00630 /* Filter callbacks register/unregister functions ****************************/
00631 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
00632                                                     HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
00633                                                     pDFSDM_Filter_CallbackTypeDef      pCallback);
00634 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
00635                                                       HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
00636 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,
00637                                                        pDFSDM_Filter_AwdCallbackTypeDef pCallback);
00638 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00639 #endif
00640 /**
00641   * @}
00642   */
00643
00644 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
00645   * @{
00646   */
00647 /* Filter control functions *********************/
00648 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00649                                                    uint32_t                    Channel,
00650                                                    uint32_t                    ContinuousMode);
00651 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00652                                                    uint32_t                    Channel);
00653 /**
00654   * @}
00655   */
00656
00657 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
00658   * @{
00659   */
00660 /* Filter operation functions *********************/
00661 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00662 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00663 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00664 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00665 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00666 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00667 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00668 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00669 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00670 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00671 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00672 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00673 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00674 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00675 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00676                                               DFSDM_Filter_AwdParamTypeDef *awdParam);
00677 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00678 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
00679 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00680
00681 int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
00682 int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
00683 int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
00684 int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
00685 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00686
00687 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00688
00689 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00690 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00691
00692 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00693 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00694 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00695 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00696 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
00697 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
00703   * @{
00704   */
00705 /* Filter state functions *****************************************************/
00706 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00707 uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00708 /**
00709   * @}
00710   */
00711
00712 /**
00713   * @}
00714   */
00715 /* End of exported functions -------------------------------------------------*/
00716
00717 /* Private macros ------------------------------------------------------------*/
00718 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
00719 * @{
00720 */
00721 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
00722                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
00723 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
00724 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
00725                                                        ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
00726                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
00727 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
00728                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
00729                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
00730 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
00731                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
00732 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
00733                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
00734                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
00735                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
00736 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
00737                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
00738                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
00739                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
00740 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
00741                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
00742                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
00743                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
00744 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))
00745 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00746 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)
00747 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)
00748 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00749                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
00750 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00751                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
00752                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
00753 #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
00754 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00755                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
00756                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00757                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
00758                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00759                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00760                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
00761                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00762                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
00763                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
00764                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
00765                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
00766                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
00767                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
00768                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
00769                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))
00770 #else
00771 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00772                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
00773                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00774                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
00775                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00776                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00777                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
00778                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00779                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
00780                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
00781                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
00782                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
00783                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
00784                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
00785                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
00786                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))
00787 #endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx  || STM32H7B0xxQ */
00788 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
00789                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
00790                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
00791 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
00792                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
00793                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
00794                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
00795                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
00796                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
00797 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))
00798 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))
00799 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
00800                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
00801 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00802 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)
00803 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
00804                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \
00805                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \
00806                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \
00807                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \
00808                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \
00809                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \
00810                                                        ((CHANNEL) == DFSDM_CHANNEL_7))
00811 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
00812 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
00813                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
00814 #if defined(DFSDM2_Channel0)
00815 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Channel0) || \
00816                                                        ((INSTANCE) == DFSDM1_Channel1) || \
00817                                                        ((INSTANCE) == DFSDM1_Channel2) || \
00818                                                        ((INSTANCE) == DFSDM1_Channel3) || \
00819                                                        ((INSTANCE) == DFSDM1_Channel4) || \
00820                                                        ((INSTANCE) == DFSDM1_Channel5) || \
00821                                                        ((INSTANCE) == DFSDM1_Channel6) || \
00822                                                        ((INSTANCE) == DFSDM1_Channel7))
00823 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE)           (((INSTANCE) == DFSDM1_Filter0) || \
00824                                                        ((INSTANCE) == DFSDM1_Filter1) || \
00825                                                        ((INSTANCE) == DFSDM1_Filter2) || \
00826                                                        ((INSTANCE) == DFSDM1_Filter3) || \
00827                                                        ((INSTANCE) == DFSDM1_Filter4) || \
00828                                                        ((INSTANCE) == DFSDM1_Filter5) || \
00829                                                        ((INSTANCE) == DFSDM1_Filter6) || \
00830                                                        ((INSTANCE) == DFSDM1_Filter7))
00831 #endif /* DFSDM2_Channel0 */
00832 /**
00833   * @}
00834   */
00835 /* End of private macros -----------------------------------------------------*/
00836
00837 /**
00838   * @}
00839   */
00840
00841 /**
00842   * @}
00843   */
00844
00845 #ifdef __cplusplus
00846 }
00847 #endif
00848
00849 #endif /* STM32H7xx_HAL_DFSDM_H */
00850
00851 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm_ex.c Source File

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stm32h7xx_hal_dfsdm_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DFSDM Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionality of the DFSDM Peripheral Controller:
00008   *           + Set and get pulses skipping on channel.
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32h7xx_hal.h"
00026
00027 /** @addtogroup STM32H7xx_HAL_Driver
00028   * @{
00029   */
00030
00031 #ifdef HAL_DFSDM_MODULE_ENABLED
00032
00033 #if defined(DFSDM_CHDLYR_PLSSKP)
00034
00035 /** @defgroup DFSDMEx DFSDMEx
00036   * @brief DFSDM Extended HAL module driver
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045 /* Exported functions --------------------------------------------------------*/
00046
00047 /** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
00048   * @{
00049   */
00050
00051 /** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
00052   * @brief    DFSDM extended channel operation functions
00053  *
00054 @verbatim
00055  ===============================================================================
00056                ##### Extended channel operation functions #####
00057  ===============================================================================
00058     [..]  This section provides functions allowing to:
00059       (+) Set and get value of pulses skipping on channel
00060
00061 @endverbatim
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  Set value of pulses skipping.
00067   * @param  hdfsdm_channel DFSDM channel handle.
00068   * @param  PulsesValue Value of pulses to be skipped.
00069   *         This parameter must be a number between Min_Data = 0 and Max_Data = 63.
00070   * @retval HAL status.
00071   */
00072 HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
00073 {
00074   HAL_StatusTypeDef status = HAL_OK;
00075
00076   /* Check pulses value */
00077   assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue));
00078
00079   /* Check DFSDM channel state */
00080   if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
00081   {
00082     /* Set new value of pulses skipping */
00083     hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP);
00084   }
00085   else
00086   {
00087     status = HAL_ERROR;
00088   }
00089   return status;
00090 }
00091
00092 /**
00093   * @brief  Get value of pulses skipping.
00094   * @param  hdfsdm_channel DFSDM channel handle.
00095   * @param  PulsesValue Value of pulses to be skipped.
00096   * @retval HAL status.
00097   */
00098 HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
00099 {
00100   HAL_StatusTypeDef status = HAL_OK;
00101
00102   /* Check DFSDM channel state */
00103   if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
00104   {
00105     /* Get value of remaining pulses to be skipped */
00106     *PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP);
00107   }
00108   else
00109   {
00110     status = HAL_ERROR;
00111   }
00112   return status;
00113 }
00114
00115 /**
00116   * @}
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /**
00124   * @}
00125   */
00126
00127 #endif /* DFSDM_CHDLYR_PLSSKP */
00128
00129 #endif /* HAL_DFSDM_MODULE_ENABLED */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dfsdm_ex.h Source File

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stm32h7xx_hal_dfsdm_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DFSDM HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DFSDM_EX_H
00022 #define STM32H7xx_HAL_DFSDM_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 #if defined(DFSDM_CHDLYR_PLSSKP)
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32h7xx_hal_def.h"
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup DFSDMEx
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /* Exported constants --------------------------------------------------------*/
00043 /* Exported macros -----------------------------------------------------------*/
00044 /* Exported functions --------------------------------------------------------*/
00045
00046 /** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
00047   * @{
00048   */
00049
00050 /** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
00051   * @{
00052   */
00053
00054 HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
00055 HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
00056
00057 /**
00058   * @}
00059   */
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macros ------------------------------------------------------------*/
00066
00067 /** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros
00068   * @{
00069   */
00070
00071 #define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE)   ((VALUE) < 64U)
00072
00073 /**
00074   * @}
00075   */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /**
00082   * @}
00083   */
00084
00085 #endif /* DFSDM_CHDLYR_PLSSKP */
00086
00087 #ifdef __cplusplus
00088 }
00089 #endif
00090
00091 #endif /* STM32H7xx_HAL_DFSDM_EX_H */
00092
00093 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma2d.c Source File

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stm32h7xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @brief   DMA2D HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DMA2D peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (#) Program the required configuration through the following parameters:
00019           the transfer mode, the output color mode and the output offset using
00020           HAL_DMA2D_Init() function.
00021
00022       (#) Program the required configuration through the following parameters:
00023           the input color mode, the input color, the input alpha value, the alpha mode,
00024           the red/blue swap mode, the inverted alpha mode and the input offset using
00025           HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
00026
00027      *** Polling mode IO operation ***
00028      =================================
00029     [..]
00030        (#) Configure pdata parameter (explained hereafter), destination and data length
00031            and enable the transfer using HAL_DMA2D_Start().
00032        (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00033            user can specify the value of timeout according to his end application.
00034
00035      *** Interrupt mode IO operation ***
00036      ===================================
00037      [..]
00038        (#) Configure pdata parameter, destination and data length and enable
00039            the transfer using HAL_DMA2D_Start_IT().
00040        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
00041        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00042            add his own function by customization of function pointer XferCpltCallback (member
00043            of DMA2D handle structure).
00044        (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
00045            XferErrorCallback.
00046
00047          -@-   In Register-to-Memory transfer mode, pdata parameter is the register
00048                color, in Memory-to-memory or Memory-to-Memory with pixel format
00049                conversion pdata is the source address.
00050
00051          -@-   Configure the foreground source address, the background source address,
00052                the destination and data length then Enable the transfer using
00053                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00054                in interrupt mode.
00055
00056          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00057                are used if the memory to memory with blending transfer mode is selected.
00058
00059       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
00060           mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
00061
00062       (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
00063
00064       (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
00065           consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
00066           and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
00067           HAL_DMA2D_DisableDeadTime().
00068
00069       (#) The transfer can be suspended, resumed and aborted using the following
00070           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00071
00072       (#) The CLUT loading can be suspended, resumed and aborted using the following
00073           functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
00074           HAL_DMA2D_CLUTLoading_Abort().
00075
00076       (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
00077
00078       (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
00079
00080      *** DMA2D HAL driver macros list ***
00081      =============================================
00082      [..]
00083        Below the list of most used macros in DMA2D HAL driver :
00084
00085       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00086       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00087       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00088       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00089       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00090       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
00091
00092      *** Callback registration ***
00093      ===================================
00094      [..]
00095       (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
00096           allows the user to configure dynamically the driver callbacks.
00097           Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
00098
00099       (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
00100             (+) XferCpltCallback : callback for transfer complete.
00101             (+) XferErrorCallback : callback for transfer error.
00102             (+) LineEventCallback : callback for line event.
00103             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
00104             (+) MspInitCallback    : DMA2D MspInit.
00105             (+) MspDeInitCallback  : DMA2D MspDeInit.
00106           This function takes as parameters the HAL peripheral handle, the Callback ID
00107           and a pointer to the user callback function.
00108
00109       (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
00110           weak (surcharged) function.
00111           @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00112           and the Callback ID.
00113           This function allows to reset following callbacks:
00114             (+) XferCpltCallback : callback for transfer complete.
00115             (+) XferErrorCallback : callback for transfer error.
00116             (+) LineEventCallback : callback for line event.
00117             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
00118             (+) MspInitCallback    : DMA2D MspInit.
00119             (+) MspDeInitCallback  : DMA2D MspDeInit.
00120
00121       (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
00122           all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00123           examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
00124           Exception done for MspInit and MspDeInit callbacks that are respectively
00125           reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
00126           and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
00127           If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
00128           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00129
00130           Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
00131           as weak (surcharged) functions. They must be defined by the user to be resorted to.
00132
00133           Callbacks can be registered/unregistered in READY state only.
00134           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00135           in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00136           during the Init/DeInit.
00137           In that case first register the MspInit/MspDeInit user callbacks
00138           using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
00139           or @ref HAL_DMA2D_Init function.
00140
00141           When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
00142           not defined, the callback registering feature is not available
00143           and weak (surcharged) callbacks are used.
00144
00145      [..]
00146       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00147
00148   @endverbatim
00149   ******************************************************************************
00150   * @attention
00151   *
00152   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00153   * All rights reserved.</center></h2>
00154   *
00155   * This software component is licensed by ST under BSD 3-Clause license,
00156   * the "License"; You may not use this file except in compliance with the
00157   * License. You may obtain a copy of the License at:
00158   *                        opensource.org/licenses/BSD-3-Clause
00159   *
00160   ******************************************************************************
00161   */
00162
00163 /* Includes ------------------------------------------------------------------*/
00164 #include "stm32h7xx_hal.h"
00165
00166 #ifdef HAL_DMA2D_MODULE_ENABLED
00167 #if defined (DMA2D)
00168
00169 /** @addtogroup STM32H7xx_HAL_Driver
00170   * @{
00171   */
00172
00173 /** @defgroup DMA2D  DMA2D
00174   * @brief DMA2D HAL module driver
00175   * @{
00176   */
00177
00178 /* Private types -------------------------------------------------------------*/
00179 /* Private define ------------------------------------------------------------*/
00180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00181   * @{
00182   */
00183
00184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
00185   * @{
00186   */
00187 #define DMA2D_TIMEOUT_ABORT           (1000U)  /*!<  1s  */
00188 #define DMA2D_TIMEOUT_SUSPEND         (1000U)  /*!<  1s  */
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /* Private variables ---------------------------------------------------------*/
00198 /* Private constants ---------------------------------------------------------*/
00199 /* Private macro -------------------------------------------------------------*/
00200 /* Private function prototypes -----------------------------------------------*/
00201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
00202   * @{
00203   */
00204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00205 /**
00206   * @}
00207   */
00208
00209 /* Private functions ---------------------------------------------------------*/
00210 /* Exported functions --------------------------------------------------------*/
00211 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00212   * @{
00213   */
00214
00215 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00216  *  @brief   Initialization and Configuration functions
00217  *
00218 @verbatim
00219  ===============================================================================
00220                 ##### Initialization and Configuration functions #####
00221  ===============================================================================
00222     [..]  This section provides functions allowing to:
00223       (+) Initialize and configure the DMA2D
00224       (+) De-initialize the DMA2D
00225
00226 @endverbatim
00227   * @{
00228   */
00229
00230 /**
00231   * @brief  Initialize the DMA2D according to the specified
00232   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00233   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00234   *                 the configuration information for the DMA2D.
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00238 {
00239   /* Check the DMA2D peripheral state */
00240   if(hdma2d == NULL)
00241   {
00242      return HAL_ERROR;
00243   }
00244
00245   /* Check the parameters */
00246   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00247   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00248   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00249   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00250   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
00251   assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
00252   assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
00253   assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
00254
00255 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00256   if (hdma2d->State == HAL_DMA2D_STATE_RESET)
00257   {
00258     /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
00259     hdma2d->LineEventCallback       = HAL_DMA2D_LineEventCallback;
00260     hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
00261     if(hdma2d->MspInitCallback == NULL)
00262     {
00263       hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
00264     }
00265
00266     /* Init the low level hardware */
00267     hdma2d->MspInitCallback(hdma2d);
00268   }
00269 #else
00270   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00271   {
00272     /* Allocate lock resource and initialize it */
00273     hdma2d->Lock = HAL_UNLOCKED;
00274     /* Init the low level hardware */
00275     HAL_DMA2D_MspInit(hdma2d);
00276   }
00277 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
00278
00279   /* Change DMA2D peripheral state */
00280   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00281
00282   /* DMA2D CR register configuration -------------------------------------------*/
00283   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
00284
00285   /* DMA2D OPFCCR register configuration ---------------------------------------*/
00286   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
00287
00288   /* DMA2D OOR register configuration ------------------------------------------*/
00289   MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
00290   /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
00291   MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
00292
00293
00294   /* Update error code */
00295   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00296
00297   /* Initialize the DMA2D state*/
00298   hdma2d->State  = HAL_DMA2D_STATE_READY;
00299
00300   return HAL_OK;
00301 }
00302
00303 /**
00304   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00305   *         values.
00306   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00307   *                 the configuration information for the DMA2D.
00308   * @retval None
00309   */
00310
00311 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00312 {
00313
00314   /* Check the DMA2D peripheral state */
00315   if(hdma2d == NULL)
00316   {
00317      return HAL_ERROR;
00318   }
00319
00320   /* Before aborting any DMA2D transfer or CLUT loading, check
00321      first whether or not DMA2D clock is enabled */
00322   if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
00323   {
00324     /* Abort DMA2D transfer if any */
00325     if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
00326     {
00327       if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
00328       {
00329         /* Issue when aborting DMA2D transfer */
00330         return HAL_ERROR;
00331       }
00332     }
00333     else
00334     {
00335       /* Abort background CLUT loading if any */
00336       if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
00337       {
00338         if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
00339         {
00340           /* Issue when aborting background CLUT loading */
00341           return HAL_ERROR;
00342         }
00343       }
00344       else
00345       {
00346         /* Abort foreground CLUT loading if any */
00347         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
00348         {
00349           if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
00350           {
00351             /* Issue when aborting foreground CLUT loading */
00352             return HAL_ERROR;
00353           }
00354         }
00355       }
00356     }
00357   }
00358
00359   /* Reset DMA2D control registers*/
00360   hdma2d->Instance->CR       =    0U;
00361   hdma2d->Instance->IFCR     = 0x3FU;
00362   hdma2d->Instance->FGOR     =    0U;
00363   hdma2d->Instance->BGOR     =    0U;
00364   hdma2d->Instance->FGPFCCR  =    0U;
00365   hdma2d->Instance->BGPFCCR  =    0U;
00366   hdma2d->Instance->OPFCCR   =    0U;
00367
00368 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00369
00370     if(hdma2d->MspDeInitCallback == NULL)
00371     {
00372       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
00373     }
00374
00375     /* DeInit the low level hardware */
00376     hdma2d->MspDeInitCallback(hdma2d);
00377
00378 #else
00379   /* Carry on with de-initialization of low level hardware */
00380   HAL_DMA2D_MspDeInit(hdma2d);
00381 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
00382
00383   /* Update error code */
00384   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00385
00386   /* Initialize the DMA2D state*/
00387   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00388
00389   /* Release Lock */
00390   __HAL_UNLOCK(hdma2d);
00391
00392   return HAL_OK;
00393 }
00394
00395 /**
00396   * @brief  Initializes the DMA2D MSP.
00397   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00398   *                 the configuration information for the DMA2D.
00399   * @retval None
00400   */
00401 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00402 {
00403   /* Prevent unused argument(s) compilation warning */
00404   UNUSED(hdma2d);
00405
00406   /* NOTE : This function should not be modified; when the callback is needed,
00407             the HAL_DMA2D_MspInit can be implemented in the user file.
00408    */
00409 }
00410
00411 /**
00412   * @brief  DeInitializes the DMA2D MSP.
00413   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00414   *                 the configuration information for the DMA2D.
00415   * @retval None
00416   */
00417 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00418 {
00419   /* Prevent unused argument(s) compilation warning */
00420   UNUSED(hdma2d);
00421
00422   /* NOTE : This function should not be modified; when the callback is needed,
00423             the HAL_DMA2D_MspDeInit can be implemented in the user file.
00424    */
00425 }
00426
00427 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00428 /**
00429   * @brief  Register a User DMA2D Callback
00430   *         To be used instead of the weak (surcharged) predefined callback
00431   * @param hdma2d DMA2D handle
00432   * @param CallbackID ID of the callback to be registered
00433   *        This parameter can be one of the following values:
00434   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
00435   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
00436   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
00437   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
00438   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
00439   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
00440   * @param pCallback pointer to the Callback function
00441   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
00442   * @retval status
00443   */
00444 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
00445 {
00446   HAL_StatusTypeDef status = HAL_OK;
00447
00448   if(pCallback == NULL)
00449   {
00450     /* Update the error code */
00451     hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00452     return HAL_ERROR;
00453   }
00454   /* Process locked */
00455   __HAL_LOCK(hdma2d);
00456
00457   if(HAL_DMA2D_STATE_READY == hdma2d->State)
00458   {
00459     switch (CallbackID)
00460     {
00461     case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
00462       hdma2d->XferCpltCallback = pCallback;
00463       break;
00464
00465     case HAL_DMA2D_TRANSFERERROR_CB_ID :
00466       hdma2d->XferErrorCallback = pCallback;
00467       break;
00468
00469     case HAL_DMA2D_LINEEVENT_CB_ID :
00470       hdma2d->LineEventCallback = pCallback;
00471       break;
00472
00473     case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
00474       hdma2d->CLUTLoadingCpltCallback = pCallback;
00475       break;
00476
00477     case HAL_DMA2D_MSPINIT_CB_ID :
00478       hdma2d->MspInitCallback = pCallback;
00479       break;
00480
00481     case HAL_DMA2D_MSPDEINIT_CB_ID :
00482       hdma2d->MspDeInitCallback = pCallback;
00483       break;
00484
00485     default :
00486      /* Update the error code */
00487      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00488      /* update return status */
00489       status =  HAL_ERROR;
00490       break;
00491     }
00492   }
00493   else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
00494   {
00495     switch (CallbackID)
00496     {
00497     case HAL_DMA2D_MSPINIT_CB_ID :
00498       hdma2d->MspInitCallback = pCallback;
00499       break;
00500
00501     case HAL_DMA2D_MSPDEINIT_CB_ID :
00502       hdma2d->MspDeInitCallback = pCallback;
00503       break;
00504
00505     default :
00506      /* Update the error code */
00507      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00508      /* update return status */
00509       status =  HAL_ERROR;
00510       break;
00511     }
00512   }
00513   else
00514   {
00515     /* Update the error code */
00516      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00517      /* update return status */
00518       status =  HAL_ERROR;
00519   }
00520
00521   /* Release Lock */
00522   __HAL_UNLOCK(hdma2d);
00523   return status;
00524 }
00525
00526 /**
00527   * @brief  Unregister a DMA2D Callback
00528   *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
00529   * @param hdma2d DMA2D handle
00530   * @param CallbackID ID of the callback to be unregistered
00531   *        This parameter can be one of the following values:
00532   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
00533   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
00534   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
00535   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
00536   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
00537   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
00538   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
00539   * @retval status
00540   */
00541 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
00542 {
00543 HAL_StatusTypeDef status = HAL_OK;
00544
00545   /* Process locked */
00546   __HAL_LOCK(hdma2d);
00547
00548   if(HAL_DMA2D_STATE_READY == hdma2d->State)
00549   {
00550     switch (CallbackID)
00551     {
00552     case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
00553       hdma2d->XferCpltCallback = NULL;
00554       break;
00555
00556     case HAL_DMA2D_TRANSFERERROR_CB_ID :
00557       hdma2d->XferErrorCallback = NULL;
00558       break;
00559
00560     case HAL_DMA2D_LINEEVENT_CB_ID :
00561       hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
00562       break;
00563
00564     case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
00565       hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
00566       break;
00567
00568     case HAL_DMA2D_MSPINIT_CB_ID :
00569       hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
00570       break;
00571
00572     case HAL_DMA2D_MSPDEINIT_CB_ID :
00573       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
00574       break;
00575
00576     default :
00577      /* Update the error code */
00578      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00579      /* update return status */
00580       status =  HAL_ERROR;
00581       break;
00582     }
00583   }
00584   else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
00585   {
00586     switch (CallbackID)
00587     {
00588     case HAL_DMA2D_MSPINIT_CB_ID :
00589       hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
00590       break;
00591
00592     case HAL_DMA2D_MSPDEINIT_CB_ID :
00593       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
00594       break;
00595
00596     default :
00597      /* Update the error code */
00598      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00599      /* update return status */
00600       status =  HAL_ERROR;
00601       break;
00602     }
00603   }
00604   else
00605   {
00606      /* Update the error code */
00607      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00608      /* update return status */
00609       status =  HAL_ERROR;
00610   }
00611
00612   /* Release Lock */
00613   __HAL_UNLOCK(hdma2d);
00614   return status;
00615 }
00616 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00617
00618 /**
00619   * @}
00620   */
00621
00622
00623 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
00624  *  @brief   IO operation functions
00625  *
00626 @verbatim
00627  ===============================================================================
00628                       #####  IO operation functions  #####
00629  ===============================================================================
00630     [..]  This section provides functions allowing to:
00631       (+) Configure the pdata, destination address and data size then
00632           start the DMA2D transfer.
00633       (+) Configure the source for foreground and background, destination address
00634           and data size then start a MultiBuffer DMA2D transfer.
00635       (+) Configure the pdata, destination address and data size then
00636           start the DMA2D transfer with interrupt.
00637       (+) Configure the source for foreground and background, destination address
00638           and data size then start a MultiBuffer DMA2D transfer with interrupt.
00639       (+) Abort DMA2D transfer.
00640       (+) Suspend DMA2D transfer.
00641       (+) Resume DMA2D transfer.
00642       (+) Enable CLUT transfer.
00643       (+) Configure CLUT loading then start transfer in polling mode.
00644       (+) Configure CLUT loading then start transfer in interrupt mode.
00645       (+) Abort DMA2D CLUT loading.
00646       (+) Suspend DMA2D CLUT loading.
00647       (+) Resume DMA2D CLUT loading.
00648       (+) Poll for transfer complete.
00649       (+) handle DMA2D interrupt request.
00650       (+) Transfer watermark callback.
00651       (+) CLUT Transfer Complete callback.
00652
00653
00654 @endverbatim
00655   * @{
00656   */
00657
00658 /**
00659   * @brief  Start the DMA2D Transfer.
00660   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00661   *                     the configuration information for the DMA2D.
00662   * @param  pdata      Configure the source memory Buffer address if
00663   *                     Memory-to-Memory or Memory-to-Memory with pixel format
00664   *                     conversion mode is selected, or configure
00665   *                     the color value if Register-to-Memory mode is selected.
00666   * @param  DstAddress The destination memory Buffer address.
00667   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00668   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00672 {
00673   /* Check the parameters */
00674   assert_param(IS_DMA2D_LINE(Height));
00675   assert_param(IS_DMA2D_PIXEL(Width));
00676
00677   /* Process locked */
00678   __HAL_LOCK(hdma2d);
00679
00680   /* Change DMA2D peripheral state */
00681   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00682
00683   /* Configure the source, destination address and the data size */
00684   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00685
00686   /* Enable the Peripheral */
00687   __HAL_DMA2D_ENABLE(hdma2d);
00688
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief  Start the DMA2D Transfer with interrupt enabled.
00694   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00695   *                     the configuration information for the DMA2D.
00696   * @param  pdata      Configure the source memory Buffer address if
00697   *                     the Memory-to-Memory or Memory-to-Memory with pixel format
00698   *                     conversion mode is selected, or configure
00699   *                     the color value if Register-to-Memory mode is selected.
00700   * @param  DstAddress The destination memory Buffer address.
00701   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00702   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00703   * @retval HAL status
00704   */
00705 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00706 {
00707   /* Check the parameters */
00708   assert_param(IS_DMA2D_LINE(Height));
00709   assert_param(IS_DMA2D_PIXEL(Width));
00710
00711   /* Process locked */
00712   __HAL_LOCK(hdma2d);
00713
00714   /* Change DMA2D peripheral state */
00715   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00716
00717   /* Configure the source, destination address and the data size */
00718   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00719
00720   /* Enable the transfer complete, transfer error and configuration error interrupts */
00721   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00722
00723   /* Enable the Peripheral */
00724   __HAL_DMA2D_ENABLE(hdma2d);
00725
00726   return HAL_OK;
00727 }
00728
00729 /**
00730   * @brief  Start the multi-source DMA2D Transfer.
00731   * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
00732   *                      the configuration information for the DMA2D.
00733   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00734   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00735   * @param  DstAddress  The destination memory Buffer address.
00736   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00737   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00738   * @retval HAL status
00739   */
00740 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00741 {
00742   /* Check the parameters */
00743   assert_param(IS_DMA2D_LINE(Height));
00744   assert_param(IS_DMA2D_PIXEL(Width));
00745
00746   /* Process locked */
00747   __HAL_LOCK(hdma2d);
00748
00749   /* Change DMA2D peripheral state */
00750   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00751
00752   if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
00753   {
00754     /*blending & fixed FG*/
00755     WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
00756     /* Configure the source, destination address and the data size */
00757     DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
00758   }
00759   else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
00760   {
00761     /*blending & fixed BG*/
00762     WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
00763     /* Configure the source, destination address and the data size */
00764     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00765   }
00766   else
00767   {
00768      /* Configure DMA2D Stream source2 address */
00769      WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00770
00771      /* Configure the source, destination address and the data size */
00772      DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00773   }
00774
00775   /* Enable the Peripheral */
00776   __HAL_DMA2D_ENABLE(hdma2d);
00777
00778   return HAL_OK;
00779 }
00780
00781 /**
00782   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00783   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00784   *                     the configuration information for the DMA2D.
00785   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00786   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00787   * @param  DstAddress  The destination memory Buffer address.
00788   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00789   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00790   * @retval HAL status
00791   */
00792 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00793 {
00794   /* Check the parameters */
00795   assert_param(IS_DMA2D_LINE(Height));
00796   assert_param(IS_DMA2D_PIXEL(Width));
00797
00798   /* Process locked */
00799   __HAL_LOCK(hdma2d);
00800
00801   /* Change DMA2D peripheral state */
00802   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00803
00804   if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
00805   {
00806     /*blending & fixed FG*/
00807     WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
00808     /* Configure the source, destination address and the data size */
00809     DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
00810   }
00811   else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
00812   {
00813     /*blending & fixed BG*/
00814     WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
00815     /* Configure the source, destination address and the data size */
00816     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00817   }
00818   else
00819   {
00820     WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00821
00822     /* Configure the source, destination address and the data size */
00823     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00824   }
00825
00826   /* Enable the transfer complete, transfer error and configuration error interrupts */
00827   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00828
00829   /* Enable the Peripheral */
00830   __HAL_DMA2D_ENABLE(hdma2d);
00831
00832   return HAL_OK;
00833 }
00834
00835 /**
00836   * @brief  Abort the DMA2D Transfer.
00837   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
00838   *                  the configuration information for the DMA2D.
00839   * @retval HAL status
00840   */
00841 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00842 {
00843   uint32_t tickstart;
00844
00845   /* Abort the DMA2D transfer */
00846   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00847      between the register read and the register write by the CPU (writing 0 has no
00848      effect on START bitvalue) */
00849    MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
00850
00851   /* Get tick */
00852   tickstart = HAL_GetTick();
00853
00854   /* Check if the DMA2D is effectively disabled */
00855   while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00856   {
00857     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00858     {
00859       /* Update error code */
00860       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00861
00862       /* Change the DMA2D state */
00863       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00864
00865       /* Process Unlocked */
00866       __HAL_UNLOCK(hdma2d);
00867
00868       return HAL_TIMEOUT;
00869     }
00870   }
00871
00872   /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
00873   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00874
00875   /* Change the DMA2D state*/
00876   hdma2d->State = HAL_DMA2D_STATE_READY;
00877
00878   /* Process Unlocked */
00879   __HAL_UNLOCK(hdma2d);
00880
00881   return HAL_OK;
00882 }
00883
00884 /**
00885   * @brief  Suspend the DMA2D Transfer.
00886   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00887   *                 the configuration information for the DMA2D.
00888   * @retval HAL status
00889   */
00890 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00891 {
00892   uint32_t tickstart;
00893
00894   /* Suspend the DMA2D transfer */
00895   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00896      between the register read and the register write by the CPU (writing 0 has no
00897      effect on START bitvalue). */
00898   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
00899
00900   /* Get tick */
00901   tickstart = HAL_GetTick();
00902
00903   /* Check if the DMA2D is effectively suspended */
00904   while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
00905   {
00906     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00907     {
00908       /* Update error code */
00909       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00910
00911       /* Change the DMA2D state */
00912       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00913
00914       return HAL_TIMEOUT;
00915     }
00916   }
00917
00918    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00919   if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00920   {
00921     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00922   }
00923   else
00924   {
00925     /* Make sure SUSP bit is cleared since it is meaningless
00926        when no tranfer is on-going */
00927     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00928   }
00929
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @brief  Resume the DMA2D Transfer.
00935   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00936   *                 the configuration information for the DMA2D.
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00940 {
00941   /* Check the SUSP and START bits */
00942   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
00943   {
00944     /* Ongoing transfer is suspended: change the DMA2D state before resuming */
00945     hdma2d->State = HAL_DMA2D_STATE_BUSY;
00946   }
00947
00948   /* Resume the DMA2D transfer */
00949   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00950      between the register read and the register write by the CPU (writing 0 has no
00951      effect on START bitvalue). */
00952   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
00953
00954   return HAL_OK;
00955 }
00956
00957
00958 /**
00959   * @brief  Enable the DMA2D CLUT Transfer.
00960   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00961   *                   the configuration information for the DMA2D.
00962   * @param  LayerIdx DMA2D Layer index.
00963   *                   This parameter can be one of the following values:
00964   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
00965   * @retval HAL status
00966   */
00967 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00968 {
00969   /* Check the parameters */
00970   assert_param(IS_DMA2D_LAYER(LayerIdx));
00971
00972   /* Process locked */
00973   __HAL_LOCK(hdma2d);
00974
00975   /* Change DMA2D peripheral state */
00976   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00977
00978   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
00979   {
00980     /* Enable the background CLUT loading */
00981     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00982   }
00983   else
00984   {
00985     /* Enable the foreground CLUT loading */
00986     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00987   }
00988
00989   return HAL_OK;
00990 }
00991
00992
00993 /**
00994   * @brief  Start DMA2D CLUT Loading.
00995   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00996   *                   the configuration information for the DMA2D.
00997   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00998   *                   the configuration information for the color look up table.
00999   * @param  LayerIdx DMA2D Layer index.
01000   *                   This parameter can be one of the following values:
01001   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01002   * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
01003   * @retval HAL status
01004   */
01005 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01006 {
01007   /* Check the parameters */
01008   assert_param(IS_DMA2D_LAYER(LayerIdx));
01009   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01010   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01011
01012   /* Process locked */
01013   __HAL_LOCK(hdma2d);
01014
01015   /* Change DMA2D peripheral state */
01016   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01017
01018   /* Configure the CLUT of the background DMA2D layer */
01019   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01020   {
01021     /* Write background CLUT memory address */
01022     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01023
01024     /* Write background CLUT size and CLUT color mode */
01025     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01026             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01027
01028     /* Enable the CLUT loading for the background */
01029     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
01030   }
01031   /* Configure the CLUT of the foreground DMA2D layer */
01032   else
01033   {
01034     /* Write foreground CLUT memory address */
01035     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01036
01037     /* Write foreground CLUT size and CLUT color mode */
01038     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01039             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01040
01041  /* Enable the CLUT loading for the foreground */
01042     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
01043   }
01044
01045   return HAL_OK;
01046 }
01047
01048 /**
01049   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
01050   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
01051   *                   the configuration information for the DMA2D.
01052   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01053   *                   the configuration information for the color look up table.
01054   * @param  LayerIdx DMA2D Layer index.
01055   *                   This parameter can be one of the following values:
01056   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01057   * @retval HAL status
01058   */
01059 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01060 {
01061   /* Check the parameters */
01062   assert_param(IS_DMA2D_LAYER(LayerIdx));
01063   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01064   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01065
01066   /* Process locked */
01067   __HAL_LOCK(hdma2d);
01068
01069   /* Change DMA2D peripheral state */
01070   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01071
01072   /* Configure the CLUT of the background DMA2D layer */
01073   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01074   {
01075     /* Write background CLUT memory address */
01076     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01077
01078     /* Write background CLUT size and CLUT color mode */
01079     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01080             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01081
01082     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
01083     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01084
01085     /* Enable the CLUT loading for the background */
01086     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
01087   }
01088   /* Configure the CLUT of the foreground DMA2D layer */
01089   else
01090   {
01091     /* Write foreground CLUT memory address */
01092     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01093
01094     /* Write foreground CLUT size and CLUT color mode */
01095     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01096             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01097
01098     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
01099     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01100
01101     /* Enable the CLUT loading for the foreground */
01102     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
01103   }
01104
01105   return HAL_OK;
01106 }
01107
01108 /**
01109   * @brief  Abort the DMA2D CLUT loading.
01110   * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
01111   *                  the configuration information for the DMA2D.
01112   * @param  LayerIdx DMA2D Layer index.
01113   *                   This parameter can be one of the following values:
01114   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01115   * @retval HAL status
01116   */
01117 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01118 {
01119   uint32_t tickstart;
01120   const __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
01121
01122   /* Abort the CLUT loading */
01123   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
01124
01125   /* If foreground CLUT loading is considered, update local variables */
01126   if(LayerIdx == DMA2D_FOREGROUND_LAYER)
01127   {
01128     reg  = &(hdma2d->Instance->FGPFCCR);
01129   }
01130
01131
01132   /* Get tick */
01133   tickstart = HAL_GetTick();
01134
01135   /* Check if the CLUT loading is aborted */
01136   while((*reg & DMA2D_BGPFCCR_START) != 0U)
01137   {
01138     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
01139     {
01140       /* Update error code */
01141       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01142
01143       /* Change the DMA2D state */
01144       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01145
01146       /* Process Unlocked */
01147       __HAL_UNLOCK(hdma2d);
01148
01149       return HAL_TIMEOUT;
01150     }
01151   }
01152
01153   /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
01154   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01155
01156   /* Change the DMA2D state*/
01157   hdma2d->State = HAL_DMA2D_STATE_READY;
01158
01159   /* Process Unlocked */
01160   __HAL_UNLOCK(hdma2d);
01161
01162   return HAL_OK;
01163 }
01164
01165 /**
01166   * @brief  Suspend the DMA2D CLUT loading.
01167   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01168   *                 the configuration information for the DMA2D.
01169   * @param  LayerIdx DMA2D Layer index.
01170   *                   This parameter can be one of the following values:
01171   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01172   * @retval HAL status
01173   */
01174 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01175 {
01176   uint32_t tickstart;
01177   uint32_t loadsuspended;
01178   const __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
01179
01180   /* Suspend the CLUT loading */
01181   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01182
01183   /* If foreground CLUT loading is considered, update local variables */
01184   if(LayerIdx == DMA2D_FOREGROUND_LAYER)
01185   {
01186     reg  = &(hdma2d->Instance->FGPFCCR);
01187   }
01188
01189   /* Get tick */
01190   tickstart = HAL_GetTick();
01191
01192   /* Check if the CLUT loading is suspended */
01193   loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
01194   loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
01195   while (loadsuspended == 0UL)
01196   {
01197     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
01198     {
01199       /* Update error code */
01200       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01201
01202       /* Change the DMA2D state */
01203       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01204
01205       return HAL_TIMEOUT;
01206     }
01207     loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
01208     loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
01209   }
01210
01211    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
01212   if ((*reg & DMA2D_BGPFCCR_START) != 0U)
01213   {
01214     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
01215   }
01216   else
01217   {
01218     /* Make sure SUSP bit is cleared since it is meaningless
01219        when no tranfer is on-going */
01220     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01221   }
01222
01223   return HAL_OK;
01224 }
01225
01226 /**
01227   * @brief  Resume the DMA2D CLUT loading.
01228   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01229   *                 the configuration information for the DMA2D.
01230   * @param  LayerIdx DMA2D Layer index.
01231   *                   This parameter can be one of the following values:
01232   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01233   * @retval HAL status
01234   */
01235 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01236 {
01237   /* Check the SUSP and START bits for background or foreground CLUT loading */
01238   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01239   {
01240     /* Background CLUT loading suspension check */
01241     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
01242     {
01243       if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
01244       {
01245       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
01246       hdma2d->State = HAL_DMA2D_STATE_BUSY;
01247     }
01248   }
01249   }
01250   else
01251   {
01252     /* Foreground CLUT loading suspension check */
01253     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
01254     {
01255       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
01256       {
01257       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
01258       hdma2d->State = HAL_DMA2D_STATE_BUSY;
01259     }
01260   }
01261   }
01262
01263   /* Resume the CLUT loading */
01264   CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01265
01266   return HAL_OK;
01267 }
01268
01269
01270 /**
01271
01272   * @brief  Polling for transfer complete or CLUT loading.
01273   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01274   *                 the configuration information for the DMA2D.
01275   * @param  Timeout Timeout duration
01276   * @retval HAL status
01277   */
01278 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
01279 {
01280   uint32_t tickstart;
01281   uint32_t layer_start;
01282   __IO uint32_t isrflags = 0x0U;
01283
01284   /* Polling for DMA2D transfer */
01285   if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
01286   {
01287    /* Get tick */
01288    tickstart = HAL_GetTick();
01289
01290     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
01291     {
01292       isrflags = READ_REG(hdma2d->Instance->ISR);
01293       if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
01294       {
01295         if ((isrflags & DMA2D_FLAG_CE) != 0U)
01296         {
01297           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01298         }
01299         if ((isrflags & DMA2D_FLAG_TE) != 0U)
01300         {
01301           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01302         }
01303         /* Clear the transfer and configuration error flags */
01304         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01305
01306         /* Change DMA2D state */
01307         hdma2d->State = HAL_DMA2D_STATE_ERROR;
01308
01309         /* Process unlocked */
01310         __HAL_UNLOCK(hdma2d);
01311
01312         return HAL_ERROR;
01313       }
01314       /* Check for the Timeout */
01315       if(Timeout != HAL_MAX_DELAY)
01316       {
01317         if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01318         {
01319           /* Update error code */
01320           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01321
01322           /* Change the DMA2D state */
01323           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01324
01325           /* Process unlocked */
01326           __HAL_UNLOCK(hdma2d);
01327
01328           return HAL_TIMEOUT;
01329         }
01330       }
01331     }
01332   }
01333   /* Polling for CLUT loading (foreground or background) */
01334   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
01335   layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
01336   if (layer_start != 0U)
01337   {
01338     /* Get tick */
01339     tickstart = HAL_GetTick();
01340
01341     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
01342     {
01343       isrflags = READ_REG(hdma2d->Instance->ISR);
01344       if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
01345       {
01346         if ((isrflags & DMA2D_FLAG_CAE) != 0U)
01347         {
01348           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01349         }
01350         if ((isrflags & DMA2D_FLAG_CE) != 0U)
01351         {
01352           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01353         }
01354         if ((isrflags & DMA2D_FLAG_TE) != 0U)
01355         {
01356           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01357         }
01358         /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
01359         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01360
01361         /* Change DMA2D state */
01362         hdma2d->State= HAL_DMA2D_STATE_ERROR;
01363
01364         /* Process unlocked */
01365         __HAL_UNLOCK(hdma2d);
01366
01367         return HAL_ERROR;
01368       }
01369       /* Check for the Timeout */
01370       if(Timeout != HAL_MAX_DELAY)
01371       {
01372         if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01373         {
01374           /* Update error code */
01375           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01376
01377           /* Change the DMA2D state */
01378           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
01379
01380           /* Process unlocked */
01381           __HAL_UNLOCK(hdma2d);
01382
01383           return HAL_TIMEOUT;
01384         }
01385       }
01386     }
01387   }
01388
01389   /* Clear the transfer complete and CLUT loading flags */
01390   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
01391
01392   /* Change DMA2D state */
01393   hdma2d->State = HAL_DMA2D_STATE_READY;
01394
01395   /* Process unlocked */
01396   __HAL_UNLOCK(hdma2d);
01397
01398   return HAL_OK;
01399 }
01400 /**
01401   * @brief  Handle DMA2D interrupt request.
01402   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01403   *                 the configuration information for the DMA2D.
01404   * @retval HAL status
01405   */
01406 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
01407 {
01408   uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
01409   uint32_t crflags = READ_REG(hdma2d->Instance->CR);
01410
01411   /* Transfer Error Interrupt management ***************************************/
01412   if ((isrflags & DMA2D_FLAG_TE) != 0U)
01413   {
01414     if ((crflags & DMA2D_IT_TE) != 0U)
01415     {
01416       /* Disable the transfer Error interrupt */
01417       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
01418
01419       /* Update error code */
01420       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01421
01422       /* Clear the transfer error flag */
01423       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
01424
01425       /* Change DMA2D state */
01426       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01427
01428       /* Process Unlocked */
01429       __HAL_UNLOCK(hdma2d);
01430
01431       if(hdma2d->XferErrorCallback != NULL)
01432       {
01433         /* Transfer error Callback */
01434         hdma2d->XferErrorCallback(hdma2d);
01435       }
01436     }
01437   }
01438   /* Configuration Error Interrupt management **********************************/
01439   if ((isrflags & DMA2D_FLAG_CE) != 0U)
01440   {
01441     if ((crflags & DMA2D_IT_CE) != 0U)
01442     {
01443       /* Disable the Configuration Error interrupt */
01444       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
01445
01446       /* Clear the Configuration error flag */
01447       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
01448
01449       /* Update error code */
01450       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01451
01452       /* Change DMA2D state */
01453       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01454
01455       /* Process Unlocked */
01456       __HAL_UNLOCK(hdma2d);
01457
01458       if(hdma2d->XferErrorCallback != NULL)
01459       {
01460         /* Transfer error Callback */
01461         hdma2d->XferErrorCallback(hdma2d);
01462       }
01463     }
01464   }
01465   /* CLUT access Error Interrupt management ***********************************/
01466   if ((isrflags & DMA2D_FLAG_CAE) != 0U)
01467   {
01468     if ((crflags & DMA2D_IT_CAE) != 0U)
01469     {
01470       /* Disable the CLUT access error interrupt */
01471       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
01472
01473       /* Clear the CLUT access error flag */
01474       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
01475
01476       /* Update error code */
01477       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01478
01479       /* Change DMA2D state */
01480       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01481
01482       /* Process Unlocked */
01483       __HAL_UNLOCK(hdma2d);
01484
01485       if(hdma2d->XferErrorCallback != NULL)
01486       {
01487         /* Transfer error Callback */
01488         hdma2d->XferErrorCallback(hdma2d);
01489       }
01490     }
01491   }
01492   /* Transfer watermark Interrupt management **********************************/
01493   if ((isrflags & DMA2D_FLAG_TW) != 0U)
01494   {
01495     if ((crflags & DMA2D_IT_TW) != 0U)
01496     {
01497       /* Disable the transfer watermark interrupt */
01498       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
01499
01500       /* Clear the transfer watermark flag */
01501       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
01502
01503       /* Transfer watermark Callback */
01504 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
01505       hdma2d->LineEventCallback(hdma2d);
01506 #else
01507       HAL_DMA2D_LineEventCallback(hdma2d);
01508 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
01509
01510     }
01511   }
01512   /* Transfer Complete Interrupt management ************************************/
01513   if ((isrflags & DMA2D_FLAG_TC) != 0U)
01514   {
01515     if ((crflags & DMA2D_IT_TC) != 0U)
01516     {
01517       /* Disable the transfer complete interrupt */
01518       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
01519
01520       /* Clear the transfer complete flag */
01521       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
01522
01523       /* Update error code */
01524       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01525
01526       /* Change DMA2D state */
01527       hdma2d->State = HAL_DMA2D_STATE_READY;
01528
01529       /* Process Unlocked */
01530       __HAL_UNLOCK(hdma2d);
01531
01532       if(hdma2d->XferCpltCallback != NULL)
01533       {
01534         /* Transfer complete Callback */
01535         hdma2d->XferCpltCallback(hdma2d);
01536       }
01537     }
01538   }
01539   /* CLUT Transfer Complete Interrupt management ******************************/
01540   if ((isrflags & DMA2D_FLAG_CTC) != 0U)
01541   {
01542     if ((crflags & DMA2D_IT_CTC) != 0U)
01543     {
01544       /* Disable the CLUT transfer complete interrupt */
01545       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
01546
01547       /* Clear the CLUT transfer complete flag */
01548       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
01549
01550       /* Update error code */
01551       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01552
01553       /* Change DMA2D state */
01554       hdma2d->State = HAL_DMA2D_STATE_READY;
01555
01556       /* Process Unlocked */
01557       __HAL_UNLOCK(hdma2d);
01558
01559       /* CLUT Transfer complete Callback */
01560 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
01561       hdma2d->CLUTLoadingCpltCallback(hdma2d);
01562 #else
01563       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
01564 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
01565     }
01566   }
01567
01568 }
01569
01570 /**
01571   * @brief  Transfer watermark callback.
01572   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01573   *                 the configuration information for the DMA2D.
01574   * @retval None
01575   */
01576 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
01577 {
01578   /* Prevent unused argument(s) compilation warning */
01579   UNUSED(hdma2d);
01580
01581   /* NOTE : This function should not be modified; when the callback is needed,
01582             the HAL_DMA2D_LineEventCallback can be implemented in the user file.
01583    */
01584 }
01585
01586 /**
01587   * @brief  CLUT Transfer Complete callback.
01588   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01589   *                 the configuration information for the DMA2D.
01590   * @retval None
01591   */
01592 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
01593 {
01594   /* Prevent unused argument(s) compilation warning */
01595   UNUSED(hdma2d);
01596
01597   /* NOTE : This function should not be modified; when the callback is needed,
01598             the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
01599    */
01600 }
01601
01602 /**
01603   * @}
01604   */
01605
01606 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
01607  *  @brief    Peripheral Control functions
01608  *
01609 @verbatim
01610  ===============================================================================
01611                     ##### Peripheral Control functions #####
01612  ===============================================================================
01613     [..]  This section provides functions allowing to:
01614       (+) Configure the DMA2D foreground or background layer parameters.
01615       (+) Configure the DMA2D CLUT transfer.
01616       (+) Configure the line watermark
01617       (+) Configure the dead time value.
01618       (+) Enable or disable the dead time value functionality.
01619
01620
01621 @endverbatim
01622   * @{
01623   */
01624
01625 /**
01626   * @brief  Configure the DMA2D Layer according to the specified
01627   *         parameters in the DMA2D_HandleTypeDef.
01628   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01629   *                 the configuration information for the DMA2D.
01630   * @param  LayerIdx DMA2D Layer index.
01631   *                   This parameter can be one of the following values:
01632   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01633   * @retval HAL status
01634   */
01635 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01636 {
01637   DMA2D_LayerCfgTypeDef *pLayerCfg;
01638   uint32_t regMask, regValue;
01639
01640   /* Check the parameters */
01641   assert_param(IS_DMA2D_LAYER(LayerIdx));
01642   assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
01643   if(hdma2d->Init.Mode != DMA2D_R2M)
01644   {
01645     assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
01646     if(hdma2d->Init.Mode != DMA2D_M2M)
01647     {
01648       assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
01649     }
01650   }
01651   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
01652   assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
01653
01654   if((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
01655   {
01656     assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling));
01657   }
01658
01659   /* Process locked */
01660   __HAL_LOCK(hdma2d);
01661
01662   /* Change DMA2D peripheral state */
01663   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01664
01665   pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
01666
01667   /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
01668   regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
01669              (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
01670   regMask  = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
01671
01672
01673   if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01674   {
01675     regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
01676   }
01677   else
01678   {
01679     regValue |=  (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
01680   }
01681
01682   /* Configure the background DMA2D layer */
01683   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01684   {
01685     /* Write DMA2D BGPFCCR register */
01686     MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
01687
01688     /* DMA2D BGOR register configuration -------------------------------------*/
01689     WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
01690
01691     /* DMA2D BGCOLR register configuration -------------------------------------*/
01692     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01693     {
01694       WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
01695     }
01696   }
01697   /* Configure the foreground DMA2D layer */
01698   else
01699   {
01700
01701     if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
01702     {
01703       regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos);
01704       regMask  |= DMA2D_FGPFCCR_CSS;
01705     }
01706
01707      /* Write DMA2D FGPFCCR register */
01708     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
01709
01710     /* DMA2D FGOR register configuration -------------------------------------*/
01711     WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
01712
01713     /* DMA2D FGCOLR register configuration -------------------------------------*/
01714     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01715     {
01716       WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
01717     }
01718   }
01719   /* Initialize the DMA2D state*/
01720   hdma2d->State = HAL_DMA2D_STATE_READY;
01721
01722   /* Process unlocked */
01723   __HAL_UNLOCK(hdma2d);
01724
01725   return HAL_OK;
01726 }
01727
01728 /**
01729   * @brief  Configure the DMA2D CLUT Transfer.
01730   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
01731   *                   the configuration information for the DMA2D.
01732   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01733   *                   the configuration information for the color look up table.
01734   * @param  LayerIdx DMA2D Layer index.
01735   *                   This parameter can be one of the following values:
01736   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01737   * @retval HAL status
01738   */
01739 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01740 {
01741   /* Check the parameters */
01742   assert_param(IS_DMA2D_LAYER(LayerIdx));
01743   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01744   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01745
01746   /* Process locked */
01747   __HAL_LOCK(hdma2d);
01748
01749   /* Change DMA2D peripheral state */
01750   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01751
01752   /* Configure the CLUT of the background DMA2D layer */
01753   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01754   {
01755     /* Write background CLUT memory address */
01756     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01757
01758     /* Write background CLUT size and CLUT color mode */
01759     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01760             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01761  }
01762  /* Configure the CLUT of the foreground DMA2D layer */
01763  else
01764  {
01765    /* Write foreground CLUT memory address */
01766     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01767
01768     /* Write foreground CLUT size and CLUT color mode */
01769     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01770             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01771   }
01772
01773   /* Set the DMA2D state to Ready*/
01774   hdma2d->State = HAL_DMA2D_STATE_READY;
01775
01776   /* Process unlocked */
01777   __HAL_UNLOCK(hdma2d);
01778
01779   return HAL_OK;
01780 }
01781
01782
01783 /**
01784   * @brief  Configure the line watermark.
01785   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01786   *                 the configuration information for the DMA2D.
01787   * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
01788   * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
01789   * @note   The transfer watermark interrupt is disabled once it has occurred.
01790   * @retval HAL status
01791   */
01792
01793 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01794 {
01795   /* Check the parameters */
01796   assert_param(IS_DMA2D_LINEWATERMARK(Line));
01797
01798   if (Line > DMA2D_LWR_LW)
01799   {
01800     return HAL_ERROR;
01801   }
01802   else
01803   {
01804     /* Process locked */
01805     __HAL_LOCK(hdma2d);
01806
01807     /* Change DMA2D peripheral state */
01808     hdma2d->State = HAL_DMA2D_STATE_BUSY;
01809
01810     /* Sets the Line watermark configuration */
01811     WRITE_REG(hdma2d->Instance->LWR, Line);
01812
01813     /* Enable the Line interrupt */
01814     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
01815
01816     /* Initialize the DMA2D state*/
01817     hdma2d->State = HAL_DMA2D_STATE_READY;
01818
01819     /* Process unlocked */
01820     __HAL_UNLOCK(hdma2d);
01821
01822     return HAL_OK;
01823   }
01824 }
01825
01826 /**
01827   * @brief Enable DMA2D dead time feature.
01828   * @param hdma2d DMA2D handle.
01829   * @retval HAL status
01830   */
01831 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01832 {
01833   /* Process Locked */
01834   __HAL_LOCK(hdma2d);
01835
01836   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01837
01838   /* Set DMA2D_AMTCR EN bit */
01839   SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01840
01841   hdma2d->State = HAL_DMA2D_STATE_READY;
01842
01843   /* Process Unlocked */
01844   __HAL_UNLOCK(hdma2d);
01845
01846   return HAL_OK;
01847 }
01848
01849 /**
01850   * @brief Disable DMA2D dead time feature.
01851   * @param hdma2d DMA2D handle.
01852   * @retval HAL status
01853   */
01854 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01855 {
01856   /* Process Locked */
01857   __HAL_LOCK(hdma2d);
01858
01859   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01860
01861   /* Clear DMA2D_AMTCR EN bit */
01862   CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01863
01864   hdma2d->State = HAL_DMA2D_STATE_READY;
01865
01866   /* Process Unlocked */
01867   __HAL_UNLOCK(hdma2d);
01868
01869   return HAL_OK;
01870 }
01871
01872 /**
01873   * @brief Configure dead time.
01874   * @note The dead time value represents the guaranteed minimum number of cycles between
01875   *       two consecutive transactions on the AHB bus.
01876   * @param hdma2d DMA2D handle.
01877   * @param DeadTime dead time value.
01878   * @retval HAL status
01879   */
01880 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
01881 {
01882   /* Process Locked */
01883   __HAL_LOCK(hdma2d);
01884
01885   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01886
01887   /* Set DMA2D_AMTCR DT field */
01888   MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
01889
01890   hdma2d->State = HAL_DMA2D_STATE_READY;
01891
01892   /* Process Unlocked */
01893   __HAL_UNLOCK(hdma2d);
01894
01895   return HAL_OK;
01896 }
01897
01898 /**
01899   * @}
01900   */
01901
01902
01903 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
01904  *  @brief    Peripheral State functions
01905  *
01906 @verbatim
01907  ===============================================================================
01908                   ##### Peripheral State and Errors functions #####
01909  ===============================================================================
01910     [..]
01911     This subsection provides functions allowing to:
01912       (+) Get the DMA2D state
01913       (+) Get the DMA2D error code
01914
01915 @endverbatim
01916   * @{
01917   */
01918
01919 /**
01920   * @brief  Return the DMA2D state
01921   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01922   *                 the configuration information for the DMA2D.
01923   * @retval HAL state
01924   */
01925 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01926 {
01927   return hdma2d->State;
01928 }
01929
01930 /**
01931   * @brief  Return the DMA2D error code
01932   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
01933   *               the configuration information for DMA2D.
01934   * @retval DMA2D Error Code
01935   */
01936 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01937 {
01938   return hdma2d->ErrorCode;
01939 }
01940
01941 /**
01942   * @}
01943   */
01944
01945 /**
01946   * @}
01947   */
01948
01949
01950 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
01951   * @{
01952   */
01953
01954 /**
01955   * @brief  Set the DMA2D transfer parameters.
01956   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
01957   *                     the configuration information for the specified DMA2D.
01958   * @param  pdata      The source memory Buffer address
01959   * @param  DstAddress The destination memory Buffer address
01960   * @param  Width      The width of data to be transferred from source to destination.
01961   * @param  Height     The height of data to be transferred from source to destination.
01962   * @retval HAL status
01963   */
01964 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01965 {
01966   uint32_t tmp;
01967   uint32_t tmp1;
01968   uint32_t tmp2;
01969   uint32_t tmp3;
01970   uint32_t tmp4;
01971
01972   /* Configure DMA2D data size */
01973   MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
01974
01975   /* Configure DMA2D destination address */
01976   WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
01977
01978   /* Register to memory DMA2D mode selected */
01979   if (hdma2d->Init.Mode == DMA2D_R2M)
01980   {
01981     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01982     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01983     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01984     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01985
01986     /* Prepare the value to be written to the OCOLR register according to the color mode */
01987     if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
01988     {
01989       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01990     }
01991     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
01992     {
01993       tmp = (tmp3 | tmp2 | tmp4);
01994     }
01995     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
01996     {
01997       tmp2 = (tmp2 >> 19U);
01998       tmp3 = (tmp3 >> 10U);
01999       tmp4 = (tmp4 >> 3U );
02000       tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
02001     }
02002     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
02003     {
02004       tmp1 = (tmp1 >> 31U);
02005       tmp2 = (tmp2 >> 19U);
02006       tmp3 = (tmp3 >> 11U);
02007       tmp4 = (tmp4 >> 3U );
02008       tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
02009     }
02010     else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
02011     {
02012       tmp1 = (tmp1 >> 28U);
02013       tmp2 = (tmp2 >> 20U);
02014       tmp3 = (tmp3 >> 12U);
02015       tmp4 = (tmp4 >> 4U );
02016       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
02017     }
02018     /* Write to DMA2D OCOLR register */
02019     WRITE_REG(hdma2d->Instance->OCOLR, tmp);
02020   }
02021   else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
02022   {
02023     WRITE_REG(hdma2d->Instance->BGMAR , pdata);
02024   }
02025   else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
02026   {
02027     /* Configure DMA2D source address */
02028     WRITE_REG(hdma2d->Instance->FGMAR, pdata);
02029   }
02030 }
02031
02032 /**
02033   * @}
02034   */
02035
02036 /**
02037   * @}
02038   */
02039
02040 /**
02041   * @}
02042   */
02043 #endif /* DMA2D */
02044 #endif /* HAL_DMA2D_MODULE_ENABLED */
02045
02046 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma2d.h Source File

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stm32h7xx_hal_dma2d.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma2d.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA2D HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DMA2D_H
00022 #define STM32H7xx_HAL_DMA2D_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 #if defined (DMA2D)
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32h7xx_hal_def.h"
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup DMA2D DMA2D
00038   * @brief DMA2D HAL module driver
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
00044   * @{
00045   */
00046 #define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
00047
00048 /**
00049   * @brief DMA2D CLUT Structure definition
00050   */
00051 typedef struct
00052 {
00053   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
00054
00055   uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
00056                                          This parameter can be one value of @ref DMA2D_CLUT_CM. */
00057
00058   uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
00059                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00060 } DMA2D_CLUTCfgTypeDef;
00061
00062 /**
00063   * @brief DMA2D Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
00068                                                 This parameter can be one value of @ref DMA2D_Mode. */
00069
00070   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
00071                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
00072
00073   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
00074                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00075   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
00076                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
00077
00078   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
00079                                                for the output pixel format converter.
00080                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
00081
00082
00083   uint32_t             BytesSwap;         /*!< Select byte regular mode or bytes swap mode (two by two).
00084                                                This parameter can be one value of @ref DMA2D_Bytes_Swap. */
00085
00086   uint32_t             LineOffsetMode;    /*!< Configures how is expressed the line offset for the foreground, background and output.
00087                                                This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
00088
00089 } DMA2D_InitTypeDef;
00090
00091
00092 /**
00093   * @brief DMA2D Layer structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
00098                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00099
00100   uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
00101                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
00102
00103   uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
00104                                                This parameter can be one value of @ref DMA2D_Alpha_Mode. */
00105
00106   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
00107                                                This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
00108                                                @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
00109                                                Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
00110                                                - InputAlpha[24:31] is the alpha value ALPHA[0:7]
00111                                                - InputAlpha[16:23] is the red value RED[0:7]
00112                                                - InputAlpha[8:15] is the green value GREEN[0:7]
00113                                                - InputAlpha[0:7] is the blue value BLUE[0:7]. */
00114   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
00115                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
00116
00117   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
00118                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
00119
00120   uint32_t             ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
00121                                                This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
00122
00123 } DMA2D_LayerCfgTypeDef;
00124
00125 /**
00126   * @brief  HAL DMA2D State structures definition
00127   */
00128 typedef enum
00129 {
00130   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
00131   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00132   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00133   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00134   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
00135   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
00136 }HAL_DMA2D_StateTypeDef;
00137
00138 /**
00139   * @brief  DMA2D handle Structure definition
00140   */
00141 typedef struct __DMA2D_HandleTypeDef
00142 {
00143   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
00144
00145   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
00146
00147   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
00148
00149   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
00150
00151 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00152   void                        (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D line event callback.      */
00153
00154   void                        (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
00155
00156   void                        (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D Msp Init callback.          */
00157
00158   void                        (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback.        */
00159
00160 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
00161
00162   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
00163
00164   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
00165
00166   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
00167
00168   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
00169 } DMA2D_HandleTypeDef;
00170
00171 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00172 /**
00173   * @brief  HAL DMA2D Callback pointer definition
00174   */
00175 typedef  void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
00176 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00177 /**
00178   * @}
00179   */
00180
00181 /* Exported constants --------------------------------------------------------*/
00182 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
00183   * @{
00184   */
00185
00186 /** @defgroup DMA2D_Error_Code DMA2D Error Code
00187   * @{
00188   */
00189 #define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */
00190 #define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */
00191 #define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */
00192 #define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */
00193 #define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */
00194 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00195 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */
00196 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup DMA2D_Mode DMA2D Mode
00203   * @{
00204   */
00205 #define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
00206 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
00207 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
00208 #define DMA2D_R2M                   (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
00209 #define DMA2D_M2M_BLEND_FG          DMA2D_CR_MODE_2                     /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
00210 #define DMA2D_M2M_BLEND_BG          (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
00216   * @{
00217   */
00218 #define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
00219 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
00220 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
00221 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
00222 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
00228   * @{
00229   */
00230 #define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */
00231 #define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */
00232 #define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */
00233 #define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */
00234 #define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */
00235 #define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */
00236 #define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */
00237 #define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */
00238 #define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */
00239 #define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */
00240 #define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */
00241 #define DMA2D_INPUT_YCBCR           0x0000000BU  /*!< YCbCr color mode */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
00247   * @{
00248   */
00249 #define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value */
00250 #define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */
00251 #define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value
00252                                                                 with original alpha channel value                              */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
00258   * @{
00259   */
00260 #define DMA2D_REGULAR_ALPHA         0x00000000U  /*!< No modification of the alpha channel value */
00261 #define DMA2D_INVERTED_ALPHA        0x00000001U  /*!< Invert the alpha channel value */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
00267   * @{
00268   */
00269 #define DMA2D_RB_REGULAR            0x00000000U  /*!< Select regular mode (RGB or ARGB) */
00270 #define DMA2D_RB_SWAP               0x00000001U  /*!< Select swap mode (BGR or ABGR) */
00271 /**
00272   * @}
00273   */
00274
00275
00276
00277 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
00278   * @{
00279   */
00280 #define DMA2D_LOM_PIXELS            0x00000000U   /*!< Line offsets expressed in pixels */
00281 #define DMA2D_LOM_BYTES             DMA2D_CR_LOM  /*!< Line offsets expressed in bytes */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
00287   * @{
00288   */
00289 #define DMA2D_BYTES_REGULAR         0x00000000U      /*!< Bytes in regular order in output FIFO */
00290 #define DMA2D_BYTES_SWAP            DMA2D_OPFCCR_SB  /*!< Bytes are swapped two by two in output FIFO */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
00296   * @{
00297   */
00298 #define DMA2D_NO_CSS               0x00000000U  /*!< No chroma sub-sampling 4:4:4 */
00299 #define DMA2D_CSS_422              0x00000001U  /*!< chroma sub-sampling 4:2:2 */
00300 #define DMA2D_CSS_420              0x00000002U  /*!< chroma sub-sampling 4:2:0 */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
00306   * @{
00307   */
00308 #define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */
00309 #define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
00315   * @{
00316   */
00317 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
00318 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
00319 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
00320 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
00321 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
00322 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup DMA2D_Flags DMA2D Flags
00328   * @{
00329   */
00330 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
00331 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
00332 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
00333 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
00334 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
00335 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup DMA2D_Aliases DMA2D API Aliases
00341   * @{
00342   */
00343 #define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
00344 /**
00345   * @}
00346   */
00347
00348 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00349 /**
00350   * @brief  HAL DMA2D common Callback ID enumeration definition
00351   */
00352 typedef enum
00353 {
00354   HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */
00355   HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */
00356   HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */
00357   HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */
00358   HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */
00359   HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */
00360 }HAL_DMA2D_CallbackIDTypeDef;
00361 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00362
00363
00364 /**
00365   * @}
00366   */
00367 /* Exported macros ------------------------------------------------------------*/
00368 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
00369   * @{
00370   */
00371
00372 /** @brief Reset DMA2D handle state
00373   * @param  __HANDLE__ specifies the DMA2D handle.
00374   * @retval None
00375   */
00376 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00377 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00378                                                       (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
00379                                                       (__HANDLE__)->MspInitCallback = NULL;       \
00380                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
00381                                                      }while(0)
00382 #else
00383 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
00384 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00385
00386
00387 /**
00388   * @brief  Enable the DMA2D.
00389   * @param  __HANDLE__ DMA2D handle
00390   * @retval None.
00391   */
00392 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
00393
00394
00395 /* Interrupt & Flag management */
00396 /**
00397   * @brief  Get the DMA2D pending flags.
00398   * @param  __HANDLE__ DMA2D handle
00399   * @param  __FLAG__ flag to check.
00400   *          This parameter can be any combination of the following values:
00401   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00402   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
00403   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
00404   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00405   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00406   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00407   * @retval The state of FLAG.
00408   */
00409 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00410
00411 /**
00412   * @brief  Clear the DMA2D pending flags.
00413   * @param  __HANDLE__ DMA2D handle
00414   * @param  __FLAG__ specifies the flag to clear.
00415   *          This parameter can be any combination of the following values:
00416   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00417   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
00418   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
00419   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00420   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00421   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00422   * @retval None
00423   */
00424 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
00425
00426 /**
00427   * @brief  Enable the specified DMA2D interrupts.
00428   * @param  __HANDLE__ DMA2D handle
00429   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
00430   *          This parameter can be any combination of the following values:
00431   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00432   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00433   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00434   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00435   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00436   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00437   * @retval None
00438   */
00439 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00440
00441 /**
00442   * @brief  Disable the specified DMA2D interrupts.
00443   * @param  __HANDLE__ DMA2D handle
00444   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
00445   *          This parameter can be any combination of the following values:
00446   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00447   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00448   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00449   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00450   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00451   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00452   * @retval None
00453   */
00454 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00455
00456 /**
00457   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
00458   * @param  __HANDLE__ DMA2D handle
00459   * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.
00460   *          This parameter can be one of the following values:
00461   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00462   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00463   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00464   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00465   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00466   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00467   * @retval The state of INTERRUPT source.
00468   */
00469 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00470
00471 /**
00472   * @}
00473   */
00474
00475 /* Exported functions --------------------------------------------------------*/
00476 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
00477   * @{
00478   */
00479
00480 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00481   * @{
00482   */
00483
00484 /* Initialization and de-initialization functions *******************************/
00485 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
00486 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
00487 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
00488 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
00489 /* Callbacks Register/UnRegister functions  ***********************************/
00490 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00491 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
00492 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
00493 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00494
00495 /**
00496   * @}
00497   */
00498
00499
00500 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
00501   * @{
00502   */
00503
00504 /* IO operation functions *******************************************************/
00505 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00506 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
00507 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00508 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00509 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
00510 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
00511 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
00512 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00513 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00514 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00515 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00516 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00517 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00518 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
00519 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
00520 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
00521 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
00522
00523 /**
00524   * @}
00525   */
00526
00527 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
00528   * @{
00529   */
00530
00531 /* Peripheral Control functions *************************************************/
00532 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00533 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00534 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
00535 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
00536 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
00537 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
00538
00539 /**
00540   * @}
00541   */
00542
00543 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
00544   * @{
00545   */
00546
00547 /* Peripheral State functions ***************************************************/
00548 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
00549 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
00550
00551 /**
00552   * @}
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /* Private constants ---------------------------------------------------------*/
00560
00561 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
00562   * @{
00563   */
00564
00565 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
00566   * @{
00567   */
00568 #define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup DMA2D_Color_Value DMA2D Color Value
00574   * @{
00575   */
00576 #define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
00582   * @{
00583   */
00584 #define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup DMA2D_Layers DMA2D Layers
00590   * @{
00591   */
00592 #define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */
00593 #define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */
00594 /**
00595   * @}
00596   */
00597
00598 /** @defgroup DMA2D_Offset DMA2D Offset
00599   * @{
00600   */
00601 #define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup DMA2D_Size DMA2D Size
00607   * @{
00608   */
00609 #define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
00610 #define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
00611 /**
00612   * @}
00613   */
00614
00615 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
00616   * @{
00617   */
00618 #define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */
00619 /**
00620   * @}
00621   */
00622
00623 /**
00624   * @}
00625   */
00626
00627
00628 /* Private macros ------------------------------------------------------------*/
00629 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
00630   * @{
00631   */
00632 #define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
00633
00634 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)          || ((MODE) == DMA2D_M2M_PFC) || \
00635                                                ((MODE) == DMA2D_M2M_BLEND)    || ((MODE) == DMA2D_R2M)     || \
00636                                                ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
00637
00638 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
00639                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
00640                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
00641
00642 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
00643 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
00644 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
00645 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
00646
00647 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
00648                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
00649                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
00650                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
00651                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
00652                                                ((INPUT_CM) == DMA2D_INPUT_A4)       || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
00653
00654 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
00655                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
00656                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
00657
00658 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
00659                                                  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
00660
00661 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
00662                                    ((RB_Swap) == DMA2D_RB_SWAP))
00663
00664 #define IS_DMA2D_LOM_MODE(LOM)          (((LOM) == DMA2D_LOM_PIXELS) || \
00665                                          ((LOM) == DMA2D_LOM_BYTES))
00666
00667 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
00668                                          ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
00669
00670 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS)  || \
00671                                            ((CSS) == DMA2D_CSS_422) || \
00672                                            ((CSS) == DMA2D_CSS_420))
00673
00674 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
00675 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
00676 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
00677 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
00678                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
00679                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
00680 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
00681                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
00682                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
00683 /**
00684   * @}
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /**
00692   * @}
00693   */
00694
00695 #endif /* defined (DMA2D) */
00696
00697 #ifdef __cplusplus
00698 }
00699 #endif
00700
00701 #endif /* STM32H7xx_HAL_DMA2D_H */
00702
00703
00704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma.c Source File

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stm32h7xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Direct Memory Access (DMA) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and errors functions
00011   @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016    (#) Enable and configure the peripheral to be connected to the DMA Stream
00017        (except for internal SRAM/FLASH memories: no initialization is
00018        necessary) please refer to Reference manual for connection between peripherals
00019        and DMA requests .
00020
00021    (#) For a given Stream, program the required configuration through the following parameters:
00022        Transfer Direction, Source and Destination data formats,
00023        Circular, Normal or peripheral flow control mode, Stream Priority level,
00024        Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
00025        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
00026
00027      *** Polling mode IO operation ***
00028      =================================
00029     [..]
00030           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00031               address and destination address and the Length of data to be transferred
00032           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00033               case a fixed Timeout can be configured by User depending from his application.
00034
00035      *** Interrupt mode IO operation ***
00036      ===================================
00037     [..]
00038           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00039           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00040           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00041               Source address and destination address and the Length of data to be transferred. In this
00042               case the DMA interrupt is configured
00043           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00044           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00045               add his own function by customization of function pointer XferCpltCallback and
00046               XferErrorCallback (i.e a member of DMA handle structure).
00047     [..]
00048      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00049          detection.
00050
00051      (#) Use HAL_DMA_Abort() function to abort the current transfer
00052
00053      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00054
00055      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
00056            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
00057            Half-Word data size for the peripheral to access its data register and set Word data size
00058            for the Memory to gain in access time. Each two half words will be packed and written in
00059            a single access to a Word in the Memory).
00060
00061      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
00062            and Destination. In this case the Peripheral Data Size will be applied to both Source
00063            and Destination.
00064
00065      *** DMA HAL driver macros list ***
00066      =============================================
00067      [..]
00068        Below the list of most used macros in DMA HAL driver.
00069
00070       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
00071       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
00072       (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
00073       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
00074       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
00075       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
00076
00077      [..]
00078       (@) You can refer to the DMA HAL driver header file for more useful macros.
00079
00080   @endverbatim
00081   ******************************************************************************
00082   * @attention
00083   *
00084   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00085   * All rights reserved.</center></h2>
00086   *
00087   * This software component is licensed by ST under BSD 3-Clause license,
00088   * the "License"; You may not use this file except in compliance with the
00089   * License. You may obtain a copy of the License at:
00090   *                        opensource.org/licenses/BSD-3-Clause
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32h7xx_hal.h"
00097
00098 /** @addtogroup STM32H7xx_HAL_Driver
00099   * @{
00100   */
00101
00102 /** @defgroup DMA DMA
00103   * @brief DMA HAL module driver
00104   * @{
00105   */
00106
00107 #ifdef HAL_DMA_MODULE_ENABLED
00108
00109 /* Private types -------------------------------------------------------------*/
00110 typedef struct
00111 {
00112   __IO uint32_t ISR;   /*!< DMA interrupt status register */
00113   __IO uint32_t Reserved0;
00114   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
00115 } DMA_Base_Registers;
00116
00117 typedef struct
00118 {
00119   __IO uint32_t ISR;   /*!< BDMA interrupt status register */
00120   __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
00121 } BDMA_Base_Registers;
00122
00123 /* Private variables ---------------------------------------------------------*/
00124 /* Private constants ---------------------------------------------------------*/
00125 /** @addtogroup DMA_Private_Constants
00126  * @{
00127  */
00128 #define HAL_TIMEOUT_DMA_ABORT         (5U)  /* 5 ms */
00129
00130 #define BDMA_PERIPH_TO_MEMORY         (0x00000000U)                /*!< Peripheral to memory direction */
00131 #define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)     /*!< Memory to peripheral direction */
00132 #define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
00133
00134 /* DMA to BDMA conversion */
00135 #define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
00136                                                   ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
00137                                                   BDMA_PERIPH_TO_MEMORY)
00138
00139 #define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
00140 #define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
00141
00142 #define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
00143 #define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
00144
00145 #define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
00146
00147 #define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
00148
00149 /**
00150   * @}
00151   */
00152 /* Private macros ------------------------------------------------------------*/
00153 /* Private functions ---------------------------------------------------------*/
00154 /** @addtogroup DMA_Private_Functions
00155   * @{
00156   */
00157 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00158 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
00159 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
00160 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
00161 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported functions ---------------------------------------------------------*/
00168 /** @addtogroup DMA_Exported_Functions
00169   * @{
00170   */
00171
00172 /** @addtogroup DMA_Exported_Functions_Group1
00173   *
00174 @verbatim
00175  ===============================================================================
00176              ##### Initialization and de-initialization functions  #####
00177  ===============================================================================
00178     [..]
00179     This section provides functions allowing to initialize the DMA Stream source
00180     and destination incrementation and data sizes, transfer direction,
00181     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
00182     [..]
00183     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00184     reference manual.
00185     The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
00186
00187 @endverbatim
00188   * @{
00189   */
00190
00191 /**
00192   * @brief  Initialize the DMA according to the specified
00193   *         parameters in the DMA_InitTypeDef and create the associated handle.
00194   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00195   *               the configuration information for the specified DMA Stream.
00196   * @retval HAL status
00197   */
00198 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00199 {
00200   uint32_t registerValue;
00201   uint32_t tickstart = HAL_GetTick();
00202   DMA_Base_Registers *regs_dma;
00203   BDMA_Base_Registers *regs_bdma;
00204
00205   /* Check the DMA peripheral handle */
00206   if(hdma == NULL)
00207   {
00208     return HAL_ERROR;
00209   }
00210
00211   /* Check the parameters */
00212   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00213   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00214   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00215   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00216   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00217   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00218   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00219   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00220
00221   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00222   {
00223     assert_param(IS_DMA_REQUEST(hdma->Init.Request));
00224     assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
00225     /* Check the memory burst, peripheral burst and FIFO threshold parameters only
00226        when FIFO mode is enabled */
00227     if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
00228     {
00229       assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
00230       assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
00231       assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
00232     }
00233
00234     /* Allocate lock resource */
00235     __HAL_UNLOCK(hdma);
00236
00237     /* Change DMA peripheral state */
00238     hdma->State = HAL_DMA_STATE_BUSY;
00239
00240     /* Disable the peripheral */
00241     __HAL_DMA_DISABLE(hdma);
00242
00243     /* Check if the DMA Stream is effectively disabled */
00244     while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
00245     {
00246       /* Check for the Timeout */
00247       if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00248       {
00249         /* Update error code */
00250         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00251
00252         /* Change the DMA state */
00253         hdma->State = HAL_DMA_STATE_ERROR;
00254
00255         return HAL_ERROR;
00256       }
00257     }
00258
00259     /* Get the CR register value */
00260     registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
00261
00262     /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
00263     registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
00264                         DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
00265                         DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
00266                         DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
00267
00268     /* Prepare the DMA Stream configuration */
00269     registerValue |=  hdma->Init.Direction           |
00270             hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00271             hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00272             hdma->Init.Mode                | hdma->Init.Priority;
00273
00274     /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
00275     if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00276     {
00277       /* Get memory burst and peripheral burst */
00278       registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
00279     }
00280
00281     /* Write to DMA Stream CR register */
00282     ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
00283
00284     /* Get the FCR register value */
00285     registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
00286
00287     /* Clear Direct mode and FIFO threshold bits */
00288     registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
00289
00290     /* Prepare the DMA Stream FIFO configuration */
00291     registerValue |= hdma->Init.FIFOMode;
00292
00293     /* the FIFO threshold is not used when the FIFO mode is disabled */
00294     if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00295     {
00296       /* Get the FIFO threshold */
00297       registerValue |= hdma->Init.FIFOThreshold;
00298
00299       /* Check compatibility between FIFO threshold level and size of the memory burst */
00300       /* for INCR4, INCR8, INCR16 */
00301       if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
00302       {
00303         if (DMA_CheckFifoParam(hdma) != HAL_OK)
00304         {
00305           /* Update error code */
00306           hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00307
00308           /* Change the DMA state */
00309           hdma->State = HAL_DMA_STATE_READY;
00310
00311           return HAL_ERROR;
00312         }
00313       }
00314     }
00315
00316     /* Write to DMA Stream FCR */
00317     ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
00318
00319     /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
00320        DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00321     regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00322
00323     /* Clear all interrupt flags */
00324     regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
00325   }
00326   else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
00327   {
00328     if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
00329     {
00330       /* Check the request parameter */
00331       assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
00332     }
00333
00334     /* Allocate lock resource */
00335     __HAL_UNLOCK(hdma);
00336
00337     /* Change DMA peripheral state */
00338     hdma->State = HAL_DMA_STATE_BUSY;
00339
00340     /* Get the CR register value */
00341     registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
00342
00343     /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
00344     registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
00345                                   BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
00346                                   BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
00347                                   BDMA_CCR_CT));
00348
00349     /* Prepare the DMA Channel configuration */
00350     registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
00351                       DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
00352                       DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
00353                       DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
00354                       DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
00355                       DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
00356                       DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
00357
00358     /* Write to DMA Channel CR register */
00359     ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
00360
00361     /* calculation of the channel index */
00362     hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
00363
00364     /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
00365     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00366     regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00367
00368     /* Clear all interrupt flags */
00369     regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
00370   }
00371   else
00372   {
00373     hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00374     hdma->State     = HAL_DMA_STATE_ERROR;
00375
00376     return HAL_ERROR;
00377   }
00378
00379   if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00380   {
00381     /* Initialize parameters for DMAMUX channel :
00382     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
00383     */
00384     DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00385
00386     if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00387     {
00388       /* if memory to memory force the request to 0*/
00389       hdma->Init.Request = DMA_REQUEST_MEM2MEM;
00390     }
00391
00392     /* Set peripheral request  to DMAMUX channel */
00393     hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
00394
00395     /* Clear the DMAMUX synchro overrun flag */
00396     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00397
00398     /* Initialize parameters for DMAMUX request generator :
00399     if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
00400     */
00401     if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
00402     {
00403       /* Initialize parameters for DMAMUX request generator :
00404       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
00405       DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00406
00407       /* Reset the DMAMUX request generator register */
00408       hdma->DMAmuxRequestGen->RGCR = 0U;
00409
00410       /* Clear the DMAMUX request generator overrun flag */
00411       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00412     }
00413     else
00414     {
00415       hdma->DMAmuxRequestGen = 0U;
00416       hdma->DMAmuxRequestGenStatus = 0U;
00417       hdma->DMAmuxRequestGenStatusMask = 0U;
00418     }
00419   }
00420
00421   /* Initialize the error code */
00422   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00423
00424   /* Initialize the DMA state */
00425   hdma->State = HAL_DMA_STATE_READY;
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  DeInitializes the DMA peripheral
00432   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00433   *               the configuration information for the specified DMA Stream.
00434   * @retval HAL status
00435   */
00436 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00437 {
00438   DMA_Base_Registers *regs_dma;
00439   BDMA_Base_Registers *regs_bdma;
00440
00441   /* Check the DMA peripheral handle */
00442   if(hdma == NULL)
00443   {
00444     return HAL_ERROR;
00445   }
00446
00447   /* Disable the selected DMA Streamx */
00448   __HAL_DMA_DISABLE(hdma);
00449
00450   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00451   {
00452     /* Reset DMA Streamx control register */
00453     ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
00454
00455     /* Reset DMA Streamx number of data to transfer register */
00456     ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
00457
00458     /* Reset DMA Streamx peripheral address register */
00459     ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
00460
00461     /* Reset DMA Streamx memory 0 address register */
00462     ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
00463
00464     /* Reset DMA Streamx memory 1 address register */
00465     ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
00466
00467     /* Reset DMA Streamx FIFO control register */
00468     ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
00469
00470     /* Get DMA steam Base Address */
00471     regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00472
00473     /* Clear all interrupt flags at correct offset within the register */
00474     regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
00475   }
00476   else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
00477   {
00478     /* Reset DMA Channel control register */
00479     ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
00480
00481     /* Reset DMA Channel Number of Data to Transfer register */
00482     ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
00483
00484     /* Reset DMA Channel peripheral address register */
00485     ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
00486
00487     /* Reset DMA Channel memory 0 address register */
00488     ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;
00489
00490     /* Reset DMA Channel memory 1 address register */
00491     ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;
00492
00493     /* Get DMA steam Base Address */
00494     regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00495
00496     /* Clear all interrupt flags at correct offset within the register */
00497     regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
00498   }
00499   else
00500   {
00501     /* Return error status */
00502     return HAL_ERROR;
00503   }
00504
00505   if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00506   {
00507     /* Initialize parameters for DMAMUX channel :
00508     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
00509     DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00510
00511     if(hdma->DMAmuxChannel != 0U)
00512     {
00513       /* Resett he DMAMUX channel that corresponds to the DMA stream */
00514       hdma->DMAmuxChannel->CCR = 0U;
00515
00516       /* Clear the DMAMUX synchro overrun flag */
00517       hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00518     }
00519
00520     if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
00521     {
00522       /* Initialize parameters for DMAMUX request generator :
00523       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
00524       DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00525
00526       /* Reset the DMAMUX request generator register */
00527       hdma->DMAmuxRequestGen->RGCR = 0U;
00528
00529       /* Clear the DMAMUX request generator overrun flag */
00530       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00531     }
00532
00533     hdma->DMAmuxRequestGen = 0U;
00534     hdma->DMAmuxRequestGenStatus = 0U;
00535     hdma->DMAmuxRequestGenStatusMask = 0U;
00536   }
00537
00538
00539   /* Clean callbacks */
00540   hdma->XferCpltCallback       = NULL;
00541   hdma->XferHalfCpltCallback   = NULL;
00542   hdma->XferM1CpltCallback     = NULL;
00543   hdma->XferM1HalfCpltCallback = NULL;
00544   hdma->XferErrorCallback      = NULL;
00545   hdma->XferAbortCallback      = NULL;
00546
00547   /* Initialize the error code */
00548   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00549
00550   /* Initialize the DMA state */
00551   hdma->State = HAL_DMA_STATE_RESET;
00552
00553   /* Release Lock */
00554   __HAL_UNLOCK(hdma);
00555
00556   return HAL_OK;
00557 }
00558
00559 /**
00560   * @}
00561   */
00562
00563 /** @addtogroup DMA_Exported_Functions_Group2
00564   *
00565 @verbatim
00566  ===============================================================================
00567                       #####  IO operation functions  #####
00568  ===============================================================================
00569     [..]  This section provides functions allowing to:
00570       (+) Configure the source, destination address and data length and Start DMA transfer
00571       (+) Configure the source, destination address and data length and
00572           Start DMA transfer with interrupt
00573       (+) Register and Unregister DMA callbacks
00574       (+) Abort DMA transfer
00575       (+) Poll for transfer complete
00576       (+) Handle DMA interrupt request
00577
00578 @endverbatim
00579   * @{
00580   */
00581
00582 /**
00583   * @brief  Starts the DMA Transfer.
00584   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00585   *                     the configuration information for the specified DMA Stream.
00586   * @param  SrcAddress: The source memory Buffer address
00587   * @param  DstAddress: The destination memory Buffer address
00588   * @param  DataLength: The length of data to be transferred from source to destination
00589   * @retval HAL status
00590   */
00591 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00592 {
00593   HAL_StatusTypeDef status = HAL_OK;
00594
00595   /* Check the parameters */
00596   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00597
00598   /* Check the DMA peripheral handle */
00599   if(hdma == NULL)
00600   {
00601     return HAL_ERROR;
00602   }
00603
00604   /* Process locked */
00605   __HAL_LOCK(hdma);
00606
00607   if(HAL_DMA_STATE_READY == hdma->State)
00608   {
00609     /* Change DMA peripheral state */
00610     hdma->State = HAL_DMA_STATE_BUSY;
00611
00612     /* Initialize the error code */
00613     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00614
00615     /* Disable the peripheral */
00616     __HAL_DMA_DISABLE(hdma);
00617
00618     /* Configure the source, destination address and the data length */
00619     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00620
00621     /* Enable the Peripheral */
00622     __HAL_DMA_ENABLE(hdma);
00623   }
00624   else
00625   {
00626     /* Process unlocked */
00627     __HAL_UNLOCK(hdma);
00628
00629     /* Set the error code to busy */
00630     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00631
00632     /* Return error status */
00633     status = HAL_ERROR;
00634   }
00635   return status;
00636 }
00637
00638 /**
00639   * @brief  Start the DMA Transfer with interrupt enabled.
00640   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00641   *                     the configuration information for the specified DMA Stream.
00642   * @param  SrcAddress: The source memory Buffer address
00643   * @param  DstAddress: The destination memory Buffer address
00644   * @param  DataLength: The length of data to be transferred from source to destination
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00648 {
00649   HAL_StatusTypeDef status = HAL_OK;
00650
00651   /* Check the parameters */
00652   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00653
00654   /* Check the DMA peripheral handle */
00655   if(hdma == NULL)
00656   {
00657     return HAL_ERROR;
00658   }
00659
00660   /* Process locked */
00661   __HAL_LOCK(hdma);
00662
00663   if(HAL_DMA_STATE_READY == hdma->State)
00664   {
00665     /* Change DMA peripheral state */
00666     hdma->State = HAL_DMA_STATE_BUSY;
00667
00668     /* Initialize the error code */
00669     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00670
00671     /* Disable the peripheral */
00672     __HAL_DMA_DISABLE(hdma);
00673
00674     /* Configure the source, destination address and the data length */
00675     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00676
00677     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00678     {
00679       /* Enable Common interrupts*/
00680       MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
00681
00682       if(hdma->XferHalfCpltCallback != NULL)
00683       {
00684         /* Enable Half Transfer IT if corresponding Callback is set */
00685         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
00686       }
00687     }
00688     else /* BDMA channel */
00689     {
00690       /* Enable Common interrupts */
00691       MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
00692
00693       if(hdma->XferHalfCpltCallback != NULL)
00694       {
00695         /*Enable Half Transfer IT if corresponding Callback is set */
00696         ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
00697       }
00698     }
00699
00700     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00701     {
00702       /* Check if DMAMUX Synchronization is enabled */
00703       if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00704       {
00705         /* Enable DMAMUX sync overrun IT*/
00706         hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00707       }
00708
00709       if(hdma->DMAmuxRequestGen != 0U)
00710       {
00711         /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00712         /* enable the request gen overrun IT */
00713         hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00714       }
00715     }
00716
00717     /* Enable the Peripheral */
00718     __HAL_DMA_ENABLE(hdma);
00719   }
00720   else
00721   {
00722     /* Process unlocked */
00723     __HAL_UNLOCK(hdma);
00724
00725     /* Set the error code to busy */
00726     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00727
00728     /* Return error status */
00729     status = HAL_ERROR;
00730   }
00731
00732   return status;
00733 }
00734
00735 /**
00736   * @brief  Aborts the DMA Transfer.
00737   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00738   *                 the configuration information for the specified DMA Stream.
00739   *
00740   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
00741   *        effectively disabled is added. If a Stream is disabled
00742   *        while a data transfer is ongoing, the current data will be transferred
00743   *        and the Stream will be effectively disabled only after the transfer of
00744   *        this single data is finished.
00745   * @retval HAL status
00746   */
00747 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00748 {
00749   /* calculate DMA base and stream number */
00750   DMA_Base_Registers *regs_dma;
00751   BDMA_Base_Registers *regs_bdma;
00752   const __IO uint32_t *enableRegister;
00753
00754   uint32_t tickstart = HAL_GetTick();
00755
00756  /* Check the DMA peripheral handle */
00757   if(hdma == NULL)
00758   {
00759     return HAL_ERROR;
00760   }
00761
00762   /* Check the DMA peripheral state */
00763   if(hdma->State != HAL_DMA_STATE_BUSY)
00764   {
00765     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00766
00767     /* Process Unlocked */
00768     __HAL_UNLOCK(hdma);
00769
00770     return HAL_ERROR;
00771   }
00772   else
00773   {
00774     /* Disable all the transfer interrupts */
00775     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00776     {
00777        /* Disable DMA All Interrupts  */
00778       ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
00779       ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
00780
00781       enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
00782     }
00783     else /* BDMA channel */
00784     {
00785       /* Disable DMA All Interrupts */
00786       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
00787
00788       enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
00789     }
00790
00791     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00792     {
00793       /* disable the DMAMUX sync overrun IT */
00794       hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00795     }
00796
00797     /* Disable the stream */
00798     __HAL_DMA_DISABLE(hdma);
00799
00800     /* Check if the DMA Stream is effectively disabled */
00801     while(((*enableRegister) & DMA_SxCR_EN) != 0U)
00802     {
00803       /* Check for the Timeout */
00804       if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00805       {
00806         /* Update error code */
00807         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00808
00809         /* Process Unlocked */
00810         __HAL_UNLOCK(hdma);
00811
00812         /* Change the DMA state */
00813         hdma->State = HAL_DMA_STATE_ERROR;
00814
00815         return HAL_ERROR;
00816       }
00817     }
00818
00819     /* Clear all interrupt flags at correct offset within the register */
00820     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00821     {
00822       regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00823       regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
00824     }
00825     else /* BDMA channel */
00826     {
00827       regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
00828       regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
00829     }
00830
00831     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00832     {
00833       /* Clear the DMAMUX synchro overrun flag */
00834       hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00835
00836       if(hdma->DMAmuxRequestGen != 0U)
00837       {
00838         /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
00839         /* disable the request gen overrun IT */
00840         hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00841
00842         /* Clear the DMAMUX request generator overrun flag */
00843         hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00844       }
00845     }
00846
00847     /* Process Unlocked */
00848     __HAL_UNLOCK(hdma);
00849
00850     /* Change the DMA state */
00851     hdma->State = HAL_DMA_STATE_READY;
00852   }
00853
00854   return HAL_OK;
00855 }
00856
00857 /**
00858   * @brief  Aborts the DMA Transfer in Interrupt mode.
00859   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00860   *                 the configuration information for the specified DMA Stream.
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00864 {
00865   BDMA_Base_Registers *regs_bdma;
00866
00867   /* Check the DMA peripheral handle */
00868   if(hdma == NULL)
00869   {
00870     return HAL_ERROR;
00871   }
00872
00873   if(hdma->State != HAL_DMA_STATE_BUSY)
00874   {
00875     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00876     return HAL_ERROR;
00877   }
00878   else
00879   {
00880     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00881     {
00882       /* Set Abort State  */
00883       hdma->State = HAL_DMA_STATE_ABORT;
00884
00885       /* Disable the stream */
00886       __HAL_DMA_DISABLE(hdma);
00887     }
00888     else /* BDMA channel */
00889     {
00890       /* Disable DMA All Interrupts  */
00891       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
00892
00893       /* Disable the channel */
00894       __HAL_DMA_DISABLE(hdma);
00895
00896       if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00897       {
00898         /* disable the DMAMUX sync overrun IT */
00899         hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00900
00901         /* Clear all flags */
00902         regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
00903         regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
00904
00905         /* Clear the DMAMUX synchro overrun flag */
00906         hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00907
00908         if(hdma->DMAmuxRequestGen != 0U)
00909         {
00910           /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00911           /* disable the request gen overrun IT */
00912           hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00913
00914           /* Clear the DMAMUX request generator overrun flag */
00915           hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00916         }
00917       }
00918
00919       /* Process Unlocked */
00920       __HAL_UNLOCK(hdma);
00921
00922       /* Change the DMA state */
00923       hdma->State = HAL_DMA_STATE_READY;
00924
00925       /* Call User Abort callback */
00926       if(hdma->XferAbortCallback != NULL)
00927       {
00928         hdma->XferAbortCallback(hdma);
00929       }
00930     }
00931   }
00932
00933   return HAL_OK;
00934 }
00935
00936 /**
00937   * @brief  Polling for transfer complete.
00938   * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
00939   *                        the configuration information for the specified DMA Stream.
00940   * @param  CompleteLevel: Specifies the DMA level complete.
00941   * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
00942   *         This model could be used for debug purpose.
00943   * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
00944   * @param  Timeout:       Timeout duration.
00945   * @retval HAL status
00946   */
00947 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
00948 {
00949   HAL_StatusTypeDef status = HAL_OK;
00950   uint32_t cpltlevel_mask;
00951   uint32_t tickstart = HAL_GetTick();
00952
00953   /* IT status register */
00954   __IO uint32_t *isr_reg;
00955   /* IT clear flag register */
00956   __IO uint32_t *ifcr_reg;
00957
00958   /* Check the DMA peripheral handle */
00959   if(hdma == NULL)
00960   {
00961     return HAL_ERROR;
00962   }
00963
00964   if(HAL_DMA_STATE_BUSY != hdma->State)
00965   {
00966     /* No transfer ongoing */
00967     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00968     __HAL_UNLOCK(hdma);
00969
00970     return HAL_ERROR;
00971   }
00972
00973   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00974   {
00975     /* Polling mode not supported in circular mode and double buffering mode */
00976     if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
00977     {
00978       hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00979       return HAL_ERROR;
00980     }
00981
00982     /* Get the level transfer complete flag */
00983     if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00984     {
00985       /* Transfer Complete flag */
00986       cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
00987     }
00988     else
00989     {
00990       /* Half Transfer Complete flag */
00991       cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
00992     }
00993
00994     isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
00995     ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
00996   }
00997   else /* BDMA channel */
00998   {
00999     /* Polling mode not supported in circular mode */
01000     if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)
01001     {
01002       hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
01003       return HAL_ERROR;
01004     }
01005
01006     /* Get the level transfer complete flag */
01007     if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
01008     {
01009       /* Transfer Complete flag */
01010       cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);
01011     }
01012     else
01013     {
01014       /* Half Transfer Complete flag */
01015       cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);
01016     }
01017
01018     isr_reg  = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
01019     ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
01020   }
01021
01022   while(((*isr_reg) & cpltlevel_mask) == 0U)
01023   {
01024     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
01025     {
01026       if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01027       {
01028         /* Update error code */
01029         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
01030
01031         /* Clear the FIFO error flag */
01032         (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
01033       }
01034
01035       if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01036       {
01037         /* Update error code */
01038         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
01039
01040         /* Clear the Direct Mode error flag */
01041         (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
01042       }
01043
01044       if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01045       {
01046         /* Update error code */
01047         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
01048
01049         /* Clear the transfer error flag */
01050         (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
01051
01052         /* Change the DMA state */
01053         hdma->State = HAL_DMA_STATE_READY;
01054
01055         /* Process Unlocked */
01056         __HAL_UNLOCK(hdma);
01057
01058         return HAL_ERROR;
01059       }
01060     }
01061     else /* BDMA channel */
01062     {
01063       if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)
01064       {
01065         /* When a DMA transfer error occurs */
01066         /* A hardware clear of its EN bits is performed */
01067         /* Clear all flags */
01068         (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));
01069
01070         /* Update error code */
01071         hdma->ErrorCode = HAL_DMA_ERROR_TE;
01072
01073         /* Change the DMA state */
01074         hdma->State = HAL_DMA_STATE_READY;
01075
01076         /* Process Unlocked */
01077         __HAL_UNLOCK(hdma);
01078
01079         return HAL_ERROR;
01080       }
01081     }
01082
01083     /* Check for the Timeout (Not applicable in circular mode)*/
01084     if(Timeout != HAL_MAX_DELAY)
01085     {
01086       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01087       {
01088         /* Update error code */
01089         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
01090
01091         /* if timeout then abort the current transfer */
01092         /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code  */
01093         (void) HAL_DMA_Abort(hdma);
01094           /*
01095             Note that the Abort function will
01096               - Clear the transfer error flags
01097               - Unlock
01098               - Set the State
01099           */
01100
01101         return HAL_ERROR;
01102       }
01103     }
01104
01105     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
01106     {
01107       /* Check for DMAMUX Request generator (if used) overrun status */
01108       if(hdma->DMAmuxRequestGen != 0U)
01109       {
01110         /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
01111         if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
01112         {
01113           /* Clear the DMAMUX request generator overrun flag */
01114           hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
01115
01116           /* Update error code */
01117           hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
01118         }
01119       }
01120
01121       /* Check for DMAMUX Synchronization overrun */
01122       if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
01123       {
01124         /* Clear the DMAMUX synchro overrun flag */
01125         hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
01126
01127         /* Update error code */
01128         hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
01129       }
01130     }
01131   }
01132
01133
01134   /* Get the level transfer complete flag */
01135   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
01136   {
01137     /* Clear the half transfer and transfer complete flags */
01138     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
01139     {
01140       (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);
01141     }
01142     else /* BDMA channel */
01143     {
01144       (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
01145     }
01146
01147     /* Process Unlocked */
01148     __HAL_UNLOCK(hdma);
01149
01150     hdma->State = HAL_DMA_STATE_READY;
01151   }
01152   else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
01153   {
01154     /* Clear the half transfer and transfer complete flags */
01155     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
01156     {
01157       (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);
01158     }
01159     else /* BDMA channel */
01160     {
01161       (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));
01162     }
01163   }
01164
01165   return status;
01166 }
01167
01168 /**
01169   * @brief  Handles DMA interrupt request.
01170   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01171   *               the configuration information for the specified DMA Stream.
01172   * @retval None
01173   */
01174 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
01175 {
01176   uint32_t tmpisr_dma, tmpisr_bdma;
01177   uint32_t ccr_reg;
01178   __IO uint32_t count = 0U;
01179   uint32_t timeout = SystemCoreClock / 9600U;
01180
01181   /* calculate DMA base and stream number */
01182   DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
01183   BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
01184
01185   tmpisr_dma  = regs_dma->ISR;
01186   tmpisr_bdma = regs_bdma->ISR;
01187
01188   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
01189   {
01190     /* Transfer Error Interrupt management ***************************************/
01191     if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01192     {
01193       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
01194       {
01195         /* Disable the transfer error interrupt */
01196         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
01197
01198         /* Clear the transfer error flag */
01199         regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
01200
01201         /* Update error code */
01202         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
01203       }
01204     }
01205     /* FIFO Error Interrupt management ******************************************/
01206     if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01207     {
01208       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
01209       {
01210         /* Clear the FIFO error flag */
01211         regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
01212
01213         /* Update error code */
01214         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
01215       }
01216     }
01217     /* Direct Mode Error Interrupt management ***********************************/
01218     if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01219     {
01220       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
01221       {
01222         /* Clear the direct mode error flag */
01223         regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
01224
01225         /* Update error code */
01226         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
01227       }
01228     }
01229     /* Half Transfer Complete Interrupt management ******************************/
01230     if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01231     {
01232       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
01233       {
01234         /* Clear the half transfer complete flag */
01235         regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
01236
01237         /* Multi_Buffering mode enabled */
01238         if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
01239         {
01240           /* Current memory buffer used is Memory 0 */
01241           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
01242           {
01243             if(hdma->XferHalfCpltCallback != NULL)
01244             {
01245               /* Half transfer callback */
01246               hdma->XferHalfCpltCallback(hdma);
01247             }
01248           }
01249           /* Current memory buffer used is Memory 1 */
01250           else
01251           {
01252             if(hdma->XferM1HalfCpltCallback != NULL)
01253             {
01254               /* Half transfer callback */
01255               hdma->XferM1HalfCpltCallback(hdma);
01256             }
01257           }
01258         }
01259         else
01260         {
01261           /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
01262           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
01263           {
01264             /* Disable the half transfer interrupt */
01265             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
01266           }
01267
01268           if(hdma->XferHalfCpltCallback != NULL)
01269           {
01270             /* Half transfer callback */
01271             hdma->XferHalfCpltCallback(hdma);
01272           }
01273         }
01274       }
01275     }
01276     /* Transfer Complete Interrupt management ***********************************/
01277     if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
01278     {
01279       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
01280       {
01281         /* Clear the transfer complete flag */
01282         regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
01283
01284         if(HAL_DMA_STATE_ABORT == hdma->State)
01285         {
01286           /* Disable all the transfer interrupts */
01287           ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
01288           ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
01289
01290           if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
01291           {
01292             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
01293           }
01294
01295           /* Clear all interrupt flags at correct offset within the register */
01296           regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
01297
01298           /* Process Unlocked */
01299           __HAL_UNLOCK(hdma);
01300
01301           /* Change the DMA state */
01302           hdma->State = HAL_DMA_STATE_READY;
01303
01304           if(hdma->XferAbortCallback != NULL)
01305           {
01306             hdma->XferAbortCallback(hdma);
01307           }
01308           return;
01309         }
01310
01311         if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
01312         {
01313           /* Current memory buffer used is Memory 0 */
01314           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
01315           {
01316             if(hdma->XferM1CpltCallback != NULL)
01317             {
01318               /* Transfer complete Callback for memory1 */
01319               hdma->XferM1CpltCallback(hdma);
01320             }
01321           }
01322           /* Current memory buffer used is Memory 1 */
01323           else
01324           {
01325             if(hdma->XferCpltCallback != NULL)
01326             {
01327               /* Transfer complete Callback for memory0 */
01328               hdma->XferCpltCallback(hdma);
01329             }
01330           }
01331         }
01332         /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
01333         else
01334         {
01335           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
01336           {
01337             /* Disable the transfer complete interrupt */
01338             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
01339
01340             /* Process Unlocked */
01341             __HAL_UNLOCK(hdma);
01342
01343             /* Change the DMA state */
01344             hdma->State = HAL_DMA_STATE_READY;
01345           }
01346
01347           if(hdma->XferCpltCallback != NULL)
01348           {
01349             /* Transfer complete callback */
01350             hdma->XferCpltCallback(hdma);
01351           }
01352         }
01353       }
01354     }
01355
01356     /* manage error case */
01357     if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
01358     {
01359       if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
01360       {
01361         hdma->State = HAL_DMA_STATE_ABORT;
01362
01363         /* Disable the stream */
01364         __HAL_DMA_DISABLE(hdma);
01365
01366         do
01367         {
01368           if (++count > timeout)
01369           {
01370             break;
01371           }
01372         }
01373         while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
01374
01375         /* Process Unlocked */
01376         __HAL_UNLOCK(hdma);
01377
01378         if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
01379         {
01380           /* Change the DMA state to error if DMA disable fails */
01381           hdma->State = HAL_DMA_STATE_ERROR;
01382         }
01383         else
01384         {
01385           /* Change the DMA state to Ready if DMA disable success */
01386           hdma->State = HAL_DMA_STATE_READY;
01387         }
01388       }
01389
01390       if(hdma->XferErrorCallback != NULL)
01391       {
01392         /* Transfer error callback */
01393         hdma->XferErrorCallback(hdma);
01394       }
01395     }
01396   }
01397   else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
01398   {
01399     ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
01400
01401     /* Half Transfer Complete Interrupt management ******************************/
01402     if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
01403     {
01404       /* Clear the half transfer complete flag */
01405       regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
01406
01407       /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
01408       if((ccr_reg & BDMA_CCR_DBM) != 0U)
01409       {
01410         /* Current memory buffer used is Memory 0 */
01411         if((ccr_reg & BDMA_CCR_CT) == 0U)
01412         {
01413           if(hdma->XferM1HalfCpltCallback != NULL)
01414           {
01415             /* Half transfer Callback for Memory 1 */
01416             hdma->XferM1HalfCpltCallback(hdma);
01417           }
01418         }
01419         /* Current memory buffer used is Memory 1 */
01420         else
01421         {
01422           if(hdma->XferHalfCpltCallback != NULL)
01423           {
01424             /* Half transfer Callback for Memory 0 */
01425             hdma->XferHalfCpltCallback(hdma);
01426           }
01427         }
01428       }
01429       else
01430       {
01431         if((ccr_reg & BDMA_CCR_CIRC) == 0U)
01432         {
01433           /* Disable the half transfer interrupt */
01434           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
01435         }
01436
01437         /* DMA peripheral state is not updated in Half Transfer */
01438         /* but in Transfer Complete case */
01439
01440        if(hdma->XferHalfCpltCallback != NULL)
01441         {
01442           /* Half transfer callback */
01443           hdma->XferHalfCpltCallback(hdma);
01444         }
01445       }
01446     }
01447
01448     /* Transfer Complete Interrupt management ***********************************/
01449     else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
01450     {
01451       /* Clear the transfer complete flag */
01452       regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
01453
01454       /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
01455       if((ccr_reg & BDMA_CCR_DBM) != 0U)
01456       {
01457         /* Current memory buffer used is Memory 0 */
01458         if((ccr_reg & BDMA_CCR_CT) == 0U)
01459         {
01460           if(hdma->XferM1CpltCallback != NULL)
01461           {
01462             /* Transfer complete Callback for Memory 1 */
01463             hdma->XferM1CpltCallback(hdma);
01464           }
01465         }
01466         /* Current memory buffer used is Memory 1 */
01467         else
01468         {
01469           if(hdma->XferCpltCallback != NULL)
01470           {
01471             /* Transfer complete Callback for Memory 0 */
01472             hdma->XferCpltCallback(hdma);
01473           }
01474         }
01475       }
01476       else
01477       {
01478         if((ccr_reg & BDMA_CCR_CIRC) == 0U)
01479         {
01480           /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
01481           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
01482
01483           /* Process Unlocked */
01484           __HAL_UNLOCK(hdma);
01485
01486           /* Change the DMA state */
01487           hdma->State = HAL_DMA_STATE_READY;
01488         }
01489
01490         if(hdma->XferCpltCallback != NULL)
01491         {
01492           /* Transfer complete callback */
01493           hdma->XferCpltCallback(hdma);
01494         }
01495       }
01496     }
01497     /* Transfer Error Interrupt management **************************************/
01498     else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
01499     {
01500       /* When a DMA transfer error occurs */
01501       /* A hardware clear of its EN bits is performed */
01502       /* Disable ALL DMA IT */
01503       __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
01504
01505       /* Clear all flags */
01506       regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
01507
01508       /* Update error code */
01509       hdma->ErrorCode = HAL_DMA_ERROR_TE;
01510
01511       /* Process Unlocked */
01512       __HAL_UNLOCK(hdma);
01513
01514       /* Change the DMA state */
01515       hdma->State = HAL_DMA_STATE_READY;
01516
01517       if (hdma->XferErrorCallback != NULL)
01518       {
01519         /* Transfer error callback */
01520         hdma->XferErrorCallback(hdma);
01521       }
01522     }
01523     else
01524     {
01525       /* Nothing To Do */
01526     }
01527   }
01528   else
01529   {
01530     /* Nothing To Do */
01531   }
01532 }
01533
01534 /**
01535   * @brief  Register callbacks
01536   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
01537   *                               the configuration information for the specified DMA Stream.
01538   * @param  CallbackID:           User Callback identifier
01539   *                               a DMA_HandleTypeDef structure as parameter.
01540   * @param  pCallback:            pointer to private callback function which has pointer to
01541   *                               a DMA_HandleTypeDef structure as parameter.
01542   * @retval HAL status
01543   */
01544 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
01545 {
01546
01547   HAL_StatusTypeDef status = HAL_OK;
01548
01549   /* Check the DMA peripheral handle */
01550   if(hdma == NULL)
01551   {
01552     return HAL_ERROR;
01553   }
01554
01555   /* Process locked */
01556   __HAL_LOCK(hdma);
01557
01558   if(HAL_DMA_STATE_READY == hdma->State)
01559   {
01560     switch (CallbackID)
01561     {
01562     case  HAL_DMA_XFER_CPLT_CB_ID:
01563       hdma->XferCpltCallback = pCallback;
01564       break;
01565
01566     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
01567       hdma->XferHalfCpltCallback = pCallback;
01568       break;
01569
01570     case  HAL_DMA_XFER_M1CPLT_CB_ID:
01571       hdma->XferM1CpltCallback = pCallback;
01572       break;
01573
01574     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
01575       hdma->XferM1HalfCpltCallback = pCallback;
01576       break;
01577
01578     case  HAL_DMA_XFER_ERROR_CB_ID:
01579       hdma->XferErrorCallback = pCallback;
01580       break;
01581
01582     case  HAL_DMA_XFER_ABORT_CB_ID:
01583       hdma->XferAbortCallback = pCallback;
01584       break;
01585
01586     default:
01587       break;
01588     }
01589   }
01590   else
01591   {
01592     /* Return error status */
01593     status =  HAL_ERROR;
01594   }
01595
01596   /* Release Lock */
01597   __HAL_UNLOCK(hdma);
01598
01599   return status;
01600 }
01601
01602 /**
01603   * @brief  UnRegister callbacks
01604   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
01605   *                               the configuration information for the specified DMA Stream.
01606   * @param  CallbackID:           User Callback identifier
01607   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
01608   * @retval HAL status
01609   */
01610 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
01611 {
01612   HAL_StatusTypeDef status = HAL_OK;
01613
01614   /* Check the DMA peripheral handle */
01615   if(hdma == NULL)
01616   {
01617     return HAL_ERROR;
01618   }
01619
01620   /* Process locked */
01621   __HAL_LOCK(hdma);
01622
01623   if(HAL_DMA_STATE_READY == hdma->State)
01624   {
01625     switch (CallbackID)
01626     {
01627     case  HAL_DMA_XFER_CPLT_CB_ID:
01628       hdma->XferCpltCallback = NULL;
01629       break;
01630
01631     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
01632       hdma->XferHalfCpltCallback = NULL;
01633       break;
01634
01635     case  HAL_DMA_XFER_M1CPLT_CB_ID:
01636       hdma->XferM1CpltCallback = NULL;
01637       break;
01638
01639     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
01640       hdma->XferM1HalfCpltCallback = NULL;
01641       break;
01642
01643     case  HAL_DMA_XFER_ERROR_CB_ID:
01644       hdma->XferErrorCallback = NULL;
01645       break;
01646
01647     case  HAL_DMA_XFER_ABORT_CB_ID:
01648       hdma->XferAbortCallback = NULL;
01649       break;
01650
01651     case   HAL_DMA_XFER_ALL_CB_ID:
01652       hdma->XferCpltCallback = NULL;
01653       hdma->XferHalfCpltCallback = NULL;
01654       hdma->XferM1CpltCallback = NULL;
01655       hdma->XferM1HalfCpltCallback = NULL;
01656       hdma->XferErrorCallback = NULL;
01657       hdma->XferAbortCallback = NULL;
01658       break;
01659
01660     default:
01661       status = HAL_ERROR;
01662       break;
01663     }
01664   }
01665   else
01666   {
01667     status = HAL_ERROR;
01668   }
01669
01670   /* Release Lock */
01671   __HAL_UNLOCK(hdma);
01672
01673   return status;
01674 }
01675
01676 /**
01677   * @}
01678   */
01679
01680 /** @addtogroup DMA_Exported_Functions_Group3
01681   *
01682 @verbatim
01683  ===============================================================================
01684                     ##### State and Errors functions #####
01685  ===============================================================================
01686     [..]
01687     This subsection provides functions allowing to
01688       (+) Check the DMA state
01689       (+) Get error code
01690
01691 @endverbatim
01692   * @{
01693   */
01694
01695 /**
01696   * @brief  Returns the DMA state.
01697   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01698   *               the configuration information for the specified DMA Stream.
01699   * @retval HAL state
01700   */
01701 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
01702 {
01703   return hdma->State;
01704 }
01705
01706 /**
01707   * @brief  Return the DMA error code
01708   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
01709   *              the configuration information for the specified DMA Stream.
01710   * @retval DMA Error Code
01711   */
01712 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
01713 {
01714   return hdma->ErrorCode;
01715 }
01716
01717 /**
01718   * @}
01719   */
01720
01721 /**
01722   * @}
01723   */
01724
01725 /** @addtogroup DMA_Private_Functions
01726   * @{
01727   */
01728
01729 /**
01730   * @brief  Sets the DMA Transfer parameter.
01731   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01732   *                     the configuration information for the specified DMA Stream.
01733   * @param  SrcAddress: The source memory Buffer address
01734   * @param  DstAddress: The destination memory Buffer address
01735   * @param  DataLength: The length of data to be transferred from source to destination
01736   * @retval None
01737   */
01738 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
01739 {
01740   /* calculate DMA base and stream number */
01741   DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
01742   BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
01743
01744   if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
01745   {
01746     /* Clear the DMAMUX synchro overrun flag */
01747     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
01748
01749     if(hdma->DMAmuxRequestGen != 0U)
01750     {
01751       /* Clear the DMAMUX request generator overrun flag */
01752       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
01753     }
01754   }
01755
01756   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
01757   {
01758     /* Clear all interrupt flags at correct offset within the register */
01759     regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
01760
01761     /* Clear DBM bit */
01762     ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
01763
01764     /* Configure DMA Stream data length */
01765     ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
01766
01767     /* Peripheral to Memory */
01768     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01769     {
01770       /* Configure DMA Stream destination address */
01771       ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
01772
01773       /* Configure DMA Stream source address */
01774       ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
01775     }
01776     /* Memory to Peripheral */
01777     else
01778     {
01779       /* Configure DMA Stream source address */
01780       ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
01781
01782       /* Configure DMA Stream destination address */
01783       ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
01784     }
01785   }
01786   else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
01787   {
01788     /* Clear all flags */
01789     regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
01790
01791     /* Configure DMA Channel data length */
01792     ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
01793
01794     /* Peripheral to Memory */
01795     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01796     {
01797       /* Configure DMA Channel destination address */
01798       ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
01799
01800       /* Configure DMA Channel source address */
01801       ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
01802     }
01803     /* Memory to Peripheral */
01804     else
01805     {
01806       /* Configure DMA Channel source address */
01807       ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
01808
01809       /* Configure DMA Channel destination address */
01810       ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
01811     }
01812   }
01813   else
01814   {
01815     /* Nothing To Do */
01816   }
01817 }
01818
01819 /**
01820   * @brief  Returns the DMA Stream base address depending on stream number
01821   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01822   *                     the configuration information for the specified DMA Stream.
01823   * @retval Stream base address
01824   */
01825 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
01826 {
01827   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
01828   {
01829     uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
01830
01831     /* lookup table for necessary bitshift of flags within status registers */
01832     static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
01833     hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
01834
01835     if (stream_number > 3U)
01836     {
01837       /* return pointer to HISR and HIFCR */
01838       hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
01839     }
01840     else
01841     {
01842       /* return pointer to LISR and LIFCR */
01843       hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
01844     }
01845   }
01846   else /* BDMA instance(s) */
01847   {
01848     /* return pointer to ISR and IFCR */
01849     hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
01850   }
01851
01852   return hdma->StreamBaseAddress;
01853 }
01854
01855 /**
01856   * @brief  Check compatibility between FIFO threshold level and size of the memory burst
01857   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01858   *                     the configuration information for the specified DMA Stream.
01859   * @retval HAL status
01860   */
01861 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
01862 {
01863   HAL_StatusTypeDef status = HAL_OK;
01864
01865   /* Memory Data size equal to Byte */
01866   if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
01867   {
01868     switch (hdma->Init.FIFOThreshold)
01869     {
01870       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01871       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01872
01873         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01874         {
01875           status = HAL_ERROR;
01876         }
01877         break;
01878
01879       case DMA_FIFO_THRESHOLD_HALFFULL:
01880         if (hdma->Init.MemBurst == DMA_MBURST_INC16)
01881         {
01882           status = HAL_ERROR;
01883         }
01884         break;
01885
01886       case DMA_FIFO_THRESHOLD_FULL:
01887         break;
01888
01889       default:
01890         break;
01891     }
01892   }
01893
01894   /* Memory Data size equal to Half-Word */
01895   else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01896   {
01897     switch (hdma->Init.FIFOThreshold)
01898     {
01899       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01900       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01901         status = HAL_ERROR;
01902         break;
01903
01904       case DMA_FIFO_THRESHOLD_HALFFULL:
01905         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01906         {
01907           status = HAL_ERROR;
01908         }
01909         break;
01910
01911       case DMA_FIFO_THRESHOLD_FULL:
01912         if (hdma->Init.MemBurst == DMA_MBURST_INC16)
01913         {
01914           status = HAL_ERROR;
01915         }
01916         break;
01917
01918       default:
01919         break;
01920     }
01921   }
01922
01923   /* Memory Data size equal to Word */
01924   else
01925   {
01926     switch (hdma->Init.FIFOThreshold)
01927     {
01928       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01929       case DMA_FIFO_THRESHOLD_HALFFULL:
01930       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01931         status = HAL_ERROR;
01932         break;
01933
01934       case DMA_FIFO_THRESHOLD_FULL:
01935         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01936         {
01937           status = HAL_ERROR;
01938         }
01939     break;
01940
01941       default:
01942         break;
01943     }
01944   }
01945
01946   return status;
01947 }
01948
01949 /**
01950   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
01951   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01952   *                     the configuration information for the specified DMA Stream.
01953   * @retval HAL status
01954   */
01955 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
01956 {
01957   uint32_t stream_number;
01958   uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
01959
01960   if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
01961   {
01962     /* BDMA Channels are connected to DMAMUX2 channels */
01963     stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
01964     hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
01965     hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
01966     hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
01967   }
01968   else
01969   {
01970     /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
01971     stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
01972
01973     if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
01974        (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
01975     {
01976       stream_number += 8U;
01977     }
01978     hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
01979     hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
01980     hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
01981   }
01982 }
01983
01984 /**
01985   * @brief  Updates the DMA handle with the DMAMUX  request generator params
01986   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01987   *                     the configuration information for the specified DMA Stream.
01988   * @retval HAL status
01989   */
01990 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
01991 {
01992   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
01993
01994   if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
01995   {
01996     if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
01997     {
01998       /* BDMA Channels are connected to DMAMUX2 request generator blocks */
01999       hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
02000
02001       hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
02002     }
02003     else
02004     {
02005       /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
02006       hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
02007
02008       hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
02009     }
02010
02011     hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
02012   }
02013 }
02014
02015 /**
02016   * @}
02017   */
02018
02019 #endif /* HAL_DMA_MODULE_ENABLED */
02020 /**
02021   * @}
02022   */
02023
02024 /**
02025   * @}
02026   */
02027
02028 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma.h Source File

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stm32h7xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DMA_H
00022 #define STM32H7xx_HAL_DMA_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DMA
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup DMA_Exported_Types DMA Exported Types
00042   * @brief    DMA Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  DMA Configuration Structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t Request;               /*!< Specifies the request selected for the specified stream.
00052                                            This parameter can be a value of @ref DMA_Request_selection              */
00053
00054   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
00055                                       from memory to memory or from peripheral to memory.
00056                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
00057
00058   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
00059                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
00060
00061   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
00062                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
00063
00064   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
00065                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
00066
00067   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
00068                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
00069
00070   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
00071                                       This parameter can be a value of @ref DMA_mode
00072                                       @note The circular buffer mode cannot be used if the memory-to-memory
00073                                             data transfer is configured on the selected Stream                        */
00074
00075   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
00076                                       This parameter can be a value of @ref DMA_Priority_level                        */
00077
00078   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
00079                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
00080                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
00081                                             memory-to-memory data transfer is configured on the selected stream       */
00082
00083   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
00084                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
00085
00086   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
00087                                       It specifies the amount of data to be transferred in a single non interruptible
00088                                       transaction.
00089                                       This parameter can be a value of @ref DMA_Memory_burst
00090                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00091
00092   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
00093                                       It specifies the amount of data to be transferred in a single non interruptible
00094                                       transaction.
00095                                       This parameter can be a value of @ref DMA_Peripheral_burst
00096                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00097 }DMA_InitTypeDef;
00098
00099 /**
00100   * @brief  HAL DMA State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
00105   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
00106   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
00107   HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
00108   HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
00109 }HAL_DMA_StateTypeDef;
00110
00111 /**
00112   * @brief  HAL DMA Transfer complete level structure definition
00113   */
00114 typedef enum
00115 {
00116   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00117   HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
00118 }HAL_DMA_LevelCompleteTypeDef;
00119
00120 /**
00121   * @brief  HAL DMA Callbacks IDs structure definition
00122   */
00123 typedef enum
00124 {
00125   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00126   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
00127   HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
00128   HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
00129   HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
00130   HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
00131   HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
00132 }HAL_DMA_CallbackIDTypeDef;
00133
00134 /**
00135   * @brief  DMA handle Structure definition
00136   */
00137 typedef struct __DMA_HandleTypeDef
00138 {
00139   void                            *Instance;                                                        /*!< Register base address                         */
00140
00141   DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
00142
00143   HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
00144
00145   __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
00146
00147   void                            *Parent;                                                          /*!< Parent object state                           */
00148
00149   void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
00150
00151   void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
00152
00153   void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
00154
00155   void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
00156
00157   void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
00158
00159   void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
00160
00161  __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
00162
00163  uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
00164
00165  uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
00166
00167  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
00168
00169  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
00170
00171  uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
00172
00173
00174  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
00175
00176  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
00177
00178  uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
00179
00180 }DMA_HandleTypeDef;
00181
00182 /**
00183   * @}
00184   */
00185
00186
00187 /* Exported constants --------------------------------------------------------*/
00188
00189 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00190   * @brief    DMA Exported constants
00191   * @{
00192   */
00193
00194 /** @defgroup DMA_Error_Code DMA Error Code
00195   * @brief    DMA Error Code
00196   * @{
00197   */
00198 #define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
00199 #define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
00200 #define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
00201 #define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
00202 #define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
00203 #define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
00204 #define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
00205 #define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
00206 #define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
00207 #define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
00208 #define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
00209
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup DMA_Request_selection DMA Request selection
00215   * @brief    DMA Request selection
00216   * @{
00217   */
00218 /* DMAMUX1 requests */
00219 #define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
00220
00221 #define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
00222 #define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
00223 #define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
00224 #define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
00225 #define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
00226 #define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
00227 #define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
00228 #define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
00229
00230 #define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
00231 #define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
00232
00233 #define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
00234 #define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
00235 #define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
00236 #define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
00237 #define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
00238 #define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
00239 #define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
00240
00241 #define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
00242 #define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
00243 #define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
00244 #define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
00245 #define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
00246
00247 #define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
00248 #define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
00249 #define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
00250 #define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
00251 #define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
00252 #define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
00253
00254 #define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
00255 #define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
00256 #define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
00257 #define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
00258
00259 #define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
00260 #define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
00261 #define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
00262 #define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
00263
00264 #define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
00265 #define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
00266 #define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
00267 #define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
00268
00269 #define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
00270 #define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
00271 #define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
00272 #define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
00273 #define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
00274 #define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
00275
00276 #define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
00277 #define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
00278 #define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
00279 #define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
00280 #define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
00281 #define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
00282 #define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
00283
00284 #define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
00285 #define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
00286 #define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
00287 #define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
00288 #define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
00289 #define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
00290
00291 #define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
00292 #define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
00293
00294 #define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
00295 #define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
00296 #define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
00297 #define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
00298
00299 #define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
00300 #define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
00301
00302 #define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
00303 #define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
00304
00305 #define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
00306 #define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
00307
00308 #define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
00309 #define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
00310
00311 #if defined (PSSI)
00312 #define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
00313 #define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
00314 #else
00315 #define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
00316 #endif /* PSSI */
00317
00318 #define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
00319 #define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
00320
00321 #define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
00322
00323 #define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
00324 #define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
00325 #define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
00326 #define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
00327
00328 #define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
00329 #define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
00330 #define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
00331 #define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
00332
00333 #define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
00334 #define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
00335 #define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
00336 #define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
00337
00338 #define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
00339 #define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
00340
00341 #define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
00342 #define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
00343
00344 #if defined(HRTIM1)
00345 #define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
00346 #define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
00347 #define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
00348 #define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
00349 #define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
00350 #define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
00351 #endif /* HRTIM1 */
00352
00353 #if defined(DFSDM1_Channel0)
00354 #define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
00355 #define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
00356 #define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
00357 #define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
00358 #endif /* DFSDM1_Channel0 */
00359
00360 #define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
00361 #define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
00362 #define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
00363 #define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
00364
00365 #define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
00366 #define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
00367
00368 #define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
00369 #define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
00370
00371 #if defined(SAI3)
00372 #define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
00373 #define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
00374 #endif /* SAI3 */
00375
00376 #if defined(ADC3)
00377 #define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
00378 #endif /* ADC3 */
00379
00380 #if defined(UART9)
00381 #define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
00382 #define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
00383 #endif /* UART9 */
00384
00385 #if defined(USART10)
00386 #define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
00387 #define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
00388 #endif /* USART10 */
00389
00390
00391 /* DMAMUX2 requests */
00392 #define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
00393 #define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
00394 #define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
00395 #define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
00396 #define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
00397 #define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
00398 #define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
00399 #define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
00400 #define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
00401 #define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
00402 #define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
00403 #define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
00404 #define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
00405 #define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
00406 #define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
00407 #if defined(SAI4)
00408 #define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
00409 #define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
00410 #endif /* SAI4 */
00411 #if defined(ADC3)
00412 #define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
00413 #endif /* ADC3 */
00414 #if defined(DAC2)
00415 #define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
00416 #endif /* DAC2 */
00417 #if defined(DFSDM2_Channel0)
00418 #define BDMA_REQUEST_DFSDM2          18U  /*!< DMAMUX2 DFSDM2 request      */
00419 #endif /* DFSDM1_Channel0 */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00426   * @brief    DMA data transfer direction
00427   * @{
00428   */
00429 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
00430 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
00431 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00437   * @brief    DMA peripheral incremented mode
00438   * @{
00439   */
00440 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
00441 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00447   * @brief    DMA memory incremented mode
00448   * @{
00449   */
00450 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
00451 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00457   * @brief    DMA peripheral data size
00458   * @{
00459   */
00460 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
00461 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
00462 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup DMA_Memory_data_size DMA Memory data size
00468   * @brief    DMA memory data size
00469   * @{
00470   */
00471 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
00472 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
00473 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup DMA_mode DMA mode
00479   * @brief    DMA mode
00480   * @{
00481   */
00482 #define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
00483 #define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
00484 #define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
00485 #define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
00486 #define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup DMA_Priority_level DMA Priority level
00492   * @brief    DMA priority levels
00493   * @{
00494   */
00495 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
00496 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
00497 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
00498 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
00504   * @brief    DMA FIFO direct mode
00505   * @{
00506   */
00507 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
00508 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
00514   * @brief    DMA FIFO level
00515   * @{
00516   */
00517 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
00518 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
00519 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
00520 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup DMA_Memory_burst DMA Memory burst
00526   * @brief    DMA memory burst
00527   * @{
00528   */
00529 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
00530 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
00531 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
00532 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
00533 /**
00534   * @}
00535   */
00536
00537 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
00538   * @brief    DMA peripheral burst
00539   * @{
00540   */
00541 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
00542 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
00543 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
00544 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00550   * @brief    DMA interrupts definition
00551   * @{
00552   */
00553 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
00554 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
00555 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
00556 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
00557 #define DMA_IT_FE                         ((uint32_t)0x00000080U)
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup DMA_flag_definitions DMA flag definitions
00563   * @brief    DMA flag definitions
00564   * @{
00565   */
00566 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
00567 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
00568 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
00569 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
00570 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
00571 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
00572 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
00573 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
00574 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
00575 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
00576 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
00577 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
00578 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
00579 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
00580 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
00581 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
00582 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
00583 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
00584 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
00585 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup BDMA_flag_definitions BDMA flag definitions
00591   * @brief    BDMA flag definitions
00592   * @{
00593   */
00594 #define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
00595 #define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
00596 #define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
00597 #define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
00598 #define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
00599 #define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
00600 #define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
00601 #define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
00602 #define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
00603 #define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
00604 #define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
00605 #define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
00606 #define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
00607 #define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
00608 #define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
00609 #define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
00610 #define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
00611 #define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
00612 #define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
00613 #define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
00614 #define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
00615 #define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
00616 #define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
00617 #define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
00618 #define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
00619 #define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
00620 #define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
00621 #define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
00622 #define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
00623 #define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
00624 #define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
00625 #define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
00626
00627 /**
00628   * @}
00629   */
00630
00631 /**
00632   * @}
00633   */
00634
00635 /* Exported macro ------------------------------------------------------------*/
00636 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00637   * @{
00638   */
00639
00640 /** @brief Reset DMA handle state
00641   * @param  __HANDLE__: specifies the DMA handle.
00642   * @retval None
00643   */
00644 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00645
00646 /**
00647   * @brief  Return the current DMA Stream FIFO filled level.
00648   * @param  __HANDLE__: DMA handle
00649   * @retval The FIFO filling state.
00650   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
00651   *                                              and not empty.
00652   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
00653   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
00654   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
00655   *           - DMA_FIFOStatus_Empty: when FIFO is empty
00656   *           - DMA_FIFOStatus_Full: when FIFO is full
00657   */
00658 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
00659
00660 /**
00661   * @brief  Enable the specified DMA Stream.
00662   * @param  __HANDLE__: DMA handle
00663   * @retval None
00664   */
00665 #define __HAL_DMA_ENABLE(__HANDLE__) \
00666 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
00667 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
00668
00669 /**
00670   * @brief  Disable the specified DMA Stream.
00671   * @param  __HANDLE__: DMA handle
00672   * @retval None
00673   */
00674 #define __HAL_DMA_DISABLE(__HANDLE__) \
00675 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
00676 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
00677
00678 /* Interrupt & Flag management */
00679
00680 /**
00681   * @brief  Return the current DMA Stream transfer complete flag.
00682   * @param  __HANDLE__: DMA handle
00683   * @retval The specified transfer complete flag index.
00684   */
00685 #if defined(BDMA1)
00686 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00687 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
00688  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
00689  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
00690  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
00691  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
00692  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
00693  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
00694  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
00695  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
00696  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
00697  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
00698  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
00699  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
00700  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
00701  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
00702  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
00703  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
00704  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
00705  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
00706  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
00707  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
00708  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
00709  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
00710  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
00711  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
00712  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
00713  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
00714  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
00715  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
00716  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
00717  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
00718  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
00719  (uint32_t)0x00000000)
00720 #else
00721 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00722 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
00723  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
00724  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
00725  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
00726  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
00727  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
00728  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
00729  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
00730  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
00731  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
00732  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
00733  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
00734  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
00735  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
00736  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
00737  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
00738  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
00739  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
00740  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
00741  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
00742  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
00743  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
00744  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
00745  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
00746  (uint32_t)0x00000000)
00747 #endif /* BDMA1 */
00748
00749 /**
00750   * @brief  Return the current DMA Stream half transfer complete flag.
00751   * @param  __HANDLE__: DMA handle
00752   * @retval The specified half transfer complete flag index.
00753   */
00754 #if defined(BDMA1)
00755 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00756 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
00757  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
00758  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
00759  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
00760  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
00761  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
00762  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
00763  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
00764  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
00765  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
00766  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
00767  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
00768  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
00769  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
00770  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
00771  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
00772  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
00773  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
00774  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
00775  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
00776  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
00777  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
00778  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
00779  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
00780  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
00781  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
00782  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
00783  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
00784  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
00785  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
00786  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
00787  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
00788  (uint32_t)0x00000000)
00789 #else
00790 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00791 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
00792  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
00793  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
00794  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
00795  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
00796  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
00797  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
00798  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
00799  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
00800  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
00801  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
00802  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
00803  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
00804  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
00805  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
00806  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
00807  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
00808  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
00809  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
00810  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
00811  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
00812  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
00813  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
00814  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
00815  (uint32_t)0x00000000)
00816 #endif /* BDMA1 */
00817
00818 /**
00819   * @brief  Return the current DMA Stream transfer error flag.
00820   * @param  __HANDLE__: DMA handle
00821   * @retval The specified transfer error flag index.
00822   */
00823 #if defined(BDMA1)
00824 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00825 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
00826  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
00827  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
00828  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
00829  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
00830  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
00831  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
00832  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
00833  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
00834  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
00835  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
00836  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
00837  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
00838  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
00839  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
00840  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
00841  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
00842  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
00843  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
00844  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
00845  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
00846  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
00847  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
00848  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
00849  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
00850  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
00851  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
00852  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
00853  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
00854  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
00855  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
00856  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
00857  (uint32_t)0x00000000)
00858 #else
00859 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00860 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
00861  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
00862  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
00863  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
00864  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
00865  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
00866  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
00867  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
00868  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
00869  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
00870  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
00871  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
00872  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
00873  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
00874  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
00875  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
00876  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
00877  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
00878  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
00879  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
00880  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
00881  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
00882  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
00883  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
00884  (uint32_t)0x00000000)
00885 #endif /* BDMA1 */
00886
00887 /**
00888   * @brief  Return the current DMA Stream FIFO error flag.
00889   * @param  __HANDLE__: DMA handle
00890   * @retval The specified FIFO error flag index.
00891   */
00892 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
00893 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
00894  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
00895  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
00896  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
00897  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
00898  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
00899  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
00900  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
00901  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
00902  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
00903  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
00904  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
00905  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
00906  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
00907  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
00908  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
00909   (uint32_t)0x00000000)
00910
00911 /**
00912   * @brief  Return the current DMA Stream direct mode error flag.
00913   * @param  __HANDLE__: DMA handle
00914   * @retval The specified direct mode error flag index.
00915   */
00916 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
00917 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
00918  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
00919  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
00920  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
00921  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
00922  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
00923  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
00924  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
00925  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
00926  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
00927  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
00928  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
00929  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
00930  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
00931  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
00932  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
00933   (uint32_t)0x00000000)
00934
00935 /**
00936   * @brief  Returns the current BDMA Channel Global interrupt flag.
00937   * @param  __HANDLE__: DMA handle
00938   * @retval The specified transfer error flag index.
00939   */
00940 #if defined(BDMA1)
00941 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00942 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
00943  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
00944  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
00945  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
00946  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
00947  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
00948  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
00949  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
00950  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
00951  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
00952  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
00953  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
00954  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
00955  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
00956  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
00957  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
00958  (uint32_t)0x00000000)
00959 #else
00960 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00961 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
00962  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
00963  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
00964  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
00965  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
00966  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
00967  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
00968  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
00969   (uint32_t)0x00000000)
00970 #endif /* BDMA1 */
00971
00972 /**
00973   * @brief  Get the DMA Stream pending flags.
00974   * @param  __HANDLE__: DMA handle
00975   * @param  __FLAG__: Get the specified flag.
00976   *          This parameter can be any combination of the following values:
00977   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00978   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00979   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00980   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00981   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00982   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00983   * @retval The state of FLAG (SET or RESET).
00984   */
00985 #if defined(BDMA1)
00986 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00987 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
00988  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
00989  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
00990  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
00991  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
00992 #else
00993 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00994 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
00995  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
00996  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
00997  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
00998 #endif /* BDMA1 */
00999
01000 /**
01001   * @brief  Clear the DMA Stream pending flags.
01002   * @param  __HANDLE__: DMA handle
01003   * @param  __FLAG__: specifies the flag to clear.
01004   *          This parameter can be any combination of the following values:
01005   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
01006   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
01007   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
01008   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
01009   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
01010   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
01011   * @retval None
01012   */
01013 #if defined(BDMA1)
01014 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
01015 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
01016  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
01017  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
01018  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
01019  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
01020 #else
01021 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
01022 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
01023  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
01024  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
01025  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
01026 #endif /* BDMA1 */
01027
01028 #define DMA_TO_BDMA_IT(__DMA_IT__) \
01029 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
01030  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
01031  (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
01032  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
01033  ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
01034  ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
01035  ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
01036  (uint32_t)0x00000000)
01037
01038
01039 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
01040 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
01041
01042 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
01043 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
01044
01045 /**
01046   * @brief  Enable the specified DMA Stream interrupts.
01047   * @param  __HANDLE__: DMA handle
01048   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
01049   *        This parameter can be one of the following values:
01050   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
01051   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
01052   *           @arg DMA_IT_TE: Transfer error interrupt mask.
01053   *           @arg DMA_IT_FE: FIFO error interrupt mask.
01054   *           @arg DMA_IT_DME: Direct mode error interrupt.
01055   * @retval None
01056   */
01057 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
01058                                                         (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
01059                                                         (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
01060
01061
01062 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
01063
01064 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
01065 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
01066
01067 /**
01068   * @brief  Disable the specified DMA Stream interrupts.
01069   * @param  __HANDLE__: DMA handle
01070   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
01071   *         This parameter can be one of the following values:
01072   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
01073   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
01074   *            @arg DMA_IT_TE: Transfer error interrupt mask.
01075   *            @arg DMA_IT_FE: FIFO error interrupt mask.
01076   *            @arg DMA_IT_DME: Direct mode error interrupt.
01077   * @retval None
01078   */
01079 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
01080                                                          (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
01081                                                          (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
01082
01083
01084 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
01085
01086 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
01087                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
01088                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
01089
01090 /**
01091   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
01092   * @param  __HANDLE__: DMA handle
01093   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
01094   *         This parameter can be one of the following values:
01095   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
01096   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
01097   *            @arg DMA_IT_TE: Transfer error interrupt mask.
01098   *            @arg DMA_IT_FE: FIFO error interrupt mask.
01099   *            @arg DMA_IT_DME: Direct mode error interrupt.
01100   * @retval The state of DMA_IT.
01101   */
01102 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
01103                                                             (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
01104                                                             (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
01105
01106 /**
01107   * @brief  Writes the number of data units to be transferred on the DMA Stream.
01108   * @param  __HANDLE__: DMA handle
01109   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
01110   *          Number of data items depends only on the Peripheral data format.
01111   *
01112   * @note   If Peripheral data format is Bytes: number of data units is equal
01113   *         to total number of bytes to be transferred.
01114   *
01115   * @note   If Peripheral data format is Half-Word: number of data units is
01116   *         equal to total number of bytes to be transferred / 2.
01117   *
01118   * @note   If Peripheral data format is Word: number of data units is equal
01119   *         to total  number of bytes to be transferred / 4.
01120   *
01121   * @retval The number of remaining data units in the current DMAy Streamx transfer.
01122   */
01123 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
01124                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
01125                                                         (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
01126
01127 /**
01128   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
01129   * @param  __HANDLE__: DMA handle
01130   *
01131   * @retval The number of remaining data units in the current DMA Stream transfer.
01132   */
01133 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
01134                                            (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
01135                                            (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
01136
01137 /**
01138   * @}
01139   */
01140
01141 /* Include DMA HAL Extension module */
01142 #include "stm32h7xx_hal_dma_ex.h"
01143
01144 /* Exported functions --------------------------------------------------------*/
01145
01146 /** @defgroup DMA_Exported_Functions DMA Exported Functions
01147   * @brief    DMA Exported functions
01148   * @{
01149   */
01150
01151 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
01152   * @brief   Initialization and de-initialization functions
01153   * @{
01154   */
01155 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
01156 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
01157 /**
01158   * @}
01159   */
01160
01161 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
01162   * @brief   I/O operation functions
01163   * @{
01164   */
01165 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
01166 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
01167 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
01168 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
01169 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
01170 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
01171 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
01172 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
01173
01174 /**
01175   * @}
01176   */
01177
01178 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
01179   * @brief    Peripheral State functions
01180   * @{
01181   */
01182 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
01183 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
01184 /**
01185   * @}
01186   */
01187 /**
01188   * @}
01189   */
01190 /* Private Constants -------------------------------------------------------------*/
01191 /** @defgroup DMA_Private_Constants DMA Private Constants
01192   * @brief    DMA private defines and constants
01193   * @{
01194   */
01195 /**
01196   * @}
01197   */
01198
01199 /* Private macros ------------------------------------------------------------*/
01200 /** @defgroup DMA_Private_Macros DMA Private Macros
01201   * @brief    DMA private macros
01202   * @{
01203   */
01204
01205 #if defined(ADC3)
01206 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
01207 #else
01208 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
01209 #endif /* ADC3 */
01210
01211 #if defined(ADC3)
01212 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
01213 #else
01214 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2))
01215 #endif /* ADC3 */
01216
01217 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
01218                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
01219                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
01220
01221 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
01222
01223 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
01224                                             ((STATE) == DMA_PINC_DISABLE))
01225
01226 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
01227                                         ((STATE) == DMA_MINC_DISABLE))
01228
01229 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
01230                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
01231                                            ((SIZE) == DMA_PDATAALIGN_WORD))
01232
01233 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
01234                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
01235                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
01236
01237 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
01238                            ((MODE) == DMA_CIRCULAR)          || \
01239                            ((MODE) == DMA_PFCTRL)            || \
01240                            ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
01241                            ((MODE) == DMA_DOUBLE_BUFFER_M1))
01242
01243 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
01244                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
01245                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
01246                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
01247
01248 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
01249                                        ((STATE) == DMA_FIFOMODE_ENABLE))
01250
01251 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
01252                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
01253                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
01254                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
01255
01256 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
01257                                     ((BURST) == DMA_MBURST_INC4)   || \
01258                                     ((BURST) == DMA_MBURST_INC8)   || \
01259                                     ((BURST) == DMA_MBURST_INC16))
01260
01261 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
01262                                         ((BURST) == DMA_PBURST_INC4)   || \
01263                                         ((BURST) == DMA_PBURST_INC8)   || \
01264                                         ((BURST) == DMA_PBURST_INC16))
01265 /**
01266   * @}
01267   */
01268
01269 /* Private functions ---------------------------------------------------------*/
01270 /** @defgroup DMA_Private_Functions DMA Private Functions
01271   * @brief    DMA private  functions
01272   * @{
01273   */
01274 /**
01275   * @}
01276   */
01277
01278 /**
01279   * @}
01280   */
01281
01282 /**
01283   * @}
01284   */
01285
01286 #ifdef __cplusplus
01287 }
01288 #endif
01289
01290 #endif /* STM32H7xx_HAL_DMA_H */
01291
01292 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma_ex.c Source File

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stm32h7xx_hal_dma_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DMA Extension HAL module driver
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DMA Extension peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015   The DMA Extension HAL driver can be used as follows:
00016    (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
00017        for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
00018
00019    (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00020    (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00021        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00022        to respectively enable/disable the request generator.
00023
00024    (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
00025        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
00026        As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
00027        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
00028       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
00029
00030      -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
00031      -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
00032      -@-  In Multi (Double) buffer mode, it is possible to update the base address for
00033           the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
00034      -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
00035
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00041   * All rights reserved.</center></h2>
00042   *
00043   * This software component is licensed by ST under BSD 3-Clause license,
00044   * the "License"; You may not use this file except in compliance with the
00045   * License. You may obtain a copy of the License at:
00046   *                        opensource.org/licenses/BSD-3-Clause
00047   *
00048   ******************************************************************************
00049   */
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32h7xx_hal.h"
00053
00054 /** @addtogroup STM32H7xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @defgroup DMAEx DMAEx
00059   * @brief DMA Extended HAL module driver
00060   * @{
00061   */
00062
00063 #ifdef HAL_DMA_MODULE_ENABLED
00064
00065 /* Private types -------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private Constants ---------------------------------------------------------*/
00068 /* Private macros ------------------------------------------------------------*/
00069 /* Private functions ---------------------------------------------------------*/
00070 /** @addtogroup DMAEx_Private_Functions
00071   * @{
00072   */
00073
00074 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00075
00076 /**
00077   * @}
00078   */
00079
00080 /* Exported functions ---------------------------------------------------------*/
00081
00082 /** @addtogroup DMAEx_Exported_Functions
00083   * @{
00084   */
00085
00086
00087 /** @addtogroup DMAEx_Exported_Functions_Group1
00088   *
00089 @verbatim
00090  ===============================================================================
00091                 #####  Extended features functions  #####
00092  ===============================================================================
00093     [..]  This section provides functions allowing to:
00094       (+) Configure the source, destination address and data length and
00095           Start MultiBuffer DMA transfer
00096       (+) Configure the source, destination address and data length and
00097           Start MultiBuffer DMA transfer with interrupt
00098       (+) Change on the fly the memory0 or memory1 address.
00099       (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00100       (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00101       (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00102           to respectively enable/disable the request generator.
00103       (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
00104           the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
00105
00106 @endverbatim
00107   * @{
00108   */
00109
00110
00111 /**
00112   * @brief  Starts the multi_buffer DMA Transfer.
00113   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00114   *                     the configuration information for the specified DMA Stream.
00115   * @param  SrcAddress: The source memory Buffer address
00116   * @param  DstAddress: The destination memory Buffer address
00117   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00118   * @param  DataLength: The length of data to be transferred from source to destination
00119   * @retval HAL status
00120   */
00121 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00122 {
00123   HAL_StatusTypeDef status = HAL_OK;
00124   __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
00125
00126   /* Check the parameters */
00127   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00128   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00129
00130   /* Memory-to-memory transfer not supported in double buffering mode */
00131   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00132   {
00133     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00134     status = HAL_ERROR;
00135   }
00136   else
00137   {
00138     /* Process Locked */
00139     __HAL_LOCK(hdma);
00140
00141     if(HAL_DMA_STATE_READY == hdma->State)
00142     {
00143       /* Change DMA peripheral state */
00144       hdma->State = HAL_DMA_STATE_BUSY;
00145
00146       /* Initialize the error code */
00147       hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00148
00149       if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00150       {
00151         /* Enable the Double buffer mode */
00152         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
00153
00154         /* Configure DMA Stream destination address */
00155         ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
00156
00157         /* Calculate the interrupt clear flag register (IFCR) base address  */
00158         ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
00159
00160         /* Clear all flags */
00161         *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
00162       }
00163       else /* BDMA instance(s) */
00164       {
00165         /* Enable the Double buffer mode */
00166         ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
00167
00168         /* Configure DMA Stream destination address */
00169         ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
00170
00171         /* Calculate the interrupt clear flag register (IFCR) base address  */
00172         ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
00173
00174         /* Clear all flags */
00175         *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
00176       }
00177
00178       if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00179       {
00180         /* Configure the source, destination address and the data length */
00181         DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00182
00183         /* Clear the DMAMUX synchro overrun flag */
00184         hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00185
00186         if(hdma->DMAmuxRequestGen != 0U)
00187         {
00188           /* Clear the DMAMUX request generator overrun flag */
00189           hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00190         }
00191       }
00192
00193       /* Enable the peripheral */
00194       __HAL_DMA_ENABLE(hdma);
00195     }
00196     else
00197     {
00198       /* Set the error code to busy */
00199       hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00200
00201       /* Return error status */
00202       status = HAL_ERROR;
00203     }
00204   }
00205   return status;
00206 }
00207
00208 /**
00209   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
00210   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00211   *                     the configuration information for the specified DMA Stream.
00212   * @param  SrcAddress: The source memory Buffer address
00213   * @param  DstAddress: The destination memory Buffer address
00214   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00215   * @param  DataLength: The length of data to be transferred from source to destination
00216   * @retval HAL status
00217   */
00218 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00219 {
00220   HAL_StatusTypeDef status = HAL_OK;
00221   __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
00222
00223   /* Check the parameters */
00224   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00225   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00226
00227   /* Memory-to-memory transfer not supported in double buffering mode */
00228   if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00229   {
00230     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00231     return HAL_ERROR;
00232   }
00233
00234   /* Process locked */
00235   __HAL_LOCK(hdma);
00236
00237   if(HAL_DMA_STATE_READY == hdma->State)
00238   {
00239     /* Change DMA peripheral state */
00240     hdma->State = HAL_DMA_STATE_BUSY;
00241
00242     /* Initialize the error code */
00243     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00244
00245     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00246     {
00247       /* Enable the Double buffer mode */
00248       ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
00249
00250       /* Configure DMA Stream destination address */
00251       ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
00252
00253       /* Calculate the interrupt clear flag register (IFCR) base address  */
00254       ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
00255
00256       /* Clear all flags */
00257       *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
00258     }
00259     else /* BDMA instance(s) */
00260     {
00261       /* Enable the Double buffer mode */
00262       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
00263
00264       /* Configure DMA Stream destination address */
00265       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
00266
00267       /* Calculate the interrupt clear flag register (IFCR) base address  */
00268       ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
00269
00270       /* Clear all flags */
00271       *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
00272     }
00273
00274     /* Configure the source, destination address and the data length */
00275     DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00276
00277     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00278     {
00279       /* Clear the DMAMUX synchro overrun flag */
00280       hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00281
00282       if(hdma->DMAmuxRequestGen != 0U)
00283       {
00284         /* Clear the DMAMUX request generator overrun flag */
00285         hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00286       }
00287     }
00288
00289     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00290     {
00291       /* Enable Common interrupts*/
00292       MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
00293       ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
00294
00295       if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
00296       {
00297         /*Enable Half Transfer IT if corresponding Callback is set*/
00298         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
00299       }
00300     }
00301     else /* BDMA instance(s) */
00302     {
00303       /* Enable Common interrupts*/
00304       MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
00305
00306       if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
00307       {
00308         /*Enable Half Transfer IT if corresponding Callback is set*/
00309         ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
00310       }
00311     }
00312
00313     if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
00314     {
00315       /* Check if DMAMUX Synchronization is enabled*/
00316       if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00317       {
00318         /* Enable DMAMUX sync overrun IT*/
00319         hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00320       }
00321
00322       if(hdma->DMAmuxRequestGen != 0U)
00323       {
00324         /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00325         /* enable the request gen overrun IT*/
00326         hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00327       }
00328     }
00329
00330     /* Enable the peripheral */
00331     __HAL_DMA_ENABLE(hdma);
00332   }
00333   else
00334   {
00335     /* Set the error code to busy */
00336     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00337
00338     /* Return error status */
00339     status = HAL_ERROR;
00340   }
00341   return status;
00342 }
00343
00344 /**
00345   * @brief  Change the memory0 or memory1 address on the fly.
00346   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00347   *                     the configuration information for the specified DMA Stream.
00348   * @param  Address:    The new address
00349   * @param  memory:     the memory to be changed, This parameter can be one of
00350   *                     the following values:
00351   *                      MEMORY0 /
00352   *                      MEMORY1
00353   * @note   The MEMORY0 address can be changed only when the current transfer use
00354   *         MEMORY1 and the MEMORY1 address can be changed only when the current
00355   *         transfer use MEMORY0.
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
00359 {
00360   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00361   {
00362     if(memory == MEMORY0)
00363     {
00364       /* change the memory0 address */
00365       ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
00366     }
00367     else
00368     {
00369       /* change the memory1 address */
00370       ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
00371     }
00372   }
00373   else /* BDMA instance(s) */
00374   {
00375     if(memory == MEMORY0)
00376     {
00377       /* change the memory0 address */
00378       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = Address;
00379     }
00380     else
00381     {
00382       /* change the memory1 address */
00383       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = Address;
00384     }
00385   }
00386
00387   return HAL_OK;
00388 }
00389
00390 /**
00391   * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
00392   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00393   *                     the configuration information for the specified DMA Stream.
00394   * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
00398 {
00399   uint32_t syncSignalID = 0;
00400   uint32_t syncPolarity = 0;
00401
00402   /* Check the parameters */
00403   assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
00404   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
00405   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
00406   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
00407
00408   if(pSyncConfig->SyncEnable == ENABLE)
00409   {
00410     assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
00411
00412     if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00413     {
00414       assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00415     }
00416     else
00417     {
00418       assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00419     }
00420     syncSignalID = pSyncConfig->SyncSignalID;
00421     syncPolarity = pSyncConfig->SyncPolarity;
00422   }
00423
00424   /*Check if the DMA state is ready */
00425   if(hdma->State == HAL_DMA_STATE_READY)
00426   {
00427     /* Process Locked */
00428     __HAL_LOCK(hdma);
00429
00430     /* Disable the synchronization and event generation before applying a new config */
00431     CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
00432
00433     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
00434     MODIFY_REG( hdma->DMAmuxChannel->CCR, \
00435                (~DMAMUX_CxCR_DMAREQ_ID) , \
00436                (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos)       | \
00437                ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
00438                syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)    | \
00439                ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
00440
00441       /* Process Locked */
00442     __HAL_UNLOCK(hdma);
00443
00444     return HAL_OK;
00445   }
00446   else
00447   {
00448     /* Set the error code to busy */
00449     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00450
00451     /* Return error status */
00452     return HAL_ERROR;
00453   }
00454 }
00455
00456 /**
00457   * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
00458   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00459   *                     the configuration information for the specified DMA Stream.
00460   * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
00461   *         contains the request generator parameters.
00462   *
00463   * @retval HAL status
00464   */
00465 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
00466 {
00467   HAL_StatusTypeDef status;
00468   HAL_DMA_StateTypeDef temp_state = hdma->State;
00469
00470   /* Check the parameters */
00471   assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
00472
00473   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00474   {
00475     assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00476   }
00477   else
00478   {
00479     assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00480   }
00481
00482
00483   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
00484   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
00485
00486   /* check if the DMA state is ready
00487      and DMA is using a DMAMUX request generator block
00488   */
00489   if(hdma->DMAmuxRequestGen == 0U)
00490   {
00491     /* Set the error code to busy */
00492     hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00493
00494     /* error status */
00495     status = HAL_ERROR;
00496   }
00497   else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
00498   {
00499     /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
00500
00501     /* Process Locked */
00502     __HAL_LOCK(hdma);
00503
00504     /* Set the request generator new parameters */
00505     hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
00506                                   ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
00507                                   pRequestGeneratorConfig->Polarity;
00508     /* Process Locked */
00509     __HAL_UNLOCK(hdma);
00510
00511     return HAL_OK;
00512   }
00513   else
00514   {
00515     /* Set the error code to busy */
00516     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00517
00518     /* error status */
00519     status = HAL_ERROR;
00520   }
00521
00522   return status;
00523 }
00524
00525 /**
00526   * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
00527   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00528   *                     the configuration information for the specified DMA Stream.
00529   * @retval HAL status
00530   */
00531 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
00532 {
00533   /* Check the parameters */
00534   assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
00535
00536   /* check if the DMA state is ready
00537      and DMA is using a DMAMUX request generator block */
00538   if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
00539   {
00540     /* Enable the request generator*/
00541     hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
00542
00543    return HAL_OK;
00544  }
00545  else
00546  {
00547    return HAL_ERROR;
00548  }
00549 }
00550
00551 /**
00552   * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
00553   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00554   *                     the configuration information for the specified DMA Stream.
00555   * @retval HAL status
00556   */
00557 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
00558 {
00559   /* Check the parameters */
00560   assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
00561
00562   /* check if the DMA state is ready
00563      and DMA is using a DMAMUX request generator block */
00564   if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
00565   {
00566     /* Disable the request generator*/
00567     hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
00568
00569    return HAL_OK;
00570  }
00571  else
00572  {
00573    return HAL_ERROR;
00574  }
00575 }
00576
00577 /**
00578   * @brief  Handles DMAMUX interrupt request.
00579   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00580   *               the configuration information for the specified DMA Stream.
00581   * @retval None
00582   */
00583 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
00584 {
00585   /* Check for DMAMUX Synchronization overrun */
00586   if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00587   {
00588     /* Disable the synchro overrun interrupt */
00589     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00590
00591     /* Clear the DMAMUX synchro overrun flag */
00592     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00593
00594     /* Update error code */
00595     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00596
00597     if(hdma->XferErrorCallback != NULL)
00598     {
00599       /* Transfer error callback */
00600       hdma->XferErrorCallback(hdma);
00601     }
00602   }
00603
00604   if(hdma->DMAmuxRequestGen != 0)
00605   {
00606    /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
00607     if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00608     {
00609       /* Disable the request gen overrun interrupt */
00610       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00611
00612       /* Clear the DMAMUX request generator overrun flag */
00613       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00614
00615       /* Update error code */
00616       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00617
00618       if(hdma->XferErrorCallback != NULL)
00619       {
00620         /* Transfer error callback */
00621         hdma->XferErrorCallback(hdma);
00622       }
00623     }
00624   }
00625 }
00626
00627
00628 /**
00629   * @}
00630   */
00631
00632 /**
00633   * @}
00634   */
00635
00636 /** @addtogroup DMAEx_Private_Functions
00637   * @{
00638   */
00639
00640 /**
00641   * @brief  Set the DMA Transfer parameter.
00642   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00643   *                     the configuration information for the specified DMA Stream.
00644   * @param  SrcAddress: The source memory Buffer address
00645   * @param  DstAddress: The destination memory Buffer address
00646   * @param  DataLength: The length of data to be transferred from source to destination
00647   * @retval HAL status
00648   */
00649 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00650 {
00651   if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
00652   {
00653     /* Configure DMA Stream data length */
00654     ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
00655
00656     /* Peripheral to Memory */
00657     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00658     {
00659       /* Configure DMA Stream destination address */
00660       ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
00661
00662       /* Configure DMA Stream source address */
00663       ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
00664     }
00665     /* Memory to Peripheral */
00666     else
00667     {
00668       /* Configure DMA Stream source address */
00669       ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
00670
00671       /* Configure DMA Stream destination address */
00672       ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
00673     }
00674   }
00675   else /* BDMA instance(s) */
00676   {
00677     /* Configure DMA Stream data length */
00678     ((BDMA_Channel_TypeDef   *)hdma->Instance)->CNDTR = DataLength;
00679
00680     /* Peripheral to Memory */
00681     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00682     {
00683       /* Configure DMA Stream destination address */
00684       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = DstAddress;
00685
00686       /* Configure DMA Stream source address */
00687       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = SrcAddress;
00688     }
00689     /* Memory to Peripheral */
00690     else
00691     {
00692       /* Configure DMA Stream source address */
00693       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = SrcAddress;
00694
00695       /* Configure DMA Stream destination address */
00696       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = DstAddress;
00697     }
00698   }
00699 }
00700
00701 /**
00702   * @}
00703   */
00704
00705 #endif /* HAL_DMA_MODULE_ENABLED */
00706 /**
00707   * @}
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dma_ex.h Source File

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stm32h7xx_hal_dma_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DMA_EX_H
00022 #define STM32H7xx_HAL_DMA_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DMAEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00041   * @brief DMAEx Exported types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL DMA Memory definition
00047   */
00048 typedef enum
00049 {
00050   MEMORY0      = 0x00U,    /*!< Memory 0     */
00051   MEMORY1      = 0x01U,    /*!< Memory 1     */
00052
00053 }HAL_DMA_MemoryTypeDef;
00054
00055 /**
00056   * @brief  HAL DMAMUX Synchronization configuration structure definition
00057   */
00058 typedef struct
00059 {
00060   uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
00061                               This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
00062
00063   uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
00064                               This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
00065
00066   FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
00067                                     This parameter can take the value ENABLE or DISABLE*/
00068
00069
00070   FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
00071                                        This parameter can take the value ENABLE or DISABLE */
00072
00073   uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
00074                                This parameters can be in the range 1 to 32 */
00075
00076 }HAL_DMA_MuxSyncConfigTypeDef;
00077
00078
00079 /**
00080   * @brief  HAL DMAMUX request generator parameters structure definition
00081   */
00082 typedef struct
00083 {
00084  uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
00085                               This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
00086
00087   uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
00088                              This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
00089
00090   uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.
00091                                 This parameters can be in the range 1 to 32 */
00092
00093 }HAL_DMA_MuxRequestGeneratorConfigTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup DMAEx_Exported_Constants DMA Exported Constants
00102   * @brief    DMAEx Exported constants
00103   * @{
00104   */
00105
00106 /** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
00107   * @brief    DMAEx MUX SyncSignalID selection
00108   * @{
00109   */
00110 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
00111 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
00112 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
00113 #define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
00114 #define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
00115 #define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
00116 #define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
00117 #define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
00118
00119 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
00120 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
00121 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
00122 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
00123 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
00124 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
00125 #define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
00126 #define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
00127 #define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
00128 #define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
00129 #define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
00130 #define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
00131 #define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
00132 #define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
00133 #define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
00134 #define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
00141   * @brief    DMAEx MUX SyncPolarity selection
00142   * @{
00143   */
00144 #define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */
00145 #define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */
00146 #define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */
00147 #define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */
00148
00149 /**
00150   * @}
00151   */
00152
00153
00154 /** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
00155   * @brief    DMAEx MUX SignalGeneratorID selection
00156   * @{
00157   */
00158 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
00159 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
00160 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
00161 #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */
00162 #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */
00163 #define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */
00164 #define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */
00165 #define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */
00166
00167 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
00168 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
00169 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
00170 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
00171 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
00172 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
00173 #define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
00174 #define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */
00175 #define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */
00176 #define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */
00177 #define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
00178 #define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
00179 #define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
00180 #if defined(LPTIM4)
00181 #define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
00182 #endif /* LPTIM4 */
00183 #if defined(LPTIM5)
00184 #define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
00185 #endif /* LPTIM5 */
00186 #define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
00187 #define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
00188 #define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
00189 #define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */
00190 #define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */
00191 #define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */
00192 #define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */
00193 #define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */
00194 #define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
00195 #define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
00196 #define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
00197 #if defined(ADC3)
00198 #define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
00199 #define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
00200 #endif /* ADC3 */
00201 #define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
00202 #define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
00203
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
00210   * @brief    DMAEx MUX RequestGeneneratorPolarity selection
00211   * @{
00212   */
00213 #define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */
00214 #define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */
00215 #define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */
00216 #define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */
00217
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Exported functions --------------------------------------------------------*/
00227 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00228   * @brief   DMAEx Exported functions
00229   * @{
00230   */
00231
00232 /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
00233   * @brief   Extended features functions
00234   * @{
00235   */
00236
00237 /* IO operation functions *******************************************************/
00238 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00239 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00240 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
00241 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
00242 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
00243 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
00244 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
00245
00246 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
00247 /**
00248   * @}
00249   */
00250 /**
00251   * @}
00252   */
00253
00254 /* Private macros ------------------------------------------------------------*/
00255 /** @defgroup DMAEx_Private_Macros DMA Private Macros
00256   * @brief    DMAEx private macros
00257   * @{
00258   */
00259
00260 #define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
00261 #define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
00262
00263 #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00264
00265 #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
00266                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
00267                                            ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
00268                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
00269
00270 #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
00271
00272 #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
00273                                      ((EVENT) == ENABLE))
00274
00275 #define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
00276 #define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
00277
00278 #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00279
00280 #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
00281                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
00282                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
00283                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
00284
00285 /**
00286   * @}
00287   */
00288
00289 /* Private functions ---------------------------------------------------------*/
00290 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
00291   * @brief DMAEx Private functions
00292   * @{
00293   */
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 #ifdef __cplusplus
00307 }
00308 #endif
00309
00310 #endif /* STM32H7xx_HAL_DMA_H */
00311
00312 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dsi.c Source File

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stm32h7xx_hal_dsi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dsi.c
00004   * @author  MCD Application Team
00005   * @brief   DSI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DSI peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
00018         PLL parameters, number of lanes and TX Escape clock divider.
00019     (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
00020         command mode.
00021     (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
00022     (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
00023     (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
00024     (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
00025         Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
00026         to write DSI short packets, long packets and to read DSI packets.
00027
00028     (#) The DSI Host Offers two Low power modes :
00029         (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
00030             It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
00031             and @ref HAL_DSI_ExitULPMData()
00032
00033         (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
00034             It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
00035             and @ref HAL_DSI_ExitULPM()
00036
00037     (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
00038         When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
00039         the error code by calling function @ref HAL_DSI_GetError()
00040
00041     (#) To control DSI state you can use the following function: HAL_DSI_GetState()
00042
00043      *** DSI HAL driver macros list ***
00044      =============================================
00045      [..]
00046        Below the list of most used macros in DSI HAL driver.
00047
00048       (+) __HAL_DSI_ENABLE: Enable the DSI Host.
00049       (+) __HAL_DSI_DISABLE: Disable the DSI Host.
00050       (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
00051       (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
00052       (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
00053       (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
00054       (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
00055       (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
00056       (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
00057       (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
00058       (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
00059       (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
00060       (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
00061
00062
00063
00064   *** Callback registration ***
00065   =============================================
00066
00067   The compilation define  USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
00068   allows the user to configure dynamically the driver callbacks.
00069   Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
00070
00071   Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
00072     (+) TearingEffectCallback : DSI Tearing Effect Callback.
00073     (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
00074     (+) ErrorCallback         : DSI Error Callback
00075     (+) MspInitCallback       : DSI MspInit.
00076     (+) MspDeInitCallback     : DSI MspDeInit.
00077   This function takes as parameters the HAL peripheral handle, the Callback ID
00078   and a pointer to the user callback function.
00079
00080   Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
00081   weak function.
00082   @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00083   and the Callback ID.
00084   This function allows to reset following callbacks:
00085     (+) TearingEffectCallback : DSI Tearing Effect Callback.
00086     (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
00087     (+) ErrorCallback         : DSI Error Callback
00088     (+) MspInitCallback       : DSI MspInit.
00089     (+) MspDeInitCallback     : DSI MspDeInit.
00090
00091   By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
00092   all callbacks are set to the corresponding weak functions:
00093   examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
00094   Exception done for MspInit and MspDeInit functions that are
00095   reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
00096   these callbacks are null (not registered beforehand).
00097   if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
00098   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00099
00100   Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
00101   Exception done MspInit/MspDeInit that can be registered/unregistered
00102   in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
00103   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00104   In that case first register the MspInit/MspDeInit user callbacks
00105   using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
00106   or HAL_DSI_Init function.
00107
00108   When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
00109   not defined, the callback registration feature is not available and all callbacks
00110   are set to the corresponding weak functions.
00111
00112      [..]
00113        (@) You can refer to the DSI HAL driver header file for more useful macros
00114
00115   @endverbatim
00116   ******************************************************************************
00117   * @attention
00118   *
00119   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00120   * All rights reserved.</center></h2>
00121   *
00122   * This software component is licensed by ST under BSD 3-Clause license,
00123   * the "License"; You may not use this file except in compliance with the
00124   * License. You may obtain a copy of the License at:
00125   *                        opensource.org/licenses/BSD-3-Clause
00126   *
00127   ******************************************************************************
00128   */
00129
00130 /* Includes ------------------------------------------------------------------*/
00131 #include "stm32h7xx_hal.h"
00132
00133 /** @addtogroup STM32H7xx_HAL_Driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_DSI_MODULE_ENABLED
00138
00139 #if defined(DSI)
00140
00141 /** @addtogroup DSI
00142   * @{
00143   */
00144
00145 /* Private types -------------------------------------------------------------*/
00146 /* Private defines -----------------------------------------------------------*/
00147 /** @addtogroup DSI_Private_Constants
00148   * @{
00149   */
00150 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U)  /* 1s */
00151
00152 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
00153                             DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
00154                             DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
00155                             DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
00156 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
00157 #define DSI_ERROR_TX_MASK  DSI_ISR1_TOHSTX
00158 #define DSI_ERROR_RX_MASK  DSI_ISR1_TOLPRX
00159 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
00160 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
00161 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
00162 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
00163 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
00164 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
00165 /**
00166   * @}
00167   */
00168
00169 /* Private variables ---------------------------------------------------------*/
00170 /* Private constants ---------------------------------------------------------*/
00171 /* Private macros ------------------------------------------------------------*/
00172 /* Private function prototypes -----------------------------------------------*/
00173 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
00174                                    uint32_t Data1);
00175
00176 static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
00177                                      uint32_t ChannelID,
00178                                      uint32_t Mode,
00179                                      uint32_t Param1,
00180                                      uint32_t Param2);
00181
00182 /* Private functions ---------------------------------------------------------*/
00183 /**
00184   * @brief  Generic DSI packet header configuration
00185   * @param  DSIx  Pointer to DSI register base
00186   * @param  ChannelID Virtual channel ID of the header packet
00187   * @param  DataType  Packet data type of the header packet
00188   *                   This parameter can be any value of :
00189   *                      @arg DSI_SHORT_WRITE_PKT_Data_Type
00190   *                      @arg DSI_LONG_WRITE_PKT_Data_Type
00191   *                      @arg DSI_SHORT_READ_PKT_Data_Type
00192   *                      @arg DSI_MAX_RETURN_PKT_SIZE
00193   * @param  Data0  Word count LSB
00194   * @param  Data1  Word count MSB
00195   * @retval None
00196   */
00197 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
00198                                    uint32_t ChannelID,
00199                                    uint32_t DataType,
00200                                    uint32_t Data0,
00201                                    uint32_t Data1)
00202 {
00203   /* Update the DSI packet header with new information */
00204   DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
00205 }
00206
00207 /**
00208   * @brief  write short DCS or short Generic command
00209   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00210   *               the configuration information for the DSI.
00211   * @param  ChannelID  Virtual channel ID.
00212   * @param  Mode  DSI short packet data type.
00213   *               This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
00214   * @param  Param1  DSC command or first generic parameter.
00215   *                 This parameter can be any value of @arg DSI_DCS_Command or a
00216   *                 generic command code.
00217   * @param  Param2  DSC parameter or second generic parameter.
00218   * @retval HAL status
00219   */
00220 static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
00221                                         uint32_t ChannelID,
00222                                         uint32_t Mode,
00223                                         uint32_t Param1,
00224                                         uint32_t Param2)
00225 {
00226   uint32_t tickstart;
00227
00228   /* Get tick */
00229   tickstart = HAL_GetTick();
00230
00231   /* Wait for Command FIFO Empty */
00232   while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
00233   {
00234     /* Check for the Timeout */
00235     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
00236     {
00237       return HAL_TIMEOUT;
00238     }
00239   }
00240
00241   /* Configure the packet to send a short DCS command with 0 or 1 parameter */
00242   /* Update the DSI packet header with new information */
00243   hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
00244
00245   return HAL_OK;
00246 }
00247
00248 /* Exported functions --------------------------------------------------------*/
00249 /** @addtogroup DSI_Exported_Functions
00250   * @{
00251   */
00252
00253 /** @defgroup DSI_Group1 Initialization and Configuration functions
00254   *  @brief   Initialization and Configuration functions
00255   *
00256 @verbatim
00257  ===============================================================================
00258                 ##### Initialization and Configuration functions #####
00259  ===============================================================================
00260     [..]  This section provides functions allowing to:
00261       (+) Initialize and configure the DSI
00262       (+) De-initialize the DSI
00263
00264 @endverbatim
00265   * @{
00266   */
00267
00268 /**
00269   * @brief  Initializes the DSI according to the specified
00270   *         parameters in the DSI_InitTypeDef and create the associated handle.
00271   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00272   *               the configuration information for the DSI.
00273   * @param  PLLInit  pointer to a DSI_PLLInitTypeDef structure that contains
00274   *                  the PLL Clock structure definition for the DSI.
00275   * @retval HAL status
00276   */
00277 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
00278 {
00279   uint32_t tickstart;
00280   uint32_t unitIntervalx4;
00281   uint32_t tempIDF;
00282
00283   /* Check the DSI handle allocation */
00284   if (hdsi == NULL)
00285   {
00286     return HAL_ERROR;
00287   }
00288
00289   /* Check function parameters */
00290   assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
00291   assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
00292   assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
00293   assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
00294   assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
00295
00296 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00297   if (hdsi->State == HAL_DSI_STATE_RESET)
00298   {
00299     /* Reset the DSI callback to the legacy weak callbacks */
00300     hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
00301     hdsi->EndOfRefreshCallback  = HAL_DSI_EndOfRefreshCallback;  /* Legacy weak EndOfRefreshCallback  */
00302     hdsi->ErrorCallback         = HAL_DSI_ErrorCallback;         /* Legacy weak ErrorCallback         */
00303
00304     if (hdsi->MspInitCallback == NULL)
00305     {
00306       hdsi->MspInitCallback = HAL_DSI_MspInit;
00307     }
00308     /* Initialize the low level hardware */
00309     hdsi->MspInitCallback(hdsi);
00310   }
00311 #else
00312   if (hdsi->State == HAL_DSI_STATE_RESET)
00313   {
00314     /* Initialize the low level hardware */
00315     HAL_DSI_MspInit(hdsi);
00316   }
00317 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00318
00319   /* Change DSI peripheral state */
00320   hdsi->State = HAL_DSI_STATE_BUSY;
00321
00322   /**************** Turn on the regulator and enable the DSI PLL ****************/
00323
00324   /* Enable the regulator */
00325   __HAL_DSI_REG_ENABLE(hdsi);
00326
00327   /* Get tick */
00328   tickstart = HAL_GetTick();
00329
00330   /* Wait until the regulator is ready */
00331   while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
00332   {
00333     /* Check for the Timeout */
00334     if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
00335     {
00336       return HAL_TIMEOUT;
00337     }
00338   }
00339
00340   /* Set the PLL division factors */
00341   hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
00342   hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
00343
00344   /* Enable the DSI PLL */
00345   __HAL_DSI_PLL_ENABLE(hdsi);
00346
00347   /* Get tick */
00348   tickstart = HAL_GetTick();
00349
00350   /* Wait for the lock of the PLL */
00351   while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
00352   {
00353     /* Check for the Timeout */
00354     if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
00355     {
00356       return HAL_TIMEOUT;
00357     }
00358   }
00359
00360   /*************************** Set the PHY parameters ***************************/
00361
00362   /* D-PHY clock and digital enable*/
00363   hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
00364
00365   /* Clock lane configuration */
00366   hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
00367   hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
00368
00369   /* Configure the number of active data lanes */
00370   hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
00371   hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
00372
00373   /************************ Set the DSI clock parameters ************************/
00374
00375   /* Set the TX escape clock division factor */
00376   hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
00377   hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
00378
00379   /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
00380   /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */
00381   /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF)                    */
00382   tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
00383   unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
00384
00385   /* Set the bit period in high-speed mode */
00386   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
00387   hdsi->Instance->WPCR[0U] |= unitIntervalx4;
00388
00389   /****************************** Error management *****************************/
00390
00391   /* Disable all error interrupts and reset the Error Mask */
00392   hdsi->Instance->IER[0U] = 0U;
00393   hdsi->Instance->IER[1U] = 0U;
00394   hdsi->ErrorMsk = 0U;
00395
00396   /* Initialise the error code */
00397   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
00398
00399   /* Initialize the DSI state*/
00400   hdsi->State = HAL_DSI_STATE_READY;
00401
00402   return HAL_OK;
00403 }
00404
00405 /**
00406   * @brief  De-initializes the DSI peripheral registers to their default reset
00407   *         values.
00408   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00409   *               the configuration information for the DSI.
00410   * @retval HAL status
00411   */
00412 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
00413 {
00414   /* Check the DSI handle allocation */
00415   if (hdsi == NULL)
00416   {
00417     return HAL_ERROR;
00418   }
00419
00420   /* Change DSI peripheral state */
00421   hdsi->State = HAL_DSI_STATE_BUSY;
00422
00423   /* Disable the DSI wrapper */
00424   __HAL_DSI_WRAPPER_DISABLE(hdsi);
00425
00426   /* Disable the DSI host */
00427   __HAL_DSI_DISABLE(hdsi);
00428
00429   /* D-PHY clock and digital disable */
00430   hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
00431
00432   /* Turn off the DSI PLL */
00433   __HAL_DSI_PLL_DISABLE(hdsi);
00434
00435   /* Disable the regulator */
00436   __HAL_DSI_REG_DISABLE(hdsi);
00437
00438 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00439   if (hdsi->MspDeInitCallback == NULL)
00440   {
00441     hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
00442   }
00443   /* DeInit the low level hardware */
00444   hdsi->MspDeInitCallback(hdsi);
00445 #else
00446   /* DeInit the low level hardware */
00447   HAL_DSI_MspDeInit(hdsi);
00448 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00449
00450   /* Initialise the error code */
00451   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
00452
00453   /* Initialize the DSI state*/
00454   hdsi->State = HAL_DSI_STATE_RESET;
00455
00456   /* Release Lock */
00457   __HAL_UNLOCK(hdsi);
00458
00459   return HAL_OK;
00460 }
00461
00462 /**
00463   * @brief  Enable the error monitor flags
00464   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00465   *               the configuration information for the DSI.
00466   * @param  ActiveErrors  indicates which error interrupts will be enabled.
00467   *                      This parameter can be any combination of @arg DSI_Error_Data_Type.
00468   * @retval HAL status
00469   */
00470 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
00471 {
00472   /* Process locked */
00473   __HAL_LOCK(hdsi);
00474
00475   hdsi->Instance->IER[0U] = 0U;
00476   hdsi->Instance->IER[1U] = 0U;
00477
00478   /* Store active errors to the handle */
00479   hdsi->ErrorMsk = ActiveErrors;
00480
00481   if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
00482   {
00483     /* Enable the interrupt generation on selected errors */
00484     hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
00485   }
00486
00487   if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
00488   {
00489     /* Enable the interrupt generation on selected errors */
00490     hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
00491   }
00492
00493   if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
00494   {
00495     /* Enable the interrupt generation on selected errors */
00496     hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
00497   }
00498
00499   if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
00500   {
00501     /* Enable the interrupt generation on selected errors */
00502     hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
00503   }
00504
00505   if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
00506   {
00507     /* Enable the interrupt generation on selected errors */
00508     hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
00509   }
00510
00511   if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
00512   {
00513     /* Enable the interrupt generation on selected errors */
00514     hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
00515   }
00516
00517   if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
00518   {
00519     /* Enable the interrupt generation on selected errors */
00520     hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
00521   }
00522
00523   if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
00524   {
00525     /* Enable the interrupt generation on selected errors */
00526     hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
00527   }
00528
00529   if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
00530   {
00531     /* Enable the interrupt generation on selected errors */
00532     hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
00533   }
00534
00535   if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
00536   {
00537     /* Enable the interrupt generation on selected errors */
00538     hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
00539   }
00540
00541   /* Process Unlocked */
00542   __HAL_UNLOCK(hdsi);
00543
00544   return HAL_OK;
00545 }
00546
00547 /**
00548   * @brief  Initializes the DSI MSP.
00549   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00550   *               the configuration information for the DSI.
00551   * @retval None
00552   */
00553 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
00554 {
00555   /* Prevent unused argument(s) compilation warning */
00556   UNUSED(hdsi);
00557   /* NOTE : This function Should not be modified, when the callback is needed,
00558             the HAL_DSI_MspInit could be implemented in the user file
00559    */
00560 }
00561
00562 /**
00563   * @brief  De-initializes the DSI MSP.
00564   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00565   *               the configuration information for the DSI.
00566   * @retval None
00567   */
00568 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
00569 {
00570   /* Prevent unused argument(s) compilation warning */
00571   UNUSED(hdsi);
00572   /* NOTE : This function Should not be modified, when the callback is needed,
00573             the HAL_DSI_MspDeInit could be implemented in the user file
00574    */
00575 }
00576
00577 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00578 /**
00579   * @brief  Register a User DSI Callback
00580   *         To be used instead of the weak predefined callback
00581   * @param hdsi dsi handle
00582   * @param CallbackID ID of the callback to be registered
00583   *        This parameter can be one of the following values:
00584   *          @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
00585   *          @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
00586   *          @arg HAL_DSI_ERROR_CB_ID Error Callback ID
00587   *          @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
00588   *          @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
00589   * @param pCallback pointer to the Callback function
00590   * @retval status
00591   */
00592 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
00593                                            pDSI_CallbackTypeDef pCallback)
00594 {
00595   HAL_StatusTypeDef status = HAL_OK;
00596
00597   if (pCallback == NULL)
00598   {
00599     /* Update the error code */
00600     hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00601
00602     return HAL_ERROR;
00603   }
00604   /* Process locked */
00605   __HAL_LOCK(hdsi);
00606
00607   if (hdsi->State == HAL_DSI_STATE_READY)
00608   {
00609     switch (CallbackID)
00610     {
00611       case HAL_DSI_TEARING_EFFECT_CB_ID :
00612         hdsi->TearingEffectCallback = pCallback;
00613         break;
00614
00615       case HAL_DSI_ENDOF_REFRESH_CB_ID :
00616         hdsi->EndOfRefreshCallback = pCallback;
00617         break;
00618
00619       case HAL_DSI_ERROR_CB_ID :
00620         hdsi->ErrorCallback = pCallback;
00621         break;
00622
00623       case HAL_DSI_MSPINIT_CB_ID :
00624         hdsi->MspInitCallback = pCallback;
00625         break;
00626
00627       case HAL_DSI_MSPDEINIT_CB_ID :
00628         hdsi->MspDeInitCallback = pCallback;
00629         break;
00630
00631       default :
00632         /* Update the error code */
00633         hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00634         /* Return error status */
00635         status =  HAL_ERROR;
00636         break;
00637     }
00638   }
00639   else if (hdsi->State == HAL_DSI_STATE_RESET)
00640   {
00641     switch (CallbackID)
00642     {
00643       case HAL_DSI_MSPINIT_CB_ID :
00644         hdsi->MspInitCallback = pCallback;
00645         break;
00646
00647       case HAL_DSI_MSPDEINIT_CB_ID :
00648         hdsi->MspDeInitCallback = pCallback;
00649         break;
00650
00651       default :
00652         /* Update the error code */
00653         hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00654         /* Return error status */
00655         status =  HAL_ERROR;
00656         break;
00657     }
00658   }
00659   else
00660   {
00661     /* Update the error code */
00662     hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00663     /* Return error status */
00664     status =  HAL_ERROR;
00665   }
00666
00667   /* Release Lock */
00668   __HAL_UNLOCK(hdsi);
00669
00670   return status;
00671 }
00672
00673 /**
00674   * @brief  Unregister a DSI Callback
00675   *         DSI callabck is redirected to the weak predefined callback
00676   * @param hdsi dsi handle
00677   * @param CallbackID ID of the callback to be unregistered
00678   *        This parameter can be one of the following values:
00679   *          @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
00680   *          @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
00681   *          @arg HAL_DSI_ERROR_CB_ID Error Callback ID
00682   *          @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
00683   *          @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
00684   * @retval status
00685   */
00686 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
00687 {
00688   HAL_StatusTypeDef status = HAL_OK;
00689
00690   /* Process locked */
00691   __HAL_LOCK(hdsi);
00692
00693   if (hdsi->State == HAL_DSI_STATE_READY)
00694   {
00695     switch (CallbackID)
00696     {
00697       case HAL_DSI_TEARING_EFFECT_CB_ID :
00698         hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
00699         break;
00700
00701       case HAL_DSI_ENDOF_REFRESH_CB_ID :
00702         hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback;   /* Legacy weak EndOfRefreshCallback  */
00703         break;
00704
00705       case HAL_DSI_ERROR_CB_ID :
00706         hdsi->ErrorCallback        = HAL_DSI_ErrorCallback;          /* Legacy weak ErrorCallback        */
00707         break;
00708
00709       case HAL_DSI_MSPINIT_CB_ID :
00710         hdsi->MspInitCallback = HAL_DSI_MspInit;                     /* Legcay weak MspInit Callback     */
00711         break;
00712
00713       case HAL_DSI_MSPDEINIT_CB_ID :
00714         hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;                 /* Legcay weak MspDeInit Callback   */
00715         break;
00716
00717       default :
00718         /* Update the error code */
00719         hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00720         /* Return error status */
00721         status =  HAL_ERROR;
00722         break;
00723     }
00724   }
00725   else if (hdsi->State == HAL_DSI_STATE_RESET)
00726   {
00727     switch (CallbackID)
00728     {
00729       case HAL_DSI_MSPINIT_CB_ID :
00730         hdsi->MspInitCallback = HAL_DSI_MspInit;                  /* Legcay weak MspInit Callback   */
00731         break;
00732
00733       case HAL_DSI_MSPDEINIT_CB_ID :
00734         hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;              /* Legcay weak MspDeInit Callback */
00735         break;
00736
00737       default :
00738         /* Update the error code */
00739         hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00740         /* Return error status */
00741         status =  HAL_ERROR;
00742         break;
00743     }
00744   }
00745   else
00746   {
00747     /* Update the error code */
00748     hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
00749     /* Return error status */
00750     status =  HAL_ERROR;
00751   }
00752
00753   /* Release Lock */
00754   __HAL_UNLOCK(hdsi);
00755
00756   return status;
00757 }
00758 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00759
00760 /**
00761   * @}
00762   */
00763
00764 /** @defgroup DSI_Group2 IO operation functions
00765   *  @brief    IO operation functions
00766   *
00767 @verbatim
00768  ===============================================================================
00769                       #####  IO operation functions  #####
00770  ===============================================================================
00771     [..]  This section provides function allowing to:
00772       (+) Handle DSI interrupt request
00773
00774 @endverbatim
00775   * @{
00776   */
00777 /**
00778   * @brief  Handles DSI interrupt request.
00779   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00780   *               the configuration information for the DSI.
00781   * @retval HAL status
00782   */
00783 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
00784 {
00785   uint32_t ErrorStatus0, ErrorStatus1;
00786
00787   /* Tearing Effect Interrupt management ***************************************/
00788   if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
00789   {
00790     if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
00791     {
00792       /* Clear the Tearing Effect Interrupt Flag */
00793       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
00794
00795       /* Tearing Effect Callback */
00796 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00797       /*Call registered Tearing Effect callback */
00798       hdsi->TearingEffectCallback(hdsi);
00799 #else
00800       /*Call legacy Tearing Effect callback*/
00801       HAL_DSI_TearingEffectCallback(hdsi);
00802 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00803     }
00804   }
00805
00806   /* End of Refresh Interrupt management ***************************************/
00807   if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
00808   {
00809     if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
00810     {
00811       /* Clear the End of Refresh Interrupt Flag */
00812       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
00813
00814       /* End of Refresh Callback */
00815 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00816       /*Call registered End of refresh callback */
00817       hdsi->EndOfRefreshCallback(hdsi);
00818 #else
00819       /*Call Legacy End of refresh callback */
00820       HAL_DSI_EndOfRefreshCallback(hdsi);
00821 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00822     }
00823   }
00824
00825   /* Error Interrupts management ***********************************************/
00826   if (hdsi->ErrorMsk != 0U)
00827   {
00828     ErrorStatus0 = hdsi->Instance->ISR[0U];
00829     ErrorStatus0 &= hdsi->Instance->IER[0U];
00830     ErrorStatus1 = hdsi->Instance->ISR[1U];
00831     ErrorStatus1 &= hdsi->Instance->IER[1U];
00832
00833     if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
00834     {
00835       hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
00836     }
00837
00838     if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
00839     {
00840       hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
00841     }
00842
00843     if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
00844     {
00845       hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
00846     }
00847
00848     if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
00849     {
00850       hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
00851     }
00852
00853     if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
00854     {
00855       hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
00856     }
00857
00858     if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
00859     {
00860       hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
00861     }
00862
00863     if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
00864     {
00865       hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
00866     }
00867
00868     if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
00869     {
00870       hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
00871     }
00872
00873     if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
00874     {
00875       hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
00876     }
00877
00878     if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
00879     {
00880       hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
00881     }
00882
00883     /* Check only selected errors */
00884     if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
00885     {
00886       /* DSI error interrupt callback */
00887 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00888       /*Call registered Error callback */
00889       hdsi->ErrorCallback(hdsi);
00890 #else
00891       /*Call Legacy Error callback */
00892       HAL_DSI_ErrorCallback(hdsi);
00893 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00894     }
00895   }
00896 }
00897
00898 /**
00899   * @brief  Tearing Effect DSI callback.
00900   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00901   *               the configuration information for the DSI.
00902   * @retval None
00903   */
00904 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
00905 {
00906   /* Prevent unused argument(s) compilation warning */
00907   UNUSED(hdsi);
00908   /* NOTE : This function Should not be modified, when the callback is needed,
00909             the HAL_DSI_TearingEffectCallback could be implemented in the user file
00910    */
00911 }
00912
00913 /**
00914   * @brief  End of Refresh DSI callback.
00915   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00916   *               the configuration information for the DSI.
00917   * @retval None
00918   */
00919 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
00920 {
00921   /* Prevent unused argument(s) compilation warning */
00922   UNUSED(hdsi);
00923   /* NOTE : This function Should not be modified, when the callback is needed,
00924             the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
00925    */
00926 }
00927
00928 /**
00929   * @brief  Operation Error DSI callback.
00930   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00931   *               the configuration information for the DSI.
00932   * @retval None
00933   */
00934 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
00935 {
00936   /* Prevent unused argument(s) compilation warning */
00937   UNUSED(hdsi);
00938   /* NOTE : This function Should not be modified, when the callback is needed,
00939             the HAL_DSI_ErrorCallback could be implemented in the user file
00940    */
00941 }
00942
00943 /**
00944   * @}
00945   */
00946
00947 /** @defgroup DSI_Group3 Peripheral Control functions
00948   *  @brief    Peripheral Control functions
00949   *
00950 @verbatim
00951  ===============================================================================
00952                     ##### Peripheral Control functions #####
00953  ===============================================================================
00954     [..]  This section provides functions allowing to:
00955       (+) Configure the Generic interface read-back Virtual Channel ID
00956       (+) Select video mode and configure the corresponding parameters
00957       (+) Configure command transmission mode: High-speed or Low-power
00958       (+) Configure the flow control
00959       (+) Configure the DSI PHY timer
00960       (+) Configure the DSI HOST timeout
00961       (+) Configure the DSI HOST timeout
00962       (+) Start/Stop the DSI module
00963       (+) Refresh the display in command mode
00964       (+) Controls the display color mode in Video mode
00965       (+) Control the display shutdown in Video mode
00966       (+) write short DCS or short Generic command
00967       (+) write long DCS or long Generic command
00968       (+) Read command (DCS or generic)
00969       (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
00970       (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
00971       (+) Start/Stop test pattern generation
00972       (+) Slew-Rate And Delay Tuning
00973       (+) Low-Power Reception Filter Tuning
00974       (+) Activate an additional current path on all lanes to meet the SDDTx parameter
00975       (+) Custom lane pins configuration
00976       (+) Set custom timing for the PHY
00977       (+) Force the Clock/Data Lane in TX Stop Mode
00978       (+) Force LP Receiver in Low-Power Mode
00979       (+) Force Data Lanes in RX Mode after a BTA
00980       (+) Enable a pull-down on the lanes to prevent from floating states when unused
00981       (+) Switch off the contention detection on data lanes
00982
00983 @endverbatim
00984   * @{
00985   */
00986
00987 /**
00988   * @brief  Configure the Generic interface read-back Virtual Channel ID.
00989   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
00990   *               the configuration information for the DSI.
00991   * @param  VirtualChannelID  Virtual channel ID
00992   * @retval HAL status
00993   */
00994 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
00995 {
00996   /* Process locked */
00997   __HAL_LOCK(hdsi);
00998
00999   /* Update the GVCID register */
01000   hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
01001   hdsi->Instance->GVCIDR |= VirtualChannelID;
01002
01003   /* Process unlocked */
01004   __HAL_UNLOCK(hdsi);
01005
01006   return HAL_OK;
01007 }
01008
01009 /**
01010   * @brief  Select video mode and configure the corresponding parameters
01011   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01012   *               the configuration information for the DSI.
01013   * @param  VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
01014   *                the DSI video mode configuration parameters
01015   * @retval HAL status
01016   */
01017 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
01018 {
01019   /* Process locked */
01020   __HAL_LOCK(hdsi);
01021
01022   /* Check the parameters */
01023   assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
01024   assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
01025   assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
01026   assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
01027   assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
01028   assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
01029   assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
01030   assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
01031   assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
01032   assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
01033   assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
01034   assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
01035   assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
01036   /* Check the LooselyPacked variant only in 18-bit mode */
01037   if (VidCfg->ColorCoding == DSI_RGB666)
01038   {
01039     assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
01040   }
01041
01042   /* Select video mode by resetting CMDM and DSIM bits */
01043   hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
01044   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
01045
01046   /* Configure the video mode transmission type */
01047   hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
01048   hdsi->Instance->VMCR |= VidCfg->Mode;
01049
01050   /* Configure the video packet size */
01051   hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
01052   hdsi->Instance->VPCR |= VidCfg->PacketSize;
01053
01054   /* Set the chunks number to be transmitted through the DSI link */
01055   hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
01056   hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
01057
01058   /* Set the size of the null packet */
01059   hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
01060   hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
01061
01062   /* Select the virtual channel for the LTDC interface traffic */
01063   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
01064   hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
01065
01066   /* Configure the polarity of control signals */
01067   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
01068   hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
01069
01070   /* Select the color coding for the host */
01071   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
01072   hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
01073
01074   /* Select the color coding for the wrapper */
01075   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
01076   hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
01077
01078   /* Enable/disable the loosely packed variant to 18-bit configuration */
01079   if (VidCfg->ColorCoding == DSI_RGB666)
01080   {
01081     hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
01082     hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
01083   }
01084
01085   /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
01086   hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
01087   hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
01088
01089   /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
01090   hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
01091   hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
01092
01093   /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
01094   hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
01095   hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
01096
01097   /* Set the Vertical Synchronization Active (VSA) */
01098   hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
01099   hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
01100
01101   /* Set the Vertical Back Porch (VBP)*/
01102   hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
01103   hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
01104
01105   /* Set the Vertical Front Porch (VFP)*/
01106   hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
01107   hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
01108
01109   /* Set the Vertical Active period*/
01110   hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
01111   hdsi->Instance->VVACR |= VidCfg->VerticalActive;
01112
01113   /* Configure the command transmission mode */
01114   hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
01115   hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
01116
01117   /* Low power largest packet size */
01118   hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
01119   hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
01120
01121   /* Low power VACT largest packet size */
01122   hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
01123   hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
01124
01125   /* Enable LP transition in HFP period */
01126   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
01127   hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
01128
01129   /* Enable LP transition in HBP period */
01130   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
01131   hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
01132
01133   /* Enable LP transition in VACT period */
01134   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
01135   hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
01136
01137   /* Enable LP transition in VFP period */
01138   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
01139   hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
01140
01141   /* Enable LP transition in VBP period */
01142   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
01143   hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
01144
01145   /* Enable LP transition in vertical sync period */
01146   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
01147   hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
01148
01149   /* Enable the request for an acknowledge response at the end of a frame */
01150   hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
01151   hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
01152
01153   /* Process unlocked */
01154   __HAL_UNLOCK(hdsi);
01155
01156   return HAL_OK;
01157 }
01158
01159 /**
01160   * @brief  Select adapted command mode and configure the corresponding parameters
01161   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01162   *               the configuration information for the DSI.
01163   * @param  CmdCfg  pointer to a DSI_CmdCfgTypeDef structure that contains
01164   *                 the DSI command mode configuration parameters
01165   * @retval HAL status
01166   */
01167 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
01168 {
01169   /* Process locked */
01170   __HAL_LOCK(hdsi);
01171
01172   /* Check the parameters */
01173   assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
01174   assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
01175   assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
01176   assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
01177   assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
01178   assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
01179   assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
01180   assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
01181   assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
01182
01183   /* Select command mode by setting CMDM and DSIM bits */
01184   hdsi->Instance->MCR |= DSI_MCR_CMDM;
01185   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
01186   hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
01187
01188   /* Select the virtual channel for the LTDC interface traffic */
01189   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
01190   hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
01191
01192   /* Configure the polarity of control signals */
01193   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
01194   hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
01195
01196   /* Select the color coding for the host */
01197   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
01198   hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
01199
01200   /* Select the color coding for the wrapper */
01201   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
01202   hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
01203
01204   /* Configure the maximum allowed size for write memory command */
01205   hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
01206   hdsi->Instance->LCCR |= CmdCfg->CommandSize;
01207
01208   /* Configure the tearing effect source and polarity and select the refresh mode */
01209   hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
01210   hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
01211                             CmdCfg->VSyncPol);
01212
01213   /* Configure the tearing effect acknowledge request */
01214   hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
01215   hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
01216
01217   /* Enable the Tearing Effect interrupt */
01218   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
01219
01220   /* Enable the End of Refresh interrupt */
01221   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
01222
01223   /* Process unlocked */
01224   __HAL_UNLOCK(hdsi);
01225
01226   return HAL_OK;
01227 }
01228
01229 /**
01230   * @brief  Configure command transmission mode: High-speed or Low-power
01231   *         and enable/disable acknowledge request after packet transmission
01232   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01233   *               the configuration information for the DSI.
01234   * @param  LPCmd  pointer to a DSI_LPCmdTypeDef structure that contains
01235   *                the DSI command transmission mode configuration parameters
01236   * @retval HAL status
01237   */
01238 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
01239 {
01240   /* Process locked */
01241   __HAL_LOCK(hdsi);
01242
01243   assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
01244   assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
01245   assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
01246   assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
01247   assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
01248   assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
01249   assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
01250   assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
01251   assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
01252   assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
01253   assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
01254   assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
01255   assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
01256
01257   /* Select High-speed or Low-power for command transmission */
01258   hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
01259                             DSI_CMCR_GSW1TX | \
01260                             DSI_CMCR_GSW2TX | \
01261                             DSI_CMCR_GSR0TX | \
01262                             DSI_CMCR_GSR1TX | \
01263                             DSI_CMCR_GSR2TX | \
01264                             DSI_CMCR_GLWTX  | \
01265                             DSI_CMCR_DSW0TX | \
01266                             DSI_CMCR_DSW1TX | \
01267                             DSI_CMCR_DSR0TX | \
01268                             DSI_CMCR_DLWTX  | \
01269                             DSI_CMCR_MRDPS);
01270   hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  | \
01271                            LPCmd->LPGenShortWriteOneP | \
01272                            LPCmd->LPGenShortWriteTwoP | \
01273                            LPCmd->LPGenShortReadNoP   | \
01274                            LPCmd->LPGenShortReadOneP  | \
01275                            LPCmd->LPGenShortReadTwoP  | \
01276                            LPCmd->LPGenLongWrite      | \
01277                            LPCmd->LPDcsShortWriteNoP  | \
01278                            LPCmd->LPDcsShortWriteOneP | \
01279                            LPCmd->LPDcsShortReadNoP   | \
01280                            LPCmd->LPDcsLongWrite      | \
01281                            LPCmd->LPMaxReadPacket);
01282
01283   /* Configure the acknowledge request after each packet transmission */
01284   hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
01285   hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
01286
01287   /* Process unlocked */
01288   __HAL_UNLOCK(hdsi);
01289
01290   return HAL_OK;
01291 }
01292
01293 /**
01294   * @brief  Configure the flow control parameters
01295   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01296   *               the configuration information for the DSI.
01297   * @param  FlowControl  flow control feature(s) to be enabled.
01298   *                      This parameter can be any combination of @arg DSI_FlowControl.
01299   * @retval HAL status
01300   */
01301 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
01302 {
01303   /* Process locked */
01304   __HAL_LOCK(hdsi);
01305
01306   /* Check the parameters */
01307   assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
01308
01309   /* Set the DSI Host Protocol Configuration Register */
01310   hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
01311   hdsi->Instance->PCR |= FlowControl;
01312
01313   /* Process unlocked */
01314   __HAL_UNLOCK(hdsi);
01315
01316   return HAL_OK;
01317 }
01318
01319 /**
01320   * @brief  Configure the DSI PHY timer parameters
01321   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01322   *               the configuration information for the DSI.
01323   * @param  PhyTimers  DSI_PHY_TimerTypeDef structure that contains
01324   *                    the DSI PHY timing parameters
01325   * @retval HAL status
01326   */
01327 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
01328 {
01329   uint32_t maxTime;
01330   /* Process locked */
01331   __HAL_LOCK(hdsi);
01332
01333   maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
01334             PhyTimers->ClockLaneHS2LPTime;
01335
01336   /* Clock lane timer configuration */
01337
01338   /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
01339      High-Speed transmission.
01340      To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
01341      to Low-Power and from Low-Power to High-Speed.
01342      This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
01343      But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
01344
01345      Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
01346     */
01347   hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
01348   hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
01349
01350   /* Data lane timer configuration */
01351   hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
01352   hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
01353                               PhyTimers->DataLaneHS2LPTime) << 24U));
01354
01355   /* Configure the wait period to request HS transmission after a stop state */
01356   hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
01357   hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
01358
01359   /* Process unlocked */
01360   __HAL_UNLOCK(hdsi);
01361
01362   return HAL_OK;
01363 }
01364
01365 /**
01366   * @brief  Configure the DSI HOST timeout parameters
01367   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01368   *               the configuration information for the DSI.
01369   * @param  HostTimeouts  DSI_HOST_TimeoutTypeDef structure that contains
01370   *                       the DSI host timeout parameters
01371   * @retval HAL status
01372   */
01373 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
01374 {
01375   /* Process locked */
01376   __HAL_LOCK(hdsi);
01377
01378   /* Set the timeout clock division factor */
01379   hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
01380   hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
01381
01382   /* High-speed transmission timeout */
01383   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
01384   hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
01385
01386   /* Low-power reception timeout */
01387   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
01388   hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
01389
01390   /* High-speed read timeout */
01391   hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
01392   hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
01393
01394   /* Low-power read timeout */
01395   hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
01396   hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
01397
01398   /* High-speed write timeout */
01399   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
01400   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
01401
01402   /* High-speed write presp mode */
01403   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
01404   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
01405
01406   /* Low-speed write timeout */
01407   hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
01408   hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
01409
01410   /* BTA timeout */
01411   hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
01412   hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
01413
01414   /* Process unlocked */
01415   __HAL_UNLOCK(hdsi);
01416
01417   return HAL_OK;
01418 }
01419
01420 /**
01421   * @brief  Start the DSI module
01422   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01423   *               the configuration information for the DSI.
01424   * @retval HAL status
01425   */
01426 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
01427 {
01428   /* Process locked */
01429   __HAL_LOCK(hdsi);
01430
01431   /* Enable the DSI host */
01432   __HAL_DSI_ENABLE(hdsi);
01433
01434   /* Enable the DSI wrapper */
01435   __HAL_DSI_WRAPPER_ENABLE(hdsi);
01436
01437   /* Process unlocked */
01438   __HAL_UNLOCK(hdsi);
01439
01440   return HAL_OK;
01441 }
01442
01443 /**
01444   * @brief  Stop the DSI module
01445   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01446   *               the configuration information for the DSI.
01447   * @retval HAL status
01448   */
01449 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
01450 {
01451   /* Process locked */
01452   __HAL_LOCK(hdsi);
01453
01454   /* Disable the DSI host */
01455   __HAL_DSI_DISABLE(hdsi);
01456
01457   /* Disable the DSI wrapper */
01458   __HAL_DSI_WRAPPER_DISABLE(hdsi);
01459
01460   /* Process unlocked */
01461   __HAL_UNLOCK(hdsi);
01462
01463   return HAL_OK;
01464 }
01465
01466 /**
01467   * @brief  Refresh the display in command mode
01468   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01469   *               the configuration information for the DSI.
01470   * @retval HAL status
01471   */
01472 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
01473 {
01474   /* Process locked */
01475   __HAL_LOCK(hdsi);
01476
01477   /* Update the display */
01478   hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
01479
01480   /* Process unlocked */
01481   __HAL_UNLOCK(hdsi);
01482
01483   return HAL_OK;
01484 }
01485
01486 /**
01487   * @brief  Controls the display color mode in Video mode
01488   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01489   *               the configuration information for the DSI.
01490   * @param  ColorMode  Color mode (full or 8-colors).
01491   *                    This parameter can be any value of @arg DSI_Color_Mode
01492   * @retval HAL status
01493   */
01494 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
01495 {
01496   /* Process locked */
01497   __HAL_LOCK(hdsi);
01498
01499   /* Check the parameters */
01500   assert_param(IS_DSI_COLOR_MODE(ColorMode));
01501
01502   /* Update the display color mode */
01503   hdsi->Instance->WCR &= ~DSI_WCR_COLM;
01504   hdsi->Instance->WCR |= ColorMode;
01505
01506   /* Process unlocked */
01507   __HAL_UNLOCK(hdsi);
01508
01509   return HAL_OK;
01510 }
01511
01512 /**
01513   * @brief  Control the display shutdown in Video mode
01514   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01515   *               the configuration information for the DSI.
01516   * @param  Shutdown  Shut-down (Display-ON or Display-OFF).
01517   *                   This parameter can be any value of @arg DSI_ShutDown
01518   * @retval HAL status
01519   */
01520 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
01521 {
01522   /* Process locked */
01523   __HAL_LOCK(hdsi);
01524
01525   /* Check the parameters */
01526   assert_param(IS_DSI_SHUT_DOWN(Shutdown));
01527
01528   /* Update the display Shutdown */
01529   hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
01530   hdsi->Instance->WCR |= Shutdown;
01531
01532   /* Process unlocked */
01533   __HAL_UNLOCK(hdsi);
01534
01535   return HAL_OK;
01536 }
01537
01538 /**
01539   * @brief  write short DCS or short Generic command
01540   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01541   *               the configuration information for the DSI.
01542   * @param  ChannelID  Virtual channel ID.
01543   * @param  Mode  DSI short packet data type.
01544   *               This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
01545   * @param  Param1  DSC command or first generic parameter.
01546   *                 This parameter can be any value of @arg DSI_DCS_Command or a
01547   *                 generic command code.
01548   * @param  Param2  DSC parameter or second generic parameter.
01549   * @retval HAL status
01550   */
01551 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
01552                                      uint32_t ChannelID,
01553                                      uint32_t Mode,
01554                                      uint32_t Param1,
01555                                      uint32_t Param2)
01556 {
01557   HAL_StatusTypeDef status;
01558   /* Check the parameters */
01559   assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
01560
01561   /* Process locked */
01562   __HAL_LOCK(hdsi);
01563
01564    status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
01565
01566   /* Process unlocked */
01567   __HAL_UNLOCK(hdsi);
01568
01569   return status;
01570 }
01571
01572 /**
01573   * @brief  write long DCS or long Generic command
01574   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01575   *               the configuration information for the DSI.
01576   * @param  ChannelID  Virtual channel ID.
01577   * @param  Mode  DSI long packet data type.
01578   *               This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
01579   * @param  NbParams  Number of parameters.
01580   * @param  Param1  DSC command or first generic parameter.
01581   *                 This parameter can be any value of @arg DSI_DCS_Command or a
01582   *                 generic command code
01583   * @param  ParametersTable  Pointer to parameter values table.
01584   * @retval HAL status
01585   */
01586 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
01587                                     uint32_t ChannelID,
01588                                     uint32_t Mode,
01589                                     uint32_t NbParams,
01590                                     uint32_t Param1,
01591                                     uint8_t *ParametersTable)
01592 {
01593   uint32_t uicounter, nbBytes, count;
01594   uint32_t tickstart;
01595   uint32_t fifoword;
01596   uint8_t *pparams = ParametersTable;
01597
01598   /* Process locked */
01599   __HAL_LOCK(hdsi);
01600
01601   /* Check the parameters */
01602   assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
01603
01604   /* Get tick */
01605   tickstart = HAL_GetTick();
01606
01607   /* Wait for Command FIFO Empty */
01608   while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
01609   {
01610     /* Check for the Timeout */
01611     if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01612     {
01613       /* Process Unlocked */
01614       __HAL_UNLOCK(hdsi);
01615
01616       return HAL_TIMEOUT;
01617     }
01618   }
01619
01620   /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
01621   fifoword = Param1;
01622   nbBytes = (NbParams < 3U) ? NbParams : 3U;
01623
01624   for (count = 0U; count < nbBytes; count++)
01625   {
01626     fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
01627   }
01628   hdsi->Instance->GPDR = fifoword;
01629
01630   uicounter = NbParams - nbBytes;
01631   pparams += nbBytes;
01632   /* Set the Next parameters on the write FIFO command*/
01633   while (uicounter != 0U)
01634   {
01635     nbBytes = (uicounter < 4U) ? uicounter : 4U;
01636     fifoword = 0U;
01637     for (count = 0U; count < nbBytes; count++)
01638     {
01639       fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
01640     }
01641     hdsi->Instance->GPDR = fifoword;
01642
01643     uicounter -= nbBytes;
01644     pparams += nbBytes;
01645   }
01646
01647   /* Configure the packet to send a long DCS command */
01648   DSI_ConfigPacketHeader(hdsi->Instance,
01649                          ChannelID,
01650                          Mode,
01651                          ((NbParams + 1U) & 0x00FFU),
01652                          (((NbParams + 1U) & 0xFF00U) >> 8U));
01653
01654   /* Process unlocked */
01655   __HAL_UNLOCK(hdsi);
01656
01657   return HAL_OK;
01658 }
01659
01660 /**
01661   * @brief  Read command (DCS or generic)
01662   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01663   *               the configuration information for the DSI.
01664   * @param  ChannelNbr  Virtual channel ID
01665   * @param  Array pointer to a buffer to store the payload of a read back operation.
01666   * @param  Size  Data size to be read (in byte).
01667   * @param  Mode  DSI read packet data type.
01668   *               This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
01669   * @param  DCSCmd  DCS get/read command.
01670   * @param  ParametersTable  Pointer to parameter values table.
01671   * @retval HAL status
01672   */
01673 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
01674                                uint32_t ChannelNbr,
01675                                uint8_t *Array,
01676                                uint32_t Size,
01677                                uint32_t Mode,
01678                                uint32_t DCSCmd,
01679                                uint8_t *ParametersTable)
01680 {
01681   uint32_t tickstart;
01682   uint8_t *pdata = Array;
01683   uint32_t datasize = Size;
01684   uint32_t fifoword;
01685   uint32_t nbbytes;
01686   uint32_t count;
01687
01688   /* Process locked */
01689   __HAL_LOCK(hdsi);
01690
01691   /* Check the parameters */
01692   assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
01693
01694   if (datasize > 2U)
01695   {
01696     /* set max return packet size */
01697     if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
01698                            (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
01699     {
01700       /* Process Unlocked */
01701       __HAL_UNLOCK(hdsi);
01702
01703       return HAL_ERROR;
01704     }
01705   }
01706
01707   /* Configure the packet to read command */
01708   if (Mode == DSI_DCS_SHORT_PKT_READ)
01709   {
01710     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
01711   }
01712   else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
01713   {
01714     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
01715   }
01716   else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
01717   {
01718     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
01719   }
01720   else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
01721   {
01722     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
01723   }
01724   else
01725   {
01726     /* Process Unlocked */
01727     __HAL_UNLOCK(hdsi);
01728
01729     return HAL_ERROR;
01730   }
01731
01732   /* Get tick */
01733   tickstart = HAL_GetTick();
01734
01735   /* If DSI fifo is not empty, read requested bytes */
01736   while (((int32_t)(datasize)) > 0)
01737   {
01738     if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
01739     {
01740       fifoword = hdsi->Instance->GPDR;
01741       nbbytes = (datasize < 4U) ? datasize : 4U;
01742
01743       for (count = 0U; count < nbbytes; count++)
01744       {
01745         *pdata = (uint8_t)(fifoword >> (8U * count));
01746         pdata++;
01747         datasize--;
01748       }
01749     }
01750
01751     /* Check for the Timeout */
01752     if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01753     {
01754       /* Process Unlocked */
01755       __HAL_UNLOCK(hdsi);
01756
01757       return HAL_TIMEOUT;
01758     }
01759   }
01760
01761   /* Process unlocked */
01762   __HAL_UNLOCK(hdsi);
01763
01764   return HAL_OK;
01765 }
01766
01767 /**
01768   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
01769   *         (only data lanes are in ULPM)
01770   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01771   *               the configuration information for the DSI.
01772   * @retval HAL status
01773   */
01774 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
01775 {
01776   uint32_t tickstart;
01777
01778   /* Process locked */
01779   __HAL_LOCK(hdsi);
01780
01781   /* ULPS Request on Data Lanes */
01782   hdsi->Instance->PUCR |= DSI_PUCR_URDL;
01783
01784   /* Get tick */
01785   tickstart = HAL_GetTick();
01786
01787   /* Wait until the D-PHY active lanes enter into ULPM */
01788   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01789   {
01790     while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
01791     {
01792       /* Check for the Timeout */
01793       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01794       {
01795         /* Process Unlocked */
01796         __HAL_UNLOCK(hdsi);
01797
01798         return HAL_TIMEOUT;
01799       }
01800     }
01801   }
01802   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01803   {
01804     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
01805     {
01806       /* Check for the Timeout */
01807       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01808       {
01809         /* Process Unlocked */
01810         __HAL_UNLOCK(hdsi);
01811
01812         return HAL_TIMEOUT;
01813       }
01814     }
01815   }
01816   else
01817   {
01818     /* Process unlocked */
01819     __HAL_UNLOCK(hdsi);
01820
01821     return HAL_ERROR;
01822   }
01823
01824   /* Process unlocked */
01825   __HAL_UNLOCK(hdsi);
01826
01827   return HAL_OK;
01828 }
01829
01830 /**
01831   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
01832   *         (only data lanes are in ULPM)
01833   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01834   *               the configuration information for the DSI.
01835   * @retval HAL status
01836   */
01837 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
01838 {
01839   uint32_t tickstart;
01840
01841   /* Process locked */
01842   __HAL_LOCK(hdsi);
01843
01844   /* Exit ULPS on Data Lanes */
01845   hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
01846
01847   /* Get tick */
01848   tickstart = HAL_GetTick();
01849
01850   /* Wait until all active lanes exit ULPM */
01851   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01852   {
01853     while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
01854     {
01855       /* Check for the Timeout */
01856       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01857       {
01858         /* Process Unlocked */
01859         __HAL_UNLOCK(hdsi);
01860
01861         return HAL_TIMEOUT;
01862       }
01863     }
01864   }
01865   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01866   {
01867     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
01868     {
01869       /* Check for the Timeout */
01870       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01871       {
01872         /* Process Unlocked */
01873         __HAL_UNLOCK(hdsi);
01874
01875         return HAL_TIMEOUT;
01876       }
01877     }
01878   }
01879   else
01880   {
01881     /* Process unlocked */
01882     __HAL_UNLOCK(hdsi);
01883
01884     return HAL_ERROR;
01885   }
01886
01887   /* wait for 1 ms*/
01888   HAL_Delay(1U);
01889
01890   /* De-assert the ULPM requests and the ULPM exit bits */
01891   hdsi->Instance->PUCR = 0U;
01892
01893   /* Process unlocked */
01894   __HAL_UNLOCK(hdsi);
01895
01896   return HAL_OK;
01897 }
01898
01899 /**
01900   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
01901   *         (both data and clock lanes are in ULPM)
01902   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01903   *               the configuration information for the DSI.
01904   * @retval HAL status
01905   */
01906 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
01907 {
01908   uint32_t tickstart;
01909
01910   /* Process locked */
01911   __HAL_LOCK(hdsi);
01912
01913   /* Clock lane configuration: no more HS request */
01914   hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
01915
01916   /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
01917   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLL2);
01918
01919   /* ULPS Request on Clock and Data Lanes */
01920   hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
01921
01922   /* Get tick */
01923   tickstart = HAL_GetTick();
01924
01925   /* Wait until all active lanes exit ULPM */
01926   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01927   {
01928     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
01929     {
01930       /* Check for the Timeout */
01931       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01932       {
01933         /* Process Unlocked */
01934         __HAL_UNLOCK(hdsi);
01935
01936         return HAL_TIMEOUT;
01937       }
01938     }
01939   }
01940   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01941   {
01942     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
01943     {
01944       /* Check for the Timeout */
01945       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01946       {
01947         /* Process Unlocked */
01948         __HAL_UNLOCK(hdsi);
01949
01950         return HAL_TIMEOUT;
01951       }
01952     }
01953   }
01954   else
01955   {
01956     /* Process unlocked */
01957     __HAL_UNLOCK(hdsi);
01958
01959     return HAL_ERROR;
01960   }
01961
01962   /* Turn off the DSI PLL */
01963   __HAL_DSI_PLL_DISABLE(hdsi);
01964
01965   /* Process unlocked */
01966   __HAL_UNLOCK(hdsi);
01967
01968   return HAL_OK;
01969 }
01970
01971 /**
01972   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
01973   *         (both data and clock lanes are in ULPM)
01974   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
01975   *               the configuration information for the DSI.
01976   * @retval HAL status
01977   */
01978 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
01979 {
01980   uint32_t tickstart;
01981
01982   /* Process locked */
01983   __HAL_LOCK(hdsi);
01984
01985   /* Turn on the DSI PLL */
01986   __HAL_DSI_PLL_ENABLE(hdsi);
01987
01988   /* Get tick */
01989   tickstart = HAL_GetTick();
01990
01991   /* Wait for the lock of the PLL */
01992   while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
01993   {
01994     /* Check for the Timeout */
01995     if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
01996     {
01997       /* Process Unlocked */
01998       __HAL_UNLOCK(hdsi);
01999
02000       return HAL_TIMEOUT;
02001     }
02002   }
02003
02004   /* Exit ULPS on Clock and Data Lanes */
02005   hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
02006
02007   /* Get tick */
02008   tickstart = HAL_GetTick();
02009
02010   /* Wait until all active lanes exit ULPM */
02011   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
02012   {
02013     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
02014     {
02015       /* Check for the Timeout */
02016       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
02017       {
02018         /* Process Unlocked */
02019         __HAL_UNLOCK(hdsi);
02020
02021         return HAL_TIMEOUT;
02022       }
02023     }
02024   }
02025   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
02026   {
02027     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
02028                                                                                     DSI_PSR_UANC))
02029     {
02030       /* Check for the Timeout */
02031       if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
02032       {
02033         /* Process Unlocked */
02034         __HAL_UNLOCK(hdsi);
02035
02036         return HAL_TIMEOUT;
02037       }
02038     }
02039   }
02040   else
02041   {
02042     /* Process unlocked */
02043     __HAL_UNLOCK(hdsi);
02044
02045     return HAL_ERROR;
02046   }
02047
02048   /* wait for 1 ms */
02049   HAL_Delay(1U);
02050
02051   /* De-assert the ULPM requests and the ULPM exit bits */
02052   hdsi->Instance->PUCR = 0U;
02053
02054   /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
02055   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PHY);
02056
02057   /* Restore clock lane configuration to HS */
02058   hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
02059
02060   /* Process unlocked */
02061   __HAL_UNLOCK(hdsi);
02062
02063   return HAL_OK;
02064 }
02065
02066 /**
02067   * @brief  Start test pattern generation
02068   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02069   *               the configuration information for the DSI.
02070   * @param  Mode  Pattern generator mode
02071   *          This parameter can be one of the following values:
02072   *           0 : Color bars (horizontal or vertical)
02073   *           1 : BER pattern (vertical only)
02074   * @param  Orientation  Pattern generator orientation
02075   *          This parameter can be one of the following values:
02076   *           0 : Vertical color bars
02077   *           1 : Horizontal color bars
02078   * @retval HAL status
02079   */
02080 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
02081 {
02082   /* Process locked */
02083   __HAL_LOCK(hdsi);
02084
02085   /* Configure pattern generator mode and orientation */
02086   hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
02087   hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
02088
02089   /* Enable pattern generator by setting PGE bit */
02090   hdsi->Instance->VMCR |= DSI_VMCR_PGE;
02091
02092   /* Process unlocked */
02093   __HAL_UNLOCK(hdsi);
02094
02095   return HAL_OK;
02096 }
02097
02098 /**
02099   * @brief  Stop test pattern generation
02100   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02101   *               the configuration information for the DSI.
02102   * @retval HAL status
02103   */
02104 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
02105 {
02106   /* Process locked */
02107   __HAL_LOCK(hdsi);
02108
02109   /* Disable pattern generator by clearing PGE bit */
02110   hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
02111
02112   /* Process unlocked */
02113   __HAL_UNLOCK(hdsi);
02114
02115   return HAL_OK;
02116 }
02117
02118 /**
02119   * @brief  Set Slew-Rate And Delay Tuning
02120   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02121   *               the configuration information for the DSI.
02122   * @param  CommDelay  Communication delay to be adjusted.
02123   *                    This parameter can be any value of @arg DSI_Communication_Delay
02124   * @param  Lane  select between clock or data lanes.
02125   *               This parameter can be any value of @arg DSI_Lane_Group
02126   * @param  Value  Custom value of the slew-rate or delay
02127   * @retval HAL status
02128   */
02129 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
02130                                                     uint32_t Value)
02131 {
02132   /* Process locked */
02133   __HAL_LOCK(hdsi);
02134
02135   /* Check function parameters */
02136   assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
02137   assert_param(IS_DSI_LANE_GROUP(Lane));
02138
02139   switch (CommDelay)
02140   {
02141     case DSI_SLEW_RATE_HSTX:
02142       if (Lane == DSI_CLOCK_LANE)
02143       {
02144         /* High-Speed Transmission Slew Rate Control on Clock Lane */
02145         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
02146         hdsi->Instance->WPCR[1U] |= Value << 16U;
02147       }
02148       else if (Lane == DSI_DATA_LANES)
02149       {
02150         /* High-Speed Transmission Slew Rate Control on Data Lanes */
02151         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
02152         hdsi->Instance->WPCR[1U] |= Value << 18U;
02153       }
02154       else
02155       {
02156         /* Process unlocked */
02157         __HAL_UNLOCK(hdsi);
02158
02159         return HAL_ERROR;
02160       }
02161       break;
02162     case DSI_SLEW_RATE_LPTX:
02163       if (Lane == DSI_CLOCK_LANE)
02164       {
02165         /* Low-Power transmission Slew Rate Compensation on Clock Lane */
02166         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
02167         hdsi->Instance->WPCR[1U] |= Value << 6U;
02168       }
02169       else if (Lane == DSI_DATA_LANES)
02170       {
02171         /* Low-Power transmission Slew Rate Compensation on Data Lanes */
02172         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
02173         hdsi->Instance->WPCR[1U] |= Value << 8U;
02174       }
02175       else
02176       {
02177         /* Process unlocked */
02178         __HAL_UNLOCK(hdsi);
02179
02180         return HAL_ERROR;
02181       }
02182       break;
02183     case DSI_HS_DELAY:
02184       if (Lane == DSI_CLOCK_LANE)
02185       {
02186         /* High-Speed Transmission Delay on Clock Lane */
02187         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
02188         hdsi->Instance->WPCR[1U] |= Value;
02189       }
02190       else if (Lane == DSI_DATA_LANES)
02191       {
02192         /* High-Speed Transmission Delay on Data Lanes */
02193         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
02194         hdsi->Instance->WPCR[1U] |= Value << 2U;
02195       }
02196       else
02197       {
02198         /* Process unlocked */
02199         __HAL_UNLOCK(hdsi);
02200
02201         return HAL_ERROR;
02202       }
02203       break;
02204     default:
02205       break;
02206   }
02207
02208   /* Process unlocked */
02209   __HAL_UNLOCK(hdsi);
02210
02211   return HAL_OK;
02212 }
02213
02214 /**
02215   * @brief  Low-Power Reception Filter Tuning
02216   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02217   *               the configuration information for the DSI.
02218   * @param  Frequency  cutoff frequency of low-pass filter at the input of LPRX
02219   * @retval HAL status
02220   */
02221 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
02222 {
02223   /* Process locked */
02224   __HAL_LOCK(hdsi);
02225
02226   /* Low-Power RX low-pass Filtering Tuning */
02227   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
02228   hdsi->Instance->WPCR[1U] |= Frequency << 25U;
02229
02230   /* Process unlocked */
02231   __HAL_UNLOCK(hdsi);
02232
02233   return HAL_OK;
02234 }
02235
02236 /**
02237   * @brief  Activate an additional current path on all lanes to meet the SDDTx parameter
02238   *         defined in the MIPI D-PHY specification
02239   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02240   *               the configuration information for the DSI.
02241   * @param  State  ENABLE or DISABLE
02242   * @retval HAL status
02243   */
02244 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
02245 {
02246   /* Process locked */
02247   __HAL_LOCK(hdsi);
02248
02249   /* Check function parameters */
02250   assert_param(IS_FUNCTIONAL_STATE(State));
02251
02252   /* Activate/Disactivate additional current path on all lanes */
02253   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
02254   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
02255
02256   /* Process unlocked */
02257   __HAL_UNLOCK(hdsi);
02258
02259   return HAL_OK;
02260 }
02261
02262 /**
02263   * @brief  Custom lane pins configuration
02264   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02265   *               the configuration information for the DSI.
02266   * @param  CustomLane  Function to be applyed on selected lane.
02267   *                     This parameter can be any value of @arg DSI_CustomLane
02268   * @param  Lane  select between clock or data lane 0 or data lane 1.
02269   *               This parameter can be any value of @arg DSI_Lane_Select
02270   * @param  State  ENABLE or DISABLE
02271   * @retval HAL status
02272   */
02273 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
02274                                                    FunctionalState State)
02275 {
02276   /* Process locked */
02277   __HAL_LOCK(hdsi);
02278
02279   /* Check function parameters */
02280   assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
02281   assert_param(IS_DSI_LANE(Lane));
02282   assert_param(IS_FUNCTIONAL_STATE(State));
02283
02284   switch (CustomLane)
02285   {
02286     case DSI_SWAP_LANE_PINS:
02287       if (Lane == DSI_CLK_LANE)
02288       {
02289         /* Swap pins on clock lane */
02290         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
02291         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
02292       }
02293       else if (Lane == DSI_DATA_LANE0)
02294       {
02295         /* Swap pins on data lane 0 */
02296         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
02297         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
02298       }
02299       else if (Lane == DSI_DATA_LANE1)
02300       {
02301         /* Swap pins on data lane 1 */
02302         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
02303         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
02304       }
02305       else
02306       {
02307         /* Process unlocked */
02308         __HAL_UNLOCK(hdsi);
02309
02310         return HAL_ERROR;
02311       }
02312       break;
02313     case DSI_INVERT_HS_SIGNAL:
02314       if (Lane == DSI_CLK_LANE)
02315       {
02316         /* Invert HS signal on clock lane */
02317         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
02318         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
02319       }
02320       else if (Lane == DSI_DATA_LANE0)
02321       {
02322         /* Invert HS signal on data lane 0 */
02323         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
02324         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
02325       }
02326       else if (Lane == DSI_DATA_LANE1)
02327       {
02328         /* Invert HS signal on data lane 1 */
02329         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
02330         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
02331       }
02332       else
02333       {
02334         /* Process unlocked */
02335         __HAL_UNLOCK(hdsi);
02336
02337         return HAL_ERROR;
02338       }
02339       break;
02340     default:
02341       break;
02342   }
02343
02344   /* Process unlocked */
02345   __HAL_UNLOCK(hdsi);
02346
02347   return HAL_OK;
02348 }
02349
02350 /**
02351   * @brief  Set custom timing for the PHY
02352   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02353   *               the configuration information for the DSI.
02354   * @param  Timing  PHY timing to be adjusted.
02355   *                 This parameter can be any value of @arg DSI_PHY_Timing
02356   * @param  State  ENABLE or DISABLE
02357   * @param  Value  Custom value of the timing
02358   * @retval HAL status
02359   */
02360 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
02361 {
02362   /* Process locked */
02363   __HAL_LOCK(hdsi);
02364
02365   /* Check function parameters */
02366   assert_param(IS_DSI_PHY_TIMING(Timing));
02367   assert_param(IS_FUNCTIONAL_STATE(State));
02368
02369   switch (Timing)
02370   {
02371     case DSI_TCLK_POST:
02372       /* Enable/Disable custom timing setting */
02373       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
02374       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
02375
02376       if (State != DISABLE)
02377       {
02378         /* Set custom value */
02379         hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
02380         hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
02381       }
02382
02383       break;
02384     case DSI_TLPX_CLK:
02385       /* Enable/Disable custom timing setting */
02386       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
02387       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
02388
02389       if (State != DISABLE)
02390       {
02391         /* Set custom value */
02392         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
02393         hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
02394       }
02395
02396       break;
02397     case DSI_THS_EXIT:
02398       /* Enable/Disable custom timing setting */
02399       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
02400       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
02401
02402       if (State != DISABLE)
02403       {
02404         /* Set custom value */
02405         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
02406         hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
02407       }
02408
02409       break;
02410     case DSI_TLPX_DATA:
02411       /* Enable/Disable custom timing setting */
02412       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
02413       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
02414
02415       if (State != DISABLE)
02416       {
02417         /* Set custom value */
02418         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
02419         hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
02420       }
02421
02422       break;
02423     case DSI_THS_ZERO:
02424       /* Enable/Disable custom timing setting */
02425       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
02426       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
02427
02428       if (State != DISABLE)
02429       {
02430         /* Set custom value */
02431         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
02432         hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
02433       }
02434
02435       break;
02436     case DSI_THS_TRAIL:
02437       /* Enable/Disable custom timing setting */
02438       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
02439       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
02440
02441       if (State != DISABLE)
02442       {
02443         /* Set custom value */
02444         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
02445         hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
02446       }
02447
02448       break;
02449     case DSI_THS_PREPARE:
02450       /* Enable/Disable custom timing setting */
02451       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
02452       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
02453
02454       if (State != DISABLE)
02455       {
02456         /* Set custom value */
02457         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
02458         hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
02459       }
02460
02461       break;
02462     case DSI_TCLK_ZERO:
02463       /* Enable/Disable custom timing setting */
02464       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
02465       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
02466
02467       if (State != DISABLE)
02468       {
02469         /* Set custom value */
02470         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
02471         hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
02472       }
02473
02474       break;
02475     case DSI_TCLK_PREPARE:
02476       /* Enable/Disable custom timing setting */
02477       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
02478       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
02479
02480       if (State != DISABLE)
02481       {
02482         /* Set custom value */
02483         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
02484         hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
02485       }
02486
02487       break;
02488     default:
02489       break;
02490   }
02491
02492   /* Process unlocked */
02493   __HAL_UNLOCK(hdsi);
02494
02495   return HAL_OK;
02496 }
02497
02498 /**
02499   * @brief  Force the Clock/Data Lane in TX Stop Mode
02500   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02501   *               the configuration information for the DSI.
02502   * @param  Lane  select between clock or data lanes.
02503   *               This parameter can be any value of @arg DSI_Lane_Group
02504   * @param  State  ENABLE or DISABLE
02505   * @retval HAL status
02506   */
02507 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
02508 {
02509   /* Process locked */
02510   __HAL_LOCK(hdsi);
02511
02512   /* Check function parameters */
02513   assert_param(IS_DSI_LANE_GROUP(Lane));
02514   assert_param(IS_FUNCTIONAL_STATE(State));
02515
02516   if (Lane == DSI_CLOCK_LANE)
02517   {
02518     /* Force/Unforce the Clock Lane in TX Stop Mode */
02519     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
02520     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
02521   }
02522   else if (Lane == DSI_DATA_LANES)
02523   {
02524     /* Force/Unforce the Data Lanes in TX Stop Mode */
02525     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
02526     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
02527   }
02528   else
02529   {
02530     /* Process unlocked */
02531     __HAL_UNLOCK(hdsi);
02532
02533     return HAL_ERROR;
02534   }
02535
02536   /* Process unlocked */
02537   __HAL_UNLOCK(hdsi);
02538
02539   return HAL_OK;
02540 }
02541
02542 /**
02543   * @brief  Force LP Receiver in Low-Power Mode
02544   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02545   *               the configuration information for the DSI.
02546   * @param  State  ENABLE or DISABLE
02547   * @retval HAL status
02548   */
02549 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
02550 {
02551   /* Process locked */
02552   __HAL_LOCK(hdsi);
02553
02554   /* Check function parameters */
02555   assert_param(IS_FUNCTIONAL_STATE(State));
02556
02557   /* Force/Unforce LP Receiver in Low-Power Mode */
02558   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
02559   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
02560
02561   /* Process unlocked */
02562   __HAL_UNLOCK(hdsi);
02563
02564   return HAL_OK;
02565 }
02566
02567 /**
02568   * @brief  Force Data Lanes in RX Mode after a BTA
02569   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02570   *               the configuration information for the DSI.
02571   * @param  State  ENABLE or DISABLE
02572   * @retval HAL status
02573   */
02574 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
02575 {
02576   /* Process locked */
02577   __HAL_LOCK(hdsi);
02578
02579   /* Check function parameters */
02580   assert_param(IS_FUNCTIONAL_STATE(State));
02581
02582   /* Force Data Lanes in RX Mode */
02583   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
02584   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
02585
02586   /* Process unlocked */
02587   __HAL_UNLOCK(hdsi);
02588
02589   return HAL_OK;
02590 }
02591
02592 /**
02593   * @brief  Enable a pull-down on the lanes to prevent from floating states when unused
02594   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02595   *               the configuration information for the DSI.
02596   * @param  State  ENABLE or DISABLE
02597   * @retval HAL status
02598   */
02599 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
02600 {
02601   /* Process locked */
02602   __HAL_LOCK(hdsi);
02603
02604   /* Check function parameters */
02605   assert_param(IS_FUNCTIONAL_STATE(State));
02606
02607   /* Enable/Disable pull-down on lanes */
02608   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
02609   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
02610
02611   /* Process unlocked */
02612   __HAL_UNLOCK(hdsi);
02613
02614   return HAL_OK;
02615 }
02616
02617 /**
02618   * @brief  Switch off the contention detection on data lanes
02619   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02620   *               the configuration information for the DSI.
02621   * @param  State  ENABLE or DISABLE
02622   * @retval HAL status
02623   */
02624 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
02625 {
02626   /* Process locked */
02627   __HAL_LOCK(hdsi);
02628
02629   /* Check function parameters */
02630   assert_param(IS_FUNCTIONAL_STATE(State));
02631
02632   /* Contention Detection on Data Lanes OFF */
02633   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
02634   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
02635
02636   /* Process unlocked */
02637   __HAL_UNLOCK(hdsi);
02638
02639   return HAL_OK;
02640 }
02641
02642 /**
02643   * @}
02644   */
02645
02646 /** @defgroup DSI_Group4 Peripheral State and Errors functions
02647   *  @brief    Peripheral State and Errors functions
02648   *
02649 @verbatim
02650  ===============================================================================
02651                   ##### Peripheral State and Errors functions #####
02652  ===============================================================================
02653     [..]
02654     This subsection provides functions allowing to
02655       (+) Check the DSI state.
02656       (+) Get error code.
02657
02658 @endverbatim
02659   * @{
02660   */
02661
02662 /**
02663   * @brief  Return the DSI state
02664   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02665   *               the configuration information for the DSI.
02666   * @retval HAL state
02667   */
02668 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
02669 {
02670   return hdsi->State;
02671 }
02672
02673 /**
02674   * @brief  Return the DSI error code
02675   * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
02676   *               the configuration information for the DSI.
02677   * @retval DSI Error Code
02678   */
02679 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
02680 {
02681   /* Get the error code */
02682   return hdsi->ErrorCode;
02683 }
02684
02685 /**
02686   * @}
02687   */
02688
02689 /**
02690   * @}
02691   */
02692
02693 /**
02694   * @}
02695   */
02696
02697 #endif /* DSI */
02698
02699 #endif /* HAL_DSI_MODULE_ENABLED */
02700
02701 /**
02702   * @}
02703   */
02704
02705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dsi.h Source File

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stm32h7xx_hal_dsi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dsi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DSI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_DSI_H
00022 #define STM32H7xx_HAL_DSI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 #if defined(DSI)
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @defgroup DSI DSI
00037   * @brief DSI HAL module driver
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /**
00043   * @brief  DSI Init Structure definition
00044   */
00045 typedef struct
00046 {
00047   uint32_t AutomaticClockLaneControl;    /*!< Automatic clock lane control
00048                                               This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
00049
00050   uint32_t TXEscapeCkdiv;                /*!< TX Escape clock division
00051                                               The values 0 and 1 stop the TX_ESC clock generation                    */
00052
00053   uint32_t NumberOfLanes;                /*!< Number of lanes
00054                                               This parameter can be any value of @ref DSI_Number_Of_Lanes            */
00055
00056 } DSI_InitTypeDef;
00057
00058 /**
00059   * @brief  DSI PLL Clock structure definition
00060   */
00061 typedef struct
00062 {
00063   uint32_t PLLNDIV;                      /*!< PLL Loop Division Factor
00064                                               This parameter must be a value between 10 and 125   */
00065
00066   uint32_t PLLIDF;                       /*!< PLL Input Division Factor
00067                                               This parameter can be any value of @ref DSI_PLL_IDF */
00068
00069   uint32_t PLLODF;                       /*!< PLL Output Division Factor
00070                                               This parameter can be any value of @ref DSI_PLL_ODF */
00071
00072 } DSI_PLLInitTypeDef;
00073
00074 /**
00075   * @brief  DSI Video mode configuration
00076   */
00077 typedef struct
00078 {
00079   uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                 */
00080
00081   uint32_t ColorCoding;                  /*!< Color coding for LTDC interface
00082                                               This parameter can be any value of @ref DSI_Color_Coding           */
00083
00084   uint32_t LooselyPacked;                /*!< Enable or disable loosely packed stream (needed only when using
00085                                               18-bit configuration).
00086                                               This parameter can be any value of @ref DSI_LooselyPacked          */
00087
00088   uint32_t Mode;                         /*!< Video mode type
00089                                               This parameter can be any value of @ref DSI_Video_Mode_Type        */
00090
00091   uint32_t PacketSize;                   /*!< Video packet size                                                  */
00092
00093   uint32_t NumberOfChunks;               /*!< Number of chunks                                                   */
00094
00095   uint32_t NullPacketSize;               /*!< Null packet size                                                   */
00096
00097   uint32_t HSPolarity;                   /*!< HSYNC pin polarity
00098                                               This parameter can be any value of @ref DSI_HSYNC_Polarity         */
00099
00100   uint32_t VSPolarity;                   /*!< VSYNC pin polarity
00101                                               This parameter can be any value of @ref DSI_VSYNC_Active_Polarity  */
00102
00103   uint32_t DEPolarity;                   /*!< Data Enable pin polarity
00104                                               This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity   */
00105
00106   uint32_t HorizontalSyncActive;         /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
00107
00108   uint32_t HorizontalBackPorch;          /*!< Horizontal back-porch duration (in lane byte clock cycles)         */
00109
00110   uint32_t HorizontalLine;               /*!< Horizontal line duration (in lane byte clock cycles)               */
00111
00112   uint32_t VerticalSyncActive;           /*!< Vertical synchronism active duration                               */
00113
00114   uint32_t VerticalBackPorch;            /*!< Vertical back-porch duration                                       */
00115
00116   uint32_t VerticalFrontPorch;           /*!< Vertical front-porch duration                                      */
00117
00118   uint32_t VerticalActive;               /*!< Vertical active duration                                           */
00119
00120   uint32_t LPCommandEnable;              /*!< Low-power command enable
00121                                               This parameter can be any value of @ref DSI_LP_Command             */
00122
00123   uint32_t LPLargestPacketSize;          /*!< The size, in bytes, of the low power largest packet that
00124                                               can fit in a line during VSA, VBP and VFP regions                  */
00125
00126   uint32_t LPVACTLargestPacketSize;      /*!< The size, in bytes, of the low power largest packet that
00127                                               can fit in a line during VACT region                               */
00128
00129   uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
00130                                               This parameter can be any value of @ref DSI_LP_HFP                 */
00131
00132   uint32_t LPHorizontalBackPorchEnable;  /*!< Low-power horizontal back-porch enable
00133                                               This parameter can be any value of @ref DSI_LP_HBP                 */
00134
00135   uint32_t LPVerticalActiveEnable;       /*!< Low-power vertical active enable
00136                                               This parameter can be any value of @ref DSI_LP_VACT                */
00137
00138   uint32_t LPVerticalFrontPorchEnable;   /*!< Low-power vertical front-porch enable
00139                                               This parameter can be any value of @ref DSI_LP_VFP                 */
00140
00141   uint32_t LPVerticalBackPorchEnable;    /*!< Low-power vertical back-porch enable
00142                                               This parameter can be any value of @ref DSI_LP_VBP                 */
00143
00144   uint32_t LPVerticalSyncActiveEnable;   /*!< Low-power vertical sync active enable
00145                                               This parameter can be any value of @ref DSI_LP_VSYNC               */
00146
00147   uint32_t FrameBTAAcknowledgeEnable;    /*!< Frame bus-turn-around acknowledge enable
00148                                               This parameter can be any value of @ref DSI_FBTA_acknowledge       */
00149
00150 } DSI_VidCfgTypeDef;
00151
00152 /**
00153   * @brief  DSI Adapted command mode configuration
00154   */
00155 typedef struct
00156 {
00157   uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                */
00158
00159   uint32_t ColorCoding;                  /*!< Color coding for LTDC interface
00160                                               This parameter can be any value of @ref DSI_Color_Coding          */
00161
00162   uint32_t CommandSize;                  /*!< Maximum allowed size for an LTDC write memory command, measured in
00163                                               pixels. This parameter can be any value between 0x00 and 0xFFFFU   */
00164
00165   uint32_t TearingEffectSource;          /*!< Tearing effect source
00166                                               This parameter can be any value of @ref DSI_TearingEffectSource   */
00167
00168   uint32_t TearingEffectPolarity;        /*!< Tearing effect pin polarity
00169                                               This parameter can be any value of @ref DSI_TearingEffectPolarity */
00170
00171   uint32_t HSPolarity;                   /*!< HSYNC pin polarity
00172                                               This parameter can be any value of @ref DSI_HSYNC_Polarity        */
00173
00174   uint32_t VSPolarity;                   /*!< VSYNC pin polarity
00175                                               This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
00176
00177   uint32_t DEPolarity;                   /*!< Data Enable pin polarity
00178                                               This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity  */
00179
00180   uint32_t VSyncPol;                     /*!< VSync edge on which the LTDC is halted
00181                                               This parameter can be any value of @ref DSI_Vsync_Polarity        */
00182
00183   uint32_t AutomaticRefresh;             /*!< Automatic refresh mode
00184                                               This parameter can be any value of @ref DSI_AutomaticRefresh      */
00185
00186   uint32_t TEAcknowledgeRequest;         /*!< Tearing Effect Acknowledge Request Enable
00187                                               This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
00188
00189 } DSI_CmdCfgTypeDef;
00190
00191 /**
00192   * @brief  DSI command transmission mode configuration
00193   */
00194 typedef struct
00195 {
00196   uint32_t LPGenShortWriteNoP;           /*!< Generic Short Write Zero parameters Transmission
00197                                               This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP  */
00198
00199   uint32_t LPGenShortWriteOneP;          /*!< Generic Short Write One parameter Transmission
00200                                               This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
00201
00202   uint32_t LPGenShortWriteTwoP;          /*!< Generic Short Write Two parameters Transmission
00203                                               This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
00204
00205   uint32_t LPGenShortReadNoP;            /*!< Generic Short Read Zero parameters Transmission
00206                                               This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP   */
00207
00208   uint32_t LPGenShortReadOneP;           /*!< Generic Short Read One parameter Transmission
00209                                               This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP  */
00210
00211   uint32_t LPGenShortReadTwoP;           /*!< Generic Short Read Two parameters Transmission
00212                                               This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP  */
00213
00214   uint32_t LPGenLongWrite;               /*!< Generic Long Write Transmission
00215                                               This parameter can be any value of @ref DSI_LP_LPGenLongWrite      */
00216
00217   uint32_t LPDcsShortWriteNoP;           /*!< DCS Short Write Zero parameters Transmission
00218                                               This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP  */
00219
00220   uint32_t LPDcsShortWriteOneP;          /*!< DCS Short Write One parameter Transmission
00221                                               This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
00222
00223   uint32_t LPDcsShortReadNoP;            /*!< DCS Short Read Zero parameters Transmission
00224                                               This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP   */
00225
00226   uint32_t LPDcsLongWrite;               /*!< DCS Long Write Transmission
00227                                               This parameter can be any value of @ref DSI_LP_LPDcsLongWrite      */
00228
00229   uint32_t LPMaxReadPacket;              /*!< Maximum Read Packet Size Transmission
00230                                               This parameter can be any value of @ref DSI_LP_LPMaxReadPacket     */
00231
00232   uint32_t AcknowledgeRequest;           /*!< Acknowledge Request Enable
00233                                               This parameter can be any value of @ref DSI_AcknowledgeRequest     */
00234
00235 } DSI_LPCmdTypeDef;
00236
00237 /**
00238   * @brief  DSI PHY Timings definition
00239   */
00240 typedef struct
00241 {
00242   uint32_t ClockLaneHS2LPTime;           /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
00243                                               to low-power transmission                                              */
00244
00245   uint32_t ClockLaneLP2HSTime;           /*!< The maximum time that the D-PHY clock lane takes to go from low-power
00246                                               to high-speed transmission                                             */
00247
00248   uint32_t DataLaneHS2LPTime;            /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
00249                                               to low-power transmission                                              */
00250
00251   uint32_t DataLaneLP2HSTime;            /*!< The maximum time that the D-PHY data lanes takes to go from low-power
00252                                               to high-speed transmission                                             */
00253
00254   uint32_t DataLaneMaxReadTime;          /*!< The maximum time required to perform a read command */
00255
00256   uint32_t StopWaitTime;                 /*!< The minimum wait period to request a High-Speed transmission after the
00257                                               Stop state                                                             */
00258
00259 } DSI_PHY_TimerTypeDef;
00260
00261 /**
00262   * @brief  DSI HOST Timeouts definition
00263   */
00264 typedef struct
00265 {
00266   uint32_t TimeoutCkdiv;                 /*!< Time-out clock division                                  */
00267
00268   uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out                         */
00269
00270   uint32_t LowPowerReceptionTimeout;     /*!< Low-power reception time-out                             */
00271
00272   uint32_t HighSpeedReadTimeout;         /*!< High-speed read time-out                                 */
00273
00274   uint32_t LowPowerReadTimeout;          /*!< Low-power read time-out                                  */
00275
00276   uint32_t HighSpeedWriteTimeout;        /*!< High-speed write time-out                                */
00277
00278   uint32_t HighSpeedWritePrespMode;      /*!< High-speed write presp mode
00279                                               This parameter can be any value of @ref DSI_HS_PrespMode */
00280
00281   uint32_t LowPowerWriteTimeout;         /*!< Low-speed write time-out                                 */
00282
00283   uint32_t BTATimeout;                   /*!< BTA time-out                                             */
00284
00285 } DSI_HOST_TimeoutTypeDef;
00286
00287 /**
00288   * @brief  DSI States Structure definition
00289   */
00290 typedef enum
00291 {
00292   HAL_DSI_STATE_RESET   = 0x00U,
00293   HAL_DSI_STATE_READY   = 0x01U,
00294   HAL_DSI_STATE_ERROR   = 0x02U,
00295   HAL_DSI_STATE_BUSY    = 0x03U,
00296   HAL_DSI_STATE_TIMEOUT = 0x04U
00297 } HAL_DSI_StateTypeDef;
00298
00299 /**
00300   * @brief  DSI Handle Structure definition
00301   */
00302 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00303 typedef struct __DSI_HandleTypeDef
00304 #else
00305 typedef struct
00306 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00307 {
00308   DSI_TypeDef               *Instance;    /*!< Register base address      */
00309   DSI_InitTypeDef           Init;         /*!< DSI required parameters    */
00310   HAL_LockTypeDef           Lock;         /*!< DSI peripheral status      */
00311   __IO HAL_DSI_StateTypeDef State;        /*!< DSI communication state    */
00312   __IO uint32_t             ErrorCode;    /*!< DSI Error code             */
00313   uint32_t                  ErrorMsk;     /*!< DSI Error monitoring mask  */
00314
00315 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00316   void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);   /*!< DSI Tearing Effect Callback */
00317   void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);    /*!< DSI End Of Refresh Callback */
00318   void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);           /*!< DSI Error Callback          */
00319
00320   void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);         /*!< DSI Msp Init callback       */
00321   void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);       /*!< DSI Msp DeInit callback     */
00322
00323 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00324
00325 } DSI_HandleTypeDef;
00326
00327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00328 /**
00329   * @brief  HAL DSI Callback ID enumeration definition
00330   */
00331 typedef enum
00332 {
00333   HAL_DSI_MSPINIT_CB_ID            = 0x00U,    /*!< DSI MspInit callback ID        */
00334   HAL_DSI_MSPDEINIT_CB_ID          = 0x01U,    /*!< DSI MspDeInit callback ID      */
00335
00336   HAL_DSI_TEARING_EFFECT_CB_ID     = 0x02U,    /*!< DSI Tearing Effect Callback ID */
00337   HAL_DSI_ENDOF_REFRESH_CB_ID      = 0x03U,    /*!< DSI End Of Refresh Callback ID */
00338   HAL_DSI_ERROR_CB_ID              = 0x04U     /*!< DSI Error Callback ID          */
00339
00340 } HAL_DSI_CallbackIDTypeDef;
00341
00342 /**
00343   * @brief  HAL DSI Callback pointer definition
00344   */
00345 typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to an DSI callback function */
00346
00347 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00348
00349 /* Exported constants --------------------------------------------------------*/
00350 /** @defgroup DSI_Exported_Constants DSI Exported Constants
00351   * @{
00352   */
00353 /** @defgroup DSI_DCS_Command DSI DCS Command
00354   * @{
00355   */
00356 #define DSI_ENTER_IDLE_MODE       0x39U
00357 #define DSI_ENTER_INVERT_MODE     0x21U
00358 #define DSI_ENTER_NORMAL_MODE     0x13U
00359 #define DSI_ENTER_PARTIAL_MODE    0x12U
00360 #define DSI_ENTER_SLEEP_MODE      0x10U
00361 #define DSI_EXIT_IDLE_MODE        0x38U
00362 #define DSI_EXIT_INVERT_MODE      0x20U
00363 #define DSI_EXIT_SLEEP_MODE       0x11U
00364 #define DSI_GET_3D_CONTROL        0x3FU
00365 #define DSI_GET_ADDRESS_MODE      0x0BU
00366 #define DSI_GET_BLUE_CHANNEL      0x08U
00367 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
00368 #define DSI_GET_DISPLAY_MODE      0x0DU
00369 #define DSI_GET_GREEN_CHANNEL     0x07U
00370 #define DSI_GET_PIXEL_FORMAT      0x0CU
00371 #define DSI_GET_POWER_MODE        0x0AU
00372 #define DSI_GET_RED_CHANNEL       0x06U
00373 #define DSI_GET_SCANLINE          0x45U
00374 #define DSI_GET_SIGNAL_MODE       0x0EU
00375 #define DSI_NOP                   0x00U
00376 #define DSI_READ_DDB_CONTINUE     0xA8U
00377 #define DSI_READ_DDB_START        0xA1U
00378 #define DSI_READ_MEMORY_CONTINUE  0x3EU
00379 #define DSI_READ_MEMORY_START     0x2EU
00380 #define DSI_SET_3D_CONTROL        0x3DU
00381 #define DSI_SET_ADDRESS_MODE      0x36U
00382 #define DSI_SET_COLUMN_ADDRESS    0x2AU
00383 #define DSI_SET_DISPLAY_OFF       0x28U
00384 #define DSI_SET_DISPLAY_ON        0x29U
00385 #define DSI_SET_GAMMA_CURVE       0x26U
00386 #define DSI_SET_PAGE_ADDRESS      0x2BU
00387 #define DSI_SET_PARTIAL_COLUMNS   0x31U
00388 #define DSI_SET_PARTIAL_ROWS      0x30U
00389 #define DSI_SET_PIXEL_FORMAT      0x3AU
00390 #define DSI_SET_SCROLL_AREA       0x33U
00391 #define DSI_SET_SCROLL_START      0x37U
00392 #define DSI_SET_TEAR_OFF          0x34U
00393 #define DSI_SET_TEAR_ON           0x35U
00394 #define DSI_SET_TEAR_SCANLINE     0x44U
00395 #define DSI_SET_VSYNC_TIMING      0x40U
00396 #define DSI_SOFT_RESET            0x01U
00397 #define DSI_WRITE_LUT             0x2DU
00398 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
00399 #define DSI_WRITE_MEMORY_START    0x2CU
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
00405   * @{
00406   */
00407 #define DSI_VID_MODE_NB_PULSES    0U
00408 #define DSI_VID_MODE_NB_EVENTS    1U
00409 #define DSI_VID_MODE_BURST        2U
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup DSI_Color_Mode DSI Color Mode
00415   * @{
00416   */
00417 #define DSI_COLOR_MODE_FULL       0x00000000U
00418 #define DSI_COLOR_MODE_EIGHT      DSI_WCR_COLM
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup DSI_ShutDown DSI ShutDown
00424   * @{
00425   */
00426 #define DSI_DISPLAY_ON            0x00000000U
00427 #define DSI_DISPLAY_OFF           DSI_WCR_SHTDN
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup DSI_LP_Command DSI LP Command
00433   * @{
00434   */
00435 #define DSI_LP_COMMAND_DISABLE    0x00000000U
00436 #define DSI_LP_COMMAND_ENABLE     DSI_VMCR_LPCE
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup DSI_LP_HFP DSI LP HFP
00442   * @{
00443   */
00444 #define DSI_LP_HFP_DISABLE        0x00000000U
00445 #define DSI_LP_HFP_ENABLE         DSI_VMCR_LPHFPE
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup DSI_LP_HBP DSI LP HBP
00451   * @{
00452   */
00453 #define DSI_LP_HBP_DISABLE        0x00000000U
00454 #define DSI_LP_HBP_ENABLE         DSI_VMCR_LPHBPE
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup DSI_LP_VACT DSI LP VACT
00460   * @{
00461   */
00462 #define DSI_LP_VACT_DISABLE       0x00000000U
00463 #define DSI_LP_VACT_ENABLE        DSI_VMCR_LPVAE
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup DSI_LP_VFP DSI LP VFP
00469   * @{
00470   */
00471 #define DSI_LP_VFP_DISABLE       0x00000000U
00472 #define DSI_LP_VFP_ENABLE        DSI_VMCR_LPVFPE
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup DSI_LP_VBP DSI LP VBP
00478   * @{
00479   */
00480 #define DSI_LP_VBP_DISABLE       0x00000000U
00481 #define DSI_LP_VBP_ENABLE        DSI_VMCR_LPVBPE
00482 /**
00483   * @}
00484   */
00485
00486 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
00487   * @{
00488   */
00489 #define DSI_LP_VSYNC_DISABLE     0x00000000U
00490 #define DSI_LP_VSYNC_ENABLE      DSI_VMCR_LPVSAE
00491 /**
00492   * @}
00493   */
00494
00495 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
00496   * @{
00497   */
00498 #define DSI_FBTAA_DISABLE        0x00000000U
00499 #define DSI_FBTAA_ENABLE         DSI_VMCR_FBTAAE
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
00505   * @{
00506   */
00507 #define DSI_TE_DSILINK           0x00000000U
00508 #define DSI_TE_EXTERNAL          DSI_WCFGR_TESRC
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
00514   * @{
00515   */
00516 #define DSI_TE_RISING_EDGE       0x00000000U
00517 #define DSI_TE_FALLING_EDGE      DSI_WCFGR_TEPOL
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
00523   * @{
00524   */
00525 #define DSI_VSYNC_FALLING        0x00000000U
00526 #define DSI_VSYNC_RISING         DSI_WCFGR_VSPOL
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
00532   * @{
00533   */
00534 #define DSI_AR_DISABLE           0x00000000U
00535 #define DSI_AR_ENABLE            DSI_WCFGR_AR
00536 /**
00537   * @}
00538   */
00539
00540 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
00541   * @{
00542   */
00543 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
00544 #define DSI_TE_ACKNOWLEDGE_ENABLE  DSI_CMCR_TEARE
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
00550   * @{
00551   */
00552 #define DSI_ACKNOWLEDGE_DISABLE   0x00000000U
00553 #define DSI_ACKNOWLEDGE_ENABLE    DSI_CMCR_ARE
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
00559   * @{
00560   */
00561 #define DSI_LP_GSW0P_DISABLE     0x00000000U
00562 #define DSI_LP_GSW0P_ENABLE      DSI_CMCR_GSW0TX
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
00568   * @{
00569   */
00570 #define DSI_LP_GSW1P_DISABLE     0x00000000U
00571 #define DSI_LP_GSW1P_ENABLE      DSI_CMCR_GSW1TX
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
00577   * @{
00578   */
00579 #define DSI_LP_GSW2P_DISABLE     0x00000000U
00580 #define DSI_LP_GSW2P_ENABLE      DSI_CMCR_GSW2TX
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
00586   * @{
00587   */
00588 #define DSI_LP_GSR0P_DISABLE     0x00000000U
00589 #define DSI_LP_GSR0P_ENABLE      DSI_CMCR_GSR0TX
00590 /**
00591   * @}
00592   */
00593
00594 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
00595   * @{
00596   */
00597 #define DSI_LP_GSR1P_DISABLE     0x00000000U
00598 #define DSI_LP_GSR1P_ENABLE      DSI_CMCR_GSR1TX
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
00604   * @{
00605   */
00606 #define DSI_LP_GSR2P_DISABLE     0x00000000U
00607 #define DSI_LP_GSR2P_ENABLE      DSI_CMCR_GSR2TX
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
00613   * @{
00614   */
00615 #define DSI_LP_GLW_DISABLE       0x00000000U
00616 #define DSI_LP_GLW_ENABLE        DSI_CMCR_GLWTX
00617 /**
00618   * @}
00619   */
00620
00621 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
00622   * @{
00623   */
00624 #define DSI_LP_DSW0P_DISABLE     0x00000000U
00625 #define DSI_LP_DSW0P_ENABLE      DSI_CMCR_DSW0TX
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
00631   * @{
00632   */
00633 #define DSI_LP_DSW1P_DISABLE     0x00000000U
00634 #define DSI_LP_DSW1P_ENABLE      DSI_CMCR_DSW1TX
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
00640   * @{
00641   */
00642 #define DSI_LP_DSR0P_DISABLE     0x00000000U
00643 #define DSI_LP_DSR0P_ENABLE      DSI_CMCR_DSR0TX
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
00649   * @{
00650   */
00651 #define DSI_LP_DLW_DISABLE       0x00000000U
00652 #define DSI_LP_DLW_ENABLE        DSI_CMCR_DLWTX
00653 /**
00654   * @}
00655   */
00656
00657 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
00658   * @{
00659   */
00660 #define DSI_LP_MRDP_DISABLE      0x00000000U
00661 #define DSI_LP_MRDP_ENABLE       DSI_CMCR_MRDPS
00662 /**
00663   * @}
00664   */
00665
00666 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
00667   * @{
00668   */
00669 #define DSI_HS_PM_DISABLE        0x00000000U
00670 #define DSI_HS_PM_ENABLE         DSI_TCCR3_PM
00671 /**
00672   * @}
00673   */
00674
00675
00676 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
00677   * @{
00678   */
00679 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
00680 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
00686   * @{
00687   */
00688 #define DSI_ONE_DATA_LANE          0U
00689 #define DSI_TWO_DATA_LANES         1U
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup DSI_FlowControl DSI Flow Control
00695   * @{
00696   */
00697 #define DSI_FLOW_CONTROL_CRC_RX    DSI_PCR_CRCRXE
00698 #define DSI_FLOW_CONTROL_ECC_RX    DSI_PCR_ECCRXE
00699 #define DSI_FLOW_CONTROL_BTA       DSI_PCR_BTAE
00700 #define DSI_FLOW_CONTROL_EOTP_RX   DSI_PCR_ETRXE
00701 #define DSI_FLOW_CONTROL_EOTP_TX   DSI_PCR_ETTXE
00702 #define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
00703                                     DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
00704                                     DSI_FLOW_CONTROL_EOTP_TX)
00705 /**
00706   * @}
00707   */
00708
00709 /** @defgroup DSI_Color_Coding DSI Color Coding
00710   * @{
00711   */
00712 #define DSI_RGB565                 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
00713 #define DSI_RGB666                 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration                 */
00714 #define DSI_RGB888                 0x00000005U
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
00720   * @{
00721   */
00722 #define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE
00723 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
00729   * @{
00730   */
00731 #define DSI_HSYNC_ACTIVE_HIGH       0x00000000U
00732 #define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
00738   * @{
00739   */
00740 #define DSI_VSYNC_ACTIVE_HIGH       0x00000000U
00741 #define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
00747   * @{
00748   */
00749 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
00750 #define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP
00751 /**
00752   * @}
00753   */
00754
00755 /** @defgroup DSI_PLL_IDF DSI PLL IDF
00756   * @{
00757   */
00758 #define DSI_PLL_IN_DIV1             0x00000001U
00759 #define DSI_PLL_IN_DIV2             0x00000002U
00760 #define DSI_PLL_IN_DIV3             0x00000003U
00761 #define DSI_PLL_IN_DIV4             0x00000004U
00762 #define DSI_PLL_IN_DIV5             0x00000005U
00763 #define DSI_PLL_IN_DIV6             0x00000006U
00764 #define DSI_PLL_IN_DIV7             0x00000007U
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup DSI_PLL_ODF DSI PLL ODF
00770   * @{
00771   */
00772 #define DSI_PLL_OUT_DIV1            0x00000000U
00773 #define DSI_PLL_OUT_DIV2            0x00000001U
00774 #define DSI_PLL_OUT_DIV4            0x00000002U
00775 #define DSI_PLL_OUT_DIV8            0x00000003U
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup DSI_Flags DSI Flags
00781   * @{
00782   */
00783 #define DSI_FLAG_TE                 DSI_WISR_TEIF
00784 #define DSI_FLAG_ER                 DSI_WISR_ERIF
00785 #define DSI_FLAG_BUSY               DSI_WISR_BUSY
00786 #define DSI_FLAG_PLLLS              DSI_WISR_PLLLS
00787 #define DSI_FLAG_PLLL               DSI_WISR_PLLLIF
00788 #define DSI_FLAG_PLLU               DSI_WISR_PLLUIF
00789 #define DSI_FLAG_RRS                DSI_WISR_RRS
00790 #define DSI_FLAG_RR                 DSI_WISR_RRIF
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup DSI_Interrupts DSI Interrupts
00796   * @{
00797   */
00798 #define DSI_IT_TE                   DSI_WIER_TEIE
00799 #define DSI_IT_ER                   DSI_WIER_ERIE
00800 #define DSI_IT_PLLL                 DSI_WIER_PLLLIE
00801 #define DSI_IT_PLLU                 DSI_WIER_PLLUIE
00802 #define DSI_IT_RR                   DSI_WIER_RRIE
00803 /**
00804   * @}
00805   */
00806
00807 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
00808   * @{
00809   */
00810 #define DSI_DCS_SHORT_PKT_WRITE_P0  0x00000005U /*!< DCS short write, no parameters      */
00811 #define DSI_DCS_SHORT_PKT_WRITE_P1  0x00000015U /*!< DCS short write, one parameter      */
00812 #define DSI_GEN_SHORT_PKT_WRITE_P0  0x00000003U /*!< Generic short write, no parameters  */
00813 #define DSI_GEN_SHORT_PKT_WRITE_P1  0x00000013U /*!< Generic short write, one parameter  */
00814 #define DSI_GEN_SHORT_PKT_WRITE_P2  0x00000023U /*!< Generic short write, two parameters */
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
00820   * @{
00821   */
00822 #define DSI_DCS_LONG_PKT_WRITE      0x00000039U /*!< DCS long write     */
00823 #define DSI_GEN_LONG_PKT_WRITE      0x00000029U /*!< Generic long write */
00824 /**
00825   * @}
00826   */
00827
00828 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
00829   * @{
00830   */
00831 #define DSI_DCS_SHORT_PKT_READ      0x00000006U /*!< DCS short read                     */
00832 #define DSI_GEN_SHORT_PKT_READ_P0   0x00000004U /*!< Generic short read, no parameters  */
00833 #define DSI_GEN_SHORT_PKT_READ_P1   0x00000014U /*!< Generic short read, one parameter  */
00834 #define DSI_GEN_SHORT_PKT_READ_P2   0x00000024U /*!< Generic short read, two parameters */
00835 /**
00836   * @}
00837   */
00838
00839 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
00840   * @{
00841   */
00842 #define HAL_DSI_ERROR_NONE              0U
00843 #define HAL_DSI_ERROR_ACK               0x00000001U /*!< acknowledge errors          */
00844 #define HAL_DSI_ERROR_PHY               0x00000002U /*!< PHY related errors          */
00845 #define HAL_DSI_ERROR_TX                0x00000004U /*!< transmission error          */
00846 #define HAL_DSI_ERROR_RX                0x00000008U /*!< reception error             */
00847 #define HAL_DSI_ERROR_ECC               0x00000010U /*!< ECC errors                  */
00848 #define HAL_DSI_ERROR_CRC               0x00000020U /*!< CRC error                   */
00849 #define HAL_DSI_ERROR_PSE               0x00000040U /*!< Packet Size error           */
00850 #define HAL_DSI_ERROR_EOT               0x00000080U /*!< End Of Transmission error   */
00851 #define HAL_DSI_ERROR_OVF               0x00000100U /*!< FIFO overflow error         */
00852 #define HAL_DSI_ERROR_GEN               0x00000200U /*!< Generic FIFO related errors */
00853 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00854 #define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U /*!< DSI Invalid Callback error  */
00855 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup DSI_Lane_Group DSI Lane Group
00861   * @{
00862   */
00863 #define DSI_CLOCK_LANE              0x00000000U
00864 #define DSI_DATA_LANES              0x00000001U
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup DSI_Communication_Delay DSI Communication Delay
00870   * @{
00871   */
00872 #define DSI_SLEW_RATE_HSTX          0x00000000U
00873 #define DSI_SLEW_RATE_LPTX          0x00000001U
00874 #define DSI_HS_DELAY                0x00000002U
00875 /**
00876   * @}
00877   */
00878
00879 /** @defgroup DSI_CustomLane DSI CustomLane
00880   * @{
00881   */
00882 #define DSI_SWAP_LANE_PINS          0x00000000U
00883 #define DSI_INVERT_HS_SIGNAL        0x00000001U
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup DSI_Lane_Select DSI Lane Select
00889   * @{
00890   */
00891 #define DSI_CLK_LANE                0x00000000U
00892 #define DSI_DATA_LANE0              0x00000001U
00893 #define DSI_DATA_LANE1              0x00000002U
00894 /**
00895   * @}
00896   */
00897
00898 /** @defgroup DSI_PHY_Timing DSI PHY Timing
00899   * @{
00900   */
00901 #define DSI_TCLK_POST               0x00000000U
00902 #define DSI_TLPX_CLK                0x00000001U
00903 #define DSI_THS_EXIT                0x00000002U
00904 #define DSI_TLPX_DATA               0x00000003U
00905 #define DSI_THS_ZERO                0x00000004U
00906 #define DSI_THS_TRAIL               0x00000005U
00907 #define DSI_THS_PREPARE             0x00000006U
00908 #define DSI_TCLK_ZERO               0x00000007U
00909 #define DSI_TCLK_PREPARE            0x00000008U
00910 /**
00911   * @}
00912   */
00913
00914 /**
00915   * @}
00916   */
00917
00918 /* Exported macros -----------------------------------------------------------*/
00919 /** @defgroup DSI_Exported_Macros DSI Exported Macros
00920   * @{
00921   */
00922
00923 /**
00924   * @brief Reset DSI handle state.
00925   * @param  __HANDLE__: DSI handle
00926   * @retval None
00927   */
00928 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
00929 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
00930                                                      (__HANDLE__)->State = HAL_DSI_STATE_RESET;    \
00931                                                      (__HANDLE__)->MspInitCallback = NULL;         \
00932                                                      (__HANDLE__)->MspDeInitCallback = NULL;       \
00933                                                    } while(0)
00934 #else
00935 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
00936 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
00937
00938 /**
00939   * @brief  Enables the DSI host.
00940   * @param  __HANDLE__  DSI handle
00941   * @retval None.
00942   */
00943 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
00944                                           __IO uint32_t tmpreg = 0x00U; \
00945                                           SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
00946                                           /* Delay after an DSI Host enabling */ \
00947                                           tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
00948                                           UNUSED(tmpreg); \
00949                                         } while(0U)
00950
00951 /**
00952   * @brief  Disables the DSI host.
00953   * @param  __HANDLE__  DSI handle
00954   * @retval None.
00955   */
00956 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
00957                                           __IO uint32_t tmpreg = 0x00U; \
00958                                           CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
00959                                           /* Delay after an DSI Host disabling */ \
00960                                           tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
00961                                           UNUSED(tmpreg); \
00962                                          } while(0U)
00963
00964 /**
00965   * @brief  Enables the DSI wrapper.
00966   * @param  __HANDLE__  DSI handle
00967   * @retval None.
00968   */
00969 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
00970                                                  __IO uint32_t tmpreg = 0x00U; \
00971                                                  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
00972                                                  /* Delay after an DSI warpper enabling */ \
00973                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
00974                                                  UNUSED(tmpreg); \
00975                                                 } while(0U)
00976
00977 /**
00978   * @brief  Disable the DSI wrapper.
00979   * @param  __HANDLE__  DSI handle
00980   * @retval None.
00981   */
00982 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
00983                                                   __IO uint32_t tmpreg = 0x00U; \
00984                                                   CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
00985                                                   /* Delay after an DSI warpper disabling*/ \
00986                                                   tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
00987                                                   UNUSED(tmpreg); \
00988                                                  } while(0U)
00989
00990 /**
00991   * @brief  Enables the DSI PLL.
00992   * @param  __HANDLE__  DSI handle
00993   * @retval None.
00994   */
00995 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
00996                                              __IO uint32_t tmpreg = 0x00U; \
00997                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
00998                                              /* Delay after an DSI PLL enabling */ \
00999                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
01000                                              UNUSED(tmpreg); \
01001                                             } while(0U)
01002
01003 /**
01004   * @brief  Disables the DSI PLL.
01005   * @param  __HANDLE__  DSI handle
01006   * @retval None.
01007   */
01008 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
01009                                               __IO uint32_t tmpreg = 0x00U; \
01010                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
01011                                               /* Delay after an DSI PLL disabling */ \
01012                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
01013                                               UNUSED(tmpreg); \
01014                                              } while(0U)
01015
01016 /**
01017   * @brief  Enables the DSI regulator.
01018   * @param  __HANDLE__  DSI handle
01019   * @retval None.
01020   */
01021 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
01022                                               __IO uint32_t tmpreg = 0x00U; \
01023                                               SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
01024                                               /* Delay after an DSI regulator enabling */ \
01025                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
01026                                               UNUSED(tmpreg); \
01027                                             } while(0U)
01028
01029 /**
01030   * @brief  Disables the DSI regulator.
01031   * @param  __HANDLE__  DSI handle
01032   * @retval None.
01033   */
01034 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
01035                                               __IO uint32_t tmpreg = 0x00U; \
01036                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
01037                                               /* Delay after an DSI regulator disabling */ \
01038                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
01039                                               UNUSED(tmpreg); \
01040                                              } while(0U)
01041
01042 /**
01043   * @brief  Get the DSI pending flags.
01044   * @param  __HANDLE__  DSI handle.
01045   * @param  __FLAG__  Get the specified flag.
01046   *          This parameter can be any combination of the following values:
01047   *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
01048   *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
01049   *            @arg DSI_FLAG_BUSY : Busy Flag
01050   *            @arg DSI_FLAG_PLLLS: PLL Lock Status
01051   *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
01052   *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
01053   *            @arg DSI_FLAG_RRS  : Regulator Ready Flag
01054   *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
01055   * @retval The state of FLAG (SET or RESET).
01056   */
01057 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
01058
01059 /**
01060   * @brief  Clears the DSI pending flags.
01061   * @param  __HANDLE__  DSI handle.
01062   * @param  __FLAG__  specifies the flag to clear.
01063   *          This parameter can be any combination of the following values:
01064   *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
01065   *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
01066   *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
01067   *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
01068   *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
01069   * @retval None
01070   */
01071 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
01072
01073 /**
01074   * @brief  Enables the specified DSI interrupts.
01075   * @param  __HANDLE__  DSI handle.
01076   * @param __INTERRUPT__  specifies the DSI interrupt sources to be enabled.
01077   *          This parameter can be any combination of the following values:
01078   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
01079   *            @arg DSI_IT_ER  : End of Refresh Interrupt
01080   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
01081   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
01082   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
01083   * @retval None
01084   */
01085 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
01086
01087 /**
01088   * @brief  Disables the specified DSI interrupts.
01089   * @param  __HANDLE__  DSI handle
01090   * @param __INTERRUPT__  specifies the DSI interrupt sources to be disabled.
01091   *          This parameter can be any combination of the following values:
01092   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
01093   *            @arg DSI_IT_ER  : End of Refresh Interrupt
01094   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
01095   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
01096   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
01097   * @retval None
01098   */
01099 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
01100
01101 /**
01102   * @brief  Checks whether the specified DSI interrupt source is enabled or not.
01103   * @param  __HANDLE__  DSI handle
01104   * @param  __INTERRUPT__  specifies the DSI interrupt source to check.
01105   *          This parameter can be one of the following values:
01106   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
01107   *            @arg DSI_IT_ER  : End of Refresh Interrupt
01108   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
01109   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
01110   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
01111   * @retval The state of INTERRUPT (SET or RESET).
01112   */
01113 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
01114
01115 /**
01116   * @}
01117   */
01118
01119 /* Exported functions --------------------------------------------------------*/
01120 /** @defgroup DSI_Exported_Functions DSI Exported Functions
01121   * @{
01122   */
01123 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
01124 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
01125 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
01126 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
01127
01128 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
01129 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
01130 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
01131 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
01132
01133 /* Callbacks Register/UnRegister functions  ***********************************/
01134 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
01135 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
01136                                            pDSI_CallbackTypeDef pCallback);
01137 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
01138 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
01139
01140 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
01141 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
01142 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
01143 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
01144 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
01145 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
01146 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
01147 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
01148 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
01149 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
01150 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
01151 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
01152 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
01153                                      uint32_t ChannelID,
01154                                      uint32_t Mode,
01155                                      uint32_t Param1,
01156                                      uint32_t Param2);
01157 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
01158                                     uint32_t ChannelID,
01159                                     uint32_t Mode,
01160                                     uint32_t NbParams,
01161                                     uint32_t Param1,
01162                                     uint8_t *ParametersTable);
01163 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
01164                                uint32_t ChannelNbr,
01165                                uint8_t *Array,
01166                                uint32_t Size,
01167                                uint32_t Mode,
01168                                uint32_t DCSCmd,
01169                                uint8_t *ParametersTable);
01170 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
01171 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
01172 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
01173 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
01174
01175 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
01176 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
01177
01178 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
01179                                                     uint32_t Value);
01180 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
01181 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
01182 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
01183                                                    FunctionalState State);
01184 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
01185                                         uint32_t Value);
01186 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
01187 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
01188 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
01189 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
01190 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
01191
01192 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
01193 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
01194 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
01195 /**
01196   * @}
01197   */
01198
01199 /* Private types -------------------------------------------------------------*/
01200 /** @defgroup DSI_Private_Types DSI Private Types
01201   * @{
01202   */
01203
01204 /**
01205   * @}
01206   */
01207
01208 /* Private defines -----------------------------------------------------------*/
01209 /** @defgroup DSI_Private_Defines DSI Private Defines
01210   * @{
01211   */
01212
01213 /**
01214   * @}
01215   */
01216
01217 /* Private variables ---------------------------------------------------------*/
01218 /** @defgroup DSI_Private_Variables DSI Private Variables
01219   * @{
01220   */
01221
01222 /**
01223   * @}
01224   */
01225
01226 /* Private constants ---------------------------------------------------------*/
01227 /** @defgroup DSI_Private_Constants DSI Private Constants
01228   * @{
01229   */
01230 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
01231 /**
01232   * @}
01233   */
01234
01235 /* Private macros ------------------------------------------------------------*/
01236 /** @defgroup DSI_Private_Macros DSI Private Macros
01237   * @{
01238   */
01239 #define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))
01240 #define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \
01241                                                      ((IDF) == DSI_PLL_IN_DIV2) || \
01242                                                      ((IDF) == DSI_PLL_IN_DIV3) || \
01243                                                      ((IDF) == DSI_PLL_IN_DIV4) || \
01244                                                      ((IDF) == DSI_PLL_IN_DIV5) || \
01245                                                      ((IDF) == DSI_PLL_IN_DIV6) || \
01246                                                      ((IDF) == DSI_PLL_IN_DIV7))
01247 #define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \
01248                                                      ((ODF) == DSI_PLL_OUT_DIV2) || \
01249                                                      ((ODF) == DSI_PLL_OUT_DIV4) || \
01250                                                      ((ODF) == DSI_PLL_OUT_DIV8))
01251 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
01252 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
01253 #define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
01254 #define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)
01255 #define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
01256 #define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
01257 #define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
01258 #define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
01259 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
01260                                                      ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
01261                                                      ((VideoModeType) == DSI_VID_MODE_BURST))
01262 #define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
01263 #define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
01264 #define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
01265 #define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
01266 #define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
01267 #define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
01268 #define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
01269 #define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
01270 #define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
01271 #define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
01272 #define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
01273 #define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
01274 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
01275 #define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
01276 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
01277 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
01278 #define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
01279 #define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
01280 #define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
01281 #define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
01282 #define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
01283 #define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
01284 #define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
01285 #define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
01286 #define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
01287 #define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
01288 #define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
01289 #define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
01290 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
01291                                                      ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
01292                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
01293                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
01294                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
01295 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
01296                                                      ((MODE) == DSI_GEN_LONG_PKT_WRITE))
01297 #define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
01298                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
01299                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
01300                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
01301 #define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
01302 #define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
01303 #define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
01304 #define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
01305 #define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \
01306                                                      ((Timing) == DSI_TLPX_CLK    ) || \
01307                                                      ((Timing) == DSI_THS_EXIT    ) || \
01308                                                      ((Timing) == DSI_TLPX_DATA   ) || \
01309                                                      ((Timing) == DSI_THS_ZERO    ) || \
01310                                                      ((Timing) == DSI_THS_TRAIL   ) || \
01311                                                      ((Timing) == DSI_THS_PREPARE ) || \
01312                                                      ((Timing) == DSI_TCLK_ZERO   ) || \
01313                                                      ((Timing) == DSI_TCLK_PREPARE))
01314
01315 /**
01316   * @}
01317   */
01318
01319 /* Private functions prototypes ----------------------------------------------*/
01320 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
01321   * @{
01322   */
01323
01324 /**
01325   * @}
01326   */
01327
01328 /* Private functions ---------------------------------------------------------*/
01329 /** @defgroup DSI_Private_Functions DSI Private Functions
01330   * @{
01331   */
01332
01333 /**
01334   * @}
01335   */
01336
01337 /**
01338   * @}
01339   */
01340
01341 /**
01342   * @}
01343   */
01344 #endif /* DSI */
01345
01346 #ifdef __cplusplus
01347 }
01348 #endif
01349
01350 #endif /* STM32H7xx_HAL_DSI_H */
01351
01352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dts.c Source File

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stm32h7xx_hal_dts.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dts.c
00004   * @author  MCD Application Team
00005   * @brief   DTS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DTS peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015 ================================================================================
00016           ##### DTS Peripheral features #####
00017 ================================================================================
00018
00019   [..]
00020       The STM32h7xx device family integrate one DTS sensor interface :
00021
00022
00023             ##### How to use this driver #####
00024 ================================================================================
00025   [..]
00026
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00033   * All rights reserved.</center></h2>
00034   *
00035   * This software component is licensed by ST under BSD 3-Clause license,
00036   * the "License"; You may not use this file except in compliance with the
00037   * License. You may obtain a copy of the License at:
00038   *                        opensource.org/licenses/BSD-3-Clause
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx_hal.h"
00045
00046 /** @addtogroup STM32H7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 #ifdef HAL_DTS_MODULE_ENABLED
00051
00052 #if defined(DTS)
00053
00054 /** @defgroup DTS DTS
00055   * @brief DTS HAL module driver
00056   * @{
00057   */
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /** @addtogroup DTS_Private_Constants
00062   * @{
00063   */
00064
00065 /* @brief Delay for DTS startup time
00066  * @note  Delay required to get ready for DTS Block.
00067  * @note  Unit: ms
00068  */
00069 #define DTS_DELAY_STARTUP (1UL)
00070
00071 /* @brief DTS measure ready flag time out value.
00072  * @note  Maximal measurement time is when LSE is selected as ref_clock and
00073  *        maximal sampling time is used, taking calibration into account this
00074  *        is equivalent to ~620 us. Use 5 ms as arbitrary timeout
00075  * @note Unit: ms
00076  */
00077 #define TS_TIMEOUT_MS     (5UL)
00078
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00083 static void DTS_ResetCallback(DTS_HandleTypeDef *hdts);
00084 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00085 /* Exported functions --------------------------------------------------------*/
00086
00087 /** @defgroup DTS_Exported_Functions DTS Exported Functions
00088   * @{
00089   */
00090
00091 /** @defgroup DTS_Exported_Functions_Group1 Initialization/de-initialization functions
00092  *  @brief    Initialization and de-initialization functions.
00093  *
00094 @verbatim
00095  ===============================================================================
00096               ##### Initialization and de-initialization functions #####
00097  ===============================================================================
00098     [..]  This section provides functions to initialize and de-initialize comparators
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  Initialize the DTS according to the specified
00106   *         parameters in the DTS_InitTypeDef and initialize the associated handle.
00107   * @param  hdts  DTS handle
00108   * @retval HAL status
00109   */
00110 HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
00111 {
00112   /* Check the DTS handle allocation */
00113   if (hdts == NULL)
00114   {
00115     return HAL_ERROR;
00116   }
00117
00118   /* Check the parameters */
00119   assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
00120   assert_param(IS_DTS_QUICKMEAS(hdts->Init.QuickMeasure));
00121   assert_param(IS_DTS_REFCLK(hdts->Init.RefClock));
00122   assert_param(IS_DTS_TRIGGERINPUT(hdts->Init.TriggerInput));
00123   assert_param(IS_DTS_SAMPLINGTIME(hdts->Init.SamplingTime));
00124   assert_param(IS_DTS_THRESHOLD(hdts->Init.HighThreshold));
00125   assert_param(IS_DTS_THRESHOLD(hdts->Init.LowThreshold));
00126
00127   if (hdts->State == HAL_DTS_STATE_RESET)
00128   {
00129 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00130     /* Reset interrupt callbacks to legacy weak callbacks */
00131     DTS_ResetCallback(hdts);
00132
00133     if (hdts->MspInitCallback == NULL)
00134     {
00135       hdts->MspInitCallback = HAL_DTS_MspInit;
00136     }
00137
00138     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00139     hdts->MspInitCallback(hdts);
00140 #else
00141     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00142     HAL_DTS_MspInit(hdts);
00143 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00144   }
00145
00146   /* Change the DTS state */
00147   hdts->State = HAL_DTS_STATE_BUSY;
00148
00149   /* Check ramp coefficient */
00150   if (hdts->Instance->RAMPVALR == 0UL)
00151   {
00152     return HAL_ERROR;
00153   }
00154
00155   /* Check factory calibration temperature  */
00156   if (hdts->Instance->T0VALR1 == 0UL)
00157   {
00158     return HAL_ERROR;
00159   }
00160
00161   /* Check Quick Measure option is enabled or disabled */
00162   if (hdts->Init.QuickMeasure == DTS_QUICKMEAS_DISABLE)
00163   {
00164     /* Check Reference clock selection */
00165     if (hdts->Init.RefClock == DTS_REFCLKSEL_PCLK)
00166     {
00167       assert_param(IS_DTS_DIVIDER_RATIO_NUMBER(hdts->Init.Divider));
00168     }
00169     /* Quick measurement mode disabled */
00170     CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
00171   }
00172   else
00173   {
00174     /* DTS_QUICKMEAS_ENABLE shall be used only when the LSE clock is
00175        selected as reference clock */
00176     if (hdts->Init.RefClock != DTS_REFCLKSEL_LSE)
00177     {
00178       return HAL_ERROR;
00179     }
00180
00181     /* Quick measurement mode enabled - no calibration needed */
00182     SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
00183   }
00184
00185   /* set the DTS clk source */
00186   if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
00187   {
00188     SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
00189   }
00190   else
00191   {
00192     CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
00193   }
00194
00195   MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_HSREF_CLK_DIV, (hdts->Init.Divider << DTS_CFGR1_HSREF_CLK_DIV_Pos));
00196   MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_SMP_TIME, hdts->Init.SamplingTime);
00197   MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL, hdts->Init.TriggerInput);
00198   MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_HITTHD, (hdts->Init.HighThreshold << DTS_ITR1_TS1_HITTHD_Pos));
00199   MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_LITTHD, hdts->Init.LowThreshold);
00200
00201   /* Change the DTS state */
00202   hdts->State = HAL_DTS_STATE_READY;
00203
00204   return HAL_OK;
00205 }
00206
00207 /**
00208   * @brief  DeInitialize the DTS peripheral.
00209   * @note   Deinitialization cannot be performed if the DTS configuration is locked.
00210   *         To unlock the configuration, perform a system reset.
00211   * @param  hdts  DTS handle
00212   * @retval HAL status
00213   */
00214 HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts)
00215 {
00216   /* Check the DTS handle allocation */
00217   if (hdts == NULL)
00218   {
00219     return HAL_ERROR;
00220   }
00221
00222   /* Check the parameter */
00223   assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
00224
00225   /* Set DTS_CFGR register to reset value */
00226   CLEAR_REG(hdts->Instance->CFGR1);
00227
00228 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00229   if (hdts->MspDeInitCallback == NULL)
00230   {
00231     hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
00232   }
00233
00234   /* DeInit the low level hardware: CLOCK, NVIC.*/
00235   hdts->MspDeInitCallback(hdts);
00236 #else
00237   /* DeInit the low level hardware: CLOCK, NVIC.*/
00238   HAL_DTS_MspDeInit(hdts);
00239 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00240
00241   hdts->State = HAL_DTS_STATE_RESET;
00242
00243   return HAL_OK;
00244 }
00245
00246 /**
00247   * @brief  Initialize the DTS MSP.
00248   * @param  hdts  DTS handle
00249   * @retval None
00250   */
00251 __weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts)
00252 {
00253   /* Prevent unused argument(s) compilation warning */
00254   UNUSED(hdts);
00255
00256   /* NOTE : This function should not be modified, when the callback is needed,
00257   the HAL_DTS_MspInit could be implemented in the user file
00258   */
00259 }
00260
00261 /**
00262   * @brief  DeInitialize the DTS MSP.
00263   * @param  hdts  DTS handle
00264   * @retval None
00265   */
00266 __weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
00267 {
00268   /* Prevent unused argument(s) compilation warning */
00269   UNUSED(hdts);
00270
00271   /* NOTE : This function should not be modified, when the callback is needed,
00272   the HAL_DTS_MspDeInit could be implemented in the user file
00273   */
00274 }
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup DTS_Exported_Functions_Group2 Start-Stop operation functions
00281  *  @brief   Start-Stop operation functions.
00282  *
00283 @verbatim
00284  ===============================================================================
00285                       ##### DTS Start Stop operation functions #####
00286  ===============================================================================
00287     [..]  This section provides functions allowing to:
00288       (+) Start a DTS Sensor without interrupt.
00289       (+) Stop a DTS Sensor without interrupt.
00290       (+) Start a DTS Sensor with interrupt generation.
00291       (+) Stop a DTS Sensor with interrupt generation.
00292
00293 @endverbatim
00294   * @{
00295   */
00296
00297 /**
00298   * @brief  Start the DTS sensor.
00299   * @param  hdts  DTS handle
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts)
00303 {
00304   uint32_t Ref_Time;
00305
00306   /* Check the DTS handle allocation */
00307   if (hdts == NULL)
00308   {
00309     return HAL_ERROR;
00310   }
00311
00312   if (hdts->State == HAL_DTS_STATE_READY)
00313   {
00314     hdts->State = HAL_DTS_STATE_BUSY;
00315
00316     /* Enable DTS sensor */
00317     __HAL_DTS_ENABLE(hdts);
00318
00319     /* Get Start Tick*/
00320     Ref_Time = HAL_GetTick();
00321
00322     /* Wait till TS1_RDY flag is set */
00323     while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
00324     {
00325       if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
00326       {
00327         return HAL_TIMEOUT;
00328       }
00329     }
00330
00331     if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
00332     {
00333       /* Start continuous measures */
00334       SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
00335
00336       /* Ensure start is taken into account */
00337       HAL_Delay(TS_TIMEOUT_MS);
00338     }
00339
00340     hdts->State = HAL_DTS_STATE_READY;
00341   }
00342   else
00343   {
00344     return HAL_BUSY;
00345   }
00346
00347   return HAL_OK;
00348 }
00349
00350 /**
00351   * @brief  Stop the DTS Sensor.
00352   * @param  hdts  DTS handle
00353   * @retval HAL status
00354   */
00355 HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts)
00356 {
00357   /* Check the DTS handle allocation */
00358   if (hdts == NULL)
00359   {
00360     return HAL_ERROR;
00361   }
00362
00363   if (hdts->State == HAL_DTS_STATE_READY)
00364   {
00365     hdts->State = HAL_DTS_STATE_BUSY;
00366
00367     if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
00368     {
00369       CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
00370     }
00371
00372     /* Disable the selected DTS sensor */
00373     __HAL_DTS_DISABLE(hdts);
00374
00375     hdts->State = HAL_DTS_STATE_READY;
00376   }
00377   else
00378   {
00379     return HAL_BUSY;
00380   }
00381
00382   return HAL_OK;
00383 }
00384
00385 /**
00386   * @brief  Enable the interrupt(s) and start the DTS sensor
00387   * @param  hdts  DTS handle
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts)
00391 {
00392   uint32_t Ref_Time;
00393
00394   /* Check the DTS handle allocation */
00395   if (hdts == NULL)
00396   {
00397     return HAL_ERROR;
00398   }
00399
00400   if (hdts->State == HAL_DTS_STATE_READY)
00401   {
00402     hdts->State = HAL_DTS_STATE_BUSY;
00403
00404     /* On Asynchronous mode enable the asynchronous IT */
00405     if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
00406     {
00407       __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
00408     }
00409     else
00410     {
00411       /* Enable the IT(s) */
00412       __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
00413     }
00414
00415     /* Enable the selected DTS sensor */
00416     __HAL_DTS_ENABLE(hdts);
00417
00418     /* Get Start Tick*/
00419     Ref_Time = HAL_GetTick();
00420
00421     /* Wait till TS1_RDY flag is set */
00422     while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
00423     {
00424       if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
00425       {
00426         return HAL_TIMEOUT;
00427       }
00428     }
00429
00430     if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
00431     {
00432       /* Start continuous measures */
00433       SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
00434
00435       /* Ensure start is taken into account */
00436       HAL_Delay(TS_TIMEOUT_MS);
00437     }
00438
00439     hdts->State = HAL_DTS_STATE_READY;
00440   }
00441   else
00442   {
00443     return HAL_BUSY;
00444   }
00445
00446   return HAL_OK;
00447 }
00448
00449 /**
00450   * @brief  Disable the interrupt(s) and stop the DTS sensor.
00451   * @param  hdts  DTS handle
00452   * @retval HAL status
00453   */
00454 HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts)
00455 {
00456   /* Check the DTS handle allocation */
00457   if (hdts == NULL)
00458   {
00459     return HAL_ERROR;
00460   }
00461
00462   if (hdts->State == HAL_DTS_STATE_READY)
00463   {
00464     hdts->State = HAL_DTS_STATE_BUSY;
00465
00466     /* On Asynchronous mode disable the asynchronous IT */
00467     if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
00468     {
00469       __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
00470     }
00471     else
00472     {
00473       /* Disable the IT(s) */
00474       __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
00475     }
00476
00477     if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
00478     {
00479       CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
00480     }
00481
00482     /* Disable the selected DTS sensor */
00483     __HAL_DTS_DISABLE(hdts);
00484
00485     hdts->State = HAL_DTS_STATE_READY;
00486   }
00487   else
00488   {
00489     return HAL_BUSY;
00490   }
00491
00492   return HAL_OK;
00493 }
00494
00495 /**
00496   * @brief  Get temperature from DTS
00497   * @param  hdts         DTS handle
00498   * @param  Temperature  Temperature in deg C
00499   * @note This function retrieves latest available measure
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature)
00503 {
00504   uint32_t freq_meas;
00505   uint32_t samples;
00506   uint32_t t0_temp;
00507   uint32_t t0_freq;
00508   uint32_t ramp_coeff;
00509
00510   if (hdts->State == HAL_DTS_STATE_READY)
00511   {
00512     hdts->State = HAL_DTS_STATE_BUSY;
00513
00514     /* Get the total number of samples */
00515     samples = (hdts->Instance->DR & DTS_DR_TS1_MFREQ);
00516
00517     if ((hdts->Init.SamplingTime == 0UL) || (samples == 0UL))
00518     {
00519       hdts->State = HAL_DTS_STATE_READY;
00520       return HAL_ERROR;
00521     }
00522
00523     if ((hdts->Init.RefClock) == DTS_REFCLKSEL_LSE)
00524     {
00525       freq_meas = (LSE_VALUE * samples) / (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos); /* On Hz */
00526     }
00527     else
00528     {
00529       freq_meas = (HAL_RCCEx_GetD3PCLK1Freq() * (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos)) / samples; /* On Hz */
00530     }
00531
00532     /* Read factory settings */
00533     t0_temp = hdts->Instance->T0VALR1 >> DTS_T0VALR1_TS1_T0_Pos;
00534
00535     if (t0_temp == 0UL)
00536     {
00537       t0_temp = 30UL; /* 30 deg C */
00538     }
00539     else if (t0_temp == 1UL)
00540     {
00541       t0_temp = 110UL; /* 110 deg C */
00542     }
00543     else
00544     {
00545       hdts->State = HAL_DTS_STATE_READY;
00546       return HAL_ERROR;
00547     }
00548
00549     t0_freq = (hdts->Instance->T0VALR1 & DTS_T0VALR1_TS1_FMT0) * 100UL; /* Hz */
00550
00551     ramp_coeff = hdts->Instance->RAMPVALR & DTS_RAMPVALR_TS1_RAMP_COEFF; /* deg C/Hz */
00552
00553     if (ramp_coeff == 0UL)
00554     {
00555       hdts->State = HAL_DTS_STATE_READY;
00556       return HAL_ERROR;
00557     }
00558
00559     /* Figure out the temperature deg C */
00560     *Temperature = (int32_t)t0_temp + (((int32_t)freq_meas - (int32_t)t0_freq) / (int32_t)ramp_coeff);
00561
00562     hdts->State = HAL_DTS_STATE_READY;
00563   }
00564   else
00565   {
00566     return HAL_BUSY;
00567   }
00568
00569   return HAL_OK;
00570 }
00571
00572 /**
00573   * @brief  DTS sensor IRQ Handler.
00574   * @param  hdts  DTS handle
00575   * @retval None
00576   */
00577 void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts)
00578 {
00579   /* Check end of measure Asynchronous IT */
00580   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITE)) != RESET)
00581   {
00582       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITE);
00583
00584 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00585       hdts->AsyncEndCallback(hdts);
00586 #else
00587       HAL_DTS_AsyncEndCallback(hdts);
00588 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00589   }
00590
00591   /* Check low threshold Asynchronous IT */
00592   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITL)) != RESET)
00593   {
00594       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITL);
00595
00596 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00597       hdts->AsyncLowCallback(hdts);
00598 #else
00599       HAL_DTS_AsyncLowCallback(hdts);
00600 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00601   }
00602
00603   /* Check high threshold Asynchronous IT */
00604   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITH)) != RESET)
00605   {
00606       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITH);
00607
00608 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00609       hdts->AsyncHighCallback(hdts);
00610 #else
00611       HAL_DTS_AsyncHighCallback(hdts);
00612 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00613   }
00614
00615   /* Check end of measure IT */
00616   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITE)) != RESET)
00617   {
00618       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITE);
00619
00620 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00621       hdts->EndCallback(hdts);
00622 #else
00623       HAL_DTS_EndCallback(hdts);
00624 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00625   }
00626
00627   /* Check low threshold IT */
00628   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITL)) != RESET)
00629   {
00630       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITL);
00631
00632 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00633       hdts->LowCallback(hdts);
00634 #else
00635       HAL_DTS_LowCallback(hdts);
00636 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00637   }
00638
00639   /* Check high threshold IT */
00640   if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITH)) != RESET)
00641   {
00642       __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITH);
00643
00644 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00645       hdts->HighCallback(hdts);
00646 #else
00647       HAL_DTS_HighCallback(hdts);
00648 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00649   }
00650 }
00651
00652 /**
00653   * @brief  DTS Sensor End measure callback.
00654   * @param  hdts  DTS handle
00655   * @retval None
00656   */
00657 __weak void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts)
00658 {
00659   /* Prevent unused argument(s) compilation warning */
00660   UNUSED(hdts);
00661
00662   /* NOTE : This function should not be modified, when the callback is needed,
00663   the HAL_DTS_EndCallback should be implemented in the user file
00664   */
00665 }
00666
00667 /**
00668   * @brief  DTS Sensor low threshold measure callback.
00669   * @param  hdts  DTS handle
00670   * @retval None
00671   */
00672 __weak void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts)
00673 {
00674   /* Prevent unused argument(s) compilation warning */
00675   UNUSED(hdts);
00676
00677   /* NOTE : This function should not be modified, when the callback is needed,
00678   the HAL_DTS_LowCallback should be implemented in the user file
00679   */
00680 }
00681
00682 /**
00683   * @brief  DTS Sensor high threshold measure callback.
00684   * @param  hdts  DTS handle
00685   * @retval None
00686   */
00687 __weak void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts)
00688 {
00689   /* Prevent unused argument(s) compilation warning */
00690   UNUSED(hdts);
00691
00692   /* NOTE : This function should not be modified, when the callback is needed,
00693   the HAL_DTS_HighCallback should be implemented in the user file
00694   */
00695 }
00696
00697 /**
00698   * @brief  DTS Sensor asynchronous end measure callback.
00699   * @param  hdts  DTS handle
00700   * @retval None
00701   */
00702 __weak void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts)
00703 {
00704   /* Prevent unused argument(s) compilation warning */
00705   UNUSED(hdts);
00706
00707   /* NOTE : This function should not be modified, when the callback is needed,
00708   the HAL_DTS_AsyncEndCallback should be implemented in the user file
00709   */
00710 }
00711
00712 /**
00713   * @brief  DTS Sensor asynchronous low threshold measure callback.
00714   * @param  hdts  DTS handle
00715   * @retval None
00716   */
00717 __weak void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts)
00718 {
00719   /* Prevent unused argument(s) compilation warning */
00720   UNUSED(hdts);
00721
00722   /* NOTE : This function should not be modified, when the callback is needed,
00723   the HAL_DTS_AsyncLowCallback should be implemented in the user file
00724   */
00725 }
00726
00727 /**
00728   * @brief  DTS Sensor asynchronous high threshold measure callback.
00729   * @param  hdts  DTS handle
00730   * @retval None
00731   */
00732 __weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts)
00733 {
00734   /* Prevent unused argument(s) compilation warning */
00735   UNUSED(hdts);
00736
00737   /* NOTE : This function should not be modified, when the callback is needed,
00738   the HAL_DTS_AsyncHighCallback should be implemented in the user file
00739   */
00740 }
00741
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup DTS_Exported_Functions_Group3 Peripheral State functions
00747  *  @brief   Peripheral State functions.
00748  *
00749 @verbatim
00750  ===============================================================================
00751                       ##### Peripheral State functions #####
00752  ===============================================================================
00753     [..]
00754     This subsection permits to get in run-time the status of the peripheral.
00755
00756 @endverbatim
00757   * @{
00758   */
00759
00760 /**
00761   * @brief  Return the DTS handle state.
00762   * @param  hdts  DTS handle
00763   * @retval HAL state
00764   */
00765 HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
00766 {
00767   /* Check the DTS handle allocation */
00768   if (hdts == NULL)
00769   {
00770     return HAL_DTS_STATE_RESET;
00771   }
00772
00773   /* Return DTS handle state */
00774   return hdts->State;
00775 }
00776 /**
00777   * @}
00778   */
00779
00780 /**
00781   * @}
00782   */
00783
00784 /* Private functions ---------------------------------------------------------*/
00785
00786 /** @defgroup DTS_Private_Functions DTS Private Functions
00787   * @{
00788   */
00789 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00790 /**
00791   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
00792   * @param  hdts pointer to a DTS_HandleTypeDef structure that contains
00793   *                the configuration information for DTS module.
00794   * @retval None
00795   */
00796 static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
00797 {
00798   /* Reset the DTS callback to the legacy weak callbacks */
00799   hdts->DTS_EndCallback       = HAL_DTS_EndCallback;        /* End measure Callback                 */
00800   hdts->DTS_LowCallback       = HAL_DTS_LowCallback;        /* low threshold Callback               */
00801   hdts->DTS_HighCallback      = HAL_DTS_HighCallback;       /* high threshold Callback              */
00802   hdts->DTS_AsyncEndCallback  = HAL_DTS_AsyncEndCallback;   /* Asynchronous end of measure Callback */
00803   hdts->DTS_AsyncLowCallback  = HAL_DTS_AsyncLowCallback;   /* Asynchronous low threshold Callback  */
00804   hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback;  /* Asynchronous high threshold Callback */
00805 }
00806 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00807 /**
00808   * @}
00809   */
00810
00811 /**
00812   * @}
00813   */
00814
00815 #endif /* DTS */
00816
00817 #endif /* HAL_DTS_MODULE_ENABLED */
00818
00819 /**
00820   * @}
00821   */
00822
00823 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_dts.h Source File

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stm32h7xx_hal_dts.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dts.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DTS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_HAL_DTS_H
00022 #define __STM32H7xx_HAL_DTS_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 #if defined(DTS)
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup DTS
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup DTS_Exported_Types DTS Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  DTS Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t QuickMeasure;  /*!< Specifies the quick measure option selection of the DTS sensor.
00051                                This parameter can be a value of @ref DTS_Quick_Measurement */
00052
00053   uint32_t RefClock;      /*!< Specifies the reference clock selection of the DTS sensor.
00054                                This parameter can be a value of @ref DTS_Reference_Clock_Selection */
00055
00056   uint32_t TriggerInput;  /*!< Specifies the trigger input of the DTS sensor.
00057                                This parameter can be a value of @ref DTS_TriggerConfig */
00058
00059   uint32_t SamplingTime;  /*!< Specifies the sampling time configuration.
00060                                This parameter can be a value of @ref DTS_Sampling_Time */
00061
00062   uint32_t Divider;       /*!< Specifies the high speed clock divider ratio.
00063                                This parameter can be a value from 0 to 127 */
00064
00065   uint32_t HighThreshold;  /*!< Specifies the high threshold of the DTS sensor */
00066
00067   uint32_t LowThreshold;   /*!< Specifies the low threshold of the DTS sensor */
00068
00069 } DTS_InitTypeDef;
00070
00071 /**
00072   * @brief  HAL State structures definition
00073   */
00074 typedef enum
00075 {
00076   HAL_DTS_STATE_RESET       = 0x00UL,     /*!< DTS not yet initialized or disabled */
00077   HAL_DTS_STATE_READY       = 0x01UL,     /*!< DTS initialized and ready for use   */
00078   HAL_DTS_STATE_BUSY        = 0x02UL,     /*!< DTS is running                      */
00079   HAL_DTS_STATE_TIMEOUT     = 0x03UL,     /*!< Timeout state                       */
00080   HAL_DTS_STATE_ERROR       = 0x04UL      /*!< Internal Process error              */
00081 } HAL_DTS_StateTypeDef;
00082
00083 /**
00084   * @brief  DTS Handle Structure definition
00085   */
00086 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00087 typedef struct __DTS_HandleTypeDef
00088 #else
00089 typedef struct
00090 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00091 {
00092   DTS_TypeDef         *Instance;    /*!< Register base address */
00093   DTS_InitTypeDef     Init;         /*!< DTS required parameters */
00094   HAL_LockTypeDef     Lock;         /*!< DTS Locking object */
00095   __IO HAL_DTS_StateTypeDef  State; /*!< DTS peripheral state  */
00096 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
00097   void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< DTS Base Msp Init Callback                   */
00098   void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);       /*!< DTS Base Msp DeInit Callback                 */
00099   void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< End measure Callback                         */
00100   void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< low threshold Callback                       */
00101   void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< high threshold Callback                      */
00102   void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous end of measure Callback         */
00103   void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous low threshold Callback          */
00104   void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous high threshold Callback         */
00105 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
00106 } DTS_HandleTypeDef;
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Exported constants --------------------------------------------------------*/
00113 /** @defgroup DTS_Exported_Constants DTS Exported Constants
00114   * @{
00115   */
00116
00117 /** @defgroup DTS_TriggerConfig  DTS Trigger Configuration
00118   * @{
00119   */
00120 /* @brief No Hardware trigger detection */
00121 #define DTS_TRIGGER_HW_NONE   (0UL)
00122
00123 /* @brief External Interrupt Mode with LPTIMER1 trigger detection */
00124 #define DTS_TRIGGER_LPTIMER1  DTS_CFGR1_TS1_INTRIG_SEL_0
00125
00126 /* @brief External Interrupt Mode with LPTIMER2 trigger detection */
00127 #define DTS_TRIGGER_LPTIMER2  DTS_CFGR1_TS1_INTRIG_SEL_1
00128
00129 /* @brief External Interrupt Mode with LPTIMER3 trigger detection */
00130 #define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
00131
00132 /* @brief External Interrupt Mode with EXTI13 trigger detection */
00133 #define DTS_TRIGGER_EXTI13    DTS_CFGR1_TS1_INTRIG_SEL_2
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup DTS_Quick_Measurement  DTS Quick Measurement
00139   * @{
00140   */
00141 #define DTS_QUICKMEAS_ENABLE    DTS_CFGR1_Q_MEAS_OPT      /*!< Enable the Quick Measure (Measure without calibration) */
00142 #define DTS_QUICKMEAS_DISABLE   (0x0UL)                   /*!< Disable the Quick Measure (Measure with calibration) */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup DTS_Reference_Clock_Selection   DTS Reference Clock Selection
00148   * @{
00149   */
00150 #define DTS_REFCLKSEL_LSE   DTS_CFGR1_REFCLK_SEL          /*!< Low speed REF clock (LSE) */
00151 #define DTS_REFCLKSEL_PCLK (0UL)                          /*!< High speed REF clock (PCLK) */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup DTS_Sampling_Time   DTS Sampling Time
00157   * @{
00158   */
00159 #define DTS_SMP_TIME_1_CYCLE     DTS_CFGR1_TS1_SMP_TIME_0                                                                                   /*!< 1 clock cycle for the sampling time  */
00160 #define DTS_SMP_TIME_2_CYCLE     DTS_CFGR1_TS1_SMP_TIME_1                                                                                   /*!< 2 clock cycle for the sampling time  */
00161 #define DTS_SMP_TIME_3_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1)                                                       /*!< 3 clock cycle for the sampling time  */
00162 #define DTS_SMP_TIME_4_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_2)                                                                                 /*!< 4 clock cycle for the sampling time  */
00163 #define DTS_SMP_TIME_5_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 5 clock cycle for the sampling time  */
00164 #define DTS_SMP_TIME_6_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 6 clock cycle for the sampling time  */
00165 #define DTS_SMP_TIME_7_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                            /*!< 7 clock cycle for the sampling time  */
00166 #define DTS_SMP_TIME_8_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_3)                                                                                  /*!< 8 clock cycle for the sampling time  */
00167 #define DTS_SMP_TIME_9_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 9 clock cycle for the sampling time  */
00168 #define DTS_SMP_TIME_10_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 10 clock cycle for the sampling time */
00169 #define DTS_SMP_TIME_11_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 11 clock cycle for the sampling time */
00170 #define DTS_SMP_TIME_12_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 12 clock cycle for the sampling time */
00171 #define DTS_SMP_TIME_13_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 13 clock cycle for the sampling time */
00172 #define DTS_SMP_TIME_14_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 14 clock cycle for the sampling time */
00173 #define DTS_SMP_TIME_15_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */
00174 /**
00175   * @}
00176   */
00177 /** @defgroup DTS_Flag_Definitions DTS Flag Definitions
00178   * @{
00179   */
00180 #define DTS_FLAG_TS1_ITE   DTS_SR_TS1_ITEF   /*!< Interrupt flag for end of measure for DTS1 */
00181 #define DTS_FLAG_TS1_ITL   DTS_SR_TS1_ITLF   /*!< Interrupt flag for low threshold for DTS1  */
00182 #define DTS_FLAG_TS1_ITH   DTS_SR_TS1_ITHF   /*!< Interrupt flag for high threshold for DTS1 */
00183 #define DTS_FLAG_TS1_AITE  DTS_SR_TS1_AITEF  /*!< Asynchronous Interrupt flag for end of measure for DTS1 */
00184 #define DTS_FLAG_TS1_AITL  DTS_SR_TS1_AITLF  /*!< Asynchronous Interrupt flag for low threshold for DTS1  */
00185 #define DTS_FLAG_TS1_AITH  DTS_SR_TS1_AITHF  /*!< Asynchronous Interrupt flag for high threshold for DTS1 */
00186 #define DTS_FLAG_TS1_RDY   DTS_SR_TS1_RDY    /*!< Ready flag for DTS1 */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions
00192   * @{
00193   */
00194 #define DTS_IT_TS1_ITE  DTS_ITENR_TS1_ITEEN   /*!< Enable interrupt flag for end of measure for DTS1 */
00195 #define DTS_IT_TS1_ITL  DTS_ITENR_TS1_ITLEN   /*!< Enable interrupt flag for low threshold for DTS1  */
00196 #define DTS_IT_TS1_ITH  DTS_ITENR_TS1_ITHEN   /*!< Enable interrupt flag for high threshold for DTS1 */
00197 #define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN  /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
00198 #define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN  /*!< Enable asynchronous interrupt flag for low threshold for DTS1  */
00199 #define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN  /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207 /* Exported macros -----------------------------------------------------------*/
00208 /** @defgroup DTS_Exported_Macros DTS Exported Macros
00209   * @{
00210   */
00211
00212 /** @brief  Reset DTS handle state
00213   * @param  __HANDLE__ DTS handle.
00214   * @retval None
00215   */
00216 #define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__)    ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
00217
00218 /**
00219   * @brief  Enable the specified DTS sensor
00220   * @param  __HANDLE__ DTS handle.
00221   * @retval None
00222   */
00223 #define __HAL_DTS_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
00224
00225 /**
00226   * @brief  Disable the specified DTS sensor
00227   * @param  __HANDLE__ DTS handle.
00228   * @retval None
00229   */
00230 #define __HAL_DTS_DISABLE(__HANDLE__)    CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
00231
00232 /**
00233   * @brief  Enable the DTS EXTI line in interrupt mode
00234   * @retval None
00235   */
00236 #define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT()  SET_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
00237
00238 /**
00239   * @brief  Disable the DTS EXTI line in interrupt mode
00240   * @retval None
00241   */
00242 #define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT()  CLEAR_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
00243
00244 /**
00245   * @brief  Enable the DTS EXTI Line in event mode
00246   * @retval None
00247   */
00248 #define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
00249
00250 /**
00251   * @brief  Disable the DTS EXTI Line in event mode
00252   * @retval None
00253   */
00254 #define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
00255
00256 /** @brief  Checks whether the specified DTS flag is set or not.
00257   * @param  __HANDLE__ specifies the DTS Handle.
00258   * @param  __FLAG__ specifies the flag to check.
00259   *        This parameter can be one of the following values:
00260   *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
00261   *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
00262   *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
00263   *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
00264   *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
00265   *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
00266   *            @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1
00267   *            @retval The new state of __FLAG__ (SET or RESET).
00268   */
00269 #define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__)  \
00270         (((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
00271
00272
00273 /** @brief  Clears the specified DTS pending flag.
00274   * @param  __HANDLE__ specifies the DTS Handle.
00275   * @param  __FLAG__ specifies the flag to check.
00276   *          This parameter can be any combination of the following values:
00277   *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
00278   *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
00279   *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
00280   *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
00281   *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
00282   *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
00283   * @retval None
00284   */
00285 #define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__)  \
00286         ((__HANDLE__)->Instance->ICIFR  = (__FLAG__))
00287
00288
00289 /** @brief  Enable the specified DTS interrupt.
00290   * @param  __HANDLE__ specifies the DTS Handle.
00291   * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.
00292   *          This parameter can be one of the following values:
00293   *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
00294   *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
00295   *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
00296   *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
00297   *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
00298   *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
00299   * @retval None
00300   */
00301 #define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  \
00302         SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
00303
00304
00305 /** @brief  Disable the specified DTS interrupt.
00306   * @param  __HANDLE__ specifies the DTS Handle.
00307   * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.
00308   *          This parameter can be one of the following values:
00309   *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
00310   *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
00311   *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
00312   *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
00313   *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
00314   *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
00315   * @retval None
00316   */
00317 #define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__)  \
00318         CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
00319
00320
00321 /** @brief  Check whether the specified DTS interrupt source is enabled or not.
00322   * @param __HANDLE__ DTS handle.
00323   * @param __INTERRUPT__ DTS interrupt source to check
00324   *          This parameter can be one of the following values:
00325   *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
00326   *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
00327   *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
00328   *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
00329   *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
00330   *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
00331   * @retval State of interruption (SET or RESET)
00332   */
00333 #define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  \
00334         (( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__) \
00335         )? SET : RESET)
00336
00337
00338 /** @brief  Check whether the specified DTS REFCLK is selected
00339   * @param __HANDLE__ DTS handle.
00340   * @param __REFCLK__ DTS reference clock to check
00341   *          This parameter can be one of the following values:
00342   * @arg DTS_REFCLKSEL_LSE:   Low speed REF clock
00343   * @arg DTS_REFCLKSEL_PCLK:  High speed REF clock
00344   * @retval State of the REF clock tested (SET or RESET)
00345   */
00346 #define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__)  ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
00347
00348 /** @brief  Get Trigger
00349   * @param __HANDLE__ DTS handle.
00350   * @retval One of the following trigger
00351   *     DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)
00352   *     DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger
00353   *     DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger
00354   *     DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger
00355   *     DTS_TRIGGER_EXTI13  : EXTI13 trigger
00356   */
00357 #define __HAL_DTS_GET_TRIGGER(__HANDLE__)  ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
00358 /**
00359   * @}
00360   */
00361
00362 /* Exported functions --------------------------------------------------------*/
00363 /** @addtogroup DTS_Exported_Functions
00364   * @{
00365   */
00366
00367 /** @addtogroup DTS_Exported_Functions_Group1
00368   * @{
00369   */
00370 /* Initialization and de-initialization functions  **********************************/
00371 HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
00372 HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
00373 void              HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
00374 void              HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
00375 /**
00376   * @}
00377   */
00378
00379 /* IO operation functions  *****************************************************/
00380 /** @addtogroup DTS_Exported_Functions_Group2
00381   * @{
00382   */
00383 HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
00384 HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
00385 HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
00386 HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
00387 HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
00388 void              HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
00389 HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts);
00390 /* Callback in Interrupt mode */
00391 void              HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
00392 void              HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
00393 void              HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
00394 void              HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
00395 void              HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
00396 void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
00397 /**
00398   * @}
00399   */
00400
00401 /* Private types -------------------------------------------------------------*/
00402 /* Private constants ---------------------------------------------------------*/
00403 /** @defgroup DTS_Private_Constants DTS Private Constants
00404   * @{
00405   */
00406 /** @defgroup DTS_ExtiLine DTS EXTI Lines
00407   * @{
00408   */
00409 #define DTS_EXTI_LINE_DTS1           (EXTI_IMR3_IM88)  /*!< EXTI line 88 connected to DTS1 output */
00410 /**
00411   * @}
00412   */
00413 /**
00414   * @}
00415   */
00416
00417 /* Private macros ------------------------------------------------------------*/
00418 /** @defgroup DTS_Private_Macros DTS Private Macros
00419   * @{
00420   */
00421
00422 /** @defgroup DTS_IS_DTS_Definitions  DTS Private macros to check input parameters
00423   * @{
00424   */
00425 #define IS_DTS_QUICKMEAS(__SEL__)   (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
00426                                      ((__SEL__) == DTS_QUICKMEAS_ENABLE))
00427
00428 #define IS_DTS_REFCLK(__SEL__)      (((__SEL__) == DTS_REFCLKSEL_LSE) || \
00429                                      ((__SEL__) == DTS_REFCLKSEL_PCLK))
00430
00431 #define IS_DTS_TRIGGERINPUT(__INPUT__)  (((__INPUT__) == DTS_TRIGGER_HW_NONE)   || \
00432                                          ((__INPUT__) == DTS_TRIGGER_LPTIMER1)  || \
00433                                          ((__INPUT__) == DTS_TRIGGER_LPTIMER2)  || \
00434                                          ((__INPUT__) == DTS_TRIGGER_LPTIMER3)  || \
00435                                          ((__INPUT__) == DTS_TRIGGER_EXTI13))
00436
00437 #define IS_DTS_THRESHOLD(__THRESHOLD__)  ((__THRESHOLD__) <= 0xFFFFUL)
00438
00439 #define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))
00440
00441 #define IS_DTS_SAMPLINGTIME(__CYCLE__)  (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE)  || \
00442                                              ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE)    || \
00443                                              ((__CYCLE__) == DTS_SMP_TIME_3_CYCLE)    || \
00444                                              ((__CYCLE__) == DTS_SMP_TIME_4_CYCLE)    || \
00445                                              ((__CYCLE__) == DTS_SMP_TIME_5_CYCLE)    || \
00446                                              ((__CYCLE__) == DTS_SMP_TIME_6_CYCLE)    || \
00447                                              ((__CYCLE__) == DTS_SMP_TIME_7_CYCLE)    || \
00448                                              ((__CYCLE__) == DTS_SMP_TIME_8_CYCLE)    || \
00449                                              ((__CYCLE__) == DTS_SMP_TIME_9_CYCLE)    || \
00450                                              ((__CYCLE__) == DTS_SMP_TIME_10_CYCLE)   || \
00451                                              ((__CYCLE__) == DTS_SMP_TIME_11_CYCLE)   || \
00452                                              ((__CYCLE__) == DTS_SMP_TIME_12_CYCLE)   || \
00453                                              ((__CYCLE__) == DTS_SMP_TIME_13_CYCLE)   || \
00454                                              ((__CYCLE__) == DTS_SMP_TIME_14_CYCLE)   || \
00455                                              ((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
00456
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Private functions ---------------------------------------------------------*/
00466
00467 /**
00468   * @}
00469   */
00470
00471 /**
00472   * @}
00473   */
00474
00475 #endif /* DTS */
00476
00477 #ifdef __cplusplus
00478 }
00479 #endif
00480
00481 #endif /* __STM32MP1xx_HAL_COMP_H */
00482
00483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth.c Source File

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stm32h7xx_hal_eth.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth.c
00004   * @author  MCD Application Team
00005   * @brief   ETH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Ethernet (ETH) peripheral:
00008   *           + Initialization and deinitialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### How to use this driver #####
00016   ==============================================================================
00017      [..]
00018      The ETH HAL driver can be used as follows:
00019
00020       (#)Declare a ETH_HandleTypeDef handle structure, for example:
00021          ETH_HandleTypeDef  heth;
00022
00023       (#)Fill parameters of Init structure in heth handle
00024
00025       (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
00026
00027       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
00028           (##) Enable the Ethernet interface clock using
00029                 (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
00030                 (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
00031                 (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()
00032
00033           (##) Initialize the related GPIO clocks
00034           (##) Configure Ethernet pinout
00035           (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
00036
00037       (#) Ethernet data reception is asynchronous, so call the following API
00038           to start the listening mode:
00039           (##) HAL_ETH_Start():
00040                This API starts the MAC and DMA transmission and reception process,
00041                without enabling end of transfer interrupts, in this mode user
00042                has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
00043           (##) HAL_ETH_Start_IT():
00044                This API starts the MAC and DMA transmission and reception process,
00045                end of transfer interrupts are enabled in this mode,
00046                HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
00047
00048       (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
00049           occurred), user can call the following APIs to get received data:
00050           (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
00051           (##) HAL_ETH_GetRxDataLength(): Get received frame length
00052           (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
00053                please refer to ETH_RxPacketInfo typedef structure
00054
00055       (#) For transmission path, two APIs are available:
00056          (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
00057          (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
00058               HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
00059
00060       (#) Communication with an external PHY device:
00061          (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
00062          (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
00063
00064       (#) Configure the Ethernet MAC after ETH peripheral initialization
00065           (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
00066           (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
00067
00068       (#) Configure the Ethernet DMA after ETH peripheral initialization
00069           (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
00070           (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
00071
00072       -@- The PTP protocol offload APIs are not supported in this driver.
00073
00074   *** Callback registration ***
00075   =============================================
00076
00077   The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
00078   allows the user to configure dynamically the driver callbacks.
00079   Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
00080
00081   Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
00082     (+) TxCpltCallback   : Tx Complete Callback.
00083     (+) RxCpltCallback   : Rx Complete Callback.
00084     (+) DMAErrorCallback : DMA Error Callback.
00085     (+) MACErrorCallback : MAC Error Callback.
00086     (+) PMTCallback      : Power Management Callback
00087     (+) EEECallback      : EEE Callback.
00088     (+) WakeUpCallback   : Wake UP Callback
00089     (+) MspInitCallback  : MspInit Callback.
00090     (+) MspDeInitCallback: MspDeInit Callback.
00091
00092   This function takes as parameters the HAL peripheral handle, the Callback ID
00093   and a pointer to the user callback function.
00094
00095   Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
00096   weak function.
00097   @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
00098   and the Callback ID.
00099   This function allows to reset following callbacks:
00100     (+) TxCpltCallback   : Tx Complete Callback.
00101     (+) RxCpltCallback   : Rx Complete Callback.
00102     (+) DMAErrorCallback : DMA Error Callback.
00103     (+) MACErrorCallback : MAC Error Callback.
00104     (+) PMTCallback      : Power Management Callback
00105     (+) EEECallback      : EEE Callback.
00106     (+) WakeUpCallback   : Wake UP Callback
00107     (+) MspInitCallback  : MspInit Callback.
00108     (+) MspDeInitCallback: MspDeInit Callback.
00109
00110   By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
00111   all callbacks are set to the corresponding weak functions:
00112   examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
00113   Exception done for MspInit and MspDeInit functions that are
00114   reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
00115   these callbacks are null (not registered beforehand).
00116   if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
00117   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00118
00119   Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
00120   Exception done MspInit/MspDeInit that can be registered/unregistered
00121   in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
00122   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00123   In that case first register the MspInit/MspDeInit user callbacks
00124   using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
00125   or HAL_ETH_Init function.
00126
00127   When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
00128   not defined, the callback registration feature is not available and all callbacks
00129   are set to the corresponding weak functions.
00130
00131   @endverbatim
00132   ******************************************************************************
00133   * @attention
00134   *
00135   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00136   * All rights reserved.</center></h2>
00137   *
00138   * This software component is licensed by ST under BSD 3-Clause license,
00139   * the "License"; You may not use this file except in compliance with the
00140   * License. You may obtain a copy of the License at:
00141   *                        opensource.org/licenses/BSD-3-Clause
00142   *
00143   ******************************************************************************
00144   */
00145
00146 /* Includes ------------------------------------------------------------------*/
00147 #include "stm32h7xx_hal.h"
00148
00149 /** @addtogroup STM32H7xx_HAL_Driver
00150   * @{
00151   */
00152 #ifdef HAL_ETH_MODULE_ENABLED
00153
00154 #if defined(ETH)
00155
00156 /** @defgroup ETH ETH
00157   * @brief ETH HAL module driver
00158   * @{
00159   */
00160
00161 /* Private typedef -----------------------------------------------------------*/
00162 /* Private define ------------------------------------------------------------*/
00163 /** @addtogroup ETH_Private_Constants ETH Private Constants
00164   * @{
00165   */
00166 #define ETH_MACCR_MASK       ((uint32_t)0xFFFB7F7CU)
00167 #define ETH_MACECR_MASK      ((uint32_t)0x3F077FFFU)
00168 #define ETH_MACPFR_MASK      ((uint32_t)0x800007FFU)
00169 #define ETH_MACWTR_MASK      ((uint32_t)0x0000010FU)
00170 #define ETH_MACTFCR_MASK     ((uint32_t)0xFFFF00F2U)
00171 #define ETH_MACRFCR_MASK     ((uint32_t)0x00000003U)
00172 #define ETH_MTLTQOMR_MASK    ((uint32_t)0x00000072U)
00173 #define ETH_MTLRQOMR_MASK    ((uint32_t)0x0000007BU)
00174
00175 #define ETH_DMAMR_MASK       ((uint32_t)0x00007802U)
00176 #define ETH_DMASBMR_MASK     ((uint32_t)0x0000D001U)
00177 #define ETH_DMACCR_MASK      ((uint32_t)0x00013FFFU)
00178 #define ETH_DMACTCR_MASK     ((uint32_t)0x003F1010U)
00179 #define ETH_DMACRCR_MASK     ((uint32_t)0x803F0000U)
00180 #define ETH_MACPCSR_MASK     (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
00181                               ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
00182                               ETH_MACPCSR_RWKPFE)
00183
00184 /* Timeout values */
00185 #define ETH_SWRESET_TIMEOUT                 ((uint32_t)500U)
00186 #define ETH_MDIO_BUS_TIMEOUT                ((uint32_t)1000U)
00187
00188 #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
00189                                                   ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
00190                                                   ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
00191
00192 #define ETH_MAC_US_TICK               ((uint32_t)1000000U)
00193 /**
00194   * @}
00195   */
00196
00197 /* Private macros ------------------------------------------------------------*/
00198 /** @defgroup ETH_Private_Macros ETH Private Macros
00199   * @{
00200   */
00201 /* Helper macros for TX descriptor handling */
00202 #define INCR_TX_DESC_INDEX(inx, offset) do {\
00203         (inx) += (offset);\
00204           if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
00205             (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
00206 } while (0)
00207
00208 /* Helper macros for RX descriptor handling */
00209 #define INCR_RX_DESC_INDEX(inx, offset) do {\
00210         (inx) += (offset);\
00211           if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
00212             (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
00213 } while (0)
00214 /**
00215   * @}
00216   */
00217 /* Private function prototypes -----------------------------------------------*/
00218 /** @defgroup ETH_Private_Functions   ETH Private Functions
00219   * @{
00220   */
00221 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
00222 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf);
00223 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf);
00224 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
00225 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
00226 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
00227 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
00228
00229 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00230 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
00231 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
00232 /**
00233   * @}
00234   */
00235
00236 /* Exported functions ---------------------------------------------------------*/
00237 /** @defgroup ETH_Exported_Functions ETH Exported Functions
00238   * @{
00239   */
00240
00241 /** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
00242   *  @brief    Initialization and Configuration functions
00243   *
00244 @verbatim
00245 ===============================================================================
00246             ##### Initialization and Configuration functions #####
00247  ===============================================================================
00248     [..]  This subsection provides a set of functions allowing to initialize and
00249           deinitialize the ETH peripheral:
00250
00251       (+) User must Implement HAL_ETH_MspInit() function in which he configures
00252           all related peripherals resources (CLOCK, GPIO and NVIC ).
00253
00254       (+) Call the function HAL_ETH_Init() to configure the selected device with
00255           the selected configuration:
00256         (++) MAC address
00257         (++) Media interface (MII or RMII)
00258         (++) Rx DMA Descriptors Tab
00259         (++) Tx DMA Descriptors Tab
00260         (++) Length of Rx Buffers
00261
00262       (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
00263           for each Rx DMA Descriptor
00264
00265       (+) Call the function HAL_ETH_DeInit() to restore the default configuration
00266           of the selected ETH peripheral.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Initialize the Ethernet peripheral registers.
00274   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00275   *         the configuration information for ETHERNET module
00276   * @retval HAL status
00277   */
00278 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
00279 {
00280   uint32_t tickstart;
00281
00282   if(heth == NULL)
00283   {
00284     return HAL_ERROR;
00285   }
00286
00287 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00288
00289   if(heth->gState == HAL_ETH_STATE_RESET)
00290   {
00291     /* Allocate lock resource and initialize it */
00292     heth->Lock = HAL_UNLOCKED;
00293
00294     ETH_InitCallbacksToDefault(heth);
00295
00296     if(heth->MspInitCallback == NULL)
00297     {
00298       heth->MspInitCallback = HAL_ETH_MspInit;
00299     }
00300
00301     /* Init the low level hardware */
00302     heth->MspInitCallback(heth);
00303   }
00304
00305 #else
00306
00307   /* Check the ETH peripheral state */
00308   if(heth->gState == HAL_ETH_STATE_RESET)
00309   {
00310     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
00311     HAL_ETH_MspInit(heth);
00312   }
00313 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
00314
00315   heth->gState = HAL_ETH_STATE_BUSY;
00316
00317   __HAL_RCC_SYSCFG_CLK_ENABLE();
00318
00319   if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
00320   {
00321     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
00322   }
00323   else
00324   {
00325     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
00326   }
00327
00328   /* Ethernet Software reset */
00329   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
00330   /* After reset all the registers holds their respective reset values */
00331   SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
00332
00333   /* Get tick */
00334   tickstart = HAL_GetTick();
00335
00336   /* Wait for software reset */
00337   while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
00338   {
00339     if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
00340     {
00341       /* Set Error Code */
00342       heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
00343       /* Set State as Error */
00344       heth->gState = HAL_ETH_STATE_ERROR;
00345       /* Return Error */
00346       return HAL_ERROR;
00347     }
00348   }
00349
00350   /*------------------ MDIO CSR Clock Range Configuration --------------------*/
00351   ETH_MAC_MDIO_ClkConfig(heth);
00352
00353   /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
00354   WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
00355
00356   /*------------------ MAC, MTL and DMA default Configuration ----------------*/
00357   ETH_MACDMAConfig(heth);
00358
00359   /* SET DSL to 64 bit */
00360   MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
00361
00362   /* Set Receive Buffers Length (must be a multiple of 4) */
00363   if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
00364   {
00365     /* Set Error Code */
00366     heth->ErrorCode = HAL_ETH_ERROR_PARAM;
00367     /* Set State as Error */
00368     heth->gState = HAL_ETH_STATE_ERROR;
00369     /* Return Error */
00370     return HAL_ERROR;
00371   }
00372   else
00373   {
00374     MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
00375   }
00376
00377   /*------------------ DMA Tx Descriptors Configuration ----------------------*/
00378   ETH_DMATxDescListInit(heth);
00379
00380   /*------------------ DMA Rx Descriptors Configuration ----------------------*/
00381   ETH_DMARxDescListInit(heth);
00382
00383   /*--------------------- ETHERNET MAC Address Configuration ------------------*/
00384   /* Set MAC addr bits 32 to 47 */
00385   heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
00386   /* Set MAC addr bits 0 to 31 */
00387   heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
00388                              ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
00389
00390   heth->ErrorCode = HAL_ETH_ERROR_NONE;
00391   heth->gState = HAL_ETH_STATE_READY;
00392   heth->RxState = HAL_ETH_STATE_READY;
00393
00394   return HAL_OK;
00395 }
00396
00397 /**
00398   * @brief  DeInitializes the ETH peripheral.
00399   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00400   *         the configuration information for ETHERNET module
00401   * @retval HAL status
00402   */
00403 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
00404 {
00405   /* Set the ETH peripheral state to BUSY */
00406   heth->gState = HAL_ETH_STATE_BUSY;
00407
00408 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00409
00410   if(heth->MspDeInitCallback == NULL)
00411   {
00412     heth->MspDeInitCallback = HAL_ETH_MspDeInit;
00413   }
00414   /* DeInit the low level hardware */
00415   heth->MspDeInitCallback(heth);
00416 #else
00417
00418   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
00419   HAL_ETH_MspDeInit(heth);
00420
00421 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
00422
00423   /* Set ETH HAL state to Disabled */
00424   heth->gState= HAL_ETH_STATE_RESET;
00425
00426   /* Return function status */
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Initializes the ETH MSP.
00432   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00433   *         the configuration information for ETHERNET module
00434   * @retval None
00435   */
00436 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
00437 {
00438   /* Prevent unused argument(s) compilation warning */
00439   UNUSED(heth);
00440   /* NOTE : This function Should not be modified, when the callback is needed,
00441   the HAL_ETH_MspInit could be implemented in the user file
00442   */
00443 }
00444
00445 /**
00446   * @brief  DeInitializes ETH MSP.
00447   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00448   *         the configuration information for ETHERNET module
00449   * @retval None
00450   */
00451 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(heth);
00455   /* NOTE : This function Should not be modified, when the callback is needed,
00456   the HAL_ETH_MspDeInit could be implemented in the user file
00457   */
00458 }
00459
00460 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00461 /**
00462   * @brief  Register a User ETH Callback
00463   *         To be used instead of the weak predefined callback
00464   * @param heth eth handle
00465   * @param CallbackID ID of the callback to be registered
00466   *        This parameter can be one of the following values:
00467   *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
00468   *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
00469   *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
00470   *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
00471   *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
00472   *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
00473   *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
00474   *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
00475   *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
00476   * @param pCallback pointer to the Callback function
00477   * @retval status
00478   */
00479 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
00480 {
00481   HAL_StatusTypeDef status = HAL_OK;
00482
00483   if(pCallback == NULL)
00484   {
00485     /* Update the error code */
00486     heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00487
00488     return HAL_ERROR;
00489   }
00490   /* Process locked */
00491   __HAL_LOCK(heth);
00492
00493   if(heth->gState == HAL_ETH_STATE_READY)
00494   {
00495     switch (CallbackID)
00496     {
00497     case HAL_ETH_TX_COMPLETE_CB_ID :
00498       heth->TxCpltCallback = pCallback;
00499       break;
00500
00501     case HAL_ETH_RX_COMPLETE_CB_ID :
00502       heth->RxCpltCallback = pCallback;
00503       break;
00504
00505     case HAL_ETH_DMA_ERROR_CB_ID :
00506       heth->DMAErrorCallback = pCallback;
00507       break;
00508
00509     case HAL_ETH_MAC_ERROR_CB_ID :
00510       heth->MACErrorCallback = pCallback;
00511       break;
00512
00513     case HAL_ETH_PMT_CB_ID :
00514       heth->PMTCallback = pCallback;
00515       break;
00516
00517     case HAL_ETH_EEE_CB_ID :
00518       heth->EEECallback = pCallback;
00519       break;
00520
00521     case HAL_ETH_WAKEUP_CB_ID :
00522       heth->WakeUpCallback = pCallback;
00523       break;
00524
00525     case HAL_ETH_MSPINIT_CB_ID :
00526       heth->MspInitCallback = pCallback;
00527       break;
00528
00529    case HAL_ETH_MSPDEINIT_CB_ID :
00530       heth->MspDeInitCallback = pCallback;
00531       break;
00532
00533     default :
00534       /* Update the error code */
00535       heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00536       /* Return error status */
00537       status =  HAL_ERROR;
00538       break;
00539     }
00540   }
00541   else if(heth->gState == HAL_ETH_STATE_RESET)
00542   {
00543     switch (CallbackID)
00544     {
00545     case HAL_ETH_MSPINIT_CB_ID :
00546       heth->MspInitCallback = pCallback;
00547       break;
00548
00549    case HAL_ETH_MSPDEINIT_CB_ID :
00550       heth->MspDeInitCallback = pCallback;
00551       break;
00552
00553     default :
00554       /* Update the error code */
00555       heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00556      /* Return error status */
00557       status =  HAL_ERROR;
00558       break;
00559     }
00560   }
00561   else
00562   {
00563     /* Update the error code */
00564     heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00565     /* Return error status */
00566     status =  HAL_ERROR;
00567   }
00568
00569   /* Release Lock */
00570   __HAL_UNLOCK(heth);
00571
00572   return status;
00573 }
00574
00575 /**
00576   * @brief  Unregister an ETH Callback
00577   *         ETH callabck is redirected to the weak predefined callback
00578   * @param heth eth handle
00579   * @param CallbackID ID of the callback to be unregistered
00580   *        This parameter can be one of the following values:
00581   *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
00582   *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
00583   *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
00584   *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
00585   *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
00586   *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
00587   *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
00588   *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
00589   *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
00590   * @retval status
00591   */
00592 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
00593 {
00594   HAL_StatusTypeDef status = HAL_OK;
00595
00596   /* Process locked */
00597   __HAL_LOCK(heth);
00598
00599   if(heth->gState == HAL_ETH_STATE_READY)
00600   {
00601     switch (CallbackID)
00602     {
00603     case HAL_ETH_TX_COMPLETE_CB_ID :
00604       heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
00605       break;
00606
00607     case HAL_ETH_RX_COMPLETE_CB_ID :
00608       heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
00609       break;
00610
00611     case HAL_ETH_DMA_ERROR_CB_ID :
00612       heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
00613       break;
00614
00615     case HAL_ETH_MAC_ERROR_CB_ID :
00616       heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
00617       break;
00618
00619     case HAL_ETH_PMT_CB_ID :
00620       heth->PMTCallback = HAL_ETH_PMTCallback;
00621       break;
00622
00623     case HAL_ETH_EEE_CB_ID :
00624       heth->EEECallback = HAL_ETH_EEECallback;
00625       break;
00626
00627     case HAL_ETH_WAKEUP_CB_ID :
00628       heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
00629       break;
00630
00631     case HAL_ETH_MSPINIT_CB_ID :
00632       heth->MspInitCallback = HAL_ETH_MspInit;
00633       break;
00634
00635    case HAL_ETH_MSPDEINIT_CB_ID :
00636       heth->MspDeInitCallback = HAL_ETH_MspDeInit;
00637       break;
00638
00639     default :
00640       /* Update the error code */
00641       heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00642      /* Return error status */
00643       status =  HAL_ERROR;
00644       break;
00645     }
00646   }
00647   else if(heth->gState == HAL_ETH_STATE_RESET)
00648   {
00649     switch (CallbackID)
00650     {
00651     case HAL_ETH_MSPINIT_CB_ID :
00652       heth->MspInitCallback = HAL_ETH_MspInit;
00653       break;
00654
00655    case HAL_ETH_MSPDEINIT_CB_ID :
00656       heth->MspDeInitCallback = HAL_ETH_MspDeInit;
00657       break;
00658
00659     default :
00660       /* Update the error code */
00661       heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00662      /* Return error status */
00663       status =  HAL_ERROR;
00664       break;
00665     }
00666   }
00667   else
00668   {
00669     /* Update the error code */
00670     heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
00671     /* Return error status */
00672     status =  HAL_ERROR;
00673   }
00674
00675   /* Release Lock */
00676   __HAL_UNLOCK(heth);
00677
00678   return status;
00679 }
00680 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
00681
00682 /**
00683   * @brief  Assign memory buffers to a DMA Rx descriptor
00684   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00685   *         the configuration information for ETHERNET module
00686   * @param  Index : index of the DMA Rx descriptor
00687   *                  this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
00688   * @param  pBuffer1: address of buffer 1
00689   * @param  pBuffer2: address of buffer 2 if available
00690   * @retval HAL status
00691   */
00692 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
00693 {
00694   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
00695
00696   if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
00697   {
00698     /* Set Error Code */
00699     heth->ErrorCode = HAL_ETH_ERROR_PARAM;
00700     /* Return Error */
00701     return HAL_ERROR;
00702   }
00703
00704   /* write buffer address to RDES0 */
00705   WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
00706   /* store buffer address */
00707   WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
00708   /* set buffer address valid bit to RDES3 */
00709   SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
00710
00711   if(pBuffer2 != NULL)
00712   {
00713     /* write buffer 2 address to RDES1 */
00714     WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
00715      /* store buffer 2 address */
00716     WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
00717     /* set buffer 2 address valid bit to RDES3 */
00718     SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
00719   }
00720   /* set OWN bit to RDES3 */
00721   SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
00722
00723   return HAL_OK;
00724 }
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
00731   *  @brief ETH Transmit and Receive functions
00732   *
00733 @verbatim
00734   ==============================================================================
00735                       ##### IO operation functions #####
00736   ==============================================================================
00737   [..]
00738     This subsection provides a set of functions allowing to manage the ETH
00739     data transfer.
00740
00741 @endverbatim
00742   * @{
00743   */
00744
00745 /**
00746   * @brief  Enables Ethernet MAC and DMA reception and transmission
00747   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00748   *         the configuration information for ETHERNET module
00749   * @retval HAL status
00750   */
00751 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
00752 {
00753   if(heth->gState == HAL_ETH_STATE_READY)
00754   {
00755     heth->gState = HAL_ETH_STATE_BUSY;
00756
00757     /* Enable the MAC transmission */
00758     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00759
00760     /* Enable the MAC reception */
00761     SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
00762
00763     /* Set the Flush Transmit FIFO bit */
00764     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00765
00766     /* Enable the DMA transmission */
00767     SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00768
00769     /* Enable the DMA reception */
00770     SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00771
00772     /* Clear Tx and Rx process stopped flags */
00773     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
00774
00775     heth->gState = HAL_ETH_STATE_READY;
00776     heth->RxState = HAL_ETH_STATE_BUSY_RX;
00777
00778     return HAL_OK;
00779   }
00780   else
00781   {
00782     return HAL_ERROR;
00783   }
00784 }
00785
00786 /**
00787   * @brief  Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
00788   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00789   *         the configuration information for ETHERNET module
00790   * @retval HAL status
00791   */
00792 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
00793 {
00794   uint32_t descindex = 0, counter;
00795   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
00796
00797   if(heth->gState == HAL_ETH_STATE_READY)
00798   {
00799     heth->gState = HAL_ETH_STATE_BUSY;
00800
00801     /* Set IOC bit to all Rx descriptors */
00802     for(counter= 0; counter < (uint32_t)ETH_RX_DESC_CNT; counter++)
00803     {
00804       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
00805       INCR_RX_DESC_INDEX(descindex, 1U);
00806       dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
00807     }
00808
00809     /* save IT mode to ETH Handle */
00810     heth->RxDescList.ItMode = 1U;
00811
00812     /* Enable the MAC transmission */
00813     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00814
00815     /* Enable the MAC reception */
00816     SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
00817
00818     /* Set the Flush Transmit FIFO bit */
00819     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00820
00821     /* Enable the DMA transmission */
00822     SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00823
00824     /* Enable the DMA reception */
00825     SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00826
00827     /* Clear Tx and Rx process stopped flags */
00828     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
00829
00830     heth->gState = HAL_ETH_STATE_READY;
00831     heth->RxState = HAL_ETH_STATE_BUSY_RX;
00832
00833     /* Enable ETH DMA interrupts:
00834     - Tx complete interrupt
00835     - Rx complete interrupt
00836     - Fatal bus interrupt
00837     */
00838     __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
00839                                    ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
00840
00841     return HAL_OK;
00842   }
00843   else
00844   {
00845     return HAL_ERROR;
00846   }
00847 }
00848
00849 /**
00850   * @brief  Stop Ethernet MAC and DMA reception/transmission
00851   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00852   *         the configuration information for ETHERNET module
00853   * @retval HAL status
00854   */
00855 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
00856 {
00857   if(heth->gState != HAL_ETH_STATE_RESET)
00858   {
00859      /* Set the ETH peripheral state to BUSY */
00860     heth->gState = HAL_ETH_STATE_BUSY;
00861
00862     /* Disable the DMA transmission */
00863     CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00864
00865     /* Disable the DMA reception */
00866     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00867
00868     /* Disable the MAC reception */
00869     CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
00870
00871     /* Set the Flush Transmit FIFO bit */
00872     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00873
00874     /* Disable the MAC transmission */
00875     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00876
00877     heth->gState = HAL_ETH_STATE_READY;
00878     heth->RxState = HAL_ETH_STATE_READY;
00879
00880     /* Return function status */
00881     return HAL_OK;
00882   }
00883   else
00884   {
00885     return HAL_ERROR;
00886   }
00887 }
00888
00889 /**
00890   * @brief  Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
00891   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00892   *         the configuration information for ETHERNET module
00893   * @retval HAL status
00894   */
00895 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
00896 {
00897   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
00898   uint32_t index;
00899
00900   if(heth->gState != HAL_ETH_STATE_RESET)
00901   {
00902     /* Set the ETH peripheral state to BUSY */
00903     heth->gState = HAL_ETH_STATE_BUSY;
00904
00905     /* Disable intrrupts:
00906     - Tx complete interrupt
00907     - Rx complete interrupt     */
00908     __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
00909
00910     /* Disable the DMA transmission */
00911     CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00912
00913     /* Disable the DMA reception */
00914     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00915
00916     /* Disable the MAC reception */
00917     CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
00918
00919     /* Set the Flush Transmit FIFO bit */
00920     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00921
00922     /* Disable the MAC transmission */
00923     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00924
00925     /* Clear IOC bit to all Rx descriptors */
00926     for(index = 0; index < (uint32_t)ETH_RX_DESC_CNT; index++)
00927     {
00928       CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
00929     }
00930
00931     heth->RxDescList.ItMode = 0U;
00932
00933     heth->gState = HAL_ETH_STATE_READY;
00934     heth->RxState = HAL_ETH_STATE_READY;
00935
00936     /* Return function status */
00937     return HAL_OK;
00938   }
00939   else
00940   {
00941     return HAL_ERROR;
00942   }
00943 }
00944
00945 /**
00946   * @brief  Sends an Ethernet Packet in polling mode.
00947   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00948   *         the configuration information for ETHERNET module
00949   * @param  pTxConfig: Hold the configuration of packet to be transmitted
00950   * @param  Timeout: timeout value
00951   * @retval HAL status
00952   */
00953 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
00954 {
00955   uint32_t tickstart;
00956   const ETH_DMADescTypeDef *dmatxdesc;
00957
00958   if(pTxConfig == NULL)
00959   {
00960     heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
00961     return HAL_ERROR;
00962   }
00963
00964   if(heth->gState == HAL_ETH_STATE_READY)
00965   {
00966     /* Config DMA Tx descriptor by Tx Packet info */
00967     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
00968     {
00969       /* Set the ETH error code */
00970       heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
00971       return HAL_ERROR;
00972     }
00973
00974     dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
00975
00976     /* Incr current tx desc index */
00977     INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
00978
00979     /* Start transmission */
00980     /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
00981     WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
00982
00983     tickstart = HAL_GetTick();
00984
00985     /* Wait for data to be transmitted or timeout occured */
00986     while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
00987     {
00988       if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
00989       {
00990         heth->ErrorCode |= HAL_ETH_ERROR_DMA;
00991         heth->DMAErrorCode = heth->Instance->DMACSR;
00992         /* Set ETH HAL State to Ready */
00993         heth->gState = HAL_ETH_STATE_ERROR;
00994         /* Return function status */
00995         return HAL_ERROR;
00996       }
00997
00998       /* Check for the Timeout */
00999       if(Timeout != HAL_MAX_DELAY)
01000       {
01001         if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
01002         {
01003           heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
01004           heth->gState = HAL_ETH_STATE_READY;
01005           return HAL_ERROR;
01006         }
01007       }
01008     }
01009
01010     /* Set ETH HAL State to Ready */
01011     heth->gState = HAL_ETH_STATE_READY;
01012
01013     /* Return function status */
01014     return HAL_OK;
01015   }
01016   else
01017   {
01018     return HAL_ERROR;
01019   }
01020 }
01021
01022 /**
01023   * @brief  Sends an Ethernet Packet in interrupt mode.
01024   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01025   *         the configuration information for ETHERNET module
01026   * @param  pTxConfig: Hold the configuration of packet to be transmitted
01027   * @retval HAL status
01028   */
01029 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
01030 {
01031   if(pTxConfig == NULL)
01032   {
01033     return HAL_ERROR;
01034   }
01035
01036   if(heth->gState == HAL_ETH_STATE_READY)
01037   {
01038     /* Config DMA Tx descriptor by Tx Packet info */
01039     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
01040     {
01041       heth->ErrorCode = HAL_ETH_ERROR_BUSY;
01042       return HAL_ERROR;
01043     }
01044
01045     /* Incr current tx desc index */
01046     INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
01047
01048     /* Start transmission */
01049     /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
01050     WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
01051
01052     return HAL_OK;
01053
01054   }
01055   else
01056   {
01057     return HAL_ERROR;
01058   }
01059 }
01060
01061 /**
01062   * @brief  Checks for received Packets.
01063   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01064   *         the configuration information for ETHERNET module
01065   * @retval  1: A Packet is received
01066   *          0: no Packet received
01067   */
01068 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
01069 {
01070   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01071   uint32_t descidx = dmarxdesclist->CurRxDesc;
01072   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01073   uint32_t descscancnt = 0;
01074   uint32_t appdesccnt = 0, firstappdescidx = 0;
01075
01076   if(dmarxdesclist->AppDescNbr != 0U)
01077   {
01078     /* data already received by not yet processed*/
01079     return 0;
01080   }
01081
01082   /* Check if descriptor is not owned by DMA */
01083   while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
01084   {
01085     descscancnt++;
01086
01087     /* Check if last descriptor */
01088     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
01089     {
01090       /* Increment the number of descriptors to be passed to the application */
01091       appdesccnt += 1U;
01092
01093       if(appdesccnt == 1U)
01094       {
01095         WRITE_REG(firstappdescidx, descidx);
01096       }
01097
01098       /* Increment current rx descriptor index */
01099       INCR_RX_DESC_INDEX(descidx, 1U);
01100
01101       /* Check for Context descriptor */
01102       /* Get current descriptor address */
01103       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01104
01105       if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_OWN)  == (uint32_t)RESET)
01106       {
01107         if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
01108         {
01109           /* Increment the number of descriptors to be passed to the application */
01110           dmarxdesclist->AppContextDesc = 1;
01111           /* Increment current rx descriptor index */
01112           INCR_RX_DESC_INDEX(descidx, 1U);
01113         }
01114       }
01115       /* Fill information to Rx descriptors list */
01116       dmarxdesclist->CurRxDesc = descidx;
01117       dmarxdesclist->FirstAppDesc = firstappdescidx;
01118       dmarxdesclist->AppDescNbr = appdesccnt;
01119
01120       /* Return function status */
01121       return 1;
01122     }
01123     /* Check if first descriptor */
01124     else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
01125     {
01126       WRITE_REG(firstappdescidx, descidx);
01127       /* Increment the number of descriptors to be passed to the application */
01128       appdesccnt = 1U;
01129
01130       /* Increment current rx descriptor index */
01131       INCR_RX_DESC_INDEX(descidx, 1U);
01132       /* Get current descriptor address */
01133       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01134     }
01135     /* It should be an intermediate descriptor */
01136     else
01137     {
01138       /* Increment the number of descriptors to be passed to the application */
01139       appdesccnt += 1U;
01140
01141       /* Increment current rx descriptor index */
01142       INCR_RX_DESC_INDEX(descidx, 1U);
01143       /* Get current descriptor address */
01144       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01145     }
01146   }
01147
01148   /* Build Descriptors if an incomplete Packet is received */
01149   if(appdesccnt > 0U)
01150   {
01151     descidx = firstappdescidx;
01152     dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01153
01154     for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
01155     {
01156       WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
01157       WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
01158
01159       if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
01160       {
01161         WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
01162         SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
01163       }
01164
01165       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
01166
01167       if(dmarxdesclist->ItMode != ((uint32_t)RESET))
01168       {
01169         SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
01170       }
01171
01172       /* Increment rx descriptor index */
01173       INCR_RX_DESC_INDEX(descidx, 1U);
01174       /* Get descriptor address */
01175       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01176     }
01177   }
01178
01179   /* Fill information to Rx descriptors list: No received Packet */
01180   dmarxdesclist->AppDescNbr = 0U;
01181
01182   return 0;
01183 }
01184
01185 /**
01186   * @brief  This function gets the buffer address of last received Packet.
01187   * @note   Please insure to allocate the RxBuffer structure before calling this function
01188   *         how to use example:
01189   *           HAL_ETH_GetRxDataLength(heth, &Length);
01190   *           BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
01191   *           RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
01192   *           HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
01193   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01194   *         the configuration information for ETHERNET module
01195   * @param  RxBuffer: Pointer to a ETH_BufferTypeDef structure
01196   * @retval HAL status
01197   */
01198 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
01199 {
01200   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01201   uint32_t descidx = dmarxdesclist->FirstAppDesc;
01202   uint32_t index, accumulatedlen = 0, lastdesclen;
01203   __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01204   ETH_BufferTypeDef *rxbuff = RxBuffer;
01205
01206   if(rxbuff == NULL)
01207   {
01208     heth->ErrorCode = HAL_ETH_ERROR_PARAM;
01209     return HAL_ERROR;
01210   }
01211
01212   if(dmarxdesclist->AppDescNbr == 0U)
01213   {
01214     if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
01215     {
01216       /* No data to be transferred to the application */
01217       return HAL_ERROR;
01218     }
01219     else
01220     {
01221       descidx = dmarxdesclist->FirstAppDesc;
01222       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01223     }
01224   }
01225
01226   /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
01227   for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
01228   {
01229     /* Get Address and length of the first buffer address */
01230     rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
01231     rxbuff->len =  heth->Init.RxBuffLen;
01232
01233     /* Check if the second buffer address of this descriptor is valid */
01234     if(dmarxdesc->BackupAddr1 != 0U)
01235     {
01236       /* Point to next buffer */
01237       rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
01238       /* Get Address and length of the second buffer address */
01239       rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
01240       rxbuff->len =  heth->Init.RxBuffLen;
01241     }
01242     else
01243     {
01244       /* Nothing to do here */
01245     }
01246
01247     /* get total length until this descriptor */
01248     accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
01249
01250     /* Increment to next descriptor */
01251     INCR_RX_DESC_INDEX(descidx, 1U);
01252     dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01253
01254     /* Point to next buffer */
01255     rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
01256   }
01257
01258   /* last descriptor data length */
01259   lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
01260
01261   /* Get Address of the first buffer address */
01262   rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
01263
01264   /* data is in only one buffer */
01265   if(lastdesclen <= heth->Init.RxBuffLen)
01266   {
01267     rxbuff->len = lastdesclen;
01268   }
01269   /* data is in two buffers */
01270   else if(dmarxdesc->BackupAddr1 != 0U)
01271   {
01272     /* Get the Length of the first buffer address */
01273     rxbuff->len = heth->Init.RxBuffLen;
01274     /* Point to next buffer */
01275     rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
01276     /* Get the Address the Length of the second buffer address */
01277     rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
01278     rxbuff->len =  lastdesclen - (heth->Init.RxBuffLen);
01279   }
01280   else /* Buffer 2 not valid*/
01281   {
01282     return HAL_ERROR;
01283   }
01284
01285   return HAL_OK;
01286 }
01287
01288 /**
01289   * @brief  This function gets the length of last received Packet.
01290   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01291   *         the configuration information for ETHERNET module
01292   * @param  Length: parameter to hold Rx packet length
01293   * @retval HAL Status
01294   */
01295 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
01296 {
01297   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01298   uint32_t descidx = dmarxdesclist->FirstAppDesc;
01299   __IO const ETH_DMADescTypeDef *dmarxdesc;
01300
01301   if(dmarxdesclist->AppDescNbr == 0U)
01302   {
01303     if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
01304     {
01305       /* No data to be transferred to the application */
01306       return HAL_ERROR;
01307     }
01308   }
01309
01310   /* Get index of last descriptor */
01311   INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
01312   /* Point to last descriptor */
01313   dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01314
01315   *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
01316
01317   return HAL_OK;
01318 }
01319
01320 /**
01321   * @brief  Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
01322   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01323   *         the configuration information for ETHERNET module
01324   * @param  RxPacketInfo: parameter to hold info of received buffer
01325   * @retval HAL status
01326   */
01327 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
01328 {
01329   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01330   uint32_t descidx = dmarxdesclist->FirstAppDesc;
01331   __IO const ETH_DMADescTypeDef *dmarxdesc;
01332
01333   if(dmarxdesclist->AppDescNbr == 0U)
01334   {
01335     if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
01336     {
01337       /* No data to be transferred to the application */
01338       return HAL_ERROR;
01339     }
01340   }
01341
01342   /* Get index of last descriptor */
01343   INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
01344   /* Point to last descriptor */
01345   dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01346
01347   if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
01348   {
01349     RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
01350   }
01351   else
01352   {
01353     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
01354     {
01355
01356       if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
01357       {
01358         RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
01359         RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
01360       }
01361       else
01362       {
01363         RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
01364       }
01365     }
01366
01367     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
01368     {
01369       /* Get Payload type */
01370       RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
01371       /* Get Header type */
01372       RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
01373       /* Get Checksum status */
01374       RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
01375     }
01376
01377     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
01378     {
01379       RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
01380       RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2,  (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
01381       RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
01382     }
01383   }
01384
01385   /* Get the segment count */
01386   WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
01387
01388   return HAL_OK;
01389 }
01390
01391 /**
01392 * @brief  This function gives back Rx Desc of the last received Packet
01393 *         to the DMA, so ETH DMA will be able to use these descriptors
01394 *         to receive next Packets.
01395 *         It should be called after processing the received Packet.
01396 * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01397 *         the configuration information for ETHERNET module
01398 * @retval HAL status.
01399 */
01400 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
01401 {
01402   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01403   uint32_t descindex = dmarxdesclist->FirstAppDesc;
01404   __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
01405   uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
01406   uint32_t descscan;
01407
01408   if(dmarxdesclist->AppDescNbr == 0U)
01409   {
01410     /* No Rx descriptors to build */
01411     return HAL_ERROR;
01412   }
01413
01414   if(dmarxdesclist->AppContextDesc != 0U)
01415   {
01416     /* A context descriptor is available */
01417     totalappdescnbr += 1U;
01418   }
01419
01420   for(descscan =0; descscan < totalappdescnbr; descscan++)
01421   {
01422     WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
01423     WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
01424
01425     if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
01426     {
01427       WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
01428       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
01429     }
01430
01431     SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
01432
01433     if(dmarxdesclist->ItMode != 0U)
01434     {
01435       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
01436     }
01437
01438     if(descscan < (dmarxdesclist->AppDescNbr - 1U))
01439     {
01440       /* Increment rx descriptor index */
01441       INCR_RX_DESC_INDEX(descindex, 1U);
01442       /* Get descriptor address */
01443       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
01444     }
01445   }
01446
01447   /* Set the Tail pointer address to the last rx descriptor hold by the app */
01448   WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
01449
01450   /* reset the Application desc number */
01451   WRITE_REG(dmarxdesclist->AppDescNbr, 0);
01452
01453   return HAL_OK;
01454 }
01455
01456
01457 /**
01458   * @brief  This function handles ETH interrupt request.
01459   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01460   *         the configuration information for ETHERNET module
01461   * @retval HAL status
01462   */
01463 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
01464 {
01465   /* Packet received */
01466   if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
01467   {
01468     if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
01469     {
01470
01471 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01472       /*Call registered Receive complete callback*/
01473       heth->RxCpltCallback(heth);
01474 #else
01475       /* Receive complete callback */
01476       HAL_ETH_RxCpltCallback(heth);
01477 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01478
01479       /* Clear the Eth DMA Rx IT pending bits */
01480       __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
01481     }
01482   }
01483
01484   /* Packet transmitted */
01485   if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
01486   {
01487     if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
01488     {
01489 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01490         /*Call registered Transmit complete callback*/
01491         heth->TxCpltCallback(heth);
01492 #else
01493       /* Transfer complete callback */
01494       HAL_ETH_TxCpltCallback(heth);
01495 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01496
01497       /* Clear the Eth DMA Tx IT pending bits */
01498       __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
01499     }
01500   }
01501
01502
01503   /* ETH DMA Error */
01504   if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
01505   {
01506     if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
01507     {
01508       heth->ErrorCode |= HAL_ETH_ERROR_DMA;
01509
01510       /* if fatal bus error occured */
01511       if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
01512       {
01513         /* Get DMA error code  */
01514         heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
01515
01516         /* Disable all interrupts */
01517         __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
01518
01519         /* Set HAL state to ERROR */
01520         heth->gState = HAL_ETH_STATE_ERROR;
01521       }
01522       else
01523       {
01524         /* Get DMA error status  */
01525        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
01526                                                        ETH_DMACSR_RBU | ETH_DMACSR_AIS));
01527
01528         /* Clear the interrupt summary flag */
01529         __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
01530                                     ETH_DMACSR_RBU | ETH_DMACSR_AIS));
01531       }
01532 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01533       /* Call registered DMA Error callback*/
01534       heth->DMAErrorCallback(heth);
01535 #else
01536       /* Ethernet DMA Error callback */
01537       HAL_ETH_DMAErrorCallback(heth);
01538 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01539
01540     }
01541   }
01542
01543   /* ETH MAC Error IT */
01544   if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
01545   {
01546     /* Get MAC Rx Tx status and clear Status register pending bit */
01547     heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
01548
01549     heth->gState = HAL_ETH_STATE_ERROR;
01550
01551 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01552     /* Call registered MAC Error callback*/
01553     heth->DMAErrorCallback(heth);
01554 #else
01555     /* Ethernet MAC Error callback */
01556     HAL_ETH_MACErrorCallback(heth);
01557 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01558
01559     heth->MACErrorCode = (uint32_t)(0x0U);
01560   }
01561
01562   /* ETH PMT IT */
01563   if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
01564   {
01565     /* Get MAC Wake-up source and clear the status register pending bit */
01566     heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
01567
01568 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01569     /* Call registered PMT callback*/
01570     heth->PMTCallback(heth);
01571 #else
01572     /* Ethernet PMT callback */
01573     HAL_ETH_PMTCallback(heth);
01574 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01575
01576     heth->MACWakeUpEvent = (uint32_t)(0x0U);
01577   }
01578
01579   /* ETH EEE IT */
01580   if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
01581   {
01582     /* Get MAC LPI interrupt source and clear the status register pending bit */
01583     heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
01584
01585 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01586     /* Call registered EEE callback*/
01587     heth->EEECallback(heth);
01588 #else
01589     /* Ethernet EEE callback */
01590     HAL_ETH_EEECallback(heth);
01591 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
01592
01593     heth->MACLPIEvent = (uint32_t)(0x0U);
01594   }
01595
01596 #if defined(DUAL_CORE)
01597   if (HAL_GetCurrentCPUID() == CM7_CPUID)
01598   {
01599     /* check ETH WAKEUP exti flag */
01600     if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
01601     {
01602       /* Clear ETH WAKEUP Exti pending bit */
01603       __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
01604 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01605       /* Call registered WakeUp callback*/
01606       heth->WakeUpCallback(heth);
01607 #else
01608       /* ETH WAKEUP callback */
01609       HAL_ETH_WakeUpCallback(heth);
01610 #endif
01611     }
01612   }
01613   else
01614   {
01615     /* check ETH WAKEUP exti flag */
01616     if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
01617     {
01618       /* Clear ETH WAKEUP Exti pending bit */
01619       __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
01620 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01621       /* Call registered WakeUp callback*/
01622       heth->WakeUpCallback(heth);
01623 #else
01624       /* ETH WAKEUP callback */
01625       HAL_ETH_WakeUpCallback(heth);
01626 #endif
01627     }
01628   }
01629 #else
01630   /* check ETH WAKEUP exti flag */
01631   if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
01632   {
01633     /* Clear ETH WAKEUP Exti pending bit */
01634     __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
01635 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01636       /* Call registered WakeUp callback*/
01637       heth->WakeUpCallback(heth);
01638 #else
01639       /* ETH WAKEUP callback */
01640       HAL_ETH_WakeUpCallback(heth);
01641 #endif
01642   }
01643 #endif
01644 }
01645
01646 /**
01647   * @brief  Tx Transfer completed callbacks.
01648   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01649   *         the configuration information for ETHERNET module
01650   * @retval None
01651   */
01652 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
01653 {
01654   /* Prevent unused argument(s) compilation warning */
01655   UNUSED(heth);
01656   /* NOTE : This function Should not be modified, when the callback is needed,
01657   the HAL_ETH_TxCpltCallback could be implemented in the user file
01658   */
01659 }
01660
01661 /**
01662   * @brief  Rx Transfer completed callbacks.
01663   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01664   *         the configuration information for ETHERNET module
01665   * @retval None
01666   */
01667 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
01668 {
01669   /* Prevent unused argument(s) compilation warning */
01670   UNUSED(heth);
01671   /* NOTE : This function Should not be modified, when the callback is needed,
01672   the HAL_ETH_RxCpltCallback could be implemented in the user file
01673   */
01674 }
01675
01676 /**
01677   * @brief  Ethernet DMA transfer error callbacks
01678   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01679   *         the configuration information for ETHERNET module
01680   * @retval None
01681   */
01682 __weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
01683 {
01684   /* Prevent unused argument(s) compilation warning */
01685   UNUSED(heth);
01686   /* NOTE : This function Should not be modified, when the callback is needed,
01687   the HAL_ETH_DMAErrorCallback could be implemented in the user file
01688   */
01689 }
01690
01691 /**
01692 * @brief  Ethernet MAC transfer error callbacks
01693   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01694   *         the configuration information for ETHERNET module
01695   * @retval None
01696   */
01697 __weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
01698 {
01699   /* Prevent unused argument(s) compilation warning */
01700   UNUSED(heth);
01701   /* NOTE : This function Should not be modified, when the callback is needed,
01702   the HAL_ETH_MACErrorCallback could be implemented in the user file
01703   */
01704 }
01705
01706 /**
01707   * @brief  Ethernet Power Management module IT callback
01708   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01709   *         the configuration information for ETHERNET module
01710   * @retval None
01711   */
01712 __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
01713 {
01714   /* Prevent unused argument(s) compilation warning */
01715   UNUSED(heth);
01716   /* NOTE : This function Should not be modified, when the callback is needed,
01717   the HAL_ETH_PMTCallback could be implemented in the user file
01718   */
01719 }
01720
01721 /**
01722   * @brief  Energy Efficient Etherent IT callback
01723   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01724   *         the configuration information for ETHERNET module
01725   * @retval None
01726   */
01727 __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
01728 {
01729   /* Prevent unused argument(s) compilation warning */
01730   UNUSED(heth);
01731   /* NOTE : This function Should not be modified, when the callback is needed,
01732   the HAL_ETH_EEECallback could be implemented in the user file
01733   */
01734 }
01735
01736 /**
01737   * @brief  ETH WAKEUP interrupt callback
01738   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01739   *         the configuration information for ETHERNET module
01740   * @retval None
01741   */
01742 __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
01743 {
01744   /* Prevent unused argument(s) compilation warning */
01745   UNUSED(heth);
01746   /* NOTE : This function Should not be modified, when the callback is needed,
01747             the HAL_ETH_WakeUpCallback could be implemented in the user file
01748    */
01749 }
01750
01751 /**
01752   * @brief  Read a PHY register
01753   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01754   *         the configuration information for ETHERNET module
01755   * @param  PHYAddr: PHY port address, must be a value from 0 to 31
01756   * @param  PHYReg: PHY register address, must be a value from 0 to 31
01757   * @param pRegValue: parameter to hold read value
01758   * @retval HAL status
01759   */
01760 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
01761 {
01762   uint32_t tmpreg, tickstart;
01763
01764   /* Check for the Busy flag */
01765   if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
01766   {
01767     return HAL_ERROR;
01768   }
01769
01770   /* Get the  MACMDIOAR value */
01771   WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
01772
01773   /* Prepare the MDIO Address Register value
01774      - Set the PHY device address
01775      - Set the PHY register address
01776      - Set the read mode
01777      - Set the MII Busy bit */
01778
01779   MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
01780   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
01781   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
01782   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
01783
01784   /* Write the result value into the MDII Address register */
01785   WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
01786
01787   tickstart = HAL_GetTick();
01788
01789   /* Wait for the Busy flag */
01790   while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
01791   {
01792     if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
01793     {
01794       return HAL_ERROR;
01795     }
01796   }
01797
01798   /* Get MACMIIDR value */
01799   WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
01800
01801   return HAL_OK;
01802 }
01803
01804
01805 /**
01806   * @brief  Writes to a PHY register.
01807   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01808   *         the configuration information for ETHERNET module
01809   * @param  PHYAddr: PHY port address, must be a value from 0 to 31
01810   * @param  PHYReg: PHY register address, must be a value from 0 to 31
01811   * @param  RegValue: the value to write
01812   * @retval HAL status
01813   */
01814 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
01815 {
01816   uint32_t tmpreg, tickstart;
01817
01818   /* Check for the Busy flag */
01819   if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
01820   {
01821     return HAL_ERROR;
01822   }
01823
01824   /* Get the  MACMDIOAR value */
01825   WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
01826
01827   /* Prepare the MDIO Address Register value
01828      - Set the PHY device address
01829      - Set the PHY register address
01830      - Set the write mode
01831      - Set the MII Busy bit */
01832
01833   MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
01834   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
01835   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
01836   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
01837
01838
01839   /* Give the value to the MII data register */
01840   WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
01841
01842   /* Write the result value into the MII Address register */
01843   WRITE_REG(ETH->MACMDIOAR, tmpreg);
01844
01845   tickstart = HAL_GetTick();
01846
01847   /* Wait for the Busy flag */
01848   while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
01849   {
01850     if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
01851     {
01852       return HAL_ERROR;
01853     }
01854   }
01855
01856   return HAL_OK;
01857 }
01858
01859 /**
01860   * @}
01861   */
01862
01863 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
01864   *  @brief   ETH control functions
01865   *
01866 @verbatim
01867   ==============================================================================
01868                       ##### Peripheral Control functions #####
01869   ==============================================================================
01870   [..]
01871     This subsection provides a set of functions allowing to control the ETH
01872     peripheral.
01873
01874 @endverbatim
01875   * @{
01876   */
01877 /**
01878   * @brief  Get the configuration of the MAC and MTL subsystems.
01879   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01880   *         the configuration information for ETHERNET module
01881   * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
01882   *         the configuration of the MAC.
01883   * @retval HAL Status
01884   */
01885 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
01886 {
01887   if (macconf == NULL)
01888   {
01889     return HAL_ERROR;
01890   }
01891
01892   /* Get MAC parameters */
01893   macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
01894   macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
01895   macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
01896   macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
01897   macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
01898   macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
01899   macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
01900   macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
01901   macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
01902   macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
01903   macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
01904   macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
01905   macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
01906   macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
01907   macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
01908   macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
01909   macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
01910   macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
01911   macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
01912   macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
01913
01914   macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
01915   macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
01916   macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
01917   macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
01918   macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
01919   macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
01920
01921
01922   macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
01923   macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
01924
01925   macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
01926   macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
01927   macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
01928   macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
01929
01930
01931   macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
01932   macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
01933
01934   macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
01935
01936   macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
01937   macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
01938   macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
01939   macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
01940
01941   return HAL_OK;
01942 }
01943
01944 /**
01945   * @brief  Get the configuration of the DMA.
01946   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01947   *         the configuration information for ETHERNET module
01948   * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
01949   *         the configuration of the ETH DMA.
01950   * @retval HAL Status
01951   */
01952 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
01953 {
01954   if (dmaconf == NULL)
01955   {
01956     return HAL_ERROR;
01957   }
01958
01959   dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
01960   dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
01961   dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
01962
01963   dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
01964
01965   dmaconf->PBLx8Mode =  ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
01966   dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
01967
01968   dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR,  ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
01969   dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
01970
01971   dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
01972   dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
01973   dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
01974
01975   return HAL_OK;
01976 }
01977
01978 /**
01979   * @brief  Set the MAC configuration.
01980   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01981   *         the configuration information for ETHERNET module
01982   * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
01983   *         the configuration of the MAC.
01984   * @retval HAL status
01985   */
01986 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
01987 {
01988   if(macconf == NULL)
01989   {
01990     return HAL_ERROR;
01991   }
01992
01993   if(heth->RxState == HAL_ETH_STATE_READY)
01994   {
01995     ETH_SetMACConfig(heth, macconf);
01996
01997     return HAL_OK;
01998   }
01999   else
02000   {
02001     return HAL_ERROR;
02002   }
02003 }
02004
02005 /**
02006   * @brief  Set the ETH DMA configuration.
02007   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02008   *         the configuration information for ETHERNET module
02009   * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
02010   *         the configuration of the ETH DMA.
02011   * @retval HAL status
02012   */
02013 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
02014 {
02015   if(dmaconf == NULL)
02016   {
02017     return HAL_ERROR;
02018   }
02019
02020   if(heth->RxState == HAL_ETH_STATE_READY)
02021   {
02022     ETH_SetDMAConfig(heth, dmaconf);
02023
02024     return HAL_OK;
02025   }
02026   else
02027   {
02028     return HAL_ERROR;
02029   }
02030 }
02031
02032 /**
02033   * @brief  Configures the Clock range of ETH MDIO interface.
02034   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02035   *         the configuration information for ETHERNET module
02036   * @retval None
02037   */
02038 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
02039 {
02040   uint32_t tmpreg, hclk;
02041
02042   /* Get the ETHERNET MACMDIOAR value */
02043   tmpreg = (heth->Instance)->MACMDIOAR;
02044
02045         /* Clear CSR Clock Range bits */
02046   tmpreg &= ~ETH_MACMDIOAR_CR;
02047
02048         /* Get hclk frequency value */
02049   hclk = HAL_RCC_GetHCLKFreq();
02050
02051         /* Set CR bits depending on hclk value */
02052   if((hclk >= 20000000U)&&(hclk < 35000000U))
02053   {
02054     /* CSR Clock Range between 20-35 MHz */
02055     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
02056   }
02057   else if((hclk >= 35000000U)&&(hclk < 60000000U))
02058   {
02059     /* CSR Clock Range between 35-60 MHz */
02060     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
02061   }
02062   else if((hclk >= 60000000U)&&(hclk < 100000000U))
02063   {
02064     /* CSR Clock Range between 60-100 MHz */
02065     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
02066   }
02067   else if((hclk >= 100000000U)&&(hclk < 150000000U))
02068   {
02069     /* CSR Clock Range between 100-150 MHz */
02070     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
02071   }
02072   else /* (hclk >= 150000000)&&(hclk <= 200000000) */
02073   {
02074     /* CSR Clock Range between 150-200 MHz */
02075     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
02076   }
02077
02078   /* Configure the CSR Clock Range */
02079   (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
02080 }
02081
02082 /**
02083   * @brief  Set the ETH MAC (L2) Filters configuration.
02084   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02085   *         the configuration information for ETHERNET module
02086   * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
02087   *         the configuration of the ETH MAC filters.
02088   * @retval HAL status
02089   */
02090 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
02091 {
02092   uint32_t filterconfig;
02093
02094   if(pFilterConfig == NULL)
02095   {
02096     return HAL_ERROR;
02097   }
02098
02099   filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
02100                   ((uint32_t)pFilterConfig->HashUnicast << 1) |
02101                     ((uint32_t)pFilterConfig->HashMulticast << 2)  |
02102                       ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
02103                         ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
02104                           ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
02105                             ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
02106                               ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
02107                                 ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
02108                                   ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
02109                                     pFilterConfig->ControlPacketsFilter);
02110
02111   MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
02112
02113   return HAL_OK;
02114 }
02115
02116 /**
02117   * @brief  Get the ETH MAC (L2) Filters configuration.
02118   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02119   *         the configuration information for ETHERNET module
02120   * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
02121   *         the configuration of the ETH MAC filters.
02122   * @retval HAL status
02123   */
02124 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
02125 {
02126   if(pFilterConfig == NULL)
02127   {
02128     return HAL_ERROR;
02129   }
02130
02131   pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
02132   pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
02133   pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
02134   pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
02135   pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
02136   pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
02137   pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
02138   pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
02139   pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
02140   pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
02141   pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
02142
02143   return HAL_OK;
02144 }
02145
02146 /**
02147   * @brief  Set the source MAC Address to be matched.
02148   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02149   *         the configuration information for ETHERNET module
02150   * @param  AddrNbr: The MAC address to configure
02151   *          This parameter must be a value of the following:
02152   *            ETH_MAC_ADDRESS1
02153   *            ETH_MAC_ADDRESS2
02154   *            ETH_MAC_ADDRESS3
02155   * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
02156   * @retval HAL status
02157   */
02158 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
02159 {
02160   uint32_t macaddrhr, macaddrlr;
02161
02162   if(pMACAddr == NULL)
02163   {
02164     return HAL_ERROR;
02165   }
02166
02167   /* Get mac addr high reg offset */
02168   macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
02169   /* Get mac addr low reg offset */
02170   macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
02171
02172   /* Set MAC addr bits 32 to 47 */
02173   (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
02174   /* Set MAC addr bits 0 to 31 */
02175   (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
02176                                    ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
02177
02178    /* Enable address and set source address bit */
02179   (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
02180
02181   return HAL_OK;
02182 }
02183
02184 /**
02185   * @brief  Set the ETH Hash Table Value.
02186   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02187   *         the configuration information for ETHERNET module
02188   * @param  pHashTable: pointer to a table of two 32 bit values, that contains
02189   *         the 64 bits of the hash table.
02190   * @retval HAL status
02191   */
02192 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
02193 {
02194   if(pHashTable == NULL)
02195   {
02196     return HAL_ERROR;
02197   }
02198
02199   heth->Instance->MACHT0R = pHashTable[0];
02200   heth->Instance->MACHT1R = pHashTable[1];
02201
02202   return HAL_OK;
02203 }
02204
02205 /**
02206   * @brief  Set the VLAN Identifier for Rx packets
02207   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02208   *         the configuration information for ETHERNET module
02209   * @param  ComparisonBits: 12 or 16 bit comparison mode
02210             must be a value of @ref ETH_VLAN_Tag_Comparison
02211   * @param  VLANIdentifier: VLAN Identifier value
02212   * @retval None
02213   */
02214 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
02215 {
02216   if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
02217   {
02218     MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
02219     CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
02220   }
02221   else
02222   {
02223     MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
02224     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
02225   }
02226 }
02227
02228 /**
02229   * @brief  Enters the Power down mode.
02230   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02231   *         the configuration information for ETHERNET module
02232   * @param  pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
02233   *         that contains the Power Down configration
02234   * @retval None.
02235   */
02236 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
02237 {
02238   uint32_t powerdownconfig;
02239
02240   powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
02241                      ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
02242                        ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
02243                          ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
02244                            ETH_MACPCSR_PWRDWN);
02245
02246   /* Enable PMT interrupt */
02247   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
02248
02249   MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
02250 }
02251
02252 /**
02253   * @brief  Exits from the Power down mode.
02254   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02255   *         the configuration information for ETHERNET module
02256   * @retval None.
02257   */
02258 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
02259 {
02260   /* clear wake up sources */
02261   CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
02262
02263   if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
02264   {
02265     /* Exit power down mode */
02266     CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
02267   }
02268
02269   /* Disable PMT interrupt */
02270   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
02271 }
02272
02273 /**
02274   * @brief  Set the WakeUp filter.
02275   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02276   *         the configuration information for ETHERNET module
02277   * @param  pFilter: pointer to filter registers values
02278   * @param  Count: number of filter registers, must be from 1 to 8.
02279   * @retval None.
02280   */
02281 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
02282 {
02283   uint32_t regindex;
02284
02285   if(pFilter == NULL)
02286   {
02287     return HAL_ERROR;
02288   }
02289
02290   /* Reset Filter Pointer */
02291   SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
02292
02293   /* Wake up packet filter config */
02294   for(regindex = 0; regindex < Count; regindex++)
02295   {
02296     /* Write filter regs */
02297     WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
02298   }
02299
02300   return HAL_OK;
02301 }
02302
02303 /**
02304   * @}
02305   */
02306
02307 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
02308   *  @brief   ETH State and Errors functions
02309   *
02310 @verbatim
02311   ==============================================================================
02312                  ##### Peripheral State and Errors functions #####
02313   ==============================================================================
02314  [..]
02315    This subsection provides a set of functions allowing to return the State of
02316    ETH communication process, return Peripheral Errors occurred during communication
02317    process
02318
02319
02320 @endverbatim
02321   * @{
02322   */
02323
02324 /**
02325   * @brief  Returns the ETH state.
02326   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02327   *         the configuration information for ETHERNET module
02328   * @retval HAL state
02329   */
02330 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
02331 {
02332   HAL_ETH_StateTypeDef ret;
02333   HAL_ETH_StateTypeDef gstate = heth->gState;
02334   HAL_ETH_StateTypeDef rxstate =heth->RxState;
02335
02336   ret = gstate;
02337   ret |= rxstate;
02338   return ret;
02339 }
02340
02341 /**
02342   * @brief  Returns the ETH error code
02343   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02344   *         the configuration information for ETHERNET module
02345   * @retval ETH Error Code
02346   */
02347 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
02348 {
02349   return heth->ErrorCode;
02350 }
02351
02352 /**
02353   * @brief  Returns the ETH DMA error code
02354   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02355   *         the configuration information for ETHERNET module
02356   * @retval ETH DMA Error Code
02357   */
02358 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
02359 {
02360   return heth->DMAErrorCode;
02361 }
02362
02363 /**
02364   * @brief  Returns the ETH MAC error code
02365   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02366   *         the configuration information for ETHERNET module
02367   * @retval ETH MAC Error Code
02368   */
02369 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
02370 {
02371   return heth->MACErrorCode;
02372 }
02373
02374 /**
02375   * @brief  Returns the ETH MAC WakeUp event source
02376   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02377   *         the configuration information for ETHERNET module
02378   * @retval ETH MAC WakeUp event source
02379   */
02380 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
02381 {
02382   return heth->MACWakeUpEvent;
02383 }
02384
02385 /**
02386   * @}
02387   */
02388
02389 /**
02390   * @}
02391   */
02392
02393 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
02394 {
02395   uint32_t macregval;
02396
02397   /*------------------------ MACCR Configuration --------------------*/
02398   macregval =(macconf->InterPacketGapVal |
02399               macconf->SourceAddrControl |
02400                 ((uint32_t)macconf->ChecksumOffload<< 27) |
02401                   ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
02402                     ((uint32_t)macconf->Support2KPacket  << 22) |
02403                       ((uint32_t)macconf->CRCStripTypePacket << 21) |
02404                         ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
02405                           ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
02406                             ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
02407                               ((uint32_t)macconf->JumboPacket << 16) |
02408                                 macconf->Speed |
02409                                   macconf->DuplexMode |
02410                                     ((uint32_t)macconf->LoopbackMode << 12) |
02411                                       ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
02412                                         ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
02413                                           ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
02414                                             ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
02415                                               macconf->BackOffLimit |
02416                                                 ((uint32_t)macconf->DeferralCheck << 4)|
02417                                                   macconf->PreambleLength);
02418
02419   /* Write to MACCR */
02420   MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
02421
02422   /*------------------------ MACECR Configuration --------------------*/
02423   macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
02424                ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
02425                  ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
02426                    ((uint32_t)macconf->SlowProtocolDetect << 17)|
02427                      ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
02428                        macconf->GiantPacketSizeLimit);
02429
02430   /* Write to MACECR */
02431   MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
02432
02433   /*------------------------ MACWTR Configuration --------------------*/
02434   macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
02435                macconf->WatchdogTimeout);
02436
02437   /* Write to MACWTR */
02438   MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
02439
02440   /*------------------------ MACTFCR Configuration --------------------*/
02441   macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
02442                macconf->PauseLowThreshold |
02443                  ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
02444                    (macconf->PauseTime << 16));
02445
02446   /* Write to MACTFCR */
02447   MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
02448
02449   /*------------------------ MACRFCR Configuration --------------------*/
02450   macregval = ((uint32_t)macconf->ReceiveFlowControl |
02451                ((uint32_t)macconf->UnicastPausePacketDetect << 1));
02452
02453   /* Write to MACRFCR */
02454   MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
02455
02456   /*------------------------ MTLTQOMR Configuration --------------------*/
02457   /* Write to MTLTQOMR */
02458   MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
02459
02460   /*------------------------ MTLRQOMR Configuration --------------------*/
02461   macregval = (macconf->ReceiveQueueMode |
02462                ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
02463                  ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
02464                    ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
02465
02466   /* Write to MTLRQOMR */
02467   MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
02468 }
02469
02470 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
02471 {
02472   uint32_t dmaregval;
02473
02474   /*------------------------ DMAMR Configuration --------------------*/
02475   MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
02476
02477   /*------------------------ DMASBMR Configuration --------------------*/
02478   dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
02479                dmaconf->BurstMode |
02480                  ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
02481
02482   MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
02483
02484   /*------------------------ DMACCR Configuration --------------------*/
02485   dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
02486                dmaconf->MaximumSegmentSize);
02487
02488   MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
02489
02490   /*------------------------ DMACTCR Configuration --------------------*/
02491   dmaregval = (dmaconf->TxDMABurstLength |
02492                ((uint32_t)dmaconf->SecondPacketOperate << 4)|
02493                  ((uint32_t)dmaconf->TCPSegmentation << 12));
02494
02495   MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
02496
02497   /*------------------------ DMACRCR Configuration --------------------*/
02498   dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
02499                dmaconf->RxDMABurstLength);
02500
02501   /* Write to DMACRCR */
02502   MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
02503 }
02504
02505 /**
02506   * @brief  Configures Ethernet MAC and DMA with default parameters.
02507   *         called by HAL_ETH_Init() API.
02508   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02509   *         the configuration information for ETHERNET module
02510   * @retval HAL status
02511   */
02512 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
02513 {
02514   ETH_MACConfigTypeDef macDefaultConf;
02515   ETH_DMAConfigTypeDef dmaDefaultConf;
02516
02517   /*--------------- ETHERNET MAC registers default Configuration --------------*/
02518   macDefaultConf.AutomaticPadCRCStrip = ENABLE;
02519   macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
02520   macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
02521   macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
02522   macDefaultConf.ChecksumOffload = ENABLE;
02523   macDefaultConf.CRCCheckingRxPackets = ENABLE;
02524   macDefaultConf.CRCStripTypePacket = ENABLE;
02525   macDefaultConf.DeferralCheck = DISABLE;
02526   macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
02527   macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
02528   macDefaultConf.ExtendedInterPacketGap = DISABLE;
02529   macDefaultConf.ExtendedInterPacketGapVal = 0x0;
02530   macDefaultConf.ForwardRxErrorPacket = DISABLE;
02531   macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
02532   macDefaultConf.GiantPacketSizeLimit = 0x618;
02533   macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
02534   macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
02535   macDefaultConf.Jabber = ENABLE;
02536   macDefaultConf.JumboPacket = DISABLE;
02537   macDefaultConf.LoopbackMode = DISABLE;
02538   macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
02539   macDefaultConf.PauseTime = 0x0;
02540   macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
02541   macDefaultConf.ProgrammableWatchdog = DISABLE;
02542   macDefaultConf.ReceiveFlowControl = DISABLE;
02543   macDefaultConf.ReceiveOwn = ENABLE;
02544   macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
02545   macDefaultConf.RetryTransmission = ENABLE;
02546   macDefaultConf.SlowProtocolDetect = DISABLE;
02547   macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
02548   macDefaultConf.Speed = ETH_SPEED_100M;
02549   macDefaultConf.Support2KPacket = DISABLE;
02550   macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
02551   macDefaultConf.TransmitFlowControl = DISABLE;
02552   macDefaultConf.UnicastPausePacketDetect = DISABLE;
02553   macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
02554   macDefaultConf.Watchdog = ENABLE;
02555   macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
02556   macDefaultConf.ZeroQuantaPause = ENABLE;
02557
02558   /* MAC default configuration */
02559   ETH_SetMACConfig(heth, &macDefaultConf);
02560
02561   /*--------------- ETHERNET DMA registers default Configuration --------------*/
02562   dmaDefaultConf.AddressAlignedBeats = ENABLE;
02563   dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
02564   dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
02565   dmaDefaultConf.FlushRxPacket = DISABLE;
02566   dmaDefaultConf.PBLx8Mode = DISABLE;
02567   dmaDefaultConf.RebuildINCRxBurst = DISABLE;
02568   dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
02569   dmaDefaultConf.SecondPacketOperate = DISABLE;
02570   dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
02571   dmaDefaultConf.TCPSegmentation = DISABLE;
02572   dmaDefaultConf.MaximumSegmentSize = 536;
02573
02574   /* DMA default configuration */
02575   ETH_SetDMAConfig(heth, &dmaDefaultConf);
02576 }
02577
02578 /**
02579   * @brief  Configures the Clock range of SMI interface.
02580   *         called by HAL_ETH_Init() API.
02581   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02582   *         the configuration information for ETHERNET module
02583   * @retval None
02584   */
02585 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
02586 {
02587   uint32_t tmpreg, hclk;
02588
02589   /* Get the ETHERNET MACMDIOAR value */
02590   tmpreg = (heth->Instance)->MACMDIOAR;
02591
02592   /* Clear CSR Clock Range bits */
02593   tmpreg &= ~ETH_MACMDIOAR_CR;
02594
02595   /* Get hclk frequency value */
02596   hclk = HAL_RCC_GetHCLKFreq();
02597
02598   /* Set CR bits depending on hclk value */
02599   if((hclk >= 20000000U)&&(hclk < 35000000U))
02600   {
02601     /* CSR Clock Range between 20-35 MHz */
02602     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
02603   }
02604   else if((hclk >= 35000000U)&&(hclk < 60000000U))
02605   {
02606     /* CSR Clock Range between 35-60 MHz */
02607     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
02608   }
02609   else if((hclk >= 60000000U)&&(hclk < 100000000U))
02610   {
02611     /* CSR Clock Range between 60-100 MHz */
02612     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
02613   }
02614   else if((hclk >= 100000000U)&&(hclk < 150000000U))
02615   {
02616     /* CSR Clock Range between 100-150 MHz */
02617     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
02618   }
02619   else /* (hclk >= 150000000)&&(hclk <= 200000000) */
02620   {
02621     /* CSR Clock Range between 150-200 MHz */
02622     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
02623   }
02624
02625   /* Configure the CSR Clock Range */
02626   (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
02627 }
02628
02629 /**
02630   * @brief  Initializes the DMA Tx descriptors.
02631   *         called by HAL_ETH_Init() API.
02632   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02633   *         the configuration information for ETHERNET module
02634   * @retval None
02635   */
02636 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
02637 {
02638   ETH_DMADescTypeDef *dmatxdesc;
02639   uint32_t i;
02640
02641   /* Fill each DMATxDesc descriptor with the right values */
02642   for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
02643   {
02644     dmatxdesc = heth->Init.TxDesc + i;
02645
02646     WRITE_REG(dmatxdesc->DESC0, 0x0);
02647     WRITE_REG(dmatxdesc->DESC1, 0x0);
02648     WRITE_REG(dmatxdesc->DESC2, 0x0);
02649     WRITE_REG(dmatxdesc->DESC3, 0x0);
02650
02651     WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
02652   }
02653
02654   heth->TxDescList.CurTxDesc = 0;
02655
02656   /* Set Transmit Descriptor Ring Length */
02657   WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
02658
02659   /* Set Transmit Descriptor List Address */
02660   WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
02661
02662   /* Set Transmit Descriptor Tail pointer */
02663   WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
02664 }
02665
02666 /**
02667   * @brief  Initializes the DMA Rx descriptors in chain mode.
02668   *         called by HAL_ETH_Init() API.
02669   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02670   *         the configuration information for ETHERNET module
02671   * @retval None
02672   */
02673 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
02674 {
02675   ETH_DMADescTypeDef *dmarxdesc;
02676   uint32_t i;
02677
02678   for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
02679   {
02680     dmarxdesc =  heth->Init.RxDesc + i;
02681
02682     WRITE_REG(dmarxdesc->DESC0, 0x0);
02683     WRITE_REG(dmarxdesc->DESC1, 0x0);
02684     WRITE_REG(dmarxdesc->DESC2, 0x0);
02685     WRITE_REG(dmarxdesc->DESC3, 0x0);
02686     WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
02687     WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
02688
02689     /* Set Rx descritors adresses */
02690     WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
02691   }
02692
02693   WRITE_REG(heth->RxDescList.CurRxDesc, 0);
02694   WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
02695   WRITE_REG(heth->RxDescList.AppDescNbr, 0);
02696   WRITE_REG(heth->RxDescList.ItMode, 0);
02697   WRITE_REG(heth->RxDescList.AppContextDesc, 0);
02698
02699   /* Set Receive Descriptor Ring Length */
02700   WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
02701
02702   /* Set Receive Descriptor List Address */
02703   WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
02704
02705   /* Set Receive Descriptor Tail pointer Address */
02706   WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (((uint32_t)(ETH_RX_DESC_CNT - 1))*sizeof(ETH_DMADescTypeDef)))));
02707 }
02708
02709 /**
02710   * @brief  Prepare Tx DMA descriptor before transmission.
02711   *         called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
02712   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02713   *         the configuration information for ETHERNET module
02714   * @param  pTxConfig: Tx packet configuration
02715   * @param  ItMode: Enable or disable Tx EOT interrept
02716   * @retval Status
02717   */
02718 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
02719 {
02720   ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
02721   uint32_t descidx = dmatxdesclist->CurTxDesc;
02722   uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
02723   uint32_t descnbr = 0, idx;
02724   ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02725
02726   ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
02727
02728   /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02729   if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
02730   {
02731     return HAL_ETH_ERROR_BUSY;
02732   }
02733
02734   /***************************************************************************/
02735   /*****************    Context descriptor configuration (Optional) **********/
02736   /***************************************************************************/
02737   /* If VLAN tag is enabled for this packet */
02738   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
02739   {
02740     /* Set vlan tag value */
02741     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
02742     /* Set vlan tag valid bit */
02743     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
02744     /* Set the descriptor as the vlan input source */
02745     SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
02746
02747     /* if inner VLAN is enabled */
02748     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
02749     {
02750       /* Set inner vlan tag value */
02751       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
02752       /* Set inner vlan tag valid bit */
02753       SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
02754
02755       /* Set Vlan Tag control */
02756       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
02757
02758       /* Set the descriptor as the inner vlan input source */
02759       SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
02760       /* Enable double VLAN processing */
02761       SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
02762     }
02763   }
02764
02765   /* if tcp segementation is enabled for this packet */
02766   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
02767   {
02768     /* Set MSS value */
02769     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
02770     /* Set MSS valid bit */
02771     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
02772   }
02773
02774   if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
02775   {
02776     /* Set as context descriptor */
02777     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
02778     /* Set own bit */
02779     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
02780     /* Increment current tx descriptor index */
02781     INCR_TX_DESC_INDEX(descidx, 1U);
02782     /* Get current descriptor address */
02783     dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02784
02785     descnbr += 1U;
02786
02787     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02788     if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
02789     {
02790       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
02791       /* Clear own bit */
02792       CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
02793
02794       return HAL_ETH_ERROR_BUSY;
02795     }
02796   }
02797
02798   /***************************************************************************/
02799   /*****************    Normal descriptors configuration     *****************/
02800   /***************************************************************************/
02801
02802   descnbr += 1U;
02803
02804   /* Set header or buffer 1 address */
02805   WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
02806   /* Set header or buffer 1 Length */
02807   MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
02808
02809   if(txbuffer->next != NULL)
02810   {
02811     txbuffer = txbuffer->next;
02812     /* Set buffer 2 address */
02813     WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
02814     /* Set buffer 2 Length */
02815     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
02816   }
02817   else
02818   {
02819     WRITE_REG(dmatxdesc->DESC1, 0x0);
02820     /* Set buffer 2 Length */
02821     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
02822   }
02823
02824   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
02825   {
02826     /* Set TCP Header length */
02827     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
02828     /* Set TCP payload length */
02829     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
02830     /* Set TCP Segmentation Enabled bit */
02831     SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
02832   }
02833   else
02834   {
02835     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
02836
02837     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
02838     {
02839       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
02840     }
02841
02842     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
02843     {
02844       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
02845     }
02846   }
02847
02848   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
02849   {
02850     /* Set Vlan Tag control */
02851     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
02852   }
02853
02854   /* Mark it as First Descriptor */
02855   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
02856   /* Mark it as NORMAL descriptor */
02857   CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
02858   /* set OWN bit of FIRST descriptor */
02859   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02860
02861   /* If source address insertion/replacement is enabled for this packet */
02862   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
02863   {
02864     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
02865   }
02866
02867   /* only if the packet is splitted into more than one descriptors > 1 */
02868   while (txbuffer->next != NULL)
02869   {
02870     /* Clear the LD bit of previous descriptor */
02871     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
02872     /* Increment current tx descriptor index */
02873     INCR_TX_DESC_INDEX(descidx, 1U);
02874     /* Get current descriptor address */
02875     dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02876
02877     /* Clear the FD bit of new Descriptor */
02878     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
02879
02880     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02881     if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
02882     {
02883       descidx = firstdescidx;
02884       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02885
02886       /* clear previous desc own bit */
02887       for(idx = 0; idx < descnbr; idx ++)
02888       {
02889         CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02890
02891         /* Increment current tx descriptor index */
02892         INCR_TX_DESC_INDEX(descidx, 1U);
02893         /* Get current descriptor address */
02894         dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02895       }
02896
02897       return HAL_ETH_ERROR_BUSY;
02898     }
02899
02900     descnbr += 1U;
02901
02902     /* Get the next Tx buffer in the list */
02903     txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
02904
02905     /* Set header or buffer 1 address */
02906     WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
02907     /* Set header or buffer 1 Length */
02908     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
02909
02910     if (txbuffer->next != NULL)
02911     {
02912       /* Get the next Tx buffer in the list */
02913       txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
02914       /* Set buffer 2 address */
02915       WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
02916       /* Set buffer 2 Length */
02917       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
02918     }
02919     else
02920     {
02921       WRITE_REG(dmatxdesc->DESC1, 0x0);
02922       /* Set buffer 2 Length */
02923       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
02924     }
02925
02926     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
02927     {
02928       /* Set TCP payload length */
02929       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
02930       /* Set TCP Segmentation Enabled bit */
02931       SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
02932     }
02933     else
02934     {
02935       /* Set the packet length */
02936       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
02937
02938       if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
02939       {
02940         /* Checksum Insertion Control */
02941         MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
02942       }
02943     }
02944
02945     /* Set Own bit */
02946     SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02947     /* Mark it as NORMAL descriptor */
02948     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
02949   }
02950
02951   if(ItMode != ((uint32_t)RESET))
02952   {
02953     /* Set Interrupt on completition bit */
02954     SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
02955   }
02956   else
02957   {
02958     /* Clear Interrupt on completition bit */
02959     CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
02960   }
02961
02962   /* Mark it as LAST descriptor */
02963   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
02964
02965   dmatxdesclist->CurTxDesc = descidx;
02966
02967   /* Return function status */
02968   return HAL_ETH_ERROR_NONE;
02969 }
02970
02971 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
02972 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
02973 {
02974   /* Init the ETH Callback settings */
02975   heth->TxCpltCallback   = HAL_ETH_TxCpltCallback;    /* Legacy weak TxCpltCallback   */
02976   heth->RxCpltCallback   = HAL_ETH_RxCpltCallback;    /* Legacy weak RxCpltCallback   */
02977   heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;  /* Legacy weak DMAErrorCallback */
02978   heth->MACErrorCallback = HAL_ETH_MACErrorCallback;  /* Legacy weak MACErrorCallback */
02979   heth->PMTCallback      = HAL_ETH_PMTCallback;       /* Legacy weak PMTCallback      */
02980   heth->EEECallback      = HAL_ETH_EEECallback;       /* Legacy weak EEECallback      */
02981   heth->WakeUpCallback   = HAL_ETH_WakeUpCallback;    /* Legacy weak WakeUpCallback   */
02982 }
02983 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
02984
02985
02986 /**
02987   * @}
02988   */
02989
02990 #endif /* ETH */
02991
02992 #endif /* HAL_ETH_MODULE_ENABLED */
02993
02994 /**
02995   * @}
02996   */
02997
02998 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth.h Source File

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stm32h7xx_hal_eth.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ETH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_ETH_H
00022 #define STM32H7xx_HAL_ETH_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 #if defined(ETH)
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup ETH
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 #ifndef ETH_TX_DESC_CNT
00042  #define ETH_TX_DESC_CNT         4U
00043 #endif
00044
00045 #ifndef ETH_RX_DESC_CNT
00046  #define ETH_RX_DESC_CNT         4U
00047 #endif
00048
00049 /*********************** Descriptors struct def section ************************/
00050 /** @defgroup ETH_Exported_Types ETH Exported Types
00051   * @{
00052   */
00053
00054 /**
00055   * @brief  ETH DMA Descriptor structure definition
00056   */
00057 typedef struct
00058 {
00059   __IO uint32_t DESC0;
00060   __IO uint32_t DESC1;
00061   __IO uint32_t DESC2;
00062   __IO uint32_t DESC3;
00063   __IO uint32_t BackupAddr0; /* used to store rx buffer 1 address */
00064   __IO uint32_t BackupAddr1; /* used to store rx buffer 2 address */
00065 }ETH_DMADescTypeDef;
00066 /**
00067   *
00068   */
00069
00070 /**
00071   * @brief  ETH Buffers List structure definition
00072   */
00073 typedef struct __ETH_BufferTypeDef
00074 {
00075   uint8_t *buffer;                /*<! buffer address */
00076
00077   uint32_t len;                   /*<! buffer length */
00078
00079   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
00080 }ETH_BufferTypeDef;
00081 /**
00082   *
00083   */
00084
00085 /**
00086   * @brief  DMA Transmit Descriptors Wrapper structure definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t  TxDesc[ETH_TX_DESC_CNT];     /*<! Tx DMA descriptors addresses */
00091
00092   uint32_t  CurTxDesc;               /*<! Current Tx descriptor index for packet transmission */
00093
00094 }ETH_TxDescListTypeDef;
00095 /**
00096   *
00097   */
00098
00099  /**
00100   * @brief  Transmit Packet Configuration structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
00105                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
00106
00107   uint32_t Length;                  /*!< Total packet length   */
00108
00109   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
00110
00111   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
00112                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
00113
00114   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
00115                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
00116
00117   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
00118                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
00119
00120   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
00121                                         This parameter can be a value from 0x0 to 0x3FFF */
00122
00123   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
00124                                         This parameter can be a value from 0x0 to 0x3FFFF */
00125
00126   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
00127                                         This parameter can be a value from 0x5 to 0xF */
00128
00129   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
00130                                         This parameter can be a value from 0x0 to 0xFFFF*/
00131
00132   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
00133                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
00134
00135   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
00136                                         This parameter can be a value from 0x0 to 0x3FFFF */
00137
00138   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
00139                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
00140
00141 }ETH_TxPacketConfig;
00142 /**
00143   *
00144   */
00145
00146 /**
00147  * @brief  DMA Receive Descriptors Wrapper structure definition
00148  */
00149 typedef struct
00150 {
00151   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
00152
00153   uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */
00154
00155   uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */
00156
00157   uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */
00158
00159   uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.
00160                                              If 0 no context descriptor is present in last received packet. */
00161
00162   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
00163                                              If 0, DMA will not generate the Rx complete interrupt. */
00164 }ETH_RxDescListTypeDef;
00165 /**
00166   *
00167   */
00168
00169 /**
00170   * @brief  Received Packet Information structure definition
00171   */
00172 typedef struct
00173 {
00174   uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */
00175
00176   uint32_t VlanTag;         /*<! Vlan Tag value */
00177
00178   uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */
00179
00180   uint32_t Checksum;        /*<! Rx Checksum status.
00181                                  This parameter can be a value of @ref ETH_Rx_Checksum_Status */
00182
00183   uint32_t HeaderType;      /*<! IP header type.
00184                                  This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
00185
00186   uint32_t PayloadType;     /*<! Payload type.
00187                                  This parameter can be a value of @ref ETH_Rx_Payload_Type */
00188
00189   uint32_t MacFilterStatus; /*<! MAC filter status.
00190                                  This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
00191
00192   uint32_t L3FilterStatus;  /*<! L3 filter status
00193                                  This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
00194
00195   uint32_t L4FilterStatus;  /*<! L4 filter status
00196                                  This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
00197
00198   uint32_t ErrorCode;       /*<! Rx error code
00199                                  This parameter can be a combination of @ref ETH_Rx_Error_Code */
00200
00201 } ETH_RxPacketInfo;
00202 /**
00203   *
00204   */
00205
00206 /**
00207   * @brief  ETH MAC Configuration Structure definition
00208   */
00209 typedef struct
00210 {
00211   uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
00212                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
00213
00214   FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
00215
00216   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
00217                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
00218
00219   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
00220
00221   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
00222
00223   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
00224
00225   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
00226
00227   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path
00228                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
00229                                                            When disabled, the MAC can receive up to 16384 bytes. */
00230
00231   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path
00232                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
00233                                                            When disabled, the MAC can send up to 16384 bytes. */
00234
00235   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
00236                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
00237                                                            without reporting a giant packet error */
00238
00239   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
00240                                                            This parameter can be a value of @ref ETH_Speed */
00241
00242   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
00243                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
00244
00245   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
00246
00247   FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
00248
00249   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
00250
00251   FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
00252
00253   FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
00254
00255   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
00256                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
00257
00258   FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
00259
00260   uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
00261                                                            This parameter can be a value of @ref ETH_Preamble_Length */
00262
00263   FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
00264
00265   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
00266
00267   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
00268
00269   uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
00270                                                           greater than the value programmed in this field in units of bytes
00271                                                           This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
00272
00273   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
00274
00275   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
00276                                                            This parameter can be a value from 0x0 to 0xFF */
00277
00278   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
00279
00280   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
00281                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
00282
00283    uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
00284                                                    This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
00285
00286   FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
00287
00288   uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
00289                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
00290
00291   FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
00292                                                    or the MAC back pressure operation in Half Duplex mode */
00293
00294   FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
00295
00296   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
00297                                                   and disables its transmitter for a specified (Pause) time */
00298
00299   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
00300                                                       This parameter can be a value of @ref ETH_Transmit_Mode */
00301
00302   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
00303                                                              This parameter can be a value of @ref ETH_Receive_Mode */
00304
00305   FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
00306
00307   FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
00308
00309   FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
00310 } ETH_MACConfigTypeDef;
00311 /**
00312   *
00313   */
00314
00315 /**
00316   * @brief  ETH DMA Configuration Structure definition
00317   */
00318  typedef struct
00319  {
00320    uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
00321                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
00322
00323    FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
00324                                                             burst transfers on Read and Write channels  */
00325
00326    uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
00327                                                      This parameter can be a value of @ref ETH_Burst_Mode */
00328
00329    FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
00330                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
00331
00332    FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
00333
00334    uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
00335                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
00336
00337    FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
00338                                                       Packet of Transmit data even before obtaining the status for the first one. */
00339
00340    uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
00341                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
00342
00343    FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
00344
00345    FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
00346
00347    uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
00348                                                   This parameter can be a value from 0x40 to 0x3FFF */
00349 } ETH_DMAConfigTypeDef;
00350 /**
00351   *
00352   */
00353
00354 /**
00355   * @brief  HAL ETH Media Interfaces enum definition
00356   */
00357 typedef enum
00358 {
00359   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
00360   HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
00361 }ETH_MediaInterfaceTypeDef;
00362 /**
00363   *
00364   */
00365
00366 /**
00367   * @brief  ETH Init Structure definition
00368   */
00369 typedef struct
00370 {
00371
00372   uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
00373
00374   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
00375
00376   ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
00377
00378   ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
00379
00380   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
00381
00382 }ETH_InitTypeDef;
00383 /**
00384   *
00385   */
00386
00387 /**
00388   * @brief  HAL State structures definition
00389   */
00390 typedef uint32_t HAL_ETH_StateTypeDef;
00391 /**
00392   *
00393   */
00394
00395 /**
00396   * @brief  ETH Handle Structure definition
00397   */
00398 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00399 typedef struct __ETH_HandleTypeDef
00400 #else
00401 typedef struct
00402 #endif
00403 {
00404   ETH_TypeDef                *Instance;                 /*!< Register base address       */
00405
00406   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
00407
00408   ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
00409                                                             addresses and current descriptor index  */
00410
00411   ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
00412                                                             addresses and current descriptor index  */
00413
00414   HAL_LockTypeDef            Lock;                      /*!< Locking object             */
00415
00416   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
00417                                                               and also related to Tx operations.
00418                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
00419
00420   __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.
00421                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
00422
00423   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
00424                                                              This parameter can be a value of of @ref ETH_Error_Code */
00425
00426   __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
00427                                                              This parameter can be a combination of @ref ETH_DMA_Status_Flags */
00428
00429   __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
00430                                                              This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
00431
00432   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
00433                                                              This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
00434
00435   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
00436                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
00437
00438 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00439
00440   void    (* TxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);   /*!< ETH Tx Complete Callback */
00441   void    (* RxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Rx  Complete Callback     */
00442   void    (* DMAErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH DMA Error Callback   */
00443   void    (* MACErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH MAC Error Callback     */
00444   void    (* PMTCallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Power Management Callback            */
00445   void    (* EEECallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH EEE Callback   */
00446   void    (* WakeUpCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Wake UP Callback   */
00447
00448   void    (* MspInitCallback)    ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp Init callback              */
00449   void    (* MspDeInitCallback)  ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp DeInit callback            */
00450
00451 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
00452
00453 } ETH_HandleTypeDef;
00454 /**
00455   *
00456   */
00457
00458 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00459 /**
00460   * @brief  HAL ETH Callback ID enumeration definition
00461   */
00462 typedef enum
00463 {
00464   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
00465   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
00466
00467   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
00468   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
00469   HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID         */
00470   HAL_ETH_MAC_ERROR_CB_ID          = 0x05U,    /*!< ETH MAC Error Callback ID         */
00471   HAL_ETH_PMT_CB_ID                = 0x06U,     /*!< ETH Power Management Callback ID  */
00472   HAL_ETH_EEE_CB_ID                = 0x07U,     /*!< ETH EEE Callback ID               */
00473   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
00474
00475
00476 }HAL_ETH_CallbackIDTypeDef;
00477
00478 /**
00479   * @brief  HAL ETH Callback pointer definition
00480   */
00481 typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
00482
00483 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
00484
00485 /**
00486   * @brief  ETH MAC filter structure definition
00487   */
00488 typedef struct{
00489   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
00490
00491   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
00492
00493   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
00494
00495   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
00496
00497   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
00498
00499   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
00500
00501   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
00502
00503   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
00504
00505   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
00506
00507   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
00508
00509   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
00510                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
00511 }ETH_MACFilterConfigTypeDef;
00512 /**
00513   *
00514   */
00515
00516 /**
00517   * @brief  ETH Power Down structure definition
00518   */
00519 typedef struct{
00520   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
00521
00522   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
00523
00524   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
00525
00526   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
00527
00528 }ETH_PowerDownConfigTypeDef;
00529 /**
00530   *
00531   */
00532
00533 /**
00534   * @}
00535   */
00536
00537 /* Exported constants --------------------------------------------------------*/
00538 /** @defgroup ETH_Exported_Constants ETH Exported Constants
00539   * @{
00540   */
00541
00542 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
00543   * @{
00544   */
00545
00546 /*
00547    DMA Tx Normal Desciptor Read Format
00548   -----------------------------------------------------------------------------------------------
00549   TDES0 |                         Buffer1 or Header Address  [31:0]                              |
00550   -----------------------------------------------------------------------------------------------
00551   TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
00552   -----------------------------------------------------------------------------------------------
00553   TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
00554   -----------------------------------------------------------------------------------------------
00555   TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
00556   -----------------------------------------------------------------------------------------------
00557 */
00558
00559 /**
00560   * @brief  Bit definition of TDES0 RF register
00561   */
00562 #define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
00563
00564 /**
00565   * @brief  Bit definition of TDES1 RF register
00566   */
00567 #define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
00568
00569 /**
00570   * @brief  Bit definition of TDES2 RF register
00571   */
00572 #define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000U)  /*!< Interrupt on Completion */
00573 #define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000U)  /*!< Transmit Timestamp Enable */
00574 #define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000U)  /*!< Buffer 2 Length */
00575 #define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000U)  /*!< VLAN Tag Insertion or Replacement mask */
00576 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)  /*!< Do not add a VLAN tag. */
00577 #define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000U)  /*!< Remove the VLAN tag from the packets before transmission. */
00578 #define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000U)  /*!< Insert a VLAN tag. */
00579 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)  /*!< Replace the VLAN tag. */
00580 #define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFFU)  /*!< Buffer 1 Length */
00581 #define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FFU)  /*!< Header Length */
00582
00583 /**
00584   * @brief  Bit definition of TDES3 RF register
00585   */
00586 #define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
00587 #define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000U)  /*!< Context Type */
00588 #define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000U)  /*!< First Descriptor */
00589 #define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000U)  /*!< Last Descriptor */
00590 #define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000U)  /*!< CRC Pad Control mask */
00591 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000U)  /*!< CRC Pad Control: CRC and Pad Insertion */
00592 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000U)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
00593 #define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000U)  /*!< CRC Pad Control: Disable CRC Insertion */
00594 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000U)  /*!< CRC Pad Control: CRC Replacement */
00595 #define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000U)  /*!< SA Insertion Control mask*/
00596 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000U)  /*!< SA Insertion Control: Do not include the source address */
00597 #define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000U)  /*!< SA Insertion Control: Include or insert the source address */
00598 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000U)  /*!< SA Insertion Control: Replace the source address */
00599 #define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000U)  /*!< TCP Header Length */
00600 #define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000U)  /*!< TCP segmentation enable */
00601 #define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000U)  /*!< Checksum Insertion Control: 4 cases */
00602 #define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is disabled */
00603 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000U)  /*!< Only IP header checksum calculation and insertion are enabled. */
00604 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000U)  /*!< IP header checksum and payload checksum calculation and insertion are
00605                                                                                           enabled, but pseudo header checksum is not calculated in hardware */
00606 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000U)  /*!< IP Header checksum and payload checksum calculation and insertion are
00607                                                                                           enabled, and pseudo header checksum is calculated in hardware. */
00608 #define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFFU)  /*!< TCP Payload Length */
00609 #define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFFU)  /*!< Transmit End of Ring */
00610
00611 /*
00612    DMA Tx Normal Descriptor Write Back Format
00613   -----------------------------------------------------------------------------------------------
00614   TDES0 |                         Timestamp Low                                                  |
00615   -----------------------------------------------------------------------------------------------
00616   TDES1 |                         Timestamp High                                                 |
00617   -----------------------------------------------------------------------------------------------
00618   TDES2 |                           Reserved[31:0]                                               |
00619   -----------------------------------------------------------------------------------------------
00620   TDES3 | OWN(31) |                          Status[30:0]                                        |
00621   -----------------------------------------------------------------------------------------------
00622 */
00623
00624 /**
00625   * @brief  Bit definition of TDES0 WBF register
00626   */
00627 #define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
00628
00629 /**
00630   * @brief  Bit definition of TDES1 WBF register
00631   */
00632 #define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
00633
00634 /**
00635   * @brief  Bit definition of TDES3 WBF register
00636   */
00637 #define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
00638 #define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000U)  /*!< Context Type */
00639 #define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000U)  /*!< First Descriptor */
00640 #define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000U)  /*!< Last Descriptor */
00641 #define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Timestamp Status */
00642 #define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */
00643 #define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Timestamp Enable */
00644 #define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
00645 #define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */
00646 #define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000U)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
00647 #define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */
00648 #define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */
00649 #define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */
00650 #define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */
00651 #define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */
00652 #define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0U)  /*!< Collision Count */
00653 #define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008U)  /*!< Excessive Deferral */
00654 #define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004U)  /*!< Underflow Error: late data arrival from the memory */
00655 #define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002U)  /*!< Deferred Bit */
00656 #define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004U)  /*!< IP Header Error */
00657
00658
00659 /*
00660    DMA Tx Context Desciptor
00661   -----------------------------------------------------------------------------------------------
00662   TDES0 |                               Timestamp Low                                            |
00663   -----------------------------------------------------------------------------------------------
00664   TDES1 |                               Timestamp High                                           |
00665   -----------------------------------------------------------------------------------------------
00666   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
00667   -----------------------------------------------------------------------------------------------
00668   TDES3 | OWN(31) |                          Status[30:0]                                        |
00669   -----------------------------------------------------------------------------------------------
00670 */
00671
00672 /**
00673   * @brief  Bit definition of Tx context descriptor register 0
00674   */
00675 #define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
00676
00677 /**
00678   * @brief  Bit definition of Tx context descriptor register 1
00679   */
00680 #define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
00681
00682 /**
00683   * @brief  Bit definition of Tx context descriptor register 2
00684   */
00685 #define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag */
00686 #define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFFU)  /*!< Maximum Segment Size */
00687
00688 /**
00689   * @brief  Bit definition of Tx context descriptor register 3
00690   */
00691 #define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000U)     /*!< OWN bit: descriptor is owned by DMA engine */
00692 #define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000U)     /*!< Context Type */
00693 #define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000U)     /*!< One-Step Timestamp Correction Enable */
00694 #define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000U)     /*!< One-Step Timestamp Correction Input or MSS Valid */
00695 #define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000U)     /*!< Context Descriptor Error */
00696 #define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000U)     /*!< Inner VLAN Tag Insert or Replace Mask */
00697 #define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000U)     /*!< Do not add the inner VLAN tag. */
00698 #define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000U)     /*!< Remove the inner VLAN tag from the packets before transmission. */
00699 #define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000U)     /*!< Insert the inner VLAN tag. */
00700 #define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000U)     /*!< Replace the inner VLAN tag. */
00701 #define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000U)     /*!< Inner VLAN Tag Valid */
00702 #define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000U)     /*!< VLAN Tag Valid */
00703 #define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFFU)     /*!< VLAN Tag */
00704
00705 /**
00706   * @}
00707   */
00708
00709
00710 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
00711   * @{
00712   */
00713
00714 /*
00715   DMA Rx Normal Descriptor read format
00716   -----------------------------------------------------------------------------------------------------------
00717   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
00718   -----------------------------------------------------------------------------------------------------------
00719   RDES1 |                                            Reserved                                               |
00720   -----------------------------------------------------------------------------------------------------------
00721   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
00722   -----------------------------------------------------------------------------------------------------------
00723   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
00724   -----------------------------------------------------------------------------------------------------------
00725 */
00726
00727 /**
00728   * @brief  Bit definition of Rx normal descriptor register 0 read format
00729   */
00730 #define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFFU)  /*!< Header or Buffer 1 Address Pointer  */
00731
00732 /**
00733   * @brief  Bit definition of Rx normal descriptor register 2 read format
00734   */
00735 #define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFFU)  /*!< Buffer 2 Address Pointer  */
00736
00737 /**
00738   * @brief  Bit definition of Rx normal descriptor register 3 read format
00739   */
00740 #define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */
00741 #define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000U)  /*!< Interrupt Enabled on Completion  */
00742 #define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000U)  /*!< Buffer 2 Address Valid */
00743 #define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000U)  /*!< Buffer 1 Address Valid */
00744
00745 /*
00746   DMA Rx Normal Descriptor write back format
00747   ---------------------------------------------------------------------------------------------------------------------
00748   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
00749         ---------------------------------------------------------------------------------------------------------------------
00750   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
00751   ---------------------------------------------------------------------------------------------------------------------
00752   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
00753   ---------------------------------------------------------------------------------------------------------------------
00754   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
00755   ---------------------------------------------------------------------------------------------------------------------
00756 */
00757
00758 /**
00759   * @brief  Bit definition of Rx normal descriptor register 0 write back format
00760   */
00761 #define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag  */
00762 #define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFFU)  /*!< Outer VLAN Tag  */
00763
00764 /**
00765   * @brief  Bit definition of Rx normal descriptor register 1 write back format
00766   */
00767 #define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000U)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
00768 #define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000U)  /*!< Timestamp Dropped  */
00769 #define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000U)  /*!< Timestamp Available  */
00770 #define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000U)  /*!< PTP Version  */
00771 #define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000U)  /*!< PTP Packet Type  */
00772 #define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000U)  /*!< PTP Message Type: No PTP message received  */
00773 #define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100U)  /*!< PTP Message Type: SYNC (all clock types)  */
00774 #define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200U)  /*!< PTP Message Type: Follow_Up (all clock types)  */
00775 #define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300U)  /*!< PTP Message Type: Delay_Req (all clock types)  */
00776 #define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400U)  /*!< PTP Message Type: Delay_Resp (all clock types)  */
00777 #define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500U)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
00778 #define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600U)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
00779 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700U)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
00780 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800U)  /*!< PTP Message Type: Announce  */
00781 #define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900U)  /*!< PTP Message Type: Management  */
00782 #define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00U)  /*!< PTP Message Type: Signaling  */
00783 #define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00U)  /*!< PTP Message Type: PTP packet with Reserved message type  */
00784 #define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080U)  /*!< IP Payload Error */
00785 #define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040U)  /*!< IP Checksum Bypassed */
00786 #define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020U)  /*!< IPv6 header Present */
00787 #define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010U)  /*!< IPv4 header Present */
00788 #define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008U)  /*!< IP Header Error */
00789 #define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003U)  /*!< Payload Type mask */
00790 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000U)  /*!< Payload Type: Unknown type or IP/AV payload not processed */
00791 #define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001U)  /*!< Payload Type: UDP */
00792 #define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002U)  /*!< Payload Type: TCP  */
00793 #define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003U)  /*!< Payload Type: ICMP */
00794
00795 /**
00796   * @brief  Bit definition of Rx normal descriptor register 2 write back format
00797   */
00798 #define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000U)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
00799 #define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000U)  /*!< Layer 4 Filter Match                  */
00800 #define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000U)  /*!< Layer 3 Filter Match                  */
00801 #define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000U)  /*!< MAC Address Match or Hash Value       */
00802 #define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000U)  /*!< Hash Filter Status                    */
00803 #define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000U)  /*!< Destination Address Filter Fail       */
00804 #define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000U)  /*!< SA Address Filter Fail                */
00805 #define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000U)  /*!< VLAN Filter Status                    */
00806 #define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400U)  /*!< ARP Reply Not Generated               */
00807
00808
00809 /**
00810   * @brief  Bit definition of Rx normal descriptor register 3 write back format
00811   */
00812 #define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit */
00813 #define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor */
00814 #define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000U)  /*!< First Descriptor */
00815 #define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000U)  /*!< Last Descriptor */
00816 #define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000U)  /*!< Receive Status RDES2 Valid */
00817 #define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000U)  /*!< Receive Status RDES1 Valid */
00818 #define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000U)  /*!< Receive Status RDES0 Valid */
00819 #define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000U)  /*!< CRC Error */
00820 #define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000U)  /*!< Giant Packet */
00821 #define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000U)  /*!< Receive Watchdog Timeout */
00822 #define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000U)  /*!< Overflow Error */
00823 #define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000U)  /*!< Receive Error */
00824 #define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000U)  /*!< Dribble Bit Error */
00825 #define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000U)  /*!< Length/Type Field */
00826 #define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000U)  /*!< The packet is a length packet */
00827 #define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000U)  /*!< The packet is a type packet */
00828 #define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000U)  /*!< The packet is a ARP Request packet type */
00829 #define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000U)  /*!< The packet is a type packet with VLAN Tag */
00830 #define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000U)  /*!< The packet is a type packet with Double VLAN Tag */
00831 #define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000U)  /*!< The packet is a MAC Control packet type */
00832 #define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000U)  /*!< The packet is a OAM packet type */
00833 #define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000U)  /*!< Error Summary */
00834 #define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFFU)  /*!< Packet Length */
00835
00836 /*
00837   DMA Rx context Descriptor
00838   ---------------------------------------------------------------------------------------------------------------------
00839   RDES0 |                                     Timestamp Low[31:0]                                                     |
00840         ---------------------------------------------------------------------------------------------------------------------
00841   RDES1 |                                     Timestamp High[31:0]                                                    |
00842   ---------------------------------------------------------------------------------------------------------------------
00843   RDES2 |                                          Reserved                                                           |
00844   ---------------------------------------------------------------------------------------------------------------------
00845   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
00846   ---------------------------------------------------------------------------------------------------------------------
00847 */
00848
00849 /**
00850   * @brief  Bit definition of Rx context descriptor register 0
00851   */
00852 #define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp Low  */
00853
00854 /**
00855   * @brief  Bit definition of Rx context descriptor register 1
00856   */
00857 #define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp High  */
00858
00859 /**
00860   * @brief  Bit definition of Rx context descriptor register 3
00861   */
00862 #define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit  */
00863 #define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor  */
00864
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup ETH_Frame_settings ETH frame settings
00870   * @{
00871   */
00872 #define ETH_MAX_PACKET_SIZE      ((uint32_t)1528U)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
00873 #define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
00874 #define ETH_CRC                  ((uint32_t)4U)    /*!< Ethernet CRC */
00875 #define ETH_VLAN_TAG             ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
00876 #define ETH_MIN_PAYLOAD          ((uint32_t)46U)    /*!< Minimum Ethernet payload size */
00877 #define ETH_MAX_PAYLOAD          ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */
00878 #define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000U)    /*!< Jumbo frame payload size */
00879 /**
00880   * @}
00881   */
00882
00883 /** @defgroup ETH_Error_Code ETH Error Code
00884   * @{
00885   */
00886 #define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00887 #define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
00888 #define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
00889 #define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
00890 #define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */
00891 #define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */
00892 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
00893 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
00894 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
00895 /**
00896   * @}
00897   */
00898
00899 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
00900   * @{
00901   */
00902 #define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001U)
00903 #define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002U)
00904 #define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004U)
00905 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008U)
00906 #define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010U)
00907 #define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020U)
00908 /**
00909   * @}
00910   */
00911
00912 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
00913   * @{
00914   */
00915 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
00916 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
00917 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
00923   * @{
00924   */
00925 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
00926 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
00927 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
00928 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
00934   * @{
00935   */
00936 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
00937 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
00938 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
00939 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
00940 /**
00941   * @}
00942   */
00943
00944 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
00945   * @{
00946   */
00947 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
00948 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
00949 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
00950 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
00956   * @{
00957   */
00958 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
00959 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
00960 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
00961 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
00962 /**
00963   * @}
00964   */
00965
00966 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
00967   * @{
00968   */
00969 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
00970 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
00971 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
00977   * @{
00978   */
00979 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
00980 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
00981 /**
00982   * @}
00983   */
00984
00985 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
00986   * @{
00987   */
00988 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
00989 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
00990 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
00991 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
00997   * @{
00998   */
00999 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
01000 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
01001 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
01002 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
01003 /**
01004   * @}
01005   */
01006
01007 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
01008   * @{
01009   */
01010 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
01011 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
01012 /**
01013   * @}
01014   */
01015
01016 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
01017   * @{
01018   */
01019 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
01020 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
01021 /**
01022   * @}
01023   */
01024
01025 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
01026   * @{
01027   */
01028 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
01029 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
01030 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
01031 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
01032 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
01033 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
01034 /**
01035   * @}
01036   */
01037
01038 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
01039   * @{
01040   */
01041 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
01042 #define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000U)
01043 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
01044 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
01045 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
01046 #define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
01047 #define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
01048 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
01049 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
01050 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
01051 #define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000U)
01052 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
01053 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
01054 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
01055 #define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
01056 #define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
01057 #define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
01058 #define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
01059 /**
01060   * @}
01061   */
01062
01063  /** @defgroup ETH_Burst_Mode ETH Burst Mode
01064   * @{
01065   */
01066 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
01067 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
01068 #define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000U)
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
01074   * @{
01075   */
01076 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
01077 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
01078 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
01079 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
01080 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
01081 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
01087   * @{
01088   */
01089 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
01090 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
01091 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
01092 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
01093 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
01094 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
01095 /**
01096   * @}
01097   */
01098
01099 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
01100   * @{
01101   */
01102 #define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
01103 #define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
01104 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
01105 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
01106 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
01107 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
01108 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
01109 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
01110 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
01111 #define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
01112 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
01113 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
01114 #define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
01115 /**
01116   * @}
01117   */
01118
01119 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
01120   * @{
01121   */
01122 #define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
01123 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
01124 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
01125 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
01126 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
01127 #define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
01128 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
01129 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
01130 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
01131 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
01132 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
01133 #define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
01134 #define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
01135 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
01136 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
01137 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
01138 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
01139 /**
01140   * @}
01141   */
01142
01143 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
01144   * @{
01145   */
01146 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
01147 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
01148 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
01149 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
01150 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
01151 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
01152 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
01153 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
01154 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
01155 /**
01156   * @}
01157   */
01158
01159 /** @defgroup ETH_Receive_Mode ETH Receive Mode
01160   * @{
01161   */
01162 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
01163 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
01164 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
01165 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
01166 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
01167 /**
01168   * @}
01169   */
01170
01171 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
01172   * @{
01173   */
01174 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
01175 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
01176 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
01177 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
01178 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
01179 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
01185   * @{
01186   */
01187 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
01188 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
01189 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
01190 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
01191 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
01192 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
01193 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
01194 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
01195 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
01196 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
01197 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
01198 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
01199 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
01200 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
01201 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
01202 /**
01203   * @}
01204   */
01205
01206 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
01207   * @{
01208   */
01209 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
01210 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
01211 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
01212 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
01213 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
01214 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
01215 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
01216 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
01217 /**
01218   * @}
01219   */
01220
01221 /** @defgroup ETH_Speed  ETH Speed
01222   * @{
01223   */
01224 #define ETH_SPEED_10M        ((uint32_t)0x00000000U)
01225 #define ETH_SPEED_100M       ETH_MACCR_FES
01226 /**
01227   * @}
01228   */
01229
01230 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
01231   * @{
01232   */
01233 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
01234 #define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000U)
01235 /**
01236   * @}
01237   */
01238
01239 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
01240   * @{
01241   */
01242 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
01243 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
01244 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
01245 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
01246 /**
01247   * @}
01248   */
01249
01250 /** @defgroup ETH_Preamble_Length ETH Preamble Length
01251   * @{
01252   */
01253 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
01254 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
01255 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
01256 /**
01257   * @}
01258   */
01259
01260 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
01261   * @{
01262   */
01263 #define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000U)
01264 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
01265 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
01266 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
01267 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
01268 /**
01269   * @}
01270   */
01271
01272 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
01273   * @{
01274   */
01275 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
01276 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
01277 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
01278 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
01279 /**
01280   * @}
01281   */
01282
01283 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
01284   * @{
01285   */
01286 #define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)
01287 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup ETH_MAC_addresses ETH MAC addresses
01293   * @{
01294   */
01295 #define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
01296 #define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
01297 #define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
01298 #define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
01304   * @{
01305   */
01306 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
01307 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
01308 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
01309 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
01310 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
01311 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
01312 /**
01313   * @}
01314   */
01315
01316 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
01317   * @{
01318   */
01319 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
01320 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
01321 /**
01322   * @}
01323   */
01324
01325 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
01326   * @{
01327   */
01328 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
01329 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
01330 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
01331 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
01332 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
01333 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
01334 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
01335 /**
01336   * @}
01337   */
01338
01339 /** @defgroup HAL_ETH_StateTypeDef ETH States
01340   * @{
01341   */
01342 #define HAL_ETH_STATE_RESET       ((uint32_t)0x00000000U)    /*!< Peripheral not yet Initialized or disabled */
01343 #define HAL_ETH_STATE_READY       ((uint32_t)0x00000010U)    /*!< Peripheral Communication started           */
01344 #define HAL_ETH_STATE_BUSY        ((uint32_t)0x00000023U)    /*!< an internal process is ongoing             */
01345 #define HAL_ETH_STATE_BUSY_TX     ((uint32_t)0x00000021U)    /*!< Transmission process is ongoing            */
01346 #define HAL_ETH_STATE_BUSY_RX     ((uint32_t)0x00000022U)    /*!< Reception process is ongoing               */
01347 #define HAL_ETH_STATE_ERROR       ((uint32_t)0x000000E0U)    /*!< Error State                                */
01348 /**
01349   * @}
01350   */
01351 /**
01352   * @}
01353   */
01354
01355 /* Exported macro ------------------------------------------------------------*/
01356 /** @defgroup ETH_Exported_Macros ETH Exported Macros
01357   * @{
01358   */
01359
01360 /** @brief Reset ETH handle state
01361   * @param  __HANDLE__: specifies the ETH handle.
01362   * @retval None
01363   */
01364 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01365 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
01366                                                        (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
01367                                                        (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
01368                                                        (__HANDLE__)->MspInitCallback = NULL;             \
01369                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
01370                                                      } while(0)
01371 #else
01372 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
01373                                                        (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
01374                                                        (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
01375                                                      } while(0)
01376 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
01377
01378 /**
01379   * @brief  Enables the specified ETHERNET DMA interrupts.
01380   * @param  __HANDLE__   : ETH Handle
01381   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01382   *   enabled @ref ETH_DMA_Interrupts
01383   * @retval None
01384   */
01385 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
01386
01387 /**
01388   * @brief  Disables the specified ETHERNET DMA interrupts.
01389   * @param  __HANDLE__   : ETH Handle
01390   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01391   *   disabled. @ref ETH_DMA_Interrupts
01392   * @retval None
01393   */
01394 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
01395
01396 /**
01397   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
01398   * @param  __HANDLE__   : ETH Handle
01399   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
01400   * @retval The ETH DMA IT Source enabled or disabled
01401   */
01402 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
01403
01404 /**
01405   * @brief  Gets the ETHERNET DMA IT pending bit.
01406   * @param  __HANDLE__   : ETH Handle
01407   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
01408   * @retval The state of ETH DMA IT (SET or RESET)
01409   */
01410 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
01411
01412 /**
01413   * @brief  Clears the ETHERNET DMA IT pending bit.
01414   * @param  __HANDLE__   : ETH Handle
01415   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
01416   * @retval None
01417   */
01418 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
01419
01420 /**
01421   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01422 * @param  __HANDLE__: ETH Handle
01423   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
01424   * @retval The state of ETH DMA FLAG (SET or RESET).
01425   */
01426 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
01427
01428 /**
01429   * @brief  Clears the specified ETHERNET DMA flag.
01430 * @param  __HANDLE__: ETH Handle
01431   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
01432   * @retval The state of ETH DMA FLAG (SET or RESET).
01433   */
01434 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
01435
01436 /**
01437   * @brief  Enables the specified ETHERNET MAC interrupts.
01438   * @param  __HANDLE__   : ETH Handle
01439   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01440   *   enabled @ref ETH_MAC_Interrupts
01441   * @retval None
01442   */
01443 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
01444
01445 /**
01446   * @brief  Disables the specified ETHERNET MAC interrupts.
01447   * @param  __HANDLE__   : ETH Handle
01448   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01449   *   enabled @ref ETH_MAC_Interrupts
01450   * @retval None
01451   */
01452 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
01453
01454 /**
01455   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
01456   * @param  __HANDLE__: ETH Handle
01457   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
01458   * @retval The state of ETH MAC IT (SET or RESET).
01459   */
01460 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
01461
01462 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
01463 #define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000U)  /* !<  86 - 64 = 22 */
01464
01465 /**
01466   * @brief Enable the ETH WAKEUP Exti Line.
01467   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
01468   *   @arg ETH_WAKEUP_EXTI_LINE
01469   * @retval None.
01470   */
01471 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
01472
01473 /**
01474   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
01475   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01476   *   @arg ETH_WAKEUP_EXTI_LINE
01477   * @retval EXTI ETH WAKEUP Line Status.
01478   */
01479 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
01480
01481 /**
01482   * @brief Clear the ETH WAKEUP Exti flag.
01483   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01484   *   @arg ETH_WAKEUP_EXTI_LINE
01485   * @retval None.
01486   */
01487 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
01488
01489 #if defined(DUAL_CORE)
01490 /**
01491   * @brief Enable the ETH WAKEUP Exti Line by Core2.
01492   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
01493   *   @arg ETH_WAKEUP_EXTI_LINE
01494   * @retval None.
01495   */
01496 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))
01497
01498 /**
01499   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
01500   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01501   *   @arg ETH_WAKEUP_EXTI_LINE
01502   * @retval EXTI ETH WAKEUP Line Status.
01503   */
01504 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))
01505
01506 /**
01507   * @brief Clear the ETH WAKEUP Exti flag.
01508   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01509   *   @arg ETH_WAKEUP_EXTI_LINE
01510   * @retval None.
01511   */
01512 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
01513 #endif
01514
01515 /**
01516   * @brief  enable rising edge interrupt on selected EXTI line.
01517   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01518   *  @arg ETH_WAKEUP_EXTI_LINE
01519   * @retval None
01520   */
01521 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
01522                                                                 (EXTI->RTSR3 |= (__EXTI_LINE__))
01523
01524 /**
01525   * @brief  enable falling edge interrupt on selected EXTI line.
01526   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01527   *  @arg ETH_WAKEUP_EXTI_LINE
01528   * @retval None
01529   */
01530 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
01531                                                                  (EXTI->FTSR3 |= (__EXTI_LINE__))
01532
01533 /**
01534   * @brief  enable falling edge interrupt on selected EXTI line.
01535   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01536   *  @arg ETH_WAKEUP_EXTI_LINE
01537   * @retval None
01538   */
01539 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
01540                                                                         (EXTI->FTSR3 |= (__EXTI_LINE__))
01541
01542 /**
01543   * @brief  Generates a Software interrupt on selected EXTI line.
01544   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01545   *  @arg ETH_WAKEUP_EXTI_LINE
01546   * @retval None
01547   */
01548 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
01549
01550 /**
01551   * @}
01552   */
01553
01554 /* Include ETH HAL Extension module */
01555 #include "stm32h7xx_hal_eth_ex.h"
01556
01557 /* Exported functions --------------------------------------------------------*/
01558
01559 /** @addtogroup ETH_Exported_Functions
01560   * @{
01561   */
01562
01563 /** @addtogroup ETH_Exported_Functions_Group1
01564   * @{
01565   */
01566 /* Initialization and de initialization functions  **********************************/
01567 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
01568 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
01569 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
01570 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
01571 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
01572
01573 /* Callbacks Register/UnRegister functions  ***********************************/
01574 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
01575 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
01576 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
01577 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
01578
01579 /**
01580   * @}
01581   */
01582
01583 /** @addtogroup ETH_Exported_Functions_Group2
01584   * @{
01585   */
01586 /* IO operation functions *******************************************************/
01587 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
01588 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
01589 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
01590 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
01591
01592 uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
01593 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
01594 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
01595 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
01596 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
01597
01598 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
01599 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
01600
01601 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
01602 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
01603
01604 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
01605 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
01606 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
01607 void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
01608 void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
01609 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
01610 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
01611 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
01612 /**
01613   * @}
01614   */
01615
01616 /** @addtogroup ETH_Exported_Functions_Group3
01617   * @{
01618   */
01619 /* Peripheral Control functions  **********************************************/
01620 /* MAC & DMA Configuration APIs  **********************************************/
01621 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
01622 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
01623 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
01624 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
01625 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
01626
01627 /* MAC VLAN Processing APIs    ************************************************/
01628 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
01629
01630 /* MAC L2 Packet Filtering APIs  **********************************************/
01631 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
01632 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
01633 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
01634 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
01635
01636 /* MAC Power Down APIs    *****************************************************/
01637 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
01638 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
01639 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
01640
01641 /**
01642   * @}
01643   */
01644
01645 /** @addtogroup ETH_Exported_Functions_Group4
01646   * @{
01647   */
01648 /* Peripheral State functions  **************************************************/
01649 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
01650 uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);
01651 uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
01652 uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
01653 uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
01654 /**
01655   * @}
01656   */
01657
01658 /**
01659   * @}
01660   */
01661
01662 /**
01663   * @}
01664   */
01665
01666 /**
01667   * @}
01668   */
01669
01670 #endif /* ETH */
01671
01672 #ifdef __cplusplus
01673 }
01674 #endif
01675
01676 #endif /* STM32H7xx_HAL_ETH_H */
01677
01678
01679
01680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth_ex.c Source File

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stm32h7xx_hal_eth_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth_ex.c
00004   * @author  MCD Application Team
00005   * @brief   ETH HAL Extended module driver.
00006   *
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00011   * All rights reserved.</center></h2>
00012   *
00013   * This software component is licensed by ST under BSD 3-Clause license,
00014   * the "License"; You may not use this file except in compliance with the
00015   * License. You may obtain a copy of the License at:
00016   *                        opensource.org/licenses/BSD-3-Clause
00017   *
00018   ******************************************************************************
00019   */
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_hal.h"
00023
00024 /** @addtogroup STM32H7xx_HAL_Driver
00025   * @{
00026   */
00027
00028 #ifdef HAL_ETH_MODULE_ENABLED
00029
00030 #if defined(ETH)
00031
00032 /** @defgroup ETHEx ETHEx
00033   * @brief ETH HAL Extended module driver
00034   * @{
00035   */
00036
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 /** @defgroup ETHEx_Private_Constants ETHEx Private Constants
00041   * @{
00042   */
00043 #define ETH_MACL4CR_MASK     (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
00044                               ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
00045                               ETH_MACL3L4CR_L4DPIM)
00046
00047 #define ETH_MACL3CR_MASK     (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
00048                               ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
00049                               ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
00050                               ETH_MACL3L4CR_L3HDBM)
00051
00052 #define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
00053                             ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
00054                             ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
00055                             ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
00056                             ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
00057                             ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
00058
00059 #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
00060                             ETH_MACVIR_VLP | ETH_MACVIR_VLC)
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macros ------------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067 /* Exported functions ---------------------------------------------------------*/
00068 /** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
00069   * @{
00070   */
00071
00072 /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
00073   * @brief    Extended features functions
00074  *
00075 @verbatim
00076  ===============================================================================
00077                       ##### Extended features functions #####
00078  ===============================================================================
00079     [..] This section provides functions allowing to:
00080       (+) Configure ARP offload module
00081       (+) Configure L3 and L4 filters
00082       (+) Configure Extended VLAN features
00083       (+) Configure Energy Efficient Ethernet module
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Enables ARP Offload.
00091   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00092   *         the configuration information for ETHERNET module
00093   * @retval None
00094   */
00095 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
00096 {
00097   SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
00098 }
00099
00100 /**
00101   * @brief  Disables ARP Offload.
00102   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00103   *         the configuration information for ETHERNET module
00104   * @retval None
00105   */
00106 void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
00107 {
00108   CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
00109 }
00110
00111 /**
00112   * @brief  Set the ARP Match IP address
00113   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00114   *         the configuration information for ETHERNET module
00115   * @param  IpAddress: IP Address to be matched for incoming ARP requests
00116   * @retval None
00117   */
00118 void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
00119 {
00120   WRITE_REG(heth->Instance->MACARPAR, IpAddress);
00121 }
00122
00123 /**
00124   * @brief  Configures the L4 Filter, this function allow to:
00125   *         set the layer 4 protocol to be matched (TCP or UDP)
00126   *         enable/disable L4 source/destination port perfect/inverse match.
00127   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00128   *         the configuration information for ETHERNET module
00129   * @param  Filter: L4 filter to configured, this parameter must be one of the following
00130   *           ETH_L4_FILTER_0
00131   *           ETH_L4_FILTER_1
00132   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
00133   *         that contains L4 filter configuration.
00134   * @retval HAL status
00135   */
00136 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
00137 {
00138   __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
00139
00140   if(pL4FilterConfig == NULL)
00141   {
00142     return HAL_ERROR;
00143   }
00144
00145   /* Write configuration to (MACL3L4C0R + filter )register */
00146   MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
00147                                             pL4FilterConfig->SrcPortFilterMatch |
00148                                               pL4FilterConfig->DestPortFilterMatch));
00149
00150   configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
00151
00152   /* Write configuration to (MACL4A0R + filter )register */
00153   MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
00154                                                                                                                   (pL4FilterConfig->DestinationPort << 16)));
00155
00156   /* Enable L4 filter */
00157   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00158
00159   return HAL_OK;
00160 }
00161
00162 /**
00163   * @brief  Configures the L4 Filter, this function allow to:
00164   *         set the layer 4 protocol to be matched (TCP or UDP)
00165   *         enable/disable L4 source/destination port perfect/inverse match.
00166   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00167   *         the configuration information for ETHERNET module
00168   * @param  Filter: L4 filter to configured, this parameter must be one of the following
00169   *           ETH_L4_FILTER_0
00170   *           ETH_L4_FILTER_1
00171   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
00172   *         that contains L4 filter configuration.
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
00176 {
00177   if(pL4FilterConfig == NULL)
00178   {
00179     return HAL_ERROR;
00180   }
00181
00182   /* Get configuration to (MACL3L4C0R + filter )register */
00183   pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
00184   pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
00185   pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
00186
00187   /* Get configuration to (MACL3L4C0R + filter )register */
00188   pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
00189   pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
00190
00191   return HAL_OK;
00192 }
00193
00194 /**
00195   * @brief  Configures the L3 Filter, this function allow to:
00196   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
00197   *         enable/disable L3 source/destination port perfect/inverse match.
00198   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00199   *         the configuration information for ETHERNET module
00200   * @param  Filter: L3 filter to configured, this parameter must be one of the following
00201   *           ETH_L3_FILTER_0
00202   *           ETH_L3_FILTER_1
00203   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
00204   *         that contains L3 filter configuration.
00205   * @retval HAL status
00206   */
00207 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
00208 {
00209   __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
00210
00211   if(pL3FilterConfig == NULL)
00212   {
00213     return HAL_ERROR;
00214   }
00215
00216   /* Write configuration to (MACL3L4C0R + filter )register */
00217   MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
00218                                             pL3FilterConfig->SrcAddrFilterMatch |
00219                                               pL3FilterConfig->DestAddrFilterMatch |
00220                                                 (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
00221                                                   (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
00222
00223   /* Check if IPv6 protocol is selected */
00224   if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
00225   {
00226     /* Set the IPv6 address match */
00227     /* Set Bits[31:0] of 128-bit IP addr */
00228     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
00229     /* Set Bits[63:32] of 128-bit IP addr */
00230     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
00231     /* update Bits[95:64] of 128-bit IP addr */
00232     *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
00233     /* update Bits[127:96] of 128-bit IP addr */
00234     *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
00235   }
00236   else /* IPv4 protocol is selected */
00237   {
00238     /* Set the IPv4 source address match */
00239     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
00240     /* Set the IPv4 destination address match */
00241     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
00242   }
00243
00244   return HAL_OK;
00245 }
00246
00247 /**
00248   * @brief  Configures the L3 Filter, this function allow to:
00249   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
00250   *         enable/disable L3 source/destination port perfect/inverse match.
00251   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00252   *         the configuration information for ETHERNET module
00253   * @param  Filter: L3 filter to configured, this parameter must be one of the following
00254   *           ETH_L3_FILTER_0
00255   *           ETH_L3_FILTER_1
00256   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
00257   *         that will contain the L3 filter configuration.
00258   * @retval HAL status
00259   */
00260 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
00261 {
00262   if(pL3FilterConfig == NULL)
00263   {
00264     return HAL_ERROR;
00265   }
00266
00267   pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
00268   pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
00269   pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
00270   pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
00271   pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
00272
00273   if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
00274   {
00275     pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
00276     pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
00277     pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
00278     pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
00279   }
00280   else
00281   {
00282     pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
00283     pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
00284   }
00285
00286   return HAL_OK;
00287 }
00288
00289 /**
00290   * @brief  Enables L3 and L4 filtering process.
00291   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00292   *         the configuration information for ETHERNET module
00293   * @retval None.
00294   */
00295 void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
00296 {
00297   /* Enable L3/L4 filter */
00298   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00299 }
00300
00301 /**
00302   * @brief  Disables L3 and L4 filtering process.
00303   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00304   *         the configuration information for ETHERNET module
00305   * @retval None.
00306   */
00307 void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
00308 {
00309   /* Disable L3/L4 filter */
00310   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00311 }
00312
00313 /**
00314   * @brief  Get the VLAN Configuration for Receive Packets.
00315   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00316   *         the configuration information for ETHERNET module
00317   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
00318   *         that will contain the VLAN filter configuration.
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
00322 {
00323   if(pVlanConfig == NULL)
00324   {
00325     return HAL_ERROR;
00326   }
00327
00328   pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
00329   pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
00330   pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
00331   pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
00332   pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
00333   pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
00334   pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
00335   pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
00336   pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
00337
00338   return HAL_OK;
00339 }
00340
00341 /**
00342   * @brief  Set the VLAN Configuration for Receive Packets.
00343   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00344   *         the configuration information for ETHERNET module
00345   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
00346   *         that contains VLAN filter configuration.
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
00350 {
00351   if(pVlanConfig == NULL)
00352   {
00353     return HAL_ERROR;
00354   }
00355
00356   /* Write config to MACVTR */
00357   MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
00358                                                           pVlanConfig->StripInnerVLANTag |
00359                                                             ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
00360                                                               ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
00361                                                                 ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
00362                                                                   ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
00363                                                                     pVlanConfig->StripVLANTag |
00364                                                                       pVlanConfig->VLANTypeCheck |
00365                                                                         ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
00366
00367   return HAL_OK;
00368 }
00369
00370 /**
00371   * @brief  Set the VLAN Hash Table
00372   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00373   *         the configuration information for ETHERNET module
00374   * @param  VLANHashTable: VLAN hash table 16 bit value
00375   * @retval None
00376   */
00377 void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
00378 {
00379   MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
00380 }
00381
00382 /**
00383   * @brief  Get the VLAN Configuration for Transmit Packets.
00384   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00385   *         the configuration information for ETHERNET module
00386   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00387   *                 ETH_OUTER_TX_VLANTAG
00388   *                 ETH_INNER_TX_VLANTAG
00389   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
00390   *         that will contain the Tx VLAN filter configuration.
00391   * @retval HAL Status.
00392   */
00393 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
00394 {
00395   if (pVlanConfig == NULL)
00396   {
00397     return HAL_ERROR;
00398   }
00399
00400   if(VLANTag == ETH_INNER_TX_VLANTAG)
00401   {
00402     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
00403     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
00404     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
00405   }
00406   else
00407   {
00408     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
00409     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
00410     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
00411   }
00412
00413   return HAL_OK;;
00414 }
00415
00416 /**
00417   * @brief  Set the VLAN Configuration for Transmit Packets.
00418   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00419   *         the configuration information for ETHERNET module
00420   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00421   *                 ETH_OUTER_TX_VLANTAG
00422   *                 ETH_INNER_TX_VLANTAG
00423   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
00424   *         that contains Tx VLAN filter configuration.
00425   * @retval HAL Status
00426   */
00427 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
00428 {
00429   if(VLANTag == ETH_INNER_TX_VLANTAG)
00430   {
00431     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
00432                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
00433                                                               pVlanConfig->VLANTagControl));
00434     /* Enable Double VLAN processing */
00435     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
00436   }
00437   else
00438   {
00439     MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
00440                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
00441                                                               pVlanConfig->VLANTagControl));
00442   }
00443
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  Set the VLAN Tag Identifier for Transmit Packets.
00449   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00450   *         the configuration information for ETHERNET module
00451   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00452   *                 ETH_OUTER_TX_VLANTAG
00453   *                 ETH_INNER_TX_VLANTAG
00454   * @param  VLANIdentifier: VLAN Identifier 16 bit value
00455   * @retval None
00456   */
00457 void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
00458 {
00459   if(VLANTag == ETH_INNER_TX_VLANTAG)
00460   {
00461     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
00462   }
00463   else
00464   {
00465     MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
00466   }
00467 }
00468
00469 /**
00470   * @brief  Enables the VLAN Tag Filtering process.
00471   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00472   *         the configuration information for ETHERNET module
00473   * @retval None.
00474   */
00475 void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
00476 {
00477   /* Enable VLAN processing */
00478   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
00479 }
00480
00481 /**
00482   * @brief  Disables the VLAN Tag Filtering process.
00483   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00484   *         the configuration information for ETHERNET module
00485   * @retval None.
00486   */
00487 void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
00488 {
00489   /* Disable VLAN processing */
00490   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
00491 }
00492
00493 /**
00494   * @brief  Enters the Low Power Idle (LPI) mode
00495   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00496   *         the configuration information for ETHERNET module
00497   * @param  TxAutomate: Enable/Disbale automate enter/exit LPI mode.
00498   * @param  TxClockStop: Enable/Disbale Tx clock stop in LPI mode.
00499   * @retval None
00500   */
00501 void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
00502 {
00503   /* Enable LPI Interrupts */
00504   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
00505
00506   /* Write to LPI Control register: Enter low power mode */
00507   MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
00508                                                                                                        ((uint32_t)TxClockStop << 21) |
00509                                                                                                          ETH_MACLCSR_LPIEN));
00510 }
00511
00512 /**
00513   * @brief  Exits the Low Power Idle (LPI) mode.
00514   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00515   *         the configuration information for ETHERNET module
00516   * @retval None
00517   */
00518 void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
00519 {
00520   /* Clear the LPI Config and exit low power mode */
00521   CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
00522
00523   /* Enable LPI Interrupts */
00524   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
00525 }
00526
00527
00528 /**
00529   * @brief  Returns the ETH MAC LPI event
00530   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00531   *         the configuration information for ETHERNET module
00532   * @retval ETH MAC WakeUp event
00533   */
00534 uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
00535 {
00536   return heth->MACLPIEvent;
00537 }
00538
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
00551 #endif /* ETH */
00552
00553 #endif /* HAL_ETH_MODULE_ENABLED */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_eth_ex.h Source File

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stm32h7xx_hal_eth_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ETH HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_ETH_EX_H
00022 #define STM32H7xx_HAL_ETH_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 #if defined(ETH)
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32h7xx_hal_def.h"
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup ETHEx
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup ETHEx_Exported_Types ETHEx Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  ETH RX VLAN structure definition
00048   */
00049 typedef struct{
00050   FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */
00051
00052   uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive
00053                                                   This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
00054
00055   FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */
00056
00057   FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */
00058
00059   FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */
00060
00061   FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */
00062
00063   uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive
00064                                                   This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
00065
00066   uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check
00067                                                   This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
00068
00069   FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */
00070 }ETH_RxVLANConfigTypeDef;
00071 /**
00072   *
00073   */
00074
00075 /**
00076   * @brief  ETH TX VLAN structure definition
00077   */
00078 typedef struct{
00079   FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
00080
00081   FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */
00082
00083   uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets
00084                                       This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
00085 }ETH_TxVLANConfigTypeDef;
00086 /**
00087   *
00088   */
00089
00090 /**
00091   * @brief  ETH L3 filter structure definition
00092   */
00093 typedef struct{
00094   uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6
00095                                          This parameter can be a value of @ref ETHEx_L3_Protocol */
00096
00097   uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match
00098                                          This parameter can be a value of @ref ETHEx_L3_Source_Match */
00099
00100   uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match
00101                                          This parameter can be a value of @ref ETHEx_L3_Destination_Match */
00102
00103   uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match
00104                                          This parameter can be a value from 0 to 31 */
00105
00106   uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
00107                                          This parameter can be a value from 0 to 31 */
00108
00109   uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
00110                                          This parameter can be a value from 0x0 to 0xFFFFFFFF */
00111
00112   uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used
00113                                          This parameter can be a value from 0 to 0xFFFFFFFF  */
00114
00115   uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
00116                                           This parameter must be a table of 4 words (4* 32 bits) */
00117 }ETH_L3FilterConfigTypeDef;
00118 /**
00119   *
00120   */
00121
00122 /**
00123   * @brief  ETH L4 filter structure definition
00124   */
00125 typedef struct{
00126   uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP
00127                                         This parameter can be a value of @ref ETHEx_L4_Protocol */
00128
00129   uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match
00130                                         This parameter can be a value of @ref ETHEx_L4_Source_Match */
00131
00132   uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match
00133                                         This parameter can be a value of @ref ETHEx_L4_Destination_Match */
00134
00135   uint32_t SourcePort;             /*!< Sets the L4 filter source port
00136                                         This parameter must be a value from 0x0 to 0xFFFF */
00137
00138   uint32_t DestinationPort;        /*!< Sets the L4 filter destination port
00139                                         This parameter must be a value from 0x0 to 0xFFFF */
00140 }ETH_L4FilterConfigTypeDef;
00141 /**
00142   *
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /* Exported constants --------------------------------------------------------*/
00150 /** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
00151   * @{
00152   */
00153
00154 /** @defgroup ETHEx_LPI_Event ETHEx LPI Event
00155   * @{
00156   */
00157 #define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN
00158 #define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX
00159 #define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN
00160 #define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
00166   * @{
00167   */
00168 #define ETH_L3_FILTER_0                 ((uint32_t)0x00000000)
00169 #define ETH_L3_FILTER_1                 ((uint32_t)0x0000000C)
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
00175   * @{
00176   */
00177 #define ETH_L4_FILTER_0                 ((uint32_t)0x00000000)
00178 #define ETH_L4_FILTER_1                 ((uint32_t)0x0000000C)
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
00184   * @{
00185   */
00186 #define ETH_L3_IPV6_MATCH                       ETH_MACL3L4CR_L3PEN
00187 #define ETH_L3_IPV4_MATCH                       ((uint32_t)0x00000000)
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
00193   * @{
00194   */
00195 #define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L3SAM
00196 #define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
00197 #define ETH_L3_SRC_ADDR_MATCH_DISABLE           ((uint32_t)0x00000000)
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
00203   * @{
00204   */
00205 #define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L3DAM
00206 #define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
00207 #define ETH_L3_DEST_ADDR_MATCH_DISABLE          ((uint32_t)0x00000000)
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
00213   * @{
00214   */
00215 #define ETH_L4_UDP_MATCH                        ETH_MACL3L4CR_L4PEN
00216 #define ETH_L4_TCP_MATCH                        ((uint32_t)0x00000000)
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
00222   * @{
00223   */
00224 #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L4SPM
00225 #define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
00226 #define ETH_L4_SRC_PORT_MATCH_DISABLE           ((uint32_t)0x00000000)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
00232   * @{
00233   */
00234 #define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L4DPM
00235 #define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
00236 #define ETH_L4_DEST_PORT_MATCH_DISABLE          ((uint32_t)0x00000000)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
00242   * @{
00243   */
00244 #define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EIVLS_DONOTSTRIP
00245 #define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EIVLS_STRIPIFPASS
00246 #define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS
00247 #define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EIVLS_ALWAYSSTRIP
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
00253   * @{
00254   */
00255 #define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EVLS_DONOTSTRIP
00256 #define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EVLS_STRIPIFPASS
00257 #define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS
00258 #define ETH_VLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EVLS_ALWAYSSTRIP
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
00264   * @{
00265   */
00266 #define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTR_DOVLTC
00267 #define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
00268 #define ETH_VLANTYPECHECK_CVLAN      ((uint32_t)0x00000000)
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
00274   * @{
00275   */
00276 #define ETH_VLANTAGCONTROL_NONE       (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
00277 #define ETH_VLANTAGCONTROL_DELETE     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
00278 #define ETH_VLANTAGCONTROL_INSERT     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
00279 #define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
00285   * @{
00286   */
00287 #define ETH_INNER_TX_VLANTAG    ((uint32_t)0x00000001U)
00288 #define ETH_OUTER_TX_VLANTAG    ((uint32_t)0x00000000U)
00289 /**
00290   * @}
00291   */
00292
00293 /**
00294   * @}
00295   */
00296
00297 /* Exported functions --------------------------------------------------------*/
00298 /** @addtogroup ETHEx_Exported_Functions
00299   * @{
00300   */
00301
00302 /** @addtogroup ETHEx_Exported_Functions_Group1
00303   * @{
00304   */
00305 /* MAC ARP Offloading APIs  ***************************************************/
00306 void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
00307 void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
00308 void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
00309
00310 /* MAC L3 L4 Filtering APIs ***************************************************/
00311 void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
00312 void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
00313 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
00314 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
00315 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
00316 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
00317
00318 /* MAC VLAN Processing APIs    ************************************************/
00319 void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
00320 void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
00321 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
00322 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
00323 void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
00324 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
00325 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
00326 void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
00327
00328 /* Energy Efficient Ethernet APIs *********************************************/
00329 void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
00330 void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
00331 uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
00332
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 #endif /* ETH */
00350
00351 #ifdef __cplusplus
00352 }
00353 #endif
00354
00355 #endif /* STM32H7xx_HAL_ETH_EX_H */
00356
00357 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_exti.c Source File

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stm32h7xx_hal_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### EXTI Peripheral features #####
00014   ==============================================================================
00015   [..]
00016     (+) Each Exti line can be configured within this driver.
00017
00018     (+) Exti line can be configured in 3 different modes
00019         (++) Interrupt (CORE1 or CORE2 in case of dual core line )
00020         (++) Event (CORE1 or CORE2 in case of dual core line )
00021         (++) a combination of the previous
00022
00023     (+) Configurable Exti lines can be configured with 3 different triggers
00024         (++) Rising
00025         (++) Falling
00026         (++) Both of them
00027
00028     (+) When set in interrupt mode, configurable Exti lines have two diffenrents
00029         interrupt pending registers which allow to distinguish which transition
00030         occurs:
00031         (++) Rising edge pending interrupt
00032         (++) Falling
00033
00034     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
00035         be selected throught multiplexer.
00036
00037     (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
00038         It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
00039         Value can be one of the following:
00040         (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
00041               In this case corresponding bit of D2PMRx register is set to 0
00042                 (+++) On a configurable Line : the D3 domain wakeup signal is
00043                       automatically cleared after after the Delay + Rising Edge detect
00044                 (+++) On a direct Line : the D3 domain wakeup signal is
00045                       cleared after the direct event input signal is cleared
00046
00047         (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
00048               In this case corresponding bit of D2PMRx register is set to 1
00049               and corresponding bits(2) of D3PCRxL/H is set to b00 :
00050                 DMA ch6 event selected as D3 domain pendclear source
00051
00052         (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
00053               In this case corresponding bit of D2PMRx register is set to 1
00054               and corresponding bits(2) of D3PCRxL/H is set to b01 :
00055                 DMA ch7 event selected as D3 domain pendclear source
00056
00057         (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
00058               In this case corresponding bit of D2PMRx register is set to 1
00059               and corresponding bits(2) of D3PCRxL/H is set to b10 :
00060                 LPTIM4 out selected as D3 domain pendclear source
00061
00062         (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
00063               In this case corresponding bit of D2PMRx register is set to 1
00064               and corresponding bits(2) of D3PCRxL/H is set to b11 :
00065                 LPTIM5 out selected as D3 domain pendclear source
00066
00067
00068                      ##### How to use this driver #####
00069   ==============================================================================
00070   [..]
00071
00072     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
00073         (++) Choose the interrupt line number by setting "Line" member from
00074              EXTI_ConfigTypeDef structure.
00075         (++) Configure the interrupt and/or event mode using "Mode" member from
00076              EXTI_ConfigTypeDef structure.
00077         (++) For configurable lines, configure rising and/or falling trigger
00078              "Trigger" member from EXTI_ConfigTypeDef structure.
00079         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
00080              member from GPIO_InitTypeDef structure.
00081         (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
00082              choose gpio D3 PendClearSource using PendClearSource
00083              member from EXTI_PendClear_Source structure.
00084
00085     (#) Get current Exti configuration of a dedicated line using
00086         HAL_EXTI_GetConfigLine().
00087         (++) Provide exiting handle as parameter.
00088         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
00089
00090     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
00091         (++) Provide exiting handle as parameter.
00092
00093     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
00094         (++) Provide exiting handle as first parameter.
00095         (++) Provide which callback will be registered using one value from
00096              EXTI_CallbackIDTypeDef.
00097         (++) Provide callback function pointer.
00098
00099     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
00100
00101     (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
00102
00103     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
00104
00105   @endverbatim
00106   ******************************************************************************
00107   * @attention
00108   *
00109   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00110   * All rights reserved.</center></h2>
00111   *
00112   * This software component is licensed by ST under BSD 3-Clause license,
00113   * the "License"; You may not use this file except in compliance with the
00114   * License. You may obtain a copy of the License at:
00115   *                        opensource.org/licenses/BSD-3-Clause
00116   *
00117   ******************************************************************************
00118   */
00119
00120 /* Includes ------------------------------------------------------------------*/
00121 #include "stm32h7xx_hal.h"
00122
00123 /** @addtogroup STM32H7xx_HAL_Driver
00124   * @{
00125   */
00126
00127 /** @addtogroup EXTI
00128   * @{
00129   */
00130
00131 #ifdef HAL_EXTI_MODULE_ENABLED
00132
00133 /* Private typedef -----------------------------------------------------------*/
00134 /* Private defines ------------------------------------------------------------*/
00135 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00136   * @{
00137   */
00138 #define EXTI_MODE_OFFSET                    0x04U   /* 0x10: offset between CPU IMR/EMR registers */
00139 #define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between CPU Rising/Falling configuration registers */
00140 /**
00141   * @}
00142   */
00143
00144 /* Private macros ------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /* Private function prototypes -----------------------------------------------*/
00147 /* Exported functions --------------------------------------------------------*/
00148
00149 /** @addtogroup EXTI_Exported_Functions
00150   * @{
00151   */
00152
00153 /** @addtogroup EXTI_Exported_Functions_Group1
00154  *  @brief    Configuration functions
00155  *
00156 @verbatim
00157  ===============================================================================
00158               ##### Configuration functions #####
00159  ===============================================================================
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Set configuration of a dedicated Exti line.
00167   * @param  hexti Exti handle.
00168   * @param  pExtiConfig Pointer on EXTI configuration to be set.
00169   * @retval HAL Status.
00170   */
00171 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00172 {
00173   __IO uint32_t *regaddr;
00174   uint32_t regval;
00175   uint32_t linepos;
00176   uint32_t maskline;
00177   uint32_t offset;
00178   uint32_t pcrlinepos;
00179
00180   /* Check null pointer */
00181   if ((hexti == NULL) || (pExtiConfig == NULL))
00182   {
00183     return HAL_ERROR;
00184   }
00185
00186   /* Check the parameters */
00187   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
00188   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
00189
00190   /* Assign line number to handle */
00191   hexti->Line = pExtiConfig->Line;
00192
00193   /* compute line register offset and line mask */
00194   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00195   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00196   maskline = (1UL << linepos);
00197
00198   /* Configure triggers for configurable lines */
00199   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
00200   {
00201     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
00202
00203     /* Configure rising trigger */
00204     regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00205     regval = *regaddr;
00206
00207     /* Mask or set line */
00208     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
00209     {
00210       regval |= maskline;
00211     }
00212     else
00213     {
00214       regval &= ~maskline;
00215     }
00216
00217     /* Store rising trigger mode */
00218     *regaddr = regval;
00219
00220     /* Configure falling trigger */
00221     regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00222     regval = *regaddr;
00223
00224     /* Mask or set line */
00225     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
00226     {
00227       regval |= maskline;
00228     }
00229     else
00230     {
00231       regval &= ~maskline;
00232     }
00233
00234     /* Store falling trigger mode */
00235     *regaddr = regval;
00236
00237     /* Configure gpio port selection in case of gpio exti line */
00238     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00239     {
00240       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
00241       assert_param(IS_EXTI_GPIO_PIN(linepos));
00242
00243       regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
00244       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
00245       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
00246       SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
00247     }
00248   }
00249
00250   /* Configure interrupt mode : read current mode */
00251   regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00252   regval = *regaddr;
00253
00254   /* Mask or set line */
00255   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
00256   {
00257     regval |= maskline;
00258   }
00259   else
00260   {
00261     regval &= ~maskline;
00262   }
00263
00264   /* Store interrupt mode */
00265   *regaddr = regval;
00266
00267   /* The event mode cannot be configured if the line does not support it */
00268   assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
00269
00270   /* Configure event mode : read current mode */
00271   regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00272   regval = *regaddr;
00273
00274   /* Mask or set line */
00275   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
00276   {
00277     regval |= maskline;
00278   }
00279   else
00280   {
00281     regval &= ~maskline;
00282   }
00283
00284   /* Store event mode */
00285   *regaddr = regval;
00286
00287 #if defined (DUAL_CORE)
00288   /* Configure interrupt mode for Core2 : read current mode */
00289   regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
00290   regval = *regaddr;
00291
00292   /* Mask or set line */
00293   if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
00294   {
00295     regval |= maskline;
00296   }
00297   else
00298   {
00299     regval &= ~maskline;
00300   }
00301
00302   /* Store interrupt mode */
00303   *regaddr = regval;
00304
00305   /* The event mode cannot be configured if the line does not support it */
00306   assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
00307
00308   /* Configure event mode : read current mode */
00309   regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
00310   regval = *regaddr;
00311
00312   /* Mask or set line */
00313   if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
00314   {
00315     regval |= maskline;
00316   }
00317   else
00318   {
00319     regval &= ~maskline;
00320   }
00321
00322   /* Store event mode */
00323   *regaddr = regval;
00324 #endif /* DUAL_CORE */
00325
00326   /* Configure the D3 PendClear source in case of Wakeup target is Any */
00327   if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
00328   {
00329     assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
00330
00331     /*Calc the PMR register address for the given line */
00332     regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
00333     regval = *regaddr;
00334
00335     if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
00336     {
00337       /* Clear D3PMRx register for the given line */
00338       regval &= ~maskline;
00339       /* Store D3PMRx register value */
00340       *regaddr = regval;
00341     }
00342     else
00343     {
00344       /* Set D3PMRx register to 1 for the given line */
00345       regval |= maskline;
00346       /* Store D3PMRx register value */
00347       *regaddr = regval;
00348
00349       if(linepos < 16UL)
00350       {
00351         regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
00352         pcrlinepos = 1UL << linepos;
00353       }
00354       else
00355       {
00356         regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
00357         pcrlinepos = 1UL << (linepos - 16UL);
00358       }
00359
00360       regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
00361       *regaddr = regval;
00362     }
00363   }
00364
00365   return HAL_OK;
00366 }
00367
00368
00369 /**
00370   * @brief  Get configuration of a dedicated Exti line.
00371   * @param  hexti Exti handle.
00372   * @param  pExtiConfig Pointer on structure to store Exti configuration.
00373   * @retval HAL Status.
00374   */
00375 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00376 {
00377   __IO uint32_t *regaddr;
00378   uint32_t regval;
00379   uint32_t linepos;
00380   uint32_t maskline;
00381   uint32_t offset;
00382   uint32_t pcrlinepos;
00383
00384   /* Check null pointer */
00385   if ((hexti == NULL) || (pExtiConfig == NULL))
00386   {
00387     return HAL_ERROR;
00388   }
00389
00390   /* Check the parameter */
00391   assert_param(IS_EXTI_LINE(hexti->Line));
00392
00393   /* Store handle line number to configuration structure */
00394   pExtiConfig->Line = hexti->Line;
00395
00396   /* compute line register offset and line mask */
00397   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00398   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00399   maskline = (1UL << linepos);
00400
00401   /* 1] Get core mode : interrupt */
00402   regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00403   regval = *regaddr;
00404
00405   pExtiConfig->Mode = EXTI_MODE_NONE;
00406
00407   /* Check if selected line is enable */
00408   if ((regval & maskline) != 0x00U)
00409   {
00410     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
00411   }
00412
00413   /* Get event mode */
00414   regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00415   regval = *regaddr;
00416
00417   /* Check if selected line is enable */
00418   if ((regval & maskline) != 0x00U)
00419   {
00420     pExtiConfig->Mode |= EXTI_MODE_EVENT;
00421   }
00422 #if defined (DUAL_CORE)
00423   regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
00424   regval = *regaddr;
00425
00426   /* Check if selected line is enable */
00427   if ((regval & maskline) != 0x00U)
00428   {
00429     pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
00430   }
00431
00432   /* Get event mode */
00433   regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
00434   regval = *regaddr;
00435
00436   /* Check if selected line is enable */
00437   if ((regval & maskline) != 0x00U)
00438   {
00439     pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
00440   }
00441 #endif /*DUAL_CORE*/
00442
00443   /* 2] Get trigger for configurable lines : rising */
00444   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
00445   {
00446     regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00447     regval = *regaddr;
00448
00449     /* Check if configuration of selected line is enable */
00450     if ((regval & maskline) != 0x00U)
00451     {
00452       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
00453     }
00454     else
00455     {
00456       pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00457     }
00458
00459     /* Get falling configuration */
00460     regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00461     regval = *regaddr;
00462
00463     /* Check if configuration of selected line is enable */
00464     if ((regval & maskline) != 0x00U)
00465     {
00466       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
00467     }
00468
00469     /* Get Gpio port selection for gpio lines */
00470     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00471     {
00472       assert_param(IS_EXTI_GPIO_PIN(linepos));
00473
00474       regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
00475       pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
00476     }
00477     else
00478     {
00479       pExtiConfig->GPIOSel = 0x00U;
00480     }
00481   }
00482   else
00483   {
00484     pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00485     pExtiConfig->GPIOSel = 0x00U;
00486   }
00487
00488   /* 3] Get D3 Pend Clear source */
00489   if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
00490   {
00491     regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
00492     if(((*regaddr) & linepos) == 0UL)
00493     {
00494       /* if PMR unset, then no pend clear source is used */
00495       pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
00496     }
00497     else
00498     {
00499       /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
00500       if(linepos < 16UL)
00501       {
00502         regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
00503         pcrlinepos = 1UL << linepos;
00504       }
00505       else
00506       {
00507         regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
00508         pcrlinepos = 1UL << (linepos - 16UL);
00509       }
00510
00511       pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
00512     }
00513   }
00514   else
00515   {
00516     /* if line wakeup target is not any, then no pend clear source is used  */
00517     pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
00518   }
00519
00520   return HAL_OK;
00521 }
00522
00523
00524 /**
00525   * @brief  Clear whole configuration of a dedicated Exti line.
00526   * @param  hexti Exti handle.
00527   * @retval HAL Status.
00528   */
00529 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
00530 {
00531   __IO uint32_t *regaddr;
00532   uint32_t regval;
00533   uint32_t linepos;
00534   uint32_t maskline;
00535   uint32_t offset;
00536   uint32_t pcrlinepos;
00537
00538   /* Check null pointer */
00539   if (hexti == NULL)
00540   {
00541     return HAL_ERROR;
00542   }
00543
00544   /* Check the parameter */
00545   assert_param(IS_EXTI_LINE(hexti->Line));
00546
00547   /* compute line register offset and line mask */
00548   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00549   linepos = (hexti->Line & EXTI_PIN_MASK);
00550   maskline = (1UL << linepos);
00551
00552   /* 1] Clear interrupt mode */
00553   regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00554   regval = (*regaddr & ~maskline);
00555   *regaddr = regval;
00556
00557   /* 2] Clear event mode */
00558   regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00559   regval = (*regaddr & ~maskline);
00560   *regaddr = regval;
00561
00562 #if defined (DUAL_CORE)
00563     /* 1] Clear CM4 interrupt mode */
00564   regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
00565   regval = (*regaddr & ~maskline);
00566   *regaddr = regval;
00567
00568   /* 2] Clear CM4 event mode */
00569   regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
00570   regval = (*regaddr & ~maskline);
00571   *regaddr = regval;
00572 #endif /* DUAL_CORE */
00573
00574   /* 3] Clear triggers in case of configurable lines */
00575   if ((hexti->Line & EXTI_CONFIG) != 0x00U)
00576   {
00577     regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00578     regval = (*regaddr & ~maskline);
00579     *regaddr = regval;
00580
00581     regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00582     regval = (*regaddr & ~maskline);
00583     *regaddr = regval;
00584
00585     /* Get Gpio port selection for gpio lines */
00586     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
00587     {
00588       assert_param(IS_EXTI_GPIO_PIN(linepos));
00589
00590       regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
00591       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
00592       SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
00593     }
00594   }
00595
00596   /* 4] Clear D3 Config lines */
00597   if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
00598   {
00599     regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
00600     *regaddr = (*regaddr & ~maskline);
00601
00602     if(linepos < 16UL)
00603     {
00604       regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
00605       pcrlinepos = 1UL << linepos;
00606     }
00607     else
00608     {
00609       regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
00610       pcrlinepos = 1UL << (linepos - 16UL);
00611     }
00612
00613     /*Clear D3 PendClear source */
00614     *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
00615   }
00616
00617   return HAL_OK;
00618 }
00619
00620
00621 /**
00622   * @brief  Register callback for a dedicated Exti line.
00623   * @param  hexti Exti handle.
00624   * @param  CallbackID User callback identifier.
00625   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
00626   * @param  pPendingCbfn function pointer to be stored as callback.
00627   * @retval HAL Status.
00628   */
00629 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
00630 {
00631   HAL_StatusTypeDef status = HAL_OK;
00632
00633   /* Check null pointer */
00634   if (hexti == NULL)
00635   {
00636     return HAL_ERROR;
00637   }
00638
00639   switch (CallbackID)
00640   {
00641     case  HAL_EXTI_COMMON_CB_ID:
00642       hexti->PendingCallback = pPendingCbfn;
00643       break;
00644
00645     default:
00646       status = HAL_ERROR;
00647       break;
00648   }
00649
00650   return status;
00651 }
00652
00653
00654 /**
00655   * @brief  Store line number as handle private field.
00656   * @param  hexti Exti handle.
00657   * @param  ExtiLine Exti line number.
00658   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
00659   * @retval HAL Status.
00660   */
00661 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
00662 {
00663   /* Check the parameters */
00664   assert_param(IS_EXTI_LINE(ExtiLine));
00665
00666   /* Check null pointer */
00667   if (hexti == NULL)
00668   {
00669     return HAL_ERROR;
00670   }
00671   else
00672   {
00673     /* Store line number as handle private field */
00674     hexti->Line = ExtiLine;
00675
00676     return HAL_OK;
00677   }
00678 }
00679
00680
00681 /**
00682   * @}
00683   */
00684
00685 /** @addtogroup EXTI_Exported_Functions_Group2
00686  *  @brief EXTI IO functions.
00687  *
00688 @verbatim
00689  ===============================================================================
00690                        ##### IO operation functions #####
00691  ===============================================================================
00692
00693 @endverbatim
00694   * @{
00695   */
00696
00697 /**
00698   * @brief  Handle EXTI interrupt request.
00699   * @param  hexti Exti handle.
00700   * @retval none.
00701   */
00702 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
00703 {
00704   __IO uint32_t *regaddr;
00705   uint32_t regval;
00706   uint32_t maskline;
00707   uint32_t offset;
00708
00709   /* Compute line register offset and line mask */
00710   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00711   maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
00712
00713 #if defined(DUAL_CORE)
00714   if (HAL_GetCurrentCPUID() == CM7_CPUID)
00715   {
00716     /* Get pending register address */
00717     regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00718   }
00719   else /* Cortex-M4*/
00720   {
00721     /* Get pending register address */
00722     regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
00723   }
00724 #else
00725   regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00726 #endif /* DUAL_CORE */
00727
00728   /* Get pending bit  */
00729   regval = (*regaddr & maskline);
00730
00731   if (regval != 0x00U)
00732   {
00733     /* Clear pending bit */
00734     *regaddr = maskline;
00735
00736     /* Call callback */
00737     if (hexti->PendingCallback != NULL)
00738     {
00739       hexti->PendingCallback();
00740     }
00741   }
00742 }
00743
00744
00745 /**
00746   * @brief  Get interrupt pending bit of a dedicated line.
00747   * @param  hexti Exti handle.
00748   * @param  Edge Specify which pending edge as to be checked.
00749   *         This parameter can be one of the following values:
00750   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
00751   *         This parameter is kept for compatibility with other series.
00752   * @retval 1 if interrupt is pending else 0.
00753   */
00754 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00755 {
00756   __IO uint32_t *regaddr;
00757   uint32_t regval;
00758   uint32_t linepos;
00759   uint32_t maskline;
00760   uint32_t offset;
00761
00762   /* Check parameters */
00763   assert_param(IS_EXTI_LINE(hexti->Line));
00764   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00765   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00766
00767   /* compute line register offset and line mask */
00768   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00769   linepos = (hexti->Line & EXTI_PIN_MASK);
00770   maskline = (1UL << linepos);
00771
00772 #if defined(DUAL_CORE)
00773   if (HAL_GetCurrentCPUID() == CM7_CPUID)
00774   {
00775     /* Get pending register address */
00776     regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00777   }
00778   else /* Cortex-M4 */
00779   {
00780     /* Get pending register address */
00781     regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
00782   }
00783 #else
00784   regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00785 #endif /* DUAL_CORE */
00786
00787   /* return 1 if bit is set else 0 */
00788   regval = ((*regaddr & maskline) >> linepos);
00789   return regval;
00790 }
00791
00792
00793 /**
00794   * @brief  Clear interrupt pending bit of a dedicated line.
00795   * @param  hexti Exti handle.
00796   * @param  Edge Specify which pending edge as to be clear.
00797   *         This parameter can be one of the following values:
00798   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
00799   *         This parameter is kept for compatibility with other series.
00800   * @retval None.
00801   */
00802 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00803 {
00804   __IO uint32_t *regaddr;
00805   uint32_t maskline;
00806   uint32_t offset;
00807
00808   /* Check parameters */
00809   assert_param(IS_EXTI_LINE(hexti->Line));
00810   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00811   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00812
00813   /* compute line register offset and line mask */
00814   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00815   maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
00816
00817 #if defined(DUAL_CORE)
00818   if (HAL_GetCurrentCPUID() == CM7_CPUID)
00819   {
00820     /* Get pending register address */
00821     regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00822   }
00823   else /* Cortex-M4 */
00824   {
00825     /* Get pending register address */
00826     regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
00827   }
00828 #else
00829   regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
00830 #endif /* DUAL_CORE */
00831
00832   /* Clear Pending bit */
00833   *regaddr =  maskline;
00834 }
00835
00836 /**
00837   * @brief  Generate a software interrupt for a dedicated line.
00838   * @param  hexti Exti handle.
00839   * @retval None.
00840   */
00841 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
00842 {
00843   __IO uint32_t *regaddr;
00844   uint32_t maskline;
00845   uint32_t offset;
00846
00847   /* Check parameters */
00848   assert_param(IS_EXTI_LINE(hexti->Line));
00849   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00850
00851   /* compute line register offset and line mask */
00852   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00853   maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
00854
00855   regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
00856   *regaddr = maskline;
00857 }
00858
00859
00860 /**
00861   * @}
00862   */
00863
00864 /**
00865   * @}
00866   */
00867
00868 #endif /* HAL_EXTI_MODULE_ENABLED */
00869 /**
00870   * @}
00871   */
00872
00873 /**
00874   * @}
00875   */
00876
00877 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_exti.h Source File

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stm32h7xx_hal_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_EXTI_H
00022 #define STM32H7xx_HAL_EXTI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup EXTI EXTI
00036   * @brief EXTI HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup EXTI_Exported_Types EXTI Exported Types
00043   * @{
00044   */
00045 typedef enum
00046 {
00047   HAL_EXTI_COMMON_CB_ID          = 0x00U,
00048 } EXTI_CallbackIDTypeDef;
00049
00050
00051 /**
00052   * @brief  EXTI Handle structure definition
00053   */
00054 typedef struct
00055 {
00056   uint32_t Line;                    /*!<  Exti line number */
00057   void (* PendingCallback)(void);   /*!<  Exti pending callback */
00058 } EXTI_HandleTypeDef;
00059
00060 /**
00061   * @brief  EXTI Configuration structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Line;           /*!< The Exti line to be configured. This parameter
00066                                 can be a value of @ref EXTI_Line */
00067   uint32_t Mode;           /*!< The Exit Mode to be configured for a core.
00068                                 This parameter can be a combination of @ref EXTI_Mode */
00069   uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter
00070                                 can be a value of @ref EXTI_Trigger */
00071   uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.
00072                                 This parameter is only possible for line 0 to 15. It
00073                                 can be a value of @ref EXTI_GPIOSel */
00074
00075   uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD
00076                                  domain. This parameter can be a value of @ref
00077                                  EXTI_PendClear_Source */
00078
00079 } EXTI_ConfigTypeDef;
00080
00081 /**
00082   * @}
00083   */
00084
00085 /* Exported constants --------------------------------------------------------*/
00086 /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
00087   * @{
00088   */
00089
00090 /** @defgroup EXTI_Line  EXTI Line
00091   * @{
00092   */
00093 #define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)
00094 #define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)
00095 #define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)
00096 #define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)
00097 #define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)
00098 #define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)
00099 #define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)
00100 #define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)
00101 #define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)
00102 #define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)
00103 #define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)
00104 #define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)
00105 #define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)
00106 #define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)
00107 #define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)
00108 #define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)
00109 #define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
00110 #define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
00111 #define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
00112 #define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)
00113 #define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)
00114 #define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)
00115 #define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
00116 #define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
00117 #define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
00118 #define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)
00119 #define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
00120 #define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
00121 #define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
00122 #define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
00123 #define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
00124 #define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
00125 #define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
00126 #define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
00127 #define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)
00128 #define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)
00129 #define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
00130 #define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
00131 #define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
00132 #define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
00133 #define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
00134 #define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
00135 #define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
00136 #define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
00137 #if !defined(USB2_OTG_FS)
00138 #define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
00139 #else
00140 #define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
00141 #endif /* USB2_OTG_FS */
00142 #define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
00143 #if defined(DSI)
00144 #define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
00145 #else
00146 #define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
00147 #endif /* DSI */
00148 #define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
00149 #define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
00150 #define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
00151 #define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
00152 #define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
00153 #if !defined(UART9)
00154 #define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
00155 #else
00156 #define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
00157 #endif /* UART9 */
00158 #if !defined(USART10)
00159 #define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
00160 #else
00161 #define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
00162 #endif /* USART10 */
00163 #define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
00164 #define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
00165 #define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
00166 #define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
00167 #define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
00168 #define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
00169 #define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
00170 #define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
00171 #define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
00172 #define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
00173 #define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
00174 #define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
00175 #define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
00176 #define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
00177 #define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
00178 #define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
00179 #define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
00180 #define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
00181 #define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
00182 #define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
00183 #define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
00184 #if defined(ADC3)
00185 #define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
00186 #else
00187 #define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
00188 #endif /* ADC3 */
00189 #if defined(SAI4)
00190 #define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
00191 #else
00192 #define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
00193 #endif /* SAI4 */
00194 #if defined (DUAL_CORE)
00195 #define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
00196 #define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
00197 #define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
00198 #define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
00199 #else
00200 #define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
00201 #define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
00202 #define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
00203 #define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
00204 #endif /* DUAL_CORE */
00205
00206 #define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
00207
00208 #if defined (DUAL_CORE)
00209 #define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
00210 #else
00211 #define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
00212 #endif /* DUAL_CORE */
00213
00214 #define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
00215 #if defined (DUAL_CORE)
00216 #define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
00217 #else
00218 #define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
00219 #endif /* DUAL_CORE */
00220 #define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
00221 #if defined(ETH)
00222 #define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
00223 #else
00224 #define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
00225 #endif /* ETH */
00226 #define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
00227 #if defined(DTS)
00228 #define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
00229 #endif /* DTS */
00230
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup EXTI_Mode  EXTI Mode
00236   * @{
00237   */
00238 #define EXTI_MODE_NONE                      0x00000000U
00239 #define EXTI_MODE_INTERRUPT                 0x00000001U
00240 #define EXTI_MODE_EVENT                     0x00000002U
00241 #if defined(DUAL_CORE)
00242 #define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT
00243 #define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT
00244 #define EXTI_MODE_CORE2_INTERRUPT           0x00000010U
00245 #define EXTI_MODE_CORE2_EVENT               0x00000020U
00246 #endif /* DUAL_CORE */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup EXTI_Trigger  EXTI Trigger
00252   * @{
00253   */
00254 #define EXTI_TRIGGER_NONE                   0x00000000U
00255 #define EXTI_TRIGGER_RISING                 0x00000001U
00256 #define EXTI_TRIGGER_FALLING                0x00000002U
00257 #define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup EXTI_GPIOSel  EXTI GPIOSel
00263   * @brief
00264   * @{
00265   */
00266 #define EXTI_GPIOA                          0x00000000U
00267 #define EXTI_GPIOB                          0x00000001U
00268 #define EXTI_GPIOC                          0x00000002U
00269 #define EXTI_GPIOD                          0x00000003U
00270 #define EXTI_GPIOE                          0x00000004U
00271 #define EXTI_GPIOF                          0x00000005U
00272 #define EXTI_GPIOG                          0x00000006U
00273 #define EXTI_GPIOH                          0x00000007U
00274 #define EXTI_GPIOI                          0x00000008U
00275 #define EXTI_GPIOJ                          0x00000009U
00276 #define EXTI_GPIOK                          0x0000000AU
00277
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup EXTI_PendClear_Source  EXTI PendClear Source
00283   * @brief
00284   * @{
00285   */
00286 #define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
00287 #define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
00288 #define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
00289 #if defined (LPTIM4)
00290 #define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
00291 #else
00292 #define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
00293 #endif
00294 #if defined (LPTIM5)
00295 #define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
00296 #else
00297 #define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
00298 #endif
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /* Exported macro ------------------------------------------------------------*/
00308 /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
00309   * @{
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /* Private constants --------------------------------------------------------*/
00317 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00318   * @{
00319   */
00320 /**
00321   * @brief  EXTI Line property definition
00322   */
00323 #define EXTI_PROPERTY_SHIFT                 24U
00324 #define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
00325 #define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
00326 #define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
00327 #define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
00328 #define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
00329
00330 /**
00331   * @brief  EXTI Event presence definition
00332   */
00333 #define EXTI_EVENT_PRESENCE_SHIFT           28U
00334 #define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
00335 #define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
00336
00337 /**
00338   * @brief  EXTI Register and bit usage
00339   */
00340 #define EXTI_REG_SHIFT                      16U
00341 #define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
00342 #define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
00343 #define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)
00344 #define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
00345 #define EXTI_PIN_MASK                       0x0000001FUL
00346
00347 /**
00348   * @brief  EXTI Target and bit usage
00349   */
00350 #define EXTI_TARGET_SHIFT                   20U
00351 #define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)
00352 #define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)
00353 #define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)
00354 #if defined (DUAL_CORE)
00355 #define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)
00356 #define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
00357 #define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
00358 #else
00359 #define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
00360 #define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1
00361 #endif /* DUAL_CORE */
00362 #define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK
00363
00364 /**
00365   * @brief  EXTI Mask for interrupt & event mode
00366   */
00367 #if defined (DUAL_CORE)
00368 #define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
00369 #else
00370 #define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
00371 #endif /* DUAL_CORE */
00372
00373 /**
00374   * @brief  EXTI Mask for trigger possibilities
00375   */
00376 #define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00377
00378 /**
00379   * @brief  EXTI Line number
00380   */
00381 #if defined (EXTI_LINE_88)
00382 #define EXTI_LINE_NB                        89UL
00383 #else
00384 #define EXTI_LINE_NB                        88UL
00385 #endif /* EXTI_LINE_88 */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /* Private macros ------------------------------------------------------------*/
00392 /** @defgroup EXTI_Private_Macros EXTI Private Macros
00393   * @{
00394   */
00395 #define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
00396                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
00397                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
00398 #if defined (DUAL_CORE)
00399 #define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \
00400                                          (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \
00401                                          (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
00402                                          (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
00403 #else
00404 #define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
00405                                          (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
00406 #endif
00407
00408 #define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
00409                                          IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
00410                                          (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
00411                                          (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
00412
00413 #define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
00414
00415 #define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
00416
00417 #define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
00418                                          ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
00419                                          ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
00420
00421 #define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)
00422
00423 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00424                                          ((__PORT__) == EXTI_GPIOB) || \
00425                                          ((__PORT__) == EXTI_GPIOC) || \
00426                                          ((__PORT__) == EXTI_GPIOD) || \
00427                                          ((__PORT__) == EXTI_GPIOE) || \
00428                                          ((__PORT__) == EXTI_GPIOF) || \
00429                                          ((__PORT__) == EXTI_GPIOG) || \
00430                                          ((__PORT__) == EXTI_GPIOH) || \
00431                                          ((__PORT__) == EXTI_GPIOI) || \
00432                                          ((__PORT__) == EXTI_GPIOJ) || \
00433                                          ((__PORT__) == EXTI_GPIOK))
00434
00435 #define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
00436 #if defined (LPTIM4) && defined (LPTIM5)
00437 #define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
00438                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
00439                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
00440                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
00441                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
00442 #else
00443 #define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
00444                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
00445                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
00446                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
00447                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
00448 #endif /* LPTIM4 && LPTIM5 */
00449
00450 /**
00451   * @}
00452   */
00453
00454
00455 /* Exported functions --------------------------------------------------------*/
00456 /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
00457   * @brief    EXTI Exported Functions
00458   * @{
00459   */
00460
00461 /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
00462   * @brief    Configuration functions
00463   * @{
00464   */
00465 /* Configuration functions ****************************************************/
00466 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00467 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00468 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
00469 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
00470 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
00476   * @brief    IO operation functions
00477   * @{
00478   */
00479 /* IO operation functions *****************************************************/
00480 void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
00481 uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00482 void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00483 void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
00484
00485 /**
00486   * @}
00487   */
00488
00489 /**
00490   * @}
00491   */
00492
00493 /**
00494   * @}
00495   */
00496
00497 /**
00498   * @}
00499   */
00500
00501 #ifdef __cplusplus
00502 }
00503 #endif
00504
00505 #endif /* STM32H7xx_HAL_EXTI_H */
00506
00507 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:58 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_fdcan.c Source File

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stm32h7xx_hal_fdcan.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_fdcan.c
00004   * @author  MCD Application Team
00005   * @brief   FDCAN HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Flexible DataRate Controller Area Network
00008   *          (FDCAN) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Configuration and Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
00020
00021       (#) If needed , configure the reception filters and optional features using
00022           the following configuration functions:
00023             (++) HAL_FDCAN_ConfigClockCalibration
00024             (++) HAL_FDCAN_ConfigFilter
00025             (++) HAL_FDCAN_ConfigGlobalFilter
00026             (++) HAL_FDCAN_ConfigExtendedIdMask
00027             (++) HAL_FDCAN_ConfigRxFifoOverwrite
00028             (++) HAL_FDCAN_ConfigFifoWatermark
00029             (++) HAL_FDCAN_ConfigRamWatchdog
00030             (++) HAL_FDCAN_ConfigTimestampCounter
00031             (++) HAL_FDCAN_EnableTimestampCounter
00032             (++) HAL_FDCAN_DisableTimestampCounter
00033             (++) HAL_FDCAN_ConfigTimeoutCounter
00034             (++) HAL_FDCAN_EnableTimeoutCounter
00035             (++) HAL_FDCAN_DisableTimeoutCounter
00036             (++) HAL_FDCAN_ConfigTxDelayCompensation
00037             (++) HAL_FDCAN_EnableTxDelayCompensation
00038             (++) HAL_FDCAN_DisableTxDelayCompensation
00039             (++) HAL_FDCAN_EnableISOMode
00040             (++) HAL_FDCAN_DisableISOMode
00041             (++) HAL_FDCAN_EnableEdgeFiltering
00042             (++) HAL_FDCAN_DisableEdgeFiltering
00043             (++) HAL_FDCAN_TT_ConfigOperation
00044             (++) HAL_FDCAN_TT_ConfigReferenceMessage
00045             (++) HAL_FDCAN_TT_ConfigTrigger
00046
00047       (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
00048           the node is active on the bus: it can send and receive messages.
00049
00050       (#) The following Tx control functions can only be called when the FDCAN
00051           module is started:
00052             (++) HAL_FDCAN_AddMessageToTxFifoQ
00053             (++) HAL_FDCAN_EnableTxBufferRequest
00054             (++) HAL_FDCAN_AbortTxRequest
00055
00056       (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
00057           get Tx buffer location used to place the Tx request thanks to
00058           HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
00059           It is then possible to abort later on the corresponding Tx Request using
00060           HAL_FDCAN_AbortTxRequest API.
00061
00062       (#) When a message is received into the FDCAN message RAM, it can be
00063           retrieved using the HAL_FDCAN_GetRxMessage function.
00064
00065       (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
00066           it to initialization mode and re-enabling access to configuration
00067           registers through the configuration functions listed here above.
00068
00069       (#) All other control functions can be called any time after initialization
00070           phase, no matter if the FDCAN module is started or stoped.
00071
00072       *** Polling mode operation ***
00073       ==============================
00074
00075     [..]
00076         (#) Reception and transmission states can be monitored via the following
00077             functions:
00078               (++) HAL_FDCAN_IsRxBufferMessageAvailable
00079               (++) HAL_FDCAN_IsTxBufferMessagePending
00080               (++) HAL_FDCAN_GetRxFifoFillLevel
00081               (++) HAL_FDCAN_GetTxFifoFreeLevel
00082
00083       *** Interrupt mode operation ***
00084       ================================
00085       [..]
00086         (#) There are two interrupt lines: line 0 and 1.
00087             By default, all interrupts are assigned to line 0. Interrupt lines
00088             can be configured using HAL_FDCAN_ConfigInterruptLines function.
00089
00090         (#) Notifications are activated using HAL_FDCAN_ActivateNotification
00091             function. Then, the process can be controlled through one of the
00092             available user callbacks: HAL_FDCAN_xxxCallback.
00093
00094   *** Callback registration ***
00095   =============================================
00096
00097   The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
00098   allows the user to configure dynamically the driver callbacks.
00099   Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
00100   to register an interrupt callback.
00101
00102   Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
00103     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00104     (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
00105     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00106     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00107     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00108     (+) ErrorCallback                : Error Callback.
00109     (+) MspInitCallback              : FDCAN MspInit.
00110     (+) MspDeInitCallback            : FDCAN MspDeInit.
00111   This function takes as parameters the HAL peripheral handle, the Callback ID
00112   and a pointer to the user callback function.
00113
00114   For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
00115   TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
00116   TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
00117   respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
00118   @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
00119   @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
00120   @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
00121   @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
00122   @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
00123
00124   Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
00125   weak function.
00126   @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
00127   and the Callback ID.
00128   This function allows to reset following callbacks:
00129     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00130     (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
00131     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00132     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00133     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00134     (+) ErrorCallback                : Error Callback.
00135     (+) MspInitCallback              : FDCAN MspInit.
00136     (+) MspDeInitCallback            : FDCAN MspDeInit.
00137
00138   For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
00139   RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
00140   TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
00141   register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
00142   @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
00143   @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
00144   @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
00145   @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
00146   @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
00147
00148   By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
00149   all callbacks are set to the corresponding weak functions:
00150   examples @ref HAL_FDCAN_ErrorCallback().
00151   Exception done for MspInit and MspDeInit functions that are
00152   reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
00153   these callbacks are null (not registered beforehand).
00154   if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
00155   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00156
00157   Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
00158   Exception done MspInit/MspDeInit that can be registered/unregistered
00159   in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
00160   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00161   In that case first register the MspInit/MspDeInit user callbacks
00162   using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
00163   or @ref HAL_FDCAN_Init() function.
00164
00165   When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
00166   not defined, the callback registration feature is not available and all callbacks
00167   are set to the corresponding weak functions.
00168
00169   @endverbatim
00170
00171   ******************************************************************************
00172   * @attention
00173   *
00174   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00175   * All rights reserved.</center></h2>
00176   *
00177   * This software component is licensed by ST under BSD 3-Clause license,
00178   * the "License"; You may not use this file except in compliance with the
00179   * License. You may obtain a copy of the License at:
00180   *                        opensource.org/licenses/BSD-3-Clause
00181   *
00182   ******************************************************************************
00183   */
00184
00185 /* Includes ------------------------------------------------------------------*/
00186 #include "stm32h7xx_hal.h"
00187
00188 /** @addtogroup STM32H7xx_HAL_Driver
00189   * @{
00190   */
00191
00192 /** @defgroup FDCAN FDCAN
00193   * @brief FDCAN HAL module driver
00194   * @{
00195   */
00196
00197 #ifdef HAL_FDCAN_MODULE_ENABLED
00198
00199 /* Private typedef -----------------------------------------------------------*/
00200 /* Private define ------------------------------------------------------------*/
00201 /** @addtogroup FDCAN_Private_Constants
00202   * @{
00203   */
00204 #define FDCAN_TIMEOUT_VALUE 10U
00205
00206 #define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
00207 #define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
00208 #define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
00209 #define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
00210 #define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
00211 #define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
00212 #define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
00213 #define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
00214 #define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
00215                                         FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
00216 #define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
00217
00218 #define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
00219 #define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
00220 #define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
00221 #define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
00222 #define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
00223 #define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
00224 #define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
00225 #define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
00226 #define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
00227 #define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
00228 #define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
00229 #define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
00230 #define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
00231 #define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
00232
00233 #define FDCAN_MESSAGE_RAM_SIZE 0x2800U
00234 #define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /* Private macro -------------------------------------------------------------*/
00241 /* Private variables ---------------------------------------------------------*/
00242 static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
00243
00244 /* Private function prototypes -----------------------------------------------*/
00245 /** @addtogroup FDCAN_Private_Functions_Prototypes
00246   * @{
00247   */
00248 static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
00249 static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
00250 /**
00251   * @}
00252   */
00253
00254 /* Exported functions --------------------------------------------------------*/
00255 /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
00256   * @{
00257   */
00258
00259 /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
00260  *  @brief    Initialization and Configuration functions
00261  *
00262 @verbatim
00263   ==============================================================================
00264               ##### Initialization and de-initialization functions #####
00265   ==============================================================================
00266     [..]  This section provides functions allowing to:
00267       (+) Initialize and configure the FDCAN.
00268       (+) De-initialize the FDCAN.
00269       (+) Enter FDCAN peripheral in power down mode.
00270       (+) Exit power down mode.
00271       (+) Register callbacks.
00272       (+) Unregister callbacks.
00273
00274 @endverbatim
00275   * @{
00276   */
00277
00278 /**
00279   * @brief  Initializes the FDCAN peripheral according to the specified
00280   *         parameters in the FDCAN_InitTypeDef structure.
00281   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00282   *         the configuration information for the specified FDCAN.
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
00286 {
00287   uint32_t tickstart;
00288   HAL_StatusTypeDef status;
00289   const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
00290
00291   /* Check FDCAN handle */
00292   if (hfdcan == NULL)
00293   {
00294     return HAL_ERROR;
00295   }
00296
00297   /* Check FDCAN instance */
00298   if (hfdcan->Instance == FDCAN1)
00299   {
00300     hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
00301   }
00302
00303   /* Check function parameters */
00304   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00305   assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
00306   assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
00307   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
00308   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
00309   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
00310   assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
00311   assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
00312   assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
00313   assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
00314   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00315   {
00316     assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
00317     assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
00318     assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
00319     assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
00320   }
00321   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
00322   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
00323   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
00324   if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
00325   {
00326     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
00327   }
00328   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
00329   if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
00330   {
00331     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
00332   }
00333   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
00334   if (hfdcan->Init.RxBuffersNbr > 0U)
00335   {
00336     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
00337   }
00338   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
00339   assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
00340   if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
00341   {
00342     assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
00343   }
00344   if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
00345   {
00346     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
00347   }
00348
00349 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00350   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00351   {
00352     /* Allocate lock resource and initialize it */
00353     hfdcan->Lock = HAL_UNLOCKED;
00354
00355     /* Reset callbacks to legacy functions */
00356     hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
00357     hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
00358     hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
00359     hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
00360     hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
00361     hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
00362     hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
00363     hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
00364     hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
00365     hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
00366     hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
00367     hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
00368     hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
00369     hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
00370     hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
00371     hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
00372     hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
00373
00374     if (hfdcan->MspInitCallback == NULL)
00375     {
00376       hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
00377     }
00378
00379     /* Init the low level hardware: CLOCK, NVIC */
00380     hfdcan->MspInitCallback(hfdcan);
00381   }
00382 #else
00383   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00384   {
00385     /* Allocate lock resource and initialize it */
00386     hfdcan->Lock = HAL_UNLOCKED;
00387
00388     /* Init the low level hardware: CLOCK, NVIC */
00389     HAL_FDCAN_MspInit(hfdcan);
00390   }
00391 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00392
00393   /* Exit from Sleep mode */
00394   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00395
00396   /* Get tick */
00397   tickstart = HAL_GetTick();
00398
00399   /* Check Sleep mode acknowledge */
00400   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00401   {
00402     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00403     {
00404       /* Update error code */
00405       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00406
00407       /* Change FDCAN state */
00408       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00409
00410       return HAL_ERROR;
00411     }
00412   }
00413
00414   /* Request initialisation */
00415   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00416
00417   /* Get tick */
00418   tickstart = HAL_GetTick();
00419
00420   /* Wait until the INIT bit into CCCR register is set */
00421   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
00422   {
00423     /* Check for the Timeout */
00424     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00425     {
00426       /* Update error code */
00427       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00428
00429       /* Change FDCAN state */
00430       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00431
00432       return HAL_ERROR;
00433     }
00434   }
00435
00436   /* Enable configuration change */
00437   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
00438
00439   /* Set the no automatic retransmission */
00440   if (hfdcan->Init.AutoRetransmission == ENABLE)
00441   {
00442     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00443   }
00444   else
00445   {
00446     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00447   }
00448
00449   /* Set the transmit pause feature */
00450   if (hfdcan->Init.TransmitPause == ENABLE)
00451   {
00452     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00453   }
00454   else
00455   {
00456     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00457   }
00458
00459   /* Set the Protocol Exception Handling */
00460   if (hfdcan->Init.ProtocolException == ENABLE)
00461   {
00462     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00463   }
00464   else
00465   {
00466     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00467   }
00468
00469   /* Set FDCAN Frame Format */
00470   MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
00471
00472   /* Reset FDCAN Operation Mode */
00473   CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
00474   CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00475
00476   /* Set FDCAN Operating Mode:
00477                | Normal | Restricted |    Bus     | Internal | External
00478                |        | Operation  | Monitoring | LoopBack | LoopBack
00479      CCCR.TEST |   0    |     0      |     0      |    1     |    1
00480      CCCR.MON  |   0    |     0      |     1      |    1     |    0
00481      TEST.LBCK |   0    |     0      |     0      |    1     |    1
00482      CCCR.ASM  |   0    |     1      |     0      |    0     |    0
00483   */
00484   if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
00485   {
00486     /* Enable Restricted Operation mode */
00487     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
00488   }
00489   else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
00490   {
00491     if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
00492     {
00493       /* Enable write access to TEST register */
00494       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
00495
00496       /* Enable LoopBack mode */
00497       SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00498
00499       if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
00500       {
00501         SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00502       }
00503     }
00504     else
00505     {
00506       /* Enable bus monitoring mode */
00507       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00508     }
00509   }
00510   else
00511   {
00512     /* Nothing to do: normal mode */
00513   }
00514
00515   /* Set the nominal bit timing register */
00516   hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
00517                             (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
00518                             (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
00519                             (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
00520
00521   /* If FD operation with BRS is selected, set the data bit timing register */
00522   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00523   {
00524     hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
00525                               (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
00526                               (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
00527                               (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
00528   }
00529
00530   if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
00531   {
00532     /* Select between Tx FIFO and Tx Queue operation modes */
00533     SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
00534   }
00535
00536   /* Configure Tx element size */
00537   if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
00538   {
00539     MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
00540   }
00541
00542   /* Configure Rx FIFO 0 element size */
00543   if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
00544   {
00545     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
00546   }
00547
00548   /* Configure Rx FIFO 1 element size */
00549   if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
00550   {
00551     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
00552   }
00553
00554   /* Configure Rx buffer element size */
00555   if (hfdcan->Init.RxBuffersNbr > 0U)
00556   {
00557     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
00558   }
00559
00560   /* By default operation mode is set to Event-driven communication.
00561      If Time-triggered communication is needed, user should call the
00562      HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
00563   if (hfdcan->Instance == FDCAN1)
00564   {
00565     CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
00566   }
00567
00568   /* Initialize the Latest Tx FIFO/Queue request buffer index */
00569   hfdcan->LatestTxFifoQRequest = 0U;
00570
00571   /* Initialize the error code */
00572   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00573
00574   /* Initialize the FDCAN state */
00575   hfdcan->State = HAL_FDCAN_STATE_READY;
00576
00577   /* Calculate each RAM block address */
00578   status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
00579
00580   /* Return function status */
00581   return status;
00582 }
00583
00584 /**
00585   * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
00586   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00587   *         the configuration information for the specified FDCAN.
00588   * @retval HAL status
00589   */
00590 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
00591 {
00592   /* Check FDCAN handle */
00593   if (hfdcan == NULL)
00594   {
00595     return HAL_ERROR;
00596   }
00597
00598   /* Check function parameters */
00599   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00600
00601   /* Stop the FDCAN module: return value is voluntary ignored */
00602   (void)HAL_FDCAN_Stop(hfdcan);
00603
00604   /* Disable Interrupt lines */
00605   CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
00606
00607 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00608   if (hfdcan->MspDeInitCallback == NULL)
00609   {
00610     hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
00611   }
00612
00613   /* DeInit the low level hardware: CLOCK, NVIC */
00614   hfdcan->MspDeInitCallback(hfdcan);
00615 #else
00616   /* DeInit the low level hardware: CLOCK, NVIC */
00617   HAL_FDCAN_MspDeInit(hfdcan);
00618 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00619
00620   /* Reset the FDCAN ErrorCode */
00621   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00622
00623   /* Change FDCAN state */
00624   hfdcan->State = HAL_FDCAN_STATE_RESET;
00625
00626   /* Return function status */
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @brief  Initializes the FDCAN MSP.
00632   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00633   *         the configuration information for the specified FDCAN.
00634   * @retval None
00635   */
00636 __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
00637 {
00638   /* Prevent unused argument(s) compilation warning */
00639   UNUSED(hfdcan);
00640   /* NOTE : This function Should not be modified, when the callback is needed,
00641             the HAL_FDCAN_MspInit could be implemented in the user file
00642    */
00643 }
00644
00645 /**
00646   * @brief  DeInitializes the FDCAN MSP.
00647   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00648   *         the configuration information for the specified FDCAN.
00649   * @retval None
00650   */
00651 __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
00652 {
00653   /* Prevent unused argument(s) compilation warning */
00654   UNUSED(hfdcan);
00655   /* NOTE : This function Should not be modified, when the callback is needed,
00656             the HAL_FDCAN_MspDeInit could be implemented in the user file
00657    */
00658 }
00659
00660 /**
00661   * @brief  Enter FDCAN peripheral in sleep mode.
00662   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00663   *         the configuration information for the specified FDCAN.
00664   * @retval HAL status
00665   */
00666 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00667 {
00668   uint32_t tickstart;
00669
00670   /* Request clock stop */
00671   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00672
00673   /* Get tick */
00674   tickstart = HAL_GetTick();
00675
00676   /* Wait until FDCAN is ready for power down */
00677   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
00678   {
00679     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00680     {
00681       /* Update error code */
00682       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00683
00684       /* Change FDCAN state */
00685       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00686
00687       return HAL_ERROR;
00688     }
00689   }
00690
00691   /* Return function status */
00692   return HAL_OK;
00693 }
00694
00695 /**
00696   * @brief  Exit power down mode.
00697   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00698   *         the configuration information for the specified FDCAN.
00699   * @retval HAL status
00700   */
00701 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00702 {
00703   uint32_t tickstart;
00704
00705   /* Reset clock stop request */
00706   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00707
00708   /* Get tick */
00709   tickstart = HAL_GetTick();
00710
00711   /* Wait until FDCAN exits sleep mode */
00712   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00713   {
00714     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00715     {
00716       /* Update error code */
00717       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00718
00719       /* Change FDCAN state */
00720       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00721
00722       return HAL_ERROR;
00723     }
00724   }
00725
00726   /* Enter normal operation */
00727   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00728
00729   /* Return function status */
00730   return HAL_OK;
00731 }
00732
00733 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00734 /**
00735   * @brief  Register a FDCAN CallBack.
00736   *         To be used instead of the weak predefined callback
00737   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00738   *         the configuration information for FDCAN module
00739   * @param  CallbackID ID of the callback to be registered
00740   *         This parameter can be one of the following values:
00741   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00742   *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
00743   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00744   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00745   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00746   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00747   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00748   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00749   * @param  pCallback pointer to the Callback function
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
00753 {
00754   HAL_StatusTypeDef status = HAL_OK;
00755
00756   if (pCallback == NULL)
00757   {
00758     /* Update the error code */
00759     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00760
00761     return HAL_ERROR;
00762   }
00763
00764   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00765   {
00766     switch (CallbackID)
00767     {
00768       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00769         hfdcan->TxFifoEmptyCallback = pCallback;
00770         break;
00771
00772       case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
00773         hfdcan->RxBufferNewMessageCallback = pCallback;
00774         break;
00775
00776       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00777         hfdcan->HighPriorityMessageCallback = pCallback;
00778         break;
00779
00780       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00781         hfdcan->TimestampWraparoundCallback = pCallback;
00782         break;
00783
00784       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00785         hfdcan->TimeoutOccurredCallback = pCallback;
00786         break;
00787
00788       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00789         hfdcan->ErrorCallback = pCallback;
00790         break;
00791
00792       case HAL_FDCAN_MSPINIT_CB_ID :
00793         hfdcan->MspInitCallback = pCallback;
00794         break;
00795
00796       case HAL_FDCAN_MSPDEINIT_CB_ID :
00797         hfdcan->MspDeInitCallback = pCallback;
00798         break;
00799
00800       default :
00801         /* Update the error code */
00802         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00803
00804         /* Return error status */
00805         status =  HAL_ERROR;
00806         break;
00807     }
00808   }
00809   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00810   {
00811     switch (CallbackID)
00812     {
00813       case HAL_FDCAN_MSPINIT_CB_ID :
00814         hfdcan->MspInitCallback = pCallback;
00815         break;
00816
00817       case HAL_FDCAN_MSPDEINIT_CB_ID :
00818         hfdcan->MspDeInitCallback = pCallback;
00819         break;
00820
00821       default :
00822         /* Update the error code */
00823         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00824
00825         /* Return error status */
00826         status =  HAL_ERROR;
00827         break;
00828     }
00829   }
00830   else
00831   {
00832     /* Update the error code */
00833     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00834
00835     /* Return error status */
00836     status =  HAL_ERROR;
00837   }
00838
00839   return status;
00840 }
00841
00842 /**
00843   * @brief  Unregister a FDCAN CallBack.
00844   *         FDCAN callback is redirected to the weak predefined callback
00845   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00846   *         the configuration information for FDCAN module
00847   * @param  CallbackID ID of the callback to be unregistered
00848   *         This parameter can be one of the following values:
00849   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00850   *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
00851   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00852   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00853   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00854   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00855   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00856   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00857   * @retval HAL status
00858   */
00859 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
00860 {
00861   HAL_StatusTypeDef status = HAL_OK;
00862
00863   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00864   {
00865     switch (CallbackID)
00866     {
00867       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00868         hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
00869         break;
00870
00871       case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
00872         hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
00873         break;
00874
00875       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00876         hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
00877         break;
00878
00879       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00880         hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
00881         break;
00882
00883       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00884         hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
00885         break;
00886
00887       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00888         hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
00889         break;
00890
00891       case HAL_FDCAN_MSPINIT_CB_ID :
00892         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00893         break;
00894
00895       case HAL_FDCAN_MSPDEINIT_CB_ID :
00896         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00897         break;
00898
00899       default :
00900         /* Update the error code */
00901         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00902
00903         /* Return error status */
00904         status =  HAL_ERROR;
00905         break;
00906     }
00907   }
00908   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00909   {
00910     switch (CallbackID)
00911     {
00912       case HAL_FDCAN_MSPINIT_CB_ID :
00913         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00914         break;
00915
00916       case HAL_FDCAN_MSPDEINIT_CB_ID :
00917         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00918         break;
00919
00920       default :
00921         /* Update the error code */
00922         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00923
00924         /* Return error status */
00925         status =  HAL_ERROR;
00926         break;
00927     }
00928   }
00929   else
00930   {
00931     /* Update the error code */
00932     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00933
00934     /* Return error status */
00935     status =  HAL_ERROR;
00936   }
00937
00938   return status;
00939 }
00940
00941 /**
00942   * @brief  Register Clock Calibration FDCAN Callback
00943   *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
00944   * @param  hfdcan FDCAN handle
00945   * @param  pCallback pointer to the Clock Calibration Callback function
00946   * @retval HAL status
00947   */
00948 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
00949 {
00950   HAL_StatusTypeDef status = HAL_OK;
00951
00952   if (pCallback == NULL)
00953   {
00954     /* Update the error code */
00955     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00956     return HAL_ERROR;
00957   }
00958
00959   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00960   {
00961     hfdcan->ClockCalibrationCallback = pCallback;
00962   }
00963   else
00964   {
00965     /* Update the error code */
00966     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00967
00968     /* Return error status */
00969     status =  HAL_ERROR;
00970   }
00971
00972   return status;
00973 }
00974
00975 /**
00976   * @brief  UnRegister the Clock Calibration FDCAN Callback
00977   *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
00978   * @param  hfdcan FDCAN handle
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
00982 {
00983   HAL_StatusTypeDef status = HAL_OK;
00984
00985   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00986   {
00987     hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
00988   }
00989   else
00990   {
00991     /* Update the error code */
00992     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00993
00994     /* Return error status */
00995     status =  HAL_ERROR;
00996   }
00997
00998   return status;
00999 }
01000
01001 /**
01002   * @brief  Register Tx Event Fifo FDCAN Callback
01003   *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
01004   * @param  hfdcan FDCAN handle
01005   * @param  pCallback pointer to the Tx Event Fifo Callback function
01006   * @retval HAL status
01007   */
01008 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
01009 {
01010   HAL_StatusTypeDef status = HAL_OK;
01011
01012   if (pCallback == NULL)
01013   {
01014     /* Update the error code */
01015     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01016     return HAL_ERROR;
01017   }
01018
01019   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01020   {
01021     hfdcan->TxEventFifoCallback = pCallback;
01022   }
01023   else
01024   {
01025     /* Update the error code */
01026     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01027
01028     /* Return error status */
01029     status =  HAL_ERROR;
01030   }
01031
01032   return status;
01033 }
01034
01035 /**
01036   * @brief  UnRegister the Tx Event Fifo FDCAN Callback
01037   *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
01038   * @param  hfdcan FDCAN handle
01039   * @retval HAL status
01040   */
01041 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
01042 {
01043   HAL_StatusTypeDef status = HAL_OK;
01044
01045   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01046   {
01047     hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
01048   }
01049   else
01050   {
01051     /* Update the error code */
01052     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01053
01054     /* Return error status */
01055     status =  HAL_ERROR;
01056   }
01057
01058   return status;
01059 }
01060
01061 /**
01062   * @brief  Register Rx Fifo 0 FDCAN Callback
01063   *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
01064   * @param  hfdcan FDCAN handle
01065   * @param  pCallback pointer to the Rx Fifo 0 Callback function
01066   * @retval HAL status
01067   */
01068 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
01069 {
01070   HAL_StatusTypeDef status = HAL_OK;
01071
01072   if (pCallback == NULL)
01073   {
01074     /* Update the error code */
01075     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01076     return HAL_ERROR;
01077   }
01078
01079   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01080   {
01081     hfdcan->RxFifo0Callback = pCallback;
01082   }
01083   else
01084   {
01085     /* Update the error code */
01086     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01087
01088     /* Return error status */
01089     status =  HAL_ERROR;
01090   }
01091
01092   return status;
01093 }
01094
01095 /**
01096   * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
01097   *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
01098   * @param  hfdcan FDCAN handle
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
01102 {
01103   HAL_StatusTypeDef status = HAL_OK;
01104
01105   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01106   {
01107     hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
01108   }
01109   else
01110   {
01111     /* Update the error code */
01112     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01113
01114     /* Return error status */
01115     status =  HAL_ERROR;
01116   }
01117
01118   return status;
01119 }
01120
01121 /**
01122   * @brief  Register Rx Fifo 1 FDCAN Callback
01123   *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01124   * @param  hfdcan FDCAN handle
01125   * @param  pCallback pointer to the Rx Fifo 1 Callback function
01126   * @retval HAL status
01127   */
01128 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
01129 {
01130   HAL_StatusTypeDef status = HAL_OK;
01131
01132   if (pCallback == NULL)
01133   {
01134     /* Update the error code */
01135     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01136     return HAL_ERROR;
01137   }
01138
01139   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01140   {
01141     hfdcan->RxFifo1Callback = pCallback;
01142   }
01143   else
01144   {
01145     /* Update the error code */
01146     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01147
01148     /* Return error status */
01149     status =  HAL_ERROR;
01150   }
01151
01152   return status;
01153 }
01154
01155 /**
01156   * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
01157   *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01158   * @param  hfdcan FDCAN handle
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
01162 {
01163   HAL_StatusTypeDef status = HAL_OK;
01164
01165   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01166   {
01167     hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
01168   }
01169   else
01170   {
01171     /* Update the error code */
01172     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01173
01174     /* Return error status */
01175     status =  HAL_ERROR;
01176   }
01177
01178   return status;
01179 }
01180
01181 /**
01182   * @brief  Register Tx Buffer Complete FDCAN Callback
01183   *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01184   * @param  hfdcan FDCAN handle
01185   * @param  pCallback pointer to the Tx Buffer Complete Callback function
01186   * @retval HAL status
01187   */
01188 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
01189 {
01190   HAL_StatusTypeDef status = HAL_OK;
01191
01192   if (pCallback == NULL)
01193   {
01194     /* Update the error code */
01195     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01196     return HAL_ERROR;
01197   }
01198
01199   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01200   {
01201     hfdcan->TxBufferCompleteCallback = pCallback;
01202   }
01203   else
01204   {
01205     /* Update the error code */
01206     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01207
01208     /* Return error status */
01209     status =  HAL_ERROR;
01210   }
01211
01212   return status;
01213 }
01214
01215 /**
01216   * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
01217   *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01218   * @param  hfdcan FDCAN handle
01219   * @retval HAL status
01220   */
01221 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
01222 {
01223   HAL_StatusTypeDef status = HAL_OK;
01224
01225   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01226   {
01227     hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
01228   }
01229   else
01230   {
01231     /* Update the error code */
01232     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01233
01234     /* Return error status */
01235     status =  HAL_ERROR;
01236   }
01237
01238   return status;
01239 }
01240
01241 /**
01242   * @brief  Register Tx Buffer Abort FDCAN Callback
01243   *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01244   * @param  hfdcan FDCAN handle
01245   * @param  pCallback pointer to the Tx Buffer Abort Callback function
01246   * @retval HAL status
01247   */
01248 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
01249 {
01250   HAL_StatusTypeDef status = HAL_OK;
01251
01252   if (pCallback == NULL)
01253   {
01254     /* Update the error code */
01255     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01256     return HAL_ERROR;
01257   }
01258
01259   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01260   {
01261     hfdcan->TxBufferAbortCallback = pCallback;
01262   }
01263   else
01264   {
01265     /* Update the error code */
01266     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01267
01268     /* Return error status */
01269     status =  HAL_ERROR;
01270   }
01271
01272   return status;
01273 }
01274
01275 /**
01276   * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
01277   *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01278   * @param  hfdcan FDCAN handle
01279   * @retval HAL status
01280   */
01281 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
01282 {
01283   HAL_StatusTypeDef status = HAL_OK;
01284
01285   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01286   {
01287     hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
01288   }
01289   else
01290   {
01291     /* Update the error code */
01292     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01293
01294     /* Return error status */
01295     status =  HAL_ERROR;
01296   }
01297
01298   return status;
01299 }
01300
01301 /**
01302   * @brief  Register Error Status FDCAN Callback
01303   *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01304   * @param  hfdcan FDCAN handle
01305   * @param  pCallback pointer to the Error Status Callback function
01306   * @retval HAL status
01307   */
01308 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
01309 {
01310   HAL_StatusTypeDef status = HAL_OK;
01311
01312   if (pCallback == NULL)
01313   {
01314     /* Update the error code */
01315     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01316     return HAL_ERROR;
01317   }
01318
01319   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01320   {
01321     hfdcan->ErrorStatusCallback = pCallback;
01322   }
01323   else
01324   {
01325     /* Update the error code */
01326     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01327
01328     /* Return error status */
01329     status =  HAL_ERROR;
01330   }
01331
01332   return status;
01333 }
01334
01335 /**
01336   * @brief  UnRegister the Error Status FDCAN Callback
01337   *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01338   * @param  hfdcan FDCAN handle
01339   * @retval HAL status
01340   */
01341 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
01342 {
01343   HAL_StatusTypeDef status = HAL_OK;
01344
01345   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01346   {
01347     hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
01348   }
01349   else
01350   {
01351     /* Update the error code */
01352     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01353
01354     /* Return error status */
01355     status =  HAL_ERROR;
01356   }
01357
01358   return status;
01359 }
01360
01361 /**
01362   * @brief  Register TT Schedule Synchronization FDCAN Callback
01363   *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
01364   * @param  hfdcan FDCAN handle
01365   * @param  pCallback pointer to the TT Schedule Synchronization Callback function
01366   * @retval HAL status
01367   */
01368 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
01369 {
01370   HAL_StatusTypeDef status = HAL_OK;
01371
01372   if (pCallback == NULL)
01373   {
01374     /* Update the error code */
01375     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01376     return HAL_ERROR;
01377   }
01378
01379   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01380   {
01381     hfdcan->TT_ScheduleSyncCallback = pCallback;
01382   }
01383   else
01384   {
01385     /* Update the error code */
01386     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01387
01388     /* Return error status */
01389     status =  HAL_ERROR;
01390   }
01391
01392   return status;
01393 }
01394
01395 /**
01396   * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
01397   *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
01398   * @param  hfdcan FDCAN handle
01399   * @retval HAL status
01400   */
01401 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
01402 {
01403   HAL_StatusTypeDef status = HAL_OK;
01404
01405   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01406   {
01407     hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
01408   }
01409   else
01410   {
01411     /* Update the error code */
01412     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01413
01414     /* Return error status */
01415     status =  HAL_ERROR;
01416   }
01417
01418   return status;
01419 }
01420
01421 /**
01422   * @brief  Register TT Time Mark FDCAN Callback
01423   *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
01424   * @param  hfdcan FDCAN handle
01425   * @param  pCallback pointer to the TT Time Mark Callback function
01426   * @retval HAL status
01427   */
01428 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
01429 {
01430   HAL_StatusTypeDef status = HAL_OK;
01431
01432   if (pCallback == NULL)
01433   {
01434     /* Update the error code */
01435     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01436     return HAL_ERROR;
01437   }
01438
01439   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01440   {
01441     hfdcan->TT_TimeMarkCallback = pCallback;
01442   }
01443   else
01444   {
01445     /* Update the error code */
01446     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01447
01448     /* Return error status */
01449     status =  HAL_ERROR;
01450   }
01451
01452   return status;
01453 }
01454
01455 /**
01456   * @brief  UnRegister the TT Time Mark FDCAN Callback
01457   *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
01458   * @param  hfdcan FDCAN handle
01459   * @retval HAL status
01460   */
01461 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
01462 {
01463   HAL_StatusTypeDef status = HAL_OK;
01464
01465   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01466   {
01467     hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
01468   }
01469   else
01470   {
01471     /* Update the error code */
01472     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01473
01474     /* Return error status */
01475     status =  HAL_ERROR;
01476   }
01477
01478   return status;
01479 }
01480
01481 /**
01482   * @brief  Register TT Stop Watch FDCAN Callback
01483   *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
01484   * @param  hfdcan FDCAN handle
01485   * @param  pCallback pointer to the TT Stop Watch Callback function
01486   * @retval HAL status
01487   */
01488 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
01489 {
01490   HAL_StatusTypeDef status = HAL_OK;
01491
01492   if (pCallback == NULL)
01493   {
01494     /* Update the error code */
01495     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01496     return HAL_ERROR;
01497   }
01498
01499   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01500   {
01501     hfdcan->TT_StopWatchCallback = pCallback;
01502   }
01503   else
01504   {
01505     /* Update the error code */
01506     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01507
01508     /* Return error status */
01509     status =  HAL_ERROR;
01510   }
01511
01512   return status;
01513 }
01514
01515 /**
01516   * @brief  UnRegister the TT Stop Watch FDCAN Callback
01517   *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
01518   * @param  hfdcan FDCAN handle
01519   * @retval HAL status
01520   */
01521 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
01522 {
01523   HAL_StatusTypeDef status = HAL_OK;
01524
01525   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01526   {
01527     hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
01528   }
01529   else
01530   {
01531     /* Update the error code */
01532     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01533
01534     /* Return error status */
01535     status =  HAL_ERROR;
01536   }
01537
01538   return status;
01539 }
01540
01541 /**
01542   * @brief  Register TT Global Time FDCAN Callback
01543   *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
01544   * @param  hfdcan FDCAN handle
01545   * @param  pCallback pointer to the TT Global Time Callback function
01546   * @retval HAL status
01547   */
01548 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
01549 {
01550   HAL_StatusTypeDef status = HAL_OK;
01551
01552   if (pCallback == NULL)
01553   {
01554     /* Update the error code */
01555     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01556     return HAL_ERROR;
01557   }
01558
01559   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01560   {
01561     hfdcan->TT_GlobalTimeCallback = pCallback;
01562   }
01563   else
01564   {
01565     /* Update the error code */
01566     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01567
01568     /* Return error status */
01569     status =  HAL_ERROR;
01570   }
01571
01572   return status;
01573 }
01574
01575 /**
01576   * @brief  UnRegister the TT Global Time FDCAN Callback
01577   *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
01578   * @param  hfdcan FDCAN handle
01579   * @retval HAL status
01580   */
01581 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
01582 {
01583   HAL_StatusTypeDef status = HAL_OK;
01584
01585   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01586   {
01587     hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
01588   }
01589   else
01590   {
01591     /* Update the error code */
01592     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01593
01594     /* Return error status */
01595     status =  HAL_ERROR;
01596   }
01597
01598   return status;
01599 }
01600
01601 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01602
01603 /**
01604   * @}
01605   */
01606
01607 /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
01608  *  @brief    FDCAN Configuration functions.
01609  *
01610 @verbatim
01611   ==============================================================================
01612               ##### Configuration functions #####
01613   ==============================================================================
01614     [..]  This section provides functions allowing to:
01615       (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
01616         (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
01617         (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
01618         (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
01619       (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
01620       (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
01621       (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
01622       (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
01623       (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
01624       (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
01625       (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
01626         (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
01627         (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
01628         (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
01629         (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
01630       (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
01631         (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
01632         (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
01633         (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
01634         (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
01635       (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
01636         (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
01637         (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
01638       (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
01639       (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
01640       (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
01641       (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
01642
01643 @endverbatim
01644   * @{
01645   */
01646
01647 /**
01648   * @brief  Configure the FDCAN clock calibration unit according to the specified
01649   *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
01650   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01651   *         the configuration information for the specified FDCAN.
01652   * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
01653   *         contains the clock calibration information
01654   * @retval HAL status
01655   */
01656 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
01657 {
01658   /* Check function parameters */
01659   assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
01660   if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
01661   {
01662     assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
01663   }
01664   else
01665   {
01666     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
01667     assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
01668     assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
01669     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
01670     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
01671   }
01672
01673   /* FDCAN1 should be initialized in order to use clock calibration */
01674   if (hfdcan->Instance != FDCAN1)
01675   {
01676     /* Update error code */
01677     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01678
01679     return HAL_ERROR;
01680   }
01681
01682   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01683   {
01684     if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
01685     {
01686       /* Bypass clock calibration */
01687       SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
01688
01689       /* Configure clock divider */
01690       MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
01691     }
01692     else /* sCcuConfig->ClockCalibration == ENABLE */
01693     {
01694       /* Clock calibration unit generates time quanta clock */
01695       CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
01696
01697       /* Configure clock calibration unit */
01698       MODIFY_REG(FDCAN_CCU->CCFG,
01699                  (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
01700                  ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
01701
01702       /* Configure the start value of the calibration watchdog counter */
01703       MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
01704     }
01705
01706     /* Return function status */
01707     return HAL_OK;
01708   }
01709   else
01710   {
01711     /* Update error code */
01712     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01713
01714     return HAL_ERROR;
01715   }
01716 }
01717
01718 /**
01719   * @brief  Get the clock calibration state.
01720   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01721   *         the configuration information for the specified FDCAN.
01722   * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
01723   */
01724 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
01725 {
01726   /* Prevent unused argument(s) compilation warning */
01727   UNUSED(hfdcan);
01728
01729   return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
01730 }
01731
01732 /**
01733   * @brief  Reset the clock calibration state.
01734   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01735   *         the configuration information for the specified FDCAN.
01736   * @retval HAL status
01737   */
01738 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
01739 {
01740   /* FDCAN1 should be initialized in order to use clock calibration */
01741   if (hfdcan->Instance != FDCAN1)
01742   {
01743     /* Update error code */
01744     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01745
01746     return HAL_ERROR;
01747   }
01748
01749   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01750   {
01751     /* Calibration software reset */
01752     SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
01753
01754     /* Return function status */
01755     return HAL_OK;
01756   }
01757   else
01758   {
01759     /* Update error code */
01760     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01761
01762     return HAL_ERROR;
01763   }
01764 }
01765
01766 /**
01767   * @brief  Get the clock calibration counter value.
01768   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01769   *         the configuration information for the specified FDCAN.
01770   * @param  Counter clock calibration counter.
01771   *         This parameter can be a value of @arg FDCAN_calibration_counter.
01772   * @retval Value clock calibration counter value
01773   */
01774 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
01775 {
01776   /* Prevent unused argument(s) compilation warning */
01777   UNUSED(hfdcan);
01778
01779   /* Check function parameters */
01780   assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
01781
01782   if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
01783   {
01784     return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
01785   }
01786   else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
01787   {
01788     return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
01789   }
01790   else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
01791   {
01792     return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
01793   }
01794 }
01795
01796 /**
01797   * @brief  Configure the FDCAN reception filter according to the specified
01798   *         parameters in the FDCAN_FilterTypeDef structure.
01799   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01800   *         the configuration information for the specified FDCAN.
01801   * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
01802   *         contains the filter configuration information
01803   * @retval HAL status
01804   */
01805 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
01806 {
01807   uint32_t FilterElementW1;
01808   uint32_t FilterElementW2;
01809   uint32_t *FilterAddress;
01810   HAL_FDCAN_StateTypeDef state = hfdcan->State;
01811
01812   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
01813   {
01814     /* Check function parameters */
01815     assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
01816     assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
01817     if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
01818     {
01819       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
01820       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
01821     }
01822
01823     if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
01824     {
01825       /* Check function parameters */
01826       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
01827       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
01828       if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
01829       {
01830         assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
01831         assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
01832       }
01833
01834       /* Build filter element */
01835       if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
01836       {
01837         FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
01838                            (sFilterConfig->FilterID1 << 16U)       |
01839                            (sFilterConfig->IsCalibrationMsg << 8U) |
01840                            sFilterConfig->RxBufferIndex);
01841       }
01842       else
01843       {
01844         FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
01845                            (sFilterConfig->FilterConfig << 27U) |
01846                            (sFilterConfig->FilterID1 << 16U)    |
01847                            sFilterConfig->FilterID2);
01848       }
01849
01850       /* Calculate filter address */
01851       FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
01852
01853       /* Write filter element to the message RAM */
01854       *FilterAddress = FilterElementW1;
01855     }
01856     else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
01857     {
01858       /* Check function parameters */
01859       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
01860       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
01861       if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
01862       {
01863         assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
01864         assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
01865       }
01866
01867       /* Build first word of filter element */
01868       FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
01869
01870       /* Build second word of filter element */
01871       if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
01872       {
01873         FilterElementW2 = sFilterConfig->RxBufferIndex;
01874       }
01875       else
01876       {
01877         FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
01878       }
01879
01880       /* Calculate filter address */
01881       FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
01882
01883       /* Write filter element to the message RAM */
01884       *FilterAddress = FilterElementW1;
01885       FilterAddress++;
01886       *FilterAddress = FilterElementW2;
01887     }
01888
01889     /* Return function status */
01890     return HAL_OK;
01891   }
01892   else
01893   {
01894     /* Update error code */
01895     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01896
01897     return HAL_ERROR;
01898   }
01899 }
01900
01901 /**
01902   * @brief  Configure the FDCAN global filter.
01903   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01904   *         the configuration information for the specified FDCAN.
01905   * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
01906   *         do not match any element of the filter list are treated.
01907   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01908   * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
01909   *         do not match any element of the filter list are treated.
01910   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01911   * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
01912   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01913   * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
01914   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01915   * @retval HAL status
01916   */
01917 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
01918                                                uint32_t NonMatchingStd,
01919                                                uint32_t NonMatchingExt,
01920                                                uint32_t RejectRemoteStd,
01921                                                uint32_t RejectRemoteExt)
01922 {
01923   /* Check function parameters */
01924   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
01925   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
01926   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
01927   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
01928
01929   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01930   {
01931     /* Configure global filter */
01932     hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
01933                              (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
01934                              (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
01935                              (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
01936
01937     /* Return function status */
01938     return HAL_OK;
01939   }
01940   else
01941   {
01942     /* Update error code */
01943     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01944
01945     return HAL_ERROR;
01946   }
01947 }
01948
01949 /**
01950   * @brief  Configure the extended ID mask.
01951   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01952   *         the configuration information for the specified FDCAN.
01953   * @param  Mask Extended ID Mask.
01954   *         This parameter must be a number between 0 and 0x1FFFFFFF
01955   * @retval HAL status
01956   */
01957 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
01958 {
01959   /* Check function parameters */
01960   assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
01961
01962   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01963   {
01964     /* Configure the extended ID mask */
01965     hfdcan->Instance->XIDAM = Mask;
01966
01967     /* Return function status */
01968     return HAL_OK;
01969   }
01970   else
01971   {
01972     /* Update error code */
01973     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01974
01975     return HAL_ERROR;
01976   }
01977 }
01978
01979 /**
01980   * @brief  Configure the Rx FIFO operation mode.
01981   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01982   *         the configuration information for the specified FDCAN.
01983   * @param  RxFifo Rx FIFO.
01984   *         This parameter can be one of the following values:
01985   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
01986   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
01987   * @param  OperationMode operation mode.
01988   *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
01989   * @retval HAL status
01990   */
01991 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
01992 {
01993   /* Check function parameters */
01994   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
01995   assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
01996
01997   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01998   {
01999     if (RxFifo == FDCAN_RX_FIFO0)
02000     {
02001       /* Select FIFO 0 Operation Mode */
02002       MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
02003     }
02004     else /* RxFifo == FDCAN_RX_FIFO1 */
02005     {
02006       /* Select FIFO 1 Operation Mode */
02007       MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
02008     }
02009
02010     /* Return function status */
02011     return HAL_OK;
02012   }
02013   else
02014   {
02015     /* Update error code */
02016     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02017
02018     return HAL_ERROR;
02019   }
02020 }
02021
02022 /**
02023   * @brief  Configure the FIFO watermark.
02024   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02025   *         the configuration information for the specified FDCAN.
02026   * @param  FIFO select the FIFO to be configured.
02027   *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
02028   * @param  Watermark level for FIFO watermark interrupt.
02029   *         This parameter must be a number between:
02030   *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
02031   *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
02032   * @retval HAL status
02033   */
02034 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
02035 {
02036   /* Check function parameters */
02037   assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
02038   if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
02039   {
02040     assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
02041   }
02042   else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
02043   {
02044     assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
02045   }
02046
02047   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02048   {
02049     /* Set the level for FIFO watermark interrupt */
02050     if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
02051     {
02052       MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
02053     }
02054     else if (FIFO == FDCAN_CFG_RX_FIFO0)
02055     {
02056       MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
02057     }
02058     else /* FIFO == FDCAN_CFG_RX_FIFO1 */
02059     {
02060       MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
02061     }
02062
02063     /* Return function status */
02064     return HAL_OK;
02065   }
02066   else
02067   {
02068     /* Update error code */
02069     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02070
02071     return HAL_ERROR;
02072   }
02073 }
02074
02075 /**
02076   * @brief  Configure the RAM watchdog.
02077   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02078   *         the configuration information for the specified FDCAN.
02079   * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
02080   *         This parameter must be a number between 0x00 and 0xFF,
02081   *         with the reset value of 0x00 the counter is disabled.
02082   * @retval HAL status
02083   */
02084 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
02085 {
02086   /* Check function parameters */
02087   assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
02088
02089   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02090   {
02091     /* Configure the RAM watchdog counter start value */
02092     MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
02093
02094     /* Return function status */
02095     return HAL_OK;
02096   }
02097   else
02098   {
02099     /* Update error code */
02100     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02101
02102     return HAL_ERROR;
02103   }
02104 }
02105
02106 /**
02107   * @brief  Configure the timestamp counter.
02108   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02109   *         the configuration information for the specified FDCAN.
02110   * @param  TimestampPrescaler Timestamp Counter Prescaler.
02111   *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
02112   * @retval HAL status
02113   */
02114 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
02115 {
02116   /* Check function parameters */
02117   assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
02118
02119   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02120   {
02121     /* Configure prescaler */
02122     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
02123
02124     /* Return function status */
02125     return HAL_OK;
02126   }
02127   else
02128   {
02129     /* Update error code */
02130     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02131
02132     return HAL_ERROR;
02133   }
02134 }
02135
02136 /**
02137   * @brief  Enable the timestamp counter.
02138   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02139   *         the configuration information for the specified FDCAN.
02140   * @param  TimestampOperation Timestamp counter operation.
02141   *         This parameter can be a value of @arg FDCAN_Timestamp.
02142   * @retval HAL status
02143   */
02144 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
02145 {
02146   /* Check function parameters */
02147   assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
02148
02149   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02150   {
02151     /* Enable timestamp counter */
02152     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
02153
02154     /* Return function status */
02155     return HAL_OK;
02156   }
02157   else
02158   {
02159     /* Update error code */
02160     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02161
02162     return HAL_ERROR;
02163   }
02164 }
02165
02166 /**
02167   * @brief  Disable the timestamp counter.
02168   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02169   *         the configuration information for the specified FDCAN.
02170   * @retval HAL status
02171   */
02172 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
02173 {
02174   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02175   {
02176     /* Disable timestamp counter */
02177     CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
02178
02179     /* Return function status */
02180     return HAL_OK;
02181   }
02182   else
02183   {
02184     /* Update error code */
02185     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02186
02187     return HAL_ERROR;
02188   }
02189 }
02190
02191 /**
02192   * @brief  Get the timestamp counter value.
02193   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02194   *         the configuration information for the specified FDCAN.
02195   * @retval Value Timestamp counter value
02196   */
02197 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
02198 {
02199   return (uint16_t)(hfdcan->Instance->TSCV);
02200 }
02201
02202 /**
02203   * @brief  Reset the timestamp counter to zero.
02204   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02205   *         the configuration information for the specified FDCAN.
02206   * @retval HAL status
02207   */
02208 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
02209 {
02210   if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
02211   {
02212     /* Reset timestamp counter.
02213        Actually any write operation to TSCV clears the counter */
02214     CLEAR_REG(hfdcan->Instance->TSCV);
02215   }
02216   else
02217   {
02218     /* Update error code.
02219        Unable to reset external counter */
02220     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
02221
02222     return HAL_ERROR;
02223   }
02224
02225   /* Return function status */
02226   return HAL_OK;
02227 }
02228
02229 /**
02230   * @brief  Configure the timeout counter.
02231   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02232   *         the configuration information for the specified FDCAN.
02233   * @param  TimeoutOperation Timeout counter operation.
02234   *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
02235   * @param  TimeoutPeriod Start value of the timeout down-counter.
02236   *         This parameter must be a number between 0x0000 and 0xFFFF
02237   * @retval HAL status
02238   */
02239 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
02240 {
02241   /* Check function parameters */
02242   assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
02243   assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
02244
02245   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02246   {
02247     /* Select timeout operation and configure period */
02248     MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
02249
02250     /* Return function status */
02251     return HAL_OK;
02252   }
02253   else
02254   {
02255     /* Update error code */
02256     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02257
02258     return HAL_ERROR;
02259   }
02260 }
02261
02262 /**
02263   * @brief  Enable the timeout counter.
02264   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02265   *         the configuration information for the specified FDCAN.
02266   * @retval HAL status
02267   */
02268 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
02269 {
02270   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02271   {
02272     /* Enable timeout counter */
02273     SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
02274
02275     /* Return function status */
02276     return HAL_OK;
02277   }
02278   else
02279   {
02280     /* Update error code */
02281     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02282
02283     return HAL_ERROR;
02284   }
02285 }
02286
02287 /**
02288   * @brief  Disable the timeout counter.
02289   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02290   *         the configuration information for the specified FDCAN.
02291   * @retval HAL status
02292   */
02293 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
02294 {
02295   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02296   {
02297     /* Disable timeout counter */
02298     CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
02299
02300     /* Return function status */
02301     return HAL_OK;
02302   }
02303   else
02304   {
02305     /* Update error code */
02306     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02307
02308     return HAL_ERROR;
02309   }
02310 }
02311
02312 /**
02313   * @brief  Get the timeout counter value.
02314   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02315   *         the configuration information for the specified FDCAN.
02316   * @retval Value Timeout counter value
02317   */
02318 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
02319 {
02320   return (uint16_t)(hfdcan->Instance->TOCV);
02321 }
02322
02323 /**
02324   * @brief  Reset the timeout counter to its start value.
02325   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02326   *         the configuration information for the specified FDCAN.
02327   * @retval HAL status
02328   */
02329 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
02330 {
02331   if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
02332   {
02333     /* Reset timeout counter to start value */
02334     CLEAR_REG(hfdcan->Instance->TOCV);
02335
02336     /* Return function status */
02337     return HAL_OK;
02338   }
02339   else
02340   {
02341     /* Update error code.
02342        Unable to reset counter: controlled only by FIFO empty state */
02343     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
02344
02345     return HAL_ERROR;
02346   }
02347 }
02348
02349 /**
02350   * @brief  Configure the transmitter delay compensation.
02351   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02352   *         the configuration information for the specified FDCAN.
02353   * @param  TdcOffset Transmitter Delay Compensation Offset.
02354   *         This parameter must be a number between 0x00 and 0x7F.
02355   * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
02356   *         This parameter must be a number between 0x00 and 0x7F.
02357   * @retval HAL status
02358   */
02359 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
02360 {
02361   /* Check function parameters */
02362   assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
02363   assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
02364
02365   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02366   {
02367     /* Configure TDC offset and filter window */
02368     hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
02369
02370     /* Return function status */
02371     return HAL_OK;
02372   }
02373   else
02374   {
02375     /* Update error code */
02376     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02377
02378     return HAL_ERROR;
02379   }
02380 }
02381
02382 /**
02383   * @brief  Enable the transmitter delay compensation.
02384   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02385   *         the configuration information for the specified FDCAN.
02386   * @retval HAL status
02387   */
02388 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
02389 {
02390   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02391   {
02392     /* Enable transmitter delay compensation */
02393     SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
02394
02395     /* Return function status */
02396     return HAL_OK;
02397   }
02398   else
02399   {
02400     /* Update error code */
02401     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02402
02403     return HAL_ERROR;
02404   }
02405 }
02406
02407 /**
02408   * @brief  Disable the transmitter delay compensation.
02409   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02410   *         the configuration information for the specified FDCAN.
02411   * @retval HAL status
02412   */
02413 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
02414 {
02415   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02416   {
02417     /* Disable transmitter delay compensation */
02418     CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
02419
02420     /* Return function status */
02421     return HAL_OK;
02422   }
02423   else
02424   {
02425     /* Update error code */
02426     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02427
02428     return HAL_ERROR;
02429   }
02430 }
02431
02432 /**
02433   * @brief  Enable ISO 11898-1 protocol mode.
02434   *         CAN FD frame format is according to ISO 11898-1 standard.
02435   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02436   *         the configuration information for the specified FDCAN.
02437   * @retval HAL status
02438   */
02439 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
02440 {
02441   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02442   {
02443     /* Disable Non ISO protocol mode */
02444     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
02445
02446     /* Return function status */
02447     return HAL_OK;
02448   }
02449   else
02450   {
02451     /* Update error code */
02452     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02453
02454     return HAL_ERROR;
02455   }
02456 }
02457
02458 /**
02459   * @brief  Disable ISO 11898-1 protocol mode.
02460   *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
02461   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02462   *         the configuration information for the specified FDCAN.
02463   * @retval HAL status
02464   */
02465 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
02466 {
02467   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02468   {
02469     /* Enable Non ISO protocol mode */
02470     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
02471
02472     /* Return function status */
02473     return HAL_OK;
02474   }
02475   else
02476   {
02477     /* Update error code */
02478     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02479
02480     return HAL_ERROR;
02481   }
02482 }
02483
02484 /**
02485   * @brief  Enable edge filtering during bus integration.
02486   *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
02487   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02488   *         the configuration information for the specified FDCAN.
02489   * @retval HAL status
02490   */
02491 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
02492 {
02493   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02494   {
02495     /* Enable edge filtering */
02496     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
02497
02498     /* Return function status */
02499     return HAL_OK;
02500   }
02501   else
02502   {
02503     /* Update error code */
02504     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02505
02506     return HAL_ERROR;
02507   }
02508 }
02509
02510 /**
02511   * @brief  Disable edge filtering during bus integration.
02512   *         One dominant tq is required to detect an edge for hard synchronization.
02513   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02514   *         the configuration information for the specified FDCAN.
02515   * @retval HAL status
02516   */
02517 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
02518 {
02519   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02520   {
02521     /* Disable edge filtering */
02522     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
02523
02524     /* Return function status */
02525     return HAL_OK;
02526   }
02527   else
02528   {
02529     /* Update error code */
02530     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02531
02532     return HAL_ERROR;
02533   }
02534 }
02535
02536 /**
02537   * @}
02538   */
02539
02540 /** @defgroup FDCAN_Exported_Functions_Group3 Control functions
02541  *  @brief    Control functions
02542  *
02543 @verbatim
02544   ==============================================================================
02545                           ##### Control functions #####
02546   ==============================================================================
02547     [..]  This section provides functions allowing to:
02548       (+) HAL_FDCAN_Start                         : Start the FDCAN module
02549       (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
02550       (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
02551       (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
02552       (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
02553       (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
02554       (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
02555       (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
02556       (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
02557       (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
02558       (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
02559       (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
02560       (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
02561       (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
02562       (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
02563       (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
02564       (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
02565       (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
02566
02567 @endverbatim
02568   * @{
02569   */
02570
02571 /**
02572   * @brief  Start the FDCAN module.
02573   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02574   *         the configuration information for the specified FDCAN.
02575   * @retval HAL status
02576   */
02577 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
02578 {
02579   if (hfdcan->State == HAL_FDCAN_STATE_READY)
02580   {
02581     /* Change FDCAN peripheral state */
02582     hfdcan->State = HAL_FDCAN_STATE_BUSY;
02583
02584     /* Request leave initialisation */
02585     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02586
02587     /* Reset the FDCAN ErrorCode */
02588     hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
02589
02590     /* Return function status */
02591     return HAL_OK;
02592   }
02593   else
02594   {
02595     /* Update error code */
02596     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02597
02598     return HAL_ERROR;
02599   }
02600 }
02601
02602 /**
02603   * @brief  Stop the FDCAN module and enable access to configuration registers.
02604   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02605   *         the configuration information for the specified FDCAN.
02606   * @retval HAL status
02607   */
02608 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
02609 {
02610   uint32_t Counter = 0U;
02611
02612   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02613   {
02614     /* Request initialisation */
02615     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02616
02617     /* Wait until the INIT bit into CCCR register is set */
02618     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
02619     {
02620       /* Check for the Timeout */
02621       if (Counter > FDCAN_TIMEOUT_VALUE)
02622       {
02623         /* Update error code */
02624         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02625
02626         /* Change FDCAN state */
02627         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02628
02629         return HAL_ERROR;
02630       }
02631
02632       /* Increment counter */
02633       Counter++;
02634     }
02635
02636     /* Reset counter */
02637     Counter = 0U;
02638
02639     /* Exit from Sleep mode */
02640     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
02641
02642     /* Wait until FDCAN exits sleep mode */
02643     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
02644     {
02645       /* Check for the Timeout */
02646       if (Counter > FDCAN_TIMEOUT_VALUE)
02647       {
02648         /* Update error code */
02649         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02650
02651         /* Change FDCAN state */
02652         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02653
02654         return HAL_ERROR;
02655       }
02656
02657       /* Increment counter */
02658       Counter++;
02659     }
02660
02661     /* Enable configuration change */
02662     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
02663
02664     /* Reset Latest Tx FIFO/Queue Request Buffer Index */
02665     hfdcan->LatestTxFifoQRequest = 0U;
02666
02667     /* Change FDCAN peripheral state */
02668     hfdcan->State = HAL_FDCAN_STATE_READY;
02669
02670     /* Return function status */
02671     return HAL_OK;
02672   }
02673   else
02674   {
02675     /* Update error code */
02676     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02677
02678     return HAL_ERROR;
02679   }
02680 }
02681
02682 /**
02683   * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
02684   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02685   *         the configuration information for the specified FDCAN.
02686   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
02687   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
02688   * @retval HAL status
02689   */
02690 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
02691 {
02692   uint32_t PutIndex;
02693
02694   /* Check function parameters */
02695   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
02696   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
02697   {
02698     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
02699   }
02700   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
02701   {
02702     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
02703   }
02704   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
02705   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
02706   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
02707   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
02708   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
02709   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
02710   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
02711
02712   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02713   {
02714     /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
02715     if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
02716     {
02717       /* Update error code */
02718       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02719
02720       return HAL_ERROR;
02721     }
02722
02723     /* Check that the Tx FIFO/Queue is not full */
02724     if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
02725     {
02726       /* Update error code */
02727       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
02728
02729       return HAL_ERROR;
02730     }
02731     else
02732     {
02733       /* Retrieve the Tx FIFO PutIndex */
02734       PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
02735
02736       /* Add the message to the Tx FIFO/Queue */
02737       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
02738
02739       /* Activate the corresponding transmission request */
02740       hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
02741
02742       /* Store the Latest Tx FIFO/Queue Request Buffer Index */
02743       hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
02744     }
02745
02746     /* Return function status */
02747     return HAL_OK;
02748   }
02749   else
02750   {
02751     /* Update error code */
02752     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02753
02754     return HAL_ERROR;
02755   }
02756 }
02757
02758 /**
02759   * @brief  Add a message to a dedicated Tx buffer
02760   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02761   *         the configuration information for the specified FDCAN.
02762   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
02763   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
02764   * @param  BufferIndex index of the buffer to be configured.
02765   *         This parameter can be a value of @arg FDCAN_Tx_location.
02766   * @retval HAL status
02767   */
02768 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
02769 {
02770   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02771
02772   /* Check function parameters */
02773   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
02774   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
02775   {
02776     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
02777   }
02778   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
02779   {
02780     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
02781   }
02782   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
02783   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
02784   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
02785   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
02786   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
02787   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
02788   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
02789   assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
02790
02791   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02792   {
02793     /* Check that the selected buffer has an allocated area into the RAM */
02794     if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
02795     {
02796       /* Update error code */
02797       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02798
02799       return HAL_ERROR;
02800     }
02801
02802     /* Check that there is no transmittion request pending for the selected buffer */
02803     if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
02804     {
02805       /* Update error code */
02806       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
02807
02808       return HAL_ERROR;
02809     }
02810     else
02811     {
02812       /* Add the message to the Tx buffer */
02813       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
02814     }
02815
02816     /* Return function status */
02817     return HAL_OK;
02818   }
02819   else
02820   {
02821     /* Update error code */
02822     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02823
02824     return HAL_ERROR;
02825   }
02826 }
02827
02828 /**
02829   * @brief  Enable transmission request.
02830   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02831   *         the configuration information for the specified FDCAN.
02832   * @param  BufferIndex buffer index.
02833   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02834   * @retval HAL status
02835   */
02836 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
02837 {
02838   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02839   {
02840     /* Add transmission request */
02841     hfdcan->Instance->TXBAR = BufferIndex;
02842
02843     /* Return function status */
02844     return HAL_OK;
02845   }
02846   else
02847   {
02848     /* Update error code */
02849     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02850
02851     return HAL_ERROR;
02852   }
02853 }
02854
02855 /**
02856   * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
02857   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02858   *         the configuration information for the specified FDCAN.
02859   * @retval Tx buffer index of last Tx FIFO/Queue request
02860   *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
02861   *          - 0 if no Tx FIFO/Queue request have been submitted.
02862   */
02863 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
02864 {
02865   /* Return Last Tx FIFO/Queue Request Buffer */
02866   return hfdcan->LatestTxFifoQRequest;
02867 }
02868
02869 /**
02870   * @brief  Abort transmission request
02871   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02872   *         the configuration information for the specified FDCAN.
02873   * @param  BufferIndex buffer index.
02874   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02875   * @retval HAL status
02876   */
02877 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
02878 {
02879   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02880   {
02881     /* Add cancellation request */
02882     hfdcan->Instance->TXBCR = BufferIndex;
02883
02884     /* Return function status */
02885     return HAL_OK;
02886   }
02887   else
02888   {
02889     /* Update error code */
02890     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02891
02892     return HAL_ERROR;
02893   }
02894 }
02895
02896 /**
02897   * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
02898   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02899   *         the configuration information for the specified FDCAN.
02900   * @param  RxLocation Location of the received message to be read.
02901   *         This parameter can be a value of @arg FDCAN_Rx_location.
02902   * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
02903   * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
02904   * @retval HAL status
02905   */
02906 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
02907 {
02908   uint32_t *RxAddress;
02909   uint8_t  *pData;
02910   uint32_t ByteCounter;
02911   uint32_t GetIndex = 0;
02912   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02913
02914   if (state == HAL_FDCAN_STATE_BUSY)
02915   {
02916     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
02917     {
02918       /* Check that the Rx FIFO 0 has an allocated area into the RAM */
02919       if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
02920       {
02921         /* Update error code */
02922         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02923
02924         return HAL_ERROR;
02925       }
02926
02927       /* Check that the Rx FIFO 0 is not empty */
02928       if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
02929       {
02930         /* Update error code */
02931         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02932
02933         return HAL_ERROR;
02934       }
02935       else
02936       {
02937         /* Calculate Rx FIFO 0 element address */
02938         GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
02939         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
02940       }
02941     }
02942     else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
02943     {
02944       /* Check that the Rx FIFO 1 has an allocated area into the RAM */
02945       if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
02946       {
02947         /* Update error code */
02948         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02949
02950         return HAL_ERROR;
02951       }
02952
02953       /* Check that the Rx FIFO 0 is not empty */
02954       if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
02955       {
02956         /* Update error code */
02957         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02958
02959         return HAL_ERROR;
02960       }
02961       else
02962       {
02963         /* Calculate Rx FIFO 1 element address */
02964         GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
02965         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
02966       }
02967     }
02968     else /* Rx element is assigned to a dedicated Rx buffer */
02969     {
02970       /* Check that the selected buffer has an allocated area into the RAM */
02971       if (RxLocation >= hfdcan->Init.RxBuffersNbr)
02972       {
02973         /* Update error code */
02974         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02975
02976         return HAL_ERROR;
02977       }
02978       else
02979       {
02980         /* Calculate Rx buffer address */
02981         RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
02982       }
02983     }
02984
02985     /* Retrieve IdType */
02986     pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
02987
02988     /* Retrieve Identifier */
02989     if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
02990     {
02991       pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
02992     }
02993     else /* Extended ID element */
02994     {
02995       pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
02996     }
02997
02998     /* Retrieve RxFrameType */
02999     pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
03000
03001     /* Retrieve ErrorStateIndicator */
03002     pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
03003
03004     /* Increment RxAddress pointer to second word of Rx FIFO element */
03005     RxAddress++;
03006
03007     /* Retrieve RxTimestamp */
03008     pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
03009
03010     /* Retrieve DataLength */
03011     pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
03012
03013     /* Retrieve BitRateSwitch */
03014     pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
03015
03016     /* Retrieve FDFormat */
03017     pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
03018
03019     /* Retrieve FilterIndex */
03020     pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
03021
03022     /* Retrieve NonMatchingFrame */
03023     pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
03024
03025     /* Increment RxAddress pointer to payload of Rx FIFO element */
03026     RxAddress++;
03027
03028     /* Retrieve Rx payload */
03029     pData = (uint8_t *)RxAddress;
03030     for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
03031     {
03032       pRxData[ByteCounter] = pData[ByteCounter];
03033     }
03034
03035     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
03036     {
03037       /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
03038       hfdcan->Instance->RXF0A = GetIndex;
03039     }
03040     else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
03041     {
03042       /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
03043       hfdcan->Instance->RXF1A = GetIndex;
03044     }
03045     else /* Rx element is assigned to a dedicated Rx buffer */
03046     {
03047       /* Clear the New Data flag of the current Rx buffer */
03048       if (RxLocation < FDCAN_RX_BUFFER32)
03049       {
03050         hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
03051       }
03052       else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
03053       {
03054         hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
03055       }
03056     }
03057
03058     /* Return function status */
03059     return HAL_OK;
03060   }
03061   else
03062   {
03063     /* Update error code */
03064     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
03065
03066     return HAL_ERROR;
03067   }
03068 }
03069
03070 /**
03071   * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
03072   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03073   *         the configuration information for the specified FDCAN.
03074   * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
03075   * @retval HAL status
03076   */
03077 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
03078 {
03079   uint32_t *TxEventAddress;
03080   uint32_t GetIndex;
03081   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03082
03083   /* Check function parameters */
03084   assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
03085
03086   if (state == HAL_FDCAN_STATE_BUSY)
03087   {
03088     /* Check that the Tx Event FIFO has an allocated area into the RAM */
03089     if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
03090     {
03091       /* Update error code */
03092       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
03093
03094       return HAL_ERROR;
03095     }
03096
03097     /* Check that the Tx event FIFO is not empty */
03098     if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
03099     {
03100       /* Update error code */
03101       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
03102
03103       return HAL_ERROR;
03104     }
03105
03106     /* Calculate Tx event FIFO element address */
03107     GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
03108     TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
03109
03110     /* Retrieve IdType */
03111     pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
03112
03113     /* Retrieve Identifier */
03114     if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
03115     {
03116       pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
03117     }
03118     else /* Extended ID element */
03119     {
03120       pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
03121     }
03122
03123     /* Retrieve RxFrameType */
03124     pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
03125
03126     /* Retrieve ErrorStateIndicator */
03127     pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
03128
03129     /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
03130     TxEventAddress++;
03131
03132     /* Retrieve RxTimestamp */
03133     pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
03134
03135     /* Retrieve DataLength */
03136     pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
03137
03138     /* Retrieve BitRateSwitch */
03139     pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
03140
03141     /* Retrieve FDFormat */
03142     pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
03143
03144     /* Retrieve EventType */
03145     pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
03146
03147     /* Retrieve MessageMarker */
03148     pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
03149
03150     /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
03151     hfdcan->Instance->TXEFA = GetIndex;
03152
03153     /* Return function status */
03154     return HAL_OK;
03155   }
03156   else
03157   {
03158     /* Update error code */
03159     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
03160
03161     return HAL_ERROR;
03162   }
03163 }
03164
03165 /**
03166   * @brief  Get high priority message status.
03167   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03168   *         the configuration information for the specified FDCAN.
03169   * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
03170   * @retval HAL status
03171   */
03172 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
03173 {
03174   HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
03175   HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
03176   HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
03177   HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
03178
03179   /* Return function status */
03180   return HAL_OK;
03181 }
03182
03183 /**
03184   * @brief  Get protocol status.
03185   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03186   *         the configuration information for the specified FDCAN.
03187   * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
03188   * @retval HAL status
03189   */
03190 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
03191 {
03192   uint32_t StatusReg;
03193
03194   /* Read the protocol status register */
03195   StatusReg = READ_REG(hfdcan->Instance->PSR);
03196
03197   /* Fill the protocol status structure */
03198   ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
03199   ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
03200   ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
03201   ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
03202   ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
03203   ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
03204   ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
03205   ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
03206   ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
03207   ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
03208   ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
03209
03210   /* Return function status */
03211   return HAL_OK;
03212 }
03213
03214 /**
03215   * @brief  Get error counter values.
03216   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03217   *         the configuration information for the specified FDCAN.
03218   * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
03219   * @retval HAL status
03220   */
03221 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
03222 {
03223   uint32_t CountersReg;
03224
03225   /* Read the error counters register */
03226   CountersReg = READ_REG(hfdcan->Instance->ECR);
03227
03228   /* Fill the error counters structure */
03229   ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
03230   ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
03231   ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
03232   ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
03233
03234   /* Return function status */
03235   return HAL_OK;
03236 }
03237
03238 /**
03239   * @brief  Check if a new message is received in the selected Rx buffer.
03240   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03241   *         the configuration information for the specified FDCAN.
03242   * @param  RxBufferIndex Rx buffer index.
03243   *         This parameter must be a number between 0 and 63.
03244   * @retval Status
03245   *          - 0 : No new message on RxBufferIndex.
03246   *          - 1 : New message received on RxBufferIndex.
03247   */
03248 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
03249 {
03250   /* Check function parameters */
03251   assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
03252   uint32_t NewData1 = hfdcan->Instance->NDAT1;
03253   uint32_t NewData2 = hfdcan->Instance->NDAT2;
03254
03255   /* Check new message reception on the selected buffer */
03256   if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
03257       ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
03258   {
03259     return 0;
03260   }
03261
03262   /* Clear the New Data flag of the current Rx buffer */
03263   if (RxBufferIndex < 32U)
03264   {
03265     hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
03266   }
03267   else /* 32 <= RxBufferIndex <= 63 */
03268   {
03269     hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
03270   }
03271
03272   return 1;
03273 }
03274
03275 /**
03276   * @brief  Check if a transmission request is pending on the selected Tx buffer.
03277   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03278   *         the configuration information for the specified FDCAN.
03279   * @param  TxBufferIndex Tx buffer index.
03280   *         This parameter can be any combination of @arg FDCAN_Tx_location.
03281   * @retval Status
03282   *          - 0 : No pending transmission request on TxBufferIndex.
03283   *          - 1 : Pending transmission request on TxBufferIndex.
03284   */
03285 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
03286 {
03287   /* Check pending transmittion request on the selected buffer */
03288   if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
03289   {
03290     return 0;
03291   }
03292   return 1;
03293 }
03294
03295 /**
03296   * @brief  Return Rx FIFO fill level.
03297   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03298   *         the configuration information for the specified FDCAN.
03299   * @param  RxFifo Rx FIFO.
03300   *         This parameter can be one of the following values:
03301   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
03302   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
03303   * @retval Level Rx FIFO fill level.
03304   */
03305 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
03306 {
03307   uint32_t FillLevel;
03308
03309   /* Check function parameters */
03310   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
03311
03312   if (RxFifo == FDCAN_RX_FIFO0)
03313   {
03314     FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
03315   }
03316   else /* RxFifo == FDCAN_RX_FIFO1 */
03317   {
03318     FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
03319   }
03320
03321   /* Return Rx FIFO fill level */
03322   return FillLevel;
03323 }
03324
03325 /**
03326   * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
03327   *         elements starting from Tx FIFO GetIndex.
03328   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03329   *         the configuration information for the specified FDCAN.
03330   * @retval Level Tx FIFO free level.
03331   */
03332 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
03333 {
03334   uint32_t FreeLevel;
03335
03336   FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
03337
03338   /* Return Tx FIFO free level */
03339   return FreeLevel;
03340 }
03341
03342 /**
03343   * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
03344   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03345   *         the configuration information for the specified FDCAN.
03346   * @retval Status
03347   *          - 0 : Normal FDCAN operation.
03348   *          - 1 : Restricted Operation Mode active.
03349   */
03350 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
03351 {
03352   uint32_t OperationMode;
03353
03354   /* Get Operation Mode */
03355   OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
03356
03357   return OperationMode;
03358 }
03359
03360 /**
03361   * @brief  Exit Restricted Operation Mode.
03362   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03363   *         the configuration information for the specified FDCAN.
03364   * @retval HAL status
03365   */
03366 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
03367 {
03368   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03369
03370   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
03371   {
03372     /* Exit Restricted Operation mode */
03373     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
03374
03375     /* Return function status */
03376     return HAL_OK;
03377   }
03378   else
03379   {
03380     /* Update error code */
03381     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03382
03383     return HAL_ERROR;
03384   }
03385 }
03386
03387 /**
03388   * @}
03389   */
03390
03391 /** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
03392  *  @brief    TT Configuration and control functions
03393  *
03394 @verbatim
03395   ==============================================================================
03396               ##### TT Configuration and control functions #####
03397   ==============================================================================
03398     [..]  This section provides functions allowing to:
03399       (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
03400       (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
03401       (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
03402       (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
03403       (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
03404       (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
03405       (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
03406         (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
03407         (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
03408       (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
03409       (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
03410       (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
03411       (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
03412       (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
03413       (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
03414       (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
03415       (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
03416       (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
03417         (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
03418         (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
03419       (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
03420
03421 @endverbatim
03422   * @{
03423   */
03424
03425 /**
03426   * @brief  Initialize TT operation parameters.
03427   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03428   *         the configuration information for the specified FDCAN.
03429   * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
03430   * @retval HAL status
03431   */
03432 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
03433 {
03434   uint32_t tickstart;
03435   uint32_t RAMcounter;
03436   uint32_t StartAddress;
03437
03438   /* Check function parameters */
03439   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03440   assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
03441   assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
03442   assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
03443   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
03444   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
03445   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
03446   assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
03447   assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
03448   assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
03449   if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
03450   {
03451     assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
03452   }
03453   if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
03454   {
03455     assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
03456     assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
03457     assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
03458     assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
03459     assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
03460   }
03461   if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
03462   {
03463     assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
03464     assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
03465     assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
03466     assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
03467   }
03468   else
03469   {
03470     assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
03471   }
03472
03473   if (hfdcan->State == HAL_FDCAN_STATE_READY)
03474   {
03475     /* Stop local time in order to enable write access to the other bits of TURCF register */
03476     CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
03477
03478     /* Get tick */
03479     tickstart = HAL_GetTick();
03480
03481     /* Wait until the ELT bit into TURCF register is reset */
03482     while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
03483     {
03484       /* Check for the Timeout */
03485       if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
03486       {
03487         /* Update error code */
03488         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03489
03490         /* Change FDCAN state */
03491         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03492
03493         return HAL_ERROR;
03494       }
03495     }
03496
03497     /* Configure TUR (Time Unit Ratio) */
03498     MODIFY_REG(hfdcan->ttcan->TURCF,
03499                (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
03500                (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
03501
03502     /* Enable local time */
03503     SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
03504
03505     /* Configure TT operation */
03506     MODIFY_REG(hfdcan->ttcan->TTOCF,
03507                (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
03508                (pTTParams->OperationMode                           | \
03509                 pTTParams->TimeMaster                              | \
03510                 (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
03511                 (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
03512     if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
03513     {
03514       MODIFY_REG(hfdcan->ttcan->TTOCF,
03515                  (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
03516                  (pTTParams->GapEnable                            | \
03517                   (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
03518                   pTTParams->EvtTrigPolarity));
03519     }
03520     if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
03521     {
03522       MODIFY_REG(hfdcan->ttcan->TTOCF,
03523                  (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
03524                  (pTTParams->ExternalClkSync  | \
03525                   pTTParams->GlobalTimeFilter | \
03526                   pTTParams->ClockCalibration));
03527     }
03528
03529     /* Configure system matrix limits */
03530     MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
03531     if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
03532     {
03533       MODIFY_REG(hfdcan->ttcan->TTMLM,
03534                  (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
03535                  (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
03536     }
03537     if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
03538     {
03539       MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
03540     }
03541
03542     /* Configure input triggers: Stop watch and Event */
03543     MODIFY_REG(hfdcan->ttcan->TTTS,
03544                (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
03545                (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
03546
03547     /* Configure trigger memory start address */
03548     StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
03549     MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
03550
03551     /* Trigger memory elements number */
03552     MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
03553
03554     /* Recalculate End Address */
03555     hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
03556     hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
03557
03558     if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
03559     {
03560       /* Update error code.
03561          Message RAM overflow */
03562       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
03563
03564       return HAL_ERROR;
03565     }
03566     else
03567     {
03568       /* Flush the allocated Message RAM area */
03569       for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
03570       {
03571         *(uint32_t *)(RAMcounter) = 0x00000000;
03572       }
03573     }
03574
03575     /* Return function status */
03576     return HAL_OK;
03577   }
03578   else
03579   {
03580     /* Update error code */
03581     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
03582
03583     return HAL_ERROR;
03584   }
03585 }
03586
03587 /**
03588   * @brief  Configure the reference message.
03589   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03590   *         the configuration information for the specified FDCAN.
03591   * @param  IdType Identifier Type.
03592   *         This parameter can be a value of @arg FDCAN_id_type.
03593   * @param  Identifier Reference Identifier.
03594   *         This parameter must be a number between:
03595   *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
03596   *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
03597   * @param  Payload Enable or disable the additional payload.
03598   *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
03599   *         This parameter is ignored in case of time slaves.
03600   *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
03601   *         following elements are taken from Tx Buffer 0:
03602   *          - MessageMarker
03603   *          - TxEventFifoControl
03604   *          - DataLength
03605   *          - Data Bytes (payload):
03606   *             - bytes 2-8, for Level 1
03607   *             - bytes 5-8, for Level 0 and Level 2
03608   * @retval HAL status
03609   */
03610 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
03611 {
03612   /* Check function parameters */
03613   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03614   assert_param(IS_FDCAN_ID_TYPE(IdType));
03615   if (IdType == FDCAN_STANDARD_ID)
03616   {
03617     assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
03618   }
03619   else /* IdType == FDCAN_EXTENDED_ID */
03620   {
03621     assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
03622   }
03623   assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
03624
03625   if (hfdcan->State == HAL_FDCAN_STATE_READY)
03626   {
03627     /* Configure reference message identifier type, identifier and payload */
03628     if (IdType == FDCAN_EXTENDED_ID)
03629     {
03630       MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
03631     }
03632     else /* IdType == FDCAN_STANDARD_ID */
03633     {
03634       MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
03635     }
03636
03637     /* Return function status */
03638     return HAL_OK;
03639   }
03640   else
03641   {
03642     /* Update error code */
03643     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
03644
03645     return HAL_ERROR;
03646   }
03647 }
03648
03649 /**
03650   * @brief  Configure the FDCAN trigger according to the specified
03651   *         parameters in the FDCAN_TriggerTypeDef structure.
03652   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03653   *         the configuration information for the specified FDCAN.
03654   * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
03655   *         contains the trigger configuration information
03656   * @retval HAL status
03657   */
03658 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
03659 {
03660   uint32_t CycleCode;
03661   uint32_t MessageNumber;
03662   uint32_t TriggerElementW1;
03663   uint32_t TriggerElementW2;
03664   uint32_t *TriggerAddress;
03665
03666   /* Check function parameters */
03667   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03668   assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
03669   assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
03670   assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
03671   if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
03672   {
03673     assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
03674   }
03675   assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
03676   assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
03677   assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
03678   assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
03679   if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
03680       (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
03681       (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
03682       (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
03683   {
03684     assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
03685   }
03686   if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
03687   {
03688     if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
03689     {
03690       assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
03691     }
03692     else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
03693     {
03694       assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
03695     }
03696   }
03697
03698   if (hfdcan->State == HAL_FDCAN_STATE_READY)
03699   {
03700     /* Calculate cycle code */
03701     if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
03702     {
03703       CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
03704     }
03705     else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
03706     {
03707       CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
03708     }
03709
03710     /* Build first word of trigger element */
03711     TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
03712                         (CycleCode << 8)                 | \
03713                         sTriggerConfig->TmEventInt       | \
03714                         sTriggerConfig->TmEventExt       | \
03715                         sTriggerConfig->TriggerType);
03716
03717     /* Select message number depending on trigger type (transmission or reception) */
03718     if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
03719     {
03720       MessageNumber = sTriggerConfig->FilterIndex;
03721     }
03722     else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
03723              (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
03724              (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
03725              (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
03726     {
03727       MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
03728     }
03729     else
03730     {
03731       MessageNumber = 0U;
03732     }
03733
03734     /* Build second word of trigger element */
03735     TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
03736
03737     /* Calculate trigger address */
03738     TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
03739
03740     /* Write trigger element to the message RAM */
03741     *TriggerAddress = TriggerElementW1;
03742     TriggerAddress++;
03743     *TriggerAddress = TriggerElementW2;
03744
03745     /* Return function status */
03746     return HAL_OK;
03747   }
03748   else
03749   {
03750     /* Update error code */
03751     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
03752
03753     return HAL_ERROR;
03754   }
03755 }
03756
03757 /**
03758   * @brief  Schedule global time adjustment for the next reference message.
03759   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03760   *         the configuration information for the specified FDCAN.
03761   * @param  TimePreset time preset value.
03762   *         This parameter must be a number between:
03763   *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
03764   *           or
03765   *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
03766   * @retval HAL status
03767   */
03768 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
03769 {
03770   uint32_t Counter = 0U;
03771   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03772
03773   /* Check function parameters */
03774   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03775   assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
03776
03777   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
03778   {
03779     /* Check that the external clock synchronization is enabled */
03780     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
03781     {
03782       /* Update error code */
03783       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03784
03785       return HAL_ERROR;
03786     }
03787
03788     /* Check that no global time preset is pending */
03789     if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
03790     {
03791       /* Update error code */
03792       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
03793
03794       return HAL_ERROR;
03795     }
03796
03797     /* Configure time preset */
03798     MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
03799
03800     /* Wait until the LCKC bit into TTOCN register is reset */
03801     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
03802     {
03803       /* Check for the Timeout */
03804       if (Counter > FDCAN_TIMEOUT_VALUE)
03805       {
03806         /* Update error code */
03807         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03808
03809         /* Change FDCAN state */
03810         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03811
03812         return HAL_ERROR;
03813       }
03814
03815       /* Increment counter */
03816       Counter++;
03817     }
03818
03819     /* Schedule time preset to take effect by the next reference message */
03820     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
03821
03822     /* Return function status */
03823     return HAL_OK;
03824   }
03825   else
03826   {
03827     /* Update error code */
03828     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03829
03830     return HAL_ERROR;
03831   }
03832 }
03833
03834 /**
03835   * @brief  Schedule TUR numerator update for the next reference message.
03836   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03837   *         the configuration information for the specified FDCAN.
03838   * @param  NewTURNumerator new value of the TUR numerator.
03839   *         This parameter must be a number between 0x10000 and 0x1FFFF.
03840   * @retval HAL status
03841   */
03842 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
03843 {
03844   uint32_t Counter = 0U;
03845   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03846
03847   /* Check function parameters */
03848   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03849   assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
03850
03851   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
03852   {
03853     /* Check that the external clock synchronization is enabled */
03854     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
03855     {
03856       /* Update error code */
03857       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03858
03859       return HAL_ERROR;
03860     }
03861
03862     /* Check that no external clock synchronization is pending */
03863     if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
03864     {
03865       /* Update error code */
03866       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
03867
03868       return HAL_ERROR;
03869     }
03870
03871     /* Configure new TUR numerator */
03872     MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
03873
03874     /* Wait until the LCKC bit into TTOCN register is reset */
03875     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
03876     {
03877       /* Check for the Timeout */
03878       if (Counter > FDCAN_TIMEOUT_VALUE)
03879       {
03880         /* Update error code */
03881         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03882
03883         /* Change FDCAN state */
03884         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03885
03886         return HAL_ERROR;
03887       }
03888
03889       /* Increment counter */
03890       Counter++;
03891     }
03892
03893     /* Schedule TUR numerator update by the next reference message */
03894     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
03895
03896     /* Return function status */
03897     return HAL_OK;
03898   }
03899   else
03900   {
03901     /* Update error code */
03902     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03903
03904     return HAL_ERROR;
03905   }
03906 }
03907
03908 /**
03909   * @brief  Configure stop watch source and polarity.
03910   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03911   *         the configuration information for the specified FDCAN.
03912   * @param  Source stop watch source.
03913   *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
03914   * @param  Polarity stop watch polarity.
03915   *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
03916   * @retval HAL status
03917   */
03918 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
03919 {
03920   uint32_t Counter = 0U;
03921   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03922
03923   /* Check function parameters */
03924   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03925   assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
03926   assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
03927
03928   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
03929   {
03930     /* Wait until the LCKC bit into TTOCN register is reset */
03931     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
03932     {
03933       /* Check for the Timeout */
03934       if (Counter > FDCAN_TIMEOUT_VALUE)
03935       {
03936         /* Update error code */
03937         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03938
03939         /* Change FDCAN state */
03940         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03941
03942         return HAL_ERROR;
03943       }
03944
03945       /* Increment counter */
03946       Counter++;
03947     }
03948
03949     /* Select stop watch source and polarity */
03950     MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
03951
03952     /* Return function status */
03953     return HAL_OK;
03954   }
03955   else
03956   {
03957     /* Update error code */
03958     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03959
03960     return HAL_ERROR;
03961   }
03962 }
03963
03964 /**
03965   * @brief  Configure register time mark pulse generation.
03966   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03967   *         the configuration information for the specified FDCAN.
03968   * @param  TimeMarkSource time mark source.
03969   *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
03970   * @param  TimeMarkValue time mark value (reference).
03971   *         This parameter must be a number between 0 and 0xFFFF.
03972   * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
03973   *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
03974   * @param  StartCycle index of the first cycle in which the time mark becomes valid.
03975   *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
03976   *         This parameter must be a number between 0 and RepeatFactor.
03977   * @retval HAL status
03978   */
03979 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
03980                                                       uint32_t TimeMarkSource, uint32_t TimeMarkValue,
03981                                                       uint32_t RepeatFactor, uint32_t StartCycle)
03982 {
03983   uint32_t Counter = 0U;
03984   uint32_t CycleCode;
03985   HAL_FDCAN_StateTypeDef state = hfdcan->State;
03986
03987   /* Check function parameters */
03988   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03989   assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
03990   assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
03991   assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
03992   if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
03993   {
03994     assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
03995   }
03996
03997   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
03998   {
03999     /* Wait until the LCKC bit into TTOCN register is reset */
04000     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04001     {
04002       /* Check for the Timeout */
04003       if (Counter > FDCAN_TIMEOUT_VALUE)
04004       {
04005         /* Update error code */
04006         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04007
04008         /* Change FDCAN state */
04009         hfdcan->State = HAL_FDCAN_STATE_ERROR;
04010
04011         return HAL_ERROR;
04012       }
04013
04014       /* Increment counter */
04015       Counter++;
04016     }
04017
04018     /* Disable the time mark compare function */
04019     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
04020
04021     if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
04022     {
04023       /* Calculate cycle code */
04024       if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
04025       {
04026         CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
04027       }
04028       else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
04029       {
04030         CycleCode = RepeatFactor + StartCycle;
04031       }
04032
04033       Counter = 0U;
04034
04035       /* Wait until the LCKM bit into TTTMK register is reset */
04036       while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
04037       {
04038         /* Check for the Timeout */
04039         if (Counter > FDCAN_TIMEOUT_VALUE)
04040         {
04041           /* Update error code */
04042           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04043
04044           /* Change FDCAN state */
04045           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04046
04047           return HAL_ERROR;
04048         }
04049
04050         /* Increment counter */
04051         Counter++;
04052       }
04053
04054       /* Configure time mark value and cycle code */
04055       hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
04056
04057       Counter = 0U;
04058
04059       /* Wait until the LCKC bit into TTOCN register is reset */
04060       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04061       {
04062         /* Check for the Timeout */
04063         if (Counter > FDCAN_TIMEOUT_VALUE)
04064         {
04065           /* Update error code */
04066           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04067
04068           /* Change FDCAN state */
04069           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04070
04071           return HAL_ERROR;
04072         }
04073
04074         /* Increment counter */
04075         Counter++;
04076       }
04077
04078       /* Update the register time mark compare source */
04079       MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
04080     }
04081
04082     /* Return function status */
04083     return HAL_OK;
04084   }
04085   else
04086   {
04087     /* Update error code */
04088     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04089
04090     return HAL_ERROR;
04091   }
04092 }
04093
04094 /**
04095   * @brief  Enable register time mark pulse generation.
04096   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04097   *         the configuration information for the specified FDCAN.
04098   * @retval HAL status
04099   */
04100 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
04101 {
04102   uint32_t Counter = 0U;
04103   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04104
04105   /* Check function parameters */
04106   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04107
04108   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04109   {
04110     /* Wait until the LCKC bit into TTOCN register is reset */
04111     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04112     {
04113       /* Check for the Timeout */
04114       if (Counter > FDCAN_TIMEOUT_VALUE)
04115       {
04116         /* Update error code */
04117         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04118
04119         /* Change FDCAN state */
04120         hfdcan->State = HAL_FDCAN_STATE_ERROR;
04121
04122         return HAL_ERROR;
04123       }
04124
04125       /* Increment counter */
04126       Counter++;
04127     }
04128
04129     /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
04130     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
04131
04132     /* Return function status */
04133     return HAL_OK;
04134   }
04135   else
04136   {
04137     /* Update error code */
04138     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04139
04140     return HAL_ERROR;
04141   }
04142 }
04143
04144 /**
04145   * @brief  Disable register time mark pulse generation.
04146   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04147   *         the configuration information for the specified FDCAN.
04148   * @retval HAL status
04149   */
04150 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
04151 {
04152   uint32_t Counter = 0U;
04153   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04154
04155   /* Check function parameters */
04156   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04157
04158   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04159   {
04160     /* Wait until the LCKC bit into TTOCN register is reset */
04161     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04162     {
04163       /* Check for the Timeout */
04164       if (Counter > FDCAN_TIMEOUT_VALUE)
04165       {
04166         /* Update error code */
04167         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04168
04169         /* Change FDCAN state */
04170         hfdcan->State = HAL_FDCAN_STATE_ERROR;
04171
04172         return HAL_ERROR;
04173       }
04174
04175       /* Increment counter */
04176       Counter++;
04177     }
04178
04179     /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
04180     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
04181
04182     /* Return function status */
04183     return HAL_OK;
04184   }
04185   else
04186   {
04187     /* Update error code */
04188     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04189
04190     return HAL_ERROR;
04191   }
04192 }
04193
04194 /**
04195   * @brief  Enable trigger time mark pulse generation.
04196   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04197   *         the configuration information for the specified FDCAN.
04198   * @retval HAL status
04199   */
04200 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
04201 {
04202   uint32_t Counter = 0U;
04203   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04204
04205   /* Check function parameters */
04206   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04207
04208   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04209   {
04210     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04211     {
04212       /* Wait until the LCKC bit into TTOCN register is reset */
04213       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04214       {
04215         /* Check for the Timeout */
04216         if (Counter > FDCAN_TIMEOUT_VALUE)
04217         {
04218           /* Update error code */
04219           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04220
04221           /* Change FDCAN state */
04222           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04223
04224           return HAL_ERROR;
04225         }
04226
04227         /* Increment counter */
04228         Counter++;
04229       }
04230
04231       /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
04232       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
04233
04234       /* Return function status */
04235       return HAL_OK;
04236     }
04237     else
04238     {
04239       /* Update error code.
04240          Feature not supported for TT Level 0 */
04241       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04242
04243       return HAL_ERROR;
04244     }
04245   }
04246   else
04247   {
04248     /* Update error code */
04249     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04250
04251     return HAL_ERROR;
04252   }
04253 }
04254
04255 /**
04256   * @brief  Disable trigger time mark pulse generation.
04257   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04258   *         the configuration information for the specified FDCAN.
04259   * @retval HAL status
04260   */
04261 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
04262 {
04263   uint32_t Counter = 0U;
04264   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04265
04266   /* Check function parameters */
04267   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04268
04269   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04270   {
04271     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04272     {
04273       /* Wait until the LCKC bit into TTOCN register is reset */
04274       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04275       {
04276         /* Check for the Timeout */
04277         if (Counter > FDCAN_TIMEOUT_VALUE)
04278         {
04279           /* Update error code */
04280           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04281
04282           /* Change FDCAN state */
04283           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04284
04285           return HAL_ERROR;
04286         }
04287
04288         /* Increment counter */
04289         Counter++;
04290       }
04291
04292       /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
04293       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
04294
04295       /* Return function status */
04296       return HAL_OK;
04297     }
04298     else
04299     {
04300       /* Update error code.
04301          Feature not supported for TT Level 0 */
04302       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04303
04304       return HAL_ERROR;
04305     }
04306   }
04307   else
04308   {
04309     /* Update error code */
04310     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04311
04312     return HAL_ERROR;
04313   }
04314 }
04315
04316 /**
04317   * @brief  Enable gap control by input pin fdcan1_evt.
04318   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04319   *         the configuration information for the specified FDCAN.
04320   * @retval HAL status
04321   */
04322 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
04323 {
04324   uint32_t Counter = 0U;
04325   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04326
04327   /* Check function parameters */
04328   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04329
04330   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04331   {
04332     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04333     {
04334       /* Wait until the LCKC bit into TTOCN register is reset */
04335       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04336       {
04337         /* Check for the Timeout */
04338         if (Counter > FDCAN_TIMEOUT_VALUE)
04339         {
04340           /* Update error code */
04341           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04342
04343           /* Change FDCAN state */
04344           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04345
04346           return HAL_ERROR;
04347         }
04348
04349         /* Increment counter */
04350         Counter++;
04351       }
04352
04353       /* Enable gap control by pin fdcan1_evt */
04354       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
04355
04356       /* Return function status */
04357       return HAL_OK;
04358     }
04359     else
04360     {
04361       /* Update error code.
04362          Feature not supported for TT Level 0 */
04363       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04364
04365       return HAL_ERROR;
04366     }
04367   }
04368   else
04369   {
04370     /* Update error code */
04371     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04372
04373     return HAL_ERROR;
04374   }
04375 }
04376
04377 /**
04378   * @brief  Disable gap control by input pin fdcan1_evt.
04379   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04380   *         the configuration information for the specified FDCAN.
04381   * @retval HAL status
04382   */
04383 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
04384 {
04385   uint32_t Counter = 0U;
04386   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04387
04388   /* Check function parameters */
04389   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04390
04391   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04392   {
04393     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04394     {
04395       /* Wait until the LCKC bit into TTOCN register is reset */
04396       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04397       {
04398         /* Check for the Timeout */
04399         if (Counter > FDCAN_TIMEOUT_VALUE)
04400         {
04401           /* Update error code */
04402           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04403
04404           /* Change FDCAN state */
04405           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04406
04407           return HAL_ERROR;
04408         }
04409
04410         /* Increment counter */
04411         Counter++;
04412       }
04413
04414       /* Disable gap control by pin fdcan1_evt */
04415       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
04416
04417       /* Return function status */
04418       return HAL_OK;
04419     }
04420     else
04421     {
04422       /* Update error code.
04423          Feature not supported for TT Level 0 */
04424       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04425
04426       return HAL_ERROR;
04427     }
04428   }
04429   else
04430   {
04431     /* Update error code */
04432     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04433
04434     return HAL_ERROR;
04435   }
04436 }
04437
04438 /**
04439   * @brief  Enable gap control (finish only) by register time mark interrupt.
04440   *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
04441   *         the Gap and start the reference message.
04442   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04443   *         the configuration information for the specified FDCAN.
04444   * @retval HAL status
04445   */
04446 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
04447 {
04448   uint32_t Counter = 0U;
04449   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04450
04451   /* Check function parameters */
04452   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04453
04454   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04455   {
04456     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04457     {
04458       /* Wait until the LCKC bit into TTOCN register is reset */
04459       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04460       {
04461         /* Check for the Timeout */
04462         if (Counter > FDCAN_TIMEOUT_VALUE)
04463         {
04464           /* Update error code */
04465           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04466
04467           /* Change FDCAN state */
04468           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04469
04470           return HAL_ERROR;
04471         }
04472
04473         /* Increment counter */
04474         Counter++;
04475       }
04476
04477       /* Enable gap control by register time mark interrupt */
04478       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
04479
04480       /* Return function status */
04481       return HAL_OK;
04482     }
04483     else
04484     {
04485       /* Update error code.
04486          Feature not supported for TT Level 0 */
04487       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04488
04489       return HAL_ERROR;
04490     }
04491   }
04492   else
04493   {
04494     /* Update error code */
04495     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04496
04497     return HAL_ERROR;
04498   }
04499 }
04500
04501 /**
04502   * @brief  Disable gap control by register time mark interrupt.
04503   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04504   *         the configuration information for the specified FDCAN.
04505   * @retval HAL status
04506   */
04507 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
04508 {
04509   uint32_t Counter = 0U;
04510   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04511
04512   /* Check function parameters */
04513   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04514
04515   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04516   {
04517     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04518     {
04519       /* Wait until the LCKC bit into TTOCN register is reset */
04520       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04521       {
04522         /* Check for the Timeout */
04523         if (Counter > FDCAN_TIMEOUT_VALUE)
04524         {
04525           /* Update error code */
04526           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04527
04528           /* Change FDCAN state */
04529           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04530
04531           return HAL_ERROR;
04532         }
04533
04534         /* Increment counter */
04535         Counter++;
04536       }
04537
04538       /* Disable gap control by register time mark interrupt */
04539       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
04540
04541       /* Return function status */
04542       return HAL_OK;
04543     }
04544     else
04545     {
04546       /* Update error code.
04547          Feature not supported for TT Level 0 */
04548       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04549
04550       return HAL_ERROR;
04551     }
04552   }
04553   else
04554   {
04555     /* Update error code */
04556     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04557
04558     return HAL_ERROR;
04559   }
04560 }
04561
04562 /**
04563   * @brief  Transmit next reference message with Next_is_Gap = "1".
04564   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04565   *         the configuration information for the specified FDCAN.
04566   * @retval HAL status
04567   */
04568 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
04569 {
04570   uint32_t Counter = 0U;
04571   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04572
04573   /* Check function parameters */
04574   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04575
04576   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04577   {
04578     /* Check that the node is configured for external event-synchronized TT operation */
04579     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
04580     {
04581       /* Update error code */
04582       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04583
04584       return HAL_ERROR;
04585     }
04586
04587     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04588     {
04589       /* Wait until the LCKC bit into TTOCN register is reset */
04590       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04591       {
04592         /* Check for the Timeout */
04593         if (Counter > FDCAN_TIMEOUT_VALUE)
04594         {
04595           /* Update error code */
04596           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04597
04598           /* Change FDCAN state */
04599           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04600
04601           return HAL_ERROR;
04602         }
04603
04604         /* Increment counter */
04605         Counter++;
04606       }
04607
04608       /* Set Next is Gap */
04609       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
04610
04611       /* Return function status */
04612       return HAL_OK;
04613     }
04614     else
04615     {
04616       /* Update error code.
04617          Feature not supported for TT Level 0 */
04618       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04619
04620       return HAL_ERROR;
04621     }
04622   }
04623   else
04624   {
04625     /* Update error code */
04626     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04627
04628     return HAL_ERROR;
04629   }
04630 }
04631
04632 /**
04633   * @brief  Finish a Gap by requesting start of reference message.
04634   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04635   *         the configuration information for the specified FDCAN.
04636   * @retval HAL status
04637   */
04638 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
04639 {
04640   uint32_t Counter = 0U;
04641   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04642
04643   /* Check function parameters */
04644   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04645
04646   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04647   {
04648     /* Check that the node is configured for external event-synchronized TT operation */
04649     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
04650     {
04651       /* Update error code */
04652       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04653
04654       return HAL_ERROR;
04655     }
04656
04657     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
04658     {
04659       /* Wait until the LCKC bit into TTOCN register is reset */
04660       while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04661       {
04662         /* Check for the Timeout */
04663         if (Counter > FDCAN_TIMEOUT_VALUE)
04664         {
04665           /* Update error code */
04666           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04667
04668           /* Change FDCAN state */
04669           hfdcan->State = HAL_FDCAN_STATE_ERROR;
04670
04671           return HAL_ERROR;
04672         }
04673
04674         /* Increment counter */
04675         Counter++;
04676       }
04677
04678       /* Set Finish Gap */
04679       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
04680
04681       /* Return function status */
04682       return HAL_OK;
04683     }
04684     else
04685     {
04686       /* Update error code.
04687          Feature not supported for TT Level 0 */
04688       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
04689
04690       return HAL_ERROR;
04691     }
04692   }
04693   else
04694   {
04695     /* Update error code */
04696     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04697
04698     return HAL_ERROR;
04699   }
04700 }
04701
04702 /**
04703   * @brief  Configure target phase used for external synchronization by event
04704   *         trigger input pin fdcan1_evt.
04705   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04706   *         the configuration information for the specified FDCAN.
04707   * @param  TargetPhase defines target value of cycle time when a rising edge
04708   *         of fdcan1_evt is expected.
04709   *         This parameter must be a number between 0 and 0xFFFF.
04710   * @retval HAL status
04711   */
04712 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
04713 {
04714   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04715
04716   /* Check function parameters */
04717   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04718   assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
04719
04720   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04721   {
04722     /* Check that no external schedule synchronization is pending */
04723     if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
04724     {
04725       /* Update error code */
04726       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
04727
04728       return HAL_ERROR;
04729     }
04730
04731     /* Configure cycle time target phase */
04732     MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
04733
04734     /* Return function status */
04735     return HAL_OK;
04736   }
04737   else
04738   {
04739     /* Update error code */
04740     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04741
04742     return HAL_ERROR;
04743   }
04744 }
04745
04746 /**
04747   * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
04748   *         using event trigger input pin fdcan1_evt.
04749   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04750   *         the configuration information for the specified FDCAN.
04751   * @retval HAL status
04752   */
04753 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
04754 {
04755   uint32_t Counter = 0U;
04756   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04757
04758   /* Check function parameters */
04759   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04760
04761   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04762   {
04763     /* Wait until the LCKC bit into TTOCN register is reset */
04764     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04765     {
04766       /* Check for the Timeout */
04767       if (Counter > FDCAN_TIMEOUT_VALUE)
04768       {
04769         /* Update error code */
04770         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04771
04772         /* Change FDCAN state */
04773         hfdcan->State = HAL_FDCAN_STATE_ERROR;
04774
04775         return HAL_ERROR;
04776       }
04777
04778       /* Increment counter */
04779       Counter++;
04780     }
04781
04782     /* Enable external synchronization */
04783     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
04784
04785     /* Return function status */
04786     return HAL_OK;
04787   }
04788   else
04789   {
04790     /* Update error code */
04791     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04792
04793     return HAL_ERROR;
04794   }
04795 }
04796
04797 /**
04798   * @brief  Disable external schedule synchronization.
04799   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04800   *         the configuration information for the specified FDCAN.
04801   * @retval HAL status
04802   */
04803 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
04804 {
04805   uint32_t Counter = 0U;
04806   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04807
04808   /* Check function parameters */
04809   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04810
04811   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04812   {
04813     /* Wait until the LCKC bit into TTOCN register is reset */
04814     while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
04815     {
04816       /* Check for the Timeout */
04817       if (Counter > FDCAN_TIMEOUT_VALUE)
04818       {
04819         /* Update error code */
04820         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
04821
04822         /* Change FDCAN state */
04823         hfdcan->State = HAL_FDCAN_STATE_ERROR;
04824
04825         return HAL_ERROR;
04826       }
04827
04828       /* Increment counter */
04829       Counter++;
04830     }
04831
04832     /* Disable external synchronization */
04833     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
04834
04835     /* Return function status */
04836     return HAL_OK;
04837   }
04838   else
04839   {
04840     /* Update error code */
04841     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04842
04843     return HAL_ERROR;
04844   }
04845 }
04846
04847 /**
04848   * @brief  Get TT operation status.
04849   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04850   *         the configuration information for the specified FDCAN.
04851   * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
04852   * @retval HAL status
04853   */
04854 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
04855 {
04856   uint32_t TTStatusReg;
04857
04858   /* Check function parameters */
04859   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04860
04861   /* Read the TT operation status register */
04862   TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
04863
04864   /* Fill the TT operation status structure */
04865   TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
04866   TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
04867   TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
04868   TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
04869   TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
04870   TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
04871   TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
04872   TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
04873   TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
04874   TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
04875   TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
04876   TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
04877   TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
04878   TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
04879
04880   /* Return function status */
04881   return HAL_OK;
04882 }
04883
04884 /**
04885   * @}
04886   */
04887
04888 /** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
04889  *  @brief    Interrupts management
04890  *
04891 @verbatim
04892   ==============================================================================
04893                        ##### Interrupts management #####
04894   ==============================================================================
04895     [..]  This section provides functions allowing to:
04896       (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
04897       (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
04898       (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
04899       (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
04900       (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
04901       (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
04902       (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
04903
04904 @endverbatim
04905   * @{
04906   */
04907
04908 /**
04909   * @brief  Assign interrupts to either Interrupt line 0 or 1.
04910   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04911   *         the configuration information for the specified FDCAN.
04912   * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
04913   *         This parameter can be any combination of @arg FDCAN_Interrupts.
04914   * @param  InterruptLine Interrupt line.
04915   *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
04916   * @retval HAL status
04917   */
04918 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
04919 {
04920   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04921
04922   /* Check function parameters */
04923   assert_param(IS_FDCAN_IT(ITList));
04924   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
04925
04926   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04927   {
04928     /* Assign list of interrupts to the selected line */
04929     if (InterruptLine == FDCAN_INTERRUPT_LINE0)
04930     {
04931       CLEAR_BIT(hfdcan->Instance->ILS, ITList);
04932     }
04933     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
04934     {
04935       SET_BIT(hfdcan->Instance->ILS, ITList);
04936     }
04937
04938     /* Return function status */
04939     return HAL_OK;
04940   }
04941   else
04942   {
04943     /* Update error code */
04944     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04945
04946     return HAL_ERROR;
04947   }
04948 }
04949
04950 /**
04951   * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
04952   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04953   *         the configuration information for the specified FDCAN.
04954   * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
04955   *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
04956   * @param  InterruptLine Interrupt line.
04957   *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
04958   * @retval HAL status
04959   */
04960 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
04961 {
04962   HAL_FDCAN_StateTypeDef state = hfdcan->State;
04963
04964   /* Check function parameters */
04965   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
04966   assert_param(IS_FDCAN_TT_IT(TTITList));
04967   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
04968
04969   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
04970   {
04971     /* Assign list of interrupts to the selected line */
04972     if (InterruptLine == FDCAN_INTERRUPT_LINE0)
04973     {
04974       CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
04975     }
04976     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
04977     {
04978       SET_BIT(hfdcan->ttcan->TTILS, TTITList);
04979     }
04980
04981     /* Return function status */
04982     return HAL_OK;
04983   }
04984   else
04985   {
04986     /* Update error code */
04987     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
04988
04989     return HAL_ERROR;
04990   }
04991 }
04992
04993 /**
04994   * @brief  Enable interrupts.
04995   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
04996   *         the configuration information for the specified FDCAN.
04997   * @param  ActiveITs indicates which interrupts will be enabled.
04998   *         This parameter can be any combination of @arg FDCAN_Interrupts.
04999   * @param  BufferIndexes Tx Buffer Indexes.
05000   *         This parameter can be any combination of @arg FDCAN_Tx_location.
05001   *         This parameter is ignored if ActiveITs does not include one of the following:
05002   *           - FDCAN_IT_TX_COMPLETE
05003   *           - FDCAN_IT_TX_ABORT_COMPLETE
05004   * @retval HAL status
05005   */
05006 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
05007 {
05008   HAL_FDCAN_StateTypeDef state = hfdcan->State;
05009
05010   /* Check function parameters */
05011   assert_param(IS_FDCAN_IT(ActiveITs));
05012
05013   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
05014   {
05015     /* Enable Interrupt lines */
05016     if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
05017     {
05018       /* Enable Interrupt line 0 */
05019       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
05020     }
05021     else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
05022     {
05023       /* Enable Interrupt line 1 */
05024       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
05025     }
05026     else
05027     {
05028       /* Enable Interrupt lines 0 and 1 */
05029       hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
05030     }
05031
05032     if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
05033     {
05034       /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
05035          but interrupt will only occure if TC is enabled in IE register */
05036       SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
05037     }
05038
05039     if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
05040     {
05041       /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
05042          but interrupt will only occure if TCF is enabled in IE register */
05043       SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
05044     }
05045
05046     /* Enable the selected interrupts */
05047     __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
05048
05049     /* Return function status */
05050     return HAL_OK;
05051   }
05052   else
05053   {
05054     /* Update error code */
05055     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
05056
05057     return HAL_ERROR;
05058   }
05059 }
05060
05061 /**
05062   * @brief  Disable interrupts.
05063   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05064   *         the configuration information for the specified FDCAN.
05065   * @param  InactiveITs indicates which interrupts will be disabled.
05066   *         This parameter can be any combination of @arg FDCAN_Interrupts.
05067   * @retval HAL status
05068   */
05069 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
05070 {
05071   uint32_t ITLineSelection;
05072   HAL_FDCAN_StateTypeDef state = hfdcan->State;
05073
05074   /* Check function parameters */
05075   assert_param(IS_FDCAN_IT(InactiveITs));
05076
05077   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
05078   {
05079     /* Disable the selected interrupts */
05080     __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
05081
05082     if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
05083     {
05084       /* Disable Tx Buffer Transmission Interrupts */
05085       CLEAR_REG(hfdcan->Instance->TXBTIE);
05086     }
05087
05088     if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
05089     {
05090       /* Disable Tx Buffer Cancellation Finished Interrupt */
05091       CLEAR_REG(hfdcan->Instance->TXBCIE);
05092     }
05093
05094     ITLineSelection = hfdcan->Instance->ILS;
05095
05096     if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
05097     {
05098       /* Disable Interrupt line 0 */
05099       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
05100     }
05101
05102     if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
05103     {
05104       /* Disable Interrupt line 1 */
05105       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
05106     }
05107
05108     /* Return function status */
05109     return HAL_OK;
05110   }
05111   else
05112   {
05113     /* Update error code */
05114     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
05115
05116     return HAL_ERROR;
05117   }
05118 }
05119
05120 /**
05121   * @brief  Enable TT interrupts.
05122   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05123   *         the configuration information for the specified FDCAN.
05124   * @param  ActiveTTITs indicates which TT interrupts will be enabled.
05125   *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
05126   * @retval HAL status
05127   */
05128 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
05129 {
05130   HAL_FDCAN_StateTypeDef state = hfdcan->State;
05131
05132   /* Check function parameters */
05133   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
05134   assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
05135
05136   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
05137   {
05138     /* Enable Interrupt lines */
05139     if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
05140     {
05141       /* Enable Interrupt line 0 */
05142       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
05143     }
05144     else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
05145     {
05146       /* Enable Interrupt line 1 */
05147       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
05148     }
05149     else
05150     {
05151       /* Enable Interrupt lines 0 and 1 */
05152       hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
05153     }
05154
05155     /* Enable the selected TT interrupts */
05156     __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
05157
05158     /* Return function status */
05159     return HAL_OK;
05160   }
05161   else
05162   {
05163     /* Update error code */
05164     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
05165
05166     return HAL_ERROR;
05167   }
05168 }
05169
05170 /**
05171   * @brief  Disable TT interrupts.
05172   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05173   *         the configuration information for the specified FDCAN.
05174   * @param  InactiveTTITs indicates which TT interrupts will be disabled.
05175   *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
05176   * @retval HAL status
05177   */
05178 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
05179 {
05180   uint32_t ITLineSelection;
05181   HAL_FDCAN_StateTypeDef state = hfdcan->State;
05182
05183   /* Check function parameters */
05184   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
05185   assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
05186
05187   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
05188   {
05189     /* Disable the selected TT interrupts */
05190     __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
05191
05192     ITLineSelection = hfdcan->ttcan->TTILS;
05193
05194     if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
05195     {
05196       /* Disable Interrupt line 0 */
05197       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
05198     }
05199
05200     if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
05201     {
05202       /* Disable Interrupt line 1 */
05203       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
05204     }
05205
05206     /* Return function status */
05207     return HAL_OK;
05208   }
05209   else
05210   {
05211     /* Update error code */
05212     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
05213
05214     return HAL_ERROR;
05215   }
05216 }
05217
05218 /**
05219   * @brief  Handles FDCAN interrupt request.
05220   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05221   *         the configuration information for the specified FDCAN.
05222   * @retval HAL status
05223   */
05224 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
05225 {
05226   uint32_t ClkCalibrationITs;
05227   uint32_t TxEventFifoITs;
05228   uint32_t RxFifo0ITs;
05229   uint32_t RxFifo1ITs;
05230   uint32_t Errors;
05231   uint32_t ErrorStatusITs;
05232   uint32_t TransmittedBuffers;
05233   uint32_t AbortedBuffers;
05234   uint32_t TTSchedSyncITs;
05235   uint32_t TTTimeMarkITs;
05236   uint32_t TTGlobTimeITs;
05237   uint32_t TTDistErrors;
05238   uint32_t TTFatalErrors;
05239   uint32_t SWTime;
05240   uint32_t SWCycleCount;
05241
05242   ClkCalibrationITs = (FDCAN_CCU->IR << 30);
05243   ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
05244   TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
05245   TxEventFifoITs &= hfdcan->Instance->IE;
05246   RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
05247   RxFifo0ITs &= hfdcan->Instance->IE;
05248   RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
05249   RxFifo1ITs &= hfdcan->Instance->IE;
05250   Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
05251   Errors &= hfdcan->Instance->IE;
05252   ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
05253   ErrorStatusITs &= hfdcan->Instance->IE;
05254
05255   /* High Priority Message interrupt management *******************************/
05256   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
05257   {
05258     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
05259     {
05260       /* Clear the High Priority Message flag */
05261       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
05262
05263 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05264       /* Call registered callback*/
05265       hfdcan->HighPriorityMessageCallback(hfdcan);
05266 #else
05267       /* High Priority Message Callback */
05268       HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
05269 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05270     }
05271   }
05272
05273   /* Transmission Abort interrupt management **********************************/
05274   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
05275   {
05276     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
05277     {
05278       /* List of aborted monitored buffers */
05279       AbortedBuffers = hfdcan->Instance->TXBCF;
05280       AbortedBuffers &= hfdcan->Instance->TXBCIE;
05281
05282       /* Clear the Transmission Cancellation flag */
05283       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
05284
05285 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05286       /* Call registered callback*/
05287       hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
05288 #else
05289       /* Transmission Cancellation Callback */
05290       HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
05291 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05292     }
05293   }
05294
05295   /* Clock calibration unit interrupts management *****************************/
05296   if (ClkCalibrationITs != 0U)
05297   {
05298     /* Clear the Clock Calibration flags */
05299     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
05300
05301 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05302     /* Call registered callback*/
05303     hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
05304 #else
05305     /* Clock Calibration Callback */
05306     HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
05307 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05308   }
05309
05310   /* Tx event FIFO interrupts management **************************************/
05311   if (TxEventFifoITs != 0U)
05312   {
05313     /* Clear the Tx Event FIFO flags */
05314     __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
05315
05316 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05317     /* Call registered callback*/
05318     hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
05319 #else
05320     /* Tx Event FIFO Callback */
05321     HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
05322 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05323   }
05324
05325   /* Rx FIFO 0 interrupts management ******************************************/
05326   if (RxFifo0ITs != 0U)
05327   {
05328     /* Clear the Rx FIFO 0 flags */
05329     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
05330
05331 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05332     /* Call registered callback*/
05333     hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
05334 #else
05335     /* Rx FIFO 0 Callback */
05336     HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
05337 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05338   }
05339
05340   /* Rx FIFO 1 interrupts management ******************************************/
05341   if (RxFifo1ITs != 0U)
05342   {
05343     /* Clear the Rx FIFO 1 flags */
05344     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
05345
05346 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05347     /* Call registered callback*/
05348     hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
05349 #else
05350     /* Rx FIFO 1 Callback */
05351     HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
05352 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05353   }
05354
05355   /* Tx FIFO empty interrupt management ***************************************/
05356   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
05357   {
05358     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
05359     {
05360       /* Clear the Tx FIFO empty flag */
05361       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
05362
05363 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05364       /* Call registered callback*/
05365       hfdcan->TxFifoEmptyCallback(hfdcan);
05366 #else
05367       /* Tx FIFO empty Callback */
05368       HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
05369 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05370     }
05371   }
05372
05373   /* Transmission Complete interrupt management *******************************/
05374   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
05375   {
05376     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
05377     {
05378       /* List of transmitted monitored buffers */
05379       TransmittedBuffers = hfdcan->Instance->TXBTO;
05380       TransmittedBuffers &= hfdcan->Instance->TXBTIE;
05381
05382       /* Clear the Transmission Complete flag */
05383       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
05384
05385 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05386       /* Call registered callback*/
05387       hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
05388 #else
05389       /* Transmission Complete Callback */
05390       HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
05391 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05392     }
05393   }
05394
05395   /* Rx Buffer New Message interrupt management *******************************/
05396   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
05397   {
05398     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
05399     {
05400       /* Clear the Rx Buffer New Message flag */
05401       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
05402
05403 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05404       /* Call registered callback*/
05405       hfdcan->RxBufferNewMessageCallback(hfdcan);
05406 #else
05407       /* Rx Buffer New Message Callback */
05408       HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
05409 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05410     }
05411   }
05412
05413   /* Timestamp Wraparound interrupt management ********************************/
05414   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
05415   {
05416     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
05417     {
05418       /* Clear the Timestamp Wraparound flag */
05419       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
05420
05421 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05422       /* Call registered callback*/
05423       hfdcan->TimestampWraparoundCallback(hfdcan);
05424 #else
05425       /* Timestamp Wraparound Callback */
05426       HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
05427 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05428     }
05429   }
05430
05431   /* Timeout Occurred interrupt management ************************************/
05432   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
05433   {
05434     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
05435     {
05436       /* Clear the Timeout Occurred flag */
05437       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
05438
05439 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05440       /* Call registered callback*/
05441       hfdcan->TimeoutOccurredCallback(hfdcan);
05442 #else
05443       /* Timeout Occurred Callback */
05444       HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
05445 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05446     }
05447   }
05448
05449   /* Message RAM access failure interrupt management **************************/
05450   if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
05451   {
05452     if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
05453     {
05454       /* Clear the Message RAM access failure flag */
05455       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
05456
05457       /* Update error code */
05458       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
05459     }
05460   }
05461
05462   /* Error Status interrupts management ***************************************/
05463   if (ErrorStatusITs != 0U)
05464   {
05465     /* Clear the Error flags */
05466     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
05467
05468 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05469     /* Call registered callback*/
05470     hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
05471 #else
05472     /* Error Status Callback */
05473     HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
05474 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05475   }
05476
05477   /* Error interrupts management **********************************************/
05478   if (Errors != 0U)
05479   {
05480     /* Clear the Error flags */
05481     __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
05482
05483     /* Update error code */
05484     hfdcan->ErrorCode |= Errors;
05485   }
05486
05487   if (hfdcan->Instance == FDCAN1)
05488   {
05489     if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
05490     {
05491       TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
05492       TTSchedSyncITs &= hfdcan->ttcan->TTIE;
05493       TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
05494       TTTimeMarkITs &= hfdcan->ttcan->TTIE;
05495       TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
05496       TTGlobTimeITs &= hfdcan->ttcan->TTIE;
05497       TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
05498       TTDistErrors &= hfdcan->ttcan->TTIE;
05499       TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
05500       TTFatalErrors &= hfdcan->ttcan->TTIE;
05501
05502       /* TT Schedule Synchronization interrupts management **********************/
05503       if (TTSchedSyncITs != 0U)
05504       {
05505         /* Clear the TT Schedule Synchronization flags */
05506         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
05507
05508 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05509         /* Call registered callback*/
05510         hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
05511 #else
05512         /* TT Schedule Synchronization Callback */
05513         HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
05514 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05515       }
05516
05517       /* TT Time Mark interrupts management *************************************/
05518       if (TTTimeMarkITs != 0U)
05519       {
05520         /* Clear the TT Time Mark flags */
05521         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
05522
05523 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05524         /* Call registered callback*/
05525         hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
05526 #else
05527         /* TT Time Mark Callback */
05528         HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
05529 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05530       }
05531
05532       /* TT Stop Watch interrupt management *************************************/
05533       if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
05534       {
05535         if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
05536         {
05537           /* Retrieve Stop watch Time and Cycle count */
05538           SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
05539           SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
05540
05541           /* Clear the TT Stop Watch flag */
05542           __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
05543
05544 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05545           /* Call registered callback*/
05546           hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
05547 #else
05548           /* TT Stop Watch Callback */
05549           HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
05550 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05551         }
05552       }
05553
05554       /* TT Global Time interrupts management ***********************************/
05555       if (TTGlobTimeITs != 0U)
05556       {
05557         /* Clear the TT Global Time flags */
05558         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
05559
05560 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05561         /* Call registered callback*/
05562         hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
05563 #else
05564         /* TT Global Time Callback */
05565         HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
05566 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05567       }
05568
05569       /* TT Disturbing Error interrupts management ******************************/
05570       if (TTDistErrors != 0U)
05571       {
05572         /* Clear the TT Disturbing Error flags */
05573         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
05574
05575         /* Update error code */
05576         hfdcan->ErrorCode |= TTDistErrors;
05577       }
05578
05579       /* TT Fatal Error interrupts management ***********************************/
05580       if (TTFatalErrors != 0U)
05581       {
05582         /* Clear the TT Fatal Error flags */
05583         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
05584
05585         /* Update error code */
05586         hfdcan->ErrorCode |= TTFatalErrors;
05587       }
05588     }
05589   }
05590
05591   if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
05592   {
05593 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
05594     /* Call registered callback*/
05595     hfdcan->ErrorCallback(hfdcan);
05596 #else
05597     /* Error Callback */
05598     HAL_FDCAN_ErrorCallback(hfdcan);
05599 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
05600   }
05601 }
05602
05603 /**
05604   * @}
05605   */
05606
05607 /** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
05608  *  @brief   FDCAN Callback functions
05609  *
05610 @verbatim
05611   ==============================================================================
05612                           ##### Callback functions #####
05613   ==============================================================================
05614     [..]
05615     This subsection provides the following callback functions:
05616       (+) HAL_FDCAN_ClockCalibrationCallback
05617       (+) HAL_FDCAN_TxEventFifoCallback
05618       (+) HAL_FDCAN_RxFifo0Callback
05619       (+) HAL_FDCAN_RxFifo1Callback
05620       (+) HAL_FDCAN_TxFifoEmptyCallback
05621       (+) HAL_FDCAN_TxBufferCompleteCallback
05622       (+) HAL_FDCAN_TxBufferAbortCallback
05623       (+) HAL_FDCAN_RxBufferNewMessageCallback
05624       (+) HAL_FDCAN_HighPriorityMessageCallback
05625       (+) HAL_FDCAN_TimestampWraparoundCallback
05626       (+) HAL_FDCAN_TimeoutOccurredCallback
05627       (+) HAL_FDCAN_ErrorCallback
05628       (+) HAL_FDCAN_ErrorStatusCallback
05629       (+) HAL_FDCAN_TT_ScheduleSyncCallback
05630       (+) HAL_FDCAN_TT_TimeMarkCallback
05631       (+) HAL_FDCAN_TT_StopWatchCallback
05632       (+) HAL_FDCAN_TT_GlobalTimeCallback
05633
05634 @endverbatim
05635   * @{
05636   */
05637
05638 /**
05639   * @brief  Clock Calibration callback.
05640   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05641   *         the configuration information for the specified FDCAN.
05642   * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
05643   *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
05644   * @retval None
05645   */
05646 __weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
05647 {
05648   /* Prevent unused argument(s) compilation warning */
05649   UNUSED(hfdcan);
05650   UNUSED(ClkCalibrationITs);
05651
05652   /* NOTE : This function Should not be modified, when the callback is needed,
05653             the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
05654    */
05655 }
05656
05657 /**
05658   * @brief  Tx Event callback.
05659   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05660   *         the configuration information for the specified FDCAN.
05661   * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
05662   *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
05663   * @retval None
05664   */
05665 __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
05666 {
05667   /* Prevent unused argument(s) compilation warning */
05668   UNUSED(hfdcan);
05669   UNUSED(TxEventFifoITs);
05670
05671   /* NOTE : This function Should not be modified, when the callback is needed,
05672             the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
05673    */
05674 }
05675
05676 /**
05677   * @brief  Rx FIFO 0 callback.
05678   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05679   *         the configuration information for the specified FDCAN.
05680   * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
05681   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
05682   * @retval None
05683   */
05684 __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
05685 {
05686   /* Prevent unused argument(s) compilation warning */
05687   UNUSED(hfdcan);
05688   UNUSED(RxFifo0ITs);
05689
05690   /* NOTE : This function Should not be modified, when the callback is needed,
05691             the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
05692    */
05693 }
05694
05695 /**
05696   * @brief  Rx FIFO 1 callback.
05697   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05698   *         the configuration information for the specified FDCAN.
05699   * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
05700   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
05701   * @retval None
05702   */
05703 __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
05704 {
05705   /* Prevent unused argument(s) compilation warning */
05706   UNUSED(hfdcan);
05707   UNUSED(RxFifo1ITs);
05708
05709   /* NOTE : This function Should not be modified, when the callback is needed,
05710             the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
05711    */
05712 }
05713
05714 /**
05715   * @brief  Tx FIFO Empty callback.
05716   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05717   *         the configuration information for the specified FDCAN.
05718   * @retval None
05719   */
05720 __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
05721 {
05722   /* Prevent unused argument(s) compilation warning */
05723   UNUSED(hfdcan);
05724
05725   /* NOTE : This function Should not be modified, when the callback is needed,
05726             the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
05727    */
05728 }
05729
05730 /**
05731   * @brief  Transmission Complete callback.
05732   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05733   *         the configuration information for the specified FDCAN.
05734   * @param  BufferIndexes Indexes of the transmitted buffers.
05735   *         This parameter can be any combination of @arg FDCAN_Tx_location.
05736   * @retval None
05737   */
05738 __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
05739 {
05740   /* Prevent unused argument(s) compilation warning */
05741   UNUSED(hfdcan);
05742   UNUSED(BufferIndexes);
05743
05744   /* NOTE : This function Should not be modified, when the callback is needed,
05745             the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
05746    */
05747 }
05748
05749 /**
05750   * @brief  Transmission Cancellation callback.
05751   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05752   *         the configuration information for the specified FDCAN.
05753   * @param  BufferIndexes Indexes of the aborted buffers.
05754   *         This parameter can be any combination of @arg FDCAN_Tx_location.
05755   * @retval None
05756   */
05757 __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
05758 {
05759   /* Prevent unused argument(s) compilation warning */
05760   UNUSED(hfdcan);
05761   UNUSED(BufferIndexes);
05762
05763   /* NOTE : This function Should not be modified, when the callback is needed,
05764             the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
05765    */
05766 }
05767
05768 /**
05769   * @brief  Rx Buffer New Message callback.
05770   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05771   *         the configuration information for the specified FDCAN.
05772   * @retval None
05773   */
05774 __weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
05775 {
05776   /* Prevent unused argument(s) compilation warning */
05777   UNUSED(hfdcan);
05778
05779   /* NOTE : This function Should not be modified, when the callback is needed,
05780             the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
05781    */
05782 }
05783
05784 /**
05785   * @brief  Timestamp Wraparound callback.
05786   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05787   *         the configuration information for the specified FDCAN.
05788   * @retval None
05789   */
05790 __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
05791 {
05792   /* Prevent unused argument(s) compilation warning */
05793   UNUSED(hfdcan);
05794
05795   /* NOTE : This function Should not be modified, when the callback is needed,
05796             the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
05797    */
05798 }
05799
05800 /**
05801   * @brief  Timeout Occurred callback.
05802   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05803   *         the configuration information for the specified FDCAN.
05804   * @retval None
05805   */
05806 __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
05807 {
05808   /* Prevent unused argument(s) compilation warning */
05809   UNUSED(hfdcan);
05810
05811   /* NOTE : This function Should not be modified, when the callback is needed,
05812             the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
05813    */
05814 }
05815
05816 /**
05817   * @brief  High Priority Message callback.
05818   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05819   *         the configuration information for the specified FDCAN.
05820   * @retval None
05821   */
05822 __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
05823 {
05824   /* Prevent unused argument(s) compilation warning */
05825   UNUSED(hfdcan);
05826
05827   /* NOTE : This function Should not be modified, when the callback is needed,
05828             the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
05829    */
05830 }
05831
05832 /**
05833   * @brief  Error callback.
05834   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05835   *         the configuration information for the specified FDCAN.
05836   * @retval None
05837   */
05838 __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
05839 {
05840   /* Prevent unused argument(s) compilation warning */
05841   UNUSED(hfdcan);
05842
05843   /* NOTE : This function Should not be modified, when the callback is needed,
05844             the HAL_FDCAN_ErrorCallback could be implemented in the user file
05845    */
05846 }
05847
05848 /**
05849   * @brief  Error status callback.
05850   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05851   *         the configuration information for the specified FDCAN.
05852   * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
05853   *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
05854   * @retval None
05855   */
05856 __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
05857 {
05858   /* Prevent unused argument(s) compilation warning */
05859   UNUSED(hfdcan);
05860   UNUSED(ErrorStatusITs);
05861
05862   /* NOTE : This function Should not be modified, when the callback is needed,
05863             the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
05864    */
05865 }
05866
05867 /**
05868   * @brief  TT Schedule Synchronization callback.
05869   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05870   *         the configuration information for the specified FDCAN.
05871   * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
05872   *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
05873   * @retval None
05874   */
05875 __weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
05876 {
05877   /* Prevent unused argument(s) compilation warning */
05878   UNUSED(hfdcan);
05879   UNUSED(TTSchedSyncITs);
05880
05881   /* NOTE : This function Should not be modified, when the callback is needed,
05882             the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
05883    */
05884 }
05885
05886 /**
05887   * @brief  TT Time Mark callback.
05888   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05889   *         the configuration information for the specified FDCAN.
05890   * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
05891   *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
05892   * @retval None
05893   */
05894 __weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
05895 {
05896   /* Prevent unused argument(s) compilation warning */
05897   UNUSED(hfdcan);
05898   UNUSED(TTTimeMarkITs);
05899
05900   /* NOTE : This function Should not be modified, when the callback is needed,
05901             the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
05902    */
05903 }
05904
05905 /**
05906   * @brief  TT Stop Watch callback.
05907   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05908   *         the configuration information for the specified FDCAN.
05909   * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
05910   *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
05911   *         This parameter is a number between 0 and 0xFFFF.
05912   * @param  SWCycleCount Cycle count value captured together with SWTime.
05913   *         This parameter is a number between 0 and 0x3F.
05914   * @retval None
05915   */
05916 __weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
05917 {
05918   /* Prevent unused argument(s) compilation warning */
05919   UNUSED(hfdcan);
05920   UNUSED(SWTime);
05921   UNUSED(SWCycleCount);
05922
05923   /* NOTE : This function Should not be modified, when the callback is needed,
05924             the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
05925    */
05926 }
05927
05928 /**
05929   * @brief  TT Global Time callback.
05930   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05931   *         the configuration information for the specified FDCAN.
05932   * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
05933   *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
05934   * @retval None
05935   */
05936 __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
05937 {
05938   /* Prevent unused argument(s) compilation warning */
05939   UNUSED(hfdcan);
05940   UNUSED(TTGlobTimeITs);
05941
05942   /* NOTE : This function Should not be modified, when the callback is needed,
05943             the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
05944    */
05945 }
05946
05947 /**
05948   * @}
05949   */
05950
05951 /** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
05952  *  @brief   FDCAN Peripheral State functions
05953  *
05954 @verbatim
05955   ==============================================================================
05956                       ##### Peripheral State functions #####
05957   ==============================================================================
05958     [..]
05959     This subsection provides functions allowing to :
05960       (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
05961       (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
05962
05963 @endverbatim
05964   * @{
05965   */
05966 /**
05967   * @brief  Return the FDCAN state
05968   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05969   *         the configuration information for the specified FDCAN.
05970   * @retval HAL state
05971   */
05972 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
05973 {
05974   /* Return FDCAN state */
05975   return hfdcan->State;
05976 }
05977
05978 /**
05979   * @brief  Return the FDCAN error code
05980   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
05981   *         the configuration information for the specified FDCAN.
05982   * @retval FDCAN Error Code
05983   */
05984 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
05985 {
05986   /* Return FDCAN error code */
05987   return hfdcan->ErrorCode;
05988 }
05989
05990 /**
05991   * @}
05992   */
05993
05994 /**
05995   * @}
05996   */
05997
05998 /** @addtogroup FDCAN_Private_Functions
05999   * @{
06000   */
06001
06002 /**
06003   * @brief  Calculate each RAM block start address and size
06004   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
06005   *         the configuration information for the specified FDCAN.
06006   * @retval HAL status
06007  */
06008 static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
06009 {
06010   uint32_t RAMcounter;
06011   uint32_t StartAddress;
06012
06013   StartAddress = hfdcan->Init.MessageRAMOffset;
06014
06015   /* Standard filter list start address */
06016   MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
06017
06018   /* Standard filter elements number */
06019   MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
06020
06021   /* Extended filter list start address */
06022   StartAddress += hfdcan->Init.StdFiltersNbr;
06023   MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
06024
06025   /* Extended filter elements number */
06026   MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
06027
06028   /* Rx FIFO 0 start address */
06029   StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
06030   MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
06031
06032   /* Rx FIFO 0 elements number */
06033   MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
06034
06035   /* Rx FIFO 1 start address */
06036   StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
06037   MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
06038
06039   /* Rx FIFO 1 elements number */
06040   MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
06041
06042   /* Rx buffer list start address */
06043   StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
06044   MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
06045
06046   /* Tx event FIFO start address */
06047   StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
06048   MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
06049
06050   /* Tx event FIFO elements number */
06051   MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
06052
06053   /* Tx buffer list start address */
06054   StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
06055   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
06056
06057   /* Dedicated Tx buffers number */
06058   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
06059
06060   /* Tx FIFO/queue elements number */
06061   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
06062
06063   hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
06064   hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
06065   hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
06066   hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
06067   hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
06068   hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
06069   hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
06070   hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
06071
06072   hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
06073
06074   if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
06075   {
06076     /* Update error code.
06077        Message RAM overflow */
06078     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
06079
06080     /* Change FDCAN state */
06081     hfdcan->State = HAL_FDCAN_STATE_ERROR;
06082
06083     return HAL_ERROR;
06084   }
06085   else
06086   {
06087     /* Flush the allocated Message RAM area */
06088     for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
06089     {
06090       *(uint32_t *)(RAMcounter) = 0x00000000;
06091     }
06092   }
06093
06094   /* Return function status */
06095   return HAL_OK;
06096 }
06097
06098 /**
06099   * @brief  Copy Tx message to the message RAM.
06100   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
06101   *         the configuration information for the specified FDCAN.
06102   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
06103   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
06104   * @param  BufferIndex index of the buffer to be configured.
06105   * @retval HAL status
06106  */
06107 static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
06108 {
06109   uint32_t TxElementW1;
06110   uint32_t TxElementW2;
06111   uint32_t *TxAddress;
06112   uint32_t ByteCounter;
06113
06114   /* Build first word of Tx header element */
06115   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
06116   {
06117     TxElementW1 = (pTxHeader->ErrorStateIndicator |
06118                    FDCAN_STANDARD_ID |
06119                    pTxHeader->TxFrameType |
06120                    (pTxHeader->Identifier << 18));
06121   }
06122   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
06123   {
06124     TxElementW1 = (pTxHeader->ErrorStateIndicator |
06125                    FDCAN_EXTENDED_ID |
06126                    pTxHeader->TxFrameType |
06127                    pTxHeader->Identifier);
06128   }
06129
06130   /* Build second word of Tx header element */
06131   TxElementW2 = ((pTxHeader->MessageMarker << 24) |
06132                  pTxHeader->TxEventFifoControl |
06133                  pTxHeader->FDFormat |
06134                  pTxHeader->BitRateSwitch |
06135                  pTxHeader->DataLength);
06136
06137   /* Calculate Tx element address */
06138   TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
06139
06140   /* Write Tx element header to the message RAM */
06141   *TxAddress = TxElementW1;
06142   TxAddress++;
06143   *TxAddress = TxElementW2;
06144   TxAddress++;
06145
06146   /* Write Tx payload to the message RAM */
06147   for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
06148   {
06149     *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
06150                   ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
06151                   ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
06152                   (uint32_t)pTxData[ByteCounter]);
06153     TxAddress++;
06154   }
06155 }
06156
06157 /**
06158   * @}
06159   */
06160 #endif /* HAL_FDCAN_MODULE_ENABLED */
06161 /**
06162   * @}
06163   */
06164
06165 /**
06166   * @}
06167   */
06168
06169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_fdcan.h Source File

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stm32h7xx_hal_fdcan.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_fdcan.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FDCAN HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_FDCAN_H
00022 #define STM32H7xx_HAL_FDCAN_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FDCAN
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief HAL State structures definition
00046   */
00047 typedef enum
00048 {
00049   HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
00050   HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
00051   HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
00052   HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
00053 } HAL_FDCAN_StateTypeDef;
00054
00055 /**
00056   * @brief FDCAN Init structure definition
00057   */
00058 typedef struct
00059 {
00060   uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
00061                                               This parameter can be a value of @ref FDCAN_frame_format     */
00062
00063   uint32_t Mode;                         /*!< Specifies the FDCAN mode.
00064                                               This parameter can be a value of @ref FDCAN_operating_mode   */
00065
00066   FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
00067                                               This parameter can be set to ENABLE or DISABLE               */
00068
00069   FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
00070                                               This parameter can be set to ENABLE or DISABLE               */
00071
00072   FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
00073                                               This parameter can be set to ENABLE or DISABLE               */
00074
00075   uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
00076                                               divided for generating the nominal bit time quanta.
00077                                               This parameter must be a number between 1 and 512            */
00078
00079   uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
00080                                               hardware is allowed to lengthen or shorten a bit to perform
00081                                               resynchronization.
00082                                               This parameter must be a number between 1 and 128            */
00083
00084   uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
00085                                               This parameter must be a number between 2 and 256            */
00086
00087   uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
00088                                               This parameter must be a number between 2 and 128            */
00089
00090   uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
00091                                               divided for generating the data bit time quanta.
00092                                               This parameter must be a number between 1 and 32             */
00093
00094   uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
00095                                               hardware is allowed to lengthen or shorten a data bit to
00096                                               perform resynchronization.
00097                                               This parameter must be a number between 1 and 16             */
00098
00099   uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
00100                                               This parameter must be a number between 1 and 32             */
00101
00102   uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
00103                                               This parameter must be a number between 1 and 16             */
00104
00105   uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
00106                                               This parameter must be a number between 0 and 2560           */
00107
00108   uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
00109                                               This parameter must be a number between 0 and 128            */
00110
00111   uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
00112                                               This parameter must be a number between 0 and 64             */
00113
00114   uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
00115                                               This parameter must be a number between 0 and 64             */
00116
00117   uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
00118                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00119
00120   uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
00121                                               This parameter must be a number between 0 and 64             */
00122
00123   uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
00124                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00125
00126   uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
00127                                               This parameter must be a number between 0 and 64             */
00128
00129   uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
00130                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00131
00132   uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
00133                                               This parameter must be a number between 0 and 32             */
00134
00135   uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
00136                                               This parameter must be a number between 0 and 32             */
00137
00138   uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
00139                                               This parameter must be a number between 0 and 32             */
00140
00141   uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
00142                                               This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
00143
00144   uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
00145                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00146
00147 } FDCAN_InitTypeDef;
00148
00149 /**
00150   * @brief  FDCAN clock calibration unit structure definition
00151   */
00152 typedef struct
00153 {
00154   uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
00155                                       This parameter can be a value of @ref FDCAN_clock_calibration.       */
00156
00157   uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
00158                                       is bypassed.
00159                                       This parameter can be a value of @ref FDCAN_clock_divider            */
00160
00161   uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
00162                                       actual configured number of periods is MinOscClkPeriods x 32.
00163                                       This parameter must be a number between 0x00 and 0xFF                */
00164
00165   uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
00166                                       This parameter can be a value of @ref FDCAN_calibration_field_length */
00167
00168   uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
00169                                       This parameter must be a number between 4 and 25                     */
00170
00171   uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
00172                                       If set to zero the counter is disabled.
00173                                       This parameter must be a number between 0x0000 and 0xFFFF            */
00174
00175 } FDCAN_ClkCalUnitTypeDef;
00176
00177 /**
00178   * @brief  FDCAN filter structure definition
00179   */
00180 typedef struct
00181 {
00182   uint32_t IdType;           /*!< Specifies the identifier type.
00183                                   This parameter can be a value of @ref FDCAN_id_type       */
00184
00185   uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
00186                                   This parameter must be a number between:
00187                                    - 0 and 127, if IdType is FDCAN_STANDARD_ID
00188                                    - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
00189
00190   uint32_t FilterType;       /*!< Specifies the filter type.
00191                                   This parameter can be a value of @ref FDCAN_filter_type.
00192                                   The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
00193                                   only when IdType is FDCAN_EXTENDED_ID.
00194                                   This parameter is ignored if FilterConfig is set to
00195                                   FDCAN_FILTER_TO_RXBUFFER                                  */
00196
00197   uint32_t FilterConfig;     /*!< Specifies the filter configuration.
00198                                   This parameter can be a value of @ref FDCAN_filter_config */
00199
00200   uint32_t FilterID1;        /*!< Specifies the filter identification 1.
00201                                   This parameter must be a number between:
00202                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00203                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00204
00205   uint32_t FilterID2;        /*!< Specifies the filter identification 2.
00206                                   This parameter is ignored if FilterConfig is set to
00207                                   FDCAN_FILTER_TO_RXBUFFER.
00208                                   This parameter must be a number between:
00209                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00210                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00211
00212   uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
00213                                   matching message will be stored.
00214                                   This parameter must be a number between 0 and 63.
00215                                   This parameter is ignored if FilterConfig is different
00216                                   from FDCAN_FILTER_TO_RXBUFFER                             */
00217
00218   uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
00219                                   calibration messages.
00220                                   This parameter is ignored if FilterConfig is different
00221                                   from FDCAN_FILTER_TO_RXBUFFER.
00222                                   This parameter can be:
00223                                    - 0 : ordinary message
00224                                    - 1 : calibration message                                */
00225
00226 } FDCAN_FilterTypeDef;
00227
00228 /**
00229   * @brief  FDCAN Tx header structure definition
00230   */
00231 typedef struct
00232 {
00233   uint32_t Identifier;          /*!< Specifies the identifier.
00234                                      This parameter must be a number between:
00235                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00236                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00237
00238   uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
00239                                      transmitted.
00240                                      This parameter can be a value of @ref FDCAN_id_type               */
00241
00242   uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
00243                                      This parameter can be a value of @ref FDCAN_frame_type            */
00244
00245   uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
00246                                       This parameter can be a value of @ref FDCAN_data_length_code     */
00247
00248   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00249                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00250
00251   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
00252                                      bit rate switching.
00253                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00254
00255   uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
00256                                      FD format.
00257                                      This parameter can be a value of @ref FDCAN_format                */
00258
00259   uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
00260                                      This parameter can be a value of @ref FDCAN_EFC                   */
00261
00262   uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
00263                                      element for identification of Tx message status.
00264                                      This parameter must be a number between 0 and 0xFF                */
00265
00266 } FDCAN_TxHeaderTypeDef;
00267
00268 /**
00269   * @brief  FDCAN Rx header structure definition
00270   */
00271 typedef struct
00272 {
00273   uint32_t Identifier;            /*!< Specifies the identifier.
00274                                        This parameter must be a number between:
00275                                         - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00276                                         - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00277
00278   uint32_t IdType;                /*!< Specifies the identifier type of the received message.
00279                                        This parameter can be a value of @ref FDCAN_id_type               */
00280
00281   uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
00282                                        This parameter can be a value of @ref FDCAN_frame_type            */
00283
00284   uint32_t DataLength;            /*!< Specifies the received frame length.
00285                                         This parameter can be a value of @ref FDCAN_data_length_code     */
00286
00287   uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
00288                                        This parameter can be a value of @ref FDCAN_error_state_indicator */
00289
00290   uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
00291                                        rate switching.
00292                                        This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00293
00294   uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
00295                                        format.
00296                                        This parameter can be a value of @ref FDCAN_format                */
00297
00298   uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
00299                                        reception.
00300                                        This parameter must be a number between 0 and 0xFFFF              */
00301
00302   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
00303                                        This parameter must be a number between:
00304                                         - 0 and 127, if IdType is FDCAN_STANDARD_ID
00305                                         - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
00306
00307   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
00308                                          Acceptance of non-matching frames may be enabled via
00309                                          HAL_FDCAN_ConfigGlobalFilter().
00310                                          This parameter can be 0 or 1                                    */
00311
00312 } FDCAN_RxHeaderTypeDef;
00313
00314 /**
00315   * @brief  FDCAN Tx event FIFO structure definition
00316   */
00317 typedef struct
00318 {
00319   uint32_t Identifier;          /*!< Specifies the identifier.
00320                                      This parameter must be a number between:
00321                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00322                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00323
00324   uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
00325                                      This parameter can be a value of @ref FDCAN_id_type               */
00326
00327   uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
00328                                      This parameter can be a value of @ref FDCAN_frame_type            */
00329
00330   uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
00331                                      This parameter can be a value of @ref FDCAN_data_length_code      */
00332
00333   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00334                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00335
00336   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
00337                                      rate switching.
00338                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00339
00340   uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
00341                                      format.
00342                                      This parameter can be a value of @ref FDCAN_format                */
00343
00344   uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
00345                                      transmission.
00346                                      This parameter must be a number between 0 and 0xFFFF              */
00347
00348   uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
00349                                      for identification of Tx message status.
00350                                      This parameter must be a number between 0 and 0xFF                */
00351
00352   uint32_t EventType;           /*!< Specifies the event type.
00353                                      This parameter can be a value of @ref FDCAN_event_type            */
00354
00355 } FDCAN_TxEventFifoTypeDef;
00356
00357 /**
00358   * @brief  FDCAN High Priority Message Status structure definition
00359   */
00360 typedef struct
00361 {
00362   uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
00363                                 This parameter can be:
00364                                  - 0 : Standard Filter List
00365                                  - 1 : Extended Filter List                                */
00366
00367   uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
00368                                 This parameter can be a number between:
00369                                 - 0 and 127, if FilterList is 0 (Standard)
00370                                 - 0 and 63, if FilterList is 1 (Extended)                  */
00371
00372   uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
00373                                 This parameter can be a value of @ref FDCAN_hp_msg_storage */
00374
00375   uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
00376                                 message was stored.
00377                                 This parameter is valid only when MessageStorage is:
00378                                   FDCAN_HP_STORAGE_RXFIFO0
00379                                  or
00380                                   FDCAN_HP_STORAGE_RXFIFO1                                 */
00381
00382 } FDCAN_HpMsgStatusTypeDef;
00383
00384 /**
00385   * @brief FDCAN Protocol Status structure definition
00386   */
00387 typedef struct
00388 {
00389   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
00390                                    This parameter can be a value of @ref FDCAN_protocol_error_code                           */
00391
00392   uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
00393                                    frame with its BRS flag set.
00394                                    This parameter can be a value of @ref FDCAN_protocol_error_code                           */
00395
00396   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
00397                                    This parameter can be a value of @ref FDCAN_communication_state                           */
00398
00399   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
00400                                    This parameter can be:
00401                                     - 0 : The FDCAN is in Error_Active state
00402                                     - 1 : The FDCAN is in Error_Passive state                                                */
00403
00404   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
00405                                    This parameter can be:
00406                                     - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
00407                                     - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
00408
00409   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
00410                                    This parameter can be:
00411                                     - 0 : The FDCAN is not in Bus_Off state
00412                                     - 1 : The FDCAN is in Bus_Off state                                                      */
00413
00414   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
00415                                    This parameter can be:
00416                                     - 0 : Last received CAN FD message did not have its ESI flag set
00417                                     - 1 : Last received CAN FD message had its ESI flag set                                  */
00418
00419   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
00420                                    This parameter can be:
00421                                     - 0 : Last received CAN FD message did not have its BRS flag set
00422                                     - 1 : Last received CAN FD message had its BRS flag set                                  */
00423
00424   uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
00425                                    This parameter can be:
00426                                     - 0 : no CAN FD message received
00427                                     - 1 : CAN FD message received                                                            */
00428
00429   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
00430                                    This parameter can be:
00431                                     - 0 : No protocol exception event occurred since last read access
00432                                     - 1 : Protocol exception event occurred                                                  */
00433
00434   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
00435                                    This parameter can be a number between 0 and 127                                          */
00436
00437 } FDCAN_ProtocolStatusTypeDef;
00438
00439 /**
00440   * @brief FDCAN Error Counters structure definition
00441   */
00442 typedef struct
00443 {
00444   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
00445                                 This parameter can be a number between 0 and 255                                         */
00446
00447   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
00448                                 This parameter can be a number between 0 and 127                                         */
00449
00450   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
00451                                 This parameter can be:
00452                                  - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
00453                                  - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
00454
00455   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
00456                                 This parameter can be a number between 0 and 255.
00457                                 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
00458                                 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
00459                                 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
00460
00461 } FDCAN_ErrorCountersTypeDef;
00462
00463 /**
00464   * @brief FDCAN TT Init structure definition
00465   */
00466 typedef struct
00467 {
00468   uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
00469                                    This parameter can be a value of @ref FDCAN_operation_mode               */
00470
00471   uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
00472                                    This parameter can be a value of @ref FDCAN_TT_operation.
00473                                    This parameter is ignored if OperationMode is set to
00474                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00475
00476   uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
00477                                    This parameter can be a value of @ref FDCAN_TT_time_master               */
00478
00479   uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
00480                                    numerator : TUR = (Numerator ± SDL) / Denominator.
00481                                    With : SDL = 2^(SyncDevLimit+5).
00482                                    This parameter must be a number between 0 and 7                          */
00483
00484   uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
00485                                    This parameter must be a number between 0 and 127                        */
00486
00487   uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
00488                                    This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
00489                                    This parameter is ignored if OperationMode is set to
00490                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00491
00492   uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
00493                                    which the application has to serve the application watchdog.
00494                                    The application watchdog is incremented once each 256 NTUs.
00495                                    The application watchdog can be disabled by setting AppWdgLimit to 0.
00496                                    This parameter must be a number between 0 and 255.
00497                                    This parameter is ignored if OperationMode is set to
00498                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00499
00500   uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
00501                                    This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
00502                                    This parameter is ignored if OperationMode is set to
00503                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00504
00505   uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
00506                                    This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
00507                                    This parameter is ignored if OperationMode is set to
00508                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00509
00510   uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
00511                                    This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
00512                                    This parameter is ignored if OperationMode is set to
00513                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00514
00515   uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
00516                                    This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
00517
00518   uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
00519                                    This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
00520
00521   uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
00522                                    This parameter must be a number between 1 and 16                         */
00523
00524   uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
00525                                    This is the sum of Tx_Triggers for exclusive, single arbitrating and
00526                                    merged arbitrating windows.
00527                                    This parameter must be a number between 0 and 4095                       */
00528
00529   uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
00530                                    It is adviced to set this parameter to the largest applicable value.
00531                                    This parameter must be a number between 0x10000 and 0x1FFFF              */
00532
00533   uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
00534                                    This parameter must be a number between 0x0001 and 0x3FFF                */
00535
00536   uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
00537                                    This parameter must be a number between 0 and 64                         */
00538
00539   uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
00540                                    This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
00541
00542   uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
00543                                    This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
00544
00545 } FDCAN_TT_ConfigTypeDef;
00546
00547 /**
00548   * @brief  FDCAN Trigger structure definition
00549   */
00550 typedef struct
00551 {
00552   uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
00553                                This parameter must be a number between 0 and 63                                 */
00554
00555   uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
00556                                This parameter must be a number between 0 and 0xFFFF                             */
00557
00558   uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
00559                                This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
00560
00561   uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
00562                                This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
00563                                This parameter must be a number between 0 and RepeatFactor                       */
00564
00565   uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
00566                                If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
00567                                becomes active.
00568                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
00569
00570   uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
00571                                If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
00572                                trigger memory element becomes active.
00573                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
00574
00575   uint32_t TriggerType;   /*!< Specifies the trigger type.
00576                                This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
00577
00578   uint32_t FilterType;    /*!< Specifies the filter identifier type.
00579                                This parameter can be a value of @ref FDCAN_id_type                              */
00580
00581   uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
00582                                This parameter can be a value of @ref FDCAN_Tx_location.
00583                                This parameter is taken in consideration only if the trigger is configured for
00584                                transmission.                                                                    */
00585
00586   uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
00587                                This parameter is taken in consideration only if the trigger is configured for
00588                                reception.
00589                                This parameter must be a number between:
00590                                 - 0 and 127, if FilterType is FDCAN_STANDARD_ID
00591                                 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
00592
00593 } FDCAN_TriggerTypeDef;
00594
00595 /**
00596   * @brief  FDCAN TT Operation Status structure definition
00597   */
00598 typedef struct
00599 {
00600   uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
00601                                   This parameter can be a value of @ref FDCAN_TT_error_level                    */
00602
00603   uint32_t MasterState;      /*!< Specifies the type of the TT master state.
00604                                   This parameter can be a value of @ref FDCAN_TT_master_state                   */
00605
00606   uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
00607                                   This parameter can be a value of @ref FDCAN_TT_sync_state                     */
00608
00609   uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
00610                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
00611                                   This parameter can be:
00612                                    - 0 : Global time not valid
00613                                    - 1 : Global time in phase with Time Master                                  */
00614
00615   uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
00616                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
00617                                   This parameter can be:
00618                                    - 0 : Local clock speed not synchronized to Time Master clock speed
00619                                    - 1 : Synchronization Deviation = SDL                                        */
00620
00621   uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
00622                                   This parameter can be a number between 0 and 0xFF                             */
00623
00624   uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
00625                                   This parameter can be:
00626                                    - 0 : No global time preset pending
00627                                    - 1 : Node waits for the global time preset to take effect                   */
00628
00629   uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
00630                                   This parameter can be:
00631                                    - 0 : Reset at the end of each reference message
00632                                    - 1 : Gap finished                                                           */
00633
00634   uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
00635                                   This parameter can be a number between 0 and 0x7                              */
00636
00637   uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
00638                                   This parameter can be:
00639                                    - 0 : No Gap in schedule
00640                                    - 1 : Gap time after Basic Cycle has started                                 */
00641
00642   uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
00643                                   This parameter can be:
00644                                    - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
00645                                    - 1 : Reference message with Next_is_Gap = 1 received                        */
00646
00647   uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
00648                                   This parameter can be:
00649                                    - 0 : Application Watchdog served in time
00650                                    - 1 : Failed to serve Application Watchdog in time                           */
00651
00652   uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
00653                                   This parameter can be:
00654                                    - 0 : No external clock synchronization pending
00655                                    - 1 : Node waits for external clock synchronization to take effect           */
00656
00657   uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
00658                                   This parameter can be:
00659                                    - 0 : Phase outside range
00660                                    - 1 : Phase inside range                                                     */
00661
00662 } FDCAN_TTOperationStatusTypeDef;
00663
00664 /**
00665   * @brief  FDCAN Message RAM blocks
00666   */
00667 typedef struct
00668 {
00669   uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
00670                                   This parameter must be a 32-bit word address      */
00671
00672   uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
00673                                   This parameter must be a 32-bit word address      */
00674
00675   uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
00676                                   This parameter must be a 32-bit word address      */
00677
00678   uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
00679                                   This parameter must be a 32-bit word address      */
00680
00681   uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
00682                                   This parameter must be a 32-bit word address      */
00683
00684   uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
00685                                   This parameter must be a 32-bit word address      */
00686
00687   uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
00688                                   This parameter must be a 32-bit word address      */
00689
00690   uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
00691                                   This parameter must be a 32-bit word address      */
00692
00693   uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
00694                                   This parameter must be a 32-bit word address      */
00695
00696   uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
00697                                   This parameter must be a 32-bit word address      */
00698
00699 } FDCAN_MsgRamAddressTypeDef;
00700
00701 /**
00702   * @brief  FDCAN handle structure definition
00703   */
00704 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00705 typedef struct __FDCAN_HandleTypeDef
00706 #else
00707 typedef struct
00708 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00709 {
00710   FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
00711
00712   TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
00713
00714   FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
00715
00716   FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
00717
00718   uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
00719                                                of latest Tx FIFO/Queue request */
00720
00721   __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
00722
00723   HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
00724
00725   __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
00726
00727 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00728   void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
00729   void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
00730   void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
00731   void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
00732   void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
00733   void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
00734   void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
00735   void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
00736   void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
00737   void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
00738   void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
00739   void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
00740   void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
00741   void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
00742   void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
00743   void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
00744   void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
00745
00746   void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
00747   void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
00748 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00749
00750 } FDCAN_HandleTypeDef;
00751
00752 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00753 /**
00754   * @brief  HAL FDCAN common Callback ID enumeration definition
00755   */
00756 typedef enum
00757 {
00758   HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
00759   HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
00760   HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
00761   HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
00762   HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
00763   HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
00764
00765   HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
00766   HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
00767
00768 } HAL_FDCAN_CallbackIDTypeDef;
00769
00770 /**
00771   * @brief  HAL FDCAN Callback pointer definition
00772   */
00773 typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
00774 typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
00775 typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
00776 typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
00777 typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
00778 typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
00779 typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
00780 typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
00781 typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
00782 typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
00783 typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
00784 typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
00785 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00786
00787 /**
00788   * @}
00789   */
00790
00791 /* Exported constants --------------------------------------------------------*/
00792 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
00793   * @{
00794   */
00795
00796 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
00797   * @{
00798   */
00799 #define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
00800 #define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
00801 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
00802 #define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
00803 #define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
00804 #define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
00805 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
00806 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
00807 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
00808 #define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
00809 #define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
00810 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
00811 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
00812 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
00813 #define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
00814 #define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
00815 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
00816 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
00817 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
00818 #define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
00819 #define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
00820 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
00821 #define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
00822 #define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
00823 #define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
00824
00825 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00826 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
00827 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00828 /**
00829   * @}
00830   */
00831
00832 /** @defgroup FDCAN_frame_format FDCAN Frame Format
00833   * @{
00834   */
00835 #define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
00836 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
00837 #define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
00838 /**
00839   * @}
00840   */
00841
00842 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
00843   * @{
00844   */
00845 #define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
00846 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
00847 #define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
00848 #define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
00849 #define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
00850 /**
00851   * @}
00852   */
00853
00854 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
00855   * @{
00856   */
00857 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
00858 #define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
00864   * @{
00865   */
00866 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
00867 #define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
00868 #define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
00869 #define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
00870 #define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
00871 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
00872 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
00873 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
00874 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
00875 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
00876 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
00877 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
00878 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
00879 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
00880 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
00881 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
00882 /**
00883   * @}
00884   */
00885
00886 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
00887   * @{
00888   */
00889 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
00890 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup FDCAN_calibration_state FDCAN Calibration State
00896   * @{
00897   */
00898 #define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
00899 #define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
00900 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
00901 /**
00902   * @}
00903   */
00904
00905 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
00906   * @{
00907   */
00908 #define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
00909 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
00910 #define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size
00916   * @{
00917   */
00918 #define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
00919 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
00920 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
00921 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
00922 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
00923 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
00924 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
00925 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
00926 /**
00927   * @}
00928   */
00929
00930 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
00931   * @{
00932   */
00933 #define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
00934 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup FDCAN_id_type FDCAN ID Type
00940   * @{
00941   */
00942 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
00943 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
00944 /**
00945   * @}
00946   */
00947
00948 /** @defgroup FDCAN_frame_type FDCAN Frame Type
00949   * @{
00950   */
00951 #define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
00952 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
00953 /**
00954   * @}
00955   */
00956
00957 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
00958   * @{
00959   */
00960 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
00961 #define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
00962 #define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
00963 #define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
00964 #define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
00965 #define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
00966 #define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
00967 #define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
00968 #define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
00969 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
00970 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
00971 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
00972 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
00973 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
00974 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
00975 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
00981   * @{
00982   */
00983 #define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
00984 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
00985 /**
00986   * @}
00987   */
00988
00989 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
00990   * @{
00991   */
00992 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
00993 #define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
00994 /**
00995   * @}
00996   */
00997
00998 /** @defgroup FDCAN_format FDCAN format
00999   * @{
01000   */
01001 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
01002 #define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
01003 /**
01004   * @}
01005   */
01006
01007 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
01008   * @{
01009   */
01010 #define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
01011 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
01012 /**
01013   * @}
01014   */
01015
01016 /** @defgroup FDCAN_filter_type FDCAN Filter Type
01017   * @{
01018   */
01019 #define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
01020 #define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
01021 #define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
01022 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
01028   * @{
01029   */
01030 #define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
01031 #define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
01032 #define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
01033 #define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
01034 #define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
01035 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
01036 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
01037 #define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
01038 /**
01039   * @}
01040   */
01041
01042 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
01043   * @{
01044   */
01045 #define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
01046 #define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
01047 #define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
01048 #define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
01049 #define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
01050 #define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
01051 #define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
01052 #define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
01053 #define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
01054 #define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
01055 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
01056 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
01057 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
01058 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
01059 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
01060 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
01061 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
01062 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
01063 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
01064 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
01065 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
01066 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
01067 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
01068 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
01069 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
01070 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
01071 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
01072 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
01073 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
01074 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
01075 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
01076 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
01077 /**
01078   * @}
01079   */
01080
01081 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
01082   * @{
01083   */
01084 #define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
01085 #define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
01086 #define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
01087 #define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
01088 #define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
01089 #define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
01090 #define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
01091 #define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
01092 #define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
01093 #define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
01094 #define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
01095 #define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
01096 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
01097 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
01098 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
01099 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
01100 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
01101 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
01102 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
01103 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
01104 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
01105 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
01106 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
01107 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
01108 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
01109 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
01110 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
01111 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
01112 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
01113 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
01114 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
01115 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
01116 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
01117 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
01118 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
01119 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
01120 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
01121 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
01122 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
01123 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
01124 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
01125 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
01126 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
01127 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
01128 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
01129 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
01130 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
01131 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
01132 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
01133 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
01134 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
01135 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
01136 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
01137 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
01138 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
01139 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
01140 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
01141 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
01142 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
01143 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
01144 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
01145 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
01146 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
01147 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
01148 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
01149 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
01150 /**
01151   * @}
01152   */
01153
01154 /** @defgroup FDCAN_event_type FDCAN Event Type
01155   * @{
01156   */
01157 #define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
01158 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
01159 /**
01160   * @}
01161   */
01162
01163 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
01164   * @{
01165   */
01166 #define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
01167 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
01168 #define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
01169 #define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
01175   * @{
01176   */
01177 #define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
01178 #define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
01179 #define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
01180 #define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
01181 #define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
01182 #define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
01183 #define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
01184 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
01185 /**
01186   * @}
01187   */
01188
01189 /** @defgroup FDCAN_communication_state FDCAN communication state
01190   * @{
01191   */
01192 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
01193 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
01194 #define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
01195 #define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
01196 /**
01197   * @}
01198   */
01199
01200 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
01201   * @{
01202   */
01203 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
01204 #define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
01205 #define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
01206 /**
01207   * @}
01208   */
01209
01210 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
01211   * @{
01212   */
01213 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
01214 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
01215 /**
01216   * @}
01217   */
01218
01219 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
01220   * @{
01221   */
01222 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
01223 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
01224 #define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
01225 /**
01226   * @}
01227   */
01228
01229 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
01230   * @{
01231   */
01232 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
01233 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
01234 /**
01235   * @}
01236   */
01237
01238 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
01239   * @{
01240   */
01241 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
01242 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
01243 /**
01244   * @}
01245   */
01246
01247 /** @defgroup FDCAN_Timestamp FDCAN timestamp
01248   * @{
01249   */
01250 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
01251 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
01252 /**
01253   * @}
01254   */
01255
01256 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
01257   * @{
01258   */
01259 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
01260 #define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
01261 #define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
01262 #define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
01263 #define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
01264 #define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
01265 #define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
01266 #define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
01267 #define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
01268 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
01269 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
01270 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
01271 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
01272 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
01273 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
01274 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
01275 /**
01276   * @}
01277   */
01278
01279 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
01280   * @{
01281   */
01282 #define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
01283 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
01284 #define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
01285 #define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
01286 /**
01287   * @}
01288   */
01289
01290 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
01291   * @{
01292   */
01293 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
01294 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
01295 /**
01296   * @}
01297   */
01298
01299 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
01300   * @{
01301   */
01302 #define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
01303 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
01304 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
01305 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
01306 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
01307 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
01308 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
01309 /**
01310   * @}
01311   */
01312
01313 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
01314   * @{
01315   */
01316 #define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
01317 #define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
01318 #define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
01319 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
01320 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
01321 #define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
01322 #define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
01323 #define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
01324 #define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
01325 #define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
01326 #define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
01327 /**
01328   * @}
01329   */
01330
01331 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
01332   * @{
01333   */
01334 #define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
01335 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
01336 /**
01337   * @}
01338   */
01339
01340 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
01341   * @{
01342   */
01343 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
01344 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
01345 /**
01346   * @}
01347   */
01348
01349 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode
01350   * @{
01351   */
01352 #define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
01353 #define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
01354 #define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
01355 /**
01356   * @}
01357   */
01358
01359 /** @defgroup FDCAN_TT_operation FDCAN TT Operation
01360   * @{
01361   */
01362 #define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
01363 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
01364 /**
01365   * @}
01366   */
01367
01368 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
01369   * @{
01370   */
01371 #define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
01372 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
01373 /**
01374   * @}
01375   */
01376
01377 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
01378   * @{
01379   */
01380 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
01381 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
01382 /**
01383   * @}
01384   */
01385
01386 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
01387   * @{
01388   */
01389 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
01390 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
01391 /**
01392   * @}
01393   */
01394
01395 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
01396   * @{
01397   */
01398 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
01399 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
01400 /**
01401   * @}
01402   */
01403
01404 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
01405   * @{
01406   */
01407 #define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
01408 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
01409 /**
01410   * @}
01411   */
01412
01413 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
01414   * @{
01415   */
01416 #define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
01417 #define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
01418 #define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
01419 #define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
01420 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
01421 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
01422 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
01423 /**
01424   * @}
01425   */
01426
01427 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
01428   * @{
01429   */
01430 #define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
01431 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
01432 #define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
01433 /**
01434   * @}
01435   */
01436
01437 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
01438   * @{
01439   */
01440 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
01441 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
01442 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
01443 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
01444 /**
01445   * @}
01446   */
01447
01448 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
01449   * @{
01450   */
01451 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
01452 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
01453 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
01454 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
01455 /**
01456   * @}
01457   */
01458
01459 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
01460   * @{
01461   */
01462 #define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
01463 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
01464 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
01465 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
01466 /**
01467   * @}
01468   */
01469
01470 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
01471   * @{
01472   */
01473 #define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
01474 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
01475 /**
01476   * @}
01477   */
01478
01479 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
01480   * @{
01481   */
01482 #define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
01483 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
01484 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
01485 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
01486 /**
01487   * @}
01488   */
01489
01490 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
01491   * @{
01492   */
01493 #define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
01494 #define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
01495 #define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
01496 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
01497 /**
01498   * @}
01499   */
01500
01501 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State
01502   * @{
01503   */
01504 #define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
01505 #define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
01506 #define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
01507 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
01508 /**
01509   * @}
01510   */
01511
01512 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
01513   * @{
01514   */
01515 #define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
01516 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
01517 #define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
01518 #define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
01519 /**
01520   * @}
01521   */
01522
01523 /** @defgroup Interrupt_Masks Interrupt masks
01524   * @{
01525   */
01526 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
01527 #define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
01528 /**
01529   * @}
01530   */
01531
01532 /** @defgroup FDCAN_flags FDCAN Flags
01533   * @{
01534   */
01535 #define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
01536 #define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
01537 #define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
01538 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
01539 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
01540 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
01541 #define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
01542 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
01543 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
01544 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
01545 #define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
01546 #define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
01547 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
01548 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
01549 #define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
01550 #define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
01551 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
01552 #define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
01553 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
01554 #define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
01555 #define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
01556 #define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
01557 #define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
01558 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
01559 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
01560 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
01561 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
01562 #define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
01563 #define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
01564 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
01565 /**
01566   * @}
01567   */
01568
01569 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
01570   * @{
01571   */
01572
01573 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
01574   * @{
01575   */
01576 #define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
01577 #define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
01578 #define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
01579 /**
01580   * @}
01581   */
01582
01583 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
01584   * @{
01585   */
01586 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
01587 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
01588 /**
01589   * @}
01590   */
01591
01592 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
01593   * @{
01594   */
01595 #define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
01596 #define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
01597 /**
01598   * @}
01599   */
01600
01601 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
01602   * @{
01603   */
01604 #define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
01605 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
01606 /**
01607   * @}
01608   */
01609
01610 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
01611   * @{
01612   */
01613 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
01614 #define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
01615 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
01616 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
01617 /**
01618   * @}
01619   */
01620
01621 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
01622   * @{
01623   */
01624 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
01625 #define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
01626 #define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
01627 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
01628 /**
01629   * @}
01630   */
01631
01632 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
01633   * @{
01634   */
01635 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
01636 #define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
01637 #define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
01638 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
01639 /**
01640   * @}
01641   */
01642
01643 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
01644   * @{
01645   */
01646 #define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
01647 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
01648 #define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
01649 #define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
01650 #define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
01651 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
01652 /**
01653   * @}
01654   */
01655
01656 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
01657   * @{
01658   */
01659 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
01660 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
01661 #define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
01662 /**
01663   * @}
01664   */
01665
01666 /**
01667   * @}
01668   */
01669
01670 /** @defgroup FDCAN_TTflags FDCAN TT Flags
01671   * @{
01672   */
01673 #define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
01674 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
01675 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
01676 #define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
01677 #define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
01678 #define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
01679 #define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
01680 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
01681 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
01682 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
01683 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
01684 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
01685 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
01686 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
01687 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
01688 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
01689 #define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
01690 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
01691 #define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
01692 /**
01693   * @}
01694   */
01695
01696 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
01697   * @{
01698   */
01699
01700 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
01701   * @{
01702   */
01703 #define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
01704 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
01705 #define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
01706 #define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
01707 /**
01708   * @}
01709   */
01710
01711 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
01712   * @{
01713   */
01714 #define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
01715 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
01716 /**
01717   * @}
01718   */
01719
01720 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
01721   * @{
01722   */
01723 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
01724 /**
01725   * @}
01726   */
01727
01728 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
01729   * @{
01730   */
01731 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
01732 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
01733 /**
01734   * @}
01735   */
01736
01737 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
01738   * @{
01739   */
01740 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
01741 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
01742 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
01743 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
01744 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
01745 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
01746 /**
01747   * @}
01748   */
01749
01750 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
01751   * @{
01752   */
01753 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
01754 #define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
01755 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
01756 #define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
01757 /**
01758   * @}
01759   */
01760
01761 /**
01762   * @}
01763   */
01764
01765 /**
01766   * @}
01767   */
01768
01769 /* Exported macro ------------------------------------------------------------*/
01770 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
01771   * @{
01772   */
01773
01774 /** @brief  Reset FDCAN handle state.
01775   * @param  __HANDLE__ FDCAN handle.
01776   * @retval None
01777   */
01778 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01779 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
01780                                                       (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
01781                                                       (__HANDLE__)->MspInitCallback = NULL;           \
01782                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
01783                                                      } while(0)
01784 #else
01785 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
01786 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01787
01788 /**
01789   * @brief  Enable the specified FDCAN interrupts.
01790   * @param  __HANDLE__ FDCAN handle.
01791   * @param  __INTERRUPT__ FDCAN interrupt.
01792   *         This parameter can be any combination of @arg FDCAN_Interrupts
01793   * @retval None
01794   */
01795 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
01796   do{                                                                \
01797     (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
01798     FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
01799   }while(0)
01800
01801
01802 /**
01803   * @brief  Disable the specified FDCAN interrupts.
01804   * @param  __HANDLE__ FDCAN handle.
01805   * @param  __INTERRUPT__ FDCAN interrupt.
01806   *         This parameter can be any combination of @arg FDCAN_Interrupts
01807   * @retval None
01808   */
01809 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
01810   do{                                                                   \
01811     ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
01812     FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
01813   }while(0)
01814
01815 /**
01816   * @brief  Check whether the specified FDCAN interrupt is set or not.
01817   * @param  __HANDLE__ FDCAN handle.
01818   * @param  __INTERRUPT__ FDCAN interrupt.
01819   *         This parameter can be one of @arg FDCAN_Interrupts
01820   * @retval ITStatus
01821   */
01822 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
01823
01824 /**
01825   * @brief  Clear the specified FDCAN interrupts.
01826   * @param  __HANDLE__ FDCAN handle.
01827   * @param  __INTERRUPT__ specifies the interrupts to clear.
01828   *         This parameter can be any combination of @arg FDCAN_Interrupts
01829   * @retval None
01830   */
01831 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
01832 do{                                                                   \
01833     ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
01834     FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
01835   }while(0)
01836
01837 /**
01838   * @brief  Check whether the specified FDCAN flag is set or not.
01839   * @param  __HANDLE__ FDCAN handle.
01840   * @param  __FLAG__ FDCAN flag.
01841   *         This parameter can be one of @arg FDCAN_flags
01842   * @retval FlagStatus
01843   */
01844 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
01845
01846 /**
01847   * @brief  Clear the specified FDCAN flags.
01848   * @param  __HANDLE__ FDCAN handle.
01849   * @param  __FLAG__ specifies the flags to clear.
01850   *         This parameter can be any combination of @arg FDCAN_flags
01851   * @retval None
01852   */
01853 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
01854 do{                                                              \
01855     ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
01856     FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
01857   }while(0)
01858
01859 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
01860   * @param  __HANDLE__ FDCAN handle.
01861   * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
01862   *         This parameter can be a value of @arg FDCAN_Interrupts
01863   * @retval ITStatus
01864   */
01865 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
01866
01867 /**
01868   * @brief  Enable the specified FDCAN TT interrupts.
01869   * @param  __HANDLE__ FDCAN handle.
01870   * @param  __INTERRUPT__ FDCAN TT interrupt.
01871   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
01872   * @retval None
01873   */
01874 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
01875
01876 /**
01877   * @brief  Disable the specified FDCAN TT interrupts.
01878   * @param  __HANDLE__ FDCAN handle.
01879   * @param  __INTERRUPT__ FDCAN TT interrupt.
01880   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
01881   * @retval None
01882   */
01883 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
01884
01885 /**
01886   * @brief  Check whether the specified FDCAN TT interrupt is set or not.
01887   * @param  __HANDLE__ FDCAN handle.
01888   * @param  __INTERRUPT__ FDCAN TT interrupt.
01889   *         This parameter can be one of @arg FDCAN_TTInterrupts
01890   * @retval ITStatus
01891   */
01892 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
01893
01894 /**
01895   * @brief  Clear the specified FDCAN TT interrupts.
01896   * @param  __HANDLE__ FDCAN handle.
01897   * @param  __INTERRUPT__ specifies the TT interrupts to clear.
01898   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
01899   * @retval None
01900   */
01901 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
01902
01903 /**
01904   * @brief  Check whether the specified FDCAN TT flag is set or not.
01905   * @param  __HANDLE__ FDCAN handle.
01906   * @param  __FLAG__ FDCAN TT flag.
01907   *         This parameter can be one of @arg FDCAN_TTflags
01908   * @retval FlagStatus
01909   */
01910 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
01911
01912 /**
01913   * @brief  Clear the specified FDCAN TT flags.
01914   * @param  __HANDLE__ FDCAN handle.
01915   * @param  __FLAG__ specifies the TT flags to clear.
01916   *         This parameter can be any combination of @arg FDCAN_TTflags
01917   * @retval None
01918   */
01919 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
01920
01921 /** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
01922   * @param  __HANDLE__ FDCAN handle.
01923   * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
01924   *         This parameter can be a value of @arg FDCAN_TTInterrupts
01925   * @retval ITStatus
01926   */
01927 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
01928
01929 /**
01930   * @}
01931   */
01932
01933 /* Exported functions --------------------------------------------------------*/
01934 /** @addtogroup FDCAN_Exported_Functions
01935   * @{
01936   */
01937
01938 /** @addtogroup FDCAN_Exported_Functions_Group1
01939   * @{
01940   */
01941 /* Initialization and de-initialization functions *****************************/
01942 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
01943 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
01944 void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
01945 void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
01946 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01947 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01948
01949 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01950 /* Callbacks Register/UnRegister functions  ***********************************/
01951 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
01952 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
01953 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
01954 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
01955 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
01956 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
01957 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
01958 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
01959 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
01960 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
01961 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
01962 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
01963 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
01964 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
01965 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
01966 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
01967 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
01968 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
01969 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
01970 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
01971 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
01972 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
01973 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
01974 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
01975 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01976 /**
01977   * @}
01978   */
01979
01980 /** @addtogroup FDCAN_Exported_Functions_Group2
01981   * @{
01982   */
01983 /* Configuration functions ****************************************************/
01984 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
01985 uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
01986 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
01987 uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
01988 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
01989 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
01990 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
01991 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
01992 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
01993 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
01994 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
01995 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
01996 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01997 uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01998 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01999 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
02000 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
02001 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
02002 uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
02003 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
02004 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
02005 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
02006 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
02007 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
02008 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
02009 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
02010 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
02011 /**
02012   * @}
02013   */
02014
02015 /** @addtogroup FDCAN_Exported_Functions_Group3
02016   * @{
02017   */
02018 /* Control functions **********************************************************/
02019 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
02020 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
02021 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
02022 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
02023 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
02024 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
02025 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
02026 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
02027 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
02028 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
02029 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
02030 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
02031 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
02032 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
02033 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
02034 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
02035 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
02036 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
02037 /**
02038   * @}
02039   */
02040
02041 /** @addtogroup FDCAN_Exported_Functions_Group4
02042   * @{
02043   */
02044 /* TT Configuration and control functions**************************************/
02045 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
02046 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
02047 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
02048 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
02049 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
02050 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
02051 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
02052 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
02053 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
02054 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
02055 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
02056 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
02057 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
02058 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
02059 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
02060 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
02061 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
02062 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
02063 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
02064 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
02065 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
02066 /**
02067   * @}
02068   */
02069
02070 /** @addtogroup FDCAN_Exported_Functions_Group5
02071   * @{
02072   */
02073 /* Interrupts management ******************************************************/
02074 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
02075 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
02076 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
02077 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
02078 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
02079 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
02080 void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
02081 /**
02082   * @}
02083   */
02084
02085 /** @addtogroup FDCAN_Exported_Functions_Group6
02086   * @{
02087   */
02088 /* Callback functions *********************************************************/
02089 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
02090 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
02091 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
02092 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
02093 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
02094 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
02095 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
02096 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
02097 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
02098 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
02099 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
02100 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
02101 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
02102 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
02103 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
02104 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
02105 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
02106 /**
02107   * @}
02108   */
02109
02110 /** @addtogroup FDCAN_Exported_Functions_Group7
02111   * @{
02112   */
02113 /* Peripheral State functions *************************************************/
02114 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
02115 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
02116 /**
02117   * @}
02118   */
02119
02120 /**
02121   * @}
02122   */
02123
02124 /* Private types -------------------------------------------------------------*/
02125 /** @defgroup FDCAN_Private_Types FDCAN Private Types
02126   * @{
02127   */
02128
02129 /**
02130   * @}
02131   */
02132
02133 /* Private variables ---------------------------------------------------------*/
02134 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
02135   * @{
02136   */
02137
02138 /**
02139   * @}
02140   */
02141
02142 /* Private constants ---------------------------------------------------------*/
02143 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
02144   * @{
02145   */
02146
02147 /**
02148   * @}
02149   */
02150
02151 /* Private macros ------------------------------------------------------------*/
02152 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
02153   * @{
02154   */
02155 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
02156                                        ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
02157                                        ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
02158 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
02159                              ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
02160                              ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
02161                              ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
02162                              ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
02163
02164 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
02165                                                  ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
02166
02167 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
02168                                ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
02169                                ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
02170                                ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
02171                                ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
02172                                ((CKDIV) == FDCAN_CLOCK_DIV10) || \
02173                                ((CKDIV) == FDCAN_CLOCK_DIV12) || \
02174                                ((CKDIV) == FDCAN_CLOCK_DIV14) || \
02175                                ((CKDIV) == FDCAN_CLOCK_DIV16) || \
02176                                ((CKDIV) == FDCAN_CLOCK_DIV18) || \
02177                                ((CKDIV) == FDCAN_CLOCK_DIV20) || \
02178                                ((CKDIV) == FDCAN_CLOCK_DIV22) || \
02179                                ((CKDIV) == FDCAN_CLOCK_DIV24) || \
02180                                ((CKDIV) == FDCAN_CLOCK_DIV26) || \
02181                                ((CKDIV) == FDCAN_CLOCK_DIV28) || \
02182                                ((CKDIV) == FDCAN_CLOCK_DIV30))
02183 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
02184 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
02185 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
02186 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
02187 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
02188 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
02189 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
02190 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
02191 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
02192 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
02193 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
02194                                   ((SIZE) == FDCAN_DATA_BYTES_12) || \
02195                                   ((SIZE) == FDCAN_DATA_BYTES_16) || \
02196                                   ((SIZE) == FDCAN_DATA_BYTES_20) || \
02197                                   ((SIZE) == FDCAN_DATA_BYTES_24) || \
02198                                   ((SIZE) == FDCAN_DATA_BYTES_32) || \
02199                                   ((SIZE) == FDCAN_DATA_BYTES_48) || \
02200                                   ((SIZE) == FDCAN_DATA_BYTES_64))
02201 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
02202                                            ((MODE) == FDCAN_TX_QUEUE_OPERATION))
02203 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
02204                                    ((ID_TYPE) == FDCAN_EXTENDED_ID))
02205 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
02206                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
02207                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
02208                                      ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
02209                                      ((CONFIG) == FDCAN_FILTER_HP           ) || \
02210                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
02211                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
02212                                      ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
02213 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
02214                                         ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
02215                                         ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
02216                                         ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
02217                                         ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
02218                                         ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
02219                                         ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
02220                                         ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
02221                                         ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
02222                                         ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
02223                                         ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
02224                                         ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
02225                                         ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
02226                                         ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
02227                                         ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
02228                                         ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
02229 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
02230                                 ((FIFO) == FDCAN_RX_FIFO1))
02231 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
02232                                      ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
02233 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
02234                                         ((TYPE) == FDCAN_FILTER_DUAL ) || \
02235                                         ((TYPE) == FDCAN_FILTER_MASK ))
02236 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
02237                                         ((TYPE) == FDCAN_FILTER_DUAL         ) || \
02238                                         ((TYPE) == FDCAN_FILTER_MASK         ) || \
02239                                         ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
02240 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
02241                                    ((TYPE) == FDCAN_REMOTE_FRAME))
02242 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
02243                            ((DLC) == FDCAN_DLC_BYTES_1 ) || \
02244                            ((DLC) == FDCAN_DLC_BYTES_2 ) || \
02245                            ((DLC) == FDCAN_DLC_BYTES_3 ) || \
02246                            ((DLC) == FDCAN_DLC_BYTES_4 ) || \
02247                            ((DLC) == FDCAN_DLC_BYTES_5 ) || \
02248                            ((DLC) == FDCAN_DLC_BYTES_6 ) || \
02249                            ((DLC) == FDCAN_DLC_BYTES_7 ) || \
02250                            ((DLC) == FDCAN_DLC_BYTES_8 ) || \
02251                            ((DLC) == FDCAN_DLC_BYTES_12) || \
02252                            ((DLC) == FDCAN_DLC_BYTES_16) || \
02253                            ((DLC) == FDCAN_DLC_BYTES_20) || \
02254                            ((DLC) == FDCAN_DLC_BYTES_24) || \
02255                            ((DLC) == FDCAN_DLC_BYTES_32) || \
02256                            ((DLC) == FDCAN_DLC_BYTES_48) || \
02257                            ((DLC) == FDCAN_DLC_BYTES_64))
02258 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
02259                            ((ESI) == FDCAN_ESI_PASSIVE))
02260 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
02261                            ((BRS) == FDCAN_BRS_ON ))
02262 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
02263                            ((FDF) == FDCAN_FD_CAN     ))
02264 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
02265                            ((EFC) == FDCAN_STORE_TX_EVENTS))
02266 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
02267 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
02268 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
02269                                        ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
02270                                        ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
02271 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
02272                                             ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
02273                                             ((DESTINATION) == FDCAN_REJECT            ))
02274 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
02275                                              ((DESTINATION) == FDCAN_REJECT_REMOTE))
02276 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
02277                                    ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
02278 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
02279                                        ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
02280 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
02281                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
02282                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
02283                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
02284                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
02285                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
02286                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
02287                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
02288                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
02289                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
02290                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
02291                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
02292                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
02293                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
02294                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
02295                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
02296 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
02297                                      ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
02298                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
02299                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
02300 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
02301                                                    ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
02302 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
02303                                                ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
02304                                                ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
02305 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
02306                                                         ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
02307 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
02308                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
02309                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
02310                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
02311                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
02312                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
02313                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
02314 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
02315                                         ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
02316                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
02317                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
02318                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
02319                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
02320                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
02321                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
02322                                         ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
02323                                         ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
02324                                         ((TYPE) == FDCAN_TT_END_OF_LIST           ))
02325 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
02326                                               ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
02327 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
02328                                               ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
02329 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
02330                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
02331                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
02332 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
02333                                           ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
02334 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
02335                                            ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
02336 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
02337                                              ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
02338 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
02339                                                       ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
02340 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
02341                                                        ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
02342 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
02343                                                       ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
02344 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
02345                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
02346                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
02347                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
02348                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
02349                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
02350                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
02351 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
02352                                             ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
02353                                             ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
02354 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
02355 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
02356 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
02357 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
02358 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
02359 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
02360                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
02361                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
02362                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
02363 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
02364                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
02365                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
02366                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
02367 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
02368 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
02369                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
02370                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
02371                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
02372 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
02373                                                    ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
02374 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
02375                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
02376                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
02377                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
02378 /**
02379   * @}
02380   */
02381
02382 /* Private functions prototypes ----------------------------------------------*/
02383 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
02384   * @{
02385   */
02386
02387 /**
02388   * @}
02389   */
02390
02391 /* Private functions ---------------------------------------------------------*/
02392 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
02393   * @{
02394   */
02395
02396 /**
02397   * @}
02398   */
02399 /**
02400   * @}
02401   */
02402
02403 /**
02404   * @}
02405   */
02406
02407 #ifdef __cplusplus
02408 }
02409 #endif
02410
02411 #endif /* STM32H7xx_HAL_FDCAN_H */
02412
02413
02414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash.c Source File

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stm32h7xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the internal FLASH memory:
00008   *           + Program operations functions
00009   *           + Memory Control functions
00010   *           + Peripheral Errors functions
00011   *
00012  @verbatim
00013   ==============================================================================
00014                         ##### FLASH peripheral features #####
00015   ==============================================================================
00016
00017   [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
00018        to the Flash memory. It implements the erase and program Flash memory operations
00019        and the read and write protection mechanisms.
00020
00021   [..] The FLASH main features are:
00022       (+) Flash memory read operations
00023       (+) Flash memory program/erase operations
00024       (+) Read / write protections
00025       (+) Option bytes programming
00026       (+) Error code correction (ECC) : Data in flash are 266-bits word
00027           (10 bits added per flash word)
00028
00029                         ##### How to use this driver #####
00030  ==============================================================================
00031     [..]
00032       This driver provides functions and macros to configure and program the FLASH
00033       memory of all STM32H7xx devices.
00034
00035       (#) FLASH Memory IO Programming functions:
00036            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00037                 HAL_FLASH_Lock() functions
00038            (++) Program functions: 256-bit word only
00039            (++) There Two modes of programming :
00040             (+++) Polling mode using HAL_FLASH_Program() function
00041             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00042
00043       (#) Interrupts and flags management functions :
00044            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00045            (++) Callback functions are called when the flash operations are finished :
00046                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00047                 HAL_FLASH_OperationErrorCallback()
00048            (++) Get error flag status by calling HAL_FLASH_GetError()
00049
00050       (#) Option bytes management functions :
00051            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00052                 HAL_FLASH_OB_Lock() functions
00053            (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
00054                 In this case, a reset is generated
00055     [..]
00056       In addition to these functions, this driver includes a set of macros allowing
00057       to handle the following operations:
00058        (+) Set the latency
00059        (+) Enable/Disable the FLASH interrupts
00060        (+) Monitor the FLASH flags status
00061      [..]
00062     (@) For any Flash memory program operation (erase or program), the CPU clock frequency
00063         (HCLK) must be at least 1MHz.
00064     (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
00065         a Flash memory operation.
00066     (@) The application can simultaneously request a read and a write operation through each AXI
00067         interface.
00068         As the Flash memory is divided into two independent banks, the embedded Flash
00069         memory interface can drive different operations at the same time on each bank. For
00070         example a read, write or erase operation can be executed on bank 1 while another read,
00071         write or erase operation is executed on bank 2.
00072
00073  @endverbatim
00074   ******************************************************************************
00075   * @attention
00076   *
00077   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00078   * All rights reserved.</center></h2>
00079   *
00080   * This software component is licensed by ST under BSD 3-Clause license,
00081   * the "License"; You may not use this file except in compliance with the
00082   * License. You may obtain a copy of the License at:
00083   *                       opensource.org/licenses/BSD-3-Clause
00084   *
00085   ******************************************************************************
00086   */
00087
00088 /* Includes ------------------------------------------------------------------*/
00089 #include "stm32h7xx_hal.h"
00090
00091 /** @addtogroup STM32H7xx_HAL_Driver
00092   * @{
00093   */
00094
00095 /** @defgroup FLASH FLASH
00096   * @brief FLASH HAL module driver
00097   * @{
00098   */
00099
00100 #ifdef HAL_FLASH_MODULE_ENABLED
00101
00102 /* Private typedef -----------------------------------------------------------*/
00103 /* Private define ------------------------------------------------------------*/
00104 /** @addtogroup FLASH_Private_Constants
00105   * @{
00106   */
00107 #define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
00108
00109 /**
00110   * @}
00111   */
00112 /* Private macro -------------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 FLASH_ProcessTypeDef pFlash;
00115 /* Private function prototypes -----------------------------------------------*/
00116 /* Exported functions ---------------------------------------------------------*/
00117
00118 /** @defgroup FLASH_Exported_Functions FLASH Exported functions
00119   * @{
00120   */
00121
00122 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00123  *  @brief   Programming operation functions
00124  *
00125 @verbatim
00126  ===============================================================================
00127                   ##### Programming operation functions #####
00128  ===============================================================================
00129     [..]
00130     This subsection provides a set of functions allowing to manage the FLASH
00131     program operations.
00132
00133 @endverbatim
00134   * @{
00135   */
00136
00137 /**
00138   * @brief  Program flash word at a specified address
00139   * @param  TypeProgram Indicate the way to program at a specified address.
00140   *         This parameter can be a value of @ref FLASH_Type_Program
00141   * @param  FlashAddress specifies the address to be programmed.
00142   * @param  DataAddress specifies the address of data to be programmed
00143   *
00144   * @retval HAL_StatusTypeDef HAL Status
00145   */
00146 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
00147 {
00148   HAL_StatusTypeDef status;
00149   __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress;
00150   __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
00151   uint32_t bank;
00152   uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
00153
00154   /* Check the parameters */
00155   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00156   assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
00157
00158   /* Process Locked */
00159   __HAL_LOCK(&pFlash);
00160
00161 #if defined (FLASH_OPTCR_PG_OTP)
00162   if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
00163 #else
00164   if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
00165 #endif /* FLASH_OPTCR_PG_OTP */
00166   {
00167     bank = FLASH_BANK_1;
00168   }
00169   else
00170   {
00171     bank = FLASH_BANK_2;
00172   }
00173
00174   /* Reset error code */
00175   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00176
00177   /* Wait for last operation to be completed */
00178   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
00179
00180   if(status == HAL_OK)
00181   {
00182     if(bank == FLASH_BANK_1)
00183     {
00184 #if defined (FLASH_OPTCR_PG_OTP)
00185       if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
00186       {
00187         /* Set OTP_PG bit */
00188         SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
00189       }
00190       else
00191 #endif /* FLASH_OPTCR_PG_OTP */
00192       {
00193         /* Set PG bit */
00194         SET_BIT(FLASH->CR1, FLASH_CR_PG);
00195       }
00196     }
00197     else
00198     {
00199       /* Set PG bit */
00200       SET_BIT(FLASH->CR2, FLASH_CR_PG);
00201     }
00202
00203     __ISB();
00204     __DSB();
00205
00206 #if defined (FLASH_OPTCR_PG_OTP)
00207     if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
00208     {
00209       /* Program an OTP word (16 bits) */
00210       *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
00211     }
00212     else
00213 #endif /* FLASH_OPTCR_PG_OTP */
00214     {
00215       /* Program the flash word */
00216       do
00217       {
00218         *dest_addr = *src_addr;
00219         dest_addr++;
00220         src_addr++;
00221         row_index--;
00222      } while (row_index != 0U);
00223     }
00224
00225     __ISB();
00226     __DSB();
00227
00228     /* Wait for last operation to be completed */
00229     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
00230
00231 #if defined (FLASH_OPTCR_PG_OTP)
00232     if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
00233     {
00234       /* If the program operation is completed, disable the OTP_PG */
00235       CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
00236     }
00237     else
00238 #endif /* FLASH_OPTCR_PG_OTP */
00239     {
00240       if(bank == FLASH_BANK_1)
00241       {
00242         /* If the program operation is completed, disable the PG */
00243         CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
00244       }
00245       else
00246       {
00247         /* If the program operation is completed, disable the PG */
00248         CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
00249       }
00250     }
00251   }
00252
00253   /* Process Unlocked */
00254   __HAL_UNLOCK(&pFlash);
00255
00256   return status;
00257 }
00258
00259 /**
00260   * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
00261   * @param  TypeProgram Indicate the way to program at a specified address.
00262   *                      This parameter can be a value of @ref FLASH_Type_Program
00263   * @param  FlashAddress specifies the address to be programmed.
00264   * @param  DataAddress specifies the address of data (256 bits) to be programmed
00265   *
00266   * @retval HAL Status
00267   */
00268 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
00269 {
00270   HAL_StatusTypeDef status;
00271   __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress;
00272   __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
00273   uint32_t bank;
00274   uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
00275
00276   /* Check the parameters */
00277   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00278   assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
00279
00280   /* Process Locked */
00281   __HAL_LOCK(&pFlash);
00282
00283   /* Reset error code */
00284   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00285
00286 #if defined (FLASH_OPTCR_PG_OTP)
00287   if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
00288 #else
00289   if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
00290 #endif /* FLASH_OPTCR_PG_OTP */
00291   {
00292     bank = FLASH_BANK_1;
00293   }
00294   else
00295   {
00296     bank = FLASH_BANK_2;
00297   }
00298
00299   /* Wait for last operation to be completed */
00300   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
00301
00302   if (status != HAL_OK)
00303   {
00304     /* Process Unlocked */
00305     __HAL_UNLOCK(&pFlash);
00306   }
00307   else
00308   {
00309     pFlash.Address = FlashAddress;
00310
00311     if(bank == FLASH_BANK_1)
00312     {
00313       /* Set internal variables used by the IRQ handler */
00314       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
00315
00316 #if defined (FLASH_OPTCR_PG_OTP)
00317       if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
00318       {
00319         /* Set OTP_PG bit */
00320         SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
00321       }
00322       else
00323 #endif /* FLASH_OPTCR_PG_OTP */
00324       {
00325         /* Set PG bit */
00326         SET_BIT(FLASH->CR1, FLASH_CR_PG);
00327       }
00328
00329       /* Enable End of Operation and Error interrupts for Bank 1 */
00330 #if defined (FLASH_CR_OPERRIE)
00331       __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00332                                   FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00333 #else
00334       __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00335                                   FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
00336 #endif /* FLASH_CR_OPERRIE */
00337     }
00338     else
00339     {
00340       /* Set internal variables used by the IRQ handler */
00341       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
00342
00343       /* Set PG bit */
00344       SET_BIT(FLASH->CR2, FLASH_CR_PG);
00345
00346       /* Enable End of Operation and Error interrupts for Bank2 */
00347 #if defined (FLASH_CR_OPERRIE)
00348       __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00349                                   FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00350 #else
00351       __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00352                                   FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
00353 #endif /* FLASH_CR_OPERRIE */
00354     }
00355
00356     __ISB();
00357     __DSB();
00358
00359 #if defined (FLASH_OPTCR_PG_OTP)
00360     if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
00361     {
00362       /* Program an OTP word (16 bits) */
00363       *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
00364     }
00365     else
00366 #endif /* FLASH_OPTCR_PG_OTP */
00367     {
00368       /* Program the flash word */
00369       do
00370       {
00371         *dest_addr = *src_addr;
00372         dest_addr++;
00373         src_addr++;
00374         row_index--;
00375       } while (row_index != 0U);
00376     }
00377
00378     __ISB();
00379     __DSB();
00380   }
00381
00382   return status;
00383 }
00384
00385 /**
00386   * @brief This function handles FLASH interrupt request.
00387   * @retval None
00388   */
00389 void HAL_FLASH_IRQHandler(void)
00390 {
00391   uint32_t temp;
00392   uint32_t errorflag;
00393   FLASH_ProcedureTypeDef procedure;
00394
00395   /* Check FLASH Bank1 End of Operation flag  */
00396   if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
00397   {
00398     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
00399     {
00400       /* Nb of sector to erased can be decreased */
00401       pFlash.NbSectorsToErase--;
00402
00403       /* Check if there are still sectors to erase */
00404       if(pFlash.NbSectorsToErase != 0U)
00405       {
00406         /* Indicate user which sector has been erased */
00407         HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
00408
00409         /* Clear bank 1 End of Operation pending bit */
00410         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00411
00412         /* Increment sector number */
00413         pFlash.Sector++;
00414         temp = pFlash.Sector;
00415         FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase);
00416       }
00417       else
00418       {
00419         /* No more sectors to Erase, user callback can be called */
00420         /* Reset Sector and stop Erase sectors procedure */
00421         pFlash.Sector = 0xFFFFFFFFU;
00422         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00423
00424         /* FLASH EOP interrupt user callback */
00425         HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
00426
00427         /* Clear FLASH End of Operation pending bit */
00428         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00429       }
00430     }
00431     else
00432     {
00433       procedure = pFlash.ProcedureOnGoing;
00434
00435       if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
00436       {
00437         /* MassErase ended. Return the selected bank */
00438         /* FLASH EOP interrupt user callback */
00439         HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
00440       }
00441       else if(procedure == FLASH_PROC_PROGRAM_BANK1)
00442       {
00443         /* Program ended. Return the selected address */
00444         /* FLASH EOP interrupt user callback */
00445         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00446       }
00447       else
00448       {
00449         /* Nothing to do */
00450       }
00451
00452       if((procedure != FLASH_PROC_SECTERASE_BANK2) && \
00453          (procedure != FLASH_PROC_MASSERASE_BANK2) && \
00454          (procedure != FLASH_PROC_PROGRAM_BANK2))
00455       {
00456         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00457         /* Clear FLASH End of Operation pending bit */
00458         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00459       }
00460     }
00461   }
00462
00463   /* Check FLASH Bank2 End of Operation flag  */
00464   if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
00465   {
00466     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
00467     {
00468       /*Nb of sector to erased can be decreased*/
00469       pFlash.NbSectorsToErase--;
00470
00471       /* Check if there are still sectors to erase*/
00472       if(pFlash.NbSectorsToErase != 0U)
00473       {
00474         /*Indicate user which sector has been erased*/
00475         HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
00476
00477         /* Clear bank 2 End of Operation pending bit */
00478         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00479
00480         /*Increment sector number*/
00481         pFlash.Sector++;
00482         temp = pFlash.Sector;
00483         FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase);
00484       }
00485       else
00486       {
00487         /* No more sectors to Erase, user callback can be called */
00488         /* Reset Sector and stop Erase sectors procedure */
00489         pFlash.Sector = 0xFFFFFFFFU;
00490         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00491
00492         /* FLASH EOP interrupt user callback */
00493         HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
00494
00495         /* Clear FLASH End of Operation pending bit */
00496         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00497       }
00498     }
00499     else
00500     {
00501       procedure = pFlash.ProcedureOnGoing;
00502
00503       if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
00504       {
00505         /*MassErase ended. Return the selected bank*/
00506         /* FLASH EOP interrupt user callback */
00507         HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
00508       }
00509       else if(procedure == FLASH_PROC_PROGRAM_BANK2)
00510       {
00511         /* Program ended. Return the selected address */
00512         /* FLASH EOP interrupt user callback */
00513         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00514       }
00515       else
00516       {
00517         /* Nothing to do */
00518       }
00519
00520       if((procedure != FLASH_PROC_SECTERASE_BANK1) && \
00521          (procedure != FLASH_PROC_MASSERASE_BANK1) && \
00522          (procedure != FLASH_PROC_PROGRAM_BANK1))
00523       {
00524         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00525         /* Clear FLASH End of Operation pending bit */
00526         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00527       }
00528     }
00529   }
00530
00531   /* Check FLASH Bank1 operation error flags */
00532 #if defined (FLASH_SR_OPERR)
00533   errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
00534                             FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
00535 #else
00536   errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
00537                             FLASH_FLAG_INCERR_BANK1);
00538 #endif /* FLASH_SR_OPERR */
00539
00540   if(errorflag != 0U)
00541   {
00542     /* Save the error code */
00543     pFlash.ErrorCode |= errorflag;
00544
00545     /* Clear error programming flags */
00546     __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
00547
00548     procedure = pFlash.ProcedureOnGoing;
00549
00550     if(procedure == FLASH_PROC_SECTERASE_BANK1)
00551     {
00552       /* Return the faulty sector */
00553       temp = pFlash.Sector;
00554       pFlash.Sector = 0xFFFFFFFFU;
00555     }
00556     else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
00557     {
00558       /* Return the faulty bank */
00559       temp = FLASH_BANK_1;
00560     }
00561     else
00562     {
00563       /* Return the faulty address */
00564       temp = pFlash.Address;
00565     }
00566
00567     /* Stop the procedure ongoing*/
00568     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00569
00570     /* FLASH error interrupt user callback */
00571     HAL_FLASH_OperationErrorCallback(temp);
00572   }
00573
00574   /* Check FLASH Bank2 operation error flags */
00575 #if defined (FLASH_SR_OPERR)
00576   errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
00577                              FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
00578 #else
00579   errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
00580                              FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
00581 #endif /* FLASH_SR_OPERR */
00582
00583   if(errorflag != 0U)
00584   {
00585     /* Save the error code */
00586     pFlash.ErrorCode |= (errorflag | 0x80000000U);
00587
00588     /* Clear error programming flags */
00589     __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
00590
00591     procedure = pFlash.ProcedureOnGoing;
00592
00593     if(procedure== FLASH_PROC_SECTERASE_BANK2)
00594     {
00595       /*return the faulty sector*/
00596       temp = pFlash.Sector;
00597       pFlash.Sector = 0xFFFFFFFFU;
00598     }
00599     else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
00600     {
00601       /*return the faulty bank*/
00602       temp = FLASH_BANK_2;
00603     }
00604     else
00605     {
00606       /*return the faulty address*/
00607       temp = pFlash.Address;
00608     }
00609
00610     /*Stop the procedure ongoing*/
00611     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00612
00613     /* FLASH error interrupt user callback */
00614     HAL_FLASH_OperationErrorCallback(temp);
00615   }
00616
00617   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00618   {
00619 #if defined (FLASH_CR_OPERRIE)
00620     /* Disable Bank1 Operation and Error source interrupt */
00621     __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00622                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00623
00624     /* Disable Bank2 Operation and Error source interrupt */
00625     __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00626                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00627 #else
00628     /* Disable Bank1 Operation and Error source interrupt */
00629     __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00630                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
00631
00632     /* Disable Bank2 Operation and Error source interrupt */
00633     __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00634                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
00635 #endif /* FLASH_CR_OPERRIE */
00636
00637     /* Process Unlocked */
00638     __HAL_UNLOCK(&pFlash);
00639   }
00640 }
00641
00642 /**
00643   * @brief  FLASH end of operation interrupt callback
00644   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00645   *                  Mass Erase: Bank number which has been requested to erase
00646   *                  Sectors Erase: Sector which has been erased
00647   *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
00648   *                  Program: Address which was selected for data program
00649   * @retval None
00650   */
00651 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00652 {
00653   /* Prevent unused argument(s) compilation warning */
00654   UNUSED(ReturnValue);
00655
00656   /* NOTE : This function Should not be modified, when the callback is needed,
00657             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00658    */
00659 }
00660
00661 /**
00662   * @brief  FLASH operation error interrupt callback
00663   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00664   *                 Mass Erase: Bank number which has been requested to erase
00665   *                 Sectors Erase: Sector number which returned an error
00666   *                 Program: Address which was selected for data program
00667   * @retval None
00668   */
00669 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00670 {
00671   /* Prevent unused argument(s) compilation warning */
00672   UNUSED(ReturnValue);
00673
00674   /* NOTE : This function Should not be modified, when the callback is needed,
00675             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00676    */
00677 }
00678
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00684  *  @brief   Management functions
00685  *
00686 @verbatim
00687  ===============================================================================
00688                       ##### Peripheral Control functions #####
00689  ===============================================================================
00690     [..]
00691     This subsection provides a set of functions allowing to control the FLASH
00692     memory operations.
00693
00694 @endverbatim
00695   * @{
00696   */
00697
00698 /**
00699   * @brief  Unlock the FLASH control registers access
00700   * @retval HAL Status
00701   */
00702 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00703 {
00704   if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
00705   {
00706     /* Authorize the FLASH Bank1 Registers access */
00707     WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
00708     WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
00709
00710     /* Verify Flash Bank1 is unlocked */
00711     if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
00712     {
00713       return HAL_ERROR;
00714     }
00715   }
00716
00717   if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
00718   {
00719     /* Authorize the FLASH Bank2 Registers access */
00720     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
00721     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
00722
00723     /* Verify Flash Bank2 is unlocked */
00724     if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
00725     {
00726       return HAL_ERROR;
00727     }
00728   }
00729
00730   return HAL_OK;
00731 }
00732
00733 /**
00734   * @brief  Locks the FLASH control registers access
00735   * @retval HAL Status
00736   */
00737 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00738 {
00739   /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */
00740   SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
00741
00742   /* Verify Flash Bank1 is locked */
00743   if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U)
00744   {
00745     return HAL_ERROR;
00746   }
00747
00748   /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
00749   SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
00750
00751   /* Verify Flash Bank2 is locked */
00752   if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U)
00753   {
00754     return HAL_ERROR;
00755   }
00756
00757   return HAL_OK;
00758 }
00759
00760 /**
00761   * @brief  Unlock the FLASH Option Control Registers access.
00762   * @retval HAL Status
00763   */
00764 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00765 {
00766   if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
00767   {
00768     /* Authorizes the Option Byte registers programming */
00769     WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
00770     WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
00771
00772     /* Verify that the Option Bytes are unlocked */
00773     if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
00774     {
00775       return HAL_ERROR;
00776     }
00777   }
00778
00779   return HAL_OK;
00780 }
00781
00782 /**
00783   * @brief  Lock the FLASH Option Control Registers access.
00784   * @retval HAL Status
00785   */
00786 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00787 {
00788   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00789   SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
00790
00791   /* Verify that the Option Bytes are locked */
00792   if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U)
00793   {
00794     return HAL_ERROR;
00795   }
00796
00797   return HAL_OK;
00798 }
00799
00800 /**
00801   * @brief  Launch the option bytes loading.
00802   * @retval HAL Status
00803   */
00804 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00805 {
00806   HAL_StatusTypeDef status;
00807
00808   /* Wait for CRC computation to be completed */
00809   if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
00810   {
00811     status = HAL_ERROR;
00812   }
00813   else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
00814   {
00815     status = HAL_ERROR;
00816   }
00817   else
00818   {
00819     status = HAL_OK;
00820   }
00821
00822   if (status == HAL_OK)
00823   {
00824     /* Set OPTSTRT Bit */
00825     SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
00826
00827     /* Wait for OB change operation to be completed */
00828     status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00829   }
00830
00831   return status;
00832 }
00833
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00839  *  @brief   Peripheral Errors functions
00840  *
00841 @verbatim
00842  ===============================================================================
00843                 ##### Peripheral Errors functions #####
00844  ===============================================================================
00845     [..]
00846     This subsection permits to get in run-time Errors of the FLASH peripheral.
00847
00848 @endverbatim
00849   * @{
00850   */
00851
00852 /**
00853   * @brief  Get the specific FLASH error flag.
00854   * @retval HAL_FLASH_ERRORCode The returned value can be:
00855   *            @arg HAL_FLASH_ERROR_NONE       : No error set
00856   *
00857   *            @arg HAL_FLASH_ERROR_WRP_BANK1  : Write Protection Error on Bank 1
00858   *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
00859   *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
00860   *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
00861   *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
00862   *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
00863   *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
00864   *            @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
00865   *            @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
00866   *            @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
00867   *
00868   *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
00869   *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
00870   *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
00871   *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
00872   *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
00873   *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
00874   *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
00875   *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
00876   *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
00877   *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
00878 */
00879
00880 uint32_t HAL_FLASH_GetError(void)
00881 {
00882    return pFlash.ErrorCode;
00883 }
00884
00885 /**
00886   * @}
00887   */
00888
00889 /**
00890   * @}
00891   */
00892
00893 /* Private functions ---------------------------------------------------------*/
00894
00895 /** @addtogroup FLASH_Private_Functions
00896   * @{
00897   */
00898
00899 /**
00900   * @brief  Wait for a FLASH operation to complete.
00901   * @param  Timeout maximum flash operation timeout
00902   * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
00903   * @retval HAL_StatusTypeDef HAL Status
00904   */
00905 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
00906 {
00907   /* Wait for the FLASH operation to complete by polling on QW flag to be reset.
00908      Even if the FLASH operation fails, the QW flag will be reset and an error
00909      flag will be set */
00910
00911   uint32_t bsyflag, errorflag;
00912   uint32_t tickstart = HAL_GetTick();
00913
00914   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
00915
00916   /* Select bsyflag depending on Bank */
00917   if(Bank == FLASH_BANK_1)
00918   {
00919     bsyflag = FLASH_FLAG_QW_BANK1;
00920   }
00921   else
00922   {
00923     bsyflag = FLASH_FLAG_QW_BANK2;
00924   }
00925
00926   while(__HAL_FLASH_GET_FLAG(bsyflag))
00927   {
00928     if(Timeout != HAL_MAX_DELAY)
00929     {
00930       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00931       {
00932         return HAL_TIMEOUT;
00933       }
00934     }
00935   }
00936
00937   /* Get Error Flags */
00938   if (Bank == FLASH_BANK_1)
00939   {
00940     errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
00941   }
00942   else
00943   {
00944     errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
00945   }
00946
00947   /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
00948   if((errorflag & 0x7DFFFFFFU) != 0U)
00949   {
00950     /*Save the error code*/
00951     pFlash.ErrorCode |= errorflag;
00952
00953     /* Clear error programming flags */
00954     __HAL_FLASH_CLEAR_FLAG(errorflag);
00955
00956     return HAL_ERROR;
00957   }
00958
00959   /* Check FLASH End of Operation flag  */
00960   if(Bank == FLASH_BANK_1)
00961   {
00962     if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
00963     {
00964       /* Clear FLASH End of Operation pending bit */
00965       __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00966     }
00967   }
00968   else
00969   {
00970     if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
00971     {
00972       /* Clear FLASH End of Operation pending bit */
00973       __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00974     }
00975   }
00976
00977   return HAL_OK;
00978 }
00979
00980 /**
00981   * @brief  Wait for a FLASH Option Bytes change operation to complete.
00982   * @param  Timeout maximum flash operation timeout
00983   * @retval HAL_StatusTypeDef HAL Status
00984   */
00985 HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
00986 {
00987   /* Get timeout */
00988   uint32_t tickstart = HAL_GetTick();
00989
00990   /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */
00991   while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U)
00992   {
00993     if(Timeout != HAL_MAX_DELAY)
00994     {
00995       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00996       {
00997         return HAL_TIMEOUT;
00998       }
00999     }
01000   }
01001
01002   /* Check option byte change error */
01003   if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U)
01004   {
01005     /* Save the error code */
01006     pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
01007
01008     /* Clear the OB error flag */
01009     FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
01010
01011     return HAL_ERROR;
01012   }
01013
01014   /* If there is no error flag set */
01015   return HAL_OK;
01016 }
01017
01018 /**
01019   * @brief  Wait for a FLASH CRC computation to complete.
01020   * @param  Timeout maximum flash operation timeout
01021   * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
01022   * @retval HAL_StatusTypeDef HAL Status
01023   */
01024 HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
01025 {
01026   uint32_t bsyflag;
01027   uint32_t tickstart = HAL_GetTick();
01028
01029   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
01030
01031   /* Select bsyflag depending on Bank */
01032   if(Bank == FLASH_BANK_1)
01033   {
01034     bsyflag = FLASH_FLAG_CRC_BUSY_BANK1;
01035   }
01036   else
01037   {
01038     bsyflag = FLASH_FLAG_CRC_BUSY_BANK2;
01039   }
01040
01041   /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */
01042   while(__HAL_FLASH_GET_FLAG(bsyflag))
01043   {
01044     if(Timeout != HAL_MAX_DELAY)
01045     {
01046       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01047       {
01048         return HAL_TIMEOUT;
01049       }
01050     }
01051   }
01052
01053   /* Check FLASH CRC read error flag  */
01054   if(Bank == FLASH_BANK_1)
01055   {
01056     if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1))
01057     {
01058       /* Save the error code */
01059       pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1;
01060
01061       /* Clear FLASH CRC read error pending bit */
01062       __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1);
01063
01064       return HAL_ERROR;
01065     }
01066   }
01067   else
01068   {
01069     if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
01070     {
01071       /* Save the error code */
01072       pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2;
01073
01074       /* Clear FLASH CRC read error pending bit */
01075       __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2);
01076
01077       return HAL_ERROR;
01078     }
01079   }
01080
01081   /* If there is no error flag set */
01082   return HAL_OK;
01083 }
01084
01085 /**
01086   * @}
01087   */
01088
01089 #endif /* HAL_FLASH_MODULE_ENABLED */
01090
01091 /**
01092   * @}
01093   */
01094
01095 /**
01096   * @}
01097   */
01098
01099 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash.h Source File

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stm32h7xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_FLASH_H
00022 #define STM32H7xx_HAL_FLASH_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FLASH
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  FLASH Procedure structure definition
00046   */
00047 typedef enum
00048 {
00049   FLASH_PROC_NONE = 0U,
00050   FLASH_PROC_SECTERASE_BANK1,
00051   FLASH_PROC_MASSERASE_BANK1,
00052   FLASH_PROC_PROGRAM_BANK1,
00053   FLASH_PROC_SECTERASE_BANK2,
00054   FLASH_PROC_MASSERASE_BANK2,
00055   FLASH_PROC_PROGRAM_BANK2,
00056   FLASH_PROC_ALLBANK_MASSERASE
00057 } FLASH_ProcedureTypeDef;
00058
00059
00060 /**
00061   * @brief  FLASH handle Structure definition
00062   */
00063 typedef struct
00064 {
00065   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
00066
00067   __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
00068
00069   __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
00070
00071   __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
00072
00073   __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
00074
00075   HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
00076
00077   __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
00078
00079 }FLASH_ProcessTypeDef;
00080
00081 /**
00082   * @}
00083   */
00084
00085 /* Exported constants --------------------------------------------------------*/
00086 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00087   * @{
00088   */
00089
00090 /** @defgroup FLASH_Error_Code FLASH Error Code
00091   * @brief    FLASH Error Code
00092   * @{
00093   */
00094 #define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
00095
00096 #define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
00097 #define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
00098 #define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
00099 #define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
00100 #if defined (FLASH_SR_OPERR)
00101 #define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
00102 #endif /* FLASH_SR_OPERR */
00103 #define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
00104 #define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
00105 #define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
00106 #define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
00107 #define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
00108
00109 #define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
00110 #define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
00111 #define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
00112 #define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
00113 #if defined (FLASH_SR_OPERR)
00114 #define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
00115 #endif /* FLASH_SR_OPERR */
00116 #define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
00117 #define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
00118 #define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
00119 #define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */
00120 #define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */
00121
00122 #define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */
00123 #define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
00124 #define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
00125 #define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
00126 #if defined (FLASH_SR_OPERR)
00127 #define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
00128 #endif /* FLASH_SR_OPERR */
00129 #define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
00130 #define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
00131 #define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
00132 #define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */
00133 #define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */
00134
00135 #define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup FLASH_Type_Program FLASH Type Program
00141   * @{
00142   */
00143 #define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
00144 #if defined (FLASH_OPTCR_PG_OTP)
00145 #define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
00146 #endif /* FLASH_OPTCR_PG_OTP */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup FLASH_Flag_definition FLASH Flag definition
00152   * @brief Flag definition
00153   * @{
00154   */
00155 #define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
00156 #define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
00157 #define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
00158 #define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
00159 #define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
00160 #define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
00161 #define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
00162 #define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
00163 #define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
00164 #if defined (FLASH_SR_OPERR)
00165 #define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
00166 #endif /* FLASH_SR_OPERR */
00167 #define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
00168 #define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
00169 #define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
00170 #define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
00171 #define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
00172 #define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
00173
00174 #define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
00175 #define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
00176 #define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
00177 #define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
00178 #define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
00179 #define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
00180 #define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
00181 #define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
00182 #define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
00183 #if defined (FLASH_SR_OPERR)
00184 #define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
00185 #endif /* FLASH_SR_OPERR */
00186 #define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
00187 #define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
00188 #define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
00189 #define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
00190 #define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
00191 #define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
00192
00193 #if defined (FLASH_SR_OPERR)
00194 #define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
00195                                            FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
00196                                            FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
00197                                            FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
00198                                            FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
00199 #else
00200 #define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
00201                                            FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
00202                                            FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
00203                                            FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
00204                                            FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
00205 #endif /* FLASH_SR_OPERR */
00206
00207 #define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
00208                                            FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
00209                                            FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
00210                                            FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
00211
00212 #define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
00213 #define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
00214 #define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
00215 #define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
00216 #define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
00217 #define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
00218 #define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
00219 #define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
00220 #define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
00221 #if defined (FLASH_SR_OPERR)
00222 #define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
00223 #endif /* FLASH_SR_OPERR */
00224 #define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
00225 #define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
00226 #define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
00227 #define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
00228 #define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
00229 #define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
00230
00231 #if defined (FLASH_SR_OPERR)
00232 #define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
00233                                            FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
00234                                            FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
00235                                            FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
00236                                            FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
00237 #else
00238 #define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
00239                                            FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
00240                                            FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
00241                                            FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
00242                                            FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
00243 #endif /* FLASH_SR_OPERR */
00244
00245 #define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
00246                                            FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
00247                                            FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
00248                                            FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
00254   * @brief FLASH Interrupt definition
00255   * @{
00256   */
00257 #define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
00258 #define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
00259 #define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
00260 #define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
00261 #define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
00262 #if defined (FLASH_CR_OPERRIE)
00263 #define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
00264 #endif /* FLASH_CR_OPERRIE */
00265 #define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
00266 #define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
00267 #define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
00268 #define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
00269 #define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
00270 #define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
00271
00272 #if defined (FLASH_CR_OPERRIE)
00273 #define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
00274                                             FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
00275                                             FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
00276                                             FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
00277                                             FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
00278                                             FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
00279 #else
00280 #define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
00281                                             FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
00282                                             FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
00283                                             FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
00284                                             FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
00285                                             FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
00286 #endif /* FLASH_CR_OPERRIE */
00287
00288 #define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
00289 #define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
00290 #define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
00291 #define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
00292 #define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
00293 #if defined (FLASH_CR_OPERRIE)
00294 #define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
00295 #endif /* FLASH_CR_OPERRIE */
00296 #define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
00297 #define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
00298 #define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
00299 #define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
00300 #define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
00301 #define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
00302
00303 #if defined (FLASH_CR_OPERRIE)
00304 #define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
00305                                             FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
00306                                             FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
00307                                             FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
00308                                             FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
00309                                             FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
00310 #else
00311 #define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
00312                                             FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
00313                                             FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
00314                                             FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
00315                                             FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
00316                                             FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
00317 #endif /* FLASH_CR_OPERRIE */
00318 /**
00319   * @}
00320   */
00321
00322 #if defined (FLASH_CR_PSIZE)
00323 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
00324   * @{
00325   */
00326 #define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */
00327 #define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
00328 #define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
00329 #define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
00330 /**
00331   * @}
00332   */
00333 #endif /* FLASH_CR_PSIZE */
00334
00335
00336 /** @defgroup FLASH_Keys FLASH Keys
00337   * @{
00338   */
00339 #define FLASH_KEY1                 0x45670123U
00340 #define FLASH_KEY2                 0xCDEF89ABU
00341 #define FLASH_OPT_KEY1             0x08192A3BU
00342 #define FLASH_OPT_KEY2             0x4C5D6E7FU
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup FLASH_Sectors FLASH Sectors
00348   * @{
00349   */
00350 #define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */
00351 #define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */
00352 #define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */
00353 #define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */
00354 #define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */
00355 #define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
00356 #define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
00357 #define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
00358 #if (FLASH_SECTOR_TOTAL == 128)
00359 #define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
00360 #define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
00361 #define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
00362 #define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
00363 #define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
00364 #define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
00365 #define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
00366 #define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
00367 #define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
00368 #define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
00369 #define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
00370 #define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
00371 #define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
00372 #define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
00373 #define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
00374 #define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
00375 #define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
00376 #define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
00377 #define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
00378 #define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
00379 #define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
00380 #define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
00381 #define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
00382 #define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
00383 #define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
00384 #define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
00385 #define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
00386 #define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
00387 #define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
00388 #define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
00389 #define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
00390 #define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
00391 #define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
00392 #define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
00393 #define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
00394 #define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
00395 #define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
00396 #define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
00397 #define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
00398 #define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
00399 #define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
00400 #define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
00401 #define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
00402 #define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
00403 #define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
00404 #define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
00405 #define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
00406 #define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
00407 #define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
00408 #define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
00409 #define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
00410 #define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
00411 #define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
00412 #define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
00413 #define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
00414 #define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
00415 #define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
00416 #define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
00417 #define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
00418 #define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
00419 #define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
00420 #define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
00421 #define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
00422 #define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
00423 #define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
00424 #define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
00425 #define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
00426 #define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
00427 #define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
00428 #define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
00429 #define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
00430 #define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
00431 #define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
00432 #define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
00433 #define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
00434 #define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
00435 #define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
00436 #define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
00437 #define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
00438 #define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
00439 #define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
00440 #define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
00441 #define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
00442 #define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
00443 #define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
00444 #define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
00445 #define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
00446 #define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
00447 #define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
00448 #define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
00449 #define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
00450 #define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
00451 #define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
00452 #define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
00453 #define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
00454 #define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
00455 #define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
00456 #define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
00457 #define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
00458 #define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
00459 #define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
00460 #define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
00461 #define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
00462 #define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
00463 #define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
00464 #define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
00465 #define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
00466 #define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
00467 #define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
00468 #define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
00469 #define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
00470 #define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
00471 #define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
00472 #define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
00473 #define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
00474 #define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
00475 #define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
00476 #define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
00477 #define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
00478 #define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
00479 #endif /* FLASH_SECTOR_TOTAL == 128 */
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /* Exported macro ------------------------------------------------------------*/
00489 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00490   * @{
00491   */
00492 /**
00493   * @brief  Set the FLASH Latency.
00494   * @param  __LATENCY__: FLASH Latency
00495   *         The value of this parameter depend on device used within the same series
00496   * @retval none
00497   */
00498 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
00499                   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
00500
00501 /**
00502   * @brief  Get the FLASH Latency.
00503   * @retval FLASH Latency
00504   *          The value of this parameter depend on device used within the same series
00505   */
00506 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00507
00508 /**
00509   * @brief  Enable the specified FLASH interrupt.
00510   * @param  __INTERRUPT__ : FLASH interrupt
00511   *   In case of Bank 1 This parameter can be any combination of the following values:
00512   *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
00513   *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
00514   *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
00515   *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
00516   *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
00517   *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
00518   *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
00519   *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
00520   *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
00521   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
00522   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
00523   *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
00524   *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
00525   *
00526   *   In case of Bank 2, this parameter can be any combination of the following values:
00527   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
00528   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
00529   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
00530   *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
00531   *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
00532   *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
00533   *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
00534   *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
00535   *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
00536   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
00537   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
00538   *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
00539   *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
00540   * @retval none
00541   */
00542
00543 #define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
00544
00545 #define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
00546
00547 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
00548                                                  __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
00549                                                  __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
00550
00551
00552 /**
00553   * @brief  Disable the specified FLASH interrupt.
00554   * @param  __INTERRUPT__ : FLASH interrupt
00555   *   In case of Bank 1 This parameter can be any combination of the following values:
00556   *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
00557   *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
00558   *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
00559   *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
00560   *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
00561   *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
00562   *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
00563   *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
00564   *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
00565   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
00566   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
00567   *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
00568   *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
00569   *
00570   *   In case of Bank 2, this parameter can be any combination of the following values:
00571   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
00572   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
00573   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
00574   *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
00575   *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
00576   *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
00577   *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
00578   *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
00579   *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
00580   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
00581   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
00582   *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
00583   *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
00584   * @retval none
00585   */
00586
00587 #define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
00588
00589 #define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
00590
00591 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
00592                                                 __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
00593                                                 __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
00594
00595
00596 /**
00597   * @brief  Checks whether the specified FLASH flag is set or not.
00598   * @param  __FLAG__: specifies the FLASH flag to check.
00599   *   In case of Bank 1 This parameter can be one of the following values :
00600   *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
00601   *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
00602   *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
00603   *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
00604   *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
00605   *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
00606   *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
00607   *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
00608   *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
00609   *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
00610   *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
00611   *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
00612   *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
00613   *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
00614   *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
00615   *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
00616   *
00617   *   In case of Bank 2 This parameter can be one of the following values :
00618   *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
00619   *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
00620   *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
00621   *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
00622   *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
00623   *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
00624   *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
00625   *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
00626   *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
00627   *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
00628   *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
00629   *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
00630   *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
00631   *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
00632   *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
00633   *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
00634   * @retval The new state of FLASH_FLAG (SET or RESET).
00635   */
00636 #define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
00637
00638 #define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
00639
00640 #define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
00641                                                   __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
00642
00643
00644 /**
00645   * @brief  Clear the specified FLASH flag.
00646   * @param  __FLAG__: specifies the FLASH flags to clear.
00647   *    In case of Bank 1, this parameter can be any combination of the following values:
00648   *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
00649   *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
00650   *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
00651   *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
00652   *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
00653   *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
00654   *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
00655   *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
00656   *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
00657   *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
00658   *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
00659   *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
00660   *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
00661   *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
00662   *
00663   *   In case of Bank 2, this parameter can be any combination of the following values :
00664   *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
00665   *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
00666   *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
00667   *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
00668   *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
00669   *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
00670   *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
00671   *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
00672   *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
00673   *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
00674   *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
00675   *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
00676   *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
00677   *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
00678   * @retval none
00679   */
00680
00681 #define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
00682
00683 #define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
00684
00685 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
00686                                                    __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
00687
00688 /**
00689   * @}
00690   */
00691
00692 /* Include FLASH HAL Extension module */
00693 #include "stm32h7xx_hal_flash_ex.h"
00694
00695 /* Exported functions --------------------------------------------------------*/
00696 /** @addtogroup FLASH_Exported_Functions
00697   * @{
00698   */
00699 /** @addtogroup FLASH_Exported_Functions_Group1
00700   * @{
00701   */
00702 /* Program operation functions  ***********************************************/
00703 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
00704 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
00705 /* FLASH IRQ handler method */
00706 void HAL_FLASH_IRQHandler(void);
00707 /* Callbacks in non blocking modes */
00708 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00709 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00710 /**
00711   * @}
00712   */
00713
00714 /** @addtogroup FLASH_Exported_Functions_Group2
00715   * @{
00716   */
00717 /* Peripheral Control functions  **********************************************/
00718 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00719 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00720 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00721 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00722 /* Option bytes control */
00723 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00724 /**
00725   * @}
00726   */
00727
00728 /** @addtogroup FLASH_Exported_Functions_Group3
00729   * @{
00730   */
00731 /* Peripheral State functions  ************************************************/
00732 uint32_t HAL_FLASH_GetError(void);
00733 /**
00734   * @}
00735   */
00736
00737 /**
00738   * @}
00739   */
00740 /* Private types -------------------------------------------------------------*/
00741 /* Private variables ---------------------------------------------------------*/
00742 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00743   * @{
00744   */
00745 extern FLASH_ProcessTypeDef pFlash;
00746 /**
00747   * @}
00748   */
00749 /* Private constants ---------------------------------------------------------*/
00750 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00751   * @{
00752   */
00753
00754 /**
00755   * @}
00756   */
00757
00758 /* Private macros ------------------------------------------------------------*/
00759 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00760   * @{
00761   */
00762
00763 #if defined (FLASH_OPTCR_PG_OTP)
00764 #define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
00765                                           ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
00766 #else
00767 #define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
00768 #endif /* FLASH_OPTCR_PG_OTP */
00769
00770 #define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
00771
00772 #define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
00773
00774 #define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
00775
00776 #define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
00777
00778 #define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
00779 #define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
00780
00781 #if defined (FLASH_OPTCR_PG_OTP)
00782 #define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
00783 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
00784                                                  IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
00785                                                  IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
00786 #else
00787 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
00788                                                  IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
00789 #endif /* FLASH_OPTCR_PG_OTP */
00790
00791 #define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
00792
00793 #define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
00794                                             ((BANK) == FLASH_BANK_2)  || \
00795                                             ((BANK) == FLASH_BANK_BOTH))
00796
00797 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
00798                                             ((BANK) == FLASH_BANK_2))
00799
00800
00801 /**
00802   * @}
00803   */
00804 /* Private functions ---------------------------------------------------------*/
00805 /** @defgroup FLASH_Private_Functions FLASH Private functions
00806   * @{
00807   */
00808 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
00809 HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
00810 HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
00811 /**
00812   * @}
00813   */
00814
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 #ifdef __cplusplus
00824 }
00825 #endif
00826
00827 #endif /* STM32H7xx_HAL_FLASH_H */
00828
00829 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash_ex.c Source File

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stm32h7xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the FLASH extension peripheral:
00008   *           + Extended programming operations functions
00009   *
00010  @verbatim
00011  ==============================================================================
00012                    ##### Flash Extension features #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
00016        devices contains the following additional features
00017
00018        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
00019            capability (RWW)
00020        (+) Dual bank memory organization
00021        (+) PCROP protection for all banks
00022        (+) Global readout protection (RDP)
00023        (+) Write protection
00024        (+) Secure access only protection
00025        (+) Bank / register swapping
00026        (+) Cyclic Redundancy Check (CRC)
00027
00028                         ##### How to use this driver #####
00029  ==============================================================================
00030   [..] This driver provides functions to configure and program the FLASH memory
00031        of all STM32H7xx devices. It includes
00032       (#) FLASH Memory Erase functions:
00033            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00034                 HAL_FLASH_Lock() functions
00035            (++) Erase function: Sector erase, bank erase and dual-bank mass erase
00036            (++) There are two modes of erase :
00037              (+++) Polling Mode using HAL_FLASHEx_Erase()
00038              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00039
00040       (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
00041         (++) Set/Reset the write protection per bank
00042         (++) Set the Read protection Level
00043         (++) Set the BOR level
00044         (++) Program the user Option Bytes
00045         (++) PCROP protection configuration and control per bank
00046         (++) Secure area configuration and control per bank
00047         (++) Core Boot address configuration
00048
00049       (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
00050           HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
00051
00052       (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
00053           (++) Enable CRC feature
00054           (++) Program the desired burst size
00055           (++) Define the user Flash Area on which the CRC has be computed
00056           (++) Perform the CRC computation
00057           (++) Disable CRC feature
00058
00059  @endverbatim
00060   ******************************************************************************
00061   * @attention
00062   *
00063   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00064   * All rights reserved.</center></h2>
00065   *
00066   * This software component is licensed by ST under BSD 3-Clause license,
00067   * the "License"; You may not use this file except in compliance with the
00068   * License. You may obtain a copy of the License at:
00069   *                       opensource.org/licenses/BSD-3-Clause
00070   *
00071   ******************************************************************************
00072   */
00073
00074 /* Includes ------------------------------------------------------------------*/
00075 #include "stm32h7xx_hal.h"
00076
00077 /** @addtogroup STM32H7xx_HAL_Driver
00078   * @{
00079   */
00080
00081 /** @defgroup FLASHEx  FLASHEx
00082   * @brief FLASH HAL Extension module driver
00083   * @{
00084   */
00085
00086 #ifdef HAL_FLASH_MODULE_ENABLED
00087
00088 /* Private typedef -----------------------------------------------------------*/
00089 /* Private define ------------------------------------------------------------*/
00090 /** @addtogroup FLASHEx_Private_Constants
00091   * @{
00092   */
00093 #define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
00094
00095 /**
00096   * @}
00097   */
00098 /* Private macro -------------------------------------------------------------*/
00099 /* Private variables ---------------------------------------------------------*/
00100 /* Private function prototypes -----------------------------------------------*/
00101 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00102   * @{
00103   */
00104 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
00105 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
00106 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
00107 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
00108 static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
00109 static uint32_t FLASH_OB_GetRDP(void);
00110 static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
00111 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
00112 static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
00113 static uint32_t FLASH_OB_GetBOR(void);
00114 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
00115 static uint32_t FLASH_OB_GetUser(void);
00116 static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
00117 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
00118 static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
00119 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
00120 static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
00121 static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
00122
00123 #if defined (DUAL_CORE)
00124 static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
00125 static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
00126 #endif /* DUAL_CORE */
00127
00128 #if defined (FLASH_OTPBL_LOCKBL)
00129 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
00130 static uint32_t FLASH_OB_OTP_GetLock(void);
00131 #endif /* FLASH_OTPBL_LOCKBL */
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported functions ---------------------------------------------------------*/
00137 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00138   * @{
00139   */
00140
00141 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00142  *  @brief   Extended IO operation functions
00143  *
00144 @verbatim
00145  ===============================================================================
00146                 ##### Extended programming operation functions #####
00147  ===============================================================================
00148     [..]
00149     This subsection provides a set of functions allowing to manage the Extension FLASH
00150     programming operations Operations.
00151
00152 @endverbatim
00153   * @{
00154   */
00155 /**
00156   * @brief  Perform a mass erase or erase the specified FLASH memory sectors
00157   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00158   *         contains the configuration information for the erasing.
00159   *
00160   * @param[out]  SectorError pointer to variable  that contains the configuration
00161   *          information on faulty sector in case of error (0xFFFFFFFF means that all
00162   *          the sectors have been correctly erased)
00163   *
00164   * @retval HAL Status
00165   */
00166 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
00167 {
00168   HAL_StatusTypeDef status = HAL_OK;
00169   uint32_t sector_index;
00170
00171   /* Check the parameters */
00172   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00173   assert_param(IS_FLASH_BANK(pEraseInit->Banks));
00174
00175   /* Process Locked */
00176   __HAL_LOCK(&pFlash);
00177
00178   /* Reset error code */
00179   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00180
00181   /* Wait for last operation to be completed on Bank1 */
00182   if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00183   {
00184     if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
00185     {
00186       status = HAL_ERROR;
00187     }
00188   }
00189
00190   /* Wait for last operation to be completed on Bank2 */
00191   if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00192   {
00193     if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
00194     {
00195       status = HAL_ERROR;
00196     }
00197   }
00198
00199   if(status == HAL_OK)
00200   {
00201     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00202     {
00203       /* Mass erase to be done */
00204       FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
00205
00206       /* Wait for last operation to be completed */
00207       if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00208       {
00209         if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
00210         {
00211           status = HAL_ERROR;
00212         }
00213         /* if the erase operation is completed, disable the Bank1 BER Bit */
00214         FLASH->CR1 &= (~FLASH_CR_BER);
00215       }
00216       if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00217       {
00218         if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
00219         {
00220           status = HAL_ERROR;
00221         }
00222         /* if the erase operation is completed, disable the Bank2 BER Bit */
00223         FLASH->CR2 &= (~FLASH_CR_BER);
00224       }
00225     }
00226     else
00227     {
00228       /*Initialization of SectorError variable*/
00229       *SectorError = 0xFFFFFFFFU;
00230
00231       /* Erase by sector by sector to be done*/
00232       for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
00233       {
00234         FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
00235
00236         if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00237         {
00238           /* Wait for last operation to be completed */
00239           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00240
00241           /* If the erase operation is completed, disable the SER Bit */
00242           FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
00243         }
00244         if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00245         {
00246           /* Wait for last operation to be completed */
00247           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00248
00249           /* If the erase operation is completed, disable the SER Bit */
00250           FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
00251         }
00252
00253         if(status != HAL_OK)
00254         {
00255           /* In case of error, stop erase procedure and return the faulty sector */
00256           *SectorError = sector_index;
00257           break;
00258         }
00259       }
00260     }
00261   }
00262
00263   /* Process Unlocked */
00264   __HAL_UNLOCK(&pFlash);
00265
00266   return status;
00267 }
00268
00269 /**
00270   * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
00271   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00272   *         contains the configuration information for the erasing.
00273   *
00274   * @retval HAL Status
00275   */
00276 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00277 {
00278   HAL_StatusTypeDef status = HAL_OK;
00279
00280   /* Check the parameters */
00281   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00282   assert_param(IS_FLASH_BANK(pEraseInit->Banks));
00283
00284   /* Process Locked */
00285   __HAL_LOCK(&pFlash);
00286
00287   /* Reset error code */
00288   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00289
00290   /* Wait for last operation to be completed */
00291   if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00292   {
00293     if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
00294     {
00295       status = HAL_ERROR;
00296     }
00297   }
00298
00299   if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00300   {
00301     if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
00302     {
00303       status = HAL_ERROR;
00304     }
00305   }
00306
00307   if (status != HAL_OK)
00308   {
00309     /* Process Unlocked */
00310     __HAL_UNLOCK(&pFlash);
00311   }
00312   else
00313   {
00314     if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00315     {
00316       /* Enable End of Operation and Error interrupts for Bank 1 */
00317 #if defined (FLASH_CR_OPERRIE)
00318       __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00319                                   FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00320 #else
00321       __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00322                                   FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
00323 #endif /* FLASH_CR_OPERRIE */
00324     }
00325     if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00326     {
00327       /* Enable End of Operation and Error interrupts for Bank 2 */
00328 #if defined (FLASH_CR_OPERRIE)
00329       __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00330                                   FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00331 #else
00332       __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00333                                   FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
00334 #endif /* FLASH_CR_OPERRIE */
00335     }
00336
00337     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00338     {
00339       /*Mass erase to be done*/
00340       if(pEraseInit->Banks == FLASH_BANK_1)
00341       {
00342         pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
00343       }
00344       else if(pEraseInit->Banks == FLASH_BANK_2)
00345       {
00346         pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
00347       }
00348       else
00349       {
00350         pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
00351       }
00352
00353       FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
00354     }
00355     else
00356     {
00357       /* Erase by sector to be done */
00358       if(pEraseInit->Banks == FLASH_BANK_1)
00359       {
00360         pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
00361       }
00362       else
00363       {
00364         pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
00365       }
00366
00367       pFlash.NbSectorsToErase = pEraseInit->NbSectors;
00368       pFlash.Sector = pEraseInit->Sector;
00369       pFlash.VoltageForErase = pEraseInit->VoltageRange;
00370
00371       /* Erase first sector and wait for IT */
00372       FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
00373     }
00374   }
00375
00376   return status;
00377 }
00378
00379 /**
00380   * @brief  Program option bytes
00381   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00382   *         contains the configuration information for the programming.
00383   *
00384   * @retval HAL Status
00385   */
00386 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00387 {
00388   HAL_StatusTypeDef status;
00389
00390   /* Check the parameters */
00391   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00392
00393   /* Process Locked */
00394   __HAL_LOCK(&pFlash);
00395
00396   /* Reset Error Code */
00397   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00398
00399   /* Wait for last operation to be completed */
00400   if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
00401   {
00402     status = HAL_ERROR;
00403   }
00404   else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
00405   {
00406     status = HAL_ERROR;
00407   }
00408   else
00409   {
00410     status = HAL_OK;
00411   }
00412
00413   if(status == HAL_OK)
00414   {
00415     /*Write protection configuration*/
00416     if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00417     {
00418       assert_param(IS_WRPSTATE(pOBInit->WRPState));
00419
00420       if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00421       {
00422         /*Enable of Write protection on the selected Sector*/
00423         FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
00424       }
00425       else
00426       {
00427         /*Disable of Write protection on the selected Sector*/
00428         FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
00429       }
00430     }
00431
00432     /* Read protection configuration */
00433     if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
00434     {
00435       /* Configure the Read protection level */
00436       FLASH_OB_RDPConfig(pOBInit->RDPLevel);
00437     }
00438
00439     /* User Configuration */
00440     if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
00441     {
00442       /* Configure the user option bytes */
00443       FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
00444     }
00445
00446     /* PCROP Configuration */
00447     if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
00448     {
00449       assert_param(IS_FLASH_BANK(pOBInit->Banks));
00450
00451       /*Configure the Proprietary code readout protection */
00452       FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
00453     }
00454
00455     /* BOR Level configuration */
00456     if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
00457     {
00458       FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
00459     }
00460
00461 #if defined(DUAL_CORE)
00462     /* CM7 Boot Address  configuration */
00463     if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
00464     {
00465       FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
00466     }
00467
00468     /* CM4 Boot Address  configuration */
00469     if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
00470     {
00471       FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
00472     }
00473 #else /* Single Core*/
00474     /* Boot Address  configuration */
00475     if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
00476     {
00477       FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
00478     }
00479 #endif /*DUAL_CORE*/
00480
00481     /* Secure area configuration */
00482     if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
00483     {
00484       FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
00485     }
00486
00487 #if defined(FLASH_OTPBL_LOCKBL)
00488     /* OTP Block Lock configuration */
00489     if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
00490     {
00491       FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
00492     }
00493 #endif /* FLASH_OTPBL_LOCKBL */
00494   }
00495
00496   /* Process Unlocked */
00497   __HAL_UNLOCK(&pFlash);
00498
00499   return status;
00500 }
00501
00502 /**
00503   * @brief Get the Option byte configuration
00504   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00505   *         contains the configuration information for the programming.
00506   * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
00507   *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
00508   *
00509   * @retval None
00510   */
00511 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00512 {
00513   pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
00514
00515   /* Get Read protection level */
00516   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00517
00518   /* Get the user option bytes */
00519   pOBInit->USERConfig = FLASH_OB_GetUser();
00520
00521   /*Get BOR Level*/
00522   pOBInit->BORLevel = FLASH_OB_GetBOR();
00523
00524   if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
00525   {
00526     pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
00527
00528     /* Get write protection on the selected area */
00529     FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
00530
00531     /* Get the Proprietary code readout protection */
00532     FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
00533
00534     /*Get Bank Secure area*/
00535     FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
00536   }
00537
00538   /*Get Boot Address*/
00539   FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
00540 #if defined(DUAL_CORE)
00541   pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
00542
00543   /*Get CM4 Boot Address*/
00544   FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
00545 #else
00546   pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
00547 #endif /*DUAL_CORE*/
00548
00549 #if defined (FLASH_OTPBL_LOCKBL)
00550   pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
00551
00552   /* Get OTP Block Lock */
00553   pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
00554 #endif /* FLASH_OTPBL_LOCKBL */
00555 }
00556
00557 /**
00558   * @brief  Unlock the FLASH Bank1 control registers access
00559   * @retval HAL Status
00560   */
00561 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
00562 {
00563   if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
00564   {
00565     /* Authorize the FLASH Bank1 Registers access */
00566     WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
00567     WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
00568
00569     /* Verify Flash Bank1 is unlocked */
00570     if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
00571     {
00572       return HAL_ERROR;
00573     }
00574   }
00575
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @brief  Locks the FLASH Bank1 control registers access
00581   * @retval HAL Status
00582   */
00583 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
00584 {
00585   /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
00586   SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
00587   return HAL_OK;
00588 }
00589
00590 /**
00591   * @brief  Unlock the FLASH Bank2 control registers access
00592   * @retval HAL Status
00593   */
00594 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
00595 {
00596   if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
00597   {
00598     /* Authorize the FLASH Bank2 Registers access */
00599     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
00600     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
00601
00602     /* Verify Flash Bank1 is unlocked */
00603     if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
00604     {
00605       return HAL_ERROR;
00606     }
00607   }
00608
00609   return HAL_OK;
00610 }
00611
00612 /**
00613   * @brief  Locks the FLASH Bank2 control registers access
00614   * @retval HAL Status
00615   */
00616 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
00617 {
00618   /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
00619   SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
00620   return HAL_OK;
00621 }
00622
00623 /*
00624   * @brief  Perform a CRC computation on the specified FLASH memory area
00625   * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
00626   *         contains the configuration information for the CRC computation.
00627   * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
00628   * @note   The application should avoid running a CRC on PCROP or secure-only
00629   *         user Flash memory area since it may alter the expected CRC value.
00630   *         A special error flag (CRC read error: CRCRDERR) can be used to
00631   *         detect such a case.
00632   * @retval HAL Status
00633 */
00634 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
00635 {
00636   HAL_StatusTypeDef status;
00637   uint32_t sector_index;
00638
00639   /* Check the parameters */
00640   assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
00641   assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
00642
00643   /* Wait for OB change operation to be completed */
00644   status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00645
00646   if (status == HAL_OK)
00647   {
00648     if (pCRCInit->Bank == FLASH_BANK_1)
00649     {
00650       /* Enable CRC feature */
00651       FLASH->CR1 |= FLASH_CR_CRC_EN;
00652
00653       /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
00654       FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
00655
00656       /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
00657       FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
00658
00659       if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
00660       {
00661         /* Clear sectors list */
00662         FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
00663
00664         /* Select CRC sectors */
00665         for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
00666         {
00667           FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
00668         }
00669       }
00670       else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
00671       {
00672         /* Enable Bank 1 CRC select bit */
00673         FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
00674       }
00675       else
00676       {
00677         /* Select CRC start and end addresses */
00678         FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
00679       }
00680
00681       /* Start the CRC calculation */
00682       FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
00683
00684       /* Wait on CRC busy flag */
00685       status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00686
00687       /* Return CRC result */
00688       (*CRC_Result) = FLASH->CRCDATA;
00689
00690       /* Disable CRC feature */
00691       FLASH->CR1 &= (~FLASH_CR_CRC_EN);
00692
00693       /* Clear CRC flags */
00694       __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
00695     }
00696     else
00697     {
00698       /* Enable CRC feature */
00699       FLASH->CR2 |= FLASH_CR_CRC_EN;
00700
00701       /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
00702       FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
00703
00704       /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
00705       FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
00706
00707       if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
00708       {
00709         /* Clear sectors list */
00710         FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
00711
00712         /* Add CRC sectors */
00713         for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
00714         {
00715           FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
00716         }
00717       }
00718       else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
00719       {
00720         /* Enable Bank 2 CRC select bit */
00721         FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
00722       }
00723       else
00724       {
00725         /* Select CRC start and end addresses */
00726         FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
00727       }
00728
00729       /* Start the CRC calculation */
00730       FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
00731
00732       /* Wait on CRC busy flag */
00733       status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00734
00735       /* Return CRC result */
00736       (*CRC_Result) = FLASH->CRCDATA;
00737
00738       /* Disable CRC feature */
00739       FLASH->CR2 &= (~FLASH_CR_CRC_EN);
00740
00741       /* Clear CRC flags */
00742       __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
00743     }
00744   }
00745
00746   return status;
00747 }
00748
00749 /**
00750   * @}
00751   */
00752
00753 /**
00754   * @}
00755   */
00756
00757 /* Private functions ---------------------------------------------------------*/
00758
00759 /** @addtogroup FLASHEx_Private_Functions
00760   * @{
00761   */
00762
00763 /**
00764   * @brief  Mass erase of FLASH memory
00765   * @param  VoltageRange The device program/erase parallelism.
00766   *          This parameter can be one of the following values:
00767   *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
00768   *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
00769   *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
00770   *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
00771   *
00772   * @param  Banks Banks to be erased
00773   *          This parameter can be one of the following values:
00774   *            @arg FLASH_BANK_1: Bank1 to be erased
00775   *            @arg FLASH_BANK_2: Bank2 to be erased
00776   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00777   *
00778   * @retval HAL Status
00779   */
00780 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
00781 {
00782   /* Check the parameters */
00783 #if defined (FLASH_CR_PSIZE)
00784   assert_param(IS_VOLTAGERANGE(VoltageRange));
00785 #else
00786   UNUSED(VoltageRange);
00787 #endif /* FLASH_CR_PSIZE */
00788   assert_param(IS_FLASH_BANK(Banks));
00789
00790   /* Flash Mass Erase */
00791   if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
00792   {
00793 #if defined (FLASH_CR_PSIZE)
00794     /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
00795     FLASH->CR1 &= (~FLASH_CR_PSIZE);
00796     FLASH->CR2 &= (~FLASH_CR_PSIZE);
00797
00798     /* Set voltage range */
00799     FLASH->CR1 |= VoltageRange;
00800     FLASH->CR2 |= VoltageRange;
00801 #endif /* FLASH_CR_PSIZE */
00802
00803     /* Set Mass Erase Bit */
00804     FLASH->OPTCR |= FLASH_OPTCR_MER;
00805   }
00806   else
00807   {
00808     /* Proceed to erase Flash Bank  */
00809     if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00810     {
00811 #if defined (FLASH_CR_PSIZE)
00812       /* Set Program/erase VoltageRange for Bank1 */
00813       FLASH->CR1 &= (~FLASH_CR_PSIZE);
00814       FLASH->CR1 |=  VoltageRange;
00815 #endif /* FLASH_CR_PSIZE */
00816
00817       /* Erase Bank1 */
00818       FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
00819     }
00820     if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00821     {
00822 #if defined (FLASH_CR_PSIZE)
00823       /* Set Program/erase VoltageRange for Bank2 */
00824       FLASH->CR2 &= (~FLASH_CR_PSIZE);
00825       FLASH->CR2 |= VoltageRange;
00826 #endif /* FLASH_CR_PSIZE */
00827
00828       /* Erase Bank2 */
00829       FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
00830     }
00831   }
00832 }
00833
00834 /**
00835   * @brief  Erase the specified FLASH memory sector
00836   * @param  Sector FLASH sector to erase
00837   *          This parameter can be a value of @ref FLASH_Sectors
00838   * @param  Banks Banks to be erased
00839   *          This parameter can be one of the following values:
00840   *            @arg FLASH_BANK_1: Bank1 to be erased
00841   *            @arg FLASH_BANK_2: Bank2 to be erased
00842   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00843   * @param  VoltageRange The device program/erase parallelism.
00844   *          This parameter can be one of the following values:
00845   *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
00846   *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
00847   *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
00848   *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
00849   *
00850   * @retval None
00851   */
00852 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
00853 {
00854   assert_param(IS_FLASH_SECTOR(Sector));
00855   assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
00856 #if defined (FLASH_CR_PSIZE)
00857   assert_param(IS_VOLTAGERANGE(VoltageRange));
00858 #else
00859   UNUSED(VoltageRange);
00860 #endif /* FLASH_CR_PSIZE */
00861
00862   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00863   {
00864 #if defined (FLASH_CR_PSIZE)
00865     /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
00866     FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
00867
00868     FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
00869 #else
00870     /* Reset Sector Number for Bank1 */
00871     FLASH->CR1 &= ~(FLASH_CR_SNB);
00872
00873     FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
00874 #endif /* FLASH_CR_PSIZE */
00875   }
00876
00877   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00878   {
00879 #if defined (FLASH_CR_PSIZE)
00880     /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
00881     FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
00882
00883     FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
00884 #else
00885     /* Reset Sector Number for Bank2 */
00886     FLASH->CR2 &= ~(FLASH_CR_SNB);
00887
00888     FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
00889 #endif /* FLASH_CR_PSIZE */
00890   }
00891 }
00892
00893 /**
00894   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
00895   * @param  WRPSector specifies the sector(s) to be write protected.
00896   *          This parameter can be one of the following values:
00897   *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
00898   *
00899   * @param  Banks the specific bank to apply WRP sectors
00900   *          This parameter can be one of the following values:
00901   *            @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
00902   *            @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
00903   *            @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
00904   *
00905   * @retval HAL FLASH State
00906   */
00907 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
00908 {
00909   /* Check the parameters */
00910   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00911   assert_param(IS_FLASH_BANK(Banks));
00912
00913   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00914   {
00915     /* Enable Write Protection for bank 1 */
00916     FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
00917   }
00918
00919   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00920   {
00921     /* Enable Write Protection for bank 2 */
00922     FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
00923   }
00924 }
00925
00926 /**
00927   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
00928   * @param  WRPSector specifies the sector(s) to disable write protection.
00929   *          This parameter can be one of the following values:
00930   *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
00931   *
00932   * @param  Banks the specific bank to apply WRP sectors
00933   *          This parameter can be one of the following values:
00934   *            @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
00935   *            @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
00936   *            @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
00937   *
00938   * @retval HAL FLASH State
00939   */
00940 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
00941 {
00942   /* Check the parameters */
00943   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00944   assert_param(IS_FLASH_BANK(Banks));
00945
00946   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00947   {
00948     /* Disable Write Protection for bank 1 */
00949     FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
00950   }
00951
00952   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00953   {
00954     /* Disable Write Protection for bank 2 */
00955     FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
00956   }
00957 }
00958
00959 /**
00960   * @brief  Get the write protection of the given bank 1 or bank 2 sectors
00961   * @param  WRPState gives the write protection state on the given bank.
00962   *          This parameter can be one of the following values:
00963   *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
00964
00965   * @param  WRPSector gives the write protected sector(s) on the given bank .
00966   *          This parameter can be one of the following values:
00967   *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
00968   *
00969   * @param  Bank the specific bank to apply WRP sectors
00970   *          This parameter can be exclusively one of the following values:
00971   *            @arg FLASH_BANK_1: Get bank1 WRP sectors
00972   *            @arg FLASH_BANK_2: Get bank2 WRP sectors
00973   *            @arg FLASH_BANK_BOTH: note allowed in this functions
00974   *
00975   * @retval HAL FLASH State
00976   */
00977 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
00978 {
00979   uint32_t regvalue = 0U;
00980
00981   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
00982   {
00983     regvalue = FLASH->WPSN_CUR1;
00984   }
00985
00986   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
00987   {
00988     regvalue = FLASH->WPSN_CUR2;
00989   }
00990
00991   (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
00992
00993   if(*WRPSector == 0U)
00994   {
00995     (*WRPState) = OB_WRPSTATE_DISABLE;
00996   }
00997   else
00998   {
00999     (*WRPState) = OB_WRPSTATE_ENABLE;
01000   }
01001 }
01002
01003 /**
01004   * @brief  Set the read protection level.
01005   *
01006   * @note   To configure the RDP level, the option lock bit OPTLOCK must be
01007   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
01008   * @note   To validate the RDP level, the option bytes must be reloaded
01009   *         through the call of the HAL_FLASH_OB_Launch() function.
01010   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
01011   *         to go back to level 1 or 0 !!!
01012   *
01013   * @param  RDPLevel specifies the read protection level.
01014   *         This parameter can be one of the following values:
01015   *            @arg OB_RDP_LEVEL_0: No protection
01016   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
01017   *            @arg OB_RDP_LEVEL_2: Full chip protection
01018   *
01019   * @retval HAL status
01020   */
01021 static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
01022 {
01023   /* Check the parameters */
01024   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
01025
01026   /* Configure the RDP level in the option bytes register */
01027   MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
01028 }
01029
01030 /**
01031   * @brief  Get the read protection level.
01032   * @retval RDPLevel specifies the read protection level.
01033   *         This return value can be one of the following values:
01034   *            @arg OB_RDP_LEVEL_0: No protection
01035   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
01036   *            @arg OB_RDP_LEVEL_2: Full chip protection
01037   */
01038 static uint32_t FLASH_OB_GetRDP(void)
01039 {
01040   uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
01041
01042   if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
01043   {
01044     return (OB_RDP_LEVEL_1);
01045   }
01046   else
01047   {
01048     return rdp_level;
01049   }
01050 }
01051
01052 #if defined(DUAL_CORE)
01053 /**
01054   * @brief  Program the FLASH User Option Byte.
01055   *
01056   * @note   To configure the user option bytes, the option lock bit OPTLOCK must
01057   *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
01058   *
01059   * @note   To validate the user option bytes, the option bytes must be reloaded
01060   *         through the call of the HAL_FLASH_OB_Launch() function.
01061   *
01062   * @param  UserType The FLASH User Option Bytes to be modified :
01063   *                   a combination of @ref FLASHEx_OB_USER_Type
01064   *
01065   * @param  UserConfig The FLASH User Option Bytes values:
01066   *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
01067   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
01068   *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
01069   *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
01070   *
01071   * @retval HAL status
01072   */
01073 #else
01074 /**
01075   * @brief  Program the FLASH User Option Byte.
01076   *
01077   * @note   To configure the user option bytes, the option lock bit OPTLOCK must
01078   *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
01079   *
01080   * @note   To validate the user option bytes, the option bytes must be reloaded
01081   *         through the call of the HAL_FLASH_OB_Launch() function.
01082   *
01083   * @param  UserType The FLASH User Option Bytes to be modified :
01084   *                   a combination of @arg FLASHEx_OB_USER_Type
01085   *
01086   * @param  UserConfig The FLASH User Option Bytes values:
01087   *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
01088   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
01089   *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
01090   *
01091   * @retval HAL status
01092   */
01093 #endif /*DUAL_CORE*/
01094 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
01095 {
01096   uint32_t optr_reg_val = 0;
01097   uint32_t optr_reg_mask = 0;
01098
01099   /* Check the parameters */
01100   assert_param(IS_OB_USER_TYPE(UserType));
01101
01102   if((UserType & OB_USER_IWDG1_SW) != 0U)
01103   {
01104     /* IWDG_HW option byte should be modified */
01105     assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
01106
01107     /* Set value and mask for IWDG_HW option byte */
01108     optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
01109     optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
01110   }
01111 #if defined(DUAL_CORE)
01112   if((UserType & OB_USER_IWDG2_SW) != 0U)
01113   {
01114     /* IWDG2_SW option byte should be modified */
01115     assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
01116
01117     /* Set value and mask for IWDG2_SW option byte */
01118     optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
01119     optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
01120   }
01121 #endif /*DUAL_CORE*/
01122   if((UserType & OB_USER_NRST_STOP_D1) != 0U)
01123   {
01124     /* NRST_STOP option byte should be modified */
01125     assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
01126
01127     /* Set value and mask for NRST_STOP option byte */
01128     optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
01129     optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
01130   }
01131
01132   if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
01133   {
01134     /* NRST_STDBY option byte should be modified */
01135     assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
01136
01137     /* Set value and mask for NRST_STDBY option byte */
01138     optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
01139     optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
01140   }
01141
01142   if((UserType & OB_USER_IWDG_STOP) != 0U)
01143   {
01144     /* IWDG_STOP option byte should be modified */
01145     assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
01146
01147     /* Set value and mask for IWDG_STOP option byte */
01148     optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
01149     optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
01150   }
01151
01152   if((UserType & OB_USER_IWDG_STDBY) != 0U)
01153   {
01154     /* IWDG_STDBY option byte should be modified */
01155     assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
01156
01157     /* Set value and mask for IWDG_STDBY option byte */
01158     optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
01159     optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
01160   }
01161
01162   if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
01163   {
01164     /* ST_RAM_SIZE option byte should be modified */
01165     assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
01166
01167     /* Set value and mask for ST_RAM_SIZE option byte */
01168     optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
01169     optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
01170   }
01171
01172   if((UserType & OB_USER_SECURITY) != 0U)
01173   {
01174     /* SECURITY option byte should be modified */
01175     assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
01176
01177     /* Set value and mask for SECURITY option byte */
01178     optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
01179     optr_reg_mask |= FLASH_OPTSR_SECURITY;
01180   }
01181
01182 #if defined(DUAL_CORE)
01183   if((UserType & OB_USER_BCM4) != 0U)
01184   {
01185     /* BCM4 option byte should be modified */
01186     assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
01187
01188     /* Set value and mask for BCM4 option byte */
01189     optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
01190     optr_reg_mask |= FLASH_OPTSR_BCM4;
01191   }
01192
01193   if((UserType & OB_USER_BCM7) != 0U)
01194   {
01195     /* BCM7 option byte should be modified */
01196     assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
01197
01198     /* Set value and mask for BCM7 option byte */
01199     optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
01200     optr_reg_mask |= FLASH_OPTSR_BCM7;
01201   }
01202
01203   if((UserType & OB_USER_NRST_STOP_D2) != 0U)
01204   {
01205     /* NRST_STOP option byte should be modified */
01206     assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
01207
01208     /* Set value and mask for NRST_STOP option byte */
01209     optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
01210     optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
01211   }
01212
01213   if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
01214   {
01215     /* NRST_STDBY option byte should be modified */
01216     assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
01217
01218     /* Set value and mask for NRST_STDBY option byte */
01219     optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
01220     optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
01221   }
01222 #endif /* DUAL_CORE */
01223   if((UserType & OB_USER_SWAP_BANK) != 0U)
01224   {
01225     /* SWAP_BANK_OPT option byte should be modified */
01226     assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
01227
01228     /* Set value and mask for SWAP_BANK_OPT option byte */
01229     optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
01230     optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
01231   }
01232
01233   if((UserType & OB_USER_IOHSLV) != 0U)
01234   {
01235     /* IOHSLV_OPT option byte should be modified */
01236     assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
01237
01238     /* Set value and mask for IOHSLV_OPT option byte */
01239     optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
01240     optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
01241   }
01242
01243 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
01244   if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
01245   {
01246     /* VDDMMC_HSLV option byte should be modified */
01247     assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
01248
01249     /* Set value and mask for VDDMMC_HSLV option byte */
01250     optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
01251     optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
01252   }
01253 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
01254
01255   /* Configure the option bytes register */
01256   MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
01257 }
01258
01259 #if defined(DUAL_CORE)
01260 /**
01261   * @brief  Return the FLASH User Option Byte value.
01262   * @retval The FLASH User Option Bytes values
01263   *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
01264   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
01265   *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
01266   *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
01267   */
01268 #else
01269 /**
01270   * @brief  Return the FLASH User Option Byte value.
01271   * @retval The FLASH User Option Bytes values
01272   *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
01273   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
01274   *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
01275   */
01276 #endif /*DUAL_CORE*/
01277 static uint32_t FLASH_OB_GetUser(void)
01278 {
01279   uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
01280   userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
01281
01282   return userConfig;
01283 }
01284
01285 /**
01286   * @brief  Configure the Proprietary code readout protection of the desired addresses
01287   *
01288   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
01289   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
01290   * @note   To validate the PCROP options, the option bytes must be reloaded
01291   *         through the call of the HAL_FLASH_OB_Launch() function.
01292   *
01293   * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
01294   *         when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
01295   *         This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
01296   *
01297   * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
01298   *          This parameter can be an address between begin and end of the bank
01299   *
01300   * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
01301   *          This parameter can be an address between PCROPStartAddr and end of the bank
01302   *
01303   * @param  Banks the specific bank to apply PCROP protection
01304   *          This parameter can be one of the following values:
01305   *            @arg FLASH_BANK_1: PCROP on specified bank1 area
01306   *            @arg FLASH_BANK_2: PCROP on specified bank2 area
01307   *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
01308   *
01309   * @retval None
01310   */
01311 static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
01312 {
01313   /* Check the parameters */
01314   assert_param(IS_FLASH_BANK(Banks));
01315   assert_param(IS_OB_PCROP_RDP(PCROPConfig));
01316
01317   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
01318   {
01319     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
01320     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
01321
01322     /* Configure the Proprietary code readout protection */
01323     FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
01324                        (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
01325                        PCROPConfig;
01326   }
01327
01328   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
01329   {
01330     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
01331     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
01332
01333     /* Configure the Proprietary code readout protection */
01334     FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
01335                        (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
01336                        PCROPConfig;
01337   }
01338 }
01339
01340 /**
01341   * @brief  Get the Proprietary code readout protection configuration on a given Bank
01342   *
01343   * @param  PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
01344   *         when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
01345   *
01346   * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
01347   *
01348   * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
01349   *
01350   * @param  Bank the specific bank to apply PCROP protection
01351   *          This parameter can be exclusively one of the following values:
01352   *            @arg FLASH_BANK_1: PCROP on specified bank1 area
01353   *            @arg FLASH_BANK_2: PCROP on specified bank2 area
01354   *            @arg FLASH_BANK_BOTH: is  not allowed here
01355   *
01356   * @retval None
01357   */
01358 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
01359 {
01360   uint32_t regvalue = 0;
01361   uint32_t bankBase = 0;
01362
01363   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
01364   {
01365     regvalue = FLASH->PRAR_CUR1;
01366     bankBase = FLASH_BANK1_BASE;
01367   }
01368
01369   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
01370   {
01371     regvalue = FLASH->PRAR_CUR2;
01372     bankBase = FLASH_BANK2_BASE;
01373   }
01374
01375   (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
01376
01377   (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
01378   (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
01379   (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
01380 }
01381
01382 /**
01383   * @brief  Set the BOR Level.
01384   * @param  Level specifies the Option Bytes BOR Reset Level.
01385   *          This parameter can be one of the following values:
01386   *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
01387   *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
01388   *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
01389   *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
01390   * @retval None
01391   */
01392 static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
01393 {
01394   assert_param(IS_OB_BOR_LEVEL(Level));
01395
01396   /* Configure BOR_LEV option byte */
01397   MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
01398 }
01399
01400 /**
01401   * @brief  Get the BOR Level.
01402   * @retval The Option Bytes BOR Reset Level.
01403   *            This parameter can be one of the following values:
01404   *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
01405   *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
01406   *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
01407   *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
01408   */
01409 static uint32_t FLASH_OB_GetBOR(void)
01410 {
01411   return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
01412 }
01413
01414 /**
01415   * @brief  Set Boot address
01416   * @param  BootOption Boot address option byte to be programmed,
01417   *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
01418                         (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
01419   *
01420   * @param  BootAddress0 Specifies the Boot Address 0
01421   * @param  BootAddress1 Specifies the Boot Address 1
01422   * @retval HAL Status
01423   */
01424 static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
01425 {
01426   /* Check the parameters */
01427   assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
01428
01429   if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
01430   {
01431     /* Check the parameters */
01432     assert_param(IS_BOOT_ADDRESS(BootAddress0));
01433
01434     /* Configure CM7 BOOT ADD0 */
01435 #if defined(DUAL_CORE)
01436     MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
01437 #else /* Single Core*/
01438     MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
01439 #endif /* DUAL_CORE */
01440   }
01441
01442   if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
01443   {
01444     /* Check the parameters */
01445     assert_param(IS_BOOT_ADDRESS(BootAddress1));
01446
01447     /* Configure CM7 BOOT ADD1 */
01448 #if defined(DUAL_CORE)
01449     MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
01450 #else /* Single Core*/
01451     MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
01452 #endif /* DUAL_CORE */
01453   }
01454 }
01455
01456 /**
01457   * @brief  Get Boot address
01458   * @param  BootAddress0 Specifies the Boot Address 0.
01459   * @param  BootAddress1 Specifies the Boot Address 1.
01460   * @retval HAL Status
01461   */
01462 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
01463 {
01464   uint32_t regvalue;
01465
01466 #if defined(DUAL_CORE)
01467   regvalue = FLASH->BOOT7_CUR;
01468
01469   (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
01470   (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
01471 #else /* Single Core */
01472   regvalue = FLASH->BOOT_CUR;
01473
01474   (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
01475   (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
01476 #endif /* DUAL_CORE */
01477 }
01478
01479 #if defined(DUAL_CORE)
01480 /**
01481   * @brief  Set CM4 Boot address
01482   * @param  BootOption Boot address option byte to be programmed,
01483   *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
01484                         (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
01485   *
01486   * @param  BootAddress0 Specifies the CM4 Boot Address 0.
01487   * @param  BootAddress1 Specifies the CM4 Boot Address 1.
01488   * @retval HAL Status
01489   */
01490 static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
01491 {
01492   /* Check the parameters */
01493   assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
01494
01495   if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
01496   {
01497     /* Check the parameters */
01498     assert_param(IS_BOOT_ADDRESS(BootAddress0));
01499
01500     /* Configure CM4 BOOT ADD0 */
01501     MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
01502
01503   }
01504
01505   if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
01506   {
01507     /* Check the parameters */
01508     assert_param(IS_BOOT_ADDRESS(BootAddress1));
01509
01510     /* Configure CM4 BOOT ADD1 */
01511     MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
01512   }
01513 }
01514
01515 /**
01516   * @brief  Get CM4 Boot address
01517   * @param  BootAddress0 Specifies the CM4 Boot Address 0.
01518   * @param  BootAddress1 Specifies the CM4 Boot Address 1.
01519   * @retval HAL Status
01520   */
01521 static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
01522 {
01523   uint32_t regvalue;
01524
01525   regvalue = FLASH->BOOT4_CUR;
01526
01527   (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
01528   (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
01529 }
01530 #endif /*DUAL_CORE*/
01531
01532 /**
01533   * @brief  Set secure area configuration
01534   * @param  SecureAreaConfig specify if the secure area will be deleted or not
01535   *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
01536   *
01537   * @param  SecureAreaStartAddr Specifies the secure area start address
01538   * @param  SecureAreaEndAddr Specifies the secure area end address
01539   * @param  Banks the specific bank to apply Security protection
01540   *          This parameter can be one of the following values:
01541   *            @arg FLASH_BANK_1: Secure area on specified bank1 area
01542   *            @arg FLASH_BANK_2: Secure area on specified bank2 area
01543   *            @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
01544   * @retval None
01545   */
01546 static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
01547 {
01548   /* Check the parameters */
01549   assert_param(IS_FLASH_BANK(Banks));
01550   assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
01551
01552   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
01553   {
01554     /* Check the parameters */
01555     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
01556     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
01557
01558     /* Configure the secure area */
01559     FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
01560                        (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
01561                        (SecureAreaConfig & FLASH_SCAR_DMES);
01562   }
01563
01564   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
01565   {
01566     /* Check the parameters */
01567     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
01568     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
01569
01570     /* Configure the secure area */
01571     FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
01572                        (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
01573                        (SecureAreaConfig & FLASH_SCAR_DMES);
01574   }
01575 }
01576
01577 /**
01578   * @brief  Get secure area configuration
01579   * @param  SecureAreaConfig indicates if the secure area will be deleted or not
01580   *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
01581   * @param  SecureAreaStartAddr gives the secure area start address
01582   * @param  SecureAreaEndAddr gives the secure area end address
01583   * @param  Bank Specifies the Bank
01584   * @retval None
01585   */
01586 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
01587 {
01588   uint32_t regvalue = 0;
01589   uint32_t bankBase = 0;
01590
01591   /* Check Bank parameter value */
01592   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
01593   {
01594     regvalue = FLASH->SCAR_CUR1;
01595     bankBase = FLASH_BANK1_BASE;
01596   }
01597
01598   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
01599   {
01600     regvalue = FLASH->SCAR_CUR2;
01601     bankBase = FLASH_BANK2_BASE;
01602   }
01603
01604   /* Get the secure area settings */
01605   (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
01606   (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
01607   (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
01608   (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
01609 }
01610
01611 /**
01612   * @brief  Add a CRC sector to the list of sectors on which the CRC will be calculated
01613   * @param  Sector Specifies the CRC sector number
01614   * @param  Bank Specifies the Bank
01615   * @retval None
01616   */
01617 static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
01618 {
01619   /* Check the parameters */
01620   assert_param(IS_FLASH_SECTOR(Sector));
01621
01622   if (Bank == FLASH_BANK_1)
01623   {
01624     /* Clear CRC sector */
01625     FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
01626
01627     /* Select CRC Sector and activate ADD_SECT bit */
01628     FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
01629   }
01630   else
01631   {
01632     /* Clear CRC sector */
01633     FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
01634
01635     /* Select CRC Sector and activate ADD_SECT bit */
01636     FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
01637   }
01638 }
01639
01640 /**
01641   * @brief  Select CRC start and end memory addresses on which the CRC will be calculated
01642   * @param  CRCStartAddr Specifies the CRC start address
01643   * @param  CRCEndAddr Specifies the CRC end address
01644   * @param  Bank Specifies the Bank
01645   * @retval None
01646   */
01647 static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
01648 {
01649   if (Bank == FLASH_BANK_1)
01650   {
01651     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
01652     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
01653
01654     /* Write CRC Start and End addresses */
01655     FLASH->CRCSADD1 = CRCStartAddr;
01656     FLASH->CRCEADD1 = CRCEndAddr;
01657   }
01658   else
01659   {
01660     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
01661     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
01662
01663     /* Write CRC Start and End addresses */
01664     FLASH->CRCSADD2 = CRCStartAddr;
01665     FLASH->CRCEADD2 = CRCEndAddr;
01666   }
01667 }
01668 /**
01669   * @}
01670   */
01671
01672 #if defined (FLASH_OTPBL_LOCKBL)
01673 /**
01674   * @brief  Configure the OTP Block Lock.
01675   * @param  OTP_Block specifies the OTP Block to lock.
01676   *         This parameter can be a value of @ref FLASHEx_OTP_Blocks
01677   * @retval None
01678   */
01679 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
01680 {
01681   /* Check the parameters */
01682   assert_param(IS_OTP_BLOCK(OTP_Block));
01683
01684   /* Configure the OTP Block lock in the option bytes register */
01685   FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
01686 }
01687
01688 /**
01689   * @brief  Get the OTP Block Lock.
01690   * @retval OTP_Block specifies the OTP Block to lock.
01691   *         This return value can be a value of @ref FLASHEx_OTP_Blocks
01692   */
01693 static uint32_t FLASH_OB_OTP_GetLock(void)
01694 {
01695   return (FLASH->OTPBL_CUR);
01696 }
01697 #endif /* FLASH_OTPBL_LOCKBL */
01698
01699 #endif /* HAL_FLASH_MODULE_ENABLED */
01700
01701 /**
01702   * @}
01703   */
01704
01705 /**
01706   * @}
01707   */
01708
01709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_flash_ex.h Source File

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stm32h7xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32H7xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_FLASH_EX_H
00022 #define STM32H7xx_HAL_FLASH_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FLASHEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  FLASH Erase structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t TypeErase;   /*!< Mass erase or sector Erase.
00050                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00051
00052   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
00053                              This parameter must be a value of @ref FLASHEx_Banks */
00054
00055   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
00056                              This parameter must be a value of @ref FLASH_Sectors */
00057
00058   uint32_t NbSectors;   /*!< Number of sectors to be erased.
00059                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
00060
00061   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
00062                              This parameter must be a value of @ref FLASHEx_Voltage_Range */
00063
00064 } FLASH_EraseInitTypeDef;
00065
00066
00067 /**
00068   * @brief  FLASH Option Bytes Program structure definition
00069   */
00070 typedef struct
00071 {
00072   uint32_t OptionType;     /*!< Option byte to be configured.
00073                                 This parameter can be a value of @ref FLASHEx_Option_Type */
00074
00075   uint32_t WRPState;       /*!< Write protection activation or deactivation.
00076                                 This parameter can be a value of @ref FLASHEx_WRP_State */
00077
00078   uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
00079                                 The value of this parameter depend on device used within the same series */
00080
00081   uint32_t RDPLevel;       /*!< Set the read protection level.
00082                                 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
00083
00084   uint32_t BORLevel;       /*!< Set the BOR Level.
00085                                 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
00086
00087   uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00088                                 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
00089
00090   uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
00091                                 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
00092
00093   uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
00094                                 This parameter must be a value of @ref FLASHEx_Banks */
00095
00096   uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
00097                                 when RDP level decreased from Level 1 to Level 0 or during a mass erase.
00098                                 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
00099
00100   uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
00101                                 This parameter must be a value between begin and end of a bank */
00102
00103   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
00104                                 This parameter must be a value between PCROP Start address and end of a bank */
00105
00106   uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
00107                                 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
00108
00109   uint32_t BootAddr0;      /*!< Boot Address 0.
00110                                 This parameter must be a value between begin and end of a bank */
00111
00112   uint32_t BootAddr1;      /*!< Boot Address 1.
00113                                 This parameter must be a value between begin and end of a bank */
00114 #if defined(DUAL_CORE)
00115   uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
00116                                 or both.
00117                                 This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
00118
00119   uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.
00120                                 This parameter must be a value between begin and end of a bank */
00121
00122   uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.
00123                                 This parameter must be a value between begin and end of a bank */
00124 #endif /*DUAL_CORE*/
00125
00126   uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
00127                                      when RDP level decreased from Level 1 to Level 0 or during a mass erase.
00128                                      This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
00129
00130   uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
00131                                      This parameter must be a value between begin address and end address of bank1 */
00132
00133   uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
00134                                      This parameter must be a value between Secure Area Start address and end address of a bank1 */
00135
00136 #if defined (FLASH_OTPBL_LOCKBL)
00137   uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
00138                                 This parameter must be a value of @ref FLASHEx_OTP_Blocks */
00139 #endif /* FLASH_OTPBL_LOCKBL */
00140
00141 } FLASH_OBProgramInitTypeDef;
00142
00143 /**
00144   * @brief  FLASH Erase structure definition
00145   */
00146 typedef struct
00147 {
00148   uint32_t TypeCRC;      /*!< CRC Selection Type.
00149                               This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
00150
00151   uint32_t BurstSize;    /*!< CRC Burst Size.
00152                               This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
00153
00154   uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
00155                               This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
00156
00157   uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
00158                               This parameter must be a value of @ref FLASH_Sectors */
00159
00160   uint32_t NbSectors;    /*!< Number of sectors to be computed.
00161                               This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
00162
00163   uint32_t CRCStartAddr; /*!< CRC Start address.
00164                               This parameter must be a value between begin address and end address of a bank */
00165
00166   uint32_t CRCEndAddr;   /*!< CRC End address.
00167                               This parameter must be a value between CRC Start address and end address of a bank */
00168
00169 } FLASH_CRCInitTypeDef;
00170
00171 /**
00172   * @}
00173   */
00174 /* Exported constants --------------------------------------------------------*/
00175
00176 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
00181   * @{
00182   */
00183 #define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */
00184 #define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */
00185 /**
00186   * @}
00187   */
00188
00189 #if defined (FLASH_CR_PSIZE)
00190 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
00191   * @{
00192   */
00193 #define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */
00194 #define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
00195 #define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
00196 #define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
00197 /**
00198   * @}
00199   */
00200 #endif /* FLASH_CR_PSIZE */
00201
00202 /** @defgroup FLASHEx_WRP_State FLASH WRP State
00203   * @{
00204   */
00205 #define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
00206 #define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup FLASHEx_Option_Type FLASH Option Type
00212   * @{
00213   */
00214 #define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */
00215 #define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */
00216 #define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */
00217 #define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
00218 #define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
00219 #define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
00220 #if defined (DUAL_CORE)
00221 #define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
00222 #define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
00223 #define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
00224 #else /* Single core */
00225 #define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
00226 #endif /*DUAL_CORE*/
00227 #if defined (FLASH_OTPBL_LOCKBL)
00228 #define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
00229 #endif /* FLASH_OTPBL_LOCKBL */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
00235   * @{
00236   */
00237 #define OB_RDP_LEVEL_0       0xAA00U
00238 #define OB_RDP_LEVEL_1       0x5500U
00239 #define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2
00240                                             it s no more possible to go back to level 1 or 0 */
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
00246   * @{
00247   */
00248 #define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */
00249 #define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */
00250 /**
00251   * @}
00252   */
00253
00254
00255 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
00256   * @{
00257   */
00258 #define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */
00259 #define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
00265   * @{
00266   */
00267 #define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */
00268 #define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
00274   * @{
00275   */
00276 #define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */
00277 #define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
00283   * @{
00284   */
00285 #define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
00286 #define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
00292   * @{
00293   */
00294 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
00295 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
00301   * @{
00302   */
00303 #define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
00304 #define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
00305 #define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
00306 #define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
00307 /**
00308   * @}
00309   */
00310
00311
00312
00313 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
00314   * @{
00315   */
00316 #define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
00317 #define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
00318 #define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
00319 #define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
00320 #define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
00321 #define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
00322 #define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup FLASH_Latency FLASH Latency
00328   * @{
00329   */
00330 #define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
00331 #define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
00332 #define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
00333 #define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
00334 #define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
00335 #define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
00336 #define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
00337 #define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
00338 #define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
00339 #define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
00340 #define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
00341 #define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
00342 #define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
00343 #define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
00344 #define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
00345 #define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup FLASHEx_Banks FLASH Banks
00351   * @{
00352   */
00353 #define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
00354 #define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
00355 #define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
00361   * @{
00362   */
00363 #define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
00364                                                       is decreased from Level 1 to Level 0 or during a mass erase */
00365 #define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
00366                                                       decreased from Level 1 to Level 0 (full mass erase) */
00367
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
00373   * @{
00374   */
00375 #if (FLASH_SECTOR_TOTAL == 128)
00376 #define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
00377 #define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
00378 #define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
00379 #define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
00380 #define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
00381 #define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
00382 #define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
00383 #define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
00384 #define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
00385 #define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
00386 #define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
00387 #define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
00388 #define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
00389 #define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
00390 #define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
00391 #define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
00392 #define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
00393 #define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
00394 #define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
00395 #define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
00396 #define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
00397 #define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
00398 #define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
00399 #define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
00400 #define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
00401 #define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
00402 #define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
00403 #define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
00404 #define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
00405 #define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
00406 #define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
00407 #define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
00408 #define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
00409 #else
00410 #define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
00411 #define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
00412 #define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
00413 #define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
00414 #define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
00415 #define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
00416 #define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
00417 #define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
00418 #define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
00419 #endif /* FLASH_SECTOR_TOTAL == 128 */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
00425   * @{
00426   */
00427 #define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */
00428 #define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
00434   * @{
00435   */
00436 #define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
00437 #define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
00438 #define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
00439 #define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
00440 /**
00441   * @}
00442   */
00443
00444 #if defined(DUAL_CORE)
00445 /** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7
00446   * @{
00447   */
00448 #define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */
00449 #define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4
00456   * @{
00457   */
00458 #define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */
00459 #define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */
00460 /**
00461   * @}
00462   */
00463 #endif /* DUAL_CORE */
00464
00465 /** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
00466   * @{
00467   */
00468 #define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
00469 #define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */
00470 /**
00471   * @}
00472   */
00473
00474 #if defined(DUAL_CORE)
00475 /** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW
00476   * @{
00477   */
00478 #define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/
00479 #define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/
00480 /**
00481   * @}
00482   */
00483 #endif
00484
00485 /** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
00486   * @{
00487   */
00488 #define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */
00489 #define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
00495   * @{
00496   */
00497 #define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */
00498 #define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
00499 /**
00500   * @}
00501   */
00502
00503 #if defined (DUAL_CORE)
00504 /** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
00505   * @{
00506   */
00507 #define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */
00508 #define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2
00514   * @{
00515   */
00516 #define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */
00517 #define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
00518 /**
00519   * @}
00520   */
00521 #endif /* DUAL_CORE */
00522
00523 /** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
00524   * @{
00525   */
00526 #define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */
00527 #define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
00528 /**
00529   * @}
00530   */
00531
00532 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
00533   * @{
00534   */
00535 #define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
00536 #define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
00537 /**
00538   * @}
00539   */
00540
00541 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
00542 /** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
00543   * @{
00544   */
00545 #define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
00546 #define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
00547 /**
00548   * @}
00549   */
00550 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
00551
00552 /** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
00553   * @{
00554   */
00555 #define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
00556 #define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
00557 #define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
00558 /**
00559   * @}
00560   */
00561
00562  /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
00563   * @{
00564   */
00565 #define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */
00566 #define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/
00567 #define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/
00568 #define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */
00569 #define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */
00570 #define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */
00571 #define OB_USER_SECURITY          0x0040U /*!< security selection */
00572 #define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
00573 #define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
00574 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
00575 #define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
00576 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
00577 #if defined (DUAL_CORE)
00578 #define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
00579 #define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
00580 #define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
00581 #define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/
00582 #define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/
00583 #endif /*DUAL_CORE*/
00584
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
00590   * @{
00591   */
00592 #define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level
00593                                                        is decreased from Level 1 to Level 0 or during a mass erase */
00594 #define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
00595                                                        decreased from Level 1 to Level 0 (full mass erase) */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
00601   * @{
00602   */
00603 #define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */
00604 #define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */
00605 #define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
00611   * @{
00612   */
00613 #define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */
00614 #define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */
00615 #define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */
00616 #define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */
00617 /**
00618   * @}
00619   */
00620
00621 /** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
00622   * @{
00623   */
00624 #define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */
00625 #define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */
00626 #define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
00627 #define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */
00628 /**
00629   * @}
00630   */
00631
00632 #if defined (FLASH_OTPBL_LOCKBL)
00633 /** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
00634   * @{
00635   */
00636 #define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
00637 #define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
00638 #define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
00639 #define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
00640 #define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
00641 #define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
00642 #define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
00643 #define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
00644 #define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
00645 #define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
00646 #define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
00647 #define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
00648 #define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
00649 #define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
00650 #define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
00651 #define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
00652 #define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
00653 /**
00654   * @}
00655   */
00656 #endif /* FLASH_OTPBL_LOCKBL */
00657
00658 /* Exported macro ------------------------------------------------------------*/
00659 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
00660   * @{
00661   */
00662 /**
00663   * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
00664   * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
00665   * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
00666   * @retval The FLASH Boot Base Adress
00667   */
00668 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
00669  /**
00670   * @}
00671   */
00672
00673 #if defined (FLASH_CR_PSIZE)
00674 /**
00675   * @brief  Set the FLASH Program/Erase parallelism.
00676   * @param  __PSIZE__ FLASH Program/Erase parallelism
00677   *         This parameter can be a value of @ref FLASH_Program_Parallelism
00678   * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
00679   * @retval none
00680   */
00681 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \
00682                               MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
00683                               MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
00684
00685 /**
00686   * @brief  Get the FLASH Program/Erase parallelism.
00687   * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
00688   * @retval FLASH Program/Erase parallelism
00689   *         This return value can be a value of @ref FLASH_Program_Parallelism
00690   */
00691 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
00692                               READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
00693                               READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
00694 #endif /* FLASH_CR_PSIZE */
00695
00696 /**
00697   * @brief  Set the FLASH Programming Delay.
00698   * @param  __DELAY__ FLASH Programming Delay
00699   *         This parameter can be a value of @ref FLASHEx_Programming_Delay
00700   * @retval none
00701   */
00702 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
00703
00704 /**
00705   * @brief  Get the FLASH Programming Delay.
00706   * @retval FLASH Programming Delay
00707   *         This return value can be a value of @ref FLASHEx_Programming_Delay
00708   */
00709 #define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
00710
00711 /* Exported functions --------------------------------------------------------*/
00712 /** @addtogroup FLASHEx_Exported_Functions
00713   * @{
00714   */
00715
00716 /** @addtogroup FLASHEx_Exported_Functions_Group1
00717   * @{
00718   */
00719 /* Extension Program operation functions  *************************************/
00720 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
00721 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00722 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00723 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00724
00725 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
00726 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
00727 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
00728 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
00729
00730 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
00731
00732 /**
00733   * @}
00734   */
00735
00736 /**
00737   * @}
00738   */
00739 /* Private types -------------------------------------------------------------*/
00740 /* Private variables ---------------------------------------------------------*/
00741 /* Private constants ---------------------------------------------------------*/
00742 /* Private macros ------------------------------------------------------------*/
00743 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00744   * @{
00745   */
00746
00747 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
00748   * @{
00749   */
00750
00751 #define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
00752                                           ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00753
00754 #if defined (FLASH_CR_PSIZE)
00755 #define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
00756                                           ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
00757                                           ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
00758                                           ((RANGE) == FLASH_VOLTAGE_RANGE_4))
00759 #endif /* FLASH_CR_PSIZE */
00760
00761 #define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
00762                                           ((VALUE) == OB_WRPSTATE_ENABLE))
00763
00764 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
00765 #define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
00766 #elif defined (DUAL_CORE)
00767 #define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
00768 #else
00769 #define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
00770 #endif /*DUAL_CORE*/
00771
00772 #define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
00773
00774 #define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
00775                                           ((LEVEL) == OB_RDP_LEVEL_1)   ||\
00776                                           ((LEVEL) == OB_RDP_LEVEL_2))
00777
00778 #define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
00779
00780 #define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00781
00782 #define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00783
00784 #define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00785
00786 #define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
00787
00788 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
00789
00790 #define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
00791                                           ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
00792
00793 #define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
00794                                           ((LATENCY) == FLASH_LATENCY_1)  || \
00795                                           ((LATENCY) == FLASH_LATENCY_2)  || \
00796                                           ((LATENCY) == FLASH_LATENCY_3)  || \
00797                                           ((LATENCY) == FLASH_LATENCY_4)  || \
00798                                           ((LATENCY) == FLASH_LATENCY_5)  || \
00799                                           ((LATENCY) == FLASH_LATENCY_6)  || \
00800                                           ((LATENCY) == FLASH_LATENCY_7)  || \
00801                                           ((LATENCY) == FLASH_LATENCY_8)  || \
00802                                           ((LATENCY) == FLASH_LATENCY_9)  || \
00803                                           ((LATENCY) == FLASH_LATENCY_10) || \
00804                                           ((LATENCY) == FLASH_LATENCY_11) || \
00805                                           ((LATENCY) == FLASH_LATENCY_12) || \
00806                                           ((LATENCY) == FLASH_LATENCY_13) || \
00807                                           ((LATENCY) == FLASH_LATENCY_14) || \
00808                                           ((LATENCY) == FLASH_LATENCY_15))
00809
00810 #define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
00811
00812 #if (FLASH_SECTOR_TOTAL == 8U)
00813 #define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00814 #else
00815 #define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
00816 #endif /* FLASH_SECTOR_TOTAL == 8U */
00817
00818 #define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
00819                                           ((CONFIG) == OB_PCROP_RDP_ERASE))
00820
00821 #define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
00822                                           ((CONFIG) == OB_SECURE_RDP_ERASE))
00823
00824 #define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
00825
00826 #define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
00827
00828 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
00829 #define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
00830 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
00831
00832 #define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
00833 #if defined (DUAL_CORE)
00834 #define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
00835 #endif /* DUAL_CORE */
00836 #define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
00837
00838 #define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
00839
00840 #define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
00841
00842 #define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
00843
00844 #define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
00845                                           ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
00846
00847 #define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
00848
00849 #if defined (DUAL_CORE)
00850 #define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
00851
00852 #define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
00853
00854 #define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
00855
00856 #define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
00857 #endif /* DUAL_CORE */
00858 #if defined (DUAL_CORE)
00859 #define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
00860 #else
00861 #define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
00862 #endif /* DUAL_CORE */
00863
00864 #define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
00865                                           ((VALUE) == OB_BOOT_ADD1)  || \
00866                                           ((VALUE) == OB_BOOT_ADD_BOTH))
00867
00868 #define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
00869                                           ((VALUE) == FLASH_CRC_SECTORS) || \
00870                                           ((VALUE) == FLASH_CRC_BANK))
00871
00872 #if defined (FLASH_OTPBL_LOCKBL)
00873 #define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
00874 #endif /* FLASH_OTPBL_LOCKBL */
00875 /**
00876   * @}
00877   */
00878
00879 /**
00880   * @}
00881   */
00882
00883 /* Private functions ---------------------------------------------------------*/
00884 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00885   * @{
00886   */
00887 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
00888 /**
00889   * @}
00890   */
00891
00892 /**
00893   * @}
00894   */
00895
00896 /**
00897   * @}
00898   */
00899
00900 /**
00901   * @}
00902   */
00903
00904 #ifdef __cplusplus
00905 }
00906 #endif
00907
00908 #endif /* STM32H7xx_HAL_FLASH_EX_H */
00909
00910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gfxmmu.c Source File

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stm32h7xx_hal_gfxmmu.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gfxmmu.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Graphic MMU (GFXMMU) peripheral:
00007   *           + Initialization and De-initialization.
00008   *           + LUT configuration.
00009   *           + Force flush and/or invalidate of cache.
00010   *           + Modify physical buffer adresses.
00011   *           + Modify cache and pre-fetch parameters.
00012   *           + Error management.
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     *** Initialization ***
00020     ======================
00021     [..]
00022       (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
00023         (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
00024         (++) If interrupts are used, enable and configure GFXMMU global
00025             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00026       (#) Configure the number of blocks per line, default value, physical
00027           buffer addresses, cache and pre-fetch parameters and interrupts
00028           using the HAL_GFXMMU_Init() function.
00029
00030     *** LUT configuration ***
00031     =========================
00032     [..]
00033       (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
00034           range of lines).
00035       (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
00036       (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
00037
00038     *** Force flush and/or invalidate of cache ***
00039     ==============================================
00040     [..]
00041       (#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
00042
00043     *** Modify physical buffer adresses ***
00044     =======================================
00045     [..]
00046       (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
00047
00048     *** Modify cache and pre-fetch parameters ***
00049     =============================================
00050     [..]
00051       (#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
00052           parameters.
00053
00054     *** Error management ***
00055     ========================
00056     [..]
00057       (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
00058           an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
00059           Use HAL_GFXMMU_GetError() to get the error code.
00060
00061     *** De-initialization ***
00062     =========================
00063     [..]
00064       (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
00065         (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
00066         (++) If interrupts has been used, disable GFXMMU global interrupt with
00067              HAL_NVIC_DisableIRQ().
00068       (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
00069
00070     *** Callback registration ***
00071     =============================
00072
00073     [..]
00074     The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
00075     allows the user to configure dynamically the driver callbacks.
00076     Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
00077
00078     [..]
00079     Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
00080       (+) ErrorCallback      : GFXMMU error.
00081       (+) MspInitCallback    : GFXMMU MspInit.
00082       (+) MspDeInitCallback  : GFXMMU MspDeInit.
00083     [..]
00084     This function takes as parameters the HAL peripheral handle, the callback ID
00085     and a pointer to the user callback function.
00086
00087     [..]
00088     Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
00089     weak (surcharged) function.
00090     HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00091     and the callback ID.
00092     [..]
00093     This function allows to reset following callbacks:
00094       (+) ErrorCallback      : GFXMMU error.
00095       (+) MspInitCallback    : GFXMMU MspInit.
00096       (+) MspDeInitCallback  : GFXMMU MspDeInit.
00097
00098     [..]
00099     By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
00100     all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00101     examples HAL_GFXMMU_ErrorCallback().
00102     Exception done for MspInit and MspDeInit callbacks that are respectively
00103     reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
00104     and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
00105     If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
00106     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00107
00108     [..]
00109     Callbacks can be registered/unregistered in READY state only.
00110     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00111     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00112     during the Init/DeInit.
00113     In that case first register the MspInit/MspDeInit user callbacks
00114     using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
00115     or HAL_GFXMMU_Init function.
00116
00117     [..]
00118     When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
00119     not defined, the callback registering feature is not available
00120     and weak (surcharged) callbacks are used.
00121
00122   @endverbatim
00123   ******************************************************************************
00124   * @attention
00125   *
00126   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00127   * All rights reserved.</center></h2>
00128   *
00129   * This software component is licensed by ST under BSD 3-Clause license,
00130   * the "License"; You may not use this file except in compliance with the
00131   * License. You may obtain a copy of the License at:
00132   *                        opensource.org/licenses/BSD-3-Clause
00133   *
00134   ******************************************************************************
00135   */
00136
00137 /* Includes ------------------------------------------------------------------*/
00138 #include "stm32h7xx_hal.h"
00139
00140 /** @addtogroup STM32H7xx_HAL_Driver
00141   * @{
00142   */
00143 #ifdef HAL_GFXMMU_MODULE_ENABLED
00144 #if defined(GFXMMU)
00145 /** @defgroup GFXMMU GFXMMU
00146   * @brief GFXMMU HAL driver module
00147   * @{
00148   */
00149
00150 /* Private typedef -----------------------------------------------------------*/
00151 /* Private define ------------------------------------------------------------*/
00152 #define GFXMMU_LUTXL_FVB_OFFSET     8U
00153 #define GFXMMU_LUTXL_LVB_OFFSET     16U
00154 #define GFXMMU_CR_ITS_MASK          0x1FU
00155 /* Private macro -------------------------------------------------------------*/
00156 /* Private variables ---------------------------------------------------------*/
00157 /* Private function prototypes -----------------------------------------------*/
00158 /* Exported functions --------------------------------------------------------*/
00159 /** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
00160   * @{
00161   */
00162
00163 /** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
00164  *  @brief    Initialization and de-initialization functions
00165  *
00166 @verbatim
00167   ==============================================================================
00168           ##### Initialization and de-initialization functions #####
00169   ==============================================================================
00170     [..]  This section provides functions allowing to:
00171       (+) Initialize the GFXMMU.
00172       (+) De-initialize the GFXMMU.
00173 @endverbatim
00174   * @{
00175   */
00176
00177 /**
00178   * @brief  Initialize the GFXMMU according to the specified parameters in the
00179   *         GFXMMU_InitTypeDef structure and initialize the associated handle.
00180   * @param  hgfxmmu GFXMMU handle.
00181   * @retval HAL status.
00182   */
00183 HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
00184 {
00185   HAL_StatusTypeDef status = HAL_OK;
00186
00187   /* Check GFXMMU handle */
00188   if(hgfxmmu == NULL)
00189   {
00190     status = HAL_ERROR;
00191   }
00192   else
00193   {
00194     /* Check parameters */
00195     assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00196     assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
00197     assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
00198     assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
00199     assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
00200     assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
00201     assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
00202     assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
00203
00204 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00205     /* Reset callback pointers to the weak predefined callbacks */
00206     hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
00207
00208     /* Call GFXMMU MSP init function */
00209     if(hgfxmmu->MspInitCallback == NULL)
00210     {
00211       hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
00212     }
00213     hgfxmmu->MspInitCallback(hgfxmmu);
00214 #else
00215     /* Call GFXMMU MSP init function */
00216     HAL_GFXMMU_MspInit(hgfxmmu);
00217 #endif
00218
00219     /* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */
00220     hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
00221                                GFXMMU_CR_AMEIE | GFXMMU_CR_192BM | GFXMMU_CR_CE    | GFXMMU_CR_CL    |
00222                                GFXMMU_CR_CLB   | GFXMMU_CR_FC    | GFXMMU_CR_PD    | GFXMMU_CR_OC    |
00223                                GFXMMU_CR_OB);
00224     hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
00225     if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
00226     {
00227       assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
00228       assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
00229       assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
00230       assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
00231       hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
00232                                 hgfxmmu->Init.CachePrefetch.CacheLock |
00233                                 hgfxmmu->Init.CachePrefetch.Prefetch |
00234                                 hgfxmmu->Init.CachePrefetch.OutterBufferability |
00235                                 hgfxmmu->Init.CachePrefetch.OutterCachability);
00236       if(hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
00237       {
00238         assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
00239         assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
00240         hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
00241                                   hgfxmmu->Init.CachePrefetch.CacheForce);
00242       }
00243     }
00244     if(hgfxmmu->Init.Interrupts.Activation == ENABLE)
00245     {
00246       assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
00247       hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
00248     }
00249
00250     /* Configure default value on GFXMMU_DVR register */
00251     hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
00252
00253     /* Configure physical buffer adresses on GFXMMU_BxCR registers */
00254     hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
00255     hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
00256     hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
00257     hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
00258
00259     /* Force invalidate cache if cache is enabled */
00260     if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
00261     {
00262       hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
00263     }
00264
00265     /* Reset GFXMMU error code */
00266     hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
00267
00268     /* Set GFXMMU to ready state */
00269     hgfxmmu->State = HAL_GFXMMU_STATE_READY;
00270   }
00271   /* Return function status */
00272   return status;
00273 }
00274
00275 /**
00276   * @brief  De-initialize the GFXMMU.
00277   * @param  hgfxmmu GFXMMU handle.
00278   * @retval HAL status.
00279   */
00280 HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
00281 {
00282   HAL_StatusTypeDef status = HAL_OK;
00283
00284   /* Check GFXMMU handle */
00285   if(hgfxmmu == NULL)
00286   {
00287     status = HAL_ERROR;
00288   }
00289   else
00290   {
00291     /* Check parameters */
00292     assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00293
00294     /* Disable all interrupts on GFXMMU_CR register */
00295     hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
00296                                GFXMMU_CR_AMEIE);
00297
00298     /* Call GFXMMU MSP de-init function */
00299 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00300     if(hgfxmmu->MspDeInitCallback == NULL)
00301     {
00302       hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
00303     }
00304     hgfxmmu->MspDeInitCallback(hgfxmmu);
00305 #else
00306     HAL_GFXMMU_MspDeInit(hgfxmmu);
00307 #endif
00308
00309     /* Set GFXMMU to reset state */
00310     hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
00311   }
00312   /* Return function status */
00313   return status;
00314 }
00315
00316 /**
00317   * @brief  Initialize the GFXMMU MSP.
00318   * @param  hgfxmmu GFXMMU handle.
00319   * @retval None.
00320   */
00321 __weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
00322 {
00323   /* Prevent unused argument(s) compilation warning */
00324   UNUSED(hgfxmmu);
00325
00326   /* NOTE : This function should not be modified, when the function is needed,
00327             the HAL_GFXMMU_MspInit could be implemented in the user file.
00328    */
00329 }
00330
00331 /**
00332   * @brief  De-initialize the GFXMMU MSP.
00333   * @param  hgfxmmu GFXMMU handle.
00334   * @retval None.
00335   */
00336 __weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
00337 {
00338   /* Prevent unused argument(s) compilation warning */
00339   UNUSED(hgfxmmu);
00340
00341   /* NOTE : This function should not be modified, when the function is needed,
00342             the HAL_GFXMMU_MspDeInit could be implemented in the user file.
00343    */
00344 }
00345
00346 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00347 /**
00348   * @brief  Register a user GFXMMU callback
00349   *         to be used instead of the weak predefined callback.
00350   * @param  hgfxmmu GFXMMU handle.
00351   * @param  CallbackID ID of the callback to be registered.
00352   *         This parameter can be one of the following values:
00353   *           @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
00354   *           @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
00355   *           @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
00356   * @param  pCallback pointer to the callback function.
00357   * @retval HAL status.
00358   */
00359 HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
00360                                               HAL_GFXMMU_CallbackIDTypeDef CallbackID,
00361                                               pGFXMMU_CallbackTypeDef      pCallback)
00362 {
00363   HAL_StatusTypeDef status = HAL_OK;
00364
00365   if(pCallback == NULL)
00366   {
00367     /* update the error code */
00368     hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00369     /* update return status */
00370     status = HAL_ERROR;
00371   }
00372   else
00373   {
00374     if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
00375     {
00376       switch (CallbackID)
00377       {
00378       case HAL_GFXMMU_ERROR_CB_ID :
00379         hgfxmmu->ErrorCallback = pCallback;
00380         break;
00381       case HAL_GFXMMU_MSPINIT_CB_ID :
00382         hgfxmmu->MspInitCallback = pCallback;
00383         break;
00384       case HAL_GFXMMU_MSPDEINIT_CB_ID :
00385         hgfxmmu->MspDeInitCallback = pCallback;
00386         break;
00387       default :
00388         /* update the error code */
00389         hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00390         /* update return status */
00391         status = HAL_ERROR;
00392         break;
00393       }
00394     }
00395     else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
00396     {
00397       switch (CallbackID)
00398       {
00399       case HAL_GFXMMU_MSPINIT_CB_ID :
00400         hgfxmmu->MspInitCallback = pCallback;
00401         break;
00402       case HAL_GFXMMU_MSPDEINIT_CB_ID :
00403         hgfxmmu->MspDeInitCallback = pCallback;
00404         break;
00405       default :
00406         /* update the error code */
00407         hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00408         /* update return status */
00409         status = HAL_ERROR;
00410         break;
00411       }
00412     }
00413     else
00414     {
00415       /* update the error code */
00416       hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00417       /* update return status */
00418       status = HAL_ERROR;
00419     }
00420   }
00421   return status;
00422 }
00423
00424 /**
00425   * @brief  Unregister a user GFXMMU callback.
00426   *         GFXMMU callback is redirected to the weak predefined callback.
00427   * @param  hgfxmmu GFXMMU handle.
00428   * @param  CallbackID ID of the callback to be unregistered.
00429   *         This parameter can be one of the following values:
00430   *           @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
00431   *           @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
00432   *           @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
00433   * @retval HAL status.
00434   */
00435 HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
00436                                                 HAL_GFXMMU_CallbackIDTypeDef CallbackID)
00437 {
00438   HAL_StatusTypeDef status = HAL_OK;
00439
00440   if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
00441   {
00442     switch (CallbackID)
00443     {
00444     case HAL_GFXMMU_ERROR_CB_ID :
00445       hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
00446       break;
00447     case HAL_GFXMMU_MSPINIT_CB_ID :
00448       hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
00449       break;
00450     case HAL_GFXMMU_MSPDEINIT_CB_ID :
00451       hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
00452       break;
00453     default :
00454       /* update the error code */
00455       hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00456       /* update return status */
00457       status = HAL_ERROR;
00458       break;
00459     }
00460   }
00461   else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
00462   {
00463     switch (CallbackID)
00464     {
00465     case HAL_GFXMMU_MSPINIT_CB_ID :
00466       hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
00467       break;
00468     case HAL_GFXMMU_MSPDEINIT_CB_ID :
00469       hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
00470       break;
00471     default :
00472       /* update the error code */
00473       hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00474       /* update return status */
00475       status = HAL_ERROR;
00476       break;
00477     }
00478   }
00479   else
00480   {
00481     /* update the error code */
00482     hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
00483     /* update return status */
00484     status = HAL_ERROR;
00485   }
00486   return status;
00487 }
00488 #endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
00489
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
00495  *  @brief    GFXMMU operation functions
00496  *
00497 @verbatim
00498   ==============================================================================
00499                       ##### Operation functions #####
00500   ==============================================================================
00501     [..]  This section provides functions allowing to:
00502       (+) Configure LUT.
00503       (+) Force flush and/or invalidate of cache.
00504       (+) Modify physical buffer adresses.
00505       (+) Modify cache and pre-fetch parameters.
00506       (+) Manage error.
00507 @endverbatim
00508   * @{
00509   */
00510
00511 /**
00512   * @brief  This function allows to copy LUT from flash to look up RAM.
00513   * @param  hgfxmmu GFXMMU handle.
00514   * @param  FirstLine First line enabled on LUT.
00515   *         This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
00516   * @param  LinesNumber Number of lines enabled on LUT.
00517   *         This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
00518   * @param  Address Start address of LUT in flash.
00519   * @retval HAL status.
00520   */
00521 HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
00522                                        uint32_t FirstLine,
00523                                        uint32_t LinesNumber,
00524                                        uint32_t Address)
00525 {
00526   HAL_StatusTypeDef status = HAL_OK;
00527
00528   /* Check parameters */
00529   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00530   assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
00531   assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
00532
00533   /* Check GFXMMU state and coherent parameters */
00534   if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
00535   {
00536     status = HAL_ERROR;
00537   }
00538   else
00539   {
00540     uint32_t current_address, current_line, lutxl_address, lutxh_address;
00541
00542     /* Initialize local variables */
00543     current_address = Address;
00544     current_line    = 0U;
00545     lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
00546     lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
00547
00548     /* Copy LUT from flash to look up RAM */
00549     while(current_line < LinesNumber)
00550     {
00551       *((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
00552       current_address += 4U;
00553       *((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
00554       current_address += 4U;
00555       lutxl_address += 8U;
00556       lutxh_address += 8U;
00557       current_line++;
00558     }
00559   }
00560   /* Return function status */
00561   return status;
00562 }
00563
00564 /**
00565   * @brief  This function allows to disable a range of LUT lines.
00566   * @param  hgfxmmu GFXMMU handle.
00567   * @param  FirstLine First line to disable on LUT.
00568   *         This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
00569   * @param  LinesNumber Number of lines to disable on LUT.
00570   *         This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
00571   * @retval HAL status.
00572   */
00573 HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
00574                                              uint32_t FirstLine,
00575                                              uint32_t LinesNumber)
00576 {
00577   HAL_StatusTypeDef status = HAL_OK;
00578
00579   /* Check parameters */
00580   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00581   assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
00582   assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
00583
00584   /* Check GFXMMU state and coherent parameters */
00585   if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
00586   {
00587     status = HAL_ERROR;
00588   }
00589   else
00590   {
00591     uint32_t current_line, lutxl_address, lutxh_address;
00592
00593     /* Initialize local variables */
00594     current_line    = 0U;
00595     lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
00596     lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
00597
00598     /* Disable LUT lines */
00599     while(current_line < LinesNumber)
00600     {
00601       *((uint32_t *)lutxl_address) = 0U;
00602       *((uint32_t *)lutxh_address) = 0U;
00603       lutxl_address += 8U;
00604       lutxh_address += 8U;
00605       current_line++;
00606     }
00607   }
00608   /* Return function status */
00609   return status;
00610 }
00611
00612 /**
00613   * @brief  This function allows to configure one line of LUT.
00614   * @param  hgfxmmu GFXMMU handle.
00615   * @param  lutLine LUT line parameters.
00616   * @retval HAL status.
00617   */
00618 HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
00619 {
00620   HAL_StatusTypeDef status = HAL_OK;
00621
00622   /* Check parameters */
00623   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00624   assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
00625   assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
00626   assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
00627   assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
00628   assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
00629
00630   /* Check GFXMMU state */
00631   if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
00632   {
00633     status = HAL_ERROR;
00634   }
00635   else
00636   {
00637     uint32_t lutxl_address, lutxh_address;
00638
00639     /* Initialize local variables */
00640     lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
00641     lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
00642
00643     /* Configure LUT line */
00644     if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
00645     {
00646       /* Enable and configure LUT line */
00647       *((uint32_t *)lutxl_address) = (lutLine->LineStatus |
00648                                      (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
00649                                      (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
00650       *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
00651     }
00652     else
00653     {
00654       /* Disable LUT line */
00655       *((uint32_t *)lutxl_address) = 0U;
00656       *((uint32_t *)lutxh_address) = 0U;
00657     }
00658   }
00659   /* Return function status */
00660   return status;
00661 }
00662
00663 /**
00664   * @brief  This function allows to force flush and/or invalidate of cache.
00665   * @param  hgfxmmu GFXMMU handle.
00666   * @param  ForceParam Force cache parameter.
00667   *         This parameter can be a values combination of @ref GFXMMU_CacheForceParam.
00668   * @retval HAL status.
00669   */
00670 HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
00671 {
00672   HAL_StatusTypeDef status = HAL_OK;
00673
00674   /* Check parameters */
00675   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00676   assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
00677
00678   /* Check GFXMMU state and cache status */
00679   if(((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
00680   {
00681     status = HAL_ERROR;
00682   }
00683   else
00684   {
00685     /* Force flush and/or invalidate cache on GFXMMU_CCR register */
00686     hgfxmmu->Instance->CCR |= ForceParam;
00687   }
00688   /* Return function status */
00689   return status;
00690 }
00691
00692 /**
00693   * @brief  This function allows to modify physical buffer addresses.
00694   * @param  hgfxmmu GFXMMU handle.
00695   * @param  Buffers Buffers parameters.
00696   * @retval HAL status.
00697   */
00698 HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
00699 {
00700   HAL_StatusTypeDef status = HAL_OK;
00701
00702   /* Check parameters */
00703   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00704   assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
00705   assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
00706   assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
00707   assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
00708
00709   /* Check GFXMMU state */
00710   if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
00711   {
00712     status = HAL_ERROR;
00713   }
00714   else
00715   {
00716     /* Modify physical buffer adresses on GFXMMU_BxCR registers */
00717     hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
00718     hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
00719     hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
00720     hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
00721   }
00722   /* Return function status */
00723   return status;
00724 }
00725
00726 /**
00727   * @brief  This function allows to modify cache and pre-fetch parameters.
00728   * @param  hgfxmmu GFXMMU handle.
00729   * @param  CachePrefetch Cache and pre-fetch parameters.
00730   * @retval HAL status.
00731   */
00732 HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
00733                                                  GFXMMU_CachePrefetchTypeDef *CachePrefetch)
00734 {
00735   HAL_StatusTypeDef status = HAL_OK;
00736   assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
00737
00738   /* Check parameters */
00739   assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
00740
00741   /* Check GFXMMU state */
00742   if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
00743   {
00744     status = HAL_ERROR;
00745   }
00746   else
00747   {
00748     /* Modify cache and pre-fetch parameters on GFXMMU_CR register */
00749     hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
00750                                GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
00751     if(CachePrefetch->Activation == ENABLE)
00752     {
00753       assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
00754       assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
00755       assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
00756       assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
00757       hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
00758                                 CachePrefetch->CacheLock |
00759                                 CachePrefetch->Prefetch |
00760                                 CachePrefetch->OutterBufferability |
00761                                 CachePrefetch->OutterCachability);
00762       if(CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
00763       {
00764         assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
00765         assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
00766         hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
00767                                   CachePrefetch->CacheForce);
00768       }
00769     }
00770   }
00771   /* Return function status */
00772   return status;
00773 }
00774
00775 /**
00776   * @brief  This function handles the GFXMMU interrupts.
00777   * @param  hgfxmmu GFXMMU handle.
00778   * @retval None.
00779   */
00780 void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
00781 {
00782   uint32_t flags, interrupts, error;
00783
00784   /* Read current flags and interrupts and determine which error occurs */
00785   flags = hgfxmmu->Instance->SR;
00786   interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
00787   error = (flags & interrupts);
00788
00789   if(error != 0U)
00790   {
00791     /* Clear flags on GFXMMU_FCR register */
00792     hgfxmmu->Instance->FCR = error;
00793
00794     /* Update GFXMMU error code */
00795     hgfxmmu->ErrorCode |= error;
00796
00797     /* Call GFXMMU error callback */
00798 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00799     hgfxmmu->ErrorCallback(hgfxmmu);
00800 #else
00801     HAL_GFXMMU_ErrorCallback(hgfxmmu);
00802 #endif
00803   }
00804 }
00805
00806 /**
00807   * @brief  Error callback.
00808   * @param  hgfxmmu GFXMMU handle.
00809   * @retval None.
00810   */
00811 __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
00812 {
00813   /* Prevent unused argument(s) compilation warning */
00814   UNUSED(hgfxmmu);
00815
00816   /* NOTE : This function should not be modified, when the callback is needed,
00817             the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
00818    */
00819 }
00820
00821 /**
00822   * @}
00823   */
00824
00825 /** @defgroup GFXMMU_Exported_Functions_Group3 State functions
00826  *  @brief    GFXMMU state functions
00827  *
00828 @verbatim
00829   ==============================================================================
00830                          ##### State functions #####
00831   ==============================================================================
00832     [..]  This section provides functions allowing to:
00833       (+) Get GFXMMU handle state.
00834       (+) Get GFXMMU error code.
00835 @endverbatim
00836   * @{
00837   */
00838
00839 /**
00840   * @brief  This function allows to get the current GFXMMU handle state.
00841   * @param  hgfxmmu GFXMMU handle.
00842   * @retval GFXMMU state.
00843   */
00844 HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
00845 {
00846   /* Return GFXMMU handle state */
00847   return hgfxmmu->State;
00848 }
00849
00850 /**
00851   * @brief  This function allows to get the current GFXMMU error code.
00852   * @param  hgfxmmu GFXMMU handle.
00853   * @retval GFXMMU error code.
00854   */
00855 uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
00856 {
00857   uint32_t error_code;
00858
00859   /* Enter in critical section */
00860   __disable_irq();
00861
00862   /* Store and reset GFXMMU error code */
00863   error_code = hgfxmmu->ErrorCode;
00864   hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
00865
00866   /* Exit from critical section */
00867   __enable_irq();
00868
00869   /* Return GFXMMU error code */
00870   return error_code;
00871 }
00872
00873 /**
00874   * @}
00875   */
00876
00877 /**
00878   * @}
00879   */
00880 /* End of exported functions -------------------------------------------------*/
00881 /* Private functions ---------------------------------------------------------*/
00882 /* End of private functions --------------------------------------------------*/
00883
00884 /**
00885   * @}
00886   */
00887 #endif /* GFXMMU */
00888 #endif /* HAL_GFXMMU_MODULE_ENABLED */
00889 /**
00890   * @}
00891   */
00892
00893 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gfxmmu.h Source File

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stm32h7xx_hal_gfxmmu.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gfxmmu.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GFXMMU HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_GFXMMU_H
00022 #define STM32H7xx_HAL_GFXMMU_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined(GFXMMU)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup GFXMMU
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL GFXMMU states definition
00048   */
00049 typedef enum
00050 {
00051   HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */
00052   HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */
00053 }HAL_GFXMMU_StateTypeDef;
00054
00055 /**
00056   * @brief  GFXMMU buffers structure definition
00057   */
00058 typedef struct
00059 {
00060   uint32_t Buf0Address; /*!< Physical address of buffer 0. */
00061   uint32_t Buf1Address; /*!< Physical address of buffer 1. */
00062   uint32_t Buf2Address; /*!< Physical address of buffer 2. */
00063   uint32_t Buf3Address; /*!< Physical address of buffer 3. */
00064 }GFXMMU_BuffersTypeDef;
00065
00066 /**
00067   * @brief  GFXMMU cache and pre-fetch structure definition
00068   */
00069 typedef struct
00070 {
00071   FunctionalState Activation;          /*!< Cache and pre-fetch enable/disable.
00072                                             @note: All following parameters are usefull only if cache and pre-fetch are enabled. */
00073   uint32_t        CacheLock;           /*!< Locking the cache to a buffer.
00074                                             This parameter can be a value of @ref GFXMMU_CacheLock. */
00075   uint32_t        CacheLockBuffer;     /*!< Buffer on which the cache is locked.
00076                                             This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
00077                                             @note: Usefull only when lock of the cache is enabled. */
00078   uint32_t        CacheForce;          /*!< Forcing the cache regardless MPU attributes.
00079                                             This parameter can be a value of @ref GFXMMU_CacheForce.
00080                                             @note: Usefull only when lock of the cache is enabled. */
00081   uint32_t        OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
00082                                             This parameter can be a value of @ref GFXMMU_OutterBufferability. */
00083   uint32_t        OutterCachability;   /*!< Cachability of an access generated by the GFXMMU cache.
00084                                             This parameter can be a value of @ref GFXMMU_OutterCachability. */
00085   uint32_t        Prefetch;            /*!< Pre-fetch enable/disable.
00086                                             This parameter can be a value of @ref GFXMMU_Prefetch. */
00087 }GFXMMU_CachePrefetchTypeDef;
00088
00089 /**
00090   * @brief  GFXMMU interrupts structure definition
00091   */
00092 typedef struct
00093 {
00094   FunctionalState Activation;     /*!< Interrupts enable/disable */
00095   uint32_t        UsedInterrupts; /*!< Interrupts used.
00096                                        This parameter can be a values combination of @ref GFXMMU_Interrupts.
00097                                        @note: Usefull only when interrupts are enabled. */
00098 }GFXMMU_InterruptsTypeDef;
00099
00100 /**
00101   * @brief  GFXMMU init structure definition
00102   */
00103 typedef struct
00104 {
00105   uint32_t                    BlocksPerLine; /*!< Number of blocks of 16 bytes per line.
00106                                                   This parameter can be a value of @ref GFXMMU_BlocksPerLine. */
00107   uint32_t                    DefaultValue;  /*!< Value returned when virtual memory location not physically mapped. */
00108   GFXMMU_BuffersTypeDef       Buffers;       /*!< Physical buffers addresses. */
00109   GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */
00110   GFXMMU_InterruptsTypeDef    Interrupts;    /*!< Interrupts parameters. */
00111 }GFXMMU_InitTypeDef;
00112
00113 /**
00114   * @brief  GFXMMU handle structure definition
00115   */
00116 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00117 typedef struct __GFXMMU_HandleTypeDef
00118 #else
00119 typedef struct
00120 #endif
00121 {
00122   GFXMMU_TypeDef          *Instance; /*!< GFXMMU instance */
00123   GFXMMU_InitTypeDef      Init;      /*!< GFXMMU init parameters */
00124   HAL_GFXMMU_StateTypeDef State;     /*!< GFXMMU state */
00125   __IO uint32_t           ErrorCode; /*!< GFXMMU error code */
00126 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00127   void (*ErrorCallback)     (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
00128   void (*MspInitCallback)   (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
00129   void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
00130 #endif
00131 }GFXMMU_HandleTypeDef;
00132
00133 /**
00134   * @brief  GFXMMU LUT line structure definition
00135   */
00136 typedef struct
00137 {
00138   uint32_t LineNumber;        /*!< LUT line number.
00139                                    This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
00140   uint32_t LineStatus;        /*!< LUT line enable/disable.
00141                                    This parameter can be a value of @ref GFXMMU_LutLineStatus. */
00142   uint32_t FirstVisibleBlock; /*!< First visible block on this line.
00143                                    This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
00144   uint32_t LastVisibleBlock;  /*!< Last visible block on this line.
00145                                    This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
00146   int32_t  LineOffset;        /*!< Offset of block 0 of the current line in physical buffer.
00147                                    This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.
00148                                    @note: Line offset has to be computed with the following formula:
00149                                           LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
00150 }GFXMMU_LutLineTypeDef;
00151
00152 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00153 /**
00154   * @brief  GFXMMU callback ID enumeration definition
00155   */
00156 typedef enum
00157 {
00158   HAL_GFXMMU_ERROR_CB_ID     = 0x00U, /*!< GFXMMU error callback ID */
00159   HAL_GFXMMU_MSPINIT_CB_ID   = 0x01U, /*!< GFXMMU MSP init callback ID */
00160   HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U  /*!< GFXMMU MSP de-init callback ID */
00161 }HAL_GFXMMU_CallbackIDTypeDef;
00162
00163 /**
00164   * @brief  GFXMMU callback pointer definition
00165   */
00166 typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
00167 #endif
00168
00169 /**
00170   * @}
00171   */
00172 /* End of exported types -----------------------------------------------------*/
00173
00174 /* Exported constants --------------------------------------------------------*/
00175 /** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line
00180   * @{
00181   */
00182 #define GFXMMU_256BLOCKS 0x00000000U     /*!< 256 blocks of 16 bytes per line */
00183 #define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup GFXMMU_CacheLock GFXMMU cache lock
00189   * @{
00190   */
00191 #define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U  /*!< Cache not locked to a buffer */
00192 #define GFXMMU_CACHE_LOCK_ENABLE  GFXMMU_CR_CL /*!< Cache locked to a buffer */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer
00198   * @{
00199   */
00200 #define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U     /*!< Cache locked to buffer 0 */
00201 #define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */
00202 #define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */
00203 #define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB   /*!< Cache locked to buffer 3 */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup GFXMMU_CacheForce GFXMMU cache force
00209   * @{
00210   */
00211 #define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U  /*!< Caching not forced */
00212 #define GFXMMU_CACHE_FORCE_ENABLE  GFXMMU_CR_FC /*!< Caching forced */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability
00218   * @{
00219   */
00220 #define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U  /*!< No bufferable */
00221 #define GFXMMU_OUTTER_BUFFERABILITY_ENABLE  GFXMMU_CR_OB /*!< Bufferable */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability
00227   * @{
00228   */
00229 #define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U  /*!< No cachable */
00230 #define GFXMMU_OUTTER_CACHABILITY_ENABLE  GFXMMU_CR_OC /*!< Cachable */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch
00236   * @{
00237   */
00238 #define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */
00239 #define GFXMMU_PREFETCH_ENABLE  0x00000000U  /*!< Pre-fetch enable */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup GFXMMU_Interrupts GFXMMU interrupts
00245   * @{
00246   */
00247 #define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */
00248 #define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */
00249 #define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */
00250 #define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */
00251 #define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup GFXMMU_Error_Code GFXMMU Error Code
00257   * @{
00258   */
00259 #define GFXMMU_ERROR_NONE             0x00000000U    /*!< No error */
00260 #define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */
00261 #define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */
00262 #define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
00263 #define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
00264 #define GFXMMU_ERROR_AHB_MASTER       GFXMMU_SR_AMEF /*!< AHB master error */
00265 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00266 #define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U    /*!< Invalid callback error */
00267 #endif
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
00273   * @{
00274   */
00275 #define GFXMMU_LUT_LINE_DISABLE 0x00000000U     /*!< LUT line disabled */
00276 #define GFXMMU_LUT_LINE_ENABLE  GFXMMU_LUTxL_EN /*!< LUT line enabled */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter
00282   * @{
00283   */
00284 #define GFXMMU_CACHE_FORCE_FLUSH      GFXMMU_CCR_FF /*!< Force cache flush */
00285 #define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293 /* End of exported constants -------------------------------------------------*/
00294
00295 /* Exported macros -----------------------------------------------------------*/
00296 /** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
00297  * @{
00298  */
00299
00300 /** @brief  Reset GFXMMU handle state.
00301   * @param  __HANDLE__ GFXMMU handle.
00302   * @retval None
00303   */
00304 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00305 #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
00306                                                         (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
00307                                                         (__HANDLE__)->MspInitCallback = NULL;         \
00308                                                         (__HANDLE__)->MspDeInitCallback = NULL;       \
00309                                                       } while(0)
00310 #else
00311 #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
00312 #endif
00313
00314 /**
00315   * @}
00316   */
00317 /* End of exported macros ----------------------------------------------------*/
00318
00319 /* Exported functions --------------------------------------------------------*/
00320 /** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
00321   * @{
00322   */
00323
00324 /** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
00325   * @{
00326   */
00327 /* Initialization and de-initialization functions *****************************/
00328 HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
00329 HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
00330 void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
00331 void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
00332 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
00333 /* GFXMMU callbacks register/unregister functions *****************************/
00334 HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
00335                                               HAL_GFXMMU_CallbackIDTypeDef CallbackID,
00336                                               pGFXMMU_CallbackTypeDef      pCallback);
00337 HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
00338                                                 HAL_GFXMMU_CallbackIDTypeDef CallbackID);
00339 #endif
00340 /**
00341   * @}
00342   */
00343
00344 /** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
00345   * @{
00346   */
00347 /* Operation functions ********************************************************/
00348 HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
00349                                        uint32_t FirstLine,
00350                                        uint32_t LinesNumber,
00351                                        uint32_t Address);
00352
00353 HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
00354                                              uint32_t FirstLine,
00355                                              uint32_t LinesNumber);
00356
00357 HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);
00358
00359 HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);
00360
00361 HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);
00362
00363 HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
00364                                                  GFXMMU_CachePrefetchTypeDef *CachePrefetch);
00365
00366 void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
00367
00368 void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup GFXMMU_Exported_Functions_Group3 State functions
00374   * @{
00375   */
00376 /* State function *************************************************************/
00377 HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);
00378
00379 uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387 /* End of exported functions -------------------------------------------------*/
00388
00389 /* Private macros ------------------------------------------------------------*/
00390 /** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
00391 * @{
00392 */
00393 #define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \
00394                                           ((VALUE) == GFXMMU_192BLOCKS))
00395
00396 #define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
00397
00398 #define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
00399                                      ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))
00400
00401 #define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
00402                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
00403                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
00404                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))
00405
00406 #define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
00407                                       ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))
00408
00409 #define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
00410                                                ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))
00411
00412 #define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
00413                                              ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))
00414
00415 #define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
00416                                    ((VALUE) == GFXMMU_PREFETCH_ENABLE))
00417
00418 #define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
00419
00420 #define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
00421
00422 #define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
00423
00424 #define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
00425                                           ((VALUE) == GFXMMU_LUT_LINE_ENABLE))
00426
00427 #define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
00428
00429 #define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
00430
00431 #define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
00432                                              ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
00433                                              ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))
00434 /**
00435   * @}
00436   */
00437 /* End of private macros -----------------------------------------------------*/
00438
00439 /**
00440   * @}
00441   */
00442
00443 /**
00444   * @}
00445   */
00446 #endif /* GFXMMU */
00447 #ifdef __cplusplus
00448 }
00449 #endif
00450
00451 #endif /* STM32H7xx_HAL_GFXMMU_H */
00452
00453 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio.c Source File

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stm32h7xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### GPIO Peripheral features #####
00014   ==============================================================================
00015   [..]
00016     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00017         configured by software in several modes:
00018         (++) Input mode
00019         (++) Analog mode
00020         (++) Output mode
00021         (++) Alternate function mode
00022         (++) External interrupt/event lines
00023
00024     (+) During and just after reset, the alternate functions and external interrupt
00025         lines are not active and the I/O ports are configured in input floating mode.
00026
00027     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00028         activated or not.
00029
00030     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00031         type and the IO speed can be selected depending on the VDD value.
00032
00033     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00034         multiplexer that allows only one peripheral alternate function (AF) connected
00035        to an IO pin at a time. In this way, there can be no conflict between peripherals
00036        sharing the same IO pin.
00037
00038     (+) All ports have external interrupt/event capability. To use external interrupt
00039         lines, the port must be configured in input mode. All available GPIO pins are
00040         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00041
00042   The external interrupt/event controller consists of up to 23 edge detectors
00043         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00044         input line can be independently configured to select the type (interrupt or event)
00045         and the corresponding trigger event (rising or falling or both). Each line can
00046         also be masked independently.
00047
00048                      ##### How to use this driver #####
00049   ==============================================================================
00050   [..]
00051     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00052
00053     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00054         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00055         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00056              structure.
00057         (++) In case of Output or alternate function mode selection: the speed is
00058              configured through "Speed" member from GPIO_InitTypeDef structure.
00059         (++) In alternate mode is selection, the alternate function connected to the IO
00060              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00061         (++) Analog mode is required when a pin is to be used as ADC channel
00062              or DAC output.
00063         (++) In case of external interrupt/event selection the "Mode" member from
00064              GPIO_InitTypeDef structure select the type (interrupt or event) and
00065              the corresponding trigger event (rising or falling or both).
00066
00067     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00068         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00069         HAL_NVIC_EnableIRQ().
00070
00071     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00072
00073     (#) To set/reset the level of a pin configured in output mode use
00074         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00075
00076    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00077
00078
00079     (#) During and just after reset, the alternate functions are not
00080         active and the GPIO pins are configured in input floating mode (except JTAG
00081         pins).
00082
00083     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00084         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00085         priority over the GPIO function.
00086
00087     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00088         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00089         The HSE has priority over the GPIO function.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00096   * All rights reserved.</center></h2>
00097   *
00098   * This software component is licensed by ST under BSD 3-Clause license,
00099   * the "License"; You may not use this file except in compliance with the
00100   * License. You may obtain a copy of the License at:
00101   *                        opensource.org/licenses/BSD-3-Clause
00102   *
00103   ******************************************************************************
00104   */
00105
00106 /* Includes ------------------------------------------------------------------*/
00107 #include "stm32h7xx_hal.h"
00108
00109 /** @addtogroup STM32H7xx_HAL_Driver
00110   * @{
00111   */
00112
00113 /** @defgroup GPIO  GPIO
00114   * @brief GPIO HAL module driver
00115   * @{
00116   */
00117
00118 #ifdef HAL_GPIO_MODULE_ENABLED
00119
00120 /* Private typedef -----------------------------------------------------------*/
00121 /* Private defines ------------------------------------------------------------*/
00122 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00123   * @{
00124   */
00125 #define GPIO_MODE             (0x00000003U)
00126 #define ANALOG_MODE           (0x00000008U)
00127 #define EXTI_MODE             (0x10000000U)
00128 #define GPIO_MODE_IT          (0x00010000U)
00129 #define GPIO_MODE_EVT         (0x00020000U)
00130 #define RISING_EDGE           (0x00100000U)
00131 #define FALLING_EDGE          (0x00200000U)
00132 #define GPIO_OUTPUT_TYPE      (0x00000010U)
00133
00134 #if defined(DUAL_CORE)
00135 #define EXTI_CPU1             (0x01000000U)
00136 #define EXTI_CPU2             (0x02000000U)
00137 #endif /*DUAL_CORE*/
00138 #define GPIO_NUMBER           (16U)
00139 /**
00140   * @}
00141   */
00142 /* Private macro -------------------------------------------------------------*/
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145 /* Private functions ---------------------------------------------------------*/
00146 /* Exported functions --------------------------------------------------------*/
00147 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
00152  *  @brief    Initialization and Configuration functions
00153  *
00154 @verbatim
00155  ===============================================================================
00156               ##### Initialization and de-initialization functions #####
00157  ===============================================================================
00158   [..]
00159     This section provides functions allowing to initialize and de-initialize the GPIOs
00160     to be ready for use.
00161
00162 @endverbatim
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00168   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00169   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00170   *         the configuration information for the specified GPIO peripheral.
00171   * @retval None
00172   */
00173 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00174 {
00175   uint32_t position = 0x00U;
00176   uint32_t iocurrent;
00177   uint32_t temp;
00178   EXTI_Core_TypeDef *EXTI_CurrentCPU;
00179
00180 #if defined(DUAL_CORE) && defined(CORE_CM4)
00181   EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
00182 #else
00183   EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
00184 #endif
00185
00186   /* Check the parameters */
00187   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00188   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00189   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00190   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00191
00192   /* Configure the port pins */
00193   while (((GPIO_Init->Pin) >> position) != 0x00U)
00194   {
00195     /* Get current io position */
00196     iocurrent = (GPIO_Init->Pin) & (1UL << position);
00197
00198     if (iocurrent != 0x00U)
00199     {
00200       /*--------------------- GPIO Mode Configuration ------------------------*/
00201       /* In case of Alternate function mode selection */
00202       if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00203       {
00204         /* Check the Alternate function parameters */
00205         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00206         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00207
00208         /* Configure Alternate function mapped with the current IO */
00209         temp = GPIOx->AFR[position >> 3U];
00210         temp &= ~(0xFU << ((position & 0x07U) * 4U));
00211         temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
00212         GPIOx->AFR[position >> 3U] = temp;
00213       }
00214
00215       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00216       temp = GPIOx->MODER;
00217       temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
00218       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
00219       GPIOx->MODER = temp;
00220
00221       /* In case of Output or Alternate function mode selection */
00222       if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00223           (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00224       {
00225         /* Check the Speed parameter */
00226         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00227         /* Configure the IO Speed */
00228         temp = GPIOx->OSPEEDR;
00229         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
00230         temp |= (GPIO_Init->Speed << (position * 2U));
00231         GPIOx->OSPEEDR = temp;
00232
00233         /* Configure the IO Output Type */
00234         temp = GPIOx->OTYPER;
00235         temp &= ~(GPIO_OTYPER_OT0 << position) ;
00236         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
00237         GPIOx->OTYPER = temp;
00238       }
00239
00240       /* Activate the Pull-up or Pull down resistor for the current IO */
00241       temp = GPIOx->PUPDR;
00242       temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
00243       temp |= ((GPIO_Init->Pull) << (position * 2U));
00244       GPIOx->PUPDR = temp;
00245
00246       /*--------------------- EXTI Mode Configuration ------------------------*/
00247       /* Configure the External Interrupt or event for the current IO */
00248       if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00249       {
00250         /* Enable SYSCFG Clock */
00251         __HAL_RCC_SYSCFG_CLK_ENABLE();
00252
00253         temp = SYSCFG->EXTICR[position >> 2U];
00254         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
00255         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
00256         SYSCFG->EXTICR[position >> 2U] = temp;
00257
00258         /* Clear EXTI line configuration */
00259         temp = EXTI_CurrentCPU->IMR1;
00260         temp &= ~(iocurrent);
00261         if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00262         {
00263           temp |= iocurrent;
00264         }
00265         EXTI_CurrentCPU->IMR1 = temp;
00266
00267         temp = EXTI_CurrentCPU->EMR1;
00268         temp &= ~(iocurrent);
00269         if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00270         {
00271           temp |= iocurrent;
00272         }
00273         EXTI_CurrentCPU->EMR1 = temp;
00274
00275         /* Clear Rising Falling edge configuration */
00276         temp = EXTI->RTSR1;
00277         temp &= ~(iocurrent);
00278         if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00279         {
00280           temp |= iocurrent;
00281         }
00282         EXTI->RTSR1 = temp;
00283
00284         temp = EXTI->FTSR1;
00285         temp &= ~(iocurrent);
00286         if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00287         {
00288           temp |= iocurrent;
00289         }
00290         EXTI->FTSR1 = temp;
00291       }
00292     }
00293
00294     position++;
00295   }
00296 }
00297
00298 /**
00299   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00300   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00301   * @param  GPIO_Pin: specifies the port bit to be written.
00302   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00303   * @retval None
00304   */
00305 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00306 {
00307   uint32_t position = 0x00U;
00308   uint32_t iocurrent;
00309   uint32_t tmp;
00310   EXTI_Core_TypeDef *EXTI_CurrentCPU;
00311
00312 #if defined(DUAL_CORE) && defined(CORE_CM4)
00313   EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
00314 #else
00315   EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
00316 #endif
00317
00318   /* Check the parameters */
00319   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00320   assert_param(IS_GPIO_PIN(GPIO_Pin));
00321
00322   /* Configure the port pins */
00323   while ((GPIO_Pin >> position) != 0x00U)
00324   {
00325     /* Get current io position */
00326     iocurrent = GPIO_Pin & (1UL << position) ;
00327
00328     if (iocurrent != 0x00U)
00329     {
00330       /*------------------------- EXTI Mode Configuration --------------------*/
00331       /* Clear the External Interrupt or Event for the current IO */
00332       tmp = SYSCFG->EXTICR[position >> 2U];
00333       tmp &= (0x0FUL << (4U * (position & 0x03U)));
00334       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
00335       {
00336         tmp = 0x0FUL << (4U * (position & 0x03U));
00337         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
00338
00339         /* Clear EXTI line configuration for Current CPU */
00340         EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
00341         EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
00342
00343         /* Clear Rising Falling edge configuration */
00344         EXTI->RTSR1 &= ~(iocurrent);
00345         EXTI->FTSR1 &= ~(iocurrent);
00346       }
00347
00348       /*------------------------- GPIO Mode Configuration --------------------*/
00349       /* Configure IO in Analog Mode */
00350       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
00351
00352       /* Configure the default Alternate Function in current IO */
00353       GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
00354
00355       /* Configure the default value for IO Speed */
00356       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
00357
00358       /* Configure the default value IO Output Type */
00359       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
00360
00361       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00362       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
00363     }
00364
00365     position++;
00366   }
00367 }
00368
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00374  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00375  *
00376 @verbatim
00377  ===============================================================================
00378                        ##### IO operation functions #####
00379  ===============================================================================
00380
00381 @endverbatim
00382   * @{
00383   */
00384
00385 /**
00386   * @brief  Reads the specified input port pin.
00387   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00388   * @param  GPIO_Pin: specifies the port bit to read.
00389   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00390   * @retval The input port pin value.
00391   */
00392 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00393 {
00394   GPIO_PinState bitstatus;
00395
00396   /* Check the parameters */
00397   assert_param(IS_GPIO_PIN(GPIO_Pin));
00398
00399   if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
00400   {
00401     bitstatus = GPIO_PIN_SET;
00402   }
00403   else
00404   {
00405     bitstatus = GPIO_PIN_RESET;
00406   }
00407   return bitstatus;
00408 }
00409
00410 /**
00411   * @brief  Sets or clears the selected data port bit.
00412   *
00413   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
00414   *         accesses. In this way, there is no risk of an IRQ occurring between
00415   *         the read and the modify access.
00416   *
00417   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00418   * @param  GPIO_Pin: specifies the port bit to be written.
00419   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00420   * @param  PinState: specifies the value to be written to the selected bit.
00421   *          This parameter can be one of the GPIO_PinState enum values:
00422   *            @arg GPIO_PIN_RESET: to clear the port pin
00423   *            @arg GPIO_PIN_SET: to set the port pin
00424   * @retval None
00425   */
00426 void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_GPIO_PIN(GPIO_Pin));
00430   assert_param(IS_GPIO_PIN_ACTION(PinState));
00431
00432   if (PinState != GPIO_PIN_RESET)
00433   {
00434     GPIOx->BSRR = GPIO_Pin;
00435   }
00436   else
00437   {
00438     GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
00439   }
00440 }
00441
00442 /**
00443   * @brief  Toggles the specified GPIO pins.
00444   * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
00445   * @param  GPIO_Pin: Specifies the pins to be toggled.
00446   * @retval None
00447   */
00448 void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00449 {
00450   /* Check the parameters */
00451   assert_param(IS_GPIO_PIN(GPIO_Pin));
00452
00453   if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
00454   {
00455     GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
00456   }
00457   else
00458   {
00459     GPIOx->BSRR = GPIO_Pin;
00460   }
00461 }
00462
00463 /**
00464   * @brief  Locks GPIO Pins configuration registers.
00465   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00466   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00467   * @note   The configuration of the locked GPIO pins can no longer be modified
00468   *         until the next reset.
00469   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
00470   * @param  GPIO_Pin: specifies the port bit to be locked.
00471   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00472   * @retval None
00473   */
00474 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00475 {
00476   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00477
00478   /* Check the parameters */
00479   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00480   assert_param(IS_GPIO_PIN(GPIO_Pin));
00481
00482   /* Apply lock key write sequence */
00483   tmp |= GPIO_Pin;
00484   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00485   GPIOx->LCKR = tmp;
00486   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00487   GPIOx->LCKR = GPIO_Pin;
00488   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00489   GPIOx->LCKR = tmp;
00490   /* Read LCKK register. This read is mandatory to complete key lock sequence*/
00491   tmp = GPIOx->LCKR;
00492
00493   /* read again in order to confirm lock is active */
00494   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
00495   {
00496     return HAL_OK;
00497   }
00498   else
00499   {
00500     return HAL_ERROR;
00501   }
00502 }
00503
00504 /**
00505   * @brief  Handle EXTI interrupt request.
00506   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00507   * @retval None
00508   */
00509 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00510 {
00511 #if defined(DUAL_CORE) && defined(CORE_CM4)
00512   if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
00513   {
00514     __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
00515     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00516   }
00517 #else
00518   /* EXTI line interrupt detected */
00519   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
00520   {
00521     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00522     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00523   }
00524 #endif
00525 }
00526
00527 /**
00528   * @brief  EXTI line detection callback.
00529   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00530   * @retval None
00531   */
00532 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00533 {
00534   /* Prevent unused argument(s) compilation warning */
00535   UNUSED(GPIO_Pin);
00536
00537   /* NOTE: This function Should not be modified, when the callback is needed,
00538            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00539    */
00540 }
00541
00542 /**
00543   * @}
00544   */
00545
00546
00547 /**
00548   * @}
00549   */
00550
00551 #endif /* HAL_GPIO_MODULE_ENABLED */
00552 /**
00553   * @}
00554   */
00555
00556 /**
00557   * @}
00558   */
00559
00560 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio.h Source File

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stm32h7xx_hal_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_GPIO_H
00022 #define STM32H7xx_HAL_GPIO_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup GPIO
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief   GPIO Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
00050                            This parameter can be any value of @ref GPIO_pins_define */
00051
00052   uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
00053                            This parameter can be a value of @ref GPIO_mode_define */
00054
00055   uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00056                            This parameter can be a value of @ref GPIO_pull_define */
00057
00058   uint32_t Speed;     /*!< Specifies the speed for the selected pins.
00059                            This parameter can be a value of @ref GPIO_speed_define */
00060
00061   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
00062                             This parameter can be a value of @ref GPIO_Alternate_function_selection */
00063 } GPIO_InitTypeDef;
00064
00065 /**
00066   * @brief  GPIO Bit SET and Bit RESET enumeration
00067   */
00068 typedef enum
00069 {
00070   GPIO_PIN_RESET = 0U,
00071   GPIO_PIN_SET
00072 } GPIO_PinState;
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported constants --------------------------------------------------------*/
00078
00079 /** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
00080   * @{
00081   */
00082
00083 /** @defgroup GPIO_pins_define  GPIO pins define
00084   * @{
00085   */
00086 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00087 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00088 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00089 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00090 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00091 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00092 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00093 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00094 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00095 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00096 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00097 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00098 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00099 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00100 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00101 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00102 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00103
00104 #define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup GPIO_mode_define  GPIO mode define
00110   * @brief GPIO Configuration Mode
00111   *        Elements values convention: 0xX0yz00YZ
00112   *           - X  : GPIO mode or EXTI Mode
00113   *           - y  : External IT or Event trigger detection
00114   *           - z  : IO configuration on External IT or Event
00115   *           - Y  : Output type (Push Pull or Open Drain)
00116   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00117   * @{
00118   */
00119 #define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
00120 #define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
00121 #define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
00122 #define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
00123 #define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
00124
00125 #define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
00126
00127 #define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00128 #define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00129 #define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00130
00131 #define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
00132 #define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
00133 #define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup GPIO_speed_define  GPIO speed define
00139   * @brief GPIO Output Maximum frequency
00140   * @{
00141   */
00142 #define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */
00143 #define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */
00144 #define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */
00145 #define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup GPIO_pull_define  GPIO pull define
00151   * @brief GPIO Pull-Up or Pull-Down Activation
00152   * @{
00153   */
00154 #define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
00155 #define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
00156 #define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported macro ------------------------------------------------------------*/
00166 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  Checks whether the specified EXTI line flag is set or not.
00172   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00173   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00174   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00175   */
00176 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
00177
00178 /**
00179   * @brief  Clears the EXTI's line pending flags.
00180   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00181   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00182   * @retval None
00183   */
00184 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
00185
00186 /**
00187   * @brief  Checks whether the specified EXTI line is asserted or not.
00188   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00189   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00190   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00191   */
00192 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
00193
00194 /**
00195   * @brief  Clears the EXTI's line pending bits.
00196   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00197   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00198   * @retval None
00199   */
00200 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
00201
00202 #if defined(DUAL_CORE)
00203 /**
00204   * @brief  Checks whether the specified EXTI line flag is set or not.
00205   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00206   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00207   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00208   */
00209 #define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
00210
00211 /**
00212   * @brief  Clears the EXTI's line pending flags.
00213   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00214   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00215   * @retval None
00216   */
00217 #define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
00218
00219 /**
00220   * @brief  Checks whether the specified EXTI line is asserted or not.
00221   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00222   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00223   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00224   */
00225 #define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
00226
00227 /**
00228   * @brief  Clears the EXTI's line pending bits.
00229   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00230   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00231   * @retval None
00232   */
00233 #define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
00234 #endif
00235
00236 /**
00237   * @brief  Generates a Software interrupt on selected EXTI line.
00238   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00239   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00240   * @retval None
00241   */
00242 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
00243 /**
00244   * @}
00245   */
00246
00247 /* Include GPIO HAL Extension module */
00248 #include "stm32h7xx_hal_gpio_ex.h"
00249
00250 /* Exported functions --------------------------------------------------------*/
00251 /** @addtogroup GPIO_Exported_Functions
00252   * @{
00253   */
00254
00255 /** @addtogroup GPIO_Exported_Functions_Group1
00256   * @{
00257   */
00258 /* Initialization and de-initialization functions *****************************/
00259 void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00260 void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup GPIO_Exported_Functions_Group2
00266   * @{
00267   */
00268 /* IO operation functions *****************************************************/
00269 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00270 void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00271 void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00272 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00273 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00274 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283 /* Private types -------------------------------------------------------------*/
00284 /* Private variables ---------------------------------------------------------*/
00285 /* Private constants ---------------------------------------------------------*/
00286 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00287   * @{
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /* Private macros ------------------------------------------------------------*/
00295 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00296   * @{
00297   */
00298 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00299 #define IS_GPIO_PIN(__PIN__)       ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
00300                                     (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
00301 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
00302                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
00303                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
00304                             ((MODE) == GPIO_MODE_AF_PP)              ||\
00305                             ((MODE) == GPIO_MODE_AF_OD)              ||\
00306                             ((MODE) == GPIO_MODE_IT_RISING)          ||\
00307                             ((MODE) == GPIO_MODE_IT_FALLING)         ||\
00308                             ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
00309                             ((MODE) == GPIO_MODE_EVT_RISING)         ||\
00310                             ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
00311                             ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
00312                             ((MODE) == GPIO_MODE_ANALOG))
00313 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
00314                               ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
00315
00316 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
00317                             ((PULL) == GPIO_PULLDOWN))
00318
00319 /**
00320   * @}
00321   */
00322
00323 /* Private functions ---------------------------------------------------------*/
00324 /** @defgroup GPIO_Private_Functions GPIO Private Functions
00325   * @{
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 #ifdef __cplusplus
00341 }
00342 #endif
00343
00344 #endif /* STM32H7xx_HAL_GPIO_H */
00345
00346 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_gpio_ex.h Source File

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stm32h7xx_hal_gpio_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_GPIO_EX_H
00022 #define STM32H7xx_HAL_GPIO_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup GPIOEx GPIOEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /* Exported constants --------------------------------------------------------*/
00042 /** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
00047   * @{
00048   */
00049
00050 /**
00051   * @brief   AF 0 selection
00052   */
00053 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
00054 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
00055 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
00056 #define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
00057 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
00058 #if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
00059 #define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
00060 #define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
00061 #define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
00062 #define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
00063 #if defined(DUAL_CORE)
00064 #define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
00065 #define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
00066 #endif /* DUAL_CORE */
00067 #endif /* PWR_CPUCR_PDDS_D2 */
00068
00069 /**
00070   * @brief   AF 1 selection
00071   */
00072 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
00073 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
00074 #define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
00075 #define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
00076 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
00077 #if defined(HRTIM1)
00078 #define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
00079 #endif /* HRTIM1 */
00080
00081 /**
00082   * @brief   AF 2 selection
00083   */
00084 #define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
00085 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
00086 #define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
00087 #define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
00088 #define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
00089 #if defined(HRTIM1)
00090 #define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
00091 #endif /* HRTIM1 */
00092 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
00093
00094 /**
00095   * @brief   AF 3 selection
00096   */
00097 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
00098 #define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
00099 #define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
00100 #define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
00101 #define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
00102 #define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
00103 #define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
00104 #if defined(OCTOSPIM)
00105 #define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
00106 #define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
00107 #endif /* OCTOSPIM */
00108 #if defined(HRTIM1)
00109 #define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
00110 #endif /* HRTIM1 */
00111
00112 /**
00113   * @brief   AF 4 selection
00114   */
00115 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
00116 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
00117 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
00118 #define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
00119 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
00120 #define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
00121 #define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
00122 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
00123 #define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
00124 #if defined(DFSDM2_BASE)
00125 #define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
00126 #endif /* DFSDM2_BASE */
00127 #if defined(PSSI)
00128 #define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
00129 #endif /* PSSI */
00130
00131 /**
00132   * @brief   AF 5 selection
00133   */
00134 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
00135 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
00136 #define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
00137 #define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
00138 #define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
00139 #define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
00140 #define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
00141
00142 /**
00143   * @brief   AF 6 selection
00144   */
00145 #define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
00146 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
00147 #define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
00148 #define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
00149 #define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
00150 #define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
00151 #if defined(DFSDM2_BASE)
00152 #define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
00153 #endif /* DFSDM2_BASE */
00154 #if defined(SAI3)
00155 #define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
00156 #endif /* SAI3 */
00157 #if defined(OCTOSPIM)
00158 #define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
00159 #endif /* OCTOSPIM */
00160
00161 /**
00162   * @brief   AF 7 selection
00163   */
00164 #define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
00165 #define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
00166 #define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
00167 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
00168 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
00169 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
00170 #define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
00171 #define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
00172 #define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
00173 #define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */
00174
00175 /**
00176   * @brief   AF 8 selection
00177   */
00178 #define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
00179 #define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
00180 #define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
00181 #define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
00182 #define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
00183 #define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
00184 #define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
00185 #define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
00186 #if defined(SAI4)
00187 #define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
00188 #endif /* SAI4 */
00189
00190 /**
00191   * @brief   AF 9 selection
00192   */
00193 #define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
00194 #define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
00195 #define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
00196 #define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
00197 #define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
00198 #define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
00199 #define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
00200 #define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
00201 #if defined(QUADSPI)
00202 #define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
00203 #endif /* QUADSPI */
00204 #if defined(SAI4)
00205 #define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
00206 #endif /* SAI4 */
00207 #if defined(OCTOSPIM)
00208 #define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
00209 #define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
00210 #endif /* OCTOSPIM */
00211
00212 /**
00213   * @brief   AF 10 selection
00214   */
00215 #define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
00216 #define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
00217 #if defined(USB2_OTG_FS)
00218 #define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
00219 #endif /*USB2_OTG_FS*/
00220 #define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
00221 #define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
00222 #if defined(LTDC)
00223 #define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
00224 #endif /*LTDC*/
00225 #define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
00226 #if defined(QUADSPI)
00227 #define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
00228 #endif /* QUADSPI */
00229 #if defined(SAI4)
00230 #define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
00231 #endif /* SAI4 */
00232 #if !defined(USB2_OTG_FS)
00233 #define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
00234 #endif /* !USB2_OTG_FS */
00235 #define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
00236 #if defined(OCTOSPIM)
00237 #define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
00238 #endif /* OCTOSPIM */
00239 #define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
00240
00241 /**
00242   * @brief   AF 11 selection
00243   */
00244 #define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
00245 #define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
00246 #define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
00247 #define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
00248 #define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
00249 #define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
00250 #define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
00251 #define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
00252 #define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
00253 #define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
00254 #if defined(DFSDM2_BASE)
00255 #define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
00256 #endif /* DFSDM2_BASE */
00257 #if defined(USART10)
00258 #define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
00259 #endif /* USART10 */
00260 #if defined(UART9)
00261 #define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
00262 #endif /* UART9 */
00263 #if defined(ETH)
00264 #define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
00265 #endif /* ETH */
00266 #if defined(LTDC)
00267 #define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
00268 #endif /*LTDC*/
00269 #if defined(OCTOSPIM)
00270 #define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
00271 #endif /* OCTOSPIM */
00272
00273 /**
00274   * @brief   AF 12 selection
00275   */
00276 #define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
00277 #define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
00278 #define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
00279 #define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
00280 #define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
00281 #define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
00282 #define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
00283 #if defined(LTDC)
00284 #define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
00285 #endif /*LTDC*/
00286 #if defined(USB2_OTG_FS)
00287 #define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
00288 #endif /* USB2_OTG_FS */
00289
00290 /**
00291   * @brief   AF 13 selection
00292   */
00293 #define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
00294 #define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
00295 #define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
00296 #if defined(LTDC)
00297 #define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
00298 #endif /*LTDC*/
00299 #if defined(DSI)
00300 #define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
00301 #endif /* DSI */
00302 #if defined(PSSI)
00303 #define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
00304 #endif /* PSSI */
00305 #define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
00306 #define GPIO_AF13_TIM8          ((uint8_t)0x0D)    /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx  */
00307
00308 /**
00309   * @brief   AF 14 selection
00310   */
00311 #define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
00312 #define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
00313
00314 /**
00315   * @brief   AF 15 selection
00316   */
00317 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00318
00319 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
00320
00321
00322
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Exported macro ------------------------------------------------------------*/
00332 /** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
00333   * @{
00334   */
00335 /**
00336   * @}
00337   */
00338
00339 /* Exported functions --------------------------------------------------------*/
00340 /** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
00341   * @{
00342   */
00343 /**
00344   * @}
00345   */
00346 /* Private types -------------------------------------------------------------*/
00347 /* Private variables ---------------------------------------------------------*/
00348 /* Private constants ---------------------------------------------------------*/
00349 /** @defgroup GPIOEx_Private_Constants GPIO Private Constants
00350   * @{
00351   */
00352
00353 /**
00354   * @brief   GPIO pin available on the platform
00355   */
00356 /* Defines the available pins per GPIOs */
00357 #define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
00358 #define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
00359 #define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
00360 #define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
00361 #define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
00362 #define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
00363 #define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
00364 #define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
00365 #define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
00366 #define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
00367 #define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
00368                               GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
00369
00370 /**
00371   * @}
00372   */
00373
00374 /* Private macros ------------------------------------------------------------*/
00375 /** @defgroup GPIOEx_Private_Macros GPIO Private Macros
00376   * @{
00377   */
00378 /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
00379   * @{
00380   */
00381 #define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\
00382                                     ((__GPIOx__) == (GPIOB))? 1UL :\
00383                                     ((__GPIOx__) == (GPIOC))? 2UL :\
00384                                     ((__GPIOx__) == (GPIOD))? 3UL :\
00385                                     ((__GPIOx__) == (GPIOE))? 4UL :\
00386                                     ((__GPIOx__) == (GPIOF))? 5UL :\
00387                                     ((__GPIOx__) == (GPIOG))? 6UL :\
00388                                     ((__GPIOx__) == (GPIOH))? 7UL :\
00389                                     ((__GPIOx__) == (GPIOI))? 8UL :\
00390                                     ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
00396   * @{
00397   */
00398 /**
00399   * @}
00400   */
00401
00402 /**
00403   * @}
00404   */
00405
00406 /* Private functions ---------------------------------------------------------*/
00407 /** @defgroup GPIOEx_Private_Functions GPIO Private Functions
00408   * @{
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 #ifdef __cplusplus
00424 }
00425 #endif
00426
00427 #endif /* STM32H7xx_HAL_GPIO_EX_H */
00428
00429 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash.c Source File

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stm32h7xx_hal_hash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash.c
00004   * @author  MCD Application Team
00005   * @brief   HASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the HASH peripheral:
00008   *           + Initialization and de-initialization methods
00009   *           + HASH or HMAC processing in polling mode
00010   *           + HASH or HMAC processing in interrupt mode
00011   *           + HASH or HMAC processing in DMA mode
00012   *           + Peripheral State methods
00013   *           + HASH or HMAC processing suspension/resumption
00014   *
00015   @verbatim
00016  ===============================================================================
00017                      ##### How to use this driver #####
00018  ===============================================================================
00019     [..]
00020     The HASH HAL driver can be used as follows:
00021
00022     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00023         (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
00024         (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
00025             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00026             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00027             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
00028         (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
00029             (+++) Enable the DMAx interface clock using
00030                    __DMAx_CLK_ENABLE()
00031             (+++) Configure and enable one DMA stream to manage data transfer from
00032                 memory to peripheral (input stream). Managing data transfer from
00033                 peripheral to memory can be performed only using CPU.
00034             (+++) Associate the initialized DMA handle to the HASH DMA handle
00035                 using  __HAL_LINKDMA()
00036             (+++) Configure the priority and enable the NVIC for the transfer complete
00037                 interrupt on the DMA Stream: use
00038                  HAL_NVIC_SetPriority() and
00039                  HAL_NVIC_EnableIRQ()
00040
00041     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
00042         (##) resorts to HAL_HASH_MspInit() for low-level initialization,
00043         (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
00044
00045     (#)Three processing schemes are available:
00046         (##) Polling mode: processing APIs are blocking functions
00047              i.e. they process the data and wait till the digest computation is finished,
00048              e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
00049         (##) Interrupt mode: processing APIs are not blocking functions
00050                 i.e. they process the data under interrupt,
00051                 e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
00052         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00053              not used for data transfer i.e. the data transfer is ensured by DMA,
00054                 e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
00055                 for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
00056                 is then required to retrieve the digest.
00057
00058     (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
00059        initialized and processes the buffer fed in input. When the input data have all been
00060        fed to the IP, the digest computation can start.
00061
00062     (#)Multi-buffer processing is possible in polling and DMA mode.
00063         (##) In polling mode, only multi-buffer HASH processing is possible.
00064              API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
00065              User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
00066              well the computed digest.
00067
00068         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
00069               (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
00070              From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
00071              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
00072              macro then wrap-up the HASH processing in feeding the last input buffer thru the
00073              same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
00074              API HAL_HASH_xxx_Finish().
00075              (+++) HMAC processing (requires to resort to extended functions):
00076              after initialization, the key and the first input buffer are entered
00077              in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00078              starts step 2.
00079              The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
00080              point, the HMAC processing is still carrying out step 2.
00081              Then, step 2 for the last input buffer and step 3 are carried out by a single call
00082              to HAL_HMACEx_xxx_Step2_3_DMA().
00083
00084              The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
00085
00086
00087     (#)Context swapping.
00088         (##) Two APIs are available to suspend HASH or HMAC processing:
00089              (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
00090              (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
00091
00092         (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
00093             to save in memory the IP context. This context can be restored afterwards
00094             to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
00095
00096         (##) Once the HASH IP has been restored to the same configuration as that at suspension
00097              time, processing can be restarted with the same API call (same API, same handle,
00098              same parameters) as done before the suspension. Relevant parameters to restart at
00099              the proper location are internally saved in the HASH handle.
00100
00101     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00102
00103      *** Callback registration ***
00104      ===================================
00105      [..]
00106       (#) The compilation define  USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
00107           allows the user to configure dynamically the driver callbacks.
00108           Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
00109
00110       (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
00111             (+) InCpltCallback    : callback for input completion.
00112             (+) DgstCpltCallback  : callback for digest computation completion.
00113             (+) ErrorCallback     : callback for error.
00114             (+) MspInitCallback   : HASH MspInit.
00115             (+) MspDeInitCallback : HASH MspDeInit.
00116           This function takes as parameters the HAL peripheral handle, the Callback ID
00117           and a pointer to the user callback function.
00118
00119       (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
00120           weak (surcharged) function.
00121           @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00122           and the Callback ID.
00123           This function allows to reset following callbacks:
00124             (+) InCpltCallback    : callback for input completion.
00125             (+) DgstCpltCallback  : callback for digest computation completion.
00126             (+) ErrorCallback     : callback for error.
00127             (+) MspInitCallback   : HASH MspInit.
00128             (+) MspDeInitCallback : HASH MspDeInit.
00129
00130       (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
00131           all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00132           examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
00133           Exception done for MspInit and MspDeInit callbacks that are respectively
00134           reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
00135           and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
00136           If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
00137           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00138
00139           Callbacks can be registered/unregistered in READY state only.
00140           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00141           in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00142           during the Init/DeInit.
00143           In that case first register the MspInit/MspDeInit user callbacks
00144           using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
00145           or @ref HAL_HASH_Init function.
00146
00147           When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
00148           not defined, the callback registering feature is not available
00149           and weak (surcharged) callbacks are used.
00150
00151   @endverbatim
00152   ******************************************************************************
00153   * @attention
00154   *
00155   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00156   * All rights reserved.</center></h2>
00157   *
00158   * This software component is licensed by ST under BSD 3-Clause license,
00159   * the "License"; You may not use this file except in compliance with the
00160   * License. You may obtain a copy of the License at:
00161   *                        opensource.org/licenses/BSD-3-Clause
00162   *
00163   ******************************************************************************
00164   */
00165
00166 /* Includes ------------------------------------------------------------------*/
00167 #include "stm32h7xx_hal.h"
00168
00169
00170 /** @addtogroup STM32H7xx_HAL_Driver
00171   * @{
00172   */
00173 #if defined (HASH)
00174
00175 /** @defgroup HASH  HASH
00176   * @brief HASH HAL module driver.
00177   * @{
00178   */
00179
00180 #ifdef HAL_HASH_MODULE_ENABLED
00181
00182 /* Private typedef -----------------------------------------------------------*/
00183 /* Private define ------------------------------------------------------------*/
00184 /** @defgroup HASH_Private_Constants HASH Private Constants
00185   * @{
00186   */
00187
00188 /** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
00189   * @{
00190   */
00191 #define HASH_DIGEST_CALCULATION_NOT_STARTED       ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
00192 #define HASH_DIGEST_CALCULATION_STARTED           ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register     */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
00198   * @{
00199   */
00200 #define HASH_NUMBER_OF_CSR_REGISTERS              54U     /*!< Number of Context Swap Registers */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup HASH_TimeOut_Value HASH TimeOut Value
00206   * @{
00207   */
00208 #define HASH_TIMEOUTVALUE                         1000U   /*!< Time-out value  */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
00214   * @{
00215   */
00216 #define HASH_DMA_SUSPENSION_WORDS_LIMIT             20U   /*!< Number of words below which DMA suspension is aborted */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /* Private macro -------------------------------------------------------------*/
00226 /* Private variables ---------------------------------------------------------*/
00227 /* Private function prototypes -----------------------------------------------*/
00228 /** @defgroup HASH_Private_Functions HASH Private Functions
00229   * @{
00230   */
00231 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
00232 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
00233 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00234 static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00235 static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00236 static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
00237 static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
00238 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup HASH_Exported_Functions HASH Exported Functions
00244   * @{
00245   */
00246
00247 /** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00248  *  @brief    Initialization, configuration and call-back functions.
00249  *
00250 @verbatim
00251  ===============================================================================
00252               ##### Initialization and de-initialization functions #####
00253  ===============================================================================
00254     [..]  This section provides functions allowing to:
00255       (+) Initialize the HASH according to the specified parameters
00256           in the HASH_InitTypeDef and create the associated handle
00257       (+) DeInitialize the HASH peripheral
00258       (+) Initialize the HASH MCU Specific Package (MSP)
00259       (+) DeInitialize the HASH MSP
00260
00261     [..]  This section provides as well call back functions definitions for user
00262           code to manage:
00263       (+) Input data transfer to IP completion
00264       (+) Calculated digest retrieval completion
00265       (+) Error management
00266
00267
00268
00269 @endverbatim
00270   * @{
00271   */
00272
00273 /**
00274   * @brief  Initialize the HASH according to the specified parameters in the
00275             HASH_HandleTypeDef and create the associated handle.
00276   * @note   Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
00277   *         other configuration bits are set by HASH or HMAC processing APIs.
00278   * @note   MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
00279   *         multi-buffer HASH processing, user needs to resort to
00280   *         __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
00281   *         relevant APIs manage themselves the MDMAT bit.
00282   * @param  hhash: HASH handle
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
00286 {
00287   /* Check the hash handle allocation */
00288   if(hhash == NULL)
00289   {
00290     return HAL_ERROR;
00291   }
00292
00293   /* Check the parameters */
00294   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
00295
00296 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00297   if (hhash->State == HAL_HASH_STATE_RESET)
00298   {
00299     /* Allocate lock resource and initialize it */
00300     hhash->Lock = HAL_UNLOCKED;
00301
00302     /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
00303     hhash->InCpltCallback =  HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
00304     hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
00305     hhash->ErrorCallback =  HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
00306     if(hhash->MspInitCallback == NULL)
00307     {
00308       hhash->MspInitCallback = HAL_HASH_MspInit;
00309     }
00310
00311     /* Init the low level hardware */
00312     hhash->MspInitCallback(hhash);
00313   }
00314 #else
00315   if(hhash->State == HAL_HASH_STATE_RESET)
00316   {
00317     /* Allocate lock resource and initialize it */
00318     hhash->Lock = HAL_UNLOCKED;
00319
00320     /* Init the low level hardware */
00321     HAL_HASH_MspInit(hhash);
00322   }
00323 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
00324
00325     /* Change the HASH state */
00326   hhash->State = HAL_HASH_STATE_BUSY;
00327
00328   /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
00329   hhash->HashInCount = 0;
00330   hhash->HashBuffSize = 0;
00331   hhash->HashITCounter = 0;
00332   hhash->NbWordsAlreadyPushed = 0;
00333   /* Reset digest calculation bridle (MDMAT bit control) */
00334   hhash->DigestCalculationDisable = RESET;
00335   /* Set phase to READY */
00336   hhash->Phase = HAL_HASH_PHASE_READY;
00337
00338   /* Set the data type bit */
00339   MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
00340   /* Reset MDMAT bit */
00341 __HAL_HASH_RESET_MDMAT();
00342   /* Reset HASH handle status */
00343   hhash->Status = HAL_OK;
00344
00345   /* Set the HASH state to Ready */
00346   hhash->State = HAL_HASH_STATE_READY;
00347
00348   /* Initialise the error code */
00349   hhash->ErrorCode = HAL_HASH_ERROR_NONE;
00350
00351   /* Return function status */
00352   return HAL_OK;
00353 }
00354
00355 /**
00356   * @brief  DeInitialize the HASH peripheral.
00357   * @param  hhash: HASH handle.
00358   * @retval HAL status
00359   */
00360 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
00361 {
00362   /* Check the HASH handle allocation */
00363   if(hhash == NULL)
00364   {
00365     return HAL_ERROR;
00366   }
00367
00368   /* Change the HASH state */
00369   hhash->State = HAL_HASH_STATE_BUSY;
00370
00371   /* Set the default HASH phase */
00372   hhash->Phase = HAL_HASH_PHASE_READY;
00373
00374   /* Reset HashInCount, HashITCounter and HashBuffSize */
00375   hhash->HashInCount = 0;
00376   hhash->HashBuffSize = 0;
00377   hhash->HashITCounter = 0;
00378   /* Reset digest calculation bridle (MDMAT bit control) */
00379   hhash->DigestCalculationDisable = RESET;
00380
00381 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00382     if(hhash->MspDeInitCallback == NULL)
00383     {
00384       hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
00385     }
00386
00387     /* DeInit the low level hardware */
00388     hhash->MspDeInitCallback(hhash);
00389 #else
00390   /* DeInit the low level hardware: CLOCK, NVIC */
00391   HAL_HASH_MspDeInit(hhash);
00392 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
00393
00394
00395   /* Reset HASH handle status */
00396   hhash->Status = HAL_OK;
00397
00398   /* Set the HASH state to Ready */
00399   hhash->State = HAL_HASH_STATE_RESET;
00400
00401   /* Initialise the error code */
00402   hhash->ErrorCode = HAL_HASH_ERROR_NONE;
00403
00404   /* Return function status */
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief  Initialize the HASH MSP.
00410   * @param  hhash: HASH handle.
00411   * @retval None
00412   */
00413 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
00414 {
00415   /* Prevent unused argument(s) compilation warning */
00416   UNUSED(hhash);
00417
00418   /* NOTE : This function should not be modified; when the callback is needed,
00419             HAL_HASH_MspInit() can be implemented in the user file.
00420    */
00421 }
00422
00423 /**
00424   * @brief  DeInitialize the HASH MSP.
00425   * @param  hhash: HASH handle.
00426   * @retval None
00427   */
00428 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
00429 {
00430   /* Prevent unused argument(s) compilation warning */
00431   UNUSED(hhash);
00432
00433   /* NOTE : This function should not be modified; when the callback is needed,
00434             HAL_HASH_MspDeInit() can be implemented in the user file.
00435    */
00436 }
00437
00438 /**
00439   * @brief  Input data transfer complete call back.
00440   * @note   HAL_HASH_InCpltCallback() is called when the complete input message
00441   *         has been fed to the IP. This API is invoked only when input data are
00442   *         entered under interruption or thru DMA.
00443   * @note   In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
00444   *         HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
00445   *         to the IP.
00446   * @param  hhash: HASH handle.
00447   * @retval None
00448   */
00449 __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
00450 {
00451   /* Prevent unused argument(s) compilation warning */
00452   UNUSED(hhash);
00453
00454   /* NOTE : This function should not be modified; when the callback is needed,
00455             HAL_HASH_InCpltCallback() can be implemented in the user file.
00456    */
00457 }
00458
00459 /**
00460   * @brief  Digest computation complete call back.
00461   * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not
00462   *         relevant with DMA.
00463   * @param  hhash: HASH handle.
00464   * @retval None
00465   */
00466 __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
00467 {
00468   /* Prevent unused argument(s) compilation warning */
00469   UNUSED(hhash);
00470
00471   /* NOTE : This function should not be modified; when the callback is needed,
00472             HAL_HASH_DgstCpltCallback() can be implemented in the user file.
00473    */
00474 }
00475
00476 /**
00477   * @brief  Error callback.
00478   * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
00479   *         to retrieve the error type.
00480   * @param  hhash: HASH handle.
00481   * @retval None
00482   */
00483 __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
00484 {
00485   /* Prevent unused argument(s) compilation warning */
00486   UNUSED(hhash);
00487
00488   /* NOTE : This function should not be modified; when the callback is needed,
00489             HAL_HASH_ErrorCallback() can be implemented in the user file.
00490    */
00491 }
00492
00493 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00494 /**
00495   * @brief  Register a User HASH Callback
00496   *         To be used instead of the weak (surcharged) predefined callback
00497   * @param hhash HASH handle
00498   * @param CallbackID ID of the callback to be registered
00499   *        This parameter can be one of the following values:
00500   *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
00501   *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
00502   *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
00503   *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
00504   *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
00505   * @param pCallback pointer to the Callback function
00506   * @retval status
00507   */
00508 HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
00509 {
00510   HAL_StatusTypeDef status = HAL_OK;
00511
00512   if(pCallback == NULL)
00513   {
00514     /* Update the error code */
00515     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00516     return HAL_ERROR;
00517   }
00518   /* Process locked */
00519   __HAL_LOCK(hhash);
00520
00521   if(HAL_HASH_STATE_READY == hhash->State)
00522   {
00523     switch (CallbackID)
00524     {
00525     case HAL_HASH_INPUTCPLT_CB_ID :
00526       hhash->InCpltCallback = pCallback;
00527       break;
00528
00529     case HAL_HASH_DGSTCPLT_CB_ID :
00530       hhash->DgstCpltCallback = pCallback;
00531       break;
00532
00533     case HAL_HASH_ERROR_CB_ID :
00534       hhash->ErrorCallback = pCallback;
00535       break;
00536
00537     case HAL_HASH_MSPINIT_CB_ID :
00538       hhash->MspInitCallback = pCallback;
00539       break;
00540
00541     case HAL_HASH_MSPDEINIT_CB_ID :
00542       hhash->MspDeInitCallback = pCallback;
00543       break;
00544
00545     default :
00546      /* Update the error code */
00547      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00548      /* update return status */
00549       status =  HAL_ERROR;
00550       break;
00551     }
00552   }
00553   else if(HAL_HASH_STATE_RESET == hhash->State)
00554   {
00555     switch (CallbackID)
00556     {
00557     case HAL_HASH_MSPINIT_CB_ID :
00558       hhash->MspInitCallback = pCallback;
00559       break;
00560
00561     case HAL_HASH_MSPDEINIT_CB_ID :
00562       hhash->MspDeInitCallback = pCallback;
00563       break;
00564
00565     default :
00566      /* Update the error code */
00567      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00568      /* update return status */
00569       status =  HAL_ERROR;
00570       break;
00571     }
00572   }
00573   else
00574   {
00575     /* Update the error code */
00576      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00577      /* update return status */
00578       status =  HAL_ERROR;
00579   }
00580
00581   /* Release Lock */
00582   __HAL_UNLOCK(hhash);
00583   return status;
00584 }
00585
00586 /**
00587   * @brief  Unregister a HASH Callback
00588   *         HASH Callback is redirected to the weak (surcharged) predefined callback
00589   * @param hhash HASH handle
00590   * @param CallbackID ID of the callback to be unregistered
00591   *        This parameter can be one of the following values:
00592   *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
00593   *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
00594   *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
00595   *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
00596   *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
00597   * @retval status
00598   */
00599 HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
00600 {
00601 HAL_StatusTypeDef status = HAL_OK;
00602
00603   /* Process locked */
00604   __HAL_LOCK(hhash);
00605
00606   if(HAL_HASH_STATE_READY == hhash->State)
00607   {
00608     switch (CallbackID)
00609     {
00610     case HAL_HASH_INPUTCPLT_CB_ID :
00611       hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
00612       break;
00613
00614     case HAL_HASH_DGSTCPLT_CB_ID :
00615       hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
00616       break;
00617
00618     case HAL_HASH_ERROR_CB_ID :
00619       hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
00620       break;
00621
00622     case HAL_HASH_MSPINIT_CB_ID :
00623       hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
00624       break;
00625
00626     case HAL_HASH_MSPDEINIT_CB_ID :
00627       hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
00628       break;
00629
00630     default :
00631      /* Update the error code */
00632      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00633      /* update return status */
00634       status =  HAL_ERROR;
00635       break;
00636     }
00637   }
00638   else if(HAL_HASH_STATE_RESET == hhash->State)
00639   {
00640     switch (CallbackID)
00641     {
00642     case HAL_HASH_MSPINIT_CB_ID :
00643       hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
00644       break;
00645
00646     case HAL_HASH_MSPDEINIT_CB_ID :
00647       hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
00648       break;
00649
00650     default :
00651      /* Update the error code */
00652      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00653      /* update return status */
00654       status =  HAL_ERROR;
00655       break;
00656     }
00657   }
00658   else
00659   {
00660      /* Update the error code */
00661      hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
00662      /* update return status */
00663       status =  HAL_ERROR;
00664   }
00665
00666   /* Release Lock */
00667   __HAL_UNLOCK(hhash);
00668   return status;
00669 }
00670 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
00677  *  @brief   HASH processing functions using polling mode.
00678  *
00679 @verbatim
00680  ===============================================================================
00681                  ##### Polling mode HASH processing functions #####
00682  ===============================================================================
00683     [..]  This section provides functions allowing to calculate in polling mode
00684           the hash value using one of the following algorithms:
00685       (+) MD5
00686          (++) HAL_HASH_MD5_Start()
00687          (++) HAL_HASH_MD5_Accumulate()
00688       (+) SHA1
00689          (++) HAL_HASH_SHA1_Start()
00690          (++) HAL_HASH_SHA1_Accumulate()
00691
00692     [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
00693
00694     [..]  In case of multi-buffer HASH processing (a single digest is computed while
00695           several buffers are fed to the IP), the user can resort to successive calls
00696           to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
00697           to HAL_HASH_xxx_Start().
00698
00699 @endverbatim
00700   * @{
00701   */
00702
00703 /**
00704   * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
00705   *         read the computed digest.
00706   * @note   Digest is available in pOutBuffer.
00707   * @param  hhash: HASH handle.
00708   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00709   * @param  Size: length of the input buffer in bytes.
00710   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00711   * @param  Timeout: Timeout value
00712   * @retval HAL status
00713   */
00714 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00715 {
00716   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
00717 }
00718
00719 /**
00720   * @brief  If not already done, initialize the HASH peripheral in MD5 mode then
00721   *         processes pInBuffer.
00722   * @note   Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
00723   *         several input buffers back-to-back to the IP that will yield a single
00724   *         HASH signature once all buffers have been entered. Wrap-up of input
00725   *         buffers feeding and retrieval of digest is done by a call to
00726   *         HAL_HASH_MD5_Start().
00727   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00728   *         the IP has already been initialized.
00729   * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
00730   *         to read it, feeding at the same time the last input buffer to the IP.
00731   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00732   *         HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
00733   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00734   * @param  hhash: HASH handle.
00735   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00736   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00737   * @retval HAL status
00738   */
00739 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00740 {
00741   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
00742 }
00743
00744 /**
00745   * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
00746   *         read the computed digest.
00747   * @note   Digest is available in pOutBuffer.
00748   * @param  hhash: HASH handle.
00749   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00750   * @param  Size: length of the input buffer in bytes.
00751   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00752   * @param  Timeout: Timeout value
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00756 {
00757   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
00758 }
00759
00760 /**
00761   * @brief  If not already done, initialize the HASH peripheral in SHA1 mode then
00762   *         processes pInBuffer.
00763   * @note   Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
00764   *         several input buffers back-to-back to the IP that will yield a single
00765   *         HASH signature once all buffers have been entered. Wrap-up of input
00766   *         buffers feeding and retrieval of digest is done by a call to
00767   *         HAL_HASH_SHA1_Start().
00768   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00769   *         the IP has already been initialized.
00770   * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
00771   *         to read it, feeding at the same time the last input buffer to the IP.
00772   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00773   *         HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
00774   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00775   * @param  hhash: HASH handle.
00776   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00777   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00778   * @retval HAL status
00779   */
00780 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00781 {
00782   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
00783 }
00784
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
00791  *  @brief   HASH processing functions using interrupt mode.
00792  *
00793 @verbatim
00794  ===============================================================================
00795                  ##### Interruption mode HASH processing functions #####
00796  ===============================================================================
00797     [..]  This section provides functions allowing to calculate in interrupt mode
00798           the hash value using one of the following algorithms:
00799       (+) MD5
00800          (++) HAL_HASH_MD5_Start_IT()
00801       (+) SHA1
00802          (++) HAL_HASH_SHA1_Start_IT()
00803
00804     [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.
00805
00806     [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
00807          HMAC processing mode.
00808
00809
00810 @endverbatim
00811   * @{
00812   */
00813
00814 /**
00815   * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
00816   *         read the computed digest in interruption mode.
00817   * @note   Digest is available in pOutBuffer.
00818   * @param  hhash: HASH handle.
00819   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00820   * @param  Size: length of the input buffer in bytes.
00821   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00822   * @retval HAL status
00823   */
00824 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00825 {
00826   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
00827 }
00828
00829
00830 /**
00831   * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
00832   *         read the computed digest in interruption mode.
00833   * @note   Digest is available in pOutBuffer.
00834   * @param  hhash: HASH handle.
00835   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00836   * @param  Size: length of the input buffer in bytes.
00837   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00838   * @retval HAL status
00839   */
00840 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00841 {
00842   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
00843 }
00844
00845 /**
00846   * @brief Handle HASH interrupt request.
00847   * @param hhash: HASH handle.
00848   * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
00849   * @note  In case of error reported during the HASH interruption processing,
00850   *        HAL_HASH_ErrorCallback() API is called so that user code can
00851   *        manage the error. The error type is available in hhash->Status field.
00852   * @retval None
00853   */
00854 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
00855 {
00856   hhash->Status = HASH_IT(hhash);
00857   if (hhash->Status != HAL_OK)
00858   {
00859     hhash->ErrorCode |= HAL_HASH_ERROR_IT;
00860 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00861     hhash->ErrorCallback(hhash);
00862 #else
00863     HAL_HASH_ErrorCallback(hhash);
00864 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00865     /* After error handling by code user, reset HASH handle HAL status */
00866     hhash->Status = HAL_OK;
00867   }
00868 }
00869
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
00875  *  @brief   HASH processing functions using DMA mode.
00876  *
00877 @verbatim
00878  ===============================================================================
00879                     ##### DMA mode HASH processing functions #####
00880  ===============================================================================
00881     [..]  This section provides functions allowing to calculate in DMA mode
00882           the hash value using one of the following algorithms:
00883       (+) MD5
00884          (++) HAL_HASH_MD5_Start_DMA()
00885          (++) HAL_HASH_MD5_Finish()
00886       (+) SHA1
00887          (++) HAL_HASH_SHA1_Start_DMA()
00888          (++) HAL_HASH_SHA1_Finish()
00889
00890     [..]  When resorting to DMA mode to enter the data in the IP, user must resort
00891           to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
00892           HAL_HASH_xxx_Finish().
00893     [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
00894           the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
00895           reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
00896           retrieved thanks to HAL_HASH_xxx_Finish().
00897
00898 @endverbatim
00899   * @{
00900   */
00901
00902 /**
00903   * @brief  Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
00904   *         to feed the input buffer to the IP.
00905   * @note   Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
00906   *         be called to retrieve the computed digest.
00907   * @param  hhash: HASH handle.
00908   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00909   * @param  Size: length of the input buffer in bytes.
00910   * @retval HAL status
00911   */
00912 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00913 {
00914   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00915 }
00916
00917 /**
00918   * @brief  Return the computed digest in MD5 mode.
00919   * @note   The API waits for DCIS to be set then reads the computed digest.
00920   * @note   HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
00921   *         HMAC MD5 mode.
00922   * @param  hhash: HASH handle.
00923   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00924   * @param  Timeout: Timeout value.
00925   * @retval HAL status
00926   */
00927 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00928 {
00929    return HASH_Finish(hhash, pOutBuffer, Timeout);
00930 }
00931
00932 /**
00933   * @brief  Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
00934   *         to feed the input buffer to the IP.
00935   * @note   Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
00936   *         be called to retrieve the computed digest.
00937   * @param  hhash: HASH handle.
00938   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00939   * @param  Size: length of the input buffer in bytes.
00940   * @retval HAL status
00941   */
00942 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00943 {
00944   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00945 }
00946
00947
00948 /**
00949   * @brief  Return the computed digest in SHA1 mode.
00950   * @note   The API waits for DCIS to be set then reads the computed digest.
00951   * @note   HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
00952   *         HMAC SHA1 mode.
00953   * @param  hhash: HASH handle.
00954   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00955   * @param  Timeout: Timeout value.
00956   * @retval HAL status
00957   */
00958 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00959 {
00960    return HASH_Finish(hhash, pOutBuffer, Timeout);
00961 }
00962
00963 /**
00964   * @}
00965   */
00966
00967 /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
00968  *  @brief   HMAC processing functions using polling mode.
00969  *
00970 @verbatim
00971  ===============================================================================
00972                  ##### Polling mode HMAC processing functions #####
00973  ===============================================================================
00974     [..]  This section provides functions allowing to calculate in polling mode
00975           the HMAC value using one of the following algorithms:
00976       (+) MD5
00977          (++) HAL_HMAC_MD5_Start()
00978       (+) SHA1
00979          (++) HAL_HMAC_SHA1_Start()
00980
00981
00982 @endverbatim
00983   * @{
00984   */
00985
00986 /**
00987   * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
00988   *         read the computed digest.
00989   * @note   Digest is available in pOutBuffer.
00990   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00991   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00992   * @param  hhash: HASH handle.
00993   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00994   * @param  Size: length of the input buffer in bytes.
00995   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00996   * @param  Timeout: Timeout value.
00997   * @retval HAL status
00998   */
00999 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01000 {
01001   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
01002 }
01003
01004 /**
01005   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
01006   *         read the computed digest.
01007   * @note   Digest is available in pOutBuffer.
01008   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
01009   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
01010   * @param  hhash: HASH handle.
01011   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01012   * @param  Size: length of the input buffer in bytes.
01013   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
01014   * @param  Timeout: Timeout value.
01015   * @retval HAL status
01016   */
01017 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01018 {
01019   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
01020 }
01021
01022 /**
01023   * @}
01024   */
01025
01026
01027 /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
01028  *  @brief   HMAC processing functions using interrupt mode.
01029  *
01030 @verbatim
01031  ===============================================================================
01032                  ##### Interrupt mode HMAC processing functions #####
01033  ===============================================================================
01034     [..]  This section provides functions allowing to calculate in interrupt mode
01035           the HMAC value using one of the following algorithms:
01036       (+) MD5
01037          (++) HAL_HMAC_MD5_Start_IT()
01038       (+) SHA1
01039          (++) HAL_HMAC_SHA1_Start_IT()
01040
01041 @endverbatim
01042   * @{
01043   */
01044
01045
01046 /**
01047   * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
01048   *         read the computed digest in interrupt mode.
01049   * @note   Digest is available in pOutBuffer.
01050   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
01051   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
01052   * @param  hhash: HASH handle.
01053   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01054   * @param  Size: length of the input buffer in bytes.
01055   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
01056   * @retval HAL status
01057   */
01058 HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
01059 {
01060   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
01061 }
01062
01063 /**
01064   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
01065   *         read the computed digest in interrupt mode.
01066   * @note   Digest is available in pOutBuffer.
01067   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
01068   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
01069   * @param  hhash: HASH handle.
01070   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01071   * @param  Size: length of the input buffer in bytes.
01072   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
01073   * @retval HAL status
01074   */
01075 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
01076 {
01077   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
01078 }
01079
01080 /**
01081   * @}
01082   */
01083
01084
01085
01086 /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
01087  *  @brief   HMAC processing functions using DMA modes.
01088  *
01089 @verbatim
01090  ===============================================================================
01091                  ##### DMA mode HMAC processing functions #####
01092  ===============================================================================
01093     [..]  This section provides functions allowing to calculate in DMA mode
01094           the HMAC value using one of the following algorithms:
01095       (+) MD5
01096          (++) HAL_HMAC_MD5_Start_DMA()
01097       (+) SHA1
01098          (++) HAL_HMAC_SHA1_Start_DMA()
01099
01100     [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
01101           user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
01102           with HAL_HASH_xxx_Finish().
01103
01104 @endverbatim
01105   * @{
01106   */
01107
01108
01109 /**
01110   * @brief  Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
01111   *         DMA transfers to feed the key and the input buffer to the IP.
01112   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
01113   *         to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
01114   *         the computed digest.
01115   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
01116   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
01117   * @note   If MDMAT bit is set before calling this function (multi-buffer
01118   *          HASH processing case), the input buffer size (in bytes) must be
01119   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
01120   *          For the processing of the last buffer of the thread, MDMAT bit must
01121   *          be reset and the buffer length (in bytes) doesn't have to be a
01122   *          multiple of 4.
01123   * @param  hhash: HASH handle.
01124   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01125   * @param  Size: length of the input buffer in bytes.
01126   * @retval HAL status
01127   */
01128 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01129 {
01130   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
01131 }
01132
01133
01134 /**
01135   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
01136   *         DMA transfers to feed the key and the input buffer to the IP.
01137   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
01138   *         to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
01139   *         the computed digest.
01140   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
01141   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
01142   * @note   If MDMAT bit is set before calling this function (multi-buffer
01143   *          HASH processing case), the input buffer size (in bytes) must be
01144   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
01145   *          For the processing of the last buffer of the thread, MDMAT bit must
01146   *          be reset and the buffer length (in bytes) doesn't have to be a
01147   *          multiple of 4.
01148   * @param  hhash: HASH handle.
01149   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01150   * @param  Size: length of the input buffer in bytes.
01151   * @retval HAL status
01152   */
01153 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01154 {
01155   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
01156 }
01157
01158 /**
01159   * @}
01160   */
01161
01162 /** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
01163  *  @brief   Peripheral State functions.
01164  *
01165 @verbatim
01166  ===============================================================================
01167                       ##### Peripheral State methods #####
01168  ===============================================================================
01169     [..]
01170     This section permits to get in run-time the state and the peripheral handle
01171     status of the peripheral:
01172       (+) HAL_HASH_GetState()
01173       (+) HAL_HASH_GetStatus()
01174
01175     [..]
01176     Additionally, this subsection provides functions allowing to save and restore
01177     the HASH or HMAC processing context in case of calculation suspension:
01178       (+) HAL_HASH_ContextSaving()
01179       (+) HAL_HASH_ContextRestoring()
01180
01181     [..]
01182     This subsection provides functions allowing to suspend the HASH processing
01183       (+) when input are fed to the IP by software
01184           (++) HAL_HASH_SwFeed_ProcessSuspend()
01185       (+) when input are fed to the IP by DMA
01186           (++) HAL_HASH_DMAFeed_ProcessSuspend()
01187
01188
01189
01190 @endverbatim
01191   * @{
01192   */
01193
01194 /**
01195   * @brief  Return the HASH handle state.
01196   * @note   The API yields the current state of the handle (BUSY, READY,...).
01197   * @param  hhash: HASH handle.
01198   * @retval HAL HASH state
01199   */
01200 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
01201 {
01202   return hhash->State;
01203 }
01204
01205
01206 /**
01207   * @brief Return the HASH HAL status.
01208   * @note  The API yields the HAL status of the handle: it is the result of the
01209   *        latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
01210   * @param  hhash: HASH handle.
01211   * @retval HAL status
01212   */
01213 HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
01214 {
01215   return hhash->Status;
01216 }
01217
01218 /**
01219   * @brief  Save the HASH context in case of processing suspension.
01220   * @param  hhash: HASH handle.
01221   * @param  pMemBuffer: pointer to the memory buffer where the HASH context
01222   *         is saved.
01223   * @note   The IMR, STR, CR then all the CSR registers are saved
01224   *         in that order. Only the r/w bits are read to be restored later on.
01225   * @note   By default, all the context swap registers (there are
01226   *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
01227   * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
01228   *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
01229   * @retval None
01230   */
01231 void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
01232 {
01233   uint32_t mem_ptr = (uint32_t)pMemBuffer;
01234   uint32_t csr_ptr = (uint32_t)HASH->CSR;
01235   uint32_t i;
01236
01237   /* Prevent unused argument(s) compilation warning */
01238   UNUSED(hhash);
01239
01240   /* Save IMR register content */
01241   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
01242   mem_ptr+=4U;
01243   /* Save STR register content */
01244   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
01245   mem_ptr+=4U;
01246   /* Save CR register content */
01247   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
01248   mem_ptr+=4U;
01249   /* By default, save all CSRs registers */
01250   for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
01251   {
01252     *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
01253     mem_ptr+=4U;
01254     csr_ptr+=4U;
01255   }
01256 }
01257
01258
01259 /**
01260   * @brief  Restore the HASH context in case of processing resumption.
01261   * @param  hhash: HASH handle.
01262   * @param  pMemBuffer: pointer to the memory buffer where the HASH context
01263   *         is stored.
01264   * @note   The IMR, STR, CR then all the CSR registers are restored
01265   *         in that order. Only the r/w bits are restored.
01266   * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
01267   *         of those) are restored (all of them have been saved by default
01268   *         beforehand).
01269   * @retval None
01270   */
01271 void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
01272 {
01273   uint32_t mem_ptr = (uint32_t)pMemBuffer;
01274   uint32_t csr_ptr = (uint32_t)HASH->CSR;
01275   uint32_t i;
01276
01277   /* Prevent unused argument(s) compilation warning */
01278   UNUSED(hhash);
01279
01280   /* Restore IMR register content */
01281   WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
01282   mem_ptr+=4U;
01283   /* Restore STR register content */
01284   WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
01285   mem_ptr+=4U;
01286   /* Restore CR register content */
01287   WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
01288   mem_ptr+=4U;
01289
01290   /* Reset the HASH processor before restoring the Context
01291   Swap Registers (CSR) */
01292   __HAL_HASH_INIT();
01293
01294   /* By default, restore all CSR registers */
01295   for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
01296   {
01297     WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
01298     mem_ptr+=4U;
01299     csr_ptr+=4U;
01300   }
01301 }
01302
01303
01304 /**
01305   * @brief  Initiate HASH processing suspension when in polling or interruption mode.
01306   * @param  hhash: HASH handle.
01307   * @note   Set the handle field SuspendRequest to the appropriate value so that
01308   *         the on-going HASH processing is suspended as soon as the required
01309   *         conditions are met. Note that the actual suspension is carried out
01310   *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
01311   *         interruption mode.
01312   * @retval None
01313   */
01314 void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
01315 {
01316   /* Set Handle Suspend Request field */
01317   hhash->SuspendRequest = HAL_HASH_SUSPEND;
01318 }
01319
01320 /**
01321   * @brief  Suspend the HASH processing when in DMA mode.
01322   * @param  hhash: HASH handle.
01323   * @note   When suspension attempt occurs at the very end of a DMA transfer and
01324   *         all the data have already been entered in the IP, hhash->State is
01325   *         set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
01326   *         recommended to wrap-up the processing in reading the digest as usual.
01327   * @retval HAL status
01328   */
01329 HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
01330 {
01331   uint32_t tmp_remaining_DMATransferSize_inWords;
01332   uint32_t tmp_initial_DMATransferSize_inWords;
01333   uint32_t tmp_words_already_pushed;
01334
01335   if (hhash->State == HAL_HASH_STATE_READY)
01336   {
01337     return HAL_ERROR;
01338   }
01339   else
01340   {
01341
01342    /* Make sure there is enough time to suspend the processing */
01343     tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
01344
01345     if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
01346     {
01347       /* No suspension attempted since almost to the end of the transferred data. */
01348       /* Best option for user code is to wrap up low priority message hashing     */
01349       return HAL_ERROR;
01350     }
01351
01352     /* Wait for DMAS to be reset */
01353     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01354     {
01355        return HAL_TIMEOUT;
01356     }
01357
01358     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
01359     {
01360       return HAL_ERROR;
01361     }
01362
01363     /* Wait for DMAS to be set */
01364     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
01365     {
01366        return HAL_TIMEOUT;
01367     }
01368
01369     /* Disable DMA channel */
01370     /*
01371       Note that the Abort function will
01372       - Clear the transfer error flags
01373       - Unlock
01374       - Set the State
01375     */
01376     if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
01377     {
01378       return HAL_ERROR;
01379     }
01380
01381     /* Clear DMAE bit */
01382     CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
01383
01384     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01385     {
01386       return HAL_TIMEOUT;
01387     }
01388
01389     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
01390     {
01391       return HAL_ERROR;
01392     }
01393
01394     /* At this point, DMA interface is disabled and no transfer is on-going */
01395     /* Retrieve from the DMA handle how many words remain to be written */
01396     tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
01397
01398     if (tmp_remaining_DMATransferSize_inWords == 0U)
01399     {
01400       /* All the DMA transfer is actually done. Suspension occurred at the very end
01401          of the transfer. Either the digest computation is about to start (HASH case)
01402          or processing is about to move from one step to another (HMAC case).
01403          In both cases, the processing can't be suspended at this point. It is
01404          safer to
01405          - retrieve the low priority block digest before starting the high
01406            priority block processing (HASH case)
01407          - re-attempt a new suspension (HMAC case)
01408          */
01409       return HAL_ERROR;
01410     }
01411     else
01412     {
01413
01414       /* Compute how many words were supposed to be transferred by DMA */
01415       tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ?  ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
01416
01417       /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
01418         by HASH IP, correct it */
01419       /* tmp_words_already_pushed reflects the number of words that were already pushed before
01420          the start of DMA transfer (multi-buffer processing case) */
01421       tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
01422       if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U)  != HASH_NBW_PUSHED())
01423       {
01424         tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
01425       }
01426
01427       /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
01428       hhash->pHashInBuffPtr +=  4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
01429
01430       /* And store in HashInCount the remaining size to transfer (in bytes) */
01431       hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
01432
01433     }
01434
01435     /* Set State as suspended */
01436     hhash->State = HAL_HASH_STATE_SUSPENDED;
01437
01438     return HAL_OK;
01439
01440   }
01441 }
01442
01443 /**
01444   * @brief  Return the HASH handle error code.
01445   * @param  hhash: pointer to a HASH_HandleTypeDef structure.
01446   * @retval HASH Error Code
01447 */
01448 uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
01449 {
01450   /* Return HASH Error Code */
01451   return hhash->ErrorCode;
01452 }
01453 /**
01454   * @}
01455   */
01456
01457
01458 /**
01459   * @}
01460   */
01461
01462 /** @defgroup HASH_Private_Functions HASH Private Functions
01463   * @{
01464   */
01465
01466 /**
01467   * @brief DMA HASH Input Data transfer completion callback.
01468   * @param hdma: DMA handle.
01469   * @note  In case of HMAC processing, HASH_DMAXferCplt() initiates
01470   *        the next DMA transfer for the following HMAC step.
01471   * @retval None
01472   */
01473 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
01474 {
01475   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01476   uint32_t inputaddr;
01477   uint32_t buffersize;
01478   HAL_StatusTypeDef status ;
01479
01480   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
01481   {
01482
01483     /* Disable the DMA transfer */
01484     CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
01485
01486     if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
01487     {
01488       /* If no HMAC processing, input data transfer is now over */
01489
01490       /* Change the HASH state to ready */
01491       hhash->State = HAL_HASH_STATE_READY;
01492
01493       /* Call Input data transfer complete call back */
01494 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01495       hhash->InCpltCallback(hhash);
01496 #else
01497       HAL_HASH_InCpltCallback(hhash);
01498 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01499
01500     }
01501     else
01502     {
01503       /* HMAC processing: depending on the current HMAC step and whether or
01504       not multi-buffer processing is on-going, the next step is initiated
01505       and MDMAT bit is set.  */
01506
01507
01508       if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
01509       {
01510         /* This is the end of HMAC processing */
01511
01512         /* Change the HASH state to ready */
01513         hhash->State = HAL_HASH_STATE_READY;
01514
01515         /* Call Input data transfer complete call back
01516         (note that the last DMA transfer was that of the key
01517         for the outer HASH operation). */
01518 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01519         hhash->InCpltCallback(hhash);
01520 #else
01521         HAL_HASH_InCpltCallback(hhash);
01522 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01523
01524         return;
01525       }
01526       else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
01527       {
01528         inputaddr = (uint32_t)hhash->pHashMsgBuffPtr;     /* DMA transfer start address */
01529         buffersize = hhash->HashBuffSize;                 /* DMA transfer size (in bytes) */
01530         hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
01531
01532         /* In case of suspension request, save the new starting parameters */
01533         hhash->HashInCount = hhash->HashBuffSize;         /* Initial DMA transfer size (in bytes) */
01534         hhash->pHashInBuffPtr  = hhash->pHashMsgBuffPtr ; /* DMA transfer start address           */
01535
01536         hhash->NbWordsAlreadyPushed = 0U;                  /* Reset number of words already pushed */
01537         /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
01538         if (hhash->DigestCalculationDisable != RESET)
01539         {
01540           /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
01541           no digest calculation will be triggered at the end of the input buffer feeding to the IP */
01542           __HAL_HASH_SET_MDMAT();
01543         }
01544       }
01545       else  /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
01546       {
01547         if (hhash->DigestCalculationDisable != RESET)
01548         {
01549           /* No automatic move to Step 3 as a new message buffer will be fed to the IP
01550           (case of multi-buffer HMAC processing):
01551           DCAL must not be set.
01552           Phase remains in Step 2, MDMAT remains set at this point.
01553           Change the HASH state to ready and call Input data transfer complete call back. */
01554           hhash->State = HAL_HASH_STATE_READY;
01555 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01556           hhash->InCpltCallback(hhash);
01557 #else
01558           HAL_HASH_InCpltCallback(hhash);
01559 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01560           return ;
01561         }
01562         else
01563         {
01564           /* Digest calculation is not disabled (case of single buffer input or last buffer
01565           of multi-buffer HMAC processing) */
01566           inputaddr = (uint32_t)hhash->Init.pKey;       /* DMA transfer start address */
01567           buffersize = hhash->Init.KeySize;             /* DMA transfer size (in bytes) */
01568           hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;    /* Move phase from Step 2 to Step 3 */
01569           /* In case of suspension request, save the new starting parameters */
01570           hhash->HashInCount = hhash->Init.KeySize;     /* Initial size for second DMA transfer (input data) */
01571           hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* address passed to DMA, now entering data message */
01572
01573           hhash->NbWordsAlreadyPushed = 0U;              /* Reset number of words already pushed */
01574         }
01575       }
01576
01577     /* Configure the Number of valid bits in last word of the message */
01578     __HAL_HASH_SET_NBVALIDBITS(buffersize);
01579
01580       /* Set the HASH DMA transfert completion call back */
01581       hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01582
01583       /* Enable the DMA In DMA Stream */
01584     status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
01585
01586     /* Enable DMA requests */
01587     SET_BIT(HASH->CR, HASH_CR_DMAE);
01588
01589           /* Return function status */
01590       if (status != HAL_OK)
01591       {
01592         /* Update DAC state machine to error */
01593         hhash->State = HAL_HASH_STATE_ERROR;
01594       }
01595       else
01596       {
01597         /* Change DAC state */
01598         hhash->State = HAL_HASH_STATE_READY;
01599       }
01600   }
01601   }
01602
01603   return;
01604 }
01605
01606 /**
01607   * @brief DMA HASH communication error callback.
01608   * @param hdma: DMA handle.
01609   * @note  HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
01610   *        can contain user code to manage the error.
01611   * @retval None
01612   */
01613 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
01614 {
01615   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01616
01617   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
01618   {
01619     hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
01620     /* Set HASH state to ready to prevent any blocking issue in user code
01621        present in HAL_HASH_ErrorCallback() */
01622     hhash->State= HAL_HASH_STATE_READY;
01623     /* Set HASH handle status to error */
01624     hhash->Status = HAL_ERROR;
01625 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01626     hhash->ErrorCallback(hhash);
01627 #else
01628     HAL_HASH_ErrorCallback(hhash);
01629 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01630     /* After error handling by code user, reset HASH handle HAL status */
01631     hhash->Status = HAL_OK;
01632
01633   }
01634 }
01635
01636 /**
01637   * @brief  Feed the input buffer to the HASH IP.
01638   * @param  hhash: HASH handle.
01639   * @param  pInBuffer: pointer to input buffer.
01640   * @param  Size: the size of input buffer in bytes.
01641   * @note   HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
01642   *         or not the HASH processing must be suspended. If this is the case, the
01643   *         processing is suspended when possible and the IP feeding point reached at
01644   *         suspension time is stored in the handle for resumption later on.
01645   * @retval HAL status
01646   */
01647 static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01648 {
01649   uint32_t buffercounter;
01650   __IO uint32_t inputaddr = (uint32_t) pInBuffer;
01651
01652   for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
01653   {
01654     /* Write input data 4 bytes at a time */
01655     HASH->DIN = *(uint32_t*)inputaddr;
01656     inputaddr+=4U;
01657
01658     /* If the suspension flag has been raised and if the processing is not about
01659     to end, suspend processing */
01660     if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
01661     {
01662       /* wait for flag BUSY not set before  Wait for DINIS = 1*/
01663       if (buffercounter >=64U)
01664       {
01665         if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01666         {
01667           return HAL_TIMEOUT;
01668         }
01669       }
01670       /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
01671       in the input buffer */
01672       if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01673       {
01674         /* Reset SuspendRequest */
01675         hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
01676
01677         /* Depending whether the key or the input data were fed to the IP, the feeding point
01678         reached at suspension time is not saved in the same handle fields */
01679         if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
01680         {
01681           /* Save current reading and writing locations of Input and Output buffers */
01682           hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
01683           /* Save the number of bytes that remain to be processed at this point */
01684           hhash->HashInCount    =  Size - (buffercounter + 4U);
01685         }
01686         else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
01687         {
01688           /* Save current reading and writing locations of Input and Output buffers */
01689           hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
01690           /* Save the number of bytes that remain to be processed at this point */
01691           hhash->HashKeyCount  =  Size - (buffercounter + 4U);
01692         }
01693         else
01694         {
01695           /* Unexpected phase: unlock process and report error */
01696           hhash->State = HAL_HASH_STATE_READY;
01697           __HAL_UNLOCK(hhash);
01698           return HAL_ERROR;
01699         }
01700
01701         /* Set the HASH state to Suspended and exit to stop entering data */
01702         hhash->State = HAL_HASH_STATE_SUSPENDED;
01703
01704         return HAL_OK;
01705       } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))  */
01706     } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
01707   }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
01708
01709   /* At this point, all the data have been entered to the IP: exit */
01710   return  HAL_OK;
01711 }
01712
01713 /**
01714   * @brief  Retrieve the message digest.
01715   * @param  pMsgDigest: pointer to the computed digest.
01716   * @param  Size: message digest size in bytes.
01717   * @retval None
01718   */
01719 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
01720 {
01721   uint32_t msgdigest = (uint32_t)pMsgDigest;
01722
01723   switch(Size)
01724   {
01725     /* Read the message digest */
01726     case 16:  /* MD5 */
01727       *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01728       msgdigest+=4U;
01729       *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01730       msgdigest+=4U;
01731       *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01732       msgdigest+=4U;
01733       *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01734     break;
01735     case 20:  /* SHA1 */
01736       *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01737       msgdigest+=4U;
01738       *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01739       msgdigest+=4U;
01740       *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01741       msgdigest+=4U;
01742       *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01743       msgdigest+=4U;
01744       *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01745     break;
01746   case 28:  /* SHA224 */
01747     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01748     msgdigest+=4U;
01749     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01750     msgdigest+=4U;
01751     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01752     msgdigest+=4U;
01753     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01754     msgdigest+=4U;
01755     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01756     msgdigest+=4U;
01757     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
01758     msgdigest+=4U;
01759     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
01760     break;
01761   case 32:   /* SHA256 */
01762     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01763     msgdigest+=4U;
01764     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01765     msgdigest+=4U;
01766     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01767     msgdigest+=4U;
01768     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01769     msgdigest+=4U;
01770     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01771     msgdigest+=4U;
01772     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
01773     msgdigest+=4U;
01774     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
01775     msgdigest+=4U;
01776     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
01777     break;
01778     default:
01779     break;
01780   }
01781 }
01782
01783
01784
01785 /**
01786   * @brief  Handle HASH processing Timeout.
01787   * @param  hhash: HASH handle.
01788   * @param  Flag: specifies the HASH flag to check.
01789   * @param  Status: the Flag status (SET or RESET).
01790   * @param  Timeout: Timeout duration.
01791   * @retval HAL status
01792   */
01793 static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01794 {
01795   uint32_t tickstart = HAL_GetTick();
01796
01797   /* Wait until flag is set */
01798   if(Status == RESET)
01799   {
01800     while(__HAL_HASH_GET_FLAG(Flag) == RESET)
01801     {
01802       /* Check for the Timeout */
01803       if(Timeout != HAL_MAX_DELAY)
01804       {
01805         if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
01806         {
01807           /* Set State to Ready to be able to restart later on */
01808           hhash->State  = HAL_HASH_STATE_READY;
01809           /* Store time out issue in handle status */
01810           hhash->Status = HAL_TIMEOUT;
01811
01812           /* Process Unlocked */
01813           __HAL_UNLOCK(hhash);
01814
01815           return HAL_TIMEOUT;
01816         }
01817       }
01818     }
01819   }
01820   else
01821   {
01822     while(__HAL_HASH_GET_FLAG(Flag) != RESET)
01823     {
01824       /* Check for the Timeout */
01825       if(Timeout != HAL_MAX_DELAY)
01826       {
01827         if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
01828         {
01829           /* Set State to Ready to be able to restart later on */
01830           hhash->State  = HAL_HASH_STATE_READY;
01831           /* Store time out issue in handle status */
01832           hhash->Status = HAL_TIMEOUT;
01833
01834           /* Process Unlocked */
01835           __HAL_UNLOCK(hhash);
01836
01837           return HAL_TIMEOUT;
01838         }
01839       }
01840     }
01841   }
01842   return HAL_OK;
01843 }
01844
01845
01846 /**
01847   * @brief  HASH processing in interruption mode.
01848   * @param  hhash: HASH handle.
01849   * @note   HASH_IT() regularly reads hhash->SuspendRequest to check whether
01850   *         or not the HASH processing must be suspended. If this is the case, the
01851   *         processing is suspended when possible and the IP feeding point reached at
01852   *         suspension time is stored in the handle for resumption later on.
01853   * @retval HAL status
01854   */
01855 static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
01856 {
01857   if (hhash->State == HAL_HASH_STATE_BUSY)
01858   {
01859     /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
01860     if(hhash->HashITCounter == 0U)
01861     {
01862       /* Disable Interrupts */
01863       __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01864       /* HASH state set back to Ready to prevent any issue in user code
01865          present in HAL_HASH_ErrorCallback() */
01866       hhash->State = HAL_HASH_STATE_READY;
01867       return HAL_ERROR;
01868     }
01869     else if (hhash->HashITCounter == 1U)
01870     {
01871      /* This is the first call to HASH_IT, the first input data are about to be
01872         entered in the IP. A specific processing is carried out at this point to
01873         start-up the processing. */
01874       hhash->HashITCounter = 2U;
01875     }
01876     else
01877     {
01878       /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
01879         the HASH processing or the end of the current step for HMAC processing. */
01880       hhash->HashITCounter = 3U;
01881     }
01882
01883     /* If digest is ready */
01884     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01885     {
01886       /* Read the digest */
01887       HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
01888
01889       /* Disable Interrupts */
01890       __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01891       /* Change the HASH state */
01892       hhash->State = HAL_HASH_STATE_READY;
01893       /* Call digest computation complete call back */
01894 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01895       hhash->DgstCpltCallback(hhash);
01896 #else
01897       HAL_HASH_DgstCpltCallback(hhash);
01898 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01899
01900       return HAL_OK;
01901     }
01902
01903     /* If IP ready to accept new data */
01904     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01905     {
01906
01907       /* If the suspension flag has been raised and if the processing is not about
01908          to end, suspend processing */
01909       if ( (hhash->HashInCount != 0U) &&  (hhash->SuspendRequest == HAL_HASH_SUSPEND))
01910       {
01911         /* Disable Interrupts */
01912         __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01913
01914         /* Reset SuspendRequest */
01915         hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
01916
01917         /* Change the HASH state */
01918         hhash->State = HAL_HASH_STATE_SUSPENDED;
01919
01920         return HAL_OK;
01921       }
01922
01923       /* Enter input data in the IP thru HASH_Write_Block_Data() call and
01924         check whether the digest calculation has been triggered */
01925       if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
01926       {
01927         /* Call Input data transfer complete call back
01928            (called at the end of each step for HMAC) */
01929 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
01930         hhash->InCpltCallback(hhash);
01931 #else
01932         HAL_HASH_InCpltCallback(hhash);
01933 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
01934
01935         if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
01936         {
01937           /* Wait until IP is not busy anymore */
01938           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01939           {
01940             /* Disable Interrupts */
01941             __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01942             return HAL_TIMEOUT;
01943           }
01944           /* Initialization start for HMAC STEP 2 */
01945           hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
01946           __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
01947           hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
01948           hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
01949           hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
01950           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
01951         }
01952         else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
01953         {
01954           /* Wait until IP is not busy anymore */
01955           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01956           {
01957             /* Disable Interrupts */
01958             __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01959             return HAL_TIMEOUT;
01960           }
01961           /* Initialization start for HMAC STEP 3 */
01962           hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;         /* Move phase from Step 2 to Step 3 */
01963           __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */
01964           hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */
01965           hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */
01966           hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
01967           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */
01968         }
01969         else
01970         {
01971           /* Nothing to do */
01972         }
01973       } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
01974     }  /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
01975
01976     /* Return function status */
01977     return HAL_OK;
01978   }
01979   else
01980   {
01981     return HAL_BUSY;
01982   }
01983 }
01984
01985
01986 /**
01987   * @brief  Write a block of data in HASH IP in interruption mode.
01988   * @param  hhash: HASH handle.
01989   * @note   HASH_Write_Block_Data() is called under interruption by HASH_IT().
01990   * @retval HAL status
01991   */
01992 static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
01993 {
01994   uint32_t inputaddr;
01995   uint32_t buffercounter;
01996   uint32_t inputcounter;
01997   uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
01998
01999   /* If there are more than 64 bytes remaining to be entered */
02000   if(hhash->HashInCount > 64U)
02001   {
02002     inputaddr = (uint32_t)hhash->pHashInBuffPtr;
02003     /* Write the Input block in the Data IN register
02004       (16 32-bit words, or 64 bytes are entered) */
02005     for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
02006     {
02007       HASH->DIN = *(uint32_t*)inputaddr;
02008       inputaddr+=4U;
02009     }
02010     /* If this is the start of input data entering, an additional word
02011       must be entered to start up the HASH processing */
02012     if(hhash->HashITCounter == 2U)
02013     {
02014       HASH->DIN = *(uint32_t*)inputaddr;
02015       if(hhash->HashInCount >= 68U)
02016       {
02017         /* There are still data waiting to be entered in the IP.
02018            Decrement buffer counter and set pointer to the proper
02019            memory location for the next data entering round. */
02020         hhash->HashInCount -= 68U;
02021         hhash->pHashInBuffPtr+= 68U;
02022       }
02023       else
02024       {
02025         /* All the input buffer has been fed to the HW. */
02026         hhash->HashInCount = 0U;
02027       }
02028     }
02029     else
02030     {
02031       /* 64 bytes have been entered and there are still some remaining:
02032          Decrement buffer counter and set pointer to the proper
02033         memory location for the next data entering round.*/
02034       hhash->HashInCount -= 64U;
02035       hhash->pHashInBuffPtr+= 64U;
02036     }
02037   }
02038   else
02039   {
02040     /* 64 or less bytes remain to be entered. This is the last
02041       data entering round. */
02042
02043     /* Get the buffer address */
02044     inputaddr = (uint32_t)hhash->pHashInBuffPtr;
02045     /* Get the buffer counter */
02046     inputcounter = hhash->HashInCount;
02047     /* Disable Interrupts */
02048     __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
02049
02050     /* Write the Input block in the Data IN register */
02051     for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
02052     {
02053       HASH->DIN = *(uint32_t*)inputaddr;
02054       inputaddr+=4U;
02055     }
02056     /* Start the Digest calculation */
02057     __HAL_HASH_START_DIGEST();
02058     /* Return indication that digest calculation has started:
02059        this return value triggers the call to Input data transfer
02060        complete call back as well as the proper transition from
02061        one step to another in HMAC mode. */
02062     ret = HASH_DIGEST_CALCULATION_STARTED;
02063     /* Reset buffer counter */
02064     hhash->HashInCount = 0;
02065   }
02066
02067   /* Return whether or digest calculation has started */
02068   return ret;
02069 }
02070
02071 /**
02072   * @brief  HMAC processing in polling mode.
02073   * @param  hhash: HASH handle.
02074   * @param  Timeout: Timeout value.
02075   * @retval HAL status
02076   */
02077 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
02078 {
02079   /* Ensure first that Phase is correct */
02080   if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
02081   {
02082     /* Change the HASH state */
02083     hhash->State = HAL_HASH_STATE_READY;
02084
02085     /* Process Unlock */
02086     __HAL_UNLOCK(hhash);
02087
02088     /* Return function status */
02089     return HAL_ERROR;
02090   }
02091
02092   /* HMAC Step 1 processing */
02093   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
02094   {
02095     /************************** STEP 1 ******************************************/
02096     /* Configure the Number of valid bits in last word of the message */
02097     __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02098
02099     /* Write input buffer in Data register */
02100     hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
02101     if (hhash->Status != HAL_OK)
02102     {
02103       return hhash->Status;
02104     }
02105
02106     /* Check whether or not key entering process has been suspended */
02107     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02108     {
02109       /* Process Unlocked */
02110       __HAL_UNLOCK(hhash);
02111
02112       /* Stop right there and return function status */
02113       return HAL_OK;
02114     }
02115
02116     /* No processing suspension at this point: set DCAL bit. */
02117     __HAL_HASH_START_DIGEST();
02118
02119     /* Wait for BUSY flag to be cleared */
02120     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
02121     {
02122       return HAL_TIMEOUT;
02123     }
02124
02125     /* Move from Step 1 to Step 2 */
02126     hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
02127
02128   }
02129
02130   /* HMAC Step 2 processing.
02131      After phase check, HMAC_Processing() may
02132      - directly start up from this point in resumption case
02133        if the same Step 2 processing was suspended previously
02134     - or fall through from the Step 1 processing carried out hereabove */
02135   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
02136   {
02137     /************************** STEP 2 ******************************************/
02138     /* Configure the Number of valid bits in last word of the message */
02139     __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
02140
02141     /* Write input buffer in Data register */
02142     hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
02143     if (hhash->Status != HAL_OK)
02144     {
02145       return hhash->Status;
02146     }
02147
02148     /* Check whether or not data entering process has been suspended */
02149     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02150     {
02151       /* Process Unlocked */
02152       __HAL_UNLOCK(hhash);
02153
02154       /* Stop right there and return function status */
02155       return HAL_OK;
02156     }
02157
02158     /* No processing suspension at this point: set DCAL bit. */
02159     __HAL_HASH_START_DIGEST();
02160
02161     /* Wait for BUSY flag to be cleared */
02162     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
02163     {
02164       return HAL_TIMEOUT;
02165     }
02166
02167     /* Move from Step 2 to Step 3 */
02168     hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
02169     /* In case Step 1 phase was suspended then resumed,
02170        set again Key input buffers and size before moving to
02171        next step */
02172     hhash->pHashKeyBuffPtr = hhash->Init.pKey;
02173     hhash->HashKeyCount    = hhash->Init.KeySize;
02174   }
02175
02176
02177  /* HMAC Step 3 processing.
02178      After phase check, HMAC_Processing() may
02179      - directly start up from this point in resumption case
02180        if the same Step 3 processing was suspended previously
02181     - or fall through from the Step 2 processing carried out hereabove */
02182   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
02183   {
02184     /************************** STEP 3 ******************************************/
02185     /* Configure the Number of valid bits in last word of the message */
02186     __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02187
02188     /* Write input buffer in Data register */
02189     hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
02190     if (hhash->Status != HAL_OK)
02191     {
02192       return hhash->Status;
02193     }
02194
02195     /* Check whether or not key entering process has been suspended */
02196     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02197     {
02198       /* Process Unlocked */
02199       __HAL_UNLOCK(hhash);
02200
02201       /* Stop right there and return function status */
02202       return HAL_OK;
02203     }
02204
02205     /* No processing suspension at this point: start the Digest calculation. */
02206     __HAL_HASH_START_DIGEST();
02207
02208     /* Wait for DCIS flag to be set */
02209      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
02210     {
02211       return HAL_TIMEOUT;
02212     }
02213
02214     /* Read the message digest */
02215     HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
02216   }
02217
02218    /* Change the HASH state */
02219    hhash->State = HAL_HASH_STATE_READY;
02220
02221    /* Process Unlock */
02222    __HAL_UNLOCK(hhash);
02223
02224    /* Return function status */
02225    return HAL_OK;
02226 }
02227
02228
02229 /**
02230   * @brief  Initialize the HASH peripheral, next process pInBuffer then
02231   *         read the computed digest.
02232   * @note   Digest is available in pOutBuffer.
02233   * @param  hhash: HASH handle.
02234   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02235   * @param  Size: length of the input buffer in bytes.
02236   * @param  pOutBuffer: pointer to the computed digest.
02237   * @param  Timeout: Timeout value.
02238   * @param  Algorithm: HASH algorithm.
02239   * @retval HAL status
02240   */
02241 HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
02242 {
02243   uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
02244   uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
02245   HAL_HASH_StateTypeDef State_tmp = hhash->State;
02246
02247
02248   /* Initiate HASH processing in case of start or resumption */
02249 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02250   {
02251     /* Check input parameters */
02252     if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
02253     {
02254       hhash->State = HAL_HASH_STATE_READY;
02255       return  HAL_ERROR;
02256     }
02257
02258     /* Process Locked */
02259     __HAL_LOCK(hhash);
02260
02261     /* Check if initialization phase has not been already performed */
02262     if(hhash->Phase == HAL_HASH_PHASE_READY)
02263     {
02264       /* Change the HASH state */
02265       hhash->State = HAL_HASH_STATE_BUSY;
02266
02267       /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02268       MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02269
02270       /* Configure the number of valid bits in last word of the message */
02271       __HAL_HASH_SET_NBVALIDBITS(Size);
02272
02273       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
02274       input parameters of HASH_WriteData() */
02275       pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
02276       Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
02277
02278       /* Set the phase */
02279       hhash->Phase = HAL_HASH_PHASE_PROCESS;
02280     }
02281     else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
02282     {
02283       /* if the IP has already been initialized, two cases are possible */
02284
02285       /* Process resumption time ... */
02286       if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02287       {
02288         /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
02289         to the API input parameters but to those saved beforehand by HASH_WriteData()
02290         when the processing was suspended */
02291         pInBuffer_tmp = hhash->pHashInBuffPtr;
02292         Size_tmp = hhash->HashInCount;
02293       }
02294       /* ... or multi-buffer HASH processing end */
02295       else
02296       {
02297         /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
02298         input parameters of HASH_WriteData() */
02299         pInBuffer_tmp = pInBuffer;
02300         Size_tmp = Size;
02301         /* Configure the number of valid bits in last word of the message */
02302         __HAL_HASH_SET_NBVALIDBITS(Size);
02303       }
02304       /* Change the HASH state */
02305       hhash->State = HAL_HASH_STATE_BUSY;
02306     }
02307     else
02308     {
02309       /* Phase error */
02310       hhash->State = HAL_HASH_STATE_READY;
02311
02312       /* Process Unlocked */
02313       __HAL_UNLOCK(hhash);
02314
02315       /* Return function status */
02316       return HAL_ERROR;
02317     }
02318
02319
02320     /* Write input buffer in Data register */
02321     hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
02322     if (hhash->Status != HAL_OK)
02323     {
02324       return hhash->Status;
02325     }
02326
02327     /* If the process has not been suspended, carry on to digest calculation */
02328     if (hhash->State != HAL_HASH_STATE_SUSPENDED)
02329     {
02330       /* Start the Digest calculation */
02331       __HAL_HASH_START_DIGEST();
02332
02333       /* Wait for DCIS flag to be set */
02334       if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
02335       {
02336         return HAL_TIMEOUT;
02337       }
02338
02339       /* Read the message digest */
02340       HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
02341
02342       /* Change the HASH state */
02343       hhash->State = HAL_HASH_STATE_READY;
02344
02345     }
02346
02347     /* Process Unlocked */
02348     __HAL_UNLOCK(hhash);
02349
02350     /* Return function status */
02351     return HAL_OK;
02352
02353   }
02354   else
02355   {
02356     return HAL_BUSY;
02357   }
02358 }
02359
02360
02361 /**
02362   * @brief  If not already done, initialize the HASH peripheral then
02363   *         processes pInBuffer.
02364   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
02365   *         the IP has already been initialized.
02366   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
02367   *         HASH digest computation is corrupted.
02368   * @param  hhash: HASH handle.
02369   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02370   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
02371   * @param  Algorithm: HASH algorithm.
02372   * @retval HAL status
02373   */
02374 HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02375 {
02376   uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
02377   uint32_t Size_tmp;  /* input data size (in bytes), input parameter of HASH_WriteData() */
02378   HAL_HASH_StateTypeDef State_tmp = hhash->State;
02379
02380   /* Make sure the input buffer size (in bytes) is a multiple of 4 */
02381    assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
02382
02383   /* Initiate HASH processing in case of start or resumption */
02384 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02385   {
02386     /* Check input parameters */
02387     if ((pInBuffer == NULL) || (Size == 0U))
02388     {
02389       hhash->State = HAL_HASH_STATE_READY;
02390       return  HAL_ERROR;
02391     }
02392
02393      /* Process Locked */
02394     __HAL_LOCK(hhash);
02395
02396     /* If resuming the HASH processing */
02397     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02398     {
02399       /* Change the HASH state */
02400       hhash->State = HAL_HASH_STATE_BUSY;
02401
02402       /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
02403          to the API input parameters but to those saved beforehand by HASH_WriteData()
02404          when the processing was suspended */
02405       pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
02406       Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
02407
02408     }
02409     else
02410     {
02411       /* Change the HASH state */
02412       hhash->State = HAL_HASH_STATE_BUSY;
02413
02414       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
02415          input parameters of HASH_WriteData() */
02416       pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */
02417       Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */
02418
02419       /* Check if initialization phase has already be performed */
02420       if(hhash->Phase == HAL_HASH_PHASE_READY)
02421       {
02422         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02423         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02424       }
02425
02426       /* Set the phase */
02427       hhash->Phase = HAL_HASH_PHASE_PROCESS;
02428
02429     }
02430
02431     /* Write input buffer in Data register */
02432     hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
02433     if (hhash->Status != HAL_OK)
02434     {
02435       return hhash->Status;
02436     }
02437
02438     /* If the process has not been suspended, move the state to Ready */
02439     if (hhash->State != HAL_HASH_STATE_SUSPENDED)
02440     {
02441       /* Change the HASH state */
02442       hhash->State = HAL_HASH_STATE_READY;
02443     }
02444
02445     /* Process Unlocked */
02446     __HAL_UNLOCK(hhash);
02447
02448     /* Return function status */
02449     return HAL_OK;
02450
02451   }
02452   else
02453   {
02454     return HAL_BUSY;
02455   }
02456
02457
02458 }
02459
02460
02461 /**
02462   * @brief  Initialize the HASH peripheral, next process pInBuffer then
02463   *         read the computed digest in interruption mode.
02464   * @note   Digest is available in pOutBuffer.
02465   * @param  hhash: HASH handle.
02466   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02467   * @param  Size: length of the input buffer in bytes.
02468   * @param  pOutBuffer: pointer to the computed digest.
02469   * @param  Algorithm: HASH algorithm.
02470   * @retval HAL status
02471   */
02472 HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
02473 {
02474    HAL_HASH_StateTypeDef State_tmp = hhash->State;
02475
02476   /* If State is ready or suspended, start or resume IT-based HASH processing */
02477 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02478   {
02479     /* Check input parameters */
02480     if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
02481     {
02482       hhash->State = HAL_HASH_STATE_READY;
02483       return  HAL_ERROR;
02484     }
02485
02486     /* Process Locked */
02487     __HAL_LOCK(hhash);
02488
02489     /* Change the HASH state */
02490     hhash->State = HAL_HASH_STATE_BUSY;
02491
02492     /* Initialize IT counter */
02493     hhash->HashITCounter = 1;
02494
02495     /* Check if initialization phase has already be performed */
02496     if(hhash->Phase == HAL_HASH_PHASE_READY)
02497     {
02498       /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02499       MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02500
02501       /* Configure the number of valid bits in last word of the message */
02502      __HAL_HASH_SET_NBVALIDBITS(Size);
02503
02504
02505       hhash->HashInCount = Size;               /* Counter used to keep track of number of data
02506                                                   to be fed to the IP */
02507       hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the IP at
02508                                                   the next interruption */
02509      /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
02510         the information describing where the HASH process is stopped.
02511         These variables are used later on to resume the HASH processing at the
02512         correct location. */
02513
02514       hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
02515     }
02516
02517     /* Set the phase */
02518     hhash->Phase = HAL_HASH_PHASE_PROCESS;
02519
02520     /* Process Unlock */
02521     __HAL_UNLOCK(hhash);
02522
02523     /* Enable Interrupts */
02524     __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
02525
02526     /* Return function status */
02527     return HAL_OK;
02528   }
02529   else
02530   {
02531     return HAL_BUSY;
02532   }
02533
02534 }
02535
02536
02537 /**
02538   * @brief  Initialize the HASH peripheral then initiate a DMA transfer
02539   *         to feed the input buffer to the IP.
02540   * @note   If MDMAT bit is set before calling this function (multi-buffer
02541   *          HASH processing case), the input buffer size (in bytes) must be
02542   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
02543   *          For the processing of the last buffer of the thread, MDMAT bit must
02544   *          be reset and the buffer length (in bytes) doesn't have to be a
02545   *          multiple of 4.
02546   * @param  hhash: HASH handle.
02547   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02548   * @param  Size: length of the input buffer in bytes.
02549   * @param  Algorithm: HASH algorithm.
02550   * @retval HAL status
02551   */
02552 HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02553 {
02554   uint32_t inputaddr;
02555   uint32_t inputSize;
02556   HAL_StatusTypeDef status ;
02557   HAL_HASH_StateTypeDef State_tmp = hhash->State;
02558
02559
02560   /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
02561      (case of multi-buffer HASH processing) */
02562   assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
02563
02564    /* If State is ready or suspended, start or resume polling-based HASH processing */
02565 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02566   {
02567     /* Check input parameters */
02568     if ( (pInBuffer == NULL ) || (Size == 0U) ||
02569     /* Check phase coherency. Phase must be
02570        either READY (fresh start)
02571        or PROCESS (multi-buffer HASH management) */
02572        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
02573     {
02574       hhash->State = HAL_HASH_STATE_READY;
02575       return  HAL_ERROR;
02576     }
02577
02578
02579     /* Process Locked */
02580     __HAL_LOCK(hhash);
02581
02582     /* If not a resumption case */
02583     if (hhash->State == HAL_HASH_STATE_READY)
02584     {
02585       /* Change the HASH state */
02586       hhash->State = HAL_HASH_STATE_BUSY;
02587
02588       /* Check if initialization phase has already been performed.
02589          If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
02590          API is processing a new input data message in case of multi-buffer HASH
02591          computation. */
02592       if(hhash->Phase == HAL_HASH_PHASE_READY)
02593       {
02594         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02595         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02596
02597         /* Set the phase */
02598         hhash->Phase = HAL_HASH_PHASE_PROCESS;
02599       }
02600
02601       /* Configure the Number of valid bits in last word of the message */
02602       __HAL_HASH_SET_NBVALIDBITS(Size);
02603
02604       inputaddr = (uint32_t)pInBuffer;     /* DMA transfer start address   */
02605       inputSize = Size;                    /* DMA transfer size (in bytes) */
02606
02607       /* In case of suspension request, save the starting parameters */
02608       hhash->pHashInBuffPtr =  pInBuffer;  /* DMA transfer start address   */
02609       hhash->HashInCount = Size;           /* DMA transfer size (in bytes) */
02610
02611     }
02612     /* If resumption case */
02613     else
02614     {
02615       /* Change the HASH state */
02616       hhash->State = HAL_HASH_STATE_BUSY;
02617
02618       /* Resumption case, inputaddr and inputSize are not set to the API input parameters
02619          but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
02620          processing was suspended */
02621       inputaddr = (uint32_t)hhash->pHashInBuffPtr;  /* DMA transfer start address   */
02622       inputSize = hhash->HashInCount;               /* DMA transfer size (in bytes) */
02623
02624     }
02625
02626     /* Set the HASH DMA transfert complete callback */
02627     hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
02628     /* Set the DMA error callback */
02629     hhash->hdmain->XferErrorCallback = HASH_DMAError;
02630
02631     /* Store number of words already pushed to manage proper DMA processing suspension */
02632     hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
02633
02634     /* Enable the DMA In DMA Stream */
02635     status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
02636
02637     /* Enable DMA requests */
02638     SET_BIT(HASH->CR, HASH_CR_DMAE);
02639
02640     /* Process Unlock */
02641     __HAL_UNLOCK(hhash);
02642
02643     /* Return function status */
02644     if (status != HAL_OK)
02645     {
02646       /* Update HASH state machine to error */
02647       hhash->State = HAL_HASH_STATE_ERROR;
02648     }
02649     else
02650     {
02651       /* Change HASH state */
02652       hhash->State = HAL_HASH_STATE_READY;
02653     }
02654
02655     return status;
02656   }
02657   else
02658   {
02659     return HAL_BUSY;
02660   }
02661 }
02662
02663 /**
02664   * @brief  Return the computed digest.
02665   * @note   The API waits for DCIS to be set then reads the computed digest.
02666   * @param  hhash: HASH handle.
02667   * @param  pOutBuffer: pointer to the computed digest.
02668   * @param  Timeout: Timeout value.
02669   * @retval HAL status
02670   */
02671 HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
02672 {
02673
02674   if(hhash->State == HAL_HASH_STATE_READY)
02675   {
02676     /* Check parameter */
02677     if (pOutBuffer == NULL)
02678     {
02679       return  HAL_ERROR;
02680     }
02681
02682     /* Process Locked */
02683     __HAL_LOCK(hhash);
02684
02685     /* Change the HASH state to busy */
02686     hhash->State = HAL_HASH_STATE_BUSY;
02687
02688     /* Wait for DCIS flag to be set */
02689     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
02690     {
02691       return HAL_TIMEOUT;
02692     }
02693
02694     /* Read the message digest */
02695     HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
02696
02697     /* Change the HASH state to ready */
02698     hhash->State = HAL_HASH_STATE_READY;
02699
02700     /* Process UnLock */
02701     __HAL_UNLOCK(hhash);
02702
02703     /* Return function status */
02704     return HAL_OK;
02705
02706   }
02707   else
02708   {
02709     return HAL_BUSY;
02710   }
02711
02712 }
02713
02714
02715 /**
02716   * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
02717   *         read the computed digest.
02718   * @note   Digest is available in pOutBuffer.
02719   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02720   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02721   * @param  hhash: HASH handle.
02722   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02723   * @param  Size: length of the input buffer in bytes.
02724   * @param  pOutBuffer: pointer to the computed digest.
02725   * @param  Timeout: Timeout value.
02726   * @param  Algorithm: HASH algorithm.
02727   * @retval HAL status
02728   */
02729 HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
02730 {
02731     HAL_HASH_StateTypeDef State_tmp = hhash->State;
02732
02733    /* If State is ready or suspended, start or resume polling-based HASH processing */
02734 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02735   {
02736     /* Check input parameters */
02737     if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
02738     {
02739       hhash->State = HAL_HASH_STATE_READY;
02740       return  HAL_ERROR;
02741     }
02742
02743     /* Process Locked */
02744     __HAL_LOCK(hhash);
02745
02746     /* Change the HASH state */
02747     hhash->State = HAL_HASH_STATE_BUSY;
02748
02749     /* Check if initialization phase has already be performed */
02750     if(hhash->Phase == HAL_HASH_PHASE_READY)
02751     {
02752       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
02753       if(hhash->Init.KeySize > 64U)
02754       {
02755         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02756       }
02757       else
02758       {
02759         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02760       }
02761       /* Set the phase to Step 1 */
02762       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02763       /* Resort to hhash internal fields to feed the IP.
02764          Parameters will be updated in case of suspension to contain the proper
02765          information at resumption time. */
02766       hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
02767       hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
02768       hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
02769       hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */
02770       hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
02771       hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */
02772     }
02773
02774     /* Carry out HMAC processing */
02775     return HMAC_Processing(hhash, Timeout);
02776
02777   }
02778   else
02779   {
02780     return HAL_BUSY;
02781   }
02782 }
02783
02784
02785
02786 /**
02787   * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
02788   *         read the computed digest in interruption mode.
02789   * @note   Digest is available in pOutBuffer.
02790   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02791   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02792   * @param  hhash: HASH handle.
02793   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02794   * @param  Size: length of the input buffer in bytes.
02795   * @param  pOutBuffer: pointer to the computed digest.
02796   * @param  Algorithm: HASH algorithm.
02797   * @retval HAL status
02798   */
02799 HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
02800 {
02801     HAL_HASH_StateTypeDef State_tmp = hhash->State;
02802
02803   /* If State is ready or suspended, start or resume IT-based HASH processing */
02804 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02805   {
02806     /* Check input parameters */
02807     if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
02808     {
02809       hhash->State = HAL_HASH_STATE_READY;
02810       return  HAL_ERROR;
02811     }
02812
02813     /* Process Locked */
02814     __HAL_LOCK(hhash);
02815
02816     /* Change the HASH state */
02817     hhash->State = HAL_HASH_STATE_BUSY;
02818
02819     /* Initialize IT counter */
02820     hhash->HashITCounter = 1;
02821
02822     /* Check if initialization phase has already be performed */
02823     if (hhash->Phase == HAL_HASH_PHASE_READY)
02824     {
02825       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
02826       if(hhash->Init.KeySize > 64U)
02827       {
02828         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02829       }
02830       else
02831       {
02832         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02833       }
02834
02835       /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
02836          to feed the IP whatever the HMAC step.
02837          Lines below are set to start HMAC Step 1 processing where key is entered first. */
02838       hhash->HashInCount     = hhash->Init.KeySize; /* Key size                      */
02839       hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* Key address                   */
02840
02841       /* Store input and output parameters in handle fields to manage steps transition
02842          or possible HMAC suspension/resumption */
02843       hhash->pHashKeyBuffPtr = hhash->Init.pKey;    /* Key address                   */
02844       hhash->pHashMsgBuffPtr = pInBuffer;           /* Input message address         */
02845       hhash->HashBuffSize    = Size;                /* Input message size (in bytes) */
02846       hhash->pHashOutBuffPtr = pOutBuffer;          /* Output digest address         */
02847
02848       /* Configure the number of valid bits in last word of the key */
02849       __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02850
02851       /* Set the phase to Step 1 */
02852       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02853     }
02854     else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
02855     {
02856       /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
02857
02858     }
02859     else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
02860     {
02861       /* Restart IT-based HASH processing after Step 2 suspension */
02862
02863     }
02864     else
02865     {
02866       /* Error report as phase incorrect */
02867       /* Process Unlock */
02868       __HAL_UNLOCK(hhash);
02869       hhash->State = HAL_HASH_STATE_READY;
02870       return HAL_ERROR;
02871     }
02872
02873     /* Process Unlock */
02874     __HAL_UNLOCK(hhash);
02875
02876     /* Enable Interrupts */
02877     __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
02878
02879     /* Return function status */
02880     return HAL_OK;
02881   }
02882   else
02883   {
02884     return HAL_BUSY;
02885   }
02886
02887 }
02888
02889
02890
02891 /**
02892   * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required
02893   *         DMA transfers to feed the key and the input buffer to the IP.
02894   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02895   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02896   * @note   In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
02897   *         be a multiple of 4 otherwise, the HASH digest computation is corrupted.
02898   *         Only the length of the last buffer of the thread doesn't have to be a
02899   *         multiple of 4.
02900   * @param  hhash: HASH handle.
02901   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02902   * @param  Size: length of the input buffer in bytes.
02903   * @param  Algorithm: HASH algorithm.
02904   * @retval HAL status
02905   */
02906 HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02907 {
02908   uint32_t inputaddr;
02909   uint32_t inputSize;
02910   HAL_StatusTypeDef status ;
02911   HAL_HASH_StateTypeDef State_tmp = hhash->State;
02912    /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
02913       is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
02914    assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
02915   /* If State is ready or suspended, start or resume DMA-based HASH processing */
02916 if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
02917   {
02918     /* Check input parameters */
02919     if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
02920    /* Check phase coherency. Phase must be
02921        either READY (fresh start)
02922        or one of HMAC PROCESS steps (multi-buffer HASH management) */
02923        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
02924     {
02925       hhash->State = HAL_HASH_STATE_READY;
02926       return  HAL_ERROR;
02927     }
02928
02929
02930     /* Process Locked */
02931     __HAL_LOCK(hhash);
02932
02933     /* If not a case of resumption after suspension */
02934     if (hhash->State == HAL_HASH_STATE_READY)
02935     {
02936     /* Check whether or not initialization phase has already be performed */
02937     if(hhash->Phase == HAL_HASH_PHASE_READY)
02938     {
02939       /* Change the HASH state */
02940       hhash->State = HAL_HASH_STATE_BUSY;
02941       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
02942          At the same time, ensure MDMAT bit is cleared. */
02943       if(hhash->Init.KeySize > 64U)
02944       {
02945         MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02946       }
02947       else
02948       {
02949         MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02950       }
02951       /* Store input aparameters in handle fields to manage steps transition
02952          or possible HMAC suspension/resumption */
02953       hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
02954       hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
02955       hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
02956       hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
02957       hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
02958
02959       /* Set DMA input parameters */
02960       inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
02961       inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
02962
02963       /* Configure the number of valid bits in last word of the key */
02964       __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02965
02966       /* Set the phase to Step 1 */
02967       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02968
02969     }
02970       else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
02971     {
02972       /* Process a new input data message in case of multi-buffer HMAC processing
02973         (this is not a resumption case) */
02974
02975       /* Change the HASH state */
02976       hhash->State = HAL_HASH_STATE_BUSY;
02977
02978       /* Save input parameters to be able to manage possible suspension/resumption */
02979         hhash->HashInCount = Size;                /* Input message address       */
02980         hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
02981
02982       /* Set DMA input parameters */
02983         inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
02984         inputSize = Size;                          /* Input message size in bytes */
02985
02986       if (hhash->DigestCalculationDisable == RESET)
02987       {
02988         /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
02989        __HAL_HASH_RESET_MDMAT();
02990         __HAL_HASH_SET_NBVALIDBITS(inputSize);
02991       }
02992     }
02993       else
02994       {
02995         /* Phase not aligned with handle READY state */
02996         __HAL_UNLOCK(hhash);
02997         /* Return function status */
02998         return HAL_ERROR;
02999       }
03000     }
03001     else
03002     {
03003        /* Resumption case (phase may be Step 1, 2 or 3) */
03004
03005       /* Change the HASH state */
03006       hhash->State = HAL_HASH_STATE_BUSY;
03007
03008       /* Set DMA input parameters at resumption location;
03009          inputaddr and inputSize are not set to the API input parameters
03010          but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
03011          processing was suspended. */
03012       inputaddr = (uint32_t)(hhash->pHashInBuffPtr);  /* Input message address       */
03013       inputSize = hhash->HashInCount;                 /* Input message size in bytes */
03014     }
03015
03016
03017     /* Set the HASH DMA transfert complete callback */
03018     hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
03019     /* Set the DMA error callback */
03020     hhash->hdmain->XferErrorCallback = HASH_DMAError;
03021
03022     /* Store number of words already pushed to manage proper DMA processing suspension */
03023     hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
03024
03025     /* Enable the DMA In DMA Stream */
03026     status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
03027     /* Enable DMA requests */
03028     SET_BIT(HASH->CR, HASH_CR_DMAE);
03029
03030     /* Process Unlocked */
03031     __HAL_UNLOCK(hhash);
03032
03033     /* Return function status */
03034     if (status != HAL_OK)
03035     {
03036       /* Update HASH state machine to error */
03037       hhash->State = HAL_HASH_STATE_ERROR;
03038     }
03039     else
03040     {
03041       /* Change HASH state */
03042       hhash->State = HAL_HASH_STATE_READY;
03043     }
03044     /* Return function status */
03045     return status;
03046   }
03047   else
03048   {
03049     return HAL_BUSY;
03050   }
03051 }
03052 /**
03053   * @}
03054   */
03055
03056 #endif /* HAL_HASH_MODULE_ENABLED */
03057
03058 /**
03059   * @}
03060   */
03061 #endif /*  HASH*/
03062 /**
03063   * @}
03064   */
03065
03066
03067
03068 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash.h Source File

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stm32h7xx_hal_hash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_HASH_H
00022 #define STM32H7xx_HAL_HASH_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined (HASH)
00035 /** @addtogroup HASH
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup HASH_Exported_Types HASH Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  HASH Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
00050                               This parameter can be a value of @ref HASH_Data_Type. */
00051
00052   uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
00053
00054   uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
00055
00056 } HASH_InitTypeDef;
00057
00058 /**
00059   * @brief HAL State structures definition
00060   */
00061 typedef enum
00062 {
00063   HAL_HASH_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized            */
00064   HAL_HASH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
00065   HAL_HASH_STATE_BUSY              = 0x02U,    /*!< Processing (hashing) is ongoing          */
00066   HAL_HASH_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                            */
00067   HAL_HASH_STATE_ERROR             = 0x07U,    /*!< Error state                              */
00068   HAL_HASH_STATE_SUSPENDED         = 0x08U     /*!< Suspended state                          */
00069 }HAL_HASH_StateTypeDef;
00070
00071 /**
00072   * @brief HAL phase structures definition
00073   */
00074 typedef enum
00075 {
00076   HAL_HASH_PHASE_READY             = 0x01U,    /*!< HASH peripheral is ready to start                    */
00077   HAL_HASH_PHASE_PROCESS           = 0x02U,    /*!< HASH peripheral is in HASH processing phase          */
00078   HAL_HASH_PHASE_HMAC_STEP_1       = 0x03U,    /*!< HASH peripheral is in HMAC step 1 processing phase
00079                                               (step 1 consists in entering the inner hash function key) */
00080   HAL_HASH_PHASE_HMAC_STEP_2       = 0x04U,    /*!< HASH peripheral is in HMAC step 2 processing phase
00081                                               (step 2 consists in entering the message text) */
00082   HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase
00083                                               (step 3 consists in entering the outer hash function key) */
00084 }HAL_HASH_PhaseTypeDef;
00085
00086 /**
00087   * @brief HAL HASH mode suspend definitions
00088   */
00089 typedef enum
00090 {
00091   HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */
00092   HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */
00093 }HAL_HASH_SuspendTypeDef;
00094
00095 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
00096 /**
00097   * @brief  HAL HASH common Callback ID enumeration definition
00098   */
00099 typedef enum
00100 {
00101   HAL_HASH_MSPINIT_CB_ID           = 0x00U,    /*!< HASH MspInit callback ID     */
00102   HAL_HASH_MSPDEINIT_CB_ID         = 0x01U,    /*!< HASH MspDeInit callback ID   */
00103   HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID */
00104   HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */
00105   HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID     */
00106 }HAL_HASH_CallbackIDTypeDef;
00107 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00108
00109
00110 /**
00111   * @brief  HASH Handle Structure definition
00112   */
00113 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00114 typedef struct __HASH_HandleTypeDef
00115 #else
00116 typedef struct
00117 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
00118 {
00119   HASH_InitTypeDef           Init;             /*!< HASH required parameters */
00120
00121   uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
00122
00123   uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
00124
00125   uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
00126
00127   uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
00128
00129   uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
00130
00131   __IO uint32_t              HashInCount;      /*!< Counter of inputted data */
00132
00133   __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */
00134
00135   __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
00136
00137   HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
00138
00139   HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */
00140
00141   DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
00142
00143   HAL_LockTypeDef            Lock;             /*!< Locking object */
00144
00145   __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */
00146
00147   HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */
00148
00149   FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
00150
00151   __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */
00152
00153   __IO  uint32_t             ErrorCode;        /*!< HASH Error code */
00154
00155 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00156   void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */
00157
00158   void    (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash);  /*!< HASH digest computation completion callback */
00159
00160   void    (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash);     /*!< HASH error callback */
00161
00162   void    (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash);   /*!< HASH Msp Init callback */
00163
00164   void    (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
00165
00166 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
00167 } HASH_HandleTypeDef;
00168
00169 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
00170 /**
00171   * @brief  HAL HASH Callback pointer definition
00172   */
00173 typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
00174 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported constants --------------------------------------------------------*/
00181
00182 /** @defgroup HASH_Exported_Constants  HASH Exported Constants
00183   * @{
00184   */
00185
00186 /** @defgroup HASH_Algo_Selection   HASH algorithm selection
00187   * @{
00188   */
00189 #define HASH_ALGOSELECTION_SHA1      0x00000000U /*!< HASH function is SHA1   */
00190 #define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
00191 #define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
00192 #define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
00198   * @{
00199   */
00200 #define HASH_ALGOMODE_HASH         0x00000000U /*!< Algorithm is HASH */
00201 #define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup HASH_Data_Type      HASH input data type
00207   * @{
00208   */
00209 #define HASH_DATATYPE_32B          0x00000000U /*!< 32-bit data. No swapping                     */
00210 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
00211 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
00212 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
00218   * @{
00219   */
00220 #define HASH_HMAC_KEYTYPE_SHORTKEY      0x00000000U /*!< HMAC Key size is <= 64 bytes */
00221 #define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup HASH_flags_definition  HASH flags definitions
00227   * @{
00228   */
00229 #define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
00230 #define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
00231 #define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
00232 #define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
00233 #define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup HASH_interrupts_definition   HASH interrupts definitions
00240   * @{
00241   */
00242 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
00243 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
00244
00245 /**
00246   * @}
00247   */
00248 /** @defgroup HASH_alias HASH API alias
00249   * @{
00250   */
00251 #define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup HASH_Error_Definition   HASH Error Definition
00257   * @{
00258   */
00259 #define  HAL_HASH_ERROR_NONE             0x00000000U   /*!< No error                */
00260 #define  HAL_HASH_ERROR_IT               0x00000001U   /*!< IT-based process error  */
00261 #define  HAL_HASH_ERROR_DMA              0x00000002U   /*!< DMA-based process error */
00262 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
00263 #define  HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U   /*!< Invalid Callback error  */
00264 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported macros -----------------------------------------------------------*/
00274 /** @defgroup HASH_Exported_Macros HASH Exported Macros
00275   * @{
00276   */
00277
00278 /** @brief  Check whether or not the specified HASH flag is set.
00279   * @param  __FLAG__: specifies the flag to check.
00280   *        This parameter can be one of the following values:
00281   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
00282   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
00283   *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
00284   *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
00285   *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
00286   * @retval The new state of __FLAG__ (TRUE or FALSE).
00287   */
00288 #define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
00289                                        ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
00290                                        ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
00291
00292
00293 /** @brief  Clear the specified HASH flag.
00294   * @param  __FLAG__: specifies the flag to clear.
00295   *        This parameter can be one of the following values:
00296   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
00297   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
00298   * @retval None
00299   */
00300 #define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
00301
00302
00303 /** @brief  Enable the specified HASH interrupt.
00304   * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
00305   *          This parameter can be one of the following values:
00306   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
00307   *            @arg @ref HASH_IT_DCI   Digest calculation complete
00308   * @retval None
00309   */
00310 #define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
00311
00312 /** @brief  Disable the specified HASH interrupt.
00313   * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
00314   *          This parameter can be one of the following values:
00315   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
00316   *            @arg @ref HASH_IT_DCI   Digest calculation complete
00317   * @retval None
00318   */
00319 #define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
00320
00321 /** @brief Reset HASH handle state.
00322   * @param  __HANDLE__: HASH handle.
00323   * @retval None
00324   */
00325
00326 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00327 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
00328                                                       (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
00329                                                       (__HANDLE__)->MspInitCallback = NULL;      \
00330                                                       (__HANDLE__)->MspDeInitCallback = NULL;    \
00331                                                      }while(0)
00332 #else
00333 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
00334 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00335
00336
00337 /** @brief Reset HASH handle status.
00338   * @param  __HANDLE__: HASH handle.
00339   * @retval None
00340   */
00341 #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
00342
00343 /**
00344   * @brief  Enable the multi-buffer DMA transfer mode.
00345   * @note   This bit is set when hashing large files when multiple DMA transfers are needed.
00346   * @retval None
00347   */
00348 #define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT)
00349
00350 /**
00351   * @brief  Disable the multi-buffer DMA transfer mode.
00352   * @retval None
00353   */
00354 #define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
00355
00356
00357 /**
00358   * @brief Start the digest computation.
00359   * @retval None
00360   */
00361 #define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
00362
00363 /**
00364   * @brief Set the number of valid bits in the last word written in data register DIN.
00365   * @param  __SIZE__: size in bytes of last data written in Data register.
00366   * @retval None
00367 */
00368 #define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
00369
00370 /**
00371   * @brief Reset the HASH core.
00372   * @retval None
00373   */
00374 #define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)
00375
00376 /**
00377   * @}
00378   */
00379
00380
00381 /* Private macros --------------------------------------------------------*/
00382 /** @defgroup HASH_Private_Macros   HASH Private Macros
00383   * @{
00384   */
00385 /**
00386   * @brief  Return digest length in bytes.
00387   * @retval Digest length
00388   */
00389 #define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : \
00390                              ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28U : \
00391                              ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32U : 16U ) ) )
00392 /**
00393   * @brief  Return number of words already pushed in the FIFO.
00394   * @retval Number of words already pushed in the FIFO
00395   */
00396 #define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
00397
00398 /**
00399   * @brief Ensure that HASH input data type is valid.
00400   * @param __DATATYPE__: HASH input data type.
00401   * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
00402   */
00403 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
00404                                         ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
00405                                         ((__DATATYPE__) == HASH_DATATYPE_8B) || \
00406                                         ((__DATATYPE__) == HASH_DATATYPE_1B))
00407
00408
00409
00410 /**
00411   * @brief Ensure that input data buffer size is valid for multi-buffer HASH
00412   *        processing in polling mode.
00413   * @note  This check is valid only for multi-buffer HASH processing in polling mode.
00414   * @param __SIZE__: input data buffer size.
00415   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00416   */
00417 #define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4U) == 0U)
00418 /**
00419   * @brief Ensure that input data buffer size is valid for multi-buffer HASH
00420   *        processing in DMA mode.
00421   * @note  This check is valid only for multi-buffer HASH processing in DMA mode.
00422   * @param __SIZE__: input data buffer size.
00423   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00424   */
00425 #define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
00426
00427 /**
00428   * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
00429   *        processing in DMA mode.
00430   * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.
00431   * @param __HANDLE__: HASH handle.
00432   * @param __SIZE__: input data buffer size.
00433   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00434   */
00435 #define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
00436 /**
00437   * @brief Ensure that handle phase is set to HASH processing.
00438   * @param __HANDLE__: HASH handle.
00439   * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
00440   */
00441 #define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
00442
00443 /**
00444   * @brief Ensure that handle phase is set to HMAC processing.
00445   * @param __HANDLE__: HASH handle.
00446   * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
00447   */
00448 #define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
00449                                          ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
00450                                          ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
00451
00452 /**
00453   * @}
00454   */
00455
00456 /* Include HASH HAL Extended module */
00457 #include "stm32h7xx_hal_hash_ex.h"
00458 /* Exported functions --------------------------------------------------------*/
00459
00460 /** @addtogroup HASH_Exported_Functions HASH Exported Functions
00461   * @{
00462   */
00463
00464 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00465   * @{
00466   */
00467
00468 /* Initialization/de-initialization methods  **********************************/
00469 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
00470 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
00471 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
00472 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
00473 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
00474 void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
00475 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
00476 /* Callbacks Register/UnRegister functions  ***********************************/
00477 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
00478 HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
00479 HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
00480 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
00481
00482
00483 /**
00484   * @}
00485   */
00486
00487 /** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
00488   * @{
00489   */
00490
00491
00492 /* HASH processing using polling  *********************************************/
00493 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00494 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00495 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00496 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00497
00498 /**
00499   * @}
00500   */
00501
00502 /** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
00503   * @{
00504   */
00505
00506 /* HASH processing using IT  **************************************************/
00507 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00508 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00509 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
00510 /**
00511   * @}
00512   */
00513
00514 /** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
00515   * @{
00516   */
00517
00518 /* HASH processing using DMA  *************************************************/
00519 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00520 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00521 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00522 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00523
00524 /**
00525   * @}
00526   */
00527
00528 /** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
00529   * @{
00530   */
00531
00532 /* HASH-MAC processing using polling  *****************************************/
00533 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00534 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00535
00536 /**
00537   * @}
00538   */
00539
00540 /** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
00541   * @{
00542   */
00543
00544 HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00545 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00546
00547 /**
00548   * @}
00549   */
00550
00551 /** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
00552   * @{
00553   */
00554
00555 /* HASH-HMAC processing using DMA  ********************************************/
00556 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00557 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00558
00559 /**
00560   * @}
00561   */
00562
00563 /** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
00564   * @{
00565   */
00566
00567
00568 /* Peripheral State methods  **************************************************/
00569 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
00570 HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
00571 void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
00572 void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
00573 void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
00574 HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
00575 uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
00576
00577 /**
00578   * @}
00579   */
00580
00581 /**
00582   * @}
00583   */
00584
00585 /* Private functions -----------------------------------------------------------*/
00586
00587 /** @addtogroup HASH_Private_Functions HASH Private Functions
00588   * @{
00589   */
00590
00591 /* Private functions */
00592 HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
00593 HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00594 HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
00595 HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00596 HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00597 HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
00598 HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
00599 HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00600
00601 /**
00602   * @}
00603   */
00604
00605 /**
00606   * @}
00607   */
00608 #endif /*  HASH*/
00609 /**
00610   * @}
00611   */
00612
00613
00614 #ifdef __cplusplus
00615 }
00616 #endif
00617
00618
00619 #endif /* STM32H7xx_HAL_HASH_H */
00620
00621 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash_ex.c Source File

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stm32h7xx_hal_hash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended HASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the HASH peripheral for SHA-224 and SHA-256
00008   *          alogrithms:
00009   *           + HASH or HMAC processing in polling mode
00010   *           + HASH or HMAC processing in interrupt mode
00011   *           + HASH or HMAC processing in DMA mode
00012   *         Additionally, this file provides functions to manage HMAC
00013   *         multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
00014   *         and SHA-256.
00015   *
00016   *
00017   @verbatim
00018  ===============================================================================
00019                      ##### HASH peripheral extended features  #####
00020  ===============================================================================
00021     [..]
00022     The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
00023     the same way as for SHA-1 or MD-5 algorithms.
00024     (#) Three modes are available.
00025         (##) Polling mode: processing APIs are blocking functions
00026              i.e. they process the data and wait till the digest computation is finished,
00027              e.g. HAL_HASHEx_xxx_Start()
00028         (##) Interrupt mode: processing APIs are not blocking functions
00029                 i.e. they process the data under interrupt,
00030                 e.g. HAL_HASHEx_xxx_Start_IT()
00031         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00032              not used for data transfer i.e. the data transfer is ensured by DMA,
00033                 e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
00034                 HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
00035
00036    (#)Multi-buffer processing is possible in polling and DMA mode.
00037         (##) In polling mode, only multi-buffer HASH processing is possible.
00038              API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
00039              User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
00040              well the computed digest.
00041
00042         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
00043
00044               (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
00045              From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
00046              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
00047              macro then wrap-up the HASH processing in feeding the last input buffer thru the
00048              same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
00049              API HAL_HASHEx_xxx_Finish().
00050
00051              (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
00052              extended functions): after initialization, the key and the first input buffer are entered
00053              in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00054              starts step 2.
00055              The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
00056              point, the HMAC processing is still carrying out step 2.
00057              Then, step 2 for the last input buffer and step 3 are carried out by a single call
00058              to HAL_HMACEx_xxx_Step2_3_DMA().
00059
00060              The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
00061              MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
00062
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00069   * All rights reserved.</center></h2>
00070   *
00071   * This software component is licensed by ST under BSD 3-Clause license,
00072   * the "License"; You may not use this file except in compliance with the
00073   * License. You may obtain a copy of the License at:
00074   *                        opensource.org/licenses/BSD-3-Clause
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32h7xx_hal.h"
00081
00082
00083
00084
00085 /** @addtogroup STM32H7xx_HAL_Driver
00086   * @{
00087   */
00088 #if defined (HASH)
00089
00090 /** @defgroup HASHEx HASHEx
00091   * @brief HASH HAL extended module driver.
00092   * @{
00093   */
00094 #ifdef HAL_HASH_MODULE_ENABLED
00095 /* Private typedef -----------------------------------------------------------*/
00096 /* Private define ------------------------------------------------------------*/
00097 /* Private functions ---------------------------------------------------------*/
00098
00099
00100 /** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
00101   * @{
00102   */
00103
00104 /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
00105  *  @brief   HASH extended processing functions using polling mode.
00106  *
00107 @verbatim
00108  ===============================================================================
00109                ##### Polling mode HASH extended processing functions #####
00110  ===============================================================================
00111     [..]  This section provides functions allowing to calculate in polling mode
00112           the hash value using one of the following algorithms:
00113       (+) SHA224
00114          (++) HAL_HASHEx_SHA224_Start()
00115          (++) HAL_HASHEx_SHA224_Accumulate()
00116       (+) SHA256
00117          (++) HAL_HASHEx_SHA256_Start()
00118          (++) HAL_HASHEx_SHA256_Accumulate()
00119
00120     [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
00121
00122     [..]  In case of multi-buffer HASH processing (a single digest is computed while
00123           several buffers are fed to the IP), the user can resort to successive calls
00124           to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
00125           to HAL_HASHEx_xxx_Start().
00126
00127 @endverbatim
00128   * @{
00129   */
00130
00131
00132 /**
00133   * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
00134   *         read the computed digest.
00135   * @note   Digest is available in pOutBuffer.
00136   * @param  hhash: HASH handle.
00137   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00138   * @param  Size: length of the input buffer in bytes.
00139   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00140   * @param  Timeout: Timeout value
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00144 {
00145   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
00146 }
00147
00148 /**
00149   * @brief  If not already done, initialize the HASH peripheral in SHA224 mode then
00150   *         processes pInBuffer.
00151   * @note   Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
00152   *         several input buffers back-to-back to the IP that will yield a single
00153   *         HASH signature once all buffers have been entered. Wrap-up of input
00154   *         buffers feeding and retrieval of digest is done by a call to
00155   *         HAL_HASHEx_SHA224_Start().
00156   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00157   *         the IP has already been initialized.
00158   * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
00159   *         to read it, feeding at the same time the last input buffer to the IP.
00160   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00161   *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
00162   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00163   * @param  hhash: HASH handle.
00164   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00165   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00169 {
00170   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
00171 }
00172
00173 /**
00174   * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
00175   *         read the computed digest.
00176   * @note   Digest is available in pOutBuffer.
00177   * @param  hhash: HASH handle.
00178   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00179   * @param  Size: length of the input buffer in bytes.
00180   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00181   * @param  Timeout: Timeout value
00182   * @retval HAL status
00183   */
00184 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00185 {
00186   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
00187 }
00188
00189 /**
00190   * @brief  If not already done, initialize the HASH peripheral in SHA256 mode then
00191   *         processes pInBuffer.
00192   * @note   Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
00193   *         several input buffers back-to-back to the IP that will yield a single
00194   *         HASH signature once all buffers have been entered. Wrap-up of input
00195   *         buffers feeding and retrieval of digest is done by a call to
00196   *         HAL_HASHEx_SHA256_Start().
00197   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00198   *         the IP has already been initialized.
00199   * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
00200   *         to read it, feeding at the same time the last input buffer to the IP.
00201   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00202   *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
00203   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00204   * @param  hhash: HASH handle.
00205   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00206   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00207   * @retval HAL status
00208   */
00209 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00210 {
00211   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
00212 }
00213
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
00220  *  @brief   HASH extended processing functions using interrupt mode.
00221  *
00222 @verbatim
00223  ===============================================================================
00224           ##### Interruption mode HASH extended processing functions #####
00225  ===============================================================================
00226     [..]  This section provides functions allowing to calculate in interrupt mode
00227           the hash value using one of the following algorithms:
00228       (+) SHA224
00229          (++) HAL_HASHEx_SHA224_Start_IT()
00230       (+) SHA256
00231          (++) HAL_HASHEx_SHA256_Start_IT()
00232
00233 @endverbatim
00234   * @{
00235   */
00236
00237
00238 /**
00239   * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
00240   *         read the computed digest in interruption mode.
00241   * @note   Digest is available in pOutBuffer.
00242   * @param  hhash: HASH handle.
00243   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00244   * @param  Size: length of the input buffer in bytes.
00245   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00246   * @retval HAL status
00247   */
00248 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00249 {
00250   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
00251 }
00252
00253 /**
00254   * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
00255   *         read the computed digest in interruption mode.
00256   * @note   Digest is available in pOutBuffer.
00257   * @param  hhash: HASH handle.
00258   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00259   * @param  Size: length of the input buffer in bytes.
00260   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00264 {
00265   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
00266 }
00267
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
00273  *  @brief   HASH extended processing functions using DMA mode.
00274  *
00275 @verbatim
00276  ===============================================================================
00277                 ##### DMA mode HASH extended  processing functionss #####
00278  ===============================================================================
00279     [..]  This section provides functions allowing to calculate in DMA mode
00280           the hash value using one of the following algorithms:
00281       (+) SHA224
00282          (++) HAL_HASHEx_SHA224_Start_DMA()
00283          (++) HAL_HASHEx_SHA224_Finish()
00284       (+) SHA256
00285          (++) HAL_HASHEx_SHA256_Start_DMA()
00286          (++) HAL_HASHEx_SHA256_Finish()
00287
00288     [..]  When resorting to DMA mode to enter the data in the IP, user must resort
00289           to  HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
00290           HAL_HASHEx_xxx_Finish().
00291
00292     [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
00293           the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
00294           reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
00295           retrieved thanks to HAL_HASHEx_xxx_Finish().
00296
00297 @endverbatim
00298   * @{
00299   */
00300
00301
00302
00303
00304 /**
00305   * @brief  Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
00306   *         to feed the input buffer to the IP.
00307   * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
00308   *         be called to retrieve the computed digest.
00309   * @param  hhash: HASH handle.
00310   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00311   * @param  Size: length of the input buffer in bytes.
00312   * @retval HAL status
00313   */
00314 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00315 {
00316   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00317 }
00318
00319 /**
00320   * @brief  Return the computed digest in SHA224 mode.
00321   * @note   The API waits for DCIS to be set then reads the computed digest.
00322   * @note   HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
00323   *         HMAC SHA224 mode.
00324   * @param  hhash: HASH handle.
00325   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00326   * @param  Timeout: Timeout value.
00327   * @retval HAL status
00328   */
00329 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00330 {
00331    return HASH_Finish(hhash, pOutBuffer, Timeout);
00332 }
00333
00334 /**
00335   * @brief  Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
00336   *         to feed the input buffer to the IP.
00337   * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
00338   *         be called to retrieve the computed digest.
00339   * @param  hhash: HASH handle.
00340   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00341   * @param  Size: length of the input buffer in bytes.
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00345 {
00346   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00347 }
00348
00349 /**
00350   * @brief  Return the computed digest in SHA256 mode.
00351   * @note   The API waits for DCIS to be set then reads the computed digest.
00352   * @note   HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
00353   *         HMAC SHA256 mode.
00354   * @param  hhash: HASH handle.
00355   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00356   * @param  Timeout: Timeout value.
00357   * @retval HAL status
00358   */
00359 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00360 {
00361    return HASH_Finish(hhash, pOutBuffer, Timeout);
00362 }
00363
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
00369  *  @brief   HMAC extended processing functions using polling mode.
00370  *
00371 @verbatim
00372  ===============================================================================
00373              ##### Polling mode HMAC extended processing functions #####
00374  ===============================================================================
00375     [..]  This section provides functions allowing to calculate in polling mode
00376           the HMAC value using one of the following algorithms:
00377       (+) SHA224
00378          (++) HAL_HMACEx_SHA224_Start()
00379       (+) SHA256
00380          (++) HAL_HMACEx_SHA256_Start()
00381
00382 @endverbatim
00383   * @{
00384   */
00385
00386
00387
00388 /**
00389   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
00390   *         read the computed digest.
00391   * @note   Digest is available in pOutBuffer.
00392   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00393   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00394   * @param  hhash: HASH handle.
00395   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00396   * @param  Size: length of the input buffer in bytes.
00397   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00398   * @param  Timeout: Timeout value.
00399   * @retval HAL status
00400   */
00401 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00402 {
00403   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
00404 }
00405
00406 /**
00407   * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
00408   *         read the computed digest.
00409   * @note   Digest is available in pOutBuffer.
00410   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00411   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00412   * @param  hhash: HASH handle.
00413   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00414   * @param  Size: length of the input buffer in bytes.
00415   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00416   * @param  Timeout: Timeout value.
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00420 {
00421   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
00422 }
00423
00424 /**
00425   * @}
00426   */
00427
00428
00429 /** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
00430  *  @brief   HMAC extended processing functions using interruption mode.
00431  *
00432 @verbatim
00433  ===============================================================================
00434              ##### Interrupt mode HMAC extended processing functions #####
00435  ===============================================================================
00436     [..]  This section provides functions allowing to calculate in interrupt mode
00437           the HMAC value using one of the following algorithms:
00438       (+) SHA224
00439          (++) HAL_HMACEx_SHA224_Start_IT()
00440       (+) SHA256
00441          (++) HAL_HMACEx_SHA256_Start_IT()
00442
00443 @endverbatim
00444   * @{
00445   */
00446
00447
00448
00449 /**
00450   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
00451   *         read the computed digest in interrupt mode.
00452   * @note   Digest is available in pOutBuffer.
00453   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00454   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00455   * @param  hhash: HASH handle.
00456   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00457   * @param  Size: length of the input buffer in bytes.
00458   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00459   * @retval HAL status
00460   */
00461 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00462 {
00463   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
00464 }
00465
00466 /**
00467   * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
00468   *         read the computed digest in interrupt mode.
00469   * @note   Digest is available in pOutBuffer.
00470   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00471   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00472   * @param  hhash: HASH handle.
00473   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00474   * @param  Size: length of the input buffer in bytes.
00475   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00476   * @retval HAL status
00477   */
00478 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00479 {
00480   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
00481 }
00482
00483
00484
00485
00486 /**
00487   * @}
00488   */
00489
00490
00491 /** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
00492  *  @brief   HMAC extended processing functions using DMA mode.
00493  *
00494 @verbatim
00495  ===============================================================================
00496               ##### DMA mode HMAC extended processing functions #####
00497  ===============================================================================
00498     [..]  This section provides functions allowing to calculate in DMA mode
00499           the HMAC value using one of the following algorithms:
00500       (+) SHA224
00501          (++) HAL_HMACEx_SHA224_Start_DMA()
00502       (+) SHA256
00503          (++) HAL_HMACEx_SHA256_Start_DMA()
00504
00505     [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
00506           user must resort to  HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
00507           with HAL_HASHEx_xxx_Finish().
00508
00509
00510 @endverbatim
00511   * @{
00512   */
00513
00514
00515
00516 /**
00517   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
00518   *         DMA transfers to feed the key and the input buffer to the IP.
00519   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00520   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
00521   *         the computed digest.
00522   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00523   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00524   * @note   If MDMAT bit is set before calling this function (multi-buffer
00525   *          HASH processing case), the input buffer size (in bytes) must be
00526   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00527   *          For the processing of the last buffer of the thread, MDMAT bit must
00528   *          be reset and the buffer length (in bytes) doesn't have to be a
00529   *          multiple of 4.
00530   * @param  hhash: HASH handle.
00531   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00532   * @param  Size: length of the input buffer in bytes.
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00536 {
00537   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00538 }
00539
00540 /**
00541   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
00542   *         DMA transfers to feed the key and the input buffer to the IP.
00543   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00544   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00545   *         the computed digest.
00546   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00547   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00548   * @note   If MDMAT bit is set before calling this function (multi-buffer
00549   *          HASH processing case), the input buffer size (in bytes) must be
00550   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00551   *          For the processing of the last buffer of the thread, MDMAT bit must
00552   *          be reset and the buffer length (in bytes) doesn't have to be a
00553   *          multiple of 4.
00554   * @param  hhash: HASH handle.
00555   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00556   * @param  Size: length of the input buffer in bytes.
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00560 {
00561   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00562 }
00563
00564
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
00570  *  @brief   HMAC extended processing functions in multi-buffer DMA mode.
00571  *
00572 @verbatim
00573  ===============================================================================
00574       ##### Multi-buffer DMA mode HMAC extended processing functions #####
00575  ===============================================================================
00576     [..]  This section provides functions to manage HMAC multi-buffer
00577           DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
00578       (+) MD5
00579          (++) HAL_HMACEx_MD5_Step1_2_DMA()
00580          (++) HAL_HMACEx_MD5_Step2_DMA()
00581          (++) HAL_HMACEx_MD5_Step2_3_DMA()
00582       (+) SHA1
00583          (++) HAL_HMACEx_SHA1_Step1_2_DMA()
00584          (++) HAL_HMACEx_SHA1_Step2_DMA()
00585          (++) HAL_HMACEx_SHA1_Step2_3_DMA()
00586
00587       (+) SHA256
00588          (++) HAL_HMACEx_SHA224_Step1_2_DMA()
00589          (++) HAL_HMACEx_SHA224_Step2_DMA()
00590          (++) HAL_HMACEx_SHA224_Step2_3_DMA()
00591       (+) SHA256
00592          (++) HAL_HMACEx_SHA256_Step1_2_DMA()
00593          (++) HAL_HMACEx_SHA256_Step2_DMA()
00594          (++) HAL_HMACEx_SHA256_Step2_3_DMA()
00595
00596     [..]  User must first start-up the multi-buffer DMA-based HMAC computation in
00597           calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00598           intiates step 2 with the first input buffer.
00599
00600     [..]  The following buffers are next fed to the IP with a call to the API
00601           HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
00602           to this API.
00603
00604     [..]  Multi-buffer DMA-based HMAC computation is wrapped up by a call to
00605           HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
00606           buffer to the IP then carries out step 3.
00607
00608     [..]  Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
00609           SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
00610
00611     [..]  If only two buffers need to be consecutively processed, a call to
00612           HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
00613           is sufficient.
00614
00615 @endverbatim
00616   * @{
00617   */
00618
00619 /**
00620   * @brief  MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00621   * @note   Step 1 consists in writing the inner hash function key in the IP,
00622   *         step 2 consists in writing the message text.
00623   * @note   The API carries out the HMAC step 1 then starts step 2 with
00624   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00625   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00626   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00627   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00628   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00629   *         HASH digest computation is corrupted.
00630   * @param  hhash: HASH handle.
00631   * @param  pInBuffer: pointer to the input buffer (message buffer).
00632   * @param  Size: length of the input buffer in bytes.
00633   * @retval HAL status
00634   */
00635 HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00636 {
00637   hhash->DigestCalculationDisable = SET;
00638   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00639 }
00640
00641 /**
00642   * @brief  MD5 HMAC step 2 in multi-buffer DMA mode.
00643   * @note   Step 2 consists in writing the message text in the IP.
00644   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00645   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00646   *         allowing other messages DMA transfers to occur.
00647   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00648   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00649   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00650   *         HASH digest computation is corrupted.
00651   * @param  hhash: HASH handle.
00652   * @param  pInBuffer: pointer to the input buffer (message buffer).
00653   * @param  Size: length of the input buffer in bytes.
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00657 {
00658   if (hhash->DigestCalculationDisable != SET)
00659   {
00660     return HAL_ERROR;
00661   }
00662   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00663 }
00664
00665 /**
00666   * @brief  MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00667   * @note   Step 2 consists in writing the message text in the IP,
00668   *         step 3 consists in writing the outer hash function key.
00669   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00670   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00671   *         then carries out HMAC step 3.
00672   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00673   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00674   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00675   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00676   *         the computed digest.
00677   * @param  hhash: HASH handle.
00678   * @param  pInBuffer: pointer to the input buffer (message buffer).
00679   * @param  Size: length of the input buffer in bytes.
00680   * @retval HAL status
00681   */
00682 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00683 {
00684   hhash->DigestCalculationDisable = RESET;
00685   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00686 }
00687
00688
00689 /**
00690   * @brief  SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00691   * @note   Step 1 consists in writing the inner hash function key in the IP,
00692   *         step 2 consists in writing the message text.
00693   * @note   The API carries out the HMAC step 1 then starts step 2 with
00694   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00695   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00696   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00697   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00698   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00699   *         HASH digest computation is corrupted.
00700   * @param  hhash: HASH handle.
00701   * @param  pInBuffer: pointer to the input buffer (message buffer).
00702   * @param  Size: length of the input buffer in bytes.
00703   * @retval HAL status
00704   */
00705 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00706 {
00707   hhash->DigestCalculationDisable = SET;
00708   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00709 }
00710
00711 /**
00712   * @brief  SHA1 HMAC step 2 in multi-buffer DMA mode.
00713   * @note   Step 2 consists in writing the message text in the IP.
00714   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00715   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00716   *         allowing other messages DMA transfers to occur.
00717   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00718   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00719   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00720   *         HASH digest computation is corrupted.
00721   * @param  hhash: HASH handle.
00722   * @param  pInBuffer: pointer to the input buffer (message buffer).
00723   * @param  Size: length of the input buffer in bytes.
00724   * @retval HAL status
00725   */
00726 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00727 {
00728   if (hhash->DigestCalculationDisable != SET)
00729   {
00730     return HAL_ERROR;
00731   }
00732   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00733 }
00734
00735 /**
00736   * @brief  SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00737   * @note   Step 2 consists in writing the message text in the IP,
00738   *         step 3 consists in writing the outer hash function key.
00739   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00740   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00741   *         then carries out HMAC step 3.
00742   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00743   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00744   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00745   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00746   *         the computed digest.
00747   * @param  hhash: HASH handle.
00748   * @param  pInBuffer: pointer to the input buffer (message buffer).
00749   * @param  Size: length of the input buffer in bytes.
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00753 {
00754   hhash->DigestCalculationDisable = RESET;
00755   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00756 }
00757
00758 /**
00759   * @brief  SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00760   * @note   Step 1 consists in writing the inner hash function key in the IP,
00761   *         step 2 consists in writing the message text.
00762   * @note   The API carries out the HMAC step 1 then starts step 2 with
00763   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00764   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00765   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00766   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00767   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00768   *         HASH digest computation is corrupted.
00769   * @param  hhash: HASH handle.
00770   * @param  pInBuffer: pointer to the input buffer (message buffer).
00771   * @param  Size: length of the input buffer in bytes.
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00775 {
00776   hhash->DigestCalculationDisable = SET;
00777   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00778 }
00779
00780 /**
00781   * @brief  SHA224 HMAC step 2 in multi-buffer DMA mode.
00782   * @note   Step 2 consists in writing the message text in the IP.
00783   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00784   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00785   *         allowing other messages DMA transfers to occur.
00786   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00787   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00788   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00789   *         HASH digest computation is corrupted.
00790   * @param  hhash: HASH handle.
00791   * @param  pInBuffer: pointer to the input buffer (message buffer).
00792   * @param  Size: length of the input buffer in bytes.
00793   * @retval HAL status
00794   */
00795 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00796 {
00797   if (hhash->DigestCalculationDisable != SET)
00798   {
00799     return HAL_ERROR;
00800   }
00801   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00802 }
00803
00804 /**
00805   * @brief  SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00806   * @note   Step 2 consists in writing the message text in the IP,
00807   *         step 3 consists in writing the outer hash function key.
00808   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00809   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00810   *         then carries out HMAC step 3.
00811   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00812   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00813   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00814   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00815   *         the computed digest.
00816   * @param  hhash: HASH handle.
00817   * @param  pInBuffer: pointer to the input buffer (message buffer).
00818   * @param  Size: length of the input buffer in bytes.
00819   * @retval HAL status
00820   */
00821 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00822 {
00823   hhash->DigestCalculationDisable = RESET;
00824   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00825 }
00826
00827 /**
00828   * @brief  SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00829   * @note   Step 1 consists in writing the inner hash function key in the IP,
00830   *         step 2 consists in writing the message text.
00831   * @note   The API carries out the HMAC step 1 then starts step 2 with
00832   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00833   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00834   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00835   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00836   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00837   *         HASH digest computation is corrupted.
00838   * @param  hhash: HASH handle.
00839   * @param  pInBuffer: pointer to the input buffer (message buffer).
00840   * @param  Size: length of the input buffer in bytes.
00841   * @retval HAL status
00842   */
00843 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00844 {
00845   hhash->DigestCalculationDisable = SET;
00846   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00847 }
00848
00849 /**
00850   * @brief  SHA256 HMAC step 2 in multi-buffer DMA mode.
00851   * @note   Step 2 consists in writing the message text in the IP.
00852   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00853   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00854   *         allowing other messages DMA transfers to occur.
00855   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00856   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00857   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00858   *         HASH digest computation is corrupted.
00859   * @param  hhash: HASH handle.
00860   * @param  pInBuffer: pointer to the input buffer (message buffer).
00861   * @param  Size: length of the input buffer in bytes.
00862   * @retval HAL status
00863   */
00864 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00865 {
00866   if (hhash->DigestCalculationDisable != SET)
00867   {
00868     return HAL_ERROR;
00869   }
00870   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00871 }
00872
00873 /**
00874   * @brief  SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00875   * @note   Step 2 consists in writing the message text in the IP,
00876   *         step 3 consists in writing the outer hash function key.
00877   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00878   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00879   *         then carries out HMAC step 3.
00880   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00881   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00882   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00883   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00884   *         the computed digest.
00885   * @param  hhash: HASH handle.
00886   * @param  pInBuffer: pointer to the input buffer (message buffer).
00887   * @param  Size: length of the input buffer in bytes.
00888   * @retval HAL status
00889   */
00890 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00891 {
00892   hhash->DigestCalculationDisable = RESET;
00893   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00894 }
00895
00896 /**
00897   * @}
00898   */
00899
00900
00901 /**
00902   * @}
00903   */
00904 #endif /* HAL_HASH_MODULE_ENABLED */
00905
00906 /**
00907   * @}
00908   */
00909 #endif /*  HASH*/
00910 /**
00911   * @}
00912   */
00913
00914
00915
00916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hash_ex.h Source File

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stm32h7xx_hal_hash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_HASH_EX_H
00022 #define STM32H7xx_HAL_HASH_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined (HASH)
00035 /** @addtogroup HASHEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macro ------------------------------------------------------------*/
00042
00043
00044 /* Exported functions --------------------------------------------------------*/
00045
00046 /** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
00047   * @{
00048   */
00049
00050 /** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
00051   * @{
00052   */
00053
00054 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00055 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00056 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00057 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00058
00059 /**
00060   * @}
00061   */
00062
00063 /** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
00064   * @{
00065   */
00066
00067 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00068 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00069
00070 /**
00071   * @}
00072   */
00073
00074 /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
00075   * @{
00076   */
00077 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00078 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00079 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00080 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
00087   * @{
00088   */
00089 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00090 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00091 /**
00092   * @}
00093   */
00094
00095 /** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
00096   * @{
00097   */
00098
00099 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00100 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00101
00102 /**
00103   * @}
00104   */
00105
00106 /** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
00107   * @{
00108   */
00109
00110 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00111 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00112
00113 /**
00114   * @}
00115   */
00116
00117 /** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
00118   * @{
00119   */
00120
00121 HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00122 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00123 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00124
00125 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00126 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00127 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00128 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00129 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00130 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00131
00132 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00133 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00134 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /**
00144   * @}
00145   */
00146 #endif /*  HASH*/
00147 /**
00148   * @}
00149   */
00150
00151
00152 #ifdef __cplusplus
00153 }
00154 #endif
00155
00156
00157 #endif /* STM32H7xx_HAL_HASH_EX_H */
00158
00159 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hcd.c Source File

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stm32h7xx_hal_hcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @brief   HCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00019        HCD_HandleTypeDef  hhcd;
00020
00021     (#)Fill parameters of Init structure in HCD handle
00022
00023     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00024
00025     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00026         (##) Enable the HCD/USB Low Level interface clock using the following macros
00027              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00028              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00029              (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
00030
00031         (##) Initialize the related GPIO clocks
00032         (##) Configure HCD pin-out
00033         (##) Configure HCD NVIC interrupt
00034
00035     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00036         (##) hhcd.pData = phost;
00037
00038     (#)Enable HCD transmission and reception:
00039         (##) HAL_HCD_Start();
00040
00041   @endverbatim
00042   ******************************************************************************
00043   * @attention
00044   *
00045   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00046   * All rights reserved.</center></h2>
00047   *
00048   * This software component is licensed by ST under BSD 3-Clause license,
00049   * the "License"; You may not use this file except in compliance with the
00050   * License. You may obtain a copy of the License at:
00051   *                        opensource.org/licenses/BSD-3-Clause
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32h7xx_hal.h"
00058
00059 /** @addtogroup STM32H7xx_HAL_Driver
00060   * @{
00061   */
00062
00063 #ifdef HAL_HCD_MODULE_ENABLED
00064
00065 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00066
00067 /** @defgroup HCD HCD
00068   * @brief HCD HAL module driver
00069   * @{
00070   */
00071
00072 /* Private typedef -----------------------------------------------------------*/
00073 /* Private define ------------------------------------------------------------*/
00074 /* Private macro -------------------------------------------------------------*/
00075 /* Private variables ---------------------------------------------------------*/
00076 /* Private function prototypes -----------------------------------------------*/
00077 /** @defgroup HCD_Private_Functions HCD Private Functions
00078   * @{
00079   */
00080 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00081 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00082 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00083 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported functions --------------------------------------------------------*/
00089 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00090   * @{
00091   */
00092
00093 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00094  *  @brief    Initialization and Configuration functions
00095  *
00096 @verbatim
00097  ===============================================================================
00098           ##### Initialization and de-initialization functions #####
00099  ===============================================================================
00100     [..]  This section provides functions allowing to:
00101
00102 @endverbatim
00103   * @{
00104   */
00105
00106 /**
00107   * @brief  Initialize the host driver.
00108   * @param  hhcd HCD handle
00109   * @retval HAL status
00110   */
00111 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00112 {
00113   USB_OTG_GlobalTypeDef *USBx;
00114
00115   /* Check the HCD handle allocation */
00116   if (hhcd == NULL)
00117   {
00118     return HAL_ERROR;
00119   }
00120
00121   /* Check the parameters */
00122   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00123
00124   USBx = hhcd->Instance;
00125
00126   if (hhcd->State == HAL_HCD_STATE_RESET)
00127   {
00128     /* Allocate lock resource and initialize it */
00129     hhcd->Lock = HAL_UNLOCKED;
00130
00131 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00132     hhcd->SOFCallback = HAL_HCD_SOF_Callback;
00133     hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
00134     hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
00135     hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
00136     hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
00137     hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
00138
00139     if (hhcd->MspInitCallback == NULL)
00140     {
00141       hhcd->MspInitCallback = HAL_HCD_MspInit;
00142     }
00143
00144     /* Init the low level hardware */
00145     hhcd->MspInitCallback(hhcd);
00146 #else
00147     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00148     HAL_HCD_MspInit(hhcd);
00149 #endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
00150   }
00151
00152   hhcd->State = HAL_HCD_STATE_BUSY;
00153
00154   /* Disable DMA mode for FS instance */
00155   if ((USBx->CID & (0x1U << 8)) == 0U)
00156   {
00157     hhcd->Init.dma_enable = 0U;
00158   }
00159
00160   /* Disable the Interrupts */
00161   __HAL_HCD_DISABLE(hhcd);
00162
00163   /* Init the Core (common init.) */
00164   (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
00165
00166   /* Force Host Mode*/
00167   (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
00168
00169   /* Init Host */
00170   (void)USB_HostInit(hhcd->Instance, hhcd->Init);
00171
00172   hhcd->State = HAL_HCD_STATE_READY;
00173
00174   return HAL_OK;
00175 }
00176
00177 /**
00178   * @brief  Initialize a host channel.
00179   * @param  hhcd HCD handle
00180   * @param  ch_num Channel number.
00181   *         This parameter can be a value from 1 to 15
00182   * @param  epnum Endpoint number.
00183   *          This parameter can be a value from 1 to 15
00184   * @param  dev_address Current device address
00185   *          This parameter can be a value from 0 to 255
00186   * @param  speed Current device speed.
00187   *          This parameter can be one of these values:
00188   *            HCD_SPEED_HIGH: High speed mode,
00189   *            HCD_SPEED_FULL: Full speed mode,
00190   *            HCD_SPEED_LOW: Low speed mode
00191   * @param  ep_type Endpoint Type.
00192   *          This parameter can be one of these values:
00193   *            EP_TYPE_CTRL: Control type,
00194   *            EP_TYPE_ISOC: Isochronous type,
00195   *            EP_TYPE_BULK: Bulk type,
00196   *            EP_TYPE_INTR: Interrupt type
00197   * @param  mps Max Packet Size.
00198   *          This parameter can be a value from 0 to32K
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00202                                   uint8_t ch_num,
00203                                   uint8_t epnum,
00204                                   uint8_t dev_address,
00205                                   uint8_t speed,
00206                                   uint8_t ep_type,
00207                                   uint16_t mps)
00208 {
00209   HAL_StatusTypeDef status;
00210
00211   __HAL_LOCK(hhcd);
00212   hhcd->hc[ch_num].do_ping = 0U;
00213   hhcd->hc[ch_num].dev_addr = dev_address;
00214   hhcd->hc[ch_num].max_packet = mps;
00215   hhcd->hc[ch_num].ch_num = ch_num;
00216   hhcd->hc[ch_num].ep_type = ep_type;
00217   hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
00218
00219   if ((epnum & 0x80U) == 0x80U)
00220   {
00221     hhcd->hc[ch_num].ep_is_in = 1U;
00222   }
00223   else
00224   {
00225     hhcd->hc[ch_num].ep_is_in = 0U;
00226   }
00227
00228   hhcd->hc[ch_num].speed = speed;
00229
00230   status =  USB_HC_Init(hhcd->Instance,
00231                         ch_num,
00232                         epnum,
00233                         dev_address,
00234                         speed,
00235                         ep_type,
00236                         mps);
00237   __HAL_UNLOCK(hhcd);
00238
00239   return status;
00240 }
00241
00242 /**
00243   * @brief  Halt a host channel.
00244   * @param  hhcd HCD handle
00245   * @param  ch_num Channel number.
00246   *         This parameter can be a value from 1 to 15
00247   * @retval HAL status
00248   */
00249 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00250 {
00251   HAL_StatusTypeDef status = HAL_OK;
00252
00253   __HAL_LOCK(hhcd);
00254   (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
00255   __HAL_UNLOCK(hhcd);
00256
00257   return status;
00258 }
00259
00260 /**
00261   * @brief  DeInitialize the host driver.
00262   * @param  hhcd HCD handle
00263   * @retval HAL status
00264   */
00265 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00266 {
00267   /* Check the HCD handle allocation */
00268   if (hhcd == NULL)
00269   {
00270     return HAL_ERROR;
00271   }
00272
00273   hhcd->State = HAL_HCD_STATE_BUSY;
00274
00275 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00276   if (hhcd->MspDeInitCallback == NULL)
00277   {
00278     hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit  */
00279   }
00280
00281   /* DeInit the low level hardware */
00282   hhcd->MspDeInitCallback(hhcd);
00283 #else
00284   /* DeInit the low level hardware: CLOCK, NVIC.*/
00285   HAL_HCD_MspDeInit(hhcd);
00286 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00287
00288   __HAL_HCD_DISABLE(hhcd);
00289
00290   hhcd->State = HAL_HCD_STATE_RESET;
00291
00292   return HAL_OK;
00293 }
00294
00295 /**
00296   * @brief  Initialize the HCD MSP.
00297   * @param  hhcd HCD handle
00298   * @retval None
00299   */
00300 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00301 {
00302   /* Prevent unused argument(s) compilation warning */
00303   UNUSED(hhcd);
00304
00305   /* NOTE : This function should not be modified, when the callback is needed,
00306             the HAL_HCD_MspInit could be implemented in the user file
00307    */
00308 }
00309
00310 /**
00311   * @brief  DeInitialize the HCD MSP.
00312   * @param  hhcd HCD handle
00313   * @retval None
00314   */
00315 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00316 {
00317   /* Prevent unused argument(s) compilation warning */
00318   UNUSED(hhcd);
00319
00320   /* NOTE : This function should not be modified, when the callback is needed,
00321             the HAL_HCD_MspDeInit could be implemented in the user file
00322    */
00323 }
00324
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
00330   *  @brief   HCD IO operation functions
00331   *
00332 @verbatim
00333  ===============================================================================
00334                       ##### IO operation functions #####
00335  ===============================================================================
00336  [..] This subsection provides a set of functions allowing to manage the USB Host Data
00337     Transfer
00338
00339 @endverbatim
00340   * @{
00341   */
00342
00343 /**
00344   * @brief  Submit a new URB for processing.
00345   * @param  hhcd HCD handle
00346   * @param  ch_num Channel number.
00347   *         This parameter can be a value from 1 to 15
00348   * @param  direction Channel number.
00349   *          This parameter can be one of these values:
00350   *           0 : Output / 1 : Input
00351   * @param  ep_type Endpoint Type.
00352   *          This parameter can be one of these values:
00353   *            EP_TYPE_CTRL: Control type/
00354   *            EP_TYPE_ISOC: Isochronous type/
00355   *            EP_TYPE_BULK: Bulk type/
00356   *            EP_TYPE_INTR: Interrupt type/
00357   * @param  token Endpoint Type.
00358   *          This parameter can be one of these values:
00359   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00360   * @param  pbuff pointer to URB data
00361   * @param  length Length of URB data
00362   * @param  do_ping activate do ping protocol (for high speed only).
00363   *          This parameter can be one of these values:
00364   *           0 : do ping inactive / 1 : do ping active
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00368                                            uint8_t ch_num,
00369                                            uint8_t direction,
00370                                            uint8_t ep_type,
00371                                            uint8_t token,
00372                                            uint8_t *pbuff,
00373                                            uint16_t length,
00374                                            uint8_t do_ping)
00375 {
00376   hhcd->hc[ch_num].ep_is_in = direction;
00377   hhcd->hc[ch_num].ep_type  = ep_type;
00378
00379   if (token == 0U)
00380   {
00381     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00382     hhcd->hc[ch_num].do_ping = do_ping;
00383   }
00384   else
00385   {
00386     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00387   }
00388
00389   /* Manage Data Toggle */
00390   switch (ep_type)
00391   {
00392     case EP_TYPE_CTRL:
00393       if ((token == 1U) && (direction == 0U)) /*send data */
00394       {
00395         if (length == 0U)
00396         {
00397           /* For Status OUT stage, Length==0, Status Out PID = 1 */
00398           hhcd->hc[ch_num].toggle_out = 1U;
00399         }
00400
00401         /* Set the Data Toggle bit as per the Flag */
00402         if (hhcd->hc[ch_num].toggle_out == 0U)
00403         {
00404           /* Put the PID 0 */
00405           hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00406         }
00407         else
00408         {
00409           /* Put the PID 1 */
00410           hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00411         }
00412       }
00413       break;
00414
00415     case EP_TYPE_BULK:
00416       if (direction == 0U)
00417       {
00418         /* Set the Data Toggle bit as per the Flag */
00419         if (hhcd->hc[ch_num].toggle_out == 0U)
00420         {
00421           /* Put the PID 0 */
00422           hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00423         }
00424         else
00425         {
00426           /* Put the PID 1 */
00427           hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00428         }
00429       }
00430       else
00431       {
00432         if (hhcd->hc[ch_num].toggle_in == 0U)
00433         {
00434           hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00435         }
00436         else
00437         {
00438           hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00439         }
00440       }
00441
00442       break;
00443     case EP_TYPE_INTR:
00444       if (direction == 0U)
00445       {
00446         /* Set the Data Toggle bit as per the Flag */
00447         if (hhcd->hc[ch_num].toggle_out == 0U)
00448         {
00449           /* Put the PID 0 */
00450           hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00451         }
00452         else
00453         {
00454           /* Put the PID 1 */
00455           hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00456         }
00457       }
00458       else
00459       {
00460         if (hhcd->hc[ch_num].toggle_in == 0U)
00461         {
00462           hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00463         }
00464         else
00465         {
00466           hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00467         }
00468       }
00469       break;
00470
00471     case EP_TYPE_ISOC:
00472       hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00473       break;
00474
00475     default:
00476       break;
00477   }
00478
00479   hhcd->hc[ch_num].xfer_buff = pbuff;
00480   hhcd->hc[ch_num].xfer_len  = length;
00481   hhcd->hc[ch_num].urb_state = URB_IDLE;
00482   hhcd->hc[ch_num].xfer_count = 0U;
00483   hhcd->hc[ch_num].ch_num = ch_num;
00484   hhcd->hc[ch_num].state = HC_IDLE;
00485
00486   return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
00487 }
00488
00489 /**
00490   * @brief  Handle HCD interrupt request.
00491   * @param  hhcd HCD handle
00492   * @retval None
00493   */
00494 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00495 {
00496   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00497   uint32_t USBx_BASE = (uint32_t)USBx;
00498   uint32_t i, interrupt;
00499
00500   /* Ensure that we are in device mode */
00501   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00502   {
00503     /* Avoid spurious interrupt */
00504     if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00505     {
00506       return;
00507     }
00508
00509     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00510     {
00511       /* Incorrect mode, acknowledge the interrupt */
00512       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00513     }
00514
00515     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00516     {
00517       /* Incorrect mode, acknowledge the interrupt */
00518       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00519     }
00520
00521     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00522     {
00523       /* Incorrect mode, acknowledge the interrupt */
00524       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00525     }
00526
00527     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00528     {
00529       /* Incorrect mode, acknowledge the interrupt */
00530       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00531     }
00532
00533     /* Handle Host Disconnect Interrupts */
00534     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00535     {
00536       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00537
00538       if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
00539       {
00540         /* Handle Host Port Disconnect Interrupt */
00541 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00542         hhcd->DisconnectCallback(hhcd);
00543 #else
00544         HAL_HCD_Disconnect_Callback(hhcd);
00545 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00546
00547         (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
00548       }
00549     }
00550
00551     /* Handle Host Port Interrupts */
00552     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00553     {
00554       HCD_Port_IRQHandler(hhcd);
00555     }
00556
00557     /* Handle Host SOF Interrupt */
00558     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00559     {
00560 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00561       hhcd->SOFCallback(hhcd);
00562 #else
00563       HAL_HCD_SOF_Callback(hhcd);
00564 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00565
00566       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00567     }
00568
00569     /* Handle Host channel Interrupt */
00570     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00571     {
00572       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00573       for (i = 0U; i < hhcd->Init.Host_channels; i++)
00574       {
00575         if ((interrupt & (1UL << (i & 0xFU))) != 0U)
00576         {
00577           if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
00578           {
00579             HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
00580           }
00581           else
00582           {
00583             HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
00584           }
00585         }
00586       }
00587       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00588     }
00589
00590     /* Handle Rx Queue Level Interrupts */
00591     if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
00592     {
00593       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00594
00595       HCD_RXQLVL_IRQHandler(hhcd);
00596
00597       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00598     }
00599   }
00600 }
00601
00602 /**
00603   * @brief  SOF callback.
00604   * @param  hhcd HCD handle
00605   * @retval None
00606   */
00607 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00608 {
00609   /* Prevent unused argument(s) compilation warning */
00610   UNUSED(hhcd);
00611
00612   /* NOTE : This function should not be modified, when the callback is needed,
00613             the HAL_HCD_SOF_Callback could be implemented in the user file
00614    */
00615 }
00616
00617 /**
00618   * @brief Connection Event callback.
00619   * @param  hhcd HCD handle
00620   * @retval None
00621   */
00622 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00623 {
00624   /* Prevent unused argument(s) compilation warning */
00625   UNUSED(hhcd);
00626
00627   /* NOTE : This function should not be modified, when the callback is needed,
00628             the HAL_HCD_Connect_Callback could be implemented in the user file
00629    */
00630 }
00631
00632 /**
00633   * @brief  Disconnection Event callback.
00634   * @param  hhcd HCD handle
00635   * @retval None
00636   */
00637 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00638 {
00639   /* Prevent unused argument(s) compilation warning */
00640   UNUSED(hhcd);
00641
00642   /* NOTE : This function should not be modified, when the callback is needed,
00643             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00644    */
00645 }
00646
00647 /**
00648   * @brief  Port Enabled  Event callback.
00649   * @param  hhcd HCD handle
00650   * @retval None
00651   */
00652 __weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
00653 {
00654   /* Prevent unused argument(s) compilation warning */
00655   UNUSED(hhcd);
00656
00657   /* NOTE : This function should not be modified, when the callback is needed,
00658             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00659    */
00660 }
00661
00662 /**
00663   * @brief  Port Disabled  Event callback.
00664   * @param  hhcd HCD handle
00665   * @retval None
00666   */
00667 __weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
00668 {
00669   /* Prevent unused argument(s) compilation warning */
00670   UNUSED(hhcd);
00671
00672   /* NOTE : This function should not be modified, when the callback is needed,
00673             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00674    */
00675 }
00676
00677 /**
00678   * @brief  Notify URB state change callback.
00679   * @param  hhcd HCD handle
00680   * @param  chnum Channel number.
00681   *         This parameter can be a value from 1 to 15
00682   * @param  urb_state:
00683   *          This parameter can be one of these values:
00684   *            URB_IDLE/
00685   *            URB_DONE/
00686   *            URB_NOTREADY/
00687   *            URB_NYET/
00688   *            URB_ERROR/
00689   *            URB_STALL/
00690   * @retval None
00691   */
00692 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00693 {
00694   /* Prevent unused argument(s) compilation warning */
00695   UNUSED(hhcd);
00696   UNUSED(chnum);
00697   UNUSED(urb_state);
00698
00699   /* NOTE : This function should not be modified, when the callback is needed,
00700             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00701    */
00702 }
00703
00704 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00705 /**
00706   * @brief  Register a User USB HCD Callback
00707   *         To be used instead of the weak predefined callback
00708   * @param  hhcd USB HCD handle
00709   * @param  CallbackID ID of the callback to be registered
00710   *         This parameter can be one of the following values:
00711   *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
00712   *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
00713   *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
00714   *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
00715   *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
00716   *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
00717   *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
00718   * @param  pCallback pointer to the Callback function
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
00722 {
00723   HAL_StatusTypeDef status = HAL_OK;
00724
00725   if (pCallback == NULL)
00726   {
00727     /* Update the error code */
00728     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00729     return HAL_ERROR;
00730   }
00731   /* Process locked */
00732   __HAL_LOCK(hhcd);
00733
00734   if (hhcd->State == HAL_HCD_STATE_READY)
00735   {
00736     switch (CallbackID)
00737     {
00738       case HAL_HCD_SOF_CB_ID :
00739         hhcd->SOFCallback = pCallback;
00740         break;
00741
00742       case HAL_HCD_CONNECT_CB_ID :
00743         hhcd->ConnectCallback = pCallback;
00744         break;
00745
00746       case HAL_HCD_DISCONNECT_CB_ID :
00747         hhcd->DisconnectCallback = pCallback;
00748         break;
00749
00750       case HAL_HCD_PORT_ENABLED_CB_ID :
00751         hhcd->PortEnabledCallback = pCallback;
00752         break;
00753
00754       case HAL_HCD_PORT_DISABLED_CB_ID :
00755         hhcd->PortDisabledCallback = pCallback;
00756         break;
00757
00758       case HAL_HCD_MSPINIT_CB_ID :
00759         hhcd->MspInitCallback = pCallback;
00760         break;
00761
00762       case HAL_HCD_MSPDEINIT_CB_ID :
00763         hhcd->MspDeInitCallback = pCallback;
00764         break;
00765
00766       default :
00767         /* Update the error code */
00768         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00769         /* Return error status */
00770         status =  HAL_ERROR;
00771         break;
00772     }
00773   }
00774   else if (hhcd->State == HAL_HCD_STATE_RESET)
00775   {
00776     switch (CallbackID)
00777     {
00778       case HAL_HCD_MSPINIT_CB_ID :
00779         hhcd->MspInitCallback = pCallback;
00780         break;
00781
00782       case HAL_HCD_MSPDEINIT_CB_ID :
00783         hhcd->MspDeInitCallback = pCallback;
00784         break;
00785
00786       default :
00787         /* Update the error code */
00788         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00789         /* Return error status */
00790         status =  HAL_ERROR;
00791         break;
00792     }
00793   }
00794   else
00795   {
00796     /* Update the error code */
00797     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00798     /* Return error status */
00799     status =  HAL_ERROR;
00800   }
00801
00802   /* Release Lock */
00803   __HAL_UNLOCK(hhcd);
00804   return status;
00805 }
00806
00807 /**
00808   * @brief  Unregister an USB HCD Callback
00809   *         USB HCD callabck is redirected to the weak predefined callback
00810   * @param  hhcd USB HCD handle
00811   * @param  CallbackID ID of the callback to be unregistered
00812   *         This parameter can be one of the following values:
00813   *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
00814   *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
00815   *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
00816   *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
00817   *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
00818   *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
00819   *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
00820   * @retval HAL status
00821   */
00822 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
00823 {
00824   HAL_StatusTypeDef status = HAL_OK;
00825
00826   /* Process locked */
00827   __HAL_LOCK(hhcd);
00828
00829   /* Setup Legacy weak Callbacks  */
00830   if (hhcd->State == HAL_HCD_STATE_READY)
00831   {
00832     switch (CallbackID)
00833     {
00834       case HAL_HCD_SOF_CB_ID :
00835         hhcd->SOFCallback = HAL_HCD_SOF_Callback;
00836         break;
00837
00838       case HAL_HCD_CONNECT_CB_ID :
00839         hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
00840         break;
00841
00842       case HAL_HCD_DISCONNECT_CB_ID :
00843         hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
00844         break;
00845
00846       case HAL_HCD_PORT_ENABLED_CB_ID :
00847         hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
00848         break;
00849
00850       case HAL_HCD_PORT_DISABLED_CB_ID :
00851         hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
00852         break;
00853
00854       case HAL_HCD_MSPINIT_CB_ID :
00855         hhcd->MspInitCallback = HAL_HCD_MspInit;
00856         break;
00857
00858       case HAL_HCD_MSPDEINIT_CB_ID :
00859         hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
00860         break;
00861
00862       default :
00863         /* Update the error code */
00864         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00865
00866         /* Return error status */
00867         status =  HAL_ERROR;
00868         break;
00869     }
00870   }
00871   else if (hhcd->State == HAL_HCD_STATE_RESET)
00872   {
00873     switch (CallbackID)
00874     {
00875       case HAL_HCD_MSPINIT_CB_ID :
00876         hhcd->MspInitCallback = HAL_HCD_MspInit;
00877         break;
00878
00879       case HAL_HCD_MSPDEINIT_CB_ID :
00880         hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
00881         break;
00882
00883       default :
00884         /* Update the error code */
00885         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00886
00887         /* Return error status */
00888         status =  HAL_ERROR;
00889         break;
00890     }
00891   }
00892   else
00893   {
00894     /* Update the error code */
00895     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00896
00897     /* Return error status */
00898     status =  HAL_ERROR;
00899   }
00900
00901   /* Release Lock */
00902   __HAL_UNLOCK(hhcd);
00903   return status;
00904 }
00905
00906 /**
00907   * @brief  Register USB HCD Host Channel Notify URB Change Callback
00908   *         To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
00909   * @param  hhcd HCD handle
00910   * @param  pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
00914 {
00915   HAL_StatusTypeDef status = HAL_OK;
00916
00917   if (pCallback == NULL)
00918   {
00919     /* Update the error code */
00920     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00921
00922     return HAL_ERROR;
00923   }
00924
00925   /* Process locked */
00926   __HAL_LOCK(hhcd);
00927
00928   if (hhcd->State == HAL_HCD_STATE_READY)
00929   {
00930     hhcd->HC_NotifyURBChangeCallback = pCallback;
00931   }
00932   else
00933   {
00934     /* Update the error code */
00935     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00936
00937     /* Return error status */
00938     status =  HAL_ERROR;
00939   }
00940
00941   /* Release Lock */
00942   __HAL_UNLOCK(hhcd);
00943
00944   return status;
00945 }
00946
00947 /**
00948   * @brief  UnRegister the USB HCD Host Channel Notify URB Change Callback
00949   *         USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
00950   * @param  hhcd HCD handle
00951   * @retval HAL status
00952   */
00953 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
00954 {
00955   HAL_StatusTypeDef status = HAL_OK;
00956
00957   /* Process locked */
00958   __HAL_LOCK(hhcd);
00959
00960   if (hhcd->State == HAL_HCD_STATE_READY)
00961   {
00962     hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback  */
00963   }
00964   else
00965   {
00966     /* Update the error code */
00967     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
00968
00969     /* Return error status */
00970     status =  HAL_ERROR;
00971   }
00972
00973   /* Release Lock */
00974   __HAL_UNLOCK(hhcd);
00975
00976   return status;
00977 }
00978 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00979
00980 /**
00981   * @}
00982   */
00983
00984 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00985  *  @brief   Management functions
00986  *
00987 @verbatim
00988  ===============================================================================
00989                       ##### Peripheral Control functions #####
00990  ===============================================================================
00991     [..]
00992     This subsection provides a set of functions allowing to control the HCD data
00993     transfers.
00994
00995 @endverbatim
00996   * @{
00997   */
00998
00999 /**
01000   * @brief  Start the host driver.
01001   * @param  hhcd HCD handle
01002   * @retval HAL status
01003   */
01004 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
01005 {
01006   __HAL_LOCK(hhcd);
01007   __HAL_HCD_ENABLE(hhcd);
01008   (void)USB_DriveVbus(hhcd->Instance, 1U);
01009   __HAL_UNLOCK(hhcd);
01010
01011   return HAL_OK;
01012 }
01013
01014 /**
01015   * @brief  Stop the host driver.
01016   * @param  hhcd HCD handle
01017   * @retval HAL status
01018   */
01019
01020 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
01021 {
01022   __HAL_LOCK(hhcd);
01023   (void)USB_StopHost(hhcd->Instance);
01024   __HAL_UNLOCK(hhcd);
01025
01026   return HAL_OK;
01027 }
01028
01029 /**
01030   * @brief  Reset the host port.
01031   * @param  hhcd HCD handle
01032   * @retval HAL status
01033   */
01034 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
01035 {
01036   return (USB_ResetPort(hhcd->Instance));
01037 }
01038
01039 /**
01040   * @}
01041   */
01042
01043 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
01044  *  @brief   Peripheral State functions
01045  *
01046 @verbatim
01047  ===============================================================================
01048                       ##### Peripheral State functions #####
01049  ===============================================================================
01050     [..]
01051     This subsection permits to get in run-time the status of the peripheral
01052     and the data flow.
01053
01054 @endverbatim
01055   * @{
01056   */
01057
01058 /**
01059   * @brief  Return the HCD handle state.
01060   * @param  hhcd HCD handle
01061   * @retval HAL state
01062   */
01063 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
01064 {
01065   return hhcd->State;
01066 }
01067
01068 /**
01069   * @brief  Return  URB state for a channel.
01070   * @param  hhcd HCD handle
01071   * @param  chnum Channel number.
01072   *         This parameter can be a value from 1 to 15
01073   * @retval URB state.
01074   *          This parameter can be one of these values:
01075   *            URB_IDLE/
01076   *            URB_DONE/
01077   *            URB_NOTREADY/
01078   *            URB_NYET/
01079   *            URB_ERROR/
01080   *            URB_STALL
01081   */
01082 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01083 {
01084   return hhcd->hc[chnum].urb_state;
01085 }
01086
01087
01088 /**
01089   * @brief  Return the last host transfer size.
01090   * @param  hhcd HCD handle
01091   * @param  chnum Channel number.
01092   *         This parameter can be a value from 1 to 15
01093   * @retval last transfer size in byte
01094   */
01095 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01096 {
01097   return hhcd->hc[chnum].xfer_count;
01098 }
01099
01100 /**
01101   * @brief  Return the Host Channel state.
01102   * @param  hhcd HCD handle
01103   * @param  chnum Channel number.
01104   *         This parameter can be a value from 1 to 15
01105   * @retval Host channel state
01106   *          This parameter can be one of these values:
01107   *            HC_IDLE/
01108   *            HC_XFRC/
01109   *            HC_HALTED/
01110   *            HC_NYET/
01111   *            HC_NAK/
01112   *            HC_STALL/
01113   *            HC_XACTERR/
01114   *            HC_BBLERR/
01115   *            HC_DATATGLERR
01116   */
01117 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01118 {
01119   return hhcd->hc[chnum].state;
01120 }
01121
01122 /**
01123   * @brief  Return the current Host frame number.
01124   * @param  hhcd HCD handle
01125   * @retval Current Host frame number
01126   */
01127 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
01128 {
01129   return (USB_GetCurrentFrame(hhcd->Instance));
01130 }
01131
01132 /**
01133   * @brief  Return the Host enumeration speed.
01134   * @param  hhcd HCD handle
01135   * @retval Enumeration speed
01136   */
01137 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
01138 {
01139   return (USB_GetHostSpeed(hhcd->Instance));
01140 }
01141
01142 /**
01143   * @}
01144   */
01145
01146 /**
01147   * @}
01148   */
01149
01150 /** @addtogroup HCD_Private_Functions
01151   * @{
01152   */
01153 /**
01154   * @brief  Handle Host Channel IN interrupt requests.
01155   * @param  hhcd HCD handle
01156   * @param  chnum Channel number.
01157   *         This parameter can be a value from 1 to 15
01158   * @retval none
01159   */
01160 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01161 {
01162   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01163   uint32_t USBx_BASE = (uint32_t)USBx;
01164   uint32_t ch_num = (uint32_t)chnum;
01165
01166   uint32_t tmpreg;
01167
01168   if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
01169   {
01170     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
01171     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01172   }
01173   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
01174   {
01175     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
01176   }
01177   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
01178   {
01179     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01180     hhcd->hc[ch_num].state = HC_STALL;
01181     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01182     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
01183     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01184   }
01185   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
01186   {
01187     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01188     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01189     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01190     hhcd->hc[ch_num].state = HC_DATATGLERR;
01191     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
01192   }
01193   else
01194   {
01195     /* ... */
01196   }
01197
01198   if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
01199   {
01200     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01201     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01202     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
01203   }
01204   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
01205   {
01206     if (hhcd->Init.dma_enable != 0U)
01207     {
01208       hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
01209                                     (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
01210     }
01211
01212     hhcd->hc[ch_num].state = HC_XFRC;
01213     hhcd->hc[ch_num].ErrCnt = 0U;
01214     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
01215
01216     if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
01217         (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
01218     {
01219       __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01220       (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01221       __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01222     }
01223     else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
01224     {
01225       USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
01226       hhcd->hc[ch_num].urb_state = URB_DONE;
01227
01228 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01229       hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01230 #else
01231       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01232 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01233     }
01234     else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
01235     {
01236       hhcd->hc[ch_num].urb_state = URB_DONE;
01237
01238 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01239       hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01240 #else
01241       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01242 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01243     }
01244     else
01245     {
01246       /* ... */
01247     }
01248     hhcd->hc[ch_num].toggle_in ^= 1U;
01249
01250   }
01251   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
01252   {
01253     __HAL_HCD_MASK_HALT_HC_INT(ch_num);
01254
01255     if (hhcd->hc[ch_num].state == HC_XFRC)
01256     {
01257       hhcd->hc[ch_num].urb_state  = URB_DONE;
01258     }
01259     else if (hhcd->hc[ch_num].state == HC_STALL)
01260     {
01261       hhcd->hc[ch_num].urb_state  = URB_STALL;
01262     }
01263     else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
01264              (hhcd->hc[ch_num].state == HC_DATATGLERR))
01265     {
01266       hhcd->hc[ch_num].ErrCnt++;
01267       if (hhcd->hc[ch_num].ErrCnt > 3U)
01268       {
01269         hhcd->hc[ch_num].ErrCnt = 0U;
01270         hhcd->hc[ch_num].urb_state = URB_ERROR;
01271       }
01272       else
01273       {
01274         hhcd->hc[ch_num].urb_state = URB_NOTREADY;
01275       }
01276
01277       /* re-activate the channel  */
01278       tmpreg = USBx_HC(ch_num)->HCCHAR;
01279       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01280       tmpreg |= USB_OTG_HCCHAR_CHENA;
01281       USBx_HC(ch_num)->HCCHAR = tmpreg;
01282     }
01283     else if (hhcd->hc[ch_num].state == HC_NAK)
01284     {
01285       hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
01286       /* re-activate the channel  */
01287       tmpreg = USBx_HC(ch_num)->HCCHAR;
01288       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01289       tmpreg |= USB_OTG_HCCHAR_CHENA;
01290       USBx_HC(ch_num)->HCCHAR = tmpreg;
01291     }
01292     else
01293     {
01294       /* ... */
01295     }
01296     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
01297     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01298   }
01299   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
01300   {
01301     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01302     hhcd->hc[ch_num].ErrCnt++;
01303     hhcd->hc[ch_num].state = HC_XACTERR;
01304     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01305     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
01306   }
01307   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
01308   {
01309     if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
01310     {
01311       hhcd->hc[ch_num].ErrCnt = 0U;
01312       __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01313       (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01314     }
01315     else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
01316              (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
01317     {
01318       hhcd->hc[ch_num].ErrCnt = 0U;
01319
01320       if (hhcd->Init.dma_enable == 0U)
01321       {
01322         hhcd->hc[ch_num].state = HC_NAK;
01323         __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01324         (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01325       }
01326     }
01327     else
01328     {
01329       /* ... */
01330     }
01331     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01332   }
01333   else
01334   {
01335     /* ... */
01336   }
01337 }
01338
01339 /**
01340   * @brief  Handle Host Channel OUT interrupt requests.
01341   * @param  hhcd HCD handle
01342   * @param  chnum Channel number.
01343   *         This parameter can be a value from 1 to 15
01344   * @retval none
01345   */
01346 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01347 {
01348   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01349   uint32_t USBx_BASE = (uint32_t)USBx;
01350   uint32_t ch_num = (uint32_t)chnum;
01351   uint32_t tmpreg;
01352
01353   if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
01354   {
01355     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
01356     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01357   }
01358   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
01359   {
01360     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
01361
01362     if (hhcd->hc[ch_num].do_ping == 1U)
01363     {
01364       hhcd->hc[ch_num].do_ping = 0U;
01365       hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
01366       __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01367       (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01368     }
01369   }
01370   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
01371   {
01372     hhcd->hc[ch_num].state = HC_NYET;
01373     hhcd->hc[ch_num].do_ping = 1U;
01374     hhcd->hc[ch_num].ErrCnt = 0U;
01375     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01376     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01377     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
01378   }
01379   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
01380   {
01381     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01382     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01383     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
01384   }
01385   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
01386   {
01387     hhcd->hc[ch_num].ErrCnt = 0U;
01388     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01389     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01390     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
01391     hhcd->hc[ch_num].state = HC_XFRC;
01392   }
01393   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
01394   {
01395     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
01396     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01397     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01398     hhcd->hc[ch_num].state = HC_STALL;
01399   }
01400   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
01401   {
01402     hhcd->hc[ch_num].ErrCnt = 0U;
01403     hhcd->hc[ch_num].state = HC_NAK;
01404
01405     if (hhcd->hc[ch_num].do_ping == 0U)
01406     {
01407       if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
01408       {
01409         hhcd->hc[ch_num].do_ping = 1U;
01410       }
01411     }
01412
01413     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01414     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01415     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01416   }
01417   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
01418   {
01419     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01420     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01421     hhcd->hc[ch_num].state = HC_XACTERR;
01422     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
01423   }
01424   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
01425   {
01426     __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
01427     (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
01428     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
01429     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
01430     hhcd->hc[ch_num].state = HC_DATATGLERR;
01431   }
01432   else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
01433   {
01434     __HAL_HCD_MASK_HALT_HC_INT(ch_num);
01435
01436     if (hhcd->hc[ch_num].state == HC_XFRC)
01437     {
01438       hhcd->hc[ch_num].urb_state  = URB_DONE;
01439       if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
01440           (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
01441       {
01442         hhcd->hc[ch_num].toggle_out ^= 1U;
01443       }
01444     }
01445     else if (hhcd->hc[ch_num].state == HC_NAK)
01446     {
01447       hhcd->hc[ch_num].urb_state = URB_NOTREADY;
01448     }
01449     else if (hhcd->hc[ch_num].state == HC_NYET)
01450     {
01451       hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
01452     }
01453     else if (hhcd->hc[ch_num].state == HC_STALL)
01454     {
01455       hhcd->hc[ch_num].urb_state  = URB_STALL;
01456     }
01457     else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
01458              (hhcd->hc[ch_num].state == HC_DATATGLERR))
01459     {
01460       hhcd->hc[ch_num].ErrCnt++;
01461       if (hhcd->hc[ch_num].ErrCnt > 3U)
01462       {
01463         hhcd->hc[ch_num].ErrCnt = 0U;
01464         hhcd->hc[ch_num].urb_state = URB_ERROR;
01465       }
01466       else
01467       {
01468         hhcd->hc[ch_num].urb_state = URB_NOTREADY;
01469       }
01470
01471       /* re-activate the channel  */
01472       tmpreg = USBx_HC(ch_num)->HCCHAR;
01473       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01474       tmpreg |= USB_OTG_HCCHAR_CHENA;
01475       USBx_HC(ch_num)->HCCHAR = tmpreg;
01476     }
01477     else
01478     {
01479       /* ... */
01480     }
01481
01482     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
01483     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
01484   }
01485   else
01486   {
01487     /* ... */
01488   }
01489 }
01490
01491 /**
01492   * @brief  Handle Rx Queue Level interrupt requests.
01493   * @param  hhcd HCD handle
01494   * @retval none
01495   */
01496 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
01497 {
01498   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01499   uint32_t USBx_BASE = (uint32_t)USBx;
01500   uint32_t pktsts;
01501   uint32_t pktcnt;
01502   uint32_t temp;
01503   uint32_t tmpreg;
01504   uint32_t ch_num;
01505
01506   temp = hhcd->Instance->GRXSTSP;
01507   ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
01508   pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
01509   pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
01510
01511   switch (pktsts)
01512   {
01513     case GRXSTS_PKTSTS_IN:
01514       /* Read the data into the host buffer. */
01515       if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
01516       {
01517         (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
01518
01519         /*manage multiple Xfer */
01520         hhcd->hc[ch_num].xfer_buff += pktcnt;
01521         hhcd->hc[ch_num].xfer_count  += pktcnt;
01522
01523         if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
01524         {
01525           /* re-activate the channel when more packets are expected */
01526           tmpreg = USBx_HC(ch_num)->HCCHAR;
01527           tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01528           tmpreg |= USB_OTG_HCCHAR_CHENA;
01529           USBx_HC(ch_num)->HCCHAR = tmpreg;
01530           hhcd->hc[ch_num].toggle_in ^= 1U;
01531         }
01532       }
01533       break;
01534
01535     case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01536       break;
01537
01538     case GRXSTS_PKTSTS_IN_XFER_COMP:
01539     case GRXSTS_PKTSTS_CH_HALTED:
01540     default:
01541       break;
01542   }
01543 }
01544
01545 /**
01546   * @brief  Handle Host Port interrupt requests.
01547   * @param  hhcd HCD handle
01548   * @retval None
01549   */
01550 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
01551 {
01552   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01553   uint32_t USBx_BASE = (uint32_t)USBx;
01554   __IO uint32_t hprt0, hprt0_dup;
01555
01556   /* Handle Host Port Interrupts */
01557   hprt0 = USBx_HPRT0;
01558   hprt0_dup = USBx_HPRT0;
01559
01560   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
01561                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
01562
01563   /* Check whether Port Connect detected */
01564   if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01565   {
01566     if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01567     {
01568 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01569       hhcd->ConnectCallback(hhcd);
01570 #else
01571       HAL_HCD_Connect_Callback(hhcd);
01572 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01573     }
01574     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01575   }
01576
01577   /* Check whether Port Enable Changed */
01578   if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01579   {
01580     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01581
01582     if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01583     {
01584       if (hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
01585       {
01586         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
01587         {
01588           (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
01589         }
01590         else
01591         {
01592           (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
01593         }
01594       }
01595       else
01596       {
01597         if (hhcd->Init.speed == HCD_SPEED_FULL)
01598         {
01599           USBx_HOST->HFIR = 60000U;
01600         }
01601       }
01602 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01603       hhcd->PortEnabledCallback(hhcd);
01604 #else
01605       HAL_HCD_PortEnabled_Callback(hhcd);
01606 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01607
01608     }
01609     else
01610     {
01611 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01612       hhcd->PortDisabledCallback(hhcd);
01613 #else
01614       HAL_HCD_PortDisabled_Callback(hhcd);
01615 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01616     }
01617   }
01618
01619   /* Check for an overcurrent */
01620   if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01621   {
01622     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01623   }
01624
01625   /* Clear Port Interrupts */
01626   USBx_HPRT0 = hprt0_dup;
01627 }
01628
01629 /**
01630   * @}
01631   */
01632
01633 /**
01634   * @}
01635   */
01636
01637 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
01638 #endif /* HAL_HCD_MODULE_ENABLED */
01639
01640 /**
01641   * @}
01642   */
01643
01644 /**
01645   * @}
01646   */
01647
01648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hcd.h Source File

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stm32h7xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_HCD_H
00022 #define STM32H7xx_HAL_HCD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_usb.h"
00030
00031 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup HCD
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup HCD_Exported_Types HCD Exported Types
00042   * @{
00043   */
00044
00045 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00046   * @{
00047   */
00048 typedef enum
00049 {
00050   HAL_HCD_STATE_RESET    = 0x00,
00051   HAL_HCD_STATE_READY    = 0x01,
00052   HAL_HCD_STATE_ERROR    = 0x02,
00053   HAL_HCD_STATE_BUSY     = 0x03,
00054   HAL_HCD_STATE_TIMEOUT  = 0x04
00055 } HCD_StateTypeDef;
00056
00057 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00058 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00059 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
00060 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
00061 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00067   * @{
00068   */
00069 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00070 typedef struct __HCD_HandleTypeDef
00071 #else
00072 typedef struct
00073 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00074 {
00075   HCD_TypeDef               *Instance;  /*!< Register base address    */
00076   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00077   HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
00078   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00079   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00080   __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
00081   void                      *pData;     /*!< Pointer Stack Handler    */
00082 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00083   void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
00084   void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
00085   void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
00086   void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
00087   void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
00088   void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
00089                                       HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
00090
00091   void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
00092   void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
00093 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00094 } HCD_HandleTypeDef;
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported constants --------------------------------------------------------*/
00104 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00105   * @{
00106   */
00107
00108 /** @defgroup HCD_Speed HCD Speed
00109   * @{
00110   */
00111 #define HCD_SPEED_HIGH               USBH_HS_SPEED
00112 #define HCD_SPEED_FULL               USBH_FS_SPEED
00113 #define HCD_SPEED_LOW                USBH_LS_SPEED
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup HCD_PHY_Module HCD PHY Module
00120   * @{
00121   */
00122 #define HCD_PHY_ULPI                 1U
00123 #define HCD_PHY_EMBEDDED             2U
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup HCD_Error_Code_definition HCD Error Code definition
00129   * @brief  HCD Error Code definition
00130   * @{
00131   */
00132 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00133 #define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00134 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Exported macro ------------------------------------------------------------*/
00145 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00146  *  @brief macros to handle interrupts and specific clock configurations
00147  * @{
00148  */
00149 #define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00150 #define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00151
00152 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00153 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00154 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00155
00156 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00157 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00158 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00159 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00160 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported functions --------------------------------------------------------*/
00166 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00167   * @{
00168   */
00169
00170 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00171   * @{
00172   */
00173 HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00174 HAL_StatusTypeDef      HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
00175 HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00176                                        uint8_t ch_num,
00177                                        uint8_t epnum,
00178                                        uint8_t dev_address,
00179                                        uint8_t speed,
00180                                        uint8_t ep_type,
00181                                        uint16_t mps);
00182
00183 HAL_StatusTypeDef     HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00184 void                  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00185 void                  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00186
00187 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00188 /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
00189   * @brief  HAL USB OTG HCD Callback ID enumeration definition
00190   * @{
00191   */
00192 typedef enum
00193 {
00194   HAL_HCD_SOF_CB_ID           = 0x01,       /*!< USB HCD SOF callback ID           */
00195   HAL_HCD_CONNECT_CB_ID       = 0x02,       /*!< USB HCD Connect callback ID       */
00196   HAL_HCD_DISCONNECT_CB_ID   = 0x03,       /*!< USB HCD Disconnect callback ID    */
00197   HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,      /*!< USB HCD Port Enable callback ID   */
00198   HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,      /*!< USB HCD Port Disable callback ID  */
00199
00200   HAL_HCD_MSPINIT_CB_ID       = 0x06,       /*!< USB HCD MspInit callback ID       */
00201   HAL_HCD_MSPDEINIT_CB_ID     = 0x07        /*!< USB HCD MspDeInit callback ID     */
00202
00203 } HAL_HCD_CallbackIDTypeDef;
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
00209   * @brief  HAL USB OTG HCD Callback pointer definition
00210   * @{
00211   */
00212
00213 typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
00214 typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
00215                                                        uint8_t epnum,
00216                                                        HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
00217 /**
00218   * @}
00219   */
00220
00221 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
00222 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
00223
00224 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
00225 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
00226 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00227 /**
00228   * @}
00229   */
00230
00231 /* I/O operation functions  ***************************************************/
00232 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
00233   * @{
00234   */
00235 HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00236                                                  uint8_t ch_num,
00237                                                  uint8_t direction,
00238                                                  uint8_t ep_type,
00239                                                  uint8_t token,
00240                                                  uint8_t *pbuff,
00241                                                  uint16_t length,
00242                                                  uint8_t do_ping);
00243
00244 /* Non-Blocking mode: Interrupt */
00245 void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00246 void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00247 void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00248 void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00249 void             HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
00250 void             HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
00251 void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00252                                                      uint8_t chnum,
00253                                                      HCD_URBStateTypeDef urb_state);
00254 /**
00255   * @}
00256   */
00257
00258 /* Peripheral Control functions  **********************************************/
00259 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00260   * @{
00261   */
00262 HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00263 HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00264 HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00265 /**
00266   * @}
00267   */
00268
00269 /* Peripheral State functions  ************************************************/
00270 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00271   * @{
00272   */
00273 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00274 HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00275 uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00276 HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00277 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00278 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Private macros ------------------------------------------------------------*/
00288 /** @defgroup HCD_Private_Macros HCD Private Macros
00289  * @{
00290  */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Private functions prototypes ----------------------------------------------*/
00297 /** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
00298   * @{
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 /* Private functions ---------------------------------------------------------*/
00306 /** @defgroup HCD_Private_Functions HCD Private Functions
00307   * @{
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00322
00323 #ifdef __cplusplus
00324 }
00325 #endif
00326
00327 #endif /* STM32H7xx_HAL_HCD_H */
00328
00329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hrtim.c Source File

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stm32h7xx_hal_hrtim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Resolution Timer (HRTIM) peripheral:
00008   *           + HRTIM Initialization
00009   *           + Timer Time Base Unit Configuration
00010   *           + Simple Time Base Start/Stop
00011   *           + Simple Time Base Start/Stop Interrupt
00012   *           + Simple Time Base Start/Stop DMA Request
00013   *           + Simple Output Compare/PWM Channel Configuration
00014   *           + Simple Output Compare/PWM Channel Start/Stop Interrupt
00015   *           + Simple Output Compare/PWM Channel Start/Stop DMA Request
00016   *           + Simple Input Capture Channel Configuration
00017   *           + Simple Input Capture Channel Start/Stop Interrupt
00018   *           + Simple Input Capture Channel Start/Stop DMA Request
00019   *           + Simple One Pulse Channel Configuration
00020   *           + Simple One Pulse Channel Start/Stop Interrupt
00021   *           + HRTIM External Synchronization Configuration
00022   *           + HRTIM Burst Mode Controller Configuration
00023   *           + HRTIM Burst Mode Controller Enabling
00024   *           + HRTIM External Events Conditioning Configuration
00025   *           + HRTIM Faults Conditioning Configuration
00026   *           + HRTIM Faults Enabling
00027   *           + HRTIM ADC trigger Configuration
00028   *           + Waveform Timer Configuration
00029   *           + Waveform Event Filtering Configuration
00030   *           + Waveform Dead Time Insertion Configuration
00031   *           + Waveform Chopper Mode Configuration
00032   *           + Waveform Compare Unit Configuration
00033   *           + Waveform Capture Unit Configuration
00034   *           + Waveform Output Configuration
00035   *           + Waveform Counter Start/Stop
00036   *           + Waveform Counter Start/Stop Interrupt
00037   *           + Waveform Counter Start/Stop DMA Request
00038   *           + Waveform Output Enabling
00039   *           + Waveform Output Level Set/Get
00040   *           + Waveform Output State Get
00041   *           + Waveform Burst DMA Operation Configuration
00042   *           + Waveform Burst DMA Operation Start
00043   *           + Waveform Timer Counter Software Reset
00044   *           + Waveform Capture Software Trigger
00045   *           + Waveform Burst Mode Controller Software Trigger
00046   *           + Waveform Timer Pre-loadable Registers Update Enabling
00047   *           + Waveform Timer Pre-loadable Registers Software Update
00048   *           + Waveform Timer Delayed Protection Status Get
00049   *           + Waveform Timer Burst Status Get
00050   *           + Waveform Timer Push-Pull Status Get
00051   *           + Peripheral State Get
00052   @verbatim
00053 ==============================================================================
00054                       ##### Simple mode v.s. waveform mode #####
00055 ==============================================================================
00056   [..] The HRTIM HAL API is split into 2 categories:
00057     (#)Simple functions: these functions allow for using a HRTIM timer as a
00058        general purpose timer with high resolution capabilities.
00059        HRTIM simple modes are managed through the set of functions named
00060        HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
00061        to the one defined for the TIM peripheral. When a HRTIM timer operates in
00062        simple mode, only a very limited set of HRTIM features are used.
00063        Following simple modes are proposed:
00064          (++)Output compare mode,
00065          (++)PWM output mode,
00066          (++)Input capture mode,
00067          (++)One pulse mode.
00068     (#)Waveform functions: These functions allow taking advantage of the HRTIM
00069        flexibility to produce numerous types of control signal. When a HRTIM timer
00070        operates in waveform mode, all the HRTIM features are accessible without
00071        any restriction. HRTIM waveform modes are managed through the set of
00072        functions named HAL_HRTIM_Waveform<Function>
00073                       ##### How to use this driver #####
00074 ==============================================================================
00075     [..]
00076      (#)Initialize the HRTIM low level resources by implementing the
00077         HAL_HRTIM_MspInit() function:
00078         (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
00079         (##)Connect HRTIM pins to MCU I/Os
00080             (+++) Enable the clock for the HRTIM GPIOs using the following
00081                   function: __HAL_RCC_GPIOx_CLK_ENABLE()
00082             (+++) Configure these GPIO pins in Alternate Function mode using
00083                   HAL_GPIO_Init()
00084         (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
00085             (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00086             (+++)Initialize the DMA handle
00087             (+++)Associate the initialized DMA handle to the appropriate DMA
00088                  handle of the HRTIM handle using __HAL_LINKDMA()
00089             (+++)Initialize the DMA channel using HAL_DMA_Init()
00090             (+++)Configure the priority and enable the NVIC for the transfer
00091                  complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
00092                  and HAL_NVIC_EnableIRQ()
00093         (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
00094             (+++)Configure the priority and enable the NVIC for the concerned
00095                  HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00096
00097     (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
00098        structure (field of the HRTIM handle) specifies which global interrupt of
00099        whole HRTIM must be enabled (Burst mode period, System fault, Faults).
00100        It also contains the HRTIM external synchronization configuration. HRTIM
00101        can act as a master (generating a synchronization signal) or as a slave
00102        (waiting for a trigger to be synchronized).
00103
00104      (#) Configure HRTIM resources shared by all HRTIM timers
00105         (##)Burst Mode Controller:
00106                 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
00107                      controller: operating mode (continuous or one-shot mode), clock
00108                      (source, prescaler) , trigger(s), period, idle duration.
00109         (##)External Events Conditioning:
00110                 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
00111                      external event channel: source, polarity, edge-sensitivity.
00112                      External event can be used as triggers (timer reset, input
00113                      capture, burst mode, ADC triggers, delayed protection)
00114                      They can also be used to set or reset timer outputs. Up to
00115                      10 event channels are available.
00116                 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
00117                      event sampling clock (used for digital filtering).
00118         (##)Fault Conditioning:
00119                 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
00120                      fault channel: source, polarity, edge-sensitivity. Fault
00121                      channels are used to disable the outputs in case of an
00122                      abnormal operation. Up to 5 fault channels are available.
00123                 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
00124                      sampling clock (used for digital filtering).
00125                 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
00126                      circuitry. By default all fault inputs are disabled.
00127         (##)ADC trigger:
00128                 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
00129                      the update of the ADC trigger register and the ADC trigger.
00130                      4 independent triggers are available to start both the regular
00131                      and the injected sequencers of the 2 ADCs
00132
00133      (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
00134          function must be called whatever the HRTIM timer operating mode is
00135          (simple v.s. waveform). It configures mainly:
00136         (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
00137         (##)The HRTIM  timer clock prescaler
00138         (##)The HRTIM  timer period
00139         (##)The HRTIM  timer repetition counter
00140
00141      *** If the HRTIM timer operates in simple mode ***
00142      ===================================================
00143      [..]
00144      (#) Start or Stop simple timers
00145               (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
00146                   HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
00147                   HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
00148               (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
00149                   HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
00150                   HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
00151                   HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
00152               (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
00153                   HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
00154                   HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
00155                   HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
00156               (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
00157                   HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
00158                   HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
00159                   HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
00160               (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
00161                   HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
00162                   HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
00163
00164      *** If the HRTIM timer operates in waveform mode ***
00165      ====================================================
00166      [..]
00167      (#) Completes waveform timer configuration
00168               (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
00169                   operating in wave form mode mainly consists in:
00170                 (+++)Enabling the HRTIM timer interrupts and DMA requests.
00171                 (+++)Enabling the half mode for the HRTIM timer.
00172                 (+++)Defining how the HRTIM timer reacts to external synchronization input.
00173                 (+++)Enabling the push-pull mode for the HRTIM timer.
00174                 (+++)Enabling the fault channels for the HRTIM timer.
00175                 (+++)Enabling the dead-time insertion for the HRTIM timer.
00176                 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
00177                      on which the delayed protection are applied).
00178                 (+++)Specifying the HRTIM timer update and reset triggers.
00179                 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
00180               (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
00181                   event blanking and windowing circuitry of a HRTIM timer:
00182                 (+++)Blanking:  to mask external events during a defined  time period a defined time period
00183                 (+++)Windowing, to enable external events only during a defined time period
00184               (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
00185                   unit for a HRTIM timer. Allows to generate a couple of
00186                   complementary signals from a single reference waveform,
00187                   with programmable delays between active state.
00188               (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
00189                   the high-frequency carrier signal added on top of the timing
00190                   unit output. Chopper mode can be enabled or disabled for each
00191                    timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
00192               (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
00193                   controller. Allows having multiple HRTIM registers updated
00194                   with a single DMA request. The burst DMA operation is started
00195                   by calling HAL_HRTIM_BurstDMATransfer().
00196               (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
00197                   of a HRTIM timer. This operation consists in setting the
00198                   compare value and possibly specifying the auto delayed mode
00199                   for compare units 2 and 4 (allows to have compare events
00200                   generated relatively to capture events). Note that when auto
00201                   delayed mode is needed, the capture unit associated to the
00202                   compare unit must be configured separately.
00203               (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
00204                   of a HRTIM timer. This operation consists in specifying the
00205                   source(s)  triggering the capture (timer register update event,
00206                   external event, timer output set/reset event, other HRTIM
00207                   timer related events).
00208               (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
00209                   output mainly consists in:
00210                 (+++)Setting the output polarity (active high or active low),
00211                 (+++)Defining the set/reset crossbar for the output,
00212                 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
00213
00214      (#) Set waveform timer output(s) level
00215               (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
00216                   active or inactive level. For example, when deadtime insertion
00217                   is enabled it is necessary to force the output level by software
00218                   to have the outputs in a complementary state as soon as the RUN mode is entered.
00219
00220      (#) Enable or Disable waveform timer output(s)
00221               (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
00222
00223      (#) Start or Stop waveform HRTIM timer(s).
00224               (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
00225               (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
00226               (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
00227      (#) Burst mode controller enabling:
00228               (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
00229                   burst mode controller.
00230
00231      (#) Some HRTIM operations can be triggered by software:
00232               (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
00233                   trigs the burst operation.
00234               (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
00235                   capture of the HRTIM timer counter.
00236               (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
00237                   update of the pre-loadable registers of the HRTIM timer
00238               (++)HAL_HRTIM_SoftwareReset():calling this function resets the
00239                   HRTIM timer counter.
00240
00241      (#) Some functions can be used any time to retrieve HRTIM timer related
00242             information
00243               (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
00244                   capture register of the designated capture unit.
00245               (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
00246                  (ACTIVE/INACTIVE) of the designated timer output.
00247               (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
00248                  (IDLE/RUN/FAULT) of the designated timer output.
00249               (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
00250                  (ACTIVE/INACTIVE) of the designated output when the delayed
00251                   protection was triggered.
00252               (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
00253                  (ACTIVE/INACTIVE) of the burst mode controller.
00254               (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
00255                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00256                  the push-pull status indicates on which output the signal is currently
00257                  active (e.g signal applied on output 1 and output 2 forced
00258                  inactive or vice versa).
00259              (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
00260                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00261                  the idle push-pull status indicates during which period the
00262                  delayed protection request occurred (e.g. protection occurred
00263                  when the output 1 was active and output 2 forced inactive or
00264                  vice versa).
00265
00266      (#) Some functions can be used any time to retrieve actual HRTIM status
00267              (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
00268
00269      *** Callback registration ***
00270      =============================
00271      [..]
00272      The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
00273      allows the user to configure dynamically the driver callbacks.
00274      Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
00275      to register an interrupt callback.
00276
00277      [..]
00278      Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
00279        (+) Fault1Callback               : Fault 1 interrupt callback function
00280        (+) Fault2Callback               : Fault 2 interrupt callback function
00281        (+) Fault3Callback               : Fault 3 interrupt callback function
00282        (+) Fault4Callback               : Fault 4 interrupt callback function
00283        (+) Fault5Callback               : Fault 5 interrupt callback function
00284        (+) SystemFaultCallback          : System fault interrupt callback function
00285        (+) BurstModePeriodCallback      : Burst mode period interrupt callback function
00286        (+) SynchronizationEventCallback : Sync Input interrupt callback function
00287        (+) ErrorCallback                : DMA error callback function
00288        (+) MspInitCallback              : HRTIM MspInit callback function
00289        (+) MspDeInitCallback            : HRTIM MspInit callback function
00290
00291      [..]
00292      Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
00293        (+) RegistersUpdateCallback   : Timer x Update interrupt callback function
00294        (+) RepetitionEventCallback   : Timer x Repetition interrupt callback function
00295        (+) Compare1EventCallback     : Timer x Compare 1 match interrupt callback function
00296        (+) Compare2EventCallback     : Timer x Compare 2 match interrupt callback function
00297        (+) Compare3EventCallback     : Timer x Compare 3 match interrupt callback function
00298        (+) Compare4EventCallback     : Timer x Compare 4 match interrupt callback function
00299        (+) Capture1EventCallback     : Timer x Capture 1 interrupts callback function
00300        (+) Capture2EventCallback     : Timer x Capture 2 interrupts callback function
00301        (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
00302        (+) CounterResetCallback      : Timer x counter reset/roll-over interrupt callback function
00303        (+) Output1SetCallback        : Timer x output 1 set interrupt callback function
00304        (+) Output1ResetCallback      : Timer x output 1 reset interrupt callback function
00305        (+) Output2SetCallback        : Timer x output 2 set interrupt callback function
00306        (+) Output2ResetCallback      : Timer x output 2 reset interrupt callback function
00307        (+) BurstDMATransferCallback  : Timer x Burst DMA completed interrupt callback function
00308
00309      [..]
00310      Both functions take as parameters the HAL peripheral handle, the Callback ID
00311      and a pointer to the user callback function.
00312
00313      [..]
00314      Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
00315      to reset a callback to the default weak function. Both functions take  as parameters
00316      the HAL peripheral handle and the Callback ID.
00317
00318      [..]
00319      By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
00320      all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
00321      Exception done for MspInit and MspDeInit functions that are reset to the legacy
00322      weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
00323      callbacks are null (not registered beforehand). If MspInit or MspDeInit are
00324      not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
00325      MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00326
00327      [..]
00328      Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
00329      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00330      in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
00331      (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00332      Then, the user first registers the MspInit/MspDeInit user callbacks
00333      using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
00334      or HAL_HRTIM_Init() function.
00335
00336      [..]
00337      When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
00338      not defined, the callback registration feature is not available and all
00339      callbacks are set to the corresponding weak functions.
00340
00341   @endverbatim
00342
00343   ******************************************************************************
00344   * @attention
00345   *
00346   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00347   * All rights reserved.</center></h2>
00348   *
00349   * This software component is licensed by ST under BSD 3-Clause license,
00350   * the "License"; You may not use this file except in compliance with the
00351   * License. You may obtain a copy of the License at:
00352   *                        opensource.org/licenses/BSD-3-Clause
00353   *
00354   ******************************************************************************
00355   */
00356
00357 /* Includes ------------------------------------------------------------------*/
00358 #include "stm32h7xx_hal.h"
00359
00360 /** @addtogroup STM32H7xx_HAL_Driver
00361   * @{
00362   */
00363
00364 #ifdef HAL_HRTIM_MODULE_ENABLED
00365
00366 #if defined(HRTIM1)
00367
00368 /** @defgroup HRTIM HRTIM
00369   * @brief HRTIM HAL module driver
00370   * @{
00371   */
00372
00373 /* Private typedef -----------------------------------------------------------*/
00374 /* Private define ------------------------------------------------------------*/
00375 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
00376   * @{
00377   */
00378 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
00379                            HRTIM_FLTR_FLT2EN |\
00380                            HRTIM_FLTR_FLT3EN |\
00381                            HRTIM_FLTR_FLT4EN | \
00382                            HRTIM_FLTR_FLT5EN)
00383
00384 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER  |\
00385                                       HRTIM_TIMUPDATETRIGGER_TIMER_A |\
00386                                       HRTIM_TIMUPDATETRIGGER_TIMER_B |\
00387                                       HRTIM_TIMUPDATETRIGGER_TIMER_C |\
00388                                       HRTIM_TIMUPDATETRIGGER_TIMER_D |\
00389                                       HRTIM_TIMUPDATETRIGGER_TIMER_E)
00390
00391 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
00392                                (HRTIM_FAULTLOCK_READONLY << 8U)  | \
00393                                (HRTIM_FAULTLOCK_READONLY << 16U) | \
00394                                (HRTIM_FAULTLOCK_READONLY << 24U))
00395
00396 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
00397                                (HRTIM_FAULTLOCK_READONLY << 8U))
00398 /**
00399   * @}
00400   */
00401
00402 /* Private macro -------------------------------------------------------------*/
00403 /* Private variables ---------------------------------------------------------*/
00404 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
00405   * @{
00406   */
00407 static uint32_t TimerIdxToTimerId[] =
00408 {
00409   HRTIM_TIMERID_TIMER_A,
00410   HRTIM_TIMERID_TIMER_B,
00411   HRTIM_TIMERID_TIMER_C,
00412   HRTIM_TIMERID_TIMER_D,
00413   HRTIM_TIMERID_TIMER_E,
00414   HRTIM_TIMERID_MASTER,
00415 };
00416 /**
00417   * @}
00418   */
00419
00420 /* Private function prototypes -----------------------------------------------*/
00421 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
00422   * @{
00423   */
00424 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
00425                                     HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00426
00427 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
00428                                         uint32_t TimerIdx,
00429                                         HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00430
00431 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00432                                         HRTIM_TimerCfgTypeDef * pTimerCfg);
00433
00434 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00435                                             uint32_t TimerIdx,
00436                                             HRTIM_TimerCfgTypeDef * pTimerCfg);
00437
00438
00439 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00440                                     uint32_t TimerIdx,
00441                                     uint32_t CaptureUnit,
00442                                     uint32_t Event);
00443
00444 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
00445                                 uint32_t TimerIdx,
00446                                 uint32_t Output,
00447                                 HRTIM_OutputCfgTypeDef * pOutputCfg);
00448
00449 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
00450                               uint32_t Event,
00451                               HRTIM_EventCfgTypeDef * pEventCfg);
00452
00453 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
00454                                   uint32_t TimerIdx,
00455                                   uint32_t Event);
00456
00457 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00458                                       uint32_t TimerIdx,
00459                                       uint32_t OCChannel);
00460
00461 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00462                                        uint32_t TimerIdx,
00463                                        uint32_t OCChannel);
00464
00465 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
00466                                                           uint32_t TimerIdx);
00467
00468 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
00469                                          DMA_HandleTypeDef * hdma);
00470
00471 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
00472                                       uint32_t TimerIdx);
00473
00474 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
00475
00476 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
00477
00478 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
00479                                        uint32_t TimerIdx);
00480
00481 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
00482
00483 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
00484
00485 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
00486
00487 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
00488 /**
00489   * @}
00490   */
00491
00492 /* Exported functions ---------------------------------------------------------*/
00493 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
00494   * @{
00495   */
00496
00497 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
00498  *  @brief    Initialization and Configuration functions
00499 @verbatim
00500  ===============================================================================
00501               ##### Initialization and Time Base Configuration functions #####
00502  ===============================================================================
00503     [..]  This section provides functions allowing to:
00504       (+) Initialize a HRTIM instance
00505       (+) De-initialize a HRTIM instance
00506       (+) Initialize the HRTIM MSP
00507       (+) De-initialize the HRTIM MSP
00508       (+) Configure the time base unit of a HRTIM timer
00509
00510 @endverbatim
00511   * @{
00512   */
00513
00514 /**
00515   * @brief  Initialize a HRTIM instance
00516   * @param  hhrtim pointer to HAL HRTIM handle
00517   * @retval HAL status
00518   */
00519 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
00520 {
00521   uint8_t timer_idx;
00522   uint32_t hrtim_mcr;
00523
00524   /* Check the HRTIM handle allocation */
00525   if(hhrtim == NULL)
00526   {
00527     return HAL_ERROR;
00528   }
00529
00530   /* Check the parameters */
00531   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00532   assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
00533
00534 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00535   if (hhrtim->State == HAL_HRTIM_STATE_RESET)
00536   {
00537     /* Initialize callback function pointers to their default values */
00538     hhrtim->Fault1Callback               = HAL_HRTIM_Fault1Callback;
00539     hhrtim->Fault2Callback               = HAL_HRTIM_Fault2Callback;
00540     hhrtim->Fault3Callback               = HAL_HRTIM_Fault3Callback;
00541     hhrtim->Fault4Callback               = HAL_HRTIM_Fault4Callback;
00542     hhrtim->Fault5Callback               = HAL_HRTIM_Fault5Callback;
00543     hhrtim->SystemFaultCallback          = HAL_HRTIM_SystemFaultCallback;
00544     hhrtim->BurstModePeriodCallback      = HAL_HRTIM_BurstModePeriodCallback;
00545     hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
00546     hhrtim->ErrorCallback                = HAL_HRTIM_ErrorCallback;
00547     hhrtim->RegistersUpdateCallback      = HAL_HRTIM_RegistersUpdateCallback;
00548     hhrtim->RepetitionEventCallback      = HAL_HRTIM_RepetitionEventCallback;
00549     hhrtim->Compare1EventCallback        = HAL_HRTIM_Compare1EventCallback;
00550     hhrtim->Compare2EventCallback        = HAL_HRTIM_Compare2EventCallback;
00551     hhrtim->Compare3EventCallback        = HAL_HRTIM_Compare3EventCallback;
00552     hhrtim->Compare4EventCallback        = HAL_HRTIM_Compare4EventCallback;
00553     hhrtim->Capture1EventCallback        = HAL_HRTIM_Capture1EventCallback;
00554     hhrtim->Capture2EventCallback        = HAL_HRTIM_Capture2EventCallback;
00555     hhrtim->DelayedProtectionCallback    = HAL_HRTIM_DelayedProtectionCallback;
00556     hhrtim->CounterResetCallback         = HAL_HRTIM_CounterResetCallback;
00557     hhrtim->Output1SetCallback           = HAL_HRTIM_Output1SetCallback;
00558     hhrtim->Output1ResetCallback         = HAL_HRTIM_Output1ResetCallback;
00559     hhrtim->Output2SetCallback           = HAL_HRTIM_Output2SetCallback;
00560     hhrtim->Output2ResetCallback         = HAL_HRTIM_Output2ResetCallback;
00561     hhrtim->BurstDMATransferCallback     = HAL_HRTIM_BurstDMATransferCallback;
00562
00563     if (hhrtim->MspInitCallback == NULL)
00564     {
00565       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
00566     }
00567   }
00568 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00569
00570   /* Set the HRTIM state */
00571   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00572
00573   /* Initialize the DMA handles */
00574   hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
00575   hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
00576   hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
00577   hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
00578   hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
00579   hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
00580
00581   /* HRTIM output synchronization configuration (if required) */
00582   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
00583   {
00584     /* Check parameters */
00585     assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
00586     assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
00587
00588     /* The synchronization output initialization procedure must be done prior
00589        to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
00590     */
00591     if (hhrtim->Instance == HRTIM1)
00592     {
00593       /* Enable the HRTIM peripheral clock */
00594       __HAL_RCC_HRTIM1_CLK_ENABLE();
00595     }
00596
00597     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00598
00599     /* Set the event to be sent on the synchronization output */
00600     hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
00601     hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
00602
00603     /* Set the polarity of the synchronization output */
00604     hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
00605     hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
00606
00607     /* Update the HRTIM registers */
00608     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00609   }
00610
00611   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00612 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00613   hhrtim->MspInitCallback(hhrtim);
00614 #else
00615   HAL_HRTIM_MspInit(hhrtim);
00616 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00617
00618   /* HRTIM input synchronization configuration (if required) */
00619   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
00620   {
00621     /* Check parameters */
00622     assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
00623
00624     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00625
00626     /* Set the synchronization input source */
00627     hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
00628     hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
00629
00630     /* Update the HRTIM registers */
00631     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00632   }
00633
00634   /* Initialize the HRTIM state*/
00635   hhrtim->State = HAL_HRTIM_STATE_READY;
00636
00637   /* Initialize the lock status of the HRTIM HAL API */
00638   __HAL_UNLOCK(hhrtim);
00639
00640   /* Initialize timer related parameters */
00641   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
00642        timer_idx <= HRTIM_TIMERINDEX_MASTER ;
00643        timer_idx++)
00644   {
00645     hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
00646     hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
00647     hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
00648     hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
00649     hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
00650     hhrtim->TimerParam[timer_idx].DMASize = 0U;
00651   }
00652
00653   return HAL_OK;
00654 }
00655
00656 /**
00657   * @brief  De-initialize a HRTIM instance
00658   * @param  hhrtim pointer to HAL HRTIM handle
00659   * @retval HAL status
00660   */
00661 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
00662 {
00663   /* Check the HRTIM handle allocation */
00664   if(hhrtim == NULL)
00665   {
00666     return HAL_ERROR;
00667   }
00668
00669   /* Check the parameters */
00670   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00671
00672   /* Set the HRTIM state */
00673   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00674
00675   /* DeInit the low level hardware */
00676 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00677   if (hhrtim->MspDeInitCallback == NULL)
00678   {
00679     hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
00680   }
00681
00682   hhrtim->MspDeInitCallback(hhrtim);
00683 #else
00684   HAL_HRTIM_MspDeInit(hhrtim);
00685 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00686
00687   hhrtim->State = HAL_HRTIM_STATE_READY;
00688
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief  MSP initialization for a HRTIM instance
00694   * @param  hhrtim pointer to HAL HRTIM handle
00695   * @retval None
00696   */
00697 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
00698 {
00699   /* Prevent unused argument(s) compilation warning */
00700   UNUSED(hhrtim);
00701
00702   /* NOTE: This function should not be modified, when the callback is needed,
00703            the HAL_HRTIM_MspInit could be implemented in the user file
00704    */
00705 }
00706
00707 /**
00708   * @brief  MSP de-initialization of a HRTIM instance
00709   * @param  hhrtim pointer to HAL HRTIM handle
00710   * @retval None
00711   */
00712 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
00713 {
00714   /* Prevent unused argument(s) compilation warning */
00715   UNUSED(hhrtim);
00716
00717   /* NOTE: This function should not be modified, when the callback is needed,
00718            the HAL_HRTIM_MspDeInit could be implemented in the user file
00719    */
00720 }
00721
00722 /**
00723   * @brief  Configure the time base unit of a timer
00724   * @param  hhrtim pointer to HAL HRTIM handle
00725   * @param  TimerIdx Timer index
00726   *                   This parameter can be one of the following values:
00727   *                   @arg HRTIM_TIMERINDEX_MASTER for master timer
00728   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00729   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00730   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00731   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00732   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00733   * @param  pTimeBaseCfg pointer to the time base configuration structure
00734   * @note This function must be called prior starting the timer
00735   * @note   The time-base unit initialization parameters specify:
00736   *           The timer counter operating mode (continuous, one shot),
00737   *           The timer clock prescaler,
00738   *           The timer period,
00739   *           The timer repetition counter.
00740   * @retval HAL status
00741   */
00742 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
00743                                            uint32_t TimerIdx,
00744                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
00745 {
00746   /* Check the parameters */
00747   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00748   assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
00749   assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
00750
00751   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00752   {
00753      return HAL_BUSY;
00754   }
00755
00756   /* Set the HRTIM state */
00757   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00758
00759   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00760   {
00761     /* Configure master timer time base unit */
00762     HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
00763   }
00764   else
00765   {
00766     /* Configure timing unit time base unit */
00767     HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
00768   }
00769
00770   /* Set HRTIM state */
00771   hhrtim->State = HAL_HRTIM_STATE_READY;
00772
00773   return HAL_OK;
00774 }
00775
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
00781  *  @brief    Simple time base mode functions.
00782 @verbatim
00783  ===============================================================================
00784               ##### Simple time base mode functions #####
00785  ===============================================================================
00786     [..]  This section provides functions allowing to:
00787       (+) Start simple time base
00788       (+) Stop simple time base
00789       (+) Start simple time base and enable interrupt
00790       (+) Stop simple time base and disable interrupt
00791       (+) Start simple time base and enable DMA transfer
00792       (+) Stop simple time base and disable DMA transfer
00793       -@-  When a HRTIM timer operates in simple time base mode, the timer
00794            counter counts from 0 to the period value.
00795
00796 @endverbatim
00797   * @{
00798   */
00799
00800 /**
00801   * @brief  Start the counter of a timer operating in simple time base mode.
00802   * @param  hhrtim pointer to HAL HRTIM handle
00803   * @param  TimerIdx Timer index.
00804   *                   This parameter can be one of the following values:
00805   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00806   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00807   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00808   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00809   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00810   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00811   * @retval HAL status
00812   */
00813 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
00814                                            uint32_t TimerIdx)
00815 {
00816    /* Check the parameters */
00817   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00818
00819   /* Process Locked */
00820   __HAL_LOCK(hhrtim);
00821
00822   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00823
00824   /* Enable the timer counter */
00825   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00826
00827   hhrtim->State = HAL_HRTIM_STATE_READY;
00828
00829   /* Process Unlocked */
00830   __HAL_UNLOCK(hhrtim);
00831
00832   return HAL_OK;
00833 }
00834
00835 /**
00836   * @brief  Stop the counter of a timer operating in simple time base mode.
00837   * @param  hhrtim pointer to HAL HRTIM handle
00838   * @param  TimerIdx Timer index.
00839   *                   This parameter can be one of the following values:
00840   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00841   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00842   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00843   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00844   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00845   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00846   * @retval HAL status
00847   */
00848 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
00849                                           uint32_t TimerIdx)
00850 {
00851    /* Check the parameters */
00852   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00853
00854   /* Process Locked */
00855   __HAL_LOCK(hhrtim);
00856
00857   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00858
00859   /* Disable the timer counter */
00860   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00861
00862   hhrtim->State = HAL_HRTIM_STATE_READY;
00863
00864   /* Process Unlocked */
00865   __HAL_UNLOCK(hhrtim);
00866
00867   return HAL_OK;
00868 }
00869
00870 /**
00871   * @brief  Start the counter of a timer operating in simple time base mode
00872   *         (Timer repetition interrupt is enabled).
00873   * @param  hhrtim pointer to HAL HRTIM handle
00874   * @param  TimerIdx Timer index.
00875   *                   This parameter can be one of the following values:
00876   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00877   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00878   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00879   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00880   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00881   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00882   * @retval HAL status
00883   */
00884 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
00885                                               uint32_t TimerIdx)
00886 {
00887    /* Check the parameters */
00888   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00889
00890   /* Process Locked */
00891   __HAL_LOCK(hhrtim);
00892
00893   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00894
00895   /* Enable the repetition interrupt */
00896   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00897   {
00898     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00899   }
00900   else
00901   {
00902     __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
00903   }
00904
00905   /* Enable the timer counter */
00906   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00907
00908   hhrtim->State = HAL_HRTIM_STATE_READY;
00909
00910   /* Process Unlocked */
00911   __HAL_UNLOCK(hhrtim);
00912
00913   return HAL_OK;
00914 }
00915
00916 /**
00917   * @brief  Stop the counter of a timer operating in simple time base mode
00918   *         (Timer repetition interrupt is disabled).
00919   * @param  hhrtim pointer to HAL HRTIM handle
00920   * @param  TimerIdx Timer index.
00921   *                   This parameter can be one of the following values:
00922   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00923   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00924   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00925   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00926   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00927   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00928   * @retval HAL status
00929   */
00930 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
00931                                              uint32_t TimerIdx)
00932 {
00933    /* Check the parameters */
00934   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00935
00936   /* Process Locked */
00937   __HAL_LOCK(hhrtim);
00938
00939   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00940
00941   /* Disable the repetition interrupt */
00942   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00943   {
00944     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00945   }
00946   else
00947   {
00948     __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
00949   }
00950
00951   /* Disable the timer counter */
00952   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00953
00954   hhrtim->State = HAL_HRTIM_STATE_READY;
00955
00956   /* Process Unlocked */
00957   __HAL_UNLOCK(hhrtim);
00958
00959   return HAL_OK;
00960 }
00961
00962 /**
00963   * @brief  Start the counter of a timer operating in simple time base mode
00964   *         (Timer repetition DMA request is enabled).
00965   * @param  hhrtim pointer to HAL HRTIM handle
00966   * @param  TimerIdx Timer index.
00967   *                   This parameter can be one of the following values:
00968   *                    @arg HRTIM_TIMERINDEX_MASTER  for master timer
00969   *                    @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00970   *                    @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00971   *                    @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00972   *                    @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00973   *                    @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00974   * @param  SrcAddr DMA transfer source address
00975   * @param  DestAddr DMA transfer destination address
00976   * @param  Length The length of data items (data size) to be transferred
00977   *                     from source to destination
00978   */
00979 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
00980                                                uint32_t TimerIdx,
00981                                                uint32_t SrcAddr,
00982                                                uint32_t DestAddr,
00983                                                uint32_t Length)
00984 {
00985   DMA_HandleTypeDef * hdma;
00986
00987   /* Check the parameters */
00988   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00989
00990   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00991   {
00992      return HAL_BUSY;
00993   }
00994   if(hhrtim->State == HAL_HRTIM_STATE_READY)
00995   {
00996     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
00997     {
00998       return HAL_ERROR;
00999     }
01000     else
01001     {
01002       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01003     }
01004   }
01005
01006   /* Process Locked */
01007   __HAL_LOCK(hhrtim);
01008
01009   /* Get the timer DMA handler */
01010   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01011
01012   if (hdma == NULL)
01013   {
01014    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01015
01016    /* Process Unlocked */
01017    __HAL_UNLOCK(hhrtim);
01018
01019    return HAL_ERROR;
01020   }
01021
01022   /* Set the DMA transfer completed callback */
01023   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01024   {
01025     hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
01026   }
01027   else
01028   {
01029     hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01030   }
01031
01032   /* Set the DMA error callback */
01033   hdma->XferErrorCallback = HRTIM_DMAError ;
01034
01035   /* Enable the DMA channel */
01036   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
01037     {
01038         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01039
01040         /* Process Unlocked */
01041         __HAL_UNLOCK(hhrtim);
01042
01043         return HAL_ERROR;
01044     }
01045
01046   /* Enable the timer repetition DMA request */
01047   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01048   {
01049     __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01050   }
01051   else
01052   {
01053     __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01054   }
01055
01056   /* Enable the timer counter */
01057   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01058
01059   hhrtim->State = HAL_HRTIM_STATE_READY;
01060
01061   /* Process Unlocked */
01062   __HAL_UNLOCK(hhrtim);
01063
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @brief  Stop the counter of a timer operating in simple time base mode
01069   *         (Timer repetition DMA request is disabled).
01070   * @param  hhrtim pointer to HAL HRTIM handle
01071   * @param  TimerIdx Timer index.
01072   *                   This parameter can be one of the following values:
01073   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01074   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01075   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01076   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01077   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01078   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01079   * @retval HAL status
01080   */
01081 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01082                                               uint32_t TimerIdx)
01083 {
01084   DMA_HandleTypeDef * hdma;
01085
01086   /* Check the parameters */
01087   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01088
01089   /* Process Locked */
01090   __HAL_LOCK(hhrtim);
01091
01092   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01093   {
01094     hhrtim->State = HAL_HRTIM_STATE_READY;
01095
01096     /* Disable the DMA */
01097     if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
01098     {
01099         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01100     }
01101     /* Disable the timer repetition DMA request */
01102     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01103   }
01104   else
01105   {
01106     /* Get the timer DMA handler */
01107     hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01108
01109     if (hdma == NULL)
01110     {
01111       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01112     }
01113     else
01114     {
01115       hhrtim->State = HAL_HRTIM_STATE_READY;
01116
01117       /* Disable the DMA */
01118       if (HAL_DMA_Abort(hdma) != HAL_OK)
01119       {
01120          hhrtim->State = HAL_HRTIM_STATE_ERROR;
01121       }
01122
01123       /* Disable the timer repetition DMA request */
01124       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01125      }
01126   }
01127
01128   /* Disable the timer counter */
01129   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01130
01131   /* Process Unlocked */
01132   __HAL_UNLOCK(hhrtim);
01133
01134   if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
01135   {
01136       return HAL_ERROR;
01137   }
01138   else
01139   {
01140       return HAL_OK;
01141   }
01142 }
01143
01144 /**
01145   * @}
01146   */
01147
01148 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
01149  *  @brief    Simple output compare functions
01150 @verbatim
01151  ===============================================================================
01152               ##### Simple output compare functions #####
01153  ===============================================================================
01154     [..]  This section provides functions allowing to:
01155       (+) Configure simple output channel
01156       (+) Start simple output compare
01157       (+) Stop simple output compare
01158       (+) Start simple output compare and enable interrupt
01159       (+) Stop simple output compare and disable interrupt
01160       (+) Start simple output compare and enable DMA transfer
01161       (+) Stop simple output compare and disable DMA transfer
01162        -@- When a HRTIM timer operates in simple output compare mode
01163            the output level is set to a programmable value when a match
01164            is found between the compare register and the counter.
01165            Compare unit 1 is automatically associated to output 1
01166            Compare unit 2 is automatically associated to output 2
01167 @endverbatim
01168   * @{
01169   */
01170
01171 /**
01172   * @brief  Configure an output in simple output compare mode
01173   * @param  hhrtim pointer to HAL HRTIM handle
01174   * @param  TimerIdx Timer index
01175   *                   This parameter can be one of the following values:
01176   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01177   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01178   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01179   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01180   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01181   * @param  OCChannel Timer output
01182   *                    This parameter can be one of the following values:
01183   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01184   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01185   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01186   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01187   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01188   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01189   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01190   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01191   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01192   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01193   * @param  pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
01194   * @note When the timer operates in simple output compare mode:
01195   *         Output 1 is implicitly controlled by the compare unit 1
01196   *         Output 2 is implicitly controlled by the compare unit 2
01197   *       Output Set/Reset crossbar is set according to the selected output compare mode:
01198   *         Toggle: SETxyR = RSTxyR = CMPy
01199   *         Active: SETxyR = CMPy, RSTxyR = 0
01200   *         Inactive: SETxy =0, RSTxy = CMPy
01201   * @retval HAL status
01202   */
01203 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01204                                                  uint32_t TimerIdx,
01205                                                  uint32_t OCChannel,
01206                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
01207 {
01208   uint32_t CompareUnit = (uint32_t)RESET;
01209   HRTIM_OutputCfgTypeDef OutputCfg;
01210
01211   /* Check parameters */
01212   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01213   assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
01214   assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
01215   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
01216   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
01217
01218   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01219   {
01220      return HAL_BUSY;
01221   }
01222
01223   /* Set HRTIM state */
01224   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01225
01226   /* Configure timer compare unit */
01227   switch (OCChannel)
01228   {
01229   case HRTIM_OUTPUT_TA1:
01230   case HRTIM_OUTPUT_TB1:
01231   case HRTIM_OUTPUT_TC1:
01232   case HRTIM_OUTPUT_TD1:
01233   case HRTIM_OUTPUT_TE1:
01234     {
01235       CompareUnit = HRTIM_COMPAREUNIT_1;
01236       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
01237       break;
01238     }
01239   case HRTIM_OUTPUT_TA2:
01240   case HRTIM_OUTPUT_TB2:
01241   case HRTIM_OUTPUT_TC2:
01242   case HRTIM_OUTPUT_TD2:
01243   case HRTIM_OUTPUT_TE2:
01244     {
01245       CompareUnit = HRTIM_COMPAREUNIT_2;
01246       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
01247       break;
01248     }
01249   default:
01250     {
01251       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01252
01253       /* Process Unlocked */
01254       __HAL_UNLOCK(hhrtim);
01255
01256       break;
01257     }
01258   }
01259
01260   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
01261   {
01262      return HAL_ERROR;
01263   }
01264
01265   /* Configure timer output */
01266   OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
01267   OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
01268   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01269   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01270   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01271   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01272
01273   switch (pSimpleOCChannelCfg->Mode)
01274   {
01275   case HRTIM_BASICOCMODE_TOGGLE:
01276     {
01277       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01278       {
01279         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01280       }
01281       else
01282       {
01283         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01284       }
01285       OutputCfg.ResetSource = OutputCfg.SetSource;
01286       break;
01287     }
01288
01289   case HRTIM_BASICOCMODE_ACTIVE:
01290     {
01291       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01292       {
01293         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01294       }
01295       else
01296       {
01297         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01298       }
01299       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01300       break;
01301     }
01302
01303   case HRTIM_BASICOCMODE_INACTIVE:
01304     {
01305       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01306       {
01307         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
01308       }
01309       else
01310       {
01311         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
01312       }
01313       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01314       break;
01315     }
01316
01317   default:
01318     {
01319       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01320       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01321
01322       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01323
01324       /* Process Unlocked */
01325       __HAL_UNLOCK(hhrtim);
01326
01327       break;
01328     }
01329   }
01330
01331   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
01332   {
01333      return HAL_ERROR;
01334   }
01335
01336   HRTIM_OutputConfig(hhrtim,
01337                      TimerIdx,
01338                      OCChannel,
01339                      &OutputCfg);
01340
01341   /* Set HRTIM state */
01342   hhrtim->State = HAL_HRTIM_STATE_READY;
01343
01344   return HAL_OK;
01345 }
01346
01347 /**
01348   * @brief  Start the output compare signal generation on the designed timer output
01349   * @param  hhrtim pointer to HAL HRTIM handle
01350   * @param  TimerIdx Timer index
01351   *                   This parameter can be one of the following values:
01352   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01353   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01354   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01355   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01356   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01357   * @param  OCChannel Timer output
01358   *                    This parameter can be one of the following values:
01359   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01360   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01361   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01362   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01363   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01364   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01365   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01366   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01367   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01368   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01369   * @retval HAL status
01370   */
01371 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
01372                                          uint32_t TimerIdx,
01373                                          uint32_t OCChannel)
01374 {
01375    /* Check the parameters */
01376   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01377
01378   /* Process Locked */
01379   __HAL_LOCK(hhrtim);
01380
01381   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01382
01383   /* Enable the timer output */
01384   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01385
01386   /* Enable the timer counter */
01387   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01388
01389   hhrtim->State = HAL_HRTIM_STATE_READY;
01390
01391   /* Process Unlocked */
01392   __HAL_UNLOCK(hhrtim);
01393
01394   return HAL_OK;
01395 }
01396
01397 /**
01398   * @brief  Stop the output compare signal generation on the designed timer output
01399   * @param  hhrtim pointer to HAL HRTIM handle
01400   * @param  TimerIdx Timer index
01401   *                   This parameter can be one of the following values:
01402   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01403   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01404   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01405   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01406   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01407   * @param  OCChannel Timer output
01408   *                    This parameter can be one of the following values:
01409   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01410   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01411   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01412   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01413   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01414   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01415   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01416   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01417   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01418   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01419   * @retval HAL status
01420   */
01421 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
01422                                         uint32_t TimerIdx,
01423                                         uint32_t OCChannel)
01424 {
01425    /* Check the parameters */
01426   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01427
01428   /* Process Locked */
01429   __HAL_LOCK(hhrtim);
01430
01431   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01432
01433   /* Disable the timer output */
01434   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01435
01436   /* Disable the timer counter */
01437   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01438
01439   hhrtim->State = HAL_HRTIM_STATE_READY;
01440
01441   /* Process Unlocked */
01442   __HAL_UNLOCK(hhrtim);
01443
01444   return HAL_OK;
01445 }
01446
01447 /**
01448   * @brief  Start the output compare signal generation on the designed timer output
01449   *         (Interrupt is enabled (see note note below)).
01450   * @param  hhrtim pointer to HAL HRTIM handle
01451   * @param  TimerIdx Timer index
01452   *                   This parameter can be one of the following values:
01453   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01454   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01455   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01456   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01457   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01458   * @param  OCChannel Timer output
01459   *                    This parameter can be one of the following values:
01460   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01461   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01462   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01463   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01464   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01465   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01466   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01467   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01468   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01469   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01470   * @note Interrupt enabling depends on the chosen output compare mode
01471   *          Output toggle: compare match interrupt is enabled
01472   *          Output set active:  output set interrupt is enabled
01473   *          Output set inactive:  output reset interrupt is enabled
01474   * @retval HAL status
01475   */
01476 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
01477                                             uint32_t TimerIdx,
01478                                             uint32_t OCChannel)
01479 {
01480   uint32_t interrupt;
01481
01482    /* Check the parameters */
01483   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01484
01485   /* Process Locked */
01486   __HAL_LOCK(hhrtim);
01487
01488   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01489
01490   /* Get the interrupt to enable (depends on the output compare mode) */
01491   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01492
01493   /* Enable the timer output */
01494   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01495
01496   /* Enable the timer interrupt (depends on the output compare mode) */
01497   __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
01498
01499   /* Enable the timer counter */
01500   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01501
01502   hhrtim->State = HAL_HRTIM_STATE_READY;
01503
01504   /* Process Unlocked */
01505   __HAL_UNLOCK(hhrtim);
01506
01507   return HAL_OK;
01508 }
01509
01510 /**
01511   * @brief  Stop the output compare signal generation on the designed timer output
01512   *         (Interrupt is disabled).
01513   * @param  hhrtim pointer to HAL HRTIM handle
01514   * @param  TimerIdx Timer index
01515   *                   This parameter can be one of the following values:
01516   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01517   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01518   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01519   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01520   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01521   * @param  OCChannel Timer output
01522   *                    This parameter can be one of the following values:
01523   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01524   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01525   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01526   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01527   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01528   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01529   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01530   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01531   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01532   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01533   * @retval HAL status
01534   */
01535 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
01536                                            uint32_t TimerIdx,
01537                                            uint32_t OCChannel)
01538 {
01539   uint32_t interrupt;
01540
01541    /* Check the parameters */
01542   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01543
01544   /* Process Locked */
01545   __HAL_LOCK(hhrtim);
01546
01547   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01548
01549   /* Disable the timer output */
01550   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01551
01552   /* Get the interrupt to disable (depends on the output compare mode) */
01553   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01554
01555   /* Disable the timer interrupt */
01556   __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
01557
01558   /* Disable the timer counter */
01559   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01560
01561   hhrtim->State = HAL_HRTIM_STATE_READY;
01562
01563   /* Process Unlocked */
01564   __HAL_UNLOCK(hhrtim);
01565
01566   return HAL_OK;
01567 }
01568
01569 /**
01570   * @brief  Start the output compare signal generation on the designed timer output
01571   *         (DMA request is enabled (see note below)).
01572   * @param  hhrtim pointer to HAL HRTIM handle
01573   * @param  TimerIdx Timer index
01574   *                   This parameter can be one of the following values:
01575   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01576   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01577   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01578   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01579   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01580   * @param  OCChannel Timer output
01581   *                    This parameter can be one of the following values:
01582   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01583   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01584   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01585   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01586   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01587   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01588   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01589   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01590   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01591   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01592   * @param  SrcAddr DMA transfer source address
01593   * @param  DestAddr DMA transfer destination address
01594   * @param  Length The length of data items (data size) to be transferred
01595   *                     from source to destination
01596   * @note  DMA request enabling depends on the chosen output compare mode
01597   *          Output toggle: compare match DMA request is enabled
01598   *          Output set active:  output set DMA request is enabled
01599   *          Output set inactive:  output reset DMA request is enabled
01600   * @retval HAL status
01601   */
01602 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01603                                              uint32_t TimerIdx,
01604                                              uint32_t OCChannel,
01605                                              uint32_t SrcAddr,
01606                                              uint32_t DestAddr,
01607                                              uint32_t Length)
01608 {
01609   DMA_HandleTypeDef * hdma;
01610   uint32_t dma_request;
01611
01612   /* Check the parameters */
01613   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01614
01615   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
01616   {
01617      return HAL_BUSY;
01618   }
01619   if((hhrtim->State == HAL_HRTIM_STATE_READY))
01620   {
01621     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
01622     {
01623       return HAL_ERROR;
01624     }
01625     else
01626     {
01627       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01628     }
01629   }
01630
01631   /* Process Locked */
01632   __HAL_LOCK(hhrtim);
01633
01634    /* Enable the timer output */
01635   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01636
01637   /* Get the DMA request to enable */
01638   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01639
01640   /* Get the timer DMA handler */
01641   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01642
01643   if (hdma == NULL)
01644   {
01645    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01646
01647    /* Process Unlocked */
01648    __HAL_UNLOCK(hhrtim);
01649
01650    return HAL_ERROR;
01651   }
01652
01653   /* Set the DMA error callback */
01654   hdma->XferErrorCallback = HRTIM_DMAError ;
01655
01656   /* Set the DMA transfer completed callback */
01657   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01658
01659   /* Enable the DMA channel */
01660   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
01661     {
01662         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01663
01664         /* Process Unlocked */
01665         __HAL_UNLOCK(hhrtim);
01666
01667         return HAL_ERROR;
01668     }
01669
01670   /* Enable the timer DMA request */
01671   __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
01672
01673   /* Enable the timer counter */
01674   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01675
01676   hhrtim->State = HAL_HRTIM_STATE_READY;
01677
01678   /* Process Unlocked */
01679   __HAL_UNLOCK(hhrtim);
01680
01681   return HAL_OK;
01682 }
01683
01684 /**
01685   * @brief  Stop the output compare signal generation on the designed timer output
01686   *         (DMA request is disabled).
01687   * @param  hhrtim pointer to HAL HRTIM handle
01688   * @param  TimerIdx Timer index
01689   *                   This parameter can be one of the following values:
01690   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01691   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01692   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01693   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01694   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01695   * @param  OCChannel Timer output
01696   *                    This parameter can be one of the following values:
01697   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01698   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01699   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01700   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01701   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01702   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01703   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01704   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01705   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01706   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01707   * @retval HAL status
01708   */
01709 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01710                                             uint32_t TimerIdx,
01711                                             uint32_t OCChannel)
01712 {
01713   uint32_t dma_request;
01714
01715   /* Check the parameters */
01716   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01717
01718   /* Process Locked */
01719   __HAL_LOCK(hhrtim);
01720
01721   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01722
01723   /* Disable the timer output */
01724   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01725
01726   /* Get the timer DMA handler */
01727   /* Disable the DMA */
01728   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
01729   {
01730     hhrtim->State = HAL_HRTIM_STATE_ERROR;
01731
01732     /* Process Unlocked */
01733     __HAL_UNLOCK(hhrtim);
01734
01735     return HAL_ERROR;
01736   }
01737
01738   /* Get the DMA request to disable */
01739   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01740
01741   /* Disable the timer DMA request */
01742   __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
01743
01744   /* Disable the timer counter */
01745   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01746
01747   hhrtim->State = HAL_HRTIM_STATE_READY;
01748
01749   /* Process Unlocked */
01750   __HAL_UNLOCK(hhrtim);
01751
01752   return HAL_OK;
01753 }
01754
01755 /**
01756   * @}
01757   */
01758
01759 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
01760  *  @brief    Simple PWM output functions
01761 @verbatim
01762  ===============================================================================
01763               ##### Simple PWM output functions #####
01764  ===============================================================================
01765     [..]  This section provides functions allowing to:
01766       (+) Configure simple PWM output channel
01767       (+) Start simple PWM output
01768       (+) Stop simple PWM output
01769       (+) Start simple PWM output and enable interrupt
01770       (+) Stop simple PWM output and disable interrupt
01771       (+) Start simple PWM output and enable DMA transfer
01772       (+) Stop simple PWM output and disable DMA transfer
01773       -@- When a HRTIM timer operates in simple PWM output mode
01774           the output level is set to a programmable value when a match is
01775           found between the compare register and the counter and reset when
01776           the timer period is reached. Duty cycle is determined by the
01777           comparison value.
01778           Compare unit 1 is automatically associated to output 1
01779           Compare unit 2 is automatically associated to output 2
01780 @endverbatim
01781   * @{
01782   */
01783
01784 /**
01785   * @brief  Configure an output in simple PWM mode
01786   * @param  hhrtim pointer to HAL HRTIM handle
01787   * @param  TimerIdx Timer index
01788   *                   This parameter can be one of the following values:
01789   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01790   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01791   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01792   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01793   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01794   * @param  PWMChannel Timer output
01795   *                    This parameter can be one of the following values:
01796   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01797   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01798   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01799   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01800   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01801   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01802   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01803   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01804   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01805   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01806   * @param  pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
01807   * @note When the timer operates in simple PWM output mode:
01808   *         Output 1 is implicitly controlled by the compare unit 1
01809   *         Output 2 is implicitly controlled by the compare unit 2
01810   *       Output Set/Reset crossbar is set as follows:
01811   *         Output 1: SETx1R = CMP1, RSTx1R = PER
01812   *         Output 2: SETx2R = CMP2, RST2R = PER
01813   * @note When Simple PWM mode is used the registers preload mechanism is
01814   *       enabled (otherwise the behavior is not guaranteed).
01815   * @retval HAL status
01816   */
01817 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01818                                                   uint32_t TimerIdx,
01819                                                   uint32_t PWMChannel,
01820                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
01821 {
01822   HRTIM_OutputCfgTypeDef OutputCfg;
01823   uint32_t hrtim_timcr;
01824
01825   /* Check parameters */
01826   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01827   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
01828   assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
01829   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
01830
01831   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01832   {
01833      return HAL_BUSY;
01834   }
01835
01836   /* Process Locked */
01837   __HAL_LOCK(hhrtim);
01838
01839   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01840
01841   /* Configure timer compare unit */
01842   switch (PWMChannel)
01843   {
01844   case HRTIM_OUTPUT_TA1:
01845   case HRTIM_OUTPUT_TB1:
01846   case HRTIM_OUTPUT_TC1:
01847   case HRTIM_OUTPUT_TD1:
01848   case HRTIM_OUTPUT_TE1:
01849     {
01850       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
01851       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01852       break;
01853     }
01854
01855   case HRTIM_OUTPUT_TA2:
01856   case HRTIM_OUTPUT_TB2:
01857   case HRTIM_OUTPUT_TC2:
01858   case HRTIM_OUTPUT_TD2:
01859   case HRTIM_OUTPUT_TE2:
01860     {
01861       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
01862       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01863       break;
01864     }
01865   default:
01866     {
01867       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01868       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01869
01870       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01871
01872       /* Process Unlocked */
01873       __HAL_UNLOCK(hhrtim);
01874
01875       break;
01876     }
01877   }
01878
01879   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
01880   {
01881      return HAL_ERROR;
01882   }
01883
01884   /* Configure timer output */
01885   OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
01886   OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
01887   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01888   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01889   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01890   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01891   OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
01892
01893   HRTIM_OutputConfig(hhrtim,
01894                      TimerIdx,
01895                      PWMChannel,
01896                      &OutputCfg);
01897
01898   /* Enable the registers preload mechanism */
01899   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
01900   hrtim_timcr |= HRTIM_TIMCR_PREEN;
01901   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
01902
01903   hhrtim->State = HAL_HRTIM_STATE_READY;
01904
01905   /* Process Unlocked */
01906   __HAL_UNLOCK(hhrtim);
01907
01908   return HAL_OK;
01909 }
01910
01911 /**
01912   * @brief  Start the PWM output signal generation on the designed timer output
01913   * @param  hhrtim pointer to HAL HRTIM handle
01914   * @param  TimerIdx Timer index
01915   *                   This parameter can be one of the following values:
01916   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01917   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01918   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01919   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01920   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01921   * @param  PWMChannel Timer output
01922   *                    This parameter can be one of the following values:
01923   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01924   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01925   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01926   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01927   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01928   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01929   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01930   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01931   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01932   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01933   * @retval HAL status
01934   */
01935 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
01936                                           uint32_t TimerIdx,
01937                                           uint32_t PWMChannel)
01938 {
01939    /* Check the parameters */
01940   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01941
01942   /* Process Locked */
01943   __HAL_LOCK(hhrtim);
01944
01945   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01946
01947   /* Enable the timer output */
01948   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
01949
01950   /* Enable the timer counter */
01951   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01952
01953   hhrtim->State = HAL_HRTIM_STATE_READY;
01954
01955   /* Process Unlocked */
01956   __HAL_UNLOCK(hhrtim);
01957
01958   return HAL_OK;
01959 }
01960
01961 /**
01962   * @brief  Stop the PWM output signal generation on the designed timer output
01963   * @param  hhrtim pointer to HAL HRTIM handle
01964   * @param  TimerIdx Timer index
01965   *                   This parameter can be one of the following values:
01966   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01967   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01968   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01969   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01970   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01971   * @param  PWMChannel Timer output
01972   *                    This parameter can be one of the following values:
01973   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01974   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01975   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01976   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01977   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01978   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01979   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01980   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01981   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01982   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01983   * @retval HAL status
01984   */
01985 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
01986                                          uint32_t TimerIdx,
01987                                          uint32_t PWMChannel)
01988 {
01989    /* Check the parameters */
01990   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01991
01992   /* Process Locked */
01993   __HAL_LOCK(hhrtim);
01994
01995   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01996
01997   /* Disable the timer output */
01998   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
01999
02000   /* Disable the timer counter */
02001   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02002
02003   hhrtim->State = HAL_HRTIM_STATE_READY;
02004
02005   /* Process Unlocked */
02006   __HAL_UNLOCK(hhrtim);
02007
02008   return HAL_OK;
02009 }
02010
02011 /**
02012   * @brief  Start the PWM output signal generation on the designed timer output
02013   *         (The compare interrupt is enabled).
02014   * @param  hhrtim pointer to HAL HRTIM handle
02015   * @param  TimerIdx Timer index
02016   *                   This parameter can be one of the following values:
02017   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02018   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02019   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02020   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02021   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02022   * @param  PWMChannel Timer output
02023   *                    This parameter can be one of the following values:
02024   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02025   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02026   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02027   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02028   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02029   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02030   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02031   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02032   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02033   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02034   * @retval HAL status
02035   */
02036 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
02037                                              uint32_t TimerIdx,
02038                                              uint32_t PWMChannel)
02039 {
02040    /* Check the parameters */
02041   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02042
02043   /* Process Locked */
02044   __HAL_LOCK(hhrtim);
02045
02046   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02047
02048   /* Enable the timer output */
02049   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02050
02051   /* Enable the timer interrupt (depends on the PWM output) */
02052   switch (PWMChannel)
02053   {
02054   case HRTIM_OUTPUT_TA1:
02055   case HRTIM_OUTPUT_TB1:
02056   case HRTIM_OUTPUT_TC1:
02057   case HRTIM_OUTPUT_TD1:
02058   case HRTIM_OUTPUT_TE1:
02059     {
02060       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02061       break;
02062     }
02063
02064   case HRTIM_OUTPUT_TA2:
02065   case HRTIM_OUTPUT_TB2:
02066   case HRTIM_OUTPUT_TC2:
02067   case HRTIM_OUTPUT_TD2:
02068   case HRTIM_OUTPUT_TE2:
02069     {
02070       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02071       break;
02072     }
02073
02074   default:
02075     {
02076       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02077
02078       /* Process Unlocked */
02079       __HAL_UNLOCK(hhrtim);
02080
02081       break;
02082     }
02083   }
02084
02085   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02086   {
02087      return HAL_ERROR;
02088   }
02089
02090   /* Enable the timer counter */
02091   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02092
02093   hhrtim->State = HAL_HRTIM_STATE_READY;
02094
02095   /* Process Unlocked */
02096   __HAL_UNLOCK(hhrtim);
02097
02098   return HAL_OK;
02099 }
02100
02101 /**
02102   * @brief  Stop the PWM output signal generation on the designed timer output
02103   *         (The compare interrupt is disabled).
02104   * @param  hhrtim pointer to HAL HRTIM handle
02105   * @param  TimerIdx Timer index
02106   *                   This parameter can be one of the following values:
02107   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02108   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02109   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02110   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02111   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02112   * @param  PWMChannel Timer output
02113   *                    This parameter can be one of the following values:
02114   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02115   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02116   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02117   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02118   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02119   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02120   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02121   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02122   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02123   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02124   * @retval HAL status
02125   */
02126 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
02127                                             uint32_t TimerIdx,
02128                                             uint32_t PWMChannel)
02129 {
02130    /* Check the parameters */
02131   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02132
02133   /* Process Locked */
02134   __HAL_LOCK(hhrtim);
02135
02136   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02137
02138   /* Disable the timer output */
02139   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02140
02141   /* Disable the timer interrupt (depends on the PWM output) */
02142   switch (PWMChannel)
02143   {
02144   case HRTIM_OUTPUT_TA1:
02145   case HRTIM_OUTPUT_TB1:
02146   case HRTIM_OUTPUT_TC1:
02147   case HRTIM_OUTPUT_TD1:
02148   case HRTIM_OUTPUT_TE1:
02149     {
02150       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02151       break;
02152     }
02153
02154   case HRTIM_OUTPUT_TA2:
02155   case HRTIM_OUTPUT_TB2:
02156   case HRTIM_OUTPUT_TC2:
02157   case HRTIM_OUTPUT_TD2:
02158   case HRTIM_OUTPUT_TE2:
02159     {
02160       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02161       break;
02162     }
02163
02164   default:
02165     {
02166       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02167
02168       /* Process Unlocked */
02169       __HAL_UNLOCK(hhrtim);
02170
02171       break;
02172     }
02173   }
02174
02175   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02176   {
02177      return HAL_ERROR;
02178   }
02179
02180   /* Disable the timer counter */
02181   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02182
02183   hhrtim->State = HAL_HRTIM_STATE_READY;
02184
02185   /* Process Unlocked */
02186   __HAL_UNLOCK(hhrtim);
02187
02188   return HAL_OK;
02189 }
02190
02191 /**
02192   * @brief  Start the PWM output signal generation on the designed timer output
02193   *         (The compare DMA request is enabled).
02194   * @param  hhrtim pointer to HAL HRTIM handle
02195   * @param  TimerIdx Timer index
02196   *                   This parameter can be one of the following values:
02197   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02198   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02199   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02200   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02201   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02202   * @param  PWMChannel Timer output
02203   *                    This parameter can be one of the following values:
02204   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02205   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02206   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02207   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02208   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02209   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02210   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02211   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02212   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02213   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02214   * @param  SrcAddr DMA transfer source address
02215   * @param  DestAddr DMA transfer destination address
02216   * @param  Length The length of data items (data size) to be transferred
02217   *                     from source to destination
02218   * @retval HAL status
02219   */
02220 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02221                                               uint32_t TimerIdx,
02222                                               uint32_t PWMChannel,
02223                                               uint32_t SrcAddr,
02224                                               uint32_t DestAddr,
02225                                               uint32_t Length)
02226 {
02227   DMA_HandleTypeDef * hdma;
02228
02229   /* Check the parameters */
02230   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02231
02232   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
02233   {
02234      return HAL_BUSY;
02235   }
02236   if((hhrtim->State == HAL_HRTIM_STATE_READY))
02237   {
02238     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
02239     {
02240       return HAL_ERROR;
02241     }
02242     else
02243     {
02244       hhrtim->State = HAL_HRTIM_STATE_BUSY;
02245     }
02246   }
02247
02248   /* Process Locked */
02249   __HAL_LOCK(hhrtim);
02250
02251   /* Enable the timer output */
02252   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02253
02254   /* Get the timer DMA handler */
02255   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02256
02257   if (hdma == NULL)
02258   {
02259     hhrtim->State = HAL_HRTIM_STATE_ERROR;
02260
02261     /* Process Unlocked */
02262     __HAL_UNLOCK(hhrtim);
02263
02264     return HAL_ERROR;
02265   }
02266
02267   /* Set the DMA error callback */
02268   hdma->XferErrorCallback = HRTIM_DMAError ;
02269
02270   /* Set the DMA transfer completed callback */
02271   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02272
02273   /* Enable the DMA channel */
02274   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
02275     {
02276         hhrtim->State = HAL_HRTIM_STATE_ERROR;
02277
02278         /* Process Unlocked */
02279         __HAL_UNLOCK(hhrtim);
02280
02281         return HAL_ERROR;
02282     }
02283
02284   /* Enable the timer DMA request */
02285   switch (PWMChannel)
02286   {
02287   case HRTIM_OUTPUT_TA1:
02288   case HRTIM_OUTPUT_TB1:
02289   case HRTIM_OUTPUT_TC1:
02290   case HRTIM_OUTPUT_TD1:
02291   case HRTIM_OUTPUT_TE1:
02292     {
02293       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02294       break;
02295     }
02296
02297   case HRTIM_OUTPUT_TA2:
02298   case HRTIM_OUTPUT_TB2:
02299   case HRTIM_OUTPUT_TC2:
02300   case HRTIM_OUTPUT_TD2:
02301   case HRTIM_OUTPUT_TE2:
02302     {
02303       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02304       break;
02305     }
02306
02307   default:
02308     {
02309       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02310
02311       /* Process Unlocked */
02312       __HAL_UNLOCK(hhrtim);
02313
02314       break;
02315     }
02316   }
02317
02318   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02319   {
02320      return HAL_ERROR;
02321   }
02322
02323   /* Enable the timer counter */
02324   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02325
02326   hhrtim->State = HAL_HRTIM_STATE_READY;
02327
02328   /* Process Unlocked */
02329   __HAL_UNLOCK(hhrtim);
02330
02331   return HAL_OK;
02332 }
02333
02334 /**
02335   * @brief  Stop the PWM output signal generation on the designed timer output
02336   *         (The compare DMA request is disabled).
02337   * @param  hhrtim pointer to HAL HRTIM handle
02338   * @param  TimerIdx Timer index
02339   *                   This parameter can be one of the following values:
02340   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02341   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02342   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02343   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02344   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02345   * @param  PWMChannel Timer output
02346   *                    This parameter can be one of the following values:
02347   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02348   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02349   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02350   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02351   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02352   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02353   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02354   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02355   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02356   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02357   * @retval HAL status
02358   */
02359 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02360                                              uint32_t TimerIdx,
02361                                              uint32_t PWMChannel)
02362 {
02363   /* Check the parameters */
02364   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02365
02366   /* Process Locked */
02367   __HAL_LOCK(hhrtim);
02368
02369   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02370
02371   /* Disable the timer output */
02372   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02373
02374   /* Get the timer DMA handler */
02375   /* Disable the DMA */
02376   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
02377   {
02378     hhrtim->State = HAL_HRTIM_STATE_ERROR;
02379
02380     /* Process Unlocked */
02381     __HAL_UNLOCK(hhrtim);
02382
02383     return HAL_ERROR;
02384   }
02385
02386   /* Disable the timer DMA request */
02387   switch (PWMChannel)
02388   {
02389   case HRTIM_OUTPUT_TA1:
02390   case HRTIM_OUTPUT_TB1:
02391   case HRTIM_OUTPUT_TC1:
02392   case HRTIM_OUTPUT_TD1:
02393   case HRTIM_OUTPUT_TE1:
02394     {
02395       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02396       break;
02397     }
02398
02399   case HRTIM_OUTPUT_TA2:
02400   case HRTIM_OUTPUT_TB2:
02401   case HRTIM_OUTPUT_TC2:
02402   case HRTIM_OUTPUT_TD2:
02403   case HRTIM_OUTPUT_TE2:
02404     {
02405       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02406       break;
02407     }
02408
02409   default:
02410     {
02411       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02412
02413       /* Process Unlocked */
02414       __HAL_UNLOCK(hhrtim);
02415
02416       break;
02417     }
02418   }
02419
02420   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02421   {
02422      return HAL_ERROR;
02423   }
02424
02425   /* Disable the timer counter */
02426   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02427
02428   hhrtim->State = HAL_HRTIM_STATE_READY;
02429
02430   /* Process Unlocked */
02431   __HAL_UNLOCK(hhrtim);
02432
02433   return HAL_OK;
02434 }
02435
02436 /**
02437   * @}
02438   */
02439
02440 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
02441  *  @brief    Simple input capture functions
02442 @verbatim
02443  ===============================================================================
02444               ##### Simple input capture functions #####
02445  ===============================================================================
02446     [..]  This section provides functions allowing to:
02447       (+) Configure simple input capture channel
02448       (+) Start simple input capture
02449       (+) Stop simple input capture
02450       (+) Start simple input capture and enable interrupt
02451       (+) Stop simple input capture and disable interrupt
02452       (+) Start simple input capture and enable DMA transfer
02453       (+) Stop simple input capture and disable DMA transfer
02454       -@- When a HRTIM timer operates in simple input capture mode
02455           the Capture Register (HRTIM_CPT1/2xR) is used to latch the
02456          value of the timer counter counter after a transition detected
02457          on a given external event input.
02458 @endverbatim
02459   * @{
02460   */
02461
02462 /**
02463   * @brief  Configure a simple capture
02464   * @param  hhrtim pointer to HAL HRTIM handle
02465   * @param  TimerIdx Timer index
02466   *                   This parameter can be one of the following values:
02467   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02468   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02469   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02470   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02471   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02472   * @param  CaptureChannel Capture unit
02473   *                    This parameter can be one of the following values:
02474   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02475   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02476   * @param  pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
02477   * @note When the timer operates in simple capture mode the capture is trigerred
02478   *       by the designated external event and GPIO input is implicitly used as event source.
02479   *       The cature can be triggered by a rising edge, a falling edge or both
02480   *       edges on event channel.
02481   * @retval HAL status
02482   */
02483 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02484                                                       uint32_t TimerIdx,
02485                                                       uint32_t CaptureChannel,
02486                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
02487 {
02488   HRTIM_EventCfgTypeDef EventCfg;
02489
02490   /* Check parameters */
02491   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02492   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02493   assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
02494   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
02495                                       pSimpleCaptureChannelCfg->EventPolarity));
02496   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
02497   assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
02498                                     pSimpleCaptureChannelCfg->EventFilter));
02499
02500   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02501   {
02502      return HAL_BUSY;
02503   }
02504
02505   /* Process Locked */
02506   __HAL_LOCK(hhrtim);
02507
02508   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02509
02510   /* Configure external event channel */
02511   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
02512   EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
02513   EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
02514   EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
02515   EventCfg.Source = HRTIM_EVENTSRC_1;
02516
02517   HRTIM_EventConfig(hhrtim,
02518                     pSimpleCaptureChannelCfg->Event,
02519                     &EventCfg);
02520
02521   /* Memorize capture trigger (will be configured when the capture is started */
02522   HRTIM_CaptureUnitConfig(hhrtim,
02523                           TimerIdx,
02524                           CaptureChannel,
02525                           pSimpleCaptureChannelCfg->Event);
02526
02527   hhrtim->State = HAL_HRTIM_STATE_READY;
02528
02529   /* Process Unlocked */
02530   __HAL_UNLOCK(hhrtim);
02531
02532   return HAL_OK;
02533 }
02534
02535 /**
02536   * @brief  Enable a simple capture on the designed capture unit
02537   * @param  hhrtim pointer to HAL HRTIM handle
02538   * @param  TimerIdx Timer index
02539   *                   This parameter can be one of the following values:
02540   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02541   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02542   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02543   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02544   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02545   * @param  CaptureChannel Timer output
02546   *                    This parameter can be one of the following values:
02547   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02548   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02549   * @retval HAL status
02550   * @note  The external event triggering the capture is available for all timing
02551   *        units. It can be used directly and is active as soon as the timing
02552   *        unit counter is enabled.
02553   */
02554 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
02555                                               uint32_t TimerIdx,
02556                                               uint32_t CaptureChannel)
02557 {
02558    /* Check the parameters */
02559   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02560   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02561
02562   /* Process Locked */
02563   __HAL_LOCK(hhrtim);
02564
02565   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02566
02567   /* Set the capture unit trigger */
02568   switch (CaptureChannel)
02569   {
02570   case HRTIM_CAPTUREUNIT_1:
02571     {
02572       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02573       break;
02574     }
02575
02576   case HRTIM_CAPTUREUNIT_2:
02577     {
02578       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02579       break;
02580     }
02581
02582   default:
02583     {
02584       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02585
02586       /* Process Unlocked */
02587       __HAL_UNLOCK(hhrtim);
02588
02589       break;
02590     }
02591   }
02592
02593   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02594   {
02595      return HAL_ERROR;
02596   }
02597
02598   /* Enable the timer counter */
02599   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02600
02601   hhrtim->State = HAL_HRTIM_STATE_READY;
02602
02603   /* Process Unlocked */
02604   __HAL_UNLOCK(hhrtim);
02605
02606   return HAL_OK;
02607 }
02608
02609 /**
02610   * @brief  Disable a simple capture on the designed capture unit
02611   * @param  hhrtim pointer to HAL HRTIM handle
02612   * @param  TimerIdx Timer index
02613   *                   This parameter can be one of the following values:
02614   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02615   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02616   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02617   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02618   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02619   * @param  CaptureChannel Timer output
02620   *                    This parameter can be one of the following values:
02621   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02622   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02623   * @retval HAL status
02624   */
02625 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
02626                                              uint32_t TimerIdx,
02627                                              uint32_t CaptureChannel)
02628 {
02629   uint32_t hrtim_cpt1cr;
02630   uint32_t hrtim_cpt2cr;
02631
02632    /* Check the parameters */
02633   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02634   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02635
02636   /* Process Locked */
02637   __HAL_LOCK(hhrtim);
02638
02639   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02640
02641   /* Set the capture unit trigger */
02642   switch (CaptureChannel)
02643   {
02644   case HRTIM_CAPTUREUNIT_1:
02645     {
02646       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02647       break;
02648     }
02649
02650   case HRTIM_CAPTUREUNIT_2:
02651     {
02652       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02653       break;
02654     }
02655
02656   default:
02657     {
02658       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02659
02660       /* Process Unlocked */
02661       __HAL_UNLOCK(hhrtim);
02662
02663       break;
02664     }
02665   }
02666
02667   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02668   {
02669      return HAL_ERROR;
02670   }
02671
02672   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
02673   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
02674
02675   /* Disable the timer counter */
02676   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
02677       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
02678   {
02679     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02680   }
02681
02682   hhrtim->State = HAL_HRTIM_STATE_READY;
02683
02684   /* Process Unlocked */
02685   __HAL_UNLOCK(hhrtim);
02686
02687   return HAL_OK;
02688 }
02689
02690 /**
02691   * @brief  Enable a simple capture on the designed capture unit
02692   *         (Capture interrupt is enabled).
02693   * @param  hhrtim pointer to HAL HRTIM handle
02694   * @param  TimerIdx Timer index
02695   *                   This parameter can be one of the following values:
02696   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02697   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02698   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02699   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02700   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02701   * @param  CaptureChannel Timer output
02702   *                    This parameter can be one of the following values:
02703   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02704   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02705   * @retval HAL status
02706   */
02707 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
02708                                                  uint32_t TimerIdx,
02709                                                  uint32_t CaptureChannel)
02710 {
02711    /* Check the parameters */
02712   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02713   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02714
02715   /* Process Locked */
02716   __HAL_LOCK(hhrtim);
02717
02718   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02719
02720   /* Set the capture unit trigger */
02721   switch (CaptureChannel)
02722   {
02723   case HRTIM_CAPTUREUNIT_1:
02724     {
02725       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02726
02727       /* Enable the capture unit 1 interrupt */
02728       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02729       break;
02730     }
02731
02732   case HRTIM_CAPTUREUNIT_2:
02733     {
02734       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02735
02736       /* Enable the capture unit 2 interrupt */
02737       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02738       break;
02739     }
02740
02741   default:
02742     {
02743       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02744
02745       /* Process Unlocked */
02746       __HAL_UNLOCK(hhrtim);
02747
02748       break;
02749     }
02750   }
02751
02752   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02753   {
02754      return HAL_ERROR;
02755   }
02756
02757   /* Enable the timer counter */
02758   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02759
02760   hhrtim->State = HAL_HRTIM_STATE_READY;
02761
02762   /* Process Unlocked */
02763   __HAL_UNLOCK(hhrtim);
02764
02765   return HAL_OK;
02766 }
02767
02768 /**
02769   * @brief  Disable a simple capture on the designed capture unit
02770   *         (Capture interrupt is disabled).
02771   * @param  hhrtim pointer to HAL HRTIM handle
02772   * @param  TimerIdx Timer index
02773   *                   This parameter can be one of the following values:
02774   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02775   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02776   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02777   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02778   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02779   * @param  CaptureChannel Timer output
02780   *                    This parameter can be one of the following values:
02781   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02782   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02783   * @retval HAL status
02784   */
02785 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
02786                                                 uint32_t TimerIdx,
02787                                                 uint32_t CaptureChannel)
02788 {
02789
02790   uint32_t hrtim_cpt1cr;
02791   uint32_t hrtim_cpt2cr;
02792
02793    /* Check the parameters */
02794   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02795   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02796
02797   /* Process Locked */
02798   __HAL_LOCK(hhrtim);
02799
02800   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02801
02802   /* Set the capture unit trigger */
02803   switch (CaptureChannel)
02804   {
02805   case HRTIM_CAPTUREUNIT_1:
02806     {
02807       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02808
02809       /* Disable the capture unit 1 interrupt */
02810       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02811       break;
02812     }
02813
02814   case HRTIM_CAPTUREUNIT_2:
02815     {
02816       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02817
02818       /* Disable the capture unit 2 interrupt */
02819       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02820       break;
02821     }
02822
02823   default:
02824     {
02825       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02826
02827       /* Process Unlocked */
02828       __HAL_UNLOCK(hhrtim);
02829
02830       break;
02831     }
02832   }
02833
02834   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02835   {
02836      return HAL_ERROR;
02837   }
02838
02839   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
02840   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
02841
02842   /* Disable the timer counter */
02843   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
02844       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
02845   {
02846     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02847   }
02848
02849   hhrtim->State = HAL_HRTIM_STATE_READY;
02850
02851   /* Process Unlocked */
02852   __HAL_UNLOCK(hhrtim);
02853
02854   return HAL_OK;
02855 }
02856
02857 /**
02858   * @brief  Enable a simple capture on the designed capture unit
02859   *         (Capture DMA request is enabled).
02860   * @param  hhrtim pointer to HAL HRTIM handle
02861   * @param  TimerIdx Timer index
02862   *                   This parameter can be one of the following values:
02863   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02864   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02865   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02866   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02867   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02868   * @param  CaptureChannel Timer output
02869   *                    This parameter can be one of the following values:
02870   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02871   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02872   * @param  SrcAddr DMA transfer source address
02873   * @param  DestAddr DMA transfer destination address
02874   * @param  Length The length of data items (data size) to be transferred
02875   *                     from source to destination
02876   * @retval HAL status
02877   */
02878 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02879                                                   uint32_t TimerIdx,
02880                                                   uint32_t CaptureChannel,
02881                                                   uint32_t SrcAddr,
02882                                                   uint32_t DestAddr,
02883                                                   uint32_t Length)
02884 {
02885   DMA_HandleTypeDef * hdma;
02886
02887    /* Check the parameters */
02888   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02889   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02890
02891   /* Process Locked */
02892   __HAL_LOCK(hhrtim);
02893
02894   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02895
02896   /* Get the timer DMA handler */
02897   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02898
02899   if (hdma == NULL)
02900   {
02901    hhrtim->State = HAL_HRTIM_STATE_ERROR;
02902
02903    /* Process Unlocked */
02904    __HAL_UNLOCK(hhrtim);
02905
02906    return HAL_ERROR;
02907   }
02908
02909   /* Set the DMA error callback */
02910   hdma->XferErrorCallback = HRTIM_DMAError ;
02911
02912   /* Set the DMA transfer completed callback */
02913   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02914
02915   /* Enable the DMA channel */
02916   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
02917     {
02918         hhrtim->State = HAL_HRTIM_STATE_ERROR;
02919
02920         /* Process Unlocked */
02921         __HAL_UNLOCK(hhrtim);
02922
02923         return HAL_ERROR;
02924     }
02925
02926   switch (CaptureChannel)
02927   {
02928   case HRTIM_CAPTUREUNIT_1:
02929     {
02930       /* Set the capture unit trigger */
02931       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02932
02933       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
02934       break;
02935     }
02936
02937   case HRTIM_CAPTUREUNIT_2:
02938     {
02939       /* Set the capture unit trigger */
02940       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02941
02942       /* Enable the timer DMA request */
02943       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
02944       break;
02945     }
02946
02947   default:
02948     {
02949       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02950
02951       /* Process Unlocked */
02952       __HAL_UNLOCK(hhrtim);
02953
02954       break;
02955     }
02956  }
02957
02958  if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02959   {
02960      return HAL_ERROR;
02961   }
02962
02963   /* Enable the timer counter */
02964   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02965
02966   hhrtim->State = HAL_HRTIM_STATE_READY;
02967
02968   /* Process Unlocked */
02969   __HAL_UNLOCK(hhrtim);
02970
02971   return HAL_OK;
02972 }
02973
02974 /**
02975   * @brief  Disable a simple capture on the designed capture unit
02976   *         (Capture DMA request is disabled).
02977   * @param  hhrtim pointer to HAL HRTIM handle
02978   * @param  TimerIdx Timer index
02979   *                   This parameter can be one of the following values:
02980   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02981   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02982   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02983   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02984   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02985   * @param  CaptureChannel Timer output
02986   *                    This parameter can be one of the following values:
02987   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02988   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02989   * @retval HAL status
02990   */
02991 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02992                                                  uint32_t TimerIdx,
02993                                                  uint32_t CaptureChannel)
02994 {
02995
02996   uint32_t hrtim_cpt1cr;
02997   uint32_t hrtim_cpt2cr;
02998
02999   /* Check the parameters */
03000   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03001   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
03002
03003   /* Process Locked */
03004   __HAL_LOCK(hhrtim);
03005
03006   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03007
03008   /* Get the timer DMA handler */
03009   /* Disable the DMA */
03010   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
03011   {
03012         hhrtim->State = HAL_HRTIM_STATE_ERROR;
03013
03014         /* Process Unlocked */
03015         __HAL_UNLOCK(hhrtim);
03016
03017         return HAL_ERROR;
03018   }
03019
03020   switch (CaptureChannel)
03021   {
03022   case HRTIM_CAPTUREUNIT_1:
03023     {
03024       /* Reset the capture unit trigger */
03025       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
03026
03027       /* Disable the capture unit 1 DMA request */
03028       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
03029       break;
03030     }
03031
03032   case HRTIM_CAPTUREUNIT_2:
03033     {
03034       /* Reset the capture unit trigger */
03035       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
03036
03037       /* Disable the capture unit 2 DMA request */
03038       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
03039       break;
03040     }
03041
03042   default:
03043     {
03044       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03045
03046       /* Process Unlocked */
03047       __HAL_UNLOCK(hhrtim);
03048
03049       break;
03050     }
03051   }
03052
03053   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03054   {
03055      return HAL_ERROR;
03056   }
03057
03058   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
03059   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
03060
03061   /* Disable the timer counter */
03062   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
03063       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
03064   {
03065     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03066   }
03067
03068   hhrtim->State = HAL_HRTIM_STATE_READY;
03069
03070   /* Process Unlocked */
03071   __HAL_UNLOCK(hhrtim);
03072
03073   return HAL_OK;
03074 }
03075
03076 /**
03077   * @}
03078   */
03079
03080 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
03081  *  @brief    Simple one pulse functions
03082 @verbatim
03083  ===============================================================================
03084               ##### Simple one pulse functions #####
03085  ===============================================================================
03086     [..]  This section provides functions allowing to:
03087       (+) Configure one pulse channel
03088       (+) Start one pulse generation
03089       (+) Stop one pulse generation
03090       (+) Start one pulse generation and enable interrupt
03091       (+) Stop one pulse generation and disable interrupt
03092       -@- When a HRTIM timer operates in simple one pulse mode
03093           the timer counter is started in response to transition detected
03094           on a given external event input to generate a pulse with a
03095           programmable length after a programmable delay.
03096 @endverbatim
03097   * @{
03098   */
03099
03100 /**
03101   * @brief  Configure an output simple one pulse mode
03102   * @param  hhrtim pointer to HAL HRTIM handle
03103   * @param  TimerIdx Timer index
03104   *                   This parameter can be one of the following values:
03105   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03106   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03107   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03108   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03109   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03110   * @param  OnePulseChannel Timer output
03111   *                    This parameter can be one of the following values:
03112   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03113   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03114   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03115   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03116   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03117   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03118   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03119   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03120   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03121   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03122   * @param  pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
03123   * @note When the timer operates in simple one pulse mode:
03124   *         the timer counter is implicitly started by the reset event,
03125   *         the reset of the timer counter is triggered by the designated external event
03126   *         GPIO input is implicitly used as event source,
03127   *         Output 1 is implicitly controlled by the compare unit 1,
03128   *         Output 2 is implicitly controlled by the compare unit 2.
03129   *       Output Set/Reset crossbar is set as follows:
03130   *         Output 1: SETx1R = CMP1, RSTx1R = PER
03131   *         Output 2: SETx2R = CMP2, RST2R = PER
03132   * @retval HAL status
03133   * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
03134   *       outputs, the reset event related configuration data provided in the
03135   *       second call will override the reset event related configuration data
03136   *       provided in the first call.
03137   */
03138 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
03139                                                        uint32_t TimerIdx,
03140                                                        uint32_t OnePulseChannel,
03141                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
03142 {
03143   HRTIM_OutputCfgTypeDef OutputCfg;
03144   HRTIM_EventCfgTypeDef EventCfg;
03145
03146   /* Check parameters */
03147   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03148   assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
03149   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
03150   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
03151   assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
03152   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
03153                                       pSimpleOnePulseChannelCfg->EventPolarity));
03154   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
03155   assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
03156                                     pSimpleOnePulseChannelCfg->EventFilter));
03157
03158   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03159   {
03160      return HAL_BUSY;
03161   }
03162
03163   /* Process Locked */
03164   __HAL_LOCK(hhrtim);
03165
03166   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03167
03168   /* Configure timer compare unit */
03169   switch (OnePulseChannel)
03170   {
03171   case HRTIM_OUTPUT_TA1:
03172   case HRTIM_OUTPUT_TB1:
03173   case HRTIM_OUTPUT_TC1:
03174   case HRTIM_OUTPUT_TD1:
03175   case HRTIM_OUTPUT_TE1:
03176     {
03177       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
03178       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
03179       break;
03180     }
03181
03182   case HRTIM_OUTPUT_TA2:
03183   case HRTIM_OUTPUT_TB2:
03184   case HRTIM_OUTPUT_TC2:
03185   case HRTIM_OUTPUT_TD2:
03186   case HRTIM_OUTPUT_TE2:
03187     {
03188       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
03189       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
03190       break;
03191     }
03192
03193   default:
03194     {
03195       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
03196       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
03197
03198       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03199
03200       /* Process Unlocked */
03201       __HAL_UNLOCK(hhrtim);
03202
03203       break;
03204     }
03205   }
03206
03207   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03208   {
03209      return HAL_ERROR;
03210   }
03211
03212   /* Configure timer output */
03213   OutputCfg.Polarity =  (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
03214   OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
03215   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
03216   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
03217   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
03218   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
03219   OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
03220
03221   HRTIM_OutputConfig(hhrtim,
03222                      TimerIdx,
03223                      OnePulseChannel,
03224                      &OutputCfg);
03225
03226   /* Configure external event channel */
03227   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
03228   EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
03229   EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
03230   EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
03231   EventCfg.Source = HRTIM_EVENTSRC_1;
03232
03233   HRTIM_EventConfig(hhrtim,
03234                     pSimpleOnePulseChannelCfg->Event,
03235                     &EventCfg);
03236
03237   /* Configure the timer reset register */
03238   HRTIM_TIM_ResetConfig(hhrtim,
03239                         TimerIdx,
03240                         pSimpleOnePulseChannelCfg->Event);
03241
03242   hhrtim->State = HAL_HRTIM_STATE_READY;
03243
03244   /* Process Unlocked */
03245   __HAL_UNLOCK(hhrtim);
03246
03247   return HAL_OK;
03248 }
03249
03250 /**
03251   * @brief  Enable the simple one pulse signal generation on the designed output
03252   * @param  hhrtim pointer to HAL HRTIM handle
03253   * @param  TimerIdx Timer index
03254   *                   This parameter can be one of the following values:
03255   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03256   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03257   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03258   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03259   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03260   * @param  OnePulseChannel Timer output
03261   *                    This parameter can be one of the following values:
03262   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03263   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03264   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03265   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03266   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03267   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03268   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03269   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03270   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03271   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03272   * @retval HAL status
03273   */
03274 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
03275                                                 uint32_t TimerIdx,
03276                                                 uint32_t OnePulseChannel)
03277 {
03278   /* Check the parameters */
03279   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03280
03281   /* Process Locked */
03282   __HAL_LOCK(hhrtim);
03283
03284   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03285
03286   /* Enable the timer output */
03287   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03288
03289   /* Enable the timer counter */
03290   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03291
03292   hhrtim->State = HAL_HRTIM_STATE_READY;
03293
03294   /* Process Unlocked */
03295   __HAL_UNLOCK(hhrtim);
03296
03297   return HAL_OK;
03298 }
03299
03300 /**
03301   * @brief  Disable the simple one pulse signal generation on the designed output
03302   * @param  hhrtim pointer to HAL HRTIM handle
03303   * @param  TimerIdx Timer index
03304   *                   This parameter can be one of the following values:
03305   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03306   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03307   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03308   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03309   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03310   * @param  OnePulseChannel Timer output
03311   *                    This parameter can be one of the following values:
03312   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03313   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03314   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03315   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03316   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03317   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03318   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03319   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03320   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03321   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03322   * @retval HAL status
03323   */
03324 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
03325                                               uint32_t TimerIdx,
03326                                               uint32_t OnePulseChannel)
03327 {
03328   /* Check the parameters */
03329   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03330
03331   /* Process Locked */
03332   __HAL_LOCK(hhrtim);
03333
03334   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03335
03336   /* Disable the timer output */
03337   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03338
03339   /* Disable the timer counter */
03340   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03341
03342   hhrtim->State = HAL_HRTIM_STATE_READY;
03343
03344   /* Process Unlocked */
03345   __HAL_UNLOCK(hhrtim);
03346
03347   return HAL_OK;
03348 }
03349
03350 /**
03351   * @brief  Enable the simple one pulse signal generation on the designed output
03352   *         (The compare interrupt is enabled (pulse start)).
03353   * @param  hhrtim pointer to HAL HRTIM handle
03354   * @param  TimerIdx Timer index
03355   *                   This parameter can be one of the following values:
03356   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03357   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03358   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03359   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03360   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03361   * @param  OnePulseChannel Timer output
03362   *                    This parameter can be one of the following values:
03363   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03364   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03365   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03366   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03367   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03368   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03369   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03370   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03371   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03372   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03373   * @retval HAL status
03374   */
03375 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
03376                                                   uint32_t TimerIdx,
03377                                                   uint32_t OnePulseChannel)
03378 {
03379   /* Check the parameters */
03380   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03381
03382   /* Process Locked */
03383   __HAL_LOCK(hhrtim);
03384
03385   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03386
03387   /* Enable the timer output */
03388   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03389
03390   /* Enable the timer interrupt (depends on the OnePulse output) */
03391   switch (OnePulseChannel)
03392   {
03393   case HRTIM_OUTPUT_TA1:
03394   case HRTIM_OUTPUT_TB1:
03395   case HRTIM_OUTPUT_TC1:
03396   case HRTIM_OUTPUT_TD1:
03397   case HRTIM_OUTPUT_TE1:
03398     {
03399       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03400       break;
03401     }
03402
03403   case HRTIM_OUTPUT_TA2:
03404   case HRTIM_OUTPUT_TB2:
03405   case HRTIM_OUTPUT_TC2:
03406   case HRTIM_OUTPUT_TD2:
03407   case HRTIM_OUTPUT_TE2:
03408     {
03409       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03410       break;
03411     }
03412
03413   default:
03414     {
03415       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03416
03417       /* Process Unlocked */
03418       __HAL_UNLOCK(hhrtim);
03419
03420       break;
03421     }
03422   }
03423
03424   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03425   {
03426      return HAL_ERROR;
03427   }
03428
03429   /* Enable the timer counter */
03430   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03431
03432   hhrtim->State = HAL_HRTIM_STATE_READY;
03433
03434   /* Process Unlocked */
03435   __HAL_UNLOCK(hhrtim);
03436
03437   return HAL_OK;
03438 }
03439
03440 /**
03441   * @brief  Disable the simple one pulse signal generation on the designed output
03442   *         (The compare interrupt is disabled).
03443   * @param  hhrtim pointer to HAL HRTIM handle
03444   * @param  TimerIdx Timer index
03445   *                   This parameter can be one of the following values:
03446   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03447   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03448   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03449   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03450   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03451   * @param  OnePulseChannel Timer output
03452   *                    This parameter can be one of the following values:
03453   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03454   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03455   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03456   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03457   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03458   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03459   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03460   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03461   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03462   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03463   * @retval HAL status
03464   */
03465 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
03466                                                  uint32_t TimerIdx,
03467                                                  uint32_t OnePulseChannel)
03468 {
03469   /* Check the parameters */
03470   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03471
03472   /* Process Locked */
03473   __HAL_LOCK(hhrtim);
03474
03475   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03476
03477   /* Disable the timer output */
03478   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03479
03480   /* Disable the timer interrupt (depends on the OnePulse output) */
03481   switch (OnePulseChannel)
03482   {
03483   case HRTIM_OUTPUT_TA1:
03484   case HRTIM_OUTPUT_TB1:
03485   case HRTIM_OUTPUT_TC1:
03486   case HRTIM_OUTPUT_TD1:
03487   case HRTIM_OUTPUT_TE1:
03488     {
03489       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03490       break;
03491     }
03492
03493   case HRTIM_OUTPUT_TA2:
03494   case HRTIM_OUTPUT_TB2:
03495   case HRTIM_OUTPUT_TC2:
03496   case HRTIM_OUTPUT_TD2:
03497   case HRTIM_OUTPUT_TE2:
03498     {
03499       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03500       break;
03501     }
03502
03503   default:
03504     {
03505       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03506
03507       /* Process Unlocked */
03508       __HAL_UNLOCK(hhrtim);
03509
03510       break;
03511     }
03512   }
03513
03514   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03515   {
03516      return HAL_ERROR;
03517   }
03518
03519   /* Disable the timer counter */
03520   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03521
03522   hhrtim->State = HAL_HRTIM_STATE_READY;
03523
03524   /* Process Unlocked */
03525   __HAL_UNLOCK(hhrtim);
03526
03527   return HAL_OK;
03528 }
03529
03530 /**
03531   * @}
03532   */
03533
03534 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
03535  *  @brief    HRTIM configuration functions
03536 @verbatim
03537  ===============================================================================
03538               ##### HRTIM configuration functions #####
03539  ===============================================================================
03540     [..]  This section provides functions allowing to configure the HRTIM
03541           resources shared by all the HRTIM timers operating in waveform mode:
03542       (+) Configure the burst mode controller
03543       (+) Configure an external event conditioning
03544       (+) Configure the external events sampling clock
03545       (+) Configure a fault conditioning
03546       (+) Enable or disable fault inputs
03547       (+) Configure the faults sampling clock
03548       (+) Configure an ADC trigger
03549
03550 @endverbatim
03551   * @{
03552   */
03553
03554 /**
03555   * @brief  Configure the burst mode feature of the HRTIM
03556   * @param  hhrtim pointer to HAL HRTIM handle
03557   * @param  pBurstModeCfg pointer to the burst mode configuration structure
03558   * @retval HAL status
03559   * @note This function must be called before starting the burst mode
03560   *       controller
03561   */
03562 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
03563                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
03564 {
03565   uint32_t hrtim_bmcr;
03566
03567   /* Check parameters */
03568   assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
03569   assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
03570   assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
03571   assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
03572   assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
03573
03574   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03575   {
03576      return HAL_BUSY;
03577   }
03578
03579   /* Process Locked */
03580   __HAL_LOCK(hhrtim);
03581
03582   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03583
03584   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
03585
03586   /* Set the burst mode operating mode */
03587   hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
03588   hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
03589
03590   /* Set the burst mode clock source */
03591   hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
03592   hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
03593
03594   /* Set the burst mode prescaler */
03595   hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
03596   hrtim_bmcr |= pBurstModeCfg->Prescaler;
03597
03598   /* Enable/disable burst mode registers preload */
03599   hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
03600   hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
03601
03602   /* Set the burst mode trigger */
03603   hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
03604
03605   /* Set the burst mode compare value */
03606   hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
03607
03608   /* Set the burst mode period */
03609   hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
03610
03611   /* Update the HRTIM registers */
03612   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
03613
03614   hhrtim->State = HAL_HRTIM_STATE_READY;
03615
03616   /* Process Unlocked */
03617   __HAL_UNLOCK(hhrtim);
03618
03619   return HAL_OK;
03620 }
03621
03622 /**
03623   * @brief  Configure the conditioning of an external event
03624   * @param  hhrtim pointer to HAL HRTIM handle
03625   * @param  Event external event to configure
03626   *                    This parameter can be one of the following values:
03627   *                    @arg HRTIM_EVENT_NONE: no external Event
03628   *                    @arg HRTIM_EVENT_1: External event 1
03629   *                    @arg HRTIM_EVENT_2: External event 2
03630   *                    @arg HRTIM_EVENT_3: External event 3
03631   *                    @arg HRTIM_EVENT_4: External event 4
03632   *                    @arg HRTIM_EVENT_5: External event 5
03633   *                    @arg HRTIM_EVENT_6: External event 6
03634   *                    @arg HRTIM_EVENT_7: External event 7
03635   *                    @arg HRTIM_EVENT_8: External event 8
03636   *                    @arg HRTIM_EVENT_9: External event 9
03637   *                    @arg HRTIM_EVENT_10: External event 10
03638   * @param  pEventCfg pointer to the event conditioning configuration structure
03639   * @note This function must be called before starting the timer
03640   * @retval HAL status
03641   */
03642 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
03643                                         uint32_t Event,
03644                                         HRTIM_EventCfgTypeDef* pEventCfg)
03645 {
03646   /* Check parameters */
03647   assert_param(IS_HRTIM_EVENT(Event));
03648   assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
03649   assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
03650   assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
03651   assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
03652   assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
03653
03654   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03655   {
03656      return HAL_BUSY;
03657   }
03658
03659   /* Process Locked */
03660   __HAL_LOCK(hhrtim);
03661
03662   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03663
03664   /* Configure the event channel */
03665   HRTIM_EventConfig(hhrtim, Event, pEventCfg);
03666
03667   hhrtim->State = HAL_HRTIM_STATE_READY;
03668
03669   /* Process Unlocked */
03670   __HAL_UNLOCK(hhrtim);
03671
03672   return HAL_OK;
03673 }
03674
03675 /**
03676   * @brief  Configure the external event conditioning block prescaler
03677   * @param  hhrtim pointer to HAL HRTIM handle
03678   * @param  Prescaler Prescaler value
03679   *                    This parameter can be one of the following values:
03680   *                    @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
03681   *                    @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
03682   *                    @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
03683   *                    @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
03684   * @note This function must be called before starting the timer
03685   * @retval HAL status
03686   */
03687 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03688                                                  uint32_t Prescaler)
03689 {
03690   /* Check parameters */
03691   assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
03692
03693   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03694   {
03695      return HAL_BUSY;
03696   }
03697
03698   /* Process Locked */
03699   __HAL_LOCK(hhrtim);
03700
03701   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03702
03703   /* Set the external event prescaler */
03704   MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
03705
03706   hhrtim->State = HAL_HRTIM_STATE_READY;
03707
03708   /* Process Unlocked */
03709   __HAL_UNLOCK(hhrtim);
03710
03711   return HAL_OK;
03712 }
03713
03714 /**
03715   * @brief  Configure the conditioning of fault input
03716   * @param  hhrtim pointer to HAL HRTIM handle
03717   * @param  Fault fault input to configure
03718   *                    This parameter can be one of the following values:
03719   *                    @arg HRTIM_FAULT_1: Fault input 1
03720   *                    @arg HRTIM_FAULT_2: Fault input 2
03721   *                    @arg HRTIM_FAULT_3: Fault input 3
03722   *                    @arg HRTIM_FAULT_4: Fault input 4
03723   *                    @arg HRTIM_FAULT_5: Fault input 5
03724   * @param  pFaultCfg pointer to the fault conditioning configuration structure
03725   * @note This function must be called before starting the timer and before
03726   *       enabling faults inputs
03727   * @retval HAL status
03728   */
03729 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
03730                                         uint32_t Fault,
03731                                         HRTIM_FaultCfgTypeDef* pFaultCfg)
03732 {
03733   uint32_t hrtim_fltinr1;
03734   uint32_t hrtim_fltinr2;
03735
03736   /* Check parameters */
03737   assert_param(IS_HRTIM_FAULT(Fault));
03738   assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
03739   assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
03740   assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
03741   assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
03742
03743   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03744   {
03745      return HAL_BUSY;
03746   }
03747
03748   /* Process Locked */
03749   __HAL_LOCK(hhrtim);
03750
03751   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03752
03753   /* Configure fault channel */
03754   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
03755   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03756
03757   switch (Fault)
03758   {
03759   case HRTIM_FAULT_1:
03760     {
03761       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
03762       hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
03763       hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
03764       hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
03765       hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
03766       break;
03767     }
03768
03769   case HRTIM_FAULT_2:
03770     {
03771       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
03772       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
03773       hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
03774       hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
03775       hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
03776       break;
03777     }
03778
03779   case HRTIM_FAULT_3:
03780     {
03781       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
03782       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
03783       hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
03784       hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
03785       hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
03786       break;
03787      }
03788
03789   case HRTIM_FAULT_4:
03790     {
03791       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
03792       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
03793       hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
03794       hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
03795       hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
03796       break;
03797     }
03798
03799   case HRTIM_FAULT_5:
03800     {
03801       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
03802       hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
03803       hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
03804       hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
03805       hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
03806       break;
03807     }
03808
03809   default:
03810     {
03811       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03812
03813       /* Process Unlocked */
03814       __HAL_UNLOCK(hhrtim);
03815
03816       break;
03817     }
03818   }
03819
03820   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03821   {
03822      return HAL_ERROR;
03823   }
03824
03825   /* Update the HRTIM registers except LOCK bit */
03826   hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
03827   hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
03828
03829   /* Update the HRTIM registers LOCK bit */
03830   SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
03831   SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
03832
03833   hhrtim->State = HAL_HRTIM_STATE_READY;
03834
03835   /* Process Unlocked */
03836   __HAL_UNLOCK(hhrtim);
03837
03838   return HAL_OK;
03839 }
03840
03841 /**
03842   * @brief  Configure the fault conditioning block prescaler
03843   * @param  hhrtim pointer to HAL HRTIM handle
03844   * @param  Prescaler Prescaler value
03845   *                    This parameter can be one of the following values:
03846   *                    @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
03847   *                    @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
03848   *                    @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
03849   *                    @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
03850   * @retval HAL status
03851   * @note This function must be called before starting the timer and before
03852   *       enabling faults inputs
03853   */
03854 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03855                                                  uint32_t Prescaler)
03856 {
03857   /* Check parameters */
03858   assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
03859
03860   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03861   {
03862      return HAL_BUSY;
03863   }
03864
03865   /* Process Locked */
03866   __HAL_LOCK(hhrtim);
03867
03868   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03869
03870   /* Set the external event prescaler */
03871   MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
03872
03873   hhrtim->State = HAL_HRTIM_STATE_READY;
03874
03875   /* Process Unlocked */
03876   __HAL_UNLOCK(hhrtim);
03877
03878   return HAL_OK;
03879 }
03880
03881 /**
03882   * @brief  Enable or disables the HRTIMx Fault mode.
03883   * @param  hhrtim pointer to HAL HRTIM handle
03884   * @param  Faults fault input(s) to enable or disable
03885   *                   This parameter can be any combination of the following values:
03886   *                    @arg HRTIM_FAULT_1: Fault input 1
03887   *                    @arg HRTIM_FAULT_2: Fault input 2
03888   *                    @arg HRTIM_FAULT_3: Fault input 3
03889   *                    @arg HRTIM_FAULT_4: Fault input 4
03890   *                    @arg HRTIM_FAULT_5: Fault input 5
03891   * @param  Enable Fault(s) enabling
03892   *                    This parameter can be one of the following values:
03893   *                    @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
03894   *                    @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
03895   * @retval None
03896   */
03897 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03898                         uint32_t Faults,
03899                         uint32_t Enable)
03900 {
03901   /* Check parameters */
03902   assert_param(IS_HRTIM_FAULT(Faults));
03903   assert_param(IS_HRTIM_FAULTMODECTL(Enable));
03904
03905   if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
03906   {
03907     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
03908   }
03909   if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
03910   {
03911     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
03912   }
03913   if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
03914   {
03915     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
03916   }
03917   if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
03918   {
03919     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
03920   }
03921   if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
03922   {
03923     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
03924   }
03925 }
03926
03927 /**
03928   * @brief  Configure both the ADC trigger register update source and the ADC
03929   *         trigger source.
03930   * @param  hhrtim pointer to HAL HRTIM handle
03931   * @param  ADCTrigger ADC trigger to configure
03932   *                    This parameter can be one of the following values:
03933   *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
03934   *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
03935   *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
03936   *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
03937   * @param  pADCTriggerCfg pointer to the ADC trigger configuration structure
03938   * @retval HAL status
03939   * @note This function must be called before starting the timer
03940   */
03941 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
03942                                              uint32_t ADCTrigger,
03943                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
03944 {
03945   uint32_t hrtim_cr1;
03946
03947   /* Check parameters */
03948   assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
03949   assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
03950
03951   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03952   {
03953      return HAL_BUSY;
03954   }
03955
03956   /* Process Locked */
03957   __HAL_LOCK(hhrtim);
03958
03959   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03960
03961   /* Set the ADC trigger update source */
03962   hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
03963
03964   switch (ADCTrigger)
03965   {
03966   case HRTIM_ADCTRIGGER_1:
03967     {
03968       hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
03969       hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
03970
03971       /* Set the ADC trigger 1 source */
03972       hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
03973       break;
03974     }
03975
03976   case HRTIM_ADCTRIGGER_2:
03977     {
03978       hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
03979       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
03980
03981       /* Set the ADC trigger 2 source */
03982       hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
03983       break;
03984     }
03985
03986   case HRTIM_ADCTRIGGER_3:
03987     {
03988       hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
03989       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
03990
03991       /* Set the ADC trigger 3 source */
03992       hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
03993       break;
03994     }
03995
03996   case HRTIM_ADCTRIGGER_4:
03997     {
03998       hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
03999       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
04000
04001       /* Set the ADC trigger 4 source */
04002       hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
04003       break;
04004     }
04005
04006   default:
04007     {
04008       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04009
04010       /* Process Unlocked */
04011       __HAL_UNLOCK(hhrtim);
04012
04013       break;
04014     }
04015   }
04016
04017   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04018   {
04019      return HAL_ERROR;
04020   }
04021
04022   /* Update the HRTIM registers */
04023   hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
04024
04025   hhrtim->State = HAL_HRTIM_STATE_READY;
04026
04027   /* Process Unlocked */
04028   __HAL_UNLOCK(hhrtim);
04029
04030   return HAL_OK;
04031 }
04032
04033
04034 /**
04035   * @}
04036   */
04037
04038 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
04039  *  @brief    HRTIM timer configuration and control functions
04040 @verbatim
04041  ===============================================================================
04042               ##### HRTIM timer configuration and control functions #####
04043  ===============================================================================
04044     [..]  This section provides functions used to configure and control a
04045           HRTIM timer operating in waveform mode:
04046       (+) Configure HRTIM timer general behavior
04047       (+) Configure HRTIM timer event filtering
04048       (+) Configure HRTIM timer deadtime insertion
04049       (+) Configure HRTIM timer chopper mode
04050       (+) Configure HRTIM timer burst DMA
04051       (+) Configure HRTIM timer compare unit
04052       (+) Configure HRTIM timer capture unit
04053       (+) Configure HRTIM timer output
04054       (+) Set HRTIM timer output level
04055       (+) Enable HRTIM timer output
04056       (+) Disable HRTIM timer output
04057       (+) Start HRTIM timer
04058       (+) Stop HRTIM timer
04059       (+) Start HRTIM timer and enable interrupt
04060       (+) Stop HRTIM timer and disable interrupt
04061       (+) Start HRTIM timer and enable DMA transfer
04062       (+) Stop HRTIM timer and disable DMA transfer
04063       (+) Enable or disable the burst mode controller
04064       (+) Start the burst mode controller (by software)
04065       (+) Trigger a Capture (by software)
04066       (+) Update the HRTIM timer preloadable registers (by software)
04067       (+) Reset the HRTIM timer counter (by software)
04068       (+) Start a burst DMA transfer
04069       (+) Enable timer register update
04070       (+) Disable timer register update
04071
04072 @endverbatim
04073   * @{
04074   */
04075
04076 /**
04077   * @brief  Configure the general behavior of a timer operating in waveform mode
04078   * @param  hhrtim pointer to HAL HRTIM handle
04079   * @param  TimerIdx Timer index
04080   *                   This parameter can be one of the following values:
04081   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04082   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04083   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04084   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04085   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04086   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04087   * @param  pTimerCfg pointer to the timer configuration structure
04088   * @note When the timer operates in waveform mode, all the features supported by
04089   *       the HRTIM are available without any limitation.
04090   * @retval HAL status
04091   * @note This function must be called before starting the timer
04092   */
04093 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
04094                                                 uint32_t TimerIdx,
04095                                                 HRTIM_TimerCfgTypeDef * pTimerCfg)
04096 {
04097   /* Check parameters */
04098   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
04099
04100   /* Relevant for all HRTIM timers, including the master */
04101   assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
04102   assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
04103   assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
04104   assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
04105   assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
04106   assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
04107   assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
04108
04109   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04110   {
04111      return HAL_BUSY;
04112   }
04113
04114   /* Process Locked */
04115   __HAL_LOCK(hhrtim);
04116
04117   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04118
04119   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
04120   {
04121     /* Check parameters */
04122     assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
04123     assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
04124     assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
04125
04126     /* Configure master timer */
04127     HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
04128   }
04129   else
04130   {
04131     /* Check parameters */
04132     assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
04133     assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
04134     assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
04135     assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
04136     assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
04137     assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
04138     assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
04139                                                pTimerCfg->DeadTimeInsertion));
04140     assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
04141                                                pTimerCfg->DelayedProtectionMode));
04142     assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
04143     assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
04144     assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
04145
04146     /* Configure timing unit */
04147     HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
04148   }
04149
04150   /* Update timer parameters */
04151   hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
04152   hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
04153   hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
04154   hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
04155   hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
04156
04157   /* Force a software update */
04158   HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
04159
04160   hhrtim->State = HAL_HRTIM_STATE_READY;
04161
04162   /* Process Unlocked */
04163   __HAL_UNLOCK(hhrtim);
04164
04165   return HAL_OK;
04166 }
04167
04168 /**
04169   * @brief  Configure the event filtering capabilities of a timer (blanking, windowing)
04170   * @param  hhrtim pointer to HAL HRTIM handle
04171   * @param  TimerIdx Timer index
04172   *                   This parameter can be one of the following values:
04173   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04174   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04175   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04176   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04177   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04178   * @param  Event external event for which timer event filtering must be configured
04179   *                    This parameter can be one of the following values:
04180   *                    @arg HRTIM_EVENT_1: External event 1
04181   *                    @arg HRTIM_EVENT_2: External event 2
04182   *                    @arg HRTIM_EVENT_3: External event 3
04183   *                    @arg HRTIM_EVENT_4: External event 4
04184   *                    @arg HRTIM_EVENT_5: External event 5
04185   *                    @arg HRTIM_EVENT_6: External event 6
04186   *                    @arg HRTIM_EVENT_7: External event 7
04187   *                    @arg HRTIM_EVENT_8: External event 8
04188   *                    @arg HRTIM_EVENT_9: External event 9
04189   *                    @arg HRTIM_EVENT_10: External event 10
04190   * @param  pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
04191   * @note This function must be called before starting the timer
04192   * @retval HAL status
04193   */
04194 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
04195                                                       uint32_t TimerIdx,
04196                                                       uint32_t Event,
04197                                                       HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
04198 {
04199   /* Check parameters */
04200   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04201   assert_param(IS_HRTIM_EVENT(Event));
04202   assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
04203
04204   assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
04205
04206   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04207   {
04208      return HAL_BUSY;
04209   }
04210
04211   /* Process Locked */
04212   __HAL_LOCK(hhrtim);
04213
04214   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04215
04216   /* Configure timer event filtering capabilities */
04217   switch (Event)
04218   {
04219   case HRTIM_EVENT_NONE:
04220     {
04221       CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
04222       CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
04223       break;
04224     }
04225
04226   case HRTIM_EVENT_1:
04227     {
04228       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
04229       break;
04230     }
04231
04232   case HRTIM_EVENT_2:
04233     {
04234       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
04235       break;
04236     }
04237
04238   case HRTIM_EVENT_3:
04239     {
04240       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
04241       break;
04242     }
04243
04244   case HRTIM_EVENT_4:
04245     {
04246       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
04247       break;
04248     }
04249
04250   case HRTIM_EVENT_5:
04251     {
04252       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
04253       break;
04254     }
04255
04256   case HRTIM_EVENT_6:
04257     {
04258       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
04259       break;
04260     }
04261
04262   case HRTIM_EVENT_7:
04263     {
04264       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
04265       break;
04266     }
04267
04268   case HRTIM_EVENT_8:
04269     {
04270       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
04271       break;
04272     }
04273
04274   case HRTIM_EVENT_9:
04275     {
04276       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
04277       break;
04278     }
04279
04280   case HRTIM_EVENT_10:
04281     {
04282       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
04283       break;
04284     }
04285
04286   default:
04287    {
04288       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04289
04290       /* Process Unlocked */
04291       __HAL_UNLOCK(hhrtim);
04292
04293       break;
04294     }
04295   }
04296
04297   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04298   {
04299      return HAL_ERROR;
04300   }
04301
04302   hhrtim->State = HAL_HRTIM_STATE_READY;
04303
04304   /* Process Unlocked */
04305   __HAL_UNLOCK(hhrtim);
04306
04307   return HAL_OK;
04308 }
04309
04310 /**
04311   * @brief  Configure the dead-time insertion feature for a timer
04312   * @param  hhrtim pointer to HAL HRTIM handle
04313   * @param  TimerIdx Timer index
04314   *                   This parameter can be one of the following values:
04315   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04316   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04317   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04318   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04319   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04320   * @param  pDeadTimeCfg pointer to the deadtime insertion configuration structure
04321   * @retval HAL status
04322   * @note This function must be called before starting the timer
04323   */
04324 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
04325                                            uint32_t TimerIdx,
04326                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
04327 {
04328   uint32_t hrtim_dtr;
04329
04330   /* Check parameters */
04331   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04332   assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
04333   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
04334   assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
04335   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
04336   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
04337   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
04338   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
04339
04340   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04341   {
04342      return HAL_BUSY;
04343   }
04344
04345   /* Process Locked */
04346   __HAL_LOCK(hhrtim);
04347
04348   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04349
04350   /* Set timer deadtime configuration */
04351   hrtim_dtr  = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
04352   hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
04353   hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
04354   hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
04355   hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
04356   hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
04357   hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
04358   hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
04359   hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
04360
04361   /* Update the HRTIM registers */
04362   MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
04363                  HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
04364                  HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
04365                  HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
04366
04367   hhrtim->State = HAL_HRTIM_STATE_READY;
04368
04369   /* Process Unlocked */
04370   __HAL_UNLOCK(hhrtim);
04371
04372   return HAL_OK;
04373 }
04374
04375 /**
04376   * @brief  Configure the chopper mode feature for a timer
04377   * @param  hhrtim pointer to HAL HRTIM handle
04378   * @param  TimerIdx Timer index
04379   *                   This parameter can be one of the following values:
04380   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04381   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04382   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04383   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04384   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04385   * @param  pChopperModeCfg pointer to the chopper mode configuration structure
04386   * @retval HAL status
04387   * @note This function must be called before configuring the timer output(s)
04388   */
04389 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
04390                                               uint32_t TimerIdx,
04391                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
04392 {
04393   uint32_t hrtim_chpr;
04394
04395   /* Check parameters */
04396   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04397   assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
04398   assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
04399   assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
04400
04401   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04402   {
04403      return HAL_BUSY;
04404   }
04405
04406   /* Process Locked */
04407   __HAL_LOCK(hhrtim);
04408
04409   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04410
04411   /* Set timer choppe mode configuration */
04412   hrtim_chpr  = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
04413   hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
04414   hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
04415
04416   /* Update the HRTIM registers */
04417   MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ |                                                           HRTIM_CHPR_CARDTY |
04418                                                              HRTIM_CHPR_STRPW) ,
04419                                                              hrtim_chpr);
04420
04421   hhrtim->State = HAL_HRTIM_STATE_READY;
04422
04423   /* Process Unlocked */
04424   __HAL_UNLOCK(hhrtim);
04425
04426   return HAL_OK;
04427 }
04428
04429 /**
04430   * @brief  Configure the burst DMA controller for a timer
04431   * @param  hhrtim pointer to HAL HRTIM handle
04432   * @param  TimerIdx Timer index
04433   *                  This parameter can be one of the following values:
04434   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04435   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04436   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04437   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04438   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04439   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04440   * @param  RegistersToUpdate registers to be written by DMA
04441   *                    This parameter can be any combination of the following values:
04442   *                    @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
04443   *                    @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
04444   *                    @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
04445   *                    @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
04446   *                    @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
04447   *                    @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
04448   *                    @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
04449   *                    @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
04450   *                    @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
04451   *                    @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
04452   *                    @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
04453   *                    @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
04454   *                    @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
04455   *                    @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
04456   *                    @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
04457   *                    @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
04458   *                    @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
04459   *                    @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
04460   *                    @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
04461   *                    @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
04462   *                    @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
04463   * @retval HAL status
04464   * @note This function must be called before starting the timer
04465   */
04466 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
04467                                            uint32_t TimerIdx,
04468                                            uint32_t RegistersToUpdate)
04469 {
04470   /* Check parameters */
04471   assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
04472
04473   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04474   {
04475      return HAL_BUSY;
04476   }
04477
04478   /* Process Locked */
04479   __HAL_LOCK(hhrtim);
04480
04481   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04482
04483   /* Set the burst DMA timer update register */
04484   switch (TimerIdx)
04485   {
04486   case HRTIM_TIMERINDEX_TIMER_A:
04487     {
04488       hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
04489       break;
04490     }
04491
04492   case HRTIM_TIMERINDEX_TIMER_B:
04493     {
04494       hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
04495       break;
04496     }
04497
04498   case HRTIM_TIMERINDEX_TIMER_C:
04499     {
04500       hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
04501       break;
04502     }
04503
04504   case HRTIM_TIMERINDEX_TIMER_D:
04505     {
04506       hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
04507       break;
04508     }
04509
04510   case HRTIM_TIMERINDEX_TIMER_E:
04511     {
04512       hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
04513       break;
04514     }
04515
04516   case HRTIM_TIMERINDEX_MASTER:
04517     {
04518       hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
04519       break;
04520     }
04521
04522   default:
04523    {
04524       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04525
04526       /* Process Unlocked */
04527       __HAL_UNLOCK(hhrtim);
04528
04529       break;
04530     }
04531   }
04532
04533   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04534   {
04535      return HAL_ERROR;
04536   }
04537
04538   hhrtim->State = HAL_HRTIM_STATE_READY;
04539
04540   /* Process Unlocked */
04541   __HAL_UNLOCK(hhrtim);
04542
04543   return HAL_OK;
04544 }
04545
04546 /**
04547   * @brief  Configure the compare unit of a timer operating in waveform mode
04548   * @param  hhrtim pointer to HAL HRTIM handle
04549   * @param  TimerIdx Timer index
04550   *                   This parameter can be one of the following values:
04551   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04552   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04553   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04554   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04555   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04556   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04557   * @param  CompareUnit Compare unit to configure
04558   *                    This parameter can be one of the following values:
04559   *                    @arg HRTIM_COMPAREUNIT_1: Compare unit 1
04560   *                    @arg HRTIM_COMPAREUNIT_2: Compare unit 2
04561   *                    @arg HRTIM_COMPAREUNIT_3: Compare unit 3
04562   *                    @arg HRTIM_COMPAREUNIT_4: Compare unit 4
04563   * @param  pCompareCfg pointer to the compare unit configuration structure
04564   * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
04565   *       application has to configure separately the capture unit. Capture unit
04566   *       to configure in that case depends on the compare unit auto delayed mode
04567   *       is applied to (see below):
04568   *         Auto delayed on output compare 2: capture unit 1 must be configured
04569   *         Auto delayed on output compare 4: capture unit 2 must be configured
04570   * @retval HAL status
04571   * @note This function must be called before starting the timer
04572   */
04573 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
04574                                                   uint32_t TimerIdx,
04575                                                   uint32_t CompareUnit,
04576                                                   HRTIM_CompareCfgTypeDef* pCompareCfg)
04577 {
04578   /* Check parameters */
04579   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
04580
04581   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04582   {
04583      return HAL_BUSY;
04584   }
04585
04586   /* Process Locked */
04587   __HAL_LOCK(hhrtim);
04588
04589   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04590
04591   /* Configure the compare unit */
04592   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
04593   {
04594     switch (CompareUnit)
04595     {
04596       case HRTIM_COMPAREUNIT_1:
04597         {
04598         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
04599         break;
04600         }
04601
04602       case HRTIM_COMPAREUNIT_2:
04603         {
04604         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
04605         break;
04606         }
04607
04608       case HRTIM_COMPAREUNIT_3:
04609         {
04610         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
04611         break;
04612         }
04613
04614       case HRTIM_COMPAREUNIT_4:
04615         {
04616         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
04617         break;
04618         }
04619
04620       default:
04621         {
04622         hhrtim->State = HAL_HRTIM_STATE_ERROR;
04623
04624         /* Process Unlocked */
04625         __HAL_UNLOCK(hhrtim);
04626
04627         break;
04628         }
04629     }
04630
04631     if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04632     {
04633      return HAL_ERROR;
04634     }
04635
04636   }
04637   else
04638   {
04639     switch (CompareUnit)
04640     {
04641     case HRTIM_COMPAREUNIT_1:
04642       {
04643         /* Set the compare value */
04644         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
04645         break;
04646       }
04647
04648     case HRTIM_COMPAREUNIT_2:
04649       {
04650         /* Check parameters */
04651         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04652
04653         /* Set the compare value */
04654         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
04655
04656         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04657         {
04658           /* Configure auto-delayed mode */
04659           /* DELCMP2 bitfield must be reset when reprogrammed from one value */
04660           /* to the other to reinitialize properly the auto-delayed mechanism */
04661           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
04662           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
04663
04664           /* Set the compare value for timeout compare unit (if any) */
04665           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04666           {
04667             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04668           }
04669           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04670           {
04671             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04672           }
04673           else
04674           {
04675             /* nothing to do */
04676           }
04677         }
04678         else
04679         {
04680           /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
04681           MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
04682         }
04683          break;
04684       }
04685
04686     case HRTIM_COMPAREUNIT_3:
04687       {
04688         /* Set the compare value */
04689         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
04690         break;
04691       }
04692
04693     case HRTIM_COMPAREUNIT_4:
04694       {
04695         /* Check parameters */
04696         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04697
04698         /* Set the compare value */
04699         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
04700
04701         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04702         {
04703           /* Configure auto-delayed mode */
04704           /* DELCMP4 bitfield must be reset when reprogrammed from one value */
04705           /* to the other to reinitialize properly the auto-delayed mechanism */
04706           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
04707           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
04708
04709           /* Set the compare value for timeout compare unit (if any) */
04710           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04711           {
04712             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04713           }
04714           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04715           {
04716             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04717           }
04718           else
04719           {
04720             /* nothing to do */
04721           }
04722         }
04723         else
04724         {
04725           /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
04726           MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
04727         }
04728          break;
04729       }
04730
04731   default:
04732      {
04733       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04734
04735       /* Process Unlocked */
04736       __HAL_UNLOCK(hhrtim);
04737
04738       break;
04739      }
04740    }
04741
04742    if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04743    {
04744      return HAL_ERROR;
04745    }
04746
04747   }
04748   hhrtim->State = HAL_HRTIM_STATE_READY;
04749
04750   /* Process Unlocked */
04751   __HAL_UNLOCK(hhrtim);
04752
04753   return HAL_OK;
04754 }
04755
04756 /**
04757   * @brief  Configure the capture unit of a timer operating in waveform mode
04758   * @param  hhrtim pointer to HAL HRTIM handle
04759   * @param  TimerIdx Timer index
04760   *                   This parameter can be one of the following values:
04761   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04762   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04763   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04764   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04765   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04766   * @param  CaptureUnit Capture unit to configure
04767   *                    This parameter can be one of the following values:
04768   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
04769   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
04770   * @param  pCaptureCfg pointer to the compare unit configuration structure
04771   * @retval HAL status
04772   * @note This function must be called before starting the timer
04773   */
04774 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
04775                                                   uint32_t TimerIdx,
04776                                                   uint32_t CaptureUnit,
04777                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg)
04778 {
04779   /* Check parameters */
04780   assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
04781
04782
04783   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04784   {
04785      return HAL_BUSY;
04786   }
04787
04788   /* Process Locked */
04789   __HAL_LOCK(hhrtim);
04790
04791   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04792
04793   /* Configure the capture unit */
04794   switch (CaptureUnit)
04795   {
04796   case HRTIM_CAPTUREUNIT_1:
04797     {
04798       WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
04799       break;
04800     }
04801
04802   case HRTIM_CAPTUREUNIT_2:
04803     {
04804       WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
04805       break;
04806     }
04807
04808   default:
04809     {
04810       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04811
04812       /* Process Unlocked */
04813       __HAL_UNLOCK(hhrtim);
04814
04815       break;
04816     }
04817   }
04818
04819   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04820   {
04821      return HAL_ERROR;
04822   }
04823
04824
04825   hhrtim->State = HAL_HRTIM_STATE_READY;
04826
04827   /* Process Unlocked */
04828   __HAL_UNLOCK(hhrtim);
04829
04830   return HAL_OK;
04831 }
04832
04833 /**
04834   * @brief  Configure the output of a timer operating in waveform mode
04835   * @param  hhrtim pointer to HAL HRTIM handle
04836   * @param  TimerIdx Timer index
04837   *                   This parameter can be one of the following values:
04838   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04839   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04840   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04841   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04842   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04843   * @param  Output Timer output
04844   *                    This parameter can be one of the following values:
04845   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04846   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04847   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04848   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04849   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04850   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04851   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04852   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04853   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04854   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04855   * @param  pOutputCfg pointer to the timer output configuration structure
04856   * @retval HAL status
04857   * @note This function must be called before configuring the timer and after
04858   *       configuring the deadtime insertion feature (if required).
04859   */
04860 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
04861                                                 uint32_t TimerIdx,
04862                                                 uint32_t Output,
04863                                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
04864 {
04865   /* Check parameters */
04866   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04867   assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
04868   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
04869   assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
04870   assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
04871   assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
04872   assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
04873
04874   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04875   {
04876      return HAL_BUSY;
04877   }
04878
04879   /* Process Locked */
04880   __HAL_LOCK(hhrtim);
04881
04882   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04883
04884   /* Configure the timer output */
04885   HRTIM_OutputConfig(hhrtim,
04886                      TimerIdx,
04887                      Output,
04888                      pOutputCfg);
04889
04890   hhrtim->State = HAL_HRTIM_STATE_READY;
04891
04892   /* Process Unlocked */
04893   __HAL_UNLOCK(hhrtim);
04894
04895   return HAL_OK;
04896 }
04897
04898 /**
04899   * @brief  Force the timer output to its active or inactive state
04900   * @param  hhrtim pointer to HAL HRTIM handle
04901   * @param  TimerIdx Timer index
04902   *                   This parameter can be one of the following values:
04903   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04904   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04905   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04906   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04907   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04908   * @param  Output Timer output
04909   *                    This parameter can be one of the following values:
04910   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04911   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04912   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04913   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04914   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04915   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04916   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04917   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04918   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04919   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04920   * @param OutputLevel indicates whether the output is forced to its active or inactive level
04921   *                    This parameter can be one of the following values:
04922   *                    @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
04923   *                    @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
04924   * @retval HAL status
04925   * @note The 'software set/reset trigger' bit in the output set/reset registers
04926   *       is automatically reset by hardware
04927   */
04928 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
04929                                                    uint32_t TimerIdx,
04930                                                    uint32_t Output,
04931                                                    uint32_t OutputLevel)
04932 {
04933   /* Check parameters */
04934   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04935   assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
04936
04937   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04938   {
04939      return HAL_BUSY;
04940   }
04941
04942   /* Process Locked */
04943   __HAL_LOCK(hhrtim);
04944
04945   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04946
04947   /* Force timer output level */
04948   switch (Output)
04949   {
04950   case HRTIM_OUTPUT_TA1:
04951   case HRTIM_OUTPUT_TB1:
04952   case HRTIM_OUTPUT_TC1:
04953   case HRTIM_OUTPUT_TD1:
04954   case HRTIM_OUTPUT_TE1:
04955     {
04956       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04957       {
04958         /* Force output to its active state */
04959         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
04960       }
04961       else
04962       {
04963         /* Force output to its inactive state */
04964         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
04965       }
04966       break;
04967     }
04968
04969   case HRTIM_OUTPUT_TA2:
04970   case HRTIM_OUTPUT_TB2:
04971   case HRTIM_OUTPUT_TC2:
04972   case HRTIM_OUTPUT_TD2:
04973   case HRTIM_OUTPUT_TE2:
04974     {
04975       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04976       {
04977         /* Force output to its active state */
04978         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
04979       }
04980       else
04981       {
04982         /* Force output to its inactive state */
04983         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
04984       }
04985       break;
04986     }
04987
04988   default:
04989     {
04990       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04991
04992       /* Process Unlocked */
04993       __HAL_UNLOCK(hhrtim);
04994
04995       break;
04996     }
04997   }
04998
04999   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05000   {
05001      return HAL_ERROR;
05002   }
05003
05004   hhrtim->State = HAL_HRTIM_STATE_READY;
05005
05006   /* Process Unlocked */
05007   __HAL_UNLOCK(hhrtim);
05008
05009   return HAL_OK;
05010 }
05011
05012 /**
05013   * @brief  Enable the generation of the waveform signal on the designated output(s)
05014   *         Outputs can be combined (ORed) to allow for simultaneous output enabling.
05015   * @param  hhrtim pointer to HAL HRTIM handle
05016   * @param  OutputsToStart Timer output(s) to enable
05017   *                    This parameter can be any combination of the following values:
05018   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05019   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05020   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05021   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05022   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05023   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05024   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05025   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05026   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05027   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05028   * @retval HAL status
05029   */
05030 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
05031                                                 uint32_t OutputsToStart)
05032 {
05033    /* Check the parameters */
05034   assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
05035
05036   /* Process Locked */
05037   __HAL_LOCK(hhrtim);
05038
05039   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05040
05041   /* Enable the HRTIM outputs */
05042   hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
05043
05044   hhrtim->State = HAL_HRTIM_STATE_READY;
05045
05046   /* Process Unlocked */
05047   __HAL_UNLOCK(hhrtim);
05048
05049   return HAL_OK;
05050 }
05051
05052 /**
05053   * @brief  Disable the generation of the waveform signal on the designated output(s)
05054   *         Outputs can be combined (ORed) to allow for simultaneous output disabling.
05055   * @param  hhrtim pointer to HAL HRTIM handle
05056   * @param  OutputsToStop Timer output(s) to disable
05057   *                    This parameter can be any combination of the following values:
05058   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05059   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05060   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05061   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05062   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05063   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05064   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05065   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05066   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05067   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05068   * @retval HAL status
05069   */
05070 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
05071                                                uint32_t OutputsToStop)
05072 {
05073    /* Check the parameters */
05074   assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
05075
05076   /* Process Locked */
05077   __HAL_LOCK(hhrtim);
05078
05079   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05080
05081   /* Enable the HRTIM outputs */
05082   hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
05083
05084   hhrtim->State = HAL_HRTIM_STATE_READY;
05085
05086   /* Process Unlocked */
05087   __HAL_UNLOCK(hhrtim);
05088
05089   return HAL_OK;
05090 }
05091
05092 /**
05093   * @brief  Start the counter of the designated timer(s) operating in waveform mode
05094   *         Timers can be combined (ORed) to allow for simultaneous counter start.
05095   * @param  hhrtim pointer to HAL HRTIM handle
05096   * @param  Timers Timer counter(s) to start
05097   *                   This parameter can be any combination of the following values:
05098   *                   @arg HRTIM_TIMERID_MASTER
05099   *                   @arg HRTIM_TIMERID_TIMER_A
05100   *                   @arg HRTIM_TIMERID_TIMER_B
05101   *                   @arg HRTIM_TIMERID_TIMER_C
05102   *                   @arg HRTIM_TIMERID_TIMER_D
05103   *                   @arg HRTIM_TIMERID_TIMER_E
05104   * @retval HAL status
05105   */
05106 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
05107                                                  uint32_t Timers)
05108 {
05109   /* Check the parameters */
05110   assert_param(IS_HRTIM_TIMERID(Timers));
05111
05112   /* Process Locked */
05113   __HAL_LOCK(hhrtim);
05114
05115   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05116
05117   /* Enable timer(s) counter */
05118   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
05119
05120   hhrtim->State = HAL_HRTIM_STATE_READY;
05121
05122   /* Process Unlocked */
05123   __HAL_UNLOCK(hhrtim);
05124
05125   return HAL_OK;
05126 }
05127
05128 /**
05129   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
05130   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
05131   * @param  hhrtim pointer to HAL HRTIM handle
05132   * @param  Timers Timer counter(s) to stop
05133   *                   This parameter can be any combination of the following values:
05134   *                   @arg HRTIM_TIMERID_MASTER
05135   *                   @arg HRTIM_TIMERID_A
05136   *                   @arg HRTIM_TIMERID_B
05137   *                   @arg HRTIM_TIMERID_C
05138   *                   @arg HRTIM_TIMERID_D
05139   *                   @arg HRTIM_TIMERID_E
05140   * @retval HAL status
05141   * @note The counter of a timer is stopped only if all timer outputs are disabled
05142   */
05143 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
05144                                                 uint32_t Timers)
05145 {
05146   /* Check the parameters */
05147   assert_param(IS_HRTIM_TIMERID(Timers));
05148
05149   /* Process Locked */
05150   __HAL_LOCK(hhrtim);
05151
05152   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05153
05154   /* Disable timer(s) counter */
05155   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
05156
05157   hhrtim->State = HAL_HRTIM_STATE_READY;
05158
05159   /* Process Unlocked */
05160   __HAL_UNLOCK(hhrtim);
05161
05162   return HAL_OK;
05163 }
05164
05165 /**
05166   * @brief  Start the counter of the designated timer(s) operating in waveform mode
05167   *         Timers can be combined (ORed) to allow for simultaneous counter start.
05168   * @param  hhrtim pointer to HAL HRTIM handle
05169   * @param  Timers Timer counter(s) to start
05170   *                   This parameter can be any combination of the following values:
05171   *                   @arg HRTIM_TIMERID_MASTER
05172   *                   @arg HRTIM_TIMERID_A
05173   *                   @arg HRTIM_TIMERID_B
05174   *                   @arg HRTIM_TIMERID_C
05175   *                   @arg HRTIM_TIMERID_D
05176   *                   @arg HRTIM_TIMERID_E
05177   * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
05178   *       to the timers to start are enabled within this function.
05179   *       Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
05180   *       function.
05181   * @retval HAL status
05182   */
05183 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
05184                                                     uint32_t Timers)
05185 {
05186   uint8_t timer_idx;
05187
05188   /* Check the parameters */
05189   assert_param(IS_HRTIM_TIMERID(Timers));
05190
05191   /* Process Locked */
05192   __HAL_LOCK(hhrtim);
05193
05194   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05195
05196   /* Enable HRTIM interrupts (if required) */
05197   __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
05198
05199   /* Enable master timer related interrupts (if required) */
05200   if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
05201   {
05202     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
05203                                  hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
05204   }
05205
05206   /* Enable timing unit related interrupts (if required) */
05207   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05208        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05209        timer_idx++)
05210   {
05211     if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
05212     {
05213       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
05214                                   timer_idx,
05215                                   hhrtim->TimerParam[timer_idx].InterruptRequests);
05216     }
05217   }
05218
05219   /* Enable timer(s) counter */
05220   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
05221
05222   hhrtim->State = HAL_HRTIM_STATE_READY;
05223
05224   /* Process Unlocked */
05225   __HAL_UNLOCK(hhrtim);
05226
05227   return HAL_OK;}
05228
05229 /**
05230   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
05231   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
05232   * @param  hhrtim pointer to HAL HRTIM handle
05233   * @param  Timers Timer counter(s) to stop
05234   *                   This parameter can be any combination of the following values:
05235   *                   @arg HRTIM_TIMERID_MASTER
05236   *                   @arg HRTIM_TIMERID_A
05237   *                   @arg HRTIM_TIMERID_B
05238   *                   @arg HRTIM_TIMERID_C
05239   *                   @arg HRTIM_TIMERID_D
05240   *                   @arg HRTIM_TIMERID_E
05241   * @retval HAL status
05242   * @note The counter of a timer is stopped only if all timer outputs are disabled
05243   * @note All enabled timer related interrupts are disabled.
05244   */
05245 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
05246                                                    uint32_t Timers)
05247 {
05248   /* ++ WA */
05249   __IO uint32_t delai = (uint32_t)(0x17FU);
05250   /* -- WA */
05251
05252   uint8_t timer_idx;
05253
05254   /* Check the parameters */
05255   assert_param(IS_HRTIM_TIMERID(Timers));
05256
05257   /* Process Locked */
05258   __HAL_LOCK(hhrtim);
05259
05260   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05261
05262   /* Disable HRTIM interrupts (if required) */
05263   __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
05264
05265   /* Disable master timer related interrupts (if required) */
05266   if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
05267   {
05268     /* Interrupts enable flag must be cleared one by one */
05269     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
05270   }
05271
05272   /* Disable timing unit related interrupts (if required) */
05273   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05274        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05275        timer_idx++)
05276   {
05277     if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
05278     {
05279       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
05280     }
05281   }
05282
05283   /* ++ WA */
05284   do { delai--; } while (delai != 0U);
05285   /* -- WA */
05286
05287   /* Disable timer(s) counter */
05288   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
05289
05290   hhrtim->State = HAL_HRTIM_STATE_READY;
05291
05292   /* Process Unlocked */
05293   __HAL_UNLOCK(hhrtim);
05294
05295   return HAL_OK;
05296 }
05297
05298 /**
05299   * @brief  Start the counter of the designated timer(s) operating in waveform mode
05300   *         Timers can be combined (ORed) to allow for simultaneous counter start.
05301   * @param  hhrtim pointer to HAL HRTIM handle
05302   * @param  Timers Timer counter(s) to start
05303   *                   This parameter can be any combination of the following values:
05304   *                   @arg HRTIM_TIMERID_MASTER
05305   *                   @arg HRTIM_TIMERID_TIMER_A
05306   *                   @arg HRTIM_TIMERID_TIMER_B
05307   *                   @arg HRTIM_TIMERID_TIMER_C
05308   *                   @arg HRTIM_TIMERID_TIMER_D
05309   *                   @arg HRTIM_TIMERID_TIMER_E
05310   * @retval HAL status
05311   * @note This function enables the dma request(s) mentionned in the timer
05312   *       configuration data structure for every timers to start.
05313   * @note The source memory address, the destination memory address and the
05314   *       size of each DMA transfer are specified at timer configuration time
05315   *       (see HAL_HRTIM_WaveformTimerConfig)
05316   */
05317 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
05318                                                      uint32_t Timers)
05319 {
05320   uint8_t timer_idx;
05321   DMA_HandleTypeDef * hdma;
05322
05323   /* Check the parameters */
05324   assert_param(IS_HRTIM_TIMERID(Timers));
05325
05326   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
05327   {
05328      return HAL_BUSY;
05329   }
05330
05331   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05332
05333   /* Process Locked */
05334   __HAL_LOCK(hhrtim);
05335
05336   if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
05337       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
05338   {
05339       /* Set the DMA error callback */
05340       hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
05341
05342       /* Set the DMA transfer completed callback */
05343       hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
05344
05345       /* Enable the DMA channel */
05346       if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
05347                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
05348                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
05349                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
05350     {
05351             hhrtim->State = HAL_HRTIM_STATE_ERROR;
05352
05353             /* Process Unlocked */
05354             __HAL_UNLOCK(hhrtim);
05355
05356             return HAL_ERROR;
05357         }
05358
05359       /* Enable the timer DMA request */
05360       __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
05361                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
05362   }
05363
05364   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05365        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05366        timer_idx++)
05367   {
05368     if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
05369          (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
05370     {
05371       /* Get the timer DMA handler */
05372       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
05373
05374       if (hdma == NULL)
05375       {
05376         hhrtim->State = HAL_HRTIM_STATE_ERROR;
05377
05378         /* Process Unlocked */
05379         __HAL_UNLOCK(hhrtim);
05380
05381         return HAL_ERROR;
05382       }
05383
05384        /* Set the DMA error callback */
05385       hdma->XferErrorCallback = HRTIM_DMAError ;
05386
05387       /* Set the DMA transfer completed callback */
05388       hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
05389
05390       /* Enable the DMA channel */
05391       if (HAL_DMA_Start_IT(hdma,
05392                        hhrtim->TimerParam[timer_idx].DMASrcAddress,
05393                        hhrtim->TimerParam[timer_idx].DMADstAddress,
05394                        hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
05395     {
05396               hhrtim->State = HAL_HRTIM_STATE_ERROR;
05397
05398               /* Process Unlocked */
05399               __HAL_UNLOCK(hhrtim);
05400
05401               return HAL_ERROR;
05402         }
05403
05404       /* Enable the timer DMA request */
05405       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
05406                                    timer_idx,
05407                                    hhrtim->TimerParam[timer_idx].DMARequests);
05408     }
05409   }
05410
05411   /* Enable the timer counter */
05412   __HAL_HRTIM_ENABLE(hhrtim, Timers);
05413
05414   hhrtim->State = HAL_HRTIM_STATE_READY;
05415
05416   /* Process Unlocked */
05417   __HAL_UNLOCK(hhrtim);
05418
05419   return HAL_OK;
05420 }
05421
05422 /**
05423   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
05424   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
05425   * @param  hhrtim pointer to HAL HRTIM handle
05426   * @param  Timers Timer counter(s) to stop
05427   *                   This parameter can be any combination of the following values:
05428   *                   @arg HRTIM_TIMERID_MASTER
05429   *                   @arg HRTIM_TIMERID_TIMER_A
05430   *                   @arg HRTIM_TIMERID_TIMER_B
05431   *                   @arg HRTIM_TIMERID_TIMER_C
05432   *                   @arg HRTIM_TIMERID_TIMER_D
05433   *                   @arg HRTIM_TIMERID_TIMER_E
05434   * @retval HAL status
05435   * @note  The counter of a timer is stopped only if all timer outputs are disabled
05436   * @note  All enabled timer related DMA requests are disabled.
05437   */
05438 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
05439                                                     uint32_t Timers)
05440 {
05441   uint8_t timer_idx;
05442
05443   /* Check the parameters */
05444   assert_param(IS_HRTIM_TIMERID(Timers));
05445
05446   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05447
05448   if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
05449       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
05450   {
05451     /* Disable the DMA */
05452     if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
05453     {
05454           hhrtim->State = HAL_HRTIM_STATE_ERROR;
05455     }
05456     else
05457     {
05458           hhrtim->State = HAL_HRTIM_STATE_READY;
05459           /* Disable the DMA request(s) */
05460           __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
05461                                          hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
05462     }
05463   }
05464
05465   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
05466        timer_idx < HRTIM_TIMERINDEX_MASTER ;
05467        timer_idx++)
05468   {
05469     if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
05470         (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
05471     {
05472       /* Get the timer DMA handler */
05473       /* Disable the DMA */
05474       if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
05475       {
05476         hhrtim->State = HAL_HRTIM_STATE_ERROR;
05477       }
05478       else
05479       {
05480         hhrtim->State = HAL_HRTIM_STATE_READY;
05481
05482         /* Disable the DMA request(s) */
05483         __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
05484                                       timer_idx,
05485                                       hhrtim->TimerParam[timer_idx].DMARequests);
05486       }
05487     }
05488   }
05489
05490   /* Disable the timer counter */
05491   __HAL_HRTIM_DISABLE(hhrtim, Timers);
05492
05493   if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
05494   {
05495       return HAL_ERROR;
05496   }
05497   else
05498   {
05499       return HAL_OK;
05500   }
05501 }
05502
05503 /**
05504   * @brief  Enable or disables the HRTIM burst mode controller.
05505   * @param  hhrtim pointer to HAL HRTIM handle
05506   * @param  Enable Burst mode controller enabling
05507   *                    This parameter can be one of the following values:
05508   *                    @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
05509   *                    @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
05510   * @retval HAL status
05511   * @note This function must be called after starting the timer(s)
05512   */
05513 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
05514                                          uint32_t Enable)
05515 {
05516   /* Check parameters */
05517   assert_param(IS_HRTIM_BURSTMODECTL(Enable));
05518
05519   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05520   {
05521      return HAL_BUSY;
05522   }
05523
05524   /* Process Locked */
05525   __HAL_LOCK(hhrtim);
05526
05527   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05528
05529   /* Enable/Disable the burst mode controller */
05530   MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
05531
05532   hhrtim->State = HAL_HRTIM_STATE_READY;
05533
05534   /* Process Unlocked */
05535   __HAL_UNLOCK(hhrtim);
05536
05537   return HAL_OK;
05538 }
05539
05540 /**
05541   * @brief  Trig the burst mode operation.
05542   * @param  hhrtim pointer to HAL HRTIM handle
05543   * @retval HAL status
05544   */
05545 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
05546 {
05547   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05548   {
05549      return HAL_BUSY;
05550   }
05551
05552   /* Process Locked */
05553   __HAL_LOCK(hhrtim);
05554
05555   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05556
05557   /* Software trigger of the burst mode controller */
05558   SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
05559
05560   hhrtim->State = HAL_HRTIM_STATE_READY;
05561
05562   /* Process Unlocked */
05563   __HAL_UNLOCK(hhrtim);
05564
05565   return HAL_OK;
05566 }
05567
05568 /**
05569   * @brief  Trig a software capture on the designed capture unit
05570   * @param  hhrtim pointer to HAL HRTIM handle
05571   * @param  TimerIdx Timer index
05572   *                   This parameter can be one of the following values:
05573   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05574   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05575   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05576   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05577   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05578   * @param  CaptureUnit Capture unit to trig
05579   *                    This parameter can be one of the following values:
05580   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
05581   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
05582   * @retval HAL status
05583   * @note The 'software capture' bit in the capure configuration register is
05584   *       automatically reset by hardware
05585   */
05586 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
05587                                             uint32_t TimerIdx,
05588                                             uint32_t CaptureUnit)
05589 {
05590   /* Check parameters */
05591   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05592   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
05593
05594   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05595   {
05596      return HAL_BUSY;
05597   }
05598
05599   /* Process Locked */
05600   __HAL_LOCK(hhrtim);
05601
05602   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05603
05604   /* Force a software capture on concerned capture unit */
05605   switch (CaptureUnit)
05606   {
05607   case HRTIM_CAPTUREUNIT_1:
05608     {
05609       SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
05610       break;
05611     }
05612
05613   case HRTIM_CAPTUREUNIT_2:
05614     {
05615       SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
05616       break;
05617     }
05618
05619   default:
05620     {
05621       hhrtim->State = HAL_HRTIM_STATE_ERROR;
05622
05623       /* Process Unlocked */
05624       __HAL_UNLOCK(hhrtim);
05625
05626     break;
05627     }
05628   }
05629
05630   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05631   {
05632      return HAL_ERROR;
05633   }
05634
05635   hhrtim->State = HAL_HRTIM_STATE_READY;
05636
05637   /* Process Unlocked */
05638   __HAL_UNLOCK(hhrtim);
05639
05640   return HAL_OK;
05641 }
05642
05643 /**
05644   * @brief  Trig the update of the registers of one or several timers
05645   * @param  hhrtim pointer to HAL HRTIM handle
05646   * @param  Timers timers concerned with the software register update
05647   *                   This parameter can be any combination of the following values:
05648   *                   @arg HRTIM_TIMERUPDATE_MASTER
05649   *                   @arg HRTIM_TIMERUPDATE_A
05650   *                   @arg HRTIM_TIMERUPDATE_B
05651   *                   @arg HRTIM_TIMERUPDATE_C
05652   *                   @arg HRTIM_TIMERUPDATE_D
05653   *                   @arg HRTIM_TIMERUPDATE_E
05654   * @retval HAL status
05655   * @note The 'software update' bits in the HRTIM conrol register 2 register are
05656   *       automatically reset by hardware
05657   */
05658 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
05659                                            uint32_t Timers)
05660 {
05661   /* Check parameters */
05662   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05663
05664   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05665   {
05666      return HAL_BUSY;
05667   }
05668
05669   /* Process Locked */
05670   __HAL_LOCK(hhrtim);
05671
05672   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05673
05674   /* Force timer(s) registers update */
05675   hhrtim->Instance->sCommonRegs.CR2 |= Timers;
05676
05677   hhrtim->State = HAL_HRTIM_STATE_READY;
05678
05679   /* Process Unlocked */
05680   __HAL_UNLOCK(hhrtim);
05681
05682   return HAL_OK;
05683 }
05684
05685 /**
05686   * @brief  Trig the reset of one or several timers
05687   * @param  hhrtim pointer to HAL HRTIM handle
05688   * @param  Timers timers concerned with the software counter reset
05689   *                   This parameter can be any combination of the following values:
05690   *                   @arg HRTIM_TIMERRESET_MASTER
05691   *                   @arg HRTIM_TIMERRESET_TIMER_A
05692   *                   @arg HRTIM_TIMERRESET_TIMER_B
05693   *                   @arg HRTIM_TIMERRESET_TIMER_C
05694   *                   @arg HRTIM_TIMERRESET_TIMER_D
05695   *                   @arg HRTIM_TIMERRESET_TIMER_E
05696   * @retval HAL status
05697   * @note The 'software reset' bits in the HRTIM conrol register 2  are
05698   *       automatically reset by hardware
05699   */
05700 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
05701                                           uint32_t Timers)
05702 {
05703   /* Check parameters */
05704   assert_param(IS_HRTIM_TIMERRESET(Timers));
05705
05706   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05707   {
05708      return HAL_BUSY;
05709   }
05710
05711   /* Process Locked */
05712   __HAL_LOCK(hhrtim);
05713
05714   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05715
05716   /* Force timer(s) registers reset */
05717   hhrtim->Instance->sCommonRegs.CR2 = Timers;
05718
05719   hhrtim->State = HAL_HRTIM_STATE_READY;
05720
05721   /* Process Unlocked */
05722   __HAL_UNLOCK(hhrtim);
05723
05724   return HAL_OK;
05725 }
05726
05727 /**
05728   * @brief  Start a burst DMA operation to update HRTIM control registers content
05729   * @param  hhrtim pointer to HAL HRTIM handle
05730   * @param  TimerIdx Timer index
05731   *                   This parameter can be one of the following values:
05732   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05733   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05734   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05735   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05736   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05737   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05738   * @param  BurstBufferAddress address of the buffer the HRTIM control registers
05739   *                             content will be updated from.
05740   * @param  BurstBufferLength size (in WORDS) of the burst buffer.
05741   * @retval HAL status
05742   * @note The TimerIdx parameter determines the dma channel to be used by the
05743   *       DMA burst controller (see below)
05744   *       HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
05745   *       HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
05746   *       HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
05747   *       HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
05748   *       HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
05749   *       HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
05750   */
05751 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
05752                                              uint32_t TimerIdx,
05753                                              uint32_t BurstBufferAddress,
05754                                              uint32_t BurstBufferLength)
05755 {
05756   DMA_HandleTypeDef * hdma;
05757
05758   /* Check the parameters */
05759   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
05760
05761   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
05762   {
05763      return HAL_BUSY;
05764   }
05765   if((hhrtim->State == HAL_HRTIM_STATE_READY))
05766   {
05767     if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
05768     {
05769       return HAL_ERROR;
05770     }
05771     else
05772     {
05773       hhrtim->State = HAL_HRTIM_STATE_BUSY;
05774     }
05775   }
05776
05777   /* Process Locked */
05778   __HAL_LOCK(hhrtim);
05779
05780   /* Get the timer DMA handler */
05781   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
05782
05783   if (hdma == NULL)
05784   {
05785     hhrtim->State = HAL_HRTIM_STATE_ERROR;
05786
05787     /* Process Unlocked */
05788     __HAL_UNLOCK(hhrtim);
05789
05790     return HAL_ERROR;
05791   }
05792
05793   /* Set the DMA transfer completed callback */
05794   hdma->XferCpltCallback = HRTIM_BurstDMACplt;
05795
05796   /* Set the DMA error callback */
05797   hdma->XferErrorCallback = HRTIM_DMAError ;
05798
05799   /* Enable the DMA channel */
05800   if (HAL_DMA_Start_IT(hdma,
05801                    BurstBufferAddress,
05802                    (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
05803                    BurstBufferLength) != HAL_OK)
05804     {
05805            hhrtim->State = HAL_HRTIM_STATE_ERROR;
05806
05807            /* Process Unlocked */
05808            __HAL_UNLOCK(hhrtim);
05809
05810            return HAL_ERROR;
05811         }
05812
05813   hhrtim->State = HAL_HRTIM_STATE_READY;
05814
05815   /* Process Unlocked */
05816   __HAL_UNLOCK(hhrtim);
05817
05818   return HAL_OK;
05819 }
05820
05821 /**
05822   * @brief  Enable the transfer from preload to active registers for one
05823   *         or several timing units (including master timer).
05824   * @param  hhrtim pointer to HAL HRTIM handle
05825   * @param  Timers Timer(s) concerned by the register preload enabling command
05826   *                   This parameter can be any combination of the following values:
05827   *                   @arg HRTIM_TIMERUPDATE_MASTER
05828   *                   @arg HRTIM_TIMERUPDATE_A
05829   *                   @arg HRTIM_TIMERUPDATE_B
05830   *                   @arg HRTIM_TIMERUPDATE_C
05831   *                   @arg HRTIM_TIMERUPDATE_D
05832   *                   @arg HRTIM_TIMERUPDATE_E
05833   * @retval HAL status
05834   */
05835 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
05836                                           uint32_t Timers)
05837 {
05838    /* Check the parameters */
05839   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05840
05841   /* Process Locked */
05842   __HAL_LOCK(hhrtim);
05843
05844   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05845
05846   /* Enable timer(s) registers update */
05847   hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
05848
05849   hhrtim->State = HAL_HRTIM_STATE_READY;
05850
05851   /* Process Unlocked */
05852   __HAL_UNLOCK(hhrtim);
05853
05854   return HAL_OK;
05855   }
05856
05857 /**
05858   * @brief  Disable the transfer from preload to active registers for one
05859   *         or several timing units (including master timer).
05860   * @param  hhrtim pointer to HAL HRTIM handle
05861   * @param  Timers Timer(s) concerned by the register preload disabling command
05862   *                   This parameter can be any combination of the following values:
05863   *                   @arg HRTIM_TIMERUPDATE_MASTER
05864   *                   @arg HRTIM_TIMERUPDATE_A
05865   *                   @arg HRTIM_TIMERUPDATE_B
05866   *                   @arg HRTIM_TIMERUPDATE_C
05867   *                   @arg HRTIM_TIMERUPDATE_D
05868   *                   @arg HRTIM_TIMERUPDATE_E
05869   * @retval HAL status
05870   */
05871 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
05872                                           uint32_t Timers)
05873 {
05874   /* Check the parameters */
05875   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05876
05877   /* Process Locked */
05878   __HAL_LOCK(hhrtim);
05879
05880   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05881
05882   /* Enable timer(s) registers update */
05883   hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
05884
05885   hhrtim->State = HAL_HRTIM_STATE_READY;
05886
05887   /* Process Unlocked */
05888   __HAL_UNLOCK(hhrtim);
05889
05890   return HAL_OK;
05891   }
05892
05893 /**
05894   * @}
05895   */
05896
05897 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
05898  *  @brief    Peripheral State functions
05899 @verbatim
05900  ===============================================================================
05901               ##### Peripheral State functions #####
05902  ===============================================================================
05903     [..]  This section provides functions used to get HRTIM or HRTIM timer
05904           specific information:
05905       (+) Get HRTIM HAL state
05906       (+) Get captured value
05907       (+) Get HRTIM timer output level
05908       (+) Get HRTIM timer output state
05909       (+) Get delayed protection status
05910       (+) Get burst status
05911       (+) Get current push-pull status
05912       (+) Get idle push-pull status
05913
05914 @endverbatim
05915   * @{
05916   */
05917
05918 /**
05919   * @brief  Return the HRTIM HAL state
05920   * @param  hhrtim pointer to HAL HRTIM handle
05921   * @retval HAL state
05922   */
05923 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
05924 {
05925   /* Return HRTIM state */
05926   return hhrtim->State;
05927 }
05928
05929 /**
05930   * @brief  Return actual value of the capture register of the designated capture unit
05931   * @param  hhrtim pointer to HAL HRTIM handle
05932   * @param  TimerIdx Timer index
05933   *                   This parameter can be one of the following values:
05934   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05935   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05936   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05937   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05938   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05939   * @param  CaptureUnit Capture unit to trig
05940   *                    This parameter can be one of the following values:
05941   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
05942   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
05943   * @retval Captured value
05944   */
05945 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
05946                                     uint32_t TimerIdx,
05947                                     uint32_t CaptureUnit)
05948 {
05949   uint32_t captured_value;
05950
05951   /* Check parameters */
05952   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05953   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
05954
05955   /* Read captured value */
05956   switch (CaptureUnit)
05957   {
05958   case HRTIM_CAPTUREUNIT_1:
05959     {
05960       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
05961       break;
05962     }
05963
05964   case HRTIM_CAPTUREUNIT_2:
05965     {
05966       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
05967       break;
05968     }
05969
05970   default:
05971    {
05972        captured_value = 0xFFFFFFFFUL;
05973
05974        hhrtim->State = HAL_HRTIM_STATE_ERROR;
05975
05976       /* Process Unlocked */
05977       __HAL_UNLOCK(hhrtim);
05978       break;
05979     }
05980
05981   }
05982
05983   return captured_value;
05984 }
05985
05986
05987 /**
05988   * @brief  Return actual level (active or inactive) of the designated output
05989   * @param  hhrtim pointer to HAL HRTIM handle
05990   * @param  TimerIdx Timer index
05991   *                   This parameter can be one of the following values:
05992   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05993   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05994   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05995   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05996   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05997   * @param  Output Timer output
05998   *                    This parameter can be one of the following values:
05999   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06000   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06001   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06002   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06003   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06004   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06005   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06006   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06007   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06008   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06009   * @retval Output level
06010   * @note Returned output level is taken before the output stage (chopper,
06011   *        polarity).
06012   */
06013 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
06014                                           uint32_t TimerIdx,
06015                                           uint32_t Output)
06016 {
06017   uint32_t output_level = (uint32_t)RESET;
06018
06019   /* Check parameters */
06020   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
06021
06022   /* Read the output level */
06023   switch (Output)
06024   {
06025   case HRTIM_OUTPUT_TA1:
06026   case HRTIM_OUTPUT_TB1:
06027   case HRTIM_OUTPUT_TC1:
06028   case HRTIM_OUTPUT_TD1:
06029   case HRTIM_OUTPUT_TE1:
06030     {
06031       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
06032       {
06033         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
06034       }
06035       else
06036       {
06037         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
06038       }
06039      break;
06040     }
06041
06042   case HRTIM_OUTPUT_TA2:
06043   case HRTIM_OUTPUT_TB2:
06044   case HRTIM_OUTPUT_TC2:
06045   case HRTIM_OUTPUT_TD2:
06046   case HRTIM_OUTPUT_TE2:
06047     {
06048       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
06049       {
06050         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
06051       }
06052       else
06053       {
06054         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
06055       }
06056       break;
06057     }
06058
06059   default:
06060     {
06061       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06062
06063       /* Process Unlocked */
06064       __HAL_UNLOCK(hhrtim);
06065
06066       break;
06067     }
06068   }
06069
06070   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06071   {
06072      return (uint32_t)HAL_ERROR;
06073   }
06074
06075   return output_level;
06076 }
06077
06078 /**
06079   * @brief  Return actual state (RUN, IDLE, FAULT) of the designated output
06080   * @param  hhrtim pointer to HAL HRTIM handle
06081   * @param  TimerIdx Timer index
06082   *                   This parameter can be one of the following values:
06083   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06084   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06085   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06086   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06087   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06088   * @param  Output Timer output
06089   *                    This parameter can be one of the following values:
06090   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06091   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06092   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06093   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06094   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06095   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06096   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06097   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06098   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06099   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06100   * @retval Output state
06101   */
06102 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
06103                                           uint32_t TimerIdx,
06104                                           uint32_t Output)
06105 {
06106   uint32_t output_bit = (uint32_t)RESET;
06107   uint32_t output_state;
06108
06109   /* Check parameters */
06110   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
06111
06112   /* Set output state according to output control status and output disable status */
06113   switch (Output)
06114   {
06115   case HRTIM_OUTPUT_TA1:
06116     {
06117       output_bit = HRTIM_OENR_TA1OEN;
06118       break;
06119     }
06120
06121   case HRTIM_OUTPUT_TA2:
06122     {
06123       output_bit = HRTIM_OENR_TA2OEN;
06124       break;
06125     }
06126
06127   case HRTIM_OUTPUT_TB1:
06128     {
06129       output_bit = HRTIM_OENR_TB1OEN;
06130       break;
06131     }
06132
06133   case HRTIM_OUTPUT_TB2:
06134     {
06135       output_bit = HRTIM_OENR_TB2OEN;
06136       break;
06137     }
06138
06139   case HRTIM_OUTPUT_TC1:
06140     {
06141       output_bit = HRTIM_OENR_TC1OEN;
06142       break;
06143     }
06144
06145   case HRTIM_OUTPUT_TC2:
06146     {
06147       output_bit = HRTIM_OENR_TC2OEN;
06148       break;
06149     }
06150
06151   case HRTIM_OUTPUT_TD1:
06152     {
06153       output_bit = HRTIM_OENR_TD1OEN;
06154       break;
06155     }
06156
06157   case HRTIM_OUTPUT_TD2:
06158     {
06159       output_bit = HRTIM_OENR_TD2OEN;
06160       break;
06161     }
06162
06163   case HRTIM_OUTPUT_TE1:
06164     {
06165       output_bit = HRTIM_OENR_TE1OEN;
06166       break;
06167     }
06168
06169   case HRTIM_OUTPUT_TE2:
06170     {
06171       output_bit = HRTIM_OENR_TE2OEN;
06172       break;
06173     }
06174
06175   default:
06176     {
06177       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06178
06179       /* Process Unlocked */
06180       __HAL_UNLOCK(hhrtim);
06181
06182       break;
06183     }
06184   }
06185
06186   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06187   {
06188      return (uint32_t)HAL_ERROR;
06189   }
06190
06191   if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
06192   {
06193     /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
06194     output_state = HRTIM_OUTPUTSTATE_RUN;
06195   }
06196   else
06197   {
06198     if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
06199     {
06200       /* Output is disabled: output in FAULT state */
06201       output_state = HRTIM_OUTPUTSTATE_FAULT;
06202     }
06203     else
06204     {
06205       /* Output is disabled: output in IDLE state */
06206       output_state = HRTIM_OUTPUTSTATE_IDLE;
06207     }
06208   }
06209
06210   return(output_state);
06211 }
06212
06213 /**
06214   * @brief  Return the level (active or inactive) of the designated output
06215   *         when the delayed protection was triggered.
06216   * @param  hhrtim pointer to HAL HRTIM handle
06217   * @param  TimerIdx Timer index
06218   *                   This parameter can be one of the following values:
06219   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06220   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06221   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06222   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06223   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06224   * @param  Output Timer output
06225   *                    This parameter can be one of the following values:
06226   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06227   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06228   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06229   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06230   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06231   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06232   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06233   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06234   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06235   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06236   * @retval Delayed protection status
06237   */
06238 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
06239                                               uint32_t TimerIdx,
06240                                               uint32_t Output)
06241 {
06242   uint32_t delayed_protection_status = (uint32_t)RESET;
06243
06244   /* Check parameters */
06245   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
06246
06247   /* Read the delayed protection status */
06248   switch (Output)
06249   {
06250   case HRTIM_OUTPUT_TA1:
06251   case HRTIM_OUTPUT_TB1:
06252   case HRTIM_OUTPUT_TC1:
06253   case HRTIM_OUTPUT_TD1:
06254   case HRTIM_OUTPUT_TE1:
06255     {
06256       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
06257       {
06258         /* Output 1 was active when the delayed idle protection was triggered */
06259         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
06260       }
06261       else
06262       {
06263         /* Output 1 was inactive when the delayed idle protection was triggered */
06264         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
06265       }
06266       break;
06267     }
06268
06269   case HRTIM_OUTPUT_TA2:
06270   case HRTIM_OUTPUT_TB2:
06271   case HRTIM_OUTPUT_TC2:
06272   case HRTIM_OUTPUT_TD2:
06273   case HRTIM_OUTPUT_TE2:
06274     {
06275       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
06276       {
06277         /* Output 2 was active when the delayed idle protection was triggered */
06278         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
06279       }
06280       else
06281       {
06282         /* Output 2 was inactive when the delayed idle protection was triggered */
06283         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
06284       }
06285       break;
06286     }
06287
06288   default:
06289     {
06290       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06291
06292       /* Process Unlocked */
06293       __HAL_UNLOCK(hhrtim);
06294
06295       break;
06296     }
06297   }
06298
06299   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06300   {
06301      return (uint32_t)HAL_ERROR;
06302   }
06303
06304   return delayed_protection_status;
06305 }
06306
06307 /**
06308   * @brief  Return the actual status (active or inactive) of the burst mode controller
06309   * @param  hhrtim pointer to HAL HRTIM handle
06310   * @retval Burst mode controller status
06311   */
06312 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
06313 {
06314   uint32_t burst_mode_status;
06315
06316   /* Read burst mode status */
06317   burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
06318
06319   return burst_mode_status;
06320 }
06321
06322 /**
06323   * @brief  Indicate on which output the signal is currently active (when the
06324   *         push pull mode is enabled).
06325   * @param  hhrtim pointer to HAL HRTIM handle
06326   * @param  TimerIdx Timer index
06327   *                   This parameter can be one of the following values:
06328   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06329   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06330   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06331   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06332   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06333   * @retval Burst mode controller status
06334   */
06335 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
06336                                             uint32_t TimerIdx)
06337 {
06338   uint32_t current_pushpull_status;
06339
06340   /* Check the parameters */
06341   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
06342
06343   /* Read current push pull status */
06344   current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
06345
06346   return current_pushpull_status;
06347 }
06348
06349
06350 /**
06351   * @brief  Indicate on which output the signal was applied, in push-pull mode,
06352             balanced fault mode or delayed idle mode, when the protection was triggered.
06353   * @param  hhrtim pointer to HAL HRTIM handle
06354   * @param  TimerIdx Timer index
06355   *                   This parameter can be one of the following values:
06356   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06357   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06358   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06359   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06360   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06361   * @retval Idle Push Pull Status
06362   */
06363 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
06364                                          uint32_t TimerIdx)
06365 {
06366   uint32_t idle_pushpull_status;
06367
06368   /* Check the parameters */
06369   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
06370
06371   /* Read current push pull status */
06372   idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
06373
06374   return idle_pushpull_status;
06375 }
06376
06377 /**
06378   * @}
06379   */
06380
06381 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
06382  *  @brief  Functions called when HRTIM generates an interrupt
06383  *          7 interrupts can be generated by the master timer:
06384  *            - Master timer registers update
06385  *            - Synchronization event received
06386  *            - Master timer repetition event
06387  *            - Master Compare 1 to 4 event
06388  *          14 interrupts can be generated by each timing unit:
06389  *            - Delayed protection triggered
06390  *            - Counter reset or roll-over event
06391  *            - Output 1 and output 2 reset (transition active to inactive)
06392  *            - Output 1 and output 2 set (transition inactive to active)
06393  *            - Capture 1 and 2 events
06394  *            - Timing unit registers update
06395  *            - Repetition event
06396  *            - Compare 1 to 4 event
06397  *          7 global interrupts are generated for the whole HRTIM:
06398  *            - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
06399  *            - Burst mode period completed
06400 @verbatim
06401  ===============================================================================
06402                       ##### HRTIM interrupts handling #####
06403  ===============================================================================
06404     [..]
06405     This subsection provides a set of functions allowing to manage the HRTIM
06406     interrupts:
06407       (+)  HRTIM interrupt handler
06408       (+)  Callback function called when Fault1 interrupt occurs
06409       (+)  Callback function called when Fault2 interrupt occurs
06410       (+)  Callback function called when Fault3 interrupt occurs
06411       (+)  Callback function called when Fault4 interrupt occurs
06412       (+)  Callback function called when Fault5 interrupt occurs
06413       (+)  Callback function called when system Fault interrupt occurs
06414       (+)  Callback function called when burst mode period interrupt occurs
06415       (+)  Callback function called when synchronization input interrupt occurs
06416       (+)  Callback function called when a timer register update interrupt occurs
06417       (+)  Callback function called when a timer repetition interrupt occurs
06418       (+)  Callback function called when a compare 1 match interrupt occurs
06419       (+)  Callback function called when a compare 2 match interrupt occurs
06420       (+)  Callback function called when a compare 3 match interrupt occurs
06421       (+)  Callback function called when a compare 4 match interrupt occurs
06422       (+)  Callback function called when a capture 1 interrupt occurs
06423       (+)  Callback function called when a capture 2 interrupt occurs
06424       (+)  Callback function called when a delayed protection interrupt occurs
06425       (+)  Callback function called when a timer counter reset interrupt occurs
06426       (+)  Callback function called when a timer output 1 set interrupt occurs
06427       (+)  Callback function called when a timer output 1 reset interrupt occurs
06428       (+)  Callback function called when a timer output 2 set interrupt occurs
06429       (+)  Callback function called when a timer output 2 reset interrupt occurs
06430       (+)  Callback function called when a timer output 2 reset interrupt occurs
06431       (+)  Callback function called upon completion of a burst DMA transfer
06432       (+)  HRTIM callback function registration
06433       (+)  HRTIM callback function unregistration
06434       (+)  HRTIM Timer x callback function registration
06435       (+)  HRTIM Timer x callback function unregistration
06436
06437 @endverbatim
06438   * @{
06439   */
06440
06441 /**
06442   * @brief  This function handles HRTIM interrupt request.
06443   * @param  hhrtim pointer to HAL HRTIM handle
06444   * @param  TimerIdx Timer index
06445   *                   This parameter can be any value of HRTIM_Timer_Index
06446   * @retval None
06447   */
06448 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
06449                           uint32_t TimerIdx)
06450 {
06451   /* HRTIM interrupts handling */
06452   if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
06453   {
06454     HRTIM_HRTIM_ISR(hhrtim);
06455   }
06456   else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
06457   {
06458     /* Master related interrupts handling */
06459     HRTIM_Master_ISR(hhrtim);
06460   }
06461   else
06462   {
06463     /* Timing unit related interrupts handling */
06464     HRTIM_Timer_ISR(hhrtim, TimerIdx);
06465   }
06466
06467 }
06468
06469 /**
06470   * @brief  Callback function invoked when a fault 1 interrupt occurred
06471   * @param  hhrtim pointer to HAL HRTIM handle  * @retval None
06472   * @retval None
06473   */
06474 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
06475 {
06476   /* Prevent unused argument(s) compilation warning */
06477   UNUSED(hhrtim);
06478
06479   /* NOTE : This function should not be modified, when the callback is needed,
06480             the HAL_HRTIM_Fault1Callback could be implemented in the user file
06481    */
06482 }
06483
06484 /**
06485   * @brief  Callback function invoked when a fault 2 interrupt occurred
06486   * @param  hhrtim pointer to HAL HRTIM handle
06487   * @retval None
06488   */
06489 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
06490 {
06491   /* Prevent unused argument(s) compilation warning */
06492   UNUSED(hhrtim);
06493
06494   /* NOTE : This function should not be modified, when the callback is needed,
06495             the HAL_HRTIM_Fault2Callback could be implemented in the user file
06496    */
06497 }
06498
06499 /**
06500   * @brief  Callback function invoked when a fault 3 interrupt occurred
06501   * @param  hhrtim pointer to HAL HRTIM handle
06502   * @retval None
06503   */
06504 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
06505 {
06506   /* Prevent unused argument(s) compilation warning */
06507   UNUSED(hhrtim);
06508
06509   /* NOTE : This function should not be modified, when the callback is needed,
06510             the HAL_HRTIM_Fault3Callback could be implemented in the user file
06511    */
06512 }
06513
06514 /**
06515   * @brief  Callback function invoked when a fault 4 interrupt occurred
06516   * @param  hhrtim pointer to HAL HRTIM handle
06517   * @retval None
06518   */
06519 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
06520 {
06521   /* Prevent unused argument(s) compilation warning */
06522   UNUSED(hhrtim);
06523
06524   /* NOTE : This function should not be modified, when the callback is needed,
06525             the HAL_HRTIM_Fault4Callback could be implemented in the user file
06526    */
06527 }
06528
06529 /**
06530   * @brief  Callback function invoked when a fault 5 interrupt occurred
06531   * @param  hhrtim pointer to HAL HRTIM handle
06532   * @retval None
06533   */
06534 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
06535 {
06536   /* Prevent unused argument(s) compilation warning */
06537   UNUSED(hhrtim);
06538
06539   /* NOTE : This function should not be modified, when the callback is needed,
06540             the HAL_HRTIM_Fault5Callback could be implemented in the user file
06541    */
06542 }
06543
06544 /**
06545   * @brief  Callback function invoked when a system fault interrupt occurred
06546   * @param  hhrtim pointer to HAL HRTIM handle
06547   * @retval None
06548   */
06549 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
06550 {
06551   /* Prevent unused argument(s) compilation warning */
06552   UNUSED(hhrtim);
06553
06554   /* NOTE : This function should not be modified, when the callback is needed,
06555             the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
06556    */
06557 }
06558
06559 /**
06560   * @brief  Callback function invoked when the end of the burst mode period is reached
06561   * @param  hhrtim pointer to HAL HRTIM handle
06562   * @retval None
06563   */
06564 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
06565 {
06566   /* Prevent unused argument(s) compilation warning */
06567   UNUSED(hhrtim);
06568
06569   /* NOTE : This function should not be modified, when the callback is needed,
06570             the HAL_HRTIM_BurstModeCallback could be implemented in the user file
06571    */
06572 }
06573
06574 /**
06575   * @brief  Callback function invoked when a synchronization input event is received
06576   * @param  hhrtim pointer to HAL HRTIM handle
06577   * @retval None
06578   */
06579 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
06580 {
06581   /* Prevent unused argument(s) compilation warning */
06582   UNUSED(hhrtim);
06583
06584   /* NOTE : This function should not be modified, when the callback is needed,
06585             the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
06586    */
06587 }
06588
06589 /**
06590   * @brief  Callback function invoked when timer registers are updated
06591   * @param  hhrtim pointer to HAL HRTIM handle
06592   * @param  TimerIdx Timer index
06593   *                   This parameter can be one of the following values:
06594   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06595   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06596   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06597   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06598   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06599   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06600   * @retval None
06601   */
06602 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
06603                                               uint32_t TimerIdx)
06604 {
06605   /* Prevent unused argument(s) compilation warning */
06606   UNUSED(hhrtim);
06607   UNUSED(TimerIdx);
06608
06609   /* NOTE : This function should not be modified, when the callback is needed,
06610             the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
06611    */
06612 }
06613
06614 /**
06615   * @brief  Callback function invoked when timer repetition period has elapsed
06616   * @param  hhrtim pointer to HAL HRTIM handle
06617   * @param  TimerIdx Timer index
06618   *                   This parameter can be one of the following values:
06619   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06620   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06621   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06622   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06623   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06624   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06625   * @retval None
06626   */
06627 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
06628                                               uint32_t TimerIdx)
06629 {
06630   /* Prevent unused argument(s) compilation warning */
06631   UNUSED(hhrtim);
06632   UNUSED(TimerIdx);
06633
06634   /* NOTE : This function should not be modified, when the callback is needed,
06635             the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
06636    */
06637 }
06638
06639 /**
06640   * @brief  Callback function invoked when the timer counter matches the value
06641   *         programmed in the compare 1 register
06642   * @param  hhrtim pointer to HAL HRTIM handle
06643   * @param  TimerIdx Timer index
06644   *                   This parameter can be one of the following values:
06645   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06646   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06647   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06648   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06649   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06650   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06651   * @retval None
06652   */
06653 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
06654                                               uint32_t TimerIdx)
06655 {
06656   /* Prevent unused argument(s) compilation warning */
06657   UNUSED(hhrtim);
06658   UNUSED(TimerIdx);
06659
06660   /* NOTE : This function should not be modified, when the callback is needed,
06661             the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
06662    */
06663 }
06664
06665 /**
06666   * @brief  Callback function invoked when the timer counter matches the value
06667   *         programmed in the compare 2 register
06668   * @param  hhrtim pointer to HAL HRTIM handle
06669   * @retval None
06670   * @param  TimerIdx Timer index
06671   *                   This parameter can be one of the following values:
06672   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06673   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06674   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06675   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06676   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06677   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06678   */
06679 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
06680                                               uint32_t TimerIdx)
06681 {
06682   /* Prevent unused argument(s) compilation warning */
06683   UNUSED(hhrtim);
06684   UNUSED(TimerIdx);
06685
06686   /* NOTE : This function should not be modified, when the callback is needed,
06687             the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
06688    */
06689 }
06690
06691 /**
06692   * @brief  Callback function invoked when the timer counter matches the value
06693   *         programmed in the compare 3 register
06694   * @param  hhrtim pointer to HAL HRTIM handle
06695   * @param  TimerIdx Timer index
06696   *                   This parameter can be one of the following values:
06697   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06698   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06699   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06700   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06701   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06702   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06703   * @retval None
06704   */
06705 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
06706                                               uint32_t TimerIdx)
06707 {
06708   /* Prevent unused argument(s) compilation warning */
06709   UNUSED(hhrtim);
06710   UNUSED(TimerIdx);
06711
06712   /* NOTE : This function should not be modified, when the callback is needed,
06713             the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
06714    */
06715 }
06716
06717 /**
06718   * @brief  Callback function invoked when the timer counter matches the value
06719   *         programmed in the compare 4 register.
06720   * @param  hhrtim pointer to HAL HRTIM handle
06721   * @param  TimerIdx Timer index
06722   *                   This parameter can be one of the following values:
06723   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06724   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06725   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06726   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06727   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06728   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06729   * @retval None
06730   */
06731 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
06732                                               uint32_t TimerIdx)
06733 {
06734   /* Prevent unused argument(s) compilation warning */
06735   UNUSED(hhrtim);
06736   UNUSED(TimerIdx);
06737
06738   /* NOTE : This function should not be modified, when the callback is needed,
06739             the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
06740    */
06741 }
06742
06743 /**
06744   * @brief  Callback function invoked when the timer x capture 1 event occurs
06745   * @param  hhrtim pointer to HAL HRTIM handle
06746   * @param  TimerIdx Timer index
06747   *                   This parameter can be one of the following values:
06748   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06749   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06750   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06751   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06752   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06753   * @retval None
06754   */
06755 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
06756                                               uint32_t TimerIdx)
06757 {
06758   /* Prevent unused argument(s) compilation warning */
06759   UNUSED(hhrtim);
06760   UNUSED(TimerIdx);
06761
06762   /* NOTE : This function should not be modified, when the callback is needed,
06763             the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
06764    */
06765 }
06766
06767 /**
06768   * @brief  Callback function invoked when the timer x capture 2 event occurs
06769   * @param  hhrtim pointer to HAL HRTIM handle
06770   * @param  TimerIdx Timer index
06771   *                   This parameter can be one of the following values:
06772   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06773   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06774   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06775   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06776   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06777   * @retval None
06778   */
06779 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
06780                                               uint32_t TimerIdx)
06781 {
06782   /* Prevent unused argument(s) compilation warning */
06783   UNUSED(hhrtim);
06784   UNUSED(TimerIdx);
06785
06786   /* NOTE : This function should not be modified, when the callback is needed,
06787             the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
06788    */
06789 }
06790
06791 /**
06792   * @brief  Callback function invoked when the delayed idle or balanced idle mode is
06793   *         entered.
06794   * @param  hhrtim pointer to HAL HRTIM handle
06795   * @param  TimerIdx Timer index
06796   *                   This parameter can be one of the following values:
06797   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06798   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06799   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06800   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06801   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06802   * @retval None
06803   */
06804 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
06805                                               uint32_t TimerIdx)
06806 {
06807   /* Prevent unused argument(s) compilation warning */
06808   UNUSED(hhrtim);
06809   UNUSED(TimerIdx);
06810
06811   /* NOTE : This function should not be modified, when the callback is needed,
06812             the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
06813    */
06814 }
06815
06816 /**
06817   * @brief  Callback function invoked when the timer x counter reset/roll-over
06818   *         event occurs.
06819   * @param  hhrtim pointer to HAL HRTIM handle
06820   * @param  TimerIdx Timer index
06821   *                   This parameter can be one of the following values:
06822   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06823   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06824   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06825   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06826   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06827   * @retval None
06828   */
06829 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
06830                                               uint32_t TimerIdx)
06831 {
06832   /* Prevent unused argument(s) compilation warning */
06833   UNUSED(hhrtim);
06834   UNUSED(TimerIdx);
06835
06836   /* NOTE : This function should not be modified, when the callback is needed,
06837             the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
06838    */
06839 }
06840
06841 /**
06842   * @brief  Callback function invoked when the timer x output 1 is set
06843   * @param  hhrtim pointer to HAL HRTIM handle
06844   * @param  TimerIdx Timer index
06845   *                   This parameter can be one of the following values:
06846   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06847   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06848   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06849   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06850   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06851   * @retval None
06852   */
06853 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
06854                                               uint32_t TimerIdx)
06855 {
06856   /* Prevent unused argument(s) compilation warning */
06857   UNUSED(hhrtim);
06858   UNUSED(TimerIdx);
06859
06860   /* NOTE : This function should not be modified, when the callback is needed,
06861             the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
06862    */
06863 }
06864
06865 /**
06866   * @brief  Callback function invoked when the timer x output 1 is reset
06867   * @param  hhrtim pointer to HAL HRTIM handle
06868   * @param  TimerIdx Timer index
06869   *                   This parameter can be one of the following values:
06870   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06871   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06872   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06873   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06874   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06875   * @retval None
06876   */
06877 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06878                                               uint32_t TimerIdx)
06879 {
06880   /* Prevent unused argument(s) compilation warning */
06881   UNUSED(hhrtim);
06882   UNUSED(TimerIdx);
06883
06884   /* NOTE : This function should not be modified, when the callback is needed,
06885             the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
06886    */
06887 }
06888
06889 /**
06890   * @brief  Callback function invoked when the timer x output 2 is set
06891   * @param  hhrtim pointer to HAL HRTIM handle
06892   * @param  TimerIdx Timer index
06893   *                   This parameter can be one of the following values:
06894   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06895   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06896   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06897   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06898   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06899   * @retval None
06900   */
06901 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
06902                                               uint32_t TimerIdx)
06903 {
06904   /* Prevent unused argument(s) compilation warning */
06905   UNUSED(hhrtim);
06906   UNUSED(TimerIdx);
06907
06908   /* NOTE : This function should not be modified, when the callback is needed,
06909             the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
06910    */
06911 }
06912
06913 /**
06914   * @brief  Callback function invoked when the timer x output 2 is reset
06915   * @param  hhrtim pointer to HAL HRTIM handle
06916   * @param  TimerIdx Timer index
06917   *                   This parameter can be one of the following values:
06918   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06919   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06920   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06921   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06922   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06923   * @retval None
06924   */
06925 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06926                                               uint32_t TimerIdx)
06927 {
06928   /* Prevent unused argument(s) compilation warning */
06929   UNUSED(hhrtim);
06930   UNUSED(TimerIdx);
06931
06932   /* NOTE : This function should not be modified, when the callback is needed,
06933             the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
06934    */
06935 }
06936
06937 /**
06938   * @brief  Callback function invoked when a DMA burst transfer is completed
06939   * @param  hhrtim pointer to HAL HRTIM handle
06940   * @param  TimerIdx Timer index
06941   *                   This parameter can be one of the following values:
06942   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06943   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06944   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06945   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06946   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06947   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06948   * @retval None
06949   */
06950 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
06951                                                uint32_t TimerIdx)
06952 {
06953   /* Prevent unused argument(s) compilation warning */
06954   UNUSED(hhrtim);
06955   UNUSED(TimerIdx);
06956
06957   /* NOTE : This function should not be modified, when the callback is needed,
06958             the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
06959    */
06960 }
06961
06962 /**
06963   * @brief  Callback function invoked when a DMA error occurs
06964   * @param  hhrtim pointer to HAL HRTIM handle
06965   * @retval None
06966   */
06967 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
06968 {
06969   /* Prevent unused argument(s) compilation warning */
06970   UNUSED(hhrtim);
06971
06972   /* NOTE : This function should not be modified, when the callback is needed,
06973             the HAL_HRTIM_ErrorCallback could be implemented in the user file
06974    */
06975 }
06976
06977 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
06978 /**
06979   * @brief  HRTIM callback function registration
06980   * @param  hhrtim pointer to HAL HRTIM handle
06981   * @param  CallbackID ID of the HRTIM callback function to register
06982   *                   This parameter can be one of the following values:
06983   *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
06984   *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
06985   *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
06986   *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
06987   *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
06988   *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
06989   *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
06990   *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
06991   *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
06992   *                   @arg HAL_HRTIM_MSPINIT_CB_ID
06993   *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
06994   * @param  pCallback Callback function pointer
06995   * @retval HAL status
06996   */
06997 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
06998                                              HAL_HRTIM_CallbackIDTypeDef CallbackID,
06999                                              pHRTIM_CallbackTypeDef      pCallback)
07000 {
07001   HAL_StatusTypeDef status = HAL_OK;
07002
07003   if (pCallback == NULL)
07004   {
07005     /* Update the state */
07006     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07007
07008     return HAL_ERROR;
07009   }
07010
07011   /* Process locked */
07012   __HAL_LOCK(hhrtim);
07013
07014   if (HAL_HRTIM_STATE_READY == hhrtim->State)
07015   {
07016     switch (CallbackID)
07017     {
07018       case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
07019         hhrtim->Fault1Callback = pCallback;
07020         break;
07021
07022       case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
07023         hhrtim->Fault2Callback = pCallback;
07024         break;
07025
07026       case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
07027         hhrtim->Fault3Callback = pCallback;
07028         break;
07029
07030       case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
07031         hhrtim->Fault4Callback = pCallback;
07032         break;
07033
07034       case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
07035         hhrtim->Fault5Callback = pCallback;
07036         break;
07037
07038       case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
07039         hhrtim->SystemFaultCallback = pCallback;
07040         break;
07041
07042
07043       case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
07044         hhrtim->BurstModePeriodCallback = pCallback;
07045         break;
07046
07047       case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
07048         hhrtim->SynchronizationEventCallback = pCallback;
07049         break;
07050
07051       case HAL_HRTIM_ERRORCALLBACK_CB_ID :
07052         hhrtim->ErrorCallback = pCallback;
07053         break;
07054
07055       case HAL_HRTIM_MSPINIT_CB_ID :
07056         hhrtim->MspInitCallback = pCallback;
07057         break;
07058
07059       case HAL_HRTIM_MSPDEINIT_CB_ID :
07060         hhrtim->MspDeInitCallback = pCallback;
07061         break;
07062
07063       default :
07064         /* Update the state */
07065         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07066
07067         /* Return error status */
07068         status = HAL_ERROR;
07069         break;
07070     }
07071   }
07072   else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
07073   {
07074     switch (CallbackID)
07075     {
07076       case HAL_HRTIM_MSPINIT_CB_ID :
07077         hhrtim->MspInitCallback = pCallback;
07078         break;
07079
07080       case HAL_HRTIM_MSPDEINIT_CB_ID :
07081         hhrtim->MspDeInitCallback = pCallback;
07082         break;
07083
07084       default :
07085         /* Update the state */
07086         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07087
07088         /* Return error status */
07089         status = HAL_ERROR;
07090         break;
07091     }
07092   }
07093   else
07094   {
07095     /* Update the state */
07096     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07097
07098     /* Return error status */
07099     status = HAL_ERROR;
07100   }
07101
07102   /* Release Lock */
07103   __HAL_UNLOCK(hhrtim);
07104
07105   return status;
07106 }
07107
07108 /**
07109   * @brief  HRTIM callback function un-registration
07110   * @param  hhrtim pointer to HAL HRTIM handle
07111   * @param  CallbackID ID of the HRTIM callback function to unregister
07112   *                   This parameter can be one of the following values:
07113   *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
07114   *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
07115   *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
07116   *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
07117   *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
07118   *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
07119   *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
07120   *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
07121   *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
07122   *                   @arg HAL_HRTIM_MSPINIT_CB_ID
07123   *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
07124   * @retval HAL status
07125   */
07126 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
07127                                                HAL_HRTIM_CallbackIDTypeDef CallbackID)
07128 {
07129   HAL_StatusTypeDef status = HAL_OK;
07130
07131   /* Process locked */
07132   __HAL_LOCK(hhrtim);
07133
07134   if (HAL_HRTIM_STATE_READY == hhrtim->State)
07135   {
07136     switch (CallbackID)
07137     {
07138     case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
07139       hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
07140       break;
07141
07142     case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
07143       hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
07144       break;
07145
07146     case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
07147       hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
07148       break;
07149
07150     case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
07151       hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
07152       break;
07153
07154     case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
07155       hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
07156       break;
07157
07158     case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
07159       hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
07160       break;
07161
07162
07163     case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
07164       hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
07165       break;
07166
07167     case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
07168       hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
07169       break;
07170
07171     case HAL_HRTIM_ERRORCALLBACK_CB_ID :
07172       hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
07173       break;
07174
07175     case HAL_HRTIM_MSPINIT_CB_ID :
07176       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
07177       break;
07178
07179     case HAL_HRTIM_MSPDEINIT_CB_ID :
07180       hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
07181       break;
07182
07183     default :
07184     /* Update the state */
07185     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07186
07187     /* Return error status */
07188     status = HAL_ERROR;
07189       break;
07190     }
07191   }
07192   else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
07193   {
07194     switch (CallbackID)
07195     {
07196     case HAL_HRTIM_MSPINIT_CB_ID :
07197       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
07198       break;
07199
07200     case HAL_HRTIM_MSPDEINIT_CB_ID :
07201       hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
07202       break;
07203
07204     default :
07205     /* Update the state */
07206     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07207
07208     /* Return error status */
07209     status =  HAL_ERROR;
07210       break;
07211     }
07212   }
07213   else
07214   {
07215     /* Update the state */
07216     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07217
07218     /* Return error status */
07219     status =  HAL_ERROR;
07220   }
07221
07222   /* Release Lock */
07223   __HAL_UNLOCK(hhrtim);
07224
07225   return status;
07226 }
07227
07228 /**
07229   * @brief  HRTIM Timer x callback function registration
07230   * @param  hhrtim pointer to HAL HRTIM handle
07231   * @param  CallbackID ID of the HRTIM Timer x callback function to register
07232   *                   This parameter can be one of the following values:
07233   *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
07234   *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
07235   *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
07236   *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
07237   *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
07238   *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
07239   *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
07240   *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
07241   *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
07242   *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
07243   *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
07244   *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
07245   *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
07246   *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
07247   *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
07248   * @param  pCallback Callback function pointer
07249   * @retval HAL status
07250   */
07251 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
07252                                                  HAL_HRTIM_CallbackIDTypeDef CallbackID,
07253                                                  pHRTIM_TIMxCallbackTypeDef pCallback)
07254 {
07255   HAL_StatusTypeDef status = HAL_OK;
07256
07257   if (pCallback == NULL)
07258   {
07259     /* Update the state */
07260     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07261
07262     return HAL_ERROR;
07263   }
07264
07265   /* Process locked */
07266   __HAL_LOCK(hhrtim);
07267
07268   if (HAL_HRTIM_STATE_READY == hhrtim->State)
07269   {
07270     switch (CallbackID)
07271     {
07272       case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
07273         hhrtim->RegistersUpdateCallback = pCallback;
07274         break;
07275
07276       case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
07277         hhrtim->RepetitionEventCallback = pCallback;
07278         break;
07279
07280       case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
07281         hhrtim->Compare1EventCallback = pCallback;
07282         break;
07283
07284       case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
07285         hhrtim->Compare2EventCallback = pCallback;
07286         break;
07287
07288       case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
07289         hhrtim->Compare3EventCallback = pCallback;
07290         break;
07291
07292       case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
07293         hhrtim->Compare4EventCallback = pCallback;
07294         break;
07295
07296       case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
07297         hhrtim->Capture1EventCallback = pCallback;
07298         break;
07299
07300       case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
07301         hhrtim->Capture2EventCallback = pCallback;
07302         break;
07303
07304       case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
07305         hhrtim->DelayedProtectionCallback = pCallback;
07306         break;
07307
07308       case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
07309         hhrtim->CounterResetCallback = pCallback;
07310         break;
07311
07312       case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
07313         hhrtim->Output1SetCallback = pCallback;
07314         break;
07315
07316       case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
07317         hhrtim->Output1ResetCallback = pCallback;
07318         break;
07319
07320       case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
07321         hhrtim->Output2SetCallback = pCallback;
07322         break;
07323
07324       case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
07325         hhrtim->Output2ResetCallback = pCallback;
07326         break;
07327
07328       case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
07329         hhrtim->BurstDMATransferCallback = pCallback;
07330         break;
07331
07332     default :
07333         /* Update the state */
07334         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07335
07336         /* Return error status */
07337         status = HAL_ERROR;
07338         break;
07339     }
07340   }
07341   else
07342   {
07343     /* Update the state */
07344     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07345
07346     /* Return error status */
07347     status = HAL_ERROR;
07348   }
07349
07350   /* Release Lock */
07351   __HAL_UNLOCK(hhrtim);
07352
07353   return status;
07354 }
07355
07356 /**
07357   * @brief  HRTIM Timer x callback function un-registration
07358   * @param  hhrtim pointer to HAL HRTIM handle
07359   * @param  CallbackID ID of the HRTIM callback Timer x function to unregister
07360   *                   This parameter can be one of the following values:
07361   *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
07362   *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
07363   *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
07364   *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
07365   *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
07366   *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
07367   *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
07368   *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
07369   *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
07370   *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
07371   *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
07372   *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
07373   *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
07374   *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
07375   *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
07376   * @retval HAL status
07377   */
07378 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
07379                                                    HAL_HRTIM_CallbackIDTypeDef CallbackID)
07380 {
07381   HAL_StatusTypeDef status = HAL_OK;
07382
07383   /* Process locked */
07384   __HAL_LOCK(hhrtim);
07385
07386   if (HAL_HRTIM_STATE_READY == hhrtim->State)
07387   {
07388     switch (CallbackID)
07389     {
07390       case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
07391         hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
07392         break;
07393
07394       case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
07395         hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
07396         break;
07397
07398       case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
07399         hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
07400         break;
07401
07402       case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
07403         hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
07404         break;
07405
07406       case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
07407         hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
07408         break;
07409
07410       case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
07411         hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
07412         break;
07413
07414       case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
07415         hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
07416         break;
07417
07418       case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
07419         hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
07420         break;
07421
07422       case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
07423         hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
07424         break;
07425
07426       case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
07427         hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
07428         break;
07429
07430       case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
07431         hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
07432         break;
07433
07434       case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
07435         hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
07436         break;
07437
07438       case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
07439         hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
07440         break;
07441
07442       case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
07443         hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
07444         break;
07445
07446       case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
07447         hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
07448         break;
07449
07450     default :
07451         /* Update the state */
07452         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07453
07454         /* Return error status */
07455         status = HAL_ERROR;
07456         break;
07457     }
07458   }
07459   else
07460   {
07461     /* Update the state */
07462     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
07463
07464     /* Return error status */
07465     status = HAL_ERROR;
07466   }
07467
07468   /* Release Lock */
07469   __HAL_UNLOCK(hhrtim);
07470
07471   return status;
07472 }
07473 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
07474 /**
07475   * @}
07476   */
07477
07478 /**
07479   * @}
07480   */
07481
07482 /** @addtogroup HRTIM_Private_Functions
07483   * @{
07484   */
07485
07486 /**
07487   * @brief  Configure the master timer time base
07488   * @param  hhrtim pointer to HAL HRTIM handle
07489   * @param  pTimeBaseCfg pointer to the time base configuration structure
07490   * @retval None
07491   */
07492 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
07493                                      HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
07494 {
07495   uint32_t hrtim_mcr;
07496
07497   /* Configure master timer */
07498   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
07499
07500   /* Set the prescaler ratio */
07501   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
07502   hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
07503
07504   /* Set the operating mode */
07505   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
07506   hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
07507
07508   /* Update the HRTIM registers */
07509   hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
07510   hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
07511   hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
07512 }
07513
07514 /**
07515   * @brief  Configure timing unit (Timer A to Timer E) time base
07516   * @param  hhrtim pointer to HAL HRTIM handle
07517   * @param  TimerIdx Timer index
07518   * @param  pTimeBaseCfg pointer to the time base configuration structure
07519   * @retval None
07520   */
07521 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
07522                                          uint32_t TimerIdx ,
07523                                          HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
07524 {
07525   uint32_t hrtim_timcr;
07526
07527   /* Configure master timing unit */
07528   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
07529
07530   /* Set the prescaler ratio */
07531   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
07532   hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
07533
07534   /* Set the operating mode */
07535   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
07536   hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
07537
07538   /* Update the HRTIM registers */
07539   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
07540   hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
07541   hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
07542 }
07543
07544 /**
07545   * @brief  Configure the master timer in waveform mode
07546   * @param  hhrtim pointer to HAL HRTIM handle
07547   * @param  pTimerCfg pointer to the timer configuration data structure
07548   * @retval None
07549   */
07550 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
07551                                          HRTIM_TimerCfgTypeDef * pTimerCfg)
07552 {
07553   uint32_t hrtim_mcr;
07554   uint32_t hrtim_bmcr;
07555
07556   /* Configure master timer */
07557   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
07558   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
07559
07560   /* Enable/Disable the half mode */
07561   hrtim_mcr &= ~(HRTIM_MCR_HALF);
07562   hrtim_mcr |= pTimerCfg->HalfModeEnable;
07563
07564   /* Enable/Disable the timer start upon synchronization event reception */
07565   hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
07566   hrtim_mcr |= pTimerCfg->StartOnSync;
07567
07568   /* Enable/Disable the timer reset upon synchronization event reception */
07569   hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
07570   hrtim_mcr |= pTimerCfg->ResetOnSync;
07571
07572   /* Enable/Disable the DAC synchronization event generation */
07573   hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
07574   hrtim_mcr |= pTimerCfg->DACSynchro;
07575
07576   /* Enable/Disable preload meachanism for timer registers */
07577   hrtim_mcr &= ~(HRTIM_MCR_PREEN);
07578   hrtim_mcr |= pTimerCfg->PreloadEnable;
07579
07580   /* Master timer registers update handling */
07581   hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
07582   hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
07583
07584   /* Enable/Disable registers update on repetition */
07585   hrtim_mcr &= ~(HRTIM_MCR_MREPU);
07586   hrtim_mcr |= pTimerCfg->RepetitionUpdate;
07587
07588   /* Set the timer burst mode */
07589   hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
07590   hrtim_bmcr |= pTimerCfg->BurstMode;
07591
07592   /* Update the HRTIM registers */
07593   hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
07594   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
07595 }
07596
07597 /**
07598   * @brief  Configure timing unit (Timer A to Timer E) in waveform mode
07599   * @param  hhrtim pointer to HAL HRTIM handle
07600   * @param  TimerIdx Timer index
07601   * @param  pTimerCfg pointer to the timer configuration data structure
07602   * @retval None
07603   */
07604 static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
07605                                              uint32_t TimerIdx,
07606                                              HRTIM_TimerCfgTypeDef * pTimerCfg)
07607 {
07608   uint32_t hrtim_timcr;
07609   uint32_t hrtim_timfltr;
07610   uint32_t hrtim_timoutr;
07611   uint32_t hrtim_timrstr;
07612   uint32_t hrtim_bmcr;
07613
07614   /* UPDGAT bitfield must be reset before programming a new value */
07615   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
07616
07617   /* Configure timing unit (Timer A to Timer E) */
07618   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
07619   hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
07620   hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
07621   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
07622
07623   /* Enable/Disable the half mode */
07624   hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
07625   hrtim_timcr |= pTimerCfg->HalfModeEnable;
07626
07627   /* Enable/Disable the timer start upon synchronization event reception */
07628   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
07629   hrtim_timcr |= pTimerCfg->StartOnSync;
07630
07631   /* Enable/Disable the timer reset upon synchronization event reception */
07632   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
07633   hrtim_timcr |= pTimerCfg->ResetOnSync;
07634
07635   /* Enable/Disable the DAC synchronization event generation */
07636   hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
07637   hrtim_timcr |= pTimerCfg->DACSynchro;
07638
07639   /* Enable/Disable preload meachanism for timer registers */
07640   hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
07641   hrtim_timcr |= pTimerCfg->PreloadEnable;
07642
07643   /* Timing unit registers update handling */
07644   hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
07645   hrtim_timcr |= pTimerCfg->UpdateGating;
07646
07647   /* Enable/Disable registers update on repetition */
07648   hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
07649   if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
07650   {
07651     hrtim_timcr |= HRTIM_TIMCR_TREPU;
07652   }
07653
07654   /* Set the push-pull mode */
07655   hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
07656   hrtim_timcr |= pTimerCfg->PushPull;
07657
07658   /* Enable/Disable registers update on timer counter reset */
07659   hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
07660   hrtim_timcr |= pTimerCfg->ResetUpdate;
07661
07662   /* Set the timer update trigger */
07663   hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
07664   hrtim_timcr |= pTimerCfg->UpdateTrigger;
07665
07666   /* Enable/Disable the fault channel at timer level */
07667   hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
07668   hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
07669
07670   /* Lock/Unlock fault sources at timer level */
07671   hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
07672   hrtim_timfltr |= pTimerCfg->FaultLock;
07673
07674   /* The deadtime cannot be used simultaneously with the push-pull mode */
07675   if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
07676   {
07677     /* Enable/Disable dead time insertion at timer level */
07678     hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
07679     hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
07680   }
07681
07682   /* Enable/Disable delayed protection at timer level
07683      Delayed Idle is available whatever the timer operating mode (regular, push-pull)
07684      Balanced Idle is only available in push-pull mode
07685   */
07686   if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
07687        && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
07688        || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
07689   {
07690     hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
07691     hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
07692   }
07693
07694   /* Set the timer counter reset trigger */
07695   hrtim_timrstr = pTimerCfg->ResetTrigger;
07696
07697   /* Set the timer burst mode */
07698   switch (TimerIdx)
07699   {
07700   case HRTIM_TIMERINDEX_TIMER_A:
07701     {
07702       hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
07703       hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
07704       break;
07705     }
07706
07707   case HRTIM_TIMERINDEX_TIMER_B:
07708     {
07709       hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
07710       hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
07711       break;
07712     }
07713
07714   case HRTIM_TIMERINDEX_TIMER_C:
07715     {
07716       hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
07717       hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
07718       break;
07719     }
07720
07721   case HRTIM_TIMERINDEX_TIMER_D:
07722     {
07723       hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
07724       hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
07725       break;
07726     }
07727
07728   case HRTIM_TIMERINDEX_TIMER_E:
07729     {
07730       hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
07731       hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
07732       break;
07733     }
07734
07735   default:
07736     break;
07737   }
07738
07739   /* Update the HRTIM registers */
07740   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
07741   hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
07742   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
07743   hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
07744   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
07745 }
07746
07747 /**
07748   * @brief  Configure a capture unit
07749   * @param  hhrtim pointer to HAL HRTIM handle
07750   * @param  TimerIdx Timer index
07751   * @param  CaptureUnit Capture unit identifier
07752   * @param  Event Event reference
07753   * @retval None
07754   */
07755 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
07756                                     uint32_t TimerIdx,
07757                                     uint32_t CaptureUnit,
07758                                     uint32_t Event)
07759 {
07760   uint32_t CaptureTrigger = 0xFFFFFFFFU;
07761
07762   switch (Event)
07763   {
07764   case HRTIM_EVENT_1:
07765     {
07766       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
07767       break;
07768     }
07769
07770   case HRTIM_EVENT_2:
07771     {
07772       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
07773       break;
07774     }
07775
07776   case HRTIM_EVENT_3:
07777     {
07778       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
07779       break;
07780     }
07781
07782   case HRTIM_EVENT_4:
07783     {
07784       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
07785       break;
07786     }
07787
07788   case HRTIM_EVENT_5:
07789     {
07790       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
07791       break;
07792     }
07793
07794   case HRTIM_EVENT_6:
07795     {
07796       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
07797       break;
07798     }
07799
07800   case HRTIM_EVENT_7:
07801     {
07802       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
07803       break;
07804     }
07805
07806   case HRTIM_EVENT_8:
07807     {
07808       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
07809       break;
07810     }
07811
07812   case HRTIM_EVENT_9:
07813     {
07814       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
07815       break;
07816     }
07817
07818   case HRTIM_EVENT_10:
07819     {
07820       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
07821       break;
07822     }
07823
07824   default:
07825     break;
07826   }
07827
07828   switch (CaptureUnit)
07829   {
07830   case HRTIM_CAPTUREUNIT_1:
07831     {
07832       hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
07833       break;
07834     }
07835
07836   case HRTIM_CAPTUREUNIT_2:
07837     {
07838       hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
07839       break;
07840     }
07841
07842   default:
07843     break;
07844   }
07845 }
07846
07847 /**
07848   * @brief  Configure the output of a timing unit
07849   * @param  hhrtim pointer to HAL HRTIM handle
07850   * @param  TimerIdx Timer index
07851   * @param  Output timing unit output identifier
07852   * @param  pOutputCfg pointer to the output configuration data structure
07853   * @retval None
07854   */
07855 static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
07856                                 uint32_t TimerIdx,
07857                                 uint32_t Output,
07858                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
07859 {
07860   uint32_t hrtim_outr;
07861   uint32_t hrtim_dtr;
07862
07863   uint32_t shift = 0U;
07864
07865   hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
07866   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
07867
07868   switch (Output)
07869   {
07870   case HRTIM_OUTPUT_TA1:
07871   case HRTIM_OUTPUT_TB1:
07872   case HRTIM_OUTPUT_TC1:
07873   case HRTIM_OUTPUT_TD1:
07874   case HRTIM_OUTPUT_TE1:
07875     {
07876       /* Set the output set/reset crossbar */
07877       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
07878       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
07879       break;
07880     }
07881
07882   case HRTIM_OUTPUT_TA2:
07883   case HRTIM_OUTPUT_TB2:
07884   case HRTIM_OUTPUT_TC2:
07885   case HRTIM_OUTPUT_TD2:
07886   case HRTIM_OUTPUT_TE2:
07887     {
07888       /* Set the output set/reset crossbar */
07889       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
07890       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
07891       shift = 16U;
07892       break;
07893     }
07894
07895   default:
07896     break;
07897   }
07898
07899   /* Clear output config */
07900   hrtim_outr &= ~((HRTIM_OUTR_POL1 |
07901                    HRTIM_OUTR_IDLM1 |
07902                    HRTIM_OUTR_IDLES1|
07903                    HRTIM_OUTR_FAULT1|
07904                    HRTIM_OUTR_CHP1 |
07905                    HRTIM_OUTR_DIDL1) << shift);
07906
07907   /* Set the polarity */
07908   hrtim_outr |= (pOutputCfg->Polarity << shift);
07909
07910   /* Set the IDLE mode */
07911   hrtim_outr |= (pOutputCfg->IdleMode << shift);
07912
07913   /* Set the IDLE state */
07914   hrtim_outr |= (pOutputCfg->IdleLevel << shift);
07915
07916   /* Set the FAULT state */
07917   hrtim_outr |= (pOutputCfg->FaultLevel << shift);
07918
07919   /* Set the chopper mode */
07920   hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
07921
07922   /* Set the burst mode entry mode : deadtime insertion when entering the idle
07923      state during a burst mode operation is allowed only under the following
07924      conditions:
07925      - the outputs is active during the burst mode (IDLES=1U)
07926      - positive deadtimes (SDTR/SDTF set to 0U)
07927   */
07928   if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
07929       ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
07930       ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
07931   {
07932     hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
07933   }
07934
07935   /* Update HRTIM register */
07936   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
07937 }
07938
07939 /**
07940   * @brief  Configure an external event channel
07941   * @param  hhrtim pointer to HAL HRTIM handle
07942   * @param  Event Event channel identifier
07943   * @param  pEventCfg pointer to the event channel configuration data structure
07944   * @retval None
07945   */
07946 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
07947                               uint32_t Event,
07948                               HRTIM_EventCfgTypeDef *pEventCfg)
07949 {
07950   uint32_t hrtim_eecr1;
07951   uint32_t hrtim_eecr2;
07952   uint32_t hrtim_eecr3;
07953
07954   /* Configure external event channel */
07955   hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
07956   hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
07957   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
07958
07959   switch (Event)
07960   {
07961   case HRTIM_EVENT_NONE:
07962     {
07963       /* Update the HRTIM registers */
07964       hhrtim->Instance->sCommonRegs.EECR1 = 0U;
07965       hhrtim->Instance->sCommonRegs.EECR2 = 0U;
07966       hhrtim->Instance->sCommonRegs.EECR3 = 0U;
07967       break;
07968     }
07969
07970   case HRTIM_EVENT_1:
07971     {
07972       hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
07973       hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
07974       hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
07975       hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
07976       /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
07977       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07978       /* Update the HRTIM registers (EE1FAST bit) */
07979       hrtim_eecr1 |= (pEventCfg->FastMode  & HRTIM_EECR1_EE1FAST);
07980       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07981       break;
07982     }
07983
07984   case HRTIM_EVENT_2:
07985     {
07986       hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
07987       hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
07988       hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
07989       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
07990       /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
07991       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07992       /* Update the HRTIM registers (EE2FAST bit) */
07993       hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
07994       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
07995       break;
07996     }
07997
07998   case HRTIM_EVENT_3:
07999     {
08000       hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
08001       hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
08002       hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
08003       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
08004       /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
08005       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08006       /* Update the HRTIM registers (EE3FAST bit) */
08007       hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
08008       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08009       break;
08010     }
08011
08012   case HRTIM_EVENT_4:
08013     {
08014       hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
08015       hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
08016       hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
08017       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
08018       /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
08019       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08020       /* Update the HRTIM registers (EE4FAST bit) */
08021       hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
08022       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08023       break;
08024     }
08025
08026   case HRTIM_EVENT_5:
08027     {
08028       hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
08029       hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
08030       hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
08031       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
08032       /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
08033       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08034       /* Update the HRTIM registers (EE5FAST bit) */
08035       hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
08036       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
08037       break;
08038     }
08039
08040   case HRTIM_EVENT_6:
08041     {
08042       hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
08043       hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
08044       hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
08045       hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
08046       hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
08047       hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
08048       /* Update the HRTIM registers */
08049       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
08050       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
08051       break;
08052     }
08053
08054   case HRTIM_EVENT_7:
08055     {
08056       hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
08057       hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
08058       hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
08059       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
08060       hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
08061       hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
08062       /* Update the HRTIM registers */
08063       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
08064       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
08065       break;
08066     }
08067
08068   case HRTIM_EVENT_8:
08069     {
08070       hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
08071       hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
08072       hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
08073       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
08074       hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
08075       hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
08076       /* Update the HRTIM registers */
08077       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
08078       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
08079       break;
08080     }
08081
08082   case HRTIM_EVENT_9:
08083     {
08084       hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
08085       hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
08086       hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
08087       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
08088       hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
08089       hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
08090       /* Update the HRTIM registers */
08091       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
08092       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
08093       break;
08094     }
08095
08096   case HRTIM_EVENT_10:
08097     {
08098       hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
08099       hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
08100       hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
08101       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
08102       hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
08103       hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
08104       /* Update the HRTIM registers */
08105       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
08106       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
08107       break;
08108     }
08109
08110   default:
08111     break;
08112   }
08113 }
08114
08115 /**
08116   * @brief  Configure the timer counter reset
08117   * @param  hhrtim pointer to HAL HRTIM handle
08118   * @param  TimerIdx Timer index
08119   * @param  Event Event channel identifier
08120   * @retval None
08121   */
08122 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
08123                                   uint32_t TimerIdx,
08124                                   uint32_t Event)
08125 {
08126   switch (Event)
08127   {
08128   case HRTIM_EVENT_1:
08129     {
08130       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
08131       break;
08132     }
08133
08134   case HRTIM_EVENT_2:
08135     {
08136       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
08137       break;
08138     }
08139
08140   case HRTIM_EVENT_3:
08141     {
08142       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
08143       break;
08144     }
08145
08146   case HRTIM_EVENT_4:
08147     {
08148       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
08149       break;
08150     }
08151
08152   case HRTIM_EVENT_5:
08153     {
08154       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
08155       break;
08156     }
08157
08158   case HRTIM_EVENT_6:
08159     {
08160       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
08161       break;
08162     }
08163
08164   case HRTIM_EVENT_7:
08165     {
08166       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
08167       break;
08168     }
08169
08170   case HRTIM_EVENT_8:
08171     {
08172       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
08173       break;
08174     }
08175
08176   case HRTIM_EVENT_9:
08177     {
08178       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
08179       break;
08180     }
08181
08182   case HRTIM_EVENT_10:
08183     {
08184       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
08185       break;
08186     }
08187
08188   default:
08189     break;
08190   }
08191 }
08192
08193 /**
08194   * @brief  Return the interrupt to enable or disable according to the
08195   *         OC mode.
08196   * @param  hhrtim pointer to HAL HRTIM handle
08197   * @param  TimerIdx Timer index
08198   * @param  OCChannel Timer output
08199   *                    This parameter can be one of the following values:
08200   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
08201   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
08202   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
08203   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
08204   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
08205   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
08206   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
08207   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
08208   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
08209   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
08210   * @retval Interrupt to enable or disable
08211   */
08212 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
08213                                       uint32_t TimerIdx,
08214                                       uint32_t OCChannel)
08215 {
08216   uint32_t hrtim_set;
08217   uint32_t hrtim_reset;
08218   uint32_t interrupt = 0U;
08219
08220   switch (OCChannel)
08221   {
08222   case HRTIM_OUTPUT_TA1:
08223   case HRTIM_OUTPUT_TB1:
08224   case HRTIM_OUTPUT_TC1:
08225   case HRTIM_OUTPUT_TD1:
08226   case HRTIM_OUTPUT_TE1:
08227     {
08228       /* Retreives actual OC mode and set interrupt accordingly */
08229       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
08230       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
08231
08232       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
08233           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
08234       {
08235         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
08236         interrupt = HRTIM_TIM_IT_CMP1;
08237       }
08238       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
08239                (hrtim_reset == 0U))
08240       {
08241          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
08242         interrupt = HRTIM_TIM_IT_SET1;
08243       }
08244       else if ((hrtim_set == 0U) &&
08245                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
08246       {
08247          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
08248         interrupt = HRTIM_TIM_IT_RST1;
08249       }
08250       else
08251       {
08252        /* nothing to do */
08253       }
08254       break;
08255     }
08256
08257   case HRTIM_OUTPUT_TA2:
08258   case HRTIM_OUTPUT_TB2:
08259   case HRTIM_OUTPUT_TC2:
08260   case HRTIM_OUTPUT_TD2:
08261   case HRTIM_OUTPUT_TE2:
08262     {
08263       /* Retreives actual OC mode and set interrupt accordingly */
08264       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
08265       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
08266
08267       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
08268           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
08269       {
08270         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
08271         interrupt = HRTIM_TIM_IT_CMP2;
08272       }
08273       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
08274                (hrtim_reset == 0U))
08275       {
08276          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
08277         interrupt = HRTIM_TIM_IT_SET2;
08278       }
08279       else if ((hrtim_set == 0U) &&
08280                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
08281       {
08282          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
08283         interrupt = HRTIM_TIM_IT_RST2;
08284       }
08285       else
08286       {
08287        /* nothing to do */
08288       }
08289       break;
08290     }
08291
08292   default:
08293     break;
08294   }
08295
08296   return interrupt;
08297 }
08298
08299 /**
08300   * @brief  Return the DMA request to enable or disable according to the
08301   *         OC mode.
08302   * @param  hhrtim pointer to HAL HRTIM handle
08303   * @param  TimerIdx Timer index
08304   * @param  OCChannel Timer output
08305   *                    This parameter can be one of the following values:
08306   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
08307   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
08308   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
08309   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
08310   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
08311   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
08312   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
08313   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
08314   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
08315   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
08316   * @retval DMA request to enable or disable
08317   */
08318 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
08319                                        uint32_t TimerIdx,
08320                                        uint32_t OCChannel)
08321 {
08322   uint32_t hrtim_set;
08323   uint32_t hrtim_reset;
08324   uint32_t dma_request = 0U;
08325
08326   switch (OCChannel)
08327   {
08328   case HRTIM_OUTPUT_TA1:
08329   case HRTIM_OUTPUT_TB1:
08330   case HRTIM_OUTPUT_TC1:
08331   case HRTIM_OUTPUT_TD1:
08332   case HRTIM_OUTPUT_TE1:
08333     {
08334       /* Retreives actual OC mode and set dma_request accordingly */
08335       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
08336       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
08337
08338       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
08339           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
08340       {
08341         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
08342         dma_request = HRTIM_TIM_DMA_CMP1;
08343       }
08344       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
08345                (hrtim_reset == 0U))
08346       {
08347          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
08348         dma_request = HRTIM_TIM_DMA_SET1;
08349       }
08350       else if ((hrtim_set == 0U) &&
08351                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
08352       {
08353          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
08354         dma_request = HRTIM_TIM_DMA_RST1;
08355       }
08356       else
08357       {
08358     /* nothing to do */
08359       }
08360       break;
08361     }
08362
08363   case HRTIM_OUTPUT_TA2:
08364   case HRTIM_OUTPUT_TB2:
08365   case HRTIM_OUTPUT_TC2:
08366   case HRTIM_OUTPUT_TD2:
08367   case HRTIM_OUTPUT_TE2:
08368     {
08369       /* Retreives actual OC mode and set dma_request accordingly */
08370       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
08371       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
08372
08373       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
08374           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
08375       {
08376         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
08377         dma_request = HRTIM_TIM_DMA_CMP2;
08378       }
08379       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
08380                (hrtim_reset == 0U))
08381       {
08382          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
08383         dma_request = HRTIM_TIM_DMA_SET2;
08384       }
08385       else if ((hrtim_set == 0U) &&
08386                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
08387       {
08388          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
08389         dma_request = HRTIM_TIM_DMA_RST2;
08390       }
08391       else
08392       {
08393     /* nothing to do */
08394       }
08395       break;
08396     }
08397
08398   default:
08399     break;
08400   }
08401
08402   return dma_request;
08403 }
08404
08405 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
08406                                                           uint32_t TimerIdx)
08407 {
08408   DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
08409
08410   switch (TimerIdx)
08411   {
08412   case HRTIM_TIMERINDEX_MASTER:
08413     {
08414       hdma = hhrtim->hdmaMaster;
08415       break;
08416     }
08417
08418   case HRTIM_TIMERINDEX_TIMER_A:
08419     {
08420       hdma = hhrtim->hdmaTimerA;
08421       break;
08422     }
08423
08424   case HRTIM_TIMERINDEX_TIMER_B:
08425     {
08426       hdma = hhrtim->hdmaTimerB;
08427       break;
08428     }
08429
08430   case HRTIM_TIMERINDEX_TIMER_C:
08431     {
08432       hdma = hhrtim->hdmaTimerC;
08433       break;
08434     }
08435
08436   case HRTIM_TIMERINDEX_TIMER_D:
08437     {
08438       hdma = hhrtim->hdmaTimerD;
08439       break;
08440     }
08441
08442   case HRTIM_TIMERINDEX_TIMER_E:
08443     {
08444       hdma = hhrtim->hdmaTimerE;
08445       break;
08446     }
08447
08448   default:
08449     break;
08450   }
08451
08452   return hdma;
08453 }
08454
08455 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
08456                                          DMA_HandleTypeDef * hdma)
08457 {
08458   uint32_t timed_idx = 0xFFFFFFFFU;
08459
08460   if (hdma == hhrtim->hdmaMaster)
08461   {
08462     timed_idx = HRTIM_TIMERINDEX_MASTER;
08463   }
08464   else if (hdma == hhrtim->hdmaTimerA)
08465   {
08466     timed_idx = HRTIM_TIMERINDEX_TIMER_A;
08467   }
08468   else if (hdma == hhrtim->hdmaTimerB)
08469   {
08470     timed_idx = HRTIM_TIMERINDEX_TIMER_B;
08471   }
08472   else if (hdma == hhrtim->hdmaTimerC)
08473   {
08474     timed_idx = HRTIM_TIMERINDEX_TIMER_C;
08475   }
08476   else if (hdma == hhrtim->hdmaTimerD)
08477   {
08478     timed_idx = HRTIM_TIMERINDEX_TIMER_D;
08479   }
08480   else if (hdma == hhrtim->hdmaTimerE)
08481   {
08482     timed_idx = HRTIM_TIMERINDEX_TIMER_E;
08483   }
08484   else
08485   {
08486     /* nothing to do */
08487   }
08488   return timed_idx;
08489 }
08490
08491 /**
08492   * @brief  Force an immediate transfer from the preload to the active
08493   *         registers.
08494   * @param  hhrtim pointer to HAL HRTIM handle
08495   * @param  TimerIdx Timer index
08496   * @retval None
08497   */
08498 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
08499                                        uint32_t TimerIdx)
08500 {
08501   switch (TimerIdx)
08502   {
08503   case HRTIM_TIMERINDEX_MASTER:
08504     {
08505       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
08506       break;
08507     }
08508
08509   case HRTIM_TIMERINDEX_TIMER_A:
08510     {
08511       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
08512       break;
08513     }
08514
08515   case HRTIM_TIMERINDEX_TIMER_B:
08516     {
08517       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
08518       break;
08519     }
08520
08521   case HRTIM_TIMERINDEX_TIMER_C:
08522     {
08523       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
08524       break;
08525     }
08526
08527   case HRTIM_TIMERINDEX_TIMER_D:
08528     {
08529       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
08530       break;
08531     }
08532
08533   case HRTIM_TIMERINDEX_TIMER_E:
08534     {
08535       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
08536       break;
08537     }
08538
08539   default:
08540     break;
08541   }
08542 }
08543
08544
08545 /**
08546   * @brief  HRTIM interrupts service routine
08547   * @param  hhrtim pointer to HAL HRTIM handle
08548   * @retval None
08549   */
08550 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
08551 {
08552   /* Fault 1 event */
08553   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET)
08554   {
08555     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
08556     {
08557       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
08558
08559       /* Invoke Fault 1 event callback */
08560 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08561       hhrtim->Fault1Callback(hhrtim);
08562 #else
08563       HAL_HRTIM_Fault1Callback(hhrtim);
08564 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08565     }
08566   }
08567
08568   /* Fault 2 event */
08569   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET)
08570   {
08571     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
08572     {
08573       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
08574
08575       /* Invoke Fault 2 event callback */
08576 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08577       hhrtim->Fault2Callback(hhrtim);
08578 #else
08579       HAL_HRTIM_Fault2Callback(hhrtim);
08580 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08581     }
08582   }
08583
08584   /* Fault 3 event */
08585   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET)
08586   {
08587     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
08588     {
08589       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
08590
08591       /* Invoke Fault 3 event callback */
08592 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08593       hhrtim->Fault3Callback(hhrtim);
08594 #else
08595       HAL_HRTIM_Fault3Callback(hhrtim);
08596 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08597     }
08598   }
08599
08600   /* Fault 4 event */
08601   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET)
08602   {
08603     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
08604     {
08605       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
08606
08607       /* Invoke Fault 4 event callback */
08608 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08609       hhrtim->Fault4Callback(hhrtim);
08610 #else
08611       HAL_HRTIM_Fault4Callback(hhrtim);
08612 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08613     }
08614   }
08615
08616   /* Fault 5 event */
08617   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET)
08618   {
08619     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
08620     {
08621       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
08622
08623       /* Invoke Fault 5 event callback */
08624 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08625       hhrtim->Fault5Callback(hhrtim);
08626 #else
08627       HAL_HRTIM_Fault5Callback(hhrtim);
08628 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08629     }
08630   }
08631
08632   /* System fault event */
08633   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
08634   {
08635     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
08636     {
08637       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
08638
08639       /* Invoke System fault event callback */
08640 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08641       hhrtim->SystemFaultCallback(hhrtim);
08642 #else
08643       HAL_HRTIM_SystemFaultCallback(hhrtim);
08644 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08645     }
08646   }
08647 }
08648
08649 /**
08650 * @brief  Master timer interrupts service routine
08651 * @param  hhrtim pointer to HAL HRTIM handle
08652 * @retval None
08653 */
08654 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
08655 {
08656   /* Burst mode period event */
08657   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET)
08658   {
08659     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
08660     {
08661       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
08662
08663       /* Invoke Burst mode period event callback */
08664 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08665       hhrtim->BurstModePeriodCallback(hhrtim);
08666 #else
08667       HAL_HRTIM_BurstModePeriodCallback(hhrtim);
08668 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08669     }
08670   }
08671
08672   /* Master timer compare 1 event */
08673   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
08674   {
08675     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
08676     {
08677       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
08678
08679       /* Invoke compare 1 event callback */
08680 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08681       hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08682 #else
08683       HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08684 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08685     }
08686   }
08687
08688   /* Master timer compare 2 event */
08689   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
08690   {
08691     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
08692     {
08693       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
08694
08695       /* Invoke compare 2 event callback */
08696 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08697       hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08698 #else
08699       HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08700 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08701     }
08702   }
08703
08704   /* Master timer compare 3 event */
08705   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
08706   {
08707     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
08708     {
08709       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
08710
08711       /* Invoke compare 3 event callback */
08712 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08713       hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08714 #else
08715       HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08716 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08717     }
08718   }
08719
08720   /* Master timer compare 4 event */
08721   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
08722   {
08723     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
08724     {
08725       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
08726
08727       /* Invoke compare 4 event callback */
08728 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08729       hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08730 #else
08731       HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08732 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08733     }
08734   }
08735
08736   /* Master timer repetition event */
08737   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
08738   {
08739     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
08740     {
08741       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
08742
08743       /* Invoke repetition event callback */
08744 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08745       hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08746 #else
08747       HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08748 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08749     }
08750   }
08751
08752   /* Synchronization input event */
08753   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
08754   {
08755     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
08756     {
08757       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
08758
08759       /* Invoke synchronization event callback */
08760 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08761       hhrtim->SynchronizationEventCallback(hhrtim);
08762 #else
08763       HAL_HRTIM_SynchronizationEventCallback(hhrtim);
08764 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08765     }
08766   }
08767
08768   /* Master timer registers update event */
08769   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
08770   {
08771     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
08772     {
08773       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
08774
08775       /* Invoke registers update event callback */
08776 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08777       hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08778 #else
08779       HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
08780 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08781     }
08782   }
08783 }
08784
08785 /**
08786   * @brief  Timer interrupts service routine
08787   * @param  hhrtim pointer to HAL HRTIM handle
08788   * @param  TimerIdx Timer index
08789   *                   This parameter can be one of the following values:
08790   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08791   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08792   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08793   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08794   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08795   * @retval None
08796 */
08797 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
08798                      uint32_t TimerIdx)
08799 {
08800   /* Timer compare 1 event */
08801   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
08802   {
08803     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
08804     {
08805       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
08806
08807       /* Invoke compare 1 event callback */
08808 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08809       hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
08810 #else
08811       HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
08812 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08813     }
08814   }
08815
08816   /* Timer compare 2 event */
08817   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
08818   {
08819     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
08820     {
08821       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
08822
08823       /* Invoke compare 2 event callback */
08824 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08825       hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
08826 #else
08827       HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
08828 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08829     }
08830   }
08831
08832   /* Timer compare 3 event */
08833   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
08834   {
08835     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
08836     {
08837       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
08838
08839       /* Invoke compare 3 event callback */
08840 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08841       hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
08842 #else
08843       HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
08844 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08845     }
08846   }
08847
08848   /* Timer compare 4 event */
08849   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
08850   {
08851     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
08852     {
08853       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
08854
08855       /* Invoke compare 4 event callback */
08856 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08857       hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
08858 #else
08859       HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
08860 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08861     }
08862   }
08863
08864   /* Timer repetition event */
08865   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
08866   {
08867     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
08868     {
08869       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
08870
08871       /* Invoke repetition event callback */
08872 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08873       hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
08874 #else
08875       HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
08876 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08877     }
08878   }
08879
08880   /* Timer registers update event */
08881   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
08882   {
08883     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
08884     {
08885       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
08886
08887       /* Invoke registers update event callback */
08888 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08889       hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
08890 #else
08891       HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
08892 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08893     }
08894   }
08895
08896   /* Timer capture 1 event */
08897   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
08898   {
08899     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
08900     {
08901       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
08902
08903       /* Invoke capture 1 event callback */
08904 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08905       hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
08906 #else
08907       HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
08908 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08909     }
08910   }
08911
08912   /* Timer capture 2 event */
08913   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
08914   {
08915     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
08916     {
08917       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
08918
08919       /* Invoke capture 2 event callback */
08920 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08921       hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
08922 #else
08923       HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
08924 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08925     }
08926   }
08927
08928   /* Timer output 1 set event */
08929   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
08930   {
08931     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
08932     {
08933       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
08934
08935       /* Invoke output 1 set event callback */
08936 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08937       hhrtim->Output1SetCallback(hhrtim, TimerIdx);
08938 #else
08939       HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
08940 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08941     }
08942   }
08943
08944   /* Timer output 1 reset event */
08945   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
08946   {
08947     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
08948     {
08949       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
08950
08951       /* Invoke output 1 reset event callback */
08952 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08953       hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
08954 #else
08955       HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
08956 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08957     }
08958   }
08959
08960   /* Timer output 2 set event */
08961   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
08962   {
08963     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
08964     {
08965       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
08966
08967       /* Invoke output 2 set event callback */
08968 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08969       hhrtim->Output2SetCallback(hhrtim, TimerIdx);
08970 #else
08971       HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
08972 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08973     }
08974   }
08975
08976   /* Timer output 2 reset event */
08977   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
08978   {
08979     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
08980     {
08981       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
08982
08983       /* Invoke output 2 reset event callback */
08984 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08985       hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
08986 #else
08987       HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
08988 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
08989     }
08990   }
08991
08992   /* Timer reset event */
08993   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
08994   {
08995     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
08996     {
08997       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
08998
08999       /* Invoke timer reset callback */
09000 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09001       hhrtim->CounterResetCallback(hhrtim, TimerIdx);
09002 #else
09003       HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
09004 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09005     }
09006   }
09007
09008   /* Delayed protection event */
09009   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
09010   {
09011     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
09012     {
09013       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
09014
09015       /* Invoke delayed protection callback */
09016 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09017       hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
09018 #else
09019       HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
09020 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09021     }
09022   }
09023 }
09024
09025 /**
09026   * @brief  DMA callback invoked upon master timer related DMA request completion
09027   * @param  hdma pointer to DMA handle.
09028   * @retval None
09029   */
09030 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
09031 {
09032   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
09033
09034   if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
09035   {
09036 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09037     hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09038 #else
09039     HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09040 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09041   }
09042   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
09043   {
09044 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09045     hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09046 #else
09047     HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09048 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09049   }
09050   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
09051   {
09052 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09053     hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09054 #else
09055     HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09056 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09057   }
09058   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
09059   {
09060 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09061     hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09062 #else
09063     HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09064 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09065   }
09066   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
09067   {
09068 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09069     hrtim->SynchronizationEventCallback(hrtim);
09070 #else
09071     HAL_HRTIM_SynchronizationEventCallback(hrtim);
09072 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09073   }
09074   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
09075   {
09076 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09077     hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09078 #else
09079     HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09080 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09081   }
09082   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
09083   {
09084 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09085     hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09086 #else
09087     HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
09088 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09089   }
09090   else
09091   {
09092     /* nothing to do */
09093   }
09094 }
09095
09096 /**
09097   * @brief  DMA callback invoked upon timer A..E related DMA request completion
09098   * @param  hdma pointer to DMA handle.
09099   * @retval None
09100   */
09101 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
09102 {
09103   uint8_t timer_idx;
09104
09105   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
09106
09107   timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
09108
09109   if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
09110
09111   if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
09112   {
09113 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09114     hrtim->Compare1EventCallback(hrtim, timer_idx);
09115 #else
09116     HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
09117 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09118   }
09119   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
09120   {
09121 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09122     hrtim->Compare2EventCallback(hrtim, timer_idx);
09123 #else
09124     HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
09125 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09126   }
09127   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
09128   {
09129 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09130     hrtim->Compare3EventCallback(hrtim, timer_idx);
09131 #else
09132     HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
09133 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09134   }
09135   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
09136   {
09137 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09138     hrtim->Compare4EventCallback(hrtim, timer_idx);
09139 #else
09140     HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
09141 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09142   }
09143   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
09144   {
09145 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09146     hrtim->RegistersUpdateCallback(hrtim, timer_idx);
09147 #else
09148     HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
09149 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09150   }
09151   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
09152   {
09153 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09154     hrtim->Capture1EventCallback(hrtim, timer_idx);
09155 #else
09156     HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
09157 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09158   }
09159   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
09160   {
09161 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09162     hrtim->Capture2EventCallback(hrtim, timer_idx);
09163 #else
09164     HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
09165 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09166   }
09167   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
09168   {
09169 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09170     hrtim->Output1SetCallback(hrtim, timer_idx);
09171 #else
09172     HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
09173 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09174   }
09175   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
09176   {
09177 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09178     hrtim->Output1ResetCallback(hrtim, timer_idx);
09179 #else
09180     HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
09181 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09182   }
09183   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
09184   {
09185 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09186     hrtim->Output2SetCallback(hrtim, timer_idx);
09187 #else
09188     HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
09189 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09190   }
09191   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
09192   {
09193 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09194     hrtim->Output2ResetCallback(hrtim, timer_idx);
09195 #else
09196     HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
09197 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09198   }
09199   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
09200   {
09201 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09202     hrtim->CounterResetCallback(hrtim, timer_idx);
09203 #else
09204     HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
09205 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09206   }
09207   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
09208   {
09209 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09210     hrtim->DelayedProtectionCallback(hrtim, timer_idx);
09211 #else
09212     HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
09213 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09214   }
09215   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
09216   {
09217 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09218     hrtim->RepetitionEventCallback(hrtim, timer_idx);
09219 #else
09220     HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
09221 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09222   }
09223   else
09224   {
09225     /* nothing to do */
09226   }
09227 }
09228
09229 /**
09230 * @brief  DMA error callback
09231 * @param  hdma pointer to DMA handle.
09232 * @retval None
09233 */
09234 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
09235 {
09236   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
09237
09238 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09239     hrtim->ErrorCallback(hrtim);
09240 #else
09241   HAL_HRTIM_ErrorCallback(hrtim);
09242 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09243 }
09244
09245 /**
09246   * @brief  DMA callback invoked upon burst DMA transfer completion
09247   * @param  hdma pointer to DMA handle.
09248   * @retval None
09249   */
09250 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
09251 {
09252   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
09253
09254 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
09255     hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
09256 #else
09257   HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
09258 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09259 }
09260
09261 /**
09262   * @}
09263   */
09264
09265 /**
09266   * @}
09267   */
09268
09269 #endif /* HRTIM1 */
09270
09271 #endif /* HAL_HRTIM_MODULE_ENABLED */
09272
09273 /**
09274   * @}
09275   */
09276
09277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hrtim.h Source File

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stm32h7xx_hal_hrtim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_HRTIM_H
00022 #define STM32H7xx_HAL_HRTIM_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined(HRTIM1)
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup HRTIM HRTIM
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
00042   * @{
00043   */
00044 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
00045   * @{
00046   */
00047 #define MAX_HRTIM_TIMER 6U
00048 /**
00049   * @}
00050   */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
00056   * @{
00057   */
00058
00059 /**
00060   * @brief  HRTIM Configuration Structure definition - Time base related parameters
00061   */
00062 typedef struct
00063 {
00064   uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
00065                                           This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
00066   uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.
00067                                           The HRTIM instance can be configured to act as a slave (waiting for a trigger
00068                                           to be synchronized) or a master (generating a synchronization signal) or both.
00069                                           This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
00070   uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when
00071                                           the HRTIM instance is configured as a slave).
00072                                           This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
00073   uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
00074                                          (significant only when the HRTIM instance is configured as a master).
00075                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
00076   uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization
00077                                           outputs (significant only when the HRTIM instance is configured as a master).
00078                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
00079 } HRTIM_InitTypeDef;
00080
00081 /**
00082   * @brief  HAL State structures definition
00083   */
00084 typedef enum
00085 {
00086   HAL_HRTIM_STATE_RESET            = 0x00U,    /*!< Peripheral is not yet Initialized                  */
00087   HAL_HRTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00088   HAL_HRTIM_STATE_BUSY             = 0x02U,    /*!< an internal process is ongoing                     */
00089   HAL_HRTIM_STATE_TIMEOUT          = 0x06U,    /*!< Timeout state                                      */
00090   HAL_HRTIM_STATE_ERROR            = 0x07U,    /*!< Error state                                        */
00091 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00092   HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U    /*!< Invalid Callback error */
00093 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00094 } HAL_HRTIM_StateTypeDef;
00095
00096 /**
00097   * @brief HRTIM Timer Structure definition
00098   */
00099 typedef struct
00100 {
00101   uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
00102                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00103                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00104   uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
00105                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00106                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00107   uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
00108   uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
00109   uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
00110   uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
00111   uint32_t DMASize;                /*!< Size of the DMA transfer */
00112 } HRTIM_TimerParamTypeDef;
00113
00114 /**
00115   * @brief  HRTIM Handle Structure definition
00116   */
00117 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00118 typedef struct __HRTIM_HandleTypeDef
00119 #else
00120 typedef struct
00121 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00122 {
00123   HRTIM_TypeDef *              Instance;                     /*!< Register base address */
00124
00125   HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
00126
00127   HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
00128
00129   HAL_LockTypeDef              Lock;                         /*!< Locking object          */
00130
00131   __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
00132
00133   DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */
00134   DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */
00135   DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */
00136   DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */
00137   DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */
00138   DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */
00139
00140 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00141   void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 1 interrupt callback function pointer                         */
00142   void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 2 interrupt callback function pointer                         */
00143   void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 3 interrupt callback function pointer                         */
00144   void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 4 interrupt callback function pointer                         */
00145   void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 5 interrupt callback function pointer                         */
00146   void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                          /*!< System fault interrupt callback function pointer                    */
00147   void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                      /*!< Burst mode period interrupt callback function pointer               */
00148   void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                 /*!< Sync Input interrupt callback function pointer                      */
00149   void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                                /*!< DMA error callback function pointer                                 */
00150
00151   void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Update interrupt callback function pointer                  */
00152   void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Repetition interrupt callback function pointer              */
00153   void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 1 match interrupt callback function pointer         */
00154   void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 2 match interrupt callback function pointer         */
00155   void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 3 match interrupt callback function pointer         */
00156   void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 4 match interrupt callback function pointer         */
00157   void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 1 interrupts callback function pointer              */
00158   void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 2 interrupts callback function pointer              */
00159   void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer      */
00160   void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x counter reset/roll-over interrupt callback function pointer */
00161   void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 1 set interrupt callback function pointer            */
00162   void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 1 reset interrupt callback function pointer          */
00163   void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 2 set interrupt callback function pointer            */
00164   void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 2 reset interrupt callback function pointer          */
00165   void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);  /*!< Timer x Burst DMA completed interrupt callback function pointer     */
00166
00167   void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                              /*!< HRTIM MspInit callback function pointer                             */
00168   void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                            /*!< HRTIM MspInit callback function pointer                             */
00169 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00170 } HRTIM_HandleTypeDef;
00171
00172 /**
00173   * @brief  Simple output compare mode configuration definition
00174   */
00175 typedef struct
00176 {
00177   uint32_t Period;                   /*!< Specifies the timer period.
00178                                           The period value must be above 3 periods of the fHRTIM clock.
00179                                           Maximum value is = 0xFFDFU */
00180   uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.
00181                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00182   uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
00183                                           This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
00184   uint32_t Mode;                     /*!< Specifies the counter operating mode.
00185                                           This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */
00186 } HRTIM_TimeBaseCfgTypeDef;
00187
00188 /**
00189   * @brief  Simple output compare mode configuration definition
00190   */
00191 typedef struct
00192 {
00193   uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).
00194                             This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
00195   uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
00196                             The compare value must be above or equal to 3 periods of the fHRTIM clock */
00197   uint32_t Polarity;   /*!< Specifies the output polarity.
00198                             This parameter can be any value of @ref HRTIM_Output_Polarity */
00199   uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.
00200                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00201 } HRTIM_SimpleOCChannelCfgTypeDef;
00202
00203 /**
00204   * @brief  Simple PWM output mode configuration definition
00205   */
00206 typedef struct
00207 {
00208   uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
00209                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
00210   uint32_t Polarity;        /*!< Specifies the output polarity.
00211                                  This parameter can be any value of @ref HRTIM_Output_Polarity */
00212   uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.
00213                                  This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00214 } HRTIM_SimplePWMChannelCfgTypeDef;
00215
00216 /**
00217   * @brief  Simple capture mode configuration definition
00218   */
00219 typedef struct
00220 {
00221   uint32_t Event;             /*!< Specifies the external event triggering the capture.
00222                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00223   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00224                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00225   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00226                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00227   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00228                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00229 } HRTIM_SimpleCaptureChannelCfgTypeDef;
00230
00231 /**
00232   * @brief  Simple One Pulse mode configuration definition
00233   */
00234 typedef struct
00235 {
00236   uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
00237                                    The compare value must be above or equal to 3 periods of the fHRTIM clock */
00238   uint32_t OutputPolarity;    /*!< Specifies the output polarity.
00239                                    This parameter can be any value of @ref HRTIM_Output_Polarity */
00240   uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.
00241                                    This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00242   uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.
00243                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00244   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00245                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00246   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00247                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
00248   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00249                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00250 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
00251
00252 /**
00253   * @brief  Timer configuration definition
00254   */
00255 typedef struct
00256 {
00257   uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.
00258                                        Specifies which interrupts requests must enabled for the timer.
00259                                        This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
00260                                        or @ref HRTIM_Timing_Unit_Interrupt_Enable */
00261   uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.
00262                                        Specifies which DMA requests must be enabled for the timer.
00263                                        This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
00264                                        or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
00265   uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.
00266                                        Specifies the address of the source address of the DMA transfer */
00267   uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.
00268                                        Specifies the address of the destination address of the DMA transfer */
00269   uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.
00270                                        Specifies the size of the DMA transfer */
00271   uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.
00272                                         Specifies whether or not half mode is enabled
00273                                         This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
00274   uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00275                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00276                                         This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
00277   uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00278                                         Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00279                                         This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
00280   uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.
00281                                         Indicates whether or not the a DAC synchronization event is generated.
00282                                         This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
00283   uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.
00284                                         Specifies whether or not register preload is enabled.
00285                                         This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
00286   uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.
00287                                         Specifies how the update occurs with respect to a burst DMA transaction or
00288                                         update enable inputs (Slave timers only).
00289                                         This parameter can be any value of @ref HRTIM_Update_Gating   */
00290   uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.
00291                                         Specifies how the timer behaves during a burst mode operation.
00292                                         This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
00293   uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.
00294                                         Specifies whether or not registers update is triggered by the repetition event.
00295                                         This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
00296   uint32_t PushPull;               /*!< Relevant for Timer A to Timer E.
00297                                         Specifies whether or not the push-pull mode is enabled.
00298                                         This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
00299   uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer E.
00300                                         Specifies which fault channels are enabled for the timer.
00301                                         This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
00302   uint32_t FaultLock;              /*!< Relevant for Timer A to Timer E.
00303                                         Specifies whether or not fault enabling status is write protected.
00304                                         This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
00305   uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer E.
00306                                         Specifies whether or not dead-time insertion is enabled for the timer.
00307                                         This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
00308   uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer E.
00309                                         Specifies the delayed protection mode.
00310                                         This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
00311   uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer E.
00312                                         Specifies source(s) triggering the timer registers update.
00313                                         This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
00314   uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer E.
00315                                         Specifies source(s) triggering the timer counter reset.
00316                                         This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
00317   uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer E.
00318                                         Specifies whether or not registers update is triggered when the timer counter is reset.
00319                                         This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
00320 } HRTIM_TimerCfgTypeDef;
00321
00322 /**
00323   * @brief  Compare unit configuration definition
00324   */
00325 typedef struct
00326 {
00327   uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.
00328                                       The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
00329                                       The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
00330   uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.
00331                                       This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
00332   uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
00333                                       CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */
00334 } HRTIM_CompareCfgTypeDef;
00335
00336 /**
00337   * @brief  Capture unit configuration definition
00338   */
00339 typedef struct
00340 {
00341   uint32_t Trigger;          /*!< Specifies source(s) triggering the capture.
00342                                   This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
00343 } HRTIM_CaptureCfgTypeDef;
00344
00345 /**
00346   * @brief  Output configuration definition
00347   */
00348 typedef struct
00349 {
00350   uint32_t Polarity;                    /*!< Specifies the output polarity.
00351                                              This parameter can be any value of @ref HRTIM_Output_Polarity */
00352   uint32_t SetSource;                   /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
00353                                              This parameter can be a combination of @ref HRTIM_Output_Set_Source */
00354   uint32_t ResetSource;                 /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
00355                                              This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
00356   uint32_t IdleMode;                    /*!< Specifies whether or not the output is affected by a burst mode operation.
00357                                              This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
00358   uint32_t IdleLevel;                   /*!< Specifies whether the output level is active or inactive when in IDLE state.
00359                                              This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00360   uint32_t FaultLevel;                  /*!< Specifies whether the output level is active or inactive when in FAULT state.
00361                                              This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
00362   uint32_t ChopperModeEnable;           /*!< Indicates whether or not the chopper mode is enabled
00363                                              This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
00364   uint32_t BurstModeEntryDelayed;       /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
00365                                              This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
00366 } HRTIM_OutputCfgTypeDef;
00367
00368 /**
00369   * @brief  External event filtering in timing units configuration definition
00370   */
00371 typedef struct
00372 {
00373   uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.
00374                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
00375   uint32_t Latch;       /*!< Specifies whether or not the signal is latched.
00376                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
00377 } HRTIM_TimerEventFilteringCfgTypeDef;
00378
00379 /**
00380   * @brief  Dead time feature configuration definition
00381   */
00382 typedef struct
00383 {
00384   uint32_t Prescaler;        /*!< Specifies the dead-time prescaler.
00385                                   This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
00386   uint32_t RisingValue;      /*!< Specifies the dead-time following a rising edge.
00387                                   This parameter can be a number between 0x0 and 0x1FFU */
00388   uint32_t RisingSign;       /*!< Specifies whether the dead-time is positive or negative on rising edge.
00389                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
00390   uint32_t RisingLock;       /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
00391                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
00392   uint32_t RisingSignLock;   /*!< Specifies whether or not dead-time rising sign is write protected.
00393                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
00394   uint32_t FallingValue;     /*!< Specifies the dead-time following a falling edge.
00395                                   This parameter can be a number between 0x0 and 0x1FFU */
00396   uint32_t FallingSign;      /*!< Specifies whether the dead-time is positive or negative on falling edge.
00397                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
00398   uint32_t FallingLock;      /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
00399                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
00400   uint32_t FallingSignLock;  /*!< Specifies whether or not dead-time falling sign is write protected.
00401                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
00402 } HRTIM_DeadTimeCfgTypeDef;
00403
00404 /**
00405   * @brief  Chopper mode configuration definition
00406   */
00407 typedef struct
00408 {
00409   uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
00410                               This parameter can be a value of @ref HRTIM_Chopper_Frequency */
00411   uint32_t DutyCycle;    /*!< Specifies the Timer chopper duty cycle value.
00412                               This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
00413   uint32_t StartPulse;   /*!< Specifies the Timer pulse width value.
00414                               This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
00415 } HRTIM_ChopperModeCfgTypeDef;
00416
00417 /**
00418   * @brief  External event channel configuration definition
00419   */
00420 typedef struct
00421 {
00422   uint32_t Source;        /*!< Identifies the source of the external event.
00423                                This parameter can be a value of @ref HRTIM_External_Event_Sources */
00424   uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).
00425                                This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00426   uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.
00427                                This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00428   uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00429                                This parameter can be a value of @ref HRTIM_External_Event_Filter */
00430   uint32_t FastMode;      /*!< Indicates whether or not low latency mode is enabled for the external event.
00431                                This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
00432 } HRTIM_EventCfgTypeDef;
00433
00434 /**
00435   * @brief  Fault channel configuration definition
00436   */
00437 typedef struct
00438 {
00439   uint32_t Source;        /*!< Identifies the source of the fault.
00440                                This parameter can be a value of @ref HRTIM_Fault_Sources */
00441   uint32_t Polarity;      /*!< Specifies the polarity of the fault event.
00442                                This parameter can be a value of @ref HRTIM_Fault_Polarity */
00443   uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
00444                                This parameter can be a value of @ref HRTIM_Fault_Filter */
00445   uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.
00446                                This parameter can be a value of @ref HRTIM_Fault_Lock */
00447 } HRTIM_FaultCfgTypeDef;
00448
00449 /**
00450   * @brief  Burst mode configuration definition
00451   */
00452 typedef struct
00453 {
00454   uint32_t Mode;           /*!< Specifies the burst mode operating mode.
00455                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
00456   uint32_t ClockSource;    /*!< Specifies the burst mode clock source.
00457                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
00458   uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.
00459                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
00460   uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
00461                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
00462   uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.
00463                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
00464   uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.
00465                                 This parameter can be a number between 0x0 and 0xFFFF  */
00466   uint32_t Period;         /*!< Specifies burst mode repetition period.
00467                                 This parameter can be a number between 0x1 and 0xFFFF  */
00468 } HRTIM_BurstModeCfgTypeDef;
00469
00470 /**
00471   * @brief  ADC trigger configuration definition
00472   */
00473 typedef struct
00474 {
00475   uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.
00476                                This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source  */
00477   uint32_t Trigger;       /*!< Specifies the event(s) triggering the ADC conversion.
00478                                This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event  */
00479 } HRTIM_ADCTriggerCfgTypeDef;
00480
00481 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00482 /**
00483   * @brief  HAL HRTIM Callback ID enumeration definition
00484   */
00485 typedef enum {
00486   HAL_HRTIM_FAULT1CALLBACK_CB_ID               = 0x00U, /*!< Fault 1 interrupt callback ID                         */
00487   HAL_HRTIM_FAULT2CALLBACK_CB_ID               = 0x01U, /*!< Fault 2 interrupt callback ID                         */
00488   HAL_HRTIM_FAULT3CALLBACK_CB_ID               = 0x02U, /*!< Fault 3 interrupt callback ID                         */
00489   HAL_HRTIM_FAULT4CALLBACK_CB_ID               = 0x03U, /*!< Fault 4 interrupt callback ID                         */
00490   HAL_HRTIM_FAULT5CALLBACK_CB_ID               = 0x04U, /*!< Fault 5 interrupt callback ID                         */
00491   HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID          = 0x05U, /*!< System fault interrupt callback ID                    */
00492   HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID      = 0x07U, /*!< Burst mode period interrupt callback ID               */
00493   HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID                      */
00494   HAL_HRTIM_ERRORCALLBACK_CB_ID                = 0x09U, /*!< DMA error callback ID                                 */
00495
00496   HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID      = 0x10U, /*!< Timer x Update interrupt callback ID                  */
00497   HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID      = 0x11U, /*!< Timer x Repetition interrupt callback ID              */
00498   HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID        = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID         */
00499   HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID        = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID         */
00500   HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID        = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID         */
00501   HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID        = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID         */
00502   HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID        = 0x16U, /*!< Timer x Capture 1 interrupts callback ID              */
00503   HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID        = 0x17U, /*!< Timer x Capture 2 interrupts callback ID              */
00504   HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID    = 0x18U, /*!< Timer x Delayed protection interrupt callback ID      */
00505   HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID         = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */
00506   HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID           = 0x1AU, /*!< Timer x output 1 set interrupt callback ID            */
00507   HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID         = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID          */
00508   HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID           = 0x1CU, /*!< Timer x output 2 set interrupt callback ID            */
00509   HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID         = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID          */
00510   HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID     = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID     */
00511
00512   HAL_HRTIM_MSPINIT_CB_ID                      = 0x20U, /*!< HRTIM MspInit callback ID                             */
00513   HAL_HRTIM_MSPDEINIT_CB_ID                    = 0x21U, /*!< HRTIM MspInit callback ID                             */
00514 }HAL_HRTIM_CallbackIDTypeDef;
00515
00516 /**
00517   * @brief  HAL HRTIM Callback function pointer definitions
00518   */
00519 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim);       /*!< HRTIM related callback function pointer         */
00520
00521 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!< HRTIM Timer x related callback function pointer */
00522                                             uint32_t TimerIdx);
00523 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /* Exported constants --------------------------------------------------------*/
00530 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
00531   * @{
00532   */
00533
00534 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
00535   * @{
00536   * @brief Constants defining the timer indexes
00537   */
00538 #define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */
00539 #define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */
00540 #define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */
00541 #define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */
00542 #define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */
00543 #define HRTIM_TIMERINDEX_MASTER  0x5U   /*!< Index used to access master registers  */
00544 #define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
00550   * @{
00551   * @brief Constants defining timer identifiers
00552   */
00553 #define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier  */
00554 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
00555 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
00556 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
00557 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
00558 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
00559 /**
00560  * @}
00561  */
00562
00563 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
00564   * @{
00565   * @brief Constants defining compare unit identifiers
00566   */
00567 #define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */
00568 #define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */
00569 #define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */
00570 #define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */
00571  /**
00572   * @}
00573   */
00574
00575 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
00576   * @{
00577   * @brief Constants defining capture unit identifiers
00578   */
00579 #define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */
00580 #define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
00586   * @{
00587   * @brief Constants defining timer output identifiers
00588   */
00589 #define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */
00590 #define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */
00591 #define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */
00592 #define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */
00593 #define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */
00594 #define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */
00595 #define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */
00596 #define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */
00597 #define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */
00598 #define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
00604   * @{
00605   * @brief Constants defining ADC triggers identifiers
00606   */
00607 #define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */
00608 #define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */
00609 #define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */
00610 #define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */
00611
00612 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
00613     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
00614      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
00615      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
00616      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
00617 /**
00618   * @}
00619   */
00620 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
00621   * @{
00622   * @brief Constants defining external event channel identifiers
00623   */
00624 #define HRTIM_EVENT_NONE    (0x00000000U)     /*!< Undefined event channel */
00625 #define HRTIM_EVENT_1       (0x00000001U)     /*!< External event channel 1  identifier */
00626 #define HRTIM_EVENT_2       (0x00000002U)     /*!< External event channel 2  identifier */
00627 #define HRTIM_EVENT_3       (0x00000003U)     /*!< External event channel 3  identifier */
00628 #define HRTIM_EVENT_4       (0x00000004U)     /*!< External event channel 4  identifier */
00629 #define HRTIM_EVENT_5       (0x00000005U)     /*!< External event channel 5  identifier */
00630 #define HRTIM_EVENT_6       (0x00000006U)     /*!< External event channel 6  identifier */
00631 #define HRTIM_EVENT_7       (0x00000007U)     /*!< External event channel 7  identifier */
00632 #define HRTIM_EVENT_8       (0x00000008U)     /*!< External event channel 8  identifier */
00633 #define HRTIM_EVENT_9       (0x00000009U)     /*!< External event channel 9  identifier */
00634 #define HRTIM_EVENT_10      (0x0000000AU)     /*!< External event channel 10 identifier */
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
00640   * @{
00641   * @brief Constants defining fault channel identifiers
00642   */
00643 #define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */
00644 #define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */
00645 #define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */
00646 #define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */
00647 #define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */
00648 /**
00649   * @}
00650   */
00651
00652
00653  /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
00654   * @{
00655   * @brief Constants defining timer high-resolution clock prescaler ratio.
00656   */
00657 #define HRTIM_PRESCALERRATIO_MUL32    (0x00000000U)  /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
00658 #define HRTIM_PRESCALERRATIO_MUL16    (0x00000001U)  /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
00659 #define HRTIM_PRESCALERRATIO_MUL8     (0x00000002U)  /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)  */
00660 #define HRTIM_PRESCALERRATIO_MUL4     (0x00000003U)  /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)    */
00661 #define HRTIM_PRESCALERRATIO_MUL2     (0x00000004U)  /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)    */
00662 #define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)         */
00663 #define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)     */
00664 #define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)        */
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
00670   * @{
00671   * @brief Constants defining timer counter operating mode.
00672   */
00673 #define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00674 #define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */
00675 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
00681   * @{
00682   * @brief Constants defining half mode enabling status.
00683   */
00684 #define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */
00685 #define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */
00686 /**
00687   * @}
00688   */
00689
00690 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
00691   * @{
00692   * @brief Constants defining the timer behavior following the synchronization event
00693   */
00694 #define HRTIM_SYNCSTART_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
00695 #define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */
00696 /**
00697   * @}
00698   */
00699
00700 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
00701   * @{
00702   * @brief Constants defining the timer behavior following the synchronization event
00703   */
00704 #define HRTIM_SYNCRESET_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
00705 #define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */
00706 /**
00707   * @}
00708   */
00709
00710 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
00711   * @{
00712   * @brief Constants defining on which output the DAC synchronization event is sent
00713   */
00714 #define HRTIM_DACSYNC_NONE          0x00000000U                                 /*!< No DAC synchronization event generated */
00715 #define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00716 #define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00717 #define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
00723   * @{
00724   * @brief Constants defining whether a write access into a preloadable
00725   *        register is done into the active or the preload register.
00726   */
00727 #define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */
00728 #define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
00734   * @{
00735   * @brief Constants defining how the update occurs relatively to the burst DMA
00736   *        transaction and the external update request on update enable inputs 1 to 3.
00737   */
00738 #define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                           /*!< Update done independently from the DMA burst transfer completion */
00739 #define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00740 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00741 #define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
00742 #define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
00743 #define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
00744 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */
00745 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */
00746 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
00752   * @{
00753   * @brief Constants defining how the timer behaves during a burst
00754             mode operation.
00755   */
00756 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U           /*!< Timer counter clock is maintained and the timer operates normally */
00757 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset */
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
00763   * @{
00764   * @brief Constants defining whether registers are updated when the timer
00765   *        repetition period is completed (either due to roll-over or
00766   *        reset events)
00767   */
00768 #define HRTIM_UPDATEONREPETITION_DISABLED  0x00000000U           /*!< Update on repetition disabled */
00769 #define HRTIM_UPDATEONREPETITION_ENABLED   (HRTIM_MCR_MREPU)     /*!< Update on repetition enabled */
00770 /**
00771   * @}
00772   */
00773
00774
00775 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
00776   * @{
00777   * @brief Constants defining whether or not the push-pull mode is enabled for
00778   *        a timer.
00779   */
00780 #define HRTIM_TIMPUSHPULLMODE_DISABLED     0x00000000U           /*!< Push-Pull mode disabled */
00781 #define HRTIM_TIMPUSHPULLMODE_ENABLED      (HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */
00782 /**
00783   * @}
00784   */
00785
00786 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
00787   * @{
00788   * @brief Constants defining whether a fault channel is enabled for a timer
00789   */
00790 #define HRTIM_TIMFAULTENABLE_NONE     0x00000000U           /*!< No fault enabled */
00791 #define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */
00792 #define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */
00793 #define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */
00794 #define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */
00795 #define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
00801   * @{
00802   * @brief Constants defining whether or not fault enabling bits are write
00803   *        protected for a timer
00804   */
00805 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */
00806 #define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
00812   * @{
00813   * @brief Constants defining whether or not fault the dead time insertion
00814   *        feature is enabled for a timer
00815   */
00816 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */
00817 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Dead-time is inserted between output 1 and output 2U */
00818 /**
00819   * @}
00820   */
00821
00822 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
00823   * @{
00824   * @brief Constants defining all possible delayed protection modes
00825   *        for a timer. Also define the source and outputs on which the delayed
00826   *        protection schemes are applied
00827   */
00828 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */
00829 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
00830 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
00831 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
00832 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */
00833 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
00834 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
00835 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
00836 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
00837
00838 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED            (0x00000000U)                                                                             /*!< No action */
00839 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8    (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
00840 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8    (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
00841 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8    (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
00842 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8       (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */
00843 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
00844 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
00845 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9    (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
00846 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9       (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */
00847 /**
00848   * @}
00849   */
00850
00851 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
00852   * @{
00853   * @brief Constants defining whether the registers update is done synchronously
00854   *        with any other timer or master update
00855   */
00856 #define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */
00857 #define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */
00858 #define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */
00859 #define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */
00860 #define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/
00861 #define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */
00862 #define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */
00863 /**
00864   * @}
00865   */
00866
00867 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
00868   * @{
00869   * @brief Constants defining the events that can be selected to trigger the reset
00870   *        of the timer counter
00871   */
00872 #define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */
00873 #define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */
00874 #define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */
00875 #define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */
00876 #define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */
00877 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */
00878 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */
00879 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */
00880 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */
00881 #define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */
00882 #define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */
00883 #define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */
00884 #define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */
00885 #define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */
00886 #define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */
00887 #define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */
00888 #define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */
00889 #define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */
00890 #define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
00891 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00892 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00893 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00894 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00895 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00896 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00897 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00898 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00899 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00900 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
00901 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
00902 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
00903 /**
00904   * @}
00905   */
00906
00907 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
00908   * @{
00909   * @brief Constants defining whether the register are updated upon Timerx
00910   *        counter reset or roll-over to 0 after reaching the period value
00911   *        in continuous mode
00912   */
00913 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U           /*!< Update by timer x reset / roll-over disabled */
00914 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */
00915 /**
00916   * @}
00917   */
00918
00919 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
00920   * @{
00921   * @brief Constants defining whether the compare register is behaving in
00922   *        regular mode (compare match issued as soon as counter equal compare),
00923   *        or in auto-delayed mode
00924   */
00925 #define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */
00926 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
00927 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
00928 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
00934   * @{
00935   * @brief Constants defining the behavior of the output signal when the timer
00936            operates in basic output compare mode
00937   */
00938 #define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */
00939 #define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */
00940 #define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */
00941
00942 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
00943               (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
00944                ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
00945                ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
00951   * @{
00952   * @brief Constants defining the polarity of a timer output
00953   */
00954 #define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is acitve HIGH */
00955 #define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
00961   * @{
00962   * @brief Constants defining the events that can be selected to configure the
00963   *        set crossbar of a timer output
00964   */
00965 #define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */
00966 #define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
00967 #define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */
00968 #define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */
00969 #define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */
00970 #define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */
00971 #define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */
00972 #define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */
00973 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */
00974 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */
00975 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */
00976 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */
00977 #define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
00978 #define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
00979 #define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
00980 #define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
00981 #define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
00982 #define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
00983 #define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
00984 #define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
00985 #define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
00986 #define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */
00987 #define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */
00988 #define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */
00989 #define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */
00990 #define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */
00991 #define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */
00992 #define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */
00993 #define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */
00994 #define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */
00995 #define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */
00996 #define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */
00997 /**
00998   * @}
00999   */
01000
01001 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
01002   * @{
01003   * @brief Constants defining the events that can be selected to configure the
01004   *        set crossbar of a timer output
01005   */
01006 #define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
01007 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
01008 #define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */
01009 #define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */
01010 #define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */
01011 #define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */
01012 #define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */
01013 #define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */
01014 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */
01015 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
01016 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
01017 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
01018 #define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
01019 #define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
01020 #define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
01021 #define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
01022 #define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
01023 #define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
01024 #define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
01025 #define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
01026 #define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
01027 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
01028 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
01029 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
01030 #define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */
01031 #define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */
01032 #define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */
01033 #define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */
01034 #define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */
01035 #define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */
01036 #define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */
01037 #define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */
01038 /**
01039   * @}
01040   */
01041
01042 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
01043   * @{
01044   * @brief Constants defining whether or not the timer output transition to its
01045            IDLE state when burst mode is entered
01046   */
01047 #define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U           /*!< The output is not affected by the burst mode operation */
01048 #define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */
01049  /**
01050   * @}
01051   */
01052
01053 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
01054   * @{
01055   * @brief Constants defining the output level when output is in IDLE state
01056   */
01057 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
01058 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
01059 /**
01060   * @}
01061   */
01062
01063 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
01064   * @{
01065   * @brief Constants defining the output level when output is in FAULT state
01066   */
01067 #define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                  /*!< The output is not affected by the fault input */
01068 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
01069 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
01070 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
01071 /**
01072   * @}
01073   */
01074
01075 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
01076   * @{
01077   * @brief Constants defining whether or not chopper mode is enabled for a timer
01078            output
01079   */
01080 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U           /*!< Output signal is not altered  */
01081 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
01087   * @{
01088   * @brief Constants defining the idle mode entry is delayed by forcing a
01089            dead-time insertion before switching the outputs to their idle state
01090   */
01091 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U           /*!< The programmed Idle state is applied immediately to the Output */
01092 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Dead-time is inserted on output before entering the idle mode */
01093 /**
01094   * @}
01095   */
01096
01097
01098 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
01099   * @{
01100   * @brief Constants defining the events that can be selected to trigger the
01101   *        capture of the timing unit counter
01102   */
01103 #define HRTIM_CAPTURETRIGGER_NONE         0x00000000U              /*!< Capture trigger is disabled */
01104 #define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */
01105 #define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */
01106 #define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */
01107 #define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */
01108 #define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */
01109 #define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */
01110 #define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */
01111 #define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */
01112 #define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */
01113 #define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */
01114 #define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
01115 #define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */
01116 #define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */
01117 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */
01118 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */
01119 #define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */
01120 #define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */
01121 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */
01122 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */
01123 #define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */
01124 #define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */
01125 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */
01126 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */
01127 #define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */
01128 #define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */
01129 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */
01130 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */
01131 #define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */
01132 #define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */
01133 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */
01134 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */
01135 /**
01136   * @}
01137   */
01138
01139 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
01140   * @{
01141   * @brief Constants defining the event filtering applied to external events
01142   *        by a timer
01143   */
01144 #define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
01145 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1U */
01146 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2U */
01147 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3U */
01148 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4U */
01149 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */
01150 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */
01151 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */
01152 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */
01153 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */
01154 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */
01155 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */
01156 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */
01157 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2U */
01158 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3U */
01159 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */
01160 /**
01161   * @}
01162   */
01163
01164 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
01165   * @{
01166   * @brief Constants defining whether or not the external event is
01167   *        memorized (latched) and generated as soon as the blanking period
01168   *        is completed or the window ends
01169   */
01170 #define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */
01171 #define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
01172 /**
01173   * @}
01174   */
01175
01176 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
01177   * @{
01178   * @brief Constants defining division ratio between the timer clock frequency
01179   *        (fHRTIM) and the dead-time generator clock (fDTG)
01180   */
01181 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */
01182 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */
01183 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */
01184 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
01185 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
01186 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
01187 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */
01188 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */
01189 /**
01190   * @}
01191   */
01192
01193 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
01194   * @{
01195   * @brief Constants defining whether the dead-time is positive or negative
01196   *        (overlapping signal) on rising edge
01197   */
01198 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on rising edge */
01199 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative dead-time on rising edge */
01200 /**
01201   * @}
01202   */
01203
01204 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
01205   * @{
01206   * @brief Constants defining whether or not the dead-time (rising sign and
01207   *        value) is write protected
01208   */
01209 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising value and sign is writeable */
01210 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Dead-time rising value and sign is read-only */
01211 /**
01212   * @}
01213   */
01214
01215 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
01216   * @{
01217   * @brief Constants defining whether or not the dead-time rising sign is write
01218   *        protected
01219   */
01220 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising sign is writeable */
01221 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Dead-time rising sign is read-only */
01222 /**
01223   * @}
01224   */
01225
01226 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
01227   * @{
01228   * @brief Constants defining whether the dead-time is positive or negative
01229   *        (overlapping signal) on falling edge
01230   */
01231 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on falling edge */
01232 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative dead-time on falling edge */
01233 /**
01234   * @}
01235   */
01236
01237 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
01238   * @{
01239   * @brief Constants defining whether or not the dead-time (falling sign and
01240   *        value) is write protected
01241   */
01242 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling value and sign is writeable */
01243 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Dead-time falling value and sign is read-only */
01244 /**
01245   * @}
01246   */
01247
01248 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
01249   * @{
01250   * @brief Constants defining whether or not the dead-time falling sign is write
01251   *        protected
01252   */
01253 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling sign is writeable */
01254 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Dead-time falling sign is read-only */
01255 /**
01256   * @}
01257   */
01258
01259 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
01260   * @{
01261   * @brief Constants defining the frequency of the generated high frequency carrier
01262   */
01263 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
01264 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
01265 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
01266 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
01267 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
01268 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
01269 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
01270 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
01271 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
01272 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
01273 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
01274 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
01275 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
01276 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
01277 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
01278 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
01279  /**
01280   * @}
01281   */
01282
01283 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
01284   * @{
01285   * @brief Constants defining the duty cycle of the generated high frequency carrier
01286   *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
01287   */
01288 #define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                                       /*!< Only 1st pulse is present */
01289 #define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */
01290 #define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */
01291 #define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */
01292 #define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */
01293 #define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */
01294 #define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */
01295 #define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
01296 /**
01297   * @}
01298   */
01299
01300 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
01301   * @{
01302   * @brief Constants defining the pulse width of the first pulse of the generated
01303   *        high frequency carrier
01304   */
01305 #define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                          /*!< tSTPW = tHRTIM x 16  */
01306 #define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
01307 #define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
01308 #define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
01309 #define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
01310 #define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
01311 #define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
01312 #define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
01313 #define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
01314 #define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
01315 #define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
01316 #define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
01317 #define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
01318 #define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
01319 #define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
01320 #define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
01321 /**
01322   * @}
01323   */
01324
01325 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
01326   * @{
01327   * @brief Constants defining the options for synchronizing multiple HRTIM
01328   *        instances, as a master unit (generating a synchronization signal)
01329   *        or as a slave (waiting for a trigger to be synchronized)
01330   */
01331 #define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
01332 #define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
01333 #define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
01334 /**
01335   * @}
01336   */
01337
01338 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
01339   * @{
01340   * @brief Constants defining defining the synchronization input source
01341   */
01342 #define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                                  /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
01343 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */
01344 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
01345 /**
01346   * @}
01347   */
01348
01349 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
01350   * @{
01351   * @brief Constants defining the source and event to be sent on the
01352   *        synchronization outputs
01353   */
01354 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
01355 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
01356 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
01357 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
01358 /**
01359   * @}
01360   */
01361
01362 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
01363   * @{
01364   * @brief Constants defining the routing and conditioning of the synchronization output event
01365   */
01366 #define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                   /*!< Synchronization output event is disabled */
01367 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
01368 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
01369 /**
01370   * @}
01371   */
01372
01373 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
01374   * @{
01375   * @brief Constants defining available sources associated to external events
01376   */
01377 #define HRTIM_EVENTSRC_1         (0x00000000U)                                  /*!< External event source 1U */
01378 #define HRTIM_EVENTSRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2U */
01379 #define HRTIM_EVENTSRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3U */
01380 #define HRTIM_EVENTSRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4U */
01381 /**
01382   * @}
01383   */
01384
01385 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
01386   * @{
01387   * @brief Constants defining the polarity of an external event
01388   */
01389 #define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */
01390 #define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01391 /**
01392   * @}
01393   */
01394
01395 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
01396   * @{
01397   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
01398   *        of an external event
01399   */
01400 #define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */
01401 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01402 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01403 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01404 /**
01405   * @}
01406   */
01407
01408 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
01409   * @{
01410   * @brief Constants defining whether or not an external event is programmed in
01411            fast mode
01412   */
01413 #define HRTIM_EVENTFASTMODE_DISABLE    (0x00000000U)               /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01414 #define HRTIM_EVENTFASTMODE_ENABLE     (HRTIM_EECR1_EE1FAST)       /*!< External Event is acting asynchronously on outputs (low latency mode) */
01415 /**
01416   * @}
01417   */
01418
01419 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
01420   * @{
01421   * @brief Constants defining the frequency used to sample an external event 6
01422   *        input and the length (N) of the digital filter applied
01423   */
01424 #define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */
01425 #define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */
01426 #define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */
01427 #define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */
01428 #define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */
01429 #define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */
01430 #define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */
01431 #define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */
01432 #define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */
01433 #define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */
01434 #define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */
01435 #define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */
01436 #define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */
01437 #define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */
01438 #define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */
01439 #define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */
01440 /**
01441   * @}
01442   */
01443
01444 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
01445   * @{
01446   * @brief Constants defining division ratio between the timer clock frequency
01447   *        fHRTIM) and the external event signal sampling clock (fEEVS)
01448   *        used by the digital filters
01449   */
01450 #define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */
01451 #define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */
01452 #define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */
01453 #define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */
01454 /**
01455   * @}
01456   */
01457
01458 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
01459   * @{
01460   * @brief Constants defining whether a fault is triggered by any external
01461   *        or internal fault source
01462   */
01463 #define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)              /*!< Fault input is FLT input pin */
01464 #define HRTIM_FAULTSOURCE_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01465 /**
01466   * @}
01467   */
01468
01469 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
01470   * @{
01471   * @brief Constants defining the polarity of a fault event
01472   */
01473 #define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)            /*!< Fault input is active low */
01474 #define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
01475 /**
01476   * @}
01477   */
01478
01479 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
01480   * @{
01481   * @ brief Constants defining the frequency used to sample the fault input and
01482   *         the length (N) of the digital filter applied
01483   */
01484 #define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */
01485 #define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */
01486 #define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */
01487 #define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */
01488 #define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */
01489 #define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */
01490 #define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */
01491 #define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */
01492 #define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */
01493 #define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */
01494 #define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */
01495 #define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */
01496 #define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */
01497 #define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */
01498 #define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */
01499 #define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */
01500 /**
01501   * @}
01502   */
01503
01504 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
01505   * @{
01506   * @brief Constants defining whether or not the fault programming bits are
01507            write protected
01508   */
01509 #define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)               /*!< Fault settings bits are read/write */
01510 #define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */
01511 /**
01512   * @}
01513   */
01514
01515 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
01516   * @{
01517   * @brief Constants defining the division ratio between the timer clock
01518   *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
01519   *        by the digital filters.
01520   */
01521 #define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */
01522 #define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */
01523 #define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */
01524 #define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */
01525 /**
01526   * @}
01527   */
01528
01529 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
01530   * @{
01531   * @brief Constants defining if the burst mode is entered once or if it is
01532   *        continuously operating
01533   */
01534 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)           /*!< Burst mode operates in single shot mode */
01535 #define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
01541   * @{
01542   * @brief Constants defining the clock source for the burst mode counter
01543   */
01544 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
01545 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
01546 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
01547 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
01548 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
01549 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
01550 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
01551 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
01552 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
01553 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
01554 /**
01555   * @}
01556   */
01557
01558 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
01559   * @{
01560   * @brief Constants defining the prescaling ratio of the fHRTIM clock
01561   *        for the burst mode controller
01562   */
01563 #define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */
01564 #define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */
01565 #define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */
01566 #define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */
01567 #define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */
01568 #define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */
01569 #define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */
01570 #define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */
01571 #define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */
01572 #define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */
01573 #define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */
01574 #define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/
01575 #define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */
01576 #define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */
01577 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */
01578 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
01579 /**
01580   * @}
01581   */
01582
01583 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
01584   * @{
01585   * @brief Constants defining whether or not burst mode registers preload
01586            mechanism is enabled, i.e. a write access into a preloadable register
01587           (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
01588   */
01589 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */
01590 #define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */
01591 /**
01592   * @}
01593   */
01594
01595 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
01596   * @{
01597   * @brief Constants defining the events that can be used to trig the burst
01598   *        mode operation
01599   */
01600 #define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U             /*!<  No trigger */
01601 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */
01602 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */
01603 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */
01604 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */
01605 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */
01606 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */
01607 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */
01608 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */
01609 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */
01610 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */
01611 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */
01612 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */
01613 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */
01614 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */
01615 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */
01616 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */
01617 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */
01618 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2        (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2  */
01619 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */
01620 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */
01621 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1        (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1  */
01622 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */
01623 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET       (HRTIM_BMTRGR_TERST)    /*!< Timer E reset  */
01624 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */
01625 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */
01626 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */
01627 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */
01628 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */
01629 #define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */
01630 #define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/
01631 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
01632 /**
01633   * @}
01634   */
01635
01636 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
01637   * @{
01638   * @brief constants defining the source triggering the update of the
01639      HRTIM_ADCxR register (transfer from preload to active register).
01640   */
01641 #define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                   /*!< Master timer */
01642 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */
01643 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */
01644 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
01645 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */
01646 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
01647 /**
01648   * @}
01649   */
01650
01651 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
01652   * @{
01653   * @brief constants defining the events triggering ADC conversion.
01654   *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
01655   *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
01656   */
01657 #define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U              /*!< No ADC trigger event */
01658 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */
01659 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */
01660 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */
01661 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */
01662 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */
01663 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */
01664 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */
01665 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */
01666 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */
01667 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */
01668 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2    (HRTIM_ADC1R_AD1TAC2)    /*!< ADC Trigger on Timer A compare 2U */
01669 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */
01670 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */
01671 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */
01672 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */
01673 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2    (HRTIM_ADC1R_AD1TBC2)    /*!< ADC Trigger on Timer B compare 2U */
01674 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */
01675 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */
01676 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */
01677 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */
01678 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2    (HRTIM_ADC1R_AD1TCC2)    /*!< ADC Trigger on Timer C compare 2U */
01679 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */
01680 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */
01681 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */
01682 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2    (HRTIM_ADC1R_AD1TDC2)    /*!< ADC Trigger on Timer D compare 2U */
01683 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */
01684 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */
01685 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */
01686 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2    (HRTIM_ADC1R_AD1TEC2)    /*!< ADC Trigger on Timer E compare 2U */
01687 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */
01688 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */
01689 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */
01690
01691 #define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */
01692 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */
01693 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */
01694 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */
01695 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */
01696 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */
01697 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */
01698 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */
01699 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */
01700 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */
01701 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */
01702 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */
01703 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3    (HRTIM_ADC2R_AD2TAC3)    /*!< ADC Trigger on Timer A compare 3U */
01704 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */
01705 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */
01706 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */
01707 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3    (HRTIM_ADC2R_AD2TBC3)    /*!< ADC Trigger on Timer B compare 3U */
01708 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */
01709 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */
01710 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */
01711 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3    (HRTIM_ADC2R_AD2TCC3)    /*!< ADC Trigger on Timer C compare 3U */
01712 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */
01713 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */
01714 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */
01715 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */
01716 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3    (HRTIM_ADC2R_AD2TDC3)    /*!< ADC Trigger on Timer D compare 3U */
01717 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */
01718 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */
01719 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */
01720 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */
01721 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */
01722 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */
01723 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */
01724
01725 /**
01726   * @}
01727   */
01728
01729 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
01730   * @{
01731   * @brief Constants defining the registers that can be written during a burst
01732   *        DMA operation
01733   */
01734 #define HRTIM_BURSTDMA_NONE  0x00000000U               /*!< No register is updated by Burst DMA accesses */
01735 #define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
01736 #define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
01737 #define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
01738 #define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
01739 #define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */
01740 #define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */
01741 #define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
01742 #define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
01743 #define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
01744 #define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
01745 #define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */
01746 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
01747 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
01748 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
01749 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
01750 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
01751 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
01752 #define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
01753 #define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
01754 #define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
01755 #define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
01756 /**
01757   * @}
01758   */
01759
01760 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
01761   * @{
01762   * @brief Constants used to enable or disable the burst mode controller
01763   */
01764 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U          /*!< Burst mode disabled */
01765 #define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */
01766 /**
01767   * @}
01768   */
01769
01770 /** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
01771   * @{
01772   * @brief Constants used to enable or disable a fault channel
01773   */
01774 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
01775 #define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */
01776 /**
01777   * @}
01778   */
01779
01780 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
01781   * @{
01782   * @brief Constants used to force timer registers update
01783   */
01784 #define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */
01785 #define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */
01786 #define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */
01787 #define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */
01788 #define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */
01789 #define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */
01790 /**
01791   * @}
01792   */
01793
01794 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
01795   * @{
01796   * @brief Constants used to force timer counter reset
01797   */
01798 #define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Reset the master timer counter */
01799 #define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Reset the timer A counter */
01800 #define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Reset the timer B counter */
01801 #define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Reset the timer C counter */
01802 #define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Reset the timer D counter */
01803 #define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Reset the timer E counter */
01804 /**
01805   * @}
01806   */
01807
01808 /** @defgroup HRTIM_Output_Level HRTIM Output Level
01809   * @{
01810   * @brief Constants defining the level of a timer output
01811   */
01812 #define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Force the output to its active state */
01813 #define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Force the output to its inactive state */
01814
01815 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
01816     (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
01817      ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
01818 /**
01819   * @}
01820   */
01821
01822 /** @defgroup HRTIM_Output_State HRTIM Output State
01823   * @{
01824   * @brief Constants defining the state of a timer output
01825   */
01826 #define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or
01827                                                               inactive level as programmed in the crossbar unit */
01828 #define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
01829                                                               outputs are disabled by software or during a burst mode operation */
01830 #define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
01831                                                               FAULTx inputs */
01832 /**
01833   * @}
01834   */
01835
01836 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
01837   * @{
01838   * @brief Constants defining the operating state of the burst mode controller
01839   */
01840 #define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U          /*!< Normal operation */
01841 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */
01842 /**
01843   * @}
01844   */
01845
01846 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
01847   * @{
01848   * @brief Constants defining on which output the signal is currently applied
01849   *        in push-pull mode
01850   */
01851 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U            /*!< Signal applied on output 1 and output 2 forced inactive */
01852 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
01853 /**
01854   * @}
01855   */
01856
01857 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
01858   * @{
01859   * @brief Constants defining on which output the signal was applied, in
01860   *        push-pull mode balanced fault mode or delayed idle mode, when the
01861   *        protection was triggered
01862   */
01863 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U               /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
01864 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
01865 /**
01866   * @}
01867   */
01868
01869 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
01870   * @{
01871   */
01872 #define HRTIM_IT_NONE           0x00000000U           /*!< No interrupt enabled */
01873 #define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */
01874 #define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */
01875 #define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */
01876 #define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */
01877 #define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */
01878 #define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */
01879 #define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */
01880 /**
01881   * @}
01882   */
01883
01884 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
01885   * @{
01886   */
01887 #define HRTIM_MASTER_IT_NONE         0x00000000U           /*!< No interrupt enabled */
01888 #define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */
01889 #define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */
01890 #define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */
01891 #define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */
01892 #define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */
01893 #define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */
01894 #define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */
01895 /**
01896   * @}
01897   */
01898
01899 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
01900   * @{
01901   */
01902 #define HRTIM_TIM_IT_NONE       0x00000000U               /*!< No interrupt enabled */
01903 #define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */
01904 #define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */
01905 #define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */
01906 #define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */
01907 #define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */
01908 #define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */
01909 #define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */
01910 #define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */
01911 #define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */
01912 #define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */
01913 #define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */
01914 #define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */
01915 #define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */
01916 #define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */
01917 /**
01918   * @}
01919   */
01920
01921 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
01922   * @{
01923   */
01924 #define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */
01925 #define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */
01926 #define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */
01927 #define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */
01928 #define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */
01929 #define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */
01930 #define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */
01931 /**
01932   * @}
01933   */
01934
01935 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
01936   * @{
01937   */
01938 #define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */
01939 #define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */
01940 #define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */
01941 #define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4    /*!< Master compare 4 interrupt flag */
01942 #define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP     /*!< Master Repetition interrupt flag */
01943 #define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC     /*!< Synchronization input interrupt flag */
01944 #define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD     /*!< Master update interrupt flag */
01945 /**
01946   * @}
01947   */
01948
01949 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
01950   * @{
01951   */
01952 #define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */
01953 #define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */
01954 #define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */
01955 #define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */
01956 #define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */
01957 #define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */
01958 #define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */
01959 #define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */
01960 #define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */
01961 #define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */
01962 #define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */
01963 #define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */
01964 #define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */
01965 #define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */
01966 /**
01967   * @}
01968   */
01969
01970 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
01971   * @{
01972   */
01973 #define HRTIM_MASTER_DMA_NONE         0x00000000U            /*!< No DMA request enable */
01974 #define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */
01975 #define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */
01976 #define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */
01977 #define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */
01978 #define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */
01979 #define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */
01980 #define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */
01981 /**
01982   * @}
01983   */
01984
01985 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
01986   * @{
01987   */
01988 #define HRTIM_TIM_DMA_NONE       0x00000000U               /*!< No DMA request enable */
01989 #define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */
01990 #define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */
01991 #define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */
01992 #define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */
01993 #define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */
01994 #define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */
01995 #define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */
01996 #define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */
01997 #define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */
01998 #define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */
01999 #define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */
02000 #define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */
02001 #define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */
02002 #define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */
02003 /**
02004   * @}
02005   */
02006
02007 /**
02008   * @}
02009   */
02010
02011   /* Private macros --------------------------------------------------------*/
02012 /** @addtogroup HRTIM_Private_Macros
02013   * @{
02014   */
02015 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
02016     (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
02017      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02018      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02019      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02020      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02021      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
02022
02023 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
02024      (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02025       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02026       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02027       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02028       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
02029
02030 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
02031
02032 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
02033     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
02034      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
02035      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
02036      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
02037
02038 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
02039     (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
02040      ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
02041
02042 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
02043
02044 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
02045     ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
02046      (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
02047       ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
02048     ||                                           \
02049     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
02050      (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
02051       ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
02052     ||                                           \
02053     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
02054      (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
02055       ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
02056     ||                                           \
02057     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
02058      (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
02059       ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
02060     ||                                           \
02061     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
02062      (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
02063       ((OUTPUT) == HRTIM_OUTPUT_TE2))))
02064
02065 #define IS_HRTIM_EVENT(EVENT)\
02066       (((EVENT) == HRTIM_EVENT_NONE)|| \
02067        ((EVENT) == HRTIM_EVENT_1)   || \
02068        ((EVENT) == HRTIM_EVENT_2)   || \
02069        ((EVENT) == HRTIM_EVENT_3)   || \
02070        ((EVENT) == HRTIM_EVENT_4)   || \
02071        ((EVENT) == HRTIM_EVENT_5)   || \
02072        ((EVENT) == HRTIM_EVENT_6)   || \
02073        ((EVENT) == HRTIM_EVENT_7)   || \
02074        ((EVENT) == HRTIM_EVENT_8)   || \
02075        ((EVENT) == HRTIM_EVENT_9)   || \
02076        ((EVENT) == HRTIM_EVENT_10))
02077
02078 #define IS_HRTIM_FAULT(FAULT)\
02079       (((FAULT) == HRTIM_FAULT_1)   || \
02080        ((FAULT) == HRTIM_FAULT_2)   || \
02081        ((FAULT) == HRTIM_FAULT_3)   || \
02082        ((FAULT) == HRTIM_FAULT_4)   || \
02083        ((FAULT) == HRTIM_FAULT_5))
02084
02085 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
02086         (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
02087          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
02088          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
02089          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
02090          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
02091          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
02092          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
02093          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
02094
02095 #define IS_HRTIM_MODE(MODE)\
02096           (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
02097            ((MODE) == HRTIM_MODE_SINGLESHOT) || \
02098            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02099
02100 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
02101           (((MODE) == HRTIM_MODE_SINGLESHOT) || \
02102            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02103
02104
02105 #define IS_HRTIM_HALFMODE(HALFMODE)\
02106             (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
02107              ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
02108
02109 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
02110               (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
02111                ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
02112
02113 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
02114                 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
02115                  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
02116
02117 #define IS_HRTIM_DACSYNC(DACSYNC)\
02118                 (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
02119                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
02120                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
02121                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
02122
02123 #define IS_HRTIM_PRELOAD(PRELOAD)\
02124                 (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
02125                  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
02126
02127 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
02128                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02129                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02130                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
02131
02132 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
02133                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02134                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02135                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
02136                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
02137                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
02138                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
02139                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
02140                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
02141                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
02142
02143 #define IS_HRTIM_TIMERBURSTMODE(MODE)                               \
02144                 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
02145                  ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
02146 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \
02147                 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
02148                  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
02149
02150 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
02151                   (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
02152                    ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
02153 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
02154
02155 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
02156       (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
02157        ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
02158
02159 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
02160     ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \
02161         ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
02162           ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \
02163       ||                                                                     \
02164         (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \
02165          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
02166
02167 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
02168           ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
02169             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
02170             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
02171             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
02172             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
02173             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
02174             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
02175             ||                                                                           \
02176             (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
02177              (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
02178              ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
02179
02180 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
02181
02182 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U)
02183
02184
02185 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
02186               (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
02187                ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
02188
02189 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
02190               (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
02191                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
02192                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
02193                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
02194
02195 /* Auto delayed mode is only available for compare units 2 and 4U */
02196 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
02197     ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
02198      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02199       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02200       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02201       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
02202     ||                                                                         \
02203     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
02204      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02205       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02206       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02207       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
02208
02209 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
02210               (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
02211                ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
02212
02213 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
02214
02215 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
02216               (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)       || \
02217                ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)     || \
02218                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)     || \
02219                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)    || \
02220                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)    || \
02221                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)    || \
02222                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)    || \
02223                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)  || \
02224                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
02225                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
02226                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
02227                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
02228                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1)    || \
02229                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2)    || \
02230                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3)    || \
02231                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4)    || \
02232                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5)    || \
02233                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6)    || \
02234                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7)    || \
02235                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8)    || \
02236                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9)    || \
02237                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)      || \
02238                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)      || \
02239                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)      || \
02240                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)      || \
02241                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)      || \
02242                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)      || \
02243                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)      || \
02244                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)      || \
02245                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)      || \
02246                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)     || \
02247                ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
02248
02249 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
02250               (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)       || \
02251                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)     || \
02252                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)     || \
02253                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)    || \
02254                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)    || \
02255                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)    || \
02256                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)    || \
02257                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)  || \
02258                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
02259                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
02260                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
02261                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
02262                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1)    || \
02263                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2)    || \
02264                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3)    || \
02265                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4)    || \
02266                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5)    || \
02267                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6)    || \
02268                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7)    || \
02269                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8)    || \
02270                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9)    || \
02271                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)      || \
02272                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)      || \
02273                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)      || \
02274                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)      || \
02275                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)      || \
02276                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)      || \
02277                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)      || \
02278                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)      || \
02279                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)      || \
02280                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)     || \
02281                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
02282
02283 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
02284               (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
02285                ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
02286
02287 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
02288               (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
02289                ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
02290
02291 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
02292               (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
02293                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
02294                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
02295                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
02296
02297 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
02298               (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
02299                ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
02300
02301 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
02302               (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
02303                ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
02304
02305
02306 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
02307    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
02308    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
02309    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
02310    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
02311    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
02312    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
02313    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
02314    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
02315    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
02316    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
02317    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
02318    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
02319    ||                                                           \
02320    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
02321      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02322       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02323       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02324       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02325       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02326       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02327       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02328       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02329       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02330       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02331       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02332       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02333       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02334       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02335       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02336       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02337     ||                                                          \
02338    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
02339      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02340       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02341       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02342       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02343       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02344       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02345       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02346       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02347       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02348       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02349       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02350       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02351       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02352       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02353       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02354       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02355     ||                                                          \
02356    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
02357      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02358       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02359       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02360       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02361       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02362       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02363       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02364       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02365       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02366       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02367       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02368       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02369       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02370       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02371       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02372       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02373     ||                                                          \
02374    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
02375      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02376       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02377       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02378       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02379       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02380       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02381       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02382       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02383       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02384       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02385       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02386       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02387       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02388       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02389       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02390       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02391     ||                                                          \
02392    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
02393      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02394       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02395       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02396       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02397       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02398       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02399       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02400       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02401       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02402       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02403       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02404       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02405       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02406       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02407       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02408       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
02409
02410 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
02411                 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \
02412                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \
02413                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \
02414                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \
02415                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \
02416                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \
02417                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \
02418                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \
02419                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \
02420                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \
02421                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \
02422                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \
02423                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \
02424                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \
02425                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \
02426                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
02427
02428 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
02429               (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
02430                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
02431
02432 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
02433                 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
02434                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
02435                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
02436                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
02437                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
02438                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
02439                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
02440                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
02441
02442 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
02443                 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
02444                  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
02445
02446 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
02447                     (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
02448                      ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
02449
02450 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
02451                   (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
02452                    ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
02453
02454 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
02455                       (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
02456                        ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
02457
02458 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
02459                           (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
02460                            ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
02461
02462 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
02463                         (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
02464                          ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
02465
02466 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
02467                         (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
02468                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
02469                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
02470                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
02471                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
02472                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
02473                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
02474                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
02475                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
02476                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
02477                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
02478                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
02479                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
02480                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
02481                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
02482                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
02483
02484 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
02485                         (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
02486                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
02487                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
02488                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
02489                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
02490                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
02491                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
02492                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
02493
02494 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
02495                         (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
02496                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
02497                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
02498                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
02499                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
02500                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
02501                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
02502                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
02503                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
02504                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
02505                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
02506                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
02507                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
02508                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
02509                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
02510                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
02511
02512 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
02513               (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
02514                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
02515                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
02516
02517 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
02518               (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
02519                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
02520                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
02521                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
02522
02523 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
02524               (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
02525                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
02526                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
02527
02528 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
02529                 (((EVENTSRC) == HRTIM_EVENTSRC_1)   || \
02530                  ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \
02531                  ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \
02532                  ((EVENTSRC) == HRTIM_EVENTSRC_4))
02533
02534 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
02535     ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
02536        (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
02537         ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
02538       ||                                                            \
02539       (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
02540        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
02541        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
02542
02543 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
02544                     (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
02545                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
02546                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
02547                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
02548
02549 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
02550     (((((EVENT) == HRTIM_EVENT_1) ||                 \
02551        ((EVENT) == HRTIM_EVENT_2) ||                 \
02552        ((EVENT) == HRTIM_EVENT_3) ||                 \
02553        ((EVENT) == HRTIM_EVENT_4) ||                 \
02554        ((EVENT) == HRTIM_EVENT_5)) &&                \
02555       (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
02556        ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
02557     ||                                               \
02558     (((EVENT) == HRTIM_EVENT_6) ||                   \
02559      ((EVENT) == HRTIM_EVENT_7) ||                   \
02560      ((EVENT) == HRTIM_EVENT_8) ||                   \
02561      ((EVENT) == HRTIM_EVENT_9) ||                   \
02562      ((EVENT) == HRTIM_EVENT_10)))
02563
02564
02565 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
02566       ((((EVENT) == HRTIM_EVENT_1) ||            \
02567         ((EVENT) == HRTIM_EVENT_2) ||            \
02568         ((EVENT) == HRTIM_EVENT_3) ||            \
02569         ((EVENT) == HRTIM_EVENT_4) ||            \
02570         ((EVENT) == HRTIM_EVENT_5))              \
02571        ||                                        \
02572       ((((EVENT) == HRTIM_EVENT_6) ||            \
02573         ((EVENT) == HRTIM_EVENT_7) ||            \
02574         ((EVENT) == HRTIM_EVENT_8) ||            \
02575         ((EVENT) == HRTIM_EVENT_9) ||            \
02576         ((EVENT) == HRTIM_EVENT_10)) &&          \
02577         (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
02578         ((FILTER) == HRTIM_EVENTFILTER_1)     || \
02579         ((FILTER) == HRTIM_EVENTFILTER_2)     || \
02580         ((FILTER) == HRTIM_EVENTFILTER_3)     || \
02581         ((FILTER) == HRTIM_EVENTFILTER_4)     || \
02582         ((FILTER) == HRTIM_EVENTFILTER_5)     || \
02583         ((FILTER) == HRTIM_EVENTFILTER_6)     || \
02584         ((FILTER) == HRTIM_EVENTFILTER_7)     || \
02585         ((FILTER) == HRTIM_EVENTFILTER_8)     || \
02586         ((FILTER) == HRTIM_EVENTFILTER_9)     || \
02587         ((FILTER) == HRTIM_EVENTFILTER_10)    || \
02588         ((FILTER) == HRTIM_EVENTFILTER_11)    || \
02589         ((FILTER) == HRTIM_EVENTFILTER_12)    || \
02590         ((FILTER) == HRTIM_EVENTFILTER_13)    || \
02591         ((FILTER) == HRTIM_EVENTFILTER_14)    || \
02592         ((FILTER) == HRTIM_EVENTFILTER_15))))
02593
02594 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
02595              (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
02596               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
02597               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
02598               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
02599
02600 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
02601               (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
02602               ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
02603
02604 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
02605               (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
02606                ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
02607
02608 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
02609     (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
02610      ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
02611
02612 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
02613                 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
02614                  ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
02615                  ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
02616                  ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
02617                  ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
02618                  ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
02619                  ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
02620                  ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
02621                  ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
02622                  ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
02623                  ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
02624                  ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
02625                  ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
02626                  ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
02627                  ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
02628                  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
02629
02630 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
02631               (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
02632                ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
02633
02634 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
02635              (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
02636               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
02637               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
02638               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
02639
02640 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
02641               (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
02642                ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
02643
02644 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
02645               (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
02646                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
02647                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
02648                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
02649                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
02650                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
02651                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
02652                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
02653                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
02654                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
02655
02656 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
02657               (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
02658                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
02659                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
02660                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
02661                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
02662                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
02663                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
02664                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
02665                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
02666                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
02667                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
02668                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
02669                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
02670                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
02671                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
02672                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
02673
02674 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
02675               (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
02676                ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
02677
02678 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
02679               (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
02680                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
02681                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
02682                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
02683                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
02684                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
02685                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
02686                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
02687                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
02688                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
02689                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
02690                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
02691                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
02692                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
02693                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
02694                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
02695                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
02696                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
02697                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP2)       || \
02698                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
02699                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
02700                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP1)       || \
02701                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
02702                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_RESET)      || \
02703                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
02704                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
02705                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
02706                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
02707                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
02708                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
02709                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
02710                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
02711
02712 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
02713              (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
02714               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
02715               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
02716               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
02717               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
02718               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
02719
02720 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
02721     (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION)   || \
02722      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
02723      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910)  || \
02724      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114)  || \
02725      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
02726
02727 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \
02728     ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
02729   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02730   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02731   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02732   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02733   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
02734
02735 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
02736     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
02737      ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
02738
02739 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
02740
02741 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
02742
02743 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
02744
02745
02746 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
02747
02748
02749 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
02750
02751
02752 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
02753
02754 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
02755 /**
02756   * @}
02757   */
02758
02759 /* Exported macros -----------------------------------------------------------*/
02760 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
02761   * @{
02762   */
02763
02764 /** @brief Reset HRTIM handle state
02765   * @param  __HANDLE__ HRTIM handle.
02766   * @retval None
02767   */
02768 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
02769 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                do{                                                       \
02770                                                                     (__HANDLE__)->State             = HAL_HRTIM_STATE_RESET; \
02771                                                                     (__HANDLE__)->MspInitCallback   = NULL;                  \
02772                                                                     (__HANDLE__)->MspDeInitCallback = NULL;                 \
02773                                                                   } while(0)
02774 #else
02775 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
02776 #endif
02777
02778 /** @brief  Enables or disables the timer counter(s)
02779   * @param  __HANDLE__ specifies the HRTIM Handle.
02780   * @param  __TIMERS__ timers to enable/disable
02781   *        This parameter can be any combinations of the following values:
02782   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
02783   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
02784   *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
02785   *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
02786   *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
02787   *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
02788   * @retval None
02789   */
02790 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
02791
02792 /* The counter of a timing unit is disabled only if all the timer outputs */
02793 /* are disabled and no capture is configured                              */
02794 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
02795 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
02796 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
02797 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
02798 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
02799 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
02800   do {\
02801     if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
02802       {\
02803         ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
02804       }\
02805     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
02806       {\
02807         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
02808           {\
02809             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
02810           }\
02811       }\
02812     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
02813       {\
02814         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
02815           {\
02816             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
02817           }\
02818       }\
02819     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
02820       {\
02821         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
02822           {\
02823             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
02824           }\
02825       }\
02826     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
02827       {\
02828         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
02829           {\
02830             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
02831           }\
02832       }\
02833     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
02834       {\
02835         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
02836           {\
02837             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
02838           }\
02839       }\
02840   } while(0U)
02841
02842
02843 /** @brief  Enables or disables the specified HRTIM common interrupts.
02844   * @param  __HANDLE__ specifies the HRTIM Handle.
02845   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02846   *        This parameter can be one of the following values:
02847   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02848   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02849   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
02850   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
02851   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
02852   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02853   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02854   * @retval None
02855   */
02856 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
02857 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
02858
02859 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
02860   * @param  __HANDLE__ specifies the HRTIM Handle.
02861   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02862   *        This parameter can be one of the following values:
02863   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02864   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02865   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02866   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02867   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02868   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02869   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02870   * @retval None
02871   */
02872 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
02873 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
02874
02875 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
02876   * @param  __HANDLE__ specifies the HRTIM Handle.
02877   * @param  __TIMER__ specified the timing unit (Timer A to E)
02878   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
02879   *        This parameter can be one of the following values:
02880   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02881   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02882   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02883   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02884   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02885   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02886   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02887   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02888   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02889   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02890   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02891   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02892   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02893   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02894   * @retval None
02895   */
02896 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
02897 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
02898
02899 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
02900   * @param  __HANDLE__ specifies the HRTIM Handle.
02901   * @param  __INTERRUPT__ specifies the interrupt source to check.
02902   *        This parameter can be one of the following values:
02903   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02904   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02905   *            @arg HRTIM_IT_FLT3: Fault 3 enable
02906   *            @arg HRTIM_IT_FLT4: Fault 4 enable
02907   *            @arg HRTIM_IT_FLT5: Fault 5 enable
02908   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02909   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02910   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02911   */
02912 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02913
02914 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
02915   * @param  __HANDLE__ specifies the HRTIM Handle.
02916   * @param  __INTERRUPT__ specifies the interrupt source to check.
02917   *        This parameter can be one of the following values:
02918   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02919   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02920   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02921   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02922   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02923   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02924   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02925   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02926   */
02927 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02928
02929 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
02930   * @param  __HANDLE__ specifies the HRTIM Handle.
02931   * @param  __TIMER__ specified the timing unit (Timer A to E)
02932   * @param  __INTERRUPT__ specifies the interrupt source to check.
02933   *        This parameter can be one of the following values:
02934   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02935   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02936   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02937   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02938   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02939   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02940   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02941   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02942   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02943   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02944   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02945   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02946   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02947   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02948   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02949   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02950   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02951   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02952   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02953   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02954   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02955   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02956   */
02957 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02958
02959 /** @brief  Clears the specified HRTIM common pending flag.
02960   * @param  __HANDLE__ specifies the HRTIM Handle.
02961   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02962   *        This parameter can be one of the following values:
02963   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
02964   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
02965   *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
02966   *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
02967   *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
02968   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
02969   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
02970   * @retval None
02971   */
02972 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
02973
02974 /** @brief  Clears the specified HRTIM Master pending flag.
02975   * @param  __HANDLE__ specifies the HRTIM Handle.
02976   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02977   *        This parameter can be one of the following values:
02978   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
02979   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
02980   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
02981   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
02982   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
02983   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
02984   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
02985   * @retval None
02986   */
02987 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
02988
02989 /** @brief  Clears the specified HRTIM Timerx pending flag.
02990   * @param  __HANDLE__ specifies the HRTIM Handle.
02991   * @param  __TIMER__ specified the timing unit (Timer A to E)
02992   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02993   *        This parameter can be one of the following values:
02994   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
02995   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
02996   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
02997   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
02998   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
02999   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
03000   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
03001   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
03002   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
03003   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
03004   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
03005   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
03006   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
03007   *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
03008   * @retval None
03009   */
03010 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
03011
03012 /* DMA HANDLING */
03013 /** @brief  Enables or disables the specified HRTIM Master timer DMA requests.
03014   * @param  __HANDLE__ specifies the HRTIM Handle.
03015   * @param  __DMA__ specifies the DMA request to enable or disable.
03016   *        This parameter can be one of the following values:
03017   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
03018   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
03019   *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
03020   *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
03021   *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
03022   *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
03023   *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
03024   * @retval None
03025   */
03026 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
03027 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
03028
03029 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
03030   * @param  __HANDLE__ specifies the HRTIM Handle.
03031   * @param  __TIMER__ specified the timing unit (Timer A to E)
03032   * @param  __DMA__ specifies the DMA request to enable or disable.
03033   *        This parameter can be one of the following values:
03034   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
03035   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
03036   *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
03037   *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
03038   *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
03039   *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
03040   *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
03041   *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
03042   *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
03043   *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
03044   *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
03045   *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
03046   *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
03047   *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
03048   * @retval None
03049   */
03050 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
03051 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
03052
03053 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
03054 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
03055
03056 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
03057 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
03058
03059 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
03060 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
03061
03062 /** @brief  Sets the HRTIM timer Counter Register value on runtime
03063   * @param  __HANDLE__ HRTIM Handle.
03064   * @param  __TIMER__ HRTIM timer
03065   *                   This parameter can be one of the following values:
03066   *                   @arg 0x5 for master timer
03067   *                   @arg 0x0 to 0x4 for timers A to E
03068   * @param  __COUNTER__ specifies the Counter Register new value.
03069   * @retval None
03070   */
03071 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
03072   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
03073    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
03074
03075 /** @brief  Gets the HRTIM timer Counter Register value on runtime
03076   * @param  __HANDLE__ HRTIM Handle.
03077   * @param  __TIMER__ HRTIM timer
03078   *                   This parameter can be one of the following values:
03079   *                   @arg 0x5 for master timer
03080   *                   @arg 0x0 to 0x4 for timers A to E
03081   * @retval HRTIM timer Counter Register value
03082   */
03083 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
03084   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
03085    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
03086
03087 /** @brief  Sets the HRTIM timer Period value on runtime
03088   * @param  __HANDLE__ HRTIM Handle.
03089   * @param  __TIMER__ HRTIM timer
03090   *                   This parameter can be one of the following values:
03091   *                   @arg 0x5 for master timer
03092   *                   @arg 0x0 to 0x4 for timers A to E
03093   * @param  __PERIOD__ specifies the Period Register new value.
03094   * @retval None
03095   */
03096 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
03097   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
03098    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
03099
03100 /** @brief  Gets the HRTIM timer Period Register value on runtime
03101   * @param  __HANDLE__ HRTIM Handle.
03102   * @param  __TIMER__ HRTIM timer
03103   *                   This parameter can be one of the following values:
03104   *                   @arg 0x5 for master timer
03105   *                   @arg 0x0 to 0x4 for timers A to E
03106   * @retval timer Period Register
03107   */
03108 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
03109   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
03110    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
03111
03112 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
03113   * @param  __HANDLE__ HRTIM Handle.
03114   * @param  __TIMER__ HRTIM timer
03115   *                   This parameter can be one of the following values:
03116   *                   @arg 0x5 for master timer
03117   *                   @arg 0x0 to 0x4 for timers A to E
03118   * @param  __PRESCALER__ specifies the clock prescaler new value.
03119   *                   This parameter can be one of the following values:
03120   *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
03121   *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
03122   *                   @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
03123   *                   @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
03124   *                   @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
03125   *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
03126   *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
03127   *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
03128   * @retval None
03129   */
03130 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
03131   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
03132    (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
03133
03134 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
03135   * @param  __HANDLE__ HRTIM Handle.
03136   * @param  __TIMER__ HRTIM timer
03137   *                   This parameter can be one of the following values:
03138   *                   @arg 0x5 for master timer
03139   *                   @arg 0x0 to 0x4 for timers A to E
03140   * @retval timer clock prescaler value
03141   */
03142 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
03143   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
03144    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
03145
03146 /** @brief  Sets the HRTIM timer Compare Register value on runtime
03147   * @param  __HANDLE__ HRTIM Handle.
03148   * @param  __TIMER__ HRTIM timer
03149   *                   This parameter can be one of the following values:
03150   *                   @arg 0x0 to 0x4 for timers A to E
03151   * @param  __COMPAREUNIT__ timer compare unit
03152   *                   This parameter can be one of the following values:
03153   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03154   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03155   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03156   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03157   * @param  __COMPARE__ specifies the Compare new value.
03158   * @retval None
03159   */
03160 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
03161       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03162         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
03163          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
03164          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
03165          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
03166          : \
03167         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
03168          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
03169          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
03170          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
03171
03172 /** @brief  Gets the HRTIM timer Compare Register value on runtime
03173   * @param  __HANDLE__ HRTIM Handle.
03174   * @param  __TIMER__ HRTIM timer
03175   *                   This parameter can be one of the following values:
03176   *                   @arg 0x0 to 0x4 for timers A to E
03177   * @param  __COMPAREUNIT__ timer compare unit
03178   *                   This parameter can be one of the following values:
03179   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03180   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03181   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03182   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03183   * @retval Compare value
03184   */
03185 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
03186       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03187         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
03188          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
03189          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
03190          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
03191          : \
03192         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
03193          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
03194          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
03195          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
03196
03197 /**
03198   * @}
03199   */
03200
03201 /* Exported functions --------------------------------------------------------*/
03202 /** @addtogroup HRTIM_Exported_Functions
03203 * @{
03204 */
03205
03206 /** @addtogroup HRTIM_Exported_Functions_Group1
03207 * @{
03208 */
03209
03210 /* Initialization and Configuration functions  ********************************/
03211 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
03212
03213 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
03214
03215 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
03216
03217 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
03218
03219 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
03220                                            uint32_t TimerIdx,
03221                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
03222 /**
03223   * @}
03224   */
03225
03226 /** @addtogroup HRTIM_Exported_Functions_Group2
03227 * @{
03228 */
03229
03230 /* Simple time base related functions  *****************************************/
03231 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
03232                                            uint32_t TimerIdx);
03233
03234 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
03235                                           uint32_t TimerIdx);
03236
03237 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03238                                               uint32_t TimerIdx);
03239
03240 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03241                                              uint32_t TimerIdx);
03242
03243 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03244                                                uint32_t TimerIdx,
03245                                                uint32_t SrcAddr,
03246                                                uint32_t DestAddr,
03247                                                uint32_t Length);
03248
03249 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03250                                               uint32_t TimerIdx);
03251
03252 /**
03253   * @}
03254   */
03255
03256 /** @addtogroup HRTIM_Exported_Functions_Group3
03257 * @{
03258 */
03259 /* Simple output compare related functions  ************************************/
03260 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03261                                                  uint32_t TimerIdx,
03262                                                  uint32_t OCChannel,
03263                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
03264
03265 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
03266                                          uint32_t TimerIdx,
03267                                          uint32_t OCChannel);
03268
03269 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
03270                                         uint32_t TimerIdx,
03271                                         uint32_t OCChannel);
03272
03273 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
03274                                             uint32_t TimerIdx,
03275                                             uint32_t OCChannel);
03276
03277 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
03278                                            uint32_t TimerIdx,
03279                                            uint32_t OCChannel);
03280
03281 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03282                                              uint32_t TimerIdx,
03283                                              uint32_t OCChannel,
03284                                              uint32_t SrcAddr,
03285                                              uint32_t DestAddr,
03286                                              uint32_t Length);
03287
03288 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03289                                             uint32_t TimerIdx,
03290                                             uint32_t OCChannel);
03291
03292 /**
03293   * @}
03294   */
03295
03296 /** @addtogroup HRTIM_Exported_Functions_Group4
03297 * @{
03298 */
03299 /* Simple PWM output related functions  ****************************************/
03300 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03301                                                   uint32_t TimerIdx,
03302                                                   uint32_t PWMChannel,
03303                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
03304
03305 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
03306                                           uint32_t TimerIdx,
03307                                           uint32_t PWMChannel);
03308
03309 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
03310                                          uint32_t TimerIdx,
03311                                          uint32_t PWMChannel);
03312
03313 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
03314                                              uint32_t TimerIdx,
03315                                              uint32_t PWMChannel);
03316
03317 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
03318                                             uint32_t TimerIdx,
03319                                             uint32_t PWMChannel);
03320
03321 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03322                                               uint32_t TimerIdx,
03323                                               uint32_t PWMChannel,
03324                                               uint32_t SrcAddr,
03325                                               uint32_t DestAddr,
03326                                               uint32_t Length);
03327
03328 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03329                                              uint32_t TimerIdx,
03330                                              uint32_t PWMChannel);
03331
03332 /**
03333   * @}
03334   */
03335
03336 /** @addtogroup HRTIM_Exported_Functions_Group5
03337 * @{
03338 */
03339 /* Simple capture related functions  *******************************************/
03340 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03341                                                       uint32_t TimerIdx,
03342                                                       uint32_t CaptureChannel,
03343                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
03344
03345 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
03346                                               uint32_t TimerIdx,
03347                                               uint32_t CaptureChannel);
03348
03349 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
03350                                              uint32_t TimerIdx,
03351                                              uint32_t CaptureChannel);
03352
03353 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
03354                                                  uint32_t TimerIdx,
03355                                                  uint32_t CaptureChannel);
03356
03357 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
03358                                                 uint32_t TimerIdx,
03359                                                 uint32_t CaptureChannel);
03360
03361 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03362                                                   uint32_t TimerIdx,
03363                                                   uint32_t CaptureChannel,
03364                                                   uint32_t SrcAddr,
03365                                                   uint32_t DestAddr,
03366                                                   uint32_t Length);
03367
03368 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03369                                                  uint32_t TimerIdx,
03370                                                  uint32_t CaptureChannel);
03371
03372 /**
03373   * @}
03374   */
03375
03376 /** @addtogroup HRTIM_Exported_Functions_Group6
03377 * @{
03378 */
03379 /* Simple one pulse related functions  *****************************************/
03380 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03381                                                        uint32_t TimerIdx,
03382                                                        uint32_t OnePulseChannel,
03383                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
03384
03385 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
03386                                                uint32_t TimerIdx,
03387                                                uint32_t OnePulseChannel);
03388
03389 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
03390                                               uint32_t TimerIdx,
03391                                              uint32_t OnePulseChannel);
03392
03393 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03394                                                   uint32_t TimerIdx,
03395                                                   uint32_t OnePulseChannel);
03396
03397 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03398                                                  uint32_t TimerIdx,
03399                                                  uint32_t OnePulseChannel);
03400
03401 /**
03402   * @}
03403   */
03404
03405 /** @addtogroup HRTIM_Exported_Functions_Group7
03406 * @{
03407 */
03408 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
03409                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
03410
03411 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
03412                                         uint32_t Event,
03413                                         HRTIM_EventCfgTypeDef* pEventCfg);
03414
03415 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03416                                                  uint32_t Prescaler);
03417
03418 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
03419                                         uint32_t Fault,
03420                                         HRTIM_FaultCfgTypeDef* pFaultCfg);
03421
03422 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03423                                                  uint32_t Prescaler);
03424
03425 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03426                             uint32_t Faults,
03427                             uint32_t Enable);
03428
03429 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
03430                                              uint32_t ADCTrigger,
03431                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
03432
03433 /**
03434   * @}
03435   */
03436
03437 /** @addtogroup HRTIM_Exported_Functions_Group8
03438 * @{
03439 */
03440 /* Waveform related functions *************************************************/
03441 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
03442                                                 uint32_t TimerIdx,
03443                                                 HRTIM_TimerCfgTypeDef * pTimerCfg);
03444
03445 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
03446                                                   uint32_t TimerIdx,
03447                                                   uint32_t CompareUnit,
03448                                                   HRTIM_CompareCfgTypeDef* pCompareCfg);
03449
03450 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
03451                                                   uint32_t TimerIdx,
03452                                                   uint32_t CaptureUnit,
03453                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg);
03454
03455 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
03456                                                  uint32_t TimerIdx,
03457                                                  uint32_t Output,
03458                                                  HRTIM_OutputCfgTypeDef * pOutputCfg);
03459
03460 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03461                                                    uint32_t TimerIdx,
03462                                                    uint32_t Output,
03463                                                    uint32_t OutputLevel);
03464
03465 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
03466                                                       uint32_t TimerIdx,
03467                                                       uint32_t Event,
03468                                                       HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
03469
03470 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
03471                                            uint32_t TimerIdx,
03472                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
03473
03474 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
03475                                               uint32_t TimerIdx,
03476                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
03477
03478 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
03479                                            uint32_t TimerIdx,
03480                                            uint32_t RegistersToUpdate);
03481
03482
03483 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
03484                                                  uint32_t Timers);
03485
03486 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
03487                                                  uint32_t Timers);
03488
03489 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
03490                                                  uint32_t Timers);
03491
03492 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
03493                                                  uint32_t Timers);
03494
03495 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03496                                                      uint32_t Timers);
03497
03498 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03499                                                     uint32_t Timers);
03500
03501 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
03502                                                 uint32_t OutputsToStart);
03503
03504 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
03505                                                uint32_t OutputsToStop);
03506
03507 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
03508                                          uint32_t Enable);
03509
03510 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
03511
03512 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
03513                                             uint32_t TimerIdx,
03514                                             uint32_t CaptureUnit);
03515
03516 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
03517                                            uint32_t Timers);
03518
03519 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
03520                                           uint32_t Timers);
03521
03522 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
03523                                              uint32_t TimerIdx,
03524                                              uint32_t BurstBufferAddress,
03525                                              uint32_t BurstBufferLength);
03526
03527 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
03528                                           uint32_t Timers);
03529
03530 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
03531                                           uint32_t Timers);
03532
03533 /**
03534   * @}
03535   */
03536
03537 /** @addtogroup HRTIM_Exported_Functions_Group9
03538 * @{
03539 */
03540 /* HRTIM peripheral state functions */
03541 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
03542
03543 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
03544                                     uint32_t TimerIdx,
03545                                     uint32_t CaptureUnit);
03546
03547 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03548                                           uint32_t TimerIdx,
03549                                           uint32_t Output);
03550
03551 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
03552                                           uint32_t TimerIdx,
03553                                           uint32_t Output);
03554
03555 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
03556                                               uint32_t TimerIdx,
03557                                               uint32_t Output);
03558
03559 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
03560
03561 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03562                                             uint32_t TimerIdx);
03563
03564 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03565                                          uint32_t TimerIdx);
03566
03567 /**
03568   * @}
03569   */
03570
03571 /** @addtogroup HRTIM_Exported_Functions_Group10
03572 * @{
03573 */
03574 /* IRQ handler */
03575 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
03576                           uint32_t TimerIdx);
03577
03578 /* HRTIM events related callback functions */
03579 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
03580 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
03581 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
03582 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
03583 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
03584 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
03585 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
03586 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
03587
03588 /* Timer events related callback functions */
03589 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
03590                                               uint32_t TimerIdx);
03591 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
03592                                               uint32_t TimerIdx);
03593 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03594                                             uint32_t TimerIdx);
03595 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03596                                             uint32_t TimerIdx);
03597 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
03598                                             uint32_t TimerIdx);
03599 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
03600                                             uint32_t TimerIdx);
03601 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03602                                             uint32_t TimerIdx);
03603 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03604                                             uint32_t TimerIdx);
03605 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
03606                                                 uint32_t TimerIdx);
03607 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
03608                                            uint32_t TimerIdx);
03609 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
03610                                          uint32_t TimerIdx);
03611 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03612                                            uint32_t TimerIdx);
03613 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
03614                                          uint32_t TimerIdx);
03615 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03616                                            uint32_t TimerIdx);
03617 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
03618                                                uint32_t TimerIdx);
03619 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
03620
03621 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
03622 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
03623                                              HAL_HRTIM_CallbackIDTypeDef CallbackID,
03624                                              pHRTIM_CallbackTypeDef      pCallback);
03625
03626 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
03627                                                HAL_HRTIM_CallbackIDTypeDef CallbackID);
03628
03629 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *        hhrtim,
03630                                                  HAL_HRTIM_CallbackIDTypeDef  CallbackID,
03631                                                  pHRTIM_TIMxCallbackTypeDef   pCallback);
03632
03633 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
03634                                                    HAL_HRTIM_CallbackIDTypeDef CallbackID);
03635 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
03636
03637 /**
03638   * @}
03639   */
03640
03641 /**
03642   * @}
03643   */
03644
03645 /**
03646   * @}
03647   */
03648
03649 /**
03650   * @}
03651   */
03652
03653 #endif /* HRTIM1 */
03654
03655 #ifdef __cplusplus
03656 }
03657 #endif
03658
03659 #endif /* STM32H7xx_HAL_HRTIM_H */
03660
03661 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hsem.c Source File

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stm32h7xx_hal_hsem.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hsem.c
00004   * @author  MCD Application Team
00005   * @brief   HSEM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the semaphore peripheral:
00008   *           + Semaphore Take function (2-Step Procedure) , non blocking
00009   *           + Semaphore FastTake function (1-Step Procedure) , non blocking
00010   *           + Semaphore Status check
00011   *           + Semaphore Clear Key Set and Get
00012   *           + Release and release all functions
00013   *           + Semaphore notification enabling and disabling and callnack functions
00014   *           + IRQ handler management
00015   *
00016   *
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021   [..]
00022       (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
00023            (++) the semaphore ID from 0 to 31
00024            (++) the process ID from 0 to 255
00025       (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
00026            (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
00027       (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
00028           (++) the semaphore ID from 0_ID to 31
00029           (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
00030       (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
00031            (++) the semaphore ID from 0 to 31
00032            (++) the process ID from 0 to 255:
00033            (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
00034          may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
00035          semaphore remains taken (locked)
00036
00037       (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
00038           This function takes as parameters :
00039            (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
00040               HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
00041            (++) the Master ID:
00042            (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
00043            to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
00044            Key or the MasterID doesn't match, semaphores remains taken (locked)
00045
00046       (#)Semaphores Release all key functions:
00047          (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
00048          (++)  HAL_HSEM_GetClearKey() to get release all Key
00049       (#)Semaphores notification functions :
00050          (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
00051                a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
00052                the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
00053                semaphores (bitfield).
00054
00055          (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
00056          (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
00057                 Used by the notification functions
00058      *** HSEM HAL driver macros list ***
00059      =============================================
00060      [..] Below the list of most used macros in HSEM HAL driver.
00061
00062       (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
00063       [..] Example of use :
00064       [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
00065       [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
00066       (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
00067       (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
00068       (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
00069       (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
00070       (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
00071
00072   @endverbatim
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00077   * All rights reserved.</center></h2>
00078   *
00079   * This software component is licensed by ST under BSD 3-Clause license,
00080   * the "License"; You may not use this file except in compliance with the
00081   * License. You may obtain a copy of the License at:
00082   *                        opensource.org/licenses/BSD-3-Clause
00083   *
00084   ******************************************************************************
00085   */
00086
00087 /* Includes ------------------------------------------------------------------*/
00088 #include "stm32h7xx_hal.h"
00089
00090 /** @addtogroup STM32H7xx_HAL_Driver
00091   * @{
00092   */
00093
00094 /** @defgroup HSEM HSEM
00095   * @brief HSEM HAL module driver
00096   * @{
00097   */
00098
00099 #ifdef HAL_HSEM_MODULE_ENABLED
00100
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private define ------------------------------------------------------------*/
00103 #if defined(DUAL_CORE)
00104 #ifndef HSEM_R_MASTERID
00105 #define HSEM_R_MASTERID HSEM_R_COREID
00106 #endif
00107
00108 #ifndef HSEM_RLR_MASTERID
00109 #define HSEM_RLR_MASTERID HSEM_RLR_COREID
00110 #endif
00111
00112 #ifndef HSEM_CR_MASTERID
00113 #define HSEM_CR_MASTERID HSEM_CR_COREID
00114 #endif
00115 #endif /* DUAL_CORE */
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Private functions ---------------------------------------------------------*/
00120 /* Exported functions --------------------------------------------------------*/
00121
00122 /** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
00127   *  @brief    HSEM Take and Release functions
00128   *
00129 @verbatim
00130  ==============================================================================
00131               ##### HSEM Take and Release functions #####
00132  ==============================================================================
00133 [..] This section provides functions allowing to:
00134       (+) Take a semaphore with 2 Step method
00135       (+) Fast Take a semaphore with 1 Step method
00136       (+) Check semaphore state Taken or not
00137       (+) Release a semaphore
00138       (+) Release all semaphore at once
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144
00145 /**
00146   * @brief  Take a semaphore in 2 Step mode.
00147   * @param  SemID: semaphore ID from 0 to 31
00148   * @param  ProcessID: Process ID from 0 to 255
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
00152 {
00153   /* Check the parameters */
00154   assert_param(IS_HSEM_SEMID(SemID));
00155   assert_param(IS_HSEM_PROCESSID(ProcessID));
00156
00157 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00158   /* First step  write R register with MasterID, processID and take bit=1*/
00159   HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
00160
00161   /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
00162   if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
00163   {
00164     /*take success when MasterID and ProcessID match and take bit set*/
00165     return HAL_OK;
00166   }
00167 #else
00168   /* First step  write R register with MasterID, processID and take bit=1*/
00169   HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
00170
00171   /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
00172   if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
00173   {
00174     /*take success when MasterID and ProcessID match and take bit set*/
00175     return HAL_OK;
00176   }
00177 #endif
00178
00179   /* Semaphore take fails*/
00180   return HAL_ERROR;
00181 }
00182
00183 /**
00184   * @brief  Fast Take a semaphore with 1 Step mode.
00185   * @param  SemID: semaphore ID from 0 to 31
00186   * @retval HAL status
00187   */
00188 HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
00189 {
00190   /* Check the parameters */
00191   assert_param(IS_HSEM_SEMID(SemID));
00192
00193 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00194   /* Read the RLR register to take the semaphore */
00195   if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
00196   {
00197     /*take success when MasterID match and take bit set*/
00198     return HAL_OK;
00199   }
00200 #else
00201   /* Read the RLR register to take the semaphore */
00202   if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
00203   {
00204     /*take success when MasterID match and take bit set*/
00205     return HAL_OK;
00206   }
00207 #endif
00208
00209   /* Semaphore take fails */
00210   return HAL_ERROR;
00211 }
00212 /**
00213   * @brief  Check semaphore state Taken or not.
00214   * @param  SemID: semaphore ID
00215   * @retval HAL HSEM state
00216   */
00217 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
00218 {
00219   return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
00220 }
00221
00222
00223 /**
00224   * @brief  Release a semaphore.
00225   * @param  SemID: semaphore ID from 0 to 31
00226   * @param  ProcessID: Process ID from 0 to 255
00227   * @retval None
00228   */
00229 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
00230 {
00231   /* Check the parameters */
00232   assert_param(IS_HSEM_SEMID(SemID));
00233   assert_param(IS_HSEM_PROCESSID(ProcessID));
00234
00235   /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
00236 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00237   HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
00238 #else
00239   HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
00240 #endif
00241
00242 }
00243
00244 /**
00245   * @brief  Release All semaphore used by a given Master .
00246   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00247   * @param  CoreID: CoreID of the CPU that is using semaphores to be released
00248   * @retval None
00249   */
00250 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
00251 {
00252   assert_param(IS_HSEM_KEY(Key));
00253   assert_param(IS_HSEM_COREID(CoreID));
00254
00255   HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
00256 }
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00263   *  @brief    HSEM Set and Get Key functions.
00264   *
00265 @verbatim
00266   ==============================================================================
00267               ##### HSEM Set and Get Key functions #####
00268   ==============================================================================
00269     [..]  This section provides functions allowing to:
00270       (+) Set semaphore Key
00271       (+) Get semaphore Key
00272 @endverbatim
00273
00274   * @{
00275   */
00276
00277 /**
00278   * @brief  Set semaphore Key .
00279   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00280   * @retval None
00281   */
00282 void  HAL_HSEM_SetClearKey(uint32_t Key)
00283 {
00284   assert_param(IS_HSEM_KEY(Key));
00285
00286   MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
00287
00288 }
00289
00290 /**
00291   * @brief  Get semaphore Key .
00292   * @retval Semaphore Key , value from 0 to 0xFFFF
00293   */
00294 uint32_t HAL_HSEM_GetClearKey(void)
00295 {
00296   return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
00297 }
00298
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
00304   *  @brief    HSEM Notification functions.
00305   *
00306 @verbatim
00307   ==============================================================================
00308       ##### HSEM IRQ handler management and Notification functions #####
00309   ==============================================================================
00310 [..]  This section provides HSEM IRQ handler and Notification function.
00311
00312 @endverbatim
00313   * @{
00314   */
00315
00316 /**
00317   * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
00318   * @param  SemMask: Mask of Released semaphores
00319   * @retval Semaphore Key
00320   */
00321 void HAL_HSEM_ActivateNotification(uint32_t SemMask)
00322 {
00323 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00324   /*enable the semaphore mask interrupts */
00325   if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
00326   {
00327     /*Use interrupt line 0 for CPU1 Master */
00328     HSEM->C1IER |= SemMask;
00329   }
00330   else /* HSEM_CPU2_COREID */
00331   {
00332     /*Use interrupt line 1 for CPU2 Master*/
00333     HSEM->C2IER |= SemMask;
00334   }
00335 #else
00336   HSEM_COMMON->IER |= SemMask;
00337 #endif
00338 }
00339
00340 /**
00341   * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
00342   * @param  SemMask: Mask of Released semaphores
00343   * @retval Semaphore Key
00344   */
00345 void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
00346 {
00347 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00348   /*enable the semaphore mask interrupts */
00349   if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
00350   {
00351     /*Use interrupt line 0 for CPU1 Master */
00352     HSEM->C1IER &= ~SemMask;
00353   }
00354   else /* HSEM_CPU2_COREID */
00355   {
00356     /*Use interrupt line 1 for CPU2 Master*/
00357     HSEM->C2IER &= ~SemMask;
00358   }
00359 #else
00360   HSEM_COMMON->IER &= ~SemMask;
00361 #endif
00362 }
00363
00364 /**
00365   * @brief  This function handles HSEM interrupt request
00366   * @retval None
00367   */
00368 void HAL_HSEM_IRQHandler(void)
00369 {
00370   uint32_t statusreg;
00371 #if  USE_MULTI_CORE_SHARED_CODE != 0U
00372   if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
00373   {
00374     /* Get the list of masked freed semaphores*/
00375     statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
00376
00377     /*Disable Interrupts*/
00378     HSEM->C1IER &= ~((uint32_t)statusreg);
00379
00380     /*Clear Flags*/
00381     HSEM->C1ICR = ((uint32_t)statusreg);
00382   }
00383   else /* HSEM_CPU2_COREID */
00384   {
00385     /* Get the list of masked freed semaphores*/
00386     statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
00387
00388     /*Disable Interrupts*/
00389     HSEM->C2IER &= ~((uint32_t)statusreg);
00390
00391     /*Clear Flags*/
00392     HSEM->C2ICR = ((uint32_t)statusreg);
00393   }
00394 #else
00395   /* Get the list of masked freed semaphores*/
00396   statusreg = HSEM_COMMON->MISR;
00397
00398   /*Disable Interrupts*/
00399   HSEM_COMMON->IER &= ~((uint32_t)statusreg);
00400
00401   /*Clear Flags*/
00402   HSEM_COMMON->ICR = ((uint32_t)statusreg);
00403
00404 #endif
00405   /* Call FreeCallback */
00406   HAL_HSEM_FreeCallback(statusreg);
00407 }
00408
00409 /**
00410   * @brief Semaphore Released Callback.
00411   * @param SemMask: Mask of Released semaphores
00412   * @retval None
00413   */
00414 __weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
00415 {
00416   /* Prevent unused argument(s) compilation warning */
00417   UNUSED(SemMask);
00418
00419   /* NOTE : This function should not be modified, when the callback is needed,
00420   the HAL_HSEM_FreeCallback can be implemented in the user file
00421     */
00422 }
00423
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 #endif /* HAL_HSEM_MODULE_ENABLED */
00433 /**
00434   * @}
00435   */
00436
00437 /**
00438   * @}
00439   */
00440
00441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_hsem.h Source File

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stm32h7xx_hal_hsem.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hsem.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HSEM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_HSEM_H
00022 #define STM32H7xx_HAL_HSEM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032    * @{
00033    */
00034
00035 /** @addtogroup HSEM
00036    * @{
00037    */
00038
00039 /* Exported macro ------------------------------------------------------------*/
00040 /** @defgroup HSEM_Exported_Macros HSEM Exported Macros
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  SemID to mask helper Macro.
00046   * @param  __SEMID__: semaphore ID from 0 to 31
00047   * @retval Semaphore Mask.
00048   */
00049 #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
00050
00051 /**
00052   * @brief  Enables the specified HSEM interrupts.
00053   * @param  __SEM_MASK__: semaphores Mask
00054   * @retval None.
00055   */
00056 #if defined(DUAL_CORE)
00057 #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00058                                             (HSEM->C1IER |= (__SEM_MASK__)) : \
00059                                             (HSEM->C2IER |= (__SEM_MASK__)))
00060 #else
00061 #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
00062 #endif /* DUAL_CORE */
00063 /**
00064   * @brief  Disables the specified HSEM interrupts.
00065   * @param  __SEM_MASK__: semaphores Mask
00066   * @retval None.
00067   */
00068 #if defined(DUAL_CORE)
00069 #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00070                                              (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
00071                                              (HSEM->C2IER &= ~(__SEM_MASK__)))
00072 #else
00073 #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
00074 #endif /* DUAL_CORE */
00075
00076 /**
00077   * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
00078   * @param  __SEM_MASK__: semaphores Mask
00079   * @retval semaphores Mask : Semaphores where an interrupt occurred.
00080   */
00081 #if defined(DUAL_CORE)
00082 #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00083                                          ((__SEM_MASK__) & HSEM->C1MISR) :        \
00084                                          ((__SEM_MASK__) & HSEM->C2MISR1))
00085 #else
00086 #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
00087 #endif /* DUAL_CORE */
00088
00089 /**
00090   * @brief  Get the semaphores release status flags.
00091   * @param  __SEM_MASK__: semaphores Mask
00092   * @retval semaphores Mask : Semaphores where Release flags rise.
00093   */
00094 #if defined(DUAL_CORE)
00095 #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00096                                            (__SEM_MASK__) & HSEM->C1ISR :           \
00097                                            (__SEM_MASK__) & HSEM->C2ISR)
00098 #else
00099 #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
00100 #endif /* DUAL_CORE */
00101
00102 /**
00103   * @brief  Clears the HSEM Interrupt flags.
00104   * @param  __SEM_MASK__: semaphores Mask
00105   * @retval None.
00106   */
00107 #if defined(DUAL_CORE)
00108 #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00109                                              (HSEM->C1ICR |= (__SEM_MASK__)) :        \
00110                                              (HSEM->C2ICR |= (__SEM_MASK__)))
00111 #else
00112 #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
00113 #endif /* DUAL_CORE */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @defgroup HSEM_Exported_Functions HSEM Exported Functions
00121   * @{
00122   */
00123
00124 /** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
00125   * @brief    HSEM Take and Release functions
00126   * @{
00127   */
00128
00129 /* HSEM semaphore take (lock) using 2-Step  method ****************************/
00130 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
00131 /* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
00132 HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
00133 /* HSEM Check semaphore state Taken or not   **********************************/
00134 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
00135 /* HSEM Release  **************************************************************/
00136 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
00137 /* HSEM Release All************************************************************/
00138 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00145   * @brief    HSEM Set and Get Key functions.
00146   * @{
00147   */
00148 /* HSEM Set Clear Key *********************************************************/
00149 void  HAL_HSEM_SetClearKey(uint32_t Key);
00150 /* HSEM Get Clear Key *********************************************************/
00151 uint32_t HAL_HSEM_GetClearKey(void);
00152 /**
00153   * @}
00154   */
00155
00156 /** @addtogroup HSEM_Exported_Functions_Group3
00157   * @brief   HSEM Notification functions
00158   * @{
00159   */
00160 /* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
00161 void HAL_HSEM_ActivateNotification(uint32_t SemMask);
00162 /* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
00163 void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
00164 /* HSEM Free Callback (When a semaphore is released)  *******************************/
00165 void HAL_HSEM_FreeCallback(uint32_t SemMask);
00166 /* HSEM IRQ Handler  **********************************************************/
00167 void HAL_HSEM_IRQHandler(void);
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /* Private macros ------------------------------------------------------------*/
00178 /** @defgroup HSEM_Private_Macros HSEM Private Macros
00179   * @{
00180   */
00181
00182 #define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
00183
00184 #define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
00185
00186 #define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
00187
00188 #if defined(DUAL_CORE)
00189 #define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
00190                                     ((__COREID__) == HSEM_CPU2_COREID))
00191 #else
00192 #define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
00193 #endif
00194
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 #ifdef __cplusplus
00209 }
00210 #endif
00211
00212 #endif /* STM32H7xx_HAL_HSEM_H */
00213
00214 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:49:59 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c.c Source File

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stm32h7xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The I2C HAL driver can be used as follows:
00018
00019     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00020         I2C_HandleTypeDef  hi2c;
00021
00022     (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
00023         (##) Enable the I2Cx interface clock
00024         (##) I2C pins configuration
00025             (+++) Enable the clock for the I2C GPIOs
00026             (+++) Configure I2C pins as alternate function open-drain
00027         (##) NVIC configuration if you need to use interrupt process
00028             (+++) Configure the I2Cx interrupt priority
00029             (+++) Enable the NVIC I2C IRQ Channel
00030         (##) DMA Configuration if you need to use DMA process
00031             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
00032             (+++) Enable the DMAx interface clock using
00033             (+++) Configure the DMA handle parameters
00034             (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
00035             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00037                   the DMA Tx or Rx stream or channel depends on Instance
00038
00039     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00040         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00041
00042     (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
00043         (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
00044
00045     (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
00046
00047     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00048
00049     *** Polling mode IO operation ***
00050     =================================
00051     [..]
00052       (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
00053       (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
00054       (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
00055       (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
00056
00057     *** Polling mode IO MEM operation ***
00058     =====================================
00059     [..]
00060       (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
00061       (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
00062
00063
00064     *** Interrupt mode IO operation ***
00065     ===================================
00066     [..]
00067       (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
00068       (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00069            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00070       (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
00071       (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00072            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00073       (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
00074       (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00075            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00076       (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
00077       (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00078            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00079       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00080            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00081       (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00082       (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00083            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00084       (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00085            This action will inform Master to generate a Stop condition to discard the communication.
00086
00087
00088     *** Interrupt mode or DMA mode IO sequential operation ***
00089     ==========================================================
00090     [..]
00091       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00092           when a direction change during transfer
00093     [..]
00094       (+) A specific option field manage the different steps of a sequential transfer
00095       (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
00096       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00097       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00098                             and data to transfer without a final stop condition
00099       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition, an then permit a call the same master sequential interface
00101                             several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
00102                             or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
00103       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00104                             and with new data to transfer if the direction change or manage only the new data to transfer
00105                             if no direction change and without a final stop condition in both cases
00106       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00107                             and with new data to transfer if the direction change or manage only the new data to transfer
00108                             if no direction change and with a final stop condition in both cases
00109       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
00110                             interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
00111                             Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00112                               or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00113                               or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00114                               or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
00115                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
00116                               without stopping the communication and so generate a restart condition.
00117       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
00118                             interface.
00119                             Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00120                               or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00121                               or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00122                               or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
00123                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
00124
00125       (+) Differents sequential I2C interfaces are listed below:
00126       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
00127             or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
00128       (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00129            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00130       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
00131             or using @ref HAL_I2C_Master_Seq_Receive_DMA()
00132       (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00133            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00134       (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00135       (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00136            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00137       (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
00138       (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
00139            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00140       (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
00141            add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
00142       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
00143             or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
00144       (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00145            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00146       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
00147             or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
00148       (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00149            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00150       (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00151            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00152       (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00153            This action will inform Master to generate a Stop condition to discard the communication.
00154
00155     *** Interrupt mode IO MEM operation ***
00156     =======================================
00157     [..]
00158       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00159           @ref HAL_I2C_Mem_Write_IT()
00160       (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
00161            add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
00162       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00163           @ref HAL_I2C_Mem_Read_IT()
00164       (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
00165            add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
00166       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00167            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00168
00169     *** DMA mode IO operation ***
00170     ==============================
00171     [..]
00172       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00173           @ref HAL_I2C_Master_Transmit_DMA()
00174       (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00175            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00176       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00177           @ref HAL_I2C_Master_Receive_DMA()
00178       (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00179            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00180       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00181           @ref HAL_I2C_Slave_Transmit_DMA()
00182       (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00183            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00184       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00185           @ref HAL_I2C_Slave_Receive_DMA()
00186       (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00187            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00188       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00189            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00190       (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00191       (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00192            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00193       (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00194            This action will inform Master to generate a Stop condition to discard the communication.
00195
00196     *** DMA mode IO MEM operation ***
00197     =================================
00198     [..]
00199       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00200           @ref HAL_I2C_Mem_Write_DMA()
00201       (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
00202            add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
00203       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00204           @ref HAL_I2C_Mem_Read_DMA()
00205       (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
00206            add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
00207       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00208            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00209
00210
00211      *** I2C HAL driver macros list ***
00212      ==================================
00213      [..]
00214        Below the list of most used macros in I2C HAL driver.
00215
00216       (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
00217       (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
00218       (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00219       (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00220       (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00221       (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00222       (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00223
00224      *** Callback registration ***
00225      =============================================
00226     [..]
00227      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
00228      allows the user to configure dynamically the driver callbacks.
00229      Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
00230      to register an interrupt callback.
00231     [..]
00232      Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
00233        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00234        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00235        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00236        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00237        (+) ListenCpltCallback   : callback for end of listen mode.
00238        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00239        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00240        (+) ErrorCallback        : callback for error detection.
00241        (+) AbortCpltCallback    : callback for abort completion process.
00242        (+) MspInitCallback      : callback for Msp Init.
00243        (+) MspDeInitCallback    : callback for Msp DeInit.
00244      This function takes as parameters the HAL peripheral handle, the Callback ID
00245      and a pointer to the user callback function.
00246     [..]
00247      For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
00248     [..]
00249      Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
00250      weak function.
00251      @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
00252      and the Callback ID.
00253      This function allows to reset following callbacks:
00254        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00255        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00256        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00257        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00258        (+) ListenCpltCallback   : callback for end of listen mode.
00259        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00260        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00261        (+) ErrorCallback        : callback for error detection.
00262        (+) AbortCpltCallback    : callback for abort completion process.
00263        (+) MspInitCallback      : callback for Msp Init.
00264        (+) MspDeInitCallback    : callback for Msp DeInit.
00265     [..]
00266      For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
00267     [..]
00268      By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
00269      all callbacks are set to the corresponding weak functions:
00270      examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
00271      Exception done for MspInit and MspDeInit functions that are
00272      reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
00273      these callbacks are null (not registered beforehand).
00274      If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
00275      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00276     [..]
00277      Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
00278      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00279      in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
00280      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00281      Then, the user first registers the MspInit/MspDeInit user callbacks
00282      using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
00283      or @ref HAL_I2C_Init() function.
00284     [..]
00285      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
00286      not defined, the callback registration feature is not available and all callbacks
00287      are set to the corresponding weak functions.
00288
00289      [..]
00290        (@) You can refer to the I2C HAL driver header file for more useful macros
00291
00292   @endverbatim
00293   ******************************************************************************
00294   * @attention
00295   *
00296   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00297   * All rights reserved.</center></h2>
00298   *
00299   * This software component is licensed by ST under BSD 3-Clause license,
00300   * the "License"; You may not use this file except in compliance with the
00301   * License. You may obtain a copy of the License at:
00302   *                        opensource.org/licenses/BSD-3-Clause
00303   *
00304   ******************************************************************************
00305   */
00306
00307 /* Includes ------------------------------------------------------------------*/
00308 #include "stm32h7xx_hal.h"
00309
00310 /** @addtogroup STM32H7xx_HAL_Driver
00311   * @{
00312   */
00313
00314 /** @defgroup I2C I2C
00315   * @brief I2C HAL module driver
00316   * @{
00317   */
00318
00319 #ifdef HAL_I2C_MODULE_ENABLED
00320
00321 /* Private typedef -----------------------------------------------------------*/
00322 /* Private define ------------------------------------------------------------*/
00323
00324 /** @defgroup I2C_Private_Define I2C Private Define
00325   * @{
00326   */
00327 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00328 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00329 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00330 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00331 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00332 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00333 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00334 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00335 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00336 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00337
00338 #define MAX_NBYTE_SIZE      255U
00339 #define SlaveAddr_SHIFT     7U
00340 #define SlaveAddr_MSK       0x06U
00341
00342 /* Private define for @ref PreviousState usage */
00343 #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
00344 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00345 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00346 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00347 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00348 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00349 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00350 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00351
00352
00353 /* Private define to centralize the enable/disable of Interrupts */
00354 #define I2C_XFER_TX_IT          (0x00000001U)
00355 #define I2C_XFER_RX_IT          (0x00000002U)
00356 #define I2C_XFER_LISTEN_IT      (0x00000004U)
00357
00358 #define I2C_XFER_ERROR_IT       (0x00000011U)
00359 #define I2C_XFER_CPLT_IT        (0x00000012U)
00360 #define I2C_XFER_RELOAD_IT      (0x00000012U)
00361
00362 /* Private define Sequential Transfer Options default/reset value */
00363 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
00364 /**
00365   * @}
00366   */
00367
00368 /* Private macro -------------------------------------------------------------*/
00369 /* Private variables ---------------------------------------------------------*/
00370 /* Private function prototypes -----------------------------------------------*/
00371
00372 /** @defgroup I2C_Private_Functions I2C Private Functions
00373   * @{
00374   */
00375 /* Private functions to handle DMA transfer */
00376 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00377 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00378 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00379 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00380 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00381 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00382
00383 /* Private functions to handle IT transfer */
00384 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00385 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
00386 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
00387 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00388 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00389 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00390 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00391
00392 /* Private functions to handle IT transfer */
00393 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00394 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00395
00396 /* Private functions for I2C transfer IRQ handler */
00397 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00398 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00399 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00400 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00401
00402 /* Private functions to handle flags during polling transfer */
00403 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00404 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00405 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00406 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00407 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00408
00409 /* Private functions to centralize the enable/disable of Interrupts */
00410 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00411 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00412
00413 /* Private function to flush TXDR register */
00414 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00415
00416 /* Private function to handle  start, restart or stop a transfer */
00417 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00418
00419 /* Private function to Convert Specific options */
00420 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
00421 /**
00422   * @}
00423   */
00424
00425 /* Exported functions --------------------------------------------------------*/
00426
00427 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00428   * @{
00429   */
00430
00431 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00432  *  @brief    Initialization and Configuration functions
00433  *
00434 @verbatim
00435  ===============================================================================
00436               ##### Initialization and de-initialization functions #####
00437  ===============================================================================
00438     [..]  This subsection provides a set of functions allowing to initialize and
00439           deinitialize the I2Cx peripheral:
00440
00441       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00442           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00443
00444       (+) Call the function HAL_I2C_Init() to configure the selected device with
00445           the selected configuration:
00446         (++) Clock Timing
00447         (++) Own Address 1
00448         (++) Addressing mode (Master, Slave)
00449         (++) Dual Addressing mode
00450         (++) Own Address 2
00451         (++) Own Address 2 Mask
00452         (++) General call mode
00453         (++) Nostretch mode
00454
00455       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00456           of the selected I2Cx peripheral.
00457
00458 @endverbatim
00459   * @{
00460   */
00461
00462 /**
00463   * @brief  Initializes the I2C according to the specified parameters
00464   *         in the I2C_InitTypeDef and initialize the associated handle.
00465   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00466   *                the configuration information for the specified I2C.
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00470 {
00471   /* Check the I2C handle allocation */
00472   if (hi2c == NULL)
00473   {
00474     return HAL_ERROR;
00475   }
00476
00477   /* Check the parameters */
00478   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00479   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00480   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00481   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00482   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00483   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00484   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00485   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00486
00487   if (hi2c->State == HAL_I2C_STATE_RESET)
00488   {
00489     /* Allocate lock resource and initialize it */
00490     hi2c->Lock = HAL_UNLOCKED;
00491
00492 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00493     /* Init the I2C Callback settings */
00494     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00495     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00496     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00497     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00498     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00499     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
00500     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
00501     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
00502     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00503     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
00504
00505     if (hi2c->MspInitCallback == NULL)
00506     {
00507       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
00508     }
00509
00510     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00511     hi2c->MspInitCallback(hi2c);
00512 #else
00513     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00514     HAL_I2C_MspInit(hi2c);
00515 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00516   }
00517
00518   hi2c->State = HAL_I2C_STATE_BUSY;
00519
00520   /* Disable the selected I2C peripheral */
00521   __HAL_I2C_DISABLE(hi2c);
00522
00523   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00524   /* Configure I2Cx: Frequency range */
00525   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00526
00527   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00528   /* Disable Own Address1 before set the Own Address1 configuration */
00529   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00530
00531   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00532   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00533   {
00534     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00535   }
00536   else /* I2C_ADDRESSINGMODE_10BIT */
00537   {
00538     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00539   }
00540
00541   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00542   /* Configure I2Cx: Addressing Master mode */
00543   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00544   {
00545     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00546   }
00547   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00548   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00549
00550   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00551   /* Disable Own Address2 before set the Own Address2 configuration */
00552   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00553
00554   /* Configure I2Cx: Dual mode and Own Address2 */
00555   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00556
00557   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00558   /* Configure I2Cx: Generalcall and NoStretch mode */
00559   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00560
00561   /* Enable the selected I2C peripheral */
00562   __HAL_I2C_ENABLE(hi2c);
00563
00564   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00565   hi2c->State = HAL_I2C_STATE_READY;
00566   hi2c->PreviousState = I2C_STATE_NONE;
00567   hi2c->Mode = HAL_I2C_MODE_NONE;
00568
00569   return HAL_OK;
00570 }
00571
00572 /**
00573   * @brief  DeInitialize the I2C peripheral.
00574   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00575   *                the configuration information for the specified I2C.
00576   * @retval HAL status
00577   */
00578 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00579 {
00580   /* Check the I2C handle allocation */
00581   if (hi2c == NULL)
00582   {
00583     return HAL_ERROR;
00584   }
00585
00586   /* Check the parameters */
00587   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00588
00589   hi2c->State = HAL_I2C_STATE_BUSY;
00590
00591   /* Disable the I2C Peripheral Clock */
00592   __HAL_I2C_DISABLE(hi2c);
00593
00594 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00595   if (hi2c->MspDeInitCallback == NULL)
00596   {
00597     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
00598   }
00599
00600   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00601   hi2c->MspDeInitCallback(hi2c);
00602 #else
00603   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00604   HAL_I2C_MspDeInit(hi2c);
00605 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00606
00607   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00608   hi2c->State = HAL_I2C_STATE_RESET;
00609   hi2c->PreviousState = I2C_STATE_NONE;
00610   hi2c->Mode = HAL_I2C_MODE_NONE;
00611
00612   /* Release Lock */
00613   __HAL_UNLOCK(hi2c);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief Initialize the I2C MSP.
00620   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00621   *                the configuration information for the specified I2C.
00622   * @retval None
00623   */
00624 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00625 {
00626   /* Prevent unused argument(s) compilation warning */
00627   UNUSED(hi2c);
00628
00629   /* NOTE : This function should not be modified, when the callback is needed,
00630             the HAL_I2C_MspInit could be implemented in the user file
00631    */
00632 }
00633
00634 /**
00635   * @brief DeInitialize the I2C MSP.
00636   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00637   *                the configuration information for the specified I2C.
00638   * @retval None
00639   */
00640 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00641 {
00642   /* Prevent unused argument(s) compilation warning */
00643   UNUSED(hi2c);
00644
00645   /* NOTE : This function should not be modified, when the callback is needed,
00646             the HAL_I2C_MspDeInit could be implemented in the user file
00647    */
00648 }
00649
00650 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00651 /**
00652   * @brief  Register a User I2C Callback
00653   *         To be used instead of the weak predefined callback
00654   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00655   *                the configuration information for the specified I2C.
00656   * @param  CallbackID ID of the callback to be registered
00657   *         This parameter can be one of the following values:
00658   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00659   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00660   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00661   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00662   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00663   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00664   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00665   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00666   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00667   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00668   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00669   * @param  pCallback pointer to the Callback function
00670   * @retval HAL status
00671   */
00672 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
00673 {
00674   HAL_StatusTypeDef status = HAL_OK;
00675
00676   if (pCallback == NULL)
00677   {
00678     /* Update the error code */
00679     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00680
00681     return HAL_ERROR;
00682   }
00683   /* Process locked */
00684   __HAL_LOCK(hi2c);
00685
00686   if (HAL_I2C_STATE_READY == hi2c->State)
00687   {
00688     switch (CallbackID)
00689     {
00690       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00691         hi2c->MasterTxCpltCallback = pCallback;
00692         break;
00693
00694       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00695         hi2c->MasterRxCpltCallback = pCallback;
00696         break;
00697
00698       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00699         hi2c->SlaveTxCpltCallback = pCallback;
00700         break;
00701
00702       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00703         hi2c->SlaveRxCpltCallback = pCallback;
00704         break;
00705
00706       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00707         hi2c->ListenCpltCallback = pCallback;
00708         break;
00709
00710       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00711         hi2c->MemTxCpltCallback = pCallback;
00712         break;
00713
00714       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00715         hi2c->MemRxCpltCallback = pCallback;
00716         break;
00717
00718       case HAL_I2C_ERROR_CB_ID :
00719         hi2c->ErrorCallback = pCallback;
00720         break;
00721
00722       case HAL_I2C_ABORT_CB_ID :
00723         hi2c->AbortCpltCallback = pCallback;
00724         break;
00725
00726       case HAL_I2C_MSPINIT_CB_ID :
00727         hi2c->MspInitCallback = pCallback;
00728         break;
00729
00730       case HAL_I2C_MSPDEINIT_CB_ID :
00731         hi2c->MspDeInitCallback = pCallback;
00732         break;
00733
00734       default :
00735         /* Update the error code */
00736         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00737
00738         /* Return error status */
00739         status =  HAL_ERROR;
00740         break;
00741     }
00742   }
00743   else if (HAL_I2C_STATE_RESET == hi2c->State)
00744   {
00745     switch (CallbackID)
00746     {
00747       case HAL_I2C_MSPINIT_CB_ID :
00748         hi2c->MspInitCallback = pCallback;
00749         break;
00750
00751       case HAL_I2C_MSPDEINIT_CB_ID :
00752         hi2c->MspDeInitCallback = pCallback;
00753         break;
00754
00755       default :
00756         /* Update the error code */
00757         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00758
00759         /* Return error status */
00760         status =  HAL_ERROR;
00761         break;
00762     }
00763   }
00764   else
00765   {
00766     /* Update the error code */
00767     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00768
00769     /* Return error status */
00770     status =  HAL_ERROR;
00771   }
00772
00773   /* Release Lock */
00774   __HAL_UNLOCK(hi2c);
00775   return status;
00776 }
00777
00778 /**
00779   * @brief  Unregister an I2C Callback
00780   *         I2C callback is redirected to the weak predefined callback
00781   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00782   *                the configuration information for the specified I2C.
00783   * @param  CallbackID ID of the callback to be unregistered
00784   *         This parameter can be one of the following values:
00785   *         This parameter can be one of the following values:
00786   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00787   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00788   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00789   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00790   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00791   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00792   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00793   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00794   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00795   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00796   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
00800 {
00801   HAL_StatusTypeDef status = HAL_OK;
00802
00803   /* Process locked */
00804   __HAL_LOCK(hi2c);
00805
00806   if (HAL_I2C_STATE_READY == hi2c->State)
00807   {
00808     switch (CallbackID)
00809     {
00810       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00811         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00812         break;
00813
00814       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00815         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00816         break;
00817
00818       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00819         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00820         break;
00821
00822       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00823         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00824         break;
00825
00826       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00827         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00828         break;
00829
00830       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00831         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
00832         break;
00833
00834       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00835         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
00836         break;
00837
00838       case HAL_I2C_ERROR_CB_ID :
00839         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
00840         break;
00841
00842       case HAL_I2C_ABORT_CB_ID :
00843         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00844         break;
00845
00846       case HAL_I2C_MSPINIT_CB_ID :
00847         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00848         break;
00849
00850       case HAL_I2C_MSPDEINIT_CB_ID :
00851         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00852         break;
00853
00854       default :
00855         /* Update the error code */
00856         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00857
00858         /* Return error status */
00859         status =  HAL_ERROR;
00860         break;
00861     }
00862   }
00863   else if (HAL_I2C_STATE_RESET == hi2c->State)
00864   {
00865     switch (CallbackID)
00866     {
00867       case HAL_I2C_MSPINIT_CB_ID :
00868         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00869         break;
00870
00871       case HAL_I2C_MSPDEINIT_CB_ID :
00872         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00873         break;
00874
00875       default :
00876         /* Update the error code */
00877         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00878
00879         /* Return error status */
00880         status =  HAL_ERROR;
00881         break;
00882     }
00883   }
00884   else
00885   {
00886     /* Update the error code */
00887     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00888
00889     /* Return error status */
00890     status =  HAL_ERROR;
00891   }
00892
00893   /* Release Lock */
00894   __HAL_UNLOCK(hi2c);
00895   return status;
00896 }
00897
00898 /**
00899   * @brief  Register the Slave Address Match I2C Callback
00900   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
00901   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00902   *                the configuration information for the specified I2C.
00903   * @param  pCallback pointer to the Address Match Callback function
00904   * @retval HAL status
00905   */
00906 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
00907 {
00908   HAL_StatusTypeDef status = HAL_OK;
00909
00910   if (pCallback == NULL)
00911   {
00912     /* Update the error code */
00913     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00914
00915     return HAL_ERROR;
00916   }
00917   /* Process locked */
00918   __HAL_LOCK(hi2c);
00919
00920   if (HAL_I2C_STATE_READY == hi2c->State)
00921   {
00922     hi2c->AddrCallback = pCallback;
00923   }
00924   else
00925   {
00926     /* Update the error code */
00927     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00928
00929     /* Return error status */
00930     status =  HAL_ERROR;
00931   }
00932
00933   /* Release Lock */
00934   __HAL_UNLOCK(hi2c);
00935   return status;
00936 }
00937
00938 /**
00939   * @brief  UnRegister the Slave Address Match I2C Callback
00940   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
00941   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00942   *                the configuration information for the specified I2C.
00943   * @retval HAL status
00944   */
00945 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
00946 {
00947   HAL_StatusTypeDef status = HAL_OK;
00948
00949   /* Process locked */
00950   __HAL_LOCK(hi2c);
00951
00952   if (HAL_I2C_STATE_READY == hi2c->State)
00953   {
00954     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
00955   }
00956   else
00957   {
00958     /* Update the error code */
00959     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00960
00961     /* Return error status */
00962     status =  HAL_ERROR;
00963   }
00964
00965   /* Release Lock */
00966   __HAL_UNLOCK(hi2c);
00967   return status;
00968 }
00969
00970 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00971
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00977  *  @brief   Data transfers functions
00978  *
00979 @verbatim
00980  ===============================================================================
00981                       ##### IO operation functions #####
00982  ===============================================================================
00983     [..]
00984     This subsection provides a set of functions allowing to manage the I2C data
00985     transfers.
00986
00987     (#) There are two modes of transfer:
00988        (++) Blocking mode : The communication is performed in the polling mode.
00989             The status of all data processing is returned by the same function
00990             after finishing transfer.
00991        (++) No-Blocking mode : The communication is performed using Interrupts
00992             or DMA. These functions return the status of the transfer startup.
00993             The end of the data processing will be indicated through the
00994             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00995             using DMA mode.
00996
00997     (#) Blocking mode functions are :
00998         (++) HAL_I2C_Master_Transmit()
00999         (++) HAL_I2C_Master_Receive()
01000         (++) HAL_I2C_Slave_Transmit()
01001         (++) HAL_I2C_Slave_Receive()
01002         (++) HAL_I2C_Mem_Write()
01003         (++) HAL_I2C_Mem_Read()
01004         (++) HAL_I2C_IsDeviceReady()
01005
01006     (#) No-Blocking mode functions with Interrupt are :
01007         (++) HAL_I2C_Master_Transmit_IT()
01008         (++) HAL_I2C_Master_Receive_IT()
01009         (++) HAL_I2C_Slave_Transmit_IT()
01010         (++) HAL_I2C_Slave_Receive_IT()
01011         (++) HAL_I2C_Mem_Write_IT()
01012         (++) HAL_I2C_Mem_Read_IT()
01013         (++) HAL_I2C_Master_Seq_Transmit_IT()
01014         (++) HAL_I2C_Master_Seq_Receive_IT()
01015         (++) HAL_I2C_Slave_Seq_Transmit_IT()
01016         (++) HAL_I2C_Slave_Seq_Receive_IT()
01017         (++) HAL_I2C_EnableListen_IT()
01018         (++) HAL_I2C_DisableListen_IT()
01019         (++) HAL_I2C_Master_Abort_IT()
01020
01021     (#) No-Blocking mode functions with DMA are :
01022         (++) HAL_I2C_Master_Transmit_DMA()
01023         (++) HAL_I2C_Master_Receive_DMA()
01024         (++) HAL_I2C_Slave_Transmit_DMA()
01025         (++) HAL_I2C_Slave_Receive_DMA()
01026         (++) HAL_I2C_Mem_Write_DMA()
01027         (++) HAL_I2C_Mem_Read_DMA()
01028         (++) HAL_I2C_Master_Seq_Transmit_DMA()
01029         (++) HAL_I2C_Master_Seq_Receive_DMA()
01030         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
01031         (++) HAL_I2C_Slave_Seq_Receive_DMA()
01032
01033     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
01034         (++) HAL_I2C_MasterTxCpltCallback()
01035         (++) HAL_I2C_MasterRxCpltCallback()
01036         (++) HAL_I2C_SlaveTxCpltCallback()
01037         (++) HAL_I2C_SlaveRxCpltCallback()
01038         (++) HAL_I2C_MemTxCpltCallback()
01039         (++) HAL_I2C_MemRxCpltCallback()
01040         (++) HAL_I2C_AddrCallback()
01041         (++) HAL_I2C_ListenCpltCallback()
01042         (++) HAL_I2C_ErrorCallback()
01043         (++) HAL_I2C_AbortCpltCallback()
01044
01045 @endverbatim
01046   * @{
01047   */
01048
01049 /**
01050   * @brief  Transmits in master mode an amount of data in blocking mode.
01051   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01052   *                the configuration information for the specified I2C.
01053   * @param  DevAddress Target device address: The device 7 bits address value
01054   *         in datasheet must be shifted to the left before calling the interface
01055   * @param  pData Pointer to data buffer
01056   * @param  Size Amount of data to be sent
01057   * @param  Timeout Timeout duration
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01061 {
01062   uint32_t tickstart;
01063
01064   if (hi2c->State == HAL_I2C_STATE_READY)
01065   {
01066     /* Process Locked */
01067     __HAL_LOCK(hi2c);
01068
01069     /* Init tickstart for timeout management*/
01070     tickstart = HAL_GetTick();
01071
01072     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01073     {
01074       return HAL_ERROR;
01075     }
01076
01077     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01078     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01079     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01080
01081     /* Prepare transfer parameters */
01082     hi2c->pBuffPtr  = pData;
01083     hi2c->XferCount = Size;
01084     hi2c->XferISR   = NULL;
01085
01086     /* Send Slave Address */
01087     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01088     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01089     {
01090       hi2c->XferSize = MAX_NBYTE_SIZE;
01091       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
01092     }
01093     else
01094     {
01095       hi2c->XferSize = hi2c->XferCount;
01096       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01097     }
01098
01099     while (hi2c->XferCount > 0U)
01100     {
01101       /* Wait until TXIS flag is set */
01102       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01103       {
01104         return HAL_ERROR;
01105       }
01106       /* Write data to TXDR */
01107       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01108
01109       /* Increment Buffer pointer */
01110       hi2c->pBuffPtr++;
01111
01112       hi2c->XferCount--;
01113       hi2c->XferSize--;
01114
01115       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01116       {
01117         /* Wait until TCR flag is set */
01118         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01119         {
01120           return HAL_ERROR;
01121         }
01122
01123         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01124         {
01125           hi2c->XferSize = MAX_NBYTE_SIZE;
01126           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01127         }
01128         else
01129         {
01130           hi2c->XferSize = hi2c->XferCount;
01131           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01132         }
01133       }
01134     }
01135
01136     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01137     /* Wait until STOPF flag is set */
01138     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01139     {
01140       return HAL_ERROR;
01141     }
01142
01143     /* Clear STOP Flag */
01144     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01145
01146     /* Clear Configuration Register 2 */
01147     I2C_RESET_CR2(hi2c);
01148
01149     hi2c->State = HAL_I2C_STATE_READY;
01150     hi2c->Mode  = HAL_I2C_MODE_NONE;
01151
01152     /* Process Unlocked */
01153     __HAL_UNLOCK(hi2c);
01154
01155     return HAL_OK;
01156   }
01157   else
01158   {
01159     return HAL_BUSY;
01160   }
01161 }
01162
01163 /**
01164   * @brief  Receives in master mode an amount of data in blocking mode.
01165   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01166   *                the configuration information for the specified I2C.
01167   * @param  DevAddress Target device address: The device 7 bits address value
01168   *         in datasheet must be shifted to the left before calling the interface
01169   * @param  pData Pointer to data buffer
01170   * @param  Size Amount of data to be sent
01171   * @param  Timeout Timeout duration
01172   * @retval HAL status
01173   */
01174 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01175 {
01176   uint32_t tickstart;
01177
01178   if (hi2c->State == HAL_I2C_STATE_READY)
01179   {
01180     /* Process Locked */
01181     __HAL_LOCK(hi2c);
01182
01183     /* Init tickstart for timeout management*/
01184     tickstart = HAL_GetTick();
01185
01186     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01187     {
01188       return HAL_ERROR;
01189     }
01190
01191     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01192     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01193     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01194
01195     /* Prepare transfer parameters */
01196     hi2c->pBuffPtr  = pData;
01197     hi2c->XferCount = Size;
01198     hi2c->XferISR   = NULL;
01199
01200     /* Send Slave Address */
01201     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01202     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01203     {
01204       hi2c->XferSize = MAX_NBYTE_SIZE;
01205       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01206     }
01207     else
01208     {
01209       hi2c->XferSize = hi2c->XferCount;
01210       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01211     }
01212
01213     while (hi2c->XferCount > 0U)
01214     {
01215       /* Wait until RXNE flag is set */
01216       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01217       {
01218         return HAL_ERROR;
01219       }
01220
01221       /* Read data from RXDR */
01222       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01223
01224       /* Increment Buffer pointer */
01225       hi2c->pBuffPtr++;
01226
01227       hi2c->XferSize--;
01228       hi2c->XferCount--;
01229
01230       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01231       {
01232         /* Wait until TCR flag is set */
01233         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01234         {
01235           return HAL_ERROR;
01236         }
01237
01238         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01239         {
01240           hi2c->XferSize = MAX_NBYTE_SIZE;
01241           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01242         }
01243         else
01244         {
01245           hi2c->XferSize = hi2c->XferCount;
01246           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01247         }
01248       }
01249     }
01250
01251     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01252     /* Wait until STOPF flag is set */
01253     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01254     {
01255       return HAL_ERROR;
01256     }
01257
01258     /* Clear STOP Flag */
01259     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01260
01261     /* Clear Configuration Register 2 */
01262     I2C_RESET_CR2(hi2c);
01263
01264     hi2c->State = HAL_I2C_STATE_READY;
01265     hi2c->Mode  = HAL_I2C_MODE_NONE;
01266
01267     /* Process Unlocked */
01268     __HAL_UNLOCK(hi2c);
01269
01270     return HAL_OK;
01271   }
01272   else
01273   {
01274     return HAL_BUSY;
01275   }
01276 }
01277
01278 /**
01279   * @brief  Transmits in slave mode an amount of data in blocking mode.
01280   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01281   *                the configuration information for the specified I2C.
01282   * @param  pData Pointer to data buffer
01283   * @param  Size Amount of data to be sent
01284   * @param  Timeout Timeout duration
01285   * @retval HAL status
01286   */
01287 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01288 {
01289   uint32_t tickstart;
01290
01291   if (hi2c->State == HAL_I2C_STATE_READY)
01292   {
01293     if ((pData == NULL) || (Size == 0U))
01294     {
01295       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01296       return  HAL_ERROR;
01297     }
01298     /* Process Locked */
01299     __HAL_LOCK(hi2c);
01300
01301     /* Init tickstart for timeout management*/
01302     tickstart = HAL_GetTick();
01303
01304     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01305     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01306     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01307
01308     /* Prepare transfer parameters */
01309     hi2c->pBuffPtr  = pData;
01310     hi2c->XferCount = Size;
01311     hi2c->XferISR   = NULL;
01312
01313     /* Enable Address Acknowledge */
01314     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01315
01316     /* Wait until ADDR flag is set */
01317     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01318     {
01319       /* Disable Address Acknowledge */
01320       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01321       return HAL_ERROR;
01322     }
01323
01324     /* Clear ADDR flag */
01325     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01326
01327     /* If 10bit addressing mode is selected */
01328     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01329     {
01330       /* Wait until ADDR flag is set */
01331       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01332       {
01333         /* Disable Address Acknowledge */
01334         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01335         return HAL_ERROR;
01336       }
01337
01338       /* Clear ADDR flag */
01339       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01340     }
01341
01342     /* Wait until DIR flag is set Transmitter mode */
01343     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
01344     {
01345       /* Disable Address Acknowledge */
01346       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01347       return HAL_ERROR;
01348     }
01349
01350     while (hi2c->XferCount > 0U)
01351     {
01352       /* Wait until TXIS flag is set */
01353       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01354       {
01355         /* Disable Address Acknowledge */
01356         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01357         return HAL_ERROR;
01358       }
01359
01360       /* Write data to TXDR */
01361       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01362
01363       /* Increment Buffer pointer */
01364       hi2c->pBuffPtr++;
01365
01366       hi2c->XferCount--;
01367     }
01368
01369     /* Wait until STOP flag is set */
01370     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01371     {
01372       /* Disable Address Acknowledge */
01373       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01374
01375       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01376       {
01377         /* Normal use case for Transmitter mode */
01378         /* A NACK is generated to confirm the end of transfer */
01379         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01380       }
01381       else
01382       {
01383         return HAL_ERROR;
01384       }
01385     }
01386
01387     /* Clear STOP flag */
01388     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01389
01390     /* Wait until BUSY flag is reset */
01391     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01392     {
01393       /* Disable Address Acknowledge */
01394       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01395       return HAL_ERROR;
01396     }
01397
01398     /* Disable Address Acknowledge */
01399     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01400
01401     hi2c->State = HAL_I2C_STATE_READY;
01402     hi2c->Mode  = HAL_I2C_MODE_NONE;
01403
01404     /* Process Unlocked */
01405     __HAL_UNLOCK(hi2c);
01406
01407     return HAL_OK;
01408   }
01409   else
01410   {
01411     return HAL_BUSY;
01412   }
01413 }
01414
01415 /**
01416   * @brief  Receive in slave mode an amount of data in blocking mode
01417   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01418   *                the configuration information for the specified I2C.
01419   * @param  pData Pointer to data buffer
01420   * @param  Size Amount of data to be sent
01421   * @param  Timeout Timeout duration
01422   * @retval HAL status
01423   */
01424 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01425 {
01426   uint32_t tickstart;
01427
01428   if (hi2c->State == HAL_I2C_STATE_READY)
01429   {
01430     if ((pData == NULL) || (Size == 0U))
01431     {
01432       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01433       return  HAL_ERROR;
01434     }
01435     /* Process Locked */
01436     __HAL_LOCK(hi2c);
01437
01438     /* Init tickstart for timeout management*/
01439     tickstart = HAL_GetTick();
01440
01441     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01442     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01443     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01444
01445     /* Prepare transfer parameters */
01446     hi2c->pBuffPtr  = pData;
01447     hi2c->XferCount = Size;
01448     hi2c->XferISR   = NULL;
01449
01450     /* Enable Address Acknowledge */
01451     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01452
01453     /* Wait until ADDR flag is set */
01454     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01455     {
01456       /* Disable Address Acknowledge */
01457       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01458       return HAL_ERROR;
01459     }
01460
01461     /* Clear ADDR flag */
01462     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01463
01464     /* Wait until DIR flag is reset Receiver mode */
01465     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01466     {
01467       /* Disable Address Acknowledge */
01468       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01469       return HAL_ERROR;
01470     }
01471
01472     while (hi2c->XferCount > 0U)
01473     {
01474       /* Wait until RXNE flag is set */
01475       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01476       {
01477         /* Disable Address Acknowledge */
01478         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01479
01480         /* Store Last receive data if any */
01481         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01482         {
01483           /* Read data from RXDR */
01484           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01485
01486           /* Increment Buffer pointer */
01487           hi2c->pBuffPtr++;
01488
01489           hi2c->XferCount--;
01490         }
01491
01492         return HAL_ERROR;
01493       }
01494
01495       /* Read data from RXDR */
01496       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01497
01498       /* Increment Buffer pointer */
01499       hi2c->pBuffPtr++;
01500
01501       hi2c->XferCount--;
01502     }
01503
01504     /* Wait until STOP flag is set */
01505     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01506     {
01507       /* Disable Address Acknowledge */
01508       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01509       return HAL_ERROR;
01510     }
01511
01512     /* Clear STOP flag */
01513     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01514
01515     /* Wait until BUSY flag is reset */
01516     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01517     {
01518       /* Disable Address Acknowledge */
01519       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01520       return HAL_ERROR;
01521     }
01522
01523     /* Disable Address Acknowledge */
01524     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01525
01526     hi2c->State = HAL_I2C_STATE_READY;
01527     hi2c->Mode  = HAL_I2C_MODE_NONE;
01528
01529     /* Process Unlocked */
01530     __HAL_UNLOCK(hi2c);
01531
01532     return HAL_OK;
01533   }
01534   else
01535   {
01536     return HAL_BUSY;
01537   }
01538 }
01539
01540 /**
01541   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01542   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01543   *                the configuration information for the specified I2C.
01544   * @param  DevAddress Target device address: The device 7 bits address value
01545   *         in datasheet must be shifted to the left before calling the interface
01546   * @param  pData Pointer to data buffer
01547   * @param  Size Amount of data to be sent
01548   * @retval HAL status
01549   */
01550 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01551 {
01552   uint32_t xfermode;
01553
01554   if (hi2c->State == HAL_I2C_STATE_READY)
01555   {
01556     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01557     {
01558       return HAL_BUSY;
01559     }
01560
01561     /* Process Locked */
01562     __HAL_LOCK(hi2c);
01563
01564     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01565     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01566     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01567
01568     /* Prepare transfer parameters */
01569     hi2c->pBuffPtr    = pData;
01570     hi2c->XferCount   = Size;
01571     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01572     hi2c->XferISR     = I2C_Master_ISR_IT;
01573
01574     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01575     {
01576       hi2c->XferSize = MAX_NBYTE_SIZE;
01577       xfermode = I2C_RELOAD_MODE;
01578     }
01579     else
01580     {
01581       hi2c->XferSize = hi2c->XferCount;
01582       xfermode = I2C_AUTOEND_MODE;
01583     }
01584
01585     /* Send Slave Address */
01586     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01587     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01588
01589     /* Process Unlocked */
01590     __HAL_UNLOCK(hi2c);
01591
01592     /* Note : The I2C interrupts must be enabled after unlocking current process
01593               to avoid the risk of I2C interrupt handle execution before current
01594               process unlock */
01595
01596     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01597     /* possible to enable all of these */
01598     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01599     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01600
01601     return HAL_OK;
01602   }
01603   else
01604   {
01605     return HAL_BUSY;
01606   }
01607 }
01608
01609 /**
01610   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01611   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01612   *                the configuration information for the specified I2C.
01613   * @param  DevAddress Target device address: The device 7 bits address value
01614   *         in datasheet must be shifted to the left before calling the interface
01615   * @param  pData Pointer to data buffer
01616   * @param  Size Amount of data to be sent
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01620 {
01621   uint32_t xfermode;
01622
01623   if (hi2c->State == HAL_I2C_STATE_READY)
01624   {
01625     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01626     {
01627       return HAL_BUSY;
01628     }
01629
01630     /* Process Locked */
01631     __HAL_LOCK(hi2c);
01632
01633     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01634     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01635     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01636
01637     /* Prepare transfer parameters */
01638     hi2c->pBuffPtr    = pData;
01639     hi2c->XferCount   = Size;
01640     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01641     hi2c->XferISR     = I2C_Master_ISR_IT;
01642
01643     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01644     {
01645       hi2c->XferSize = MAX_NBYTE_SIZE;
01646       xfermode = I2C_RELOAD_MODE;
01647     }
01648     else
01649     {
01650       hi2c->XferSize = hi2c->XferCount;
01651       xfermode = I2C_AUTOEND_MODE;
01652     }
01653
01654     /* Send Slave Address */
01655     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01656     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01657
01658     /* Process Unlocked */
01659     __HAL_UNLOCK(hi2c);
01660
01661     /* Note : The I2C interrupts must be enabled after unlocking current process
01662               to avoid the risk of I2C interrupt handle execution before current
01663               process unlock */
01664
01665     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01666     /* possible to enable all of these */
01667     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01668     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01669
01670     return HAL_OK;
01671   }
01672   else
01673   {
01674     return HAL_BUSY;
01675   }
01676 }
01677
01678 /**
01679   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01680   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01681   *                the configuration information for the specified I2C.
01682   * @param  pData Pointer to data buffer
01683   * @param  Size Amount of data to be sent
01684   * @retval HAL status
01685   */
01686 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01687 {
01688   if (hi2c->State == HAL_I2C_STATE_READY)
01689   {
01690     /* Process Locked */
01691     __HAL_LOCK(hi2c);
01692
01693     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01694     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01695     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01696
01697     /* Enable Address Acknowledge */
01698     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01699
01700     /* Prepare transfer parameters */
01701     hi2c->pBuffPtr    = pData;
01702     hi2c->XferCount   = Size;
01703     hi2c->XferSize    = hi2c->XferCount;
01704     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01705     hi2c->XferISR     = I2C_Slave_ISR_IT;
01706
01707     /* Process Unlocked */
01708     __HAL_UNLOCK(hi2c);
01709
01710     /* Note : The I2C interrupts must be enabled after unlocking current process
01711               to avoid the risk of I2C interrupt handle execution before current
01712               process unlock */
01713
01714     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01715     /* possible to enable all of these */
01716     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01717     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01718
01719     return HAL_OK;
01720   }
01721   else
01722   {
01723     return HAL_BUSY;
01724   }
01725 }
01726
01727 /**
01728   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01729   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01730   *                the configuration information for the specified I2C.
01731   * @param  pData Pointer to data buffer
01732   * @param  Size Amount of data to be sent
01733   * @retval HAL status
01734   */
01735 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01736 {
01737   if (hi2c->State == HAL_I2C_STATE_READY)
01738   {
01739     /* Process Locked */
01740     __HAL_LOCK(hi2c);
01741
01742     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01743     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01744     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01745
01746     /* Enable Address Acknowledge */
01747     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01748
01749     /* Prepare transfer parameters */
01750     hi2c->pBuffPtr    = pData;
01751     hi2c->XferCount   = Size;
01752     hi2c->XferSize    = hi2c->XferCount;
01753     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01754     hi2c->XferISR     = I2C_Slave_ISR_IT;
01755
01756     /* Process Unlocked */
01757     __HAL_UNLOCK(hi2c);
01758
01759     /* Note : The I2C interrupts must be enabled after unlocking current process
01760               to avoid the risk of I2C interrupt handle execution before current
01761               process unlock */
01762
01763     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01764     /* possible to enable all of these */
01765     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01766     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01767
01768     return HAL_OK;
01769   }
01770   else
01771   {
01772     return HAL_BUSY;
01773   }
01774 }
01775
01776 /**
01777   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01778   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01779   *                the configuration information for the specified I2C.
01780   * @param  DevAddress Target device address: The device 7 bits address value
01781   *         in datasheet must be shifted to the left before calling the interface
01782   * @param  pData Pointer to data buffer
01783   * @param  Size Amount of data to be sent
01784   * @retval HAL status
01785   */
01786 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01787 {
01788   uint32_t xfermode;
01789   HAL_StatusTypeDef dmaxferstatus;
01790
01791   if (hi2c->State == HAL_I2C_STATE_READY)
01792   {
01793     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01794     {
01795       return HAL_BUSY;
01796     }
01797
01798     /* Process Locked */
01799     __HAL_LOCK(hi2c);
01800
01801     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01802     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01803     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01804
01805     /* Prepare transfer parameters */
01806     hi2c->pBuffPtr    = pData;
01807     hi2c->XferCount   = Size;
01808     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01809     hi2c->XferISR     = I2C_Master_ISR_DMA;
01810
01811     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01812     {
01813       hi2c->XferSize = MAX_NBYTE_SIZE;
01814       xfermode = I2C_RELOAD_MODE;
01815     }
01816     else
01817     {
01818       hi2c->XferSize = hi2c->XferCount;
01819       xfermode = I2C_AUTOEND_MODE;
01820     }
01821
01822     if (hi2c->XferSize > 0U)
01823     {
01824       if (hi2c->hdmatx != NULL)
01825       {
01826         /* Set the I2C DMA transfer complete callback */
01827         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01828
01829         /* Set the DMA error callback */
01830         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01831
01832         /* Set the unused DMA callbacks to NULL */
01833         hi2c->hdmatx->XferHalfCpltCallback = NULL;
01834         hi2c->hdmatx->XferAbortCallback = NULL;
01835
01836         /* Enable the DMA stream or channel depends on Instance */
01837         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01838       }
01839       else
01840       {
01841         /* Update I2C state */
01842         hi2c->State     = HAL_I2C_STATE_READY;
01843         hi2c->Mode      = HAL_I2C_MODE_NONE;
01844
01845         /* Update I2C error code */
01846         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
01847
01848         /* Process Unlocked */
01849         __HAL_UNLOCK(hi2c);
01850
01851         return HAL_ERROR;
01852       }
01853
01854       if (dmaxferstatus == HAL_OK)
01855       {
01856         /* Send Slave Address */
01857         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01858         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01859
01860         /* Update XferCount value */
01861         hi2c->XferCount -= hi2c->XferSize;
01862
01863         /* Process Unlocked */
01864         __HAL_UNLOCK(hi2c);
01865
01866         /* Note : The I2C interrupts must be enabled after unlocking current process
01867                   to avoid the risk of I2C interrupt handle execution before current
01868                   process unlock */
01869         /* Enable ERR and NACK interrupts */
01870         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01871
01872         /* Enable DMA Request */
01873         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01874       }
01875       else
01876       {
01877         /* Update I2C state */
01878         hi2c->State     = HAL_I2C_STATE_READY;
01879         hi2c->Mode      = HAL_I2C_MODE_NONE;
01880
01881         /* Update I2C error code */
01882         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
01883
01884         /* Process Unlocked */
01885         __HAL_UNLOCK(hi2c);
01886
01887         return HAL_ERROR;
01888       }
01889     }
01890     else
01891     {
01892       /* Update Transfer ISR function pointer */
01893       hi2c->XferISR = I2C_Master_ISR_IT;
01894
01895       /* Send Slave Address */
01896       /* Set NBYTES to write and generate START condition */
01897       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01898
01899       /* Process Unlocked */
01900       __HAL_UNLOCK(hi2c);
01901
01902       /* Note : The I2C interrupts must be enabled after unlocking current process
01903                 to avoid the risk of I2C interrupt handle execution before current
01904                 process unlock */
01905       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01906       /* possible to enable all of these */
01907       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01908       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01909     }
01910
01911     return HAL_OK;
01912   }
01913   else
01914   {
01915     return HAL_BUSY;
01916   }
01917 }
01918
01919 /**
01920   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01921   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01922   *                the configuration information for the specified I2C.
01923   * @param  DevAddress Target device address: The device 7 bits address value
01924   *         in datasheet must be shifted to the left before calling the interface
01925   * @param  pData Pointer to data buffer
01926   * @param  Size Amount of data to be sent
01927   * @retval HAL status
01928   */
01929 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01930 {
01931   uint32_t xfermode;
01932   HAL_StatusTypeDef dmaxferstatus;
01933
01934   if (hi2c->State == HAL_I2C_STATE_READY)
01935   {
01936     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01937     {
01938       return HAL_BUSY;
01939     }
01940
01941     /* Process Locked */
01942     __HAL_LOCK(hi2c);
01943
01944     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01945     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01946     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01947
01948     /* Prepare transfer parameters */
01949     hi2c->pBuffPtr    = pData;
01950     hi2c->XferCount   = Size;
01951     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01952     hi2c->XferISR     = I2C_Master_ISR_DMA;
01953
01954     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01955     {
01956       hi2c->XferSize = MAX_NBYTE_SIZE;
01957       xfermode = I2C_RELOAD_MODE;
01958     }
01959     else
01960     {
01961       hi2c->XferSize = hi2c->XferCount;
01962       xfermode = I2C_AUTOEND_MODE;
01963     }
01964
01965     if (hi2c->XferSize > 0U)
01966     {
01967       if (hi2c->hdmarx != NULL)
01968       {
01969         /* Set the I2C DMA transfer complete callback */
01970         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01971
01972         /* Set the DMA error callback */
01973         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01974
01975         /* Set the unused DMA callbacks to NULL */
01976         hi2c->hdmarx->XferHalfCpltCallback = NULL;
01977         hi2c->hdmarx->XferAbortCallback = NULL;
01978
01979         /* Enable the DMA stream or channel depends on Instance */
01980         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01981       }
01982       else
01983       {
01984         /* Update I2C state */
01985         hi2c->State     = HAL_I2C_STATE_READY;
01986         hi2c->Mode      = HAL_I2C_MODE_NONE;
01987
01988         /* Update I2C error code */
01989         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
01990
01991         /* Process Unlocked */
01992         __HAL_UNLOCK(hi2c);
01993
01994         return HAL_ERROR;
01995       }
01996
01997       if (dmaxferstatus == HAL_OK)
01998       {
01999         /* Send Slave Address */
02000         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02001         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02002
02003         /* Update XferCount value */
02004         hi2c->XferCount -= hi2c->XferSize;
02005
02006         /* Process Unlocked */
02007         __HAL_UNLOCK(hi2c);
02008
02009         /* Note : The I2C interrupts must be enabled after unlocking current process
02010                   to avoid the risk of I2C interrupt handle execution before current
02011                   process unlock */
02012         /* Enable ERR and NACK interrupts */
02013         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02014
02015         /* Enable DMA Request */
02016         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02017       }
02018       else
02019       {
02020         /* Update I2C state */
02021         hi2c->State     = HAL_I2C_STATE_READY;
02022         hi2c->Mode      = HAL_I2C_MODE_NONE;
02023
02024         /* Update I2C error code */
02025         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02026
02027         /* Process Unlocked */
02028         __HAL_UNLOCK(hi2c);
02029
02030         return HAL_ERROR;
02031       }
02032     }
02033     else
02034     {
02035       /* Update Transfer ISR function pointer */
02036       hi2c->XferISR = I2C_Master_ISR_IT;
02037
02038       /* Send Slave Address */
02039       /* Set NBYTES to read and generate START condition */
02040       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02041
02042       /* Process Unlocked */
02043       __HAL_UNLOCK(hi2c);
02044
02045       /* Note : The I2C interrupts must be enabled after unlocking current process
02046                 to avoid the risk of I2C interrupt handle execution before current
02047                 process unlock */
02048       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02049       /* possible to enable all of these */
02050       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02051       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02052     }
02053
02054     return HAL_OK;
02055   }
02056   else
02057   {
02058     return HAL_BUSY;
02059   }
02060 }
02061
02062 /**
02063   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
02064   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02065   *                the configuration information for the specified I2C.
02066   * @param  pData Pointer to data buffer
02067   * @param  Size Amount of data to be sent
02068   * @retval HAL status
02069   */
02070 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02071 {
02072   HAL_StatusTypeDef dmaxferstatus;
02073
02074   if (hi2c->State == HAL_I2C_STATE_READY)
02075   {
02076     if ((pData == NULL) || (Size == 0U))
02077     {
02078       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02079       return  HAL_ERROR;
02080     }
02081     /* Process Locked */
02082     __HAL_LOCK(hi2c);
02083
02084     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02085     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02086     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02087
02088     /* Prepare transfer parameters */
02089     hi2c->pBuffPtr    = pData;
02090     hi2c->XferCount   = Size;
02091     hi2c->XferSize    = hi2c->XferCount;
02092     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02093     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02094
02095     if (hi2c->hdmatx != NULL)
02096     {
02097       /* Set the I2C DMA transfer complete callback */
02098       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
02099
02100       /* Set the DMA error callback */
02101       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02102
02103       /* Set the unused DMA callbacks to NULL */
02104       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02105       hi2c->hdmatx->XferAbortCallback = NULL;
02106
02107       /* Enable the DMA stream or channel depends on Instance */
02108       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02109     }
02110     else
02111     {
02112       /* Update I2C state */
02113       hi2c->State     = HAL_I2C_STATE_LISTEN;
02114       hi2c->Mode      = HAL_I2C_MODE_NONE;
02115
02116       /* Update I2C error code */
02117       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02118
02119       /* Process Unlocked */
02120       __HAL_UNLOCK(hi2c);
02121
02122       return HAL_ERROR;
02123     }
02124
02125     if (dmaxferstatus == HAL_OK)
02126     {
02127       /* Enable Address Acknowledge */
02128       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02129
02130       /* Process Unlocked */
02131       __HAL_UNLOCK(hi2c);
02132
02133       /* Note : The I2C interrupts must be enabled after unlocking current process
02134                 to avoid the risk of I2C interrupt handle execution before current
02135                 process unlock */
02136       /* Enable ERR, STOP, NACK, ADDR interrupts */
02137       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02138
02139       /* Enable DMA Request */
02140       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02141     }
02142     else
02143     {
02144       /* Update I2C state */
02145       hi2c->State     = HAL_I2C_STATE_LISTEN;
02146       hi2c->Mode      = HAL_I2C_MODE_NONE;
02147
02148       /* Update I2C error code */
02149       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02150
02151       /* Process Unlocked */
02152       __HAL_UNLOCK(hi2c);
02153
02154       return HAL_ERROR;
02155     }
02156
02157     return HAL_OK;
02158   }
02159   else
02160   {
02161     return HAL_BUSY;
02162   }
02163 }
02164
02165 /**
02166   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
02167   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02168   *                the configuration information for the specified I2C.
02169   * @param  pData Pointer to data buffer
02170   * @param  Size Amount of data to be sent
02171   * @retval HAL status
02172   */
02173 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02174 {
02175   HAL_StatusTypeDef dmaxferstatus;
02176
02177   if (hi2c->State == HAL_I2C_STATE_READY)
02178   {
02179     if ((pData == NULL) || (Size == 0U))
02180     {
02181       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02182       return  HAL_ERROR;
02183     }
02184     /* Process Locked */
02185     __HAL_LOCK(hi2c);
02186
02187     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02188     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02189     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02190
02191     /* Prepare transfer parameters */
02192     hi2c->pBuffPtr    = pData;
02193     hi2c->XferCount   = Size;
02194     hi2c->XferSize    = hi2c->XferCount;
02195     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02196     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02197
02198     if (hi2c->hdmarx != NULL)
02199     {
02200       /* Set the I2C DMA transfer complete callback */
02201       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
02202
02203       /* Set the DMA error callback */
02204       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02205
02206       /* Set the unused DMA callbacks to NULL */
02207       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02208       hi2c->hdmarx->XferAbortCallback = NULL;
02209
02210       /* Enable the DMA stream or channel depends on Instance */
02211       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02212     }
02213     else
02214     {
02215       /* Update I2C state */
02216       hi2c->State     = HAL_I2C_STATE_LISTEN;
02217       hi2c->Mode      = HAL_I2C_MODE_NONE;
02218
02219       /* Update I2C error code */
02220       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02221
02222       /* Process Unlocked */
02223       __HAL_UNLOCK(hi2c);
02224
02225       return HAL_ERROR;
02226     }
02227
02228     if (dmaxferstatus == HAL_OK)
02229     {
02230       /* Enable Address Acknowledge */
02231       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02232
02233       /* Process Unlocked */
02234       __HAL_UNLOCK(hi2c);
02235
02236       /* Note : The I2C interrupts must be enabled after unlocking current process
02237                 to avoid the risk of I2C interrupt handle execution before current
02238                 process unlock */
02239       /* Enable ERR, STOP, NACK, ADDR interrupts */
02240       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02241
02242       /* Enable DMA Request */
02243       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02244     }
02245     else
02246     {
02247       /* Update I2C state */
02248       hi2c->State     = HAL_I2C_STATE_LISTEN;
02249       hi2c->Mode      = HAL_I2C_MODE_NONE;
02250
02251       /* Update I2C error code */
02252       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02253
02254       /* Process Unlocked */
02255       __HAL_UNLOCK(hi2c);
02256
02257       return HAL_ERROR;
02258     }
02259
02260     return HAL_OK;
02261   }
02262   else
02263   {
02264     return HAL_BUSY;
02265   }
02266 }
02267 /**
02268   * @brief  Write an amount of data in blocking mode to a specific memory address
02269   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02270   *                the configuration information for the specified I2C.
02271   * @param  DevAddress Target device address: The device 7 bits address value
02272   *         in datasheet must be shifted to the left before calling the interface
02273   * @param  MemAddress Internal memory address
02274   * @param  MemAddSize Size of internal memory address
02275   * @param  pData Pointer to data buffer
02276   * @param  Size Amount of data to be sent
02277   * @param  Timeout Timeout duration
02278   * @retval HAL status
02279   */
02280 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02281 {
02282   uint32_t tickstart;
02283
02284   /* Check the parameters */
02285   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02286
02287   if (hi2c->State == HAL_I2C_STATE_READY)
02288   {
02289     if ((pData == NULL) || (Size == 0U))
02290     {
02291       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02292       return  HAL_ERROR;
02293     }
02294
02295     /* Process Locked */
02296     __HAL_LOCK(hi2c);
02297
02298     /* Init tickstart for timeout management*/
02299     tickstart = HAL_GetTick();
02300
02301     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02302     {
02303       return HAL_ERROR;
02304     }
02305
02306     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02307     hi2c->Mode      = HAL_I2C_MODE_MEM;
02308     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02309
02310     /* Prepare transfer parameters */
02311     hi2c->pBuffPtr  = pData;
02312     hi2c->XferCount = Size;
02313     hi2c->XferISR   = NULL;
02314
02315     /* Send Slave Address and Memory Address */
02316     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02317     {
02318       /* Process Unlocked */
02319       __HAL_UNLOCK(hi2c);
02320       return HAL_ERROR;
02321     }
02322
02323     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
02324     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02325     {
02326       hi2c->XferSize = MAX_NBYTE_SIZE;
02327       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02328     }
02329     else
02330     {
02331       hi2c->XferSize = hi2c->XferCount;
02332       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02333     }
02334
02335     do
02336     {
02337       /* Wait until TXIS flag is set */
02338       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02339       {
02340         return HAL_ERROR;
02341       }
02342
02343       /* Write data to TXDR */
02344       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02345
02346       /* Increment Buffer pointer */
02347       hi2c->pBuffPtr++;
02348
02349       hi2c->XferCount--;
02350       hi2c->XferSize--;
02351
02352       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02353       {
02354         /* Wait until TCR flag is set */
02355         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02356         {
02357           return HAL_ERROR;
02358         }
02359
02360         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02361         {
02362           hi2c->XferSize = MAX_NBYTE_SIZE;
02363           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02364         }
02365         else
02366         {
02367           hi2c->XferSize = hi2c->XferCount;
02368           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02369         }
02370       }
02371
02372     }
02373     while (hi2c->XferCount > 0U);
02374
02375     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02376     /* Wait until STOPF flag is reset */
02377     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02378     {
02379       return HAL_ERROR;
02380     }
02381
02382     /* Clear STOP Flag */
02383     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02384
02385     /* Clear Configuration Register 2 */
02386     I2C_RESET_CR2(hi2c);
02387
02388     hi2c->State = HAL_I2C_STATE_READY;
02389     hi2c->Mode  = HAL_I2C_MODE_NONE;
02390
02391     /* Process Unlocked */
02392     __HAL_UNLOCK(hi2c);
02393
02394     return HAL_OK;
02395   }
02396   else
02397   {
02398     return HAL_BUSY;
02399   }
02400 }
02401
02402 /**
02403   * @brief  Read an amount of data in blocking mode from a specific memory address
02404   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02405   *                the configuration information for the specified I2C.
02406   * @param  DevAddress Target device address: The device 7 bits address value
02407   *         in datasheet must be shifted to the left before calling the interface
02408   * @param  MemAddress Internal memory address
02409   * @param  MemAddSize Size of internal memory address
02410   * @param  pData Pointer to data buffer
02411   * @param  Size Amount of data to be sent
02412   * @param  Timeout Timeout duration
02413   * @retval HAL status
02414   */
02415 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02416 {
02417   uint32_t tickstart;
02418
02419   /* Check the parameters */
02420   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02421
02422   if (hi2c->State == HAL_I2C_STATE_READY)
02423   {
02424     if ((pData == NULL) || (Size == 0U))
02425     {
02426       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02427       return  HAL_ERROR;
02428     }
02429
02430     /* Process Locked */
02431     __HAL_LOCK(hi2c);
02432
02433     /* Init tickstart for timeout management*/
02434     tickstart = HAL_GetTick();
02435
02436     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02437     {
02438       return HAL_ERROR;
02439     }
02440
02441     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02442     hi2c->Mode      = HAL_I2C_MODE_MEM;
02443     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02444
02445     /* Prepare transfer parameters */
02446     hi2c->pBuffPtr  = pData;
02447     hi2c->XferCount = Size;
02448     hi2c->XferISR   = NULL;
02449
02450     /* Send Slave Address and Memory Address */
02451     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02452     {
02453       /* Process Unlocked */
02454       __HAL_UNLOCK(hi2c);
02455       return HAL_ERROR;
02456     }
02457
02458     /* Send Slave Address */
02459     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02460     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02461     {
02462       hi2c->XferSize = MAX_NBYTE_SIZE;
02463       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
02464     }
02465     else
02466     {
02467       hi2c->XferSize = hi2c->XferCount;
02468       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02469     }
02470
02471     do
02472     {
02473       /* Wait until RXNE flag is set */
02474       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
02475       {
02476         return HAL_ERROR;
02477       }
02478
02479       /* Read data from RXDR */
02480       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
02481
02482       /* Increment Buffer pointer */
02483       hi2c->pBuffPtr++;
02484
02485       hi2c->XferSize--;
02486       hi2c->XferCount--;
02487
02488       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02489       {
02490         /* Wait until TCR flag is set */
02491         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02492         {
02493           return HAL_ERROR;
02494         }
02495
02496         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02497         {
02498           hi2c->XferSize = MAX_NBYTE_SIZE;
02499           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02500         }
02501         else
02502         {
02503           hi2c->XferSize = hi2c->XferCount;
02504           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02505         }
02506       }
02507     }
02508     while (hi2c->XferCount > 0U);
02509
02510     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02511     /* Wait until STOPF flag is reset */
02512     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02513     {
02514       return HAL_ERROR;
02515     }
02516
02517     /* Clear STOP Flag */
02518     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02519
02520     /* Clear Configuration Register 2 */
02521     I2C_RESET_CR2(hi2c);
02522
02523     hi2c->State = HAL_I2C_STATE_READY;
02524     hi2c->Mode  = HAL_I2C_MODE_NONE;
02525
02526     /* Process Unlocked */
02527     __HAL_UNLOCK(hi2c);
02528
02529     return HAL_OK;
02530   }
02531   else
02532   {
02533     return HAL_BUSY;
02534   }
02535 }
02536 /**
02537   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02538   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02539   *                the configuration information for the specified I2C.
02540   * @param  DevAddress Target device address: The device 7 bits address value
02541   *         in datasheet must be shifted to the left before calling the interface
02542   * @param  MemAddress Internal memory address
02543   * @param  MemAddSize Size of internal memory address
02544   * @param  pData Pointer to data buffer
02545   * @param  Size Amount of data to be sent
02546   * @retval HAL status
02547   */
02548 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02549 {
02550   uint32_t tickstart;
02551   uint32_t xfermode;
02552
02553   /* Check the parameters */
02554   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02555
02556   if (hi2c->State == HAL_I2C_STATE_READY)
02557   {
02558     if ((pData == NULL) || (Size == 0U))
02559     {
02560       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02561       return  HAL_ERROR;
02562     }
02563
02564     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02565     {
02566       return HAL_BUSY;
02567     }
02568
02569     /* Process Locked */
02570     __HAL_LOCK(hi2c);
02571
02572     /* Init tickstart for timeout management*/
02573     tickstart = HAL_GetTick();
02574
02575     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02576     hi2c->Mode        = HAL_I2C_MODE_MEM;
02577     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02578
02579     /* Prepare transfer parameters */
02580     hi2c->pBuffPtr    = pData;
02581     hi2c->XferCount   = Size;
02582     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02583     hi2c->XferISR     = I2C_Master_ISR_IT;
02584
02585     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02586     {
02587       hi2c->XferSize = MAX_NBYTE_SIZE;
02588       xfermode = I2C_RELOAD_MODE;
02589     }
02590     else
02591     {
02592       hi2c->XferSize = hi2c->XferCount;
02593       xfermode = I2C_AUTOEND_MODE;
02594     }
02595
02596     /* Send Slave Address and Memory Address */
02597     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02598     {
02599       /* Process Unlocked */
02600       __HAL_UNLOCK(hi2c);
02601       return HAL_ERROR;
02602     }
02603
02604     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02605     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02606
02607     /* Process Unlocked */
02608     __HAL_UNLOCK(hi2c);
02609
02610     /* Note : The I2C interrupts must be enabled after unlocking current process
02611               to avoid the risk of I2C interrupt handle execution before current
02612               process unlock */
02613
02614     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02615     /* possible to enable all of these */
02616     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02617     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02618
02619     return HAL_OK;
02620   }
02621   else
02622   {
02623     return HAL_BUSY;
02624   }
02625 }
02626
02627 /**
02628   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02629   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02630   *                the configuration information for the specified I2C.
02631   * @param  DevAddress Target device address: The device 7 bits address value
02632   *         in datasheet must be shifted to the left before calling the interface
02633   * @param  MemAddress Internal memory address
02634   * @param  MemAddSize Size of internal memory address
02635   * @param  pData Pointer to data buffer
02636   * @param  Size Amount of data to be sent
02637   * @retval HAL status
02638   */
02639 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02640 {
02641   uint32_t tickstart;
02642   uint32_t xfermode;
02643
02644   /* Check the parameters */
02645   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02646
02647   if (hi2c->State == HAL_I2C_STATE_READY)
02648   {
02649     if ((pData == NULL) || (Size == 0U))
02650     {
02651       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02652       return  HAL_ERROR;
02653     }
02654
02655     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02656     {
02657       return HAL_BUSY;
02658     }
02659
02660     /* Process Locked */
02661     __HAL_LOCK(hi2c);
02662
02663     /* Init tickstart for timeout management*/
02664     tickstart = HAL_GetTick();
02665
02666     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02667     hi2c->Mode        = HAL_I2C_MODE_MEM;
02668     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02669
02670     /* Prepare transfer parameters */
02671     hi2c->pBuffPtr    = pData;
02672     hi2c->XferCount   = Size;
02673     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02674     hi2c->XferISR     = I2C_Master_ISR_IT;
02675
02676     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02677     {
02678       hi2c->XferSize = MAX_NBYTE_SIZE;
02679       xfermode = I2C_RELOAD_MODE;
02680     }
02681     else
02682     {
02683       hi2c->XferSize = hi2c->XferCount;
02684       xfermode = I2C_AUTOEND_MODE;
02685     }
02686
02687     /* Send Slave Address and Memory Address */
02688     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02689     {
02690       /* Process Unlocked */
02691       __HAL_UNLOCK(hi2c);
02692       return HAL_ERROR;
02693     }
02694
02695     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02696     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02697
02698     /* Process Unlocked */
02699     __HAL_UNLOCK(hi2c);
02700
02701     /* Note : The I2C interrupts must be enabled after unlocking current process
02702               to avoid the risk of I2C interrupt handle execution before current
02703               process unlock */
02704
02705     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02706     /* possible to enable all of these */
02707     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02708     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02709
02710     return HAL_OK;
02711   }
02712   else
02713   {
02714     return HAL_BUSY;
02715   }
02716 }
02717 /**
02718   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02719   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02720   *                the configuration information for the specified I2C.
02721   * @param  DevAddress Target device address: The device 7 bits address value
02722   *         in datasheet must be shifted to the left before calling the interface
02723   * @param  MemAddress Internal memory address
02724   * @param  MemAddSize Size of internal memory address
02725   * @param  pData Pointer to data buffer
02726   * @param  Size Amount of data to be sent
02727   * @retval HAL status
02728   */
02729 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02730 {
02731   uint32_t tickstart;
02732   uint32_t xfermode;
02733   HAL_StatusTypeDef dmaxferstatus;
02734
02735   /* Check the parameters */
02736   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02737
02738   if (hi2c->State == HAL_I2C_STATE_READY)
02739   {
02740     if ((pData == NULL) || (Size == 0U))
02741     {
02742       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02743       return  HAL_ERROR;
02744     }
02745
02746     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02747     {
02748       return HAL_BUSY;
02749     }
02750
02751     /* Process Locked */
02752     __HAL_LOCK(hi2c);
02753
02754     /* Init tickstart for timeout management*/
02755     tickstart = HAL_GetTick();
02756
02757     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02758     hi2c->Mode        = HAL_I2C_MODE_MEM;
02759     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02760
02761     /* Prepare transfer parameters */
02762     hi2c->pBuffPtr    = pData;
02763     hi2c->XferCount   = Size;
02764     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02765     hi2c->XferISR     = I2C_Master_ISR_DMA;
02766
02767     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02768     {
02769       hi2c->XferSize = MAX_NBYTE_SIZE;
02770       xfermode = I2C_RELOAD_MODE;
02771     }
02772     else
02773     {
02774       hi2c->XferSize = hi2c->XferCount;
02775       xfermode = I2C_AUTOEND_MODE;
02776     }
02777
02778     /* Send Slave Address and Memory Address */
02779     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02780     {
02781       /* Process Unlocked */
02782       __HAL_UNLOCK(hi2c);
02783       return HAL_ERROR;
02784     }
02785
02786
02787     if (hi2c->hdmatx != NULL)
02788     {
02789       /* Set the I2C DMA transfer complete callback */
02790       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02791
02792       /* Set the DMA error callback */
02793       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02794
02795       /* Set the unused DMA callbacks to NULL */
02796       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02797       hi2c->hdmatx->XferAbortCallback = NULL;
02798
02799       /* Enable the DMA stream or channel depends on Instance */
02800       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02801     }
02802     else
02803     {
02804       /* Update I2C state */
02805       hi2c->State     = HAL_I2C_STATE_READY;
02806       hi2c->Mode      = HAL_I2C_MODE_NONE;
02807
02808       /* Update I2C error code */
02809       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02810
02811       /* Process Unlocked */
02812       __HAL_UNLOCK(hi2c);
02813
02814       return HAL_ERROR;
02815     }
02816
02817     if (dmaxferstatus == HAL_OK)
02818     {
02819       /* Send Slave Address */
02820       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02821       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02822
02823       /* Update XferCount value */
02824       hi2c->XferCount -= hi2c->XferSize;
02825
02826       /* Process Unlocked */
02827       __HAL_UNLOCK(hi2c);
02828
02829       /* Note : The I2C interrupts must be enabled after unlocking current process
02830                 to avoid the risk of I2C interrupt handle execution before current
02831                 process unlock */
02832       /* Enable ERR and NACK interrupts */
02833       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02834
02835       /* Enable DMA Request */
02836       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02837     }
02838     else
02839     {
02840       /* Update I2C state */
02841       hi2c->State     = HAL_I2C_STATE_READY;
02842       hi2c->Mode      = HAL_I2C_MODE_NONE;
02843
02844       /* Update I2C error code */
02845       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02846
02847       /* Process Unlocked */
02848       __HAL_UNLOCK(hi2c);
02849
02850       return HAL_ERROR;
02851     }
02852
02853     return HAL_OK;
02854   }
02855   else
02856   {
02857     return HAL_BUSY;
02858   }
02859 }
02860
02861 /**
02862   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02863   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02864   *                the configuration information for the specified I2C.
02865   * @param  DevAddress Target device address: The device 7 bits address value
02866   *         in datasheet must be shifted to the left before calling the interface
02867   * @param  MemAddress Internal memory address
02868   * @param  MemAddSize Size of internal memory address
02869   * @param  pData Pointer to data buffer
02870   * @param  Size Amount of data to be read
02871   * @retval HAL status
02872   */
02873 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02874 {
02875   uint32_t tickstart;
02876   uint32_t xfermode;
02877   HAL_StatusTypeDef dmaxferstatus;
02878
02879   /* Check the parameters */
02880   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02881
02882   if (hi2c->State == HAL_I2C_STATE_READY)
02883   {
02884     if ((pData == NULL) || (Size == 0U))
02885     {
02886       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02887       return  HAL_ERROR;
02888     }
02889
02890     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02891     {
02892       return HAL_BUSY;
02893     }
02894
02895     /* Process Locked */
02896     __HAL_LOCK(hi2c);
02897
02898     /* Init tickstart for timeout management*/
02899     tickstart = HAL_GetTick();
02900
02901     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02902     hi2c->Mode        = HAL_I2C_MODE_MEM;
02903     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02904
02905     /* Prepare transfer parameters */
02906     hi2c->pBuffPtr    = pData;
02907     hi2c->XferCount   = Size;
02908     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02909     hi2c->XferISR     = I2C_Master_ISR_DMA;
02910
02911     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02912     {
02913       hi2c->XferSize = MAX_NBYTE_SIZE;
02914       xfermode = I2C_RELOAD_MODE;
02915     }
02916     else
02917     {
02918       hi2c->XferSize = hi2c->XferCount;
02919       xfermode = I2C_AUTOEND_MODE;
02920     }
02921
02922     /* Send Slave Address and Memory Address */
02923     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02924     {
02925       /* Process Unlocked */
02926       __HAL_UNLOCK(hi2c);
02927       return HAL_ERROR;
02928     }
02929
02930     if (hi2c->hdmarx != NULL)
02931     {
02932       /* Set the I2C DMA transfer complete callback */
02933       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02934
02935       /* Set the DMA error callback */
02936       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02937
02938       /* Set the unused DMA callbacks to NULL */
02939       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02940       hi2c->hdmarx->XferAbortCallback = NULL;
02941
02942       /* Enable the DMA stream or channel depends on Instance */
02943       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02944     }
02945     else
02946     {
02947       /* Update I2C state */
02948       hi2c->State     = HAL_I2C_STATE_READY;
02949       hi2c->Mode      = HAL_I2C_MODE_NONE;
02950
02951       /* Update I2C error code */
02952       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02953
02954       /* Process Unlocked */
02955       __HAL_UNLOCK(hi2c);
02956
02957       return HAL_ERROR;
02958     }
02959
02960     if (dmaxferstatus == HAL_OK)
02961     {
02962       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02963       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02964
02965       /* Update XferCount value */
02966       hi2c->XferCount -= hi2c->XferSize;
02967
02968       /* Process Unlocked */
02969       __HAL_UNLOCK(hi2c);
02970
02971       /* Note : The I2C interrupts must be enabled after unlocking current process
02972                 to avoid the risk of I2C interrupt handle execution before current
02973                 process unlock */
02974       /* Enable ERR and NACK interrupts */
02975       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02976
02977       /* Enable DMA Request */
02978       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02979     }
02980     else
02981     {
02982       /* Update I2C state */
02983       hi2c->State     = HAL_I2C_STATE_READY;
02984       hi2c->Mode      = HAL_I2C_MODE_NONE;
02985
02986       /* Update I2C error code */
02987       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02988
02989       /* Process Unlocked */
02990       __HAL_UNLOCK(hi2c);
02991
02992       return HAL_ERROR;
02993     }
02994
02995     return HAL_OK;
02996   }
02997   else
02998   {
02999     return HAL_BUSY;
03000   }
03001 }
03002
03003 /**
03004   * @brief  Checks if target device is ready for communication.
03005   * @note   This function is used with Memory devices
03006   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03007   *                the configuration information for the specified I2C.
03008   * @param  DevAddress Target device address: The device 7 bits address value
03009   *         in datasheet must be shifted to the left before calling the interface
03010   * @param  Trials Number of trials
03011   * @param  Timeout Timeout duration
03012   * @retval HAL status
03013   */
03014 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
03015 {
03016   uint32_t tickstart;
03017
03018   __IO uint32_t I2C_Trials = 0UL;
03019
03020   FlagStatus tmp1;
03021   FlagStatus tmp2;
03022
03023   if (hi2c->State == HAL_I2C_STATE_READY)
03024   {
03025     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
03026     {
03027       return HAL_BUSY;
03028     }
03029
03030     /* Process Locked */
03031     __HAL_LOCK(hi2c);
03032
03033     hi2c->State = HAL_I2C_STATE_BUSY;
03034     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03035
03036     do
03037     {
03038       /* Generate Start */
03039       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
03040
03041       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03042       /* Wait until STOPF flag is set or a NACK flag is set*/
03043       tickstart = HAL_GetTick();
03044
03045       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03046       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03047
03048       while ((tmp1 == RESET) && (tmp2 == RESET))
03049       {
03050         if (Timeout != HAL_MAX_DELAY)
03051         {
03052           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03053           {
03054             /* Update I2C state */
03055             hi2c->State = HAL_I2C_STATE_READY;
03056
03057             /* Update I2C error code */
03058             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03059
03060             /* Process Unlocked */
03061             __HAL_UNLOCK(hi2c);
03062
03063             return HAL_ERROR;
03064           }
03065         }
03066
03067         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03068         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03069       }
03070
03071       /* Check if the NACKF flag has not been set */
03072       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
03073       {
03074         /* Wait until STOPF flag is reset */
03075         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03076         {
03077           return HAL_ERROR;
03078         }
03079
03080         /* Clear STOP Flag */
03081         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03082
03083         /* Device is ready */
03084         hi2c->State = HAL_I2C_STATE_READY;
03085
03086         /* Process Unlocked */
03087         __HAL_UNLOCK(hi2c);
03088
03089         return HAL_OK;
03090       }
03091       else
03092       {
03093         /* Wait until STOPF flag is reset */
03094         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03095         {
03096           return HAL_ERROR;
03097         }
03098
03099         /* Clear NACK Flag */
03100         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03101
03102         /* Clear STOP Flag, auto generated with autoend*/
03103         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03104       }
03105
03106       /* Check if the maximum allowed number of trials has been reached */
03107       if (I2C_Trials == Trials)
03108       {
03109         /* Generate Stop */
03110         hi2c->Instance->CR2 |= I2C_CR2_STOP;
03111
03112         /* Wait until STOPF flag is reset */
03113         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03114         {
03115           return HAL_ERROR;
03116         }
03117
03118         /* Clear STOP Flag */
03119         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03120       }
03121
03122       /* Increment Trials */
03123       I2C_Trials++;
03124     }
03125     while (I2C_Trials < Trials);
03126
03127     /* Update I2C state */
03128     hi2c->State = HAL_I2C_STATE_READY;
03129
03130     /* Update I2C error code */
03131     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03132
03133     /* Process Unlocked */
03134     __HAL_UNLOCK(hi2c);
03135
03136     return HAL_ERROR;
03137   }
03138   else
03139   {
03140     return HAL_BUSY;
03141   }
03142 }
03143
03144 /**
03145   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
03146   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03147   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03148   *                the configuration information for the specified I2C.
03149   * @param  DevAddress Target device address: The device 7 bits address value
03150   *         in datasheet must be shifted to the left before calling the interface
03151   * @param  pData Pointer to data buffer
03152   * @param  Size Amount of data to be sent
03153   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03154   * @retval HAL status
03155   */
03156 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03157 {
03158   uint32_t xfermode;
03159   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03160
03161   /* Check the parameters */
03162   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03163
03164   if (hi2c->State == HAL_I2C_STATE_READY)
03165   {
03166     /* Process Locked */
03167     __HAL_LOCK(hi2c);
03168
03169     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03170     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03171     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03172
03173     /* Prepare transfer parameters */
03174     hi2c->pBuffPtr    = pData;
03175     hi2c->XferCount   = Size;
03176     hi2c->XferOptions = XferOptions;
03177     hi2c->XferISR     = I2C_Master_ISR_IT;
03178
03179     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03180     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03181     {
03182       hi2c->XferSize = MAX_NBYTE_SIZE;
03183       xfermode = I2C_RELOAD_MODE;
03184     }
03185     else
03186     {
03187       hi2c->XferSize = hi2c->XferCount;
03188       xfermode = hi2c->XferOptions;
03189     }
03190
03191     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03192     /* Mean Previous state is same as current state */
03193     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03194     {
03195       xferrequest = I2C_NO_STARTSTOP;
03196     }
03197     else
03198     {
03199       /* Convert OTHER_xxx XferOptions if any */
03200       I2C_ConvertOtherXferOptions(hi2c);
03201
03202       /* Update xfermode accordingly if no reload is necessary */
03203       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03204       {
03205         xfermode = hi2c->XferOptions;
03206       }
03207     }
03208
03209     /* Send Slave Address and set NBYTES to write */
03210     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03211
03212     /* Process Unlocked */
03213     __HAL_UNLOCK(hi2c);
03214
03215     /* Note : The I2C interrupts must be enabled after unlocking current process
03216               to avoid the risk of I2C interrupt handle execution before current
03217               process unlock */
03218     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03219
03220     return HAL_OK;
03221   }
03222   else
03223   {
03224     return HAL_BUSY;
03225   }
03226 }
03227
03228 /**
03229   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
03230   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03231   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03232   *                the configuration information for the specified I2C.
03233   * @param  DevAddress Target device address: The device 7 bits address value
03234   *         in datasheet must be shifted to the left before calling the interface
03235   * @param  pData Pointer to data buffer
03236   * @param  Size Amount of data to be sent
03237   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03238   * @retval HAL status
03239   */
03240 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03241 {
03242   uint32_t xfermode;
03243   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03244   HAL_StatusTypeDef dmaxferstatus;
03245
03246   /* Check the parameters */
03247   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03248
03249   if (hi2c->State == HAL_I2C_STATE_READY)
03250   {
03251     /* Process Locked */
03252     __HAL_LOCK(hi2c);
03253
03254     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03255     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03256     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03257
03258     /* Prepare transfer parameters */
03259     hi2c->pBuffPtr    = pData;
03260     hi2c->XferCount   = Size;
03261     hi2c->XferOptions = XferOptions;
03262     hi2c->XferISR     = I2C_Master_ISR_DMA;
03263
03264     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03265     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03266     {
03267       hi2c->XferSize = MAX_NBYTE_SIZE;
03268       xfermode = I2C_RELOAD_MODE;
03269     }
03270     else
03271     {
03272       hi2c->XferSize = hi2c->XferCount;
03273       xfermode = hi2c->XferOptions;
03274     }
03275
03276     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03277     /* Mean Previous state is same as current state */
03278     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03279     {
03280       xferrequest = I2C_NO_STARTSTOP;
03281     }
03282     else
03283     {
03284       /* Convert OTHER_xxx XferOptions if any */
03285       I2C_ConvertOtherXferOptions(hi2c);
03286
03287       /* Update xfermode accordingly if no reload is necessary */
03288       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03289       {
03290         xfermode = hi2c->XferOptions;
03291       }
03292     }
03293
03294     if (hi2c->XferSize > 0U)
03295     {
03296       if (hi2c->hdmatx != NULL)
03297       {
03298         /* Set the I2C DMA transfer complete callback */
03299         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
03300
03301         /* Set the DMA error callback */
03302         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03303
03304         /* Set the unused DMA callbacks to NULL */
03305         hi2c->hdmatx->XferHalfCpltCallback = NULL;
03306         hi2c->hdmatx->XferAbortCallback = NULL;
03307
03308         /* Enable the DMA stream or channel depends on Instance */
03309         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03310       }
03311       else
03312       {
03313         /* Update I2C state */
03314         hi2c->State     = HAL_I2C_STATE_READY;
03315         hi2c->Mode      = HAL_I2C_MODE_NONE;
03316
03317         /* Update I2C error code */
03318         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03319
03320         /* Process Unlocked */
03321         __HAL_UNLOCK(hi2c);
03322
03323         return HAL_ERROR;
03324       }
03325
03326       if (dmaxferstatus == HAL_OK)
03327       {
03328         /* Send Slave Address and set NBYTES to write */
03329         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03330
03331         /* Update XferCount value */
03332         hi2c->XferCount -= hi2c->XferSize;
03333
03334         /* Process Unlocked */
03335         __HAL_UNLOCK(hi2c);
03336
03337         /* Note : The I2C interrupts must be enabled after unlocking current process
03338                   to avoid the risk of I2C interrupt handle execution before current
03339                   process unlock */
03340         /* Enable ERR and NACK interrupts */
03341         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03342
03343         /* Enable DMA Request */
03344         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03345       }
03346       else
03347       {
03348         /* Update I2C state */
03349         hi2c->State     = HAL_I2C_STATE_READY;
03350         hi2c->Mode      = HAL_I2C_MODE_NONE;
03351
03352         /* Update I2C error code */
03353         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03354
03355         /* Process Unlocked */
03356         __HAL_UNLOCK(hi2c);
03357
03358         return HAL_ERROR;
03359       }
03360     }
03361     else
03362     {
03363       /* Update Transfer ISR function pointer */
03364       hi2c->XferISR = I2C_Master_ISR_IT;
03365
03366       /* Send Slave Address */
03367       /* Set NBYTES to write and generate START condition */
03368       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
03369
03370       /* Process Unlocked */
03371       __HAL_UNLOCK(hi2c);
03372
03373       /* Note : The I2C interrupts must be enabled after unlocking current process
03374                 to avoid the risk of I2C interrupt handle execution before current
03375                 process unlock */
03376       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03377       /* possible to enable all of these */
03378       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03379       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03380     }
03381
03382     return HAL_OK;
03383   }
03384   else
03385   {
03386     return HAL_BUSY;
03387   }
03388 }
03389
03390 /**
03391   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
03392   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03393   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03394   *                the configuration information for the specified I2C.
03395   * @param  DevAddress Target device address: The device 7 bits address value
03396   *         in datasheet must be shifted to the left before calling the interface
03397   * @param  pData Pointer to data buffer
03398   * @param  Size Amount of data to be sent
03399   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03400   * @retval HAL status
03401   */
03402 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03403 {
03404   uint32_t xfermode;
03405   uint32_t xferrequest = I2C_GENERATE_START_READ;
03406
03407   /* Check the parameters */
03408   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03409
03410   if (hi2c->State == HAL_I2C_STATE_READY)
03411   {
03412     /* Process Locked */
03413     __HAL_LOCK(hi2c);
03414
03415     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03416     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03417     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03418
03419     /* Prepare transfer parameters */
03420     hi2c->pBuffPtr    = pData;
03421     hi2c->XferCount   = Size;
03422     hi2c->XferOptions = XferOptions;
03423     hi2c->XferISR     = I2C_Master_ISR_IT;
03424
03425     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03426     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03427     {
03428       hi2c->XferSize = MAX_NBYTE_SIZE;
03429       xfermode = I2C_RELOAD_MODE;
03430     }
03431     else
03432     {
03433       hi2c->XferSize = hi2c->XferCount;
03434       xfermode = hi2c->XferOptions;
03435     }
03436
03437     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03438     /* Mean Previous state is same as current state */
03439     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03440     {
03441       xferrequest = I2C_NO_STARTSTOP;
03442     }
03443     else
03444     {
03445       /* Convert OTHER_xxx XferOptions if any */
03446       I2C_ConvertOtherXferOptions(hi2c);
03447
03448       /* Update xfermode accordingly if no reload is necessary */
03449       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03450       {
03451         xfermode = hi2c->XferOptions;
03452       }
03453     }
03454
03455     /* Send Slave Address and set NBYTES to read */
03456     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03457
03458     /* Process Unlocked */
03459     __HAL_UNLOCK(hi2c);
03460
03461     /* Note : The I2C interrupts must be enabled after unlocking current process
03462               to avoid the risk of I2C interrupt handle execution before current
03463               process unlock */
03464     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
03465
03466     return HAL_OK;
03467   }
03468   else
03469   {
03470     return HAL_BUSY;
03471   }
03472 }
03473
03474 /**
03475   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
03476   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03477   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03478   *                the configuration information for the specified I2C.
03479   * @param  DevAddress Target device address: The device 7 bits address value
03480   *         in datasheet must be shifted to the left before calling the interface
03481   * @param  pData Pointer to data buffer
03482   * @param  Size Amount of data to be sent
03483   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03484   * @retval HAL status
03485   */
03486 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03487 {
03488   uint32_t xfermode;
03489   uint32_t xferrequest = I2C_GENERATE_START_READ;
03490   HAL_StatusTypeDef dmaxferstatus;
03491
03492   /* Check the parameters */
03493   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03494
03495   if (hi2c->State == HAL_I2C_STATE_READY)
03496   {
03497     /* Process Locked */
03498     __HAL_LOCK(hi2c);
03499
03500     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03501     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03502     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03503
03504     /* Prepare transfer parameters */
03505     hi2c->pBuffPtr    = pData;
03506     hi2c->XferCount   = Size;
03507     hi2c->XferOptions = XferOptions;
03508     hi2c->XferISR     = I2C_Master_ISR_DMA;
03509
03510     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03511     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03512     {
03513       hi2c->XferSize = MAX_NBYTE_SIZE;
03514       xfermode = I2C_RELOAD_MODE;
03515     }
03516     else
03517     {
03518       hi2c->XferSize = hi2c->XferCount;
03519       xfermode = hi2c->XferOptions;
03520     }
03521
03522     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03523     /* Mean Previous state is same as current state */
03524     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03525     {
03526       xferrequest = I2C_NO_STARTSTOP;
03527     }
03528     else
03529     {
03530       /* Convert OTHER_xxx XferOptions if any */
03531       I2C_ConvertOtherXferOptions(hi2c);
03532
03533       /* Update xfermode accordingly if no reload is necessary */
03534       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03535       {
03536         xfermode = hi2c->XferOptions;
03537       }
03538     }
03539
03540     if (hi2c->XferSize > 0U)
03541     {
03542       if (hi2c->hdmarx != NULL)
03543       {
03544         /* Set the I2C DMA transfer complete callback */
03545         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03546
03547         /* Set the DMA error callback */
03548         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03549
03550         /* Set the unused DMA callbacks to NULL */
03551         hi2c->hdmarx->XferHalfCpltCallback = NULL;
03552         hi2c->hdmarx->XferAbortCallback = NULL;
03553
03554         /* Enable the DMA stream or channel depends on Instance */
03555         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
03556       }
03557       else
03558       {
03559         /* Update I2C state */
03560         hi2c->State     = HAL_I2C_STATE_READY;
03561         hi2c->Mode      = HAL_I2C_MODE_NONE;
03562
03563         /* Update I2C error code */
03564         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03565
03566         /* Process Unlocked */
03567         __HAL_UNLOCK(hi2c);
03568
03569         return HAL_ERROR;
03570       }
03571
03572       if (dmaxferstatus == HAL_OK)
03573       {
03574         /* Send Slave Address and set NBYTES to read */
03575         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03576
03577         /* Update XferCount value */
03578         hi2c->XferCount -= hi2c->XferSize;
03579
03580         /* Process Unlocked */
03581         __HAL_UNLOCK(hi2c);
03582
03583         /* Note : The I2C interrupts must be enabled after unlocking current process
03584                   to avoid the risk of I2C interrupt handle execution before current
03585                   process unlock */
03586         /* Enable ERR and NACK interrupts */
03587         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03588
03589         /* Enable DMA Request */
03590         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03591       }
03592       else
03593       {
03594         /* Update I2C state */
03595         hi2c->State     = HAL_I2C_STATE_READY;
03596         hi2c->Mode      = HAL_I2C_MODE_NONE;
03597
03598         /* Update I2C error code */
03599         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03600
03601         /* Process Unlocked */
03602         __HAL_UNLOCK(hi2c);
03603
03604         return HAL_ERROR;
03605       }
03606     }
03607     else
03608     {
03609       /* Update Transfer ISR function pointer */
03610       hi2c->XferISR = I2C_Master_ISR_IT;
03611
03612       /* Send Slave Address */
03613       /* Set NBYTES to read and generate START condition */
03614       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
03615
03616       /* Process Unlocked */
03617       __HAL_UNLOCK(hi2c);
03618
03619       /* Note : The I2C interrupts must be enabled after unlocking current process
03620                 to avoid the risk of I2C interrupt handle execution before current
03621                 process unlock */
03622       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03623       /* possible to enable all of these */
03624       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03625       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03626     }
03627
03628     return HAL_OK;
03629   }
03630   else
03631   {
03632     return HAL_BUSY;
03633   }
03634 }
03635
03636 /**
03637   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03638   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03639   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03640   *                the configuration information for the specified I2C.
03641   * @param  pData Pointer to data buffer
03642   * @param  Size Amount of data to be sent
03643   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03644   * @retval HAL status
03645   */
03646 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03647 {
03648   /* Check the parameters */
03649   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03650
03651   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03652   {
03653     if ((pData == NULL) || (Size == 0U))
03654     {
03655       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03656       return  HAL_ERROR;
03657     }
03658
03659     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03660     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03661
03662     /* Process Locked */
03663     __HAL_LOCK(hi2c);
03664
03665     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03666     /* and then toggle the HAL slave RX state to TX state */
03667     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03668     {
03669       /* Disable associated Interrupts */
03670       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03671
03672       /* Abort DMA Xfer if any */
03673       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03674       {
03675         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03676
03677         if (hi2c->hdmarx != NULL)
03678         {
03679           /* Set the I2C DMA Abort callback :
03680            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03681           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03682
03683           /* Abort DMA RX */
03684           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03685           {
03686             /* Call Directly XferAbortCallback function in case of error */
03687             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03688           }
03689         }
03690       }
03691     }
03692
03693     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03694     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03695     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03696
03697     /* Enable Address Acknowledge */
03698     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03699
03700     /* Prepare transfer parameters */
03701     hi2c->pBuffPtr    = pData;
03702     hi2c->XferCount   = Size;
03703     hi2c->XferSize    = hi2c->XferCount;
03704     hi2c->XferOptions = XferOptions;
03705     hi2c->XferISR     = I2C_Slave_ISR_IT;
03706
03707     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
03708     {
03709       /* Clear ADDR flag after prepare the transfer parameters */
03710       /* This action will generate an acknowledge to the Master */
03711       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03712     }
03713
03714     /* Process Unlocked */
03715     __HAL_UNLOCK(hi2c);
03716
03717     /* Note : The I2C interrupts must be enabled after unlocking current process
03718     to avoid the risk of I2C interrupt handle execution before current
03719     process unlock */
03720     /* REnable ADDR interrupt */
03721     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
03722
03723     return HAL_OK;
03724   }
03725   else
03726   {
03727     return HAL_ERROR;
03728   }
03729 }
03730
03731 /**
03732   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
03733   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03734   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03735   *                the configuration information for the specified I2C.
03736   * @param  pData Pointer to data buffer
03737   * @param  Size Amount of data to be sent
03738   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03739   * @retval HAL status
03740   */
03741 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03742 {
03743   HAL_StatusTypeDef dmaxferstatus;
03744
03745   /* Check the parameters */
03746   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03747
03748   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03749   {
03750     if ((pData == NULL) || (Size == 0U))
03751     {
03752       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03753       return  HAL_ERROR;
03754     }
03755
03756     /* Process Locked */
03757     __HAL_LOCK(hi2c);
03758
03759     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03760     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03761
03762     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03763     /* and then toggle the HAL slave RX state to TX state */
03764     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03765     {
03766       /* Disable associated Interrupts */
03767       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03768
03769       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03770       {
03771         /* Abort DMA Xfer if any */
03772         if (hi2c->hdmarx != NULL)
03773         {
03774           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03775
03776           /* Set the I2C DMA Abort callback :
03777            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03778           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03779
03780           /* Abort DMA RX */
03781           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03782           {
03783             /* Call Directly XferAbortCallback function in case of error */
03784             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03785           }
03786         }
03787       }
03788     }
03789     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03790     {
03791       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
03792       {
03793         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03794
03795         /* Abort DMA Xfer if any */
03796         if (hi2c->hdmatx != NULL)
03797         {
03798           /* Set the I2C DMA Abort callback :
03799            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03800           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
03801
03802           /* Abort DMA TX */
03803           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
03804           {
03805             /* Call Directly XferAbortCallback function in case of error */
03806             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
03807           }
03808         }
03809       }
03810     }
03811     else
03812     {
03813       /* Nothing to do */
03814     }
03815
03816     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03817     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03818     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03819
03820     /* Enable Address Acknowledge */
03821     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03822
03823     /* Prepare transfer parameters */
03824     hi2c->pBuffPtr    = pData;
03825     hi2c->XferCount   = Size;
03826     hi2c->XferSize    = hi2c->XferCount;
03827     hi2c->XferOptions = XferOptions;
03828     hi2c->XferISR     = I2C_Slave_ISR_DMA;
03829
03830     if (hi2c->hdmatx != NULL)
03831     {
03832       /* Set the I2C DMA transfer complete callback */
03833       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
03834
03835       /* Set the DMA error callback */
03836       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03837
03838       /* Set the unused DMA callbacks to NULL */
03839       hi2c->hdmatx->XferHalfCpltCallback = NULL;
03840       hi2c->hdmatx->XferAbortCallback = NULL;
03841
03842       /* Enable the DMA stream or channel depends on Instance */
03843       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03844     }
03845     else
03846     {
03847       /* Update I2C state */
03848       hi2c->State     = HAL_I2C_STATE_LISTEN;
03849       hi2c->Mode      = HAL_I2C_MODE_NONE;
03850
03851       /* Update I2C error code */
03852       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03853
03854       /* Process Unlocked */
03855       __HAL_UNLOCK(hi2c);
03856
03857       return HAL_ERROR;
03858     }
03859
03860     if (dmaxferstatus == HAL_OK)
03861     {
03862       /* Update XferCount value */
03863       hi2c->XferCount -= hi2c->XferSize;
03864
03865       /* Reset XferSize */
03866       hi2c->XferSize = 0;
03867     }
03868     else
03869     {
03870       /* Update I2C state */
03871       hi2c->State     = HAL_I2C_STATE_LISTEN;
03872       hi2c->Mode      = HAL_I2C_MODE_NONE;
03873
03874       /* Update I2C error code */
03875       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03876
03877       /* Process Unlocked */
03878       __HAL_UNLOCK(hi2c);
03879
03880       return HAL_ERROR;
03881     }
03882
03883     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
03884     {
03885       /* Clear ADDR flag after prepare the transfer parameters */
03886       /* This action will generate an acknowledge to the Master */
03887       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03888     }
03889
03890     /* Process Unlocked */
03891     __HAL_UNLOCK(hi2c);
03892
03893     /* Note : The I2C interrupts must be enabled after unlocking current process
03894     to avoid the risk of I2C interrupt handle execution before current
03895     process unlock */
03896     /* Enable ERR, STOP, NACK, ADDR interrupts */
03897     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03898
03899     /* Enable DMA Request */
03900     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03901
03902     return HAL_OK;
03903   }
03904   else
03905   {
03906     return HAL_ERROR;
03907   }
03908 }
03909
03910 /**
03911   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03912   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03913   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03914   *                the configuration information for the specified I2C.
03915   * @param  pData Pointer to data buffer
03916   * @param  Size Amount of data to be sent
03917   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03918   * @retval HAL status
03919   */
03920 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03921 {
03922   /* Check the parameters */
03923   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03924
03925   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03926   {
03927     if ((pData == NULL) || (Size == 0U))
03928     {
03929       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03930       return  HAL_ERROR;
03931     }
03932
03933     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03934     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
03935
03936     /* Process Locked */
03937     __HAL_LOCK(hi2c);
03938
03939     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03940     /* and then toggle the HAL slave TX state to RX state */
03941     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03942     {
03943       /* Disable associated Interrupts */
03944       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03945
03946       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
03947       {
03948         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03949
03950         /* Abort DMA Xfer if any */
03951         if (hi2c->hdmatx != NULL)
03952         {
03953           /* Set the I2C DMA Abort callback :
03954            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03955           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
03956
03957           /* Abort DMA TX */
03958           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
03959           {
03960             /* Call Directly XferAbortCallback function in case of error */
03961             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
03962           }
03963         }
03964       }
03965     }
03966
03967     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
03968     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03969     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03970
03971     /* Enable Address Acknowledge */
03972     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03973
03974     /* Prepare transfer parameters */
03975     hi2c->pBuffPtr    = pData;
03976     hi2c->XferCount   = Size;
03977     hi2c->XferSize    = hi2c->XferCount;
03978     hi2c->XferOptions = XferOptions;
03979     hi2c->XferISR     = I2C_Slave_ISR_IT;
03980
03981     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
03982     {
03983       /* Clear ADDR flag after prepare the transfer parameters */
03984       /* This action will generate an acknowledge to the Master */
03985       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03986     }
03987
03988     /* Process Unlocked */
03989     __HAL_UNLOCK(hi2c);
03990
03991     /* Note : The I2C interrupts must be enabled after unlocking current process
03992     to avoid the risk of I2C interrupt handle execution before current
03993     process unlock */
03994     /* REnable ADDR interrupt */
03995     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
03996
03997     return HAL_OK;
03998   }
03999   else
04000   {
04001     return HAL_ERROR;
04002   }
04003 }
04004
04005 /**
04006   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
04007   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04008   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04009   *                the configuration information for the specified I2C.
04010   * @param  pData Pointer to data buffer
04011   * @param  Size Amount of data to be sent
04012   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04013   * @retval HAL status
04014   */
04015 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
04016 {
04017   HAL_StatusTypeDef dmaxferstatus;
04018
04019   /* Check the parameters */
04020   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04021
04022   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04023   {
04024     if ((pData == NULL) || (Size == 0U))
04025     {
04026       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04027       return  HAL_ERROR;
04028     }
04029
04030     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04031     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04032
04033     /* Process Locked */
04034     __HAL_LOCK(hi2c);
04035
04036     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04037     /* and then toggle the HAL slave TX state to RX state */
04038     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04039     {
04040       /* Disable associated Interrupts */
04041       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04042
04043       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04044       {
04045         /* Abort DMA Xfer if any */
04046         if (hi2c->hdmatx != NULL)
04047         {
04048           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04049
04050           /* Set the I2C DMA Abort callback :
04051            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04052           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04053
04054           /* Abort DMA TX */
04055           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04056           {
04057             /* Call Directly XferAbortCallback function in case of error */
04058             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04059           }
04060         }
04061       }
04062     }
04063     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
04064     {
04065       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04066       {
04067         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04068
04069         /* Abort DMA Xfer if any */
04070         if (hi2c->hdmarx != NULL)
04071         {
04072           /* Set the I2C DMA Abort callback :
04073            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04074           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04075
04076           /* Abort DMA RX */
04077           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04078           {
04079             /* Call Directly XferAbortCallback function in case of error */
04080             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04081           }
04082         }
04083       }
04084     }
04085     else
04086     {
04087       /* Nothing to do */
04088     }
04089
04090     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04091     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04092     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04093
04094     /* Enable Address Acknowledge */
04095     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04096
04097     /* Prepare transfer parameters */
04098     hi2c->pBuffPtr    = pData;
04099     hi2c->XferCount   = Size;
04100     hi2c->XferSize    = hi2c->XferCount;
04101     hi2c->XferOptions = XferOptions;
04102     hi2c->XferISR     = I2C_Slave_ISR_DMA;
04103
04104     if (hi2c->hdmarx != NULL)
04105     {
04106       /* Set the I2C DMA transfer complete callback */
04107       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
04108
04109       /* Set the DMA error callback */
04110       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
04111
04112       /* Set the unused DMA callbacks to NULL */
04113       hi2c->hdmarx->XferHalfCpltCallback = NULL;
04114       hi2c->hdmarx->XferAbortCallback = NULL;
04115
04116       /* Enable the DMA stream or channel depends on Instance */
04117       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
04118     }
04119     else
04120     {
04121       /* Update I2C state */
04122       hi2c->State     = HAL_I2C_STATE_LISTEN;
04123       hi2c->Mode      = HAL_I2C_MODE_NONE;
04124
04125       /* Update I2C error code */
04126       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
04127
04128       /* Process Unlocked */
04129       __HAL_UNLOCK(hi2c);
04130
04131       return HAL_ERROR;
04132     }
04133
04134     if (dmaxferstatus == HAL_OK)
04135     {
04136       /* Update XferCount value */
04137       hi2c->XferCount -= hi2c->XferSize;
04138
04139       /* Reset XferSize */
04140       hi2c->XferSize = 0;
04141     }
04142     else
04143     {
04144       /* Update I2C state */
04145       hi2c->State     = HAL_I2C_STATE_LISTEN;
04146       hi2c->Mode      = HAL_I2C_MODE_NONE;
04147
04148       /* Update I2C error code */
04149       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04150
04151       /* Process Unlocked */
04152       __HAL_UNLOCK(hi2c);
04153
04154       return HAL_ERROR;
04155     }
04156
04157     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
04158     {
04159       /* Clear ADDR flag after prepare the transfer parameters */
04160       /* This action will generate an acknowledge to the Master */
04161       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04162     }
04163
04164     /* Process Unlocked */
04165     __HAL_UNLOCK(hi2c);
04166
04167     /* Note : The I2C interrupts must be enabled after unlocking current process
04168     to avoid the risk of I2C interrupt handle execution before current
04169     process unlock */
04170     /* REnable ADDR interrupt */
04171     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04172
04173     /* Enable DMA Request */
04174     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04175
04176     return HAL_OK;
04177   }
04178   else
04179   {
04180     return HAL_ERROR;
04181   }
04182 }
04183
04184 /**
04185   * @brief  Enable the Address listen mode with Interrupt.
04186   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04187   *                the configuration information for the specified I2C.
04188   * @retval HAL status
04189   */
04190 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
04191 {
04192   if (hi2c->State == HAL_I2C_STATE_READY)
04193   {
04194     hi2c->State = HAL_I2C_STATE_LISTEN;
04195     hi2c->XferISR = I2C_Slave_ISR_IT;
04196
04197     /* Enable the Address Match interrupt */
04198     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04199
04200     return HAL_OK;
04201   }
04202   else
04203   {
04204     return HAL_BUSY;
04205   }
04206 }
04207
04208 /**
04209   * @brief  Disable the Address listen mode with Interrupt.
04210   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04211   *                the configuration information for the specified I2C
04212   * @retval HAL status
04213   */
04214 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
04215 {
04216   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04217   uint32_t tmp;
04218
04219   /* Disable Address listen mode only if a transfer is not ongoing */
04220   if (hi2c->State == HAL_I2C_STATE_LISTEN)
04221   {
04222     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
04223     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
04224     hi2c->State = HAL_I2C_STATE_READY;
04225     hi2c->Mode = HAL_I2C_MODE_NONE;
04226     hi2c->XferISR = NULL;
04227
04228     /* Disable the Address Match interrupt */
04229     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04230
04231     return HAL_OK;
04232   }
04233   else
04234   {
04235     return HAL_BUSY;
04236   }
04237 }
04238
04239 /**
04240   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
04241   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04242   *                the configuration information for the specified I2C.
04243   * @param  DevAddress Target device address: The device 7 bits address value
04244   *         in datasheet must be shifted to the left before calling the interface
04245   * @retval HAL status
04246   */
04247 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
04248 {
04249   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
04250   {
04251     /* Process Locked */
04252     __HAL_LOCK(hi2c);
04253
04254     /* Disable Interrupts */
04255     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
04256     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04257
04258     /* Set State at HAL_I2C_STATE_ABORT */
04259     hi2c->State = HAL_I2C_STATE_ABORT;
04260
04261     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
04262     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
04263     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
04264
04265     /* Process Unlocked */
04266     __HAL_UNLOCK(hi2c);
04267
04268     /* Note : The I2C interrupts must be enabled after unlocking current process
04269               to avoid the risk of I2C interrupt handle execution before current
04270               process unlock */
04271     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04272
04273     return HAL_OK;
04274   }
04275   else
04276   {
04277     /* Wrong usage of abort function */
04278     /* This function should be used only in case of abort monitored by master device */
04279     return HAL_ERROR;
04280   }
04281 }
04282
04283 /**
04284   * @}
04285   */
04286
04287 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
04288  * @{
04289  */
04290
04291 /**
04292   * @brief  This function handles I2C event interrupt request.
04293   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04294   *                the configuration information for the specified I2C.
04295   * @retval None
04296   */
04297 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
04298 {
04299   /* Get current IT Flags and IT sources value */
04300   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04301   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04302
04303   /* I2C events treatment -------------------------------------*/
04304   if (hi2c->XferISR != NULL)
04305   {
04306     hi2c->XferISR(hi2c, itflags, itsources);
04307   }
04308 }
04309
04310 /**
04311   * @brief  This function handles I2C error interrupt request.
04312   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04313   *                the configuration information for the specified I2C.
04314   * @retval None
04315   */
04316 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
04317 {
04318   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04319   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04320   uint32_t tmperror;
04321
04322   /* I2C Bus error interrupt occurred ------------------------------------*/
04323   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04324   {
04325     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
04326
04327     /* Clear BERR flag */
04328     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
04329   }
04330
04331   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
04332   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04333   {
04334     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
04335
04336     /* Clear OVR flag */
04337     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
04338   }
04339
04340   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
04341   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04342   {
04343     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
04344
04345     /* Clear ARLO flag */
04346     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
04347   }
04348
04349   /* Store current volatile hi2c->ErrorCode, misra rule */
04350   tmperror = hi2c->ErrorCode;
04351
04352   /* Call the Error Callback in case of Error detected */
04353   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
04354   {
04355     I2C_ITError(hi2c, tmperror);
04356   }
04357 }
04358
04359 /**
04360   * @brief  Master Tx Transfer completed callback.
04361   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04362   *                the configuration information for the specified I2C.
04363   * @retval None
04364   */
04365 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
04366 {
04367   /* Prevent unused argument(s) compilation warning */
04368   UNUSED(hi2c);
04369
04370   /* NOTE : This function should not be modified, when the callback is needed,
04371             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
04372    */
04373 }
04374
04375 /**
04376   * @brief  Master Rx Transfer completed callback.
04377   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04378   *                the configuration information for the specified I2C.
04379   * @retval None
04380   */
04381 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
04382 {
04383   /* Prevent unused argument(s) compilation warning */
04384   UNUSED(hi2c);
04385
04386   /* NOTE : This function should not be modified, when the callback is needed,
04387             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
04388    */
04389 }
04390
04391 /** @brief  Slave Tx Transfer completed callback.
04392   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04393   *                the configuration information for the specified I2C.
04394   * @retval None
04395   */
04396 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
04397 {
04398   /* Prevent unused argument(s) compilation warning */
04399   UNUSED(hi2c);
04400
04401   /* NOTE : This function should not be modified, when the callback is needed,
04402             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
04403    */
04404 }
04405
04406 /**
04407   * @brief  Slave Rx Transfer completed callback.
04408   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04409   *                the configuration information for the specified I2C.
04410   * @retval None
04411   */
04412 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
04413 {
04414   /* Prevent unused argument(s) compilation warning */
04415   UNUSED(hi2c);
04416
04417   /* NOTE : This function should not be modified, when the callback is needed,
04418             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
04419    */
04420 }
04421
04422 /**
04423   * @brief  Slave Address Match callback.
04424   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04425   *                the configuration information for the specified I2C.
04426   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
04427   * @param  AddrMatchCode Address Match Code
04428   * @retval None
04429   */
04430 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
04431 {
04432   /* Prevent unused argument(s) compilation warning */
04433   UNUSED(hi2c);
04434   UNUSED(TransferDirection);
04435   UNUSED(AddrMatchCode);
04436
04437   /* NOTE : This function should not be modified, when the callback is needed,
04438             the HAL_I2C_AddrCallback() could be implemented in the user file
04439    */
04440 }
04441
04442 /**
04443   * @brief  Listen Complete callback.
04444   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04445   *                the configuration information for the specified I2C.
04446   * @retval None
04447   */
04448 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
04449 {
04450   /* Prevent unused argument(s) compilation warning */
04451   UNUSED(hi2c);
04452
04453   /* NOTE : This function should not be modified, when the callback is needed,
04454             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
04455    */
04456 }
04457
04458 /**
04459   * @brief  Memory Tx Transfer completed callback.
04460   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04461   *                the configuration information for the specified I2C.
04462   * @retval None
04463   */
04464 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
04465 {
04466   /* Prevent unused argument(s) compilation warning */
04467   UNUSED(hi2c);
04468
04469   /* NOTE : This function should not be modified, when the callback is needed,
04470             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
04471    */
04472 }
04473
04474 /**
04475   * @brief  Memory Rx Transfer completed callback.
04476   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04477   *                the configuration information for the specified I2C.
04478   * @retval None
04479   */
04480 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
04481 {
04482   /* Prevent unused argument(s) compilation warning */
04483   UNUSED(hi2c);
04484
04485   /* NOTE : This function should not be modified, when the callback is needed,
04486             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
04487    */
04488 }
04489
04490 /**
04491   * @brief  I2C error callback.
04492   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04493   *                the configuration information for the specified I2C.
04494   * @retval None
04495   */
04496 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
04497 {
04498   /* Prevent unused argument(s) compilation warning */
04499   UNUSED(hi2c);
04500
04501   /* NOTE : This function should not be modified, when the callback is needed,
04502             the HAL_I2C_ErrorCallback could be implemented in the user file
04503    */
04504 }
04505
04506 /**
04507   * @brief  I2C abort callback.
04508   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04509   *                the configuration information for the specified I2C.
04510   * @retval None
04511   */
04512 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
04513 {
04514   /* Prevent unused argument(s) compilation warning */
04515   UNUSED(hi2c);
04516
04517   /* NOTE : This function should not be modified, when the callback is needed,
04518             the HAL_I2C_AbortCpltCallback could be implemented in the user file
04519    */
04520 }
04521
04522 /**
04523   * @}
04524   */
04525
04526 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
04527  *  @brief   Peripheral State, Mode and Error functions
04528  *
04529 @verbatim
04530  ===============================================================================
04531             ##### Peripheral State, Mode and Error functions #####
04532  ===============================================================================
04533     [..]
04534     This subsection permit to get in run-time the status of the peripheral
04535     and the data flow.
04536
04537 @endverbatim
04538   * @{
04539   */
04540
04541 /**
04542   * @brief  Return the I2C handle state.
04543   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04544   *                the configuration information for the specified I2C.
04545   * @retval HAL state
04546   */
04547 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
04548 {
04549   /* Return I2C handle state */
04550   return hi2c->State;
04551 }
04552
04553 /**
04554   * @brief  Returns the I2C Master, Slave, Memory or no mode.
04555   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04556   *         the configuration information for I2C module
04557   * @retval HAL mode
04558   */
04559 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
04560 {
04561   return hi2c->Mode;
04562 }
04563
04564 /**
04565 * @brief  Return the I2C error code.
04566   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04567   *              the configuration information for the specified I2C.
04568 * @retval I2C Error Code
04569 */
04570 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
04571 {
04572   return hi2c->ErrorCode;
04573 }
04574
04575 /**
04576   * @}
04577   */
04578
04579 /**
04580   * @}
04581   */
04582
04583 /** @addtogroup I2C_Private_Functions
04584   * @{
04585   */
04586
04587 /**
04588   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
04589   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04590   *                the configuration information for the specified I2C.
04591   * @param  ITFlags Interrupt flags to handle.
04592   * @param  ITSources Interrupt sources enabled.
04593   * @retval HAL status
04594   */
04595 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04596 {
04597   uint16_t devaddress;
04598   uint32_t tmpITFlags = ITFlags;
04599
04600   /* Process Locked */
04601   __HAL_LOCK(hi2c);
04602
04603   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04604   {
04605     /* Clear NACK Flag */
04606     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04607
04608     /* Set corresponding Error Code */
04609     /* No need to generate STOP, it is automatically done */
04610     /* Error callback will be send during stop flag treatment */
04611     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04612
04613     /* Flush TX register */
04614     I2C_Flush_TXDR(hi2c);
04615   }
04616   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04617   {
04618     /* Remove RXNE flag on temporary variable as read done */
04619     tmpITFlags &= ~I2C_FLAG_RXNE;
04620
04621     /* Read data from RXDR */
04622     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04623
04624     /* Increment Buffer pointer */
04625     hi2c->pBuffPtr++;
04626
04627     hi2c->XferSize--;
04628     hi2c->XferCount--;
04629   }
04630   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04631   {
04632     /* Write data to TXDR */
04633     hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04634
04635     /* Increment Buffer pointer */
04636     hi2c->pBuffPtr++;
04637
04638     hi2c->XferSize--;
04639     hi2c->XferCount--;
04640   }
04641   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04642   {
04643     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
04644     {
04645       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04646
04647       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04648       {
04649         hi2c->XferSize = MAX_NBYTE_SIZE;
04650         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
04651       }
04652       else
04653       {
04654         hi2c->XferSize = hi2c->XferCount;
04655         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04656         {
04657           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
04658         }
04659         else
04660         {
04661           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
04662         }
04663       }
04664     }
04665     else
04666     {
04667       /* Call TxCpltCallback() if no stop mode is set */
04668       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04669       {
04670         /* Call I2C Master Sequential complete process */
04671         I2C_ITMasterSeqCplt(hi2c);
04672       }
04673       else
04674       {
04675         /* Wrong size Status regarding TCR flag event */
04676         /* Call the corresponding callback to inform upper layer of End of Transfer */
04677         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04678       }
04679     }
04680   }
04681   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04682   {
04683     if (hi2c->XferCount == 0U)
04684     {
04685       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04686       {
04687         /* Generate a stop condition in case of no transfer option */
04688         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
04689         {
04690           /* Generate Stop */
04691           hi2c->Instance->CR2 |= I2C_CR2_STOP;
04692         }
04693         else
04694         {
04695           /* Call I2C Master Sequential complete process */
04696           I2C_ITMasterSeqCplt(hi2c);
04697         }
04698       }
04699     }
04700     else
04701     {
04702       /* Wrong size Status regarding TC flag event */
04703       /* Call the corresponding callback to inform upper layer of End of Transfer */
04704       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04705     }
04706   }
04707   else
04708   {
04709     /* Nothing to do */
04710   }
04711
04712   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04713   {
04714     /* Call I2C Master complete process */
04715     I2C_ITMasterCplt(hi2c, tmpITFlags);
04716   }
04717
04718   /* Process Unlocked */
04719   __HAL_UNLOCK(hi2c);
04720
04721   return HAL_OK;
04722 }
04723
04724 /**
04725   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
04726   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04727   *                the configuration information for the specified I2C.
04728   * @param  ITFlags Interrupt flags to handle.
04729   * @param  ITSources Interrupt sources enabled.
04730   * @retval HAL status
04731   */
04732 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04733 {
04734   uint32_t tmpoptions = hi2c->XferOptions;
04735   uint32_t tmpITFlags = ITFlags;
04736
04737   /* Process locked */
04738   __HAL_LOCK(hi2c);
04739
04740   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04741   {
04742     /* Check that I2C transfer finished */
04743     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
04744     /* Mean XferCount == 0*/
04745     /* So clear Flag NACKF only */
04746     if (hi2c->XferCount == 0U)
04747     {
04748       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
04749       {
04750         /* Call I2C Listen complete process */
04751         I2C_ITListenCplt(hi2c, tmpITFlags);
04752       }
04753       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
04754       {
04755         /* Clear NACK Flag */
04756         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04757
04758         /* Flush TX register */
04759         I2C_Flush_TXDR(hi2c);
04760
04761         /* Last Byte is Transmitted */
04762         /* Call I2C Slave Sequential complete process */
04763         I2C_ITSlaveSeqCplt(hi2c);
04764       }
04765       else
04766       {
04767         /* Clear NACK Flag */
04768         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04769       }
04770     }
04771     else
04772     {
04773       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
04774       /* Clear NACK Flag */
04775       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04776
04777       /* Set ErrorCode corresponding to a Non-Acknowledge */
04778       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04779
04780       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
04781       {
04782         /* Call the corresponding callback to inform upper layer of End of Transfer */
04783         I2C_ITError(hi2c, hi2c->ErrorCode);
04784       }
04785     }
04786   }
04787   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04788   {
04789     if (hi2c->XferCount > 0U)
04790     {
04791       /* Remove RXNE flag on temporary variable as read done */
04792       tmpITFlags &= ~I2C_FLAG_RXNE;
04793
04794       /* Read data from RXDR */
04795       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04796
04797       /* Increment Buffer pointer */
04798       hi2c->pBuffPtr++;
04799
04800       hi2c->XferSize--;
04801       hi2c->XferCount--;
04802     }
04803
04804     if ((hi2c->XferCount == 0U) && \
04805         (tmpoptions != I2C_NO_OPTION_FRAME))
04806     {
04807       /* Call I2C Slave Sequential complete process */
04808       I2C_ITSlaveSeqCplt(hi2c);
04809     }
04810   }
04811   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
04812   {
04813     I2C_ITAddrCplt(hi2c, tmpITFlags);
04814   }
04815   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04816   {
04817     /* Write data to TXDR only if XferCount not reach "0" */
04818     /* A TXIS flag can be set, during STOP treatment      */
04819     /* Check if all Datas have already been sent */
04820     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
04821     if (hi2c->XferCount > 0U)
04822     {
04823       /* Write data to TXDR */
04824       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04825
04826       /* Increment Buffer pointer */
04827       hi2c->pBuffPtr++;
04828
04829       hi2c->XferCount--;
04830       hi2c->XferSize--;
04831     }
04832     else
04833     {
04834       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
04835       {
04836         /* Last Byte is Transmitted */
04837         /* Call I2C Slave Sequential complete process */
04838         I2C_ITSlaveSeqCplt(hi2c);
04839       }
04840     }
04841   }
04842   else
04843   {
04844     /* Nothing to do */
04845   }
04846
04847   /* Check if STOPF is set */
04848   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04849   {
04850     /* Call I2C Slave complete process */
04851     I2C_ITSlaveCplt(hi2c, tmpITFlags);
04852   }
04853
04854   /* Process Unlocked */
04855   __HAL_UNLOCK(hi2c);
04856
04857   return HAL_OK;
04858 }
04859
04860 /**
04861   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
04862   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04863   *                the configuration information for the specified I2C.
04864   * @param  ITFlags Interrupt flags to handle.
04865   * @param  ITSources Interrupt sources enabled.
04866   * @retval HAL status
04867   */
04868 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04869 {
04870   uint16_t devaddress;
04871   uint32_t xfermode;
04872
04873   /* Process Locked */
04874   __HAL_LOCK(hi2c);
04875
04876   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04877   {
04878     /* Clear NACK Flag */
04879     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04880
04881     /* Set corresponding Error Code */
04882     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04883
04884     /* No need to generate STOP, it is automatically done */
04885     /* But enable STOP interrupt, to treat it */
04886     /* Error callback will be send during stop flag treatment */
04887     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04888
04889     /* Flush TX register */
04890     I2C_Flush_TXDR(hi2c);
04891   }
04892   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04893   {
04894     /* Disable TC interrupt */
04895     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
04896
04897     if (hi2c->XferCount != 0U)
04898     {
04899       /* Recover Slave address */
04900       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04901
04902       /* Prepare the new XferSize to transfer */
04903       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04904       {
04905         hi2c->XferSize = MAX_NBYTE_SIZE;
04906         xfermode = I2C_RELOAD_MODE;
04907       }
04908       else
04909       {
04910         hi2c->XferSize = hi2c->XferCount;
04911         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04912         {
04913           xfermode = hi2c->XferOptions;
04914         }
04915         else
04916         {
04917           xfermode = I2C_AUTOEND_MODE;
04918         }
04919       }
04920
04921       /* Set the new XferSize in Nbytes register */
04922       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
04923
04924       /* Update XferCount value */
04925       hi2c->XferCount -= hi2c->XferSize;
04926
04927       /* Enable DMA Request */
04928       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04929       {
04930         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04931       }
04932       else
04933       {
04934         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
04935       }
04936     }
04937     else
04938     {
04939       /* Call TxCpltCallback() if no stop mode is set */
04940       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04941       {
04942         /* Call I2C Master Sequential complete process */
04943         I2C_ITMasterSeqCplt(hi2c);
04944       }
04945       else
04946       {
04947         /* Wrong size Status regarding TCR flag event */
04948         /* Call the corresponding callback to inform upper layer of End of Transfer */
04949         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04950       }
04951     }
04952   }
04953   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04954   {
04955     if (hi2c->XferCount == 0U)
04956     {
04957       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04958       {
04959         /* Generate a stop condition in case of no transfer option */
04960         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
04961         {
04962           /* Generate Stop */
04963           hi2c->Instance->CR2 |= I2C_CR2_STOP;
04964         }
04965         else
04966         {
04967           /* Call I2C Master Sequential complete process */
04968           I2C_ITMasterSeqCplt(hi2c);
04969         }
04970       }
04971     }
04972     else
04973     {
04974       /* Wrong size Status regarding TC flag event */
04975       /* Call the corresponding callback to inform upper layer of End of Transfer */
04976       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04977     }
04978   }
04979   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04980   {
04981     /* Call I2C Master complete process */
04982     I2C_ITMasterCplt(hi2c, ITFlags);
04983   }
04984   else
04985   {
04986     /* Nothing to do */
04987   }
04988
04989   /* Process Unlocked */
04990   __HAL_UNLOCK(hi2c);
04991
04992   return HAL_OK;
04993 }
04994
04995 /**
04996   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
04997   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04998   *                the configuration information for the specified I2C.
04999   * @param  ITFlags Interrupt flags to handle.
05000   * @param  ITSources Interrupt sources enabled.
05001   * @retval HAL status
05002   */
05003 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
05004 {
05005   uint32_t tmpoptions = hi2c->XferOptions;
05006   uint32_t treatdmanack = 0U;
05007
05008   /* Process locked */
05009   __HAL_LOCK(hi2c);
05010
05011   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05012   {
05013     /* Check that I2C transfer finished */
05014     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05015     /* Mean XferCount == 0 */
05016     /* So clear Flag NACKF only */
05017     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
05018         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
05019     {
05020       /* Split check of hdmarx, for MISRA compliance */
05021       if (hi2c->hdmarx != NULL)
05022       {
05023         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
05024         {
05025           if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
05026           {
05027             treatdmanack = 1U;
05028           }
05029         }
05030       }
05031
05032       /* Split check of hdmatx, for MISRA compliance  */
05033       if (hi2c->hdmatx != NULL)
05034       {
05035         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
05036         {
05037           if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
05038           {
05039             treatdmanack = 1U;
05040           }
05041         }
05042       }
05043
05044       if (treatdmanack == 1U)
05045       {
05046         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
05047         {
05048           /* Call I2C Listen complete process */
05049           I2C_ITListenCplt(hi2c, ITFlags);
05050         }
05051         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05052         {
05053           /* Clear NACK Flag */
05054           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05055
05056           /* Flush TX register */
05057           I2C_Flush_TXDR(hi2c);
05058
05059           /* Last Byte is Transmitted */
05060           /* Call I2C Slave Sequential complete process */
05061           I2C_ITSlaveSeqCplt(hi2c);
05062         }
05063         else
05064         {
05065           /* Clear NACK Flag */
05066           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05067         }
05068       }
05069       else
05070       {
05071         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05072         /* Clear NACK Flag */
05073         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05074
05075         /* Set ErrorCode corresponding to a Non-Acknowledge */
05076         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05077
05078         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05079         {
05080           /* Call the corresponding callback to inform upper layer of End of Transfer */
05081           I2C_ITError(hi2c, hi2c->ErrorCode);
05082         }
05083       }
05084     }
05085     else
05086     {
05087       /* Only Clear NACK Flag, no DMA treatment is pending */
05088       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05089     }
05090   }
05091   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05092   {
05093     I2C_ITAddrCplt(hi2c, ITFlags);
05094   }
05095   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05096   {
05097     /* Call I2C Slave complete process */
05098     I2C_ITSlaveCplt(hi2c, ITFlags);
05099   }
05100   else
05101   {
05102     /* Nothing to do */
05103   }
05104
05105   /* Process Unlocked */
05106   __HAL_UNLOCK(hi2c);
05107
05108   return HAL_OK;
05109 }
05110
05111 /**
05112   * @brief  Master sends target device address followed by internal memory address for write request.
05113   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05114   *                the configuration information for the specified I2C.
05115   * @param  DevAddress Target device address: The device 7 bits address value
05116   *         in datasheet must be shifted to the left before calling the interface
05117   * @param  MemAddress Internal memory address
05118   * @param  MemAddSize Size of internal memory address
05119   * @param  Timeout Timeout duration
05120   * @param  Tickstart Tick start value
05121   * @retval HAL status
05122   */
05123 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
05124 {
05125   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
05126
05127   /* Wait until TXIS flag is set */
05128   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05129   {
05130     return HAL_ERROR;
05131   }
05132
05133   /* If Memory address size is 8Bit */
05134   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05135   {
05136     /* Send Memory Address */
05137     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05138   }
05139   /* If Memory address size is 16Bit */
05140   else
05141   {
05142     /* Send MSB of Memory Address */
05143     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05144
05145     /* Wait until TXIS flag is set */
05146     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05147     {
05148       return HAL_ERROR;
05149     }
05150
05151     /* Send LSB of Memory Address */
05152     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05153   }
05154
05155   /* Wait until TCR flag is set */
05156   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
05157   {
05158     return HAL_ERROR;
05159   }
05160
05161   return HAL_OK;
05162 }
05163
05164 /**
05165   * @brief  Master sends target device address followed by internal memory address for read request.
05166   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05167   *                the configuration information for the specified I2C.
05168   * @param  DevAddress Target device address: The device 7 bits address value
05169   *         in datasheet must be shifted to the left before calling the interface
05170   * @param  MemAddress Internal memory address
05171   * @param  MemAddSize Size of internal memory address
05172   * @param  Timeout Timeout duration
05173   * @param  Tickstart Tick start value
05174   * @retval HAL status
05175   */
05176 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
05177 {
05178   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
05179
05180   /* Wait until TXIS flag is set */
05181   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05182   {
05183     return HAL_ERROR;
05184   }
05185
05186   /* If Memory address size is 8Bit */
05187   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05188   {
05189     /* Send Memory Address */
05190     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05191   }
05192   /* If Memory address size is 16Bit */
05193   else
05194   {
05195     /* Send MSB of Memory Address */
05196     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05197
05198     /* Wait until TXIS flag is set */
05199     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05200     {
05201       return HAL_ERROR;
05202     }
05203
05204     /* Send LSB of Memory Address */
05205     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05206   }
05207
05208   /* Wait until TC flag is set */
05209   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
05210   {
05211     return HAL_ERROR;
05212   }
05213
05214   return HAL_OK;
05215 }
05216
05217 /**
05218   * @brief  I2C Address complete process callback.
05219   * @param  hi2c I2C handle.
05220   * @param  ITFlags Interrupt flags to handle.
05221   * @retval None
05222   */
05223 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05224 {
05225   uint8_t transferdirection;
05226   uint16_t slaveaddrcode;
05227   uint16_t ownadd1code;
05228   uint16_t ownadd2code;
05229
05230   /* Prevent unused argument(s) compilation warning */
05231   UNUSED(ITFlags);
05232
05233   /* In case of Listen state, need to inform upper layer of address match code event */
05234   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
05235   {
05236     transferdirection = I2C_GET_DIR(hi2c);
05237     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
05238     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
05239     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
05240
05241     /* If 10bits addressing mode is selected */
05242     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
05243     {
05244       if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
05245       {
05246         slaveaddrcode = ownadd1code;
05247         hi2c->AddrEventCount++;
05248         if (hi2c->AddrEventCount == 2U)
05249         {
05250           /* Reset Address Event counter */
05251           hi2c->AddrEventCount = 0U;
05252
05253           /* Clear ADDR flag */
05254           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05255
05256           /* Process Unlocked */
05257           __HAL_UNLOCK(hi2c);
05258
05259           /* Call Slave Addr callback */
05260 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05261           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05262 #else
05263           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05264 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05265         }
05266       }
05267       else
05268       {
05269         slaveaddrcode = ownadd2code;
05270
05271         /* Disable ADDR Interrupts */
05272         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05273
05274         /* Process Unlocked */
05275         __HAL_UNLOCK(hi2c);
05276
05277         /* Call Slave Addr callback */
05278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05279         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05280 #else
05281         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05283       }
05284     }
05285     /* else 7 bits addressing mode is selected */
05286     else
05287     {
05288       /* Disable ADDR Interrupts */
05289       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05290
05291       /* Process Unlocked */
05292       __HAL_UNLOCK(hi2c);
05293
05294       /* Call Slave Addr callback */
05295 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05296       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05297 #else
05298       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05299 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05300     }
05301   }
05302   /* Else clear address flag only */
05303   else
05304   {
05305     /* Clear ADDR flag */
05306     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05307
05308     /* Process Unlocked */
05309     __HAL_UNLOCK(hi2c);
05310   }
05311 }
05312
05313 /**
05314   * @brief  I2C Master sequential complete process.
05315   * @param  hi2c I2C handle.
05316   * @retval None
05317   */
05318 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
05319 {
05320   /* Reset I2C handle mode */
05321   hi2c->Mode = HAL_I2C_MODE_NONE;
05322
05323   /* No Generate Stop, to permit restart mode */
05324   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
05325   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05326   {
05327     hi2c->State         = HAL_I2C_STATE_READY;
05328     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
05329     hi2c->XferISR       = NULL;
05330
05331     /* Disable Interrupts */
05332     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05333
05334     /* Process Unlocked */
05335     __HAL_UNLOCK(hi2c);
05336
05337     /* Call the corresponding callback to inform upper layer of End of Transfer */
05338 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05339     hi2c->MasterTxCpltCallback(hi2c);
05340 #else
05341     HAL_I2C_MasterTxCpltCallback(hi2c);
05342 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05343   }
05344   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
05345   else
05346   {
05347     hi2c->State         = HAL_I2C_STATE_READY;
05348     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
05349     hi2c->XferISR       = NULL;
05350
05351     /* Disable Interrupts */
05352     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05353
05354     /* Process Unlocked */
05355     __HAL_UNLOCK(hi2c);
05356
05357     /* Call the corresponding callback to inform upper layer of End of Transfer */
05358 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05359     hi2c->MasterRxCpltCallback(hi2c);
05360 #else
05361     HAL_I2C_MasterRxCpltCallback(hi2c);
05362 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05363   }
05364 }
05365
05366 /**
05367   * @brief  I2C Slave sequential complete process.
05368   * @param  hi2c I2C handle.
05369   * @retval None
05370   */
05371 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
05372 {
05373   /* Reset I2C handle mode */
05374   hi2c->Mode = HAL_I2C_MODE_NONE;
05375
05376   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
05377   {
05378     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
05379     hi2c->State         = HAL_I2C_STATE_LISTEN;
05380     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
05381
05382     /* Disable Interrupts */
05383     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05384
05385     /* Process Unlocked */
05386     __HAL_UNLOCK(hi2c);
05387
05388     /* Call the corresponding callback to inform upper layer of End of Transfer */
05389 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05390     hi2c->SlaveTxCpltCallback(hi2c);
05391 #else
05392     HAL_I2C_SlaveTxCpltCallback(hi2c);
05393 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05394   }
05395
05396   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
05397   {
05398     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
05399     hi2c->State         = HAL_I2C_STATE_LISTEN;
05400     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
05401
05402     /* Disable Interrupts */
05403     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05404
05405     /* Process Unlocked */
05406     __HAL_UNLOCK(hi2c);
05407
05408     /* Call the corresponding callback to inform upper layer of End of Transfer */
05409 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05410     hi2c->SlaveRxCpltCallback(hi2c);
05411 #else
05412     HAL_I2C_SlaveRxCpltCallback(hi2c);
05413 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05414   }
05415   else
05416   {
05417     /* Nothing to do */
05418   }
05419 }
05420
05421 /**
05422   * @brief  I2C Master complete process.
05423   * @param  hi2c I2C handle.
05424   * @param  ITFlags Interrupt flags to handle.
05425   * @retval None
05426   */
05427 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05428 {
05429   uint32_t tmperror;
05430
05431   /* Clear STOP Flag */
05432   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05433
05434   /* Clear Configuration Register 2 */
05435   I2C_RESET_CR2(hi2c);
05436
05437   /* Reset handle parameters */
05438   hi2c->PreviousState = I2C_STATE_NONE;
05439   hi2c->XferISR       = NULL;
05440   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
05441
05442   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
05443   {
05444     /* Clear NACK Flag */
05445     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05446
05447     /* Set acknowledge error code */
05448     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05449   }
05450
05451   /* Flush TX register */
05452   I2C_Flush_TXDR(hi2c);
05453
05454   /* Disable Interrupts */
05455   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
05456
05457   /* Store current volatile hi2c->ErrorCode, misra rule */
05458   tmperror = hi2c->ErrorCode;
05459
05460   /* Call the corresponding callback to inform upper layer of End of Transfer */
05461   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
05462   {
05463     /* Call the corresponding callback to inform upper layer of End of Transfer */
05464     I2C_ITError(hi2c, hi2c->ErrorCode);
05465   }
05466   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
05467   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05468   {
05469     hi2c->State = HAL_I2C_STATE_READY;
05470
05471     if (hi2c->Mode == HAL_I2C_MODE_MEM)
05472     {
05473       hi2c->Mode = HAL_I2C_MODE_NONE;
05474
05475       /* Process Unlocked */
05476       __HAL_UNLOCK(hi2c);
05477
05478       /* Call the corresponding callback to inform upper layer of End of Transfer */
05479 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05480       hi2c->MemTxCpltCallback(hi2c);
05481 #else
05482       HAL_I2C_MemTxCpltCallback(hi2c);
05483 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05484     }
05485     else
05486     {
05487       hi2c->Mode = HAL_I2C_MODE_NONE;
05488
05489       /* Process Unlocked */
05490       __HAL_UNLOCK(hi2c);
05491
05492       /* Call the corresponding callback to inform upper layer of End of Transfer */
05493 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05494       hi2c->MasterTxCpltCallback(hi2c);
05495 #else
05496       HAL_I2C_MasterTxCpltCallback(hi2c);
05497 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05498     }
05499   }
05500   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
05501   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05502   {
05503     hi2c->State = HAL_I2C_STATE_READY;
05504
05505     if (hi2c->Mode == HAL_I2C_MODE_MEM)
05506     {
05507       hi2c->Mode = HAL_I2C_MODE_NONE;
05508
05509       /* Process Unlocked */
05510       __HAL_UNLOCK(hi2c);
05511
05512       /* Call the corresponding callback to inform upper layer of End of Transfer */
05513 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05514       hi2c->MemRxCpltCallback(hi2c);
05515 #else
05516       HAL_I2C_MemRxCpltCallback(hi2c);
05517 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05518     }
05519     else
05520     {
05521       hi2c->Mode = HAL_I2C_MODE_NONE;
05522
05523       /* Process Unlocked */
05524       __HAL_UNLOCK(hi2c);
05525
05526       /* Call the corresponding callback to inform upper layer of End of Transfer */
05527 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05528       hi2c->MasterRxCpltCallback(hi2c);
05529 #else
05530       HAL_I2C_MasterRxCpltCallback(hi2c);
05531 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05532     }
05533   }
05534   else
05535   {
05536     /* Nothing to do */
05537   }
05538 }
05539
05540 /**
05541   * @brief  I2C Slave complete process.
05542   * @param  hi2c I2C handle.
05543   * @param  ITFlags Interrupt flags to handle.
05544   * @retval None
05545   */
05546 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05547 {
05548   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
05549   uint32_t tmpITFlags = ITFlags;
05550
05551   /* Clear STOP Flag */
05552   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05553
05554   /* Disable all interrupts */
05555   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
05556
05557   /* Disable Address Acknowledge */
05558   hi2c->Instance->CR2 |= I2C_CR2_NACK;
05559
05560   /* Clear Configuration Register 2 */
05561   I2C_RESET_CR2(hi2c);
05562
05563   /* Flush TX register */
05564   I2C_Flush_TXDR(hi2c);
05565
05566   /* If a DMA is ongoing, Update handle size context */
05567   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
05568   {
05569     if (hi2c->hdmatx != NULL)
05570     {
05571       hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
05572     }
05573   }
05574   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
05575   {
05576     if (hi2c->hdmarx != NULL)
05577     {
05578       hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
05579     }
05580   }
05581   else
05582   {
05583     /* Do nothing */
05584   }
05585
05586   /* Store Last receive data if any */
05587   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
05588   {
05589     /* Remove RXNE flag on temporary variable as read done */
05590     tmpITFlags &= ~I2C_FLAG_RXNE;
05591
05592     /* Read data from RXDR */
05593     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05594
05595     /* Increment Buffer pointer */
05596     hi2c->pBuffPtr++;
05597
05598     if ((hi2c->XferSize > 0U))
05599     {
05600       hi2c->XferSize--;
05601       hi2c->XferCount--;
05602     }
05603   }
05604
05605   /* All data are not transferred, so set error code accordingly */
05606   if (hi2c->XferCount != 0U)
05607   {
05608     /* Set ErrorCode corresponding to a Non-Acknowledge */
05609     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05610   }
05611
05612   hi2c->PreviousState = I2C_STATE_NONE;
05613   hi2c->Mode = HAL_I2C_MODE_NONE;
05614   hi2c->XferISR = NULL;
05615
05616   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
05617   {
05618     /* Call the corresponding callback to inform upper layer of End of Transfer */
05619     I2C_ITError(hi2c, hi2c->ErrorCode);
05620
05621     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05622     if (hi2c->State == HAL_I2C_STATE_LISTEN)
05623     {
05624       /* Call I2C Listen complete process */
05625       I2C_ITListenCplt(hi2c, tmpITFlags);
05626     }
05627   }
05628   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
05629   {
05630     /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
05631     I2C_ITSlaveSeqCplt(hi2c);
05632
05633     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
05634     hi2c->State = HAL_I2C_STATE_READY;
05635
05636     /* Process Unlocked */
05637     __HAL_UNLOCK(hi2c);
05638
05639     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05640 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05641     hi2c->ListenCpltCallback(hi2c);
05642 #else
05643     HAL_I2C_ListenCpltCallback(hi2c);
05644 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05645   }
05646   /* Call the corresponding callback to inform upper layer of End of Transfer */
05647   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05648   {
05649     hi2c->State = HAL_I2C_STATE_READY;
05650
05651     /* Process Unlocked */
05652     __HAL_UNLOCK(hi2c);
05653
05654     /* Call the corresponding callback to inform upper layer of End of Transfer */
05655 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05656     hi2c->SlaveRxCpltCallback(hi2c);
05657 #else
05658     HAL_I2C_SlaveRxCpltCallback(hi2c);
05659 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05660   }
05661   else
05662   {
05663     hi2c->State = HAL_I2C_STATE_READY;
05664
05665     /* Process Unlocked */
05666     __HAL_UNLOCK(hi2c);
05667
05668     /* Call the corresponding callback to inform upper layer of End of Transfer */
05669 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05670     hi2c->SlaveTxCpltCallback(hi2c);
05671 #else
05672     HAL_I2C_SlaveTxCpltCallback(hi2c);
05673 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05674   }
05675 }
05676
05677 /**
05678   * @brief  I2C Listen complete process.
05679   * @param  hi2c I2C handle.
05680   * @param  ITFlags Interrupt flags to handle.
05681   * @retval None
05682   */
05683 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05684 {
05685   /* Reset handle parameters */
05686   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
05687   hi2c->PreviousState = I2C_STATE_NONE;
05688   hi2c->State = HAL_I2C_STATE_READY;
05689   hi2c->Mode = HAL_I2C_MODE_NONE;
05690   hi2c->XferISR = NULL;
05691
05692   /* Store Last receive data if any */
05693   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
05694   {
05695     /* Read data from RXDR */
05696     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05697
05698     /* Increment Buffer pointer */
05699     hi2c->pBuffPtr++;
05700
05701     if ((hi2c->XferSize > 0U))
05702     {
05703       hi2c->XferSize--;
05704       hi2c->XferCount--;
05705
05706       /* Set ErrorCode corresponding to a Non-Acknowledge */
05707       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05708     }
05709   }
05710
05711   /* Disable all Interrupts*/
05712   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05713
05714   /* Clear NACK Flag */
05715   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05716
05717   /* Process Unlocked */
05718   __HAL_UNLOCK(hi2c);
05719
05720   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05721 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05722   hi2c->ListenCpltCallback(hi2c);
05723 #else
05724   HAL_I2C_ListenCpltCallback(hi2c);
05725 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05726 }
05727
05728 /**
05729   * @brief  I2C interrupts error process.
05730   * @param  hi2c I2C handle.
05731   * @param  ErrorCode Error code to handle.
05732   * @retval None
05733   */
05734 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
05735 {
05736   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
05737
05738   /* Reset handle parameters */
05739   hi2c->Mode          = HAL_I2C_MODE_NONE;
05740   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
05741   hi2c->XferCount     = 0U;
05742
05743   /* Set new error code */
05744   hi2c->ErrorCode |= ErrorCode;
05745
05746   /* Disable Interrupts */
05747   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
05748       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
05749       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
05750   {
05751     /* Disable all interrupts, except interrupts related to LISTEN state */
05752     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05753
05754     /* keep HAL_I2C_STATE_LISTEN if set */
05755     hi2c->State         = HAL_I2C_STATE_LISTEN;
05756     hi2c->PreviousState = I2C_STATE_NONE;
05757     hi2c->XferISR       = I2C_Slave_ISR_IT;
05758   }
05759   else
05760   {
05761     /* Disable all interrupts */
05762     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05763
05764     /* If state is an abort treatment on goind, don't change state */
05765     /* This change will be do later */
05766     if (hi2c->State != HAL_I2C_STATE_ABORT)
05767     {
05768       /* Set HAL_I2C_STATE_READY */
05769       hi2c->State         = HAL_I2C_STATE_READY;
05770     }
05771     hi2c->PreviousState = I2C_STATE_NONE;
05772     hi2c->XferISR       = NULL;
05773   }
05774
05775   /* Abort DMA TX transfer if any */
05776   if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
05777   {
05778     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05779
05780     if (hi2c->hdmatx != NULL)
05781     {
05782       /* Set the I2C DMA Abort callback :
05783        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
05784       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
05785
05786       /* Process Unlocked */
05787       __HAL_UNLOCK(hi2c);
05788
05789       /* Abort DMA TX */
05790       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
05791       {
05792         /* Call Directly XferAbortCallback function in case of error */
05793         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
05794       }
05795     }
05796   }
05797   /* Abort DMA RX transfer if any */
05798   else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
05799   {
05800     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
05801
05802     if (hi2c->hdmarx != NULL)
05803     {
05804       /* Set the I2C DMA Abort callback :
05805         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
05806       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
05807
05808       /* Process Unlocked */
05809       __HAL_UNLOCK(hi2c);
05810
05811       /* Abort DMA RX */
05812       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
05813       {
05814         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
05815         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
05816       }
05817     }
05818   }
05819   else if (hi2c->State == HAL_I2C_STATE_ABORT)
05820   {
05821     hi2c->State = HAL_I2C_STATE_READY;
05822
05823     /* Process Unlocked */
05824     __HAL_UNLOCK(hi2c);
05825
05826     /* Call the corresponding callback to inform upper layer of End of Transfer */
05827 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05828     hi2c->AbortCpltCallback(hi2c);
05829 #else
05830     HAL_I2C_AbortCpltCallback(hi2c);
05831 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05832   }
05833   else
05834   {
05835     /* Process Unlocked */
05836     __HAL_UNLOCK(hi2c);
05837
05838     /* Call the corresponding callback to inform upper layer of End of Transfer */
05839 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05840     hi2c->ErrorCallback(hi2c);
05841 #else
05842     HAL_I2C_ErrorCallback(hi2c);
05843 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05844   }
05845 }
05846
05847 /**
05848   * @brief  I2C Tx data register flush process.
05849   * @param  hi2c I2C handle.
05850   * @retval None
05851   */
05852 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
05853 {
05854   /* If a pending TXIS flag is set */
05855   /* Write a dummy data in TXDR to clear it */
05856   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
05857   {
05858     hi2c->Instance->TXDR = 0x00U;
05859   }
05860
05861   /* Flush TX register if not empty */
05862   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
05863   {
05864     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
05865   }
05866 }
05867
05868 /**
05869   * @brief  DMA I2C master transmit process complete callback.
05870   * @param  hdma DMA handle
05871   * @retval None
05872   */
05873 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
05874 {
05875   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05876
05877   /* Disable DMA Request */
05878   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05879
05880   /* If last transfer, enable STOP interrupt */
05881   if (hi2c->XferCount == 0U)
05882   {
05883     /* Enable STOP interrupt */
05884     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05885   }
05886   /* else prepare a new DMA transfer and enable TCReload interrupt */
05887   else
05888   {
05889     /* Update Buffer pointer */
05890     hi2c->pBuffPtr += hi2c->XferSize;
05891
05892     /* Set the XferSize to transfer */
05893     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05894     {
05895       hi2c->XferSize = MAX_NBYTE_SIZE;
05896     }
05897     else
05898     {
05899       hi2c->XferSize = hi2c->XferCount;
05900     }
05901
05902     /* Enable the DMA stream or channel depends on Instance */
05903     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
05904     {
05905       /* Call the corresponding callback to inform upper layer of End of Transfer */
05906       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
05907     }
05908     else
05909     {
05910       /* Enable TC interrupts */
05911       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
05912     }
05913   }
05914 }
05915
05916 /**
05917   * @brief  DMA I2C slave transmit process complete callback.
05918   * @param  hdma DMA handle
05919   * @retval None
05920   */
05921 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
05922 {
05923   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05924   uint32_t tmpoptions = hi2c->XferOptions;
05925
05926   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
05927   {
05928     /* Disable DMA Request */
05929     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05930
05931     /* Last Byte is Transmitted */
05932     /* Call I2C Slave Sequential complete process */
05933     I2C_ITSlaveSeqCplt(hi2c);
05934   }
05935   else
05936   {
05937     /* No specific action, Master fully manage the generation of STOP condition */
05938     /* Mean that this generation can arrive at any time, at the end or during DMA process */
05939     /* So STOP condition should be manage through Interrupt treatment */
05940   }
05941 }
05942
05943 /**
05944   * @brief DMA I2C master receive process complete callback.
05945   * @param  hdma DMA handle
05946   * @retval None
05947   */
05948 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
05949 {
05950   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05951
05952   /* Disable DMA Request */
05953   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
05954
05955   /* If last transfer, enable STOP interrupt */
05956   if (hi2c->XferCount == 0U)
05957   {
05958     /* Enable STOP interrupt */
05959     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05960   }
05961   /* else prepare a new DMA transfer and enable TCReload interrupt */
05962   else
05963   {
05964     /* Update Buffer pointer */
05965     hi2c->pBuffPtr += hi2c->XferSize;
05966
05967     /* Set the XferSize to transfer */
05968     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05969     {
05970       hi2c->XferSize = MAX_NBYTE_SIZE;
05971     }
05972     else
05973     {
05974       hi2c->XferSize = hi2c->XferCount;
05975     }
05976
05977     /* Enable the DMA stream or channel depends on Instance */
05978     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
05979     {
05980       /* Call the corresponding callback to inform upper layer of End of Transfer */
05981       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
05982     }
05983     else
05984     {
05985       /* Enable TC interrupts */
05986       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
05987     }
05988   }
05989 }
05990
05991 /**
05992   * @brief  DMA I2C slave receive process complete callback.
05993   * @param  hdma DMA handle
05994   * @retval None
05995   */
05996 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
05997 {
05998   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05999   uint32_t tmpoptions = hi2c->XferOptions;
06000
06001   if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
06002       (tmpoptions != I2C_NO_OPTION_FRAME))
06003   {
06004     /* Disable DMA Request */
06005     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06006
06007     /* Call I2C Slave Sequential complete process */
06008     I2C_ITSlaveSeqCplt(hi2c);
06009   }
06010   else
06011   {
06012     /* No specific action, Master fully manage the generation of STOP condition */
06013     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06014     /* So STOP condition should be manage through Interrupt treatment */
06015   }
06016 }
06017
06018 /**
06019   * @brief  DMA I2C communication error callback.
06020   * @param hdma DMA handle
06021   * @retval None
06022   */
06023 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
06024 {
06025   uint32_t treatdmaerror = 0U;
06026   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
06027
06028   if (hi2c->hdmatx != NULL)
06029   {
06030     if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
06031     {
06032       treatdmaerror = 1U;
06033     }
06034   }
06035
06036   if (hi2c->hdmarx != NULL)
06037   {
06038     if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
06039     {
06040       treatdmaerror = 1U;
06041     }
06042   }
06043
06044   /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
06045   if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
06046   {
06047     /* Disable Acknowledge */
06048     hi2c->Instance->CR2 |= I2C_CR2_NACK;
06049
06050     /* Call the corresponding callback to inform upper layer of End of Transfer */
06051     I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06052   }
06053 }
06054
06055 /**
06056   * @brief DMA I2C communication abort callback
06057   *        (To be called at end of DMA Abort procedure).
06058   * @param hdma DMA handle.
06059   * @retval None
06060   */
06061 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
06062 {
06063   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
06064
06065   /* Reset AbortCpltCallback */
06066   hi2c->hdmatx->XferAbortCallback = NULL;
06067   hi2c->hdmarx->XferAbortCallback = NULL;
06068
06069   /* Check if come from abort from user */
06070   if (hi2c->State == HAL_I2C_STATE_ABORT)
06071   {
06072     hi2c->State = HAL_I2C_STATE_READY;
06073
06074     /* Call the corresponding callback to inform upper layer of End of Transfer */
06075 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06076     hi2c->AbortCpltCallback(hi2c);
06077 #else
06078     HAL_I2C_AbortCpltCallback(hi2c);
06079 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06080   }
06081   else
06082   {
06083     /* Call the corresponding callback to inform upper layer of End of Transfer */
06084 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06085     hi2c->ErrorCallback(hi2c);
06086 #else
06087     HAL_I2C_ErrorCallback(hi2c);
06088 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06089   }
06090 }
06091
06092 /**
06093   * @brief  This function handles I2C Communication Timeout.
06094   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06095   *                the configuration information for the specified I2C.
06096   * @param  Flag Specifies the I2C flag to check.
06097   * @param  Status The new Flag status (SET or RESET).
06098   * @param  Timeout Timeout duration
06099   * @param  Tickstart Tick start value
06100   * @retval HAL status
06101   */
06102 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
06103 {
06104   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
06105   {
06106     /* Check for the Timeout */
06107     if (Timeout != HAL_MAX_DELAY)
06108     {
06109       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06110       {
06111         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06112         hi2c->State = HAL_I2C_STATE_READY;
06113         hi2c->Mode = HAL_I2C_MODE_NONE;
06114
06115         /* Process Unlocked */
06116         __HAL_UNLOCK(hi2c);
06117         return HAL_ERROR;
06118       }
06119     }
06120   }
06121   return HAL_OK;
06122 }
06123
06124 /**
06125   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
06126   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06127   *                the configuration information for the specified I2C.
06128   * @param  Timeout Timeout duration
06129   * @param  Tickstart Tick start value
06130   * @retval HAL status
06131   */
06132 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06133 {
06134   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
06135   {
06136     /* Check if a NACK is detected */
06137     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06138     {
06139       return HAL_ERROR;
06140     }
06141
06142     /* Check for the Timeout */
06143     if (Timeout != HAL_MAX_DELAY)
06144     {
06145       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06146       {
06147         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06148         hi2c->State = HAL_I2C_STATE_READY;
06149         hi2c->Mode = HAL_I2C_MODE_NONE;
06150
06151         /* Process Unlocked */
06152         __HAL_UNLOCK(hi2c);
06153
06154         return HAL_ERROR;
06155       }
06156     }
06157   }
06158   return HAL_OK;
06159 }
06160
06161 /**
06162   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
06163   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06164   *                the configuration information for the specified I2C.
06165   * @param  Timeout Timeout duration
06166   * @param  Tickstart Tick start value
06167   * @retval HAL status
06168   */
06169 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06170 {
06171   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06172   {
06173     /* Check if a NACK is detected */
06174     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06175     {
06176       return HAL_ERROR;
06177     }
06178
06179     /* Check for the Timeout */
06180     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06181     {
06182       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06183       hi2c->State = HAL_I2C_STATE_READY;
06184       hi2c->Mode = HAL_I2C_MODE_NONE;
06185
06186       /* Process Unlocked */
06187       __HAL_UNLOCK(hi2c);
06188
06189       return HAL_ERROR;
06190     }
06191   }
06192   return HAL_OK;
06193 }
06194
06195 /**
06196   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
06197   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06198   *                the configuration information for the specified I2C.
06199   * @param  Timeout Timeout duration
06200   * @param  Tickstart Tick start value
06201   * @retval HAL status
06202   */
06203 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06204 {
06205   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
06206   {
06207     /* Check if a NACK is detected */
06208     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06209     {
06210       return HAL_ERROR;
06211     }
06212
06213     /* Check if a STOPF is detected */
06214     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
06215     {
06216       /* Check if an RXNE is pending */
06217       /* Store Last receive data if any */
06218       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
06219       {
06220         /* Return HAL_OK */
06221         /* The Reading of data from RXDR will be done in caller function */
06222         return HAL_OK;
06223       }
06224       else
06225       {
06226         /* Clear STOP Flag */
06227         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06228
06229         /* Clear Configuration Register 2 */
06230         I2C_RESET_CR2(hi2c);
06231
06232         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
06233         hi2c->State = HAL_I2C_STATE_READY;
06234         hi2c->Mode = HAL_I2C_MODE_NONE;
06235
06236         /* Process Unlocked */
06237         __HAL_UNLOCK(hi2c);
06238
06239         return HAL_ERROR;
06240       }
06241     }
06242
06243     /* Check for the Timeout */
06244     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06245     {
06246       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06247       hi2c->State = HAL_I2C_STATE_READY;
06248
06249       /* Process Unlocked */
06250       __HAL_UNLOCK(hi2c);
06251
06252       return HAL_ERROR;
06253     }
06254   }
06255   return HAL_OK;
06256 }
06257
06258 /**
06259   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
06260   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06261   *                the configuration information for the specified I2C.
06262   * @param  Timeout Timeout duration
06263   * @param  Tickstart Tick start value
06264   * @retval HAL status
06265   */
06266 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06267 {
06268   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
06269   {
06270     /* Wait until STOP Flag is reset */
06271     /* AutoEnd should be initiate after AF */
06272     while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06273     {
06274       /* Check for the Timeout */
06275       if (Timeout != HAL_MAX_DELAY)
06276       {
06277         if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06278         {
06279           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06280           hi2c->State = HAL_I2C_STATE_READY;
06281           hi2c->Mode = HAL_I2C_MODE_NONE;
06282
06283           /* Process Unlocked */
06284           __HAL_UNLOCK(hi2c);
06285
06286           return HAL_ERROR;
06287         }
06288       }
06289     }
06290
06291     /* Clear NACKF Flag */
06292     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06293
06294     /* Clear STOP Flag */
06295     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06296
06297     /* Flush TX register */
06298     I2C_Flush_TXDR(hi2c);
06299
06300     /* Clear Configuration Register 2 */
06301     I2C_RESET_CR2(hi2c);
06302
06303     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06304     hi2c->State = HAL_I2C_STATE_READY;
06305     hi2c->Mode = HAL_I2C_MODE_NONE;
06306
06307     /* Process Unlocked */
06308     __HAL_UNLOCK(hi2c);
06309
06310     return HAL_ERROR;
06311   }
06312   return HAL_OK;
06313 }
06314
06315 /**
06316   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
06317   * @param  hi2c I2C handle.
06318   * @param  DevAddress Specifies the slave address to be programmed.
06319   * @param  Size Specifies the number of bytes to be programmed.
06320   *   This parameter must be a value between 0 and 255.
06321   * @param  Mode New state of the I2C START condition generation.
06322   *   This parameter can be one of the following values:
06323   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
06324   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
06325   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
06326   * @param  Request New state of the I2C START condition generation.
06327   *   This parameter can be one of the following values:
06328   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
06329   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
06330   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
06331   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
06332   * @retval None
06333   */
06334 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
06335 {
06336   /* Check the parameters */
06337   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
06338   assert_param(IS_TRANSFER_MODE(Mode));
06339   assert_param(IS_TRANSFER_REQUEST(Request));
06340
06341   /* update CR2 register */
06342   MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
06343              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
06344 }
06345
06346 /**
06347   * @brief  Manage the enabling of Interrupts.
06348   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06349   *                the configuration information for the specified I2C.
06350   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
06351   * @retval None
06352   */
06353 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
06354 {
06355   uint32_t tmpisr = 0U;
06356
06357   if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
06358       (hi2c->XferISR == I2C_Slave_ISR_DMA))
06359   {
06360     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06361     {
06362       /* Enable ERR, STOP, NACK and ADDR interrupts */
06363       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06364     }
06365
06366     if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
06367     {
06368       /* Enable ERR and NACK interrupts */
06369       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
06370     }
06371
06372     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06373     {
06374       /* Enable STOP interrupts */
06375       tmpisr |= I2C_IT_STOPI;
06376     }
06377
06378     if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
06379     {
06380       /* Enable TC interrupts */
06381       tmpisr |= I2C_IT_TCI;
06382     }
06383   }
06384   else
06385   {
06386     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06387     {
06388       /* Enable ERR, STOP, NACK, and ADDR interrupts */
06389       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06390     }
06391
06392     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
06393     {
06394       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
06395       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
06396     }
06397
06398     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
06399     {
06400       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
06401       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
06402     }
06403
06404     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06405     {
06406       /* Enable STOP interrupts */
06407       tmpisr |= I2C_IT_STOPI;
06408     }
06409   }
06410
06411   /* Enable interrupts only at the end */
06412   /* to avoid the risk of I2C interrupt handle execution before */
06413   /* all interrupts requested done */
06414   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
06415 }
06416
06417 /**
06418   * @brief  Manage the disabling of Interrupts.
06419   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06420   *                the configuration information for the specified I2C.
06421   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
06422   * @retval None
06423   */
06424 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
06425 {
06426   uint32_t tmpisr = 0U;
06427
06428   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
06429   {
06430     /* Disable TC and TXI interrupts */
06431     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
06432
06433     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
06434     {
06435       /* Disable NACK and STOP interrupts */
06436       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06437     }
06438   }
06439
06440   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
06441   {
06442     /* Disable TC and RXI interrupts */
06443     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
06444
06445     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
06446     {
06447       /* Disable NACK and STOP interrupts */
06448       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06449     }
06450   }
06451
06452   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06453   {
06454     /* Disable ADDR, NACK and STOP interrupts */
06455     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06456   }
06457
06458   if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
06459   {
06460     /* Enable ERR and NACK interrupts */
06461     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
06462   }
06463
06464   if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06465   {
06466     /* Enable STOP interrupts */
06467     tmpisr |= I2C_IT_STOPI;
06468   }
06469
06470   if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
06471   {
06472     /* Enable TC interrupts */
06473     tmpisr |= I2C_IT_TCI;
06474   }
06475
06476   /* Disable interrupts only at the end */
06477   /* to avoid a breaking situation like at "t" time */
06478   /* all disable interrupts request are not done */
06479   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
06480 }
06481
06482 /**
06483   * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
06484   * @param  hi2c I2C handle.
06485   * @retval None
06486   */
06487 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
06488 {
06489   /* if user set XferOptions to I2C_OTHER_FRAME            */
06490   /* it request implicitly to generate a restart condition */
06491   /* set XferOptions to I2C_FIRST_FRAME                    */
06492   if (hi2c->XferOptions == I2C_OTHER_FRAME)
06493   {
06494     hi2c->XferOptions = I2C_FIRST_FRAME;
06495   }
06496   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
06497   /* it request implicitly to generate a restart condition    */
06498   /* then generate a stop condition at the end of transfer    */
06499   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
06500   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
06501   {
06502     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
06503   }
06504   else
06505   {
06506     /* Nothing to do */
06507   }
06508 }
06509
06510 /**
06511   * @}
06512   */
06513
06514 #endif /* HAL_I2C_MODULE_ENABLED */
06515 /**
06516   * @}
06517   */
06518
06519 /**
06520   * @}
06521   */
06522
06523 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c.h Source File

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stm32h7xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_I2C_H
00022 #define STM32H7xx_HAL_I2C_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2C
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup I2C_Exported_Types I2C Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00045   * @brief  I2C Configuration Structure definition
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00051                                   This parameter calculated by referring to I2C initialization
00052                                          section in Reference manual */
00053
00054   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00055                                   This parameter can be a 7-bit or 10-bit address. */
00056
00057   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00058                                   This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00059
00060   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00061                                   This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00062
00063   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00064                                   This parameter can be a 7-bit address. */
00065
00066   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00067                                   This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00068
00069   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00070                                   This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00071
00072   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00073                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00074
00075 } I2C_InitTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HAL_state_structure_definition HAL state structure definition
00082   * @brief  HAL State structure definition
00083   * @note  HAL I2C State value coding follow below described bitmap :\n
00084   *          b7-b6  Error information\n
00085   *             00 : No Error\n
00086   *             01 : Abort (Abort user request on going)\n
00087   *             10 : Timeout\n
00088   *             11 : Error\n
00089   *          b5     Peripheral initialization status\n
00090   *             0  : Reset (peripheral not initialized)\n
00091   *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
00092   *          b4     (not used)\n
00093   *             x  : Should be set to 0\n
00094   *          b3\n
00095   *             0  : Ready or Busy (No Listen mode ongoing)\n
00096   *             1  : Listen (peripheral in Address Listen Mode)\n
00097   *          b2     Intrinsic process state\n
00098   *             0  : Ready\n
00099   *             1  : Busy (peripheral busy with some configuration or internal operations)\n
00100   *          b1     Rx state\n
00101   *             0  : Ready (no Rx operation ongoing)\n
00102   *             1  : Busy (Rx operation ongoing)\n
00103   *          b0     Tx state\n
00104   *             0  : Ready (no Tx operation ongoing)\n
00105   *             1  : Busy (Tx operation ongoing)
00106   * @{
00107   */
00108 typedef enum
00109 {
00110   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00111   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00112   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00113   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00114   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00115   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00116   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00117                                                  process is ongoing                         */
00118   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00119                                                  process is ongoing                         */
00120   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00121   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00122   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00123
00124 } HAL_I2C_StateTypeDef;
00125
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00131   * @brief  HAL Mode structure definition
00132   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00133   *          b7     (not used)\n
00134   *             x  : Should be set to 0\n
00135   *          b6\n
00136   *             0  : None\n
00137   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00138   *          b5\n
00139   *             0  : None\n
00140   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00141   *          b4\n
00142   *             0  : None\n
00143   *             1  : Master (HAL I2C communication is in Master Mode)\n
00144   *          b3-b2-b1-b0  (not used)\n
00145   *             xxxx : Should be set to 0000
00146   * @{
00147   */
00148 typedef enum
00149 {
00150   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00151   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00152   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00153   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00154
00155 } HAL_I2C_ModeTypeDef;
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00162   * @brief  I2C Error Code definition
00163   * @{
00164   */
00165 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00166 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00167 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00168 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00169 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00170 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00171 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00172 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00173 #define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
00174 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00175 #define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00176 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00177 #define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00183   * @brief  I2C handle Structure definition
00184   * @{
00185   */
00186 typedef struct __I2C_HandleTypeDef
00187 {
00188   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00189
00190   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00191
00192   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00193
00194   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00195
00196   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00197
00198   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00199                                                   be a value of @ref I2C_XFEROPTIONS */
00200
00201   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00202
00203   HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
00204
00205   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00206
00207   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00208
00209   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00210
00211   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00212
00213   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00214
00215   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00216
00217   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00218
00219 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00220   void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
00221   void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
00222   void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
00223   void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
00224   void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
00225   void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
00226   void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
00227   void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
00228   void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
00229
00230   void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
00231
00232   void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
00233   void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
00234
00235 #endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
00236 } I2C_HandleTypeDef;
00237
00238 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00239 /**
00240   * @brief  HAL I2C Callback ID enumeration definition
00241   */
00242 typedef enum
00243 {
00244   HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
00245   HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
00246   HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
00247   HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
00248   HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
00249   HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
00250   HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
00251   HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
00252   HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
00253
00254   HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
00255   HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
00256
00257 } HAL_I2C_CallbackIDTypeDef;
00258
00259 /**
00260   * @brief  HAL I2C Callback pointer definition
00261   */
00262 typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
00263 typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
00264
00265 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273 /* Exported constants --------------------------------------------------------*/
00274
00275 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00276   * @{
00277   */
00278
00279 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00280   * @{
00281   */
00282 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00283 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00284 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00285 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00286 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00287 #define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
00288
00289 /* List of XferOptions in usage of :
00290  * 1- Restart condition in all use cases (direction change or not)
00291  */
00292 #define  I2C_OTHER_FRAME                (0x000000AAU)
00293 #define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00299   * @{
00300   */
00301 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00302 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00308   * @{
00309   */
00310 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00311 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00317   * @{
00318   */
00319 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00320 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00321 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00322 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00323 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00324 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00325 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00326 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00332   * @{
00333   */
00334 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00335 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00341   * @{
00342   */
00343 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00344 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00350   * @{
00351   */
00352 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00353 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
00359   * @{
00360   */
00361 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00362 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00368   * @{
00369   */
00370 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00371 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00372 #define  I2C_SOFTEND_MODE               (0x00000000U)
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00378   * @{
00379   */
00380 #define  I2C_NO_STARTSTOP               (0x00000000U)
00381 #define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
00382 #define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00383 #define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00389   * @brief I2C Interrupt definition
00390   *        Elements values convention: 0xXXXXXXXX
00391   *           - XXXXXXXX  : Interrupt control mask
00392   * @{
00393   */
00394 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00395 #define I2C_IT_TCI                      I2C_CR1_TCIE
00396 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00397 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00398 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00399 #define I2C_IT_RXI                      I2C_CR1_RXIE
00400 #define I2C_IT_TXI                      I2C_CR1_TXIE
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup I2C_Flag_definition I2C Flag definition
00406   * @{
00407   */
00408 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00409 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00410 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00411 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00412 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00413 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00414 #define I2C_FLAG_TC                     I2C_ISR_TC
00415 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00416 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00417 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00418 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00419 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00420 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00421 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00422 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00423 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Exported macros -----------------------------------------------------------*/
00433
00434 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00435   * @{
00436   */
00437
00438 /** @brief Reset I2C handle state.
00439   * @param  __HANDLE__ specifies the I2C Handle.
00440   * @retval None
00441   */
00442 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00443 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
00444                                                                     (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
00445                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00446                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00447                                                                   } while(0)
00448 #else
00449 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00450 #endif
00451
00452 /** @brief  Enable the specified I2C interrupt.
00453   * @param  __HANDLE__ specifies the I2C Handle.
00454   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00455   *        This parameter can be one of the following values:
00456   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00457   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00458   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00459   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00460   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00461   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00462   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00463   *
00464   * @retval None
00465   */
00466 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00467
00468 /** @brief  Disable the specified I2C interrupt.
00469   * @param  __HANDLE__ specifies the I2C Handle.
00470   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00471   *        This parameter can be one of the following values:
00472   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00473   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00474   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00475   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00476   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00477   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00478   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00479   *
00480   * @retval None
00481   */
00482 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00483
00484 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00485   * @param  __HANDLE__ specifies the I2C Handle.
00486   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00487   *          This parameter can be one of the following values:
00488   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00489   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00490   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00491   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00492   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00493   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00494   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00495   *
00496   * @retval The new state of __INTERRUPT__ (SET or RESET).
00497   */
00498 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00499
00500 /** @brief  Check whether the specified I2C flag is set or not.
00501   * @param  __HANDLE__ specifies the I2C Handle.
00502   * @param  __FLAG__ specifies the flag to check.
00503   *        This parameter can be one of the following values:
00504   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00505   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00506   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00507   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00508   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00509   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00510   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00511   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00512   *            @arg @ref I2C_FLAG_BERR    Bus error
00513   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00514   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00515   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00516   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00517   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00518   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00519   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00520   *
00521   * @retval The new state of __FLAG__ (SET or RESET).
00522   */
00523 #define I2C_FLAG_MASK  (0x0001FFFFU)
00524 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00525
00526 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00527   * @param  __HANDLE__ specifies the I2C Handle.
00528   * @param  __FLAG__ specifies the flag to clear.
00529   *          This parameter can be any combination of the following values:
00530   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00531   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00532   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00533   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00534   *            @arg @ref I2C_FLAG_BERR    Bus error
00535   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00536   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00537   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00538   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00539   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00540   *
00541   * @retval None
00542   */
00543 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
00544                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00545
00546 /** @brief  Enable the specified I2C peripheral.
00547   * @param  __HANDLE__ specifies the I2C Handle.
00548   * @retval None
00549   */
00550 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00551
00552 /** @brief  Disable the specified I2C peripheral.
00553   * @param  __HANDLE__ specifies the I2C Handle.
00554   * @retval None
00555   */
00556 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00557
00558 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00559   * @param  __HANDLE__ specifies the I2C Handle.
00560   * @retval None
00561   */
00562 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00563 /**
00564   * @}
00565   */
00566
00567 /* Include I2C HAL Extended module */
00568 #include "stm32h7xx_hal_i2c_ex.h"
00569
00570 /* Exported functions --------------------------------------------------------*/
00571 /** @addtogroup I2C_Exported_Functions
00572   * @{
00573   */
00574
00575 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00576   * @{
00577   */
00578 /* Initialization and de-initialization functions******************************/
00579 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00580 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
00581 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00582 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00583
00584 /* Callbacks Register/UnRegister functions  ***********************************/
00585 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00586 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
00587 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
00588
00589 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
00590 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
00591 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00592 /**
00593   * @}
00594   */
00595
00596 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00597   * @{
00598   */
00599 /* IO operation functions  ****************************************************/
00600 /******* Blocking mode: Polling */
00601 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00602 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00603 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00604 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00605 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00606 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00607 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00608
00609 /******* Non-Blocking mode: Interrupt */
00610 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00611 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00612 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00613 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00614 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00615 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00616
00617 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00618 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00619 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00620 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00621 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00622 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00623 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00624
00625 /******* Non-Blocking mode: DMA */
00626 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00627 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00628 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00629 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00630 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00631 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00632
00633 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00634 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00635 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00636 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00637 /**
00638   * @}
00639   */
00640
00641 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00642  * @{
00643  */
00644 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00645 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00646 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00647 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00648 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00649 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00650 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00651 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00652 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00653 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00654 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00655 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00656 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00657 /**
00658   * @}
00659   */
00660
00661 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00662   * @{
00663   */
00664 /* Peripheral State, Mode and Error functions  *********************************/
00665 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00666 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00667 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00668
00669 /**
00670   * @}
00671   */
00672
00673 /**
00674   * @}
00675   */
00676
00677 /* Private constants ---------------------------------------------------------*/
00678 /** @defgroup I2C_Private_Constants I2C Private Constants
00679   * @{
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /* Private macros ------------------------------------------------------------*/
00687 /** @defgroup I2C_Private_Macro I2C Private Macros
00688   * @{
00689   */
00690
00691 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00692                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00693
00694 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00695                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00696
00697 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00698                                          ((MASK) == I2C_OA2_MASK01) || \
00699                                          ((MASK) == I2C_OA2_MASK02) || \
00700                                          ((MASK) == I2C_OA2_MASK03) || \
00701                                          ((MASK) == I2C_OA2_MASK04) || \
00702                                          ((MASK) == I2C_OA2_MASK05) || \
00703                                          ((MASK) == I2C_OA2_MASK06) || \
00704                                          ((MASK) == I2C_OA2_MASK07))
00705
00706 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00707                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00708
00709 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00710                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00711
00712 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00713                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00714
00715 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00716                                          ((MODE) == I2C_AUTOEND_MODE) || \
00717                                          ((MODE) == I2C_SOFTEND_MODE))
00718
00719 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00720                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00721                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00722                                          ((REQUEST) == I2C_NO_STARTSTOP))
00723
00724 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00725                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00726                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00727                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00728                                                    ((REQUEST) == I2C_LAST_FRAME)           || \
00729                                                    ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
00730                                                    IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00731
00732 #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
00733                                                         ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
00734
00735 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00736
00737 #define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
00738 #define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
00739 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00740 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
00741 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
00742
00743 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00744 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00745
00746 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00747 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00748
00749 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00750                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00751
00752 #define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
00753 #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00754 /**
00755   * @}
00756   */
00757
00758 /* Private Functions ---------------------------------------------------------*/
00759 /** @defgroup I2C_Private_Functions I2C Private Functions
00760   * @{
00761   */
00762 /* Private functions are defined in stm32h7xx_hal_i2c.c file */
00763 /**
00764   * @}
00765   */
00766
00767 /**
00768   * @}
00769   */
00770
00771 /**
00772   * @}
00773   */
00774
00775 #ifdef __cplusplus
00776 }
00777 #endif
00778
00779
00780 #endif /* STM32H7xx_HAL_I2C_H */
00781
00782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c_ex.c Source File

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stm32h7xx_hal_i2c_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2C Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2C Extended peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                ##### I2C peripheral Extended features  #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the I2C interface for STM32H7xx
00016        devices contains the following additional features
00017
00018        (+) Possibility to disable or enable Analog Noise Filter
00019        (+) Use of a configured Digital Noise Filter
00020        (+) Disable or enable wakeup from Stop mode(s)
00021        (+) Disable or enable Fast Mode Plus
00022
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00026     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00027     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00028     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00029           (++) HAL_I2CEx_EnableWakeUp()
00030           (++) HAL_I2CEx_DisableWakeUp()
00031     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00032           (++) HAL_I2CEx_EnableFastModePlus()
00033           (++) HAL_I2CEx_DisableFastModePlus()
00034   @endverbatim
00035   ******************************************************************************
00036   * @attention
00037   *
00038   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00039   * All rights reserved.</center></h2>
00040   *
00041   * This software component is licensed by ST under BSD 3-Clause license,
00042   * the "License"; You may not use this file except in compliance with the
00043   * License. You may obtain a copy of the License at:
00044   *                        opensource.org/licenses/BSD-3-Clause
00045   *
00046   ******************************************************************************
00047   */
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32h7xx_hal.h"
00051
00052 /** @addtogroup STM32H7xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @defgroup I2CEx I2CEx
00057   * @brief I2C Extended HAL module driver
00058   * @{
00059   */
00060
00061 #ifdef HAL_I2C_MODULE_ENABLED
00062
00063 /* Private typedef -----------------------------------------------------------*/
00064 /* Private define ------------------------------------------------------------*/
00065 /* Private macro -------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068 /* Private functions ---------------------------------------------------------*/
00069
00070 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00071   * @{
00072   */
00073
00074 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00075   * @brief    Extended features functions
00076  *
00077 @verbatim
00078  ===============================================================================
00079                       ##### Extended features functions #####
00080  ===============================================================================
00081     [..] This section provides functions allowing to:
00082       (+) Configure Noise Filters
00083       (+) Configure Wake Up Feature
00084       (+) Configure Fast Mode Plus
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  Configure I2C Analog noise filter.
00092   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00093   *                the configuration information for the specified I2Cx peripheral.
00094   * @param  AnalogFilter New state of the Analog filter.
00095   * @retval HAL status
00096   */
00097 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00098 {
00099   /* Check the parameters */
00100   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00101   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00102
00103   if (hi2c->State == HAL_I2C_STATE_READY)
00104   {
00105     /* Process Locked */
00106     __HAL_LOCK(hi2c);
00107
00108     hi2c->State = HAL_I2C_STATE_BUSY;
00109
00110     /* Disable the selected I2C peripheral */
00111     __HAL_I2C_DISABLE(hi2c);
00112
00113     /* Reset I2Cx ANOFF bit */
00114     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00115
00116     /* Set analog filter bit*/
00117     hi2c->Instance->CR1 |= AnalogFilter;
00118
00119     __HAL_I2C_ENABLE(hi2c);
00120
00121     hi2c->State = HAL_I2C_STATE_READY;
00122
00123     /* Process Unlocked */
00124     __HAL_UNLOCK(hi2c);
00125
00126     return HAL_OK;
00127   }
00128   else
00129   {
00130     return HAL_BUSY;
00131   }
00132 }
00133
00134 /**
00135   * @brief  Configure I2C Digital noise filter.
00136   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00137   *                the configuration information for the specified I2Cx peripheral.
00138   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00139   * @retval HAL status
00140   */
00141 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00142 {
00143   uint32_t tmpreg;
00144
00145   /* Check the parameters */
00146   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00147   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00148
00149   if (hi2c->State == HAL_I2C_STATE_READY)
00150   {
00151     /* Process Locked */
00152     __HAL_LOCK(hi2c);
00153
00154     hi2c->State = HAL_I2C_STATE_BUSY;
00155
00156     /* Disable the selected I2C peripheral */
00157     __HAL_I2C_DISABLE(hi2c);
00158
00159     /* Get the old register value */
00160     tmpreg = hi2c->Instance->CR1;
00161
00162     /* Reset I2Cx DNF bits [11:8] */
00163     tmpreg &= ~(I2C_CR1_DNF);
00164
00165     /* Set I2Cx DNF coefficient */
00166     tmpreg |= DigitalFilter << 8U;
00167
00168     /* Store the new register value */
00169     hi2c->Instance->CR1 = tmpreg;
00170
00171     __HAL_I2C_ENABLE(hi2c);
00172
00173     hi2c->State = HAL_I2C_STATE_READY;
00174
00175     /* Process Unlocked */
00176     __HAL_UNLOCK(hi2c);
00177
00178     return HAL_OK;
00179   }
00180   else
00181   {
00182     return HAL_BUSY;
00183   }
00184 }
00185
00186 /**
00187   * @brief  Enable I2C wakeup from Stop mode(s).
00188   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00189   *                the configuration information for the specified I2Cx peripheral.
00190   * @retval HAL status
00191   */
00192 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
00193 {
00194   /* Check the parameters */
00195   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00196
00197   if (hi2c->State == HAL_I2C_STATE_READY)
00198   {
00199     /* Process Locked */
00200     __HAL_LOCK(hi2c);
00201
00202     hi2c->State = HAL_I2C_STATE_BUSY;
00203
00204     /* Disable the selected I2C peripheral */
00205     __HAL_I2C_DISABLE(hi2c);
00206
00207     /* Enable wakeup from stop mode */
00208     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00209
00210     __HAL_I2C_ENABLE(hi2c);
00211
00212     hi2c->State = HAL_I2C_STATE_READY;
00213
00214     /* Process Unlocked */
00215     __HAL_UNLOCK(hi2c);
00216
00217     return HAL_OK;
00218   }
00219   else
00220   {
00221     return HAL_BUSY;
00222   }
00223 }
00224
00225 /**
00226   * @brief  Disable I2C wakeup from Stop mode(s).
00227   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00228   *                the configuration information for the specified I2Cx peripheral.
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
00232 {
00233   /* Check the parameters */
00234   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00235
00236   if (hi2c->State == HAL_I2C_STATE_READY)
00237   {
00238     /* Process Locked */
00239     __HAL_LOCK(hi2c);
00240
00241     hi2c->State = HAL_I2C_STATE_BUSY;
00242
00243     /* Disable the selected I2C peripheral */
00244     __HAL_I2C_DISABLE(hi2c);
00245
00246     /* Enable wakeup from stop mode */
00247     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00248
00249     __HAL_I2C_ENABLE(hi2c);
00250
00251     hi2c->State = HAL_I2C_STATE_READY;
00252
00253     /* Process Unlocked */
00254     __HAL_UNLOCK(hi2c);
00255
00256     return HAL_OK;
00257   }
00258   else
00259   {
00260     return HAL_BUSY;
00261   }
00262 }
00263
00264 /**
00265   * @brief Enable the I2C fast mode plus driving capability.
00266   * @param ConfigFastModePlus Selects the pin.
00267   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00268   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00269   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00270   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00271   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00272   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00273   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00274   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00275   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00276   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00277   * @note  For all I2C4 pins fast mode plus driving capability can be enabled
00278   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
00279   * @retval None
00280   */
00281 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00282 {
00283   /* Check the parameter */
00284   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00285
00286   /* Enable SYSCFG clock */
00287   __HAL_RCC_SYSCFG_CLK_ENABLE();
00288
00289   /* Enable fast mode plus driving capability for selected pin */
00290   SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
00291 }
00292
00293 /**
00294   * @brief Disable the I2C fast mode plus driving capability.
00295   * @param ConfigFastModePlus Selects the pin.
00296   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00297   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00298   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00299   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00300   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00301   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00302   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00303   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00304   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00305   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00306   * @note  For all I2C4 pins fast mode plus driving capability can be disabled
00307   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
00308   * @retval None
00309   */
00310 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00311 {
00312   /* Check the parameter */
00313   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00314
00315   /* Enable SYSCFG clock */
00316   __HAL_RCC_SYSCFG_CLK_ENABLE();
00317
00318   /* Disable fast mode plus driving capability for selected pin */
00319   CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
00320 }
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 #endif /* HAL_I2C_MODULE_ENABLED */
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2c_ex.h Source File

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stm32h7xx_hal_i2c_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_I2C_EX_H
00022 #define STM32H7xx_HAL_I2C_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2CEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00047   * @{
00048   */
00049 #define I2C_ANALOGFILTER_ENABLE         0x00000000U
00050 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00056   * @{
00057   */
00058 #define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00059 #define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00060 #define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00061 #define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00062 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00063 #define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00064 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00065 #define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Exported macro ------------------------------------------------------------*/
00075 /* Exported functions --------------------------------------------------------*/
00076
00077 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00078   * @{
00079   */
00080
00081 /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
00082   * @brief    Extended features functions
00083   * @{
00084   */
00085
00086 /* Peripheral Control functions  ************************************************/
00087 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00088 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00089 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00090 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00091 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00092 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00093
00094 /* Private constants ---------------------------------------------------------*/
00095 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00096   * @{
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Private macros ------------------------------------------------------------*/
00104 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00105   * @{
00106   */
00107 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00108                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00109
00110 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00111
00112 #if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
00113 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00114                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00115                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00116                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00117                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00118                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
00119                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
00120                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
00121 #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
00122 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00123                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00124                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00125                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00126                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00127                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
00128                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
00129 #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
00130 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00131                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00132                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00133                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00134                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00135                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
00136 #elif defined(SYSCFG_PMCR_I2C1_FMP)
00137 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00138                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00139                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00140                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00141                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
00142 #endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
00143
00144
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Private Functions ---------------------------------------------------------*/
00151 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00152   * @{
00153   */
00154 /* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 #ifdef __cplusplus
00176 }
00177 #endif
00178
00179 #endif /* STM32H7xx_HAL_I2C_EX_H */
00180
00181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s.c Source File

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stm32h7xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @brief   I2S HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   @verbatim
00012  ===============================================================================
00013                   ##### How to use this driver #####
00014  ===============================================================================
00015  [..]
00016     The I2S HAL driver can be used as follow:
00017
00018     (#) Declare a I2S_HandleTypeDef handle structure.
00019     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00020         (##) Enable the SPIx interface clock.
00021         (##) I2S pins configuration:
00022             (+++) Enable the clock for the I2S GPIOs.
00023             (+++) Configure these I2S pins as alternate function pull-up.
00024         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00025              and HAL_I2S_Receive_IT() APIs).
00026             (+++) Configure the I2Sx interrupt priority.
00027             (+++) Enable the NVIC I2S IRQ handle.
00028         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00029              and HAL_I2S_Receive_DMA() APIs:
00030             (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
00031             (+++) Enable the DMAx interface clock.
00032             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00033             (+++) Configure the DMA Tx/Rx Stream/Channel.
00034             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00035             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00036                   DMA Tx/Rx Stream/Channel.
00037
00038    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00039        using HAL_I2S_Init() function.
00040
00041    -@- The specific I2S interrupts (Transmission complete interrupt,
00042        RXNE interrupt and Error Interrupts) will be managed using the macros
00043        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00044
00045         (+@) External clock source is configured after setting correctly
00046              the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
00047
00048     (#) Three mode of operations are available within this driver :
00049
00050    *** Polling mode IO operation ***
00051    =================================
00052    [..]
00053      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00054      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00055
00056    *** Interrupt mode IO operation ***
00057    ===================================
00058    [..]
00059      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00060      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00061          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00062      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00063          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00064      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00065      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00067      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00068          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00069      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00070          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00071
00072    *** DMA mode IO operation ***
00073    ==============================
00074    [..]
00075      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00076      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00077          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00078      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00079          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00080      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00081      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00083      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00084          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00085      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00086          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00087      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00088      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00089      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00090
00091    *** I2S HAL driver macros list ***
00092    ===================================
00093    [..]
00094      Below the list of most used macros in I2S HAL driver.
00095
00096       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00097       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00098       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00099       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00100       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00101
00102     [..]
00103       (@) You can refer to the I2S HAL driver header file for more useful macros
00104
00105    *** I2S HAL driver macros list ***
00106    ===================================
00107    [..]
00108        Callback registration:
00109
00110       (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
00111           allows the user to configure dynamically the driver callbacks.
00112           Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
00113
00114           Function HAL_I2S_RegisterCallback() allows to register following callbacks:
00115             (+) TxCpltCallback        : I2S Tx Completed callback
00116             (+) RxCpltCallback        : I2S Rx Completed callback
00117             (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
00118             (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
00119             (+) ErrorCallback         : I2S Error callback
00120             (+) MspInitCallback       : I2S Msp Init callback
00121             (+) MspDeInitCallback     : I2S Msp DeInit callback
00122           This function takes as parameters the HAL peripheral handle, the Callback ID
00123           and a pointer to the user callback function.
00124
00125
00126       (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
00127           weak function.
00128           HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
00129           and the Callback ID.
00130           This function allows to reset following callbacks:
00131             (+) TxCpltCallback        : I2S Tx Completed callback
00132             (+) RxCpltCallback        : I2S Rx Completed callback
00133             (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
00134             (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
00135             (+) ErrorCallback         : I2S Error callback
00136             (+) MspInitCallback       : I2S Msp Init callback
00137             (+) MspDeInitCallback     : I2S Msp DeInit callback
00138
00139        By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
00140        all callbacks are set to the corresponding weak functions:
00141        examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
00142        Exception done for MspInit and MspDeInit functions that are
00143        reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
00144        these callbacks are null (not registered beforehand).
00145        If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
00146        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00147
00148        Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
00149        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00150        in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
00151        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00152        Then, the user first registers the MspInit/MspDeInit user callbacks
00153        using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
00154        or HAL_I2S_Init() function.
00155
00156        When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
00157        not defined, the callback registering feature is not available
00158        and weak (surcharged) callbacks are used.
00159
00160
00161   @endverbatim
00162   ******************************************************************************
00163   * @attention
00164   *
00165   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00166   * All rights reserved.</center></h2>
00167   *
00168   * This software component is licensed by ST under BSD 3-Clause license,
00169   * the "License"; You may not use this file except in compliance with the
00170   * License. You may obtain a copy of the License at:
00171   *                        opensource.org/licenses/BSD-3-Clause
00172   *
00173   ******************************************************************************
00174   */
00175
00176 /* Includes ------------------------------------------------------------------*/
00177 #include "stm32h7xx_hal.h"
00178
00179 #ifdef HAL_I2S_MODULE_ENABLED
00180
00181 /** @addtogroup STM32H7xx_HAL_Driver
00182   * @{
00183   */
00184
00185 /** @defgroup I2S I2S
00186   * @brief I2S HAL module driver
00187   * @{
00188   */
00189
00190 /* Private typedef -----------------------------------------------------------*/
00191 /* Private define ------------------------------------------------------------*/
00192 #define I2S_TIMEOUT 0xFFFFUL
00193
00194 /* Private macro -------------------------------------------------------------*/
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @defgroup I2S_Private_Functions I2S Private Functions
00198   * @{
00199   */
00200 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00201 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00202 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00203 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00204 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00205 static void               I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
00206 static void               I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
00207 static void               I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
00208 static void               I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
00209 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
00210                                                         uint32_t Timeout);
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported functions ---------------------------------------------------------*/
00216
00217 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00218   * @{
00219   */
00220
00221 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00222   *  @brief    Initialization and Configuration functions
00223   *
00224 @verbatim
00225  ===============================================================================
00226               ##### Initialization and de-initialization functions #####
00227  ===============================================================================
00228     [..]  This subsection provides a set of functions allowing to initialize and
00229           de-initialize the I2Sx peripheral in simplex mode:
00230
00231       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00232           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00233
00234       (+) Call the function HAL_I2S_Init() to configure the selected device with
00235           the selected configuration:
00236         (++) Mode
00237         (++) Standard
00238         (++) Data Format
00239         (++) MCLK Output
00240         (++) Audio frequency
00241         (++) Polarity
00242
00243      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00244           of the selected I2Sx peripheral.
00245   @endverbatim
00246   * @{
00247   */
00248
00249 /**
00250   * @brief  Initializes the I2S according to the specified parameters
00251   *         in the I2S_InitTypeDef and create the associated handle.
00252   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00253   *         the configuration information for I2S module
00254   * @retval HAL status
00255   */
00256 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00257 {
00258   uint32_t i2sdiv;
00259   uint32_t i2sodd;
00260   uint32_t packetlength;
00261   uint32_t tmp;
00262   uint32_t i2sclk;
00263   uint32_t ispcm;
00264
00265   /* Check the I2S handle allocation */
00266   if (hi2s == NULL)
00267   {
00268     return HAL_ERROR;
00269   }
00270
00271   /* Check the I2S parameters */
00272   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00273   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00274   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00275   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00276   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00277   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00278   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00279   assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
00280   assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
00281   assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
00282   assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
00283
00284   if (hi2s->State == HAL_I2S_STATE_RESET)
00285   {
00286     /* Allocate lock resource and initialize it */
00287     hi2s->Lock = HAL_UNLOCKED;
00288
00289 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00290     /* Init the I2S Callback settings */
00291     hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
00292     hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
00293     hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
00294     hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
00295     hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
00296
00297     if (hi2s->MspInitCallback == NULL)
00298     {
00299       hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
00300     }
00301
00302     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00303     hi2s->MspInitCallback(hi2s);
00304 #else
00305     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00306     HAL_I2S_MspInit(hi2s);
00307 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00308   }
00309
00310   hi2s->State = HAL_I2S_STATE_BUSY;
00311
00312   /* Disable the selected I2S peripheral */
00313   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
00314   {
00315     /* Disable I2S peripheral */
00316     __HAL_I2S_DISABLE(hi2s);
00317   }
00318
00319   /* Clear I2S configuration register */
00320   CLEAR_REG(hi2s->Instance->I2SCFGR);
00321
00322   if (IS_I2S_MASTER(hi2s->Init.Mode))
00323   {
00324     /*------------------------- I2SDIV and ODD Calculation ---------------------*/
00325     /* If the requested audio frequency is not the default, compute the prescaler */
00326     if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00327     {
00328       /* Check the frame length (For the Prescaler computing) ********************/
00329       if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00330       {
00331         /* Channel length is 32 bits */
00332         packetlength = 2UL;
00333       }
00334       else
00335       {
00336         /* Channel length is 16 bits */
00337         packetlength = 1UL;
00338       }
00339
00340       /* Check if PCM standard is used */
00341       if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
00342           (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
00343       {
00344         ispcm = 1UL;
00345       }
00346       else
00347       {
00348         ispcm = 0UL;
00349       }
00350
00351       /* Get the source clock value: based on System Clock value */
00352 #if defined (SPI_SPI6I2S_SUPPORT)
00353       if (hi2s->Instance == SPI6)
00354       {
00355         /* SPI6 source clock */
00356         i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
00357       }
00358       else
00359       {
00360         /* SPI1,SPI2 and SPI3 share the same source clock */
00361         i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
00362       }
00363 #else
00364       /* SPI1,SPI2 and SPI3 share the same source clock */
00365       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
00366 #endif
00367
00368       /* Compute the Real divider depending on the MCLK output state, with a floating point */
00369       if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00370       {
00371         /* MCLK output is enabled */
00372         tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
00373       }
00374       else
00375       {
00376         /* MCLK output is disabled */
00377         tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
00378       }
00379
00380       /* Remove the flatting point */
00381       tmp = tmp / 10UL;
00382
00383       /* Check the parity of the divider */
00384       i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
00385
00386       /* Compute the i2sdiv prescaler */
00387       i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
00388     }
00389     else
00390     {
00391       /* Set the default values */
00392       i2sdiv = 2UL;
00393       i2sodd = 0UL;
00394     }
00395
00396     /* Test if the obtain values are forbidden or out of range */
00397     if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
00398     {
00399       /* Set the error code */
00400       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
00401       return  HAL_ERROR;
00402     }
00403
00404     /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
00405     if (i2sdiv == 0UL)
00406     {
00407       i2sodd = 1UL;
00408     }
00409
00410     MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV                 | SPI_I2SCFGR_ODD),
00411                                         ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
00412   }
00413
00414   /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
00415   /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
00416   /* And configure the I2S with the I2S_InitStruct values */
00417   MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD   | SPI_I2SCFGR_I2SCFG     | \
00418                                        SPI_I2SCFGR_I2SSTD   | SPI_I2SCFGR_PCMSYNC    | \
00419                                        SPI_I2SCFGR_DATLEN   | SPI_I2SCFGR_CHLEN      | \
00420                                        SPI_I2SCFGR_CKPOL    | SPI_I2SCFGR_WSINV      | \
00421                                        SPI_I2SCFGR_DATFMT   | SPI_I2SCFGR_MCKOE),
00422                                       (SPI_I2SCFGR_I2SMOD   | hi2s->Init.Mode        | \
00423                                        hi2s->Init.Standard  | hi2s->Init.DataFormat  | \
00424                                        hi2s->Init.CPOL      | hi2s->Init.WSInversion | \
00425                                        hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
00426   /*Clear status register*/
00427   WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
00428
00429   /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
00430
00431   /* Unlock the AF configuration to configure CFG2 register*/
00432   CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
00433
00434   MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
00435
00436   /* Insure that AFCNTR is managed only by Master */
00437   if (IS_I2S_MASTER(hi2s->Init.Mode))
00438   {
00439     /* Alternate function GPIOs control */
00440     MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
00441   }
00442
00443   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00444   hi2s->State     = HAL_I2S_STATE_READY;
00445
00446   return HAL_OK;
00447 }
00448
00449 /**
00450   * @brief DeInitializes the I2S peripheral
00451   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00452   *         the configuration information for I2S module
00453   * @retval HAL status
00454   */
00455 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00456 {
00457   /* Check the I2S handle allocation */
00458   if (hi2s == NULL)
00459   {
00460     return HAL_ERROR;
00461   }
00462
00463   /* Check the parameters */
00464   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00465
00466   hi2s->State = HAL_I2S_STATE_BUSY;
00467
00468   /* Disable the I2S Peripheral Clock */
00469   __HAL_I2S_DISABLE(hi2s);
00470
00471 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00472   if (hi2s->MspDeInitCallback == NULL)
00473   {
00474     hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
00475   }
00476
00477   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00478   hi2s->MspDeInitCallback(hi2s);
00479 #else
00480   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00481   HAL_I2S_MspDeInit(hi2s);
00482 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00483
00484   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00485   hi2s->State     = HAL_I2S_STATE_RESET;
00486
00487   /* Release Lock */
00488   __HAL_UNLOCK(hi2s);
00489
00490   return HAL_OK;
00491 }
00492
00493 /**
00494   * @brief I2S MSP Init
00495   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00496   *         the configuration information for I2S module
00497   * @retval None
00498   */
00499 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00500 {
00501   /* Prevent unused argument(s) compilation warning */
00502   UNUSED(hi2s);
00503
00504   /* NOTE : This function Should not be modified, when the callback is needed,
00505             the HAL_I2S_MspInit could be implemented in the user file
00506    */
00507 }
00508
00509 /**
00510   * @brief I2S MSP DeInit
00511   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00512   *         the configuration information for I2S module
00513   * @retval None
00514   */
00515 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00516 {
00517   /* Prevent unused argument(s) compilation warning */
00518   UNUSED(hi2s);
00519
00520   /* NOTE : This function Should not be modified, when the callback is needed,
00521             the HAL_I2S_MspDeInit could be implemented in the user file
00522    */
00523 }
00524
00525 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00526 /**
00527   * @brief  Register a User I2S Callback
00528   *         To be used instead of the weak predefined callback
00529   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00530   *                the configuration information for the specified I2S.
00531   * @param  CallbackID ID of the callback to be registered
00532   * @param  pCallback pointer to the Callback function
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
00536 {
00537   HAL_StatusTypeDef status = HAL_OK;
00538
00539   if (pCallback == NULL)
00540   {
00541     /* Update the error code */
00542     hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
00543
00544     return HAL_ERROR;
00545   }
00546   /* Process locked */
00547   __HAL_LOCK(hi2s);
00548
00549   if (HAL_I2S_STATE_READY == hi2s->State)
00550   {
00551     switch (CallbackID)
00552     {
00553       case HAL_I2S_TX_COMPLETE_CB_ID :
00554         hi2s->TxCpltCallback = pCallback;
00555         break;
00556
00557       case HAL_I2S_RX_COMPLETE_CB_ID :
00558         hi2s->RxCpltCallback = pCallback;
00559         break;
00560
00561       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00562         hi2s->TxHalfCpltCallback = pCallback;
00563         break;
00564
00565       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00566         hi2s->RxHalfCpltCallback = pCallback;
00567         break;
00568
00569       case HAL_I2S_ERROR_CB_ID :
00570         hi2s->ErrorCallback = pCallback;
00571         break;
00572
00573       case HAL_I2S_MSPINIT_CB_ID :
00574         hi2s->MspInitCallback = pCallback;
00575         break;
00576
00577       case HAL_I2S_MSPDEINIT_CB_ID :
00578         hi2s->MspDeInitCallback = pCallback;
00579         break;
00580
00581       default :
00582         /* Update the error code */
00583         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00584
00585         /* Return error status */
00586         status =  HAL_ERROR;
00587         break;
00588     }
00589   }
00590   else if (HAL_I2S_STATE_RESET == hi2s->State)
00591   {
00592     switch (CallbackID)
00593     {
00594       case HAL_I2S_MSPINIT_CB_ID :
00595         hi2s->MspInitCallback = pCallback;
00596         break;
00597
00598       case HAL_I2S_MSPDEINIT_CB_ID :
00599         hi2s->MspDeInitCallback = pCallback;
00600         break;
00601
00602       default :
00603         /* Update the error code */
00604         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00605
00606         /* Return error status */
00607         status =  HAL_ERROR;
00608         break;
00609     }
00610   }
00611   else
00612   {
00613     /* Update the error code */
00614     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00615
00616     /* Return error status */
00617     status =  HAL_ERROR;
00618   }
00619
00620   /* Release Lock */
00621   __HAL_UNLOCK(hi2s);
00622   return status;
00623 }
00624
00625 /**
00626   * @brief  Unregister an I2S Callback
00627   *         I2S callback is redirected to the weak predefined callback
00628   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00629   *                the configuration information for the specified I2S.
00630   * @param  CallbackID ID of the callback to be unregistered
00631   * @retval HAL status
00632   */
00633 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
00634 {
00635   HAL_StatusTypeDef status = HAL_OK;
00636
00637   /* Process locked */
00638   __HAL_LOCK(hi2s);
00639
00640   if (HAL_I2S_STATE_READY == hi2s->State)
00641   {
00642     switch (CallbackID)
00643     {
00644       case HAL_I2S_TX_COMPLETE_CB_ID :
00645         hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
00646         break;
00647
00648       case HAL_I2S_RX_COMPLETE_CB_ID :
00649         hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
00650         break;
00651
00652       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00653         hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
00654         break;
00655
00656       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00657         hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
00658         break;
00659
00660       case HAL_I2S_ERROR_CB_ID :
00661         hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
00662         break;
00663
00664       case HAL_I2S_MSPINIT_CB_ID :
00665         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00666         break;
00667
00668       case HAL_I2S_MSPDEINIT_CB_ID :
00669         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00670         break;
00671
00672       default :
00673         /* Update the error code */
00674         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00675
00676         /* Return error status */
00677         status =  HAL_ERROR;
00678         break;
00679     }
00680   }
00681   else if (HAL_I2S_STATE_RESET == hi2s->State)
00682   {
00683     switch (CallbackID)
00684     {
00685       case HAL_I2S_MSPINIT_CB_ID :
00686         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00687         break;
00688
00689       case HAL_I2S_MSPDEINIT_CB_ID :
00690         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00691         break;
00692
00693       default :
00694         /* Update the error code */
00695         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00696
00697         /* Return error status */
00698         status =  HAL_ERROR;
00699         break;
00700     }
00701   }
00702   else
00703   {
00704     /* Update the error code */
00705     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00706
00707     /* Return error status */
00708     status =  HAL_ERROR;
00709   }
00710
00711   /* Release Lock */
00712   __HAL_UNLOCK(hi2s);
00713   return status;
00714 }
00715 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00716 /**
00717   * @}
00718   */
00719
00720 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00721   *  @brief Data transfers functions
00722   *
00723 @verbatim
00724  ===============================================================================
00725                       ##### IO operation functions #####
00726  ===============================================================================
00727     [..]
00728     This subsection provides a set of functions allowing to manage the I2S data
00729     transfers.
00730
00731     (#) There are two modes of transfer:
00732        (++) Blocking mode : The communication is performed in the polling mode.
00733             The status of all data processing is returned by the same function
00734             after finishing transfer.
00735        (++) No-Blocking mode : The communication is performed using Interrupts
00736             or DMA. These functions return the status of the transfer startup.
00737             The end of the data processing will be indicated through the
00738             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00739             using DMA mode.
00740
00741     (#) Blocking mode functions are :
00742         (++) HAL_I2S_Transmit()
00743         (++) HAL_I2S_Receive()
00744
00745     (#) No-Blocking mode functions with Interrupt are :
00746         (++) HAL_I2S_Transmit_IT()
00747         (++) HAL_I2S_Receive_IT()
00748
00749     (#) No-Blocking mode functions with DMA are :
00750         (++) HAL_I2S_Transmit_DMA()
00751         (++) HAL_I2S_Receive_DMA()
00752
00753     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00754         (++) HAL_I2S_TxCpltCallback()
00755         (++) HAL_I2S_RxCpltCallback()
00756         (++) HAL_I2S_ErrorCallback()
00757
00758 @endverbatim
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Transmit an amount of data in blocking mode
00764   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00765   *         the configuration information for I2S module
00766   * @param  pData a 16-bit pointer to data buffer.
00767   * @param  Size number of data sample to be sent:
00768   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00769   *         configuration phase, the Size parameter means the number of 16-bit data length
00770   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00771   *         the Size parameter means the number of 16-bit data length.
00772   * @param  Timeout Timeout duration
00773   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00774   *         between Master and Slave(example: audio streaming).
00775   * @retval HAL status
00776   */
00777 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00778 {
00779   if ((pData == NULL) || (Size == 0UL))
00780   {
00781     return  HAL_ERROR;
00782   }
00783
00784   /* Process Locked */
00785   __HAL_LOCK(hi2s);
00786
00787   if (hi2s->State != HAL_I2S_STATE_READY)
00788   {
00789     __HAL_UNLOCK(hi2s);
00790     return HAL_BUSY;
00791   }
00792
00793   /* Set state and reset error code */
00794   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
00795   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
00796   hi2s->pTxBuffPtr  = pData;
00797   hi2s->TxXferSize  = Size;
00798   hi2s->TxXferCount = Size;
00799
00800   /* Initialize fields not used in handle to zero */
00801   hi2s->pRxBuffPtr  = NULL;
00802   hi2s->RxXferSize  = (uint16_t) 0UL;
00803   hi2s->RxXferCount = (uint16_t) 0UL;
00804
00805   /* Check if the I2S is already enabled */
00806   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00807   {
00808     /* Enable I2S peripheral */
00809     __HAL_I2S_ENABLE(hi2s);
00810   }
00811
00812   /* Start the transfer */
00813   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
00814
00815
00816   /* Wait until TXP flag is set */
00817   if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
00818   {
00819     /* Set the error code */
00820     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00821     hi2s->State = HAL_I2S_STATE_READY;
00822     __HAL_UNLOCK(hi2s);
00823     return HAL_ERROR;
00824   }
00825
00826   while (hi2s->TxXferCount > 0UL)
00827   {
00828     if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
00829     {
00830       /* Transmit data in 32 Bit mode */
00831       hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
00832       hi2s->pTxBuffPtr += 2;
00833       hi2s->TxXferCount--;
00834     }
00835     else
00836     {
00837       /* Transmit data in 16 Bit mode */
00838       *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
00839       hi2s->pTxBuffPtr++;
00840       hi2s->TxXferCount--;
00841     }
00842
00843     /* Wait until TXP flag is set */
00844     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
00845     {
00846       /* Set the error code */
00847       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00848       hi2s->State = HAL_I2S_STATE_READY;
00849       __HAL_UNLOCK(hi2s);
00850       return HAL_ERROR;
00851     }
00852
00853     /* Check if an underrun occurs */
00854     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00855     {
00856       /* Clear underrun flag */
00857       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00858
00859       /* Set the error code */
00860       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00861     }
00862   }
00863
00864   hi2s->State = HAL_I2S_STATE_READY;
00865   __HAL_UNLOCK(hi2s);
00866   return HAL_OK;
00867 }
00868
00869 /**
00870   * @brief  Receive an amount of data in blocking mode
00871   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00872   *         the configuration information for I2S module
00873   * @param  pData a 16-bit pointer to data buffer.
00874   * @param  Size number of data sample to be sent:
00875   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00876   *         configuration phase, the Size parameter means the number of 16-bit data length
00877   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00878   *         the Size parameter means the number of 16-bit data length.
00879   * @param  Timeout Timeout duration
00880   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00881   *         between Master and Slave(example: audio streaming).
00882   * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00883   *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00884   * @retval HAL status
00885   */
00886 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00887 {
00888   if ((pData == NULL) || (Size == 0UL))
00889   {
00890     return  HAL_ERROR;
00891   }
00892
00893   /* Process Locked */
00894   __HAL_LOCK(hi2s);
00895
00896   if (hi2s->State != HAL_I2S_STATE_READY)
00897   {
00898     __HAL_UNLOCK(hi2s);
00899     return HAL_BUSY;
00900   }
00901
00902   /* Set state and reset error code */
00903   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
00904   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
00905   hi2s->pRxBuffPtr  = pData;
00906   hi2s->RxXferSize  = Size;
00907   hi2s->RxXferCount = Size;
00908
00909   /* Initialize fields not used in handle to zero */
00910   hi2s->pTxBuffPtr  = NULL;
00911   hi2s->TxXferSize  = (uint16_t) 0UL;
00912   hi2s->TxXferCount = (uint16_t) 0UL;
00913
00914   /* Check if the I2S is already enabled */
00915   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00916   {
00917     /* Enable I2S peripheral */
00918     __HAL_I2S_ENABLE(hi2s);
00919   }
00920
00921   /* Start the transfer */
00922   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
00923
00924   /* Receive data */
00925   while (hi2s->RxXferCount > 0UL)
00926   {
00927     /* Wait until RXNE flag is set */
00928     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK)
00929     {
00930       /* Set the error code */
00931       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00932       hi2s->State = HAL_I2S_STATE_READY;
00933       __HAL_UNLOCK(hi2s);
00934       return HAL_ERROR;
00935     }
00936
00937     if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
00938     {
00939       /* Receive data in 32 Bit mode */
00940       *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
00941       hi2s->pRxBuffPtr += 2;
00942       hi2s->RxXferCount--;
00943     }
00944     else
00945     {
00946       /* Receive data in 16 Bit mode */
00947       *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
00948       hi2s->pRxBuffPtr++;
00949       hi2s->RxXferCount--;
00950     }
00951
00952     /* Check if an overrun occurs */
00953     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00954     {
00955       /* Clear overrun flag */
00956       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00957
00958       /* Set the error code */
00959       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00960     }
00961   }
00962
00963   hi2s->State = HAL_I2S_STATE_READY;
00964   __HAL_UNLOCK(hi2s);
00965   return HAL_OK;
00966 }
00967
00968 /**
00969   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
00970   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00971   *         the configuration information for I2S module
00972   * @param  pData a 16-bit pointer to data buffer.
00973   * @param  Size number of data sample to be sent:
00974   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00975   *         configuration phase, the Size parameter means the number of 16-bit data length
00976   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00977   *         the Size parameter means the number of 16-bit data length.
00978   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00979   *         between Master and Slave(example: audio streaming).
00980   * @retval HAL status
00981   */
00982 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00983 {
00984   if ((pData == NULL) || (Size == 0UL))
00985   {
00986     return  HAL_ERROR;
00987   }
00988
00989   /* Process Locked */
00990   __HAL_LOCK(hi2s);
00991
00992   if (hi2s->State != HAL_I2S_STATE_READY)
00993   {
00994     __HAL_UNLOCK(hi2s);
00995     return HAL_BUSY;
00996   }
00997
00998   /* Set state and reset error code */
00999   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
01000   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
01001   hi2s->pTxBuffPtr  = (uint16_t *)pData;
01002   hi2s->TxXferSize  = Size;
01003   hi2s->TxXferCount = Size;
01004
01005   /* Initialize fields not used in handle to zero */
01006   hi2s->pRxBuffPtr  = NULL;
01007   hi2s->RxXferSize  = (uint16_t) 0UL;
01008   hi2s->RxXferCount = (uint16_t) 0UL;
01009
01010   /* Set the function for IT treatment */
01011   if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
01012   {
01013     hi2s->TxISR = I2S_Transmit_32Bit_IT;
01014   }
01015   else
01016   {
01017     hi2s->TxISR = I2S_Transmit_16Bit_IT;
01018   }
01019
01020   /* Check if the I2S is already enabled */
01021   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01022   {
01023     /* Enable I2S peripheral */
01024     __HAL_I2S_ENABLE(hi2s);
01025   }
01026
01027   /* Enable TXP and UDR interrupt */
01028   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR));
01029
01030   /* Enable TIFRE interrupt if the mode is Slave  */
01031   if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
01032   {
01033     __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
01034   }
01035
01036   /* Start the transfer */
01037   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
01038
01039   __HAL_UNLOCK(hi2s);
01040   return HAL_OK;
01041 }
01042
01043 /**
01044   * @brief  Receive an amount of data in non-blocking mode with Interrupt
01045   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01046   *         the configuration information for I2S module
01047   * @param  pData a 16-bit pointer to the Receive data buffer.
01048   * @param  Size number of data sample to be sent:
01049   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01050   *         configuration phase, the Size parameter means the number of 16-bit data length
01051   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01052   *         the Size parameter means the number of 16-bit data length.
01053   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01054   *         between Master and Slave(example: audio streaming).
01055   * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
01056   * between Master and Slave otherwise the I2S interrupt should be optimized.
01057   * @retval HAL status
01058   */
01059 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01060 {
01061   if ((pData == NULL) || (Size == 0UL))
01062   {
01063     return  HAL_ERROR;
01064   }
01065
01066   /* Process Locked */
01067   __HAL_LOCK(hi2s);
01068
01069   if (hi2s->State != HAL_I2S_STATE_READY)
01070   {
01071     __HAL_UNLOCK(hi2s);
01072     return HAL_BUSY;
01073   }
01074
01075   /* Set state and reset error code */
01076   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
01077   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
01078   hi2s->pRxBuffPtr  = pData;
01079   hi2s->RxXferSize  = Size;
01080   hi2s->RxXferCount = Size;
01081
01082   /* Initialize fields not used in handle to zero */
01083   hi2s->pTxBuffPtr  = NULL;
01084   hi2s->TxXferSize  = (uint16_t) 0UL;
01085   hi2s->TxXferCount = (uint16_t) 0UL;
01086
01087   /* Set the function for IT treatment */
01088   if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
01089   {
01090     hi2s->RxISR = I2S_Receive_32Bit_IT;
01091   }
01092   else
01093   {
01094     hi2s->RxISR = I2S_Receive_16Bit_IT;
01095   }
01096
01097   /* Check if the I2S is already enabled */
01098   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01099   {
01100     /* Enable I2S peripheral */
01101     __HAL_I2S_ENABLE(hi2s);
01102   }
01103   /* Enable RXNE and ERR interrupt */
01104   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
01105
01106   /* Enable TIFRE interrupt if the mode is Slave  */
01107   if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
01108   {
01109     __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
01110   }
01111
01112   /* Start the transfer */
01113   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
01114
01115   __HAL_UNLOCK(hi2s);
01116   return HAL_OK;
01117 }
01118
01119 /**
01120   * @brief  Transmit an amount of data in non-blocking mode with DMA
01121   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01122   *         the configuration information for I2S module
01123   * @param  pData a 16-bit pointer to the Transmit data buffer.
01124   * @param  Size number of data sample to be sent:
01125   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01126   *         configuration phase, the Size parameter means the number of 16-bit data length
01127   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01128   *         the Size parameter means the number of 16-bit data length.
01129   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01130   *         between Master and Slave(example: audio streaming).
01131   * @retval HAL status
01132   */
01133 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01134 {
01135   if ((pData == NULL) || (Size == 0UL))
01136   {
01137     return  HAL_ERROR;
01138   }
01139
01140   /* Process Locked */
01141   __HAL_LOCK(hi2s);
01142
01143   if (hi2s->State != HAL_I2S_STATE_READY)
01144   {
01145     __HAL_UNLOCK(hi2s);
01146     return HAL_BUSY;
01147   }
01148
01149   /* Set state and reset error code */
01150   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
01151   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
01152   hi2s->pTxBuffPtr  = pData;
01153   hi2s->TxXferSize  = Size;
01154   hi2s->TxXferCount = Size;
01155
01156   /* Init field not used in handle to zero */
01157   hi2s->pRxBuffPtr  = NULL;
01158   hi2s->RxXferSize  = (uint16_t)0UL;
01159   hi2s->RxXferCount = (uint16_t)0UL;
01160
01161   /* Set the I2S Tx DMA Half transfer complete callback */
01162   hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
01163
01164   /* Set the I2S Tx DMA transfer complete callback */
01165   hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
01166
01167   /* Set the DMA error callback */
01168   hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
01169
01170   /* Enable the Tx DMA Stream/Channel */
01171   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
01172   {
01173     /* Update SPI error code */
01174     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01175     hi2s->State = HAL_I2S_STATE_READY;
01176
01177     __HAL_UNLOCK(hi2s);
01178     return HAL_ERROR;
01179   }
01180
01181   /* Check if the I2S Tx request is already enabled */
01182   if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
01183   {
01184     /* Enable Tx DMA Request */
01185     SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01186   }
01187
01188   /* Check if the I2S is already enabled */
01189   if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
01190   {
01191     /* Enable I2S peripheral */
01192     __HAL_I2S_ENABLE(hi2s);
01193   }
01194
01195   /* Start the transfer */
01196   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
01197
01198   __HAL_UNLOCK(hi2s);
01199   return HAL_OK;
01200 }
01201
01202 /**
01203   * @brief  Receive an amount of data in non-blocking mode with DMA
01204   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01205   *         the configuration information for I2S module
01206   * @param  pData a 16-bit pointer to the Receive data buffer.
01207   * @param  Size number of data sample to be sent:
01208   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01209   *         configuration phase, the Size parameter means the number of 16-bit data length
01210   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01211   *         the Size parameter means the number of 16-bit data length.
01212   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01213   *         between Master and Slave(example: audio streaming).
01214   * @retval HAL status
01215   */
01216 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01217 {
01218   if ((pData == NULL) || (Size == 0UL))
01219   {
01220     return  HAL_ERROR;
01221   }
01222
01223   /* Process Locked */
01224   __HAL_LOCK(hi2s);
01225
01226   if (hi2s->State != HAL_I2S_STATE_READY)
01227   {
01228     __HAL_UNLOCK(hi2s);
01229     return HAL_BUSY;
01230   }
01231
01232   /* Set state and reset error code */
01233   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
01234   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
01235   hi2s->pRxBuffPtr  = pData;
01236   hi2s->RxXferSize  = Size;
01237   hi2s->RxXferCount = Size;
01238
01239   /* Init field not used in handle to zero */
01240   hi2s->pTxBuffPtr  = NULL;
01241   hi2s->TxXferSize  = (uint16_t)0UL;
01242   hi2s->TxXferCount = (uint16_t)0UL;
01243
01244
01245   /* Set the I2S Rx DMA Half transfer complete callback */
01246   hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
01247
01248   /* Set the I2S Rx DMA transfer complete callback */
01249   hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
01250
01251   /* Set the DMA error callback */
01252   hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
01253
01254   /* Enable the Rx DMA Stream/Channel */
01255   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
01256   {
01257     /* Update SPI error code */
01258     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01259     hi2s->State = HAL_I2S_STATE_READY;
01260
01261     __HAL_UNLOCK(hi2s);
01262     return HAL_ERROR;
01263   }
01264
01265   /* Check if the I2S Rx request is already enabled */
01266   if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
01267   {
01268     /* Enable Rx DMA Request */
01269     SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01270   }
01271
01272   /* Check if the I2S is already enabled */
01273   if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
01274   {
01275     /* Enable I2S peripheral */
01276     __HAL_I2S_ENABLE(hi2s);
01277   }
01278
01279   /* Start the transfer */
01280   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
01281
01282   __HAL_UNLOCK(hi2s);
01283   return HAL_OK;
01284 }
01285
01286 /**
01287   * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
01288   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01289   *         the configuration information for I2S module
01290   * @retval HAL status
01291   */
01292 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
01293 {
01294   /* Process Locked */
01295   __HAL_LOCK(hi2s);
01296
01297   uint32_t tickstart;
01298
01299   /* Get tick */
01300   tickstart = HAL_GetTick();
01301
01302
01303   /* Check if the I2S peripheral is in master mode */
01304   if (IS_I2S_MASTER(hi2s->Init.Mode))
01305   {
01306     /* Check if there is a transfer on-going */
01307     if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
01308     {
01309       /* Set error code to no on going transfer */
01310       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
01311       hi2s->State = HAL_I2S_STATE_READY;
01312
01313       __HAL_UNLOCK(hi2s);
01314       return HAL_ERROR;
01315     }
01316
01317     SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
01318
01319     while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
01320     {
01321       if ((((HAL_GetTick() - tickstart) >=  I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
01322       {
01323         /* Set the I2S State ready */
01324         hi2s->State = HAL_I2S_STATE_READY;
01325
01326         /* Process Unlocked */
01327         __HAL_UNLOCK(hi2s);
01328
01329         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
01330         hi2s->State = HAL_I2S_STATE_READY;
01331         return HAL_TIMEOUT;
01332       }
01333     }
01334
01335     /* Disable I2S peripheral */
01336     __HAL_I2S_DISABLE(hi2s);
01337
01338     hi2s->State = HAL_I2S_STATE_READY;
01339
01340     /* Process Unlocked */
01341     __HAL_UNLOCK(hi2s);
01342
01343     return HAL_OK;
01344   }
01345   else
01346   {
01347     /* Set error code to not supported */
01348     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
01349     hi2s->State = HAL_I2S_STATE_READY;
01350
01351     /* Process Unlocked */
01352     __HAL_UNLOCK(hi2s);
01353
01354     return HAL_ERROR;
01355   }
01356 }
01357
01358 /**
01359   * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
01360   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01361   *         the configuration information for I2S module
01362   * @retval HAL status
01363   */
01364 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
01365 {
01366   /* Process Locked */
01367   __HAL_LOCK(hi2s);
01368
01369   if (hi2s->State != HAL_I2S_STATE_READY)
01370   {
01371     hi2s->State = HAL_I2S_STATE_READY;
01372
01373     __HAL_UNLOCK(hi2s);
01374     return HAL_ERROR;
01375   }
01376
01377   /* Set state and reset error code */
01378   hi2s->State       = HAL_I2S_STATE_BUSY;
01379   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
01380
01381   /* Enable I2S peripheral */
01382   __HAL_I2S_ENABLE(hi2s);
01383
01384   /* Start the transfer */
01385   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
01386
01387   /* Process Unlocked */
01388   __HAL_UNLOCK(hi2s);
01389
01390   return HAL_OK;
01391 }
01392
01393 /**
01394   * @brief  Stops the audio DMA Stream/Channel playing from the Media.
01395   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01396   *         the configuration information for I2S module
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01400 {
01401   HAL_StatusTypeDef errorcode = HAL_OK;
01402   /* The Lock is not implemented on this API to allow the user application
01403      to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01404      when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
01405      and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01406      */
01407
01408   /* Disable the I2S Tx/Rx DMA requests */
01409   CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01410   CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01411
01412   /* Abort the I2S DMA tx Stream/Channel */
01413   if (hi2s->hdmatx != NULL)
01414   {
01415     /* Disable the I2S DMA tx Stream/Channel */
01416     if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
01417     {
01418       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01419       errorcode = HAL_ERROR;
01420     }
01421   }
01422
01423   /* Abort the I2S DMA rx Stream/Channel */
01424   if (hi2s->hdmarx != NULL)
01425   {
01426     /* Disable the I2S DMA rx Stream/Channel */
01427     if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
01428     {
01429       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01430       errorcode = HAL_ERROR;
01431     }
01432   }
01433
01434   /* Disable I2S peripheral */
01435   __HAL_I2S_DISABLE(hi2s);
01436
01437   hi2s->State = HAL_I2S_STATE_READY;
01438
01439   return errorcode;
01440 }
01441
01442 /**
01443   * @brief  This function handles I2S interrupt request.
01444   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01445   *         the configuration information for I2S module
01446   * @retval None
01447   */
01448 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01449 {
01450   uint32_t itsource = hi2s->Instance->IER;
01451   uint32_t itflag   = hi2s->Instance->SR;
01452   uint32_t trigger  = itsource & itflag;
01453
01454   /* I2S in mode Receiver ------------------------------------------------*/
01455   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP))
01456   {
01457     hi2s->RxISR(hi2s);
01458   }
01459
01460   /* I2S in mode Transmitter -----------------------------------------------*/
01461   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP))
01462   {
01463     hi2s->TxISR(hi2s);
01464   }
01465
01466   /* I2S interrupt error ----------------------------------------------------*/
01467   if ((trigger & (I2S_FLAG_OVR| I2S_FLAG_UDR | I2S_FLAG_FRE)) != 0UL)
01468   {
01469     /* I2S Overrun error interrupt occurred ---------------------------------*/
01470     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
01471     {
01472       /* Disable RXP and ERR interrupt */
01473       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
01474
01475       /* Set the error code and execute error callback*/
01476       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
01477       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01478     }
01479
01480     /* I2S Underrun error interrupt occurred --------------------------------*/
01481     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
01482     {
01483       /* Disable TXP and ERR interrupt */
01484       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
01485
01486       /* Set the error code and execute error callback*/
01487       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
01488       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01489     }
01490
01491     /* I2S Frame error interrupt occurred -----------------------------------*/
01492     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_FRE) != RESET)
01493     {
01494       /* Disable FRE and ERR interrupt */
01495       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_FRE | I2S_IT_ERR));
01496
01497       /* Set the error code and execute error callback*/
01498       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
01499       __HAL_I2S_CLEAR_FREFLAG(hi2s);
01500     }
01501
01502     /* Set the I2S State ready */
01503     hi2s->State = HAL_I2S_STATE_READY;
01504
01505     /* Call user error callback */
01506 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01507     hi2s->ErrorCallback(hi2s);
01508 #else
01509     HAL_I2S_ErrorCallback(hi2s);
01510 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01511   }
01512 }
01513
01514 /**
01515   * @brief  Tx Transfer Half completed callbacks
01516   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01517   *         the configuration information for I2S module
01518   * @retval None
01519   */
01520 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01521 {
01522   /* Prevent unused argument(s) compilation warning */
01523   UNUSED(hi2s);
01524
01525   /* NOTE : This function Should not be modified, when the callback is needed,
01526             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01527    */
01528 }
01529
01530 /**
01531   * @brief  Tx Transfer completed callbacks
01532   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01533   *         the configuration information for I2S module
01534   * @retval None
01535   */
01536 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01537 {
01538   /* Prevent unused argument(s) compilation warning */
01539   UNUSED(hi2s);
01540
01541   /* NOTE : This function Should not be modified, when the callback is needed,
01542             the HAL_I2S_TxCpltCallback could be implemented in the user file
01543    */
01544 }
01545
01546 /**
01547   * @brief  Rx Transfer half completed callbacks
01548   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01549   *         the configuration information for I2S module
01550   * @retval None
01551   */
01552 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01553 {
01554   /* Prevent unused argument(s) compilation warning */
01555   UNUSED(hi2s);
01556
01557   /* NOTE : This function Should not be modified, when the callback is needed,
01558             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
01559    */
01560 }
01561
01562 /**
01563   * @brief  Rx Transfer completed callbacks
01564   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01565   *         the configuration information for I2S module
01566   * @retval None
01567   */
01568 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01569 {
01570   /* Prevent unused argument(s) compilation warning */
01571   UNUSED(hi2s);
01572
01573   /* NOTE : This function Should not be modified, when the callback is needed,
01574             the HAL_I2S_RxCpltCallback could be implemented in the user file
01575    */
01576 }
01577
01578 /**
01579   * @brief  I2S error callbacks
01580   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01581   *         the configuration information for I2S module
01582   * @retval None
01583   */
01584 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01585 {
01586   /* Prevent unused argument(s) compilation warning */
01587   UNUSED(hi2s);
01588
01589   /* NOTE : This function Should not be modified, when the callback is needed,
01590             the HAL_I2S_ErrorCallback could be implemented in the user file
01591    */
01592 }
01593
01594 /**
01595   * @}
01596   */
01597
01598 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01599   *  @brief   Peripheral State functions
01600   *
01601 @verbatim
01602  ===============================================================================
01603                       ##### Peripheral State and Errors functions #####
01604  ===============================================================================
01605     [..]
01606     This subsection permits to get in run-time the status of the peripheral
01607     and the data flow.
01608
01609 @endverbatim
01610   * @{
01611   */
01612
01613 /**
01614   * @brief  Return the I2S state
01615   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01616   *         the configuration information for I2S module
01617   * @retval HAL state
01618   */
01619 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01620 {
01621   return hi2s->State;
01622 }
01623
01624 /**
01625   * @brief  Return the I2S error code
01626   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01627   *         the configuration information for I2S module
01628   * @retval I2S Error Code
01629   */
01630 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01631 {
01632   return hi2s->ErrorCode;
01633 }
01634 /**
01635   * @}
01636   */
01637
01638
01639 /**
01640   * @brief  DMA I2S transmit process complete callback
01641   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01642   *                the configuration information for the specified DMA module.
01643   * @retval None
01644   */
01645 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01646 {
01647   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01648
01649   /* if DMA is configured in DMA_NORMAL Mode */
01650   if (hdma->Init.Mode == DMA_NORMAL)
01651   {
01652     /* Disable Tx DMA Request */
01653     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01654
01655     hi2s->TxXferCount = (uint16_t) 0UL;
01656     hi2s->State = HAL_I2S_STATE_READY;
01657   }
01658   /* Call user Tx complete callback */
01659 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01660   hi2s->TxCpltCallback(hi2s);
01661 #else
01662   HAL_I2S_TxCpltCallback(hi2s);
01663 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01664 }
01665
01666 /**
01667   * @brief  DMA I2S transmit process half complete callback
01668   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01669   *         the configuration information for the specified DMA module.
01670   * @retval None
01671   */
01672 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01673 {
01674   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01675
01676   /* Call user Tx half complete callback */
01677 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01678   hi2s->TxHalfCpltCallback(hi2s);
01679 #else
01680   HAL_I2S_TxHalfCpltCallback(hi2s);
01681 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01682 }
01683
01684 /**
01685   * @brief  DMA I2S receive process complete callback
01686   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01687   *         the configuration information for the specified DMA module.
01688   * @retval None
01689   */
01690 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01691 {
01692   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01693
01694   /* if DMA is configured in DMA_NORMAL Mode */
01695   if (hdma->Init.Mode == DMA_NORMAL)
01696   {
01697     /* Disable Rx DMA Request */
01698     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01699     hi2s->RxXferCount = (uint16_t)0UL;
01700     hi2s->State = HAL_I2S_STATE_READY;
01701   }
01702   /* Call user Rx complete callback */
01703 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01704   hi2s->RxCpltCallback(hi2s);
01705 #else
01706   HAL_I2S_RxCpltCallback(hi2s);
01707 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01708 }
01709
01710 /**
01711   * @brief  DMA I2S receive process half complete callback
01712   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01713   *         the configuration information for the specified DMA module.
01714   * @retval None
01715   */
01716 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01717 {
01718   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01719
01720   /* Call user Rx half complete callback */
01721 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01722   hi2s->RxHalfCpltCallback(hi2s);
01723 #else
01724   HAL_I2S_RxHalfCpltCallback(hi2s);
01725 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01726 }
01727
01728 /**
01729   * @brief  DMA I2S communication error callback
01730   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01731   *         the configuration information for the specified DMA module.
01732   * @retval None
01733   */
01734 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01735 {
01736   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01737
01738   /* Disable Rx and Tx DMA Request */
01739   CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
01740   hi2s->TxXferCount = (uint16_t) 0UL;
01741   hi2s->RxXferCount = (uint16_t) 0UL;
01742
01743   hi2s->State = HAL_I2S_STATE_READY;
01744
01745   /* Set the error code and execute error callback*/
01746   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01747   /* Call user error callback */
01748 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01749   hi2s->ErrorCallback(hi2s);
01750 #else
01751   HAL_I2S_ErrorCallback(hi2s);
01752 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01753 }
01754
01755 /**
01756   * @brief  Manage the transmission 16-bit in Interrupt context
01757   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01758   *         the configuration information for I2S module
01759   * @retval None
01760   */
01761 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
01762 {
01763   /* Transmit data */
01764   *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
01765   hi2s->pTxBuffPtr++;
01766   hi2s->TxXferCount--;
01767
01768   if (hi2s->TxXferCount == 0UL)
01769   {
01770     /* Disable TXE and ERR interrupt */
01771     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
01772
01773     hi2s->State = HAL_I2S_STATE_READY;
01774     /* Call user Tx complete callback */
01775 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01776     hi2s->TxCpltCallback(hi2s);
01777 #else
01778     HAL_I2S_TxCpltCallback(hi2s);
01779 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01780   }
01781 }
01782
01783 /**
01784   * @brief  Manage the transmission 32-bit in Interrupt context
01785   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01786   *         the configuration information for I2S module
01787   * @retval None
01788   */
01789 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
01790 {
01791   /* Transmit data */
01792   hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
01793   hi2s->pTxBuffPtr += 2;
01794   hi2s->TxXferCount--;
01795
01796   if (hi2s->TxXferCount == 0UL)
01797   {
01798     /* Disable TXE and ERR interrupt */
01799     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
01800
01801     hi2s->State = HAL_I2S_STATE_READY;
01802     /* Call user Tx complete callback */
01803 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01804     hi2s->TxCpltCallback(hi2s);
01805 #else
01806     HAL_I2S_TxCpltCallback(hi2s);
01807 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01808   }
01809 }
01810
01811 /**
01812   * @brief  Manage the reception 16-bit in Interrupt context
01813   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01814   *         the configuration information for I2S module
01815   * @retval None
01816   */
01817 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
01818 {
01819   /* Receive data */
01820   *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
01821   hi2s->pRxBuffPtr++;
01822   hi2s->RxXferCount--;
01823
01824   if (hi2s->RxXferCount == 0UL)
01825   {
01826     /* Disable RXNE and ERR interrupt */
01827     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
01828
01829     hi2s->State = HAL_I2S_STATE_READY;
01830     /* Call user Rx complete callback */
01831 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01832     hi2s->RxCpltCallback(hi2s);
01833 #else
01834     HAL_I2S_RxCpltCallback(hi2s);
01835 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01836   }
01837 }
01838
01839 /**
01840   * @brief  Manage the reception 32-bit in Interrupt context
01841   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01842   *         the configuration information for I2S module
01843   * @retval None
01844   */
01845 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
01846 {
01847   /* Receive data */
01848   *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
01849   hi2s->pRxBuffPtr += 2;
01850   hi2s->RxXferCount--;
01851
01852   if (hi2s->RxXferCount == 0UL)
01853   {
01854     /* Disable RXNE and ERR interrupt */
01855     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
01856
01857     hi2s->State = HAL_I2S_STATE_READY;
01858     /* Call user Rx complete callback */
01859 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
01860     hi2s->RxCpltCallback(hi2s);
01861 #else
01862     HAL_I2S_RxCpltCallback(hi2s);
01863 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01864   }
01865 }
01866
01867 /**
01868   * @brief  This function handles I2S Communication Timeout.
01869   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01870   *         the configuration information for I2S module
01871   * @param  Flag Flag checked
01872   * @param  State Value of the flag expected
01873   * @param  Timeout Duration of the timeout
01874   * @retval HAL status
01875   */
01876 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
01877 {
01878   uint32_t tickstart;
01879
01880   /* Get tick */
01881   tickstart = HAL_GetTick();
01882
01883   /* Wait until flag is set to status*/
01884   while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01885   {
01886     if (Timeout != HAL_MAX_DELAY)
01887     {
01888       if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0UL))
01889       {
01890         /* Set the I2S State ready */
01891         hi2s->State = HAL_I2S_STATE_READY;
01892
01893         /* Process Unlocked */
01894         __HAL_UNLOCK(hi2s);
01895
01896         return HAL_TIMEOUT;
01897       }
01898     }
01899   }
01900   return HAL_OK;
01901 }
01902
01903 /**
01904   * @}
01905   */
01906
01907 /**
01908   * @}
01909   */
01910
01911 /**
01912   * @}
01913   */
01914
01915 #endif /* HAL_I2S_MODULE_ENABLED */
01916
01917 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s.h Source File

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stm32h7xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_I2S_H
00022 #define STM32H7xx_HAL_I2S_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2S
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup I2S_Exported_Types I2S Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief I2S Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Mode;                /*!< Specifies the I2S operating mode.
00050                                      This parameter can be a value of @ref I2S_Mode */
00051
00052   uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
00053                                      This parameter can be a value of @ref I2S_Standard */
00054
00055   uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
00056                                      This parameter can be a value of @ref I2S_Data_Format */
00057
00058   uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
00059                                      This parameter can be a value of @ref I2S_MCLK_Output */
00060
00061   uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
00062                                      This parameter can be a value of @ref I2S_Audio_Frequency */
00063
00064   uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
00065                                      This parameter can be a value of @ref I2S_Clock_Polarity */
00066
00067   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00068                                      This parameter can be a value of @ref I2S_MSB_LSB_transmission       */
00069
00070   uint32_t WSInversion;         /*!< Control the Word Select Inversion.
00071                                      This parameter can be a value of @ref I2S_WSInversion                */
00072
00073   uint32_t Data24BitAlignment;  /*!< Specifies the Data Padding for 24 bits data length
00074                                       This parameter can be a value of @ref I2S_Data_24Bit_Alignment       */
00075
00076   uint32_t MasterKeepIOState;   /*!< Control of Alternate function GPIOs state
00077                                      This parameter can be a value of @ref SPI_Master_Keep_IO_State */
00078
00079 } I2S_InitTypeDef;
00080
00081 /**
00082   * @brief  HAL State structures definition
00083   */
00084 typedef enum
00085 {
00086   HAL_I2S_STATE_RESET      = 0x00UL,  /*!< I2S not yet initialized or disabled                */
00087   HAL_I2S_STATE_READY      = 0x01UL,  /*!< I2S initialized and ready for use                  */
00088   HAL_I2S_STATE_BUSY       = 0x02UL,  /*!< I2S internal process is ongoing                    */
00089   HAL_I2S_STATE_BUSY_TX    = 0x03UL,  /*!< Data Transmission process is ongoing               */
00090   HAL_I2S_STATE_BUSY_RX    = 0x04UL,  /*!< Data Reception process is ongoing                  */
00091   HAL_I2S_STATE_TIMEOUT    = 0x06UL,  /*!< I2S timeout state                                  */
00092   HAL_I2S_STATE_ERROR      = 0x07UL   /*!< I2S error state                                    */
00093 } HAL_I2S_StateTypeDef;
00094
00095 /**
00096   * @brief I2S handle Structure definition
00097   */
00098 typedef struct __I2S_HandleTypeDef
00099 {
00100   SPI_TypeDef                *Instance;            /*!< I2S registers base address */
00101
00102   I2S_InitTypeDef            Init;                 /*!< I2S communication parameters */
00103
00104   uint16_t                   *pTxBuffPtr;          /*!< Pointer to I2S Tx transfer buffer */
00105
00106   __IO uint16_t              TxXferSize;           /*!< I2S Tx transfer size */
00107
00108   __IO uint16_t              TxXferCount;          /*!< I2S Tx transfer Counter */
00109
00110   uint16_t                   *pRxBuffPtr;          /*!< Pointer to I2S Rx transfer buffer */
00111
00112   __IO uint16_t              RxXferSize;           /*!< I2S Rx transfer size */
00113
00114   __IO uint16_t              RxXferCount;          /*!< I2S Rx transfer counter
00115                                                       (This field is initialized at the
00116                                                        same value as transfer size at the
00117                                                        beginning of the transfer and
00118                                                        decremented when a sample is received
00119                                                        NbSamplesReceived = RxBufferSize-RxBufferCount) */
00120
00121   void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
00122
00123   void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
00124
00125   DMA_HandleTypeDef          *hdmatx;              /*!< I2S Tx DMA handle parameters */
00126
00127   DMA_HandleTypeDef          *hdmarx;              /*!< I2S Rx DMA handle parameters */
00128
00129   __IO HAL_LockTypeDef       Lock;                 /*!< I2S locking object */
00130
00131   __IO HAL_I2S_StateTypeDef  State;                /*!< I2S communication state */
00132
00133   __IO uint32_t              ErrorCode;            /*!< I2S Error code
00134                                                         This parameter can be a value of @ref I2S_Error */
00135
00136 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00137   void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
00138   void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
00139   void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
00140   void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
00141   void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
00142   void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
00143   void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
00144
00145 #endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
00146 } I2S_HandleTypeDef;
00147
00148 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00149 /**
00150
00151   * @brief  HAL I2S Callback ID enumeration definition
00152   */
00153 typedef enum
00154 {
00155   HAL_I2S_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< I2S Tx Completed callback ID         */
00156   HAL_I2S_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< I2S Rx Completed callback ID         */
00157   HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< I2S Tx Half Completed callback ID    */
00158   HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< I2S Rx Half Completed callback ID    */
00159   HAL_I2S_ERROR_CB_ID                   = 0x06UL,    /*!< I2S Error callback ID                */
00160   HAL_I2S_MSPINIT_CB_ID                 = 0x07UL,    /*!< I2S Msp Init callback ID             */
00161   HAL_I2S_MSPDEINIT_CB_ID               = 0x08UL     /*!< I2S Msp DeInit callback ID           */
00162
00163 } HAL_I2S_CallbackIDTypeDef;
00164
00165 /**
00166   * @brief  HAL I2S Callback pointer definition
00167   */
00168 typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
00169
00170 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00177   * @{
00178   */
00179 /** @defgroup I2S_Error I2S Error
00180   * @{
00181   */
00182 #define HAL_I2S_ERROR_NONE               (0x00000000UL)  /*!< No error                          */
00183 #define HAL_I2S_ERROR_TIMEOUT            (0x00000001UL)  /*!< Timeout error                     */
00184 #define HAL_I2S_ERROR_OVR                (0x00000002UL)  /*!< OVR error                         */
00185 #define HAL_I2S_ERROR_UDR                (0x00000004UL)  /*!< UDR error                         */
00186 #define HAL_I2S_ERROR_DMA                (0x00000008UL)  /*!< DMA transfer error                */
00187 #define HAL_I2S_ERROR_PRESCALER          (0x00000010UL)  /*!< Prescaler Calculation error       */
00188 #define HAL_I2S_ERROR_FRE                (0x00000020UL)  /*!< FRE error                         */
00189 #define HAL_I2S_ERROR_NO_OGT             (0x00000040UL)  /*!< No On Going Transfer error        */
00190 #define HAL_I2S_ERROR_NOT_SUPPORTED      (0x00000080UL)  /*!< Requested operation not supported */
00191 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00192 #define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000100UL)  /*!< Invalid Callback error      */
00193 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup I2S_Mode I2S Mode
00199   * @{
00200   */
00201 #define I2S_MODE_SLAVE_TX                (0x00000000UL)
00202 #define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
00203 #define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
00204 #define I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
00205 #define I2S_MODE_SLAVE_FULLDUPLEX        (SPI_I2SCFGR_I2SCFG_2)
00206 #define I2S_MODE_MASTER_FULLDUPLEX       (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup I2S_Standard I2S Standard
00212   * @{
00213   */
00214 #define I2S_STANDARD_PHILIPS             (0x00000000UL)
00215 #define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
00216 #define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
00217 #define I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
00218 #define I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup I2S_Data_Format I2S Data Format
00224   * @{
00225   */
00226 #define I2S_DATAFORMAT_16B               (0x00000000UL)
00227 #define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
00228 #define I2S_DATAFORMAT_24B               (SPI_I2SCFGR_DATLEN_0)
00229 #define I2S_DATAFORMAT_32B               (SPI_I2SCFGR_DATLEN_1)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup I2S_MCLK_Output I2S MCLK Output
00235   * @{
00236   */
00237 #define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SCFGR_MCKOE)
00238 #define I2S_MCLKOUTPUT_DISABLE           (0x00000000UL)
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00244   * @{
00245   */
00246 #define I2S_AUDIOFREQ_192K               (192000UL)
00247 #define I2S_AUDIOFREQ_96K                (96000UL)
00248 #define I2S_AUDIOFREQ_48K                (48000UL)
00249 #define I2S_AUDIOFREQ_44K                (44100UL)
00250 #define I2S_AUDIOFREQ_32K                (32000UL)
00251 #define I2S_AUDIOFREQ_22K                (22050UL)
00252 #define I2S_AUDIOFREQ_16K                (16000UL)
00253 #define I2S_AUDIOFREQ_11K                (11025UL)
00254 #define I2S_AUDIOFREQ_8K                 (8000UL)
00255 #define I2S_AUDIOFREQ_DEFAULT            (2UL)
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
00261   * @{
00262   */
00263 #define I2S_CPOL_LOW                     (0x00000000UL)
00264 #define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
00270   * @{
00271   */
00272 #define I2S_FIRSTBIT_MSB                 (0x00000000UL)
00273 #define I2S_FIRSTBIT_LSB                 SPI_CFG2_LSBFRST
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup I2S_WSInversion I2S Word Select Inversion
00279   * @{
00280   */
00281 #define I2S_WS_INVERSION_DISABLE         (0x00000000UL)
00282 #define I2S_WS_INVERSION_ENABLE          SPI_I2SCFGR_WSINV
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
00288   * @{
00289   */
00290 #define I2S_DATA_24BIT_ALIGNMENT_RIGHT   (0x00000000UL)
00291 #define I2S_DATA_24BIT_ALIGNMENT_LEFT    SPI_I2SCFGR_DATFMT
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup I2S_Master_Keep_IO_State Keep IO State
00297   * @{
00298   */
00299 #define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
00300 #define I2S_MASTER_KEEP_IO_STATE_ENABLE  SPI_CFG2_AFCNTR
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00306   * @{
00307   */
00308 #define I2S_IT_RXP                       SPI_IER_RXPIE
00309 #define I2S_IT_TXP                       SPI_IER_TXPIE
00310 #define I2S_IT_UDR                       SPI_IER_UDRIE
00311 #define I2S_IT_OVR                       SPI_IER_OVRIE
00312 #define I2S_IT_FRE                       SPI_IER_TIFREIE
00313 #define I2S_IT_ERR                       (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00319   * @{
00320   */
00321 #define I2S_FLAG_RXP                     SPI_SR_RXP       /* I2S status flag : Rx-Packet available flag                 */
00322 #define I2S_FLAG_TXP                     SPI_SR_TXP       /* I2S status flag : Tx-Packet space available flag           */
00323 #define I2S_FLAG_UDR                     SPI_SR_UDR       /* I2S Error flag  : Underrun flag                            */
00324 #define I2S_FLAG_OVR                     SPI_SR_OVR       /* I2S Error flag  : Overrun flag                             */
00325 #define I2S_FLAG_FRE                     SPI_SR_TIFRE     /* I2S Error flag  : TI mode frame format error flag          */
00326
00327 #define I2S_FLAG_MASK                    (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /* Exported macros -----------------------------------------------------------*/
00337 /** @defgroup I2S_Exported_macros I2S Exported Macros
00338   * @{
00339   */
00340
00341 /** @brief  Reset I2S handle state
00342   * @param  __HANDLE__ specifies the I2S Handle.
00343   * @retval None
00344   */
00345 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00346 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00347                                                                     (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
00348                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00349                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00350                                                                   } while(0)
00351 #else
00352 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00353 #endif
00354
00355 /** @brief  Enable the specified SPI peripheral (in I2S mode).
00356   * @param  __HANDLE__ specifies the I2S Handle.
00357   * @retval None
00358   */
00359 #define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
00360
00361 /** @brief  Disable the specified SPI peripheral (in I2S mode).
00362   * @param  __HANDLE__ specifies the I2S Handle.
00363   * @retval None
00364   */
00365 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
00366
00367 /** @brief  Enable the specified I2S interrupts.
00368   * @param  __HANDLE__ specifies the I2S Handle.
00369   *        This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
00370   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00371   *         This parameter can be one of the following values:
00372   *            @arg I2S_IT_RXP : Rx-Packet available interrupt
00373   *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
00374   *            @arg I2S_IT_UDR : Underrun interrupt
00375   *            @arg I2S_IT_OVR : Overrun interrupt
00376   *            @arg I2S_IT_FRE : TI mode frame format error interrupt
00377   *            @arg I2S_IT_ERR : Error interrupt enable
00378   * @retval None
00379   */
00380 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00381
00382 /** @brief  Disable the specified I2S interrupts.
00383   * @param  __HANDLE__ specifies the I2S Handle.
00384   *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
00385   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00386   *         This parameter can be one of the following values:
00387   *            @arg I2S_IT_RXP : Rx-Packet available interrupt
00388   *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
00389   *            @arg I2S_IT_UDR : Underrun interrupt
00390   *            @arg I2S_IT_OVR : Overrun interrupt
00391   *            @arg I2S_IT_FRE : TI mode frame format error interrupt
00392   *            @arg I2S_IT_ERR : Error interrupt enable
00393   * @retval None
00394   */
00395 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00396
00397 /** @brief  Check if the specified I2S interrupt source is enabled or disabled.
00398   * @param  __HANDLE__ specifies the I2S Handle.
00399   *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
00400   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00401   *          This parameter can be one of the following values:
00402   *            @arg I2S_IT_RXP : Rx-Packet available interrupt
00403   *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
00404   *            @arg I2S_IT_UDR : Underrun interrupt
00405   *            @arg I2S_IT_OVR : Overrun interrupt
00406   *            @arg I2S_IT_FRE : TI mode frame format error interrupt
00407   *            @arg I2S_IT_ERR : Error interrupt enable
00408   * @retval The new state of __IT__ (TRUE or FALSE).
00409   */
00410 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00411
00412 /** @brief  Check whether the specified I2S flag is set or not.
00413   * @param  __HANDLE__ specifies the I2S Handle.
00414   *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
00415   * @param  __FLAG__ specifies the flag to check.
00416   *         This parameter can be one of the following values:
00417   *            @arg I2S_FLAG_RXP : Rx-Packet available flag
00418   *            @arg I2S_FLAG_TXP : Tx-Packet space available flag
00419   *            @arg I2S_FLAG_UDR : Underrun flag
00420   *            @arg I2S_FLAG_OVR : Overrun flag
00421   *            @arg I2S_FLAG_FRE : TI mode frame format error flag
00422   * @retval The new state of __FLAG__ (TRUE or FALSE).
00423   */
00424 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00425
00426 /** @brief Clear the I2S OVR pending flag.
00427   * @param  __HANDLE__ specifies the I2S Handle.
00428   * @retval None
00429   */
00430 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
00431
00432 /** @brief Clear the I2S UDR pending flag.
00433   * @param  __HANDLE__ specifies the I2S Handle.
00434   * @retval None
00435   */
00436 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
00437
00438 /** @brief  Clear the I2S FRE pending flag.
00439   * @param  __HANDLE__: specifies the I2S Handle.
00440   * @retval None
00441   */
00442 #define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
00443
00444 /**
00445   * @}
00446   */
00447
00448 /* Exported functions --------------------------------------------------------*/
00449 /** @addtogroup I2S_Exported_Functions
00450   * @{
00451   */
00452
00453 /** @addtogroup I2S_Exported_Functions_Group1
00454   * @{
00455   */
00456 /* Initialization/de-initialization functions  ********************************/
00457 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00458 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
00459 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00460 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00461
00462 /* Callbacks Register/UnRegister functions  ***********************************/
00463 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
00464 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
00465 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
00466 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00467 /**
00468   * @}
00469   */
00470
00471 /** @addtogroup I2S_Exported_Functions_Group2
00472   * @{
00473   */
00474 /* I/O operation functions  ***************************************************/
00475 /* Blocking mode: Polling */
00476 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00477 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00478
00479 /* Non-Blocking mode: Interrupt */
00480 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00481 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00482 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00483
00484 /* Non-Blocking mode: DMA */
00485 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00486 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00487
00488 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00489 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00490 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00491
00492 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00493 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00494 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00495 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00496 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00497 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00498 /**
00499   * @}
00500   */
00501
00502 /** @addtogroup I2S_Exported_Functions_Group3
00503   * @{
00504   */
00505 /* Peripheral Control and State functions  ************************************/
00506 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00507 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00508 /**
00509   * @}
00510   */
00511
00512 /**
00513   * @}
00514   */
00515
00516 /* Private types -------------------------------------------------------------*/
00517 /* Private variables ---------------------------------------------------------*/
00518 /* Private constants ---------------------------------------------------------*/
00519 /** @defgroup I2S_Private_Constants I2S Private Constants
00520   * @{
00521   */
00522
00523 /**
00524   * @}
00525   */
00526
00527 /* Private macros ------------------------------------------------------------*/
00528 /** @defgroup I2S_Private_Macros I2S Private Macros
00529   * @{
00530   */
00531
00532 /** @brief  Check whether the specified SPI flag is set or not.
00533   * @param  __SR__  copy of I2S SR register.
00534   * @param  __FLAG__ specifies the flag to check.
00535   *         This parameter can be one of the following values:
00536   *            @arg I2S_FLAG_RXP : Rx-Packet available flag
00537   *            @arg I2S_FLAG_TXP : Tx-Packet space available flag
00538   *            @arg I2S_FLAG_UDR : Underrun flag
00539   *            @arg I2S_FLAG_OVR : Overrun flag
00540   *            @arg I2S_FLAG_FRE : TI mode frame format error flag
00541   * @retval SET or RESET.
00542   */
00543 #define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
00544
00545 /** @brief  Check whether the specified SPI Interrupt is set or not.
00546   * @param  __IER__  copy of I2S IER register.
00547   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00548   *         This parameter can be one of the following values:
00549   *            @arg I2S_IT_RXP : Rx-Packet available interrupt
00550   *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
00551   *            @arg I2S_IT_UDR : Underrun interrupt
00552   *            @arg I2S_IT_OVR : Overrun interrupt
00553   *            @arg I2S_IT_FRE : TI mode frame format error interrupt
00554   *            @arg I2S_IT_ERR : Error interrupt enable
00555   * @retval SET or RESET.
00556   */
00557 #define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__)      ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00558
00559 /** @brief  Checks if I2S Mode parameter is in allowed range.
00560   * @param  __MODE__ specifies the I2S Mode.
00561   *         This parameter can be a value of @ref I2S_Mode
00562   * @retval None
00563   */
00564 #define IS_I2S_MODE(__MODE__)                       (((__MODE__) == I2S_MODE_SLAVE_TX)                   || \
00565                                                      ((__MODE__) == I2S_MODE_SLAVE_RX)                   || \
00566                                                      ((__MODE__) == I2S_MODE_MASTER_TX)                  || \
00567                                                      ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
00568                                                      ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)           || \
00569                                                      ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
00570
00571 #define IS_I2S_MASTER(__MODE__)                     (((__MODE__) == I2S_MODE_MASTER_TX)                  || \
00572                                                      ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
00573                                                      ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
00574
00575 #define IS_I2S_SLAVE(__MODE__)                      (((__MODE__) == I2S_MODE_SLAVE_TX)                  || \
00576                                                      ((__MODE__) == I2S_MODE_SLAVE_RX)                  || \
00577                                                      ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
00578
00579 #define IS_I2S_STANDARD(__STANDARD__)               (((__STANDARD__) == I2S_STANDARD_PHILIPS)            || \
00580                                                      ((__STANDARD__) == I2S_STANDARD_MSB)                || \
00581                                                      ((__STANDARD__) == I2S_STANDARD_LSB)                || \
00582                                                      ((__STANDARD__) == I2S_STANDARD_PCM_SHORT)          || \
00583                                                      ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
00584
00585 #define IS_I2S_DATA_FORMAT(__FORMAT__)              (((__FORMAT__) == I2S_DATAFORMAT_16B)                || \
00586                                                      ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)       || \
00587                                                      ((__FORMAT__) == I2S_DATAFORMAT_24B)                || \
00588                                                      ((__FORMAT__) == I2S_DATAFORMAT_32B))
00589
00590 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__)              (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)             || \
00591                                                      ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
00592
00593 #define IS_I2S_AUDIO_FREQ(__FREQ__)                ((((__FREQ__) >= I2S_AUDIOFREQ_8K)                    && \
00594                                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K))                 || \
00595                                                      ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
00596
00597 #define IS_I2S_CPOL(__CPOL__)                       (((__CPOL__) == I2S_CPOL_LOW)                        || \
00598                                                      ((__CPOL__) == I2S_CPOL_HIGH))
00599
00600 #define IS_I2S_FIRST_BIT(__BIT__)                   (((__BIT__) == I2S_FIRSTBIT_MSB)                     || \
00601                                                      ((__BIT__) == I2S_FIRSTBIT_LSB))
00602
00603 #define IS_I2S_WS_INVERSION(__WSINV__)              (((__WSINV__) == I2S_WS_INVERSION_DISABLE)           || \
00604                                                      ((__WSINV__) == I2S_WS_INVERSION_ENABLE))
00605
00606 #define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__)  (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
00607                                                      ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
00608
00609 #define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__)     (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE)  || \
00610                                                      ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
00611
00612
00613 /**
00614   * @}
00615   */
00616
00617 /**
00618   * @}
00619   */
00620
00621 /**
00622   * @}
00623   */
00624
00625 #ifdef __cplusplus
00626 }
00627 #endif
00628
00629 #endif /* STM32H7xx_HAL_I2S_H */
00630
00631 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s_ex.c Source File

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stm32h7xx_hal_i2s_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2S HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2S extension peripheral:
00008   *           + Extension features Functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                     ##### I2S Extension features #####
00013   ==============================================================================
00014   [..]
00015      (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
00016          data simultaneously using two data lines. Each SPI peripheral has an extended block
00017          called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
00018      (#) The extension block is not a full SPI IP, it is used only as I2S slave to
00019          implement full duplex mode. The extension block uses the same clock sources
00020          as its master.
00021
00022      (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
00023
00024      [..]
00025        (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
00026          I2Sx can be I2S2 or I2S3.
00027
00028                   ##### How to use this driver #####
00029  ===============================================================================
00030  [..]
00031    Three operation modes are available within this driver :
00032
00033    *** Polling mode IO operation ***
00034    =================================
00035    [..]
00036      (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
00037
00038    *** Interrupt mode IO operation ***
00039    ===================================
00040    [..]
00041      (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
00042      (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
00043          add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
00044      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00045          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00046
00047    *** DMA mode IO operation ***
00048    ==============================
00049    [..]
00050      (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
00051      (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
00052          add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
00053      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00054          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00055   @endverbatim
00056
00057  Additional Figure: The Extended block uses the same clock sources as its master.
00058
00059                 +-----------------------+
00060     I2Sx_SCK    |                       |
00061  ----------+-->|          I2Sx         |------------------->I2Sx_SD(in/out)
00062          +--|-->|                       |
00063         |   |   +-----------------------+
00064         |   |
00065  I2S_WS |   |
00066  ------>|   |
00067         |   |   +-----------------------+
00068         |   +-->|                       |
00069         |       |       I2Sx_ext        |------------------->I2Sx_extSD(in/out)
00070          +----->|                       |
00071                 +-----------------------+
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00076   * All rights reserved.</center></h2>
00077   *
00078   * This software component is licensed by ST under BSD 3-Clause license,
00079   * the "License"; You may not use this file except in compliance with the
00080   * License. You may obtain a copy of the License at:
00081   *                        opensource.org/licenses/BSD-3-Clause
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32h7xx_hal.h"
00088
00089 /** @addtogroup STM32H7xx_HAL_Driver
00090   * @{
00091   */
00092
00093 #ifdef HAL_I2S_MODULE_ENABLED
00094
00095 /** @defgroup I2SEx I2SEx
00096   * @brief I2S Extended HAL module driver
00097   * @{
00098   */
00099
00100 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
00101
00102 /* Private typedef -----------------------------------------------------------*/
00103 /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
00104   * @{
00105   */
00106 typedef enum
00107 {
00108   I2S_USE_I2S      = 0x00U,   /*!< I2Sx should be used      */
00109   I2S_USE_I2SEXT   = 0x01U,   /*!< I2Sx_ext should be used  */
00110 } I2S_UseTypeDef;
00111 /**
00112   * @}
00113   */
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
00119   * @{
00120   */
00121 static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
00122 static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
00123 static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
00124 static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
00125 static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
00126 static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
00127 static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
00128 static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
00129     uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private functions ---------------------------------------------------------*/
00139 /* Exported functions --------------------------------------------------------*/
00140
00141 /** @addtogroup I2SEx I2SEx
00142   * @{
00143   */
00144
00145 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
00146   * @{
00147   */
00148
00149 /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
00150   *  @brief   I2SEx IO operation functions
00151   *
00152 @verbatim
00153  ===============================================================================
00154                        ##### IO operation functions#####
00155  ===============================================================================
00156     [..]
00157     This subsection provides a set of functions allowing to manage the I2S data
00158     transfers.
00159
00160     (#) There are two modes of transfer:
00161        (++) Blocking mode : The communication is performed in the polling mode.
00162             The status of all data processing is returned by the same function
00163             after finishing transfer.
00164        (++) No-Blocking mode : The communication is performed using Interrupts
00165             or DMA. These functions return the status of the transfer startup.
00166             The end of the data processing will be indicated through the
00167             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00168             using DMA mode.
00169
00170     (#) Blocking mode functions are :
00171         (++) HAL_I2SEx_TransmitReceive()
00172
00173     (#) No-Blocking mode functions with Interrupt are :
00174         (++) HAL_I2SEx_TransmitReceive_IT()
00175         (++) HAL_I2SEx_FullDuplex_IRQHandler()
00176
00177     (#) No-Blocking mode functions with DMA are :
00178         (++) HAL_I2SEx_TransmitReceive_DMA()
00179
00180     (#) A set of Transfer Complete Callback are provided in non Blocking mode:
00181         (++) HAL_I2SEx_TxRxCpltCallback()
00182 @endverbatim
00183   * @{
00184   */
00185 /**
00186   * @brief  Full-Duplex Transmit/Receive data in blocking mode.
00187   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00188   *         the configuration information for I2S module
00189   * @param  pTxData a 16-bit pointer to the Transmit data buffer.
00190   * @param  pRxData a 16-bit pointer to the Receive data buffer.
00191   * @param  Size number of data sample to be sent:
00192   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00193   *         configuration phase, the Size parameter means the number of 16-bit data length
00194   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00195   *         the Size parameter means the number of 16-bit data length.
00196   * @param  Timeout Timeout duration
00197   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00198   *         between Master and Slave(example: audio streaming).
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00202                                             uint16_t Size, uint32_t Timeout)
00203 {
00204   uint32_t tmp1 = 0U;
00205   HAL_StatusTypeDef errorcode = HAL_OK;
00206
00207   if (hi2s->State != HAL_I2S_STATE_READY)
00208   {
00209     errorcode = HAL_BUSY;
00210     goto error;
00211   }
00212
00213   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00214   {
00215     return  HAL_ERROR;
00216   }
00217
00218   /* Process Locked */
00219   __HAL_LOCK(hi2s);
00220
00221   tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00222   /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00223      is selected during the I2S configuration phase, the Size parameter means the number
00224      of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00225      frame is selected the Size parameter means the number of 16-bit data length. */
00226   if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00227   {
00228     hi2s->TxXferSize  = (Size << 1U);
00229     hi2s->TxXferCount = (Size << 1U);
00230     hi2s->RxXferSize  = (Size << 1U);
00231     hi2s->RxXferCount = (Size << 1U);
00232   }
00233   else
00234   {
00235     hi2s->TxXferSize  = Size;
00236     hi2s->TxXferCount = Size;
00237     hi2s->RxXferSize  = Size;
00238     hi2s->RxXferCount = Size;
00239   }
00240
00241   /* Set state and reset error code */
00242   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00243   hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00244
00245   tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00246   /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00247   if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00248   {
00249     /* Prepare the First Data before enabling the I2S */
00250     hi2s->Instance->DR = (*pTxData++);
00251     hi2s->TxXferCount--;
00252
00253     /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00254     __HAL_I2SEXT_ENABLE(hi2s);
00255
00256     /* Enable I2Sx peripheral */
00257     __HAL_I2S_ENABLE(hi2s);
00258
00259     /* Check if Master Receiver mode is selected */
00260     if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
00261     {
00262       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00263       access to the SPI_SR register. */
00264       __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
00265     }
00266
00267     while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
00268     {
00269       if (hi2s->TxXferCount > 0U)
00270       {
00271         /* Wait until TXE flag is set */
00272         if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
00273         {
00274           /* Set the error code */
00275           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00276           errorcode = HAL_ERROR;
00277           goto error;
00278         }
00279         /* Write Data on DR register */
00280         hi2s->Instance->DR = (*pTxData++);
00281         hi2s->TxXferCount--;
00282
00283         /* Check if an underrun occurs */
00284         if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
00285         {
00286           /* Clear Underrun flag */
00287           __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00288
00289           /* Set the error code */
00290           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00291         }
00292       }
00293       if (hi2s->RxXferCount > 0U)
00294       {
00295         /* Wait until RXNE flag is set */
00296         if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
00297         {
00298           /* Set the error code */
00299           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00300           errorcode = HAL_ERROR;
00301           goto error;
00302         }
00303         /* Read Data from DR register */
00304         (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
00305         hi2s->RxXferCount--;
00306
00307         /* Check if an overrun occurs */
00308         if (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00309         {
00310           /* Clear Overrun flag */
00311           __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00312
00313           /* Set the error code */
00314           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00315         }
00316       }
00317     }
00318   }
00319   /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00320   else
00321   {
00322     /* Prepare the First Data before enabling the I2S */
00323     I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
00324     hi2s->TxXferCount--;
00325
00326     /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
00327     __HAL_I2SEXT_ENABLE(hi2s);
00328
00329     /* Enable I2S peripheral before the I2Sext*/
00330     __HAL_I2S_ENABLE(hi2s);
00331
00332     /* Check if Master Receiver mode is selected */
00333     if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00334     {
00335       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00336       access to the SPI_SR register. */
00337       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00338     }
00339
00340     while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
00341     {
00342       if (hi2s->TxXferCount > 0U)
00343       {
00344         /* Wait until TXE flag is set */
00345         if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
00346         {
00347           /* Set the error code */
00348           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00349           errorcode = HAL_ERROR;
00350           goto error;
00351         }
00352         /* Write Data on DR register */
00353         I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
00354         hi2s->TxXferCount--;
00355
00356         /* Check if an underrun occurs */
00357         if ((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
00358         {
00359           /* Clear Underrun flag */
00360           __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00361
00362           /* Set the error code */
00363           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00364         }
00365       }
00366       if (hi2s->RxXferCount > 0U)
00367       {
00368         /* Wait until RXNE flag is set */
00369         if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
00370         {
00371           /* Set the error code */
00372           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00373           errorcode = HAL_ERROR;
00374           goto error;
00375         }
00376         /* Read Data from DR register */
00377         (*pRxData++) = hi2s->Instance->DR;
00378         hi2s->RxXferCount--;
00379
00380         /* Check if an overrun occurs */
00381         if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00382         {
00383           /* Clear Overrun flag */
00384           __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00385
00386           /* Set the error code */
00387           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00388         }
00389       }
00390     }
00391   }
00392
00393   if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
00394   {
00395     errorcode = HAL_ERROR;
00396   }
00397
00398 error :
00399   hi2s->State = HAL_I2S_STATE_READY;
00400   __HAL_UNLOCK(hi2s);
00401   return errorcode;
00402 }
00403
00404 /**
00405   * @brief  Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
00406   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00407   *         the configuration information for I2S module
00408   * @param  pTxData a 16-bit pointer to the Transmit data buffer.
00409   * @param  pRxData a 16-bit pointer to the Receive data buffer.
00410   * @param  Size number of data sample to be sent:
00411   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00412   *         configuration phase, the Size parameter means the number of 16-bit data length
00413   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00414   *         the Size parameter means the number of 16-bit data length.
00415   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00416   *         between Master and Slave(example: audio streaming).
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00420                                                uint16_t Size)
00421 {
00422   uint32_t tmp1 = 0U;
00423   HAL_StatusTypeDef errorcode = HAL_OK;
00424
00425   if (hi2s->State != HAL_I2S_STATE_READY)
00426   {
00427     errorcode = HAL_BUSY;
00428     goto error;
00429   }
00430
00431   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00432   {
00433     return  HAL_ERROR;
00434   }
00435
00436   /* Process Locked */
00437   __HAL_LOCK(hi2s);
00438
00439   hi2s->pTxBuffPtr = pTxData;
00440   hi2s->pRxBuffPtr = pRxData;
00441
00442   tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00443   /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00444   is selected during the I2S configuration phase, the Size parameter means the number
00445   of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00446   frame is selected the Size parameter means the number of 16-bit data length. */
00447   if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00448   {
00449     hi2s->TxXferSize  = (Size << 1U);
00450     hi2s->TxXferCount = (Size << 1U);
00451     hi2s->RxXferSize  = (Size << 1U);
00452     hi2s->RxXferCount = (Size << 1U);
00453   }
00454   else
00455   {
00456     hi2s->TxXferSize  = Size;
00457     hi2s->TxXferCount = Size;
00458     hi2s->RxXferSize  = Size;
00459     hi2s->RxXferCount = Size;
00460   }
00461
00462   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00463   hi2s->State     = HAL_I2S_STATE_BUSY_TX_RX;
00464
00465   /* Set the function for IT treatment */
00466   if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
00467   {
00468     /* Enable I2Sext RXNE and ERR interrupts */
00469     __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00470
00471     /* Enable I2Sx TXE and ERR interrupts */
00472     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00473
00474     /* Transmit First data */
00475     hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
00476     hi2s->TxXferCount--;
00477
00478     if (hi2s->TxXferCount == 0U)
00479     {
00480       /* Disable TXE and ERR interrupt */
00481       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00482     }
00483   }
00484   else  /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00485   {
00486     /* Enable I2Sext TXE and ERR interrupts */
00487     __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00488
00489     /* Enable I2Sext RXNE and ERR interrupts */
00490     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00491
00492     /* Transmit First data */
00493     I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
00494     hi2s->TxXferCount--;
00495
00496     if (hi2s->TxXferCount == 0U)
00497     {
00498       /* Disable I2Sext TXE and ERR interrupt */
00499       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00500     }
00501   }
00502
00503   /* Enable I2Sext peripheral */
00504   __HAL_I2SEXT_ENABLE(hi2s);
00505
00506   /* Enable I2S peripheral */
00507   __HAL_I2S_ENABLE(hi2s);
00508
00509 error :
00510   __HAL_UNLOCK(hi2s);
00511   return errorcode;
00512 }
00513
00514 /**
00515   * @brief  Full-Duplex Transmit/Receive data in non-blocking mode using DMA
00516   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00517   *         the configuration information for I2S module
00518   * @param  pTxData a 16-bit pointer to the Transmit data buffer.
00519   * @param  pRxData a 16-bit pointer to the Receive data buffer.
00520   * @param  Size number of data sample to be sent:
00521   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00522   *         configuration phase, the Size parameter means the number of 16-bit data length
00523   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00524   *         the Size parameter means the number of 16-bit data length.
00525   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00526   *         between Master and Slave(example: audio streaming).
00527   * @retval HAL status
00528   */
00529 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00530                                                 uint16_t Size)
00531 {
00532   uint32_t *tmp = NULL;
00533   uint32_t tmp1 = 0U;
00534   HAL_StatusTypeDef errorcode = HAL_OK;
00535
00536   if (hi2s->State != HAL_I2S_STATE_READY)
00537   {
00538     errorcode = HAL_BUSY;
00539     goto error;
00540   }
00541
00542   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00543   {
00544     return  HAL_ERROR;
00545   }
00546
00547   /* Process Locked */
00548   __HAL_LOCK(hi2s);
00549
00550   hi2s->pTxBuffPtr = pTxData;
00551   hi2s->pRxBuffPtr = pRxData;
00552
00553   tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00554   /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00555   is selected during the I2S configuration phase, the Size parameter means the number
00556   of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00557   frame is selected the Size parameter means the number of 16-bit data length. */
00558   if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00559   {
00560     hi2s->TxXferSize  = (Size << 1U);
00561     hi2s->TxXferCount = (Size << 1U);
00562     hi2s->RxXferSize  = (Size << 1U);
00563     hi2s->RxXferCount = (Size << 1U);
00564   }
00565   else
00566   {
00567     hi2s->TxXferSize  = Size;
00568     hi2s->TxXferCount = Size;
00569     hi2s->RxXferSize  = Size;
00570     hi2s->RxXferCount = Size;
00571   }
00572
00573   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00574   hi2s->State     = HAL_I2S_STATE_BUSY_TX_RX;
00575
00576   /* Set the I2S Rx DMA Half transfer complete callback */
00577   hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
00578
00579   /* Set the I2S Rx DMA transfer complete callback */
00580   hi2s->hdmarx->XferCpltCallback  = I2SEx_TxRxDMACplt;
00581
00582   /* Set the I2S Rx DMA error callback */
00583   hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
00584
00585   /* Set the I2S Tx DMA Half transfer complete callback */
00586   hi2s->hdmatx->XferHalfCpltCallback  = I2SEx_TxRxDMAHalfCplt;
00587
00588   /* Set the I2S Tx DMA transfer complete callback */
00589   hi2s->hdmatx->XferCpltCallback  = I2SEx_TxRxDMACplt;
00590
00591   /* Set the I2S Tx DMA error callback */
00592   hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
00593
00594   tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00595   /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00596   if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00597   {
00598     /* Enable the Rx DMA Stream */
00599     tmp = (uint32_t *)&pRxData;
00600     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
00601
00602     /* Enable Rx DMA Request */
00603     SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
00604
00605     /* Enable the Tx DMA Stream */
00606     tmp = (uint32_t *)&pTxData;
00607     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00608
00609     /* Enable Tx DMA Request */
00610     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
00611
00612     /* Check if the I2S is already enabled */
00613     if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00614     {
00615       /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00616       __HAL_I2SEXT_ENABLE(hi2s);
00617
00618       /* Enable I2S peripheral after the I2Sext */
00619       __HAL_I2S_ENABLE(hi2s);
00620     }
00621   }
00622   else
00623   {
00624     /* Check if Master Receiver mode is selected */
00625     if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00626     {
00627       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00628       access to the SPI_SR register. */
00629       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00630     }
00631     /* Enable the Tx DMA Stream */
00632     tmp = (uint32_t *)&pTxData;
00633     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
00634
00635     /* Enable Tx DMA Request */
00636     SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
00637
00638     /* Enable the Rx DMA Stream */
00639     tmp = (uint32_t *)&pRxData;
00640     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
00641
00642     /* Enable Rx DMA Request */
00643     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
00644
00645     /* Check if the I2S is already enabled */
00646     if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00647     {
00648       /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
00649       __HAL_I2SEXT_ENABLE(hi2s);
00650       /* Enable I2S peripheral before the I2Sext */
00651       __HAL_I2S_ENABLE(hi2s);
00652     }
00653   }
00654
00655 error :
00656   __HAL_UNLOCK(hi2s);
00657   return errorcode;
00658 }
00659
00660 /**
00661   * @brief  This function handles I2S/I2Sext interrupt requests in full-duplex mode.
00662   * @param  hi2s I2S handle
00663   * @retval HAL status
00664   */
00665 void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
00666 {
00667   __IO uint32_t i2ssr     = hi2s->Instance->SR;
00668   __IO uint32_t i2sextsr  = I2SxEXT(hi2s->Instance)->SR;
00669   __IO uint32_t i2scr2    = hi2s->Instance->CR2;
00670   __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2;
00671
00672   /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00673   if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
00674   {
00675     /* I2S in mode Transmitter -------------------------------------------------*/
00676     if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET))
00677     {
00678       /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
00679       the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
00680       I2SEx_TxISR_I2S(hi2s);
00681     }
00682
00683     /* I2Sext in mode Receiver -----------------------------------------------*/
00684     if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET))
00685     {
00686       /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
00687       the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
00688       I2SEx_RxISR_I2SExt(hi2s);
00689     }
00690
00691     /* I2Sext Overrun error interrupt occurred --------------------------------*/
00692     if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
00693     {
00694       /* Disable RXNE and ERR interrupt */
00695       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00696
00697       /* Disable TXE and ERR interrupt */
00698       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00699
00700       /* Clear Overrun flag */
00701       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00702
00703       /* Set the I2S State ready */
00704       hi2s->State = HAL_I2S_STATE_READY;
00705
00706       /* Set the error code and execute error callback*/
00707       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00708       /* Call user error callback */
00709 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00710       hi2s->ErrorCallback(hi2s);
00711 #else
00712       HAL_I2S_ErrorCallback(hi2s);
00713 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00714     }
00715
00716     /* I2S Underrun error interrupt occurred ----------------------------------*/
00717     if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
00718     {
00719       /* Disable TXE and ERR interrupt */
00720       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00721
00722       /* Disable RXNE and ERR interrupt */
00723       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00724
00725       /* Clear underrun flag */
00726       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00727
00728       /* Set the I2S State ready */
00729       hi2s->State = HAL_I2S_STATE_READY;
00730
00731       /* Set the error code and execute error callback*/
00732       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00733       /* Call user error callback */
00734 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00735       hi2s->ErrorCallback(hi2s);
00736 #else
00737       HAL_I2S_ErrorCallback(hi2s);
00738 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00739     }
00740   }
00741   /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00742   else
00743   {
00744     /* I2Sext in mode Transmitter ----------------------------------------------*/
00745     if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET))
00746     {
00747       /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
00748       the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
00749       I2SEx_TxISR_I2SExt(hi2s);
00750     }
00751
00752     /* I2S in mode Receiver --------------------------------------------------*/
00753     if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET))
00754     {
00755       /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
00756       the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
00757       I2SEx_RxISR_I2S(hi2s);
00758     }
00759
00760     /* I2S Overrun error interrupt occurred -------------------------------------*/
00761     if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET))
00762     {
00763       /* Disable RXNE and ERR interrupt */
00764       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00765
00766       /* Disable TXE and ERR interrupt */
00767       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00768
00769       /* Set the I2S State ready */
00770       hi2s->State = HAL_I2S_STATE_READY;
00771
00772       /* Set the error code and execute error callback*/
00773       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00774       /* Call user error callback */
00775 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00776       hi2s->ErrorCallback(hi2s);
00777 #else
00778       HAL_I2S_ErrorCallback(hi2s);
00779 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00780     }
00781
00782     /* I2Sext Underrun error interrupt occurred -------------------------------*/
00783     if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
00784     {
00785       /* Disable TXE and ERR interrupt */
00786       __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00787
00788       /* Disable RXNE and ERR interrupt */
00789       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00790
00791       /* Set the I2S State ready */
00792       hi2s->State = HAL_I2S_STATE_READY;
00793
00794       /* Set the error code and execute error callback*/
00795       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00796       /* Call user error callback */
00797 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00798       hi2s->ErrorCallback(hi2s);
00799 #else
00800       HAL_I2S_ErrorCallback(hi2s);
00801 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00802     }
00803   }
00804 }
00805
00806 /**
00807   * @brief  Tx and Rx Transfer half completed callback
00808   * @param  hi2s I2S handle
00809   * @retval None
00810   */
00811 __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
00812 {
00813   /* Prevent unused argument(s) compilation warning */
00814   UNUSED(hi2s);
00815
00816   /* NOTE : This function Should not be modified, when the callback is needed,
00817             the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file
00818    */
00819 }
00820
00821 /**
00822   * @brief  Tx and Rx Transfer completed callback
00823   * @param  hi2s I2S handle
00824   * @retval None
00825   */
00826 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
00827 {
00828   /* Prevent unused argument(s) compilation warning */
00829   UNUSED(hi2s);
00830
00831   /* NOTE : This function should not be modified, when the callback is needed,
00832             the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
00833    */
00834 }
00835
00836 /**
00837   * @}
00838   */
00839
00840 /**
00841   * @}
00842   */
00843
00844 /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
00845   * @{
00846   */
00847
00848 /**
00849   * @brief  DMA I2S transmit receive process half complete callback
00850   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00851   *               the configuration information for the specified DMA module.
00852   * @retval None
00853   */
00854 static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
00855 {
00856   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00857
00858   /* Call user TxRx Half complete callback */
00859 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00860   hi2s->TxRxHalfCpltCallback(hi2s);
00861 #else
00862   HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
00863 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00864 }
00865
00866 /**
00867   * @brief  DMA I2S transmit receive process complete callback
00868   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00869   *               the configuration information for the specified DMA module.
00870   * @retval None
00871   */
00872 static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
00873 {
00874   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00875
00876   /* if DMA is configured in DMA_NORMAL mode */
00877   if (hdma->Init.Mode == DMA_NORMAL)
00878   {
00879     if (hi2s->hdmarx == hdma)
00880     {
00881       /* Disable Rx DMA Request */
00882       if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
00883           ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
00884       {
00885         CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
00886       }
00887       else
00888       {
00889         CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
00890       }
00891
00892       hi2s->RxXferCount = 0U;
00893
00894       if (hi2s->TxXferCount == 0U)
00895       {
00896         hi2s->State = HAL_I2S_STATE_READY;
00897
00898         /* Call user TxRx complete callback */
00899 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00900         hi2s->TxRxCpltCallback(hi2s);
00901 #else
00902         HAL_I2SEx_TxRxCpltCallback(hi2s);
00903 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00904       }
00905     }
00906
00907     if (hi2s->hdmatx == hdma)
00908     {
00909       /* Disable Tx DMA Request */
00910       if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
00911           ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
00912       {
00913         CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
00914       }
00915       else
00916       {
00917         CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
00918       }
00919
00920       hi2s->TxXferCount = 0U;
00921
00922       if (hi2s->RxXferCount == 0U)
00923       {
00924         hi2s->State = HAL_I2S_STATE_READY;
00925
00926         /* Call user TxRx complete callback */
00927 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00928         hi2s->TxRxCpltCallback(hi2s);
00929 #else
00930         HAL_I2SEx_TxRxCpltCallback(hi2s);
00931 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00932       }
00933     }
00934   }
00935 }
00936
00937 /**
00938   * @brief  DMA I2S communication error callback
00939   * @param  hdma DMA handle
00940   * @retval None
00941   */
00942 static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
00943 {
00944   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00945
00946   /* Disable Rx and Tx DMA Request */
00947   CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00948   CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
00949
00950   hi2s->TxXferCount = 0U;
00951   hi2s->RxXferCount = 0U;
00952
00953   hi2s->State = HAL_I2S_STATE_READY;
00954
00955   /* Set the error code and execute error callback*/
00956   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
00957   /* Call user error callback */
00958 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00959   hi2s->ErrorCallback(hi2s);
00960 #else
00961   HAL_I2S_ErrorCallback(hi2s);
00962 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00963 }
00964
00965 /**
00966   * @brief  I2S Full-Duplex IT handler transmit function
00967   * @param  hi2s I2S handle
00968   * @retval None
00969   */
00970 static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s)
00971 {
00972   /* Write Data on DR register */
00973   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
00974   hi2s->TxXferCount--;
00975
00976   if (hi2s->TxXferCount == 0U)
00977   {
00978     /* Disable TXE and ERR interrupt */
00979     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00980
00981     if (hi2s->RxXferCount == 0U)
00982     {
00983       hi2s->State = HAL_I2S_STATE_READY;
00984       /* Call user TxRx complete callback */
00985 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00986       hi2s->TxRxCpltCallback(hi2s);
00987 #else
00988       HAL_I2SEx_TxRxCpltCallback(hi2s);
00989 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00990     }
00991   }
00992 }
00993
00994 /**
00995   * @brief  I2SExt Full-Duplex IT handler transmit function
00996   * @param  hi2s I2S handle
00997   * @retval None
00998   */
00999 static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s)
01000 {
01001   /* Write Data on DR register */
01002   I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
01003   hi2s->TxXferCount--;
01004
01005   if (hi2s->TxXferCount == 0U)
01006   {
01007     /* Disable I2Sext TXE and ERR interrupt */
01008     __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01009
01010     if (hi2s->RxXferCount == 0U)
01011     {
01012       hi2s->State = HAL_I2S_STATE_READY;
01013       /* Call user TxRx complete callback */
01014 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01015       hi2s->TxRxCpltCallback(hi2s);
01016 #else
01017       HAL_I2SEx_TxRxCpltCallback(hi2s);
01018 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01019     }
01020   }
01021 }
01022
01023 /**
01024   * @brief  I2S Full-Duplex IT handler receive function
01025   * @param  hi2s I2S handle
01026   * @retval None
01027   */
01028 static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s)
01029 {
01030   /* Read Data from DR register */
01031   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01032   hi2s->RxXferCount--;
01033
01034   if (hi2s->RxXferCount == 0U)
01035   {
01036     /* Disable RXNE and ERR interrupt */
01037     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01038
01039     if (hi2s->TxXferCount == 0U)
01040     {
01041       hi2s->State = HAL_I2S_STATE_READY;
01042       /* Call user TxRx complete callback */
01043 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01044       hi2s->TxRxCpltCallback(hi2s);
01045 #else
01046       HAL_I2SEx_TxRxCpltCallback(hi2s);
01047 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01048     }
01049   }
01050 }
01051
01052 /**
01053   * @brief  I2SExt Full-Duplex IT handler receive function
01054   * @param  hi2s I2S handle
01055   * @retval None
01056   */
01057 static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
01058 {
01059   /* Read Data from DR register */
01060   (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
01061   hi2s->RxXferCount--;
01062
01063   if (hi2s->RxXferCount == 0U)
01064   {
01065     /* Disable I2Sext RXNE and ERR interrupt */
01066     __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01067
01068     if (hi2s->TxXferCount == 0U)
01069     {
01070       hi2s->State = HAL_I2S_STATE_READY;
01071       /* Call user TxRx complete callback */
01072 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01073       hi2s->TxRxCpltCallback(hi2s);
01074 #else
01075       HAL_I2SEx_TxRxCpltCallback(hi2s);
01076 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01077     }
01078   }
01079 }
01080
01081 /**
01082   * @brief This function handles I2S Communication Timeout.
01083   * @param hi2s I2S handle
01084   * @param Flag Flag checked
01085   * @param State Value of the flag expected
01086   * @param Timeout Duration of the timeout
01087   * @param i2sUsed I2S instance reference
01088   * @retval HAL status
01089   */
01090 static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
01091     uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
01092 {
01093   uint32_t tickstart = HAL_GetTick();
01094
01095   if (i2sUsed == I2S_USE_I2S)
01096   {
01097     /* Wait until flag is reset */
01098     while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01099     {
01100       if (Timeout != HAL_MAX_DELAY)
01101       {
01102         if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01103         {
01104           /* Set the I2S State ready */
01105           hi2s->State = HAL_I2S_STATE_READY;
01106
01107           /* Process Unlocked */
01108           __HAL_UNLOCK(hi2s);
01109
01110           return HAL_TIMEOUT;
01111         }
01112       }
01113     }
01114   }
01115   else /* i2sUsed == I2S_USE_I2SEXT */
01116   {
01117     /* Wait until flag is reset */
01118     while (((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01119     {
01120       if (Timeout != HAL_MAX_DELAY)
01121       {
01122         if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01123         {
01124           /* Set the I2S State ready */
01125           hi2s->State = HAL_I2S_STATE_READY;
01126
01127           /* Process Unlocked */
01128           __HAL_UNLOCK(hi2s);
01129
01130           return HAL_TIMEOUT;
01131         }
01132       }
01133     }
01134   }
01135   return HAL_OK;
01136 }
01137
01138 /**
01139   * @}
01140   */
01141 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
01142
01143 /**
01144   * @}
01145   */
01146 #endif /* HAL_I2S_MODULE_ENABLED */
01147
01148 /**
01149   * @}
01150   */
01151
01152 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_i2s_ex.h Source File

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stm32h7xx_hal_i2s_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_I2S_EX_H
00022 #define STM32H7xx_HAL_I2S_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
00035 /** @addtogroup I2SEx I2SEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
00043   * @{
00044   */
00045
00046 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
00047
00048 /** @brief  Enable or disable the specified I2SExt peripheral.
00049   * @param  __HANDLE__ specifies the I2S Handle.
00050   * @retval None
00051   */
00052 #define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
00053 #define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
00054
00055 /** @brief  Enable or disable the specified I2SExt interrupts.
00056   * @param  __HANDLE__ specifies the I2S Handle.
00057   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00058   *        This parameter can be one of the following values:
00059   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00060   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00061   *            @arg I2S_IT_ERR: Error interrupt enable
00062   * @retval None
00063   */
00064 #define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
00065 #define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
00066
00067 /** @brief  Checks if the specified I2SExt interrupt source is enabled or disabled.
00068   * @param  __HANDLE__ specifies the I2S Handle.
00069   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00070   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00071   *          This parameter can be one of the following values:
00072   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00073   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00074   *            @arg I2S_IT_ERR: Error interrupt enable
00075   * @retval The new state of __IT__ (TRUE or FALSE).
00076   */
00077 #define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00078
00079 /** @brief  Checks whether the specified I2SExt flag is set or not.
00080   * @param  __HANDLE__ specifies the I2S Handle.
00081   * @param  __FLAG__ specifies the flag to check.
00082   *        This parameter can be one of the following values:
00083   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00084   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00085   *            @arg I2S_FLAG_UDR: Underrun flag
00086   *            @arg I2S_FLAG_OVR: Overrun flag
00087   *            @arg I2S_FLAG_FRE: Frame error flag
00088   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00089   *            @arg I2S_FLAG_BSY: Busy flag
00090   * @retval The new state of __FLAG__ (TRUE or FALSE).
00091   */
00092 #define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
00093
00094 /** @brief Clears the I2SExt OVR pending flag.
00095   * @param  __HANDLE__ specifies the I2S Handle.
00096   * @retval None
00097   */
00098 #define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{                                                 \
00099                                                   __IO uint32_t tmpreg_ovr = 0x00U;                \
00100                                                   tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
00101                                                   tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
00102                                                   UNUSED(tmpreg_ovr);                              \
00103                                                   }while(0U)
00104 /** @brief Clears the I2SExt UDR pending flag.
00105   * @param  __HANDLE__ specifies the I2S Handle.
00106   * @retval None
00107   */
00108 #define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{                                                 \
00109                                                   __IO uint32_t tmpreg_udr = 0x00U;                \
00110                                                   tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
00111                                                   UNUSED(tmpreg_udr);                              \
00112                                                   }while(0U)
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
00123   * @{
00124   */
00125
00126 /* Extended features functions *************************************************/
00127 /* Blocking mode: Polling */
00128 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00129                                             uint16_t Size, uint32_t Timeout);
00130 /* Non-Blocking mode: Interrupt */
00131 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00132                                                uint16_t Size);
00133 /* Non-Blocking mode: DMA */
00134 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
00135                                                 uint16_t Size);
00136 /* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00137 void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
00138 void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00139 void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147 /* Private types -------------------------------------------------------------*/
00148 /* Private variables ---------------------------------------------------------*/
00149 /* Private constants ---------------------------------------------------------*/
00150 /* Private macros ------------------------------------------------------------*/
00151
00152 /**
00153   * @}
00154   */
00155
00156 /* Private functions ---------------------------------------------------------*/
00157
00158 /**
00159   * @}
00160   */
00161
00162 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
00163 /**
00164   * @}
00165   */
00166
00167 #ifdef __cplusplus
00168 }
00169 #endif
00170
00171
00172 #endif /* STM32H7xx_HAL_I2S_EX_H */
00173
00174 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda.c Source File

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stm32h7xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @brief   IRDA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00008   *          (IRDA)
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *           + Peripheral Control functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00023         in setting the associated USART or UART in IRDA mode:
00024         (++) Enable the USARTx/UARTx interface clock.
00025         (++) USARTx/UARTx pins configuration:
00026             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00027             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00028         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00029              and HAL_IRDA_Receive_IT() APIs):
00030             (+++) Configure the USARTx/UARTx interrupt priority.
00031             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00032             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00035
00036         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00037              and HAL_IRDA_Receive_DMA() APIs):
00038             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00039             (+++) Enable the DMAx interface clock.
00040             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00041             (+++) Configure the DMA Tx/Rx channel.
00042             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00043             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00044
00045     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00046         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00047
00048     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00049         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00050              by calling the customized HAL_IRDA_MspInit() API.
00051
00052          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00053              RXNE interrupt and Error Interrupts) will be managed using the macros
00054              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00055
00056     (#) Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00068        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00071        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00080        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00082        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00084        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00085        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00086             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00087        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00088             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00089        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00090             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00091
00092      *** IRDA HAL driver macros list ***
00093      ====================================
00094      [..]
00095        Below the list of most used macros in IRDA HAL driver.
00096
00097        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00098        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00099        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00100        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00101        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00102        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00103        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00104
00105      [..]
00106        (@) You can refer to the IRDA HAL driver header file for more useful macros
00107
00108     ##### Callback registration #####
00109     ==================================
00110
00111     [..]
00112     The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
00113     allows the user to configure dynamically the driver callbacks.
00114
00115     [..]
00116     Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
00117     Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
00118     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00119     (+) TxCpltCallback            : Tx Complete Callback.
00120     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00121     (+) RxCpltCallback            : Rx Complete Callback.
00122     (+) ErrorCallback             : Error Callback.
00123     (+) AbortCpltCallback         : Abort Complete Callback.
00124     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00125     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00126     (+) MspInitCallback           : IRDA MspInit.
00127     (+) MspDeInitCallback         : IRDA MspDeInit.
00128     This function takes as parameters the HAL peripheral handle, the Callback ID
00129     and a pointer to the user callback function.
00130
00131     [..]
00132     Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
00133     weak (surcharged) function.
00134     @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00135     and the Callback ID.
00136     This function allows to reset following callbacks:
00137     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00138     (+) TxCpltCallback            : Tx Complete Callback.
00139     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00140     (+) RxCpltCallback            : Rx Complete Callback.
00141     (+) ErrorCallback             : Error Callback.
00142     (+) AbortCpltCallback         : Abort Complete Callback.
00143     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00144     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00145     (+) MspInitCallback           : IRDA MspInit.
00146     (+) MspDeInitCallback         : IRDA MspDeInit.
00147
00148     [..]
00149     By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
00150     all callbacks are set to the corresponding weak (surcharged) functions:
00151     examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
00152     Exception done for MspInit and MspDeInit functions that are respectively
00153     reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
00154     and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
00155     If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
00156     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00157
00158     [..]
00159     Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
00160     Exception done MspInit/MspDeInit that can be registered/unregistered
00161     in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
00162     MspInit/DeInit callbacks can be used during the Init/DeInit.
00163     In that case first register the MspInit/MspDeInit user callbacks
00164     using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
00165     or @ref HAL_IRDA_Init() function.
00166
00167     [..]
00168     When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
00169     not defined, the callback registration feature is not available
00170     and weak (surcharged) callbacks are used.
00171
00172   @endverbatim
00173   ******************************************************************************
00174   * @attention
00175   *
00176   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00177   * All rights reserved.</center></h2>
00178   *
00179   * This software component is licensed by ST under BSD 3-Clause license,
00180   * the "License"; You may not use this file except in compliance with the
00181   * License. You may obtain a copy of the License at:
00182   *                        opensource.org/licenses/BSD-3-Clause
00183   *
00184   ******************************************************************************
00185   */
00186
00187 /* Includes ------------------------------------------------------------------*/
00188 #include "stm32h7xx_hal.h"
00189
00190 /** @addtogroup STM32H7xx_HAL_Driver
00191   * @{
00192   */
00193
00194 /** @defgroup IRDA IRDA
00195   * @brief HAL IRDA module driver
00196   * @{
00197   */
00198
00199 #ifdef HAL_IRDA_MODULE_ENABLED
00200
00201 /* Private typedef -----------------------------------------------------------*/
00202 /* Private define ------------------------------------------------------------*/
00203 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00204   * @{
00205   */
00206 #define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00207
00208 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00209                                      | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00210
00211 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00212
00213 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00214 /**
00215   * @}
00216   */
00217
00218 /* Private macros ------------------------------------------------------------*/
00219 /** @defgroup IRDA_Private_Macros IRDA Private Macros
00220   * @{
00221   */
00222 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
00223   * @param  __PCLK__ IRDA clock source.
00224   * @param  __BAUD__ Baud rate set by the user.
00225   * @param  __PRESCALER__ IRDA clock prescaler value.
00226   * @retval Division result
00227   */
00228 #define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
00229                                                                   + ((__BAUD__)/2U)) / (__BAUD__))
00230 /**
00231   * @}
00232   */
00233
00234 /* Private variables ---------------------------------------------------------*/
00235 /* Private function prototypes -----------------------------------------------*/
00236 /** @addtogroup IRDA_Private_Functions
00237   * @{
00238   */
00239 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00240 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
00241 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00242 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00243 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00244 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
00245                                                      uint32_t Tickstart, uint32_t Timeout);
00246 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00247 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00248 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00249 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00250 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00251 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00252 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00253 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00254 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00255 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00256 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00257 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00258 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00259 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00260 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00261 /**
00262   * @}
00263   */
00264
00265 /* Exported functions --------------------------------------------------------*/
00266
00267 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00268   * @{
00269   */
00270
00271 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00272   *  @brief    Initialization and Configuration functions
00273   *
00274 @verbatim
00275   ==============================================================================
00276               ##### Initialization and Configuration functions #####
00277   ==============================================================================
00278   [..]
00279   This subsection provides a set of functions allowing to initialize the USARTx
00280   in asynchronous IRDA mode.
00281   (+) For the asynchronous mode only these parameters can be configured:
00282       (++) Baud Rate
00283       (++) Word Length
00284       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00285            in the data register is transmitted but is changed by the parity bit.
00286       (++) Power mode
00287       (++) Prescaler setting
00288       (++) Receiver/transmitter modes
00289
00290   [..]
00291   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00292   (details for the procedures are available in reference manual).
00293
00294 @endverbatim
00295
00296   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00297   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00298   following table.
00299
00300     Table 1. IRDA frame format.
00301     +-----------------------------------------------------------------------+
00302     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00303     |---------|---------|-----------|---------------------------------------|
00304     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00305     |---------|---------|-----------|---------------------------------------|
00306     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00307     |---------|---------|-----------|---------------------------------------|
00308     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00309     |---------|---------|-----------|---------------------------------------|
00310     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00311     |---------|---------|-----------|---------------------------------------|
00312     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00313     |---------|---------|-----------|---------------------------------------|
00314     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00315     +-----------------------------------------------------------------------+
00316
00317   * @{
00318   */
00319
00320 /**
00321   * @brief Initialize the IRDA mode according to the specified
00322   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00323   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00324   *               the configuration information for the specified IRDA module.
00325   * @retval HAL status
00326   */
00327 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00328 {
00329   /* Check the IRDA handle allocation */
00330   if (hirda == NULL)
00331   {
00332     return HAL_ERROR;
00333   }
00334
00335   /* Check the USART/UART associated to the IRDA handle */
00336   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00337
00338   if (hirda->gState == HAL_IRDA_STATE_RESET)
00339   {
00340     /* Allocate lock resource and initialize it */
00341     hirda->Lock = HAL_UNLOCKED;
00342
00343 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00344     IRDA_InitCallbacksToDefault(hirda);
00345
00346     if (hirda->MspInitCallback == NULL)
00347     {
00348       hirda->MspInitCallback = HAL_IRDA_MspInit;
00349     }
00350
00351     /* Init the low level hardware */
00352     hirda->MspInitCallback(hirda);
00353 #else
00354     /* Init the low level hardware : GPIO, CLOCK */
00355     HAL_IRDA_MspInit(hirda);
00356 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00357   }
00358
00359   hirda->gState = HAL_IRDA_STATE_BUSY;
00360
00361   /* Disable the Peripheral to update the configuration registers */
00362   __HAL_IRDA_DISABLE(hirda);
00363
00364   /* Set the IRDA Communication parameters */
00365   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00366   {
00367     return HAL_ERROR;
00368   }
00369
00370   /* In IRDA mode, the following bits must be kept cleared:
00371   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00372   - SCEN and HDSEL bits in the USART_CR3 register.*/
00373   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00374   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00375
00376   /* set the UART/USART in IRDA mode */
00377   hirda->Instance->CR3 |= USART_CR3_IREN;
00378
00379   /* Enable the Peripheral */
00380   __HAL_IRDA_ENABLE(hirda);
00381
00382   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00383   return (IRDA_CheckIdleState(hirda));
00384 }
00385
00386 /**
00387   * @brief DeInitialize the IRDA peripheral.
00388   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00389   *               the configuration information for the specified IRDA module.
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00393 {
00394   /* Check the IRDA handle allocation */
00395   if (hirda == NULL)
00396   {
00397     return HAL_ERROR;
00398   }
00399
00400   /* Check the USART/UART associated to the IRDA handle */
00401   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00402
00403   hirda->gState = HAL_IRDA_STATE_BUSY;
00404
00405   /* DeInit the low level hardware */
00406 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00407   if (hirda->MspDeInitCallback == NULL)
00408   {
00409     hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00410   }
00411   /* DeInit the low level hardware */
00412   hirda->MspDeInitCallback(hirda);
00413 #else
00414   HAL_IRDA_MspDeInit(hirda);
00415 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00416   /* Disable the Peripheral */
00417   __HAL_IRDA_DISABLE(hirda);
00418
00419   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00420   hirda->gState    = HAL_IRDA_STATE_RESET;
00421   hirda->RxState   = HAL_IRDA_STATE_RESET;
00422
00423   /* Process Unlock */
00424   __HAL_UNLOCK(hirda);
00425
00426   return HAL_OK;
00427 }
00428
00429 /**
00430   * @brief Initialize the IRDA MSP.
00431   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00432   *               the configuration information for the specified IRDA module.
00433   * @retval None
00434   */
00435 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00436 {
00437   /* Prevent unused argument(s) compilation warning */
00438   UNUSED(hirda);
00439
00440   /* NOTE: This function should not be modified, when the callback is needed,
00441            the HAL_IRDA_MspInit can be implemented in the user file
00442    */
00443 }
00444
00445 /**
00446   * @brief DeInitialize the IRDA MSP.
00447   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00448   *               the configuration information for the specified IRDA module.
00449   * @retval None
00450   */
00451 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hirda);
00455
00456   /* NOTE: This function should not be modified, when the callback is needed,
00457            the HAL_IRDA_MspDeInit can be implemented in the user file
00458    */
00459 }
00460
00461 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00462 /**
00463   * @brief  Register a User IRDA Callback
00464   *         To be used instead of the weak predefined callback
00465   * @param  hirda irda handle
00466   * @param  CallbackID ID of the callback to be registered
00467   *         This parameter can be one of the following values:
00468   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00469   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00470   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00471   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00472   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00473   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00474   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00475   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00476   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00477   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00478   * @param  pCallback pointer to the Callback function
00479   * @retval HAL status
00480   */
00481 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00482                                             pIRDA_CallbackTypeDef pCallback)
00483 {
00484   HAL_StatusTypeDef status = HAL_OK;
00485
00486   if (pCallback == NULL)
00487   {
00488     /* Update the error code */
00489     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00490
00491     return HAL_ERROR;
00492   }
00493   /* Process locked */
00494   __HAL_LOCK(hirda);
00495
00496   if (hirda->gState == HAL_IRDA_STATE_READY)
00497   {
00498     switch (CallbackID)
00499     {
00500       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00501         hirda->TxHalfCpltCallback = pCallback;
00502         break;
00503
00504       case HAL_IRDA_TX_COMPLETE_CB_ID :
00505         hirda->TxCpltCallback = pCallback;
00506         break;
00507
00508       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00509         hirda->RxHalfCpltCallback = pCallback;
00510         break;
00511
00512       case HAL_IRDA_RX_COMPLETE_CB_ID :
00513         hirda->RxCpltCallback = pCallback;
00514         break;
00515
00516       case HAL_IRDA_ERROR_CB_ID :
00517         hirda->ErrorCallback = pCallback;
00518         break;
00519
00520       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00521         hirda->AbortCpltCallback = pCallback;
00522         break;
00523
00524       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00525         hirda->AbortTransmitCpltCallback = pCallback;
00526         break;
00527
00528       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00529         hirda->AbortReceiveCpltCallback = pCallback;
00530         break;
00531
00532       case HAL_IRDA_MSPINIT_CB_ID :
00533         hirda->MspInitCallback = pCallback;
00534         break;
00535
00536       case HAL_IRDA_MSPDEINIT_CB_ID :
00537         hirda->MspDeInitCallback = pCallback;
00538         break;
00539
00540       default :
00541         /* Update the error code */
00542         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00543
00544         /* Return error status */
00545         status =  HAL_ERROR;
00546         break;
00547     }
00548   }
00549   else if (hirda->gState == HAL_IRDA_STATE_RESET)
00550   {
00551     switch (CallbackID)
00552     {
00553       case HAL_IRDA_MSPINIT_CB_ID :
00554         hirda->MspInitCallback = pCallback;
00555         break;
00556
00557       case HAL_IRDA_MSPDEINIT_CB_ID :
00558         hirda->MspDeInitCallback = pCallback;
00559         break;
00560
00561       default :
00562         /* Update the error code */
00563         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00564
00565         /* Return error status */
00566         status =  HAL_ERROR;
00567         break;
00568     }
00569   }
00570   else
00571   {
00572     /* Update the error code */
00573     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00574
00575     /* Return error status */
00576     status =  HAL_ERROR;
00577   }
00578
00579   /* Release Lock */
00580   __HAL_UNLOCK(hirda);
00581
00582   return status;
00583 }
00584
00585 /**
00586   * @brief  Unregister an IRDA callback
00587   *         IRDA callback is redirected to the weak predefined callback
00588   * @param  hirda irda handle
00589   * @param  CallbackID ID of the callback to be unregistered
00590   *         This parameter can be one of the following values:
00591   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00592   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00593   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00594   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00595   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00596   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00597   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00598   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00599   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00600   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
00604 {
00605   HAL_StatusTypeDef status = HAL_OK;
00606
00607   /* Process locked */
00608   __HAL_LOCK(hirda);
00609
00610   if (HAL_IRDA_STATE_READY == hirda->gState)
00611   {
00612     switch (CallbackID)
00613     {
00614       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00615         hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00616         break;
00617
00618       case HAL_IRDA_TX_COMPLETE_CB_ID :
00619         hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00620         break;
00621
00622       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00623         hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00624         break;
00625
00626       case HAL_IRDA_RX_COMPLETE_CB_ID :
00627         hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00628         break;
00629
00630       case HAL_IRDA_ERROR_CB_ID :
00631         hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00632         break;
00633
00634       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00635         hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00636         break;
00637
00638       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00639         hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00640         break;
00641
00642       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00643         hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00644         break;
00645
00646       case HAL_IRDA_MSPINIT_CB_ID :
00647         hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback           */
00648         break;
00649
00650       case HAL_IRDA_MSPDEINIT_CB_ID :
00651         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00652         break;
00653
00654       default :
00655         /* Update the error code */
00656         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00657
00658         /* Return error status */
00659         status =  HAL_ERROR;
00660         break;
00661     }
00662   }
00663   else if (HAL_IRDA_STATE_RESET == hirda->gState)
00664   {
00665     switch (CallbackID)
00666     {
00667       case HAL_IRDA_MSPINIT_CB_ID :
00668         hirda->MspInitCallback = HAL_IRDA_MspInit;
00669         break;
00670
00671       case HAL_IRDA_MSPDEINIT_CB_ID :
00672         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00673         break;
00674
00675       default :
00676         /* Update the error code */
00677         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00678
00679         /* Return error status */
00680         status =  HAL_ERROR;
00681         break;
00682     }
00683   }
00684   else
00685   {
00686     /* Update the error code */
00687     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00688
00689     /* Return error status */
00690     status =  HAL_ERROR;
00691   }
00692
00693   /* Release Lock */
00694   __HAL_UNLOCK(hirda);
00695
00696   return status;
00697 }
00698 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00699
00700 /**
00701   * @}
00702   */
00703
00704 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00705   *  @brief   IRDA Transmit and Receive functions
00706   *
00707 @verbatim
00708  ===============================================================================
00709                          ##### IO operation functions #####
00710  ===============================================================================
00711   [..]
00712     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00713
00714   [..]
00715     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00716     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00717     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00718     While receiving data, transmission should be avoided as the data to be transmitted
00719     could be corrupted.
00720
00721   [..]
00722     (#) There are two modes of transfer:
00723         (++) Blocking mode: the communication is performed in polling mode.
00724              The HAL status of all data processing is returned by the same function
00725              after finishing transfer.
00726         (++) Non-Blocking mode: the communication is performed using Interrupts
00727              or DMA, these API's return the HAL status.
00728              The end of the data processing will be indicated through the
00729              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00730              using DMA mode.
00731              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00732              will be executed respectively at the end of the Transmit or Receive process
00733              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00734
00735     (#) Blocking mode APIs are :
00736         (++) HAL_IRDA_Transmit()
00737         (++) HAL_IRDA_Receive()
00738
00739     (#) Non Blocking mode APIs with Interrupt are :
00740         (++) HAL_IRDA_Transmit_IT()
00741         (++) HAL_IRDA_Receive_IT()
00742         (++) HAL_IRDA_IRQHandler()
00743
00744     (#) Non Blocking mode functions with DMA are :
00745         (++) HAL_IRDA_Transmit_DMA()
00746         (++) HAL_IRDA_Receive_DMA()
00747         (++) HAL_IRDA_DMAPause()
00748         (++) HAL_IRDA_DMAResume()
00749         (++) HAL_IRDA_DMAStop()
00750
00751     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00752         (++) HAL_IRDA_TxHalfCpltCallback()
00753         (++) HAL_IRDA_TxCpltCallback()
00754         (++) HAL_IRDA_RxHalfCpltCallback()
00755         (++) HAL_IRDA_RxCpltCallback()
00756         (++) HAL_IRDA_ErrorCallback()
00757
00758     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00759         (++) HAL_IRDA_Abort()
00760         (++) HAL_IRDA_AbortTransmit()
00761         (++) HAL_IRDA_AbortReceive()
00762         (++) HAL_IRDA_Abort_IT()
00763         (++) HAL_IRDA_AbortTransmit_IT()
00764         (++) HAL_IRDA_AbortReceive_IT()
00765
00766     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00767         (++) HAL_IRDA_AbortCpltCallback()
00768         (++) HAL_IRDA_AbortTransmitCpltCallback()
00769         (++) HAL_IRDA_AbortReceiveCpltCallback()
00770
00771     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00772         Errors are handled as follows :
00773         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00774              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00775              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00776              and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
00777              If user wants to abort it, Abort services should be called by user.
00778         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00779              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00780              Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00781
00782 @endverbatim
00783   * @{
00784   */
00785
00786 /**
00787   * @brief Send an amount of data in blocking mode.
00788   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00789   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00790   *        of u16 available through pData.
00791   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00792   *               the configuration information for the specified IRDA module.
00793   * @param pData Pointer to data buffer (u8 or u16 data elements).
00794   * @param Size Amount of data elements (u8 or u16) to be sent.
00795   * @param Timeout Specify timeout value.
00796   * @retval HAL status
00797   */
00798 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00799 {
00800   uint8_t  *pdata8bits;
00801   uint16_t *pdata16bits;
00802   uint32_t tickstart;
00803
00804   /* Check that a Tx process is not already ongoing */
00805   if (hirda->gState == HAL_IRDA_STATE_READY)
00806   {
00807     if ((pData == NULL) || (Size == 0U))
00808     {
00809       return  HAL_ERROR;
00810     }
00811
00812     /* Process Locked */
00813     __HAL_LOCK(hirda);
00814
00815     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00816     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00817
00818     /* Init tickstart for timeout managment*/
00819     tickstart = HAL_GetTick();
00820
00821     hirda->TxXferSize = Size;
00822     hirda->TxXferCount = Size;
00823
00824     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
00825     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00826     {
00827       pdata8bits  = NULL;
00828       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00829     }
00830     else
00831     {
00832       pdata8bits  = pData;
00833       pdata16bits = NULL;
00834     }
00835
00836     while (hirda->TxXferCount > 0U)
00837     {
00838       hirda->TxXferCount--;
00839
00840       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00841       {
00842         return HAL_TIMEOUT;
00843       }
00844       if (pdata8bits == NULL)
00845       {
00846         hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
00847         pdata16bits++;
00848       }
00849       else
00850       {
00851         hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
00852         pdata8bits++;
00853       }
00854     }
00855
00856     if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00857     {
00858       return HAL_TIMEOUT;
00859     }
00860
00861     /* At end of Tx process, restore hirda->gState to Ready */
00862     hirda->gState = HAL_IRDA_STATE_READY;
00863
00864     /* Process Unlocked */
00865     __HAL_UNLOCK(hirda);
00866
00867     return HAL_OK;
00868   }
00869   else
00870   {
00871     return HAL_BUSY;
00872   }
00873 }
00874
00875 /**
00876   * @brief Receive an amount of data in blocking mode.
00877   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00878   *        the received data is handled as a set of u16. In this case, Size must reflect the number
00879   *        of u16 available through pData.
00880   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00881   *                the configuration information for the specified IRDA module.
00882   * @param pData Pointer to data buffer (u8 or u16 data elements).
00883   * @param Size Amount of data elements (u8 or u16) to be received.
00884   * @param Timeout Specify timeout value.
00885   * @retval HAL status
00886   */
00887 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00888 {
00889   uint8_t  *pdata8bits;
00890   uint16_t *pdata16bits;
00891   uint16_t uhMask;
00892   uint32_t tickstart;
00893
00894   /* Check that a Rx process is not already ongoing */
00895   if (hirda->RxState == HAL_IRDA_STATE_READY)
00896   {
00897     if ((pData == NULL) || (Size == 0U))
00898     {
00899       return  HAL_ERROR;
00900     }
00901
00902     /* Process Locked */
00903     __HAL_LOCK(hirda);
00904
00905     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00906     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00907
00908     /* Init tickstart for timeout managment*/
00909     tickstart = HAL_GetTick();
00910
00911     hirda->RxXferSize = Size;
00912     hirda->RxXferCount = Size;
00913
00914     /* Computation of the mask to apply to RDR register
00915        of the UART associated to the IRDA */
00916     IRDA_MASK_COMPUTATION(hirda);
00917     uhMask = hirda->Mask;
00918
00919     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00920     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00921     {
00922       pdata8bits  = NULL;
00923       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00924     }
00925     else
00926     {
00927       pdata8bits  = pData;
00928       pdata16bits = NULL;
00929     }
00930
00931     /* Check data remaining to be received */
00932     while (hirda->RxXferCount > 0U)
00933     {
00934       hirda->RxXferCount--;
00935
00936       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00937       {
00938         return HAL_TIMEOUT;
00939       }
00940       if (pdata8bits == NULL)
00941       {
00942         *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
00943         pdata16bits++;
00944       }
00945       else
00946       {
00947         *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00948         pdata8bits++;
00949       }
00950     }
00951
00952     /* At end of Rx process, restore hirda->RxState to Ready */
00953     hirda->RxState = HAL_IRDA_STATE_READY;
00954
00955     /* Process Unlocked */
00956     __HAL_UNLOCK(hirda);
00957
00958     return HAL_OK;
00959   }
00960   else
00961   {
00962     return HAL_BUSY;
00963   }
00964 }
00965
00966 /**
00967   * @brief Send an amount of data in interrupt mode.
00968   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00969   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00970   *        of u16 available through pData.
00971   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00972   *                the configuration information for the specified IRDA module.
00973   * @param pData Pointer to data buffer (u8 or u16 data elements).
00974   * @param Size Amount of data elements (u8 or u16) to be sent.
00975   * @retval HAL status
00976   */
00977 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00978 {
00979   /* Check that a Tx process is not already ongoing */
00980   if (hirda->gState == HAL_IRDA_STATE_READY)
00981   {
00982     if ((pData == NULL) || (Size == 0U))
00983     {
00984       return HAL_ERROR;
00985     }
00986
00987     /* Process Locked */
00988     __HAL_LOCK(hirda);
00989
00990     hirda->pTxBuffPtr = pData;
00991     hirda->TxXferSize = Size;
00992     hirda->TxXferCount = Size;
00993
00994     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00995     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00996
00997     /* Process Unlocked */
00998     __HAL_UNLOCK(hirda);
00999
01000     /* Enable the IRDA Transmit Data Register Empty Interrupt */
01001     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01002
01003     return HAL_OK;
01004   }
01005   else
01006   {
01007     return HAL_BUSY;
01008   }
01009 }
01010
01011 /**
01012   * @brief Receive an amount of data in interrupt mode.
01013   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01014   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01015   *        of u16 available through pData.
01016   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01017   *                the configuration information for the specified IRDA module.
01018   * @param pData Pointer to data buffer (u8 or u16 data elements).
01019   * @param Size Amount of data elements (u8 or u16) to be received.
01020   * @retval HAL status
01021   */
01022 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01023 {
01024   /* Check that a Rx process is not already ongoing */
01025   if (hirda->RxState == HAL_IRDA_STATE_READY)
01026   {
01027     if ((pData == NULL) || (Size == 0U))
01028     {
01029       return HAL_ERROR;
01030     }
01031
01032     /* Process Locked */
01033     __HAL_LOCK(hirda);
01034
01035     hirda->pRxBuffPtr = pData;
01036     hirda->RxXferSize = Size;
01037     hirda->RxXferCount = Size;
01038
01039     /* Computation of the mask to apply to the RDR register
01040        of the UART associated to the IRDA */
01041     IRDA_MASK_COMPUTATION(hirda);
01042
01043     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01044     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01045
01046     /* Process Unlocked */
01047     __HAL_UNLOCK(hirda);
01048
01049     /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
01050     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01051
01052     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01053     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01054
01055     return HAL_OK;
01056   }
01057   else
01058   {
01059     return HAL_BUSY;
01060   }
01061 }
01062
01063 /**
01064   * @brief Send an amount of data in DMA mode.
01065   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01066   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
01067   *        of u16 available through pData.
01068   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01069   *               the configuration information for the specified IRDA module.
01070   * @param pData pointer to data buffer (u8 or u16 data elements).
01071   * @param Size Amount of data elements (u8 or u16) to be sent.
01072   * @retval HAL status
01073   */
01074 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01075 {
01076   /* Check that a Tx process is not already ongoing */
01077   if (hirda->gState == HAL_IRDA_STATE_READY)
01078   {
01079     if ((pData == NULL) || (Size == 0U))
01080     {
01081       return HAL_ERROR;
01082     }
01083
01084     /* Process Locked */
01085     __HAL_LOCK(hirda);
01086
01087     hirda->pTxBuffPtr = pData;
01088     hirda->TxXferSize = Size;
01089     hirda->TxXferCount = Size;
01090
01091     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01092     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
01093
01094     /* Set the IRDA DMA transfer complete callback */
01095     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
01096
01097     /* Set the IRDA DMA half transfer complete callback */
01098     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
01099
01100     /* Set the DMA error callback */
01101     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
01102
01103     /* Set the DMA abort callback */
01104     hirda->hdmatx->XferAbortCallback = NULL;
01105
01106     /* Enable the IRDA transmit DMA channel */
01107     if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
01108     {
01109       /* Clear the TC flag in the ICR register */
01110       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
01111
01112       /* Process Unlocked */
01113       __HAL_UNLOCK(hirda);
01114
01115       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01116          in the USART CR3 register */
01117       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01118
01119       return HAL_OK;
01120     }
01121     else
01122     {
01123       /* Set error code to DMA */
01124       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01125
01126       /* Process Unlocked */
01127       __HAL_UNLOCK(hirda);
01128
01129       /* Restore hirda->gState to ready */
01130       hirda->gState = HAL_IRDA_STATE_READY;
01131
01132       return HAL_ERROR;
01133     }
01134   }
01135   else
01136   {
01137     return HAL_BUSY;
01138   }
01139 }
01140
01141 /**
01142   * @brief Receive an amount of data in DMA mode.
01143   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01144   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01145   *        of u16 available through pData.
01146   * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
01147   *         the parity bit (MSB position).
01148   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01149   *               the configuration information for the specified IRDA module.
01150   * @param pData Pointer to data buffer (u8 or u16 data elements).
01151   * @param Size Amount of data elements (u8 or u16) to be received.
01152   * @retval HAL status
01153   */
01154 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01155 {
01156   /* Check that a Rx process is not already ongoing */
01157   if (hirda->RxState == HAL_IRDA_STATE_READY)
01158   {
01159     if ((pData == NULL) || (Size == 0U))
01160     {
01161       return HAL_ERROR;
01162     }
01163
01164     /* Process Locked */
01165     __HAL_LOCK(hirda);
01166
01167     hirda->pRxBuffPtr = pData;
01168     hirda->RxXferSize = Size;
01169
01170     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01171     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01172
01173     /* Set the IRDA DMA transfer complete callback */
01174     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
01175
01176     /* Set the IRDA DMA half transfer complete callback */
01177     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
01178
01179     /* Set the DMA error callback */
01180     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
01181
01182     /* Set the DMA abort callback */
01183     hirda->hdmarx->XferAbortCallback = NULL;
01184
01185     /* Enable the DMA channel */
01186     if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
01187     {
01188       /* Process Unlocked */
01189       __HAL_UNLOCK(hirda);
01190
01191       /* Enable the UART Parity Error Interrupt */
01192       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01193
01194       /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01195       SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01196
01197       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01198          in the USART CR3 register */
01199       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01200
01201       return HAL_OK;
01202     }
01203     else
01204     {
01205       /* Set error code to DMA */
01206       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01207
01208       /* Process Unlocked */
01209       __HAL_UNLOCK(hirda);
01210
01211       /* Restore hirda->RxState to ready */
01212       hirda->RxState = HAL_IRDA_STATE_READY;
01213
01214       return HAL_ERROR;
01215     }
01216   }
01217   else
01218   {
01219     return HAL_BUSY;
01220   }
01221 }
01222
01223
01224 /**
01225   * @brief Pause the DMA Transfer.
01226   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01227   *                the configuration information for the specified IRDA module.
01228   * @retval HAL status
01229   */
01230 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
01231 {
01232   /* Process Locked */
01233   __HAL_LOCK(hirda);
01234
01235   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01236   {
01237     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01238     {
01239       /* Disable the IRDA DMA Tx request */
01240       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01241     }
01242   }
01243   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01244   {
01245     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01246     {
01247       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01248       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01249       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01250
01251       /* Disable the IRDA DMA Rx request */
01252       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01253     }
01254   }
01255
01256   /* Process Unlocked */
01257   __HAL_UNLOCK(hirda);
01258
01259   return HAL_OK;
01260 }
01261
01262 /**
01263   * @brief Resume the DMA Transfer.
01264   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01265   *                the configuration information for the specified UART module.
01266   * @retval HAL status
01267   */
01268 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
01269 {
01270   /* Process Locked */
01271   __HAL_LOCK(hirda);
01272
01273   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01274   {
01275     /* Enable the IRDA DMA Tx request */
01276     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01277   }
01278   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01279   {
01280     /* Clear the Overrun flag before resuming the Rx transfer*/
01281     __HAL_IRDA_CLEAR_OREFLAG(hirda);
01282
01283     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01284     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01285     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01286
01287     /* Enable the IRDA DMA Rx request */
01288     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01289   }
01290
01291   /* Process Unlocked */
01292   __HAL_UNLOCK(hirda);
01293
01294   return HAL_OK;
01295 }
01296
01297 /**
01298   * @brief Stop the DMA Transfer.
01299   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01300   *                the configuration information for the specified UART module.
01301   * @retval HAL status
01302   */
01303 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
01304 {
01305   /* The Lock is not implemented on this API to allow the user application
01306      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
01307      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
01308      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01309      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01310      the stream and the corresponding call back is executed. */
01311
01312   /* Stop IRDA DMA Tx request if ongoing */
01313   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01314   {
01315     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01316     {
01317       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01318
01319       /* Abort the IRDA DMA Tx channel */
01320       if (hirda->hdmatx != NULL)
01321       {
01322         if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01323         {
01324           if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01325           {
01326             /* Set error code to DMA */
01327             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01328
01329             return HAL_TIMEOUT;
01330           }
01331         }
01332       }
01333
01334       IRDA_EndTxTransfer(hirda);
01335     }
01336   }
01337
01338   /* Stop IRDA DMA Rx request if ongoing */
01339   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01340   {
01341     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01342     {
01343       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01344
01345       /* Abort the IRDA DMA Rx channel */
01346       if (hirda->hdmarx != NULL)
01347       {
01348         if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01349         {
01350           if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01351           {
01352             /* Set error code to DMA */
01353             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01354
01355             return HAL_TIMEOUT;
01356           }
01357         }
01358       }
01359
01360       IRDA_EndRxTransfer(hirda);
01361     }
01362   }
01363
01364   return HAL_OK;
01365 }
01366
01367 /**
01368   * @brief  Abort ongoing transfers (blocking mode).
01369   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01370   *               the configuration information for the specified UART module.
01371   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01372   *         This procedure performs following operations :
01373   *           - Disable IRDA Interrupts (Tx and Rx)
01374   *           - Disable the DMA transfer in the peripheral register (if enabled)
01375   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01376   *           - Set handle State to READY
01377   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
01381 {
01382   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01383   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01384   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01385
01386   /* Disable the IRDA DMA Tx request if enabled */
01387   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01388   {
01389     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01390
01391     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01392     if (hirda->hdmatx != NULL)
01393     {
01394       /* Set the IRDA DMA Abort callback to Null.
01395          No call back execution at end of DMA abort procedure */
01396       hirda->hdmatx->XferAbortCallback = NULL;
01397
01398       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01399       {
01400         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01401         {
01402           /* Set error code to DMA */
01403           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01404
01405           return HAL_TIMEOUT;
01406         }
01407       }
01408     }
01409   }
01410
01411   /* Disable the IRDA DMA Rx request if enabled */
01412   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01413   {
01414     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01415
01416     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01417     if (hirda->hdmarx != NULL)
01418     {
01419       /* Set the IRDA DMA Abort callback to Null.
01420          No call back execution at end of DMA abort procedure */
01421       hirda->hdmarx->XferAbortCallback = NULL;
01422
01423       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01424       {
01425         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01426         {
01427           /* Set error code to DMA */
01428           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01429
01430           return HAL_TIMEOUT;
01431         }
01432       }
01433     }
01434   }
01435
01436   /* Reset Tx and Rx transfer counters */
01437   hirda->TxXferCount = 0U;
01438   hirda->RxXferCount = 0U;
01439
01440   /* Clear the Error flags in the ICR register */
01441   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01442
01443   /* Restore hirda->gState and hirda->RxState to Ready */
01444   hirda->gState  = HAL_IRDA_STATE_READY;
01445   hirda->RxState = HAL_IRDA_STATE_READY;
01446
01447   /* Reset Handle ErrorCode to No Error */
01448   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01449
01450   return HAL_OK;
01451 }
01452
01453 /**
01454   * @brief  Abort ongoing Transmit transfer (blocking mode).
01455   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01456   *               the configuration information for the specified UART module.
01457   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01458   *         This procedure performs following operations :
01459   *           - Disable IRDA Interrupts (Tx)
01460   *           - Disable the DMA transfer in the peripheral register (if enabled)
01461   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01462   *           - Set handle State to READY
01463   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01464   * @retval HAL status
01465   */
01466 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01467 {
01468   /* Disable TXEIE and TCIE interrupts */
01469   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01470
01471   /* Disable the IRDA DMA Tx request if enabled */
01472   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01473   {
01474     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01475
01476     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01477     if (hirda->hdmatx != NULL)
01478     {
01479       /* Set the IRDA DMA Abort callback to Null.
01480          No call back execution at end of DMA abort procedure */
01481       hirda->hdmatx->XferAbortCallback = NULL;
01482
01483       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01484       {
01485         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01486         {
01487           /* Set error code to DMA */
01488           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01489
01490           return HAL_TIMEOUT;
01491         }
01492       }
01493     }
01494   }
01495
01496   /* Reset Tx transfer counter */
01497   hirda->TxXferCount = 0U;
01498
01499   /* Restore hirda->gState to Ready */
01500   hirda->gState = HAL_IRDA_STATE_READY;
01501
01502   return HAL_OK;
01503 }
01504
01505 /**
01506   * @brief  Abort ongoing Receive transfer (blocking mode).
01507   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01508   *               the configuration information for the specified UART module.
01509   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01510   *         This procedure performs following operations :
01511   *           - Disable IRDA Interrupts (Rx)
01512   *           - Disable the DMA transfer in the peripheral register (if enabled)
01513   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01514   *           - Set handle State to READY
01515   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01516   * @retval HAL status
01517   */
01518 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01519 {
01520   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01521   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01522   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01523
01524   /* Disable the IRDA DMA Rx request if enabled */
01525   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01526   {
01527     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01528
01529     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01530     if (hirda->hdmarx != NULL)
01531     {
01532       /* Set the IRDA DMA Abort callback to Null.
01533          No call back execution at end of DMA abort procedure */
01534       hirda->hdmarx->XferAbortCallback = NULL;
01535
01536       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01537       {
01538         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01539         {
01540           /* Set error code to DMA */
01541           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01542
01543           return HAL_TIMEOUT;
01544         }
01545       }
01546     }
01547   }
01548
01549   /* Reset Rx transfer counter */
01550   hirda->RxXferCount = 0U;
01551
01552   /* Clear the Error flags in the ICR register */
01553   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01554
01555   /* Restore hirda->RxState to Ready */
01556   hirda->RxState = HAL_IRDA_STATE_READY;
01557
01558   return HAL_OK;
01559 }
01560
01561 /**
01562   * @brief  Abort ongoing transfers (Interrupt mode).
01563   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01564   *               the configuration information for the specified UART module.
01565   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01566   *         This procedure performs following operations :
01567   *           - Disable IRDA Interrupts (Tx and Rx)
01568   *           - Disable the DMA transfer in the peripheral register (if enabled)
01569   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01570   *           - Set handle State to READY
01571   *           - At abort completion, call user abort complete callback
01572   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01573   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01574   * @retval HAL status
01575   */
01576 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01577 {
01578   uint32_t abortcplt = 1U;
01579
01580   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01581   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01582   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01583
01584   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01585      before any call to DMA Abort functions */
01586   /* DMA Tx Handle is valid */
01587   if (hirda->hdmatx != NULL)
01588   {
01589     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01590        Otherwise, set it to NULL */
01591     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01592     {
01593       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01594     }
01595     else
01596     {
01597       hirda->hdmatx->XferAbortCallback = NULL;
01598     }
01599   }
01600   /* DMA Rx Handle is valid */
01601   if (hirda->hdmarx != NULL)
01602   {
01603     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01604        Otherwise, set it to NULL */
01605     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01606     {
01607       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01608     }
01609     else
01610     {
01611       hirda->hdmarx->XferAbortCallback = NULL;
01612     }
01613   }
01614
01615   /* Disable the IRDA DMA Tx request if enabled */
01616   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01617   {
01618     /* Disable DMA Tx at UART level */
01619     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01620
01621     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01622     if (hirda->hdmatx != NULL)
01623     {
01624       /* IRDA Tx DMA Abort callback has already been initialised :
01625          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01626
01627       /* Abort DMA TX */
01628       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01629       {
01630         hirda->hdmatx->XferAbortCallback = NULL;
01631       }
01632       else
01633       {
01634         abortcplt = 0U;
01635       }
01636     }
01637   }
01638
01639   /* Disable the IRDA DMA Rx request if enabled */
01640   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01641   {
01642     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01643
01644     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01645     if (hirda->hdmarx != NULL)
01646     {
01647       /* IRDA Rx DMA Abort callback has already been initialised :
01648          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01649
01650       /* Abort DMA RX */
01651       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01652       {
01653         hirda->hdmarx->XferAbortCallback = NULL;
01654         abortcplt = 1U;
01655       }
01656       else
01657       {
01658         abortcplt = 0U;
01659       }
01660     }
01661   }
01662
01663   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01664   if (abortcplt == 1U)
01665   {
01666     /* Reset Tx and Rx transfer counters */
01667     hirda->TxXferCount = 0U;
01668     hirda->RxXferCount = 0U;
01669
01670     /* Reset errorCode */
01671     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01672
01673     /* Clear the Error flags in the ICR register */
01674     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01675
01676     /* Restore hirda->gState and hirda->RxState to Ready */
01677     hirda->gState  = HAL_IRDA_STATE_READY;
01678     hirda->RxState = HAL_IRDA_STATE_READY;
01679
01680     /* As no DMA to be aborted, call directly user Abort complete callback */
01681 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01682     /* Call registered Abort complete callback */
01683     hirda->AbortCpltCallback(hirda);
01684 #else
01685     /* Call legacy weak Abort complete callback */
01686     HAL_IRDA_AbortCpltCallback(hirda);
01687 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01688   }
01689
01690   return HAL_OK;
01691 }
01692
01693 /**
01694   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01695   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01696   *               the configuration information for the specified UART module.
01697   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01698   *         This procedure performs following operations :
01699   *           - Disable IRDA Interrupts (Tx)
01700   *           - Disable the DMA transfer in the peripheral register (if enabled)
01701   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01702   *           - Set handle State to READY
01703   *           - At abort completion, call user abort complete callback
01704   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01705   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01706   * @retval HAL status
01707   */
01708 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01709 {
01710   /* Disable TXEIE and TCIE interrupts */
01711   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01712
01713   /* Disable the IRDA DMA Tx request if enabled */
01714   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01715   {
01716     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01717
01718     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01719     if (hirda->hdmatx != NULL)
01720     {
01721       /* Set the IRDA DMA Abort callback :
01722          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01723       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01724
01725       /* Abort DMA TX */
01726       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01727       {
01728         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01729         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01730       }
01731     }
01732     else
01733     {
01734       /* Reset Tx transfer counter */
01735       hirda->TxXferCount = 0U;
01736
01737       /* Restore hirda->gState to Ready */
01738       hirda->gState = HAL_IRDA_STATE_READY;
01739
01740       /* As no DMA to be aborted, call directly user Abort complete callback */
01741 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01742       /* Call registered Abort Transmit Complete Callback */
01743       hirda->AbortTransmitCpltCallback(hirda);
01744 #else
01745       /* Call legacy weak Abort Transmit Complete Callback */
01746       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01747 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01748     }
01749   }
01750   else
01751   {
01752     /* Reset Tx transfer counter */
01753     hirda->TxXferCount = 0U;
01754
01755     /* Restore hirda->gState to Ready */
01756     hirda->gState = HAL_IRDA_STATE_READY;
01757
01758     /* As no DMA to be aborted, call directly user Abort complete callback */
01759 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01760     /* Call registered Abort Transmit Complete Callback */
01761     hirda->AbortTransmitCpltCallback(hirda);
01762 #else
01763     /* Call legacy weak Abort Transmit Complete Callback */
01764     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01765 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01766   }
01767
01768   return HAL_OK;
01769 }
01770
01771 /**
01772   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01773   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01774   *               the configuration information for the specified UART module.
01775   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01776   *         This procedure performs following operations :
01777   *           - Disable IRDA Interrupts (Rx)
01778   *           - Disable the DMA transfer in the peripheral register (if enabled)
01779   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01780   *           - Set handle State to READY
01781   *           - At abort completion, call user abort complete callback
01782   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01783   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01784   * @retval HAL status
01785   */
01786 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01787 {
01788   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01789   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01790   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01791
01792   /* Disable the IRDA DMA Rx request if enabled */
01793   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01794   {
01795     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01796
01797     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01798     if (hirda->hdmarx != NULL)
01799     {
01800       /* Set the IRDA DMA Abort callback :
01801          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01802       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01803
01804       /* Abort DMA RX */
01805       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01806       {
01807         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01808         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01809       }
01810     }
01811     else
01812     {
01813       /* Reset Rx transfer counter */
01814       hirda->RxXferCount = 0U;
01815
01816       /* Clear the Error flags in the ICR register */
01817       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01818
01819       /* Restore hirda->RxState to Ready */
01820       hirda->RxState = HAL_IRDA_STATE_READY;
01821
01822       /* As no DMA to be aborted, call directly user Abort complete callback */
01823 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01824       /* Call registered Abort Receive Complete Callback */
01825       hirda->AbortReceiveCpltCallback(hirda);
01826 #else
01827       /* Call legacy weak Abort Receive Complete Callback */
01828       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01829 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01830     }
01831   }
01832   else
01833   {
01834     /* Reset Rx transfer counter */
01835     hirda->RxXferCount = 0U;
01836
01837     /* Clear the Error flags in the ICR register */
01838     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01839
01840     /* Restore hirda->RxState to Ready */
01841     hirda->RxState = HAL_IRDA_STATE_READY;
01842
01843     /* As no DMA to be aborted, call directly user Abort complete callback */
01844 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01845     /* Call registered Abort Receive Complete Callback */
01846     hirda->AbortReceiveCpltCallback(hirda);
01847 #else
01848     /* Call legacy weak Abort Receive Complete Callback */
01849     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01850 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01851   }
01852
01853   return HAL_OK;
01854 }
01855
01856 /**
01857   * @brief Handle IRDA interrupt request.
01858   * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
01859   *               the configuration information for the specified IRDA module.
01860   * @retval None
01861   */
01862 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01863 {
01864   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01865   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01866   uint32_t cr3its;
01867   uint32_t errorflags;
01868   uint32_t errorcode;
01869
01870   /* If no error occurs */
01871   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01872   if (errorflags == 0U)
01873   {
01874     /* IRDA in mode Receiver ---------------------------------------------------*/
01875     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01876     {
01877       IRDA_Receive_IT(hirda);
01878       return;
01879     }
01880   }
01881
01882   /* If some errors occur */
01883   cr3its = READ_REG(hirda->Instance->CR3);
01884   if ((errorflags != 0U)
01885       && (((cr3its & USART_CR3_EIE) != 0U)
01886           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
01887   {
01888     /* IRDA parity error interrupt occurred -------------------------------------*/
01889     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01890     {
01891       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
01892
01893       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01894     }
01895
01896     /* IRDA frame error interrupt occurred --------------------------------------*/
01897     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01898     {
01899       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
01900
01901       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01902     }
01903
01904     /* IRDA noise error interrupt occurred --------------------------------------*/
01905     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01906     {
01907       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
01908
01909       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01910     }
01911
01912     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
01913     if (((isrflags & USART_ISR_ORE) != 0U) &&
01914         (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
01915     {
01916       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
01917
01918       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01919     }
01920
01921     /* Call IRDA Error Call back function if need be --------------------------*/
01922     if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01923     {
01924       /* IRDA in mode Receiver ---------------------------------------------------*/
01925       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01926       {
01927         IRDA_Receive_IT(hirda);
01928       }
01929
01930       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01931          consider error as blocking */
01932       errorcode = hirda->ErrorCode;
01933       if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
01934           ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
01935       {
01936         /* Blocking error : transfer is aborted
01937            Set the IRDA state ready to be able to start again the process,
01938            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01939         IRDA_EndRxTransfer(hirda);
01940
01941         /* Disable the IRDA DMA Rx request if enabled */
01942         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01943         {
01944           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01945
01946           /* Abort the IRDA DMA Rx channel */
01947           if (hirda->hdmarx != NULL)
01948           {
01949             /* Set the IRDA DMA Abort callback :
01950                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01951             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01952
01953             /* Abort DMA RX */
01954             if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01955             {
01956               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01957               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01958             }
01959           }
01960           else
01961           {
01962 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01963             /* Call registered user error callback */
01964             hirda->ErrorCallback(hirda);
01965 #else
01966             /* Call legacy weak user error callback */
01967             HAL_IRDA_ErrorCallback(hirda);
01968 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01969           }
01970         }
01971         else
01972         {
01973 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01974           /* Call registered user error callback */
01975           hirda->ErrorCallback(hirda);
01976 #else
01977           /* Call legacy weak user error callback */
01978           HAL_IRDA_ErrorCallback(hirda);
01979 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01980         }
01981       }
01982       else
01983       {
01984         /* Non Blocking error : transfer could go on.
01985            Error is notified to user through user error callback */
01986 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01987         /* Call registered user error callback */
01988         hirda->ErrorCallback(hirda);
01989 #else
01990         /* Call legacy weak user error callback */
01991         HAL_IRDA_ErrorCallback(hirda);
01992 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01993         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01994       }
01995     }
01996     return;
01997
01998   } /* End if some error occurs */
01999
02000   /* IRDA in mode Transmitter ------------------------------------------------*/
02001   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
02002   {
02003     IRDA_Transmit_IT(hirda);
02004     return;
02005   }
02006
02007   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
02008   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02009   {
02010     IRDA_EndTransmit_IT(hirda);
02011     return;
02012   }
02013
02014 }
02015
02016 /**
02017   * @brief  Tx Transfer completed callback.
02018   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02019   *               the configuration information for the specified IRDA module.
02020   * @retval None
02021   */
02022 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
02023 {
02024   /* Prevent unused argument(s) compilation warning */
02025   UNUSED(hirda);
02026
02027   /* NOTE : This function should not be modified, when the callback is needed,
02028             the HAL_IRDA_TxCpltCallback can be implemented in the user file.
02029    */
02030 }
02031
02032 /**
02033   * @brief  Tx Half Transfer completed callback.
02034   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02035   *               the configuration information for the specified USART module.
02036   * @retval None
02037   */
02038 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02039 {
02040   /* Prevent unused argument(s) compilation warning */
02041   UNUSED(hirda);
02042
02043   /* NOTE : This function should not be modified, when the callback is needed,
02044             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
02045    */
02046 }
02047
02048 /**
02049   * @brief  Rx Transfer completed callback.
02050   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02051   *               the configuration information for the specified IRDA module.
02052   * @retval None
02053   */
02054 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
02055 {
02056   /* Prevent unused argument(s) compilation warning */
02057   UNUSED(hirda);
02058
02059   /* NOTE : This function should not be modified, when the callback is needed,
02060             the HAL_IRDA_RxCpltCallback can be implemented in the user file.
02061    */
02062 }
02063
02064 /**
02065   * @brief  Rx Half Transfer complete callback.
02066   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02067   *               the configuration information for the specified IRDA module.
02068   * @retval None
02069   */
02070 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02071 {
02072   /* Prevent unused argument(s) compilation warning */
02073   UNUSED(hirda);
02074
02075   /* NOTE : This function should not be modified, when the callback is needed,
02076             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
02077    */
02078 }
02079
02080 /**
02081   * @brief  IRDA error callback.
02082   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02083   *               the configuration information for the specified IRDA module.
02084   * @retval None
02085   */
02086 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
02087 {
02088   /* Prevent unused argument(s) compilation warning */
02089   UNUSED(hirda);
02090
02091   /* NOTE : This function should not be modified, when the callback is needed,
02092             the HAL_IRDA_ErrorCallback can be implemented in the user file.
02093    */
02094 }
02095
02096 /**
02097   * @brief  IRDA Abort Complete callback.
02098   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02099   *               the configuration information for the specified IRDA module.
02100   * @retval None
02101   */
02102 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
02103 {
02104   /* Prevent unused argument(s) compilation warning */
02105   UNUSED(hirda);
02106
02107   /* NOTE : This function should not be modified, when the callback is needed,
02108             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
02109    */
02110 }
02111
02112 /**
02113   * @brief  IRDA Abort Complete callback.
02114   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02115   *               the configuration information for the specified IRDA module.
02116   * @retval None
02117   */
02118 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
02119 {
02120   /* Prevent unused argument(s) compilation warning */
02121   UNUSED(hirda);
02122
02123   /* NOTE : This function should not be modified, when the callback is needed,
02124             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
02125    */
02126 }
02127
02128 /**
02129   * @brief  IRDA Abort Receive Complete callback.
02130   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02131   *               the configuration information for the specified IRDA module.
02132   * @retval None
02133   */
02134 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
02135 {
02136   /* Prevent unused argument(s) compilation warning */
02137   UNUSED(hirda);
02138
02139   /* NOTE : This function should not be modified, when the callback is needed,
02140             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
02141    */
02142 }
02143
02144 /**
02145   * @}
02146   */
02147
02148 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
02149   *  @brief   IRDA State and Errors functions
02150   *
02151 @verbatim
02152   ==============================================================================
02153             ##### Peripheral State and Error functions #####
02154   ==============================================================================
02155   [..]
02156     This subsection provides a set of functions allowing to return the State of IrDA
02157     communication process and also return Peripheral Errors occurred during communication process
02158      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
02159          of the IRDA peripheral handle.
02160      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
02161          communication.
02162
02163 @endverbatim
02164   * @{
02165   */
02166
02167 /**
02168   * @brief Return the IRDA handle state.
02169   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02170   *                the configuration information for the specified IRDA module.
02171   * @retval HAL state
02172   */
02173 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
02174 {
02175   /* Return IRDA handle state */
02176   uint32_t temp1;
02177   uint32_t temp2;
02178   temp1 = (uint32_t)hirda->gState;
02179   temp2 = (uint32_t)hirda->RxState;
02180
02181   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
02182 }
02183
02184 /**
02185   * @brief Return the IRDA handle error code.
02186   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02187   *               the configuration information for the specified IRDA module.
02188   * @retval IRDA Error Code
02189   */
02190 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
02191 {
02192   return hirda->ErrorCode;
02193 }
02194
02195 /**
02196   * @}
02197   */
02198
02199 /**
02200   * @}
02201   */
02202
02203 /** @defgroup IRDA_Private_Functions IRDA Private Functions
02204   * @{
02205   */
02206
02207 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02208 /**
02209   * @brief  Initialize the callbacks to their default values.
02210   * @param  hirda IRDA handle.
02211   * @retval none
02212   */
02213 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
02214 {
02215   /* Init the IRDA Callback settings */
02216   hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02217   hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02218   hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02219   hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02220   hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
02221   hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02222   hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02223   hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02224
02225 }
02226 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02227
02228 /**
02229   * @brief Configure the IRDA peripheral.
02230   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02231   *               the configuration information for the specified IRDA module.
02232   * @retval HAL status
02233   */
02234 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
02235 {
02236   uint32_t tmpreg;
02237   IRDA_ClockSourceTypeDef clocksource;
02238   HAL_StatusTypeDef ret = HAL_OK;
02239   const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02240   PLL2_ClocksTypeDef pll2_clocks;
02241   PLL3_ClocksTypeDef pll3_clocks;
02242   uint32_t pclk;
02243
02244   /* Check the communication parameters */
02245   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
02246   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
02247   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
02248   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
02249   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
02250   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
02251   assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
02252
02253   /*-------------------------- USART CR1 Configuration -----------------------*/
02254   /* Configure the IRDA Word Length, Parity and transfer Mode:
02255      Set the M bits according to hirda->Init.WordLength value
02256      Set PCE and PS bits according to hirda->Init.Parity value
02257      Set TE and RE bits according to hirda->Init.Mode value */
02258   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
02259
02260   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
02261
02262   /*-------------------------- USART CR3 Configuration -----------------------*/
02263   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
02264
02265   /*--------------------- USART clock PRESC Configuration ----------------*/
02266   /* Configure
02267   * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
02268   MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
02269
02270   /*-------------------------- USART GTPR Configuration ----------------------*/
02271   MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
02272
02273   /*-------------------------- USART BRR Configuration -----------------------*/
02274   IRDA_GETCLOCKSOURCE(hirda, clocksource);
02275   tmpreg =   0U;
02276   switch (clocksource)
02277   {
02278     case IRDA_CLOCKSOURCE_D2PCLK1:
02279       pclk = HAL_RCC_GetPCLK1Freq();
02280       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02281       break;
02282     case IRDA_CLOCKSOURCE_D2PCLK2:
02283       pclk = HAL_RCC_GetPCLK2Freq();
02284       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02285       break;
02286     case IRDA_CLOCKSOURCE_PLL2Q:
02287       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02288       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02289       break;
02290     case IRDA_CLOCKSOURCE_PLL3Q:
02291       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02292       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02293       break;
02294     case IRDA_CLOCKSOURCE_CSI:
02295       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02296       break;
02297     case IRDA_CLOCKSOURCE_HSI:
02298       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02299       break;
02300     case IRDA_CLOCKSOURCE_LSE:
02301       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02302       break;
02303     default:
02304       ret = HAL_ERROR;
02305       break;
02306   }
02307
02308   /* USARTDIV must be greater than or equal to 0d16 */
02309   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02310   {
02311     hirda->Instance->BRR = tmpreg;
02312   }
02313   else
02314   {
02315     ret = HAL_ERROR;
02316   }
02317
02318   return ret;
02319 }
02320
02321 /**
02322   * @brief Check the IRDA Idle State.
02323   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02324   *               the configuration information for the specified IRDA module.
02325   * @retval HAL status
02326   */
02327 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
02328 {
02329   uint32_t tickstart;
02330
02331   /* Initialize the IRDA ErrorCode */
02332   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02333
02334   /* Init tickstart for timeout managment*/
02335   tickstart = HAL_GetTick();
02336
02337   /* Check if the Transmitter is enabled */
02338   if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02339   {
02340     /* Wait until TEACK flag is set */
02341     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02342     {
02343       /* Timeout occurred */
02344       return HAL_TIMEOUT;
02345     }
02346   }
02347   /* Check if the Receiver is enabled */
02348   if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02349   {
02350     /* Wait until REACK flag is set */
02351     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02352     {
02353       /* Timeout occurred */
02354       return HAL_TIMEOUT;
02355     }
02356   }
02357
02358   /* Initialize the IRDA state*/
02359   hirda->gState  = HAL_IRDA_STATE_READY;
02360   hirda->RxState = HAL_IRDA_STATE_READY;
02361
02362   /* Process Unlocked */
02363   __HAL_UNLOCK(hirda);
02364
02365   return HAL_OK;
02366 }
02367
02368 /**
02369   * @brief  Handle IRDA Communication Timeout.
02370   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02371   *               the configuration information for the specified IRDA module.
02372   * @param  Flag Specifies the IRDA flag to check.
02373   * @param  Status Flag status (SET or RESET)
02374   * @param  Tickstart Tick start value
02375   * @param  Timeout Timeout duration
02376   * @retval HAL status
02377   */
02378 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
02379                                                      uint32_t Tickstart, uint32_t Timeout)
02380 {
02381   /* Wait until flag is set */
02382   while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
02383   {
02384     /* Check for the Timeout */
02385     if (Timeout != HAL_MAX_DELAY)
02386     {
02387       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02388       {
02389         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02390         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02391         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02392
02393         hirda->gState  = HAL_IRDA_STATE_READY;
02394         hirda->RxState = HAL_IRDA_STATE_READY;
02395
02396         /* Process Unlocked */
02397         __HAL_UNLOCK(hirda);
02398         return HAL_TIMEOUT;
02399       }
02400     }
02401   }
02402   return HAL_OK;
02403 }
02404
02405
02406 /**
02407   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
02408   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02409   *               the configuration information for the specified IRDA module.
02410   * @retval None
02411   */
02412 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
02413 {
02414   /* Disable TXEIE and TCIE interrupts */
02415   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02416
02417   /* At end of Tx process, restore hirda->gState to Ready */
02418   hirda->gState = HAL_IRDA_STATE_READY;
02419 }
02420
02421
02422 /**
02423   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02424   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02425   *               the configuration information for the specified IRDA module.
02426   * @retval None
02427   */
02428 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
02429 {
02430   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02431   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02432   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02433
02434   /* At end of Rx process, restore hirda->RxState to Ready */
02435   hirda->RxState = HAL_IRDA_STATE_READY;
02436 }
02437
02438
02439 /**
02440   * @brief  DMA IRDA transmit process complete callback.
02441   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02442   *              the configuration information for the specified DMA module.
02443   * @retval None
02444   */
02445 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02446 {
02447   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02448
02449   /* DMA Normal mode */
02450   if (hdma->Init.Mode != DMA_CIRCULAR)
02451   {
02452     hirda->TxXferCount = 0U;
02453
02454     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02455        in the IRDA CR3 register */
02456     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
02457
02458     /* Enable the IRDA Transmit Complete Interrupt */
02459     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02460   }
02461   /* DMA Circular mode */
02462   else
02463   {
02464 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02465     /* Call registered Tx complete callback */
02466     hirda->TxCpltCallback(hirda);
02467 #else
02468     /* Call legacy weak Tx complete callback */
02469     HAL_IRDA_TxCpltCallback(hirda);
02470 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02471   }
02472
02473 }
02474
02475 /**
02476   * @brief  DMA IRDA transmit process half complete callback.
02477   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02478   *              the configuration information for the specified DMA module.
02479   * @retval None
02480   */
02481 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
02482 {
02483   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02484
02485 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02486   /* Call registered Tx Half complete callback */
02487   hirda->TxHalfCpltCallback(hirda);
02488 #else
02489   /* Call legacy weak Tx complete callback */
02490   HAL_IRDA_TxHalfCpltCallback(hirda);
02491 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02492 }
02493
02494 /**
02495   * @brief  DMA IRDA receive process complete callback.
02496   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02497   *               the configuration information for the specified DMA module.
02498   * @retval None
02499   */
02500 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02501 {
02502   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02503
02504   /* DMA Normal mode */
02505   if (hdma->Init.Mode != DMA_CIRCULAR)
02506   {
02507     hirda->RxXferCount = 0U;
02508
02509     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02510     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
02511     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02512
02513     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02514        in the IRDA CR3 register */
02515     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
02516
02517     /* At end of Rx process, restore hirda->RxState to Ready */
02518     hirda->RxState = HAL_IRDA_STATE_READY;
02519   }
02520
02521 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02522   /* Call registered Rx complete callback */
02523   hirda->RxCpltCallback(hirda);
02524 #else
02525   /* Call legacy weak Rx complete callback */
02526   HAL_IRDA_RxCpltCallback(hirda);
02527 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02528 }
02529
02530 /**
02531   * @brief DMA IRDA receive process half complete callback.
02532   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02533   *              the configuration information for the specified DMA module.
02534   * @retval None
02535   */
02536 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
02537 {
02538   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02539
02540 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02541   /*Call registered Rx Half complete callback*/
02542   hirda->RxHalfCpltCallback(hirda);
02543 #else
02544   /* Call legacy weak Rx Half complete callback */
02545   HAL_IRDA_RxHalfCpltCallback(hirda);
02546 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02547 }
02548
02549 /**
02550   * @brief DMA IRDA communication error callback.
02551   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02552   *              the configuration information for the specified DMA module.
02553   * @retval None
02554   */
02555 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
02556 {
02557   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02558
02559   /* Stop IRDA DMA Tx request if ongoing */
02560   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02561   {
02562     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
02563     {
02564       hirda->TxXferCount = 0U;
02565       IRDA_EndTxTransfer(hirda);
02566     }
02567   }
02568
02569   /* Stop IRDA DMA Rx request if ongoing */
02570   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02571   {
02572     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
02573     {
02574       hirda->RxXferCount = 0U;
02575       IRDA_EndRxTransfer(hirda);
02576     }
02577   }
02578
02579   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
02580 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02581   /* Call registered user error callback */
02582   hirda->ErrorCallback(hirda);
02583 #else
02584   /* Call legacy weak user error callback */
02585   HAL_IRDA_ErrorCallback(hirda);
02586 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02587 }
02588
02589 /**
02590   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
02591   *         (To be called at end of DMA Abort procedure following error occurrence).
02592   * @param  hdma DMA handle.
02593   * @retval None
02594   */
02595 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02596 {
02597   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02598   hirda->RxXferCount = 0U;
02599   hirda->TxXferCount = 0U;
02600
02601 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02602   /* Call registered user error callback */
02603   hirda->ErrorCallback(hirda);
02604 #else
02605   /* Call legacy weak user error callback */
02606   HAL_IRDA_ErrorCallback(hirda);
02607 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02608 }
02609
02610 /**
02611   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02612   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02613   * @note   When this callback is executed, User Abort complete call back is called only if no
02614   *         Abort still ongoing for Rx DMA Handle.
02615   * @param  hdma DMA handle.
02616   * @retval None
02617   */
02618 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02619 {
02620   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02621
02622   hirda->hdmatx->XferAbortCallback = NULL;
02623
02624   /* Check if an Abort process is still ongoing */
02625   if (hirda->hdmarx != NULL)
02626   {
02627     if (hirda->hdmarx->XferAbortCallback != NULL)
02628     {
02629       return;
02630     }
02631   }
02632
02633   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02634   hirda->TxXferCount = 0U;
02635   hirda->RxXferCount = 0U;
02636
02637   /* Reset errorCode */
02638   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02639
02640   /* Clear the Error flags in the ICR register */
02641   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02642
02643   /* Restore hirda->gState and hirda->RxState to Ready */
02644   hirda->gState  = HAL_IRDA_STATE_READY;
02645   hirda->RxState = HAL_IRDA_STATE_READY;
02646
02647   /* Call user Abort complete callback */
02648 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02649   /* Call registered Abort complete callback */
02650   hirda->AbortCpltCallback(hirda);
02651 #else
02652   /* Call legacy weak Abort complete callback */
02653   HAL_IRDA_AbortCpltCallback(hirda);
02654 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02655 }
02656
02657
02658 /**
02659   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02660   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02661   * @note   When this callback is executed, User Abort complete call back is called only if no
02662   *         Abort still ongoing for Tx DMA Handle.
02663   * @param  hdma DMA handle.
02664   * @retval None
02665   */
02666 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02667 {
02668   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02669
02670   hirda->hdmarx->XferAbortCallback = NULL;
02671
02672   /* Check if an Abort process is still ongoing */
02673   if (hirda->hdmatx != NULL)
02674   {
02675     if (hirda->hdmatx->XferAbortCallback != NULL)
02676     {
02677       return;
02678     }
02679   }
02680
02681   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02682   hirda->TxXferCount = 0U;
02683   hirda->RxXferCount = 0U;
02684
02685   /* Reset errorCode */
02686   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02687
02688   /* Clear the Error flags in the ICR register */
02689   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02690
02691   /* Restore hirda->gState and hirda->RxState to Ready */
02692   hirda->gState  = HAL_IRDA_STATE_READY;
02693   hirda->RxState = HAL_IRDA_STATE_READY;
02694
02695   /* Call user Abort complete callback */
02696 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02697   /* Call registered Abort complete callback */
02698   hirda->AbortCpltCallback(hirda);
02699 #else
02700   /* Call legacy weak Abort complete callback */
02701   HAL_IRDA_AbortCpltCallback(hirda);
02702 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02703 }
02704
02705
02706 /**
02707   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02708   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02709   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02710   *         and leads to user Tx Abort Complete callback execution).
02711   * @param  hdma DMA handle.
02712   * @retval None
02713   */
02714 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02715 {
02716   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02717
02718   hirda->TxXferCount = 0U;
02719
02720   /* Restore hirda->gState to Ready */
02721   hirda->gState = HAL_IRDA_STATE_READY;
02722
02723   /* Call user Abort complete callback */
02724 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02725   /* Call registered Abort Transmit Complete Callback */
02726   hirda->AbortTransmitCpltCallback(hirda);
02727 #else
02728   /* Call legacy weak Abort Transmit Complete Callback */
02729   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02730 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02731 }
02732
02733 /**
02734   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02735   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02736   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02737   *         and leads to user Rx Abort Complete callback execution).
02738   * @param  hdma DMA handle.
02739   * @retval None
02740   */
02741 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02742 {
02743   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02744
02745   hirda->RxXferCount = 0U;
02746
02747   /* Clear the Error flags in the ICR register */
02748   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02749
02750   /* Restore hirda->RxState to Ready */
02751   hirda->RxState = HAL_IRDA_STATE_READY;
02752
02753   /* Call user Abort complete callback */
02754 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02755   /* Call registered Abort Receive Complete Callback */
02756   hirda->AbortReceiveCpltCallback(hirda);
02757 #else
02758   /* Call legacy weak Abort Receive Complete Callback */
02759   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02760 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02761 }
02762
02763 /**
02764   * @brief  Send an amount of data in interrupt mode.
02765   * @note   Function is called under interruption only, once
02766   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02767   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02768   *               the configuration information for the specified IRDA module.
02769   * @retval None
02770   */
02771 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02772 {
02773   uint16_t *tmp;
02774
02775   /* Check that a Tx process is ongoing */
02776   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02777   {
02778     if (hirda->TxXferCount == 0U)
02779     {
02780       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02781       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02782
02783       /* Enable the IRDA Transmit Complete Interrupt */
02784       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02785     }
02786     else
02787     {
02788       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02789       {
02790         tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
02791         hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
02792         hirda->pTxBuffPtr += 2U;
02793       }
02794       else
02795       {
02796         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
02797         hirda->pTxBuffPtr++;
02798       }
02799       hirda->TxXferCount--;
02800     }
02801   }
02802 }
02803
02804 /**
02805   * @brief  Wrap up transmission in non-blocking mode.
02806   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02807   *               the configuration information for the specified IRDA module.
02808   * @retval None
02809   */
02810 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02811 {
02812   /* Disable the IRDA Transmit Complete Interrupt */
02813   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02814
02815   /* Tx process is ended, restore hirda->gState to Ready */
02816   hirda->gState = HAL_IRDA_STATE_READY;
02817
02818 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02819   /* Call registered Tx complete callback */
02820   hirda->TxCpltCallback(hirda);
02821 #else
02822   /* Call legacy weak Tx complete callback */
02823   HAL_IRDA_TxCpltCallback(hirda);
02824 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02825 }
02826
02827 /**
02828   * @brief  Receive an amount of data in interrupt mode.
02829   * @note   Function is called under interruption only, once
02830   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
02831   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02832   *               the configuration information for the specified IRDA module.
02833   * @retval None
02834   */
02835 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02836 {
02837   uint16_t *tmp;
02838   uint16_t  uhMask = hirda->Mask;
02839   uint16_t  uhdata;
02840
02841   /* Check that a Rx process is ongoing */
02842   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02843   {
02844     uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
02845     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02846     {
02847       tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
02848       *tmp = (uint16_t)(uhdata & uhMask);
02849       hirda->pRxBuffPtr  += 2U;
02850     }
02851     else
02852     {
02853       *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
02854       hirda->pRxBuffPtr++;
02855     }
02856
02857     hirda->RxXferCount--;
02858     if (hirda->RxXferCount == 0U)
02859     {
02860       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02861       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02862
02863       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02864       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02865
02866       /* Rx process is completed, restore hirda->RxState to Ready */
02867       hirda->RxState = HAL_IRDA_STATE_READY;
02868
02869 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02870       /* Call registered Rx complete callback */
02871       hirda->RxCpltCallback(hirda);
02872 #else
02873       /* Call legacy weak Rx complete callback */
02874       HAL_IRDA_RxCpltCallback(hirda);
02875 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02876     }
02877   }
02878   else
02879   {
02880     /* Clear RXNE interrupt flag */
02881     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02882   }
02883 }
02884
02885 /**
02886   * @}
02887   */
02888
02889 #endif /* HAL_IRDA_MODULE_ENABLED */
02890 /**
02891   * @}
02892   */
02893
02894 /**
02895   * @}
02896   */
02897
02898 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda.h Source File

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stm32h7xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_IRDA_H
00022 #define STM32H7xx_HAL_IRDA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup IRDA
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief IRDA Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051                                               Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
00052                                            where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
00053
00054   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00055                                            This parameter can be a value of @ref IRDAEx_Word_Length */
00056
00057   uint32_t Parity;                    /*!< Specifies the parity mode.
00058                                            This parameter can be a value of @ref IRDA_Parity
00059                                            @note When parity is enabled, the computed parity is inserted
00060                                                  at the MSB position of the transmitted data (9th bit when
00061                                                  the word length is set to 9 data bits; 8th bit when the
00062                                                  word length is set to 8 data bits). */
00063
00064   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00065                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00066
00067   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00068                                            to achieve low-power frequency.
00069                                            @note Prescaler value 0 is forbidden */
00070
00071   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00072                                            This parameter can be a value of @ref IRDA_Low_Power */
00073
00074   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
00075                                            This parameter can be a value of @ref IRDA_ClockPrescaler. */
00076
00077 } IRDA_InitTypeDef;
00078
00079 /**
00080   * @brief HAL IRDA State definition
00081   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
00082   *        - gState contains IRDA state information related to global Handle management
00083   *          and also information related to Tx operations.
00084   *          gState value coding follow below described bitmap :
00085   *          b7-b6  Error information
00086   *             00 : No Error
00087   *             01 : (Not Used)
00088   *             10 : Timeout
00089   *             11 : Error
00090   *          b5     Peripheral initialization status
00091   *             0  : Reset (Peripheral not initialized)
00092   *             1  : Init done (Peripheral not initialized. HAL IRDA Init function already called)
00093   *          b4-b3  (not used)
00094   *             xx : Should be set to 00
00095   *          b2     Intrinsic process state
00096   *             0  : Ready
00097   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00098   *          b1     (not used)
00099   *             x  : Should be set to 0
00100   *          b0     Tx state
00101   *             0  : Ready (no Tx operation ongoing)
00102   *             1  : Busy (Tx operation ongoing)
00103   *        - RxState contains information related to Rx operations.
00104   *          RxState value coding follow below described bitmap :
00105   *          b7-b6  (not used)
00106   *             xx : Should be set to 00
00107   *          b5     Peripheral initialization status
00108   *             0  : Reset (Peripheral not initialized)
00109   *             1  : Init done (Peripheral not initialized)
00110   *          b4-b2  (not used)
00111   *            xxx : Should be set to 000
00112   *          b1     Rx state
00113   *             0  : Ready (no Rx operation ongoing)
00114   *             1  : Busy (Rx operation ongoing)
00115   *          b0     (not used)
00116   *             x  : Should be set to 0.
00117   */
00118 typedef uint32_t HAL_IRDA_StateTypeDef;
00119
00120 /**
00121   * @brief IRDA clock sources definition
00122   */
00123 typedef enum
00124 {
00125   IRDA_CLOCKSOURCE_D2PCLK1    = 0x11U,    /*!< Domain2 PCLK1 clock source */
00126   IRDA_CLOCKSOURCE_D2PCLK2    = 0x12U,    /*!< Domain2 PCLK2 clock source */
00127   IRDA_CLOCKSOURCE_PLL2Q      = 0x14U,    /*!< PLL2Q clock source         */
00128   IRDA_CLOCKSOURCE_PLL3Q      = 0x18U,    /*!< PCLK2 clock source         */
00129   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
00130   IRDA_CLOCKSOURCE_CSI        = 0x08U,    /*!< CSI clock source           */
00131   IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
00132   IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
00133 } IRDA_ClockSourceTypeDef;
00134
00135 /**
00136   * @brief  IRDA handle Structure definition
00137   */
00138 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00139 typedef struct __IRDA_HandleTypeDef
00140 #else
00141 typedef struct
00142 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00143 {
00144   USART_TypeDef            *Instance;        /*!< USART registers base address       */
00145
00146   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00147
00148   uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00149
00150   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00151
00152   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00153
00154   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00155
00156   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00157
00158   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00159
00160   uint16_t                 Mask;             /*!< USART RX RDR register mask         */
00161
00162   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00163
00164   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00165
00166   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00167
00168   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00169                                                   and also related to Tx operations.
00170                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00171
00172   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00173                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00174
00175   __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
00176
00177 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00178   void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
00179
00180   void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
00181
00182   void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
00183
00184   void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
00185
00186   void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
00187
00188   void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
00189
00190   void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
00191
00192   void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
00193
00194
00195   void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
00196
00197   void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
00198 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00199
00200 } IRDA_HandleTypeDef;
00201
00202 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00203 /**
00204   * @brief  HAL IRDA Callback ID enumeration definition
00205   */
00206 typedef enum
00207 {
00208   HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
00209   HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
00210   HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
00211   HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
00212   HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
00213   HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
00214   HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
00215   HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
00216
00217   HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
00218   HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
00219
00220 } HAL_IRDA_CallbackIDTypeDef;
00221
00222 /**
00223   * @brief  HAL IRDA Callback pointer definition
00224   */
00225 typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
00226
00227 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /* Exported constants --------------------------------------------------------*/
00234 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00235   * @{
00236   */
00237
00238 /** @defgroup IRDA_State_Definition IRDA State Code Definition
00239   * @{
00240   */
00241 #define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
00242                                                                Value is allowed for gState and RxState */
00243 #define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
00244                                                                Value is allowed for gState and RxState */
00245 #define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
00246                                                                Value is allowed for gState only */
00247 #define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
00248                                                                Value is allowed for gState only */
00249 #define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
00250                                                                Value is allowed for RxState only */
00251 #define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
00252                                                                Not to be used for neither gState nor RxState.
00253                                                                Value is result of combination (Or) between gState and RxState values */
00254 #define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
00255                                                                Value is allowed for gState only */
00256 #define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
00257                                                                Value is allowed for gState only */
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup IRDA_Error_Definition IRDA Error Code Definition
00263   * @{
00264   */
00265 #define HAL_IRDA_ERROR_NONE                 ((uint32_t)0x00000000U)          /*!< No error                */
00266 #define HAL_IRDA_ERROR_PE                   ((uint32_t)0x00000001U)          /*!< Parity error            */
00267 #define HAL_IRDA_ERROR_NE                   ((uint32_t)0x00000002U)          /*!< Noise error             */
00268 #define HAL_IRDA_ERROR_FE                   ((uint32_t)0x00000004U)          /*!< frame error             */
00269 #define HAL_IRDA_ERROR_ORE                  ((uint32_t)0x00000008U)          /*!< Overrun error           */
00270 #define HAL_IRDA_ERROR_DMA                  ((uint32_t)0x00000010U)          /*!< DMA transfer error      */
00271 #define HAL_IRDA_ERROR_BUSY                 ((uint32_t)0x00000020U)          /*!< Busy Error              */
00272 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00273 #define HAL_IRDA_ERROR_INVALID_CALLBACK     ((uint32_t)0x00000040U)          /*!< Invalid Callback error  */
00274 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup IRDA_Parity IRDA Parity
00280   * @{
00281   */
00282 #define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
00283 #define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
00284 #define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00290   * @{
00291   */
00292 #define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
00293 #define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
00294 #define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup IRDA_Low_Power IRDA Low Power
00300   * @{
00301   */
00302 #define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
00303 #define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
00309   * @{
00310   */
00311 #define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00312 #define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00313 #define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00314 #define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00315 #define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00316 #define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00317 #define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00318 #define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00319 #define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00320 #define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00321 #define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00322 #define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup IRDA_State IRDA State
00328   * @{
00329   */
00330 #define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
00331 #define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup IRDA_Mode IRDA Mode
00337   * @{
00338   */
00339 #define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
00340 #define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup IRDA_One_Bit IRDA One Bit Sampling
00346   * @{
00347   */
00348 #define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
00349 #define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00355   * @{
00356   */
00357 #define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
00358 #define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
00364   * @{
00365   */
00366 #define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
00367 #define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00373   * @{
00374   */
00375 #define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00376 #define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00377 #define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup IRDA_Flags IRDA Flags
00383   *        Elements values convention: 0xXXXX
00384   *           - 0xXXXX  : Flag mask in the ISR register
00385   * @{
00386   */
00387 #define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
00388 #define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
00389 #define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
00390 #define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
00391 #define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
00392 #define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
00393 #define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
00394 #define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
00395 #define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
00396 #define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
00397 #define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
00398 #define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00404   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00405   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00406   *           - XX  : Interrupt source register (2bits)
00407   *                 - 01: CR1 register
00408   *                 - 10: CR2 register
00409   *                 - 11: CR3 register
00410   *           - ZZZZ  : Flag position in the ISR register(4bits)
00411   * @{
00412   */
00413 #define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
00414 #define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
00415 #define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
00416 #define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
00417 #define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
00418
00419 /*       Elements values convention: 000000000XXYYYYYb
00420              - YYYYY  : Interrupt source position in the XX register (5bits)
00421              - XX  : Interrupt source register (2bits)
00422                    - 01: CR1 register
00423                    - 10: CR2 register
00424                    - 11: CR3 register */
00425 #define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
00426
00427 /*       Elements values convention: 0000ZZZZ00000000b
00428              - ZZZZ  : Flag position in the ISR register(4bits) */
00429 #define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
00430 #define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
00431 #define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
00437   * @{
00438   */
00439 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00440 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00441 #define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
00442 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00443 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00444 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
00450   * @{
00451   */
00452 #define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
00453 #define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
00454 #define IRDA_CR_POS   5U       /*!< IRDA control register position */
00455 #define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
00456 #define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Exported macros -----------------------------------------------------------*/
00466 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00467   * @{
00468   */
00469
00470 /** @brief  Reset IRDA handle state.
00471   * @param  __HANDLE__ IRDA handle.
00472   * @retval None
00473   */
00474 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00475 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00476                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00477                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00478                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00479                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00480                                                      } while(0U)
00481 #else
00482 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00483                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00484                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00485                                                      } while(0U)
00486 #endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
00487
00488 /** @brief  Flush the IRDA DR register.
00489   * @param  __HANDLE__ specifies the IRDA Handle.
00490   * @retval None
00491   */
00492 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00493   do{                                                                    \
00494     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00495     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00496   } while(0U)
00497
00498 /** @brief  Clear the specified IRDA pending flag.
00499   * @param  __HANDLE__ specifies the IRDA Handle.
00500   * @param  __FLAG__ specifies the flag to check.
00501   *          This parameter can be any combination of the following values:
00502   *            @arg @ref IRDA_CLEAR_PEF
00503   *            @arg @ref IRDA_CLEAR_FEF
00504   *            @arg @ref IRDA_CLEAR_NEF
00505   *            @arg @ref IRDA_CLEAR_OREF
00506   *            @arg @ref IRDA_CLEAR_TCF
00507   *            @arg @ref IRDA_CLEAR_IDLEF
00508   * @retval None
00509   */
00510 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00511
00512 /** @brief  Clear the IRDA PE pending flag.
00513   * @param  __HANDLE__ specifies the IRDA Handle.
00514   * @retval None
00515   */
00516 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00517
00518
00519 /** @brief  Clear the IRDA FE pending flag.
00520   * @param  __HANDLE__ specifies the IRDA Handle.
00521   * @retval None
00522   */
00523 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00524
00525 /** @brief  Clear the IRDA NE pending flag.
00526   * @param  __HANDLE__ specifies the IRDA Handle.
00527   * @retval None
00528   */
00529 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00530
00531 /** @brief  Clear the IRDA ORE pending flag.
00532   * @param  __HANDLE__ specifies the IRDA Handle.
00533   * @retval None
00534   */
00535 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00536
00537 /** @brief  Clear the IRDA IDLE pending flag.
00538   * @param  __HANDLE__ specifies the IRDA Handle.
00539   * @retval None
00540   */
00541 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00542
00543 /** @brief  Check whether the specified IRDA flag is set or not.
00544   * @param  __HANDLE__ specifies the IRDA Handle.
00545   * @param  __FLAG__ specifies the flag to check.
00546   *        This parameter can be one of the following values:
00547   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00548   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00549   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00550   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00551   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00552   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00553   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00554   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00555   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00556   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00557   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00558   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00559   * @retval The new state of __FLAG__ (TRUE or FALSE).
00560   */
00561 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00562
00563
00564 /** @brief  Enable the specified IRDA interrupt.
00565   * @param  __HANDLE__ specifies the IRDA Handle.
00566   * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
00567   *          This parameter can be one of the following values:
00568   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00569   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00570   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00571   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00572   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00573   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00574   * @retval None
00575   */
00576 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00577                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00578                                                            ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00579
00580 /** @brief  Disable the specified IRDA interrupt.
00581   * @param  __HANDLE__ specifies the IRDA Handle.
00582   * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
00583   *          This parameter can be one of the following values:
00584   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00585   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00586   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00587   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00588   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00589   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00590   * @retval None
00591   */
00592 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00593                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00594                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00595
00596
00597 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00598   * @param  __HANDLE__ specifies the IRDA Handle.
00599   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00600   *          This parameter can be one of the following values:
00601   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00602   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00603   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00604   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00605   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00606   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00607   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00608   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00609   * @retval The new state of __IT__ (SET or RESET).
00610   */
00611 #define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00612                                                         & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
00613
00614 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00615   * @param  __HANDLE__ specifies the IRDA Handle.
00616   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00617   *          This parameter can be one of the following values:
00618   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00619   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00620   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00621   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00622   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00623   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00624   * @retval The new state of __IT__ (SET or RESET).
00625   */
00626 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
00627                                                                 (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
00628                                                                  (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
00629
00630 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00631   * @param  __HANDLE__ specifies the IRDA Handle.
00632   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00633   *                       to clear the corresponding interrupt
00634   *          This parameter can be one of the following values:
00635   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00636   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00637   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00638   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00639   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00640   * @retval None
00641   */
00642 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00643
00644
00645 /** @brief  Set a specific IRDA request flag.
00646   * @param  __HANDLE__ specifies the IRDA Handle.
00647   * @param  __REQ__ specifies the request flag to set
00648   *          This parameter can be one of the following values:
00649   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00650   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00651   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00652   * @retval None
00653   */
00654 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00655
00656 /** @brief  Enable the IRDA one bit sample method.
00657   * @param  __HANDLE__ specifies the IRDA Handle.
00658   * @retval None
00659   */
00660 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00661
00662 /** @brief  Disable the IRDA one bit sample method.
00663   * @param  __HANDLE__ specifies the IRDA Handle.
00664   * @retval None
00665   */
00666 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00667                                                        &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00668
00669 /** @brief  Enable UART/USART associated to IRDA Handle.
00670   * @param  __HANDLE__ specifies the IRDA Handle.
00671   * @retval None
00672   */
00673 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00674
00675 /** @brief  Disable UART/USART associated to IRDA Handle.
00676   * @param  __HANDLE__ specifies the IRDA Handle.
00677   * @retval None
00678   */
00679 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00680
00681 /**
00682   * @}
00683   */
00684
00685 /* Private macros --------------------------------------------------------*/
00686 /** @addtogroup IRDA_Private_Macros
00687   * @{
00688   */
00689
00690 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00691   * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
00692   * @retval True or False
00693   */
00694 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
00695
00696 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00697   * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
00698   * @retval True or False
00699   */
00700 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
00701
00702 /** @brief Ensure that IRDA frame parity is valid.
00703   * @param __PARITY__ IRDA frame parity.
00704   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00705   */
00706 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00707                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00708                                     ((__PARITY__) == IRDA_PARITY_ODD))
00709
00710 /** @brief Ensure that IRDA communication mode is valid.
00711   * @param __MODE__ IRDA communication mode.
00712   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00713   */
00714 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
00715                                         & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
00716
00717 /** @brief Ensure that IRDA power mode is valid.
00718   * @param __MODE__ IRDA power mode.
00719   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00720   */
00721 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00722                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00723
00724 /** @brief Ensure that IRDA clock Prescaler is valid.
00725   * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
00726   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00727   */
00728 #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
00729                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
00730                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
00731                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
00732                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
00733                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
00734                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
00735                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
00736                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
00737                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
00738                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
00739                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
00740
00741 /** @brief Ensure that IRDA state is valid.
00742   * @param __STATE__ IRDA state mode.
00743   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00744   */
00745 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00746                                   ((__STATE__) == IRDA_STATE_ENABLE))
00747
00748 /** @brief Ensure that IRDA associated UART/USART mode is valid.
00749   * @param __MODE__ IRDA associated UART/USART mode.
00750   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00751   */
00752 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00753                                  ((__MODE__) == IRDA_MODE_ENABLE))
00754
00755 /** @brief Ensure that IRDA sampling rate is valid.
00756   * @param __ONEBIT__ IRDA sampling rate.
00757   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00758   */
00759 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00760                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00761
00762 /** @brief Ensure that IRDA DMA TX mode is valid.
00763   * @param __DMATX__ IRDA DMA TX mode.
00764   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00765   */
00766 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00767                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00768
00769 /** @brief Ensure that IRDA DMA RX mode is valid.
00770   * @param __DMARX__ IRDA DMA RX mode.
00771   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00772   */
00773 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00774                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00775
00776 /** @brief Ensure that IRDA request is valid.
00777   * @param __PARAM__ IRDA request.
00778   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00779   */
00780 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00781                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00782                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00783 /**
00784   * @}
00785   */
00786
00787 /* Include IRDA HAL Extended module */
00788 #include "stm32h7xx_hal_irda_ex.h"
00789
00790 /* Exported functions --------------------------------------------------------*/
00791 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00792   * @{
00793   */
00794
00795 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00796   * @{
00797   */
00798
00799 /* Initialization and de-initialization functions  ****************************/
00800 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00801 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00802 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00803 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00804
00805 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00806 /* Callbacks Register/UnRegister functions  ***********************************/
00807 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00808                                             pIRDA_CallbackTypeDef pCallback);
00809 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
00810 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00817   * @{
00818   */
00819
00820 /* IO operation functions *****************************************************/
00821 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00822 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00823 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00824 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00825 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00826 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00827 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00828 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00829 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00830 /* Transfer Abort functions */
00831 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00832 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00833 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00834 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00835 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00836 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00837
00838 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00839 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00840 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00841 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00842 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00843 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00844 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
00845 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
00846 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
00847
00848 /**
00849   * @}
00850   */
00851
00852 /* Peripheral Control functions  ************************************************/
00853
00854 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00855   * @{
00856   */
00857
00858 /* Peripheral State and Error functions ***************************************/
00859 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00860 uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00861
00862 /**
00863   * @}
00864   */
00865
00866 /**
00867   * @}
00868   */
00869
00870 /**
00871   * @}
00872   */
00873
00874 /**
00875   * @}
00876   */
00877
00878 #ifdef __cplusplus
00879 }
00880 #endif
00881
00882 #endif /* STM32H7xx_HAL_IRDA_H */
00883
00884 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_irda_ex.h Source File

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stm32h7xx_hal_irda_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_IRDA_EX_H
00022 #define STM32H7xx_HAL_IRDA_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup IRDAEx IRDAEx
00036   * @brief IRDA Extended HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /* Exported constants --------------------------------------------------------*/
00042 /** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup IRDAEx_Word_Length IRDAEx Word Length
00047   * @{
00048   */
00049 #define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
00050 #define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
00051 #define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
00052 /**
00053   * @}
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /* Exported macros -----------------------------------------------------------*/
00061
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00065   * @{
00066   */
00067
00068 /** @brief  Report the IRDA clock source.
00069   * @param  __HANDLE__ specifies the IRDA Handle.
00070   * @param  __CLOCKSOURCE__ output variable.
00071   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00072   */
00073 #if defined(UART9) && defined(USART10)
00074 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00075   do {                                                        \
00076     if((__HANDLE__)->Instance == USART1)                      \
00077     {                                                         \
00078       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00079       {                                                       \
00080         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00081           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00082           break;                                              \
00083         case RCC_USART1CLKSOURCE_PLL2:                        \
00084           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00085           break;                                              \
00086         case RCC_USART1CLKSOURCE_PLL3:                        \
00087           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00088           break;                                              \
00089         case RCC_USART1CLKSOURCE_HSI:                         \
00090           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00091           break;                                              \
00092         case RCC_USART1CLKSOURCE_CSI:                         \
00093           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00094           break;                                              \
00095         case RCC_USART1CLKSOURCE_LSE:                         \
00096           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00097           break;                                              \
00098         default:                                              \
00099           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00100           break;                                              \
00101       }                                                       \
00102     }                                                         \
00103     else if((__HANDLE__)->Instance == USART2)                 \
00104     {                                                         \
00105       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00106       {                                                       \
00107         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00108           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00109           break;                                              \
00110         case RCC_USART2CLKSOURCE_PLL2:                        \
00111           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00112           break;                                              \
00113         case RCC_USART2CLKSOURCE_PLL3:                        \
00114           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00115           break;                                              \
00116         case RCC_USART2CLKSOURCE_HSI:                         \
00117           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00118           break;                                              \
00119         case RCC_USART2CLKSOURCE_CSI:                         \
00120           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00121           break;                                              \
00122         case RCC_USART2CLKSOURCE_LSE:                         \
00123           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00124           break;                                              \
00125         default:                                              \
00126           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00127           break;                                              \
00128       }                                                       \
00129     }                                                         \
00130     else if((__HANDLE__)->Instance == USART3)                 \
00131     {                                                         \
00132       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00133       {                                                       \
00134         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00135           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00136           break;                                              \
00137         case RCC_USART3CLKSOURCE_PLL2:                        \
00138           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00139           break;                                              \
00140         case RCC_USART3CLKSOURCE_PLL3:                        \
00141           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00142           break;                                              \
00143         case RCC_USART3CLKSOURCE_HSI:                         \
00144           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00145           break;                                              \
00146         case RCC_USART3CLKSOURCE_CSI:                         \
00147           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00148           break;                                              \
00149         case RCC_USART3CLKSOURCE_LSE:                         \
00150           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00151           break;                                              \
00152         default:                                              \
00153           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00154           break;                                              \
00155       }                                                       \
00156     }                                                         \
00157     else if((__HANDLE__)->Instance == UART4)                  \
00158     {                                                         \
00159       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00160       {                                                       \
00161         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00162           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00163           break;                                              \
00164         case RCC_UART4CLKSOURCE_PLL2:                         \
00165           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00166           break;                                              \
00167         case RCC_UART4CLKSOURCE_PLL3:                         \
00168           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00169           break;                                              \
00170         case RCC_UART4CLKSOURCE_HSI:                          \
00171           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00172           break;                                              \
00173         case RCC_UART4CLKSOURCE_CSI:                          \
00174           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00175           break;                                              \
00176         case RCC_UART4CLKSOURCE_LSE:                          \
00177           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00178           break;                                              \
00179         default:                                              \
00180           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00181           break;                                              \
00182       }                                                       \
00183     }                                                         \
00184     else if ((__HANDLE__)->Instance == UART5)                 \
00185     {                                                         \
00186       switch(__HAL_RCC_GET_UART5_SOURCE())                    \
00187       {                                                       \
00188         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00189           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00190           break;                                              \
00191         case RCC_UART5CLKSOURCE_PLL2:                         \
00192           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00193           break;                                              \
00194         case RCC_UART5CLKSOURCE_PLL3:                         \
00195           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00196           break;                                              \
00197         case RCC_UART5CLKSOURCE_HSI:                          \
00198           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00199           break;                                              \
00200         case RCC_UART5CLKSOURCE_CSI:                          \
00201           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00202           break;                                              \
00203         case RCC_UART5CLKSOURCE_LSE:                          \
00204           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00205           break;                                              \
00206         default:                                              \
00207           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00208           break;                                              \
00209       }                                                       \
00210     }                                                         \
00211     else if((__HANDLE__)->Instance == USART6)                 \
00212     {                                                         \
00213       switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00214       {                                                       \
00215         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00216           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00217           break;                                              \
00218         case RCC_USART6CLKSOURCE_PLL2:                        \
00219           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00220           break;                                              \
00221         case RCC_USART6CLKSOURCE_PLL3:                        \
00222           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00223           break;                                              \
00224         case RCC_USART6CLKSOURCE_HSI:                         \
00225           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00226           break;                                              \
00227         case RCC_USART6CLKSOURCE_CSI:                         \
00228           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00229           break;                                              \
00230         case RCC_USART6CLKSOURCE_LSE:                         \
00231           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00232           break;                                              \
00233         default:                                              \
00234           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00235           break;                                              \
00236       }                                                       \
00237     }                                                         \
00238     else if((__HANDLE__)->Instance == UART7)                  \
00239     {                                                         \
00240       switch(__HAL_RCC_GET_UART7_SOURCE())                    \
00241       {                                                       \
00242         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00243           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00244           break;                                              \
00245         case RCC_UART7CLKSOURCE_PLL2:                         \
00246           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00247           break;                                              \
00248         case RCC_UART7CLKSOURCE_PLL3:                         \
00249           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00250           break;                                              \
00251         case RCC_UART7CLKSOURCE_HSI:                          \
00252           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00253           break;                                              \
00254         case RCC_UART7CLKSOURCE_CSI:                          \
00255           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00256           break;                                              \
00257         case RCC_UART7CLKSOURCE_LSE:                          \
00258           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00259           break;                                              \
00260         default:                                              \
00261           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00262           break;                                              \
00263       }                                                       \
00264     }                                                         \
00265     else if((__HANDLE__)->Instance == UART8)                  \
00266     {                                                         \
00267       switch(__HAL_RCC_GET_UART8_SOURCE())                    \
00268       {                                                       \
00269         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00270           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00271           break;                                              \
00272         case RCC_UART8CLKSOURCE_PLL2:                         \
00273           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00274           break;                                              \
00275         case RCC_UART8CLKSOURCE_PLL3:                         \
00276           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00277           break;                                              \
00278         case RCC_UART8CLKSOURCE_HSI:                          \
00279           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00280           break;                                              \
00281         case RCC_UART8CLKSOURCE_CSI:                          \
00282           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00283           break;                                              \
00284         case RCC_UART8CLKSOURCE_LSE:                          \
00285           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00286           break;                                              \
00287         default:                                              \
00288           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00289           break;                                              \
00290       }                                                       \
00291     }                                                         \
00292     else if((__HANDLE__)->Instance == UART9)                  \
00293     {                                                         \
00294       switch(__HAL_RCC_GET_UART9_SOURCE())                    \
00295       {                                                       \
00296         case RCC_UART9CLKSOURCE_D2PCLK2:                      \
00297           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00298           break;                                              \
00299         case RCC_UART9CLKSOURCE_PLL2:                         \
00300           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00301           break;                                              \
00302         case RCC_UART9CLKSOURCE_PLL3:                         \
00303           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00304           break;                                              \
00305         case RCC_UART9CLKSOURCE_HSI:                          \
00306           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00307           break;                                              \
00308         case RCC_UART9CLKSOURCE_CSI:                          \
00309           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00310           break;                                              \
00311         case RCC_UART9CLKSOURCE_LSE:                          \
00312           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00313           break;                                              \
00314         default:                                              \
00315           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00316           break;                                              \
00317       }                                                       \
00318     }                                                         \
00319     else if((__HANDLE__)->Instance == USART10)                \
00320     {                                                         \
00321       switch(__HAL_RCC_GET_USART10_SOURCE())                  \
00322       {                                                       \
00323         case RCC_USART10CLKSOURCE_D2PCLK2:                    \
00324           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00325           break;                                              \
00326         case RCC_USART10CLKSOURCE_PLL2:                       \
00327           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00328           break;                                              \
00329         case RCC_USART10CLKSOURCE_PLL3:                       \
00330           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00331           break;                                              \
00332         case RCC_USART10CLKSOURCE_HSI:                        \
00333           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00334           break;                                              \
00335         case RCC_USART10CLKSOURCE_CSI:                        \
00336           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00337           break;                                              \
00338         case RCC_USART10CLKSOURCE_LSE:                        \
00339           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00340           break;                                              \
00341         default:                                              \
00342           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00343           break;                                              \
00344       }                                                       \
00345     }                                                         \
00346     else                                                      \
00347     {                                                         \
00348       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00349     }                                                         \
00350   } while(0U)
00351 #else
00352 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00353   do {                                                        \
00354     if((__HANDLE__)->Instance == USART1)                      \
00355     {                                                         \
00356       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00357       {                                                       \
00358         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00359           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00360           break;                                              \
00361         case RCC_USART1CLKSOURCE_PLL2:                        \
00362           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00363           break;                                              \
00364         case RCC_USART1CLKSOURCE_PLL3:                        \
00365           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00366           break;                                              \
00367         case RCC_USART1CLKSOURCE_HSI:                         \
00368           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00369           break;                                              \
00370         case RCC_USART1CLKSOURCE_CSI:                         \
00371           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00372           break;                                              \
00373         case RCC_USART1CLKSOURCE_LSE:                         \
00374           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00375           break;                                              \
00376         default:                                              \
00377           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00378           break;                                              \
00379       }                                                       \
00380     }                                                         \
00381     else if((__HANDLE__)->Instance == USART2)                 \
00382     {                                                         \
00383       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00384       {                                                       \
00385         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00386           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00387           break;                                              \
00388         case RCC_USART2CLKSOURCE_PLL2:                        \
00389           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00390           break;                                              \
00391         case RCC_USART2CLKSOURCE_PLL3:                        \
00392           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00393           break;                                              \
00394         case RCC_USART2CLKSOURCE_HSI:                         \
00395           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00396           break;                                              \
00397         case RCC_USART2CLKSOURCE_CSI:                         \
00398           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00399           break;                                              \
00400         case RCC_USART2CLKSOURCE_LSE:                         \
00401           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00402           break;                                              \
00403         default:                                              \
00404           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00405           break;                                              \
00406       }                                                       \
00407     }                                                         \
00408     else if((__HANDLE__)->Instance == USART3)                 \
00409     {                                                         \
00410       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00411       {                                                       \
00412         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00413           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00414           break;                                              \
00415         case RCC_USART3CLKSOURCE_PLL2:                        \
00416           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00417           break;                                              \
00418         case RCC_USART3CLKSOURCE_PLL3:                        \
00419           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00420           break;                                              \
00421         case RCC_USART3CLKSOURCE_HSI:                         \
00422           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00423           break;                                              \
00424         case RCC_USART3CLKSOURCE_CSI:                         \
00425           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00426           break;                                              \
00427         case RCC_USART3CLKSOURCE_LSE:                         \
00428           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00429           break;                                              \
00430         default:                                              \
00431           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00432           break;                                              \
00433       }                                                       \
00434     }                                                         \
00435     else if((__HANDLE__)->Instance == UART4)                  \
00436     {                                                         \
00437       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00438       {                                                       \
00439         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00440           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00441           break;                                              \
00442         case RCC_UART4CLKSOURCE_PLL2:                         \
00443           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00444           break;                                              \
00445         case RCC_UART4CLKSOURCE_PLL3:                         \
00446           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00447           break;                                              \
00448         case RCC_UART4CLKSOURCE_HSI:                          \
00449           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00450           break;                                              \
00451         case RCC_UART4CLKSOURCE_CSI:                          \
00452           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00453           break;                                              \
00454         case RCC_UART4CLKSOURCE_LSE:                          \
00455           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00456           break;                                              \
00457         default:                                              \
00458           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00459           break;                                              \
00460       }                                                       \
00461     }                                                         \
00462     else if ((__HANDLE__)->Instance == UART5)                 \
00463     {                                                         \
00464       switch(__HAL_RCC_GET_UART5_SOURCE())                    \
00465       {                                                       \
00466         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00467           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00468           break;                                              \
00469         case RCC_UART5CLKSOURCE_PLL2:                         \
00470           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00471           break;                                              \
00472         case RCC_UART5CLKSOURCE_PLL3:                         \
00473           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00474           break;                                              \
00475         case RCC_UART5CLKSOURCE_HSI:                          \
00476           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00477           break;                                              \
00478         case RCC_UART5CLKSOURCE_CSI:                          \
00479           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00480           break;                                              \
00481         case RCC_UART5CLKSOURCE_LSE:                          \
00482           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00483           break;                                              \
00484         default:                                              \
00485           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00486           break;                                              \
00487       }                                                       \
00488     }                                                         \
00489     else if((__HANDLE__)->Instance == USART6)                 \
00490     {                                                         \
00491       switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00492       {                                                       \
00493         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00494           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00495           break;                                              \
00496         case RCC_USART6CLKSOURCE_PLL2:                        \
00497           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00498           break;                                              \
00499         case RCC_USART6CLKSOURCE_PLL3:                        \
00500           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00501           break;                                              \
00502         case RCC_USART6CLKSOURCE_HSI:                         \
00503           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00504           break;                                              \
00505         case RCC_USART6CLKSOURCE_CSI:                         \
00506           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00507           break;                                              \
00508         case RCC_USART6CLKSOURCE_LSE:                         \
00509           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00510           break;                                              \
00511         default:                                              \
00512           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00513           break;                                              \
00514       }                                                       \
00515     }                                                         \
00516     else if((__HANDLE__)->Instance == UART7)                  \
00517     {                                                         \
00518       switch(__HAL_RCC_GET_UART7_SOURCE())                    \
00519       {                                                       \
00520         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00521           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00522           break;                                              \
00523         case RCC_UART7CLKSOURCE_PLL2:                         \
00524           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00525           break;                                              \
00526         case RCC_UART7CLKSOURCE_PLL3:                         \
00527           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00528           break;                                              \
00529         case RCC_UART7CLKSOURCE_HSI:                          \
00530           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00531           break;                                              \
00532         case RCC_UART7CLKSOURCE_CSI:                          \
00533           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00534           break;                                              \
00535         case RCC_UART7CLKSOURCE_LSE:                          \
00536           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00537           break;                                              \
00538         default:                                              \
00539           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00540           break;                                              \
00541       }                                                       \
00542     }                                                         \
00543     else if((__HANDLE__)->Instance == UART8)                  \
00544     {                                                         \
00545       switch(__HAL_RCC_GET_UART8_SOURCE())                    \
00546       {                                                       \
00547         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00548           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00549           break;                                              \
00550         case RCC_UART8CLKSOURCE_PLL2:                         \
00551           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00552           break;                                              \
00553         case RCC_UART8CLKSOURCE_PLL3:                         \
00554           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00555           break;                                              \
00556         case RCC_UART8CLKSOURCE_HSI:                          \
00557           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00558           break;                                              \
00559         case RCC_UART8CLKSOURCE_CSI:                          \
00560           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00561           break;                                              \
00562         case RCC_UART8CLKSOURCE_LSE:                          \
00563           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00564           break;                                              \
00565         default:                                              \
00566           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00567           break;                                              \
00568       }                                                       \
00569     }                                                         \
00570     else                                                      \
00571     {                                                         \
00572       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00573     }                                                         \
00574   } while(0U)
00575 #endif /* UART9 && USART10 */
00576
00577 /** @brief  Compute the mask to apply to retrieve the received data
00578   *         according to the word length and to the parity bits activation.
00579   * @param  __HANDLE__ specifies the IRDA Handle.
00580   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00581   */
00582 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00583   do {                                                                \
00584     if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
00585     {                                                                 \
00586       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00587       {                                                               \
00588         (__HANDLE__)->Mask = 0x01FFU ;                                \
00589       }                                                               \
00590       else                                                            \
00591       {                                                               \
00592         (__HANDLE__)->Mask = 0x00FFU ;                                \
00593       }                                                               \
00594     }                                                                 \
00595     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
00596     {                                                                 \
00597       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00598       {                                                               \
00599         (__HANDLE__)->Mask = 0x00FFU ;                                \
00600       }                                                               \
00601       else                                                            \
00602       {                                                               \
00603         (__HANDLE__)->Mask = 0x007FU ;                                \
00604       }                                                               \
00605     }                                                                 \
00606     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
00607     {                                                                 \
00608       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00609       {                                                               \
00610         (__HANDLE__)->Mask = 0x007FU ;                                \
00611       }                                                               \
00612       else                                                            \
00613       {                                                               \
00614         (__HANDLE__)->Mask = 0x003FU ;                                \
00615       }                                                               \
00616     }                                                                 \
00617     else                                                              \
00618     {                                                                 \
00619       (__HANDLE__)->Mask = 0x0000U;                                   \
00620     }                                                                 \
00621   } while(0U)
00622
00623 /** @brief Ensure that IRDA frame length is valid.
00624   * @param __LENGTH__ IRDA frame length.
00625   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00626   */
00627 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00628                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00629                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00630 /**
00631   * @}
00632   */
00633
00634 /* Exported functions --------------------------------------------------------*/
00635
00636 /**
00637   * @}
00638   */
00639
00640 /**
00641   * @}
00642   */
00643
00644 #ifdef __cplusplus
00645 }
00646 #endif
00647
00648 #endif /* STM32H7xx_HAL_IRDA_EX_H */
00649
00650 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_iwdg.c Source File

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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @brief   IWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00008   *           + Initialization and Start functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### IWDG Generic features #####
00014   ==============================================================================
00015   [..]
00016     (+) The IWDG can be started by either software or hardware (configurable
00017         through option byte).
00018
00019     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00020         if the main clock fails.
00021
00022     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00023         disabled. The counter starts counting down from the reset value (0xFFF).
00024         When it reaches the end of count value (0x000) a reset signal is
00025         generated (IWDG reset).
00026
00027     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00028         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00029         prevented.
00030
00031     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00032         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00033         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00034         reset occurs.
00035
00036     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00037         the IWDG counter either continues to work normally or stops, depending
00038         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00039         __HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
00040         __HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.
00041
00042     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00043          The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
00044          devices provide the capability to measure the LSI frequency (LSI clock
00045          connected internally to TIM16 CH1 input capture). The measured value
00046          can be used to have an IWDG timeout with an acceptable accuracy.
00047
00048                      ##### How to use this driver #####
00049   ==============================================================================
00050   [..]
00051     (#) Use IWDG using HAL_IWDG_Init() function to :
00052       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00053            clock is forced ON and IWDG counter starts counting down.
00054       (++) Enable write access to configuration registers:
00055           IWDG_PR, IWDG_RLR and IWDG_WINR.
00056       (++) Configure the IWDG prescaler and counter reload value. This reload
00057            value will be loaded in the IWDG counter each time the watchdog is
00058            reloaded, then the IWDG will start counting down from this value.
00059       (++) Wait for status flags to be reset.
00060       (++) Depending on window parameter:
00061         (+++) If Window Init parameter is same as Window register value,
00062              nothing more is done but reload counter value in order to exit
00063              function with exact time base.
00064         (+++) Else modify Window register. This will automatically reload
00065              watchdog counter.
00066
00067     (#) Then the application program must refresh the IWDG counter at regular
00068         intervals during normal operation to prevent an MCU reset, using
00069         HAL_IWDG_Refresh() function.
00070
00071      *** IWDG HAL driver macros list ***
00072      ====================================
00073      [..]
00074        Below the list of most used macros in IWDG HAL driver:
00075       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00076       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00077           the reload register
00078
00079   @endverbatim
00080   ******************************************************************************
00081   * @attention
00082   *
00083   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00084   * All rights reserved.</center></h2>
00085   *
00086   * This software component is licensed by ST under BSD 3-Clause license,
00087   * the "License"; You may not use this file except in compliance with the
00088   * License. You may obtain a copy of the License at:
00089   *                        opensource.org/licenses/BSD-3-Clause
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32h7xx_hal.h"
00096
00097 /** @addtogroup STM32H7xx_HAL_Driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_IWDG_MODULE_ENABLED
00102 /** @addtogroup IWDG
00103   * @brief IWDG HAL module driver.
00104   * @{
00105   */
00106
00107 /* Private typedef -----------------------------------------------------------*/
00108 /* Private define ------------------------------------------------------------*/
00109 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00110   * @{
00111   */
00112 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00113    higher prescaler (256), and according to LSI variation, we need to wait at
00114    least 6 cycles so 48 ms. */
00115 #define HAL_IWDG_DEFAULT_TIMEOUT            48u
00116 /**
00117   * @}
00118   */
00119
00120 /* Private macro -------------------------------------------------------------*/
00121 /* Private variables ---------------------------------------------------------*/
00122 /* Private function prototypes -----------------------------------------------*/
00123 /* Exported functions --------------------------------------------------------*/
00124
00125 /** @addtogroup IWDG_Exported_Functions
00126   * @{
00127   */
00128
00129 /** @addtogroup IWDG_Exported_Functions_Group1
00130   *  @brief    Initialization and Start functions.
00131   *
00132 @verbatim
00133  ===============================================================================
00134           ##### Initialization and Start functions #####
00135  ===============================================================================
00136  [..]  This section provides functions allowing to:
00137       (+) Initialize the IWDG according to the specified parameters in the
00138           IWDG_InitTypeDef of associated handle.
00139       (+) Manage Window option.
00140       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00141           is reloaded in order to exit function with correct time base.
00142
00143 @endverbatim
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Initialize the IWDG according to the specified parameters in the
00149   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00150   *         watchdog is refreshed in order to have correct time base.
00151   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00152   *                the configuration information for the specified IWDG module.
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00156 {
00157   uint32_t tickstart;
00158
00159   /* Check the IWDG handle allocation */
00160   if (hiwdg == NULL)
00161   {
00162     return HAL_ERROR;
00163   }
00164
00165   /* Check the parameters */
00166   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00167   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00168   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00169   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00170
00171   /* Enable IWDG. LSI is turned on automatically */
00172   __HAL_IWDG_START(hiwdg);
00173
00174   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00175   0x5555 in KR */
00176   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00177
00178   /* Write to IWDG registers the Prescaler & Reload values to work with */
00179   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00180   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00181
00182   /* Check pending flag, if previous update not done, return timeout */
00183   tickstart = HAL_GetTick();
00184
00185   /* Wait for register to be updated */
00186   while (hiwdg->Instance->SR != 0x00u)
00187   {
00188     if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
00189     {
00190       return HAL_TIMEOUT;
00191     }
00192   }
00193
00194   /* If window parameter is different than current value, modify window
00195   register */
00196   if (hiwdg->Instance->WINR != hiwdg->Init.Window)
00197   {
00198     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00199     even if window feature is disabled, Watchdog will be reloaded by writing
00200     windows register */
00201     hiwdg->Instance->WINR = hiwdg->Init.Window;
00202   }
00203   else
00204   {
00205     /* Reload IWDG counter with value defined in the reload register */
00206     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00207   }
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213 /**
00214   * @}
00215   */
00216
00217
00218 /** @addtogroup IWDG_Exported_Functions_Group2
00219   *  @brief   IO operation functions
00220   *
00221 @verbatim
00222  ===============================================================================
00223                       ##### IO operation functions #####
00224  ===============================================================================
00225  [..]  This section provides functions allowing to:
00226       (+) Refresh the IWDG.
00227
00228 @endverbatim
00229   * @{
00230   */
00231
00232
00233 /**
00234   * @brief  Refresh the IWDG.
00235   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00236   *                the configuration information for the specified IWDG module.
00237   * @retval HAL status
00238   */
00239 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00240 {
00241   /* Reload IWDG counter with value defined in the reload register */
00242   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00243
00244   /* Return function status */
00245   return HAL_OK;
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
00255
00256 #endif /* HAL_IWDG_MODULE_ENABLED */
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_iwdg.h Source File

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  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_IWDG_H
00022 #define STM32H7xx_HAL_IWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup IWDG IWDG
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  IWDG Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00050                             This parameter can be a value of @ref IWDG_Prescaler */
00051
00052   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00053                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00054
00055   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00056                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00057
00058 } IWDG_InitTypeDef;
00059
00060 /**
00061   * @brief  IWDG Handle Structure definition
00062   */
00063 typedef struct
00064 {
00065   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00066
00067   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00068 } IWDG_HandleTypeDef;
00069
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Exported constants --------------------------------------------------------*/
00076 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00077   * @{
00078   */
00079
00080 /** @defgroup IWDG_Prescaler IWDG Prescaler
00081   * @{
00082   */
00083 #define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
00084 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
00085 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
00086 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
00087 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
00088 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
00089 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup IWDG_Window_option IWDG Window option
00096   * @{
00097   */
00098 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00099 /**
00100   * @}
00101   */
00102
00103
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported macros -----------------------------------------------------------*/
00109 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Enable the IWDG peripheral.
00115   * @param  __HANDLE__  IWDG handle
00116   * @retval None
00117   */
00118 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00119
00120 /**
00121   * @brief  Reload IWDG counter with value defined in the reload register
00122   *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
00123   * @param  __HANDLE__  IWDG handle
00124   * @retval None
00125   */
00126 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00134   * @{
00135   */
00136
00137 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00138   * @{
00139   */
00140 /* Initialization/Start functions  ********************************************/
00141 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00147   * @{
00148   */
00149 /* I/O operation functions ****************************************************/
00150 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Private constants ---------------------------------------------------------*/
00160 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  IWDG Key Register BitMask
00166   */
00167 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00168 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00169 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00170 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Private macros ------------------------------------------------------------*/
00177 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00183   * @param  __HANDLE__  IWDG handle
00184   * @retval None
00185   */
00186 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00187
00188 /**
00189   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00190   * @param  __HANDLE__  IWDG handle
00191   * @retval None
00192   */
00193 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00194
00195 /**
00196   * @brief  Check IWDG prescaler value.
00197   * @param  __PRESCALER__  IWDG prescaler value
00198   * @retval None
00199   */
00200 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00201                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00202                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00203                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00204                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00205                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00206                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00207
00208 /**
00209   * @brief  Check IWDG reload value.
00210   * @param  __RELOAD__  IWDG reload value
00211   * @retval None
00212   */
00213 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00214
00215 /**
00216   * @brief  Check IWDG window value.
00217   * @param  __WINDOW__  IWDG window value
00218   * @retval None
00219   */
00220 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00221
00222
00223 /**
00224   * @}
00225   */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235
00236 #ifdef __cplusplus
00237 }
00238 #endif
00239
00240 #endif /* STM32H7xx_HAL_IWDG_H */
00241
00242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_jpeg.c Source File

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stm32h7xx_hal_jpeg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_jpeg.c
00004   * @author  MCD Application Team
00005   * @brief   JPEG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the JPEG encoder/decoder peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + JPEG processing functions encoding and decoding
00010   *           + JPEG decoding Getting Info and encoding configuration setting
00011   *           + JPEG enable/disable header parsing functions (for decoding)
00012   *           + JPEG Input/Output Buffer configuration.
00013   *           + JPEG callback functions
00014   *           + JPEG Abort/Pause/Resume functions
00015   *           + JPEG custom quantization tables setting functions
00016   *           + IRQ handler management
00017   *           + Peripheral State and Error functions
00018   *
00019   @verbatim
00020   ==============================================================================
00021                      ##### How to use this driver #####
00022   ==============================================================================
00023     [..]
00024      (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
00025          Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.
00026
00027      (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
00028          the encoding parameters (mandatory before calling the encoding function).
00029          the application can change the encoding parameter ImageQuality from
00030          1 to 100 to obtain a more or less quality (visual quality vs the original row image),
00031          and inversely more or less jpg file size.
00032
00033      (#) Note that for decoding operation the JPEG peripheral output data are organized in
00034          YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
00035          ISO/IEC 10918-1 standard.
00036          It is up to the application to transform these YCbCr blocks to RGB data that can be display.
00037
00038          Respectively, for Encoding operation the JPEG peripheral input should be organized
00039          in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
00040          MCU blocks transformation before feeding the JPEG peripheral with data.
00041
00042      (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
00043          a JPEG encoding/decoding operation in polling method (blocking).
00044
00045      (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
00046          a JPEG encoding/decoding operation with Interrupt method (not blocking).
00047
00048      (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
00049          a JPEG encoding/decoding operation with DMA method (not blocking).
00050
00051      (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
00052          is a JPEG decoding to provide the application with JPEG image  parameters.
00053          This callback is asserted when the JPEG peripheral successfully parse the
00054          JPEG header.
00055
00056      (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
00057          operations to inform the application that the input buffer has been
00058          consumed by the peripheral and to ask for a new data chunk if the operation
00059          (encoding/decoding) has not been complete yet.
00060
00061         (++) This CallBack should be implemented in the application side. It should
00062              call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
00063              or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
00064              to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
00065              application to provide a new input data chunk.
00066              Once the application succeed getting new data and if the input has been paused,
00067              the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
00068              input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
00069              If the application has ended feeding the HAL JPEG with input data (no more input data), the application
00070              Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
00071              with the parameter InDataLength set to zero.
00072
00073          (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
00074               to the application to provide the input data (for encoding or decoding) by chunks.
00075               If the new input data chunk is not available (because data should be read from an input file
00076               for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
00077               Once the new input data chunk is available ( read from a file for example), the application
00078               can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
00079               then resume the JPEG HAL input by calling function HAL_JPEG_Resume.
00080
00081          (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
00082               any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.
00083               However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
00084               (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
00085               Transferring the previous chunk buffer to the JPEG peripheral.
00086
00087      (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
00088          has filled the given output buffer with the given size.
00089
00090          (++) This CallBack should be implemented in the application side. It should
00091               call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
00092               with the new output buffer location and size to be used  to store next data chunk.
00093               if the application is not ready to provide the output chunk location then it can
00094               call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT
00095               to inform the JPEG HAL driver that it shall pause output data. Once the application
00096               is ready to receive the new data chunk (output buffer location free or available) it should call
00097               the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
00098               with the new output chunk buffer location and size, then call HAL_JPEG_Resume
00099               to inform the HAL that it shall resume outputting data in the given output buffer.
00100
00101          (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
00102               the application to receive data from the JPEG peripheral by chunks. when a chunk
00103               is received, the application can pause the HAL JPEG output data to be able to process
00104               these received data (YCbCr to RGB conversion in case of decoding or data storage in case
00105               of encoding).
00106
00107          (++) The application can call  functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
00108               any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
00109               However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
00110               (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
00111               Transferring the previous chunk buffer from the JPEG peripheral to the application.
00112
00113      (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
00114          ended the current JPEG encoding operation, and all output data has been transmitted
00115          to the application.
00116
00117      (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
00118          ended the current JPEG decoding operation. and all output data has been transmitted
00119          to the application.
00120
00121      (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
00122          the current operation. the application can call the function HAL_JPEG_GetError()
00123          to retrieve the error codes.
00124
00125      (#) By default the HAL JPEG driver uses the default quantization tables
00126          as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
00127          User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
00128          Note that for decoding the quantization tables are automatically extracted from
00129          the JPEG header.
00130
00131       (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()
00132
00133      *** JPEG HAL driver macros list ***
00134      =============================================
00135      [..]
00136        Below the list of most used macros in JPEG HAL driver.
00137
00138       (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
00139       (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.
00140       (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.
00141       (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.
00142       (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.
00143       (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.
00144       (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.
00145       (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).
00146
00147   *** Callback registration ***
00148   =============================================
00149
00150   The compilation define  USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1
00151   allows the user to configure dynamically the driver callbacks.
00152   Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback()
00153   to register an interrupt callback.
00154
00155   Function HAL_JPEG_RegisterCallback() allows to register following callbacks:
00156     (+) EncodeCpltCallback : callback for end of encoding operation.
00157     (+) DecodeCpltCallback : callback for end of decoding operation.
00158     (+) ErrorCallback      : callback for error detection.
00159     (+) MspInitCallback    : JPEG MspInit.
00160     (+) MspDeInitCallback  : JPEG MspDeInit.
00161   This function takes as parameters the HAL peripheral handle, the Callback ID
00162   and a pointer to the user callback function.
00163
00164   For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
00165   register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(),
00166   HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback().
00167
00168   Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default
00169   weak function.
00170   HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00171   and the Callback ID.
00172   This function allows to reset following callbacks:
00173     (+) EncodeCpltCallback : callback for end of encoding operation.
00174     (+) DecodeCpltCallback : callback for end of decoding operation.
00175     (+) ErrorCallback      : callback for error detection.
00176     (+) MspInitCallback    : JPEG MspInit.
00177     (+) MspDeInitCallback  : JPEG MspDeInit.
00178
00179   For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
00180   unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(),
00181   HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback().
00182
00183   By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET
00184   all callbacks are set to the corresponding weak functions :
00185   examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback().
00186   Exception done for MspInit and MspDeInit functions that are
00187   reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when
00188   these callbacks are null (not registered beforehand).
00189   if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit()
00190   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00191
00192   Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only.
00193   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00194   in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state,
00195   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00196   In that case first register the MspInit/MspDeInit user callbacks
00197   using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit()
00198   or HAL_JPEG_Init() function.
00199
00200   When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or
00201   not defined, the callback registration feature is not available and all callbacks
00202   are set to the corresponding weak functions.
00203
00204   @endverbatim
00205   ******************************************************************************
00206   * @attention
00207   *
00208   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00209   * All rights reserved.</center></h2>
00210   *
00211   * This software component is licensed by ST under BSD 3-Clause license,
00212   * the "License"; You may not use this file except in compliance with the
00213   * License. You may obtain a copy of the License at:
00214   *                        opensource.org/licenses/BSD-3-Clause
00215   *
00216   ******************************************************************************
00217   */
00218
00219 /* Includes ------------------------------------------------------------------*/
00220 #include "stm32h7xx_hal.h"
00221
00222 /** @addtogroup STM32H7xx_HAL_Driver
00223   * @{
00224   */
00225
00226 /** @defgroup JPEG JPEG
00227   * @brief JPEG HAL module driver.
00228   * @{
00229   */
00230
00231 #ifdef HAL_JPEG_MODULE_ENABLED
00232
00233 #if defined (JPEG)
00234
00235 /* Private define ------------------------------------------------------------*/
00236 /** @addtogroup JPEG_Private_Constants
00237   * @{
00238   */
00239 #define JPEG_TIMEOUT_VALUE  ((uint32_t)1000)     /* 1s */
00240 #define JPEG_AC_HUFF_TABLE_SIZE  ((uint32_t)162) /* Huffman AC table size : 162 codes*/
00241 #define JPEG_DC_HUFF_TABLE_SIZE  ((uint32_t)12)  /* Huffman AC table size : 12 codes*/
00242
00243 #define JPEG_FIFO_SIZE ((uint32_t)16U)             /* JPEG Input/Output HW FIFO size in words*/
00244
00245 #define JPEG_FIFO_TH_SIZE ((uint32_t)8U)              /* JPEG Input/Output HW FIFO Threshold in words*/
00246
00247 #define JPEG_INTERRUPT_MASK  ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
00248
00249 #define JPEG_CONTEXT_ENCODE          ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/
00250 #define JPEG_CONTEXT_DECODE          ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/
00251 #define JPEG_CONTEXT_OPERATION_MASK  ((uint32_t)0x00000003) /* JPEG context : operation Mask */
00252
00253 #define JPEG_CONTEXT_POLLING        ((uint32_t)0x00000004)  /* JPEG context : Transfer use Polling */
00254 #define JPEG_CONTEXT_IT             ((uint32_t)0x00000008)  /* JPEG context : Transfer use Interrupt */
00255 #define JPEG_CONTEXT_DMA            ((uint32_t)0x0000000C)  /* JPEG context : Transfer use DMA */
00256 #define JPEG_CONTEXT_METHOD_MASK    ((uint32_t)0x0000000C)  /* JPEG context : Transfer Mask */
00257
00258
00259 #define JPEG_CONTEXT_CONF_ENCODING  ((uint32_t)0x00000100)  /* JPEG context : encoding config done */
00260
00261 #define JPEG_CONTEXT_PAUSE_INPUT    ((uint32_t)0x00001000)  /* JPEG context : Pause Input */
00262 #define JPEG_CONTEXT_PAUSE_OUTPUT   ((uint32_t)0x00002000)  /* JPEG context : Pause Output */
00263
00264 #define JPEG_CONTEXT_CUSTOM_TABLES  ((uint32_t)0x00004000)  /* JPEG context : Use custom quantization tables */
00265
00266 #define JPEG_CONTEXT_ENDING_DMA     ((uint32_t)0x00008000)  /* JPEG context : ending with DMA in progress */
00267
00268 #define JPEG_PROCESS_ONGOING        ((uint32_t)0x00000000)  /* Process is on going */
00269 #define JPEG_PROCESS_DONE           ((uint32_t)0x00000001)  /* Process is done (ends) */
00270 /**
00271   * @}
00272   */
00273
00274 /* Private typedef -----------------------------------------------------------*/
00275 /** @addtogroup JPEG_Private_Types
00276   * @{
00277   */
00278
00279 /*
00280  JPEG Huffman Table Structure definition :
00281  This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification
00282  */
00283 typedef struct
00284 {
00285   /* These two fields directly represent the contents of a JPEG DHT marker */
00286   uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
00287
00288   uint8_t HuffVal[162];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
00289
00290
00291 } JPEG_ACHuffTableTypeDef;
00292
00293 typedef struct
00294 {
00295   /* These two fields directly represent the contents of a JPEG DHT marker */
00296   uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
00297
00298   uint8_t HuffVal[12];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
00299
00300
00301 } JPEG_DCHuffTableTypeDef;
00302
00303 typedef struct
00304 {
00305   uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE];      /*!< Code length  */
00306
00307   uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
00308
00309 } JPEG_AC_HuffCodeTableTypeDef;
00310
00311 typedef struct
00312 {
00313   uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE];        /*!< Code length  */
00314
00315   uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
00316
00317 } JPEG_DC_HuffCodeTableTypeDef;
00318 /**
00319   * @}
00320   */
00321
00322 /* Private macro -------------------------------------------------------------*/
00323
00324 /* Private variables ---------------------------------------------------------*/
00325 /** @addtogroup JPEG_Private_Variables
00326   * @{
00327   */
00328
00329 static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =
00330 {
00331   { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },   /*Bits*/
00332
00333   { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }           /*HUFFVAL */
00334
00335 };
00336
00337 static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =
00338 {
00339   { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },  /*Bits*/
00340
00341   { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }          /*HUFFVAL */
00342 };
00343
00344 static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =
00345 {
00346   { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },  /*Bits*/
00347
00348   {
00349     0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,     /*HUFFVAL */
00350     0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
00351     0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
00352     0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
00353     0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
00354     0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
00355     0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
00356     0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
00357     0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
00358     0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
00359     0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
00360     0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
00361     0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
00362     0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
00363     0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
00364     0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
00365     0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
00366     0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
00367     0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
00368     0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
00369     0xf9, 0xfa
00370   }
00371 };
00372
00373 static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =
00374 {
00375   { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },   /*Bits*/
00376
00377   {
00378     0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,      /*HUFFVAL */
00379     0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
00380     0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
00381     0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
00382     0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
00383     0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
00384     0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
00385     0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
00386     0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
00387     0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
00388     0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
00389     0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
00390     0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
00391     0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
00392     0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
00393     0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
00394     0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
00395     0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
00396     0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
00397     0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
00398     0xf9, 0xfa
00399   }
00400 };
00401
00402 static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
00403 {
00404   0,   1,   8,  16,   9,   2,   3,  10,
00405   17,  24,  32,  25,  18,  11,   4,   5,
00406   12,  19,  26,  33,  40,  48,  41,  34,
00407   27,  20,  13,   6,   7,  14,  21,  28,
00408   35,  42,  49,  56,  57,  50,  43,  36,
00409   29,  22,  15,  23,  30,  37,  44,  51,
00410   58,  59,  52,  45,  38,  31,  39,  46,
00411   53,  60,  61,  54,  47,  55,  62,  63
00412 };
00413 /**
00414   * @}
00415   */
00416
00417 /* Private function prototypes -----------------------------------------------*/
00418 /** @addtogroup JPEG_Private_Functions_Prototypes
00419   * @{
00420   */
00421
00422 static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);
00423 static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
00424                                                            JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
00425 static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
00426                                                            JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
00427 static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
00428                                              const __IO uint32_t *DCTableAddress);
00429 static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
00430                                              const __IO uint32_t *ACTableAddress);
00431 static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg);
00432 static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg);
00433 static uint32_t  JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
00434                                                     __IO uint32_t *QTableAddress);
00435 static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);
00436 static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);
00437 static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);
00438
00439 static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);
00440 static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);
00441 static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);
00442 static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);
00443 static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);
00444
00445 static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
00446 static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
00447 static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
00448 static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
00449 static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma);
00450 static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma);
00451 static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma);
00452 static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma);
00453
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup JPEG_Exported_Functions JPEG Exported Functions
00459   * @{
00460   */
00461
00462 /** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions
00463   *  @brief    Initialization and de-initialization functions.
00464   *
00465 @verbatim
00466   ==============================================================================
00467               ##### Initialization and de-initialization functions #####
00468   ==============================================================================
00469     [..]  This section provides functions allowing to:
00470       (+) Initialize the JPEG peripheral and creates the associated handle
00471       (+) DeInitialize the JPEG peripheral
00472
00473 @endverbatim
00474   * @{
00475   */
00476
00477 /**
00478   * @brief  Initializes the JPEG according to the specified
00479   *         parameters in the JPEG_InitTypeDef and creates the associated handle.
00480   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
00481   *         the configuration information for JPEG module
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
00485 {
00486   /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */
00487   static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
00488   {
00489     16,  11,  10,  16,  24,  40,  51,  61,
00490     12,  12,  14,  19,  26,  58,  60,  55,
00491     14,  13,  16,  24,  40,  57,  69,  56,
00492     14,  17,  22,  29,  51,  87,  80,  62,
00493     18,  22,  37,  56,  68, 109, 103,  77,
00494     24,  35,  55,  64,  81, 104, 113,  92,
00495     49,  64,  78,  87, 103, 121, 120, 101,
00496     72,  92,  95,  98, 112, 100, 103,  99
00497   };
00498   static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
00499   {
00500     17,  18,  24,  47,  99,  99,  99,  99,
00501     18,  21,  26,  66,  99,  99,  99,  99,
00502     24,  26,  56,  99,  99,  99,  99,  99,
00503     47,  66,  99,  99,  99,  99,  99,  99,
00504     99,  99,  99,  99,  99,  99,  99,  99,
00505     99,  99,  99,  99,  99,  99,  99,  99,
00506     99,  99,  99,  99,  99,  99,  99,  99,
00507     99,  99,  99,  99,  99,  99,  99,  99
00508   };
00509
00510   /* Check the JPEG handle allocation */
00511   if (hjpeg == NULL)
00512   {
00513     return HAL_ERROR;
00514   }
00515
00516 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00517   if (hjpeg->State == HAL_JPEG_STATE_RESET)
00518   {
00519     /* Allocate lock resource and initialize it */
00520     hjpeg->Lock = HAL_UNLOCKED;
00521
00522     hjpeg->InfoReadyCallback  = HAL_JPEG_InfoReadyCallback;  /* Legacy weak InfoReadyCallback  */
00523     hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */
00524     hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */
00525     hjpeg->ErrorCallback      = HAL_JPEG_ErrorCallback;      /* Legacy weak ErrorCallback      */
00526     hjpeg->GetDataCallback    = HAL_JPEG_GetDataCallback;    /* Legacy weak GetDataCallback    */
00527     hjpeg->DataReadyCallback  = HAL_JPEG_DataReadyCallback;  /* Legacy weak DataReadyCallback  */
00528
00529     if (hjpeg->MspInitCallback == NULL)
00530     {
00531       hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit  */
00532     }
00533
00534     /* Init the low level hardware */
00535     hjpeg->MspInitCallback(hjpeg);
00536   }
00537 #else
00538   if (hjpeg->State == HAL_JPEG_STATE_RESET)
00539   {
00540     /* Allocate lock resource and initialize it */
00541     hjpeg->Lock = HAL_UNLOCKED;
00542
00543     /* Init the low level hardware : GPIO, CLOCK */
00544     HAL_JPEG_MspInit(hjpeg);
00545   }
00546 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00547
00548   /* Change the JPEG state */
00549   hjpeg->State = HAL_JPEG_STATE_BUSY;
00550
00551   /* Start the JPEG Core*/
00552   __HAL_JPEG_ENABLE(hjpeg);
00553
00554   /* Stop the JPEG encoding/decoding process*/
00555   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
00556
00557   /* Disable All Interrupts */
00558   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
00559
00560
00561   /* Flush input and output FIFOs*/
00562   hjpeg->Instance->CR |= JPEG_CR_IFF;
00563   hjpeg->Instance->CR |= JPEG_CR_OFF;
00564
00565   /* Clear all flags */
00566   __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
00567
00568   /* init default quantization tables*/
00569   hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable);
00570   hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable);
00571   hjpeg->QuantTable2 = NULL;
00572   hjpeg->QuantTable3 = NULL;
00573
00574   /* init the default Huffman tables*/
00575   if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK)
00576   {
00577     hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;
00578
00579     return HAL_ERROR;
00580   }
00581
00582   /* Enable header processing*/
00583   hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
00584
00585   /* Reset JpegInCount and JpegOutCount */
00586   hjpeg->JpegInCount = 0;
00587   hjpeg->JpegOutCount = 0;
00588
00589   /* Change the JPEG state */
00590   hjpeg->State = HAL_JPEG_STATE_READY;
00591
00592   /* Reset the JPEG ErrorCode */
00593   hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
00594
00595   /*Clear the context filelds*/
00596   hjpeg->Context = 0;
00597
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601
00602 /**
00603   * @brief  DeInitializes the JPEG peripheral.
00604   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
00605   *         the configuration information for JPEG module
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)
00609 {
00610   /* Check the JPEG handle allocation */
00611   if (hjpeg == NULL)
00612   {
00613     return HAL_ERROR;
00614   }
00615
00616 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00617   if (hjpeg->MspDeInitCallback == NULL)
00618   {
00619     hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit  */
00620   }
00621
00622   /* DeInit the low level hardware */
00623   hjpeg->MspDeInitCallback(hjpeg);
00624
00625 #else
00626   /* DeInit the low level hardware: CLOCK, NVIC.*/
00627   HAL_JPEG_MspDeInit(hjpeg);
00628 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00629
00630   /* Change the JPEG state */
00631   hjpeg->State = HAL_JPEG_STATE_BUSY;
00632
00633   /* Reset the JPEG ErrorCode */
00634   hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
00635
00636   /* Reset JpegInCount and JpegOutCount */
00637   hjpeg->JpegInCount = 0;
00638   hjpeg->JpegOutCount = 0;
00639
00640   /* Change the JPEG state */
00641   hjpeg->State = HAL_JPEG_STATE_RESET;
00642
00643   /*Clear the context fields*/
00644   hjpeg->Context = 0;
00645
00646   /* Release Lock */
00647   __HAL_UNLOCK(hjpeg);
00648
00649   /* Return function status */
00650   return HAL_OK;
00651 }
00652
00653 /**
00654   * @brief  Initializes the JPEG MSP.
00655   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
00656   *         the configuration information for JPEG module
00657   * @retval None
00658   */
00659 __weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)
00660 {
00661   /* Prevent unused argument(s) compilation warning */
00662   UNUSED(hjpeg);
00663
00664   /* NOTE : This function Should not be modified, when the callback is needed,
00665             the HAL_JPEG_MspInit could be implemented in the user file
00666    */
00667 }
00668
00669 /**
00670   * @brief  DeInitializes JPEG MSP.
00671   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
00672   *         the configuration information for JPEG module
00673   * @retval None
00674   */
00675 __weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
00676 {
00677   /* Prevent unused argument(s) compilation warning */
00678   UNUSED(hjpeg);
00679
00680   /* NOTE : This function Should not be modified, when the callback is needed,
00681             the HAL_JPEG_MspDeInit could be implemented in the user file
00682    */
00683 }
00684
00685 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00686 /**
00687   * @brief  Register a User JPEG Callback
00688   *         To be used instead of the weak predefined callback
00689   * @param  hjpeg JPEG handle
00690   * @param  CallbackID ID of the callback to be registered
00691   *         This parameter can be one of the following values:
00692   *          @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
00693   *          @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
00694   *          @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
00695   *          @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
00696   *          @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
00697   * @param  pCallback pointer to the Callback function
00698   * @retval HAL status
00699   */
00700 HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
00701                                             pJPEG_CallbackTypeDef pCallback)
00702 {
00703   HAL_StatusTypeDef status = HAL_OK;
00704
00705   if (pCallback == NULL)
00706   {
00707     /* Update the error code */
00708     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00709     return HAL_ERROR;
00710   }
00711   /* Process locked */
00712   __HAL_LOCK(hjpeg);
00713
00714   if (HAL_JPEG_STATE_READY == hjpeg->State)
00715   {
00716     switch (CallbackID)
00717     {
00718       case HAL_JPEG_ENCODE_CPLT_CB_ID :
00719         hjpeg->EncodeCpltCallback = pCallback;
00720         break;
00721
00722       case HAL_JPEG_DECODE_CPLT_CB_ID :
00723         hjpeg->DecodeCpltCallback = pCallback;
00724         break;
00725
00726       case HAL_JPEG_ERROR_CB_ID :
00727         hjpeg->ErrorCallback = pCallback;
00728         break;
00729
00730       case HAL_JPEG_MSPINIT_CB_ID :
00731         hjpeg->MspInitCallback = pCallback;
00732         break;
00733
00734       case HAL_JPEG_MSPDEINIT_CB_ID :
00735         hjpeg->MspDeInitCallback = pCallback;
00736         break;
00737
00738       default :
00739         /* Update the error code */
00740         hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00741         /* Return error status */
00742         status =  HAL_ERROR;
00743         break;
00744     }
00745   }
00746   else if (HAL_JPEG_STATE_RESET == hjpeg->State)
00747   {
00748     switch (CallbackID)
00749     {
00750       case HAL_JPEG_MSPINIT_CB_ID :
00751         hjpeg->MspInitCallback = pCallback;
00752         break;
00753
00754       case HAL_JPEG_MSPDEINIT_CB_ID :
00755         hjpeg->MspDeInitCallback = pCallback;
00756         break;
00757
00758       default :
00759         /* Update the error code */
00760         hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00761         /* Return error status */
00762         status =  HAL_ERROR;
00763         break;
00764     }
00765   }
00766   else
00767   {
00768     /* Update the error code */
00769     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00770     /* Return error status */
00771     status =  HAL_ERROR;
00772   }
00773
00774   /* Release Lock */
00775   __HAL_UNLOCK(hjpeg);
00776   return status;
00777 }
00778
00779 /**
00780   * @brief  Unregister a JPEG Callback
00781   *         JPEG callabck is redirected to the weak predefined callback
00782   * @param  hjpeg JPEG handle
00783   * @param  CallbackID ID of the callback to be unregistered
00784   *         This parameter can be one of the following values:
00785   *         This parameter can be one of the following values:
00786   *          @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
00787   *          @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
00788   *          @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
00789   *          @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
00790   *          @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
00794 {
00795   HAL_StatusTypeDef status = HAL_OK;
00796
00797   /* Process locked */
00798   __HAL_LOCK(hjpeg);
00799
00800   if (HAL_JPEG_STATE_READY == hjpeg->State)
00801   {
00802     switch (CallbackID)
00803     {
00804       case HAL_JPEG_ENCODE_CPLT_CB_ID :
00805         hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback  */
00806         break;
00807
00808       case HAL_JPEG_DECODE_CPLT_CB_ID :
00809         hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback  */
00810         break;
00811
00812       case HAL_JPEG_ERROR_CB_ID :
00813         hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback;           /* Legacy weak ErrorCallback  */
00814         break;
00815
00816       case HAL_JPEG_MSPINIT_CB_ID :
00817         hjpeg->MspInitCallback = HAL_JPEG_MspInit;              /* Legacy weak MspInit  */
00818         break;
00819
00820       case HAL_JPEG_MSPDEINIT_CB_ID :
00821         hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit;          /* Legacy weak MspDeInit  */
00822         break;
00823
00824       default :
00825         /* Update the error code */
00826         hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00827         /* Return error status */
00828         status =  HAL_ERROR;
00829         break;
00830     }
00831   }
00832   else if (HAL_JPEG_STATE_RESET == hjpeg->State)
00833   {
00834     switch (CallbackID)
00835     {
00836       case HAL_JPEG_MSPINIT_CB_ID :
00837         hjpeg->MspInitCallback = HAL_JPEG_MspInit;           /* Legacy weak MspInit  */
00838         break;
00839
00840       case HAL_JPEG_MSPDEINIT_CB_ID :
00841         hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit;       /* Legacy weak MspInit  */
00842         break;
00843
00844       default :
00845         /* Update the error code */
00846         hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00847         /* Return error status */
00848         status =  HAL_ERROR;
00849         break;
00850     }
00851   }
00852   else
00853   {
00854     /* Update the error code */
00855     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00856     /* Return error status */
00857     status =  HAL_ERROR;
00858   }
00859
00860   /* Release Lock */
00861   __HAL_UNLOCK(hjpeg);
00862   return status;
00863 }
00864
00865 /**
00866   * @brief  Register Info Ready JPEG Callback
00867   *         To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback
00868   * @param  hjpeg JPEG handle
00869   * @param  pCallback pointer to the Info Ready Callback function
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
00873                                                      pJPEG_InfoReadyCallbackTypeDef pCallback)
00874 {
00875   HAL_StatusTypeDef status = HAL_OK;
00876
00877   if (pCallback == NULL)
00878   {
00879     /* Update the error code */
00880     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00881     return HAL_ERROR;
00882   }
00883   /* Process locked */
00884   __HAL_LOCK(hjpeg);
00885
00886   if (HAL_JPEG_STATE_READY == hjpeg->State)
00887   {
00888     hjpeg->InfoReadyCallback = pCallback;
00889   }
00890   else
00891   {
00892     /* Update the error code */
00893     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00894     /* Return error status */
00895     status =  HAL_ERROR;
00896   }
00897
00898   /* Release Lock */
00899   __HAL_UNLOCK(hjpeg);
00900   return status;
00901 }
00902
00903 /**
00904   * @brief  UnRegister the Info Ready JPEG Callback
00905   *         Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback
00906   * @param  hjpeg JPEG handle
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg)
00910 {
00911   HAL_StatusTypeDef status = HAL_OK;
00912
00913   /* Process locked */
00914   __HAL_LOCK(hjpeg);
00915
00916   if (HAL_JPEG_STATE_READY == hjpeg->State)
00917   {
00918     hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback  */
00919   }
00920   else
00921   {
00922     /* Update the error code */
00923     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00924     /* Return error status */
00925     status =  HAL_ERROR;
00926   }
00927
00928   /* Release Lock */
00929   __HAL_UNLOCK(hjpeg);
00930   return status;
00931 }
00932
00933 /**
00934   * @brief  Register Get Data JPEG Callback
00935   *         To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback
00936   * @param  hjpeg JPEG handle
00937   * @param  pCallback pointer to the Get Data Callback function
00938   * @retval HAL status
00939   */
00940 HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
00941 {
00942   HAL_StatusTypeDef status = HAL_OK;
00943
00944   if (pCallback == NULL)
00945   {
00946     /* Update the error code */
00947     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00948     return HAL_ERROR;
00949   }
00950   /* Process locked */
00951   __HAL_LOCK(hjpeg);
00952
00953   if (HAL_JPEG_STATE_READY == hjpeg->State)
00954   {
00955     hjpeg->GetDataCallback = pCallback;
00956   }
00957   else
00958   {
00959     /* Update the error code */
00960     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00961     /* Return error status */
00962     status =  HAL_ERROR;
00963   }
00964
00965   /* Release Lock */
00966   __HAL_UNLOCK(hjpeg);
00967   return status;
00968 }
00969
00970 /**
00971   * @brief  UnRegister the Get Data JPEG Callback
00972   *         Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback
00973   * @param  hjpeg JPEG handle
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg)
00977 {
00978   HAL_StatusTypeDef status = HAL_OK;
00979
00980   /* Process locked */
00981   __HAL_LOCK(hjpeg);
00982
00983   if (HAL_JPEG_STATE_READY == hjpeg->State)
00984   {
00985     hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback;  /* Legacy weak GetDataCallback  */
00986   }
00987   else
00988   {
00989     /* Update the error code */
00990     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
00991     /* Return error status */
00992     status =  HAL_ERROR;
00993   }
00994
00995   /* Release Lock */
00996   __HAL_UNLOCK(hjpeg);
00997   return status;
00998 }
00999
01000 /**
01001   * @brief  Register Data Ready JPEG Callback
01002   *         To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback
01003   * @param  hjpeg JPEG handle
01004   * @param  pCallback pointer to the Get Data Callback function
01005   * @retval HAL status
01006   */
01007 HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
01008                                                      pJPEG_DataReadyCallbackTypeDef pCallback)
01009 {
01010   HAL_StatusTypeDef status = HAL_OK;
01011
01012   if (pCallback == NULL)
01013   {
01014     /* Update the error code */
01015     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
01016     return HAL_ERROR;
01017   }
01018   /* Process locked */
01019   __HAL_LOCK(hjpeg);
01020
01021   if (HAL_JPEG_STATE_READY == hjpeg->State)
01022   {
01023     hjpeg->DataReadyCallback = pCallback;
01024   }
01025   else
01026   {
01027     /* Update the error code */
01028     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
01029     /* Return error status */
01030     status =  HAL_ERROR;
01031   }
01032
01033   /* Release Lock */
01034   __HAL_UNLOCK(hjpeg);
01035   return status;
01036 }
01037
01038 /**
01039   * @brief  UnRegister the Data Ready JPEG Callback
01040   *         Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback
01041   * @param  hjpeg JPEG handle
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg)
01045 {
01046   HAL_StatusTypeDef status = HAL_OK;
01047
01048   /* Process locked */
01049   __HAL_LOCK(hjpeg);
01050
01051   if (HAL_JPEG_STATE_READY == hjpeg->State)
01052   {
01053     hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback;  /* Legacy weak DataReadyCallback  */
01054   }
01055   else
01056   {
01057     /* Update the error code */
01058     hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
01059     /* Return error status */
01060     status =  HAL_ERROR;
01061   }
01062
01063   /* Release Lock */
01064   __HAL_UNLOCK(hjpeg);
01065   return status;
01066 }
01067
01068 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
01069
01070 /**
01071   * @}
01072   */
01073
01074 /** @defgroup JPEG_Exported_Functions_Group2 Configuration functions
01075   *  @brief    JPEG Configuration functions.
01076   *
01077 @verbatim
01078   ==============================================================================
01079               ##### Configuration functions #####
01080   ==============================================================================
01081     [..]  This section provides functions allowing to:
01082       (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
01083       (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding
01084       (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding
01085       (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
01086       (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.
01087
01088 @endverbatim
01089   * @{
01090   */
01091
01092 /**
01093   * @brief  Set the JPEG encoding configuration.
01094   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01095   *         the configuration information for JPEG module
01096   * @param  pConf pointer to a JPEG_ConfTypeDef structure that contains
01097   *         the encoding configuration
01098   * @retval HAL status
01099   */
01100 HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
01101 {
01102   uint32_t error;
01103   uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
01104
01105   /* Check the JPEG handle allocation */
01106   if ((hjpeg == NULL) || (pConf == NULL))
01107   {
01108     return HAL_ERROR;
01109   }
01110   else
01111   {
01112     /* Check the parameters */
01113     assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));
01114     assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));
01115     assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));
01116
01117     /* Process Locked */
01118     __HAL_LOCK(hjpeg);
01119
01120     if (hjpeg->State == HAL_JPEG_STATE_READY)
01121     {
01122       hjpeg->State = HAL_JPEG_STATE_BUSY;
01123
01124       hjpeg->Conf.ColorSpace          =  pConf->ColorSpace;
01125       hjpeg->Conf.ChromaSubsampling   =  pConf->ChromaSubsampling;
01126       hjpeg->Conf.ImageHeight         =  pConf->ImageHeight;
01127       hjpeg->Conf.ImageWidth          =  pConf->ImageWidth;
01128       hjpeg->Conf.ImageQuality        =  pConf->ImageQuality;
01129
01130       /* Reset the Color Space : by default only one quantization table is used*/
01131       hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;
01132
01133       /* Set Number of color components*/
01134       if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
01135       {
01136         /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/
01137         hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;
01138
01139         JPEG_SetColorGrayScale(hjpeg);
01140         /* Set quantization table 0*/
01141         error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
01142       }
01143       else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
01144       {
01145         /*
01146            Set the Color Space for YCbCr : 2 quantization tables are used
01147            one for Luminance(Y) and one for both Chrominances (Cb & Cr)
01148           */
01149         hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;
01150
01151         JPEG_SetColorYCBCR(hjpeg);
01152
01153         /* Set quantization table 0*/
01154         error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
01155         /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/
01156         error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
01157
01158         if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
01159         {
01160           /*Use user customized quantization tables , 1 table per component*/
01161           /* use 3 quantization tables , one for each component*/
01162           hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);
01163           hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;
01164
01165           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
01166
01167           /*Use Quantization 1 table for component 1*/
01168           hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
01169           hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
01170
01171           /*Use Quantization 2 table for component 2*/
01172           hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);
01173           hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
01174         }
01175       }
01176       else /* ColorSpace == JPEG_CMYK_COLORSPACE */
01177       {
01178         JPEG_SetColorCMYK(hjpeg);
01179
01180         /* Set quantization table 0*/
01181         error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
01182         /*By default quantization table 0 for All components*/
01183
01184         if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
01185         {
01186           /*Use user customized quantization tables , 1 table per component*/
01187           /* use 4 quantization tables , one for each component*/
01188           hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;
01189
01190           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
01191           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
01192           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3));
01193
01194           /*Use Quantization 1 table for component 1*/
01195           hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
01196
01197           /*Use Quantization 2 table for component 2*/
01198           hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
01199
01200           /*Use Quantization 3 table for component 3*/
01201           hjpeg->Instance->CONFR7 |=  JPEG_CONFR7_QT;
01202         }
01203       }
01204
01205       if (error != 0UL)
01206       {
01207         hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;
01208
01209         /* Process Unlocked */
01210         __HAL_UNLOCK(hjpeg);
01211
01212         /* Set the JPEG State to ready */
01213         hjpeg->State = HAL_JPEG_STATE_READY;
01214
01215         return  HAL_ERROR;
01216       }
01217       /* Set the image size*/
01218       /* set the number of lines*/
01219       MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16));
01220       /* set the number of pixels per line*/
01221       MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16));
01222
01223
01224       if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
01225       {
01226         hfactor = 16;
01227         vfactor = 16;
01228       }
01229       else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
01230       {
01231         hfactor = 16;
01232         vfactor = 8;
01233       }
01234       else /* Default is 8x8 MCU,  4:4:4*/
01235       {
01236         hfactor = 8;
01237         vfactor = 8;
01238       }
01239
01240       hMCU = (hjpeg->Conf.ImageWidth / hfactor);
01241       if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL)
01242       {
01243         hMCU++; /*+1 for horizontal incomplete MCU */
01244       }
01245
01246       vMCU = (hjpeg->Conf.ImageHeight / vfactor);
01247       if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL)
01248       {
01249         vMCU++; /*+1 for vertical incomplete MCU */
01250       }
01251
01252       numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
01253       /* Set the number of MCU*/
01254       hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);
01255
01256       hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;
01257
01258       /* Process Unlocked */
01259       __HAL_UNLOCK(hjpeg);
01260
01261       /* Set the JPEG State to ready */
01262       hjpeg->State = HAL_JPEG_STATE_READY;
01263
01264       /* Return function status */
01265       return HAL_OK;
01266     }
01267     else
01268     {
01269       /* Process Unlocked */
01270       __HAL_UNLOCK(hjpeg);
01271
01272       /* Return function status */
01273       return HAL_BUSY;
01274     }
01275   }
01276 }
01277
01278 /**
01279   * @brief  Extract the image configuration from the JPEG header during the decoding
01280   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01281   *         the configuration information for JPEG module
01282   * @param  pInfo pointer to a JPEG_ConfTypeDef structure that contains
01283   *         The JPEG decoded header informations
01284   * @retval HAL status
01285   */
01286 HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
01287 {
01288   uint32_t yblockNb, cBblockNb, cRblockNb;
01289
01290   /* Check the JPEG handle allocation */
01291   if ((hjpeg == NULL) || (pInfo == NULL))
01292   {
01293     return HAL_ERROR;
01294   }
01295
01296   /*Read the conf parameters */
01297   if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
01298   {
01299     pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;
01300   }
01301   else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL)
01302   {
01303     pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;
01304   }
01305   else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
01306   {
01307     pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;
01308   }
01309   else
01310   {
01311     return HAL_ERROR;
01312   }
01313
01314   pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16;
01315   pInfo->ImageWidth  = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16;
01316
01317   if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
01318   {
01319     yblockNb  = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;
01320     cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;
01321     cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;
01322
01323     if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
01324     {
01325       pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/
01326     }
01327     else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
01328     {
01329       pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
01330     }
01331     else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
01332     {
01333       pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;
01334     }
01335     else /*Default is 4:4:4*/
01336     {
01337       pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
01338     }
01339   }
01340   else
01341   {
01342     pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
01343   }
01344
01345   pInfo->ImageQuality = JPEG_GetQuality(hjpeg);
01346
01347   /* Return function status */
01348   return HAL_OK;
01349 }
01350
01351 /**
01352   * @brief  Enable JPEG Header parsing for decoding
01353   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01354   *               the configuration information for the JPEG.
01355   * @retval HAL status
01356   */
01357 HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
01358 {
01359   /* Process locked */
01360   __HAL_LOCK(hjpeg);
01361
01362   if (hjpeg->State == HAL_JPEG_STATE_READY)
01363   {
01364     /* Change the JPEG state */
01365     hjpeg->State = HAL_JPEG_STATE_BUSY;
01366
01367     /* Enable header processing*/
01368     hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
01369
01370     /* Process unlocked */
01371     __HAL_UNLOCK(hjpeg);
01372
01373     /* Change the JPEG state */
01374     hjpeg->State = HAL_JPEG_STATE_READY;
01375
01376     return HAL_OK;
01377   }
01378   else
01379   {
01380     /* Process unlocked */
01381     __HAL_UNLOCK(hjpeg);
01382
01383     return HAL_BUSY;
01384   }
01385 }
01386
01387 /**
01388   * @brief  Disable JPEG Header parsing for decoding
01389   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01390   *               the configuration information for the JPEG.
01391   * @retval HAL status
01392   */
01393 HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
01394 {
01395   /* Process locked */
01396   __HAL_LOCK(hjpeg);
01397
01398   if (hjpeg->State == HAL_JPEG_STATE_READY)
01399   {
01400     /* Change the JPEG state */
01401     hjpeg->State = HAL_JPEG_STATE_BUSY;
01402
01403     /* Disable header processing*/
01404     hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;
01405
01406     /* Process unlocked */
01407     __HAL_UNLOCK(hjpeg);
01408
01409     /* Change the JPEG state */
01410     hjpeg->State = HAL_JPEG_STATE_READY;
01411
01412     return HAL_OK;
01413   }
01414   else
01415   {
01416     /* Process unlocked */
01417     __HAL_UNLOCK(hjpeg);
01418
01419     return HAL_BUSY;
01420   }
01421 }
01422
01423 /**
01424   * @brief  Modify the default Quantization tables used for JPEG encoding.
01425   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01426   *         the configuration information for JPEG module
01427   * @param  QTable0  pointer to uint8_t , define the user quantification table for color component 1.
01428   *                  If NULL assume no need to update  the table and no error return
01429   * @param  QTable1  pointer to uint8_t , define the user quantification table for color component 2.
01430   *                  If NULL assume no need to update  the table and no error return.
01431   * @param  QTable2  pointer to uint8_t , define the user quantification table for color component 3,
01432   *                  If NULL assume no need to update  the table and no error return.
01433   * @param  QTable3  pointer to uint8_t , define the user quantification table for color component 4.
01434   *                  If NULL assume no need to update  the table and no error return.
01435   *
01436   * @retval HAL status
01437   */
01438
01439
01440 HAL_StatusTypeDef  HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
01441                                                uint8_t *QTable2, uint8_t *QTable3)
01442 {
01443   /* Process Locked */
01444   __HAL_LOCK(hjpeg);
01445
01446   if (hjpeg->State == HAL_JPEG_STATE_READY)
01447   {
01448     /* Change the DMA state */
01449     hjpeg->State = HAL_JPEG_STATE_BUSY;
01450
01451     hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;
01452
01453     hjpeg->QuantTable0 = QTable0;
01454     hjpeg->QuantTable1 = QTable1;
01455     hjpeg->QuantTable2 = QTable2;
01456     hjpeg->QuantTable3 = QTable3;
01457
01458     /* Process Unlocked */
01459     __HAL_UNLOCK(hjpeg);
01460
01461     /* Change the DMA state */
01462     hjpeg->State = HAL_JPEG_STATE_READY;
01463
01464     /* Return function status */
01465     return HAL_OK;
01466   }
01467   else
01468   {
01469     /* Process Unlocked */
01470     __HAL_UNLOCK(hjpeg);
01471
01472     return HAL_BUSY;
01473   }
01474 }
01475
01476 /**
01477   * @}
01478   */
01479
01480 /** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions
01481   *  @brief   processing functions.
01482   *
01483 @verbatim
01484   ==============================================================================
01485                       ##### JPEG processing functions #####
01486   ==============================================================================
01487     [..]  This section provides functions allowing to:
01488       (+) HAL_JPEG_Encode()     : JPEG encoding with polling process
01489       (+) HAL_JPEG_Decode()     : JPEG decoding with polling process
01490       (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process
01491       (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process
01492       (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
01493       (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
01494       (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing
01495       (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing
01496       (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer
01497       (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
01498       (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding
01499
01500 @endverbatim
01501   * @{
01502   */
01503
01504 /**
01505   * @brief  Starts JPEG encoding with polling processing
01506   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01507   *         the configuration information for JPEG module
01508   * @param  pDataInMCU Pointer to the Input buffer
01509   * @param  InDataLength size in bytes Input buffer
01510   * @param  pDataOut Pointer to the jpeg output data buffer
01511   * @param  OutDataLength size in bytes of the Output buffer
01512   * @param  Timeout Specify Timeout value
01513   * @retval HAL status
01514   */
01515 HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
01516                                    uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
01517 {
01518   uint32_t tickstart;
01519
01520   /* Check the parameters */
01521   assert_param((InDataLength >= 4UL));
01522   assert_param((OutDataLength >= 4UL));
01523
01524   /* Check In/out buffer allocation and size */
01525   if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01526   {
01527     return HAL_ERROR;
01528   }
01529   /* Process locked */
01530   __HAL_LOCK(hjpeg);
01531
01532   if (hjpeg->State != HAL_JPEG_STATE_READY)
01533   {
01534     /* Process Unlocked */
01535     __HAL_UNLOCK(hjpeg);
01536
01537     return HAL_BUSY;
01538   }
01539
01540   if (hjpeg->State == HAL_JPEG_STATE_READY)
01541   {
01542     if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
01543     {
01544       /*Change JPEG state*/
01545       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01546
01547       /*Set the Context to Encode with Polling*/
01548       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01549       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);
01550
01551       /* Get tick */
01552       tickstart = HAL_GetTick();
01553
01554       /*Store In/out buffers pointers and size*/
01555       hjpeg->pJpegInBuffPtr = pDataInMCU;
01556       hjpeg->pJpegOutBuffPtr = pDataOut;
01557       hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /* In Data length must be multiple of 4 Bytes (1 word)*/
01558       hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple of 4 Bytes (1 word)*/
01559
01560       /*Reset In/out data counter */
01561       hjpeg->JpegInCount = 0;
01562       hjpeg->JpegOutCount = 0;
01563
01564       /*Init decoding process*/
01565       JPEG_Init_Process(hjpeg);
01566
01567       /*JPEG data processing : In/Out FIFO transfer*/
01568       while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
01569       {
01570         if (Timeout != HAL_MAX_DELAY)
01571         {
01572           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01573           {
01574
01575             /* Update error code */
01576             hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
01577
01578             /* Process Unlocked */
01579             __HAL_UNLOCK(hjpeg);
01580
01581             /*Change JPEG state*/
01582             hjpeg->State = HAL_JPEG_STATE_READY;
01583
01584             return HAL_TIMEOUT;
01585           }
01586         }
01587       }
01588
01589       /* Process Unlocked */
01590       __HAL_UNLOCK(hjpeg);
01591
01592       /*Change JPEG state*/
01593       hjpeg->State = HAL_JPEG_STATE_READY;
01594
01595     }
01596     else
01597     {
01598       /* Process Unlocked */
01599       __HAL_UNLOCK(hjpeg);
01600
01601       return HAL_ERROR;
01602     }
01603   }
01604   /* Return function status */
01605   return HAL_OK;
01606 }
01607
01608 /**
01609   * @brief  Starts JPEG decoding with polling processing
01610   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01611   *         the configuration information for JPEG module
01612   * @param  pDataIn Pointer to the input data buffer
01613   * @param  InDataLength size in bytes Input buffer
01614   * @param  pDataOutMCU Pointer to the Output data buffer
01615   * @param  OutDataLength size in bytes of the Output buffer
01616   * @param  Timeout Specify Timeout value
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
01620                                    uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
01621 {
01622   uint32_t tickstart;
01623
01624   /* Check the parameters */
01625   assert_param((InDataLength >= 4UL));
01626   assert_param((OutDataLength >= 4UL));
01627
01628   /* Check In/out buffer allocation and size */
01629   if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01630   {
01631     return HAL_ERROR;
01632   }
01633
01634   /* Process Locked */
01635   __HAL_LOCK(hjpeg);
01636
01637   /* Get tick */
01638   tickstart = HAL_GetTick();
01639
01640   if (hjpeg->State == HAL_JPEG_STATE_READY)
01641   {
01642     /*Change JPEG state*/
01643     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01644
01645     /*Set the Context to Decode with Polling*/
01646     /*Set the Context to Encode with Polling*/
01647     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01648     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);
01649
01650     /*Store In/out buffers pointers and size*/
01651     hjpeg->pJpegInBuffPtr = pDataIn;
01652     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01653     hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple of 4 Bytes (1 word)*/
01654     hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
01655
01656     /*Reset In/out data counter */
01657     hjpeg->JpegInCount = 0;
01658     hjpeg->JpegOutCount = 0;
01659
01660     /*Init decoding process*/
01661     JPEG_Init_Process(hjpeg);
01662
01663     /*JPEG data processing : In/Out FIFO transfer*/
01664     while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
01665     {
01666       if (Timeout != HAL_MAX_DELAY)
01667       {
01668         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01669         {
01670
01671           /* Update error code */
01672           hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
01673
01674           /* Process Unlocked */
01675           __HAL_UNLOCK(hjpeg);
01676
01677           /*Change JPEG state*/
01678           hjpeg->State = HAL_JPEG_STATE_READY;
01679
01680           return HAL_TIMEOUT;
01681         }
01682       }
01683     }
01684
01685     /* Process Unlocked */
01686     __HAL_UNLOCK(hjpeg);
01687
01688     /*Change JPEG state*/
01689     hjpeg->State = HAL_JPEG_STATE_READY;
01690
01691   }
01692   else
01693   {
01694     /* Process Unlocked */
01695     __HAL_UNLOCK(hjpeg);
01696
01697     return HAL_BUSY;
01698   }
01699   /* Return function status */
01700   return HAL_OK;
01701 }
01702
01703 /**
01704   * @brief  Starts JPEG encoding with interrupt processing
01705   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01706   *         the configuration information for JPEG module
01707   * @param  pDataInMCU Pointer to the Input buffer
01708   * @param  InDataLength size in bytes Input buffer
01709   * @param  pDataOut Pointer to the jpeg output data buffer
01710   * @param  OutDataLength size in bytes of the Output buffer
01711   * @retval HAL status
01712   */
01713 HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
01714                                       uint8_t *pDataOut, uint32_t OutDataLength)
01715 {
01716   /* Check the parameters */
01717   assert_param((InDataLength >= 4UL));
01718   assert_param((OutDataLength >= 4UL));
01719
01720   /* Check In/out buffer allocation and size */
01721   if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01722   {
01723     return HAL_ERROR;
01724   }
01725
01726   /* Process Locked */
01727   __HAL_LOCK(hjpeg);
01728
01729   if (hjpeg->State != HAL_JPEG_STATE_READY)
01730   {
01731     /* Process Unlocked */
01732     __HAL_UNLOCK(hjpeg);
01733
01734     return HAL_BUSY;
01735   }
01736   else
01737   {
01738     if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
01739     {
01740       /*Change JPEG state*/
01741       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01742
01743       /*Set the Context to Encode with IT*/
01744       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01745       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);
01746
01747       /*Store In/out buffers pointers and size*/
01748       hjpeg->pJpegInBuffPtr = pDataInMCU;
01749       hjpeg->pJpegOutBuffPtr = pDataOut;
01750       hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple of 4 Bytes (1 word)*/
01751       hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
01752
01753       /*Reset In/out data counter */
01754       hjpeg->JpegInCount = 0;
01755       hjpeg->JpegOutCount = 0;
01756
01757       /*Init decoding process*/
01758       JPEG_Init_Process(hjpeg);
01759
01760     }
01761     else
01762     {
01763       /* Process Unlocked */
01764       __HAL_UNLOCK(hjpeg);
01765
01766       return HAL_ERROR;
01767     }
01768   }
01769   /* Return function status */
01770   return HAL_OK;
01771 }
01772
01773 /**
01774   * @brief  Starts JPEG decoding with interrupt processing
01775   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01776   *         the configuration information for JPEG module
01777   * @param  pDataIn Pointer to the input data buffer
01778   * @param  InDataLength size in bytes Input buffer
01779   * @param  pDataOutMCU Pointer to the Output data buffer
01780   * @param  OutDataLength size in bytes of the Output buffer
01781   * @retval HAL status
01782   */
01783 HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
01784                                       uint8_t *pDataOutMCU, uint32_t OutDataLength)
01785 {
01786   /* Check the parameters */
01787   assert_param((InDataLength >= 4UL));
01788   assert_param((OutDataLength >= 4UL));
01789
01790   /* Check In/out buffer allocation and size */
01791   if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01792   {
01793     return HAL_ERROR;
01794   }
01795
01796   /* Process Locked */
01797   __HAL_LOCK(hjpeg);
01798
01799   if (hjpeg->State == HAL_JPEG_STATE_READY)
01800   {
01801     /*Change JPEG state*/
01802     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01803
01804     /*Set the Context to Decode with IT*/
01805     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01806     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);
01807
01808     /*Store In/out buffers pointers and size*/
01809     hjpeg->pJpegInBuffPtr = pDataIn;
01810     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01811     hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple of 4 Bytes (1 word)*/
01812     hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
01813
01814     /*Reset In/out data counter */
01815     hjpeg->JpegInCount = 0;
01816     hjpeg->JpegOutCount = 0;
01817
01818     /*Init decoding process*/
01819     JPEG_Init_Process(hjpeg);
01820
01821   }
01822   else
01823   {
01824     /* Process Unlocked */
01825     __HAL_UNLOCK(hjpeg);
01826
01827     return HAL_BUSY;
01828   }
01829   /* Return function status */
01830   return HAL_OK;
01831 }
01832
01833 /**
01834   * @brief  Starts JPEG encoding with DMA processing
01835   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01836   *         the configuration information for JPEG module
01837   * @param  pDataInMCU Pointer to the Input buffer
01838   * @param  InDataLength size in bytes Input buffer
01839   * @param  pDataOut Pointer to the jpeg output data buffer
01840   * @param  OutDataLength size in bytes of the Output buffer
01841   * @retval HAL status
01842   */
01843 HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
01844                                        uint8_t *pDataOut, uint32_t OutDataLength)
01845 {
01846   /* Check the parameters */
01847   assert_param((InDataLength >= 4UL));
01848   assert_param((OutDataLength >= 4UL));
01849
01850   /* Check In/out buffer allocation and size */
01851   if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01852   {
01853     return HAL_ERROR;
01854   }
01855
01856   /* Process Locked */
01857   __HAL_LOCK(hjpeg);
01858
01859   if (hjpeg->State != HAL_JPEG_STATE_READY)
01860   {
01861     /* Process Unlocked */
01862     __HAL_UNLOCK(hjpeg);
01863
01864     return HAL_BUSY;
01865   }
01866   else
01867   {
01868     if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
01869     {
01870       /*Change JPEG state*/
01871       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01872
01873       /*Set the Context to Encode with DMA*/
01874       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01875       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA);
01876
01877       /*Store In/out buffers pointers and size*/
01878       hjpeg->pJpegInBuffPtr = pDataInMCU;
01879       hjpeg->pJpegOutBuffPtr = pDataOut;
01880       hjpeg->InDataLength = InDataLength;
01881       hjpeg->OutDataLength = OutDataLength;
01882
01883       /*Reset In/out data counter */
01884       hjpeg->JpegInCount = 0;
01885       hjpeg->JpegOutCount = 0;
01886
01887       /*Init decoding process*/
01888       JPEG_Init_Process(hjpeg);
01889
01890       /* JPEG encoding process using DMA */
01891       if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
01892       {
01893         /* Update State */
01894         hjpeg->State = HAL_JPEG_STATE_ERROR;
01895         /* Process Unlocked */
01896         __HAL_UNLOCK(hjpeg);
01897
01898         return HAL_ERROR;
01899       }
01900
01901     }
01902     else
01903     {
01904       /* Process Unlocked */
01905       __HAL_UNLOCK(hjpeg);
01906
01907       return HAL_ERROR;
01908     }
01909   }
01910   /* Return function status */
01911   return HAL_OK;
01912 }
01913
01914 /**
01915   * @brief  Starts JPEG decoding with DMA processing
01916   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01917   *         the configuration information for JPEG module
01918   * @param  pDataIn Pointer to the input data buffer
01919   * @param  InDataLength size in bytes Input buffer
01920   * @param  pDataOutMCU Pointer to the Output data buffer
01921   * @param  OutDataLength size in bytes of the Output buffer
01922   * @retval HAL status
01923   */
01924 HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
01925                                        uint8_t *pDataOutMCU, uint32_t OutDataLength)
01926 {
01927   /* Check the parameters */
01928   assert_param((InDataLength >= 4UL));
01929   assert_param((OutDataLength >= 4UL));
01930
01931   /* Check In/out buffer allocation and size */
01932   if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01933   {
01934     return HAL_ERROR;
01935   }
01936
01937   /* Process Locked */
01938   __HAL_LOCK(hjpeg);
01939
01940   if (hjpeg->State == HAL_JPEG_STATE_READY)
01941   {
01942     /*Change JPEG state*/
01943     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01944
01945     /*Set the Context to Decode with DMA*/
01946     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01947     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA);
01948
01949     /*Store In/out buffers pointers and size*/
01950     hjpeg->pJpegInBuffPtr = pDataIn;
01951     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01952     hjpeg->InDataLength = InDataLength;
01953     hjpeg->OutDataLength = OutDataLength;
01954
01955     /*Reset In/out data counter */
01956     hjpeg->JpegInCount = 0;
01957     hjpeg->JpegOutCount = 0;
01958
01959     /*Init decoding process*/
01960     JPEG_Init_Process(hjpeg);
01961
01962     /* JPEG decoding process using DMA */
01963     if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
01964     {
01965       /* Update State */
01966       hjpeg->State = HAL_JPEG_STATE_ERROR;
01967       /* Process Unlocked */
01968       __HAL_UNLOCK(hjpeg);
01969
01970       return HAL_ERROR;
01971     }
01972   }
01973   else
01974   {
01975     /* Process Unlocked */
01976     __HAL_UNLOCK(hjpeg);
01977
01978     return HAL_BUSY;
01979   }
01980   /* Return function status */
01981   return HAL_OK;
01982 }
01983
01984 /**
01985   * @brief  Pause the JPEG Input/Output processing
01986   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
01987   *         the configuration information for JPEG module
01988   * @param  XferSelection This parameter can be one of the following values :
01989   *                           JPEG_PAUSE_RESUME_INPUT : Pause Input processing
01990   *                           JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing
01991   *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
01992   * @retval HAL status
01993   */
01994 HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
01995 {
01996   uint32_t mask = 0;
01997
01998   assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
01999
02000   if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
02001   {
02002     if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
02003     {
02004       hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
02005     }
02006     if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
02007     {
02008       hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
02009     }
02010
02011   }
02012   else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
02013   {
02014
02015     if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
02016     {
02017       hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
02018       mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
02019     }
02020     if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
02021     {
02022       hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
02023       mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
02024     }
02025     __HAL_JPEG_DISABLE_IT(hjpeg, mask);
02026
02027   }
02028   else
02029   {
02030     /* Nothing to do */
02031   }
02032
02033   /* Return function status */
02034   return HAL_OK;
02035 }
02036
02037 /**
02038   * @brief  Resume the JPEG Input/Output processing
02039   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02040   *         the configuration information for JPEG module
02041   * @param  XferSelection This parameter can be one of the following values :
02042   *                           JPEG_PAUSE_RESUME_INPUT : Resume Input processing
02043   *                           JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing
02044   *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
02045   * @retval HAL status
02046   */
02047 HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
02048 {
02049   uint32_t mask = 0;
02050   uint32_t xfrSize;
02051
02052   assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
02053
02054   if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL)
02055   {
02056     /* if nothing paused to resume return error*/
02057     return HAL_ERROR;
02058   }
02059
02060   if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
02061   {
02062
02063     if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
02064     {
02065       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
02066       /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
02067         then MDMA In buffer size is 32 bytes
02068
02069         else (MDMA In is triggred with JPEG In FIFO not full flag)
02070         then MDMA In buffer size is 4 bytes
02071         */
02072       xfrSize = hjpeg->hdmain->Init.BufferTransferLength;
02073
02074       if (xfrSize == 0UL)
02075       {
02076         hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02077         hjpeg->State = HAL_JPEG_STATE_ERROR;
02078         return HAL_ERROR;
02079       }
02080       /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
02081       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % xfrSize);
02082
02083
02084       if (hjpeg->InDataLength > 0UL)
02085       {
02086         /* Start DMA FIFO In transfer */
02087         if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
02088                               hjpeg->InDataLength, 1) != HAL_OK)
02089         {
02090           hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02091           hjpeg->State = HAL_JPEG_STATE_ERROR;
02092           return HAL_ERROR;
02093         }
02094       }
02095     }
02096     if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
02097     {
02098       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
02099
02100       if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
02101       {
02102         JPEG_DMA_PollResidualData(hjpeg);
02103       }
02104       else
02105       {
02106         /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
02107           then MDMA out buffer size is 32 bytes
02108           else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
02109           then MDMA buffer size is 4 bytes
02110           */
02111         xfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
02112
02113         if (xfrSize == 0UL)
02114         {
02115           hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02116           hjpeg->State = HAL_JPEG_STATE_ERROR;
02117           return HAL_ERROR;
02118         }
02119         /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
02120         hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % xfrSize);
02121
02122         /* Start DMA FIFO Out transfer */
02123         if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
02124                               hjpeg->OutDataLength, 1) != HAL_OK)
02125         {
02126           hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02127           hjpeg->State = HAL_JPEG_STATE_ERROR;
02128           return HAL_ERROR;
02129         }
02130       }
02131
02132     }
02133
02134   }
02135   else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
02136   {
02137     if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
02138     {
02139       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
02140       mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
02141     }
02142     if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
02143     {
02144       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
02145       mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
02146     }
02147     __HAL_JPEG_ENABLE_IT(hjpeg, mask);
02148
02149   }
02150   else
02151   {
02152     /* Nothing to do */
02153   }
02154
02155   /* Return function status */
02156   return HAL_OK;
02157 }
02158
02159 /**
02160   * @brief  Config Encoding/Decoding Input Buffer.
02161   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02162   *         the configuration information for JPEG module.
02163   * @param  pNewInputBuffer Pointer to the new input data buffer
02164   * @param  InDataLength Size in bytes of the new Input data buffer
02165   * @retval HAL status
02166   */
02167 void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
02168 {
02169   hjpeg->pJpegInBuffPtr =  pNewInputBuffer;
02170   hjpeg->InDataLength = InDataLength;
02171 }
02172
02173 /**
02174   * @brief  Config Encoding/Decoding Output Buffer.
02175   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02176   *         the configuration information for JPEG module.
02177   * @param  pNewOutputBuffer Pointer to the new output data buffer
02178   * @param  OutDataLength Size in bytes of the new Output data buffer
02179   * @retval HAL status
02180   */
02181 void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
02182 {
02183   hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;
02184   hjpeg->OutDataLength = OutDataLength;
02185 }
02186
02187 /**
02188   * @brief  Aborts the JPEG Encoding/Decoding.
02189   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02190   *         the configuration information for JPEG module
02191   * @retval HAL status
02192   */
02193 HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
02194 {
02195   uint32_t tickstart, tmpContext;
02196   tmpContext = hjpeg->Context;
02197
02198   /*Reset the Context operation and method*/
02199   hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);
02200
02201   if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
02202   {
02203     /* Stop the DMA In/out Xfer*/
02204     if (HAL_MDMA_Abort(hjpeg->hdmaout) != HAL_OK)
02205     {
02206       if (hjpeg->hdmaout->ErrorCode == HAL_MDMA_ERROR_TIMEOUT)
02207       {
02208         hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02209       }
02210     }
02211     if (HAL_MDMA_Abort(hjpeg->hdmain) != HAL_OK)
02212     {
02213       if (hjpeg->hdmain->ErrorCode == HAL_MDMA_ERROR_TIMEOUT)
02214       {
02215         hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
02216       }
02217     }
02218
02219   }
02220
02221   /* Stop the JPEG encoding/decoding process*/
02222   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
02223
02224   /* Get tick */
02225   tickstart = HAL_GetTick();
02226
02227   /* Check if the JPEG Codec is effectively disabled */
02228   while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL)
02229   {
02230     /* Check for the Timeout */
02231     if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE)
02232     {
02233       /* Update error code */
02234       hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
02235
02236       /* Change the DMA state */
02237       hjpeg->State = HAL_JPEG_STATE_ERROR;
02238       break;
02239     }
02240   }
02241
02242   /* Disable All Interrupts */
02243   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
02244
02245
02246   /* Flush input and output FIFOs*/
02247   hjpeg->Instance->CR |= JPEG_CR_IFF;
02248   hjpeg->Instance->CR |= JPEG_CR_OFF;
02249
02250   /* Clear all flags */
02251   __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
02252
02253   /* Reset JpegInCount and JpegOutCount */
02254   hjpeg->JpegInCount = 0;
02255   hjpeg->JpegOutCount = 0;
02256
02257   /*Reset the Context Pause*/
02258   hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);
02259
02260   /* Change the DMA state*/
02261   if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE)
02262   {
02263     hjpeg->State = HAL_JPEG_STATE_ERROR;
02264     /* Process Unlocked */
02265     __HAL_UNLOCK(hjpeg);
02266     /* Return function status */
02267     return HAL_ERROR;
02268   }
02269   else
02270   {
02271     hjpeg->State = HAL_JPEG_STATE_READY;
02272     /* Process Unlocked */
02273     __HAL_UNLOCK(hjpeg);
02274     /* Return function status */
02275     return HAL_OK;
02276   }
02277
02278 }
02279
02280
02281 /**
02282   * @}
02283   */
02284
02285 /** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions
02286   *  @brief   JPEG process callback functions.
02287   *
02288 @verbatim
02289   ==============================================================================
02290               #####  JPEG Decode and Encode callback functions  #####
02291   ==============================================================================
02292     [..]  This section provides callback functions:
02293       (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback
02294       (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
02295       (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
02296       (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.
02297       (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback.
02298       (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback.
02299
02300 @endverbatim
02301   * @{
02302   */
02303
02304 /**
02305   * @brief  Decoding JPEG Info ready callback.
02306   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02307   *         the configuration information for JPEG module
02308   * @param  pInfo pointer to a JPEG_ConfTypeDef structure that contains
02309   *         The JPEG decoded header informations
02310   * @retval None
02311   */
02312 __weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
02313 {
02314   /* Prevent unused argument(s) compilation warning */
02315   UNUSED(hjpeg);
02316   UNUSED(pInfo);
02317
02318   /* NOTE : This function Should not be modified, when the callback is needed,
02319             the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file
02320    */
02321 }
02322
02323 /**
02324   * @brief  Encoding complete callback.
02325   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02326   *         the configuration information for JPEG module
02327   * @retval None
02328   */
02329 __weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
02330 {
02331   /* Prevent unused argument(s) compilation warning */
02332   UNUSED(hjpeg);
02333
02334   /* NOTE : This function Should not be modified, when the callback is needed,
02335             the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
02336    */
02337 }
02338
02339 /**
02340   * @brief  Decoding complete callback.
02341   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02342   *         the configuration information for JPEG module
02343   * @retval None
02344   */
02345 __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
02346 {
02347   /* Prevent unused argument(s) compilation warning */
02348   UNUSED(hjpeg);
02349
02350   /* NOTE : This function Should not be modified, when the callback is needed,
02351             the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
02352    */
02353 }
02354
02355 /**
02356   * @brief  JPEG error callback.
02357   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02358   *         the configuration information for JPEG module
02359   * @retval None
02360   */
02361 __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
02362 {
02363   /* Prevent unused argument(s) compilation warning */
02364   UNUSED(hjpeg);
02365
02366   /* NOTE : This function Should not be modified, when the callback is needed,
02367             the HAL_JPEG_ErrorCallback could be implemented in the user file
02368    */
02369 }
02370
02371 /**
02372   * @brief  Get New Data chunk callback.
02373   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02374   *         the configuration information for JPEG module
02375   * @param  NbDecodedData Number of consummed data in the previous chunk in bytes
02376   * @retval None
02377   */
02378 __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
02379 {
02380   /* Prevent unused argument(s) compilation warning */
02381   UNUSED(hjpeg);
02382   UNUSED(NbDecodedData);
02383
02384   /* NOTE : This function Should not be modified, when the callback is needed,
02385             the HAL_JPEG_GetDataCallback could be implemented in the user file
02386    */
02387 }
02388
02389 /**
02390   * @brief  Decoded/Encoded Data ready  callback.
02391   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02392   *         the configuration information for JPEG module
02393   * @param  pDataOut pointer to the output data buffer
02394   * @param  OutDataLength number in bytes of data available in the specified output buffer
02395   * @retval None
02396   */
02397 __weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
02398 {
02399   /* Prevent unused argument(s) compilation warning */
02400   UNUSED(hjpeg);
02401   UNUSED(pDataOut);
02402   UNUSED(OutDataLength);
02403
02404   /* NOTE : This function Should not be modified, when the callback is needed,
02405             the HAL_JPEG_DataReadyCallback could be implemented in the user file
02406    */
02407 }
02408
02409 /**
02410   * @}
02411   */
02412
02413
02414 /** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management
02415   *  @brief   JPEG IRQ handler.
02416   *
02417 @verbatim
02418   ==============================================================================
02419                 ##### JPEG IRQ handler management #####
02420   ==============================================================================
02421     [..]  This section provides JPEG IRQ handler function.
02422       (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request
02423
02424 @endverbatim
02425   * @{
02426   */
02427
02428 /**
02429   * @brief  This function handles JPEG interrupt request.
02430   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02431   *         the configuration information for JPEG module
02432   * @retval None
02433   */
02434 void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
02435 {
02436   switch (hjpeg->State)
02437   {
02438     case HAL_JPEG_STATE_BUSY_ENCODING:
02439     case HAL_JPEG_STATE_BUSY_DECODING:
02440       /* continue JPEG data encoding/Decoding*/
02441       /* JPEG data processing : In/Out FIFO transfer*/
02442       if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
02443       {
02444         (void) JPEG_Process(hjpeg);
02445       }
02446       else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
02447       {
02448         JPEG_DMA_ContinueProcess(hjpeg);
02449       }
02450       else
02451       {
02452         /* Nothing to do */
02453       }
02454       break;
02455
02456     default:
02457       break;
02458   }
02459 }
02460
02461 /**
02462   * @}
02463   */
02464
02465 /** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions
02466   *  @brief   Peripheral State functions.
02467   *
02468 @verbatim
02469   ==============================================================================
02470                     ##### Peripheral State and Error functions #####
02471   ==============================================================================
02472     [..]  This section provides JPEG State and Errors function.
02473       (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.
02474       (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.
02475
02476 @endverbatim
02477   * @{
02478   */
02479
02480 /**
02481   * @brief  Returns the JPEG state.
02482   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02483   *         the configuration information for JPEG module
02484   * @retval JPEG state
02485   */
02486 HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)
02487 {
02488   return hjpeg->State;
02489 }
02490
02491 /**
02492   * @brief  Return the JPEG error code
02493   * @param  hjpeg  pointer to a JPEG_HandleTypeDef structure that contains
02494   *              the configuration information for the specified JPEG.
02495   * @retval JPEG Error Code
02496   */
02497 uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
02498 {
02499   return hjpeg->ErrorCode;
02500 }
02501
02502 /**
02503   * @}
02504   */
02505
02506 /**
02507   * @}
02508   */
02509
02510
02511 /** @addtogroup JPEG_Private_Functions
02512   * @{
02513   */
02514
02515 /**
02516   * @brief  Generates Huffman sizes/Codes Table from Bits/vals Table
02517   * @param  Bits pointer to bits table
02518   * @param  Huffsize pointer to sizes table
02519   * @param  Huffcode pointer to codes table
02520   * @param  LastK pointer to last Coeff (table dimmension)
02521   * @retval HAL status
02522   */
02523 static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
02524 {
02525   uint32_t i, p, l, code, si;
02526
02527   /* Figure C.1: Generation of table of Huffman code sizes */
02528   p = 0;
02529   for (l = 0; l < 16UL; l++)
02530   {
02531     i = (uint32_t)Bits[l];
02532     if ((p + i) > 256UL)
02533     {
02534       /* check for table overflow */
02535       return HAL_ERROR;
02536     }
02537     while (i != 0UL)
02538     {
02539       Huffsize[p] = (uint8_t) l + 1U;
02540       p++;
02541       i--;
02542     }
02543   }
02544   Huffsize[p] = 0;
02545   *LastK = p;
02546
02547   /* Figure C.2: Generation of table of Huffman codes */
02548   code = 0;
02549   si = Huffsize[0];
02550   p = 0;
02551   while (Huffsize[p] != 0U)
02552   {
02553     while (((uint32_t) Huffsize[p]) == si)
02554     {
02555       Huffcode[p] = code;
02556       p++;
02557       code++;
02558     }
02559     /* code must fit in "size" bits (si), no code is allowed to be all ones*/
02560     if(si > 31UL)
02561     {
02562       return HAL_ERROR;
02563     }
02564     if (((uint32_t) code) >= (((uint32_t) 1) << si))
02565     {
02566       return HAL_ERROR;
02567     }
02568     code <<= 1;
02569     si++;
02570   }
02571   /* Return function status */
02572   return HAL_OK;
02573 }
02574
02575 /**
02576   * @brief  Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table
02577   *         that can programmed to the JPEG encoder registers
02578   * @param  AC_BitsValsTable pointer to AC huffman bits/vals table
02579   * @param  AC_SizeCodesTable pointer to AC huffman Sizes/Codes table
02580   * @retval HAL status
02581   */
02582 static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
02583                                                            JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
02584 {
02585   HAL_StatusTypeDef error;
02586   uint8_t huffsize[257];
02587   uint32_t huffcode[257];
02588   uint32_t k;
02589   uint32_t l, lsb, msb;
02590   uint32_t lastK;
02591
02592   error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
02593   if (error != HAL_OK)
02594   {
02595     return  error;
02596   }
02597
02598   /* Figure C.3: Ordering procedure for encoding procedure code tables */
02599   k = 0;
02600
02601   while (k < lastK)
02602   {
02603     l = AC_BitsValsTable->HuffVal[k];
02604     if (l == 0UL)
02605     {
02606       l = 160; /*l = 0x00 EOB code*/
02607     }
02608     else if (l == 0xF0UL) /* l = 0xF0 ZRL code*/
02609     {
02610       l = 161;
02611     }
02612     else
02613     {
02614       msb = (l & 0xF0UL) >> 4;
02615       lsb = (l & 0x0FUL);
02616       l = (msb * 10UL) + lsb - 1UL;
02617     }
02618     if (l >= JPEG_AC_HUFF_TABLE_SIZE)
02619     {
02620       return HAL_ERROR; /* Huffman Table overflow error*/
02621     }
02622     else
02623     {
02624       AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
02625       AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U;
02626       k++;
02627     }
02628   }
02629
02630   /* Return function status */
02631   return HAL_OK;
02632 }
02633
02634 /**
02635   * @brief  Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table
02636   *         that can programmed to the JPEG encoder registers
02637   * @param  DC_BitsValsTable pointer to DC huffman bits/vals table
02638   * @param  DC_SizeCodesTable pointer to DC huffman Sizes/Codes table
02639   * @retval HAL status
02640   */
02641 static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
02642                                                            JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
02643 {
02644   HAL_StatusTypeDef error;
02645
02646   uint32_t k;
02647   uint32_t l;
02648   uint32_t lastK;
02649   uint8_t huffsize[257];
02650   uint32_t huffcode[257];
02651   error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
02652   if (error != HAL_OK)
02653   {
02654     return  error;
02655   }
02656   /* Figure C.3: ordering procedure for encoding procedure code tables */
02657   k = 0;
02658
02659   while (k < lastK)
02660   {
02661     l = DC_BitsValsTable->HuffVal[k];
02662     if (l >= JPEG_DC_HUFF_TABLE_SIZE)
02663     {
02664       return HAL_ERROR; /* Huffman Table overflow error*/
02665     }
02666     else
02667     {
02668       DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
02669       DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U;
02670       k++;
02671     }
02672   }
02673
02674   /* Return function status */
02675   return HAL_OK;
02676 }
02677
02678 /**
02679   * @brief  Set the JPEG register with an DC huffman table at the given DC table address
02680   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02681   *         the configuration information for JPEG module
02682   * @param  HuffTableDC pointer to DC huffman table
02683   * @param  DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
02684   * @retval HAL status
02685   */
02686 static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
02687                                              const __IO uint32_t *DCTableAddress)
02688 {
02689   HAL_StatusTypeDef error;
02690   JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
02691   uint32_t i, lsb, msb;
02692   __IO uint32_t *address, *addressDef;
02693
02694   if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
02695   {
02696     address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
02697   }
02698   else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1))
02699   {
02700     address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
02701   }
02702   else
02703   {
02704     return HAL_ERROR;
02705   }
02706
02707   if (HuffTableDC != NULL)
02708   {
02709     error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);
02710     if (error != HAL_OK)
02711     {
02712       return  error;
02713     }
02714     addressDef = address;
02715     *addressDef = 0x0FFF0FFF;
02716     addressDef++;
02717     *addressDef = 0x0FFF0FFF;
02718
02719     i = JPEG_DC_HUFF_TABLE_SIZE;
02720     while (i > 1UL)
02721     {
02722       i--;
02723       address --;
02724       msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] &
02725                                                                                    0xFFUL);
02726       i--;
02727       lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] &
02728                                                                                    0xFFUL);
02729
02730       *address = lsb | (msb << 16);
02731     }
02732   }
02733
02734   /* Return function status */
02735   return HAL_OK;
02736 }
02737
02738 /**
02739   * @brief  Set the JPEG register with an AC huffman table at the given AC table address
02740   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02741   *         the configuration information for JPEG module
02742   * @param  HuffTableAC pointer to AC huffman table
02743   * @param  ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
02744   * @retval HAL status
02745   */
02746 static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
02747                                              const __IO uint32_t *ACTableAddress)
02748 {
02749   HAL_StatusTypeDef error;
02750   JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;
02751   uint32_t i, lsb, msb;
02752   __IO uint32_t *address, *addressDef;
02753
02754   if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0))
02755   {
02756     address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
02757   }
02758   else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1))
02759   {
02760     address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
02761   }
02762   else
02763   {
02764     return HAL_ERROR;
02765   }
02766
02767   if (HuffTableAC != NULL)
02768   {
02769     error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);
02770     if (error != HAL_OK)
02771     {
02772       return  error;
02773     }
02774     /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */
02775     /* Locations 162:175 of each AC table contain information used internally by the core */
02776
02777     addressDef = address;
02778     for (i = 0; i < 3UL; i++)
02779     {
02780       *addressDef = 0x0FFF0FFF;
02781       addressDef++;
02782     }
02783     *addressDef = 0x0FD10FD0;
02784     addressDef++;
02785     *addressDef = 0x0FD30FD2;
02786     addressDef++;
02787     *addressDef = 0x0FD50FD4;
02788     addressDef++;
02789     *addressDef = 0x0FD70FD6;
02790     /* end of Locations 162:175  */
02791
02792
02793     i = JPEG_AC_HUFF_TABLE_SIZE;
02794     while (i > 1UL)
02795     {
02796       i--;
02797       address--;
02798       msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] &
02799                                                                                    0xFFUL);
02800       i--;
02801       lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] &
02802                                                                                    0xFFUL);
02803
02804       *address = lsb | (msb << 16);
02805     }
02806   }
02807
02808   /* Return function status */
02809   return HAL_OK;
02810 }
02811
02812 /**
02813   * @brief  Configure the JPEG encoder register huffman tables to used during
02814   *         the encdoing operation
02815   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02816   *         the configuration information for JPEG module
02817   * @retval None
02818   */
02819 static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg)
02820 {
02821   HAL_StatusTypeDef error;
02822
02823   JPEG_Set_Huff_DHTMem(hjpeg);
02824   error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable,
02825                               (hjpeg->Instance->HUFFENC_AC0));
02826   if (error != HAL_OK)
02827   {
02828     return  error;
02829   }
02830
02831   error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable,
02832                               (hjpeg->Instance->HUFFENC_AC1));
02833   if (error != HAL_OK)
02834   {
02835     return  error;
02836   }
02837
02838   error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable,
02839                               hjpeg->Instance->HUFFENC_DC0);
02840   if (error != HAL_OK)
02841   {
02842     return  error;
02843   }
02844
02845   error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable,
02846                               hjpeg->Instance->HUFFENC_DC1);
02847   if (error != HAL_OK)
02848   {
02849     return  error;
02850   }
02851   /* Return function status */
02852   return HAL_OK;
02853 }
02854
02855 /**
02856   * @brief  Configure the JPEG register huffman tables to be included in the JPEG
02857   *         file header (used for encoding only)
02858   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
02859   *         the configuration information for JPEG module
02860   * @retval None
02861   */
02862 static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg)
02863 {
02864   JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable;
02865   JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable;
02866   JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable;
02867   JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable;
02868   uint32_t value, index;
02869   __IO uint32_t *address;
02870
02871   /* DC0 Huffman Table : BITS*/
02872   /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
02873   address = (hjpeg->Instance->DHTMEM + 3);
02874   index = 16;
02875   while (index > 3UL)
02876   {
02877
02878     *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) |
02879                (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) |
02880                (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) |
02881                ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL);
02882     address--;
02883     index -= 4UL;
02884
02885   }
02886   /* DC0 Huffman Table : Val*/
02887   /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
02888   address = (hjpeg->Instance->DHTMEM + 6);
02889   index = 12;
02890   while (index > 3UL)
02891   {
02892     *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
02893                (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
02894                (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
02895                ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL);
02896     address--;
02897     index -= 4UL;
02898   }
02899
02900   /* AC0 Huffman Table : BITS*/
02901   /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
02902   address = (hjpeg->Instance->DHTMEM + 10UL);
02903   index = 16;
02904   while (index > 3UL)
02905   {
02906
02907     *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) |
02908                (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) |
02909                (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) |
02910                ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL);
02911     address--;
02912     index -= 4UL;
02913
02914   }
02915   /* AC0 Huffman Table : Val*/
02916   /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
02917   /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
02918   address = (hjpeg->Instance->DHTMEM + 51);
02919   value = *address & 0xFFFF0000U;
02920   value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL);
02921   *address = value;
02922
02923   /*continue setting 160 AC0 huffman values */
02924   address--; /* address = hjpeg->Instance->DHTMEM + 50*/
02925   index = 160;
02926   while (index > 3UL)
02927   {
02928     *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
02929                (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
02930                (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
02931                ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL);
02932     address--;
02933     index -= 4UL;
02934   }
02935
02936   /* DC1 Huffman Table : BITS*/
02937   /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
02938   /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
02939   address = (hjpeg->Instance->DHTMEM + 51);
02940   value = *address & 0x0000FFFFU;
02941   value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16);
02942   *address = value;
02943
02944   /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
02945   address = (hjpeg->Instance->DHTMEM + 55);
02946   value = *address & 0xFFFF0000U;
02947   value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL);
02948   *address = value;
02949
02950   /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
02951   address--;
02952   index = 12;
02953   while (index > 3UL)
02954   {
02955
02956     *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) |
02957                (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) |
02958                (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) |
02959                ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL);
02960     address--;
02961     index -= 4UL;
02962
02963   }
02964   /* DC1 Huffman Table : Val*/
02965   /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
02966   /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
02967   address = (hjpeg->Instance->DHTMEM + 55);
02968   value = *address & 0x0000FFFFUL;
02969   value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) <<
02970                                                                          16);
02971   *address = value;
02972
02973   /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
02974   address = (hjpeg->Instance->DHTMEM + 58);
02975   value = *address & 0xFFFF0000UL;
02976   value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL);
02977   *address = value;
02978
02979   /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
02980   address--;
02981   index = 8;
02982   while (index > 3UL)
02983   {
02984     *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
02985                (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) |
02986                (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
02987                ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL);
02988     address--;
02989     index -= 4UL;
02990   }
02991
02992   /* AC1 Huffman Table : BITS*/
02993   /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
02994   /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
02995   address = (hjpeg->Instance->DHTMEM + 58);
02996   value = *address & 0x0000FFFFU;
02997   value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16);
02998   *address = value;
02999
03000   /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
03001   address = (hjpeg->Instance->DHTMEM + 62);
03002   value = *address & 0xFFFF0000U;
03003   value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL);
03004   *address = value;
03005
03006   /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
03007   address--;
03008   index = 12;
03009   while (index > 3UL)
03010   {
03011
03012     *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) |
03013                (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) |
03014                (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) |
03015                ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL);
03016     address--;
03017     index -= 4UL;
03018
03019   }
03020   /* AC1 Huffman Table : Val*/
03021   /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
03022   /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
03023   address = (hjpeg->Instance->DHTMEM + 62);
03024   value = *address & 0x0000FFFFUL;
03025   value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) <<
03026                                                                          16);
03027   *address = value;
03028
03029   /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
03030   address = (hjpeg->Instance->DHTMEM + 102);
03031   index = 160;
03032   while (index > 3UL)
03033   {
03034     *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
03035                (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) |
03036                (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
03037                ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL);
03038     address--;
03039     index -= 4UL;
03040   }
03041
03042 }
03043
03044 /**
03045   * @brief  Configure the JPEG registers with a given quantization table
03046   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03047   *         the configuration information for JPEG module
03048   * @param  QTable pointer to an array of 64 bytes giving the quantization table
03049   * @param  QTableAddress destination quantization address in the JPEG peripheral
03050   *         it could be QMEM0, QMEM1, QMEM2 or QMEM3
03051   * @retval 0 if no error, 1 if error
03052   */
03053 static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
03054                                                     __IO uint32_t *QTableAddress)
03055 {
03056   uint32_t i, j, quantRow, quantVal, ScaleFactor;
03057   __IO uint32_t *tableAddress;
03058
03059   tableAddress = QTableAddress;
03060
03061   if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL))
03062   {
03063     ScaleFactor = 200UL - (hjpeg->Conf.ImageQuality * 2UL);
03064   }
03065   else if (hjpeg->Conf.ImageQuality > 0UL)
03066   {
03067     ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);
03068   }
03069   else
03070   {
03071     return 1UL;
03072   }
03073
03074   /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/
03075   i = 0;
03076   while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
03077   {
03078     quantRow = 0;
03079     for (j = 0; j < 4UL; j++)
03080     {
03081       /* Note that the quantization coefficients must be specified in the table in zigzag order */
03082       quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL;
03083
03084       if (quantVal == 0UL)
03085       {
03086         quantVal = 1UL;
03087       }
03088       else if (quantVal > 255UL)
03089       {
03090         quantVal = 255UL;
03091       }
03092       else
03093       {
03094         /* Nothing to do, keep same value of quantVal */
03095       }
03096
03097       quantRow |= ((quantVal & 0xFFUL) << (8UL * j));
03098     }
03099
03100     i += 4UL;
03101     *tableAddress = quantRow;
03102     tableAddress ++;
03103   }
03104
03105   /* Return function status */
03106   return 0UL;
03107 }
03108
03109 /**
03110   * @brief  Configure the JPEG registers for YCbCr color space
03111   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03112   *         the configuration information for JPEG module
03113   * @retval None
03114   */
03115 static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
03116 {
03117   uint32_t ySamplingH;
03118   uint32_t ySamplingV;
03119   uint32_t yblockNb;
03120
03121   /*Set Number of color components to 3*/
03122   hjpeg->Instance->CONFR1 &=  ~JPEG_CONFR1_NF;
03123   hjpeg->Instance->CONFR1 |=  JPEG_CONFR1_NF_1;
03124
03125   /* compute MCU block size and Y, Cb ,Cr sampling factors*/
03126   if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
03127   {
03128     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
03129     ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
03130
03131     yblockNb  = 0x30; /* 4 blocks of 8x8*/
03132   }
03133   else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
03134   {
03135     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
03136     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
03137
03138     yblockNb  = 0x10; /* 2 blocks of 8x8*/
03139   }
03140   else /*JPEG_444_SUBSAMPLING and default*/
03141   {
03142     ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
03143     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
03144
03145     yblockNb  = 0; /* 1 block of 8x8*/
03146   }
03147
03148   hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
03149   hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
03150
03151   /*Reset CONFR4 register*/
03152   hjpeg->Instance->CONFR4 =  0;
03153   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
03154   hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
03155
03156   /*Reset CONFR5 register*/
03157   hjpeg->Instance->CONFR5 =  0;
03158   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
03159   hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);
03160
03161   /*Reset CONFR6 register*/
03162   hjpeg->Instance->CONFR6 =  0;
03163   /*Set Horizental and Vertical  sampling factor and number of blocks for component 2*/
03164   /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */
03165   /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */
03166   hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);
03167
03168 }
03169
03170 /**
03171   * @brief  Configure the JPEG registers for GrayScale color space
03172   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03173   *         the configuration information for JPEG module
03174   * @retval None
03175   */
03176 static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)
03177 {
03178   /*Set Number of color components to 1*/
03179   hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
03180
03181   /*in GrayScale use 1 single Quantization table (Table 0)*/
03182   /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/
03183
03184   /*Reset CONFR4 register*/
03185   hjpeg->Instance->CONFR4 =  0;
03186   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
03187   hjpeg->Instance->CONFR4 |=  JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;
03188 }
03189
03190 /**
03191   * @brief  Configure the JPEG registers for CMYK color space
03192   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03193   *         the configuration information for JPEG module
03194   * @retval None
03195   */
03196 static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
03197 {
03198   uint32_t ySamplingH;
03199   uint32_t ySamplingV;
03200   uint32_t yblockNb;
03201
03202   /*Set Number of color components to 4*/
03203   hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);
03204
03205   /* compute MCU block size and Y, Cb ,Cr sampling factors*/
03206   if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
03207   {
03208     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
03209     ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
03210
03211     yblockNb  = 0x30; /* 4 blocks of 8x8*/
03212   }
03213   else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
03214   {
03215     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
03216     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
03217
03218     yblockNb  = 0x10; /* 2 blocks of 8x8*/
03219   }
03220   else /*JPEG_444_SUBSAMPLING and default*/
03221   {
03222     ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
03223     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
03224
03225     yblockNb  = 0; /* 1 block of 8x8*/
03226   }
03227
03228   /*Reset CONFR4 register*/
03229   hjpeg->Instance->CONFR4 =  0;
03230   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
03231   hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
03232
03233   /*Reset CONFR5 register*/
03234   hjpeg->Instance->CONFR5 =  0;
03235   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
03236   hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
03237
03238   /*Reset CONFR6 register*/
03239   hjpeg->Instance->CONFR6 =  0;
03240   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/
03241   hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
03242
03243   /*Reset CONFR7 register*/
03244   hjpeg->Instance->CONFR7 =  0;
03245   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/
03246   hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
03247 }
03248
03249 /**
03250   * @brief  Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA
03251   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03252   *         the configuration information for JPEG module
03253   * @retval None
03254   */
03255 static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
03256 {
03257   /*Reset pause*/
03258   hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));
03259
03260   if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03261   {
03262     /*Set JPEG Codec to Decoding mode */
03263     hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;
03264   }
03265   else /* JPEG_CONTEXT_ENCODE */
03266   {
03267     /*Set JPEG Codec to Encoding mode */
03268     hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;
03269   }
03270
03271   /*Stop JPEG processing */
03272   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03273
03274   /* Disable All Interrupts */
03275   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
03276
03277   /* Flush input and output FIFOs*/
03278   hjpeg->Instance->CR |= JPEG_CR_IFF;
03279   hjpeg->Instance->CR |= JPEG_CR_OFF;
03280
03281   /* Clear all flags */
03282   __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
03283
03284   /*Start Encoding/Decoding*/
03285   hjpeg->Instance->CONFR0 |=  JPEG_CONFR0_START;
03286
03287   if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
03288   {
03289     /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/
03290     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD);
03291   }
03292   else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
03293   {
03294     /*Enable End Of Conversation, and End Of Header parsing interruptions*/
03295     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
03296
03297   }
03298   else
03299   {
03300     /* Nothing to do */
03301   }
03302 }
03303
03304 /**
03305   * @brief  JPEG encoding/decoding process in case of Polling or Interrupt
03306   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03307   *         the configuration information for JPEG module
03308   * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING
03309   */
03310 static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
03311 {
03312   uint32_t tmpContext;
03313
03314   /*End of header processing flag rised*/
03315   if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03316   {
03317     if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
03318     {
03319       /*Call Header parsing complet callback */
03320       (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
03321       /* Reset the ImageQuality */
03322       hjpeg->Conf.ImageQuality = 0;
03323       /* Note : the image quality is only available at the end of the decoding operation */
03324       /* at the current stage the calculated image quality is not correct so reset it */
03325
03326       /*Call Info Ready callback */
03327 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03328       hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
03329 #else
03330       HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
03331 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03332
03333       __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
03334
03335       /* Clear header processing done flag */
03336       __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
03337     }
03338   }
03339
03340   /*Input FIFO status handling*/
03341   if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL)
03342   {
03343     if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL)
03344     {
03345       /*Input FIFO threshold flag rised*/
03346       /*JPEG_FIFO_TH_SIZE words can be written in */
03347       JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE);
03348     }
03349     else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL)
03350     {
03351       /*Input FIFO Not Full flag rised*/
03352       /*32-bit value can be written in */
03353       JPEG_ReadInputData(hjpeg, 1);
03354     }
03355     else
03356     {
03357       /* Nothing to do */
03358     }
03359   }
03360
03361
03362   /*Output FIFO flag handling*/
03363   if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
03364   {
03365     if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL)
03366     {
03367       /*Output FIFO threshold flag rised*/
03368       /*JPEG_FIFO_TH_SIZE words can be read out */
03369       JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
03370     }
03371     else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
03372     {
03373       /*Output FIFO Not Empty flag rised*/
03374       /*32-bit value can be read out */
03375       JPEG_StoreOutputData(hjpeg, 1);
03376     }
03377     else
03378     {
03379       /* Nothing to do */
03380     }
03381   }
03382
03383   /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/
03384   if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)
03385   {
03386     /*Stop Encoding/Decoding*/
03387     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03388
03389     if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
03390     {
03391       /* Disable All Interrupts */
03392       __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
03393     }
03394
03395     /* Clear all flags */
03396     __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
03397
03398     /*Call End of conversion callback */
03399     if (hjpeg->JpegOutCount > 0UL)
03400     {
03401       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
03402 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03403       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03404 #else
03405       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03406 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03407
03408       hjpeg->JpegOutCount = 0;
03409     }
03410
03411     /*Reset Context Operation*/
03412     tmpContext = hjpeg->Context;
03413     /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
03414     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
03415
03416     /* Process Unlocked */
03417     __HAL_UNLOCK(hjpeg);
03418
03419     /* Change the JPEG state */
03420     hjpeg->State = HAL_JPEG_STATE_READY;
03421
03422     /*Call End of Encoding/Decoding callback */
03423     if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03424     {
03425 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03426       hjpeg->DecodeCpltCallback(hjpeg);
03427 #else
03428       HAL_JPEG_DecodeCpltCallback(hjpeg);
03429 #endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
03430     }
03431     else /* JPEG_CONTEXT_ENCODE */
03432     {
03433 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03434       hjpeg->EncodeCpltCallback(hjpeg);
03435 #else
03436       HAL_JPEG_EncodeCpltCallback(hjpeg);
03437 #endif
03438     }
03439
03440     return JPEG_PROCESS_DONE;
03441   }
03442
03443
03444   return JPEG_PROCESS_ONGOING;
03445 }
03446
03447 /**
03448   * @brief  Store some output data from the JPEG peripheral to the output buffer.
03449   *         This function is used when the JPEG peripheral has new data to output
03450   *         in case of Polling or Interrupt process
03451   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03452   *         the configuration information for JPEG module
03453   * @param  nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral
03454   * @retval None
03455   */
03456 static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
03457 {
03458   uint32_t index, nBwords, nbBytes, dataword;
03459
03460   if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
03461   {
03462     for (index = 0; index < nbOutputWords; index++)
03463     {
03464       /*Transfer 32 bits from the JPEG output FIFO*/
03465       dataword = hjpeg->Instance->DOR;
03466       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
03467       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
03468       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
03469       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
03470       hjpeg->JpegOutCount += 4UL;
03471     }
03472     if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
03473     {
03474       /*Output Buffer is full, call DecodedDataReadyCallback*/
03475 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03476       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03477 #else
03478       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03479 #endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
03480       hjpeg->JpegOutCount = 0;
03481     }
03482   }
03483   else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
03484   {
03485     nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
03486     for (index = 0; index < nBwords; index++)
03487     {
03488       /*Transfer 32 bits from the JPEG output FIFO*/
03489       dataword = hjpeg->Instance->DOR;
03490       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
03491       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
03492       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
03493       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
03494       hjpeg->JpegOutCount += 4UL;
03495     }
03496     if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
03497     {
03498       /*Output Buffer is full, call DecodedDataReadyCallback*/
03499 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03500       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03501 #else
03502       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03503 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03504       hjpeg->JpegOutCount = 0;
03505     }
03506     else
03507     {
03508       nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
03509       dataword = hjpeg->Instance->DOR;
03510       for (index = 0; index < nbBytes; index++)
03511       {
03512         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
03513         hjpeg->JpegOutCount++;
03514       }
03515       /*Output Buffer is full, call DecodedDataReadyCallback*/
03516 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03517       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03518 #else
03519       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03520 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03521
03522       hjpeg->JpegOutCount = 0;
03523
03524       nbBytes = 4UL - nbBytes;
03525       for (index = nbBytes; index < 4UL; index++)
03526       {
03527         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
03528         hjpeg->JpegOutCount++;
03529       }
03530     }
03531   }
03532   else
03533   {
03534     /* Nothing to do */
03535   }
03536 }
03537
03538 /**
03539   * @brief  Read some input Data from the input buffer.
03540   *         This function is used when the JPEG peripheral needs new data
03541   *         in case of Polling or Interrupt process
03542   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03543   *         the configuration information for JPEG module
03544   * @param  nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request
03545   * @retval None
03546   */
03547 static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
03548 {
03549   uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
03550
03551   if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
03552   {
03553     /* No more Input data : nothing to do*/
03554     (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
03555   }
03556   else if (hjpeg->InDataLength > hjpeg->JpegInCount)
03557   {
03558     nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
03559   }
03560   else if (hjpeg->InDataLength == hjpeg->JpegInCount)
03561   {
03562     /*Call HAL_JPEG_GetDataCallback to get new data */
03563 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03564     hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
03565 #else
03566     HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
03567 #endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
03568
03569     if (hjpeg->InDataLength > 4UL)
03570     {
03571       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
03572     }
03573     hjpeg->JpegInCount = 0;
03574     nbBytes = hjpeg->InDataLength;
03575   }
03576   else
03577   {
03578     /* Nothing to do */
03579   }
03580   if (((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
03581   {
03582     nBwords = nbBytes / 4UL;
03583     if (nBwords >= nbRequestWords)
03584     {
03585       for (index = 0; index < nbRequestWords; index++)
03586       {
03587         inputCount = hjpeg->JpegInCount;
03588         hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
03589                                 (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
03590                                 (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
03591                                 (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
03592
03593         hjpeg->JpegInCount += 4UL;
03594       }
03595     }
03596     else /*nBwords < nbRequestWords*/
03597     {
03598       if (nBwords > 0UL)
03599       {
03600         for (index = 0; index < nBwords; index++)
03601         {
03602           inputCount = hjpeg->JpegInCount;
03603           hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
03604                                   (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
03605                                   (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
03606                                   (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
03607
03608           hjpeg->JpegInCount += 4UL;
03609         }
03610       }
03611       else
03612       {
03613         /* end of file*/
03614         Dataword = 0;
03615         for (index = 0; index < nbBytes; index++)
03616         {
03617           Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
03618           hjpeg->JpegInCount++;
03619         }
03620         hjpeg->Instance->DIR = Dataword;
03621       }
03622     }
03623   }
03624 }
03625
03626 /**
03627   * @brief  Start the JPEG DMA process (encoding/decoding)
03628   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03629   *         the configuration information for JPEG module
03630   * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
03631   */
03632 static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
03633 {
03634   uint32_t inXfrSize, outXfrSize;
03635
03636   /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
03637       then MDMA In buffer size is 32 bytes
03638     else (MDMA In is triggred with JPEG In FIFO not full flag)
03639       then MDMA In buffer size is 4 bytes
03640     */
03641   inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
03642
03643   /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
03644       then MDMA out buffer size is 32 bytes
03645     else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
03646       then MDMA buffer size is 4 bytes
03647     */
03648   outXfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
03649
03650   if ((hjpeg->InDataLength < inXfrSize) || (hjpeg->OutDataLength < outXfrSize))
03651   {
03652     return HAL_ERROR;
03653   }
03654   /* Set the JPEG MDMA In transfer complete callback */
03655   hjpeg->hdmain->XferCpltCallback = JPEG_MDMAInCpltCallback;
03656   /* Set the MDMA In error callback */
03657   hjpeg->hdmain->XferErrorCallback = JPEG_MDMAErrorCallback;
03658
03659   /* Set the JPEG MDMA Out transfer complete callback */
03660   hjpeg->hdmaout->XferCpltCallback = JPEG_MDMAOutCpltCallback;
03661   /* Set the MDMA In error callback */
03662   hjpeg->hdmaout->XferErrorCallback = JPEG_MDMAErrorCallback;
03663   /* Set the MDMA Out Abort callback */
03664   hjpeg->hdmaout->XferAbortCallback = JPEG_MDMAOutAbortCallback;
03665
03666   if ((inXfrSize == 0UL) || (outXfrSize == 0UL))
03667   {
03668     hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
03669     return HAL_ERROR;
03670   }
03671   /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
03672   hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
03673
03674   /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
03675   hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % outXfrSize);
03676
03677
03678   /* Start MDMA FIFO Out transfer */
03679   if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
03680                         hjpeg->OutDataLength, 1) != HAL_OK)
03681   {
03682     hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
03683     return HAL_ERROR;
03684   }
03685   /* Start DMA FIFO In transfer */
03686   if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
03687                         hjpeg->InDataLength, 1) != HAL_OK)
03688   {
03689     hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
03690     return HAL_ERROR;
03691   }
03692
03693   return HAL_OK;
03694 }
03695
03696 /**
03697   * @brief  Continue the current JPEG DMA process (encoding/decoding)
03698   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03699   *         the configuration information for JPEG module
03700   * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
03701   */
03702 static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
03703 {
03704   /*End of header processing flag rises*/
03705   if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03706   {
03707     if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
03708     {
03709       /*Call Header parsing complete callback */
03710       (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
03711
03712       /* Reset the ImageQuality */
03713       hjpeg->Conf.ImageQuality = 0;
03714       /* Note : the image quality is only available at the end of the decoding operation */
03715       /* at the current stage the calculated image quality is not correct so reset it */
03716
03717       /*Call Info Ready callback */
03718 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03719       hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
03720 #else
03721       HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
03722 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03723
03724       __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
03725
03726       /* Clear header processing done flag */
03727       __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
03728     }
03729   }
03730
03731   /*End of Conversion handling*/
03732   if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL)
03733   {
03734
03735     hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;
03736
03737     /*Stop Encoding/Decoding*/
03738     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03739
03740     __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
03741
03742     /* Clear all flags */
03743     __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
03744
03745     if (hjpeg->hdmain->State == HAL_MDMA_STATE_BUSY)
03746     {
03747       /* Stop the MDMA In Xfer*/
03748       (void) HAL_MDMA_Abort_IT(hjpeg->hdmain);
03749     }
03750
03751     if (hjpeg->hdmaout->State == HAL_MDMA_STATE_BUSY)
03752     {
03753       /* Stop the MDMA out Xfer*/
03754       (void) HAL_MDMA_Abort_IT(hjpeg->hdmaout);
03755     }
03756     else
03757     {
03758       JPEG_DMA_EndProcess(hjpeg);
03759     }
03760   }
03761
03762
03763 }
03764
03765 /**
03766   * @brief  Finalize the current JPEG DMA process (encoding/decoding)
03767   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03768   *         the configuration information for JPEG module
03769   * @retval JPEG_PROCESS_DONE
03770   */
03771 static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
03772 {
03773   uint32_t tmpContext;
03774   hjpeg->JpegOutCount = hjpeg->OutDataLength - (hjpeg->hdmaout->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
03775
03776   /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
03777   if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
03778   {
03779 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03780     hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03781 #else
03782     HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03783 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03784
03785     hjpeg->JpegOutCount = 0;
03786   }
03787
03788   /*Check if remaining data in the output FIFO*/
03789   if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL)
03790   {
03791     if (hjpeg->JpegOutCount > 0UL)
03792     {
03793       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
03794 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03795       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03796 #else
03797       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03798 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03799
03800       hjpeg->JpegOutCount = 0;
03801     }
03802
03803     /*Stop Encoding/Decoding*/
03804     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03805
03806     tmpContext = hjpeg->Context;
03807     /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
03808     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
03809
03810     /* Process Unlocked */
03811     __HAL_UNLOCK(hjpeg);
03812
03813     /* Change the JPEG state */
03814     hjpeg->State = HAL_JPEG_STATE_READY;
03815
03816     /*Call End of Encoding/Decoding callback */
03817     if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03818     {
03819 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03820       hjpeg->DecodeCpltCallback(hjpeg);
03821 #else
03822       HAL_JPEG_DecodeCpltCallback(hjpeg);
03823 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03824     }
03825     else /* JPEG_CONTEXT_ENCODE */
03826     {
03827 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03828       hjpeg->EncodeCpltCallback(hjpeg);
03829 #else
03830       HAL_JPEG_EncodeCpltCallback(hjpeg);
03831 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03832     }
03833   }
03834   else if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
03835   {
03836     JPEG_DMA_PollResidualData(hjpeg);
03837   }
03838   else
03839   {
03840     /* Nothing to do */
03841   }
03842
03843 }
03844
03845 /**
03846   * @brief  Poll residual output data when DMA process (encoding/decoding)
03847   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
03848   *         the configuration information for JPEG module
03849   * @retval None.
03850   */
03851 static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
03852 {
03853   uint32_t tmpContext, count, dataOut;
03854
03855   for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
03856   {
03857     if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
03858     {
03859       if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
03860       {
03861         dataOut = hjpeg->Instance->DOR;
03862         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL);
03863         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8);
03864         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16);
03865         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24);
03866         hjpeg->JpegOutCount += 4UL;
03867
03868         if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
03869         {
03870           /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
03871 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03872           hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03873 #else
03874           HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03875 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03876
03877           hjpeg->JpegOutCount = 0;
03878         }
03879
03880       }
03881     }
03882   }
03883
03884   tmpContext = hjpeg->Context;
03885
03886   if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL))
03887   {
03888     /*Stop Encoding/Decoding*/
03889     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03890
03891     if (hjpeg->JpegOutCount > 0UL)
03892     {
03893       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
03894 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03895       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03896 #else
03897       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03898 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03899
03900       hjpeg->JpegOutCount = 0;
03901     }
03902
03903     tmpContext = hjpeg->Context;
03904     /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
03905     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
03906
03907     /* Process Unlocked */
03908     __HAL_UNLOCK(hjpeg);
03909
03910     /* Change the JPEG state */
03911     hjpeg->State = HAL_JPEG_STATE_READY;
03912
03913     /*Call End of Encoding/Decoding callback */
03914     if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03915     {
03916 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03917       hjpeg->DecodeCpltCallback(hjpeg);
03918 #else
03919       HAL_JPEG_DecodeCpltCallback(hjpeg);
03920 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03921     }
03922     else /* JPEG_CONTEXT_ENCODE */
03923     {
03924 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03925       hjpeg->EncodeCpltCallback(hjpeg);
03926 #else
03927       HAL_JPEG_EncodeCpltCallback(hjpeg);
03928 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03929     }
03930   }
03931 }
03932
03933 /**
03934   * @brief  MDMA input transfer complete callback
03935   * @param  hmdma pointer to a MDMA_HandleTypeDef structure.
03936   * @retval None
03937   */
03938 static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma)
03939 {
03940   uint32_t inXfrSize;
03941
03942   JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent;
03943
03944   /* Disable The JPEG IT so the MDMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
03945   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
03946
03947   /* Check if context method is DMA and we are not in ending DMA stage */
03948   if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == JPEG_CONTEXT_DMA)
03949   {
03950
03951     /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
03952       then MDMA In buffer size is 32 bytes
03953       else (MDMA In is triggred with JPEG In FIFO not full flag)
03954       then MDMA In buffer size is 4 bytes
03955       */
03956     inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
03957
03958     hjpeg->JpegInCount = hjpeg->InDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
03959
03960     /*Call HAL_JPEG_GetDataCallback to get new data */
03961 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03962     hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
03963 #else
03964     HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
03965 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03966
03967
03968     if (hjpeg->InDataLength >= inXfrSize)
03969     {
03970       if (inXfrSize == 0UL)
03971       {
03972         hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
03973         hjpeg->State = HAL_JPEG_STATE_ERROR;
03974 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
03975         hjpeg->ErrorCallback(hjpeg);
03976 #else
03977         HAL_JPEG_ErrorCallback(hjpeg);
03978 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
03979         return;
03980       }
03981       /*JPEG Input MDMA transfer data number must be multiple of MDMA buffer size
03982         as the destination is a 32 bits register */
03983       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
03984
03985     }
03986     else if (hjpeg->InDataLength > 0UL)
03987     {
03988       /* Transfer the remaining Data, must be multiple of source data size (byte) and destination data size (word) */
03989       if ((hjpeg->InDataLength % 4UL) != 0UL)
03990       {
03991         hjpeg->InDataLength = ((hjpeg->InDataLength / 4UL) + 1UL) * 4UL;
03992       }
03993     }
03994     else
03995     {
03996       /* Nothing to do */
03997     }
03998
03999     if (((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL))
04000     {
04001       /* Start MDMA FIFO In transfer */
04002       if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
04003                             hjpeg->InDataLength, 1) != HAL_OK)
04004       {
04005         hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
04006         hjpeg->State = HAL_JPEG_STATE_ERROR;
04007 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
04008         hjpeg->ErrorCallback(hjpeg);
04009 #else
04010         HAL_JPEG_ErrorCallback(hjpeg);
04011 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
04012         return;
04013       }
04014     }
04015
04016     /* JPEG Conversion still on going : Enable the JPEG IT */
04017     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
04018   }
04019 }
04020
04021 /**
04022   * @brief  MDMA output transfer complete callback
04023   * @param  hmdma pointer to a MDMA_HandleTypeDef structure.
04024   * @retval None
04025   */
04026 static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma)
04027 {
04028   JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent;
04029
04030
04031   /* Disable The JPEG IT so the MDMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
04032   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
04033
04034   if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) ==
04035       JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */
04036   {
04037     if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL)
04038     {
04039       hjpeg->JpegOutCount = hjpeg->OutDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
04040
04041       /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
04042 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
04043       hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
04044 #else
04045       HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
04046 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
04047
04048       if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
04049       {
04050         /* Start MDMA FIFO Out transfer */
04051         if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
04052                               hjpeg->OutDataLength, 1) != HAL_OK)
04053         {
04054           hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
04055           hjpeg->State = HAL_JPEG_STATE_ERROR;
04056 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
04057           hjpeg->ErrorCallback(hjpeg);
04058 #else
04059           HAL_JPEG_ErrorCallback(hjpeg);
04060 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
04061           return;
04062         }
04063       }
04064     }
04065
04066     /* JPEG Conversion still on going : Enable the JPEG IT */
04067     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
04068   }
04069
04070 }
04071
04072 /**
04073   * @brief  MDMA Transfer error callback
04074   * @param  hmdma pointer to a MDMA_HandleTypeDef structure.
04075   * @retval None
04076   */
04077 static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma)
04078 {
04079   JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent;
04080
04081   /*Stop Encoding/Decoding*/
04082   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
04083
04084   /* Disable All Interrupts */
04085   __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
04086
04087   hjpeg->State = HAL_JPEG_STATE_READY;
04088   hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
04089
04090 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
04091   hjpeg->ErrorCallback(hjpeg);
04092 #else
04093   HAL_JPEG_ErrorCallback(hjpeg);
04094 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
04095 }
04096
04097 /**
04098   * @brief  MDMA output Abort callback
04099   * @param  hmdma pointer to a MDMA_HandleTypeDef structure.
04100   * @retval None
04101   */
04102 static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma)
04103 {
04104   JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent;
04105
04106   if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
04107   {
04108     JPEG_DMA_EndProcess(hjpeg);
04109   }
04110 }
04111
04112
04113 /**
04114   * @brief  Calculate the decoded image quality (from 1 to 100)
04115   * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
04116   *         the configuration information for JPEG module
04117   * @retval JPEG image quality from 1 to 100.
04118   */
04119 static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
04120 {
04121   uint32_t quality = 0;
04122   uint32_t quantRow, quantVal, scale, i, j;
04123   __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0;
04124
04125   i = 0;
04126   while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
04127   {
04128     quantRow = *tableAddress;
04129     for (j = 0; j < 4UL; j++)
04130     {
04131       quantVal = (quantRow >> (8UL * j)) & 0xFFUL;
04132       if (quantVal == 1UL)
04133       {
04134         /* if Quantization value = 1 then quality is 100%*/
04135         quality += 100UL;
04136       }
04137       else
04138       {
04139         /* Note that the quantization coefficients must be specified in the table in zigzag order */
04140         scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]);
04141
04142         if (scale <= 100UL)
04143         {
04144           quality += (200UL - scale) / 2UL;
04145         }
04146         else
04147         {
04148           quality += 5000UL / scale;
04149         }
04150       }
04151     }
04152
04153     i += 4UL;
04154     tableAddress ++;
04155   }
04156
04157   return (quality / 64UL);
04158 }
04159 /**
04160   * @}
04161   */
04162
04163 #endif /* JPEG */
04164 #endif /* HAL_JPEG_MODULE_ENABLED */
04165 /**
04166   * @}
04167   */
04168
04169 /**
04170   * @}
04171   */
04172
04173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_jpeg.h Source File

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stm32h7xx_hal_jpeg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_jpeg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of JPEG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_JPEG_H
00022 #define STM32H7xx_HAL_JPEG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (JPEG)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup JPEG
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup JPEG_Exported_Types JPEG Exported Types
00043   * @{
00044   */
00045
00046 /** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
00047   * @brief  JPEG encoding configuration Structure definition
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   uint32_t ColorSpace;               /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
00053                                            This parameter can be a value of @ref JPEG_ColorSpace */
00054
00055   uint32_t ChromaSubsampling;        /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
00056                                            This parameter can be a value of @ref JPEG_ChromaSubsampling */
00057
00058   uint32_t ImageHeight;              /*!< Image height : number of lines */
00059
00060   uint32_t ImageWidth;               /*!< Image width : number of pixels per line */
00061
00062   uint32_t ImageQuality;             /*!< Quality of the JPEG encoding : from 1 to 100 */
00063
00064 } JPEG_ConfTypeDef;
00065 /**
00066   * @}
00067   */
00068
00069 /** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
00070   * @brief  HAL JPEG State structure definition
00071   * @{
00072   */
00073 typedef enum
00074 {
00075   HAL_JPEG_STATE_RESET              = 0x00U,  /*!< JPEG not yet initialized or disabled  */
00076   HAL_JPEG_STATE_READY              = 0x01U,  /*!< JPEG initialized and ready for use    */
00077   HAL_JPEG_STATE_BUSY               = 0x02U,  /*!< JPEG internal processing is ongoing   */
00078   HAL_JPEG_STATE_BUSY_ENCODING      = 0x03U,  /*!< JPEG encoding processing is ongoing   */
00079   HAL_JPEG_STATE_BUSY_DECODING      = 0x04U,  /*!< JPEG decoding processing is ongoing   */
00080   HAL_JPEG_STATE_TIMEOUT            = 0x05U,  /*!< JPEG timeout state                    */
00081   HAL_JPEG_STATE_ERROR              = 0x06U   /*!< JPEG error state                      */
00082 } HAL_JPEG_STATETypeDef;
00083
00084 /**
00085   * @}
00086   */
00087
00088
00089 /** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
00090   * @brief  JPEG handle Structure definition
00091   * @{
00092   */
00093 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00094 typedef struct __JPEG_HandleTypeDef
00095 #else
00096 typedef struct
00097 #endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
00098 {
00099   JPEG_TypeDef             *Instance;        /*!< JPEG peripheral register base address */
00100
00101   JPEG_ConfTypeDef         Conf;             /*!< Current JPEG encoding/decoding parameters */
00102
00103   uint8_t                  *pJpegInBuffPtr;  /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
00104
00105   uint8_t                  *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
00106
00107   __IO uint32_t            JpegInCount;      /*!< Internal Counter of input data */
00108
00109   __IO uint32_t            JpegOutCount;     /*!< Internal Counter of output data */
00110
00111   uint32_t                 InDataLength;     /*!< Input Buffer Length in Bytes */
00112
00113   uint32_t                 OutDataLength;    /*!< Output Buffer Length in Bytes */
00114
00115   MDMA_HandleTypeDef        *hdmain;          /*!< JPEG In MDMA handle parameters */
00116
00117   MDMA_HandleTypeDef        *hdmaout;         /*!< JPEG Out MDMA handle parameters */
00118
00119   uint8_t                  CustomQuanTable;  /*!< If set to 1 specify that user customized quantization tables are used */
00120
00121   uint8_t                  *QuantTable0;     /*!< Basic Quantization Table for component 0 */
00122
00123   uint8_t                  *QuantTable1;     /*!< Basic Quantization Table for component 1 */
00124
00125   uint8_t                  *QuantTable2;     /*!< Basic Quantization Table for component 2 */
00126
00127   uint8_t                  *QuantTable3;     /*!< Basic Quantization Table for component 3 */
00128
00129   HAL_LockTypeDef          Lock;             /*!< JPEG locking object */
00130
00131   __IO  HAL_JPEG_STATETypeDef State;         /*!< JPEG peripheral state */
00132
00133   __IO  uint32_t           ErrorCode;        /*!< JPEG Error code */
00134
00135   __IO uint32_t Context;                     /*!< JPEG Internal context */
00136
00137 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00138   void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg,
00139                             JPEG_ConfTypeDef *pInfo);  /*!< JPEG Info ready callback      */
00140   void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef
00141                              *hjpeg);                          /*!< JPEG Encode complete callback */
00142   void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef
00143                              *hjpeg);                          /*!< JPEG Decode complete callback */
00144   void (*ErrorCallback)(struct __JPEG_HandleTypeDef
00145                         *hjpeg);                               /*!< JPEG Error callback           */
00146   void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg,
00147                           uint32_t NbDecodedData);     /*!< JPEG Get Data callback        */
00148   void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
00149                             uint32_t OutDataLength);   /*!< JPEG Data ready callback */
00150
00151   void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg);                            /*!< JPEG Msp Init callback  */
00152   void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef
00153                              *hjpeg);                          /*!< JPEG Msp DeInit callback  */
00154
00155
00156 #endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
00157
00158
00159 } JPEG_HandleTypeDef;
00160 /**
00161   * @}
00162   */
00163
00164
00165 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00166 /** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition
00167   * @brief  HAL JPEG Callback ID enumeration definition
00168   * @{
00169   */
00170 typedef enum
00171 {
00172   HAL_JPEG_ENCODE_CPLT_CB_ID    = 0x01U,    /*!< JPEG Encode Complete callback ID */
00173   HAL_JPEG_DECODE_CPLT_CB_ID    = 0x02U,    /*!< JPEG Decode Complete callback ID */
00174   HAL_JPEG_ERROR_CB_ID          = 0x03U,    /*!< JPEG Error callback ID           */
00175
00176   HAL_JPEG_MSPINIT_CB_ID        = 0x04U,    /*!< JPEG MspInit callback ID         */
00177   HAL_JPEG_MSPDEINIT_CB_ID      = 0x05U     /*!< JPEG MspDeInit callback ID       */
00178
00179 } HAL_JPEG_CallbackIDTypeDef;
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition
00185   * @brief  HAL JPEG Callback pointer definition
00186   * @{
00187   */
00188 typedef  void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg);    /*!< pointer to a common JPEG callback function */
00189 typedef  void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
00190                                                 JPEG_ConfTypeDef *pInfo);  /*!< pointer to an Info ready JPEG callback function */
00191 typedef  void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
00192                                               uint32_t NbDecodedData);     /*!< pointer to a Get data JPEG callback function */
00193 typedef  void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
00194                                                 uint32_t OutDataLength);  /*!< pointer to a Data ready JPEG callback function */
00195 /**
00196   * @}
00197   */
00198
00199 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /* Exported constants --------------------------------------------------------*/
00206
00207 /** @defgroup JPEG_Exported_Constants JPEG Exported Constants
00208   * @{
00209   */
00210
00211 /** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
00212   * @brief  JPEG Error Code definition
00213   * @{
00214   */
00215
00216 #define  HAL_JPEG_ERROR_NONE        ((uint32_t)0x00000000U)    /*!< No error             */
00217 #define  HAL_JPEG_ERROR_HUFF_TABLE  ((uint32_t)0x00000001U)    /*!< HUffman Table programming error */
00218 #define  HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)    /*!< Quantization Table programming error */
00219 #define  HAL_JPEG_ERROR_DMA         ((uint32_t)0x00000004U)    /*!< DMA transfer error   */
00220 #define  HAL_JPEG_ERROR_TIMEOUT     ((uint32_t)0x00000008U)    /*!< Timeout error        */
00221 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00222 #define  HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)    /*!< Invalid Callback error  */
00223 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
00229   * @brief  JPEG Quantization Table Size
00230   * @{
00231   */
00232 #define JPEG_QUANT_TABLE_SIZE  ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes  */
00233 /**
00234   * @}
00235   */
00236
00237
00238 /** @defgroup JPEG_ColorSpace JPEG ColorSpace
00239   * @brief  JPEG Color Space
00240   * @{
00241   */
00242 #define JPEG_GRAYSCALE_COLORSPACE     ((uint32_t)0x00000000U)
00243 #define JPEG_YCBCR_COLORSPACE         JPEG_CONFR1_COLORSPACE_0
00244 #define JPEG_CMYK_COLORSPACE          JPEG_CONFR1_COLORSPACE
00245
00246
00247 /**
00248   * @}
00249   */
00250
00251
00252 /** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
00253   * @brief  JPEG Chrominance Sampling
00254   * @{
00255   */
00256 #define JPEG_444_SUBSAMPLING     ((uint32_t)0x00000000U)   /*!< Chroma Subsampling 4:4:4 */
00257 #define JPEG_420_SUBSAMPLING     ((uint32_t)0x00000001U)   /*!< Chroma Subsampling 4:2:0 */
00258 #define JPEG_422_SUBSAMPLING     ((uint32_t)0x00000002U)   /*!< Chroma Subsampling 4:2:2 */
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup JPEG_ImageQuality JPEG Image Quality
00265   * @brief  JPEG Min and Max Image Quality
00266   * @{
00267   */
00268 #define JPEG_IMAGE_QUALITY_MIN     ((uint32_t)1U)     /*!< Minimum JPEG quality */
00269 #define JPEG_IMAGE_QUALITY_MAX     ((uint32_t)100U)   /*!< Maximum JPEG quality */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
00276   * @brief JPEG Interrupt definition
00277   * @{
00278   */
00279 #define JPEG_IT_IFT     ((uint32_t)JPEG_CR_IFTIE)   /*!< Input FIFO Threshold Interrupt */
00280 #define JPEG_IT_IFNF    ((uint32_t)JPEG_CR_IFNFIE)  /*!< Input FIFO Not Full Interrupt */
00281 #define JPEG_IT_OFT     ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Threshold Interrupt */
00282 #define JPEG_IT_OFNE    ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Not Empty Interrupt */
00283 #define JPEG_IT_EOC     ((uint32_t)JPEG_CR_EOCIE)   /*!< End of Conversion Interrupt */
00284 #define JPEG_IT_HPD     ((uint32_t)JPEG_CR_HPDIE)   /*!< Header Parsing Done Interrupt */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup JPEG_Flag_definition JPEG Flag definition
00290   * @brief JPEG Flags definition
00291   * @{
00292   */
00293 #define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is bellow its threshold flag */
00294 #define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */
00295 #define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */
00296 #define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */
00297 #define JPEG_FLAG_EOCF     ((uint32_t)JPEG_SR_EOCF)   /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO  */
00298 #define JPEG_FLAG_HPDF     ((uint32_t)JPEG_SR_HPDF)   /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated  */
00299 #define JPEG_FLAG_COF      ((uint32_t)JPEG_SR_COF)    /*!< JPEG Codec operation on going  flag*/
00300
00301 #define JPEG_FLAG_ALL      ((uint32_t)0x000000FEU)     /*!< JPEG Codec All previous flag*/
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
00307   * @brief JPEG process pause, resume definition
00308   * @{
00309   */
00310 #define JPEG_PAUSE_RESUME_INPUT          ((uint32_t)0x00000001U)     /*!< Pause/Resume Input FIFO Xfer*/
00311 #define JPEG_PAUSE_RESUME_OUTPUT         ((uint32_t)0x00000002U)     /*!< Pause/Resume Output FIFO Xfer*/
00312 #define JPEG_PAUSE_RESUME_INPUT_OUTPUT   ((uint32_t)0x00000003U)     /*!< Pause/Resume Input and Output FIFO Xfer*/
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320 /* Exported macro ------------------------------------------------------------*/
00321
00322 /** @defgroup JPEG_Exported_Macros JPEG Exported Macros
00323   * @{
00324   */
00325
00326 /** @brief Reset JPEG handle state
00327   * @param  __HANDLE__ specifies the JPEG handle.
00328   * @retval None
00329   */
00330 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00331 #define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\
00332                                                       (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\
00333                                                       (__HANDLE__)->MspInitCallback = NULL;\
00334                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00335                                                       }while(0)
00336 #else
00337 #define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
00338 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00339
00340
00341 /**
00342   * @brief  Enable the JPEG peripheral.
00343   * @param  __HANDLE__ specifies the JPEG handle.
00344   * @retval None
00345   */
00346 #define __HAL_JPEG_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  JPEG_CR_JCEN)
00347
00348 /**
00349   * @brief Disable the JPEG peripheral.
00350   * @param  __HANDLE__ specifies the JPEG handle.
00351   * @retval None
00352   */
00353 #define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~JPEG_CR_JCEN)
00354
00355
00356 /**
00357   * @brief  Check the specified JPEG status flag.
00358   * @param  __HANDLE__ specifies the JPEG handle.
00359   * @param  __FLAG__  specifies the flag to check
00360   *         This parameter can be one of the following values:
00361   *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is bellow its threshold flag
00362   *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
00363   *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold
00364   *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
00365   *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
00366   *                                and than last data has been sent to the output FIFO
00367   *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
00368   *                                and the internal registers have been updated
00369   *         @arg JPEG_FLAG_COF   : JPEG Codec operation on going  flag
00370   *
00371   * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
00372   */
00373
00374 #define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->SR & (__FLAG__)))
00375
00376 /**
00377   * @brief  Clear the specified JPEG status flag.
00378   * @param  __HANDLE__ specifies the JPEG handle.
00379   * @param  __FLAG__  specifies the flag to clear
00380   *         This parameter can be one of the following values:
00381   *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
00382   *                                and than last data has been sent to the output FIFO
00383   *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
00384   * @retval None
00385   */
00386
00387 #define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
00388
00389
00390 /**
00391   * @brief  Enable Interrupt.
00392   * @param   __HANDLE__ specifies the JPEG handle.
00393   * @param  __INTERRUPT__  specifies the interrupt to enable
00394   *         This parameter can be one of the following values:
00395   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00396   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00397   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00398   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00399   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00400   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00401   *
00402   * @retval No retrun
00403   */
00404 #define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
00405
00406 /**
00407   * @brief  Disable Interrupt.
00408   * @param   __HANDLE__ specifies the JPEG handle.
00409   * @param  __INTERRUPT__ specifies the interrupt to disable
00410   *         This parameter can be one of the following values:
00411   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00412   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00413   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00414   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00415   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00416   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00417   *
00418   * @note    To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
00419   *          located in the same IT enable register (CR register).
00420   * @retval  No retrun
00421   */
00422 #define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
00423
00424
00425 /**
00426   * @brief  Get Interrupt state.
00427   * @param   __HANDLE__ specifies the JPEG handle.
00428   * @param  __INTERRUPT__  specifies the interrupt to check
00429   *         This parameter can be one of the following values:
00430   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00431   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00432   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00433   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00434   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00435   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00436   *
00437   * @retval returns The new state of __INTERRUPT__ (Enabled or disabled)
00438   */
00439 #define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__)     ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00440
00441 /**
00442   * @}
00443   */
00444
00445 /* Exported functions --------------------------------------------------------*/
00446 /** @addtogroup JPEG_Exported_Functions
00447   * @{
00448   */
00449
00450 /** @addtogroup JPEG_Exported_Functions_Group1
00451   * @{
00452   */
00453 /* Initialization/de-initialization functions  ********************************/
00454 HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
00455 HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
00456 void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
00457 void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
00458
00459 #if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
00460 HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
00461                                             pJPEG_CallbackTypeDef pCallback);
00462 HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID);
00463
00464 HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
00465                                                      pJPEG_InfoReadyCallbackTypeDef pCallback);
00466 HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg);
00467
00468 HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback);
00469 HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg);
00470
00471 HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
00472                                                      pJPEG_DataReadyCallbackTypeDef pCallback);
00473 HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg);
00474
00475 #endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
00476
00477 /**
00478   * @}
00479   */
00480
00481 /** @addtogroup JPEG_Exported_Functions_Group2
00482   * @{
00483   */
00484 /* Encoding/Decoding Configuration functions  ********************************/
00485 HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
00486 HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
00487 HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
00488 HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
00489 HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
00490                                               uint8_t *QTable2, uint8_t *QTable3);
00491
00492 /**
00493   * @}
00494   */
00495
00496 /** @addtogroup JPEG_Exported_Functions_Group3
00497   * @{
00498   */
00499 /* JPEG processing functions  **************************************/
00500 HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
00501                                    uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
00502 HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
00503                                    uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout);
00504 HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
00505                                       uint8_t *pDataOut, uint32_t OutDataLength);
00506 HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
00507                                       uint8_t *pDataOutMCU, uint32_t OutDataLength);
00508 HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
00509                                        uint8_t *pDataOut, uint32_t OutDataLength);
00510 HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
00511                                        uint8_t *pDataOutMCU, uint32_t OutDataLength);
00512 HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
00513 HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
00514 void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
00515 void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
00516 HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @addtogroup JPEG_Exported_Functions_Group4
00523   * @{
00524   */
00525 /* JPEG Decode/Encode callback functions  ********************************************************/
00526 void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
00527 void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
00528 void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
00529 void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
00530 void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
00531 void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
00532
00533 /**
00534   * @}
00535   */
00536
00537 /** @addtogroup JPEG_Exported_Functions_Group5
00538   * @{
00539   */
00540 /* JPEG IRQ handler management  ******************************************************/
00541 void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
00542
00543 /**
00544   * @}
00545   */
00546
00547 /** @addtogroup JPEG_Exported_Functions_Group6
00548   * @{
00549   */
00550 /* Peripheral State and Error functions  ************************************************/
00551 HAL_JPEG_STATETypeDef  HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
00552 uint32_t               HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
00553
00554 /**
00555   * @}
00556   */
00557
00558 /**
00559   * @}
00560   */
00561
00562 /* Private types -------------------------------------------------------------*/
00563 /** @defgroup JPEG_Private_Types JPEG Private Types
00564   * @{
00565   */
00566
00567 /**
00568   * @}
00569   */
00570
00571 /* Private defines -----------------------------------------------------------*/
00572 /** @defgroup JPEG_Private_Defines JPEG Private Defines
00573   * @{
00574   */
00575
00576 /**
00577   * @}
00578   */
00579
00580 /* Private variables ---------------------------------------------------------*/
00581 /** @defgroup JPEG_Private_Variables JPEG Private Variables
00582   * @{
00583   */
00584
00585 /**
00586   * @}
00587   */
00588
00589 /* Private constants ---------------------------------------------------------*/
00590 /** @defgroup JPEG_Private_Constants JPEG Private Constants
00591   * @{
00592   */
00593
00594 /**
00595   * @}
00596   */
00597
00598 /* Private macros ------------------------------------------------------------*/
00599 /** @defgroup JPEG_Private_Macros JPEG Private Macros
00600   * @{
00601   */
00602
00603 #define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
00604                                                 ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
00605                                                 ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
00606
00607 #define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
00608
00609 #define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
00610                                         ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \
00611                                         ((COLORSPACE) == JPEG_CMYK_COLORSPACE))
00612
00613 #define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
00614                                            ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
00615                                            ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
00616
00617 /**
00618   * @}
00619   */
00620
00621 /* Private functions prototypes ----------------------------------------------*/
00622 /** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
00623   * @{
00624   */
00625
00626 /**
00627   * @}
00628   */
00629
00630 /* Private functions ---------------------------------------------------------*/
00631 /** @defgroup JPEG_Private_Functions JPEG Private Functions
00632   * @{
00633   */
00634
00635 /**
00636   * @}
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /**
00644   * @}
00645   */
00646
00647 #endif /* JPEG */
00648
00649 #ifdef __cplusplus
00650 }
00651 #endif
00652
00653 #endif /* STM32H7xx_HAL_JPEG_H */
00654
00655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_lptim.c Source File

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stm32h7xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00008   *           + Initialization and de-initialization functions.
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Reading operation functions.
00012   *           + Peripheral State functions.
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The LPTIM HAL driver can be used as follows:
00020
00021       (#)Initialize the LPTIM low level resources by implementing the
00022         HAL_LPTIM_MspInit():
00023          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00024          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00025              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00026              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00027              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00028
00029       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00030          configures mainly:
00031          (++) The instance: LPTIM1 or LPTIM2.
00032          (++) Clock: the counter clock.
00033              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00034                               the internal clock; (APB, LSE, LSI or MSI).
00035              (+++) Prescaler: select the clock divider.
00036          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00037                as counter clock source.
00038              (+++) Polarity:   polarity of the active edge for the counter unit
00039                                if the ULPTIM input is selected.
00040              (+++) SampleTime: clock sampling time to configure the clock glitch
00041                                filter.
00042          (++) Trigger: How the counter start.
00043              (+++) Source: trigger can be software or one of the hardware triggers.
00044              (+++) ActiveEdge : only for hardware trigger.
00045              (+++) SampleTime : trigger sampling time to configure the trigger
00046                                 glitch filter.
00047          (++) OutputPolarity : 2 opposite polarities are possible.
00048          (++) UpdateMode: specifies whether the update of the autoreload and
00049               the compare values is done immediately or after the end of current
00050               period.
00051          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00052          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00053               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00054
00055       (#)Six modes are available:
00056
00057          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00058          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00059          mode.
00060
00061          (++) One Pulse Mode: To generate pulse with specified width in response
00062          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00063          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00064
00065          (++) Set once Mode: In this mode, the output changes the level (from
00066          low level to high level if the output polarity is configured high, else
00067          the opposite) when a compare match occurs. To start this mode, call
00068          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00069          interruption mode.
00070
00071          (++) Encoder Mode: To use the encoder interface call
00072          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00073          interruption mode. Only available for LPTIM1 instance.
00074
00075          (++) Time out Mode: an active edge on one selected trigger input rests
00076          the counter. The first trigger event will start the timer, any
00077          successive trigger event will reset the counter and the timer will
00078          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00079          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00080
00081          (++) Counter Mode: counter can be used to count external events on
00082          the LPTIM Input1 or it can be used to count internal clock cycles.
00083          To start this mode, call HAL_LPTIM_Counter_Start() or
00084          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00085
00086
00087       (#) User can stop any process by calling the corresponding API:
00088           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00089           already started in interruption mode.
00090
00091       (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00092
00093     *** Callback registration ***
00094   =============================================
00095   [..]
00096   The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
00097   allows the user to configure dynamically the driver callbacks.
00098   [..]
00099   Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
00100   @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00101   the Callback ID and a pointer to the user callback function.
00102   [..]
00103   Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
00104   default weak function.
00105   @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00106   and the Callback ID.
00107   [..]
00108   These functions allow to register/unregister following callbacks:
00109
00110     (+) MspInitCallback         : LPTIM Base Msp Init Callback.
00111     (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
00112     (+) CompareMatchCallback    : Compare match Callback.
00113     (+) AutoReloadMatchCallback : Auto-reload match Callback.
00114     (+) TriggerCallback         : External trigger event detection Callback.
00115     (+) CompareWriteCallback    : Compare register write complete Callback.
00116     (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
00117     (+) DirectionUpCallback     : Up-counting direction change Callback.
00118     (+) DirectionDownCallback   : Down-counting direction change Callback.
00119
00120   [..]
00121   By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
00122   all interrupt callbacks are set to the corresponding weak functions:
00123   examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
00124
00125   [..]
00126   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00127   functionalities in the Init/DeInit only when these callbacks are null
00128   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
00129   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00130
00131   [..]
00132   Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
00133   Exception done MspInit/MspDeInit that can be registered/unregistered
00134   in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
00135   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00136   In that case first register the MspInit/MspDeInit user callbacks
00137   using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
00138
00139   [..]
00140   When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
00141   not defined, the callback registration feature is not available and all callbacks
00142   are set to the corresponding weak functions.
00143
00144   @endverbatim
00145   ******************************************************************************
00146   * @attention
00147   *
00148   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00149   * All rights reserved.</center></h2>
00150   *
00151   * This software component is licensed by ST under BSD 3-Clause license,
00152   * the "License"; You may not use this file except in compliance with the
00153   * License. You may obtain a copy of the License at:
00154   *                        opensource.org/licenses/BSD-3-Clause
00155   *
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32h7xx_hal.h"
00161
00162 /** @addtogroup STM32H7xx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup LPTIM LPTIM
00167   * @brief LPTIM HAL module driver.
00168   * @{
00169   */
00170
00171 #ifdef HAL_LPTIM_MODULE_ENABLED
00172
00173 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /* Private macro -------------------------------------------------------------*/
00178 /** @addtogroup LPTIM_Private_Constants
00179   * @{
00180   */
00181 #define TIMEOUT                                     1000UL /* Timeout is 1s */
00182 /**
00183   * @}
00184   */
00185
00186 /* Private variables ---------------------------------------------------------*/
00187 /* Private function prototypes -----------------------------------------------*/
00188 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00189 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
00190 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00191 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
00192
00193 /* Exported functions --------------------------------------------------------*/
00194
00195 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00196   * @{
00197   */
00198
00199 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00200  *  @brief    Initialization and Configuration functions.
00201  *
00202 @verbatim
00203   ==============================================================================
00204               ##### Initialization and de-initialization functions #####
00205   ==============================================================================
00206     [..]  This section provides functions allowing to:
00207       (+) Initialize the LPTIM according to the specified parameters in the
00208           LPTIM_InitTypeDef and initialize the associated handle.
00209       (+) DeInitialize the LPTIM peripheral.
00210       (+) Initialize the LPTIM MSP.
00211       (+) DeInitialize the LPTIM MSP.
00212
00213 @endverbatim
00214   * @{
00215   */
00216
00217 /**
00218   * @brief  Initialize the LPTIM according to the specified parameters in the
00219   *         LPTIM_InitTypeDef and initialize the associated handle.
00220   * @param  hlptim LPTIM handle
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00224 {
00225   uint32_t tmpcfgr;
00226
00227   /* Check the LPTIM handle allocation */
00228   if (hlptim == NULL)
00229   {
00230     return HAL_ERROR;
00231   }
00232
00233   /* Check the parameters */
00234   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00235
00236   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00237   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00238   if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
00239   {
00240     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00241     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00242   }
00243   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00244   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00245   {
00246     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00247     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00248   }
00249   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00250   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00251   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00252
00253   if (hlptim->State == HAL_LPTIM_STATE_RESET)
00254   {
00255     /* Allocate lock resource and initialize it */
00256     hlptim->Lock = HAL_UNLOCKED;
00257
00258 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00259     /* Reset interrupt callbacks to legacy weak callbacks */
00260     LPTIM_ResetCallback(hlptim);
00261
00262     if (hlptim->MspInitCallback == NULL)
00263     {
00264       hlptim->MspInitCallback = HAL_LPTIM_MspInit;
00265     }
00266
00267     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00268     hlptim->MspInitCallback(hlptim);
00269 #else
00270     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00271     HAL_LPTIM_MspInit(hlptim);
00272 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00273   }
00274
00275   /* Change the LPTIM state */
00276   hlptim->State = HAL_LPTIM_STATE_BUSY;
00277
00278   /* Get the LPTIMx CFGR value */
00279   tmpcfgr = hlptim->Instance->CFGR;
00280
00281   if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
00282   {
00283     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00284   }
00285   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00286   {
00287     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00288   }
00289
00290   /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00291   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00292                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
00293
00294   /* Set initialization parameters */
00295   tmpcfgr |= (hlptim->Init.Clock.Source    |
00296               hlptim->Init.Clock.Prescaler |
00297               hlptim->Init.OutputPolarity  |
00298               hlptim->Init.UpdateMode      |
00299               hlptim->Init.CounterSource);
00300
00301   if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
00302   {
00303     tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
00304                 hlptim->Init.UltraLowPowerClock.SampleTime);
00305   }
00306
00307   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00308   {
00309     /* Enable External trigger and set the trigger source */
00310     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00311                 hlptim->Init.Trigger.ActiveEdge |
00312                 hlptim->Init.Trigger.SampleTime);
00313   }
00314
00315   /* Write to LPTIMx CFGR */
00316   hlptim->Instance->CFGR = tmpcfgr;
00317
00318   /* Configure LPTIM input sources */
00319  if ((hlptim->Instance == LPTIM1)||(hlptim->Instance == LPTIM2))
00320   {
00321     /* Check LPTIM Input1 and Input2 sources */
00322     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00323     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
00324
00325     /* Configure LPTIM Input1 and Input2 sources */
00326     hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00327   }
00328   else
00329   {
00330     if(hlptim->Instance == LPTIM3)
00331     {
00332       /* Check LPTIM3 Input1 source */
00333       assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00334
00335       /* Configure LPTIM3 Input1 source */
00336       hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
00337     }
00338   }
00339
00340   /* Change the LPTIM state */
00341   hlptim->State = HAL_LPTIM_STATE_READY;
00342
00343   /* Return function status */
00344   return HAL_OK;
00345 }
00346
00347 /**
00348   * @brief  DeInitialize the LPTIM peripheral.
00349   * @param  hlptim LPTIM handle
00350   * @retval HAL status
00351   */
00352 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00353 {
00354   /* Check the LPTIM handle allocation */
00355   if (hlptim == NULL)
00356   {
00357     return HAL_ERROR;
00358   }
00359
00360   /* Change the LPTIM state */
00361   hlptim->State = HAL_LPTIM_STATE_BUSY;
00362
00363   /* Disable the LPTIM Peripheral Clock */
00364   __HAL_LPTIM_DISABLE(hlptim);
00365
00366   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00367   {
00368     return HAL_TIMEOUT;
00369   }
00370
00371 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00372   if (hlptim->MspDeInitCallback == NULL)
00373   {
00374     hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
00375   }
00376
00377   /* DeInit the low level hardware: CLOCK, NVIC.*/
00378   hlptim->MspDeInitCallback(hlptim);
00379 #else
00380   /* DeInit the low level hardware: CLOCK, NVIC.*/
00381   HAL_LPTIM_MspDeInit(hlptim);
00382 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00383
00384   /* Change the LPTIM state */
00385   hlptim->State = HAL_LPTIM_STATE_RESET;
00386
00387   /* Release Lock */
00388   __HAL_UNLOCK(hlptim);
00389
00390   /* Return function status */
00391   return HAL_OK;
00392 }
00393
00394 /**
00395   * @brief  Initialize the LPTIM MSP.
00396   * @param  hlptim LPTIM handle
00397   * @retval None
00398   */
00399 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00400 {
00401   /* Prevent unused argument(s) compilation warning */
00402   UNUSED(hlptim);
00403
00404   /* NOTE : This function should not be modified, when the callback is needed,
00405             the HAL_LPTIM_MspInit could be implemented in the user file
00406    */
00407 }
00408
00409 /**
00410   * @brief  DeInitialize LPTIM MSP.
00411   * @param  hlptim LPTIM handle
00412   * @retval None
00413   */
00414 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00415 {
00416   /* Prevent unused argument(s) compilation warning */
00417   UNUSED(hlptim);
00418
00419   /* NOTE : This function should not be modified, when the callback is needed,
00420             the HAL_LPTIM_MspDeInit could be implemented in the user file
00421    */
00422 }
00423
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00429  *  @brief   Start-Stop operation functions.
00430  *
00431 @verbatim
00432   ==============================================================================
00433                 ##### LPTIM Start Stop operation functions #####
00434   ==============================================================================
00435     [..]  This section provides functions allowing to:
00436       (+) Start the PWM mode.
00437       (+) Stop the PWM mode.
00438       (+) Start the One pulse mode.
00439       (+) Stop the One pulse mode.
00440       (+) Start the Set once mode.
00441       (+) Stop the Set once mode.
00442       (+) Start the Encoder mode.
00443       (+) Stop the Encoder mode.
00444       (+) Start the Timeout mode.
00445       (+) Stop the Timeout mode.
00446       (+) Start the Counter mode.
00447       (+) Stop the Counter mode.
00448
00449
00450 @endverbatim
00451   * @{
00452   */
00453
00454 /**
00455   * @brief  Start the LPTIM PWM generation.
00456   * @param  hlptim LPTIM handle
00457   * @param  Period Specifies the Autoreload value.
00458   *         This parameter must be a value between 0x0000 and 0xFFFF.
00459   * @param  Pulse Specifies the compare value.
00460   *         This parameter must be a value between 0x0000 and 0xFFFF.
00461   * @retval HAL status
00462   */
00463 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00464 {
00465   /* Check the parameters */
00466   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00467   assert_param(IS_LPTIM_PERIOD(Period));
00468   assert_param(IS_LPTIM_PULSE(Pulse));
00469
00470   /* Set the LPTIM state */
00471   hlptim->State = HAL_LPTIM_STATE_BUSY;
00472
00473   /* Reset WAVE bit to set PWM mode */
00474   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00475
00476   /* Enable the Peripheral */
00477   __HAL_LPTIM_ENABLE(hlptim);
00478
00479   /* Clear flag */
00480   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00481
00482   /* Load the period value in the autoreload register */
00483   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00484
00485   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00486   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00487   {
00488     return HAL_TIMEOUT;
00489   }
00490
00491   /* Clear flag */
00492   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00493
00494   /* Load the pulse value in the compare register */
00495   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00496
00497   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00498   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00499   {
00500     return HAL_TIMEOUT;
00501   }
00502
00503   /* Start timer in continuous mode */
00504   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00505
00506   /* Change the TIM state*/
00507   hlptim->State = HAL_LPTIM_STATE_READY;
00508
00509   /* Return function status */
00510   return HAL_OK;
00511 }
00512
00513 /**
00514   * @brief  Stop the LPTIM PWM generation.
00515   * @param  hlptim LPTIM handle
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00519 {
00520   /* Check the parameters */
00521   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00522
00523   /* Set the LPTIM state */
00524   hlptim->State = HAL_LPTIM_STATE_BUSY;
00525
00526   /* Disable the Peripheral */
00527   __HAL_LPTIM_DISABLE(hlptim);
00528
00529   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00530   {
00531     return HAL_TIMEOUT;
00532   }
00533
00534   /* Change the TIM state*/
00535   hlptim->State = HAL_LPTIM_STATE_READY;
00536
00537   /* Return function status */
00538   return HAL_OK;
00539 }
00540
00541 /**
00542   * @brief  Start the LPTIM PWM generation in interrupt mode.
00543   * @param  hlptim LPTIM handle
00544   * @param  Period Specifies the Autoreload value.
00545   *         This parameter must be a value between 0x0000 and 0xFFFF
00546   * @param  Pulse Specifies the compare value.
00547   *         This parameter must be a value between 0x0000 and 0xFFFF
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00551 {
00552   /* Check the parameters */
00553   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00554   assert_param(IS_LPTIM_PERIOD(Period));
00555   assert_param(IS_LPTIM_PULSE(Pulse));
00556
00557   /* Set the LPTIM state */
00558   hlptim->State = HAL_LPTIM_STATE_BUSY;
00559
00560   /* Reset WAVE bit to set PWM mode */
00561   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00562
00563   /* Enable the Peripheral */
00564   __HAL_LPTIM_ENABLE(hlptim);
00565
00566   /* Clear flag */
00567   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00568
00569   /* Load the period value in the autoreload register */
00570   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00571
00572   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00573   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00574   {
00575     return HAL_TIMEOUT;
00576   }
00577
00578   /* Clear flag */
00579   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00580
00581   /* Load the pulse value in the compare register */
00582   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00583
00584   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00585   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00586   {
00587     return HAL_TIMEOUT;
00588   }
00589
00590   /* Disable the Peripheral */
00591   __HAL_LPTIM_DISABLE(hlptim);
00592
00593   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00594   {
00595     return HAL_TIMEOUT;
00596   }
00597
00598   /* Enable Autoreload write complete interrupt */
00599   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00600
00601   /* Enable Compare write complete interrupt */
00602   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00603
00604   /* Enable Autoreload match interrupt */
00605   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00606
00607   /* Enable Compare match interrupt */
00608   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00609
00610   /* If external trigger source is used, then enable external trigger interrupt */
00611   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00612   {
00613     /* Enable external trigger interrupt */
00614     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00615   }
00616
00617   /* Enable the Peripheral */
00618   __HAL_LPTIM_ENABLE(hlptim);
00619
00620   /* Start timer in continuous mode */
00621   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00622
00623   /* Change the TIM state*/
00624   hlptim->State = HAL_LPTIM_STATE_READY;
00625
00626   /* Return function status */
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00632   * @param  hlptim LPTIM handle
00633   * @retval HAL status
00634   */
00635 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00636 {
00637   /* Check the parameters */
00638   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00639
00640   /* Set the LPTIM state */
00641   hlptim->State = HAL_LPTIM_STATE_BUSY;
00642
00643   /* Disable the Peripheral */
00644   __HAL_LPTIM_DISABLE(hlptim);
00645
00646   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00647   {
00648     return HAL_TIMEOUT;
00649   }
00650
00651   /* Disable Autoreload write complete interrupt */
00652   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00653
00654   /* Disable Compare write complete interrupt */
00655   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00656
00657   /* Disable Autoreload match interrupt */
00658   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00659
00660   /* Disable Compare match interrupt */
00661   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00662
00663   /* If external trigger source is used, then disable external trigger interrupt */
00664   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00665   {
00666     /* Disable external trigger interrupt */
00667     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00668   }
00669
00670   /* Change the TIM state*/
00671   hlptim->State = HAL_LPTIM_STATE_READY;
00672
00673   /* Return function status */
00674   return HAL_OK;
00675 }
00676
00677 /**
00678   * @brief  Start the LPTIM One pulse generation.
00679   * @param  hlptim LPTIM handle
00680   * @param  Period Specifies the Autoreload value.
00681   *         This parameter must be a value between 0x0000 and 0xFFFF.
00682   * @param  Pulse Specifies the compare value.
00683   *         This parameter must be a value between 0x0000 and 0xFFFF.
00684   * @retval HAL status
00685   */
00686 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00687 {
00688   /* Check the parameters */
00689   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00690   assert_param(IS_LPTIM_PERIOD(Period));
00691   assert_param(IS_LPTIM_PULSE(Pulse));
00692
00693   /* Set the LPTIM state */
00694   hlptim->State = HAL_LPTIM_STATE_BUSY;
00695
00696   /* Reset WAVE bit to set one pulse mode */
00697   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00698
00699   /* Enable the Peripheral */
00700   __HAL_LPTIM_ENABLE(hlptim);
00701
00702   /* Clear flag */
00703   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00704
00705   /* Load the period value in the autoreload register */
00706   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00707
00708   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00709   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00710   {
00711     return HAL_TIMEOUT;
00712   }
00713
00714   /* Clear flag */
00715   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00716
00717   /* Load the pulse value in the compare register */
00718   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00719
00720   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00721   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00722   {
00723     return HAL_TIMEOUT;
00724   }
00725
00726   /* Start timer in single (one shot) mode */
00727   __HAL_LPTIM_START_SINGLE(hlptim);
00728
00729   /* Change the TIM state*/
00730   hlptim->State = HAL_LPTIM_STATE_READY;
00731
00732   /* Return function status */
00733   return HAL_OK;
00734 }
00735
00736 /**
00737   * @brief  Stop the LPTIM One pulse generation.
00738   * @param  hlptim LPTIM handle
00739   * @retval HAL status
00740   */
00741 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00742 {
00743   /* Check the parameters */
00744   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00745
00746   /* Set the LPTIM state */
00747   hlptim->State = HAL_LPTIM_STATE_BUSY;
00748
00749   /* Disable the Peripheral */
00750   __HAL_LPTIM_DISABLE(hlptim);
00751
00752   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00753   {
00754     return HAL_TIMEOUT;
00755   }
00756
00757   /* Change the TIM state*/
00758   hlptim->State = HAL_LPTIM_STATE_READY;
00759
00760   /* Return function status */
00761   return HAL_OK;
00762 }
00763
00764 /**
00765   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00766   * @param  hlptim LPTIM handle
00767   * @param  Period Specifies the Autoreload value.
00768   *         This parameter must be a value between 0x0000 and 0xFFFF.
00769   * @param  Pulse Specifies the compare value.
00770   *         This parameter must be a value between 0x0000 and 0xFFFF.
00771   * @retval HAL status
00772   */
00773 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00774 {
00775   /* Check the parameters */
00776   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00777   assert_param(IS_LPTIM_PERIOD(Period));
00778   assert_param(IS_LPTIM_PULSE(Pulse));
00779
00780   /* Set the LPTIM state */
00781   hlptim->State = HAL_LPTIM_STATE_BUSY;
00782
00783   /* Reset WAVE bit to set one pulse mode */
00784   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00785
00786   /* Enable the Peripheral */
00787   __HAL_LPTIM_ENABLE(hlptim);
00788
00789   /* Clear flag */
00790   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00791
00792   /* Load the period value in the autoreload register */
00793   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00794
00795   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00796   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00797   {
00798     return HAL_TIMEOUT;
00799   }
00800
00801   /* Clear flag */
00802   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00803
00804   /* Load the pulse value in the compare register */
00805   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00806
00807   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00808   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00809   {
00810     return HAL_TIMEOUT;
00811   }
00812
00813   /* Disable the Peripheral */
00814   __HAL_LPTIM_DISABLE(hlptim);
00815
00816   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00817   {
00818     return HAL_TIMEOUT;
00819   }
00820
00821   /* Enable Autoreload write complete interrupt */
00822   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00823
00824   /* Enable Compare write complete interrupt */
00825   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00826
00827   /* Enable Autoreload match interrupt */
00828   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00829
00830   /* Enable Compare match interrupt */
00831   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00832
00833   /* If external trigger source is used, then enable external trigger interrupt */
00834   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00835   {
00836     /* Enable external trigger interrupt */
00837     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00838   }
00839
00840   /* Enable the Peripheral */
00841   __HAL_LPTIM_ENABLE(hlptim);
00842
00843   /* Start timer in single (one shot) mode */
00844   __HAL_LPTIM_START_SINGLE(hlptim);
00845
00846   /* Change the TIM state*/
00847   hlptim->State = HAL_LPTIM_STATE_READY;
00848
00849   /* Return function status */
00850   return HAL_OK;
00851 }
00852
00853 /**
00854   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00855   * @param  hlptim LPTIM handle
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00859 {
00860   /* Check the parameters */
00861   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00862
00863   /* Set the LPTIM state */
00864   hlptim->State = HAL_LPTIM_STATE_BUSY;
00865
00866   /* Disable the Peripheral */
00867   __HAL_LPTIM_DISABLE(hlptim);
00868
00869   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00870   {
00871     return HAL_TIMEOUT;
00872   }
00873
00874   /* Disable Autoreload write complete interrupt */
00875   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00876
00877   /* Disable Compare write complete interrupt */
00878   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00879
00880   /* Disable Autoreload match interrupt */
00881   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00882
00883   /* Disable Compare match interrupt */
00884   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00885
00886   /* If external trigger source is used, then disable external trigger interrupt */
00887   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00888   {
00889     /* Disable external trigger interrupt */
00890     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00891   }
00892
00893   /* Change the TIM state*/
00894   hlptim->State = HAL_LPTIM_STATE_READY;
00895
00896   /* Return function status */
00897   return HAL_OK;
00898 }
00899
00900 /**
00901   * @brief  Start the LPTIM in Set once mode.
00902   * @param  hlptim LPTIM handle
00903   * @param  Period Specifies the Autoreload value.
00904   *         This parameter must be a value between 0x0000 and 0xFFFF.
00905   * @param  Pulse Specifies the compare value.
00906   *         This parameter must be a value between 0x0000 and 0xFFFF.
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00910 {
00911   /* Check the parameters */
00912   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00913   assert_param(IS_LPTIM_PERIOD(Period));
00914   assert_param(IS_LPTIM_PULSE(Pulse));
00915
00916   /* Set the LPTIM state */
00917   hlptim->State = HAL_LPTIM_STATE_BUSY;
00918
00919   /* Set WAVE bit to enable the set once mode */
00920   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00921
00922   /* Enable the Peripheral */
00923   __HAL_LPTIM_ENABLE(hlptim);
00924
00925   /* Clear flag */
00926   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00927
00928   /* Load the period value in the autoreload register */
00929   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00930
00931   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00932   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00933   {
00934     return HAL_TIMEOUT;
00935   }
00936
00937   /* Clear flag */
00938   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00939
00940   /* Load the pulse value in the compare register */
00941   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00942
00943   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00944   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00945   {
00946     return HAL_TIMEOUT;
00947   }
00948
00949   /* Start timer in single (one shot) mode */
00950   __HAL_LPTIM_START_SINGLE(hlptim);
00951
00952   /* Change the TIM state*/
00953   hlptim->State = HAL_LPTIM_STATE_READY;
00954
00955   /* Return function status */
00956   return HAL_OK;
00957 }
00958
00959 /**
00960   * @brief  Stop the LPTIM Set once mode.
00961   * @param  hlptim LPTIM handle
00962   * @retval HAL status
00963   */
00964 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00965 {
00966   /* Check the parameters */
00967   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00968
00969   /* Set the LPTIM state */
00970   hlptim->State = HAL_LPTIM_STATE_BUSY;
00971
00972   /* Disable the Peripheral */
00973   __HAL_LPTIM_DISABLE(hlptim);
00974
00975   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00976   {
00977     return HAL_TIMEOUT;
00978   }
00979
00980   /* Change the TIM state*/
00981   hlptim->State = HAL_LPTIM_STATE_READY;
00982
00983   /* Return function status */
00984   return HAL_OK;
00985 }
00986
00987 /**
00988   * @brief  Start the LPTIM Set once mode in interrupt mode.
00989   * @param  hlptim LPTIM handle
00990   * @param  Period Specifies the Autoreload value.
00991   *         This parameter must be a value between 0x0000 and 0xFFFF.
00992   * @param  Pulse Specifies the compare value.
00993   *         This parameter must be a value between 0x0000 and 0xFFFF.
00994   * @retval HAL status
00995   */
00996 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00997 {
00998   /* Check the parameters */
00999   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01000   assert_param(IS_LPTIM_PERIOD(Period));
01001   assert_param(IS_LPTIM_PULSE(Pulse));
01002
01003   /* Set the LPTIM state */
01004   hlptim->State = HAL_LPTIM_STATE_BUSY;
01005
01006   /* Set WAVE bit to enable the set once mode */
01007   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
01008
01009   /* Enable the Peripheral */
01010   __HAL_LPTIM_ENABLE(hlptim);
01011
01012   /* Clear flag */
01013   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01014
01015   /* Load the period value in the autoreload register */
01016   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01017
01018   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01019   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01020   {
01021     return HAL_TIMEOUT;
01022   }
01023
01024   /* Clear flag */
01025   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01026
01027   /* Load the pulse value in the compare register */
01028   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
01029
01030   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01031   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01032   {
01033     return HAL_TIMEOUT;
01034   }
01035
01036   /* Disable the Peripheral */
01037   __HAL_LPTIM_DISABLE(hlptim);
01038
01039   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01040   {
01041     return HAL_TIMEOUT;
01042   }
01043
01044   /* Enable Autoreload write complete interrupt */
01045   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01046
01047   /* Enable Compare write complete interrupt */
01048   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
01049
01050   /* Enable Autoreload match interrupt */
01051   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01052
01053   /* Enable Compare match interrupt */
01054   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01055
01056   /* If external trigger source is used, then enable external trigger interrupt */
01057   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01058   {
01059     /* Enable external trigger interrupt */
01060     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01061   }
01062
01063   /* Enable the Peripheral */
01064   __HAL_LPTIM_ENABLE(hlptim);
01065
01066   /* Start timer in single (one shot) mode */
01067   __HAL_LPTIM_START_SINGLE(hlptim);
01068
01069   /* Change the TIM state*/
01070   hlptim->State = HAL_LPTIM_STATE_READY;
01071
01072   /* Return function status */
01073   return HAL_OK;
01074 }
01075
01076 /**
01077   * @brief  Stop the LPTIM Set once mode in interrupt mode.
01078   * @param  hlptim LPTIM handle
01079   * @retval HAL status
01080   */
01081 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01082 {
01083   /* Check the parameters */
01084   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01085
01086   /* Set the LPTIM state */
01087   hlptim->State = HAL_LPTIM_STATE_BUSY;
01088
01089   /* Disable the Peripheral */
01090   __HAL_LPTIM_DISABLE(hlptim);
01091
01092   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01093   {
01094     return HAL_TIMEOUT;
01095   }
01096
01097   /* Disable Autoreload write complete interrupt */
01098   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01099
01100   /* Disable Compare write complete interrupt */
01101   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
01102
01103   /* Disable Autoreload match interrupt */
01104   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01105
01106   /* Disable Compare match interrupt */
01107   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01108
01109   /* If external trigger source is used, then disable external trigger interrupt */
01110   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01111   {
01112     /* Disable external trigger interrupt */
01113     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01114   }
01115
01116   /* Change the TIM state*/
01117   hlptim->State = HAL_LPTIM_STATE_READY;
01118
01119   /* Return function status */
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief  Start the Encoder interface.
01125   * @param  hlptim LPTIM handle
01126   * @param  Period Specifies the Autoreload value.
01127   *         This parameter must be a value between 0x0000 and 0xFFFF.
01128   * @retval HAL status
01129   */
01130 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01131 {
01132   uint32_t          tmpcfgr;
01133
01134   /* Check the parameters */
01135   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01136   assert_param(IS_LPTIM_PERIOD(Period));
01137   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01138   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01139   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01140
01141   /* Set the LPTIM state */
01142   hlptim->State = HAL_LPTIM_STATE_BUSY;
01143
01144   /* Get the LPTIMx CFGR value */
01145   tmpcfgr = hlptim->Instance->CFGR;
01146
01147   /* Clear CKPOL bits */
01148   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01149
01150   /* Set Input polarity */
01151   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01152
01153   /* Write to LPTIMx CFGR */
01154   hlptim->Instance->CFGR = tmpcfgr;
01155
01156   /* Set ENC bit to enable the encoder interface */
01157   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01158
01159   /* Enable the Peripheral */
01160   __HAL_LPTIM_ENABLE(hlptim);
01161
01162   /* Clear flag */
01163   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01164
01165   /* Load the period value in the autoreload register */
01166   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01167
01168   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01169   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01170   {
01171     return HAL_TIMEOUT;
01172   }
01173
01174   /* Start timer in continuous mode */
01175   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01176
01177   /* Change the TIM state*/
01178   hlptim->State = HAL_LPTIM_STATE_READY;
01179
01180   /* Return function status */
01181   return HAL_OK;
01182 }
01183
01184 /**
01185   * @brief  Stop the Encoder interface.
01186   * @param  hlptim LPTIM handle
01187   * @retval HAL status
01188   */
01189 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
01190 {
01191   /* Check the parameters */
01192   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01193
01194   /* Set the LPTIM state */
01195   hlptim->State = HAL_LPTIM_STATE_BUSY;
01196
01197   /* Disable the Peripheral */
01198   __HAL_LPTIM_DISABLE(hlptim);
01199
01200   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01201   {
01202     return HAL_TIMEOUT;
01203   }
01204
01205   /* Reset ENC bit to disable the encoder interface */
01206   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01207
01208   /* Change the TIM state*/
01209   hlptim->State = HAL_LPTIM_STATE_READY;
01210
01211   /* Return function status */
01212   return HAL_OK;
01213 }
01214
01215 /**
01216   * @brief  Start the Encoder interface in interrupt mode.
01217   * @param  hlptim LPTIM handle
01218   * @param  Period Specifies the Autoreload value.
01219   *         This parameter must be a value between 0x0000 and 0xFFFF.
01220   * @retval HAL status
01221   */
01222 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01223 {
01224   uint32_t          tmpcfgr;
01225
01226   /* Check the parameters */
01227   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01228   assert_param(IS_LPTIM_PERIOD(Period));
01229   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01230   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01231   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01232
01233   /* Set the LPTIM state */
01234   hlptim->State = HAL_LPTIM_STATE_BUSY;
01235
01236   /* Configure edge sensitivity for encoder mode */
01237   /* Get the LPTIMx CFGR value */
01238   tmpcfgr = hlptim->Instance->CFGR;
01239
01240   /* Clear CKPOL bits */
01241   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01242
01243   /* Set Input polarity */
01244   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01245
01246   /* Write to LPTIMx CFGR */
01247   hlptim->Instance->CFGR = tmpcfgr;
01248
01249   /* Set ENC bit to enable the encoder interface */
01250   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01251
01252   /* Enable the Peripheral */
01253   __HAL_LPTIM_ENABLE(hlptim);
01254
01255   /* Clear flag */
01256   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01257
01258   /* Load the period value in the autoreload register */
01259   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01260
01261   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01262   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01263   {
01264     return HAL_TIMEOUT;
01265   }
01266
01267   /* Disable the Peripheral */
01268   __HAL_LPTIM_DISABLE(hlptim);
01269
01270   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01271   {
01272     return HAL_TIMEOUT;
01273   }
01274
01275   /* Enable "switch to down direction" interrupt */
01276   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01277
01278   /* Enable "switch to up direction" interrupt */
01279   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01280
01281   /* Enable the Peripheral */
01282   __HAL_LPTIM_ENABLE(hlptim);
01283
01284   /* Start timer in continuous mode */
01285   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01286
01287   /* Change the TIM state*/
01288   hlptim->State = HAL_LPTIM_STATE_READY;
01289
01290   /* Return function status */
01291   return HAL_OK;
01292 }
01293
01294 /**
01295   * @brief  Stop the Encoder interface in interrupt mode.
01296   * @param  hlptim LPTIM handle
01297   * @retval HAL status
01298   */
01299 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01300 {
01301   /* Check the parameters */
01302   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01303
01304   /* Set the LPTIM state */
01305   hlptim->State = HAL_LPTIM_STATE_BUSY;
01306
01307   /* Disable the Peripheral */
01308   __HAL_LPTIM_DISABLE(hlptim);
01309
01310   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01311   {
01312     return HAL_TIMEOUT;
01313   }
01314
01315   /* Reset ENC bit to disable the encoder interface */
01316   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01317
01318   /* Disable "switch to down direction" interrupt */
01319   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01320
01321   /* Disable "switch to up direction" interrupt */
01322   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01323
01324   /* Change the TIM state*/
01325   hlptim->State = HAL_LPTIM_STATE_READY;
01326
01327   /* Return function status */
01328   return HAL_OK;
01329 }
01330
01331 /**
01332   * @brief  Start the Timeout function.
01333   * @note   The first trigger event will start the timer, any successive
01334   *         trigger event will reset the counter and the timer restarts.
01335   * @param  hlptim LPTIM handle
01336   * @param  Period Specifies the Autoreload value.
01337   *         This parameter must be a value between 0x0000 and 0xFFFF.
01338   * @param  Timeout Specifies the TimeOut value to reset the counter.
01339   *         This parameter must be a value between 0x0000 and 0xFFFF.
01340   * @retval HAL status
01341   */
01342 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01343 {
01344   /* Check the parameters */
01345   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01346   assert_param(IS_LPTIM_PERIOD(Period));
01347   assert_param(IS_LPTIM_PULSE(Timeout));
01348
01349   /* Set the LPTIM state */
01350   hlptim->State = HAL_LPTIM_STATE_BUSY;
01351
01352   /* Set TIMOUT bit to enable the timeout function */
01353   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01354
01355   /* Enable the Peripheral */
01356   __HAL_LPTIM_ENABLE(hlptim);
01357
01358   /* Clear flag */
01359   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01360
01361   /* Load the period value in the autoreload register */
01362   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01363
01364   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01365   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01366   {
01367     return HAL_TIMEOUT;
01368   }
01369
01370   /* Clear flag */
01371   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01372
01373   /* Load the Timeout value in the compare register */
01374   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01375
01376   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01377   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01378   {
01379     return HAL_TIMEOUT;
01380   }
01381
01382   /* Start timer in continuous mode */
01383   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01384
01385   /* Change the TIM state*/
01386   hlptim->State = HAL_LPTIM_STATE_READY;
01387
01388   /* Return function status */
01389   return HAL_OK;
01390 }
01391
01392 /**
01393   * @brief  Stop the Timeout function.
01394   * @param  hlptim LPTIM handle
01395   * @retval HAL status
01396   */
01397 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01398 {
01399   /* Check the parameters */
01400   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01401
01402   /* Set the LPTIM state */
01403   hlptim->State = HAL_LPTIM_STATE_BUSY;
01404
01405   /* Disable the Peripheral */
01406   __HAL_LPTIM_DISABLE(hlptim);
01407
01408   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01409   {
01410     return HAL_TIMEOUT;
01411   }
01412
01413   /* Reset TIMOUT bit to enable the timeout function */
01414   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01415
01416   /* Change the TIM state*/
01417   hlptim->State = HAL_LPTIM_STATE_READY;
01418
01419   /* Return function status */
01420   return HAL_OK;
01421 }
01422
01423 /**
01424   * @brief  Start the Timeout function in interrupt mode.
01425   * @note   The first trigger event will start the timer, any successive
01426   *         trigger event will reset the counter and the timer restarts.
01427   * @param  hlptim LPTIM handle
01428   * @param  Period Specifies the Autoreload value.
01429   *         This parameter must be a value between 0x0000 and 0xFFFF.
01430   * @param  Timeout Specifies the TimeOut value to reset the counter.
01431   *         This parameter must be a value between 0x0000 and 0xFFFF.
01432   * @retval HAL status
01433   */
01434 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01435 {
01436   /* Check the parameters */
01437   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01438   assert_param(IS_LPTIM_PERIOD(Period));
01439   assert_param(IS_LPTIM_PULSE(Timeout));
01440
01441   /* Set the LPTIM state */
01442   hlptim->State = HAL_LPTIM_STATE_BUSY;
01443
01444   /* Set TIMOUT bit to enable the timeout function */
01445   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01446
01447   /* Enable the Peripheral */
01448   __HAL_LPTIM_ENABLE(hlptim);
01449
01450   /* Clear flag */
01451   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01452
01453   /* Load the period value in the autoreload register */
01454   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01455
01456   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01457   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01458   {
01459     return HAL_TIMEOUT;
01460   }
01461
01462   /* Clear flag */
01463   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01464
01465   /* Load the Timeout value in the compare register */
01466   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01467
01468   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01469   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01470   {
01471     return HAL_TIMEOUT;
01472   }
01473
01474   /* Disable the Peripheral */
01475   __HAL_LPTIM_DISABLE(hlptim);
01476
01477   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01478   {
01479     return HAL_TIMEOUT;
01480   }
01481
01482   /* Enable Compare match interrupt */
01483   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01484
01485   /* Enable the Peripheral */
01486   __HAL_LPTIM_ENABLE(hlptim);
01487
01488   /* Start timer in continuous mode */
01489   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01490
01491   /* Change the TIM state*/
01492   hlptim->State = HAL_LPTIM_STATE_READY;
01493
01494   /* Return function status */
01495   return HAL_OK;
01496 }
01497
01498 /**
01499   * @brief  Stop the Timeout function in interrupt mode.
01500   * @param  hlptim LPTIM handle
01501   * @retval HAL status
01502   */
01503 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01504 {
01505   /* Check the parameters */
01506   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01507
01508   /* Set the LPTIM state */
01509   hlptim->State = HAL_LPTIM_STATE_BUSY;
01510
01511   /* Disable the Peripheral */
01512   __HAL_LPTIM_DISABLE(hlptim);
01513
01514   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01515   {
01516     return HAL_TIMEOUT;
01517   }
01518
01519   /* Reset TIMOUT bit to enable the timeout function */
01520   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01521
01522   /* Disable Compare match interrupt */
01523   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01524
01525   /* Change the TIM state*/
01526   hlptim->State = HAL_LPTIM_STATE_READY;
01527
01528   /* Return function status */
01529   return HAL_OK;
01530 }
01531
01532 /**
01533   * @brief  Start the Counter mode.
01534   * @param  hlptim LPTIM handle
01535   * @param  Period Specifies the Autoreload value.
01536   *         This parameter must be a value between 0x0000 and 0xFFFF.
01537   * @retval HAL status
01538   */
01539 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01540 {
01541   /* Check the parameters */
01542   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01543   assert_param(IS_LPTIM_PERIOD(Period));
01544
01545   /* Set the LPTIM state */
01546   hlptim->State = HAL_LPTIM_STATE_BUSY;
01547
01548   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01549   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01550   {
01551     /* Check if clock is prescaled */
01552     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01553     /* Set clock prescaler to 0 */
01554     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01555   }
01556
01557   /* Enable the Peripheral */
01558   __HAL_LPTIM_ENABLE(hlptim);
01559
01560   /* Clear flag */
01561   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01562
01563   /* Load the period value in the autoreload register */
01564   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01565
01566   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01567   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01568   {
01569     return HAL_TIMEOUT;
01570   }
01571
01572   /* Start timer in continuous mode */
01573   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01574
01575   /* Change the TIM state*/
01576   hlptim->State = HAL_LPTIM_STATE_READY;
01577
01578   /* Return function status */
01579   return HAL_OK;
01580 }
01581
01582 /**
01583   * @brief  Stop the Counter mode.
01584   * @param  hlptim LPTIM handle
01585   * @retval HAL status
01586   */
01587 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01588 {
01589   /* Check the parameters */
01590   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01591
01592   /* Set the LPTIM state */
01593   hlptim->State = HAL_LPTIM_STATE_BUSY;
01594
01595   /* Disable the Peripheral */
01596   __HAL_LPTIM_DISABLE(hlptim);
01597
01598   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01599   {
01600     return HAL_TIMEOUT;
01601   }
01602
01603   /* Change the TIM state*/
01604   hlptim->State = HAL_LPTIM_STATE_READY;
01605
01606   /* Return function status */
01607   return HAL_OK;
01608 }
01609
01610 /**
01611   * @brief  Start the Counter mode in interrupt mode.
01612   * @param  hlptim LPTIM handle
01613   * @param  Period Specifies the Autoreload value.
01614   *         This parameter must be a value between 0x0000 and 0xFFFF.
01615   * @retval HAL status
01616   */
01617 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01618 {
01619   /* Check the parameters */
01620   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01621   assert_param(IS_LPTIM_PERIOD(Period));
01622
01623   /* Set the LPTIM state */
01624   hlptim->State = HAL_LPTIM_STATE_BUSY;
01625
01626   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01627   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01628   {
01629     /* Check if clock is prescaled */
01630     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01631     /* Set clock prescaler to 0 */
01632     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01633   }
01634
01635   /* Enable the Peripheral */
01636   __HAL_LPTIM_ENABLE(hlptim);
01637
01638   /* Clear flag */
01639   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01640
01641   /* Load the period value in the autoreload register */
01642   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01643
01644   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01645   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01646   {
01647     return HAL_TIMEOUT;
01648   }
01649
01650   /* Disable the Peripheral */
01651   __HAL_LPTIM_DISABLE(hlptim);
01652
01653   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01654   {
01655     return HAL_TIMEOUT;
01656   }
01657
01658   /* Enable Autoreload write complete interrupt */
01659   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01660
01661   /* Enable Autoreload match interrupt */
01662   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01663
01664   /* Enable the Peripheral */
01665   __HAL_LPTIM_ENABLE(hlptim);
01666
01667   /* Start timer in continuous mode */
01668   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01669
01670   /* Change the TIM state*/
01671   hlptim->State = HAL_LPTIM_STATE_READY;
01672
01673   /* Return function status */
01674   return HAL_OK;
01675 }
01676
01677 /**
01678   * @brief  Stop the Counter mode in interrupt mode.
01679   * @param  hlptim LPTIM handle
01680   * @retval HAL status
01681   */
01682 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01683 {
01684   /* Check the parameters */
01685   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01686
01687   /* Set the LPTIM state */
01688   hlptim->State = HAL_LPTIM_STATE_BUSY;
01689
01690   /* Disable the Peripheral */
01691   __HAL_LPTIM_DISABLE(hlptim);
01692
01693   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01694   {
01695     return HAL_TIMEOUT;
01696   }
01697
01698   /* Disable Autoreload write complete interrupt */
01699   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01700
01701   /* Disable Autoreload match interrupt */
01702   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01703   /* Change the TIM state*/
01704   hlptim->State = HAL_LPTIM_STATE_READY;
01705
01706   /* Return function status */
01707   return HAL_OK;
01708 }
01709
01710 /**
01711   * @}
01712   */
01713
01714 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01715  *  @brief  Read operation functions.
01716  *
01717 @verbatim
01718   ==============================================================================
01719                   ##### LPTIM Read operation functions #####
01720   ==============================================================================
01721 [..]  This section provides LPTIM Reading functions.
01722       (+) Read the counter value.
01723       (+) Read the period (Auto-reload) value.
01724       (+) Read the pulse (Compare)value.
01725 @endverbatim
01726   * @{
01727   */
01728
01729 /**
01730   * @brief  Return the current counter value.
01731   * @param  hlptim LPTIM handle
01732   * @retval Counter value.
01733   */
01734 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01735 {
01736   /* Check the parameters */
01737   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01738
01739   return (hlptim->Instance->CNT);
01740 }
01741
01742 /**
01743   * @brief  Return the current Autoreload (Period) value.
01744   * @param  hlptim LPTIM handle
01745   * @retval Autoreload value.
01746   */
01747 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01748 {
01749   /* Check the parameters */
01750   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01751
01752   return (hlptim->Instance->ARR);
01753 }
01754
01755 /**
01756   * @brief  Return the current Compare (Pulse) value.
01757   * @param  hlptim LPTIM handle
01758   * @retval Compare value.
01759   */
01760 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01761 {
01762   /* Check the parameters */
01763   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01764
01765   return (hlptim->Instance->CMP);
01766 }
01767
01768 /**
01769   * @}
01770   */
01771
01772 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01773  *  @brief  LPTIM  IRQ handler.
01774  *
01775 @verbatim
01776   ==============================================================================
01777                       ##### LPTIM IRQ handler and callbacks  #####
01778   ==============================================================================
01779 [..]  This section provides LPTIM IRQ handler and callback functions called within
01780       the IRQ handler:
01781    (+) LPTIM interrupt request handler
01782    (+) Compare match Callback
01783    (+) Auto-reload match Callback
01784    (+) External trigger event detection Callback
01785    (+) Compare register write complete Callback
01786    (+) Auto-reload register write complete Callback
01787    (+) Up-counting direction change Callback
01788    (+) Down-counting direction change Callback
01789
01790 @endverbatim
01791   * @{
01792   */
01793
01794 /**
01795   * @brief  Handle LPTIM interrupt request.
01796   * @param  hlptim LPTIM handle
01797   * @retval None
01798   */
01799 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01800 {
01801   /* Compare match interrupt */
01802   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01803   {
01804     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01805     {
01806       /* Clear Compare match flag */
01807       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01808
01809       /* Compare match Callback */
01810 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01811       hlptim->CompareMatchCallback(hlptim);
01812 #else
01813       HAL_LPTIM_CompareMatchCallback(hlptim);
01814 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01815     }
01816   }
01817
01818   /* Autoreload match interrupt */
01819   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01820   {
01821     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01822     {
01823       /* Clear Autoreload match flag */
01824       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01825
01826       /* Autoreload match Callback */
01827 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01828       hlptim->AutoReloadMatchCallback(hlptim);
01829 #else
01830       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01831 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01832     }
01833   }
01834
01835   /* Trigger detected interrupt */
01836   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01837   {
01838     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01839     {
01840       /* Clear Trigger detected flag */
01841       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01842
01843       /* Trigger detected callback */
01844 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01845       hlptim->TriggerCallback(hlptim);
01846 #else
01847       HAL_LPTIM_TriggerCallback(hlptim);
01848 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01849     }
01850   }
01851
01852   /* Compare write interrupt */
01853   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01854   {
01855     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01856     {
01857       /* Clear Compare write flag */
01858       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01859
01860       /* Compare write Callback */
01861 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01862       hlptim->CompareWriteCallback(hlptim);
01863 #else
01864       HAL_LPTIM_CompareWriteCallback(hlptim);
01865 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01866     }
01867   }
01868
01869   /* Autoreload write interrupt */
01870   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01871   {
01872     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01873     {
01874       /* Clear Autoreload write flag */
01875       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01876
01877       /* Autoreload write Callback */
01878 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01879       hlptim->AutoReloadWriteCallback(hlptim);
01880 #else
01881       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01882 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01883     }
01884   }
01885
01886   /* Direction counter changed from Down to Up interrupt */
01887   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01888   {
01889     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01890     {
01891       /* Clear Direction counter changed from Down to Up flag */
01892       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01893
01894       /* Direction counter changed from Down to Up Callback */
01895 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01896       hlptim->DirectionUpCallback(hlptim);
01897 #else
01898       HAL_LPTIM_DirectionUpCallback(hlptim);
01899 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01900     }
01901   }
01902
01903   /* Direction counter changed from Up to Down interrupt */
01904   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01905   {
01906     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01907     {
01908       /* Clear Direction counter changed from Up to Down flag */
01909       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01910
01911       /* Direction counter changed from Up to Down Callback */
01912 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01913       hlptim->DirectionDownCallback(hlptim);
01914 #else
01915       HAL_LPTIM_DirectionDownCallback(hlptim);
01916 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01917     }
01918   }
01919 }
01920
01921 /**
01922   * @brief  Compare match callback in non-blocking mode.
01923   * @param  hlptim LPTIM handle
01924   * @retval None
01925   */
01926 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01927 {
01928   /* Prevent unused argument(s) compilation warning */
01929   UNUSED(hlptim);
01930
01931   /* NOTE : This function should not be modified, when the callback is needed,
01932             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01933    */
01934 }
01935
01936 /**
01937   * @brief  Autoreload match callback in non-blocking mode.
01938   * @param  hlptim LPTIM handle
01939   * @retval None
01940   */
01941 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01942 {
01943   /* Prevent unused argument(s) compilation warning */
01944   UNUSED(hlptim);
01945
01946   /* NOTE : This function should not be modified, when the callback is needed,
01947             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01948    */
01949 }
01950
01951 /**
01952   * @brief  Trigger detected callback in non-blocking mode.
01953   * @param  hlptim LPTIM handle
01954   * @retval None
01955   */
01956 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01957 {
01958   /* Prevent unused argument(s) compilation warning */
01959   UNUSED(hlptim);
01960
01961   /* NOTE : This function should not be modified, when the callback is needed,
01962             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01963    */
01964 }
01965
01966 /**
01967   * @brief  Compare write callback in non-blocking mode.
01968   * @param  hlptim LPTIM handle
01969   * @retval None
01970   */
01971 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01972 {
01973   /* Prevent unused argument(s) compilation warning */
01974   UNUSED(hlptim);
01975
01976   /* NOTE : This function should not be modified, when the callback is needed,
01977             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01978    */
01979 }
01980
01981 /**
01982   * @brief  Autoreload write callback in non-blocking mode.
01983   * @param  hlptim LPTIM handle
01984   * @retval None
01985   */
01986 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01987 {
01988   /* Prevent unused argument(s) compilation warning */
01989   UNUSED(hlptim);
01990
01991   /* NOTE : This function should not be modified, when the callback is needed,
01992             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01993    */
01994 }
01995
01996 /**
01997   * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
01998   * @param  hlptim LPTIM handle
01999   * @retval None
02000   */
02001 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
02002 {
02003   /* Prevent unused argument(s) compilation warning */
02004   UNUSED(hlptim);
02005
02006   /* NOTE : This function should not be modified, when the callback is needed,
02007             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
02008    */
02009 }
02010
02011 /**
02012   * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
02013   * @param  hlptim LPTIM handle
02014   * @retval None
02015   */
02016 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
02017 {
02018   /* Prevent unused argument(s) compilation warning */
02019   UNUSED(hlptim);
02020
02021   /* NOTE : This function should not be modified, when the callback is needed,
02022             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
02023    */
02024 }
02025
02026 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02027 /**
02028   * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
02029   * @param hlptim LPTIM handle
02030   * @param CallbackID ID of the callback to be registered
02031   *        This parameter can be one of the following values:
02032   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02033   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02034   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02035   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02036   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02037   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02038   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02039   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02040   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02041   * @param pCallback pointer to the callback function
02042   * @retval status
02043   */
02044 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02045                                              HAL_LPTIM_CallbackIDTypeDef CallbackID,
02046                                              pLPTIM_CallbackTypeDef      pCallback)
02047 {
02048   HAL_StatusTypeDef status = HAL_OK;
02049
02050   if (pCallback == NULL)
02051   {
02052     return HAL_ERROR;
02053   }
02054
02055   /* Process locked */
02056   __HAL_LOCK(hlptim);
02057
02058   if (hlptim->State == HAL_LPTIM_STATE_READY)
02059   {
02060     switch (CallbackID)
02061     {
02062       case HAL_LPTIM_MSPINIT_CB_ID :
02063         hlptim->MspInitCallback = pCallback;
02064         break;
02065
02066       case HAL_LPTIM_MSPDEINIT_CB_ID :
02067         hlptim->MspDeInitCallback = pCallback;
02068         break;
02069
02070       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02071         hlptim->CompareMatchCallback = pCallback;
02072         break;
02073
02074       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02075         hlptim->AutoReloadMatchCallback = pCallback;
02076         break;
02077
02078       case HAL_LPTIM_TRIGGER_CB_ID :
02079         hlptim->TriggerCallback = pCallback;
02080         break;
02081
02082       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02083         hlptim->CompareWriteCallback = pCallback;
02084         break;
02085
02086       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02087         hlptim->AutoReloadWriteCallback = pCallback;
02088         break;
02089
02090       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02091         hlptim->DirectionUpCallback = pCallback;
02092         break;
02093
02094       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02095         hlptim->DirectionDownCallback = pCallback;
02096         break;
02097
02098       default :
02099         /* Return error status */
02100         status =  HAL_ERROR;
02101         break;
02102     }
02103   }
02104   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02105   {
02106     switch (CallbackID)
02107     {
02108       case HAL_LPTIM_MSPINIT_CB_ID :
02109         hlptim->MspInitCallback = pCallback;
02110         break;
02111
02112       case HAL_LPTIM_MSPDEINIT_CB_ID :
02113         hlptim->MspDeInitCallback = pCallback;
02114         break;
02115
02116       default :
02117         /* Return error status */
02118         status =  HAL_ERROR;
02119         break;
02120     }
02121   }
02122   else
02123   {
02124     /* Return error status */
02125     status =  HAL_ERROR;
02126   }
02127
02128   /* Release Lock */
02129   __HAL_UNLOCK(hlptim);
02130
02131   return status;
02132 }
02133
02134 /**
02135   * @brief  Unregister a LPTIM callback
02136   *         LLPTIM callback is redirected to the weak predefined callback
02137   * @param hlptim LPTIM handle
02138   * @param CallbackID ID of the callback to be unregistered
02139   *        This parameter can be one of the following values:
02140   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02141   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02142   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02143   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02144   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02145   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02146   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02147   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02148   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02149   * @retval status
02150   */
02151 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02152                                                HAL_LPTIM_CallbackIDTypeDef CallbackID)
02153 {
02154   HAL_StatusTypeDef status = HAL_OK;
02155
02156   /* Process locked */
02157   __HAL_LOCK(hlptim);
02158
02159   if (hlptim->State == HAL_LPTIM_STATE_READY)
02160   {
02161     switch (CallbackID)
02162     {
02163       case HAL_LPTIM_MSPINIT_CB_ID :
02164         hlptim->MspInitCallback = HAL_LPTIM_MspInit;                          /* Legacy weak MspInit Callback */
02165         break;
02166
02167       case HAL_LPTIM_MSPDEINIT_CB_ID :
02168         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                       /* Legacy weak Msp DeInit Callback */
02169         break;
02170
02171       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02172         hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;         /* Legacy weak Compare match Callback */
02173         break;
02174
02175       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02176         hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;   /* Legacy weak Auto-reload match Callback */
02177         break;
02178
02179       case HAL_LPTIM_TRIGGER_CB_ID :
02180         hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;                   /* Legacy weak External trigger event detection Callback */
02181         break;
02182
02183       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02184         hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;         /* Legacy weak Compare register write complete Callback */
02185         break;
02186
02187       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02188         hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;   /* Legacy weak Auto-reload register write complete Callback */
02189         break;
02190
02191       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02192         hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;           /* Legacy weak Up-counting direction change Callback */
02193         break;
02194
02195       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02196         hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;       /* Legacy weak Down-counting direction change Callback */
02197         break;
02198
02199       default :
02200         /* Return error status */
02201         status =  HAL_ERROR;
02202         break;
02203     }
02204   }
02205   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02206   {
02207     switch (CallbackID)
02208     {
02209       case HAL_LPTIM_MSPINIT_CB_ID :
02210         hlptim->MspInitCallback = HAL_LPTIM_MspInit;                           /* Legacy weak MspInit Callback */
02211         break;
02212
02213       case HAL_LPTIM_MSPDEINIT_CB_ID :
02214         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                        /* Legacy weak Msp DeInit Callback */
02215         break;
02216
02217       default :
02218         /* Return error status */
02219         status =  HAL_ERROR;
02220         break;
02221     }
02222   }
02223   else
02224   {
02225     /* Return error status */
02226     status =  HAL_ERROR;
02227   }
02228
02229   /* Release Lock */
02230   __HAL_UNLOCK(hlptim);
02231
02232   return status;
02233 }
02234 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02235
02236 /**
02237   * @}
02238   */
02239
02240 /** @defgroup LPTIM_Group5 Peripheral State functions
02241  *  @brief   Peripheral State functions.
02242  *
02243 @verbatim
02244   ==============================================================================
02245                       ##### Peripheral State functions #####
02246   ==============================================================================
02247     [..]
02248     This subsection permits to get in run-time the status of the peripheral.
02249
02250 @endverbatim
02251   * @{
02252   */
02253
02254 /**
02255   * @brief  Return the LPTIM handle state.
02256   * @param  hlptim LPTIM handle
02257   * @retval HAL state
02258   */
02259 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
02260 {
02261   /* Return LPTIM handle state */
02262   return hlptim->State;
02263 }
02264
02265 /**
02266   * @}
02267   */
02268
02269
02270 /**
02271   * @}
02272   */
02273
02274 /* Private functions ---------------------------------------------------------*/
02275
02276 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
02277   * @{
02278   */
02279 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02280 /**
02281   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
02282   * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
02283   *                the configuration information for LPTIM module.
02284   * @retval None
02285   */
02286 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
02287 {
02288   /* Reset the LPTIM callback to the legacy weak callbacks */
02289   lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;    /* Compare match Callback                       */
02290   lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback                   */
02291   lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;         /* External trigger event detection Callback    */
02292   lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;    /* Compare register write complete Callback     */
02293   lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
02294   lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;     /* Up-counting direction change Callback        */
02295   lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;   /* Down-counting direction change Callback      */
02296 }
02297 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02298
02299 /**
02300   * @brief  LPTimer Wait for flag set
02301   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02302   *                the configuration information for LPTIM module.
02303   * @param  flag   The lptim flag
02304   * @retval HAL status
02305   */
02306 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
02307 {
02308   HAL_StatusTypeDef result = HAL_OK;
02309   uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
02310     do
02311     {
02312       count--;
02313       if (count == 0UL)
02314       {
02315         result = HAL_TIMEOUT;
02316       }
02317     }
02318     while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
02319
02320     return result;
02321 }
02322
02323 /**
02324   * @brief  Disable LPTIM HW instance.
02325   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02326   *                the configuration information for LPTIM module.
02327   * @note   The following sequence is required to solve LPTIM disable HW limitation.
02328   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
02329   *         stuck in LPTIM interrupt when entering Stop mode" section.
02330   * @retval None
02331   */
02332 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
02333 {
02334   uint32_t tmpclksource = 0;
02335   uint32_t tmpIER;
02336   uint32_t tmpCFGR;
02337   uint32_t tmpCMP;
02338   uint32_t tmpARR;
02339   uint32_t tmpCFGR2;
02340
02341   __disable_irq();
02342
02343   /*********** Save LPTIM Config ***********/
02344   /* Save LPTIM source clock */
02345   switch ((uint32_t)hlptim->Instance)
02346   {
02347      case LPTIM1_BASE:
02348        tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
02349        break;
02350      case LPTIM2_BASE:
02351        tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
02352        break;
02353 #if defined(LPTIM3)
02354      case LPTIM3_BASE:
02355        tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
02356        break;
02357 #endif /* LPTIM3 */
02358 #if defined(LPTIM4)
02359      case LPTIM4_BASE:
02360        tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
02361        break;
02362 #endif /* LPTIM4 */
02363 #if defined(LPTIM5)
02364      case LPTIM5_BASE:
02365        tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
02366        break;
02367 #endif /* LPTIM5 */
02368      default:
02369        break;
02370   }
02371
02372   /* Save LPTIM configuration registers */
02373   tmpIER = hlptim->Instance->IER;
02374   tmpCFGR = hlptim->Instance->CFGR;
02375   tmpCMP = hlptim->Instance->CMP;
02376   tmpARR = hlptim->Instance->ARR;
02377   tmpCFGR2 = hlptim->Instance->CFGR2;
02378
02379   /*********** Reset LPTIM ***********/
02380   switch ((uint32_t)hlptim->Instance)
02381   {
02382      case LPTIM1_BASE:
02383        __HAL_RCC_LPTIM1_FORCE_RESET();
02384        __HAL_RCC_LPTIM1_RELEASE_RESET();
02385        break;
02386      case LPTIM2_BASE:
02387        __HAL_RCC_LPTIM2_FORCE_RESET();
02388        __HAL_RCC_LPTIM2_RELEASE_RESET();
02389        break;
02390 #if defined(LPTIM3)
02391      case LPTIM3_BASE:
02392        __HAL_RCC_LPTIM3_FORCE_RESET();
02393        __HAL_RCC_LPTIM3_RELEASE_RESET();
02394        break;
02395 #endif /* LPTIM3 */
02396 #if defined(LPTIM4)
02397      case LPTIM4_BASE:
02398        __HAL_RCC_LPTIM4_FORCE_RESET();
02399        __HAL_RCC_LPTIM4_RELEASE_RESET();
02400        break;
02401 #endif /* LPTIM4 */
02402 #if defined(LPTIM5)
02403      case LPTIM5_BASE:
02404        __HAL_RCC_LPTIM5_FORCE_RESET();
02405        __HAL_RCC_LPTIM5_RELEASE_RESET();
02406        break;
02407 #endif /* LPTIM5 */
02408      default:
02409        break;
02410   }
02411
02412   /*********** Restore LPTIM Config ***********/
02413   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
02414   {
02415     /* Force LPTIM source kernel clock from APB */
02416     switch ((uint32_t)hlptim->Instance)
02417     {
02418        case LPTIM1_BASE:
02419          __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
02420          break;
02421        case LPTIM2_BASE:
02422          __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
02423          break;
02424 #if defined(LPTIM3)
02425        case LPTIM3_BASE:
02426          __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
02427          break;
02428 #endif /* LPTIM3 */
02429 #if defined(LPTIM4)
02430        case LPTIM4_BASE:
02431          __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
02432          break;
02433 #endif /* LPTIM4 */
02434 #if defined(LPTIM5)
02435        case LPTIM5_BASE:
02436          __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
02437          break;
02438 #endif /* LPTIM5 */
02439        default:
02440          break;
02441     }
02442
02443     if (tmpCMP != 0UL)
02444     {
02445       /* Restore CMP register (LPTIM should be enabled first) */
02446       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02447       hlptim->Instance->CMP = tmpCMP;
02448
02449       /* Wait for the completion of the write operation to the LPTIM_CMP register */
02450       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
02451       {
02452         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02453       }
02454       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
02455     }
02456
02457     if (tmpARR != 0UL)
02458     {
02459       /* Restore ARR register (LPTIM should be enabled first) */
02460       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02461       hlptim->Instance->ARR = tmpARR;
02462
02463       /* Wait for the completion of the write operation to the LPTIM_ARR register */
02464       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
02465       {
02466         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02467       }
02468
02469       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
02470     }
02471
02472     /* Restore LPTIM source kernel clock */
02473     switch ((uint32_t)hlptim->Instance)
02474     {
02475        case LPTIM1_BASE:
02476          __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
02477          break;
02478        case LPTIM2_BASE:
02479          __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
02480          break;
02481 #if defined(LPTIM3)
02482        case LPTIM3_BASE:
02483          __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
02484          break;
02485 #endif /* LPTIM3 */
02486 #if defined(LPTIM4)
02487        case LPTIM4_BASE:
02488          __HAL_RCC_LPTIM4_CONFIG(tmpclksource);
02489          break;
02490 #endif /* LPTIM4 */
02491 #if defined(LPTIM5)
02492        case LPTIM5_BASE:
02493          __HAL_RCC_LPTIM5_CONFIG(tmpclksource);
02494          break;
02495 #endif /* LPTIM5 */
02496        default:
02497          break;
02498     }
02499   }
02500
02501   /* Restore configuration registers (LPTIM should be disabled first) */
02502   hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
02503   hlptim->Instance->IER = tmpIER;
02504   hlptim->Instance->CFGR = tmpCFGR;
02505   hlptim->Instance->CFGR2 = tmpCFGR2;
02506
02507   __enable_irq();
02508 }
02509 /**
02510   * @}
02511   */
02512 #endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */
02513
02514 #endif /* HAL_LPTIM_MODULE_ENABLED */
02515 /**
02516   * @}
02517   */
02518
02519 /**
02520   * @}
02521   */
02522
02523 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_lptim.h Source File

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stm32h7xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_LPTIM_H
00022 #define STM32H7xx_HAL_LPTIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
00036
00037 /** @addtogroup LPTIM
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  LPTIM Clock configuration definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t Source;         /*!< Selects the clock source.
00052                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00053
00054   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00055                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00056
00057 } LPTIM_ClockConfigTypeDef;
00058
00059 /**
00060   * @brief  LPTIM Clock configuration definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00065                            if the ULPTIM input is selected.
00066                            Note: This parameter is used only when Ultra low power clock source is used.
00067                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00068                            (one of the Low power oscillator) must be active.
00069                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00070
00071   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00072                            Note: This parameter is used only when Ultra low power clock source is used.
00073                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00074
00075 } LPTIM_ULPClockConfigTypeDef;
00076
00077 /**
00078   * @brief  LPTIM Trigger configuration definition
00079   */
00080 typedef struct
00081 {
00082   uint32_t Source;        /*!< Selects the Trigger source.
00083                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00084
00085   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00086                           Note: This parameter is used only when an external trigger is used.
00087                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00088
00089   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00090                           Note: This parameter is used only when an external trigger is used.
00091                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00092 } LPTIM_TriggerConfigTypeDef;
00093
00094 /**
00095   * @brief  LPTIM Initialization Structure definition
00096   */
00097 typedef struct
00098 {
00099   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00100
00101   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00102
00103   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00104
00105   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00106                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00107
00108   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
00109                                                     values is done immediately or after the end of current period.
00110                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00111
00112   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00113                                                     or each external event.
00114                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00115
00116   uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
00117                                                     This parameter can be a value of @ref LPTIM_Input1_Source */
00118
00119   uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
00120                                                     Note: This parameter is used only for encoder feature so is used only
00121                                                     for LPTIM1 instance.
00122                                                     This parameter can be a value of @ref LPTIM_Input2_Source */
00123 } LPTIM_InitTypeDef;
00124
00125 /**
00126   * @brief  HAL LPTIM State structure definition
00127   */
00128 typedef enum
00129 {
00130   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00131   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00132   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00133   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00134   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
00135 } HAL_LPTIM_StateTypeDef;
00136
00137 /**
00138   * @brief  LPTIM handle Structure definition
00139   */
00140 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00141 typedef struct __LPTIM_HandleTypeDef
00142 #else
00143 typedef struct
00144 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00145 {
00146   LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
00147
00148   LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
00149
00150   HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
00151
00152   HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
00153
00154   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00155
00156 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00157   void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
00158   void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
00159   void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
00160   void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
00161   void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
00162   void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
00163   void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
00164   void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
00165   void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
00166 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00167 } LPTIM_HandleTypeDef;
00168
00169 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00170 /**
00171   * @brief  HAL LPTIM Callback ID enumeration definition
00172   */
00173 typedef enum
00174 {
00175   HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
00176   HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
00177   HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
00178   HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
00179   HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
00180   HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
00181   HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
00182   HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
00183   HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
00184 } HAL_LPTIM_CallbackIDTypeDef;
00185
00186 /**
00187   * @brief  HAL TIM Callback pointer definition
00188   */
00189 typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
00190
00191 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00192 /**
00193   * @}
00194   */
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00198   * @{
00199   */
00200
00201 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00202   * @{
00203   */
00204 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
00205 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00211   * @{
00212   */
00213 #define LPTIM_PRESCALER_DIV1                    0x00000000U
00214 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00215 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00216 #define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
00217 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00218 #define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
00219 #define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
00220 #define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00226   * @{
00227   */
00228
00229 #define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
00230 #define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00236   * @{
00237   */
00238 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
00239 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00240 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00241 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00247   * @{
00248   */
00249 #define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
00250 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00251 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00257   * @{
00258   */
00259 #define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
00260 #define LPTIM_TRIGSOURCE_0                      0x00000000U
00261 #define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
00262 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00263 #define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00264 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00265 #define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00266 #define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00267 #define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00273   * @{
00274   */
00275 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00276 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00277 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00283   * @{
00284   */
00285 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
00286 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00287 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00288 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00294   * @{
00295   */
00296
00297 #define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
00298 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00304   * @{
00305   */
00306
00307 #define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
00308 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00314   * @{
00315   */
00316
00317 #define LPTIM_INPUT1SOURCE_GPIO          0x00000000U                                   /*!< For LPTIM1 and LPTIM2 */
00318 #define LPTIM_INPUT1SOURCE_COMP1         LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM1 and LPTIM2 */
00319 #define LPTIM_INPUT1SOURCE_COMP2         LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM2 */
00320 #define LPTIM_INPUT1SOURCE_COMP1_COMP2   (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
00321 #define LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U                                   /*!< For LPTIM3 */
00322 #define LPTIM_INPUT1SOURCE_SAI4_FSA      LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM3 */
00323 #define LPTIM_INPUT1SOURCE_SAI4_FSB      LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM3 */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00329   * @{
00330   */
00331
00332 #define LPTIM_INPUT2SOURCE_GPIO         0x00000000U                    /*!< For LPTIM1 */
00333 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_CFGR2_IN2SEL_0           /*!< For LPTIM1 */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00339   * @{
00340   */
00341
00342 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00343 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00344 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00345 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00346 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00347 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00348 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00354   * @{
00355   */
00356 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00357 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00358 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00359 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00360 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00361 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00362 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 /* Exported macros -----------------------------------------------------------*/
00372 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00373   * @{
00374   */
00375
00376 /** @brief Reset LPTIM handle state.
00377   * @param  __HANDLE__ LPTIM handle
00378   * @retval None
00379   */
00380 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00381 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00382                                                       (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
00383                                                       (__HANDLE__)->MspInitCallback   = NULL;                  \
00384                                                       (__HANDLE__)->MspDeInitCallback = NULL;                  \
00385                                                      } while(0)
00386 #else
00387 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00388 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00389
00390 /**
00391   * @brief  Enable the LPTIM peripheral.
00392   * @param  __HANDLE__ LPTIM handle
00393   * @retval None
00394   */
00395 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
00396
00397 /**
00398   * @brief  Disable the LPTIM peripheral.
00399   * @param  __HANDLE__ LPTIM handle
00400   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00401   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00402   *         stuck in LPTIM interrupt when entering Stop mode" section.
00403   * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
00404   *         check for TIMEOUT.
00405   * @retval None
00406   */
00407 #define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
00408
00409 /**
00410   * @brief  Start the LPTIM peripheral in Continuous mode.
00411   * @param  __HANDLE__ LPTIM handle
00412   * @retval None
00413   */
00414 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00415 /**
00416   * @brief  Start the LPTIM peripheral in single mode.
00417   * @param  __HANDLE__ LPTIM handle
00418   * @retval None
00419   */
00420 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00421
00422 /**
00423   * @brief  Reset the LPTIM Counter register in synchronous mode.
00424   * @param  __HANDLE__ LPTIM handle
00425   * @retval None
00426   */
00427 #define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
00428
00429 /**
00430   * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
00431   * @param  __HANDLE__ LPTIM handle
00432   * @retval None
00433   */
00434 #define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
00435
00436 /**
00437   * @brief  Write the passed parameter in the Autoreload register.
00438   * @param  __HANDLE__ LPTIM handle
00439   * @param  __VALUE__ Autoreload value
00440   * @retval None
00441   * @note   The ARR register can only be modified when the LPTIM instance is enabled.
00442   */
00443 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00444
00445 /**
00446   * @brief  Write the passed parameter in the Compare register.
00447   * @param  __HANDLE__ LPTIM handle
00448   * @param  __VALUE__ Compare value
00449   * @retval None
00450   * @note   The CMP register can only be modified when the LPTIM instance is enabled.
00451   */
00452 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00453
00454 /**
00455   * @brief  Check whether the specified LPTIM flag is set or not.
00456   * @param  __HANDLE__ LPTIM handle
00457   * @param  __FLAG__ LPTIM flag to check
00458   *            This parameter can be a value of:
00459   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00460   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00461   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00462   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00463   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00464   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00465   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00466   * @retval The state of the specified flag (SET or RESET).
00467   */
00468 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00469
00470 /**
00471   * @brief  Clear the specified LPTIM flag.
00472   * @param  __HANDLE__ LPTIM handle.
00473   * @param  __FLAG__ LPTIM flag to clear.
00474   *            This parameter can be a value of:
00475   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00476   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00477   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00478   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00479   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00480   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00481   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00482   * @retval None.
00483   */
00484 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00485
00486 /**
00487   * @brief  Enable the specified LPTIM interrupt.
00488   * @param  __HANDLE__ LPTIM handle.
00489   * @param  __INTERRUPT__ LPTIM interrupt to set.
00490   *            This parameter can be a value of:
00491   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00492   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00493   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00494   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00495   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00496   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00497   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00498   * @retval None.
00499   * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
00500   */
00501 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00502
00503 /**
00504   * @brief  Disable the specified LPTIM interrupt.
00505   * @param  __HANDLE__ LPTIM handle.
00506   * @param  __INTERRUPT__ LPTIM interrupt to set.
00507   *            This parameter can be a value of:
00508   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00509   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00510   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00511   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00512   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00513   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00514   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00515   * @retval None.
00516   * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
00517   */
00518 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00519
00520 /**
00521   * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
00522   * @param  __HANDLE__ LPTIM handle.
00523   * @param  __INTERRUPT__ LPTIM interrupt to check.
00524   *            This parameter can be a value of:
00525   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00526   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00527   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00528   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00529   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00530   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00531   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00532   * @retval Interrupt status.
00533   */
00534
00535 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00536
00537 /**
00538   * @}
00539   */
00540
00541 /* Exported functions --------------------------------------------------------*/
00542 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00543   * @{
00544   */
00545
00546 /** @addtogroup LPTIM_Exported_Functions_Group1
00547  *  @brief    Initialization and Configuration functions.
00548  * @{
00549  */
00550 /* Initialization/de-initialization functions  ********************************/
00551 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00552 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00553
00554 /* MSP functions  *************************************************************/
00555 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00556 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00557 /**
00558   * @}
00559   */
00560
00561 /** @addtogroup LPTIM_Exported_Functions_Group2
00562  *  @brief   Start-Stop operation functions.
00563  * @{
00564  */
00565 /* Start/Stop operation functions  *********************************************/
00566 /* ################################# PWM Mode ################################*/
00567 /* Blocking mode: Polling */
00568 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00569 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00570 /* Non-Blocking mode: Interrupt */
00571 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00572 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00573
00574 /* ############################# One Pulse Mode ##############################*/
00575 /* Blocking mode: Polling */
00576 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00577 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00578 /* Non-Blocking mode: Interrupt */
00579 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00580 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00581
00582 /* ############################## Set once Mode ##############################*/
00583 /* Blocking mode: Polling */
00584 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00585 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00586 /* Non-Blocking mode: Interrupt */
00587 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00588 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00589
00590 /* ############################### Encoder Mode ##############################*/
00591 /* Blocking mode: Polling */
00592 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00593 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00594 /* Non-Blocking mode: Interrupt */
00595 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00596 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00597
00598 /* ############################# Time out  Mode ##############################*/
00599 /* Blocking mode: Polling */
00600 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00601 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00602 /* Non-Blocking mode: Interrupt */
00603 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00604 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00605
00606 /* ############################## Counter Mode ###############################*/
00607 /* Blocking mode: Polling */
00608 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00609 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00610 /* Non-Blocking mode: Interrupt */
00611 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00612 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00613 /**
00614   * @}
00615   */
00616
00617 /** @addtogroup LPTIM_Exported_Functions_Group3
00618  *  @brief  Read operation functions.
00619  * @{
00620  */
00621 /* Reading operation functions ************************************************/
00622 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00623 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00624 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00625 /**
00626   * @}
00627   */
00628
00629 /** @addtogroup LPTIM_Exported_Functions_Group4
00630  *  @brief  LPTIM IRQ handler and callback functions.
00631  * @{
00632  */
00633 /* LPTIM IRQ functions  *******************************************************/
00634 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00635
00636 /* CallBack functions  ********************************************************/
00637 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00638 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00639 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00640 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00641 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00642 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00643 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00644
00645 /* Callbacks Register/UnRegister functions  ***********************************/
00646 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00647 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
00648 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
00649 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00650 /**
00651   * @}
00652   */
00653
00654 /** @addtogroup LPTIM_Group5
00655  *  @brief   Peripheral State functions.
00656  * @{
00657  */
00658 /* Peripheral State functions  ************************************************/
00659 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00660 /**
00661   * @}
00662   */
00663
00664 /**
00665   * @}
00666   */
00667
00668 /* Private types -------------------------------------------------------------*/
00669 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00670   * @{
00671   */
00672
00673 /**
00674   * @}
00675   */
00676
00677 /* Private variables ---------------------------------------------------------*/
00678 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00679   * @{
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /* Private constants ---------------------------------------------------------*/
00687 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00688   * @{
00689   */
00690
00691 /**
00692   * @}
00693   */
00694
00695 /* Private macros ------------------------------------------------------------*/
00696 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00697   * @{
00698   */
00699
00700 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00701                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00702
00703
00704 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00705                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00706                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00707                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00708                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00709                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00710                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00711                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00712
00713 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00714
00715 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00716                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00717
00718 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00719                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00720                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00721                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00722
00723 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00724                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00725                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00726
00727 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00728                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00729                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00730                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00731                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00732                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00733                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00734                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00735                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7))
00736
00737 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00738                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00739                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00740
00741 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00742                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00743                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00744                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00745
00746 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00747                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00748
00749 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00750                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00751
00752 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)
00753
00754 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
00755
00756 #define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)
00757
00758 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
00759
00760 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)     \
00761     ((((__INSTANCE__) == LPTIM1) &&                          \
00762      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
00763       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))           \
00764      ||                                                      \
00765      (((__INSTANCE__) == LPTIM2) &&                          \
00766      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
00767       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||          \
00768       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||          \
00769       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))     \
00770      ||                                                      \
00771      (((__INSTANCE__) == LPTIM3) &&                          \
00772      (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) ||  \
00773       ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) ||       \
00774       ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))
00775
00776 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00777      ((((__INSTANCE__) == LPTIM1) ||                      \
00778        ((__INSTANCE__) == LPTIM2)) &&                     \
00779      (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00780       ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
00781
00782 /**
00783   * @}
00784   */
00785
00786 /* Private functions ---------------------------------------------------------*/
00787 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00788   * @{
00789   */
00790 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798
00799 #endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */
00800 /**
00801   * @}
00802   */
00803
00804 #ifdef __cplusplus
00805 }
00806 #endif
00807
00808 #endif /* STM32H7xx_HAL_LPTIM_H */
00809
00810 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc.c Source File

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stm32h7xx_hal_ltdc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc.c
00004   * @author  MCD Application Team
00005   * @brief   LTDC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the LTDC peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017      [..]
00018      The LTDC HAL driver can be used as follows:
00019
00020      (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef  hltdc;
00021
00022      (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
00023          (##) Enable the LTDC interface clock
00024          (##) NVIC configuration if you need to use interrupt process
00025              (+++) Configure the LTDC interrupt priority
00026              (+++) Enable the NVIC LTDC IRQ Channel
00027
00028      (#) Initialize the required configuration through the following parameters:
00029          the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
00030          Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
00031
00032      *** Configuration ***
00033      =========================
00034      [..]
00035      (#) Program the required configuration through the following parameters:
00036          the pixel format, the blending factors, input alpha value, the window size
00037          and the image size using HAL_LTDC_ConfigLayer() function for foreground
00038          or/and background layer.
00039
00040      (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
00041          HAL_LTDC_EnableCLUT functions.
00042
00043      (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
00044
00045      (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
00046          and HAL_LTDC_EnableColorKeying functions.
00047
00048      (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
00049          function
00050
00051      (#) If needed, reconfigure and change the pixel format value, the alpha value
00052          value, the window size, the window position and the layer start address
00053          for foreground or/and background layer using respectively the following
00054          functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
00055          HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
00056
00057      (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
00058          This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
00059          then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
00060
00061          After calling the _NoReload functions to set different color/format/layer settings,
00062          the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
00063          Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
00064          an immediate reload is required.
00065          Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
00066          the reload should be done in the next vertical blanking period,
00067          this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
00068
00069
00070      (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
00071
00072      *** LTDC HAL driver macros list ***
00073      =============================================
00074      [..]
00075        Below the list of most used macros in LTDC HAL driver.
00076
00077       (+) __HAL_LTDC_ENABLE: Enable the LTDC.
00078       (+) __HAL_LTDC_DISABLE: Disable the LTDC.
00079       (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
00080       (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
00081       (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
00082       (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
00083       (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
00084       (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
00085       (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
00086       (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
00087
00088      [..]
00089        (@) You can refer to the LTDC HAL driver header file for more useful macros
00090
00091
00092      *** Callback registration ***
00093      =============================================
00094      [..]
00095      The compilation define  USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
00096      allows the user to configure dynamically the driver callbacks.
00097      Use function HAL_LTDC_RegisterCallback() to register a callback.
00098
00099     [..]
00100     Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
00101       (+) LineEventCallback   : LTDC Line Event Callback.
00102       (+) ReloadEventCallback : LTDC Reload Event Callback.
00103       (+) ErrorCallback       : LTDC Error Callback
00104       (+) MspInitCallback     : LTDC MspInit.
00105       (+) MspDeInitCallback   : LTDC MspDeInit.
00106     [..]
00107     This function takes as parameters the HAL peripheral handle, the callback ID
00108     and a pointer to the user callback function.
00109
00110     [..]
00111     Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
00112     weak function.
00113     HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
00114     and the callback ID.
00115     [..]
00116     This function allows to reset following callbacks:
00117       (+) LineEventCallback   : LTDC Line Event Callback
00118       (+) ReloadEventCallback : LTDC Reload Event Callback
00119       (+) ErrorCallback       : LTDC Error Callback
00120       (+) MspInitCallback     : LTDC MspInit
00121       (+) MspDeInitCallback   : LTDC MspDeInit.
00122
00123     [..]
00124     By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
00125     all callbacks are set to the corresponding weak functions:
00126     examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
00127     Exception done for MspInit and MspDeInit functions that are
00128     reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
00129     only when these callbacks are null (not registered beforehand).
00130     If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
00131     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00132
00133     [..]
00134     Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
00135     Exception done MspInit/MspDeInit that can be registered/unregistered
00136     in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
00137     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00138     In that case first register the MspInit/MspDeInit user callbacks
00139     using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
00140     or HAL_LTDC_Init() function.
00141
00142     [..]
00143     When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
00144     not defined, the callback registration feature is not available and all callbacks
00145     are set to the corresponding weak functions.
00146
00147   @endverbatim
00148   ******************************************************************************
00149   * @attention
00150   *
00151   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00152   * All rights reserved.</center></h2>
00153   *
00154   * This software component is licensed by ST under BSD 3-Clause license,
00155   * the "License"; You may not use this file except in compliance with the
00156   * License. You may obtain a copy of the License at:
00157   *                        opensource.org/licenses/BSD-3-Clause
00158   *
00159   ******************************************************************************
00160   */
00161
00162 /* Includes ------------------------------------------------------------------*/
00163 #include "stm32h7xx_hal.h"
00164
00165 /** @addtogroup STM32H7xx_HAL_Driver
00166   * @{
00167   */
00168
00169 #ifdef HAL_LTDC_MODULE_ENABLED
00170
00171 #if defined (LTDC)
00172
00173 /** @defgroup LTDC LTDC
00174   * @brief LTDC HAL module driver
00175   * @{
00176   */
00177
00178
00179 /* Private typedef -----------------------------------------------------------*/
00180 /* Private define ------------------------------------------------------------*/
00181 /* Private macro -------------------------------------------------------------*/
00182 /* Private variables ---------------------------------------------------------*/
00183 /* Private function prototypes -----------------------------------------------*/
00184 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00185 /* Private functions ---------------------------------------------------------*/
00186
00187 /** @defgroup LTDC_Exported_Functions LTDC Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
00192   *  @brief   Initialization and Configuration functions
00193   *
00194 @verbatim
00195  ===============================================================================
00196                 ##### Initialization and Configuration functions #####
00197  ===============================================================================
00198     [..]  This section provides functions allowing to:
00199       (+) Initialize and configure the LTDC
00200       (+) De-initialize the LTDC
00201
00202 @endverbatim
00203   * @{
00204   */
00205
00206 /**
00207   * @brief  Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
00208   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00209   *                the configuration information for the LTDC.
00210   * @retval HAL status
00211   */
00212 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
00213 {
00214   uint32_t tmp, tmp1;
00215
00216   /* Check the LTDC peripheral state */
00217   if (hltdc == NULL)
00218   {
00219     return HAL_ERROR;
00220   }
00221
00222   /* Check function parameters */
00223   assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
00224   assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
00225   assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
00226   assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
00227   assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
00228   assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
00229   assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
00230   assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
00231   assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
00232   assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
00233   assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
00234   assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
00235   assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
00236
00237 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00238   if (hltdc->State == HAL_LTDC_STATE_RESET)
00239   {
00240     /* Allocate lock resource and initialize it */
00241     hltdc->Lock = HAL_UNLOCKED;
00242
00243     /* Reset the LTDC callback to the legacy weak callbacks */
00244     hltdc->LineEventCallback   = HAL_LTDC_LineEventCallback;    /* Legacy weak LineEventCallback    */
00245     hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
00246     hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
00247
00248     if (hltdc->MspInitCallback == NULL)
00249     {
00250       hltdc->MspInitCallback = HAL_LTDC_MspInit;
00251     }
00252     /* Init the low level hardware */
00253     hltdc->MspInitCallback(hltdc);
00254   }
00255 #else
00256   if (hltdc->State == HAL_LTDC_STATE_RESET)
00257   {
00258     /* Allocate lock resource and initialize it */
00259     hltdc->Lock = HAL_UNLOCKED;
00260     /* Init the low level hardware */
00261     HAL_LTDC_MspInit(hltdc);
00262   }
00263 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00264
00265   /* Change LTDC peripheral state */
00266   hltdc->State = HAL_LTDC_STATE_BUSY;
00267
00268   /* Configure the HS, VS, DE and PC polarity */
00269   hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
00270   hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
00271                                      hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
00272
00273   /* Set Synchronization size */
00274   hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
00275   tmp = (hltdc->Init.HorizontalSync << 16U);
00276   hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
00277
00278   /* Set Accumulated Back porch */
00279   hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
00280   tmp = (hltdc->Init.AccumulatedHBP << 16U);
00281   hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
00282
00283   /* Set Accumulated Active Width */
00284   hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
00285   tmp = (hltdc->Init.AccumulatedActiveW << 16U);
00286   hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
00287
00288   /* Set Total Width */
00289   hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
00290   tmp = (hltdc->Init.TotalWidth << 16U);
00291   hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
00292
00293   /* Set the background color value */
00294   tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
00295   tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
00296   hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
00297   hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
00298
00299   /* Enable the Transfer Error and FIFO underrun interrupts */
00300   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
00301
00302   /* Enable LTDC by setting LTDCEN bit */
00303   __HAL_LTDC_ENABLE(hltdc);
00304
00305   /* Initialize the error code */
00306   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00307
00308   /* Initialize the LTDC state*/
00309   hltdc->State = HAL_LTDC_STATE_READY;
00310
00311   return HAL_OK;
00312 }
00313
00314 /**
00315   * @brief  De-initialize the LTDC peripheral.
00316   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00317   *                the configuration information for the LTDC.
00318   * @retval None
00319   */
00320
00321 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
00322 {
00323 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00324   if (hltdc->MspDeInitCallback == NULL)
00325   {
00326     hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
00327   }
00328   /* DeInit the low level hardware */
00329   hltdc->MspDeInitCallback(hltdc);
00330 #else
00331   /* DeInit the low level hardware */
00332   HAL_LTDC_MspDeInit(hltdc);
00333 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00334
00335   /* Initialize the error code */
00336   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00337
00338   /* Initialize the LTDC state*/
00339   hltdc->State = HAL_LTDC_STATE_RESET;
00340
00341   /* Release Lock */
00342   __HAL_UNLOCK(hltdc);
00343
00344   return HAL_OK;
00345 }
00346
00347 /**
00348   * @brief  Initialize the LTDC MSP.
00349   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00350   *                the configuration information for the LTDC.
00351   * @retval None
00352   */
00353 __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hltdc);
00357
00358   /* NOTE : This function should not be modified, when the callback is needed,
00359             the HAL_LTDC_MspInit could be implemented in the user file
00360    */
00361 }
00362
00363 /**
00364   * @brief  De-initialize the LTDC MSP.
00365   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00366   *                the configuration information for the LTDC.
00367   * @retval None
00368   */
00369 __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
00370 {
00371   /* Prevent unused argument(s) compilation warning */
00372   UNUSED(hltdc);
00373
00374   /* NOTE : This function should not be modified, when the callback is needed,
00375             the HAL_LTDC_MspDeInit could be implemented in the user file
00376    */
00377 }
00378
00379 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00380 /**
00381   * @brief  Register a User LTDC Callback
00382   *         To be used instead of the weak predefined callback
00383   * @param hltdc ltdc handle
00384   * @param CallbackID ID of the callback to be registered
00385   *        This parameter can be one of the following values:
00386   *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
00387   *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
00388   *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
00389   *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
00390   *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
00391   * @param pCallback pointer to the Callback function
00392   * @retval status
00393   */
00394 HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
00395 {
00396   HAL_StatusTypeDef status = HAL_OK;
00397
00398   if (pCallback == NULL)
00399   {
00400     /* Update the error code */
00401     hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00402
00403     return HAL_ERROR;
00404   }
00405   /* Process locked */
00406   __HAL_LOCK(hltdc);
00407
00408   if (hltdc->State == HAL_LTDC_STATE_READY)
00409   {
00410     switch (CallbackID)
00411     {
00412       case HAL_LTDC_LINE_EVENT_CB_ID :
00413         hltdc->LineEventCallback = pCallback;
00414         break;
00415
00416       case HAL_LTDC_RELOAD_EVENT_CB_ID :
00417         hltdc->ReloadEventCallback = pCallback;
00418         break;
00419
00420       case HAL_LTDC_ERROR_CB_ID :
00421         hltdc->ErrorCallback = pCallback;
00422         break;
00423
00424       case HAL_LTDC_MSPINIT_CB_ID :
00425         hltdc->MspInitCallback = pCallback;
00426         break;
00427
00428       case HAL_LTDC_MSPDEINIT_CB_ID :
00429         hltdc->MspDeInitCallback = pCallback;
00430         break;
00431
00432       default :
00433         /* Update the error code */
00434         hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00435         /* Return error status */
00436         status =  HAL_ERROR;
00437         break;
00438     }
00439   }
00440   else if (hltdc->State == HAL_LTDC_STATE_RESET)
00441   {
00442     switch (CallbackID)
00443     {
00444       case HAL_LTDC_MSPINIT_CB_ID :
00445         hltdc->MspInitCallback = pCallback;
00446         break;
00447
00448       case HAL_LTDC_MSPDEINIT_CB_ID :
00449         hltdc->MspDeInitCallback = pCallback;
00450         break;
00451
00452       default :
00453         /* Update the error code */
00454         hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00455         /* Return error status */
00456         status =  HAL_ERROR;
00457         break;
00458     }
00459   }
00460   else
00461   {
00462     /* Update the error code */
00463     hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00464     /* Return error status */
00465     status =  HAL_ERROR;
00466   }
00467
00468   /* Release Lock */
00469   __HAL_UNLOCK(hltdc);
00470
00471   return status;
00472 }
00473
00474 /**
00475   * @brief  Unregister an LTDC Callback
00476   *         LTDC callabck is redirected to the weak predefined callback
00477   * @param hltdc ltdc handle
00478   * @param CallbackID ID of the callback to be unregistered
00479   *        This parameter can be one of the following values:
00480   *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
00481   *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
00482   *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
00483   *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
00484   *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
00485   * @retval status
00486   */
00487 HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
00488 {
00489   HAL_StatusTypeDef status = HAL_OK;
00490
00491   /* Process locked */
00492   __HAL_LOCK(hltdc);
00493
00494   if (hltdc->State == HAL_LTDC_STATE_READY)
00495   {
00496     switch (CallbackID)
00497     {
00498       case HAL_LTDC_LINE_EVENT_CB_ID :
00499         hltdc->LineEventCallback = HAL_LTDC_LineEventCallback;      /* Legacy weak LineEventCallback    */
00500         break;
00501
00502       case HAL_LTDC_RELOAD_EVENT_CB_ID :
00503         hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
00504         break;
00505
00506       case HAL_LTDC_ERROR_CB_ID :
00507         hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
00508         break;
00509
00510       case HAL_LTDC_MSPINIT_CB_ID :
00511         hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
00512         break;
00513
00514       case HAL_LTDC_MSPDEINIT_CB_ID :
00515         hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
00516         break;
00517
00518       default :
00519         /* Update the error code */
00520         hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00521         /* Return error status */
00522         status =  HAL_ERROR;
00523         break;
00524     }
00525   }
00526   else if (hltdc->State == HAL_LTDC_STATE_RESET)
00527   {
00528     switch (CallbackID)
00529     {
00530       case HAL_LTDC_MSPINIT_CB_ID :
00531         hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
00532         break;
00533
00534       case HAL_LTDC_MSPDEINIT_CB_ID :
00535         hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
00536         break;
00537
00538       default :
00539         /* Update the error code */
00540         hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00541         /* Return error status */
00542         status =  HAL_ERROR;
00543         break;
00544     }
00545   }
00546   else
00547   {
00548     /* Update the error code */
00549     hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
00550     /* Return error status */
00551     status =  HAL_ERROR;
00552   }
00553
00554   /* Release Lock */
00555   __HAL_UNLOCK(hltdc);
00556
00557   return status;
00558 }
00559 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00560
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
00566   *  @brief   IO operation functions
00567   *
00568 @verbatim
00569  ===============================================================================
00570                       #####  IO operation functions  #####
00571  ===============================================================================
00572     [..]  This section provides function allowing to:
00573       (+) Handle LTDC interrupt request
00574
00575 @endverbatim
00576   * @{
00577   */
00578 /**
00579   * @brief  Handle LTDC interrupt request.
00580   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00581   *                the configuration information for the LTDC.
00582   * @retval HAL status
00583   */
00584 void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
00585 {
00586   uint32_t isrflags  = READ_REG(hltdc->Instance->ISR);
00587   uint32_t itsources = READ_REG(hltdc->Instance->IER);
00588
00589   /* Transfer Error Interrupt management ***************************************/
00590   if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
00591   {
00592     /* Disable the transfer Error interrupt */
00593     __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
00594
00595     /* Clear the transfer error flag */
00596     __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
00597
00598     /* Update error code */
00599     hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
00600
00601     /* Change LTDC state */
00602     hltdc->State = HAL_LTDC_STATE_ERROR;
00603
00604     /* Process unlocked */
00605     __HAL_UNLOCK(hltdc);
00606
00607     /* Transfer error Callback */
00608 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00609     /*Call registered error callback*/
00610     hltdc->ErrorCallback(hltdc);
00611 #else
00612     /* Call legacy error callback*/
00613     HAL_LTDC_ErrorCallback(hltdc);
00614 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00615   }
00616
00617   /* FIFO underrun Interrupt management ***************************************/
00618   if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
00619   {
00620     /* Disable the FIFO underrun interrupt */
00621     __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
00622
00623     /* Clear the FIFO underrun flag */
00624     __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
00625
00626     /* Update error code */
00627     hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
00628
00629     /* Change LTDC state */
00630     hltdc->State = HAL_LTDC_STATE_ERROR;
00631
00632     /* Process unlocked */
00633     __HAL_UNLOCK(hltdc);
00634
00635     /* Transfer error Callback */
00636 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00637     /*Call registered error callback*/
00638     hltdc->ErrorCallback(hltdc);
00639 #else
00640     /* Call legacy error callback*/
00641     HAL_LTDC_ErrorCallback(hltdc);
00642 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00643   }
00644
00645   /* Line Interrupt management ************************************************/
00646   if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
00647   {
00648     /* Disable the Line interrupt */
00649     __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
00650
00651     /* Clear the Line interrupt flag */
00652     __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
00653
00654     /* Change LTDC state */
00655     hltdc->State = HAL_LTDC_STATE_READY;
00656
00657     /* Process unlocked */
00658     __HAL_UNLOCK(hltdc);
00659
00660     /* Line interrupt Callback */
00661 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00662     /*Call registered Line Event callback */
00663     hltdc->LineEventCallback(hltdc);
00664 #else
00665     /*Call Legacy Line Event callback */
00666     HAL_LTDC_LineEventCallback(hltdc);
00667 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00668   }
00669
00670   /* Register reload Interrupt management ***************************************/
00671   if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
00672   {
00673     /* Disable the register reload interrupt */
00674     __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
00675
00676     /* Clear the register reload flag */
00677     __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
00678
00679     /* Change LTDC state */
00680     hltdc->State = HAL_LTDC_STATE_READY;
00681
00682     /* Process unlocked */
00683     __HAL_UNLOCK(hltdc);
00684
00685     /* Reload interrupt Callback */
00686 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00687     /*Call registered reload Event callback */
00688     hltdc->ReloadEventCallback(hltdc);
00689 #else
00690     /*Call Legacy Reload Event callback */
00691     HAL_LTDC_ReloadEventCallback(hltdc);
00692 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00693   }
00694 }
00695
00696 /**
00697   * @brief  Error LTDC callback.
00698   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00699   *                the configuration information for the LTDC.
00700   * @retval None
00701   */
00702 __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
00703 {
00704   /* Prevent unused argument(s) compilation warning */
00705   UNUSED(hltdc);
00706
00707   /* NOTE : This function should not be modified, when the callback is needed,
00708             the HAL_LTDC_ErrorCallback could be implemented in the user file
00709    */
00710 }
00711
00712 /**
00713   * @brief  Line Event callback.
00714   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00715   *                the configuration information for the LTDC.
00716   * @retval None
00717   */
00718 __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
00719 {
00720   /* Prevent unused argument(s) compilation warning */
00721   UNUSED(hltdc);
00722
00723   /* NOTE : This function should not be modified, when the callback is needed,
00724             the HAL_LTDC_LineEventCallback could be implemented in the user file
00725    */
00726 }
00727
00728 /**
00729   * @brief  Reload Event callback.
00730   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00731   *                the configuration information for the LTDC.
00732   * @retval None
00733   */
00734 __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
00735 {
00736   /* Prevent unused argument(s) compilation warning */
00737   UNUSED(hltdc);
00738
00739   /* NOTE : This function should not be modified, when the callback is needed,
00740             the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
00741    */
00742 }
00743
00744 /**
00745   * @}
00746   */
00747
00748 /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
00749   *  @brief    Peripheral Control functions
00750   *
00751 @verbatim
00752  ===============================================================================
00753                     ##### Peripheral Control functions #####
00754  ===============================================================================
00755     [..]  This section provides functions allowing to:
00756       (+) Configure the LTDC foreground or/and background parameters.
00757       (+) Set the active layer.
00758       (+) Configure the color keying.
00759       (+) Configure the C-LUT.
00760       (+) Enable / Disable the color keying.
00761       (+) Enable / Disable the C-LUT.
00762       (+) Update the layer position.
00763       (+) Update the layer size.
00764       (+) Update pixel format on the fly.
00765       (+) Update transparency on the fly.
00766       (+) Update address on the fly.
00767
00768 @endverbatim
00769   * @{
00770   */
00771
00772 /**
00773   * @brief  Configure the LTDC Layer according to the specified
00774   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00775   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
00776   *                    the configuration information for the LTDC.
00777   * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
00778   *                    the configuration information for the Layer.
00779   * @param  LayerIdx  LTDC Layer index.
00780   *                    This parameter can be one of the following values:
00781   *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00782   * @retval HAL status
00783   */
00784 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
00785 {
00786   /* Check the parameters */
00787   assert_param(IS_LTDC_LAYER(LayerIdx));
00788   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00789   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00790   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00791   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00792   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
00793   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
00794   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
00795   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
00796   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
00797   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
00798   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
00799
00800   /* Process locked */
00801   __HAL_LOCK(hltdc);
00802
00803   /* Change LTDC peripheral state */
00804   hltdc->State = HAL_LTDC_STATE_BUSY;
00805
00806   /* Copy new layer configuration into handle structure */
00807   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
00808
00809   /* Configure the LTDC Layer */
00810   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00811
00812   /* Set the Immediate Reload type */
00813   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00814
00815   /* Initialize the LTDC state*/
00816   hltdc->State  = HAL_LTDC_STATE_READY;
00817
00818   /* Process unlocked */
00819   __HAL_UNLOCK(hltdc);
00820
00821   return HAL_OK;
00822 }
00823
00824 /**
00825   * @brief  Configure the color keying.
00826   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00827   *                   the configuration information for the LTDC.
00828   * @param  RGBValue  the color key value
00829   * @param  LayerIdx  LTDC Layer index.
00830   *                   This parameter can be one of the following values:
00831   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
00835 {
00836   /* Check the parameters */
00837   assert_param(IS_LTDC_LAYER(LayerIdx));
00838
00839   /* Process locked */
00840   __HAL_LOCK(hltdc);
00841
00842   /* Change LTDC peripheral state */
00843   hltdc->State = HAL_LTDC_STATE_BUSY;
00844
00845   /* Configure the default color values */
00846   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
00847   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
00848
00849   /* Set the Immediate Reload type */
00850   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00851
00852   /* Change the LTDC state*/
00853   hltdc->State = HAL_LTDC_STATE_READY;
00854
00855   /* Process unlocked */
00856   __HAL_UNLOCK(hltdc);
00857
00858   return HAL_OK;
00859 }
00860
00861 /**
00862   * @brief  Load the color lookup table.
00863   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00864   *                   the configuration information for the LTDC.
00865   * @param  pCLUT     pointer to the color lookup table address.
00866   * @param  CLUTSize  the color lookup table size.
00867   * @param  LayerIdx  LTDC Layer index.
00868   *                   This parameter can be one of the following values:
00869   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
00873 {
00874   uint32_t tmp;
00875   uint32_t counter;
00876   uint32_t *pcolorlut = pCLUT;
00877   /* Check the parameters */
00878   assert_param(IS_LTDC_LAYER(LayerIdx));
00879
00880   /* Process locked */
00881   __HAL_LOCK(hltdc);
00882
00883   /* Change LTDC peripheral state */
00884   hltdc->State = HAL_LTDC_STATE_BUSY;
00885
00886   for (counter = 0U; (counter < CLUTSize); counter++)
00887   {
00888     if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
00889     {
00890       tmp  = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
00891     }
00892     else
00893     {
00894       tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
00895     }
00896
00897     pcolorlut++;
00898
00899     /* Specifies the C-LUT address and RGB value */
00900     LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
00901   }
00902
00903   /* Change the LTDC state*/
00904   hltdc->State = HAL_LTDC_STATE_READY;
00905
00906   /* Process unlocked */
00907   __HAL_UNLOCK(hltdc);
00908
00909   return HAL_OK;
00910 }
00911
00912 /**
00913   * @brief  Enable the color keying.
00914   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00915   *                   the configuration information for the LTDC.
00916   * @param  LayerIdx  LTDC Layer index.
00917   *                   This parameter can be one of the following values:
00918   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00919   * @retval  HAL status
00920   */
00921 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00922 {
00923   /* Check the parameters */
00924   assert_param(IS_LTDC_LAYER(LayerIdx));
00925
00926   /* Process locked */
00927   __HAL_LOCK(hltdc);
00928
00929   /* Change LTDC peripheral state */
00930   hltdc->State = HAL_LTDC_STATE_BUSY;
00931
00932   /* Enable LTDC color keying by setting COLKEN bit */
00933   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
00934
00935   /* Set the Immediate Reload type */
00936   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00937
00938   /* Change the LTDC state*/
00939   hltdc->State = HAL_LTDC_STATE_READY;
00940
00941   /* Process unlocked */
00942   __HAL_UNLOCK(hltdc);
00943
00944   return HAL_OK;
00945 }
00946
00947 /**
00948   * @brief  Disable the color keying.
00949   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00950   *                   the configuration information for the LTDC.
00951   * @param  LayerIdx  LTDC Layer index.
00952   *                   This parameter can be one of the following values:
00953   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00954   * @retval  HAL status
00955   */
00956 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00957 {
00958   /* Check the parameters */
00959   assert_param(IS_LTDC_LAYER(LayerIdx));
00960
00961   /* Process locked */
00962   __HAL_LOCK(hltdc);
00963
00964   /* Change LTDC peripheral state */
00965   hltdc->State = HAL_LTDC_STATE_BUSY;
00966
00967   /* Disable LTDC color keying by setting COLKEN bit */
00968   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
00969
00970   /* Set the Immediate Reload type */
00971   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00972
00973   /* Change the LTDC state*/
00974   hltdc->State = HAL_LTDC_STATE_READY;
00975
00976   /* Process unlocked */
00977   __HAL_UNLOCK(hltdc);
00978
00979   return HAL_OK;
00980 }
00981
00982 /**
00983   * @brief  Enable the color lookup table.
00984   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00985   *                   the configuration information for the LTDC.
00986   * @param  LayerIdx  LTDC Layer index.
00987   *                   This parameter can be one of the following values:
00988   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00989   * @retval  HAL status
00990   */
00991 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00992 {
00993   /* Check the parameters */
00994   assert_param(IS_LTDC_LAYER(LayerIdx));
00995
00996   /* Process locked */
00997   __HAL_LOCK(hltdc);
00998
00999   /* Change LTDC peripheral state */
01000   hltdc->State = HAL_LTDC_STATE_BUSY;
01001
01002   /* Enable LTDC color lookup table by setting CLUTEN bit */
01003   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
01004
01005   /* Set the Immediate Reload type */
01006   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01007
01008   /* Change the LTDC state*/
01009   hltdc->State = HAL_LTDC_STATE_READY;
01010
01011   /* Process unlocked */
01012   __HAL_UNLOCK(hltdc);
01013
01014   return HAL_OK;
01015 }
01016
01017 /**
01018   * @brief  Disable the color lookup table.
01019   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01020   *                   the configuration information for the LTDC.
01021   * @param  LayerIdx  LTDC Layer index.
01022   *                   This parameter can be one of the following values:
01023   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01024   * @retval  HAL status
01025   */
01026 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01027 {
01028   /* Check the parameters */
01029   assert_param(IS_LTDC_LAYER(LayerIdx));
01030
01031   /* Process locked */
01032   __HAL_LOCK(hltdc);
01033
01034   /* Change LTDC peripheral state */
01035   hltdc->State = HAL_LTDC_STATE_BUSY;
01036
01037   /* Disable LTDC color lookup table by setting CLUTEN bit */
01038   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
01039
01040   /* Set the Immediate Reload type */
01041   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01042
01043   /* Change the LTDC state*/
01044   hltdc->State = HAL_LTDC_STATE_READY;
01045
01046   /* Process unlocked */
01047   __HAL_UNLOCK(hltdc);
01048
01049   return HAL_OK;
01050 }
01051
01052 /**
01053   * @brief  Enable Dither.
01054   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
01055   *                the configuration information for the LTDC.
01056   * @retval  HAL status
01057   */
01058
01059 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
01060 {
01061   /* Process locked */
01062   __HAL_LOCK(hltdc);
01063
01064   /* Change LTDC peripheral state */
01065   hltdc->State = HAL_LTDC_STATE_BUSY;
01066
01067   /* Enable Dither by setting DTEN bit */
01068   LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
01069
01070   /* Change the LTDC state*/
01071   hltdc->State = HAL_LTDC_STATE_READY;
01072
01073   /* Process unlocked */
01074   __HAL_UNLOCK(hltdc);
01075
01076   return HAL_OK;
01077 }
01078
01079 /**
01080   * @brief  Disable Dither.
01081   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
01082   *                the configuration information for the LTDC.
01083   * @retval  HAL status
01084   */
01085
01086 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
01087 {
01088   /* Process locked */
01089   __HAL_LOCK(hltdc);
01090
01091   /* Change LTDC peripheral state */
01092   hltdc->State = HAL_LTDC_STATE_BUSY;
01093
01094   /* Disable Dither by setting DTEN bit */
01095   LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
01096
01097   /* Change the LTDC state*/
01098   hltdc->State = HAL_LTDC_STATE_READY;
01099
01100   /* Process unlocked */
01101   __HAL_UNLOCK(hltdc);
01102
01103   return HAL_OK;
01104 }
01105
01106 /**
01107   * @brief  Set the LTDC window size.
01108   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01109   *                   the configuration information for the LTDC.
01110   * @param  XSize     LTDC Pixel per line
01111   * @param  YSize     LTDC Line number
01112   * @param  LayerIdx  LTDC Layer index.
01113   *                   This parameter can be one of the following values:
01114   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01115   * @retval  HAL status
01116   */
01117 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
01118 {
01119   LTDC_LayerCfgTypeDef *pLayerCfg;
01120
01121   /* Check the parameters (Layers parameters)*/
01122   assert_param(IS_LTDC_LAYER(LayerIdx));
01123   assert_param(IS_LTDC_CFBLL(XSize));
01124   assert_param(IS_LTDC_CFBLNBR(YSize));
01125
01126   /* Process locked */
01127   __HAL_LOCK(hltdc);
01128
01129   /* Change LTDC peripheral state */
01130   hltdc->State = HAL_LTDC_STATE_BUSY;
01131
01132   /* Get layer configuration from handle structure */
01133   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01134
01135   /* update horizontal stop */
01136   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
01137
01138   /* update vertical stop */
01139   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
01140
01141   /* Reconfigures the color frame buffer pitch in byte */
01142   pLayerCfg->ImageWidth = XSize;
01143
01144   /* Reconfigures the frame buffer line number */
01145   pLayerCfg->ImageHeight = YSize;
01146
01147   /* Set LTDC parameters */
01148   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01149
01150   /* Set the Immediate Reload type */
01151   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01152
01153   /* Change the LTDC state*/
01154   hltdc->State = HAL_LTDC_STATE_READY;
01155
01156   /* Process unlocked */
01157   __HAL_UNLOCK(hltdc);
01158
01159   return HAL_OK;
01160 }
01161
01162 /**
01163   * @brief  Set the LTDC window position.
01164   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01165   *                   the configuration information for the LTDC.
01166   * @param  X0        LTDC window X offset
01167   * @param  Y0        LTDC window Y offset
01168   * @param  LayerIdx  LTDC Layer index.
01169   *                         This parameter can be one of the following values:
01170   *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01171   * @retval  HAL status
01172   */
01173 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
01174 {
01175   LTDC_LayerCfgTypeDef *pLayerCfg;
01176
01177   /* Check the parameters */
01178   assert_param(IS_LTDC_LAYER(LayerIdx));
01179   assert_param(IS_LTDC_CFBLL(X0));
01180   assert_param(IS_LTDC_CFBLNBR(Y0));
01181
01182   /* Process locked */
01183   __HAL_LOCK(hltdc);
01184
01185   /* Change LTDC peripheral state */
01186   hltdc->State = HAL_LTDC_STATE_BUSY;
01187
01188   /* Get layer configuration from handle structure */
01189   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01190
01191   /* update horizontal start/stop */
01192   pLayerCfg->WindowX0 = X0;
01193   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
01194
01195   /* update vertical start/stop */
01196   pLayerCfg->WindowY0 = Y0;
01197   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
01198
01199   /* Set LTDC parameters */
01200   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01201
01202   /* Set the Immediate Reload type */
01203   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01204
01205   /* Change the LTDC state*/
01206   hltdc->State = HAL_LTDC_STATE_READY;
01207
01208   /* Process unlocked */
01209   __HAL_UNLOCK(hltdc);
01210
01211   return HAL_OK;
01212 }
01213
01214 /**
01215   * @brief  Reconfigure the pixel format.
01216   * @param  hltdc        pointer to a LTDC_HandleTypeDef structure that contains
01217   *                      the configuration information for the LTDC.
01218   * @param  Pixelformat  new pixel format value.
01219   * @param  LayerIdx     LTDC Layer index.
01220   *                      This parameter can be one of the following values:
01221   *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01222   * @retval  HAL status
01223   */
01224 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
01225 {
01226   LTDC_LayerCfgTypeDef *pLayerCfg;
01227
01228   /* Check the parameters */
01229   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
01230   assert_param(IS_LTDC_LAYER(LayerIdx));
01231
01232   /* Process locked */
01233   __HAL_LOCK(hltdc);
01234
01235   /* Change LTDC peripheral state */
01236   hltdc->State = HAL_LTDC_STATE_BUSY;
01237
01238   /* Get layer configuration from handle structure */
01239   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01240
01241   /* Reconfigure the pixel format */
01242   pLayerCfg->PixelFormat = Pixelformat;
01243
01244   /* Set LTDC parameters */
01245   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01246
01247   /* Set the Immediate Reload type */
01248   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01249
01250   /* Change the LTDC state*/
01251   hltdc->State = HAL_LTDC_STATE_READY;
01252
01253   /* Process unlocked */
01254   __HAL_UNLOCK(hltdc);
01255
01256   return HAL_OK;
01257 }
01258
01259 /**
01260   * @brief  Reconfigure the layer alpha value.
01261   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01262   *                   the configuration information for the LTDC.
01263   * @param  Alpha     new alpha value.
01264   * @param  LayerIdx  LTDC Layer index.
01265   *                   This parameter can be one of the following values:
01266   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01267   * @retval  HAL status
01268   */
01269 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
01270 {
01271   LTDC_LayerCfgTypeDef *pLayerCfg;
01272
01273   /* Check the parameters */
01274   assert_param(IS_LTDC_ALPHA(Alpha));
01275   assert_param(IS_LTDC_LAYER(LayerIdx));
01276
01277   /* Process locked */
01278   __HAL_LOCK(hltdc);
01279
01280   /* Change LTDC peripheral state */
01281   hltdc->State = HAL_LTDC_STATE_BUSY;
01282
01283   /* Get layer configuration from handle structure */
01284   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01285
01286   /* Reconfigure the Alpha value */
01287   pLayerCfg->Alpha = Alpha;
01288
01289   /* Set LTDC parameters */
01290   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01291
01292   /* Set the Immediate Reload type */
01293   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01294
01295   /* Change the LTDC state*/
01296   hltdc->State = HAL_LTDC_STATE_READY;
01297
01298   /* Process unlocked */
01299   __HAL_UNLOCK(hltdc);
01300
01301   return HAL_OK;
01302 }
01303 /**
01304   * @brief  Reconfigure the frame buffer Address.
01305   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01306   *                   the configuration information for the LTDC.
01307   * @param  Address   new address value.
01308   * @param  LayerIdx  LTDC Layer index.
01309   *                   This parameter can be one of the following values:
01310   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01311   * @retval  HAL status
01312   */
01313 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
01314 {
01315   LTDC_LayerCfgTypeDef *pLayerCfg;
01316
01317   /* Check the parameters */
01318   assert_param(IS_LTDC_LAYER(LayerIdx));
01319
01320   /* Process locked */
01321   __HAL_LOCK(hltdc);
01322
01323   /* Change LTDC peripheral state */
01324   hltdc->State = HAL_LTDC_STATE_BUSY;
01325
01326   /* Get layer configuration from handle structure */
01327   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01328
01329   /* Reconfigure the Address */
01330   pLayerCfg->FBStartAdress = Address;
01331
01332   /* Set LTDC parameters */
01333   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01334
01335   /* Set the Immediate Reload type */
01336   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01337
01338   /* Change the LTDC state*/
01339   hltdc->State = HAL_LTDC_STATE_READY;
01340
01341   /* Process unlocked */
01342   __HAL_UNLOCK(hltdc);
01343
01344   return HAL_OK;
01345 }
01346
01347 /**
01348   * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
01349   *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
01350   *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
01351   *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
01352   * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
01353   *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
01354   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
01355   *                            the configuration information for the LTDC.
01356   * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
01357   * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
01358   * @retval HAL status
01359   */
01360 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
01361 {
01362   uint32_t tmp;
01363   uint32_t pitchUpdate;
01364   uint32_t pixelFormat;
01365
01366   /* Check the parameters */
01367   assert_param(IS_LTDC_LAYER(LayerIdx));
01368
01369   /* Process locked */
01370   __HAL_LOCK(hltdc);
01371
01372   /* Change LTDC peripheral state */
01373   hltdc->State = HAL_LTDC_STATE_BUSY;
01374
01375   /* get LayerIdx used pixel format */
01376   pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
01377
01378   if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01379   {
01380     tmp = 4U;
01381   }
01382   else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01383   {
01384     tmp = 3U;
01385   }
01386   else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01387            (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01388            (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01389            (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
01390   {
01391     tmp = 2U;
01392   }
01393   else
01394   {
01395     tmp = 1U;
01396   }
01397
01398   pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
01399
01400   /* Clear previously set standard pitch */
01401   LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
01402
01403   /* Set the Reload type as immediate update of LTDC pitch configured above */
01404   LTDC->SRCR |= LTDC_SRCR_IMR;
01405
01406   /* Set new line pitch value */
01407   LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
01408
01409   /* Set the Reload type as immediate update of LTDC pitch configured above */
01410   LTDC->SRCR |= LTDC_SRCR_IMR;
01411
01412   /* Change the LTDC state*/
01413   hltdc->State = HAL_LTDC_STATE_READY;
01414
01415   /* Process unlocked */
01416   __HAL_UNLOCK(hltdc);
01417
01418   return HAL_OK;
01419 }
01420
01421 /**
01422   * @brief  Define the position of the line interrupt.
01423   * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
01424   *                 the configuration information for the LTDC.
01425   * @param  Line    Line Interrupt Position.
01426   * @note   User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
01427   * @retval  HAL status
01428   */
01429 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
01430 {
01431   /* Check the parameters */
01432   assert_param(IS_LTDC_LIPOS(Line));
01433
01434   /* Process locked */
01435   __HAL_LOCK(hltdc);
01436
01437   /* Change LTDC peripheral state */
01438   hltdc->State = HAL_LTDC_STATE_BUSY;
01439
01440   /* Disable the Line interrupt */
01441   __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
01442
01443   /* Set the Line Interrupt position */
01444   LTDC->LIPCR = (uint32_t)Line;
01445
01446   /* Enable the Line interrupt */
01447   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
01448
01449   /* Change the LTDC state*/
01450   hltdc->State = HAL_LTDC_STATE_READY;
01451
01452   /* Process unlocked */
01453   __HAL_UNLOCK(hltdc);
01454
01455   return HAL_OK;
01456 }
01457
01458 /**
01459   * @brief  Reload LTDC Layers configuration.
01460   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
01461   *                    the configuration information for the LTDC.
01462   * @param  ReloadType This parameter can be one of the following values :
01463   *                      LTDC_RELOAD_IMMEDIATE : Immediate Reload
01464   *                      LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking
01465   * @note   User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
01466   * @retval  HAL status
01467   */
01468 HAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
01469 {
01470   /* Check the parameters */
01471   assert_param(IS_LTDC_RELOAD(ReloadType));
01472
01473   /* Process locked */
01474   __HAL_LOCK(hltdc);
01475
01476   /* Change LTDC peripheral state */
01477   hltdc->State = HAL_LTDC_STATE_BUSY;
01478
01479   /* Enable the Reload interrupt */
01480   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
01481
01482   /* Apply Reload type */
01483   hltdc->Instance->SRCR = ReloadType;
01484
01485   /* Change the LTDC state*/
01486   hltdc->State = HAL_LTDC_STATE_READY;
01487
01488   /* Process unlocked */
01489   __HAL_UNLOCK(hltdc);
01490
01491   return HAL_OK;
01492 }
01493
01494 /**
01495   * @brief  Configure the LTDC Layer according to the specified without reloading
01496   *         parameters in the LTDC_InitTypeDef and create the associated handle.
01497   *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
01498   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
01499   *                    the configuration information for the LTDC.
01500   * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
01501   *                    the configuration information for the Layer.
01502   * @param  LayerIdx   LTDC Layer index.
01503   *                    This parameter can be one of the following values:
01504   *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01505   * @retval HAL status
01506   */
01507 HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
01508 {
01509   /* Check the parameters */
01510   assert_param(IS_LTDC_LAYER(LayerIdx));
01511   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
01512   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
01513   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
01514   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
01515   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
01516   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
01517   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
01518   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
01519   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
01520   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
01521   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
01522
01523   /* Process locked */
01524   __HAL_LOCK(hltdc);
01525
01526   /* Change LTDC peripheral state */
01527   hltdc->State = HAL_LTDC_STATE_BUSY;
01528
01529   /* Copy new layer configuration into handle structure */
01530   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
01531
01532   /* Configure the LTDC Layer */
01533   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01534
01535   /* Initialize the LTDC state*/
01536   hltdc->State  = HAL_LTDC_STATE_READY;
01537
01538   /* Process unlocked */
01539   __HAL_UNLOCK(hltdc);
01540
01541   return HAL_OK;
01542 }
01543
01544 /**
01545   * @brief  Set the LTDC window size without reloading.
01546   *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
01547   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01548   *                   the configuration information for the LTDC.
01549   * @param  XSize     LTDC Pixel per line
01550   * @param  YSize     LTDC Line number
01551   * @param  LayerIdx  LTDC Layer index.
01552   *                   This parameter can be one of the following values:
01553   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01554   * @retval  HAL status
01555   */
01556 HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
01557 {
01558   LTDC_LayerCfgTypeDef *pLayerCfg;
01559
01560   /* Check the parameters (Layers parameters)*/
01561   assert_param(IS_LTDC_LAYER(LayerIdx));
01562   assert_param(IS_LTDC_CFBLL(XSize));
01563   assert_param(IS_LTDC_CFBLNBR(YSize));
01564
01565   /* Process locked */
01566   __HAL_LOCK(hltdc);
01567
01568   /* Change LTDC peripheral state */
01569   hltdc->State = HAL_LTDC_STATE_BUSY;
01570
01571   /* Get layer configuration from handle structure */
01572   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01573
01574   /* update horizontal stop */
01575   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
01576
01577   /* update vertical stop */
01578   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
01579
01580   /* Reconfigures the color frame buffer pitch in byte */
01581   pLayerCfg->ImageWidth = XSize;
01582
01583   /* Reconfigures the frame buffer line number */
01584   pLayerCfg->ImageHeight = YSize;
01585
01586   /* Set LTDC parameters */
01587   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01588
01589   /* Change the LTDC state*/
01590   hltdc->State = HAL_LTDC_STATE_READY;
01591
01592   /* Process unlocked */
01593   __HAL_UNLOCK(hltdc);
01594
01595   return HAL_OK;
01596 }
01597
01598 /**
01599   * @brief  Set the LTDC window position without reloading.
01600   *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
01601   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01602   *                   the configuration information for the LTDC.
01603   * @param  X0        LTDC window X offset
01604   * @param  Y0        LTDC window Y offset
01605   * @param  LayerIdx  LTDC Layer index.
01606   *                         This parameter can be one of the following values:
01607   *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01608   * @retval  HAL status
01609   */
01610 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
01611 {
01612   LTDC_LayerCfgTypeDef *pLayerCfg;
01613
01614   /* Check the parameters */
01615   assert_param(IS_LTDC_LAYER(LayerIdx));
01616   assert_param(IS_LTDC_CFBLL(X0));
01617   assert_param(IS_LTDC_CFBLNBR(Y0));
01618
01619   /* Process locked */
01620   __HAL_LOCK(hltdc);
01621
01622   /* Change LTDC peripheral state */
01623   hltdc->State = HAL_LTDC_STATE_BUSY;
01624
01625   /* Get layer configuration from handle structure */
01626   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01627
01628   /* update horizontal start/stop */
01629   pLayerCfg->WindowX0 = X0;
01630   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
01631
01632   /* update vertical start/stop */
01633   pLayerCfg->WindowY0 = Y0;
01634   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
01635
01636   /* Set LTDC parameters */
01637   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01638
01639   /* Change the LTDC state*/
01640   hltdc->State = HAL_LTDC_STATE_READY;
01641
01642   /* Process unlocked */
01643   __HAL_UNLOCK(hltdc);
01644
01645   return HAL_OK;
01646 }
01647
01648 /**
01649   * @brief  Reconfigure the pixel format without reloading.
01650   *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
01651   * @param  hltdc        pointer to a LTDC_HandleTypeDfef structure that contains
01652   *                      the configuration information for the LTDC.
01653   * @param  Pixelformat  new pixel format value.
01654   * @param  LayerIdx     LTDC Layer index.
01655   *                      This parameter can be one of the following values:
01656   *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01657   * @retval  HAL status
01658   */
01659 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
01660 {
01661   LTDC_LayerCfgTypeDef *pLayerCfg;
01662
01663   /* Check the parameters */
01664   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
01665   assert_param(IS_LTDC_LAYER(LayerIdx));
01666
01667   /* Process locked */
01668   __HAL_LOCK(hltdc);
01669
01670   /* Change LTDC peripheral state */
01671   hltdc->State = HAL_LTDC_STATE_BUSY;
01672
01673   /* Get layer configuration from handle structure */
01674   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01675
01676   /* Reconfigure the pixel format */
01677   pLayerCfg->PixelFormat = Pixelformat;
01678
01679   /* Set LTDC parameters */
01680   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01681
01682   /* Change the LTDC state*/
01683   hltdc->State = HAL_LTDC_STATE_READY;
01684
01685   /* Process unlocked */
01686   __HAL_UNLOCK(hltdc);
01687
01688   return HAL_OK;
01689 }
01690
01691 /**
01692   * @brief  Reconfigure the layer alpha value without reloading.
01693   *         Variant of the function HAL_LTDC_SetAlpha without immediate reload.
01694   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01695   *                   the configuration information for the LTDC.
01696   * @param  Alpha     new alpha value.
01697   * @param  LayerIdx  LTDC Layer index.
01698   *                   This parameter can be one of the following values:
01699   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01700   * @retval  HAL status
01701   */
01702 HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
01703 {
01704   LTDC_LayerCfgTypeDef *pLayerCfg;
01705
01706   /* Check the parameters */
01707   assert_param(IS_LTDC_ALPHA(Alpha));
01708   assert_param(IS_LTDC_LAYER(LayerIdx));
01709
01710   /* Process locked */
01711   __HAL_LOCK(hltdc);
01712
01713   /* Change LTDC peripheral state */
01714   hltdc->State = HAL_LTDC_STATE_BUSY;
01715
01716   /* Get layer configuration from handle structure */
01717   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01718
01719   /* Reconfigure the Alpha value */
01720   pLayerCfg->Alpha = Alpha;
01721
01722   /* Set LTDC parameters */
01723   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01724
01725   /* Change the LTDC state*/
01726   hltdc->State = HAL_LTDC_STATE_READY;
01727
01728   /* Process unlocked */
01729   __HAL_UNLOCK(hltdc);
01730
01731   return HAL_OK;
01732 }
01733
01734 /**
01735   * @brief  Reconfigure the frame buffer Address without reloading.
01736   *         Variant of the function HAL_LTDC_SetAddress without immediate reload.
01737   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01738   *                   the configuration information for the LTDC.
01739   * @param  Address   new address value.
01740   * @param  LayerIdx  LTDC Layer index.
01741   *                   This parameter can be one of the following values:
01742   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01743   * @retval  HAL status
01744   */
01745 HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
01746 {
01747   LTDC_LayerCfgTypeDef *pLayerCfg;
01748
01749   /* Check the parameters */
01750   assert_param(IS_LTDC_LAYER(LayerIdx));
01751
01752   /* Process locked */
01753   __HAL_LOCK(hltdc);
01754
01755   /* Change LTDC peripheral state */
01756   hltdc->State = HAL_LTDC_STATE_BUSY;
01757
01758   /* Get layer configuration from handle structure */
01759   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01760
01761   /* Reconfigure the Address */
01762   pLayerCfg->FBStartAdress = Address;
01763
01764   /* Set LTDC parameters */
01765   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01766
01767   /* Change the LTDC state*/
01768   hltdc->State = HAL_LTDC_STATE_READY;
01769
01770   /* Process unlocked */
01771   __HAL_UNLOCK(hltdc);
01772
01773   return HAL_OK;
01774 }
01775
01776 /**
01777   * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
01778   *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
01779   *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
01780   *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
01781   * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
01782   *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
01783   *         Variant of the function HAL_LTDC_SetPitch without immediate reload.
01784   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
01785   *                            the configuration information for the LTDC.
01786   * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
01787   * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
01788   * @retval HAL status
01789   */
01790 HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
01791 {
01792   uint32_t tmp;
01793   uint32_t pitchUpdate;
01794   uint32_t pixelFormat;
01795
01796   /* Check the parameters */
01797   assert_param(IS_LTDC_LAYER(LayerIdx));
01798
01799   /* Process locked */
01800   __HAL_LOCK(hltdc);
01801
01802   /* Change LTDC peripheral state */
01803   hltdc->State = HAL_LTDC_STATE_BUSY;
01804
01805   /* get LayerIdx used pixel format */
01806   pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
01807
01808   if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01809   {
01810     tmp = 4U;
01811   }
01812   else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01813   {
01814     tmp = 3U;
01815   }
01816   else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01817            (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01818            (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01819            (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
01820   {
01821     tmp = 2U;
01822   }
01823   else
01824   {
01825     tmp = 1U;
01826   }
01827
01828   pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
01829
01830   /* Clear previously set standard pitch */
01831   LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
01832
01833   /* Set new line pitch value */
01834   LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
01835
01836   /* Change the LTDC state*/
01837   hltdc->State = HAL_LTDC_STATE_READY;
01838
01839   /* Process unlocked */
01840   __HAL_UNLOCK(hltdc);
01841
01842   return HAL_OK;
01843 }
01844
01845
01846 /**
01847   * @brief  Configure the color keying without reloading.
01848   *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
01849   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01850   *                   the configuration information for the LTDC.
01851   * @param  RGBValue the color key value
01852   * @param  LayerIdx  LTDC Layer index.
01853   *                   This parameter can be one of the following values:
01854   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01855   * @retval HAL status
01856   */
01857 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
01858 {
01859   /* Check the parameters */
01860   assert_param(IS_LTDC_LAYER(LayerIdx));
01861
01862   /* Process locked */
01863   __HAL_LOCK(hltdc);
01864
01865   /* Change LTDC peripheral state */
01866   hltdc->State = HAL_LTDC_STATE_BUSY;
01867
01868   /* Configure the default color values */
01869   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
01870   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
01871
01872   /* Change the LTDC state*/
01873   hltdc->State = HAL_LTDC_STATE_READY;
01874
01875   /* Process unlocked */
01876   __HAL_UNLOCK(hltdc);
01877
01878   return HAL_OK;
01879 }
01880
01881 /**
01882   * @brief  Enable the color keying without reloading.
01883   *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
01884   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01885   *                   the configuration information for the LTDC.
01886   * @param  LayerIdx  LTDC Layer index.
01887   *                   This parameter can be one of the following values:
01888   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01889   * @retval  HAL status
01890   */
01891 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01892 {
01893   /* Check the parameters */
01894   assert_param(IS_LTDC_LAYER(LayerIdx));
01895
01896   /* Process locked */
01897   __HAL_LOCK(hltdc);
01898
01899   /* Change LTDC peripheral state */
01900   hltdc->State = HAL_LTDC_STATE_BUSY;
01901
01902   /* Enable LTDC color keying by setting COLKEN bit */
01903   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
01904
01905   /* Change the LTDC state*/
01906   hltdc->State = HAL_LTDC_STATE_READY;
01907
01908   /* Process unlocked */
01909   __HAL_UNLOCK(hltdc);
01910
01911   return HAL_OK;
01912 }
01913
01914 /**
01915   * @brief  Disable the color keying without reloading.
01916   *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
01917   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01918   *                   the configuration information for the LTDC.
01919   * @param  LayerIdx  LTDC Layer index.
01920   *                   This parameter can be one of the following values:
01921   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01922   * @retval  HAL status
01923   */
01924 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01925 {
01926   /* Check the parameters */
01927   assert_param(IS_LTDC_LAYER(LayerIdx));
01928
01929   /* Process locked */
01930   __HAL_LOCK(hltdc);
01931
01932   /* Change LTDC peripheral state */
01933   hltdc->State = HAL_LTDC_STATE_BUSY;
01934
01935   /* Disable LTDC color keying by setting COLKEN bit */
01936   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
01937
01938   /* Change the LTDC state*/
01939   hltdc->State = HAL_LTDC_STATE_READY;
01940
01941   /* Process unlocked */
01942   __HAL_UNLOCK(hltdc);
01943
01944   return HAL_OK;
01945 }
01946
01947 /**
01948   * @brief  Enable the color lookup table without reloading.
01949   *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
01950   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01951   *                   the configuration information for the LTDC.
01952   * @param  LayerIdx  LTDC Layer index.
01953   *                   This parameter can be one of the following values:
01954   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01955   * @retval  HAL status
01956   */
01957 HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01958 {
01959   /* Check the parameters */
01960   assert_param(IS_LTDC_LAYER(LayerIdx));
01961
01962   /* Process locked */
01963   __HAL_LOCK(hltdc);
01964
01965   /* Change LTDC peripheral state */
01966   hltdc->State = HAL_LTDC_STATE_BUSY;
01967
01968   /* Disable LTDC color lookup table by setting CLUTEN bit */
01969   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
01970
01971   /* Change the LTDC state*/
01972   hltdc->State = HAL_LTDC_STATE_READY;
01973
01974   /* Process unlocked */
01975   __HAL_UNLOCK(hltdc);
01976
01977   return HAL_OK;
01978 }
01979
01980 /**
01981   * @brief  Disable the color lookup table without reloading.
01982   *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
01983   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01984   *                   the configuration information for the LTDC.
01985   * @param  LayerIdx  LTDC Layer index.
01986   *                   This parameter can be one of the following values:
01987   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01988   * @retval  HAL status
01989   */
01990 HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01991 {
01992   /* Check the parameters */
01993   assert_param(IS_LTDC_LAYER(LayerIdx));
01994
01995   /* Process locked */
01996   __HAL_LOCK(hltdc);
01997
01998   /* Change LTDC peripheral state */
01999   hltdc->State = HAL_LTDC_STATE_BUSY;
02000
02001   /* Disable LTDC color lookup table by setting CLUTEN bit */
02002   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
02003
02004   /* Change the LTDC state*/
02005   hltdc->State = HAL_LTDC_STATE_READY;
02006
02007   /* Process unlocked */
02008   __HAL_UNLOCK(hltdc);
02009
02010   return HAL_OK;
02011 }
02012
02013 /**
02014   * @}
02015   */
02016
02017 /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
02018   *  @brief    Peripheral State and Errors functions
02019   *
02020 @verbatim
02021  ===============================================================================
02022                   ##### Peripheral State and Errors functions #####
02023  ===============================================================================
02024     [..]
02025     This subsection provides functions allowing to
02026       (+) Check the LTDC handle state.
02027       (+) Get the LTDC handle error code.
02028
02029 @endverbatim
02030   * @{
02031   */
02032
02033 /**
02034   * @brief  Return the LTDC handle state.
02035   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
02036   *                the configuration information for the LTDC.
02037   * @retval HAL state
02038   */
02039 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
02040 {
02041   return hltdc->State;
02042 }
02043
02044 /**
02045   * @brief  Return the LTDC handle error code.
02046   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
02047   *               the configuration information for the LTDC.
02048   * @retval LTDC Error Code
02049   */
02050 uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
02051 {
02052   return hltdc->ErrorCode;
02053 }
02054
02055 /**
02056   * @}
02057   */
02058
02059 /**
02060   * @}
02061   */
02062
02063 /** @defgroup LTDC_Private_Functions LTDC Private Functions
02064   * @{
02065   */
02066
02067 /**
02068   * @brief  Configure the LTDC peripheral
02069   * @param  hltdc     Pointer to a LTDC_HandleTypeDef structure that contains
02070   *                   the configuration information for the LTDC.
02071   * @param  pLayerCfg Pointer LTDC Layer Configuration structure
02072   * @param  LayerIdx  LTDC Layer index.
02073   *                   This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
02074   * @retval None
02075   */
02076 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
02077 {
02078   uint32_t tmp;
02079   uint32_t tmp1;
02080   uint32_t tmp2;
02081
02082   /* Configure the horizontal start and stop position */
02083   tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
02084   LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
02085   LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
02086
02087   /* Configure the vertical start and stop position */
02088   tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
02089   LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
02090   LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
02091
02092   /* Specifies the pixel format */
02093   LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
02094   LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
02095
02096   /* Configure the default color values */
02097   tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
02098   tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
02099   tmp2 = (pLayerCfg->Alpha0 << 24U);
02100   LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
02101   LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
02102
02103   /* Specifies the constant alpha value */
02104   LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
02105   LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
02106
02107   /* Specifies the blending factors */
02108   LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
02109   LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
02110
02111   /* Configure the color frame buffer start address */
02112   LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
02113   LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
02114
02115   if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
02116   {
02117     tmp = 4U;
02118   }
02119   else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
02120   {
02121     tmp = 3U;
02122   }
02123   else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
02124            (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
02125            (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
02126            (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
02127   {
02128     tmp = 2U;
02129   }
02130   else
02131   {
02132     tmp = 1U;
02133   }
02134
02135   /* Configure the color frame buffer pitch in byte */
02136   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
02137   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 7U));
02138   /* Configure the frame buffer line number */
02139   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
02140   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
02141
02142   /* Enable LTDC_Layer by setting LEN bit */
02143   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
02144 }
02145
02146 /**
02147   * @}
02148   */
02149
02150
02151 /**
02152   * @}
02153   */
02154
02155 #endif /* LTDC */
02156
02157 #endif /* HAL_LTDC_MODULE_ENABLED */
02158
02159 /**
02160   * @}
02161   */
02162
02163 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc.h Source File

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stm32h7xx_hal_ltdc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LTDC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_LTDC_H
00022 #define STM32H7xx_HAL_LTDC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (LTDC)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @defgroup LTDC LTDC
00038   * @brief LTDC HAL module driver
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup LTDC_Exported_Types LTDC Exported Types
00044   * @{
00045   */
00046 #define MAX_LAYER  2U
00047
00048 /**
00049   * @brief  LTDC color structure definition
00050   */
00051 typedef struct
00052 {
00053   uint8_t Blue;                    /*!< Configures the blue value.
00054                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00055
00056   uint8_t Green;                   /*!< Configures the green value.
00057                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00058
00059   uint8_t Red;                     /*!< Configures the red value.
00060                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00061
00062   uint8_t Reserved;                /*!< Reserved 0xFF */
00063 } LTDC_ColorTypeDef;
00064
00065 /**
00066   * @brief  LTDC Init structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
00071                                                       This parameter can be one value of @ref LTDC_HS_POLARITY */
00072
00073   uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
00074                                                       This parameter can be one value of @ref LTDC_VS_POLARITY */
00075
00076   uint32_t            DEPolarity;                /*!< configures the data enable polarity.
00077                                                       This parameter can be one of value of @ref LTDC_DE_POLARITY */
00078
00079   uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
00080                                                       This parameter can be one of value of @ref LTDC_PC_POLARITY */
00081
00082   uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
00083                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00084
00085   uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
00086                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00087
00088   uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
00089                                                       This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
00090
00091   uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
00092                                                       This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
00093
00094   uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
00095                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
00096
00097   uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
00098                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
00099
00100   uint32_t            TotalWidth;                /*!< configures the total width.
00101                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
00102
00103   uint32_t            TotalHeigh;                /*!< configures the total height.
00104                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
00105
00106   LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
00107 } LTDC_InitTypeDef;
00108
00109 /**
00110   * @brief  LTDC Layer structure definition
00111   */
00112 typedef struct
00113 {
00114   uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
00115                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00116
00117   uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
00118                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00119
00120   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
00121                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00122
00123   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
00124                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
00125
00126   uint32_t PixelFormat;                /*!< Specifies the pixel format.
00127                                             This parameter can be one of value of @ref LTDC_Pixelformat */
00128
00129   uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
00130                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00131
00132   uint32_t Alpha0;                     /*!< Configures the default alpha value.
00133                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00134
00135   uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
00136                                             This parameter can be one of value of @ref LTDC_BlendingFactor1 */
00137
00138   uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
00139                                             This parameter can be one of value of @ref LTDC_BlendingFactor2 */
00140
00141   uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
00142
00143   uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
00144                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
00145
00146   uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
00147                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00148
00149   LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
00150 } LTDC_LayerCfgTypeDef;
00151
00152 /**
00153   * @brief  HAL LTDC State structures definition
00154   */
00155 typedef enum
00156 {
00157   HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */
00158   HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */
00159   HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */
00160   HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */
00161   HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */
00162 } HAL_LTDC_StateTypeDef;
00163
00164 /**
00165   * @brief  LTDC handle Structure definition
00166   */
00167 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00168 typedef struct __LTDC_HandleTypeDef
00169 #else
00170 typedef struct
00171 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00172 {
00173   LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
00174
00175   LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
00176
00177   LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
00178
00179   HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
00180
00181   __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
00182
00183   __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
00184
00185 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00186   void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Line Event Callback    */
00187   void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc);   /*!< LTDC Reload Event Callback  */
00188   void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc);         /*!< LTDC Error Callback         */
00189
00190   void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc);       /*!< LTDC Msp Init callback      */
00191   void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Msp DeInit callback    */
00192
00193 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00194
00195
00196 } LTDC_HandleTypeDef;
00197
00198 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00199 /**
00200   * @brief  HAL LTDC Callback ID enumeration definition
00201   */
00202 typedef enum
00203 {
00204   HAL_LTDC_MSPINIT_CB_ID            = 0x00U,    /*!< LTDC MspInit callback ID       */
00205   HAL_LTDC_MSPDEINIT_CB_ID          = 0x01U,    /*!< LTDC MspDeInit callback ID     */
00206
00207   HAL_LTDC_LINE_EVENT_CB_ID         = 0x02U,    /*!< LTDC Line Event Callback ID    */
00208   HAL_LTDC_RELOAD_EVENT_CB_ID       = 0x03U,    /*!< LTDC Reload Callback ID        */
00209   HAL_LTDC_ERROR_CB_ID              = 0x04U     /*!< LTDC Error Callback ID         */
00210
00211 } HAL_LTDC_CallbackIDTypeDef;
00212
00213 /**
00214   * @brief  HAL LTDC Callback pointer definition
00215   */
00216 typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer to an LTDC callback function */
00217
00218 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /* Exported constants --------------------------------------------------------*/
00225 /** @defgroup LTDC_Exported_Constants LTDC Exported Constants
00226   * @{
00227   */
00228
00229 /** @defgroup LTDC_Error_Code LTDC Error Code
00230   * @{
00231   */
00232 #define HAL_LTDC_ERROR_NONE               0x00000000U   /*!< LTDC No error             */
00233 #define HAL_LTDC_ERROR_TE                 0x00000001U   /*!< LTDC Transfer error       */
00234 #define HAL_LTDC_ERROR_FU                 0x00000002U   /*!< LTDC FIFO Underrun        */
00235 #define HAL_LTDC_ERROR_TIMEOUT            0x00000020U   /*!< LTDC Timeout error        */
00236 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00237 #define  HAL_LTDC_ERROR_INVALID_CALLBACK  0x00000040U   /*!< LTDC Invalid Callback error  */
00238 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup LTDC_Layer LTDC Layer
00244   * @{
00245   */
00246 #define LTDC_LAYER_1                      0x00000000U   /*!< LTDC Layer 1 */
00247 #define LTDC_LAYER_2                      0x00000001U   /*!< LTDC Layer 2 */
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
00253   * @{
00254   */
00255 #define LTDC_HSPOLARITY_AL                0x00000000U   /*!< Horizontal Synchronization is active low. */
00256 #define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL            /*!< Horizontal Synchronization is active high. */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
00262   * @{
00263   */
00264 #define LTDC_VSPOLARITY_AL                0x00000000U   /*!< Vertical Synchronization is active low. */
00265 #define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL            /*!< Vertical Synchronization is active high. */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
00271   * @{
00272   */
00273 #define LTDC_DEPOLARITY_AL                0x00000000U   /*!< Data Enable, is active low. */
00274 #define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL            /*!< Data Enable, is active high. */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
00280   * @{
00281   */
00282 #define LTDC_PCPOLARITY_IPC               0x00000000U   /*!< input pixel clock. */
00283 #define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL            /*!< inverted input pixel clock. */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup LTDC_SYNC LTDC SYNC
00289   * @{
00290   */
00291 #define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16U)    /*!< Horizontal synchronization width. */
00292 #define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH             /*!< Vertical synchronization height. */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
00298   * @{
00299   */
00300 #define LTDC_COLOR                        0x000000FFU   /*!< Color mask */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
00306   * @{
00307   */
00308 #define LTDC_BLENDING_FACTOR1_CA          0x00000400U   /*!< Blending factor : Cte Alpha */
00309 #define LTDC_BLENDING_FACTOR1_PAxCA       0x00000600U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
00315   * @{
00316   */
00317 #define LTDC_BLENDING_FACTOR2_CA          0x00000005U   /*!< Blending factor : Cte Alpha */
00318 #define LTDC_BLENDING_FACTOR2_PAxCA       0x00000007U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup LTDC_Pixelformat LTDC Pixel format
00324   * @{
00325   */
00326 #define LTDC_PIXEL_FORMAT_ARGB8888        0x00000000U   /*!< ARGB8888 LTDC pixel format */
00327 #define LTDC_PIXEL_FORMAT_RGB888          0x00000001U   /*!< RGB888 LTDC pixel format   */
00328 #define LTDC_PIXEL_FORMAT_RGB565          0x00000002U   /*!< RGB565 LTDC pixel format   */
00329 #define LTDC_PIXEL_FORMAT_ARGB1555        0x00000003U   /*!< ARGB1555 LTDC pixel format */
00330 #define LTDC_PIXEL_FORMAT_ARGB4444        0x00000004U   /*!< ARGB4444 LTDC pixel format */
00331 #define LTDC_PIXEL_FORMAT_L8              0x00000005U   /*!< L8 LTDC pixel format       */
00332 #define LTDC_PIXEL_FORMAT_AL44            0x00000006U   /*!< AL44 LTDC pixel format     */
00333 #define LTDC_PIXEL_FORMAT_AL88            0x00000007U   /*!< AL88 LTDC pixel format     */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup LTDC_Alpha LTDC Alpha
00339   * @{
00340   */
00341 #define LTDC_ALPHA                        LTDC_LxCACR_CONSTA        /*!< LTDC Constant Alpha mask */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup LTDC_LAYER_Config LTDC LAYER Config
00347   * @{
00348   */
00349 #define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position  */
00350 #define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS          /*!< LTDC Layer start position */
00351
00352 #define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL            /*!< LTDC Layer Line length    */
00353 #define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR         /*!< LTDC Layer Line number    */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup LTDC_Interrupts LTDC Interrupts
00359   * @{
00360   */
00361 #define LTDC_IT_LI                        LTDC_IER_LIE              /*!< LTDC Line Interrupt            */
00362 #define LTDC_IT_FU                        LTDC_IER_FUIE             /*!< LTDC FIFO Underrun Interrupt   */
00363 #define LTDC_IT_TE                        LTDC_IER_TERRIE           /*!< LTDC Transfer Error Interrupt  */
00364 #define LTDC_IT_RR                        LTDC_IER_RRIE             /*!< LTDC Register Reload Interrupt */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup LTDC_Flags LTDC Flags
00370   * @{
00371   */
00372 #define LTDC_FLAG_LI                      LTDC_ISR_LIF              /*!< LTDC Line Interrupt Flag            */
00373 #define LTDC_FLAG_FU                      LTDC_ISR_FUIF             /*!< LTDC FIFO Underrun interrupt Flag   */
00374 #define LTDC_FLAG_TE                      LTDC_ISR_TERRIF           /*!< LTDC Transfer Error interrupt Flag  */
00375 #define LTDC_FLAG_RR                      LTDC_ISR_RRIF             /*!< LTDC Register Reload interrupt Flag */
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup LTDC_Reload_Type LTDC Reload Type
00381   * @{
00382   */
00383 #define LTDC_RELOAD_IMMEDIATE             LTDC_SRCR_IMR             /*!< Immediate Reload */
00384 #define LTDC_RELOAD_VERTICAL_BLANKING     LTDC_SRCR_VBR             /*!< Vertical Blanking Reload */
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 /* Exported macro ------------------------------------------------------------*/
00394 /** @defgroup LTDC_Exported_Macros LTDC Exported Macros
00395   * @{
00396   */
00397
00398 /** @brief Reset LTDC handle state.
00399   * @param  __HANDLE__  LTDC handle
00400   * @retval None
00401   */
00402 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00403 #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
00404                                                       (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \
00405                                                       (__HANDLE__)->MspInitCallback = NULL;           \
00406                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
00407                                                     } while(0)
00408 #else
00409 #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
00410 #endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
00411
00412 /**
00413   * @brief  Enable the LTDC.
00414   * @param  __HANDLE__  LTDC handle
00415   * @retval None.
00416   */
00417 #define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
00418
00419 /**
00420   * @brief  Disable the LTDC.
00421   * @param  __HANDLE__  LTDC handle
00422   * @retval None.
00423   */
00424 #define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
00425
00426 /**
00427   * @brief  Enable the LTDC Layer.
00428   * @param  __HANDLE__  LTDC handle
00429   * @param  __LAYER__   Specify the layer to be enabled.
00430   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
00431   * @retval None.
00432   */
00433 #define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
00434
00435 /**
00436   * @brief  Disable the LTDC Layer.
00437   * @param  __HANDLE__  LTDC handle
00438   * @param  __LAYER__   Specify the layer to be disabled.
00439   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
00440   * @retval None.
00441   */
00442 #define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
00443
00444 /**
00445   * @brief  Reload immediately all LTDC Layers.
00446   * @param  __HANDLE__  LTDC handle
00447   * @retval None.
00448   */
00449 #define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
00450
00451 /**
00452   * @brief  Reload during vertical blanking period all LTDC Layers.
00453   * @param  __HANDLE__  LTDC handle
00454   * @retval None.
00455   */
00456 #define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
00457
00458 /* Interrupt & Flag management */
00459 /**
00460   * @brief  Get the LTDC pending flags.
00461   * @param  __HANDLE__  LTDC handle
00462   * @param  __FLAG__    Get the specified flag.
00463   *          This parameter can be any combination of the following values:
00464   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00465   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00466   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00467   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00468   * @retval The state of FLAG (SET or RESET).
00469   */
00470 #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00471
00472 /**
00473   * @brief  Clears the LTDC pending flags.
00474   * @param  __HANDLE__  LTDC handle
00475   * @param  __FLAG__    Specify the flag to clear.
00476   *          This parameter can be any combination of the following values:
00477   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00478   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00479   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00480   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00481   * @retval None
00482   */
00483 #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00484
00485 /**
00486   * @brief  Enables the specified LTDC interrupts.
00487   * @param  __HANDLE__  LTDC handle
00488   * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
00489   *          This parameter can be any combination of the following values:
00490   *            @arg LTDC_IT_LI: Line Interrupt flag
00491   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00492   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00493   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00494   * @retval None
00495   */
00496 #define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00497
00498 /**
00499   * @brief  Disables the specified LTDC interrupts.
00500   * @param  __HANDLE__  LTDC handle
00501   * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
00502   *          This parameter can be any combination of the following values:
00503   *            @arg LTDC_IT_LI: Line Interrupt flag
00504   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00505   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00506   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00507   * @retval None
00508   */
00509 #define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00510
00511 /**
00512   * @brief  Check whether the specified LTDC interrupt has occurred or not.
00513   * @param  __HANDLE__  LTDC handle
00514   * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
00515   *          This parameter can be one of the following values:
00516   *            @arg LTDC_IT_LI: Line Interrupt flag
00517   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00518   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00519   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00520   * @retval The state of INTERRUPT (SET or RESET).
00521   */
00522 #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00523 /**
00524   * @}
00525   */
00526
00527 /* Include LTDC HAL Extension module */
00528 #include "stm32h7xx_hal_ltdc_ex.h"
00529
00530 /* Exported functions --------------------------------------------------------*/
00531 /** @addtogroup LTDC_Exported_Functions
00532   * @{
00533   */
00534 /** @addtogroup LTDC_Exported_Functions_Group1
00535   * @{
00536   */
00537 /* Initialization and de-initialization functions *****************************/
00538 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
00539 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
00540 void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
00541 void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
00542 void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
00543 void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
00544 void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
00545
00546 /* Callbacks Register/UnRegister functions  ***********************************/
00547 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
00548 HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
00549 HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
00550 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
00551
00552 /**
00553   * @}
00554   */
00555
00556 /** @addtogroup LTDC_Exported_Functions_Group2
00557   * @{
00558   */
00559 /* IO operation functions *****************************************************/
00560 void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
00561 /**
00562   * @}
00563   */
00564
00565 /** @addtogroup LTDC_Exported_Functions_Group3
00566   * @{
00567   */
00568 /* Peripheral Control functions ***********************************************/
00569 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00570 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00571 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00572 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00573 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00574 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00575 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
00576 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00577 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
00578 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00579 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00580 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00581 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00582 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
00583 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
00584 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
00585 HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
00586 HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00587 HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00588 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00589 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00590 HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00591 HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00592 HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
00593 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00594 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00595 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00596 HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00597 HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00598
00599 /**
00600   * @}
00601   */
00602
00603 /** @addtogroup LTDC_Exported_Functions_Group4
00604   * @{
00605   */
00606 /* Peripheral State functions *************************************************/
00607 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
00608 uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
00609 /**
00610   * @}
00611   */
00612
00613 /**
00614   * @}
00615   */
00616
00617 /* Private types -------------------------------------------------------------*/
00618 /* Private variables ---------------------------------------------------------*/
00619 /* Private constants ---------------------------------------------------------*/
00620 /* Private macros ------------------------------------------------------------*/
00621 /** @defgroup LTDC_Private_Macros LTDC Private Macros
00622   * @{
00623   */
00624 #define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
00625 #define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)
00626 #define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
00627 #define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
00628 #define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
00629 #define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
00630 #define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)
00631 #define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)
00632 #define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)
00633 #define IS_LTDC_AVBP(__AVBP__)                         ((__AVBP__)   <= LTDC_VERTICALSYNC)
00634 #define IS_LTDC_AAW(__AAW__)                           ((__AAW__)    <= LTDC_HORIZONTALSYNC)
00635 #define IS_LTDC_AAH(__AAH__)                           ((__AAH__)    <= LTDC_VERTICALSYNC)
00636 #define IS_LTDC_TOTALW(__TOTALW__)                     ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
00637 #define IS_LTDC_TOTALH(__TOTALH__)                     ((__TOTALH__) <= LTDC_VERTICALSYNC)
00638 #define IS_LTDC_BLUEVALUE(__BBLUE__)                   ((__BBLUE__)  <= LTDC_COLOR)
00639 #define IS_LTDC_GREENVALUE(__BGREEN__)                 ((__BGREEN__) <= LTDC_COLOR)
00640 #define IS_LTDC_REDVALUE(__BRED__)                     ((__BRED__)   <= LTDC_COLOR)
00641 #define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
00642                                                         ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
00643 #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
00644                                                         ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
00645 #define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
00646                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
00647                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
00648                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
00649 #define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)
00650 #define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)
00651 #define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
00652 #define IS_LTDC_VCONFIGST(__VCONFIGST__)               ((__VCONFIGST__) <= LTDC_STARTPOSITION)
00653 #define IS_LTDC_VCONFIGSP(__VCONFIGSP__)               ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
00654 #define IS_LTDC_CFBP(__CFBP__)                         ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
00655 #define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
00656 #define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
00657 #define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)
00658 #define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
00659 /**
00660   * @}
00661   */
00662
00663 /* Private functions ---------------------------------------------------------*/
00664 /** @defgroup LTDC_Private_Functions LTDC Private Functions
00665   * @{
00666   */
00667
00668 /**
00669   * @}
00670   */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /**
00677   * @}
00678   */
00679
00680 #endif /* LTDC */
00681
00682 #ifdef __cplusplus
00683 }
00684 #endif
00685
00686 #endif /* STM32H7xx_HAL_LTDC_H */
00687
00688 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc_ex.c Source File

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stm32h7xx_hal_ltdc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   LTDC Extension HAL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32h7xx_hal.h"
00022
00023 /** @addtogroup STM32H7xx_HAL_Driver
00024   * @{
00025   */
00026
00027 #if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
00028
00029 #if defined (LTDC) && defined (DSI)
00030
00031 /** @defgroup LTDCEx LTDCEx
00032   * @brief LTDC HAL module driver
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042
00043 /** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
00044   * @{
00045   */
00046
00047 /** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
00048   *  @brief   Initialization and Configuration functions
00049   *
00050 @verbatim
00051  ===============================================================================
00052                 ##### Initialization and Configuration functions #####
00053  ===============================================================================
00054     [..]  This section provides functions allowing to:
00055       (+) Initialize and configure the LTDC
00056
00057 @endverbatim
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  Retrieve common parameters from DSI Video mode configuration structure
00063   * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
00064   *                 the configuration information for the LTDC.
00065   * @param  VidCfg  pointer to a DSI_VidCfgTypeDef structure that contains
00066   *                 the DSI video mode configuration parameters
00067   * @note   The implementation of this function is taking into account the LTDC
00068   *         polarities inversion as described in the current LTDC specification
00069   * @retval HAL status
00070   */
00071 HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
00072 {
00073   /* Retrieve signal polarities from DSI */
00074
00075   /* The following polarity is inverted:
00076                      LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
00077
00078   /* Note 1 : Code in line w/ Current LTDC specification */
00079   hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
00080   hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
00081   hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
00082
00083   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
00084   /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
00085      hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
00086      hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
00087
00088   /* Retrieve vertical timing parameters from DSI */
00089   hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1U;
00090   hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
00091   hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
00092   hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
00093
00094   return HAL_OK;
00095 }
00096
00097 /**
00098   * @brief  Retrieve common parameters from DSI Adapted command mode configuration structure
00099   * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
00100   *                 the configuration information for the LTDC.
00101   * @param  CmdCfg  pointer to a DSI_CmdCfgTypeDef structure that contains
00102   *                 the DSI command mode configuration parameters
00103   * @note   The implementation of this function is taking into account the LTDC
00104   *         polarities inversion as described in the current LTDC specification
00105   * @retval HAL status
00106   */
00107 HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
00108 {
00109   /* Retrieve signal polarities from DSI */
00110
00111   /* The following polarities are inverted:
00112                      LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
00113                      LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
00114                      LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
00115
00116   /* Note 1 : Code in line w/ Current LTDC specification */
00117   hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
00118   hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
00119   hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
00120
00121   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
00122   /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
00123      hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
00124      hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
00125
00126   return HAL_OK;
00127 }
00128
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141 #endif /* LTDC && DSI */
00142
00143 #endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ltdc_ex.h Source File

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stm32h7xx_hal_ltdc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LTDC HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_LTDC_EX_H
00022 #define STM32H7xx_HAL_LTDC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (LTDC) && defined (DSI)
00032
00033 #include "stm32h7xx_hal_dsi.h"
00034
00035 /** @addtogroup STM32H7xx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @addtogroup LTDCEx
00040   * @{
00041   */
00042
00043 /* Exported types ------------------------------------------------------------*/
00044 /* Exported constants --------------------------------------------------------*/
00045 /* Exported macro ------------------------------------------------------------*/
00046 /* Exported functions --------------------------------------------------------*/
00047 /** @addtogroup LTDCEx_Exported_Functions
00048   * @{
00049   */
00050
00051 /** @addtogroup LTDCEx_Exported_Functions_Group1
00052   * @{
00053   */
00054 HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
00055 HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private types -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private constants ---------------------------------------------------------*/
00067 /* Private macros ------------------------------------------------------------*/
00068 /* Private functions ---------------------------------------------------------*/
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 #endif /* LTDC && DSI */
00079
00080 #ifdef __cplusplus
00081 }
00082 #endif
00083
00084 #endif /* STM32H7xx_HAL_LTDC_EX_H */
00085
00086 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdios.c Source File

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stm32h7xx_hal_mdios.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdios.c
00004   * @author  MCD Application Team
00005   * @brief   MDIOS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the MDIOS Peripheral.
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *
00012   *
00013   @verbatim
00014  ===============================================================================
00015                         ##### How to use this driver #####
00016  ===============================================================================
00017     [..]
00018     The MDIOS HAL driver can be used as follow:
00019
00020     (#) Declare a MDIOS_HandleTypeDef handle structure.
00021
00022     (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
00023         (##) Enable the MDIOS interface clock.
00024         (##) MDIOS pins configuration:
00025             (+++) Enable clocks for the MDIOS GPIOs.
00026             (+++) Configure the MDIOS pins as alternate function.
00027         (##) NVIC configuration if you need to use interrupt process:
00028             (+++) Configure the MDIOS interrupt priority.
00029             (+++) Enable the NVIC MDIOS IRQ handle.
00030
00031     (#) Program the Port Address and the Preamble Check in the Init structure.
00032
00033     (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
00034
00035     (#) Perform direct slave read/write operations using the following APIs:
00036         (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
00037         (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
00038
00039     (#) Get the Master read/write operations flags using the following APIs:
00040         (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
00041         (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
00042
00043     (#) Clear the read/write flags using the following APIs:
00044         (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
00045         (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
00046
00047     (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
00048         the MDIOS will generate an interrupt in the following cases:
00049         (##) a DINn register written by the Master
00050         (##) a DOUTn register read by the Master
00051         (##) an error occur
00052
00053         (@) A callback is executed for each genereted interrupt, so the driver provide the following
00054             HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
00055         (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
00056             and execute the previous callbacks
00057
00058     (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
00059         (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
00060             (GPIO, Clocks, NVIC configuration ...)
00061
00062   *** Callback registration ***
00063   =============================================
00064
00065   The compilation define  USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1
00066   allows the user to configure dynamically the driver callbacks.
00067   Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback.
00068
00069   Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks:
00070     (+) WriteCpltCallback  : Write Complete Callback.
00071     (+) ReadCpltCallback   : Read Complete Callback.
00072     (+) ErrorCallback      : Error Callback.
00073     (+) WakeUpCallback     : Wake UP Callback
00074     (+) MspInitCallback    : MspInit Callback.
00075     (+) MspDeInitCallback  : MspDeInit Callback.
00076
00077   This function takes as parameters the HAL peripheral handle, the Callback ID
00078   and a pointer to the user callback function.
00079
00080   Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default
00081   weak function.
00082   @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle,
00083   and the Callback ID.
00084   This function allows to reset following callbacks:
00085     (+) WriteCpltCallback  : Write Complete Callback.
00086     (+) ReadCpltCallback   : Read Complete Callback.
00087     (+) ErrorCallback      : Error Callback.
00088     (+) WakeUpCallback     : Wake UP Callback
00089     (+) MspInitCallback    : MspInit Callback.
00090     (+) MspDeInitCallback  : MspDeInit Callback.
00091
00092   By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET
00093   all callbacks are set to the corresponding weak functions:
00094   examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback().
00095   Exception done for MspInit and MspDeInit functions that are
00096   reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when
00097   these callbacks are null (not registered beforehand).
00098   if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit
00099   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00100
00101   Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only.
00102   Exception done MspInit/MspDeInit that can be registered/unregistered
00103   in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state,
00104   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00105   In that case first register the MspInit/MspDeInit user callbacks
00106   using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit
00107   or HAL_MDIOS_Init function.
00108
00109   When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or
00110   not defined, the callback registration feature is not available and all callbacks
00111   are set to the corresponding weak functions.
00112
00113
00114   @endverbatim
00115   ******************************************************************************
00116   * @attention
00117   *
00118   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00119   * All rights reserved.</center></h2>
00120   *
00121   * This software component is licensed by ST under BSD 3-Clause license,
00122   * the "License"; You may not use this file except in compliance with the
00123   * License. You may obtain a copy of the License at:
00124   *                        opensource.org/licenses/BSD-3-Clause
00125   *
00126   ******************************************************************************
00127   */
00128
00129 /* Includes ------------------------------------------------------------------*/
00130 #include "stm32h7xx_hal.h"
00131
00132 /** @addtogroup STM32H7xx_HAL_Driver
00133   * @{
00134   */
00135 #if defined (MDIOS)
00136 /** @defgroup MDIOS  MDIOS
00137   * @brief HAL MDIOS module driver
00138   * @{
00139   */
00140 #ifdef HAL_MDIOS_MODULE_ENABLED
00141
00142
00143
00144 /* Private typedef -----------------------------------------------------------*/
00145 /* Private define ------------------------------------------------------------*/
00146 #define MDIOS_PORT_ADDRESS_SHIFT        ((uint32_t)8)
00147 #define  MDIOS_ALL_REG_FLAG             ((uint32_t)0xFFFFFFFFU)
00148 #define  MDIOS_ALL_ERRORS_FLAG          ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
00149
00150 #define MDIOS_DIN_BASE_ADDR             (MDIOS_BASE + 0x100U)
00151 #define MDIOS_DOUT_BASE_ADDR            (MDIOS_BASE + 0x180U)
00152
00153 /* Private macro -------------------------------------------------------------*/
00154 /* Private variables ---------------------------------------------------------*/
00155 /* Private function prototypes -----------------------------------------------*/
00156 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00157 static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios);
00158 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00159 /* Private functions ---------------------------------------------------------*/
00160 /* Exported functions --------------------------------------------------------*/
00161 /** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
00162   * @{
00163   */
00164
00165 /** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
00166   *  @brief    Initialization and Configuration functions
00167   *
00168 @verbatim
00169 ===============================================================================
00170             ##### Initialization and Configuration functions #####
00171  ===============================================================================
00172     [..]
00173     This subsection provides a set of functions allowing to initialize the MDIOS
00174       (+) The following parameters can be configured:
00175         (++) Port Address
00176         (++) Preamble Check
00177
00178 @endverbatim
00179   * @{
00180   */
00181
00182 /**
00183   * @brief  Initializes the MDIOS according to the specified parameters in
00184   *         the MDIOS_InitTypeDef and creates the associated handle .
00185   * @param  hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
00186   *         the configuration information for MDIOS module
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
00190 {
00191   uint32_t tmpcr;
00192
00193   /* Check the MDIOS handle allocation */
00194   if(hmdios == NULL)
00195   {
00196     return HAL_ERROR;
00197   }
00198
00199   /* Check the parameters */
00200   assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
00201   assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
00202   assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
00203
00204 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00205
00206   if(hmdios->State == HAL_MDIOS_STATE_RESET)
00207   {
00208     MDIOS_InitCallbacksToDefault(hmdios);
00209
00210     if(hmdios->MspInitCallback == NULL)
00211     {
00212       hmdios->MspInitCallback = HAL_MDIOS_MspInit;
00213     }
00214
00215     /* Init the low level hardware */
00216     hmdios->MspInitCallback(hmdios);
00217   }
00218
00219 #else
00220
00221   if(hmdios->State == HAL_MDIOS_STATE_RESET)
00222   {
00223     /* Init the low level hardware */
00224     HAL_MDIOS_MspInit(hmdios);
00225   }
00226
00227 #endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
00228
00229   /* Change the MDIOS state */
00230   hmdios->State = HAL_MDIOS_STATE_BUSY;
00231
00232   /* Get the MDIOS CR value */
00233   tmpcr = hmdios->Instance->CR;
00234
00235   /* Clear PORT_ADDRESS, DPC and EN bits */
00236   tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
00237
00238   /* Set MDIOS control parametrs and enable the peripheral */
00239   tmpcr |=  (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT)    |\
00240                         (hmdios->Init.PreambleCheck) | \
00241                         (MDIOS_CR_EN));
00242
00243   /* Write the MDIOS CR */
00244   hmdios->Instance->CR = tmpcr;
00245
00246   hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
00247
00248   /* Change the MDIOS state */
00249   hmdios->State = HAL_MDIOS_STATE_READY;
00250
00251   /* Release Lock */
00252   __HAL_UNLOCK(hmdios);
00253
00254   /* Return function status */
00255   return HAL_OK;
00256
00257 }
00258
00259 /**
00260   * @brief  DeInitializes the MDIOS peripheral.
00261   * @param  hmdios: MDIOS handle
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
00265 {
00266   /* Check the MDIOS handle allocation */
00267   if(hmdios == NULL)
00268   {
00269     return HAL_ERROR;
00270   }
00271
00272   /* Check the parameters */
00273   assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
00274
00275   /* Change the MDIOS state */
00276   hmdios->State = HAL_MDIOS_STATE_BUSY;
00277
00278   /* Disable the Peripheral */
00279   __HAL_MDIOS_DISABLE(hmdios);
00280
00281 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00282
00283   if(hmdios->MspDeInitCallback == NULL)
00284   {
00285     hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
00286   }
00287   /* DeInit the low level hardware */
00288   hmdios->MspDeInitCallback(hmdios);
00289 #else
00290
00291   /* DeInit the low level hardware */
00292   HAL_MDIOS_MspDeInit(hmdios);
00293
00294 #endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
00295
00296   /* Change the MDIOS state */
00297   hmdios->State = HAL_MDIOS_STATE_RESET;
00298
00299   /* Release Lock */
00300   __HAL_UNLOCK(hmdios);
00301
00302   /* Return function status */
00303   return HAL_OK;
00304 }
00305
00306 /**
00307   * @brief  MDIOS MSP Init
00308   * @param  hmdios: mdios handle
00309   * @retval None
00310   */
00311  __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
00312 {
00313   /* Prevent unused argument(s) compilation warning */
00314   UNUSED(hmdios);
00315
00316   /* NOTE : This function should not be modified, when the callback is needed,
00317             the HAL_MDIOS_MspInit can be implemented in the user file
00318    */
00319 }
00320
00321 /**
00322   * @brief  MDIOS MSP DeInit
00323   * @param  hmdios: mdios handle
00324   * @retval None
00325   */
00326  __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
00327 {
00328   /* Prevent unused argument(s) compilation warning */
00329   UNUSED(hmdios);
00330
00331   /* NOTE : This function should not be modified, when the callback is needed,
00332             the HAL_MDIOS_MspDeInit can be implemented in the user file
00333    */
00334 }
00335
00336 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00337 /**
00338   * @brief  Register a User MDIOS Callback
00339   *         To be used instead of the weak predefined callback
00340   * @param hmdios mdios handle
00341   * @param CallbackID ID of the callback to be registered
00342   *        This parameter can be one of the following values:
00343   *          @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
00344   *          @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID  Read Complete Callback ID
00345   *          @arg @ref HAL_MDIOS_ERROR_CB_ID          Error Callback ID
00346   *          @arg @ref HAL_MDIOS_WAKEUP_CB_ID         Wake Up Callback ID
00347   *          @arg @ref HAL_MDIOS_MSPINIT_CB_ID        MspInit callback ID
00348   *          @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID      MspDeInit callback ID
00349   * @param pCallback pointer to the Callback function
00350   * @retval status
00351   */
00352 HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
00353 {
00354   HAL_StatusTypeDef status = HAL_OK;
00355
00356   if(pCallback == NULL)
00357   {
00358     /* Update the error code */
00359     hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00360
00361     return HAL_ERROR;
00362   }
00363   /* Process locked */
00364   __HAL_LOCK(hmdios);
00365
00366   if(hmdios->State == HAL_MDIOS_STATE_READY)
00367   {
00368     switch (CallbackID)
00369     {
00370     case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
00371       hmdios->WriteCpltCallback = pCallback;
00372       break;
00373
00374     case HAL_MDIOS_READ_COMPLETE_CB_ID :
00375       hmdios->ReadCpltCallback = pCallback;
00376       break;
00377
00378     case HAL_MDIOS_ERROR_CB_ID :
00379       hmdios->ErrorCallback = pCallback;
00380       break;
00381
00382     case HAL_MDIOS_WAKEUP_CB_ID :
00383       hmdios->WakeUpCallback = pCallback;
00384       break;
00385
00386     case HAL_MDIOS_MSPINIT_CB_ID :
00387       hmdios->MspInitCallback = pCallback;
00388       break;
00389
00390    case HAL_MDIOS_MSPDEINIT_CB_ID :
00391       hmdios->MspDeInitCallback = pCallback;
00392       break;
00393
00394     default :
00395       /* Update the error code */
00396       hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00397       /* Return error status */
00398       status =  HAL_ERROR;
00399       break;
00400     }
00401   }
00402   else if(hmdios->State == HAL_MDIOS_STATE_RESET)
00403   {
00404     switch (CallbackID)
00405     {
00406     case HAL_MDIOS_MSPINIT_CB_ID :
00407       hmdios->MspInitCallback = pCallback;
00408       break;
00409
00410    case HAL_MDIOS_MSPDEINIT_CB_ID :
00411       hmdios->MspDeInitCallback = pCallback;
00412       break;
00413
00414     default :
00415       /* Update the error code */
00416       hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00417      /* Return error status */
00418       status =  HAL_ERROR;
00419       break;
00420     }
00421   }
00422   else
00423   {
00424     /* Update the error code */
00425     hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00426     /* Return error status */
00427     status =  HAL_ERROR;
00428   }
00429
00430   /* Release Lock */
00431   __HAL_UNLOCK(hmdios);
00432
00433   return status;
00434 }
00435
00436 /**
00437   * @brief  Unregister an MDIOS Callback
00438   *         MDIOS callabck is redirected to the weak predefined callback
00439   * @param hmdios mdios handle
00440   * @param CallbackID ID of the callback to be unregistered
00441   *        This parameter can be one of the following values:
00442   *          @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
00443   *          @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID  Read Complete Callback ID
00444   *          @arg @ref HAL_MDIOS_ERROR_CB_ID          Error Callback ID
00445   *          @arg @ref HAL_MDIOS_WAKEUP_CB_ID         Wake Up Callback ID
00446   *          @arg @ref HAL_MDIOS_MSPINIT_CB_ID        MspInit callback ID
00447   *          @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID      MspDeInit callback ID
00448   * @retval status
00449   */
00450 HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
00451 {
00452   HAL_StatusTypeDef status = HAL_OK;
00453
00454   /* Process locked */
00455   __HAL_LOCK(hmdios);
00456
00457   if(hmdios->State == HAL_MDIOS_STATE_READY)
00458   {
00459     switch (CallbackID)
00460     {
00461     case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
00462       hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback;
00463       break;
00464
00465     case HAL_MDIOS_READ_COMPLETE_CB_ID :
00466       hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback;
00467       break;
00468
00469     case HAL_MDIOS_ERROR_CB_ID :
00470       hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback;
00471       break;
00472
00473     case HAL_MDIOS_WAKEUP_CB_ID :
00474       hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback;
00475       break;
00476
00477     case HAL_MDIOS_MSPINIT_CB_ID :
00478       hmdios->MspInitCallback = HAL_MDIOS_MspInit;
00479       break;
00480
00481    case HAL_MDIOS_MSPDEINIT_CB_ID :
00482       hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
00483       break;
00484
00485     default :
00486       /* Update the error code */
00487       hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00488      /* Return error status */
00489       status =  HAL_ERROR;
00490       break;
00491     }
00492   }
00493   else if(hmdios->State == HAL_MDIOS_STATE_RESET)
00494   {
00495     switch (CallbackID)
00496     {
00497     case HAL_MDIOS_MSPINIT_CB_ID :
00498       hmdios->MspInitCallback = HAL_MDIOS_MspInit;
00499       break;
00500
00501    case HAL_MDIOS_MSPDEINIT_CB_ID :
00502       hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
00503       break;
00504
00505     default :
00506       /* Update the error code */
00507       hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00508      /* Return error status */
00509       status =  HAL_ERROR;
00510       break;
00511     }
00512   }
00513   else
00514   {
00515     /* Update the error code */
00516     hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
00517     /* Return error status */
00518     status =  HAL_ERROR;
00519   }
00520
00521   /* Release Lock */
00522   __HAL_UNLOCK(hmdios);
00523
00524   return status;
00525 }
00526 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
00533   *  @brief MDIOS Read/Write functions
00534   *
00535 @verbatim
00536  ===============================================================================
00537                       ##### IO operation functions #####
00538  ===============================================================================
00539     This subsection provides a set of functions allowing to manage the MDIOS
00540     read and write operations.
00541
00542     (#) APIs that allow to the MDIOS to read/write from/to the
00543         values of one of the DINn/DOUTn registers:
00544         (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
00545         (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
00546
00547     (#) APIs that provide if there are some Slave registres have been
00548         read or written by the Master:
00549         (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
00550         (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
00551
00552     (#) APIs that Clear the read/write flags:
00553         (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
00554         (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
00555
00556     (#) A set of Callbacks are provided:
00557         (+) HAL_MDIOS_WriteCpltCallback()
00558         (+) HAL_MDIOS_ReadCpltCallback()
00559         (+) HAL_MDIOS_ErrorCallback()
00560
00561 @endverbatim
00562   * @{
00563   */
00564
00565 /**
00566   * @brief  Writes to an MDIOS output register
00567   * @param  hmdios: mdios handle
00568   * @param  RegNum: MDIOS output register address
00569   * @param  Data: Data to write
00570   * @retval HAL status
00571   */
00572 HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
00573 {
00574   uint32_t tmpreg;
00575
00576   /* Check the parameters */
00577   assert_param(IS_MDIOS_REGISTER(RegNum));
00578
00579   /* Process Locked */
00580   __HAL_LOCK(hmdios);
00581
00582   /* Get the addr of output register to be written by the MDIOS */
00583   tmpreg = MDIOS_DOUT_BASE_ADDR + (4U * RegNum);
00584
00585   /* Write to DOUTn register */
00586   *((uint32_t *)tmpreg) = Data;
00587
00588     /* Process Unlocked */
00589   __HAL_UNLOCK(hmdios);
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @brief  Reads an MDIOS input register
00596   * @param  hmdios: mdios handle
00597   * @param  RegNum: MDIOS input register address
00598   * @param  pData: pointer to Data
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
00602 {
00603   uint32_t tmpreg;
00604
00605   /* Check the parameters */
00606   assert_param(IS_MDIOS_REGISTER(RegNum));
00607
00608   /* Process Locked */
00609   __HAL_LOCK(hmdios);
00610
00611   /* Get the addr of input register to be read by the MDIOS */
00612   tmpreg = MDIOS_DIN_BASE_ADDR + (4U * RegNum);
00613
00614   /* Read DINn register */
00615   *pData = (uint16_t)(*((uint32_t *)tmpreg));
00616
00617   /* Process Unlocked */
00618   __HAL_UNLOCK(hmdios);
00619
00620   return HAL_OK;
00621 }
00622
00623 /**
00624   * @brief  Gets Written registers by MDIO master
00625   * @param  hmdios: mdios handle
00626   * @retval bit map of written registers addresses
00627   */
00628 uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
00629 {
00630   return hmdios->Instance->WRFR;
00631 }
00632
00633 /**
00634   * @brief  Gets Read registers by MDIO master
00635   * @param  hmdios: mdios handle
00636   * @retval bit map of read registers addresses
00637   */
00638 uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
00639 {
00640   return hmdios->Instance->RDFR;
00641 }
00642
00643 /**
00644   * @brief  Clears Write registers flag
00645   * @param  hmdios: mdios handle
00646   * @param  RegNum: registers addresses to be cleared
00647   * @retval HAL status
00648   */
00649 HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
00650 {
00651   /* Check the parameters */
00652   assert_param(IS_MDIOS_REGISTER(RegNum));
00653
00654   /* Process Locked */
00655   __HAL_LOCK(hmdios);
00656
00657   /* Clear write registers flags */
00658   hmdios->Instance->CWRFR |= (RegNum);
00659
00660   /* Release Lock */
00661   __HAL_UNLOCK(hmdios);
00662
00663   return HAL_OK;
00664 }
00665
00666 /**
00667   * @brief  Clears Read register flag
00668   * @param  hmdios: mdios handle
00669   * @param  RegNum: registers addresses to be cleared
00670   * @retval HAL status
00671   */
00672 HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
00673 {
00674   /* Check the parameters */
00675   assert_param(IS_MDIOS_REGISTER(RegNum));
00676
00677   /* Process Locked */
00678   __HAL_LOCK(hmdios);
00679
00680   /* Clear read registers flags */
00681   hmdios->Instance->CRDFR |= (RegNum);
00682
00683   /* Release Lock */
00684   __HAL_UNLOCK(hmdios);
00685
00686   return HAL_OK;
00687 }
00688
00689 /**
00690   * @brief  Enables Events for MDIOS peripheral
00691   * @param  hmdios: mdios handle
00692   * @retval HAL status
00693   */
00694 HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
00695 {
00696   /* Process Locked */
00697   __HAL_LOCK(hmdios);
00698
00699   /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
00700   __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
00701
00702   /* Process Unlocked */
00703   __HAL_UNLOCK(hmdios);
00704
00705   return HAL_OK;
00706 }
00707
00708 /**
00709   * @brief This function handles MDIOS interrupt request.
00710   * @param hmdios: MDIOS handle
00711   * @retval None
00712   */
00713 void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
00714 {
00715   /* Write Register Interrupt enabled ? */
00716   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET)
00717   {
00718     /* Write register flag */
00719     if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET)
00720     {
00721 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00722         /*Call registered Write complete callback*/
00723         hmdios->WriteCpltCallback(hmdios);
00724 #else
00725       /* Write callback function */
00726       HAL_MDIOS_WriteCpltCallback(hmdios);
00727 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00728
00729       /* Clear write register flag */
00730       hmdios->Instance->CWRFR |= MDIOS_ALL_REG_FLAG;
00731     }
00732   }
00733
00734   /* Read Register Interrupt enabled ? */
00735   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET)
00736   {
00737     /* Read register flag */
00738     if(HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET)
00739     {
00740 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00741         /*Call registered Read complete callback*/
00742         hmdios->ReadCpltCallback(hmdios);
00743 #else
00744       /* Read callback function  */
00745       HAL_MDIOS_ReadCpltCallback(hmdios);
00746 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00747
00748       /* Clear read register flag */
00749       hmdios->Instance->CRDFR |= MDIOS_ALL_REG_FLAG;
00750     }
00751   }
00752
00753   /* Error Interrupt enabled ? */
00754   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET)
00755   {
00756     /* All Errors Flag */
00757     if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET)
00758     {
00759       hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA;
00760
00761 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00762         /*Call registered Error callback*/
00763         hmdios->ErrorCallback(hmdios);
00764 #else
00765       /* Error Callback */
00766       HAL_MDIOS_ErrorCallback(hmdios);
00767 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00768
00769       /* Clear errors flag */
00770       __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
00771     }
00772     hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
00773   }
00774 #if defined(DUAL_CORE)
00775
00776   if (HAL_GetCurrentCPUID() == CM7_CPUID)
00777   {
00778     if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
00779     {
00780       /* Clear MDIOS WAKEUP Exti pending bit */
00781       __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
00782
00783 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00784       /*Call registered WakeUp callback*/
00785       hmdios->WakeUpCallback(hmdios);
00786 #else
00787       /* MDIOS WAKEUP callback */
00788       HAL_MDIOS_WakeUpCallback(hmdios);
00789 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00790     }
00791   }
00792   else
00793   {
00794     if(__HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
00795     {
00796       /* Clear MDIOS WAKEUP Exti D2 pending bit */
00797       __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
00798 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00799       /*Call registered WakeUp callback*/
00800       hmdios->WakeUpCallback(hmdios);
00801 #else
00802       /* MDIOS WAKEUP callback */
00803       HAL_MDIOS_WakeUpCallback(hmdios);
00804 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00805     }
00806   }
00807 #else
00808   /* check MDIOS WAKEUP exti flag */
00809   if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
00810   {
00811     /* Clear MDIOS WAKEUP Exti pending bit */
00812     __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
00813 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00814       /*Call registered WakeUp callback*/
00815       hmdios->WakeUpCallback(hmdios);
00816 #else
00817       /* MDIOS WAKEUP callback */
00818       HAL_MDIOS_WakeUpCallback(hmdios);
00819 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00820   }
00821 #endif
00822 }
00823
00824 /**
00825   * @brief  Write Complete Callback
00826   * @param  hmdios: mdios handle
00827   * @retval None
00828   */
00829  __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
00830 {
00831   /* Prevent unused argument(s) compilation warning */
00832   UNUSED(hmdios);
00833
00834   /* NOTE : This function should not be modified, when the callback is needed,
00835             the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
00836    */
00837 }
00838
00839 /**
00840   * @brief  Read Complete Callback
00841   * @param  hmdios: mdios handle
00842   * @retval None
00843   */
00844  __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
00845 {
00846   /* Prevent unused argument(s) compilation warning */
00847   UNUSED(hmdios);
00848
00849   /* NOTE : This function should not be modified, when the callback is needed,
00850             the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
00851    */
00852 }
00853
00854 /**
00855   * @brief Error Callback
00856   * @param hmdios: mdios handle
00857   * @retval None
00858   */
00859  __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
00860 {
00861   /* Prevent unused argument(s) compilation warning */
00862   UNUSED(hmdios);
00863
00864   /* NOTE : This function should not be modified, when the callback is needed,
00865             the HAL_MDIOS_ErrorCallback can be implemented in the user file
00866    */
00867 }
00868
00869 /**
00870   * @brief  MDIOS WAKEUP interrupt callback
00871   * @param hmdios: mdios handle
00872   * @retval None
00873   */
00874 __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
00875 {
00876   /* Prevent unused argument(s) compilation warning */
00877   UNUSED(hmdios);
00878
00879   /* NOTE : This function Should not be modified, when the callback is needed,
00880             the HAL_MDIOS_WakeUpCallback could be implemented in the user file
00881    */
00882 }
00883
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
00889   *  @brief   MDIOS control functions
00890   *
00891 @verbatim
00892  ===============================================================================
00893                       ##### Peripheral Control functions #####
00894  ===============================================================================
00895     [..]
00896     This subsection provides a set of functions allowing to control the MDIOS.
00897      (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
00898      (+) HAL_MDIOS_GetError() API, returns the errors code of the HAL state machine.
00899
00900 @endverbatim
00901   * @{
00902   */
00903
00904 /**
00905   * @brief  Gets MDIOS error code
00906   * @param  hmdios: mdios handle
00907   * @retval mdios error code
00908   */
00909 uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
00910 {
00911   /* return the error code */
00912   return hmdios->ErrorCode;
00913 }
00914
00915 /**
00916   * @brief  Return the MDIOS HAL state
00917   * @param  hmdios: mdios handle
00918   * @retval HAL state
00919   */
00920 HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
00921 {
00922   /* Return MDIOS state */
00923   return hmdios->State;
00924 }
00925
00926 /**
00927   * @}
00928   */
00929
00930 /**
00931   * @}
00932   */
00933
00934 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00935 static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
00936 {
00937   /* Init the MDIOS Callback settings */
00938   hmdios->WriteCpltCallback  = HAL_MDIOS_WriteCpltCallback;   /* Legacy weak WriteCpltCallback   */
00939   hmdios->ReadCpltCallback   = HAL_MDIOS_ReadCpltCallback;    /* Legacy weak ReadCpltCallback   */
00940   hmdios->ErrorCallback      = HAL_MDIOS_ErrorCallback;       /* Legacy weak ErrorCallback */
00941   hmdios->WakeUpCallback     = HAL_MDIOS_WakeUpCallback;        /* Legacy weak WakeUpCallback   */
00942 }
00943 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00944
00945 /**
00946   * @}
00947   */
00948 #endif /* HAL_MDIOS_MODULE_ENABLED */
00949 /**
00950   * @}
00951   */
00952 #endif /* MDIOS */
00953 /**
00954   * @}
00955   */
00956
00957 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdios.h Source File

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stm32h7xx_hal_mdios.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdios.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of MDIOS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_MDIOS_H
00022 #define STM32H7xx_HAL_MDIOS_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 #if defined (MDIOS)
00033
00034 /** @addtogroup STM32H7xx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup MDIOS
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup MDIOS_Exported_Types MDIOS Exported Types
00044   * @{
00045   */
00046
00047 /** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
00048   * @{
00049   */
00050
00051 typedef enum
00052 {
00053   HAL_MDIOS_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
00054   HAL_MDIOS_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00055   HAL_MDIOS_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
00056   HAL_MDIOS_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
00057 }HAL_MDIOS_StateTypeDef;
00058
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
00064   * @{
00065   */
00066
00067 typedef struct
00068 {
00069   uint32_t PortAddress;           /*!< Specifies the MDIOS port address.
00070                                        This parameter can be a value from 0 to 31 */
00071   uint32_t PreambleCheck;         /*!< Specifies whether the preamble check is enabled or disabled.
00072                                        This parameter can be a value of @ref MDIOS_Preamble_Check */
00073 }MDIOS_InitTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
00080   * @{
00081   */
00082
00083 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00084 typedef struct __MDIOS_HandleTypeDef
00085 #else
00086 typedef struct
00087 #endif
00088 {
00089   MDIOS_TypeDef                *Instance;     /*!< Register base address       */
00090
00091   MDIOS_InitTypeDef            Init;          /*!< MDIOS Init Structure        */
00092
00093   __IO HAL_MDIOS_StateTypeDef  State;         /*!< MDIOS communication state
00094                                                    This parameter can be a value of of @ref HAL_MDIOS_StateTypeDef */
00095
00096   __IO uint32_t                ErrorCode;     /*!< Holds the global Error code of the MDIOS HAL status machine
00097                                                    This parameter can be a value of of @ref MDIOS_Error_Code */
00098
00099   HAL_LockTypeDef              Lock;          /*!< MDIOS Lock                  */
00100
00101 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00102
00103   void    (* WriteCpltCallback)  ( struct __MDIOS_HandleTypeDef * hmdios);   /*!< MDIOS Write Complete Callback */
00104   void    (* ReadCpltCallback)   ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Read  Complete Callback     */
00105   void    (* ErrorCallback)      ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Error Callback   */
00106   void    (* WakeUpCallback)     ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Wake UP Callback   */
00107
00108   void    (* MspInitCallback)    ( struct __MDIOS_HandleTypeDef * hmdios);    /*!< MDIOS Msp Init callback              */
00109   void    (* MspDeInitCallback)  ( struct __MDIOS_HandleTypeDef * hmdios);    /*!< MDIOS Msp DeInit callback            */
00110
00111 #endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00112 }MDIOS_HandleTypeDef;
00113
00114 /**
00115   * @}
00116   */
00117
00118 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00119 /**
00120   * @brief  HAL MDIOS Callback ID enumeration definition
00121   */
00122 typedef enum
00123 {
00124   HAL_MDIOS_MSPINIT_CB_ID            = 0x00U,    /*!< MDIOS MspInit callback ID           */
00125   HAL_MDIOS_MSPDEINIT_CB_ID          = 0x01U,    /*!< MDIOS MspDeInit callback ID         */
00126
00127   HAL_MDIOS_WRITE_COMPLETE_CB_ID     = 0x02U,    /*!< MDIOS Write Complete Callback ID       */
00128   HAL_MDIOS_READ_COMPLETE_CB_ID      = 0x03U,    /*!< MDIOS Read Complete Callback ID       */
00129   HAL_MDIOS_ERROR_CB_ID              = 0x04U,    /*!< MDIOS Error Callback ID         */
00130   HAL_MDIOS_WAKEUP_CB_ID             = 0x05U     /*!< MDIOS Wake UP Callback ID           */
00131 }HAL_MDIOS_CallbackIDTypeDef;
00132
00133 /**
00134   * @brief  HAL MDIOS Callback pointer definition
00135   */
00136 typedef  void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< pointer to an MDIOS callback function */
00137
00138 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Exported constants --------------------------------------------------------*/
00145 /** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
00146   * @{
00147   */
00148
00149 /** @defgroup MDIOS_Preamble_Check  MDIOS Preamble Check
00150   * @{
00151   */
00152 #define MDIOS_PREAMBLE_CHECK_ENABLE      ((uint32_t)0x00000000U)
00153 #define MDIOS_PREAMBLE_CHECK_DISABLE     MDIOS_CR_DPC
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
00159   * @{
00160   */
00161 #define MDIOS_REG0                      ((uint32_t)0x00000000U)
00162 #define MDIOS_REG1                      ((uint32_t)0x00000001U)
00163 #define MDIOS_REG2                      ((uint32_t)0x00000002U)
00164 #define MDIOS_REG3                      ((uint32_t)0x00000003U)
00165 #define MDIOS_REG4                      ((uint32_t)0x00000004U)
00166 #define MDIOS_REG5                      ((uint32_t)0x00000005U)
00167 #define MDIOS_REG6                      ((uint32_t)0x00000006U)
00168 #define MDIOS_REG7                      ((uint32_t)0x00000007U)
00169 #define MDIOS_REG8                      ((uint32_t)0x00000008U)
00170 #define MDIOS_REG9                      ((uint32_t)0x00000009U)
00171 #define MDIOS_REG10                     ((uint32_t)0x0000000AU)
00172 #define MDIOS_REG11                     ((uint32_t)0x0000000BU)
00173 #define MDIOS_REG12                     ((uint32_t)0x0000000CU)
00174 #define MDIOS_REG13                     ((uint32_t)0x0000000DU)
00175 #define MDIOS_REG14                     ((uint32_t)0x0000000EU)
00176 #define MDIOS_REG15                     ((uint32_t)0x0000000FU)
00177 #define MDIOS_REG16                     ((uint32_t)0x00000010U)
00178 #define MDIOS_REG17                     ((uint32_t)0x00000011U)
00179 #define MDIOS_REG18                     ((uint32_t)0x00000012U)
00180 #define MDIOS_REG19                     ((uint32_t)0x00000013U)
00181 #define MDIOS_REG20                     ((uint32_t)0x00000014U)
00182 #define MDIOS_REG21                     ((uint32_t)0x00000015U)
00183 #define MDIOS_REG22                     ((uint32_t)0x00000016U)
00184 #define MDIOS_REG23                     ((uint32_t)0x00000017U)
00185 #define MDIOS_REG24                     ((uint32_t)0x00000018U)
00186 #define MDIOS_REG25                     ((uint32_t)0x00000019U)
00187 #define MDIOS_REG26                     ((uint32_t)0x0000001AU)
00188 #define MDIOS_REG27                     ((uint32_t)0x0000001BU)
00189 #define MDIOS_REG28                     ((uint32_t)0x0000001CU)
00190 #define MDIOS_REG29                     ((uint32_t)0x0000001DU)
00191 #define MDIOS_REG30                     ((uint32_t)0x0000001EU)
00192 #define MDIOS_REG31                     ((uint32_t)0x0000001FU)
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup MDIOS_Registers_Flags  MDIOS Registers Flags
00198   * @{
00199   */
00200 #define MDIOS_REG0_FLAG                 ((uint32_t)0x00000001U)
00201 #define MDIOS_REG1_FLAG                 ((uint32_t)0x00000002U)
00202 #define MDIOS_REG2_FLAG                 ((uint32_t)0x00000004U)
00203 #define MDIOS_REG3_FLAG                 ((uint32_t)0x00000008U)
00204 #define MDIOS_REG4_FLAG                 ((uint32_t)0x00000010U)
00205 #define MDIOS_REG5_FLAG                 ((uint32_t)0x00000020U)
00206 #define MDIOS_REG6_FLAG                 ((uint32_t)0x00000040U)
00207 #define MDIOS_REG7_FLAG                 ((uint32_t)0x00000080U)
00208 #define MDIOS_REG8_FLAG                 ((uint32_t)0x00000100U)
00209 #define MDIOS_REG9_FLAG                 ((uint32_t)0x00000200U)
00210 #define MDIOS_REG10_FLAG                ((uint32_t)0x00000400U)
00211 #define MDIOS_REG11_FLAG                ((uint32_t)0x00000800U)
00212 #define MDIOS_REG12_FLAG                ((uint32_t)0x00001000U)
00213 #define MDIOS_REG13_FLAG                ((uint32_t)0x00002000U)
00214 #define MDIOS_REG14_FLAG                ((uint32_t)0x00004000U)
00215 #define MDIOS_REG15_FLAG                ((uint32_t)0x00008000U)
00216 #define MDIOS_REG16_FLAG                ((uint32_t)0x00010000U)
00217 #define MDIOS_REG17_FLAG                ((uint32_t)0x00020000U)
00218 #define MDIOS_REG18_FLAG                ((uint32_t)0x00040000U)
00219 #define MDIOS_REG19_FLAG                ((uint32_t)0x00080000U)
00220 #define MDIOS_REG20_FLAG                ((uint32_t)0x00100000U)
00221 #define MDIOS_REG21_FLAG                ((uint32_t)0x00200000U)
00222 #define MDIOS_REG22_FLAG                ((uint32_t)0x00400000U)
00223 #define MDIOS_REG23_FLAG                ((uint32_t)0x00800000U)
00224 #define MDIOS_REG24_FLAG                ((uint32_t)0x01000000U)
00225 #define MDIOS_REG25_FLAG                ((uint32_t)0x02000000U)
00226 #define MDIOS_REG26_FLAG                ((uint32_t)0x04000000U)
00227 #define MDIOS_REG27_FLAG                ((uint32_t)0x08000000U)
00228 #define MDIOS_REG28_FLAG                ((uint32_t)0x10000000U)
00229 #define MDIOS_REG29_FLAG                ((uint32_t)0x20000000U)
00230 #define MDIOS_REG30_FLAG                ((uint32_t)0x40000000U)
00231 #define MDIOS_REG31_FLAG                ((uint32_t)0x80000000U)
00232 #define MDIOS_ALLREG_FLAG               ((uint32_t)0xFFFFFFFFU)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup MDIOS_Interrupt_sources Interrupt Sources
00238   * @{
00239   */
00240 #define MDIOS_IT_WRITE                   MDIOS_CR_WRIE
00241 #define MDIOS_IT_READ                    MDIOS_CR_RDIE
00242 #define MDIOS_IT_ERROR                   MDIOS_CR_EIE
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup MDIOS_Interrupt_Flags  MDIOS Interrupt Flags
00248   * @{
00249   */
00250 #define MDIOS_TURNAROUND_ERROR_FLAG       MDIOS_SR_TERF
00251 #define MDIOS_START_ERROR_FLAG            MDIOS_SR_SERF
00252 #define MDIOS_PREAMBLE_ERROR_FLAG         MDIOS_SR_PERF
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup MDIOS_Error_Code MDIOS Error Code
00258   * @{
00259   */
00260 #define HAL_MDIOS_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00261 #define HAL_MDIOS_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
00262 #define HAL_MDIOS_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
00263 #define HAL_MDIOS_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
00264 #define HAL_MDIOS_ERROR_DATA         ((uint32_t)0x00000010U)   /*!< Data transfer error       */
00265 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00266 #define HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
00267 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00268 /**
00269   * @}
00270   */
00271
00272  /** @defgroup MDIOS_Wakeup_Line  MDIOS Wakeup Line
00273   * @{
00274   */
00275 #define MDIOS_WAKEUP_EXTI_LINE  ((uint32_t)0x00000400)  /* !<  42 - 32 = 10 */
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283 /* Exported macros -----------------------------------------------------------*/
00284 /** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
00285   * @{
00286   */
00287
00288 /** @brief Reset MDIOS handle state
00289   * @param  __HANDLE__: MDIOS handle.
00290   * @retval None
00291   */
00292 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00293 #define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00294                                                        (__HANDLE__)->State = HAL_MDIOS_STATE_RESET;      \
00295                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00296                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00297                                                      } while(0)
00298 #else
00299 #define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
00300 #endif /*USE_HAL_MDIOS_REGISTER_CALLBACKS */
00301
00302 /**
00303   * @brief  Enable/Disable the MDIOS peripheral.
00304   * @param  __HANDLE__: specifies the MDIOS handle.
00305   * @retval None
00306   */
00307 #define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
00308 #define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
00309
00310
00311 /**
00312   * @brief  Enable the MDIOS device interrupt.
00313   * @param  __HANDLE__: specifies the MDIOS handle.
00314   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
00315   *         This parameter can be one or a combination of the following values:
00316   *            @arg MDIOS_IT_WRITE: Register write interrupt
00317   *            @arg MDIOS_IT_READ: Register read interrupt
00318   *            @arg MDIOS_IT_ERROR: Error interrupt
00319   * @retval None
00320   */
00321 #define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00322
00323 /**
00324   * @brief  Disable the MDIOS device interrupt.
00325   * @param  __HANDLE__: specifies the MDIOS handle.
00326   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
00327   *         This parameter can be one or a combination of the following values:
00328   *            @arg MDIOS_IT_WRITE: Register write interrupt
00329   *            @arg MDIOS_IT_READ: Register read interrupt
00330   *            @arg MDIOS_IT_ERROR: Error interrupt
00331   * @retval None
00332   */
00333 #define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00334
00335 /** @brief Set MDIOS slave get write register flag
00336   * @param  __HANDLE__: specifies the MDIOS handle.
00337   * @param  __FLAG__: specifies the write register flag
00338   * @retval The state of write flag
00339   */
00340 #define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->WRFR &  (__FLAG__))
00341
00342 /** @brief MDIOS slave get read register flag
00343   * @param  __HANDLE__: specifies the MDIOS handle.
00344   * @param  __FLAG__: specifies the read register flag
00345   * @retval The state of read flag
00346   */
00347 #define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->RDFR &  (__FLAG__))
00348
00349 /** @brief MDIOS slave get interrupt
00350   * @param  __HANDLE__: specifies the MDIOS handle.
00351   * @param  __FLAG__ : specifies the Error flag.
00352   *         This parameter can be one or a combination of the following values:
00353   *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
00354   *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
00355   *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
00356   * @retval The state of the error flag
00357   */
00358 #define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR &  (__FLAG__))
00359
00360 /** @brief  MDIOS slave clear interrupt
00361   * @param  __HANDLE__: specifies the MDIOS handle.
00362   * @param  __FLAG__ : specifies the Error flag.
00363   *         This parameter can be one or a combination of the following values:
00364   *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
00365   *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
00366   *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
00367   * @retval none
00368   */
00369 #define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
00370
00371 /**
00372   * @brief  Checks whether the specified MDIOS interrupt is set or not.
00373   * @param  __HANDLE__: specifies the MDIOS handle.
00374   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources
00375   *            This parameter can be one or a combination of the following values:
00376   *            @arg MDIOS_IT_WRITE: Register write interrupt
00377   *            @arg MDIOS_IT_READ: Register read interrupt
00378   *            @arg MDIOS_IT_ERROR: Error interrupt
00379   * @retval The state of the interrupt source
00380   */
00381 #define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00382
00383 /**
00384   * @brief Enable the MDIOS WAKEUP Exti Line.
00385   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
00386   * This parameter can be:
00387   *   @arg MDIOS_WAKEUP_EXTI_LINE
00388   * @retval None.
00389   */
00390 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR2 |= (__EXTI_LINE__))
00391
00392 #if defined(DUAL_CORE)
00393 /**
00394   * @brief Enable the MDIOS WAKEUP Exti Line by Domain2.
00395   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
00396   * This parameter can be:
00397   *   @arg MDIOS_WAKEUP_EXTI_LINE
00398   * @retval None.
00399   */
00400 #define __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI->C2IMR2 |= (__EXTI_LINE__))
00401
00402 #endif
00403 /**
00404   * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
00405   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00406   * This parameter can be:
00407   *   @arg MDIOS_WAKEUP_EXTI_LINE
00408   * @retval EXTI MDIOS WAKEUP Line Status.
00409   */
00410 #define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->PR2 & (__EXTI_LINE__))
00411
00412 #if defined(DUAL_CORE)
00413 /**
00414   * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
00415   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00416   * This parameter can be:
00417   *   @arg MDIOS_WAKEUP_EXTI_LINE
00418   * @retval EXTI MDIOS WAKEUP Line Status.
00419   */
00420 #define __HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI->C2PR2 & (__EXTI_LINE__))
00421 #endif
00422 /**
00423   * @brief Clear the MDIOS WAKEUP Exti flag.
00424   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00425   * This parameter can be:
00426   *   @arg MDIOS_WAKEUP_EXTI_LINE
00427   * @retval None.
00428   */
00429 #define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__))
00430
00431 #if defined(DUAL_CORE)
00432 /**
00433   * @brief Clear the MDIOS WAKEUP Exti flag.
00434   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00435   * This parameter can be:
00436   *   @arg MDIOS_WAKEUP_EXTI_LINE
00437   * @retval None.
00438   */
00439 #define __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR2 = (__EXTI_LINE__))
00440
00441 #endif
00442 /**
00443   * @brief  enable rising edge interrupt on selected EXTI line.
00444   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
00445   * This parameter can be:
00446   *  @arg MDIOS_WAKEUP_EXTI_LINE
00447   * @retval None
00448   */
00449 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
00450                                                                    (EXTI->RTSR2 |= (__EXTI_LINE__))
00451
00452 /**
00453   * @brief  enable falling edge interrupt on selected EXTI line.
00454   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
00455   * This parameter can be:
00456   *  @arg MDIOS_WAKEUP_EXTI_LINE
00457   * @retval None
00458   */
00459 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
00460                                                                  (EXTI->FTSR2 |= (__EXTI_LINE__))
00461
00462 /**
00463   * @brief  enable falling edge interrupt on selected EXTI line.
00464   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
00465   * This parameter can be:
00466   *  @arg MDIOS_WAKEUP_EXTI_LINE
00467   * @retval None
00468   */
00469 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
00470                                                                           (EXTI->FTSR2 |= (__EXTI_LINE__))
00471
00472 /**
00473   * @brief  Generates a Software interrupt on selected EXTI line.
00474   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
00475   * This parameter can be:
00476   *  @arg MDIOS_WAKEUP_EXTI_LINE
00477   * @retval None
00478   */
00479 #define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
00480
00481 /**
00482   * @}
00483   */
00484
00485 /* Exported functions --------------------------------------------------------*/
00486 /** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
00487   * @{
00488   */
00489
00490 /** @addtogroup MDIOS_Exported_Functions_Group1
00491   * @{
00492   */
00493 HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
00494 HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
00495 void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
00496 void  HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
00497
00498 /* Callbacks Register/UnRegister functions  ***********************************/
00499 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
00500 HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback);
00501 HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID);
00502 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
00503 /**
00504   * @}
00505   */
00506
00507 /** @addtogroup MDIOS_Exported_Functions_Group2
00508   * @{
00509   */
00510 HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t Data);
00511 HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t *pData);
00512
00513 uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
00514 uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
00515 HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
00516 HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
00517
00518 HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
00519 void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
00520 void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
00521 void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
00522 void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
00523 void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
00524 /**
00525   * @}
00526   */
00527
00528 /** @addtogroup MDIOS_Exported_Functions_Group3
00529   * @{
00530   */
00531 uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
00532 HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /* Private types -------------------------------------------------------------*/
00542 /** @defgroup MDIOS_Private_Types MDIOS Private Types
00543   * @{
00544   */
00545
00546 /**
00547   * @}
00548   */
00549
00550 /* Private variables ---------------------------------------------------------*/
00551 /** @defgroup MDIOS_Private_Variables MDIOS Private Variables
00552   * @{
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /* Private constants ---------------------------------------------------------*/
00560 /** @defgroup MDIOS_Private_Constants MDIOS Private Constants
00561   * @{
00562   */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /* Private macros ------------------------------------------------------------*/
00569 /** @defgroup MDIOS_Private_Macros MDIOS Private Macros
00570   * @{
00571   */
00572
00573 #define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U)
00574
00575 #define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U)
00576
00577 #define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
00578                                                    ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
00579
00580  /**
00581   * @}
00582   */
00583
00584 /* Private functions ---------------------------------------------------------*/
00585 /** @defgroup MDIOS_Private_Functions MDIOS Private Functions
00586   * @{
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593
00594 /**
00595   * @}
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 #endif /* MDIOS */
00603
00604 #ifdef __cplusplus
00605 }
00606 #endif
00607
00608 #endif /* STM32H7xx_HAL_MDIOS_H */
00609
00610 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdma.c Source File

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stm32h7xx_hal_mdma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdma.c
00004   * @author  MCD Application Team
00005   * @brief  This file provides firmware functions to manage the following
00006   *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
00007   *           + Initialization/de-initialization functions
00008   *           + I/O operation functions
00009   *           + Peripheral State and errors functions
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015    (#) Enable and configure the peripheral to be connected to the MDMA Channel
00016        (except for internal SRAM/FLASH memories: no initialization is
00017        necessary) please refer to Reference manual for connection between peripherals
00018        and MDMA requests.
00019
00020    (#)
00021        For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
00022        transfer request , channel priority, data endianness, Source increment, destination increment ,
00023        source data size, destination data size, data alignment, source Burst, destination Burst ,
00024        buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
00025        or full transfer) source and destination block address offset, mask address and data.
00026
00027        If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
00028        Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
00029        Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
00030        User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
00031        last node of the list to the first one in order to make the list circular.
00032        In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
00033
00034       -@-   The initial transfer itself (node 0 corresponding to the Init).
00035             User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
00036             the connection between last node and first one.
00037
00038        Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
00039        When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
00040        the linked list remains circular and node 2 becomes the first one.
00041        Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
00042
00043     [..]
00044        (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
00045            transfer upon a request :
00046              (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
00047                with BufferTransferLength defined within the HAL_MDMA_Init.
00048              (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
00049                with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
00050                or within the current linked list node parameters.
00051              (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
00052                with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
00053                or within the current linked list node parameters.
00054              (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
00055               all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
00056
00057      *** Polling mode IO operation ***
00058      =================================
00059     [..]
00060           (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
00061               address and destination address and the Length of data to be transferred.
00062           (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
00063              In this case a fixed Timeout can be configured by User depending from his application.
00064           (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
00065               when the abort ends or timeout (should not be called from an interrupt service routine).
00066
00067      *** Interrupt mode IO operation ***
00068      ===================================
00069     [..]
00070           (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
00071           (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
00072           (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
00073               Source address and destination address and the Length of data to be transferred. In this
00074               case the MDMA interrupt is configured.
00075           (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
00076           (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
00077               add his own function by customization of function pointer XferCpltCallback and
00078               XferErrorCallback (i.e a member of MDMA handle structure).
00079
00080           (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
00081               then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
00082               (could be called from an interrupt service routine).
00083
00084           (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
00085               from the following list :
00086               (++) XferCpltCallback            : transfer complete callback.
00087               (++) XferBufferCpltCallback      : buffer transfer complete callback.
00088               (++) XferBlockCpltCallback       : block transfer complete callback.
00089               (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
00090               (++) XferErrorCallback           : transfer error callback.
00091               (++) XferAbortCallback           : transfer abort complete callback.
00092
00093     [..]
00094          (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
00095               trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
00096               (++) This function returns an error if used while the Transfer has ended or not started.
00097               (++) If used while the current request has not been served yet (current request transfer on going)
00098                 this function returns an error and the new request is ignored.
00099
00100               Generally this function should be used in conjunctions with the MDMA callbacks:
00101               (++) example 1:
00102                  (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
00103                  (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
00104                  (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
00105                  (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
00106                    request using HAL_MDMA_GenerateSWRequest.
00107
00108               (++) example 2:
00109                  (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
00110                  (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
00111                  (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
00112                  (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
00113                    for a new block transfer request using HAL_MDMA_GenerateSWRequest.
00114
00115     [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
00116
00117      *** MDMA HAL driver macros list ***
00118      =============================================
00119      [..]
00120        Below the list of most used macros in MDMA HAL driver.
00121
00122       (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
00123       (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
00124       (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
00125       (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
00126       (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
00127       (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
00128       (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
00129
00130      [..]
00131       (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
00132
00133     [..]
00134
00135     @endverbatim
00136   ******************************************************************************
00137   * @attention
00138   *
00139   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00140   * All rights reserved.</center></h2>
00141   *
00142   * This software component is licensed by ST under BSD 3-Clause license,
00143   * the "License"; You may not use this file except in compliance with the
00144   * License. You may obtain a copy of the License at:
00145   *                        opensource.org/licenses/BSD-3-Clause
00146   *
00147   ******************************************************************************
00148   */
00149
00150 /* Includes ------------------------------------------------------------------*/
00151 #include "stm32h7xx_hal.h"
00152
00153 /** @addtogroup STM32H7xx_HAL_Driver
00154   * @{
00155   */
00156
00157 /** @defgroup MDMA  MDMA
00158   * @brief MDMA HAL module driver
00159   * @{
00160   */
00161
00162 #ifdef HAL_MDMA_MODULE_ENABLED
00163
00164 /* Private typedef -----------------------------------------------------------*/
00165 /* Private constants ---------------------------------------------------------*/
00166 /** @addtogroup MDMA_Private_Constants
00167  * @{
00168  */
00169 #define HAL_TIMEOUT_MDMA_ABORT    5U    /* 5 ms */
00170 #define HAL_MDMA_CHANNEL_SIZE     0x40U /* an MDMA instance channel size is 64 byte  */
00171 /**
00172   * @}
00173   */
00174 /* Private macro -------------------------------------------------------------*/
00175 /* Private variables ---------------------------------------------------------*/
00176 /* Private function prototypes -----------------------------------------------*/
00177 /** @addtogroup MDMA_Private_Functions_Prototypes
00178   * @{
00179   */
00180 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00181 static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
00188   * @{
00189   */
00190
00191 /** @addtogroup MDMA_Exported_Functions_Group1
00192   *
00193 @verbatim
00194  ===============================================================================
00195              ##### Initialization and de-initialization functions  #####
00196  ===============================================================================
00197     [..]
00198     This section provides functions allowing to :
00199       Initialize and de-initialize the MDMA channel.
00200       Register and Unregister MDMA callbacks
00201     [..]
00202     The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
00203     reference manual.
00204     The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
00205     HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
00206     respectevely to register/unregister an MDMA callback function.
00207
00208 @endverbatim
00209   * @{
00210   */
00211
00212 /**
00213   * @brief  Initializes the MDMA according to the specified
00214   *         parameters in the MDMA_InitTypeDef and create the associated handle.
00215   * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
00216   *               the configuration information for the specified MDMA Channel.
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
00220 {
00221   uint32_t tickstart = HAL_GetTick();
00222
00223   /* Check the MDMA peripheral handle */
00224   if(hmdma == NULL)
00225   {
00226     return HAL_ERROR;
00227   }
00228
00229   /* Check the parameters */
00230   assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
00231   assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
00232   assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
00233   assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
00234   assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
00235   assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
00236   assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
00237   assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
00238   assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
00239   assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
00240   assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
00241   assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
00242   assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
00243   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
00244   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
00245
00246
00247   /* Allocate lock resource */
00248   __HAL_UNLOCK(hmdma);
00249
00250   /* Change MDMA peripheral state */
00251   hmdma->State = HAL_MDMA_STATE_BUSY;
00252
00253   /* Disable the MDMA channel */
00254   __HAL_MDMA_DISABLE(hmdma);
00255
00256   /* Check if the MDMA channel is effectively disabled */
00257   while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
00258   {
00259     /* Check for the Timeout */
00260     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
00261     {
00262       /* Update error code */
00263       hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
00264
00265       /* Change the MDMA state */
00266       hmdma->State = HAL_MDMA_STATE_ERROR;
00267
00268       return HAL_ERROR;
00269     }
00270   }
00271
00272   /* Initialize the MDMA channel registers */
00273   MDMA_Init(hmdma);
00274
00275   /* Reset the MDMA first/last linkedlist node addresses and node counter */
00276   hmdma->FirstLinkedListNodeAddress  = 0;
00277   hmdma->LastLinkedListNodeAddress   = 0;
00278   hmdma->LinkedListNodeCounter  = 0;
00279
00280   /* Initialize the error code */
00281   hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
00282
00283   /* Initialize the MDMA state */
00284   hmdma->State = HAL_MDMA_STATE_READY;
00285
00286   return HAL_OK;
00287 }
00288
00289 /**
00290   * @brief  DeInitializes the MDMA peripheral
00291   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
00292   *               the configuration information for the specified MDMA Channel.
00293   * @retval HAL status
00294   */
00295 HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
00296 {
00297
00298   /* Check the MDMA peripheral handle */
00299   if(hmdma == NULL)
00300   {
00301     return HAL_ERROR;
00302   }
00303
00304   /* Disable the selected MDMA Channelx */
00305   __HAL_MDMA_DISABLE(hmdma);
00306
00307   /* Reset MDMA Channel control register */
00308   hmdma->Instance->CCR  = 0;
00309   hmdma->Instance->CTCR = 0;
00310   hmdma->Instance->CBNDTR = 0;
00311   hmdma->Instance->CSAR = 0;
00312   hmdma->Instance->CDAR = 0;
00313   hmdma->Instance->CBRUR = 0;
00314   hmdma->Instance->CLAR = 0;
00315   hmdma->Instance->CTBR = 0;
00316   hmdma->Instance->CMAR = 0;
00317   hmdma->Instance->CMDR = 0;
00318
00319   /* Clear all flags */
00320   __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
00321
00322   /* Reset the  MDMA first/last linkedlist node addresses and node counter */
00323   hmdma->FirstLinkedListNodeAddress  = 0;
00324   hmdma->LastLinkedListNodeAddress   = 0;
00325   hmdma->LinkedListNodeCounter  = 0;
00326
00327   /* Initialize the error code */
00328   hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
00329
00330   /* Initialize the MDMA state */
00331   hmdma->State = HAL_MDMA_STATE_RESET;
00332
00333   /* Release Lock */
00334   __HAL_UNLOCK(hmdma);
00335
00336   return HAL_OK;
00337 }
00338
00339 /**
00340   * @brief  Config the Post request Mask address and Mask data
00341   * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
00342   *                               the configuration information for the specified MDMA Channel.
00343   * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
00344   * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
00345   *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
00346   * @retval HAL status
00347   */
00348 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
00349 {
00350   HAL_StatusTypeDef  status = HAL_OK;
00351
00352   /* Check the MDMA peripheral handle */
00353   if(hmdma == NULL)
00354   {
00355     return HAL_ERROR;
00356   }
00357
00358   /* Process locked */
00359   __HAL_LOCK(hmdma);
00360
00361   if(HAL_MDMA_STATE_READY == hmdma->State)
00362   {
00363     /* if HW request set Post Request MaskAddress and MaskData,  */
00364     if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
00365     {
00366       /* Set the HW request clear Mask and Data */
00367       hmdma->Instance->CMAR = MaskAddress;
00368       hmdma->Instance->CMDR = MaskData;
00369
00370       /*
00371       -If the request is done by SW : BWM could be set to 1 or 0.
00372       -If the request is done by a peripheral :
00373          If mask address not set (0) => BWM must be set to 0
00374          If mask address set (different than 0) => BWM could be set to 1 or 0
00375       */
00376       if(MaskAddress == 0U)
00377       {
00378         hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
00379       }
00380       else
00381       {
00382         hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
00383       }
00384     }
00385     else
00386     {
00387       /* Return error status */
00388       status =  HAL_ERROR;
00389     }
00390   }
00391   else
00392   {
00393     /* Return error status */
00394     status =  HAL_ERROR;
00395   }
00396   /* Release Lock */
00397   __HAL_UNLOCK(hmdma);
00398
00399   return status;
00400 }
00401
00402 /**
00403   * @brief  Register callbacks
00404   * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
00405   *                               the configuration information for the specified MDMA Channel.
00406   * @param  CallbackID:           User Callback identifier
00407   * @param  pCallback:            pointer to callbacsk function.
00408   * @retval HAL status
00409   */
00410 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
00411 {
00412   HAL_StatusTypeDef status = HAL_OK;
00413
00414   /* Check the MDMA peripheral handle */
00415   if(hmdma == NULL)
00416   {
00417     return HAL_ERROR;
00418   }
00419
00420   /* Process locked */
00421   __HAL_LOCK(hmdma);
00422
00423   if(HAL_MDMA_STATE_READY == hmdma->State)
00424   {
00425     switch (CallbackID)
00426     {
00427     case  HAL_MDMA_XFER_CPLT_CB_ID:
00428       hmdma->XferCpltCallback = pCallback;
00429       break;
00430
00431     case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
00432       hmdma->XferBufferCpltCallback = pCallback;
00433       break;
00434
00435     case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
00436       hmdma->XferBlockCpltCallback = pCallback;
00437       break;
00438
00439     case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
00440       hmdma->XferRepeatBlockCpltCallback = pCallback;
00441       break;
00442
00443     case  HAL_MDMA_XFER_ERROR_CB_ID:
00444       hmdma->XferErrorCallback = pCallback;
00445       break;
00446
00447     case  HAL_MDMA_XFER_ABORT_CB_ID:
00448       hmdma->XferAbortCallback = pCallback;
00449       break;
00450
00451     default:
00452       break;
00453     }
00454   }
00455   else
00456   {
00457     /* Return error status */
00458     status =  HAL_ERROR;
00459   }
00460
00461   /* Release Lock */
00462   __HAL_UNLOCK(hmdma);
00463
00464   return status;
00465 }
00466
00467 /**
00468   * @brief  UnRegister callbacks
00469   * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
00470   *                               the configuration information for the specified MDMA Channel.
00471   * @param  CallbackID:           User Callback identifier
00472   *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
00476 {
00477   HAL_StatusTypeDef status = HAL_OK;
00478
00479   /* Check the MDMA peripheral handle */
00480   if(hmdma == NULL)
00481   {
00482     return HAL_ERROR;
00483   }
00484
00485   /* Process locked */
00486   __HAL_LOCK(hmdma);
00487
00488   if(HAL_MDMA_STATE_READY == hmdma->State)
00489   {
00490     switch (CallbackID)
00491     {
00492     case  HAL_MDMA_XFER_CPLT_CB_ID:
00493       hmdma->XferCpltCallback = NULL;
00494       break;
00495
00496     case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
00497       hmdma->XferBufferCpltCallback = NULL;
00498       break;
00499
00500     case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
00501       hmdma->XferBlockCpltCallback = NULL;
00502       break;
00503
00504     case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
00505       hmdma->XferRepeatBlockCpltCallback = NULL;
00506       break;
00507
00508     case  HAL_MDMA_XFER_ERROR_CB_ID:
00509       hmdma->XferErrorCallback = NULL;
00510       break;
00511
00512     case  HAL_MDMA_XFER_ABORT_CB_ID:
00513       hmdma->XferAbortCallback = NULL;
00514       break;
00515
00516     case   HAL_MDMA_XFER_ALL_CB_ID:
00517       hmdma->XferCpltCallback = NULL;
00518       hmdma->XferBufferCpltCallback = NULL;
00519       hmdma->XferBlockCpltCallback = NULL;
00520       hmdma->XferRepeatBlockCpltCallback = NULL;
00521       hmdma->XferErrorCallback = NULL;
00522       hmdma->XferAbortCallback = NULL;
00523       break;
00524
00525     default:
00526       status = HAL_ERROR;
00527       break;
00528     }
00529   }
00530   else
00531   {
00532     status = HAL_ERROR;
00533   }
00534
00535   /* Release Lock */
00536   __HAL_UNLOCK(hmdma);
00537
00538   return status;
00539 }
00540
00541 /**
00542   * @}
00543   */
00544
00545 /** @addtogroup MDMA_Exported_Functions_Group2
00546  *
00547 @verbatim
00548  ===============================================================================
00549                       #####  Linked list operation functions  #####
00550  ===============================================================================
00551     [..]  This section provides functions allowing to:
00552       (+) Create a linked list node
00553       (+) Add a node to the MDMA linked list
00554       (+) Remove a node from the MDMA linked list
00555       (+) Enable/Disable linked list circular mode
00556 @endverbatim
00557   * @{
00558   */
00559
00560 /**
00561   * @brief  Initializes an MDMA Link Node according to the specified
00562   *         parameters in the pMDMA_LinkedListNodeConfig .
00563   * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00564   *         registers configurations.
00565   * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
00566   *               the configuration information for the specified MDMA Linked List Node.
00567   * @retval HAL status
00568   */
00569 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
00570 {
00571   uint32_t addressMask;
00572   uint32_t blockoffset;
00573
00574   /* Check the MDMA peripheral state */
00575   if((pNode == NULL) || (pNodeConfig == NULL))
00576   {
00577     return HAL_ERROR;
00578   }
00579
00580   /* Check the parameters */
00581   assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
00582   assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
00583   assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
00584   assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
00585   assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
00586   assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
00587   assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
00588   assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
00589   assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
00590   assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
00591   assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
00592   assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
00593   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
00594   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
00595
00596   assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
00597   assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
00598
00599
00600   /* Configure next Link node Address Register to zero */
00601   pNode->CLAR =  0;
00602
00603   /* Configure the Link Node registers*/
00604   pNode->CTBR   = 0;
00605   pNode->CMAR   = 0;
00606   pNode->CMDR   = 0;
00607   pNode->Reserved = 0;
00608
00609   /* Write new CTCR Register value */
00610   pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
00611     pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize           | \
00612       pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst            | \
00613         pNodeConfig->Init.DestBurst                                             | \
00614           ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
00615             pNodeConfig->Init.TransferTriggerMode;
00616
00617   /* If SW request set the CTCR register to SW Request Mode*/
00618   if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
00619   {
00620     pNode->CTCR |= MDMA_CTCR_SWRM;
00621   }
00622
00623   /*
00624   -If the request is done by SW : BWM could be set to 1 or 0.
00625   -If the request is done by a peripheral :
00626      If mask address not set (0) => BWM must be set to 0
00627      If mask address set (different than 0) => BWM could be set to 1 or 0
00628   */
00629   if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
00630   {
00631     pNode->CTCR |=  MDMA_CTCR_BWM;
00632   }
00633
00634   /* Set the new CBNDTR Register value */
00635   pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
00636
00637   /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
00638   if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
00639   {
00640     pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
00641     /*write new CBRUR Register value : source repeat block offset */
00642     blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
00643     pNode->CBRUR = blockoffset & 0x0000FFFFU;
00644   }
00645   else
00646   {
00647     /*write new CBRUR Register value : source repeat block offset */
00648     pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
00649   }
00650
00651   /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
00652   if(pNodeConfig->Init.DestBlockAddressOffset < 0)
00653   {
00654     pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
00655     /*write new CBRUR Register value : destination repeat block offset */
00656     blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
00657     pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
00658   }
00659   else
00660   {
00661     /*write new CBRUR Register value : destination repeat block offset */
00662     pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
00663   }
00664
00665   /* Configure MDMA Link Node data length */
00666   pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
00667
00668   /* Configure MDMA Link Node destination address */
00669   pNode->CDAR = pNodeConfig->DstAddress;
00670
00671   /* Configure MDMA Link Node Source address */
00672   pNode->CSAR = pNodeConfig->SrcAddress;
00673
00674   /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
00675   if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
00676   {
00677     /* Set the HW request in CTBR register  */
00678     pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
00679     /* Set the HW request clear Mask and Data */
00680     pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
00681     pNode->CMDR = pNodeConfig->PostRequestMaskData;
00682   }
00683
00684   addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
00685   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
00686   {
00687     /*The AHBSbus is used as source (read operation) on channel x */
00688     pNode->CTBR |= MDMA_CTBR_SBUS;
00689   }
00690
00691   addressMask = pNodeConfig->DstAddress & 0xFF000000U;
00692   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
00693   {
00694     /*The AHB bus is used as destination (write operation) on channel x */
00695     pNode->CTBR |= MDMA_CTBR_DBUS;
00696   }
00697
00698   return HAL_OK;
00699 }
00700
00701 /**
00702   * @brief  Connect a node to the linked list.
00703   * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
00704   *                    the configuration information for the specified MDMA Channel.
00705   * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00706   *                    to be add to the list.
00707   * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
00708   *                    at the end of the list
00709   *
00710   * @retval HAL status
00711   */
00712 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
00713 {
00714   MDMA_LinkNodeTypeDef *pNode;
00715   uint32_t counter = 0, nodeInserted = 0;
00716   HAL_StatusTypeDef hal_status = HAL_OK;
00717
00718   /* Check the MDMA peripheral handle */
00719   if((hmdma == NULL) || (pNewNode == NULL))
00720   {
00721     return HAL_ERROR;
00722   }
00723
00724   /* Process locked */
00725   __HAL_LOCK(hmdma);
00726
00727   if(HAL_MDMA_STATE_READY == hmdma->State)
00728   {
00729     /* Change MDMA peripheral state */
00730     hmdma->State = HAL_MDMA_STATE_BUSY;
00731
00732     /* Check if this is the first node (after the Inititlization node) */
00733     if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
00734     {
00735       if(pPrevNode == NULL)
00736       {
00737         /* if this is the first node after the initialization
00738         connect this node to the node 0 by updating
00739         the MDMA channel CLAR register to this node address */
00740         hmdma->Instance->CLAR = (uint32_t)pNewNode;
00741         /* Set the MDMA handle First linked List node*/
00742         hmdma->FirstLinkedListNodeAddress = pNewNode;
00743
00744         /*reset New node link */
00745         pNewNode->CLAR = 0;
00746
00747         /* Update the Handle last node address */
00748         hmdma->LastLinkedListNodeAddress = pNewNode;
00749
00750         hmdma->LinkedListNodeCounter = 1;
00751       }
00752       else
00753       {
00754         hal_status = HAL_ERROR;
00755       }
00756     }
00757     else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
00758     {
00759       /* Check if the node to insert already exists*/
00760       pNode = hmdma->FirstLinkedListNodeAddress;
00761       while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
00762       {
00763         if(pNode->CLAR == (uint32_t)pNewNode)
00764         {
00765           hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
00766         }
00767         pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
00768         counter++;
00769       }
00770
00771       if(hal_status == HAL_OK)
00772       {
00773         /* Check if the previous node is the last one in the current list or zero */
00774         if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
00775         {
00776           /* insert the new node at the end of the list */
00777           pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
00778           hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
00779           /* Update the Handle last node address */
00780           hmdma->LastLinkedListNodeAddress = pNewNode;
00781           /* Increment the linked list node counter */
00782           hmdma->LinkedListNodeCounter++;
00783         }
00784         else
00785         {
00786           /*insert the new node after the pPreviousNode node */
00787           pNode = hmdma->FirstLinkedListNodeAddress;
00788           counter = 0;
00789           while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
00790           {
00791             counter++;
00792             if(pNode == pPrevNode)
00793             {
00794               /*Insert the new node after the previous one */
00795               pNewNode->CLAR = pNode->CLAR;
00796               pNode->CLAR = (uint32_t)pNewNode;
00797               /* Increment the linked list node counter */
00798               hmdma->LinkedListNodeCounter++;
00799               nodeInserted = 1;
00800             }
00801             else
00802             {
00803               pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
00804             }
00805           }
00806
00807           if(nodeInserted == 0U)
00808           {
00809             hal_status = HAL_ERROR;
00810           }
00811         }
00812       }
00813     }
00814     else
00815     {
00816       hal_status = HAL_ERROR;
00817     }
00818
00819     /* Process unlocked */
00820     __HAL_UNLOCK(hmdma);
00821
00822     hmdma->State = HAL_MDMA_STATE_READY;
00823
00824     return hal_status;
00825   }
00826   else
00827   {
00828     /* Process unlocked */
00829     __HAL_UNLOCK(hmdma);
00830
00831     /* Return error status */
00832     return HAL_BUSY;
00833   }
00834 }
00835
00836 /**
00837   * @brief  Disconnect/Remove a node from the transfer linked list.
00838   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
00839   *                 the configuration information for the specified MDMA Channel.
00840   * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00841   *                 to be removed from the list.
00842   *
00843   * @retval HAL status
00844   */
00845 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
00846 {
00847   MDMA_LinkNodeTypeDef *ptmpNode;
00848   uint32_t counter = 0, nodeDeleted = 0;
00849   HAL_StatusTypeDef hal_status = HAL_OK;
00850
00851   /* Check the MDMA peripheral handle */
00852   if((hmdma == NULL) || (pNode == NULL))
00853   {
00854     return HAL_ERROR;
00855   }
00856
00857   /* Process locked */
00858   __HAL_LOCK(hmdma);
00859
00860   if(HAL_MDMA_STATE_READY == hmdma->State)
00861   {
00862     /* Change MDMA peripheral state */
00863     hmdma->State = HAL_MDMA_STATE_BUSY;
00864
00865     /* If first and last node are null (no nodes in the list) : return error*/
00866     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
00867     {
00868       hal_status = HAL_ERROR;
00869     }
00870     else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
00871     {
00872       /* Delete 1st node */
00873       if(hmdma->LastLinkedListNodeAddress == pNode)
00874       {
00875         /*if the last node is at the same time the first one (1 single node after the init node 0)
00876         then update the last node too */
00877
00878         hmdma->FirstLinkedListNodeAddress = 0;
00879         hmdma->LastLinkedListNodeAddress  = 0;
00880         hmdma->LinkedListNodeCounter = 0;
00881
00882         hmdma->Instance->CLAR = 0;
00883       }
00884       else
00885       {
00886         if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
00887         {
00888           /* if last node is looping to first (circular list) one update the last node connection */
00889           hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
00890         }
00891
00892         /* if deleting the first node after the initialization
00893         connect the next node to the node 0 by updating
00894         the MDMA channel CLAR register to this node address */
00895         hmdma->Instance->CLAR = pNode->CLAR;
00896         hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
00897         /* Update the Handle node counter */
00898         hmdma->LinkedListNodeCounter--;
00899       }
00900     }
00901     else /* Deleting any other node */
00902     {
00903       /*Deleted node is not the first one : find it  */
00904       ptmpNode = hmdma->FirstLinkedListNodeAddress;
00905       while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
00906       {
00907         counter++;
00908         if(ptmpNode->CLAR == ((uint32_t)pNode))
00909         {
00910           /* if deleting the last node */
00911           if(pNode == hmdma->LastLinkedListNodeAddress)
00912           {
00913             /*Update the linked list last node address in the handle*/
00914             hmdma->LastLinkedListNodeAddress = ptmpNode;
00915           }
00916           /* update the next node link after deleting pMDMA_LinkedListNode */
00917           ptmpNode->CLAR = pNode->CLAR;
00918           nodeDeleted = 1;
00919           /* Update the Handle node counter */
00920           hmdma->LinkedListNodeCounter--;
00921         }
00922         else
00923         {
00924           ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
00925         }
00926       }
00927
00928       if(nodeDeleted == 0U)
00929       {
00930         /* last node reashed without finding the node to delete : return error */
00931         hal_status = HAL_ERROR;
00932       }
00933     }
00934
00935     /* Process unlocked */
00936     __HAL_UNLOCK(hmdma);
00937
00938     hmdma->State = HAL_MDMA_STATE_READY;
00939
00940     return hal_status;
00941   }
00942   else
00943   {
00944     /* Process unlocked */
00945     __HAL_UNLOCK(hmdma);
00946
00947     /* Return error status */
00948     return HAL_BUSY;
00949   }
00950 }
00951
00952 /**
00953   * @brief  Make the linked list circular by connecting the last node to the first.
00954   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
00955   *                 the configuration information for the specified MDMA Channel.
00956   * @retval HAL status
00957   */
00958 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
00959 {
00960   HAL_StatusTypeDef hal_status = HAL_OK;
00961
00962   /* Check the MDMA peripheral handle */
00963   if(hmdma == NULL)
00964   {
00965     return HAL_ERROR;
00966   }
00967
00968   /* Process locked */
00969   __HAL_LOCK(hmdma);
00970
00971   if(HAL_MDMA_STATE_READY == hmdma->State)
00972   {
00973     /* Change MDMA peripheral state */
00974     hmdma->State = HAL_MDMA_STATE_BUSY;
00975
00976     /* If first and last node are null (no nodes in the list) : return error*/
00977     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
00978     {
00979       hal_status = HAL_ERROR;
00980     }
00981     else
00982     {
00983       /* to enable circular mode Last Node should be connected to first node */
00984       hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
00985     }
00986
00987   }
00988   /* Process unlocked */
00989   __HAL_UNLOCK(hmdma);
00990
00991   hmdma->State = HAL_MDMA_STATE_READY;
00992
00993   return hal_status;
00994 }
00995
00996 /**
00997   * @brief  Disable the linked list circular mode by setting the last node connection to null
00998   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
00999   *                 the configuration information for the specified MDMA Channel.
01000   * @retval HAL status
01001   */
01002 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
01003 {
01004   HAL_StatusTypeDef hal_status = HAL_OK;
01005
01006   /* Check the MDMA peripheral handle */
01007   if(hmdma == NULL)
01008   {
01009     return HAL_ERROR;
01010   }
01011
01012   /* Process locked */
01013   __HAL_LOCK(hmdma);
01014
01015   if(HAL_MDMA_STATE_READY == hmdma->State)
01016   {
01017     /* Change MDMA peripheral state */
01018     hmdma->State = HAL_MDMA_STATE_BUSY;
01019
01020     /* If first and last node are null (no nodes in the list) : return error*/
01021     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
01022     {
01023       hal_status = HAL_ERROR;
01024     }
01025     else
01026     {
01027       /* to disable circular mode Last Node should be connected to NULL */
01028       hmdma->LastLinkedListNodeAddress->CLAR = 0;
01029     }
01030
01031   }
01032   /* Process unlocked */
01033   __HAL_UNLOCK(hmdma);
01034
01035   hmdma->State = HAL_MDMA_STATE_READY;
01036
01037   return hal_status;
01038 }
01039
01040 /**
01041   * @}
01042   */
01043
01044 /** @addtogroup MDMA_Exported_Functions_Group3
01045  *
01046 @verbatim
01047  ===============================================================================
01048                       #####  IO operation functions  #####
01049  ===============================================================================
01050     [..]  This section provides functions allowing to:
01051       (+) Configure the source, destination address and data length and Start MDMA transfer
01052       (+) Configure the source, destination address and data length and
01053           Start MDMA transfer with interrupt
01054       (+) Abort MDMA transfer
01055       (+) Poll for transfer complete
01056       (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
01057       (+) Handle MDMA interrupt request
01058
01059 @endverbatim
01060   * @{
01061   */
01062
01063 /**
01064   * @brief  Starts the MDMA Transfer.
01065   * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
01066   *                           the configuration information for the specified MDMA Channel.
01067   * @param  SrcAddress      : The source memory Buffer address
01068   * @param  DstAddress      : The destination memory Buffer address
01069   * @param  BlockDataLength : The length of a block transfer in bytes
01070   * @param  BlockCount      : The number of a blocks to be transfer
01071   * @retval HAL status
01072   */
01073 HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01074 {
01075   /* Check the parameters */
01076   assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
01077   assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
01078
01079   /* Check the MDMA peripheral handle */
01080   if(hmdma == NULL)
01081   {
01082     return HAL_ERROR;
01083   }
01084
01085   /* Process locked */
01086   __HAL_LOCK(hmdma);
01087
01088   if(HAL_MDMA_STATE_READY == hmdma->State)
01089   {
01090     /* Change MDMA peripheral state */
01091     hmdma->State = HAL_MDMA_STATE_BUSY;
01092
01093     /* Initialize the error code */
01094     hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
01095
01096     /* Disable the peripheral */
01097     __HAL_MDMA_DISABLE(hmdma);
01098
01099     /* Configure the source, destination address and the data length */
01100     MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
01101
01102     /* Enable the Peripheral */
01103     __HAL_MDMA_ENABLE(hmdma);
01104
01105     if(hmdma->Init.Request == MDMA_REQUEST_SW)
01106     {
01107       /* activate If SW request mode*/
01108       hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
01109     }
01110   }
01111   else
01112   {
01113     /* Process unlocked */
01114     __HAL_UNLOCK(hmdma);
01115
01116     /* Return error status */
01117     return HAL_BUSY;
01118   }
01119
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief  Starts the MDMA Transfer with interrupts enabled.
01125   * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
01126   *                           the configuration information for the specified MDMA Channel.
01127   * @param  SrcAddress      : The source memory Buffer address
01128   * @param  DstAddress      : The destination memory Buffer address
01129   * @param  BlockDataLength : The length of a block transfer in bytes
01130   * @param  BlockCount      : The number of a blocks to be transfer
01131   * @retval HAL status
01132   */
01133 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01134 {
01135   /* Check the parameters */
01136   assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
01137   assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
01138
01139   /* Check the MDMA peripheral handle */
01140   if(hmdma == NULL)
01141   {
01142     return HAL_ERROR;
01143   }
01144
01145   /* Process locked */
01146   __HAL_LOCK(hmdma);
01147
01148   if(HAL_MDMA_STATE_READY == hmdma->State)
01149   {
01150     /* Change MDMA peripheral state */
01151     hmdma->State = HAL_MDMA_STATE_BUSY;
01152
01153     /* Initialize the error code */
01154     hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
01155
01156     /* Disable the peripheral */
01157     __HAL_MDMA_DISABLE(hmdma);
01158
01159     /* Configure the source, destination address and the data length */
01160     MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
01161
01162     /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
01163     __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
01164
01165     if(hmdma->XferBlockCpltCallback != NULL)
01166     {
01167       /* if Block transfer complete Callback is set enable the corresponding IT*/
01168       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
01169     }
01170
01171     if(hmdma->XferRepeatBlockCpltCallback != NULL)
01172     {
01173       /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
01174       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
01175     }
01176
01177     if(hmdma->XferBufferCpltCallback != NULL)
01178     {
01179       /* if buffer transfer complete Callback is set enable the corresponding IT*/
01180       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
01181     }
01182
01183     /* Enable the Peripheral */
01184     __HAL_MDMA_ENABLE(hmdma);
01185
01186     if(hmdma->Init.Request == MDMA_REQUEST_SW)
01187     {
01188       /* activate If SW request mode*/
01189       hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
01190     }
01191   }
01192   else
01193   {
01194     /* Process unlocked */
01195     __HAL_UNLOCK(hmdma);
01196
01197     /* Return error status */
01198     return HAL_BUSY;
01199   }
01200
01201   return HAL_OK;
01202 }
01203
01204 /**
01205   * @brief  Aborts the MDMA Transfer.
01206   * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
01207   *                 the configuration information for the specified MDMA Channel.
01208   *
01209   * @note  After disabling a MDMA Channel, a check for wait until the MDMA Channel is
01210   *        effectively disabled is added. If a Channel is disabled
01211   *        while a data transfer is ongoing, the current data will be transferred
01212   *        and the Channel will be effectively disabled only after the transfer of
01213   *        this single data is finished.
01214   * @retval HAL status
01215   */
01216 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
01217 {
01218   uint32_t tickstart =  HAL_GetTick();
01219
01220   /* Check the MDMA peripheral handle */
01221   if(hmdma == NULL)
01222   {
01223     return HAL_ERROR;
01224   }
01225
01226   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01227   {
01228     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01229
01230     /* Process Unlocked */
01231     __HAL_UNLOCK(hmdma);
01232
01233     return HAL_ERROR;
01234   }
01235   else
01236   {
01237     /* Disable all the transfer interrupts */
01238     __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
01239
01240     /* Disable the channel */
01241     __HAL_MDMA_DISABLE(hmdma);
01242
01243     /* Check if the MDMA Channel is effectively disabled */
01244     while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
01245     {
01246       /* Check for the Timeout */
01247       if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
01248       {
01249         /* Update error code */
01250         hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
01251
01252         /* Process Unlocked */
01253         __HAL_UNLOCK(hmdma);
01254
01255         /* Change the MDMA state */
01256         hmdma->State = HAL_MDMA_STATE_ERROR;
01257
01258         return HAL_ERROR;
01259       }
01260     }
01261
01262     /* Clear all interrupt flags */
01263     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
01264
01265     /* Process Unlocked */
01266     __HAL_UNLOCK(hmdma);
01267
01268     /* Change the MDMA state*/
01269     hmdma->State = HAL_MDMA_STATE_READY;
01270   }
01271
01272   return HAL_OK;
01273 }
01274
01275 /**
01276   * @brief  Aborts the MDMA Transfer in Interrupt mode.
01277   * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
01278   *                 the configuration information for the specified MDMA Channel.
01279   * @retval HAL status
01280   */
01281 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
01282 {
01283   /* Check the MDMA peripheral handle */
01284   if(hmdma == NULL)
01285   {
01286     return HAL_ERROR;
01287   }
01288
01289   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01290   {
01291     /* No transfer ongoing */
01292     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01293
01294     return HAL_ERROR;
01295   }
01296   else
01297   {
01298     /* Set Abort State  */
01299     hmdma->State = HAL_MDMA_STATE_ABORT;
01300
01301     /* Disable the stream */
01302     __HAL_MDMA_DISABLE(hmdma);
01303   }
01304
01305   return HAL_OK;
01306 }
01307
01308 /**
01309   * @brief  Polling for transfer complete.
01310   * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
01311   *                        the configuration information for the specified MDMA Channel.
01312   * @param  CompleteLevel: Specifies the MDMA level complete.
01313   * @param  Timeout:       Timeout duration.
01314   * @retval HAL status
01315   */
01316 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
01317 {
01318   uint32_t levelFlag, errorFlag;
01319   uint32_t tickstart;
01320
01321   /* Check the parameters */
01322   assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
01323
01324   /* Check the MDMA peripheral handle */
01325   if(hmdma == NULL)
01326   {
01327     return HAL_ERROR;
01328   }
01329
01330   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01331   {
01332     /* No transfer ongoing */
01333     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01334
01335     return HAL_ERROR;
01336   }
01337
01338   /* Get the level transfer complete flag */
01339   levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER)  ? MDMA_FLAG_CTC  : \
01340                (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
01341                (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   : \
01342                MDMA_FLAG_BRT);
01343
01344
01345   /* Get timeout */
01346   tickstart = HAL_GetTick();
01347
01348   while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
01349   {
01350     if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
01351     {
01352       /* Get the transfer error source flag */
01353       errorFlag = hmdma->Instance->CESR;
01354
01355       if((errorFlag & MDMA_CESR_TED) == 0U)
01356       {
01357         /* Update error code : Read Transfer error  */
01358         hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
01359       }
01360       else
01361       {
01362         /* Update error code : Write Transfer error */
01363         hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
01364       }
01365
01366       if((errorFlag & MDMA_CESR_TEMD) != 0U)
01367       {
01368         /* Update error code : Error Mask Data */
01369         hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
01370       }
01371
01372       if((errorFlag & MDMA_CESR_TELD) != 0U)
01373       {
01374         /* Update error code : Error Linked list */
01375         hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
01376       }
01377
01378       if((errorFlag & MDMA_CESR_ASE) != 0U)
01379       {
01380         /* Update error code : Address/Size alignment error */
01381         hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
01382       }
01383
01384       if((errorFlag & MDMA_CESR_BSE) != 0U)
01385       {
01386         /* Update error code : Block Size error */
01387         hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
01388       }
01389
01390       (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
01391
01392       /*
01393         Note that the Abort function will
01394           - Clear all transfer flags
01395           - Unlock
01396           - Set the State
01397       */
01398
01399       return HAL_ERROR;
01400
01401     }
01402
01403     /* Check for the Timeout */
01404     if(Timeout != HAL_MAX_DELAY)
01405     {
01406       if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
01407       {
01408         /* Update error code */
01409         hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
01410
01411         (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
01412
01413         /*
01414           Note that the Abort function will
01415             - Clear all transfer flags
01416             - Unlock
01417             - Set the State
01418         */
01419
01420         return HAL_ERROR;
01421       }
01422     }
01423   }
01424
01425   /* Clear the transfer level flag */
01426   if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
01427   {
01428     __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
01429
01430   }
01431   else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
01432   {
01433     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
01434
01435   }
01436   else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
01437   {
01438     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
01439   }
01440   else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
01441   {
01442     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
01443
01444     /* Process unlocked */
01445     __HAL_UNLOCK(hmdma);
01446
01447     hmdma->State = HAL_MDMA_STATE_READY;
01448   }
01449   else
01450   {
01451     return HAL_ERROR;
01452   }
01453
01454   return HAL_OK;
01455 }
01456
01457 /**
01458   * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
01459   * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
01460   *                     the configuration information for the specified MDMA Stream.
01461   * @retval HAL status
01462   */
01463 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
01464 {
01465   uint32_t request_mode;
01466
01467   /* Check the MDMA peripheral handle */
01468   if(hmdma == NULL)
01469   {
01470     return HAL_ERROR;
01471   }
01472
01473   /* Get the softawre request mode */
01474   request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
01475
01476   if((hmdma->Instance->CCR &  MDMA_CCR_EN) == 0U)
01477   {
01478     /* if no Transfer on going (MDMA enable bit not set) retrun error */
01479     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01480
01481     return HAL_ERROR;
01482   }
01483   else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
01484   {
01485     /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
01486     hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
01487
01488     return HAL_ERROR;
01489   }
01490   else
01491   {
01492     /* Set the SW request bit to activate the request on the Channel */
01493     hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
01494
01495     return HAL_OK;
01496   }
01497 }
01498
01499 /**
01500   * @brief  Handles MDMA interrupt request.
01501   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
01502   *               the configuration information for the specified MDMA Channel.
01503   * @retval None
01504   */
01505 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
01506 {
01507   __IO uint32_t count = 0;
01508   uint32_t timeout = SystemCoreClock / 9600U;
01509
01510   uint32_t generalIntFlag, errorFlag;
01511
01512   /* General Interrupt Flag management ****************************************/
01513   generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
01514   if((MDMA->GISR0 & generalIntFlag) == 0U)
01515   {
01516     return; /* the  General interrupt flag for the current channel is down , nothing to do */
01517   }
01518
01519   /* Transfer Error Interrupt management ***************************************/
01520   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
01521   {
01522     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
01523     {
01524       /* Disable the transfer error interrupt */
01525       __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
01526
01527       /* Get the transfer error source flag */
01528       errorFlag = hmdma->Instance->CESR;
01529
01530       if((errorFlag & MDMA_CESR_TED) == 0U)
01531       {
01532         /* Update error code : Read Transfer error  */
01533         hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
01534       }
01535       else
01536       {
01537         /* Update error code : Write Transfer error */
01538         hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
01539       }
01540
01541       if((errorFlag & MDMA_CESR_TEMD) != 0U)
01542       {
01543         /* Update error code : Error Mask Data */
01544         hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
01545       }
01546
01547       if((errorFlag & MDMA_CESR_TELD) != 0U)
01548       {
01549         /* Update error code : Error Linked list */
01550         hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
01551       }
01552
01553       if((errorFlag & MDMA_CESR_ASE) != 0U)
01554       {
01555         /* Update error code : Address/Size alignment error */
01556         hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
01557       }
01558
01559       if((errorFlag & MDMA_CESR_BSE) != 0U)
01560       {
01561         /* Update error code : Block Size error error */
01562         hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
01563       }
01564
01565       /* Clear the transfer error flags */
01566       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
01567     }
01568   }
01569
01570   /* Buffer Transfer Complete Interrupt management ******************************/
01571   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
01572   {
01573     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
01574     {
01575       /* Clear the buffer transfer complete flag */
01576       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
01577
01578       if(hmdma->XferBufferCpltCallback != NULL)
01579       {
01580         /* Buffer transfer callback */
01581         hmdma->XferBufferCpltCallback(hmdma);
01582       }
01583     }
01584   }
01585
01586   /* Block Transfer Complete Interrupt management ******************************/
01587   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
01588   {
01589     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
01590     {
01591       /* Clear the block transfer complete flag */
01592       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
01593
01594       if(hmdma->XferBlockCpltCallback != NULL)
01595       {
01596         /* Block transfer callback */
01597         hmdma->XferBlockCpltCallback(hmdma);
01598       }
01599     }
01600   }
01601
01602   /* Repeated Block Transfer Complete Interrupt management ******************************/
01603   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
01604   {
01605     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
01606     {
01607       /* Clear the repeat block transfer complete flag */
01608       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
01609
01610       if(hmdma->XferRepeatBlockCpltCallback != NULL)
01611       {
01612         /* Repeated Block transfer callback */
01613         hmdma->XferRepeatBlockCpltCallback(hmdma);
01614       }
01615     }
01616   }
01617
01618   /* Channel Transfer Complete Interrupt management ***********************************/
01619   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
01620   {
01621     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
01622     {
01623       /* Disable all the transfer interrupts */
01624       __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
01625
01626       if(HAL_MDMA_STATE_ABORT == hmdma->State)
01627       {
01628         /* Process Unlocked */
01629         __HAL_UNLOCK(hmdma);
01630
01631         /* Change the DMA state */
01632         hmdma->State = HAL_MDMA_STATE_READY;
01633
01634         if(hmdma->XferAbortCallback != NULL)
01635         {
01636           hmdma->XferAbortCallback(hmdma);
01637         }
01638         return;
01639       }
01640
01641       /* Clear the Channel Transfer Complete flag */
01642       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
01643
01644       /* Process Unlocked */
01645       __HAL_UNLOCK(hmdma);
01646
01647       /* Change MDMA peripheral state */
01648       hmdma->State = HAL_MDMA_STATE_READY;
01649
01650       if(hmdma->XferCpltCallback != NULL)
01651       {
01652         /* Channel Transfer Complete callback */
01653         hmdma->XferCpltCallback(hmdma);
01654       }
01655     }
01656   }
01657
01658   /* manage error case */
01659   if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
01660   {
01661     hmdma->State = HAL_MDMA_STATE_ABORT;
01662
01663     /* Disable the channel */
01664     __HAL_MDMA_DISABLE(hmdma);
01665
01666     do
01667     {
01668       if (++count > timeout)
01669       {
01670         break;
01671       }
01672     }
01673     while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
01674
01675     /* Process Unlocked */
01676     __HAL_UNLOCK(hmdma);
01677
01678     if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
01679     {
01680       /* Change the MDMA state to error if MDMA disable fails */
01681       hmdma->State = HAL_MDMA_STATE_ERROR;
01682     }
01683     else
01684     {
01685       /* Change the MDMA state to Ready if MDMA disable success */
01686       hmdma->State = HAL_MDMA_STATE_READY;
01687     }
01688
01689
01690     if (hmdma->XferErrorCallback != NULL)
01691     {
01692       /* Transfer error callback */
01693       hmdma->XferErrorCallback(hmdma);
01694     }
01695   }
01696 }
01697
01698 /**
01699   * @}
01700   */
01701
01702 /** @addtogroup MDMA_Exported_Functions_Group4
01703  *
01704 @verbatim
01705  ===============================================================================
01706                     ##### State and Errors functions #####
01707  ===============================================================================
01708     [..]
01709     This subsection provides functions allowing to
01710       (+) Check the MDMA state
01711       (+) Get error code
01712
01713 @endverbatim
01714   * @{
01715   */
01716
01717 /**
01718   * @brief  Returns the MDMA state.
01719   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
01720   *               the configuration information for the specified MDMA Channel.
01721   * @retval HAL state
01722   */
01723 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
01724 {
01725   return hmdma->State;
01726 }
01727
01728 /**
01729   * @brief  Return the MDMA error code
01730   * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
01731   *              the configuration information for the specified MDMA Channel.
01732   * @retval MDMA Error Code
01733   */
01734 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
01735 {
01736   return hmdma->ErrorCode;
01737 }
01738
01739 /**
01740   * @}
01741   */
01742
01743 /**
01744   * @}
01745   */
01746
01747 /** @addtogroup MDMA_Private_Functions
01748   * @{
01749   */
01750
01751 /**
01752   * @brief  Sets the MDMA Transfer parameter.
01753   * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
01754   *                     the configuration information for the specified MDMA Channel.
01755   * @param  SrcAddress: The source memory Buffer address
01756   * @param  DstAddress: The destination memory Buffer address
01757   * @param  BlockDataLength : The length of a block transfer in bytes
01758   * @param  BlockCount: The number of blocks to be transfered
01759   * @retval HAL status
01760   */
01761 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01762 {
01763   uint32_t addressMask;
01764
01765   /* Configure the MDMA Channel data length */
01766   MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
01767
01768   /* Configure the MDMA block repeat count */
01769   MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
01770
01771   /* Clear all interrupt flags */
01772   __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
01773
01774   /* Configure MDMA Channel destination address */
01775   hmdma->Instance->CDAR = DstAddress;
01776
01777   /* Configure MDMA Channel Source address */
01778   hmdma->Instance->CSAR = SrcAddress;
01779
01780   addressMask = SrcAddress & 0xFF000000U;
01781   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
01782   {
01783     /*The AHBSbus is used as source (read operation) on channel x */
01784     hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
01785   }
01786   else
01787   {
01788     /*The AXI bus is used as source (read operation) on channel x */
01789     hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
01790   }
01791
01792   addressMask = DstAddress & 0xFF000000U;
01793   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
01794   {
01795     /*The AHB bus is used as destination (write operation) on channel x */
01796     hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
01797   }
01798   else
01799   {
01800     /*The AXI bus is used as destination (write operation) on channel x */
01801     hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
01802   }
01803
01804   /* Set the linked list register to the first node of the list */
01805   hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
01806 }
01807
01808 /**
01809   * @brief  Initializes the MDMA handle according to the specified
01810   *         parameters in the MDMA_InitTypeDef
01811   * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
01812   *                     the configuration information for the specified MDMA Channel.
01813   * @retval None
01814   */
01815 static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
01816 {
01817   uint32_t blockoffset;
01818
01819   /* Prepare the MDMA Channel configuration */
01820   hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
01821
01822   /* Write new CTCR Register value */
01823   hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
01824                            hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
01825                            hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
01826                            hmdma->Init.DestBurst                                   | \
01827                            ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
01828                            hmdma->Init.TransferTriggerMode;
01829
01830   /* If SW request set the CTCR register to SW Request Mode */
01831   if(hmdma->Init.Request == MDMA_REQUEST_SW)
01832   {
01833     /*
01834     -If the request is done by SW : BWM could be set to 1 or 0.
01835     -If the request is done by a peripheral :
01836     If mask address not set (0) => BWM must be set to 0
01837     If mask address set (different than 0) => BWM could be set to 1 or 0
01838     */
01839     hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
01840   }
01841
01842   /* Reset CBNDTR Register */
01843   hmdma->Instance->CBNDTR = 0;
01844
01845   /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
01846   if(hmdma->Init.SourceBlockAddressOffset < 0)
01847   {
01848     hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
01849     /* Write new CBRUR Register value : source repeat block offset */
01850     blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
01851     hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
01852   }
01853   else
01854   {
01855     /* Write new CBRUR Register value : source repeat block offset */
01856     hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
01857   }
01858
01859   /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
01860   if(hmdma->Init.DestBlockAddressOffset < 0)
01861   {
01862     hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
01863     /* Write new CBRUR Register value : destination repeat block offset */
01864     blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
01865     hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
01866   }
01867   else
01868   {
01869     /*write new CBRUR Register value : destination repeat block offset */
01870     hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
01871   }
01872
01873   /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
01874   if(hmdma->Init.Request != MDMA_REQUEST_SW)
01875   {
01876     /* Set the HW request in CTRB register  */
01877     hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
01878   }
01879   else /* SW request : reset the CTBR register */
01880   {
01881     hmdma->Instance->CTBR = 0;
01882   }
01883
01884   /* Write Link Address Register */
01885   hmdma->Instance->CLAR =  0;
01886 }
01887
01888 /**
01889   * @}
01890   */
01891
01892 #endif /* HAL_MDMA_MODULE_ENABLED */
01893 /**
01894   * @}
01895   */
01896
01897 /**
01898   * @}
01899   */
01900
01901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mdma.h Source File

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stm32h7xx_hal_mdma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_MDMA_H
00022 #define STM32H7xx_HAL_MDMA_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup MDMA
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup MDMA_Exported_Types MDMA Exported Types
00042   * @brief    MDMA Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  MDMA Configuration Structure definition
00048   */
00049 typedef struct
00050 {
00051
00052   uint32_t Request;                 /*!< Specifies the MDMA request.
00053                                         This parameter can be a value of @ref MDMA_Request_selection*/
00054
00055   uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
00056                                          a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
00057                                          This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
00058
00059   uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
00060                                          This parameter can be a value of @ref MDMA_Priority_level */
00061
00062   uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
00063                                          This parameter can be a value of @ref MDMA_Endianness */
00064
00065   uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
00066                                          This parameter can be a value of @ref MDMA_Source_increment_mode */
00067
00068   uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
00069                                          This parameter can be a value of @ref MDMA_Destination_increment_mode */
00070
00071   uint32_t SourceDataSize;           /*!< Specifies the source data size.
00072                                          This parameter can be a value of @ref MDMA_Source_data_size */
00073
00074   uint32_t DestDataSize;             /*!< Specifies the destination data size.
00075                                           This parameter can be a value of @ref MDMA_Destination_data_size */
00076
00077
00078   uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
00079                                             This parameter can be a value of @ref MDMA_data_Alignment */
00080
00081   uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
00082                                           this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
00083
00084   uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
00085                                          It specifies the amount of data to be transferred in a single non interruptable
00086                                          transaction.
00087                                          This parameter can be a value of @ref MDMA_Source_burst
00088                                          @note : the burst may be FIXED/INCR based on SourceInc value ,
00089                                          the BURST must be programmed as to ensure that the burst size will be lower than than
00090                                          BufferTransferLength */
00091
00092   uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
00093                                            It specifies the amount of data to be transferred in a single non interruptable
00094                                            transaction.
00095                                            This parameter can be a value of @ref MDMA_Destination_burst
00096                                            @note : the burst may be FIXED/INCR based on DestinationInc value ,
00097                                            the BURST must be programmed as to ensure that the burst size will be lower than than
00098                                            BufferTransferLength */
00099
00100   int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
00101                                            signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
00102                                                           if < 0 then  decrement the next block source Address by offset from where the last block ends
00103                                                           if == 0, the next block source address starts from where the last block ends
00104                                        */
00105
00106
00107   int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
00108                                            signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
00109                                                           if < 0 then  decrement the next block destination Address by offset from where the last block ends
00110                                                           if == 0, the next block destination address starts from where the last block ends
00111                                        */
00112
00113 }MDMA_InitTypeDef;
00114
00115 /**
00116   * @brief  HAL MDMA linked list node structure definition
00117   * @note   The Linked list node allows to define a new MDMA configuration
00118   *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
00119   *         When CLAR register is configured to a non NULL value , each time a transfer ends,
00120   *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
00121   */
00122 typedef struct
00123 {
00124   __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
00125   __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
00126   __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
00127   __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
00128   __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
00129   __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
00130   __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
00131   __IO uint32_t Reserved; /*!< Reserved register                                                     */
00132   __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
00133   __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
00134
00135 }MDMA_LinkNodeTypeDef;
00136
00137 /**
00138   * @brief  HAL MDMA linked list node configuration structure definition
00139   * @note   used with HAL_MDMA_LinkedList_CreateNode function
00140   */
00141 typedef struct
00142 {
00143   MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
00144   uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
00145   uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
00146   uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
00147   uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
00148
00149   uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
00150                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
00151
00152   uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
00153                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
00154
00155
00156 }MDMA_LinkNodeConfTypeDef;
00157
00158
00159 /**
00160   * @brief  HAL MDMA State structure definition
00161   */
00162 typedef enum
00163 {
00164   HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
00165   HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
00166   HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
00167   HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
00168   HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
00169
00170 }HAL_MDMA_StateTypeDef;
00171
00172 /**
00173   * @brief  HAL MDMA Level Complete structure definition
00174   */
00175 typedef enum
00176 {
00177   HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
00178   HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
00179   HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
00180   HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
00181
00182 }HAL_MDMA_LevelCompleteTypeDef;
00183
00184 /**
00185   * @brief  HAL MDMA Callbacks IDs structure definition
00186   */
00187 typedef enum
00188 {
00189   HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
00190   HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
00191   HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
00192   HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
00193   HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
00194   HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
00195   HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
00196
00197 }HAL_MDMA_CallbackIDTypeDef;
00198
00199
00200 /**
00201   * @brief  MDMA handle Structure definition
00202   */
00203 typedef struct __MDMA_HandleTypeDef
00204 {
00205   MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
00206
00207   MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
00208
00209   HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
00210
00211   __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
00212
00213   void                  *Parent;                                                               /*!< Parent object state                    */
00214
00215   void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
00216
00217   void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
00218
00219   void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
00220
00221   void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
00222
00223   void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
00224
00225   void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
00226
00227
00228   MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
00229                                                                                                      (after the initial node defined by the Init struct)
00230                                                                                                      this parameter is used internally by the MDMA driver
00231                                                                                                      to construct the linked list node
00232                                                                                                 */
00233
00234   MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
00235                                                                                                     this parameter is used internally by the MDMA driver
00236                                                                                                     to construct the linked list node
00237                                                                                                 */
00238   uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
00239
00240   __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
00241
00242 } MDMA_HandleTypeDef;
00243
00244 /**
00245   * @}
00246   */
00247
00248 /* Exported constants --------------------------------------------------------*/
00249
00250 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants
00251   * @brief    MDMA Exported constants
00252   * @{
00253   */
00254
00255 /** @defgroup MDMA_Error_Codes MDMA Error Codes
00256   * @brief    MDMA Error Codes
00257   * @{
00258   */
00259 #define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
00260 #define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
00261 #define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
00262 #define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
00263 #define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
00264 #define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
00265 #define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
00266 #define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
00267 #define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
00268 #define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup MDMA_Request_selection MDMA Request selection
00275   * @brief    MDMA_Request_selection
00276   * @{
00277   */
00278
00279 #define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
00280 #define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
00281 #define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
00282 #define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
00283 #define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
00284 #define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
00285 #define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
00286 #define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
00287 #define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
00288 #define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
00289 #define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
00290 #define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
00291 #define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
00292 #define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
00293 #define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
00294 #define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
00295 #if defined (LTDC)
00296 #define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
00297 #endif /* LTDC */
00298 #if defined (JPEG)
00299 #define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
00300 #define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
00301 #define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
00302 #define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
00303 #define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
00304 #endif /* JPEG */
00305 #if defined (OCTOSPI1)
00306 #define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
00307 #define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
00308 #endif /* OCTOSPI1 */
00309 #if defined (QUADSPI)
00310 #define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
00311 #define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
00312 #endif /* QUADSPI */
00313 #define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
00314 #define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
00315 #define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
00316
00317 #if defined (DSI)
00318 #define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
00319 #define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
00320 #endif /* DSI */
00321
00322 #define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
00323
00324 #define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
00325 #define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
00326
00327 #if defined (OCTOSPI2)
00328 #define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
00329 #define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
00330 #endif /* OCTOSPI2 */
00331
00332 #define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
00333
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
00339   * @brief    MDMA Transfer Trigger Mode
00340   * @{
00341   */
00342 #define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
00343 #define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
00344 #define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
00345 #define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup MDMA_Priority_level MDMA Priority level
00352   * @brief    MDMA Priority level
00353   * @{
00354   */
00355 #define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
00356 #define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
00357 #define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
00358 #define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
00359
00360 /**
00361   * @}
00362   */
00363
00364
00365 /** @defgroup MDMA_Endianness MDMA Endianness
00366   * @brief    MDMA Endianness
00367   * @{
00368   */
00369 #define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
00370 #define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
00371 #define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
00372 #define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
00373
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
00379   * @brief    MDMA Source increment mode
00380   * @{
00381   */
00382 #define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
00383 #define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
00384 #define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
00385 #define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
00386 #define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
00387 #define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
00388 #define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
00389 #define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
00390 #define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
00397   * @brief    MDMA Destination increment mode
00398   * @{
00399   */
00400 #define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
00401 #define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
00402 #define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
00403 #define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
00404 #define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
00405 #define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
00406 #define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
00407 #define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
00408 #define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup MDMA_Source_data_size MDMA Source data size
00415   * @brief    MDMA Source data size
00416   * @{
00417   */
00418 #define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
00419 #define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
00420 #define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
00421 #define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup MDMA_Destination_data_size MDMA Destination data size
00428   * @brief    MDMA Destination data size
00429   * @{
00430   */
00431 #define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
00432 #define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
00433 #define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
00434 #define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
00435
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup MDMA_data_Alignment MDMA data alignment
00441   * @brief    MDMA data alignment
00442   * @{
00443   */
00444 #define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
00445                                                                             All data are right aligned, in Little Endien mode.                                              */
00446 #define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
00447 #define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
00448                                                                             Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
00449 #define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup MDMA_Source_burst MDMA Source burst
00456   * @brief    MDMA Source burst
00457   * @{
00458   */
00459 #define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
00460 #define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
00461 #define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
00462 #define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
00463 #define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
00464 #define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
00465 #define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
00466 #define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
00467
00468 /**
00469   * @}
00470   */
00471
00472 /** @defgroup MDMA_Destination_burst MDMA Destination burst
00473   * @brief    MDMA Destination burst
00474   * @{
00475   */
00476 #define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
00477 #define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
00478 #define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
00479 #define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
00480 #define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
00481 #define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
00482 #define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
00483 #define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
00484
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
00490   * @brief    MDMA interrupt enable definitions
00491   * @{
00492   */
00493 #define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
00494 #define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
00495 #define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
00496 #define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
00497 #define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
00498
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup MDMA_flag_definitions MDMA flag definitions
00504   * @brief    MDMA flag definitions
00505   * @{
00506   */
00507 #define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
00508 #define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
00509 #define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
00510 #define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
00511 #define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
00512 #define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /* Exported macro ------------------------------------------------------------*/
00523
00524 /** @defgroup MDMA_Exported_Macros MDMA Exported Macros
00525   * @{
00526   */
00527
00528 /**
00529   * @brief  Enable the specified MDMA Channel.
00530   * @param  __HANDLE__: MDMA handle
00531   * @retval None
00532   */
00533 #define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
00534
00535 /**
00536   * @brief  Disable the specified MDMA Channel.
00537   * @param  __HANDLE__: MDMA handle
00538   * @retval None
00539   */
00540 #define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
00541
00542 /**
00543   * @brief  Get the MDMA Channel pending flags.
00544   * @param  __HANDLE__: MDMA handle
00545   * @param  __FLAG__: Get the specified flag.
00546   *          This parameter can be any combination of the following values:
00547   *            @arg MDMA_FLAG_TE   : Transfer Error flag.
00548   *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
00549   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
00550   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
00551   *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
00552   *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
00553   * @retval The state of FLAG (SET or RESET).
00554   */
00555 #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
00556
00557 /**
00558   * @brief  Clear the MDMA Stream pending flags.
00559   * @param  __HANDLE__: MDMA handle
00560   * @param  __FLAG__: specifies the flag to clear.
00561   *          This parameter can be any combination of the following values:
00562   *            @arg MDMA_FLAG_TE   : Transfer Error flag.
00563   *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
00564   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
00565   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
00566   *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
00567   * @retval None
00568   */
00569 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
00570
00571 /**
00572   * @brief  Enables the specified MDMA Channel interrupts.
00573   * @param  __HANDLE__: MDMA handle
00574   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00575   *          This parameter can be any combination of the following values:
00576   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00577   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00578   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00579   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00580   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00581   * @retval None
00582   */
00583 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00584
00585 /**
00586   * @brief  Disables the specified MDMA Channel interrupts.
00587   * @param  __HANDLE__: MDMA handle
00588   * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
00589   *          This parameter can be any combination of the following values:
00590   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00591   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00592   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00593   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00594   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00595   * @retval None
00596   */
00597 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00598
00599 /**
00600   * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
00601   * @param  __HANDLE__: DMA handle
00602   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00603   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00604   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00605   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00606   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00607   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00608   * @retval The state of MDMA_IT (SET or RESET).
00609   */
00610 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00611
00612 /**
00613   * @}
00614   */
00615
00616 /* Exported functions --------------------------------------------------------*/
00617 /** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
00618   * @{
00619   */
00620
00621 /* Initialization and de-initialization functions *****************************/
00622 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
00623   * @brief   Initialization and de-initialization functions
00624   * @{
00625   */
00626 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
00627 HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
00628 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
00629
00630 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
00631 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
00632
00633 /**
00634   * @}
00635   */
00636
00637 /* Linked list operation functions ********************************************/
00638 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
00639   * @brief   Linked list operation functions
00640   * @{
00641   */
00642
00643 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
00644 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
00645 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
00646 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
00647 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
00648
00649
00650 /**
00651   * @}
00652   */
00653
00654 /* IO operation functions *****************************************************/
00655 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
00656   * @brief   I/O operation functions
00657   * @{
00658   */
00659 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00660 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00661 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
00662 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
00663 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
00664 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
00665 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
00666
00667 /**
00668   * @}
00669   */
00670
00671 /* Peripheral State and Error functions ***************************************/
00672 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
00673   * @brief    Peripheral State functions
00674   * @{
00675   */
00676 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
00677 uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
00678
00679 /**
00680   * @}
00681   */
00682
00683 /**
00684   * @}
00685   */
00686
00687 /* Private types -------------------------------------------------------------*/
00688 /** @defgroup MDMA_Private_Types MDMA Private Types
00689   * @{
00690   */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /* Private defines -----------------------------------------------------------*/
00697 /** @defgroup MDMA_Private_Defines MDMA Private Defines
00698   * @{
00699   */
00700
00701 /**
00702   * @}
00703   */
00704
00705 /* Private variables ---------------------------------------------------------*/
00706 /** @defgroup MDMA_Private_Variables MDMA Private Variables
00707   * @{
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /* Private constants ---------------------------------------------------------*/
00715 /** @defgroup MDMA_Private_Constants MDMA Private Constants
00716   * @{
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /* Private macros ------------------------------------------------------------*/
00724 /** @defgroup MDMA_Private_Macros MDMA Private Macros
00725   * @{
00726   */
00727
00728 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
00729                                            ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
00730                                            ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
00731                                            ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
00732
00733
00734 #define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
00735                                         ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
00736                                         ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
00737                                         ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
00738
00739 #define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
00740                                                  ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
00741                                                  ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
00742                                                  ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
00743
00744
00745 #if defined (OCTOSPI2)
00746 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
00747 #else
00748 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
00749 #endif /* OCTOSPI2 */
00750
00751 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
00752                                      ((__INC__) == MDMA_SRC_INC_BYTE )      || \
00753                                      ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
00754                                      ((__INC__) == MDMA_SRC_INC_WORD )      || \
00755                                      ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
00756                                      ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
00757                                      ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
00758                                      ((__INC__) == MDMA_SRC_DEC_WORD)       || \
00759                                      ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
00760
00761 #define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
00762                                           ((__INC__) == MDMA_DEST_INC_BYTE )      || \
00763                                           ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
00764                                           ((__INC__) == MDMA_DEST_INC_WORD )      || \
00765                                           ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
00766                                           ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
00767                                           ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
00768                                           ((__INC__) == MDMA_DEST_DEC_WORD)       || \
00769                                           ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
00770
00771 #define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
00772                                            ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
00773                                            ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
00774                                            ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
00775
00776 #define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
00777                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
00778                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
00779                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
00780
00781 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
00782                                                ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
00783                                                ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
00784                                                ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
00785
00786
00787 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
00788                                          ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
00789                                          ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
00790                                          ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
00791                                          ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
00792                                          ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
00793                                          ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
00794                                          ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
00795
00796
00797 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
00798                                               ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
00799                                               ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
00800                                               ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
00801                                               ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
00802                                               ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
00803                                               ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
00804                                               ((__BURST__) == MDMA_DEST_BURST_128BEATS))
00805
00806  #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
00807                                                   ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
00808                                                   ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
00809                                                   ((__MODE__) == MDMA_FULL_TRANSFER))
00810
00811 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
00812
00813 #define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
00814
00815 #define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
00816
00817 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
00818
00819 /**
00820   * @}
00821   */
00822
00823 /* Private functions prototypes ----------------------------------------------*/
00824 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
00825   * @{
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 /* Private functions ---------------------------------------------------------*/
00833 /** @defgroup MDMA_Private_Functions MDMA Private Functions
00834   * @{
00835   */
00836
00837 /**
00838   * @}
00839   */
00840
00841 /**
00842   * @}
00843   */
00844
00845 /**
00846   * @}
00847   */
00848
00849 #ifdef __cplusplus
00850 }
00851 #endif
00852
00853 #endif /* STM32H7xx_HAL_MDMA_H */
00854
00855 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc.c Source File

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stm32h7xx_hal_mmc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc.c
00004   * @author  MCD Application Team
00005   * @brief   MMC card HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Secure Digital (MMC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + MMC card Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     This driver implements a high level communication layer for read and write from/to
00019     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
00020     the user in HAL_MMC_MspInit() function (MSP layer).
00021     Basically, the MSP layer configuration should be the same as we provide in the
00022     examples.
00023     You can easily tailor this configuration according to hardware resources.
00024
00025   [..]
00026     This driver is a generic layered driver for SDMMC memories which uses the HAL
00027     SDMMC driver functions to interface with MMC and eMMC cards devices.
00028     It is used as follows:
00029
00030     (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
00031         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
00032         (##) SDMMC pins configuration for MMC card
00033             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00034             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00035                   and according to your pin assignment;
00036         (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
00037              and HAL_MMC_WriteBlocks_IT() APIs).
00038             (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
00039             (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00040             (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
00041                   and __HAL_MMC_DISABLE_IT() inside the communication process.
00042             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
00043                   and __HAL_MMC_CLEAR_IT()
00044         (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
00045
00046     (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
00047
00048
00049   *** MMC Card Initialization and configuration ***
00050   ================================================
00051   [..]
00052     To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
00053     SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
00054     This function provide the following operations:
00055
00056     (#) Initialize the SDMMC peripheral interface with defaullt configuration.
00057         The initialization process is done at 400KHz. You can change or adapt
00058         this frequency by adjusting the "ClockDiv" field.
00059         The MMC Card frequency (SDMMC_CK) is computed as follows:
00060
00061            SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
00062
00063         In initialization mode and according to the MMC Card standard,
00064         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00065
00066         This phase of initialization is done through SDMMC_Init() and
00067         SDMMC_PowerState_ON() SDMMC low level APIs.
00068
00069     (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
00070         This phase allows the card initialization and identification
00071         and check the MMC Card type (Standard Capacity or High Capacity)
00072         The initialization flow is compatible with MMC standard.
00073
00074         This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
00075         of plug-off plug-in.
00076
00077     (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
00078         frequency by adjusting the "ClockDiv" field.
00079         In transfer mode and according to the MMC Card standard, make sure that the
00080         SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
00081
00082     (#) Select the corresponding MMC Card according to the address read with the step 2.
00083
00084     (#) Configure the MMC Card in wide bus mode: 4-bits data.
00085
00086   *** MMC Card Read operation ***
00087   ==============================
00088   [..]
00089     (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
00090         This function support only 512-bytes block length (the block size should be
00091         chosen as 512 bytes).
00092         You can choose either one block read operation or multiple block read operation
00093         by adjusting the "NumberOfBlocks" parameter.
00094         After this, you have to ensure that the transfer is done correctly. The check is done
00095         through HAL_MMC_GetCardState() function for MMC card state.
00096
00097     (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
00098         This function support only 512-bytes block length (the block size should be
00099         chosen as 512 bytes).
00100         You can choose either one block read operation or multiple block read operation
00101         by adjusting the "NumberOfBlocks" parameter.
00102         After this, you have to ensure that the transfer is done correctly. The check is done
00103         through HAL_MMC_GetCardState() function for MMC card state.
00104         You could also check the DMA transfer process through the MMC Rx interrupt event.
00105
00106     (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
00107         This function allows the read of 512 bytes blocks.
00108         You can choose either one block read operation or multiple block read operation
00109         by adjusting the "NumberOfBlocks" parameter.
00110         After this, you have to ensure that the transfer is done correctly. The check is done
00111         through HAL_MMC_GetCardState() function for MMC card state.
00112         You could also check the IT transfer process through the MMC Rx interrupt event.
00113
00114   *** MMC Card Write operation ***
00115   ===============================
00116   [..]
00117     (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
00118         This function support only 512-bytes block length (the block size should be
00119         chosen as 512 bytes).
00120         You can choose either one block read operation or multiple block read operation
00121         by adjusting the "NumberOfBlocks" parameter.
00122         After this, you have to ensure that the transfer is done correctly. The check is done
00123         through HAL_MMC_GetCardState() function for MMC card state.
00124
00125     (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
00126         This function support only 512-bytes block length (the block size should be
00127         chosen as 512 byte).
00128         You can choose either one block read operation or multiple block read operation
00129         by adjusting the "NumberOfBlocks" parameter.
00130         After this, you have to ensure that the transfer is done correctly. The check is done
00131         through HAL_MMC_GetCardState() function for MMC card state.
00132         You could also check the DMA transfer process through the MMC Tx interrupt event.
00133
00134     (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
00135         This function allows the read of 512 bytes blocks.
00136         You can choose either one block read operation or multiple block read operation
00137         by adjusting the "NumberOfBlocks" parameter.
00138         After this, you have to ensure that the transfer is done correctly. The check is done
00139         through HAL_MMC_GetCardState() function for MMC card state.
00140         You could also check the IT transfer process through the MMC Tx interrupt event.
00141
00142   *** MMC card information ***
00143   ===========================
00144   [..]
00145     (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
00146         It returns useful information about the MMC card such as block size, card type,
00147         block number ...
00148
00149   *** MMC card CSD register ***
00150   ============================
00151   [..]
00152     (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
00153         Some of the CSD parameters are useful for card initialization and identification.
00154
00155   *** MMC card CID register ***
00156   ============================
00157   [..]
00158     (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
00159         Some of the CID parameters are useful for card initialization and identification.
00160
00161   *** MMC HAL driver macros list ***
00162   ==================================
00163   [..]
00164     Below the list of most used macros in MMC HAL driver.
00165
00166     (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
00167     (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
00168     (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
00169     (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
00170
00171   [..]
00172     (@) You can refer to the MMC HAL driver header file for more useful macros
00173
00174   *** Callback registration ***
00175   =============================================
00176   [..]
00177     The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
00178     allows the user to configure dynamically the driver callbacks.
00179
00180     Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
00181     it allows to register following callbacks:
00182       (+) TxCpltCallback : callback when a transmission transfer is completed.
00183       (+) RxCpltCallback : callback when a reception transfer is completed.
00184       (+) ErrorCallback : callback when error occurs.
00185       (+) AbortCpltCallback : callback when abort is completed.
00186       (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
00187       (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
00188       (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
00189       (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
00190       (+) MspInitCallback    : MMC MspInit.
00191       (+) MspDeInitCallback  : MMC MspDeInit.
00192     This function takes as parameters the HAL peripheral handle, the Callback ID
00193     and a pointer to the user callback function.
00194
00195     Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
00196     weak (surcharged) function. It allows to reset following callbacks:
00197       (+) TxCpltCallback : callback when a transmission transfer is completed.
00198       (+) RxCpltCallback : callback when a reception transfer is completed.
00199       (+) ErrorCallback : callback when error occurs.
00200       (+) AbortCpltCallback : callback when abort is completed.
00201       (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
00202       (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
00203       (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
00204       (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
00205       (+) MspInitCallback    : MMC MspInit.
00206       (+) MspDeInitCallback  : MMC MspDeInit.
00207     This function) takes as parameters the HAL peripheral handle and the Callback ID.
00208
00209     By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
00210     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00211     Exception done for MspInit and MspDeInit callbacks that are respectively
00212     reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
00213     and @ref  HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
00214     If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
00215     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00216
00217     Callbacks can be registered/unregistered in READY state only.
00218     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00219     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00220     during the Init/DeInit.
00221     In that case first register the MspInit/MspDeInit user callbacks
00222     using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
00223     or @ref HAL_MMC_Init function.
00224
00225     When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
00226     not defined, the callback registering feature is not available
00227     and weak (surcharged) callbacks are used.
00228
00229   @endverbatim
00230   ******************************************************************************
00231   * @attention
00232   *
00233   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00234   * All rights reserved.</center></h2>
00235   *
00236   * This software component is licensed by ST under BSD 3-Clause license,
00237   * the "License"; You may not use this file except in compliance with the
00238   * License. You may obtain a copy of the License at:
00239   *                       opensource.org/licenses/BSD-3-Clause
00240   *
00241   ******************************************************************************
00242   */
00243
00244 /* Includes ------------------------------------------------------------------*/
00245 #include "stm32h7xx_hal.h"
00246
00247 /** @addtogroup STM32H7xx_HAL_Driver
00248   * @{
00249   */
00250
00251 /** @defgroup MMC MMC
00252   * @brief MMC HAL module driver
00253   * @{
00254   */
00255
00256 #ifdef HAL_MMC_MODULE_ENABLED
00257
00258 /* Private typedef -----------------------------------------------------------*/
00259 /* Private define ------------------------------------------------------------*/
00260 /** @addtogroup MMC_Private_Defines
00261   * @{
00262   */
00263
00264 /**
00265   * @}
00266   */
00267
00268 /* Private macro -------------------------------------------------------------*/
00269 /* Private variables ---------------------------------------------------------*/
00270 /* Private function prototypes -----------------------------------------------*/
00271 /* Private functions ---------------------------------------------------------*/
00272 /** @defgroup MMC_Private_Functions MMC Private Functions
00273   * @{
00274   */
00275 static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
00276 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
00277 static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
00278 static void     MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
00279 static void     MMC_Write_IT(MMC_HandleTypeDef *hmmc);
00280 static void     MMC_Read_IT(MMC_HandleTypeDef *hmmc);
00281 static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
00282 static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
00283 HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
00284
00285
00286 /**
00287   * @}
00288   */
00289 /* Exported functions --------------------------------------------------------*/
00290 /** @addtogroup MMC_Exported_Functions
00291   * @{
00292   */
00293
00294 /** @addtogroup MMC_Exported_Functions_Group1
00295  *  @brief   Initialization and de-initialization functions
00296  *
00297 @verbatim
00298   ==============================================================================
00299           ##### Initialization and de-initialization functions #####
00300   ==============================================================================
00301   [..]
00302     This section provides functions allowing to initialize/de-initialize the MMC
00303     card device to be ready for use.
00304
00305 @endverbatim
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Initializes the MMC according to the specified parameters in the
00311             MMC_HandleTypeDef and create the associated handle.
00312   * @param  hmmc: Pointer to the MMC handle
00313   * @retval HAL status
00314   */
00315 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
00316 {
00317   /* Check the MMC handle allocation */
00318   if(hmmc == NULL)
00319   {
00320     return HAL_ERROR;
00321   }
00322
00323   /* Check the parameters */
00324   assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
00325   assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
00326   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
00327   assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
00328   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
00329   assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
00330
00331   if(hmmc->State == HAL_MMC_STATE_RESET)
00332   {
00333     /* Allocate lock resource and initialize it */
00334     hmmc->Lock = HAL_UNLOCKED;
00335 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00336     /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
00337     hmmc->TxCpltCallback    = HAL_MMC_TxCpltCallback;
00338     hmmc->RxCpltCallback    = HAL_MMC_RxCpltCallback;
00339     hmmc->ErrorCallback     = HAL_MMC_ErrorCallback;
00340     hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
00341     hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback;
00342     hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback;
00343     hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback;
00344     hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback;
00345
00346     if(hmmc->MspInitCallback == NULL)
00347     {
00348       hmmc->MspInitCallback = HAL_MMC_MspInit;
00349     }
00350
00351     /* Init the low level hardware */
00352     hmmc->MspInitCallback(hmmc);
00353 #else
00354     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00355     HAL_MMC_MspInit(hmmc);
00356 #endif
00357   }
00358
00359   hmmc->State = HAL_MMC_STATE_BUSY;
00360
00361   /* Initialize the Card parameters */
00362   if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
00363   {
00364     return HAL_ERROR;
00365   }
00366
00367   /* Initialize the error code */
00368   hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00369
00370   /* Initialize the MMC operation */
00371   hmmc->Context = MMC_CONTEXT_NONE;
00372
00373   /* Initialize the MMC state */
00374   hmmc->State = HAL_MMC_STATE_READY;
00375
00376   return HAL_OK;
00377 }
00378
00379 /**
00380   * @brief  Initializes the MMC Card.
00381   * @param  hmmc: Pointer to MMC handle
00382   * @note   This function initializes the MMC card. It could be used when a card
00383             re-initialization is needed.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
00387 {
00388   uint32_t errorstate;
00389   MMC_InitTypeDef Init;
00390   HAL_StatusTypeDef status;
00391
00392   /* Default SDMMC peripheral configuration for MMC card initialization */
00393   Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00394   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00395   Init.BusWide             = SDMMC_BUS_WIDE_1B;
00396   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00397   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
00398
00399   /* Initialize SDMMC peripheral interface with default configuration */
00400   status = SDMMC_Init(hmmc->Instance, Init);
00401   if(status == HAL_ERROR)
00402   {
00403     return HAL_ERROR;
00404   }
00405
00406   /* Set Power State to ON */
00407   status = SDMMC_PowerState_ON(hmmc->Instance);
00408   if(status == HAL_ERROR)
00409   {
00410     return HAL_ERROR;
00411   }
00412
00413   /* Identify card operating voltage */
00414   errorstate = MMC_PowerON(hmmc);
00415   if(errorstate != HAL_MMC_ERROR_NONE)
00416   {
00417     hmmc->State = HAL_MMC_STATE_READY;
00418     hmmc->ErrorCode |= errorstate;
00419     return HAL_ERROR;
00420   }
00421
00422   /* Card initialization */
00423   errorstate = MMC_InitCard(hmmc);
00424   if(errorstate != HAL_MMC_ERROR_NONE)
00425   {
00426     hmmc->State = HAL_MMC_STATE_READY;
00427     hmmc->ErrorCode |= errorstate;
00428     return HAL_ERROR;
00429   }
00430
00431   return HAL_OK;
00432 }
00433
00434 /**
00435   * @brief  De-Initializes the MMC card.
00436   * @param  hmmc: Pointer to MMC handle
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
00440 {
00441   /* Check the MMC handle allocation */
00442   if(hmmc == NULL)
00443   {
00444     return HAL_ERROR;
00445   }
00446
00447   /* Check the parameters */
00448   assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
00449
00450   hmmc->State = HAL_MMC_STATE_BUSY;
00451
00452   /* Set MMC power state to off */
00453   MMC_PowerOFF(hmmc);
00454
00455 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00456   if(hmmc->MspDeInitCallback == NULL)
00457   {
00458     hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
00459   }
00460
00461   /* DeInit the low level hardware */
00462   hmmc->MspDeInitCallback(hmmc);
00463 #else
00464   /* De-Initialize the MSP layer */
00465   HAL_MMC_MspDeInit(hmmc);
00466 #endif
00467
00468   hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00469   hmmc->State = HAL_MMC_STATE_RESET;
00470
00471   return HAL_OK;
00472 }
00473
00474
00475 /**
00476   * @brief  Initializes the MMC MSP.
00477   * @param  hmmc: Pointer to MMC handle
00478   * @retval None
00479   */
00480 __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
00481 {
00482   /* Prevent unused argument(s) compilation warning */
00483   UNUSED(hmmc);
00484
00485   /* NOTE : This function Should not be modified, when the callback is needed,
00486             the HAL_MMC_MspInit could be implemented in the user file
00487    */
00488 }
00489
00490 /**
00491   * @brief  De-Initialize MMC MSP.
00492   * @param  hmmc: Pointer to MMC handle
00493   * @retval None
00494   */
00495 __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
00496 {
00497   /* Prevent unused argument(s) compilation warning */
00498   UNUSED(hmmc);
00499
00500   /* NOTE : This function Should not be modified, when the callback is needed,
00501             the HAL_MMC_MspDeInit could be implemented in the user file
00502    */
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 /** @addtogroup MMC_Exported_Functions_Group2
00510  *  @brief   Data transfer functions
00511  *
00512 @verbatim
00513   ==============================================================================
00514                         ##### IO operation functions #####
00515   ==============================================================================
00516   [..]
00517     This subsection provides a set of functions allowing to manage the data
00518     transfer from/to MMC card.
00519
00520 @endverbatim
00521   * @{
00522   */
00523
00524 /**
00525   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00526   *         is managed by polling mode.
00527   * @note   This API should be followed by a check on the card state through
00528   *         HAL_MMC_GetCardState().
00529   * @param  hmmc: Pointer to MMC handle
00530   * @param  pData: pointer to the buffer that will contain the received data
00531   * @param  BlockAdd: Block Address from where data is to be read
00532   * @param  NumberOfBlocks: Number of MMC blocks to read
00533   * @param  Timeout: Specify timeout value
00534   * @retval HAL status
00535   */
00536 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00537 {
00538   SDMMC_DataInitTypeDef config;
00539   uint32_t errorstate;
00540   uint32_t tickstart = HAL_GetTick();
00541   uint32_t count, data, dataremaining;
00542   uint32_t add = BlockAdd;
00543   uint8_t *tempbuff = pData;
00544
00545   if(NULL == pData)
00546   {
00547     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00548     return HAL_ERROR;
00549   }
00550
00551   if(hmmc->State == HAL_MMC_STATE_READY)
00552   {
00553     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00554
00555     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00556     {
00557       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00558       return HAL_ERROR;
00559     }
00560
00561     hmmc->State = HAL_MMC_STATE_BUSY;
00562
00563     /* Initialize data control register */
00564     hmmc->Instance->DCTRL = 0U;
00565
00566     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00567     {
00568       add *= 512U;
00569     }
00570
00571     /* Set Block Size for Card */
00572     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
00573     if(errorstate != HAL_MMC_ERROR_NONE)
00574     {
00575       /* Clear all the static flags */
00576       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00577       hmmc->ErrorCode |= errorstate;
00578       hmmc->State = HAL_MMC_STATE_READY;
00579       return HAL_ERROR;
00580     }
00581
00582     /* Configure the MMC DPSM (Data Path State Machine) */
00583     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00584     config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
00585     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00586     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00587     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00588     config.DPSM          = SDMMC_DPSM_DISABLE;
00589     (void)SDMMC_ConfigData(hmmc->Instance, &config);
00590     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00591
00592     /* Read block(s) in polling mode */
00593     if(NumberOfBlocks > 1U)
00594     {
00595       hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
00596
00597       /* Read Multi Block command */
00598       errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
00599     }
00600     else
00601     {
00602       hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
00603
00604       /* Read Single Block command */
00605       errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
00606     }
00607     if(errorstate != HAL_MMC_ERROR_NONE)
00608     {
00609       /* Clear all the static flags */
00610       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00611       hmmc->ErrorCode |= errorstate;
00612       hmmc->State = HAL_MMC_STATE_READY;
00613       return HAL_ERROR;
00614     }
00615
00616     /* Poll on SDMMC flags */
00617     dataremaining = config.DataLength;
00618     while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00619     {
00620       if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
00621       {
00622         /* Read data from SDMMC Rx FIFO */
00623         for(count = 0U; count < 8U; count++)
00624         {
00625           data = SDMMC_ReadFIFO(hmmc->Instance);
00626           *tempbuff = (uint8_t)(data & 0xFFU);
00627           tempbuff++;
00628           *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
00629           tempbuff++;
00630           *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
00631           tempbuff++;
00632           *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
00633           tempbuff++;
00634         }
00635         dataremaining -= 32U;
00636       }
00637
00638       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
00639       {
00640         /* Clear all the static flags */
00641         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00642         hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
00643         hmmc->State= HAL_MMC_STATE_READY;
00644         return HAL_TIMEOUT;
00645       }
00646     }
00647     __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
00648
00649     /* Send stop transmission command in case of multiblock read */
00650     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00651     {
00652       /* Send stop transmission command */
00653       errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
00654       if(errorstate != HAL_MMC_ERROR_NONE)
00655       {
00656         /* Clear all the static flags */
00657         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00658         hmmc->ErrorCode |= errorstate;
00659         hmmc->State = HAL_MMC_STATE_READY;
00660         return HAL_ERROR;
00661       }
00662     }
00663
00664     /* Get error state */
00665     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
00666     {
00667       /* Clear all the static flags */
00668       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00669       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
00670       hmmc->State = HAL_MMC_STATE_READY;
00671       return HAL_ERROR;
00672     }
00673     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
00674     {
00675       /* Clear all the static flags */
00676       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00677       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
00678       hmmc->State = HAL_MMC_STATE_READY;
00679       return HAL_ERROR;
00680     }
00681     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
00682     {
00683       /* Clear all the static flags */
00684       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00685       hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
00686       hmmc->State = HAL_MMC_STATE_READY;
00687       return HAL_ERROR;
00688     }
00689     else
00690     {
00691       /* Nothing to do */
00692     }
00693
00694     /* Clear all the static flags */
00695     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
00696
00697     hmmc->State = HAL_MMC_STATE_READY;
00698
00699     return HAL_OK;
00700   }
00701   else
00702   {
00703     hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
00704     return HAL_ERROR;
00705   }
00706 }
00707
00708 /**
00709   * @brief  Allows to write block(s) to a specified address in a card. The Data
00710   *         transfer is managed by polling mode.
00711   * @note   This API should be followed by a check on the card state through
00712   *         HAL_MMC_GetCardState().
00713   * @param  hmmc: Pointer to MMC handle
00714   * @param  pData: pointer to the buffer that will contain the data to transmit
00715   * @param  BlockAdd: Block Address where data will be written
00716   * @param  NumberOfBlocks: Number of MMC blocks to write
00717   * @param  Timeout: Specify timeout value
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00721 {
00722   SDMMC_DataInitTypeDef config;
00723   uint32_t errorstate;
00724   uint32_t tickstart = HAL_GetTick();
00725   uint32_t count, data, dataremaining;
00726   uint32_t add = BlockAdd;
00727   uint8_t *tempbuff = pData;
00728
00729   if(NULL == pData)
00730   {
00731     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00732     return HAL_ERROR;
00733   }
00734
00735   if(hmmc->State == HAL_MMC_STATE_READY)
00736   {
00737     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00738
00739     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00740     {
00741       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00742       return HAL_ERROR;
00743     }
00744
00745     hmmc->State = HAL_MMC_STATE_BUSY;
00746
00747     /* Initialize data control register */
00748     hmmc->Instance->DCTRL = 0U;
00749
00750     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00751     {
00752       add *= 512U;
00753     }
00754
00755     /* Set Block Size for Card */
00756     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
00757     if(errorstate != HAL_MMC_ERROR_NONE)
00758     {
00759       /* Clear all the static flags */
00760       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00761       hmmc->ErrorCode |= errorstate;
00762       hmmc->State = HAL_MMC_STATE_READY;
00763       return HAL_ERROR;
00764     }
00765
00766     /* Configure the MMC DPSM (Data Path State Machine) */
00767     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00768     config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
00769     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00770     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00771     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00772     config.DPSM          = SDMMC_DPSM_DISABLE;
00773     (void)SDMMC_ConfigData(hmmc->Instance, &config);
00774     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00775
00776     /* Write Blocks in Polling mode */
00777     if(NumberOfBlocks > 1U)
00778     {
00779       hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
00780
00781       /* Write Multi Block command */
00782       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
00783     }
00784     else
00785     {
00786       hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
00787
00788       /* Write Single Block command */
00789       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
00790     }
00791     if(errorstate != HAL_MMC_ERROR_NONE)
00792     {
00793       /* Clear all the static flags */
00794       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00795       hmmc->ErrorCode |= errorstate;
00796       hmmc->State = HAL_MMC_STATE_READY;
00797       return HAL_ERROR;
00798     }
00799
00800     /* Write block(s) in polling mode */
00801     dataremaining = config.DataLength;
00802     while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00803     {
00804       if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
00805       {
00806         /* Write data to SDMMC Tx FIFO */
00807         for(count = 0U; count < 8U; count++)
00808         {
00809           data = (uint32_t)(*tempbuff);
00810           tempbuff++;
00811           data |= ((uint32_t)(*tempbuff) << 8U);
00812           tempbuff++;
00813           data |= ((uint32_t)(*tempbuff) << 16U);
00814           tempbuff++;
00815           data |= ((uint32_t)(*tempbuff) << 24U);
00816           tempbuff++;
00817           (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
00818         }
00819         dataremaining -= 32U;
00820       }
00821
00822       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
00823       {
00824         /* Clear all the static flags */
00825         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00826         hmmc->ErrorCode |= errorstate;
00827         hmmc->State = HAL_MMC_STATE_READY;
00828         return HAL_TIMEOUT;
00829       }
00830     }
00831     __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
00832
00833     /* Send stop transmission command in case of multiblock write */
00834     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00835     {
00836       /* Send stop transmission command */
00837       errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
00838       if(errorstate != HAL_MMC_ERROR_NONE)
00839       {
00840         /* Clear all the static flags */
00841         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00842         hmmc->ErrorCode |= errorstate;
00843         hmmc->State = HAL_MMC_STATE_READY;
00844         return HAL_ERROR;
00845       }
00846     }
00847
00848     /* Get error state */
00849     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
00850     {
00851       /* Clear all the static flags */
00852       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00853       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
00854       hmmc->State = HAL_MMC_STATE_READY;
00855       return HAL_ERROR;
00856     }
00857     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
00858     {
00859       /* Clear all the static flags */
00860       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00861       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
00862       hmmc->State = HAL_MMC_STATE_READY;
00863       return HAL_ERROR;
00864     }
00865     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
00866     {
00867       /* Clear all the static flags */
00868       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00869       hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
00870       hmmc->State = HAL_MMC_STATE_READY;
00871       return HAL_ERROR;
00872     }
00873     else
00874     {
00875       /* Nothing to do */
00876     }
00877
00878     /* Clear all the static flags */
00879     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
00880
00881     hmmc->State = HAL_MMC_STATE_READY;
00882
00883     return HAL_OK;
00884   }
00885   else
00886   {
00887     hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
00888     return HAL_ERROR;
00889   }
00890 }
00891
00892 /**
00893   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00894   *         is managed in interrupt mode.
00895   * @note   This API should be followed by a check on the card state through
00896   *         HAL_MMC_GetCardState().
00897   * @note   You could also check the IT transfer process through the MMC Rx
00898   *         interrupt event.
00899   * @param  hmmc: Pointer to MMC handle
00900   * @param  pData: Pointer to the buffer that will contain the received data
00901   * @param  BlockAdd: Block Address from where data is to be read
00902   * @param  NumberOfBlocks: Number of blocks to read.
00903   * @retval HAL status
00904   */
00905 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00906 {
00907   SDMMC_DataInitTypeDef config;
00908   uint32_t errorstate;
00909   uint32_t add = BlockAdd;
00910
00911   if(NULL == pData)
00912   {
00913     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00914     return HAL_ERROR;
00915   }
00916
00917   if(hmmc->State == HAL_MMC_STATE_READY)
00918   {
00919     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00920
00921     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00922     {
00923       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00924       return HAL_ERROR;
00925     }
00926
00927     hmmc->State = HAL_MMC_STATE_BUSY;
00928
00929     /* Initialize data control register */
00930     hmmc->Instance->DCTRL = 0U;
00931
00932     hmmc->pRxBuffPtr = pData;
00933     hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
00934
00935     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
00936
00937     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00938     {
00939       add *= 512U;
00940     }
00941
00942     /* Set Block Size for Card */
00943     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
00944     if(errorstate != HAL_MMC_ERROR_NONE)
00945     {
00946       /* Clear all the static flags */
00947       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00948       hmmc->ErrorCode |= errorstate;
00949       hmmc->State = HAL_MMC_STATE_READY;
00950       return HAL_ERROR;
00951     }
00952
00953     /* Configure the MMC DPSM (Data Path State Machine) */
00954     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00955     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
00956     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00957     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00958     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00959     config.DPSM          = SDMMC_DPSM_DISABLE;
00960     (void)SDMMC_ConfigData(hmmc->Instance, &config);
00961     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00962
00963     /* Read Blocks in IT mode */
00964     if(NumberOfBlocks > 1U)
00965     {
00966       hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
00967
00968       /* Read Multi Block command */
00969       errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
00970     }
00971     else
00972     {
00973       hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
00974
00975       /* Read Single Block command */
00976       errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
00977     }
00978
00979     if(errorstate != HAL_MMC_ERROR_NONE)
00980     {
00981       /* Clear all the static flags */
00982       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00983       hmmc->ErrorCode |= errorstate;
00984       hmmc->State = HAL_MMC_STATE_READY;
00985       return HAL_ERROR;
00986     }
00987
00988     return HAL_OK;
00989   }
00990   else
00991   {
00992     return HAL_BUSY;
00993   }
00994 }
00995
00996 /**
00997   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00998   *         is managed in interrupt mode.
00999   * @note   This API should be followed by a check on the card state through
01000   *         HAL_MMC_GetCardState().
01001   * @note   You could also check the IT transfer process through the MMC Tx
01002   *         interrupt event.
01003   * @param  hmmc: Pointer to MMC handle
01004   * @param  pData: Pointer to the buffer that will contain the data to transmit
01005   * @param  BlockAdd: Block Address where data will be written
01006   * @param  NumberOfBlocks: Number of blocks to write
01007   * @retval HAL status
01008   */
01009 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01010 {
01011   SDMMC_DataInitTypeDef config;
01012   uint32_t errorstate;
01013   uint32_t add = BlockAdd;
01014
01015   if(NULL == pData)
01016   {
01017     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01018     return HAL_ERROR;
01019   }
01020
01021   if(hmmc->State == HAL_MMC_STATE_READY)
01022   {
01023     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
01024
01025     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
01026     {
01027       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01028       return HAL_ERROR;
01029     }
01030
01031     hmmc->State = HAL_MMC_STATE_BUSY;
01032
01033     /* Initialize data control register */
01034     hmmc->Instance->DCTRL = 0U;
01035
01036     hmmc->pTxBuffPtr = pData;
01037     hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
01038
01039     /* Enable transfer interrupts */
01040     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
01041
01042     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01043     {
01044       add *= 512U;
01045     }
01046
01047     /* Set Block Size for Card */
01048     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
01049     if(errorstate != HAL_MMC_ERROR_NONE)
01050     {
01051       /* Clear all the static flags */
01052       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01053       hmmc->ErrorCode |= errorstate;
01054       hmmc->State = HAL_MMC_STATE_READY;
01055       return HAL_ERROR;
01056     }
01057
01058     /* Configure the MMC DPSM (Data Path State Machine) */
01059     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01060     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
01061     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01062     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01063     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01064     config.DPSM          = SDMMC_DPSM_DISABLE;
01065     (void)SDMMC_ConfigData(hmmc->Instance, &config);
01066
01067     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
01068
01069     /* Write Blocks in Polling mode */
01070     if(NumberOfBlocks > 1U)
01071     {
01072       hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
01073
01074       /* Write Multi Block command */
01075       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
01076     }
01077     else
01078     {
01079       hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
01080
01081       /* Write Single Block command */
01082       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
01083     }
01084     if(errorstate != HAL_MMC_ERROR_NONE)
01085     {
01086       /* Clear all the static flags */
01087       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01088       hmmc->ErrorCode |= errorstate;
01089       hmmc->State = HAL_MMC_STATE_READY;
01090       return HAL_ERROR;
01091     }
01092
01093     return HAL_OK;
01094   }
01095   else
01096   {
01097     return HAL_BUSY;
01098   }
01099 }
01100
01101 /**
01102   * @brief  Reads block(s) from a specified address in a card. The Data transfer
01103   *         is managed by DMA mode.
01104   * @note   This API should be followed by a check on the card state through
01105   *         HAL_MMC_GetCardState().
01106   * @note   You could also check the DMA transfer process through the MMC Rx
01107   *         interrupt event.
01108   * @param  hmmc: Pointer MMC handle
01109   * @param  pData: Pointer to the buffer that will contain the received data
01110   * @param  BlockAdd: Block Address from where data is to be read
01111   * @param  NumberOfBlocks: Number of blocks to read.
01112   * @retval HAL status
01113   */
01114 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01115 {
01116   SDMMC_DataInitTypeDef config;
01117   uint32_t errorstate;
01118   uint32_t add = BlockAdd;
01119
01120   if(NULL == pData)
01121   {
01122     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01123     return HAL_ERROR;
01124   }
01125
01126   if(hmmc->State == HAL_MMC_STATE_READY)
01127   {
01128     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
01129
01130     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
01131     {
01132       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01133       return HAL_ERROR;
01134     }
01135
01136     hmmc->State = HAL_MMC_STATE_BUSY;
01137
01138     /* Initialize data control register */
01139     hmmc->Instance->DCTRL = 0U;
01140
01141     hmmc->pRxBuffPtr = pData;
01142     hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
01143
01144     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01145     {
01146       add *= 512U;
01147     }
01148
01149     /* Set Block Size for Card */
01150     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
01151     if(errorstate != HAL_MMC_ERROR_NONE)
01152     {
01153       /* Clear all the static flags */
01154       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01155       hmmc->ErrorCode = errorstate;
01156       hmmc->State = HAL_MMC_STATE_READY;
01157       return HAL_ERROR;
01158     }
01159
01160     /* Configure the MMC DPSM (Data Path State Machine) */
01161     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01162     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
01163     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01164     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01165     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01166     config.DPSM          = SDMMC_DPSM_DISABLE;
01167     (void)SDMMC_ConfigData(hmmc->Instance, &config);
01168
01169     /* Enable transfer interrupts */
01170     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01171
01172     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
01173     hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
01174     hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01175
01176     /* Read Blocks in DMA mode */
01177     if(NumberOfBlocks > 1U)
01178     {
01179       hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
01180
01181       /* Read Multi Block command */
01182       errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
01183     }
01184     else
01185     {
01186       hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
01187
01188       /* Read Single Block command */
01189       errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
01190     }
01191     if(errorstate != HAL_MMC_ERROR_NONE)
01192     {
01193       /* Clear all the static flags */
01194       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01195       __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01196       hmmc->ErrorCode = errorstate;
01197       hmmc->State = HAL_MMC_STATE_READY;
01198       return HAL_ERROR;
01199     }
01200
01201     return HAL_OK;
01202   }
01203   else
01204   {
01205     return HAL_BUSY;
01206   }
01207 }
01208
01209 /**
01210   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01211   *         is managed by DMA mode.
01212   * @note   This API should be followed by a check on the card state through
01213   *         HAL_MMC_GetCardState().
01214   * @note   You could also check the DMA transfer process through the MMC Tx
01215   *         interrupt event.
01216   * @param  hmmc: Pointer to MMC handle
01217   * @param  pData: Pointer to the buffer that will contain the data to transmit
01218   * @param  BlockAdd: Block Address where data will be written
01219   * @param  NumberOfBlocks: Number of blocks to write
01220   * @retval HAL status
01221   */
01222 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01223 {
01224   SDMMC_DataInitTypeDef config;
01225   uint32_t errorstate;
01226   uint32_t add = BlockAdd;
01227
01228   if(NULL == pData)
01229   {
01230     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01231     return HAL_ERROR;
01232   }
01233
01234   if(hmmc->State == HAL_MMC_STATE_READY)
01235   {
01236     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
01237
01238     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
01239     {
01240       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01241       return HAL_ERROR;
01242     }
01243
01244     hmmc->State = HAL_MMC_STATE_BUSY;
01245
01246     /* Initialize data control register */
01247     hmmc->Instance->DCTRL = 0U;
01248
01249     hmmc->pTxBuffPtr = pData;
01250     hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
01251
01252     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01253     {
01254       add *= 512U;
01255     }
01256
01257     /* Set Block Size for Card */
01258     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
01259     if(errorstate != HAL_MMC_ERROR_NONE)
01260     {
01261       /* Clear all the static flags */
01262       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01263       hmmc->ErrorCode |= errorstate;
01264       hmmc->State = HAL_MMC_STATE_READY;
01265       return HAL_ERROR;
01266     }
01267
01268     /* Configure the MMC DPSM (Data Path State Machine) */
01269     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01270     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
01271     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01272     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01273     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01274     config.DPSM          = SDMMC_DPSM_DISABLE;
01275     (void)SDMMC_ConfigData(hmmc->Instance, &config);
01276
01277     /* Enable transfer interrupts */
01278     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01279
01280     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
01281
01282     hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
01283     hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01284
01285     /* Write Blocks in Polling mode */
01286     if(NumberOfBlocks > 1U)
01287     {
01288       hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
01289
01290       /* Write Multi Block command */
01291       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
01292     }
01293     else
01294     {
01295       hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
01296
01297       /* Write Single Block command */
01298       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
01299     }
01300     if(errorstate != HAL_MMC_ERROR_NONE)
01301     {
01302       /* Clear all the static flags */
01303       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01304       __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01305       hmmc->ErrorCode |= errorstate;
01306       hmmc->State = HAL_MMC_STATE_READY;
01307       return HAL_ERROR;
01308     }
01309
01310     return HAL_OK;
01311   }
01312   else
01313   {
01314     return HAL_BUSY;
01315   }
01316 }
01317
01318 /**
01319   * @brief  Erases the specified memory area of the given MMC card.
01320   * @note   This API should be followed by a check on the card state through
01321   *         HAL_MMC_GetCardState().
01322   * @param  hmmc: Pointer to MMC handle
01323   * @param  BlockStartAdd: Start Block address
01324   * @param  BlockEndAdd: End Block address
01325   * @retval HAL status
01326   */
01327 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
01328 {
01329   uint32_t errorstate;
01330   uint32_t start_add = BlockStartAdd;
01331   uint32_t end_add = BlockEndAdd;
01332
01333   if(hmmc->State == HAL_MMC_STATE_READY)
01334   {
01335     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
01336
01337     if(end_add < start_add)
01338     {
01339       hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01340       return HAL_ERROR;
01341     }
01342
01343     if(end_add > (hmmc->MmcCard.LogBlockNbr))
01344     {
01345       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01346       return HAL_ERROR;
01347     }
01348
01349     hmmc->State = HAL_MMC_STATE_BUSY;
01350
01351     /* Check if the card command class supports erase command */
01352     if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
01353     {
01354       /* Clear all the static flags */
01355       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01356       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
01357       hmmc->State = HAL_MMC_STATE_READY;
01358       return HAL_ERROR;
01359     }
01360
01361     if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
01362     {
01363       /* Clear all the static flags */
01364       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01365       hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
01366       hmmc->State = HAL_MMC_STATE_READY;
01367       return HAL_ERROR;
01368     }
01369
01370     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01371     {
01372       start_add *= 512U;
01373       end_add   *= 512U;
01374     }
01375
01376     /* Send CMD35 MMC_ERASE_GRP_START with argument as addr  */
01377     errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
01378     if(errorstate != HAL_MMC_ERROR_NONE)
01379     {
01380       /* Clear all the static flags */
01381       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01382       hmmc->ErrorCode |= errorstate;
01383       hmmc->State = HAL_MMC_STATE_READY;
01384       return HAL_ERROR;
01385     }
01386
01387     /* Send CMD36 MMC_ERASE_GRP_END with argument as addr  */
01388     errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
01389     if(errorstate != HAL_MMC_ERROR_NONE)
01390     {
01391       /* Clear all the static flags */
01392       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01393       hmmc->ErrorCode |= errorstate;
01394       hmmc->State = HAL_MMC_STATE_READY;
01395       return HAL_ERROR;
01396     }
01397
01398     /* Send CMD38 ERASE */
01399     errorstate = SDMMC_CmdErase(hmmc->Instance);
01400     if(errorstate != HAL_MMC_ERROR_NONE)
01401     {
01402       /* Clear all the static flags */
01403       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01404       hmmc->ErrorCode |= errorstate;
01405       hmmc->State = HAL_MMC_STATE_READY;
01406       return HAL_ERROR;
01407     }
01408
01409     hmmc->State = HAL_MMC_STATE_READY;
01410
01411     return HAL_OK;
01412   }
01413   else
01414   {
01415     return HAL_BUSY;
01416   }
01417 }
01418
01419 /**
01420   * @brief  This function handles MMC card interrupt request.
01421   * @param  hmmc: Pointer to MMC handle
01422   * @retval None
01423   */
01424 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
01425 {
01426   uint32_t errorstate;
01427   uint32_t context = hmmc->Context;
01428
01429   /* Check for SDMMC interrupt flags */
01430   if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
01431   {
01432     MMC_Read_IT(hmmc);
01433   }
01434
01435   else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
01436   {
01437     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
01438
01439     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
01440                                SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE |\
01441                                SDMMC_IT_RXFIFOHF);
01442
01443     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
01444     __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
01445
01446     if((context & MMC_CONTEXT_DMA) != 0U)
01447     {
01448       hmmc->Instance->DLEN = 0;
01449       hmmc->Instance->DCTRL = 0;
01450       hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
01451
01452       /* Stop Transfer for Write Multi blocks or Read Multi blocks */
01453       if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01454       {
01455         errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
01456         if(errorstate != HAL_MMC_ERROR_NONE)
01457         {
01458           hmmc->ErrorCode |= errorstate;
01459 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01460           hmmc->ErrorCallback(hmmc);
01461 #else
01462           HAL_MMC_ErrorCallback(hmmc);
01463 #endif
01464         }
01465       }
01466
01467       /* Clear all the static flags */
01468       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
01469
01470       hmmc->State = HAL_MMC_STATE_READY;
01471       if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01472       {
01473 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01474         hmmc->TxCpltCallback(hmmc);
01475 #else
01476         HAL_MMC_TxCpltCallback(hmmc);
01477 #endif
01478       }
01479       if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
01480       {
01481 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01482         hmmc->RxCpltCallback(hmmc);
01483 #else
01484         HAL_MMC_RxCpltCallback(hmmc);
01485 #endif
01486       }
01487     }
01488     else if((context & MMC_CONTEXT_IT) != 0U)
01489     {
01490       /* Stop Transfer for Write Multi blocks or Read Multi blocks */
01491       if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01492       {
01493         errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
01494         if(errorstate != HAL_MMC_ERROR_NONE)
01495         {
01496           hmmc->ErrorCode |= errorstate;
01497 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01498           hmmc->ErrorCallback(hmmc);
01499 #else
01500           HAL_MMC_ErrorCallback(hmmc);
01501 #endif
01502         }
01503       }
01504
01505       /* Clear all the static flags */
01506       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
01507
01508       hmmc->State = HAL_MMC_STATE_READY;
01509       if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
01510       {
01511 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01512         hmmc->RxCpltCallback(hmmc);
01513 #else
01514         HAL_MMC_RxCpltCallback(hmmc);
01515 #endif
01516       }
01517       else
01518       {
01519 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01520         hmmc->TxCpltCallback(hmmc);
01521 #else
01522         HAL_MMC_TxCpltCallback(hmmc);
01523 #endif
01524       }
01525     }
01526     else
01527     {
01528       /* Nothing to do */
01529     }
01530   }
01531
01532   else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
01533   {
01534     MMC_Write_IT(hmmc);
01535   }
01536
01537   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
01538   {
01539     /* Set Error code */
01540     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
01541     {
01542       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
01543     }
01544     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
01545     {
01546       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
01547     }
01548     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
01549     {
01550       hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
01551     }
01552     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
01553     {
01554       hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
01555     }
01556
01557     /* Clear All flags */
01558     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
01559
01560     /* Disable all interrupts */
01561     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
01562                                SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
01563
01564     __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
01565     hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
01566     hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
01567     hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
01568     hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
01569     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
01570
01571     if((context & MMC_CONTEXT_IT) != 0U)
01572     {
01573       /* Set the MMC state to ready to be able to start again the process */
01574       hmmc->State = HAL_MMC_STATE_READY;
01575 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01576       hmmc->ErrorCallback(hmmc);
01577 #else
01578       HAL_MMC_ErrorCallback(hmmc);
01579 #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
01580     }
01581     else if((context & MMC_CONTEXT_DMA) != 0U)
01582     {
01583       if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
01584       {
01585         /* Disable Internal DMA */
01586         __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
01587         hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
01588
01589         /* Set the MMC state to ready to be able to start again the process */
01590         hmmc->State = HAL_MMC_STATE_READY;
01591 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01592         hmmc->ErrorCallback(hmmc);
01593 #else
01594         HAL_MMC_ErrorCallback(hmmc);
01595 #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
01596       }
01597     }
01598     else
01599     {
01600       /* Nothing to do */
01601     }
01602   }
01603
01604   else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
01605   {
01606     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
01607     if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
01608     {
01609       /* Current buffer is buffer0, Transfer complete for buffer1 */
01610       if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
01611       {
01612 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01613         hmmc->Write_DMADblBuf1CpltCallback(hmmc);
01614 #else
01615         HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(hmmc);
01616 #endif
01617       }
01618       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
01619       {
01620 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01621         hmmc->Read_DMADblBuf1CpltCallback(hmmc);
01622 #else
01623         HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(hmmc);
01624 #endif
01625       }
01626     }
01627     else /* MMC_DMA_BUFFER1 */
01628     {
01629       /* Current buffer is buffer1, Transfer complete for buffer0 */
01630       if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
01631       {
01632 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01633         hmmc->Write_DMADblBuf0CpltCallback(hmmc);
01634 #else
01635         HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(hmmc);
01636 #endif
01637       }
01638       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
01639       {
01640 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01641         hmmc->Read_DMADblBuf0CpltCallback(hmmc);
01642 #else
01643         HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(hmmc);
01644 #endif
01645       }
01646     }
01647   }
01648
01649   else
01650   {
01651     /* Nothing to do */
01652   }
01653 }
01654
01655 /**
01656   * @brief return the MMC state
01657   * @param hmmc: Pointer to mmc handle
01658   * @retval HAL state
01659   */
01660 HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
01661 {
01662   return hmmc->State;
01663 }
01664
01665 /**
01666 * @brief  Return the MMC error code
01667 * @param  hmmc : Pointer to a MMC_HandleTypeDef structure that contains
01668   *              the configuration information.
01669 * @retval MMC Error Code
01670 */
01671 uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
01672 {
01673   return hmmc->ErrorCode;
01674 }
01675
01676 /**
01677   * @brief Tx Transfer completed callbacks
01678   * @param hmmc: Pointer to MMC handle
01679   * @retval None
01680   */
01681 __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
01682 {
01683   /* Prevent unused argument(s) compilation warning */
01684   UNUSED(hmmc);
01685
01686   /* NOTE : This function should not be modified, when the callback is needed,
01687             the HAL_MMC_TxCpltCallback can be implemented in the user file
01688    */
01689 }
01690
01691 /**
01692   * @brief Rx Transfer completed callbacks
01693   * @param hmmc: Pointer MMC handle
01694   * @retval None
01695   */
01696 __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
01697 {
01698   /* Prevent unused argument(s) compilation warning */
01699   UNUSED(hmmc);
01700
01701   /* NOTE : This function should not be modified, when the callback is needed,
01702             the HAL_MMC_RxCpltCallback can be implemented in the user file
01703    */
01704 }
01705
01706 /**
01707   * @brief MMC error callbacks
01708   * @param hmmc: Pointer MMC handle
01709   * @retval None
01710   */
01711 __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
01712 {
01713   /* Prevent unused argument(s) compilation warning */
01714   UNUSED(hmmc);
01715
01716   /* NOTE : This function should not be modified, when the callback is needed,
01717             the HAL_MMC_ErrorCallback can be implemented in the user file
01718    */
01719 }
01720
01721 /**
01722   * @brief MMC Abort callbacks
01723   * @param hmmc: Pointer MMC handle
01724   * @retval None
01725   */
01726 __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
01727 {
01728   /* Prevent unused argument(s) compilation warning */
01729   UNUSED(hmmc);
01730
01731   /* NOTE : This function should not be modified, when the callback is needed,
01732             the HAL_MMC_AbortCallback can be implemented in the user file
01733    */
01734 }
01735
01736 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
01737 /**
01738   * @brief  Register a User MMC Callback
01739   *         To be used instead of the weak (surcharged) predefined callback
01740   * @param hmmc : MMC handle
01741   * @param CallbackId : ID of the callback to be registered
01742   *        This parameter can be one of the following values:
01743   *          @arg @ref HAL_MMC_TX_CPLT_CB_ID                 MMC Tx Complete Callback ID
01744   *          @arg @ref HAL_MMC_RX_CPLT_CB_ID                 MMC Rx Complete Callback ID
01745   *          @arg @ref HAL_MMC_ERROR_CB_ID                   MMC Error Callback ID
01746   *          @arg @ref HAL_MMC_ABORT_CB_ID                   MMC Abort Callback ID
01747   *          @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID  MMC DMA Rx Double buffer 0 Callback ID
01748   *          @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID  MMC DMA Rx Double buffer 1 Callback ID
01749   *          @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
01750   *          @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
01751   *          @arg @ref HAL_MMC_MSP_INIT_CB_ID                MMC MspInit Callback ID
01752   *          @arg @ref HAL_MMC_MSP_DEINIT_CB_ID              MMC MspDeInit Callback ID
01753   * @param pCallback : pointer to the Callback function
01754   * @retval status
01755   */
01756 HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
01757 {
01758   HAL_StatusTypeDef status = HAL_OK;
01759
01760   if(pCallback == NULL)
01761   {
01762     /* Update the error code */
01763     hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01764     return HAL_ERROR;
01765   }
01766
01767   /* Process locked */
01768   __HAL_LOCK(hmmc);
01769
01770   if(hmmc->State == HAL_MMC_STATE_READY)
01771   {
01772     switch (CallbackId)
01773     {
01774     case HAL_MMC_TX_CPLT_CB_ID :
01775       hmmc->TxCpltCallback = pCallback;
01776       break;
01777     case HAL_MMC_RX_CPLT_CB_ID :
01778       hmmc->RxCpltCallback = pCallback;
01779       break;
01780     case HAL_MMC_ERROR_CB_ID :
01781       hmmc->ErrorCallback = pCallback;
01782       break;
01783     case HAL_MMC_ABORT_CB_ID :
01784       hmmc->AbortCpltCallback = pCallback;
01785       break;
01786     case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
01787       hmmc->Read_DMADblBuf0CpltCallback = pCallback;
01788       break;
01789     case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
01790       hmmc->Read_DMADblBuf1CpltCallback = pCallback;
01791       break;
01792     case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
01793       hmmc->Write_DMADblBuf0CpltCallback = pCallback;
01794       break;
01795     case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
01796       hmmc->Write_DMADblBuf1CpltCallback = pCallback;
01797       break;
01798     case HAL_MMC_MSP_INIT_CB_ID :
01799       hmmc->MspInitCallback = pCallback;
01800       break;
01801     case HAL_MMC_MSP_DEINIT_CB_ID :
01802       hmmc->MspDeInitCallback = pCallback;
01803       break;
01804     default :
01805       /* Update the error code */
01806       hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01807       /* update return status */
01808       status =  HAL_ERROR;
01809       break;
01810     }
01811   }
01812   else if (hmmc->State == HAL_MMC_STATE_RESET)
01813   {
01814     switch (CallbackId)
01815     {
01816     case HAL_MMC_MSP_INIT_CB_ID :
01817       hmmc->MspInitCallback = pCallback;
01818       break;
01819     case HAL_MMC_MSP_DEINIT_CB_ID :
01820       hmmc->MspDeInitCallback = pCallback;
01821       break;
01822     default :
01823       /* Update the error code */
01824       hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01825       /* update return status */
01826       status =  HAL_ERROR;
01827       break;
01828     }
01829   }
01830   else
01831   {
01832     /* Update the error code */
01833     hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01834     /* update return status */
01835     status =  HAL_ERROR;
01836   }
01837
01838   /* Release Lock */
01839   __HAL_UNLOCK(hmmc);
01840   return status;
01841 }
01842
01843 /**
01844   * @brief  Unregister a User MMC Callback
01845   *         MMC Callback is redirected to the weak (surcharged) predefined callback
01846   * @param hmmc : MMC handle
01847   * @param CallbackId : ID of the callback to be unregistered
01848   *        This parameter can be one of the following values:
01849   *          @arg @ref HAL_MMC_TX_CPLT_CB_ID                 MMC Tx Complete Callback ID
01850   *          @arg @ref HAL_MMC_RX_CPLT_CB_ID                 MMC Rx Complete Callback ID
01851   *          @arg @ref HAL_MMC_ERROR_CB_ID                   MMC Error Callback ID
01852   *          @arg @ref HAL_MMC_ABORT_CB_ID                   MMC Abort Callback ID
01853   *          @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID  MMC DMA Rx Double buffer 0 Callback ID
01854   *          @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID  MMC DMA Rx Double buffer 1 Callback ID
01855   *          @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
01856   *          @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
01857   *          @arg @ref HAL_MMC_MSP_INIT_CB_ID                MMC MspInit Callback ID
01858   *          @arg @ref HAL_MMC_MSP_DEINIT_CB_ID              MMC MspDeInit Callback ID
01859   * @retval status
01860   */
01861 HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
01862 {
01863   HAL_StatusTypeDef status = HAL_OK;
01864
01865   /* Process locked */
01866   __HAL_LOCK(hmmc);
01867
01868   if(hmmc->State == HAL_MMC_STATE_READY)
01869   {
01870     switch (CallbackId)
01871     {
01872     case HAL_MMC_TX_CPLT_CB_ID :
01873       hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
01874       break;
01875     case HAL_MMC_RX_CPLT_CB_ID :
01876       hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
01877       break;
01878     case HAL_MMC_ERROR_CB_ID :
01879       hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
01880       break;
01881     case HAL_MMC_ABORT_CB_ID :
01882       hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
01883       break;
01884     case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
01885       hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback;
01886       break;
01887     case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
01888       hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback;
01889       break;
01890     case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
01891       hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback;
01892       break;
01893     case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
01894       hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback;
01895       break;
01896     case HAL_MMC_MSP_INIT_CB_ID :
01897       hmmc->MspInitCallback = HAL_MMC_MspInit;
01898       break;
01899     case HAL_MMC_MSP_DEINIT_CB_ID :
01900       hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
01901       break;
01902     default :
01903       /* Update the error code */
01904       hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01905       /* update return status */
01906       status =  HAL_ERROR;
01907       break;
01908     }
01909   }
01910   else if (hmmc->State == HAL_MMC_STATE_RESET)
01911   {
01912     switch (CallbackId)
01913     {
01914     case HAL_MMC_MSP_INIT_CB_ID :
01915       hmmc->MspInitCallback = HAL_MMC_MspInit;
01916       break;
01917     case HAL_MMC_MSP_DEINIT_CB_ID :
01918       hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
01919       break;
01920     default :
01921       /* Update the error code */
01922       hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01923       /* update return status */
01924       status =  HAL_ERROR;
01925       break;
01926     }
01927   }
01928   else
01929   {
01930     /* Update the error code */
01931     hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
01932     /* update return status */
01933     status =  HAL_ERROR;
01934   }
01935
01936   /* Release Lock */
01937   __HAL_UNLOCK(hmmc);
01938   return status;
01939 }
01940 #endif
01941
01942 /**
01943   * @}
01944   */
01945
01946 /** @addtogroup MMC_Exported_Functions_Group3
01947  *  @brief   management functions
01948  *
01949 @verbatim
01950   ==============================================================================
01951                       ##### Peripheral Control functions #####
01952   ==============================================================================
01953   [..]
01954     This subsection provides a set of functions allowing to control the MMC card
01955     operations and get the related information
01956
01957 @endverbatim
01958   * @{
01959   */
01960
01961 /**
01962   * @brief  Returns information the information of the card which are stored on
01963   *         the CID register.
01964   * @param  hmmc: Pointer to MMC handle
01965   * @param  pCID: Pointer to a HAL_MMC_CIDTypedef structure that
01966   *         contains all CID register parameters
01967   * @retval HAL status
01968   */
01969 HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
01970 {
01971   pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
01972
01973   pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
01974
01975   pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
01976
01977   pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
01978
01979   pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
01980
01981   pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
01982
01983   pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
01984
01985   pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
01986
01987   pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
01988
01989   pCID->Reserved2 = 1U;
01990
01991   return HAL_OK;
01992 }
01993
01994 /**
01995   * @brief  Returns information the information of the card which are stored on
01996   *         the CSD register.
01997   * @param  hmmc: Pointer to MMC handle
01998   * @param  pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
01999   *         contains all CSD register parameters
02000   * @retval HAL status
02001   */
02002 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
02003 {
02004   uint32_t block_nbr = 0;
02005
02006   pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
02007
02008   pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
02009
02010   pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
02011
02012   pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
02013
02014   pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
02015
02016   pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
02017
02018   pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
02019
02020   pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
02021
02022   pCSD->PartBlockRead   = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
02023
02024   pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
02025
02026   pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
02027
02028   pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
02029
02030   pCSD->Reserved2 = 0U; /*!< Reserved */
02031
02032   if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
02033   {
02034     return HAL_ERROR;
02035   }
02036
02037   if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
02038   {
02039     pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
02040
02041     pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
02042
02043     pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
02044
02045     pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
02046
02047     pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
02048
02049     pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
02050
02051     hmmc->MmcCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
02052     hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
02053     hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
02054
02055     hmmc->MmcCard.LogBlockNbr =  (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
02056     hmmc->MmcCard.LogBlockSize = 512U;
02057   }
02058   else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
02059   {
02060     hmmc->MmcCard.BlockNbr = block_nbr;
02061     hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
02062     hmmc->MmcCard.BlockSize = 512U;
02063     hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
02064   }
02065   else
02066   {
02067     /* Clear all the static flags */
02068     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02069     hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
02070     hmmc->State = HAL_MMC_STATE_READY;
02071     return HAL_ERROR;
02072   }
02073
02074   pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
02075
02076   pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
02077
02078   pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
02079
02080   pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
02081
02082   pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
02083
02084   pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
02085
02086   pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
02087
02088   pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
02089
02090   pCSD->Reserved3 = 0;
02091
02092   pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
02093
02094   pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
02095
02096   pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
02097
02098   pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
02099
02100   pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
02101
02102   pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
02103
02104   pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
02105
02106   pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
02107
02108   pCSD->Reserved4 = 1;
02109
02110   return HAL_OK;
02111 }
02112
02113 /**
02114   * @brief  Gets the MMC card info.
02115   * @param  hmmc: Pointer to MMC handle
02116   * @param  pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
02117   *         will contain the MMC card status information
02118   * @retval HAL status
02119   */
02120 HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
02121 {
02122   pCardInfo->CardType     = (uint32_t)(hmmc->MmcCard.CardType);
02123   pCardInfo->Class        = (uint32_t)(hmmc->MmcCard.Class);
02124   pCardInfo->RelCardAdd   = (uint32_t)(hmmc->MmcCard.RelCardAdd);
02125   pCardInfo->BlockNbr     = (uint32_t)(hmmc->MmcCard.BlockNbr);
02126   pCardInfo->BlockSize    = (uint32_t)(hmmc->MmcCard.BlockSize);
02127   pCardInfo->LogBlockNbr  = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
02128   pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
02129
02130   return HAL_OK;
02131 }
02132
02133 /**
02134   * @brief  Enables wide bus operation for the requested card if supported by
02135   *         card.
02136   * @param  hmmc: Pointer to MMC handle
02137   * @param  WideMode: Specifies the MMC card wide bus mode
02138   *          This parameter can be one of the following values:
02139   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
02140   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
02141   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
02142   * @retval HAL status
02143   */
02144 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
02145 {
02146   __IO uint32_t count = 0U;
02147   SDMMC_InitTypeDef Init;
02148   uint32_t errorstate;
02149   uint32_t response = 0U, busy = 0U;
02150
02151   /* Check the parameters */
02152   assert_param(IS_SDMMC_BUS_WIDE(WideMode));
02153
02154   /* Chnage Satte */
02155   hmmc->State = HAL_MMC_STATE_BUSY;
02156
02157   if(WideMode == SDMMC_BUS_WIDE_8B)
02158   {
02159     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
02160     if(errorstate != HAL_MMC_ERROR_NONE)
02161     {
02162       hmmc->ErrorCode |= errorstate;
02163     }
02164   }
02165   else if(WideMode == SDMMC_BUS_WIDE_4B)
02166   {
02167     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
02168     if(errorstate != HAL_MMC_ERROR_NONE)
02169     {
02170       hmmc->ErrorCode |= errorstate;
02171     }
02172   }
02173   else if(WideMode == SDMMC_BUS_WIDE_1B)
02174   {
02175     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
02176     if(errorstate != HAL_MMC_ERROR_NONE)
02177     {
02178       hmmc->ErrorCode |= errorstate;
02179     }
02180   }
02181   else
02182   {
02183     /* WideMode is not a valid argument*/
02184     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
02185   }
02186
02187   /* Check for switch error and violation of the trial number of sending CMD 13 */
02188   while(busy == 0U)
02189   {
02190     if(count == SDMMC_MAX_TRIAL)
02191     {
02192       hmmc->State = HAL_MMC_STATE_READY;
02193       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
02194       return HAL_ERROR;
02195     }
02196     count++;
02197
02198     /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02199     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02200     if(errorstate != HAL_MMC_ERROR_NONE)
02201     {
02202       hmmc->ErrorCode |= errorstate;
02203     }
02204
02205     /* Get command response */
02206     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02207
02208     /* Get operating voltage*/
02209     busy = (((response >> 7U) == 1U) ? 0U : 1U);
02210   }
02211
02212   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02213   count = SDMMC_DATATIMEOUT;
02214   while((response & 0x00000100U) == 0U)
02215   {
02216     if(count == 0U)
02217     {
02218       hmmc->State = HAL_MMC_STATE_READY;
02219       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
02220       return HAL_ERROR;
02221     }
02222     count--;
02223
02224     /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02225     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02226     if(errorstate != HAL_MMC_ERROR_NONE)
02227     {
02228       hmmc->ErrorCode |= errorstate;
02229     }
02230
02231     /* Get command response */
02232     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02233   }
02234
02235   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
02236   {
02237     /* Clear all the static flags */
02238     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02239     hmmc->State = HAL_MMC_STATE_READY;
02240     return HAL_ERROR;
02241   }
02242   else
02243   {
02244     /* Configure the SDMMC peripheral */
02245     Init.ClockEdge           = hmmc->Init.ClockEdge;
02246     Init.ClockPowerSave      = hmmc->Init.ClockPowerSave;
02247     Init.BusWide             = WideMode;
02248     Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
02249     Init.ClockDiv            = hmmc->Init.ClockDiv;
02250     (void)SDMMC_Init(hmmc->Instance, Init);
02251   }
02252
02253   /* Change State */
02254   hmmc->State = HAL_MMC_STATE_READY;
02255
02256   return HAL_OK;
02257 }
02258
02259 /**
02260   * @brief  Configure the speed bus mode
02261   * @param  hmmc: Pointer to the MMC handle
02262   * @param  SpeedMode: Specifies the MMC card speed bus mode
02263   *          This parameter can be one of the following values:
02264   *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
02265   *            @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
02266   *            @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
02267   *            @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
02268   * @retval HAL status
02269   */
02270
02271 HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
02272 {
02273   uint32_t tickstart;
02274   HAL_StatusTypeDef status = HAL_OK;
02275   uint32_t device_type;
02276   uint32_t errorstate;
02277
02278   /* Check the parameters */
02279   assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
02280   /* Change State */
02281   hmmc->State = HAL_MMC_STATE_BUSY;
02282
02283   if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */
02284   {
02285     return HAL_ERROR;
02286   }
02287
02288   switch (SpeedMode)
02289   {
02290     case SDMMC_SPEED_MODE_AUTO:
02291     {
02292       if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
02293       {
02294         /* High Speed DDR mode allowed */
02295         errorstate = MMC_HighSpeed(hmmc, ENABLE);
02296         if(errorstate != HAL_MMC_ERROR_NONE)
02297         {
02298           hmmc->ErrorCode |= errorstate;
02299         }
02300         else
02301         {
02302           errorstate = MMC_DDR_Mode(hmmc, ENABLE);
02303           if(errorstate != HAL_MMC_ERROR_NONE)
02304           {
02305             hmmc->ErrorCode |= errorstate;
02306           }
02307         }
02308       }
02309       else if ((device_type & 0x02U) != 0U)
02310       {
02311         /* High Speed mode allowed */
02312         errorstate = MMC_HighSpeed(hmmc, ENABLE);
02313         if(errorstate != HAL_MMC_ERROR_NONE)
02314         {
02315           hmmc->ErrorCode |= errorstate;
02316         }
02317       }
02318       else
02319       {
02320         /* Nothing to do : keep current speed */
02321       }
02322       break;
02323     }
02324     case SDMMC_SPEED_MODE_DDR:
02325     {
02326       if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
02327       {
02328         /* High Speed DDR mode allowed */
02329         errorstate = MMC_HighSpeed(hmmc, ENABLE);
02330         if(errorstate != HAL_MMC_ERROR_NONE)
02331         {
02332           hmmc->ErrorCode |= errorstate;
02333         }
02334         else
02335         {
02336           errorstate = MMC_DDR_Mode(hmmc, ENABLE);
02337           if(errorstate != HAL_MMC_ERROR_NONE)
02338           {
02339             hmmc->ErrorCode |= errorstate;
02340           }
02341         }
02342       }
02343       else
02344       {
02345         /* High Speed DDR mode not allowed */
02346         hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
02347         status = HAL_ERROR;
02348       }
02349       break;
02350     }
02351     case SDMMC_SPEED_MODE_HIGH:
02352     {
02353       if ((device_type & 0x02U) != 0U)
02354       {
02355         /* High Speed mode allowed */
02356         errorstate = MMC_HighSpeed(hmmc, ENABLE);
02357         if(errorstate != HAL_MMC_ERROR_NONE)
02358         {
02359           hmmc->ErrorCode |= errorstate;
02360         }
02361       }
02362       else
02363       {
02364         /* High Speed mode not allowed */
02365         hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
02366         status = HAL_ERROR;
02367       }
02368       break;
02369     }
02370     case SDMMC_SPEED_MODE_DEFAULT:
02371     {
02372       if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
02373       {
02374         /* High Speed DDR mode activated */
02375         errorstate = MMC_DDR_Mode(hmmc, DISABLE);
02376         if(errorstate != HAL_MMC_ERROR_NONE)
02377         {
02378           hmmc->ErrorCode |= errorstate;
02379         }
02380       }
02381       if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
02382       {
02383         /* High Speed mode activated */
02384         errorstate = MMC_HighSpeed(hmmc, DISABLE);
02385         if(errorstate != HAL_MMC_ERROR_NONE)
02386         {
02387           hmmc->ErrorCode |= errorstate;
02388         }
02389       }
02390       break;
02391     }
02392     default:
02393       hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
02394       status = HAL_ERROR;
02395       break;
02396   }
02397
02398   /* Verify that MMC card is ready to use after Speed mode switch*/
02399   tickstart = HAL_GetTick();
02400   while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER))
02401   {
02402     if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02403     {
02404       hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
02405       hmmc->State = HAL_MMC_STATE_READY;
02406       return HAL_TIMEOUT;
02407     }
02408   }
02409
02410   /* Change State */
02411   hmmc->State = HAL_MMC_STATE_READY;
02412   return status;
02413 }
02414
02415 /**
02416   * @brief  Gets the current mmc card data state.
02417   * @param  hmmc: pointer to MMC handle
02418   * @retval Card state
02419   */
02420 HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
02421 {
02422   uint32_t cardstate;
02423   uint32_t errorstate;
02424   uint32_t resp1 = 0U;
02425
02426   errorstate = MMC_SendStatus(hmmc, &resp1);
02427   if(errorstate != HAL_MMC_ERROR_NONE)
02428   {
02429     hmmc->ErrorCode |= errorstate;
02430   }
02431
02432   cardstate = ((resp1 >> 9U) & 0x0FU);
02433
02434   return (HAL_MMC_CardStateTypeDef)cardstate;
02435 }
02436
02437 /**
02438   * @brief  Abort the current transfer and disable the MMC.
02439   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02440   *                the configuration information for MMC module.
02441   * @retval HAL status
02442   */
02443 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
02444 {
02445   HAL_MMC_CardStateTypeDef CardState;
02446
02447   /* DIsable All interrupts */
02448   __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02449                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02450
02451   /* Clear All flags */
02452   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
02453
02454   /* If IDMA Context, disable Internal DMA */
02455   hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
02456
02457   hmmc->State = HAL_MMC_STATE_READY;
02458
02459   /* Initialize the MMC operation */
02460   hmmc->Context = MMC_CONTEXT_NONE;
02461
02462   CardState = HAL_MMC_GetCardState(hmmc);
02463   if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
02464   {
02465     hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
02466   }
02467   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
02468   {
02469     return HAL_ERROR;
02470   }
02471   return HAL_OK;
02472 }
02473
02474 /**
02475   * @brief  Abort the current transfer and disable the MMC (IT mode).
02476   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02477   *                the configuration information for MMC module.
02478   * @retval HAL status
02479   */
02480 HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
02481 {
02482   HAL_MMC_CardStateTypeDef CardState;
02483
02484   /* DIsable All interrupts */
02485   __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02486                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02487
02488   /* If IDMA Context, disable Internal DMA */
02489   hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
02490
02491   /* Clear All flags */
02492   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
02493
02494   CardState = HAL_MMC_GetCardState(hmmc);
02495   hmmc->State = HAL_MMC_STATE_READY;
02496
02497   if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
02498   {
02499     hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
02500   }
02501   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
02502   {
02503     return HAL_ERROR;
02504   }
02505   else
02506   {
02507 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
02508     hmmc->AbortCpltCallback(hmmc);
02509 #else
02510     HAL_MMC_AbortCallback(hmmc);
02511 #endif
02512   }
02513
02514   return HAL_OK;
02515 }
02516
02517 /**
02518   * @}
02519   */
02520
02521 /**
02522   * @}
02523   */
02524
02525 /* Private function ----------------------------------------------------------*/
02526 /** @addtogroup MMC_Private_Functions
02527   * @{
02528   */
02529
02530
02531 /**
02532   * @brief  Initializes the mmc card.
02533   * @param  hmmc: Pointer to MMC handle
02534   * @retval MMC Card error state
02535   */
02536 static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
02537 {
02538   HAL_MMC_CardCSDTypeDef CSD;
02539   uint32_t errorstate;
02540   uint16_t mmc_rca = 1U;
02541   MMC_InitTypeDef Init;
02542
02543   /* Check the power State */
02544   if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
02545   {
02546     /* Power off */
02547     return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
02548   }
02549
02550   /* Send CMD2 ALL_SEND_CID */
02551   errorstate = SDMMC_CmdSendCID(hmmc->Instance);
02552   if(errorstate != HAL_MMC_ERROR_NONE)
02553   {
02554     return errorstate;
02555   }
02556   else
02557   {
02558     /* Get Card identification number data */
02559     hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02560     hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
02561     hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
02562     hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
02563   }
02564
02565   /* Send CMD3 SET_REL_ADDR with argument 0 */
02566   /* MMC Card publishes its RCA. */
02567   errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
02568   if(errorstate != HAL_MMC_ERROR_NONE)
02569   {
02570     return errorstate;
02571   }
02572
02573   /* Get the MMC card RCA */
02574   hmmc->MmcCard.RelCardAdd = mmc_rca;
02575
02576   /* Send CMD9 SEND_CSD with argument as card's RCA */
02577   errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
02578   if(errorstate != HAL_MMC_ERROR_NONE)
02579   {
02580     return errorstate;
02581   }
02582   else
02583   {
02584     /* Get Card Specific Data */
02585     hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02586     hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
02587     hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
02588     hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
02589   }
02590
02591   /* Get the Card Class */
02592   hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
02593
02594    /* Select the Card */
02595   errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02596   if(errorstate != HAL_MMC_ERROR_NONE)
02597   {
02598     return errorstate;
02599   }
02600
02601   /* Get CSD parameters */
02602   if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
02603   {
02604     return hmmc->ErrorCode;
02605   }
02606
02607   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02608   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02609   if(errorstate != HAL_MMC_ERROR_NONE)
02610   {
02611     hmmc->ErrorCode |= errorstate;
02612   }
02613
02614   /* Configure the SDMMC peripheral */
02615   Init.ClockEdge           = hmmc->Init.ClockEdge;
02616   Init.ClockPowerSave      = hmmc->Init.ClockPowerSave;
02617   Init.BusWide             = SDMMC_BUS_WIDE_1B;
02618   Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
02619   Init.ClockDiv            = hmmc->Init.ClockDiv;
02620   (void)SDMMC_Init(hmmc->Instance, Init);
02621
02622   /* All cards are initialized */
02623   return HAL_MMC_ERROR_NONE;
02624 }
02625
02626 /**
02627   * @brief  Enquires cards about their operating voltage and configures clock
02628   *         controls and stores MMC information that will be needed in future
02629   *         in the MMC handle.
02630   * @param  hmmc: Pointer to MMC handle
02631   * @retval error state
02632   */
02633 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
02634 {
02635   __IO uint32_t count = 0U;
02636   uint32_t response = 0U, validvoltage = 0U;
02637   uint32_t errorstate;
02638
02639   /* CMD0: GO_IDLE_STATE */
02640   errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
02641   if(errorstate != HAL_MMC_ERROR_NONE)
02642   {
02643     return errorstate;
02644   }
02645
02646   while(validvoltage == 0U)
02647   {
02648     if(count++ == SDMMC_MAX_VOLT_TRIAL)
02649     {
02650       return HAL_MMC_ERROR_INVALID_VOLTRANGE;
02651     }
02652
02653     /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
02654     errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
02655     if(errorstate != HAL_MMC_ERROR_NONE)
02656     {
02657       return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
02658     }
02659
02660     /* Get command response */
02661     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02662
02663     /* Get operating voltage*/
02664     validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
02665   }
02666
02667   /* When power routine is finished and command returns valid voltage */
02668   if (((response & (0xFF000000U)) >> 24) == 0xC0U)
02669   {
02670     hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
02671   }
02672   else
02673   {
02674     hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
02675   }
02676
02677   return HAL_MMC_ERROR_NONE;
02678 }
02679
02680 /**
02681   * @brief  Turns the SDMMC output signals off.
02682   * @param  hmmc: Pointer to MMC handle
02683   * @retval None
02684   */
02685 static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
02686 {
02687   /* Set Power State to OFF */
02688   (void)SDMMC_PowerState_OFF(hmmc->Instance);
02689 }
02690
02691 /**
02692   * @brief  Returns the current card's status.
02693   * @param  hmmc: Pointer to MMC handle
02694   * @param  pCardStatus: pointer to the buffer that will contain the MMC card
02695   *         status (Card Status register)
02696   * @retval error state
02697   */
02698 static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
02699 {
02700   uint32_t errorstate;
02701
02702   if(pCardStatus == NULL)
02703   {
02704     return HAL_MMC_ERROR_PARAM;
02705   }
02706
02707   /* Send Status command */
02708   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
02709   if(errorstate != HAL_MMC_ERROR_NONE)
02710   {
02711     return errorstate;
02712   }
02713
02714   /* Get MMC card status */
02715   *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02716
02717   return HAL_MMC_ERROR_NONE;
02718 }
02719
02720 /**
02721   * @brief  Reads extended CSD register to get the sectors number of the device
02722   * @param  hmmc: Pointer to MMC handle
02723   * @param  pFieldData: Pointer to the read buffer
02724   * @param  pFieldIndex: Index of the field to be read
02725   * @param  Timeout: Specify timeout value
02726   * @retval HAL status
02727   */
02728 HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
02729 {
02730   SDMMC_DataInitTypeDef config;
02731   uint32_t errorstate;
02732   uint32_t tickstart = HAL_GetTick();
02733   uint32_t count;
02734   uint32_t i = 0;
02735   uint32_t tmp_data;
02736
02737   hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
02738
02739   /* Initialize data control register */
02740   hmmc->Instance->DCTRL = 0;
02741
02742   /* Configure the MMC DPSM (Data Path State Machine) */
02743   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02744   config.DataLength    = 0;
02745   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
02746   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02747   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02748   config.DPSM          = SDMMC_DPSM_DISABLE;
02749   (void)SDMMC_ConfigData(hmmc->Instance, &config);
02750
02751   /* Set Block Size for Card */
02752   errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
02753   if(errorstate != HAL_MMC_ERROR_NONE)
02754   {
02755     /* Clear all the static flags */
02756     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02757     hmmc->ErrorCode |= errorstate;
02758     hmmc->State = HAL_MMC_STATE_READY;
02759     return HAL_ERROR;
02760   }
02761
02762   /* Configure the MMC DPSM (Data Path State Machine) */
02763   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02764   config.DataLength    = 512;
02765   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
02766   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02767   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02768   config.DPSM          = SDMMC_DPSM_ENABLE;
02769   (void)SDMMC_ConfigData(hmmc->Instance, &config);
02770
02771   /* Set Block Size for Card */
02772   errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
02773   if(errorstate != HAL_MMC_ERROR_NONE)
02774   {
02775     /* Clear all the static flags */
02776     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02777     hmmc->ErrorCode |= errorstate;
02778     hmmc->State = HAL_MMC_STATE_READY;
02779     return HAL_ERROR;
02780   }
02781
02782   /* Poll on SDMMC flags */
02783   while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
02784   {
02785     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
02786     {
02787       /* Read data from SDMMC Rx FIFO */
02788       for(count = 0U; count < 8U; count++)
02789       {
02790         tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
02791                 /* eg : SEC_COUNT   : FieldIndex = 212 => i+count = 53 */
02792                 /*      DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
02793         if ((i + count) == ((uint32_t)FieldIndex/4U))
02794         {
02795           *pFieldData = tmp_data;
02796         }
02797       }
02798       i += 8U;
02799     }
02800
02801     if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
02802     {
02803       /* Clear all the static flags */
02804       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02805       hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
02806       hmmc->State= HAL_MMC_STATE_READY;
02807       return HAL_TIMEOUT;
02808     }
02809   }
02810
02811   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02812   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
02813   if(errorstate != HAL_MMC_ERROR_NONE)
02814   {
02815     hmmc->ErrorCode |= errorstate;
02816   }
02817
02818   /* Clear all the static flags */
02819   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
02820
02821   hmmc->State = HAL_MMC_STATE_READY;
02822
02823   return HAL_OK;
02824 }
02825
02826 /**
02827   * @brief  Wrap up reading in non-blocking mode.
02828   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02829   *              the configuration information.
02830   * @retval None
02831   */
02832 static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
02833 {
02834   uint32_t count, data;
02835   uint8_t* tmp;
02836
02837   tmp = hmmc->pRxBuffPtr;
02838
02839   if (hmmc->RxXferSize >= 32U)
02840   {
02841     /* Read data from SDMMC Rx FIFO */
02842     for(count = 0U; count < 8U; count++)
02843     {
02844       data = SDMMC_ReadFIFO(hmmc->Instance);
02845       *tmp = (uint8_t)(data & 0xFFU);
02846       tmp++;
02847       *tmp = (uint8_t)((data >> 8U) & 0xFFU);
02848       tmp++;
02849       *tmp = (uint8_t)((data >> 16U) & 0xFFU);
02850       tmp++;
02851       *tmp = (uint8_t)((data >> 24U) & 0xFFU);
02852       tmp++;
02853     }
02854
02855     hmmc->pRxBuffPtr = tmp;
02856     hmmc->RxXferSize -= 32U;
02857   }
02858 }
02859
02860 /**
02861   * @brief  Wrap up writing in non-blocking mode.
02862   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02863   *              the configuration information.
02864   * @retval None
02865   */
02866 static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
02867 {
02868   uint32_t count, data;
02869   uint8_t* tmp;
02870
02871   tmp = hmmc->pTxBuffPtr;
02872
02873   if (hmmc->TxXferSize >= 32U)
02874   {
02875     /* Write data to SDMMC Tx FIFO */
02876     for(count = 0U; count < 8U; count++)
02877     {
02878       data = (uint32_t)(*tmp);
02879       tmp++;
02880       data |= ((uint32_t)(*tmp) << 8U);
02881       tmp++;
02882       data |= ((uint32_t)(*tmp) << 16U);
02883       tmp++;
02884       data |= ((uint32_t)(*tmp) << 24U);
02885       tmp++;
02886       (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
02887     }
02888
02889     hmmc->pTxBuffPtr = tmp;
02890     hmmc->TxXferSize -= 32U;
02891   }
02892 }
02893
02894 /**
02895   * @brief  Switches the MMC card to high speed mode.
02896   * @param  hmmc: MMC handle
02897   * @param  state: State of high speed mode
02898   * @retval MMC Card error state
02899   */
02900 static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
02901 {
02902   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02903   uint32_t response, count;
02904
02905   if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
02906   {
02907     /* Index : 185 - Value : 0 */
02908     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
02909   }
02910
02911   if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
02912   {
02913     /* Index : 185 - Value : 1 */
02914     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
02915   }
02916
02917   if(errorstate == HAL_MMC_ERROR_NONE)
02918   {
02919     /* Check for switch error */
02920     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02921     if(errorstate == HAL_MMC_ERROR_NONE)
02922     {
02923       /* Get command response */
02924       response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02925       if ((response & 0x80U) != 0U)
02926       {
02927         errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
02928       }
02929       else
02930       {
02931         /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02932         count = SDMMC_MAX_TRIAL;
02933         while(((response & 0x100U) == 0U) && (count != 0U))
02934         {
02935           count--;
02936
02937           errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
02938           if(errorstate != HAL_MMC_ERROR_NONE)
02939           {
02940             break;
02941           }
02942
02943           /* Get command response */
02944           response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02945         }
02946
02947         /* Configure high speed */
02948         if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
02949         {
02950           if (state == DISABLE)
02951           {
02952             CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
02953           }
02954           else
02955           {
02956             SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
02957           }
02958         }
02959       }
02960     }
02961   }
02962
02963   return errorstate;
02964 }
02965
02966 /**
02967   * @brief  Switches the MMC card to Double Data Rate (DDR) mode.
02968   * @param  hmmc: MMC handle
02969   * @param  state: State of DDR mode
02970   * @retval MMC Card error state
02971   */
02972 static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
02973 {
02974   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02975   uint32_t response, count;
02976
02977   if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
02978   {
02979     if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
02980     {
02981       /* Index : 183 - Value : 5 */
02982       errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
02983     }
02984     else
02985     {
02986       /* Index : 183 - Value : 6 */
02987       errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
02988     }
02989   }
02990
02991   if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
02992   {
02993     if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
02994     {
02995       /* Index : 183 - Value : 1 */
02996       errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
02997     }
02998     else
02999     {
03000       /* Index : 183 - Value : 2 */
03001       errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
03002     }
03003   }
03004
03005   if(errorstate == HAL_MMC_ERROR_NONE)
03006   {
03007     /* Check for switch error */
03008     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
03009     if(errorstate == HAL_MMC_ERROR_NONE)
03010     {
03011       /* Get command response */
03012       response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
03013       if ((response & 0x80U) != 0U)
03014       {
03015         errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
03016       }
03017       else
03018       {
03019         /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
03020         count = SDMMC_MAX_TRIAL;
03021         while(((response & 0x100U) == 0U) && (count != 0U))
03022         {
03023           count--;
03024
03025           errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
03026           if(errorstate != HAL_MMC_ERROR_NONE)
03027           {
03028             break;
03029           }
03030
03031           /* Get command response */
03032           response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
03033         }
03034
03035         /* Configure DDR mode */
03036         if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
03037         {
03038           if (state == DISABLE)
03039           {
03040             CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
03041           }
03042           else
03043           {
03044             SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
03045           }
03046         }
03047       }
03048     }
03049   }
03050
03051   return errorstate;
03052 }
03053
03054 /**
03055   * @brief Read DMA Buffer 0 Transfer completed callbacks
03056   * @param hmmc: MMC handle
03057   * @retval None
03058   */
03059 __weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
03060 {
03061   /* Prevent unused argument(s) compilation warning */
03062   UNUSED(hmmc);
03063
03064   /* NOTE : This function should not be modified, when the callback is needed,
03065             the HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
03066    */
03067 }
03068
03069 /**
03070   * @brief Read DMA Buffer 1 Transfer completed callbacks
03071   * @param hmmc: MMC handle
03072   * @retval None
03073   */
03074 __weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
03075 {
03076   /* Prevent unused argument(s) compilation warning */
03077   UNUSED(hmmc);
03078
03079   /* NOTE : This function should not be modified, when the callback is needed,
03080             the HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
03081    */
03082 }
03083
03084 /**
03085   * @brief Write DMA Buffer 0 Transfer completed callbacks
03086   * @param hmmc: MMC handle
03087   * @retval None
03088   */
03089 __weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
03090 {
03091   /* Prevent unused argument(s) compilation warning */
03092   UNUSED(hmmc);
03093
03094   /* NOTE : This function should not be modified, when the callback is needed,
03095             the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
03096    */
03097 }
03098
03099 /**
03100   * @brief Write DMA Buffer 1 Transfer completed callbacks
03101   * @param hmmc: MMC handle
03102   * @retval None
03103   */
03104 __weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
03105 {
03106   /* Prevent unused argument(s) compilation warning */
03107   UNUSED(hmmc);
03108
03109   /* NOTE : This function should not be modified, when the callback is needed,
03110             the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
03111    */
03112 }
03113
03114 /**
03115   * @}
03116   */
03117
03118 #endif /* HAL_MMC_MODULE_ENABLED */
03119
03120 /**
03121   * @}
03122   */
03123
03124 /**
03125   * @}
03126   */
03127
03128 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc.h Source File

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stm32h7xx_hal_mmc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of MMC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_MMC_H
00022 #define STM32H7xx_HAL_MMC_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_sdmmc.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup MMC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup MMC_Exported_Types MMC Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
00045   * @{
00046   */
00047 typedef enum
00048 {
00049   HAL_MMC_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< MMC not yet initialized or disabled  */
00050   HAL_MMC_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< MMC initialized and ready for use    */
00051   HAL_MMC_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< MMC Timeout state                    */
00052   HAL_MMC_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< MMC process ongoing                  */
00053   HAL_MMC_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< MMC Programming State                */
00054   HAL_MMC_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< MMC Receinving State                 */
00055   HAL_MMC_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< MMC Transfert State                  */
00056   HAL_MMC_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< MMC is in error state                */
00057 }HAL_MMC_StateTypeDef;
00058 /**
00059   * @}
00060   */
00061
00062 /** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
00063   * @{
00064   */
00065 typedef uint32_t HAL_MMC_CardStateTypeDef;
00066
00067 #define HAL_MMC_CARD_READY          0x00000001U  /*!< Card state is ready                     */
00068 #define HAL_MMC_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
00069 #define HAL_MMC_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
00070 #define HAL_MMC_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
00071 #define HAL_MMC_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
00072 #define HAL_MMC_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
00073 #define HAL_MMC_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
00074 #define HAL_MMC_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
00075 #define HAL_MMC_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
00081   * @{
00082   */
00083 #define MMC_InitTypeDef      SDMMC_InitTypeDef
00084 #define MMC_TypeDef          SDMMC_TypeDef
00085
00086 /**
00087   * @brief  MMC Card Information Structure definition
00088   */
00089 typedef struct
00090 {
00091   uint32_t CardType;                     /*!< Specifies the card Type                         */
00092
00093   uint32_t Class;                        /*!< Specifies the class of the card class           */
00094
00095   uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
00096
00097   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
00098
00099   uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
00100
00101   uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
00102
00103   uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
00104
00105 }HAL_MMC_CardInfoTypeDef;
00106
00107 /**
00108   * @brief  MMC handle Structure definition
00109   */
00110 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00111 typedef struct __MMC_HandleTypeDef
00112 #else
00113 typedef struct
00114 #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
00115 {
00116   MMC_TypeDef                  *Instance;        /*!< MMC registers base address           */
00117
00118   MMC_InitTypeDef              Init;             /*!< MMC required parameters              */
00119
00120   HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */
00121
00122   uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
00123
00124   uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */
00125
00126   uint8_t                      *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer    */
00127
00128   uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                 */
00129
00130   __IO uint32_t                Context;          /*!< MMC transfer context                 */
00131
00132   __IO HAL_MMC_StateTypeDef    State;            /*!< MMC card State                       */
00133
00134   __IO uint32_t                ErrorCode;        /*!< MMC Card Error codes                 */
00135
00136   HAL_MMC_CardInfoTypeDef      MmcCard;          /*!< MMC Card information                 */
00137
00138   uint32_t                     CSD[4U];          /*!< MMC card specific data table         */
00139
00140   uint32_t                     CID[4U];          /*!< MMC card identification number table */
00141
00142   uint32_t                     Ext_CSD[128];
00143
00144 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00145   void (* TxCpltCallback)                 (struct __MMC_HandleTypeDef *hmmc);
00146   void (* RxCpltCallback)                 (struct __MMC_HandleTypeDef *hmmc);
00147   void (* ErrorCallback)                  (struct __MMC_HandleTypeDef *hmmc);
00148   void (* AbortCpltCallback)              (struct __MMC_HandleTypeDef *hmmc);
00149   void (* Read_DMADblBuf0CpltCallback)    (struct __MMC_HandleTypeDef *hmmc);
00150   void (* Read_DMADblBuf1CpltCallback)    (struct __MMC_HandleTypeDef *hmmc);
00151   void (* Write_DMADblBuf0CpltCallback)   (struct __MMC_HandleTypeDef *hmmc);
00152   void (* Write_DMADblBuf1CpltCallback)   (struct __MMC_HandleTypeDef *hmmc);
00153
00154   void (* MspInitCallback)                (struct __MMC_HandleTypeDef *hmmc);
00155   void (* MspDeInitCallback)              (struct __MMC_HandleTypeDef *hmmc);
00156 #endif
00157 }MMC_HandleTypeDef;
00158
00159
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
00165   * @{
00166   */
00167 typedef struct
00168 {
00169   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00170   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00171   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00172   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00173   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00174   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00175   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00176   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00177   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00178   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00179   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00180   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00181   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00182   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00183   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00184   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00185   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00186   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00187   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00188   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00189   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00190   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00191   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00192   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00193   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00194   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00195   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00196   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00197   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00198   __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
00199   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00200   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00201   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00202   __IO uint8_t  FileFormat;           /*!< File format                           */
00203   __IO uint8_t  ECC;                  /*!< ECC code                              */
00204   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00205   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00206
00207 }HAL_MMC_CardCSDTypeDef;
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
00213   * @{
00214   */
00215 typedef struct
00216 {
00217   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00218   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00219   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00220   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00221   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00222   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00223   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00224   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00225   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00226   __IO uint8_t  Reserved2;       /*!< Always 1              */
00227
00228 }HAL_MMC_CardCIDTypeDef;
00229 /**
00230   * @}
00231   */
00232
00233 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00234 /** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
00235   * @{
00236   */
00237 typedef enum
00238 {
00239   HAL_MMC_TX_CPLT_CB_ID                 = 0x00U,  /*!< MMC Tx Complete Callback ID                     */
00240   HAL_MMC_RX_CPLT_CB_ID                 = 0x01U,  /*!< MMC Rx Complete Callback ID                     */
00241   HAL_MMC_ERROR_CB_ID                   = 0x02U,  /*!< MMC Error Callback ID                           */
00242   HAL_MMC_ABORT_CB_ID                   = 0x03U,  /*!< MMC Abort Callback ID                           */
00243   HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID  = 0x04U,  /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */
00244   HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID  = 0x05U,  /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */
00245   HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U,  /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */
00246   HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,  /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */
00247
00248   HAL_MMC_MSP_INIT_CB_ID                = 0x10U,  /*!< MMC MspInit Callback ID                         */
00249   HAL_MMC_MSP_DEINIT_CB_ID              = 0x11U   /*!< MMC MspDeInit Callback ID                       */
00250 }HAL_MMC_CallbackIDTypeDef;
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
00256   * @{
00257   */
00258 typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
00259 /**
00260   * @}
00261   */
00262 #endif
00263 /**
00264   * @}
00265   */
00266
00267 /* Exported constants --------------------------------------------------------*/
00268 /** @defgroup MMC_Exported_Constants Exported Constants
00269   * @{
00270   */
00271
00272 #define MMC_BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
00273
00274 /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
00275   * @{
00276   */
00277 #define HAL_MMC_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
00278 #define HAL_MMC_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
00279 #define HAL_MMC_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
00280 #define HAL_MMC_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
00281 #define HAL_MMC_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
00282 #define HAL_MMC_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
00283 #define HAL_MMC_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
00284 #define HAL_MMC_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
00285 #define HAL_MMC_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the
00286                                                                                         number of transferred bytes does not match the block length   */
00287 #define HAL_MMC_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
00288 #define HAL_MMC_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
00289 #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
00290 #define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock
00291                                                                                         command or if there was an attempt to access a locked card    */
00292 #define HAL_MMC_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
00293 #define HAL_MMC_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
00294 #define HAL_MMC_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
00295 #define HAL_MMC_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
00296 #define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
00297 #define HAL_MMC_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
00298 #define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
00299 #define HAL_MMC_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
00300 #define HAL_MMC_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
00301 #define HAL_MMC_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
00302 #define HAL_MMC_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out
00303                                                                                         of erase sequence command was received                        */
00304 #define HAL_MMC_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
00305 #define HAL_MMC_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */
00306 #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */
00307 #define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */
00308 #define HAL_MMC_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */
00309 #define HAL_MMC_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
00310 #define HAL_MMC_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */
00311 #define HAL_MMC_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
00312 #define HAL_MMC_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
00313
00314 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00315 #define HAL_MMC_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
00316 #endif
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
00322   * @{
00323   */
00324 #define   MMC_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
00325 #define   MMC_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
00326 #define   MMC_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
00327 #define   MMC_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
00328 #define   MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
00329 #define   MMC_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
00330 #define   MMC_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
00337   * @{
00338   */
00339 /**
00340   * @brief
00341   */
00342 #define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< VALUE OF ARGUMENT            */
00343 #define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< VALUE OF ARGUMENT            */
00344 #define eMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< for eMMC > 2Gb sector mode   */
00345 #define eMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< for eMMC > 2Gb sector mode   */
00346 #define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
00352   * @{
00353   */
00354 #define  MMC_LOW_CAPACITY_CARD     ((uint32_t)0x00000000U)   /*!< MMC Card Capacity <=2Gbytes   */
00355 #define  MMC_HIGH_CAPACITY_CARD    ((uint32_t)0x00000001U)   /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macro ------------------------------------------------------------*/
00366 /** @defgroup MMC_Exported_macros MMC Exported Macros
00367  *  @brief macros to handle interrupts and specific clock configurations
00368  * @{
00369  */
00370 /** @brief Reset MMC handle state.
00371   * @param  __HANDLE__ : MMC handle.
00372   * @retval None
00373   */
00374 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00375 #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00376                                                                (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
00377                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00378                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00379                                                              } while(0)
00380 #else
00381 #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
00382 #endif
00383
00384 /**
00385   * @brief  Enable the MMC device interrupt.
00386   * @param  __HANDLE__: MMC Handle
00387   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00388   *         This parameter can be one or a combination of the following values:
00389   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00390   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00391   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00392   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00393   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00394   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00395   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00396   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00397   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00398   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00399   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00400   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00401   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00402   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00403   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00404   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00405   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00406   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00407   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00408   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00409   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00410   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00411   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00412   * @retval None
00413   */
00414 #define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00415
00416 /**
00417   * @brief  Disable the MMC device interrupt.
00418   * @param  __HANDLE__: MMC Handle
00419   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00420   *          This parameter can be one or a combination of the following values:
00421   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00422   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00423   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00424   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00425   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00426   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00427   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00428   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00429   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00430   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00431   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00432   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00433   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00434   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00435   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00436   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00437   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00438   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00439   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00440   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00441   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00442   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00443   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00444   * @retval None
00445   */
00446 #define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00447
00448 /**
00449   * @brief  Check whether the specified MMC flag is set or not.
00450   * @param  __HANDLE__: MMC Handle
00451   * @param  __FLAG__: specifies the flag to check.
00452   *          This parameter can be one of the following values:
00453   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00454   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00455   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00456   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00457   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00458   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00459   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00460   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00461   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00462   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00463   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00464   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00465   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
00466   *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
00467   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
00468   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
00469   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
00470   *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
00471   *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
00472   *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
00473   *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00474   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00475   *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
00476   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00477   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00478   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00479   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00480   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00481   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00482   * @retval The new state of MMC FLAG (SET or RESET).
00483   */
00484 #define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00485
00486 /**
00487   * @brief  Clear the MMC's pending flags.
00488   * @param  __HANDLE__: MMC Handle
00489   * @param  __FLAG__: specifies the flag to clear.
00490   *          This parameter can be one or a combination of the following values:
00491   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00492   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00493   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00494   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00495   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00496   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00497   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00498   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00499   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00500   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00501   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00502   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00503   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00504   *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
00505   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00506   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00507   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00508   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00509   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00510   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00511   * @retval None
00512   */
00513 #define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00514
00515 /**
00516   * @brief  Check whether the specified MMC interrupt has occurred or not.
00517   * @param  __HANDLE__: MMC Handle
00518   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00519   *          This parameter can be one of the following values:
00520   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00521   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00522   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00523   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00524   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00525   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00526   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00527   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00528   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00529   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00530   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00531   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00532   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00533   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00534   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00535   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00536   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00537   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00538   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00539   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00540   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00541   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00542   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00543   * @retval The new state of MMC IT (SET or RESET).
00544   */
00545 #define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00546
00547 /**
00548   * @brief  Clear the MMC's interrupt pending bits.
00549   * @param  __HANDLE__: MMC Handle
00550   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00551   *          This parameter can be one or a combination of the following values:
00552   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00553   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00554   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00555   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00556   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00557   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00558   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00559   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00560   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00561   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00562   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00563   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00564   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00565   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00566   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00567   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00568   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00569   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00570   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00571   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00572   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00573   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00574   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00575   * @retval None
00576   */
00577 #define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00578
00579 /**
00580   * @}
00581   */
00582
00583 /* Include MMC HAL Extension module */
00584 #include "stm32h7xx_hal_mmc_ex.h"
00585
00586 /* Exported functions --------------------------------------------------------*/
00587 /** @defgroup MMC_Exported_Functions MMC Exported Functions
00588   * @{
00589   */
00590
00591 /** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
00592   * @{
00593   */
00594 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
00595 HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
00596 HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
00597 void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
00598 void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
00599
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
00605   * @{
00606   */
00607 /* Blocking mode: Polling */
00608 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00609 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00610 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
00611 /* Non-Blocking mode: IT */
00612 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00613 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00614 /* Non-Blocking mode: DMA */
00615 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00616 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00617
00618 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
00619
00620 /* Callback in non blocking modes (DMA) */
00621 void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
00622 void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
00623 void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
00624 void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
00625
00626 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
00627 /* MMC callback registering/unregistering */
00628 HAL_StatusTypeDef HAL_MMC_RegisterCallback  (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
00629 HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
00630 #endif
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
00636   * @{
00637   */
00638 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
00639 HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
00645   * @{
00646   */
00647 HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
00648 HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
00649 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
00650 HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
00651 /**
00652   * @}
00653   */
00654
00655 /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
00656   * @{
00657   */
00658 HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
00659 uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
00665   * @{
00666   */
00667 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
00668 HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
00669 /**
00670   * @}
00671   */
00672
00673 /* Private types -------------------------------------------------------------*/
00674 /** @defgroup MMC_Private_Types MMC Private Types
00675   * @{
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /* Private defines -----------------------------------------------------------*/
00683 /** @defgroup MMC_Private_Defines MMC Private Defines
00684   * @{
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /* Private variables ---------------------------------------------------------*/
00692 /** @defgroup MMC_Private_Variables MMC Private Variables
00693   * @{
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /* Private constants ---------------------------------------------------------*/
00701 /** @defgroup MMC_Private_Constants MMC Private Constants
00702   * @{
00703   */
00704
00705 /**
00706   * @}
00707   */
00708
00709 /* Private macros ------------------------------------------------------------*/
00710 /** @defgroup MMC_Private_Macros MMC Private Macros
00711   * @{
00712   */
00713
00714 /**
00715   * @}
00716   */
00717
00718 /* Private functions prototypes ----------------------------------------------*/
00719 /** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
00720   * @{
00721   */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /* Private functions ---------------------------------------------------------*/
00728 /** @defgroup MMC_Private_Functions MMC Private Functions
00729   * @{
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736
00737 /**
00738   * @}
00739   */
00740
00741 /**
00742   * @}
00743   */
00744
00745 /**
00746   * @}
00747   */
00748
00749 #ifdef __cplusplus
00750 }
00751 #endif
00752
00753
00754 #endif /* STM32H7xx_HAL_MMC_H */
00755
00756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc_ex.c Source File

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stm32h7xx_hal_mmc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   MMC card Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Secure Digital (MMC) peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015    The MMC Extension HAL driver can be used as follows:
00016    (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
00017
00018    (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00025   * All rights reserved.</center></h2>
00026   *
00027   * This software component is licensed by ST under BSD 3-Clause license,
00028   * the "License"; You may not use this file except in compliance with the
00029   * License. You may obtain a copy of the License at:
00030   *                       opensource.org/licenses/BSD-3-Clause
00031   *
00032   ******************************************************************************
00033   */
00034
00035 /* Includes ------------------------------------------------------------------*/
00036 #include "stm32h7xx_hal.h"
00037
00038 /** @addtogroup STM32H7xx_HAL_Driver
00039   * @{
00040   */
00041
00042 /** @defgroup MMCEx MMCEx
00043   * @brief MMC Extended HAL module driver
00044   * @{
00045   */
00046
00047 #ifdef HAL_MMC_MODULE_ENABLED
00048
00049 /* Private typedef -----------------------------------------------------------*/
00050 /* Private define ------------------------------------------------------------*/
00051 /* Private macro -------------------------------------------------------------*/
00052 /* Private variables ---------------------------------------------------------*/
00053 /* Private function prototypes -----------------------------------------------*/
00054 /* Private functions ---------------------------------------------------------*/
00055 /* Exported functions --------------------------------------------------------*/
00056 /** @addtogroup MMCEx_Exported_Functions
00057   * @{
00058   */
00059
00060 /** @addtogroup MMCEx_Exported_Functions_Group1
00061  *  @brief   Multibuffer functions
00062  *
00063 @verbatim
00064   ==============================================================================
00065           ##### Multibuffer functions #####
00066   ==============================================================================
00067   [..]
00068     This section provides functions allowing to configure the multibuffer mode and start read and write
00069     multibuffer mode for MMC HAL driver.
00070
00071 @endverbatim
00072   * @{
00073   */
00074
00075 /**
00076   * @brief  Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
00077   * @param  hmmc: MMC handle
00078   * @param  pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
00079   * @param  pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
00080   * @param  BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
00081   * @retval HAL status
00082   */
00083 HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
00084 {
00085   if(hmmc->State == HAL_MMC_STATE_READY)
00086   {
00087     hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
00088     hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
00089     hmmc->Instance->IDMABSIZE= (uint32_t) BufferSize;
00090
00091     return HAL_OK;
00092   }
00093   else
00094   {
00095     return HAL_BUSY;
00096   }
00097 }
00098
00099 /**
00100   * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
00101   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
00102   * @param  hmmc: MMC handle
00103   * @param  BlockAdd: Block Address from where data is to be read
00104   * @param  NumberOfBlocks: Total number of blocks to read
00105   * @retval HAL status
00106   */
00107 HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00108 {
00109   SDMMC_DataInitTypeDef config;
00110   uint32_t DmaBase0_reg, DmaBase1_reg;
00111   uint32_t errorstate;
00112   uint32_t add = BlockAdd;
00113
00114   if(hmmc->State == HAL_MMC_STATE_READY)
00115   {
00116     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00117     {
00118       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00119       return HAL_ERROR;
00120     }
00121
00122     DmaBase0_reg = hmmc->Instance->IDMABASE0;
00123     DmaBase1_reg = hmmc->Instance->IDMABASE1;
00124     if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
00125     {
00126       hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00127       return HAL_ERROR;
00128     }
00129
00130     /* Initialize data control register */
00131     hmmc->Instance->DCTRL = 0;
00132
00133     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00134     hmmc->State = HAL_MMC_STATE_BUSY;
00135
00136     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00137     {
00138       add *= 512U;
00139     }
00140
00141     /* Configure the MMC DPSM (Data Path State Machine) */
00142     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00143     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
00144     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00145     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00146     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00147     config.DPSM          = SDMMC_DPSM_DISABLE;
00148     (void)SDMMC_ConfigData(hmmc->Instance, &config);
00149
00150     hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
00151
00152     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00153
00154     hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00155
00156      __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00157
00158     /* Read Blocks in DMA mode */
00159     hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
00160
00161     /* Read Multi Block command */
00162     errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
00163     if(errorstate != HAL_MMC_ERROR_NONE)
00164     {
00165       hmmc->State = HAL_MMC_STATE_READY;
00166       hmmc->ErrorCode |= errorstate;
00167       return HAL_ERROR;
00168     }
00169
00170     return HAL_OK;
00171   }
00172   else
00173   {
00174     return HAL_BUSY;
00175   }
00176
00177 }
00178
00179 /**
00180   * @brief  Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
00181   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
00182   * @param  hmmc: MMC handle
00183   * @param  BlockAdd: Block Address from where data is to be read
00184   * @param  NumberOfBlocks: Total number of blocks to read
00185   * @retval HAL status
00186 */
00187 HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00188 {
00189   SDMMC_DataInitTypeDef config;
00190   uint32_t errorstate;
00191   uint32_t DmaBase0_reg, DmaBase1_reg;
00192   uint32_t add = BlockAdd;
00193
00194   if(hmmc->State == HAL_MMC_STATE_READY)
00195   {
00196     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00197     {
00198       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00199       return HAL_ERROR;
00200     }
00201
00202     DmaBase0_reg = hmmc->Instance->IDMABASE0;
00203     DmaBase1_reg = hmmc->Instance->IDMABASE1;
00204     if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
00205     {
00206       hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00207       return HAL_ERROR;
00208     }
00209
00210     /* Initialize data control register */
00211     hmmc->Instance->DCTRL = 0;
00212
00213     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00214
00215     hmmc->State = HAL_MMC_STATE_BUSY;
00216
00217     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00218     {
00219       add *= 512U;
00220     }
00221
00222     /* Configure the MMC DPSM (Data Path State Machine) */
00223     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00224     config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
00225     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00226     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00227     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00228     config.DPSM          = SDMMC_DPSM_DISABLE;
00229     (void)SDMMC_ConfigData(hmmc->Instance, &config);
00230
00231     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00232
00233     hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00234
00235     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00236
00237     /* Write Blocks in DMA mode */
00238     hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
00239
00240     /* Write Multi Block command */
00241     errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
00242     if(errorstate != HAL_MMC_ERROR_NONE)
00243     {
00244       hmmc->State = HAL_MMC_STATE_READY;
00245       hmmc->ErrorCode |= errorstate;
00246       return HAL_ERROR;
00247     }
00248
00249     return HAL_OK;
00250   }
00251   else
00252   {
00253     return HAL_BUSY;
00254   }
00255 }
00256
00257
00258 /**
00259   * @brief  Change the DMA Buffer0 or Buffer1 address on the fly.
00260   * @param  hmmc:           pointer to a MMC_HandleTypeDef structure.
00261   * @param  Buffer:        the buffer to be changed, This parameter can be one of
00262   *                        the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
00263   * @param  pDataBuffer:   The new address
00264   * @note   The BUFFER0 address can be changed only when the current transfer use
00265   *         BUFFER1 and the BUFFER1 address can be changed only when the current
00266   *         transfer use BUFFER0.
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
00270 {
00271   if(Buffer == MMC_DMA_BUFFER0)
00272   {
00273     /* change the buffer0 address */
00274     hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
00275   }
00276   else
00277   {
00278     /* change the memory1 address */
00279     hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
00280   }
00281
00282   return HAL_OK;
00283 }
00284
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 #endif /* HAL_MMC_MODULE_ENABLED */
00295
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_mmc_ex.h Source File

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stm32h7xx_hal_mmc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SD HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_MMC_EX_H
00022 #define STM32H7xx_HAL_MMC_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup MMCEx
00036   * @brief SD HAL extended module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup MMCEx_Exported_Types MMCEx Exported Types
00042   * @{
00043   */
00044
00045 /** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
00046   * @{
00047   */
00048 typedef enum
00049 {
00050   MMC_DMA_BUFFER0      = 0x00U,    /*!< selects MMC internal DMA Buffer 0     */
00051   MMC_DMA_BUFFER1      = 0x01U,    /*!< selects MMC internal DMA Buffer 1     */
00052
00053 }HAL_MMCEx_DMABuffer_MemoryTypeDef;
00054
00055
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063 /* Exported constants --------------------------------------------------------*/
00064 /* Exported macro ------------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
00067   * @{
00068   */
00069
00070 /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
00071   * @{
00072   */
00073 HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
00074 HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00075 HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00076 HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
00077
00078 void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
00079 void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
00080 void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
00081 void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
00082
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Private types -------------------------------------------------------------*/
00092 /* Private defines -----------------------------------------------------------*/
00093 /* Private variables ---------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /* Private macros ------------------------------------------------------------*/
00096 /* Private functions prototypes ----------------------------------------------*/
00097 /* Private functions ---------------------------------------------------------*/
00098
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106 #ifdef __cplusplus
00107 }
00108 #endif
00109
00110
00111 #endif /* STM32H7xx_HAL_MMCEx_H */
00112
00113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nand.c Source File

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stm32h7xx_hal_nand.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @brief   NAND HAL module driver.
00006   *          This file provides a generic firmware to drive NAND memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                          ##### How to use this driver #####
00012   ==============================================================================
00013     [..]
00014       This driver is a generic layered driver which contains a set of APIs used to
00015       control NAND flash memories. It uses the FMC layer functions to interface
00016       with NAND devices. This driver is used as follows:
00017
00018       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00019           with control and timing parameters for both common and attribute spaces.
00020
00021       (+) Read NAND flash memory maker and device IDs using the function
00022           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00023           structure declared by the function caller.
00024
00025       (+) Access NAND flash memory by read/write operations using the functions
00026           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
00027           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
00028           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
00029           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
00030           to read/write page(s)/spare area(s). These functions use specific device
00031           information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
00032           structure. The read/write address information is contained by the Nand_Address_Typedef
00033           structure passed as parameter.
00034
00035       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00036
00037       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00038           The erase block address information is contained in the Nand_Address_Typedef
00039           structure passed as parameter.
00040
00041       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00042
00043       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00044           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00045           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00046
00047       (+) You can monitor the NAND device HAL state by calling the function
00048           HAL_NAND_GetState()
00049
00050     [..]
00051       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00052           If a NAND flash device contains different operations and/or implementations,
00053           it should be implemented separately.
00054
00055     *** Callback registration ***
00056     =============================================
00057     [..]
00058       The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
00059       allows the user to configure dynamically the driver callbacks.
00060
00061       Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
00062       it allows to register following callbacks:
00063         (+) MspInitCallback    : NAND MspInit.
00064         (+) MspDeInitCallback  : NAND MspDeInit.
00065       This function takes as parameters the HAL peripheral handle, the Callback ID
00066       and a pointer to the user callback function.
00067
00068       Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
00069       weak (surcharged) function. It allows to reset following callbacks:
00070         (+) MspInitCallback    : NAND MspInit.
00071         (+) MspDeInitCallback  : NAND MspDeInit.
00072       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00073
00074       By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
00075       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00076       Exception done for MspInit and MspDeInit callbacks that are respectively
00077       reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
00078       and @ref  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
00079       If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
00080       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00081
00082       Callbacks can be registered/unregistered in READY state only.
00083       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00084       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00085       during the Init/DeInit.
00086       In that case first register the MspInit/MspDeInit user callbacks
00087       using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
00088       or @ref HAL_NAND_Init function.
00089
00090       When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
00091       not defined, the callback registering feature is not available
00092       and weak (surcharged) callbacks are used.
00093
00094   @endverbatim
00095   ******************************************************************************
00096   * @attention
00097   *
00098   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00099   *
00100   * This software component is licensed by ST under BSD 3-Clause license,
00101   * the "License"; You may not use this file except in compliance with the
00102   * License. You may obtain a copy of the License at:
00103   *                       opensource.org/licenses/BSD-3-Clause
00104   *
00105   ******************************************************************************
00106   */
00107
00108 /* Includes ------------------------------------------------------------------*/
00109 #include "stm32h7xx_hal.h"
00110
00111
00112 /** @addtogroup STM32H7xx_HAL_Driver
00113   * @{
00114   */
00115
00116 #ifdef HAL_NAND_MODULE_ENABLED
00117
00118 /** @defgroup NAND NAND
00119   * @brief NAND HAL module driver
00120   * @{
00121   */
00122
00123 /* Private typedef -----------------------------------------------------------*/
00124 /* Private Constants ------------------------------------------------------------*/
00125 /* Private macro -------------------------------------------------------------*/
00126 /* Private variables ---------------------------------------------------------*/
00127 /* Private function prototypes -----------------------------------------------*/
00128 /* Exported functions ---------------------------------------------------------*/
00129
00130 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00131   * @{
00132   */
00133
00134 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00135   * @brief    Initialization and Configuration functions
00136   *
00137   @verbatim
00138   ==============================================================================
00139             ##### NAND Initialization and de-initialization functions #####
00140   ==============================================================================
00141   [..]
00142     This section provides functions allowing to initialize/de-initialize
00143     the NAND memory
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  Perform NAND memory Initialization sequence
00151   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00152   *                the configuration information for NAND module.
00153   * @param  ComSpace_Timing pointer to Common space timing structure
00154   * @param  AttSpace_Timing pointer to Attribute space timing structure
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00158 {
00159   /* Check the NAND handle state */
00160   if (hnand == NULL)
00161   {
00162     return HAL_ERROR;
00163   }
00164
00165   if (hnand->State == HAL_NAND_STATE_RESET)
00166   {
00167     /* Allocate lock resource and initialize it */
00168     hnand->Lock = HAL_UNLOCKED;
00169
00170 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00171     if(hnand->MspInitCallback == NULL)
00172     {
00173       hnand->MspInitCallback = HAL_NAND_MspInit;
00174     }
00175     hnand->ItCallback = HAL_NAND_ITCallback;
00176
00177     /* Init the low level hardware */
00178     hnand->MspInitCallback(hnand);
00179 #else
00180     /* Initialize the low level hardware (MSP) */
00181     HAL_NAND_MspInit(hnand);
00182 #endif
00183   }
00184
00185   /* Initialize NAND control Interface */
00186   (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00187
00188   /* Initialize NAND common space timing Interface */
00189   (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00190
00191   /* Initialize NAND attribute space timing Interface */
00192   (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00193
00194   /* Enable the NAND device */
00195   __FMC_NAND_ENABLE(hnand->Instance);
00196
00197   /* Enable FMC Peripheral */
00198   __FMC_ENABLE();
00199   /* Update the NAND controller state */
00200   hnand->State = HAL_NAND_STATE_READY;
00201
00202   return HAL_OK;
00203 }
00204
00205 /**
00206   * @brief  Perform NAND memory De-Initialization sequence
00207   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00208   *                the configuration information for NAND module.
00209   * @retval HAL status
00210   */
00211 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00212 {
00213 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00214   if(hnand->MspDeInitCallback == NULL)
00215   {
00216     hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
00217   }
00218
00219   /* DeInit the low level hardware */
00220   hnand->MspDeInitCallback(hnand);
00221 #else
00222   /* Initialize the low level hardware (MSP) */
00223   HAL_NAND_MspDeInit(hnand);
00224 #endif
00225
00226   /* Configure the NAND registers with their reset values */
00227   (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00228
00229   /* Reset the NAND controller state */
00230   hnand->State = HAL_NAND_STATE_RESET;
00231
00232   /* Release Lock */
00233   __HAL_UNLOCK(hnand);
00234
00235   return HAL_OK;
00236 }
00237
00238 /**
00239   * @brief  NAND MSP Init
00240   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00241   *                the configuration information for NAND module.
00242   * @retval None
00243   */
00244 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00245 {
00246   /* Prevent unused argument(s) compilation warning */
00247   UNUSED(hnand);
00248
00249   /* NOTE : This function Should not be modified, when the callback is needed,
00250             the HAL_NAND_MspInit could be implemented in the user file
00251    */
00252 }
00253
00254 /**
00255   * @brief  NAND MSP DeInit
00256   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00257   *                the configuration information for NAND module.
00258   * @retval None
00259   */
00260 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00261 {
00262   /* Prevent unused argument(s) compilation warning */
00263   UNUSED(hnand);
00264
00265   /* NOTE : This function Should not be modified, when the callback is needed,
00266             the HAL_NAND_MspDeInit could be implemented in the user file
00267    */
00268 }
00269
00270
00271 /**
00272   * @brief  This function handles NAND device interrupt request.
00273   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00274   *                the configuration information for NAND module.
00275   * @retval HAL status
00276 */
00277 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00278 {
00279   /* Check NAND interrupt Rising edge flag */
00280   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00281   {
00282     /* NAND interrupt callback*/
00283 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00284     hnand->ItCallback(hnand);
00285 #else
00286     HAL_NAND_ITCallback(hnand);
00287 #endif
00288
00289     /* Clear NAND interrupt Rising edge pending bit */
00290     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
00291   }
00292
00293   /* Check NAND interrupt Level flag */
00294   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00295   {
00296     /* NAND interrupt callback*/
00297 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00298     hnand->ItCallback(hnand);
00299 #else
00300     HAL_NAND_ITCallback(hnand);
00301 #endif
00302
00303     /* Clear NAND interrupt Level pending bit */
00304     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
00305   }
00306
00307   /* Check NAND interrupt Falling edge flag */
00308   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00309   {
00310     /* NAND interrupt callback*/
00311 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00312     hnand->ItCallback(hnand);
00313 #else
00314     HAL_NAND_ITCallback(hnand);
00315 #endif
00316
00317     /* Clear NAND interrupt Falling edge pending bit */
00318     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
00319   }
00320
00321   /* Check NAND interrupt FIFO empty flag */
00322   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00323   {
00324     /* NAND interrupt callback*/
00325 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00326     hnand->ItCallback(hnand);
00327 #else
00328     HAL_NAND_ITCallback(hnand);
00329 #endif
00330
00331     /* Clear NAND interrupt FIFO empty pending bit */
00332     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
00333   }
00334
00335 }
00336
00337 /**
00338   * @brief  NAND interrupt feature callback
00339   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00340   *                the configuration information for NAND module.
00341   * @retval None
00342   */
00343 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00344 {
00345   /* Prevent unused argument(s) compilation warning */
00346   UNUSED(hnand);
00347
00348   /* NOTE : This function Should not be modified, when the callback is needed,
00349             the HAL_NAND_ITCallback could be implemented in the user file
00350    */
00351 }
00352
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00358   * @brief    Input Output and memory control functions
00359   *
00360   @verbatim
00361   ==============================================================================
00362                     ##### NAND Input and Output functions #####
00363   ==============================================================================
00364   [..]
00365     This section provides functions allowing to use and control the NAND
00366     memory
00367
00368 @endverbatim
00369   * @{
00370   */
00371
00372 /**
00373   * @brief  Read the NAND memory electronic signature
00374   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00375   *                the configuration information for NAND module.
00376   * @param  pNAND_ID NAND ID structure
00377   * @retval HAL status
00378   */
00379 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00380 {
00381   __IO uint32_t data = 0;
00382   __IO uint32_t data1 = 0;
00383   uint32_t deviceAddress;
00384
00385   /* Check the NAND controller state */
00386   if (hnand->State == HAL_NAND_STATE_BUSY)
00387   {
00388     return HAL_BUSY;
00389   }
00390   else if (hnand->State == HAL_NAND_STATE_READY)
00391   {
00392     /* Process Locked */
00393     __HAL_LOCK(hnand);
00394
00395     /* Update the NAND controller state */
00396     hnand->State = HAL_NAND_STATE_BUSY;
00397
00398     /* Identify the device address */
00399     deviceAddress = NAND_DEVICE;
00400
00401     /* Send Read ID command sequence */
00402     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_READID;
00403     __DSB();
00404     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00405     __DSB();
00406
00407     /* Read the electronic signature from NAND flash */
00408     if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
00409     {
00410       data = *(__IO uint32_t *)deviceAddress;
00411
00412       /* Return the data read */
00413       pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00414       pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00415       pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00416       pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00417     }
00418     else
00419     {
00420       data = *(__IO uint32_t *)deviceAddress;
00421       data1 = *((__IO uint32_t *)deviceAddress + 4);
00422
00423       /* Return the data read */
00424       pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00425       pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
00426       pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
00427       pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
00428     }
00429
00430     /* Update the NAND controller state */
00431     hnand->State = HAL_NAND_STATE_READY;
00432
00433     /* Process unlocked */
00434     __HAL_UNLOCK(hnand);
00435   }
00436   else
00437   {
00438     return HAL_ERROR;
00439   }
00440
00441   return HAL_OK;
00442 }
00443
00444 /**
00445   * @brief  NAND memory reset
00446   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00447   *                the configuration information for NAND module.
00448   * @retval HAL status
00449   */
00450 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00451 {
00452   uint32_t deviceAddress;
00453
00454   /* Check the NAND controller state */
00455   if (hnand->State == HAL_NAND_STATE_BUSY)
00456   {
00457     return HAL_BUSY;
00458   }
00459   else if (hnand->State == HAL_NAND_STATE_READY)
00460   {
00461     /* Process Locked */
00462     __HAL_LOCK(hnand);
00463
00464     /* Update the NAND controller state */
00465     hnand->State = HAL_NAND_STATE_BUSY;
00466
00467     /* Identify the device address */
00468     deviceAddress = NAND_DEVICE;
00469
00470     /* Send NAND reset command */
00471     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
00472
00473     /* Update the NAND controller state */
00474     hnand->State = HAL_NAND_STATE_READY;
00475
00476     /* Process unlocked */
00477     __HAL_UNLOCK(hnand);
00478   }
00479   else
00480   {
00481     return HAL_ERROR;
00482   }
00483
00484   return HAL_OK;
00485
00486 }
00487
00488 /**
00489   * @brief  Configure the device: Enter the physical parameters of the device
00490   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00491   *                the configuration information for NAND module.
00492   * @param  pDeviceConfig  pointer to NAND_DeviceConfigTypeDef structure
00493   * @retval HAL status
00494   */
00495 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
00496 {
00497   hnand->Config.PageSize           = pDeviceConfig->PageSize;
00498   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
00499   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
00500   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
00501   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
00502   hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
00503   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
00504
00505   return HAL_OK;
00506 }
00507
00508
00509 /**
00510   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
00511   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00512   *                the configuration information for NAND module.
00513   * @param  pAddress  pointer to NAND address structure
00514   * @param  pBuffer  pointer to destination read buffer
00515   * @param  NumPageToRead  number of pages to read from block
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00519 {
00520   uint32_t index;
00521   uint32_t tickstart;
00522   uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
00523   uint8_t * buff = pBuffer;
00524
00525   /* Check the NAND controller state */
00526   if (hnand->State == HAL_NAND_STATE_BUSY)
00527   {
00528     return HAL_BUSY;
00529   }
00530   else if (hnand->State == HAL_NAND_STATE_READY)
00531   {
00532     /* Process Locked */
00533     __HAL_LOCK(hnand);
00534
00535     /* Update the NAND controller state */
00536     hnand->State = HAL_NAND_STATE_BUSY;
00537
00538     /* Identify the device address */
00539     deviceAddress = NAND_DEVICE;
00540
00541     /* NAND raw address calculation */
00542     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00543
00544     /* Page(s) read loop */
00545     while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00546     {
00547       /* Send read page command sequence */
00548       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00549       __DSB();
00550
00551       /* Cards with page size <= 512 bytes */
00552       if ((hnand->Config.PageSize) <= 512U)
00553       {
00554         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00555         {
00556           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00557           __DSB();
00558           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00559           __DSB();
00560           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00561           __DSB();
00562         }
00563         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00564         {
00565           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00566           __DSB();
00567           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00568           __DSB();
00569           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00570           __DSB();
00571           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00572           __DSB();
00573         }
00574       }
00575       else /* (hnand->Config.PageSize) > 512 */
00576       {
00577         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00578         {
00579           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00580           __DSB();
00581           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00582           __DSB();
00583           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00584           __DSB();
00585           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00586           __DSB();
00587         }
00588         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00589         {
00590           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00591           __DSB();
00592           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00593           __DSB();
00594           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00595           __DSB();
00596           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00597           __DSB();
00598           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00599           __DSB();
00600         }
00601       }
00602
00603       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00604       __DSB();
00605
00606
00607       if (hnand->Config.ExtraCommandEnable == ENABLE)
00608       {
00609         /* Get tick */
00610         tickstart = HAL_GetTick();
00611
00612         /* Read status until NAND is ready */
00613         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00614         {
00615           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00616           {
00617             /* Update the NAND controller state */
00618             hnand->State = HAL_NAND_STATE_ERROR;
00619
00620             /* Process unlocked */
00621             __HAL_UNLOCK(hnand);
00622
00623             return HAL_TIMEOUT;
00624           }
00625         }
00626
00627         /* Go back to read mode */
00628         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
00629         __DSB();
00630       }
00631
00632       /* Get Data into Buffer */
00633       for (index = 0U; index < hnand->Config.PageSize; index++)
00634       {
00635         *buff = *(uint8_t *)deviceAddress;
00636         buff++;
00637       }
00638
00639       /* Increment read pages number */
00640       numPagesRead++;
00641
00642       /* Decrement pages to read */
00643       nbpages--;
00644
00645       /* Increment the NAND address */
00646       nandAddress = (uint32_t)(nandAddress + 1U);
00647     }
00648
00649     /* Update the NAND controller state */
00650     hnand->State = HAL_NAND_STATE_READY;
00651
00652     /* Process unlocked */
00653     __HAL_UNLOCK(hnand);
00654   }
00655   else
00656   {
00657     return HAL_ERROR;
00658   }
00659
00660   return HAL_OK;
00661
00662 }
00663
00664 /**
00665   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
00666   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00667   *                the configuration information for NAND module.
00668   * @param  pAddress  pointer to NAND address structure
00669   * @param  pBuffer  pointer to destination read buffer. pBuffer should be 16bits aligned
00670   * @param  NumPageToRead  number of pages to read from block
00671   * @retval HAL status
00672   */
00673 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
00674 {
00675   uint32_t index;
00676   uint32_t tickstart;
00677   uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
00678   uint16_t * buff = pBuffer;
00679
00680   /* Check the NAND controller state */
00681   if (hnand->State == HAL_NAND_STATE_BUSY)
00682   {
00683     return HAL_BUSY;
00684   }
00685   else if (hnand->State == HAL_NAND_STATE_READY)
00686   {
00687     /* Process Locked */
00688     __HAL_LOCK(hnand);
00689
00690     /* Update the NAND controller state */
00691     hnand->State = HAL_NAND_STATE_BUSY;
00692
00693     /* Identify the device address */
00694     deviceAddress = NAND_DEVICE;
00695
00696     /* NAND raw address calculation */
00697     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00698
00699     /* Page(s) read loop */
00700     while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00701     {
00702       /* Send read page command sequence */
00703       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00704       __DSB();
00705
00706       /* Cards with page size <= 512 bytes */
00707       if ((hnand->Config.PageSize) <= 512U)
00708       {
00709         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00710         {
00711           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00712           __DSB();
00713           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00714           __DSB();
00715           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00716           __DSB();
00717         }
00718         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00719         {
00720           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00721           __DSB();
00722           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00723           __DSB();
00724           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00725           __DSB();
00726           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00727           __DSB();
00728         }
00729       }
00730       else /* (hnand->Config.PageSize) > 512 */
00731       {
00732         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00733         {
00734           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00735           __DSB();
00736           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00737           __DSB();
00738           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00739           __DSB();
00740           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00741           __DSB();
00742         }
00743         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00744         {
00745           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00746           __DSB();
00747           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00748           __DSB();
00749           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00750           __DSB();
00751           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00752           __DSB();
00753           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00754           __DSB();
00755         }
00756       }
00757
00758       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00759       __DSB();
00760
00761       if (hnand->Config.ExtraCommandEnable == ENABLE)
00762       {
00763         /* Get tick */
00764         tickstart = HAL_GetTick();
00765
00766         /* Read status until NAND is ready */
00767         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00768         {
00769           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00770           {
00771             /* Update the NAND controller state */
00772             hnand->State = HAL_NAND_STATE_ERROR;
00773
00774             /* Process unlocked */
00775             __HAL_UNLOCK(hnand);
00776
00777             return HAL_TIMEOUT;
00778           }
00779         }
00780
00781         /* Go back to read mode */
00782         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
00783         __DSB();
00784       }
00785
00786       /* Get Data into Buffer */
00787       for (index = 0U; index < hnand->Config.PageSize; index++)
00788       {
00789         *buff = *(uint16_t *)deviceAddress;
00790         buff++;
00791       }
00792
00793       /* Increment read pages number */
00794       numPagesRead++;
00795
00796       /* Decrement pages to read */
00797       nbpages--;
00798
00799       /* Increment the NAND address */
00800       nandAddress = (uint32_t)(nandAddress + 1U);
00801     }
00802
00803     /* Update the NAND controller state */
00804     hnand->State = HAL_NAND_STATE_READY;
00805
00806     /* Process unlocked */
00807     __HAL_UNLOCK(hnand);
00808   }
00809   else
00810   {
00811     return HAL_ERROR;
00812   }
00813
00814   return HAL_OK;
00815 }
00816
00817 /**
00818   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
00819   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00820   *                the configuration information for NAND module.
00821   * @param  pAddress  pointer to NAND address structure
00822   * @param  pBuffer  pointer to source buffer to write
00823   * @param  NumPageToWrite   number of pages to write to block
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00827 {
00828   uint32_t index;
00829   uint32_t tickstart;
00830   uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
00831   uint8_t * buff = pBuffer;
00832
00833   /* Check the NAND controller state */
00834   if (hnand->State == HAL_NAND_STATE_BUSY)
00835   {
00836     return HAL_BUSY;
00837   }
00838   else if (hnand->State == HAL_NAND_STATE_READY)
00839   {
00840     /* Process Locked */
00841     __HAL_LOCK(hnand);
00842
00843     /* Update the NAND controller state */
00844     hnand->State = HAL_NAND_STATE_BUSY;
00845
00846     /* Identify the device address */
00847     deviceAddress = NAND_DEVICE;
00848
00849     /* NAND raw address calculation */
00850     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00851
00852     /* Page(s) write loop */
00853     while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00854     {
00855       /* Send write page command sequence */
00856       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00857       __DSB();
00858       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
00859       __DSB();
00860
00861       /* Cards with page size <= 512 bytes */
00862       if ((hnand->Config.PageSize) <= 512U)
00863       {
00864         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00865         {
00866           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00867           __DSB();
00868           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00869           __DSB();
00870           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00871           __DSB();
00872         }
00873         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00874         {
00875           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00876           __DSB();
00877           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00878           __DSB();
00879           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00880           __DSB();
00881           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00882           __DSB();
00883         }
00884       }
00885       else /* (hnand->Config.PageSize) > 512 */
00886       {
00887         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00888         {
00889           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00890           __DSB();
00891           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00892           __DSB();
00893           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00894           __DSB();
00895           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00896           __DSB();
00897         }
00898         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00899         {
00900           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00901           __DSB();
00902           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
00903           __DSB();
00904           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00905           __DSB();
00906           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00907           __DSB();
00908           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00909           __DSB();
00910         }
00911       }
00912
00913       /* Write data to memory */
00914       for (index = 0U; index < hnand->Config.PageSize; index++)
00915       {
00916         *(__IO uint8_t *)deviceAddress = *buff;
00917         buff++;
00918         __DSB();
00919       }
00920
00921       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00922       __DSB();
00923
00924       /* Get tick */
00925       tickstart = HAL_GetTick();
00926
00927       /* Read status until NAND is ready */
00928       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00929       {
00930         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00931         {
00932           /* Update the NAND controller state */
00933           hnand->State = HAL_NAND_STATE_ERROR;
00934
00935           /* Process unlocked */
00936           __HAL_UNLOCK(hnand);
00937
00938           return HAL_TIMEOUT;
00939         }
00940       }
00941
00942       /* Increment written pages number */
00943       numPagesWritten++;
00944
00945       /* Decrement pages to write */
00946       nbpages--;
00947
00948       /* Increment the NAND address */
00949       nandAddress = (uint32_t)(nandAddress + 1U);
00950     }
00951
00952     /* Update the NAND controller state */
00953     hnand->State = HAL_NAND_STATE_READY;
00954
00955     /* Process unlocked */
00956     __HAL_UNLOCK(hnand);
00957   }
00958   else
00959   {
00960     return HAL_ERROR;
00961   }
00962
00963   return HAL_OK;
00964 }
00965
00966 /**
00967   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
00968   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00969   *                the configuration information for NAND module.
00970   * @param  pAddress  pointer to NAND address structure
00971   * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned
00972   * @param  NumPageToWrite   number of pages to write to block
00973   * @retval HAL status
00974   */
00975 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
00976 {
00977   uint32_t index;
00978   uint32_t tickstart;
00979   uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
00980   uint16_t * buff = pBuffer;
00981
00982   /* Check the NAND controller state */
00983   if (hnand->State == HAL_NAND_STATE_BUSY)
00984   {
00985     return HAL_BUSY;
00986   }
00987   else if (hnand->State == HAL_NAND_STATE_READY)
00988   {
00989     /* Process Locked */
00990     __HAL_LOCK(hnand);
00991
00992     /* Update the NAND controller state */
00993     hnand->State = HAL_NAND_STATE_BUSY;
00994
00995     /* Identify the device address */
00996     deviceAddress = NAND_DEVICE;
00997
00998     /* NAND raw address calculation */
00999     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01000
01001     /* Page(s) write loop */
01002     while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01003     {
01004       /* Send write page command sequence */
01005       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01006       __DSB();
01007       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01008       __DSB();
01009
01010       /* Cards with page size <= 512 bytes */
01011       if ((hnand->Config.PageSize) <= 512U)
01012       {
01013         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01014         {
01015           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01016           __DSB();
01017           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01018           __DSB();
01019           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01020           __DSB();
01021         }
01022         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01023         {
01024           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01025           __DSB();
01026           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01027           __DSB();
01028           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01029           __DSB();
01030           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01031           __DSB();
01032         }
01033       }
01034       else /* (hnand->Config.PageSize) > 512 */
01035       {
01036         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01037         {
01038           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01039           __DSB();
01040           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01041           __DSB();
01042           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01043           __DSB();
01044           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01045           __DSB();
01046         }
01047         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01048         {
01049           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01050           __DSB();
01051           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01052           __DSB();
01053           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01054           __DSB();
01055           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01056           __DSB();
01057           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01058           __DSB();
01059         }
01060       }
01061
01062       /* Write data to memory */
01063       for (index = 0U; index < hnand->Config.PageSize; index++)
01064       {
01065         *(__IO uint16_t *)deviceAddress = *buff;
01066         buff++;
01067         __DSB();
01068       }
01069
01070       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01071       __DSB();
01072
01073       /* Get tick */
01074       tickstart = HAL_GetTick();
01075
01076       /* Read status until NAND is ready */
01077       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01078       {
01079         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01080         {
01081           /* Update the NAND controller state */
01082           hnand->State = HAL_NAND_STATE_ERROR;
01083
01084           /* Process unlocked */
01085           __HAL_UNLOCK(hnand);
01086
01087           return HAL_TIMEOUT;
01088         }
01089       }
01090
01091       /* Increment written pages number */
01092       numPagesWritten++;
01093
01094       /* Decrement pages to write */
01095       nbpages--;
01096
01097       /* Increment the NAND address */
01098       nandAddress = (uint32_t)(nandAddress + 1U);
01099     }
01100
01101     /* Update the NAND controller state */
01102     hnand->State = HAL_NAND_STATE_READY;
01103
01104     /* Process unlocked */
01105     __HAL_UNLOCK(hnand);
01106   }
01107   else
01108   {
01109     return HAL_ERROR;
01110   }
01111
01112   return HAL_OK;
01113 }
01114
01115 /**
01116   * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
01117   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01118   *                the configuration information for NAND module.
01119   * @param  pAddress  pointer to NAND address structure
01120   * @param  pBuffer pointer to source buffer to write
01121   * @param  NumSpareAreaToRead Number of spare area to read
01122   * @retval HAL status
01123 */
01124 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
01125 {
01126   uint32_t index;
01127   uint32_t tickstart;
01128   uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
01129   uint8_t * buff = pBuffer;
01130
01131   /* Check the NAND controller state */
01132   if (hnand->State == HAL_NAND_STATE_BUSY)
01133   {
01134     return HAL_BUSY;
01135   }
01136   else if (hnand->State == HAL_NAND_STATE_READY)
01137   {
01138     /* Process Locked */
01139     __HAL_LOCK(hnand);
01140
01141     /* Update the NAND controller state */
01142     hnand->State = HAL_NAND_STATE_BUSY;
01143
01144     /* Identify the device address */
01145     deviceAddress = NAND_DEVICE;
01146
01147     /* NAND raw address calculation */
01148     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01149
01150     /* Column in page address */
01151     columnAddress = COLUMN_ADDRESS(hnand);
01152
01153     /* Spare area(s) read loop */
01154     while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01155     {
01156       /* Cards with page size <= 512 bytes */
01157       if ((hnand->Config.PageSize) <= 512U)
01158       {
01159         /* Send read spare area command sequence */
01160         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01161         __DSB();
01162
01163         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01164         {
01165           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01166           __DSB();
01167           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01168           __DSB();
01169           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01170           __DSB();
01171         }
01172         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01173         {
01174           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01175           __DSB();
01176           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01177           __DSB();
01178           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01179           __DSB();
01180           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01181           __DSB();
01182         }
01183       }
01184       else /* (hnand->Config.PageSize) > 512 */
01185       {
01186         /* Send read spare area command sequence */
01187         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01188         __DSB();
01189
01190         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01191         {
01192           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01193           __DSB();
01194           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01195           __DSB();
01196           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01197           __DSB();
01198           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01199           __DSB();
01200         }
01201         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01202         {
01203           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01204           __DSB();
01205           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01206           __DSB();
01207           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01208           __DSB();
01209           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01210           __DSB();
01211           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01212           __DSB();
01213         }
01214       }
01215
01216       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01217       __DSB();
01218
01219       if (hnand->Config.ExtraCommandEnable == ENABLE)
01220       {
01221         /* Get tick */
01222         tickstart = HAL_GetTick();
01223
01224         /* Read status until NAND is ready */
01225         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01226         {
01227           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01228           {
01229             /* Update the NAND controller state */
01230             hnand->State = HAL_NAND_STATE_ERROR;
01231
01232             /* Process unlocked */
01233             __HAL_UNLOCK(hnand);
01234
01235             return HAL_TIMEOUT;
01236           }
01237         }
01238
01239         /* Go back to read mode */
01240         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
01241         __DSB();
01242       }
01243
01244       /* Get Data into Buffer */
01245       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01246       {
01247         *buff = *(uint8_t *)deviceAddress;
01248         buff++;
01249       }
01250
01251       /* Increment read spare areas number */
01252       numSpareAreaRead++;
01253
01254       /* Decrement spare areas to read */
01255       nbspare--;
01256
01257       /* Increment the NAND address */
01258       nandAddress = (uint32_t)(nandAddress + 1U);
01259     }
01260
01261     /* Update the NAND controller state */
01262     hnand->State = HAL_NAND_STATE_READY;
01263
01264     /* Process unlocked */
01265     __HAL_UNLOCK(hnand);
01266   }
01267   else
01268   {
01269     return HAL_ERROR;
01270   }
01271
01272   return HAL_OK;
01273 }
01274
01275 /**
01276   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
01277   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01278   *                the configuration information for NAND module.
01279   * @param  pAddress  pointer to NAND address structure
01280   * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
01281   * @param  NumSpareAreaToRead Number of spare area to read
01282   * @retval HAL status
01283 */
01284 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
01285 {
01286   uint32_t index;
01287   uint32_t tickstart;
01288   uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
01289   uint16_t * buff = pBuffer;
01290
01291   /* Check the NAND controller state */
01292   if (hnand->State == HAL_NAND_STATE_BUSY)
01293   {
01294     return HAL_BUSY;
01295   }
01296   else if (hnand->State == HAL_NAND_STATE_READY)
01297   {
01298     /* Process Locked */
01299     __HAL_LOCK(hnand);
01300
01301     /* Update the NAND controller state */
01302     hnand->State = HAL_NAND_STATE_BUSY;
01303
01304     /* Identify the device address */
01305     deviceAddress = NAND_DEVICE;
01306
01307     /* NAND raw address calculation */
01308     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01309
01310     /* Column in page address */
01311     columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01312
01313     /* Spare area(s) read loop */
01314     while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01315     {
01316       /* Cards with page size <= 512 bytes */
01317       if ((hnand->Config.PageSize) <= 512U)
01318       {
01319         /* Send read spare area command sequence */
01320         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01321         __DSB();
01322
01323         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01324         {
01325           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01326           __DSB();
01327           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01328           __DSB();
01329           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01330           __DSB();
01331         }
01332         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01333         {
01334           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01335           __DSB();
01336           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01337           __DSB();
01338           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01339           __DSB();
01340           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01341           __DSB();
01342         }
01343       }
01344       else /* (hnand->Config.PageSize) > 512 */
01345       {
01346         /* Send read spare area command sequence */
01347         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01348         __DSB();
01349
01350         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01351         {
01352           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01353           __DSB();
01354           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01355           __DSB();
01356           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01357           __DSB();
01358           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01359           __DSB();
01360         }
01361         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01362         {
01363           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01364           __DSB();
01365           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01366           __DSB();
01367           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01368           __DSB();
01369           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01370           __DSB();
01371           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01372           __DSB();
01373         }
01374       }
01375
01376       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01377       __DSB();
01378
01379       if (hnand->Config.ExtraCommandEnable == ENABLE)
01380       {
01381         /* Get tick */
01382         tickstart = HAL_GetTick();
01383
01384         /* Read status until NAND is ready */
01385         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01386         {
01387           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01388           {
01389             /* Update the NAND controller state */
01390             hnand->State = HAL_NAND_STATE_ERROR;
01391
01392             /* Process unlocked */
01393             __HAL_UNLOCK(hnand);
01394
01395             return HAL_TIMEOUT;
01396           }
01397         }
01398
01399         /* Go back to read mode */
01400         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
01401         __DSB();
01402       }
01403
01404       /* Get Data into Buffer */
01405       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01406       {
01407         *buff = *(uint16_t *)deviceAddress;
01408         buff++;
01409       }
01410
01411       /* Increment read spare areas number */
01412       numSpareAreaRead++;
01413
01414       /* Decrement spare areas to read */
01415       nbspare--;
01416
01417       /* Increment the NAND address */
01418       nandAddress = (uint32_t)(nandAddress + 1U);
01419     }
01420
01421     /* Update the NAND controller state */
01422     hnand->State = HAL_NAND_STATE_READY;
01423
01424     /* Process unlocked */
01425     __HAL_UNLOCK(hnand);
01426   }
01427   else
01428   {
01429     return HAL_ERROR;
01430   }
01431
01432   return HAL_OK;
01433 }
01434
01435 /**
01436   * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
01437   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01438   *                the configuration information for NAND module.
01439   * @param  pAddress  pointer to NAND address structure
01440   * @param  pBuffer  pointer to source buffer to write
01441   * @param  NumSpareAreaTowrite   number of spare areas to write to block
01442   * @retval HAL status
01443   */
01444 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
01445 {
01446   uint32_t index;
01447   uint32_t tickstart;
01448   uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
01449   uint8_t * buff = pBuffer;
01450
01451   /* Check the NAND controller state */
01452   if (hnand->State == HAL_NAND_STATE_BUSY)
01453   {
01454     return HAL_BUSY;
01455   }
01456   else if (hnand->State == HAL_NAND_STATE_READY)
01457   {
01458     /* Process Locked */
01459     __HAL_LOCK(hnand);
01460
01461     /* Update the NAND controller state */
01462     hnand->State = HAL_NAND_STATE_BUSY;
01463
01464     /* Identify the device address */
01465     deviceAddress = NAND_DEVICE;
01466
01467     /* Page address calculation */
01468     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01469
01470     /* Column in page address */
01471     columnAddress = COLUMN_ADDRESS(hnand);
01472
01473     /* Spare area(s) write loop */
01474     while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01475     {
01476       /* Cards with page size <= 512 bytes */
01477       if ((hnand->Config.PageSize) <= 512U)
01478       {
01479         /* Send write Spare area command sequence */
01480         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01481         __DSB();
01482         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01483         __DSB();
01484
01485         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01486         {
01487           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01488           __DSB();
01489           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01490           __DSB();
01491           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01492           __DSB();
01493         }
01494         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01495         {
01496           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01497           __DSB();
01498           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01499           __DSB();
01500           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01501           __DSB();
01502           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01503           __DSB();
01504         }
01505       }
01506       else /* (hnand->Config.PageSize) > 512 */
01507       {
01508         /* Send write Spare area command sequence */
01509         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01510         __DSB();
01511         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01512         __DSB();
01513
01514         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01515         {
01516           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01517           __DSB();
01518           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01519           __DSB();
01520           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01521           __DSB();
01522           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01523           __DSB();
01524         }
01525         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01526         {
01527           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01528           __DSB();
01529           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01530           __DSB();
01531           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01532           __DSB();
01533           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01534           __DSB();
01535           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01536           __DSB();
01537         }
01538       }
01539
01540       /* Write data to memory */
01541       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01542       {
01543         *(__IO uint8_t *)deviceAddress = *buff;
01544         buff++;
01545         __DSB();
01546       }
01547
01548       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01549       __DSB();
01550
01551       /* Get tick */
01552       tickstart = HAL_GetTick();
01553
01554       /* Read status until NAND is ready */
01555       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01556       {
01557         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01558         {
01559           /* Update the NAND controller state */
01560           hnand->State = HAL_NAND_STATE_ERROR;
01561
01562           /* Process unlocked */
01563           __HAL_UNLOCK(hnand);
01564
01565           return HAL_TIMEOUT;
01566         }
01567       }
01568
01569       /* Increment written spare areas number */
01570       numSpareAreaWritten++;
01571
01572       /* Decrement spare areas to write */
01573       nbspare--;
01574
01575       /* Increment the NAND address */
01576       nandAddress = (uint32_t)(nandAddress + 1U);
01577     }
01578
01579     /* Update the NAND controller state */
01580     hnand->State = HAL_NAND_STATE_READY;
01581
01582     /* Process unlocked */
01583     __HAL_UNLOCK(hnand);
01584   }
01585   else
01586   {
01587     return HAL_ERROR;
01588   }
01589
01590   return HAL_OK;
01591 }
01592
01593 /**
01594   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
01595   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01596   *                the configuration information for NAND module.
01597   * @param  pAddress  pointer to NAND address structure
01598   * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned.
01599   * @param  NumSpareAreaTowrite   number of spare areas to write to block
01600   * @retval HAL status
01601   */
01602 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
01603 {
01604   uint32_t index;
01605   uint32_t tickstart;
01606   uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
01607   uint16_t * buff = pBuffer;
01608
01609   /* Check the NAND controller state */
01610   if (hnand->State == HAL_NAND_STATE_BUSY)
01611   {
01612     return HAL_BUSY;
01613   }
01614   else if (hnand->State == HAL_NAND_STATE_READY)
01615   {
01616     /* Process Locked */
01617     __HAL_LOCK(hnand);
01618
01619     /* Update the NAND controller state */
01620     hnand->State = HAL_NAND_STATE_BUSY;
01621
01622     /* Identify the device address */
01623     deviceAddress = NAND_DEVICE;
01624
01625     /* NAND raw address calculation */
01626     nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01627
01628     /* Column in page address */
01629     columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01630
01631     /* Spare area(s) write loop */
01632     while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01633     {
01634       /* Cards with page size <= 512 bytes */
01635       if ((hnand->Config.PageSize) <= 512U)
01636       {
01637         /* Send write Spare area command sequence */
01638         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01639         __DSB();
01640         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01641         __DSB();
01642
01643         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01644         {
01645           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01646           __DSB();
01647           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01648           __DSB();
01649           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01650           __DSB();
01651         }
01652         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01653         {
01654           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
01655           __DSB();
01656           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01657           __DSB();
01658           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01659           __DSB();
01660           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01661           __DSB();
01662         }
01663       }
01664       else /* (hnand->Config.PageSize) > 512 */
01665       {
01666         /* Send write Spare area command sequence */
01667         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01668         __DSB();
01669         *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01670         __DSB();
01671
01672         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01673         {
01674           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01675           __DSB();
01676           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01677           __DSB();
01678           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01679           __DSB();
01680           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01681           __DSB();
01682         }
01683         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01684         {
01685           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01686           __DSB();
01687           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01688           __DSB();
01689           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01690           __DSB();
01691           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01692           __DSB();
01693           *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01694           __DSB();
01695         }
01696       }
01697
01698       /* Write data to memory */
01699       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01700       {
01701         *(__IO uint16_t *)deviceAddress = *buff;
01702         buff++;
01703         __DSB();
01704       }
01705
01706       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01707       __DSB();
01708
01709       /* Get tick */
01710       tickstart = HAL_GetTick();
01711
01712       /* Read status until NAND is ready */
01713       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01714       {
01715         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01716         {
01717           /* Update the NAND controller state */
01718           hnand->State = HAL_NAND_STATE_ERROR;
01719
01720           /* Process unlocked */
01721           __HAL_UNLOCK(hnand);
01722
01723           return HAL_TIMEOUT;
01724         }
01725       }
01726
01727       /* Increment written spare areas number */
01728       numSpareAreaWritten++;
01729
01730       /* Decrement spare areas to write */
01731       nbspare--;
01732
01733       /* Increment the NAND address */
01734       nandAddress = (uint32_t)(nandAddress + 1U);
01735     }
01736
01737     /* Update the NAND controller state */
01738     hnand->State = HAL_NAND_STATE_READY;
01739
01740     /* Process unlocked */
01741     __HAL_UNLOCK(hnand);
01742   }
01743   else
01744   {
01745     return HAL_ERROR;
01746   }
01747
01748   return HAL_OK;
01749 }
01750
01751 /**
01752   * @brief  NAND memory Block erase
01753   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01754   *                the configuration information for NAND module.
01755   * @param  pAddress  pointer to NAND address structure
01756   * @retval HAL status
01757   */
01758 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01759 {
01760   uint32_t DeviceAddress;
01761
01762   /* Check the NAND controller state */
01763   if (hnand->State == HAL_NAND_STATE_BUSY)
01764   {
01765     return HAL_BUSY;
01766   }
01767   else if (hnand->State == HAL_NAND_STATE_READY)
01768   {
01769     /* Process Locked */
01770     __HAL_LOCK(hnand);
01771
01772     /* Update the NAND controller state */
01773     hnand->State = HAL_NAND_STATE_BUSY;
01774
01775     /* Identify the device address */
01776     DeviceAddress = NAND_DEVICE;
01777
01778     /* Send Erase block command sequence */
01779     *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
01780     __DSB();
01781     *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01782     __DSB();
01783     *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01784     __DSB();
01785     *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01786     __DSB();
01787
01788     *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
01789     __DSB();
01790
01791     /* Update the NAND controller state */
01792     hnand->State = HAL_NAND_STATE_READY;
01793
01794     /* Process unlocked */
01795     __HAL_UNLOCK(hnand);
01796   }
01797   else
01798   {
01799     return HAL_ERROR;
01800   }
01801
01802   return HAL_OK;
01803 }
01804
01805 /**
01806   * @brief  Increment the NAND memory address
01807   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01808   *                the configuration information for NAND module.
01809   * @param pAddress pointer to NAND address structure
01810   * @retval The new status of the increment address operation. It can be:
01811   *           - NAND_VALID_ADDRESS: When the new address is valid address
01812   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
01813   */
01814 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01815 {
01816   uint32_t status = NAND_VALID_ADDRESS;
01817
01818   /* Increment page address */
01819   pAddress->Page++;
01820
01821   /* Check NAND address is valid */
01822   if (pAddress->Page == hnand->Config.BlockSize)
01823   {
01824     pAddress->Page = 0;
01825     pAddress->Block++;
01826
01827     if (pAddress->Block == hnand->Config.PlaneSize)
01828     {
01829       pAddress->Block = 0;
01830       pAddress->Plane++;
01831
01832       if (pAddress->Plane == (hnand->Config.PlaneNbr))
01833       {
01834         status = NAND_INVALID_ADDRESS;
01835       }
01836     }
01837   }
01838
01839   return (status);
01840 }
01841
01842 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
01843 /**
01844   * @brief  Register a User NAND Callback
01845   *         To be used instead of the weak (surcharged) predefined callback
01846   * @param hnand : NAND handle
01847   * @param CallbackId : ID of the callback to be registered
01848   *        This parameter can be one of the following values:
01849   *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
01850   *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
01851   *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
01852   * @param pCallback : pointer to the Callback function
01853   * @retval status
01854   */
01855 HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
01856 {
01857   HAL_StatusTypeDef status = HAL_OK;
01858
01859   if(pCallback == NULL)
01860   {
01861     return HAL_ERROR;
01862   }
01863
01864   /* Process locked */
01865   __HAL_LOCK(hnand);
01866
01867   if(hnand->State == HAL_NAND_STATE_READY)
01868   {
01869     switch (CallbackId)
01870     {
01871     case HAL_NAND_MSP_INIT_CB_ID :
01872       hnand->MspInitCallback = pCallback;
01873       break;
01874     case HAL_NAND_MSP_DEINIT_CB_ID :
01875       hnand->MspDeInitCallback = pCallback;
01876       break;
01877     case HAL_NAND_IT_CB_ID :
01878       hnand->ItCallback = pCallback;
01879       break;
01880     default :
01881       /* update return status */
01882       status =  HAL_ERROR;
01883       break;
01884     }
01885   }
01886   else if(hnand->State == HAL_NAND_STATE_RESET)
01887   {
01888     switch (CallbackId)
01889     {
01890     case HAL_NAND_MSP_INIT_CB_ID :
01891       hnand->MspInitCallback = pCallback;
01892       break;
01893     case HAL_NAND_MSP_DEINIT_CB_ID :
01894       hnand->MspDeInitCallback = pCallback;
01895       break;
01896     default :
01897       /* update return status */
01898       status =  HAL_ERROR;
01899       break;
01900     }
01901   }
01902   else
01903   {
01904     /* update return status */
01905     status =  HAL_ERROR;
01906   }
01907
01908   /* Release Lock */
01909   __HAL_UNLOCK(hnand);
01910   return status;
01911 }
01912
01913 /**
01914   * @brief  Unregister a User NAND Callback
01915   *         NAND Callback is redirected to the weak (surcharged) predefined callback
01916   * @param hnand : NAND handle
01917   * @param CallbackId : ID of the callback to be unregistered
01918   *        This parameter can be one of the following values:
01919   *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
01920   *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
01921   *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
01922   * @retval status
01923   */
01924 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
01925 {
01926   HAL_StatusTypeDef status = HAL_OK;
01927
01928   /* Process locked */
01929   __HAL_LOCK(hnand);
01930
01931   if(hnand->State == HAL_NAND_STATE_READY)
01932   {
01933     switch (CallbackId)
01934     {
01935     case HAL_NAND_MSP_INIT_CB_ID :
01936       hnand->MspInitCallback = HAL_NAND_MspInit;
01937       break;
01938     case HAL_NAND_MSP_DEINIT_CB_ID :
01939       hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
01940       break;
01941     case HAL_NAND_IT_CB_ID :
01942       hnand->ItCallback = HAL_NAND_ITCallback;
01943       break;
01944     default :
01945       /* update return status */
01946       status =  HAL_ERROR;
01947       break;
01948     }
01949   }
01950   else if(hnand->State == HAL_NAND_STATE_RESET)
01951   {
01952     switch (CallbackId)
01953     {
01954     case HAL_NAND_MSP_INIT_CB_ID :
01955       hnand->MspInitCallback = HAL_NAND_MspInit;
01956       break;
01957     case HAL_NAND_MSP_DEINIT_CB_ID :
01958       hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
01959       break;
01960     default :
01961       /* update return status */
01962       status =  HAL_ERROR;
01963       break;
01964     }
01965   }
01966   else
01967   {
01968     /* update return status */
01969     status =  HAL_ERROR;
01970   }
01971
01972   /* Release Lock */
01973   __HAL_UNLOCK(hnand);
01974   return status;
01975 }
01976 #endif
01977
01978 /**
01979   * @}
01980   */
01981
01982 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
01983  *  @brief   management functions
01984  *
01985 @verbatim
01986   ==============================================================================
01987                          ##### NAND Control functions #####
01988   ==============================================================================
01989   [..]
01990     This subsection provides a set of functions allowing to control dynamically
01991     the NAND interface.
01992
01993 @endverbatim
01994   * @{
01995   */
01996
01997
01998 /**
01999   * @brief  Enables dynamically NAND ECC feature.
02000   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02001   *                the configuration information for NAND module.
02002   * @retval HAL status
02003   */
02004 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
02005 {
02006   /* Check the NAND controller state */
02007   if (hnand->State == HAL_NAND_STATE_BUSY)
02008   {
02009     return HAL_BUSY;
02010   }
02011   else if (hnand->State == HAL_NAND_STATE_READY)
02012   {
02013     /* Update the NAND state */
02014     hnand->State = HAL_NAND_STATE_BUSY;
02015
02016     /* Enable ECC feature */
02017     (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
02018
02019     /* Update the NAND state */
02020     hnand->State = HAL_NAND_STATE_READY;
02021   }
02022   else
02023   {
02024     return HAL_ERROR;
02025   }
02026
02027   return HAL_OK;
02028 }
02029
02030 /**
02031   * @brief  Disables dynamically FMC_NAND ECC feature.
02032   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02033   *                the configuration information for NAND module.
02034   * @retval HAL status
02035   */
02036 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
02037 {
02038   /* Check the NAND controller state */
02039   if (hnand->State == HAL_NAND_STATE_BUSY)
02040   {
02041     return HAL_BUSY;
02042   }
02043   else if (hnand->State == HAL_NAND_STATE_READY)
02044   {
02045     /* Update the NAND state */
02046     hnand->State = HAL_NAND_STATE_BUSY;
02047
02048     /* Disable ECC feature */
02049     (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
02050
02051     /* Update the NAND state */
02052     hnand->State = HAL_NAND_STATE_READY;
02053   }
02054   else
02055   {
02056     return HAL_ERROR;
02057   }
02058
02059   return HAL_OK;
02060 }
02061
02062 /**
02063   * @brief  Disables dynamically NAND ECC feature.
02064   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02065   *                the configuration information for NAND module.
02066   * @param  ECCval pointer to ECC value
02067   * @param  Timeout maximum timeout to wait
02068   * @retval HAL status
02069   */
02070 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
02071 {
02072   HAL_StatusTypeDef status;
02073
02074   /* Check the NAND controller state */
02075   if (hnand->State == HAL_NAND_STATE_BUSY)
02076   {
02077     return HAL_BUSY;
02078   }
02079   else if (hnand->State == HAL_NAND_STATE_READY)
02080   {
02081     /* Update the NAND state */
02082     hnand->State = HAL_NAND_STATE_BUSY;
02083
02084     /* Get NAND ECC value */
02085     status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
02086
02087     /* Update the NAND state */
02088     hnand->State = HAL_NAND_STATE_READY;
02089   }
02090   else
02091   {
02092     return HAL_ERROR;
02093   }
02094
02095   return status;
02096 }
02097
02098 /**
02099   * @}
02100   */
02101
02102
02103 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
02104  *  @brief   Peripheral State functions
02105  *
02106 @verbatim
02107   ==============================================================================
02108                          ##### NAND State functions #####
02109   ==============================================================================
02110   [..]
02111     This subsection permits to get in run-time the status of the NAND controller
02112     and the data flow.
02113
02114 @endverbatim
02115   * @{
02116   */
02117
02118 /**
02119   * @brief  return the NAND state
02120   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02121   *                the configuration information for NAND module.
02122   * @retval HAL state
02123   */
02124 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
02125 {
02126   return hnand->State;
02127 }
02128
02129 /**
02130   * @brief  NAND memory read status
02131   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02132   *                the configuration information for NAND module.
02133   * @retval NAND status
02134   */
02135 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
02136 {
02137   uint32_t data;
02138   uint32_t DeviceAddress;
02139   UNUSED(hnand);
02140
02141   /* Identify the device address */
02142   DeviceAddress = NAND_DEVICE;
02143
02144   /* Send Read status operation command */
02145   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
02146
02147   /* Read status register data */
02148   data = *(__IO uint8_t *)DeviceAddress;
02149
02150   /* Return the status */
02151   if ((data & NAND_ERROR) == NAND_ERROR)
02152   {
02153     return NAND_ERROR;
02154   }
02155   else if ((data & NAND_READY) == NAND_READY)
02156   {
02157     return NAND_READY;
02158   }
02159   else
02160   {
02161     return NAND_BUSY;
02162   }
02163 }
02164
02165 /**
02166   * @}
02167   */
02168
02169 /**
02170   * @}
02171   */
02172
02173 /**
02174   * @}
02175   */
02176
02177 #endif /* HAL_NAND_MODULE_ENABLED  */
02178
02179 /**
02180   * @}
02181   */
02182
02183
02184 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nand.h Source File

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stm32h7xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NAND HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   *
00011   * This software component is licensed by ST under BSD 3-Clause license,
00012   * the "License"; You may not use this file except in compliance with the
00013   * License. You may obtain a copy of the License at:
00014   *                       opensource.org/licenses/BSD-3-Clause
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32H7xx_HAL_NAND_H
00021 #define STM32H7xx_HAL_NAND_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_fmc.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup NAND
00036   * @{
00037   */
00038
00039 /* Exported typedef ----------------------------------------------------------*/
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup NAND_Exported_Types NAND Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL NAND State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00051   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00052   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00053   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00054 } HAL_NAND_StateTypeDef;
00055
00056 /**
00057   * @brief  NAND Memory electronic signature Structure definition
00058   */
00059 typedef struct
00060 {
00061   /*<! NAND memory electronic signature maker and device IDs */
00062
00063   uint8_t Maker_Id;
00064
00065   uint8_t Device_Id;
00066
00067   uint8_t Third_Id;
00068
00069   uint8_t Fourth_Id;
00070 } NAND_IDTypeDef;
00071
00072 /**
00073   * @brief  NAND Memory address Structure definition
00074   */
00075 typedef struct
00076 {
00077   uint16_t Page;   /*!< NAND memory Page address  */
00078
00079   uint16_t Plane;   /*!< NAND memory Zone address  */
00080
00081   uint16_t Block;  /*!< NAND memory Block address */
00082
00083 } NAND_AddressTypeDef;
00084
00085 /**
00086   * @brief  NAND Memory info Structure definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
00091                                               for 8 bits adressing or words for 16 bits addressing             */
00092
00093   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
00094                                               for 8 bits adressing or words for 16 bits addressing             */
00095
00096   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
00097
00098   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
00099
00100   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
00101
00102   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
00103
00104   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
00105                                               parameter is mandatory for some NAND parts after the read
00106                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
00107                                               Example: Toshiba THTH58BYG3S0HBAI6.
00108                                               This parameter could be ENABLE or DISABLE
00109                                               Please check the Read Mode sequnece in the NAND device datasheet */
00110 } NAND_DeviceConfigTypeDef;
00111
00112 /**
00113   * @brief  NAND handle Structure definition
00114   */
00115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00116 typedef struct __NAND_HandleTypeDef
00117 #else
00118 typedef struct
00119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
00120 {
00121   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
00122
00123   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
00124
00125   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
00126
00127   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
00128
00129   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
00130
00131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00132   void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */
00133   void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */
00134   void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */
00135 #endif
00136 } NAND_HandleTypeDef;
00137
00138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00139 /**
00140   * @brief  HAL NAND Callback ID enumeration definition
00141   */
00142 typedef enum
00143 {
00144   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
00145   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
00146   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
00147 }HAL_NAND_CallbackIDTypeDef;
00148
00149 /**
00150   * @brief  HAL NAND Callback pointer definition
00151   */
00152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
00153 #endif
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported constants --------------------------------------------------------*/
00160 /* Exported macro ------------------------------------------------------------*/
00161 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00162  * @{
00163  */
00164
00165 /** @brief Reset NAND handle state
00166   * @param  __HANDLE__ specifies the NAND handle.
00167   * @retval None
00168   */
00169 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
00171                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
00172                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00173                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00174                                                              } while(0)
00175 #else
00176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00177 #endif
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00185   * @{
00186   */
00187
00188 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00189   * @{
00190   */
00191
00192 /* Initialization/de-initialization functions  ********************************/
00193 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00194 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00195
00196 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
00197
00198 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00199
00200 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00201 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00202 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00203 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00210   * @{
00211   */
00212
00213 /* IO operation functions  ****************************************************/
00214
00215 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00216
00217 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00218 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00219 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00220 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00221
00222 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
00223 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
00224 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
00225 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
00226
00227 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00228
00229 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00230
00231 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00232 /* NAND callback registering/unregistering */
00233 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
00234 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
00235 #endif
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00242   * @{
00243   */
00244
00245 /* NAND Control functions  ****************************************************/
00246 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00247 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00248 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00255   * @{
00256   */
00257 /* NAND State functions *******************************************************/
00258 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00259 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267 /* Private types -------------------------------------------------------------*/
00268 /* Private variables ---------------------------------------------------------*/
00269 /* Private constants ---------------------------------------------------------*/
00270 /** @defgroup NAND_Private_Constants NAND Private Constants
00271   * @{
00272   */
00273 #define NAND_DEVICE                ((uint32_t)0x80000000U)
00274 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
00275
00276 #define CMD_AREA                   ((uint32_t)(1UL<<16U))  /* A16 = CLE high */
00277 #define ADDR_AREA                  ((uint32_t)(1UL<<17U))  /* A17 = ALE high */
00278
00279 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
00280 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
00281 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
00282 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
00283
00284 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
00285 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
00286 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
00287 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
00288 #define NAND_CMD_READID            ((uint8_t)0x90U)
00289 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
00290 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
00291 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
00292
00293 /* NAND memory status */
00294 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
00295 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
00296 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
00297 #define NAND_BUSY                  ((uint32_t)0x00000000U)
00298 #define NAND_ERROR                 ((uint32_t)0x00000001U)
00299 #define NAND_READY                 ((uint32_t)0x00000040U)
00300 /**
00301   * @}
00302   */
00303
00304 /* Private macros ------------------------------------------------------------*/
00305 /** @defgroup NAND_Private_Macros NAND Private Macros
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  NAND memory address computation.
00311   * @param  __ADDRESS__ NAND memory address.
00312   * @param  __HANDLE__  NAND handle.
00313   * @retval NAND Raw address value
00314   */
00315 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00316                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
00317
00318 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
00319
00320 /**
00321   * @brief  NAND memory address cycling.
00322   * @param  __ADDRESS__ NAND memory address.
00323   * @retval NAND address cycling value.
00324   */
00325 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00326 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00327 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00328 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00329
00330 /**
00331   * @brief  NAND memory Columns cycling.
00332   * @param  __ADDRESS__ NAND memory address.
00333   * @retval NAND Column address cycling value.
00334   */
00335 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
00336 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /**
00343   * @}
00344   */
00345
00346 /**
00347   * @}
00348   */
00349
00350 /**
00351   * @}
00352   */
00353
00354
00355 #ifdef __cplusplus
00356 }
00357 #endif
00358
00359 #endif /* STM32H7xx_HAL_NAND_H */
00360
00361 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nor.c Source File

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stm32h7xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @brief   NOR HAL module driver.
00006   *          This file provides a generic firmware to drive NOR memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                      ##### How to use this driver #####
00012   ==============================================================================
00013     [..]
00014       This driver is a generic layered driver which contains a set of APIs used to
00015       control NOR flash memories. It uses the FMC layer functions to interface
00016       with NOR devices. This driver is used as follows:
00017
00018       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00019           with control and timing parameters for both normal and extended mode.
00020
00021       (+) Read NOR flash memory manufacturer code and device IDs using the function
00022           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00023           structure declared by the function caller.
00024
00025       (+) Access NOR flash memory by read/write data unit operations using the functions
00026           HAL_NOR_Read(), HAL_NOR_Program().
00027
00028       (+) Perform NOR flash erase block/chip operations using the functions
00029           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00030
00031       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00032           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00033           structure declared by the function caller.
00034
00035       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00036           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00037
00038       (+) You can monitor the NOR device HAL state by calling the function
00039           HAL_NOR_GetState()
00040     [..]
00041      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00042          If a NOR flash device contains different operations and/or implementations,
00043          it should be implemented separately.
00044
00045      *** NOR HAL driver macros list ***
00046      =============================================
00047      [..]
00048        Below the list of most used macros in NOR HAL driver.
00049
00050       (+) NOR_WRITE : NOR memory write data to specified address
00051
00052     *** Callback registration ***
00053     =============================================
00054     [..]
00055       The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
00056       allows the user to configure dynamically the driver callbacks.
00057
00058       Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
00059       it allows to register following callbacks:
00060         (+) MspInitCallback    : NOR MspInit.
00061         (+) MspDeInitCallback  : NOR MspDeInit.
00062       This function takes as parameters the HAL peripheral handle, the Callback ID
00063       and a pointer to the user callback function.
00064
00065       Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
00066       weak (surcharged) function. It allows to reset following callbacks:
00067         (+) MspInitCallback    : NOR MspInit.
00068         (+) MspDeInitCallback  : NOR MspDeInit.
00069       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00070
00071       By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
00072       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00073       Exception done for MspInit and MspDeInit callbacks that are respectively
00074       reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
00075       and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
00076       If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
00077       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00078
00079       Callbacks can be registered/unregistered in READY state only.
00080       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00081       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00082       during the Init/DeInit.
00083       In that case first register the MspInit/MspDeInit user callbacks
00084       using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
00085       or @ref HAL_NOR_Init function.
00086
00087       When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
00088       not defined, the callback registering feature is not available
00089       and weak (surcharged) callbacks are used.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00096   *
00097   * This software component is licensed by ST under BSD 3-Clause license,
00098   * the "License"; You may not use this file except in compliance with the
00099   * License. You may obtain a copy of the License at:
00100   *                       opensource.org/licenses/BSD-3-Clause
00101   *
00102   ******************************************************************************
00103   */
00104
00105 /* Includes ------------------------------------------------------------------*/
00106 #include "stm32h7xx_hal.h"
00107
00108
00109 /** @addtogroup STM32H7xx_HAL_Driver
00110   * @{
00111   */
00112
00113 #ifdef HAL_NOR_MODULE_ENABLED
00114
00115 /** @defgroup NOR NOR
00116   * @brief NOR driver modules
00117   * @{
00118   */
00119
00120 /* Private typedef -----------------------------------------------------------*/
00121 /* Private define ------------------------------------------------------------*/
00122
00123 /** @defgroup NOR_Private_Defines NOR Private Defines
00124   * @{
00125   */
00126
00127 /* Constants to define address to set to write a command */
00128 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00129 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00130 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00131 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00132 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00133 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00134 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00135
00136 /* Constants to define data to program a command */
00137 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00138 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00139 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00140 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00141 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00142 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00143 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00144 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00145 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00146 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00147
00148 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00149 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00150 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00151
00152 /* Mask on NOR STATUS REGISTER */
00153 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00154 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Private macro -------------------------------------------------------------*/
00161 /* Private variables ---------------------------------------------------------*/
00162 /** @defgroup NOR_Private_Variables NOR Private Variables
00163   * @{
00164   */
00165
00166 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Private functions ---------------------------------------------------------*/
00173 /* Exported functions --------------------------------------------------------*/
00174 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00175   * @{
00176   */
00177
00178 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00179   * @brief    Initialization and Configuration functions
00180   *
00181   @verbatim
00182   ==============================================================================
00183            ##### NOR Initialization and de_initialization functions #####
00184   ==============================================================================
00185   [..]
00186     This section provides functions allowing to initialize/de-initialize
00187     the NOR memory
00188
00189 @endverbatim
00190   * @{
00191   */
00192
00193 /**
00194   * @brief  Perform the NOR memory Initialization sequence
00195   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00196   *                the configuration information for NOR module.
00197   * @param  Timing pointer to NOR control timing structure
00198   * @param  ExtTiming pointer to NOR extended mode timing structure
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00202 {
00203   /* Check the NOR handle parameter */
00204   if (hnor == NULL)
00205   {
00206     return HAL_ERROR;
00207   }
00208
00209   if (hnor->State == HAL_NOR_STATE_RESET)
00210   {
00211     /* Allocate lock resource and initialize it */
00212     hnor->Lock = HAL_UNLOCKED;
00213
00214 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00215     if(hnor->MspInitCallback == NULL)
00216     {
00217       hnor->MspInitCallback = HAL_NOR_MspInit;
00218     }
00219
00220     /* Init the low level hardware */
00221     hnor->MspInitCallback(hnor);
00222 #else
00223     /* Initialize the low level hardware (MSP) */
00224     HAL_NOR_MspInit(hnor);
00225 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
00226   }
00227
00228   /* Initialize NOR control Interface */
00229   (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00230
00231   /* Initialize NOR timing Interface */
00232   (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00233
00234   /* Initialize NOR extended mode timing Interface */
00235   (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00236
00237   /* Enable the NORSRAM device */
00238   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00239
00240   /* Initialize NOR Memory Data Width*/
00241   if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
00242   {
00243     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00244   }
00245   else
00246   {
00247     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00248   }
00249
00250   /* Enable FMC Peripheral */
00251   __FMC_ENABLE();
00252
00253   /* Initialize the NOR controller state */
00254   hnor->State = HAL_NOR_STATE_READY;
00255
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Perform NOR memory De-Initialization sequence
00261   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00262   *                the configuration information for NOR module.
00263   * @retval HAL status
00264   */
00265 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00266 {
00267 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00268   if(hnor->MspDeInitCallback == NULL)
00269   {
00270     hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
00271   }
00272
00273   /* DeInit the low level hardware */
00274   hnor->MspDeInitCallback(hnor);
00275 #else
00276   /* De-Initialize the low level hardware (MSP) */
00277   HAL_NOR_MspDeInit(hnor);
00278 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
00279
00280   /* Configure the NOR registers with their reset values */
00281   (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00282
00283   /* Reset the NOR controller state */
00284   hnor->State = HAL_NOR_STATE_RESET;
00285
00286   /* Release Lock */
00287   __HAL_UNLOCK(hnor);
00288
00289   return HAL_OK;
00290 }
00291
00292 /**
00293   * @brief  NOR MSP Init
00294   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00295   *                the configuration information for NOR module.
00296   * @retval None
00297   */
00298 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00299 {
00300   /* Prevent unused argument(s) compilation warning */
00301   UNUSED(hnor);
00302
00303   /* NOTE : This function Should not be modified, when the callback is needed,
00304             the HAL_NOR_MspInit could be implemented in the user file
00305    */
00306 }
00307
00308 /**
00309   * @brief  NOR MSP DeInit
00310   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00311   *                the configuration information for NOR module.
00312   * @retval None
00313   */
00314 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00315 {
00316   /* Prevent unused argument(s) compilation warning */
00317   UNUSED(hnor);
00318
00319   /* NOTE : This function Should not be modified, when the callback is needed,
00320             the HAL_NOR_MspDeInit could be implemented in the user file
00321    */
00322 }
00323
00324 /**
00325   * @brief  NOR MSP Wait for Ready/Busy signal
00326   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00327   *                the configuration information for NOR module.
00328   * @param  Timeout Maximum timeout value
00329   * @retval None
00330   */
00331 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00332 {
00333   /* Prevent unused argument(s) compilation warning */
00334   UNUSED(hnor);
00335   UNUSED(Timeout);
00336
00337   /* NOTE : This function Should not be modified, when the callback is needed,
00338             the HAL_NOR_MspWait could be implemented in the user file
00339    */
00340 }
00341
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00347   * @brief    Input Output and memory control functions
00348   *
00349   @verbatim
00350   ==============================================================================
00351                 ##### NOR Input and Output functions #####
00352   ==============================================================================
00353   [..]
00354     This section provides functions allowing to use and control the NOR memory
00355
00356 @endverbatim
00357   * @{
00358   */
00359
00360 /**
00361   * @brief  Read NOR flash IDs
00362   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00363   *                the configuration information for NOR module.
00364   * @param  pNOR_ID  pointer to NOR ID structure
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00368 {
00369   uint32_t deviceaddress;
00370   HAL_NOR_StateTypeDef state;
00371
00372   /* Check the NOR controller state */
00373   state = hnor->State;
00374   if (state == HAL_NOR_STATE_BUSY)
00375   {
00376     return HAL_BUSY;
00377   }
00378   else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
00379   {
00380     /* Process Locked */
00381     __HAL_LOCK(hnor);
00382
00383     /* Update the NOR controller state */
00384     hnor->State = HAL_NOR_STATE_BUSY;
00385
00386     /* Select the NOR device address */
00387     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00388     {
00389       deviceaddress = NOR_MEMORY_ADRESS1;
00390     }
00391     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00392     {
00393       deviceaddress = NOR_MEMORY_ADRESS2;
00394     }
00395     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00396     {
00397       deviceaddress = NOR_MEMORY_ADRESS3;
00398     }
00399     else /* FMC_NORSRAM_BANK4 */
00400     {
00401       deviceaddress = NOR_MEMORY_ADRESS4;
00402     }
00403
00404     /* Send read ID command */
00405     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00406     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00407     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00408
00409     /* Read the NOR IDs */
00410     pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00411     pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
00412     pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
00413     pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
00414
00415     /* Check the NOR controller state */
00416     hnor->State = state;
00417
00418     /* Process unlocked */
00419     __HAL_UNLOCK(hnor);
00420   }
00421   else
00422   {
00423     return HAL_ERROR;
00424   }
00425
00426   return HAL_OK;
00427 }
00428
00429 /**
00430   * @brief  Returns the NOR memory to Read mode.
00431   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00432   *                the configuration information for NOR module.
00433   * @retval HAL status
00434   */
00435 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00436 {
00437   uint32_t deviceaddress;
00438   HAL_NOR_StateTypeDef state;
00439
00440   /* Check the NOR controller state */
00441   state = hnor->State;
00442   if (state == HAL_NOR_STATE_BUSY)
00443   {
00444     return HAL_BUSY;
00445   }
00446   else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
00447   {
00448     /* Process Locked */
00449     __HAL_LOCK(hnor);
00450
00451     /* Update the NOR controller state */
00452     hnor->State = HAL_NOR_STATE_BUSY;
00453
00454     /* Select the NOR device address */
00455     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00456     {
00457       deviceaddress = NOR_MEMORY_ADRESS1;
00458     }
00459     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00460     {
00461       deviceaddress = NOR_MEMORY_ADRESS2;
00462     }
00463     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00464     {
00465       deviceaddress = NOR_MEMORY_ADRESS3;
00466     }
00467     else /* FMC_NORSRAM_BANK4 */
00468     {
00469       deviceaddress = NOR_MEMORY_ADRESS4;
00470     }
00471
00472     NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00473
00474     /* Check the NOR controller state */
00475     hnor->State = state;
00476
00477     /* Process unlocked */
00478     __HAL_UNLOCK(hnor);
00479   }
00480   else
00481   {
00482     return HAL_ERROR;
00483   }
00484
00485   return HAL_OK;
00486 }
00487
00488 /**
00489   * @brief  Read data from NOR memory
00490   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00491   *                the configuration information for NOR module.
00492   * @param  pAddress pointer to Device address
00493   * @param  pData  pointer to read data
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00497 {
00498   uint32_t deviceaddress;
00499   HAL_NOR_StateTypeDef state;
00500
00501   /* Check the NOR controller state */
00502   state = hnor->State;
00503   if (state == HAL_NOR_STATE_BUSY)
00504   {
00505     return HAL_BUSY;
00506   }
00507   else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
00508   {
00509     /* Process Locked */
00510     __HAL_LOCK(hnor);
00511
00512     /* Update the NOR controller state */
00513     hnor->State = HAL_NOR_STATE_BUSY;
00514
00515     /* Select the NOR device address */
00516     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00517     {
00518       deviceaddress = NOR_MEMORY_ADRESS1;
00519     }
00520     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00521     {
00522       deviceaddress = NOR_MEMORY_ADRESS2;
00523     }
00524     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00525     {
00526       deviceaddress = NOR_MEMORY_ADRESS3;
00527     }
00528     else /* FMC_NORSRAM_BANK4 */
00529     {
00530       deviceaddress = NOR_MEMORY_ADRESS4;
00531     }
00532
00533     /* Send read data command */
00534     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00535     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00536     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00537
00538     /* Read the data */
00539     *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
00540
00541     /* Check the NOR controller state */
00542     hnor->State = state;
00543
00544     /* Process unlocked */
00545     __HAL_UNLOCK(hnor);
00546   }
00547   else
00548   {
00549     return HAL_ERROR;
00550   }
00551
00552   return HAL_OK;
00553 }
00554
00555 /**
00556   * @brief  Program data to NOR memory
00557   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00558   *                the configuration information for NOR module.
00559   * @param  pAddress Device address
00560   * @param  pData  pointer to the data to write
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00564 {
00565   uint32_t deviceaddress;
00566
00567   /* Check the NOR controller state */
00568   if (hnor->State == HAL_NOR_STATE_BUSY)
00569   {
00570     return HAL_BUSY;
00571   }
00572   else if (hnor->State == HAL_NOR_STATE_READY)
00573   {
00574     /* Process Locked */
00575     __HAL_LOCK(hnor);
00576
00577     /* Update the NOR controller state */
00578     hnor->State = HAL_NOR_STATE_BUSY;
00579
00580     /* Select the NOR device address */
00581     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00582     {
00583       deviceaddress = NOR_MEMORY_ADRESS1;
00584     }
00585     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00586     {
00587       deviceaddress = NOR_MEMORY_ADRESS2;
00588     }
00589     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00590     {
00591       deviceaddress = NOR_MEMORY_ADRESS3;
00592     }
00593     else /* FMC_NORSRAM_BANK4 */
00594     {
00595       deviceaddress = NOR_MEMORY_ADRESS4;
00596     }
00597
00598     /* Send program data command */
00599     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00600     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00601     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00602
00603     /* Write the data */
00604     NOR_WRITE(pAddress, *pData);
00605
00606     /* Check the NOR controller state */
00607     hnor->State = HAL_NOR_STATE_READY;
00608
00609     /* Process unlocked */
00610     __HAL_UNLOCK(hnor);
00611   }
00612   else
00613   {
00614     return HAL_ERROR;
00615   }
00616
00617   return HAL_OK;
00618 }
00619
00620 /**
00621   * @brief  Reads a half-word buffer from the NOR memory.
00622   * @param  hnor pointer to the NOR handle
00623   * @param  uwAddress NOR memory internal address to read from.
00624   * @param  pData pointer to the buffer that receives the data read from the
00625   *         NOR memory.
00626   * @param  uwBufferSize  number of Half word to read.
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00630 {
00631   uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
00632   uint16_t *data = pData;
00633   HAL_NOR_StateTypeDef state;
00634
00635   /* Check the NOR controller state */
00636   state = hnor->State;
00637   if (state == HAL_NOR_STATE_BUSY)
00638   {
00639     return HAL_BUSY;
00640   }
00641   else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
00642   {
00643     /* Process Locked */
00644     __HAL_LOCK(hnor);
00645
00646     /* Update the NOR controller state */
00647     hnor->State = HAL_NOR_STATE_BUSY;
00648
00649     /* Select the NOR device address */
00650     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00651     {
00652       deviceaddress = NOR_MEMORY_ADRESS1;
00653     }
00654     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00655     {
00656       deviceaddress = NOR_MEMORY_ADRESS2;
00657     }
00658     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00659     {
00660       deviceaddress = NOR_MEMORY_ADRESS3;
00661     }
00662     else /* FMC_NORSRAM_BANK4 */
00663     {
00664       deviceaddress = NOR_MEMORY_ADRESS4;
00665     }
00666
00667     /* Send read data command */
00668     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00669     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00670     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00671
00672     /* Read buffer */
00673     while (size > 0U)
00674     {
00675       *data = *(__IO uint16_t *)address;
00676       data++;
00677       address += 2U;
00678       size--;
00679     }
00680
00681     /* Check the NOR controller state */
00682     hnor->State = state;
00683
00684     /* Process unlocked */
00685     __HAL_UNLOCK(hnor);
00686   }
00687   else
00688   {
00689     return HAL_ERROR;
00690   }
00691
00692   return HAL_OK;
00693 }
00694
00695 /**
00696   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
00697             only with S29GL128P NOR memory.
00698   * @param  hnor pointer to the NOR handle
00699   * @param  uwAddress NOR memory internal start write address
00700   * @param  pData pointer to source data buffer.
00701   * @param  uwBufferSize Size of the buffer to write
00702   * @retval HAL status
00703   */
00704 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00705 {
00706   uint16_t *p_currentaddress;
00707   const uint16_t *p_endaddress;
00708   uint16_t *data = pData;
00709   uint32_t lastloadedaddress, deviceaddress;
00710
00711   /* Check the NOR controller state */
00712   if (hnor->State == HAL_NOR_STATE_BUSY)
00713   {
00714     return HAL_BUSY;
00715   }
00716   else if (hnor->State == HAL_NOR_STATE_READY)
00717   {
00718     /* Process Locked */
00719     __HAL_LOCK(hnor);
00720
00721     /* Update the NOR controller state */
00722     hnor->State = HAL_NOR_STATE_BUSY;
00723
00724     /* Select the NOR device address */
00725     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00726     {
00727       deviceaddress = NOR_MEMORY_ADRESS1;
00728     }
00729     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00730     {
00731       deviceaddress = NOR_MEMORY_ADRESS2;
00732     }
00733     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00734     {
00735       deviceaddress = NOR_MEMORY_ADRESS3;
00736     }
00737     else /* FMC_NORSRAM_BANK4 */
00738     {
00739       deviceaddress = NOR_MEMORY_ADRESS4;
00740     }
00741
00742     /* Initialize variables */
00743     p_currentaddress  = (uint16_t *)(uwAddress);
00744     p_endaddress      = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
00745     lastloadedaddress = uwAddress;
00746
00747     /* Issue unlock command sequence */
00748     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00749     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00750
00751     /* Write Buffer Load Command */
00752     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00753     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
00754
00755     /* Load Data into NOR Buffer */
00756     while (p_currentaddress <= p_endaddress)
00757     {
00758       /* Store last loaded address & data value (for polling) */
00759       lastloadedaddress = (uint32_t)p_currentaddress;
00760
00761       NOR_WRITE(p_currentaddress, *data);
00762
00763       data++;
00764       p_currentaddress ++;
00765     }
00766
00767     NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00768
00769     /* Check the NOR controller state */
00770     hnor->State = HAL_NOR_STATE_READY;
00771
00772     /* Process unlocked */
00773     __HAL_UNLOCK(hnor);
00774   }
00775   else
00776   {
00777     return HAL_ERROR;
00778   }
00779
00780   return HAL_OK;
00781
00782 }
00783
00784 /**
00785   * @brief  Erase the specified block of the NOR memory
00786   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00787   *                the configuration information for NOR module.
00788   * @param  BlockAddress  Block to erase address
00789   * @param  Address Device address
00790   * @retval HAL status
00791   */
00792 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00793 {
00794   uint32_t deviceaddress;
00795
00796   /* Check the NOR controller state */
00797   if (hnor->State == HAL_NOR_STATE_BUSY)
00798   {
00799     return HAL_BUSY;
00800   }
00801   else if (hnor->State == HAL_NOR_STATE_READY)
00802   {
00803     /* Process Locked */
00804     __HAL_LOCK(hnor);
00805
00806     /* Update the NOR controller state */
00807     hnor->State = HAL_NOR_STATE_BUSY;
00808
00809     /* Select the NOR device address */
00810     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00811     {
00812       deviceaddress = NOR_MEMORY_ADRESS1;
00813     }
00814     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00815     {
00816       deviceaddress = NOR_MEMORY_ADRESS2;
00817     }
00818     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00819     {
00820       deviceaddress = NOR_MEMORY_ADRESS3;
00821     }
00822     else /* FMC_NORSRAM_BANK4 */
00823     {
00824       deviceaddress = NOR_MEMORY_ADRESS4;
00825     }
00826
00827     /* Send block erase command sequence */
00828     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00829     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00830     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00831     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00832     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00833     NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00834
00835     /* Check the NOR memory status and update the controller state */
00836     hnor->State = HAL_NOR_STATE_READY;
00837
00838     /* Process unlocked */
00839     __HAL_UNLOCK(hnor);
00840   }
00841   else
00842   {
00843     return HAL_ERROR;
00844   }
00845
00846   return HAL_OK;
00847
00848 }
00849
00850 /**
00851   * @brief  Erase the entire NOR chip.
00852   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00853   *                the configuration information for NOR module.
00854   * @param  Address  Device address
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00858 {
00859   uint32_t deviceaddress;
00860   UNUSED(Address);
00861
00862   /* Check the NOR controller state */
00863   if (hnor->State == HAL_NOR_STATE_BUSY)
00864   {
00865     return HAL_BUSY;
00866   }
00867   else if (hnor->State == HAL_NOR_STATE_READY)
00868   {
00869     /* Process Locked */
00870     __HAL_LOCK(hnor);
00871
00872     /* Update the NOR controller state */
00873     hnor->State = HAL_NOR_STATE_BUSY;
00874
00875     /* Select the NOR device address */
00876     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00877     {
00878       deviceaddress = NOR_MEMORY_ADRESS1;
00879     }
00880     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00881     {
00882       deviceaddress = NOR_MEMORY_ADRESS2;
00883     }
00884     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00885     {
00886       deviceaddress = NOR_MEMORY_ADRESS3;
00887     }
00888     else /* FMC_NORSRAM_BANK4 */
00889     {
00890       deviceaddress = NOR_MEMORY_ADRESS4;
00891     }
00892
00893     /* Send NOR chip erase command sequence */
00894     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00895     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00896     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00897     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00898     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00899     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00900
00901     /* Check the NOR memory status and update the controller state */
00902     hnor->State = HAL_NOR_STATE_READY;
00903
00904     /* Process unlocked */
00905     __HAL_UNLOCK(hnor);
00906   }
00907   else
00908   {
00909     return HAL_ERROR;
00910   }
00911
00912   return HAL_OK;
00913 }
00914
00915 /**
00916   * @brief  Read NOR flash CFI IDs
00917   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00918   *                the configuration information for NOR module.
00919   * @param  pNOR_CFI  pointer to NOR CFI IDs structure
00920   * @retval HAL status
00921   */
00922 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00923 {
00924   uint32_t deviceaddress;
00925   HAL_NOR_StateTypeDef state;
00926
00927   /* Check the NOR controller state */
00928   state = hnor->State;
00929   if (state == HAL_NOR_STATE_BUSY)
00930   {
00931     return HAL_BUSY;
00932   }
00933   else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
00934   {
00935     /* Process Locked */
00936     __HAL_LOCK(hnor);
00937
00938     /* Update the NOR controller state */
00939     hnor->State = HAL_NOR_STATE_BUSY;
00940
00941     /* Select the NOR device address */
00942     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00943     {
00944       deviceaddress = NOR_MEMORY_ADRESS1;
00945     }
00946     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00947     {
00948       deviceaddress = NOR_MEMORY_ADRESS2;
00949     }
00950     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00951     {
00952       deviceaddress = NOR_MEMORY_ADRESS3;
00953     }
00954     else /* FMC_NORSRAM_BANK4 */
00955     {
00956       deviceaddress = NOR_MEMORY_ADRESS4;
00957     }
00958
00959     /* Send read CFI query command */
00960     NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00961
00962     /* read the NOR CFI information */
00963     pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
00964     pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
00965     pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
00966     pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
00967
00968     /* Check the NOR controller state */
00969     hnor->State = state;
00970
00971     /* Process unlocked */
00972     __HAL_UNLOCK(hnor);
00973   }
00974   else
00975   {
00976     return HAL_ERROR;
00977   }
00978
00979   return HAL_OK;
00980 }
00981
00982 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00983 /**
00984   * @brief  Register a User NOR Callback
00985   *         To be used instead of the weak (surcharged) predefined callback
00986   * @param hnor : NOR handle
00987   * @param CallbackId : ID of the callback to be registered
00988   *        This parameter can be one of the following values:
00989   *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
00990   *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
00991   * @param pCallback : pointer to the Callback function
00992   * @retval status
00993   */
00994 HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
00995 {
00996   HAL_StatusTypeDef status = HAL_OK;
00997   HAL_NOR_StateTypeDef state;
00998
00999   if(pCallback == NULL)
01000   {
01001     return HAL_ERROR;
01002   }
01003
01004   /* Process locked */
01005   __HAL_LOCK(hnor);
01006
01007   state = hnor->State;
01008   if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
01009   {
01010     switch (CallbackId)
01011     {
01012     case HAL_NOR_MSP_INIT_CB_ID :
01013       hnor->MspInitCallback = pCallback;
01014       break;
01015     case HAL_NOR_MSP_DEINIT_CB_ID :
01016       hnor->MspDeInitCallback = pCallback;
01017       break;
01018     default :
01019       /* update return status */
01020       status =  HAL_ERROR;
01021       break;
01022     }
01023   }
01024   else
01025   {
01026     /* update return status */
01027     status =  HAL_ERROR;
01028   }
01029
01030   /* Release Lock */
01031   __HAL_UNLOCK(hnor);
01032   return status;
01033 }
01034
01035 /**
01036   * @brief  Unregister a User NOR Callback
01037   *         NOR Callback is redirected to the weak (surcharged) predefined callback
01038   * @param hnor : NOR handle
01039   * @param CallbackId : ID of the callback to be unregistered
01040   *        This parameter can be one of the following values:
01041   *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
01042   *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
01043   * @retval status
01044   */
01045 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
01046 {
01047   HAL_StatusTypeDef status = HAL_OK;
01048   HAL_NOR_StateTypeDef state;
01049
01050   /* Process locked */
01051   __HAL_LOCK(hnor);
01052
01053   state = hnor->State;
01054   if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
01055   {
01056     switch (CallbackId)
01057     {
01058     case HAL_NOR_MSP_INIT_CB_ID :
01059       hnor->MspInitCallback = HAL_NOR_MspInit;
01060       break;
01061     case HAL_NOR_MSP_DEINIT_CB_ID :
01062       hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
01063       break;
01064     default :
01065       /* update return status */
01066       status =  HAL_ERROR;
01067       break;
01068     }
01069   }
01070   else
01071   {
01072     /* update return status */
01073     status =  HAL_ERROR;
01074   }
01075
01076   /* Release Lock */
01077   __HAL_UNLOCK(hnor);
01078   return status;
01079 }
01080 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
01081
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
01087  *  @brief   management functions
01088  *
01089 @verbatim
01090   ==============================================================================
01091                         ##### NOR Control functions #####
01092   ==============================================================================
01093   [..]
01094     This subsection provides a set of functions allowing to control dynamically
01095     the NOR interface.
01096
01097 @endverbatim
01098   * @{
01099   */
01100
01101 /**
01102   * @brief  Enables dynamically NOR write operation.
01103   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01104   *                the configuration information for NOR module.
01105   * @retval HAL status
01106   */
01107 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
01108 {
01109   /* Check the NOR controller state */
01110   if(hnor->State == HAL_NOR_STATE_PROTECTED)
01111   {
01112     /* Process Locked */
01113     __HAL_LOCK(hnor);
01114
01115     /* Update the NOR controller state */
01116     hnor->State = HAL_NOR_STATE_BUSY;
01117
01118     /* Enable write operation */
01119     (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
01120
01121     /* Update the NOR controller state */
01122     hnor->State = HAL_NOR_STATE_READY;
01123
01124     /* Process unlocked */
01125     __HAL_UNLOCK(hnor);
01126   }
01127   else
01128   {
01129     return HAL_ERROR;
01130   }
01131
01132   return HAL_OK;
01133 }
01134
01135 /**
01136   * @brief  Disables dynamically NOR write operation.
01137   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01138   *                the configuration information for NOR module.
01139   * @retval HAL status
01140   */
01141 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
01142 {
01143   /* Check the NOR controller state */
01144   if(hnor->State == HAL_NOR_STATE_READY)
01145   {
01146     /* Process Locked */
01147     __HAL_LOCK(hnor);
01148
01149     /* Update the NOR controller state */
01150     hnor->State = HAL_NOR_STATE_BUSY;
01151
01152     /* Disable write operation */
01153     (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
01154
01155     /* Update the NOR controller state */
01156     hnor->State = HAL_NOR_STATE_PROTECTED;
01157
01158     /* Process unlocked */
01159     __HAL_UNLOCK(hnor);
01160   }
01161   else
01162   {
01163     return HAL_ERROR;
01164   }
01165
01166   return HAL_OK;
01167 }
01168
01169 /**
01170   * @}
01171   */
01172
01173 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
01174  *  @brief   Peripheral State functions
01175  *
01176 @verbatim
01177   ==============================================================================
01178                       ##### NOR State functions #####
01179   ==============================================================================
01180   [..]
01181     This subsection permits to get in run-time the status of the NOR controller
01182     and the data flow.
01183
01184 @endverbatim
01185   * @{
01186   */
01187
01188 /**
01189   * @brief  return the NOR controller state
01190   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01191   *                the configuration information for NOR module.
01192   * @retval NOR controller state
01193   */
01194 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
01195 {
01196   return hnor->State;
01197 }
01198
01199 /**
01200   * @brief  Returns the NOR operation status.
01201   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01202   *                the configuration information for NOR module.
01203   * @param  Address Device address
01204   * @param  Timeout NOR programming Timeout
01205   * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
01206   *         or HAL_NOR_STATUS_TIMEOUT
01207   */
01208 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
01209 {
01210   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
01211   uint16_t tmpSR1, tmpSR2;
01212   uint32_t tickstart;
01213
01214   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
01215   HAL_NOR_MspWait(hnor, Timeout);
01216
01217   /* Get the NOR memory operation status -------------------------------------*/
01218
01219   /* Get tick */
01220   tickstart = HAL_GetTick();
01221   while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
01222   {
01223     /* Check for the Timeout */
01224     if (Timeout != HAL_MAX_DELAY)
01225     {
01226       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01227       {
01228         status = HAL_NOR_STATUS_TIMEOUT;
01229       }
01230     }
01231
01232     /* Read NOR status register (DQ6 and DQ5) */
01233     tmpSR1 = *(__IO uint16_t *)Address;
01234     tmpSR2 = *(__IO uint16_t *)Address;
01235
01236     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01237     if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
01238     {
01239       return HAL_NOR_STATUS_SUCCESS ;
01240     }
01241
01242     if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01243     {
01244       status = HAL_NOR_STATUS_ONGOING;
01245     }
01246
01247     tmpSR1 = *(__IO uint16_t *)Address;
01248     tmpSR2 = *(__IO uint16_t *)Address;
01249
01250     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01251     if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
01252     {
01253       return HAL_NOR_STATUS_SUCCESS;
01254     }
01255     if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01256     {
01257       return HAL_NOR_STATUS_ERROR;
01258     }
01259   }
01260
01261   /* Return the operation status */
01262   return status;
01263 }
01264
01265 /**
01266   * @}
01267   */
01268
01269 /**
01270   * @}
01271   */
01272
01273 /**
01274   * @}
01275   */
01276
01277 #endif /* HAL_NOR_MODULE_ENABLED */
01278
01279 /**
01280   * @}
01281   */
01282
01283
01284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_nor.h Source File

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stm32h7xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NOR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   *
00011   * This software component is licensed by ST under BSD 3-Clause license,
00012   * the "License"; You may not use this file except in compliance with the
00013   * License. You may obtain a copy of the License at:
00014   *                       opensource.org/licenses/BSD-3-Clause
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32H7xx_HAL_NOR_H
00021 #define STM32H7xx_HAL_NOR_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_fmc.h"
00030
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup NOR
00037   * @{
00038   */
00039
00040 /* Exported typedef ----------------------------------------------------------*/
00041 /** @defgroup NOR_Exported_Types NOR Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL SRAM State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00051   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00052   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00053   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00054   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
00055 } HAL_NOR_StateTypeDef;
00056
00057 /**
00058   * @brief  FMC NOR Status typedef
00059   */
00060 typedef enum
00061 {
00062   HAL_NOR_STATUS_SUCCESS  = 0U,
00063   HAL_NOR_STATUS_ONGOING,
00064   HAL_NOR_STATUS_ERROR,
00065   HAL_NOR_STATUS_TIMEOUT
00066 } HAL_NOR_StatusTypeDef;
00067
00068 /**
00069   * @brief  FMC NOR ID typedef
00070   */
00071 typedef struct
00072 {
00073   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00074
00075   uint16_t Device_Code1;
00076
00077   uint16_t Device_Code2;
00078
00079   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00080                                     These codes can be accessed by performing read operations with specific
00081                                     control signals and addresses set.They can also be accessed by issuing
00082                                     an Auto Select command                                                   */
00083 } NOR_IDTypeDef;
00084
00085 /**
00086   * @brief  FMC NOR CFI typedef
00087   */
00088 typedef struct
00089 {
00090   /*!< Defines the information stored in the memory's Common flash interface
00091        which contains a description of various electrical and timing parameters,
00092        density information and functions supported by the memory                   */
00093
00094   uint16_t CFI_1;
00095
00096   uint16_t CFI_2;
00097
00098   uint16_t CFI_3;
00099
00100   uint16_t CFI_4;
00101 } NOR_CFITypeDef;
00102
00103 /**
00104   * @brief  NOR handle Structure definition
00105   */
00106 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00107 typedef struct __NOR_HandleTypeDef
00108 #else
00109 typedef struct
00110 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
00111
00112 {
00113   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00114
00115   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00116
00117   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00118
00119   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00120
00121   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00122
00123 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00124   void  (* MspInitCallback)        ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp Init callback              */
00125   void  (* MspDeInitCallback)      ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp DeInit callback            */
00126 #endif
00127 } NOR_HandleTypeDef;
00128
00129 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00130 /**
00131   * @brief  HAL NOR Callback ID enumeration definition
00132   */
00133 typedef enum
00134 {
00135   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
00136   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
00137 }HAL_NOR_CallbackIDTypeDef;
00138
00139 /**
00140   * @brief  HAL NOR Callback pointer definition
00141   */
00142 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
00143 #endif
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported constants --------------------------------------------------------*/
00149 /* Exported macro ------------------------------------------------------------*/
00150 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00151   * @{
00152   */
00153 /** @brief Reset NOR handle state
00154   * @param  __HANDLE__ specifies the NOR handle.
00155   * @retval None
00156   */
00157 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00158 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
00159                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
00160                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00161                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00162                                                              } while(0)
00163 #else
00164 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00165 #endif
00166 /**
00167   * @}
00168   */
00169
00170 /* Exported functions --------------------------------------------------------*/
00171 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00172   * @{
00173   */
00174
00175 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00176   * @{
00177   */
00178
00179 /* Initialization/de-initialization functions  ********************************/
00180 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00181 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00182 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00183 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00184 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00185 /**
00186   * @}
00187   */
00188
00189 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00190   * @{
00191   */
00192
00193 /* I/O operation functions  ***************************************************/
00194 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00195 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00196 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00197 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00198
00199 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00200 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00201
00202 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00203 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00204 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00205
00206 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00207 /* NOR callback registering/unregistering */
00208 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
00209 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
00210 #endif
00211 /**
00212   * @}
00213   */
00214
00215 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
00216   * @{
00217   */
00218
00219 /* NOR Control functions  *****************************************************/
00220 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00221 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00222 /**
00223   * @}
00224   */
00225
00226 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
00227   * @{
00228   */
00229
00230 /* NOR State functions ********************************************************/
00231 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00232 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00233 /**
00234   * @}
00235   */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /* Private types -------------------------------------------------------------*/
00242 /* Private variables ---------------------------------------------------------*/
00243 /* Private constants ---------------------------------------------------------*/
00244 /** @defgroup NOR_Private_Constants NOR Private Constants
00245   * @{
00246   */
00247 /* NOR device IDs addresses */
00248 #define MC_ADDRESS               ((uint16_t)0x0000U)
00249 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
00250 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
00251 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
00252
00253 /* NOR CFI IDs addresses */
00254 #define CFI1_ADDRESS             ((uint16_t)0x61U)
00255 #define CFI2_ADDRESS             ((uint16_t)0x62U)
00256 #define CFI3_ADDRESS             ((uint16_t)0x63U)
00257 #define CFI4_ADDRESS             ((uint16_t)0x64U)
00258
00259 /* NOR operation wait timeout */
00260 #define NOR_TMEOUT               ((uint16_t)0xFFFFU)
00261
00262 /* NOR memory data width */
00263 #define NOR_MEMORY_8B            ((uint8_t)0x0U)
00264 #define NOR_MEMORY_16B           ((uint8_t)0x1U)
00265
00266 /* NOR memory device read/write start address */
00267 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
00268 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
00269 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
00270 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
00271 /**
00272   * @}
00273   */
00274
00275 /* Private macros ------------------------------------------------------------*/
00276 /** @defgroup NOR_Private_Macros NOR Private Macros
00277   * @{
00278   */
00279 /**
00280   * @brief  NOR memory address shifting.
00281   * @param  __NOR_ADDRESS NOR base address
00282   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
00283   * @param  __ADDRESS__ NOR memory address
00284   * @retval NOR shifted address value
00285   */
00286 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
00287               ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
00288               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
00289               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00290
00291 /**
00292   * @brief  NOR memory write data to specified address.
00293   * @param  __ADDRESS__ NOR memory address
00294   * @param  __DATA__ Data to write
00295   * @retval None
00296   */
00297 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
00298                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
00299                                                __DSB();                                                    \
00300                                              } while(0)
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314
00315 #ifdef __cplusplus
00316 }
00317 #endif
00318
00319 #endif /* STM32H7xx_HAL_NOR_H */
00320
00321 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp.c Source File

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stm32h7xx_hal_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the operational amplifier(s) peripheral:
00008   *           + OPAMP configuration
00009   *           + OPAMP calibration
00010   *          Thanks to
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017 ================================================================================
00018           ##### OPAMP Peripheral Features #####
00019 ================================================================================
00020
00021   [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2
00022
00023        (#) The OPAMP(s) provides several exclusive running modes.
00024        (++) Standalone mode
00025        (++) Programmable Gain Amplifier (PGA) modes
00026        (++) Follower mode
00027
00028        (#) Each OPAMP(s) can be configured in normal and high speed mode.
00029
00030        (#) The OPAMP(s) provide(s) calibration capabilities.
00031        (++) Calibration aims at correcting some offset for running mode.
00032        (++) The OPAMP uses either factory calibration settings OR user defined
00033            calibration (trimming) settings (i.e. trimming mode).
00034        (++) The user defined settings can be figured out using self calibration
00035            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
00036        (++) HAL_OPAMP_SelfCalibrate:
00037        (+++) Runs automatically the calibration in 2 steps.
00038             (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
00039             (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
00040              appropriate and enough in most cases).
00041        (+++) Runs automatically the calibration.
00042        (+++) Enables the user trimming mode
00043        (+++) Updates the init structure with trimming values with fresh calibration
00044             results.
00045             The user may store the calibration results for larger
00046             (ex monitoring the trimming as a function of temperature
00047             for instance)
00048        (+++) HAL_OPAMPEx_SelfCalibrateAll
00049             runs calibration of all OPAMPs in parallel to save search time.
00050
00051        (#) Running mode: Standalone mode
00052        (++) Gain is set externally (gain depends on external loads).
00053        (++) Follower mode also possible externally by connecting the inverting input to
00054            the output.
00055
00056        (#) Running mode: Follower mode
00057        (++) No Inverting Input is connected.
00058
00059        (#) Running mode: Programmable Gain Amplifier (PGA) mode
00060            (Resistor feedback output)
00061        (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
00062            output.
00063        (#) OPAMP gain can be selected as :
00064
00065       (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
00066       (+++) VREF- referenced.
00067       (+++) Filtering on VINM0, VREF- referenced.
00068       (+++) VINM0 node for bias voltage and VINP0 for input signal.
00069       (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.
00070
00071       (##) Gain of x-1, x-3, x-7 or x-15 for inverting mode with:
00072       (+++) VINM0 node for input signal and VINP0 for bias.
00073       (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.
00074
00075        (#) The OPAMPs inverting input can be selected according to the Reference Manual
00076            "OPAMP functional description" chapter.
00077
00078        (#) The OPAMPs non inverting input can be selected according to the Reference Manual
00079            "OPAMP functional description" chapter.
00080
00081
00082             ##### How to use this driver #####
00083 ================================================================================
00084   [..]
00085
00086     *** High speed / normal power mode ***
00087     ============================================
00088     [..]  To run in high speed mode:
00089
00090       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00091       (++) Select OPAMP_POWERMODE_HIGHSPEED
00092       (++) Otherwise select OPAMP_POWERMODE_NORMAL
00093
00094     *** Calibration ***
00095     ============================================
00096     [..]  To run the OPAMP calibration self calibration:
00097
00098       (#) Start calibration using HAL_OPAMP_SelfCalibrate.
00099            Store the calibration results.
00100
00101     *** Running mode ***
00102     ============================================
00103
00104     [..]  To use the OPAMP, perform the following steps:
00105
00106       (#) Fill in the HAL_OPAMP_MspInit() to
00107       (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
00108       (++) Configure the OPAMP input AND output in analog mode using
00109            HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
00110
00111       (#) Registrate Callbacks
00112       (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
00113            allows the user to configure dynamically the driver callbacks.
00114
00115       (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
00116            it allows to register following callbacks:
00117       (+++) MspInitCallback         : OPAMP MspInit.
00118       (+++) MspDeInitCallback       : OPAMP MspDeInit.
00119            This function takes as parameters the HAL peripheral handle, the Callback ID
00120            and a pointer to the user callback function.
00121
00122       (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
00123            weak (surcharged) function. It allows to reset following callbacks:
00124       (+++) MspInitCallback         : OPAMP MspInit.
00125       (+++) MspDeInitCallback       : OPAMP MspDeInit.
00126       (+++) All Callbacks
00127       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00128       (++) Select the mode
00129       (++) Select the inverting input
00130       (++) Select the non-inverting input
00131       (++) If PGA mode is enabled, Select if inverting input is connected.
00132       (++) Select either factory or user defined trimming mode.
00133       (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
00134           (typically values set by HAL_OPAMP_SelfCalibrate function).
00135
00136       (#) Enable the OPAMP using HAL_OPAMP_Start() function.
00137
00138       (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
00139
00140       (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
00141           Caution: On STM32H7, HAL OPAMP lock is software lock only (not
00142           hardware lock as on some other STM32 devices)
00143
00144       (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
00145
00146     *** Running mode: change of configuration while OPAMP ON  ***
00147     ============================================
00148     [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
00149       (#) If needed, fill in the HAL_OPAMP_MspInit()
00150       (++) This is the case for instance if you wish to use new OPAMP I/O
00151
00152       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00153       (++) As in configure case, select first the parameters you wish to modify.
00154
00155       (#) Change from high speed mode to normal power mode (& vice versa) requires
00156           first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
00157           In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
00158           alone.
00159
00160   @endverbatim
00161   ******************************************************************************
00162     Table 1.  OPAMPs inverting/non-inverting inputs for the STM32H7 devices:
00163
00164     +------------------------------------------------------------------------|
00165     |                 |         | OPAMP1               | OPAMP2              |
00166     |-----------------|---------|----------------------|---------------------|
00167     | Inverting Input | VM_SEL  |   VINM0-> PC5        |    VINM0-> PE8      |
00168     |                 |         |   VINM1-> PA7        |    VINM1-> PG1      |
00169     |                 |         |   Internal:          |    Internal:        |
00170     |                 |         |     ADC1_IN9         |      OPAMP2_OUT     |
00171     |                 |         |     ADC2_IN9         |     PGA mode        |
00172     |                 |         |     OPAMP1_OUT       |                     |
00173     |                 |         |     PGA mode         |                     |
00174     |-----------------|---------|----------------------|---------------------|
00175     |  Non Inverting  | VP_SEL  |                      |                     |
00176     |                 |         |  VP0 -> PB0 (GPIO)   |  VP0 -> PE9 (GPIO)  |
00177     |                 |         |  Internal:           |  Internal:          |
00178     |    Input        |         |    DAC1_CH1_int      |   DAC1_CH2_int      |
00179     |                 |         |    ADC1_IN8          |   DAC2_CH1_int      |
00180     |                 |         |    ADC2_IN8          |   COMP2_INP         |
00181     |                 |         |    COMP1_INP         |                     |
00182     +------------------------------------------------------------------------|
00183
00184
00185    [..] Table 2.  OPAMPs outputs for the STM32H7 devices:
00186
00187     +-------------------------------------------------------------------------
00188     |                 |        | OPAMP1                | OPAMP2              |
00189     |-----------------|--------|-----------------------|---------------------|
00190     | Output          |  VOUT  |  PC4                  |  PE7                |
00191     |                 |        |  & ADC1_IN4|          | & COMP2_INN7 if     |
00192     |                 |        |    ADC2_IN4           |connected internally |
00193     |                 |        |   COMP1_INN7 if       |                     |
00194     |                 |        |  connected internally |                     |
00195     |-----------------|--------|-----------------------|---------------------|
00196   ******************************************************************************
00197   * @attention
00198   *
00199   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00200   * All rights reserved.</center></h2>
00201   *
00202   * This software component is licensed by ST under BSD 3-Clause license,
00203   * the "License"; You may not use this file except in compliance with the
00204   * License. You may obtain a copy of the License at:
00205   *                        opensource.org/licenses/BSD-3-Clause
00206   *
00207   ******************************************************************************
00208   */
00209
00210 /* Includes ------------------------------------------------------------------*/
00211 #include "stm32h7xx_hal.h"
00212
00213 /** @addtogroup STM32H7xx_HAL_Driver
00214   * @{
00215   */
00216
00217 /** @defgroup OPAMP OPAMP
00218   * @brief OPAMP module driver
00219   * @{
00220   */
00221
00222 #ifdef HAL_OPAMP_MODULE_ENABLED
00223
00224 /* Private types -------------------------------------------------------------*/
00225 /* Private variables ---------------------------------------------------------*/
00226 /* Private constants ---------------------------------------------------------*/
00227 /** @addtogroup OPAMP_Private_Constants
00228   * @{
00229   */
00230
00231 /* CSR register reset value */
00232 #define OPAMP_CSR_RESET_VALUE             0x00000000U
00233
00234 /* CSR Init masks */
00235
00236 #define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_PGGAIN | OPAMP_CSR_PGGAIN  \
00237                                 | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)
00238
00239
00240 #define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
00241                                     | OPAMP_CSR_USERTRIM)
00242
00243
00244 #define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
00245                                        | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
00246 /**
00247   * @}
00248   */
00249
00250 /* Private macros ------------------------------------------------------------*/
00251 /* Private functions ---------------------------------------------------------*/
00252 /* Exported functions --------------------------------------------------------*/
00253
00254 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00255   * @{
00256   */
00257
00258 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00259  *  @brief    Initialization and Configuration functions
00260  *
00261 @verbatim
00262   ==============================================================================
00263               ##### Initialization and de-initialization functions #####
00264   ==============================================================================
00265
00266 @endverbatim
00267   * @{
00268   */
00269
00270 /**
00271   * @brief  Initialize the OPAMP according to the specified
00272   *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.
00273   * @note   If the selected opamp is locked, initialization can't be performed.
00274   *         To unlock the configuration, perform a system reset.
00275   * @param  hopamp OPAMP handle
00276   * @retval HAL status
00277   */
00278 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
00279 {
00280   HAL_StatusTypeDef status = HAL_OK;
00281   uint32_t updateotrlpotr;
00282
00283   /* Check the OPAMP handle allocation and lock status */
00284   /* Init not allowed if calibration is ongoing */
00285   if(hopamp == NULL)
00286   {
00287     return HAL_ERROR;
00288   }
00289   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00290   {
00291     return HAL_ERROR;
00292   }
00293   else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00294   {
00295     return HAL_ERROR;
00296   }
00297   else
00298   {
00299     /* Check the parameter */
00300     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00301
00302     /* Set OPAMP parameters */
00303     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00304     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
00305     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
00306
00307 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00308     if(hopamp->State == HAL_OPAMP_STATE_RESET)
00309     {
00310       if(hopamp->MspInitCallback == NULL)
00311       {
00312         hopamp->MspInitCallback               = HAL_OPAMP_MspInit;
00313       }
00314     }
00315 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00316     if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00317     {
00318       assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
00319     }
00320
00321     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00322     {
00323       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
00324       assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
00325     }
00326
00327
00328     assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
00329
00330     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
00331     {
00332       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00333       {
00334         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
00335         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
00336       }
00337     else
00338       {
00339         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePHighSpeed));
00340         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNHighSpeed));
00341       }
00342     }
00343
00344     if(hopamp->State == HAL_OPAMP_STATE_RESET)
00345     {
00346       /* Allocate lock resource and initialize it */
00347       hopamp->Lock = HAL_UNLOCKED;
00348     }
00349
00350 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00351     hopamp->MspInitCallback(hopamp);
00352 #else
00353     /* Call MSP init function */
00354     HAL_OPAMP_MspInit(hopamp);
00355 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00356
00357     /* Set operating mode */
00358     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
00359     /* In PGA mode InvertingInput is Not Applicable  */
00360     if (hopamp->Init.Mode == OPAMP_PGA_MODE)
00361     {
00362       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
00363                                         hopamp->Init.PowerMode | \
00364                                         hopamp->Init.Mode | \
00365                                         hopamp->Init.PgaGain | \
00366                                         hopamp->Init.PgaConnect | \
00367                                         hopamp->Init.NonInvertingInput | \
00368                                         hopamp->Init.UserTrimming);
00369     }
00370
00371     if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
00372     {
00373   /* In Follower mode InvertingInput is Not Applicable  */
00374     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
00375                                               hopamp->Init.PowerMode | \
00376                                               hopamp->Init.Mode | \
00377                                               hopamp->Init.NonInvertingInput | \
00378                                               hopamp->Init.UserTrimming);
00379     }
00380
00381     if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
00382     {
00383       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
00384                                         hopamp->Init.PowerMode | \
00385                                         hopamp->Init.Mode | \
00386                                         hopamp->Init.InvertingInput    | \
00387                                         hopamp->Init.NonInvertingInput | \
00388                                         hopamp->Init.UserTrimming);
00389     }
00390
00391     if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
00392     {
00393       /* Set power mode and associated calibration parameters */
00394       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00395       {
00396         /* OPAMP_POWERMODE_NORMAL */
00397         /* Set calibration mode (factory or user) and values for            */
00398         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00399         /* normal mode.                                                     */
00400         updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
00401                          | (hopamp->Init.TrimmingValueN));
00402         MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00403       }
00404       else
00405       {
00406         /* OPAMP_POWERMODE_HIGHSPEED*/
00407         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00408         /* high speed mode.                                                     */
00409         updateotrlpotr = (((hopamp->Init.TrimmingValuePHighSpeed) << (OPAMP_INPUT_NONINVERTING)) \
00410                          | (hopamp->Init.TrimmingValueNHighSpeed));
00411         MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00412       }
00413     }
00414
00415     /* Update the OPAMP state*/
00416     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00417     {
00418       /* From RESET state to READY State */
00419       hopamp->State = HAL_OPAMP_STATE_READY;
00420     }
00421     /* else: remain in READY or BUSY state (no update) */
00422     return status;
00423   }
00424 }
00425
00426 /**
00427   * @brief  DeInitialize the OPAMP peripheral
00428   * @note   Deinitialization can be performed if the OPAMP configuration is locked.
00429   *         (the lock is SW in H7)
00430   * @param  hopamp OPAMP handle
00431   * @retval HAL status
00432   */
00433 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
00434 {
00435   HAL_StatusTypeDef status = HAL_OK;
00436
00437   /* Check the OPAMP handle allocation */
00438   /* DeInit not allowed if calibration is on going */
00439   if(hopamp == NULL)
00440   {
00441     status = HAL_ERROR;
00442   }
00443   else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00444   {
00445     status = HAL_ERROR;
00446   }
00447   else
00448   {
00449     /* Check the parameter */
00450     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00451
00452     /* Set OPAMP_CSR register to reset value */
00453     WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
00454
00455     /* DeInit the low level hardware */
00456 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00457     if(hopamp->MspDeInitCallback == NULL)
00458     {
00459       hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
00460     }
00461     /* DeInit the low level hardware */
00462     hopamp->MspDeInitCallback(hopamp);
00463 #else
00464     HAL_OPAMP_MspDeInit(hopamp);
00465 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00466
00467     /* Update the OPAMP state*/
00468     hopamp->State = HAL_OPAMP_STATE_RESET;
00469     /* Process unlocked */
00470     __HAL_UNLOCK(hopamp);
00471
00472   }
00473
00474   return status;
00475 }
00476
00477
00478 /**
00479   * @brief  Initialize the OPAMP MSP.
00480   * @param  hopamp OPAMP handle
00481   * @retval None
00482   */
00483 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
00484 {
00485   /* Prevent unused argument(s) compilation warning */
00486   UNUSED(hopamp);
00487
00488   /* NOTE : This function should not be modified, when the callback is needed,
00489             the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
00490    */
00491 }
00492
00493 /**
00494   * @brief  DeInitialize OPAMP MSP.
00495   * @param  hopamp OPAMP handle
00496   * @retval None
00497   */
00498 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
00499 {
00500   /* Prevent unused argument(s) compilation warning */
00501   UNUSED(hopamp);
00502   /* NOTE : This function should not be modified, when the callback is needed,
00503             the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
00504    */
00505 }
00506
00507 /**
00508   * @}
00509   */
00510
00511
00512 /** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
00513  *  @brief   IO operation functions
00514  *
00515 @verbatim
00516  ===============================================================================
00517                         ##### IO operation functions #####
00518  ===============================================================================
00519     [..]
00520     This subsection provides a set of functions allowing to manage the OPAMP
00521     start, stop and calibration actions.
00522
00523 @endverbatim
00524   * @{
00525   */
00526
00527 /**
00528   * @brief  Start the OPAMP.
00529   * @param  hopamp OPAMP handle
00530   * @retval HAL status
00531   */
00532 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
00533 {
00534   HAL_StatusTypeDef status = HAL_OK;
00535
00536   /* Check the OPAMP handle allocation */
00537   /* Check if OPAMP locked */
00538   if(hopamp == NULL)
00539   {
00540     status = HAL_ERROR;
00541   }
00542   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00543   {
00544     status = HAL_ERROR;
00545   }
00546   else
00547   {
00548     /* Check the parameter */
00549     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00550
00551     if(hopamp->State == HAL_OPAMP_STATE_READY)
00552     {
00553       /* Enable the selected opamp */
00554       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00555
00556       /* Update the OPAMP state*/
00557       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
00558       hopamp->State = HAL_OPAMP_STATE_BUSY;
00559     }
00560     else
00561     {
00562       status = HAL_ERROR;
00563     }
00564
00565    }
00566   return status;
00567 }
00568
00569 /**
00570   * @brief  Stop the OPAMP.
00571   * @param  hopamp OPAMP handle
00572   * @retval HAL status
00573   */
00574 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
00575 {
00576   HAL_StatusTypeDef status = HAL_OK;
00577
00578   /* Check the OPAMP handle allocation */
00579   /* Check if OPAMP locked */
00580   /* Check if OPAMP calibration ongoing */
00581   if(hopamp == NULL)
00582   {
00583     status = HAL_ERROR;
00584   }
00585   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00586   {
00587     status = HAL_ERROR;
00588   }
00589   else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00590   {
00591     status = HAL_ERROR;
00592   }
00593   else
00594   {
00595     /* Check the parameter */
00596     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00597
00598     if(hopamp->State == HAL_OPAMP_STATE_BUSY)
00599     {
00600       /* Disable the selected opamp */
00601       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00602
00603       /* Update the OPAMP state*/
00604       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
00605       hopamp->State = HAL_OPAMP_STATE_READY;
00606     }
00607     else
00608     {
00609       status = HAL_ERROR;
00610     }
00611   }
00612   return status;
00613 }
00614
00615 /**
00616   * @brief  Run the self calibration of one OPAMP.
00617   * @note   Calibration is performed in the mode specified in OPAMP init
00618   *         structure (mode normal or high-speed). To perform calibration for
00619   *         both modes, repeat this function twice after OPAMP init structure
00620   *         accordingly updated.
00621   * @param  hopamp handle
00622   * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00623   * @retval HAL status
00624   */
00625 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
00626 {
00627
00628   HAL_StatusTypeDef status = HAL_OK;
00629
00630   uint32_t trimmingvaluen;
00631   uint32_t trimmingvaluep;
00632   uint32_t delta;
00633   uint32_t opampmode;
00634
00635   __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or HSOTR */
00636
00637   /* Check the OPAMP handle allocation */
00638   /* Check if OPAMP locked */
00639   if(hopamp == NULL)
00640   {
00641     status = HAL_ERROR;
00642   }
00643   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00644   {
00645     status = HAL_ERROR;
00646   }
00647   else
00648   {
00649
00650     /* Check if OPAMP in calibration mode and calibration not yet enable */
00651     if(hopamp->State ==  HAL_OPAMP_STATE_READY)
00652     {
00653       /* Check the parameter */
00654       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00655       assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00656
00657       opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_VMSEL);
00658
00659       /* Use of standalone mode */
00660       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00661       /*  user trimming values are used for offset calibration */
00662       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00663
00664       /* Select trimming settings depending on power mode */
00665       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00666       {
00667         tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
00668
00669       }
00670       else
00671       {
00672         /* high speed Mode */
00673         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
00674       }
00675
00676
00677       /* Enable calibration */
00678       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00679
00680       /* Force internal reference on VP */
00681       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00682
00683       /* 1st calibration - N */
00684       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00685
00686       /* Enable the selected opamp */
00687       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00688
00689       /* Init trimming counter */
00690       /* Medium value */
00691       trimmingvaluen = 16U;
00692       delta = 8U;
00693
00694       while (delta != 0U)
00695       {
00696         /* Set candidate trimming */
00697         /* OPAMP_POWERMODE_NORMAL */
00698         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00699
00700         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00701         /* Offset trim time: during calibration, minimum time needed between */
00702         /* two steps to have 1 mV accuracy */
00703         HAL_Delay(OPAMP_TRIMMING_DELAY);
00704
00705         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
00706         {
00707           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00708           trimmingvaluen += delta;
00709         }
00710         else
00711         {
00712           /* OPAMP_CSR_CALOUT is LOW try lower trimming */
00713           trimmingvaluen -= delta;
00714         }
00715         /* Divide range by 2 to continue dichotomy sweep */
00716         delta >>= 1;
00717       }
00718
00719       /* Still need to check if right calibration is current value or one step below */
00720       /* Indeed the first value that causes the OUTCAL bit to change from 1  to 0  */
00721
00722       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00723
00724       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00725       /* Offset trim time: during calibration, minimum time needed between */
00726       /* two steps to have 1 mV accuracy */
00727       HAL_Delay(OPAMP_TRIMMING_DELAY);
00728
00729       if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
00730       {
00731         /* Trimming value is actually one value more */
00732         trimmingvaluen++;
00733         /* Set right trimming */
00734         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00735       }
00736
00737       /* 2nd calibration - P */
00738       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00739
00740       /* Init trimming counter */
00741       /* Medium value */
00742       trimmingvaluep = 16U;
00743       delta = 8U;
00744
00745       while (delta != 0U)
00746       {
00747         /* Set candidate trimming */
00748         /* OPAMP_POWERMODE_NORMAL */
00749         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00750
00751         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00752         /* Offset trim time: during calibration, minimum time needed between */
00753         /* two steps to have 1 mV accuracy */
00754         HAL_Delay(OPAMP_TRIMMING_DELAY);
00755
00756         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00757         {
00758           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00759           trimmingvaluep += delta;
00760         }
00761         else
00762         {
00763           /* OPAMP_CSR_CALOUT  is LOW try lower trimming */
00764           trimmingvaluep -= delta;
00765         }
00766
00767         /* Divide range by 2 to continue dichotomy sweep */
00768         delta >>= 1U;
00769       }
00770
00771       /* Still need to check if right calibration is current value or one step below */
00772       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00773       /* Set candidate trimming */
00774       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00775
00776       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00777       /* Offset trim time: during calibration, minimum time needed between */
00778       /* two steps to have 1 mV accuracy */
00779       HAL_Delay(OPAMP_TRIMMING_DELAY);
00780
00781       if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
00782       {
00783         /* Trimming value is actually one value more */
00784         trimmingvaluep++;
00785         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00786       }
00787
00788       /* Disable calibration & set normal mode (operating mode) */
00789       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00790
00791       /* Disable the OPAMP */
00792       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00793
00794       /* Set operating mode back */
00795       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00796
00797       /* Self calibration is successful  */
00798       /* Store calibration(user trimming) results in init structure. */
00799
00800       /* Set user trimming mode */
00801       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
00802
00803       /* Affect calibration parameters depending on mode normal/high speed */
00804       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00805       {
00806         /* Write calibration result N */
00807         hopamp->Init.TrimmingValueN = trimmingvaluen;
00808         /* Write calibration result P */
00809         hopamp->Init.TrimmingValueP = trimmingvaluep;
00810       }
00811       else
00812       {
00813         /* Write calibration result N */
00814         hopamp->Init.TrimmingValueNHighSpeed = trimmingvaluen;
00815         /* Write calibration result P */
00816         hopamp->Init.TrimmingValuePHighSpeed = trimmingvaluep;
00817       }
00818     /* Restore OPAMP mode after calibration */
00819     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, opampmode);
00820     }
00821
00822     else
00823     {
00824       /* OPAMP can not be calibrated from this mode */
00825       status = HAL_ERROR;
00826     }
00827   }
00828   return status;
00829 }
00830
00831 /**
00832   * @}
00833   */
00834
00835 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00836  *  @brief   Peripheral Control functions
00837  *
00838 @verbatim
00839  ===============================================================================
00840                       ##### Peripheral Control functions #####
00841  ===============================================================================
00842     [..]
00843     This subsection provides a set of functions allowing to control the OPAMP data
00844     transfers.
00845
00846
00847
00848 @endverbatim
00849   * @{
00850   */
00851
00852 /**
00853   * @brief  Lock the selected OPAMP configuration.
00854   * @note   On STM32H7, HAL OPAMP lock is software lock only (in
00855   *         contrast of hardware lock available on some other STM32
00856   *         devices)
00857   * @param  hopamp OPAMP handle
00858   * @retval HAL status
00859   */
00860 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
00861 {
00862   HAL_StatusTypeDef status = HAL_OK;
00863
00864   /* Check the OPAMP handle allocation */
00865   /* Check if OPAMP locked */
00866   /* OPAMP can be locked when enabled and running in normal mode */
00867   /*   It is meaningless otherwise */
00868   if(hopamp == NULL)
00869   {
00870     status = HAL_ERROR;
00871   }
00872
00873   else if(hopamp->State != HAL_OPAMP_STATE_BUSY)
00874   {
00875     status = HAL_ERROR;
00876   }
00877   else
00878   {
00879     /* Check the parameter */
00880     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00881
00882    /* OPAMP state changed to locked */
00883     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
00884   }
00885   return status;
00886 }
00887
00888 /**
00889   * @brief  Return the OPAMP factory trimming value.
00890   * @note            On STM32H7 OPAMP, user can retrieve factory trimming if
00891   *                  OPAMP has never been set to user trimming before.
00892   *                  Therefore, this function must be called when OPAMP init
00893   *                  parameter "UserTrimming" is set to trimming factory,
00894   *                  and before OPAMP  calibration (function
00895   *                  "HAL_OPAMP_SelfCalibrate()").
00896   *                  Otherwise, factory trimming value cannot be retrieved and
00897   *                  error status is returned.
00898   * @param  hopamp  OPAMP handle
00899   * @param  trimmingoffset  Trimming offset (P or N)
00900   *         This parameter must be a value of @ref OPAMP_FactoryTrimming
00901   * @note   Calibration parameter retrieved is corresponding to the mode
00902   *         specified in OPAMP init structure (mode normal or high-speed).
00903   *         To retrieve calibration parameters for both modes, repeat this
00904   *         function after OPAMP init structure accordingly updated.
00905   * @retval Trimming value (P or N): range: 0->31
00906   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
00907   *
00908   */
00909 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
00910 {
00911   HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
00912   __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
00913
00914   /* Check the OPAMP handle allocation */
00915   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
00916   if(hopamp == NULL)
00917   {
00918     return OPAMP_FACTORYTRIMMING_DUMMY;
00919   }
00920
00921   if(hopamp->State == HAL_OPAMP_STATE_READY)
00922   {
00923     /* Check the parameter */
00924     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00925     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
00926     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00927
00928     /* Check the trimming mode */
00929     if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= 0U)
00930     {
00931       /* This function must called when OPAMP init parameter "UserTrimming"   */
00932       /* is set to trimming factory, and before OPAMP calibration (function   */
00933       /* "HAL_OPAMP_SelfCalibrate()").                                        */
00934       /* Otherwise, factory trimming value cannot be retrieved and error       */
00935       /* status is returned.                                                  */
00936       trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
00937     }
00938     else
00939     {
00940       /* Select trimming settings depending on power mode */
00941       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00942       {
00943         tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
00944       }
00945       else
00946       {
00947         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
00948       }
00949
00950       /* Get factory trimming  */
00951       if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
00952       {
00953         /* OPAMP_FACTORYTRIMMING_P */
00954         trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
00955       }
00956       else
00957       {
00958         /* OPAMP_FACTORYTRIMMING_N */
00959         trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
00960       }
00961     }
00962   }
00963   else
00964   {
00965     return OPAMP_FACTORYTRIMMING_DUMMY;
00966   }
00967
00968   return trimmingvalue;
00969 }
00970
00971 /**
00972   * @}
00973   */
00974
00975
00976 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00977  *  @brief   Peripheral State functions
00978  *
00979 @verbatim
00980  ===============================================================================
00981                       ##### Peripheral State functions #####
00982  ===============================================================================
00983     [..]
00984     This subsection permits to get in run-time the status of the peripheral.
00985
00986 @endverbatim
00987   * @{
00988   */
00989
00990 /**
00991   * @brief  Return the OPAMP handle state.
00992   * @param  hopamp  OPAMP handle
00993   * @retval HAL state
00994   */
00995 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
00996 {
00997   /* Check the OPAMP handle allocation */
00998   if(hopamp == NULL)
00999   {
01000     return HAL_OPAMP_STATE_RESET;
01001   }
01002
01003   /* Check the parameter */
01004   assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
01005
01006  /* Return OPAMP handle state */
01007   return hopamp->State;
01008 }
01009
01010 /**
01011   * @}
01012   */
01013
01014 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
01015 /**
01016   * @brief  Register a User OPAMP Callback
01017   *         To be used instead of the weak (surcharged) predefined callback
01018   * @param hopamp  OPAMP handle
01019   * @param CallbackId  ID of the callback to be registered
01020   *        This parameter can be one of the following values:
01021   *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID       OPAMP MspInit callback ID
01022   *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID     OPAMP MspDeInit callback ID
01023   * @param pCallback  pointer to the Callback function
01024   * @retval status
01025   */
01026 HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
01027 {
01028   HAL_StatusTypeDef status = HAL_OK;
01029
01030   if(pCallback == NULL)
01031   {
01032     return HAL_ERROR;
01033   }
01034
01035   /* Process locked */
01036   __HAL_LOCK(hopamp);
01037
01038   if(hopamp->State == HAL_OPAMP_STATE_READY)
01039   {
01040     switch (CallbackId)
01041     {
01042     case HAL_OPAMP_MSPINIT_CB_ID :
01043       hopamp->MspInitCallback = pCallback;
01044       break;
01045     case HAL_OPAMP_MSPDEINIT_CB_ID :
01046       hopamp->MspDeInitCallback = pCallback;
01047       break;
01048     default :
01049       /* update return status */
01050       status =  HAL_ERROR;
01051       break;
01052     }
01053   }
01054   else if (hopamp->State == HAL_OPAMP_STATE_RESET)
01055   {
01056     switch (CallbackId)
01057     {
01058     case HAL_OPAMP_MSPINIT_CB_ID :
01059       hopamp->MspInitCallback = pCallback;
01060       break;
01061     case HAL_OPAMP_MSPDEINIT_CB_ID :
01062       hopamp->MspDeInitCallback = pCallback;
01063       break;
01064     default :
01065       /* update return status */
01066       status =  HAL_ERROR;
01067       break;
01068     }
01069   }
01070   else
01071   {
01072     /* update return status */
01073     status =  HAL_ERROR;
01074   }
01075
01076   /* Release Lock */
01077   __HAL_UNLOCK(hopamp);
01078   return status;
01079 }
01080
01081 /**
01082   * @brief  Unregister a User OPAMP Callback
01083   *         OPAMP Callback is redirected to the weak (surcharged) predefined callback
01084   * @param hopamp  OPAMP handle
01085   * @param CallbackId  ID of the callback to be unregistered
01086   *        This parameter can be one of the following values:
01087   *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID    OPAMP MSP Init Callback ID
01088   *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID  OPAMP MSP DeInit Callback ID
01089   *          @arg @ref HAL_OPAMP_ALL_CB_ID        OPAMP All Callbacks
01090   * @retval status
01091   */
01092 HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
01093 {
01094   HAL_StatusTypeDef status = HAL_OK;
01095
01096   /* Process locked */
01097   __HAL_LOCK(hopamp);
01098
01099   if(hopamp->State == HAL_OPAMP_STATE_READY)
01100   {
01101     switch (CallbackId)
01102     {
01103     case HAL_OPAMP_MSPINIT_CB_ID :
01104       hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01105       break;
01106     case HAL_OPAMP_MSPDEINIT_CB_ID :
01107       hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01108       break;
01109     case HAL_OPAMP_ALL_CB_ID :
01110       hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01111       hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01112       break;
01113     default :
01114       /* update return status */
01115       status =  HAL_ERROR;
01116       break;
01117     }
01118   }
01119   else if (hopamp->State == HAL_OPAMP_STATE_RESET)
01120   {
01121     switch (CallbackId)
01122     {
01123     case HAL_OPAMP_MSPINIT_CB_ID :
01124       hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01125       break;
01126     case HAL_OPAMP_MSPDEINIT_CB_ID :
01127       hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01128       break;
01129     default :
01130       /* update return status */
01131       status =  HAL_ERROR;
01132       break;
01133     }
01134   }
01135   else
01136   {
01137     /* update return status */
01138     status =  HAL_ERROR;
01139   }
01140
01141   /* Release Lock */
01142   __HAL_UNLOCK(hopamp);
01143   return status;
01144 }
01145
01146 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
01147   /**
01148   * @}
01149   */
01150
01151 /**
01152   * @}
01153   */
01154 #endif /* HAL_OPAMP_MODULE_ENABLED */
01155 /**
01156   * @}
01157   */
01158
01159 /**
01160   * @}
01161   */
01162
01163 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp.h Source File

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stm32h7xx_hal_opamp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_OPAMP_H
00022 #define STM32H7xx_HAL_OPAMP_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup OPAMP
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup OPAMP_Exported_Types OPAMP Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  OPAMP Init structure definition
00047   */
00048
00049 typedef struct
00050 {
00051
00052   uint32_t PowerMode;                   /*!< Specifies the power mode Normal or High Speed.
00053                                              This parameter must be a value of @ref OPAMP_PowerMode */
00054
00055   uint32_t Mode;                        /*!< Specifies the OPAMP mode
00056                                              This parameter must be a value of @ref OPAMP_Mode
00057                                              mode is either Standalone, - Follower or PGA */
00058
00059   uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes
00060                                              - In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE
00061                                                  This parameter must be a value of @ref OPAMP_InvertingInput
00062                                              - In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
00063                                            & In PGA mode i.e when mode is OPAMP_PGA_MODE
00064                                                  This parameter is Not Applicable */
00065
00066   uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
00067                                              This parameter must be a value of @ref OPAMP_NonInvertingInput */
00068
00069   uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
00070                                              i.e. when mode is OPAMP_PGA_MODE.
00071                                              This parameter must be a value of @ref OPAMP_PgaGain */
00072
00073   uint32_t PgaConnect;                  /*!< Specifies the inverting pin in PGA mode
00074                                              i.e. when mode is OPAMP_PGA_MODE
00075                                              This parameter must be a value of @ref OPAMP_PgaConnect
00076                                              Either: not connected, connected to VINM0, connected to VINM1
00077                                              (VINM0 or VINM1 are typically used for external filtering) */
00078
00079   uint32_t UserTrimming;                /*!< Specifies the trimming mode
00080                                              This parameter must be a value of @ref OPAMP_UserTrimming
00081                                              UserTrimming is either factory or user trimming.*/
00082
00083   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS) in Normal Mode
00084                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00085                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00086                                              16 is typical default value */
00087
00088   uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS) in Normal Mode
00089                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00090                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00091                                              16 is typical default value */
00092
00093   uint32_t TrimmingValuePHighSpeed;      /*!< Specifies the offset trimming value (PMOS) in High Speed Mode
00094                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00095                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00096                                              16 is typical default value */
00097
00098   uint32_t TrimmingValueNHighSpeed;      /*!< Specifies the offset trimming value (NMOS) in High Speed Mode
00099                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00100                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00101                                              16 is typical default value */
00102
00103 }OPAMP_InitTypeDef;
00104
00105 /**
00106   * @brief  HAL State structures definition
00107   */
00108
00109 typedef enum
00110 {
00111   HAL_OPAMP_STATE_RESET               = 0x00000000U, /*!< OPAMP is not yet Initialized          */
00112
00113   HAL_OPAMP_STATE_READY               = 0x00000001U, /*!< OPAMP is initialized and ready for use */
00114   HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
00115
00116   HAL_OPAMP_STATE_BUSY                = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
00117   HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005U  /*!< OPAMP is locked
00118                                                          only system reset allows reconfiguring the opamp. */
00119
00120 }HAL_OPAMP_StateTypeDef;
00121
00122 /**
00123   * @brief OPAMP Handle Structure definition
00124   */
00125 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00126 typedef struct __OPAMP_HandleTypeDef
00127 #else
00128 typedef struct
00129 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00130 {
00131   OPAMP_TypeDef                 *Instance;                    /*!< OPAMP instance's registers base address */
00132   OPAMP_InitTypeDef              Init;                         /*!< OPAMP required parameters */
00133   HAL_StatusTypeDef              Status;                       /*!< OPAMP peripheral status   */
00134   HAL_LockTypeDef                Lock;                         /*!< Locking object          */
00135   __IO HAL_OPAMP_StateTypeDef    State;                        /*!< OPAMP communication state */
00136
00137 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00138 void (* MspInitCallback)                (struct __OPAMP_HandleTypeDef *hopamp);
00139 void (* MspDeInitCallback)              (struct __OPAMP_HandleTypeDef *hopamp);
00140 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00141 } OPAMP_HandleTypeDef;
00142
00143 /**
00144   * @brief HAl_OPAMP_TrimmingValueTypeDef definition
00145   */
00146
00147 typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
00148
00149 /**
00150   * @}
00151   */
00152
00153 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00154 /**
00155   * @brief  HAL OPAMP Callback ID enumeration definition
00156   */
00157 typedef enum
00158 {
00159   HAL_OPAMP_MSPINIT_CB_ID                     = 0x01U,  /*!< OPAMP MspInit Callback ID           */
00160   HAL_OPAMP_MSPDEINIT_CB_ID                   = 0x02U,  /*!< OPAMP MspDeInit Callback ID         */
00161   HAL_OPAMP_ALL_CB_ID                         = 0x03U   /*!< OPAMP All ID                        */
00162 }HAL_OPAMP_CallbackIDTypeDef;
00163
00164 /**
00165   * @brief  HAL OPAMP Callback pointer definition
00166   */
00167 typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
00168 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00169
00170
00171 /* Exported constants --------------------------------------------------------*/
00172 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
00173   * @{
00174   */
00175
00176 /** @defgroup OPAMP_Mode OPAMP Mode
00177   * @{
00178   */
00179 #define OPAMP_STANDALONE_MODE             0x00000000U                                  /*!< standalone mode */
00180 #define OPAMP_PGA_MODE                    OPAMP_CSR_VMSEL_1                            /*!< PGA mode */
00181 #define OPAMP_FOLLOWER_MODE               (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)      /*!< follower mode */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
00188   * @{
00189   */
00190
00191 #define OPAMP_NONINVERTINGINPUT_IO0         0x00000000U                /*!< OPAMP non-inverting input connected to dedicated IO pin */
00192 #define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL_0          /*!< OPAMP non-inverting input connected internally to DAC channel */
00193 #if defined(DAC2)
00194 #define OPAMP_NONINVERTINGINPUT_DAC2_CH     OPAMP_CSR_VPSEL_1         /*!< Only OPAMP2 non-inverting input connected internally to DAC2 channel */
00195 #endif /* DAC2 */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
00202   * @{
00203   */
00204
00205 #define OPAMP_INVERTINGINPUT_IO0               0x00000000U                            /*!< OPAMP inverting input connected to dedicated IO pin */
00206 #define OPAMP_INVERTINGINPUT_IO1               OPAMP_CSR_VMSEL_0                      /*!< OPAMP inverting input connected to dedicated IO pin */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
00213   * @{
00214   */
00215
00216 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO                0x00000000U                                /*!< In PGA mode, the inverting input is not connected */
00217 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0               OPAMP_CSR_PGGAIN_2                         /*!< In PGA mode, the inverting input is connected to VINM0 */
00218 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS          OPAMP_CSR_PGGAIN_3                         /*!< In PGA mode, the inverting input is connected to VINM0 or bias */
00219 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS      (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)  /*!< In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering */
00220
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup OPAMP_PgaGain OPAMP Pga Gain
00227   * @{
00228   */
00229
00230 #define OPAMP_PGA_GAIN_2_OR_MINUS_1               0x00000000U                                 /*!< PGA gain could be 2 or -1   */
00231 #define OPAMP_PGA_GAIN_4_OR_MINUS_3               OPAMP_CSR_PGGAIN_0                          /*!< PGA gain could be 4 or -3   */
00232 #define OPAMP_PGA_GAIN_8_OR_MINUS_7               OPAMP_CSR_PGGAIN_1                          /*!< PGA gain could be 8 or -7   */
00233 #define OPAMP_PGA_GAIN_16_OR_MINUS_15             (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)   /*!< PGA gain could be 16 or -15 */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup OPAMP_PowerMode OPAMP PowerMode
00240   * @{
00241   */
00242 #define OPAMP_POWERMODE_NORMAL         0x00000000U
00243 #define OPAMP_POWERMODE_HIGHSPEED      OPAMP_CSR_OPAHSM
00244
00245 /**
00246   * @}
00247   */
00248
00249
00250 /** @defgroup OPAMP_VREF OPAMP VREF
00251   * @{
00252   */
00253
00254 #define OPAMP_VREF_3VDDA                     0x00000000U                 /*!< OPAMP Vref = 3.3% VDDA */
00255 #define OPAMP_VREF_10VDDA                    OPAMP_CSR_CALSEL_0          /*!< OPAMP Vref = 10% VDDA  */
00256 #define OPAMP_VREF_50VDDA                    OPAMP_CSR_CALSEL_1          /*!< OPAMP Vref = 50% VDDA  */
00257 #define OPAMP_VREF_90VDDA                    OPAMP_CSR_CALSEL            /*!< OPAMP Vref = 90% VDDA  */
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
00264   * @{
00265   */
00266 #define OPAMP_TRIMMING_FACTORY         0x00000000U                             /*!< Factory trimming */
00267 #define OPAMP_TRIMMING_USER            OPAMP_CSR_USERTRIM                      /*!< User trimming */
00268
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
00275   * @{
00276   */
00277 #define OPAMP_FACTORYTRIMMING_DUMMY    0xFFFFFFFFU                          /*!< Dummy value if trimming value could not be retrieved */
00278
00279 #define OPAMP_FACTORYTRIMMING_N        0x00000000U                          /*!< Offset trimming N */
00280 #define OPAMP_FACTORYTRIMMING_P        0x00000001U                          /*!< Offset trimming P */
00281
00282 /**
00283   * @}
00284   */
00285
00286  /**
00287   * @}
00288   */
00289
00290 /* Private constants ---------------------------------------------------------*/
00291 /** @defgroup OPAMP_Private_Constants OPAMP Private Constants
00292   * @brief   OPAMP Private constants and defines
00293   * @{
00294   */
00295
00296 /* NONINVERTING bit position in OTR & HSOTR */
00297 #define OPAMP_INPUT_NONINVERTING           (8U)  /*!< Non inverting input */
00298
00299 /* Offset trimming time: during calibration, minimum time needed between two  */
00300 /* steps to have 1 mV accuracy.                                               */
00301 /* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=2ms.*/
00302 /* Unit: ms.                                                                  */
00303 #define OPAMP_TRIMMING_DELAY               (2U)
00304
00305 /**
00306   * @}
00307   */
00308
00309 /* Exported macros -----------------------------------------------------------*/
00310 /** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
00311   * @{
00312   */
00313
00314 /** @brief Reset OPAMP handle state.
00315   * @param  __HANDLE__: OPAMP handle.
00316   * @retval None
00317   */
00318 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
00319
00320 /**
00321   * @}
00322   */
00323
00324 /* Private macro -------------------------------------------------------------*/
00325
00326 /** @defgroup OPAMP_Private_Macros OPAMP Private Macros
00327   * @{
00328   */
00329
00330 #define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
00331                                                ((INPUT) == OPAMP_PGA_MODE) || \
00332                                                ((INPUT) == OPAMP_FOLLOWER_MODE))
00333
00334 #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00335                                                     ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
00336
00337 #if defined(DAC2)
00338 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00339                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH) || \
00340                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC2_CH))
00341 #else
00342 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00343                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
00344 #endif /* DAC2 */
00345
00346 #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
00347                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
00348                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
00349                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
00350
00351 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
00352                                  ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
00353                                  ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
00354                                  ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))
00355
00356
00357 #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA)  || \
00358                              ((VREF) == OPAMP_VREF_10VDDA) || \
00359                              ((VREF) == OPAMP_VREF_50VDDA) || \
00360                              ((VREF) == OPAMP_VREF_90VDDA))
00361
00362 #define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
00363                                       ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )
00364
00365
00366 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00367                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00368
00369
00370 #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00371
00372 #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
00373                                              ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
00374
00375 /**
00376   * @}
00377   */
00378
00379 /* Include OPAMP HAL Extended module */
00380 #include "stm32h7xx_hal_opamp_ex.h"
00381
00382 /* Exported functions --------------------------------------------------------*/
00383 /** @addtogroup OPAMP_Exported_Functions
00384   * @{
00385   */
00386
00387 /** @addtogroup OPAMP_Exported_Functions_Group1
00388   * @{
00389   */
00390 /* Initialization/de-initialization functions  **********************************/
00391 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
00392 HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
00393 void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
00394 void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
00395 /**
00396   * @}
00397   */
00398
00399 /** @addtogroup OPAMP_Exported_Functions_Group2
00400   * @{
00401   */
00402
00403 /* I/O operation functions  *****************************************************/
00404 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
00405 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
00406 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
00407
00408 /**
00409   * @}
00410   */
00411
00412 /** @addtogroup OPAMP_Exported_Functions_Group3
00413   * @{
00414   */
00415
00416 /* Peripheral Control functions  ************************************************/
00417 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00418 /* OPAMP callback registering/unregistering */
00419 HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback);
00420 HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);
00421 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00422 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
00423 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
00424
00425 /**
00426   * @}
00427   */
00428
00429 /** @addtogroup OPAMP_Exported_Functions_Group4
00430   * @{
00431   */
00432
00433 /* Peripheral State functions  **************************************************/
00434 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
00435
00436 /**
00437   * @}
00438   */
00439
00440 /**
00441   * @}
00442   */
00443
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 #ifdef __cplusplus
00453 }
00454 #endif
00455
00456 #endif /* STM32H7xx_HAL_OPAMP_H */
00457
00458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp_ex.c Source File

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stm32h7xx_hal_opamp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended OPAMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
00008   *          peripheral:
00009   *           + Extended Initialization and de-initialization functions
00010   *           + Extended Peripheral Control functions
00011   *
00012   @verbatim
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00017   * All rights reserved.</center></h2>
00018   *
00019   * This software component is licensed by ST under BSD 3-Clause license,
00020   * the "License"; You may not use this file except in compliance with the
00021   * License. You may obtain a copy of the License at:
00022   *                        opensource.org/licenses/BSD-3-Clause
00023   *
00024   ******************************************************************************
00025   */
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32h7xx_hal.h"
00029
00030 /** @addtogroup STM32H7xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup OPAMPEx OPAMPEx
00035   * @brief OPAMP Extended HAL module driver
00036   * @{
00037   */
00038
00039 #ifdef HAL_OPAMP_MODULE_ENABLED
00040
00041 /* Private typedef -----------------------------------------------------------*/
00042 /* Private define ------------------------------------------------------------*/
00043 /* Private macro -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Exported functions --------------------------------------------------------*/
00047
00048 /** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00049   * @{
00050   */
00051
00052 /** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00053   * @brief    Extended operation functions
00054   *
00055 @verbatim
00056  ===============================================================================
00057               ##### Extended IO operation functions #####
00058  ===============================================================================
00059   [..]
00060       (+) OPAMP Self calibration.
00061
00062 @endverbatim
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  Run the self calibration of 2 OPAMPs in parallel.
00068   * @note   Trimming values (PMOS & NMOS) are updated and user trimming is
00069   *         enabled is calibration is successful.
00070   * @note   Calibration is performed in the mode specified in OPAMP init
00071   *         structure (mode normal or low power). To perform calibration for
00072   *         both modes, repeat this function twice after OPAMP init structure
00073   *         accordingly updated.
00074   * @param  hopamp1 handle
00075   * @param  hopamp2 handle
00076   * @retval HAL status
00077   */
00078
00079 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
00080 {
00081   HAL_StatusTypeDef status = HAL_OK;
00082
00083   uint32_t trimmingvaluen1;
00084   uint32_t trimmingvaluep1;
00085   uint32_t trimmingvaluen2;
00086   uint32_t trimmingvaluep2;
00087
00088 /* Selection of register of trimming depending on power mode: OTR or HSOTR */
00089   __IO uint32_t* tmp_opamp1_reg_trimming;
00090   __IO uint32_t* tmp_opamp2_reg_trimming;
00091
00092   uint32_t delta;
00093   uint32_t opampmode1;
00094   uint32_t opampmode2;
00095
00096   if((hopamp1 == NULL) || (hopamp2 == NULL))
00097   {
00098     status = HAL_ERROR;
00099   }
00100   /* Check if OPAMP in calibration mode and calibration not yet enable */
00101   else if(hopamp1->State !=  HAL_OPAMP_STATE_READY)
00102   {
00103     status = HAL_ERROR;
00104   }
00105   else if(hopamp2->State != HAL_OPAMP_STATE_READY)
00106   {
00107     status = HAL_ERROR;
00108   }
00109   else
00110   {
00111       /* Check the parameter */
00112       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00113       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00114
00115       assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
00116       assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
00117
00118       /* Set Calibration mode */
00119       /* Non-inverting input connected to calibration reference voltage. */
00120       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00121       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00122
00123       /* Save OPAMP mode  */
00124       opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_VMSEL);
00125       opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_VMSEL);
00126
00127       /* Use of standalone mode */
00128       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00129       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00130
00131       /*  user trimming values are used for offset calibration */
00132       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00133       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00134
00135       /* Select trimming settings depending on power mode */
00136       if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00137       {
00138         tmp_opamp1_reg_trimming = &OPAMP1->OTR;
00139       }
00140       else
00141       {
00142         tmp_opamp1_reg_trimming = &OPAMP1->HSOTR;
00143       }
00144
00145       if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00146       {
00147         tmp_opamp2_reg_trimming = &OPAMP2->OTR;
00148       }
00149       else
00150       {
00151         tmp_opamp2_reg_trimming = &OPAMP2->HSOTR;
00152       }
00153
00154       /* Enable calibration */
00155       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00156       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00157
00158       /* 1st calibration - N */
00159       /* Select 90U% VREF */
00160       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00161       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00162
00163       /* Enable the selected opamp */
00164       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00165       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00166
00167       /* Init trimming counter */
00168       /* Medium value */
00169       trimmingvaluen1 = 16U;
00170       trimmingvaluen2 = 16U;
00171       delta = 8U;
00172
00173       while (delta != 0U)
00174       {
00175         /* Set candidate trimming */
00176         /* OPAMP_POWERMODE_NORMAL */
00177         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00178         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00179
00180         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00181         /* Offset trim time: during calibration, minimum time needed between */
00182         /* two steps to have 1 mV accuracy */
00183         HAL_Delay(OPAMP_TRIMMING_DELAY);
00184
00185         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00186         {
00187           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00188           trimmingvaluen1 += delta;
00189         }
00190         else
00191         {
00192           /* OPAMP_CSR_CALOUT is High try lower trimming */
00193           trimmingvaluen1 -= delta;
00194         }
00195
00196         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00197         {
00198           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00199           trimmingvaluen2 += delta;
00200         }
00201         else
00202         {
00203           /* OPAMP_CSR_CALOUT is High try lower trimming */
00204           trimmingvaluen2 -= delta;
00205         }
00206         /* Divide range by 2 to continue dichotomy sweep */
00207         delta >>= 1U;
00208       }
00209
00210       /* Still need to check if right calibration is current value or one step below */
00211       /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
00212       /* Set candidate trimming */
00213       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00214       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00215
00216       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00217       /* Offset trim time: during calibration, minimum time needed between */
00218       /* two steps to have 1 mV accuracy */
00219       HAL_Delay(OPAMP_TRIMMING_DELAY);
00220
00221       if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
00222       {
00223         /* Trimming value is actually one value more */
00224         trimmingvaluen1++;
00225         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00226       }
00227
00228       if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
00229       {
00230         /* Trimming value is actually one value more */
00231         trimmingvaluen2++;
00232         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00233       }
00234
00235       /* 2nd calibration - P */
00236       /* Select 10U% VREF */
00237       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00238       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00239
00240       /* Init trimming counter */
00241       /* Medium value */
00242       trimmingvaluep1 = 16U;
00243       trimmingvaluep2 = 16U;
00244       delta = 8U;
00245
00246       while (delta != 0U)
00247       {
00248         /* Set candidate trimming */
00249         /* OPAMP_POWERMODE_NORMAL */
00250         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00251         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00252
00253         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00254         /* Offset trim time: during calibration, minimum time needed between */
00255         /* two steps to have 1 mV accuracy */
00256         HAL_Delay(OPAMP_TRIMMING_DELAY);
00257
00258         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00259         {
00260           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00261           trimmingvaluep1 += delta;
00262         }
00263         else
00264         {
00265           /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
00266           trimmingvaluep1 -= delta;
00267         }
00268
00269         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00270         {
00271           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00272           trimmingvaluep2 += delta;
00273         }
00274         else
00275         {
00276           /* OPAMP_CSR_CALOUT is High try lower trimming */
00277           trimmingvaluep2 -= delta;
00278         }
00279         /* Divide range by 2 to continue dichotomy sweep */
00280         delta >>= 1U;
00281       }
00282
00283       /* Still need to check if right calibration is current value or one step below */
00284       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00285       /* Set candidate trimming */
00286       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00287       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00288
00289       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00290       /* Offset trim time: during calibration, minimum time needed between */
00291       /* two steps to have 1 mV accuracy */
00292       HAL_Delay(OPAMP_TRIMMING_DELAY);
00293
00294       if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00295       {
00296         /* Trimming value is actually one value more */
00297         trimmingvaluep1++;
00298         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00299       }
00300
00301       if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
00302       {
00303         /* Trimming value is actually one value more */
00304         trimmingvaluep2++;
00305         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00306       }
00307
00308       /* Disable calibration & set normal mode (operating mode) */
00309       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00310       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00311
00312      /* Disable the OPAMPs */
00313       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00314       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00315
00316       /* Self calibration is successful */
00317       /* Store calibration (user trimming) results in init structure. */
00318
00319       /* Set user trimming mode */
00320       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00321       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00322
00323       /* Affect calibration parameters depending on mode normal/high speed */
00324       if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00325       {
00326         /* Write calibration result N */
00327         hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00328         /* Write calibration result P */
00329         hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00330       }
00331       else
00332       {
00333         /* Write calibration result N */
00334         hopamp1->Init.TrimmingValueNHighSpeed = trimmingvaluen1;
00335         /* Write calibration result P */
00336         hopamp1->Init.TrimmingValuePHighSpeed = trimmingvaluep1;
00337       }
00338
00339       if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00340       {
00341         /* Write calibration result N */
00342         hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00343         /* Write calibration result P */
00344         hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00345       }
00346       else
00347       {
00348         /* Write calibration result N */
00349         hopamp2->Init.TrimmingValueNHighSpeed = trimmingvaluen2;
00350         /* Write calibration result P */
00351         hopamp2->Init.TrimmingValuePHighSpeed = trimmingvaluep2;
00352
00353        }
00354       /* Update OPAMP state */
00355       hopamp1->State = HAL_OPAMP_STATE_READY;
00356       hopamp2->State = HAL_OPAMP_STATE_READY;
00357
00358       /* Restore OPAMP mode after calibration */
00359       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, opampmode1);
00360       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, opampmode2);
00361   }
00362
00363   return status;
00364 }
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
00371  *  @brief   Peripheral Control functions
00372  *
00373 @verbatim
00374  ===============================================================================
00375              ##### Peripheral Control functions #####
00376  ===============================================================================
00377     [..]
00378       (+) OPAMP unlock.
00379
00380 @endverbatim
00381   * @{
00382   */
00383
00384 /**
00385   * @brief  Unlock the selected OPAMP configuration.
00386   * @note   This function must be called only when OPAMP is in state "locked".
00387   * @param  hopamp: OPAMP handle
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
00391 {
00392   HAL_StatusTypeDef status = HAL_OK;
00393
00394   /* Check the OPAMP handle allocation */
00395   /* Check if OPAMP locked */
00396   if(hopamp == NULL)
00397   {
00398     status = HAL_ERROR;
00399   }
00400   /* Check the OPAMP handle allocation */
00401   /* Check if OPAMP locked */
00402   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00403   {
00404     /* Check the parameter */
00405     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00406
00407    /* OPAMP state changed to locked */
00408     hopamp->State = HAL_OPAMP_STATE_BUSY;
00409   }
00410   else
00411   {
00412     status = HAL_ERROR;
00413   }
00414
00415   return status;
00416 }
00417
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /**
00427   * @}
00428   */
00429
00430 /**
00431   * @}
00432   */
00433
00434 #endif /* HAL_OPAMP_MODULE_ENABLED */
00435 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_opamp_ex.h Source File

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stm32h7xx_hal_opamp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_OPAMP_EX_H
00022 #define STM32H7xx_HAL_OPAMP_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup OPAMPEx
00036   * @{
00037   */
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /* Exported macro ------------------------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
00043   * @{
00044   */
00045
00046 /* Extended IO operation functions  *****************************************************/
00047 /** @addtogroup OPAMPEx_Exported_Functions_Group1
00048   * @{
00049   */
00050 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
00051
00052 /**
00053   * @}
00054   */
00055 /* Peripheral Control functions  ************************************************/
00056 /** @addtogroup OPAMPEx_Exported_Functions_Group2
00057   * @{
00058   */
00059 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /**
00069   * @}
00070   */
00071
00072 /**
00073   * @}
00074   */
00075
00076 #ifdef __cplusplus
00077 }
00078 #endif
00079
00080
00081 #endif /* STM32H7xx_HAL_OPAMP_EX_H */
00082
00083 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:00 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ospi.c Source File

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stm32h7xx_hal_ospi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ospi.c
00004   * @author  MCD Application Team
00005   * @brief   OSPI HAL module driver.
00006              This file provides firmware functions to manage the following
00007              functionalities of the OctoSPI interface (OSPI).
00008               + Initialization and de-initialization functions
00009               + Hyperbus configuration
00010               + Indirect functional mode management
00011               + Memory-mapped functional mode management
00012               + Auto-polling functional mode management
00013               + Interrupts and flags management
00014               + DMA channel configuration for indirect functional mode
00015               + Errors management and abort functionality
00016               + IO manager configuration
00017
00018   @verbatim
00019  ===============================================================================
00020                         ##### How to use this driver #####
00021  ===============================================================================
00022   [..]
00023     *** Initialization ***
00024     ======================
00025     [..]
00026       (#) As prerequisite, fill in the HAL_OSPI_MspInit() :
00027         (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
00028         (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
00029         (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00030         (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
00031         (++) If interrupt or DMA mode is used, enable and configure OctoSPI global
00032             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00033         (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
00034             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00035             link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
00036             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00037       (#) Configure the fifo threshold, the dual-quad mode, the memory type, the
00038           device size, the CS high time, the free running clock, the clock mode,
00039           the wrap size, the clock prescaler, the sample shifting, the hold delay
00040           and the CS boundary using the HAL_OSPI_Init() function.
00041       (#) When using Hyperbus, configure the RW recovery time, the access time,
00042           the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
00043           function.
00044
00045     *** Indirect functional mode ***
00046     ================================
00047     [..]
00048       (#) In regular mode, configure the command sequence using the HAL_OSPI_Command()
00049           or HAL_OSPI_Command_IT() functions :
00050          (++) Instruction phase : the mode used and if present the size, the instruction
00051               opcode and the DTR mode.
00052          (++) Address phase : the mode used and if present the size, the address
00053               value and the DTR mode.
00054          (++) Alternate-bytes phase : the mode used and if present the size, the
00055               alternate bytes values and the DTR mode.
00056          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00057          (++) Data phase : the mode used and if present the number of bytes and the DTR mode.
00058          (++) Data strobe (DQS) mode : the activation (or not) of this mode
00059          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00060          (++) Flash identifier : in dual-quad mode, indicates which flash is concerned
00061          (++) Operation type : always common configuration
00062       (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
00063           function :
00064          (++) Address space : indicate if the access will be done in register or memory
00065          (++) Address size
00066          (++) Number of data
00067          (++) Data strobe (DQS) mode : the activation (or not) of this mode
00068       (#) If no data is required for the command (only for regular mode, not for
00069           Hyperbus mode), it is sent directly to the memory :
00070          (++) In polling mode, the output of the function is done when the transfer is complete.
00071          (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
00072       (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
00073           HAL_OSPI_Transmit_IT() after the command configuration :
00074          (++) In polling mode, the output of the function is done when the transfer is complete.
00075          (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
00076              is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
00077          (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
00078              HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
00079       (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
00080           HAL_OSPI_Receive_IT() after the command configuration :
00081          (++) In polling mode, the output of the function is done when the transfer is complete.
00082          (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
00083              is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
00084          (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
00085              HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
00086
00087     *** Auto-polling functional mode ***
00088     ====================================
00089     [..]
00090       (#) Configure the command sequence by the same way than the indirect mode
00091       (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
00092           or HAL_OSPI_AutoPolling_IT() functions :
00093          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00094              the polling interval and the automatic stop activation.
00095       (#) After the configuration :
00096          (++) In polling mode, the output of the function is done when the status match is reached. The
00097              automatic stop is activated to avoid an infinite loop.
00098          (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
00099     *** MDMA functional mode ***
00100     ====================================
00101     [..]
00102       (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_OSPI_MspInit() function :
00103          (++) MDMA settings for write operation :
00104           (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
00105           (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
00106           (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
00107               aligned with @ref MDMA_Source_increment_mode .
00108           (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
00109          (++) MDMA settings for read operation :
00110           (+) The SourceInc should be MDMA_SRC_INC_DISABLE
00111           (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
00112           (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
00113           (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
00114               aligned with @ref MDMA_Destination_increment_mode.
00115          (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
00116       (#)In case of wrong MDMA setting
00117         (++) For write operation :
00118          (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
00119         (++) For read operation :
00120          (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
00121
00122     *** Memory-mapped functional mode ***
00123     =====================================
00124     [..]
00125       (#) Configure the command sequence by the same way than the indirect mode except
00126           for the operation type in regular mode :
00127          (++) Operation type equals to read configuration : the command configuration
00128               applies to read access in memory-mapped mode
00129          (++) Operation type equals to write configuration : the command configuration
00130               applies to write access in memory-mapped mode
00131          (++) Both read and write configuration should be performed before activating
00132               memory-mapped mode
00133       (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
00134           functions :
00135          (++) The timeout activation and the timeout period.
00136       (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
00137           the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
00138
00139     *** Errors management and abort functionality ***
00140     =================================================
00141     [..]
00142       (#) HAL_OSPI_GetError() function gives the error raised during the last operation.
00143       (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
00144           flushes the fifo :
00145          (++) In polling mode, the output of the function is done when the transfer
00146               complete bit is set and the busy bit cleared.
00147          (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
00148               the transfer complete bit is set.
00149
00150     *** Control functions ***
00151     =========================
00152     [..]
00153       (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
00154       (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
00155       (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
00156       (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00157
00158     *** IO manager configuration functions ***
00159     ==========================================
00160     [..]
00161       (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
00162
00163     *** Callback registration ***
00164     =============================================
00165     [..]
00166       The compilation define  USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
00167       allows the user to configure dynamically the driver callbacks.
00168
00169       Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback,
00170       it allows to register following callbacks:
00171         (+) ErrorCallback : callback when error occurs.
00172         (+) AbortCpltCallback : callback when abort is completed.
00173         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00174         (+) CmdCpltCallback : callback when a command without data is completed.
00175         (+) RxCpltCallback : callback when a reception transfer is completed.
00176         (+) TxCpltCallback : callback when a transmission transfer is completed.
00177         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00178         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00179         (+) StatusMatchCallback : callback when a status match occurs.
00180         (+) TimeOutCallback : callback when the timeout perioed expires.
00181         (+) MspInitCallback    : OSPI MspInit.
00182         (+) MspDeInitCallback  : OSPI MspDeInit.
00183       This function takes as parameters the HAL peripheral handle, the Callback ID
00184       and a pointer to the user callback function.
00185
00186       Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default
00187       weak (surcharged) function. It allows to reset following callbacks:
00188         (+) ErrorCallback : callback when error occurs.
00189         (+) AbortCpltCallback : callback when abort is completed.
00190         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00191         (+) CmdCpltCallback : callback when a command without data is completed.
00192         (+) RxCpltCallback : callback when a reception transfer is completed.
00193         (+) TxCpltCallback : callback when a transmission transfer is completed.
00194         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00195         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00196         (+) StatusMatchCallback : callback when a status match occurs.
00197         (+) TimeOutCallback : callback when the timeout perioed expires.
00198         (+) MspInitCallback    : OSPI MspInit.
00199         (+) MspDeInitCallback  : OSPI MspDeInit.
00200       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00201
00202       By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET
00203       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00204       Exception done for MspInit and MspDeInit callbacks that are respectively
00205       reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init
00206       and @ref  HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand).
00207       If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit
00208       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00209
00210       Callbacks can be registered/unregistered in READY state only.
00211       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00212       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00213       during the Init/DeInit.
00214       In that case first register the MspInit/MspDeInit user callbacks
00215       using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit
00216       or @ref HAL_OSPI_Init function.
00217
00218       When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
00219       not defined, the callback registering feature is not available
00220       and weak (surcharged) callbacks are used.
00221
00222   @endverbatim
00223   ******************************************************************************
00224   * @attention
00225   *
00226   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
00227   * All rights reserved.</center></h2>
00228   *
00229   * This software component is licensed by ST under BSD 3-Clause license,
00230   * the "License"; You may not use this file except in compliance with the
00231   * License. You may obtain a copy of the License at:
00232   *                       opensource.org/licenses/BSD-3-Clause
00233   *
00234   ******************************************************************************
00235   */
00236
00237 /* Includes ------------------------------------------------------------------*/
00238 #include "stm32h7xx_hal.h"
00239
00240 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
00241
00242 /** @addtogroup STM32H7xx_HAL_Driver
00243   * @{
00244   */
00245
00246 /** @defgroup OSPI OSPI
00247   * @brief OSPI HAL module driver
00248   * @{
00249   */
00250
00251 #ifdef HAL_OSPI_MODULE_ENABLED
00252
00253 /**
00254   @cond 0
00255   */
00256 /* Private typedef -----------------------------------------------------------*/
00257
00258 /* Private define ------------------------------------------------------------*/
00259 #define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)         /*!< Indirect write mode    */
00260 #define OSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode     */
00261 #define OSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */
00262 #define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)OCTOSPI_CR_FMODE)   /*!< Memory-mapped mode     */
00263
00264 #define OSPI_CFG_STATE_MASK  0x00000004U
00265 #define OSPI_BUSY_STATE_MASK 0x00000008U
00266
00267 #define OSPI_NB_INSTANCE   2U
00268 #define OSPI_IOM_NB_PORTS  2U
00269 #define OSPI_IOM_PORT_MASK 0x1U
00270
00271 /* Private macro -------------------------------------------------------------*/
00272 #define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00273                                        ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00274                                        ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00275                                        ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00276
00277 /* Private variables ---------------------------------------------------------*/
00278
00279 /* Private function prototypes -----------------------------------------------*/
00280 static void              OSPI_DMACplt                  (MDMA_HandleTypeDef *hmdma);
00281 static void              OSPI_DMAError                 (MDMA_HandleTypeDef *hmdma);
00282 static void              OSPI_DMAAbortCplt             (MDMA_HandleTypeDef *hmdma);
00283 static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
00284 static HAL_StatusTypeDef OSPI_ConfigCmd                (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
00285 static HAL_StatusTypeDef OSPIM_GetConfig               (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
00286 /**
00287   @endcond
00288   */
00289
00290 /* Exported functions --------------------------------------------------------*/
00291
00292 /** @defgroup OSPI_Exported_Functions OSPI Exported Functions
00293   * @{
00294   */
00295
00296 /** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00297   * @brief    Initialization and Configuration functions
00298   *
00299 @verbatim
00300 ===============================================================================
00301             ##### Initialization and Configuration functions #####
00302  ===============================================================================
00303     [..]
00304     This subsection provides a set of functions allowing to :
00305       (+) Initialize the OctoSPI.
00306       (+) De-initialize the OctoSPI.
00307
00308 @endverbatim
00309   * @{
00310   */
00311
00312 /**
00313   * @brief  Initialize the OSPI mode according to the specified parameters
00314   *         in the OSPI_InitTypeDef and initialize the associated handle.
00315   * @param  hospi : OSPI handle
00316   * @retval HAL status
00317   */
00318 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
00319 {
00320   HAL_StatusTypeDef status = HAL_OK;
00321   uint32_t tickstart = HAL_GetTick();
00322
00323   /* Check the OSPI handle allocation */
00324   if (hospi == NULL)
00325   {
00326     status = HAL_ERROR;
00327     /* No error code can be set set as the handler is null */
00328   }
00329   else
00330   {
00331     /* Check the parameters of the initialization structure */
00332     assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold));
00333     assert_param(IS_OSPI_DUALQUAD_MODE  (hospi->Init.DualQuad));
00334     assert_param(IS_OSPI_MEMORY_TYPE    (hospi->Init.MemoryType));
00335     assert_param(IS_OSPI_DEVICE_SIZE    (hospi->Init.DeviceSize));
00336     assert_param(IS_OSPI_CS_HIGH_TIME   (hospi->Init.ChipSelectHighTime));
00337     assert_param(IS_OSPI_FREE_RUN_CLK   (hospi->Init.FreeRunningClock));
00338     assert_param(IS_OSPI_CLOCK_MODE     (hospi->Init.ClockMode));
00339     assert_param(IS_OSPI_WRAP_SIZE      (hospi->Init.WrapSize));
00340     assert_param(IS_OSPI_CLK_PRESCALER  (hospi->Init.ClockPrescaler));
00341     assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
00342     assert_param(IS_OSPI_DHQC           (hospi->Init.DelayHoldQuarterCycle));
00343     assert_param(IS_OSPI_CS_BOUNDARY    (hospi->Init.ChipSelectBoundary));
00344     assert_param(IS_OSPI_CKCSHT         (hospi->Init.ClkChipSelectHighTime));
00345     assert_param(IS_OSPI_DLYBYP         (hospi->Init.DelayBlockBypass));
00346     assert_param(IS_OSPI_MAXTRAN        (hospi->Init.MaxTran));
00347
00348     /* Initialize error code */
00349     hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
00350
00351     /* Check if the state is the reset state */
00352     if (hospi->State == HAL_OSPI_STATE_RESET)
00353     {
00354 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00355       /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */
00356       hospi->ErrorCallback         = HAL_OSPI_ErrorCallback;
00357       hospi->AbortCpltCallback     = HAL_OSPI_AbortCpltCallback;
00358       hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
00359       hospi->CmdCpltCallback       = HAL_OSPI_CmdCpltCallback;
00360       hospi->RxCpltCallback        = HAL_OSPI_RxCpltCallback;
00361       hospi->TxCpltCallback        = HAL_OSPI_TxCpltCallback;
00362       hospi->RxHalfCpltCallback    = HAL_OSPI_RxHalfCpltCallback;
00363       hospi->TxHalfCpltCallback    = HAL_OSPI_TxHalfCpltCallback;
00364       hospi->StatusMatchCallback   = HAL_OSPI_StatusMatchCallback;
00365       hospi->TimeOutCallback       = HAL_OSPI_TimeOutCallback;
00366
00367       if(hospi->MspInitCallback == NULL)
00368       {
00369         hospi->MspInitCallback = HAL_OSPI_MspInit;
00370       }
00371
00372       /* Init the low level hardware */
00373       hospi->MspInitCallback(hospi);
00374 #else
00375       /* Initialization of the low level hardware */
00376       HAL_OSPI_MspInit(hospi);
00377 #endif
00378
00379       /* Configure the default timeout for the OSPI memory access */
00380       status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
00381     }
00382
00383     if (status == HAL_OK)
00384     {
00385       /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
00386       MODIFY_REG(hospi->Instance->DCR1,
00387                  (OCTOSPI_DCR1_MTYP   | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
00388                   OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK    | OCTOSPI_DCR1_CKMODE),
00389                  (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
00390                   ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
00391                   (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) |
00392                   hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
00393
00394       /* Configure wrap size */
00395       MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
00396
00397       /* Configure chip select boundary and maximun transfer */
00398       hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
00399
00400       /* Configure refresh */
00401       hospi->Instance->DCR4 = hospi->Init.Refresh;
00402
00403       /* Configure FIFO threshold */
00404       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
00405
00406       /* Wait till busy flag is reset */
00407       status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
00408
00409       if (status == HAL_OK)
00410       {
00411          /* Configure clock prescaler */
00412          MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
00413
00414          /* Configure Dual Quad mode */
00415          MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
00416
00417          /* Configure sample shifting and delay hold quarter cycle */
00418          MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
00419
00420          /* Enable OctoSPI */
00421          __HAL_OSPI_ENABLE(hospi);
00422
00423          /* Enable free running clock if needed : must be done after OSPI enable */
00424          if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
00425          {
00426            SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
00427          }
00428
00429          /* Initialize the OSPI state */
00430          if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
00431          {
00432             hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
00433          }
00434          else
00435          {
00436             hospi->State = HAL_OSPI_STATE_READY;
00437          }
00438       }
00439     }
00440   }
00441
00442   /* Return function status */
00443   return status;
00444 }
00445
00446 /**
00447   * @brief  Initialize the OSPI MSP.
00448   * @param  hospi : OSPI handle
00449   * @retval None
00450   */
00451 __weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hospi);
00455
00456   /* NOTE : This function should not be modified, when the callback is needed,
00457             the HAL_OSPI_MspInit can be implemented in the user file
00458    */
00459 }
00460
00461 /**
00462   * @brief  De-Initialize the OSPI peripheral.
00463   * @param  hospi : OSPI handle
00464   * @retval HAL status
00465   */
00466 HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
00467 {
00468   HAL_StatusTypeDef status = HAL_OK;
00469
00470   /* Check the OSPI handle allocation */
00471   if (hospi == NULL)
00472   {
00473     status = HAL_ERROR;
00474     /* No error code can be set set as the handler is null */
00475   }
00476   else
00477   {
00478      /* Disable OctoSPI */
00479      __HAL_OSPI_DISABLE(hospi);
00480
00481      /* Disable free running clock if needed : must be done after OSPI disable */
00482      CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
00483
00484 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00485      if(hospi->MspDeInitCallback == NULL)
00486      {
00487        hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
00488      }
00489
00490      /* DeInit the low level hardware */
00491      hospi->MspDeInitCallback(hospi);
00492 #else
00493      /* De-initialize the low-level hardware */
00494      HAL_OSPI_MspDeInit(hospi);
00495 #endif
00496
00497      /* Reset the driver state */
00498      hospi->State = HAL_OSPI_STATE_RESET;
00499   }
00500
00501   return status;
00502 }
00503
00504 /**
00505   * @brief  DeInitialize the OSPI MSP.
00506   * @param  hospi : OSPI handle
00507   * @retval None
00508   */
00509 __weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi)
00510 {
00511   /* Prevent unused argument(s) compilation warning */
00512   UNUSED(hospi);
00513
00514   /* NOTE : This function should not be modified, when the callback is needed,
00515             the HAL_OSPI_MspDeInit can be implemented in the user file
00516    */
00517 }
00518
00519 /**
00520   * @}
00521   */
00522
00523 /** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions
00524   *  @brief OSPI Transmit/Receive functions
00525   *
00526 @verbatim
00527  ===============================================================================
00528                       ##### IO operation functions #####
00529  ===============================================================================
00530     [..]
00531     This subsection provides a set of functions allowing to :
00532       (+) Handle the interrupts.
00533       (+) Handle the command sequence (regular and Hyperbus).
00534       (+) Handle the Hyperbus configuration.
00535       (+) Transmit data in blocking, interrupt or DMA mode.
00536       (+) Receive data in blocking, interrupt or DMA mode.
00537       (+) Manage the auto-polling functional mode.
00538       (+) Manage the memory-mapped functional mode.
00539
00540 @endverbatim
00541   * @{
00542   */
00543
00544 /**
00545   * @brief  Handle OSPI interrupt request.
00546   * @param  hospi : OSPI handle
00547   * @retval None
00548   */
00549 void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
00550 {
00551   __IO uint32_t *data_reg = &hospi->Instance->DR;
00552   uint32_t flag           = hospi->Instance->SR;
00553   uint32_t itsource       = hospi->Instance->CR;
00554   uint32_t currentstate   = hospi->State;
00555
00556   /* OctoSPI fifo threshold interrupt occurred -------------------------------*/
00557   if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U))
00558   {
00559     if (currentstate == HAL_OSPI_STATE_BUSY_TX)
00560     {
00561       /* Write a data in the fifo */
00562       *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
00563       hospi->pBuffPtr++;
00564       hospi->XferCount--;
00565     }
00566     else if (currentstate == HAL_OSPI_STATE_BUSY_RX)
00567     {
00568       /* Read a data from the fifo */
00569       *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
00570       hospi->pBuffPtr++;
00571       hospi->XferCount--;
00572     }
00573     else
00574     {
00575       /* Nothing to do */
00576     }
00577
00578     if (hospi->XferCount == 0U)
00579     {
00580       /* All data have been received or transmitted for the transfer */
00581       /* Disable fifo threshold interrupt */
00582       __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT);
00583     }
00584
00585     /* Fifo threshold callback */
00586 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00587     hospi->FifoThresholdCallback(hospi);
00588 #else
00589     HAL_OSPI_FifoThresholdCallback(hospi);
00590 #endif
00591   }
00592   /* OctoSPI transfer complete interrupt occurred ----------------------------*/
00593   else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
00594   {
00595     if (currentstate == HAL_OSPI_STATE_BUSY_RX)
00596     {
00597       if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U))
00598       {
00599         /* Read the last data received in the fifo */
00600         *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
00601         hospi->pBuffPtr++;
00602         hospi->XferCount--;
00603       }
00604       else if(hospi->XferCount == 0U)
00605       {
00606         /* Clear flag */
00607         hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
00608
00609         /* Disable the interrupts */
00610         __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
00611
00612         /* Update state */
00613         hospi->State = HAL_OSPI_STATE_READY;
00614
00615         /* RX complete callback */
00616 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00617         hospi->RxCpltCallback(hospi);
00618 #else
00619         HAL_OSPI_RxCpltCallback(hospi);
00620 #endif
00621       }
00622       else
00623       {
00624         /* Nothing to do */
00625       }
00626     }
00627     else
00628     {
00629       /* Clear flag */
00630       hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
00631
00632       /* Disable the interrupts */
00633       __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
00634
00635       /* Update state */
00636       hospi->State = HAL_OSPI_STATE_READY;
00637
00638       if (currentstate == HAL_OSPI_STATE_BUSY_TX)
00639       {
00640         /* TX complete callback */
00641 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00642         hospi->TxCpltCallback(hospi);
00643 #else
00644         HAL_OSPI_TxCpltCallback(hospi);
00645 #endif
00646       }
00647       else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
00648       {
00649         /* Command complete callback */
00650 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00651         hospi->CmdCpltCallback(hospi);
00652 #else
00653         HAL_OSPI_CmdCpltCallback(hospi);
00654 #endif
00655       }
00656       else if (currentstate == HAL_OSPI_STATE_ABORT)
00657       {
00658         if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE)
00659         {
00660           /* Abort called by the user */
00661           /* Abort complete callback */
00662 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00663           hospi->AbortCpltCallback(hospi);
00664 #else
00665           HAL_OSPI_AbortCpltCallback(hospi);
00666 #endif
00667         }
00668         else
00669         {
00670           /* Abort due to an error (eg : DMA error) */
00671           /* Error callback */
00672 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00673           hospi->ErrorCallback(hospi);
00674 #else
00675           HAL_OSPI_ErrorCallback(hospi);
00676 #endif
00677         }
00678       }
00679       else
00680       {
00681         /* Nothing to do */
00682       }
00683     }
00684   }
00685   /* OctoSPI status match interrupt occurred ---------------------------------*/
00686   else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U))
00687   {
00688     /* Clear flag */
00689     hospi->Instance->FCR = HAL_OSPI_FLAG_SM;
00690
00691     /* Check if automatic poll mode stop is activated */
00692     if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U)
00693     {
00694       /* Disable the interrupts */
00695       __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
00696
00697       /* Update state */
00698       hospi->State = HAL_OSPI_STATE_READY;
00699     }
00700
00701     /* Status match callback */
00702 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00703     hospi->StatusMatchCallback(hospi);
00704 #else
00705     HAL_OSPI_StatusMatchCallback(hospi);
00706 #endif
00707   }
00708   /* OctoSPI transfer error interrupt occurred -------------------------------*/
00709   else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
00710   {
00711     /* Clear flag */
00712     hospi->Instance->FCR = HAL_OSPI_FLAG_TE;
00713
00714     /* Disable all interrupts */
00715     __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
00716
00717     /* Set error code */
00718     hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER;
00719
00720     /* Check if the DMA is enabled */
00721     if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
00722     {
00723       /* Disable the DMA transfer on the OctoSPI side */
00724       CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
00725
00726       /* Disable the DMA transfer on the DMA side */
00727       hospi->hmdma->XferAbortCallback = OSPI_DMAAbortCplt;
00728       if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
00729       {
00730         /* Update state */
00731         hospi->State = HAL_OSPI_STATE_READY;
00732
00733         /* Error callback */
00734 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00735         hospi->ErrorCallback(hospi);
00736 #else
00737         HAL_OSPI_ErrorCallback(hospi);
00738 #endif
00739       }
00740     }
00741     else
00742     {
00743       /* Update state */
00744       hospi->State = HAL_OSPI_STATE_READY;
00745
00746       /* Error callback */
00747 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00748       hospi->ErrorCallback(hospi);
00749 #else
00750       HAL_OSPI_ErrorCallback(hospi);
00751 #endif
00752     }
00753   }
00754   /* OctoSPI timeout interrupt occurred --------------------------------------*/
00755   else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U))
00756   {
00757     /* Clear flag */
00758     hospi->Instance->FCR = HAL_OSPI_FLAG_TO;
00759
00760     /* Timeout callback */
00761 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00762     hospi->TimeOutCallback(hospi);
00763 #else
00764     HAL_OSPI_TimeOutCallback(hospi);
00765 #endif
00766   }
00767   else
00768   {
00769     /* Nothing to do */
00770   }
00771 }
00772
00773 /**
00774   * @brief  Set the command configuration.
00775   * @param  hospi   : OSPI handle
00776   * @param  cmd     : structure that contains the command configuration information
00777   * @param  Timeout : Timeout duration
00778   * @retval HAL status
00779   */
00780 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
00781 {
00782   HAL_StatusTypeDef status;
00783   uint32_t state;
00784   uint32_t tickstart = HAL_GetTick();
00785
00786   /* Check the parameters of the command structure */
00787   assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
00788
00789   if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
00790   {
00791     assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
00792   }
00793
00794   assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00795   if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
00796   {
00797     assert_param(IS_OSPI_INSTRUCTION_SIZE    (cmd->InstructionSize));
00798     assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
00799   }
00800
00801   assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
00802   if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
00803   {
00804     assert_param(IS_OSPI_ADDRESS_SIZE    (cmd->AddressSize));
00805     assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
00806   }
00807
00808   assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
00809   if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
00810   {
00811     assert_param(IS_OSPI_ALT_BYTES_SIZE    (cmd->AlternateBytesSize));
00812     assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
00813   }
00814
00815   assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
00816   if (cmd->DataMode != HAL_OSPI_DATA_NONE)
00817   {
00818     if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
00819     {
00820       assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
00821     }
00822     assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
00823     assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
00824   }
00825
00826   assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
00827   assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
00828
00829   /* Check the state of the driver */
00830   state = hospi->State;
00831   if (((state == HAL_OSPI_STATE_READY)         && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
00832       ((state == HAL_OSPI_STATE_READ_CMD_CFG)  && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
00833       ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)  || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
00834   {
00835     /* Wait till busy flag is reset */
00836     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00837
00838     if (status == HAL_OK)
00839     {
00840       /* Initialize error code */
00841       hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
00842
00843       /* Configure the registers */
00844       status = OSPI_ConfigCmd(hospi, cmd);
00845
00846       if (status == HAL_OK)
00847       {
00848         if (cmd->DataMode == HAL_OSPI_DATA_NONE)
00849         {
00850           /* When there is no data phase, the transfer start as soon as the configuration is done
00851              so wait until TC flag is set to go back in idle state */
00852           status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
00853
00854           __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
00855         }
00856         else
00857         {
00858           /* Update the state */
00859           if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
00860           {
00861             hospi->State = HAL_OSPI_STATE_CMD_CFG;
00862           }
00863           else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)
00864           {
00865             if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG)
00866             {
00867               hospi->State = HAL_OSPI_STATE_CMD_CFG;
00868             }
00869             else
00870             {
00871               hospi->State = HAL_OSPI_STATE_READ_CMD_CFG;
00872             }
00873           }
00874           else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
00875           {
00876             if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG)
00877             {
00878               hospi->State = HAL_OSPI_STATE_CMD_CFG;
00879             }
00880             else
00881             {
00882               hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG;
00883             }
00884           }
00885           else
00886           {
00887             /* Wrap configuration, no state change */
00888           }
00889         }
00890       }
00891     }
00892   }
00893   else
00894   {
00895     status = HAL_ERROR;
00896     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
00897   }
00898
00899   /* Return function status */
00900   return status;
00901 }
00902
00903 /**
00904   * @brief  Set the command configuration in interrupt mode.
00905   * @param  hospi : OSPI handle
00906   * @param  cmd   : structure that contains the command configuration information
00907   * @note   This function is used only in Indirect Read or Write Modes
00908   * @retval HAL status
00909   */
00910 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
00911 {
00912   HAL_StatusTypeDef status;
00913   uint32_t tickstart = HAL_GetTick();
00914
00915   /* Check the parameters of the command structure */
00916   assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
00917
00918   if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
00919   {
00920     assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
00921   }
00922
00923   assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00924   if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
00925   {
00926     assert_param(IS_OSPI_INSTRUCTION_SIZE    (cmd->InstructionSize));
00927     assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
00928   }
00929
00930   assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
00931   if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
00932   {
00933     assert_param(IS_OSPI_ADDRESS_SIZE    (cmd->AddressSize));
00934     assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
00935   }
00936
00937   assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
00938   if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
00939   {
00940     assert_param(IS_OSPI_ALT_BYTES_SIZE    (cmd->AlternateBytesSize));
00941     assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
00942   }
00943
00944   assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
00945   if (cmd->DataMode != HAL_OSPI_DATA_NONE)
00946   {
00947     assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
00948     assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
00949     assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
00950   }
00951
00952   assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
00953   assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
00954
00955   /* Check the state of the driver */
00956   if ((hospi->State  == HAL_OSPI_STATE_READY) && (cmd->OperationType     == HAL_OSPI_OPTYPE_COMMON_CFG) &&
00957       (cmd->DataMode == HAL_OSPI_DATA_NONE)   && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS))
00958   {
00959     /* Wait till busy flag is reset */
00960     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
00961
00962     if (status == HAL_OK)
00963     {
00964       /* Initialize error code */
00965       hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
00966
00967       /* Clear flags related to interrupt */
00968       __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
00969
00970       /* Configure the registers */
00971       status = OSPI_ConfigCmd(hospi, cmd);
00972
00973       if (status == HAL_OK)
00974       {
00975         /* Update the state */
00976           hospi->State = HAL_OSPI_STATE_BUSY_CMD;
00977
00978         /* Enable the transfer complete and transfer error interrupts */
00979         __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
00980       }
00981     }
00982   }
00983   else
00984   {
00985     status = HAL_ERROR;
00986     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
00987   }
00988
00989   /* Return function status */
00990   return status;
00991 }
00992
00993 /**
00994   * @brief  Configure the Hyperbus parameters.
00995   * @param  hospi   : OSPI handle
00996   * @param  cfg     : Structure containing the Hyperbus configuration
00997   * @param  Timeout : Timeout duration
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
01001 {
01002   HAL_StatusTypeDef status;
01003   uint32_t state;
01004   uint32_t tickstart = HAL_GetTick();
01005
01006   /* Check the parameters of the hyperbus configuration structure */
01007   assert_param(IS_OSPI_RW_RECOVERY_TIME  (cfg->RWRecoveryTime));
01008   assert_param(IS_OSPI_ACCESS_TIME       (cfg->AccessTime));
01009   assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
01010   assert_param(IS_OSPI_LATENCY_MODE      (cfg->LatencyMode));
01011
01012   /* Check the state of the driver */
01013   state = hospi->State;
01014   if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY))
01015   {
01016     /* Wait till busy flag is reset */
01017     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01018
01019     if (status == HAL_OK)
01020     {
01021       /* Configure Hyperbus configuration Latency register */
01022       WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) |
01023                                         (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos)     |
01024                                         cfg->WriteZeroLatency | cfg->LatencyMode));
01025
01026       /* Update the state */
01027       hospi->State = HAL_OSPI_STATE_READY;
01028     }
01029   }
01030   else
01031   {
01032     status = HAL_ERROR;
01033     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01034   }
01035
01036   /* Return function status */
01037   return status;
01038 }
01039
01040 /**
01041   * @brief  Set the Hyperbus command configuration.
01042   * @param  hospi   : OSPI handle
01043   * @param  cmd     : Structure containing the Hyperbus command
01044   * @param  Timeout : Timeout duration
01045   * @retval HAL status
01046   */
01047 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
01048 {
01049   HAL_StatusTypeDef status;
01050   uint32_t tickstart = HAL_GetTick();
01051
01052   /* Check the parameters of the hyperbus command structure */
01053   assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
01054   assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
01055   assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
01056   assert_param(IS_OSPI_DQS_MODE     (cmd->DQSMode));
01057
01058   /* Check the state of the driver */
01059   if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
01060   {
01061     /* Wait till busy flag is reset */
01062     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01063
01064     if (status == HAL_OK)
01065     {
01066       /* Re-initialize the value of the functional mode */
01067       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
01068
01069       /* Configure the address space in the DCR1 register */
01070       MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace);
01071
01072       /* Configure the CCR and WCCR registers with the address size and the following configuration :
01073          - DQS signal enabled (used as RWDS)
01074          - DTR mode enabled on address and data
01075          - address and data on 8 lines */
01076       WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 |
01077                                        cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2));
01078       WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 |
01079                                         cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2));
01080
01081       /* Configure the DLR register with the number of data */
01082       WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U));
01083
01084       /* Configure the AR register with the address value */
01085       WRITE_REG(hospi->Instance->AR, cmd->Address);
01086
01087       /* Update the state */
01088       hospi->State = HAL_OSPI_STATE_CMD_CFG;
01089     }
01090   }
01091   else
01092   {
01093     status = HAL_ERROR;
01094     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01095   }
01096
01097   /* Return function status */
01098   return status;
01099 }
01100
01101 /**
01102   * @brief  Transmit an amount of data in blocking mode.
01103   * @param  hospi   : OSPI handle
01104   * @param  pData   : pointer to data buffer
01105   * @param  Timeout : Timeout duration
01106   * @note   This function is used only in Indirect Write Mode
01107   * @retval HAL status
01108   */
01109 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
01110 {
01111   HAL_StatusTypeDef status;
01112   uint32_t tickstart = HAL_GetTick();
01113   __IO uint32_t *data_reg = &hospi->Instance->DR;
01114
01115   /* Check the data pointer allocation */
01116   if (pData == NULL)
01117   {
01118     status = HAL_ERROR;
01119     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01120   }
01121   else
01122   {
01123     /* Check the state */
01124     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01125     {
01126       /* Configure counters and size */
01127       hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
01128       hospi->XferSize  = hospi->XferCount;
01129       hospi->pBuffPtr  = pData;
01130
01131       /* Configure CR register with functional mode as indirect write */
01132       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01133
01134       do
01135       {
01136         /* Wait till fifo threshold flag is set to send data */
01137         status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout);
01138
01139         if (status != HAL_OK)
01140         {
01141           break;
01142         }
01143
01144         *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
01145         hospi->pBuffPtr++;
01146         hospi->XferCount--;
01147       } while (hospi->XferCount > 0U);
01148
01149       if (status == HAL_OK)
01150       {
01151         /* Wait till transfer complete flag is set to go back in idle state */
01152         status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
01153
01154         if (status == HAL_OK)
01155         {
01156           /* Clear transfer complete flag */
01157           __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
01158
01159           /* Update state */
01160           hospi->State = HAL_OSPI_STATE_READY;
01161         }
01162       }
01163     }
01164     else
01165     {
01166       status = HAL_ERROR;
01167       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01168     }
01169   }
01170
01171   /* Return function status */
01172   return status;
01173 }
01174
01175 /**
01176   * @brief  Receive an amount of data in blocking mode.
01177   * @param  hospi   : OSPI handle
01178   * @param  pData   : pointer to data buffer
01179   * @param  Timeout : Timeout duration
01180   * @note   This function is used only in Indirect Read Mode
01181   * @retval HAL status
01182   */
01183 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
01184 {
01185   HAL_StatusTypeDef status;
01186   uint32_t tickstart = HAL_GetTick();
01187   __IO uint32_t *data_reg = &hospi->Instance->DR;
01188   uint32_t addr_reg = hospi->Instance->AR;
01189   uint32_t ir_reg = hospi->Instance->IR;
01190
01191   /* Check the data pointer allocation */
01192   if (pData == NULL)
01193   {
01194     status = HAL_ERROR;
01195     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01196   }
01197   else
01198   {
01199     /* Check the state */
01200     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01201     {
01202       /* Configure counters and size */
01203       hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
01204       hospi->XferSize  = hospi->XferCount;
01205       hospi->pBuffPtr  = pData;
01206
01207       /* Configure CR register with functional mode as indirect read */
01208       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01209
01210       /* Trig the transfer by re-writing address or instruction register */
01211       if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
01212       {
01213         WRITE_REG(hospi->Instance->AR, addr_reg);
01214       }
01215       else
01216       {
01217         if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
01218         {
01219           WRITE_REG(hospi->Instance->AR, addr_reg);
01220         }
01221         else
01222         {
01223           WRITE_REG(hospi->Instance->IR, ir_reg);
01224         }
01225       }
01226
01227       do
01228       {
01229         /* Wait till fifo threshold or transfer complete flags are set to read received data */
01230         status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout);
01231
01232         if (status != HAL_OK)
01233         {
01234           break;
01235         }
01236
01237         *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
01238         hospi->pBuffPtr++;
01239         hospi->XferCount--;
01240       } while(hospi->XferCount > 0U);
01241
01242       if (status == HAL_OK)
01243       {
01244         /* Wait till transfer complete flag is set to go back in idle state */
01245         status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
01246
01247         if (status == HAL_OK)
01248         {
01249           /* Clear transfer complete flag */
01250           __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
01251
01252           /* Update state */
01253           hospi->State = HAL_OSPI_STATE_READY;
01254         }
01255       }
01256     }
01257     else
01258     {
01259       status = HAL_ERROR;
01260       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01261     }
01262   }
01263
01264   /* Return function status */
01265   return status;
01266 }
01267
01268 /**
01269   * @brief  Send an amount of data in non-blocking mode with interrupt.
01270   * @param  hospi : OSPI handle
01271   * @param  pData : pointer to data buffer
01272   * @note   This function is used only in Indirect Write Mode
01273   * @retval HAL status
01274   */
01275 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
01276 {
01277   HAL_StatusTypeDef status = HAL_OK;
01278
01279   /* Check the data pointer allocation */
01280   if (pData == NULL)
01281   {
01282     status = HAL_ERROR;
01283     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01284   }
01285   else
01286   {
01287     /* Check the state */
01288     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01289     {
01290       /* Configure counters and size */
01291       hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
01292       hospi->XferSize  = hospi->XferCount;
01293       hospi->pBuffPtr  = pData;
01294
01295       /* Configure CR register with functional mode as indirect write */
01296       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01297
01298       /* Clear flags related to interrupt */
01299       __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
01300
01301       /* Update the state */
01302       hospi->State = HAL_OSPI_STATE_BUSY_TX;
01303
01304       /* Enable the transfer complete, fifo threshold and transfer error interrupts */
01305       __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
01306     }
01307     else
01308     {
01309       status = HAL_ERROR;
01310       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01311     }
01312   }
01313
01314   /* Return function status */
01315   return status;
01316 }
01317
01318 /**
01319   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01320   * @param  hospi : OSPI handle
01321   * @param  pData : pointer to data buffer
01322   * @note   This function is used only in Indirect Read Mode
01323   * @retval HAL status
01324   */
01325 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
01326 {
01327   HAL_StatusTypeDef status = HAL_OK;
01328   uint32_t addr_reg = hospi->Instance->AR;
01329   uint32_t ir_reg = hospi->Instance->IR;
01330
01331   /* Check the data pointer allocation */
01332   if (pData == NULL)
01333   {
01334     status = HAL_ERROR;
01335     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01336   }
01337   else
01338   {
01339     /* Check the state */
01340     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01341     {
01342       /* Configure counters and size */
01343       hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
01344       hospi->XferSize  = hospi->XferCount;
01345       hospi->pBuffPtr  = pData;
01346
01347       /* Configure CR register with functional mode as indirect read */
01348       MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01349
01350       /* Clear flags related to interrupt */
01351       __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
01352
01353       /* Update the state */
01354       hospi->State = HAL_OSPI_STATE_BUSY_RX;
01355
01356       /* Enable the transfer complete, fifo threshold and transfer error interrupts */
01357       __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
01358
01359       /* Trig the transfer by re-writing address or instruction register */
01360       if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
01361       {
01362         WRITE_REG(hospi->Instance->AR, addr_reg);
01363       }
01364       else
01365       {
01366         if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
01367         {
01368           WRITE_REG(hospi->Instance->AR, addr_reg);
01369         }
01370         else
01371         {
01372           WRITE_REG(hospi->Instance->IR, ir_reg);
01373         }
01374       }
01375     }
01376     else
01377     {
01378       status = HAL_ERROR;
01379       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01380     }
01381   }
01382
01383   /* Return function status */
01384   return status;
01385 }
01386
01387 /**
01388   * @brief  Send an amount of data in non-blocking mode with DMA.
01389   * @param  hospi : OSPI handle
01390   * @param  pData : pointer to data buffer
01391   * @note   This function is used only in Indirect Write Mode
01392   * @note   If DMA peripheral access is configured as halfword, the number
01393   *         of data and the fifo threshold should be aligned on halfword
01394   * @note   If DMA peripheral access is configured as word, the number
01395   *         of data and the fifo threshold should be aligned on word
01396   * @retval HAL status
01397   */
01398 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
01399 {
01400   HAL_StatusTypeDef status = HAL_OK;
01401   uint32_t data_size = hospi->Instance->DLR + 1U;
01402
01403   /* Check the data pointer allocation */
01404   if (pData == NULL)
01405   {
01406     status = HAL_ERROR;
01407     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01408   }
01409   else
01410   {
01411     /* Check the state */
01412     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01413     {
01414       hospi->XferCount = data_size;
01415
01416       if (status == HAL_OK)
01417       {
01418         hospi->XferSize = hospi->XferCount;
01419         hospi->pBuffPtr = pData;
01420
01421         /* Configure CR register with functional mode as indirect write */
01422         MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01423
01424         /* Clear flags related to interrupt */
01425         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
01426
01427         /* Update the state */
01428         hospi->State = HAL_OSPI_STATE_BUSY_TX;
01429
01430         /* Set the MDMA transfer complete callback */
01431         hospi->hmdma->XferCpltCallback = OSPI_DMACplt;
01432
01433         /* Set the MDMA error callback */
01434         hospi->hmdma->XferErrorCallback = OSPI_DMAError;
01435
01436         /* Clear the MDMA abort callback */
01437         hospi->hmdma->XferAbortCallback = NULL;
01438
01439         /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */
01440         MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
01441
01442         /* Update MDMA configuration with the correct SourceInc field for Write operation */
01443         if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
01444         {
01445           MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
01446         }
01447         else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
01448         {
01449           MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
01450         }
01451         else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
01452         {
01453           MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
01454         }
01455         else
01456         {
01457           /* in case of incorrect source data size */
01458           hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
01459           status = HAL_ERROR;
01460         }
01461
01462         /* Enable the transmit MDMA Channel */
01463         if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
01464         {
01465           /* Enable the transfer error interrupt */
01466           __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
01467
01468           /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
01469         }
01470         else
01471         {
01472           status = HAL_ERROR;
01473           hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
01474           hospi->State = HAL_OSPI_STATE_READY;
01475         }
01476       }
01477     }
01478     else
01479     {
01480       status = HAL_ERROR;
01481       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01482     }
01483   }
01484
01485   /* Return function status */
01486   return status;
01487 }
01488
01489 /**
01490   * @brief  Receive an amount of data in non-blocking mode with DMA.
01491   * @param  hospi : OSPI handle
01492   * @param  pData : pointer to data buffer.
01493   * @note   This function is used only in Indirect Read Mode
01494   * @note   If DMA peripheral access is configured as halfword, the number
01495   *         of data and the fifo threshold should be aligned on halfword
01496   * @note   If DMA peripheral access is configured as word, the number
01497   *         of data and the fifo threshold should be aligned on word
01498   * @retval HAL status
01499   */
01500 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
01501 {
01502   HAL_StatusTypeDef status = HAL_OK;
01503   uint32_t data_size = hospi->Instance->DLR + 1U;
01504   uint32_t addr_reg = hospi->Instance->AR;
01505   uint32_t ir_reg = hospi->Instance->IR;
01506
01507   /* Check the data pointer allocation */
01508   if (pData == NULL)
01509   {
01510     status = HAL_ERROR;
01511     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
01512   }
01513   else
01514   {
01515     /* Check the state */
01516     if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01517     {
01518       hospi->XferCount = data_size;
01519
01520       if (status == HAL_OK)
01521       {
01522         hospi->XferSize  = hospi->XferCount;
01523         hospi->pBuffPtr  = pData;
01524
01525         /* Configure CR register with functional mode as indirect read */
01526         MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01527
01528         /* Clear flags related to interrupt */
01529         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
01530
01531         /* Update the state */
01532         hospi->State = HAL_OSPI_STATE_BUSY_RX;
01533
01534         /* Set the DMA transfer complete callback */
01535         hospi->hmdma->XferCpltCallback = OSPI_DMACplt;
01536
01537         /* Set the DMA error callback */
01538         hospi->hmdma->XferErrorCallback = OSPI_DMAError;
01539
01540         /* Clear the DMA abort callback */
01541         hospi->hmdma->XferAbortCallback = NULL;
01542
01543 /* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
01544       MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
01545
01546       /* Update MDMA configuration with the correct DestinationInc field for read operation */
01547       if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
01548       {
01549         MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
01550       }
01551       else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
01552       {
01553         MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
01554       }
01555       else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
01556       {
01557         MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
01558       }
01559       else
01560       {
01561        /* in case of incorrect destination data size */
01562         hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
01563         status = HAL_ERROR;
01564       }
01565
01566         /* Enable the transmit MDMA Channel */
01567         if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK)
01568         {
01569           /* Enable the transfer error interrupt */
01570           __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
01571
01572           /* Trig the transfer by re-writing address or instruction register */
01573           if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
01574           {
01575             WRITE_REG(hospi->Instance->AR, addr_reg);
01576           }
01577           else
01578           {
01579             if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
01580             {
01581               WRITE_REG(hospi->Instance->AR, addr_reg);
01582             }
01583             else
01584             {
01585               WRITE_REG(hospi->Instance->IR, ir_reg);
01586             }
01587           }
01588
01589           /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
01590         }
01591         else
01592         {
01593           status = HAL_ERROR;
01594           hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
01595           hospi->State = HAL_OSPI_STATE_READY;
01596         }
01597       }
01598     }
01599     else
01600     {
01601       status = HAL_ERROR;
01602       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01603     }
01604   }
01605
01606   /* Return function status */
01607   return status;
01608 }
01609
01610 /**
01611   * @brief  Configure the OSPI Automatic Polling Mode in blocking mode.
01612   * @param  hospi   : OSPI handle
01613   * @param  cfg     : structure that contains the polling configuration information.
01614   * @param  Timeout : Timeout duration
01615   * @note   This function is used only in Automatic Polling Mode
01616   * @retval HAL status
01617   */
01618 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01619 {
01620   HAL_StatusTypeDef status;
01621   uint32_t tickstart = HAL_GetTick();
01622   uint32_t addr_reg = hospi->Instance->AR;
01623   uint32_t ir_reg = hospi->Instance->IR;
01624 #ifdef USE_FULL_ASSERT
01625   uint32_t dlr_reg = hospi->Instance->DLR;
01626 #endif
01627
01628   /* Check the parameters of the autopolling configuration structure */
01629   assert_param(IS_OSPI_MATCH_MODE       (cfg->MatchMode));
01630   assert_param(IS_OSPI_AUTOMATIC_STOP   (cfg->AutomaticStop));
01631   assert_param(IS_OSPI_INTERVAL         (cfg->Interval));
01632   assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
01633
01634   /* Check the state */
01635   if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
01636   {
01637     /* Wait till busy flag is reset */
01638     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01639
01640     if (status == HAL_OK)
01641     {
01642       /* Configure registers */
01643       WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
01644       WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
01645       WRITE_REG (hospi->Instance->PIR,   cfg->Interval);
01646       MODIFY_REG(hospi->Instance->CR,    (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
01647                  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
01648
01649       /* Trig the transfer by re-writing address or instruction register */
01650       if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
01651       {
01652         WRITE_REG(hospi->Instance->AR, addr_reg);
01653       }
01654       else
01655       {
01656         if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
01657         {
01658           WRITE_REG(hospi->Instance->AR, addr_reg);
01659         }
01660         else
01661         {
01662           WRITE_REG(hospi->Instance->IR, ir_reg);
01663         }
01664       }
01665
01666       /* Wait till status match flag is set to go back in idle state */
01667       status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout);
01668
01669       if (status == HAL_OK)
01670       {
01671         /* Clear status match flag */
01672         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM);
01673
01674         /* Update state */
01675         hospi->State = HAL_OSPI_STATE_READY;
01676       }
01677     }
01678   }
01679   else
01680   {
01681     status = HAL_ERROR;
01682     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01683   }
01684
01685   /* Return function status */
01686   return status;
01687 }
01688
01689 /**
01690   * @brief  Configure the OSPI Automatic Polling Mode in non-blocking mode.
01691   * @param  hospi : OSPI handle
01692   * @param  cfg   : structure that contains the polling configuration information.
01693   * @note   This function is used only in Automatic Polling Mode
01694   * @retval HAL status
01695   */
01696 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
01697 {
01698   HAL_StatusTypeDef status;
01699   uint32_t tickstart = HAL_GetTick();
01700   uint32_t addr_reg = hospi->Instance->AR;
01701   uint32_t ir_reg = hospi->Instance->IR;
01702 #ifdef USE_FULL_ASSERT
01703   uint32_t dlr_reg = hospi->Instance->DLR;
01704 #endif
01705
01706   /* Check the parameters of the autopolling configuration structure */
01707   assert_param(IS_OSPI_MATCH_MODE       (cfg->MatchMode));
01708   assert_param(IS_OSPI_AUTOMATIC_STOP   (cfg->AutomaticStop));
01709   assert_param(IS_OSPI_INTERVAL         (cfg->Interval));
01710   assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
01711
01712   /* Check the state */
01713   if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01714   {
01715     /* Wait till busy flag is reset */
01716     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
01717
01718     if (status == HAL_OK)
01719     {
01720       /* Configure registers */
01721       WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
01722       WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
01723       WRITE_REG (hospi->Instance->PIR,   cfg->Interval);
01724       MODIFY_REG(hospi->Instance->CR,    (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
01725                  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
01726
01727       /* Clear flags related to interrupt */
01728       __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM);
01729
01730       /* Update state */
01731       hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING;
01732
01733       /* Enable the status match and transfer error interrupts */
01734       __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
01735
01736       /* Trig the transfer by re-writing address or instruction register */
01737       if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
01738       {
01739         WRITE_REG(hospi->Instance->AR, addr_reg);
01740       }
01741       else
01742       {
01743         if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
01744         {
01745           WRITE_REG(hospi->Instance->AR, addr_reg);
01746         }
01747         else
01748         {
01749           WRITE_REG(hospi->Instance->IR, ir_reg);
01750         }
01751       }
01752     }
01753   }
01754   else
01755   {
01756     status = HAL_ERROR;
01757     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01758   }
01759
01760   /* Return function status */
01761   return status;
01762 }
01763
01764 /**
01765   * @brief  Configure the Memory Mapped mode.
01766   * @param  hospi : OSPI handle
01767   * @param  cfg   : structure that contains the memory mapped configuration information.
01768   * @note   This function is used only in Memory mapped Mode
01769   * @retval HAL status
01770   */
01771 HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
01772 {
01773   HAL_StatusTypeDef status;
01774   uint32_t tickstart = HAL_GetTick();
01775
01776   /* Check the parameters of the memory-mapped configuration structure */
01777   assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01778
01779   /* Check the state */
01780   if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
01781   {
01782     /* Wait till busy flag is reset */
01783     status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
01784
01785     if (status == HAL_OK)
01786     {
01787       /* Update state */
01788       hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
01789
01790       if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)
01791       {
01792         assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01793
01794         /* Configure register */
01795         WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod);
01796
01797         /* Clear flags related to interrupt */
01798         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO);
01799
01800         /* Enable the timeout interrupt */
01801         __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO);
01802       }
01803
01804       /* Configure CR register with functional mode as memory-mapped */
01805       MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE),
01806                  (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED));
01807     }
01808   }
01809   else
01810   {
01811     status = HAL_ERROR;
01812     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
01813   }
01814
01815   /* Return function status */
01816   return status;
01817 }
01818
01819 /**
01820   * @brief  Transfer Error callback.
01821   * @param  hospi : OSPI handle
01822   * @retval None
01823   */
01824 __weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
01825 {
01826   /* Prevent unused argument(s) compilation warning */
01827   UNUSED(hospi);
01828
01829   /* NOTE : This function should not be modified, when the callback is needed,
01830             the HAL_OSPI_ErrorCallback could be implemented in the user file
01831    */
01832 }
01833
01834 /**
01835   * @brief  Abort completed callback.
01836   * @param  hospi : OSPI handle
01837   * @retval None
01838   */
01839 __weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi)
01840 {
01841   /* Prevent unused argument(s) compilation warning */
01842   UNUSED(hospi);
01843
01844   /* NOTE: This function should not be modified, when the callback is needed,
01845            the HAL_OSPI_AbortCpltCallback could be implemented in the user file
01846    */
01847 }
01848
01849 /**
01850   * @brief  FIFO Threshold callback.
01851   * @param  hospi : OSPI handle
01852   * @retval None
01853   */
01854 __weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi)
01855 {
01856   /* Prevent unused argument(s) compilation warning */
01857   UNUSED(hospi);
01858
01859   /* NOTE : This function should not be modified, when the callback is needed,
01860             the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file
01861    */
01862 }
01863
01864 /**
01865   * @brief  Command completed callback.
01866   * @param  hospi : OSPI handle
01867   * @retval None
01868   */
01869 __weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
01870 {
01871   /* Prevent unused argument(s) compilation warning */
01872   UNUSED(hospi);
01873
01874   /* NOTE: This function should not be modified, when the callback is needed,
01875            the HAL_OSPI_CmdCpltCallback could be implemented in the user file
01876    */
01877 }
01878
01879 /**
01880   * @brief  Rx Transfer completed callback.
01881   * @param  hospi : OSPI handle
01882   * @retval None
01883   */
01884 __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
01885 {
01886   /* Prevent unused argument(s) compilation warning */
01887   UNUSED(hospi);
01888
01889   /* NOTE: This function should not be modified, when the callback is needed,
01890            the HAL_OSPI_RxCpltCallback could be implemented in the user file
01891    */
01892 }
01893
01894 /**
01895   * @brief  Tx Transfer completed callback.
01896   * @param  hospi : OSPI handle
01897   * @retval None
01898   */
01899  __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
01900 {
01901   /* Prevent unused argument(s) compilation warning */
01902   UNUSED(hospi);
01903
01904   /* NOTE: This function should not be modified, when the callback is needed,
01905            the HAL_OSPI_TxCpltCallback could be implemented in the user file
01906    */
01907 }
01908
01909 /**
01910   * @brief  Rx Half Transfer completed callback.
01911   * @param  hospi : OSPI handle
01912   * @retval None
01913   */
01914 __weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
01915 {
01916   /* Prevent unused argument(s) compilation warning */
01917   UNUSED(hospi);
01918
01919   /* NOTE: This function should not be modified, when the callback is needed,
01920            the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file
01921    */
01922 }
01923
01924 /**
01925   * @brief  Tx Half Transfer completed callback.
01926   * @param  hospi : OSPI handle
01927   * @retval None
01928   */
01929 __weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
01930 {
01931   /* Prevent unused argument(s) compilation warning */
01932   UNUSED(hospi);
01933
01934   /* NOTE: This function should not be modified, when the callback is needed,
01935            the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file
01936    */
01937 }
01938
01939 /**
01940   * @brief  Status Match callback.
01941   * @param  hospi : OSPI handle
01942   * @retval None
01943   */
01944 __weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
01945 {
01946   /* Prevent unused argument(s) compilation warning */
01947   UNUSED(hospi);
01948
01949   /* NOTE : This function should not be modified, when the callback is needed,
01950             the HAL_OSPI_StatusMatchCallback could be implemented in the user file
01951    */
01952 }
01953
01954 /**
01955   * @brief  Timeout callback.
01956   * @param  hospi : OSPI handle
01957   * @retval None
01958   */
01959 __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
01960 {
01961   /* Prevent unused argument(s) compilation warning */
01962   UNUSED(hospi);
01963
01964   /* NOTE : This function should not be modified, when the callback is needed,
01965             the HAL_OSPI_TimeOutCallback could be implemented in the user file
01966    */
01967 }
01968
01969 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
01970 /**
01971   * @brief  Register a User OSPI Callback
01972   *         To be used instead of the weak (surcharged) predefined callback
01973   * @param hospi : OSPI handle
01974   * @param CallbackID : ID of the callback to be registered
01975   *        This parameter can be one of the following values:
01976   *          @arg @ref HAL_OSPI_ERROR_CB_ID          OSPI Error Callback ID
01977   *          @arg @ref HAL_OSPI_ABORT_CB_ID          OSPI Abort Callback ID
01978   *          @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
01979   *          @arg @ref HAL_OSPI_CMD_CPLT_CB_ID       OSPI Command Complete Callback ID
01980   *          @arg @ref HAL_OSPI_RX_CPLT_CB_ID        OSPI Rx Complete Callback ID
01981   *          @arg @ref HAL_OSPI_TX_CPLT_CB_ID        OSPI Tx Complete Callback ID
01982   *          @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID   OSPI Rx Half Complete Callback ID
01983   *          @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID   OSPI Tx Half Complete Callback ID
01984   *          @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID   OSPI Status Match Callback ID
01985   *          @arg @ref HAL_OSPI_TIMEOUT_CB_ID        OSPI Timeout Callback ID
01986   *          @arg @ref HAL_OSPI_MSP_INIT_CB_ID       OSPI MspInit callback ID
01987   *          @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID     OSPI MspDeInit callback ID
01988   * @param pCallback : pointer to the Callback function
01989   * @retval status
01990   */
01991 HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
01992 {
01993   HAL_StatusTypeDef status = HAL_OK;
01994
01995   if(pCallback == NULL)
01996   {
01997     /* Update the error code */
01998     hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
01999     return HAL_ERROR;
02000   }
02001
02002   if(hospi->State == HAL_OSPI_STATE_READY)
02003   {
02004     switch (CallbackID)
02005     {
02006     case  HAL_OSPI_ERROR_CB_ID :
02007       hospi->ErrorCallback = pCallback;
02008       break;
02009     case HAL_OSPI_ABORT_CB_ID :
02010       hospi->AbortCpltCallback = pCallback;
02011       break;
02012     case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
02013       hospi->FifoThresholdCallback = pCallback;
02014       break;
02015     case HAL_OSPI_CMD_CPLT_CB_ID :
02016       hospi->CmdCpltCallback = pCallback;
02017       break;
02018     case HAL_OSPI_RX_CPLT_CB_ID :
02019       hospi->RxCpltCallback = pCallback;
02020       break;
02021     case HAL_OSPI_TX_CPLT_CB_ID :
02022       hospi->TxCpltCallback = pCallback;
02023       break;
02024     case HAL_OSPI_RX_HALF_CPLT_CB_ID :
02025       hospi->RxHalfCpltCallback = pCallback;
02026       break;
02027     case HAL_OSPI_TX_HALF_CPLT_CB_ID :
02028       hospi->TxHalfCpltCallback = pCallback;
02029       break;
02030     case HAL_OSPI_STATUS_MATCH_CB_ID :
02031       hospi->StatusMatchCallback = pCallback;
02032       break;
02033     case HAL_OSPI_TIMEOUT_CB_ID :
02034       hospi->TimeOutCallback = pCallback;
02035       break;
02036     case HAL_OSPI_MSP_INIT_CB_ID :
02037       hospi->MspInitCallback = pCallback;
02038       break;
02039     case HAL_OSPI_MSP_DEINIT_CB_ID :
02040       hospi->MspDeInitCallback = pCallback;
02041       break;
02042     default :
02043       /* Update the error code */
02044       hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02045       /* update return status */
02046       status =  HAL_ERROR;
02047       break;
02048     }
02049   }
02050   else if (hospi->State == HAL_OSPI_STATE_RESET)
02051   {
02052     switch (CallbackID)
02053     {
02054     case HAL_OSPI_MSP_INIT_CB_ID :
02055       hospi->MspInitCallback = pCallback;
02056       break;
02057     case HAL_OSPI_MSP_DEINIT_CB_ID :
02058       hospi->MspDeInitCallback = pCallback;
02059       break;
02060     default :
02061       /* Update the error code */
02062       hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02063       /* update return status */
02064       status =  HAL_ERROR;
02065       break;
02066     }
02067   }
02068   else
02069   {
02070     /* Update the error code */
02071     hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02072     /* update return status */
02073     status =  HAL_ERROR;
02074   }
02075
02076   return status;
02077 }
02078
02079 /**
02080   * @brief  Unregister a User OSPI Callback
02081   *         OSPI Callback is redirected to the weak (surcharged) predefined callback
02082   * @param hospi : OSPI handle
02083   * @param CallbackID : ID of the callback to be unregistered
02084   *        This parameter can be one of the following values:
02085   *          @arg @ref HAL_OSPI_ERROR_CB_ID          OSPI Error Callback ID
02086   *          @arg @ref HAL_OSPI_ABORT_CB_ID          OSPI Abort Callback ID
02087   *          @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
02088   *          @arg @ref HAL_OSPI_CMD_CPLT_CB_ID       OSPI Command Complete Callback ID
02089   *          @arg @ref HAL_OSPI_RX_CPLT_CB_ID        OSPI Rx Complete Callback ID
02090   *          @arg @ref HAL_OSPI_TX_CPLT_CB_ID        OSPI Tx Complete Callback ID
02091   *          @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID   OSPI Rx Half Complete Callback ID
02092   *          @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID   OSPI Tx Half Complete Callback ID
02093   *          @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID   OSPI Status Match Callback ID
02094   *          @arg @ref HAL_OSPI_TIMEOUT_CB_ID        OSPI Timeout Callback ID
02095   *          @arg @ref HAL_OSPI_MSP_INIT_CB_ID       OSPI MspInit callback ID
02096   *          @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID     OSPI MspDeInit callback ID
02097   * @retval status
02098   */
02099 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
02100 {
02101   HAL_StatusTypeDef status = HAL_OK;
02102
02103   if(hospi->State == HAL_OSPI_STATE_READY)
02104   {
02105     switch (CallbackID)
02106     {
02107     case  HAL_OSPI_ERROR_CB_ID :
02108       hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
02109       break;
02110     case HAL_OSPI_ABORT_CB_ID :
02111       hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
02112       break;
02113     case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
02114       hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
02115       break;
02116     case HAL_OSPI_CMD_CPLT_CB_ID :
02117       hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
02118       break;
02119     case HAL_OSPI_RX_CPLT_CB_ID :
02120       hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
02121       break;
02122     case HAL_OSPI_TX_CPLT_CB_ID :
02123       hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
02124       break;
02125     case HAL_OSPI_RX_HALF_CPLT_CB_ID :
02126       hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
02127       break;
02128     case HAL_OSPI_TX_HALF_CPLT_CB_ID :
02129       hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
02130       break;
02131     case HAL_OSPI_STATUS_MATCH_CB_ID :
02132       hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
02133       break;
02134     case HAL_OSPI_TIMEOUT_CB_ID :
02135       hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
02136       break;
02137     case HAL_OSPI_MSP_INIT_CB_ID :
02138       hospi->MspInitCallback = HAL_OSPI_MspInit;
02139       break;
02140     case HAL_OSPI_MSP_DEINIT_CB_ID :
02141       hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
02142       break;
02143     default :
02144       /* Update the error code */
02145       hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02146       /* update return status */
02147       status =  HAL_ERROR;
02148       break;
02149     }
02150   }
02151   else if (hospi->State == HAL_OSPI_STATE_RESET)
02152   {
02153     switch (CallbackID)
02154     {
02155     case HAL_OSPI_MSP_INIT_CB_ID :
02156       hospi->MspInitCallback = HAL_OSPI_MspInit;
02157       break;
02158     case HAL_OSPI_MSP_DEINIT_CB_ID :
02159       hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
02160       break;
02161     default :
02162       /* Update the error code */
02163       hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02164       /* update return status */
02165       status =  HAL_ERROR;
02166       break;
02167     }
02168   }
02169   else
02170   {
02171     /* Update the error code */
02172     hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
02173     /* update return status */
02174     status =  HAL_ERROR;
02175   }
02176
02177   return status;
02178 }
02179 #endif
02180
02181 /**
02182   * @}
02183   */
02184
02185 /** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions
02186   *  @brief   OSPI control and State functions
02187   *
02188 @verbatim
02189  ===============================================================================
02190                   ##### Peripheral Control and State functions #####
02191  ===============================================================================
02192     [..]
02193     This subsection provides a set of functions allowing to :
02194       (+) Check in run-time the state of the driver.
02195       (+) Check the error code set during last operation.
02196       (+) Abort any operation.
02197       (+) Manage the Fifo threshold.
02198       (+) Configure the timeout duration used in the driver.
02199
02200 @endverbatim
02201   * @{
02202   */
02203
02204 /**
02205 * @brief  Abort the current transmission.
02206 * @param  hospi : OSPI handle
02207 * @retval HAL status
02208 */
02209 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
02210 {
02211   HAL_StatusTypeDef status = HAL_OK;
02212   uint32_t state;
02213   uint32_t tickstart = HAL_GetTick();
02214
02215   /* Check if the state is in one of the busy or configured states */
02216   state = hospi->State;
02217   if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
02218   {
02219     /* Check if the DMA is enabled */
02220     if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
02221     {
02222       /* Disable the DMA transfer on the OctoSPI side */
02223       CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
02224
02225       /* Disable the DMA transfer on the DMA side */
02226       status = HAL_MDMA_Abort(hospi->hmdma);
02227       if (status != HAL_OK)
02228       {
02229         hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
02230       }
02231     }
02232
02233     if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
02234     {
02235       /* Perform an abort of the OctoSPI */
02236       SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
02237
02238       /* Wait until the transfer complete flag is set to go back in idle state */
02239       status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout);
02240
02241       if (status == HAL_OK)
02242       {
02243         /* Clear transfer complete flag */
02244         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
02245
02246         /* Wait until the busy flag is reset to go back in idle state */
02247         status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
02248
02249         if (status == HAL_OK)
02250         {
02251           /* Update state */
02252           hospi->State = HAL_OSPI_STATE_READY;
02253         }
02254       }
02255     }
02256     else
02257     {
02258       /* Update state */
02259       hospi->State = HAL_OSPI_STATE_READY;
02260     }
02261   }
02262   else
02263   {
02264     status = HAL_ERROR;
02265     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
02266   }
02267
02268   /* Return function status */
02269   return status;
02270 }
02271
02272 /**
02273 * @brief  Abort the current transmission (non-blocking function)
02274 * @param  hospi : OSPI handle
02275 * @retval HAL status
02276 */
02277 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
02278 {
02279   HAL_StatusTypeDef status = HAL_OK;
02280   uint32_t state;
02281
02282   /* Check if the state is in one of the busy or configured states */
02283   state = hospi->State;
02284   if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
02285   {
02286     /* Disable all interrupts */
02287     __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
02288
02289     /* Update state */
02290     hospi->State = HAL_OSPI_STATE_ABORT;
02291
02292     /* Check if the DMA is enabled */
02293     if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
02294     {
02295       /* Disable the DMA transfer on the OctoSPI side */
02296       CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
02297
02298       /* Disable the DMA transfer on the DMA side */
02299       hospi->hmdma->XferAbortCallback = OSPI_DMAAbortCplt;
02300       if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
02301       {
02302         /* Update state */
02303         hospi->State = HAL_OSPI_STATE_READY;
02304
02305         /* Abort callback */
02306 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
02307         hospi->AbortCpltCallback(hospi);
02308 #else
02309         HAL_OSPI_AbortCpltCallback(hospi);
02310 #endif
02311       }
02312     }
02313     else
02314     {
02315       if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
02316       {
02317         /* Clear transfer complete flag */
02318         __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
02319
02320         /* Enable the transfer complete interrupts */
02321         __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
02322
02323         /* Perform an abort of the OctoSPI */
02324         SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
02325       }
02326       else
02327       {
02328         /* Update state */
02329         hospi->State = HAL_OSPI_STATE_READY;
02330
02331         /* Abort callback */
02332 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
02333         hospi->AbortCpltCallback(hospi);
02334 #else
02335         HAL_OSPI_AbortCpltCallback(hospi);
02336 #endif
02337       }
02338     }
02339   }
02340   else
02341   {
02342     status = HAL_ERROR;
02343     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
02344   }
02345
02346   /* Return function status */
02347   return status;
02348 }
02349
02350 /** @brief  Set OSPI Fifo threshold.
02351   * @param  hospi     : OSPI handle.
02352   * @param  Threshold : Threshold of the Fifo.
02353   * @retval HAL status
02354   */
02355 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold)
02356 {
02357   HAL_StatusTypeDef status = HAL_OK;
02358
02359   /* Check the state */
02360   if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U)
02361   {
02362     /* Synchronize initialization structure with the new fifo threshold value */
02363     hospi->Init.FifoThreshold = Threshold;
02364
02365     /* Configure new fifo threshold */
02366     MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos));
02367
02368   }
02369   else
02370   {
02371     status = HAL_ERROR;
02372     hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
02373   }
02374
02375   /* Return function status */
02376   return status;
02377 }
02378
02379 /** @brief  Get OSPI Fifo threshold.
02380   * @param  hospi : OSPI handle.
02381   * @retval Fifo threshold
02382   */
02383 uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
02384 {
02385   return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
02386 }
02387
02388 /** @brief Set OSPI timeout.
02389   * @param  hospi   : OSPI handle.
02390   * @param  Timeout : Timeout for the memory access.
02391   * @retval None
02392   */
02393 HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout)
02394 {
02395   hospi->Timeout = Timeout;
02396   return HAL_OK;
02397 }
02398
02399 /**
02400 * @brief  Return the OSPI error code.
02401 * @param  hospi : OSPI handle
02402 * @retval OSPI Error Code
02403 */
02404 uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
02405 {
02406   return hospi->ErrorCode;
02407 }
02408
02409 /**
02410   * @brief  Return the OSPI handle state.
02411   * @param  hospi : OSPI handle
02412   * @retval HAL state
02413   */
02414 uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
02415 {
02416   /* Return OSPI handle state */
02417   return hospi->State;
02418 }
02419
02420 /**
02421   * @}
02422   */
02423
02424 /** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function
02425   *  @brief   OSPI IO Manager configuration function
02426   *
02427 @verbatim
02428  ===============================================================================
02429                   ##### IO Manager configuration function #####
02430  ===============================================================================
02431     [..]
02432     This subsection provides a set of functions allowing to :
02433       (+) Configure the IO manager.
02434
02435 @endverbatim
02436   * @{
02437   */
02438
02439 /**
02440   * @brief  Configure the OctoSPI IO manager.
02441   * @param  hospi   : OSPI handle
02442   * @param  cfg     : Configuration of the IO Manager for the instance
02443   * @param  Timeout : Timeout duration
02444   * @retval HAL status
02445   */
02446 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
02447 {
02448   HAL_StatusTypeDef status = HAL_OK;
02449   uint32_t instance;
02450   uint8_t index, ospi_enabled = 0U, other_instance;
02451   OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
02452
02453   /* Prevent unused argument(s) compilation warning */
02454   UNUSED(Timeout);
02455
02456   /* Check the parameters of the OctoSPI IO Manager configuration structure */
02457   assert_param(IS_OSPIM_PORT(cfg->ClkPort));
02458   assert_param(IS_OSPIM_PORT(cfg->DQSPort));
02459   assert_param(IS_OSPIM_PORT(cfg->NCSPort));
02460   assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
02461   assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
02462
02463   if (hospi->Instance == OCTOSPI1)
02464   {
02465     instance = 0U;
02466     other_instance = 1U;
02467   }
02468   else
02469   {
02470     instance = 1U;
02471     other_instance = 0U;
02472   }
02473
02474   /**************** Get current configuration of the instances ****************/
02475   for (index = 0U; index < OSPI_NB_INSTANCE; index++)
02476   {
02477     if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK)
02478     {
02479       status = HAL_ERROR;
02480       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
02481     }
02482   }
02483
02484   if (status == HAL_OK)
02485   {
02486     /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/
02487     if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U)
02488     {
02489       CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
02490       ospi_enabled |= 0x1U;
02491     }
02492     if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U)
02493     {
02494       CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
02495       ospi_enabled |= 0x2U;
02496     }
02497
02498     /***************** Deactivation of previous configuration *****************/
02499     if (IOM_cfg[instance].ClkPort != 0U)
02500     {
02501       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)],                          OCTOSPIM_PCR_CLKEN);
02502       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)],                          OCTOSPIM_PCR_DQSEN);
02503       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)],                          OCTOSPIM_PCR_NCSEN);
02504       CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],  OCTOSPIM_PCR_IOLEN);
02505       CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
02506     }
02507
02508     /********************* Deactivation of other instance *********************/
02509     if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort)     ||
02510         (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
02511         (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
02512     {
02513       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)],                          OCTOSPIM_PCR_CLKEN);
02514       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)],                          OCTOSPIM_PCR_DQSEN);
02515       CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)],                          OCTOSPIM_PCR_NCSEN);
02516       CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],  OCTOSPIM_PCR_IOLEN);
02517       CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
02518     }
02519
02520     /******************** Activation of new configuration *********************/
02521     MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
02522     MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
02523     MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
02524
02525     if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
02526     {
02527       MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
02528                  (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
02529     }
02530     else
02531     {
02532       MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
02533                  (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
02534     }
02535
02536     if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
02537     {
02538       MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
02539                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
02540     }
02541     else
02542     {
02543       MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
02544                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
02545     }
02546
02547     /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
02548     if ((ospi_enabled & 0x1U) != 0U)
02549     {
02550       SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
02551     }
02552     if ((ospi_enabled & 0x2U) != 0U)
02553     {
02554       SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
02555     }
02556   }
02557
02558   /* Return function status */
02559   return status;
02560 }
02561
02562 /**
02563   * @}
02564   */
02565
02566 /**
02567   @cond 0
02568   */
02569 /**
02570   * @brief  DMA OSPI process complete callback.
02571   * @param  hdma : DMA handle
02572   * @retval None
02573   */
02574 static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma)
02575 {
02576   OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
02577   hospi->XferCount = 0;
02578
02579   /* Disable the DMA transfer on the OctoSPI side */
02580   CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
02581
02582   /* Disable the DMA channel */
02583   __HAL_MDMA_DISABLE(hmdma);
02584
02585   /* Enable the OSPI transfer complete Interrupt */
02586   __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
02587 }
02588
02589 /**
02590   * @brief  DMA OSPI communication error callback.
02591   * @param  hdma : DMA handle
02592   * @retval None
02593   */
02594 static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma)
02595 {
02596   OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
02597   hospi->XferCount = 0;
02598   hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
02599
02600   /* Disable the DMA transfer on the OctoSPI side */
02601   CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
02602
02603   /* Abort the OctoSPI */
02604   if (HAL_OSPI_Abort_IT(hospi) != HAL_OK)
02605   {
02606     /* Disable the interrupts */
02607     __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
02608
02609     /* Update state */
02610     hospi->State = HAL_OSPI_STATE_READY;
02611
02612     /* Error callback */
02613 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
02614     hospi->ErrorCallback(hospi);
02615 #else
02616     HAL_OSPI_ErrorCallback(hospi);
02617 #endif
02618   }
02619 }
02620
02621 /**
02622   * @brief  DMA OSPI abort complete callback.
02623   * @param  hdma : DMA handle
02624   * @retval None
02625   */
02626 static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
02627 {
02628   OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
02629   hospi->XferCount = 0;
02630
02631   /* Check the state */
02632   if (hospi->State == HAL_OSPI_STATE_ABORT)
02633   {
02634     /* DMA abort called by OctoSPI abort */
02635     if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
02636     {
02637       /* Clear transfer complete flag */
02638       __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
02639
02640       /* Enable the transfer complete interrupts */
02641       __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
02642
02643       /* Perform an abort of the OctoSPI */
02644       SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
02645     }
02646     else
02647     {
02648       /* Update state */
02649       hospi->State = HAL_OSPI_STATE_READY;
02650
02651       /* Abort callback */
02652 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
02653       hospi->AbortCpltCallback(hospi);
02654 #else
02655       HAL_OSPI_AbortCpltCallback(hospi);
02656 #endif
02657     }
02658   }
02659   else
02660   {
02661     /* DMA abort called due to a transfer error interrupt */
02662     /* Update state */
02663     hospi->State = HAL_OSPI_STATE_READY;
02664
02665     /* Error callback */
02666 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
02667     hospi->ErrorCallback(hospi);
02668 #else
02669     HAL_OSPI_ErrorCallback(hospi);
02670 #endif
02671   }
02672 }
02673
02674 /**
02675   * @brief  Wait for a flag state until timeout.
02676   * @param  hospi     : OSPI handle
02677   * @param  Flag      : Flag checked
02678   * @param  State     : Value of the flag expected
02679   * @param  Timeout   : Duration of the timeout
02680   * @param  Tickstart : Tick start value
02681   * @retval HAL status
02682   */
02683 static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag,
02684                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
02685 {
02686   /* Wait until flag is in expected state */
02687   while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
02688   {
02689     /* Check for the Timeout */
02690     if (Timeout != HAL_MAX_DELAY)
02691     {
02692       if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02693       {
02694         hospi->State     = HAL_OSPI_STATE_ERROR;
02695         hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
02696
02697         return HAL_ERROR;
02698       }
02699     }
02700   }
02701   return HAL_OK;
02702 }
02703
02704 /**
02705   * @brief  Configure the registers for the regular command mode.
02706   * @param  hospi : OSPI handle
02707   * @param  cmd   : structure that contains the command configuration information
02708   * @retval HAL status
02709   */
02710 static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
02711 {
02712   HAL_StatusTypeDef status = HAL_OK;
02713   __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg;
02714
02715   /* Re-initialize the value of the functional mode */
02716   MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
02717
02718   /* Configure the flash ID */
02719   if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
02720   {
02721     MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId);
02722   }
02723
02724   if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
02725   {
02726     ccr_reg = &(hospi->Instance->WCCR);
02727     tcr_reg = &(hospi->Instance->WTCR);
02728     ir_reg  = &(hospi->Instance->WIR);
02729     abr_reg = &(hospi->Instance->WABR);
02730   }
02731   else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)
02732   {
02733     ccr_reg = &(hospi->Instance->WPCCR);
02734     tcr_reg = &(hospi->Instance->WPTCR);
02735     ir_reg  = &(hospi->Instance->WPIR);
02736     abr_reg = &(hospi->Instance->WPABR);
02737   }
02738   else
02739   {
02740     ccr_reg = &(hospi->Instance->CCR);
02741     tcr_reg = &(hospi->Instance->TCR);
02742     ir_reg  = &(hospi->Instance->IR);
02743     abr_reg = &(hospi->Instance->ABR);
02744   }
02745
02746   /* Configure the CCR register with DQS and SIOO modes */
02747   *ccr_reg = (cmd->DQSMode | cmd->SIOOMode);
02748
02749   if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
02750   {
02751     /* Configure the ABR register with alternate bytes value */
02752     *abr_reg = cmd->AlternateBytes;
02753
02754     /* Configure the CCR register with alternate bytes communication parameters */
02755     MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
02756                            (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
02757   }
02758
02759   /* Configure the TCR register with the number of dummy cycles */
02760   MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles);
02761
02762   if (cmd->DataMode != HAL_OSPI_DATA_NONE)
02763   {
02764     if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
02765     {
02766       /* Configure the DLR register with the number of data */
02767       hospi->Instance->DLR = (cmd->NbData - 1U);
02768     }
02769   }
02770
02771   if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
02772   {
02773     if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
02774     {
02775       if (cmd->DataMode != HAL_OSPI_DATA_NONE)
02776       {
02777         /* ---- Command with instruction, address and data ---- */
02778
02779         /* Configure the CCR register with all communication parameters */
02780         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
02781                                 OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
02782                                 OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
02783                                (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
02784                                 cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize     |
02785                                 cmd->DataMode        | cmd->DataDtrMode));
02786       }
02787       else
02788       {
02789         /* ---- Command with instruction and address ---- */
02790
02791         /* Configure the CCR register with all communication parameters */
02792         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
02793                                 OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
02794                                (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
02795                                 cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize));
02796
02797         /* The DHQC bit is linked with DDTR bit which should be activated */
02798         if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
02799             (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
02800         {
02801           MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
02802         }
02803       }
02804
02805       /* Configure the IR register with the instruction value */
02806       *ir_reg = cmd->Instruction;
02807
02808       /* Configure the AR register with the address value */
02809       hospi->Instance->AR = cmd->Address;
02810     }
02811     else
02812     {
02813       if (cmd->DataMode != HAL_OSPI_DATA_NONE)
02814       {
02815         /* ---- Command with instruction and data ---- */
02816
02817         /* Configure the CCR register with all communication parameters */
02818         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
02819                                 OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
02820                                (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
02821                                 cmd->DataMode        | cmd->DataDtrMode));
02822       }
02823       else
02824       {
02825         /* ---- Command with only instruction ---- */
02826
02827         /* Configure the CCR register with all communication parameters */
02828         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
02829                                (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
02830
02831         /* The DHQC bit is linked with DDTR bit which should be activated */
02832         if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
02833             (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
02834         {
02835           MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
02836         }
02837       }
02838
02839       /* Configure the IR register with the instruction value */
02840       *ir_reg = cmd->Instruction;
02841
02842     }
02843   }
02844   else
02845   {
02846     if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
02847     {
02848       if (cmd->DataMode != HAL_OSPI_DATA_NONE)
02849       {
02850         /* ---- Command with address and data ---- */
02851
02852         /* Configure the CCR register with all communication parameters */
02853         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
02854                                 OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
02855                                (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize     |
02856                                 cmd->DataMode    | cmd->DataDtrMode));
02857       }
02858       else
02859       {
02860         /* ---- Command with only address ---- */
02861
02862         /* Configure the CCR register with all communication parameters */
02863         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
02864                                (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
02865       }
02866
02867       /* Configure the AR register with the instruction value */
02868       hospi->Instance->AR = cmd->Address;
02869     }
02870     else
02871     {
02872       /* ---- Invalid command configuration (no instruction, no address) ---- */
02873       status = HAL_ERROR;
02874       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
02875     }
02876   }
02877
02878   /* Return function status */
02879   return status;
02880 }
02881
02882 /**
02883   * @brief  Get the current IOM configuration for an OctoSPI instance.
02884   * @param  instance_nb : number of the instance
02885   * @param  cfg         : configuration of the IO Manager for the instance
02886   * @retval HAL status
02887   */
02888 static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
02889 {
02890   HAL_StatusTypeDef status = HAL_OK;
02891   uint32_t reg, value = 0U;
02892   uint32_t index;
02893
02894   if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
02895   {
02896     /* Invalid parameter -> error returned */
02897     status = HAL_ERROR;
02898   }
02899   else
02900   {
02901     /* Initialize the structure */
02902     cfg->ClkPort    = 0U;
02903     cfg->DQSPort    = 0U;
02904     cfg->NCSPort    = 0U;
02905     cfg->IOLowPort  = 0U;
02906     cfg->IOHighPort = 0U;
02907
02908     if (instance_nb == 2U)
02909     {
02910       value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
02911     }
02912
02913     /* Get the information about the instance */
02914     for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++)
02915     {
02916       reg = OCTOSPIM->PCR[index];
02917
02918       if ((reg & OCTOSPIM_PCR_CLKEN) != 0U)
02919       {
02920         /* The clock is enabled on this port */
02921         if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
02922         {
02923           /* The clock correspond to the instance passed as parameter */
02924           cfg->ClkPort = index+1U;
02925         }
02926       }
02927
02928       if ((reg & OCTOSPIM_PCR_DQSEN) != 0U)
02929       {
02930         /* The DQS is enabled on this port */
02931         if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
02932         {
02933           /* The DQS correspond to the instance passed as parameter */
02934           cfg->DQSPort = index+1U;
02935         }
02936       }
02937
02938       if ((reg & OCTOSPIM_PCR_NCSEN) != 0U)
02939       {
02940         /* The nCS is enabled on this port */
02941         if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
02942         {
02943           /* The nCS correspond to the instance passed as parameter */
02944           cfg->NCSPort = index+1U;
02945         }
02946       }
02947
02948       if ((reg & OCTOSPIM_PCR_IOLEN) != 0U)
02949       {
02950         /* The IO Low is enabled on this port */
02951         if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1))
02952         {
02953           /* The IO Low correspond to the instance passed as parameter */
02954           if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
02955           {
02956             cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
02957           }
02958           else
02959           {
02960             cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
02961           }
02962         }
02963       }
02964
02965       if ((reg & OCTOSPIM_PCR_IOHEN) != 0U)
02966       {
02967         /* The IO High is enabled on this port */
02968         if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1))
02969         {
02970           /* The IO High correspond to the instance passed as parameter */
02971           if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
02972           {
02973             cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
02974           }
02975           else
02976           {
02977             cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
02978           }
02979         }
02980       }
02981     }
02982   }
02983
02984   /* Return function status */
02985   return status;
02986 }
02987
02988 /**
02989   @endcond
02990   */
02991
02992 /**
02993   * @}
02994   */
02995
02996 #endif /* HAL_OSPI_MODULE_ENABLED */
02997
02998 /**
02999   * @}
03000   */
03001
03002 /**
03003   * @}
03004   */
03005
03006 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
03007
03008 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ospi.h Source File

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stm32h7xx_hal_ospi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ospi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OSPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_OSPI_H
00022 #define STM32H7xx_HAL_OSPI_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup OSPI
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup OSPI_Exported_Types OSPI Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief OSPI Init structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t FifoThreshold;             /* This is the threshold used by the Peripheral to generate the interrupt
00052                                          indicating that data are available in reception or free place
00053                                          is available in transmission.
00054                                          This parameter can be a value between 1 and 32 */
00055   uint32_t DualQuad;                  /* It enables or not the dual-quad mode which allow to access up to
00056                                          quad mode on two different devices to increase the throughput.
00057                                          This parameter can be a value of @ref OSPI_DualQuad */
00058   uint32_t MemoryType;                /* It indicates the external device type connected to the OSPI.
00059                                          This parameter can be a value of @ref OSPI_MemoryType */
00060   uint32_t DeviceSize;                /* It defines the size of the external device connected to the OSPI,
00061                                          it corresponds to the number of address bits required to access
00062                                          the external device.
00063                                          This parameter can be a value between 1 and 32 */
00064   uint32_t ChipSelectHighTime;        /* It defines the minimun number of clocks which the chip select
00065                                          must remain high between commands.
00066                                          This parameter can be a value between 1 and 8 */
00067   uint32_t FreeRunningClock;          /* It enables or not the free running clock.
00068                                          This parameter can be a value of @ref OSPI_FreeRunningClock */
00069   uint32_t ClockMode;                 /* It indicates the level of clock when the chip select is released.
00070                                          This parameter can be a value of @ref OSPI_ClockMode */
00071   uint32_t WrapSize;                  /* It indicates the wrap-size corresponding the external device configuration.
00072                                          This parameter can be a value of @ref OSPI_WrapSize */
00073   uint32_t ClockPrescaler;            /* It specifies the prescaler factor used for generating
00074                                          the external clock based on the AHB clock.
00075                                          This parameter can be a value between 1 and 256 */
00076   uint32_t SampleShifting;            /* It allows to delay to 1/2 cycle the data sampling in order
00077                                          to take in account external signal delays.
00078                                          This parameter can be a value of @ref OSPI_SampleShifting */
00079   uint32_t DelayHoldQuarterCycle;     /* It allows to hold to 1/4 cycle the data.
00080                                          This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
00081   uint32_t ChipSelectBoundary;        /* It enables the transaction boundary feature and
00082                                          defines the boundary of bytes to release the chip select.
00083                                          This parameter can be a value between 0 and 31 */
00084   uint32_t ClkChipSelectHighTime;     /* It defines the number of clocks provided on the CLK/nCLK pins when
00085                                          the chip select is set to high at the end of a transaction.
00086                                          This parameter can be a value between 0 and 7 */
00087   uint32_t DelayBlockBypass;          /* It enables the delay block bypass, so the sampling is not affected
00088                                          by the delay block.
00089                                          This parameter can be a value of @ref OSPI_DelayBlockBypass */
00090   uint32_t MaxTran;                   /* It enables the communication regulation feature. The chip select is
00091                                          released every MaxTran+1 bytes when the other OctoSPI request the access
00092                                          to the bus.
00093                                          This parameter can be a value between 0 and 255 */
00094   uint32_t Refresh;                   /* It enables the refresh rate feature. The chip select is released every
00095                                          Refresh+1 clock cycles.
00096                                          This parameter can be a value between 0 and 0xFFFFFFFF */
00097 }OSPI_InitTypeDef;
00098
00099 /**
00100   * @brief  HAL OSPI Handle Structure definition
00101   */
00102 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00103 typedef struct __OSPI_HandleTypeDef
00104 #else
00105 typedef struct
00106 #endif
00107 {
00108   OCTOSPI_TypeDef            *Instance;     /* OSPI registers base address                      */
00109   OSPI_InitTypeDef           Init;          /* OSPI initialization parameters                   */
00110   uint8_t                    *pBuffPtr;     /* Address of the OSPI buffer for transfer          */
00111   __IO uint32_t              XferSize;      /* Number of data to transfer                       */
00112   __IO uint32_t              XferCount;     /* Counter of data transferred                      */
00113   MDMA_HandleTypeDef     *hmdma;    /* Handle of the MDMA channel used for the transfer  */
00114   __IO uint32_t              State;         /* Internal state of the OSPI HAL driver            */
00115   __IO uint32_t              ErrorCode;     /* Error code in case of HAL driver internal error  */
00116   uint32_t                   Timeout;       /* Timeout used for the OSPI external device access */
00117 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00118   void (* ErrorCallback)        (struct __OSPI_HandleTypeDef *hospi);
00119   void (* AbortCpltCallback)    (struct __OSPI_HandleTypeDef *hospi);
00120   void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
00121   void (* CmdCpltCallback)      (struct __OSPI_HandleTypeDef *hospi);
00122   void (* RxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
00123   void (* TxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
00124   void (* RxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
00125   void (* TxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
00126   void (* StatusMatchCallback)  (struct __OSPI_HandleTypeDef *hospi);
00127   void (* TimeOutCallback)      (struct __OSPI_HandleTypeDef *hospi);
00128
00129   void (* MspInitCallback)      (struct __OSPI_HandleTypeDef *hospi);
00130   void (* MspDeInitCallback)    (struct __OSPI_HandleTypeDef *hospi);
00131 #endif
00132 }OSPI_HandleTypeDef;
00133
00134 /**
00135   * @brief  HAL OSPI Regular Command Structure definition
00136   */
00137 typedef struct
00138 {
00139   uint32_t OperationType;             /* It indicates if the configuration applies to the common regsiters or
00140                                          to the registers for the write operation (these registers are only
00141                                          used for memory-mapped mode).
00142                                          This parameter can be a value of @ref OSPI_OperationType */
00143   uint32_t FlashId;                   /* It indicates which external device is selected for this command (it
00144                                          applies only if Dualquad is disabled in the initialization structure).
00145                                          This parameter can be a value of @ref OSPI_FlashId */
00146   uint32_t Instruction;               /* It contains the instruction to be sent to the device.
00147                                          This parameter can be a value between 0 and 0xFFFFFFFF */
00148   uint32_t InstructionMode;           /* It indicates the mode of the instruction.
00149                                          This parameter can be a value of @ref OSPI_InstructionMode */
00150   uint32_t InstructionSize;           /* It indicates the size of the instruction.
00151                                          This parameter can be a value of @ref OSPI_InstructionSize */
00152   uint32_t InstructionDtrMode;        /* It enables or not the DTR mode for the instruction phase.
00153                                          This parameter can be a value of @ref OSPI_InstructionDtrMode */
00154   uint32_t Address;                   /* It contains the address to be sent to the device.
00155                                          This parameter can be a value between 0 and 0xFFFFFFFF */
00156   uint32_t AddressMode;               /* It indicates the mode of the address.
00157                                          This parameter can be a value of @ref OSPI_AddressMode */
00158   uint32_t AddressSize;               /* It indicates the size of the address.
00159                                          This parameter can be a value of @ref OSPI_AddressSize */
00160   uint32_t AddressDtrMode;            /* It enables or not the DTR mode for the address phase.
00161                                          This parameter can be a value of @ref OSPI_AddressDtrMode */
00162   uint32_t AlternateBytes;            /* It contains the alternate bytes to be sent to the device.
00163                                          This parameter can be a value between 0 and 0xFFFFFFFF */
00164   uint32_t AlternateBytesMode;        /* It indicates the mode of the alternate bytes.
00165                                          This parameter can be a value of @ref OSPI_AlternateBytesMode */
00166   uint32_t AlternateBytesSize;        /* It indicates the size of the alternate bytes.
00167                                          This parameter can be a value of @ref OSPI_AlternateBytesSize */
00168   uint32_t AlternateBytesDtrMode;     /* It enables or not the DTR mode for the alternate bytes phase.
00169                                          This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
00170   uint32_t DataMode;                  /* It indicates the mode of the data.
00171                                          This parameter can be a value of @ref OSPI_DataMode */
00172   uint32_t NbData;                    /* It indicates the number of data transferred with this command.
00173                                          This field is only used for indirect mode.
00174                                          This parameter can be a value between 1 and 0xFFFFFFFF */
00175   uint32_t DataDtrMode;               /* It enables or not the DTR mode for the data phase.
00176                                          This parameter can be a value of @ref OSPI_DataDtrMode */
00177   uint32_t DummyCycles;               /* It indicates the number of dummy cycles inserted before data phase.
00178                                          This parameter can be a value between 0 and 31 */
00179   uint32_t DQSMode;                   /* It enables or not the data strobe management.
00180                                          This parameter can be a value of @ref OSPI_DQSMode */
00181   uint32_t SIOOMode;                  /* It enables or not the SIOO mode.
00182                                          This parameter can be a value of @ref OSPI_SIOOMode */
00183 }OSPI_RegularCmdTypeDef;
00184
00185 /**
00186   * @brief  HAL OSPI Hyperbus Configuration Structure definition
00187   */
00188 typedef struct
00189 {
00190   uint32_t RWRecoveryTime;       /* It indicates the number of cycles for the device read write recovery time.
00191                                     This parameter can be a value between 0 and 255 */
00192   uint32_t AccessTime;           /* It indicates the number of cycles for the device acces time.
00193                                     This parameter can be a value between 0 and 255 */
00194   uint32_t WriteZeroLatency;     /* It enables or not the latency for the write access.
00195                                     This parameter can be a value of @ref OSPI_WriteZeroLatency */
00196   uint32_t LatencyMode;          /* It configures the latency mode.
00197                                     This parameter can be a value of @ref OSPI_LatencyMode */
00198 }OSPI_HyperbusCfgTypeDef;
00199
00200 /**
00201   * @brief  HAL OSPI Hyperbus Command Structure definition
00202   */
00203 typedef struct
00204 {
00205   uint32_t AddressSpace;     /* It indicates the address space accessed by the command.
00206                                 This parameter can be a value of @ref OSPI_AddressSpace */
00207   uint32_t Address;          /* It contains the address to be sent tot he device.
00208                                 This parameter can be a value between 0 and 0xFFFFFFFF */
00209   uint32_t AddressSize;      /* It indicates the size of the address.
00210                                 This parameter can be a value of @ref OSPI_AddressSize */
00211   uint32_t NbData;           /* It indicates the number of data transferred with this command.
00212                                 This field is only used for indirect mode.
00213                                 This parameter can be a value between 1 and 0xFFFFFFFF
00214                                 In case of autopolling mode, this parameter can be any value between 1 and 4 */
00215   uint32_t DQSMode;          /* It enables or not the data strobe management.
00216                                 This parameter can be a value of @ref OSPI_DQSMode */
00217 }OSPI_HyperbusCmdTypeDef;
00218
00219 /**
00220   * @brief  HAL OSPI Auto Polling mode configuration structure definition
00221   */
00222 typedef struct
00223 {
00224   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00225                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00226   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00227                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00228   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00229                                   This parameter can be a value of @ref OSPI_MatchMode */
00230   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00231                                   This parameter can be a value of @ref OSPI_AutomaticStop */
00232   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00233                                   This parameter can be any value between 0 and 0xFFFF */
00234 }OSPI_AutoPollingTypeDef;
00235
00236 /**
00237   * @brief  HAL OSPI Memory Mapped mode configuration structure definition
00238   */
00239 typedef struct
00240 {
00241   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
00242                                   This parameter can be a value of @ref OSPI_TimeOutActivation */
00243   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00244                                   This parameter can be any value between 0 and 0xFFFF */
00245 }OSPI_MemoryMappedTypeDef;
00246
00247 /**
00248   * @brief HAL OSPI IO Manager Configuration structure definition
00249   */
00250 typedef struct
00251 {
00252   uint32_t ClkPort;                /* It indicates which port of the OSPI IO Manager is used for the CLK pins.
00253                                       This parameter can be a value between 1 and 8 */
00254   uint32_t DQSPort;                /* It indicates which port of the OSPI IO Manager is used for the DQS pin.
00255                                       This parameter can be a value between 1 and 8 */
00256   uint32_t NCSPort;                /* It indicates which port of the OSPI IO Manager is used for the NCS pin.
00257                                       This parameter can be a value between 1 and 8 */
00258   uint32_t IOLowPort;              /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
00259                                       This parameter can be a value of @ref OSPIM_IOPort */
00260   uint32_t IOHighPort;             /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
00261                                       This parameter can be a value of @ref OSPIM_IOPort */
00262 }OSPIM_CfgTypeDef;
00263
00264 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00265 /**
00266   * @brief  HAL OSPI Callback ID enumeration definition
00267   */
00268 typedef enum
00269 {
00270   HAL_OSPI_ERROR_CB_ID          = 0x00U,  /*!< OSPI Error Callback ID            */
00271   HAL_OSPI_ABORT_CB_ID          = 0x01U,  /*!< OSPI Abort Callback ID            */
00272   HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< OSPI FIFO Threshold Callback ID   */
00273   HAL_OSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< OSPI Command Complete Callback ID */
00274   HAL_OSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< OSPI Rx Complete Callback ID      */
00275   HAL_OSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< OSPI Tx Complete Callback ID      */
00276   HAL_OSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< OSPI Rx Half Complete Callback ID */
00277   HAL_OSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< OSPI Tx Half Complete Callback ID */
00278   HAL_OSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< OSPI Status Match Callback ID     */
00279   HAL_OSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< OSPI Timeout Callback ID          */
00280
00281   HAL_OSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< OSPI MspInit Callback ID          */
00282   HAL_OSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< OSPI MspDeInit Callback ID        */
00283 }HAL_OSPI_CallbackIDTypeDef;
00284
00285 /**
00286   * @brief  HAL OSPI Callback pointer definition
00287   */
00288 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
00289 #endif
00290 /**
00291   * @}
00292   */
00293
00294 /* Exported constants --------------------------------------------------------*/
00295 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants
00296   * @{
00297   */
00298
00299 /** @defgroup OSPI_State OSPI State
00300   * @{
00301   */
00302 #define HAL_OSPI_STATE_RESET                 ((uint32_t)0x00000000U)      /*!< Initial state                                                          */
00303 #define HAL_OSPI_STATE_HYPERBUS_INIT         ((uint32_t)0x00000001U)      /*!< Initialization done in hyperbus mode but timing configuration not done */
00304 #define HAL_OSPI_STATE_READY                 ((uint32_t)0x00000002U)      /*!< Driver ready to be used                                                */
00305 #define HAL_OSPI_STATE_CMD_CFG               ((uint32_t)0x00000004U)      /*!< Command (regular or hyperbus) configured, ready for an action          */
00306 #define HAL_OSPI_STATE_READ_CMD_CFG          ((uint32_t)0x00000014U)      /*!< Read command configuration done, not the write command configuration   */
00307 #define HAL_OSPI_STATE_WRITE_CMD_CFG         ((uint32_t)0x00000024U)      /*!< Write command configuration done, not the read command configuration   */
00308 #define HAL_OSPI_STATE_BUSY_CMD              ((uint32_t)0x00000008U)      /*!< Command without data on-going                                          */
00309 #define HAL_OSPI_STATE_BUSY_TX               ((uint32_t)0x00000018U)      /*!< Indirect Tx on-going                                                   */
00310 #define HAL_OSPI_STATE_BUSY_RX               ((uint32_t)0x00000028U)      /*!< Indirect Rx on-going                                                   */
00311 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING     ((uint32_t)0x00000048U)      /*!< Auto-polling on-going                                                  */
00312 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED       ((uint32_t)0x00000088U)      /*!< Memory-mapped on-going                                                 */
00313 #define HAL_OSPI_STATE_ABORT                 ((uint32_t)0x00000100U)      /*!< Abort on-going                                                         */
00314 #define HAL_OSPI_STATE_ERROR                 ((uint32_t)0x00000200U)      /*!< Blocking error, driver should be re-initialized                        */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup OSPI_ErrorCode OSPI Error Code
00320   * @{
00321   */
00322 #define HAL_OSPI_ERROR_NONE                  ((uint32_t)0x00000000U)                                         /*!< No error                                   */
00323 #define HAL_OSPI_ERROR_TIMEOUT               ((uint32_t)0x00000001U)                                         /*!< Timeout error                              */
00324 #define HAL_OSPI_ERROR_TRANSFER              ((uint32_t)0x00000002U)                                         /*!< Transfer error                             */
00325 #define HAL_OSPI_ERROR_DMA                   ((uint32_t)0x00000004U)                                         /*!< DMA transfer error                         */
00326 #define HAL_OSPI_ERROR_INVALID_PARAM         ((uint32_t)0x00000008U)                                         /*!< Invalid parameters error                   */
00327 #define HAL_OSPI_ERROR_INVALID_SEQUENCE      ((uint32_t)0x00000010U)                                         /*!< Sequence of the state machine is incorrect */
00328 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00329 #define HAL_OSPI_ERROR_INVALID_CALLBACK      ((uint32_t)0x00000020U)                                         /*!< Invalid callback error                     */
00330 #endif
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup OSPI_DualQuad OSPI Dual-Quad
00336   * @{
00337   */
00338 #define HAL_OSPI_DUALQUAD_DISABLE            ((uint32_t)0x00000000U)                                         /*!< Dual-Quad mode disabled */
00339 #define HAL_OSPI_DUALQUAD_ENABLE             ((uint32_t)OCTOSPI_CR_DQM)                                      /*!< Dual-Quad mode enabled  */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup OSPI_MemoryType OSPI Memory Type
00345   * @{
00346   */
00347 #define HAL_OSPI_MEMTYPE_MICRON              ((uint32_t)0x00000000U)                                         /*!< Micron mode       */
00348 #define HAL_OSPI_MEMTYPE_MACRONIX            ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< Macronix mode     */
00349 #define HAL_OSPI_MEMTYPE_APMEMORY            ((uint32_t)OCTOSPI_DCR1_MTYP_1)                                 /*!< AP Memory mode    */
00350 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM        ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))         /*!< Macronix RAM mode */
00351 #define HAL_OSPI_MEMTYPE_HYPERBUS            ((uint32_t)OCTOSPI_DCR1_MTYP_2)                                 /*!< Hyperbus mode     */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock
00357   * @{
00358   */
00359 #define HAL_OSPI_FREERUNCLK_DISABLE          ((uint32_t)0x00000000U)                                         /*!< CLK is not free running               */
00360 #define HAL_OSPI_FREERUNCLK_ENABLE           ((uint32_t)OCTOSPI_DCR1_FRCK)                                   /*!< CLK is free running (always provided) */
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup OSPI_ClockMode OSPI Clock Mode
00366   * @{
00367   */
00368 #define HAL_OSPI_CLOCK_MODE_0                ((uint32_t)0x00000000U)                                         /*!< CLK must stay low while nCS is high  */
00369 #define HAL_OSPI_CLOCK_MODE_3                ((uint32_t)OCTOSPI_DCR1_CKMODE)                                 /*!< CLK must stay high while nCS is high */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup OSPI_WrapSize OSPI Wrap-Size
00375   * @{
00376   */
00377 #define HAL_OSPI_WRAP_NOT_SUPPORTED          ((uint32_t)0x00000000U)                                         /*!< wrapped reads are not supported by the memory   */
00378 #define HAL_OSPI_WRAP_16_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)                             /*!< external memory supports wrap size of 16 bytes  */
00379 #define HAL_OSPI_WRAP_32_BYTES               ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes  */
00380 #define HAL_OSPI_WRAP_64_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)                             /*!< external memory supports wrap size of 64 bytes  */
00381 #define HAL_OSPI_WRAP_128_BYTES              ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting
00387   * @{
00388   */
00389 #define HAL_OSPI_SAMPLE_SHIFTING_NONE        ((uint32_t)0x00000000U)                                         /*!< No shift        */
00390 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE   ((uint32_t)OCTOSPI_TCR_SSHIFT)                                  /*!< 1/2 cycle shift */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle
00396   * @{
00397   */
00398 #define HAL_OSPI_DHQC_DISABLE                ((uint32_t)0x00000000U)                                         /*!< No Delay             */
00399 #define HAL_OSPI_DHQC_ENABLE                 ((uint32_t)OCTOSPI_TCR_DHQC)                                    /*!< Delay Hold 1/4 cycle */
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas
00405   * @{
00406   */
00407 #define HAL_OSPI_DELAY_BLOCK_USED            ((uint32_t)0x00000000U)                                         /*!< Sampling clock is delayed by the delay block */
00408 #define HAL_OSPI_DELAY_BLOCK_BYPASSED        ((uint32_t)OCTOSPI_DCR1_DLYBYP)                                 /*!< Delay block is bypassed                      */
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup OSPI_OperationType OSPI Operation Type
00414   * @{
00415   */
00416 #define HAL_OSPI_OPTYPE_COMMON_CFG           ((uint32_t)0x00000000U)                                         /*!< Common configuration (indirect or auto-polling mode) */
00417 #define HAL_OSPI_OPTYPE_READ_CFG             ((uint32_t)0x00000001U)                                         /*!< Read configuration (memory-mapped mode)              */
00418 #define HAL_OSPI_OPTYPE_WRITE_CFG            ((uint32_t)0x00000002U)                                         /*!< Write configuration (memory-mapped mode)             */
00419 #define HAL_OSPI_OPTYPE_WRAP_CFG             ((uint32_t)0x00000003U)                                         /*!< Wrap configuration (memory-mapped mode)              */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup OSPI_FlashID OSPI Flash Id
00425   * @{
00426   */
00427 #define HAL_OSPI_FLASH_ID_1                  ((uint32_t)0x00000000U)                                         /*!< FLASH 1 selected */
00428 #define HAL_OSPI_FLASH_ID_2                  ((uint32_t)OCTOSPI_CR_FSEL)                                     /*!< FLASH 2 selected */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
00434   * @{
00435   */
00436 #define HAL_OSPI_INSTRUCTION_NONE            ((uint32_t)0x00000000U)                                         /*!< No instruction               */
00437 #define HAL_OSPI_INSTRUCTION_1_LINE          ((uint32_t)OCTOSPI_CCR_IMODE_0)                                 /*!< Instruction on a single line */
00438 #define HAL_OSPI_INSTRUCTION_2_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_1)                                 /*!< Instruction on two lines     */
00439 #define HAL_OSPI_INSTRUCTION_4_LINES         ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))         /*!< Instruction on four lines    */
00440 #define HAL_OSPI_INSTRUCTION_8_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_2)                                 /*!< Instruction on eight lines   */
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup OSPI_InstructionSize OSPI Instruction Size
00446   * @{
00447   */
00448 #define HAL_OSPI_INSTRUCTION_8_BITS          ((uint32_t)0x00000000U)                                         /*!< 8-bit instruction  */
00449 #define HAL_OSPI_INSTRUCTION_16_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_0)                                 /*!< 16-bit instruction */
00450 #define HAL_OSPI_INSTRUCTION_24_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_1)                                 /*!< 24-bit instruction */
00451 #define HAL_OSPI_INSTRUCTION_32_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE)                                   /*!< 32-bit instruction */
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
00457   * @{
00458   */
00459 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE     ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for instruction phase */
00460 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)OCTOSPI_CCR_IDTR)                                    /*!< DTR mode enabled for instruction phase  */
00461 /**
00462   * @}
00463   */
00464
00465 /** @defgroup OSPI_AddressMode OSPI Address Mode
00466   * @{
00467   */
00468 #define HAL_OSPI_ADDRESS_NONE                ((uint32_t)0x00000000U)                                         /*!< No address               */
00469 #define HAL_OSPI_ADDRESS_1_LINE              ((uint32_t)OCTOSPI_CCR_ADMODE_0)                                /*!< Address on a single line */
00470 #define HAL_OSPI_ADDRESS_2_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_1)                                /*!< Address on two lines     */
00471 #define HAL_OSPI_ADDRESS_4_LINES             ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))       /*!< Address on four lines    */
00472 #define HAL_OSPI_ADDRESS_8_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_2)                                /*!< Address on eight lines   */
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup OSPI_AddressSize OSPI Address Size
00478   * @{
00479   */
00480 #define HAL_OSPI_ADDRESS_8_BITS              ((uint32_t)0x00000000U)                                         /*!< 8-bit address  */
00481 #define HAL_OSPI_ADDRESS_16_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_0)                                /*!< 16-bit address */
00482 #define HAL_OSPI_ADDRESS_24_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_1)                                /*!< 24-bit address */
00483 #define HAL_OSPI_ADDRESS_32_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE)                                  /*!< 32-bit address */
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
00489   * @{
00490   */
00491 #define HAL_OSPI_ADDRESS_DTR_DISABLE         ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for address phase */
00492 #define HAL_OSPI_ADDRESS_DTR_ENABLE          ((uint32_t)OCTOSPI_CCR_ADDTR)                                   /*!< DTR mode enabled for address phase  */
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
00498   * @{
00499   */
00500 #define HAL_OSPI_ALTERNATE_BYTES_NONE        ((uint32_t)0x00000000U)                                         /*!< No alternate bytes               */
00501 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE      ((uint32_t)OCTOSPI_CCR_ABMODE_0)                                /*!< Alternate bytes on a single line */
00502 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_1)                                /*!< Alternate bytes on two lines     */
00503 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES     ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))       /*!< Alternate bytes on four lines    */
00504 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_2)                                /*!< Alternate bytes on eight lines   */
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size
00510   * @{
00511   */
00512 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS      ((uint32_t)0x00000000U)                                         /*!< 8-bit alternate bytes  */
00513 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_0)                                /*!< 16-bit alternate bytes */
00514 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_1)                                /*!< 24-bit alternate bytes */
00515 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE)                                  /*!< 32-bit alternate bytes */
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
00521   * @{
00522   */
00523 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for alternate bytes phase */
00524 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE  ((uint32_t)OCTOSPI_CCR_ABDTR)                                   /*!< DTR mode enabled for alternate bytes phase  */
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup OSPI_DataMode OSPI Data Mode
00530   * @{
00531   */
00532 #define HAL_OSPI_DATA_NONE                   ((uint32_t)0x00000000U)                                         /*!< No data               */
00533 #define HAL_OSPI_DATA_1_LINE                 ((uint32_t)OCTOSPI_CCR_DMODE_0)                                 /*!< Data on a single line */
00534 #define HAL_OSPI_DATA_2_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_1)                                 /*!< Data on two lines     */
00535 #define HAL_OSPI_DATA_4_LINES                ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))         /*!< Data on four lines    */
00536 #define HAL_OSPI_DATA_8_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_2)                                 /*!< Data on eight lines   */
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
00542   * @{
00543   */
00544 #define HAL_OSPI_DATA_DTR_DISABLE            ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for data phase */
00545 #define HAL_OSPI_DATA_DTR_ENABLE             ((uint32_t)OCTOSPI_CCR_DDTR)                                    /*!< DTR mode enabled for data phase  */
00546 /**
00547   * @}
00548   */
00549
00550 /** @defgroup OSPI_DQSMode OSPI DQS Mode
00551   * @{
00552   */
00553 #define HAL_OSPI_DQS_DISABLE                 ((uint32_t)0x00000000U)                                         /*!< DQS disabled */
00554 #define HAL_OSPI_DQS_ENABLE                  ((uint32_t)OCTOSPI_CCR_DQSE)                                    /*!< DQS enabled  */
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
00560   * @{
00561   */
00562 #define HAL_OSPI_SIOO_INST_EVERY_CMD         ((uint32_t)0x00000000U)                                         /*!< Send instruction on every transaction       */
00563 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD    ((uint32_t)OCTOSPI_CCR_SIOO)                                    /*!< Send instruction only for the first command */
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation
00569   * @{
00570   */
00571 #define HAL_OSPI_LATENCY_ON_WRITE            ((uint32_t)0x00000000U)                                         /*!< Latency on write accesses    */
00572 #define HAL_OSPI_NO_LATENCY_ON_WRITE         ((uint32_t)OCTOSPI_HLCR_WZL)                                    /*!< No latency on write accesses */
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
00578   * @{
00579   */
00580 #define HAL_OSPI_VARIABLE_LATENCY            ((uint32_t)0x00000000U)                                         /*!< Variable initial latency */
00581 #define HAL_OSPI_FIXED_LATENCY               ((uint32_t)OCTOSPI_HLCR_LM)                                     /*!< Fixed latency            */
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space
00587   * @{
00588   */
00589 #define HAL_OSPI_MEMORY_ADDRESS_SPACE        ((uint32_t)0x00000000U)                                         /*!< HyperBus memory mode   */
00590 #define HAL_OSPI_REGISTER_ADDRESS_SPACE      ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< HyperBus register mode */
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup OSPI_MatchMode OSPI Match Mode
00596   * @{
00597   */
00598 #define HAL_OSPI_MATCH_MODE_AND              ((uint32_t)0x00000000U)                                         /*!< AND match mode between unmasked bits */
00599 #define HAL_OSPI_MATCH_MODE_OR               ((uint32_t)OCTOSPI_CR_PMM)                                      /*!< OR match mode between unmasked bits  */
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop
00605   * @{
00606   */
00607 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE      ((uint32_t)0x00000000U)                                         /*!< AutoPolling stops only with abort or OSPI disabling */
00608 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE       ((uint32_t)OCTOSPI_CR_APMS)                                     /*!< AutoPolling stops as soon as there is a match       */
00609 /**
00610   * @}
00611   */
00612
00613 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation
00614   * @{
00615   */
00616 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE     ((uint32_t)0x00000000U)                                         /*!< Timeout counter disabled, nCS remains active               */
00617 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE      ((uint32_t)OCTOSPI_CR_TCEN)                                     /*!< Timeout counter enabled, nCS released when timeout expires */
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup OSPI_Flags OSPI Flags
00623   * @{
00624   */
00625 #define HAL_OSPI_FLAG_BUSY                   OCTOSPI_SR_BUSY                                                 /*!< Busy flag: operation is ongoing                                                                          */
00626 #define HAL_OSPI_FLAG_TO                     OCTOSPI_SR_TOF                                                  /*!< Timeout flag: timeout occurs in memory-mapped mode                                                       */
00627 #define HAL_OSPI_FLAG_SM                     OCTOSPI_SR_SMF                                                  /*!< Status match flag: received data matches in autopolling mode                                             */
00628 #define HAL_OSPI_FLAG_FT                     OCTOSPI_SR_FTF                                                  /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete              */
00629 #define HAL_OSPI_FLAG_TC                     OCTOSPI_SR_TCF                                                  /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
00630 #define HAL_OSPI_FLAG_TE                     OCTOSPI_SR_TEF                                                  /*!< Transfer error flag: invalid address is being accessed                                                   */
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup OSPI_Interrupts OSPI Interrupts
00636   * @{
00637   */
00638 #define HAL_OSPI_IT_TO                       OCTOSPI_CR_TOIE                                                 /*!< Interrupt on the timeout flag           */
00639 #define HAL_OSPI_IT_SM                       OCTOSPI_CR_SMIE                                                 /*!< Interrupt on the status match flag      */
00640 #define HAL_OSPI_IT_FT                       OCTOSPI_CR_FTIE                                                 /*!< Interrupt on the fifo threshold flag    */
00641 #define HAL_OSPI_IT_TC                       OCTOSPI_CR_TCIE                                                 /*!< Interrupt on the transfer complete flag */
00642 #define HAL_OSPI_IT_TE                       OCTOSPI_CR_TEIE                                                 /*!< Interrupt on the transfer error flag    */
00643 /**
00644   * @}
00645   */
00646
00647 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition
00648   * @{
00649   */
00650 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE       ((uint32_t)5000U)                                               /* 5 s */
00651 /**
00652   * @}
00653   */
00654
00655 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
00656   * @{
00657   */
00658 #define HAL_OSPIM_IOPORT_1_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))                          /*!< Port 1 - IO[3:0] */
00659 #define HAL_OSPIM_IOPORT_1_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))                          /*!< Port 1 - IO[7:4] */
00660 #define HAL_OSPIM_IOPORT_2_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))                          /*!< Port 2 - IO[3:0] */
00661 #define HAL_OSPIM_IOPORT_2_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))                          /*!< Port 2 - IO[7:4] */
00662 #define HAL_OSPIM_IOPORT_3_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))                          /*!< Port 3 - IO[3:0] */
00663 #define HAL_OSPIM_IOPORT_3_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))                          /*!< Port 3 - IO[7:4] */
00664 #define HAL_OSPIM_IOPORT_4_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))                          /*!< Port 4 - IO[3:0] */
00665 #define HAL_OSPIM_IOPORT_4_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))                          /*!< Port 4 - IO[7:4] */
00666 #define HAL_OSPIM_IOPORT_5_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))                          /*!< Port 5 - IO[3:0] */
00667 #define HAL_OSPIM_IOPORT_5_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))                          /*!< Port 5 - IO[7:4] */
00668 #define HAL_OSPIM_IOPORT_6_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))                          /*!< Port 6 - IO[3:0] */
00669 #define HAL_OSPIM_IOPORT_6_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))                          /*!< Port 6 - IO[7:4] */
00670 #define HAL_OSPIM_IOPORT_7_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))                          /*!< Port 7 - IO[3:0] */
00671 #define HAL_OSPIM_IOPORT_7_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))                          /*!< Port 7 - IO[7:4] */
00672 #define HAL_OSPIM_IOPORT_8_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))                          /*!< Port 8 - IO[3:0] */
00673 #define HAL_OSPIM_IOPORT_8_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))                          /*!< Port 8 - IO[7:4] */
00674 /**
00675   * @}
00676   */
00677 /**
00678   * @}
00679   */
00680
00681 /* Exported macros -----------------------------------------------------------*/
00682 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros
00683   * @{
00684   */
00685 /** @brief Reset OSPI handle state.
00686   * @param  __HANDLE__: OSPI handle.
00687   * @retval None
00688   */
00689 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00690 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00691                                                                   (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
00692                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
00693                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
00694                                                                } while(0)
00695 #else
00696 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
00697 #endif
00698
00699 /** @brief  Enable the OSPI peripheral.
00700   * @param  __HANDLE__: specifies the OSPI Handle.
00701   * @retval None
00702   */
00703 #define __HAL_OSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
00704
00705 /** @brief  Disable the OSPI peripheral.
00706   * @param  __HANDLE__: specifies the OSPI Handle.
00707   * @retval None
00708   */
00709 #define __HAL_OSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
00710
00711 /** @brief  Enable the specified OSPI interrupt.
00712   * @param  __HANDLE__: specifies the OSPI Handle.
00713   * @param  __INTERRUPT__: specifies the OSPI interrupt source to enable.
00714   *          This parameter can be one of the following values:
00715   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
00716   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
00717   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
00718   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
00719   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
00720   * @retval None
00721   */
00722 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00723
00724
00725 /** @brief  Disable the specified OSPI interrupt.
00726   * @param  __HANDLE__: specifies the OSPI Handle.
00727   * @param  __INTERRUPT__: specifies the OSPI interrupt source to disable.
00728   *          This parameter can be one of the following values:
00729   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
00730   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
00731   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
00732   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
00733   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
00734   * @retval None
00735   */
00736 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00737
00738 /** @brief  Check whether the specified OSPI interrupt source is enabled or not.
00739   * @param  __HANDLE__: specifies the OSPI Handle.
00740   * @param  __INTERRUPT__: specifies the OSPI interrupt source to check.
00741   *          This parameter can be one of the following values:
00742   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
00743   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
00744   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
00745   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
00746   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
00747   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00748   */
00749 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00750
00751 /**
00752   * @brief  Check whether the selected OSPI flag is set or not.
00753   * @param  __HANDLE__: specifies the OSPI Handle.
00754   * @param  __FLAG__: specifies the OSPI flag to check.
00755   *          This parameter can be one of the following values:
00756   *            @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
00757   *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag
00758   *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag
00759   *            @arg HAL_OSPI_FLAG_FT:   OSPI FIFO threshold flag
00760   *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag
00761   *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag
00762   * @retval None
00763   */
00764 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
00765
00766 /** @brief  Clears the specified OSPI's flag status.
00767   * @param  __HANDLE__: specifies the OSPI Handle.
00768   * @param  __FLAG__: specifies the OSPI clear register flag that needs to be set
00769   *          This parameter can be one of the following values:
00770   *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag
00771   *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag
00772   *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag
00773   *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag
00774   * @retval None
00775   */
00776 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00777
00778 /**
00779   * @}
00780   */
00781
00782 /* Exported functions --------------------------------------------------------*/
00783 /** @addtogroup OSPI_Exported_Functions
00784   * @{
00785   */
00786
00787 /* Initialization/de-initialization functions  ********************************/
00788 /** @addtogroup OSPI_Exported_Functions_Group1
00789   * @{
00790   */
00791 HAL_StatusTypeDef     HAL_OSPI_Init                 (OSPI_HandleTypeDef *hospi);
00792 void                  HAL_OSPI_MspInit              (OSPI_HandleTypeDef *hospi);
00793 HAL_StatusTypeDef     HAL_OSPI_DeInit               (OSPI_HandleTypeDef *hospi);
00794 void                  HAL_OSPI_MspDeInit            (OSPI_HandleTypeDef *hospi);
00795
00796 /**
00797   * @}
00798   */
00799
00800 /* IO operation functions *****************************************************/
00801 /** @addtogroup OSPI_Exported_Functions_Group2
00802   * @{
00803   */
00804 /* OSPI IRQ handler function */
00805 void                  HAL_OSPI_IRQHandler           (OSPI_HandleTypeDef *hospi);
00806
00807 /* OSPI command configuration functions */
00808 HAL_StatusTypeDef     HAL_OSPI_Command              (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
00809 HAL_StatusTypeDef     HAL_OSPI_Command_IT           (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
00810 HAL_StatusTypeDef     HAL_OSPI_HyperbusCfg          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
00811 HAL_StatusTypeDef     HAL_OSPI_HyperbusCmd          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
00812
00813 /* OSPI indirect mode functions */
00814 HAL_StatusTypeDef     HAL_OSPI_Transmit             (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
00815 HAL_StatusTypeDef     HAL_OSPI_Receive              (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
00816 HAL_StatusTypeDef     HAL_OSPI_Transmit_IT          (OSPI_HandleTypeDef *hospi, uint8_t *pData);
00817 HAL_StatusTypeDef     HAL_OSPI_Receive_IT           (OSPI_HandleTypeDef *hospi, uint8_t *pData);
00818 HAL_StatusTypeDef     HAL_OSPI_Transmit_DMA         (OSPI_HandleTypeDef *hospi, uint8_t *pData);
00819 HAL_StatusTypeDef     HAL_OSPI_Receive_DMA          (OSPI_HandleTypeDef *hospi, uint8_t *pData);
00820
00821 /* OSPI status flag polling mode functions */
00822 HAL_StatusTypeDef     HAL_OSPI_AutoPolling          (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00823 HAL_StatusTypeDef     HAL_OSPI_AutoPolling_IT       (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
00824
00825 /* OSPI memory-mapped mode functions */
00826 HAL_StatusTypeDef     HAL_OSPI_MemoryMapped         (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
00827
00828 /* Callback functions in non-blocking modes ***********************************/
00829 void                  HAL_OSPI_ErrorCallback        (OSPI_HandleTypeDef *hospi);
00830 void                  HAL_OSPI_AbortCpltCallback    (OSPI_HandleTypeDef *hospi);
00831 void                  HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
00832
00833 /* OSPI indirect mode functions */
00834 void                  HAL_OSPI_CmdCpltCallback      (OSPI_HandleTypeDef *hospi);
00835 void                  HAL_OSPI_RxCpltCallback       (OSPI_HandleTypeDef *hospi);
00836 void                  HAL_OSPI_TxCpltCallback       (OSPI_HandleTypeDef *hospi);
00837 void                  HAL_OSPI_RxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
00838 void                  HAL_OSPI_TxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
00839
00840 /* OSPI status flag polling mode functions */
00841 void                  HAL_OSPI_StatusMatchCallback  (OSPI_HandleTypeDef *hospi);
00842
00843 /* OSPI memory-mapped mode functions */
00844 void                  HAL_OSPI_TimeOutCallback      (OSPI_HandleTypeDef *hospi);
00845
00846 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
00847 /* OSPI callback registering/unregistering */
00848 HAL_StatusTypeDef     HAL_OSPI_RegisterCallback     (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);
00849 HAL_StatusTypeDef     HAL_OSPI_UnRegisterCallback   (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
00850 #endif
00851 /**
00852   * @}
00853   */
00854
00855 /* Peripheral Control and State functions  ************************************/
00856 /** @addtogroup OSPI_Exported_Functions_Group3
00857   * @{
00858   */
00859 HAL_StatusTypeDef     HAL_OSPI_Abort                (OSPI_HandleTypeDef *hospi);
00860 HAL_StatusTypeDef     HAL_OSPI_Abort_IT             (OSPI_HandleTypeDef *hospi);
00861 HAL_StatusTypeDef     HAL_OSPI_SetFifoThreshold     (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
00862 uint32_t              HAL_OSPI_GetFifoThreshold     (OSPI_HandleTypeDef *hospi);
00863 HAL_StatusTypeDef     HAL_OSPI_SetTimeout           (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
00864 uint32_t              HAL_OSPI_GetError             (OSPI_HandleTypeDef *hospi);
00865 uint32_t              HAL_OSPI_GetState             (OSPI_HandleTypeDef *hospi);
00866
00867 /**
00868   * @}
00869   */
00870
00871 /* OSPI IO Manager configuration function  ************************************/
00872 /** @addtogroup OSPI_Exported_Functions_Group4
00873   * @{
00874   */
00875 HAL_StatusTypeDef     HAL_OSPIM_Config              (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
00876
00877 /**
00878   * @}
00879   */
00880
00881 /**
00882   * @}
00883   */
00884 /* End of exported functions -------------------------------------------------*/
00885
00886 /* Private macros ------------------------------------------------------------*/
00887 /**
00888   @cond 0
00889   */
00890 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD)  (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
00891
00892 #define IS_OSPI_DUALQUAD_MODE(MODE)        (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
00893                                             ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
00894
00895 #define IS_OSPI_MEMORY_TYPE(TYPE)          (((TYPE) == HAL_OSPI_MEMTYPE_MICRON)       || \
00896                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX)     || \
00897                                             ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY)     || \
00898                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
00899                                             ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
00900
00901 #define IS_OSPI_DEVICE_SIZE(SIZE)          (((SIZE) >= 1U) && ((SIZE) <= 32U))
00902
00903 #define IS_OSPI_CS_HIGH_TIME(TIME)         (((TIME) >= 1U) && ((TIME) <= 8U))
00904
00905 #define IS_OSPI_FREE_RUN_CLK(CLK)          (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
00906                                             ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
00907
00908 #define IS_OSPI_CLOCK_MODE(MODE)           (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
00909                                             ((MODE) == HAL_OSPI_CLOCK_MODE_3))
00910
00911 #define IS_OSPI_WRAP_SIZE(SIZE)            (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
00912                                             ((SIZE) == HAL_OSPI_WRAP_16_BYTES)      || \
00913                                             ((SIZE) == HAL_OSPI_WRAP_32_BYTES)      || \
00914                                             ((SIZE) == HAL_OSPI_WRAP_64_BYTES)      || \
00915                                             ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
00916
00917 #define IS_OSPI_CLK_PRESCALER(PRESCALER)   (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
00918
00919 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE)     (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE)      || \
00920                                             ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
00921
00922 #define IS_OSPI_DHQC(CYCLE)                (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
00923                                             ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
00924
00925 #define IS_OSPI_OPERATION_TYPE(TYPE)       (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
00926                                             ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG)   || \
00927                                             ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)  || \
00928                                             ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG))
00929
00930 #define IS_OSPI_FLASH_ID(FLASHID)          (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \
00931                                             ((FLASHID) == HAL_OSPI_FLASH_ID_2))
00932
00933 #define IS_OSPI_INSTRUCTION_MODE(MODE)     (((MODE) == HAL_OSPI_INSTRUCTION_NONE)    || \
00934                                             ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE)  || \
00935                                             ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
00936                                             ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
00937                                             ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
00938
00939 #define IS_OSPI_INSTRUCTION_SIZE(SIZE)     (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS)  || \
00940                                             ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
00941                                             ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
00942                                             ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
00943
00944 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
00945                                             ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
00946
00947 #define IS_OSPI_ADDRESS_MODE(MODE)         (((MODE) == HAL_OSPI_ADDRESS_NONE)    || \
00948                                             ((MODE) == HAL_OSPI_ADDRESS_1_LINE)  || \
00949                                             ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
00950                                             ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
00951                                             ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
00952
00953 #define IS_OSPI_ADDRESS_SIZE(SIZE)         (((SIZE) == HAL_OSPI_ADDRESS_8_BITS)  || \
00954                                             ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
00955                                             ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
00956                                             ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
00957
00958 #define IS_OSPI_ADDRESS_DTR_MODE(MODE)     (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
00959                                             ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
00960
00961 #define IS_OSPI_ALT_BYTES_MODE(MODE)       (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE)    || \
00962                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE)  || \
00963                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
00964                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
00965                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
00966
00967 #define IS_OSPI_ALT_BYTES_SIZE(SIZE)       (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS)  || \
00968                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
00969                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
00970                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
00971
00972 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE)   (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
00973                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
00974
00975 #define IS_OSPI_DATA_MODE(MODE)            (((MODE) == HAL_OSPI_DATA_NONE)    || \
00976                                             ((MODE) == HAL_OSPI_DATA_1_LINE)  || \
00977                                             ((MODE) == HAL_OSPI_DATA_2_LINES) || \
00978                                             ((MODE) == HAL_OSPI_DATA_4_LINES) || \
00979                                             ((MODE) == HAL_OSPI_DATA_8_LINES))
00980
00981 #define IS_OSPI_NUMBER_DATA(NUMBER)        ((NUMBER) >= 1U)
00982
00983 #define IS_OSPI_DATA_DTR_MODE(MODE)        (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
00984                                             ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
00985
00986 #define IS_OSPI_DUMMY_CYCLES(NUMBER)       ((NUMBER) <= 31U)
00987
00988 #define IS_OSPI_DQS_MODE(MODE)             (((MODE) == HAL_OSPI_DQS_DISABLE) || \
00989                                             ((MODE) == HAL_OSPI_DQS_ENABLE))
00990
00991 #define IS_OSPI_SIOO_MODE(MODE)            (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
00992                                             ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
00993
00994 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER)   ((NUMBER) <= 255U)
00995
00996 #define IS_OSPI_ACCESS_TIME(NUMBER)        ((NUMBER) <= 255U)
00997
00998 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE)   (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
00999                                             ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
01000
01001 #define IS_OSPI_LATENCY_MODE(MODE)         (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
01002                                             ((MODE) == HAL_OSPI_FIXED_LATENCY))
01003
01004 #define IS_OSPI_ADDRESS_SPACE(SPACE)       (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
01005                                             ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
01006
01007 #define IS_OSPI_MATCH_MODE(MODE)           (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
01008                                             ((MODE) == HAL_OSPI_MATCH_MODE_OR))
01009
01010 #define IS_OSPI_AUTOMATIC_STOP(MODE)       (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
01011                                             ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
01012
01013 #define IS_OSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= 0xFFFFU)
01014
01015 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
01016
01017 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE)   (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
01018                                             ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
01019
01020 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
01021
01022 #define IS_OSPI_CS_BOUNDARY(BOUNDARY)      ((BOUNDARY) <= 31U)
01023
01024 #define IS_OSPI_CKCSHT(CLK_NB)             ((CLK_NB) <= 7U)
01025
01026 #define IS_OSPI_DLYBYP(MODE)               (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
01027                                             ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
01028
01029 #define IS_OSPI_MAXTRAN(NB_BYTES)          ((NB_BYTES) <= 255U)
01030
01031 #define IS_OSPIM_PORT(NUMBER)              (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
01032
01033 #define IS_OSPIM_IO_PORT(PORT)             (((PORT) == HAL_OSPIM_IOPORT_1_LOW)  || \
01034                                             ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
01035                                             ((PORT) == HAL_OSPIM_IOPORT_2_LOW)  || \
01036                                             ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \
01037                                             ((PORT) == HAL_OSPIM_IOPORT_3_LOW)  || \
01038                                             ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \
01039                                             ((PORT) == HAL_OSPIM_IOPORT_4_LOW)  || \
01040                                             ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \
01041                                             ((PORT) == HAL_OSPIM_IOPORT_5_LOW)  || \
01042                                             ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \
01043                                             ((PORT) == HAL_OSPIM_IOPORT_6_LOW)  || \
01044                                             ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \
01045                                             ((PORT) == HAL_OSPIM_IOPORT_7_LOW)  || \
01046                                             ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
01047                                             ((PORT) == HAL_OSPIM_IOPORT_8_LOW)  || \
01048                                             ((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
01049 /**
01050   @endcond
01051   */
01052
01053 /* End of private macros -----------------------------------------------------*/
01054
01055 /**
01056   * @}
01057   */
01058
01059 /**
01060   * @}
01061   */
01062
01063 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
01064
01065 #ifdef __cplusplus
01066 }
01067 #endif
01068
01069 #endif /* STM32H7xx_HAL_OSPI_H */
01070
01071 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_otfdec.c Source File

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stm32h7xx_hal_otfdec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_otfdec.c
00004   * @author  MCD Application Team
00005   * @brief   OTFDEC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the On-The-Fly Decryption (OTFDEC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Region setting/enable functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016  [..]
00017     The OTFDEC HAL driver can be used as follows:
00018
00019     (#) Declare an OTFDEC_HandleTypeDef handle structure (eg. OTFDEC_HandleTypeDef hotfdec).
00020
00021     (#) Initialize the OTFDEC low level resources by implementing the HAL_OTFDEC_MspInit() API:
00022         (++) Enable the OTFDEC interface clock.
00023         (++) NVIC configuration if interrupts are used
00024             (+++) Configure the OTFDEC interrupt priority.
00025             (+++) Enable the NVIC OTFDEC IRQ handle.
00026
00027     (#) Initialize the OTFDEC peripheral by calling the HAL_OTFDEC_Init() API.
00028
00029     (#) For each region,
00030
00031         (++) Configure the region deciphering mode by calling the HAL_OTFDEC_RegionSetMode() API.
00032
00033         (++) Write the region Key by calling the HAL_OTFDEC_RegionSetKey() API. If desired,
00034         read the key CRC by calling HAL_OTFDEC_RegionGetKeyCRC() API and compare the
00035         result with the theoretically expected CRC.
00036
00037         (++) Initialize the OTFDEC region config structure with the Nonce, protected
00038         region start and end addresses and firmware version, and wrap-up the region
00039         configuration by calling HAL_OTFDEC_RegionConfig() API.
00040
00041     (#) At this point, the OTFDEC region configuration is done and the deciphering
00042         is enabled. The region can be deciphered on the fly after having made sure
00043         the OctoSPI is configured in memory-mapped mode.
00044
00045     [..]
00046     (@) Warning: the OTFDEC deciphering is based on a different endianness compared
00047         to the AES-CTR as implemented in the AES peripheral. E.g., if the OTFEC
00048         resorts to the Key (B0, B1, B2, B3) where Bi are 32-bit longwords and B0
00049         is the Least Significant Word, the AES has to be configured with the Key
00050         (B3, B2, B1, B0) to report the same result (with the same swapping applied
00051         to the Initialization Vector).
00052
00053     [..]
00054
00055     *** Callback registration ***
00056     =============================================
00057     [..]
00058
00059      The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
00060      allows the user to configure dynamically the driver callbacks.
00061      Use Functions @ref HAL_OTFDEC_RegisterCallback()
00062      to register an interrupt callback.
00063     [..]
00064
00065      Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
00066        (+) ErrorCallback                  : OTFDEC error callback
00067        (+) MspInitCallback                : OTFDEC Msp Init callback
00068        (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
00069      This function takes as parameters the HAL peripheral handle, the Callback ID
00070      and a pointer to the user callback function.
00071     [..]
00072
00073      Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
00074      weak function.
00075     [..]
00076
00077      @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00078      and the Callback ID.
00079      This function allows to reset following callbacks:
00080        (+) ErrorCallback                  : OTFDEC error callback
00081        (+) MspInitCallback                : OTFDEC Msp Init callback
00082        (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
00083      [..]
00084
00085      By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
00086      all callbacks are set to the corresponding weak functions:
00087      example @ref HAL_OTFDEC_ErrorCallback().
00088      Exception done for MspInit and MspDeInit functions that are
00089      reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
00090      these callbacks are null (not registered beforehand).
00091     [..]
00092
00093      If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
00094      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00095      [..]
00096
00097      Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
00098      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00099      in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
00100      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00101     [..]
00102
00103      Then, the user first registers the MspInit/MspDeInit user callbacks
00104      using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
00105      or @ref HAL_OTFDEC_Init() function.
00106      [..]
00107
00108      When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
00109      not defined, the callback registration feature is not available and all callbacks
00110      are set to the corresponding weak functions.
00111
00112   @endverbatim
00113   ******************************************************************************
00114   * @attention
00115   *
00116   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
00117   * All rights reserved.</center></h2>
00118   *
00119   * This software component is licensed by ST under BSD 3-Clause license,
00120   * the "License"; You may not use this file except in compliance with the
00121   * License. You may obtain a copy of the License at:
00122   *                        opensource.org/licenses/BSD-3-Clause
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32h7xx_hal.h"
00129
00130 /** @addtogroup STM32H7xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup OTFDEC OTFDEC
00135   * @brief OTFDEC HAL module driver.
00136   * @{
00137   */
00138
00139
00140 #ifdef HAL_OTFDEC_MODULE_ENABLED
00141
00142 #if defined(OTFDEC1)
00143
00144 /* Private typedef -----------------------------------------------------------*/
00145 /* Private define ------------------------------------------------------------*/
00146 /* Private macro -------------------------------------------------------------*/
00147 /* Private variables ---------------------------------------------------------*/
00148 /* Private function prototypes -----------------------------------------------*/
00149 /* Private functions ---------------------------------------------------------*/
00150
00151
00152
00153  /* Exported functions --------------------------------------------------------*/
00154 /** @addtogroup OTFDEC_Exported_Functions
00155   * @{
00156   */
00157
00158 /** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
00159  *  @brief    Initialization and Configuration functions.
00160  *
00161 @verbatim
00162   ==============================================================================
00163               ##### Initialization and de-initialization functions #####
00164   ==============================================================================
00165
00166 @endverbatim
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  Initialize the OTFDEC peripheral and create the associated handle.
00172   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00173   *         the configuration information for OTFDEC module
00174   * @retval HAL status
00175   */
00176 HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
00177 {
00178   /* Check the OTFDEC handle allocation */
00179   if(hotfdec == NULL)
00180   {
00181     return HAL_ERROR;
00182   }
00183
00184   /* Check the parameters */
00185   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00186
00187   if(hotfdec->State == HAL_OTFDEC_STATE_RESET)
00188   {
00189     /* Allocate lock resource and initialize it */
00190     __HAL_UNLOCK(hotfdec);
00191
00192 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00193     /* Init the OTFDEC Callback settings */
00194     hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback; /* Legacy weak callback */
00195
00196     if (hotfdec->MspInitCallback == NULL)
00197     {
00198       hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
00199     }
00200
00201     /* Init the low level hardware */
00202     hotfdec->MspInitCallback(hotfdec);
00203 #else
00204     /* Init the low level hardware */
00205     HAL_OTFDEC_MspInit(hotfdec);
00206 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00207   }
00208
00209   /* Change the OTFDEC state */
00210   hotfdec->State = HAL_OTFDEC_STATE_READY;
00211
00212   /* Return function status */
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  DeInitialize the OTFDEC peripheral.
00218   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00219   *         the configuration information for OTFDEC module
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
00223 {
00224   /* Check the OTFDEC handle allocation */
00225   if(hotfdec == NULL)
00226   {
00227     return HAL_ERROR;
00228   }
00229
00230   /* Check the parameters */
00231   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00232
00233   /* Change the OTFDEC state */
00234   hotfdec->State = HAL_OTFDEC_STATE_BUSY;
00235
00236 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00237   if (hotfdec->MspDeInitCallback == NULL)
00238   {
00239     hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
00240   }
00241
00242   /* DeInit the low level hardware: CLOCK, NVIC */
00243   hotfdec->MspDeInitCallback(hotfdec);
00244 #else
00245   /* DeInit the low level hardware: CLOCK, NVIC */
00246   HAL_OTFDEC_MspDeInit(hotfdec);
00247 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00248
00249   /* Change the OTFDEC state */
00250   hotfdec->State = HAL_OTFDEC_STATE_RESET;
00251
00252   /* Reset OTFDEC error status */
00253   hotfdec->ErrorCode = HAL_OTFDEC_ERROR_NONE;
00254
00255   /* Release Lock */
00256   __HAL_UNLOCK(hotfdec);
00257
00258   /* Return function status */
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  Initialize the OTFDEC MSP.
00264   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00265   *         the configuration information for OTFDEC module
00266   * @retval None
00267   */
00268 __weak void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec)
00269 {
00270   /* Prevent unused argument(s) compilation warning */
00271   UNUSED(hotfdec);
00272
00273   /* NOTE : This function should not be modified; when the callback is needed,
00274             the HAL_OTFDEC_MspInit can be implemented in the user file.
00275    */
00276 }
00277
00278 /**
00279   * @brief  DeInitialize OTFDEC MSP.
00280   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00281   *         the configuration information for OTFDEC module
00282   * @retval None
00283   */
00284 __weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec)
00285 {
00286   /* Prevent unused argument(s) compilation warning */
00287   UNUSED(hotfdec);
00288
00289   /* NOTE : This function should not be modified; when the callback is needed,
00290             the HAL_OTFDEC_MspDeInit can be implemented in the user file.
00291    */
00292 }
00293
00294 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00295 /**
00296   * @brief  Register a User OTFDEC Callback
00297   *         To be used instead of the weak predefined callback
00298   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00299   *         the configuration information for OTFDEC module
00300   * @param  CallbackID ID of the callback to be registered
00301   *         This parameter can be one of the following values:
00302   *          @arg @ref HAL_OTFDEC_ERROR_CB_ID           OTFDEC error callback ID
00303   *          @arg @ref HAL_OTFDEC_MSPINIT_CB_ID         MspInit callback ID
00304   *          @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID       MspDeInit callback ID
00305   * @param  pCallback pointer to the Callback function
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback)
00309 {
00310   HAL_StatusTypeDef status = HAL_OK;
00311
00312   if (pCallback == NULL)
00313   {
00314     /* Update the error code */
00315     hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00316
00317     return HAL_ERROR;
00318   }
00319
00320   if (hotfdec->State == HAL_OTFDEC_STATE_READY)
00321   {
00322     switch (CallbackID)
00323     {
00324       case HAL_OTFDEC_ERROR_CB_ID :
00325         hotfdec->ErrorCallback = pCallback;
00326         break;
00327
00328       case HAL_OTFDEC_MSPINIT_CB_ID :
00329         hotfdec->MspInitCallback = pCallback;
00330         break;
00331
00332       case HAL_OTFDEC_MSPDEINIT_CB_ID :
00333         hotfdec->MspDeInitCallback = pCallback;
00334         break;
00335
00336       default :
00337         /* Update the error code */
00338         hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00339
00340         /* Return error status */
00341         status = HAL_ERROR;
00342         break;
00343     }
00344   }
00345   else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
00346   {
00347     switch (CallbackID)
00348     {
00349       case HAL_OTFDEC_MSPINIT_CB_ID :
00350         hotfdec->MspInitCallback = pCallback;
00351         break;
00352
00353       case HAL_OTFDEC_MSPDEINIT_CB_ID :
00354         hotfdec->MspDeInitCallback = pCallback;
00355         break;
00356
00357       default :
00358         /* Update the error code */
00359         hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00360
00361         /* Return error status */
00362         status = HAL_ERROR;
00363         break;
00364     }
00365   }
00366   else
00367   {
00368     /* Update the error code */
00369     hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00370
00371     /* Return error status */
00372     status =  HAL_ERROR;
00373   }
00374
00375   return status;
00376 }
00377
00378 /**
00379   * @brief  Unregister a OTFDEC Callback
00380   *         OTFDEC callback is redirected to the weak predefined callback
00381   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00382   *         the configuration information for OTFDEC module
00383   * @param  CallbackID ID of the callback to be registered
00384   *         This parameter can be one of the following values:
00385   *          @arg @ref HAL_OTFDEC_ERROR_CB_ID           OTFDEC error callback ID
00386   *          @arg @ref HAL_OTFDEC_MSPINIT_CB_ID         MspInit callback ID
00387   *          @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID       MspDeInit callback ID
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
00391 {
00392   HAL_StatusTypeDef status = HAL_OK;
00393
00394   if (hotfdec->State == HAL_OTFDEC_STATE_READY)
00395   {
00396     switch (CallbackID)
00397     {
00398       case HAL_OTFDEC_ERROR_CB_ID :
00399         hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback;
00400         break;
00401
00402       case HAL_OTFDEC_MSPINIT_CB_ID :
00403         hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
00404         break;
00405
00406       case HAL_OTFDEC_MSPDEINIT_CB_ID :
00407         hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
00408         break;
00409
00410       default :
00411         /* Update the error code */
00412         hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00413
00414         /* Return error status */
00415         status =  HAL_ERROR;
00416         break;
00417     }
00418   }
00419   else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
00420   {
00421     switch (CallbackID)
00422     {
00423       case HAL_OTFDEC_MSPINIT_CB_ID :
00424         hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
00425         break;
00426
00427       case HAL_OTFDEC_MSPDEINIT_CB_ID :
00428         hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
00429         break;
00430
00431       default :
00432         /* Update the error code */
00433         hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00434
00435         /* Return error status */
00436         status =  HAL_ERROR;
00437         break;
00438     }
00439   }
00440   else
00441   {
00442     /* Update the error code */
00443     hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
00444
00445     /* Return error status */
00446     status =  HAL_ERROR;
00447   }
00448
00449   return status;
00450 }
00451
00452 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00453
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup OTFDEC_Exported_Functions_Group2  OTFDEC IRQ handler management
00459  *  @brief   OTFDEC IRQ handler.
00460  *
00461 @verbatim
00462   ==============================================================================
00463                 ##### OTFDEC IRQ handler management #####
00464   ==============================================================================
00465 [..]  This section provides OTFDEC IRQ handler function.
00466
00467 @endverbatim
00468   * @{
00469   */
00470
00471 /**
00472   * @brief  Handle OTFDEC interrupt request.
00473   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00474   *         the configuration information for OTFDEC module
00475   * @retval None
00476   */
00477 void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
00478 {
00479   uint32_t isr_reg;
00480
00481   isr_reg = READ_REG(hotfdec->Instance->ISR);
00482   if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
00483   {
00484     SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_SEIF );
00485     hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
00486   }
00487   if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
00488   {
00489     SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF );
00490     hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
00491   }
00492   if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
00493   {
00494     SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_KEIF );
00495     hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
00496   }
00497
00498 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00499   hotfdec->ErrorCallback(hotfdec);
00500 #else
00501   HAL_OTFDEC_ErrorCallback(hotfdec);
00502 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00503 }
00504
00505 /**
00506   * @brief OTFDEC error callback.
00507   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00508   *         the configuration information for OTFDEC module
00509   * @retval None
00510   */
00511 __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
00512 {
00513   /* Prevent unused argument(s) compilation warning */
00514   UNUSED(hotfdec);
00515
00516   /* NOTE : This function should not be modified; when the callback is needed,
00517             the HAL_OTFDEC_ErrorCallback can be implemented in the user file.
00518    */
00519 }
00520
00521 /**
00522   * @}
00523   */
00524
00525
00526
00527
00528 /** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
00529  *  @brief   Peripheral control functions.
00530  *
00531 @verbatim
00532   ==============================================================================
00533                       ##### Peripheral Control functions #####
00534   ==============================================================================
00535     [..]
00536     This subsection permits to configure the OTFDEC peripheral
00537
00538 @endverbatim
00539   * @{
00540   */
00541
00542 /**
00543   * @brief  Lock region keys.
00544   * @note   Writes to this region KEYRx registers are ignored until next OTFDEC reset.
00545   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00546   *         the configuration information for OTFDEC module
00547   * @param  RegionIndex index of region the keys of which are locked
00548   * @retval HAL state
00549   */
00550 HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
00551 {
00552   OTFDEC_Region_TypeDef * region;
00553   uint32_t address;
00554
00555   /* Check the parameters */
00556   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00557   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00558
00559   /* Take Lock */
00560   __HAL_LOCK(hotfdec);
00561
00562   address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00563   region = (OTFDEC_Region_TypeDef *)address;
00564
00565   SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK );
00566
00567   /* Release Lock */
00568   __HAL_UNLOCK(hotfdec);
00569
00570   /* Status is okay */
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Set region keys.
00576   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00577   *         the configuration information for OTFDEC module
00578   * @param  RegionIndex index of region the keys of which are set
00579   * @param  pKey pointer at set of keys
00580   * @note   The API reads the key CRC computed by the peripheral and compares it with thzt
00581   *         theoretically expected. An error is reported if they are different.
00582   * @retval HAL state
00583   */
00584 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
00585 {
00586   OTFDEC_Region_TypeDef * region;
00587   uint32_t address;
00588
00589   /* Check the parameters */
00590   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00591   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00592
00593   if (pKey == NULL)
00594   {
00595     return HAL_ERROR;
00596   }
00597   else
00598   {
00599     /* Take Lock */
00600     __HAL_LOCK(hotfdec);
00601
00602     address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00603     region = (OTFDEC_Region_TypeDef *)address;
00604
00605     /* Set Key */
00606     WRITE_REG( region->REG_KEYR0, pKey[0]);
00607
00608     __DSB();
00609     __ISB();
00610
00611     WRITE_REG( region->REG_KEYR1, pKey[1]);
00612
00613     __DSB();
00614     __ISB();
00615
00616     WRITE_REG( region->REG_KEYR2, pKey[2]);
00617
00618     __DSB();
00619     __ISB();
00620
00621     WRITE_REG( region->REG_KEYR3, pKey[3]);
00622
00623     /* Compute theoretically expected CRC and compare it with that reported by the peripheral */
00624     if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
00625     {
00626       /* Release Lock */
00627       __HAL_UNLOCK(hotfdec);
00628
00629       /* Status is okay */
00630       return HAL_ERROR;
00631     }
00632
00633     /* Release Lock */
00634     __HAL_UNLOCK(hotfdec);
00635
00636     /* Status is okay */
00637     return HAL_OK;
00638   }
00639 }
00640
00641 /**
00642   * @brief  Set region mode.
00643   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00644   *         the configuration information for OTFDEC module
00645   * @param  RegionIndex index of region the mode of which is set
00646   * @param  mode This parameter can be only:
00647   *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY             Only instruction accesses are decrypted
00648   *           @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY                    Only data accesses are decrypted
00649   *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES          All read accesses are decrypted (instruction or data)
00650   *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated
00651   * @retval HAL state
00652   */
00653 HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
00654 {
00655   OTFDEC_Region_TypeDef * region;
00656   uint32_t address;
00657
00658   /* Check the parameters */
00659   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00660   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00661   assert_param(IS_OTFDEC_REGION_OPERATING_MODE(mode));
00662
00663   /* Take Lock */
00664   __HAL_LOCK(hotfdec);
00665
00666   address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00667   region = (OTFDEC_Region_TypeDef *)address;
00668
00669   /* Set mode */
00670   MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_MODE, mode);
00671
00672   /* Release Lock */
00673   __HAL_UNLOCK(hotfdec);
00674
00675   /* Status is okay */
00676   return HAL_OK;
00677 }
00678
00679 /**
00680   * @brief  Set region configuration.
00681   * @note  Region deciphering is enabled at the end of this function
00682   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00683   *         the configuration information for OTFDEC module
00684   * @param  RegionIndex index of region that is configured
00685   * @param  Config pointer on structure containing the region configuration parameters
00686   * @param  lock configuration lock enable or disable parameter
00687   *         This parameter can be one of the following values:
00688   *          @arg @ref OTFDEC_REG_CONFIGR_LOCK_DISABLE      OTFDEC region configuration is not locked
00689   *          @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE       OTFDEC region configuration is locked
00690   * @retval HAL state
00691   */
00692 HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
00693 {
00694   OTFDEC_Region_TypeDef * region;
00695   uint32_t address;
00696
00697   /* Check the parameters */
00698   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00699   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00700   assert_param(IS_OTFDEC_REGION_CONFIG_LOCK(lock));
00701
00702   if (Config == NULL)
00703   {
00704     return HAL_ERROR;
00705   }
00706   else
00707   {
00708
00709     /* Take Lock */
00710     __HAL_LOCK(hotfdec);
00711
00712     address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00713     region = (OTFDEC_Region_TypeDef *)address;
00714
00715     /* Set Nonce */
00716     WRITE_REG( region->REG_NONCER0, Config->Nonce[0]);
00717
00718     WRITE_REG( region->REG_NONCER1, Config->Nonce[1]);
00719
00720     /* Write region protected area start and end addresses */
00721     WRITE_REG( region->REG_START_ADDR, Config->StartAddress);
00722
00723     WRITE_REG( region->REG_END_ADDR, Config->EndAddress);
00724
00725     /* Write Version */
00726     MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
00727
00728     /* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
00729     SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
00730
00731     /* Lock the region configuration according to lock parameter value */
00732     if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
00733     {
00734       SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
00735     }
00736
00737     /* Release Lock */
00738     __HAL_UNLOCK(hotfdec);
00739
00740     /* Status is okay */
00741     return HAL_OK;
00742   }
00743 }
00744
00745
00746 /**
00747   * @brief  Compute Key CRC
00748   * @param  pKey pointer at set of keys
00749   * @retval CRC value
00750   */
00751 uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
00752 {
00753   uint8_t crc7_poly = 0x7;
00754   uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
00755   uint8_t  i;
00756   uint8_t crc = 0;
00757   uint32_t  j, keyval, k;
00758   uint32_t * temp = pKey;
00759
00760   for (j = 0U; j < 4U; j++)
00761   {
00762     keyval = *temp;
00763     temp++;
00764     if (j == 0U)
00765     {
00766       keyval ^= key_strobe[0];
00767     }
00768     else
00769     {
00770       keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc;
00771     }
00772
00773     crc = 0;
00774     for (i = 0; i < (uint8_t)32; i++)
00775     {
00776       k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31-i))&((uint8_t)0xF)))) & 1U;
00777       crc <<= 1;
00778       if (k != 0U)
00779       {
00780         crc ^= crc7_poly;
00781        }
00782     }
00783
00784     crc^=(uint8_t)0x55;
00785   }
00786
00787   return (uint32_t) crc;
00788 }
00789
00790
00791 /**
00792   * @brief  Enable region deciphering.
00793   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00794   *         the configuration information for OTFDEC module
00795   * @param  RegionIndex index of region the deciphering is enabled
00796   * @note   An error is reported when the configuration is locked.
00797   * @retval HAL state
00798   */
00799 HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
00800 {
00801   OTFDEC_Region_TypeDef * region;
00802   uint32_t address;
00803
00804   /* Check the parameters */
00805   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00806   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00807
00808   /* Take Lock */
00809   __HAL_LOCK(hotfdec);
00810
00811   address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00812   region = (OTFDEC_Region_TypeDef *)address;
00813
00814   if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
00815   {
00816     /* Configuration is locked, REG_EN bit can't be modified */
00817     __HAL_UNLOCK(hotfdec);
00818
00819      return HAL_ERROR;
00820   }
00821
00822   /* Enable region processing */
00823   SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
00824
00825   /* Release Lock */
00826   __HAL_UNLOCK(hotfdec);
00827
00828   /* Status is okay */
00829   return HAL_OK;
00830 }
00831
00832 /**
00833   * @brief  Disable region deciphering.
00834   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00835   *         the configuration information for OTFDEC module
00836   * @param  RegionIndex index of region the deciphering is disabled
00837   * @note   An error is reported when the configuration is locked.
00838   * @retval HAL state
00839   */
00840 HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
00841 {
00842   OTFDEC_Region_TypeDef * region;
00843   uint32_t address;
00844
00845   /* Check the parameters */
00846   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00847   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00848
00849   /* Take Lock */
00850   __HAL_LOCK(hotfdec);
00851
00852   address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00853   region = (OTFDEC_Region_TypeDef *)address;
00854
00855   if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
00856   {
00857     /* Configuration is locked, REG_EN bit can't be modified */
00858     __HAL_UNLOCK(hotfdec);
00859
00860      return HAL_ERROR;
00861   }
00862
00863   /* Disable region processing */
00864   CLEAR_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
00865
00866   /* Release Lock */
00867   __HAL_UNLOCK(hotfdec);
00868
00869   /* Status is okay */
00870   return HAL_OK;
00871 }
00872
00873 /**
00874   * @}
00875   */
00876
00877 /** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
00878  *  @brief   Peripheral State functions.
00879  *
00880 @verbatim
00881   ==============================================================================
00882                       ##### Peripheral State functions #####
00883   ==============================================================================
00884     [..]
00885     This subsection permits to get in run-time the status of the peripheral.
00886
00887 @endverbatim
00888   * @{
00889   */
00890
00891 /**
00892   * @brief  Return the OTFDEC state.
00893   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00894   *         the configuration information for OTFDEC module
00895   * @retval HAL state
00896   */
00897 HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
00898 {
00899   return hotfdec->State;
00900 }
00901
00902
00903 /**
00904   * @brief  Return region keys CRC.
00905   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00906   *         the configuration information for OTFDEC module
00907   * @param  RegionIndex index of region the keys CRC of which is read
00908   * @retval Key CRC
00909   */
00910 uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
00911 {
00912   OTFDEC_Region_TypeDef * region;
00913   uint32_t address;
00914   uint32_t keycrc;
00915
00916   /* Check the parameters */
00917   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00918   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00919
00920   address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00921   region = (OTFDEC_Region_TypeDef *)address;
00922
00923   keycrc = (READ_REG( region->REG_CONFIGR )) & OTFDEC_REG_CONFIGR_KEYCRC;
00924
00925   keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
00926
00927   return keycrc;
00928 }
00929
00930 /**
00931   * @brief  Return region configuration parameters.
00932   * @param  hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
00933   *         the configuration information for OTFDEC module
00934   * @param  RegionIndex index of region the configuration of which is read
00935   * @param  Config pointer on structure that will be filled up with the region configuration parameters
00936   * @retval HAL state
00937   */
00938 HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config)
00939 {
00940   OTFDEC_Region_TypeDef * region;
00941   uint32_t address;
00942
00943   /* Check the parameters */
00944   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
00945   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
00946
00947   if (Config == NULL)
00948   {
00949     return HAL_ERROR;
00950   }
00951   else
00952   {
00953     /* Take Lock */
00954     __HAL_LOCK(hotfdec);
00955
00956     address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
00957     region = (OTFDEC_Region_TypeDef *)address;
00958
00959     /* Read Nonce */
00960     Config->Nonce[0] = READ_REG(region->REG_NONCER0);
00961     Config->Nonce[1] = READ_REG(region->REG_NONCER1);
00962
00963     /* Read Addresses */
00964     Config->StartAddress = READ_REG(region->REG_START_ADDR);
00965     Config->EndAddress = READ_REG(region->REG_END_ADDR);
00966
00967     /* Read Version */
00968     Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
00969
00970     /* Release Lock */
00971     __HAL_UNLOCK(hotfdec);
00972
00973     /* Status is okay */
00974     return HAL_OK;
00975   }
00976 }
00977
00978
00979 /**
00980   * @}
00981   */
00982
00983 /**
00984   * @}
00985   */
00986
00987 #endif /* OTFDEC1 */
00988
00989 #endif /* HAL_OTFDEC_MODULE_ENABLED */
00990
00991
00992 /**
00993   * @}
00994   */
00995
00996 /**
00997   * @}
00998   */
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_otfdec.h Source File

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stm32h7xx_hal_otfdec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_otfdec.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OTFDEC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_HAL_OTFDEC_H
00022 #define __STM32H7xx_HAL_OTFDEC_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 #if defined(OTFDEC1)
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal_def.h"
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup OTFDEC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup OTFDEC_Exported_Types OTFDEC Exported Types
00043   * @{
00044   */
00045
00046 /** @defgroup OTFDEC_Exported_Types_Group1 OTFDEC region configuration definitions
00047   * @{
00048   */
00049
00050 /**
00051   * @brief OTFDEC region configuration structure definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t          Nonce[2];        /*!< OTFDEC region nonce */
00056
00057   uint32_t          StartAddress;    /*!< OTFDEC region start address */
00058
00059   uint32_t          EndAddress;      /*!< OTFDEC region end address */
00060
00061   uint16_t          Version;         /*!< OTFDEC region firmware version */
00062
00063 }OTFDEC_RegionConfigTypeDef;
00064
00065 /**
00066   * @}
00067   */
00068
00069 /** @defgroup OTFDEC_Exported_Types_Group2 OTFDEC Peripheral handle definitions
00070   * @{
00071   */
00072
00073 /**
00074   * @brief OTFDEC states structure definition
00075   */
00076 typedef enum
00077 {
00078   HAL_OTFDEC_STATE_RESET             = 0x00U,  /*!< OTFDEC not yet initialized or disabled */
00079   HAL_OTFDEC_STATE_READY             = 0x01U,  /*!< OTFDEC initialized and ready for use   */
00080   HAL_OTFDEC_STATE_BUSY              = 0x02U,  /*!< OTFDEC internal processing is ongoing  */
00081 }HAL_OTFDEC_StateTypeDef;
00082
00083 /**
00084   * @brief OTFDEC handle structure definition
00085   */
00086 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00087 typedef struct __OTFDEC_HandleTypeDef
00088 #else
00089 typedef struct
00090 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00091 {
00092   OTFDEC_TypeDef             *Instance;  /*!< OTFDEC registers base address */
00093
00094   HAL_OTFDEC_StateTypeDef    State;      /*!< OTFDEC state */
00095
00096   HAL_LockTypeDef            Lock;       /*!< OTFDEC locking object */
00097
00098   __IO uint32_t              ErrorCode;  /*!< OTFDEC error code */
00099
00100 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00101   void (* ErrorCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);     /*!< OTFDEC error callback */
00102
00103   void (* MspInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);   /*!< OTFDEC Msp Init callback */
00104
00105   void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */
00106 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00107
00108 }OTFDEC_HandleTypeDef;
00109
00110 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00111 /**
00112   * @brief  HAL OTFDEC Callback ID enumeration definition
00113   */
00114 typedef enum
00115 {
00116   HAL_OTFDEC_ERROR_CB_ID       = 0x00U,  /*!< OTFDEC error callback ID      */
00117   HAL_OTFDEC_MSPINIT_CB_ID     = 0x01U,  /*!< OTFDEC Msp DeInit callback ID */
00118   HAL_OTFDEC_MSPDEINIT_CB_ID   = 0x02U   /*!< OTFDEC Msp DeInit callback ID */
00119 } HAL_OTFDEC_CallbackIDTypeDef;
00120
00121 /**
00122   * @brief  HAL OTFDEC Callback pointer definition
00123   */
00124 typedef  void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< pointer to a OTFDEC callback function */
00125
00126 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup OTFDEC_Exported_Constants OTFDEC Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup OTFDEC_Interrupts    OTFDEC Interrupts
00142   * @{
00143   */
00144 #define OTFDEC_SEC_ERROR_INT     (OTFDEC_IER_SEIE                                  )  /*!< OTFDEC security error interrupt                  */
00145 #define OTFDEC_EXE_ERROR_INT     (               OTFDEC_IER_XONEIE                 )  /*!< OTFDEC execution error interrupt                 */
00146 #define OTFDEC_KEY_ERROR_INT     (                                  OTFDEC_IER_KEIE)  /*!< OTFDEC key error interrupt                       */
00147 #define OTFDEC_SEC_EXE_ERROR_INT (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE                )  /*!< OTFDEC security and execution errors interrupts  */
00148 #define OTFDEC_SEC_KEY_ERROR_INT (OTFDEC_IER_SEIE|                  OTFDEC_IER_KEIE)  /*!< OTFDEC security and key errors interrupts        */
00149 #define OTFDEC_EXE_KEY_ERROR_INT (                OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC execution and key errors interrupts       */
00150 #define OTFDEC_ALL_INT           (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC all interrupts                            */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup OTFDEC_Region_Enable   OTFDEC Region Enable
00156   * @{
00157   */
00158 #define OTFDEC_REG_CONFIGR_REG_DISABLE   0x00000000U                /*!< OTFDEC region encryption or on-the-fly decryption disable */
00159 #define OTFDEC_REG_CONFIGR_REG_ENABLE    OTFDEC_REG_CONFIGR_REG_EN  /*!< OTFDEC region encryption or on-the-fly decryption enable  */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup OTFDEC_Region_Configuration_Lock    OTFDEC Region Configuration Lock
00165   * @{
00166   */
00167 #define OTFDEC_REG_CONFIGR_LOCK_DISABLE   0x00000000U                     /*!< OTFDEC region configuration lock disable */
00168 #define OTFDEC_REG_CONFIGR_LOCK_ENABLE    OTFDEC_REG_CONFIGR_CONFIGLOCK   /*!< OTFDEC region configuration lock enable  */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup OTFDEC_Region_Operating_Mode    OTFDEC Region Operating Mode
00174   * @{
00175   */
00176 #define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY              0x00000000U                /*!< Only instruction accesses are decrypted                                   */
00177 #define OTFDEC_REG_MODE_DATA_ACCESSES_ONLY                     OTFDEC_REG_CONFIGR_MODE_0  /*!< Only data accesses are decrypted                                          */
00178 #define OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES           OTFDEC_REG_CONFIGR_MODE_1  /*!< All read accesses are decrypted                                           */
00179 #define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER  OTFDEC_REG_CONFIGR_MODE    /*!< Only instruction accesses are decrypted with proprietary cipher activated */
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup OTFDEC_Error_Definition   OTFDEC Error Definition
00185   * @{
00186   */
00187 #define  HAL_OTFDEC_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                         */
00188 #define  HAL_OTFDEC_SECURITY_ERROR         ((uint32_t)0x00000001U)    /*!< Security error                   */
00189 #define  HAL_OTFDEC_EXECUTE_ERROR          ((uint32_t)0x00000002U)    /*!< Execute-only Execute-Never error */
00190 #define  HAL_OTFDEC_KEY_ERROR              ((uint32_t)0x00000004U)    /*!< Key error                        */
00191 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00192 #define HAL_OTFDEC_ERROR_INVALID_CALLBACK  ((uint32_t)0x00000008U)   /*!< Invalid Callback error            */
00193 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup OTFDEC_Regions_Index   OTFDEC Regions Index
00199   * @{
00200   */
00201 #define  OTFDEC_REGION1            ((uint32_t)0x00000000U)    /*!< OTFDEC region 1 */
00202 #define  OTFDEC_REGION2            ((uint32_t)0x00000001U)    /*!< OTFDEC region 2 */
00203 #define  OTFDEC_REGION3            ((uint32_t)0x00000002U)    /*!< OTFDEC region 3 */
00204 #define  OTFDEC_REGION4            ((uint32_t)0x00000003U)    /*!< OTFDEC region 4 */
00205 /**
00206   * @}
00207   */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported macro ------------------------------------------------------------*/
00214 /** @defgroup OTFDEC_Exported_Macros OTFDEC Exported Macros
00215   * @{
00216   */
00217
00218 /** @brief  Reset OTFDEC handle state.
00219   * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
00220   *         the configuration information for OTFDEC module
00221   * @retval None
00222   */
00223 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00224 #define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \
00225   do{                                                                          \
00226     (__HANDLE__)->State = HAL_OTFDEC_STATE_RESET;                              \
00227     (__HANDLE__)->MspInitCallback = NULL;                                      \
00228     (__HANDLE__)->MspDeInitCallback = NULL;                                    \
00229   } while(0)
00230 #else
00231 #define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \
00232   ((__HANDLE__)->State = HAL_OTFDEC_STATE_RESET)
00233 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00234
00235 /**
00236   * @brief  Enable OTFDEC peripheral interrupts combination
00237   * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
00238   *         the configuration information for OTFDEC module
00239   * @param  __INTERRUPT__ mask on enabled interrupts
00240   *          This parameter can be one of the following values:
00241   *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt
00242   *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt
00243   *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt
00244   *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts
00245   *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts
00246   *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts
00247   *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts
00248   * @retval None
00249   */
00250 #define __HAL_OTFDEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
00251
00252 /**
00253   * @brief  Disable OTFDEC peripheral interrupts combination
00254   * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
00255   *         the configuration information for OTFDEC module
00256   * @param  __INTERRUPT__ mask on disabled interrupts
00257   *          This parameter can be one of the following values:
00258   *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt
00259   *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt
00260   *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt
00261   *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts
00262   *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts
00263   *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts
00264   *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts
00265   * @retval None
00266   */
00267 #define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported functions --------------------------------------------------------*/
00274 /** @defgroup OTFDEC_Exported_Functions OTFDEC Exported Functions
00275   * @{
00276   */
00277
00278 /** @addtogroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
00279   * @{
00280   */
00281 HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec);
00282 HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec);
00283 void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec);
00284 void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);
00285
00286 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
00287 /* Callbacks Register/UnRegister functions  ***********************************/
00288 HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
00289                                            pOTFDEC_CallbackTypeDef pCallback);
00290 HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);
00291 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
00292 /**
00293   * @}
00294   */
00295
00296
00297 /** @addtogroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
00298   * @{
00299   */
00300 void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec);
00301 void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec);
00302 /**
00303   * @}
00304   */
00305
00306 /** @addtogroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
00307   * @{
00308   */
00309 HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
00310 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
00311 HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
00312 HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
00313 uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
00314 HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
00315 HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
00316 /**
00317   * @}
00318   */
00319
00320 /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
00321   * @{
00322   */
00323 HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);
00324 uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
00325 HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config);
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /* Private types -------------------------------------------------------------*/
00335 /** @defgroup OTFDEC_Private_Types OTFDEC Private Types
00336   * @{
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Private variables ---------------------------------------------------------*/
00344 /** @defgroup OTFDEC_Private_Variables OTFDEC Private Variables
00345   * @{
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /* Private constants ---------------------------------------------------------*/
00353 /** @defgroup OTFDEC_Private_Constants OTFDEC Private Constants
00354   * @{
00355   */
00356 /**
00357   * @}
00358   */
00359
00360 /* Private macros ------------------------------------------------------------*/
00361 /** @defgroup OTFDEC_Private_Macros OTFDEC Private Macros
00362   * @{
00363   */
00364
00365 /**
00366   * @brief Verify the OTFDEC peripheral interrupts parameter.
00367   * @param __INT__ OTFDEC peripheral set of interrupts parameter
00368   * @retval SET (__INT__ is valid) or RESET (__INT__ is invalid)
00369   */
00370 #define IS_OTFDEC_INTERRUPTS(__INT__) (((__INT__) == OTFDEC_SEC_ERROR_INT)     || \
00371                                        ((__INT__) == OTFDEC_EXE_ERROR_INT)     || \
00372                                        ((__INT__) == OTFDEC_KEY_ERROR_INT)     || \
00373                                        ((__INT__) == OTFDEC_SEC_EXE_ERROR_INT) || \
00374                                        ((__INT__) == OTFDEC_SEC_KEY_ERROR_INT) || \
00375                                        ((__INT__) == OTFDEC_EXE_KEY_ERROR_INT) || \
00376                                        ((__INT__) == OTFDEC_ALL_INT)  )
00377
00378 /**
00379   * @brief Verify the OTFDEC region configuration lock parameter.
00380   * @param __LOCK__ OTFDEC region lock parameter.
00381   * @retval SET (__LOCK__ is valid) or RESET (__LOCK__ is invalid)
00382   */
00383 #define IS_OTFDEC_REGION_CONFIG_LOCK(__LOCK__) (((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_DISABLE) || \
00384                                                 ((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)  )
00385
00386 /**
00387   * @brief Verify the OTFDEC region operating mode.
00388   * @param __MODE__ OTFDEC region operating mode parameter.
00389   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00390   */
00391 #define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY)    || \
00392                                                    ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY)           || \
00393                                                    ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
00394                                                    ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
00395
00396 /**
00397   * @brief Verify the OTFDEC region index.
00398   * @param __INDEX__ OTFDEC region index
00399   * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid)
00400   */
00401 #define IS_OTFDEC_REGIONINDEX(__INDEX__) (((__INDEX__) == OTFDEC_REGION1)     || \
00402                                           ((__INDEX__) == OTFDEC_REGION2)     || \
00403                                           ((__INDEX__) == OTFDEC_REGION3)     || \
00404                                           ((__INDEX__) == OTFDEC_REGION4)  )
00405
00406 /**
00407   * @brief Verify the OTFDEC configuration attributes.
00408   * @param __ATTRIBUTE__ OTFDEC region index
00409   * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid)
00410   */
00411 #define IS_OTFDEC_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_PRIV)   || \
00412                                             ((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_NPRIV)  )
00413
00414 /**
00415   * @}
00416   */
00417
00418 /* Private functions ---------------------------------------------------------*/
00419 /** @defgroup OTFDEC_Private_Functions OTFDEC Private Functions
00420   * @{
00421   */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /**
00428   * @}
00429   */
00430
00431
00432 /**
00433   * @}
00434   */
00435 #endif /* OTFDEC1 */
00436
00437 #ifdef __cplusplus
00438 }
00439 #endif
00440
00441 #endif /* __STM32H7xx_HAL_OTFDEC_H */
00442
00443 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00444
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd.c Source File

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stm32h7xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @brief   PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The PCD HAL driver can be used as follows:
00019
00020      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00021          PCD_HandleTypeDef  hpcd;
00022
00023      (#) Fill parameters of Init structure in HCD handle
00024
00025      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00026
00027      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00028          (##) Enable the PCD/USB Low Level interface clock using
00029               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00030               (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00031
00032          (##) Initialize the related GPIO clocks
00033          (##) Configure PCD pin-out
00034          (##) Configure PCD NVIC interrupt
00035
00036      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00037          (##) hpcd.pData = pdev;
00038
00039      (#)Enable PCD transmission and reception:
00040          (##) HAL_PCD_Start();
00041
00042   @endverbatim
00043   ******************************************************************************
00044   * @attention
00045   *
00046   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00047   * All rights reserved.</center></h2>
00048   *
00049   * This software component is licensed by ST under BSD 3-Clause license,
00050   * the "License"; You may not use this file except in compliance with the
00051   * License. You may obtain a copy of the License at:
00052   *                        opensource.org/licenses/BSD-3-Clause
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32h7xx_hal.h"
00059
00060 /** @addtogroup STM32H7xx_HAL_Driver
00061   * @{
00062   */
00063
00064 /** @defgroup PCD PCD
00065   * @brief PCD HAL module driver
00066   * @{
00067   */
00068
00069 #ifdef HAL_PCD_MODULE_ENABLED
00070
00071 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00072
00073 /* Private types -------------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075 /* Private constants ---------------------------------------------------------*/
00076 /* Private macros ------------------------------------------------------------*/
00077 /** @defgroup PCD_Private_Macros PCD Private Macros
00078   * @{
00079   */
00080 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00081 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00082 /**
00083   * @}
00084   */
00085
00086 /* Private functions prototypes ----------------------------------------------*/
00087 /** @defgroup PCD_Private_Functions PCD Private Functions
00088   * @{
00089   */
00090 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00091 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00092 static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00093 static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00094 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported functions --------------------------------------------------------*/
00100 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00101   * @{
00102   */
00103
00104 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00105  *  @brief    Initialization and Configuration functions
00106  *
00107 @verbatim
00108  ===============================================================================
00109             ##### Initialization and de-initialization functions #####
00110  ===============================================================================
00111     [..]  This section provides functions allowing to:
00112
00113 @endverbatim
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Initializes the PCD according to the specified
00119   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00120   * @param  hpcd PCD handle
00121   * @retval HAL status
00122   */
00123 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00124 {
00125   USB_OTG_GlobalTypeDef *USBx;
00126   uint8_t i;
00127
00128   /* Check the PCD handle allocation */
00129   if (hpcd == NULL)
00130   {
00131     return HAL_ERROR;
00132   }
00133
00134   /* Check the parameters */
00135   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00136
00137   USBx = hpcd->Instance;
00138
00139   if (hpcd->State == HAL_PCD_STATE_RESET)
00140   {
00141     /* Allocate lock resource and initialize it */
00142     hpcd->Lock = HAL_UNLOCKED;
00143
00144 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00145     hpcd->SOFCallback = HAL_PCD_SOFCallback;
00146     hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00147     hpcd->ResetCallback = HAL_PCD_ResetCallback;
00148     hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00149     hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00150     hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00151     hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00152     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
00153     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
00154     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
00155     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
00156     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
00157     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
00158
00159     if (hpcd->MspInitCallback == NULL)
00160     {
00161       hpcd->MspInitCallback = HAL_PCD_MspInit;
00162     }
00163
00164     /* Init the low level hardware */
00165     hpcd->MspInitCallback(hpcd);
00166 #else
00167     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00168     HAL_PCD_MspInit(hpcd);
00169 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
00170   }
00171
00172   hpcd->State = HAL_PCD_STATE_BUSY;
00173
00174   /* Disable DMA mode for FS instance */
00175   if ((USBx->CID & (0x1U << 8)) == 0U)
00176   {
00177     hpcd->Init.dma_enable = 0U;
00178   }
00179
00180   /* Disable the Interrupts */
00181   __HAL_PCD_DISABLE(hpcd);
00182
00183   /*Init the Core (common init.) */
00184   if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
00185   {
00186     hpcd->State = HAL_PCD_STATE_ERROR;
00187     return HAL_ERROR;
00188   }
00189
00190   /* Force Device Mode*/
00191   (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
00192
00193   /* Init endpoints structures */
00194   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00195   {
00196     /* Init ep structure */
00197     hpcd->IN_ep[i].is_in = 1U;
00198     hpcd->IN_ep[i].num = i;
00199     hpcd->IN_ep[i].tx_fifo_num = i;
00200     /* Control until ep is activated */
00201     hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00202     hpcd->IN_ep[i].maxpacket = 0U;
00203     hpcd->IN_ep[i].xfer_buff = 0U;
00204     hpcd->IN_ep[i].xfer_len = 0U;
00205   }
00206
00207   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00208   {
00209     hpcd->OUT_ep[i].is_in = 0U;
00210     hpcd->OUT_ep[i].num = i;
00211     /* Control until ep is activated */
00212     hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00213     hpcd->OUT_ep[i].maxpacket = 0U;
00214     hpcd->OUT_ep[i].xfer_buff = 0U;
00215     hpcd->OUT_ep[i].xfer_len = 0U;
00216   }
00217
00218   /* Init Device */
00219   if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
00220   {
00221     hpcd->State = HAL_PCD_STATE_ERROR;
00222     return HAL_ERROR;
00223   }
00224
00225   hpcd->USB_Address = 0U;
00226   hpcd->State = HAL_PCD_STATE_READY;
00227
00228   /* Activate LPM */
00229   if (hpcd->Init.lpm_enable == 1U)
00230   {
00231     (void)HAL_PCDEx_ActivateLPM(hpcd);
00232   }
00233
00234   (void)USB_DevDisconnect(hpcd->Instance);
00235
00236   return HAL_OK;
00237 }
00238
00239 /**
00240   * @brief  DeInitializes the PCD peripheral.
00241   * @param  hpcd PCD handle
00242   * @retval HAL status
00243   */
00244 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00245 {
00246   /* Check the PCD handle allocation */
00247   if (hpcd == NULL)
00248   {
00249     return HAL_ERROR;
00250   }
00251
00252   hpcd->State = HAL_PCD_STATE_BUSY;
00253
00254   /* Stop Device */
00255   (void)HAL_PCD_Stop(hpcd);
00256
00257 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00258   if (hpcd->MspDeInitCallback == NULL)
00259   {
00260     hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
00261   }
00262
00263   /* DeInit the low level hardware */
00264   hpcd->MspDeInitCallback(hpcd);
00265 #else
00266   /* DeInit the low level hardware: CLOCK, NVIC.*/
00267   HAL_PCD_MspDeInit(hpcd);
00268 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00269
00270   hpcd->State = HAL_PCD_STATE_RESET;
00271
00272   return HAL_OK;
00273 }
00274
00275 /**
00276   * @brief  Initializes the PCD MSP.
00277   * @param  hpcd PCD handle
00278   * @retval None
00279   */
00280 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(hpcd);
00284
00285   /* NOTE : This function should not be modified, when the callback is needed,
00286             the HAL_PCD_MspInit could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @brief  DeInitializes PCD MSP.
00292   * @param  hpcd PCD handle
00293   * @retval None
00294   */
00295 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00296 {
00297   /* Prevent unused argument(s) compilation warning */
00298   UNUSED(hpcd);
00299
00300   /* NOTE : This function should not be modified, when the callback is needed,
00301             the HAL_PCD_MspDeInit could be implemented in the user file
00302    */
00303 }
00304
00305 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00306 /**
00307   * @brief  Register a User USB PCD Callback
00308   *         To be used instead of the weak predefined callback
00309   * @param  hpcd USB PCD handle
00310   * @param  CallbackID ID of the callback to be registered
00311   *         This parameter can be one of the following values:
00312   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00313   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00314   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00315   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00316   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00317   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00318   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00319   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00320   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00321   * @param  pCallback pointer to the Callback function
00322   * @retval HAL status
00323   */
00324 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
00325 {
00326   HAL_StatusTypeDef status = HAL_OK;
00327
00328   if (pCallback == NULL)
00329   {
00330     /* Update the error code */
00331     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00332     return HAL_ERROR;
00333   }
00334   /* Process locked */
00335   __HAL_LOCK(hpcd);
00336
00337   if (hpcd->State == HAL_PCD_STATE_READY)
00338   {
00339     switch (CallbackID)
00340     {
00341       case HAL_PCD_SOF_CB_ID :
00342         hpcd->SOFCallback = pCallback;
00343         break;
00344
00345       case HAL_PCD_SETUPSTAGE_CB_ID :
00346         hpcd->SetupStageCallback = pCallback;
00347         break;
00348
00349       case HAL_PCD_RESET_CB_ID :
00350         hpcd->ResetCallback = pCallback;
00351         break;
00352
00353       case HAL_PCD_SUSPEND_CB_ID :
00354         hpcd->SuspendCallback = pCallback;
00355         break;
00356
00357       case HAL_PCD_RESUME_CB_ID :
00358         hpcd->ResumeCallback = pCallback;
00359         break;
00360
00361       case HAL_PCD_CONNECT_CB_ID :
00362         hpcd->ConnectCallback = pCallback;
00363         break;
00364
00365       case HAL_PCD_DISCONNECT_CB_ID :
00366         hpcd->DisconnectCallback = pCallback;
00367         break;
00368
00369       case HAL_PCD_MSPINIT_CB_ID :
00370         hpcd->MspInitCallback = pCallback;
00371         break;
00372
00373       case HAL_PCD_MSPDEINIT_CB_ID :
00374         hpcd->MspDeInitCallback = pCallback;
00375         break;
00376
00377       default :
00378         /* Update the error code */
00379         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00380         /* Return error status */
00381         status =  HAL_ERROR;
00382         break;
00383     }
00384   }
00385   else if (hpcd->State == HAL_PCD_STATE_RESET)
00386   {
00387     switch (CallbackID)
00388     {
00389       case HAL_PCD_MSPINIT_CB_ID :
00390         hpcd->MspInitCallback = pCallback;
00391         break;
00392
00393       case HAL_PCD_MSPDEINIT_CB_ID :
00394         hpcd->MspDeInitCallback = pCallback;
00395         break;
00396
00397       default :
00398         /* Update the error code */
00399         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00400         /* Return error status */
00401         status =  HAL_ERROR;
00402         break;
00403     }
00404   }
00405   else
00406   {
00407     /* Update the error code */
00408     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00409     /* Return error status */
00410     status =  HAL_ERROR;
00411   }
00412
00413   /* Release Lock */
00414   __HAL_UNLOCK(hpcd);
00415   return status;
00416 }
00417
00418 /**
00419   * @brief  Unregister an USB PCD Callback
00420   *         USB PCD callabck is redirected to the weak predefined callback
00421   * @param  hpcd USB PCD handle
00422   * @param  CallbackID ID of the callback to be unregistered
00423   *         This parameter can be one of the following values:
00424   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00425   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00426   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00427   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00428   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00429   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00430   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00431   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00432   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00433   * @retval HAL status
00434   */
00435 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
00436 {
00437   HAL_StatusTypeDef status = HAL_OK;
00438
00439   /* Process locked */
00440   __HAL_LOCK(hpcd);
00441
00442   /* Setup Legacy weak Callbacks  */
00443   if (hpcd->State == HAL_PCD_STATE_READY)
00444   {
00445     switch (CallbackID)
00446     {
00447       case HAL_PCD_SOF_CB_ID :
00448         hpcd->SOFCallback = HAL_PCD_SOFCallback;
00449         break;
00450
00451       case HAL_PCD_SETUPSTAGE_CB_ID :
00452         hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00453         break;
00454
00455       case HAL_PCD_RESET_CB_ID :
00456         hpcd->ResetCallback = HAL_PCD_ResetCallback;
00457         break;
00458
00459       case HAL_PCD_SUSPEND_CB_ID :
00460         hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00461         break;
00462
00463       case HAL_PCD_RESUME_CB_ID :
00464         hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00465         break;
00466
00467       case HAL_PCD_CONNECT_CB_ID :
00468         hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00469         break;
00470
00471       case HAL_PCD_DISCONNECT_CB_ID :
00472         hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00473         break;
00474
00475       case HAL_PCD_MSPINIT_CB_ID :
00476         hpcd->MspInitCallback = HAL_PCD_MspInit;
00477         break;
00478
00479       case HAL_PCD_MSPDEINIT_CB_ID :
00480         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00481         break;
00482
00483       default :
00484         /* Update the error code */
00485         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00486
00487         /* Return error status */
00488         status =  HAL_ERROR;
00489         break;
00490     }
00491   }
00492   else if (hpcd->State == HAL_PCD_STATE_RESET)
00493   {
00494     switch (CallbackID)
00495     {
00496       case HAL_PCD_MSPINIT_CB_ID :
00497         hpcd->MspInitCallback = HAL_PCD_MspInit;
00498         break;
00499
00500       case HAL_PCD_MSPDEINIT_CB_ID :
00501         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00502         break;
00503
00504       default :
00505         /* Update the error code */
00506         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00507
00508         /* Return error status */
00509         status =  HAL_ERROR;
00510         break;
00511     }
00512   }
00513   else
00514   {
00515     /* Update the error code */
00516     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00517
00518     /* Return error status */
00519     status =  HAL_ERROR;
00520   }
00521
00522   /* Release Lock */
00523   __HAL_UNLOCK(hpcd);
00524   return status;
00525 }
00526
00527 /**
00528   * @brief  Register USB PCD Data OUT Stage Callback
00529   *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
00530   * @param  hpcd PCD handle
00531   * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
00535 {
00536   HAL_StatusTypeDef status = HAL_OK;
00537
00538   if (pCallback == NULL)
00539   {
00540     /* Update the error code */
00541     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00542
00543     return HAL_ERROR;
00544   }
00545
00546   /* Process locked */
00547   __HAL_LOCK(hpcd);
00548
00549   if (hpcd->State == HAL_PCD_STATE_READY)
00550   {
00551     hpcd->DataOutStageCallback = pCallback;
00552   }
00553   else
00554   {
00555     /* Update the error code */
00556     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00557
00558     /* Return error status */
00559     status =  HAL_ERROR;
00560   }
00561
00562   /* Release Lock */
00563   __HAL_UNLOCK(hpcd);
00564
00565   return status;
00566 }
00567
00568 /**
00569   * @brief  UnRegister the USB PCD Data OUT Stage Callback
00570   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
00571   * @param  hpcd PCD handle
00572   * @retval HAL status
00573   */
00574 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
00575 {
00576   HAL_StatusTypeDef status = HAL_OK;
00577
00578   /* Process locked */
00579   __HAL_LOCK(hpcd);
00580
00581   if (hpcd->State == HAL_PCD_STATE_READY)
00582   {
00583     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
00584   }
00585   else
00586   {
00587     /* Update the error code */
00588     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00589
00590     /* Return error status */
00591     status =  HAL_ERROR;
00592   }
00593
00594   /* Release Lock */
00595   __HAL_UNLOCK(hpcd);
00596
00597   return status;
00598 }
00599
00600 /**
00601   * @brief  Register USB PCD Data IN Stage Callback
00602   *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
00603   * @param  hpcd PCD handle
00604   * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
00605   * @retval HAL status
00606   */
00607 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
00608 {
00609   HAL_StatusTypeDef status = HAL_OK;
00610
00611   if (pCallback == NULL)
00612   {
00613     /* Update the error code */
00614     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00615
00616     return HAL_ERROR;
00617   }
00618
00619   /* Process locked */
00620   __HAL_LOCK(hpcd);
00621
00622   if (hpcd->State == HAL_PCD_STATE_READY)
00623   {
00624     hpcd->DataInStageCallback = pCallback;
00625   }
00626   else
00627   {
00628     /* Update the error code */
00629     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00630
00631     /* Return error status */
00632     status =  HAL_ERROR;
00633   }
00634
00635   /* Release Lock */
00636   __HAL_UNLOCK(hpcd);
00637
00638   return status;
00639 }
00640
00641 /**
00642   * @brief  UnRegister the USB PCD Data IN Stage Callback
00643   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
00644   * @param  hpcd PCD handle
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
00648 {
00649   HAL_StatusTypeDef status = HAL_OK;
00650
00651   /* Process locked */
00652   __HAL_LOCK(hpcd);
00653
00654   if (hpcd->State == HAL_PCD_STATE_READY)
00655   {
00656     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
00657   }
00658   else
00659   {
00660     /* Update the error code */
00661     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00662
00663     /* Return error status */
00664     status =  HAL_ERROR;
00665   }
00666
00667   /* Release Lock */
00668   __HAL_UNLOCK(hpcd);
00669
00670   return status;
00671 }
00672
00673 /**
00674   * @brief  Register USB PCD Iso OUT incomplete Callback
00675   *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00676   * @param  hpcd PCD handle
00677   * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
00678   * @retval HAL status
00679   */
00680 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
00681 {
00682   HAL_StatusTypeDef status = HAL_OK;
00683
00684   if (pCallback == NULL)
00685   {
00686     /* Update the error code */
00687     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00688
00689     return HAL_ERROR;
00690   }
00691
00692   /* Process locked */
00693   __HAL_LOCK(hpcd);
00694
00695   if (hpcd->State == HAL_PCD_STATE_READY)
00696   {
00697     hpcd->ISOOUTIncompleteCallback = pCallback;
00698   }
00699   else
00700   {
00701     /* Update the error code */
00702     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00703
00704     /* Return error status */
00705     status =  HAL_ERROR;
00706   }
00707
00708   /* Release Lock */
00709   __HAL_UNLOCK(hpcd);
00710
00711   return status;
00712 }
00713
00714 /**
00715   * @brief  UnRegister the USB PCD Iso OUT incomplete Callback
00716   *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00717   * @param  hpcd PCD handle
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
00721 {
00722   HAL_StatusTypeDef status = HAL_OK;
00723
00724   /* Process locked */
00725   __HAL_LOCK(hpcd);
00726
00727   if (hpcd->State == HAL_PCD_STATE_READY)
00728   {
00729     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
00730   }
00731   else
00732   {
00733     /* Update the error code */
00734     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00735
00736     /* Return error status */
00737     status =  HAL_ERROR;
00738   }
00739
00740   /* Release Lock */
00741   __HAL_UNLOCK(hpcd);
00742
00743   return status;
00744 }
00745
00746 /**
00747   * @brief  Register USB PCD Iso IN incomplete Callback
00748   *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00749   * @param  hpcd PCD handle
00750   * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
00754 {
00755   HAL_StatusTypeDef status = HAL_OK;
00756
00757   if (pCallback == NULL)
00758   {
00759     /* Update the error code */
00760     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00761
00762     return HAL_ERROR;
00763   }
00764
00765   /* Process locked */
00766   __HAL_LOCK(hpcd);
00767
00768   if (hpcd->State == HAL_PCD_STATE_READY)
00769   {
00770     hpcd->ISOINIncompleteCallback = pCallback;
00771   }
00772   else
00773   {
00774     /* Update the error code */
00775     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00776
00777     /* Return error status */
00778     status =  HAL_ERROR;
00779   }
00780
00781   /* Release Lock */
00782   __HAL_UNLOCK(hpcd);
00783
00784   return status;
00785 }
00786
00787 /**
00788   * @brief  UnRegister the USB PCD Iso IN incomplete Callback
00789   *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00790   * @param  hpcd PCD handle
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
00794 {
00795   HAL_StatusTypeDef status = HAL_OK;
00796
00797   /* Process locked */
00798   __HAL_LOCK(hpcd);
00799
00800   if (hpcd->State == HAL_PCD_STATE_READY)
00801   {
00802     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
00803   }
00804   else
00805   {
00806     /* Update the error code */
00807     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00808
00809     /* Return error status */
00810     status =  HAL_ERROR;
00811   }
00812
00813   /* Release Lock */
00814   __HAL_UNLOCK(hpcd);
00815
00816   return status;
00817 }
00818
00819 /**
00820   * @brief  Register USB PCD BCD Callback
00821   *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
00822   * @param  hpcd PCD handle
00823   * @param  pCallback pointer to the USB PCD BCD Callback function
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
00827 {
00828   HAL_StatusTypeDef status = HAL_OK;
00829
00830   if (pCallback == NULL)
00831   {
00832     /* Update the error code */
00833     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00834
00835     return HAL_ERROR;
00836   }
00837
00838   /* Process locked */
00839   __HAL_LOCK(hpcd);
00840
00841   if (hpcd->State == HAL_PCD_STATE_READY)
00842   {
00843     hpcd->BCDCallback = pCallback;
00844   }
00845   else
00846   {
00847     /* Update the error code */
00848     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00849
00850     /* Return error status */
00851     status =  HAL_ERROR;
00852   }
00853
00854   /* Release Lock */
00855   __HAL_UNLOCK(hpcd);
00856
00857   return status;
00858 }
00859
00860 /**
00861   * @brief  UnRegister the USB PCD BCD Callback
00862   *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
00863   * @param  hpcd PCD handle
00864   * @retval HAL status
00865   */
00866 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
00867 {
00868   HAL_StatusTypeDef status = HAL_OK;
00869
00870   /* Process locked */
00871   __HAL_LOCK(hpcd);
00872
00873   if (hpcd->State == HAL_PCD_STATE_READY)
00874   {
00875     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
00876   }
00877   else
00878   {
00879     /* Update the error code */
00880     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00881
00882     /* Return error status */
00883     status =  HAL_ERROR;
00884   }
00885
00886   /* Release Lock */
00887   __HAL_UNLOCK(hpcd);
00888
00889   return status;
00890 }
00891
00892 /**
00893   * @brief  Register USB PCD LPM Callback
00894   *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
00895   * @param  hpcd PCD handle
00896   * @param  pCallback pointer to the USB PCD LPM Callback function
00897   * @retval HAL status
00898   */
00899 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
00900 {
00901   HAL_StatusTypeDef status = HAL_OK;
00902
00903   if (pCallback == NULL)
00904   {
00905     /* Update the error code */
00906     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00907
00908     return HAL_ERROR;
00909   }
00910
00911   /* Process locked */
00912   __HAL_LOCK(hpcd);
00913
00914   if (hpcd->State == HAL_PCD_STATE_READY)
00915   {
00916     hpcd->LPMCallback = pCallback;
00917   }
00918   else
00919   {
00920     /* Update the error code */
00921     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00922
00923     /* Return error status */
00924     status =  HAL_ERROR;
00925   }
00926
00927   /* Release Lock */
00928   __HAL_UNLOCK(hpcd);
00929
00930   return status;
00931 }
00932
00933 /**
00934   * @brief  UnRegister the USB PCD LPM Callback
00935   *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
00936   * @param  hpcd PCD handle
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
00940 {
00941   HAL_StatusTypeDef status = HAL_OK;
00942
00943   /* Process locked */
00944   __HAL_LOCK(hpcd);
00945
00946   if (hpcd->State == HAL_PCD_STATE_READY)
00947   {
00948     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
00949   }
00950   else
00951   {
00952     /* Update the error code */
00953     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00954
00955     /* Return error status */
00956     status =  HAL_ERROR;
00957   }
00958
00959   /* Release Lock */
00960   __HAL_UNLOCK(hpcd);
00961
00962   return status;
00963 }
00964 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00965
00966 /**
00967   * @}
00968   */
00969
00970 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00971  *  @brief   Data transfers functions
00972  *
00973 @verbatim
00974  ===============================================================================
00975                       ##### IO operation functions #####
00976  ===============================================================================
00977     [..]
00978     This subsection provides a set of functions allowing to manage the PCD data
00979     transfers.
00980
00981 @endverbatim
00982   * @{
00983   */
00984
00985 /**
00986   * @brief  Start the USB device
00987   * @param  hpcd PCD handle
00988   * @retval HAL status
00989   */
00990 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00991 {
00992 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00993   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00994 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00995
00996   __HAL_LOCK(hpcd);
00997 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00998   if ((hpcd->Init.battery_charging_enable == 1U) &&
00999       (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
01000   {
01001     /* Enable USB Transceiver */
01002     USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
01003   }
01004 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
01005   (void)USB_DevConnect(hpcd->Instance);
01006   __HAL_PCD_ENABLE(hpcd);
01007   __HAL_UNLOCK(hpcd);
01008   return HAL_OK;
01009 }
01010
01011 /**
01012   * @brief  Stop the USB device.
01013   * @param  hpcd PCD handle
01014   * @retval HAL status
01015   */
01016 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
01017 {
01018   __HAL_LOCK(hpcd);
01019   __HAL_PCD_DISABLE(hpcd);
01020
01021   if (USB_StopDevice(hpcd->Instance) != HAL_OK)
01022   {
01023     __HAL_UNLOCK(hpcd);
01024     return HAL_ERROR;
01025   }
01026
01027   (void)USB_DevDisconnect(hpcd->Instance);
01028   __HAL_UNLOCK(hpcd);
01029
01030   return HAL_OK;
01031 }
01032 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
01033 /**
01034   * @brief  Handles PCD interrupt request.
01035   * @param  hpcd PCD handle
01036   * @retval HAL status
01037   */
01038 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
01039 {
01040   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01041   uint32_t USBx_BASE = (uint32_t)USBx;
01042   uint32_t i, ep_intr, epint, epnum;
01043   uint32_t fifoemptymsk, temp;
01044   USB_OTG_EPTypeDef *ep;
01045
01046   /* ensure that we are in device mode */
01047   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
01048   {
01049     /* avoid spurious interrupt */
01050     if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
01051     {
01052       return;
01053     }
01054
01055     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
01056     {
01057       /* incorrect mode, acknowledge the interrupt */
01058       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
01059     }
01060
01061      /* Handle RxQLevel Interrupt */
01062     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
01063     {
01064       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
01065
01066       temp = USBx->GRXSTSP;
01067
01068       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
01069
01070       if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
01071       {
01072         if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
01073         {
01074           (void)USB_ReadPacket(USBx, ep->xfer_buff,
01075                                (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
01076
01077           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
01078           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
01079         }
01080       }
01081       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
01082       {
01083         (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
01084         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
01085       }
01086       else
01087       {
01088         /* ... */
01089       }
01090       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
01091     }
01092
01093     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
01094     {
01095       epnum = 0U;
01096
01097       /* Read in the device interrupt bits */
01098       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
01099
01100       while (ep_intr != 0U)
01101       {
01102         if ((ep_intr & 0x1U) != 0U)
01103         {
01104           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
01105
01106           if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
01107           {
01108             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
01109             (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
01110           }
01111
01112           if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
01113           {
01114             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
01115             /* Class B setup phase done for previous decoded setup */
01116             (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
01117           }
01118
01119           if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
01120           {
01121             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
01122           }
01123
01124           /* Clear Status Phase Received interrupt */
01125           if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
01126           {
01127             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
01128           }
01129
01130           /* Clear OUT NAK interrupt */
01131           if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
01132           {
01133             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
01134           }
01135         }
01136         epnum++;
01137         ep_intr >>= 1U;
01138       }
01139     }
01140
01141     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
01142     {
01143       /* Read in the device interrupt bits */
01144       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
01145
01146       epnum = 0U;
01147
01148       while (ep_intr != 0U)
01149       {
01150         if ((ep_intr & 0x1U) != 0U) /* In ITR */
01151         {
01152           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
01153
01154           if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
01155           {
01156             fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
01157             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01158
01159             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
01160
01161             if (hpcd->Init.dma_enable == 1U)
01162             {
01163               hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
01164
01165               /* this is ZLP, so prepare EP0 for next setup */
01166               if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
01167               {
01168                 /* prepare to rx more setup packets */
01169                 (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
01170               }
01171             }
01172
01173 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01174             hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
01175 #else
01176             HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
01177 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01178           }
01179           if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
01180           {
01181             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
01182           }
01183           if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
01184           {
01185             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
01186           }
01187           if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
01188           {
01189             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
01190           }
01191           if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
01192           {
01193             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
01194           }
01195           if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
01196           {
01197             (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
01198           }
01199         }
01200         epnum++;
01201         ep_intr >>= 1U;
01202       }
01203     }
01204
01205     /* Handle Resume Interrupt */
01206     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
01207     {
01208       /* Clear the Remote Wake-up Signaling */
01209       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
01210
01211       if (hpcd->LPM_State == LPM_L1)
01212       {
01213         hpcd->LPM_State = LPM_L0;
01214
01215 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01216         hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
01217 #else
01218         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
01219 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01220       }
01221       else
01222       {
01223 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01224         hpcd->ResumeCallback(hpcd);
01225 #else
01226         HAL_PCD_ResumeCallback(hpcd);
01227 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01228       }
01229
01230       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
01231     }
01232
01233     /* Handle Suspend Interrupt */
01234     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
01235     {
01236       if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
01237       {
01238 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01239         hpcd->SuspendCallback(hpcd);
01240 #else
01241         HAL_PCD_SuspendCallback(hpcd);
01242 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01243       }
01244       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
01245     }
01246
01247     /* Handle LPM Interrupt */
01248     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
01249     {
01250       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
01251
01252       if (hpcd->LPM_State == LPM_L0)
01253       {
01254         hpcd->LPM_State = LPM_L1;
01255         hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
01256
01257 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01258         hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
01259 #else
01260         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
01261 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01262       }
01263       else
01264       {
01265 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01266         hpcd->SuspendCallback(hpcd);
01267 #else
01268         HAL_PCD_SuspendCallback(hpcd);
01269 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01270       }
01271     }
01272
01273     /* Handle Reset Interrupt */
01274     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
01275     {
01276       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
01277       (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
01278
01279       for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
01280       {
01281         USBx_INEP(i)->DIEPINT = 0xFB7FU;
01282         USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
01283         USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
01284         USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
01285         USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
01286         USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
01287       }
01288       USBx_DEVICE->DAINTMSK |= 0x10001U;
01289
01290       if (hpcd->Init.use_dedicated_ep1 != 0U)
01291       {
01292         USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
01293                                    USB_OTG_DOEPMSK_XFRCM |
01294                                    USB_OTG_DOEPMSK_EPDM;
01295
01296         USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
01297                                   USB_OTG_DIEPMSK_XFRCM |
01298                                   USB_OTG_DIEPMSK_EPDM;
01299       }
01300       else
01301       {
01302         USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
01303                                 USB_OTG_DOEPMSK_XFRCM |
01304                                 USB_OTG_DOEPMSK_EPDM |
01305                                 USB_OTG_DOEPMSK_OTEPSPRM |
01306                                 USB_OTG_DOEPMSK_NAKM;
01307
01308         USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
01309                                 USB_OTG_DIEPMSK_XFRCM |
01310                                 USB_OTG_DIEPMSK_EPDM;
01311       }
01312
01313       /* Set Default Address to 0 */
01314       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
01315
01316       /* setup EP0 to receive SETUP packets */
01317       (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
01318                              (uint8_t *)hpcd->Setup);
01319
01320       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
01321     }
01322
01323     /* Handle Enumeration done Interrupt */
01324     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
01325     {
01326       (void)USB_ActivateSetup(hpcd->Instance);
01327       hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
01328
01329       /* Set USB Turnaround time */
01330       (void)USB_SetTurnaroundTime(hpcd->Instance,
01331                                   HAL_RCC_GetHCLKFreq(),
01332                                   (uint8_t)hpcd->Init.speed);
01333
01334 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01335       hpcd->ResetCallback(hpcd);
01336 #else
01337       HAL_PCD_ResetCallback(hpcd);
01338 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01339
01340       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
01341     }
01342
01343     /* Handle SOF Interrupt */
01344     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
01345     {
01346 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01347       hpcd->SOFCallback(hpcd);
01348 #else
01349       HAL_PCD_SOFCallback(hpcd);
01350 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01351
01352       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
01353     }
01354
01355     /* Handle Incomplete ISO IN Interrupt */
01356     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
01357     {
01358       /* Keep application checking the corresponding Iso IN endpoint
01359       causing the incomplete Interrupt */
01360       epnum = 0U;
01361
01362 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01363       hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
01364 #else
01365       HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
01366 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01367
01368       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
01369     }
01370
01371     /* Handle Incomplete ISO OUT Interrupt */
01372     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
01373     {
01374       /* Keep application checking the corresponding Iso OUT endpoint
01375       causing the incomplete Interrupt */
01376       epnum = 0U;
01377
01378 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01379       hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
01380 #else
01381       HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
01382 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01383
01384       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
01385     }
01386
01387     /* Handle Connection event Interrupt */
01388     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
01389     {
01390 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01391       hpcd->ConnectCallback(hpcd);
01392 #else
01393       HAL_PCD_ConnectCallback(hpcd);
01394 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01395
01396       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
01397     }
01398
01399     /* Handle Disconnection event Interrupt */
01400     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
01401     {
01402       temp = hpcd->Instance->GOTGINT;
01403
01404       if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
01405       {
01406 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01407         hpcd->DisconnectCallback(hpcd);
01408 #else
01409         HAL_PCD_DisconnectCallback(hpcd);
01410 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01411       }
01412       hpcd->Instance->GOTGINT |= temp;
01413     }
01414   }
01415 }
01416 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
01417
01418
01419 /**
01420   * @brief  Data OUT stage callback.
01421   * @param  hpcd PCD handle
01422   * @param  epnum endpoint number
01423   * @retval None
01424   */
01425 __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01426 {
01427   /* Prevent unused argument(s) compilation warning */
01428   UNUSED(hpcd);
01429   UNUSED(epnum);
01430
01431   /* NOTE : This function should not be modified, when the callback is needed,
01432             the HAL_PCD_DataOutStageCallback could be implemented in the user file
01433    */
01434 }
01435
01436 /**
01437   * @brief  Data IN stage callback
01438   * @param  hpcd PCD handle
01439   * @param  epnum endpoint number
01440   * @retval None
01441   */
01442 __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01443 {
01444   /* Prevent unused argument(s) compilation warning */
01445   UNUSED(hpcd);
01446   UNUSED(epnum);
01447
01448   /* NOTE : This function should not be modified, when the callback is needed,
01449             the HAL_PCD_DataInStageCallback could be implemented in the user file
01450    */
01451 }
01452 /**
01453   * @brief  Setup stage callback
01454   * @param  hpcd PCD handle
01455   * @retval None
01456   */
01457 __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
01458 {
01459   /* Prevent unused argument(s) compilation warning */
01460   UNUSED(hpcd);
01461
01462   /* NOTE : This function should not be modified, when the callback is needed,
01463             the HAL_PCD_SetupStageCallback could be implemented in the user file
01464    */
01465 }
01466
01467 /**
01468   * @brief  USB Start Of Frame callback.
01469   * @param  hpcd PCD handle
01470   * @retval None
01471   */
01472 __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
01473 {
01474   /* Prevent unused argument(s) compilation warning */
01475   UNUSED(hpcd);
01476
01477   /* NOTE : This function should not be modified, when the callback is needed,
01478             the HAL_PCD_SOFCallback could be implemented in the user file
01479    */
01480 }
01481
01482 /**
01483   * @brief  USB Reset callback.
01484   * @param  hpcd PCD handle
01485   * @retval None
01486   */
01487 __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
01488 {
01489   /* Prevent unused argument(s) compilation warning */
01490   UNUSED(hpcd);
01491
01492   /* NOTE : This function should not be modified, when the callback is needed,
01493             the HAL_PCD_ResetCallback could be implemented in the user file
01494    */
01495 }
01496
01497 /**
01498   * @brief  Suspend event callback.
01499   * @param  hpcd PCD handle
01500   * @retval None
01501   */
01502 __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
01503 {
01504   /* Prevent unused argument(s) compilation warning */
01505   UNUSED(hpcd);
01506
01507   /* NOTE : This function should not be modified, when the callback is needed,
01508             the HAL_PCD_SuspendCallback could be implemented in the user file
01509    */
01510 }
01511
01512 /**
01513   * @brief  Resume event callback.
01514   * @param  hpcd PCD handle
01515   * @retval None
01516   */
01517 __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
01518 {
01519   /* Prevent unused argument(s) compilation warning */
01520   UNUSED(hpcd);
01521
01522   /* NOTE : This function should not be modified, when the callback is needed,
01523             the HAL_PCD_ResumeCallback could be implemented in the user file
01524    */
01525 }
01526
01527 /**
01528   * @brief  Incomplete ISO OUT callback.
01529   * @param  hpcd PCD handle
01530   * @param  epnum endpoint number
01531   * @retval None
01532   */
01533 __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01534 {
01535   /* Prevent unused argument(s) compilation warning */
01536   UNUSED(hpcd);
01537   UNUSED(epnum);
01538
01539   /* NOTE : This function should not be modified, when the callback is needed,
01540             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
01541    */
01542 }
01543
01544 /**
01545   * @brief  Incomplete ISO IN callback.
01546   * @param  hpcd PCD handle
01547   * @param  epnum endpoint number
01548   * @retval None
01549   */
01550 __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01551 {
01552   /* Prevent unused argument(s) compilation warning */
01553   UNUSED(hpcd);
01554   UNUSED(epnum);
01555
01556   /* NOTE : This function should not be modified, when the callback is needed,
01557             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
01558    */
01559 }
01560
01561 /**
01562   * @brief  Connection event callback.
01563   * @param  hpcd PCD handle
01564   * @retval None
01565   */
01566 __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
01567 {
01568   /* Prevent unused argument(s) compilation warning */
01569   UNUSED(hpcd);
01570
01571   /* NOTE : This function should not be modified, when the callback is needed,
01572             the HAL_PCD_ConnectCallback could be implemented in the user file
01573    */
01574 }
01575
01576 /**
01577   * @brief  Disconnection event callback.
01578   * @param  hpcd PCD handle
01579   * @retval None
01580   */
01581 __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
01582 {
01583   /* Prevent unused argument(s) compilation warning */
01584   UNUSED(hpcd);
01585
01586   /* NOTE : This function should not be modified, when the callback is needed,
01587             the HAL_PCD_DisconnectCallback could be implemented in the user file
01588    */
01589 }
01590
01591 /**
01592   * @}
01593   */
01594
01595 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
01596  *  @brief   management functions
01597  *
01598 @verbatim
01599  ===============================================================================
01600                       ##### Peripheral Control functions #####
01601  ===============================================================================
01602     [..]
01603     This subsection provides a set of functions allowing to control the PCD data
01604     transfers.
01605
01606 @endverbatim
01607   * @{
01608   */
01609
01610 /**
01611   * @brief  Connect the USB device
01612   * @param  hpcd PCD handle
01613   * @retval HAL status
01614   */
01615 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
01616 {
01617 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
01618   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01619 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
01620
01621   __HAL_LOCK(hpcd);
01622 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
01623   if ((hpcd->Init.battery_charging_enable == 1U) &&
01624       (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
01625   {
01626     /* Enable USB Transceiver */
01627     USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
01628   }
01629 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
01630   (void)USB_DevConnect(hpcd->Instance);
01631   __HAL_UNLOCK(hpcd);
01632   return HAL_OK;
01633 }
01634
01635 /**
01636   * @brief  Disconnect the USB device.
01637   * @param  hpcd PCD handle
01638   * @retval HAL status
01639   */
01640 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
01641 {
01642   __HAL_LOCK(hpcd);
01643   (void)USB_DevDisconnect(hpcd->Instance);
01644   __HAL_UNLOCK(hpcd);
01645   return HAL_OK;
01646 }
01647
01648 /**
01649   * @brief  Set the USB Device address.
01650   * @param  hpcd PCD handle
01651   * @param  address new device address
01652   * @retval HAL status
01653   */
01654 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
01655 {
01656   __HAL_LOCK(hpcd);
01657   hpcd->USB_Address = address;
01658   (void)USB_SetDevAddress(hpcd->Instance, address);
01659   __HAL_UNLOCK(hpcd);
01660   return HAL_OK;
01661 }
01662 /**
01663   * @brief  Open and configure an endpoint.
01664   * @param  hpcd PCD handle
01665   * @param  ep_addr endpoint address
01666   * @param  ep_mps endpoint max packet size
01667   * @param  ep_type endpoint type
01668   * @retval HAL status
01669   */
01670 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
01671 {
01672   HAL_StatusTypeDef  ret = HAL_OK;
01673   PCD_EPTypeDef *ep;
01674
01675   if ((ep_addr & 0x80U) == 0x80U)
01676   {
01677     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01678     ep->is_in = 1U;
01679   }
01680   else
01681   {
01682     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01683     ep->is_in = 0U;
01684   }
01685
01686   ep->num = ep_addr & EP_ADDR_MSK;
01687   ep->maxpacket = ep_mps;
01688   ep->type = ep_type;
01689
01690   if (ep->is_in != 0U)
01691   {
01692     /* Assign a Tx FIFO */
01693     ep->tx_fifo_num = ep->num;
01694   }
01695   /* Set initial data PID. */
01696   if (ep_type == EP_TYPE_BULK)
01697   {
01698     ep->data_pid_start = 0U;
01699   }
01700
01701   __HAL_LOCK(hpcd);
01702   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
01703   __HAL_UNLOCK(hpcd);
01704
01705   return ret;
01706 }
01707
01708 /**
01709   * @brief  Deactivate an endpoint.
01710   * @param  hpcd PCD handle
01711   * @param  ep_addr endpoint address
01712   * @retval HAL status
01713   */
01714 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01715 {
01716   PCD_EPTypeDef *ep;
01717
01718   if ((ep_addr & 0x80U) == 0x80U)
01719   {
01720     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01721     ep->is_in = 1U;
01722   }
01723   else
01724   {
01725     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01726     ep->is_in = 0U;
01727   }
01728   ep->num   = ep_addr & EP_ADDR_MSK;
01729
01730   __HAL_LOCK(hpcd);
01731   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
01732   __HAL_UNLOCK(hpcd);
01733   return HAL_OK;
01734 }
01735
01736
01737 /**
01738   * @brief  Receive an amount of data.
01739   * @param  hpcd PCD handle
01740   * @param  ep_addr endpoint address
01741   * @param  pBuf pointer to the reception buffer
01742   * @param  len amount of data to be received
01743   * @retval HAL status
01744   */
01745 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01746 {
01747   PCD_EPTypeDef *ep;
01748
01749   ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01750
01751   /*setup and start the Xfer */
01752   ep->xfer_buff = pBuf;
01753   ep->xfer_len = len;
01754   ep->xfer_count = 0U;
01755   ep->is_in = 0U;
01756   ep->num = ep_addr & EP_ADDR_MSK;
01757
01758   if (hpcd->Init.dma_enable == 1U)
01759   {
01760     ep->dma_addr = (uint32_t)pBuf;
01761   }
01762
01763   if ((ep_addr & EP_ADDR_MSK) == 0U)
01764   {
01765     (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
01766   }
01767   else
01768   {
01769     (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
01770   }
01771
01772   return HAL_OK;
01773 }
01774
01775 /**
01776   * @brief  Get Received Data Size
01777   * @param  hpcd PCD handle
01778   * @param  ep_addr endpoint address
01779   * @retval Data Size
01780   */
01781 uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01782 {
01783   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
01784 }
01785 /**
01786   * @brief  Send an amount of data
01787   * @param  hpcd PCD handle
01788   * @param  ep_addr endpoint address
01789   * @param  pBuf pointer to the transmission buffer
01790   * @param  len amount of data to be sent
01791   * @retval HAL status
01792   */
01793 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01794 {
01795   PCD_EPTypeDef *ep;
01796
01797   ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01798
01799   /*setup and start the Xfer */
01800   ep->xfer_buff = pBuf;
01801   ep->xfer_len = len;
01802   ep->xfer_count = 0U;
01803   ep->is_in = 1U;
01804   ep->num = ep_addr & EP_ADDR_MSK;
01805
01806   if (hpcd->Init.dma_enable == 1U)
01807   {
01808     ep->dma_addr = (uint32_t)pBuf;
01809   }
01810
01811   if ((ep_addr & EP_ADDR_MSK) == 0U)
01812   {
01813     (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
01814   }
01815   else
01816   {
01817     (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
01818   }
01819
01820   return HAL_OK;
01821 }
01822
01823 /**
01824   * @brief  Set a STALL condition over an endpoint
01825   * @param  hpcd PCD handle
01826   * @param  ep_addr endpoint address
01827   * @retval HAL status
01828   */
01829 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01830 {
01831   PCD_EPTypeDef *ep;
01832
01833   if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
01834   {
01835     return HAL_ERROR;
01836   }
01837
01838   if ((0x80U & ep_addr) == 0x80U)
01839   {
01840     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01841     ep->is_in = 1U;
01842   }
01843   else
01844   {
01845     ep = &hpcd->OUT_ep[ep_addr];
01846     ep->is_in = 0U;
01847   }
01848
01849   ep->is_stall = 1U;
01850   ep->num = ep_addr & EP_ADDR_MSK;
01851
01852   __HAL_LOCK(hpcd);
01853
01854   (void)USB_EPSetStall(hpcd->Instance, ep);
01855   if ((ep_addr & EP_ADDR_MSK) == 0U)
01856   {
01857     (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
01858   }
01859   __HAL_UNLOCK(hpcd);
01860
01861   return HAL_OK;
01862 }
01863
01864 /**
01865   * @brief  Clear a STALL condition over in an endpoint
01866   * @param  hpcd PCD handle
01867   * @param  ep_addr endpoint address
01868   * @retval HAL status
01869   */
01870 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01871 {
01872   PCD_EPTypeDef *ep;
01873
01874   if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
01875   {
01876     return HAL_ERROR;
01877   }
01878
01879   if ((0x80U & ep_addr) == 0x80U)
01880   {
01881     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01882     ep->is_in = 1U;
01883   }
01884   else
01885   {
01886     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01887     ep->is_in = 0U;
01888   }
01889
01890   ep->is_stall = 0U;
01891   ep->num = ep_addr & EP_ADDR_MSK;
01892
01893   __HAL_LOCK(hpcd);
01894   (void)USB_EPClearStall(hpcd->Instance, ep);
01895   __HAL_UNLOCK(hpcd);
01896
01897   return HAL_OK;
01898 }
01899
01900 /**
01901   * @brief  Flush an endpoint
01902   * @param  hpcd PCD handle
01903   * @param  ep_addr endpoint address
01904   * @retval HAL status
01905   */
01906 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01907 {
01908   __HAL_LOCK(hpcd);
01909
01910   if ((ep_addr & 0x80U) == 0x80U)
01911   {
01912     (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
01913   }
01914   else
01915   {
01916     (void)USB_FlushRxFifo(hpcd->Instance);
01917   }
01918
01919   __HAL_UNLOCK(hpcd);
01920
01921   return HAL_OK;
01922 }
01923
01924 /**
01925   * @brief  Activate remote wakeup signalling
01926   * @param  hpcd PCD handle
01927   * @retval HAL status
01928   */
01929 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01930 {
01931   return (USB_ActivateRemoteWakeup(hpcd->Instance));
01932 }
01933
01934 /**
01935   * @brief  De-activate remote wakeup signalling.
01936   * @param  hpcd PCD handle
01937   * @retval HAL status
01938   */
01939 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01940 {
01941   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
01942 }
01943
01944 /**
01945   * @}
01946   */
01947
01948 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01949  *  @brief   Peripheral State functions
01950  *
01951 @verbatim
01952  ===============================================================================
01953                       ##### Peripheral State functions #####
01954  ===============================================================================
01955     [..]
01956     This subsection permits to get in run-time the status of the peripheral
01957     and the data flow.
01958
01959 @endverbatim
01960   * @{
01961   */
01962
01963 /**
01964   * @brief  Return the PCD handle state.
01965   * @param  hpcd PCD handle
01966   * @retval HAL state
01967   */
01968 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01969 {
01970   return hpcd->State;
01971 }
01972
01973 /**
01974   * @}
01975   */
01976
01977 /**
01978   * @}
01979   */
01980
01981 /* Private functions ---------------------------------------------------------*/
01982 /** @addtogroup PCD_Private_Functions
01983   * @{
01984   */
01985 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
01986 /**
01987   * @brief  Check FIFO for the next packet to be loaded.
01988   * @param  hpcd PCD handle
01989   * @param  epnum endpoint number
01990   * @retval HAL status
01991   */
01992 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01993 {
01994   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01995   uint32_t USBx_BASE = (uint32_t)USBx;
01996   USB_OTG_EPTypeDef *ep;
01997   uint32_t len;
01998   uint32_t len32b;
01999   uint32_t fifoemptymsk;
02000
02001   ep = &hpcd->IN_ep[epnum];
02002
02003   if (ep->xfer_count > ep->xfer_len)
02004   {
02005     return HAL_ERROR;
02006   }
02007
02008   len = ep->xfer_len - ep->xfer_count;
02009
02010   if (len > ep->maxpacket)
02011   {
02012     len = ep->maxpacket;
02013   }
02014
02015   len32b = (len + 3U) / 4U;
02016
02017   while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
02018          (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
02019   {
02020     /* Write the FIFO */
02021     len = ep->xfer_len - ep->xfer_count;
02022
02023     if (len > ep->maxpacket)
02024     {
02025       len = ep->maxpacket;
02026     }
02027     len32b = (len + 3U) / 4U;
02028
02029     (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
02030                           (uint8_t)hpcd->Init.dma_enable);
02031
02032     ep->xfer_buff  += len;
02033     ep->xfer_count += len;
02034   }
02035
02036   if (ep->xfer_len <= ep->xfer_count)
02037   {
02038     fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
02039     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
02040   }
02041
02042   return HAL_OK;
02043 }
02044
02045
02046 /**
02047   * @brief  process EP OUT transfer complete interrupt.
02048   * @param  hpcd PCD handle
02049   * @param  epnum endpoint number
02050   * @retval HAL status
02051   */
02052 static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
02053 {
02054   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
02055   uint32_t USBx_BASE = (uint32_t)USBx;
02056   uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
02057   uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
02058
02059   if (hpcd->Init.dma_enable == 1U)
02060   {
02061     if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
02062     {
02063       /* StupPktRcvd = 1 this is a setup packet */
02064       if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
02065           ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
02066       {
02067         CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
02068       }
02069     }
02070     else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
02071     {
02072       CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
02073     }
02074     else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
02075     {
02076       /* StupPktRcvd = 1 this is a setup packet */
02077       if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
02078           ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
02079       {
02080         CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
02081       }
02082       else
02083       {
02084         /* out data packet received over EP0 */
02085         hpcd->OUT_ep[epnum].xfer_count =
02086           hpcd->OUT_ep[epnum].maxpacket -
02087           (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
02088
02089         hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
02090
02091         if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
02092         {
02093           /* this is ZLP, so prepare EP0 for next setup */
02094           (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
02095         }
02096 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02097         hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
02098 #else
02099         HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
02100 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02101       }
02102     }
02103     else
02104     {
02105       /* ... */
02106     }
02107   }
02108   else
02109   {
02110     if (gSNPSiD == USB_OTG_CORE_ID_310A)
02111     {
02112       /* StupPktRcvd = 1 this is a setup packet */
02113       if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
02114       {
02115         CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
02116       }
02117       else
02118       {
02119         if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
02120         {
02121           CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
02122         }
02123
02124 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02125         hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
02126 #else
02127         HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
02128 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02129       }
02130     }
02131     else
02132     {
02133       if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
02134       {
02135         /* this is ZLP, so prepare EP0 for next setup */
02136         (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
02137       }
02138
02139 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02140       hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
02141 #else
02142       HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
02143 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02144     }
02145   }
02146
02147   return HAL_OK;
02148 }
02149
02150
02151 /**
02152   * @brief  process EP OUT setup packet received interrupt.
02153   * @param  hpcd PCD handle
02154   * @param  epnum endpoint number
02155   * @retval HAL status
02156   */
02157 static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
02158 {
02159   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
02160   uint32_t USBx_BASE = (uint32_t)USBx;
02161   uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
02162   uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
02163
02164   if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
02165       ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
02166   {
02167     CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
02168   }
02169
02170   /* Inform the upper layer that a setup packet is available */
02171 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02172   hpcd->SetupStageCallback(hpcd);
02173 #else
02174   HAL_PCD_SetupStageCallback(hpcd);
02175 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02176
02177   if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
02178   {
02179     (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
02180   }
02181
02182   return HAL_OK;
02183 }
02184 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
02185
02186
02187 /**
02188   * @}
02189   */
02190 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
02191 #endif /* HAL_PCD_MODULE_ENABLED */
02192
02193 /**
02194   * @}
02195   */
02196
02197 /**
02198   * @}
02199   */
02200
02201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd.h Source File

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stm32h7xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_PCD_H
00022 #define STM32H7xx_HAL_PCD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_usb.h"
00030
00031 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup PCD
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup PCD_Exported_Types PCD Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  PCD State structure definition
00048   */
00049 typedef enum
00050 {
00051   HAL_PCD_STATE_RESET   = 0x00,
00052   HAL_PCD_STATE_READY   = 0x01,
00053   HAL_PCD_STATE_ERROR   = 0x02,
00054   HAL_PCD_STATE_BUSY    = 0x03,
00055   HAL_PCD_STATE_TIMEOUT = 0x04
00056 } PCD_StateTypeDef;
00057
00058 /* Device LPM suspend state */
00059 typedef enum
00060 {
00061   LPM_L0 = 0x00, /* on */
00062   LPM_L1 = 0x01, /* LPM L1 sleep */
00063   LPM_L2 = 0x02, /* suspend */
00064   LPM_L3 = 0x03, /* off */
00065 } PCD_LPM_StateTypeDef;
00066
00067 typedef enum
00068 {
00069   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00070   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00071 } PCD_LPM_MsgTypeDef;
00072
00073 typedef enum
00074 {
00075   PCD_BCD_ERROR                     = 0xFF,
00076   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00077   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00078   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00079   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00080   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00081
00082 } PCD_BCD_MsgTypeDef;
00083
00084 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00085 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00086 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00087 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
00088 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00089
00090 /**
00091   * @brief  PCD Handle Structure definition
00092   */
00093 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00094 typedef struct __PCD_HandleTypeDef
00095 #else
00096 typedef struct
00097 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00098 {
00099   PCD_TypeDef             *Instance;   /*!< Register base address              */
00100   PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
00101   __IO uint8_t            USB_Address; /*!< USB Address                        */
00102   PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */
00103   PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */
00104   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
00105   __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
00106   __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
00107   uint32_t                Setup[12];   /*!< Setup packet buffer                */
00108   PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
00109   uint32_t                BESL;
00110
00111
00112   uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
00113                                        This parameter can be set to ENABLE or DISABLE        */
00114
00115   uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
00116                                        This parameter can be set to ENABLE or DISABLE        */
00117   void                    *pData;      /*!< Pointer to upper stack Handler */
00118
00119 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00120   void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
00121   void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
00122   void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
00123   void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
00124   void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
00125   void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
00126   void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
00127
00128   void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
00129   void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
00130   void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
00131   void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
00132   void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
00133   void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
00134
00135   void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
00136   void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
00137 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00138 } PCD_HandleTypeDef;
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Include PCD HAL Extended module */
00145 #include "stm32h7xx_hal_pcd_ex.h"
00146
00147 /* Exported constants --------------------------------------------------------*/
00148 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00149   * @{
00150   */
00151
00152 /** @defgroup PCD_Speed PCD Speed
00153   * @{
00154   */
00155 #define PCD_SPEED_HIGH               USBD_HS_SPEED
00156 #define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
00157 #define PCD_SPEED_FULL               USBD_FS_SPEED
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup PCD_PHY_Module PCD PHY Module
00163   * @{
00164   */
00165 #define PCD_PHY_ULPI                 1U
00166 #define PCD_PHY_EMBEDDED             2U
00167 #define PCD_PHY_UTMI                 3U
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup PCD_Error_Code_definition PCD Error Code definition
00173   * @brief  PCD Error Code definition
00174   * @{
00175   */
00176 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00177 #define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00178 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macros -----------------------------------------------------------*/
00189 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00190  *  @brief macros to handle interrupts and specific clock configurations
00191  * @{
00192  */
00193 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00194 #define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00195 #define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00196
00197 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00198 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
00199 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00200
00201
00202 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00203                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
00204
00205 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00206
00207 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
00208
00209 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
00210 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00211 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
00212 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00213 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00214
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported functions --------------------------------------------------------*/
00221 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00222   * @{
00223   */
00224
00225 /* Initialization/de-initialization functions  ********************************/
00226 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00227   * @{
00228   */
00229 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00230 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
00231 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00232 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00233
00234 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00235 /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
00236   * @brief  HAL USB OTG PCD Callback ID enumeration definition
00237   * @{
00238   */
00239 typedef enum
00240 {
00241   HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
00242   HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
00243   HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
00244   HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
00245   HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
00246   HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
00247   HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
00248
00249   HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
00250   HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
00251
00252 } HAL_PCD_CallbackIDTypeDef;
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
00258   * @brief  HAL USB OTG PCD Callback pointer definition
00259   * @{
00260   */
00261
00262 typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
00263 typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
00264 typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
00265 typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
00266 typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
00267 typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
00268 typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
00269
00270 /**
00271   * @}
00272   */
00273
00274 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
00275 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
00276
00277 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
00278 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
00279
00280 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
00281 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
00282
00283 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
00284 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
00285
00286 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
00287 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
00288
00289 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
00290 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
00291
00292 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
00293 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
00294 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00295 /**
00296   * @}
00297   */
00298
00299 /* I/O operation functions  ***************************************************/
00300 /* Non-Blocking mode: Interrupt */
00301 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00302   * @{
00303   */
00304 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00305 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00306 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00307
00308 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00309 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00310 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00311 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00312 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00313 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00314 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00315
00316 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00317 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00318 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00319 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00320 /**
00321   * @}
00322   */
00323
00324 /* Peripheral Control functions  **********************************************/
00325 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00326   * @{
00327   */
00328 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00329 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00330 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00331 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00332 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00333 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00334 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00335 uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00336 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00337 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00338 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00339 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00340 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00341 /**
00342   * @}
00343   */
00344
00345 /* Peripheral State functions  ************************************************/
00346 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00347   * @{
00348   */
00349 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /* Private constants ---------------------------------------------------------*/
00359 /** @defgroup PCD_Private_Constants PCD Private Constants
00360   * @{
00361   */
00362 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00363   * @{
00364   */
00365 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00366 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
00367 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
00368 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
00369
00370 #define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U
00371 #define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
00372 #define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
00373
00374 #define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 12)  /*!< USB FS EXTI Line WakeUp Interrupt */
00375 #define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 11)  /*!< USB HS EXTI Line WakeUp Interrupt */
00376 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00377
00378
00379 /**
00380   * @}
00381   */
00382 /**
00383   * @}
00384   */
00385
00386 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00387 #ifndef USB_OTG_DOEPINT_OTEPSPR
00388 #define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
00389 #endif
00390
00391 #ifndef USB_OTG_DOEPMSK_OTEPSPRM
00392 #define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
00393 #endif
00394
00395 #ifndef USB_OTG_DOEPINT_NAK
00396 #define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
00397 #endif
00398
00399 #ifndef USB_OTG_DOEPMSK_NAKM
00400 #define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
00401 #endif
00402
00403 #ifndef USB_OTG_DOEPINT_STPKTRX
00404 #define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
00405 #endif
00406
00407 #ifndef USB_OTG_DOEPMSK_NYETM
00408 #define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
00409 #endif
00410 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00411
00412 /* Private macros ------------------------------------------------------------*/
00413 /** @defgroup PCD_Private_Macros PCD Private Macros
00414  * @{
00415  */
00416
00417 /**
00418   * @}
00419   */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00429
00430 #ifdef __cplusplus
00431 }
00432 #endif
00433
00434 #endif /* STM32H7xx_HAL_PCD_H */
00435
00436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd_ex.c Source File

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stm32h7xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   PCD Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32h7xx_hal.h"
00026
00027 /** @addtogroup STM32H7xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup PCDEx PCDEx
00032   * @brief PCD Extended HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_PCD_MODULE_ENABLED
00037
00038 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044 /* Exported functions --------------------------------------------------------*/
00045
00046 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00047   * @{
00048   */
00049
00050 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00051   * @brief    PCDEx control functions
00052  *
00053 @verbatim
00054  ===============================================================================
00055                  ##### Extended features functions #####
00056  ===============================================================================
00057     [..]  This section provides functions allowing to:
00058       (+) Update FIFO configuration
00059
00060 @endverbatim
00061   * @{
00062   */
00063 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00064 /**
00065   * @brief  Set Tx FIFO
00066   * @param  hpcd PCD handle
00067   * @param  fifo The number of Tx fifo
00068   * @param  size Fifo size
00069   * @retval HAL status
00070   */
00071 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00072 {
00073   uint8_t i;
00074   uint32_t Tx_Offset;
00075
00076   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00077       When a TxFIFO is not used, the Configuration should be as follows:
00078           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00079          --> Txm can use the space allocated for Txn.
00080          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00081          --> Txn should be configured with the minimum space of 16 words
00082      The FIFO is used optimally when used TxFIFOs are allocated in the top
00083          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00084      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00085
00086   Tx_Offset = hpcd->Instance->GRXFSIZ;
00087
00088   if (fifo == 0U)
00089   {
00090     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
00091   }
00092   else
00093   {
00094     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
00095     for (i = 0U; i < (fifo - 1U); i++)
00096     {
00097       Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
00098     }
00099
00100     /* Multiply Tx_Size by 2 to get higher performance */
00101     hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
00102   }
00103
00104   return HAL_OK;
00105 }
00106
00107 /**
00108   * @brief  Set Rx FIFO
00109   * @param  hpcd PCD handle
00110   * @param  size Size of Rx fifo
00111   * @retval HAL status
00112   */
00113 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00114 {
00115   hpcd->Instance->GRXFSIZ = size;
00116
00117   return HAL_OK;
00118 }
00119
00120 /**
00121   * @brief  Activate LPM feature.
00122   * @param  hpcd PCD handle
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00126 {
00127   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00128
00129   hpcd->lpm_active = 1U;
00130   hpcd->LPM_State = LPM_L0;
00131   USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
00132   USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00133
00134   return HAL_OK;
00135 }
00136
00137 /**
00138   * @brief  Deactivate LPM feature.
00139   * @param  hpcd PCD handle
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00143 {
00144   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00145
00146   hpcd->lpm_active = 0U;
00147   USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
00148   USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00149
00150   return HAL_OK;
00151 }
00152
00153
00154 /**
00155   * @brief  Handle BatteryCharging Process.
00156   * @param  hpcd PCD handle
00157   * @retval HAL status
00158   */
00159 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00160 {
00161   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00162   uint32_t tickstart = HAL_GetTick();
00163
00164   /* Enable DCD : Data Contact Detect */
00165   USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
00166
00167   /* Wait Detect flag or a timeout is happen*/
00168   while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
00169   {
00170     /* Check for the Timeout */
00171     if ((HAL_GetTick() - tickstart) > 1000U)
00172     {
00173 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00174       hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
00175 #else
00176       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00177 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00178
00179       return;
00180     }
00181   }
00182
00183   /* Right response got */
00184   HAL_Delay(200U);
00185
00186   /* Check Detect flag*/
00187   if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
00188   {
00189 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00190     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
00191 #else
00192     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00193 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00194   }
00195
00196   /*Primary detection: checks if connected to Standard Downstream Port
00197   (without charging capability) */
00198   USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
00199   HAL_Delay(50U);
00200   USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
00201   HAL_Delay(50U);
00202
00203   if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
00204   {
00205     /* Case of Standard Downstream Port */
00206 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00207     hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00208 #else
00209     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00210 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00211   }
00212   else
00213   {
00214     /* start secondary detection to check connection to Charging Downstream
00215     Port or Dedicated Charging Port */
00216     USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
00217     HAL_Delay(50U);
00218     USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
00219     HAL_Delay(50U);
00220
00221     if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
00222     {
00223       /* case Dedicated Charging Port  */
00224 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00225       hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00226 #else
00227       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00228 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00229     }
00230     else
00231     {
00232       /* case Charging Downstream Port  */
00233 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00234       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00235 #else
00236       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00237 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00238     }
00239   }
00240
00241   /* Battery Charging capability discovery finished */
00242   (void)HAL_PCDEx_DeActivateBCD(hpcd);
00243
00244 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00245   hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00246 #else
00247   HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00248 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00249 }
00250
00251 /**
00252   * @brief  Activate BatteryCharging feature.
00253   * @param  hpcd PCD handle
00254   * @retval HAL status
00255   */
00256 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00257 {
00258   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00259
00260   USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
00261   USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
00262
00263   /* Power Down USB tranceiver  */
00264   USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
00265
00266   /* Enable Battery charging */
00267   USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
00268
00269   hpcd->battery_charging_active = 1U;
00270
00271   return HAL_OK;
00272 }
00273
00274 /**
00275   * @brief  Deactivate BatteryCharging feature.
00276   * @param  hpcd PCD handle
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00280 {
00281   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00282
00283   USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
00284   USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
00285
00286   /* Disable Battery charging */
00287   USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
00288
00289   hpcd->battery_charging_active = 0U;
00290
00291   return HAL_OK;
00292 }
00293
00294 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00295
00296 /**
00297   * @brief  Send LPM message to user layer callback.
00298   * @param  hpcd PCD handle
00299   * @param  msg LPM message
00300   * @retval HAL status
00301   */
00302 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(hpcd);
00306   UNUSED(msg);
00307
00308   /* NOTE : This function should not be modified, when the callback is needed,
00309             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00310    */
00311 }
00312
00313 /**
00314   * @brief  Send BatteryCharging message to user layer callback.
00315   * @param  hpcd PCD handle
00316   * @param  msg LPM message
00317   * @retval HAL status
00318   */
00319 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00320 {
00321   /* Prevent unused argument(s) compilation warning */
00322   UNUSED(hpcd);
00323   UNUSED(msg);
00324
00325   /* NOTE : This function should not be modified, when the callback is needed,
00326             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00327    */
00328 }
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00338 #endif /* HAL_PCD_MODULE_ENABLED */
00339
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pcd_ex.h Source File

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  • Inc
stm32h7xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_PCD_EX_H
00022 #define STM32H7xx_HAL_PCD_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup PCDEx
00037   * @{
00038   */
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /* Exported functions --------------------------------------------------------*/
00043 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00044   * @{
00045   */
00046 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00047   * @{
00048   */
00049
00050 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
00051 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00052 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00053 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00054
00055
00056 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00057 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00058
00059
00060 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00061 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00062 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00063
00064 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00065 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00066
00067 /**
00068   * @}
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /**
00080   * @}
00081   */
00082 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
00083
00084 #ifdef __cplusplus
00085 }
00086 #endif
00087
00088
00089 #endif /* STM32H7xx_HAL_PCD_EX_H */
00090
00091 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pssi.c Source File

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stm32h7xx_hal_pssi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pssi.c
00004   * @author  MCD Application Team
00005   * @brief   PSSI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The PSSI HAL driver can be used as follows:
00018
00019     (#) Declare a PSSI_HandleTypeDef handle structure, for example:
00020         PSSI_HandleTypeDef  hpssi;
00021
00022     (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
00023         (##) Enable the PSSIx interface clock
00024         (##) PSSI pins configuration
00025             (+++) Enable the clock for the PSSI GPIOs
00026             (+++) Configure PSSI pins as alternate function open-drain
00027         (##) NVIC configuration if you need to use interrupt process
00028             (+++) Configure the PSSIx interrupt priority
00029             (+++) Enable the NVIC PSSI IRQ Channel
00030         (##) DMA Configuration if you need to use DMA process
00031             (+++) Declare  DMA_HandleTypeDef handles structure for the transmit and receive
00032             (+++) Enable the DMAx interface clock
00033             (+++) Configure the DMA handle parameters
00034             (+++) Configure the DMA Tx and Rx
00035             (+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00037                   the DMA Tx and Rx
00038
00039     (#) Configure the Communication Bus Width,  Control Signals, Input Polarity and Output Polarity
00040          in the hpssi Init structure.
00041
00042     (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
00043         (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
00044
00045
00046     (#) For PSSI IO operations, two operation modes are available within this driver :
00047
00048     *** Polling mode IO operation ***
00049     =================================
00050     [..]
00051       (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
00052       (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()
00053
00054     *** DMA mode IO operation ***
00055     ==============================
00056     [..]
00057       (+) Transmit an amount of data in non-blocking mode (DMA) using
00058           @ref HAL_PSSI_Transmit_DMA()
00059       (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
00060            add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
00061       (+) Receive an amount of data in non-blocking mode (DMA) using
00062           @ref HAL_PSSI_Receive_DMA()
00063       (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
00064            add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
00065       (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
00066            add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
00067       (+) Abort a  PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
00068       (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
00069            add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()
00070
00071      *** PSSI HAL driver macros list ***
00072      ==================================
00073      [..]
00074        Below the list of most used macros in PSSI HAL driver.
00075
00076       (+) @ref HAL_PSSI_ENABLE     : Enable the PSSI peripheral
00077       (+) @ref HAL_PSSI_DISABLE    : Disable the PSSI peripheral
00078       (+) @ref HAL_PSSI_GET_FLAG   : Check whether the specified PSSI flag is set or not
00079       (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
00080       (+) @ref HAL_PSSI_ENABLE_IT  : Enable the specified PSSI interrupt
00081       (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
00082
00083      *** Callback registration ***
00084      =============================================
00085      Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
00086      to register an interrupt callback.
00087
00088      Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
00089        (+) TxCpltCallback       : callback for transmission end of transfer.
00090        (+) RxCpltCallback       : callback for reception end of transfer.
00091        (+) ErrorCallback        : callback for error detection.
00092        (+) AbortCpltCallback    : callback for abort completion process.
00093        (+) MspInitCallback      : callback for Msp Init.
00094        (+) MspDeInitCallback    : callback for Msp DeInit.
00095      This function takes as parameters the HAL peripheral handle, the Callback ID
00096      and a pointer to the user callback function.
00097
00098
00099      Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
00100      weak function.
00101      @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00102      and the Callback ID.
00103      This function allows to reset following callbacks:
00104        (+) TxCpltCallback       : callback for transmission end of transfer.
00105        (+) RxCpltCallback       : callback for reception end of transfer.
00106        (+) ErrorCallback        : callback for error detection.
00107        (+) AbortCpltCallback    : callback for abort completion process.
00108        (+) MspInitCallback      : callback for Msp Init.
00109        (+) MspDeInitCallback    : callback for Msp DeInit.
00110
00111
00112      By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
00113      all callbacks are set to the corresponding weak functions:
00114      examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
00115      Exception done for MspInit and MspDeInit functions that are
00116      reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
00117      these callbacks are null (not registered beforehand).
00118      If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
00119      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00120
00121      Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
00122      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00123      in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
00124      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00125      Then, the user first registers the MspInit/MspDeInit user callbacks
00126      using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
00127      or @ref HAL_PSSI_Init() function.
00128
00129
00130      [..]
00131        (@) You can refer to the PSSI HAL driver header file for more useful macros
00132
00133   @endverbatim
00134   ******************************************************************************
00135   * @attention
00136   *
00137   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00138   * All rights reserved.</center></h2>
00139   *
00140   * This software component is licensed by ST under BSD 3-Clause license,
00141   * the "License"; You may not use this file except in compliance with the
00142   * License. You may obtain a copy of the License at:
00143   *                        opensource.org/licenses/BSD-3-Clause
00144   *
00145   ******************************************************************************
00146   */
00147
00148 /* Includes ------------------------------------------------------------------*/
00149 #include "stm32h7xx_hal.h"
00150
00151 /** @addtogroup STM32H7xx_HAL_Driver
00152   * @{
00153   */
00154
00155 /** @defgroup PSSI PSSI
00156   * @brief PSSI HAL module driver
00157   * @{
00158   */
00159
00160 #ifdef HAL_PSSI_MODULE_ENABLED
00161 #if defined(PSSI)
00162 /* Private typedef -----------------------------------------------------------*/
00163 /* Private define ------------------------------------------------------------*/
00164
00165 /** @defgroup PSSI_Private_Define PSSI Private Define
00166   * @{
00167   */
00168
00169
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Private macro -------------------------------------------------------------*/
00176 /* Private variables ---------------------------------------------------------*/
00177 /* Private function prototypes -----------------------------------------------*/
00178
00179 /** @defgroup PSSI_Private_Functions PSSI Private Functions
00180   * @{
00181   */
00182 /* Private functions to handle DMA transfer */
00183 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00184 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00185 void PSSI_DMAError(DMA_HandleTypeDef *hdma);
00186 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
00187
00188 /* Private functions to handle IT transfer */
00189 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
00190
00191 /* Private functions to handle flags during polling transfer */
00192 static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00193
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported functions --------------------------------------------------------*/
00199
00200 /** @defgroup PSSI_Exported_Functions PSSI Exported Functions
00201   * @{
00202   */
00203
00204 /** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
00205  *  @brief    Initialization and Configuration functions
00206  *
00207 @verbatim
00208  ===============================================================================
00209               ##### Initialization and de-initialization functions #####
00210  ===============================================================================
00211     [..]  This subsection provides a set of functions allowing to initialize and
00212           deinitialize the PSSIx peripheral:
00213
00214       (+) User must implement HAL_PSSI_MspInit() function in which he configures
00215           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00216
00217       (+) Call the function HAL_PSSI_Init() to configure the selected device with
00218           the selected configuration:
00219         (++) Data Width
00220         (++) Control Signals
00221         (++) Input Clock polarity
00222         (++) Output Clock polarity
00223
00224       (+) Call the function HAL_PSSI_DeInit() to restore the default configuration
00225           of the selected PSSIx peripheral.
00226
00227 @endverbatim
00228   * @{
00229   */
00230
00231 /**
00232   * @brief  Initializes the PSSI according to the specified parameters
00233   *         in the PSSI_InitTypeDef and initialize the associated handle.
00234   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00235   *                the configuration information for the specified PSSI.
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
00239 {
00240   /* Check the PSSI handle allocation */
00241   if (hpssi == NULL)
00242   {
00243     return HAL_ERROR;
00244   }
00245
00246   /* Check the parameters */
00247   assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
00248   assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal));
00249   assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth));
00250   assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity));
00251   assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity));
00252   assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity));
00253
00254   if (hpssi->State == HAL_PSSI_STATE_RESET)
00255   {
00256     /* Allocate lock resource and initialize it */
00257     hpssi->Lock = HAL_UNLOCKED;
00258
00259     /* Init the PSSI Callback settings */
00260     hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
00261     hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
00262     hpssi->ErrorCallback        = HAL_PSSI_ErrorCallback;        /* Legacy weak ErrorCallback        */
00263     hpssi->AbortCpltCallback    = HAL_PSSI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00264
00265     if (hpssi->MspInitCallback == NULL)
00266     {
00267       hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit  */
00268     }
00269
00270     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00271     hpssi->MspInitCallback(hpssi);
00272
00273   }
00274
00275   hpssi->State = HAL_PSSI_STATE_BUSY;
00276
00277   /* Disable the selected PSSI peripheral */
00278   HAL_PSSI_DISABLE(hpssi);
00279
00280   /*---------------------------- PSSIx CR Configuration ----------------------*/
00281   /* Configure PSSIx: Control Signal and Bus Width*/
00282
00283   MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DERDYCFG|PSSI_CR_EDM|PSSI_CR_DEPOL|PSSI_CR_RDYPOL,
00284              hpssi->Init.ControlSignal|hpssi->Init.DataEnablePolarity|hpssi->Init.ReadyPolarity|hpssi->Init.BusWidth);
00285
00286   hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
00287   hpssi->State = HAL_PSSI_STATE_READY;
00288
00289   return HAL_OK;
00290 }
00291
00292 /**
00293   * @brief  DeInitialize the PSSI peripheral.
00294   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00295   *                the configuration information for the specified PSSI.
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
00299 {
00300   /* Check the PSSI handle allocation */
00301   if (hpssi == NULL)
00302   {
00303     return HAL_ERROR;
00304   }
00305
00306   /* Check the parameters */
00307   assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
00308
00309   hpssi->State = HAL_PSSI_STATE_BUSY;
00310
00311   /* Disable the PSSI Peripheral Clock */
00312   HAL_PSSI_DISABLE(hpssi);
00313
00314   if (hpssi->MspDeInitCallback == NULL)
00315   {
00316     hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit  */
00317   }
00318
00319   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00320   hpssi->MspDeInitCallback(hpssi);
00321
00322   hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
00323   hpssi->State = HAL_PSSI_STATE_RESET;
00324
00325   /* Release Lock */
00326   __HAL_UNLOCK(hpssi);
00327
00328   return HAL_OK;
00329 }
00330
00331 /**
00332   * @brief Initialize the PSSI MSP.
00333   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00334   *                the configuration information for the specified PSSI.
00335   * @retval None
00336   */
00337 __weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
00338 {
00339   /* Prevent unused argument(s) compilation warning */
00340   UNUSED(hpssi);
00341
00342   /* NOTE : This function should not be modified, when the callback is needed,
00343             the HAL_PSSI_MspInit can be implemented in the user file
00344    */
00345 }
00346
00347 /**
00348   * @brief DeInitialize the PSSI MSP.
00349   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00350   *                the configuration information for the specified PSSI.
00351   * @retval None
00352   */
00353 __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hpssi);
00357
00358   /* NOTE : This function should not be modified, when the callback is needed,
00359             the HAL_PSSI_MspDeInit can be implemented in the user file
00360    */
00361 }
00362
00363 /**
00364   * @brief  Register a User PSSI Callback
00365   *         To be used instead of the weak predefined callback
00366   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00367   *                the configuration information for the specified PSSI.
00368   * @param  CallbackID ID of the callback to be registered
00369   *         This parameter can be one of the following values:
00370   *          @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID  Tx Transfer completed callback ID
00371   *          @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID  Rx Transfer completed callback ID
00372   *          @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
00373   *          @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
00374   *          @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
00375   *          @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
00376   * @param  pCallback pointer to the Callback function
00377   * @retval HAL status
00378   */
00379 HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback)
00380 {
00381   HAL_StatusTypeDef status = HAL_OK;
00382
00383   if (pCallback == NULL)
00384   {
00385     /* Update the error code */
00386     hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00387
00388     return HAL_ERROR;
00389   }
00390   /* Process locked */
00391   __HAL_LOCK(hpssi);
00392
00393   if (HAL_PSSI_STATE_READY == hpssi->State)
00394   {
00395     switch (CallbackID)
00396     {
00397       case HAL_PSSI_TX_COMPLETE_CB_ID :
00398         hpssi->TxCpltCallback = pCallback;
00399         break;
00400
00401       case HAL_PSSI_RX_COMPLETE_CB_ID :
00402         hpssi->RxCpltCallback = pCallback;
00403         break;
00404
00405       case HAL_PSSI_ERROR_CB_ID :
00406         hpssi->ErrorCallback = pCallback;
00407         break;
00408
00409       case HAL_PSSI_ABORT_CB_ID :
00410         hpssi->AbortCpltCallback = pCallback;
00411         break;
00412
00413       case HAL_PSSI_MSPINIT_CB_ID :
00414         hpssi->MspInitCallback = pCallback;
00415         break;
00416
00417       case HAL_PSSI_MSPDEINIT_CB_ID :
00418         hpssi->MspDeInitCallback = pCallback;
00419         break;
00420
00421       default :
00422         /* Update the error code */
00423         hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00424
00425         /* Return error status */
00426         status =  HAL_ERROR;
00427         break;
00428     }
00429   }
00430   else if (HAL_PSSI_STATE_RESET == hpssi->State)
00431   {
00432     switch (CallbackID)
00433     {
00434       case HAL_PSSI_MSPINIT_CB_ID :
00435         hpssi->MspInitCallback = pCallback;
00436         break;
00437
00438       case HAL_PSSI_MSPDEINIT_CB_ID :
00439         hpssi->MspDeInitCallback = pCallback;
00440         break;
00441
00442       default :
00443         /* Update the error code */
00444         hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00445
00446         /* Return error status */
00447         status =  HAL_ERROR;
00448         break;
00449     }
00450   }
00451   else
00452   {
00453     /* Update the error code */
00454     hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00455
00456     /* Return error status */
00457     status =  HAL_ERROR;
00458   }
00459
00460   /* Release Lock */
00461   __HAL_UNLOCK(hpssi);
00462   return status;
00463 }
00464
00465 /**
00466   * @brief  Unregister an PSSI Callback
00467   *         PSSI callback is redirected to the weak predefined callback
00468   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00469   *                the configuration information for the specified PSSI.
00470   * @param  CallbackID ID of the callback to be unregistered
00471   *         This parameter can be one of the following values:
00472   *          @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID  Tx Transfer completed callback ID
00473   *          @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID  Rx Transfer completed callback ID
00474   *          @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
00475   *          @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
00476   *          @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
00477   *          @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
00478   * @retval HAL status
00479   */
00480 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
00481 {
00482   HAL_StatusTypeDef status = HAL_OK;
00483
00484   /* Process locked */
00485   __HAL_LOCK(hpssi);
00486
00487   if (HAL_PSSI_STATE_READY == hpssi->State)
00488   {
00489     switch (CallbackID)
00490     {
00491       case HAL_PSSI_TX_COMPLETE_CB_ID :
00492         hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
00493         break;
00494
00495       case HAL_PSSI_RX_COMPLETE_CB_ID :
00496         hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;   /* Legacy weak RxCpltCallback  */
00497         break;
00498
00499       case HAL_PSSI_ERROR_CB_ID :
00500         hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;               /* Legacy weak ErrorCallback        */
00501         break;
00502
00503       case HAL_PSSI_ABORT_CB_ID :
00504         hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00505         break;
00506
00507       case HAL_PSSI_MSPINIT_CB_ID :
00508         hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit              */
00509         break;
00510
00511       case HAL_PSSI_MSPDEINIT_CB_ID :
00512         hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit            */
00513         break;
00514
00515       default :
00516         /* Update the error code */
00517         hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00518
00519         /* Return error status */
00520         status =  HAL_ERROR;
00521         break;
00522     }
00523   }
00524   else if (HAL_PSSI_STATE_RESET == hpssi->State)
00525   {
00526     switch (CallbackID)
00527     {
00528       case HAL_PSSI_MSPINIT_CB_ID :
00529         hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit              */
00530         break;
00531
00532       case HAL_PSSI_MSPDEINIT_CB_ID :
00533         hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit            */
00534         break;
00535
00536       default :
00537         /* Update the error code */
00538         hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00539
00540         /* Return error status */
00541         status =  HAL_ERROR;
00542         break;
00543     }
00544   }
00545   else
00546   {
00547     /* Update the error code */
00548     hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
00549
00550     /* Return error status */
00551     status =  HAL_ERROR;
00552   }
00553
00554   /* Release Lock */
00555   __HAL_UNLOCK(hpssi);
00556   return status;
00557 }
00558
00559
00560 /**
00561   * @}
00562   */
00563
00564 /** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions
00565  *  @brief   Data transfers functions
00566  *
00567 @verbatim
00568  ===============================================================================
00569                       ##### IO operation functions #####
00570  ===============================================================================
00571     [..]
00572     This subsection provides a set of functions allowing to manage the PSSI data
00573     transfers.
00574
00575     (#) There are two modes of transfer:
00576        (++) Blocking mode : The communication is performed in the polling mode.
00577             The status of all data processing is returned by the same function
00578             after finishing transfer.
00579        (++) No-Blocking mode : The communication is performed using DMA.
00580             These functions return the status of the transfer startup.
00581             The end of the data processing will be indicated through the
00582             dedicated  the DMA IRQ .
00583
00584     (#) Blocking mode functions are :
00585         (++) HAL_PSSI_Transmit()
00586         (++) HAL_PSSI_Receive()
00587
00588     (#) No-Blocking mode functions with DMA are :
00589         (++) HAL_PSSI_Transmit_DMA()
00590         (++) HAL_PSSI_Receive_DMA()
00591
00592     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00593         (++) HAL_PSSI_TxCpltCallback()
00594         (++) HAL_PSSI_RxCpltCallback()
00595         (++) HAL_PSSI_ErrorCallback()
00596         (++) HAL_PSSI_AbortCpltCallback()
00597
00598 @endverbatim
00599   * @{
00600   */
00601
00602 /**
00603   * @brief  Transmits in master mode an amount of data in blocking mode.
00604   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00605   *                the configuration information for the specified PSSI.
00606   * @param  pData Pointer to data buffer
00607   * @param  Size Amount of data to be sent (in bytes)
00608   * @param  Timeout Timeout duration
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
00612 {
00613   uint32_t tickstart;
00614   uint32_t  transfer_size = Size;
00615
00616   if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
00617       ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
00618       ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
00619   {
00620     hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
00621     return HAL_ERROR;
00622   }
00623   if (hpssi->State == HAL_PSSI_STATE_READY)
00624   {
00625     /* Process Locked */
00626     __HAL_LOCK(hpssi);
00627
00628     hpssi->State     = HAL_PSSI_STATE_BUSY;
00629     hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
00630
00631     /* Disable the selected PSSI peripheral */
00632     HAL_PSSI_DISABLE(hpssi);
00633
00634     /* Configure transfer parameters */
00635     hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
00636       ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL);
00637     /* DMA Disable */
00638     hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
00639
00640     /* Enable the selected PSSI peripheral */
00641     HAL_PSSI_ENABLE(hpssi);
00642
00643     if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
00644     {
00645       uint8_t *pbuffer = pData;
00646       while (transfer_size > 0U)
00647       {
00648         /* Init tickstart for timeout management*/
00649         tickstart = HAL_GetTick();
00650         /* Wait until Fifo is ready to transfer one byte flag is set */
00651         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
00652         {
00653           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00654           hpssi->State = HAL_PSSI_STATE_READY;
00655           /* Process Unlocked */
00656           __HAL_UNLOCK(hpssi);
00657           return HAL_ERROR;
00658         }
00659         /* Write data to DR */
00660         *(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer;
00661
00662         /* Increment Buffer pointer */
00663         pbuffer++;
00664
00665         transfer_size--;
00666       }
00667     }
00668     else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
00669     {
00670       uint16_t *pbuffer = (uint16_t *)pData;
00671       while (transfer_size > 0U)
00672       {
00673         /* Init tickstart for timeout management*/
00674         tickstart = HAL_GetTick();
00675         /* Wait until Fifo is ready to transfer four bytes flag is set */
00676         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
00677         {
00678           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00679           hpssi->State = HAL_PSSI_STATE_READY;
00680           /* Process Unlocked */
00681           __HAL_UNLOCK(hpssi);
00682           return HAL_ERROR;
00683         }
00684         /* Write data to DR */
00685         *(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer;
00686
00687         /* Increment Buffer pointer */
00688         pbuffer++;
00689         transfer_size -= 2U;
00690
00691       }
00692     }
00693     else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
00694     {
00695       uint32_t *pbuffer = (uint32_t *)pData;
00696       while (transfer_size > 0U)
00697       {
00698         /* Init tickstart for timeout management*/
00699         tickstart = HAL_GetTick();
00700         /* Wait until Fifo is ready to transfer four bytes flag is set */
00701         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
00702         {
00703           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00704           hpssi->State = HAL_PSSI_STATE_READY;
00705           /* Process Unlocked */
00706           __HAL_UNLOCK(hpssi);
00707           return HAL_ERROR;
00708         }
00709         /* Write data to DR */
00710         *(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer;
00711
00712         /* Increment Buffer pointer */
00713         pbuffer++;
00714         transfer_size -= 4U;
00715       }
00716
00717     }
00718     else
00719     {
00720       hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
00721       hpssi->State = HAL_PSSI_STATE_READY;
00722       /* Process Unlocked */
00723       __HAL_UNLOCK(hpssi);
00724       return HAL_ERROR;
00725     }
00726
00727     /* Check Errors Flags */
00728     if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
00729     {
00730       HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
00731       HAL_PSSI_DISABLE(hpssi);
00732       hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN;
00733       hpssi->State = HAL_PSSI_STATE_READY;
00734       /* Process Unlocked */
00735       __HAL_UNLOCK(hpssi);
00736       return HAL_ERROR;
00737     }
00738
00739     hpssi->State = HAL_PSSI_STATE_READY;
00740
00741     /* Process Unlocked */
00742     __HAL_UNLOCK(hpssi);
00743
00744     return HAL_OK;
00745   }
00746   else
00747   {
00748     return HAL_BUSY;
00749   }
00750 }
00751
00752
00753 /**
00754   * @brief  Receives an amount of data in blocking mode.
00755   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00756   *                the configuration information for the specified PSSI.
00757   * @param  pData Pointer to data buffer
00758   * @param  Size Amount of data to be received (in bytes)
00759   * @param  Timeout Timeout duration
00760   * @retval HAL status
00761   */
00762 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
00763 {
00764   uint32_t tickstart;
00765   uint32_t  transfer_size = Size;
00766
00767   if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
00768       ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
00769       ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
00770   {
00771     hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
00772     return HAL_ERROR;
00773   }
00774
00775   if (hpssi->State == HAL_PSSI_STATE_READY)
00776   {
00777     /* Process Locked */
00778     __HAL_LOCK(hpssi);
00779
00780     hpssi->State     = HAL_PSSI_STATE_BUSY;
00781     hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
00782
00783     /* Disable the selected PSSI peripheral */
00784     HAL_PSSI_DISABLE(hpssi);
00785     /* Configure transfer parameters */
00786     hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE)?0U:PSSI_CR_CKPOL);
00787
00788
00789     /* DMA Disable */
00790     hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
00791
00792     /* Enable the selected PSSI peripheral */
00793     HAL_PSSI_ENABLE(hpssi);
00794     if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
00795     {
00796       uint8_t *pbuffer = pData;
00797
00798       while (transfer_size > 0U)
00799       {
00800         /* Init tickstart for timeout management*/
00801         tickstart = HAL_GetTick();
00802         /* Wait until Fifo is ready to receive one byte flag is set */
00803         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
00804         {
00805           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00806           hpssi->State = HAL_PSSI_STATE_READY;
00807           /* Process Unlocked */
00808           __HAL_UNLOCK(hpssi);
00809           return HAL_ERROR;
00810         }
00811         /* Read data from DR */
00812         *pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR);
00813         pbuffer++;
00814         transfer_size--;
00815       }
00816     }
00817     else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
00818     {
00819       uint16_t *pbuffer = (uint16_t *)pData;
00820
00821       while (transfer_size > 0U)
00822       {
00823         /* Init tickstart for timeout management*/
00824         tickstart = HAL_GetTick();
00825         /* Wait until Fifo is ready to receive four bytes flag is set */
00826         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
00827         {
00828           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00829           hpssi->State = HAL_PSSI_STATE_READY;
00830           /* Process Unlocked */
00831           __HAL_UNLOCK(hpssi);
00832           return HAL_ERROR;
00833         }
00834
00835         /* Read data from DR */
00836         *pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR);
00837         pbuffer++;
00838         transfer_size -= 2U;
00839
00840       }
00841     }
00842     else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
00843     {
00844       uint32_t *pbuffer = (uint32_t *)pData;
00845
00846       while (transfer_size > 0U)
00847       {
00848         /* Init tickstart for timeout management*/
00849         tickstart = HAL_GetTick();
00850         /* Wait until Fifo is ready to receive four bytes flag is set */
00851         if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
00852         {
00853           hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
00854           hpssi->State = HAL_PSSI_STATE_READY;
00855           /* Process Unlocked */
00856           __HAL_UNLOCK(hpssi);
00857           return HAL_ERROR;
00858         }
00859
00860         /* Read data from DR */
00861         *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
00862         pbuffer++;
00863         transfer_size -= 4U;
00864
00865       }
00866     }
00867     else
00868     {
00869       hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
00870       hpssi->State = HAL_PSSI_STATE_READY;
00871       /* Process Unlocked */
00872       __HAL_UNLOCK(hpssi);
00873       return HAL_ERROR;
00874     }
00875     /* Check Errors Flags */
00876
00877     if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
00878     {
00879       HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
00880       hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN;
00881       __HAL_UNLOCK(hpssi);
00882       return HAL_ERROR;
00883     }
00884
00885
00886     hpssi->State = HAL_PSSI_STATE_READY;
00887
00888     /* Process Unlocked */
00889     __HAL_UNLOCK(hpssi);
00890
00891     return HAL_OK;
00892   }
00893   else
00894   {
00895     return HAL_BUSY;
00896   }
00897 }
00898
00899 /**
00900   * @brief  Transmit an amount of data in non-blocking mode with DMA
00901   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
00902   *                the configuration information for the specified PSSI.
00903   * @param  pData Pointer to data buffer
00904   * @param  Size Amount of data to be sent (in bytes)
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
00908 {
00909   HAL_StatusTypeDef dmaxferstatus;
00910
00911   if (hpssi->State == HAL_PSSI_STATE_READY)
00912   {
00913
00914     /* Process Locked */
00915     __HAL_LOCK(hpssi);
00916
00917     hpssi->State       = HAL_PSSI_STATE_BUSY_TX;
00918     hpssi->ErrorCode   = HAL_PSSI_ERROR_NONE;
00919
00920     /* Disable the selected PSSI peripheral */
00921     HAL_PSSI_DISABLE(hpssi);
00922
00923     /* Prepare transfer parameters */
00924     hpssi->pBuffPtr    = pData;
00925     hpssi->XferCount   = Size;
00926
00927     if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
00928     {
00929       hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
00930     }
00931     else
00932     {
00933       hpssi->XferSize = hpssi->XferCount;
00934     }
00935
00936     if (hpssi->XferSize > 0U)
00937     {
00938       if (hpssi->hdmatx != NULL)
00939       {
00940
00941         /* Configure BusWidth */
00942         if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
00943         {
00944           MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
00945                      ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
00946         }
00947         else
00948         {
00949           MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
00950                      ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
00951         }
00952
00953         /* Set the PSSI DMA transfer complete callback */
00954         hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
00955
00956         /* Set the DMA error callback */
00957         hpssi->hdmatx->XferErrorCallback = PSSI_DMAError;
00958
00959         /* Set the unused DMA callbacks to NULL */
00960         hpssi->hdmatx->XferHalfCpltCallback = NULL;
00961         hpssi->hdmatx->XferAbortCallback = NULL;
00962
00963         /* Enable the DMA  */
00964         dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR, hpssi->XferSize);
00965       }
00966       else
00967       {
00968         /* Update PSSI state */
00969         hpssi->State     = HAL_PSSI_STATE_READY;
00970
00971         /* Update PSSI error code */
00972         hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
00973
00974         /* Process Unlocked */
00975         __HAL_UNLOCK(hpssi);
00976
00977         return HAL_ERROR;
00978       }
00979
00980       if (dmaxferstatus == HAL_OK)
00981       {
00982
00983
00984         /* Update XferCount value */
00985         hpssi->XferCount -= hpssi->XferSize;
00986
00987         /* Process Unlocked */
00988         __HAL_UNLOCK(hpssi);
00989
00990         /* Note : The PSSI interrupts must be enabled after unlocking current process
00991                   to avoid the risk of PSSI interrupt handle execution before current
00992                   process unlock */
00993         /* Enable ERR interrupt */
00994         HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
00995
00996         /* Enable DMA Request */
00997         hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
00998         /* Enable the selected PSSI peripheral */
00999         HAL_PSSI_ENABLE(hpssi);
01000       }
01001       else
01002       {
01003         /* Update PSSI state */
01004         hpssi->State     = HAL_PSSI_STATE_READY;
01005
01006         /* Update PSSI error code */
01007         hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
01008
01009         /* Process Unlocked */
01010         __HAL_UNLOCK(hpssi);
01011
01012         return HAL_ERROR;
01013       }
01014     }
01015     else
01016     {
01017       /* Process Unlocked */
01018       __HAL_UNLOCK(hpssi);
01019
01020       /* Note : The PSSI interrupts must be enabled after unlocking current process
01021                 to avoid the risk of PSSI interrupt handle execution before current
01022                 process unlock */
01023       /* Enable ERRinterrupt */
01024       /* possible to enable all of these */
01025
01026       HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01027     }
01028
01029     return HAL_OK;
01030   }
01031   else
01032   {
01033     return HAL_BUSY;
01034   }
01035 }
01036
01037 /**
01038   * @brief  Receive an amount of data in non-blocking mode with DMA
01039   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01040   *                the configuration information for the specified PSSI.
01041   * @param  pData Pointer to data buffer
01042   * @param  Size Amount of data to be received (in bytes)
01043   * @retval HAL status
01044   */
01045 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
01046 {
01047
01048   HAL_StatusTypeDef dmaxferstatus;
01049
01050   if (hpssi->State == HAL_PSSI_STATE_READY)
01051   {
01052
01053     /* Disable the selected PSSI peripheral */
01054     HAL_PSSI_DISABLE(hpssi);
01055     /* Process Locked */
01056     __HAL_LOCK(hpssi);
01057
01058     hpssi->State       = HAL_PSSI_STATE_BUSY_RX;
01059     hpssi->ErrorCode   = HAL_PSSI_ERROR_NONE;
01060
01061     /* Prepare transfer parameters */
01062     hpssi->pBuffPtr    = pData;
01063     hpssi->XferCount   = Size;
01064
01065     if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
01066     {
01067       hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
01068     }
01069     else
01070     {
01071       hpssi->XferSize = hpssi->XferCount;
01072     }
01073
01074     if (hpssi->XferSize > 0U)
01075     {
01076       if (hpssi->hdmarx != NULL)
01077       {
01078
01079         /* Configure BusWidth */
01080         if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01081         {
01082           MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE |
01083                      ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
01084         }
01085         else
01086         {
01087           MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
01088                      ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
01089         }
01090
01091         /* Set the PSSI DMA transfer complete callback */
01092         hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
01093
01094         /* Set the DMA error callback */
01095         hpssi->hdmarx->XferErrorCallback = PSSI_DMAError;
01096
01097         /* Set the unused DMA callbacks to NULL */
01098         hpssi->hdmarx->XferHalfCpltCallback = NULL;
01099         hpssi->hdmarx->XferAbortCallback = NULL;
01100
01101         /* Enable the DMA  */
01102         dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData, hpssi->XferSize);
01103       }
01104       else
01105       {
01106         /* Update PSSI state */
01107         hpssi->State     = HAL_PSSI_STATE_READY;
01108
01109         /* Update PSSI error code */
01110         hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
01111
01112         /* Process Unlocked */
01113         __HAL_UNLOCK(hpssi);
01114
01115         return HAL_ERROR;
01116       }
01117
01118       if (dmaxferstatus == HAL_OK)
01119       {
01120         /* Update XferCount value */
01121         hpssi->XferCount -= hpssi->XferSize;
01122
01123         /* Process Unlocked */
01124         __HAL_UNLOCK(hpssi);
01125
01126         /* Note : The PSSI interrupts must be enabled after unlocking current process
01127                   to avoid the risk of PSSI interrupt handle execution before current
01128                   process unlock */
01129         /* Enable ERR  interrupt */
01130         HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01131
01132         /* Enable DMA Request */
01133         hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
01134         /* Enable the selected PSSI peripheral */
01135         HAL_PSSI_ENABLE(hpssi);
01136       }
01137       else
01138       {
01139         /* Update PSSI state */
01140         hpssi->State     = HAL_PSSI_STATE_READY;
01141
01142         /* Update PSSI error code */
01143         hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
01144
01145         /* Process Unlocked */
01146         __HAL_UNLOCK(hpssi);
01147
01148         return HAL_ERROR;
01149       }
01150     }
01151     else
01152     {
01153
01154       /* Process Unlocked */
01155       __HAL_UNLOCK(hpssi);
01156
01157       /* Enable ERR,interrupt */
01158       HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01159     }
01160
01161     return HAL_OK;
01162   }
01163   else
01164   {
01165     return HAL_BUSY;
01166   }
01167 }
01168
01169
01170
01171 /**
01172   * @brief  Abort a DMA process communication with Interrupt.
01173   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01174   *                the configuration information for the specified PSSI.
01175   * @retval HAL status
01176   */
01177 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
01178 {
01179
01180   /* Process Locked */
01181   __HAL_LOCK(hpssi);
01182
01183   /* Disable Interrupts */
01184   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01185
01186   /* Set State at HAL_PSSI_STATE_ABORT */
01187   hpssi->State = HAL_PSSI_STATE_ABORT;
01188
01189   /* Abort DMA TX transfer if any */
01190   if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
01191   {
01192     if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
01193     {
01194
01195       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01196
01197       if (hpssi->hdmatx != NULL)
01198       {
01199         /* Set the PSSI DMA Abort callback :
01200         will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01201         hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
01202
01203         /* Abort DMA TX */
01204         if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
01205         {
01206           /* Call Directly XferAbortCallback function in case of error */
01207           hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
01208         }
01209       }
01210
01211     }
01212     /* Abort DMA RX transfer if any */
01213     else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
01214     {
01215
01216       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01217
01218       if (hpssi->hdmarx != NULL)
01219       {
01220         /* Set the PSSI DMA Abort callback :
01221         will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01222         hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
01223
01224         /* Abort DMA RX */
01225         if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
01226         {
01227           /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
01228           hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
01229         }
01230       }
01231     }
01232     else
01233     {
01234       /* Call the error callback */
01235       hpssi->ErrorCallback(hpssi);
01236     }
01237   }
01238
01239
01240   /* Process Unlocked */
01241   __HAL_UNLOCK(hpssi);
01242
01243   /* Note : The PSSI interrupts must be enabled after unlocking current process
01244             to avoid the risk of PSSI interrupt handle execution before current
01245             process unlock */
01246   HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01247
01248   return HAL_OK;
01249
01250 }
01251
01252 /**
01253   * @}
01254   */
01255
01256 /** @defgroup PSSI_Exported_Functions_Group3 IRQ Handler and Callbacks
01257  * @{
01258  */
01259
01260 /**
01261   * @brief  This function handles PSSI event interrupt request.
01262   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01263   *                the configuration information for the specified PSSI.
01264   * @retval None
01265   */
01266 void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
01267 {
01268   /* Overrun/ Underrun Errors */
01269   if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
01270   {
01271     /* Reset handle parameters */
01272
01273     hpssi->XferCount     = 0U;
01274
01275     /* Disable all interrupts */
01276     HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01277
01278
01279     /* Abort DMA TX transfer if any */
01280     if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
01281     {
01282       if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
01283       {
01284         /* Set new error code */
01285         hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN;
01286
01287         hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01288
01289         if (hpssi->hdmatx != NULL)
01290         {
01291           /* Set the PSSI DMA Abort callback :
01292           will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01293           hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
01294
01295           /* Process Unlocked */
01296           __HAL_UNLOCK(hpssi);
01297
01298           /* Abort DMA TX */
01299           if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
01300           {
01301             /* Call Directly XferAbortCallback function in case of error */
01302             hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
01303           }
01304         }
01305
01306       }
01307       /* Abort DMA RX transfer if any */
01308       else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
01309       {
01310         /* Set new error code */
01311         hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN;
01312
01313         hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01314
01315         if (hpssi->hdmarx != NULL)
01316         {
01317           /* Set the PSSI DMA Abort callback :
01318           will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01319           hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
01320
01321           /* Process Unlocked */
01322           __HAL_UNLOCK(hpssi);
01323
01324           /* Abort DMA RX */
01325           if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
01326           {
01327             /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
01328             hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
01329           }
01330         }
01331       }
01332       else
01333       {
01334         /* Call the corresponding callback to inform upper layer of the error */
01335         hpssi->ErrorCallback(hpssi);
01336       }
01337     }
01338
01339     /* If state is an abort treatment on going, don't change state */
01340     if (hpssi->State == HAL_PSSI_STATE_ABORT)
01341     {
01342       hpssi->State = HAL_PSSI_STATE_READY;
01343
01344       /* Process Unlocked */
01345       __HAL_UNLOCK(hpssi);
01346
01347       /* Call the corresponding callback to inform upper layer of End of Transfer */
01348       hpssi->AbortCpltCallback(hpssi);
01349
01350     }
01351     else
01352     {
01353       /* Set HAL_PSSI_STATE_READY */
01354       hpssi->State         = HAL_PSSI_STATE_READY;
01355       /* Process Unlocked */
01356       __HAL_UNLOCK(hpssi);
01357
01358       /* Call the corresponding callback to inform upper layer of End of Transfer */
01359       hpssi->ErrorCallback(hpssi);
01360
01361     }
01362
01363   }
01364 }
01365
01366
01367 /**
01368   * @brief   Tx Transfer complete callback.
01369   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01370   *                the configuration information for the specified PSSI.
01371   * @retval None
01372   */
01373 __weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi)
01374 {
01375   /* Prevent unused argument(s) compilation warning */
01376   UNUSED(hpssi);
01377
01378   /* NOTE : This function should not be modified, when the callback is needed,
01379             the HAL_PSSI_TxCpltCallback can be implemented in the user file
01380    */
01381 }
01382
01383 /**
01384   * @brief   Rx Transfer complete callback.
01385   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01386   *                the configuration information for the specified PSSI.
01387   * @retval None
01388   */
01389 __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
01390 {
01391   /* Prevent unused argument(s) compilation warning */
01392   UNUSED(hpssi);
01393
01394   /* NOTE : This function should not be modified, when the callback is needed,
01395             the HAL_PSSI_RxCpltCallback can be implemented in the user file
01396    */
01397 }
01398
01399
01400 /**
01401   * @brief  PSSI error callback.
01402   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01403   *                the configuration information for the specified PSSI.
01404   * @retval None
01405   */
01406 __weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi)
01407 {
01408   /* Prevent unused argument(s) compilation warning */
01409   UNUSED(hpssi);
01410
01411   /* NOTE : This function should not be modified, when the callback is needed,
01412             the HAL_PSSI_ErrorCallback could be implemented in the user file
01413    */
01414 }
01415
01416 /**
01417   * @brief  PSSI abort callback.
01418   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01419   *                the configuration information for the specified PSSI.
01420   * @retval None
01421   */
01422 __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
01423 {
01424   /* Prevent unused argument(s) compilation warning */
01425   UNUSED(hpssi);
01426
01427   /* NOTE : This function should not be modified, when the callback is needed,
01428             the HAL_PSSI_AbortCpltCallback could be implemented in the user file
01429    */
01430 }
01431
01432 /**
01433   * @}
01434   */
01435
01436 /** @defgroup PSSI_Exported_Functions_Group4 Peripheral State, Mode and Error functions
01437  *  @brief   Peripheral State, Mode and Error functions
01438  *
01439 @verbatim
01440  ===============================================================================
01441             ##### Peripheral State, Mode and Error functions #####
01442  ===============================================================================
01443     [..]
01444     This subsection permit to get in run-time the status of the peripheral
01445     and the data flow.
01446
01447 @endverbatim
01448   * @{
01449   */
01450
01451 /**
01452   * @brief  Return the PSSI handle state.
01453   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01454   *                the configuration information for the specified PSSI.
01455   * @retval HAL state
01456   */
01457 HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
01458 {
01459   /* Return PSSI handle state */
01460   return hpssi->State;
01461 }
01462
01463
01464 /**
01465 * @brief  Return the PSSI error code.
01466   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01467   *              the configuration information for the specified PSSI.
01468 * @retval PSSI Error Code
01469 */
01470 uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
01471 {
01472   return hpssi->ErrorCode;
01473 }
01474
01475 /**
01476   * @}
01477   */
01478
01479 /**
01480   * @}
01481   */
01482
01483 /** @addtogroup PSSI_Private_Functions
01484   * @{
01485   */
01486
01487 /**
01488   * @brief  PSSI Errors process.
01489   * @param  hpssi PSSI handle.
01490   * @param  ErrorCode Error code to handle.
01491   * @retval None
01492   */
01493 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
01494 {
01495
01496   /* Reset handle parameters */
01497
01498   hpssi->XferCount     = 0U;
01499
01500   /* Set new error code */
01501   hpssi->ErrorCode |= ErrorCode;
01502
01503   /* Disable all interrupts */
01504   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01505
01506
01507   /* Abort DMA TX transfer if any */
01508   if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
01509   {
01510     if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
01511     {
01512       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01513
01514       if (hpssi->hdmatx != NULL)
01515       {
01516         /* Set the PSSI DMA Abort callback :
01517         will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01518         hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
01519
01520         /* Process Unlocked */
01521         __HAL_UNLOCK(hpssi);
01522
01523         /* Abort DMA TX */
01524         if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
01525         {
01526           /* Call Directly XferAbortCallback function in case of error */
01527           hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
01528         }
01529       }
01530
01531     }
01532     /* Abort DMA RX transfer if any */
01533     else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
01534     {
01535       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
01536
01537       if (hpssi->hdmarx != NULL)
01538       {
01539         /* Set the PSSI DMA Abort callback :
01540         will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
01541         hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
01542
01543         /* Process Unlocked */
01544         __HAL_UNLOCK(hpssi);
01545
01546         /* Abort DMA RX */
01547         if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
01548         {
01549           /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
01550           hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
01551         }
01552       }
01553     }
01554     else
01555     {
01556       /*Nothing to do*/
01557     }
01558   }
01559
01560   /* If state is an abort treatment on going, don't change state */
01561   if (hpssi->State == HAL_PSSI_STATE_ABORT)
01562   {
01563     hpssi->State = HAL_PSSI_STATE_READY;
01564
01565     /* Process Unlocked */
01566     __HAL_UNLOCK(hpssi);
01567
01568     /* Call the corresponding callback to inform upper layer of End of Transfer */
01569
01570     hpssi->AbortCpltCallback(hpssi);
01571
01572   }
01573   else
01574   {
01575     /* Set HAL_PSSI_STATE_READY */
01576     hpssi->State = HAL_PSSI_STATE_READY;
01577
01578     /* Process Unlocked */
01579     __HAL_UNLOCK(hpssi);
01580
01581     /* Call the corresponding callback to inform upper layer of End of Transfer */
01582     hpssi->ErrorCallback(hpssi);
01583
01584   }
01585 }
01586
01587 /**
01588   * @brief  DMA PSSI slave transmit process complete callback.
01589   * @param  hdma DMA handle
01590   * @retval None
01591   */
01592 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01593 {
01594   PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
01595
01596   uint32_t tmperror;
01597
01598
01599   /* Disable Interrupts */
01600   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01601
01602   /* Store current volatile hpssi->ErrorCode, misra rule */
01603   tmperror = hpssi->ErrorCode;
01604
01605   /* Call the corresponding callback to inform upper layer of End of Transfer */
01606   if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
01607   {
01608     /* Call the corresponding callback to inform upper layer of End of Transfer */
01609     PSSI_Error(hpssi, hpssi->ErrorCode);
01610   }
01611   /* hpssi->State == HAL_PSSI_STATE_BUSY_TX */
01612   else
01613   {
01614     hpssi->State = HAL_PSSI_STATE_READY;
01615
01616     /* Process Unlocked */
01617     __HAL_UNLOCK(hpssi);
01618
01619     /* Call the corresponding callback to inform upper layer of End of Transfer */
01620
01621     hpssi->TxCpltCallback(hpssi);
01622
01623   }
01624
01625
01626 }
01627
01628 /**
01629   * @brief DMA PSSI master receive process complete callback.
01630   * @param  hdma DMA handle
01631   * @retval None
01632   */
01633 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01634 {
01635   PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
01636
01637   uint32_t tmperror;
01638
01639
01640   /* Disable Interrupts */
01641   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01642
01643   /* Store current volatile hpssi->ErrorCode, misra rule */
01644   tmperror = hpssi->ErrorCode;
01645
01646   /* Call the corresponding callback to inform upper layer of End of Transfer */
01647   if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
01648   {
01649     /* Call the corresponding callback to inform upper layer of End of Transfer */
01650     PSSI_Error(hpssi, hpssi->ErrorCode);
01651   }
01652   /* hpssi->State == HAL_PSSI_STATE_BUSY_RX */
01653   else
01654   {
01655     hpssi->State = HAL_PSSI_STATE_READY;
01656
01657     /* Process Unlocked */
01658     __HAL_UNLOCK(hpssi);
01659
01660     /* Call the corresponding callback to inform upper layer of End of Transfer */
01661     hpssi->RxCpltCallback(hpssi);
01662
01663   }
01664
01665
01666 }
01667
01668 /**
01669   * @brief DMA PSSI communication abort callback
01670   *        (To be called at end of DMA Abort procedure).
01671   * @param hdma DMA handle.
01672   * @retval None
01673   */
01674 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
01675 {
01676   PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
01677
01678   /* Reset AbortCpltCallback */
01679   hpssi->hdmatx->XferAbortCallback = NULL;
01680   hpssi->hdmarx->XferAbortCallback = NULL;
01681
01682   /* Check if come from abort from user */
01683   if (hpssi->State == HAL_PSSI_STATE_ABORT)
01684   {
01685     hpssi->State = HAL_PSSI_STATE_READY;
01686
01687     /* Call the corresponding callback to inform upper layer of End of Transfer */
01688
01689     hpssi->AbortCpltCallback(hpssi);
01690
01691   }
01692   else
01693   {
01694     /* Call the corresponding callback to inform upper layer of End of Transfer */
01695     hpssi->ErrorCallback(hpssi);
01696   }
01697 }
01698
01699 /**
01700   * @brief  This function handles PSSI Communication Timeout.
01701   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
01702   *                the configuration information for the specified PSSI.
01703   * @param  Flag Specifies the PSSI flag to check.
01704   * @param  Status The new Flag status (SET or RESET).
01705   * @param  Timeout Timeout duration
01706   * @param  Tickstart Tick start value
01707   * @retval HAL status
01708   */
01709 static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
01710 {
01711   while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
01712   {
01713     /* Check for the Timeout */
01714     if (Timeout != HAL_MAX_DELAY)
01715     {
01716       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
01717       {
01718         hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT;
01719         hpssi->State = HAL_PSSI_STATE_READY;
01720
01721         /* Process Unlocked */
01722         __HAL_UNLOCK(hpssi);
01723
01724         return HAL_ERROR;
01725       }
01726     }
01727   }
01728   return HAL_OK;
01729 }
01730 void PSSI_DMAError(DMA_HandleTypeDef *hdma)
01731 {
01732   PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
01733
01734   uint32_t tmperror;
01735
01736
01737   /* Disable the selected PSSI peripheral */
01738   HAL_PSSI_DISABLE(hpssi);
01739
01740   /* Disable Interrupts */
01741   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
01742
01743   /* Store current volatile hpssi->ErrorCode, misra rule */
01744   tmperror = hpssi->ErrorCode;
01745
01746   /* Call the corresponding callback to inform upper layer of End of Transfer */
01747   if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
01748   {
01749     /* Call the corresponding callback to inform upper layer of End of Transfer */
01750     PSSI_Error(hpssi, hpssi->ErrorCode);
01751   }
01752   else
01753   {
01754     hpssi->State = HAL_PSSI_STATE_READY;
01755
01756     /* Process Unlocked */
01757     __HAL_UNLOCK(hpssi);
01758
01759     /* Call the corresponding callback to inform upper layer of End of Transfer */
01760     hpssi->ErrorCallback(hpssi);
01761
01762   }
01763
01764 }
01765
01766
01767
01768 /**
01769   * @}
01770   */
01771 #endif /* PSSI */
01772 #endif /* HAL_PSSI_MODULE_ENABLED */
01773 /**
01774   * @}
01775   */
01776
01777 /**
01778   * @}
01779   */
01780
01781 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pssi.h Source File

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stm32h7xx_hal_pssi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pssi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PSSI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_PSSI_H
00022 #define STM32H7xx_HAL_PSSI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined(PSSI)
00035 /** @addtogroup PSSI PSSI
00036   * @brief PSSI HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup PSSI_Exported_Types PSSI Exported Types
00042   * @{
00043   */
00044
00045
00046 /**
00047   * @brief PSSI Init structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t  DataWidth;          /* !< Configures the parallel bus width 8 lines or 16 lines */
00052   uint32_t  BusWidth;           /* !< Configures the parallel bus width 8 lines or 16 lines */
00053   uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready */
00054   uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity */
00055   uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
00056   uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity */
00057
00058 } PSSI_InitTypeDef;
00059
00060
00061 /**
00062   * @brief  HAL PSSI State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_PSSI_STATE_RESET   = 0x00U, /* !< PSSI not yet initialized or disabled     */
00067   HAL_PSSI_STATE_READY   = 0x01U, /* !< Peripheral initialized and ready for use */
00068   HAL_PSSI_STATE_BUSY    = 0x02U, /* !< An internal process is ongoing           */
00069   HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing              */
00070   HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing               */
00071   HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state                            */
00072   HAL_PSSI_STATE_ERROR   = 0x06U, /* !< PSSI state error                         */
00073   HAL_PSSI_STATE_ABORT   = 0x07U, /* !< PSSI process is aborted                  */
00074
00075 } HAL_PSSI_StateTypeDef;
00076
00077 /**
00078   * @brief  PSSI handle Structure definition
00079   */
00080 typedef struct __PSSI_HandleTypeDef
00081 {
00082   PSSI_TypeDef         *Instance;    /*!< PSSI register base address.    */
00083   PSSI_InitTypeDef      Init;        /*!< PSSI Initialization Structure. */
00084   uint32_t             *pBuffPtr;    /*!< PSSI Data buffer.              */
00085   uint32_t              XferCount;   /*!< PSSI transfer count            */
00086   uint32_t              XferSize;    /*!< PSSI  transfer size            */
00087   DMA_HandleTypeDef    *hdmatx;      /*!< PSSI Tx DMA Handle parameters  */
00088   DMA_HandleTypeDef    *hdmarx;      /*!< PSSI Rx DMA Handle parameters  */
00089
00090   void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
00091   void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
00092   void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi);     /*!< PSSI transfer complete callback. */
00093   void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback.    */
00094
00095   void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi);   /*!< PSSI Msp Init callback.          */
00096   void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback.        */
00097
00098   HAL_LockTypeDef             Lock;                               /*!< PSSI lock.                       */
00099   __IO HAL_PSSI_StateTypeDef State;                               /*!< PSSI transfer state.             */
00100   __IO uint32_t               ErrorCode;                          /*!< PSSI error code.                 */
00101
00102 } PSSI_HandleTypeDef;
00103
00104
00105 /**
00106   * @brief  HAL PSSI Callback pointer definition
00107   */
00108 typedef  void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi);  /*!< Pointer to a PSSI common callback function */
00109
00110 /**
00111   * @}
00112   */
00113 /**
00114   * @brief  HAL PSSI Callback ID enumeration definition
00115   */
00116 typedef enum
00117 {
00118   HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID  */
00119   HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID  */
00120   HAL_PSSI_ERROR_CB_ID       = 0x03U, /*!< PSSI Error callback ID                  */
00121   HAL_PSSI_ABORT_CB_ID       = 0x04U, /*!< PSSI Abort callback ID                  */
00122
00123   HAL_PSSI_MSPINIT_CB_ID     = 0x05U, /*!< PSSI Msp Init callback ID               */
00124   HAL_PSSI_MSPDEINIT_CB_ID   = 0x06U  /*!< PSSI Msp DeInit callback ID             */
00125
00126 } HAL_PSSI_CallbackIDTypeDef;
00127
00128 /* Exported constants --------------------------------------------------------*/
00129 /** @defgroup PSSI_Exported_Constants PSSI Exported Constants
00130   * @{
00131   */
00132
00133 /** @defgroup PSSI_Error_Code PSSI Error Code
00134   * @{
00135   */
00136 #define HAL_PSSI_ERROR_NONE             0x00000000U /*!< No error                */
00137 #define HAL_PSSI_ERROR_NOT_SUPPORTED    0x00000001U /*!< Not supported operation */
00138 #define HAL_PSSI_ERROR_UNDER_RUN        0x00000002U /*!< FIFO Under-run error    */
00139 #define HAL_PSSI_ERROR_OVER_RUN         0x00000004U /*!< FIFO Over-run  error    */
00140 #define HAL_PSSI_ERROR_DMA              0x00000008U /*!< Dma     error           */
00141 #define HAL_PSSI_ERROR_TIMEOUT          0x00000010U /*!< Timeout error           */
00142 #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error  */
00143
00144
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup PSSI_DATA_WIDTH PSSI Data Width
00150   * @{
00151   */
00152
00153 #define HAL_PSSI_8BITS                  0x00000000U   /*!<  8 Bits  */
00154 #define HAL_PSSI_16BITS                 0x00000001U   /*!< 16 Bits  */
00155 #define HAL_PSSI_32BITS                 0x00000002U   /*!< 32 Bits  */
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup PSSI_BUS_WIDTH PSSI Bus Width
00161   * @{
00162   */
00163
00164 #define HAL_PSSI_8LINES                 0x00000000U   /*!< 8 data lines  */
00165 #define HAL_PSSI_16LINES                PSSI_CR_EDM   /*!< 16 data lines */
00166 /**
00167   * @}
00168   */
00169 /** @defgroup PSSI_MODE PSSI mode
00170   * @{
00171   */
00172 #define HAL_PSSI_UNIDIRECTIONAL         0x00000000U /*!< Uni-directional mode */
00173 #define HAL_PSSI_BIDIRECTIONAL          0x00000001U /*!< Bi-directional mode  */
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup PSSI_ControlSignal Configuration
00179   * @{
00180   */
00181 #define HAL_PSSI_DE_RDY_DISABLE           (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */
00182 #define HAL_PSSI_RDY_ENABLE               (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */
00183 #define HAL_PSSI_DE_ENABLE                (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */
00184 #define HAL_PSSI_DE_RDY_ALT_ENABLE        (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */
00185 #define HAL_PSSI_MAP_RDY_BIDIR_ENABLE     (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */
00186 #define HAL_PSSI_RDY_MAP_ENABLE           (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */
00187 #define HAL_PSSI_DE_MAP_ENABLE            (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */
00188 #define HAL_PSSI_MAP_DE_BIDIR_ENABLE      (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */
00189
00190 /**
00191   * @}
00192   */
00193
00194
00195 /** @defgroup PSSI_Data_Enable_Polarity Data Enable Polarity
00196   * @{
00197   */
00198 #define HAL_PSSI_DEPOL_ACTIVE_LOW         0x0U            /*!< Active Low */
00199 #define HAL_PSSI_DEPOL_ACTIVE_HIGH        PSSI_CR_DEPOL   /*!< Active High */
00200 /**
00201   * @}
00202   */
00203 /** @defgroup PSSI_Reday_Polarity Reday Polarity
00204   * @{
00205   */
00206 #define HAL_PSSI_RDYPOL_ACTIVE_LOW        0x0U            /*!< Active Low */
00207 #define HAL_PSSI_RDYPOL_ACTIVE_HIGH       PSSI_CR_RDYPOL  /*!< Active High */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup PSSI_Clock_Polarity Clock Polarity
00213   * @{
00214   */
00215 #define HAL_PSSI_FALLING_EDGE             0x0U            /*!< Fallling Edge */
00216 #define HAL_PSSI_RISING_EDGE              0x1U            /*!< Rising Edge */
00217
00218
00219 /**
00220   * @}
00221   */
00222
00223
00224 /** @defgroup PSSI_DEFINITION PSSI definitions
00225   * @{
00226   */
00227
00228 #define PSSI_MAX_NBYTE_SIZE         0x10000U         /* 64 KB */
00229 #define PSSI_TIMEOUT_TRANSMIT       0x0000FFFFU      /*!< Timeout Value   */
00230
00231 #define PSSI_CR_OUTEN_INPUT         0x00000000U      /*!< Input Mode      */
00232 #define PSSI_CR_OUTEN_OUTPUT        PSSI_CR_OUTEN    /*!< Output Mode     */
00233
00234 #define PSSI_CR_DMA_ENABLE          PSSI_CR_DMAEN    /*!< DMA Mode Enable */
00235 #define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */
00236
00237 #define PSSI_CR_16BITS              PSSI_CR_EDM      /*!< 16 Lines Mode   */
00238 #define PSSI_CR_8BITS               (~PSSI_CR_EDM)   /*!< 8 Lines Mode    */
00239
00240 #define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag*/
00241 #define PSSI_FLAG_RTT4B             PSSI_SR_RTT4B    /*!< 4 Bytes Fifo Flag*/
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup PSSI_Interrupts PSSI Interrupts
00247   * @{
00248   */
00249
00250 #define PSSI_FLAG_OVR_RIS            PSSI_RIS_OVR_RIS     /*!< Overrun, Underrun errors flag */
00251 #define PSSI_FLAG_MASK               PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */
00252 #define PSSI_FLAG_OVR_MIS            PSSI_MIS_OVR_MIS     /*!< Overrun, Underrun masked errors flag */
00253 /**
00254   * @}
00255   */
00256 /**
00257   * @}
00258   */
00259 /* Exported macros ------------------------------------------------------------*/
00260 /** @defgroup PSSI_Exported_Macros PSSI Exported Macros
00261   * @{
00262   */
00263
00264 /** @brief Reset PSSI handle state
00265   * @param  __HANDLE__ specifies the PSSI handle.
00266   * @retval None
00267   */
00268
00269 #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00270                                                       (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
00271                                                       (__HANDLE__)->MspInitCallback = NULL;       \
00272                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
00273                                                      }while(0)
00274
00275
00276 /**
00277   * @brief  Enable the PSSI.
00278   * @param  __HANDLE__ PSSI handle
00279   * @retval None.
00280   */
00281 #define HAL_PSSI_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
00282 /**
00283   * @brief  Disable the PSSI.
00284   * @param  __HANDLE__ PSSI handle
00285   * @retval None.
00286   */
00287 #define HAL_PSSI_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
00288
00289 /* PSSI pripheral STATUS */
00290 /**
00291   * @brief  Get the PSSI pending flags.
00292   * @param  __HANDLE__ PSSI handle
00293   * @param  __FLAG__ flag to check.
00294   *          This parameter can be any combination of the following values:
00295   *            @arg PSSI_FLAG_RTT1B:  FIFO is ready to transfer one byte
00296   *            @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes
00297   * @retval The state of FLAG.
00298   */
00299
00300 #define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
00301
00302
00303
00304 /* Interrupt & Flag management */
00305 /**
00306   * @brief  Get the PSSI pending flags.
00307   * @param  __HANDLE__ PSSI handle
00308   * @param  __FLAG__ flag to check.
00309   *          This parameter can be any combination of the following values:
00310   *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
00311   * @retval The state of FLAG.
00312   */
00313 #define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
00314
00315 /**
00316   * @brief  Clear the PSSI pending flags.
00317   * @param  __HANDLE__ PSSI handle
00318   * @param  __FLAG__ specifies the flag to clear.
00319   *          This parameter can be any combination of the following values:
00320   *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
00321   * @retval None
00322   */
00323 #define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00324
00325 /**
00326   * @brief  Enable the specified PSSI interrupts.
00327   * @param  __HANDLE__ PSSI handle
00328   * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled.
00329   *          This parameter can be any combination of the following values:
00330   *            @arg PSSI_FLAG_OVR_RIS: Configuration error mask
00331   * @retval None
00332   */
00333 #define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00334
00335 /**
00336   * @brief  Disable the specified PSSI interrupts.
00337   * @param  __HANDLE__ PSSI handle
00338   * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled.
00339   *          This parameter can be any combination of the following values:
00340   *            @arg PSSI_IT_OVR_IE: Configuration error mask
00341   * @retval None
00342   */
00343 #define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00344
00345 /**
00346   * @brief  Check whether the specified PSSI interrupt source is enabled or not.
00347   * @param  __HANDLE__ PSSI handle
00348   * @param  __INTERRUPT__ specifies the PSSI interrupt source to check.
00349   *          This parameter can be one of the following values:
00350   *            @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask
00351   * @retval The state of INTERRUPT source.
00352   */
00353 #define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00354
00355 /**
00356   * @brief  Check whether the PSSI Control signal is valid.
00357   * @param  __CONTROL__ Control signals configuration
00358   * @retval Valid or not.
00359   */
00360
00361 #define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE        ) || \
00362                                              ((__CONTROL__) == HAL_PSSI_RDY_ENABLE            ) || \
00363                                              ((__CONTROL__) == HAL_PSSI_DE_ENABLE             ) || \
00364                                              ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE     ) || \
00365                                              ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE  ) || \
00366                                              ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \
00367                                              ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \
00368                                              ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))
00369 /**
00370   * @brief  Check whether the PSSI Bus Width is valid.
00371   * @param  __BUSWIDTH__ PSSI Bush width
00372   * @retval Valid or not.
00373   */
00374
00375 #define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES    ) || \
00376                                         ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))
00377
00378 /**
00379   * @brief  Check whether the PSSI Clock Polarity is valid.
00380   * @param  __CLOCKPOL__ PSSI Clock Polarity
00381   * @retval Valid or not.
00382   */
00383
00384 #define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \
00385                                               ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))
00386 /**
00387   * @brief  Check whether the PSSI Data Enable Polarity is valid.
00388   * @param  __DEPOL__ PSSI DE Polarity
00389   * @retval Valid or not.
00390   */
00391
00392 #define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \
00393                                         ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))
00394 /**
00395   * @brief  Check whether the PSSI Ready Polarity is valid.
00396   * @param  __RDYPOL__ PSSI RDY Polarity
00397   * @retval Valid or not.
00398   */
00399
00400 #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \
00401                                          ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))
00402 /**
00403   * @}
00404   */
00405
00406 /* Exported functions --------------------------------------------------------*/
00407 /** @addtogroup PSSI_Exported_Functions
00408   * @{
00409   */
00410
00411 /** @addtogroup PSSI_Exported_Functions_Group1
00412   * @{
00413   */
00414 /* Initialization and de-initialization functions *******************************/
00415 HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
00416 HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
00417 void              HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
00418 void              HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
00419 /* Callbacks Register/UnRegister functions  ***********************************/
00420
00421 HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);
00422 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
00423 /**
00424   * @}
00425   */
00426
00427 /** @addtogroup PSSI_Exported_Functions_Group2
00428   * @{
00429   */
00430 /* IO operation functions *******************************************************/
00431 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
00432 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
00433 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
00434 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
00435 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
00436 void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
00437 /**
00438   * @}
00439   */
00440
00441 /** @addtogroup PSSI_Exported_Functions_Group3
00442   * @{
00443   */
00444 void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
00445 void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
00446 void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
00447 void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
00448 /**
00449   * @}
00450   */
00451
00452 /** @addtogroup PSSI_Exported_Functions_Group4
00453   * @{
00454   */
00455 /* Peripheral State functions ***************************************************/
00456 HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
00457 uint32_t              HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
00458 /**
00459   * @}
00460   */
00461
00462 /**
00463   * @}
00464   */
00465
00466 /* Private constants ---------------------------------------------------------*/
00467
00468
00469 /* Private macros ------------------------------------------------------------*/
00470
00471
00472 /**
00473   * @}
00474   */
00475 #endif /* PSSI */
00476
00477 /**
00478   * @}
00479   */
00480
00481
00482 #ifdef __cplusplus
00483 }
00484 #endif
00485
00486 #endif /* STM32H7xx_HAL_PSSI_H */
00487
00488
00489 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr.c Source File

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stm32h7xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization and de-initialization functions.
00009   *           + Peripheral Control functions.
00010   *           + Interrupt Handling functions.
00011   @verbatim
00012   ==============================================================================
00013                         ##### PWR peripheral overview #####
00014   ==============================================================================
00015   [..]
00016    (#) The Power control (PWR) provides an overview of the supply architecture
00017        for the different power domains and of the supply configuration
00018        controller.
00019        In the H7 family, the number of power domains is different between
00020        device lines. This difference is due to characteristics of each device.
00021
00022    (#) Domain architecture overview for the different H7 lines:
00023       (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
00024           These devices have 3 power domains (D1, D2 and D3).
00025           The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
00026           peripherals. The D2 domain contains peripherals and a CPU
00027           (Cortex-M4). The D3 domain contains the system control, I/O logic
00028           and low-power peripherals.
00029       (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
00030           domains (D1, D2 and D3).
00031           The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
00032           peripherals. The D2 domain contains peripherals. The D3 domains
00033           contains the system control, I/O logic and low-power peripherals.
00034       (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
00035           power domains (CD and SRD).
00036           The core domain (CD) contains a CPU (Cortex-M7), a Flash
00037           memory and peripherals. The SmartRun domain contains the system
00038           control, I/O logic and low-power peripherals.
00039
00040    (#) Every entity have low power mode as decribed below :
00041    (#) The CPU low power modes are :
00042       (+) CPU CRUN.
00043       (+) CPU CSLEEP.
00044       (+) CPU CSTOP.
00045    (#) The domain low power modes are :
00046       (+) DRUN.
00047       (+) DSTOP.
00048       (+) DSTANDBY.
00049    (#) The SYSTEM low power modes are :
00050       (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
00051                  Standby. In Run* mode, the performance is limited and the
00052                  system supply configuration shall be programmed. The system
00053                  enters Run mode only when the ACTVOSRDY bit in PWR control
00054                  status register 1 (PWR_CSR1) is set to 1.
00055       (+) RUN.
00056       (+) STOP.
00057       (+) STANDBY.
00058
00059   ==============================================================================
00060                         ##### How to use this driver #####
00061   ==============================================================================
00062   [..]
00063    (#) Power management peripheral is active by default at startup level in
00064        STM32h7xx lines.
00065
00066    (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
00067        to enable/disable access to the backup domain (RTC registers, RTC backup
00068        data registers and backup SRAM).
00069
00070    (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
00071        mode and voltage threshold) in order to set up the Power Voltage Detector,
00072        then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
00073        and stop the PVD detection.
00074        (+) PVD level could be one of the following values :
00075              (++) 1V95
00076              (++) 2V1
00077              (++) 2V25
00078              (++) 2V4
00079              (++) 2V55
00080              (++) 2V7
00081              (++) 2V85
00082              (++) External voltage level
00083
00084    (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
00085        with the right parameter to configure the wake up pin polarity (Low or
00086        High) and to enable and disable it.
00087
00088    (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
00089        mode. Wake-up from SLEEP mode could be following to an event or an
00090        interrupt according to low power mode intrinsic request called (__WFI()
00091        or __WFE()).
00092        Please ensure to clear all CPU pending events by calling
00093        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
00094        in SLEEP mode with __WFE() entry.
00095
00096    (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
00097        mode for single core devices. For dual core devices, this API will enter
00098        the domain (containing Cortex-Mx that executing this function) in DSTOP
00099        mode. According to the used parameter, user could select the regulator to
00100        be kept actif in low power mode and wake-up event type.
00101        Please ensure to clear all CPU pending events by calling
00102        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
00103        in CSTOP mode with __WFE() entry.
00104
00105    (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
00106        STANDBY mode for single core devices. For dual core devices, this API
00107        will enter the domain (containing Cortex-Mx that executing this function)
00108        in DSTANDBY mode.
00109
00110    (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
00111        enable and disable the Cortex-Mx re-entring in SLEEP mode after an
00112        interruption handling is over.
00113
00114    (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
00115        to configure the Cortex-Mx to wake-up after any pending event / interrupt
00116        even if it's disabled or has insufficient priority to cause exception
00117        entry.
00118
00119    (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
00120        request.
00121
00122      *** PWR HAL driver macros list ***
00123      =============================================
00124      [..]
00125        Below the list of most used macros in PWR HAL driver.
00126
00127       (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
00128                                               regulator output voltage.
00129       (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
00130       (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
00131
00132   @endverbatim
00133   ******************************************************************************
00134   * @attention
00135   *
00136   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00137   * All rights reserved.</center></h2>
00138   *
00139   * This software component is licensed by ST under BSD 3-Clause license,
00140   * the "License"; You may not use this file except in compliance with the
00141   * License. You may obtain a copy of the License at:
00142   *                        opensource.org/licenses/BSD-3-Clause
00143   *
00144   ******************************************************************************
00145   */
00146
00147 /* Includes ------------------------------------------------------------------*/
00148 #include "stm32h7xx_hal.h"
00149
00150 /** @addtogroup STM32H7xx_HAL_Driver
00151   * @{
00152   */
00153
00154 /** @defgroup PWR PWR
00155   * @brief PWR HAL module driver
00156   * @{
00157   */
00158
00159 #ifdef HAL_PWR_MODULE_ENABLED
00160
00161 /* Private typedef -----------------------------------------------------------*/
00162 /* Private define ------------------------------------------------------------*/
00163
00164 /** @addtogroup PWR_Private_Constants PWR Private Constants
00165   * @{
00166   */
00167
00168 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00169   * @{
00170   */
00171 #if !defined (DUAL_CORE)
00172 #define PVD_MODE_IT              (0x00010000U)
00173 #define PVD_MODE_EVT             (0x00020000U)
00174 #endif /* !defined (DUAL_CORE) */
00175
00176 #define PVD_RISING_EDGE          (0x00000001U)
00177 #define PVD_FALLING_EDGE         (0x00000002U)
00178 #define PVD_RISING_FALLING_EDGE  (0x00000003U)
00179 /**
00180   * @}
00181   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /* Private macro -------------------------------------------------------------*/
00188 /* Private variables ---------------------------------------------------------*/
00189 /* Private function prototypes -----------------------------------------------*/
00190 /* Private functions ---------------------------------------------------------*/
00191
00192 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00193   * @{
00194   */
00195
00196 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
00197   * @brief    Initialization and De-Initialization functions
00198   *
00199 @verbatim
00200  ===============================================================================
00201               ##### Initialization and De-Initialization Functions #####
00202  ===============================================================================
00203     [..]
00204       This section provides functions allowing to deinitialize power peripheral.
00205
00206     [..]
00207       After system reset, the backup domain (RTC registers, RTC backup data
00208       registers and backup SRAM) is protected against possible unwanted write
00209       accesses.
00210       The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
00211       domain.
00212       The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
00213       domain.
00214
00215 @endverbatim
00216   * @{
00217   */
00218
00219 /**
00220   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
00221   *         values.
00222   * @note   This functionality is not available in this product.
00223   *         The prototype is kept just to maintain compatibility with other
00224   *         products.
00225   * @retval None.
00226   */
00227 void HAL_PWR_DeInit (void)
00228 {
00229 }
00230
00231 /**
00232   * @brief  Enable access to the backup domain (RTC registers, RTC backup data
00233   *         registers and backup SRAM).
00234   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00235   *         Backup Domain Access should be kept enabled.
00236   * @retval None.
00237   */
00238 void HAL_PWR_EnableBkUpAccess (void)
00239 {
00240   /* Enable access to RTC and backup registers */
00241   SET_BIT (PWR->CR1, PWR_CR1_DBP);
00242 }
00243
00244 /**
00245   * @brief  Disable access to the backup domain (RTC registers, RTC backup data
00246   *         registers and backup SRAM).
00247   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00248   *         Backup Domain Access should be kept enabled.
00249   * @retval None.
00250   */
00251 void HAL_PWR_DisableBkUpAccess (void)
00252 {
00253   /* Disable access to RTC and backup registers */
00254   CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
00255 }
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
00261   *  @brief   Power Control functions
00262   *
00263 @verbatim
00264  ===============================================================================
00265                  ##### Peripheral Control Functions #####
00266  ===============================================================================
00267     [..]
00268       This section provides functions allowing to control power peripheral.
00269
00270     *** PVD configuration ***
00271     =========================
00272     [..]
00273       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00274           threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
00275           register).
00276
00277       (+) A PVDO flag is available to indicate if VDD is higher or lower
00278           than the PVD threshold. This event is internally connected to the EXTI
00279           line 16 to generate an interrupt if enabled.
00280           It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
00281
00282       (+) The PVD is stopped in STANDBY mode.
00283
00284     *** Wake-up pin configuration ***
00285     =================================
00286     [..]
00287       (+) Wake-up pin is used to wake up the system from STANDBY mode.
00288           The pin pull is configurable through the WKUPEPR register to be in
00289           No-pull, Pull-up and Pull-down.
00290           The pin polarity is configurable through the WKUPEPR register to be
00291           active on rising or falling edges.
00292
00293       (+) There are up to six Wake-up pin in the STM32H7 devices family.
00294
00295     *** Low Power modes configuration ***
00296     =====================================
00297     [..]
00298      The device present 3 principles low-power modes features:
00299       (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
00300                          active (Powered and Clocked).
00301
00302       (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
00303                          regulator is running. The Main regulator or the LP
00304                          regulator could be selected.
00305
00306       (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
00307                          supply regulator is powered off.
00308
00309    *** SLEEP mode ***
00310    ==================
00311     [..]
00312       (+) Entry:
00313         The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
00314         SLEEPEntry) function.
00315
00316           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
00317           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
00318
00319       -@@- The Regulator parameter is not used for the STM32H7 family
00320               and is kept as parameter just to maintain compatibility with the
00321               lower power families (STM32L).
00322
00323       (+) Exit:
00324         Any peripheral interrupt acknowledged by the nested vectored interrupt
00325         controller (NVIC) can wake up the device from SLEEP mode.
00326
00327    *** STOP mode ***
00328    =================
00329     [..]
00330       In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
00331       the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
00332       register contents are preserved.
00333       The voltage regulator can be configured either in normal or low-power mode.
00334       To minimize the consumption in STOP mode, FLASH can be powered off before
00335       entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
00336       It can be switched on again by software after exiting the STOP mode using
00337       the HAL_PWREx_DisableFlashPowerDown() function.
00338
00339       (+) Entry:
00340          The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
00341          STOPEntry) function with:
00342
00343          (++) Regulator:
00344           (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
00345           (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
00346
00347          (++) STOPEntry:
00348           (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
00349           (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
00350
00351       (+) Exit:
00352          Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00353
00354    *** STANDBY mode ***
00355    ====================
00356     [..]
00357     (+)
00358       The system STANDBY mode allows to achieve the lowest power consumption.
00359       It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
00360       disabled. The system is consequently powered off. The PLL, the HSI
00361       oscillator and the HSE oscillator are also switched off. SRAM and register
00362       contents are lost except for the RTC registers, RTC backup registers,
00363       backup SRAM and standby circuitry.
00364
00365     [..]
00366       The voltage regulator is OFF.
00367
00368       (++) Entry:
00369         (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
00370               function.
00371
00372       (++) Exit:
00373         (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
00374               RTC wakeup, tamper event, time stamp event, external reset in NRST
00375               pin, IWDG reset.
00376
00377    *** Auto-wakeup (AWU) from low-power mode ***
00378    =============================================
00379     [..]
00380      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
00381          RTC Wakeup event, a tamper event or a time-stamp event, without
00382          depending on an external interrupt (Auto-wakeup mode).
00383
00384      (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
00385
00386        (++) To wake up from the STOP mode with an RTC alarm event, it is
00387             necessary to configure the RTC to generate the RTC alarm using the
00388             HAL_RTC_SetAlarm_IT() function.
00389
00390        (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
00391             it is necessary to configure the RTC to detect the tamper or time
00392             stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
00393             HAL_RTCEx_SetTamper_IT() functions.
00394
00395        (++) To wake up from the STOP mode with an RTC WakeUp event, it is
00396             necessary to configure the RTC to generate the RTC WakeUp event
00397             using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00398
00399 @endverbatim
00400   * @{
00401   */
00402
00403 /**
00404   * @brief  Configure the event mode and the voltage threshold detected by the
00405   *         Programmable Voltage Detector(PVD).
00406   * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
00407   *                      the configuration information for the PVD.
00408   * @note   Refer to the electrical characteristics of your device datasheet for
00409   *         more details about the voltage threshold corresponding to each
00410   *         detection level.
00411   * @note   For dual core devices, please ensure to configure the EXTI lines for
00412   *         the different Cortex-Mx through PWR_Exported_Macro provided by this
00413   *         driver. All combination are allowed: wake up only Cortex-M7, wake up
00414   *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
00415   * @retval None.
00416   */
00417 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
00418 {
00419   /* Check the PVD configuration parameter */
00420   if (sConfigPVD == NULL)
00421   {
00422     return;
00423   }
00424
00425   /* Check the parameters */
00426   assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
00427   assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
00428
00429   /* Set PLS[7:5] bits according to PVDLevel value */
00430   MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
00431
00432   /* Clear previous config */
00433 #if !defined (DUAL_CORE)
00434   __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
00435   __HAL_PWR_PVD_EXTI_DISABLE_IT ();
00436 #endif /* !defined (DUAL_CORE) */
00437
00438   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
00439   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
00440
00441 #if !defined (DUAL_CORE)
00442   /* Interrupt mode configuration */
00443   if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00444   {
00445     __HAL_PWR_PVD_EXTI_ENABLE_IT ();
00446   }
00447
00448   /* Event mode configuration */
00449   if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00450   {
00451     __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
00452   }
00453 #endif /* !defined (DUAL_CORE) */
00454
00455   /* Rising edge configuration */
00456   if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00457   {
00458     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
00459   }
00460
00461   /* Falling edge configuration */
00462   if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00463   {
00464     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
00465   }
00466 }
00467
00468 /**
00469   * @brief Enable the Programmable Voltage Detector (PVD).
00470   * @retval None.
00471   */
00472 void HAL_PWR_EnablePVD (void)
00473 {
00474   /* Enable the power voltage detector */
00475   SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
00476 }
00477
00478 /**
00479   * @brief Disable the Programmable Voltage Detector (PVD).
00480   * @retval None.
00481   */
00482 void HAL_PWR_DisablePVD (void)
00483 {
00484   /* Disable the power voltage detector */
00485   CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
00486 }
00487
00488 /**
00489   * @brief  Enable the WakeUp PINx functionality.
00490   * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
00491   *          This parameter can be one of the following legacy values, which
00492   *          sets the default (rising edge):
00493   *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
00494   *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
00495   *          or one of the following values where the user can explicitly states
00496   *          the enabled pin and the chosen polarity:
00497   *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
00498   *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
00499   *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
00500   *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
00501   *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
00502   *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
00503   * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00504   * @retval None.
00505   */
00506 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
00507 {
00508   /* Check the parameters */
00509   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
00510
00511   /*
00512      Enable and Specify the Wake-Up pin polarity and the pull configuration
00513      for the event detection (rising or falling edge).
00514   */
00515   MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
00516 }
00517
00518 /**
00519   * @brief  Disable the WakeUp PINx functionality.
00520   * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
00521   *          This parameter can be one of the following values:
00522   *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
00523   *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
00524   *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
00525   *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
00526   *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
00527   *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
00528   *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
00529   *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
00530   * @retval None.
00531   */
00532 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
00533 {
00534   /* Check the parameters */
00535   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
00536
00537   /* Disable the wake up pin selected */
00538   CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
00539 }
00540
00541 /**
00542   * @brief  Enter the current core in SLEEP mode (CSLEEP).
00543   * @param  Regulator : Specifies the regulator state in SLEEP mode.
00544   *          This parameter can be one of the following values:
00545   *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
00546   *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
00547   *                                           regulator ON.
00548   * @note   This parameter is not used for the STM32H7 family and is kept as
00549   *         parameter just to maintain compatibility with the lower power
00550   *         families.
00551   * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
00552   *                      intrinsic instruction.
00553   *          This parameter can be one of the following values:
00554   *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
00555   *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
00556   * @note   Ensure to clear pending events before calling this API through
00557   *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
00558   * @retval None.
00559   */
00560 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
00561 {
00562   /* Check the parameters */
00563   assert_param (IS_PWR_REGULATOR (Regulator));
00564   assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
00565
00566   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00567   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00568
00569   /* Select SLEEP mode entry */
00570   if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
00571   {
00572     /* Request Wait For Interrupt */
00573     __WFI ();
00574   }
00575   else
00576   {
00577     /* Request Wait For Event */
00578     __WFE ();
00579   }
00580 }
00581
00582 /**
00583   * @brief  Enter STOP mode.
00584   * @note   For single core devices, this API will enter the system in STOP mode
00585   *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
00586   *         cleared.
00587   *         For dual core devices, this API will enter the domain (containing
00588   *         Cortex-Mx that executing this function) in DSTOP mode. If all
00589   *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
00590   *         cleared, all the system will enter in STOP mode.
00591   * @param  Regulator : Specifies the regulator state in STOP mode.
00592   *          This parameter can be one of the following values:
00593   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
00594   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
00595   *                                            regulator ON.
00596   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
00597   *                     intrinsic instruction.
00598   *          This parameter can be one of the following values:
00599   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
00600   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
00601   * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
00602   * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
00603   *         event, the HSI RC oscillator is selected as default system wakeup
00604   *         clock.
00605   * @note   In System STOP mode, when the voltage regulator operates in low
00606   *         power mode, an additional startup delay is incurred when the system
00607   *         is waking up. By keeping the internal regulator ON during STOP mode,
00608   *         the consumption is higher although the startup time is reduced.
00609   * @retval None.
00610   */
00611 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
00612 {
00613   /* Check the parameters */
00614   assert_param (IS_PWR_REGULATOR (Regulator));
00615   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
00616
00617   /* Select the regulator state in STOP mode */
00618   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
00619
00620   /* Configure the PWR mode for the different Domains */
00621 #if defined (DUAL_CORE)
00622   /* Check CPU ID */
00623   if (HAL_GetCurrentCPUID () == CM7_CPUID)
00624   {
00625     /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
00626     CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
00627   }
00628   else
00629   {
00630     /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
00631     CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
00632   }
00633 #else /* Single core devices */
00634   /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
00635   CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
00636
00637 #if defined (PWR_CPUCR_PDDS_D2)
00638   /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
00639   CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00640 #endif /* PWR_CPUCR_PDDS_D2 */
00641 #endif /* defined (DUAL_CORE) */
00642
00643   /* Set SLEEPDEEP bit of Cortex System Control Register */
00644   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00645
00646   /* Ensure that all instructions are done before entering STOP mode */
00647   __DSB ();
00648   __ISB ();
00649
00650   /* Select STOP mode entry */
00651   if (STOPEntry == PWR_STOPENTRY_WFI)
00652   {
00653     /* Request Wait For Interrupt */
00654     __WFI ();
00655   }
00656   else
00657   {
00658     /* Request Wait For Event */
00659     __WFE ();
00660   }
00661
00662   /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
00663   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00664 }
00665
00666 /**
00667   * @brief  Enter STANDBY mode.
00668   * @note   For single core devices, this API will enter the system in STANDBY
00669   *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
00670   *         regiter is cleared.
00671   *         For dual core devices, this API will enter the domain (containing
00672   *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
00673   *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
00674   *         is cleared, all the system will enter in STANDBY mode.
00675   * @note   The system enters Standby mode only when all domains are in DSTANDBY.
00676   * @note   When the System exit STANDBY mode by issuing an interrupt or a
00677   *         wakeup event, the HSI RC oscillator is selected as system clock.
00678   * @retval None.
00679   */
00680 void HAL_PWR_EnterSTANDBYMode (void)
00681 {
00682   /* Configure the PWR mode for the different Domains */
00683 #if defined (DUAL_CORE)
00684   /* Check CPU ID */
00685   if (HAL_GetCurrentCPUID () == CM7_CPUID)
00686   {
00687     /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
00688     SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
00689     SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
00690   }
00691   else
00692   {
00693     /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
00694     SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
00695     SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
00696   }
00697 #else /* Single core devices */
00698   /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
00699   SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
00700
00701 #if defined (PWR_CPUCR_PDDS_D2)
00702   /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
00703   SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00704 #endif /* PWR_CPUCR_PDDS_D2 */
00705 #endif /* defined (DUAL_CORE) */
00706
00707   /* Set SLEEPDEEP bit of Cortex System Control Register */
00708   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00709
00710   /* Ensure that all instructions are done before entering STOP mode */
00711   __DSB ();
00712   __ISB ();
00713
00714   /* This option is used to ensure that store operations are completed */
00715 #if defined (__CC_ARM)
00716   __force_stores();
00717 #endif /* defined (__CC_ARM) */
00718
00719   /* Request Wait For Interrupt */
00720   __WFI ();
00721 }
00722
00723 /**
00724   * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
00725   *         Thread mode.
00726   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
00727   *         processor re-enters SLEEP mode when an interruption handling is over.
00728   *         Setting this bit is useful when the processor is expected to run
00729   *         only on interruptions handling.
00730   * @retval None.
00731   */
00732 void HAL_PWR_EnableSleepOnExit (void)
00733 {
00734   /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
00735   SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
00736 }
00737
00738 /**
00739   * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
00740   *         Thread mode.
00741   * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
00742   *         processor re-enters SLEEP mode when an interruption handling is over.
00743   * @retval None
00744   */
00745 void HAL_PWR_DisableSleepOnExit (void)
00746 {
00747   /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
00748   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
00749 }
00750
00751 /**
00752   * @brief  Enable CORTEX SEVONPEND feature.
00753   * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
00754   *         pending event / interrupt even if it's disabled or has insufficient
00755   *         priority to cause exception entry wakes up the Cortex-Mx.
00756   * @retval None.
00757   */
00758 void HAL_PWR_EnableSEVOnPend (void)
00759 {
00760   /* Set SEVONPEND bit of Cortex-Mx System Control Register */
00761   SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
00762 }
00763
00764 /**
00765   * @brief  Disable CORTEX SEVONPEND feature.
00766   * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
00767   *         enabled pending causes exception entry wakes up the Cortex-Mx.
00768   * @retval None.
00769   */
00770 void HAL_PWR_DisableSEVOnPend (void)
00771 {
00772   /* Clear SEVONPEND bit of Cortex System Control Register */
00773   CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
00774 }
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
00780   *  @brief   Interrupt Handling functions
00781   *
00782 @verbatim
00783  ===============================================================================
00784                     ##### Interrupt Handling Functions #####
00785  ===============================================================================
00786     [..]
00787     This section provides functions allowing to handle the PVD pending
00788     interrupts.
00789
00790 @endverbatim
00791   * @{
00792   */
00793
00794 /**
00795   * @brief  This function handles the PWR PVD interrupt request.
00796   * @note   This API should be called under the PVD_AVD_IRQHandler().
00797   * @retval None.
00798   */
00799 void HAL_PWR_PVD_IRQHandler (void)
00800 {
00801 #if defined (DUAL_CORE)
00802   /* Check Cortex-Mx ID */
00803   if (HAL_GetCurrentCPUID () == CM7_CPUID)
00804   {
00805     /* Check PWR EXTI D1 flag */
00806     if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
00807     {
00808       /* Clear PWR EXTI D1 pending bit */
00809       __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
00810
00811       /* PWR PVD interrupt user callback */
00812       HAL_PWR_PVDCallback ();
00813     }
00814   }
00815   else
00816   {
00817     /* Check PWR EXTI D2 flag */
00818     if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
00819     {
00820       /* Clear PWR EXTI D2 pending bit */
00821       __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
00822
00823       /* PWR PVD interrupt user callback */
00824       HAL_PWR_PVDCallback ();
00825     }
00826   }
00827 #else /* Single core devices */
00828   /* PVD EXTI line interrupt detected */
00829   if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
00830   {
00831     /* Clear PWR EXTI pending bit */
00832     __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
00833
00834     /* PWR PVD interrupt user callback */
00835     HAL_PWR_PVDCallback ();
00836   }
00837 #endif /* defined (DUAL_CORE) */
00838 }
00839
00840 /**
00841   * @brief  PWR PVD interrupt callback.
00842   * @retval None.
00843   */
00844 __weak void HAL_PWR_PVDCallback (void)
00845 {
00846   /* NOTE : This function should not be modified, when the callback is needed,
00847             the HAL_PWR_PVDCallback can be implemented in the user file
00848   */
00849 }
00850
00851 /**
00852   * @}
00853   */
00854
00855 /**
00856   * @}
00857   */
00858
00859 #endif /* HAL_PWR_MODULE_ENABLED */
00860 /**
00861   * @}
00862   */
00863
00864 /**
00865   * @}
00866   */
00867
00868 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr.h Source File

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stm32h7xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_PWR_H
00022 #define STM32H7xx_HAL_PWR_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif /* __cplusplus */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup PWR
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup PWR_Exported_Types PWR Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  PWR PVD configuration structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
00051                                     parameter can be a value of @ref
00052                                     PWR_PVD_detection_level.
00053                      */
00054
00055   uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
00056                                 event. This parameter can be a value of @ref
00057                                 PWR_PVD_Mode.
00058                      */
00059 }PWR_PVDTypeDef;
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
00071   * @{
00072   */
00073 #define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
00074                                                level 0 selection : 1V95       */
00075 #define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
00076                                                level 1 selection : 2V1        */
00077 #define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
00078                                                level 2 selection : 2V25       */
00079 #define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
00080                                                level 3 selection : 2V4        */
00081 #define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
00082                                                level 4 selection : 2V55       */
00083 #define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
00084                                                level 5 selection : 2V7        */
00085 #define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
00086                                                level 6 selection : 2V85       */
00087 #define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
00088                                                (Compare internally to VREF)   */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup PWR_PVD_Mode PWR PVD Mode
00094   * @{
00095   */
00096 #define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
00097 #define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
00098 #define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
00099 #define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
00100 #define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
00101 #define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
00102 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
00108   * @{
00109   */
00110 #define PWR_MAINREGULATOR_ON      (0U)
00111 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00117   * @{
00118   */
00119 #define PWR_SLEEPENTRY_WFI  (0x01U)
00120 #define PWR_SLEEPENTRY_WFE  (0x02U)
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00126   * @{
00127   */
00128 #define PWR_STOPENTRY_WFI  (0x01U)
00129 #define PWR_STOPENTRY_WFE  (0x02U)
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
00135   * @{
00136   */
00137 #if defined(PWR_SRDCR_VOS)
00138 #define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
00139 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
00140 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
00141 #define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
00142 #else
00143 #define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
00144 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
00145 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
00146 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
00147 #endif /* PWR_SRDCR_VOS */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup PWR_Flag PWR Flag
00153   * @{
00154   */
00155 /* PWR CPU flag */
00156 #define PWR_FLAG_STOP       (0x01U)
00157 #if defined (PWR_CPUCR_SBF_D2)
00158 #define PWR_FLAG_SB_D1      (0x02U)
00159 #define PWR_FLAG_SB_D2      (0x03U)
00160 #endif /* defined (PWR_CPUCR_SBF_D2) */
00161 #define PWR_FLAG_SB         (0x04U)
00162 #if defined (DUAL_CORE)
00163 #define PWR_FLAG_CPU_HOLD   (0x05U)
00164 #define PWR_FLAG_CPU2_HOLD  (0x06U)
00165 #define PWR_FLAG2_STOP      (0x07U)
00166 #define PWR_FLAG2_SB_D1     (0x08U)
00167 #define PWR_FLAG2_SB_D2     (0x09U)
00168 #define PWR_FLAG2_SB        (0x0AU)
00169 #endif /* defined (DUAL_CORE) */
00170 #define PWR_FLAG_PVDO       (0x0BU)
00171 #define PWR_FLAG_AVDO       (0x0CU)
00172 #define PWR_FLAG_ACTVOSRDY  (0x0DU)
00173 #define PWR_FLAG_ACTVOS     (0x0EU)
00174 #define PWR_FLAG_BRR        (0x0FU)
00175 #define PWR_FLAG_VOSRDY     (0x10U)
00176 #if defined (SMPS)
00177 #define PWR_FLAG_SMPSEXTRDY (0x11U)
00178 #else
00179 #define PWR_FLAG_SCUEN      (0x11U)
00180 #endif /* defined (SMPS) */
00181 #if defined (PWR_CSR1_MMCVDO)
00182 #define PWR_FLAG_MMCVDO     (0x12U)
00183 #endif /* defined (PWR_CSR1_MMCVDO) */
00184 #define PWR_FLAG_USB33RDY   (0x13U)
00185 #define PWR_FLAG_TEMPH      (0x14U)
00186 #define PWR_FLAG_TEMPL      (0x15U)
00187 #define PWR_FLAG_VBATH      (0x16U)
00188 #define PWR_FLAG_VBATL      (0x17U)
00189
00190 /* PWR Wake up flag */
00191 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
00192 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
00193 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
00194 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
00195 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
00196 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
00202   * @{
00203   */
00204 #define  PWR_EWUP_MASK  (0x0FFF3F3FU)
00205 /**
00206   * @}
00207   */
00208
00209 /**
00210   * @}
00211   */
00212 /* Exported macro ------------------------------------------------------------*/
00213 /** @defgroup PWR_Exported_Macro PWR Exported Macro
00214   * @{
00215   */
00216
00217 /** @brief  Configure the main internal regulator output voltage.
00218   * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
00219   *                         trade-off between performance and power consumption
00220   *                         when the device does not operate at the maximum
00221   *                         frequency (refer to the datasheet for more details).
00222   *          This parameter can be one of the following values:
00223   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
00224   *                                                Scale 0 mode.
00225   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
00226   *                                                Scale 1 mode.
00227   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
00228   *                                                Scale 2 mode.
00229   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
00230   *                                                Scale 3 mode.
00231   * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
00232   *         configuring Voltage Scale 0 is only possible when Vcore is supplied
00233   *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
00234   *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
00235   *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
00236   *         Transition to Voltage Scale 0 is only possible when the system is
00237   *         already in Voltage Scale 1.
00238   *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
00239   *         then once in Voltage Scale 1 it is possible to switch to another
00240   *         voltage scale.
00241   *         After each regulator voltage setting, wait on VOSRDY flag to be set
00242   *         using macro __HAL_PWR_GET_FLAG().
00243   *         To enter low power mode , and if current regulator voltage is
00244   *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
00245   *         low power mode.
00246   * @retval None.
00247   */
00248 #if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
00249 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
00250 do {                                                                           \
00251       __IO uint32_t tmpreg = 0x00;                                             \
00252       MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
00253       /* Delay after setting the voltage scaling */                            \
00254       tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
00255       UNUSED(tmpreg);                                                          \
00256 } while(0)
00257 #else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
00258 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
00259 do {                                                                           \
00260       __IO uint32_t tmpreg = 0x00;                                             \
00261       /* Check the voltage scaling to be configured */                         \
00262       if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
00263       {                                                                        \
00264         /* Configure the Voltage Scaling 1 */                                  \
00265         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
00266         /* Delay after setting the voltage scaling */                          \
00267         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
00268         /* Enable the PWR overdrive */                                         \
00269         SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
00270         /* Delay after setting the syscfg boost setting */                     \
00271         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
00272       }                                                                        \
00273       else                                                                     \
00274       {                                                                        \
00275         /* Disable the PWR overdrive */                                        \
00276         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
00277         /* Delay after setting the syscfg boost setting */                     \
00278         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
00279         /* Configure the Voltage Scaling x */                                  \
00280         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
00281         /* Delay after setting the voltage scaling */                          \
00282         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
00283       }                                                                        \
00284       UNUSED(tmpreg);                                                          \
00285 } while(0)
00286 #endif /* PWR_SRDCR_VOS */
00287
00288 /** @brief  Check PWR flags are set or not.
00289   * @param  __FLAG__ : Specifies the flag to check.
00290   *           This parameter can be one of the following values:
00291   *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
00292   *                                 is enabled by the HAL_PWR_EnablePVD()
00293   *                                 function.
00294   *                                 The PVD is stopped by STANDBY mode. For this
00295   *                                 reason, this bit is equal to 0 after STANDBY
00296   *                                 or reset until the PVDE bit is set.
00297   *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
00298   *                                 is enabled by the HAL_PWREx_EnableAVD()
00299   *                                 function. The AVD is stopped by STANDBY mode.
00300   *                                 For this reason, this bit is equal to 0
00301   *                                 after STANDBY or reset until the AVDE bit
00302   *                                 is set.
00303   *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
00304   *                                      voltage scaling output selection is
00305   *                                      ready.
00306   *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
00307   *                                reset when the device wakes up from STANDBY
00308   *                                mode or by a system reset or power-on reset.
00309   *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
00310   *                                   voltage scaling output selection is ready.
00311   *                                mode or by a system reset or power-on reset.
00312   *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
00313   *                                     from regulator is ready.
00314   *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
00315   *                                  equal or above high threshold level.
00316   *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
00317   *                                  equal or below low threshold level.
00318   *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
00319   *                                  or above high threshold level.
00320   *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
00321   *                                  or below low threshold level.
00322   *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
00323   *                                 in STOP mode.
00324   *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
00325   *                               STANDBY mode.
00326   *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
00327   *                                  entered in STANDBY mode.
00328   *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
00329   *                                  entered in STANDBY mode.
00330   *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
00331   *                                 in STOP mode.
00332   *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
00333   *                                in STANDBY mode.
00334   *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
00335   *                                   entered in STANDBY mode.
00336   *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
00337   *                                   entered in STANDBY mode.
00338   *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
00339   *                                     up with hold.
00340   *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
00341   *                                      up with hold.
00342   *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
00343   *                                       External supply is sready.
00344   *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
00345   *                                  configuration update is enabled.
00346   *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
00347   *                                   above or equal to 1.2 V.
00348   * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
00349   *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
00350   *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
00351   *         are used for all H7 family lines.
00352   *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
00353   *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
00354   *         dual core lines.
00355   *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
00356   *         family except STM32H7Axxx and STM32H7Bxxx lines.
00357   *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
00358   *         STM32H7Bxxx lines.
00359   *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
00360   *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
00361   *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
00362   *         STM32H7BxxQ lines.
00363   * @retval The (__FLAG__) state (TRUE or FALSE).
00364   */
00365 #if defined (DUAL_CORE) /* Dual core lines */
00366 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
00367 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
00368  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
00369  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
00370  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
00371  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
00372  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
00373  ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
00374  ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
00375  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
00376  ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
00377  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
00378  ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
00379  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
00380  ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
00381  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
00382  ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
00383  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
00384  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
00385  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
00386  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
00387  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
00388 #else /* Single core lines */
00389 #if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
00390 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
00391 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
00392  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
00393  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
00394  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
00395  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
00396  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
00397  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
00398  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
00399  ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
00400  ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
00401  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
00402  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
00403  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
00404  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
00405  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
00406 #else /* STM32H7Axxx and STM32H7Bxxx lines */
00407 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
00408 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
00409 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
00410  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
00411  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
00412  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
00413  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
00414  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
00415  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
00416  ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
00417  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
00418  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
00419  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
00420  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
00421  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
00422  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
00423 #else /* STM32H7Axx and STM32H7Bxx LDO lines */
00424 #define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
00425 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
00426  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
00427  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
00428  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
00429  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
00430  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
00431  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
00432  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
00433  ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
00434  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
00435  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
00436  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
00437  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
00438  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
00439 #endif /* SMPS */
00440 #endif /* PWR_CPUCR_SBF_D2 */
00441 #endif /* DUAL_CORE */
00442
00443 /** @brief  Check PWR wake up flags are set or not.
00444   * @param  __FLAG__: specifies the wake up flag to check.
00445   *           This parameter can be one of the following values:
00446   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
00447   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
00448   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
00449   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
00450   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
00451   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
00452   * @retval The (__FLAG__) state (TRUE or FALSE).
00453   */
00454 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
00455
00456 #if defined (DUAL_CORE)
00457 /** @brief  Clear CPU PWR flags.
00458   * @param  __FLAG__ : Specifies the flag to clear.
00459   * @note   This parameter is not used for the STM32H7 family and is kept as
00460   *         parameter just to maintain compatibility with other families.
00461   * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
00462   *           This parameter can be one of the following values :
00463   *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
00464   *                                 CPU flags.
00465   * @retval None.
00466   */
00467 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
00468 do {                                        \
00469      SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
00470      SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
00471 } while(0)
00472 #else
00473 /** @brief  Clear CPU PWR flags.
00474   * @param  __FLAG__ : Specifies the flag to clear.
00475   * @note   This parameter is not used for the STM32H7 family and is kept as
00476   *         parameter just to maintain compatibility with other families.
00477   * @note   This macro clear all CPU flags.
00478   *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
00479   *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
00480   * @retval None.
00481   */
00482 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
00483 #endif /* defined (DUAL_CORE) */
00484
00485 /** @brief  Clear PWR wake up flags.
00486   * @param  __FLAG__ : Specifies the wake up flag to be cleared.
00487   *           This parameter can be one of the following values :
00488   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
00489   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
00490   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
00491   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
00492   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
00493   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
00494   * @retval None.
00495   */
00496 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
00497
00498 /**
00499   * @brief Enable the PVD EXTI Line 16.
00500   * @retval None.
00501   */
00502 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00503
00504 #if defined (DUAL_CORE)
00505 /**
00506   * @brief Enable the PVD EXTI D2 Line 16.
00507   * @retval None.
00508   */
00509 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
00510 #endif /* defined (DUAL_CORE) */
00511
00512 /**
00513   * @brief Disable the PVD EXTI Line 16.
00514   * @retval None.
00515   */
00516 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00517
00518 #if defined (DUAL_CORE)
00519 /**
00520   * @brief Disable the PVD EXTI D2 Line 16.
00521   * @retval None.
00522   */
00523 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
00524 #endif /* defined (DUAL_CORE) */
00525
00526 /**
00527   * @brief   Enable event on PVD EXTI Line 16.
00528   * @retval None.
00529   */
00530 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
00531
00532 #if defined (DUAL_CORE)
00533 /**
00534   * @brief Enable event on PVD EXTI D2 Line.
00535   * @retval None.
00536   */
00537 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
00538 #endif /* defined (DUAL_CORE) */
00539
00540 /**
00541   * @brief   Disable event on PVD EXTI Line 16.
00542   * @retval None.
00543   */
00544 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
00545
00546 #if defined (DUAL_CORE)
00547 /**
00548   * @brief Disable event on PVD EXTI D2 Line.
00549   * @retval None.
00550   */
00551 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
00552 #endif /* defined (DUAL_CORE) */
00553
00554 /**
00555   * @brief Enable the PVD Rising Interrupt Trigger.
00556   * @retval None.
00557   */
00558 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00559
00560 /**
00561   * @brief Disable the PVD Rising Interrupt Trigger.
00562   * @retval None.
00563   */
00564 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00565
00566 /**
00567   * @brief Enable the PVD Falling Interrupt Trigger.
00568   * @retval None.
00569   */
00570 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00571
00572 /**
00573   * @brief Disable the PVD Falling Interrupt Trigger.
00574   * @retval None.
00575   */
00576 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00577
00578 /**
00579   * @brief Enable the PVD Rising & Falling Interrupt Trigger.
00580   * @retval None.
00581   */
00582 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
00583 do {                                                    \
00584       __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
00585       __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
00586 } while(0);
00587
00588 /**
00589   * @brief Disable the PVD Rising & Falling Interrupt Trigger.
00590   * @retval None.
00591   */
00592 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
00593 do {                                                     \
00594       __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
00595       __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
00596 } while(0);
00597
00598 /**
00599   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
00600   * @retval EXTI PVD Line Status.
00601   */
00602 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
00603
00604 #if defined (DUAL_CORE)
00605 /**
00606   * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
00607   * @retval EXTI D2 PVD Line Status.
00608   */
00609 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
00610 #endif /* defined (DUAL_CORE) */
00611
00612 /**
00613   * @brief Clear the PVD EXTI flag.
00614   * @retval None.
00615   */
00616 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
00617
00618 #if defined (DUAL_CORE)
00619 /**
00620   * @brief Clear the PVD EXTI D2 flag.
00621   * @retval None.
00622   */
00623 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
00624 #endif /* defined (DUAL_CORE) */
00625
00626 /**
00627   * @brief  Generates a Software interrupt on PVD EXTI line.
00628   * @retval None.
00629   */
00630 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
00631 /**
00632   * @}
00633   */
00634
00635 /* Include PWR HAL Extension module */
00636 #include "stm32h7xx_hal_pwr_ex.h"
00637
00638 /* Exported functions --------------------------------------------------------*/
00639 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00640   * @{
00641   */
00642
00643 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
00644   * @{
00645   */
00646 /* Initialization and de-initialization functions *****************************/
00647 void HAL_PWR_DeInit(void);
00648 void HAL_PWR_EnableBkUpAccess(void);
00649 void HAL_PWR_DisableBkUpAccess(void);
00650 /**
00651   * @}
00652   */
00653
00654 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00655   * @{
00656   */
00657 /* Peripheral Control functions  **********************************************/
00658 /* PVD configuration */
00659 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00660 void HAL_PWR_EnablePVD(void);
00661 void HAL_PWR_DisablePVD(void);
00662
00663 /* WakeUp pins configuration */
00664 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00665 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00666
00667 /* Low Power modes entry */
00668 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00669 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00670 void HAL_PWR_EnterSTANDBYMode(void);
00671
00672 /* Power PVD IRQ Handler */
00673 void HAL_PWR_PVD_IRQHandler(void);
00674 void HAL_PWR_PVDCallback(void);
00675
00676 /* Cortex System Control functions  *******************************************/
00677 void HAL_PWR_EnableSleepOnExit(void);
00678 void HAL_PWR_DisableSleepOnExit(void);
00679 void HAL_PWR_EnableSEVOnPend(void);
00680 void HAL_PWR_DisableSEVOnPend(void);
00681 /**
00682   * @}
00683   */
00684
00685 /**
00686   * @}
00687   */
00688
00689 /* Private types -------------------------------------------------------------*/
00690 /* Private variables ---------------------------------------------------------*/
00691 /* Private constants ---------------------------------------------------------*/
00692 /** @defgroup PWR_Private_Constants PWR Private Constants
00693   * @{
00694   */
00695
00696 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
00697   * @{
00698   */
00699 #define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
00700                                                Connected to the PVD EXTI Line */
00701 /**
00702   * @}
00703   */
00704
00705 /**
00706   * @}
00707   */
00708 /* Private macros ------------------------------------------------------------*/
00709 /** @defgroup PWR_Private_Macros PWR Private Macros
00710   * @{
00711   */
00712
00713 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
00714   * @{
00715   */
00716 /* Check PVD level parameter */
00717 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
00718                                  ((LEVEL) == PWR_PVDLEVEL_1) ||\
00719                                  ((LEVEL) == PWR_PVDLEVEL_2) ||\
00720                                  ((LEVEL) == PWR_PVDLEVEL_3) ||\
00721                                  ((LEVEL) == PWR_PVDLEVEL_4) ||\
00722                                  ((LEVEL) == PWR_PVDLEVEL_5) ||\
00723                                  ((LEVEL) == PWR_PVDLEVEL_6) ||\
00724                                  ((LEVEL) == PWR_PVDLEVEL_7))
00725
00726 /* Check PVD mode parameter */
00727 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
00728                                ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
00729                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
00730                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
00731                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
00732                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
00733                                ((MODE) == PWR_PVD_MODE_NORMAL))
00734
00735 /* Check low power regulator parameter */
00736 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
00737                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00738
00739 /* Check low power mode entry parameter */
00740 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
00741                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
00742
00743 /* Check low power mode entry parameter */
00744 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
00745                                   ((ENTRY) == PWR_STOPENTRY_WFE))
00746
00747 /* Check voltage scale level parameter */
00748 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
00749                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00750                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
00751                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
00752 /**
00753   * @}
00754   */
00755
00756 /**
00757   * @}
00758   */
00759
00760 /**
00761   * @}
00762   */
00763
00764 /**
00765   * @}
00766   */
00767
00768 #ifdef __cplusplus
00769 }
00770 #endif /* __cplusplus */
00771
00772 #endif /* STM32H7xx_HAL_PWR_H */
00773
00774 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr_ex.c Source File

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stm32h7xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of PWR extension peripheral:
00008   *           + Peripheral Extended features functions
00009   @verbatim
00010   ==============================================================================
00011                         ##### How to use this driver #####
00012   ==============================================================================
00013   [..]
00014    (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
00015        with the following different setups according to hardware (support SMPS):
00016        (+) PWR_DIRECT_SMPS_SUPPLY
00017        (+) PWR_SMPS_1V8_SUPPLIES_LDO
00018        (+) PWR_SMPS_2V5_SUPPLIES_LDO
00019        (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
00020        (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
00021        (+) PWR_SMPS_1V8_SUPPLIES_EXT
00022        (+) PWR_SMPS_2V5_SUPPLIES_EXT
00023        (+) PWR_LDO_SUPPLY
00024        (+) PWR_EXTERNAL_SOURCE_SUPPLY
00025
00026    (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
00027
00028    (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
00029        internal regulator output voltage. The voltage scaling could be one of
00030        the following scales :
00031        (+) PWR_REGULATOR_VOLTAGE_SCALE0
00032        (+) PWR_REGULATOR_VOLTAGE_SCALE1
00033        (+) PWR_REGULATOR_VOLTAGE_SCALE2
00034        (+) PWR_REGULATOR_VOLTAGE_SCALE3
00035
00036    (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
00037        voltage applied to the main regulator.
00038
00039    (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
00040        main internal regulator output voltage in STOP mode. The voltage scaling
00041        in STOP mode could be one of the following scales :
00042        (+) PWR_REGULATOR_SVOS_SCALE3
00043        (+) PWR_REGULATOR_SVOS_SCALE4
00044        (+) PWR_REGULATOR_SVOS_SCALE5
00045
00046    (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
00047        output voltage applied to the main regulator in STOP mode.
00048
00049    (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
00050        with core domain in D2STOP mode. This API is used only for STM32H7Axxx
00051        and STM32H7Bxxx devices.
00052        Please ensure to clear all CPU pending events by calling
00053        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
00054        in DEEP-SLEEP mode with __WFE() entry.
00055
00056    (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
00057        DSTOP mode. Call this API with all available power domains to enter the
00058        system in STOP mode.
00059        Please ensure to clear all CPU pending events by calling
00060        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
00061        in DEEP-SLEEP mode with __WFE() entry.
00062
00063    (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
00064        Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
00065
00066    (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
00067        in DSTANDBY mode. Call this API with all available power domains to enter
00068        the system in STANDBY mode.
00069
00070    (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
00071        (RUN/STOP) when the system enter to low power mode.
00072
00073    (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
00074        selected power domain. This API is used only for dual core devices.
00075
00076    (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
00077        and release the selected CPU and and their domain peripherals when
00078        exiting STOP mode. These APIs are used only for dual core devices.
00079
00080    (#) Call HAL_PWREx_EnableFlashPowerDown() and
00081        HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
00082        Flash Power Down in STOP mode.
00083
00084    (#) Call HAL_PWREx_EnableMemoryShutOff() and
00085        HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
00086        memory block shut-off in DStop or DStop2. These APIs are used only for
00087        STM32H7Axxx and STM32H7Bxxx lines.
00088
00089    (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
00090        functions to enable and disable the Wake-up pin functionality for
00091        the selected pin.
00092
00093    (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
00094        functions to manage wake-up flag for the selected pin.
00095
00096    (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
00097        pins interrupts.
00098
00099    (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
00100        to enable and disable the backup domain regulator.
00101
00102    (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
00103        HAL_PWREx_EnableUSBVoltageDetector() and
00104        HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
00105        regulation functionnalities.
00106
00107    (#) Call HAL_PWREx_EnableBatteryCharging() and
00108        HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
00109        battery charging feature with the selected resistor.
00110
00111    (#) Call HAL_PWREx_EnableAnalogBooster() and
00112        HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
00113        AVD boost feature when the VDD supply voltage is below 2V7.
00114
00115    (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
00116        functions to enable and disable the VBAT and Temperature monitoring.
00117        When VBAT and Temperature monitoring feature is enables, use
00118        HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
00119        respectively the Temperature level and VBAT level.
00120
00121    (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
00122        function to get VDDMMC voltage level. This API is used only for
00123        STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
00124
00125    (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
00126        (event mode and voltage threshold) in order to set up the Analog Voltage
00127        Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
00128        functions to start and stop the AVD detection.
00129        (+) AVD level could be one of the following values :
00130              (++) 1V7
00131              (++) 2V1
00132              (++) 2V5
00133              (++) 2V8
00134
00135    (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
00136        AVD interrupt request.
00137
00138   @endverbatim
00139   ******************************************************************************
00140   * @attention
00141   *
00142   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00143   * All rights reserved.</center></h2>
00144   *
00145   * This software component is licensed by ST under BSD 3-Clause license,
00146   * the "License"; You may not use this file except in compliance with the
00147   * License. You may obtain a copy of the License at:
00148   *                        opensource.org/licenses/BSD-3-Clause
00149   *
00150   ******************************************************************************
00151   */
00152
00153 /* Includes ------------------------------------------------------------------*/
00154 #include "stm32h7xx_hal.h"
00155
00156 /** @addtogroup STM32H7xx_HAL_Driver
00157   * @{
00158   */
00159
00160 /** @defgroup PWREx PWREx
00161   * @brief PWR Extended HAL module driver
00162   * @{
00163   */
00164
00165 #ifdef HAL_PWR_MODULE_ENABLED
00166
00167 /* Private typedef -----------------------------------------------------------*/
00168 /* Private define ------------------------------------------------------------*/
00169
00170 /** @addtogroup PWREx_Private_Constants
00171   * @{
00172   */
00173
00174 /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
00175   * @{
00176   */
00177 #define AVD_MODE_IT              (0x00010000U)
00178 #define AVD_MODE_EVT             (0x00020000U)
00179 #define AVD_RISING_EDGE          (0x00000001U)
00180 #define AVD_FALLING_EDGE         (0x00000002U)
00181 #define AVD_RISING_FALLING_EDGE  (0x00000003U)
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
00187   * @{
00188   */
00189 #define PWR_FLAG_SETTING_DELAY   (1000U)
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
00195   * @{
00196   */
00197 /* Wake-Up Pins EXTI register mask */
00198 #define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
00199                                     EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
00200                                     EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
00201
00202 /* Wake-Up Pins PWR Pin Pull shift offsets */
00203 #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
00204 /**
00205   * @}
00206   */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /* Private macro -------------------------------------------------------------*/
00213 /* Private variables ---------------------------------------------------------*/
00214 /* Private function prototypes -----------------------------------------------*/
00215 /* Private functions ---------------------------------------------------------*/
00216 /* Exported types ------------------------------------------------------------*/
00217 /* Exported functions --------------------------------------------------------*/
00218
00219 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
00220   * @{
00221   */
00222
00223 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
00224   * @brief    Power supply control functions
00225   *
00226 @verbatim
00227  ===============================================================================
00228                   ##### Power supply control functions #####
00229  ===============================================================================
00230     [..]
00231    (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
00232        above the POR threshold level, the voltage regulator is enabled in the
00233        default supply configuration:
00234       (+) The Voltage converter output level is set at 1V0 in accordance with
00235           the VOS3 level configured in PWR (D3/SRD) domain control register
00236           (PWR_D3CR/PWR_SRDCR).
00237       (+) The system is kept in reset mode as long as VCORE is not ok.
00238       (+) Once VCORE is ok, the system is taken out of reset and the HSI
00239           oscillator is enabled.
00240       (+) Once the oscillator is stable, the system is initialized: Flash memory
00241           and option bytes are loaded and the CPU starts in Run* mode.
00242       (+) The software shall then initialize the system including supply
00243           configuration programming using the HAL_PWREx_ConfigSupply().
00244       (+) Once the supply configuration has been configured, the
00245           HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
00246           control status register 1 (PWR_CSR1) to guarantee a valid voltage
00247           levels:
00248        (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
00249             system is in limited Run* mode, write accesses to the RAMs are not
00250             permitted and VOS shall not be changed.
00251        (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
00252             is in normal Run mode, write accesses to RAMs are allowed and VOS
00253             can be changed.
00254
00255 @endverbatim
00256   * @{
00257   */
00258
00259 /**
00260   * @brief Configure the system Power Supply.
00261   * @param  SupplySource : Specifies the Power Supply source to set after a
00262   *                        system startup.
00263   *         This parameter can be one of the following values :
00264   *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
00265   *                                          Domains. The LDO is Bypassed.
00266   *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
00267   *                                             the LDO. The Vcore Power Domains
00268   *                                             are supplied from the LDO.
00269   *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
00270   *                                             the LDO. The Vcore Power Domains
00271   *                                             are supplied from the LDO.
00272   *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
00273   *                                                     supplies external
00274   *                                                     circuits and the LDO.
00275   *                                                     The Vcore Power Domains
00276   *                                                     are supplied from the
00277   *                                                     LDO.
00278   *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
00279   *                                                     supplies external
00280   *                                                     circuits and the LDO.
00281   *                                                     The Vcore Power Domains
00282   *                                                     are supplied from the
00283   *                                                     LDO.
00284   *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
00285   *                                             external circuits. The LDO is
00286   *                                             Bypassed. The Vcore Power
00287   *                                             Domains are supplied from
00288   *                                             external source.
00289   *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
00290   *                                             external circuits. The LDO is
00291   *                                             Bypassed. The Vcore Power
00292   *                                             Domains are supplied from
00293   *                                             external source.
00294   *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
00295   *                                  Domains. The SMPS regulator is Bypassed.
00296   *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
00297   *                                              Bypassed. The Vcore Power
00298   *                                              Domains are supplied from
00299   *                                              external source.
00300   * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
00301   *         H7 lines.
00302   *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
00303   *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
00304   *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
00305   *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
00306   *         regulator.
00307   * @retval HAL status.
00308   */
00309 HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
00310 {
00311   uint32_t tickstart;
00312
00313   /* Check the parameters */
00314   assert_param (IS_PWR_SUPPLY (SupplySource));
00315
00316   /* Check if supply source was configured */
00317 #if defined (PWR_FLAG_SCUEN)
00318   if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
00319 #else
00320   if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
00321 #endif /* defined (PWR_FLAG_SCUEN) */
00322   {
00323     /* Check supply configuration */
00324     if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
00325     {
00326       /* Supply configuration update locked, can't apply a new supply config */
00327       return HAL_ERROR;
00328     }
00329     else
00330     {
00331       /* Supply configuration update locked, but new supply configuration
00332          matches with old supply configuration : nothing to do
00333       */
00334       return HAL_OK;
00335     }
00336   }
00337
00338   /* Set the power supply configuration */
00339   MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
00340
00341   /* Get tick */
00342   tickstart = HAL_GetTick ();
00343
00344   /* Wait till voltage level flag is set */
00345   while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
00346   {
00347     if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
00348     {
00349       return HAL_ERROR;
00350     }
00351   }
00352
00353 #if defined (SMPS)
00354   /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
00355   if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
00356       (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
00357       (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
00358       (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
00359   {
00360     /* Get the current tick number */
00361     tickstart = HAL_GetTick ();
00362
00363     /* Wait till SMPS external supply ready flag is set */
00364     while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
00365     {
00366       if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
00367       {
00368         return HAL_ERROR;
00369       }
00370     }
00371   }
00372 #endif /* defined (SMPS) */
00373
00374   return HAL_OK;
00375 }
00376
00377 /**
00378   * @brief Get the power supply configuration.
00379   * @retval The supply configuration.
00380   */
00381 uint32_t HAL_PWREx_GetSupplyConfig (void)
00382 {
00383   return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
00384 }
00385
00386 /**
00387   * @brief Configure the main internal regulator output voltage.
00388   * @note   For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
00389   *         configuring Voltage Scale 0 is only possible when Vcore is supplied
00390   *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
00391   *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
00392   *         Scale 0.
00393   * @param  VoltageScaling : Specifies the regulator output voltage to achieve
00394   *                          a tradeoff between performance and power
00395   *                          consumption.
00396   *          This parameter can be one of the following values :
00397   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
00398   *                                                Scale 0 mode.
00399   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
00400   *                                                range 1 mode.
00401   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
00402   *                                                range 2 mode.
00403   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
00404   *                                                range 3 mode.
00405   * @retval HAL Status
00406   */
00407 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
00408 {
00409   uint32_t tickstart;
00410
00411   /* Check the parameters */
00412   assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
00413
00414   /* Get the voltage scaling  */
00415   if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
00416   {
00417     /* Old and new voltage scaling configuration match : nothing to do */
00418     return HAL_OK;
00419   }
00420
00421 #if defined (PWR_SRDCR_VOS)
00422   /* Set the voltage range */
00423   MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
00424 #else
00425   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
00426   {
00427     if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
00428     {
00429       /* Set the voltage range */
00430       MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
00431
00432       /* Get tick */
00433       tickstart = HAL_GetTick ();
00434
00435       /* Wait till voltage level flag is set */
00436       while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
00437       {
00438         if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
00439         {
00440           return HAL_ERROR;
00441         }
00442       }
00443
00444       /* Enable the PWR overdrive */
00445       SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
00446     }
00447     else
00448     {
00449       /* The voltage scale 0 is only possible when LDO regulator is enabled */
00450       return HAL_ERROR;
00451     }
00452   }
00453   else
00454   {
00455     if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
00456     {
00457       if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
00458       {
00459         /* Disable the PWR overdrive */
00460         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
00461
00462         /* Get tick */
00463         tickstart = HAL_GetTick ();
00464
00465         /* Wait till voltage level flag is set */
00466         while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
00467         {
00468           if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
00469           {
00470             return HAL_ERROR;
00471           }
00472         }
00473       }
00474     }
00475
00476     /* Set the voltage range */
00477     MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
00478   }
00479 #endif /* defined (PWR_SRDCR_VOS) */
00480
00481   /* Get tick */
00482   tickstart = HAL_GetTick ();
00483
00484   /* Wait till voltage level flag is set */
00485   while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
00486   {
00487     if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
00488     {
00489       return HAL_ERROR;
00490     }
00491   }
00492
00493   return HAL_OK;
00494 }
00495
00496 /**
00497   * @brief Get the main internal regulator output voltage. Reflecting the last
00498   *        VOS value applied to the PMU.
00499   * @retval The current applied VOS selection.
00500   */
00501 uint32_t HAL_PWREx_GetVoltageRange (void)
00502 {
00503   /* Get the active voltage scaling */
00504   return (PWR->CSR1 & PWR_CSR1_ACTVOS);
00505 }
00506
00507 /**
00508   * @brief Configure the main internal regulator output voltage in STOP mode.
00509   * @param  VoltageScaling : Specifies the regulator output voltage when the
00510   *         system enters Stop mode to achieve a tradeoff between performance
00511   *         and power consumption.
00512   *          This parameter can be one of the following values:
00513   *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
00514   *                                             3 mode.
00515   *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
00516   *                                             4 mode.
00517   *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
00518   *                                             5 mode.
00519   * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
00520   *         regulator in Low-power (LP) mode to further reduce power consumption.
00521   *         When preselecting SVOS3, the use of the voltage regulator low-power
00522   *         mode (LP) can be selected by LPDS register bit.
00523   * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
00524   *         when exiting from system Stop mode.
00525   * @retval HAL Status.
00526   */
00527 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
00528 {
00529   /* Check the parameters */
00530   assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
00531
00532   /* Return the stop mode voltage range */
00533   MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
00534
00535   return HAL_OK;
00536 }
00537
00538 /**
00539   * @brief Get the main internal regulator output voltage in STOP mode.
00540   * @retval The actual applied VOS selection.
00541   */
00542 uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
00543 {
00544   /* Return the stop voltage scaling */
00545   return (PWR->CR1 & PWR_CR1_SVOS);
00546 }
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
00552   * @brief    Low power control functions
00553   *
00554 @verbatim
00555  ===============================================================================
00556                      ##### Low power control functions #####
00557  ===============================================================================
00558
00559     *** Domains Low Power modes configuration ***
00560     =============================================
00561     [..]
00562       This section provides the extended low power mode control APIs.
00563       The system presents 3 principles domains (D1, D2 and D3) that can be
00564       operated in low-power modes (DSTOP or DSTANDBY mode):
00565
00566       (+) DSTOP mode to enters a domain to STOP mode:
00567        (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
00568             subsystem is in CSTOP mode and has allocated peripheral in the
00569             domain.
00570             In DSTOP mode the domain bus matrix clock is stopped.
00571        (++) The system enters STOP mode using one of the following scenarios:
00572         (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
00573               enter DSTOP mode.
00574         (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
00575               enter DSTOP mode.
00576         (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
00577               enter DSTOP mode.
00578         (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
00579               enters DSTOP mode.
00580         (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
00581               enters DSTOP mode.
00582         (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
00583               enters DSTOP mode.
00584         (+++) D1, D2 and D3 domains enter DSTOP mode.
00585        (++) When the system enters STOP mode, the clocks are stopped and the
00586             regulator is running in main or low power mode.
00587        (++) D3 domain can be kept in Run mode regardless of the CPU status when
00588             enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
00589
00590       (+) DSTANDBY mode to enters a domain to STANDBY mode:
00591        (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
00592             register (PWR_CPUCR) for the Dn domain selects Standby mode.
00593        (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
00594             DSTANDBY mode. Consequently the VCORE supply regulator is powered
00595             off.
00596
00597    *** DSTOP mode ***
00598    ==================
00599     [..]
00600       In DStop mode the domain bus matrix clock is stopped.
00601       The Flash memory can enter low-power Stop mode when it is enabled through
00602       FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
00603       restart time and low power consumption.
00604     [..]
00605       In DStop mode domain peripherals using the LSI or LSE clock and
00606       peripherals having a kernel clock request are still able to operate.
00607     [..]
00608       Before entering DSTOP mode it is recommended to call SCB_CleanDCache
00609       function in order to clean the D-Cache and guarantee the data integrity
00610       for the SRAM memories.
00611
00612       (+) Entry:
00613          The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
00614          STOPEntry, Domain) function with:
00615          (++) Regulator:
00616           (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
00617           (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
00618          (++) STOPEntry:
00619           (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
00620           (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
00621          (++) Domain:
00622           (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
00623           (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
00624           (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
00625
00626       (+) Exit:
00627         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00628
00629    *** DSTANDBY mode ***
00630    =====================
00631     [..]
00632       In DStandby mode:
00633         (+) The domain bus matrix clock is stopped.
00634         (+) The domain is powered down and the domain RAM and register contents
00635             are lost.
00636     [..]
00637       Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
00638       function in order to clean the D-Cache and guarantee the data integrity
00639       for the SRAM memories.
00640
00641       (+) Entry:
00642          The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
00643          (Domain) function with:
00644        (++) Domain:
00645         (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
00646         (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
00647         (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
00648
00649       (+) Exit:
00650         WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
00651         wakeup, tamper event, time stamp event, external reset in NRST pin,
00652         IWDG reset.
00653
00654    *** Keep D3/SRD in RUN mode ***
00655    ===============================
00656     [..]
00657       D3/SRD domain can be kept in Run mode regardless of the CPU status when
00658       entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
00659       with :
00660        (+) D3State:
00661         (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
00662                                   mode.
00663         (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
00664                                  of CPU subsystem mode.
00665
00666     *** FLASH Power Down configuration ****
00667     =======================================
00668     [..]
00669       By setting the FLPS bit in the PWR_CR1 register using the
00670       HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
00671       power down mode when the device enters STOP mode. When the Flash memory is
00672       in power down mode, an additional startup delay is incurred when waking up
00673       from STOP mode.
00674
00675     *** Wakeup Pins configuration ****
00676     ===================================
00677     [..]
00678       Wakeup pins allow the system to exit from Standby mode. The configuration
00679       of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
00680       function with:
00681        (+) sPinParams: structure to enable and configure a wakeup pin:
00682         (++) WakeUpPin: Wakeup pin to be enabled.
00683         (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
00684         (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
00685     [..]
00686       The wakeup pins are internally connected to the EXTI lines [55-60] to
00687       generate an interrupt if enabled. The EXTI lines configuration is done by
00688       the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
00689       file.
00690     [..]
00691       When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
00692       called and the appropriate flag is set in the PWR_WKUPFR register. Then in
00693       the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
00694       cleared and the appropriate user callback will be called. The user can add
00695       his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
00696
00697 @endverbatim
00698   * @{
00699   */
00700
00701 #if defined (PWR_CPUCR_RETDS_CD)
00702 /**
00703   * @brief Enter the system to STOP mode with main domain in DSTOP2.
00704   * @note   In STOP mode, the domain bus matrix clock is stalled.
00705   * @note   In STOP mode, memories and registers are maintained and peripherals
00706   *         in CPU domain are no longer operational.
00707   * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
00708   *         HSE oscillators are disabled. Only Peripherals that have wakeup
00709   *         capability can switch on the HSI to receive a frame, and switch off
00710   *         the HSI after receiving the frame if it is not a wakeup frame. In
00711   *         this case the HSI clock is propagated only to the peripheral
00712   *         requesting it.
00713   * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
00714   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
00715   *         RCC_CFGR register is set.
00716   * @param  Regulator : Specifies the regulator state in STOP mode.
00717   *          This parameter can be one of the following values:
00718   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
00719   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
00720   *                                            regulator ON.
00721   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
00722   *                     intrinsic instruction.
00723   *          This parameter can be one of the following values:
00724   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
00725   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
00726   * @retval None.
00727   */
00728 void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
00729 {
00730   /* Check the parameters */
00731   assert_param (IS_PWR_REGULATOR (Regulator));
00732   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
00733
00734   /* Select the regulator state in Stop mode */
00735   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
00736
00737   /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
00738   SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
00739
00740   /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
00741   CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
00742
00743   /* Set SLEEPDEEP bit of Cortex System Control Register */
00744   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00745
00746   /* Ensure that all instructions are done before entering STOP mode */
00747   __ISB ();
00748   __DSB ();
00749
00750   /* Select Stop mode entry */
00751   if (STOPEntry == PWR_STOPENTRY_WFI)
00752   {
00753     /* Request Wait For Interrupt */
00754     __WFI ();
00755   }
00756   else
00757   {
00758     /* Request Wait For Event */
00759     __WFE ();
00760   }
00761
00762   /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
00763   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00764 }
00765 #endif /* defined (PWR_CPUCR_RETDS_CD) */
00766
00767 /**
00768   * @brief Enter a Domain to DSTOP mode.
00769   * @note   This API gives flexibility to manage independently each domain STOP
00770   *         mode. For dual core lines, this API should be executed with the
00771   *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
00772   *         executed by all available Cortex-Mx, the system enter to STOP mode.
00773   *         For single core lines, calling this API with domain parameter set to
00774   *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
00775   *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
00776   *         CPUCR_RUN_D3 is cleared.
00777   * @note   In DStop mode the domain bus matrix clock is stopped.
00778   * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
00779   *         is in CStop mode, the EXTI wakeup sources are inactive and at least
00780   *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
00781   *         any domain request Stop.
00782   * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
00783   *         function in order to clean the D-Cache and guarantee the data
00784   *         integrity for the SRAM memories.
00785   * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
00786   *         clock, and the peripherals that have a kernel clock request to
00787   *         select HSI or CSI as source, are still able to operate.
00788   * @param  Regulator : Specifies the regulator state in STOP mode.
00789   *          This parameter can be one of the following values:
00790   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
00791   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
00792   *                                            regulator ON.
00793   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
00794   *                     intrinsic instruction.
00795   *          This parameter can be one of the following values:
00796   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
00797   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
00798   * @param  Domain : Specifies the Domain to enter in DSTOP mode.
00799   *          This parameter can be one of the following values:
00800   *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
00801   *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
00802   *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
00803   * @retval None.
00804   */
00805 void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
00806 {
00807   /* Check the parameters */
00808   assert_param (IS_PWR_REGULATOR (Regulator));
00809   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
00810   assert_param (IS_PWR_DOMAIN (Domain));
00811
00812   /* Select the regulator state in Stop mode */
00813   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
00814
00815   /* Select the domain Power Down DeepSleep */
00816   if (Domain == PWR_D1_DOMAIN)
00817   {
00818     /* Check current core */
00819     if (HAL_GetCurrentCPUID () != CM7_CPUID)
00820     {
00821       /*
00822          When the domain selected and the cortex-mx don't match, entering stop
00823          mode will not be performed
00824       */
00825       return;
00826     }
00827
00828     /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
00829     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
00830
00831     /* Set SLEEPDEEP bit of Cortex System Control Register */
00832     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00833
00834     /* Ensure that all instructions are done before entering STOP mode */
00835     __DSB ();
00836     __ISB ();
00837
00838     /* Select Stop mode entry */
00839     if (STOPEntry == PWR_STOPENTRY_WFI)
00840     {
00841       /* Request Wait For Interrupt */
00842       __WFI ();
00843     }
00844     else
00845     {
00846       /* Request Wait For Event */
00847       __WFE ();
00848     }
00849
00850     /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
00851     CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00852   }
00853 #if defined (PWR_CPUCR_PDDS_D2)
00854   else if (Domain == PWR_D2_DOMAIN)
00855   {
00856     /* Keep DSTOP mode when D2 domain enters Deepsleep */
00857     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00858
00859 #if defined (DUAL_CORE)
00860     /* Check current core */
00861     if (HAL_GetCurrentCPUID () != CM4_CPUID)
00862     {
00863       /*
00864          When the domain selected and the cortex-mx don't match, entering stop
00865          mode will not be performed
00866       */
00867       return;
00868     }
00869
00870     /* Set SLEEPDEEP bit of Cortex System Control Register */
00871     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00872
00873     /* Ensure that all instructions are done before entering STOP mode */
00874     __DSB ();
00875     __ISB ();
00876
00877     /* Select Stop mode entry */
00878     if (STOPEntry == PWR_STOPENTRY_WFI)
00879     {
00880       /* Request Wait For Interrupt */
00881       __WFI ();
00882     }
00883     else
00884     {
00885       /* Request Wait For Event */
00886       __WFE ();
00887     }
00888
00889     /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
00890     CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00891 #endif /* defined (DUAL_CORE) */
00892   }
00893 #endif /* defined (PWR_CPUCR_PDDS_D2) */
00894   else
00895   {
00896     /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
00897     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
00898   }
00899 }
00900
00901 /**
00902   * @brief Clear pending event.
00903   * @note   This API clears the pending event in order to enter a given CPU
00904   *         to CSLEEP or CSTOP. It should be called just before APIs performing
00905   *         enter low power mode using Wait For Event request.
00906   * @retval None.
00907   */
00908 void HAL_PWREx_ClearPendingEvent (void)
00909 {
00910 #if defined (DUAL_CORE)
00911   /* Check the current Core */
00912   if (HAL_GetCurrentCPUID () == CM7_CPUID)
00913   {
00914     __WFE ();
00915   }
00916   else
00917   {
00918     __SEV ();
00919     __WFE ();
00920   }
00921 #else
00922   __WFE ();
00923 #endif /* defined (DUAL_CORE) */
00924 }
00925
00926 /**
00927   * @brief Enter a Domain to DSTANDBY mode.
00928   * @note   This API gives flexibility to manage independently each domain
00929   *         STANDBY mode. For dual core lines, this API should be executed with
00930   *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
00931   *         it is executed by all available Cortex-Mx, the system enter STANDBY
00932   *         mode.
00933   *         For single core lines, calling this API with D1/SRD the selected
00934   *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
00935   *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
00936   * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
00937   *         the Dn domain select Standby mode. When the system enters Standby
00938   *         mode, the voltage regulator is disabled.
00939   * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
00940   *         domain PDDS_Dn bit to select Stop mode, the domain remains in
00941   *         DStandby mode. The domain will only exit DStandby when the CPU
00942   *         allocates a peripheral in the domain.
00943   * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
00944   *         domain are in DStandby.
00945   * @note   Before entering DSTANDBY mode it is recommended to call
00946   *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
00947   *         the data integrity for the SRAM memories.
00948   * @param  Domain : Specifies the Domain to enter to STANDBY mode.
00949   *          This parameter can be one of the following values:
00950   *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
00951   *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
00952   *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
00953   * @retval None
00954   */
00955 void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
00956 {
00957   /* Check the parameters */
00958   assert_param (IS_PWR_DOMAIN (Domain));
00959
00960   /* Select the domain Power Down DeepSleep */
00961   if (Domain == PWR_D1_DOMAIN)
00962   {
00963     /* Check current core */
00964     if (HAL_GetCurrentCPUID () != CM7_CPUID)
00965     {
00966       /*
00967          When the domain selected and the cortex-mx don't match, entering
00968          standby mode will not be performed
00969       */
00970       return;
00971     }
00972
00973     /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
00974     SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
00975
00976 #if defined (DUAL_CORE)
00977     /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
00978     SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
00979 #endif /*DUAL_CORE*/
00980
00981     /* Set SLEEPDEEP bit of Cortex System Control Register */
00982     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00983
00984     /* This option is used to ensure that store operations are completed */
00985 #if defined (__CC_ARM)
00986     __force_stores ();
00987 #endif /* defined (__CC_ARM) */
00988
00989     /* Request Wait For Interrupt */
00990     __WFI ();
00991   }
00992 #if defined (PWR_CPUCR_PDDS_D2)
00993   else if (Domain == PWR_D2_DOMAIN)
00994   {
00995     /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
00996     SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
00997
00998 #if defined (DUAL_CORE)
00999     /* Check current core */
01000     if (HAL_GetCurrentCPUID () != CM7_CPUID)
01001     {
01002       /*
01003          When the domain selected and the cortex-mx don't match, entering
01004          standby mode will not be performed
01005       */
01006       return;
01007     }
01008
01009     /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
01010     SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
01011
01012     /* Set SLEEPDEEP bit of Cortex System Control Register */
01013     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
01014
01015     /* This option is used to ensure that store operations are completed */
01016 #if defined (__CC_ARM)
01017     __force_stores ();
01018 #endif /* defined (__CC_ARM) */
01019
01020     /* Request Wait For Interrupt */
01021     __WFI ();
01022 #endif /* defined (DUAL_CORE) */
01023   }
01024 #endif /* defined (PWR_CPUCR_PDDS_D2) */
01025   else
01026   {
01027     /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
01028     SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
01029
01030 #if defined (DUAL_CORE)
01031     /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
01032     SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
01033 #endif /* defined (DUAL_CORE) */
01034   }
01035 }
01036
01037 /**
01038   * @brief Configure the D3/SRD Domain state when the System in low power mode.
01039   * @param  D3State : Specifies the D3/SRD state.
01040   *          This parameter can be one of the following values :
01041   *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
01042   *                                      CPU sub-system low power mode.
01043   *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
01044   *                                     regardless of the CPU sub-system low
01045   *                                     power mode.
01046   * @retval None
01047   */
01048 void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
01049 {
01050   /* Check the parameter */
01051   assert_param (IS_D3_STATE (D3State));
01052
01053   /* Keep D3/SRD in run mode */
01054   MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
01055 }
01056
01057 #if defined (DUAL_CORE)
01058 /**
01059   * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
01060   *        given domain.
01061   * @param  DomainFlags : Specifies the Domain flags to be cleared.
01062   *          This parameter can be one of the following values:
01063   *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
01064   *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
01065   *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
01066   * @retval None.
01067   */
01068 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
01069 {
01070   /* Check the parameter */
01071   assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
01072
01073   /* D1 CPU flags */
01074   if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
01075   {
01076     /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
01077     SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
01078   }
01079   /* D2 CPU flags */
01080   else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
01081   {
01082     /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
01083     SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
01084   }
01085   else
01086   {
01087     /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
01088     SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
01089     /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
01090     SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
01091   }
01092 }
01093
01094 /**
01095   * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
01096   * @param  CPU : Specifies the core to be held.
01097   *         This parameter can be one of the following values:
01098   *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
01099   *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
01100   * @retval HAL status
01101   */
01102 HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
01103 {
01104   HAL_StatusTypeDef status = HAL_OK;
01105
01106   /* Check the parameters */
01107   assert_param (IS_PWR_CORE (CPU));
01108
01109   /* Check CPU index */
01110   if (CPU == PWR_CORE_CPU2)
01111   {
01112     /* If CPU1 is not held */
01113     if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
01114     {
01115       /* Set HOLD2 bit */
01116       SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
01117     }
01118     else
01119     {
01120       status = HAL_ERROR;
01121     }
01122   }
01123   else
01124   {
01125     /* If CPU2 is not held */
01126     if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
01127     {
01128       /* Set HOLD1 bit */
01129       SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
01130     }
01131     else
01132     {
01133       status = HAL_ERROR;
01134     }
01135   }
01136
01137   return status;
01138 }
01139
01140 /**
01141   * @brief Release the CPU and their domain peripherals after a wake-up from
01142   *        STOP mode.
01143   * @param  CPU: Specifies the core to be released.
01144   *         This parameter can be one of the following values:
01145   *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
01146   *                   peripherals from holding.
01147   *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
01148   *                   peripherals from holding.
01149   * @retval None
01150   */
01151 void HAL_PWREx_ReleaseCore (uint32_t CPU)
01152 {
01153   /* Check the parameters */
01154   assert_param (IS_PWR_CORE (CPU));
01155
01156   /* Check CPU index */
01157   if (CPU == PWR_CORE_CPU2)
01158   {
01159     /* Reset HOLD2 bit */
01160     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
01161   }
01162   else
01163   {
01164     /* Reset HOLD1 bit */
01165     CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
01166   }
01167 }
01168 #endif /* defined (DUAL_CORE) */
01169
01170
01171 /**
01172   * @brief Enable the Flash Power Down in Stop mode.
01173   * @note   When Flash Power Down is enabled  the Flash memory enters low-power
01174   *         mode when D1/SRD domain is in DStop mode. This feature allows to
01175   *         obtain the best trade-off between low-power consumption and restart
01176   *         time when exiting from DStop mode.
01177   * @retval None.
01178   */
01179 void HAL_PWREx_EnableFlashPowerDown (void)
01180 {
01181   /* Enable the Flash Power Down */
01182   SET_BIT (PWR->CR1, PWR_CR1_FLPS);
01183 }
01184
01185 /**
01186   * @brief Disable the Flash Power Down in Stop mode.
01187   * @note   When Flash Power Down is disabled  the Flash memory is kept on
01188   *         normal mode when D1/SRD domain is in DStop mode. This feature allows
01189   *         to obtain the best trade-off between low-power consumption and
01190   *         restart time when exiting from DStop mode.
01191   * @retval None.
01192   */
01193 void HAL_PWREx_DisableFlashPowerDown (void)
01194 {
01195   /* Disable the Flash Power Down */
01196   CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
01197 }
01198
01199 #if defined (PWR_CR1_SRDRAMSO)
01200 /**
01201   * @brief Enable memory block shut-off in DStop or DStop2 modes
01202   * @note   In DStop or DStop2 mode, the content of the memory blocks is
01203   *         maintained. Further power optimization can be obtained by switching
01204   *         off some memory blocks. This optimization implies loss of the memory
01205   *         content. The user can select which memory is discarded during STOP
01206   *         mode by means of xxSO bits.
01207   * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
01208   *                       DStop2 mode.
01209   *          This parameter can be one of the following values:
01210   *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
01211   *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
01212   *                                              FDCAN memories.
01213   *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
01214   *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
01215   *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
01216   *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
01217   *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
01218   *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
01219   *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
01220   * @retval None.
01221   */
01222 void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
01223 {
01224   /* Check the parameter */
01225   assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
01226
01227   /* Enable memory block shut-off */
01228   SET_BIT (PWR->CR1, MemoryBlock);
01229 }
01230
01231 /**
01232   * @brief Disable memory block shut-off in DStop or DStop2 modes
01233   * @param  MemoryBlock : Specifies the memory block to keep content during
01234   *                       DStop or DStop2 mode.
01235   *          This parameter can be one of the following values:
01236   *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
01237   *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
01238   *                                              FDCAN memories.
01239   *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
01240   *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
01241   *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
01242   *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
01243   *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
01244   *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
01245   *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
01246   * @retval None.
01247   */
01248 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
01249 {
01250   /* Check the parameter */
01251   assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
01252
01253   /* Disable memory block shut-off */
01254   CLEAR_BIT (PWR->CR1, MemoryBlock);
01255 }
01256 #endif /* defined (PWR_CR1_SRDRAMSO) */
01257
01258 /**
01259   * @brief Enable the Wake-up PINx functionality.
01260   * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
01261   *                      contains the configuration information for the wake-up
01262   *                      Pin.
01263   * @note   For dual core devices, please ensure to configure the EXTI lines for
01264   *         the different Cortex-Mx. All combination are allowed: wake up only
01265   *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
01266   *         Cortex-M4.
01267   * @retval None.
01268   */
01269 void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
01270 {
01271   uint32_t pinConfig;
01272   uint32_t regMask;
01273   const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
01274
01275   /* Check the parameters */
01276   assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
01277   assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
01278   assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
01279
01280   pinConfig = sPinParams->WakeUpPin | \
01281               (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
01282               (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
01283
01284   regMask   = sPinParams->WakeUpPin | \
01285               (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
01286               (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
01287
01288   /* Enable and Specify the Wake-Up pin polarity and the pull configuration
01289      for the event detection (rising or falling edge) */
01290   MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
01291 #ifndef DUAL_CORE
01292   /* Configure the Wakeup Pin EXTI Line */
01293   MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
01294 #endif /* !DUAL_CORE */
01295 }
01296
01297 /**
01298   * @brief Disable the Wake-up PINx functionality.
01299   * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
01300   *          This parameter can be one of the following values:
01301   *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
01302   *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
01303   *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
01304   *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
01305   *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
01306   *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
01307   * @retval None
01308   */
01309 void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
01310 {
01311   /* Check the parameter */
01312   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
01313
01314   /* Disable the WakeUpPin */
01315   CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
01316 }
01317
01318 /**
01319   * @brief Get the Wake-Up Pin pending flags.
01320   * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
01321   *          This parameter can be one of the following values:
01322   *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
01323   *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
01324   *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PC1.
01325   *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
01326   *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI8.
01327   *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PI11.
01328   *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
01329   *                                      wake up pins.
01330   * @retval The Wake-Up pin flag.
01331   */
01332 uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
01333 {
01334   /* Check the parameters */
01335   assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
01336
01337   /* Return the wake up pin flag */
01338   return (PWR->WKUPFR & WakeUpFlag);
01339 }
01340
01341 /**
01342   * @brief Clear the Wake-Up pin pending flag.
01343   * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
01344   *          This parameter can be one of the following values:
01345   *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
01346   *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
01347   *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PC1.
01348   *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
01349   *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI8.
01350   *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PI11.
01351   *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
01352   *                                      all wake up pins.
01353   * @retval HAL status.
01354   */
01355 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
01356 {
01357   /* Check the parameter */
01358   assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
01359
01360   /* Clear the wake up event received from wake up pin x */
01361   SET_BIT (PWR->WKUPCR, WakeUpFlag);
01362
01363   /* Check if the wake up event is well cleared */
01364   if ((PWR->WKUPFR & WakeUpFlag) != 0U)
01365   {
01366     return HAL_ERROR;
01367   }
01368
01369   return HAL_OK;
01370 }
01371
01372 /**
01373   * @brief This function handles the PWR WAKEUP PIN interrupt request.
01374   * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
01375   * @retval None.
01376   */
01377 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
01378 {
01379   /* Wakeup pin EXTI line interrupt detected */
01380   if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
01381   {
01382     /* Clear PWR WKUPF1 flag */
01383     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
01384
01385     /* PWR WKUP1 interrupt user callback */
01386     HAL_PWREx_WKUP1_Callback ();
01387   }
01388   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
01389   {
01390     /* Clear PWR WKUPF2 flag */
01391     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
01392
01393     /* PWR WKUP2 interrupt user callback */
01394     HAL_PWREx_WKUP2_Callback ();
01395   }
01396   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
01397   {
01398     /* Clear PWR WKUPF3 flag */
01399     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
01400
01401     /* PWR WKUP3 interrupt user callback */
01402     HAL_PWREx_WKUP3_Callback ();
01403   }
01404   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
01405   {
01406     /* Clear PWR WKUPF4 flag */
01407     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
01408
01409     /* PWR WKUP4 interrupt user callback */
01410     HAL_PWREx_WKUP4_Callback ();
01411   }
01412   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
01413   {
01414     /* Clear PWR WKUPF5 flag */
01415     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
01416
01417     /* PWR WKUP5 interrupt user callback */
01418     HAL_PWREx_WKUP5_Callback ();
01419   }
01420   else
01421   {
01422     /* Clear PWR WKUPF6 flag */
01423     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
01424
01425     /* PWR WKUP6 interrupt user callback */
01426     HAL_PWREx_WKUP6_Callback ();
01427   }
01428 }
01429
01430 /**
01431   * @brief PWR WKUP1 interrupt callback.
01432   * @retval None.
01433   */
01434 __weak void HAL_PWREx_WKUP1_Callback (void)
01435 {
01436   /* NOTE : This function should not be modified, when the callback is needed,
01437             the HAL_PWREx_WKUP1Callback can be implemented in the user file
01438   */
01439 }
01440
01441 /**
01442   * @brief PWR WKUP2 interrupt callback.
01443   * @retval None.
01444   */
01445 __weak void HAL_PWREx_WKUP2_Callback (void)
01446 {
01447   /* NOTE : This function should not be modified, when the callback is needed,
01448             the HAL_PWREx_WKUP2Callback can be implemented in the user file
01449   */
01450 }
01451
01452 /**
01453   * @brief PWR WKUP3 interrupt callback.
01454   * @retval None.
01455   */
01456 __weak void HAL_PWREx_WKUP3_Callback (void)
01457 {
01458   /* NOTE : This function should not be modified, when the callback is needed,
01459             the HAL_PWREx_WKUP3Callback can be implemented in the user file
01460   */
01461 }
01462
01463 /**
01464   * @brief PWR WKUP4 interrupt callback.
01465   * @retval None.
01466   */
01467 __weak void HAL_PWREx_WKUP4_Callback (void)
01468 {
01469   /* NOTE : This function should not be modified, when the callback is needed,
01470             the HAL_PWREx_WKUP4Callback can be implemented in the user file
01471   */
01472 }
01473
01474 /**
01475   * @brief PWR WKUP5 interrupt callback.
01476   * @retval None.
01477   */
01478 __weak void HAL_PWREx_WKUP5_Callback (void)
01479 {
01480   /* NOTE : This function should not be modified, when the callback is needed,
01481             the HAL_PWREx_WKUP5Callback can be implemented in the user file
01482   */
01483 }
01484
01485 /**
01486   * @brief PWR WKUP6 interrupt callback.
01487   * @retval None.
01488   */
01489 __weak void HAL_PWREx_WKUP6_Callback (void)
01490 {
01491   /* NOTE : This function should not be modified, when the callback is needed,
01492             the HAL_PWREx_WKUP6Callback can be implemented in the user file
01493   */
01494 }
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
01500   * @brief    Peripherals control functions
01501   *
01502 @verbatim
01503  ===============================================================================
01504                  ##### Peripherals control functions #####
01505  ===============================================================================
01506
01507     *** Main and Backup Regulators configuration ***
01508     ================================================
01509     [..]
01510       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
01511           from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
01512           content is retained even in Standby or VBAT mode when the low power
01513           backup regulator is enabled. It can be considered as an internal
01514           EEPROM when VBAT is always present. You can use the
01515           HAL_PWREx_EnableBkUpReg() function to enable the low power backup
01516           regulator.
01517       (+) When the backup domain is supplied by VDD (analog switch connected to
01518           VDD) the backup SRAM is powered from VDD which replaces the VBAT power
01519           supply to save battery life.
01520       (+) The backup SRAM is not mass erased by a tamper event. It is read
01521           protected to prevent confidential data, such as cryptographic private
01522           key, from being accessed. The backup SRAM can be erased only through
01523           the Flash interface when a protection level change from level 1 to
01524           level 0 is requested.
01525       -@- Refer to the description of Read protection (RDP) in the Flash
01526           programming manual.
01527       (+) The main internal regulator can be configured to have a tradeoff
01528           between performance and power consumption when the device does not
01529           operate at the maximum frequency. This is done through
01530           HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
01531           bit in PWR_D3CR register.
01532       (+) The main internal regulator can be configured to operate in Low Power
01533           mode when the system enters STOP mode to further reduce power
01534           consumption.
01535           This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
01536           function which configure the SVOS bit in PWR_CR1 register.
01537           The selected SVOS4 and SVOS5 levels add an additional startup delay
01538           when exiting from system Stop mode.
01539     -@- Refer to the product datasheets for more details.
01540
01541     *** USB Regulator configuration ***
01542     ===================================
01543     [..]
01544       (+) The USB transceivers are supplied from a dedicated VDD33USB supply
01545           that can be provided either by the integrated USB regulator, or by an
01546           external USB supply.
01547       (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
01548           VDD33USB is then provided from the USB regulator.
01549       (+) When the USB regulator is enabled, the VDD33USB supply level detector
01550           shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
01551           function.
01552       (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
01553           function and VDD33USB can be provided from an external supply. In this
01554           case VDD33USB and VDD50USB shall be connected together.
01555
01556     *** VBAT battery charging ***
01557     =============================
01558     [..]
01559       (+) When VDD is present, the external battery connected to VBAT can be
01560           charged through an internal resistance. VBAT charging can be performed
01561           either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
01562       (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
01563           (ResistorValue) function with:
01564        (++) ResistorValue:
01565         (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
01566         (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
01567       (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
01568           function.
01569
01570 @endverbatim
01571   * @{
01572   */
01573
01574 /**
01575   * @brief Enable the Backup Regulator.
01576   * @retval HAL status.
01577   */
01578 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
01579 {
01580   uint32_t tickstart;
01581
01582   /* Enable the Backup regulator */
01583   SET_BIT (PWR->CR2, PWR_CR2_BREN);
01584
01585   /* Get tick */
01586   tickstart = HAL_GetTick ();
01587
01588   /* Wait till Backup regulator ready flag is set */
01589   while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
01590   {
01591     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
01592     {
01593       return HAL_ERROR;
01594     }
01595   }
01596
01597   return HAL_OK;
01598 }
01599
01600 /**
01601   * @brief Disable the Backup Regulator.
01602   * @retval HAL status.
01603   */
01604 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
01605 {
01606   uint32_t tickstart;
01607
01608   /* Disable the Backup regulator */
01609   CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
01610
01611   /* Get tick */
01612   tickstart = HAL_GetTick ();
01613
01614   /* Wait till Backup regulator ready flag is reset */
01615   while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
01616   {
01617     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
01618     {
01619       return HAL_ERROR;
01620     }
01621   }
01622
01623   return HAL_OK;
01624 }
01625
01626 /**
01627   * @brief Enable the USB Regulator.
01628   * @retval HAL status.
01629   */
01630 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
01631 {
01632   uint32_t tickstart;
01633
01634   /* Enable the USB regulator */
01635   SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
01636
01637   /* Get tick */
01638   tickstart = HAL_GetTick ();
01639
01640   /* Wait till the USB regulator ready flag is set */
01641   while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
01642   {
01643     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
01644     {
01645       return HAL_ERROR;
01646     }
01647   }
01648
01649   return HAL_OK;
01650 }
01651
01652 /**
01653   * @brief Disable the USB Regulator.
01654   * @retval HAL status.
01655   */
01656 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
01657 {
01658   uint32_t tickstart;
01659
01660   /* Disable the USB regulator */
01661   CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
01662
01663   /* Get tick */
01664   tickstart = HAL_GetTick ();
01665
01666   /* Wait till the USB regulator ready flag is reset */
01667   while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
01668   {
01669     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
01670     {
01671       return HAL_ERROR;
01672     }
01673   }
01674
01675   return HAL_OK;
01676 }
01677
01678 /**
01679   * @brief Enable the USB voltage level detector.
01680   * @retval None.
01681   */
01682 void HAL_PWREx_EnableUSBVoltageDetector (void)
01683 {
01684   /* Enable the USB voltage detector */
01685   SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
01686 }
01687
01688 /**
01689   * @brief Disable the USB voltage level detector.
01690   * @retval None.
01691   */
01692 void HAL_PWREx_DisableUSBVoltageDetector (void)
01693 {
01694   /* Disable the USB voltage detector */
01695   CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
01696 }
01697
01698 /**
01699   * @brief Enable the Battery charging.
01700   * @note   When VDD is present, charge the external battery through an internal
01701   *         resistor.
01702   * @param  ResistorValue : Specifies the charging resistor.
01703   *          This parameter can be one of the following values :
01704   *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
01705   *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
01706   * @retval None.
01707   */
01708 void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
01709 {
01710   /* Check the parameter */
01711   assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
01712
01713   /* Specify the charging resistor */
01714   MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
01715
01716   /* Enable the Battery charging */
01717   SET_BIT (PWR->CR3, PWR_CR3_VBE);
01718 }
01719
01720 /**
01721   * @brief Disable the Battery charging.
01722   * @retval None.
01723   */
01724 void HAL_PWREx_DisableBatteryCharging (void)
01725 {
01726   /* Disable the Battery charging */
01727   CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
01728 }
01729
01730 #if defined (PWR_CR1_BOOSTE)
01731 /**
01732   * @brief Enable the booster to guarantee the analog switch AC performance when
01733   *        the VDD supply voltage is below 2V7.
01734   * @note   The VDD supply voltage can be monitored through the PVD and the PLS
01735   *         field bits.
01736   * @retval None.
01737   */
01738 void HAL_PWREx_EnableAnalogBooster (void)
01739 {
01740   /* Enable the Analog voltage */
01741   SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
01742
01743   /* Enable VDDA booster */
01744   SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
01745 }
01746
01747 /**
01748   * @brief Disable the analog booster.
01749   * @retval None.
01750   */
01751 void HAL_PWREx_DisableAnalogBooster (void)
01752 {
01753   /* Disable VDDA booster */
01754   CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
01755
01756   /* Disable the Analog voltage */
01757   CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
01758 }
01759 #endif /* defined (PWR_CR1_BOOSTE) */
01760 /**
01761   * @}
01762   */
01763
01764 /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
01765   * @brief    Power Monitoring functions
01766   *
01767 @verbatim
01768  ===============================================================================
01769                  ##### Power Monitoring functions #####
01770  ===============================================================================
01771
01772     *** VBAT and Temperature supervision ***
01773     ========================================
01774     [..]
01775       (+) The VBAT battery voltage supply can be monitored by comparing it with
01776           two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
01777           in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
01778           lower than the threshold.
01779       (+) The temperature can be monitored by comparing it with two threshold
01780           levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
01781           control register 2 (PWR_CR2), indicate whether the device temperature
01782           is higher or lower than the threshold.
01783       (+) The VBAT and the temperature monitoring is enabled by
01784           HAL_PWREx_EnableMonitoring() function and disabled by
01785           HAL_PWREx_DisableMonitoring() function.
01786       (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
01787           be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
01788           PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
01789       (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
01790           level which can be :
01791           PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
01792           PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
01793
01794     *** AVD configuration ***
01795     =========================
01796     [..]
01797       (+) The AVD is used to monitor the VDDA power supply by comparing it to a
01798           threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
01799           register).
01800       (+) A AVDO flag is available to indicate if VDDA is higher or lower
01801           than the AVD threshold. This event is internally connected to the EXTI
01802           line 16 to generate an interrupt if enabled.
01803           It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
01804       (+) The AVD is stopped in System Standby mode.
01805
01806 @endverbatim
01807   * @{
01808   */
01809
01810 /**
01811   * @brief Enable the VBAT and temperature monitoring.
01812   * @retval HAL status.
01813   */
01814 void HAL_PWREx_EnableMonitoring (void)
01815 {
01816   /* Enable the VBAT and Temperature monitoring */
01817   SET_BIT (PWR->CR2, PWR_CR2_MONEN);
01818 }
01819
01820 /**
01821   * @brief Disable the VBAT and temperature monitoring.
01822   * @retval HAL status.
01823   */
01824 void HAL_PWREx_DisableMonitoring (void)
01825 {
01826   /* Disable the VBAT and Temperature monitoring */
01827   CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
01828 }
01829
01830 /**
01831   * @brief Indicate whether the junction temperature is between, above or below
01832   *        the thresholds.
01833   * @retval Temperature level.
01834   */
01835 uint32_t HAL_PWREx_GetTemperatureLevel (void)
01836 {
01837   uint32_t tempLevel, regValue;
01838
01839   /* Read the temperature flags */
01840   regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
01841
01842   /* Check if the temperature is below the threshold */
01843   if (regValue == PWR_CR2_TEMPL)
01844   {
01845     tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
01846   }
01847   /* Check if the temperature is above the threshold */
01848   else if (regValue == PWR_CR2_TEMPH)
01849   {
01850     tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
01851   }
01852   /* The temperature is between the thresholds */
01853   else
01854   {
01855     tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
01856   }
01857
01858   return tempLevel;
01859 }
01860
01861 /**
01862   * @brief Indicate whether the Battery voltage level is between, above or below
01863   *        the thresholds.
01864   * @retval VBAT level.
01865   */
01866 uint32_t HAL_PWREx_GetVBATLevel (void)
01867 {
01868   uint32_t VBATLevel, regValue;
01869
01870   /* Read the VBAT flags */
01871   regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
01872
01873   /* Check if the VBAT is below the threshold */
01874   if (regValue == PWR_CR2_VBATL)
01875   {
01876     VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
01877   }
01878   /* Check if the VBAT is above the threshold */
01879   else if (regValue == PWR_CR2_VBATH)
01880   {
01881     VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
01882   }
01883   /* The VBAT is between the thresholds */
01884   else
01885   {
01886     VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
01887   }
01888
01889   return VBATLevel;
01890 }
01891
01892 #if defined (PWR_CSR1_MMCVDO)
01893 /**
01894   * @brief Get the VDDMMC voltage level.
01895   * @retval The VDDMMC voltage level.
01896   */
01897 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
01898 {
01899   PWREx_MMC_VoltageLevel mmc_voltage;
01900
01901   /* Check voltage detector output on VDDMMC value */
01902   if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
01903   {
01904     mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
01905   }
01906   else
01907   {
01908     mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
01909   }
01910
01911   return mmc_voltage;
01912 }
01913 #endif /* defined (PWR_CSR1_MMCVDO) */
01914
01915 /**
01916   * @brief  Configure the event mode and the voltage threshold detected by the
01917   *         Analog Voltage Detector (AVD).
01918   * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
01919   *                      the configuration information for the AVD.
01920   * @note   Refer to the electrical characteristics of your device datasheet for
01921   *         more details about the voltage threshold corresponding to each
01922   *         detection level.
01923   * @note   For dual core devices, please ensure to configure the EXTI lines for
01924   *         the different Cortex-Mx through PWR_Exported_Macro provided by this
01925   *         driver. All combination are allowed: wake up only Cortex-M7, wake up
01926   *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
01927   * @retval None.
01928   */
01929 void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
01930 {
01931   /* Check the parameters */
01932   assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
01933   assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
01934
01935   /* Set the ALS[18:17] bits according to AVDLevel value */
01936   MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
01937
01938   /* Clear any previous config */
01939 #if !defined (DUAL_CORE)
01940   __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
01941   __HAL_PWR_AVD_EXTI_DISABLE_IT ();
01942 #endif /* !defined (DUAL_CORE) */
01943
01944   __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
01945   __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
01946
01947 #if !defined (DUAL_CORE)
01948   /* Configure the interrupt mode */
01949   if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
01950   {
01951     __HAL_PWR_AVD_EXTI_ENABLE_IT ();
01952   }
01953
01954   /* Configure the event mode */
01955   if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
01956   {
01957     __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
01958   }
01959 #endif /* !defined (DUAL_CORE) */
01960
01961   /* Rising edge configuration */
01962   if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
01963   {
01964     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
01965   }
01966
01967   /* Falling edge configuration */
01968   if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
01969   {
01970     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
01971   }
01972 }
01973
01974 /**
01975   * @brief Enable the Analog Voltage Detector (AVD).
01976   * @retval None.
01977   */
01978 void HAL_PWREx_EnableAVD (void)
01979 {
01980   /* Enable the Analog Voltage Detector */
01981   SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
01982 }
01983
01984 /**
01985   * @brief Disable the Analog Voltage Detector(AVD).
01986   * @retval None.
01987   */
01988 void HAL_PWREx_DisableAVD (void)
01989 {
01990   /* Disable the Analog Voltage Detector */
01991   CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
01992 }
01993
01994 /**
01995   * @brief  This function handles the PWR PVD/AVD interrupt request.
01996   * @note   This API should be called under the PVD_AVD_IRQHandler().
01997   * @retval None
01998   */
01999 void HAL_PWREx_PVD_AVD_IRQHandler (void)
02000 {
02001   /* Check if the Programmable Voltage Detector is enabled (PVD) */
02002   if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
02003   {
02004     if (HAL_GetCurrentCPUID () == CM7_CPUID)
02005     {
02006       /* Check PWR D1/CD EXTI flag */
02007       if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
02008       {
02009         /* PWR PVD interrupt user callback */
02010         HAL_PWR_PVDCallback ();
02011
02012         /* Clear PWR EXTI D1/CD pending bit */
02013         __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
02014       }
02015     }
02016 #if defined (DUAL_CORE)
02017     else
02018     {
02019       /* Check PWR EXTI D2 flag */
02020       if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
02021       {
02022         /* PWR PVD interrupt user callback */
02023         HAL_PWR_PVDCallback ();
02024
02025         /* Clear PWR EXTI D2 pending bit */
02026         __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
02027       }
02028     }
02029 #endif /* defined (DUAL_CORE) */
02030   }
02031
02032   /* Check if the Analog Voltage Detector is enabled (AVD) */
02033   if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
02034   {
02035     if (HAL_GetCurrentCPUID () == CM7_CPUID)
02036     {
02037       /* Check PWR EXTI D1/CD flag */
02038       if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
02039       {
02040         /* PWR AVD interrupt user callback */
02041         HAL_PWREx_AVDCallback ();
02042
02043         /* Clear PWR EXTI D1/CD pending bit */
02044         __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
02045       }
02046     }
02047 #if defined (DUAL_CORE)
02048     else
02049     {
02050       /* Check PWR EXTI D2 flag */
02051       if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
02052       {
02053         /* PWR AVD interrupt user callback */
02054         HAL_PWREx_AVDCallback ();
02055
02056         /* Clear PWR EXTI D2 pending bit */
02057         __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
02058       }
02059     }
02060 #endif /* defined (DUAL_CORE) */
02061   }
02062 }
02063
02064 /**
02065   * @brief PWR AVD interrupt callback.
02066   * @retval None.
02067   */
02068 __weak void HAL_PWREx_AVDCallback (void)
02069 {
02070   /* NOTE : This function should not be modified, when the callback is needed,
02071             the HAL_PWR_AVDCallback can be implemented in the user file
02072   */
02073 }
02074 /**
02075   * @}
02076   */
02077
02078 /**
02079   * @}
02080   */
02081
02082 #endif /* HAL_PWR_MODULE_ENABLED */
02083
02084 /**
02085   * @}
02086   */
02087
02088 /**
02089   * @}
02090   */
02091
02092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_pwr_ex.h Source File

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stm32h7xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_PWR_EX_H
00022 #define STM32H7xx_HAL_PWR_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif /* __cplusplus */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup PWREx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup PWREx_Exported_Types PWREx Exported Types
00041   * @{
00042   */
00043 /**
00044   * @brief  PWREx AVD configuration structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
00049                           parameter can be a value of @ref
00050                           PWREx_AVD_detection_level
00051                      */
00052
00053   uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
00054                                  event. This parameter can be a value of @ref
00055                                  PWREx_AVD_Mode.
00056                      */
00057 }PWREx_AVDTypeDef;
00058
00059 /**
00060   * @brief  PWREx Wakeup pin configuration structure definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
00065                                         This parameter can be a value of @ref
00066                                         PWREx_WakeUp_Pins
00067                         */
00068
00069   uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
00070                                           This parameter can be a value of @ref
00071                                           PWREx_PIN_Polarity
00072                         */
00073
00074   uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
00075                                       parameter can be a value of @ref
00076                                       PWREx_PIN_Pull
00077                         */
00078 }PWREx_WakeupPinTypeDef;
00079
00080 #if defined (PWR_CSR1_MMCVDO)
00081 /**
00082   * @brief  PWR VDDMMC voltage level enum definition
00083   */
00084 typedef enum
00085 {
00086   PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
00087   PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
00088 } PWREx_MMC_VoltageLevel;
00089 #endif /* defined (PWR_CSR1_MMCVDO) */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096
00097 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
00098   * @{
00099   */
00100 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
00101   * @{
00102   */
00103 /* High level and No pull (default configuration) */
00104 #define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
00105 #define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
00106 #define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
00107 #define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
00108 #define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
00109 #define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
00110
00111 /* High level and No pull */
00112 #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
00113 #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
00114 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
00115 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
00116 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
00117 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
00118
00119 /* Low level and No pull */
00120 #define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
00121 #define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
00122 #define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
00123 #define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
00124 #define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
00125 #define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
00131   * @{
00132   */
00133 #define PWR_PIN_POLARITY_HIGH (0x00000000U)
00134 #define PWR_PIN_POLARITY_LOW  (0x00000001U)
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
00140   * @{
00141   */
00142 #define PWR_PIN_NO_PULL   (0x00000000U)
00143 #define PWR_PIN_PULL_UP   (0x00000001U)
00144 #define PWR_PIN_PULL_DOWN (0x00000002U)
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
00150   * @{
00151   */
00152 #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on pin 1 */
00153 #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on pin 2 */
00154 #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on pin 3 */
00155 #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on pin 4 */
00156 #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on pin 5 */
00157 #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on pin 6 */
00158 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
00159                              PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
00160                              PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
00161 /**
00162   * @}
00163   */
00164
00165 #if defined (DUAL_CORE)
00166 /** @defgroup PWREx_Core_Select PWREx Core definition
00167   * @{
00168   */
00169 #define PWR_CORE_CPU1 (0x00000000U)
00170 #define PWR_CORE_CPU2 (0x00000001U)
00171 /**
00172   * @}
00173   */
00174 #endif /* defined (DUAL_CORE) */
00175
00176 /** @defgroup PWREx_Domains PWREx Domains definition
00177   * @{
00178   */
00179 #define PWR_D1_DOMAIN (0x00000000U)
00180 #if defined (PWR_CPUCR_PDDS_D2)
00181 #define PWR_D2_DOMAIN (0x00000001U)
00182 #endif /* defined (PWR_CPUCR_PDDS_D2) */
00183 #define PWR_D3_DOMAIN (0x00000002U)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
00189   * @{
00190   */
00191 #if defined (DUAL_CORE)
00192 #define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
00193 #define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
00194 #define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
00195 #else
00196 #define PWR_CPU_FLAGS       (0x00000000U)
00197 #endif /* defined (DUAL_CORE) */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup PWREx_D3_State PWREx D3 Domain State
00203   * @{
00204   */
00205 #define PWR_D3_DOMAIN_STOP (0x00000000U)
00206 #define PWR_D3_DOMAIN_RUN  (0x00000800U)
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration
00213   * @{
00214   */
00215 #define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
00216 #if defined (SMPS)
00217 #define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
00218 #define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
00219 #define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
00220 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
00221 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
00222 #define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
00223 #define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
00224 #endif /* defined (SMPS) */
00225 #define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
00226
00227 #if defined (SMPS)
00228 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
00229                                 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
00230 #else
00231 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
00232 #endif /* defined (SMPS) */
00233 /**
00234   * @}
00235   */
00236
00237
00238 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
00239   * @{
00240   */
00241 #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
00242 #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
00243 #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
00244 #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode
00250   * @{
00251   */
00252 #define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
00253 #define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
00254 #define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
00255 #define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00256 #define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
00257 #define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
00258 #define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
00264   * @{
00265   */
00266 #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
00267 #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
00268 #define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
00274   * @{
00275   */
00276 #define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
00277 #define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
00283   * @{
00284   */
00285 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
00286 #define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
00287 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
00293   * @{
00294   */
00295 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
00296 #define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
00297 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
00298 /**
00299   * @}
00300   */
00301 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
00302   * @{
00303   */
00304 #define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
00305                                               Connected to the AVD EXTI Line */
00306 /**
00307   * @}
00308   */
00309
00310 #if defined (PWR_CR1_SRDRAMSO)
00311 /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
00312   * @{
00313   */
00314 #define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
00315 #define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
00316 #define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
00317 #define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
00318 #define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
00319 #define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
00320 #define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
00321 #define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
00322 #define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
00323 #define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
00324 #define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
00325 /**
00326   * @}
00327   */
00328 #endif /* defined (PWR_CR1_SRDRAMSO) */
00329 /**
00330   * @}
00331   */
00332
00333 /* Exported macro ------------------------------------------------------------*/
00334
00335 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
00336   *  @{
00337   */
00338
00339 /**
00340   * @brief Enable the AVD EXTI Line 16.
00341   * @retval None.
00342   */
00343 #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
00344
00345 #if defined (DUAL_CORE)
00346 /**
00347   * @brief Enable the AVD EXTI D2 Line 16.
00348   * @retval None.
00349   */
00350 #define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
00351 #endif /* defined (DUAL_CORE) */
00352
00353 /**
00354   * @brief Disable the AVD EXTI Line 16
00355   * @retval None.
00356   */
00357 #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
00358
00359 #if defined (DUAL_CORE)
00360 /**
00361   * @brief Disable the AVD EXTI D2 Line 16.
00362   * @retval None.
00363   */
00364 #define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
00365 #endif /* defined (DUAL_CORE) */
00366
00367 /**
00368   * @brief Enable event on AVD EXTI Line 16.
00369   * @retval None.
00370   */
00371 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
00372
00373 #if defined (DUAL_CORE)
00374 /**
00375   * @brief Enable event on AVD EXTI D2 Line 16.
00376   * @retval None.
00377   */
00378 #define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
00379 #endif /* defined (DUAL_CORE) */
00380
00381 /**
00382   * @brief Disable event on AVD EXTI Line 16.
00383   * @retval None.
00384   */
00385 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
00386
00387 #if defined (DUAL_CORE)
00388 /**
00389   * @brief Disable event on AVD EXTI D2 Line 16.
00390   * @retval None.
00391   */
00392 #define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
00393 #endif /* defined (DUAL_CORE) */
00394
00395 /**
00396   * @brief Enable the AVD Extended Interrupt Rising Trigger.
00397   * @retval None.
00398   */
00399 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
00400
00401 /**
00402   * @brief Disable the AVD Extended Interrupt Rising Trigger.
00403   * @retval None.
00404   */
00405 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
00406
00407 /**
00408   * @brief Enable the AVD Extended Interrupt Falling Trigger.
00409   * @retval None.
00410   */
00411 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
00412
00413 /**
00414   * @brief Disable the AVD Extended Interrupt Falling Trigger.
00415   * @retval None.
00416   */
00417 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
00418
00419 /**
00420   * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
00421   * @retval None.
00422   */
00423 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
00424 do {                                                    \
00425      __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
00426      __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
00427 } while(0);
00428
00429 /**
00430   * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
00431   * @retval None.
00432   */
00433 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
00434 do {                                                     \
00435      __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
00436      __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
00437 } while(0);
00438
00439 /**
00440   * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
00441   * @retval EXTI AVD Line Status.
00442   */
00443 #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
00444
00445 #if defined (DUAL_CORE)
00446 /**
00447   * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
00448   * @retval EXTI D2 AVD Line Status.
00449   */
00450 #define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
00451 #endif /* defined (DUAL_CORE) */
00452
00453 /**
00454   * @brief  Clear the AVD EXTI flag.
00455   * @retval None.
00456   */
00457 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
00458
00459 #if defined (DUAL_CORE)
00460 /**
00461   * @brief  Clear the AVD EXTI D2 flag.
00462   * @retval None.
00463   */
00464 #define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
00465 #endif /* defined (DUAL_CORE) */
00466
00467 /**
00468   * @brief  Generates a Software interrupt on AVD EXTI line.
00469   * @retval None.
00470   */
00471 #define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
00472 /**
00473   * @}
00474   */
00475
00476 /* Exported functions --------------------------------------------------------*/
00477
00478 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
00479   * @{
00480   */
00481
00482 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
00483   * @{
00484   */
00485 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
00486 uint32_t HAL_PWREx_GetSupplyConfig(void);
00487 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00488 uint32_t HAL_PWREx_GetVoltageRange(void);
00489 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
00490 uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
00491 /**
00492   * @}
00493   */
00494
00495 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
00496   * @{
00497   */
00498 /* System low power control functions */
00499 #if defined (PWR_CPUCR_RETDS_CD)
00500 void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
00501 #endif /* defined (PWR_CPUCR_RETDS_CD) */
00502 void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
00503 void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
00504 void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
00505 /* Clear Cortex-Mx pending flag */
00506 void HAL_PWREx_ClearPendingEvent(void);
00507 #if defined (DUAL_CORE)
00508 /* Clear domain flags */
00509 void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
00510 /* Core Hold/Release functions */
00511 HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
00512 void HAL_PWREx_ReleaseCore(uint32_t CPU);
00513 #endif /* defined (DUAL_CORE) */
00514 /* Flash low power control functions */
00515 void HAL_PWREx_EnableFlashPowerDown(void);
00516 void HAL_PWREx_DisableFlashPowerDown(void);
00517 #if defined (PWR_CR1_SRDRAMSO)
00518 /* Memory shut-off functions */
00519 void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
00520 void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
00521 #endif /* defined(PWR_CR1_SRDRAMSO) */
00522 /* Wakeup Pins control functions */
00523 void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
00524 void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
00525 uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
00526 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
00527 /* Power Wakeup PIN IRQ Handler */
00528 void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
00529 void HAL_PWREx_WKUP1_Callback(void);
00530 void HAL_PWREx_WKUP2_Callback(void);
00531 void HAL_PWREx_WKUP3_Callback(void);
00532 void HAL_PWREx_WKUP4_Callback(void);
00533 void HAL_PWREx_WKUP5_Callback(void);
00534 void HAL_PWREx_WKUP6_Callback(void);
00535 /**
00536   * @}
00537   */
00538
00539 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
00540   * @{
00541   */
00542 /* Backup regulator control functions */
00543 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
00544 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
00545 /* USB regulator control functions */
00546 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
00547 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
00548 void HAL_PWREx_EnableUSBVoltageDetector(void);
00549 void HAL_PWREx_DisableUSBVoltageDetector(void);
00550 /* Battery control functions */
00551 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
00552 void HAL_PWREx_DisableBatteryCharging(void);
00553 #if defined(PWR_CR1_BOOSTE)
00554 /* Analog Booster functions */
00555 void HAL_PWREx_EnableAnalogBooster(void);
00556 void HAL_PWREx_DisableAnalogBooster(void);
00557 #endif /* PWR_CR1_BOOSTE */
00558 /**
00559   * @}
00560   */
00561
00562 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
00563   * @{
00564   */
00565 /* Power VBAT/Temperature monitoring functions */
00566 void HAL_PWREx_EnableMonitoring(void);
00567 void HAL_PWREx_DisableMonitoring(void);
00568 uint32_t HAL_PWREx_GetTemperatureLevel(void);
00569 uint32_t HAL_PWREx_GetVBATLevel(void);
00570 #if defined(PWR_CSR1_MMCVDO)
00571 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
00572 #endif /* PWR_CSR1_MMCVDO */
00573 /* Power AVD configuration functions */
00574 void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
00575 void HAL_PWREx_EnableAVD(void);
00576 void HAL_PWREx_DisableAVD(void);
00577 /* Power PVD/AVD IRQ Handler */
00578 void HAL_PWREx_PVD_AVD_IRQHandler(void);
00579 void HAL_PWREx_AVDCallback(void);
00580 /**
00581   * @}
00582   */
00583
00584 /**
00585   * @}
00586   */
00587 /* Private types -------------------------------------------------------------*/
00588 /* Private variables ---------------------------------------------------------*/
00589 /* Private constants ---------------------------------------------------------*/
00590 /* Private macros ------------------------------------------------------------*/
00591 /** @defgroup PWREx_Private_Macros PWREx Private Macros
00592   * @{
00593   */
00594
00595 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
00596   * @{
00597   */
00598 /* Check PWR regulator configuration parameter */
00599 #if defined (SMPS)
00600 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
00601                                    ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
00602                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
00603                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
00604                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
00605                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
00606                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
00607                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
00608                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
00609
00610 #else
00611 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
00612                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
00613 #endif /* defined (SMPS) */
00614
00615 /* Check PWR regulator configuration in STOP mode parameter */
00616 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
00617                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
00618                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
00619
00620 /* Check PWR domain parameter */
00621 #if defined (PWR_CPUCR_PDDS_D2)
00622 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
00623                                ((DOMAIN) == PWR_D2_DOMAIN) ||\
00624                                ((DOMAIN) == PWR_D3_DOMAIN))
00625 #else
00626 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
00627                                ((DOMAIN) == PWR_D3_DOMAIN))
00628 #endif /* defined (PWR_CPUCR_PDDS_D2) */
00629
00630 /* Check D3/SRD domain state parameter */
00631 #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
00632                             ((STATE) == PWR_D3_DOMAIN_RUN))
00633
00634 /* Check wake up pin parameter */
00635 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
00636                                 ((PIN) == PWR_WAKEUP_PIN2)      ||\
00637                                 ((PIN) == PWR_WAKEUP_PIN3)      ||\
00638                                 ((PIN) == PWR_WAKEUP_PIN4)      ||\
00639                                 ((PIN) == PWR_WAKEUP_PIN5)      ||\
00640                                 ((PIN) == PWR_WAKEUP_PIN6)      ||\
00641                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
00642                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
00643                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
00644                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
00645                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
00646                                 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
00647                                 ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
00648                                 ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
00649                                 ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
00650                                 ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
00651                                 ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
00652                                 ((PIN) == PWR_WAKEUP_PIN6_LOW))
00653
00654 /* Check wake up pin polarity parameter */
00655 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
00656                                               ((POLARITY) == PWR_PIN_POLARITY_LOW))
00657
00658 /* Check wake up pin pull configuration parameter */
00659 #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
00660                                       ((PULL) == PWR_PIN_PULL_UP) ||\
00661                                       ((PULL) == PWR_PIN_PULL_DOWN))
00662
00663 /* Check wake up flag parameter */
00664 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
00665                                   ((FLAG) == PWR_WAKEUP_FLAG2) ||\
00666                                   ((FLAG) == PWR_WAKEUP_FLAG3) ||\
00667                                   ((FLAG) == PWR_WAKEUP_FLAG4) ||\
00668                                   ((FLAG) == PWR_WAKEUP_FLAG5) ||\
00669                                   ((FLAG) == PWR_WAKEUP_FLAG6) ||\
00670                                   ((FLAG) == PWR_WAKEUP_FLAG_ALL))
00671
00672 /* Check wake up flag parameter */
00673 #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
00674                                  ((LEVEL) == PWR_AVDLEVEL_1) ||\
00675                                  ((LEVEL) == PWR_AVDLEVEL_2) ||\
00676                                  ((LEVEL) == PWR_AVDLEVEL_3))
00677
00678 /* Check AVD mode parameter */
00679 #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
00680                                ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
00681                                ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
00682                                ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
00683                                ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
00684                                ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
00685                                ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
00686
00687 /* Check resistor battery parameter */
00688 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00689                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00690 /* Check D1/CD CPU ID parameter */
00691 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
00692
00693 #if defined (DUAL_CORE)
00694 /* Check CPU parameter */
00695 #define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
00696
00697 /* Check D2 CPU ID parameter */
00698 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
00699
00700 /* Check PWR domain flag parameter */
00701 #define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
00702                                    ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
00703                                    ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
00704 #endif /* defined (DUAL_CORE) */
00705
00706 #if defined (PWR_CR1_SRDRAMSO)
00707 /* Check memory block parameter */
00708 #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
00709                                     ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
00710                                     ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
00711                                     ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
00712                                     ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
00713                                     ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
00714                                     ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
00715                                     ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
00716                                     ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
00717 #endif /* defined (PWR_CR1_SRDRAMSO) */
00718 /**
00719   * @}
00720   */
00721 /**
00722   * @}
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 /**
00730   * @}
00731   */
00732 #ifdef __cplusplus
00733 }
00734 #endif /* __cplusplus */
00735
00736
00737 #endif /* STM32H7xx_HAL_PWR_EX_H */
00738
00739 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_qspi.c Source File

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stm32h7xx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @brief   QSPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the QuadSPI interface (QSPI).
00008   *           + Initialization and de-initialization functions
00009   *           + Indirect functional mode management
00010   *           + Memory-mapped functional mode management
00011   *           + Auto-polling functional mode management
00012   *           + Interrupts and flags management
00013   *           + MDMA channel configuration for indirect functional mode
00014   *           + Errors management and abort functionality
00015   *
00016   *
00017   @verbatim
00018  ===============================================================================
00019                         ##### How to use this driver #####
00020  ===============================================================================
00021   [..]
00022     *** Initialization ***
00023     ======================
00024     [..]
00025       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00026         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00027         (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00028         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00029         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00030         (++) If interrupt mode is used, enable and configure QuadSPI global
00031             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00032         (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
00033             with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
00034             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00035             MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00036       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00037           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00038
00039     *** Indirect functional mode ***
00040     ================================
00041     [..]
00042       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00043           functions :
00044          (++) Instruction phase : the mode used and if present the instruction opcode.
00045          (++) Address phase : the mode used and if present the size and the address value.
00046          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00047              bytes values.
00048          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00049          (++) Data phase : the mode used and if present the number of bytes.
00050          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00051              if activated.
00052          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00053       (#) If no data is required for the command, it is sent directly to the memory :
00054          (++) In polling mode, the output of the function is done when the transfer is complete.
00055          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00056       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00057           HAL_QSPI_Transmit_IT() after the command configuration :
00058          (++) In polling mode, the output of the function is done when the transfer is complete.
00059          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00060              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00061          (++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00062       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00063           HAL_QSPI_Receive_IT() after the command configuration :
00064          (++) In polling mode, the output of the function is done when the transfer is complete.
00065          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00066              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00067          (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00068
00069     *** Auto-polling functional mode ***
00070     ====================================
00071     [..]
00072       (#) Configure the command sequence and the auto-polling functional mode using the
00073           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00074          (++) Instruction phase : the mode used and if present the instruction opcode.
00075          (++) Address phase : the mode used and if present the size and the address value.
00076          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00077              bytes values.
00078          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00079          (++) Data phase : the mode used.
00080          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00081              if activated.
00082          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00083          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00084              the polling interval and the automatic stop activation.
00085       (#) After the configuration :
00086          (++) In polling mode, the output of the function is done when the status match is reached. The
00087              automatic stop is activated to avoid an infinite loop.
00088          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00089
00090     *** MDMA functional mode ***
00091     ====================================
00092     [..]
00093       (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
00094          (++) MDMA settings for write operation :
00095           (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
00096           (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
00097           (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
00098               aligned with @ref MDMA_Source_increment_mode .
00099           (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
00100          (++) MDMA settings for read operation :
00101           (+) The SourceInc should be MDMA_SRC_INC_DISABLE
00102           (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
00103           (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
00104           (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
00105               aligned with @ref MDMA_Destination_increment_mode.
00106          (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
00107       (#)In case of wrong MDMA setting
00108         (++) For write operation :
00109          (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
00110         (++) For read operation :
00111          (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().
00112
00113     *** Memory-mapped functional mode ***
00114     =====================================
00115     [..]
00116       (#) Configure the command sequence and the memory-mapped functional mode using the
00117           HAL_QSPI_MemoryMapped() functions :
00118          (++) Instruction phase : the mode used and if present the instruction opcode.
00119          (++) Address phase : the mode used and the size.
00120          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00121              bytes values.
00122          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00123          (++) Data phase : the mode used.
00124          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00125              if activated.
00126          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00127          (++) The timeout activation and the timeout period.
00128       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00129           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00130
00131     *** Errors management and abort functionality ***
00132     =================================================
00133     [..]
00134       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00135       (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
00136           flushes the fifo :
00137          (++) In polling mode, the output of the function is done when the transfer
00138               complete bit is set and the busy bit cleared.
00139          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
00140               the transfer complete bi is set.
00141
00142     *** Control functions ***
00143     =========================
00144     [..]
00145       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00146       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
00147       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
00148       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00149
00150     *** Callback registration ***
00151     =============================================
00152     [..]
00153       The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
00154       allows the user to configure dynamically the driver callbacks.
00155
00156       Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
00157       it allows to register following callbacks:
00158         (+) ErrorCallback : callback when error occurs.
00159         (+) AbortCpltCallback : callback when abort is completed.
00160         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00161         (+) CmdCpltCallback : callback when a command without data is completed.
00162         (+) RxCpltCallback : callback when a reception transfer is completed.
00163         (+) TxCpltCallback : callback when a transmission transfer is completed.
00164         (+) StatusMatchCallback : callback when a status match occurs.
00165         (+) TimeOutCallback : callback when the timeout perioed expires.
00166         (+) MspInitCallback    : QSPI MspInit.
00167         (+) MspDeInitCallback  : QSPI MspDeInit.
00168       This function takes as parameters the HAL peripheral handle, the Callback ID
00169       and a pointer to the user callback function.
00170
00171       Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
00172       weak (surcharged) function. It allows to reset following callbacks:
00173         (+) ErrorCallback : callback when error occurs.
00174         (+) AbortCpltCallback : callback when abort is completed.
00175         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00176         (+) CmdCpltCallback : callback when a command without data is completed.
00177         (+) RxCpltCallback : callback when a reception transfer is completed.
00178         (+) TxCpltCallback : callback when a transmission transfer is completed.
00179         (+) StatusMatchCallback : callback when a status match occurs.
00180         (+) TimeOutCallback : callback when the timeout perioed expires.
00181         (+) MspInitCallback    : QSPI MspInit.
00182         (+) MspDeInitCallback  : QSPI MspDeInit.
00183       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00184
00185       By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
00186       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00187       Exception done for MspInit and MspDeInit callbacks that are respectively
00188       reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
00189       and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
00190       If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
00191       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00192
00193       Callbacks can be registered/unregistered in READY state only.
00194       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00195       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00196       during the Init/DeInit.
00197       In that case first register the MspInit/MspDeInit user callbacks
00198       using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
00199       or @ref HAL_QSPI_Init function.
00200
00201       When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
00202       not defined, the callback registering feature is not available
00203       and weak (surcharged) callbacks are used.
00204
00205     *** Workarounds linked to Silicon Limitation ***
00206     ====================================================
00207     [..]
00208       (#) Workarounds Implemented inside HAL Driver
00209          (++) Extra data written in the FIFO at the end of a read transfer
00210
00211   @endverbatim
00212   ******************************************************************************
00213   * @attention
00214   *
00215   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00216   * All rights reserved.</center></h2>
00217   *
00218   * This software component is licensed by ST under BSD 3-Clause license,
00219   * the "License"; You may not use this file except in compliance with the
00220   * License. You may obtain a copy of the License at:
00221   *                        opensource.org/licenses/BSD-3-Clause
00222   *
00223   ******************************************************************************
00224   */
00225
00226 /* Includes ------------------------------------------------------------------*/
00227 #include "stm32h7xx_hal.h"
00228
00229 /** @addtogroup STM32H7xx_HAL_Driver
00230   * @{
00231   */
00232
00233 #ifdef HAL_QSPI_MODULE_ENABLED
00234
00235 #if defined(QUADSPI)
00236
00237 /** @defgroup QSPI QSPI
00238   * @brief QSPI HAL module driver
00239   * @{
00240   */
00241
00242 /* Private typedef -----------------------------------------------------------*/
00243
00244 /* Private define ------------------------------------------------------------*/
00245 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00246   * @{
00247   */
00248 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
00249 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00250 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00251 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00252 /**
00253   * @}
00254   */
00255
00256 /* Private macro -------------------------------------------------------------*/
00257 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00258   * @{
00259   */
00260 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00261                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00262                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00263                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00264 /**
00265   * @}
00266   */
00267
00268 /* Private variables ---------------------------------------------------------*/
00269
00270 /* Private function prototypes -----------------------------------------------*/
00271 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma);
00272 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma);
00273 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma);
00274 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
00275 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
00276 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00277
00278 /* Exported functions --------------------------------------------------------*/
00279
00280 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00281   * @{
00282   */
00283
00284 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00285   *  @brief    Initialization and Configuration functions
00286   *
00287 @verbatim
00288 ===============================================================================
00289             ##### Initialization and Configuration functions #####
00290  ===============================================================================
00291     [..]
00292     This subsection provides a set of functions allowing to :
00293       (+) Initialize the QuadSPI.
00294       (+) De-initialize the QuadSPI.
00295
00296 @endverbatim
00297   * @{
00298   */
00299
00300 /**
00301   * @brief Initialize the QSPI mode according to the specified parameters
00302   *        in the QSPI_InitTypeDef and initialize the associated handle.
00303   * @param hqspi: QSPI handle
00304   * @retval HAL status
00305   */
00306 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00307 {
00308   HAL_StatusTypeDef status;
00309   uint32_t tickstart = HAL_GetTick();
00310
00311   /* Check the QSPI handle allocation */
00312   if(hqspi == NULL)
00313   {
00314     return HAL_ERROR;
00315   }
00316
00317   /* Check the parameters */
00318   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00319   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00320   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00321   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00322   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00323   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00324   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00325   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00326
00327   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00328   {
00329     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00330   }
00331
00332   /* Process locked */
00333   __HAL_LOCK(hqspi);
00334
00335   if(hqspi->State == HAL_QSPI_STATE_RESET)
00336   {
00337     /* Allocate lock resource and initialize it */
00338     hqspi->Lock = HAL_UNLOCKED;
00339
00340 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00341     /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
00342     hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
00343     hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
00344     hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
00345     hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
00346     hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
00347     hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
00348     hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
00349     hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
00350
00351     if(hqspi->MspInitCallback == NULL)
00352     {
00353       hqspi->MspInitCallback = HAL_QSPI_MspInit;
00354     }
00355
00356     /* Init the low level hardware */
00357     hqspi->MspInitCallback(hqspi);
00358 #else
00359     /* Init the low level hardware : GPIO, CLOCK */
00360     HAL_QSPI_MspInit(hqspi);
00361 #endif
00362     /* Configure the default timeout for the QSPI memory access */
00363     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
00364   }
00365
00366   /* Configure QSPI FIFO Threshold */
00367   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
00368              ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
00369
00370   /* Wait till BUSY flag reset */
00371   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00372
00373   if(status == HAL_OK)
00374   {
00375     /* Configure QSPI Clock Prescaler and Sample Shift */
00376     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
00377                ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
00378                 hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
00379
00380     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00381     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00382                ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
00383                 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00384
00385     /* Enable the QSPI peripheral */
00386     __HAL_QSPI_ENABLE(hqspi);
00387
00388     /* Set QSPI error code to none */
00389     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00390
00391     /* Initialize the QSPI state */
00392     hqspi->State = HAL_QSPI_STATE_READY;
00393   }
00394
00395   /* Release Lock */
00396   __HAL_UNLOCK(hqspi);
00397
00398   /* Return function status */
00399   return status;
00400 }
00401
00402 /**
00403   * @brief De-Initialize the QSPI peripheral.
00404   * @param hqspi: QSPI handle
00405   * @retval HAL status
00406   */
00407 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00408 {
00409   /* Check the QSPI handle allocation */
00410   if(hqspi == NULL)
00411   {
00412     return HAL_ERROR;
00413   }
00414
00415   /* Process locked */
00416   __HAL_LOCK(hqspi);
00417
00418   /* Disable the QSPI Peripheral Clock */
00419   __HAL_QSPI_DISABLE(hqspi);
00420
00421 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00422   if(hqspi->MspDeInitCallback == NULL)
00423   {
00424     hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
00425   }
00426
00427   /* DeInit the low level hardware */
00428   hqspi->MspDeInitCallback(hqspi);
00429 #else
00430   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00431   HAL_QSPI_MspDeInit(hqspi);
00432 #endif
00433
00434   /* Set QSPI error code to none */
00435   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00436
00437   /* Initialize the QSPI state */
00438   hqspi->State = HAL_QSPI_STATE_RESET;
00439
00440   /* Release Lock */
00441   __HAL_UNLOCK(hqspi);
00442
00443   return HAL_OK;
00444 }
00445
00446 /**
00447   * @brief Initialize the QSPI MSP.
00448   * @param hqspi: QSPI handle
00449   * @retval None
00450   */
00451 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hqspi);
00455
00456   /* NOTE : This function should not be modified, when the callback is needed,
00457             the HAL_QSPI_MspInit can be implemented in the user file
00458    */
00459 }
00460
00461 /**
00462   * @brief DeInitialize the QSPI MSP.
00463   * @param hqspi: QSPI handle
00464   * @retval None
00465   */
00466 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00467 {
00468   /* Prevent unused argument(s) compilation warning */
00469   UNUSED(hqspi);
00470
00471   /* NOTE : This function should not be modified, when the callback is needed,
00472             the HAL_QSPI_MspDeInit can be implemented in the user file
00473    */
00474 }
00475
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
00481   *  @brief QSPI Transmit/Receive functions
00482   *
00483 @verbatim
00484  ===============================================================================
00485                       ##### IO operation functions #####
00486  ===============================================================================
00487     [..]
00488     This subsection provides a set of functions allowing to :
00489       (+) Handle the interrupts.
00490       (+) Handle the command sequence.
00491       (+) Transmit data in blocking, interrupt or DMA mode.
00492       (+) Receive data in blocking, interrupt or DMA mode.
00493       (+) Manage the auto-polling functional mode.
00494       (+) Manage the memory-mapped functional mode.
00495
00496 @endverbatim
00497   * @{
00498   */
00499
00500 /**
00501   * @brief Handle QSPI interrupt request.
00502   * @param hqspi: QSPI handle
00503   * @retval None
00504   */
00505 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00506 {
00507   __IO uint32_t *data_reg;
00508   uint32_t flag = READ_REG(hqspi->Instance->SR);
00509   uint32_t itsource = READ_REG(hqspi->Instance->CR);
00510
00511   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
00512   if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
00513   {
00514     data_reg = &hqspi->Instance->DR;
00515
00516     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00517     {
00518       /* Transmission process */
00519       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00520       {
00521         if (hqspi->TxXferCount > 0U)
00522         {
00523           /* Fill the FIFO until the threshold is reached */
00524           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
00525           hqspi->pTxBuffPtr++;
00526           hqspi->TxXferCount--;
00527         }
00528         else
00529         {
00530           /* No more data available for the transfer */
00531           /* Disable the QSPI FIFO Threshold Interrupt */
00532           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00533           break;
00534         }
00535       }
00536     }
00537     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00538     {
00539       /* Receiving Process */
00540       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00541       {
00542         if (hqspi->RxXferCount > 0U)
00543         {
00544           /* Read the FIFO until the threshold is reached */
00545           *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
00546           hqspi->pRxBuffPtr++;
00547           hqspi->RxXferCount--;
00548         }
00549         else
00550         {
00551           /* All data have been received for the transfer */
00552           /* Disable the QSPI FIFO Threshold Interrupt */
00553           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00554           break;
00555         }
00556       }
00557     }
00558     else
00559     {
00560       /* Nothing to do */
00561     }
00562     /* FIFO Threshold callback */
00563 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00564     hqspi->FifoThresholdCallback(hqspi);
00565 #else
00566     HAL_QSPI_FifoThresholdCallback(hqspi);
00567 #endif
00568   }
00569
00570   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00571   else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
00572   {
00573     /* Clear interrupt */
00574     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
00575
00576     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00577     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00578
00579     /* Transfer complete callback */
00580     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00581     {
00582       if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
00583       {
00584         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00585         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00586
00587         /* Disable the MDMA channel */
00588         __HAL_MDMA_DISABLE(hqspi->hmdma);
00589       }
00590
00591       /* Change state of QSPI */
00592       hqspi->State = HAL_QSPI_STATE_READY;
00593
00594       /* TX Complete callback */
00595 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00596       hqspi->TxCpltCallback(hqspi);
00597 #else
00598       HAL_QSPI_TxCpltCallback(hqspi);
00599 #endif
00600     }
00601     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00602     {
00603       if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
00604       {
00605         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00606         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00607
00608         /* Disable the MDMA channel */
00609         __HAL_MDMA_DISABLE(hqspi->hmdma);
00610       }
00611       else
00612       {
00613         data_reg = &hqspi->Instance->DR;
00614         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
00615         {
00616           if (hqspi->RxXferCount > 0U)
00617           {
00618             /* Read the last data received in the FIFO until it is empty */
00619             *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
00620             hqspi->pRxBuffPtr++;
00621             hqspi->RxXferCount--;
00622           }
00623           else
00624           {
00625             /* All data have been received for the transfer */
00626             break;
00627           }
00628         }
00629       }
00630
00631       /* Change state of QSPI */
00632       hqspi->State = HAL_QSPI_STATE_READY;
00633
00634       /* RX Complete callback */
00635 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00636       hqspi->RxCpltCallback(hqspi);
00637 #else
00638       HAL_QSPI_RxCpltCallback(hqspi);
00639 #endif
00640     }
00641     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00642     {
00643       /* Change state of QSPI */
00644       hqspi->State = HAL_QSPI_STATE_READY;
00645
00646       /* Command Complete callback */
00647 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00648       hqspi->CmdCpltCallback(hqspi);
00649 #else
00650       HAL_QSPI_CmdCpltCallback(hqspi);
00651 #endif
00652     }
00653     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
00654     {
00655       /* Reset functional mode configuration to indirect write mode by default */
00656       CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
00657
00658       /* Change state of QSPI */
00659       hqspi->State = HAL_QSPI_STATE_READY;
00660
00661       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
00662       {
00663         /* Abort called by the user */
00664
00665         /* Abort Complete callback */
00666 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00667         hqspi->AbortCpltCallback(hqspi);
00668 #else
00669         HAL_QSPI_AbortCpltCallback(hqspi);
00670 #endif
00671       }
00672       else
00673       {
00674         /* Abort due to an error (eg :  MDMA error) */
00675
00676         /* Error callback */
00677 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00678         hqspi->ErrorCallback(hqspi);
00679 #else
00680         HAL_QSPI_ErrorCallback(hqspi);
00681 #endif
00682       }
00683     }
00684     else
00685     {
00686      /* Nothing to do */
00687     }
00688   }
00689
00690   /* QSPI Status Match interrupt occurred ------------------------------------*/
00691   else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
00692   {
00693     /* Clear interrupt */
00694     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
00695
00696     /* Check if the automatic poll mode stop is activated */
00697     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
00698     {
00699       /* Disable the QSPI Transfer Error and Status Match Interrupts */
00700       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
00701
00702       /* Change state of QSPI */
00703       hqspi->State = HAL_QSPI_STATE_READY;
00704     }
00705
00706     /* Status match callback */
00707 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00708     hqspi->StatusMatchCallback(hqspi);
00709 #else
00710     HAL_QSPI_StatusMatchCallback(hqspi);
00711 #endif
00712   }
00713
00714   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00715   else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
00716   {
00717     /* Clear interrupt */
00718     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
00719
00720     /* Disable all the QSPI Interrupts */
00721     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00722
00723     /* Set error code */
00724     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00725
00726     if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
00727     {
00728       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00729       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00730
00731       /* Disable the MDMA channel */
00732       hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
00733       if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
00734       {
00735         /* Set error code to DMA */
00736         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
00737
00738         /* Change state of QSPI */
00739         hqspi->State = HAL_QSPI_STATE_READY;
00740
00741         /* Error callback */
00742 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00743         hqspi->ErrorCallback(hqspi);
00744 #else
00745         HAL_QSPI_ErrorCallback(hqspi);
00746 #endif
00747       }
00748     }
00749     else
00750     {
00751       /* Change state of QSPI */
00752       hqspi->State = HAL_QSPI_STATE_READY;
00753
00754       /* Error callback */
00755 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00756       hqspi->ErrorCallback(hqspi);
00757 #else
00758       HAL_QSPI_ErrorCallback(hqspi);
00759 #endif
00760     }
00761   }
00762
00763   /* QSPI Timeout interrupt occurred -----------------------------------------*/
00764   else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
00765   {
00766     /* Clear interrupt */
00767     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
00768
00769     /* Timeout callback */
00770 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00771     hqspi->TimeOutCallback(hqspi);
00772 #else
00773     HAL_QSPI_TimeOutCallback(hqspi);
00774 #endif
00775   }
00776    else
00777   {
00778    /* Nothing to do */
00779   }
00780 }
00781
00782 /**
00783   * @brief Set the command configuration.
00784   * @param hqspi: QSPI handle
00785   * @param cmd : structure that contains the command configuration information
00786   * @param Timeout : Timeout duration
00787   * @note   This function is used only in Indirect Read or Write Modes
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00791 {
00792   HAL_StatusTypeDef status;
00793   uint32_t tickstart = HAL_GetTick();
00794
00795   /* Check the parameters */
00796   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00797   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00798   {
00799     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00800   }
00801
00802   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00803   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00804   {
00805     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00806   }
00807
00808   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00809   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00810   {
00811     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00812   }
00813
00814   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00815   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00816
00817   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00818   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00819   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00820
00821   /* Process locked */
00822   __HAL_LOCK(hqspi);
00823
00824   if(hqspi->State == HAL_QSPI_STATE_READY)
00825   {
00826     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00827
00828     /* Update QSPI state */
00829     hqspi->State = HAL_QSPI_STATE_BUSY;
00830
00831     /* Wait till BUSY flag reset */
00832     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00833
00834     if (status == HAL_OK)
00835     {
00836       /* Call the configuration function */
00837       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00838
00839       if (cmd->DataMode == QSPI_DATA_NONE)
00840       {
00841         /* When there is no data phase, the transfer start as soon as the configuration is done
00842         so wait until TC flag is set to go back in idle state */
00843         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00844
00845         if (status == HAL_OK)
00846         {
00847           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00848
00849           /* Update QSPI state */
00850           hqspi->State = HAL_QSPI_STATE_READY;
00851         }
00852
00853       }
00854       else
00855       {
00856         /* Update QSPI state */
00857         hqspi->State = HAL_QSPI_STATE_READY;
00858       }
00859     }
00860   }
00861   else
00862   {
00863     status = HAL_BUSY;
00864   }
00865
00866   /* Process unlocked */
00867   __HAL_UNLOCK(hqspi);
00868
00869   /* Return function status */
00870   return status;
00871 }
00872
00873 /**
00874   * @brief Set the command configuration in interrupt mode.
00875   * @param hqspi: QSPI handle
00876   * @param cmd : structure that contains the command configuration information
00877   * @note   This function is used only in Indirect Read or Write Modes
00878   * @retval HAL status
00879   */
00880 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00881 {
00882   HAL_StatusTypeDef status;
00883   uint32_t tickstart = HAL_GetTick();
00884
00885   /* Check the parameters */
00886   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00887   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00888   {
00889     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00890   }
00891
00892   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00893   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00894   {
00895     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00896   }
00897
00898   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00899   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00900   {
00901     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00902   }
00903
00904   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00905   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00906
00907   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00908   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00909   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00910
00911   /* Process locked */
00912   __HAL_LOCK(hqspi);
00913
00914   if(hqspi->State == HAL_QSPI_STATE_READY)
00915   {
00916     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00917
00918     /* Update QSPI state */
00919     hqspi->State = HAL_QSPI_STATE_BUSY;
00920
00921     /* Wait till BUSY flag reset */
00922     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00923
00924     if (status == HAL_OK)
00925     {
00926       if (cmd->DataMode == QSPI_DATA_NONE)
00927       {
00928         /* Clear interrupt */
00929         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
00930       }
00931
00932       /* Call the configuration function */
00933       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00934
00935       if (cmd->DataMode == QSPI_DATA_NONE)
00936       {
00937         /* When there is no data phase, the transfer start as soon as the configuration is done
00938         so activate TC and TE interrupts */
00939         /* Process unlocked */
00940         __HAL_UNLOCK(hqspi);
00941
00942         /* Enable the QSPI Transfer Error Interrupt */
00943         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00944       }
00945       else
00946       {
00947         /* Update QSPI state */
00948         hqspi->State = HAL_QSPI_STATE_READY;
00949
00950         /* Process unlocked */
00951         __HAL_UNLOCK(hqspi);
00952       }
00953     }
00954     else
00955     {
00956       /* Process unlocked */
00957       __HAL_UNLOCK(hqspi);
00958     }
00959   }
00960   else
00961   {
00962     status = HAL_BUSY;
00963
00964     /* Process unlocked */
00965     __HAL_UNLOCK(hqspi);
00966   }
00967
00968   /* Return function status */
00969   return status;
00970 }
00971
00972 /**
00973   * @brief Transmit an amount of data in blocking mode.
00974   * @param hqspi: QSPI handle
00975   * @param pData: pointer to data buffer
00976   * @param Timeout : Timeout duration
00977   * @note   This function is used only in Indirect Write Mode
00978   * @retval HAL status
00979   */
00980 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00981 {
00982   HAL_StatusTypeDef status = HAL_OK;
00983   uint32_t tickstart = HAL_GetTick();
00984   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00985
00986   /* Process locked */
00987   __HAL_LOCK(hqspi);
00988
00989   if(hqspi->State == HAL_QSPI_STATE_READY)
00990   {
00991     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00992
00993     if(pData != NULL )
00994     {
00995       /* Update state */
00996       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00997
00998       /* Configure counters and size of the handle */
00999       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01000       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01001       hqspi->pTxBuffPtr = pData;
01002
01003       /* Configure QSPI: CCR register with functional as indirect write */
01004       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01005
01006       while(hqspi->TxXferCount > 0U)
01007       {
01008         /* Wait until FT flag is set to send data */
01009         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
01010
01011         if (status != HAL_OK)
01012         {
01013           break;
01014         }
01015
01016         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
01017         hqspi->pTxBuffPtr++;
01018         hqspi->TxXferCount--;
01019       }
01020
01021       if (status == HAL_OK)
01022       {
01023         /* Wait until TC flag is set to go back in idle state */
01024         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01025
01026         if (status == HAL_OK)
01027         {
01028           /* Clear Transfer Complete bit */
01029           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01030
01031         }
01032       }
01033
01034       /* Update QSPI state */
01035       hqspi->State = HAL_QSPI_STATE_READY;
01036     }
01037     else
01038     {
01039       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01040       status = HAL_ERROR;
01041     }
01042   }
01043   else
01044   {
01045     status = HAL_BUSY;
01046   }
01047
01048   /* Process unlocked */
01049   __HAL_UNLOCK(hqspi);
01050
01051   return status;
01052 }
01053
01054
01055 /**
01056   * @brief Receive an amount of data in blocking mode.
01057   * @param hqspi: QSPI handle
01058   * @param pData: pointer to data buffer
01059   * @param Timeout : Timeout duration
01060   * @note   This function is used only in Indirect Read Mode
01061   * @retval HAL status
01062   */
01063 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
01064 {
01065   HAL_StatusTypeDef status = HAL_OK;
01066   uint32_t tickstart = HAL_GetTick();
01067   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01068   __IO uint32_t *data_reg = &hqspi->Instance->DR;
01069
01070   /* Process locked */
01071   __HAL_LOCK(hqspi);
01072
01073   if(hqspi->State == HAL_QSPI_STATE_READY)
01074   {
01075     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01076
01077     if(pData != NULL )
01078     {
01079       /* Update state */
01080       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01081
01082       /* Configure counters and size of the handle */
01083       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01084       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01085       hqspi->pRxBuffPtr = pData;
01086
01087       /* Configure QSPI: CCR register with functional as indirect read */
01088       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01089
01090       /* Start the transfer by re-writing the address in AR register */
01091       WRITE_REG(hqspi->Instance->AR, addr_reg);
01092
01093       while(hqspi->RxXferCount > 0U)
01094       {
01095         /* Wait until FT or TC flag is set to read received data */
01096         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
01097
01098         if  (status != HAL_OK)
01099         {
01100           break;
01101         }
01102
01103         *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
01104         hqspi->pRxBuffPtr++;
01105         hqspi->RxXferCount--;
01106       }
01107
01108       if (status == HAL_OK)
01109       {
01110         /* Wait until TC flag is set to go back in idle state */
01111         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01112
01113         if  (status == HAL_OK)
01114         {
01115           /* Clear Transfer Complete bit */
01116           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01117         }
01118       }
01119
01120       /* Update QSPI state */
01121       hqspi->State = HAL_QSPI_STATE_READY;
01122     }
01123     else
01124     {
01125       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01126       status = HAL_ERROR;
01127     }
01128   }
01129   else
01130   {
01131     status = HAL_BUSY;
01132   }
01133
01134   /* Process unlocked */
01135   __HAL_UNLOCK(hqspi);
01136
01137   return status;
01138 }
01139
01140 /**
01141   * @brief  Send an amount of data in non-blocking mode with interrupt.
01142   * @param  hqspi: QSPI handle
01143   * @param  pData: pointer to data buffer
01144   * @note   This function is used only in Indirect Write Mode
01145   * @retval HAL status
01146   */
01147 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01148 {
01149   HAL_StatusTypeDef status = HAL_OK;
01150
01151   /* Process locked */
01152   __HAL_LOCK(hqspi);
01153
01154   if(hqspi->State == HAL_QSPI_STATE_READY)
01155   {
01156     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01157
01158     if(pData != NULL )
01159     {
01160       /* Update state */
01161       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01162
01163       /* Configure counters and size of the handle */
01164       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01165       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01166       hqspi->pTxBuffPtr = pData;
01167
01168       /* Clear interrupt */
01169       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01170
01171       /* Configure QSPI: CCR register with functional as indirect write */
01172       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01173
01174       /* Process unlocked */
01175       __HAL_UNLOCK(hqspi);
01176
01177       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01178       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01179     }
01180     else
01181     {
01182       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01183       status = HAL_ERROR;
01184
01185       /* Process unlocked */
01186       __HAL_UNLOCK(hqspi);
01187     }
01188   }
01189   else
01190   {
01191     status = HAL_BUSY;
01192
01193     /* Process unlocked */
01194     __HAL_UNLOCK(hqspi);
01195   }
01196
01197   return status;
01198 }
01199
01200 /**
01201   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01202   * @param  hqspi: QSPI handle
01203   * @param  pData: pointer to data buffer
01204   * @note   This function is used only in Indirect Read Mode
01205   * @retval HAL status
01206   */
01207 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01208 {
01209   HAL_StatusTypeDef status = HAL_OK;
01210   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01211
01212   /* Process locked */
01213   __HAL_LOCK(hqspi);
01214
01215   if(hqspi->State == HAL_QSPI_STATE_READY)
01216   {
01217     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01218
01219     if(pData != NULL )
01220     {
01221       /* Update state */
01222       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01223
01224       /* Configure counters and size of the handle */
01225       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01226       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01227       hqspi->pRxBuffPtr = pData;
01228
01229       /* Clear interrupt */
01230       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01231
01232       /* Configure QSPI: CCR register with functional as indirect read */
01233       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01234
01235       /* Start the transfer by re-writing the address in AR register */
01236       WRITE_REG(hqspi->Instance->AR, addr_reg);
01237
01238       /* Process unlocked */
01239       __HAL_UNLOCK(hqspi);
01240
01241       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01242       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01243     }
01244     else
01245     {
01246       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01247       status = HAL_ERROR;
01248
01249       /* Process unlocked */
01250       __HAL_UNLOCK(hqspi);
01251     }
01252   }
01253   else
01254   {
01255     status = HAL_BUSY;
01256
01257     /* Process unlocked */
01258     __HAL_UNLOCK(hqspi);
01259   }
01260
01261   return status;
01262 }
01263
01264 /**
01265   * @brief  Send an amount of data in non-blocking mode with DMA.
01266   * @param  hqspi: QSPI handle
01267   * @param  pData: pointer to data buffer
01268   * @note   This function is used only in Indirect Write Mode
01269   * @note   If MDMA peripheral access is configured as halfword, the number
01270   *         of data and the fifo threshold should be aligned on halfword
01271   * @note   If MDMA peripheral access is configured as word, the number
01272   *         of data and the fifo threshold should be aligned on word
01273   * @retval HAL status
01274   */
01275 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01276 {
01277   HAL_StatusTypeDef status = HAL_OK;
01278
01279   /* Process locked */
01280   __HAL_LOCK(hqspi);
01281
01282   if(hqspi->State == HAL_QSPI_STATE_READY)
01283   {
01284     /* Clear the error code */
01285     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01286
01287     if(pData != NULL )
01288     {
01289
01290       /* Update state */
01291       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01292
01293       /* Clear interrupt */
01294       __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01295
01296       /* Configure counters and size of the handle */
01297       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01298       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01299       hqspi->pTxBuffPtr = pData;
01300
01301       /* Configure QSPI: CCR register with functional mode as indirect write */
01302       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01303
01304       /* Set the QSPI MDMA transfer complete callback */
01305       hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
01306
01307       /* Set the MDMA error callback */
01308       hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
01309
01310       /* Clear the MDMA abort callback */
01311       hqspi->hmdma->XferAbortCallback = NULL;
01312
01313       /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
01314       MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
01315
01316       /* Update MDMA configuration with the correct SourceInc field for Write operation */
01317       if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
01318       {
01319         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
01320       }
01321       else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
01322       {
01323         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
01324       }
01325       else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
01326       {
01327         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
01328       }
01329       else
01330       {
01331         /* in case of incorrect source data size */
01332         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01333         status = HAL_ERROR;
01334       }
01335
01336       /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
01337       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
01338
01339       /* Enable the QSPI transmit MDMA */
01340       if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
01341       {
01342         /* Process unlocked */
01343         __HAL_UNLOCK(hqspi);
01344
01345         /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
01346       }
01347     }
01348     else
01349     {
01350       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01351       status = HAL_ERROR;
01352
01353       /* Process unlocked */
01354       __HAL_UNLOCK(hqspi);
01355     }
01356   }
01357   else
01358   {
01359     status = HAL_BUSY;
01360
01361     /* Process unlocked */
01362     __HAL_UNLOCK(hqspi);
01363   }
01364
01365   return status;
01366 }
01367
01368 /**
01369   * @brief  Receive an amount of data in non-blocking mode with DMA.
01370   * @param  hqspi: QSPI handle
01371   * @param  pData: pointer to data buffer.
01372   * @note   This function is used only in Indirect Read Mode
01373   * @retval HAL status
01374   */
01375 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01376 {
01377   HAL_StatusTypeDef status = HAL_OK;
01378   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01379
01380   /* Process locked */
01381   __HAL_LOCK(hqspi);
01382
01383   if(hqspi->State == HAL_QSPI_STATE_READY)
01384   {
01385     /* Clear the error code */
01386     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01387
01388     if(pData != NULL )
01389     {
01390
01391       /* Update state */
01392       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01393
01394       /* Clear interrupt */
01395       __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01396
01397       /* Configure counters and size of the handle */
01398       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01399       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01400       hqspi->pRxBuffPtr = pData;
01401
01402       /* Set the QSPI DMA transfer complete callback */
01403       hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
01404
01405       /* Set the MDMA error callback */
01406       hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
01407
01408       /* Clear the MDMA abort callback */
01409       hqspi->hmdma->XferAbortCallback = NULL;
01410
01411
01412       /* QSPI need to be configured to indirect mode before starting
01413          the MDMA to avoid primatury triggering for the MDMA transfert */
01414       /* Configure QSPI: CCR register with functional as indirect read */
01415       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01416
01417       /* Start the transfer by re-writing the address in AR register */
01418       WRITE_REG(hqspi->Instance->AR, addr_reg);
01419
01420       /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
01421       MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
01422
01423       /* Update MDMA configuration with the correct DestinationInc field for read operation */
01424       if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
01425       {
01426         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
01427       }
01428       else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
01429       {
01430         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
01431       }
01432       else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
01433       {
01434         MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
01435       }
01436       else
01437       {
01438        /* in case of incorrect destination data size */
01439         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01440         status = HAL_ERROR;
01441       }
01442
01443       /* Enable the MDMA */
01444       if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
01445       {
01446         /* Process unlocked */
01447         __HAL_UNLOCK(hqspi);
01448
01449         /* Enable the QSPI transfer error Interrupt */
01450         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01451
01452         /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
01453       }
01454     }
01455     else
01456     {
01457       status = HAL_ERROR;
01458
01459       /* Process unlocked */
01460       __HAL_UNLOCK(hqspi);
01461     }
01462   }
01463   else
01464   {
01465     status = HAL_BUSY;
01466
01467     /* Process unlocked */
01468     __HAL_UNLOCK(hqspi);
01469   }
01470
01471   return status;
01472 }
01473
01474 /**
01475   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01476   * @param  hqspi: QSPI handle
01477   * @param  cmd: structure that contains the command configuration information.
01478   * @param  cfg: structure that contains the polling configuration information.
01479   * @param  Timeout : Timeout duration
01480   * @note   This function is used only in Automatic Polling Mode
01481   * @retval HAL status
01482   */
01483 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01484 {
01485   HAL_StatusTypeDef status;
01486   uint32_t tickstart = HAL_GetTick();
01487
01488   /* Check the parameters */
01489   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01490   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01491   {
01492     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01493   }
01494
01495   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01496   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01497   {
01498     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01499   }
01500
01501   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01502   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01503   {
01504     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01505   }
01506
01507   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01508   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01509
01510   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01511   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01512   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01513
01514   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01515   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01516   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01517
01518   /* Process locked */
01519   __HAL_LOCK(hqspi);
01520
01521   if(hqspi->State == HAL_QSPI_STATE_READY)
01522   {
01523     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01524
01525     /* Update state */
01526     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01527
01528     /* Wait till BUSY flag reset */
01529     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01530
01531     if (status == HAL_OK)
01532     {
01533       /* Configure QSPI: PSMAR register with the status match value */
01534       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01535
01536       /* Configure QSPI: PSMKR register with the status mask value */
01537       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01538
01539       /* Configure QSPI: PIR register with the interval value */
01540       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01541
01542       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01543       (otherwise there will be an infinite loop in blocking mode) */
01544       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01545                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01546
01547       /* Call the configuration function */
01548       cmd->NbData = cfg->StatusBytesSize;
01549       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01550
01551       /* Wait until SM flag is set to go back in idle state */
01552       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
01553
01554       if (status == HAL_OK)
01555       {
01556         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01557
01558         /* Update state */
01559         hqspi->State = HAL_QSPI_STATE_READY;
01560       }
01561     }
01562   }
01563   else
01564   {
01565     status = HAL_BUSY;
01566   }
01567
01568   /* Process unlocked */
01569   __HAL_UNLOCK(hqspi);
01570
01571   /* Return function status */
01572   return status;
01573 }
01574
01575 /**
01576   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01577   * @param  hqspi: QSPI handle
01578   * @param  cmd: structure that contains the command configuration information.
01579   * @param  cfg: structure that contains the polling configuration information.
01580   * @note   This function is used only in Automatic Polling Mode
01581   * @retval HAL status
01582   */
01583 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01584 {
01585   HAL_StatusTypeDef status;
01586   uint32_t tickstart = HAL_GetTick();
01587
01588   /* Check the parameters */
01589   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01590   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01591   {
01592     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01593   }
01594
01595   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01596   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01597   {
01598     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01599   }
01600
01601   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01602   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01603   {
01604     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01605   }
01606
01607   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01608   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01609
01610   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01611   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01612   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01613
01614   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01615   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01616   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01617   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01618
01619   /* Process locked */
01620   __HAL_LOCK(hqspi);
01621
01622   if(hqspi->State == HAL_QSPI_STATE_READY)
01623   {
01624     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01625
01626     /* Update state */
01627     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01628
01629     /* Wait till BUSY flag reset */
01630     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01631
01632     if (status == HAL_OK)
01633     {
01634       /* Configure QSPI: PSMAR register with the status match value */
01635       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01636
01637       /* Configure QSPI: PSMKR register with the status mask value */
01638       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01639
01640       /* Configure QSPI: PIR register with the interval value */
01641       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01642
01643       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01644       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01645                (cfg->MatchMode | cfg->AutomaticStop));
01646
01647       /* Clear interrupt */
01648       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01649
01650       /* Call the configuration function */
01651       cmd->NbData = cfg->StatusBytesSize;
01652       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01653
01654       /* Process unlocked */
01655       __HAL_UNLOCK(hqspi);
01656
01657       /* Enable the QSPI Transfer Error and status match Interrupt */
01658       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01659
01660     }
01661     else
01662     {
01663       /* Process unlocked */
01664       __HAL_UNLOCK(hqspi);
01665     }
01666   }
01667   else
01668   {
01669     status = HAL_BUSY;
01670
01671     /* Process unlocked */
01672     __HAL_UNLOCK(hqspi);
01673   }
01674
01675   /* Return function status */
01676   return status;
01677 }
01678
01679 /**
01680   * @brief  Configure the Memory Mapped mode.
01681   * @param  hqspi: QSPI handle
01682   * @param  cmd: structure that contains the command configuration information.
01683   * @param  cfg: structure that contains the memory mapped configuration information.
01684   * @note   This function is used only in Memory mapped Mode
01685   * @retval HAL status
01686   */
01687 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01688 {
01689   HAL_StatusTypeDef status;
01690   uint32_t tickstart = HAL_GetTick();
01691
01692   /* Check the parameters */
01693   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01694   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01695   {
01696   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01697   }
01698
01699   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01700   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01701   {
01702     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01703   }
01704
01705   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01706   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01707   {
01708     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01709   }
01710
01711   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01712   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01713
01714   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01715   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01716   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01717
01718   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01719
01720   /* Process locked */
01721   __HAL_LOCK(hqspi);
01722
01723   if(hqspi->State == HAL_QSPI_STATE_READY)
01724   {
01725     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01726
01727     /* Update state */
01728     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01729
01730     /* Wait till BUSY flag reset */
01731     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01732
01733     if (status == HAL_OK)
01734     {
01735       /* Configure QSPI: CR register with timeout counter enable */
01736       MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01737
01738       if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01739       {
01740         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01741
01742         /* Configure QSPI: LPTR register with the low-power timeout value */
01743         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01744
01745         /* Clear interrupt */
01746         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
01747
01748         /* Enable the QSPI TimeOut Interrupt */
01749         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01750       }
01751
01752       /* Call the configuration function */
01753       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01754     }
01755   }
01756   else
01757   {
01758     status = HAL_BUSY;
01759   }
01760
01761   /* Process unlocked */
01762   __HAL_UNLOCK(hqspi);
01763
01764   /* Return function status */
01765   return status;
01766 }
01767
01768 /**
01769   * @brief  Transfer Error callback.
01770   * @param  hqspi: QSPI handle
01771   * @retval None
01772   */
01773 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01774 {
01775   /* Prevent unused argument(s) compilation warning */
01776   UNUSED(hqspi);
01777
01778   /* NOTE : This function should not be modified, when the callback is needed,
01779             the HAL_QSPI_ErrorCallback could be implemented in the user file
01780    */
01781 }
01782
01783 /**
01784   * @brief  Abort completed callback.
01785   * @param  hqspi: QSPI handle
01786   * @retval None
01787   */
01788 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
01789 {
01790   /* Prevent unused argument(s) compilation warning */
01791   UNUSED(hqspi);
01792
01793   /* NOTE: This function should not be modified, when the callback is needed,
01794            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
01795    */
01796 }
01797
01798 /**
01799   * @brief  Command completed callback.
01800   * @param  hqspi: QSPI handle
01801   * @retval None
01802   */
01803 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01804 {
01805   /* Prevent unused argument(s) compilation warning */
01806   UNUSED(hqspi);
01807
01808   /* NOTE: This function should not be modified, when the callback is needed,
01809            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01810    */
01811 }
01812
01813 /**
01814   * @brief  Rx Transfer completed callback.
01815   * @param  hqspi: QSPI handle
01816   * @retval None
01817   */
01818 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01819 {
01820   /* Prevent unused argument(s) compilation warning */
01821   UNUSED(hqspi);
01822
01823   /* NOTE: This function should not be modified, when the callback is needed,
01824            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01825    */
01826 }
01827
01828 /**
01829   * @brief  Tx Transfer completed callback.
01830   * @param  hqspi: QSPI handle
01831   * @retval None
01832   */
01833  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01834 {
01835   /* Prevent unused argument(s) compilation warning */
01836   UNUSED(hqspi);
01837
01838   /* NOTE: This function should not be modified, when the callback is needed,
01839            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01840    */
01841 }
01842
01843
01844 /**
01845   * @brief  FIFO Threshold callback.
01846   * @param  hqspi: QSPI handle
01847   * @retval None
01848   */
01849 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01850 {
01851   /* Prevent unused argument(s) compilation warning */
01852   UNUSED(hqspi);
01853
01854   /* NOTE : This function should not be modified, when the callback is needed,
01855             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01856    */
01857 }
01858
01859 /**
01860   * @brief  Status Match callback.
01861   * @param  hqspi: QSPI handle
01862   * @retval None
01863   */
01864 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01865 {
01866   /* Prevent unused argument(s) compilation warning */
01867   UNUSED(hqspi);
01868
01869   /* NOTE : This function should not be modified, when the callback is needed,
01870             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01871    */
01872 }
01873
01874 /**
01875   * @brief  Timeout callback.
01876   * @param  hqspi: QSPI handle
01877   * @retval None
01878   */
01879 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01880 {
01881   /* Prevent unused argument(s) compilation warning */
01882   UNUSED(hqspi);
01883
01884   /* NOTE : This function should not be modified, when the callback is needed,
01885             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01886    */
01887 }
01888 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
01889 /**
01890   * @brief  Register a User QSPI Callback
01891   *         To be used instead of the weak (surcharged) predefined callback
01892   * @param hqspi : QSPI handle
01893   * @param CallbackId : ID of the callback to be registered
01894   *        This parameter can be one of the following values:
01895   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
01896   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
01897   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
01898   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
01899   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
01900   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
01901   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
01902   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
01903   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
01904   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
01905   * @param pCallback : pointer to the Callback function
01906   * @retval status
01907   */
01908 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
01909 {
01910   HAL_StatusTypeDef status = HAL_OK;
01911
01912   if(pCallback == NULL)
01913   {
01914     /* Update the error code */
01915     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
01916     return HAL_ERROR;
01917   }
01918
01919   /* Process locked */
01920   __HAL_LOCK(hqspi);
01921
01922   if(hqspi->State == HAL_QSPI_STATE_READY)
01923   {
01924     switch (CallbackId)
01925     {
01926     case  HAL_QSPI_ERROR_CB_ID :
01927       hqspi->ErrorCallback = pCallback;
01928       break;
01929     case HAL_QSPI_ABORT_CB_ID :
01930       hqspi->AbortCpltCallback = pCallback;
01931       break;
01932     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
01933       hqspi->FifoThresholdCallback = pCallback;
01934       break;
01935     case HAL_QSPI_CMD_CPLT_CB_ID :
01936       hqspi->CmdCpltCallback = pCallback;
01937       break;
01938     case HAL_QSPI_RX_CPLT_CB_ID :
01939       hqspi->RxCpltCallback = pCallback;
01940       break;
01941     case HAL_QSPI_TX_CPLT_CB_ID :
01942       hqspi->TxCpltCallback = pCallback;
01943       break;
01944     case HAL_QSPI_STATUS_MATCH_CB_ID :
01945       hqspi->StatusMatchCallback = pCallback;
01946       break;
01947     case HAL_QSPI_TIMEOUT_CB_ID :
01948       hqspi->TimeOutCallback = pCallback;
01949       break;
01950     case HAL_QSPI_MSP_INIT_CB_ID :
01951       hqspi->MspInitCallback = pCallback;
01952       break;
01953     case HAL_QSPI_MSP_DEINIT_CB_ID :
01954       hqspi->MspDeInitCallback = pCallback;
01955       break;
01956     default :
01957       /* Update the error code */
01958       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
01959       /* update return status */
01960       status =  HAL_ERROR;
01961       break;
01962     }
01963   }
01964   else if (hqspi->State == HAL_QSPI_STATE_RESET)
01965   {
01966     switch (CallbackId)
01967     {
01968     case HAL_QSPI_MSP_INIT_CB_ID :
01969       hqspi->MspInitCallback = pCallback;
01970       break;
01971     case HAL_QSPI_MSP_DEINIT_CB_ID :
01972       hqspi->MspDeInitCallback = pCallback;
01973       break;
01974     default :
01975       /* Update the error code */
01976       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
01977       /* update return status */
01978       status =  HAL_ERROR;
01979       break;
01980     }
01981   }
01982   else
01983   {
01984     /* Update the error code */
01985     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
01986     /* update return status */
01987     status =  HAL_ERROR;
01988   }
01989
01990   /* Release Lock */
01991   __HAL_UNLOCK(hqspi);
01992   return status;
01993 }
01994
01995 /**
01996   * @brief  Unregister a User QSPI Callback
01997   *         QSPI Callback is redirected to the weak (surcharged) predefined callback
01998   * @param hqspi : QSPI handle
01999   * @param CallbackId : ID of the callback to be unregistered
02000   *        This parameter can be one of the following values:
02001   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
02002   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
02003   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
02004   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
02005   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
02006   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
02007   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
02008   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
02009   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
02010   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
02011   * @retval status
02012   */
02013 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
02014 {
02015   HAL_StatusTypeDef status = HAL_OK;
02016
02017   /* Process locked */
02018   __HAL_LOCK(hqspi);
02019
02020   if(hqspi->State == HAL_QSPI_STATE_READY)
02021   {
02022     switch (CallbackId)
02023     {
02024     case  HAL_QSPI_ERROR_CB_ID :
02025       hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
02026       break;
02027     case HAL_QSPI_ABORT_CB_ID :
02028       hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
02029       break;
02030     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
02031       hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
02032       break;
02033     case HAL_QSPI_CMD_CPLT_CB_ID :
02034       hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
02035       break;
02036     case HAL_QSPI_RX_CPLT_CB_ID :
02037       hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
02038       break;
02039     case HAL_QSPI_TX_CPLT_CB_ID :
02040       hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
02041       break;
02042     case HAL_QSPI_STATUS_MATCH_CB_ID :
02043       hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
02044       break;
02045     case HAL_QSPI_TIMEOUT_CB_ID :
02046       hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
02047       break;
02048     case HAL_QSPI_MSP_INIT_CB_ID :
02049       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02050       break;
02051     case HAL_QSPI_MSP_DEINIT_CB_ID :
02052       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02053       break;
02054     default :
02055       /* Update the error code */
02056       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02057       /* update return status */
02058       status =  HAL_ERROR;
02059       break;
02060     }
02061   }
02062   else if (hqspi->State == HAL_QSPI_STATE_RESET)
02063   {
02064     switch (CallbackId)
02065     {
02066     case HAL_QSPI_MSP_INIT_CB_ID :
02067       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02068       break;
02069     case HAL_QSPI_MSP_DEINIT_CB_ID :
02070       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02071       break;
02072     default :
02073       /* Update the error code */
02074       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02075       /* update return status */
02076       status =  HAL_ERROR;
02077       break;
02078     }
02079   }
02080   else
02081   {
02082     /* Update the error code */
02083     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02084     /* update return status */
02085     status =  HAL_ERROR;
02086   }
02087
02088   /* Release Lock */
02089   __HAL_UNLOCK(hqspi);
02090   return status;
02091 }
02092 #endif
02093
02094 /**
02095   * @}
02096   */
02097
02098 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
02099   *  @brief   QSPI control and State functions
02100   *
02101 @verbatim
02102  ===============================================================================
02103                   ##### Peripheral Control and State functions #####
02104  ===============================================================================
02105     [..]
02106     This subsection provides a set of functions allowing to :
02107       (+) Check in run-time the state of the driver.
02108       (+) Check the error code set during last operation.
02109       (+) Abort any operation.
02110
02111
02112 @endverbatim
02113   * @{
02114   */
02115
02116 /**
02117   * @brief  Return the QSPI handle state.
02118   * @param  hqspi: QSPI handle
02119   * @retval HAL state
02120   */
02121 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
02122 {
02123   /* Return QSPI handle state */
02124   return hqspi->State;
02125 }
02126
02127 /**
02128 * @brief  Return the QSPI error code.
02129 * @param  hqspi: QSPI handle
02130 * @retval QSPI Error Code
02131 */
02132 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
02133 {
02134   return hqspi->ErrorCode;
02135 }
02136
02137 /**
02138 * @brief  Abort the current transmission.
02139 * @param  hqspi: QSPI handle
02140 * @retval HAL status
02141 */
02142 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
02143 {
02144   HAL_StatusTypeDef status = HAL_OK;
02145   uint32_t tickstart = HAL_GetTick();
02146
02147   /* Check if the state is in one of the busy states */
02148   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02149   {
02150     /* Process unlocked */
02151     __HAL_UNLOCK(hqspi);
02152
02153     if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
02154     {
02155       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02156       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02157
02158       /* Abort MDMA */
02159       status = HAL_MDMA_Abort(hqspi->hmdma);
02160       if(status != HAL_OK)
02161       {
02162         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
02163       }
02164     }
02165
02166     /* Configure QSPI: CR register with Abort request */
02167     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02168
02169     /* Wait until TC flag is set to go back in idle state */
02170     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
02171
02172     if(status == HAL_OK)
02173     {
02174       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02175
02176       /* Wait until BUSY flag is reset */
02177       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
02178     }
02179
02180     if (status == HAL_OK)
02181     {
02182       /* Update state */
02183       hqspi->State = HAL_QSPI_STATE_READY;
02184     }
02185   }
02186
02187   return status;
02188 }
02189
02190 /**
02191 * @brief  Abort the current transmission (non-blocking function)
02192 * @param  hqspi: QSPI handle
02193 * @retval HAL status
02194 */
02195 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
02196 {
02197   HAL_StatusTypeDef status = HAL_OK;
02198
02199   /* Check if the state is in one of the busy states */
02200   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02201   {
02202     /* Process unlocked */
02203     __HAL_UNLOCK(hqspi);
02204
02205     /* Update QSPI state */
02206     hqspi->State = HAL_QSPI_STATE_ABORT;
02207
02208     /* Disable all interrupts */
02209     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
02210
02211     if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
02212     {
02213       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02214       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02215
02216       /* Abort MDMA channel */
02217       hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
02218       if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
02219       {
02220         /* Set error code to DMA */
02221         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
02222
02223         status = HAL_ERROR;
02224       }
02225     }
02226     else
02227     {
02228       /* Clear interrupt */
02229       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02230
02231       /* Enable the QSPI Transfer Complete Interrupt */
02232       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02233
02234       /* Configure QSPI: CR register with Abort request */
02235       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02236     }
02237   }
02238   return status;
02239 }
02240
02241 /** @brief Set QSPI timeout.
02242   * @param  hqspi: QSPI handle.
02243   * @param  Timeout: Timeout for the QSPI memory access.
02244   * @retval None
02245   */
02246 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
02247 {
02248   hqspi->Timeout = Timeout;
02249 }
02250
02251 /** @brief Set QSPI Fifo threshold.
02252   * @param  hqspi: QSPI handle.
02253   * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
02254   * @retval HAL status
02255   */
02256 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
02257 {
02258   HAL_StatusTypeDef status = HAL_OK;
02259
02260   /* Process locked */
02261   __HAL_LOCK(hqspi);
02262
02263   if(hqspi->State == HAL_QSPI_STATE_READY)
02264   {
02265     /* Synchronize init structure with new FIFO threshold value */
02266     hqspi->Init.FifoThreshold = Threshold;
02267
02268     /* Configure QSPI FIFO Threshold */
02269     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
02270                ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
02271   }
02272   else
02273   {
02274     status = HAL_BUSY;
02275   }
02276
02277   /* Process unlocked */
02278   __HAL_UNLOCK(hqspi);
02279
02280   /* Return function status */
02281   return status;
02282 }
02283
02284 /** @brief Get QSPI Fifo threshold.
02285   * @param  hqspi: QSPI handle.
02286   * @retval Fifo threshold (value between 1 and 16)
02287   */
02288 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
02289 {
02290   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
02291 }
02292
02293 /** @brief  Set FlashID.
02294   * @param  hqspi : QSPI handle.
02295   * @param  FlashID : Index of the flash memory to be accessed.
02296   *                   This parameter can be a value of @ref QSPI_Flash_Select.
02297   * @note   The FlashID is ignored when dual flash mode is enabled.
02298   * @retval HAL status
02299   */
02300 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
02301 {
02302   HAL_StatusTypeDef status = HAL_OK;
02303
02304   /* Check the parameter */
02305   assert_param(IS_QSPI_FLASH_ID(FlashID));
02306
02307   /* Process locked */
02308   __HAL_LOCK(hqspi);
02309
02310   if(hqspi->State == HAL_QSPI_STATE_READY)
02311   {
02312     /* Synchronize init structure with new FlashID value */
02313     hqspi->Init.FlashID = FlashID;
02314
02315     /* Configure QSPI FlashID */
02316     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
02317   }
02318   else
02319   {
02320     status = HAL_BUSY;
02321   }
02322
02323   /* Process unlocked */
02324   __HAL_UNLOCK(hqspi);
02325
02326   /* Return function status */
02327   return status;
02328 }
02329
02330 /**
02331   * @}
02332   */
02333
02334 /**
02335   * @brief  DMA QSPI receive process complete callback.
02336   * @param  hmdma: MDMA handle
02337   * @retval None
02338   */
02339 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
02340 {
02341   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
02342   hqspi->RxXferCount = 0U;
02343
02344   /* Enable the QSPI transfer complete Interrupt */
02345   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02346 }
02347
02348 /**
02349   * @brief  DMA QSPI transmit process complete callback.
02350   * @param  hmdma: MDMA handle
02351   * @retval None
02352   */
02353 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
02354 {
02355   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
02356   hqspi->TxXferCount = 0U;
02357
02358   /* Enable the QSPI transfer complete Interrupt */
02359   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02360 }
02361
02362 /**
02363   * @brief  DMA QSPI communication error callback.
02364   * @param  hmdma: MDMA handle
02365   * @retval None
02366   */
02367 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
02368 {
02369   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
02370
02371   hqspi->RxXferCount = 0U;
02372   hqspi->TxXferCount = 0U;
02373   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
02374
02375   /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
02376   CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02377
02378   /* Abort the QSPI */
02379   (void)HAL_QSPI_Abort_IT(hqspi);
02380
02381 }
02382
02383 /**
02384   * @brief  MDMA QSPI abort complete callback.
02385   * @param  hmdma: MDMA handle
02386   * @retval None
02387   */
02388 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
02389 {
02390   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
02391
02392   hqspi->RxXferCount = 0U;
02393   hqspi->TxXferCount = 0U;
02394
02395   if(hqspi->State == HAL_QSPI_STATE_ABORT)
02396   {
02397     /* MDMA Abort called by QSPI abort */
02398     /* Clear interrupt */
02399     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02400
02401     /* Enable the QSPI Transfer Complete Interrupt */
02402     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02403
02404     /* Configure QSPI: CR register with Abort request */
02405     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02406   }
02407   else
02408   {
02409     /* MDMA Abort called due to a transfer error interrupt */
02410     /* Change state of QSPI */
02411     hqspi->State = HAL_QSPI_STATE_READY;
02412
02413     /* Error callback */
02414 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02415     hqspi->ErrorCallback(hqspi);
02416 #else
02417     HAL_QSPI_ErrorCallback(hqspi);
02418 #endif
02419   }
02420 }
02421 /**
02422   * @brief  Wait for a flag state until timeout.
02423   * @param  hqspi: QSPI handle
02424   * @param  Flag: Flag checked
02425   * @param  State: Value of the flag expected
02426   * @param  Tickstart: Tick start value
02427   * @param  Timeout: Duration of the timeout
02428   * @retval HAL status
02429   */
02430 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
02431                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
02432 {
02433   /* Wait until flag is in expected state */
02434   while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
02435   {
02436     /* Check for the Timeout */
02437     if (Timeout != HAL_MAX_DELAY)
02438     {
02439       if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02440       {
02441         hqspi->State     = HAL_QSPI_STATE_ERROR;
02442         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
02443
02444         return HAL_ERROR;
02445       }
02446     }
02447   }
02448   return HAL_OK;
02449 }
02450
02451 /**
02452   * @brief  Configure the communication registers.
02453   * @param  hqspi: QSPI handle
02454   * @param  cmd: structure that contains the command configuration information
02455   * @param  FunctionalMode: functional mode to configured
02456   *           This parameter can be one of the following values:
02457   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
02458   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
02459   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
02460   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
02461   * @retval None
02462   */
02463 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
02464 {
02465   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
02466
02467   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
02468   {
02469     /* Configure QSPI: DLR register with the number of data to read or write */
02470     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
02471   }
02472
02473   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
02474   {
02475     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02476     {
02477       /* Configure QSPI: ABR register with alternate bytes value */
02478       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02479
02480       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02481       {
02482         /*---- Command with instruction, address and alternate bytes ----*/
02483         /* Configure QSPI: CCR register with all communications parameters */
02484         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02485                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02486                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02487                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
02488                                          cmd->Instruction | FunctionalMode));
02489
02490         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02491         {
02492           /* Configure QSPI: AR register with address value */
02493           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02494         }
02495       }
02496       else
02497       {
02498         /*---- Command with instruction and alternate bytes ----*/
02499         /* Configure QSPI: CCR register with all communications parameters */
02500         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02501                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02502                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02503                                          cmd->AddressMode | cmd->InstructionMode |
02504                                          cmd->Instruction | FunctionalMode));
02505       }
02506     }
02507     else
02508     {
02509       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02510       {
02511         /*---- Command with instruction and address ----*/
02512         /* Configure QSPI: CCR register with all communications parameters */
02513         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02514                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02515                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
02516                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02517
02518         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02519         {
02520           /* Configure QSPI: AR register with address value */
02521           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02522         }
02523       }
02524       else
02525       {
02526         /*---- Command with only instruction ----*/
02527         /* Configure QSPI: CCR register with all communications parameters */
02528         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02529                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02530                                          cmd->AlternateByteMode | cmd->AddressMode |
02531                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02532       }
02533     }
02534   }
02535   else
02536   {
02537     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02538     {
02539       /* Configure QSPI: ABR register with alternate bytes value */
02540       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02541
02542       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02543       {
02544         /*---- Command with address and alternate bytes ----*/
02545         /* Configure QSPI: CCR register with all communications parameters */
02546         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02547                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02548                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02549                                          cmd->AddressSize | cmd->AddressMode |
02550                                          cmd->InstructionMode | FunctionalMode));
02551
02552         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02553         {
02554           /* Configure QSPI: AR register with address value */
02555           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02556         }
02557       }
02558       else
02559       {
02560         /*---- Command with only alternate bytes ----*/
02561         /* Configure QSPI: CCR register with all communications parameters */
02562         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02563                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02564                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02565                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02566       }
02567     }
02568     else
02569     {
02570       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02571       {
02572         /*---- Command with only address ----*/
02573         /* Configure QSPI: CCR register with all communications parameters */
02574         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02575                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02576                                          cmd->AlternateByteMode | cmd->AddressSize |
02577                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02578
02579         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02580         {
02581           /* Configure QSPI: AR register with address value */
02582           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02583         }
02584       }
02585       else
02586       {
02587         /*---- Command with only data phase ----*/
02588         if (cmd->DataMode != QSPI_DATA_NONE)
02589         {
02590           /* Configure QSPI: CCR register with all communications parameters */
02591           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02592                                            cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02593                                            cmd->AlternateByteMode | cmd->AddressMode |
02594                                            cmd->InstructionMode | FunctionalMode));
02595         }
02596       }
02597     }
02598   }
02599 }
02600
02601 /**
02602   * @}
02603   */
02604
02605 /**
02606   * @}
02607   */
02608
02609 /**
02610   * @}
02611   */
02612
02613 #endif /* QUADSPI */
02614
02615 #endif /* HAL_QSPI_MODULE_ENABLED */
02616
02617 /**
02618   * @}
02619   */
02620
02621 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_qspi.h Source File

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stm32h7xx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of QSPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_QSPI_H
00022 #define STM32H7xx_HAL_QSPI_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 #if defined(QUADSPI)
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32h7xx_hal_def.h"
00032
00033 /** @addtogroup STM32H7xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup QSPI
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  QSPI Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00053                                   This parameter can be a number between 0 and 255 */
00054
00055   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00056                                   This parameter can be a value between 1 and 32 */
00057
00058   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00059                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00060                                   This parameter can be a value of @ref QSPI_SampleShifting */
00061
00062   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00063                                   required to address the flash memory. The flash capacity can be up to 4GB
00064                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00065                                   memory-mapped mode is limited to 256MB
00066                                   This parameter can be a number between 0 and 31 */
00067
00068   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00069                                   of clock cycles which the chip select must remain high between commands.
00070                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00071
00072   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00073                                   This parameter can be a value of @ref QSPI_ClockMode */
00074
00075   uint32_t FlashID;            /* Specifies the Flash which will be used,
00076                                   This parameter can be a value of @ref QSPI_Flash_Select */
00077
00078   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00079                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00080 }QSPI_InitTypeDef;
00081
00082 /**
00083   * @brief HAL QSPI State structures definition
00084   */
00085 typedef enum
00086 {
00087   HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
00088   HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
00089   HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
00090   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
00091   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
00092   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
00093   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
00094   HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
00095   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
00096 }HAL_QSPI_StateTypeDef;
00097
00098 /**
00099   * @brief  QSPI Handle Structure definition
00100   */
00101 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00102 typedef struct __QSPI_HandleTypeDef
00103 #else
00104 typedef struct
00105 #endif/* USE_HAL_QSPI_REGISTER_CALLBACKS  */
00106 {
00107   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00108   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00109   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00110   __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
00111   __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00112   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00113   __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
00114   __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00115   MDMA_HandleTypeDef         *hmdma;           /* QSPI Rx/Tx MDMA Handle parameters  */
00116   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00117   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00118   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00119   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00120 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00121   void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
00122   void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00123   void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
00124   void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00125   void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00126   void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00127   void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
00128   void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00129
00130   void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00131   void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00132 #endif
00133 }QSPI_HandleTypeDef;
00134
00135 /**
00136   * @brief  QSPI Command structure definition
00137   */
00138 typedef struct
00139 {
00140   uint32_t Instruction;        /* Specifies the Instruction to be sent
00141                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00142   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00143                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00144   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00145                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00146   uint32_t AddressSize;        /* Specifies the Address Size
00147                                   This parameter can be a value of @ref QSPI_AddressSize */
00148   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00149                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00150   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00151                                   This parameter can be a number between 0 and 31 */
00152   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00153                                   This parameter can be a value of @ref QSPI_InstructionMode */
00154   uint32_t AddressMode;        /* Specifies the Address Mode
00155                                   This parameter can be a value of @ref QSPI_AddressMode */
00156   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00157                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00158   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00159                                   This parameter can be a value of @ref QSPI_DataMode */
00160   uint32_t NbData;             /* Specifies the number of data to transfer.
00161                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00162                                   until end of memory)*/
00163   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00164                                   This parameter can be a value of @ref QSPI_DdrMode */
00165   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
00166                                   system clock in DDR mode.
00167                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00168   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00169                                   This parameter can be a value of @ref QSPI_SIOOMode */
00170 }QSPI_CommandTypeDef;
00171
00172 /**
00173   * @brief  QSPI Auto Polling mode configuration structure definition
00174   */
00175 typedef struct
00176 {
00177   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00178                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00179   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00180                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00181   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00182                                   This parameter can be any value between 0 and 0xFFFF */
00183   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00184                                   This parameter can be any value between 1 and 4 */
00185   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00186                                   This parameter can be a value of @ref QSPI_MatchMode */
00187   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00188                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00189 }QSPI_AutoPollingTypeDef;
00190
00191 /**
00192   * @brief  QSPI Memory Mapped mode configuration structure definition
00193   */
00194 typedef struct
00195 {
00196   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00197                                   This parameter can be any value between 0 and 0xFFFF */
00198   uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select.
00199                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00200 }QSPI_MemoryMappedTypeDef;
00201
00202 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00203 /**
00204   * @brief  HAL QSPI Callback ID enumeration definition
00205   */
00206 typedef enum
00207 {
00208   HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
00209   HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
00210   HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
00211   HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
00212   HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
00213   HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
00214   HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
00215   HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
00216
00217   HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
00218   HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
00219 }HAL_QSPI_CallbackIDTypeDef;
00220
00221 /**
00222   * @brief  HAL QSPI Callback pointer definition
00223   */
00224 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
00225 #endif
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported constants --------------------------------------------------------*/
00231 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00232   * @{
00233   */
00234
00235 /** @defgroup QSPI_ErrorCode QSPI Error Code
00236   * @{
00237   */
00238 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error           */
00239 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */
00240 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */
00241 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */
00242 #define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008U) /*!< Invalid parameters error */
00243 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00244 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
00245 #endif
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00251   * @{
00252   */
00253 #define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000U)        /*!<No clock cycle shift to sample data*/
00254 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00260   * @{
00261   */
00262 #define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000U)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00263 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00264 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00265 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00266 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00267 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00268 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00269 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00275   * @{
00276   */
00277 #define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
00278 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00284   * @{
00285   */
00286 #define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
00287 #define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
00288 /**
00289   * @}
00290   */
00291
00292   /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
00293   * @{
00294   */
00295 #define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
00296 #define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup QSPI_AddressSize QSPI Address Size
00302   * @{
00303   */
00304 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
00305 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00306 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00307 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00313   * @{
00314   */
00315 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
00316 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00317 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00318 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00324 * @{
00325 */
00326 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
00327 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00328 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00329 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup QSPI_AddressMode QSPI Address Mode
00335 * @{
00336 */
00337 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
00338 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00339 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00340 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00346 * @{
00347 */
00348 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
00349 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00350 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00351 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup QSPI_DataMode QSPI Data Mode
00357   * @{
00358   */
00359 #define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
00360 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00361 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00362 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00368   * @{
00369   */
00370 #define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
00371 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
00377   * @{
00378   */
00379 #define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
00380 #define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00386   * @{
00387   */
00388 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
00389 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup QSPI_MatchMode QSPI Match Mode
00395   * @{
00396   */
00397 #define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
00398 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00404   * @{
00405   */
00406 #define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00407 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00413   * @{
00414   */
00415 #define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
00416 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup QSPI_Flags QSPI Flags
00422   * @{
00423   */
00424 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00425 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00426 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00427 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00428 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00429 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup QSPI_Interrupts QSPI Interrupts
00435   * @{
00436   */
00437 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00438 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00439 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00440 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00441 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00447   * @brief QSPI Timeout definition
00448   * @{
00449   */
00450 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
00451 /**
00452   * @}
00453   */
00454
00455 /**
00456   * @}
00457   */
00458
00459 /* Exported macros -----------------------------------------------------------*/
00460 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00461   * @{
00462   */
00463 /** @brief Reset QSPI handle state.
00464   * @param  __HANDLE__: QSPI handle.
00465   * @retval None
00466   */
00467 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00468 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00469                                                                   (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
00470                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
00471                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
00472                                                                } while(0)
00473 #else
00474 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00475 #endif
00476
00477 /** @brief  Enable the QSPI peripheral.
00478   * @param  __HANDLE__: specifies the QSPI Handle.
00479   * @retval None
00480   */
00481 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00482
00483 /** @brief  Disable the QSPI peripheral.
00484   * @param  __HANDLE__: specifies the QSPI Handle.
00485   * @retval None
00486   */
00487 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00488
00489 /** @brief  Enable the specified QSPI interrupt.
00490   * @param  __HANDLE__: specifies the QSPI Handle.
00491   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00492   *          This parameter can be one of the following values:
00493   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00494   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00495   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00496   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00497   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00498   * @retval None
00499   */
00500 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00501
00502
00503 /** @brief  Disable the specified QSPI interrupt.
00504   * @param  __HANDLE__: specifies the QSPI Handle.
00505   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00506   *          This parameter can be one of the following values:
00507   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00508   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00509   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00510   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00511   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00512   * @retval None
00513   */
00514 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00515
00516 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00517   * @param  __HANDLE__: specifies the QSPI Handle.
00518   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00519   *          This parameter can be one of the following values:
00520   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00521   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00522   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00523   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00524   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00525   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00526   */
00527 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00528
00529 /**
00530   * @brief  Check whether the selected QSPI flag is set or not.
00531   * @param  __HANDLE__: specifies the QSPI Handle.
00532   * @param  __FLAG__: specifies the QSPI flag to check.
00533   *          This parameter can be one of the following values:
00534   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00535   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00536   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00537   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00538   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00539   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00540   * @retval None
00541   */
00542 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
00543
00544 /** @brief  Clears the specified QSPI's flag status.
00545   * @param  __HANDLE__: specifies the QSPI Handle.
00546   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00547   *          This parameter can be one of the following values:
00548   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00549   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00550   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00551   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00552   * @retval None
00553   */
00554 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00555 /**
00556   * @}
00557   */
00558
00559 /* Exported functions --------------------------------------------------------*/
00560 /** @addtogroup QSPI_Exported_Functions
00561   * @{
00562   */
00563 /* Initialization/de-initialization functions  ********************************/
00564 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00565 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00566 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00567 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00568
00569 /* IO operation functions *****************************************************/
00570 /* QSPI IRQ handler method */
00571 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00572
00573 /* QSPI indirect mode */
00574 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00575 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00576 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00577 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00578 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00579 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00580 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00581 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00582
00583 /* QSPI status flag polling mode */
00584 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00585 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00586
00587 /* QSPI memory-mapped mode */
00588 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00589
00590 /* Callback functions in non-blocking modes ***********************************/
00591 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00592 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00593 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00594
00595 /* QSPI indirect mode */
00596 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00597 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00598 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00599
00600 /* QSPI status flag polling mode */
00601 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00602
00603 /* QSPI memory-mapped mode */
00604 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00605
00606 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00607 /* QSPI callback registering/unregistering */
00608 HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
00609 HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
00610 #endif
00611 /**
00612   * @}
00613   */
00614
00615 /** @addtogroup QSPI_Exported_Functions_Group3
00616   * @{
00617   */
00618 /* Peripheral Control and State functions  ************************************/
00619 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
00620 uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
00621 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00622 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00623 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00624 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00625 uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
00626 HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
00627 /**
00628   * @}
00629   */
00630
00631 /* End of exported functions -------------------------------------------------*/
00632
00633 /* Private macros ------------------------------------------------------------*/
00634 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00635 * @{
00636 */
00637 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
00638
00639 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 32U))
00640
00641 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00642                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00643
00644 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
00645
00646 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00647                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00648                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00649                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00650                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00651                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00652                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00653                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00654
00655 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00656                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00657
00658
00659 #define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \
00660                                             ((FLASH_ID) == QSPI_FLASH_ID_2))
00661
00662 #define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00663                                             ((MODE) == QSPI_DUALFLASH_DISABLE))
00664
00665 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
00666
00667 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00668                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00669                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00670                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00671
00672 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00673                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00674                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00675                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00676
00677 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
00678
00679 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00680                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00681                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00682                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00683
00684 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00685                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00686                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00687                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00688
00689 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00690                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00691                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00692                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00693
00694 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00695                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00696                                             ((MODE) == QSPI_DATA_2_LINES) || \
00697                                             ((MODE) == QSPI_DATA_4_LINES))
00698
00699 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00700                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00701
00702 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00703                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00704
00705 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00706                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00707
00708 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00709
00710 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
00711
00712 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00713                                             ((MODE) == QSPI_MATCH_MODE_OR))
00714
00715 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00716                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00717
00718 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00719                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00720
00721 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
00722 /**
00723 * @}
00724 */
00725 /* End of private macros -----------------------------------------------------*/
00726
00727 /**
00728   * @}
00729   */
00730
00731 /**
00732   * @}
00733   */
00734
00735 /**
00736   * @}
00737   */
00738
00739 #endif /* QUADSPI */
00740
00741 #ifdef __cplusplus
00742 }
00743 #endif
00744
00745 #endif /* STM32H7xx_HAL_QSPI_H */
00746
00747 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ramecc.c Source File

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stm32h7xx_hal_ramecc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ramecc.c
00004   * @author  MCD Application Team
00005   * @brief   RAMECC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the RAM ECC monitoring (RAMECC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Monitoring operation functions
00010   *           + Error informations functions
00011   *           + State and error functions
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017    (#) Enable and latch error informations through HAL_RAMECC_Init().
00018
00019    (#) For a given Monitor, enable and disable interrupt through
00020        HAL_RAMECC_EnableNotifiaction().
00021        To enable a notification for a given RAMECC instance, use global
00022        interrupts.
00023        To enable a notification for only RAMECC monitor, use monitor interrupts.
00024        All possible notifications are defined in the driver header file under
00025        RAMECC_Interrupt group.
00026
00027      *** Silent mode ***
00028      ===================
00029     [..]
00030           (+) Use HAL_RAMECC_StartMonitor() to start RAMECC latch failing
00031               information without enabling any notification.
00032
00033      *** Interrupt mode ***
00034      ======================
00035     [..]
00036           (+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a
00037               given error.
00038           (+) Configure the RAMECC interrupt priority using
00039               HAL_NVIC_SetPriority().
00040           (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().
00041
00042      *** Failing informations ***
00043      ======================
00044     [..]
00045      (#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC
00046          failing address.
00047      (#) Use HAL_RAMECC_GetFailingDataLow() function to return the RAMECC
00048          failing data low.
00049      (#) Use HAL_RAMECC_GetFailingDataHigh() function to return the RAMECC
00050          failing data high.
00051      (#) Use HAL_RAMECC_GetHammingErrorCode() function to return the RAMECC
00052          Hamming bits injected.
00053      (#) Use HAL_RAMECC_IsECCSingleErrorDetected() function to check if a single
00054          error was detected and corrected.
00055      (#) Use HAL_RAMECC_IsECCDoubleErrorDetected() function to check if a double
00056          error was dedetected.
00057
00058      *** RAMECC HAL driver macros list ***
00059      =============================================
00060      [..]
00061        Below the list of used macros in RAMECC HAL driver.
00062
00063       (+) __HAL_RAMECC_ENABLE_IT  : Enable the specified ECCRAM Monitor
00064                                     interrupts.
00065       (+) __HAL_RAMECC_DISABLE_IT : Disable the specified ECCRAM Monitor
00066                                     interrupts.
00067       (+) __HAL_RAMECC_GET_FLAG   : Return the current RAMECC Monitor selected
00068                                     flag.
00069       (+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
00070                                     flag.
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00076   * All rights reserved.</center></h2>
00077   *
00078   * This software component is licensed by ST under BSD 3-Clause license,
00079   * the "License"; You may not use this file except in compliance with the
00080   * License. You may obtain a copy of the License at:
00081   *                        opensource.org/licenses/BSD-3-Clause
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32h7xx_hal.h"
00088
00089 /** @addtogroup STM32H7xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @defgroup RAMECC RAMECC
00094   * @brief RAMECC HAL module driver
00095   * @{
00096   */
00097
00098 #ifdef HAL_RAMECC_MODULE_ENABLED
00099
00100 /* Private types -------------------------------------------------------------*/
00101 /* Private variables ---------------------------------------------------------*/
00102 /* Private constants ---------------------------------------------------------*/
00103 /* Private macros ------------------------------------------------------------*/
00104 /* Private functions ---------------------------------------------------------*/
00105 /* Exported functions --------------------------------------------------------*/
00106
00107 /** @addtogroup RAMECC_Exported_Functions
00108   * @{
00109   */
00110
00111 /** @addtogroup RAMECC_Exported_Functions_Group1
00112   *
00113 @verbatim
00114  ===============================================================================
00115              ##### Initialization and de-initialization functions  #####
00116  ===============================================================================
00117     [..]
00118     This section provides functions allowing to initialize the RAMECC Monitor.
00119     [..]
00120     The HAL_RAMECC_Init() function follows the RAMECC configuration procedures
00121     as described in reference manual.
00122     The HAL_RAMECC_DeInit() function allows to deinitialize the RAMECC monitor.
00123
00124 @endverbatim
00125   * @{
00126   */
00127
00128 /**
00129   * @brief  Initialize the RAMECC by clearing flags and disabling interrupts.
00130   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00131   *                  the configuration information for the specified RAMECC
00132   *                  Monitor.
00133   * @retval HAL status.
00134   */
00135 HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
00136 {
00137   /* Check the RAMECC peripheral handle */
00138   if (hramecc == NULL)
00139   {
00140     /* Return HAL status */
00141     return HAL_ERROR;
00142   }
00143
00144   /* Check the parameters */
00145   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00146
00147   /* Change RAMECC peripheral state */
00148   hramecc->State = HAL_RAMECC_STATE_BUSY;
00149
00150   /* Disable RAMECC monitor */
00151   hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
00152
00153   /* Disable all global interrupts */
00154   ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
00155     ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
00156
00157   /* Disable all interrupts monitor  */
00158   hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE);
00159
00160   /* Clear RAMECC monitor flags */
00161   __HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
00162
00163   /* Initialise the RAMECC error code */
00164   hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
00165
00166   /* Update the RAMECC state */
00167   hramecc->State = HAL_RAMECC_STATE_READY;
00168
00169   /* Return HAL status */
00170   return HAL_OK;
00171 }
00172
00173
00174 /**
00175   * @brief  DeInitializes the RAMECC peripheral.
00176   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00177   *                  the configuration information for the specified RAMECC
00178   *                  Monitor.
00179   * @retval HAL status.
00180   */
00181 HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
00182 {
00183   /* Check the RAMECC peripheral handle */
00184   if (hramecc == NULL)
00185   {
00186     /* Return HAL status */
00187     return HAL_ERROR;
00188   }
00189
00190   /* Check the parameters */
00191   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00192
00193   /* Disable RAMECC monitor */
00194   hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
00195
00196   /* Disable all global interrupts */
00197   ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
00198     ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
00199
00200   /* Disable all interrupts monitor  */
00201   hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE);
00202
00203   /* Clear RAMECC monitor flags */
00204   __HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
00205
00206   /* Clean callback */
00207   hramecc->DetectErrorCallback = NULL;
00208
00209   /* Initialise the RAMECC error code */
00210   hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
00211
00212   /* Change RAMECC peripheral state */
00213   hramecc->State = HAL_RAMECC_STATE_RESET;
00214
00215   /* Return HAL status */
00216   return HAL_OK;
00217 }
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @addtogroup RAMECC_Exported_Functions_Group2
00227   *
00228 @verbatim
00229  ===============================================================================
00230                    #####  Monitoring operation functions  #####
00231  ===============================================================================
00232     [..]  This section provides functions allowing to:
00233       (+) Configure latching error informations.
00234       (+) Configure RAMECC Global/Monitor interrupts.
00235       (+) Register and Unregister RAMECC callbacks
00236       (+) Handle RAMECC interrupt request
00237
00238 @endverbatim
00239   * @{
00240   */
00241
00242 /**
00243   * @brief  Starts the RAMECC latching error information.
00244   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00245   *                  the configuration information for the specified RAMECC
00246   *                  Monitor.
00247   * @retval HAL status.
00248   */
00249 HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
00250 {
00251   /* Check the parameters */
00252   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00253
00254   /* Check RAMECC state */
00255   if (hramecc->State == HAL_RAMECC_STATE_READY)
00256   {
00257     /* Change RAMECC peripheral state */
00258     hramecc->State = HAL_RAMECC_STATE_BUSY;
00259
00260     /* Enable RAMECC monitor */
00261     hramecc->Instance->CR |= RAMECC_CR_ECCELEN;
00262
00263     /* Change RAMECC peripheral state */
00264     hramecc->State = HAL_RAMECC_STATE_READY;
00265   }
00266   else
00267   {
00268     /* Update the error code */
00269     hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
00270
00271     /* Return HAL status */
00272     return HAL_ERROR;
00273   }
00274
00275   /* Return HAL status */
00276   return HAL_OK;
00277 }
00278
00279
00280 /**
00281   * @brief  Stop the RAMECC latching error informations.
00282   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00283   *                  the configuration information for the specified RAMECC
00284   *                  Monitor.
00285   * @retval HAL status.
00286   */
00287 HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
00288 {
00289   /* Check the parameters */
00290   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00291
00292   /* Check RAMECC state */
00293   if (hramecc->State == HAL_RAMECC_STATE_READY)
00294   {
00295     /* Change RAMECC peripheral state */
00296     hramecc->State = HAL_RAMECC_STATE_BUSY;
00297
00298     /* Disable RAMECC monitor */
00299     hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
00300
00301     /* Change RAMECC peripheral state */
00302     hramecc->State = HAL_RAMECC_STATE_READY;
00303   }
00304   else
00305   {
00306     /* Update the error code */
00307     hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
00308
00309     /* Return HAL status */
00310     return HAL_ERROR;
00311   }
00312
00313   /* Return HAL status */
00314   return HAL_OK;
00315 }
00316
00317
00318 /**
00319   * @brief  Enable the RAMECC error interrupts.
00320   * @param  hramecc        Pointer to a RAMECC_HandleTypeDef structure that
00321   *                        contains the configuration information for the
00322   *                        specified RAMECC Monitor.
00323   * @param  Notifications  Select the notification.
00324   * @retval HAL status.
00325   */
00326 HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
00327 {
00328   /* Check the parameters */
00329   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00330   assert_param (IS_RAMECC_INTERRUPT (Notifications));
00331
00332   /* Check RAMECC state */
00333   if (hramecc->State == HAL_RAMECC_STATE_READY)
00334   {
00335     /* Change RAMECC peripheral state */
00336     hramecc->State = HAL_RAMECC_STATE_BUSY;
00337
00338     /* Enable RAMECC interrupts */
00339     __HAL_RAMECC_ENABLE_IT (hramecc, Notifications);
00340
00341     /* Change RAMECC peripheral state */
00342     hramecc->State = HAL_RAMECC_STATE_READY;
00343   }
00344   else
00345   {
00346     /* Update the error code */
00347     hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
00348
00349     /* Return HAL status */
00350     return HAL_ERROR;
00351   }
00352
00353   /* Return HAL status */
00354   return HAL_OK;
00355 }
00356
00357
00358 /**
00359   * @brief  Disable the RAMECC error interrupts.
00360   * @param  hramecc        Pointer to a RAMECC_HandleTypeDef structure that
00361   *                        contains the configuration information for the
00362   *                        specified RAMECC Monitor.
00363   * @param  Notifications  Select the notification.
00364   * @retval HAL status.
00365   */
00366 HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
00367 {
00368   /* Check the parameters */
00369   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00370   assert_param (IS_RAMECC_INTERRUPT (Notifications));
00371
00372   /* Check RAMECC state */
00373   if (hramecc->State == HAL_RAMECC_STATE_READY)
00374   {
00375     /* Change RAMECC peripheral state */
00376     hramecc->State = HAL_RAMECC_STATE_BUSY;
00377
00378     /* Disable RAMECC interrupts */
00379     __HAL_RAMECC_DISABLE_IT (hramecc, Notifications);
00380
00381     /* Change RAMECC peripheral state */
00382     hramecc->State = HAL_RAMECC_STATE_READY;
00383   }
00384   else
00385   {
00386     /* Update the error code */
00387     hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
00388
00389     /* Return HAL status */
00390     return HAL_ERROR;
00391   }
00392
00393   /* Return HAL status */
00394   return HAL_OK;
00395 }
00396
00397
00398 /**
00399   * @brief  Register callbacks.
00400   * @param  hramecc    Pointer to a RAMECC_HandleTypeDef structure that contains
00401   *                    the configuration information for the specified RAMECC
00402   *                    Monitor.
00403   * @param  pCallback  pointer to private callbacsk function which has pointer to
00404   *                    a RAMECC_HandleTypeDef structure as parameter.
00405   * @retval HAL status.
00406   */
00407 HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc))
00408 {
00409   HAL_StatusTypeDef status = HAL_OK;
00410
00411   if (pCallback == NULL)
00412   {
00413     /* Update the error code */
00414     hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK;
00415
00416     /* Return HAL status */
00417     return HAL_ERROR;
00418   }
00419
00420   /* Check the parameters */
00421   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00422
00423   /* Check RAMECC state */
00424   if (hramecc->State == HAL_RAMECC_STATE_READY)
00425   {
00426     hramecc->DetectErrorCallback = pCallback;
00427   }
00428   else
00429   {
00430     /* Update the error code */
00431     hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK;
00432
00433     /* Update HAL status */
00434     status = HAL_ERROR;
00435   }
00436
00437   /* Return HAL status */
00438   return status;
00439 }
00440
00441
00442 /**
00443   * @brief  UnRegister callbacks.
00444   * @param  hramecc    Pointer to a RAMECC_HandleTypeDef structure that contains
00445   *                    the configuration information for the specified RAMECC
00446   *                    Monitor.
00447   * @retval HAL status.
00448   */
00449 HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
00450 {
00451   HAL_StatusTypeDef status = HAL_OK;
00452
00453   /* Check the parameters */
00454   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00455
00456   /* Check RAMECC state */
00457   if(hramecc->State == HAL_RAMECC_STATE_READY)
00458   {
00459     hramecc->DetectErrorCallback = NULL;
00460   }
00461   else
00462   {
00463     /* Update the error code */
00464     hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK;
00465
00466     /* Update HAL status */
00467     status = HAL_ERROR;
00468   }
00469
00470   /* Return HAL status */
00471   return status;
00472 }
00473
00474
00475 /**
00476   * @brief  Handles RAMECC interrupt request.
00477   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00478   *                  the configuration information for the specified RAMECC
00479   *                  Monitor.
00480   * @retval None.
00481   */
00482 void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
00483 {
00484   uint32_t ier_reg = ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER;
00485   uint32_t cr_reg = hramecc->Instance->CR >> 1U;
00486   uint32_t sr_reg = hramecc->Instance->SR << 1U;
00487
00488   /* Update global interrupt variables */
00489   if ((ier_reg & RAMECC_IER_GIE) == RAMECC_IER_GIE)
00490   {
00491     ier_reg = RAMECC_IT_GLOBAL_ALL;
00492   }
00493
00494   /* Clear active flags */
00495   __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U));
00496
00497   /* Check if a valid double error callback is registred */
00498   if (hramecc->DetectErrorCallback != NULL)
00499   {
00500     /* Error detection callback */
00501     hramecc->DetectErrorCallback(hramecc);
00502   }
00503 }
00504
00505
00506 /** @addtogroup RAMECC_Exported_Functions_Group3
00507   *
00508 @verbatim
00509  ===============================================================================
00510                    #####  Error informations functions  #####
00511  ===============================================================================
00512     [..]  This section provides functions allowing to:
00513       (+) Get failing address.
00514       (+) Get failing data low.
00515       (+) Get failing data high.
00516       (+) Get hamming bits injected.
00517       (+) Check single error flag.
00518       (+) Check double error flag.
00519
00520 @endverbatim
00521   * @{
00522   */
00523
00524 /**
00525   * @brief  Return the RAMECC failing address.
00526   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00527   *                  the configuration information for the specified RAMECC
00528   *                  Monitor.
00529   * @retval Failing address offset.
00530   */
00531 uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
00532 {
00533   /* Check the parameters */
00534   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00535
00536   /* Return failing address */
00537   return hramecc->Instance->FAR;
00538 }
00539
00540
00541 /**
00542   * @brief  Return the RAMECC data low.
00543   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00544   *                  the configuration information for the specified RAMECC
00545   *                  Monitor.
00546   * @retval Failing data low.
00547   */
00548 uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
00549 {
00550   /* Check the parameters */
00551   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00552
00553   /* Return failing data low */
00554   return hramecc->Instance->FDRL;
00555 }
00556
00557
00558 /**
00559   * @brief  Return the RAMECC data high.
00560   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00561   *                  the configuration information for the specified RAMECC
00562   *                  Monitor.
00563   * @retval Failing data high.
00564   */
00565 uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
00566 {
00567   /* Check the parameters */
00568   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00569
00570   /* Return failing data high */
00571   return hramecc->Instance->FDRH;
00572 }
00573
00574
00575 /**
00576   * @brief  Return the RAMECC Hamming bits injected.
00577   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00578   *                  the configuration information for the specified RAMECC
00579   *                  Monitor.
00580   * @retval Hamming bits injected.
00581   */
00582 uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
00583 {
00584   /* Check the parameters */
00585   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00586
00587   /* Return hamming bits injected */
00588   return hramecc->Instance->FECR;
00589 }
00590
00591 /**
00592   * @brief  Check if an ECC single error was occured.
00593   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00594   *                  the configuration information for the specified RAMECC
00595   *                  Monitor.
00596   * @retval State of bit (1 or 0).
00597   */
00598 uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
00599 {
00600   /* Check the parameters */
00601   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00602
00603   /* Return the state of SEDC flag */
00604   return ((READ_BIT(hramecc->Instance->SR, RAMECC_SR_SEDCF) == (RAMECC_SR_SEDCF)) ? 1UL : 0UL);
00605 }
00606
00607 /**
00608   * @brief  Check if an ECC double error was occured.
00609   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
00610   *                  the configuration information for the specified RAMECC
00611   *                  Monitor.
00612   * @retval State of bit (1 or 0).
00613   */
00614 uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
00615 {
00616   /* Check the parameters */
00617   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
00618
00619   /* Return the state of DEDF | DEBWDF flags */
00620   return ((READ_BIT(hramecc->Instance->SR, (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U) ? 1UL : 0UL);
00621 }
00622 /**
00623   * @}
00624   */
00625
00626
00627 /** @addtogroup RAMECC_Exported_Functions_Group4
00628   *
00629 @verbatim
00630  ===============================================================================
00631                     ##### State and Error Functions  #####
00632  ===============================================================================
00633     [..]
00634     This section provides functions allowing to check and get the RAMECC state
00635     and the error code .
00636     [..]
00637     The HAL_RAMECC_GetState() function allows to get the RAMECC peripheral
00638     state.
00639     The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error
00640     code.
00641
00642 @endverbatim
00643   * @{
00644   */
00645
00646 /**
00647   * @brief  Get the RAMECC peripheral state.
00648   * @param  hramecc       : Pointer to a RAMECC_HandleTypeDef structure that
00649   *                         contains the configuration information for the
00650   *                         specified RAMECC instance.
00651   * @retval RAMECC state.
00652   */
00653 HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
00654 {
00655   /* Return the RAMECC state */
00656   return hramecc->State;
00657 }
00658
00659 /**
00660   * @brief  Get the RAMECC peripheral error code.
00661   * @param  hramecc       : Pointer to a RAMECC_HandleTypeDef structure that
00662   *                         contains the configuration information for the
00663   *                         specified RAMECC instance.
00664   * @retval RAMECC error code.
00665   */
00666 uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
00667 {
00668   /* Return the RAMECC error code */
00669   return hramecc->ErrorCode;
00670 }
00671 /**
00672   * @}
00673   */
00674 #endif /* HAL_RAMECC_MODULE_ENABLED */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /**
00685   * @}
00686   */
00687
00688 /**
00689   * @}
00690   */
00691
00692 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_ramecc.h Source File

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stm32h7xx_hal_ramecc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ramecc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RAMECC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RAMECC_H
00022 #define STM32H7xx_HAL_RAMECC_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup RAMECC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup RAMECC_Exported_Types RAMECC Exported Types
00042   * @brief    RAMECC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL RAMECC State structures definition
00048   */
00049 typedef enum
00050 {
00051   HAL_RAMECC_STATE_RESET             = 0x00U,  /*!< RAMECC not yet initialized or disabled */
00052   HAL_RAMECC_STATE_READY             = 0x01U,  /*!< RAMECC initialized and ready for use   */
00053   HAL_RAMECC_STATE_BUSY              = 0x02U,  /*!< RAMECC process is ongoing              */
00054   HAL_RAMECC_STATE_ERROR             = 0x03U,  /*!< RAMECC error state                     */
00055 }HAL_RAMECC_StateTypeDef;
00056
00057
00058 /**
00059   * @brief  RAMECC handle Structure definition
00060   */
00061
00062 typedef struct __RAMECC_HandleTypeDef
00063 {
00064   RAMECC_MonitorTypeDef           *Instance;                                                            /*!< Register base address        */
00065   __IO HAL_RAMECC_StateTypeDef    State;                                                                /*!< RAMECC state                 */
00066   __IO uint32_t                   ErrorCode;                                                            /*!< RAMECC Error Code            */
00067   void                            (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc);     /*!< RAMECC error detect callback */
00068 }RAMECC_HandleTypeDef;
00069
00070 /**
00071   * @}
00072   */
00073
00074
00075 /* Exported constants --------------------------------------------------------*/
00076
00077 /** @defgroup RAMECC_Error_Codes RAMECC Error Codes
00078   * @{
00079   */
00080 #define HAL_RAMECC_ERROR_NONE              0x00000000U  /*!< RAMECC No Error         */
00081 #define HAL_RAMECC_ERROR_TIMEOUT           0x00000001U  /*!< RAMECC Timeout Error    */
00082 #define HAL_RAMECC_ERROR_BUSY              0x00000002U  /*!< RAMECC Busy Error       */
00083 #define HAL_RAMECC_ERROR_INVALID_CALLBACK  0x00000003U  /*!< Invalid Callback error  */
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup RAMECC_Interrupt RAMECC interrupts
00089   * @{
00090   */
00091 #define RAMECC_IT_GLOBAL_ID                0x10000000UL
00092 #define RAMECC_IT_MONITOR_ID               0x20000000UL
00093
00094 #define RAMECC_IT_GLOBAL_ENABLE            (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE)
00095 #define RAMECC_IT_GLOBAL_SINGLEERR_R       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE)
00096 #define RAMECC_IT_GLOBAL_DOUBLEERR_R       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE)
00097 #define RAMECC_IT_GLOBAL_DOUBLEERR_W       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE)
00098 #define RAMECC_IT_GLOBAL_ALL               (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE)
00099
00100
00101 #define RAMECC_IT_MONITOR_SINGLEERR_R      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE)
00102 #define RAMECC_IT_MONITOR_DOUBLEERR_R      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE)
00103 #define RAMECC_IT_MONITOR_DOUBLEERR_W      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE)
00104 #define RAMECC_IT_MONITOR_ALL              (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE)
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup RAMECC_FLAG RAMECC Monitor flags
00110   * @{
00111   */
00112 #define RAMECC_FLAG_SINGLEERR_R            RAMECC_SR_SEDCF
00113 #define RAMECC_FLAG_DOUBLEERR_R            RAMECC_SR_DEDF
00114 #define RAMECC_FLAG_DOUBLEERR_W            RAMECC_SR_DEBWDF
00115 #define RAMECC_FLAGS_ALL                   (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Exported macro ------------------------------------------------------------*/
00122 /** @defgroup RAMECC_Exported_Macros RAMECC Exported Macros
00123   * @{
00124   */
00125
00126 #define __HAL_RAMECC_ENABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
00127 #define __HAL_RAMECC_ENABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
00128
00129 /**
00130   * @brief  Enable the specified RAMECC interrupts.
00131   * @param  __HANDLE__   : RAMECC handle.
00132   * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
00133   *        This parameter can be one of the following values:
00134   *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
00135   *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
00136   *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
00137   *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
00138   *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
00139   *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
00140   *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
00141   *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
00142   *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
00143   * @retval None
00144   */
00145 #define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \
00146 (IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_ENABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\
00147 (__HAL_RAMECC_ENABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))
00148
00149
00150 #define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
00151 #define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
00152
00153 /**
00154   * @brief  Disable the specified RAMECC interrupts.
00155   * @param  __HANDLE__   : RAMECC handle.
00156   * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
00157   *        This parameter can be one of the following values:
00158   *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
00159   *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
00160   *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
00161   *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
00162   *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
00163   *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
00164   *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
00165   *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
00166   *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
00167   * @retval None
00168   */
00169 #define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \
00170 (IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_DISABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\
00171 (__HAL_RAMECC_DISABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))
00172
00173
00174 #define __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
00175 #define __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
00176
00177 /**
00178   * @brief  Check whether the specified RAMECC interrupt source is enabled or not.
00179   * @param  __HANDLE__    : Specifies the RAMECC Handle.
00180   * @param  __INTERRUPT__ : Specifies the RAMECC interrupt source to check.
00181   *          This parameter can be one of the following values:
00182   *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
00183   *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
00184   *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
00185   *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
00186   *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
00187   *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
00188   *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
00189   *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
00190   *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
00191   * @retval The new state of __INTERRUPT__ (SET or RESET).
00192   */
00193 #define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (  \
00194 (IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_GET_GLOBAL_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
00195 (__HAL_RAMECC_GET_MONITOR_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
00196
00197
00198 /**
00199   * @brief  Get the RAMECC pending flags.
00200   * @param  __HANDLE__   : RAMECC handle.
00201   * @param  __FLAG__     : specifies the flag to clear.
00202   *          This parameter can be any combination of the following values:
00203   *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.
00204   *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.
00205   *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
00206   *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.
00207   * @retval The state of __FLAG__ (SET or RESET).
00208   */
00209 #define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
00210
00211
00212 /**
00213   * @brief  Clear the RAMECC pending flags.
00214   * @param  __HANDLE__   : RAMECC handle.
00215   * @param  __FLAG__     : specifies the flag to clear.
00216   *          This parameter can be any combination of the following values:
00217   *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.
00218   *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.
00219   *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
00220   *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.
00221   * @retval None.
00222   */
00223 #define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
00224
00225 /**
00226   * @brief  Reset the RAMECC handle state.
00227   * @param  __HANDLE__    : Specifies the RAMECC Handle.
00228   * @retval None.
00229   */
00230 #define __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)
00231 /**
00232   * @}
00233   */
00234
00235 /* Exported functions --------------------------------------------------------*/
00236
00237 /** @defgroup RAMECC_Exported_Functions RAMECC Exported Functions
00238   * @brief    RAMECC Exported functions
00239   * @{
00240   */
00241
00242 /** @defgroup RAMECC_Exported_Functions_Group1 Initialization and de-initialization functions
00243   * @brief    Initialization and de-initialization functions
00244   * @{
00245   */
00246 HAL_StatusTypeDef HAL_RAMECC_Init   (RAMECC_HandleTypeDef *hramecc);
00247 HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup RAMECC_Exported_Functions_Group2 monitoring operation functions
00253   * @brief    monitoring operation functions
00254   * @{
00255   */
00256 HAL_StatusTypeDef HAL_RAMECC_StartMonitor        (RAMECC_HandleTypeDef *hramecc);
00257 HAL_StatusTypeDef HAL_RAMECC_StopMonitor         (RAMECC_HandleTypeDef *hramecc);
00258 HAL_StatusTypeDef HAL_RAMECC_EnableNotification  (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
00259 HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
00260 void              HAL_RAMECC_IRQHandler          (RAMECC_HandleTypeDef *hramecc);
00261 HAL_StatusTypeDef HAL_RAMECC_RegisterCallback    (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
00262 HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback  (RAMECC_HandleTypeDef *hramecc);
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions
00268   * @brief    Error informations functions
00269   * @{
00270   */
00271 uint32_t HAL_RAMECC_GetFailingAddress        (RAMECC_HandleTypeDef *hramecc);
00272 uint32_t HAL_RAMECC_GetFailingDataLow        (RAMECC_HandleTypeDef *hramecc);
00273 uint32_t HAL_RAMECC_GetFailingDataHigh       (RAMECC_HandleTypeDef *hramecc);
00274 uint32_t HAL_RAMECC_GetHammingErrorCode      (RAMECC_HandleTypeDef *hramecc);
00275 uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);
00276 uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions
00282   * @brief    Error informations functions
00283   * @{
00284   */
00285 HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
00286 uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294 /* Private Constants -------------------------------------------------------------*/
00295 /** @defgroup RAMECC_Private_Constants RAMECC Private Constants
00296   * @brief    RAMECC private defines and constants
00297   * @{
00298   */
00299 /**
00300   * @}
00301   */
00302
00303 /* Private macros ------------------------------------------------------------*/
00304 /** @defgroup RAMECC_Private_Macros RAMECC Private Macros
00305   * @brief    RAMECC private macros
00306   * @{
00307   */
00308
00309 #define IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_GLOBAL_ENABLE)      || \
00310                                                ((INTERRUPT) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \
00311                                                ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \
00312                                                ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_W) || \
00313                                                ((INTERRUPT) == RAMECC_IT_GLOBAL_ALL))
00314
00315
00316 #define IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_MONITOR_SINGLEERR_R) || \
00317                                                 ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \
00318                                                 ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \
00319                                                 ((INTERRUPT) == RAMECC_IT_MONITOR_ALL))
00320
00321 #define IS_RAMECC_INTERRUPT(INTERRUPT) ((IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)) || \
00322                                         (IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)))
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RAMECC_FLAG RAMECC Monitor flags
00329   * @{
00330   */
00331
00332 /* Private functions ---------------------------------------------------------*/
00333 /** @defgroup RAMECC_Private_Functions RAMECC Private Functions
00334   * @brief    RAMECC private  functions
00335   * @{
00336   */
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352 #ifdef __cplusplus
00353 }
00354 #endif
00355
00356 #endif /* STM32H7xx_HAL_RAMECC_H */
00357
00358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc.c Source File

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stm32h7xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                       ##### RCC specific features #####
00014   ==============================================================================
00015     [..]
00016       After reset the device is running from Internal High Speed oscillator
00017       (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
00018       internal SRAM, Flash, JTAG and PWR
00019       (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
00020           all peripherals mapped on these buses are running at HSI speed.
00021       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00022       (+) All GPIOs are in analogue mode , except the JTAG pins which
00023           are assigned to be used for debug purpose.
00024
00025     [..]
00026       Once the device started from reset, the user application has to:
00027       (+) Configure the clock source to be used to drive the System clock
00028           (if the application needs higher frequency/performance)
00029       (+) Configure the System clock frequency and Flash settings
00030       (+) Configure the AHB and APB buses pre-scalers
00031       (+) Enable the clock for the peripheral(s) to be used
00032       (+) Configure the clock kernel source(s) for peripherals which clocks are not
00033           derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
00034           and RCC_D3CCIPR registers
00035
00036                       ##### RCC Limitations #####
00037   ==============================================================================
00038     [..]
00039       A delay between an RCC peripheral clock enable and the effective peripheral
00040       enabling should be taken into account in order to manage the peripheral read/write
00041       from/to registers.
00042       (+) This delay depends on the peripheral mapping.
00043       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
00044           after the clock enable bit is set on the hardware register
00045       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
00046           after the clock enable bit is set on the hardware register
00047
00048     [..]
00049       Implemented Workaround:
00050       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
00051           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00052
00053   @endverbatim
00054  ******************************************************************************
00055   * @attention
00056   *
00057   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00058   * All rights reserved.</center></h2>
00059   *
00060   * This software component is licensed by ST under BSD 3-Clause license,
00061   * the "License"; You may not use this file except in compliance with the
00062   * License. You may obtain a copy of the License at:
00063   *                        opensource.org/licenses/BSD-3-Clause
00064   *
00065   ******************************************************************************
00066   */
00067
00068 /* Includes ------------------------------------------------------------------*/
00069 #include "stm32h7xx_hal.h"
00070
00071 /** @addtogroup STM32H7xx_HAL_Driver
00072   * @{
00073   */
00074
00075 /** @defgroup RCC  RCC
00076   * @brief RCC HAL module driver
00077   * @{
00078   */
00079
00080 #ifdef HAL_RCC_MODULE_ENABLED
00081
00082 /* Private typedef -----------------------------------------------------------*/
00083 /* Private define ------------------------------------------------------------*/
00084 /* Private macro -------------------------------------------------------------*/
00085 /** @defgroup RCC_Private_Macros RCC Private Macros
00086   * @{
00087   */
00088 #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
00089 #define MCO1_GPIO_PORT        GPIOA
00090 #define MCO1_PIN              GPIO_PIN_8
00091
00092 #define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
00093 #define MCO2_GPIO_PORT         GPIOC
00094 #define MCO2_PIN               GPIO_PIN_9
00095
00096 /**
00097   * @}
00098   */
00099 /* Private variables ---------------------------------------------------------*/
00100 /** @defgroup RCC_Private_Variables RCC Private Variables
00101   * @{
00102   */
00103
00104 /**
00105   * @}
00106   */
00107 /* Private function prototypes -----------------------------------------------*/
00108 /* Exported functions --------------------------------------------------------*/
00109
00110 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00111   * @{
00112   */
00113
00114 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00115  *  @brief    Initialization and Configuration functions
00116  *
00117 @verbatim
00118  ===============================================================================
00119            ##### Initialization and de-initialization functions #####
00120  ===============================================================================
00121     [..]
00122       This section provides functions allowing to configure the internal/external oscillators
00123       (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
00124        AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
00125
00126     [..] Internal/external clock and PLL configuration
00127          (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
00128              the PLL as System clock source.
00129          (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
00130              clock, or PLL input.But even with frequency calibration, is less accurate than an
00131              external crystal oscillator or ceramic resonator.
00132          (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00133              clock source.
00134
00135          (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
00136              through the PLL as System clock source. Can be used also as RTC clock source.
00137
00138          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00139
00140          (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
00141              featuring three different output clocks and able  to work either in integer or Fractional mode.
00142            (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
00143                 and to some peripherals.
00144            (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
00145
00146
00147          (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
00148             (HSE used directly or through PLL as System clock source), the System clock
00149              is automatically switched to HSI and an interrupt is generated if enabled.
00150              The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
00151              exception vector.
00152
00153          (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
00154              or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
00155
00156          (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
00157              LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
00158
00159     [..] System, AHB and APB buses clocks configuration
00160          (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
00161              HSE and PLL.
00162              The AHB clock (HCLK) is derived from System core clock through configurable
00163              pre-scaler and used to clock the CPU, memory and peripherals mapped
00164              on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
00165              and used to clock the peripherals mapped on these buses. You can use
00166              "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
00167
00168          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
00169              with dual clock domain where kernel source clock could be selected through
00170              RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
00171
00172      (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
00173 @endverbatim
00174   * @{
00175   */
00176
00177 /**
00178   * @brief  Resets the RCC clock configuration to the default reset state.
00179   * @note   The default reset state of the clock configuration is given below:
00180   *            - HSI ON and used as system clock source
00181   *            - HSE, PLL1, PLL2 and PLL3 OFF
00182   *            - AHB, APB Bus pre-scaler set to 1.
00183   *            - CSS, MCO1 and MCO2 OFF
00184   *            - All interrupts disabled
00185   * @note   This function doesn't modify the configuration of the
00186   *            - Peripheral clocks
00187   *            - LSI, LSE and RTC clocks
00188   * @retval HAL status
00189   */
00190 HAL_StatusTypeDef HAL_RCC_DeInit(void)
00191 {
00192   uint32_t tickstart;
00193
00194         /* Increasing the CPU frequency */
00195   if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
00196   {
00197     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00198     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
00199
00200     /* Check that the new number of wait states is taken into account to access the Flash
00201     memory by reading the FLASH_ACR register */
00202     if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
00203     {
00204       return HAL_ERROR;
00205     }
00206
00207   }
00208
00209
00210   /* Get Start Tick */
00211   tickstart = HAL_GetTick();
00212
00213   /* Set HSION bit */
00214   SET_BIT(RCC->CR, RCC_CR_HSION);
00215
00216   /* Wait till HSI is ready */
00217   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00218   {
00219     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00220     {
00221       return HAL_TIMEOUT;
00222     }
00223   }
00224
00225   /* Set HSITRIM[6:0] bits to the reset value */
00226   SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
00227
00228   /* Reset CFGR register */
00229   CLEAR_REG(RCC->CFGR);
00230
00231   /* Update the SystemCoreClock global variable */
00232   SystemCoreClock = HSI_VALUE;
00233
00234   /* Adapt Systick interrupt period */
00235   if(HAL_InitTick(uwTickPrio) != HAL_OK)
00236   {
00237     return HAL_ERROR;
00238   }
00239
00240   /* Get Start Tick */
00241   tickstart = HAL_GetTick();
00242
00243   /* Wait till clock switch is ready */
00244   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
00245   {
00246     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00247     {
00248       return HAL_TIMEOUT;
00249     }
00250   }
00251
00252   /* Get Start Tick */
00253   tickstart = HAL_GetTick();
00254
00255   /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
00256   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
00257   | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
00258
00259   /* Wait till HSE is disabled */
00260   while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
00261   {
00262     if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00263     {
00264       return HAL_TIMEOUT;
00265     }
00266   }
00267
00268   /* Get Start Tick */
00269   tickstart = HAL_GetTick();
00270
00271   /* Clear PLLON bit */
00272   CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
00273
00274   /* Wait till PLL is disabled */
00275   while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
00276   {
00277     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00278     {
00279       return HAL_TIMEOUT;
00280     }
00281   }
00282
00283   /* Get Start Tick */
00284   tickstart = HAL_GetTick();
00285
00286   /* Reset PLL2ON bit */
00287   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
00288
00289   /* Wait till PLL2 is disabled */
00290   while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
00291   {
00292     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00293     {
00294       return HAL_TIMEOUT;
00295     }
00296   }
00297
00298   /* Get Start Tick */
00299   tickstart = HAL_GetTick();
00300
00301   /* Reset PLL3 bit */
00302   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
00303
00304   /* Wait till PLL3 is disabled */
00305   while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
00306   {
00307     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00308     {
00309       return HAL_TIMEOUT;
00310     }
00311   }
00312
00313 #if defined(RCC_D1CFGR_HPRE)
00314   /* Reset D1CFGR register */
00315   CLEAR_REG(RCC->D1CFGR);
00316
00317   /* Reset D2CFGR register */
00318   CLEAR_REG(RCC->D2CFGR);
00319
00320   /* Reset D3CFGR register */
00321   CLEAR_REG(RCC->D3CFGR);
00322 #else
00323   /* Reset CDCFGR1 register */
00324   CLEAR_REG(RCC->CDCFGR1);
00325
00326   /* Reset CDCFGR2 register */
00327   CLEAR_REG(RCC->CDCFGR2);
00328
00329   /* Reset SRDCFGR register */
00330   CLEAR_REG(RCC->SRDCFGR);
00331 #endif
00332
00333   /* Reset PLLCKSELR register to default value */
00334   RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
00335
00336   /* Reset PLLCFGR register to default value */
00337   WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
00338
00339   /* Reset PLL1DIVR register to default value */
00340   WRITE_REG(RCC->PLL1DIVR,0x01010280U);
00341
00342   /* Reset PLL1FRACR register */
00343   CLEAR_REG(RCC->PLL1FRACR);
00344
00345   /* Reset PLL2DIVR register to default value */
00346   WRITE_REG(RCC->PLL2DIVR,0x01010280U);
00347
00348   /* Reset PLL2FRACR register */
00349   CLEAR_REG(RCC->PLL2FRACR);
00350
00351   /* Reset PLL3DIVR register to default value */
00352   WRITE_REG(RCC->PLL3DIVR,0x01010280U);
00353
00354   /* Reset PLL3FRACR register */
00355   CLEAR_REG(RCC->PLL3FRACR);
00356
00357   /* Reset HSEBYP bit */
00358   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00359
00360   /* Disable all interrupts */
00361   CLEAR_REG(RCC->CIER);
00362
00363   /* Clear all interrupts flags */
00364   WRITE_REG(RCC->CICR,0xFFFFFFFFU);
00365
00366   /* Reset all RSR flags */
00367   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
00368
00369       /* Decreasing the number of wait states because of lower CPU frequency */
00370   if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
00371   {
00372     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00373     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
00374
00375     /* Check that the new number of wait states is taken into account to access the Flash
00376     memory by reading the FLASH_ACR register */
00377     if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
00378     {
00379       return HAL_ERROR;
00380     }
00381
00382 }
00383
00384   return HAL_OK;
00385 }
00386
00387 /**
00388   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00389   *         RCC_OscInitTypeDef.
00390   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
00391   *         contains the configuration information for the RCC Oscillators.
00392   * @note   The PLL is not disabled when used as system clock.
00393   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00394   *         supported by this function. User should request a transition to LSE Off
00395   *         first and then LSE On or LSE Bypass.
00396   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00397   *         supported by this function. User should request a transition to HSE Off
00398   *         first and then HSE On or HSE Bypass.
00399   * @retval HAL status
00400   */
00401 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00402 {
00403   uint32_t tickstart;
00404   uint32_t temp1_pllckcfg, temp2_pllckcfg;
00405
00406     /* Check Null pointer */
00407   if(RCC_OscInitStruct == NULL)
00408   {
00409     return HAL_ERROR;
00410   }
00411
00412   /* Check the parameters */
00413   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00414   /*------------------------------- HSE Configuration ------------------------*/
00415   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00416   {
00417     /* Check the parameters */
00418     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00419
00420     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00421     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
00422     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
00423     if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
00424     {
00425       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00426       {
00427         return HAL_ERROR;
00428       }
00429     }
00430     else
00431     {
00432       /* Set the new HSE configuration ---------------------------------------*/
00433       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00434
00435       /* Check the HSE State */
00436       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00437       {
00438         /* Get Start Tick*/
00439         tickstart = HAL_GetTick();
00440
00441         /* Wait till HSE is ready */
00442         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
00443         {
00444           if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00445           {
00446             return HAL_TIMEOUT;
00447           }
00448         }
00449       }
00450       else
00451       {
00452         /* Get Start Tick*/
00453         tickstart = HAL_GetTick();
00454
00455         /* Wait till HSE is disabled */
00456         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
00457         {
00458           if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00459           {
00460             return HAL_TIMEOUT;
00461           }
00462         }
00463       }
00464     }
00465   }
00466   /*----------------------------- HSI Configuration --------------------------*/
00467   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00468   {
00469     /* Check the parameters */
00470     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00471     assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00472
00473     /* When the HSI is used as system clock it will not be disabled */
00474     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00475     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
00476     if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
00477     {
00478       /* When HSI is used as system clock it will not be disabled */
00479       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00480       {
00481         return HAL_ERROR;
00482       }
00483       /* Otherwise, just the calibration is allowed */
00484       else
00485       {
00486         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00487         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00488       }
00489     }
00490
00491     else
00492     {
00493       /* Check the HSI State */
00494       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
00495       {
00496      /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
00497         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
00498
00499         /* Get Start Tick*/
00500         tickstart = HAL_GetTick();
00501
00502         /* Wait till HSI is ready */
00503         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
00504         {
00505           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00506           {
00507             return HAL_TIMEOUT;
00508           }
00509         }
00510
00511         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00512         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00513       }
00514       else
00515       {
00516         /* Disable the Internal High Speed oscillator (HSI). */
00517         __HAL_RCC_HSI_DISABLE();
00518
00519         /* Get Start Tick*/
00520         tickstart = HAL_GetTick();
00521
00522         /* Wait till HSI is disabled */
00523         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
00524         {
00525           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00526           {
00527             return HAL_TIMEOUT;
00528           }
00529         }
00530       }
00531     }
00532   }
00533   /*----------------------------- CSI Configuration --------------------------*/
00534   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
00535   {
00536     /* Check the parameters */
00537     assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
00538     assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
00539
00540     /* When the CSI is used as system clock it will not disabled */
00541     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00542     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
00543     if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
00544     {
00545       /* When CSI is used as system clock it will not disabled */
00546       if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
00547       {
00548         return HAL_ERROR;
00549       }
00550       /* Otherwise, just the calibration is allowed */
00551       else
00552       {
00553         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
00554         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
00555       }
00556     }
00557     else
00558     {
00559       /* Check the CSI State */
00560       if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
00561       {
00562         /* Enable the Internal High Speed oscillator (CSI). */
00563         __HAL_RCC_CSI_ENABLE();
00564
00565         /* Get Start Tick*/
00566         tickstart = HAL_GetTick();
00567
00568         /* Wait till CSI is ready */
00569         while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
00570         {
00571           if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
00572           {
00573             return HAL_TIMEOUT;
00574           }
00575         }
00576
00577         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
00578         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
00579       }
00580       else
00581       {
00582         /* Disable the Internal High Speed oscillator (CSI). */
00583         __HAL_RCC_CSI_DISABLE();
00584
00585         /* Get Start Tick*/
00586         tickstart = HAL_GetTick();
00587
00588         /* Wait till CSI is disabled */
00589         while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
00590         {
00591           if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
00592           {
00593             return HAL_TIMEOUT;
00594           }
00595         }
00596       }
00597     }
00598   }
00599   /*------------------------------ LSI Configuration -------------------------*/
00600   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00601   {
00602     /* Check the parameters */
00603     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00604
00605     /* Check the LSI State */
00606     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
00607     {
00608       /* Enable the Internal Low Speed oscillator (LSI). */
00609       __HAL_RCC_LSI_ENABLE();
00610
00611       /* Get Start Tick*/
00612       tickstart = HAL_GetTick();
00613
00614       /* Wait till LSI is ready */
00615       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
00616       {
00617         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00618         {
00619           return HAL_TIMEOUT;
00620         }
00621       }
00622     }
00623     else
00624     {
00625       /* Disable the Internal Low Speed oscillator (LSI). */
00626       __HAL_RCC_LSI_DISABLE();
00627
00628       /* Get Start Tick*/
00629       tickstart = HAL_GetTick();
00630
00631       /* Wait till LSI is ready */
00632       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
00633       {
00634         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00635         {
00636           return HAL_TIMEOUT;
00637         }
00638       }
00639     }
00640   }
00641
00642   /*------------------------------ HSI48 Configuration -------------------------*/
00643   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00644   {
00645     /* Check the parameters */
00646     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00647
00648     /* Check the HSI48 State */
00649     if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
00650     {
00651       /* Enable the Internal Low Speed oscillator (HSI48). */
00652       __HAL_RCC_HSI48_ENABLE();
00653
00654       /* Get time-out */
00655       tickstart = HAL_GetTick();
00656
00657       /* Wait till HSI48 is ready */
00658       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
00659       {
00660         if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
00661         {
00662           return HAL_TIMEOUT;
00663         }
00664       }
00665     }
00666     else
00667     {
00668       /* Disable the Internal Low Speed oscillator (HSI48). */
00669       __HAL_RCC_HSI48_DISABLE();
00670
00671       /* Get time-out */
00672       tickstart = HAL_GetTick();
00673
00674       /* Wait till HSI48 is ready */
00675       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
00676       {
00677         if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
00678         {
00679           return HAL_TIMEOUT;
00680         }
00681       }
00682     }
00683   }
00684   /*------------------------------ LSE Configuration -------------------------*/
00685   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00686   {
00687     /* Check the parameters */
00688     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00689
00690     /* Enable write access to Backup domain */
00691     PWR->CR1 |= PWR_CR1_DBP;
00692
00693     /* Wait for Backup domain Write protection disable */
00694     tickstart = HAL_GetTick();
00695
00696     while((PWR->CR1 & PWR_CR1_DBP) == 0U)
00697     {
00698       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
00699       {
00700         return HAL_TIMEOUT;
00701       }
00702     }
00703
00704     /* Set the new LSE configuration -----------------------------------------*/
00705     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00706     /* Check the LSE State */
00707     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
00708     {
00709       /* Get Start Tick*/
00710       tickstart = HAL_GetTick();
00711
00712       /* Wait till LSE is ready */
00713       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
00714       {
00715         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00716         {
00717           return HAL_TIMEOUT;
00718         }
00719       }
00720     }
00721     else
00722     {
00723       /* Get Start Tick*/
00724       tickstart = HAL_GetTick();
00725
00726       /* Wait till LSE is disabled */
00727       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
00728       {
00729         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00730         {
00731           return HAL_TIMEOUT;
00732         }
00733       }
00734     }
00735   }
00736   /*-------------------------------- PLL Configuration -----------------------*/
00737   /* Check the parameters */
00738   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00739   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00740   {
00741     /* Check if the PLL is used as system clock or not */
00742     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
00743     {
00744       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00745       {
00746         /* Check the parameters */
00747         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00748         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00749         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00750         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00751         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00752         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
00753         assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
00754
00755         /* Disable the main PLL. */
00756         __HAL_RCC_PLL_DISABLE();
00757
00758         /* Get Start Tick*/
00759         tickstart = HAL_GetTick();
00760
00761         /* Wait till PLL is disabled */
00762         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
00763         {
00764           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00765           {
00766             return HAL_TIMEOUT;
00767           }
00768         }
00769
00770         /* Configure the main PLL clock source, multiplication and division factors. */
00771         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00772                              RCC_OscInitStruct->PLL.PLLM,
00773                              RCC_OscInitStruct->PLL.PLLN,
00774                              RCC_OscInitStruct->PLL.PLLP,
00775                              RCC_OscInitStruct->PLL.PLLQ,
00776                              RCC_OscInitStruct->PLL.PLLR);
00777
00778          /* Disable PLLFRACN . */
00779          __HAL_RCC_PLLFRACN_DISABLE();
00780
00781          /* Configure PLL PLL1FRACN */
00782          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
00783
00784         /* Select PLL1 input reference frequency range: VCI */
00785         __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
00786
00787         /* Select PLL1 output frequency range : VCO */
00788         __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
00789
00790         /* Enable PLL System Clock output. */
00791          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
00792
00793         /* Enable PLL1Q Clock output. */
00794          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00795
00796         /* Enable PLL1R  Clock output. */
00797          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
00798
00799         /* Enable PLL1FRACN . */
00800          __HAL_RCC_PLLFRACN_ENABLE();
00801
00802         /* Enable the main PLL. */
00803         __HAL_RCC_PLL_ENABLE();
00804
00805         /* Get Start Tick*/
00806         tickstart = HAL_GetTick();
00807
00808         /* Wait till PLL is ready */
00809         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
00810         {
00811           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00812           {
00813             return HAL_TIMEOUT;
00814           }
00815         }
00816       }
00817       else
00818       {
00819         /* Disable the main PLL. */
00820         __HAL_RCC_PLL_DISABLE();
00821
00822         /* Get Start Tick*/
00823         tickstart = HAL_GetTick();
00824
00825         /* Wait till PLL is disabled */
00826         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
00827         {
00828           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00829           {
00830             return HAL_TIMEOUT;
00831           }
00832         }
00833       }
00834     }
00835     else
00836     {
00837       /* Do not return HAL_ERROR if request repeats the current configuration */
00838       temp1_pllckcfg = RCC->PLLCKSELR;
00839       temp2_pllckcfg = RCC->PLL1DIVR;
00840       if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
00841          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
00842          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
00843          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
00844          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
00845          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
00846          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
00847       {
00848         return HAL_ERROR;
00849       }
00850     }
00851   }
00852   return HAL_OK;
00853 }
00854
00855 /**
00856   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
00857   *         parameters in the RCC_ClkInitStruct.
00858   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
00859   *         contains the configuration information for the RCC peripheral.
00860   * @param  FLatency: FLASH Latency, this parameter depend on device selected
00861   *
00862   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00863   *         and updated by HAL_InitTick() function called within this function
00864   *
00865   * @note   The HSI is used (enabled by hardware) as system clock source after
00866   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
00867   *         of failure of the HSE used directly or indirectly as system clock
00868   *         (if the Clock Security System CSS is enabled).
00869   *
00870   * @note   A switch from one clock source to another occurs only if the target
00871   *         clock source is ready (clock stable after start-up delay or PLL locked).
00872   *         If a clock source which is not yet ready is selected, the switch will
00873   *         occur when the clock source will be ready.
00874   *         You can use HAL_RCC_GetClockConfig() function to know which clock is
00875   *         currently used as system clock source.
00876   * @note   Depending on the device voltage range, the software has to set correctly
00877   *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
00878   *         (for more details refer to section above "Initialization/de-initialization functions")
00879   * @retval None
00880   */
00881 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00882 {
00883   HAL_StatusTypeDef halstatus;
00884   uint32_t tickstart;
00885
00886    /* Check Null pointer */
00887   if(RCC_ClkInitStruct == NULL)
00888   {
00889     return HAL_ERROR;
00890   }
00891
00892   /* Check the parameters */
00893   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00894   assert_param(IS_FLASH_LATENCY(FLatency));
00895
00896   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00897     must be correctly programmed according to the frequency of the CPU clock
00898     (HCLK) and the supply voltage of the device. */
00899
00900   /* Increasing the CPU frequency */
00901   if(FLatency > __HAL_FLASH_GET_LATENCY())
00902   {
00903     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00904     __HAL_FLASH_SET_LATENCY(FLatency);
00905
00906     /* Check that the new number of wait states is taken into account to access the Flash
00907     memory by reading the FLASH_ACR register */
00908     if(__HAL_FLASH_GET_LATENCY() != FLatency)
00909     {
00910       return HAL_ERROR;
00911     }
00912
00913   }
00914
00915   /* Increasing the BUS frequency divider */
00916   /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
00917   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
00918   {
00919 #if defined (RCC_D1CFGR_D1PPRE)
00920     if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
00921     {
00922       assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
00923       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
00924     }
00925 #else
00926     if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
00927     {
00928       assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
00929       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
00930     }
00931 #endif
00932   }
00933
00934   /*-------------------------- PCLK1 Configuration ---------------------------*/
00935   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00936   {
00937 #if defined (RCC_D2CFGR_D2PPRE1)
00938     if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
00939     {
00940       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
00941       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
00942     }
00943 #else
00944     if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
00945     {
00946       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
00947       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
00948   }
00949 #endif
00950     }
00951   /*-------------------------- PCLK2 Configuration ---------------------------*/
00952   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00953   {
00954 #if defined(RCC_D2CFGR_D2PPRE2)
00955     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
00956     {
00957       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
00958       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
00959     }
00960 #else
00961      if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
00962     {
00963       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
00964       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
00965     }
00966 #endif
00967   }
00968
00969   /*-------------------------- D3PCLK1 Configuration ---------------------------*/
00970   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
00971   {
00972 #if defined(RCC_D3CFGR_D3PPRE)
00973     if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
00974     {
00975       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
00976       MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
00977     }
00978 #else
00979     if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
00980     {
00981       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
00982       MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
00983     }
00984 #endif
00985   }
00986
00987    /*-------------------------- HCLK Configuration --------------------------*/
00988   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00989   {
00990 #if defined (RCC_D1CFGR_HPRE)
00991     if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
00992     {
00993       /* Set the new HCLK clock divider */
00994       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00995       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00996     }
00997 #else
00998         if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
00999     {
01000       /* Set the new HCLK clock divider */
01001       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
01002       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
01003     }
01004 #endif
01005   }
01006
01007     /*------------------------- SYSCLK Configuration -------------------------*/
01008     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
01009     {
01010       assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
01011       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
01012 #if defined(RCC_D1CFGR_D1CPRE)
01013       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
01014 #else
01015       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
01016 #endif
01017       /* HSE is selected as System Clock Source */
01018       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
01019       {
01020         /* Check the HSE ready flag */
01021         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
01022         {
01023           return HAL_ERROR;
01024         }
01025       }
01026       /* PLL is selected as System Clock Source */
01027       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
01028       {
01029         /* Check the PLL ready flag */
01030         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
01031         {
01032           return HAL_ERROR;
01033         }
01034       }
01035       /* CSI is selected as System Clock Source */
01036       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
01037       {
01038         /* Check the PLL ready flag */
01039         if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
01040         {
01041           return HAL_ERROR;
01042         }
01043       }
01044       /* HSI is selected as System Clock Source */
01045       else
01046       {
01047         /* Check the HSI ready flag */
01048         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
01049         {
01050           return HAL_ERROR;
01051         }
01052       }
01053       MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
01054
01055       /* Get Start Tick*/
01056       tickstart = HAL_GetTick();
01057
01058         while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
01059         {
01060           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
01061           {
01062             return HAL_TIMEOUT;
01063           }
01064         }
01065
01066     }
01067
01068     /* Decreasing the BUS frequency divider */
01069    /*-------------------------- HCLK Configuration --------------------------*/
01070   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
01071   {
01072 #if defined(RCC_D1CFGR_HPRE)
01073     if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
01074     {
01075       /* Set the new HCLK clock divider */
01076       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
01077       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
01078     }
01079 #else
01080     if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
01081     {
01082       /* Set the new HCLK clock divider */
01083       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
01084       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
01085     }
01086 #endif
01087   }
01088
01089   /* Decreasing the number of wait states because of lower CPU frequency */
01090   if(FLatency < __HAL_FLASH_GET_LATENCY())
01091   {
01092     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
01093     __HAL_FLASH_SET_LATENCY(FLatency);
01094
01095     /* Check that the new number of wait states is taken into account to access the Flash
01096     memory by reading the FLASH_ACR register */
01097     if(__HAL_FLASH_GET_LATENCY() != FLatency)
01098     {
01099       return HAL_ERROR;
01100     }
01101  }
01102
01103   /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
01104  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
01105  {
01106 #if defined(RCC_D1CFGR_D1PPRE)
01107    if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
01108    {
01109      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
01110      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
01111    }
01112 #else
01113    if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
01114    {
01115      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
01116      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
01117    }
01118 #endif
01119  }
01120
01121   /*-------------------------- PCLK1 Configuration ---------------------------*/
01122  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
01123  {
01124 #if defined(RCC_D2CFGR_D2PPRE1)
01125    if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
01126    {
01127      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
01128      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
01129    }
01130 #else
01131    if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
01132    {
01133      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
01134      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
01135    }
01136 #endif
01137  }
01138
01139   /*-------------------------- PCLK2 Configuration ---------------------------*/
01140  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
01141  {
01142 #if defined (RCC_D2CFGR_D2PPRE2)
01143    if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
01144    {
01145      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
01146      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
01147    }
01148 #else
01149    if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
01150    {
01151      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
01152      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
01153    }
01154 #endif
01155  }
01156
01157   /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
01158  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
01159  {
01160 #if defined(RCC_D3CFGR_D3PPRE)
01161    if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
01162    {
01163      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
01164      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
01165    }
01166 #else
01167    if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
01168    {
01169      assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
01170      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
01171    }
01172 #endif
01173  }
01174
01175   /* Update the SystemCoreClock global variable */
01176 #if defined(RCC_D1CFGR_D1CPRE)
01177   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
01178 #else
01179   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
01180 #endif
01181   /* Configure the source of time base considering new system clocks settings*/
01182   halstatus = HAL_InitTick (uwTickPrio);
01183
01184   return halstatus;
01185 }
01186
01187 /**
01188   * @}
01189   */
01190
01191 /** @defgroup RCC_Group2 Peripheral Control functions
01192  *  @brief   RCC clocks control functions
01193  *
01194 @verbatim
01195  ===============================================================================
01196                       ##### Peripheral Control functions #####
01197  ===============================================================================
01198     [..]
01199     This subsection provides a set of functions allowing to control the RCC Clocks
01200     frequencies.
01201
01202 @endverbatim
01203   * @{
01204   */
01205
01206 /**
01207   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
01208   * @note   PA8/PC9 should be configured in alternate function mode.
01209   * @param  RCC_MCOx: specifies the output direction for the clock source.
01210   *          This parameter can be one of the following values:
01211   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
01212   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
01213   * @param  RCC_MCOSource: specifies the clock source to output.
01214   *          This parameter can be one of the following values:
01215   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
01216   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
01217   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
01218   *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
01219   *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
01220   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
01221   *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
01222   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
01223   *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
01224   *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
01225   *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
01226   * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
01227   *          This parameter can be one of the following values:
01228   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
01229   * @retval None
01230   */
01231 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
01232 {
01233   GPIO_InitTypeDef GPIO_InitStruct;
01234   /* Check the parameters */
01235   assert_param(IS_RCC_MCO(RCC_MCOx));
01236   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
01237   /* RCC_MCO1 */
01238   if(RCC_MCOx == RCC_MCO1)
01239   {
01240     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
01241
01242     /* MCO1 Clock Enable */
01243     MCO1_CLK_ENABLE();
01244
01245     /* Configure the MCO1 pin in alternate function mode */
01246     GPIO_InitStruct.Pin = MCO1_PIN;
01247     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
01248     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
01249     GPIO_InitStruct.Pull = GPIO_NOPULL;
01250     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01251     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
01252
01253     /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
01254     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
01255   }
01256   else
01257   {
01258     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
01259
01260     /* MCO2 Clock Enable */
01261     MCO2_CLK_ENABLE();
01262
01263     /* Configure the MCO2 pin in alternate function mode */
01264     GPIO_InitStruct.Pin = MCO2_PIN;
01265     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
01266     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
01267     GPIO_InitStruct.Pull = GPIO_NOPULL;
01268     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01269     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
01270
01271     /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
01272     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
01273   }
01274 }
01275
01276 /**
01277   * @brief  Enables the Clock Security System.
01278   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01279   *         is automatically disabled and an interrupt is generated to inform the
01280   *         software about the failure (Clock Security System Interrupt, CSSI),
01281   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01282   *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
01283   * @retval None
01284   */
01285 void HAL_RCC_EnableCSS(void)
01286 {
01287   SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
01288 }
01289
01290 /**
01291   * @brief  Disables the Clock Security System.
01292   * @retval None
01293   */
01294 void HAL_RCC_DisableCSS(void)
01295 {
01296   CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
01297 }
01298
01299 /**
01300   * @brief  Returns the SYSCLK frequency
01301   *
01302   * @note   The system frequency computed by this function is not the real
01303   *         frequency in the chip. It is calculated based on the predefined
01304   *         constant and the selected clock source:
01305   * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
01306   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
01307   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
01308   * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
01309   *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
01310   * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01311   *               4 MHz) but the real value may vary depending on the variations
01312   *               in voltage and temperature.
01313   * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01314   *               64 MHz) but the real value may vary depending on the variations
01315   *               in voltage and temperature.
01316   * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01317   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
01318   *                frequency of the crystal used. Otherwise, this function may
01319   *                have wrong result.
01320   *
01321   * @note   The result of this function could be not correct when using fractional
01322   *         value for HSE crystal.
01323   *
01324   * @note   This function can be used by the user application to compute the
01325   *         baud rate for the communication peripherals or configure other parameters.
01326   *
01327   * @note   Each time SYSCLK changes, this function must be called to update the
01328   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01329   *
01330   *
01331   * @retval SYSCLK frequency
01332   */
01333 uint32_t HAL_RCC_GetSysClockFreq(void)
01334 {
01335   uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
01336   float_t fracn1, pllvco;
01337   uint32_t sysclockfreq;
01338
01339   /* Get SYSCLK source -------------------------------------------------------*/
01340
01341   switch (RCC->CFGR & RCC_CFGR_SWS)
01342   {
01343   case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
01344
01345    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
01346       {
01347         sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
01348       }
01349       else
01350       {
01351         sysclockfreq = (uint32_t) HSI_VALUE;
01352       }
01353
01354     break;
01355
01356   case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
01357     sysclockfreq = CSI_VALUE;
01358     break;
01359
01360   case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
01361     sysclockfreq = HSE_VALUE;
01362     break;
01363
01364   case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
01365
01366     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
01367     SYSCLK = PLL_VCO / PLLR
01368     */
01369     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
01370     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
01371     pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
01372     fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
01373
01374     if (pllm != 0U)
01375     {
01376       switch (pllsource)
01377       {
01378       case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01379
01380        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
01381         {
01382           hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
01383           pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
01384         }
01385         else
01386         {
01387           pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
01388         }
01389         break;
01390
01391       case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
01392         pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
01393         break;
01394
01395       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01396         pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
01397         break;
01398
01399       default:
01400         pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
01401         break;
01402       }
01403       pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
01404       sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
01405     }
01406     else
01407     {
01408       sysclockfreq = 0U;
01409     }
01410     break;
01411
01412   default:
01413     sysclockfreq = CSI_VALUE;
01414     break;
01415   }
01416
01417   return sysclockfreq;
01418 }
01419
01420
01421 /**
01422   * @brief  Returns the HCLK frequency
01423   * @note   Each time HCLK changes, this function must be called to update the
01424   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01425   *
01426   * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
01427   *         and updated within this function
01428   * @retval HCLK frequency
01429   */
01430 uint32_t HAL_RCC_GetHCLKFreq(void)
01431 {
01432 #if defined(RCC_D1CFGR_HPRE)
01433   SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
01434 #else
01435   SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
01436 #endif
01437   return SystemD2Clock;
01438 }
01439
01440
01441 /**
01442   * @brief  Returns the PCLK1 frequency
01443   * @note   Each time PCLK1 changes, this function must be called to update the
01444   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01445   * @retval PCLK1 frequency
01446   */
01447 uint32_t HAL_RCC_GetPCLK1Freq(void)
01448 {
01449 #if defined (RCC_D2CFGR_D2PPRE1)
01450   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01451   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
01452 #else
01453  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01454   return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> POSITION_VAL(RCC_CDCFGR2_CDPPRE1_0)]);
01455 #endif
01456 }
01457
01458
01459 /**
01460   * @brief  Returns the PCLK2 frequency
01461   * @note   Each time PCLK2 changes, this function must be called to update the
01462   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01463   * @retval PCLK1 frequency
01464   */
01465 uint32_t HAL_RCC_GetPCLK2Freq(void)
01466 {
01467   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01468 #if defined(RCC_D2CFGR_D2PPRE2)
01469   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
01470 #else
01471   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
01472 #endif
01473 }
01474
01475 /**
01476   * @brief  Configures the RCC_OscInitStruct according to the internal
01477   * RCC configuration registers.
01478   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
01479   * will be configured.
01480   * @retval None
01481   */
01482 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01483 {
01484   /* Set all possible values for the Oscillator type parameter ---------------*/
01485   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
01486                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
01487
01488   /* Get the HSE configuration -----------------------------------------------*/
01489 #if defined(RCC_CR_HSEEXT)
01490   if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
01491   {
01492     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01493   }
01494   else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
01495   {
01496     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
01497   }
01498   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01499   {
01500     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01501   }
01502   else
01503   {
01504     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01505   }
01506 #else
01507   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01508   {
01509     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01510   }
01511   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01512   {
01513     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01514   }
01515   else
01516   {
01517     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01518   }
01519 #endif /* RCC_CR_HSEEXT */
01520
01521    /* Get the CSI configuration -----------------------------------------------*/
01522   if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
01523   {
01524     RCC_OscInitStruct->CSIState = RCC_CSI_ON;
01525   }
01526   else
01527   {
01528     RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
01529   }
01530
01531 #if defined(RCC_VER_X)
01532   if(HAL_GetREVID() <= REV_ID_Y)
01533   {
01534     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
01535   }
01536   else
01537   {
01538     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
01539   }
01540 #else
01541  RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
01542 #endif /*RCC_VER_X*/
01543
01544   /* Get the HSI configuration -----------------------------------------------*/
01545   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
01546   {
01547     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01548   }
01549   else
01550   {
01551     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01552   }
01553
01554 #if defined(RCC_VER_X)
01555   if(HAL_GetREVID() <= REV_ID_Y)
01556   {
01557     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
01558   }
01559   else
01560   {
01561     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
01562   }
01563 #else
01564     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
01565 #endif /*RCC_VER_X*/
01566
01567   /* Get the LSE configuration -----------------------------------------------*/
01568 #if defined(RCC_BDCR_LSEEXT)
01569   if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
01570   {
01571     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01572   }
01573   else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
01574   {
01575     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
01576   }
01577   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01578   {
01579     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01580   }
01581   else
01582   {
01583     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01584   }
01585 #else
01586   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01587   {
01588     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01589   }
01590   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01591   {
01592     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01593   }
01594   else
01595   {
01596     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01597   }
01598 #endif /* RCC_BDCR_LSEEXT */
01599
01600   /* Get the LSI configuration -----------------------------------------------*/
01601   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01602   {
01603     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01604   }
01605   else
01606   {
01607     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01608   }
01609
01610   /* Get the HSI48 configuration ---------------------------------------------*/
01611   if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
01612   {
01613     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01614   }
01615   else
01616   {
01617     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01618   }
01619
01620   /* Get the PLL configuration -----------------------------------------------*/
01621   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01622   {
01623     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01624   }
01625   else
01626   {
01627     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01628   }
01629   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
01630   RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
01631   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
01632   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
01633   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
01634   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
01635   RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
01636   RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
01637   RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
01638 }
01639
01640 /**
01641   * @brief  Configures the RCC_ClkInitStruct according to the internal
01642   * RCC configuration registers.
01643   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
01644   * will be configured.
01645   * @param  pFLatency: Pointer on the Flash Latency.
01646   * @retval None
01647   */
01648 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01649 {
01650   /* Set all possible values for the Clock type parameter --------------------*/
01651   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
01652                                  RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
01653
01654   /* Get the SYSCLK configuration --------------------------------------------*/
01655   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01656
01657 #if defined(RCC_D1CFGR_D1CPRE)
01658   /* Get the SYSCLK configuration ----------------------------------------------*/
01659   RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
01660
01661   /* Get the D1HCLK configuration ----------------------------------------------*/
01662   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
01663
01664   /* Get the APB3 configuration ----------------------------------------------*/
01665   RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
01666
01667   /* Get the APB1 configuration ----------------------------------------------*/
01668   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
01669
01670   /* Get the APB2 configuration ----------------------------------------------*/
01671   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
01672
01673   /* Get the APB4 configuration ----------------------------------------------*/
01674   RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
01675 #else
01676   /* Get the SYSCLK configuration ----------------------------------------------*/
01677   RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
01678
01679   /* Get the D1HCLK configuration ----------------------------------------------*/
01680   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
01681
01682   /* Get the APB3 configuration ----------------------------------------------*/
01683   RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
01684
01685   /* Get the APB1 configuration ----------------------------------------------*/
01686   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
01687
01688   /* Get the APB2 configuration ----------------------------------------------*/
01689   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
01690
01691   /* Get the APB4 configuration ----------------------------------------------*/
01692   RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
01693 #endif
01694
01695   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01696   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01697 }
01698
01699 /**
01700   * @brief This function handles the RCC CSS interrupt request.
01701   * @note This API should be called under the NMI_Handler().
01702   * @retval None
01703   */
01704 void HAL_RCC_NMI_IRQHandler(void)
01705 {
01706   /* Check RCC CSSF flag  */
01707   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01708   {
01709     /* RCC Clock Security System interrupt user callback */
01710     HAL_RCC_CCSCallback();
01711
01712     /* Clear RCC CSS pending bit */
01713     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01714   }
01715 }
01716
01717 /**
01718   * @brief  RCC Clock Security System interrupt callback
01719   * @retval none
01720   */
01721 __weak void HAL_RCC_CCSCallback(void)
01722 {
01723   /* NOTE : This function Should not be modified, when the callback is needed,
01724             the HAL_RCC_CCSCallback could be implemented in the user file
01725    */
01726 }
01727
01728 /**
01729   * @}
01730   */
01731
01732 /**
01733   * @}
01734   */
01735
01736 #endif /* HAL_RCC_MODULE_ENABLED */
01737 /**
01738   * @}
01739   */
01740
01741 /**
01742   * @}
01743   */
01744
01745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc.h Source File

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stm32h7xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RCC_H
00022 #define STM32H7xx_HAL_RCC_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup RCC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup RCC_Exported_Types RCC Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  RCC PLL configuration structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t PLLState;   /*!< The new state of the PLL.
00051                             This parameter can be a value of @ref RCC_PLL_Config                      */
00052
00053   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00054                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00055
00056   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00057                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00058
00059   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00060                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
00061                             or between Min_Data = 8 and Max_Data = 420(*)
00062                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
00063
00064   uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
00065                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
00066                           odd division factors are not allowed                                        */
00067
00068   uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
00069                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00070
00071   uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
00072                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00073   uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
00074                          This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
00075   uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
00076                          This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
00077
00078   uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
00079                         PLL1 VCO It should be a value between 0 and 8191                              */
00080
00081 }RCC_PLLInitTypeDef;
00082
00083 /**
00084   * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
00085   */
00086 typedef struct
00087 {
00088   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00089                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00090
00091   uint32_t HSEState;             /*!< The new state of the HSE.
00092                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00093
00094   uint32_t LSEState;             /*!< The new state of the LSE.
00095                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00096
00097   uint32_t HSIState;             /*!< The new state of the HSI.
00098                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00099
00100   uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
00101                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
00102                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
00103
00104   uint32_t LSIState;             /*!< The new state of the LSI.
00105                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00106
00107  uint32_t HSI48State;            /*!< The new state of the HSI48.
00108                                       This parameter can be a value of @ref RCC_HSI48_Config                      */
00109
00110   uint32_t CSIState;             /*!< The new state of the CSI.
00111                                       This parameter can be a value of @ref RCC_CSI_Config */
00112
00113   uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
00114                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
00115                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
00116
00117   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
00118
00119 }RCC_OscInitTypeDef;
00120
00121 /**
00122   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00123   */
00124 typedef struct
00125 {
00126   uint32_t ClockType;             /*!< The clock to be configured.
00127                                        This parameter can be a value of @ref RCC_System_Clock_Type                          */
00128
00129   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00130                                        This parameter can be a value of @ref RCC_System_Clock_Source                        */
00131
00132   uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
00133                                        a value of @ref RCC_SYS_Clock_Source                                                 */
00134
00135   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00136                                        This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
00137
00138   uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00139                                        This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
00140
00141   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00142                                        This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
00143   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00144                                        This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
00145   uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00146                                        This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
00147 }RCC_ClkInitTypeDef;
00148
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported constants --------------------------------------------------------*/
00154
00155 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00156   * @{
00157   */
00158
00159 /** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
00160   * @{
00161   */
00162 #define RCC_OSCILLATORTYPE_NONE        (0x00000000U)
00163 #define RCC_OSCILLATORTYPE_HSE         (0x00000001U)
00164 #define RCC_OSCILLATORTYPE_HSI         (0x00000002U)
00165 #define RCC_OSCILLATORTYPE_LSE         (0x00000004U)
00166 #define RCC_OSCILLATORTYPE_LSI         (0x00000008U)
00167 #define RCC_OSCILLATORTYPE_CSI         (0x00000010U)
00168 #define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)
00169
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup RCC_HSE_Config  RCC HSE Config
00175   * @{
00176   */
00177 #define RCC_HSE_OFF                    (0x00000000U)
00178 #define RCC_HSE_ON                     RCC_CR_HSEON
00179 #define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
00180 #if defined(RCC_CR_HSEEXT)
00181 #define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
00182 #endif /* RCC_CR_HSEEXT */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup RCC_LSE_Config  RCC LSE Config
00189   * @{
00190   */
00191 #define RCC_LSE_OFF                    (0x00000000U)
00192 #define RCC_LSE_ON                     RCC_BDCR_LSEON
00193 #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
00194 #if defined(RCC_BDCR_LSEEXT)
00195 #define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
00196 #endif /* RCC_BDCR_LSEEXT */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup RCC_HSI_Config  RCC HSI Config
00203   * @{
00204   */
00205 #define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
00206 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
00207
00208 #define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
00209 #define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
00210 #define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
00211 #define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
00212
00213
00214 #if defined(RCC_HSICFGR_HSITRIM_6)
00215 #define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */
00216 #else
00217 #define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */
00218 #endif
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup RCC_HSI48_Config  RCC HSI48 Config
00224   * @{
00225   */
00226 #define RCC_HSI48_OFF                      ((uint8_t)0x00)
00227 #define RCC_HSI48_ON                       ((uint8_t)0x01)
00228
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup RCC_LSI_Config  RCC LSI Config
00234   * @{
00235   */
00236 #define RCC_LSI_OFF                    (0x00000000U)
00237 #define RCC_LSI_ON                     RCC_CSR_LSION
00238
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup RCC_CSI_Config  RCC CSI Config
00244   * @{
00245   */
00246 #define RCC_CSI_OFF                    (0x00000000U)
00247 #define RCC_CSI_ON                     RCC_CR_CSION
00248
00249 #if defined(RCC_CSICFGR_CSITRIM_5)
00250 #define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */
00251 #else
00252 #define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */
00253 #endif /* RCC_CSICFGR_CSITRIM_5 */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup RCC_PLL_Config  RCC PLL Config
00259   * @{
00260   */
00261 #define RCC_PLL_NONE                   (0x00000000U)
00262 #define RCC_PLL_OFF                    (0x00000001U)
00263 #define RCC_PLL_ON                     (0x00000002U)
00264
00265 /**
00266   * @}
00267   */
00268
00269
00270 /** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
00271   * @{
00272   */
00273 #define RCC_PLLSOURCE_HSI              (0x00000000U)
00274 #define RCC_PLLSOURCE_CSI              (0x00000001U)
00275 #define RCC_PLLSOURCE_HSE              (0x00000002U)
00276 #define RCC_PLLSOURCE_NONE             (0x00000003U)
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
00282   * @{
00283   */
00284 #define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
00285 #define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
00286 #define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
00287
00288 /**
00289   * @}
00290   */
00291
00292
00293
00294 /** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
00295   * @{
00296   */
00297 #define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0
00298 #define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1
00299 #define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2
00300 #define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3
00301
00302
00303 /**
00304   * @}
00305   */
00306
00307
00308 /** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
00309   * @{
00310   */
00311 #define RCC_PLL1VCOWIDE                 (0x00000000U)
00312 #define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
00313
00314 /**
00315   * @}
00316   */
00317
00318
00319 /** @defgroup RCC_System_Clock_Type  RCC System Clock Type
00320   * @{
00321   */
00322 #define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)
00323 #define RCC_CLOCKTYPE_HCLK             (0x00000002U)
00324 #define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)
00325 #define RCC_CLOCKTYPE_PCLK1            (0x00000008U)
00326 #define RCC_CLOCKTYPE_PCLK2            (0x00000010U)
00327 #define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)
00328
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup RCC_System_Clock_Source  RCC System Clock Source
00334   * @{
00335   */
00336 #define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
00337 #define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
00338 #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
00339 #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
00340
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00346   * @{
00347   */
00348 #define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
00349 #define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00350 #define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00351 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
00357   * @{
00358   */
00359 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
00360 #define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
00361 #define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
00362 #define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
00363 #define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
00364 #define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
00365 #define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
00366 #define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
00367 #define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
00368 #define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
00369 #else
00370 #define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1
00371 #define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2
00372 #define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4
00373 #define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8
00374 #define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16
00375 #define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64
00376 #define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128
00377 #define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256
00378 #define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512
00379 #endif
00380 /**
00381   * @}
00382   */
00383
00384
00385 /** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
00386   * @{
00387   */
00388 #if defined(RCC_D1CFGR_HPRE_DIV1)
00389 #define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
00390 #define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
00391 #define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
00392 #define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
00393 #define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
00394 #define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
00395 #define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
00396 #define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
00397 #define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
00398 #else
00399 #define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1
00400 #define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2
00401 #define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4
00402 #define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8
00403 #define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16
00404 #define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64
00405 #define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128
00406 #define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256
00407 #define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512
00408 #endif
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
00414   * @{
00415   */
00416 #if defined (RCC_D1CFGR_D1PPRE_DIV1)
00417 #define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
00418 #define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
00419 #define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
00420 #define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
00421 #define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
00422 #else
00423 #define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1
00424 #define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2
00425 #define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4
00426 #define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8
00427 #define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16
00428 #endif
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
00434   * @{
00435   */
00436 #if defined (RCC_D2CFGR_D2PPRE1_DIV1)
00437 #define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
00438 #define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
00439 #define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
00440 #define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
00441 #define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
00442 #else
00443 #define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1
00444 #define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2
00445 #define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4
00446 #define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8
00447 #define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16
00448 #endif
00449
00450 /**
00451   * @}
00452   */
00453
00454 /** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
00455   * @{
00456   */
00457 #if defined (RCC_D2CFGR_D2PPRE2_DIV1)
00458 #define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
00459 #define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
00460 #define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
00461 #define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
00462 #define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
00463 #else
00464 #define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1
00465 #define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2
00466 #define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4
00467 #define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8
00468 #define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16
00469 #endif
00470 /**
00471   * @}
00472   */
00473
00474 /** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
00475   * @{
00476   */
00477 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
00478 #define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
00479 #define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
00480 #define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
00481 #define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
00482 #define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
00483 #else
00484 #define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1
00485 #define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2
00486 #define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4
00487 #define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8
00488 #define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16
00489 #endif
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
00495   * @{
00496   */
00497 #define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)
00498 #define RCC_RTCCLKSOURCE_LSE             (0x00000100U)
00499 #define RCC_RTCCLKSOURCE_LSI             (0x00000200U)
00500 #define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)
00501 #define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)
00502 #define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)
00503 #define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)
00504 #define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)
00505 #define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)
00506 #define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)
00507 #define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)
00508 #define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)
00509 #define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)
00510 #define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)
00511 #define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)
00512 #define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)
00513 #define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)
00514 #define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)
00515 #define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)
00516 #define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)
00517 #define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)
00518 #define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)
00519 #define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)
00520 #define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)
00521 #define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)
00522 #define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)
00523 #define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)
00524 #define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)
00525 #define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)
00526 #define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)
00527 #define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)
00528 #define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)
00529 #define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)
00530 #define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)
00531 #define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)
00532 #define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)
00533 #define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)
00534 #define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)
00535 #define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)
00536 #define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)
00537 #define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)
00538 #define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)
00539 #define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)
00540 #define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)
00541 #define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)
00542 #define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)
00543 #define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)
00544 #define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)
00545 #define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)
00546 #define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)
00547 #define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)
00548 #define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)
00549 #define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)
00550 #define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)
00551 #define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)
00552 #define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)
00553 #define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)
00554 #define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)
00555 #define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)
00556 #define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)
00557 #define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)
00558 #define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)
00559 #define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)
00560 #define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)
00561 #define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)
00562
00563
00564 /**
00565   * @}
00566   */
00567
00568
00569 /** @defgroup RCC_MCO_Index  RCC MCO Index
00570   * @{
00571   */
00572 #define RCC_MCO1                         (0x00000000U)
00573 #define RCC_MCO2                         (0x00000001U)
00574
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
00580   * @{
00581   */
00582 #define RCC_MCO1SOURCE_HSI               (0x00000000U)
00583 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
00584 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
00585 #define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
00586 #define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
00587
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
00593   * @{
00594   */
00595 #define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)
00596 #define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
00597 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
00598 #define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
00599 #define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
00600 #define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
00601
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
00607   * @{
00608   */
00609 #define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
00610 #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
00611 #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
00612 #define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
00613 #define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
00614 #define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00615 #define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00616 #define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
00617 #define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
00618 #define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00619 #define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00620 #define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00621 #define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00622 #define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00623 #define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
00624
00625
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup RCC_Interrupt  RCC Interrupt
00631   * @{
00632   */
00633 #define RCC_IT_LSIRDY                  (0x00000001U)
00634 #define RCC_IT_LSERDY                  (0x00000002U)
00635 #define RCC_IT_HSIRDY                  (0x00000004U)
00636 #define RCC_IT_HSERDY                  (0x00000008U)
00637 #define RCC_IT_CSIRDY                  (0x00000010U)
00638 #define RCC_IT_HSI48RDY                (0x00000020U)
00639 #define RCC_IT_PLLRDY                  (0x00000040U)
00640 #define RCC_IT_PLL2RDY                 (0x00000080U)
00641 #define RCC_IT_PLL3RDY                 (0x00000100U)
00642 #define RCC_IT_LSECSS                  (0x00000200U)
00643 #define RCC_IT_CSS                     (0x00000400U)
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup RCC_Flag  RCC Flag
00649   *        Elements values convention: XXXYYYYYb
00650   *           - YYYYY  : Flag position in the register
00651   *           - XXX  : Register index
00652   *                 - 001: CR register
00653   *                 - 010: BDCR register
00654   *                 - 011: CSR register
00655   *                 - 100: RSR register
00656   * @{
00657   */
00658 /* Flags in the CR register */
00659 #define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
00660 #define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
00661 #define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
00662 #define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
00663 #if defined(RCC_CR_D1CKRDY)
00664 #define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
00665 #else
00666 #define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)
00667 #define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */
00668 #endif /* RCC_CR_D1CKRDY */
00669 #if defined(RCC_CR_D2CKRDY)
00670 #define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
00671 #else
00672 #define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)
00673 #define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */
00674 #endif /* RCC_CR_D2CKRDY */
00675 #define RCC_FLAG_HSERDY                ((uint8_t)0x31)
00676 #define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
00677 #define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
00678 #define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
00679 /* Flags in the BDCR register */
00680 #define RCC_FLAG_LSERDY                ((uint8_t)0x41)
00681
00682 /* Flags in the CSR register */
00683 #define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
00684
00685 /* Flags in the RSR register */
00686 #if defined(RCC_RSR_CPURSTF)
00687 #define RCC_FLAG_CPURST                ((uint8_t)0x91)
00688 #endif /* RCC_RSR_CPURSTF */
00689
00690 #if defined(RCC_RSR_D1RSTF)
00691 #define RCC_FLAG_D1RST                 ((uint8_t)0x93)
00692 #else
00693 #define RCC_FLAG_CDRST                 ((uint8_t)0x93)
00694 #endif /* RCC_RSR_D1RSTF */
00695 #if defined(RCC_RSR_D2RSTF)
00696 #define RCC_FLAG_D2RST                 ((uint8_t)0x94)
00697 #endif /* RCC_RSR_D2RSTF */
00698 #define RCC_FLAG_BORRST                ((uint8_t)0x95)
00699 #define RCC_FLAG_PINRST                ((uint8_t)0x96)
00700 #define RCC_FLAG_PORRST                ((uint8_t)0x97)
00701 #define RCC_FLAG_SFTRST                ((uint8_t)0x98)
00702 #define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
00703 #define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
00704 #define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
00705 #define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
00706
00707 #if defined(DUAL_CORE)
00708 #define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)
00709 #define RCC_FLAG_C2RST                 ((uint8_t)0x92)
00710 #define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)
00711 #define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)
00712 #define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)
00713 #define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)
00714 #endif /*DUAL_CORE*/
00715
00716
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
00722   * @{
00723   */
00724 #define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */
00725 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
00726 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
00727 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
00728 /**
00729   * @}
00730   */
00731
00732 /** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
00733   * @{
00734   */
00735 #define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)
00736 #define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
00737
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
00743   * @{
00744   */
00745 #define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)
00746 #define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
00747
00748
00749 /**
00750   * @}
00751   */
00752
00753 #if defined(RCC_VER_X)
00754 #define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)
00755 #define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)
00756 #define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)
00757 #define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)
00758 #endif /* RCC_VER_X */
00759
00760 /**
00761   * @}
00762   */
00763
00764 /* Exported macros -----------------------------------------------------------*/
00765
00766 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00767   * @{
00768   */
00769
00770 /** @brief  Enable or disable the AHB3 peripheral clock.
00771   * @note   After reset, the peripheral clock (used for registers read/write access)
00772   *         is disabled and the application software has to enable this clock before
00773   *         using it.
00774   */
00775 #define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
00776                                         __IO uint32_t tmpreg; \
00777                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
00778                                         /* Delay after an RCC peripheral clock enabling */ \
00779                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
00780                                         UNUSED(tmpreg); \
00781                                        } while(0)
00782
00783 #define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
00784                                         __IO uint32_t tmpreg; \
00785                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
00786                                         /* Delay after an RCC peripheral clock enabling */ \
00787                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
00788                                         UNUSED(tmpreg); \
00789                                        } while(0)
00790
00791 #if defined(JPEG)
00792 #define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
00793                                         __IO uint32_t tmpreg; \
00794                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
00795                                         /* Delay after an RCC peripheral clock enabling */ \
00796                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
00797                                         UNUSED(tmpreg); \
00798                                        } while(0)
00799 #endif /* JPEG */
00800
00801 #define __HAL_RCC_FMC_CLK_ENABLE()   do { \
00802                                         __IO uint32_t tmpreg; \
00803                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00804                                         /* Delay after an RCC peripheral clock enabling */ \
00805                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00806                                         UNUSED(tmpreg); \
00807                                        } while(0)
00808
00809 #if defined(QUADSPI)
00810 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
00811                                         __IO uint32_t tmpreg; \
00812                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00813                                         /* Delay after an RCC peripheral clock enabling */ \
00814                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00815                                         UNUSED(tmpreg); \
00816                                        } while(0)
00817 #endif /* QUADSPI */
00818 #if defined(OCTOSPI1)
00819 #define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \
00820                                         __IO uint32_t tmpreg; \
00821                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
00822                                         /* Delay after an RCC peripheral clock enabling */ \
00823                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
00824                                         UNUSED(tmpreg); \
00825                                        } while(0)
00826 #endif /* OCTOSPI1 */
00827 #if defined(OCTOSPI2)
00828 #define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \
00829                                         __IO uint32_t tmpreg; \
00830                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
00831                                         /* Delay after an RCC peripheral clock enabling */ \
00832                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
00833                                         UNUSED(tmpreg); \
00834                                        } while(0)
00835 #endif /* OCTOSPI2 */
00836 #if defined(OCTOSPIM)
00837 #define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \
00838                                         __IO uint32_t tmpreg; \
00839                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
00840                                         /* Delay after an RCC peripheral clock enabling */ \
00841                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
00842                                         UNUSED(tmpreg); \
00843                                        } while(0)
00844 #endif /* OCTOSPIM */
00845 #if defined(OTFDEC1)
00846 #define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \
00847                                         __IO uint32_t tmpreg; \
00848                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
00849                                         /* Delay after an RCC peripheral clock enabling */ \
00850                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
00851                                         UNUSED(tmpreg); \
00852                                        } while(0)
00853 #endif /* OTFDEC1 */
00854 #if defined(OTFDEC2)
00855 #define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \
00856                                         __IO uint32_t tmpreg; \
00857                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
00858                                         /* Delay after an RCC peripheral clock enabling */ \
00859                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
00860                                         UNUSED(tmpreg); \
00861                                        } while(0)
00862 #endif /* OTFDEC2 */
00863 #if defined(GFXMMU)
00864 #define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \
00865                                         __IO uint32_t tmpreg; \
00866                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
00867                                         /* Delay after an RCC peripheral clock enabling */ \
00868                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
00869                                         UNUSED(tmpreg); \
00870                                        } while(0)
00871 #endif /* GFXMMU */
00872 #define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
00873                                         __IO uint32_t tmpreg; \
00874                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
00875                                         /* Delay after an RCC peripheral clock enabling */ \
00876                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
00877                                         UNUSED(tmpreg); \
00878                                        } while(0)
00879
00880
00881 #define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
00882 #define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
00883 #if defined(JPEG)
00884 #define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
00885 #endif /* JPEG */
00886 #define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
00887
00888 #if defined(QUADSPI)
00889 #define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
00890 #endif /* QUADSPI */
00891 #if defined(OCTOSPI1)
00892 #define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
00893 #endif /* OCTOSPII */
00894 #if defined(OCTOSPI2)
00895 #define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
00896 #endif /* OCTOSPI2 */
00897 #define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
00898 #if defined(OCTOSPIM)
00899 #define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
00900 #endif /* OCTOSPIM */
00901 #if defined(OTFDEC1)
00902 #define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
00903 #endif /* OTOFDEC1 */
00904 #if defined(OTFDEC2)
00905 #define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
00906 #endif /* OTOFDEC2 */
00907 #if defined(GFXMMU)
00908 #define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
00909 #endif /* GFXMMU */
00910
00911 /** @brief  Get the enable or disable status of the AHB3 peripheral clock
00912   * @note   After reset, the peripheral clock (used for registers read/write access)
00913   *         is disabled and the application software has to enable this clock before
00914   *         using it.
00915   */
00916
00917 #define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)
00918 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)
00919 #if defined(JPEG)
00920 #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
00921 #endif /* JPEG */
00922 #define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)
00923 #if defined (QUADSPI)
00924 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)
00925 #endif /* QUADSPI */
00926 #if defined(OCTOSPI1)
00927 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)
00928 #endif /* OCTOSPII */
00929 #if defined(OCTOSPI2)
00930 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)
00931 #endif /* OCTOSPI2 */
00932 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
00933 #if defined(OCTOSPIM)
00934 #define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
00935 #endif /* OCTOSPIM */
00936 #if defined(OTFDEC1)
00937 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
00938 #endif /* OTOFDEC1 */
00939 #if defined(OTFDEC2)
00940 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
00941 #endif /* OTOFDEC2 */
00942 #if defined(GFXMMU)
00943 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
00944 #endif /* GFXMMU */
00945
00946 #define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)
00947 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)
00948 #if defined(JPEG)
00949 #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
00950 #endif /* JPEG */
00951 #define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)
00952 #if defined (QUADSPI)
00953 #define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)
00954 #endif /* QUADSPI */
00955 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
00956 #if defined(OCTOSPI1)
00957 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
00958 #endif
00959 #if defined(OCTOSPI2)
00960 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
00961 #endif
00962 #if defined(OCTOSPIM)
00963 #define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
00964 #endif
00965 #if defined(OTFDEC1)
00966 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
00967 #endif
00968 #if defined(OTFDEC2)
00969 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
00970 #endif
00971 #if defined(GFXMMU)
00972 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
00973 #endif
00974 /** @brief  Enable or disable the AHB1 peripheral clock.
00975   * @note   After reset, the peripheral clock (used for registers read/write access)
00976   *         is disabled and the application software has to enable this clock before
00977   *         using it.
00978   */
00979
00980 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
00981                                         __IO uint32_t tmpreg; \
00982                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00983                                         /* Delay after an RCC peripheral clock enabling */ \
00984                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00985                                         UNUSED(tmpreg); \
00986                                        } while(0)
00987
00988 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
00989                                         __IO uint32_t tmpreg; \
00990                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00991                                         /* Delay after an RCC peripheral clock enabling */ \
00992                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00993                                         UNUSED(tmpreg); \
00994                                        } while(0)
00995
00996 #define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
00997                                         __IO uint32_t tmpreg; \
00998                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
00999                                         /* Delay after an RCC peripheral clock enabling */ \
01000                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
01001                                         UNUSED(tmpreg); \
01002                                        } while(0)
01003
01004 #if defined(DUAL_CORE)
01005 #define __HAL_RCC_ART_CLK_ENABLE()   do { \
01006                                         __IO uint32_t tmpreg; \
01007                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
01008                                         /* Delay after an RCC peripheral clock enabling */ \
01009                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
01010                                         UNUSED(tmpreg); \
01011                                        } while(0)
01012 #endif /*DUAL_CORE*/
01013
01014 #if defined(RCC_AHB1ENR_CRCEN)
01015 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
01016                                         __IO uint32_t tmpreg; \
01017                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
01018                                         /* Delay after an RCC peripheral clock enabling */ \
01019                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
01020                                         UNUSED(tmpreg); \
01021                                        } while(0)
01022 #endif
01023
01024 #if defined(ETH)
01025 #define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
01026                                         __IO uint32_t tmpreg; \
01027                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
01028                                         /* Delay after an RCC peripheral clock enabling */ \
01029                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
01030                                         UNUSED(tmpreg); \
01031                                        } while(0)
01032
01033 #define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
01034                                         __IO uint32_t tmpreg; \
01035                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
01036                                         /* Delay after an RCC peripheral clock enabling */ \
01037                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
01038                                         UNUSED(tmpreg); \
01039                                        } while(0)
01040
01041 #define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
01042                                         __IO uint32_t tmpreg; \
01043                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
01044                                         /* Delay after an RCC peripheral clock enabling */ \
01045                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
01046                                         UNUSED(tmpreg); \
01047                                        } while(0)
01048 #endif
01049
01050 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
01051                                         __IO uint32_t tmpreg; \
01052                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
01053                                         /* Delay after an RCC peripheral clock enabling */ \
01054                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
01055                                         UNUSED(tmpreg); \
01056                                        } while(0)
01057
01058 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
01059                                         __IO uint32_t tmpreg; \
01060                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
01061                                         /* Delay after an RCC peripheral clock enabling */ \
01062                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
01063                                         UNUSED(tmpreg); \
01064                                        } while(0)
01065
01066 #if defined(USB2_OTG_FS)
01067 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
01068                                         __IO uint32_t tmpreg; \
01069                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
01070                                         /* Delay after an RCC peripheral clock enabling */ \
01071                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
01072                                         UNUSED(tmpreg); \
01073                                        } while(0)
01074
01075 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
01076                                         __IO uint32_t tmpreg; \
01077                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
01078                                         /* Delay after an RCC peripheral clock enabling */ \
01079                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
01080                                         UNUSED(tmpreg); \
01081                                        } while(0)
01082 #endif
01083
01084 #define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
01085 #define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
01086 #define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
01087 #if defined(DUAL_CORE)
01088 #define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
01089 #endif /*DUAL_CORE*/
01090 #if defined(RCC_AHB1ENR_CRCEN)
01091 #define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
01092 #endif
01093 #if defined(ETH)
01094 #define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
01095 #define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
01096 #define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
01097 #endif
01098 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
01099 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
01100 #if defined(USB2_OTG_FS)
01101 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
01102 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
01103 #endif /* USB2_OTG_FS */
01104
01105 /** @brief  Get the enable or disable status of the AHB1 peripheral clock
01106   * @note   After reset, the peripheral clock (used for registers read/write access)
01107   *         is disabled and the application software has to enable this clock before
01108   *         using it.
01109   */
01110
01111 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)
01112 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)
01113 #define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)
01114 #if defined(DUAL_CORE)
01115 #define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)
01116 #endif /*DUAL_CORE*/
01117 #if defined(RCC_AHB1ENR_CRCEN)
01118 #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)
01119 #endif
01120 #if defined(ETH)
01121 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)
01122 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)
01123 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)
01124 #endif
01125 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)
01126 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
01127 #if defined(USB2_OTG_FS)
01128 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)
01129 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
01130 #endif /* USB2_OTG_FS */
01131
01132 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)
01133 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)
01134 #define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)
01135 #if defined(DUAL_CORE)
01136 #define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)
01137 #endif /*DUAL_CORE*/
01138 #if defined(RCC_AHB1ENR_CRCEN)
01139 #define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)
01140 #endif
01141 #if defined(ETH)
01142 #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)
01143 #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)
01144 #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)
01145 #endif
01146 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)
01147 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
01148 #if defined(USB2_OTG_FS)
01149 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)
01150 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
01151 #endif /* USB2_OTG_FS */
01152
01153 /** @brief  Enable or disable the AHB2 peripheral clock.
01154   * @note   After reset, the peripheral clock (used for registers read/write access)
01155   *         is disabled and the application software has to enable this clock before
01156   *         using it.
01157   */
01158
01159 #if defined(DCMI) && defined(PSSI)
01160 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \
01161                                         __IO uint32_t tmpreg; \
01162                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
01163                                         /* Delay after an RCC peripheral clock enabling */ \
01164                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
01165                                         UNUSED(tmpreg); \
01166                                        } while(0)
01167
01168 #define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/
01169 #else
01170 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
01171                                         __IO uint32_t tmpreg; \
01172                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
01173                                         /* Delay after an RCC peripheral clock enabling */ \
01174                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
01175                                         UNUSED(tmpreg); \
01176                                        } while(0)
01177 #endif /* DCMI && PSSI */
01178
01179 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
01180                                         __IO uint32_t tmpreg; \
01181                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
01182                                         /* Delay after an RCC peripheral clock enabling */ \
01183                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
01184                                         UNUSED(tmpreg); \
01185                                        } while(0)
01186
01187 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
01188                                         __IO uint32_t tmpreg; \
01189                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
01190                                         /* Delay after an RCC peripheral clock enabling */ \
01191                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
01192                                         UNUSED(tmpreg); \
01193                                        } while(0)
01194
01195 #define __HAL_RCC_RNG_CLK_ENABLE()   do { \
01196                                         __IO uint32_t tmpreg; \
01197                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
01198                                         /* Delay after an RCC peripheral clock enabling */ \
01199                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
01200                                         UNUSED(tmpreg); \
01201                                        } while(0)
01202
01203 #define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
01204                                         __IO uint32_t tmpreg; \
01205                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
01206                                         /* Delay after an RCC peripheral clock enabling */ \
01207                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
01208                                         UNUSED(tmpreg); \
01209                                        } while(0)
01210
01211 #if defined(RCC_AHB2ENR_D2SRAM1EN)
01212 #define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
01213                                         __IO uint32_t tmpreg; \
01214                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
01215                                         /* Delay after an RCC peripheral clock enabling */ \
01216                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
01217                                         UNUSED(tmpreg); \
01218                                        } while(0)
01219 #else
01220 #define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \
01221                                         __IO uint32_t tmpreg; \
01222                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
01223                                         /* Delay after an RCC peripheral clock enabling */ \
01224                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
01225                                         UNUSED(tmpreg); \
01226                                        } while(0)
01227 #endif /* RCC_AHB2ENR_D2SRAM1EN */
01228
01229 #if defined(RCC_AHB2ENR_D2SRAM2EN)
01230 #define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
01231                                         __IO uint32_t tmpreg; \
01232                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
01233                                         /* Delay after an RCC peripheral clock enabling */ \
01234                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
01235                                         UNUSED(tmpreg); \
01236                                        } while(0)
01237 #else
01238 #define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \
01239                                         __IO uint32_t tmpreg; \
01240                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
01241                                         /* Delay after an RCC peripheral clock enabling */ \
01242                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
01243                                         UNUSED(tmpreg); \
01244                                        } while(0)
01245 #endif /* RCC_AHB2ENR_D2SRAM2EN */
01246
01247 #if defined(RCC_AHB2ENR_D2SRAM3EN)
01248 #define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
01249                                         __IO uint32_t tmpreg; \
01250                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
01251                                         /* Delay after an RCC peripheral clock enabling */ \
01252                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
01253                                         UNUSED(tmpreg); \
01254                                        } while(0)
01255 #endif
01256
01257 #if defined(RCC_AHB2ENR_HSEMEN)
01258 #define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
01259                                         __IO uint32_t tmpreg; \
01260                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
01261                                         /* Delay after an RCC peripheral clock enabling */ \
01262                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
01263                                         UNUSED(tmpreg); \
01264                                        } while(0)
01265 #endif /* RCC_AHB2ENR_HSEMEN */
01266
01267 #if defined(BDMA1)
01268 #define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \
01269                                         __IO uint32_t tmpreg; \
01270                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
01271                                         /* Delay after an RCC peripheral clock enabling */ \
01272                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
01273                                         UNUSED(tmpreg); \
01274                                        } while(0)
01275 #endif /* BDMA1 */
01276
01277 #if defined(DCMI) && defined(PSSI)
01278 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
01279 #define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/
01280 #else
01281 #define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
01282 #endif /* DCMI && PSSI */
01283 #define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
01284 #define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
01285 #define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
01286 #define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
01287 #if defined(RCC_AHB2ENR_D2SRAM1EN)
01288 #define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
01289 #else
01290 #define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
01291 #endif /* RCC_AHB2ENR_D2SRAM1EN */
01292 #if defined(RCC_AHB2ENR_D2SRAM2EN)
01293 #define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
01294 #else
01295 #define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
01296 #endif /* RCC_AHB2ENR_D2SRAM2EN */
01297 #if defined(RCC_AHB2ENR_D2SRAM3EN)
01298 #define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
01299 #endif
01300 #if defined(RCC_AHB2ENR_HSEMEN)
01301 #define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
01302 #endif
01303 #if defined(BDMA1)
01304 #define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
01305 #endif
01306
01307 /** @brief  Get the enable or disable status of the AHB2 peripheral clock
01308   * @note   After reset, the peripheral clock (used for registers read/write access)
01309   *         is disabled and the application software has to enable this clock before
01310   *         using it.
01311   */
01312
01313 #if defined(DCMI) && defined(PSSI)
01314 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)
01315 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/
01316 #else
01317 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)
01318 #endif /* DCMI && PSSI */
01319 #define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)
01320 #define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)
01321 #define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)
01322 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)
01323 #if defined(RCC_AHB2ENR_D2SRAM1EN)
01324 #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
01325 #else
01326 #define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
01327 #endif /* RCC_AHB2ENR_D2SRAM1EN */
01328 #if defined(RCC_AHB2ENR_D2SRAM2EN)
01329 #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
01330 #else
01331 #define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
01332 #endif /* RCC_AHB2ENR_D2SRAM2EN */
01333 #if defined(RCC_AHB2ENR_D2SRAM3EN)
01334 #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
01335 #endif
01336 #if defined(RCC_AHB2ENR_HSEMEN)
01337 #define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)
01338 #endif
01339 #if defined(BDMA1)
01340 #define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)
01341 #endif
01342
01343 #if defined(DCMI) && defined(PSSI)
01344 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)
01345 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/
01346 #else
01347 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)
01348 #endif /* DCMI && PSSI */
01349 #define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)
01350 #define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)
01351 #define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)
01352 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)
01353 #if defined(RCC_AHB2ENR_D2SRAM1EN)
01354 #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
01355 #else
01356 #define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
01357 #endif /* RCC_AHB2ENR_D2SRAM1EN */
01358 #if defined(RCC_AHB2ENR_D2SRAM2EN)
01359 #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
01360 #else
01361 #define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
01362 #endif /* RCC_AHB2ENR_D2SRAM2EN */
01363 #if defined(RCC_AHB2ENR_D2SRAM3EN)
01364 #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
01365 #endif
01366 #if defined(RCC_AHB2ENR_HSEMEN)
01367 #define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)
01368 #endif
01369 #if defined(BDMA1)
01370 #define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)
01371 #endif
01372
01373 /** @brief  Enable or disable the AHB4 peripheral clock.
01374   * @note   After reset, the peripheral clock (used for registers read/write access)
01375   *         is disabled and the application software has to enable this clock before
01376   *         using it.
01377   */
01378
01379 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
01380                                         __IO uint32_t tmpreg; \
01381                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
01382                                         /* Delay after an RCC peripheral clock enabling */ \
01383                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
01384                                         UNUSED(tmpreg); \
01385                                        } while(0)
01386
01387 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
01388                                         __IO uint32_t tmpreg; \
01389                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
01390                                         /* Delay after an RCC peripheral clock enabling */ \
01391                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
01392                                         UNUSED(tmpreg); \
01393                                        } while(0)
01394
01395 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
01396                                         __IO uint32_t tmpreg; \
01397                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
01398                                         /* Delay after an RCC peripheral clock enabling */ \
01399                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
01400                                         UNUSED(tmpreg); \
01401                                        } while(0)
01402
01403 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
01404                                         __IO uint32_t tmpreg; \
01405                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
01406                                         /* Delay after an RCC peripheral clock enabling */ \
01407                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
01408                                         UNUSED(tmpreg); \
01409                                        } while(0)
01410
01411 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
01412                                         __IO uint32_t tmpreg; \
01413                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
01414                                         /* Delay after an RCC peripheral clock enabling */ \
01415                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
01416                                         UNUSED(tmpreg); \
01417                                        } while(0)
01418
01419 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
01420                                         __IO uint32_t tmpreg; \
01421                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
01422                                         /* Delay after an RCC peripheral clock enabling */ \
01423                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
01424                                         UNUSED(tmpreg); \
01425                                        } while(0)
01426
01427 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
01428                                         __IO uint32_t tmpreg; \
01429                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
01430                                         /* Delay after an RCC peripheral clock enabling */ \
01431                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
01432                                         UNUSED(tmpreg); \
01433                                        } while(0)
01434
01435 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
01436                                         __IO uint32_t tmpreg; \
01437                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
01438                                         /* Delay after an RCC peripheral clock enabling */ \
01439                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
01440                                         UNUSED(tmpreg); \
01441                                        } while(0)
01442
01443 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
01444                                         __IO uint32_t tmpreg; \
01445                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
01446                                         /* Delay after an RCC peripheral clock enabling */ \
01447                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
01448                                         UNUSED(tmpreg); \
01449                                        } while(0)
01450
01451 #define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
01452                                         __IO uint32_t tmpreg; \
01453                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
01454                                         /* Delay after an RCC peripheral clock enabling */ \
01455                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
01456                                         UNUSED(tmpreg); \
01457                                        } while(0)
01458
01459 #define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
01460                                         __IO uint32_t tmpreg; \
01461                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
01462                                         /* Delay after an RCC peripheral clock enabling */ \
01463                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
01464                                         UNUSED(tmpreg); \
01465                                        } while(0)
01466
01467 #if defined(RCC_AHB4ENR_CRCEN)
01468 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
01469                                         __IO uint32_t tmpreg; \
01470                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
01471                                         /* Delay after an RCC peripheral clock enabling */ \
01472                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
01473                                         UNUSED(tmpreg); \
01474                                        } while(0)
01475 #endif
01476
01477 #if defined(BDMA2)
01478 #define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \
01479                                         __IO uint32_t tmpreg; \
01480                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
01481                                         /* Delay after an RCC peripheral clock enabling */ \
01482                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
01483                                         UNUSED(tmpreg); \
01484                                        } while(0)
01485
01486 #define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/
01487 #else
01488 #define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
01489                                         __IO uint32_t tmpreg; \
01490                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
01491                                         /* Delay after an RCC peripheral clock enabling */ \
01492                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
01493                                         UNUSED(tmpreg); \
01494                                        } while(0)
01495 #endif
01496
01497 #if defined(ADC3)
01498 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
01499                                         __IO uint32_t tmpreg; \
01500                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
01501                                         /* Delay after an RCC peripheral clock enabling */ \
01502                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
01503                                         UNUSED(tmpreg); \
01504                                        } while(0)
01505 #endif
01506
01507 #if defined(RCC_AHB4ENR_HSEMEN)
01508 #define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
01509                                         __IO uint32_t tmpreg; \
01510                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
01511                                         /* Delay after an RCC peripheral clock enabling */ \
01512                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
01513                                         UNUSED(tmpreg); \
01514                                        } while(0)
01515 #endif
01516
01517 #if defined(RCC_AHB4ENR_SRDSRAMEN)
01518 #define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \
01519                                         __IO uint32_t tmpreg; \
01520                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
01521                                         /* Delay after an RCC peripheral clock enabling */ \
01522                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
01523                                         UNUSED(tmpreg); \
01524                                        } while(0)
01525 #endif
01526
01527 #define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
01528                                         __IO uint32_t tmpreg; \
01529                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
01530                                         /* Delay after an RCC peripheral clock enabling */ \
01531                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
01532                                         UNUSED(tmpreg); \
01533                                        } while(0)
01534
01535
01536 #define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
01537 #define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
01538 #define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
01539 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
01540 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
01541 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
01542 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
01543 #define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
01544 #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
01545 #define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
01546 #define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
01547 #if defined(RCC_AHB4ENR_CRCEN)
01548 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
01549 #endif
01550 #if defined(BDMA2)
01551 #define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
01552 #define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/
01553 #else
01554 #define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
01555 #endif
01556 #if defined(ADC3)
01557 #define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
01558 #endif
01559 #if defined(RCC_AHB4ENR_HSEMEN)
01560 #define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
01561 #endif
01562 #if defined(RCC_AHB4ENR_SRDSRAMEN)
01563 #define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
01564 #endif
01565 #define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
01566
01567
01568 /** @brief  Get the enable or disable status of the AHB4 peripheral clock
01569   * @note   After reset, the peripheral clock (used for registers read/write access)
01570   *         is disabled and the application software has to enable this clock before
01571   *         using it.
01572   */
01573
01574 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)
01575 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)
01576 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)
01577 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)
01578 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)
01579 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)
01580 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)
01581 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)
01582 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)
01583 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)
01584 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)
01585 #if defined(RCC_AHB4ENR_CRCEN)
01586 #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)
01587 #endif
01588 #if defined(BDMA2)
01589 #define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)
01590 #define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/
01591 #else
01592 #define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)
01593 #endif
01594 #if defined(ADC3)
01595 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)
01596 #endif
01597 #if defined(RCC_AHB4ENR_HSEMEN)
01598 #define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)
01599 #endif
01600 #if defined(RCC_AHB4ENR_SRDSRAMEN)
01601 #define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
01602 #endif
01603 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
01604
01605 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)
01606 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)
01607 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)
01608 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)
01609 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)
01610 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)
01611 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)
01612 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)
01613 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)
01614 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)
01615 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)
01616
01617 #if defined(RCC_AHB4ENR_CRCEN)
01618 #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)
01619 #endif
01620 #if defined(BDMA2)
01621 #define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)
01622 #define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/
01623 #else
01624 #define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)
01625 #endif
01626 #if defined(ADC3)
01627 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)
01628 #endif
01629 #if defined(RCC_AHB4ENR_HSEMEN)
01630 #define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)
01631 #endif
01632 #if defined(RCC_AHB4ENR_SRDSRAMEN)
01633 #define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)
01634 #endif
01635 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
01636
01637
01638 /** @brief  Enable or disable the APB3 peripheral clock.
01639   * @note   After reset, the peripheral clock (used for registers read/write access)
01640   *         is disabled and the application software has to enable this clock before
01641   *         using it.
01642   */
01643
01644 #if defined(LTDC)
01645 #define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
01646                                         __IO uint32_t tmpreg; \
01647                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
01648                                         /* Delay after an RCC peripheral clock enabling */ \
01649                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
01650                                         UNUSED(tmpreg); \
01651                                        } while(0)
01652 #endif /* LTDC */
01653
01654 #if defined(DSI)
01655 #define __HAL_RCC_DSI_CLK_ENABLE()   do { \
01656                                         __IO uint32_t tmpreg; \
01657                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
01658                                         /* Delay after an RCC peripheral clock enabling */ \
01659                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
01660                                         UNUSED(tmpreg); \
01661                                        } while(0)
01662 #endif /*DSI*/
01663
01664 #define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
01665                                         __IO uint32_t tmpreg; \
01666                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
01667                                         /* Delay after an RCC peripheral clock enabling */ \
01668                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
01669                                         UNUSED(tmpreg); \
01670                                        } while(0)
01671
01672 #if defined(LTDC)
01673 #define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
01674 #endif /* LTDC */
01675 #if defined(DSI)
01676 #define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
01677 #endif /*DSI*/
01678 #define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
01679
01680 /** @brief  Get the enable or disable status of the APB3 peripheral clock
01681   * @note   After reset, the peripheral clock (used for registers read/write access)
01682   *         is disabled and the application software has to enable this clock before
01683   *         using it.
01684   */
01685
01686 #if defined(LTDC)
01687 #define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)
01688 #endif /* LTDC */
01689 #if defined(DSI)
01690 #define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)
01691 #endif /*DSI*/
01692 #define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
01693 #if defined(LTDC)
01694 #define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)
01695 #endif /* LTDC */
01696 #if defined(DSI)
01697 #define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)
01698 #endif /*DSI*/
01699 #define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
01700
01701
01702 /** @brief  Enable or disable the APB1 peripheral clock.
01703   * @note   After reset, the peripheral clock (used for registers read/write access)
01704   *         is disabled and the application software has to enable this clock before
01705   *         using it.
01706   */
01707
01708 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
01709                                         __IO uint32_t tmpreg; \
01710                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
01711                                         /* Delay after an RCC peripheral clock enabling */ \
01712                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
01713                                         UNUSED(tmpreg); \
01714                                        } while(0)
01715
01716 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
01717                                         __IO uint32_t tmpreg; \
01718                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
01719                                         /* Delay after an RCC peripheral clock enabling */ \
01720                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
01721                                         UNUSED(tmpreg); \
01722                                        } while(0)
01723
01724 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
01725                                         __IO uint32_t tmpreg; \
01726                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
01727                                         /* Delay after an RCC peripheral clock enabling */ \
01728                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
01729                                         UNUSED(tmpreg); \
01730                                        } while(0)
01731
01732 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
01733                                         __IO uint32_t tmpreg; \
01734                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
01735                                         /* Delay after an RCC peripheral clock enabling */ \
01736                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
01737                                         UNUSED(tmpreg); \
01738                                        } while(0)
01739
01740 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
01741                                         __IO uint32_t tmpreg; \
01742                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
01743                                         /* Delay after an RCC peripheral clock enabling */ \
01744                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
01745                                         UNUSED(tmpreg); \
01746                                        } while(0)
01747
01748 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
01749                                         __IO uint32_t tmpreg; \
01750                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
01751                                         /* Delay after an RCC peripheral clock enabling */ \
01752                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
01753                                         UNUSED(tmpreg); \
01754                                        } while(0)
01755
01756 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
01757                                         __IO uint32_t tmpreg; \
01758                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
01759                                         /* Delay after an RCC peripheral clock enabling */ \
01760                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
01761                                         UNUSED(tmpreg); \
01762                                        } while(0)
01763
01764 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
01765                                         __IO uint32_t tmpreg; \
01766                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
01767                                         /* Delay after an RCC peripheral clock enabling */ \
01768                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
01769                                         UNUSED(tmpreg); \
01770                                        } while(0)
01771
01772 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
01773                                         __IO uint32_t tmpreg; \
01774                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
01775                                         /* Delay after an RCC peripheral clock enabling */ \
01776                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
01777                                         UNUSED(tmpreg); \
01778                                        } while(0)
01779
01780 #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
01781                                         __IO uint32_t tmpreg; \
01782                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
01783                                         /* Delay after an RCC peripheral clock enabling */ \
01784                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
01785                                         UNUSED(tmpreg); \
01786                                        } while(0)
01787
01788 #if defined(DUAL_CORE)
01789 #define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \
01790                                         __IO uint32_t tmpreg; \
01791                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
01792                                         /* Delay after an RCC peripheral clock enabling */ \
01793                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
01794                                         UNUSED(tmpreg); \
01795                                        } while(0)
01796 #endif /*DUAL_CORE*/
01797
01798 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
01799                                         __IO uint32_t tmpreg; \
01800                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
01801                                         /* Delay after an RCC peripheral clock enabling */ \
01802                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
01803                                         UNUSED(tmpreg); \
01804                                        } while(0)
01805
01806 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
01807                                         __IO uint32_t tmpreg; \
01808                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
01809                                         /* Delay after an RCC peripheral clock enabling */ \
01810                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
01811                                         UNUSED(tmpreg); \
01812                                        } while(0)
01813
01814 #define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
01815                                         __IO uint32_t tmpreg; \
01816                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
01817                                         /* Delay after an RCC peripheral clock enabling */ \
01818                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
01819                                         UNUSED(tmpreg); \
01820                                        } while(0)
01821
01822 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
01823                                         __IO uint32_t tmpreg; \
01824                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
01825                                         /* Delay after an RCC peripheral clock enabling */ \
01826                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
01827                                         UNUSED(tmpreg); \
01828                                        } while(0)
01829
01830 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
01831                                         __IO uint32_t tmpreg; \
01832                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
01833                                         /* Delay after an RCC peripheral clock enabling */ \
01834                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
01835                                         UNUSED(tmpreg); \
01836                                        } while(0)
01837
01838 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
01839                                         __IO uint32_t tmpreg; \
01840                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
01841                                         /* Delay after an RCC peripheral clock enabling */ \
01842                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
01843                                         UNUSED(tmpreg); \
01844                                        } while(0)
01845
01846 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
01847                                         __IO uint32_t tmpreg; \
01848                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
01849                                         /* Delay after an RCC peripheral clock enabling */ \
01850                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
01851                                         UNUSED(tmpreg); \
01852                                        } while(0)
01853
01854 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
01855                                         __IO uint32_t tmpreg; \
01856                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
01857                                         /* Delay after an RCC peripheral clock enabling */ \
01858                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
01859                                         UNUSED(tmpreg); \
01860                                        } while(0)
01861
01862 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
01863                                         __IO uint32_t tmpreg; \
01864                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
01865                                         /* Delay after an RCC peripheral clock enabling */ \
01866                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
01867                                         UNUSED(tmpreg); \
01868                                        } while(0)
01869
01870 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
01871                                         __IO uint32_t tmpreg; \
01872                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
01873                                         /* Delay after an RCC peripheral clock enabling */ \
01874                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
01875                                         UNUSED(tmpreg); \
01876                                        } while(0)
01877
01878 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
01879                                         __IO uint32_t tmpreg; \
01880                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
01881                                         /* Delay after an RCC peripheral clock enabling */ \
01882                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
01883                                         UNUSED(tmpreg); \
01884                                        } while(0)
01885
01886 #define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
01887                                         __IO uint32_t tmpreg; \
01888                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
01889                                         /* Delay after an RCC peripheral clock enabling */ \
01890                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
01891                                         UNUSED(tmpreg); \
01892                                        } while(0)
01893
01894 #define __HAL_RCC_UART7_CLK_ENABLE()   do { \
01895                                         __IO uint32_t tmpreg; \
01896                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
01897                                         /* Delay after an RCC peripheral clock enabling */ \
01898                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
01899                                         UNUSED(tmpreg); \
01900                                        } while(0)
01901
01902 #define __HAL_RCC_UART8_CLK_ENABLE()   do { \
01903                                         __IO uint32_t tmpreg; \
01904                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
01905                                         /* Delay after an RCC peripheral clock enabling */ \
01906                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
01907                                         UNUSED(tmpreg); \
01908                                        } while(0)
01909
01910 #define __HAL_RCC_CRS_CLK_ENABLE()   do { \
01911                                         __IO uint32_t tmpreg; \
01912                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
01913                                         /* Delay after an RCC peripheral clock enabling */ \
01914                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
01915                                         UNUSED(tmpreg); \
01916                                        } while(0)
01917
01918 #define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
01919                                         __IO uint32_t tmpreg; \
01920                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
01921                                         /* Delay after an RCC peripheral clock enabling */ \
01922                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
01923                                         UNUSED(tmpreg); \
01924                                        } while(0)
01925
01926 #define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
01927                                         __IO uint32_t tmpreg; \
01928                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
01929                                         /* Delay after an RCC peripheral clock enabling */ \
01930                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
01931                                         UNUSED(tmpreg); \
01932                                        } while(0)
01933
01934 #define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
01935                                         __IO uint32_t tmpreg; \
01936                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
01937                                         /* Delay after an RCC peripheral clock enabling */ \
01938                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
01939                                         UNUSED(tmpreg); \
01940                                        } while(0)
01941
01942 #define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
01943                                         __IO uint32_t tmpreg; \
01944                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
01945                                         /* Delay after an RCC peripheral clock enabling */ \
01946                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
01947                                         UNUSED(tmpreg); \
01948                                        } while(0)
01949
01950
01951 #define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
01952 #define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
01953 #define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
01954 #define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
01955 #define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
01956 #define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
01957 #define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
01958 #define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
01959 #define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
01960 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
01961
01962 #if defined(DUAL_CORE)
01963 #define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
01964 #endif /*DUAL_CORE*/
01965
01966 #define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
01967 #define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
01968 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
01969 #define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
01970 #define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
01971 #define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
01972 #define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
01973 #define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
01974 #define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
01975 #define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
01976 #define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
01977 #define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
01978 #define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
01979 #define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
01980 #define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
01981 #define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
01982 #define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
01983 #define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
01984 #define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
01985
01986
01987 /** @brief  Get the enable or disable status of the APB1 peripheral clock
01988   * @note   After reset, the peripheral clock (used for registers read/write access)
01989   *         is disabled and the application software has to enable this clock before
01990   *         using it.
01991   */
01992
01993 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)
01994 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)
01995 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)
01996 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)
01997 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)
01998 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)
01999 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)
02000 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)
02001 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)
02002 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)
02003 #if defined(DUAL_CORE)
02004 #define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)
02005 #endif /*DUAL_CORE*/
02006 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)
02007 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)
02008 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
02009 #define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)
02010 #define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)
02011 #define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)
02012 #define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)
02013 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)
02014 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)
02015 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)
02016 #define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)
02017 #define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)
02018 #define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)
02019 #define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)
02020 #define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)
02021 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)
02022 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)
02023 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)
02024 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)
02025
02026 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
02027 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)
02028 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)
02029 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)
02030 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)
02031 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)
02032 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)
02033 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)
02034 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)
02035 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)
02036 #if defined(DUAL_CORE)
02037 #define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)
02038 #endif /*DUAL_CORE*/
02039 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)
02040 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)
02041 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
02042 #define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)
02043 #define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)
02044 #define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)
02045 #define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)
02046 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)
02047 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)
02048 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)
02049 #define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)
02050 #define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)
02051 #define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)
02052 #define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)
02053 #define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)
02054 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)
02055 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)
02056 #define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)
02057 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)
02058
02059
02060 /** @brief  Enable or disable the APB2 peripheral clock.
02061   * @note   After reset, the peripheral clock (used for registers read/write access)
02062   *         is disabled and the application software has to enable this clock before
02063   *         using it.
02064   */
02065
02066 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
02067                                         __IO uint32_t tmpreg; \
02068                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
02069                                         /* Delay after an RCC peripheral clock enabling */ \
02070                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
02071                                         UNUSED(tmpreg); \
02072                                        } while(0)
02073
02074 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
02075                                         __IO uint32_t tmpreg; \
02076                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02077                                         /* Delay after an RCC peripheral clock enabling */ \
02078                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02079                                         UNUSED(tmpreg); \
02080                                        } while(0)
02081
02082 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
02083                                         __IO uint32_t tmpreg; \
02084                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
02085                                         /* Delay after an RCC peripheral clock enabling */ \
02086                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
02087                                         UNUSED(tmpreg); \
02088                                        } while(0)
02089
02090 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
02091                                         __IO uint32_t tmpreg; \
02092                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
02093                                         /* Delay after an RCC peripheral clock enabling */ \
02094                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
02095                                         UNUSED(tmpreg); \
02096                                        } while(0)
02097
02098 #if defined(UART9)
02099 #define __HAL_RCC_UART9_CLK_ENABLE()   do { \
02100                                         __IO uint32_t tmpreg; \
02101                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
02102                                         /* Delay after an RCC peripheral clock enabling */ \
02103                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
02104                                         UNUSED(tmpreg); \
02105                                        } while(0)
02106 #endif /*UART9*/
02107
02108 #if defined(USART10)
02109 #define __HAL_RCC_USART10_CLK_ENABLE()   do { \
02110                                         __IO uint32_t tmpreg; \
02111                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
02112                                         /* Delay after an RCC peripheral clock enabling */ \
02113                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
02114                                         UNUSED(tmpreg); \
02115                                        } while(0)
02116 #endif /*USART10*/
02117
02118 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
02119                                         __IO uint32_t tmpreg; \
02120                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02121                                         /* Delay after an RCC peripheral clock enabling */ \
02122                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
02123                                         UNUSED(tmpreg); \
02124                                        } while(0)
02125
02126 #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
02127                                         __IO uint32_t tmpreg; \
02128                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02129                                         /* Delay after an RCC peripheral clock enabling */ \
02130                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02131                                         UNUSED(tmpreg); \
02132                                        } while(0)
02133
02134 #define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
02135                                         __IO uint32_t tmpreg; \
02136                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
02137                                         /* Delay after an RCC peripheral clock enabling */ \
02138                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
02139                                         UNUSED(tmpreg); \
02140                                        } while(0)
02141
02142 #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
02143                                         __IO uint32_t tmpreg; \
02144                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
02145                                         /* Delay after an RCC peripheral clock enabling */ \
02146                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
02147                                         UNUSED(tmpreg); \
02148                                        } while(0)
02149
02150 #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
02151                                         __IO uint32_t tmpreg; \
02152                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
02153                                         /* Delay after an RCC peripheral clock enabling */ \
02154                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
02155                                         UNUSED(tmpreg); \
02156                                        } while(0)
02157
02158 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
02159                                         __IO uint32_t tmpreg; \
02160                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
02161                                         /* Delay after an RCC peripheral clock enabling */ \
02162                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
02163                                         UNUSED(tmpreg); \
02164                                        } while(0)
02165
02166 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
02167                                         __IO uint32_t tmpreg; \
02168                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
02169                                         /* Delay after an RCC peripheral clock enabling */ \
02170                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
02171                                         UNUSED(tmpreg); \
02172                                        } while(0)
02173
02174 #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
02175                                         __IO uint32_t tmpreg; \
02176                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
02177                                         /* Delay after an RCC peripheral clock enabling */ \
02178                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
02179                                         UNUSED(tmpreg); \
02180                                        } while(0)
02181
02182 #if defined(SAI3)
02183 #define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
02184                                         __IO uint32_t tmpreg; \
02185                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
02186                                         /* Delay after an RCC peripheral clock enabling */ \
02187                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
02188                                         UNUSED(tmpreg); \
02189                                        } while(0)
02190 #endif /*SAI3*/
02191
02192 #define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
02193                                         __IO uint32_t tmpreg; \
02194                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
02195                                         /* Delay after an RCC peripheral clock enabling */ \
02196                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
02197                                         UNUSED(tmpreg); \
02198                                        } while(0)
02199
02200 #if defined(HRTIM1)
02201 #define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
02202                                         __IO uint32_t tmpreg; \
02203                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
02204                                         /* Delay after an RCC peripheral clock enabling */ \
02205                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
02206                                         UNUSED(tmpreg); \
02207                                        } while(0)
02208 #endif /*HRTIM1*/
02209
02210 #define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
02211 #define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
02212 #define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
02213 #define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
02214 #if defined(UART9)
02215 #define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
02216 #endif /*UART9*/
02217 #if defined(USART10)
02218 #define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
02219 #endif /*USART10*/
02220 #define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
02221 #define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
02222 #define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
02223 #define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
02224 #define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
02225 #define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
02226 #define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
02227 #define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
02228 #if defined(SAI3)
02229 #define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
02230 #endif /*SAI3*/
02231 #define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
02232 #if defined(HRTIM1)
02233 #define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
02234 #endif /*HRTIM*/
02235
02236 /** @brief  Get the enable or disable status of the APB2 peripheral clock
02237   * @note   After reset, the peripheral clock (used for registers read/write access)
02238   *         is disabled and the application software has to enable this clock before
02239   *         using it.
02240   */
02241
02242 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)
02243 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)
02244 #define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
02245 #define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
02246 #if defined(UART9)
02247 #define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
02248 #endif /*UART9*/
02249 #if defined(USART10)
02250 #define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
02251 #endif /*USART10*/
02252 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)
02253 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)
02254 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)
02255 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)
02256 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)
02257 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)
02258 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)
02259 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)
02260 #if defined(SAI3)
02261 #define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)
02262 #endif /* SAI3 */
02263 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
02264 #if defined(HRTIM1)
02265 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)
02266 #endif /*HRTIM1*/
02267
02268 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)
02269 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)
02270 #define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
02271 #define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
02272 #if defined(UART9)
02273 #define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
02274 #endif /*UART9*/
02275 #if defined(USART10)
02276 #define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
02277 #endif /*USART10*/
02278 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)
02279 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)
02280 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)
02281 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)
02282 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)
02283 #define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)
02284 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)
02285 #define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)
02286 #if defined(SAI3)
02287 #define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)
02288 #endif /*SAI3*/
02289 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
02290 #if defined(HRTIM1)
02291 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)
02292 #endif /*HRTIM1*/
02293
02294 /** @brief  Enable or disable the APB4 peripheral clock.
02295   * @note   After reset, the peripheral clock (used for registers read/write access)
02296   *         is disabled and the application software has to enable this clock before
02297   *         using it.
02298   */
02299
02300 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
02301                                         __IO uint32_t tmpreg; \
02302                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
02303                                         /* Delay after an RCC peripheral clock enabling */ \
02304                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
02305                                         UNUSED(tmpreg); \
02306                                        } while(0)
02307
02308 #define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
02309                                         __IO uint32_t tmpreg; \
02310                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
02311                                         /* Delay after an RCC peripheral clock enabling */ \
02312                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
02313                                         UNUSED(tmpreg); \
02314                                        } while(0)
02315
02316 #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
02317                                         __IO uint32_t tmpreg; \
02318                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
02319                                         /* Delay after an RCC peripheral clock enabling */ \
02320                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
02321                                         UNUSED(tmpreg); \
02322                                        } while(0)
02323
02324 #define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
02325                                         __IO uint32_t tmpreg; \
02326                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
02327                                         /* Delay after an RCC peripheral clock enabling */ \
02328                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
02329                                         UNUSED(tmpreg); \
02330                                        } while(0)
02331
02332 #define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
02333                                         __IO uint32_t tmpreg; \
02334                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
02335                                         /* Delay after an RCC peripheral clock enabling */ \
02336                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
02337                                         UNUSED(tmpreg); \
02338                                        } while(0)
02339
02340 #define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
02341                                         __IO uint32_t tmpreg; \
02342                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
02343                                         /* Delay after an RCC peripheral clock enabling */ \
02344                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
02345                                         UNUSED(tmpreg); \
02346                                        } while(0)
02347
02348 #if defined(LPTIM4)
02349 #define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
02350                                         __IO uint32_t tmpreg; \
02351                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
02352                                         /* Delay after an RCC peripheral clock enabling */ \
02353                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
02354                                         UNUSED(tmpreg); \
02355                                        } while(0)
02356 #endif /* LPTIM4 */
02357
02358 #if defined(LPTIM5)
02359 #define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
02360                                         __IO uint32_t tmpreg; \
02361                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
02362                                         /* Delay after an RCC peripheral clock enabling */ \
02363                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
02364                                         UNUSED(tmpreg); \
02365                                        } while(0)
02366 #endif /* LPTIM5 */
02367
02368 #if defined(DAC2)
02369 #define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
02370                                         __IO uint32_t tmpreg; \
02371                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
02372                                         /* Delay after an RCC peripheral clock enabling */ \
02373                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
02374                                         UNUSED(tmpreg); \
02375                                        } while(0)
02376 #endif /*  DAC2 */
02377
02378 #define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
02379                                         __IO uint32_t tmpreg; \
02380                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
02381                                         /* Delay after an RCC peripheral clock enabling */ \
02382                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
02383                                         UNUSED(tmpreg); \
02384                                        } while(0)
02385
02386 #define __HAL_RCC_VREF_CLK_ENABLE()   do { \
02387                                         __IO uint32_t tmpreg; \
02388                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
02389                                         /* Delay after an RCC peripheral clock enabling */ \
02390                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
02391                                         UNUSED(tmpreg); \
02392                                        } while(0)
02393
02394 #if defined(SAI4)
02395 #define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
02396                                         __IO uint32_t tmpreg; \
02397                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
02398                                         /* Delay after an RCC peripheral clock enabling */ \
02399                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
02400                                         UNUSED(tmpreg); \
02401                                        } while(0)
02402 #endif /* SAI4 */
02403
02404 #define __HAL_RCC_RTC_CLK_ENABLE()   do { \
02405                                         __IO uint32_t tmpreg; \
02406                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
02407                                         /* Delay after an RCC peripheral clock enabling */ \
02408                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
02409                                         UNUSED(tmpreg); \
02410                                        } while(0)
02411
02412 #if defined(DTS)
02413 #define __HAL_RCC_DTS_CLK_ENABLE()   do { \
02414                                         __IO uint32_t tmpreg; \
02415                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
02416                                         /* Delay after an RCC peripheral clock enabling */ \
02417                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
02418                                         UNUSED(tmpreg); \
02419                                        } while(0)
02420 #endif /*DTS*/
02421
02422 #if defined(DFSDM2_BASE)
02423 #define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \
02424                                         __IO uint32_t tmpreg; \
02425                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
02426                                         /* Delay after an RCC peripheral clock enabling */ \
02427                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
02428                                         UNUSED(tmpreg); \
02429                                        } while(0)
02430 #endif /*DFSDM2*/
02431
02432 #define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
02433 #define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
02434 #define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
02435 #define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
02436 #define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
02437 #define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
02438 #if defined(LPTIM4)
02439 #define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
02440 #endif /*LPTIM4*/
02441 #if defined(LPTIM5)
02442 #define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
02443 #endif /*LPTIM5*/
02444 #if defined(DAC2)
02445 #define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
02446 #endif /*DAC2*/
02447 #define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
02448 #define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
02449 #define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
02450 #if defined(SAI4)
02451 #define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
02452 #endif /*SAI4*/
02453 #if defined(DTS)
02454 #define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
02455 #endif /*DTS*/
02456 #if defined(DFSDM2_BASE)
02457 #define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
02458 #endif /*DFSDM2*/
02459
02460 /** @brief  Get the enable or disable status of the APB4 peripheral clock
02461   * @note   After reset, the peripheral clock (used for registers read/write access)
02462   *         is disabled and the application software has to enable this clock before
02463   *         using it.
02464   */
02465
02466 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)
02467 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
02468 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)
02469 #define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)
02470 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)
02471 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)
02472 #if defined(LPTIM4)
02473 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)
02474 #endif /*LPTIM4*/
02475 #if defined(LPTIM5)
02476 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)
02477 #endif /*LPTIM5*/
02478 #if defined(DAC2)
02479 #define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)
02480 #endif /*DAC2*/
02481 #define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)
02482 #define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)
02483 #define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)
02484 #if defined(SAI4)
02485 #define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)
02486 #endif /*SAI4*/
02487 #if defined(DTS)
02488 #define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)
02489 #endif /*DTS*/
02490 #if defined(DFSDM2_BASE)
02491 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)
02492 #endif /*DFSDM2*/
02493
02494 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)
02495 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
02496 #define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)
02497 #define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)
02498 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)
02499 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)
02500 #if defined(LPTIM4)
02501 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)
02502 #endif /*LPTIM4*/
02503 #if defined(LPTIM5)
02504 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)
02505 #endif /*LPTIM5*/
02506 #if defined(DAC2)
02507 #define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)
02508 #endif /*DAC2*/
02509 #define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)
02510 #define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)
02511 #define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)
02512 #if defined(SAI4)
02513 #define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)
02514 #endif /*SAI4*/
02515 #if defined(DTS)
02516 #define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)
02517 #endif /*DTS*/
02518 #if defined(DFSDM2_BASE)
02519 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)
02520 #endif /*DFSDM2*/
02521
02522 #if defined(DUAL_CORE)
02523
02524 /* Exported macros for RCC_C1 -------------------------------------------------*/
02525
02526 /** @brief  Enable or disable the AHB3 peripheral clock.
02527   * @note   After reset, the peripheral clock (used for registers read/write access)
02528   *         is disabled and the application software has to enable this clock before
02529   *         using it.
02530   */
02531
02532 #define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \
02533                                         __IO uint32_t tmpreg; \
02534                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
02535                                         /* Delay after an RCC peripheral clock enabling */ \
02536                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
02537                                         UNUSED(tmpreg); \
02538                                        } while(0)
02539
02540 #define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \
02541                                         __IO uint32_t tmpreg; \
02542                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
02543                                         /* Delay after an RCC peripheral clock enabling */ \
02544                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
02545                                         UNUSED(tmpreg); \
02546                                        } while(0)
02547
02548 #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \
02549                                         __IO uint32_t tmpreg; \
02550                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
02551                                         /* Delay after an RCC peripheral clock enabling */ \
02552                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
02553                                         UNUSED(tmpreg); \
02554                                        } while(0)
02555
02556
02557 #define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \
02558                                         __IO uint32_t tmpreg; \
02559                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
02560                                         /* Delay after an RCC peripheral clock enabling */ \
02561                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
02562                                         UNUSED(tmpreg); \
02563                                        } while(0)
02564
02565 #define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \
02566                                         __IO uint32_t tmpreg; \
02567                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
02568                                         /* Delay after an RCC peripheral clock enabling */ \
02569                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
02570                                         UNUSED(tmpreg); \
02571                                        } while(0)
02572
02573 #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \
02574                                         __IO uint32_t tmpreg; \
02575                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
02576                                         /* Delay after an RCC peripheral clock enabling */ \
02577                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
02578                                         UNUSED(tmpreg); \
02579                                        } while(0)
02580
02581
02582
02583
02584 #define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
02585 #define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
02586 #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
02587 #define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
02588 #define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
02589 #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
02590
02591
02592
02593
02594 /** @brief  Enable or disable the AHB1 peripheral clock.
02595   * @note   After reset, the peripheral clock (used for registers read/write access)
02596   *         is disabled and the application software has to enable this clock before
02597   *         using it.
02598   */
02599
02600 #define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \
02601                                         __IO uint32_t tmpreg; \
02602                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
02603                                         /* Delay after an RCC peripheral clock enabling */ \
02604                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
02605                                         UNUSED(tmpreg); \
02606                                        } while(0)
02607
02608 #define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \
02609                                         __IO uint32_t tmpreg; \
02610                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
02611                                         /* Delay after an RCC peripheral clock enabling */ \
02612                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
02613                                         UNUSED(tmpreg); \
02614                                        } while(0)
02615
02616 #define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \
02617                                         __IO uint32_t tmpreg; \
02618                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
02619                                         /* Delay after an RCC peripheral clock enabling */ \
02620                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
02621                                         UNUSED(tmpreg); \
02622                                        } while(0)
02623
02624 #define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \
02625                                         __IO uint32_t tmpreg; \
02626                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
02627                                         /* Delay after an RCC peripheral clock enabling */ \
02628                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
02629                                         UNUSED(tmpreg); \
02630                                        } while(0)
02631
02632 #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \
02633                                         __IO uint32_t tmpreg; \
02634                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
02635                                         /* Delay after an RCC peripheral clock enabling */ \
02636                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
02637                                         UNUSED(tmpreg); \
02638                                        } while(0)
02639
02640 #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \
02641                                         __IO uint32_t tmpreg; \
02642                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
02643                                         /* Delay after an RCC peripheral clock enabling */ \
02644                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
02645                                         UNUSED(tmpreg); \
02646                                        } while(0)
02647
02648 #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \
02649                                         __IO uint32_t tmpreg; \
02650                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
02651                                         /* Delay after an RCC peripheral clock enabling */ \
02652                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
02653                                         UNUSED(tmpreg); \
02654                                        } while(0)
02655
02656
02657 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \
02658                                         __IO uint32_t tmpreg; \
02659                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
02660                                         /* Delay after an RCC peripheral clock enabling */ \
02661                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
02662                                         UNUSED(tmpreg); \
02663                                        } while(0)
02664
02665 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
02666                                         __IO uint32_t tmpreg; \
02667                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
02668                                         /* Delay after an RCC peripheral clock enabling */ \
02669                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
02670                                         UNUSED(tmpreg); \
02671                                        } while(0)
02672
02673 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \
02674                                         __IO uint32_t tmpreg; \
02675                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
02676                                         /* Delay after an RCC peripheral clock enabling */ \
02677                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
02678                                         UNUSED(tmpreg); \
02679                                        } while(0)
02680
02681 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
02682                                         __IO uint32_t tmpreg; \
02683                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
02684                                         /* Delay after an RCC peripheral clock enabling */ \
02685                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
02686                                         UNUSED(tmpreg); \
02687                                        } while(0)
02688
02689 #define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
02690 #define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
02691 #define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
02692 #define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
02693 #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
02694 #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
02695 #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
02696 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
02697 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
02698 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
02699 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
02700
02701 /** @brief  Enable or disable the AHB2 peripheral clock.
02702   * @note   After reset, the peripheral clock (used for registers read/write access)
02703   *         is disabled and the application software has to enable this clock before
02704   *         using it.
02705   */
02706
02707 #define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \
02708                                         __IO uint32_t tmpreg; \
02709                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
02710                                         /* Delay after an RCC peripheral clock enabling */ \
02711                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
02712                                         UNUSED(tmpreg); \
02713                                        } while(0)
02714
02715 #define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \
02716                                         __IO uint32_t tmpreg; \
02717                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
02718                                         /* Delay after an RCC peripheral clock enabling */ \
02719                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
02720                                         UNUSED(tmpreg); \
02721                                        } while(0)
02722
02723 #define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \
02724                                         __IO uint32_t tmpreg; \
02725                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
02726                                         /* Delay after an RCC peripheral clock enabling */ \
02727                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
02728                                         UNUSED(tmpreg); \
02729                                        } while(0)
02730
02731 #define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \
02732                                         __IO uint32_t tmpreg; \
02733                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
02734                                         /* Delay after an RCC peripheral clock enabling */ \
02735                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
02736                                         UNUSED(tmpreg); \
02737                                        } while(0)
02738
02739 #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \
02740                                         __IO uint32_t tmpreg; \
02741                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
02742                                         /* Delay after an RCC peripheral clock enabling */ \
02743                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
02744                                         UNUSED(tmpreg); \
02745                                        } while(0)
02746
02747 #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \
02748                                         __IO uint32_t tmpreg; \
02749                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
02750                                         /* Delay after an RCC peripheral clock enabling */ \
02751                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
02752                                         UNUSED(tmpreg); \
02753                                        } while(0)
02754
02755 #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \
02756                                         __IO uint32_t tmpreg; \
02757                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
02758                                         /* Delay after an RCC peripheral clock enabling */ \
02759                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
02760                                         UNUSED(tmpreg); \
02761                                        } while(0)
02762
02763 #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \
02764                                         __IO uint32_t tmpreg; \
02765                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
02766                                         /* Delay after an RCC peripheral clock enabling */ \
02767                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
02768                                         UNUSED(tmpreg); \
02769                                        } while(0)
02770
02771 #define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
02772 #define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
02773 #define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
02774 #define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
02775 #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
02776 #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
02777 #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
02778 #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
02779
02780 /** @brief  Enable or disable the AHB4 peripheral clock.
02781   * @note   After reset, the peripheral clock (used for registers read/write access)
02782   *         is disabled and the application software has to enable this clock before
02783   *         using it.
02784   */
02785
02786 #define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \
02787                                         __IO uint32_t tmpreg; \
02788                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
02789                                         /* Delay after an RCC peripheral clock enabling */ \
02790                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
02791                                         UNUSED(tmpreg); \
02792                                        } while(0)
02793
02794 #define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \
02795                                         __IO uint32_t tmpreg; \
02796                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
02797                                         /* Delay after an RCC peripheral clock enabling */ \
02798                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
02799                                         UNUSED(tmpreg); \
02800                                        } while(0)
02801
02802 #define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \
02803                                         __IO uint32_t tmpreg; \
02804                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
02805                                         /* Delay after an RCC peripheral clock enabling */ \
02806                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
02807                                         UNUSED(tmpreg); \
02808                                        } while(0)
02809
02810 #define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \
02811                                         __IO uint32_t tmpreg; \
02812                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
02813                                         /* Delay after an RCC peripheral clock enabling */ \
02814                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
02815                                         UNUSED(tmpreg); \
02816                                        } while(0)
02817
02818 #define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \
02819                                         __IO uint32_t tmpreg; \
02820                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
02821                                         /* Delay after an RCC peripheral clock enabling */ \
02822                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
02823                                         UNUSED(tmpreg); \
02824                                        } while(0)
02825
02826 #define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \
02827                                         __IO uint32_t tmpreg; \
02828                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
02829                                         /* Delay after an RCC peripheral clock enabling */ \
02830                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
02831                                         UNUSED(tmpreg); \
02832                                        } while(0)
02833
02834 #define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \
02835                                         __IO uint32_t tmpreg; \
02836                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
02837                                         /* Delay after an RCC peripheral clock enabling */ \
02838                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
02839                                         UNUSED(tmpreg); \
02840                                        } while(0)
02841
02842 #define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \
02843                                         __IO uint32_t tmpreg; \
02844                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
02845                                         /* Delay after an RCC peripheral clock enabling */ \
02846                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
02847                                         UNUSED(tmpreg); \
02848                                        } while(0)
02849
02850 #define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \
02851                                         __IO uint32_t tmpreg; \
02852                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
02853                                         /* Delay after an RCC peripheral clock enabling */ \
02854                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
02855                                         UNUSED(tmpreg); \
02856                                        } while(0)
02857
02858 #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \
02859                                         __IO uint32_t tmpreg; \
02860                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
02861                                         /* Delay after an RCC peripheral clock enabling */ \
02862                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
02863                                         UNUSED(tmpreg); \
02864                                        } while(0)
02865
02866 #define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \
02867                                         __IO uint32_t tmpreg; \
02868                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
02869                                         /* Delay after an RCC peripheral clock enabling */ \
02870                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
02871                                         UNUSED(tmpreg); \
02872                                        } while(0)
02873
02874 #define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \
02875                                         __IO uint32_t tmpreg; \
02876                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
02877                                         /* Delay after an RCC peripheral clock enabling */ \
02878                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
02879                                         UNUSED(tmpreg); \
02880                                        } while(0)
02881
02882 #define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \
02883                                         __IO uint32_t tmpreg; \
02884                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
02885                                         /* Delay after an RCC peripheral clock enabling */ \
02886                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
02887                                         UNUSED(tmpreg); \
02888                                        } while(0)
02889
02890 #define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \
02891                                         __IO uint32_t tmpreg; \
02892                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
02893                                         /* Delay after an RCC peripheral clock enabling */ \
02894                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
02895                                         UNUSED(tmpreg); \
02896                                        } while(0)
02897
02898 #define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \
02899                                         __IO uint32_t tmpreg; \
02900                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
02901                                         /* Delay after an RCC peripheral clock enabling */ \
02902                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
02903                                         UNUSED(tmpreg); \
02904                                        } while(0)
02905
02906 #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \
02907                                         __IO uint32_t tmpreg; \
02908                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
02909                                         /* Delay after an RCC peripheral clock enabling */ \
02910                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
02911                                         UNUSED(tmpreg); \
02912                                        } while(0)
02913
02914
02915 #define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
02916 #define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
02917 #define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
02918 #define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
02919 #define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
02920 #define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
02921 #define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
02922 #define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
02923 #define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
02924 #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
02925 #define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
02926 #define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
02927 #define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
02928 #define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
02929 #define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
02930 #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
02931
02932
02933 /** @brief  Enable or disable the APB3 peripheral clock.
02934   * @note   After reset, the peripheral clock (used for registers read/write access)
02935   *         is disabled and the application software has to enable this clock before
02936   *         using it.
02937   */
02938
02939 #define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \
02940                                         __IO uint32_t tmpreg; \
02941                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
02942                                         /* Delay after an RCC peripheral clock enabling */ \
02943                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
02944                                         UNUSED(tmpreg); \
02945                                        } while(0)
02946
02947 #define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \
02948                                         __IO uint32_t tmpreg; \
02949                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
02950                                         /* Delay after an RCC peripheral clock enabling */ \
02951                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
02952                                         UNUSED(tmpreg); \
02953                                        } while(0)
02954
02955 #define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \
02956                                         __IO uint32_t tmpreg; \
02957                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
02958                                         /* Delay after an RCC peripheral clock enabling */ \
02959                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
02960                                         UNUSED(tmpreg); \
02961                                        } while(0)
02962
02963 #define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
02964 #define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
02965 #define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
02966
02967 /** @brief  Enable or disable the APB1 peripheral clock.
02968   * @note   After reset, the peripheral clock (used for registers read/write access)
02969   *         is disabled and the application software has to enable this clock before
02970   *         using it.
02971   */
02972
02973 #define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \
02974                                         __IO uint32_t tmpreg; \
02975                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
02976                                         /* Delay after an RCC peripheral clock enabling */ \
02977                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
02978                                         UNUSED(tmpreg); \
02979                                        } while(0)
02980
02981 #define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \
02982                                         __IO uint32_t tmpreg; \
02983                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
02984                                         /* Delay after an RCC peripheral clock enabling */ \
02985                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
02986                                         UNUSED(tmpreg); \
02987                                        } while(0)
02988
02989 #define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \
02990                                         __IO uint32_t tmpreg; \
02991                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
02992                                         /* Delay after an RCC peripheral clock enabling */ \
02993                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
02994                                         UNUSED(tmpreg); \
02995                                        } while(0)
02996
02997 #define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \
02998                                         __IO uint32_t tmpreg; \
02999                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
03000                                         /* Delay after an RCC peripheral clock enabling */ \
03001                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
03002                                         UNUSED(tmpreg); \
03003                                        } while(0)
03004
03005 #define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \
03006                                         __IO uint32_t tmpreg; \
03007                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
03008                                         /* Delay after an RCC peripheral clock enabling */ \
03009                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
03010                                         UNUSED(tmpreg); \
03011                                        } while(0)
03012
03013 #define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \
03014                                         __IO uint32_t tmpreg; \
03015                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
03016                                         /* Delay after an RCC peripheral clock enabling */ \
03017                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
03018                                         UNUSED(tmpreg); \
03019                                        } while(0)
03020
03021 #define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \
03022                                         __IO uint32_t tmpreg; \
03023                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
03024                                         /* Delay after an RCC peripheral clock enabling */ \
03025                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
03026                                         UNUSED(tmpreg); \
03027                                        } while(0)
03028
03029 #define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \
03030                                         __IO uint32_t tmpreg; \
03031                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
03032                                         /* Delay after an RCC peripheral clock enabling */ \
03033                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
03034                                         UNUSED(tmpreg); \
03035                                        } while(0)
03036
03037 #define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \
03038                                         __IO uint32_t tmpreg; \
03039                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
03040                                         /* Delay after an RCC peripheral clock enabling */ \
03041                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
03042                                         UNUSED(tmpreg); \
03043                                        } while(0)
03044
03045 #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \
03046                                         __IO uint32_t tmpreg; \
03047                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
03048                                         /* Delay after an RCC peripheral clock enabling */ \
03049                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
03050                                         UNUSED(tmpreg); \
03051                                        } while(0)
03052
03053 #define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \
03054                                         __IO uint32_t tmpreg; \
03055                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
03056                                         /* Delay after an RCC peripheral clock enabling */ \
03057                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
03058                                         UNUSED(tmpreg); \
03059                                        } while(0)
03060
03061 #define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \
03062                                         __IO uint32_t tmpreg; \
03063                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
03064                                         /* Delay after an RCC peripheral clock enabling */ \
03065                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
03066                                         UNUSED(tmpreg); \
03067                                        } while(0)
03068
03069 #define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \
03070                                         __IO uint32_t tmpreg; \
03071                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
03072                                         /* Delay after an RCC peripheral clock enabling */ \
03073                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
03074                                         UNUSED(tmpreg); \
03075                                        } while(0)
03076
03077 #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \
03078                                         __IO uint32_t tmpreg; \
03079                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
03080                                         /* Delay after an RCC peripheral clock enabling */ \
03081                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
03082                                         UNUSED(tmpreg); \
03083                                        } while(0)
03084
03085 #define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \
03086                                         __IO uint32_t tmpreg; \
03087                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
03088                                         /* Delay after an RCC peripheral clock enabling */ \
03089                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
03090                                         UNUSED(tmpreg); \
03091                                        } while(0)
03092
03093 #define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \
03094                                         __IO uint32_t tmpreg; \
03095                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
03096                                         /* Delay after an RCC peripheral clock enabling */ \
03097                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
03098                                         UNUSED(tmpreg); \
03099                                        } while(0)
03100
03101 #define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \
03102                                         __IO uint32_t tmpreg; \
03103                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
03104                                         /* Delay after an RCC peripheral clock enabling */ \
03105                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
03106                                         UNUSED(tmpreg); \
03107                                        } while(0)
03108
03109 #define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \
03110                                         __IO uint32_t tmpreg; \
03111                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
03112                                         /* Delay after an RCC peripheral clock enabling */ \
03113                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
03114                                         UNUSED(tmpreg); \
03115                                        } while(0)
03116
03117 #define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \
03118                                         __IO uint32_t tmpreg; \
03119                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
03120                                         /* Delay after an RCC peripheral clock enabling */ \
03121                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
03122                                         UNUSED(tmpreg); \
03123                                        } while(0)
03124
03125 #define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \
03126                                         __IO uint32_t tmpreg; \
03127                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
03128                                         /* Delay after an RCC peripheral clock enabling */ \
03129                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
03130                                         UNUSED(tmpreg); \
03131                                        } while(0)
03132
03133 #define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \
03134                                         __IO uint32_t tmpreg; \
03135                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
03136                                         /* Delay after an RCC peripheral clock enabling */ \
03137                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
03138                                         UNUSED(tmpreg); \
03139                                        } while(0)
03140
03141 #define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \
03142                                         __IO uint32_t tmpreg; \
03143                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
03144                                         /* Delay after an RCC peripheral clock enabling */ \
03145                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
03146                                         UNUSED(tmpreg); \
03147                                        } while(0)
03148
03149 #define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \
03150                                         __IO uint32_t tmpreg; \
03151                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
03152                                         /* Delay after an RCC peripheral clock enabling */ \
03153                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
03154                                         UNUSED(tmpreg); \
03155                                        } while(0)
03156
03157 #define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \
03158                                         __IO uint32_t tmpreg; \
03159                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
03160                                         /* Delay after an RCC peripheral clock enabling */ \
03161                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
03162                                         UNUSED(tmpreg); \
03163                                        } while(0)
03164
03165 #define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \
03166                                         __IO uint32_t tmpreg; \
03167                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
03168                                         /* Delay after an RCC peripheral clock enabling */ \
03169                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
03170                                         UNUSED(tmpreg); \
03171                                        } while(0)
03172
03173 #define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \
03174                                         __IO uint32_t tmpreg; \
03175                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
03176                                         /* Delay after an RCC peripheral clock enabling */ \
03177                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
03178                                         UNUSED(tmpreg); \
03179                                        } while(0)
03180
03181 #define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \
03182                                         __IO uint32_t tmpreg; \
03183                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
03184                                         /* Delay after an RCC peripheral clock enabling */ \
03185                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
03186                                         UNUSED(tmpreg); \
03187                                        } while(0)
03188
03189 #define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \
03190                                         __IO uint32_t tmpreg; \
03191                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
03192                                         /* Delay after an RCC peripheral clock enabling */ \
03193                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
03194                                         UNUSED(tmpreg); \
03195                                        } while(0)
03196
03197 #define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \
03198                                         __IO uint32_t tmpreg; \
03199                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
03200                                         /* Delay after an RCC peripheral clock enabling */ \
03201                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
03202                                         UNUSED(tmpreg); \
03203                                        } while(0)
03204
03205 #define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \
03206                                         __IO uint32_t tmpreg; \
03207                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
03208                                         /* Delay after an RCC peripheral clock enabling */ \
03209                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
03210                                         UNUSED(tmpreg); \
03211                                        } while(0)
03212
03213
03214 #define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
03215 #define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
03216 #define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
03217 #define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
03218 #define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
03219 #define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
03220 #define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
03221 #define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
03222 #define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
03223 #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
03224 #define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
03225 #define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
03226 #define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
03227 #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
03228 #define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
03229 #define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
03230 #define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
03231 #define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
03232 #define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
03233 #define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
03234 #define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
03235 #define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
03236 #define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
03237 #define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
03238 #define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
03239 #define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
03240 #define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
03241 #define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
03242 #define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
03243 #define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
03244
03245 /** @brief  Enable or disable the APB2 peripheral clock.
03246   * @note   After reset, the peripheral clock (used for registers read/write access)
03247   *         is disabled and the application software has to enable this clock before
03248   *         using it.
03249   */
03250
03251 #define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \
03252                                         __IO uint32_t tmpreg; \
03253                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
03254                                         /* Delay after an RCC peripheral clock enabling */ \
03255                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
03256                                         UNUSED(tmpreg); \
03257                                        } while(0)
03258
03259 #define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \
03260                                         __IO uint32_t tmpreg; \
03261                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
03262                                         /* Delay after an RCC peripheral clock enabling */ \
03263                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
03264                                         UNUSED(tmpreg); \
03265                                        } while(0)
03266
03267 #define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \
03268                                         __IO uint32_t tmpreg; \
03269                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
03270                                         /* Delay after an RCC peripheral clock enabling */ \
03271                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
03272                                         UNUSED(tmpreg); \
03273                                        } while(0)
03274
03275 #define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \
03276                                         __IO uint32_t tmpreg; \
03277                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
03278                                         /* Delay after an RCC peripheral clock enabling */ \
03279                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
03280                                         UNUSED(tmpreg); \
03281                                        } while(0)
03282
03283 #define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \
03284                                         __IO uint32_t tmpreg; \
03285                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
03286                                         /* Delay after an RCC peripheral clock enabling */ \
03287                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
03288                                         UNUSED(tmpreg); \
03289                                        } while(0)
03290
03291 #define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \
03292                                         __IO uint32_t tmpreg; \
03293                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
03294                                         /* Delay after an RCC peripheral clock enabling */ \
03295                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
03296                                         UNUSED(tmpreg); \
03297                                        } while(0)
03298
03299 #define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \
03300                                         __IO uint32_t tmpreg; \
03301                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
03302                                         /* Delay after an RCC peripheral clock enabling */ \
03303                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
03304                                         UNUSED(tmpreg); \
03305                                        } while(0)
03306
03307 #define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \
03308                                         __IO uint32_t tmpreg; \
03309                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
03310                                         /* Delay after an RCC peripheral clock enabling */ \
03311                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
03312                                         UNUSED(tmpreg); \
03313                                        } while(0)
03314
03315 #define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \
03316                                         __IO uint32_t tmpreg; \
03317                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
03318                                         /* Delay after an RCC peripheral clock enabling */ \
03319                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
03320                                         UNUSED(tmpreg); \
03321                                        } while(0)
03322
03323 #define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \
03324                                         __IO uint32_t tmpreg; \
03325                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
03326                                         /* Delay after an RCC peripheral clock enabling */ \
03327                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
03328                                         UNUSED(tmpreg); \
03329                                        } while(0)
03330
03331 #define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \
03332                                         __IO uint32_t tmpreg; \
03333                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
03334                                         /* Delay after an RCC peripheral clock enabling */ \
03335                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
03336                                         UNUSED(tmpreg); \
03337                                        } while(0)
03338
03339 #define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \
03340                                         __IO uint32_t tmpreg; \
03341                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
03342                                         /* Delay after an RCC peripheral clock enabling */ \
03343                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
03344                                         UNUSED(tmpreg); \
03345                                        } while(0)
03346
03347 #define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \
03348                                         __IO uint32_t tmpreg; \
03349                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
03350                                         /* Delay after an RCC peripheral clock enabling */ \
03351                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
03352                                         UNUSED(tmpreg); \
03353                                        } while(0)
03354
03355 #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \
03356                                         __IO uint32_t tmpreg; \
03357                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
03358                                         /* Delay after an RCC peripheral clock enabling */ \
03359                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
03360                                         UNUSED(tmpreg); \
03361                                        } while(0)
03362
03363 #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \
03364                                         __IO uint32_t tmpreg; \
03365                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
03366                                         /* Delay after an RCC peripheral clock enabling */ \
03367                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
03368                                         UNUSED(tmpreg); \
03369                                        } while(0)
03370
03371 #define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
03372 #define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
03373 #define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
03374 #define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
03375 #define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
03376 #define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
03377 #define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
03378 #define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
03379 #define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
03380 #define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
03381 #define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
03382 #define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
03383 #define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
03384 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
03385 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
03386
03387 /** @brief  Enable or disable the APB4 peripheral clock.
03388   * @note   After reset, the peripheral clock (used for registers read/write access)
03389   *         is disabled and the application software has to enable this clock before
03390   *         using it.
03391   */
03392
03393 #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \
03394                                         __IO uint32_t tmpreg; \
03395                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
03396                                         /* Delay after an RCC peripheral clock enabling */ \
03397                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
03398                                         UNUSED(tmpreg); \
03399                                        } while(0)
03400
03401 #define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \
03402                                         __IO uint32_t tmpreg; \
03403                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
03404                                         /* Delay after an RCC peripheral clock enabling */ \
03405                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
03406                                         UNUSED(tmpreg); \
03407                                        } while(0)
03408
03409 #define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \
03410                                         __IO uint32_t tmpreg; \
03411                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
03412                                         /* Delay after an RCC peripheral clock enabling */ \
03413                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
03414                                         UNUSED(tmpreg); \
03415                                        } while(0)
03416
03417 #define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \
03418                                         __IO uint32_t tmpreg; \
03419                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
03420                                         /* Delay after an RCC peripheral clock enabling */ \
03421                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
03422                                         UNUSED(tmpreg); \
03423                                        } while(0)
03424
03425 #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \
03426                                         __IO uint32_t tmpreg; \
03427                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
03428                                         /* Delay after an RCC peripheral clock enabling */ \
03429                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
03430                                         UNUSED(tmpreg); \
03431                                        } while(0)
03432
03433 #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \
03434                                         __IO uint32_t tmpreg; \
03435                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
03436                                         /* Delay after an RCC peripheral clock enabling */ \
03437                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
03438                                         UNUSED(tmpreg); \
03439                                        } while(0)
03440
03441 #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \
03442                                         __IO uint32_t tmpreg; \
03443                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
03444                                         /* Delay after an RCC peripheral clock enabling */ \
03445                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
03446                                         UNUSED(tmpreg); \
03447                                        } while(0)
03448
03449 #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \
03450                                         __IO uint32_t tmpreg; \
03451                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
03452                                         /* Delay after an RCC peripheral clock enabling */ \
03453                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
03454                                         UNUSED(tmpreg); \
03455                                        } while(0)
03456
03457 #define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \
03458                                         __IO uint32_t tmpreg; \
03459                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
03460                                         /* Delay after an RCC peripheral clock enabling */ \
03461                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
03462                                         UNUSED(tmpreg); \
03463                                        } while(0)
03464
03465
03466 #define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \
03467                                         __IO uint32_t tmpreg; \
03468                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
03469                                         /* Delay after an RCC peripheral clock enabling */ \
03470                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
03471                                         UNUSED(tmpreg); \
03472                                        } while(0)
03473
03474 #define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \
03475                                         __IO uint32_t tmpreg; \
03476                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
03477                                         /* Delay after an RCC peripheral clock enabling */ \
03478                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
03479                                         UNUSED(tmpreg); \
03480                                        } while(0)
03481
03482 #define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \
03483                                         __IO uint32_t tmpreg; \
03484                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
03485                                         /* Delay after an RCC peripheral clock enabling */ \
03486                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
03487                                         UNUSED(tmpreg); \
03488                                        } while(0)
03489
03490
03491 #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
03492 #define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
03493 #define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
03494 #define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
03495 #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
03496 #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
03497 #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
03498 #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
03499 #define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
03500 #define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
03501 #define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
03502 #define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
03503
03504 /* Exported macros for RCC_C2 -------------------------------------------------*/
03505
03506 /** @brief  Enable or disable the AHB3 peripheral clock.
03507   * @note   After reset, the peripheral clock (used for registers read/write access)
03508   *         is disabled and the application software has to enable this clock before
03509   *         using it.
03510   */
03511
03512
03513 #define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \
03514                                         __IO uint32_t tmpreg; \
03515                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
03516                                         /* Delay after an RCC peripheral clock enabling */ \
03517                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
03518                                         UNUSED(tmpreg); \
03519                                        } while(0)
03520
03521 #define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \
03522                                         __IO uint32_t tmpreg; \
03523                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
03524                                         /* Delay after an RCC peripheral clock enabling */ \
03525                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
03526                                         UNUSED(tmpreg); \
03527                                        } while(0)
03528
03529 #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \
03530                                         __IO uint32_t tmpreg; \
03531                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
03532                                         /* Delay after an RCC peripheral clock enabling */ \
03533                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
03534                                         UNUSED(tmpreg); \
03535                                        } while(0)
03536
03537 #define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \
03538                                         __IO uint32_t tmpreg; \
03539                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
03540                                         /* Delay after an RCC peripheral clock enabling */ \
03541                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
03542                                         UNUSED(tmpreg); \
03543                                        } while(0)
03544
03545 #define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \
03546                                         __IO uint32_t tmpreg; \
03547                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
03548                                         /* Delay after an RCC peripheral clock enabling */ \
03549                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
03550                                         UNUSED(tmpreg); \
03551                                        } while(0)
03552
03553 #define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \
03554                                         __IO uint32_t tmpreg; \
03555                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
03556                                         /* Delay after an RCC peripheral clock enabling */ \
03557                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
03558                                         UNUSED(tmpreg); \
03559                                        } while(0)
03560
03561 #define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \
03562                                         __IO uint32_t tmpreg; \
03563                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
03564                                         /* Delay after an RCC peripheral clock enabling */ \
03565                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
03566                                         UNUSED(tmpreg); \
03567                                        } while(0)
03568
03569 #define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \
03570                                         __IO uint32_t tmpreg; \
03571                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
03572                                         /* Delay after an RCC peripheral clock enabling */ \
03573                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
03574                                         UNUSED(tmpreg); \
03575                                        } while(0)
03576
03577 #define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \
03578                                         __IO uint32_t tmpreg; \
03579                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
03580                                         /* Delay after an RCC peripheral clock enabling */ \
03581                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
03582                                         UNUSED(tmpreg); \
03583                                        } while(0)
03584
03585 #define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \
03586                                         __IO uint32_t tmpreg; \
03587                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
03588                                         /* Delay after an RCC peripheral clock enabling */ \
03589                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
03590                                         UNUSED(tmpreg); \
03591                                        } while(0)
03592
03593 #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \
03594                                         __IO uint32_t tmpreg; \
03595                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
03596                                         /* Delay after an RCC peripheral clock enabling */ \
03597                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
03598                                         UNUSED(tmpreg); \
03599                                        } while(0)
03600
03601
03602
03603
03604 #define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
03605 #define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
03606 #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
03607 #define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
03608 #define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
03609 #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
03610 #define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
03611 #define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
03612 #define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
03613 #define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
03614 #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
03615
03616 /** @brief  Enable or disable the AHB1 peripheral clock.
03617   * @note   After reset, the peripheral clock (used for registers read/write access)
03618   *         is disabled and the application software has to enable this clock before
03619   *         using it.
03620   */
03621
03622 #define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \
03623                                         __IO uint32_t tmpreg; \
03624                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
03625                                         /* Delay after an RCC peripheral clock enabling */ \
03626                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
03627                                         UNUSED(tmpreg); \
03628                                        } while(0)
03629
03630 #define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \
03631                                         __IO uint32_t tmpreg; \
03632                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
03633                                         /* Delay after an RCC peripheral clock enabling */ \
03634                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
03635                                         UNUSED(tmpreg); \
03636                                        } while(0)
03637
03638 #define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \
03639                                         __IO uint32_t tmpreg; \
03640                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
03641                                         /* Delay after an RCC peripheral clock enabling */ \
03642                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
03643                                         UNUSED(tmpreg); \
03644                                        } while(0)
03645
03646 #define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \
03647                                         __IO uint32_t tmpreg; \
03648                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
03649                                         /* Delay after an RCC peripheral clock enabling */ \
03650                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
03651                                         UNUSED(tmpreg); \
03652                                        } while(0)
03653
03654 #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \
03655                                         __IO uint32_t tmpreg; \
03656                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
03657                                         /* Delay after an RCC peripheral clock enabling */ \
03658                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
03659                                         UNUSED(tmpreg); \
03660                                        } while(0)
03661
03662 #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \
03663                                         __IO uint32_t tmpreg; \
03664                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
03665                                         /* Delay after an RCC peripheral clock enabling */ \
03666                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
03667                                         UNUSED(tmpreg); \
03668                                        } while(0)
03669
03670 #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \
03671                                         __IO uint32_t tmpreg; \
03672                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
03673                                         /* Delay after an RCC peripheral clock enabling */ \
03674                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
03675                                         UNUSED(tmpreg); \
03676                                        } while(0)
03677
03678 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \
03679                                         __IO uint32_t tmpreg; \
03680                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
03681                                         /* Delay after an RCC peripheral clock enabling */ \
03682                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
03683                                         UNUSED(tmpreg); \
03684                                        } while(0)
03685
03686 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
03687                                         __IO uint32_t tmpreg; \
03688                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
03689                                         /* Delay after an RCC peripheral clock enabling */ \
03690                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
03691                                         UNUSED(tmpreg); \
03692                                        } while(0)
03693
03694 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \
03695                                         __IO uint32_t tmpreg; \
03696                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
03697                                         /* Delay after an RCC peripheral clock enabling */ \
03698                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
03699                                         UNUSED(tmpreg); \
03700                                        } while(0)
03701
03702 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
03703                                         __IO uint32_t tmpreg; \
03704                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
03705                                         /* Delay after an RCC peripheral clock enabling */ \
03706                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
03707                                         UNUSED(tmpreg); \
03708                                        } while(0)
03709
03710
03711 #define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
03712 #define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
03713 #define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
03714 #define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
03715 #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
03716 #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
03717 #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
03718 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
03719 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
03720 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
03721 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
03722
03723 /** @brief  Enable or disable the AHB2 peripheral clock.
03724   * @note   After reset, the peripheral clock (used for registers read/write access)
03725   *         is disabled and the application software has to enable this clock before
03726   *         using it.
03727   */
03728
03729 #define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \
03730                                         __IO uint32_t tmpreg; \
03731                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
03732                                         /* Delay after an RCC peripheral clock enabling */ \
03733                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
03734                                         UNUSED(tmpreg); \
03735                                        } while(0)
03736
03737 #define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \
03738                                         __IO uint32_t tmpreg; \
03739                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
03740                                         /* Delay after an RCC peripheral clock enabling */ \
03741                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
03742                                         UNUSED(tmpreg); \
03743                                        } while(0)
03744
03745 #define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \
03746                                         __IO uint32_t tmpreg; \
03747                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
03748                                         /* Delay after an RCC peripheral clock enabling */ \
03749                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
03750                                         UNUSED(tmpreg); \
03751                                        } while(0)
03752
03753 #define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \
03754                                         __IO uint32_t tmpreg; \
03755                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
03756                                         /* Delay after an RCC peripheral clock enabling */ \
03757                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
03758                                         UNUSED(tmpreg); \
03759                                        } while(0)
03760
03761 #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \
03762                                         __IO uint32_t tmpreg; \
03763                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
03764                                         /* Delay after an RCC peripheral clock enabling */ \
03765                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
03766                                         UNUSED(tmpreg); \
03767                                        } while(0)
03768
03769 #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \
03770                                         __IO uint32_t tmpreg; \
03771                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
03772                                         /* Delay after an RCC peripheral clock enabling */ \
03773                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
03774                                         UNUSED(tmpreg); \
03775                                        } while(0)
03776
03777 #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \
03778                                         __IO uint32_t tmpreg; \
03779                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
03780                                         /* Delay after an RCC peripheral clock enabling */ \
03781                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
03782                                         UNUSED(tmpreg); \
03783                                        } while(0)
03784
03785 #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \
03786                                         __IO uint32_t tmpreg; \
03787                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
03788                                         /* Delay after an RCC peripheral clock enabling */ \
03789                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
03790                                         UNUSED(tmpreg); \
03791                                        } while(0)
03792
03793 #define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
03794 #define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
03795 #define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
03796 #define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
03797 #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
03798 #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
03799 #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
03800 #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
03801
03802 /** @brief  Enable or disable the AHB4 peripheral clock.
03803   * @note   After reset, the peripheral clock (used for registers read/write access)
03804   *         is disabled and the application software has to enable this clock before
03805   *         using it.
03806   */
03807
03808 #define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \
03809                                         __IO uint32_t tmpreg; \
03810                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
03811                                         /* Delay after an RCC peripheral clock enabling */ \
03812                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
03813                                         UNUSED(tmpreg); \
03814                                        } while(0)
03815
03816 #define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \
03817                                         __IO uint32_t tmpreg; \
03818                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
03819                                         /* Delay after an RCC peripheral clock enabling */ \
03820                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
03821                                         UNUSED(tmpreg); \
03822                                        } while(0)
03823
03824 #define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \
03825                                         __IO uint32_t tmpreg; \
03826                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
03827                                         /* Delay after an RCC peripheral clock enabling */ \
03828                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
03829                                         UNUSED(tmpreg); \
03830                                        } while(0)
03831
03832 #define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \
03833                                         __IO uint32_t tmpreg; \
03834                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
03835                                         /* Delay after an RCC peripheral clock enabling */ \
03836                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
03837                                         UNUSED(tmpreg); \
03838                                        } while(0)
03839
03840 #define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \
03841                                         __IO uint32_t tmpreg; \
03842                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
03843                                         /* Delay after an RCC peripheral clock enabling */ \
03844                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
03845                                         UNUSED(tmpreg); \
03846                                        } while(0)
03847
03848 #define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \
03849                                         __IO uint32_t tmpreg; \
03850                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
03851                                         /* Delay after an RCC peripheral clock enabling */ \
03852                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
03853                                         UNUSED(tmpreg); \
03854                                        } while(0)
03855
03856 #define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \
03857                                         __IO uint32_t tmpreg; \
03858                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
03859                                         /* Delay after an RCC peripheral clock enabling */ \
03860                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
03861                                         UNUSED(tmpreg); \
03862                                        } while(0)
03863
03864 #define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \
03865                                         __IO uint32_t tmpreg; \
03866                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
03867                                         /* Delay after an RCC peripheral clock enabling */ \
03868                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
03869                                         UNUSED(tmpreg); \
03870                                        } while(0)
03871
03872 #define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \
03873                                         __IO uint32_t tmpreg; \
03874                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
03875                                         /* Delay after an RCC peripheral clock enabling */ \
03876                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
03877                                         UNUSED(tmpreg); \
03878                                        } while(0)
03879
03880 #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \
03881                                         __IO uint32_t tmpreg; \
03882                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
03883                                         /* Delay after an RCC peripheral clock enabling */ \
03884                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
03885                                         UNUSED(tmpreg); \
03886                                        } while(0)
03887
03888 #define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \
03889                                         __IO uint32_t tmpreg; \
03890                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
03891                                         /* Delay after an RCC peripheral clock enabling */ \
03892                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
03893                                         UNUSED(tmpreg); \
03894                                        } while(0)
03895
03896 #define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \
03897                                         __IO uint32_t tmpreg; \
03898                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
03899                                         /* Delay after an RCC peripheral clock enabling */ \
03900                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
03901                                         UNUSED(tmpreg); \
03902                                        } while(0)
03903
03904 #define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \
03905                                         __IO uint32_t tmpreg; \
03906                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
03907                                         /* Delay after an RCC peripheral clock enabling */ \
03908                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
03909                                         UNUSED(tmpreg); \
03910                                        } while(0)
03911
03912 #define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \
03913                                         __IO uint32_t tmpreg; \
03914                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
03915                                         /* Delay after an RCC peripheral clock enabling */ \
03916                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
03917                                         UNUSED(tmpreg); \
03918                                        } while(0)
03919
03920 #define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \
03921                                         __IO uint32_t tmpreg; \
03922                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
03923                                         /* Delay after an RCC peripheral clock enabling */ \
03924                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
03925                                         UNUSED(tmpreg); \
03926                                        } while(0)
03927
03928 #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \
03929                                         __IO uint32_t tmpreg; \
03930                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
03931                                         /* Delay after an RCC peripheral clock enabling */ \
03932                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
03933                                         UNUSED(tmpreg); \
03934                                        } while(0)
03935
03936
03937 #define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
03938 #define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
03939 #define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
03940 #define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
03941 #define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
03942 #define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
03943 #define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
03944 #define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
03945 #define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
03946 #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
03947 #define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
03948 #define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
03949 #define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
03950 #define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
03951 #define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
03952 #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
03953
03954
03955 /** @brief  Enable or disable the APB3 peripheral clock.
03956   * @note   After reset, the peripheral clock (used for registers read/write access)
03957   *         is disabled and the application software has to enable this clock before
03958   *         using it.
03959   */
03960
03961 #define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \
03962                                         __IO uint32_t tmpreg; \
03963                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
03964                                         /* Delay after an RCC peripheral clock enabling */ \
03965                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
03966                                         UNUSED(tmpreg); \
03967                                        } while(0)
03968
03969 #define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \
03970                                         __IO uint32_t tmpreg; \
03971                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
03972                                         /* Delay after an RCC peripheral clock enabling */ \
03973                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
03974                                         UNUSED(tmpreg); \
03975                                        } while(0)
03976
03977 #define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \
03978                                         __IO uint32_t tmpreg; \
03979                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
03980                                         /* Delay after an RCC peripheral clock enabling */ \
03981                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
03982                                         UNUSED(tmpreg); \
03983                                        } while(0)
03984
03985 #define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
03986 #define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
03987 #define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
03988
03989 /** @brief  Enable or disable the APB1 peripheral clock.
03990   * @note   After reset, the peripheral clock (used for registers read/write access)
03991   *         is disabled and the application software has to enable this clock before
03992   *         using it.
03993   */
03994
03995 #define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \
03996                                         __IO uint32_t tmpreg; \
03997                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
03998                                         /* Delay after an RCC peripheral clock enabling */ \
03999                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
04000                                         UNUSED(tmpreg); \
04001                                        } while(0)
04002
04003 #define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \
04004                                         __IO uint32_t tmpreg; \
04005                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
04006                                         /* Delay after an RCC peripheral clock enabling */ \
04007                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
04008                                         UNUSED(tmpreg); \
04009                                        } while(0)
04010
04011 #define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \
04012                                         __IO uint32_t tmpreg; \
04013                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
04014                                         /* Delay after an RCC peripheral clock enabling */ \
04015                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
04016                                         UNUSED(tmpreg); \
04017                                        } while(0)
04018
04019 #define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \
04020                                         __IO uint32_t tmpreg; \
04021                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
04022                                         /* Delay after an RCC peripheral clock enabling */ \
04023                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
04024                                         UNUSED(tmpreg); \
04025                                        } while(0)
04026
04027 #define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \
04028                                         __IO uint32_t tmpreg; \
04029                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
04030                                         /* Delay after an RCC peripheral clock enabling */ \
04031                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
04032                                         UNUSED(tmpreg); \
04033                                        } while(0)
04034
04035 #define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \
04036                                         __IO uint32_t tmpreg; \
04037                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
04038                                         /* Delay after an RCC peripheral clock enabling */ \
04039                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
04040                                         UNUSED(tmpreg); \
04041                                        } while(0)
04042
04043 #define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \
04044                                         __IO uint32_t tmpreg; \
04045                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
04046                                         /* Delay after an RCC peripheral clock enabling */ \
04047                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
04048                                         UNUSED(tmpreg); \
04049                                        } while(0)
04050
04051 #define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \
04052                                         __IO uint32_t tmpreg; \
04053                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
04054                                         /* Delay after an RCC peripheral clock enabling */ \
04055                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
04056                                         UNUSED(tmpreg); \
04057                                        } while(0)
04058
04059 #define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \
04060                                         __IO uint32_t tmpreg; \
04061                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
04062                                         /* Delay after an RCC peripheral clock enabling */ \
04063                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
04064                                         UNUSED(tmpreg); \
04065                                        } while(0)
04066
04067 #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \
04068                                         __IO uint32_t tmpreg; \
04069                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
04070                                         /* Delay after an RCC peripheral clock enabling */ \
04071                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
04072                                         UNUSED(tmpreg); \
04073                                        } while(0)
04074
04075 #define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \
04076                                         __IO uint32_t tmpreg; \
04077                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
04078                                         /* Delay after an RCC peripheral clock enabling */ \
04079                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
04080                                         UNUSED(tmpreg); \
04081                                        } while(0)
04082
04083 #define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \
04084                                         __IO uint32_t tmpreg; \
04085                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
04086                                         /* Delay after an RCC peripheral clock enabling */ \
04087                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
04088                                         UNUSED(tmpreg); \
04089                                        } while(0)
04090
04091 #define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \
04092                                         __IO uint32_t tmpreg; \
04093                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
04094                                         /* Delay after an RCC peripheral clock enabling */ \
04095                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
04096                                         UNUSED(tmpreg); \
04097                                        } while(0)
04098
04099 #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \
04100                                         __IO uint32_t tmpreg; \
04101                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
04102                                         /* Delay after an RCC peripheral clock enabling */ \
04103                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
04104                                         UNUSED(tmpreg); \
04105                                        } while(0)
04106
04107 #define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \
04108                                         __IO uint32_t tmpreg; \
04109                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
04110                                         /* Delay after an RCC peripheral clock enabling */ \
04111                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
04112                                         UNUSED(tmpreg); \
04113                                        } while(0)
04114
04115 #define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \
04116                                         __IO uint32_t tmpreg; \
04117                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
04118                                         /* Delay after an RCC peripheral clock enabling */ \
04119                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
04120                                         UNUSED(tmpreg); \
04121                                        } while(0)
04122
04123 #define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \
04124                                         __IO uint32_t tmpreg; \
04125                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
04126                                         /* Delay after an RCC peripheral clock enabling */ \
04127                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
04128                                         UNUSED(tmpreg); \
04129                                        } while(0)
04130
04131 #define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \
04132                                         __IO uint32_t tmpreg; \
04133                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
04134                                         /* Delay after an RCC peripheral clock enabling */ \
04135                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
04136                                         UNUSED(tmpreg); \
04137                                        } while(0)
04138
04139 #define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \
04140                                         __IO uint32_t tmpreg; \
04141                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
04142                                         /* Delay after an RCC peripheral clock enabling */ \
04143                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
04144                                         UNUSED(tmpreg); \
04145                                        } while(0)
04146
04147 #define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \
04148                                         __IO uint32_t tmpreg; \
04149                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
04150                                         /* Delay after an RCC peripheral clock enabling */ \
04151                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
04152                                         UNUSED(tmpreg); \
04153                                        } while(0)
04154
04155 #define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \
04156                                         __IO uint32_t tmpreg; \
04157                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
04158                                         /* Delay after an RCC peripheral clock enabling */ \
04159                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
04160                                         UNUSED(tmpreg); \
04161                                        } while(0)
04162
04163 #define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \
04164                                         __IO uint32_t tmpreg; \
04165                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
04166                                         /* Delay after an RCC peripheral clock enabling */ \
04167                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
04168                                         UNUSED(tmpreg); \
04169                                        } while(0)
04170
04171 #define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \
04172                                         __IO uint32_t tmpreg; \
04173                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
04174                                         /* Delay after an RCC peripheral clock enabling */ \
04175                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
04176                                         UNUSED(tmpreg); \
04177                                        } while(0)
04178
04179 #define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \
04180                                         __IO uint32_t tmpreg; \
04181                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
04182                                         /* Delay after an RCC peripheral clock enabling */ \
04183                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
04184                                         UNUSED(tmpreg); \
04185                                        } while(0)
04186
04187 #define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \
04188                                         __IO uint32_t tmpreg; \
04189                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
04190                                         /* Delay after an RCC peripheral clock enabling */ \
04191                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
04192                                         UNUSED(tmpreg); \
04193                                        } while(0)
04194
04195 #define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \
04196                                         __IO uint32_t tmpreg; \
04197                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
04198                                         /* Delay after an RCC peripheral clock enabling */ \
04199                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
04200                                         UNUSED(tmpreg); \
04201                                        } while(0)
04202
04203 #define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \
04204                                         __IO uint32_t tmpreg; \
04205                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
04206                                         /* Delay after an RCC peripheral clock enabling */ \
04207                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
04208                                         UNUSED(tmpreg); \
04209                                        } while(0)
04210
04211 #define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \
04212                                         __IO uint32_t tmpreg; \
04213                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
04214                                         /* Delay after an RCC peripheral clock enabling */ \
04215                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
04216                                         UNUSED(tmpreg); \
04217                                        } while(0)
04218
04219 #define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \
04220                                         __IO uint32_t tmpreg; \
04221                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
04222                                         /* Delay after an RCC peripheral clock enabling */ \
04223                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
04224                                         UNUSED(tmpreg); \
04225                                        } while(0)
04226
04227 #define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \
04228                                         __IO uint32_t tmpreg; \
04229                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
04230                                         /* Delay after an RCC peripheral clock enabling */ \
04231                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
04232                                         UNUSED(tmpreg); \
04233                                        } while(0)
04234
04235
04236 #define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
04237 #define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
04238 #define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
04239 #define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
04240 #define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
04241 #define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
04242 #define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
04243 #define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
04244 #define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
04245 #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
04246 #define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
04247 #define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
04248 #define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
04249 #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
04250 #define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
04251 #define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
04252 #define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
04253 #define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
04254 #define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
04255 #define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
04256 #define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
04257 #define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
04258 #define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
04259 #define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
04260 #define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
04261 #define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
04262 #define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
04263 #define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
04264 #define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
04265 #define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
04266
04267 /** @brief  Enable or disable the APB2 peripheral clock.
04268   * @note   After reset, the peripheral clock (used for registers read/write access)
04269   *         is disabled and the application software has to enable this clock before
04270   *         using it.
04271   */
04272
04273 #define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \
04274                                         __IO uint32_t tmpreg; \
04275                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
04276                                         /* Delay after an RCC peripheral clock enabling */ \
04277                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
04278                                         UNUSED(tmpreg); \
04279                                        } while(0)
04280
04281 #define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \
04282                                         __IO uint32_t tmpreg; \
04283                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
04284                                         /* Delay after an RCC peripheral clock enabling */ \
04285                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
04286                                         UNUSED(tmpreg); \
04287                                        } while(0)
04288
04289 #define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \
04290                                         __IO uint32_t tmpreg; \
04291                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
04292                                         /* Delay after an RCC peripheral clock enabling */ \
04293                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
04294                                         UNUSED(tmpreg); \
04295                                        } while(0)
04296
04297 #define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \
04298                                         __IO uint32_t tmpreg; \
04299                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
04300                                         /* Delay after an RCC peripheral clock enabling */ \
04301                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
04302                                         UNUSED(tmpreg); \
04303                                        } while(0)
04304
04305 #define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \
04306                                         __IO uint32_t tmpreg; \
04307                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
04308                                         /* Delay after an RCC peripheral clock enabling */ \
04309                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
04310                                         UNUSED(tmpreg); \
04311                                        } while(0)
04312
04313 #define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \
04314                                         __IO uint32_t tmpreg; \
04315                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
04316                                         /* Delay after an RCC peripheral clock enabling */ \
04317                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
04318                                         UNUSED(tmpreg); \
04319                                        } while(0)
04320
04321 #define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \
04322                                         __IO uint32_t tmpreg; \
04323                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
04324                                         /* Delay after an RCC peripheral clock enabling */ \
04325                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
04326                                         UNUSED(tmpreg); \
04327                                        } while(0)
04328
04329 #define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \
04330                                         __IO uint32_t tmpreg; \
04331                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
04332                                         /* Delay after an RCC peripheral clock enabling */ \
04333                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
04334                                         UNUSED(tmpreg); \
04335                                        } while(0)
04336
04337 #define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \
04338                                         __IO uint32_t tmpreg; \
04339                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
04340                                         /* Delay after an RCC peripheral clock enabling */ \
04341                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
04342                                         UNUSED(tmpreg); \
04343                                        } while(0)
04344
04345 #define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \
04346                                         __IO uint32_t tmpreg; \
04347                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
04348                                         /* Delay after an RCC peripheral clock enabling */ \
04349                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
04350                                         UNUSED(tmpreg); \
04351                                        } while(0)
04352
04353 #define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \
04354                                         __IO uint32_t tmpreg; \
04355                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
04356                                         /* Delay after an RCC peripheral clock enabling */ \
04357                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
04358                                         UNUSED(tmpreg); \
04359                                        } while(0)
04360
04361 #define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \
04362                                         __IO uint32_t tmpreg; \
04363                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
04364                                         /* Delay after an RCC peripheral clock enabling */ \
04365                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
04366                                         UNUSED(tmpreg); \
04367                                        } while(0)
04368
04369 #define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \
04370                                         __IO uint32_t tmpreg; \
04371                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
04372                                         /* Delay after an RCC peripheral clock enabling */ \
04373                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
04374                                         UNUSED(tmpreg); \
04375                                        } while(0)
04376
04377 #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \
04378                                         __IO uint32_t tmpreg; \
04379                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
04380                                         /* Delay after an RCC peripheral clock enabling */ \
04381                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
04382                                         UNUSED(tmpreg); \
04383                                        } while(0)
04384
04385 #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \
04386                                         __IO uint32_t tmpreg; \
04387                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
04388                                         /* Delay after an RCC peripheral clock enabling */ \
04389                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
04390                                         UNUSED(tmpreg); \
04391                                        } while(0)
04392
04393 #define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
04394 #define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
04395 #define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
04396 #define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
04397 #define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
04398 #define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
04399 #define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
04400 #define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
04401 #define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
04402 #define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
04403 #define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
04404 #define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
04405 #define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
04406 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
04407 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
04408
04409 /** @brief  Enable or disable the APB4 peripheral clock.
04410   * @note   After reset, the peripheral clock (used for registers read/write access)
04411   *         is disabled and the application software has to enable this clock before
04412   *         using it.
04413   */
04414
04415 #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \
04416                                         __IO uint32_t tmpreg; \
04417                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
04418                                         /* Delay after an RCC peripheral clock enabling */ \
04419                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
04420                                         UNUSED(tmpreg); \
04421                                        } while(0)
04422
04423 #define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \
04424                                         __IO uint32_t tmpreg; \
04425                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
04426                                         /* Delay after an RCC peripheral clock enabling */ \
04427                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
04428                                         UNUSED(tmpreg); \
04429                                        } while(0)
04430
04431 #define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \
04432                                         __IO uint32_t tmpreg; \
04433                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
04434                                         /* Delay after an RCC peripheral clock enabling */ \
04435                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
04436                                         UNUSED(tmpreg); \
04437                                        } while(0)
04438
04439 #define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \
04440                                         __IO uint32_t tmpreg; \
04441                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
04442                                         /* Delay after an RCC peripheral clock enabling */ \
04443                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
04444                                         UNUSED(tmpreg); \
04445                                        } while(0)
04446
04447 #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \
04448                                         __IO uint32_t tmpreg; \
04449                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
04450                                         /* Delay after an RCC peripheral clock enabling */ \
04451                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
04452                                         UNUSED(tmpreg); \
04453                                        } while(0)
04454
04455 #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \
04456                                         __IO uint32_t tmpreg; \
04457                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
04458                                         /* Delay after an RCC peripheral clock enabling */ \
04459                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
04460                                         UNUSED(tmpreg); \
04461                                        } while(0)
04462
04463 #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \
04464                                         __IO uint32_t tmpreg; \
04465                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
04466                                         /* Delay after an RCC peripheral clock enabling */ \
04467                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
04468                                         UNUSED(tmpreg); \
04469                                        } while(0)
04470
04471 #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \
04472                                         __IO uint32_t tmpreg; \
04473                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
04474                                         /* Delay after an RCC peripheral clock enabling */ \
04475                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
04476                                         UNUSED(tmpreg); \
04477                                        } while(0)
04478
04479 #define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \
04480                                         __IO uint32_t tmpreg; \
04481                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
04482                                         /* Delay after an RCC peripheral clock enabling */ \
04483                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
04484                                         UNUSED(tmpreg); \
04485                                        } while(0)
04486
04487 #define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \
04488                                         __IO uint32_t tmpreg; \
04489                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
04490                                         /* Delay after an RCC peripheral clock enabling */ \
04491                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
04492                                         UNUSED(tmpreg); \
04493                                        } while(0)
04494
04495 #define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \
04496                                         __IO uint32_t tmpreg; \
04497                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
04498                                         /* Delay after an RCC peripheral clock enabling */ \
04499                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
04500                                         UNUSED(tmpreg); \
04501                                        } while(0)
04502
04503 #define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \
04504                                         __IO uint32_t tmpreg; \
04505                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
04506                                         /* Delay after an RCC peripheral clock enabling */ \
04507                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
04508                                         UNUSED(tmpreg); \
04509                                        } while(0)
04510
04511
04512
04513 #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
04514 #define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
04515 #define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
04516 #define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
04517 #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
04518 #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
04519 #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
04520 #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
04521 #define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
04522 #define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
04523 #define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
04524 #define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
04525
04526 #endif /*DUAL_CORE*/
04527
04528 /** @brief  Enable or disable the AHB3 peripheral reset.
04529   */
04530
04531 #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0xFFFFFFFFU)
04532 #define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
04533 #define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
04534 #if defined(JPEG)
04535 #define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
04536 #endif /* JPEG */
04537 #define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
04538 #if defined(QUADSPI)
04539 #define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
04540 #endif /*QUADSPI*/
04541 #if defined(OCTOSPI1)
04542 #define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
04543 #endif /*OCTOSPI1*/
04544 #define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
04545 #if defined(OCTOSPI2)
04546 #define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
04547 #endif /*OCTOSPI2*/
04548 #if defined(OCTOSPIM)
04549 #define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
04550 #endif /*OCTOSPIM*/
04551 #if defined(OTFDEC1)
04552 #define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
04553 #endif /*OTFDEC1*/
04554 #if defined(OTFDEC2)
04555 #define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
04556 #endif /*OTFDEC2*/
04557 #if defined(GFXMMU)
04558 #define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
04559 #endif /*GFXMMU*/
04560
04561 #define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
04562 #define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
04563 #define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
04564 #if defined(JPEG)
04565 #define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
04566 #endif /* JPEG */
04567 #define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
04568 #if defined(QUADSPI)
04569 #define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
04570 #endif /*QUADSPI*/
04571 #if defined(OCTOSPI1)
04572 #define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
04573 #endif /*OCTOSPI1*/
04574 #define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
04575 #if defined(OCTOSPI2)
04576 #define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
04577 #endif /*OCTOSPI2*/
04578 #if defined(OCTOSPIM)
04579 #define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
04580 #endif /*OCTOSPIM*/
04581 #if defined(OTFDEC1)
04582 #define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
04583 #endif /*OTFDEC1*/
04584 #if defined(OTFDEC2)
04585 #define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
04586 #endif /*OTFDEC2*/
04587 #if defined(GFXMMU)
04588 #define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
04589 #endif /*GFXMMU*/
04590
04591
04592
04593 /** @brief  Force or release the AHB1 peripheral reset.
04594   */
04595 #define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)
04596 #define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
04597 #define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
04598 #define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
04599 #if defined(DUAL_CORE)
04600 #define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
04601 #endif /*DUAL_CORE*/
04602 #if defined(RCC_AHB1RSTR_CRCRST)
04603 #define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
04604 #endif
04605 #if defined(ETH)
04606 #define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
04607 #endif /*ETH*/
04608 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
04609 #if defined(USB2_OTG_FS)
04610 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
04611 #endif /*USB2_OTG_FS*/
04612
04613 #define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)
04614 #define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
04615 #define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
04616 #define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
04617 #if defined(DUAL_CORE)
04618 #define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
04619 #endif /*DUAL_CORE*/
04620 #if defined(RCC_AHB1RSTR_CRCRST)
04621 #define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
04622 #endif
04623 #if defined(ETH)
04624 #define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
04625 #endif /*ETH*/
04626 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
04627 #if defined(USB2_OTG_FS)
04628 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
04629 #endif /*USB2_OTG_FS*/
04630
04631 /** @brief  Force or release the AHB2 peripheral reset.
04632   */
04633 #define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)
04634 #if defined(DCMI) && defined(PSSI)
04635 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
04636 #define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/
04637 #else
04638 #define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
04639 #endif /* DCMI && PSSI */
04640 #define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
04641 #define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
04642 #define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
04643 #define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
04644 #if defined(RCC_AHB2RSTR_HSEMRST)
04645 #define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
04646 #endif
04647 #if defined(BDMA1)
04648 #define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
04649 #endif /*BDMA1*/
04650
04651 #define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)
04652 #if defined(DCMI) && defined(PSSI)
04653 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
04654 #define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/
04655 #else
04656 #define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
04657 #endif /* DCMI && PSSI */
04658 #define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
04659 #define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
04660 #define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
04661 #define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
04662 #if defined(RCC_AHB2RSTR_HSEMRST)
04663 #define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
04664 #endif
04665 #if defined(BDMA1)
04666 #define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
04667 #endif /*BDMA1*/
04668
04669
04670 /** @brief  Force or release the AHB4 peripheral reset.
04671   */
04672
04673 #define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)
04674 #define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
04675 #define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
04676 #define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
04677 #define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
04678 #define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
04679 #define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
04680 #define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
04681 #define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
04682 #define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
04683 #define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
04684 #define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
04685 #if defined(RCC_AHB4RSTR_CRCRST)
04686 #define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
04687 #endif
04688 #if defined(BDMA2)
04689 #define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
04690 #define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/
04691 #else
04692 #define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
04693 #endif /*BDMA2*/
04694 #if defined(ADC3)
04695 #define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
04696 #endif /*ADC3*/
04697 #if defined(RCC_AHB4RSTR_HSEMRST)
04698 #define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
04699 #endif
04700
04701 #define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)
04702 #define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
04703 #define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
04704 #define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
04705 #define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
04706 #define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
04707 #define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
04708 #define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
04709 #define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
04710 #define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
04711 #define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
04712 #define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
04713 #if defined(RCC_AHB4RSTR_CRCRST)
04714 #define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
04715 #endif
04716 #if defined(BDMA2)
04717 #define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
04718 #define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/
04719 #else
04720 #define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
04721 #endif /*BDMA2*/
04722 #if defined(ADC3)
04723 #define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
04724 #endif /*ADC3*/
04725 #if defined(RCC_AHB4RSTR_HSEMRST)
04726 #define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
04727 #endif
04728
04729 /** @brief  Force or release the APB3 peripheral reset.
04730   */
04731 #define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)
04732 #if defined(LTDC)
04733 #define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
04734 #endif /* LTDC */
04735 #if defined(DSI)
04736 #define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
04737 #endif /*DSI*/
04738
04739 #define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)
04740 #if defined(LTDC)
04741 #define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
04742 #endif /* LTDC */
04743 #if defined(DSI)
04744 #define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
04745 #endif /*DSI*/
04746
04747 /** @brief  Force or release the APB1 peripheral reset.
04748   */
04749 #define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)
04750 #define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)
04751 #define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
04752 #define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
04753 #define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
04754 #define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
04755 #define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
04756 #define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
04757 #define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
04758 #define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
04759 #define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
04760 #define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
04761 #define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
04762 #define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
04763 #define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
04764 #define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
04765 #define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
04766 #define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
04767 #define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
04768 #define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
04769 #define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
04770 #define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
04771 #define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
04772 #define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
04773 #define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
04774 #define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
04775 #define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
04776 #define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
04777 #define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
04778 #define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
04779 #define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
04780
04781 #define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)
04782 #define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)
04783 #define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
04784 #define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
04785 #define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
04786 #define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
04787 #define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
04788 #define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
04789 #define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
04790 #define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
04791 #define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
04792 #define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
04793 #define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
04794 #define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
04795 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
04796 #define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
04797 #define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
04798 #define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
04799 #define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
04800 #define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
04801 #define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
04802 #define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
04803 #define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
04804 #define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
04805 #define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
04806 #define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
04807 #define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
04808 #define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
04809 #define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
04810 #define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
04811 #define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
04812
04813 /** @brief  Force or release the APB2 peripheral reset.
04814   */
04815 #define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)
04816 #define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
04817 #define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
04818 #define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
04819 #define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
04820 #if defined(UART9)
04821 #define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
04822 #endif /*UART9*/
04823 #if defined(USART10)
04824 #define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
04825 #endif /*USART10*/
04826 #define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
04827 #define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
04828 #define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
04829 #define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
04830 #define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
04831 #define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
04832 #define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
04833 #define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
04834 #if defined(SAI3)
04835 #define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
04836 #endif /*SAI3*/
04837 #define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
04838 #if defined(HRTIM1)
04839 #define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
04840 #endif /*HRTIM1*/
04841
04842 #define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)
04843 #define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
04844 #define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
04845 #define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
04846 #define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
04847 #if defined(UART9)
04848 #define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
04849 #endif /*UART9*/
04850 #if defined(USART10)
04851 #define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
04852 #endif /*USART10*/
04853 #define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
04854 #define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
04855 #define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
04856 #define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
04857 #define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
04858 #define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
04859 #define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
04860 #define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
04861 #if defined(SAI3)
04862 #define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
04863 #endif /*SAI3*/
04864 #define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
04865 #if defined(HRTIM1)
04866 #define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
04867 #endif /*HRTIM1*/
04868
04869 /** @brief  Force or release the APB4 peripheral reset.
04870   */
04871
04872 #define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)
04873 #define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
04874 #define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
04875 #define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
04876 #define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
04877 #define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
04878 #define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
04879 #if defined(LPTIM4)
04880 #define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
04881 #endif /*LPTIM4*/
04882 #if defined(LPTIM5)
04883 #define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
04884 #endif /*LPTIM5*/
04885 #if defined(DAC2)
04886 #define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
04887 #endif /*DAC2*/
04888 #define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
04889 #define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
04890 #if defined(SAI4)
04891 #define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
04892 #endif /*SAI4*/
04893 #if defined(DTS)
04894 #define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
04895 #endif /*DTS*/
04896 #if defined(DFSDM2_BASE)
04897 #define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
04898 #endif /*DFSDM2*/
04899
04900 #define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)
04901 #define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
04902 #define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
04903 #define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
04904 #define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
04905 #define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
04906 #define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
04907 #if defined(LPTIM4)
04908 #define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
04909 #endif /*LPTIM4*/
04910 #if defined(LPTIM5)
04911 #define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
04912 #endif /*LPTIM5*/
04913 #if defined(RCC_APB4RSTR_DAC2RST)
04914 #define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
04915 #endif
04916 #define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
04917 #define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
04918 #if defined(SAI4)
04919 #define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
04920 #endif /*SAI4*/
04921 #if defined(DTS)
04922 #define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
04923 #endif /*DTS*/
04924 #if defined(DFSDM2_BASE)
04925 #define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
04926 #endif /*DFSDM2*/
04927
04928 /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
04929   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04930   *         power consumption.
04931   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
04932   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04933   */
04934
04935
04936 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
04937 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
04938 #if defined(JPEG)
04939 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
04940 #endif /* JPEG */
04941 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
04942 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
04943 #if defined(QUADSPI)
04944 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
04945 #endif /*QUADSPI*/
04946 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
04947 #if defined(OCTOSPI1)
04948 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
04949 #endif /*OCTOSPI1*/
04950 #if defined(OCTOSPI2)
04951 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
04952 #endif /*OCTOSPI2*/
04953 #if defined(OCTOSPIM)
04954 #define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
04955 #endif /*OCTOSPIM*/
04956 #if defined(OTFDEC1)
04957 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
04958 #endif /*OTFDEC1*/
04959 #if defined(OTFDEC2)
04960 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
04961 #endif /*OTFDEC2*/
04962 #if defined(GFXMMU)
04963 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
04964 #endif /*GFXMMU*/
04965 #if defined(CD_AXISRAM2_BASE)
04966 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
04967 #endif
04968 #if defined(CD_AXISRAM3_BASE)
04969 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
04970 #endif
04971 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
04972 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
04973 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
04974 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
04975 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
04976 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
04977 #else
04978 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
04979 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */
04980 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
04981
04982 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
04983 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
04984 #if defined(JPEG)
04985 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
04986 #endif /* JPEG */
04987 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
04988 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
04989 #if defined(QUADSPI)
04990 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
04991 #endif /*QUADSPI*/
04992 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
04993 #if defined(OCTOSPI1)
04994 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
04995 #endif /*OCTOSPI1*/
04996 #if defined(OCTOSPI2)
04997 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
04998 #endif /*OCTOSPI2*/
04999 #if defined(OCTOSPIM)
05000 #define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
05001 #endif /*OCTOSPIM*/
05002 #if defined(OTFDEC1)
05003 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
05004 #endif /*OTFDEC1*/
05005 #if defined(OTFDEC2)
05006 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
05007 #endif /*OTFDEC2*/
05008 #if defined(GFXMMU)
05009 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
05010 #endif /*GFXMMU*/
05011 #if defined(CD_AXISRAM2_BASE)
05012 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
05013 #endif
05014 #if defined(CD_AXISRAM3_BASE)
05015 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
05016 #endif
05017 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
05018 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
05019 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
05020 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
05021 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
05022 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
05023 #else
05024 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
05025 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */
05026 #endif  /* RCC_AHB3LPENR_AXISRAMLPEN */
05027
05028 /** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
05029   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05030   *         power consumption.
05031   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05032   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05033   */
05034
05035 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)
05036 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)
05037 #if defined(JPEG)
05038 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)
05039 #endif /* JPEG */
05040 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)
05041 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)
05042 #if defined(QUADSPI)
05043 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)
05044 #endif /*QUADSPI*/
05045 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)
05046 #if defined(OCTOSPI1)
05047 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)
05048 #endif /*OCTOSPI1*/
05049 #if defined(OCTOSPI2)
05050 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)
05051 #endif /*OCTOSPI2*/
05052 #if defined(OCTOSPIM)
05053 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)
05054 #endif /*OCTOSPIM*/
05055 #if defined(OTFDEC1)
05056 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
05057 #endif /*OTFDEC1*/
05058 #if defined(OTFDEC2)
05059 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
05060 #endif /*OTFDEC2*/
05061 #if defined(GFXMMU)
05062 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)
05063 #endif /*GFXMMU*/
05064 #if defined(CD_AXISRAM2_BASE)
05065 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)
05066 #endif
05067 #if defined(CD_AXISRAM3_BASE)
05068 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)
05069 #endif
05070 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)
05071 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)
05072 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)
05073 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
05074 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
05075 #else
05076 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
05077 #endif
05078
05079 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)
05080 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)
05081 #if defined(JPEG)
05082 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)
05083 #endif /* JPEG */
05084 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)
05085 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)
05086 #if defined(QUADSPI)
05087 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)
05088 #endif /*QUADSPI*/
05089 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)
05090 #if defined(OCTOSPI1)
05091 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)
05092 #endif /*OCTOSPI1*/
05093 #if defined(OCTOSPI2)
05094 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)
05095 #endif /*OCTOSPI2*/
05096 #if defined(OCTOSPIM)
05097 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
05098 #endif /*OCTOSPIM*/
05099 #if defined(OTFDEC1)
05100 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)
05101 #endif /*OTFDEC1*/
05102 #if defined(OTFDEC2)
05103 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)
05104 #endif /*OTFDEC2*/
05105 #if defined(GFXMMU)
05106 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)
05107 #endif /*GFXMMU*/
05108 #if defined(CD_AXISRAM2_BASE)
05109 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)
05110 #endif
05111 #if defined(CD_AXISRAM3_BASE)
05112 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)
05113 #endif
05114 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)
05115 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)
05116 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)
05117 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
05118 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
05119 #else
05120 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
05121 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
05122
05123 /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
05124   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05125   *         power consumption.
05126   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05127   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05128   */
05129
05130 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
05131 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
05132 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
05133 #if defined(RCC_AHB1LPENR_CRCLPEN)
05134 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
05135 #endif
05136 #if defined(ETH)
05137 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
05138 #endif /*ETH*/
05139 #if defined(DUAL_CORE)
05140 #define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
05141 #endif /*DUAL_CORE*/
05142 #if defined(ETH)
05143 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
05144 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
05145 #endif /*ETH*/
05146 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
05147 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
05148 #if defined(USB2_OTG_FS)
05149 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
05150 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
05151 #endif /* USB2_OTG_FS */
05152
05153 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
05154 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
05155 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
05156 #if defined(RCC_AHB1LPENR_CRCLPEN)
05157 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
05158 #endif
05159 #if defined(ETH)
05160 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
05161 #endif  /*ETH*/
05162 #if defined(DUAL_CORE)
05163 #define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
05164 #endif /*DUAL_CORE*/
05165 #if defined(ETH)
05166 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
05167 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
05168 #endif  /*ETH*/
05169 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
05170 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
05171 #if defined(USB2_OTG_FS)
05172 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
05173 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
05174 #endif /* USB2_OTG_FS */
05175
05176 /** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
05177   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05178   *         power consumption.
05179   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05180   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05181   */
05182
05183 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)
05184 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)
05185 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)
05186 #if defined(RCC_AHB1LPENR_CRCLPEN)
05187 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)
05188 #endif
05189 #if defined(ETH)
05190 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)
05191 #endif  /*ETH*/
05192 #if defined(DUAL_CORE)
05193 #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)
05194 #endif /*DUAL_CORE*/
05195 #if defined(ETH)
05196 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)
05197 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)
05198 #endif  /*ETH*/
05199 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)
05200 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
05201 #if defined(USB2_OTG_FS)
05202 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)
05203 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
05204 #endif /* USB2_OTG_FS */
05205
05206 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)
05207 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)
05208 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)
05209 #if defined(RCC_AHB1LPENR_CRCLPEN)
05210 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)
05211 #endif
05212 #if defined(ETH)
05213 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)
05214 #endif /* ETH */
05215 #if defined(DUAL_CORE)
05216 #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)
05217 #endif /*DUAL_CORE*/
05218 #if defined(ETH)
05219 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)
05220 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)
05221 #endif /* ETH */
05222 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)
05223 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
05224 #if defined(USB2_OTG_FS)
05225 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)
05226 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
05227 #endif /* USB2_OTG_FS */
05228
05229
05230 /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
05231   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05232   *         power consumption.
05233   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05234   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05235   */
05236
05237 #if defined(DCMI) && defined(PSSI)
05238 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
05239 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/
05240 #else
05241 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
05242 #endif /* DCMI && PSSI */
05243 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
05244 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
05245 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
05246 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
05247 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
05248 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
05249 #endif
05250 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
05251 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
05252 #else
05253 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
05254 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
05255 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
05256 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
05257 #else
05258 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
05259 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
05260 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
05261 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
05262 #endif
05263
05264 #if defined(DCMI) && defined(PSSI)
05265 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
05266 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/
05267 #else
05268 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
05269 #endif /* DCMI && PSSI */
05270 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
05271 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
05272 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
05273 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
05274 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
05275 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
05276 #endif
05277 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
05278 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
05279 #else
05280 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
05281 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
05282 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
05283 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
05284 #else
05285 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
05286 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
05287 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
05288 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
05289 #endif
05290
05291 /** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
05292   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05293   *         power consumption.
05294   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05295   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05296   */
05297
05298 #if defined(DCMI) && defined(PSSI)
05299 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)
05300 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/
05301 #else
05302 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)
05303 #endif /* DCMI && PSSI */
05304 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)
05305 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)
05306 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)
05307 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)
05308 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
05309 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
05310 #endif
05311 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
05312 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
05313 #else
05314 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
05315 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
05316 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
05317 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
05318 #else
05319 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
05320 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
05321 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
05322 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
05323 #endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
05324
05325 #if defined(DCMI) && defined(PSSI)
05326 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)
05327 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/
05328 #else
05329 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)
05330 #endif /* DCMI && PSSI */
05331 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)
05332 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)
05333 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)
05334 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
05335 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
05336 #endif
05337 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)
05338 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
05339 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
05340 #else
05341 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
05342 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
05343 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
05344 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
05345 #else
05346 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
05347 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
05348 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
05349 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
05350 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
05351
05352
05353 /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
05354   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05355   *         power consumption.
05356   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05357   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05358   */
05359
05360 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
05361 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
05362 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
05363 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
05364 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
05365 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
05366 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
05367 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
05368 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
05369 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
05370 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
05371 #if defined(RCC_AHB4LPENR_CRCLPEN)
05372 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
05373 #endif
05374 #if defined(BDMA2)
05375 #define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
05376 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
05377 #else
05378 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
05379 #endif /* BDMA2 */
05380 #if defined(ADC3)
05381 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
05382 #endif /* ADC3 */
05383 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
05384 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
05385 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))
05386 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
05387 #else
05388 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
05389 #endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
05390
05391 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
05392 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
05393 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
05394 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
05395 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
05396 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
05397 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
05398 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
05399 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
05400 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
05401 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
05402 #if defined(RCC_AHB4LPENR_CRCLPEN)
05403 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
05404 #endif
05405 #if defined(BDMA2)
05406 #define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
05407 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/
05408 #else
05409 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
05410 #endif /*BDMA2*/
05411 #if defined(ADC3)
05412 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
05413 #endif /*ADC3*/
05414 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
05415 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
05416 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
05417 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
05418 #else
05419 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
05420 #endif
05421
05422
05423 /** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
05424   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05425   *         power consumption.
05426   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05427   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05428   */
05429
05430 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)
05431 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)
05432 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)
05433 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)
05434 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)
05435 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)
05436 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)
05437 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)
05438 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)
05439 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)
05440 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)
05441 #if defined(RCC_AHB4LPENR_CRCLPEN)
05442 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)
05443 #endif
05444 #if defined(BDMA2)
05445 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)
05446 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
05447 #else
05448 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)
05449 #endif /*BDMA2*/
05450 #if defined(ADC3)
05451 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)
05452 #endif /*ADC3*/
05453 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)
05454 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
05455 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
05456 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
05457 #else
05458 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
05459 #endif
05460
05461 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)
05462 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)
05463 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)
05464 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)
05465 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)
05466 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)
05467 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)
05468 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)
05469 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)
05470 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)
05471 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)
05472 #if defined(RCC_AHB4LPENR_CRCLPEN)
05473 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)
05474 #endif
05475 #if defined(BDMA2)
05476 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)
05477 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
05478 #else
05479 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)
05480 #endif /*BDMA2*/
05481 #if defined(ADC3)
05482 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)
05483 #endif /*ADC3*/
05484 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)
05485 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
05486 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
05487 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
05488 #else
05489 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
05490 #endif
05491
05492
05493 /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
05494   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05495   *         power consumption.
05496   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05497   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05498   */
05499
05500 #if defined(LTDC)
05501 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
05502 #endif /* LTDC */
05503 #if defined(DSI)
05504 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
05505 #endif /*DSI*/
05506 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
05507
05508 #if defined(LTDC)
05509 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
05510 #endif /* LTDC */
05511 #if defined(DSI)
05512 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
05513 #endif /*DSI*/
05514 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
05515
05516
05517 /** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
05518   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05519   *         power consumption.
05520   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05521   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05522   */
05523
05524 #if defined(LTDC)
05525 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)
05526 #endif /* LTDC */
05527 #if defined(DSI)
05528 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)
05529 #endif /*DSI*/
05530 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
05531
05532 #if defined(LTDC)
05533 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)
05534 #endif /* LTDC */
05535 #if defined(DSI)
05536 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)
05537 #endif /*DSI*/
05538 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
05539
05540
05541 /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
05542   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05543   *         power consumption.
05544   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05545   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05546   */
05547
05548 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
05549 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
05550 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
05551 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
05552 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
05553 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
05554 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
05555 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
05556 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
05557 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
05558
05559 #if defined(DUAL_CORE)
05560 #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
05561 #endif /*DUAL_CORE*/
05562
05563 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
05564 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
05565 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
05566 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
05567 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
05568 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
05569 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
05570 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
05571 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
05572 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
05573 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
05574 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
05575 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
05576 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
05577 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
05578 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
05579 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
05580 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
05581 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
05582
05583
05584 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
05585 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
05586 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
05587 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
05588 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
05589 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
05590 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
05591 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
05592 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
05593 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
05594
05595 #if defined(DUAL_CORE)
05596 #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
05597 #endif /*DUAL_CORE*/
05598
05599 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
05600 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
05601 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
05602 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
05603 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
05604 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
05605 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
05606 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
05607 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
05608 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
05609 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
05610 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
05611 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
05612 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
05613 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
05614 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
05615 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
05616 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
05617 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
05618
05619
05620 /** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
05621   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05622   *         power consumption.
05623   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05624   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05625   */
05626
05627 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)
05628 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)
05629 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)
05630 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)
05631 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)
05632 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)
05633 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)
05634 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)
05635 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)
05636 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)
05637 #if defined(DUAL_CORE)
05638 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)
05639 #endif /*DUAL_CORE*/
05640 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)
05641 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)
05642 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
05643 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)
05644 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)
05645 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)
05646 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)
05647 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)
05648 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)
05649 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)
05650 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)
05651 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)
05652 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)
05653 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)
05654 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)
05655 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)
05656 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)
05657 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)
05658 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)
05659
05660 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)
05661 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)
05662 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)
05663 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)
05664 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)
05665 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)
05666 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)
05667 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)
05668 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)
05669 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)
05670 #if defined(DUAL_CORE)
05671 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)
05672 #endif /*DUAL_CORE*/
05673 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)
05674 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)
05675 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
05676 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)
05677 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)
05678 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)
05679 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)
05680 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)
05681 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)
05682 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)
05683 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)
05684 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)
05685 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)
05686 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)
05687 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)
05688 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)
05689 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)
05690 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)
05691 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)
05692
05693
05694 /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
05695   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05696   *         power consumption.
05697   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05698   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05699   */
05700
05701 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
05702 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
05703 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
05704 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
05705 #if defined(UART9)
05706 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
05707 #endif /*UART9*/
05708 #if defined(USART10)
05709 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
05710 #endif /*USART10*/
05711 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
05712 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
05713 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
05714 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
05715 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
05716 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
05717 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
05718 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
05719 #if defined(SAI3)
05720 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
05721 #endif /*SAI3*/
05722 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
05723 #if defined(HRTIM1)
05724 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
05725 #endif /*HRTIM1*/
05726
05727 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
05728 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
05729 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
05730 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
05731 #if defined(UART9)
05732 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
05733 #endif /*UART9*/
05734 #if defined(USART10)
05735 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
05736 #endif /*USART10*/
05737 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
05738 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
05739 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
05740 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
05741 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
05742 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
05743 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
05744 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
05745 #if defined(SAI3)
05746 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
05747 #endif /*SAI3*/
05748 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
05749 #if defined(HRTIM1)
05750 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
05751 #endif /*HRTIM1*/
05752
05753
05754 /** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
05755   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05756   *         power consumption.
05757   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05758   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05759   */
05760
05761 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)
05762 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)
05763 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
05764 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
05765 #if defined(UART9)
05766 #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
05767 #endif /*UART9*/
05768 #if defined(USART10)
05769 #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
05770 #endif /*USART10*/
05771 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)
05772 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)
05773 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)
05774 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)
05775 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)
05776 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)
05777 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)
05778 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)
05779 #if defined(SAI3)
05780 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)
05781 #endif /*SAI3*/
05782 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
05783 #if defined(HRTIM1)
05784 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)
05785 #endif /*HRTIM1*/
05786
05787 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)
05788 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)
05789 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
05790 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
05791 #if defined(UART9)
05792 #define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
05793 #endif /*UART9*/
05794 #if defined(USART10)
05795 #define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
05796 #endif /*USART10*/
05797 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)
05798 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)
05799 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)
05800 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)
05801 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)
05802 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)
05803 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)
05804 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)
05805 #if defined(SAI3)
05806 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)
05807 #endif /*SAI3*/
05808 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
05809 #if defined(HRTIM1)
05810 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)
05811 #endif /*HRTIM1*/
05812
05813 /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
05814   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05815   *         power consumption.
05816   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05817   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05818   */
05819
05820 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
05821 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
05822 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
05823 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
05824 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
05825 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
05826 #if defined(LPTIM4)
05827 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
05828 #endif /*LPTIM4*/
05829 #if defined(LPTIM5)
05830 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
05831 #endif /*LPTIM5*/
05832 #if defined(DAC2)
05833 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
05834 #endif /*DAC2*/
05835 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
05836 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
05837 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
05838 #if defined(SAI4)
05839 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
05840 #endif /*SAI4*/
05841 #if defined(DTS)
05842 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
05843 #endif /*DTS*/
05844 #if defined(DFSDM2_BASE)
05845 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
05846 #endif /*DFSDM2*/
05847
05848 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
05849 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
05850 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
05851 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
05852 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
05853 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
05854 #if defined(LPTIM4)
05855 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
05856 #endif /*LPTIM4*/
05857 #if defined(LPTIM5)
05858 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
05859 #endif /*LPTIM5*/
05860 #if defined(DAC2)
05861 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
05862 #endif /*DAC2*/
05863 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
05864 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
05865 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
05866 #if defined(SAI4)
05867 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
05868 #endif /*SAI4*/
05869 #if defined(DTS)
05870 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
05871 #endif /*DTS*/
05872 #if defined(DFSDM2_BASE)
05873 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
05874 #endif /*DFSDM2*/
05875
05876
05877 /** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
05878   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05879   *         power consumption.
05880   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05881   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05882   */
05883
05884 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)
05885 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
05886 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)
05887 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)
05888 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)
05889 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)
05890 #if defined(LPTIM4)
05891 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)
05892 #endif /*LPTIM4*/
05893 #if defined(LPTIM5)
05894 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)
05895 #endif /*LPTIM5*/
05896 #if defined(DAC2)
05897 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)
05898 #endif /*DAC2*/
05899 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)
05900 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)
05901 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)
05902 #if defined(SAI4)
05903 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)
05904 #endif /*SAI4*/
05905 #if defined(DTS)
05906 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)
05907 #endif /*DTS*/
05908 #if defined(DFSDM2_BASE)
05909 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
05910 #endif /*DFSDM2*/
05911
05912 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)
05913 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
05914 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)
05915 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)
05916 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)
05917 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)
05918 #if defined(LPTIM4)
05919 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)
05920 #endif /*LPTIM4*/
05921 #if defined(LPTIM5)
05922 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)
05923 #endif /*LPTIM5*/
05924 #if defined(DAC2)
05925 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)
05926 #endif /*DAC2*/
05927 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)
05928 #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)
05929 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)
05930 #if defined(SAI4)
05931 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)
05932 #endif /*SAI4*/
05933 #if defined(DTS)
05934 #define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)
05935 #endif /*DTS*/
05936 #if defined(DFSDM2_BASE)
05937 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
05938 #endif /*DFSDM2*/
05939
05940
05941 #if defined(DUAL_CORE)
05942
05943 /** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
05944   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05945   *         power consumption.
05946   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
05947   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
05948   */
05949 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
05950 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
05951 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
05952 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
05953 #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
05954 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
05955 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
05956 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
05957 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
05958 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
05959 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
05960
05961
05962 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
05963 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
05964 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
05965 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
05966 #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
05967 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
05968 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
05969 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
05970 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
05971 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
05972 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
05973
05974
05975
05976 /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
05977   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
05978   *         power consumption.
05979   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
05980   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
05981   */
05982
05983 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
05984 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
05985 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
05986 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
05987 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
05988 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
05989 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
05990 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
05991 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
05992 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
05993
05994 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
05995 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
05996 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
05997 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
05998 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
05999 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
06000 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
06001 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
06002 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
06003 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
06004
06005 /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
06006   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06007   *         power consumption.
06008   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06009   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06010   */
06011
06012 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
06013 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
06014 #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
06015 #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
06016 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
06017 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
06018 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
06019 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
06020
06021 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
06022 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
06023 #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
06024 #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
06025 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
06026 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
06027 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
06028 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
06029
06030 /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
06031   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06032   *         power consumption.
06033   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06034   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06035   */
06036
06037 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
06038 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
06039 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
06040 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
06041 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
06042 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
06043 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
06044 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
06045 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
06046 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
06047 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
06048 #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
06049 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
06050 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
06051 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
06052 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
06053
06054 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
06055 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
06056 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
06057 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
06058 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
06059 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
06060 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
06061 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
06062 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
06063 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
06064 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
06065 #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
06066 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
06067 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
06068 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
06069 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
06070
06071 /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
06072   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06073   *         power consumption.
06074   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06075   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06076   */
06077
06078 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
06079 #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
06080 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
06081
06082 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
06083 #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
06084 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
06085
06086 /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
06087   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06088   *         power consumption.
06089   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06090   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06091   */
06092
06093 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
06094 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
06095 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
06096 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
06097 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
06098 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
06099 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
06100 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
06101 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
06102 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
06103 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
06104 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
06105 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
06106 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
06107 #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
06108 #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
06109 #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
06110 #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
06111 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
06112 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
06113 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
06114 #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
06115 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
06116 #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
06117 #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
06118 #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
06119 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
06120 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
06121 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
06122 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
06123
06124
06125 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
06126 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
06127 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
06128 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
06129 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
06130 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
06131 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
06132 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
06133 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
06134 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
06135 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
06136 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
06137 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
06138 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
06139 #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
06140 #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
06141 #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
06142 #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
06143 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
06144 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
06145 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
06146 #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
06147 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
06148 #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
06149 #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
06150 #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
06151 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
06152 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
06153 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
06154 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
06155
06156 /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
06157   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06158   *         power consumption.
06159   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06160   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06161   */
06162
06163 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
06164 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
06165 #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
06166 #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
06167 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
06168 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
06169 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
06170 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
06171 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
06172 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
06173 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
06174 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
06175 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
06176 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
06177 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
06178
06179 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
06180 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
06181 #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
06182 #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
06183 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
06184 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
06185 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
06186 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
06187 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
06188 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
06189 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
06190 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
06191 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
06192 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
06193 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
06194
06195 /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
06196   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06197   *         power consumption.
06198   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06199   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06200   */
06201
06202 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
06203 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
06204 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
06205 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
06206 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
06207 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
06208 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
06209 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
06210 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
06211 #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
06212 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
06213 #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
06214
06215
06216 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
06217 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
06218 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
06219 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
06220 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
06221 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
06222 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
06223 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
06224 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
06225 #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
06226 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
06227 #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
06228
06229 /** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
06230   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06231   *         power consumption.
06232   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
06233   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
06234   */
06235
06236
06237 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
06238 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
06239 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
06240 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
06241 #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
06242 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
06243 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
06244 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
06245 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
06246 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
06247 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
06248
06249
06250 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
06251 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
06252 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
06253 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
06254 #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
06255 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
06256 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
06257 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
06258 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
06259 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
06260 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
06261
06262
06263
06264 /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
06265   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06266   *         power consumption.
06267   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06268   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06269   */
06270
06271 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
06272 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
06273 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
06274 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
06275 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
06276 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
06277 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
06278 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
06279 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
06280 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
06281
06282 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
06283 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
06284 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
06285 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
06286 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
06287 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
06288 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
06289 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
06290 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
06291 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
06292
06293 /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
06294   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06295   *         power consumption.
06296   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06297   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06298   */
06299
06300 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
06301 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
06302 #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
06303 #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
06304 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
06305 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
06306 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
06307 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
06308
06309 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
06310 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
06311 #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
06312 #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
06313 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
06314 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
06315 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
06316 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
06317
06318 /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
06319   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06320   *         power consumption.
06321   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06322   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06323   */
06324
06325 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
06326 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
06327 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
06328 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
06329 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
06330 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
06331 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
06332 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
06333 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
06334 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
06335 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
06336 #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
06337 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
06338 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
06339 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
06340 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
06341
06342 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
06343 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
06344 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
06345 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
06346 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
06347 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
06348 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
06349 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
06350 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
06351 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
06352 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
06353 #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
06354 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
06355 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
06356 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
06357 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
06358
06359 /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
06360   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06361   *         power consumption.
06362   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06363   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06364   */
06365
06366 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
06367 #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
06368 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
06369
06370 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
06371 #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
06372 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
06373
06374 /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
06375   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06376   *         power consumption.
06377   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06378   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06379   */
06380
06381 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
06382 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
06383 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
06384 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
06385 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
06386 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
06387 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
06388 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
06389 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
06390 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
06391 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
06392 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
06393 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
06394 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
06395 #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
06396 #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
06397 #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
06398 #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
06399 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
06400 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
06401 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
06402 #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
06403 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
06404 #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
06405 #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
06406 #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
06407 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
06408 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
06409 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
06410 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
06411
06412
06413 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
06414 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
06415 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
06416 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
06417 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
06418 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
06419 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
06420 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
06421 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
06422 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
06423 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
06424 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
06425 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
06426 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
06427 #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
06428 #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
06429 #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
06430 #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
06431 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
06432 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
06433 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
06434 #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
06435 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
06436 #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
06437 #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
06438 #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
06439 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
06440 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
06441 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
06442 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
06443
06444 /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
06445   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06446   *         power consumption.
06447   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06448   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06449   */
06450
06451 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
06452 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
06453 #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
06454 #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
06455 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
06456 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
06457 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
06458 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
06459 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
06460 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
06461 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
06462 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
06463 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
06464 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
06465 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
06466
06467 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
06468 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
06469 #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
06470 #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
06471 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
06472 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
06473 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
06474 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
06475 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
06476 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
06477 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
06478 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
06479 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
06480 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
06481 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
06482
06483 /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
06484   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
06485   *         power consumption.
06486   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
06487   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
06488   */
06489
06490 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
06491 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
06492 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
06493 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
06494 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
06495 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
06496 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
06497 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
06498 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
06499 #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
06500 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
06501 #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
06502
06503 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
06504 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
06505 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
06506 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
06507 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
06508 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
06509 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
06510 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
06511 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
06512 #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
06513 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
06514 #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
06515
06516 #endif /*DUAL_CORE*/
06517
06518 #if defined(DUAL_CORE)
06519 /** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
06520   * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
06521   */
06522 #else
06523 /** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
06524   * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP
06525   */
06526 #endif /*DUAL_CORE*/
06527
06528 #if defined(RCC_D3AMR_BDMAAMEN)
06529 #define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
06530 #endif
06531 #if defined(RCC_D3AMR_LPUART1AMEN)
06532 #define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
06533 #endif
06534 #if defined(RCC_D3AMR_SPI6AMEN)
06535 #define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
06536 #endif
06537 #if defined(RCC_D3AMR_I2C4AMEN)
06538 #define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
06539 #endif
06540 #if defined(RCC_D3AMR_LPTIM2AMEN)
06541 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
06542 #endif
06543 #if defined(RCC_D3AMR_LPTIM3AMEN)
06544 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
06545 #endif
06546 #if defined(LPTIM4)
06547 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
06548 #endif
06549 #if defined(LPTIM5)
06550 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
06551 #endif
06552 #if defined(RCC_D3AMR_COMP12AMEN)
06553 #define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
06554 #endif
06555 #if defined(RCC_D3AMR_VREFAMEN)
06556 #define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
06557 #endif
06558 #if defined(RCC_D3AMR_RTCAMEN)
06559 #define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
06560 #endif
06561 #if defined(RCC_D3AMR_CRCAMEN)
06562 #define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
06563 #endif
06564 #if defined(SAI4)
06565 #define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
06566 #endif
06567 #if defined(ADC3)
06568 #define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
06569 #endif
06570 #if defined(RCC_D3AMR_BKPRAMAMEN)
06571 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
06572 #endif
06573 #if defined(RCC_D3AMR_SRAM4AMEN)
06574 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
06575 #endif
06576
06577 #if defined(BDMA2)
06578 #define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
06579 #endif
06580 #if defined(RCC_SRDAMR_GPIOAMEN)
06581 #define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
06582 #endif
06583 #if defined(RCC_SRDAMR_LPUART1AMEN)
06584 #define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
06585 #endif
06586 #if defined(RCC_SRDAMR_SPI6AMEN)
06587 #define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
06588 #endif
06589 #if defined(RCC_SRDAMR_I2C4AMEN)
06590 #define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
06591 #endif
06592 #if defined(RCC_SRDAMR_LPTIM2AMEN)
06593 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
06594 #endif
06595 #if defined(RCC_SRDAMR_LPTIM3AMEN)
06596 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
06597 #endif
06598 #if defined(DAC2)
06599 #define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
06600 #endif
06601 #if defined(RCC_SRDAMR_COMP12AMEN)
06602 #define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
06603 #endif
06604 #if defined(RCC_SRDAMR_VREFAMEN)
06605 #define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
06606 #endif
06607 #if defined(RCC_SRDAMR_RTCAMEN)
06608 #define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
06609 #endif
06610 #if defined(RCC_SRDAMR_DTSAMEN)
06611 #define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
06612 #endif
06613 #if defined(DFSDM2_BASE)
06614 #define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
06615 #endif
06616 #if defined(RCC_SRDAMR_BKPRAMAMEN)
06617 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
06618 #endif
06619 #if defined(RCC_SRDAMR_SRDSRAMAMEN)
06620 #define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
06621 #endif
06622
06623 #if defined(RCC_D3AMR_BDMAAMEN)
06624 #define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
06625 #endif
06626 #if defined(RCC_D3AMR_LPUART1AMEN)
06627 #define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
06628 #endif
06629 #if defined(RCC_D3AMR_SPI6AMEN)
06630 #define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
06631 #endif
06632 #if defined(RCC_D3AMR_I2C4AMEN)
06633 #define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
06634 #endif
06635 #if defined(RCC_D3AMR_LPTIM2AMEN)
06636 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
06637 #endif
06638 #if defined(RCC_D3AMR_LPTIM3AMEN)
06639 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
06640 #endif
06641 #if defined(LPTIM4)
06642 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
06643 #endif
06644 #if defined(LPTIM5)
06645 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
06646 #endif
06647 #if defined(RCC_D3AMR_COMP12AMEN)
06648 #define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
06649 #endif
06650 #if defined(RCC_D3AMR_VREFAMEN)
06651 #define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
06652 #endif
06653 #if defined(RCC_D3AMR_RTCAMEN)
06654 #define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
06655 #endif
06656 #if defined(RCC_D3AMR_CRCAMEN)
06657 #define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
06658 #endif
06659 #if defined(SAI4)
06660 #define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
06661 #endif
06662 #if defined(ADC3)
06663 #define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
06664 #endif
06665 #if defined(RCC_D3AMR_BKPRAMAMEN)
06666 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
06667 #endif
06668 #if defined(RCC_D3AMR_SRAM4AMEN)
06669 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
06670 #endif
06671
06672 #if defined(BDMA2)
06673 #define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
06674 #endif
06675 #if defined(RCC_SRDAMR_GPIOAMEN)
06676 #define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
06677 #endif
06678 #if defined(RCC_SRDAMR_LPUART1AMEN)
06679 #define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
06680 #endif
06681 #if defined(RCC_SRDAMR_SPI6AMEN)
06682 #define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
06683 #endif
06684 #if defined(RCC_SRDAMR_I2C4AMEN)
06685 #define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
06686 #endif
06687 #if defined(RCC_SRDAMR_LPTIM2AMEN)
06688 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
06689 #endif
06690 #if defined(RCC_SRDAMR_LPTIM3AMEN)
06691 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
06692 #endif
06693 #if defined(RCC_SRDAMR_DAC2AMEN)
06694 #define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
06695 #endif
06696 #if defined(RCC_SRDAMR_COMP12AMEN)
06697 #define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
06698 #endif
06699 #if defined(RCC_SRDAMR_VREFAMEN)
06700 #define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
06701 #endif
06702 #if defined(RCC_SRDAMR_RTCAMEN)
06703 #define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
06704 #endif
06705 #if defined(RCC_SRDAMR_DTSAMEN)
06706 #define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
06707 #endif
06708 #if defined(DFSDM2_BASE)
06709 #define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
06710 #endif
06711 #if defined(RCC_SRDAMR_BKPRAMAMEN)
06712 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
06713 #endif
06714 #if defined(RCC_SRDAMR_SRDSRAMAMEN)
06715 #define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
06716 #endif
06717
06718
06719 #if defined(RCC_CKGAENR_AXICKG)
06720     /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
06721   * @note
06722   * @note
06723   * @note
06724   * @param
06725   * @note
06726   */
06727
06728 #define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
06729 #define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
06730 #define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
06731 #define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
06732 #define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
06733 #define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
06734 #define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
06735 #define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
06736 #define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
06737 #define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
06738 #define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
06739 #define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
06740 #define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
06741 #define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
06742 #define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
06743 #define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
06744 #define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
06745 #define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
06746 #define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
06747 #define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
06748 #define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
06749
06750
06751 #define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
06752 #define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
06753 #define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
06754 #define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
06755 #define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
06756 #define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
06757 #define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
06758 #define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
06759 #define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
06760 #define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
06761 #define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
06762 #define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
06763 #define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
06764 #define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
06765 #define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
06766 #define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
06767 #define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
06768 #define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
06769 #define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
06770 #define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
06771 #define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
06772
06773 #endif /* RCC_CKGAENR_AXICKG */
06774
06775
06776
06777
06778 /** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
06779   * @note     After enabling the HSI, the application software should wait on
06780   *           HSIRDY flag to be set indicating that HSI clock is stable and can
06781   *           be used to clock the PLL and/or system clock.
06782   * @note     HSI can not be stopped if it is used directly or through the PLL
06783   *           as system clock. In this case, you have to select another source
06784   *           of the system clock then stop the HSI.
06785   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
06786   * @param    __STATE__ specifies the new state of the HSI.
06787   *           This parameter can be one of the following values:
06788   *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
06789   *            @arg RCC_HSI_ON turn ON the HSI oscillator
06790   *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
06791   *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
06792   *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
06793   *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
06794   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
06795   *         clock cycles.
06796   */
06797 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
06798                   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
06799
06800
06801 /** @brief  Macro to get the HSI divider.
06802   * @retval The HSI divider. The returned value can be one
06803   *         of the following:
06804   *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
06805   *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
06806   *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
06807   *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
06808   */
06809 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
06810
06811 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
06812   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
06813   *         It is used (enabled by hardware) as system clock source after start-up
06814   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
06815   *         of the HSE used directly or indirectly as system clock (if the Clock
06816   *         Security System CSS is enabled).
06817   * @note   HSI can not be stopped if it is used as system clock source. In this case,
06818   *         you have to select another source of the system clock then stop the HSI.
06819   * @note   After enabling the HSI, the application software should wait on HSIRDY
06820   *         flag to be set indicating that HSI clock is stable and can be used as
06821   *         system clock source.
06822   *         This parameter can be: ENABLE or DISABLE.
06823   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
06824   *         clock cycles.
06825   */
06826 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
06827 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
06828
06829
06830 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
06831   * @note   The calibration is used to compensate for the variations in voltage
06832   *         and temperature that influence the frequency of the internal HSI RC.
06833   * @param  __HSICalibrationValue__: specifies the calibration trimming value.
06834   *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
06835   */
06836 #if defined(RCC_VER_X)
06837 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
06838            do {                                                                                                                          \
06839               if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \
06840              {                                                                                                                           \
06841                MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \
06842              }                                                                                                                           \
06843              else                                                                                                                        \
06844              {                                                                                                                           \
06845                MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \
06846              }                                                                                                                           \
06847            } while(0)
06848
06849 #else
06850 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
06851                MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
06852 #endif /*RCC_VER_X*/
06853 /**
06854   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
06855   *           in STOP mode to be quickly available as kernel clock for some peripherals.
06856   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
06857   *           speed because of the HSI start-up time.
06858   * @note     The enable of this function has not effect on the HSION bit.
06859   *           This parameter can be: ENABLE or DISABLE.
06860   * @retval None
06861   */
06862 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
06863 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
06864
06865
06866 /**
06867   * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
06868   * @note   After enabling the HSI48, the application software should wait on
06869   *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
06870   *         be used to clock the USB.
06871   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
06872   */
06873 #define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
06874
06875 #define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
06876
06877 /**
06878   * @brief  Macros to enable or disable the Internal  oscillator (CSI).
06879   * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
06880   *           It is used (enabled by hardware) as system clock source after
06881   *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
06882   *           of failure of the HSE used directly or indirectly as system clock
06883   *           (if the Clock Security System CSS is enabled).
06884   * @note     CSI can not be stopped if it is used as system clock source.
06885   *           In this case, you have to select another source of the system
06886   *           clock then stop the CSI.
06887   * @note     After enabling the CSI, the application software should wait on
06888   *           CSIRDY flag to be set indicating that CSI clock is stable and can
06889   *           be used as system clock source.
06890   * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
06891   *           clock cycles.
06892   */
06893 #define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
06894 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
06895
06896 /** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
06897   * @note   The calibration is used to compensate for the variations in voltage
06898   *         and temperature that influence the frequency of the internal CSI RC.
06899   * @param  __CSICalibrationValue__: specifies the calibration trimming value.
06900   *         This parameter must be a number between 0 and 0x1F.
06901   */
06902 #if defined(RCC_VER_X)
06903 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
06904            do {                                                                                                                          \
06905              if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \
06906              {                                                                                                                           \
06907                MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \
06908              }                                                                                                                           \
06909              else                                                                                                                        \
06910              {                                                                                                                           \
06911                MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
06912              }                                                                                                                           \
06913            } while(0)
06914
06915 #else
06916 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
06917            do {                                                                                                                          \
06918                MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
06919                } while(0)
06920
06921 #endif /*RCC_VER_X*/
06922 /**
06923   * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
06924   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
06925   * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
06926   *           speed because of the CSI start-up time.
06927   * @note     The enable of this function has not effect on the CSION bit.
06928   *           This parameter can be: ENABLE or DISABLE.
06929   * @retval None
06930   */
06931 #define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
06932 #define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
06933
06934
06935 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
06936   * @note   After enabling the LSI, the application software should wait on
06937   *         LSIRDY flag to be set indicating that LSI clock is stable and can
06938   *         be used to clock the IWDG and/or the RTC.
06939   * @note   LSI can not be disabled if the IWDG is running.
06940   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
06941   *         clock cycles.
06942   */
06943 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
06944 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
06945
06946 /**
06947   * @brief  Macro to configure the External High Speed oscillator (__HSE__).
06948   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
06949   *         software should wait on HSERDY flag to be set indicating that HSE clock
06950   *         is stable and can be used to clock the PLL and/or system clock.
06951   * @note   HSE state can not be changed if it is used directly or through the
06952   *         PLL as system clock. In this case, you have to select another source
06953   *         of the system clock then change the HSE state (ex. disable it).
06954   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
06955   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
06956   *         was previously enabled you have to enable it again after calling this
06957   *         function.
06958   * @param  __STATE__: specifies the new state of the HSE.
06959   *         This parameter can be one of the following values:
06960   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
06961   *                              6 HSE oscillator clock cycles.
06962   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
06963   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
06964   */
06965 #if defined(RCC_CR_HSEEXT)
06966 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                \
06967                     do {                                               \
06968                       if ((__STATE__) == RCC_HSE_ON)                   \
06969                       {                                                \
06970                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \
06971                       }                                                \
06972                       else if ((__STATE__) == RCC_HSE_OFF)             \
06973                       {                                                \
06974                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
06975                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
06976                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
06977                       }                                                \
06978                       else if ((__STATE__) == RCC_HSE_BYPASS)          \
06979                       {                                                \
06980                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
06981                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
06982                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \
06983                       }                                                \
06984                       else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
06985                       {                                                \
06986                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
06987                         SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
06988                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \
06989                       }                                                \
06990                       else                                             \
06991                       {                                                \
06992                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
06993                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
06994                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
06995                       }                                                \
06996                     } while(0)
06997 #else
06998 #define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
06999                     do {                                        \
07000                       if ((__STATE__) == RCC_HSE_ON)            \
07001                       {                                         \
07002                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \
07003                       }                                         \
07004                       else if ((__STATE__) == RCC_HSE_OFF)      \
07005                       {                                         \
07006                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
07007                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
07008                       }                                         \
07009                       else if ((__STATE__) == RCC_HSE_BYPASS)   \
07010                       {                                         \
07011                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
07012                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \
07013                       }                                         \
07014                       else                                      \
07015                       {                                         \
07016                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
07017                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
07018                       }                                         \
07019                     } while(0)
07020 #endif /* RCC_CR_HSEEXT */
07021
07022 /** @defgroup RCC_LSE_Configuration LSE Configuration
07023   * @{
07024   */
07025
07026 /**
07027   * @brief  Macro to configure the External Low Speed oscillator (LSE).
07028   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
07029   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
07030   * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
07031             A duty cycle close to 50% is recommended.
07032   * @note   As the LSE is in the Backup domain and write access is denied to
07033   *         this domain after reset, you have to enable write access using
07034   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
07035   *         (to be done once after reset).
07036   * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application
07037   *         software should wait on LSERDY flag to be set indicating that LSE clock
07038   *         is stable and can be used to clock the RTC.
07039   * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
07040   * @param  __STATE__: specifies the new state of the LSE.
07041   *         This parameter can be one of the following values:
07042   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
07043   *                              6 LSE oscillator clock cycles.
07044   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
07045   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
07046   *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
07047   *
07048   *         (*) Available on some STM32H7 lines only.
07049   */
07050 #if defined(RCC_BDCR_LSEEXT)
07051 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
07052                     do {                                               \
07053                       if((__STATE__) == RCC_LSE_ON)                    \
07054                       {                                                \
07055                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
07056                       }                                                \
07057                       else if((__STATE__) == RCC_LSE_OFF)              \
07058                       {                                                \
07059                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
07060                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
07061                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
07062                       }                                                \
07063                       else if((__STATE__) == RCC_LSE_BYPASS)           \
07064                       {                                                \
07065                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
07066                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
07067                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
07068                       }                                                \
07069                       else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
07070                       {                                                \
07071                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
07072                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
07073                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
07074                       }                                                \
07075                       else                                             \
07076                       {                                                \
07077                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
07078                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
07079                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
07080                       }                                                \
07081                     } while(0)
07082 #else
07083
07084 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
07085                     do {                                       \
07086                       if((__STATE__) == RCC_LSE_ON)            \
07087                       {                                        \
07088                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
07089                       }                                        \
07090                       else if((__STATE__) == RCC_LSE_OFF)      \
07091                       {                                        \
07092                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
07093                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
07094                       }                                        \
07095                       else if((__STATE__) == RCC_LSE_BYPASS)   \
07096                       {                                        \
07097                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
07098                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
07099                       }                                        \
07100                       else                                     \
07101                       {                                        \
07102                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
07103                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
07104                       }                                        \
07105                     } while(0)
07106
07107 #endif /* RCC_BDCR_LSEEXT */
07108 /**
07109   * @}
07110   */
07111
07112 /** @brief  Macros to enable or disable the the RTC clock.
07113   * @note   These macros must be used only after the RTC clock source was selected.
07114   */
07115 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
07116 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
07117
07118 /** @brief  Macros to configure the RTC clock (RTCCLK).
07119   * @note   As the RTC clock configuration bits are in the Backup domain and write
07120   *         access is denied to this domain after reset, you have to enable write
07121   *         access using the Power Backup Access macro before to configure
07122   *         the RTC clock source (to be done once after reset).
07123   * @note   Once the RTC clock is configured it can't be changed unless the
07124   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
07125   *         a Power On Reset (POR).
07126   * @param  __RTCCLKSource__: specifies the RTC clock source.
07127   *         This parameter can be one of the following values:
07128   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
07129   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
07130   *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
07131   *                                            as RTC clock, where x:[2,31]
07132   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
07133   *         work in STOP and STANDBY modes, and can be used as wakeup source.
07134   *         However, when the HSE clock is used as RTC clock source, the RTC
07135   *         cannot be used in STOP and STANDBY modes.
07136   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
07137   *         RTC clock source).
07138   */
07139 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
07140                                                  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
07141
07142 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
07143                                                     RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
07144                                                    } while (0)
07145
07146 #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
07147
07148
07149 /** @brief  Macros to force or release the Backup domain reset.
07150   * @note   This function resets the RTC peripheral (including the backup registers)
07151   *         and the RTC clock source selection in RCC_BDCR register.
07152   * @note   The BKPSRAM is not affected by this reset.
07153   */
07154 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
07155 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
07156
07157 /** @brief  Macros to enable or disable the main PLL.
07158   * @note   After enabling the main PLL, the application software should wait on
07159   *         PLLRDY flag to be set indicating that PLL clock is stable and can
07160   *         be used as system clock source.
07161   * @note   The main PLL can not be disabled if it is used as system clock source
07162   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
07163   */
07164 #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
07165 #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
07166
07167 /**
07168   * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
07169   * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.
07170   *         This is mainly used to save Power.
07171   *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
07172   * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
07173   *          This parameter can be one of the following values:
07174   *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
07175   *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
07176   *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
07177   *
07178   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
07179   *
07180   * @retval None
07181   */
07182 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
07183
07184 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
07185
07186
07187 /**
07188   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
07189   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
07190   * @retval None
07191   */
07192 #define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
07193
07194 #define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
07195
07196
07197 /**
07198   * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
07199   * @note   This function must be used only when the main PLL is disabled.
07200   *
07201   * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
07202   *          This parameter can be one of the following values:
07203   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
07204   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
07205   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
07206   * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
07207   *
07208   * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
07209   *          This parameter must be a number between 1 and 63.
07210   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
07211   *         frequency ranges from 1 to 16 MHz.
07212   *
07213   * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
07214   *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
07215   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
07216   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
07217   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
07218   *
07219   * @param  __PLLP1__: specifies the division factor for system  clock.
07220   *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
07221   *
07222   * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
07223   *          This parameter must be a number between 1 and 128
07224   *
07225   * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
07226   *          This parameter must be a number between 1 and 128
07227   *
07228   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
07229   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
07230   *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
07231   * @retval None
07232   *
07233   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
07234   */
07235
07236
07237 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
07238                   do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
07239                       WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
07240                                 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
07241                     } while(0)
07242
07243
07244 /** @brief  Macro to configure the PLLs clock source.
07245   * @note   This function must be used only when all PLLs are disabled.
07246   * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
07247   *         This parameter can be one of the following values:
07248   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
07249   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
07250   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
07251   *
07252   */
07253 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
07254
07255
07256 /**
07257   * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
07258   *
07259   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
07260   *
07261   * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
07262   *                            It should be a value between 0 and 8191
07263   * @note   Warning: The software has to set correctly these bits to insure that the VCO
07264   *                  output frequency is between its valid frequency range, which is:
07265   *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0
07266   *                   150 to 420 MHz if PLL1VCOSEL = 1.
07267   *
07268   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
07269   *
07270   * @retval None
07271   */
07272  #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
07273
07274
07275 /** @brief  Macro to select  the PLL1  reference frequency range.
07276   * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
07277   *         This parameter can be one of the following values:
07278   *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
07279   *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
07280   *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
07281   *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
07282   * @retval None
07283   */
07284 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
07285                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
07286
07287
07288 /** @brief  Macro to select  the PLL1  reference frequency range.
07289   * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
07290   *         This parameter can be one of the following values:
07291   *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
07292   *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
07293   *
07294   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
07295   *
07296   * @retval None
07297   */
07298 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
07299                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
07300
07301
07302
07303 /** @brief  Macro to get the clock source used as system clock.
07304   * @retval The clock source used as system clock. The returned value can be one
07305   *         of the following:
07306   *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
07307   *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
07308   *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
07309   *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
07310   */
07311 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
07312
07313
07314 /**
07315   * @brief Macro to configure the system clock source.
07316   * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
07317   * This parameter can be one of the following values:
07318   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
07319   *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
07320   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
07321   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
07322   */
07323 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
07324
07325 /** @brief  Macro to get the oscillator used as PLL clock source.
07326   * @retval The oscillator used as PLL clock source. The returned value can be one
07327   *         of the following:
07328   *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
07329   *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
07330   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
07331   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
07332   */
07333 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
07334
07335 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
07336   * @{
07337   */
07338
07339 /** @brief  Macro to configure the MCO1 clock.
07340   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
07341   *          This parameter can be one of the following values:
07342   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
07343   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
07344   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
07345   *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
07346   *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
07347   * @param  __MCODIV__ specifies the MCO clock prescaler.
07348   *          This parameter can be one of the following values:
07349   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock
07350   */
07351 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
07352                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
07353
07354 /** @brief  Macro to configure the MCO2 clock.
07355   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
07356   *          This parameter can be one of the following values:
07357   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
07358   *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
07359   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
07360   *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
07361   *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
07362   *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
07363   * @param  __MCODIV__ specifies the MCO clock prescaler.
07364   *          This parameter can be one of the following values:
07365   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock
07366   */
07367 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
07368     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
07369
07370 /**
07371   * @}
07372   */
07373
07374 /**
07375   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
07376   * @note   As the LSE is in the Backup domain and write access is denied to
07377   *         this domain after reset, you have to enable write access using
07378   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
07379   *         (to be done once after reset).
07380   * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
07381   * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
07382   *          This parameter can be one of the following values:
07383   *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
07384   *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
07385   *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
07386   *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
07387   * @retval None
07388   */
07389 #if defined(RCC_VER_X)
07390 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
07391            do{                                                                                                                                \
07392              if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \
07393              {                                                                                                                                \
07394               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \
07395              }                                                                                                                                \
07396              else                                                                                                                             \
07397              {                                                                                                                                \
07398                MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \
07399              }                                                                                                                                \
07400            } while(0)
07401 #else
07402 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
07403                MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
07404 #endif /*RCC_VER_X*/
07405 /**
07406   * @brief  Macro to configure the wake up from stop clock.
07407   * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
07408   *         This parameter can be one of the following values:
07409   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
07410   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
07411   * @retval None
07412   */
07413 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
07414                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
07415
07416 /**
07417   * @brief  Macro to configure the Kernel wake up from stop clock.
07418   * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
07419   *         This parameter can be one of the following values:
07420   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
07421   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
07422   * @retval None
07423   */
07424 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
07425                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
07426
07427 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
07428   * @brief macros to manage the specified RCC Flags and interrupts.
07429   * @{
07430   */
07431 /** @brief  Enable RCC interrupt.
07432   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
07433   *         This parameter can be any combination of the following values:
07434   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
07435   *            @arg RCC_IT_LSERDY: LSE ready interrupt
07436   *            @arg RCC_IT_CSIRDY: HSI ready interrupt
07437   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
07438   *            @arg RCC_IT_HSERDY: HSE ready interrupt
07439   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
07440   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
07441   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
07442   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
07443   *            @arg RCC_IT_LSECSS: Clock security system interrupt
07444   */
07445 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
07446
07447 /** @brief Disable RCC interrupt
07448   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
07449   *         This parameter can be any combination of the following values:
07450   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
07451   *            @arg RCC_IT_LSERDY: LSE ready interrupt
07452   *            @arg RCC_IT_CSIRDY: HSI ready interrupt
07453   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
07454   *            @arg RCC_IT_HSERDY: HSE ready interrupt
07455   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
07456   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
07457   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
07458   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
07459   *            @arg RCC_IT_LSECSS: Clock security system interrupt
07460   */
07461 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
07462
07463 /** @brief  Clear the RCC's interrupt pending bits
07464   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
07465   *         This parameter can be any combination of the following values:
07466   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
07467   *            @arg RCC_IT_LSERDY: LSE ready interrupt
07468   *            @arg RCC_IT_CSIRDY: CSI ready interrupt
07469   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
07470   *            @arg RCC_IT_HSERDY: HSE ready interrupt
07471   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
07472   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
07473   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
07474   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
07475   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
07476   *            @arg RCC_IT_LSECSS: Clock security system interrupt
07477   */
07478 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
07479
07480 /** @brief  Check the RCC's interrupt has occurred or not.
07481   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
07482   *         This parameter can be any combination of the following values:
07483   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
07484   *            @arg RCC_IT_LSERDY: LSE ready interrupt
07485   *            @arg RCC_IT_CSIRDY: CSI ready interrupt
07486   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
07487   *            @arg RCC_IT_HSERDY: HSE ready interrupt
07488   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
07489   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
07490   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
07491   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
07492   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
07493   *            @arg RCC_IT_LSECSS: Clock security system interrupt
07494   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
07495   */
07496 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
07497
07498 /** @brief Set RMVF bit to clear the reset flags.
07499   */
07500 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
07501
07502 #if defined(DUAL_CORE)
07503 #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
07504
07505 #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
07506 #endif /*DUAL_CORE*/
07507
07508 #if defined(DUAL_CORE)
07509 /** @brief  Check RCC flag is set or not.
07510   * @param  __FLAG__: specifies the flag to check.
07511   *         This parameter can be one of the following values:
07512   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
07513   *            @arg RCC_FLAG_HSIDIV: HSI divider flag
07514   *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
07515   *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
07516   *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
07517   *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
07518   *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
07519   *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
07520   *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
07521   *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
07522   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
07523   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
07524   *            @arg RCC_FLAG_C1RST:  CPU reset flag
07525   *            @arg RCC_FLAG_C2RST:  CPU2 reset flag
07526   *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
07527   *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
07528   *            @arg RCC_FLAG_BORRST: BOR reset flag
07529   *            @arg RCC_FLAG_PINRST: Pin reset
07530   *            @arg RCC_FLAG_PORRST: POR/PDR  reset
07531   *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
07532   *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
07533   *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
07534   *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
07535   *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
07536   *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
07537   *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
07538   *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
07539   *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
07540   * @retval The new state of __FLAG__ (TRUE or FALSE).
07541   */
07542 #define RCC_FLAG_MASK  ((uint8_t)0x1F)
07543 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
07544 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
07545
07546 #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
07547 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
07548
07549 #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
07550 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
07551
07552 #else
07553
07554 /** @brief  Check RCC flag is set or not.
07555   * @param  __FLAG__: specifies the flag to check.
07556   *         This parameter can be one of the following values:
07557   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
07558   *            @arg RCC_FLAG_HSIDIV: HSI divider flag
07559   *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
07560   *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
07561   *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
07562   *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)
07563   *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)
07564   *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
07565   *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)
07566   *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
07567   *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
07568   *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
07569   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
07570   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
07571   *            @arg RCC_FLAG_CPURST: CPU reset flag
07572   *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)
07573   *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)
07574   *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)
07575   *            @arg RCC_FLAG_BORRST: BOR reset flag
07576   *            @arg RCC_FLAG_PINRST: Pin reset
07577   *            @arg RCC_FLAG_PORRST: POR/PDR  reset
07578   *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
07579   *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
07580   *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
07581   *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
07582   *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
07583   *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
07584   * @retval The new state of __FLAG__ (TRUE or FALSE).
07585   *
07586   *  (*) Available on some STM32H7 lines only.
07587   */
07588 #define RCC_FLAG_MASK  ((uint8_t)0x1F)
07589 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
07590 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
07591 #endif /*DUAL_CORE*/
07592
07593 /**
07594   * @}
07595   */
07596
07597 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
07598
07599 /**
07600   * @}
07601   */
07602
07603 /* Include RCC HAL Extension module */
07604 #include "stm32h7xx_hal_rcc_ex.h"
07605
07606 /* Exported functions --------------------------------------------------------*/
07607  /** @addtogroup RCC_Exported_Functions
07608   * @{
07609   */
07610
07611 /** @addtogroup RCC_Exported_Functions_Group1
07612   * @{
07613   */
07614 /* Initialization and de-initialization functions  ******************************/
07615 HAL_StatusTypeDef HAL_RCC_DeInit(void);
07616 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
07617 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
07618
07619 /**
07620   * @}
07621   */
07622
07623 /** @addtogroup RCC_Exported_Functions_Group2
07624   * @{
07625   */
07626 /* Peripheral Control functions  ************************************************/
07627 void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
07628 void     HAL_RCC_EnableCSS(void);
07629 void     HAL_RCC_DisableCSS(void);
07630 uint32_t HAL_RCC_GetSysClockFreq(void);
07631 uint32_t HAL_RCC_GetHCLKFreq(void);
07632 uint32_t HAL_RCC_GetPCLK1Freq(void);
07633 uint32_t HAL_RCC_GetPCLK2Freq(void);
07634 void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
07635 void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
07636 /* CSS NMI IRQ handler */
07637 void     HAL_RCC_NMI_IRQHandler(void);
07638 /* User Callbacks in non blocking mode (IT mode) */
07639 void     HAL_RCC_CCSCallback(void);
07640
07641 /**
07642   * @}
07643   */
07644
07645 /**
07646   * @}
07647   */
07648
07649 /* Private types -------------------------------------------------------------*/
07650 /* Private variables ---------------------------------------------------------*/
07651 /* Private constants ---------------------------------------------------------*/
07652 /** @defgroup RCC_Private_Constants RCC Private Constants
07653   * @{
07654   */
07655
07656 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
07657 #define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
07658 #define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */
07659 #define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
07660 #define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
07661 #define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
07662 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
07663 #define RCC_DBP_TIMEOUT_VALUE      (100U)
07664 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
07665
07666 /**
07667   * @}
07668   */
07669
07670 /* Private macros ------------------------------------------------------------*/
07671 /** @addtogroup RCC_Private_Macros RCC Private Macros
07672   * @{
07673   */
07674
07675 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
07676   * @{
07677   */
07678
07679 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
07680                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
07681                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
07682                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
07683                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
07684                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
07685                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
07686
07687 #if defined(RCC_CR_HSEEXT)
07688 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
07689                          ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
07690 #else
07691 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
07692                          ((HSE) == RCC_HSE_BYPASS))
07693 #endif /* RCC_CR_HSEEXT */
07694
07695 #if defined(RCC_BDCR_LSEEXT)
07696 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
07697                          ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
07698 #else
07699 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
07700                          ((LSE) == RCC_LSE_BYPASS))
07701 #endif /* RCC_BDCR_LSEEXT */
07702
07703 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
07704                          ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
07705                          ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
07706
07707 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
07708
07709 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
07710
07711 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
07712
07713 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
07714                          ((PLL) == RCC_PLL_ON))
07715
07716 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
07717                                   ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
07718                                   ((SOURCE) == RCC_PLLSOURCE_NONE) || \
07719                                   ((SOURCE) == RCC_PLLSOURCE_HSE))
07720 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
07721 #if !defined(RCC_VER_2_0)
07722 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
07723 #else
07724 #define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
07725 #endif /* !RCC_VER_2_0 */
07726 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
07727 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
07728 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
07729
07730 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
07731                                          ((VALUE) == RCC_PLL1_DIVQ) || \
07732                                          ((VALUE) == RCC_PLL1_DIVR))
07733
07734 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
07735
07736 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
07737                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
07738                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
07739                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
07740
07741 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
07742                                ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
07743                                ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
07744                                ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
07745                                ((SYSCLK) == RCC_SYSCLK_DIV512))
07746
07747
07748 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
07749                            ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
07750                            ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
07751                            ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
07752                            ((HCLK) == RCC_HCLK_DIV512))
07753
07754 #define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
07755                                  ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
07756                                  ((CDPCLK1) == RCC_APB3_DIV16))
07757
07758 #define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */
07759
07760 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
07761                              ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
07762                             ((PCLK1) == RCC_APB1_DIV16))
07763
07764 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
07765                              ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
07766                              ((PCLK2) == RCC_APB2_DIV16))
07767
07768 #define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
07769                                   ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
07770                                   ((SRDPCLK1) == RCC_APB4_DIV16))
07771
07772 #define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
07773
07774 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
07775                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
07776                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
07777                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
07778                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
07779                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
07780                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
07781                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
07782                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
07783                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
07784                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
07785                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
07786                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
07787                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
07788                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
07789                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
07790                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
07791                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
07792                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
07793                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
07794                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
07795                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
07796                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
07797                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
07798                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
07799                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
07800                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
07801                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
07802                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
07803                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
07804                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
07805                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
07806
07807 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
07808
07809 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
07810                                    ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
07811                                    ((SOURCE) == RCC_MCO1SOURCE_HSI48))
07812
07813 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
07814                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
07815                                    ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
07816
07817 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
07818                             ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
07819                             ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
07820                             ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
07821                             ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
07822                             ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
07823                             ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
07824                             ((DIV) == RCC_MCODIV_15))
07825
07826 #if defined(DUAL_CORE)
07827 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
07828                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
07829                            ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
07830                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
07831                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
07832                            ((FLAG) == RCC_FLAG_LSIRDY)    || \
07833                            ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \
07834                            ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
07835                            ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \
07836                            ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
07837                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
07838                            ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
07839                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
07840                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))
07841
07842 #else
07843
07844 #if defined(RCC_CR_D2CKRDY)
07845 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
07846                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
07847                            ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
07848                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
07849                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
07850                            ((FLAG) == RCC_FLAG_LSIRDY)    || \
07851                            ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
07852                            ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
07853                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
07854                            ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
07855                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
07856                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
07857 #else
07858 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
07859                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
07860                            ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
07861                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
07862                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
07863                            ((FLAG) == RCC_FLAG_LSIRDY)    || \
07864                            ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
07865                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
07866                            ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
07867                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
07868                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
07869 #endif /* RCC_CR_D2CKRDY */
07870
07871 #endif /*DUAL_CORE*/
07872
07873 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
07874 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
07875
07876 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
07877                                          ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
07878
07879 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
07880                                           ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
07881 /**
07882   * @}
07883   */
07884
07885 /**
07886   * @}
07887   */
07888
07889 /**
07890   * @}
07891   */
07892
07893 /**
07894   * @}
07895   */
07896 #ifdef __cplusplus
07897 }
07898 #endif
07899
07900 #endif /* STM32H7xx_HAL_RCC_H */
07901
07902 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc_ex.c Source File

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stm32h7xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities RCC extension peripheral:
00008   *           + Extended Peripheral Control functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32h7xx_hal.h"
00026
00027 /** @addtogroup STM32H7xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup RCCEx  RCCEx
00032   * @brief RCC HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_RCC_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private defines -----------------------------------------------------------*/
00040 /** @defgroup RCCEx_Private_defines Private Defines
00041  * @{
00042  */
00043 #define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
00044 #define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
00045
00046 #define DIVIDER_P_UPDATE          0U
00047 #define DIVIDER_Q_UPDATE          1U
00048 #define DIVIDER_R_UPDATE          2U
00049 /**
00050   * @}
00051   */
00052
00053 /* Private function prototypes -----------------------------------------------*/
00054 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
00055 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
00056
00057 /* Exported functions --------------------------------------------------------*/
00058 /** @defgroup RCCEx_Exported_Functions Exported Functions
00059   * @{
00060   */
00061
00062 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00063  *  @brief  Extended Peripheral Control functions
00064  *
00065 @verbatim
00066  ===============================================================================
00067                 ##### Extended Peripheral Control functions  #####
00068  ===============================================================================
00069     [..]
00070     This subsection provides a set of functions allowing to control the RCC Clocks
00071     frequencies.
00072     [..]
00073     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00074         select the RTC clock source; in this case the Backup domain will be reset in
00075         order to modify the RTC Clock source, as consequence RTC registers (including
00076         the backup registers) and RCC_BDCR register are set to their reset values.
00077
00078 @endverbatim
00079   * @{
00080   */
00081 /**
00082   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00083   *         parameters in the RCC_PeriphCLKInitTypeDef.
00084   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00085   *         contains the configuration information for the Extended Peripherals
00086   *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
00087   *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
00088   *         SAI4A*, SAI4B*, SPI6, RTC).
00089   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00090   *         the RTC clock source; in this case the Backup domain will be reset in
00091   *         order to modify the RTC Clock source, as consequence RTC registers (including
00092   *         the backup registers) are set to their reset values.
00093   *
00094   * (*) : Available on some STM32H7 lines only.
00095   *
00096   * @retval HAL status
00097   */
00098 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00099 {
00100   uint32_t tmpreg;
00101   uint32_t tickstart;
00102   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
00103   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
00104
00105   /*---------------------------- SPDIFRX configuration -------------------------------*/
00106
00107   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
00108   {
00109
00110     switch(PeriphClkInit->SpdifrxClockSelection)
00111     {
00112     case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
00113       /* Enable PLL1Q Clock output generated form System PLL . */
00114       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00115
00116       /* SPDIFRX clock source configuration done later after clock selection check */
00117       break;
00118
00119     case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
00120
00121       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
00122
00123       /* SPDIFRX clock source configuration done later after clock selection check */
00124       break;
00125
00126     case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
00127       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
00128
00129       /* SPDIFRX clock source configuration done later after clock selection check */
00130       break;
00131
00132     case RCC_SPDIFRXCLKSOURCE_HSI:
00133       /* Internal OSC clock is used as source of SPDIFRX clock*/
00134       /* SPDIFRX clock source configuration done later after clock selection check */
00135       break;
00136
00137     default:
00138       ret = HAL_ERROR;
00139       break;
00140     }
00141
00142     if(ret == HAL_OK)
00143     {
00144       /* Set the source of SPDIFRX clock*/
00145       __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
00146     }
00147     else
00148     {
00149       /* set overall return value */
00150       status = ret;
00151     }
00152   }
00153
00154   /*---------------------------- SAI1 configuration -------------------------------*/
00155   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
00156   {
00157     switch(PeriphClkInit->Sai1ClockSelection)
00158     {
00159     case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
00160       /* Enable SAI Clock output generated form System PLL . */
00161       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00162
00163       /* SAI1 clock source configuration done later after clock selection check */
00164       break;
00165
00166     case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
00167
00168       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00169
00170       /* SAI1 clock source configuration done later after clock selection check */
00171       break;
00172
00173     case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
00174       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00175
00176       /* SAI1 clock source configuration done later after clock selection check */
00177       break;
00178
00179     case RCC_SAI1CLKSOURCE_PIN:
00180       /* External clock is used as source of SAI1 clock*/
00181       /* SAI1 clock source configuration done later after clock selection check */
00182       break;
00183
00184     case RCC_SAI1CLKSOURCE_CLKP:
00185       /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
00186       /* SAI1 clock source configuration done later after clock selection check */
00187       break;
00188
00189     default:
00190       ret = HAL_ERROR;
00191       break;
00192     }
00193
00194     if(ret == HAL_OK)
00195     {
00196       /* Set the source of SAI1 clock*/
00197       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00198     }
00199     else
00200     {
00201       /* set overall return value */
00202       status = ret;
00203     }
00204   }
00205
00206 #if defined(SAI3)
00207   /*---------------------------- SAI2/3 configuration -------------------------------*/
00208   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
00209   {
00210     switch(PeriphClkInit->Sai23ClockSelection)
00211     {
00212     case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
00213       /* Enable SAI Clock output generated form System PLL . */
00214       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00215
00216       /* SAI2/3 clock source configuration done later after clock selection check */
00217       break;
00218
00219     case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
00220
00221       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00222
00223       /* SAI2/3 clock source configuration done later after clock selection check */
00224       break;
00225
00226     case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
00227       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00228
00229       /* SAI2/3 clock source configuration done later after clock selection check */
00230       break;
00231
00232     case RCC_SAI23CLKSOURCE_PIN:
00233       /* External clock is used as source of SAI2/3 clock*/
00234       /* SAI2/3 clock source configuration done later after clock selection check */
00235       break;
00236
00237     case RCC_SAI23CLKSOURCE_CLKP:
00238       /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
00239       /* SAI2/3 clock source configuration done later after clock selection check */
00240       break;
00241
00242     default:
00243       ret = HAL_ERROR;
00244       break;
00245     }
00246
00247     if(ret == HAL_OK)
00248     {
00249       /* Set the source of SAI2/3 clock*/
00250       __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
00251     }
00252     else
00253     {
00254       /* set overall return value */
00255       status = ret;
00256     }
00257   }
00258
00259 #endif /* SAI3 */
00260
00261 #if defined(RCC_CDCCIP1R_SAI2ASEL)
00262   /*---------------------------- SAI2A configuration -------------------------------*/
00263   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
00264   {
00265     switch(PeriphClkInit->Sai2AClockSelection)
00266     {
00267     case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
00268       /* Enable SAI2A Clock output generated form System PLL . */
00269       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00270
00271       /* SAI2A clock source configuration done later after clock selection check */
00272       break;
00273
00274     case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
00275
00276       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00277
00278       /* SAI2A clock source configuration done later after clock selection check */
00279       break;
00280
00281     case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
00282       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00283
00284       /* SAI2A clock source configuration done later after clock selection check */
00285       break;
00286
00287     case RCC_SAI2ACLKSOURCE_PIN:
00288       /* External clock is used as source of SAI2A clock*/
00289       /* SAI2A clock source configuration done later after clock selection check */
00290       break;
00291
00292     case RCC_SAI2ACLKSOURCE_CLKP:
00293       /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
00294       /* SAI2A clock source configuration done later after clock selection check */
00295       break;
00296
00297     case RCC_SAI2ACLKSOURCE_SPDIF:
00298       /* SPDIF clock is used as source of SAI2A clock */
00299       /* SAI2A clock source configuration done later after clock selection check */
00300       break;
00301
00302     default:
00303       ret = HAL_ERROR;
00304       break;
00305     }
00306
00307     if(ret == HAL_OK)
00308     {
00309       /* Set the source of SAI2A clock*/
00310       __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
00311     }
00312     else
00313     {
00314       /* set overall return value */
00315       status = ret;
00316     }
00317   }
00318 #endif  /*SAI2A*/
00319
00320 #if defined(RCC_CDCCIP1R_SAI2BSEL)
00321
00322   /*---------------------------- SAI2B configuration -------------------------------*/
00323   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
00324   {
00325     switch(PeriphClkInit->Sai2BClockSelection)
00326     {
00327     case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
00328       /* Enable SAI Clock output generated form System PLL . */
00329       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00330
00331       /* SAI2B clock source configuration done later after clock selection check */
00332       break;
00333
00334     case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
00335
00336       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00337
00338       /* SAI2B clock source configuration done later after clock selection check */
00339       break;
00340
00341     case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
00342       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00343
00344       /* SAI2B clock source configuration done later after clock selection check */
00345       break;
00346
00347     case RCC_SAI2BCLKSOURCE_PIN:
00348       /* External clock is used as source of SAI2B clock*/
00349       /* SAI2B clock source configuration done later after clock selection check */
00350       break;
00351
00352     case RCC_SAI2BCLKSOURCE_CLKP:
00353       /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
00354       /* SAI2B clock source configuration done later after clock selection check */
00355       break;
00356
00357     case RCC_SAI2BCLKSOURCE_SPDIF:
00358       /* SPDIF clock is used as source of SAI2B clock */
00359       /* SAI2B clock source configuration done later after clock selection check */
00360       break;
00361
00362     default:
00363       ret = HAL_ERROR;
00364       break;
00365     }
00366
00367     if(ret == HAL_OK)
00368     {
00369       /* Set the source of SAI2B clock*/
00370       __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
00371     }
00372     else
00373     {
00374       /* set overall return value */
00375       status = ret;
00376     }
00377   }
00378 #endif  /*SAI2B*/
00379
00380 #if defined(SAI4)
00381   /*---------------------------- SAI4A configuration -------------------------------*/
00382   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
00383   {
00384     switch(PeriphClkInit->Sai4AClockSelection)
00385     {
00386     case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00387       /* Enable SAI Clock output generated form System PLL . */
00388       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00389
00390       /* SAI1 clock source configuration done later after clock selection check */
00391       break;
00392
00393     case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00394
00395       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00396
00397       /* SAI2 clock source configuration done later after clock selection check */
00398       break;
00399
00400     case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00401       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00402
00403       /* SAI1 clock source configuration done later after clock selection check */
00404       break;
00405
00406     case RCC_SAI4ACLKSOURCE_PIN:
00407       /* External clock is used as source of SAI2 clock*/
00408       /* SAI2 clock source configuration done later after clock selection check */
00409       break;
00410
00411     case RCC_SAI4ACLKSOURCE_CLKP:
00412       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00413       /* SAI1 clock source configuration done later after clock selection check */
00414       break;
00415
00416     default:
00417       ret = HAL_ERROR;
00418       break;
00419     }
00420
00421     if(ret == HAL_OK)
00422     {
00423       /* Set the source of SAI4A clock*/
00424       __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
00425     }
00426     else
00427     {
00428       /* set overall return value */
00429       status = ret;
00430     }
00431   }
00432   /*---------------------------- SAI4B configuration -------------------------------*/
00433   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
00434   {
00435     switch(PeriphClkInit->Sai4BClockSelection)
00436     {
00437     case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00438       /* Enable SAI Clock output generated form System PLL . */
00439       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00440
00441       /* SAI1 clock source configuration done later after clock selection check */
00442       break;
00443
00444     case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00445
00446       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00447
00448       /* SAI2 clock source configuration done later after clock selection check */
00449       break;
00450
00451     case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00452       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
00453
00454       /* SAI1 clock source configuration done later after clock selection check */
00455       break;
00456
00457     case RCC_SAI4BCLKSOURCE_PIN:
00458       /* External clock is used as source of SAI2 clock*/
00459       /* SAI2 clock source configuration done later after clock selection check */
00460       break;
00461
00462     case RCC_SAI4BCLKSOURCE_CLKP:
00463       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00464       /* SAI1 clock source configuration done later after clock selection check */
00465       break;
00466
00467     default:
00468       ret = HAL_ERROR;
00469       break;
00470     }
00471
00472     if(ret == HAL_OK)
00473     {
00474       /* Set the source of SAI4B clock*/
00475       __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
00476     }
00477     else
00478     {
00479       /* set overall return value */
00480       status = ret;
00481     }
00482   }
00483 #endif  /*SAI4*/
00484
00485 #if defined(QUADSPI)
00486   /*---------------------------- QSPI configuration -------------------------------*/
00487   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
00488   {
00489     switch(PeriphClkInit->QspiClockSelection)
00490     {
00491     case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
00492       /* Enable QSPI Clock output generated form System PLL . */
00493       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00494
00495       /* QSPI clock source configuration done later after clock selection check */
00496       break;
00497
00498     case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
00499
00500       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
00501
00502       /* QSPI clock source configuration done later after clock selection check */
00503       break;
00504
00505
00506     case RCC_QSPICLKSOURCE_CLKP:
00507       /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
00508       /* QSPI clock source configuration done later after clock selection check */
00509       break;
00510
00511     case RCC_QSPICLKSOURCE_D1HCLK:
00512       /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
00513       break;
00514
00515     default:
00516       ret = HAL_ERROR;
00517       break;
00518     }
00519
00520     if(ret == HAL_OK)
00521     {
00522       /* Set the source of QSPI clock*/
00523       __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
00524     }
00525     else
00526     {
00527       /* set overall return value */
00528       status = ret;
00529     }
00530   }
00531 #endif  /*QUADSPI*/
00532
00533 #if defined(OCTOSPI1) || defined(OCTOSPI2)
00534   /*---------------------------- OCTOSPI configuration -------------------------------*/
00535   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
00536   {
00537     switch(PeriphClkInit->OspiClockSelection)
00538     {
00539     case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
00540       /* Enable OSPI Clock output generated form System PLL . */
00541       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00542
00543       /* OSPI clock source configuration done later after clock selection check */
00544       break;
00545
00546     case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
00547
00548       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
00549
00550       /* OSPI clock source configuration done later after clock selection check */
00551       break;
00552
00553
00554     case RCC_OSPICLKSOURCE_CLKP:
00555       /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
00556       /* OSPI clock source configuration done later after clock selection check */
00557       break;
00558
00559     case RCC_OSPICLKSOURCE_HCLK:
00560       /* HCLK clock selected as OSPI kernel peripheral clock */
00561       break;
00562
00563     default:
00564       ret = HAL_ERROR;
00565       break;
00566     }
00567
00568     if(ret == HAL_OK)
00569     {
00570       /* Set the source of OSPI clock*/
00571       __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
00572     }
00573     else
00574     {
00575       /* set overall return value */
00576       status = ret;
00577     }
00578   }
00579 #endif  /*OCTOSPI*/
00580
00581   /*---------------------------- SPI1/2/3 configuration -------------------------------*/
00582   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
00583   {
00584     switch(PeriphClkInit->Spi123ClockSelection)
00585     {
00586     case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
00587       /* Enable SPI Clock output generated form System PLL . */
00588       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00589
00590       /* SPI1/2/3 clock source configuration done later after clock selection check */
00591       break;
00592
00593     case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
00594       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
00595
00596       /* SPI1/2/3 clock source configuration done later after clock selection check */
00597       break;
00598
00599     case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
00600       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
00601
00602       /* SPI1/2/3 clock source configuration done later after clock selection check */
00603       break;
00604
00605     case RCC_SPI123CLKSOURCE_PIN:
00606       /* External clock is used as source of SPI1/2/3 clock*/
00607       /* SPI1/2/3 clock source configuration done later after clock selection check */
00608       break;
00609
00610     case RCC_SPI123CLKSOURCE_CLKP:
00611       /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
00612       /* SPI1/2/3 clock source configuration done later after clock selection check */
00613       break;
00614
00615     default:
00616       ret = HAL_ERROR;
00617       break;
00618     }
00619
00620     if(ret == HAL_OK)
00621     {
00622       /* Set the source of SPI1/2/3 clock*/
00623       __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
00624     }
00625     else
00626     {
00627       /* set overall return value */
00628       status = ret;
00629     }
00630   }
00631
00632   /*---------------------------- SPI4/5 configuration -------------------------------*/
00633   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
00634   {
00635     switch(PeriphClkInit->Spi45ClockSelection)
00636     {
00637     case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
00638       /* SPI4/5 clock source configuration done later after clock selection check */
00639       break;
00640
00641     case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
00642
00643       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
00644
00645       /* SPI4/5 clock source configuration done later after clock selection check */
00646       break;
00647     case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
00648       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
00649       /* SPI4/5 clock source configuration done later after clock selection check */
00650       break;
00651
00652     case RCC_SPI45CLKSOURCE_HSI:
00653       /* HSI oscillator clock is used as source of SPI4/5 clock*/
00654       /* SPI4/5 clock source configuration done later after clock selection check */
00655       break;
00656
00657     case RCC_SPI45CLKSOURCE_CSI:
00658       /*  CSI oscillator clock is used as source of SPI4/5 clock */
00659       /* SPI4/5 clock source configuration done later after clock selection check */
00660       break;
00661
00662     case RCC_SPI45CLKSOURCE_HSE:
00663       /* HSE,  oscillator is used as source of SPI4/5 clock */
00664       /* SPI4/5 clock source configuration done later after clock selection check */
00665       break;
00666
00667     default:
00668       ret = HAL_ERROR;
00669       break;
00670     }
00671
00672     if(ret == HAL_OK)
00673     {
00674       /* Set the source of SPI4/5 clock*/
00675       __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
00676     }
00677     else
00678     {
00679       /* set overall return value */
00680       status = ret;
00681     }
00682   }
00683
00684   /*---------------------------- SPI6 configuration -------------------------------*/
00685   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
00686   {
00687     switch(PeriphClkInit->Spi6ClockSelection)
00688     {
00689     case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
00690       /* SPI6 clock source configuration done later after clock selection check */
00691       break;
00692
00693     case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
00694
00695       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
00696
00697       /* SPI6 clock source configuration done later after clock selection check */
00698       break;
00699     case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
00700       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
00701       /* SPI6 clock source configuration done later after clock selection check */
00702       break;
00703
00704     case RCC_SPI6CLKSOURCE_HSI:
00705       /* HSI oscillator clock is used as source of SPI6 clock*/
00706       /* SPI6 clock source configuration done later after clock selection check */
00707       break;
00708
00709     case RCC_SPI6CLKSOURCE_CSI:
00710       /*  CSI oscillator clock is used as source of SPI6 clock */
00711       /* SPI6 clock source configuration done later after clock selection check */
00712       break;
00713
00714     case RCC_SPI6CLKSOURCE_HSE:
00715       /* HSE,  oscillator is used as source of SPI6 clock */
00716       /* SPI6 clock source configuration done later after clock selection check */
00717       break;
00718 #if defined(RCC_SPI6CLKSOURCE_PIN)
00719     case RCC_SPI6CLKSOURCE_PIN:
00720       /* 2S_CKIN is used as source of SPI6 clock */
00721       /* SPI6 clock source configuration done later after clock selection check */
00722       break;
00723 #endif
00724
00725     default:
00726       ret = HAL_ERROR;
00727       break;
00728     }
00729
00730     if(ret == HAL_OK)
00731     {
00732       /* Set the source of SPI6 clock*/
00733       __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
00734     }
00735     else
00736     {
00737       /* set overall return value */
00738       status = ret;
00739     }
00740   }
00741
00742 #if defined(DSI)
00743   /*---------------------------- DSI configuration -------------------------------*/
00744   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
00745   {
00746     switch(PeriphClkInit->DsiClockSelection)
00747     {
00748
00749     case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
00750
00751       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
00752
00753       /* DSI clock source configuration done later after clock selection check */
00754       break;
00755
00756     case RCC_DSICLKSOURCE_PHY:
00757       /* PHY is used as clock source for DSI*/
00758       /* DSI clock source configuration done later after clock selection check */
00759       break;
00760
00761     default:
00762       ret = HAL_ERROR;
00763       break;
00764     }
00765
00766     if(ret == HAL_OK)
00767     {
00768       /* Set the source of DSI clock*/
00769       __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
00770     }
00771     else
00772     {
00773       /* set overall return value */
00774       status = ret;
00775     }
00776   }
00777 #endif /*DSI*/
00778
00779 #if defined(FDCAN1) || defined(FDCAN2)
00780   /*---------------------------- FDCAN configuration -------------------------------*/
00781   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
00782   {
00783     switch(PeriphClkInit->FdcanClockSelection)
00784     {
00785     case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
00786       /* Enable FDCAN Clock output generated form System PLL . */
00787       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00788
00789       /* FDCAN clock source configuration done later after clock selection check */
00790       break;
00791
00792     case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
00793
00794       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
00795
00796       /* FDCAN clock source configuration done later after clock selection check */
00797       break;
00798
00799     case RCC_FDCANCLKSOURCE_HSE:
00800       /* HSE is used as clock source for FDCAN*/
00801       /* FDCAN clock source configuration done later after clock selection check */
00802       break;
00803
00804     default:
00805       ret = HAL_ERROR;
00806       break;
00807     }
00808
00809     if(ret == HAL_OK)
00810     {
00811       /* Set the source of FDCAN clock*/
00812       __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
00813     }
00814     else
00815     {
00816       /* set overall return value */
00817       status = ret;
00818     }
00819   }
00820 #endif /*FDCAN1 || FDCAN2*/
00821
00822   /*---------------------------- FMC configuration -------------------------------*/
00823   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
00824   {
00825     switch(PeriphClkInit->FmcClockSelection)
00826     {
00827     case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
00828       /* Enable FMC Clock output generated form System PLL . */
00829       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00830
00831       /* FMC clock source configuration done later after clock selection check */
00832       break;
00833
00834     case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
00835
00836       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
00837
00838       /* FMC clock source configuration done later after clock selection check */
00839       break;
00840
00841
00842     case RCC_FMCCLKSOURCE_CLKP:
00843       /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
00844       /* FMC clock source configuration done later after clock selection check */
00845       break;
00846
00847     case RCC_FMCCLKSOURCE_HCLK:
00848       /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
00849       break;
00850
00851     default:
00852       ret = HAL_ERROR;
00853       break;
00854     }
00855
00856     if(ret == HAL_OK)
00857     {
00858       /* Set the source of FMC clock*/
00859       __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
00860     }
00861     else
00862     {
00863       /* set overall return value */
00864       status = ret;
00865     }
00866   }
00867
00868   /*---------------------------- RTC configuration -------------------------------*/
00869   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
00870   {
00871     /* check for RTC Parameters used to output RTCCLK */
00872     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00873
00874     /* Enable write access to Backup domain */
00875     SET_BIT(PWR->CR1, PWR_CR1_DBP);
00876
00877     /* Wait for Backup domain Write protection disable */
00878     tickstart = HAL_GetTick();
00879
00880     while((PWR->CR1 & PWR_CR1_DBP) == 0U)
00881     {
00882       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00883       {
00884         ret = HAL_TIMEOUT;
00885         break;
00886       }
00887     }
00888
00889     if(ret == HAL_OK)
00890     {
00891       /* Reset the Backup domain only if the RTC Clock source selection is modified */
00892       if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
00893       {
00894         /* Store the content of BDCR register before the reset of Backup Domain */
00895         tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00896         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00897         __HAL_RCC_BACKUPRESET_FORCE();
00898         __HAL_RCC_BACKUPRESET_RELEASE();
00899         /* Restore the Content of BDCR register */
00900         RCC->BDCR = tmpreg;
00901       }
00902
00903       /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
00904       if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
00905       {
00906         /* Get Start Tick*/
00907         tickstart = HAL_GetTick();
00908
00909         /* Wait till LSE is ready */
00910         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
00911         {
00912           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00913           {
00914             ret = HAL_TIMEOUT;
00915             break;
00916           }
00917         }
00918       }
00919
00920       if(ret == HAL_OK)
00921       {
00922         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00923       }
00924       else
00925       {
00926         /* set overall return value */
00927         status = ret;
00928       }
00929     }
00930     else
00931     {
00932       /* set overall return value */
00933       status = ret;
00934     }
00935   }
00936
00937
00938   /*-------------------------- USART1/6 configuration --------------------------*/
00939   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
00940   {
00941     switch(PeriphClkInit->Usart16ClockSelection)
00942     {
00943     case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
00944       /* USART1/6 clock source configuration done later after clock selection check */
00945       break;
00946
00947     case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
00948       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
00949       /* USART1/6 clock source configuration done later after clock selection check */
00950       break;
00951
00952     case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
00953       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
00954       /* USART1/6 clock source configuration done later after clock selection check */
00955       break;
00956
00957     case RCC_USART16CLKSOURCE_HSI:
00958       /* HSI oscillator clock is used as source of USART1/6 clock */
00959       /* USART1/6 clock source configuration done later after clock selection check */
00960       break;
00961
00962     case RCC_USART16CLKSOURCE_CSI:
00963       /* CSI oscillator clock is used as source of USART1/6 clock */
00964       /* USART1/6 clock source configuration done later after clock selection check */
00965       break;
00966
00967     case RCC_USART16CLKSOURCE_LSE:
00968       /* LSE,  oscillator is used as source of USART1/6 clock */
00969       /* USART1/6 clock source configuration done later after clock selection check */
00970       break;
00971
00972     default:
00973       ret = HAL_ERROR;
00974       break;
00975     }
00976
00977     if(ret == HAL_OK)
00978     {
00979       /* Set the source of USART1/6 clock */
00980       __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
00981     }
00982     else
00983     {
00984       /* set overall return value */
00985       status = ret;
00986     }
00987   }
00988
00989   /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
00990   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
00991   {
00992     switch(PeriphClkInit->Usart234578ClockSelection)
00993     {
00994     case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
00995       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
00996       break;
00997
00998     case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
00999       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
01000       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
01001       break;
01002
01003     case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
01004       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
01005       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
01006       break;
01007
01008     case RCC_USART234578CLKSOURCE_HSI:
01009       /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
01010       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
01011       break;
01012
01013     case RCC_USART234578CLKSOURCE_CSI:
01014       /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
01015       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
01016       break;
01017
01018     case RCC_USART234578CLKSOURCE_LSE:
01019       /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
01020       /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
01021       break;
01022
01023     default:
01024       ret = HAL_ERROR;
01025       break;
01026     }
01027
01028     if(ret == HAL_OK)
01029     {
01030       /* Set the source of USART2/3/4/5/7/8 clock */
01031       __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
01032     }
01033     else
01034     {
01035       /* set overall return value */
01036       status = ret;
01037     }
01038   }
01039
01040   /*-------------------------- LPUART1 Configuration -------------------------*/
01041   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
01042   {
01043     switch(PeriphClkInit->Lpuart1ClockSelection)
01044     {
01045     case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
01046       /* LPUART1 clock source configuration done later after clock selection check */
01047       break;
01048
01049     case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
01050       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
01051       /* LPUART1 clock source configuration done later after clock selection check */
01052       break;
01053
01054     case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
01055       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
01056       /* LPUART1 clock source configuration done later after clock selection check */
01057       break;
01058
01059     case RCC_LPUART1CLKSOURCE_HSI:
01060       /* HSI oscillator clock is used as source of LPUART1 clock */
01061       /* LPUART1 clock source configuration done later after clock selection check */
01062       break;
01063
01064     case RCC_LPUART1CLKSOURCE_CSI:
01065       /* CSI oscillator clock is used as source of LPUART1 clock */
01066       /* LPUART1 clock source configuration done later after clock selection check */
01067       break;
01068
01069     case RCC_LPUART1CLKSOURCE_LSE:
01070       /* LSE,  oscillator is used as source of LPUART1 clock */
01071       /* LPUART1 clock source configuration done later after clock selection check */
01072       break;
01073
01074     default:
01075       ret = HAL_ERROR;
01076       break;
01077     }
01078
01079     if(ret == HAL_OK)
01080     {
01081       /* Set the source of LPUART1 clock */
01082       __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
01083     }
01084     else
01085     {
01086       /* set overall return value */
01087       status = ret;
01088     }
01089   }
01090
01091   /*---------------------------- LPTIM1 configuration -------------------------------*/
01092   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
01093   {
01094     switch(PeriphClkInit->Lptim1ClockSelection)
01095     {
01096     case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
01097       /* LPTIM1 clock source configuration done later after clock selection check */
01098       break;
01099
01100     case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
01101
01102       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
01103
01104       /* LPTIM1 clock source configuration done later after clock selection check */
01105       break;
01106
01107     case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
01108       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
01109
01110       /* LPTIM1 clock source configuration done later after clock selection check */
01111       break;
01112
01113     case RCC_LPTIM1CLKSOURCE_LSE:
01114       /* External low speed OSC clock is used as source of LPTIM1 clock*/
01115       /* LPTIM1 clock source configuration done later after clock selection check */
01116       break;
01117
01118     case RCC_LPTIM1CLKSOURCE_LSI:
01119       /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
01120       /* LPTIM1 clock source configuration done later after clock selection check */
01121       break;
01122     case RCC_LPTIM1CLKSOURCE_CLKP:
01123       /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
01124       /* LPTIM1 clock source configuration done later after clock selection check */
01125       break;
01126
01127     default:
01128       ret = HAL_ERROR;
01129       break;
01130     }
01131
01132     if(ret == HAL_OK)
01133     {
01134       /* Set the source of LPTIM1 clock*/
01135       __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
01136     }
01137     else
01138     {
01139       /* set overall return value */
01140       status = ret;
01141     }
01142   }
01143
01144   /*---------------------------- LPTIM2 configuration -------------------------------*/
01145   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
01146   {
01147     switch(PeriphClkInit->Lptim2ClockSelection)
01148     {
01149     case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
01150       /* LPTIM2 clock source configuration done later after clock selection check */
01151       break;
01152
01153     case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
01154
01155       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
01156
01157       /* LPTIM2 clock source configuration done later after clock selection check */
01158       break;
01159
01160     case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
01161       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
01162
01163       /* LPTIM2 clock source configuration done later after clock selection check */
01164       break;
01165
01166     case RCC_LPTIM2CLKSOURCE_LSE:
01167       /* External low speed OSC clock is used as source of LPTIM2 clock*/
01168       /* LPTIM2 clock source configuration done later after clock selection check */
01169       break;
01170
01171     case RCC_LPTIM2CLKSOURCE_LSI:
01172       /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
01173       /* LPTIM2 clock source configuration done later after clock selection check */
01174       break;
01175     case RCC_LPTIM2CLKSOURCE_CLKP:
01176       /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
01177       /* LPTIM2 clock source configuration done later after clock selection check */
01178       break;
01179
01180     default:
01181       ret = HAL_ERROR;
01182       break;
01183     }
01184
01185     if(ret == HAL_OK)
01186     {
01187       /* Set the source of LPTIM2 clock*/
01188       __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
01189     }
01190     else
01191     {
01192       /* set overall return value */
01193       status = ret;
01194     }
01195   }
01196
01197   /*---------------------------- LPTIM345 configuration -------------------------------*/
01198   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
01199   {
01200     switch(PeriphClkInit->Lptim345ClockSelection)
01201     {
01202
01203     case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
01204       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01205       break;
01206
01207     case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
01208       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
01209
01210       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01211       break;
01212
01213     case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
01214       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
01215
01216       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01217       break;
01218
01219     case RCC_LPTIM345CLKSOURCE_LSE:
01220       /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
01221       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01222       break;
01223
01224     case RCC_LPTIM345CLKSOURCE_LSI:
01225       /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
01226       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01227       break;
01228     case RCC_LPTIM345CLKSOURCE_CLKP:
01229       /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
01230       /* LPTIM3/4/5 clock source configuration done later after clock selection check */
01231       break;
01232
01233     default:
01234       ret = HAL_ERROR;
01235       break;
01236     }
01237
01238     if(ret == HAL_OK)
01239     {
01240       /* Set the source of LPTIM3/4/5 clock */
01241       __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
01242     }
01243     else
01244     {
01245       /* set overall return value */
01246       status = ret;
01247     }
01248   }
01249
01250   /*------------------------------ I2C1/2/3 Configuration ------------------------*/
01251   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
01252   {
01253     /* Check the parameters */
01254     assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
01255
01256     if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
01257     {
01258         if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
01259         {
01260           status = HAL_ERROR;
01261         }
01262     }
01263
01264       __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
01265
01266   }
01267
01268   /*------------------------------ I2C4 Configuration ------------------------*/
01269   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
01270   {
01271     /* Check the parameters */
01272     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
01273
01274     if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
01275     {
01276       if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
01277       {
01278         status = HAL_ERROR;
01279       }
01280     }
01281
01282       __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
01283
01284   }
01285
01286   /*---------------------------- ADC configuration -------------------------------*/
01287   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
01288   {
01289     switch(PeriphClkInit->AdcClockSelection)
01290     {
01291
01292     case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
01293
01294       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
01295
01296       /* ADC clock source configuration done later after clock selection check */
01297       break;
01298
01299     case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
01300       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
01301
01302       /* ADC clock source configuration done later after clock selection check */
01303       break;
01304
01305     case RCC_ADCCLKSOURCE_CLKP:
01306       /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
01307       /* ADC clock source configuration done later after clock selection check */
01308       break;
01309
01310     default:
01311       ret = HAL_ERROR;
01312       break;
01313     }
01314
01315     if(ret == HAL_OK)
01316     {
01317       /* Set the source of ADC clock*/
01318       __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
01319     }
01320     else
01321     {
01322       /* set overall return value */
01323       status = ret;
01324     }
01325   }
01326
01327   /*------------------------------ USB Configuration -------------------------*/
01328   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
01329   {
01330
01331     switch(PeriphClkInit->UsbClockSelection)
01332     {
01333     case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
01334       /* Enable USB Clock output generated form System USB . */
01335       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01336
01337       /* USB clock source configuration done later after clock selection check */
01338       break;
01339
01340     case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
01341
01342       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
01343
01344       /* USB clock source configuration done later after clock selection check */
01345       break;
01346
01347     case RCC_USBCLKSOURCE_HSI48:
01348       /* HSI48 oscillator is used as source of USB clock */
01349       /* USB clock source configuration done later after clock selection check */
01350       break;
01351
01352     default:
01353       ret = HAL_ERROR;
01354       break;
01355     }
01356
01357     if(ret == HAL_OK)
01358     {
01359       /* Set the source of USB clock*/
01360       __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
01361     }
01362     else
01363     {
01364       /* set overall return value */
01365       status = ret;
01366     }
01367
01368   }
01369
01370   /*------------------------------------- SDMMC Configuration ------------------------------------*/
01371   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
01372   {
01373     /* Check the parameters */
01374     assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
01375
01376     switch(PeriphClkInit->SdmmcClockSelection)
01377     {
01378     case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
01379       /* Enable SDMMC Clock output generated form System PLL . */
01380       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01381
01382       /* SDMMC clock source configuration done later after clock selection check */
01383       break;
01384
01385     case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
01386
01387       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
01388
01389       /* SDMMC clock source configuration done later after clock selection check */
01390       break;
01391
01392     default:
01393       ret = HAL_ERROR;
01394       break;
01395     }
01396
01397     if(ret == HAL_OK)
01398     {
01399       /* Set the source of SDMMC clock*/
01400       __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
01401     }
01402     else
01403     {
01404       /* set overall return value */
01405       status = ret;
01406     }
01407   }
01408
01409 #if defined(LTDC)
01410   /*-------------------------------------- LTDC Configuration -----------------------------------*/
01411   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
01412   {
01413     if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
01414     {
01415       status=HAL_ERROR;
01416     }
01417   }
01418 #endif /* LTDC */
01419
01420   /*------------------------------ RNG Configuration -------------------------*/
01421   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
01422   {
01423
01424     switch(PeriphClkInit->RngClockSelection)
01425     {
01426     case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
01427       /* Enable RNG Clock output generated form System RNG . */
01428       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01429
01430       /* RNG clock source configuration done later after clock selection check */
01431       break;
01432
01433     case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
01434
01435       /* RNG clock source configuration done later after clock selection check */
01436       break;
01437
01438     case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
01439
01440       /* RNG clock source configuration done later after clock selection check */
01441       break;
01442     case RCC_RNGCLKSOURCE_HSI48:
01443       /* HSI48 oscillator is used as source of RNG clock */
01444       /* RNG clock source configuration done later after clock selection check */
01445       break;
01446
01447     default:
01448       ret = HAL_ERROR;
01449       break;
01450     }
01451
01452     if(ret == HAL_OK)
01453     {
01454       /* Set the source of RNG clock*/
01455       __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
01456     }
01457     else
01458     {
01459       /* set overall return value */
01460       status = ret;
01461     }
01462
01463   }
01464
01465   /*------------------------------ SWPMI1 Configuration ------------------------*/
01466   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
01467   {
01468     /* Check the parameters */
01469     assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
01470
01471     /* Configure the SWPMI1 interface clock source */
01472     __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
01473   }
01474 #if defined(HRTIM)
01475   /*------------------------------ HRTIM1 clock Configuration ----------------*/
01476   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
01477   {
01478     /* Check the parameters */
01479     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
01480
01481     /* Configure the HRTIM1 clock source */
01482     __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
01483   }
01484 #endif  /*HRTIM*/
01485   /*------------------------------ DFSDM1 Configuration ------------------------*/
01486   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
01487   {
01488     /* Check the parameters */
01489     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
01490
01491     /* Configure the DFSDM1 interface clock source */
01492     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
01493   }
01494
01495 #if defined(DFSDM2_BASE)
01496   /*------------------------------ DFSDM2 Configuration ------------------------*/
01497   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
01498   {
01499     /* Check the parameters */
01500     assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
01501
01502     /* Configure the DFSDM2 interface clock source */
01503     __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
01504   }
01505 #endif  /* DFSDM2 */
01506
01507   /*------------------------------------ TIM configuration --------------------------------------*/
01508   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
01509   {
01510     /* Check the parameters */
01511     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
01512
01513     /* Configure Timer Prescaler */
01514     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
01515   }
01516
01517   /*------------------------------------ CKPER configuration --------------------------------------*/
01518   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
01519   {
01520     /* Check the parameters */
01521     assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
01522
01523     /* Configure the CKPER clock source */
01524     __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
01525   }
01526
01527   if (status == HAL_OK)
01528   {
01529     return HAL_OK;
01530   }
01531   return HAL_ERROR;
01532 }
01533
01534 /**
01535   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
01536   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01537   *         returns the configuration information for the Extended Peripherals clocks :
01538   *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
01539   *         USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
01540   *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
01541   * @retval None
01542   *
01543   *   (*) : Available on some STM32H7 lines only.
01544   */
01545 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01546 {
01547   /* Set all possible values for the extended clock type parameter------------*/
01548   PeriphClkInit->PeriphClockSelection =
01549                  RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
01550                  RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
01551                  RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
01552                  RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
01553                  RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
01554                  RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
01555                  RCC_PERIPHCLK_CKPER;
01556
01557 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
01558 #if defined(RCC_CDCCIP1R_SAI2ASEL)
01559   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
01560 #endif /* RCC_CDCCIP1R_SAI2ASEL */
01561 #if defined(RCC_CDCCIP1R_SAI2BSEL)
01562   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
01563 #endif /* RCC_CDCCIP1R_SAI2BSEL */
01564 #if defined(SAI3)
01565   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
01566 #endif /* SAI3 */
01567 #if defined(SAI4)
01568   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
01569   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
01570 #endif /* SAI4 */
01571 #if defined(DFSDM2_BASE)
01572   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
01573 #endif /* DFSDM2 */
01574 #if defined(QUADSPI)
01575   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
01576 #endif /* QUADSPI */
01577 #if defined(OCTOSPI1) || defined(OCTOSPI2)
01578   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
01579 #endif /* OCTOSPI1 || OCTOSPI2 */
01580 #if defined(HRTIM)
01581   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
01582 #endif /* HRTIM */
01583 #if defined(LTDC)
01584   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
01585 #endif /* LTDC */
01586 #if defined(DSI)
01587   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
01588 #endif /* DSI */
01589
01590   /* Get the PLL3 Clock configuration -----------------------------------------------*/
01591   PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
01592   PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
01593   PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
01594   PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
01595   PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
01596   PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
01597   PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
01598
01599   /* Get the PLL2 Clock configuration -----------------------------------------------*/
01600   PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
01601   PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
01602   PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
01603   PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
01604   PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
01605   PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
01606   PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
01607
01608   /* Get the USART1 configuration --------------------------------------------*/
01609   PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
01610   /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
01611   PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
01612   /* Get the LPUART1 clock source --------------------------------------------*/
01613   PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
01614   /* Get the I2C1/2/3 clock source -------------------------------------------*/
01615   PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
01616   /* Get the LPTIM1 clock source ---------------------------------------------*/
01617   PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
01618   /* Get the LPTIM2 clock source ---------------------------------------------*/
01619   PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
01620   /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
01621   PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
01622   /* Get the SAI1 clock source -----------------------------------------------*/
01623   PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
01624 #if defined(SAI3)
01625   /* Get the SAI2/3 clock source ---------------------------------------------*/
01626   PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
01627 #endif  /*SAI3*/
01628 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
01629   /* Get the SAI2A clock source ---------------------------------------------*/
01630   PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
01631 #endif  /*SAI2A*/
01632 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
01633   /* Get the SAI2B clock source ---------------------------------------------*/
01634   PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
01635 #endif  /*SAI2B*/
01636 #if defined(SAI4)
01637   /* Get the SAI4A clock source ----------------------------------------------*/
01638   PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
01639   /* Get the SAI4B clock source ----------------------------------------------*/
01640   PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
01641 #endif  /*SAI4*/
01642   /* Get the RTC clock source ------------------------------------------------*/
01643   PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
01644   /* Get the USB clock source ------------------------------------------------*/
01645   PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
01646   /* Get the SDMMC clock source ----------------------------------------------*/
01647   PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
01648   /* Get the RNG clock source ------------------------------------------------*/
01649   PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
01650 #if defined(HRTIM1)
01651   /* Get the HRTIM1 clock source ---------------------------------------------*/
01652   PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
01653 #endif /* HRTIM1 */
01654   /* Get the ADC clock source ------------------------------------------------*/
01655   PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
01656   /* Get the SWPMI1 clock source ---------------------------------------------*/
01657   PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
01658   /* Get the DFSDM1 clock source ---------------------------------------------*/
01659   PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
01660 #if defined(DFSDM2_BASE)
01661   /* Get the DFSDM2 clock source ---------------------------------------------*/
01662   PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
01663 #endif /* DFSDM2 */
01664   /* Get the SPDIFRX clock source --------------------------------------------*/
01665   PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
01666   /* Get the SPI1/2/3 clock source -------------------------------------------*/
01667   PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
01668   /* Get the SPI4/5 clock source ---------------------------------------------*/
01669   PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
01670   /* Get the SPI6 clock source -----------------------------------------------*/
01671   PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
01672   /* Get the FDCAN clock source ----------------------------------------------*/
01673   PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
01674   /* Get the CEC clock source ------------------------------------------------*/
01675   PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
01676   /* Get the FMC clock source ------------------------------------------------*/
01677   PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
01678 #if defined(QUADSPI)
01679   /* Get the QSPI clock source -----------------------------------------------*/
01680   PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
01681 #endif /* QUADSPI */
01682 #if defined(OCTOSPI1) || defined(OCTOSPI2)
01683   /* Get the OSPI clock source -----------------------------------------------*/
01684   PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
01685 #endif /* OCTOSPI1 || OCTOSPI2 */
01686
01687 #if defined(DSI)
01688   /* Get the DSI clock source ------------------------------------------------*/
01689   PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
01690 #endif /*DSI*/
01691
01692   /* Get the CKPER clock source ----------------------------------------------*/
01693   PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
01694
01695   /* Get the TIM Prescaler configuration -------------------------------------*/
01696   if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
01697   {
01698     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
01699   }
01700   else
01701   {
01702     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
01703   }
01704 }
01705
01706 /**
01707   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
01708   * @note   Return 0 if peripheral clock identifier not managed by this API
01709   * @param  PeriphClk: Peripheral clock identifier
01710   *         This parameter can be one of the following values:
01711   *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
01712   *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
01713   *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
01714   *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
01715   *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
01716   *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
01717   *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
01718   *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
01719   *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
01720   *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
01721   * @retval Frequency in KHz
01722   *
01723   *  (*) : Available on some STM32H7 lines only.
01724   */
01725 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
01726 {
01727   PLL1_ClocksTypeDef pll1_clocks;
01728   PLL2_ClocksTypeDef pll2_clocks;
01729   PLL3_ClocksTypeDef pll3_clocks;
01730
01731   /* This variable is used to store the SAI clock frequency (value in Hz) */
01732   uint32_t frequency;
01733   /* This variable is used to store the SAI and CKP clock source */
01734   uint32_t saiclocksource;
01735   uint32_t ckpclocksource;
01736   uint32_t srcclk;
01737
01738   if (PeriphClk == RCC_PERIPHCLK_SAI1)
01739     {
01740
01741       saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
01742
01743       switch (saiclocksource)
01744       {
01745       case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
01746         {
01747           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
01748           frequency = pll1_clocks.PLL1_Q_Frequency;
01749           break;
01750         }
01751       case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
01752         {
01753           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01754           frequency = pll2_clocks.PLL2_P_Frequency;
01755           break;
01756         }
01757
01758       case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
01759         {
01760           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01761           frequency = pll3_clocks.PLL3_P_Frequency;
01762           break;
01763         }
01764
01765       case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
01766         {
01767
01768           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
01769
01770           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
01771           {
01772             /* In Case the CKPER Source is HSI */
01773             frequency = HSI_VALUE;
01774           }
01775
01776           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
01777           {
01778             /* In Case the CKPER Source is CSI */
01779             frequency = CSI_VALUE;
01780           }
01781
01782           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
01783           {
01784             /* In Case the CKPER Source is HSE */
01785             frequency = HSE_VALUE;
01786           }
01787
01788           else
01789           {
01790             /* In Case the CKPER is disabled*/
01791             frequency = 0;
01792           }
01793
01794           break;
01795         }
01796
01797       case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
01798         {
01799           frequency = EXTERNAL_CLOCK_VALUE;
01800           break;
01801         }
01802       default :
01803         {
01804           frequency = 0;
01805           break;
01806         }
01807       }
01808     }
01809
01810 #if defined(SAI3)
01811   else if (PeriphClk == RCC_PERIPHCLK_SAI23)
01812     {
01813
01814       saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
01815
01816       switch (saiclocksource)
01817       {
01818       case 0: /* PLL1 is the clock source for SAI2/3 */
01819         {
01820           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
01821           frequency = pll1_clocks.PLL1_Q_Frequency;
01822           break;
01823         }
01824       case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
01825         {
01826           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01827           frequency = pll2_clocks.PLL2_P_Frequency;
01828           break;
01829         }
01830
01831       case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
01832         {
01833           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01834           frequency = pll3_clocks.PLL3_P_Frequency;
01835           break;
01836         }
01837
01838       case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
01839         {
01840
01841           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
01842
01843           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
01844           {
01845             /* In Case the CKPER Source is HSI */
01846             frequency = HSI_VALUE;
01847           }
01848
01849           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
01850           {
01851             /* In Case the CKPER Source is CSI */
01852             frequency = CSI_VALUE;
01853           }
01854
01855           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
01856           {
01857             /* In Case the CKPER Source is HSE */
01858             frequency = HSE_VALUE;
01859           }
01860
01861           else
01862           {
01863             /* In Case the CKPER is disabled*/
01864             frequency = 0;
01865           }
01866
01867           break;
01868         }
01869
01870       case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
01871         {
01872           frequency = EXTERNAL_CLOCK_VALUE;
01873           break;
01874         }
01875       default :
01876         {
01877           frequency = 0;
01878           break;
01879         }
01880       }
01881     }
01882 #endif /* SAI3 */
01883
01884 #if  defined(RCC_CDCCIP1R_SAI2ASEL)
01885
01886     else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
01887     {
01888       saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
01889
01890       switch (saiclocksource)
01891       {
01892       case 0: /* PLL1 is the clock source for SAI2A */
01893         {
01894           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
01895           frequency = pll1_clocks.PLL1_Q_Frequency;
01896           break;
01897         }
01898       case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
01899         {
01900           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01901           frequency = pll2_clocks.PLL2_P_Frequency;
01902           break;
01903         }
01904
01905       case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
01906         {
01907           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01908           frequency = pll3_clocks.PLL3_P_Frequency;
01909           break;
01910         }
01911
01912       case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
01913         {
01914
01915           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
01916
01917           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
01918           {
01919             /* In Case the CKPER Source is HSI */
01920             frequency = HSI_VALUE;
01921           }
01922
01923           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
01924           {
01925             /* In Case the CKPER Source is CSI */
01926             frequency = CSI_VALUE;
01927           }
01928
01929           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
01930           {
01931             /* In Case the CKPER Source is HSE */
01932             frequency = HSE_VALUE;
01933           }
01934
01935           else
01936           {
01937             /* In Case the CKPER is disabled*/
01938             frequency = 0;
01939           }
01940
01941           break;
01942         }
01943
01944       case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
01945         {
01946           frequency = EXTERNAL_CLOCK_VALUE;
01947           break;
01948         }
01949
01950       default :
01951         {
01952           frequency = 0;
01953           break;
01954         }
01955       }
01956
01957     }
01958 #endif
01959
01960 #if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
01961   else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
01962     {
01963
01964       saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
01965
01966       switch (saiclocksource)
01967       {
01968       case 0: /* PLL1 is the clock source for SAI2B */
01969         {
01970           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
01971           frequency = pll1_clocks.PLL1_Q_Frequency;
01972           break;
01973         }
01974       case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
01975         {
01976           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01977           frequency = pll2_clocks.PLL2_P_Frequency;
01978           break;
01979         }
01980
01981       case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
01982         {
01983           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01984           frequency = pll3_clocks.PLL3_P_Frequency;
01985           break;
01986         }
01987
01988       case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
01989         {
01990
01991           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
01992
01993           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
01994           {
01995             /* In Case the CKPER Source is HSI */
01996             frequency = HSI_VALUE;
01997           }
01998
01999           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02000           {
02001             /* In Case the CKPER Source is CSI */
02002             frequency = CSI_VALUE;
02003           }
02004
02005           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02006           {
02007             /* In Case the CKPER Source is HSE */
02008             frequency = HSE_VALUE;
02009           }
02010
02011           else
02012           {
02013             /* In Case the CKPER is disabled*/
02014             frequency = 0;
02015           }
02016           break;
02017         }
02018
02019       case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
02020         {
02021           frequency = EXTERNAL_CLOCK_VALUE;
02022           break;
02023         }
02024
02025       default :
02026         {
02027           frequency = 0;
02028           break;
02029         }
02030       }
02031     }
02032 #endif
02033
02034 #if defined(SAI4)
02035   else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
02036     {
02037
02038       saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
02039
02040       switch (saiclocksource)
02041       {
02042       case 0: /* PLL1 is the clock source for SAI4A */
02043         {
02044           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02045           frequency = pll1_clocks.PLL1_Q_Frequency;
02046           break;
02047         }
02048       case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
02049         {
02050           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02051           frequency = pll2_clocks.PLL2_P_Frequency;
02052           break;
02053         }
02054
02055       case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
02056         {
02057           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02058           frequency = pll3_clocks.PLL3_P_Frequency;
02059           break;
02060         }
02061
02062       case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
02063         {
02064
02065           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02066
02067           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
02068           {
02069             /* In Case the CKPER Source is HSI */
02070             frequency = HSI_VALUE;
02071           }
02072
02073           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02074           {
02075             /* In Case the CKPER Source is CSI */
02076             frequency = CSI_VALUE;
02077           }
02078
02079           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02080           {
02081             /* In Case the CKPER Source is HSE */
02082             frequency = HSE_VALUE;
02083           }
02084
02085           else
02086           {
02087             /* In Case the CKPER is disabled*/
02088             frequency = 0;
02089           }
02090
02091           break;
02092         }
02093
02094       case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
02095         {
02096           frequency = EXTERNAL_CLOCK_VALUE;
02097           break;
02098         }
02099
02100       default :
02101         {
02102           frequency = 0;
02103           break;
02104         }
02105       }
02106     }
02107
02108   else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
02109     {
02110
02111       saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
02112
02113       switch (saiclocksource)
02114       {
02115       case 0: /* PLL1 is the clock source for SAI4B */
02116         {
02117           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02118           frequency = pll1_clocks.PLL1_Q_Frequency;
02119           break;
02120         }
02121       case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
02122         {
02123           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02124           frequency = pll2_clocks.PLL2_P_Frequency;
02125           break;
02126         }
02127
02128       case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
02129         {
02130           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02131           frequency = pll3_clocks.PLL3_P_Frequency;
02132           break;
02133         }
02134
02135       case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
02136         {
02137
02138           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02139
02140           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
02141           {
02142             /* In Case the CKPER Source is HSI */
02143             frequency = HSI_VALUE;
02144           }
02145
02146           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02147           {
02148             /* In Case the CKPER Source is CSI */
02149             frequency = CSI_VALUE;
02150           }
02151
02152           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02153           {
02154             /* In Case the CKPER Source is HSE */
02155             frequency = HSE_VALUE;
02156           }
02157
02158           else
02159           {
02160             /* In Case the CKPER is disabled*/
02161             frequency = 0;
02162           }
02163
02164           break;
02165         }
02166
02167       case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
02168         {
02169           frequency = EXTERNAL_CLOCK_VALUE;
02170           break;
02171         }
02172
02173       default :
02174         {
02175           frequency = 0;
02176           break;
02177         }
02178       }
02179     }
02180 #endif /*SAI4*/
02181   else if (PeriphClk == RCC_PERIPHCLK_SPI123)
02182     {
02183       /* Get SPI1/2/3 clock source */
02184       srcclk= __HAL_RCC_GET_SPI123_SOURCE();
02185
02186       switch (srcclk)
02187       {
02188       case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
02189         {
02190           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02191           frequency = pll1_clocks.PLL1_Q_Frequency;
02192           break;
02193         }
02194       case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
02195         {
02196           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02197           frequency = pll2_clocks.PLL2_P_Frequency;
02198           break;
02199         }
02200
02201       case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
02202         {
02203           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02204           frequency = pll3_clocks.PLL3_P_Frequency;
02205           break;
02206         }
02207
02208       case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
02209         {
02210
02211           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02212
02213           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
02214           {
02215             /* In Case the CKPER Source is HSI */
02216             frequency = HSI_VALUE;
02217           }
02218
02219           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02220           {
02221             /* In Case the CKPER Source is CSI */
02222             frequency = CSI_VALUE;
02223           }
02224
02225           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02226           {
02227             /* In Case the CKPER Source is HSE */
02228             frequency = HSE_VALUE;
02229           }
02230
02231           else
02232           {
02233             /* In Case the CKPER is disabled*/
02234             frequency = 0;
02235           }
02236
02237           break;
02238         }
02239
02240       case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
02241         {
02242           frequency = EXTERNAL_CLOCK_VALUE;
02243           break;
02244         }
02245       default :
02246         {
02247           frequency = 0;
02248           break;
02249         }
02250       }
02251     }
02252   else if (PeriphClk == RCC_PERIPHCLK_ADC)
02253     {
02254       /* Get ADC clock source */
02255       srcclk= __HAL_RCC_GET_ADC_SOURCE();
02256
02257       switch (srcclk)
02258       {
02259       case RCC_ADCCLKSOURCE_PLL2:
02260         {
02261           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02262           frequency = pll2_clocks.PLL2_P_Frequency;
02263           break;
02264         }
02265       case RCC_ADCCLKSOURCE_PLL3:
02266         {
02267           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02268           frequency = pll3_clocks.PLL3_R_Frequency;
02269           break;
02270         }
02271
02272       case RCC_ADCCLKSOURCE_CLKP:
02273         {
02274
02275           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02276
02277           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
02278           {
02279             /* In Case the CKPER Source is HSI */
02280             frequency = HSI_VALUE;
02281           }
02282
02283           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02284           {
02285             /* In Case the CKPER Source is CSI */
02286             frequency = CSI_VALUE;
02287           }
02288
02289           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02290           {
02291             /* In Case the CKPER Source is HSE */
02292             frequency = HSE_VALUE;
02293           }
02294
02295           else
02296           {
02297             /* In Case the CKPER is disabled*/
02298             frequency = 0;
02299           }
02300
02301           break;
02302         }
02303
02304       default :
02305         {
02306           frequency = 0;
02307           break;
02308         }
02309       }
02310     }
02311   else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
02312     {
02313       /* Get SDMMC clock source */
02314       srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
02315
02316       switch (srcclk)
02317       {
02318       case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
02319         {
02320           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02321           frequency = pll1_clocks.PLL1_Q_Frequency;
02322           break;
02323         }
02324       case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
02325         {
02326           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02327           frequency = pll2_clocks.PLL2_R_Frequency;
02328           break;
02329         }
02330
02331       default :
02332         {
02333           frequency = 0;
02334           break;
02335         }
02336       }
02337     }
02338   else if (PeriphClk == RCC_PERIPHCLK_SPI6)
02339     {
02340       /* Get SPI6 clock source */
02341       srcclk= __HAL_RCC_GET_SPI6_SOURCE();
02342
02343       switch (srcclk)
02344       {
02345       case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
02346         {
02347           frequency = HAL_RCCEx_GetD3PCLK1Freq();
02348           break;
02349         }
02350       case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
02351         {
02352           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02353           frequency = pll2_clocks.PLL2_Q_Frequency;
02354           break;
02355         }
02356       case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
02357         {
02358           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02359           frequency = pll3_clocks.PLL3_Q_Frequency;
02360           break;
02361         }
02362       case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
02363         {
02364           frequency = HSI_VALUE;
02365           break;
02366         }
02367       case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
02368         {
02369           frequency = CSI_VALUE;
02370           break;
02371         }
02372       case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
02373         {
02374           frequency = HSE_VALUE;
02375           break;
02376         }
02377 #if defined(RCC_SPI6CLKSOURCE_PIN)
02378       case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
02379         {
02380           frequency = EXTERNAL_CLOCK_VALUE;
02381           break;
02382         }
02383 #endif /* RCC_SPI6CLKSOURCE_PIN */
02384       default :
02385         {
02386           frequency = 0;
02387           break;
02388         }
02389       }
02390     }
02391   else
02392     {
02393       frequency = 0;
02394     }
02395
02396   return frequency;
02397 }
02398
02399
02400 /**
02401   * @brief  Returns the D1PCLK1 frequency
02402   * @note   Each time D1PCLK1 changes, this function must be called to update the
02403   *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
02404   * @retval D1PCLK1 frequency
02405   */
02406 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
02407 {
02408 #if defined(RCC_D1CFGR_D1PPRE)
02409   /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
02410   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
02411 #else
02412 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
02413   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
02414 #endif
02415 }
02416
02417 /**
02418   * @brief  Returns the D3PCLK1 frequency
02419   * @note   Each time D3PCLK1 changes, this function must be called to update the
02420   *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
02421   * @retval D3PCLK1 frequency
02422   */
02423 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
02424 {
02425 #if defined(RCC_D3CFGR_D3PPRE)
02426   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
02427   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
02428 #else
02429   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
02430   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
02431 #endif
02432 }
02433 /**
02434 * @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
02435   * @note   The PLL2 clock frequencies computed by this function is not the real
02436   *         frequency in the chip. It is calculated based on the predefined
02437   *         constant and the selected clock source:
02438   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02439   * @note   This function can be used by the user application to compute the
02440   *         baud-rate for the communication peripherals or configure other parameters.
02441   *
02442   * @note   Each time PLL2CLK changes, this function must be called to update the
02443   *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
02444   * @param  PLL2_Clocks structure.
02445   * @retval None
02446   */
02447 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
02448 {
02449   uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
02450   float_t fracn2, pll2vco;
02451
02452   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
02453      PLL2xCLK = PLL2_VCO / PLL2x
02454   */
02455   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02456   pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
02457   pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
02458   fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
02459
02460   if (pll2m != 0U)
02461   {
02462     switch (pllsource)
02463     {
02464
02465     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
02466
02467       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02468       {
02469         hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02470         pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
02471       }
02472       else
02473       {
02474         pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
02475       }
02476       break;
02477
02478     case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
02479       pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
02480       break;
02481
02482     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
02483       pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
02484       break;
02485
02486     default:
02487       pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
02488       break;
02489     }
02490     PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
02491     PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
02492     PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
02493   }
02494   else
02495   {
02496     PLL2_Clocks->PLL2_P_Frequency = 0U;
02497     PLL2_Clocks->PLL2_Q_Frequency = 0U;
02498     PLL2_Clocks->PLL2_R_Frequency = 0U;
02499   }
02500 }
02501
02502 /**
02503 * @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
02504   * @note   The PLL3 clock frequencies computed by this function is not the real
02505   *         frequency in the chip. It is calculated based on the predefined
02506   *         constant and the selected clock source:
02507   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02508   * @note   This function can be used by the user application to compute the
02509   *         baud-rate for the communication peripherals or configure other parameters.
02510   *
02511   * @note   Each time PLL3CLK changes, this function must be called to update the
02512   *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
02513   * @param  PLL3_Clocks structure.
02514   * @retval None
02515   */
02516 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
02517 {
02518   uint32_t pllsource, pll3m, pll3fracen, hsivalue;
02519   float_t fracn3, pll3vco;
02520
02521   /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
02522      PLL3xCLK = PLL3_VCO / PLLxR
02523   */
02524   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02525   pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
02526   pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
02527   fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
02528
02529   if (pll3m != 0U)
02530   {
02531     switch (pllsource)
02532     {
02533     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
02534
02535       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02536       {
02537         hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02538         pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
02539       }
02540       else
02541       {
02542         pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
02543       }
02544       break;
02545     case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
02546       pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
02547       break;
02548
02549     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
02550       pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
02551       break;
02552
02553     default:
02554       pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
02555       break;
02556     }
02557     PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
02558     PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
02559     PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
02560   }
02561   else
02562   {
02563     PLL3_Clocks->PLL3_P_Frequency = 0U;
02564     PLL3_Clocks->PLL3_Q_Frequency = 0U;
02565     PLL3_Clocks->PLL3_R_Frequency = 0U;
02566   }
02567
02568 }
02569
02570 /**
02571 * @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
02572   * @note   The PLL1 clock frequencies computed by this function is not the real
02573   *         frequency in the chip. It is calculated based on the predefined
02574   *         constant and the selected clock source:
02575   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02576   * @note   This function can be used by the user application to compute the
02577   *         baud-rate for the communication peripherals or configure other parameters.
02578   *
02579   * @note   Each time PLL1CLK changes, this function must be called to update the
02580   *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
02581   * @param  PLL1_Clocks structure.
02582   * @retval None
02583   */
02584 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
02585 {
02586   uint32_t pllsource, pll1m, pll1fracen, hsivalue;
02587   float_t fracn1, pll1vco;
02588
02589   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02590   pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
02591   pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
02592   fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
02593
02594   if (pll1m != 0U)
02595   {
02596     switch (pllsource)
02597     {
02598
02599     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
02600
02601       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02602       {
02603         hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02604         pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
02605       }
02606       else
02607       {
02608         pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
02609       }
02610       break;
02611     case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
02612       pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
02613       break;
02614
02615     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
02616       pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
02617       break;
02618
02619     default:
02620       pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
02621       break;
02622     }
02623
02624     PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
02625     PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
02626     PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
02627   }
02628   else
02629   {
02630     PLL1_Clocks->PLL1_P_Frequency = 0U;
02631     PLL1_Clocks->PLL1_Q_Frequency = 0U;
02632     PLL1_Clocks->PLL1_R_Frequency = 0U;
02633   }
02634
02635 }
02636
02637 /**
02638   * @brief  Returns the main Core frequency
02639   * @note   Each time core clock changes, this function must be called to update the
02640   *         right system core clock value. Otherwise, any configuration based on this function will be incorrect.
02641   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
02642   *         and updated within this function
02643   * @retval HCLK frequency
02644   */
02645 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
02646 {
02647 #if defined(RCC_D1CFGR_D1CPRE)
02648   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
02649 #else
02650   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
02651 #endif
02652   return SystemCoreClock;
02653 }
02654 /**
02655   * @}
02656   */
02657
02658 /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
02659  *  @brief  Extended Peripheral Control functions
02660   * @{
02661   */
02662 /**
02663   * @brief  Enables the LSE Clock Security System.
02664   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
02665   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
02666   *         clock with HAL_RCCEx_PeriphCLKConfig().
02667   * @retval None
02668   */
02669 void HAL_RCCEx_EnableLSECSS(void)
02670 {
02671   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
02672 }
02673
02674 /**
02675   * @brief  Disables the LSE Clock Security System.
02676   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
02677   * @retval None
02678   */
02679 void HAL_RCCEx_DisableLSECSS(void)
02680 {
02681   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
02682   /* Disable LSE CSS IT if any */
02683   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
02684 }
02685
02686 /**
02687   * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
02688   * @param  WakeUpClk: Wakeup clock
02689   *         This parameter can be one of the following values:
02690   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
02691   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
02692   * @note   This function shall not be called after the Clock Security System on HSE has been
02693   *         enabled.
02694   * @retval None
02695   */
02696 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
02697 {
02698   assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
02699
02700   __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
02701 }
02702
02703 /**
02704   * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
02705   * @param  WakeUpClk: Kernel Wakeup clock
02706   *         This parameter can be one of the following values:
02707   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
02708   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
02709   * @retval None
02710   */
02711 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
02712 {
02713   assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
02714
02715   __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
02716 }
02717
02718 #if defined(DUAL_CORE)
02719 /**
02720   * @brief  Enable COREx boot independently of CMx_B option byte value
02721   * @param  RCC_BootCx: Boot Core to be enabled
02722   *         This parameter can be one of the following values:
02723   *            @arg RCC_BOOT_C1: CM7 core selection
02724   *            @arg RCC_BOOT_C2: CM4 core selection
02725   * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
02726   *
02727   * @retval None
02728   */
02729 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
02730 {
02731   assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
02732   SET_BIT(RCC->GCR, RCC_BootCx) ;
02733 }
02734
02735 #endif /*DUAL_CORE*/
02736
02737 #if defined(DUAL_CORE)
02738 /**
02739   * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
02740   * @param  RCC_WWDGx: WWDGx to be configured
02741   *         This parameter can be one of the following values:
02742   *            @arg RCC_WWDG1: WWDG1 generates system reset
02743   *            @arg RCC_WWDG2: WWDG2 generates system reset
02744   * @note   This bit can be set by software but is cleared by hardware during a system reset
02745   *
02746   * @retval None
02747   */
02748 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
02749 {
02750   assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
02751   SET_BIT(RCC->GCR, RCC_WWDGx) ;
02752 }
02753
02754 #else
02755 #if defined(RCC_GCR_WW1RSC)
02756 /**
02757   * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
02758   * @param  RCC_WWDGx: WWDGx to be configured
02759   *         This parameter can be one of the following values:
02760   *            @arg RCC_WWDG1: WWDG1 generates system reset
02761   * @note   This bit can be set by software but is cleared by hardware during a system reset
02762   *
02763   * @retval None
02764   */
02765 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
02766 {
02767   assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
02768   SET_BIT(RCC->GCR, RCC_WWDGx) ;
02769 }
02770 #endif
02771 #endif /*DUAL_CORE*/
02772
02773 /**
02774   * @}
02775   */
02776
02777 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
02778  *  @brief  Extended Clock Recovery System Control functions
02779  *
02780 @verbatim
02781  ===============================================================================
02782                 ##### Extended Clock Recovery System Control functions  #####
02783  ===============================================================================
02784     [..]
02785       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
02786
02787       (#) In System clock config, HSI48 needs to be enabled
02788
02789       (#) Enable CRS clock in IP MSP init which will use CRS functions
02790
02791       (#) Call CRS functions as follows:
02792           (##) Prepare synchronization configuration necessary for HSI48 calibration
02793               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
02794                         and also HSI48 oscillator smooth trimming.
02795               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
02796                         directly reload value with target and synchronization frequencies values
02797           (##) Call function HAL_RCCEx_CRSConfig which
02798               (+++) Resets CRS registers to their default values.
02799               (+++) Configures CRS registers with synchronization configuration
02800               (+++) Enables automatic calibration and frequency error counter feature
02801            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
02802            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
02803            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
02804            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
02805            should be used as SYNC signal.
02806
02807           (##) A polling function is provided to wait for complete synchronization
02808               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
02809               (+++) According to CRS status, user can decide to adjust again the calibration or continue
02810                         application if synchronization is OK
02811
02812       (#) User can retrieve information related to synchronization in calling function
02813             HAL_RCCEx_CRSGetSynchronizationInfo()
02814
02815       (#) Regarding synchronization status and synchronization information, user can try a new calibration
02816            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
02817            Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
02818            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
02819            incremented), while when it is detected during the up-counting phase it means that the actual frequency
02820            is higher (and that the TRIM value should be decremented).
02821
02822       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
02823           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
02824               (++) Call function HAL_RCCEx_CRSConfig()
02825               (++) Enable CRS_IRQn (thanks to NVIC functions)
02826               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
02827               (++) Implement CRS status management in the following user callbacks called from
02828                    HAL_RCCEx_CRS_IRQHandler():
02829                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
02830                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
02831                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
02832                    (+++) HAL_RCCEx_CRS_ErrorCallback()
02833
02834       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
02835           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
02836
02837 @endverbatim
02838  * @{
02839  */
02840
02841 /**
02842   * @brief  Start automatic synchronization for polling mode
02843   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
02844   * @retval None
02845   */
02846 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
02847 {
02848   uint32_t value;
02849
02850   /* Check the parameters */
02851   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
02852   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
02853   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
02854   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
02855   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
02856   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
02857
02858   /* CONFIGURATION */
02859
02860   /* Before configuration, reset CRS registers to their default values*/
02861   __HAL_RCC_CRS_FORCE_RESET();
02862   __HAL_RCC_CRS_RELEASE_RESET();
02863
02864   /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
02865   /* Set the SYNCSRC[1:0] bits according to Source value */
02866   /* Set the SYNCSPOL bit according to Polarity value */
02867   if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
02868   {
02869     /* Use Rev.Y value of USB2 */
02870     value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
02871   }
02872   else
02873   {
02874     value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
02875   }
02876   /* Set the RELOAD[15:0] bits according to ReloadValue value */
02877   value |= pInit->ReloadValue;
02878   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
02879   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
02880   WRITE_REG(CRS->CFGR, value);
02881
02882   /* Adjust HSI48 oscillator smooth trimming */
02883   /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
02884   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
02885
02886   /* START AUTOMATIC SYNCHRONIZATION*/
02887
02888   /* Enable Automatic trimming & Frequency error counter */
02889   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
02890 }
02891
02892 /**
02893   * @brief  Generate the software synchronization event
02894   * @retval None
02895   */
02896 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
02897 {
02898   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
02899 }
02900
02901 /**
02902   * @brief  Return synchronization info
02903   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
02904   * @retval None
02905   */
02906 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
02907 {
02908   /* Check the parameter */
02909   assert_param(pSynchroInfo != (void *)NULL);
02910
02911   /* Get the reload value */
02912   pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
02913
02914   /* Get HSI48 oscillator smooth trimming */
02915   pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
02916
02917   /* Get Frequency error capture */
02918   pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
02919
02920   /* Get Frequency error direction */
02921   pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
02922 }
02923
02924 /**
02925 * @brief Wait for CRS Synchronization status.
02926 * @param Timeout  Duration of the time-out
02927 * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
02928 *        frequency.
02929 * @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
02930 * @retval Combination of Synchronization status
02931 *          This parameter can be a combination of the following values:
02932 *            @arg @ref RCC_CRS_TIMEOUT
02933 *            @arg @ref RCC_CRS_SYNCOK
02934 *            @arg @ref RCC_CRS_SYNCWARN
02935 *            @arg @ref RCC_CRS_SYNCERR
02936 *            @arg @ref RCC_CRS_SYNCMISS
02937 *            @arg @ref RCC_CRS_TRIMOVF
02938 */
02939 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
02940 {
02941   uint32_t crsstatus = RCC_CRS_NONE;
02942   uint32_t tickstart;
02943
02944   /* Get time-out */
02945   tickstart = HAL_GetTick();
02946
02947   /* Wait for CRS flag or time-out detection */
02948   do
02949   {
02950     if(Timeout != HAL_MAX_DELAY)
02951     {
02952       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02953       {
02954         crsstatus = RCC_CRS_TIMEOUT;
02955       }
02956     }
02957     /* Check CRS SYNCOK flag  */
02958     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
02959     {
02960       /* CRS SYNC event OK */
02961       crsstatus |= RCC_CRS_SYNCOK;
02962
02963       /* Clear CRS SYNC event OK bit */
02964       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
02965     }
02966
02967     /* Check CRS SYNCWARN flag  */
02968     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
02969     {
02970       /* CRS SYNC warning */
02971       crsstatus |= RCC_CRS_SYNCWARN;
02972
02973       /* Clear CRS SYNCWARN bit */
02974       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
02975     }
02976
02977     /* Check CRS TRIM overflow flag  */
02978     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
02979     {
02980       /* CRS SYNC Error */
02981       crsstatus |= RCC_CRS_TRIMOVF;
02982
02983       /* Clear CRS Error bit */
02984       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
02985     }
02986
02987     /* Check CRS Error flag  */
02988     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
02989     {
02990       /* CRS SYNC Error */
02991       crsstatus |= RCC_CRS_SYNCERR;
02992
02993       /* Clear CRS Error bit */
02994       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
02995     }
02996
02997     /* Check CRS SYNC Missed flag  */
02998     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
02999     {
03000       /* CRS SYNC Missed */
03001       crsstatus |= RCC_CRS_SYNCMISS;
03002
03003       /* Clear CRS SYNC Missed bit */
03004       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
03005     }
03006
03007     /* Check CRS Expected SYNC flag  */
03008     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
03009     {
03010       /* frequency error counter reached a zero value */
03011       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
03012     }
03013   } while(RCC_CRS_NONE == crsstatus);
03014
03015   return crsstatus;
03016 }
03017
03018 /**
03019   * @brief Handle the Clock Recovery System interrupt request.
03020   * @retval None
03021   */
03022 void HAL_RCCEx_CRS_IRQHandler(void)
03023 {
03024   uint32_t crserror = RCC_CRS_NONE;
03025   /* Get current IT flags and IT sources values */
03026   uint32_t itflags = READ_REG(CRS->ISR);
03027   uint32_t itsources = READ_REG(CRS->CR);
03028
03029   /* Check CRS SYNCOK flag  */
03030   if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
03031   {
03032     /* Clear CRS SYNC event OK flag */
03033     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
03034
03035     /* user callback */
03036     HAL_RCCEx_CRS_SyncOkCallback();
03037   }
03038   /* Check CRS SYNCWARN flag  */
03039   else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
03040   {
03041     /* Clear CRS SYNCWARN flag */
03042     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
03043
03044     /* user callback */
03045     HAL_RCCEx_CRS_SyncWarnCallback();
03046   }
03047   /* Check CRS Expected SYNC flag  */
03048   else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
03049   {
03050     /* frequency error counter reached a zero value */
03051     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
03052
03053     /* user callback */
03054     HAL_RCCEx_CRS_ExpectedSyncCallback();
03055   }
03056   /* Check CRS Error flags  */
03057   else
03058   {
03059     if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
03060     {
03061       if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
03062       {
03063         crserror |= RCC_CRS_SYNCERR;
03064       }
03065       if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
03066       {
03067         crserror |= RCC_CRS_SYNCMISS;
03068       }
03069       if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
03070       {
03071         crserror |= RCC_CRS_TRIMOVF;
03072       }
03073
03074       /* Clear CRS Error flags */
03075       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
03076
03077       /* user error callback */
03078       HAL_RCCEx_CRS_ErrorCallback(crserror);
03079     }
03080   }
03081 }
03082
03083 /**
03084   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
03085   * @retval none
03086   */
03087 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
03088 {
03089   /* NOTE : This function should not be modified, when the callback is needed,
03090             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
03091    */
03092 }
03093
03094 /**
03095   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
03096   * @retval none
03097   */
03098 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
03099 {
03100   /* NOTE : This function should not be modified, when the callback is needed,
03101             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
03102    */
03103 }
03104
03105 /**
03106   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
03107   * @retval none
03108   */
03109 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
03110 {
03111   /* NOTE : This function should not be modified, when the callback is needed,
03112             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
03113    */
03114 }
03115
03116 /**
03117   * @brief  RCCEx Clock Recovery System Error interrupt callback.
03118   * @param  Error Combination of Error status.
03119   *         This parameter can be a combination of the following values:
03120   *           @arg @ref RCC_CRS_SYNCERR
03121   *           @arg @ref RCC_CRS_SYNCMISS
03122   *           @arg @ref RCC_CRS_TRIMOVF
03123   * @retval none
03124   */
03125 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
03126 {
03127   /* Prevent unused argument(s) compilation warning */
03128   UNUSED(Error);
03129
03130   /* NOTE : This function should not be modified, when the callback is needed,
03131             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
03132    */
03133 }
03134
03135
03136 /**
03137   * @}
03138   */
03139
03140 /**
03141   * @}
03142   */
03143
03144 /** @defgroup RCCEx_Private_functions Private Functions
03145  * @{
03146  */
03147 /**
03148   * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
03149   * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
03150   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
03151   * @param  Divider  divider parameter to be updated
03152   * @note   PLL2 is temporary disabled to apply new parameters
03153   *
03154   * @retval HAL status
03155   */
03156 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
03157 {
03158
03159   uint32_t tickstart;
03160   HAL_StatusTypeDef status = HAL_OK;
03161   assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
03162   assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
03163   assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
03164   assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
03165   assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
03166   assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
03167   assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
03168   assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
03169
03170   /* Check that PLL2 OSC clock source is already set */
03171   if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
03172   {
03173     return HAL_ERROR;
03174   }
03175
03176
03177   else
03178   {
03179     /* Disable  PLL2. */
03180     __HAL_RCC_PLL2_DISABLE();
03181
03182     /* Get Start Tick*/
03183     tickstart = HAL_GetTick();
03184
03185     /* Wait till PLL is disabled */
03186     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
03187     {
03188       if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
03189       {
03190         return HAL_TIMEOUT;
03191       }
03192     }
03193
03194     /* Configure PLL2 multiplication and division factors. */
03195     __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
03196                           pll2->PLL2N,
03197                           pll2->PLL2P,
03198                           pll2->PLL2Q,
03199                           pll2->PLL2R);
03200
03201     /* Select PLL2 input reference frequency range: VCI */
03202     __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
03203
03204     /* Select PLL2 output frequency range : VCO */
03205     __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
03206
03207     /* Disable PLL2FRACN . */
03208     __HAL_RCC_PLL2FRACN_DISABLE();
03209
03210     /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
03211     __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
03212
03213     /* Enable PLL2FRACN . */
03214     __HAL_RCC_PLL2FRACN_ENABLE();
03215
03216     /* Enable the PLL2 clock output */
03217     if(Divider == DIVIDER_P_UPDATE)
03218     {
03219       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
03220     }
03221     else if(Divider == DIVIDER_Q_UPDATE)
03222     {
03223       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
03224     }
03225     else
03226     {
03227       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
03228     }
03229
03230     /* Enable  PLL2. */
03231     __HAL_RCC_PLL2_ENABLE();
03232
03233     /* Get Start Tick*/
03234     tickstart = HAL_GetTick();
03235
03236     /* Wait till PLL2 is ready */
03237     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
03238     {
03239       if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
03240       {
03241         return HAL_TIMEOUT;
03242       }
03243     }
03244
03245   }
03246
03247
03248   return status;
03249 }
03250
03251
03252 /**
03253   * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
03254   * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
03255   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
03256   * @param  Divider  divider parameter to be updated
03257   * @note   PLL3 is temporary disabled to apply new parameters
03258   *
03259   * @retval HAL status
03260   */
03261 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
03262 {
03263   uint32_t tickstart;
03264   HAL_StatusTypeDef status = HAL_OK;
03265   assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
03266   assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
03267   assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
03268   assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
03269   assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
03270   assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
03271   assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
03272   assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
03273
03274   /* Check that PLL3 OSC clock source is already set */
03275   if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
03276   {
03277     return HAL_ERROR;
03278   }
03279
03280
03281   else
03282   {
03283     /* Disable  PLL3. */
03284     __HAL_RCC_PLL3_DISABLE();
03285
03286     /* Get Start Tick*/
03287     tickstart = HAL_GetTick();
03288     /* Wait till PLL3 is ready */
03289     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
03290     {
03291       if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
03292       {
03293         return HAL_TIMEOUT;
03294       }
03295     }
03296
03297     /* Configure the PLL3  multiplication and division factors. */
03298     __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
03299                           pll3->PLL3N,
03300                           pll3->PLL3P,
03301                           pll3->PLL3Q,
03302                           pll3->PLL3R);
03303
03304     /* Select PLL3 input reference frequency range: VCI */
03305     __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
03306
03307     /* Select PLL3 output frequency range : VCO */
03308     __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
03309
03310     /* Disable PLL3FRACN . */
03311     __HAL_RCC_PLL3FRACN_DISABLE();
03312
03313     /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
03314     __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
03315
03316     /* Enable PLL3FRACN . */
03317     __HAL_RCC_PLL3FRACN_ENABLE();
03318
03319     /* Enable the PLL3 clock output */
03320     if(Divider == DIVIDER_P_UPDATE)
03321     {
03322       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
03323     }
03324     else if(Divider == DIVIDER_Q_UPDATE)
03325     {
03326       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
03327     }
03328     else
03329     {
03330       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
03331     }
03332
03333     /* Enable  PLL3. */
03334     __HAL_RCC_PLL3_ENABLE();
03335
03336     /* Get Start Tick*/
03337     tickstart = HAL_GetTick();
03338
03339     /* Wait till PLL3 is ready */
03340     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
03341     {
03342       if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
03343       {
03344         return HAL_TIMEOUT;
03345       }
03346     }
03347
03348   }
03349
03350
03351   return status;
03352 }
03353
03354 /**
03355   * @}
03356   */
03357
03358 #endif /* HAL_RCC_MODULE_ENABLED */
03359 /**
03360   * @}
03361   */
03362
03363 /**
03364   * @}
03365   */
03366
03367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rcc_ex.h Source File

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stm32h7xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RCC_EX_H
00022 #define STM32H7xx_HAL_RCC_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup RCCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  PLL2 Clock structure definition
00046   */
00047 typedef struct
00048 {
00049
00050   uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
00051                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00052
00053   uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
00054                              This parameter must be a number between Min_Data = 4 and Max_Data = 512
00055                              or between Min_Data = 8 and Max_Data = 420(*)
00056                              (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
00057
00058   uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
00059                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
00060                              odd division factors are not allowed                                      */
00061
00062   uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
00063                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00064
00065   uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
00066                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00067   uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
00068                           This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
00069   uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
00070                           This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
00071
00072   uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
00073                             PLL2 VCO It should be a value between 0 and 8191                           */
00074 }RCC_PLL2InitTypeDef;
00075
00076 /**
00077   * @brief  PLL3 Clock structure definition
00078   */
00079 typedef struct
00080 {
00081
00082   uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
00083                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00084
00085   uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
00086                              This parameter must be a number between Min_Data = 4 and Max_Data = 512
00087                              or between Min_Data = 8 and Max_Data = 420(*)
00088                              (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
00089
00090   uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
00091                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
00092                              odd division factors are not allowed                                      */
00093
00094   uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
00095                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00096
00097   uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
00098                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00099   uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
00100                           This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
00101   uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
00102                           This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
00103
00104   uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
00105                             PLL3 VCO It should be a value between 0 and 8191                           */
00106 }RCC_PLL3InitTypeDef;
00107
00108 /**
00109   * @brief  RCC PLL1 Clocks structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t PLL1_P_Frequency;
00114   uint32_t PLL1_Q_Frequency;
00115   uint32_t PLL1_R_Frequency;
00116 }PLL1_ClocksTypeDef;
00117
00118 /**
00119   * @brief  RCC PLL2 Clocks structure definition
00120   */
00121 typedef struct
00122 {
00123   uint32_t PLL2_P_Frequency;
00124   uint32_t PLL2_Q_Frequency;
00125   uint32_t PLL2_R_Frequency;
00126 }PLL2_ClocksTypeDef;
00127
00128 /**
00129   * @brief  RCC PLL3 Clocks structure definition
00130   */
00131 typedef struct
00132 {
00133   uint32_t PLL3_P_Frequency;
00134   uint32_t PLL3_Q_Frequency;
00135   uint32_t PLL3_R_Frequency;
00136 }PLL3_ClocksTypeDef;
00137
00138
00139 /**
00140   * @brief  RCC extended clocks structure definition
00141   */
00142 typedef struct
00143 {
00144   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00145                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00146
00147   RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
00148                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
00149
00150   RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
00151                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
00152
00153   uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
00154                                         This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
00155
00156 #if defined(QUADSPI)
00157   uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
00158                                         This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
00159 #endif /* QUADSPI */
00160
00161 #if defined(OCTOSPI1) || defined(OCTOSPI2)
00162   uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source
00163                                         This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */
00164 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
00165
00166
00167 #if defined(DSI)
00168   uint32_t DsiClockSelection;     /*!< Specifies DSI clock source
00169                                      This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */
00170 #endif /* DSI */
00171
00172   uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
00173                                         This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
00174
00175   uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
00176                                         This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
00177
00178   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
00179                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
00180
00181 #if defined(SAI3)
00182   uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source
00183                                          This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */
00184 #endif /* SAI3 */
00185
00186 #if defined(RCC_CDCCIP1R_SAI2ASEL)
00187   uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source
00188                                         This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */
00189 #endif /* RCC_CDCCIP1R_SAI2ASEL */
00190
00191 #if defined(RCC_CDCCIP1R_SAI2BSEL)
00192   uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source
00193                                          This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */
00194 #endif /* RCC_CDCCIP1R_SAI2BSEL */
00195
00196   uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source
00197                                           This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */
00198
00199   uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source
00200                                          This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */
00201
00202   uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
00203                                         This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
00204
00205   uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
00206                                         This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
00207
00208 #if defined(DFSDM2_BASE)
00209   uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source
00210                                         This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */
00211 #endif /* DFSDM2_BASE */
00212
00213 #if defined(FDCAN1) || defined(FDCAN2)
00214   uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
00215                                         This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
00216 #endif /*FDCAN1 || FDCAN2*/
00217
00218   uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
00219                                         This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
00220
00221   uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source
00222                                              This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */
00223
00224   uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
00225                                         This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
00226
00227    uint32_t RngClockSelection;      /*!< Specifies RNG clock source
00228                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
00229
00230    uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
00231                                         This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */
00232
00233   uint32_t UsbClockSelection;      /*!< Specifies USB clock source
00234                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
00235
00236   uint32_t CecClockSelection;     /*!< Specifies CEC clock source
00237                                         This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
00238
00239   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
00240                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
00241
00242   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
00243                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00244
00245   uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
00246                                         This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
00247
00248   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
00249                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
00250
00251   uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source
00252                                           This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */
00253
00254   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
00255                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
00256 #if defined(SAI4)
00257   uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
00258                                         This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
00259
00260   uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
00261                                         This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
00262 #endif /* SAI4 */
00263
00264   uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
00265                                         This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
00266
00267   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
00268                                         This parameter can be a value of @ref RCC_RTC_Clock_Source       */
00269
00270 #if defined(HRTIM1)
00271   uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
00272                                         This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
00273 #endif /* HRTIM1 */
00274
00275   uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
00276                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
00277 }RCC_PeriphCLKInitTypeDef;
00278
00279
00280 /**
00281   * @brief RCC_CRS Init structure definition
00282   */
00283 typedef struct
00284 {
00285   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00286                                      This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
00287
00288   uint32_t Source;                /*!< Specifies the SYNC signal source.
00289                                      This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
00290
00291   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00292                                      This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00293
00294   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00295                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00296                                      This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00297
00298   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00299                                      This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00300
00301   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00302                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00303
00304 }RCC_CRSInitTypeDef;
00305
00306 /**
00307   * @brief RCC_CRS Synchronization structure definition
00308   */
00309 typedef struct
00310 {
00311   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00312                                      This parameter must be a number between 0 and 0xFFFF */
00313
00314   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00315                                      This parameter must be a number between 0 and 0x3F */
00316
00317   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00318                                                                     value latched in the time of the last SYNC event.
00319                                     This parameter must be a number between 0 and 0xFFFF */
00320
00321   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00322                                                                     frequency error counter latched in the time of the last SYNC event.
00323                                                                     It shows whether the actual frequency is below or above the target.
00324                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00325
00326 }RCC_CRSSynchroInfoTypeDef;
00327
00328 /**
00329   * @}
00330   */
00331
00332
00333 /* Exported constants --------------------------------------------------------*/
00334 /** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
00335   * @{
00336   */
00337
00338 /** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
00339   * @{
00340   */
00341
00342 #if defined(UART9) && defined(USART10)
00343 #define RCC_PERIPHCLK_USART16910       (0x00000001U)
00344 #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
00345 #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
00346 #define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
00347 #define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910
00348 /*alias*/
00349 #define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
00350 #else
00351 #define RCC_PERIPHCLK_USART16          (0x00000001U)
00352 #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
00353 #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
00354 /* alias */
00355 #define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
00356 #endif /* UART9 && USART10*/
00357 #define RCC_PERIPHCLK_USART234578      (0x00000002U)
00358 #define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
00359 #define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
00360 #define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
00361 #define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
00362 #define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
00363 #define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
00364 #define RCC_PERIPHCLK_LPUART1          (0x00000004U)
00365 #define RCC_PERIPHCLK_I2C123           (0x00000008U)
00366 #define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
00367 #define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
00368 #define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
00369 #define RCC_PERIPHCLK_I2C4             (0x00000010U)
00370 #define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
00371 #define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
00372 #define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
00373 #define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
00374 #if defined(LPTIM4)
00375 #define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
00376 #endif /*LPTIM4*/
00377 #if defined(LPTIM5)
00378 #define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
00379 #endif /*LPTIM5*/
00380 #define RCC_PERIPHCLK_SAI1             (0x00000100U)
00381 #if defined(SAI3)
00382 #define RCC_PERIPHCLK_SAI23            (0x00000200U)
00383 #define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
00384 #define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
00385 #endif /* SAI3 */
00386 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
00387 #define RCC_PERIPHCLK_SAI2A            (0x00000200U)
00388 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
00389 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
00390 #define RCC_PERIPHCLK_SAI2B            (0x00000400U)
00391 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
00392 #if defined(SAI4)
00393 #define RCC_PERIPHCLK_SAI4A            (0x00000400U)
00394 #define RCC_PERIPHCLK_SAI4B            (0x00000800U)
00395 #endif /* SAI4 */
00396 #define RCC_PERIPHCLK_SPI123           (0x00001000U)
00397 #define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
00398 #define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
00399 #define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
00400 #define RCC_PERIPHCLK_SPI45            (0x00002000U)
00401 #define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
00402 #define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
00403 #define RCC_PERIPHCLK_SPI6             (0x00004000U)
00404 #define RCC_PERIPHCLK_FDCAN            (0x00008000U)
00405 #define RCC_PERIPHCLK_SDMMC            (0x00010000U)
00406 #define RCC_PERIPHCLK_RNG              (0x00020000U)
00407 #define RCC_PERIPHCLK_USB              (0x00040000U)
00408 #define RCC_PERIPHCLK_ADC              (0x00080000U)
00409 #define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
00410 #define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
00411 #if defined(DFSDM2_BASE)
00412 #define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
00413 #endif /* DFSDM2 */
00414 #define RCC_PERIPHCLK_RTC              (0x00400000U)
00415 #define RCC_PERIPHCLK_CEC              (0x00800000U)
00416 #define RCC_PERIPHCLK_FMC              (0x01000000U)
00417 #if defined(QUADSPI)
00418 #define RCC_PERIPHCLK_QSPI             (0x02000000U)
00419 #endif /* QUADSPI */
00420 #if defined(OCTOSPI1) || defined(OCTOSPI2)
00421 #define RCC_PERIPHCLK_OSPI             (0x02000000U)
00422 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
00423 #define RCC_PERIPHCLK_DSI              (0x04000000U)
00424 #define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
00425 #if defined(HRTIM1)
00426 #define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
00427 #endif /* HRTIM1 */
00428 #if defined(LTDC)
00429 #define RCC_PERIPHCLK_LTDC             (0x20000000U)
00430 #endif /* LTDC */
00431 #define RCC_PERIPHCLK_TIM              (0x40000000U)
00432 #define RCC_PERIPHCLK_CKPER            (0x80000000U)
00433
00434 /**
00435   * @}
00436   */
00437
00438
00439 /** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
00440   * @{
00441   */
00442 #define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
00443 #define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
00444 #define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
00445
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
00451   * @{
00452   */
00453 #define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
00454 #define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
00455 #define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
00462   * @{
00463   */
00464 #define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0
00465 #define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1
00466 #define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2
00467 #define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3
00468
00469 /**
00470   * @}
00471   */
00472
00473
00474 /** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
00475   * @{
00476   */
00477 #define RCC_PLL2VCOWIDE                 (0x00000000U)
00478 #define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
00479
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
00485   * @{
00486   */
00487 #define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0
00488 #define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1
00489 #define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2
00490 #define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3
00491
00492 /**
00493   * @}
00494   */
00495
00496
00497 /** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
00498   * @{
00499   */
00500 #define RCC_PLL3VCOWIDE                 (0x00000000U)
00501 #define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
00502
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source
00508   * @{
00509   */
00510 #if defined(RCC_D2CCIP2R_USART16SEL)
00511 #define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)
00512 /* alias */
00513 #define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2
00514 #define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0
00515 #define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1
00516 #define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
00517 #define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2
00518 #define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
00519
00520 #else
00521 #define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)
00522 /* alias */
00523 #define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2
00524 #define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0
00525 #define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1
00526 #define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
00527 #define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2
00528 #define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
00529
00530 /*  Aliases */
00531 #define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2
00532 #define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2
00533 #define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2
00534 #define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2
00535 #define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3
00536 #define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI
00537 #define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI
00538 #define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE
00539 #endif /* RCC_D2CCIP2R_USART16SEL */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
00545   * @{
00546   */
00547 #define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
00548 #define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
00549 #define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
00550 #define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
00551 #define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
00552 #define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
00558   * @{
00559   */
00560 #define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
00561 #define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
00562 #define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
00563 #define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
00564 #define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
00565 #define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
00566
00567 /**
00568   * @}
00569   */
00570
00571 #if defined(UART9)
00572 /** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source
00573   * @{
00574   */
00575 #define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
00576 #define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
00577 #define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
00578 #define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
00579 #define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
00580 #define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
00581 /**
00582   * @}
00583   */
00584 #endif /* UART9 */
00585
00586 #if defined(USART10)
00587 /** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source
00588   * @{
00589   */
00590 #define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
00591 #define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
00592 #define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
00593 #define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
00594 #define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
00595 #define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
00596 /**
00597   * @}
00598   */
00599 #endif /* USART10 */
00600
00601 /** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source
00602   * @{
00603   */
00604 #if defined(RCC_D2CCIP2R_USART28SEL)
00605 #define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)
00606 /* alias */
00607 #define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1
00608 #define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0
00609 #define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1
00610 #define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00611 #define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00612 #define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00613 #else
00614 #define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)
00615 /* alias */
00616 #define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1
00617 #define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1
00618 #define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0
00619 #define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1
00620 #define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
00621 #define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2
00622 #define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
00623 #endif /* RCC_D2CCIP2R_USART28SEL */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
00629   * @{
00630   */
00631 #define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00632 #define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00633 #define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00634 #define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00635 #define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00636 #define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00637
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
00643   * @{
00644   */
00645 #define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00646 #define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00647 #define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00648 #define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00649 #define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00650 #define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00651
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
00657   * @{
00658   */
00659 #define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00660 #define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00661 #define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00662 #define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00663 #define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00664 #define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00665
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
00671   * @{
00672   */
00673 #define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00674 #define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00675 #define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00676 #define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00677 #define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00678 #define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00679
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
00685   * @{
00686   */
00687 #define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00688 #define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00689 #define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00690 #define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00691 #define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00692 #define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00693
00694 /**
00695   * @}
00696   */
00697
00698 /** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
00699   * @{
00700   */
00701 #define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
00702 #define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
00703 #define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
00704 #define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
00705 #define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
00706 #define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
00707
00708 /**
00709   * @}
00710   */
00711
00712 /** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
00713   * @{
00714   */
00715 #if defined(RCC_D3CCIPR_LPUART1SEL)
00716 #define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)
00717 /* alias */
00718 #define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1
00719 #define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
00720 #define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
00721 #define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
00722 #define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
00723 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
00724 #else
00725 #define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)
00726 /* alias*/
00727 #define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4
00728 #define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4
00729 #define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0
00730 #define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1
00731 #define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
00732 #define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2
00733 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
00734 #endif /* RCC_D3CCIPR_LPUART1SEL */
00735 /**
00736   * @}
00737   */
00738
00739 /** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source
00740   * @{
00741   */
00742 #if defined (RCC_D2CCIP2R_I2C123SEL)
00743 #define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)
00744 #define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
00745 #define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
00746 #define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
00747 #else
00748 #define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)
00749 /* alias */
00750 #define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1
00751 #define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0
00752 #define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1
00753 #define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
00754 #endif /* RCC_D2CCIP2R_I2C123SEL */
00755 /**
00756   * @}
00757   */
00758
00759 /** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
00760   * @{
00761   */
00762 #define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
00763 #define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
00764 #define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
00765 #define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
00766
00767 /**
00768   * @}
00769   */
00770
00771 /** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
00772   * @{
00773   */
00774 #define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
00775 #define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
00776 #define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
00777 #define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
00778
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
00784   * @{
00785   */
00786 #define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
00787 #define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
00788 #define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
00789 #define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
00790
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
00796   * @{
00797   */
00798 #if defined(RCC_D3CCIPR_I2C4SEL)
00799 #define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)
00800 #define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
00801 #define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
00802 #define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
00803 #else
00804 #define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)
00805 /* alias */
00806 #define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4
00807 #define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0
00808 #define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1
00809 #define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
00810 #endif /* RCC_D3CCIPR_I2C4SEL */
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
00817   * @{
00818   */
00819 #if defined(RCC_D2CCIP2R_RNGSEL)
00820 #define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
00821 #define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
00822 #define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
00823 #define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
00824 #else
00825 #define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
00826 #define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0
00827 #define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1
00828 #define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL
00829 #endif /* RCC_D2CCIP2R_RNGSEL */
00830
00831 /**
00832   * @}
00833   */
00834 #if defined(HRTIM1)
00835
00836 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
00837   * @{
00838   */
00839 #define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)
00840 #define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
00841
00842 /**
00843   * @}
00844   */
00845 #endif /*HRTIM1*/
00846
00847 /** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
00848   * @{
00849   */
00850 #if defined(RCC_D2CCIP2R_USBSEL)
00851 #define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
00852 #define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
00853 #define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
00854 #else
00855 #define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0
00856 #define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1
00857 #define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL
00858 #endif /* RCC_D2CCIP2R_USBSEL */
00859
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00865   * @{
00866   */
00867 #if defined(RCC_D2CCIP1R_SAI1SEL)
00868 #define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
00869 #define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
00870 #define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
00871 #define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
00872 #define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
00873 #else
00874 #define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
00875 #define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0
00876 #define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1
00877 #define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
00878 #define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2
00879 #endif /* RCC_D2CCIP1R_SAI1SEL */
00880 /**
00881   * @}
00882   */
00883
00884 #if defined(SAI3)
00885 /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
00886   * @{
00887   */
00888 #define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)
00889 #define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
00890 #define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
00891 #define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
00892 #define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
00893 /**
00894   * @}
00895   */
00896
00897 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
00898   * @{
00899   */
00900 #define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
00901 #define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
00902 #define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
00903 #define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
00904 #define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
00905
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
00911   * @{
00912   */
00913 #define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
00914 #define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
00915 #define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
00916 #define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
00917 #define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
00918 /**
00919   * @}
00920   */
00921 #endif /* SAI3 */
00922
00923 #if defined(RCC_CDCCIP1R_SAI2ASEL)
00924 /** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
00925   * @{
00926   */
00927 #define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)
00928 #define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0
00929 #define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1
00930 #define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
00931 #define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
00932 #define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
00933  /**
00934   * @}
00935   */
00936 #endif /* RCC_CDCCIP1R_SAI2ASEL */
00937
00938 #if defined(RCC_CDCCIP1R_SAI2BSEL)
00939 /** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
00940   * @{
00941   */
00942 #define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)
00943 #define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0
00944 #define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1
00945 #define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
00946 #define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2
00947 #define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
00948 /**
00949   * @}
00950   */
00951 #endif /* RCC_CDCCIP1R_SAI2BSEL */
00952
00953
00954 /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
00955   * @{
00956   */
00957 #if defined(RCC_D2CCIP1R_SPI123SEL)
00958 #define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
00959 #define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
00960 #define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
00961 #define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
00962 #define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
00963 #else
00964 #define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
00965 #define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0
00966 #define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1
00967 #define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
00968 #define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2
00969 #endif /* RCC_D2CCIP1R_SPI123SEL */
00970 /**
00971   * @}
00972   */
00973
00974 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
00975   * @{
00976   */
00977 #define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
00978 #define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
00979 #define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
00980 #define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
00981 #define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
00982
00983 /**
00984   * @}
00985   */
00986
00987 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
00988   * @{
00989   */
00990 #define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
00991 #define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
00992 #define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
00993 #define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
00994 #define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
00995
00996 /**
00997   * @}
00998   */
00999
01000 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
01001   * @{
01002   */
01003 #define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
01004 #define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
01005 #define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
01006 #define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
01007 #define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
01008
01009 /**
01010   * @}
01011   */
01012
01013 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
01014   * @{
01015   */
01016 #if defined(RCC_D2CCIP1R_SPI45SEL)
01017 #define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
01018 #define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
01019 #define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
01020 #define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
01021 #define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
01022 #define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
01023 #define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
01024 #else
01025 #define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
01026 /* aliases */
01027 #define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
01028 #define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
01029 #define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
01030 #define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
01031 #define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
01032 #define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2
01033 #define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
01034 #endif /* RCC_D2CCIP1R_SPI45SEL */
01035 /**
01036   * @}
01037   */
01038
01039 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
01040   * @{
01041   */
01042 #define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
01043 #define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
01044 #define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
01045 #define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
01046 #define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
01047 #define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
01048
01049 /**
01050   * @}
01051   */
01052
01053 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
01054   * @{
01055   */
01056 #define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
01057 #define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
01058 #define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
01059 #define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
01060 #define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
01061 #define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
01062
01063 /**
01064   * @}
01065   */
01066
01067 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
01068   * @{
01069   */
01070 #if defined(RCC_D3CCIPR_SPI6SEL)
01071 #define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)
01072 #define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1
01073 #define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
01074 #define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
01075 #define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
01076 #define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
01077 #define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
01078 #else
01079 #define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)
01080 /* alias */
01081 #define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
01082 #define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4
01083 #define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0
01084 #define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1
01085 #define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
01086 #define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2
01087 #define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
01088 #define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
01089 #endif /* RCC_D3CCIPR_SPI6SEL */
01090
01091 /**
01092   * @}
01093   */
01094
01095
01096 #if defined(SAI4_Block_A)
01097 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
01098   * @{
01099   */
01100 #define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)
01101 #define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
01102 #define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
01103 #define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
01104 #define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
01105
01106 /**
01107   * @}
01108   */
01109 #endif /* SAI4_Block_A */
01110
01111
01112
01113 #if defined(SAI4_Block_B)
01114 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
01115   * @{
01116   */
01117 #define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)
01118 #define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
01119 #define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
01120 #define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
01121 #define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
01122
01123 /**
01124   * @}
01125   */
01126 #endif /* SAI4_Block_B */
01127
01128
01129 /** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
01130   * @{
01131   */
01132 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
01133 #define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)
01134 /* alias */
01135 #define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1
01136 #define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
01137 #define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
01138 #define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
01139 #define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2
01140 #define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
01141 #else
01142 #define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)
01143 /* alias */
01144 #define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1
01145 #define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1
01146 #define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0
01147 #define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1
01148 #define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
01149 #define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2
01150 #define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
01151 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
01152
01153 /**
01154   * @}
01155   */
01156
01157 /** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
01158   * @{
01159   */
01160 #if defined(RCC_D3CCIPR_LPTIM2SEL)
01161 #define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)
01162 /* alias */
01163 #define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1
01164 #define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
01165 #define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
01166 #define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
01167 #define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2
01168 #define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
01169 #else
01170 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)
01171 /*alias*/
01172 #define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4
01173 #define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4
01174 #define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0
01175 #define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1
01176 #define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
01177 #define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2
01178 #define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
01179 #endif /* RCC_D3CCIPR_LPTIM2SEL */
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source
01185   * @{
01186   */
01187 #if defined(RCC_D3CCIPR_LPTIM345SEL)
01188 #define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)
01189 /* alias*/
01190 #define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1
01191 #define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
01192 #define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
01193 #define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
01194 #define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
01195 #define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
01196 #else
01197 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)
01198 /* alias */
01199 #define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4
01200 #define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4
01201 #define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0
01202 #define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1
01203 #define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
01204 #define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2
01205 #define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
01206 #endif /* RCC_D3CCIPR_LPTIM345SEL */
01207 /**
01208   * @}
01209   */
01210
01211 /** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
01212   * @{
01213   */
01214 #define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
01215 #define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
01216 #define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
01217 #define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
01218 #define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
01219 #define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
01220
01221 /**
01222   * @}
01223   */
01224 #if defined(LPTIM4)
01225 /** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
01226   * @{
01227   */
01228 #define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
01229 #define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
01230 #define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
01231 #define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
01232 #define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
01233 #define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
01234 /**
01235   * @}
01236   */
01237 #endif /* LPTIM4 */
01238
01239 #if defined(LPTIM5)
01240 /** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
01241   * @{
01242   */
01243 #define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
01244 #define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
01245 #define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
01246 #define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
01247 #define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
01248 #define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
01249
01250 /**
01251   * @}
01252   */
01253 #endif /* LPTIM5 */
01254
01255 #if defined(QUADSPI)
01256 /** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
01257   * @{
01258   */
01259 #define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)
01260 #define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
01261 #define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
01262 #define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
01263
01264 /**
01265   * @}
01266   */
01267 #endif /* QUADSPI */
01268
01269
01270 #if defined(OCTOSPI1) || defined(OCTOSPI2)
01271 /** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source
01272   * @{
01273   */
01274 #define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)
01275 /*aliases*/
01276 #define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK
01277 #define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK
01278 #define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0
01279 #define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1
01280 #define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL
01281
01282 /**
01283   * @}
01284   */
01285 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
01286
01287 #if defined(DSI)
01288 /** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source
01289   * @{
01290   */
01291 #define RCC_DSICLKSOURCE_PHY       (0x00000000U)
01292 #define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL
01293
01294 /**
01295   * @}
01296   */
01297 #endif /* DSI */
01298
01299 /** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
01300   * @{
01301   */
01302 #if defined(RCC_D1CCIPR_FMCSEL)
01303 #define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)
01304 #define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK
01305 #define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
01306 #define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
01307 #define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
01308 #else
01309 #define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)
01310 #define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK
01311 /*alias*/
01312 #define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK
01313 #define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0
01314 #define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1
01315 #define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL
01316 #endif /* RCC_D1CCIPR_FMCSEL */
01317
01318 /**
01319   * @}
01320   */
01321
01322 #if defined(FDCAN1) || defined(FDCAN2)
01323 /** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
01324   * @{
01325   */
01326 #if defined(RCC_D2CCIP1R_FDCANSEL)
01327 #define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
01328 #define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
01329 #define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
01330 #else
01331 #define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
01332 #define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0
01333 #define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1
01334 #endif /* D3_SRAM_BASE */
01335 /**
01336   * @}
01337   */
01338 #endif /*FDCAN1 || FDCAN2*/
01339
01340
01341 /** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
01342   * @{
01343   */
01344 #if defined(RCC_D1CCIPR_SDMMCSEL)
01345 #define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
01346 #define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
01347 #else
01348 #define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
01349 #define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL
01350 #endif /* RCC_D1CCIPR_SDMMCSEL */
01351 /**
01352   * @}
01353   */
01354
01355
01356 /** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
01357   * @{
01358   */
01359 #if defined(RCC_D3CCIPR_ADCSEL_0)
01360 #define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
01361 #define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
01362 #define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
01363 #else
01364 #define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
01365 #define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0
01366 #define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1
01367 #endif /* RCC_D3CCIPR_ADCSEL_0  */
01368 /**
01369   * @}
01370   */
01371
01372 /** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
01373   * @{
01374   */
01375 #if defined(RCC_D2CCIP1R_SWPSEL)
01376 #define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)
01377 #define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
01378 #else
01379 #define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)
01380 /* alias */
01381 #define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1
01382 #define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL
01383 #endif /* RCC_D2CCIP1R_SWPSEL */
01384 /**
01385   * @}
01386   */
01387
01388 /** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
01389   * @{
01390   */
01391 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
01392 #define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)
01393 #define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
01394 #else
01395 #define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)
01396 /* alias */
01397 #define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1
01398 #define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL
01399 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
01400 /**
01401   * @}
01402   */
01403
01404 #if defined(DFSDM2_BASE)
01405 /** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source
01406   * @{
01407   */
01408 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)
01409 /* alias */
01410 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4
01411 #define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL
01412 /**
01413   * @}
01414   */
01415 #endif /* DFSDM2 */
01416
01417 /** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
01418   * @{
01419   */
01420 #if defined(RCC_D2CCIP1R_SPDIFSEL_0)
01421 #define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
01422 #define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
01423 #define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
01424 #define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
01425 #else
01426 #define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
01427 #define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0
01428 #define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1
01429 #define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL
01430 #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
01431 /**
01432   * @}
01433   */
01434
01435 /** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
01436   * @{
01437   */
01438 #if defined(RCC_D2CCIP2R_CECSEL_0)
01439 #define RCC_CECCLKSOURCE_LSE        (0x00000000U)
01440 #define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
01441 #define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
01442 #else
01443 #define RCC_CECCLKSOURCE_LSE        (0x00000000U)
01444 #define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0
01445 #define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1
01446 #endif /* RCC_D2CCIP2R_CECSEL_0 */
01447 /**
01448   * @}
01449   */
01450
01451
01452 /** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
01453   * @{
01454   */
01455 #if defined(RCC_D1CCIPR_CKPERSEL_0)
01456 #define RCC_CLKPSOURCE_HSI        (0x00000000U)
01457 #define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
01458 #define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
01459 #else
01460 #define RCC_CLKPSOURCE_HSI        (0x00000000U)
01461 #define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0
01462 #define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1
01463 #endif /* RCC_D1CCIPR_CKPERSEL_0 */
01464 /**
01465   * @}
01466   */
01467
01468 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
01469   * @{
01470   */
01471 #define RCC_TIMPRES_DESACTIVATED        (0x00000000U)
01472 #define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
01473
01474 /**
01475   * @}
01476   */
01477
01478 #if defined(DUAL_CORE)
01479
01480 /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
01481   * @{
01482   */
01483 #define RCC_BOOT_C1        RCC_GCR_BOOT_C1
01484 #define RCC_BOOT_C2        RCC_GCR_BOOT_C2
01485
01486 /**
01487   * @}
01488   */
01489 #endif /*DUAL_CORE*/
01490
01491 #if defined(DUAL_CORE)
01492 /** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
01493   * @{
01494   */
01495 #define RCC_WWDG1        RCC_GCR_WW1RSC
01496 #define RCC_WWDG2        RCC_GCR_WW2RSC
01497
01498 /**
01499   * @}
01500   */
01501
01502 #else
01503
01504 /** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
01505   * @{
01506   */
01507 #define RCC_WWDG1        RCC_GCR_WW1RSC
01508
01509 /**
01510   * @}
01511   */
01512
01513 #endif /*DUAL_CORE*/
01514
01515 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
01516   * @{
01517   */
01518 #define RCC_CRS_NONE                   (0x00000000U)
01519 #define RCC_CRS_TIMEOUT                (0x00000001U)
01520 #define RCC_CRS_SYNCOK                 (0x00000002U)
01521 #define RCC_CRS_SYNCWARN               (0x00000004U)
01522 #define RCC_CRS_SYNCERR                (0x00000008U)
01523 #define RCC_CRS_SYNCMISS               (0x00000010U)
01524 #define RCC_CRS_TRIMOVF                (0x00000020U)
01525 /**
01526   * @}
01527   */
01528
01529 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
01530   * @{
01531   */
01532 #define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */
01533 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */
01534 #define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */
01535 #define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
01541   * @{
01542   */
01543 #define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */
01544 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
01545 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
01546 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
01547 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
01548 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
01549 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
01550 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
01551 /**
01552   * @}
01553   */
01554
01555 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
01556   * @{
01557   */
01558 #define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
01559 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
01560 /**
01561   * @}
01562   */
01563
01564 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
01565   * @{
01566   */
01567 #define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
01568                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
01569 /**
01570   * @}
01571   */
01572
01573 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
01574   * @{
01575   */
01576 #define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
01577 /**
01578   * @}
01579   */
01580
01581 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
01582   * @{
01583   */
01584 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
01585                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
01586                                                                       corresponds to a higher output frequency */
01587 /**
01588   * @}
01589   */
01590
01591 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
01592   * @{
01593   */
01594 #define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
01595 #define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
01596 /**
01597   * @}
01598   */
01599
01600 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
01601   * @{
01602   */
01603 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
01604 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
01605 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
01606 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
01607 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
01608 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
01609 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
01610
01611 /**
01612   * @}
01613   */
01614
01615 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
01616   * @{
01617   */
01618 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
01619 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
01620 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
01621 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
01622 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
01623 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
01624 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
01625
01626 /**
01627   * @}
01628   */
01629
01630 /**
01631   * @}
01632   */
01633
01634 /* Exported functions --------------------------------------------------------*/
01635 /** @addtogroup RCCEx_Exported_Functions
01636   * @{
01637   */
01638 /** @addtogroup RCCEx_Exported_Functions_Group1
01639   * @{
01640   */
01641 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01642 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01643 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01644 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
01645 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
01646 uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
01647 void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
01648 void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
01649 void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
01650 /**
01651   * @}
01652   */
01653
01654 /** @addtogroup RCCEx_Exported_Functions_Group2
01655   * @{
01656   */
01657 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
01658 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
01659 void HAL_RCCEx_EnableLSECSS(void);
01660 void HAL_RCCEx_DisableLSECSS(void);
01661 #if defined(DUAL_CORE)
01662 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
01663 #endif /*DUAL_CORE*/
01664 #if defined(RCC_GCR_WW1RSC)
01665 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
01666 #endif /*RCC_GCR_WW1RSC*/
01667 /**
01668   * @}
01669   */
01670
01671
01672 /** @addtogroup RCCEx_Exported_Functions_Group3
01673   * @{
01674   */
01675 void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01676 void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01677 void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01678 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01679 void     HAL_RCCEx_CRS_IRQHandler(void);
01680 void     HAL_RCCEx_CRS_SyncOkCallback(void);
01681 void     HAL_RCCEx_CRS_SyncWarnCallback(void);
01682 void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01683 void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01684
01685 /**
01686   * @}
01687   */
01688 /**
01689   * @}
01690   */
01691
01692 /* Private macros ------------------------------------------------------------*/
01693 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
01694  * @{
01695  */
01696 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
01697   * @{
01698   */
01699
01700 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
01701                                          ((VALUE) == RCC_PLL2_DIVQ)  || \
01702                                          ((VALUE) == RCC_PLL2_DIVR))
01703
01704 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
01705                                           ((VALUE) == RCC_PLL3_DIVQ) || \
01706                                           ((VALUE) == RCC_PLL3_DIVR))
01707
01708 #if defined(RCC_D2CCIP2R_USART16SEL)
01709 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
01710                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
01711                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
01712                                          ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
01713                                          ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
01714                                          ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
01715 #else
01716 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
01717                                          ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
01718                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
01719                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
01720                                          ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
01721                                          ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
01722                                          ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
01723 /* alias*/
01724 #define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE
01725 #endif /* RCC_D2CCIP2R_USART16SEL */
01726
01727 #if defined(RCC_D2CCIP2R_USART28SEL)
01728 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
01729                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
01730                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
01731                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
01732                                              ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
01733                                              ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
01734 #else
01735 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
01736                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
01737                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
01738                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
01739                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
01740                                              ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
01741                                              ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
01742 #endif /* RCC_D2CCIP2R_USART28SEL */
01743
01744 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
01745                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
01746                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
01747                                         ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
01748                                         ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
01749                                         ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
01750
01751 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
01752                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
01753                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
01754                                         ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
01755                                         ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
01756                                         ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
01757
01758 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
01759                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
01760                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
01761                                         ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
01762                                         ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
01763                                         ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
01764
01765 #define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
01766                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
01767                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
01768                                         ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
01769                                         ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
01770                                         ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
01771
01772 #define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
01773                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
01774                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
01775                                         ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
01776                                         ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
01777                                         ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
01778
01779 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
01780                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
01781                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
01782                                         ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
01783                                         ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
01784                                         ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
01785
01786 #define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
01787                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
01788                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
01789                                         ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
01790                                         ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
01791                                         ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
01792
01793 #define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
01794                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
01795                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
01796                                         ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
01797                                         ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
01798                                         ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
01799
01800 #if defined(UART9)
01801 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
01802                                         ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
01803                                         ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
01804                                         ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
01805                                         ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
01806                                         ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
01807 #endif
01808
01809 #if defined(USART10)
01810 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
01811                                         ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
01812                                         ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
01813                                         ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
01814                                         ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
01815                                         ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
01816 #endif
01817
01818 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
01819                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
01820                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
01821                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
01822                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
01823                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
01824
01825 #define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
01826                                           ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
01827                                           ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
01828                                           ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
01829
01830 #define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
01831                                         ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
01832                                         ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
01833                                         ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
01834
01835 #define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
01836                                         ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
01837                                         ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
01838                                         ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
01839
01840 #define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
01841                                         ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
01842                                         ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
01843                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
01844
01845 #define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
01846                                         ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
01847                                         ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
01848                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
01849
01850 #define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
01851                                         ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
01852                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
01853                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
01854
01855 #if defined(HRTIM1)
01856 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
01857                                         ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
01858 #endif
01859
01860 #define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
01861                                         ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
01862                                         ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
01863
01864 #define IS_RCC_SAI1CLK(__SOURCE__)   \
01865                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
01866                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
01867                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
01868                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
01869                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
01870
01871 #if defined(SAI3)
01872 #define IS_RCC_SAI23CLK(__SOURCE__)   \
01873                (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \
01874                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
01875                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
01876                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
01877                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
01878
01879 #define IS_RCC_SAI2CLK(__SOURCE__)   \
01880                (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
01881                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
01882                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
01883                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
01884                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
01885
01886
01887 #define IS_RCC_SAI3CLK(__SOURCE__)   \
01888                (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
01889                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
01890                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
01891                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
01892                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
01893 #endif
01894
01895 #if defined(RCC_CDCCIP1R_SAI2ASEL)
01896 #define IS_RCC_SAI2ACLK(__SOURCE__)   \
01897                (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
01898                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
01899                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
01900                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
01901                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
01902                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
01903 #endif
01904
01905 #if defined(RCC_CDCCIP1R_SAI2BSEL)
01906 #define IS_RCC_SAI2BCLK(__SOURCE__)   \
01907                (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
01908                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
01909                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
01910                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
01911                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
01912                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
01913 #endif
01914
01915 #define IS_RCC_SPI123CLK(__SOURCE__)   \
01916                (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
01917                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
01918                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
01919                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
01920                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
01921
01922 #define IS_RCC_SPI1CLK(__SOURCE__)   \
01923                (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
01924                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
01925                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
01926                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
01927                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
01928
01929 #define IS_RCC_SPI2CLK(__SOURCE__)   \
01930                (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
01931                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
01932                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
01933                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
01934                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
01935
01936 #define IS_RCC_SPI3CLK(__SOURCE__)   \
01937                (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
01938                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
01939                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
01940                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
01941                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
01942
01943 #define IS_RCC_SPI45CLK(__SOURCE__)   \
01944                (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
01945                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
01946                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
01947                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
01948                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
01949                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
01950
01951 #define IS_RCC_SPI4CLK(__SOURCE__)   \
01952                (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
01953                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
01954                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
01955                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
01956                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
01957                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
01958
01959 #define IS_RCC_SPI5CLK(__SOURCE__)   \
01960                (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
01961                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
01962                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
01963                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
01964                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
01965                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
01966
01967 #if defined(RCC_D3CCIPR_SPI6SEL)
01968 #define IS_RCC_SPI6CLK(__SOURCE__)   \
01969                (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
01970                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
01971                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
01972                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
01973                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
01974                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
01975 #else
01976 #define IS_RCC_SPI6CLK(__SOURCE__)   \
01977                (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
01978                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
01979                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
01980                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
01981                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
01982                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
01983                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
01984 #endif /* RCC_D3CCIPR_SPI6SEL */
01985
01986 #if defined(SAI4)
01987 #define IS_RCC_SAI4ACLK(__SOURCE__)   \
01988                (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
01989                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
01990                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
01991                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
01992                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
01993
01994 #define IS_RCC_SAI4BCLK(__SOURCE__)   \
01995                (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
01996                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
01997                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
01998                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
01999                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
02000 #endif /*SAI4*/
02001
02002 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
02003 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
02004 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02005 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02006 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02007
02008 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
02009 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
02010 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02011 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02012 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
02013
02014 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \
02015                                     ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
02016                                     ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
02017                                     ((VALUE) == RCC_PLL2VCIRANGE_3))
02018
02019 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \
02020                                     ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
02021                                     ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
02022                                     ((VALUE) == RCC_PLL3VCIRANGE_3))
02023
02024 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \
02025                                     ((VALUE) == RCC_PLL2VCOMEDIUM))
02026
02027 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \
02028                                     ((VALUE) == RCC_PLL3VCOMEDIUM))
02029
02030 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
02031
02032 #define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
02033                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
02034                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
02035                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
02036                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
02037                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
02038
02039 #define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
02040                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
02041                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
02042                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
02043                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
02044                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
02045
02046 #define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
02047                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
02048                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
02049                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
02050                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
02051                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
02052
02053 #define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
02054                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
02055                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
02056                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
02057                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
02058                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
02059
02060 #if defined(LPTIM4)
02061 #define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
02062                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
02063                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
02064                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
02065                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
02066                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
02067 #endif /* LPTIM4*/
02068
02069 #if defined(LPTIM5)
02070 #define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
02071                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
02072                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
02073                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
02074                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
02075                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
02076 #endif /*LPTIM5*/
02077
02078 #if defined(QUADSPI)
02079 #define IS_RCC_QSPICLK(__SOURCE__)   \
02080                (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
02081                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
02082                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
02083                 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
02084 #endif /*QUADSPI*/
02085
02086 #if defined(OCTOSPI1) || defined(OCTOSPI1)
02087 #define IS_RCC_OSPICLK(__SOURCE__)   \
02088                (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
02089                 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
02090                 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
02091                 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
02092 #endif /*OCTOSPI1 || OCTOSPI1*/
02093
02094 #if defined(DSI)
02095 #define IS_RCC_DSICLK(__SOURCE__)   \
02096                (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
02097                 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
02098 #endif /*DSI*/
02099
02100 #define IS_RCC_FMCCLK(__SOURCE__)   \
02101                (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
02102                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
02103                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
02104                 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
02105
02106 #if defined(FDCAN1) || defined(FDCAN2)
02107 #define IS_RCC_FDCANCLK(__SOURCE__)   \
02108                (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
02109                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
02110                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
02111 #endif /*FDCAN1 || FDCAN2*/
02112
02113 #define IS_RCC_SDMMC(__SOURCE__)   \
02114                 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
02115                 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
02116
02117 #define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
02118                                         ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
02119                                         ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
02120
02121 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
02122                                         ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
02123
02124 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
02125                                          ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
02126
02127 #if defined(DFSDM2_BASE)
02128 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
02129                                         ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
02130 #endif /*DFSDM2*/
02131
02132 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
02133                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
02134                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
02135                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
02136
02137 #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
02138                                       ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
02139                                       ((SOURCE) == RCC_CECCLKSOURCE_CSI))
02140
02141 #define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
02142                                       ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
02143                                       ((SOURCE) == RCC_CLKPSOURCE_HSE))
02144 #define IS_RCC_TIMPRES(VALUE)  \
02145                (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
02146                 ((VALUE) == RCC_TIMPRES_ACTIVATED))
02147
02148 #if defined(DUAL_CORE)
02149 #define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \
02150                                   ((CORE) == RCC_BOOT_C2))
02151 #endif /*DUAL_CORE*/
02152
02153 #if defined(DUAL_CORE)
02154 #define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \
02155                                   ((WWDG) == RCC_WWDG2))
02156 #else
02157 #define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
02158
02159 #endif /*DUAL_CORE*/
02160
02161 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
02162                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
02163                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
02164                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
02165
02166 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
02167                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
02168                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
02169                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
02170
02171 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
02172                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
02173
02174 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
02175
02176 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
02177
02178 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
02179
02180 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
02181                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
02182 /**
02183   * @}
02184   */
02185
02186 /**
02187   * @}
02188   */
02189
02190 /* Exported macro ------------------------------------------------------------*/
02191 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
02192   * @{
02193   */
02194
02195 /** @brief  Macros to enable or disable PLL2.
02196   * @note   After enabling PLL2, the application software should wait on
02197   *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
02198   *         be used as kernel clock source.
02199   * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
02200   */
02201 #define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
02202 #define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
02203
02204 /**
02205   * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
02206   * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,
02207   *         This is mainly used to save Power.
02208   * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
02209   *          This parameter can be one of the following values:
02210   *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
02211   *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
02212   *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
02213   *
02214   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02215   *
02216   * @retval None
02217   */
02218 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
02219
02220 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
02221
02222 /**
02223   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
02224   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
02225   * @retval None
02226   */
02227 #define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
02228
02229 #define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
02230
02231 /**
02232   * @brief  Macro to configures the PLL2  multiplication and division factors.
02233   * @note   This function must be used only when PLL2 is disabled.
02234   *
02235   * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock
02236   *          This parameter must be a number between 1 and 63.
02237   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02238   *         frequency ranges from 1 to 16 MHz.
02239   *
02240   * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
02241   *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
02242   * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
02243   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
02244   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
02245   *
02246   * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks
02247   *          This parameter must be a number between 1 and 128.
02248   *
02249   * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks
02250   *          This parameter must be a number between 1 and 128.
02251   *
02252   * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks
02253   *          This parameter must be a number between 1 and 128.
02254   *
02255   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
02256   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
02257   *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
02258   * @retval None
02259   *
02260   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02261   */
02262
02263 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
02264                   do{ \
02265                        MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
02266                        WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
02267                        ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
02268                     } while(0)
02269
02270 /**
02271   * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
02272   *
02273   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
02274   *
02275   * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
02276   *                           It should be a value between 0 and 8191
02277   * @note   Warning: the software has to set correctly these bits to insure that the VCO
02278   *                  output frequency is between its valid frequency range, which is:
02279   *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
02280   *                  150 to 420 MHz if PLL2VCOSEL = 1.
02281   *
02282   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02283   *
02284   * @retval None
02285   */
02286 #define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
02287                  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
02288
02289 /** @brief  Macro to select  the PLL2  reference frequency range.
02290   * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
02291   *         This parameter can be one of the following values:
02292   *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
02293   *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
02294   *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
02295   *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
02296   * @retval None
02297   */
02298 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
02299                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
02300
02301
02302 /** @brief  Macro to select  the PLL2  reference frequency range.
02303   * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
02304   *         This parameter can be one of the following values:
02305   *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
02306   *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
02307   *
02308   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02309   *
02310   * @retval None
02311   */
02312 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
02313                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
02314
02315 /** @brief  Macros to enable or disable the main PLL3.
02316   * @note   After enabling  PLL3, the application software should wait on
02317   *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
02318   *         be used as kernel clock source.
02319   * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
02320   */
02321 #define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
02322 #define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
02323
02324 /**
02325   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
02326   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
02327   * @retval None
02328   */
02329 #define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
02330
02331 #define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
02332
02333 /**
02334   * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
02335   * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,
02336   *         This is mainly used to save Power.
02337   * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
02338   *          This parameter can be one of the following values:
02339   *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
02340   *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)
02341   *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
02342   *
02343   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02344   *
02345   * @retval None
02346   */
02347 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
02348
02349 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
02350
02351 /**
02352   * @brief  Macro to configures the PLL3  multiplication and division factors.
02353   * @note   This function must be used only when PLL3 is disabled.
02354   *
02355   * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock
02356   *          This parameter must be a number between 1 and 63.
02357   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02358   *         frequency ranges from 1 to 16 MHz.
02359   *
02360   * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
02361   *          This parameter must be a number between 4 and 512.
02362   * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
02363   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
02364   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
02365   *
02366   * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks
02367   *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
02368   *
02369   * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks
02370   *          This parameter must be a number between 1 and 128
02371   *
02372   * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks
02373   *          This parameter must be a number between 1 and 128
02374   *
02375   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
02376   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
02377   *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
02378   * @retval None
02379   *
02380   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02381   */
02382
02383 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
02384                   do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
02385                          WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
02386                                    ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
02387                        } while(0)
02388
02389
02390
02391 /**
02392   * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
02393   *
02394   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
02395   *
02396   * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
02397   *                            It should be a value between 0 and 8191
02398   * @note   Warning: the software has to set correctly these bits to insure that the VCO
02399   *                  output frequency is between its valid frequency range, which is:
02400   *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
02401   *                  150 to 420 MHz if PLL3VCOSEL = 1.
02402   *
02403   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02404   *
02405   * @retval None
02406   */
02407  #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
02408
02409 /** @brief  Macro to select  the PLL3  reference frequency range.
02410   * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
02411   *         This parameter can be one of the following values:
02412   *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
02413   *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
02414   *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
02415   *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
02416   * @retval None
02417   */
02418 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
02419                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
02420
02421
02422 /** @brief  Macro to select  the PLL3  reference frequency range.
02423   * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
02424   *         This parameter can be one of the following values:
02425   *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)
02426   *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
02427   *
02428   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
02429   *
02430   * @retval None
02431   */
02432 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
02433                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
02434 /**
02435   * @brief  Macro to Configure the SAI1 clock source.
02436   * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
02437   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02438   *          This parameter can be one of the following values:
02439   *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
02440   *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
02441   *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
02442   *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC
02443   *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
02444   * @retval None
02445   */
02446 #if defined(RCC_D2CCIP1R_SAI1SEL)
02447 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
02448                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
02449 #else
02450 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
02451                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
02452 #endif /* RCC_D2CCIP1R_SAI1SEL */
02453
02454 /** @brief  Macro to get the SAI1 clock source.
02455   * @retval The clock source can be one of the following values:
02456   *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
02457   *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
02458   *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
02459   *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP
02460   *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
02461   */
02462 #if defined(RCC_D2CCIP1R_SAI1SEL)
02463 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
02464 #else
02465 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
02466 #endif /* RCC_D2CCIP1R_SAI1SEL */
02467
02468 /**
02469   * @brief  Macro to Configure the SPDIFRX clock source.
02470   * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
02471   *         from system PLL, PLL2, PLL3,  or internal OSC clock
02472   *          This parameter can be one of the following values:
02473   *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
02474   *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
02475   *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
02476   *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
02477   * @retval None
02478   */
02479 #if defined(RCC_D2CCIP1R_SPDIFSEL)
02480 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
02481                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
02482 #else
02483 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
02484                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
02485 #endif /* RCC_D2CCIP1R_SPDIFSEL */
02486
02487 /**
02488   * @brief  Macro to get the SPDIFRX clock source.
02489   * @retval None
02490   */
02491 #if defined(RCC_D2CCIP1R_SPDIFSEL)
02492 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
02493 #else
02494 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
02495 #endif /* RCC_D2CCIP1R_SPDIFSEL */
02496
02497 #if defined(SAI3)
02498 /**
02499   * @brief  Macro to Configure the SAI2/3 clock source.
02500   * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
02501   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02502   *          This parameter can be one of the following values:
02503   *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
02504   *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
02505   *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
02506   *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
02507   *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
02508   * @retval None
02509   */
02510 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
02511                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
02512
02513 /** @brief  Macro to get the SAI2/3 clock source.
02514   * @retval The clock source can be one of the following values:
02515   *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
02516   *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
02517   *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
02518   *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
02519   *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
02520   */
02521 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
02522
02523 /**
02524   * @brief  Macro to Configure the SAI2 clock source.
02525   * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
02526   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02527   *          This parameter can be one of the following values:
02528   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
02529   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
02530   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
02531   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
02532   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
02533   * @retval None
02534   */
02535 #define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG
02536
02537 /** @brief  Macro to get the SAI2 clock source.
02538   * @retval The clock source can be one of the following values:
02539   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
02540   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
02541   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
02542   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
02543   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
02544   */
02545 #define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
02546
02547 /**
02548   * @brief  Macro to Configure the SAI3 clock source.
02549   * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
02550   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02551   *          This parameter can be one of the following values:
02552   *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
02553   *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
02554   *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
02555   *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
02556   *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
02557   * @retval None
02558   */
02559 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
02560
02561 /** @brief  Macro to get the SAI3 clock source.
02562   * @retval The clock source can be one of the following values:
02563   *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
02564   *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
02565   *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
02566   *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
02567   *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
02568   */
02569 #define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
02570 #endif /* SAI3 */
02571
02572 #if defined(RCC_CDCCIP1R_SAI2ASEL)
02573 /**
02574   * @brief  Macro to Configure the SAI2A clock source.
02575   * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived
02576   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02577   *          This parameter can be one of the following values:
02578   *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
02579   *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
02580   *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
02581   *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP
02582   *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
02583   *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
02584   * @retval None
02585   */
02586 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
02587                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
02588
02589 /** @brief  Macro to get the SAI2A clock source.
02590   * @retval The clock source can be one of the following values:
02591   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
02592   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
02593   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
02594   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP
02595   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
02596   *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
02597   */
02598 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
02599 #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
02600
02601 #if defined(RCC_CDCCIP1R_SAI2BSEL)
02602 /**
02603   * @brief  Macro to Configure the SAI2B clock source.
02604   * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived
02605   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02606   *          This parameter can be one of the following values:
02607   *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
02608   *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
02609   *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
02610   *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
02611   *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
02612   *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
02613   * @retval None
02614   */
02615 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
02616                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
02617
02618 /** @brief  Macro to get the SAI2B clock source.
02619   * @retval The clock source can be one of the following values:
02620   *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
02621   *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
02622   *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
02623   *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
02624   *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
02625   *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
02626   */
02627 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
02628 #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
02629
02630
02631 #if defined(SAI4_Block_A)
02632 /**
02633   * @brief  Macro to Configure the SAI4A clock source.
02634   * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
02635   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02636   *          This parameter can be one of the following values:
02637   *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
02638   *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
02639   *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
02640   *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP
02641   *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
02642   * @retval None
02643   */
02644 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
02645                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
02646
02647 /** @brief  Macro to get the SAI4A clock source.
02648   * @retval The clock source can be one of the following values:
02649   *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
02650   *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
02651   *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
02652   *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP
02653   *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
02654   */
02655 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
02656 #endif /* SAI4_Block_A */
02657
02658 #if defined(SAI4_Block_B)
02659 /**
02660   * @brief  Macro to Configure the SAI4B clock source.
02661   * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
02662   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02663   *          This parameter can be one of the following values:
02664   *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
02665   *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
02666   *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
02667   *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
02668   *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
02669   * @retval None
02670   */
02671 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
02672                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
02673
02674 /** @brief  Macro to get the SAI4B clock source.
02675   * @retval The clock source can be one of the following values:
02676   *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
02677   *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
02678   *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
02679   *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
02680   *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
02681   */
02682 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
02683 #endif /* SAI4_Block_B */
02684
02685 /** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
02686   *
02687   * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
02688   *          This parameter can be one of the following values:
02689   *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
02690   *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
02691   *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
02692   *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
02693   */
02694 #if defined(RCC_D2CCIP2R_I2C123SEL)
02695 #define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
02696                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
02697 #else
02698 #define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
02699                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
02700 #endif /* RCC_D2CCIP2R_I2C123SEL */
02701
02702 /** @brief  macro to get the I2C1/2/3 clock source.
02703   * @retval The clock source can be one of the following values:
02704   *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
02705   *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
02706   *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
02707   *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
02708   */
02709 #if defined(RCC_D2CCIP2R_I2C123SEL)
02710 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
02711 #else
02712 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
02713 #endif /* RCC_D2CCIP2R_I2C123SEL */
02714
02715 /** @brief macro to configure the I2C1 clock (I2C1CLK).
02716   *
02717   * @param  __I2C1CLKSource__ specifies the I2C1 clock source.
02718   *          This parameter can be one of the following values:
02719   *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
02720   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
02721   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
02722   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
02723   */
02724 #define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG
02725
02726 /** @brief  macro to get the I2C1 clock source.
02727   * @retval The clock source can be one of the following values:
02728   *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
02729   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
02730   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
02731   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
02732   */
02733 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
02734
02735 /** @brief macro to configure the I2C2 clock (I2C2CLK).
02736   *
02737   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
02738   *          This parameter can be one of the following values:
02739   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
02740   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
02741   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
02742   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
02743   */
02744 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
02745
02746 /** @brief  macro to get the I2C2 clock source.
02747   * @retval The clock source can be one of the following values:
02748   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
02749   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
02750   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
02751   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
02752   */
02753 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
02754
02755 /** @brief macro to configure the I2C3 clock (I2C3CLK).
02756   *
02757   * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
02758   *          This parameter can be one of the following values:
02759   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
02760   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
02761   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
02762   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
02763   */
02764 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
02765
02766 /** @brief  macro to get the I2C3 clock source.
02767   * @retval The clock source can be one of the following values:
02768   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
02769   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
02770   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
02771   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
02772   */
02773 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
02774
02775 /** @brief macro to configure the I2C4 clock (I2C4CLK).
02776   *
02777   * @param  __I2C4CLKSource__ specifies the I2C4 clock source.
02778   *          This parameter can be one of the following values:
02779   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
02780   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
02781   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
02782   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
02783   */
02784 #if defined(RCC_D3CCIPR_I2C4SEL)
02785 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
02786                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
02787 #else
02788 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
02789                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
02790 #endif /* RCC_D3CCIPR_I2C4SEL */
02791
02792 /** @brief  macro to get the I2C4 clock source.
02793   * @retval The clock source can be one of the following values:
02794   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
02795   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
02796   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
02797   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
02798   */
02799 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
02800
02801 /** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
02802   *
02803   * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
02804   *          This parameter can be one of the following values:
02805   *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
02806   *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
02807   *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
02808   *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
02809   *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
02810   *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
02811   *
02812   * (*) : Available on some STM32H7 lines only.
02813   */
02814 #if defined(RCC_D2CCIP2R_USART16SEL)
02815 #define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
02816                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
02817 #else
02818 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
02819                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
02820 /* alias */
02821 #define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG
02822 #endif /* RCC_D2CCIP2R_USART16SEL */
02823
02824 /** @brief  macro to get the USART1/6/9* /10* clock source.
02825   * @retval The clock source can be one of the following values:
02826   *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
02827   *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
02828   *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
02829   *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
02830   *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
02831   *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
02832   *
02833   * (*) : Available on some STM32H7 lines only.
02834   */
02835 #if defined(RCC_D2CCIP2R_USART16SEL)
02836 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
02837 #else
02838 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
02839 /* alias*/
02840 #define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE
02841 #endif /* RCC_D2CCIP2R_USART16SEL */
02842
02843 /** @brief macro to configure the USART234578 clock (USART234578CLK).
02844   *
02845   * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
02846   *          This parameter can be one of the following values:
02847   *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
02848   *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
02849   *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
02850   *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
02851   *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
02852   *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
02853   */
02854 #if defined(RCC_D2CCIP2R_USART28SEL)
02855 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
02856                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
02857 #else
02858 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
02859                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
02860 #endif /* RCC_D2CCIP2R_USART28SEL */
02861
02862 /** @brief  macro to get the USART2/3/4/5/7/8 clock source.
02863   * @retval The clock source can be one of the following values:
02864   *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
02865   *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
02866   *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
02867   *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
02868   *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
02869   *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
02870   */
02871 #if defined(RCC_D2CCIP2R_USART28SEL)
02872 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
02873 #else
02874 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
02875 #endif /* RCC_D2CCIP2R_USART28SEL */
02876
02877 /** @brief macro to configure the USART1 clock (USART1CLK).
02878   *
02879   * @param  __USART1CLKSource__ specifies the USART1 clock source.
02880   *          This parameter can be one of the following values:
02881   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
02882   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
02883   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
02884   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
02885   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
02886   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
02887   */
02888 #define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG
02889
02890 /** @brief  macro to get the USART1 clock source.
02891   * @retval The clock source can be one of the following values:
02892   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
02893   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
02894   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
02895   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
02896   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
02897   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
02898   */
02899 #define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE
02900
02901 /** @brief macro to configure the USART2 clock (USART2CLK).
02902   *
02903   * @param  __USART2CLKSource__ specifies the USART2 clock source.
02904   *          This parameter can be one of the following values:
02905   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
02906   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
02907   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
02908   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
02909   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
02910   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
02911   */
02912 #define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG
02913
02914 /** @brief  macro to get the USART2 clock source.
02915   * @retval The clock source can be one of the following values:
02916   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
02917   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
02918   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
02919   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
02920   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
02921   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
02922   */
02923 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
02924
02925 /** @brief macro to configure the USART3 clock (USART3CLK).
02926   *
02927   * @param  __USART3CLKSource__ specifies the USART3 clock source.
02928   *          This parameter can be one of the following values:
02929   *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
02930   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
02931   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
02932   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
02933   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
02934   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
02935   */
02936 #define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG
02937
02938 /** @brief  macro to get the USART3 clock source.
02939   * @retval The clock source can be one of the following values:
02940   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
02941   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
02942   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
02943   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
02944   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
02945   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
02946   */
02947 #define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
02948
02949 /** @brief macro to configure the UART4 clock (UART4CLK).
02950   *
02951   * @param  __UART4CLKSource__ specifies the UART4 clock source.
02952   *          This parameter can be one of the following values:
02953   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
02954   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
02955   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
02956   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
02957   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
02958   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
02959   */
02960 #define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG
02961
02962 /** @brief  macro to get the UART4 clock source.
02963   * @retval The clock source can be one of the following values:
02964   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
02965   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
02966   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
02967   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
02968   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
02969   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
02970   */
02971 #define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
02972
02973 /** @brief macro to configure the UART5 clock (UART5CLK).
02974   *
02975   * @param  __UART5CLKSource__ specifies the UART5 clock source.
02976   *          This parameter can be one of the following values:
02977   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
02978   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
02979   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
02980   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
02981   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
02982   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
02983   */
02984 #define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG
02985
02986 /** @brief  macro to get the UART5 clock source.
02987   * @retval The clock source can be one of the following values:
02988   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
02989   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
02990   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
02991   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
02992   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
02993   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
02994   */
02995 #define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
02996
02997 /** @brief macro to configure the USART6 clock (USART6CLK).
02998   *
02999   * @param  __USART6CLKSource__ specifies the USART6 clock source.
03000   *          This parameter can be one of the following values:
03001   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
03002   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
03003   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
03004   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
03005   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
03006   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
03007   */
03008 #define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG
03009
03010 /** @brief  macro to get the USART6 clock source.
03011   * @retval The clock source can be one of the following values:
03012   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
03013   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
03014   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
03015   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
03016   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
03017   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
03018   */
03019 #define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE
03020
03021 /** @brief macro to configure the UART5 clock (UART7CLK).
03022   *
03023   * @param  __UART7CLKSource__ specifies the UART7 clock source.
03024   *          This parameter can be one of the following values:
03025   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
03026   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
03027   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
03028   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
03029   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
03030   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
03031   */
03032 #define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG
03033
03034 /** @brief  macro to get the UART7 clock source.
03035   * @retval The clock source can be one of the following values:
03036   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
03037   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
03038   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
03039   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
03040   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
03041   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
03042   */
03043 #define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
03044
03045 /** @brief macro to configure the UART8 clock (UART8CLK).
03046   *
03047   * @param  __UART8CLKSource__ specifies the UART8 clock source.
03048   *          This parameter can be one of the following values:
03049   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
03050   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
03051   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
03052   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
03053   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
03054   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
03055   */
03056 #define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG
03057
03058 /** @brief  macro to get the UART8 clock source.
03059   * @retval The clock source can be one of the following values:
03060   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
03061   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
03062   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
03063   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
03064   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
03065   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
03066   */
03067 #define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
03068
03069 #if defined(UART9)
03070 /** @brief macro to configure the UART9 clock (UART9CLK).
03071   *
03072   * @param  __UART8CLKSource__ specifies the UART8 clock source.
03073   *          This parameter can be one of the following values:
03074   *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
03075   *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
03076   *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
03077   *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
03078   *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
03079   *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
03080   */
03081 #define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG
03082
03083 /** @brief  macro to get the UART9 clock source.
03084   * @retval The clock source can be one of the following values:
03085   *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
03086   *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
03087   *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
03088   *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
03089   *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
03090   *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
03091   */
03092 #define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE
03093 #endif /* UART9 */
03094
03095 #if defined(USART10)
03096 /** @brief macro to configure the USART10 clock (USART10CLK).
03097   *
03098   * @param  __UART8CLKSource__ specifies the UART8 clock source.
03099   *          This parameter can be one of the following values:
03100   *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
03101   *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
03102   *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
03103   *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
03104   *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
03105   *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
03106   */
03107 #define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG
03108
03109 /** @brief  macro to get the USART10 clock source.
03110   * @retval The clock source can be one of the following values:
03111   *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
03112   *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
03113   *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
03114   *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
03115   *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
03116   *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
03117   */
03118 #define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE
03119 #endif /* USART10 */
03120
03121 /** @brief macro to configure the LPUART1 clock (LPUART1CLK).
03122   *
03123   * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.
03124   *          This parameter can be one of the following values:
03125   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
03126   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
03127   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
03128   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
03129   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
03130   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
03131   */
03132 #if defined (RCC_D3CCIPR_LPUART1SEL)
03133 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
03134                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
03135 #else
03136 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
03137                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
03138 #endif /* RCC_D3CCIPR_LPUART1SEL */
03139
03140 /** @brief  macro to get the LPUART1 clock source.
03141   * @retval The clock source can be one of the following values:
03142   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
03143   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
03144   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
03145   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
03146   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
03147   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
03148   */
03149 #if defined (RCC_D3CCIPR_LPUART1SEL)
03150 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
03151 #else
03152 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
03153 #endif /* RCC_D3CCIPR_LPUART1SEL */
03154
03155 /** @brief  macro to configure the LPTIM1 clock source.
03156   *
03157   * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
03158   *          This parameter can be one of the following values:
03159   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
03160   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
03161   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
03162   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
03163   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
03164   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
03165   */
03166 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
03167 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
03168                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
03169 #else
03170 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
03171                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
03172 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
03173
03174 /** @brief  macro to get the LPTIM1 clock source.
03175   * @retval The clock source can be one of the following values:
03176   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
03177   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
03178   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
03179   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
03180   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
03181   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
03182   */
03183 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
03184 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
03185 #else
03186 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
03187 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
03188
03189 /** @brief  macro to configure the LPTIM2 clock source.
03190   *
03191   * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
03192   *          This parameter can be one of the following values:
03193   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
03194   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
03195   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
03196   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
03197   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
03198   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
03199   */
03200 #if defined(RCC_D3CCIPR_LPTIM2SEL)
03201 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
03202                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
03203 #else
03204 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
03205                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
03206 #endif /* RCC_D3CCIPR_LPTIM2SEL */
03207
03208 /** @brief  macro to get the LPTIM2 clock source.
03209   * @retval The clock source can be one of the following values:
03210   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
03211   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
03212   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
03213   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
03214   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
03215   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
03216   */
03217 #if defined(RCC_D3CCIPR_LPTIM2SEL)
03218 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
03219 #else
03220 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
03221 #endif /* RCC_D3CCIPR_LPTIM2SEL */
03222
03223 /** @brief  macro to configure the LPTIM3/4/5 clock source.
03224   *
03225   * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
03226   *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
03227   *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
03228   *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
03229   *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
03230   *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
03231   *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
03232   */
03233 #if defined(RCC_D3CCIPR_LPTIM345SEL)
03234 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
03235                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
03236 #else
03237 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
03238                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
03239 #endif /* RCC_D3CCIPR_LPTIM345SEL */
03240
03241 /** @brief  macro to get the LPTIM3/4/5 clock source.
03242   * @retval The clock source can be one of the following values:
03243   *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
03244   *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
03245   *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
03246   *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
03247   *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
03248   *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
03249   */
03250 #if defined(RCC_D3CCIPR_LPTIM345SEL)
03251 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
03252 #else
03253 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
03254 #endif /* RCC_D3CCIPR_LPTIM345SEL */
03255
03256 /** @brief  macro to configure the LPTIM3 clock source.
03257   *
03258   * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
03259   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
03260   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
03261   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
03262   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
03263   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
03264   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
03265   */
03266 #define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG
03267
03268 /** @brief  macro to get the LPTIM3 clock source.
03269   * @retval The clock source can be one of the following values:
03270   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
03271   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
03272   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
03273   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
03274   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
03275   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
03276   */
03277 #define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
03278
03279 #if defined(LPTIM4)
03280 /** @brief  macro to configure the LPTIM4 clock source.
03281   *
03282   * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
03283   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
03284   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
03285   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
03286   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
03287   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
03288   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
03289   */
03290 #define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG
03291
03292
03293 /** @brief  macro to get the LPTIM4 clock source.
03294   * @retval The clock source can be one of the following values:
03295   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
03296   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
03297   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
03298   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
03299   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
03300   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
03301   */
03302 #define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
03303 #endif /* LPTIM4 */
03304
03305 #if defined(LPTIM5)
03306 /** @brief  macro to configure the LPTIM5 clock source.
03307   *
03308   * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
03309   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
03310   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
03311   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
03312   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
03313   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
03314   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
03315   */
03316 #define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG
03317
03318
03319 /** @brief  macro to get the LPTIM5 clock source.
03320   * @retval The clock source can be one of the following values:
03321   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
03322   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
03323   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
03324   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
03325   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
03326   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
03327   */
03328 #define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
03329 #endif /* LPTIM5 */
03330
03331 #if defined(QUADSPI)
03332 /** @brief  macro to configure the QSPI clock source.
03333   *
03334   * @param  __QSPICLKSource__ specifies the QSPI clock source.
03335   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
03336   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
03337   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
03338   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
03339   */
03340 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
03341                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
03342
03343
03344 /** @brief  macro to get the QSPI clock source.
03345   * @retval The clock source can be one of the following values:
03346   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
03347   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
03348   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
03349   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
03350   */
03351 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
03352 #endif /* QUADSPI */
03353
03354 #if defined(OCTOSPI1) || defined(OCTOSPI2)
03355 /** @brief  macro to configure the OSPI clock source.
03356   *
03357   * @param  __OSPICLKSource__ specifies the OSPI clock source.
03358   *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
03359   *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
03360   *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
03361   *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
03362   */
03363 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
03364                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
03365
03366
03367 /** @brief  macro to get the OSPI clock source.
03368   * @retval The clock source can be one of the following values:
03369   *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
03370   *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
03371   *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
03372   *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
03373   */
03374 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
03375 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
03376
03377
03378 #if defined(DSI)
03379 /** @brief  macro to configure the DSI clock source.
03380   *
03381   * @param  __DSICLKSource__ specifies the DSI clock source.
03382   *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
03383   *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock
03384   */
03385 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
03386                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
03387
03388
03389 /** @brief  macro to get the DSI clock source.
03390   * @retval The clock source can be one of the following values:
03391   *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
03392   *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
03393   */
03394 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
03395 #endif /*DSI*/
03396
03397 /** @brief  macro to configure the FMC clock source.
03398   *
03399   * @param  __FMCCLKSource__ specifies the FMC clock source.
03400   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
03401   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
03402   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
03403   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
03404   */
03405 #if defined(RCC_D1CCIPR_FMCSEL)
03406 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
03407                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
03408 #else
03409 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
03410                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
03411 #endif /* RCC_D1CCIPR_FMCSEL */
03412
03413 /** @brief  macro to get the FMC clock source.
03414   * @retval The clock source can be one of the following values:
03415   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
03416   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
03417   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
03418   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
03419   */
03420 #if defined(RCC_D1CCIPR_FMCSEL)
03421 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
03422 #else
03423 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
03424 #endif /* RCC_D1CCIPR_FMCSEL */
03425
03426 /** @brief  Macro to configure the USB clock (USBCLK).
03427   * @param  __USBCLKSource__ specifies the USB clock source.
03428   *         This parameter can be one of the following values:
03429   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
03430   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
03431   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
03432   */
03433 #if defined(RCC_D2CCIP2R_USBSEL)
03434 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
03435                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
03436 #else
03437 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
03438                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
03439 #endif /* RCC_D2CCIP2R_USBSEL */
03440
03441 /** @brief  Macro to get the USB clock source.
03442   * @retval The clock source can be one of the following values:
03443   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
03444   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
03445   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
03446   */
03447 #if defined(RCC_D2CCIP2R_USBSEL)
03448 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
03449 #else
03450 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
03451 #endif /* RCC_D2CCIP2R_USBSEL */
03452
03453 /** @brief  Macro to configure the ADC clock
03454   * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.
03455   *         This parameter can be one of the following values:
03456   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
03457   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
03458   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
03459   */
03460 #if defined(RCC_D3CCIPR_ADCSEL)
03461 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
03462                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
03463 #else
03464 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
03465                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
03466 #endif /* RCC_D3CCIPR_ADCSEL */
03467
03468 /** @brief  Macro to get the ADC clock source.
03469   * @retval The clock source can be one of the following values:
03470   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
03471   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
03472   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
03473   */
03474 #if defined(RCC_D3CCIPR_ADCSEL)
03475 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
03476 #else
03477 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
03478 #endif /* RCC_D3CCIPR_ADCSEL */
03479
03480  /** @brief  Macro to configure the SWPMI1 clock
03481   * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
03482   *         This parameter can be one of the following values:
03483   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
03484   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
03485   */
03486 #if defined(RCC_D2CCIP1R_SWPSEL)
03487 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
03488                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
03489 #else
03490 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
03491                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
03492 #endif /* RCC_D2CCIP1R_SWPSEL */
03493
03494 /** @brief  Macro to get the SWPMI1 clock source.
03495   * @retval The clock source can be one of the following values:
03496   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
03497   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
03498   */
03499 #if defined(RCC_D2CCIP1R_SWPSEL)
03500 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
03501 #else
03502 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
03503 #endif /* RCC_D2CCIP1R_SWPSEL */
03504
03505  /** @brief  Macro to configure the DFSDM1 clock
03506   * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
03507   *         This parameter can be one of the following values:
03508   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
03509   *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
03510   */
03511 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
03512 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
03513                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
03514 #else
03515 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
03516                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
03517 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
03518
03519 /** @brief  Macro to get the DFSDM1 clock source.
03520   * @retval The clock source can be one of the following values:
03521   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
03522   *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
03523   */
03524 #if defined (RCC_D2CCIP1R_DFSDM1SEL)
03525 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
03526 #else
03527 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
03528 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
03529
03530 #if defined(DFSDM2_BASE)
03531  /** @brief  Macro to configure the DFSDM2 clock
03532   * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
03533   *         This parameter can be one of the following values:
03534   *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
03535   *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
03536   */
03537 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
03538                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
03539
03540 /** @brief  Macro to get the DFSDM2 clock source.
03541   * @retval The clock source can be one of the following values:
03542   *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
03543   *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
03544   */
03545 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
03546 #endif /* DFSDM2 */
03547
03548 /** @brief macro to configure the CEC clock (CECCLK).
03549   *
03550   * @param  __CECCLKSource__ specifies the CEC clock source.
03551   *          This parameter can be one of the following values:
03552   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
03553   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
03554   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
03555   */
03556 #if defined(RCC_D2CCIP2R_CECSEL)
03557 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
03558                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
03559 #else
03560 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
03561                   MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
03562 #endif /* RCC_D2CCIP2R_CECSEL */
03563
03564 /** @brief  macro to get the CEC clock source.
03565   * @retval The clock source can be one of the following values:
03566   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
03567   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
03568   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
03569   */
03570 #if defined(RCC_D2CCIP2R_CECSEL)
03571 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
03572 #else
03573 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
03574 #endif /* RCC_D2CCIP2R_CECSEL */
03575
03576 /** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
03577   * @param  __CLKPSource__ specifies Oscillator clock for peripheral
03578   *         This parameter can be one of the following values:
03579   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
03580   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
03581   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
03582   */
03583 #if defined(RCC_D1CCIPR_CKPERSEL)
03584 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
03585                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
03586 #else
03587 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
03588                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
03589 #endif /* RCC_D1CCIPR_CKPERSEL */
03590
03591 /** @brief  Macro to get the Oscillator clock for peripheral  source.
03592   * @retval The clock source can be one of the following values:
03593   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
03594   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
03595   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
03596   */
03597 #if defined(RCC_D1CCIPR_CKPERSEL)
03598 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
03599 #else
03600 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
03601 #endif /* RCC_D1CCIPR_CKPERSEL */
03602
03603 #if defined(FDCAN1) || defined(FDCAN2)
03604 /** @brief  Macro to configure the FDCAN clock
03605   * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN
03606   *         This parameter can be one of the following values:
03607   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
03608   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
03609   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
03610   */
03611 #if defined(RCC_D2CCIP1R_FDCANSEL)
03612 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
03613                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
03614 #else
03615 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
03616                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
03617 #endif /* RCC_D2CCIP1R_FDCANSEL */
03618
03619 /** @brief  Macro to get the FDCAN clock
03620   * @retval The clock source can be one of the following values:
03621   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
03622   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
03623   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
03624   */
03625 #if defined(RCC_D2CCIP1R_FDCANSEL)
03626 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
03627 #else
03628 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
03629 #endif /* RCC_D2CCIP1R_FDCANSEL */
03630
03631 #endif /*FDCAN1 || FDCAN2*/
03632
03633 /**
03634   * @brief  Macro to Configure the SPI1/2/3 clock source.
03635   * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
03636   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
03637   *          This parameter can be one of the following values:
03638   *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
03639   *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
03640   *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
03641   *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
03642   *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
03643   * @retval None
03644   */
03645 #if defined(RCC_D2CCIP1R_SPI123SEL)
03646 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
03647                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
03648 #else
03649 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
03650                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
03651 #endif /* RCC_D2CCIP1R_SPI123SEL */
03652
03653 /** @brief  Macro to get the SPI1/2/3 clock source.
03654   * @retval The clock source can be one of the following values:
03655   *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
03656   *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
03657   *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
03658   *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
03659   *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
03660   */
03661 #if defined(RCC_D2CCIP1R_SPI123SEL)
03662 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
03663 #else
03664 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
03665 #endif /* RCC_D2CCIP1R_SPI123SEL */
03666
03667 /**
03668   * @brief  Macro to Configure the SPI1 clock source.
03669   * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
03670   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
03671   *          This parameter can be one of the following values:
03672   *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
03673   *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
03674   *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
03675   *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
03676   *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
03677   * @retval None
03678   */
03679 #define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG
03680
03681 /** @brief  Macro to get the SPI1 clock source.
03682   * @retval The clock source can be one of the following values:
03683   *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
03684   *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
03685   *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
03686   *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
03687   *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
03688   */
03689 #define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
03690
03691 /**
03692   * @brief  Macro to Configure the SPI2 clock source.
03693   * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
03694   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
03695   *          This parameter can be one of the following values:
03696   *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
03697   *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
03698   *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
03699   *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
03700   *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
03701   * @retval None
03702   */
03703 #define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG
03704
03705 /** @brief  Macro to get the SPI2 clock source.
03706   * @retval The clock source can be one of the following values:
03707   *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
03708   *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
03709   *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
03710   *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
03711   *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
03712   */
03713 #define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
03714
03715 /**
03716   * @brief  Macro to Configure the SPI3 clock source.
03717   * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
03718   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
03719   *          This parameter can be one of the following values:
03720   *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
03721   *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
03722   *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
03723   *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
03724   *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
03725   * @retval None
03726   */
03727 #define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG
03728
03729 /** @brief  Macro to get the SPI3 clock source.
03730   * @retval The clock source can be one of the following values:
03731   *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
03732   *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
03733   *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
03734   *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
03735   *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
03736   */
03737 #define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
03738
03739 /**
03740   * @brief  Macro to Configure the SPI4/5 clock source.
03741   * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
03742   *         from system PCLK, PLL2, PLL3, OSC
03743   *          This parameter can be one of the following values:
03744   *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
03745   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
03746   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
03747   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
03748   *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
03749   *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
03750   * @retval None
03751   */
03752 #if defined(RCC_D2CCIP1R_SPI45SEL)
03753 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
03754                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
03755 #else
03756 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
03757                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
03758 #endif /* RCC_D2CCIP1R_SPI45SEL */
03759
03760 /** @brief  Macro to get the SPI4/5 clock source.
03761   * @retval The clock source can be one of the following values:
03762   *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
03763   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
03764   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
03765   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
03766   *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
03767   *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
03768 */
03769 #if defined(RCC_D2CCIP1R_SPI45SEL)
03770 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
03771 #else
03772 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
03773 #endif /* RCC_D2CCIP1R_SPI45SEL */
03774
03775 /**
03776   * @brief  Macro to Configure the SPI4 clock source.
03777   * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
03778   *         from system PCLK, PLL2, PLL3, OSC
03779   *          This parameter can be one of the following values:
03780   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
03781   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
03782   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
03783   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
03784   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
03785   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
03786   * @retval None
03787   */
03788 #define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG
03789
03790 /** @brief  Macro to get the SPI4 clock source.
03791   * @retval The clock source can be one of the following values:
03792   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
03793   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
03794   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
03795   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
03796   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
03797   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
03798 */
03799 #define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
03800
03801 /**
03802   * @brief  Macro to Configure the SPI5 clock source.
03803   * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
03804   *         from system PCLK, PLL2, PLL3, OSC
03805   *          This parameter can be one of the following values:
03806   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
03807   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
03808   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
03809   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
03810   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
03811   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
03812   * @retval None
03813   */
03814 #define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG
03815
03816 /** @brief  Macro to get the SPI5 clock source.
03817   * @retval The clock source can be one of the following values:
03818   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
03819   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
03820   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
03821   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
03822   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
03823   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
03824 */
03825 #define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
03826
03827 /**
03828   * @brief  Macro to Configure the SPI6 clock source.
03829   * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
03830   *         from system PCLK, PLL2, PLL3, OSC
03831   *          This parameter can be one of the following values:
03832   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
03833   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
03834   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
03835   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
03836   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
03837   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
03838   *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)
03839   *
03840   * @retval None
03841   *
03842   * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
03843   *
03844   */
03845 #if defined(RCC_D3CCIPR_SPI6SEL)
03846 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
03847                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
03848 #else
03849 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
03850                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
03851 #endif /* RCC_D3CCIPR_SPI6SEL */
03852
03853 /** @brief  Macro to get the SPI6 clock source.
03854   * @retval The clock source can be one of the following values:
03855   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
03856   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
03857   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
03858   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
03859   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
03860   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
03861   *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN
03862 */
03863 #if defined(RCC_D3CCIPR_SPI6SEL)
03864 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
03865 #else
03866 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
03867 #endif /* RCC_D3CCIPR_SPI6SEL */
03868
03869 /** @brief  Macro to configure the SDMMC clock
03870   * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC
03871   *         This parameter can be one of the following values:
03872   *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
03873   *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
03874   */
03875 #if defined(RCC_D1CCIPR_SDMMCSEL)
03876 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
03877                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
03878 #else
03879 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
03880                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
03881 #endif /* RCC_D1CCIPR_SDMMCSEL */
03882
03883 /** @brief  Macro to get the SDMMC clock
03884   */
03885 #if defined(RCC_D1CCIPR_SDMMCSEL)
03886 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
03887 #else
03888 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
03889 #endif /* RCC_D1CCIPR_SDMMCSEL */
03890
03891 /** @brief macro to configure the RNG clock (RNGCLK).
03892   *
03893   * @param  __RNGCLKSource__ specifies the RNG clock source.
03894   *          This parameter can be one of the following values:
03895   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
03896   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
03897   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
03898   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
03899   */
03900 #if defined(RCC_D2CCIP2R_RNGSEL)
03901 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
03902                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
03903 #else
03904 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
03905                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
03906 #endif /* RCC_D2CCIP2R_RNGSEL */
03907
03908 /** @brief  macro to get the RNG clock source.
03909   * @retval The clock source can be one of the following values:
03910   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
03911   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
03912   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
03913   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
03914   */
03915 #if defined(RCC_D2CCIP2R_RNGSEL)
03916 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
03917 #else
03918 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
03919 #endif /* RCC_D2CCIP2R_RNGSEL */
03920
03921 #if defined(HRTIM1)
03922 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
03923   * @{
03924   */
03925 /** @brief  Macro to configure the HRTIM1 prescaler clock source.
03926   * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
03927   *         This parameter can be one of the following values:
03928   *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
03929   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
03930   */
03931 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
03932                   MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
03933
03934 /** @brief  Macro to get the HRTIM1 clock source.
03935   * @retval The clock source can be one of the following values:
03936   *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
03937   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
03938   */
03939 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
03940 #endif /* HRTIM1 */
03941
03942 /** @brief  Macro to configure the Timers clocks prescalers
03943   * @param  __PRESC__  specifies the Timers clocks prescalers selection
03944   *         This parameter can be one of the following values:
03945   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
03946   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
03947   *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
03948   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
03949   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
03950   *                 else it is equal to 4 x Frcc_pclkx_d2
03951   */
03952 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
03953                                                  RCC->CFGR |= (__PRESC__);       \
03954                                                 }while(0)
03955
03956 /**
03957   * @}
03958   */
03959 /**
03960   * @brief  Enable the specified CRS interrupts.
03961   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
03962   *          This parameter can be any combination of the following values:
03963   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
03964   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
03965   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
03966   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
03967   * @retval None
03968   */
03969 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
03970
03971 /**
03972   * @brief  Disable the specified CRS interrupts.
03973   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
03974   *          This parameter can be any combination of the following values:
03975   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
03976   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
03977   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
03978   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
03979   * @retval None
03980   */
03981 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
03982
03983 /** @brief  Check whether the CRS interrupt has occurred or not.
03984   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
03985   *         This parameter can be one of the following values:
03986   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
03987   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
03988   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
03989   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
03990   * @retval The new state of __INTERRUPT__ (SET or RESET).
03991   */
03992 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
03993
03994 /** @brief  Clear the CRS interrupt pending bits
03995   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
03996   *         This parameter can be any combination of the following values:
03997   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
03998   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
03999   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
04000   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
04001   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
04002   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
04003   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
04004   */
04005 /* CRS IT Error Mask */
04006 #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
04007
04008 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
04009                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
04010                                                  { \
04011                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
04012                                                  } \
04013                                                  else \
04014                                                  { \
04015                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
04016                                                  } \
04017                                                } while(0)
04018
04019 /**
04020   * @brief  Check whether the specified CRS flag is set or not.
04021   * @param  __FLAG__ specifies the flag to check.
04022   *          This parameter can be one of the following values:
04023   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
04024   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
04025   *              @arg @ref RCC_CRS_FLAG_ERR  Error
04026   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
04027   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
04028   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
04029   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
04030   * @retval The new state of _FLAG_ (TRUE or FALSE).
04031   */
04032 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
04033
04034 /**
04035   * @brief  Clear the CRS specified FLAG.
04036   * @param __FLAG__ specifies the flag to clear.
04037   *          This parameter can be one of the following values:
04038   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
04039   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
04040   *              @arg @ref RCC_CRS_FLAG_ERR  Error
04041   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
04042   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
04043   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
04044   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
04045   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
04046   * @retval None
04047   */
04048
04049 /* CRS Flag Error Mask */
04050 #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
04051
04052 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
04053                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
04054                                                  { \
04055                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
04056                                                  } \
04057                                                  else \
04058                                                  { \
04059                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
04060                                                  } \
04061                                                } while(0)
04062
04063  /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
04064   * @{
04065   */
04066 /**
04067   * @brief  Enable the oscillator clock for frequency error counter.
04068   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
04069   * @retval None
04070   */
04071 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
04072
04073 /**
04074   * @brief  Disable the oscillator clock for frequency error counter.
04075   * @retval None
04076   */
04077 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
04078
04079 /**
04080   * @brief  Enable the automatic hardware adjustment of TRIM bits.
04081   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
04082   * @retval None
04083   */
04084 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
04085
04086 /**
04087   * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
04088   * @retval None
04089   */
04090 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
04091
04092 /**
04093   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
04094   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
04095   *             of the synchronization source after pre-scaling. It is then decreased by one in order to
04096   *             reach the expected synchronization on the zero value. The formula is the following:
04097   *             RELOAD = (fTARGET / fSYNC) -1
04098   * @param  __FTARGET__ Target frequency (value in Hz)
04099   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
04100   * @retval None
04101   */
04102 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
04103
04104 /**
04105   * @}
04106   */
04107
04108 /**
04109   * @}
04110   */
04111
04112
04113 /**
04114   * @}
04115   */
04116
04117 /**
04118   * @}
04119   */
04120
04121 #ifdef __cplusplus
04122 }
04123 #endif
04124
04125 #endif /* STM32H7xx_HAL_RCC_EX_H */
04126
04127 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng.c Source File

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stm32h7xx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Random Number Generator (RNG) peripheral:
00008   *           + Initialization and configuration functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017       The RNG HAL driver can be used as follows:
00018
00019       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00020           in HAL_RNG_MspInit().
00021       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00022       (#) Wait until the 32 bit Random Number Generator contains a valid
00023           random data using (polling/interrupt) mode.
00024       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00025
00026     ##### Callback registration #####
00027     ==================================
00028
00029     [..]
00030     The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
00031     allows the user to configure dynamically the driver callbacks.
00032
00033     [..]
00034     Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
00035     Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
00036     (+) ErrorCallback             : RNG Error Callback.
00037     (+) MspInitCallback           : RNG MspInit.
00038     (+) MspDeInitCallback         : RNG MspDeInit.
00039     This function takes as parameters the HAL peripheral handle, the Callback ID
00040     and a pointer to the user callback function.
00041
00042     [..]
00043     Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
00044     weak (surcharged) function.
00045     @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00046     and the Callback ID.
00047     This function allows to reset following callbacks:
00048     (+) ErrorCallback             : RNG Error Callback.
00049     (+) MspInitCallback           : RNG MspInit.
00050     (+) MspDeInitCallback         : RNG MspDeInit.
00051
00052     [..]
00053     For specific callback ReadyDataCallback, use dedicated register callbacks:
00054     respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
00055
00056     [..]
00057     By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
00058     all callbacks are set to the corresponding weak (surcharged) functions:
00059     example @ref HAL_RNG_ErrorCallback().
00060     Exception done for MspInit and MspDeInit functions that are respectively
00061     reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
00062     and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
00063     If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
00064     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00065
00066     [..]
00067     Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
00068     Exception done MspInit/MspDeInit that can be registered/unregistered
00069     in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
00070     MspInit/DeInit callbacks can be used during the Init/DeInit.
00071     In that case first register the MspInit/MspDeInit user callbacks
00072     using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
00073     or @ref HAL_RNG_Init() function.
00074
00075     [..]
00076     When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
00077     not defined, the callback registration feature is not available
00078     and weak (surcharged) callbacks are used.
00079
00080   @endverbatim
00081   ******************************************************************************
00082   * @attention
00083   *
00084   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00085   * All rights reserved.</center></h2>
00086   *
00087   * This software component is licensed by ST under BSD 3-Clause license,
00088   * the "License"; You may not use this file except in compliance with the
00089   * License. You may obtain a copy of the License at:
00090   *                        opensource.org/licenses/BSD-3-Clause
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32h7xx_hal.h"
00097
00098 /** @addtogroup STM32H7xx_HAL_Driver
00099   * @{
00100   */
00101
00102 #if defined (RNG)
00103
00104 /** @addtogroup RNG
00105   * @brief RNG HAL module driver.
00106   * @{
00107   */
00108
00109 #ifdef HAL_RNG_MODULE_ENABLED
00110
00111 /* Private types -------------------------------------------------------------*/
00112 /* Private defines -----------------------------------------------------------*/
00113 /** @defgroup RNG_Private_Defines
00114   * @{
00115   */
00116 /*  Health test control register information to use in CCM algorithm */
00117 #define RNG_HTCFG_1   0x17590ABCU /*!< magic number */
00118 #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
00119 #define RNG_HTCFG     0x000CAA74U /*!< for best latency and To be compliant with NIST */
00120 #else /*RNG_VER_3_2*/
00121 #define RNG_HTCFG     0x00007274U /*!< for best latency and To be compliant with NIST */
00122 #endif
00123 /**
00124   * @}
00125   */
00126 /* Private variables ---------------------------------------------------------*/
00127 /* Private constants ---------------------------------------------------------*/
00128 /** @defgroup RNG_Private_Constants RNG Private Constants
00129   * @{
00130   */
00131 #define RNG_TIMEOUT_VALUE     2U
00132 /**
00133   * @}
00134   */
00135 /* Private macros ------------------------------------------------------------*/
00136 /* Private functions prototypes ----------------------------------------------*/
00137 /* Private functions ---------------------------------------------------------*/
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @addtogroup RNG_Exported_Functions
00141   * @{
00142   */
00143
00144 /** @addtogroup RNG_Exported_Functions_Group1
00145  *  @brief   Initialization and configuration functions
00146  *
00147 @verbatim
00148  ===============================================================================
00149           ##### Initialization and configuration functions #####
00150  ===============================================================================
00151     [..]  This section provides functions allowing to:
00152       (+) Initialize the RNG according to the specified parameters
00153           in the RNG_InitTypeDef and create the associated handle
00154       (+) DeInitialize the RNG peripheral
00155       (+) Initialize the RNG MSP
00156       (+) DeInitialize RNG MSP
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initializes the RNG peripheral and creates the associated handle.
00164   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00165   *                the configuration information for RNG.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00169 {
00170   uint32_t tickstart;
00171   /* Check the RNG handle allocation */
00172   if (hrng == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176   /* Check the parameters */
00177   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00178   assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
00179
00180 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00181   if (hrng->State == HAL_RNG_STATE_RESET)
00182   {
00183     /* Allocate lock resource and initialize it */
00184     hrng->Lock = HAL_UNLOCKED;
00185
00186     hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
00187     hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
00188
00189     if (hrng->MspInitCallback == NULL)
00190     {
00191       hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
00192     }
00193
00194     /* Init the low level hardware */
00195     hrng->MspInitCallback(hrng);
00196   }
00197 #else
00198   if (hrng->State == HAL_RNG_STATE_RESET)
00199   {
00200     /* Allocate lock resource and initialize it */
00201     hrng->Lock = HAL_UNLOCKED;
00202
00203     /* Init the low level hardware */
00204     HAL_RNG_MspInit(hrng);
00205   }
00206 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00207
00208   /* Change RNG peripheral state */
00209   hrng->State = HAL_RNG_STATE_BUSY;
00210
00211 #if defined(RNG_CR_CONDRST)
00212   /* Disable RNG */
00213   __HAL_RNG_DISABLE(hrng);
00214
00215   /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
00216   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
00217
00218 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
00219   /*!< magic number must be written immediately before to RNG_HTCRG */
00220   WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
00221   /* for best latency and to be compliant with NIST */
00222   WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
00223 #endif
00224
00225   /* Writing bits CONDRST=0*/
00226   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
00227
00228   /* Get tick */
00229   tickstart = HAL_GetTick();
00230
00231   /* Wait for conditioning reset process to be completed */
00232   while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
00233   {
00234     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00235     {
00236       hrng->State = HAL_RNG_STATE_READY;
00237       hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00238       return HAL_ERROR;
00239     }
00240   }
00241 #else
00242   /* Clock Error Detection Configuration */
00243   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
00244 #endif /* end of RNG_CR_CONDRST */
00245
00246   /* Enable the RNG Peripheral */
00247   __HAL_RNG_ENABLE(hrng);
00248
00249   /* verify that no seed error */
00250   if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
00251   {
00252     hrng->State = HAL_RNG_STATE_ERROR;
00253     return HAL_ERROR;
00254   }
00255   /* Get tick */
00256   tickstart = HAL_GetTick();
00257   /* Check if data register contains valid random data */
00258   while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
00259   {
00260     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00261     {
00262       hrng->State = HAL_RNG_STATE_ERROR;
00263       hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00264       return HAL_ERROR;
00265     }
00266   }
00267
00268   /* Initialize the RNG state */
00269   hrng->State = HAL_RNG_STATE_READY;
00270
00271   /* Initialise the error code */
00272   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00273
00274   /* Return function status */
00275   return HAL_OK;
00276 }
00277
00278 /**
00279   * @brief  DeInitializes the RNG peripheral.
00280   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00281   *                the configuration information for RNG.
00282   * @retval HAL status
00283   */
00284 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00285 {
00286 #if defined(RNG_CR_CONDRST)
00287   uint32_t tickstart;
00288
00289 #endif /* RNG_CR_CONDRST */
00290   /* Check the RNG handle allocation */
00291   if (hrng == NULL)
00292   {
00293     return HAL_ERROR;
00294   }
00295
00296 #if defined(RNG_CR_CONDRST)
00297   /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
00298   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
00299
00300   /* Writing bits CONDRST=0*/
00301   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
00302
00303   /* Get tick */
00304   tickstart = HAL_GetTick();
00305
00306   /* Wait for conditioning reset process to be completed */
00307   while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
00308   {
00309     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00310     {
00311       hrng->State = HAL_RNG_STATE_READY;
00312       hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00313       /* Process Unlocked */
00314       __HAL_UNLOCK(hrng);
00315       return HAL_ERROR;
00316     }
00317   }
00318
00319 #else
00320   /* Clear Clock Error Detection bit */
00321   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
00322 #endif /* RNG_CR_CONDRST */
00323   /* Disable the RNG Peripheral */
00324   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00325
00326   /* Clear RNG interrupt status flags */
00327   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00328
00329 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00330   if (hrng->MspDeInitCallback == NULL)
00331   {
00332     hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
00333   }
00334
00335   /* DeInit the low level hardware */
00336   hrng->MspDeInitCallback(hrng);
00337 #else
00338   /* DeInit the low level hardware */
00339   HAL_RNG_MspDeInit(hrng);
00340 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00341
00342   /* Update the RNG state */
00343   hrng->State = HAL_RNG_STATE_RESET;
00344
00345   /* Initialise the error code */
00346   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00347
00348   /* Release Lock */
00349   __HAL_UNLOCK(hrng);
00350
00351   /* Return the function status */
00352   return HAL_OK;
00353 }
00354
00355 /**
00356   * @brief  Initializes the RNG MSP.
00357   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00358   *                the configuration information for RNG.
00359   * @retval None
00360   */
00361 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00362 {
00363   /* Prevent unused argument(s) compilation warning */
00364   UNUSED(hrng);
00365   /* NOTE : This function should not be modified. When the callback is needed,
00366             function HAL_RNG_MspInit must be implemented in the user file.
00367    */
00368 }
00369
00370 /**
00371   * @brief  DeInitializes the RNG MSP.
00372   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00373   *                the configuration information for RNG.
00374   * @retval None
00375   */
00376 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00377 {
00378   /* Prevent unused argument(s) compilation warning */
00379   UNUSED(hrng);
00380   /* NOTE : This function should not be modified. When the callback is needed,
00381             function HAL_RNG_MspDeInit must be implemented in the user file.
00382    */
00383 }
00384
00385 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00386 /**
00387   * @brief  Register a User RNG Callback
00388   *         To be used instead of the weak predefined callback
00389   * @param  hrng RNG handle
00390   * @param  CallbackID ID of the callback to be registered
00391   *         This parameter can be one of the following values:
00392   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00393   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00394   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00395   * @param  pCallback pointer to the Callback function
00396   * @retval HAL status
00397   */
00398 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
00399 {
00400   HAL_StatusTypeDef status = HAL_OK;
00401
00402   if (pCallback == NULL)
00403   {
00404     /* Update the error code */
00405     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00406     return HAL_ERROR;
00407   }
00408   /* Process locked */
00409   __HAL_LOCK(hrng);
00410
00411   if (HAL_RNG_STATE_READY == hrng->State)
00412   {
00413     switch (CallbackID)
00414     {
00415       case HAL_RNG_ERROR_CB_ID :
00416         hrng->ErrorCallback = pCallback;
00417         break;
00418
00419       case HAL_RNG_MSPINIT_CB_ID :
00420         hrng->MspInitCallback = pCallback;
00421         break;
00422
00423       case HAL_RNG_MSPDEINIT_CB_ID :
00424         hrng->MspDeInitCallback = pCallback;
00425         break;
00426
00427       default :
00428         /* Update the error code */
00429         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00430         /* Return error status */
00431         status =  HAL_ERROR;
00432         break;
00433     }
00434   }
00435   else if (HAL_RNG_STATE_RESET == hrng->State)
00436   {
00437     switch (CallbackID)
00438     {
00439       case HAL_RNG_MSPINIT_CB_ID :
00440         hrng->MspInitCallback = pCallback;
00441         break;
00442
00443       case HAL_RNG_MSPDEINIT_CB_ID :
00444         hrng->MspDeInitCallback = pCallback;
00445         break;
00446
00447       default :
00448         /* Update the error code */
00449         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00450         /* Return error status */
00451         status =  HAL_ERROR;
00452         break;
00453     }
00454   }
00455   else
00456   {
00457     /* Update the error code */
00458     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00459     /* Return error status */
00460     status =  HAL_ERROR;
00461   }
00462
00463   /* Release Lock */
00464   __HAL_UNLOCK(hrng);
00465   return status;
00466 }
00467
00468 /**
00469   * @brief  Unregister an RNG Callback
00470   *         RNG callabck is redirected to the weak predefined callback
00471   * @param  hrng RNG handle
00472   * @param  CallbackID ID of the callback to be unregistered
00473   *         This parameter can be one of the following values:
00474   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00475   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00476   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00477   * @retval HAL status
00478   */
00479 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
00480 {
00481   HAL_StatusTypeDef status = HAL_OK;
00482
00483   /* Process locked */
00484   __HAL_LOCK(hrng);
00485
00486   if (HAL_RNG_STATE_READY == hrng->State)
00487   {
00488     switch (CallbackID)
00489     {
00490       case HAL_RNG_ERROR_CB_ID :
00491         hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
00492         break;
00493
00494       case HAL_RNG_MSPINIT_CB_ID :
00495         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00496         break;
00497
00498       case HAL_RNG_MSPDEINIT_CB_ID :
00499         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
00500         break;
00501
00502       default :
00503         /* Update the error code */
00504         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00505         /* Return error status */
00506         status =  HAL_ERROR;
00507         break;
00508     }
00509   }
00510   else if (HAL_RNG_STATE_RESET == hrng->State)
00511   {
00512     switch (CallbackID)
00513     {
00514       case HAL_RNG_MSPINIT_CB_ID :
00515         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00516         break;
00517
00518       case HAL_RNG_MSPDEINIT_CB_ID :
00519         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
00520         break;
00521
00522       default :
00523         /* Update the error code */
00524         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00525         /* Return error status */
00526         status =  HAL_ERROR;
00527         break;
00528     }
00529   }
00530   else
00531   {
00532     /* Update the error code */
00533     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00534     /* Return error status */
00535     status =  HAL_ERROR;
00536   }
00537
00538   /* Release Lock */
00539   __HAL_UNLOCK(hrng);
00540   return status;
00541 }
00542
00543 /**
00544   * @brief  Register Data Ready RNG Callback
00545   *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
00546   * @param  hrng RNG handle
00547   * @param  pCallback pointer to the Data Ready Callback function
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
00551 {
00552   HAL_StatusTypeDef status = HAL_OK;
00553
00554   if (pCallback == NULL)
00555   {
00556     /* Update the error code */
00557     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00558     return HAL_ERROR;
00559   }
00560   /* Process locked */
00561   __HAL_LOCK(hrng);
00562
00563   if (HAL_RNG_STATE_READY == hrng->State)
00564   {
00565     hrng->ReadyDataCallback = pCallback;
00566   }
00567   else
00568   {
00569     /* Update the error code */
00570     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00571     /* Return error status */
00572     status =  HAL_ERROR;
00573   }
00574
00575   /* Release Lock */
00576   __HAL_UNLOCK(hrng);
00577   return status;
00578 }
00579
00580 /**
00581   * @brief  UnRegister the Data Ready RNG Callback
00582   *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
00583   * @param  hrng RNG handle
00584   * @retval HAL status
00585   */
00586 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
00587 {
00588   HAL_StatusTypeDef status = HAL_OK;
00589
00590   /* Process locked */
00591   __HAL_LOCK(hrng);
00592
00593   if (HAL_RNG_STATE_READY == hrng->State)
00594   {
00595     hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
00596   }
00597   else
00598   {
00599     /* Update the error code */
00600     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00601     /* Return error status */
00602     status =  HAL_ERROR;
00603   }
00604
00605   /* Release Lock */
00606   __HAL_UNLOCK(hrng);
00607   return status;
00608 }
00609
00610 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /** @addtogroup RNG_Exported_Functions_Group2
00617  *  @brief   Peripheral Control functions
00618  *
00619 @verbatim
00620  ===============================================================================
00621                       ##### Peripheral Control functions #####
00622  ===============================================================================
00623     [..]  This section provides functions allowing to:
00624       (+) Get the 32 bit Random number
00625       (+) Get the 32 bit Random number with interrupt enabled
00626       (+) Handle RNG interrupt request
00627
00628 @endverbatim
00629   * @{
00630   */
00631
00632 /**
00633   * @brief  Generates a 32-bit random number.
00634   * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
00635   *         random number is available in the DR register (RNG_FLAG_DRDY flag set
00636   *         whenever a random number is available through the RNG_DR register).
00637   *         After transitioning from 0 to 1 (random number available),
00638   *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
00639   *         four words from the RNG_DR register, i.e. further function calls
00640   *         will immediately return a new u32 random number (additional words are
00641   *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
00642   * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
00643   *         flag is automatically cleared.
00644   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00645   *                the configuration information for RNG.
00646   * @param  random32bit pointer to generated random number variable if successful.
00647   * @retval HAL status
00648   */
00649
00650 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00651 {
00652   uint32_t tickstart;
00653   HAL_StatusTypeDef status = HAL_OK;
00654
00655   /* Process Locked */
00656   __HAL_LOCK(hrng);
00657
00658   /* Check RNG peripheral state */
00659   if (hrng->State == HAL_RNG_STATE_READY)
00660   {
00661     /* Change RNG peripheral state */
00662     hrng->State = HAL_RNG_STATE_BUSY;
00663
00664     /* Get tick */
00665     tickstart = HAL_GetTick();
00666
00667     /* Check if data register contains valid random data */
00668     while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00669     {
00670       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00671       {
00672         hrng->State = HAL_RNG_STATE_READY;
00673         hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00674         /* Process Unlocked */
00675         __HAL_UNLOCK(hrng);
00676         return HAL_ERROR;
00677       }
00678     }
00679
00680     /* Get a 32bit Random number */
00681     hrng->RandomNumber = hrng->Instance->DR;
00682     *random32bit = hrng->RandomNumber;
00683
00684     hrng->State = HAL_RNG_STATE_READY;
00685   }
00686   else
00687   {
00688     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00689     status = HAL_ERROR;
00690   }
00691
00692   /* Process Unlocked */
00693   __HAL_UNLOCK(hrng);
00694
00695   return status;
00696 }
00697
00698 /**
00699   * @brief  Generates a 32-bit random number in interrupt mode.
00700   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00701   *                the configuration information for RNG.
00702   * @retval HAL status
00703   */
00704 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00705 {
00706   HAL_StatusTypeDef status = HAL_OK;
00707
00708   /* Process Locked */
00709   __HAL_LOCK(hrng);
00710
00711   /* Check RNG peripheral state */
00712   if (hrng->State == HAL_RNG_STATE_READY)
00713   {
00714     /* Change RNG peripheral state */
00715     hrng->State = HAL_RNG_STATE_BUSY;
00716
00717     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00718     __HAL_RNG_ENABLE_IT(hrng);
00719   }
00720   else
00721   {
00722     /* Process Unlocked */
00723     __HAL_UNLOCK(hrng);
00724
00725     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00726     status = HAL_ERROR;
00727   }
00728
00729   return status;
00730 }
00731
00732 /**
00733   * @brief  Handles RNG interrupt request.
00734   * @note   In the case of a clock error, the RNG is no more able to generate
00735   *         random numbers because the PLL48CLK clock is not correct. User has
00736   *         to check that the clock controller is correctly configured to provide
00737   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00738   *         The clock error has no impact on the previously generated
00739   *         random numbers, and the RNG_DR register contents can be used.
00740   * @note   In the case of a seed error, the generation of random numbers is
00741   *         interrupted as long as the SECS bit is '1'. If a number is
00742   *         available in the RNG_DR register, it must not be used because it may
00743   *         not have enough entropy. In this case, it is recommended to clear the
00744   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00745   *         the RNG peripheral to reinitialize and restart the RNG.
00746   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00747   *         or CEIS are set.
00748   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00749   *                the configuration information for RNG.
00750   * @retval None
00751
00752   */
00753 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00754 {
00755   uint32_t rngclockerror = 0U;
00756
00757   /* RNG clock error interrupt occurred */
00758   if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
00759   {
00760     /* Update the error code */
00761     hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
00762     rngclockerror = 1U;
00763   }
00764   else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
00765   {
00766     /* Update the error code */
00767     hrng->ErrorCode = HAL_RNG_ERROR_SEED;
00768     rngclockerror = 1U;
00769   }
00770   else
00771   {
00772     /* Nothing to do */
00773   }
00774
00775   if (rngclockerror == 1U)
00776   {
00777     /* Change RNG peripheral state */
00778     hrng->State = HAL_RNG_STATE_ERROR;
00779
00780 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00781     /* Call registered Error callback */
00782     hrng->ErrorCallback(hrng);
00783 #else
00784     /* Call legacy weak Error callback */
00785     HAL_RNG_ErrorCallback(hrng);
00786 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00787
00788     /* Clear the clock error flag */
00789     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
00790   }
00791
00792   /* Check RNG data ready interrupt occurred */
00793   if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00794   {
00795     /* Generate random number once, so disable the IT */
00796     __HAL_RNG_DISABLE_IT(hrng);
00797
00798     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00799     hrng->RandomNumber = hrng->Instance->DR;
00800
00801     if (hrng->State != HAL_RNG_STATE_ERROR)
00802     {
00803       /* Change RNG peripheral state */
00804       hrng->State = HAL_RNG_STATE_READY;
00805       /* Process Unlocked */
00806       __HAL_UNLOCK(hrng);
00807
00808 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00809       /* Call registered Data Ready callback */
00810       hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
00811 #else
00812       /* Call legacy weak Data Ready callback */
00813       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00814 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00815     }
00816   }
00817 }
00818
00819 /**
00820   * @brief  Read latest generated random number.
00821   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00822   *                the configuration information for RNG.
00823   * @retval random value
00824   */
00825 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00826 {
00827   return (hrng->RandomNumber);
00828 }
00829
00830 /**
00831   * @brief  Data Ready callback in non-blocking mode.
00832   * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
00833   *         from DR register in IRQ Handler and is provided as callback parameter.
00834   *         Depending on valid data available in the conditioning output buffer,
00835   *         additional words can be read by the application from DR register till
00836   *         DRDY bit remains high.
00837   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00838   *                the configuration information for RNG.
00839   * @param  random32bit generated random number.
00840   * @retval None
00841   */
00842 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00843 {
00844   /* Prevent unused argument(s) compilation warning */
00845   UNUSED(hrng);
00846   UNUSED(random32bit);
00847   /* NOTE : This function should not be modified. When the callback is needed,
00848             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00849    */
00850 }
00851
00852 /**
00853   * @brief  RNG error callbacks.
00854   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00855   *                the configuration information for RNG.
00856   * @retval None
00857   */
00858 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00859 {
00860   /* Prevent unused argument(s) compilation warning */
00861   UNUSED(hrng);
00862   /* NOTE : This function should not be modified. When the callback is needed,
00863             function HAL_RNG_ErrorCallback must be implemented in the user file.
00864    */
00865 }
00866 /**
00867   * @}
00868   */
00869
00870
00871 /** @addtogroup RNG_Exported_Functions_Group3
00872  *  @brief   Peripheral State functions
00873  *
00874 @verbatim
00875  ===============================================================================
00876                       ##### Peripheral State functions #####
00877  ===============================================================================
00878     [..]
00879     This subsection permits to get in run-time the status of the peripheral
00880     and the data flow.
00881
00882 @endverbatim
00883   * @{
00884   */
00885
00886 /**
00887   * @brief  Returns the RNG state.
00888   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00889   *                the configuration information for RNG.
00890   * @retval HAL state
00891   */
00892 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00893 {
00894   return hrng->State;
00895 }
00896
00897 /**
00898   * @brief  Return the RNG handle error code.
00899   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00900   * @retval RNG Error Code
00901 */
00902 uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
00903 {
00904   /* Return RNG Error Code */
00905   return hrng->ErrorCode;
00906 }
00907 /**
00908   * @}
00909   */
00910
00911 /**
00912   * @}
00913   */
00914
00915
00916 #endif /* HAL_RNG_MODULE_ENABLED */
00917 /**
00918   * @}
00919   */
00920
00921 #endif /* RNG */
00922
00923 /**
00924   * @}
00925   */
00926
00927 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng.h Source File

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stm32h7xx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RNG_H
00022 #define STM32H7xx_HAL_RNG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @defgroup RNG RNG
00038   * @brief RNG HAL module driver
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043
00044 /** @defgroup RNG_Exported_Types RNG Exported Types
00045   * @{
00046   */
00047
00048 /** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
00049   * @{
00050   */
00051 typedef struct
00052 {
00053   uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
00054 } RNG_InitTypeDef;
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
00061   * @{
00062   */
00063 typedef enum
00064 {
00065   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00066   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00067   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00068   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00069   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00070
00071 } HAL_RNG_StateTypeDef;
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
00078   * @{
00079   */
00080 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00081 typedef struct  __RNG_HandleTypeDef
00082 #else
00083 typedef struct
00084 #endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
00085 {
00086   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00087
00088   RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
00089
00090   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00091
00092   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00093
00094   __IO  uint32_t              ErrorCode;     /*!< RNG Error code               */
00095
00096   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00097
00098 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00099   void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
00100   void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
00101
00102   void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
00103   void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
00104 #endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
00105
00106 } RNG_HandleTypeDef;
00107
00108 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00109 /**
00110   * @brief  HAL RNG Callback ID enumeration definition
00111   */
00112 typedef enum
00113 {
00114   HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
00115
00116   HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
00117   HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
00118
00119 } HAL_RNG_CallbackIDTypeDef;
00120
00121 /**
00122   * @brief  HAL RNG Callback pointer definition
00123   */
00124 typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
00125 typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
00126
00127 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00143   * @{
00144   */
00145 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00146 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00147 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00153   * @{
00154   */
00155 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00156 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00157 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
00163   * @{
00164   */
00165 #define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
00166 #define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup RNG_Error_Definition   RNG Error Definition
00172   * @{
00173   */
00174 #define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error             */
00175 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00176 #define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
00177 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00178 #define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */
00179 #define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
00180 #define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
00181 #define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported macros -----------------------------------------------------------*/
00191 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00192   * @{
00193   */
00194
00195 /** @brief Reset RNG handle state
00196   * @param  __HANDLE__ RNG Handle
00197   * @retval None
00198   */
00199 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00200 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00201                                                        (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
00202                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00203                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00204                                                     } while(0U)
00205 #else
00206 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00207 #endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
00208
00209 /**
00210   * @brief  Enables the RNG peripheral.
00211   * @param  __HANDLE__ RNG Handle
00212   * @retval None
00213   */
00214 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00215
00216 /**
00217   * @brief  Disables the RNG peripheral.
00218   * @param  __HANDLE__ RNG Handle
00219   * @retval None
00220   */
00221 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00222
00223 /**
00224   * @brief  Check the selected RNG flag status.
00225   * @param  __HANDLE__ RNG Handle
00226   * @param  __FLAG__ RNG flag
00227   *          This parameter can be one of the following values:
00228   *            @arg RNG_FLAG_DRDY:  Data ready
00229   *            @arg RNG_FLAG_CECS:  Clock error current status
00230   *            @arg RNG_FLAG_SECS:  Seed error current status
00231   * @retval The new state of __FLAG__ (SET or RESET).
00232   */
00233 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00234
00235 /**
00236   * @brief  Clears the selected RNG flag status.
00237   * @param  __HANDLE__ RNG handle
00238   * @param  __FLAG__ RNG flag to clear
00239   * @note   WARNING: This is a dummy macro for HAL code alignment,
00240   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00241   * @retval None
00242   */
00243 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00244
00245 /**
00246   * @brief  Enables the RNG interrupts.
00247   * @param  __HANDLE__ RNG Handle
00248   * @retval None
00249   */
00250 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00251
00252 /**
00253   * @brief  Disables the RNG interrupts.
00254   * @param  __HANDLE__ RNG Handle
00255   * @retval None
00256   */
00257 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00258
00259 /**
00260   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00261   * @param  __HANDLE__ RNG Handle
00262   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
00263   *         This parameter can be one of the following values:
00264   *            @arg RNG_IT_DRDY: Data ready interrupt
00265   *            @arg RNG_IT_CEI: Clock error interrupt
00266   *            @arg RNG_IT_SEI: Seed error interrupt
00267   * @retval The new state of __INTERRUPT__ (SET or RESET).
00268   */
00269 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00270
00271 /**
00272   * @brief  Clear the RNG interrupt status flags.
00273   * @param  __HANDLE__ RNG Handle
00274   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
00275   *          This parameter can be one of the following values:
00276   *            @arg RNG_IT_CEI: Clock error interrupt
00277   *            @arg RNG_IT_SEI: Seed error interrupt
00278   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00279   * @retval None
00280   */
00281 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00282
00283 /**
00284   * @}
00285   */
00286
00287 #if defined (RNG_CR_CONDRST)
00288 /* Include HASH HAL Extended module */
00289 #include "stm32h7xx_hal_rng_ex.h"
00290 #endif  /* CONDRST */
00291 /* Exported functions --------------------------------------------------------*/
00292 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00293   * @{
00294   */
00295
00296 /** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
00297   * @{
00298   */
00299 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00300 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
00301 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00302 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00303
00304 /* Callbacks Register/UnRegister functions  ***********************************/
00305 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00306 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
00307 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
00308
00309 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
00310 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
00311 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00318   * @{
00319   */
00320 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00321 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00322 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00323
00324 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00325 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00326 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00333   * @{
00334   */
00335 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00336 uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /* Private macros ------------------------------------------------------------*/
00346 /** @defgroup RNG_Private_Macros RNG Private Macros
00347   * @{
00348   */
00349 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00350                        ((IT) == RNG_IT_SEI))
00351
00352 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00353                             ((FLAG) == RNG_FLAG_CECS) || \
00354                             ((FLAG) == RNG_FLAG_SECS))
00355
00356 /**
00357   * @brief Verify the RNG Clock Error Detection mode.
00358   * @param __MODE__ RNG Clock Error Detection mode
00359   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00360   */
00361 #define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
00362                                 ((__MODE__) == RNG_CED_DISABLE))
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 #endif /* RNG */
00372
00373 /**
00374   * @}
00375   */
00376
00377 #ifdef __cplusplus
00378 }
00379 #endif
00380
00381
00382 #endif /* STM32H7xx_HAL_RNG_H */
00383
00384 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng_ex.c Source File

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stm32h7xx_hal_rng_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RNG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Random Number Generator (RNG) peripheral:
00008   *           + Lock configuration functions
00009   *           + Reset the RNG
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00015   * All rights reserved.</center></h2>
00016   *
00017   * This software component is licensed by ST under BSD 3-Clause license,
00018   * the "License"; You may not use this file except in compliance with the
00019   * License. You may obtain a copy of the License at:
00020   *                        opensource.org/licenses/BSD-3-Clause
00021   *
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32h7xx_hal.h"
00027
00028 /** @addtogroup STM32H7xx_HAL_Driver
00029   * @{
00030   */
00031
00032 #if defined (RNG)
00033
00034 /** @addtogroup RNGEx
00035   * @brief RNG Extended HAL module driver.
00036   * @{
00037   */
00038
00039 #ifdef HAL_RNG_MODULE_ENABLED
00040 #if defined (RNG_CR_CONDRST)
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private defines -----------------------------------------------------------*/
00043 /** @defgroup RNGEx_Private_Defines
00044   * @{
00045   */
00046 /*  Health test control register information to use in CCM algorithm */
00047 #define RNG_HTCFG_1   0x17590ABCU /*!< magic number */
00048 #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
00049 #define RNG_HTCFG     0x000CAA74U /*!< for best latency and To be compliant with NIST */
00050 #else /*RNG_VER_3_2*/
00051 #define RNG_HTCFG     0x00007274U /*!< for best latency and To be compliant with NIST */
00052 #endif
00053 /**
00054   * @}
00055   */
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058 /** @defgroup RNGEx_Private_Constants RNG Private Constants
00059   * @{
00060   */
00061 #define RNG_TIMEOUT_VALUE     2U
00062 /**
00063   * @}
00064   */
00065 /* Private macros ------------------------------------------------------------*/
00066 /* Private functions prototypes ----------------------------------------------*/
00067 /* Private functions ---------------------------------------------------------*/
00068 /* Exported functions --------------------------------------------------------*/
00069
00070 /** @addtogroup RNGEx_Exported_Functions
00071   * @{
00072   */
00073
00074 /** @addtogroup RNGEx_Exported_Functions_Group1
00075  *  @brief   Configuration functions
00076  *
00077 @verbatim
00078  ===============================================================================
00079           ##### Configuration and lock functions #####
00080  ===============================================================================
00081     [..]  This section provides functions allowing to:
00082       (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef
00083       (+) Lock RNG configuration Allows user to lock a configuration until next reset.
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Configure the RNG with the specified parameters in the
00091   *         RNG_ConfigTypeDef.
00092   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00093   *          the configuration information for RNG.
00094   * @param  pConf: pointer to a RNG_ConfigTypeDef structure that contains
00095   *         the configuration information for RNG module
00096
00097   * @retval HAL status
00098 */
00099 HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
00100 {
00101   uint32_t tickstart;
00102   uint32_t cr_value;
00103   HAL_StatusTypeDef status ;
00104
00105   /* Check the RNG handle allocation */
00106   if ((hrng == NULL) || (pConf == NULL))
00107   {
00108     return HAL_ERROR;
00109   }
00110
00111   /* Check the parameters */
00112   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00113   assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider));
00114   assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance));
00115   assert_param(IS_RNG_CONFIG1(pConf->Config1));
00116   assert_param(IS_RNG_CONFIG2(pConf->Config2));
00117   assert_param(IS_RNG_CONFIG3(pConf->Config3));
00118
00119   /* Check RNG peripheral state */
00120   if (hrng->State == HAL_RNG_STATE_READY)
00121   {
00122     /* Change RNG peripheral state */
00123     hrng->State = HAL_RNG_STATE_BUSY;
00124
00125     /* Disable RNG */
00126     __HAL_RNG_DISABLE(hrng);
00127
00128     /* RNG CR register configuration. Set value in CR register for :
00129         - NIST Compliance setting
00130         - Clock divider value
00131         - CONFIG 1, CONFIG 2 and CONFIG 3 values */
00132
00133     cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance
00134                           | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
00135                           | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
00136                           | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
00137
00138     MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
00139                | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
00140                (uint32_t)(RNG_CR_CONDRST | cr_value));
00141
00142 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
00143     /*!< magic number must be written immediately before to RNG_HTCRG */
00144     WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
00145     /* for best latency and to be compliant with NIST */
00146     WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
00147 #endif
00148
00149     /* Writing bits CONDRST=0*/
00150     CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
00151     /* Get tick */
00152     tickstart = HAL_GetTick();
00153
00154     /* Wait for conditioning reset process to be completed */
00155     while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
00156     {
00157       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00158       {
00159         hrng->State = HAL_RNG_STATE_READY;
00160         hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00161         return HAL_ERROR;
00162       }
00163     }
00164
00165     /* Enable RNG */
00166     __HAL_RNG_ENABLE(hrng);
00167
00168     /* Initialize the RNG state */
00169     hrng->State = HAL_RNG_STATE_READY;
00170
00171     /* function status */
00172     status = HAL_OK;
00173   }
00174   else
00175   {
00176     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00177     status = HAL_ERROR;
00178   }
00179
00180   /* Return the function status */
00181   return status;
00182 }
00183
00184 /**
00185   * @brief  Get the RNG Configuration and fill parameters in the
00186   *         RNG_ConfigTypeDef.
00187   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00188   *          the configuration information for RNG.
00189   * @param  pConf: pointer to a RNG_ConfigTypeDef structure that contains
00190   *         the configuration information for RNG module
00191
00192   * @retval HAL status
00193 */
00194 HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
00195 {
00196
00197   HAL_StatusTypeDef status ;
00198
00199   /* Check the RNG handle allocation */
00200   if ((hrng == NULL) || (pConf == NULL))
00201   {
00202     return HAL_ERROR;
00203   }
00204
00205   /* Check RNG peripheral state */
00206   if (hrng->State == HAL_RNG_STATE_READY)
00207   {
00208     /* Change RNG peripheral state */
00209     hrng->State = HAL_RNG_STATE_BUSY;
00210
00211     /* Get  RNG parameters  */
00212     pConf->Config1        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
00213     pConf->Config2        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
00214     pConf->Config3        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
00215     pConf->ClockDivider   = (hrng->Instance->CR & RNG_CR_CLKDIV);
00216     pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC);
00217
00218     /* Initialize the RNG state */
00219     hrng->State = HAL_RNG_STATE_READY;
00220
00221     /* function status */
00222     status = HAL_OK;
00223   }
00224   else
00225   {
00226     hrng->ErrorCode |= HAL_RNG_ERROR_BUSY;
00227     status = HAL_ERROR;
00228   }
00229
00230   /* Return the function status */
00231   return status;
00232 }
00233
00234 /**
00235   * @brief  RNG current configuration lock.
00236   * @note   This function allows to lock RNG peripheral configuration.
00237   *         Once locked, HW RNG reset has to be perfomed prior any further
00238   *         configuration update.
00239   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00240   *                the configuration information for RNG.
00241   * @retval HAL status
00242 */
00243 HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
00244 {
00245   HAL_StatusTypeDef status;
00246
00247   /* Check the RNG handle allocation */
00248   if (hrng == NULL)
00249   {
00250     return HAL_ERROR;
00251   }
00252
00253   /* Check RNG peripheral state */
00254   if (hrng->State == HAL_RNG_STATE_READY)
00255   {
00256     /* Change RNG peripheral state */
00257     hrng->State = HAL_RNG_STATE_BUSY;
00258
00259     /* Perform RNG configuration Lock */
00260     MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK);
00261
00262     /* Change RNG peripheral state */
00263     hrng->State = HAL_RNG_STATE_READY;
00264
00265     /* function status */
00266     status = HAL_OK;
00267   }
00268   else
00269   {
00270     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00271     status = HAL_ERROR;
00272   }
00273
00274   /* Return the function status */
00275   return status;
00276 }
00277
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 #endif  /* CONDRST */
00288 #endif /* HAL_RNG_MODULE_ENABLED */
00289 /**
00290   * @}
00291   */
00292
00293 #endif /* RNG */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rng_ex.h Source File

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stm32h7xx_hal_rng_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RNG_EX_H
00022 #define STM32H7xx_HAL_RNG_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036 #if defined (RNG_CR_CONDRST)
00037
00038 /** @defgroup RNGEx RNGEx
00039   * @brief RNG Extension HAL module driver
00040   * @{
00041   */
00042
00043 /* Exported types ------------------------------------------------------------*/
00044 /** @defgroup RNGEx_Exported_Types RNGEx Exported Types
00045   * @brief RNGEx Exported types
00046   * @{
00047   */
00048
00049 /**
00050   * @brief RNGEX Configuration Structure definition
00051   */
00052
00053 typedef struct
00054 {
00055   uint32_t        Config1;           /*!< Config1 must be a value between 0 and 0x3F */
00056   uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */
00057   uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */
00058   uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can
00059                                           be a value of @ref RNGEX_Clock_Divider_Factor   */
00060   uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a
00061                                           value of @ref RNGEX_NIST_Compliance   */
00062 } RNG_ConfigTypeDef;
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Exported constants --------------------------------------------------------*/
00069 /** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
00070   * @{
00071   */
00072
00073 /** @defgroup RNGEX_Clock_Divider_Factor  Value used to configure an internal
00074  *            programmable divider acting on the incoming RNG clock
00075   * @{
00076   */
00077 #define RNG_CLKDIV_BY_1       (0x00000000UL)      /*!< No clock division  */
00078 #define RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)
00079 /*!< 2 RNG clock cycles per internal RNG clock    */
00080 #define RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)
00081 /*!< 4 RNG clock cycles per internal RNG clock    */
00082 #define RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
00083 /*!< 8 RNG clock cycles per internal RNG clock    */
00084 #define RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)
00085 /*!< 16 RNG clock cycles per internal RNG clock   */
00086 #define RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
00087 /*!< 32 RNG clock cycles per internal RNG clock   */
00088 #define RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
00089 /*!< 64 RNG clock cycles per internal RNG clock   */
00090 #define RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
00091 /*!< 128 RNG clock cycles per internal RNG clock  */
00092 #define RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)
00093 /*!< 256 RNG clock cycles per internal RNG clock  */
00094 #define RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
00095 /*!< 512 RNG clock cycles per internal RNG clock  */
00096 #define RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
00097 /*!< 1024 RNG clock cycles per internal RNG clock */
00098 #define RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
00099 /*!< 2048 RNG clock cycles per internal RNG clock  */
00100 #define RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
00101 /*!< 4096 RNG clock cycles per internal RNG clock  */
00102 #define RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
00103 /*!< 8192 RNG clock cycles per internal RNG clock  */
00104 #define RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
00105 /*!< 16384 RNG clock cycles per internal RNG clock */
00106 #define RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
00107 /*!< 32768 RNG clock cycles per internal RNG clock */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup RNGEX_NIST_Compliance  NIST Compliance configuration
00113   * @{
00114   */
00115 #define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/
00116 #define RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Private types -------------------------------------------------------------*/
00127 /** @defgroup RNGEx_Private_Types RNGEx Private Types
00128   * @{
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /* Private variables ---------------------------------------------------------*/
00136 /** @defgroup RNGEx_Private_Variables RNGEx Private Variables
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Private constants ---------------------------------------------------------*/
00145 /** @defgroup RNGEx_Private_Constants RNGEx Private Constants
00146   * @{
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /* Private macros ------------------------------------------------------------*/
00154 /** @defgroup RNGEx_Private_Macros RNGEx Private Macros
00155   * @{
00156   */
00157
00158 #define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \
00159                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \
00160                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \
00161                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \
00162                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \
00163                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \
00164                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \
00165                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \
00166                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \
00167                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \
00168                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \
00169                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \
00170                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \
00171                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \
00172                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
00173                                              ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
00174
00175
00176 #define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
00177                                                      ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
00178
00179 #define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
00180
00181 #define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
00182
00183 #define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
00184
00185
00186 /**
00187  * @}
00188  */
00189
00190 /* Private functions ---------------------------------------------------------*/
00191 /** @defgroup RNGEx_Private_Functions RNGEx Private Functions
00192   * @{
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported functions --------------------------------------------------------*/
00200 /** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
00201   * @{
00202   */
00203
00204 /** @addtogroup RNGEx_Exported_Functions_Group1
00205   * @{
00206   */
00207 HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
00208 HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
00209 HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /**
00224   * @}
00225   */
00226
00227 #endif  /* CONDRST */
00228 #endif /* RNG */
00229
00230 /**
00231   * @}
00232   */
00233
00234 #ifdef __cplusplus
00235 }
00236 #endif
00237
00238
00239 #endif /* STM32H7xx_HAL_RNGEX_H */
00240
00241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc.c Source File

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stm32h7xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real-Time Clock (RTC) peripheral:
00008   *           + Initialization/de-initialization
00009   *           + Calendar (Time and Date) configuration
00010   *           + Alarms (Alarm A and Alarm B) configuration
00011   *           + WakeUp Timer configuration
00012   *           + TimeStamp configuration
00013   *           + Tampers configuration
00014   *           + Backup Data Registers configuration
00015   *           + RTC Tamper and TimeStamp Pins Selection
00016   *           + Interrupts and flags management
00017   *
00018   @verbatim
00019  ===============================================================================
00020                           ##### RTC Operating Condition #####
00021  ===============================================================================
00022   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00023        from the VBAT voltage when the main VDD supply is powered off.
00024        To retain the content of the RTC backup registers and supply the RTC
00025        when VDD is turned off, VBAT pin can be connected to an optional
00026        standby voltage supplied by a battery or by another source.
00027
00028                    ##### Backup Domain Reset #####
00029  ===============================================================================
00030   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00031        to their reset values.
00032        A backup domain reset is generated when one of the following events occurs:
00033     (#) Software reset, triggered by setting the BDRST bit in the
00034         RCC Backup domain control register (RCC_BDCR).
00035     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00036     (#) Tamper detection event resets all data backup registers.
00037
00038                    ##### Backup Domain Access #####
00039  ===================================================================
00040   [..] After reset, the backup domain (RTC registers, RTC backup data
00041        registers and backup SRAM) is protected against possible unwanted write
00042        accesses.
00043
00044   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00045     (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00046         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
00047     (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00048
00049                   ##### How to use RTC Driver #####
00050  ===================================================================
00051   [..]
00052     (+) Enable the RTC domain access (see description in the section above).
00053     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00054         format using the HAL_RTC_Init() function.
00055
00056   *** Time and Date configuration ***
00057   ===================================
00058   [..]
00059     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00060         and HAL_RTC_SetDate() functions.
00061     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00062
00063   *** Alarm configuration ***
00064   ===========================
00065   [..]
00066     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00067             You can also configure the RTC Alarm with interrupt mode using the
00068             HAL_RTC_SetAlarm_IT() function.
00069     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00070
00071                   ##### RTC and low power modes #####
00072  ===================================================================
00073   [..] The MCU can be woken up from a low power mode by an RTC alternate
00074        function.
00075   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00076        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00077        These RTC alternate functions can wake up the system from the Stop and
00078        Standby low power modes.
00079   [..] The system can also wake up from low power modes without depending
00080        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00081        or the RTC wakeup events.
00082   [..] The RTC provides a programmable time base for waking up from the
00083        Stop or Standby mode at regular intervals.
00084        Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
00085        is LSE or LSI.
00086
00087   *** Callback registration ***
00088   =============================================
00089   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00090   not defined, the callback registration feature is not available and all callbacks
00091   are set to the corresponding weak functions. This is the recommended configuration
00092   in order to optimize memory/code consumption footprint/performances.
00093
00094   The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
00095   allows the user to configure dynamically the driver callbacks.
00096   Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
00097
00098   Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
00099     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00100     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00101     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00102     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00103     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00104     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00105     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00106     (+) MspInitCallback              : RTC MspInit callback.
00107     (+) MspDeInitCallback            : RTC MspDeInit callback.
00108   This function takes as parameters the HAL peripheral handle, the Callback ID
00109   and a pointer to the user callback function.
00110
00111   Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
00112   weak function.
00113   @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00114   and the Callback ID.
00115   This function allows to reset following callbacks:
00116     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00117     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00118     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00119     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00120     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00121     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00122     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00123     (+) MspInitCallback              : RTC MspInit callback.
00124     (+) MspDeInitCallback            : RTC MspDeInit callback.
00125
00126   By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
00127   all callbacks are set to the corresponding weak functions :
00128   examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
00129   Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
00130   in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
00131   (not registered beforehand).
00132   If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
00133   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00134
00135   Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
00136   Exception done MspInit/MspDeInit that can be registered/unregistered
00137   in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
00138   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00139   In that case first register the MspInit/MspDeInit user callbacks
00140   using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
00141   or @ref HAL_RTC_Init() function.
00142
00143   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00144   not defined, the callback registration feature is not available and all callbacks
00145   are set to the corresponding weak functions.
00146    @endverbatim
00147
00148   ******************************************************************************
00149   * @attention
00150   *
00151   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00152   * All rights reserved.</center></h2>
00153   *
00154   * This software component is licensed by ST under BSD 3-Clause license,
00155   * the "License"; You may not use this file except in compliance with the
00156   * License. You may obtain a copy of the License at:
00157   *                        opensource.org/licenses/BSD-3-Clause
00158   *
00159   ******************************************************************************
00160   */
00161
00162 /* Includes ------------------------------------------------------------------*/
00163 #include "stm32h7xx_hal.h"
00164
00165 /** @addtogroup STM32H7xx_HAL_Driver
00166   * @{
00167   */
00168
00169
00170 /** @addtogroup RTC
00171   * @brief RTC HAL module driver
00172   * @{
00173   */
00174
00175 #ifdef HAL_RTC_MODULE_ENABLED
00176
00177 /* Private typedef -----------------------------------------------------------*/
00178 /* Private define ------------------------------------------------------------*/
00179 /* Private macro -------------------------------------------------------------*/
00180 /* Private variables ---------------------------------------------------------*/
00181 /* Private function prototypes -----------------------------------------------*/
00182 /* Exported functions --------------------------------------------------------*/
00183
00184 /** @addtogroup RTC_Exported_Functions
00185   * @{
00186   */
00187
00188 /** @addtogroup RTC_Exported_Functions_Group1
00189  *  @brief    Initialization and Configuration functions
00190  *
00191 @verbatim
00192  ===============================================================================
00193               ##### Initialization and de-initialization functions #####
00194  ===============================================================================
00195    [..] This section provides functions allowing to initialize and configure the
00196          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00197          RTC registers Write protection, enter and exit the RTC initialization mode,
00198          RTC registers synchronization check and reference clock detection enable.
00199          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00200              It is split into 2 programmable prescalers to minimize power consumption.
00201              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00202              (++) When both prescalers are used, it is recommended to configure the
00203                  asynchronous prescaler to a high value to minimize power consumption.
00204          (#) All RTC registers are Write protected. Writing to the RTC registers
00205              is enabled by writing a key into the Write Protection register, RTC_WPR.
00206          (#) To configure the RTC Calendar, user application should enter
00207              initialization mode. In this mode, the calendar counter is stopped
00208              and its value can be updated. When the initialization sequence is
00209              complete, the calendar restarts counting after 4 RTCCLK cycles.
00210          (#) To read the calendar through the shadow registers after Calendar
00211              initialization, calendar update or after wakeup from low power modes
00212              the software must first clear the RSF flag. The software must then
00213              wait until it is set again before reading the calendar, which means
00214              that the calendar registers have been correctly copied into the
00215              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00216              implements the above software sequence (RSF clear and RSF check).
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Initialize the RTC peripheral
00224   * @param  hrtc RTC handle
00225   * @retval HAL status
00226   */
00227 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00228 {
00229   HAL_StatusTypeDef status = HAL_ERROR;
00230
00231   /* Check RTC handler */
00232   if(hrtc != NULL)
00233   {
00234     status = HAL_OK;
00235
00236     /* Check the parameters */
00237     assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00238     assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00239     assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00240     assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00241     assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00242     assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00243     assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00244     assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00245 #if defined(RTC_CR_TAMPALRM_PU)
00246     assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
00247 #endif /* RTC_CR_TAMPALRM_PU */
00248
00249 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00250     if(hrtc->State == HAL_RTC_STATE_RESET)
00251     {
00252       /* Allocate lock resource and initialize it */
00253       hrtc->Lock = HAL_UNLOCKED;
00254
00255       hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;             /* Legacy weak AlarmAEventCallback      */
00256       hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;           /* Legacy weak AlarmBEventCallback      */
00257       hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;        /* Legacy weak TimeStampEventCallback   */
00258       hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback;      /* Legacy weak WakeUpTimerEventCallback */
00259       hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;          /* Legacy weak Tamper1EventCallback     */
00260       hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;          /* Legacy weak Tamper2EventCallback     */
00261       hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;          /* Legacy weak Tamper3EventCallback     */
00262
00263 #if defined(TAMP_CR1_ITAMP1E)
00264       hrtc->InternalTamper1EventCallback =  HAL_RTCEx_InternalTamper1EventCallback;
00265 #endif /* TAMP_CR1_ITAMP1E */
00266 #if defined(TAMP_CR1_ITAMP2E)
00267       hrtc->InternalTamper2EventCallback =  HAL_RTCEx_InternalTamper2EventCallback;
00268 #endif /* TAMP_CR1_ITAMP2E */
00269 #if defined(TAMP_CR1_ITAMP3E)
00270       hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;
00271 #endif /* TAMP_CR1_ITAMP3E */
00272 #if defined(TAMP_CR1_ITAMP4E)
00273       hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;
00274 #endif /* TAMP_CR1_ITAMP4E */
00275 #if defined(TAMP_CR1_ITAMP5E)
00276       hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;
00277 #endif /* TAMP_CR1_ITAMP5E */
00278 #if defined(TAMP_CR1_ITAMP6E)
00279       hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;
00280 #endif /* TAMP_CR1_ITAMP6E */
00281 #if defined(TAMP_CR1_ITAMP8E)
00282       hrtc->InternalTamper8EventCallback =  HAL_RTCEx_InternalTamper8EventCallback;
00283 #endif /* TAMP_CR1_ITAMP8E */
00284
00285
00286       if(hrtc->MspInitCallback == NULL)
00287       {
00288         hrtc->MspInitCallback = HAL_RTC_MspInit;
00289       }
00290       /* Init the low level hardware */
00291       hrtc->MspInitCallback(hrtc);
00292
00293       if(hrtc->MspDeInitCallback == NULL)
00294       {
00295         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00296       }
00297     }
00298 #else /*  (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
00299     if(hrtc->State == HAL_RTC_STATE_RESET)
00300     {
00301       /* Allocate lock resource and initialize it */
00302       hrtc->Lock = HAL_UNLOCKED;
00303
00304       /* Initialize RTC MSP */
00305       HAL_RTC_MspInit(hrtc);
00306     }
00307 #endif /*  (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
00308
00309     /* Set RTC state */
00310     hrtc->State = HAL_RTC_STATE_BUSY;
00311
00312     /* Disable the write protection for RTC registers */
00313     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00314
00315     /* Set Initialization mode */
00316     if(RTC_EnterInitMode(hrtc) != HAL_OK)
00317     {
00318       /* Enable the write protection for RTC registers */
00319       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00320
00321       /* Set RTC state */
00322       hrtc->State = HAL_RTC_STATE_ERROR;
00323
00324       status = HAL_ERROR;
00325     }
00326     else
00327     {
00328 #if defined(RTC_CR_TAMPOE)
00329       /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
00330       hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
00331 #else  /* RTC_CR_TAMPOE */
00332       /* Clear RTC_CR FMT, OSEL and POL Bits */
00333       hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
00334 #endif /* RTC_CR_TAMPOE */
00335
00336       /* Set RTC_CR register */
00337       hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00338
00339       /* Configure the RTC PRER */
00340       hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos);
00341
00342       /* Exit Initialization mode */
00343 #if defined(RTC_ICSR_INIT)
00344       CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
00345 #endif /* RTC_ICSR_INIT */
00346 #if defined(RTC_ISR_INIT)
00347       CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
00348 #endif /* RTC_ISR_INIT */
00349
00350       /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00351       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00352       {
00353         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00354         {
00355           /* Enable the write protection for RTC registers */
00356           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00357
00358           hrtc->State = HAL_RTC_STATE_ERROR;
00359           status = HAL_ERROR;
00360         }
00361       }
00362
00363       if(status == HAL_OK)
00364       {
00365 #if defined(RTC_CR_TAMPALRM_PU) && defined(RTC_CR_TAMPALRM_TYPE) && defined(RTC_CR_OUT2EN)
00366         hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
00367         hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00368 #endif /* RTC_CR_TAMPALRM_TYPE && RTC_CR_OUT2EN && RTC_CR_TAMPALRM_PU */
00369
00370 #if defined(RTC_OR_ALARMOUTTYPE) && defined(RTC_OR_OUT_RMP)
00371         hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
00372         hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00373 #endif /* ALARMOUTTYPE && RTC_OR_OUT_RMP */
00374
00375         /* Enable the write protection for RTC registers */
00376         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00377
00378         /* Set RTC state */
00379         hrtc->State = HAL_RTC_STATE_READY;
00380       }
00381     }
00382   }
00383
00384   /* return status */
00385   return status;
00386 }
00387
00388 /**
00389   * @brief  DeInitialize the RTC peripheral.
00390   * @note   This function doesn't reset the RTC Backup Data registers.
00391   * @param  hrtc RTC handle
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00395 {
00396   HAL_StatusTypeDef status = HAL_ERROR;
00397   uint32_t          tickstart;
00398
00399   /* Check RTC handler */
00400   if(hrtc != NULL)
00401   {
00402     status = HAL_OK;
00403
00404     /* Check the parameters */
00405     assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00406
00407     /* Set RTC state */
00408     hrtc->State = HAL_RTC_STATE_BUSY;
00409
00410     /* Disable the write protection for RTC registers */
00411     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00412
00413     /* Set Initialization mode */
00414     if(RTC_EnterInitMode(hrtc) != HAL_OK)
00415     {
00416       /* Enable the write protection for RTC registers */
00417       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00418
00419       /* Set RTC state */
00420       hrtc->State = HAL_RTC_STATE_ERROR;
00421
00422       status = HAL_ERROR;
00423     }
00424     else
00425     {
00426       /* Reset TR, DR and CR registers */
00427       hrtc->Instance->TR = 0x00000000U;
00428       hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00429       /* Reset All CR bits except CR[2:0] */
00430       hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00431
00432       tickstart = HAL_GetTick();
00433
00434       /* Wait till WUTWF flag is set and if Time out is reached exit */
00435 #if defined(RTC_ICSR_WUTWF)
00436       while (((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U)
00437 #endif /* RTC_ICSR_WUTWF */
00438 #if defined(RTC_ISR_WUTWF)
00439       while (((hrtc->Instance->ISR)  & RTC_ISR_WUTWF)  == 0U)
00440 #endif /* RTC_ISR_WUTWF */
00441         {
00442           if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00443           {
00444             /* Enable the write protection for RTC registers */
00445             __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00446
00447             /* Set RTC state */
00448             hrtc->State = HAL_RTC_STATE_TIMEOUT;
00449
00450             status = HAL_TIMEOUT;
00451           }
00452         }
00453
00454     if(status == HAL_OK)
00455     {
00456       /* Reset all RTC CR register bits */
00457       hrtc->Instance->CR &= 0x00000000U;
00458
00459       /* Reset other RTC registers */
00460       hrtc->Instance->WUTR = RTC_WUTR_WUT;
00461       hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
00462       hrtc->Instance->ALRMAR = 0x00000000U;
00463       hrtc->Instance->ALRMBR = 0x00000000U;
00464       hrtc->Instance->SHIFTR = 0x00000000U;
00465       hrtc->Instance->CALR = 0x00000000U;
00466       hrtc->Instance->ALRMASSR = 0x00000000U;
00467       hrtc->Instance->ALRMBSSR = 0x00000000U;
00468
00469 #if defined(RTC_ICSR_INIT)
00470         /* Exit initialization mode */
00471         CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
00472 #endif /* RTC_ICSR_INIT */
00473 #if defined(RTC_ISR_INIT)
00474         /* Reset ISR register and exit initialization mode */
00475         hrtc->Instance->ISR = 0x00000000U;
00476
00477         /* Reset Tamper configuration register */
00478         hrtc->Instance->TAMPCR = 0x00000000U;
00479
00480         /* Reset Option register */
00481         hrtc->Instance->OR = 0x00000000U;
00482 #endif /* RTC_ISR_INIT */
00483
00484         /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00485         if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00486         {
00487           if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00488           {
00489             /* Enable the write protection for RTC registers */
00490             __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00491
00492             hrtc->State = HAL_RTC_STATE_ERROR;
00493
00494             status = HAL_ERROR;
00495           }
00496         }
00497       }
00498     }
00499
00500     if(status == HAL_OK)
00501     {
00502 #if defined(TAMP_CR1_TAMP1E)
00503       /* Reset TAMP registers */
00504       ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR1 = 0xFFFF0000U;
00505       ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR2 = 0x00000000U;
00506 #endif /* TAMP_CR1_TAMP1E */
00507
00508       /* Enable the write protection for RTC registers */
00509       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00510
00511 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00512       if(hrtc->MspDeInitCallback == NULL)
00513       {
00514         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00515       }
00516
00517       /* DeInit the low level hardware: CLOCK, NVIC.*/
00518       hrtc->MspDeInitCallback(hrtc);
00519 #else
00520       /* De-Initialize RTC MSP */
00521       HAL_RTC_MspDeInit(hrtc);
00522 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00523
00524       hrtc->State = HAL_RTC_STATE_RESET;
00525
00526       /* Release Lock */
00527       __HAL_UNLOCK(hrtc);
00528     }
00529   }
00530
00531   /* return status */
00532   return status;
00533 }
00534
00535 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00536 /**
00537   * @brief  Register a User RTC Callback
00538   *         To be used instead of the weak predefined callback
00539   * @param  hrtc RTC handle
00540   * @param  CallbackID ID of the callback to be registered
00541   *         This parameter can be one of the following values:
00542   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00543   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00544   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00545   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00546   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00547   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00548   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
00549   *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
00550   *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
00551   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00552   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00553   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00554   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00555   *          @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
00556   *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
00557   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
00558   * @param  pCallback pointer to the Callback function
00559   * @retval HAL status
00560   */
00561 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
00562 {
00563   HAL_StatusTypeDef status = HAL_OK;
00564
00565   if(pCallback == NULL)
00566   {
00567     return HAL_ERROR;
00568   }
00569
00570   /* Process locked */
00571   __HAL_LOCK(hrtc);
00572
00573   if(HAL_RTC_STATE_READY == hrtc->State)
00574   {
00575     switch (CallbackID)
00576     {
00577       case HAL_RTC_ALARM_A_EVENT_CB_ID :
00578         hrtc->AlarmAEventCallback = pCallback;
00579         break;
00580
00581       case HAL_RTC_ALARM_B_EVENT_CB_ID :
00582         hrtc->AlarmBEventCallback = pCallback;
00583         break;
00584
00585       case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00586         hrtc->TimeStampEventCallback = pCallback;
00587         break;
00588
00589       case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00590         hrtc->WakeUpTimerEventCallback = pCallback;
00591         break;
00592
00593       case HAL_RTC_TAMPER1_EVENT_CB_ID :
00594         hrtc->Tamper1EventCallback = pCallback;
00595         break;
00596
00597       case HAL_RTC_TAMPER2_EVENT_CB_ID :
00598         hrtc->Tamper2EventCallback = pCallback;
00599         break;
00600
00601       case HAL_RTC_TAMPER3_EVENT_CB_ID :
00602         hrtc->Tamper3EventCallback = pCallback;
00603         break;
00604
00605 #if defined(TAMP_CR1_ITAMP1E)
00606       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
00607         hrtc->InternalTamper1EventCallback =  pCallback;
00608         break;
00609 #endif /* TAMP_CR1_ITAMP1E */
00610
00611 #if defined(TAMP_CR1_ITAMP2E)
00612       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
00613         hrtc->InternalTamper2EventCallback =  pCallback;
00614         break;
00615 #endif /* TAMP_CR1_ITAMP2E */
00616
00617 #if defined(TAMP_CR1_ITAMP3E)
00618       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00619         hrtc->InternalTamper3EventCallback =  pCallback;
00620         break;
00621 #endif /* TAMP_CR1_ITAMP3E */
00622
00623 #if defined(TAMP_CR1_ITAMP4E)
00624       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00625         hrtc->InternalTamper4EventCallback =  pCallback;
00626         break;
00627 #endif /* TAMP_CR1_ITAMP4E */
00628
00629 #if defined(TAMP_CR1_ITAMP5E)
00630       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00631         hrtc->InternalTamper5EventCallback =  pCallback;
00632         break;
00633 #endif /* TAMP_CR1_ITAMP5E */
00634
00635 #if defined(TAMP_CR1_ITAMP6E)
00636       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00637         hrtc->InternalTamper6EventCallback =  pCallback;
00638         break;
00639 #endif /* TAMP_CR1_ITAMP6E */
00640
00641 #if defined(TAMP_CR1_ITAMP8E)
00642       case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
00643         hrtc->InternalTamper8EventCallback =  pCallback;
00644         break;
00645 #endif /* TAMP_CR1_ITAMP8E */
00646
00647       case HAL_RTC_MSPINIT_CB_ID :
00648         hrtc->MspInitCallback = pCallback;
00649         break;
00650
00651       case HAL_RTC_MSPDEINIT_CB_ID :
00652         hrtc->MspDeInitCallback = pCallback;
00653         break;
00654
00655       default :
00656         /* Return error status */
00657         status =  HAL_ERROR;
00658         break;
00659     }
00660   }
00661   else if(HAL_RTC_STATE_RESET == hrtc->State)
00662   {
00663     switch (CallbackID)
00664     {
00665       case HAL_RTC_MSPINIT_CB_ID :
00666         hrtc->MspInitCallback = pCallback;
00667         break;
00668
00669       case HAL_RTC_MSPDEINIT_CB_ID :
00670         hrtc->MspDeInitCallback = pCallback;
00671         break;
00672
00673       default :
00674         /* Return error status */
00675         status =  HAL_ERROR;
00676         break;
00677     }
00678   }
00679   else
00680   {
00681     /* Return error status */
00682     status =  HAL_ERROR;
00683   }
00684
00685   /* Release Lock */
00686   __HAL_UNLOCK(hrtc);
00687
00688   return status;
00689 }
00690
00691 /**
00692   * @brief  Unregister an RTC Callback
00693   *         RTC callabck is redirected to the weak predefined callback
00694   * @param  hrtc RTC handle
00695   * @param  CallbackID ID of the callback to be unregistered
00696   *         This parameter can be one of the following values:
00697   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00698   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00699   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00700   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00701   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00702   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00703   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
00704   *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
00705   *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
00706   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00707   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00708   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00709   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00710   *          @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
00711   *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
00712   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
00713   * @retval HAL status
00714   */
00715 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
00716 {
00717   HAL_StatusTypeDef status = HAL_OK;
00718
00719   /* Process locked */
00720   __HAL_LOCK(hrtc);
00721
00722   if(HAL_RTC_STATE_READY == hrtc->State)
00723   {
00724     switch (CallbackID)
00725     {
00726       case HAL_RTC_ALARM_A_EVENT_CB_ID :
00727         hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;             /* Legacy weak AlarmAEventCallback    */
00728         break;
00729
00730       case HAL_RTC_ALARM_B_EVENT_CB_ID :
00731         hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;           /* Legacy weak AlarmBEventCallback */
00732         break;
00733
00734       case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00735         hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;     /* Legacy weak TimeStampEventCallback    */
00736         break;
00737
00738       case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00739         hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00740         break;
00741
00742       case HAL_RTC_TAMPER1_EVENT_CB_ID :
00743         hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
00744         break;
00745
00746       case HAL_RTC_TAMPER2_EVENT_CB_ID :
00747         hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
00748         break;
00749
00750       case HAL_RTC_TAMPER3_EVENT_CB_ID :
00751         hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
00752         break;
00753
00754 #if defined(TAMP_CR1_ITAMP1E)
00755       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
00756         hrtc->InternalTamper1EventCallback =  HAL_RTCEx_InternalTamper1EventCallback;
00757         break;
00758 #endif /* TAMP_CR1_ITAMP1E */
00759
00760 #if defined(TAMP_CR1_ITAMP2E)
00761       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
00762         hrtc->InternalTamper2EventCallback =  HAL_RTCEx_InternalTamper2EventCallback;
00763         break;
00764 #endif /* TAMP_CR1_ITAMP2E */
00765
00766 #if defined(TAMP_CR1_ITAMP3E)
00767       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00768         hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;
00769         break;
00770 #endif /* TAMP_CR1_ITAMP3E */
00771
00772 #if defined(TAMP_CR1_ITAMP4E)
00773       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00774         hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;
00775         break;
00776 #endif /* TAMP_CR1_ITAMP4E */
00777
00778 #if defined(TAMP_CR1_ITAMP5E)
00779       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00780         hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;
00781         break;
00782 #endif /* TAMP_CR1_ITAMP5E */
00783
00784 #if defined(TAMP_CR1_ITAMP6E)
00785       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00786         hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;
00787         break;
00788 #endif /* TAMP_CR1_ITAMP6E */
00789
00790 #if defined(TAMP_CR1_ITAMP8E)
00791       case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
00792         hrtc->InternalTamper8EventCallback =  HAL_RTCEx_InternalTamper8EventCallback;
00793         break;
00794 #endif /* TAMP_CR1_ITAMP8E */
00795
00796       case HAL_RTC_MSPINIT_CB_ID :
00797         hrtc->MspInitCallback = HAL_RTC_MspInit;
00798         break;
00799
00800       case HAL_RTC_MSPDEINIT_CB_ID :
00801         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00802         break;
00803
00804       default :
00805         /* Return error status */
00806         status =  HAL_ERROR;
00807         break;
00808     }
00809   }
00810   else if(HAL_RTC_STATE_RESET == hrtc->State)
00811   {
00812     switch (CallbackID)
00813     {
00814       case HAL_RTC_MSPINIT_CB_ID :
00815         hrtc->MspInitCallback = HAL_RTC_MspInit;
00816         break;
00817
00818       case HAL_RTC_MSPDEINIT_CB_ID :
00819         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00820         break;
00821
00822       default :
00823         /* Return error status */
00824         status =  HAL_ERROR;
00825         break;
00826     }
00827   }
00828   else
00829   {
00830     /* Return error status */
00831     status =  HAL_ERROR;
00832   }
00833
00834   /* Release Lock */
00835   __HAL_UNLOCK(hrtc);
00836
00837   return status;
00838 }
00839 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00840
00841 /**
00842   * @brief  Initialize the RTC MSP.
00843   * @param  hrtc RTC handle
00844   * @retval None
00845   */
00846 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
00847 {
00848   /* Prevent unused argument(s) compilation warning */
00849   UNUSED(hrtc);
00850
00851   /* NOTE : This function should not be modified, when the callback is needed,
00852             the HAL_RTC_MspInit could be implemented in the user file
00853    */
00854 }
00855
00856 /**
00857   * @brief  DeInitialize the RTC MSP.
00858   * @param  hrtc RTC handle
00859   * @retval None
00860   */
00861 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
00862 {
00863   /* Prevent unused argument(s) compilation warning */
00864   UNUSED(hrtc);
00865
00866   /* NOTE : This function should not be modified, when the callback is needed,
00867             the HAL_RTC_MspDeInit could be implemented in the user file
00868    */
00869 }
00870
00871 /**
00872   * @}
00873   */
00874
00875 /** @addtogroup RTC_Exported_Functions_Group2
00876  *  @brief   RTC Time and Date functions
00877  *
00878 @verbatim
00879  ===============================================================================
00880                  ##### RTC Time and Date functions #####
00881  ===============================================================================
00882
00883  [..] This section provides functions allowing to configure Time and Date features
00884
00885 @endverbatim
00886   * @{
00887   */
00888
00889 /**
00890   * @brief  Set RTC current time.
00891   * @param  hrtc RTC handle
00892   * @param  sTime Pointer to Time structure
00893   * @param  Format Specifies the format of the entered parameters.
00894   *          This parameter can be one of the following values:
00895   *            @arg RTC_FORMAT_BIN: Binary data format
00896   *            @arg RTC_FORMAT_BCD: BCD data format
00897   * @retval HAL status
00898   */
00899 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00900 {
00901   uint32_t tmpreg;
00902
00903   /* Check the parameters */
00904   assert_param(IS_RTC_FORMAT(Format));
00905   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00906   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00907
00908   /* Process Locked */
00909   __HAL_LOCK(hrtc);
00910
00911   hrtc->State = HAL_RTC_STATE_BUSY;
00912
00913   /* Disable the write protection for RTC registers */
00914   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00915
00916   /* Set Initialization mode */
00917   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00918   {
00919     /* Enable the write protection for RTC registers */
00920     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00921
00922     /* Set RTC state */
00923     hrtc->State = HAL_RTC_STATE_ERROR;
00924
00925     /* Process Unlocked */
00926     __HAL_UNLOCK(hrtc);
00927
00928     return HAL_ERROR;
00929   }
00930   else
00931   {
00932     if(Format == RTC_FORMAT_BIN)
00933     {
00934       if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00935       {
00936         assert_param(IS_RTC_HOUR12(sTime->Hours));
00937         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00938       }
00939       else
00940       {
00941         sTime->TimeFormat = 0x00U;
00942         assert_param(IS_RTC_HOUR24(sTime->Hours));
00943       }
00944       assert_param(IS_RTC_MINUTES(sTime->Minutes));
00945       assert_param(IS_RTC_SECONDS(sTime->Seconds));
00946
00947       tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours)   << RTC_TR_HU_Pos)  | \
00948                           ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00949                           ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos)  | \
00950                           (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
00951     }
00952     else
00953     {
00954       if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00955       {
00956         assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
00957         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00958       }
00959       else
00960       {
00961         sTime->TimeFormat = 0x00U;
00962         assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00963       }
00964       assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00965       assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00966       tmpreg = (((uint32_t)(sTime->Hours)   << RTC_TR_HU_Pos)  | \
00967                 ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00968                 ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos)  | \
00969                 ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
00970     }
00971
00972     /* Set the RTC_TR register */
00973     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00974
00975     /* Clear the bits to be configured */
00976     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
00977
00978     /* Configure the RTC_CR register */
00979     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00980
00981     /* Exit Initialization mode */
00982 #if defined(RTC_ICSR_INIT)
00983     CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
00984 #endif /* RTC_ICSR_INIT */
00985 #if defined(RTC_ISR_INIT)
00986     CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
00987 #endif /* RTC_ISR_INIT */
00988
00989     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00990     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00991     {
00992       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00993       {
00994         /* Enable the write protection for RTC registers */
00995         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00996
00997         hrtc->State = HAL_RTC_STATE_ERROR;
00998
00999         /* Process Unlocked */
01000         __HAL_UNLOCK(hrtc);
01001
01002         return HAL_ERROR;
01003       }
01004     }
01005
01006     /* Enable the write protection for RTC registers */
01007     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01008
01009     hrtc->State = HAL_RTC_STATE_READY;
01010
01011     __HAL_UNLOCK(hrtc);
01012
01013     return HAL_OK;
01014   }
01015 }
01016
01017 /**
01018   * @brief  Get RTC current time.
01019   * @param  hrtc RTC handle
01020   * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
01021   *                with input format (BIN or BCD), also SubSeconds field returning the
01022   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
01023   *                factor to be used for second fraction ratio computation.
01024   * @param  Format Specifies the format of the entered parameters.
01025   *          This parameter can be one of the following values:
01026   *            @arg RTC_FORMAT_BIN: Binary data format
01027   *            @arg RTC_FORMAT_BCD: BCD data format
01028   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
01029   *        value in second fraction ratio with time unit following generic formula:
01030   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01031   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
01032   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
01033   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
01034   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
01035   *        to ensure consistency between the time and date values.
01036   * @retval HAL status
01037   */
01038 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
01039 {
01040   uint32_t tmpreg;
01041
01042   /* Check the parameters */
01043   assert_param(IS_RTC_FORMAT(Format));
01044
01045   /* Get subseconds structure field from the corresponding register*/
01046   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
01047
01048   /* Get SecondFraction structure field from the corresponding register field*/
01049   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
01050
01051   /* Get the TR register */
01052   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
01053
01054   /* Fill the structure fields with the read parameters */
01055   sTime->Hours      = (uint8_t)((tmpreg & (RTC_TR_HT  | RTC_TR_HU))  >> RTC_TR_HU_Pos);
01056   sTime->Minutes    = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
01057   sTime->Seconds    = (uint8_t)((tmpreg & (RTC_TR_ST  | RTC_TR_SU))  >> RTC_TR_SU_Pos);
01058   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM))               >> RTC_TR_PM_Pos);
01059
01060   /* Check the input parameters format */
01061   if(Format == RTC_FORMAT_BIN)
01062   {
01063     /* Convert the time structure parameters to Binary format */
01064     sTime->Hours   = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
01065     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
01066     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
01067   }
01068
01069   return HAL_OK;
01070 }
01071
01072 /**
01073   * @brief  Set RTC current date.
01074   * @param  hrtc RTC handle
01075   * @param  sDate Pointer to date structure
01076   * @param  Format specifies the format of the entered parameters.
01077   *          This parameter can be one of the following values:
01078   *            @arg RTC_FORMAT_BIN: Binary data format
01079   *            @arg RTC_FORMAT_BCD: BCD data format
01080   * @retval HAL status
01081   */
01082 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
01083 {
01084   uint32_t datetmpreg;
01085
01086   /* Check the parameters */
01087   assert_param(IS_RTC_FORMAT(Format));
01088
01089   /* Process Locked */
01090   __HAL_LOCK(hrtc);
01091
01092   hrtc->State = HAL_RTC_STATE_BUSY;
01093
01094   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
01095   {
01096     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
01097   }
01098
01099   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
01100
01101   if(Format == RTC_FORMAT_BIN)
01102   {
01103     assert_param(IS_RTC_YEAR(sDate->Year));
01104     assert_param(IS_RTC_MONTH(sDate->Month));
01105     assert_param(IS_RTC_DATE(sDate->Date));
01106
01107     datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year)  << RTC_DR_YU_Pos) | \
01108                   ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
01109                   ((uint32_t)RTC_ByteToBcd2(sDate->Date)  << RTC_DR_DU_Pos) | \
01110                   ((uint32_t)sDate->WeekDay               << RTC_DR_WDU_Pos));
01111   }
01112   else
01113   {
01114     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
01115     assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
01116     assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
01117
01118     datetmpreg = ((((uint32_t)sDate->Year)    << RTC_DR_YU_Pos) | \
01119                   (((uint32_t)sDate->Month)   << RTC_DR_MU_Pos) | \
01120                   (((uint32_t)sDate->Date)    << RTC_DR_DU_Pos) | \
01121                   (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
01122   }
01123
01124   /* Disable the write protection for RTC registers */
01125   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01126
01127   /* Set Initialization mode */
01128   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01129   {
01130     /* Enable the write protection for RTC registers */
01131     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01132
01133     /* Set RTC state*/
01134     hrtc->State = HAL_RTC_STATE_ERROR;
01135
01136     /* Process Unlocked */
01137     __HAL_UNLOCK(hrtc);
01138
01139     return HAL_ERROR;
01140   }
01141   else
01142   {
01143     /* Set the RTC_DR register */
01144     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
01145
01146     /* Exit Initialization mode */
01147 #if defined(RTC_ICSR_INIT)
01148     CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
01149 #endif /* RTC_ISR_INIT */
01150 #if defined(RTC_ISR_INIT)
01151     CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
01152 #endif /* RTC_ISR_INIT */
01153
01154     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01155     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
01156     {
01157       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01158       {
01159         /* Enable the write protection for RTC registers */
01160         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01161
01162         hrtc->State = HAL_RTC_STATE_ERROR;
01163
01164         /* Process Unlocked */
01165         __HAL_UNLOCK(hrtc);
01166
01167         return HAL_ERROR;
01168       }
01169     }
01170
01171     /* Enable the write protection for RTC registers */
01172     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01173
01174     hrtc->State = HAL_RTC_STATE_READY ;
01175
01176     /* Process Unlocked */
01177     __HAL_UNLOCK(hrtc);
01178
01179     return HAL_OK;
01180   }
01181 }
01182
01183 /**
01184   * @brief  Get RTC current date.
01185   * @param  hrtc RTC handle
01186   * @param  sDate Pointer to Date structure
01187   * @param  Format Specifies the format of the entered parameters.
01188   *          This parameter can be one of the following values:
01189   *            @arg RTC_FORMAT_BIN:  Binary data format
01190   *            @arg RTC_FORMAT_BCD:  BCD data format
01191   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
01192   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
01193   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
01194   * @retval HAL status
01195   */
01196 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
01197 {
01198   uint32_t datetmpreg;
01199
01200   /* Check the parameters */
01201   assert_param(IS_RTC_FORMAT(Format));
01202
01203   /* Get the DR register */
01204   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
01205
01206   /* Fill the structure fields with the read parameters */
01207   sDate->Year    = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
01208   sDate->Month   = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
01209   sDate->Date    = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
01210   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU))            >> RTC_DR_WDU_Pos);
01211
01212   /* Check the input parameters format */
01213   if(Format == RTC_FORMAT_BIN)
01214   {
01215     /* Convert the date structure parameters to Binary format */
01216     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
01217     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
01218     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
01219   }
01220   return HAL_OK;
01221 }
01222
01223 /**
01224   * @}
01225   */
01226
01227 /** @addtogroup RTC_Exported_Functions_Group3
01228  *  @brief   RTC Alarm functions
01229  *
01230 @verbatim
01231  ===============================================================================
01232                  ##### RTC Alarm functions #####
01233  ===============================================================================
01234
01235  [..] This section provides functions allowing to configure Alarm feature
01236
01237 @endverbatim
01238   * @{
01239   */
01240 /**
01241   * @brief  Set the specified RTC Alarm.
01242   * @param  hrtc RTC handle
01243   * @param  sAlarm Pointer to Alarm structure
01244   * @param  Format Specifies the format of the entered parameters.
01245   *          This parameter can be one of the following values:
01246   *             @arg RTC_FORMAT_BIN: Binary data format
01247   *             @arg RTC_FORMAT_BCD: BCD data format
01248   * @retval HAL status
01249   */
01250 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01251 {
01252   uint32_t tickstart;
01253   uint32_t tmpreg;
01254   uint32_t subsecondtmpreg;
01255
01256   /* Check the parameters */
01257   assert_param(IS_RTC_FORMAT(Format));
01258   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01259   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01260   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01261   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01262   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01263
01264   /* Process Locked */
01265   __HAL_LOCK(hrtc);
01266
01267   hrtc->State = HAL_RTC_STATE_BUSY;
01268
01269   if(Format == RTC_FORMAT_BIN)
01270   {
01271     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01272     {
01273       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01274       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01275     }
01276     else
01277     {
01278       sAlarm->AlarmTime.TimeFormat = 0x00U;
01279       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01280     }
01281     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01282     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01283
01284     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01285     {
01286       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01287     }
01288     else
01289     {
01290       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01291     }
01292
01293     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours)   << RTC_ALRMAR_HU_Pos)  | \
01294               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01295               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos)  | \
01296               ((uint32_t)sAlarm->AlarmTime.TimeFormat              << RTC_ALRMAR_PM_Pos)  | \
01297               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay)  << RTC_ALRMAR_DU_Pos)  | \
01298               ((uint32_t)sAlarm->AlarmDateWeekDaySel)                                     | \
01299               ((uint32_t)sAlarm->AlarmMask));
01300   }
01301   else
01302   {
01303     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01304     {
01305       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01306       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01307     }
01308     else
01309     {
01310       sAlarm->AlarmTime.TimeFormat = 0x00U;
01311       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01312     }
01313
01314     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01315     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01316
01317     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01318     {
01319       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01320     }
01321     else
01322     {
01323       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01324     }
01325
01326     tmpreg = (((uint32_t)sAlarm->AlarmTime.Hours       << RTC_ALRMAR_HU_Pos)  | \
01327               ((uint32_t)sAlarm->AlarmTime.Minutes     << RTC_ALRMAR_MNU_Pos) | \
01328               ((uint32_t)sAlarm->AlarmTime.Seconds     << RTC_ALRMAR_SU_Pos)  | \
01329               ((uint32_t)sAlarm->AlarmTime.TimeFormat  << RTC_ALRMAR_PM_Pos)  | \
01330               ((uint32_t)sAlarm->AlarmDateWeekDay      << RTC_ALRMAR_DU_Pos)  | \
01331               ((uint32_t)sAlarm->AlarmDateWeekDaySel)                         | \
01332               ((uint32_t)sAlarm->AlarmMask));
01333   }
01334
01335   /* Configure the Alarm A or Alarm B Sub Second registers */
01336   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01337
01338   /* Disable the write protection for RTC registers */
01339   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01340
01341   /* Configure the Alarm register */
01342   if(sAlarm->Alarm == RTC_ALARM_A)
01343   {
01344     /* Disable the Alarm A interrupt */
01345     __HAL_RTC_ALARMA_DISABLE(hrtc);
01346     /* Clear flag alarm A */
01347     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01348     /* In case of interrupt mode is used, the interrupt source must disabled */
01349     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01350
01351     tickstart = HAL_GetTick();
01352     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01353   #if defined(RTC_ICSR_ALRAWF)
01354     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
01355   #endif /* RTC_ICSR_ALRAWF */
01356   #if defined(RTC_ISR_ALRAWF)
01357     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01358   #endif /* RTC_ISR_ALRAWF */
01359     {
01360       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01361       {
01362         /* Enable the write protection for RTC registers */
01363         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01364
01365         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01366
01367         /* Process Unlocked */
01368         __HAL_UNLOCK(hrtc);
01369
01370         return HAL_TIMEOUT;
01371       }
01372     }
01373
01374     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01375     /* Configure the Alarm A Sub Second register */
01376     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01377     /* Configure the Alarm state: Enable Alarm */
01378     __HAL_RTC_ALARMA_ENABLE(hrtc);
01379   }
01380   else
01381   {
01382     /* Disable the Alarm B interrupt */
01383     __HAL_RTC_ALARMB_DISABLE(hrtc);
01384     /* Clear flag alarm B */
01385     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01386     /* In case of interrupt mode is used, the interrupt source must disabled */
01387     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
01388
01389     tickstart = HAL_GetTick();
01390     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01391   #if defined(RTC_ICSR_ALRBWF)
01392     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
01393   #endif /* RTC_ICSR_ALRBWF */
01394   #if defined(RTC_ISR_ALRBWF)
01395     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01396   #endif /* RTC_ISR_ALRBWF */
01397     {
01398       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01399       {
01400         /* Enable the write protection for RTC registers */
01401         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01402
01403         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01404
01405         /* Process Unlocked */
01406         __HAL_UNLOCK(hrtc);
01407
01408         return HAL_TIMEOUT;
01409       }
01410     }
01411
01412     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01413     /* Configure the Alarm B Sub Second register */
01414     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01415     /* Configure the Alarm state: Enable Alarm */
01416     __HAL_RTC_ALARMB_ENABLE(hrtc);
01417   }
01418
01419   /* Enable the write protection for RTC registers */
01420   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01421
01422   /* Change RTC state */
01423   hrtc->State = HAL_RTC_STATE_READY;
01424
01425   /* Process Unlocked */
01426   __HAL_UNLOCK(hrtc);
01427
01428   return HAL_OK;
01429 }
01430
01431 /**
01432   * @brief  Set the specified RTC Alarm with Interrupt.
01433   * @param  hrtc RTC handle
01434   * @param  sAlarm Pointer to Alarm structure
01435   * @param  Format Specifies the format of the entered parameters.
01436   *          This parameter can be one of the following values:
01437   *             @arg RTC_FORMAT_BIN: Binary data format
01438   *             @arg RTC_FORMAT_BCD: BCD data format
01439   * @note   The Alarm register can only be written when the corresponding Alarm
01440   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
01441   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
01442   * @retval HAL status
01443   */
01444 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01445 {
01446   uint32_t tickstart;
01447   uint32_t tmpreg;
01448   uint32_t subsecondtmpreg;
01449
01450   /* Check the parameters */
01451   assert_param(IS_RTC_FORMAT(Format));
01452   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01453   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01454   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01455   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01456   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01457
01458   /* Process Locked */
01459   __HAL_LOCK(hrtc);
01460
01461   hrtc->State = HAL_RTC_STATE_BUSY;
01462
01463   if(Format == RTC_FORMAT_BIN)
01464   {
01465     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01466     {
01467       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01468       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01469     }
01470     else
01471     {
01472       sAlarm->AlarmTime.TimeFormat = 0x00U;
01473       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01474     }
01475     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01476     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01477
01478     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01479     {
01480       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01481     }
01482     else
01483     {
01484       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01485     }
01486
01487     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours)   << RTC_ALRMAR_HU_Pos)  | \
01488               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01489               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos)  | \
01490               ((uint32_t)sAlarm->AlarmTime.TimeFormat              << RTC_ALRMAR_PM_Pos)  | \
01491               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay)  << RTC_ALRMAR_DU_Pos)  | \
01492               ((uint32_t)sAlarm->AlarmDateWeekDaySel)                                     | \
01493               ((uint32_t)sAlarm->AlarmMask));
01494   }
01495   else
01496   {
01497     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01498     {
01499       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01500       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01501     }
01502     else
01503     {
01504       sAlarm->AlarmTime.TimeFormat = 0x00U;
01505       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01506     }
01507
01508     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01509     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01510
01511     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01512     {
01513       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01514     }
01515     else
01516     {
01517       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01518     }
01519
01520     tmpreg = (((uint32_t)sAlarm->AlarmTime.Hours       << RTC_ALRMAR_HU_Pos)  | \
01521               ((uint32_t)sAlarm->AlarmTime.Minutes     << RTC_ALRMAR_MNU_Pos) | \
01522               ((uint32_t)sAlarm->AlarmTime.Seconds     << RTC_ALRMAR_SU_Pos)  | \
01523               ((uint32_t)sAlarm->AlarmTime.TimeFormat  << RTC_ALRMAR_PM_Pos)  | \
01524               ((uint32_t)sAlarm->AlarmDateWeekDay      << RTC_ALRMAR_DU_Pos)  | \
01525               ((uint32_t)sAlarm->AlarmDateWeekDaySel)                         | \
01526               ((uint32_t)sAlarm->AlarmMask));
01527   }
01528   /* Configure the Alarm A or Alarm B Sub Second registers */
01529   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01530
01531   /* Disable the write protection for RTC registers */
01532   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01533
01534   /* Configure the Alarm register */
01535   if(sAlarm->Alarm == RTC_ALARM_A)
01536   {
01537     /* Disable the Alarm A interrupt */
01538     __HAL_RTC_ALARMA_DISABLE(hrtc);
01539
01540     /* Clear flag alarm A */
01541     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01542
01543     tickstart = HAL_GetTick();
01544     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01545   #if defined(RTC_ICSR_ALRAWF)
01546     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
01547   #endif /* RTC_ICSR_ALRAWF */
01548   #if defined(RTC_ISR_ALRAWF)
01549     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01550   #endif /* RTC_ISR_ALRAWF */
01551     {
01552       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01553       {
01554         /* Enable the write protection for RTC registers */
01555         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01556
01557         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01558
01559         /* Process Unlocked */
01560         __HAL_UNLOCK(hrtc);
01561
01562         return HAL_TIMEOUT;
01563       }
01564     }
01565
01566     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01567     /* Configure the Alarm A Sub Second register */
01568     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01569     /* Configure the Alarm state: Enable Alarm */
01570     __HAL_RTC_ALARMA_ENABLE(hrtc);
01571     /* Configure the Alarm interrupt */
01572     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
01573   }
01574   else
01575   {
01576     /* Disable the Alarm B interrupt */
01577     __HAL_RTC_ALARMB_DISABLE(hrtc);
01578
01579     /* Clear flag alarm B */
01580     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01581
01582     tickstart = HAL_GetTick();
01583     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01584 #if defined(RTC_ICSR_ALRBWF)
01585     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
01586 #endif /* RTC_ICSR_ALRBWF */
01587 #if defined(RTC_ISR_ALRBWF)
01588     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01589 #endif /* RTC_ISR_ALRBWF */
01590     {
01591       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01592       {
01593         /* Enable the write protection for RTC registers */
01594         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01595
01596         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01597
01598         /* Process Unlocked */
01599         __HAL_UNLOCK(hrtc);
01600
01601         return HAL_TIMEOUT;
01602       }
01603     }
01604
01605     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01606     /* Configure the Alarm B Sub Second register */
01607     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01608     /* Configure the Alarm state: Enable Alarm */
01609     __HAL_RTC_ALARMB_ENABLE(hrtc);
01610     /* Configure the Alarm interrupt */
01611     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01612   }
01613
01614 #if !defined(DUAL_CORE)
01615   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01616   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01617 #endif
01618
01619   __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01620
01621   /* Enable the write protection for RTC registers */
01622   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01623
01624   hrtc->State = HAL_RTC_STATE_READY;
01625
01626   /* Process Unlocked */
01627   __HAL_UNLOCK(hrtc);
01628
01629   return HAL_OK;
01630 }
01631
01632 /**
01633   * @brief  Deactivate the specified RTC Alarm.
01634   * @param  hrtc RTC handle
01635   * @param  Alarm Specifies the Alarm.
01636   *          This parameter can be one of the following values:
01637   *            @arg RTC_ALARM_A:  AlarmA
01638   *            @arg RTC_ALARM_B:  AlarmB
01639   * @retval HAL status
01640   */
01641 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01642 {
01643   uint32_t tickstart;
01644
01645   /* Check the parameters */
01646   assert_param(IS_RTC_ALARM(Alarm));
01647
01648   /* Process Locked */
01649   __HAL_LOCK(hrtc);
01650
01651   hrtc->State = HAL_RTC_STATE_BUSY;
01652
01653   /* Disable the write protection for RTC registers */
01654   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01655
01656   if(Alarm == RTC_ALARM_A)
01657   {
01658     /* AlarmA */
01659     __HAL_RTC_ALARMA_DISABLE(hrtc);
01660
01661     /* In case of interrupt mode is used, the interrupt source must disabled */
01662     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01663
01664     tickstart = HAL_GetTick();
01665
01666     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01667 #if defined(RTC_ICSR_ALRAWF)
01668     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
01669 #endif /* RTC_ICSR_ALRAWF */
01670 #if defined(RTC_ISR_ALRAWF)
01671     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01672 #endif /* RTC_ISR_ALRAWF */
01673     {
01674       if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
01675       {
01676         /* Enable the write protection for RTC registers */
01677         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01678
01679         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01680
01681         /* Process Unlocked */
01682         __HAL_UNLOCK(hrtc);
01683
01684         return HAL_TIMEOUT;
01685       }
01686     }
01687   }
01688   else
01689   {
01690     /* AlarmB */
01691     __HAL_RTC_ALARMB_DISABLE(hrtc);
01692
01693     /* In case of interrupt mode is used, the interrupt source must disabled */
01694     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
01695
01696     tickstart = HAL_GetTick();
01697
01698     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01699 #if defined(RTC_ICSR_ALRBWF)
01700     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
01701 #endif /* RTC_ICSR_ALRBWF */
01702 #if defined(RTC_ISR_ALRBWF)
01703     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01704 #endif /* RTC_ISR_ALRBWF */
01705     {
01706       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01707       {
01708         /* Enable the write protection for RTC registers */
01709         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01710
01711         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01712
01713         /* Process Unlocked */
01714         __HAL_UNLOCK(hrtc);
01715
01716         return HAL_TIMEOUT;
01717       }
01718     }
01719   }
01720   /* Enable the write protection for RTC registers */
01721   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01722
01723   hrtc->State = HAL_RTC_STATE_READY;
01724
01725   /* Process Unlocked */
01726   __HAL_UNLOCK(hrtc);
01727
01728   return HAL_OK;
01729 }
01730
01731 /**
01732   * @brief  Get the RTC Alarm value and masks.
01733   * @param  hrtc RTC handle
01734   * @param  sAlarm Pointer to Date structure
01735   * @param  Alarm Specifies the Alarm.
01736   *          This parameter can be one of the following values:
01737   *             @arg RTC_ALARM_A: AlarmA
01738   *             @arg RTC_ALARM_B: AlarmB
01739   * @param  Format Specifies the format of the entered parameters.
01740   *          This parameter can be one of the following values:
01741   *             @arg RTC_FORMAT_BIN: Binary data format
01742   *             @arg RTC_FORMAT_BCD: BCD data format
01743   * @retval HAL status
01744   */
01745 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01746 {
01747   uint32_t tmpreg;
01748   uint32_t subsecondtmpreg;
01749
01750   /* Check the parameters */
01751   assert_param(IS_RTC_FORMAT(Format));
01752   assert_param(IS_RTC_ALARM(Alarm));
01753
01754   if(Alarm == RTC_ALARM_A)
01755   {
01756     /* AlarmA */
01757     sAlarm->Alarm = RTC_ALARM_A;
01758
01759     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01760     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
01761
01762     /* Fill the structure with the read parameters */
01763     sAlarm->AlarmTime.Hours      = (uint8_t)((tmpreg & (RTC_ALRMAR_HT  | RTC_ALRMAR_HU))  >> RTC_ALRMAR_HU_Pos);
01764     sAlarm->AlarmTime.Minutes    = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
01765     sAlarm->AlarmTime.Seconds    = (uint8_t)((tmpreg & (RTC_ALRMAR_ST  | RTC_ALRMAR_SU))  >> RTC_ALRMAR_SU_Pos);
01766     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg &  RTC_ALRMAR_PM)                    >> RTC_ALRMAR_PM_Pos);
01767     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01768     sAlarm->AlarmDateWeekDay     = (uint8_t)((tmpreg & (RTC_ALRMAR_DT  | RTC_ALRMAR_DU))  >> RTC_ALRMAR_DU_Pos);
01769     sAlarm->AlarmDateWeekDaySel  = (uint32_t)(tmpreg &  RTC_ALRMAR_WDSEL);
01770     sAlarm->AlarmMask            = (uint32_t)(tmpreg &  RTC_ALARMMASK_ALL);
01771   }
01772   else
01773   {
01774     sAlarm->Alarm = RTC_ALARM_B;
01775
01776     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01777     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01778
01779     /* Fill the structure with the read parameters */
01780     sAlarm->AlarmTime.Hours      = (uint8_t)((tmpreg & (RTC_ALRMBR_HT  | RTC_ALRMBR_HU))  >> RTC_ALRMBR_HU_Pos);
01781     sAlarm->AlarmTime.Minutes    = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos);
01782     sAlarm->AlarmTime.Seconds    = (uint8_t)((tmpreg & (RTC_ALRMBR_ST  | RTC_ALRMBR_SU))  >> RTC_ALRMBR_SU_Pos);
01783     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg &  RTC_ALRMBR_PM)                    >> RTC_ALRMBR_PM_Pos);
01784     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01785     sAlarm->AlarmDateWeekDay     = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU))   >> RTC_ALRMBR_DU_Pos);
01786     sAlarm->AlarmDateWeekDaySel  = (uint32_t)(tmpreg &  RTC_ALRMBR_WDSEL);
01787     sAlarm->AlarmMask            = (uint32_t)(tmpreg &  RTC_ALARMMASK_ALL);
01788   }
01789
01790   if(Format == RTC_FORMAT_BIN)
01791   {
01792     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01793     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01794     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01795     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01796   }
01797
01798   return HAL_OK;
01799 }
01800
01801 /**
01802   * @brief  Handle Alarm interrupt request.
01803   * @param  hrtc RTC handle
01804   * @retval None
01805   */
01806 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
01807 {
01808   /* Clear the EXTI's line Flag for RTC Alarm */
01809 #if defined(DUAL_CORE)
01810   if(HAL_GetCurrentCPUID() == CM7_CPUID)
01811   {
01812     __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01813   }
01814   else
01815   {
01816     __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG();
01817   }
01818 #else  /* SINGLE_CORE */
01819   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01820 #endif /* DUAL_CORE */
01821
01822 #if defined(RTC_MISR_ALRAMF)
01823   /* Get interrupt status */
01824   uint32_t tmp = hrtc->Instance->MISR;
01825
01826   if((tmp & RTC_MISR_ALRAMF) != 0u)
01827   {
01828     /* Clear the AlarmA interrupt pending bit */
01829     hrtc->Instance->SCR = RTC_SCR_CALRAF;
01830
01831 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01832     /* Call Compare Match registered Callback */
01833     hrtc->AlarmAEventCallback(hrtc);
01834 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01835     HAL_RTC_AlarmAEventCallback(hrtc);
01836 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01837   }
01838 #endif /* RTC_MISR_ALRAMF */
01839
01840 #if defined(RTC_MISR_ALRBMF)
01841   if((tmp & RTC_MISR_ALRBMF) != 0u)
01842   {
01843     /* Clear the AlarmB interrupt pending bit */
01844     hrtc->Instance->SCR = RTC_SCR_CALRBF;
01845
01846 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01847     /* Call Compare Match registered Callback */
01848     hrtc->AlarmBEventCallback(hrtc);
01849 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01850     HAL_RTCEx_AlarmBEventCallback(hrtc);
01851 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01852   }
01853 #endif /* RTC_MISR_ALRBMF */
01854
01855 #if defined(RTC_ISR_ALRAF)
01856   /* Get the AlarmA interrupt source enable status */
01857   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
01858   {
01859     /* Get the pending status of the AlarmA Interrupt */
01860     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
01861     {
01862       /* Clear the AlarmA interrupt pending bit */
01863       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01864
01865 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01866       hrtc->AlarmAEventCallback(hrtc);
01867 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01868       HAL_RTC_AlarmAEventCallback(hrtc);
01869 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01870     }
01871   }
01872 #endif /* RTC_ISR_ALRAF */
01873
01874 #if defined(RTC_ISR_ALRBF)
01875   /* Get the AlarmB interrupt source enable status */
01876   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
01877   {
01878     /* Get the pending status of the AlarmB Interrupt */
01879     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
01880     {
01881       /* Clear the AlarmB interrupt pending bit */
01882       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01883
01884       /* AlarmB callback */
01885 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01886       hrtc->AlarmBEventCallback(hrtc);
01887 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01888       HAL_RTCEx_AlarmBEventCallback(hrtc);
01889 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01890     }
01891   }
01892 #endif /* RTC_ISR_ALRBF */
01893
01894   /* Change RTC state */
01895   hrtc->State = HAL_RTC_STATE_READY;
01896 }
01897
01898 /**
01899   * @brief  Alarm A callback.
01900   * @param  hrtc RTC handle
01901   * @retval None
01902   */
01903 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01904 {
01905   /* Prevent unused argument(s) compilation warning */
01906   UNUSED(hrtc);
01907
01908   /* NOTE : This function should not be modified, when the callback is needed,
01909             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01910    */
01911 }
01912
01913 /**
01914   * @brief  Handle AlarmA Polling request.
01915   * @param  hrtc RTC handle
01916   * @param  Timeout Timeout duration
01917   * @retval HAL status
01918   */
01919 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01920 {
01921
01922   uint32_t tickstart = HAL_GetTick();
01923
01924   while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
01925   {
01926     if(Timeout != HAL_MAX_DELAY)
01927     {
01928       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01929       {
01930         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01931         return HAL_TIMEOUT;
01932       }
01933     }
01934   }
01935
01936   /* Clear the Alarm interrupt pending bit */
01937   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01938
01939   /* Change RTC state */
01940   hrtc->State = HAL_RTC_STATE_READY;
01941
01942   return HAL_OK;
01943 }
01944
01945 /**
01946   * @}
01947   */
01948
01949 /** @addtogroup RTC_Exported_Functions_Group4
01950  *  @brief   Peripheral Control functions
01951  *
01952 @verbatim
01953  ===============================================================================
01954                      ##### Peripheral Control functions #####
01955  ===============================================================================
01956     [..]
01957     This subsection provides functions allowing to
01958       (+) Wait for RTC Time and Date Synchronization
01959
01960 @endverbatim
01961   * @{
01962   */
01963
01964 /**
01965   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01966   *         synchronized with RTC APB clock.
01967   * @note   The RTC Resynchronization mode is write protected, use the
01968   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01969   * @note   To read the calendar through the shadow registers after Calendar
01970   *         initialization, calendar update or after wakeup from low power modes
01971   *         the software must first clear the RSF flag.
01972   *         The software must then wait until it is set again before reading
01973   *         the calendar, which means that the calendar registers have been
01974   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01975   * @param  hrtc RTC handle
01976   * @retval HAL status
01977   */
01978 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
01979 {
01980   uint32_t tickstart;
01981
01982   /* Clear RSF flag */
01983 #if defined(RTC_ICSR_RSF)
01984   hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
01985 #endif /* RTC_ICSR_RSF */
01986 #if defined(RTC_ISR_RSF)
01987   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01988 #endif /* RTC_ISR_RSF */
01989
01990   tickstart = HAL_GetTick();
01991
01992   /* Wait the registers to be synchronised */
01993 #if defined(RTC_ICSR_RSF)
01994   while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
01995 #endif /* RTC_ICSR_RSF */
01996 #if defined(RTC_ISR_RSF)
01997     while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
01998 #endif /* RTC_ISR_RSF */
01999     {
02000       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02001       {
02002         return HAL_TIMEOUT;
02003       }
02004     }
02005
02006   return HAL_OK;
02007 }
02008
02009 /**
02010   * @}
02011   */
02012
02013 /** @addtogroup RTC_Exported_Functions_Group5
02014  *  @brief   Peripheral State functions
02015  *
02016 @verbatim
02017  ===============================================================================
02018                      ##### Peripheral State functions #####
02019  ===============================================================================
02020     [..]
02021     This subsection provides functions allowing to
02022       (+) Get RTC state
02023
02024 @endverbatim
02025   * @{
02026   */
02027 /**
02028   * @brief  Return the RTC handle state.
02029   * @param  hrtc RTC handle
02030   * @retval HAL state
02031   */
02032 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
02033 {
02034   /* Return RTC handle state */
02035   return hrtc->State;
02036 }
02037
02038 /**
02039   * @}
02040   */
02041
02042 /**
02043   * @}
02044   */
02045
02046 /** @addtogroup RTC_Private_Functions
02047   * @{
02048   */
02049 /**
02050   * @brief  Enter the RTC Initialization mode.
02051   * @note   The RTC Initialization mode is write protected, use the
02052   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
02053   * @param  hrtc RTC handle
02054   * @retval HAL status
02055   */
02056 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
02057 {
02058   uint32_t tickstart;
02059
02060   /* Check if the Initialization mode is set */
02061 #if defined(RTC_ICSR_INITF)
02062   if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
02063   {
02064     /* Set the Initialization mode */
02065     SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
02066
02067     tickstart = HAL_GetTick();
02068     /* Wait till RTC is in INIT state and if Time out is reached exit */
02069     while ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
02070     {
02071       if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
02072       {
02073         return HAL_TIMEOUT;
02074       }
02075     }
02076   }
02077 #endif /* RTC_ICSR_INITF */
02078 #if defined(RTC_ISR_INITF)
02079   if((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
02080   {
02081     /* Set the Initialization mode */
02082     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
02083
02084     tickstart = HAL_GetTick();
02085     /* Wait till RTC is in INIT state and if Time out is reached exit */
02086     while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
02087     {
02088       if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
02089       {
02090         return HAL_TIMEOUT;
02091       }
02092     }
02093   }
02094 #endif /* RTC_ISR_INITF */
02095
02096   return HAL_OK;
02097 }
02098
02099
02100 /**
02101   * @brief  Convert a 2 digit decimal to BCD format.
02102   * @param  Value Byte to be converted
02103   * @retval Converted byte
02104   */
02105 uint8_t RTC_ByteToBcd2(uint8_t Value)
02106 {
02107   uint32_t bcdhigh = 0U;
02108   uint8_t  bcdlow  = Value;
02109
02110   while (bcdlow >= 10U)
02111   {
02112     bcdhigh++;
02113     bcdlow -= 10U;
02114   }
02115
02116   return ((uint8_t)(bcdhigh << 4U) | bcdlow);
02117 }
02118
02119 /**
02120   * @brief  Convert from 2 digit BCD to Binary.
02121   * @param  Value BCD value to be converted
02122   * @retval Converted word
02123   */
02124 uint8_t RTC_Bcd2ToByte(uint8_t Value)
02125 {
02126   uint8_t tmp;
02127   tmp = ((Value & 0xF0U) >> 4U) * 10U;
02128   return (tmp + (Value & 0x0FU));
02129 }
02130
02131 /**
02132   * @}
02133   */
02134
02135 #endif /* HAL_RTC_MODULE_ENABLED */
02136 /**
02137   * @}
02138   */
02139
02140 /**
02141   * @}
02142   */
02143
02144 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc.h Source File

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stm32h7xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RTC_H
00022 #define STM32H7xx_HAL_RTC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup RTC RTC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup RTC_Exported_Types RTC Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  HAL State structures definition
00046   */
00047 typedef enum
00048 {
00049   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00050   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00051   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00052   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00053   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00054
00055 } HAL_RTCStateTypeDef;
00056
00057 /**
00058   * @brief  RTC Configuration Structure definition
00059   */
00060 typedef struct
00061 {
00062   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00063                                  This parameter can be a value of @ref RTC_Hour_Formats */
00064
00065   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00066                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00067
00068   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00069                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00070
00071   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00072                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00073
00074   uint32_t OutPutRemap;     /*!< Specifies the remap for RTC output.
00075                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00076
00077   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00078                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00079
00080   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00081                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00082 #if defined(RTC_CR_TAMPALRM_PU)
00083   uint32_t OutPutPullUp;    /*!< Specifies the RTC Output Pull-Up mode.
00084                                  This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
00085 #endif /* RTC_CR_TAMPALRM_PU */
00086 } RTC_InitTypeDef;
00087
00088 /**
00089   * @brief  RTC Time structure definition
00090   */
00091 typedef struct
00092 {
00093   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00094                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00095                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00096
00097   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00098                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00099
00100   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00101                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00102
00103   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00104                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00105
00106   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00107                                  This parameter corresponds to a time unit range between [0-1] Second
00108                                  with [1 Sec / SecondFraction +1] granularity */
00109
00110   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00111                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00112                                  This parameter corresponds to a time unit range between [0-1] Second
00113                                  with [1 Sec / SecondFraction +1] granularity.
00114                                  This field will be used only by HAL_RTC_GetTime function */
00115
00116   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00117                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00118
00119   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
00120                                  in CR register to store the operation.
00121                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00122 } RTC_TimeTypeDef;
00123
00124 /**
00125   * @brief  RTC Date structure definition
00126   */
00127 typedef struct
00128 {
00129   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00130                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00131
00132   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00133                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00134
00135   uint8_t Date;     /*!< Specifies the RTC Date.
00136                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00137
00138   uint8_t Year;     /*!< Specifies the RTC Date Year.
00139                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00140
00141 } RTC_DateTypeDef;
00142
00143 /**
00144   * @brief  RTC Alarm structure definition
00145   */
00146 typedef struct
00147 {
00148   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00149
00150   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00151                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00152
00153   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00154                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00155
00156   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00157                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00158
00159   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00160                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00161                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00162
00163   uint32_t Alarm;                /*!< Specifies the alarm .
00164                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00165 } RTC_AlarmTypeDef;
00166
00167 /**
00168   * @brief  RTC Handle Structure definition
00169   */
00170 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00171 typedef struct __RTC_HandleTypeDef
00172 #else
00173 typedef struct
00174 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00175 {
00176   RTC_TypeDef               *Instance;  /*!< Register base address    */
00177
00178   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00179
00180   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00181
00182   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00183
00184 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00185   void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm A Event callback         */
00186
00187   void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm B Event callback         */
00188
00189   void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC TimeStamp Event callback       */
00190
00191   void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);       /*!< RTC WakeUpTimer Event callback     */
00192
00193   void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 1 Event callback        */
00194
00195   void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 2 Event callback        */
00196
00197   void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 3 Event callback        */
00198
00199 #if defined(TAMP_CR1_ITAMP1E)
00200   void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 1 Event callback  */
00201 #endif /* TAMP_CR1_ITAMP1E */
00202
00203 #if defined(TAMP_CR1_ITAMP2E)
00204   void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 2 Event callback  */
00205 #endif /* TAMP_CR1_ITAMP2E */
00206
00207 #if defined(TAMP_CR1_ITAMP3E)
00208   void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 3 Event callback  */
00209 #endif /* TAMP_CR1_ITAMP3E */
00210
00211 #if defined(TAMP_CR1_ITAMP4E)
00212   void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 4 Event callback  */
00213 #endif /* TAMP_CR1_ITAMP4E */
00214
00215 #if defined(TAMP_CR1_ITAMP5E)
00216   void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 5 Event callback  */
00217 #endif /* TAMP_CR1_ITAMP5E */
00218
00219 #if defined(TAMP_CR1_ITAMP6E)
00220   void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 6 Event callback  */
00221 #endif /* TAMP_CR1_ITAMP6E */
00222
00223 #if defined(TAMP_CR1_ITAMP8E)
00224   void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 8 Event callback  */
00225 #endif /* TAMP_CR1_ITAMP8E */
00226
00227   void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC Msp Init callback              */
00228
00229   void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC Msp DeInit callback            */
00230
00231 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
00232
00233 } RTC_HandleTypeDef;
00234
00235 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00236 /**
00237   * @brief  HAL RTC Callback ID enumeration definition
00238   */
00239 typedef enum
00240 {
00241   HAL_RTC_ALARM_A_EVENT_CB_ID           = 0u,    /*!< RTC Alarm A Event Callback ID      */
00242   HAL_RTC_ALARM_B_EVENT_CB_ID           = 1u,    /*!< RTC Alarm B Event Callback ID      */
00243   HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 2u,    /*!< RTC TimeStamp Event Callback ID    */
00244   HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 3u,    /*!< RTC WakeUp Timer Event Callback ID */
00245   HAL_RTC_TAMPER1_EVENT_CB_ID           = 4u,    /*!< RTC Tamper 1 Callback ID           */
00246   HAL_RTC_TAMPER2_EVENT_CB_ID           = 5u,    /*!< RTC Tamper 2 Callback ID           */
00247   HAL_RTC_TAMPER3_EVENT_CB_ID           = 6u,    /*!< RTC Tamper 3 Callback ID           */
00248
00249 #if defined(TAMP_CR1_ITAMP1E)
00250   HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 12u,   /*!< RTC Internal Tamper 1 Callback ID  */
00251 #endif /* TAMP_CR1_ITAMP1E */
00252 #if defined(TAMP_CR1_ITAMP2E)
00253   HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 13u,   /*!< RTC Internal Tamper 2 Callback ID  */
00254 #endif /* TAMP_CR1_ITAMP2E */
00255 #if defined(TAMP_CR1_ITAMP3E)
00256   HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 14u,   /*!< RTC Internal Tamper 3 Callback ID  */
00257 #endif /* TAMP_CR1_ITAMP3E */
00258 #if defined(TAMP_CR1_ITAMP4E)
00259   HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 15u,   /*!< RTC Internal Tamper 4 Callback ID  */
00260 #endif /* TAMP_CR1_ITAMP4E */
00261 #if defined(TAMP_CR1_ITAMP5E)
00262   HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 16u,   /*!< RTC Internal Tamper 5 Callback ID  */
00263 #endif /* TAMP_CR1_ITAMP5E */
00264 #if defined(TAMP_CR1_ITAMP6E)
00265   HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 17u,   /*!< RTC Internal Tamper 6 Callback ID  */
00266 #endif /* TAMP_CR1_ITAMP6E */
00267 #if defined(TAMP_CR1_ITAMP8E)
00268   HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 19u,   /*!< RTC Internal Tamper 8 Callback ID  */
00269 #endif /* TAMP_CR1_ITAMP8E */
00270   HAL_RTC_MSPINIT_CB_ID                 = 20u,   /*!< RTC Msp Init callback ID           */
00271   HAL_RTC_MSPDEINIT_CB_ID               = 21u    /*!< RTC Msp DeInit callback ID         */
00272 } HAL_RTC_CallbackIDTypeDef;
00273
00274 /**
00275   * @brief  HAL RTC Callback pointer definition
00276   */
00277 typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
00278 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /* Exported constants --------------------------------------------------------*/
00285 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00286   * @{
00287   */
00288
00289 /** @defgroup RTC_Hour_Formats_Definitions RTC Hour Formats Definitions
00290   * @{
00291   */
00292 #define RTC_HOURFORMAT_24              0x00000000u
00293 #define RTC_HOURFORMAT_12              RTC_CR_FMT
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
00299   * @{
00300   */
00301 #define RTC_OUTPUT_DISABLE             0x00000000u
00302 #define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0
00303 #define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1
00304 #define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL
00305 #if defined(RTC_CR_TAMPOE)
00306 #define RTC_OUTPUT_TAMPER              RTC_CR_TAMPOE
00307 #endif /* RTC_CR_TAMPOE */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00313   * @{
00314   */
00315 #define RTC_OUTPUT_POLARITY_HIGH       0x00000000u
00316 #define RTC_OUTPUT_POLARITY_LOW        RTC_CR_POL
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00322   * @{
00323   */
00324 #if defined(RTC_CR_TAMPALRM_TYPE)
00325 #define RTC_OUTPUT_TYPE_PUSHPULL       0x00000000u
00326 #define RTC_OUTPUT_TYPE_OPENDRAIN      RTC_CR_TAMPALRM_TYPE
00327 #define RTC_ALARM_OUTPUT_TYPE          RTC_CR_TAMPALRM_TYPE
00328 #endif /* RTC_CR_TAMPALRM_TYPE */
00329
00330 #if defined(RTC_OR_ALARMOUTTYPE)
00331 #define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMOUTTYPE
00332 #define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000u
00333 #define RTC_ALARM_OUTPUT_TYPE          RTC_OR_ALARMOUTTYPE
00334 #endif /* RTC_OR_ALARMOUTTYPE */
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
00340   * @{
00341   */
00342 #if defined(RTC_CR_TAMPALRM_PU)
00343 #define RTC_OUTPUT_PULLUP_NONE         0x00000000u
00344 #define RTC_OUTPUT_PULLUP_ON           RTC_CR_TAMPALRM_PU
00345 #endif /* RTC_CR_TAMPALRM_PU */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00351   * @{
00352   */
00353 #if defined(RTC_CR_OUT2EN)
00354 #define RTC_OUTPUT_REMAP_NONE          0x00000000u
00355 #define RTC_OUTPUT_REMAP_POS1          RTC_CR_OUT2EN
00356 #endif /* RTC_CR_OUT2EN */
00357
00358 #if defined(RTC_OR_OUT_RMP)
00359 #define RTC_OUTPUT_REMAP_NONE          0x00000000u
00360 #define RTC_OUTPUT_REMAP_POS1          RTC_OR_OUT_RMP
00361 #endif /* RTC_OR_OUT_RMP */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00367   * @{
00368   */
00369 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
00370 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x01)
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
00376   * @{
00377   */
00378 #define RTC_DAYLIGHTSAVING_SUB1H       RTC_CR_SUB1H
00379 #define RTC_DAYLIGHTSAVING_ADD1H       RTC_CR_ADD1H
00380 #define RTC_DAYLIGHTSAVING_NONE        0x00000000u
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
00386   * @{
00387   */
00388 #define RTC_STOREOPERATION_RESET        0x00000000u
00389 #define RTC_STOREOPERATION_SET          RTC_CR_BKP
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00395   * @{
00396   */
00397 #define RTC_FORMAT_BIN                  0x00000000u
00398 #define RTC_FORMAT_BCD                  0x00000001u
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
00404   * @{
00405   */
00406 #define RTC_MONTH_JANUARY                   ((uint8_t)0x01)
00407 #define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02)
00408 #define RTC_MONTH_MARCH                     ((uint8_t)0x03)
00409 #define RTC_MONTH_APRIL                     ((uint8_t)0x04)
00410 #define RTC_MONTH_MAY                       ((uint8_t)0x05)
00411 #define RTC_MONTH_JUNE                      ((uint8_t)0x06)
00412 #define RTC_MONTH_JULY                      ((uint8_t)0x07)
00413 #define RTC_MONTH_AUGUST                    ((uint8_t)0x08)
00414 #define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09)
00415 #define RTC_MONTH_OCTOBER                   ((uint8_t)0x10)
00416 #define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11)
00417 #define RTC_MONTH_DECEMBER                  ((uint8_t)0x12)
00418
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00424   * @{
00425   */
00426 #define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01)
00427 #define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02)
00428 #define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03)
00429 #define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04)
00430 #define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05)
00431 #define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06)
00432 #define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07)
00433
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
00439   * @{
00440   */
00441 #define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000u
00442 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL
00443
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
00449   * @{
00450   */
00451 #define RTC_ALARMMASK_NONE                0x00000000u
00452 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00453 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00454 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00455 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00456 #define RTC_ALARMMASK_ALL                 (RTC_ALARMMASK_DATEWEEKDAY | \
00457                                            RTC_ALARMMASK_HOURS       | \
00458                                            RTC_ALARMMASK_MINUTES     | \
00459                                            RTC_ALARMMASK_SECONDS)
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00465   * @{
00466   */
00467 #define RTC_ALARM_A                       RTC_CR_ALRAE
00468 #define RTC_ALARM_B                       RTC_CR_ALRBE
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00474   * @{
00475   */
00476 /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
00477 #define RTC_ALARMSUBSECONDMASK_ALL         0x00000000u
00478 /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.     */
00479 #define RTC_ALARMSUBSECONDMASK_SS14_1      RTC_ALRMASSR_MASKSS_0
00480 /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared.  */
00481 #define RTC_ALARMSUBSECONDMASK_SS14_2      RTC_ALRMASSR_MASKSS_1
00482 /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared.  */
00483 #define RTC_ALARMSUBSECONDMASK_SS14_3      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
00484 /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared.  */
00485 #define RTC_ALARMSUBSECONDMASK_SS14_4      RTC_ALRMASSR_MASKSS_2
00486 /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared.  */
00487 #define RTC_ALARMSUBSECONDMASK_SS14_5      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
00488 /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared.  */
00489 #define RTC_ALARMSUBSECONDMASK_SS14_6      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
00490 /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared.  */
00491 #define RTC_ALARMSUBSECONDMASK_SS14_7      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
00492 /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared.  */
00493 #define RTC_ALARMSUBSECONDMASK_SS14_8      RTC_ALRMASSR_MASKSS_3
00494 /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared.  */
00495 #define RTC_ALARMSUBSECONDMASK_SS14_9      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
00496 /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
00497 #define RTC_ALARMSUBSECONDMASK_SS14_10     (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
00498 /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
00499 #define RTC_ALARMSUBSECONDMASK_SS14_11     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
00500 /*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
00501 #define RTC_ALARMSUBSECONDMASK_SS14_12     (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
00502 /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
00503 #define RTC_ALARMSUBSECONDMASK_SS14_13     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
00504 /*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
00505 #define RTC_ALARMSUBSECONDMASK_SS14        (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
00506 /*!< SS[14:0] are compared and must match to activate alarm. */
00507 #define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS
00508
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00514   * @{
00515   */
00516 #define RTC_IT_TS                         RTC_CR_TSIE         /*!< Enable Timestamp Interrupt               */
00517 #define RTC_IT_WUT                        RTC_CR_WUTIE        /*!< Enable Wakeup timer Interrupt            */
00518 #define RTC_IT_ALRA                       RTC_CR_ALRAIE       /*!< Enable Alarm A Interrupt                 */
00519 #define RTC_IT_ALRB                       RTC_CR_ALRBIE       /*!< Enable Alarm B Interrupt                 */
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00525   * @{
00526   */
00527 #if defined(RTC_ICSR_RECALPF)
00528 #define RTC_FLAG_RECALPF                  RTC_ICSR_RECALPF  /*!< Recalibration pending Flag */
00529 #endif /* RTC_ICSR_RECALPF */
00530 #if defined(RTC_ICSR_INITF)
00531 #define RTC_FLAG_INITF                    RTC_ICSR_INITF    /*!< Initialization pending flag */
00532 #endif /* RTC_ICSR_INITF */
00533 #if defined(RTC_ICSR_RSF)
00534 #define RTC_FLAG_RSF                      RTC_ICSR_RSF      /*!< Registers synchronization flag */
00535 #endif /* RTC_ICSR_RSF */
00536 #if defined(RTC_ICSR_INITS)
00537 #define RTC_FLAG_INITS                    RTC_ICSR_INITS    /*!< Initialization status flag */
00538 #endif /* RTC_ICSR_INITS */
00539 #if defined(RTC_ICSR_SHPF)
00540 #define RTC_FLAG_SHPF                     RTC_ICSR_SHPF     /*!< Shift operation pending flag */
00541 #endif /* RTC_ICSR_SHPF */
00542 #if defined(RTC_ICSR_WUTWF)
00543 #define RTC_FLAG_WUTWF                    RTC_ICSR_WUTWF    /*!< Wakeup timer write operation pending flag */
00544 #endif /* RTC_ICSR_WUTWF */
00545 #if defined(RTC_ICSR_ALRBWF)
00546 #define RTC_FLAG_ALRBWF                   RTC_ICSR_ALRBWF   /*!< Alarm B write operation pending flag */
00547 #endif /* RTC_ICSR_ALRBWF */
00548 #if defined(RTC_ICSR_ALRAWF)
00549 #define RTC_FLAG_ALRAWF                   RTC_ICSR_ALRAWF   /*!< Alarm A write operation pending flag */
00550 #endif /* RTC_ICSR_ALRAWF */
00551 #if defined(RTC_SR_ITSF)
00552 #define RTC_FLAG_ITSF                     RTC_SR_ITSF       /*!< Internal Time-stamp flag */
00553 #endif /* RTC_SR_ITSF */
00554 #if defined(RTC_SR_TSOVF)
00555 #define RTC_FLAG_TSOVF                    RTC_SR_TSOVF      /*!< Time-stamp overflow flag */
00556 #endif /* RTC_SR_TSOVF */
00557 #if defined(RTC_SR_TSF)
00558 #define RTC_FLAG_TSF                      RTC_SR_TSF        /*!< Time-stamp flag */
00559 #endif /* RTC_SR_TSF */
00560 #if defined(RTC_SR_WUTF)
00561 #define RTC_FLAG_WUTF                     RTC_SR_WUTF       /*!< Wakeup timer flag */
00562 #endif /* RTC_SR_WUTF */
00563 #if defined(RTC_SR_ALRBF)
00564 #define RTC_FLAG_ALRBF                    RTC_SR_ALRBF      /*!< Alarm B flag */
00565 #endif /* RTC_SR_ALRBF */
00566 #if defined(RTC_SR_ALRAF)
00567 #define RTC_FLAG_ALRAF                    RTC_SR_ALRAF      /*!< Alarm A flag */
00568 #endif /* RTC_SR_ALRAF */
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
00574   * @{
00575   */
00576 #if defined(RTC_SCR_CITSF)
00577 #define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
00578 #endif /* RTC_SCR_CITSF */
00579 #if defined(RTC_SCR_CTSOVF)
00580 #define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
00581 #endif /* RTC_SCR_CTSOVF */
00582 #if defined(RTC_SCR_CTSF)
00583 #define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
00584 #endif /* RTC_SCR_CTSF */
00585 #if defined(RTC_SCR_CWUTF)
00586 #define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
00587 #endif /* RTC_SCR_CWUTF */
00588 #if defined(RTC_SCR_CALRBF)
00589 #define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
00590 #endif /* RTC_SCR_CALRBF */
00591 #if defined(RTC_SCR_CALRAF)
00592 #define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
00593 #endif /* RTC_SCR_CALRAF */
00594 /**
00595   * @}
00596   */
00597
00598 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00599   * @{
00600   */
00601 #if defined(RTC_ISR_RECALPF)
00602 #define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
00603 #endif /* RTC_ISR_RECALPF */
00604 #if defined(RTC_ISR_TSOVF)
00605 #define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
00606 #endif /* RTC_ISR_TSOVF */
00607 #if defined(RTC_ISR_TSF)
00608 #define RTC_FLAG_TSF                      RTC_ISR_TSF
00609 #endif /* RTC_ISR_TSF */
00610 #if defined(RTC_ISR_ITSF)
00611 #define RTC_FLAG_ITSF                     RTC_ISR_ITSF
00612 #endif /* RTC_ISR_ITSF */
00613 #if defined(RTC_ISR_WUTF)
00614 #define RTC_FLAG_WUTF                     RTC_ISR_WUTF
00615 #endif /* RTC_ISR_WUTF */
00616 #if defined(RTC_ISR_ALRBF)
00617 #define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
00618 #endif /* RTC_ISR_ALRBF */
00619 #if defined(RTC_ISR_ALRAF)
00620 #define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
00621 #endif /* RTC_ISR_ALRAF */
00622 #if defined(RTC_ISR_INITF)
00623 #define RTC_FLAG_INITF                    RTC_ISR_INITF
00624 #endif /* RTC_ISR_INITF */
00625 #if defined(RTC_ISR_RSF)
00626 #define RTC_FLAG_RSF                      RTC_ISR_RSF
00627 #endif /* RTC_ISR_RSF */
00628 #if defined(RTC_ISR_INITS)
00629 #define RTC_FLAG_INITS                    RTC_ISR_INITS
00630 #endif /* RTC_ISR_INITS */
00631 #if defined(RTC_ISR_SHPF)
00632 #define RTC_FLAG_SHPF                     RTC_ISR_SHPF
00633 #endif /* RTC_ISR_SHPF */
00634 #if defined(RTC_ISR_WUTWF)
00635 #define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
00636 #endif /* RTC_ISR_WUTWF */
00637 #if defined(RTC_ISR_ALRBWF)
00638 #define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
00639 #endif /* RTC_ISR_ALRBWF */
00640 #if defined(RTC_ISR_ALRAWF)
00641 #define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
00642 #endif /* RTC_ISR_ALRAWF */
00643 /**
00644   * @}
00645   */
00646
00647 /**
00648   * @}
00649   */
00650
00651 /* Exported macros -----------------------------------------------------------*/
00652 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00653   * @{
00654   */
00655
00656 /** @brief Reset RTC handle state
00657   * @param  __HANDLE__ RTC handle.
00658   * @retval None
00659   */
00660 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00661 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{                                              \
00662                                                       (__HANDLE__)->State = HAL_RTC_STATE_RESET;  \
00663                                                       (__HANDLE__)->MspInitCallback = NULL;       \
00664                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
00665                                                      }while(0u)
00666 #else
00667 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00668 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00669
00670 /**
00671   * @brief  Disable the write protection for RTC registers.
00672   * @param  __HANDLE__ specifies the RTC handle.
00673   * @retval None
00674   */
00675 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)              \
00676                         do{                                        \
00677                             (__HANDLE__)->Instance->WPR = 0xCAU;   \
00678                             (__HANDLE__)->Instance->WPR = 0x53U;   \
00679                           } while(0u)
00680
00681 /**
00682   * @brief  Enable the write protection for RTC registers.
00683   * @param  __HANDLE__ specifies the RTC handle.
00684   * @retval None
00685   */
00686 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)               \
00687                         do{                                        \
00688                             (__HANDLE__)->Instance->WPR = 0xFFU;   \
00689                           } while(0u)
00690
00691 /**
00692   * @brief  Add 1 hour (summer time change).
00693   * @param  __HANDLE__ specifies the RTC handle.
00694   * @param  __BKP__ Backup
00695   *         This parameter can be:
00696   *            @arg @ref RTC_STOREOPERATION_RESET
00697   *            @arg @ref RTC_STOREOPERATION_SET
00698   * @retval None
00699   */
00700 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                           \
00701                         do {                                                                \
00702                             __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
00703                             SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);              \
00704                             MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00705                             __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
00706                         } while(0u);
00707
00708 /**
00709   * @brief  Subtract 1 hour (winter time change).
00710   * @param  __HANDLE__ specifies the RTC handle.
00711   * @param  __BKP__ Backup
00712   *         This parameter can be:
00713   *            @arg @ref RTC_STOREOPERATION_RESET
00714   *            @arg @ref RTC_STOREOPERATION_SET
00715   * @retval None
00716   */
00717 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                           \
00718                         do {                                                                \
00719                             __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
00720                             SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);              \
00721                             MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00722                             __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
00723                         } while(0u);
00724
00725 /**
00726   * @brief  Enable the RTC ALARMA peripheral.
00727   * @param  __HANDLE__ specifies the RTC handle.
00728   * @retval None
00729   */
00730 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00731
00732 /**
00733   * @brief  Disable the RTC ALARMA peripheral.
00734   * @param  __HANDLE__ specifies the RTC handle.
00735   * @retval None
00736   */
00737 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00738
00739 /**
00740   * @brief  Enable the RTC ALARMB peripheral.
00741   * @param  __HANDLE__ specifies the RTC handle.
00742   * @retval None
00743   */
00744 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00745
00746 /**
00747   * @brief  Disable the RTC ALARMB peripheral.
00748   * @param  __HANDLE__ specifies the RTC handle.
00749   * @retval None
00750   */
00751 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00752
00753 /**
00754   * @brief  Enable the RTC Alarm interrupt.
00755   * @param  __HANDLE__ specifies the RTC handle.
00756   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00757   *          This parameter can be any combination of the following values:
00758   *             @arg @ref RTC_IT_ALRA Alarm A interrupt
00759   *             @arg @ref RTC_IT_ALRB Alarm B interrupt
00760   * @retval None
00761   */
00762 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00763
00764 /**
00765   * @brief  Disable the RTC Alarm interrupt.
00766   * @param  __HANDLE__ specifies the RTC handle.
00767   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00768   *         This parameter can be any combination of the following values:
00769   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00770   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00771   * @retval None
00772   */
00773 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00774
00775 /**
00776   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00777   * @param  __HANDLE__ specifies the RTC handle.
00778   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00779   *         This parameter can be:
00780   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00781   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00782   * @retval None
00783   */
00784 #if defined(RTC_MISR_ALRAMF)
00785 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)
00786 #endif /* RTC_MISR_ALRAMF */
00787 #if defined(RTC_ISR_ALRAF)
00788 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U)
00789 #endif /* RTC_ISR_ALRAF */
00790
00791 /**
00792   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00793   * @param  __HANDLE__ specifies the RTC handle.
00794   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00795   *         This parameter can be:
00796   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00797   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00798   * @retval None
00799   */
00800 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00801
00802 #if defined(RTC_SR_ALRAF)
00803 /**
00804   * @brief  Get the selected RTC Alarm's flag status.
00805   * @param  __HANDLE__ specifies the RTC handle.
00806   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
00807   *         This parameter can be:
00808   *            @arg @ref RTC_FLAG_ALRAF
00809   *            @arg @ref RTC_FLAG_ALRBF
00810   * @retval None
00811   */
00812 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
00813 #endif /* RTC_SR_ALRAF */
00814 #if defined(RTC_ISR_ALRAF)
00815 /**
00816   * @brief  Get the selected RTC Alarm's flag status.
00817   * @param  __HANDLE__ specifies the RTC handle.
00818   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
00819   *         This parameter can be:
00820   *            @arg @ref RTC_FLAG_ALRAF
00821   *            @arg @ref RTC_FLAG_ALRBF
00822   *            @arg @ref RTC_FLAG_ALRAWF
00823   *            @arg @ref RTC_FLAG_ALRBWF
00824   * @retval None
00825   */
00826 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00827 #endif /* RTC_ISR_ALRAF */
00828
00829 /**
00830   * @brief  Clear the RTC Alarm's pending flags.
00831   * @param  __HANDLE__ specifies the RTC handle.
00832   * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
00833   *          This parameter can be:
00834   *             @arg @ref RTC_FLAG_ALRAF
00835   *             @arg @ref RTC_FLAG_ALRBF
00836   * @retval None
00837   */
00838 #if defined(RTC_SCR_CALRAF)
00839 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->SCR |= __FLAG__)
00840 #endif /* RTC_SCR_CALRAF */
00841 #if defined(RTC_ISR_ALRAF)
00842 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
00843 #endif /* RTC_ISR_ALRAF */
00844
00845
00846 /**
00847   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00848   * @retval None
00849   */
00850 #if defined(EXTI_D1)
00851 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00852 #else  /* EXTI */
00853 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1    |= RTC_EXTI_LINE_ALARM_EVENT)
00854 #endif /* EXTI_D1 */
00855
00856 /**
00857   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00858   * @retval None
00859   */
00860 #if defined(EXTI_D1)
00861 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00862 #else  /* EXTI */
00863 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00864 #endif /* EXTI_D1 */
00865
00866 /**
00867   * @brief  Enable event on the RTC Alarm associated Exti line.
00868   * @retval None.
00869   */
00870 #if defined(EXTI_D1)
00871 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00872 #else  /* EXTI */
00873 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1    |= RTC_EXTI_LINE_ALARM_EVENT)
00874 #endif /* EXTI_D1 */
00875
00876 /**
00877   * @brief  Disable event on the RTC Alarm associated Exti line.
00878   * @retval None.
00879   */
00880 #if defined(EXTI_D1)
00881 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00882 #else  /* EXTI */
00883 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00884 #endif /* EXTI_D1 */
00885
00886 #if defined(DUAL_CORE)
00887 /**
00888   * @brief  Enable interrupt on the RTC Alarm associated D2 Exti line.
00889   * @retval None
00890   */
00891 #define __HAL_RTC_ALARM_EXTID2_ENABLE_IT()          (EXTI_D2->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00892
00893 /**
00894   * @brief  Disable interrupt on the RTC Alarm associated D2 Exti line.
00895   * @retval None
00896   */
00897 #define __HAL_RTC_ALARM_EXTID2_DISABLE_IT()         (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00898
00899 /**
00900   * @brief  Enable event on the RTC Alarm associated D2 Exti line.
00901   * @retval None
00902   */
00903 #define __HAL_RTC_ALARM_EXTID2_ENABLE_EVENT()        (EXTI_D2->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00904
00905 /**
00906   * @brief  Disable event on the RTC Alarm associated D2 Exti line.
00907   * @retval None
00908   */
00909 #define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT()       (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00910
00911 #endif
00912 /**
00913   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00914   * @retval None
00915   */
00916 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00917
00918 /**
00919   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00920   * @retval None
00921   */
00922 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00923
00924 /**
00925   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00926   * @retval None
00927   */
00928 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00929
00930 /**
00931   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00932   * @retval None
00933   */
00934 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00935
00936 /**
00937   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00938   * @retval None
00939   */
00940 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00941                                                              __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
00942                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
00943                                                            } while(0u)
00944
00945 /**
00946   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00947   * @retval None
00948   */
00949 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00950                                                              __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
00951                                                              __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
00952                                                            } while(0u)
00953
00954 /**
00955   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00956   * @retval Line Status.
00957   */
00958 #if defined(EXTI_D1)
00959 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
00960 #else  /* EXTI */
00961 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1    & RTC_EXTI_LINE_ALARM_EVENT)
00962 #endif /* EXTI_D1 */
00963
00964 /**
00965   * @brief Clear the RTC Alarm associated Exti line flag.
00966   * @retval None.
00967   */
00968 #if defined(EXTI_D1)
00969 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
00970 #else  /* EXTI */
00971 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1    = (RTC_EXTI_LINE_ALARM_EVENT))
00972 #endif /* EXTI_D1 */
00973
00974 #if defined(DUAL_CORE)
00975 /**
00976   * @brief Check whether the RTC Alarm associated D2 Exti line interrupt flag is set or not.
00977   * @retval Line Status
00978   */
00979 #define __HAL_RTC_ALARM_EXTID2_GET_FLAG()            (EXTI_D2->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
00980
00981 /**
00982   * @brief Clear the RTC Alarm associated D2 Exti line flag.
00983   * @retval None
00984   */
00985 #define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG()          (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
00986 #endif
00987 /**
00988   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00989   * @retval None
00990   */
00991 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
00992
00993 /**
00994   * @}
00995   */
00996
00997 /* Include RTC HAL Extended module */
00998 #include "stm32h7xx_hal_rtc_ex.h"
00999
01000 /* Exported functions --------------------------------------------------------*/
01001 /** @defgroup RTC_Exported_Functions RTC Exported Functions
01002   * @{
01003   */
01004
01005 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
01006   * @{
01007   */
01008 /* Initialization and de-initialization functions  ****************************/
01009 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
01010 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
01011
01012 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
01013 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
01014
01015 /* Callbacks Register/UnRegister functions  ***********************************/
01016 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01017 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
01018 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
01019 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01020 /**
01021   * @}
01022   */
01023
01024 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
01025   * @{
01026   */
01027 /* RTC Time and Date functions ************************************************/
01028 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
01029 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
01030 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
01031 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
01032 /**
01033   * @}
01034   */
01035
01036 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
01037   * @{
01038   */
01039 /* RTC Alarm functions ********************************************************/
01040 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
01041 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
01042 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
01043 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
01044 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
01045 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
01046 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01047 /**
01048   * @}
01049   */
01050
01051 /** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
01052   * @{
01053   */
01054 /* Peripheral Control functions ***********************************************/
01055 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
01056 /**
01057   * @}
01058   */
01059
01060 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
01061   * @{
01062   */
01063 /* Peripheral State functions *************************************************/
01064 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
01065 /**
01066   * @}
01067   */
01068
01069 /**
01070   * @}
01071   */
01072
01073 /* Private types -------------------------------------------------------------*/
01074 /* Private variables ---------------------------------------------------------*/
01075 /* Private constants ---------------------------------------------------------*/
01076 /** @defgroup RTC_Private_Constants RTC Private Constants
01077   * @{
01078   */
01079 /* Masks Definition */
01080 #define RTC_TR_RESERVED_MASK    (RTC_TR_PM  | RTC_TR_HT | RTC_TR_HU | \
01081                                  RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
01082                                  RTC_TR_SU)
01083
01084 #define RTC_DR_RESERVED_MASK    (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
01085                                  RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
01086                                  RTC_DR_DU)
01087
01088 #define RTC_INIT_MASK           0xFFFFFFFFu
01089
01090 #if defined(RTC_ICSR_INIT) && defined(RTC_ICSR_RSF)
01091 #define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
01092 #endif /* RTC_ICSR_INIT && RTC_ICSR_RSF */
01093
01094 #if defined(RTC_ISR_INIT) && defined(RTC_ISR_RSF)
01095 #define RTC_RSF_MASK                        (~(RTC_ISR_INIT | RTC_ISR_RSF))
01096 #endif /* RTC_ISR_INIT && RTC_ISR_RSF */
01097
01098 #define RTC_TIMEOUT_VALUE  1000u
01099
01100 #define RTC_EXTI_LINE_ALARM_EVENT    EXTI_IMR1_IM17  /*!< External interrupt line 17 Connected to the RTC Alarm event */
01101
01102 /**
01103   * @}
01104   */
01105
01106 /* Private macros ------------------------------------------------------------*/
01107 /** @defgroup RTC_Private_Macros RTC Private Macros
01108   * @{
01109   */
01110
01111 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
01112   * @{
01113   */
01114
01115 #if defined(RTC_CR_TAMPOE)
01116 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
01117                                ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
01118                                ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
01119                                ((OUTPUT) == RTC_OUTPUT_WAKEUP)      || \
01120                                ((OUTPUT) == RTC_OUTPUT_TAMPER))
01121 #else  /* RTC_CR_TAMPOE not defined */
01122 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
01123                                ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
01124                                ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
01125                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
01126 #endif /* RTC_CR_TAMPOE */
01127
01128 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
01129                                         ((FORMAT) == RTC_HOURFORMAT_24))
01130
01131 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
01132                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
01133
01134 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
01135                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
01136
01137 #if defined(RTC_CR_TAMPALRM_PU)
01138 #define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
01139                                     ((TYPE) == RTC_OUTPUT_PULLUP_ON))
01140 #endif /* RTC_CR_TAMPALRM_PU */
01141
01142 #define IS_RTC_OUTPUT_REMAP(REMAP)     (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
01143                                         ((REMAP) == RTC_OUTPUT_REMAP_POS1))
01144
01145 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
01146                                   ((PM) == RTC_HOURFORMAT12_PM))
01147
01148 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
01149                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
01150                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
01151
01152 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
01153                                            ((OPERATION) == RTC_STOREOPERATION_SET))
01154
01155 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
01156                                ((FORMAT) == RTC_FORMAT_BCD))
01157
01158 #define IS_RTC_YEAR(YEAR)              ((YEAR)   <= 99u)
01159
01160 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))
01161
01162 #define IS_RTC_DATE(DATE)              (((DATE)  >= 1u) && ((DATE)  <= 31u))
01163
01164 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
01165                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
01166                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
01167                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
01168                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
01169                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
01170                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
01171
01172 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0u) && ((DATE) <= 31u))
01173
01174 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
01175                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
01176                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
01177                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
01178                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
01179                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
01180                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
01181
01182 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
01183                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
01184
01185 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)
01186
01187 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
01188                                   ((ALARM) == RTC_ALARM_B))
01189
01190 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
01191
01192 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0u) || \
01193                                                     (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
01194
01195 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
01196
01197 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
01198
01199 #define IS_RTC_HOUR12(HOUR)            (((HOUR) >  0u) && ((HOUR) <= 12u))
01200
01201 #define IS_RTC_HOUR24(HOUR)            ((HOUR)    <= 23u)
01202
01203 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)
01204
01205 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59u)
01206
01207 /**
01208   * @}
01209   */
01210
01211 /**
01212   * @}
01213   */
01214
01215 /* Private functions -------------------------------------------------------------*/
01216 /** @defgroup RTC_Private_Functions RTC Private Functions
01217   * @{
01218   */
01219 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
01220 uint8_t            RTC_ByteToBcd2(uint8_t Value);
01221 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
01222
01223 /**
01224   * @}
01225   */
01226
01227 /**
01228   * @}
01229   */
01230
01231 /**
01232   * @}
01233   */
01234
01235 #ifdef __cplusplus
01236 }
01237 #endif
01238
01239 #endif /* STM32H7xx_HAL_RTC_H */
01240
01241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc_ex.c Source File

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stm32h7xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00008   *           + RTC Time Stamp functions
00009   *           + RTC Tamper functions
00010   *           + RTC Wake-up functions
00011   *           + Extended Control functions
00012   *           + Extended RTC features functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                   ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     (+) Enable the RTC domain access.
00020     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00021         format using the HAL_RTC_Init() function.
00022
00023   *** RTC Wakeup configuration ***
00024   ================================
00025   [..]
00026     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00027         function. You can also configure the RTC Wakeup timer with interrupt mode
00028         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00029     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00030         function.
00031
00032   *** Outputs configuration ***
00033   =============================
00034   [..]  The RTC has 2 different outputs:
00035     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00036         and WaKeUp signals.
00037         To output the selected RTC signal, use the HAL_RTC_Init() function.
00038     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00039         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00040     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00041         the RTC_OR register.
00042     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00043         automatically configured in output alternate function.
00044
00045   *** Smooth digital Calibration configuration ***
00046   ================================================
00047   [..]
00048     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00049         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00050         function.
00051
00052   *** TimeStamp configuration ***
00053   ===============================
00054   [..]
00055     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00056         You can also configure the RTC TimeStamp with interrupt mode using the
00057         HAL_RTCEx_SetTimeStamp_IT() function.
00058     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00059         function.
00060
00061   *** Internal TimeStamp configuration ***
00062   ===============================
00063   [..]
00064     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00065         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00066     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00067         function.
00068
00069   *** Tamper configuration ***
00070   ============================
00071   [..]
00072     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00073         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00074         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00075         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00076         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00077     (+) The default configuration of the Tamper erases the backup registers. To avoid
00078         erase, enable the NoErase field on the RTC_TAMPCR register.
00079
00080   *** Backup Data Registers configuration ***
00081   ===========================================
00082   [..]
00083     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00084         function.
00085     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00086         function.
00087
00088    @endverbatim
00089   ******************************************************************************
00090   * @attention
00091   *
00092   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00093   * All rights reserved.</center></h2>
00094   *
00095   * This software component is licensed by ST under BSD 3-Clause license,
00096   * the "License"; You may not use this file except in compliance with the
00097   * License. You may obtain a copy of the License at:
00098   *                        opensource.org/licenses/BSD-3-Clause
00099   *
00100   ******************************************************************************
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32h7xx_hal.h"
00105
00106 /** @addtogroup STM32H7xx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @addtogroup RTCEx
00111   * @brief RTC Extended HAL module driver
00112   * @{
00113   */
00114
00115 #ifdef HAL_RTC_MODULE_ENABLED
00116
00117 /* Private typedef -----------------------------------------------------------*/
00118 /* Private define ------------------------------------------------------------*/
00119 /** @addtogroup RTCEx_Exported_Constants
00120   * @{
00121   */
00122 /** @addtogroup RTCEx_Tamper_Pins_Definitions
00123   * @{
00124   */
00125 #define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)
00126 /**
00127   * @}
00128   */
00129 /**
00130   * @}
00131   */
00132
00133 /* Private macro -------------------------------------------------------------*/
00134 /* Private variables ---------------------------------------------------------*/
00135 /* Private function prototypes -----------------------------------------------*/
00136 /* Exported functions --------------------------------------------------------*/
00137
00138 /** @addtogroup RTCEx_Exported_Functions
00139   * @{
00140   */
00141
00142
00143 /** @addtogroup RTCEx_Exported_Functions_Group1
00144  *  @brief   RTC TimeStamp and Tamper functions
00145   *
00146 @verbatim
00147  ===============================================================================
00148                  ##### RTC TimeStamp and Tamper functions #####
00149  ===============================================================================
00150
00151  [..] This section provides functions allowing to configure TimeStamp feature
00152
00153 @endverbatim
00154   * @{
00155   */
00156
00157 /**
00158   * @brief  Set TimeStamp.
00159   * @note   This API must be called before enabling the TimeStamp feature.
00160   * @param  hrtc RTC handle
00161   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00162   *         activated.
00163   *          This parameter can be one of the following values:
00164   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00165   *                                        rising edge of the related pin.
00166   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00167   *                                         falling edge of the related pin.
00168   * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
00169   *          This parameter can be one of the following values:
00170   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00171   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00172   *               compatibility, this parameter is required.
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00176 {
00177   uint32_t tmpreg;
00178
00179   /* Check the parameters */
00180   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00181   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00182
00183   /* Prevent unused argument(s) compilation warning if no assert_param check */
00184   UNUSED(RTC_TimeStampPin);
00185
00186   /* Process Locked */
00187   __HAL_LOCK(hrtc);
00188
00189   hrtc->State = HAL_RTC_STATE_BUSY;
00190
00191   /* Get the RTC_CR register and clear the bits to be configured */
00192   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00193
00194   tmpreg |= TimeStampEdge;
00195
00196   /* Disable the write protection for RTC registers */
00197   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00198
00199   /* Configure the Time Stamp TSEDGE and Enable bits */
00200   hrtc->Instance->CR = (uint32_t)tmpreg;
00201
00202   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00203
00204   /* Enable the write protection for RTC registers */
00205   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00206
00207   /* Change RTC state */
00208   hrtc->State = HAL_RTC_STATE_READY;
00209
00210   /* Process Unlocked */
00211   __HAL_UNLOCK(hrtc);
00212
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  Set TimeStamp with Interrupt.
00218   * @note   This API must be called before enabling the TimeStamp feature.
00219   * @param  hrtc RTC handle
00220   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00221   *         activated.
00222   *          This parameter can be one of the following values:
00223   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00224   *                                        rising edge of the related pin.
00225   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00226   *                                         falling edge of the related pin.
00227   * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
00228   *          This parameter can be one of the following values:
00229   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00230   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00231   *               compatibility, this parameter is required.
00232   * @retval HAL status
00233   */
00234 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00235 {
00236   uint32_t tmpreg;
00237
00238   /* Check the parameters */
00239   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00240   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00241
00242   /* Prevent unused argument(s) compilation warning if no assert_param check */
00243   UNUSED(RTC_TimeStampPin);
00244
00245   /* Process Locked */
00246   __HAL_LOCK(hrtc);
00247
00248   hrtc->State = HAL_RTC_STATE_BUSY;
00249
00250   /* Get the RTC_CR register and clear the bits to be configured */
00251   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00252
00253   tmpreg |= TimeStampEdge;
00254
00255   /* Disable the write protection for RTC registers */
00256   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00257
00258   /* Configure the Time Stamp TSEDGE and Enable bits */
00259   hrtc->Instance->CR = (uint32_t)tmpreg;
00260
00261   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00262
00263   /* Enable IT timestamp */
00264   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
00265
00266 #if !defined(DUAL_CORE)
00267   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00268   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00269 #endif
00270
00271   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00272
00273   /* Enable the write protection for RTC registers */
00274   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00275
00276   hrtc->State = HAL_RTC_STATE_READY;
00277
00278   /* Process Unlocked */
00279   __HAL_UNLOCK(hrtc);
00280
00281   return HAL_OK;
00282 }
00283
00284 /**
00285   * @brief  Deactivate TimeStamp.
00286   * @param  hrtc RTC handle
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00290 {
00291   uint32_t tmpreg;
00292
00293   /* Process Locked */
00294   __HAL_LOCK(hrtc);
00295
00296   hrtc->State = HAL_RTC_STATE_BUSY;
00297
00298   /* Disable the write protection for RTC registers */
00299   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00300
00301   /* In case of interrupt mode is used, the interrupt source must disabled */
00302   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00303
00304   /* Get the RTC_CR register and clear the bits to be configured */
00305   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00306
00307   /* Configure the Time Stamp TSEDGE and Enable bits */
00308   hrtc->Instance->CR = (uint32_t)tmpreg;
00309
00310   /* Enable the write protection for RTC registers */
00311   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00312
00313   hrtc->State = HAL_RTC_STATE_READY;
00314
00315   /* Process Unlocked */
00316   __HAL_UNLOCK(hrtc);
00317
00318   return HAL_OK;
00319 }
00320
00321 /**
00322   * @brief  Set Internal TimeStamp.
00323   * @note   This API must be called before enabling the internal TimeStamp feature.
00324   * @param  hrtc RTC handle
00325   * @retval HAL status
00326   */
00327 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00328 {
00329   /* Process Locked */
00330   __HAL_LOCK(hrtc);
00331
00332   hrtc->State = HAL_RTC_STATE_BUSY;
00333
00334   /* Disable the write protection for RTC registers */
00335   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00336
00337   /* Configure the internal Time Stamp Enable bits */
00338   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00339
00340   /* Enable the write protection for RTC registers */
00341   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00342
00343   /* Change RTC state */
00344   hrtc->State = HAL_RTC_STATE_READY;
00345
00346   /* Process Unlocked */
00347   __HAL_UNLOCK(hrtc);
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Deactivate Internal TimeStamp.
00354   * @param  hrtc RTC handle
00355   * @retval HAL status
00356   */
00357 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00358 {
00359   /* Process Locked */
00360   __HAL_LOCK(hrtc);
00361
00362   hrtc->State = HAL_RTC_STATE_BUSY;
00363
00364   /* Disable the write protection for RTC registers */
00365   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00366
00367   /* Configure the internal Time Stamp Enable bits */
00368   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00369
00370   /* Enable the write protection for RTC registers */
00371   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00372
00373   hrtc->State = HAL_RTC_STATE_READY;
00374
00375   /* Process Unlocked */
00376   __HAL_UNLOCK(hrtc);
00377
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @brief  Get the RTC TimeStamp value.
00383   * @param  hrtc RTC handle
00384   * @param  sTimeStamp Pointer to Time structure
00385   * @param  sTimeStampDate Pointer to Date structure
00386   * @param  Format specifies the format of the entered parameters.
00387   *          This parameter can be one of the following values:
00388   *             @arg RTC_FORMAT_BIN: Binary data format
00389   *             @arg RTC_FORMAT_BCD: BCD data format
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
00393 {
00394   uint32_t tmptime;
00395   uint32_t tmpdate;
00396
00397   /* Check the parameters */
00398   assert_param(IS_RTC_FORMAT(Format));
00399
00400   /* Get the TimeStamp time and date registers values */
00401   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00402   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00403
00404   /* Fill the Time structure fields with the read parameters */
00405   sTimeStamp->Hours      = (uint8_t)((tmptime & (RTC_TSTR_HT  | RTC_TSTR_HU))  >> RTC_TSTR_HU_Pos);
00406   sTimeStamp->Minutes    = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
00407   sTimeStamp->Seconds    = (uint8_t)((tmptime & (RTC_TSTR_ST  | RTC_TSTR_SU))  >> RTC_TSTR_SU_Pos);
00408   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM))                 >> RTC_TSTR_PM_Pos);
00409   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00410
00411   /* Fill the Date structure fields with the read parameters */
00412   sTimeStampDate->Year    = 0U;
00413   sTimeStampDate->Month   = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
00414   sTimeStampDate->Date    = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos);
00415   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU))              >> RTC_TSDR_WDU_Pos);
00416
00417   /* Check the input parameters format */
00418   if (Format == RTC_FORMAT_BIN)
00419   {
00420     /* Convert the TimeStamp structure parameters to Binary format */
00421     sTimeStamp->Hours   = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00422     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00423     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00424
00425     /* Convert the DateTimeStamp structure parameters to Binary format */
00426     sTimeStampDate->Month   = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00427     sTimeStampDate->Date    = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00428     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00429   }
00430
00431   /* Clear the TIMESTAMP Flags */
00432   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00433   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00434
00435   return HAL_OK;
00436 }
00437
00438 /**
00439   * @}
00440   */
00441
00442 /** @addtogroup RTCEx_Exported_Functions_Group5
00443   * @brief      Extended RTC Tamper functions
00444   *
00445 @verbatim
00446  ==============================================================================
00447                         ##### Tamper functions #####
00448  ==============================================================================
00449  [..]
00450   (+) Before calling any tamper or internal tamper function, you have to call first
00451       HAL_RTC_Init() function.
00452   (+) In that ine you can select to output tamper event on RTC pin.
00453  [..]
00454   (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
00455       or Level according to the Tamper filter (if equal to 0 Edge else Level)
00456       value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
00457       Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
00458       You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00459   (+) The default configuration of the Tamper erases the backup registers. To avoid
00460       erase, enable the NoErase field on the TAMP_TAMPCR register.
00461  [..]
00462   (+) Enable Internal Tamper and configure it with interrupt, timestamp using
00463       the HAL_RTCEx_SetInternalTamper() function.
00464
00465 @endverbatim
00466 * @{
00467 */
00468
00469 #if defined(TAMP_CR1_TAMP1E)
00470 /**
00471   * @brief  Set Tamper
00472   * @param  hrtc RTC handle
00473   * @param  sTamper Pointer to Tamper Structure.
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper)
00477 {
00478   uint32_t tmpreg;
00479
00480   /* Point on TAMPER registers base address */
00481   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET);
00482
00483   /* Check the parameters */
00484   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00485   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00486   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00487   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00488   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00489   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00490   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00491   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00492   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00493   assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
00494
00495   /* Configuration register 2 */
00496   tmpreg = tamp->CR2;
00497   tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
00498
00499   /* Configure the tamper trigger bit */
00500   if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
00501   {
00502     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
00503   }
00504
00505   /* Configure the tamper flags masking bit */
00506   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00507   {
00508     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
00509   }
00510
00511   /* Configure the tamper backup registers erasure bit */
00512   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00513   {
00514     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
00515   }
00516   tamp->CR2 = tmpreg;
00517
00518   /* Configure filtering parameters */
00519   tamp->FLTCR = (sTamper->Filter)            | (sTamper->SamplingFrequency) | \
00520                 (sTamper->PrechargeDuration) | (sTamper->TamperPullUp);
00521
00522   /* Configure Timestamp saving on tamper detection */
00523   if ((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection))
00524   {
00525     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00526     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
00527     hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection));
00528     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00529   }
00530
00531   /* Enable selected tamper */
00532   tamp->CR1 |= (sTamper->Tamper);
00533
00534   return HAL_OK;
00535 }
00536 #endif /* TAMP_CR1_TAMP1E */
00537 #if defined (RTC_TAMPCR_TAMP1E)
00538 /**
00539   * @brief  Set Tamper.
00540   * @note   By calling this API we disable the tamper interrupt for all tampers.
00541   * @param  hrtc RTC handle
00542   * @param  sTamper Pointer to Tamper Structure.
00543   * @retval HAL status
00544   */
00545 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper)
00546 {
00547   uint32_t tmpreg;
00548
00549   /* Check the parameters */
00550   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00551   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00552   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00553   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00554   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00555   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00556   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00557   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00558   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00559   assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
00560
00561   /* Process Locked */
00562   __HAL_LOCK(hrtc);
00563
00564   hrtc->State = HAL_RTC_STATE_BUSY;
00565
00566   /* Copy control register into temporary variable */
00567   tmpreg = hrtc->Instance->TAMPCR;
00568
00569   /* Enable selected tamper */
00570   tmpreg |= (sTamper->Tamper);
00571
00572   /* Configure the bit (located just next to the tamper enable bit) */
00573   if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
00574   {
00575     /* Set the tamper trigger bit */
00576     tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
00577   }
00578   else
00579   {
00580     /* Clear the tamper trigger bit */
00581     tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
00582   }
00583
00584   /* Configure the tamper backup registers erasure bit */
00585   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00586   {
00587 #if defined(RTC_TAMPCR_TAMP1E)
00588     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00589     {
00590       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE);
00591     }
00592 #endif /* RTC_TAMPCR_TAMP1E */
00593 #if defined(RTC_TAMPCR_TAMP2E)
00594     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00595     {
00596       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE);
00597     }
00598 #endif /* RTC_TAMPCR_TAMP2E */
00599 #if defined(RTC_TAMPCR_TAMP3E)
00600     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00601     {
00602       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE);
00603     }
00604 #endif /* RTC_TAMPCR_TAMP3E */
00605   }
00606   else
00607   {
00608 #if defined(RTC_TAMPCR_TAMP1E)
00609     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00610     {
00611       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE);
00612     }
00613 #endif /* RTC_TAMPCR_TAMP1E */
00614 #if defined(RTC_TAMPCR_TAMP2E)
00615     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00616     {
00617       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE);
00618     }
00619 #endif /* RTC_TAMPCR_TAMP2E */
00620 #if defined(RTC_TAMPCR_TAMP3E)
00621     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00622     {
00623       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE);
00624     }
00625 #endif /* RTC_TAMPCR_TAMP3E */
00626   }
00627
00628   /* Configure the tamper flags masking bit */
00629   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00630   {
00631 #if defined(RTC_TAMPCR_TAMP1E)
00632     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00633     {
00634       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF);
00635     }
00636 #endif /* RTC_TAMPCR_TAMP1E */
00637 #if defined(RTC_TAMPCR_TAMP2E)
00638     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00639     {
00640       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF);
00641     }
00642 #endif /* RTC_TAMPCR_TAMP2E */
00643 #if defined(RTC_TAMPCR_TAMP3E)
00644     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00645     {
00646       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF);
00647     }
00648 #endif /* RTC_TAMPCR_TAMP3E */
00649   }
00650   else
00651   {
00652 #if defined(RTC_TAMPCR_TAMP1E)
00653     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00654     {
00655       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF);
00656     }
00657 #endif /* RTC_TAMPCR_TAMP1E */
00658 #if defined(RTC_TAMPCR_TAMP2E)
00659     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00660     {
00661       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF);
00662     }
00663 #endif /* RTC_TAMPCR_TAMP2E */
00664 #if defined(RTC_TAMPCR_TAMP3E)
00665     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00666     {
00667       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF);
00668     }
00669 #endif /* RTC_TAMPCR_TAMP3E */
00670   }
00671
00672   /* Clearing remaining fields before setting them */
00673   tmpreg &= ~(RTC_TAMPERFILTER_MASK            | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
00674               RTC_TAMPERPRECHARGEDURATION_MASK | RTC_TAMPER_PULLUP_MASK             | \
00675               RTC_TIMESTAMPONTAMPERDETECTION_MASK);
00676
00677   /* Set remaining parameters of desired configuration into temporary variable */
00678   tmpreg |= ((uint32_t)sTamper->Filter            | \
00679              (uint32_t)sTamper->SamplingFrequency | \
00680              (uint32_t)sTamper->PrechargeDuration | \
00681              (uint32_t)sTamper->TamperPullUp      | \
00682              (uint32_t)sTamper->TimeStampOnTamperDetection);
00683
00684   /* Copy desired configuration into configuration register */
00685   hrtc->Instance->TAMPCR = tmpreg;
00686
00687   hrtc->State = HAL_RTC_STATE_READY;
00688
00689   /* Process Unlocked */
00690   __HAL_UNLOCK(hrtc);
00691
00692   return HAL_OK;
00693 }
00694 #endif /* RTC_TAMPCR_TAMP1E */
00695
00696 #if defined(TAMP_CR1_TAMP1E)
00697 /**
00698   * @brief  Set Tamper with interrupt.
00699   * @param  hrtc RTC handle
00700   * @param  sTamper Pointer to Tamper Structure.
00701   * @retval HAL status
00702   */
00703 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper)
00704 {
00705   uint32_t tmpreg;
00706
00707   /* Point on TAMPER registers base address */
00708   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET);
00709
00710   /* Check the parameters */
00711   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00712   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00713   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00714   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00715   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00716   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00717   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00718   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00719   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00720   assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
00721
00722   /* Copy configuration register into temporary variable */
00723   tmpreg = tamp->CR2;
00724
00725   /* Clear the bits that are going to be configured and leave the others unchanged */
00726   tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
00727
00728   /* Configure the tamper trigger bit */
00729   if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
00730   {
00731     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
00732   }
00733
00734   /* Configure the tamper flags masking bit */
00735   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00736   {
00737     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
00738   }
00739
00740   /* Configure the tamper backup registers erasure bit */
00741   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00742   {
00743     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
00744   }
00745   tamp->CR2 = tmpreg;
00746
00747   /* Configure filtering parameters */
00748   tamp->FLTCR = (sTamper->Filter)            | (sTamper->SamplingFrequency) | \
00749                 (sTamper->PrechargeDuration) | (sTamper->TamperPullUp);
00750
00751   /* Configure Timestamp saving on tamper detection */
00752   if ((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection))
00753   {
00754     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00755     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
00756     hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection));
00757     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00758   }
00759
00760   /* Configure RTC Tamper Interrupt: EXTI configuration */
00761   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00762   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE();
00763
00764   /* Enable interrupt on selected tamper */
00765   tamp->IER |= sTamper->Tamper;
00766
00767   /* Enable selected tamper */
00768   tamp->CR1 |= sTamper->Tamper;
00769
00770   return HAL_OK;
00771 }
00772 #endif /* TAMP_CR1_TAMP1E */
00773 #if defined(RTC_TAMPCR_TAMP1E)
00774 /**
00775   * @brief  Set Tamper with interrupt.
00776   * @note   By calling this API we force the tamper interrupt for all tampers.
00777   * @param  hrtc RTC handle
00778   * @param  sTamper Pointer to Tamper Structure.
00779   * @retval HAL status
00780   */
00781 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper)
00782 {
00783   uint32_t tmpreg;
00784
00785   /* Check the parameters */
00786   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00787   assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
00788   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00789   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00790   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00791   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00792   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00793   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00794   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00795   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00796   assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
00797
00798   /* Process Locked */
00799   __HAL_LOCK(hrtc);
00800
00801   hrtc->State = HAL_RTC_STATE_BUSY;
00802
00803   /* Copy control register into temporary variable */
00804   tmpreg = hrtc->Instance->TAMPCR;
00805
00806   /* Enable selected tamper */
00807   tmpreg |= (sTamper->Tamper);
00808
00809   /* Configure the tamper trigger bit (located just next to the tamper enable bit) */
00810   if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
00811   {
00812     /* Set the tamper trigger bit */
00813     tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
00814   }
00815   else
00816   {
00817     /* Clear the tamper trigger bit */
00818     tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
00819   }
00820
00821   /* Configure the tamper backup registers erasure bit */
00822   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00823   {
00824 #if defined(RTC_TAMPCR_TAMP1E)
00825     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00826     {
00827       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE);
00828     }
00829 #endif /* RTC_TAMPCR_TAMP1E */
00830 #if defined(RTC_TAMPCR_TAMP2E)
00831     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00832     {
00833       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE);
00834     }
00835 #endif /* RTC_TAMPCR_TAMP2E */
00836 #if defined(RTC_TAMPCR_TAMP3E)
00837     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00838     {
00839       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE);
00840     }
00841 #endif /* RTC_TAMPCR_TAMP3E */
00842   }
00843   else
00844   {
00845 #if defined(RTC_TAMPCR_TAMP1E)
00846     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00847     {
00848       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE);
00849     }
00850 #endif /* RTC_TAMPCR_TAMP1E */
00851 #if defined(RTC_TAMPCR_TAMP2E)
00852     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00853     {
00854       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE);
00855     }
00856 #endif /* RTC_TAMPCR_TAMP2E */
00857 #if defined(RTC_TAMPCR_TAMP3E)
00858     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00859     {
00860       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE);
00861     }
00862 #endif /* RTC_TAMPCR_TAMP3E */
00863   }
00864
00865   /* Configure the tamper flags masking bit */
00866   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00867   {
00868 #if defined(RTC_TAMPCR_TAMP1E)
00869     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00870     {
00871       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF);
00872     }
00873 #endif /* RTC_TAMPCR_TAMP1E */
00874 #if defined(RTC_TAMPCR_TAMP2E)
00875     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00876     {
00877       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF);
00878     }
00879 #endif /* RTC_TAMPCR_TAMP2E */
00880 #if defined(RTC_TAMPCR_TAMP3E)
00881     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00882     {
00883       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF);
00884     }
00885 #endif /* RTC_TAMPCR_TAMP3E */
00886   }
00887   else
00888   {
00889 #if defined(RTC_TAMPCR_TAMP1E)
00890     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00891     {
00892       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF);
00893     }
00894 #endif /* RTC_TAMPCR_TAMP1E */
00895 #if defined(RTC_TAMPCR_TAMP2E)
00896     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00897     {
00898       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF);
00899     }
00900 #endif /* RTC_TAMPCR_TAMP2E */
00901 #if defined(RTC_TAMPCR_TAMP3E)
00902     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00903     {
00904       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF);
00905     }
00906 #endif /* RTC_TAMPCR_TAMP3E */
00907   }
00908
00909   /* Clearing remaining fields before setting them */
00910   tmpreg &= ~(RTC_TAMPERFILTER_MASK            | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
00911               RTC_TAMPERPRECHARGEDURATION_MASK | RTC_TAMPER_PULLUP_MASK             | \
00912               RTC_TIMESTAMPONTAMPERDETECTION_MASK);
00913
00914   /* Set remaining parameters of desired configuration into temporary variable */
00915   tmpreg |= ((uint32_t)sTamper->Filter            | \
00916              (uint32_t)sTamper->SamplingFrequency | \
00917              (uint32_t)sTamper->PrechargeDuration | \
00918              (uint32_t)sTamper->TamperPullUp      | \
00919              (uint32_t)sTamper->TimeStampOnTamperDetection);
00920
00921   /* Enable interrupt on selected tamper */
00922   tmpreg |= (uint32_t)sTamper->Interrupt;
00923
00924   /* Copy desired configuration into configuration register */
00925   hrtc->Instance->TAMPCR = tmpreg;
00926
00927 #if !defined(DUAL_CORE)
00928   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00929   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00930 #endif
00931
00932   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00933
00934   hrtc->State = HAL_RTC_STATE_READY;
00935
00936   /* Process Unlocked */
00937   __HAL_UNLOCK(hrtc);
00938
00939   return HAL_OK;
00940 }
00941 #endif /* RTC_TAMPCR_TAMP1E */
00942
00943 #if defined(TAMP_CR1_TAMP1E)
00944 /**
00945   * @brief  Deactivate Tamper.
00946   * @param  hrtc RTC handle
00947   * @param  Tamper Selected tamper pin.
00948   *         This parameter can be a combination of the following values:
00949   *         @arg RTC_TAMPER_1
00950   *         @arg RTC_TAMPER_2
00951   * @retval HAL status
00952   */
00953 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t Tamper)
00954 {
00955   /* Point on TAMPER registers base address */
00956   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET);
00957
00958   assert_param(IS_RTC_TAMPER(Tamper));
00959
00960   /* Disable the selected Tamper pin */
00961   tamp->CR1 &= ~Tamper;
00962
00963   /* Disable the selected Tamper interrupt */
00964   tamp->IER &= ~Tamper;
00965
00966   /* Clear the selected tamper flags in SR register by setting corresponding bits in SCR register */
00967   tamp->SCR = Tamper;
00968
00969   /* Clear the selected tamper configuration (trigger, mask flag, and no-erase) */
00970   tamp->CR2 &= ~((Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
00971
00972   return HAL_OK;
00973 }
00974 #endif /* TAMP_CR1_TAMP1E */
00975 #if defined(RTC_TAMPCR_TAMP1E)
00976 /**
00977   * @brief  Deactivate Tamper.
00978   * @param  hrtc RTC handle
00979   * @param  Tamper Selected tamper pin.
00980   *         This parameter can be any combination of the following values:
00981   *         @arg RTC_TAMPER_1
00982   *         @arg RTC_TAMPER_2
00983   *         @arg RTC_TAMPER_3
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t Tamper)
00987 {
00988   assert_param(IS_RTC_TAMPER(Tamper));
00989
00990   /* Process Locked */
00991   __HAL_LOCK(hrtc);
00992
00993   hrtc->State = HAL_RTC_STATE_BUSY;
00994
00995   /* Disable the selected Tamper pin */
00996   hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
00997
00998   /* Disable the selected Tamper interrupt */
00999 #if defined(RTC_TAMPCR_TAMP1E)
01000   if ((Tamper & RTC_TAMPER_1) != 0U)
01001   {
01002     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
01003   }
01004 #endif /* RTC_TAMPCR_TAMP1E */
01005 #if defined(RTC_TAMPCR_TAMP2E)
01006   if ((Tamper & RTC_TAMPER_2) != 0U)
01007   {
01008     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
01009   }
01010 #endif /* RTC_TAMPCR_TAMP2E */
01011 #if defined(RTC_TAMPCR_TAMP3E)
01012   if ((Tamper & RTC_TAMPER_3) != 0U)
01013   {
01014     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
01015   }
01016 #endif /* RTC_TAMPCR_TAMP3E */
01017
01018   hrtc->State = HAL_RTC_STATE_READY;
01019
01020   /* Process Unlocked */
01021   __HAL_UNLOCK(hrtc);
01022
01023   return HAL_OK;
01024 }
01025 #endif /* RTC_TAMPCR_TAMP1E */
01026
01027 #if defined(TAMP_CR1_ITAMP1E)
01028 /**
01029   * @brief  Set Internal Tamper
01030   * @param  hrtc RTC handle
01031   * @param  sIntTamper Pointer to Internal Tamper Structure.
01032   * @retval HAL status
01033   */
01034 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
01035 {
01036   /* Check the parameters */
01037   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01038   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01039
01040   /* Time-Stamp on internal tamper */
01041   if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
01042   {
01043     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01044     MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
01045     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01046   }
01047
01048   /* Control register 1 */
01049   SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
01050
01051   return HAL_OK;
01052 }
01053
01054 /**
01055   * @brief  Set Internal Tamper in interrupt mode
01056   * @param  hrtc RTC handle
01057   * @param  sIntTamper Pointer to Internal Tamper Structure.
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
01061 {
01062   /* Check the parameters */
01063   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01064   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01065
01066   /* Time-stamp on internal tamper */
01067   if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
01068   {
01069     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01070     MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
01071     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01072   }
01073
01074   /* RTC Tamper Interrupt Configuration: EXTI configuration */
01075   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
01076   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE();
01077   /* Interrupt enable register */
01078   SET_BIT(TAMP->IER, sIntTamper->IntTamper);
01079
01080   /* Control register 1 */
01081   SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
01082
01083   return HAL_OK;
01084 }
01085
01086 /**
01087   * @brief  Deactivate Internal Tamper.
01088   * @param  hrtc RTC handle
01089   * @param  IntTamper Selected internal tamper event.
01090   *          This parameter can be any combination of existing internal tampers.
01091   * @retval HAL status
01092   */
01093 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
01094 {
01095   UNUSED(hrtc);
01096   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01097
01098   /* Disable the selected Tamper pin */
01099   CLEAR_BIT(TAMP->CR1, IntTamper);
01100
01101   /* Clear internal tamper interrupt mode configuration */
01102   CLEAR_BIT(TAMP->IER, IntTamper);
01103
01104   /* Clear internal tamper interrupt */
01105   WRITE_REG(TAMP->SCR, IntTamper);
01106
01107   return HAL_OK;
01108 }
01109 #endif /* TAMP_CR1_ITAMP1E */
01110
01111 #if defined(TAMP_ATCR1_TAMP1AM)
01112 /**
01113   * @brief  Set all active Tampers at the same time.
01114   * @param  hrtc RTC handle
01115   * @param  sAllTamper Pointer to active Tamper Structure.
01116   * @retval HAL status
01117   */
01118 HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper)
01119 {
01120   uint32_t IER, CR1, CR2, ATCR1, CR, i, tickstart;
01121
01122 #ifdef  USE_FULL_ASSERT
01123   for (i = 0; i < RTC_TAMP_NB; i++)
01124   {
01125     assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase));
01126     assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag));
01127     /* Mask flag only supported by TAMPER 1, 2 and 3 */
01128     assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3)));
01129   }
01130   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection));
01131 #endif /* #ifdef  USE_FULL_ASSERT */
01132
01133   /* Active Tampers must not be already enabled */
01134   if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U)
01135   {
01136     /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers and try again */
01137     return HAL_ERROR;
01138   }
01139
01140   /* Set TimeStamp on tamper detection */
01141   CR = READ_REG(RTC->CR);
01142   if ((CR & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection))
01143   {
01144     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01145     MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection);
01146     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01147   }
01148
01149   CR1 = READ_REG(TAMP->CR1);
01150   CR2 = READ_REG(TAMP->CR2);
01151   IER = READ_REG(TAMP->IER);
01152
01153   /* Set common parameters */
01154   ATCR1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) | sAllTamper->ActiveAsyncPrescaler);
01155
01156   /* Set specific parameters for each active tamper inputs if enable */
01157   for (i = 0; i < RTC_TAMP_NB; i++)
01158   {
01159     if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE)
01160     {
01161       CR1 |= (TAMP_CR1_TAMP1E << i);
01162       ATCR1 |= (TAMP_ATCR1_TAMP1AM << i);
01163
01164       if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE)
01165       {
01166         /* RTC Tamper Interrupt Configuration: EXTI configuration */
01167         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
01168         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
01169
01170         /* Interrupt enable register */
01171         IER |= (TAMP_IER_TAMP1IE << i);
01172       }
01173
01174       if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
01175       {
01176         CR2 |= (TAMP_CR2_TAMP1MSK << i);
01177       }
01178
01179       if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
01180       {
01181         CR2 |= (TAMP_CR2_TAMP1NOERASE << i);
01182       }
01183
01184       /* Set ATOSHARE and configure ATOSELx[] in case of output sharing */
01185       if (sAllTamper->TampInput[i].Output != i)
01186       {
01187         ATCR1 |= TAMP_ATCR1_ATOSHARE;
01188         ATCR1 |= sAllTamper->TampInput[i].Output << ((2u * i) + TAMP_ATCR1_ATOSEL1_Pos);
01189       }
01190     }
01191   }
01192
01193   WRITE_REG(TAMP->IER, IER);
01194   WRITE_REG(TAMP->IER, IER);
01195   WRITE_REG(TAMP->ATCR1, ATCR1);
01196 #if defined(TAMP_ATCR2_ATOSEL1)
01197   WRITE_REG(TAMP->ATCR2, ATCR2);
01198 #endif /* TAMP_ATCR2_ATOSEL1 */
01199   WRITE_REG(TAMP->CR2, CR2);
01200   WRITE_REG(TAMP->CR1, CR1);
01201
01202   /* Write seed */
01203   for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
01204   {
01205     WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]);
01206   }
01207
01208   /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
01209   tickstart = HAL_GetTick();
01210   while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0u)
01211   {
01212     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01213     {
01214       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01215       return HAL_TIMEOUT;
01216     }
01217   }
01218
01219   return HAL_OK;
01220 }
01221 #endif /* TAMP_ATCR1_TAMP1AM */
01222
01223 #if defined(TAMP_ATSEEDR_SEED)
01224 /**
01225   * @brief  Write a new seed. Active tamper must be enabled.
01226   * @param  hrtc RTC handle
01227   * @param  pSeed Pointer to active tamper seed values.
01228   * @retval HAL status
01229   */
01230 HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed)
01231 {
01232   uint32_t i, tickstart;
01233
01234   /* Active Tampers must be enabled */
01235   if (READ_BIT(TAMP->ATOR,  TAMP_ATOR_INITS) == 0U)
01236   {
01237     return HAL_ERROR;
01238   }
01239
01240   for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
01241   {
01242     WRITE_REG(TAMP->ATSEEDR, pSeed[i]);
01243   }
01244
01245   /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
01246   tickstart = HAL_GetTick();
01247   while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0U)
01248   {
01249     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01250     {
01251       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01252       return HAL_TIMEOUT;
01253     }
01254   }
01255
01256   return HAL_OK;
01257 }
01258 #endif /* TAMP_ATSEEDR_SEED */
01259
01260 #if defined(TAMP_ATCR1_TAMP1AM)
01261 /**
01262   * @brief  Deactivate all Active Tampers at the same time.
01263   * @param  hrtc RTC handle
01264   * @retval HAL status
01265   */
01266 HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc)
01267 {
01268   /* Get Active tampers */
01269   uint32_t ATamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL);
01270
01271   UNUSED(hrtc);
01272   /* Disable all actives tampers but not passives tampers */
01273   CLEAR_BIT(TAMP->CR1, ATamp_mask);
01274   /* Disable no erase and mask */
01275   CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos)));
01276
01277   /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */
01278   WRITE_REG(TAMP->SCR, ATamp_mask);
01279
01280   /* Clear all active tampers interrupt mode configuration but not passives tampers */
01281   CLEAR_BIT(TAMP->IER, ATamp_mask);
01282
01283   CLEAR_BIT(TAMP->ATCR1, TAMP_ALL | TAMP_ATCR1_ATCKSEL | TAMP_ATCR1_ATPER | \
01284             TAMP_ATCR1_ATOSHARE | TAMP_ATCR1_FLTEN);
01285
01286 #if defined(TAMP_ATCR2_ATOSEL1)
01287   CLEAR_BIT(TAMP->ATCR2, TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 |
01288             TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8);
01289 #endif /* TAMP_ATCR2_ATOSEL1 */
01290
01291   return HAL_OK;
01292 }
01293 #endif /* TAMP_ATCR1_TAMP1AM */
01294
01295 /**
01296   * @}
01297   */
01298
01299 /** @addtogroup RTCEx_Exported_Functions_Group1
01300  *  @brief   RTC TimeStamp and Tamper functions
01301  *
01302 * @{
01303 */
01304
01305 /**
01306   * @brief  Handle TimeStamp interrupt request.
01307   * @param  hrtc RTC handle
01308   * @retval None
01309   */
01310 #if defined(RTC_MISR_TSMF)
01311 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
01312 {
01313
01314   /* Point on TAMPER registers base address */
01315   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET);
01316
01317   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
01318   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
01319
01320   if ((hrtc->Instance->MISR & RTC_MISR_TSMF) != 0u)
01321   {
01322 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01323     /* Call TimeStampEvent registered Callback */
01324     hrtc->TimeStampEventCallback(hrtc);
01325 #else
01326     HAL_RTCEx_TimeStampEventCallback(hrtc);
01327 #endif
01328     /* Not immediately clear flags because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/
01329     hrtc->Instance->SCR = RTC_SCR_CTSF;
01330   }
01331
01332   /* Get interrupt status */
01333   uint32_t tmp = tamp->MISR;
01334
01335   /* Immediately clear flags */
01336   tamp->SCR = tmp;
01337
01338 #if defined(TAMP_CR1_TAMP1E)
01339   /* Check Tamper1 status */
01340   if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
01341   {
01342 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01343     /* Call Tamper 1 Event registered Callback */
01344     hrtc->Tamper1EventCallback(hrtc);
01345 #else
01346     /* Tamper1 callback */
01347     HAL_RTCEx_Tamper1EventCallback(hrtc);
01348 #endif
01349   }
01350 #endif /* TAMP_CR1_TAMP1E */
01351
01352 #if defined(TAMP_CR1_TAMP2E)
01353   /* Check Tamper2 status */
01354   if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
01355   {
01356 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01357     /* Call Tamper 2 Event registered Callback */
01358     hrtc->Tamper2EventCallback(hrtc);
01359 #else
01360     /* Tamper2 callback */
01361     HAL_RTCEx_Tamper2EventCallback(hrtc);
01362 #endif
01363   }
01364 #endif /* TAMP_CR1_TAMP2E */
01365
01366 #if defined(TAMP_CR1_TAMP3E)
01367   /* Check Tamper3 status */
01368   if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
01369   {
01370 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01371     /* Call Tamper 3 Event registered Callback */
01372     hrtc->Tamper3EventCallback(hrtc);
01373 #else
01374     /* Tamper3 callback */
01375     HAL_RTCEx_Tamper3EventCallback(hrtc);
01376 #endif
01377   }
01378 #endif /* TAMP_CR1_TAMP3E */
01379
01380 #if defined(TAMP_CR1_ITAMP1E)
01381   /* Check Internal Tamper status */
01382   if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
01383   {
01384 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01385     /* Call Internal Tamper Event registered callback */
01386     hrtc->InternalTamper1EventCallback(hrtc);
01387 #else
01388     /* Call Internal Tamper Event by-default callback */
01389     HAL_RTCEx_InternalTamper1EventCallback(hrtc);
01390 #endif
01391   }
01392 #endif /* TAMP_CR1_ITAMP1E */
01393
01394 #if defined(TAMP_CR1_ITAMP2E)
01395   /* Check Internal Tamper status */
01396   if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
01397   {
01398 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01399     /* Call Internal Tamper Event registered callback */
01400     hrtc->InternalTamper2EventCallback(hrtc);
01401 #else
01402     /* Call Internal Tamper Event by-default callback */
01403     HAL_RTCEx_InternalTamper2EventCallback(hrtc);
01404 #endif
01405   }
01406 #endif /* TAMP_CR1_ITAMP2E */
01407
01408 #if defined(TAMP_CR1_ITAMP3E)
01409   /* Check Internal Tamper status */
01410   if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
01411   {
01412 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01413     /* Call Internal Tamper Event registered callback */
01414     hrtc->InternalTamper3EventCallback(hrtc);
01415 #else
01416     /* Call Internal Tamper Event by-default callback */
01417     HAL_RTCEx_InternalTamper3EventCallback(hrtc);
01418 #endif
01419   }
01420 #endif /* TAMP_CR1_ITAMP3E */
01421
01422 #if defined(TAMP_CR1_ITAMP4E)
01423   /* Check Internal Tamper status */
01424   if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4)
01425   {
01426 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01427     /* Call Internal Tamper Event registered callback */
01428     hrtc->InternalTamper4EventCallback(hrtc);
01429 #else
01430     /* Call Internal Tamper Event by-default callback */
01431     HAL_RTCEx_InternalTamper4EventCallback(hrtc);
01432 #endif
01433   }
01434 #endif /* TAMP_CR1_ITAMP4E */
01435
01436 #if defined(TAMP_CR1_ITAMP5E)
01437   /* Check Internal Tamper status */
01438   if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
01439   {
01440 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01441     /* Call Internal Tamper Event registered callback */
01442     hrtc->InternalTamper5EventCallback(hrtc);
01443 #else
01444     /* Call Internal Tamper Event by-default callback */
01445     HAL_RTCEx_InternalTamper5EventCallback(hrtc);
01446 #endif
01447   }
01448 #endif /* TAMP_CR1_ITAMP5E */
01449
01450 #if defined(TAMP_CR1_ITAMP6E)
01451   /* Check Internal Tamper status */
01452   if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
01453   {
01454 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01455     /* Call Internal Tamper Event registered callback */
01456     hrtc->InternalTamper6EventCallback(hrtc);
01457 #else
01458     /* Call Internal Tamper Event by-default callback */
01459     HAL_RTCEx_InternalTamper6EventCallback(hrtc);
01460 #endif
01461   }
01462 #endif /* TAMP_CR1_ITAMP6E */
01463
01464 #if defined(TAMP_CR1_ITAMP8E)
01465   /* Check Internal Tamper status */
01466   if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
01467   {
01468 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01469     /* Call Internal Tamper Event registered callback */
01470     hrtc->InternalTamper8EventCallback(hrtc);
01471 #else
01472     /* Call Internal Tamper Event by-default callback */
01473     HAL_RTCEx_InternalTamper8EventCallback(hrtc);
01474 #endif
01475   }
01476 #endif /* TAMP_CR1_ITAMP8E */
01477
01478   /* Change RTC state */
01479   hrtc->State = HAL_RTC_STATE_READY;
01480 }
01481 #endif /* RTC_MISR_TSMF */
01482 #if defined(RTC_ISR_TSF)
01483 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
01484 {
01485   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
01486 #if defined(DUAL_CORE)
01487   if (HAL_GetCurrentCPUID() == CM7_CPUID)
01488   {
01489     __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
01490   }
01491   else
01492   {
01493     __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG();
01494   }
01495 #else  /* SINGLE_CORE */
01496   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
01497 #endif /* DUAL_CORE */
01498
01499   /* Get the TimeStamp interrupt source enable status */
01500   if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
01501   {
01502     /* Get the pending status of the TIMESTAMP Interrupt */
01503     if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
01504     {
01505       /* TIMESTAMP callback */
01506 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01507       hrtc->TimeStampEventCallback(hrtc);
01508 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01509       HAL_RTCEx_TimeStampEventCallback(hrtc);
01510 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01511
01512       /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */
01513       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
01514     }
01515   }
01516
01517 #if defined(RTC_TAMPCR_TAMP1E)
01518   /* Get the Tamper1 interrupt source enable status */
01519   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
01520   {
01521     /* Get the pending status of the Tamper1 Interrupt */
01522     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
01523     {
01524       /* Clear the Tamper1 interrupt pending bit */
01525       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
01526
01527       /* Tamper1 callback */
01528 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01529       hrtc->Tamper1EventCallback(hrtc);
01530 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01531       HAL_RTCEx_Tamper1EventCallback(hrtc);
01532 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01533     }
01534   }
01535 #endif /* RTC_TAMPCR_TAMP1E */
01536
01537 #if defined(RTC_TAMPCR_TAMP2E)
01538   /* Get the Tamper2 interrupt source enable status */
01539   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U)
01540   {
01541     /* Get the pending status of the Tamper2 Interrupt */
01542     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
01543     {
01544       /* Clear the Tamper2 interrupt pending bit */
01545       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
01546
01547       /* Tamper2 callback */
01548 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01549       hrtc->Tamper2EventCallback(hrtc);
01550 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01551       HAL_RTCEx_Tamper2EventCallback(hrtc);
01552 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01553     }
01554   }
01555 #endif /* RTC_TAMPCR_TAMP2E */
01556
01557 #if defined(RTC_TAMPCR_TAMP3E)
01558   /* Get the Tamper3 interrupts source enable status */
01559   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U)
01560   {
01561     /* Get the pending status of the Tamper3 Interrupt */
01562     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
01563     {
01564       /* Clear the Tamper3 interrupt pending bit */
01565       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
01566
01567       /* Tamper3 callback */
01568 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01569       hrtc->Tamper3EventCallback(hrtc);
01570 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01571       HAL_RTCEx_Tamper3EventCallback(hrtc);
01572 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
01573     }
01574   }
01575 #endif /* RTC_TAMPCR_TAMP3E */
01576
01577   /* Change RTC state */
01578   hrtc->State = HAL_RTC_STATE_READY;
01579 }
01580 #endif /* RTC_ISR_TSF */
01581
01582 /**
01583   * @brief  TimeStamp callback.
01584   * @param  hrtc RTC handle
01585   * @retval None
01586   */
01587 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
01588 {
01589   /* Prevent unused argument(s) compilation warning */
01590   UNUSED(hrtc);
01591
01592   /* NOTE : This function should not be modified, when the callback is needed,
01593             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
01594   */
01595 }
01596
01597 /**
01598   * @}
01599   */
01600
01601 /** @addtogroup RTCEx_Exported_Functions_Group5
01602   * @brief      Extended RTC Tamper functions
01603   *
01604 * @{
01605 */
01606
01607 #if defined(RTC_TAMPER_1)
01608 /**
01609   * @brief  Tamper 1 callback.
01610   * @param  hrtc RTC handle
01611   * @retval None
01612   */
01613 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef * hrtc)
01614 {
01615   /* Prevent unused argument(s) compilation warning */
01616   UNUSED(hrtc);
01617
01618   /* NOTE : This function should not be modified, when the callback is needed,
01619             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
01620    */
01621 }
01622 #endif /* RTC_TAMPER_1 */
01623
01624 #if defined(RTC_TAMPER_2)
01625 /**
01626   * @brief  Tamper 2 callback.
01627   * @param  hrtc RTC handle
01628   * @retval None
01629   */
01630 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef * hrtc)
01631 {
01632   /* Prevent unused argument(s) compilation warning */
01633   UNUSED(hrtc);
01634
01635   /* NOTE : This function should not be modified, when the callback is needed,
01636             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
01637    */
01638 }
01639 #endif /* RTC_TAMPER_2 */
01640
01641 #if defined(RTC_TAMPER_3)
01642 /**
01643   * @brief  Tamper 3 callback.
01644   * @param  hrtc RTC handle
01645   * @retval None
01646   */
01647 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef * hrtc)
01648 {
01649   /* Prevent unused argument(s) compilation warning */
01650   UNUSED(hrtc);
01651
01652   /* NOTE : This function should not be modified, when the callback is needed,
01653             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
01654    */
01655 }
01656 #endif /* RTC_TAMPER_3 */
01657
01658 /**
01659   * @brief  Internal Tamper 1 callback.
01660   * @param  hrtc RTC handle
01661   * @retval None
01662   */
01663 __weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc)
01664 {
01665   /* Prevent unused argument(s) compilation warning */
01666   UNUSED(hrtc);
01667
01668   /* NOTE : This function should not be modified, when the callback is needed,
01669             the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file
01670    */
01671 }
01672
01673 /**
01674   * @brief  Internal Tamper 2 callback.
01675   * @param  hrtc RTC handle
01676   * @retval None
01677   */
01678 __weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc)
01679 {
01680   /* Prevent unused argument(s) compilation warning */
01681   UNUSED(hrtc);
01682
01683   /* NOTE : This function should not be modified, when the callback is needed,
01684             the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file
01685    */
01686 }
01687
01688 /**
01689   * @brief  Internal Tamper 3 callback.
01690   * @param  hrtc RTC handle
01691   * @retval None
01692   */
01693 __weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc)
01694 {
01695   /* Prevent unused argument(s) compilation warning */
01696   UNUSED(hrtc);
01697
01698   /* NOTE : This function should not be modified, when the callback is needed,
01699             the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file
01700    */
01701 }
01702
01703 /**
01704   * @brief  Internal Tamper 4 callback.
01705   * @param  hrtc RTC handle
01706   * @retval None
01707   */
01708 __weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc)
01709 {
01710   /* Prevent unused argument(s) compilation warning */
01711   UNUSED(hrtc);
01712
01713   /* NOTE : This function should not be modified, when the callback is needed,
01714             the HAL_RTCEx_InternalTamper4EventCallback could be implemented in the user file
01715    */
01716 }
01717
01718 /**
01719   * @brief  Internal Tamper 5 callback.
01720   * @param  hrtc RTC handle
01721   * @retval None
01722   */
01723 __weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc)
01724 {
01725   /* Prevent unused argument(s) compilation warning */
01726   UNUSED(hrtc);
01727
01728   /* NOTE : This function should not be modified, when the callback is needed,
01729             the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file
01730    */
01731 }
01732
01733 /**
01734   * @brief  Internal Tamper 6 callback.
01735   * @param  hrtc RTC handle
01736   * @retval None
01737   */
01738 __weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc)
01739 {
01740   /* Prevent unused argument(s) compilation warning */
01741   UNUSED(hrtc);
01742
01743   /* NOTE : This function should not be modified, when the callback is needed,
01744             the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file
01745    */
01746 }
01747
01748 /**
01749   * @brief  Internal Tamper 8 callback.
01750   * @param  hrtc RTC handle
01751   * @retval None
01752   */
01753 __weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc)
01754 {
01755   /* Prevent unused argument(s) compilation warning */
01756   UNUSED(hrtc);
01757
01758   /* NOTE : This function should not be modified, when the callback is needed,
01759             the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file
01760    */
01761 }
01762 /**
01763   * @}
01764   */
01765
01766 /** @addtogroup RTCEx_Exported_Functions_Group1
01767  *  @brief   RTC TimeStamp and Tamper functions
01768  *
01769 * @{
01770 */
01771
01772 /**
01773   * @brief  Handle TimeStamp polling request.
01774   * @param  hrtc RTC handle
01775   * @param  Timeout Timeout duration
01776   * @retval HAL status
01777   */
01778 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01779 {
01780   uint32_t tickstart = HAL_GetTick();
01781
01782   while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
01783   {
01784     if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
01785     {
01786       /* Clear the TIMESTAMP OverRun Flag */
01787       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
01788
01789       /* Change TIMESTAMP state */
01790       hrtc->State = HAL_RTC_STATE_ERROR;
01791
01792       return HAL_ERROR;
01793     }
01794
01795     if (Timeout != HAL_MAX_DELAY)
01796     {
01797       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01798       {
01799         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01800         return HAL_TIMEOUT;
01801       }
01802     }
01803   }
01804
01805   /* Change RTC state */
01806   hrtc->State = HAL_RTC_STATE_READY;
01807
01808   return HAL_OK;
01809 }
01810
01811 /**
01812   * @}
01813   */
01814
01815 /** @addtogroup RTCEx_Exported_Functions_Group5
01816   * @brief      Extended RTC Tamper functions
01817   *
01818 * @{
01819 */
01820
01821 #if defined(RTC_TAMPER_1)
01822 /**
01823   * @brief  Handle Tamper1 Polling.
01824   * @param  hrtc RTC handle
01825   * @param  Timeout Timeout duration
01826   * @retval HAL status
01827   */
01828 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef * hrtc, uint32_t Timeout)
01829 {
01830   uint32_t tickstart = HAL_GetTick();
01831
01832   /* Get the status of the Interrupt */
01833   while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U)
01834   {
01835     if (Timeout != HAL_MAX_DELAY)
01836     {
01837       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01838       {
01839         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01840         return HAL_TIMEOUT;
01841       }
01842     }
01843   }
01844
01845   /* Clear the Tamper Flag */
01846   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
01847
01848   /* Change RTC state */
01849   hrtc->State = HAL_RTC_STATE_READY;
01850
01851   return HAL_OK;
01852 }
01853 #endif /* RTC_TAMPER_1 */
01854
01855 #if defined(RTC_TAMPER_2)
01856 /**
01857   * @brief  Handle Tamper2 Polling.
01858   * @param  hrtc RTC handle
01859   * @param  Timeout Timeout duration
01860   * @retval HAL status
01861   */
01862 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef * hrtc, uint32_t Timeout)
01863 {
01864   uint32_t tickstart = HAL_GetTick();
01865
01866   /* Get the status of the Interrupt */
01867   while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
01868   {
01869     if (Timeout != HAL_MAX_DELAY)
01870     {
01871       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01872       {
01873         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01874         return HAL_TIMEOUT;
01875       }
01876     }
01877   }
01878
01879   /* Clear the Tamper Flag */
01880   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
01881
01882   /* Change RTC state */
01883   hrtc->State = HAL_RTC_STATE_READY;
01884
01885   return HAL_OK;
01886 }
01887 #endif /* RTC_TAMPER_2 */
01888
01889 #if defined(RTC_TAMPER_3)
01890 /**
01891   * @brief  Handle Tamper3 Polling.
01892   * @param  hrtc RTC handle
01893   * @param  Timeout Timeout duration
01894   * @retval HAL status
01895   */
01896 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef * hrtc, uint32_t Timeout)
01897 {
01898   uint32_t tickstart = HAL_GetTick();
01899
01900   /* Get the status of the Interrupt */
01901   while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U)
01902   {
01903     if (Timeout != HAL_MAX_DELAY)
01904     {
01905       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01906       {
01907         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01908         return HAL_TIMEOUT;
01909       }
01910     }
01911   }
01912
01913   /* Clear the Tamper Flag */
01914   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
01915
01916   /* Change RTC state */
01917   hrtc->State = HAL_RTC_STATE_READY;
01918
01919   return HAL_OK;
01920 }
01921 #endif /* RTC_TAMPER_3 */
01922
01923 #if defined(TAMP_CR1_ITAMP1E)
01924 /**
01925   * @brief  Internal Tamper event polling.
01926   * @param  hrtc RTC handle
01927   * @param  IntTamper selected tamper.
01928   *          This parameter can be any combination of existing internal tampers.
01929   * @param  Timeout Timeout duration
01930   * @retval HAL status
01931   */
01932 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
01933 {
01934   UNUSED(hrtc);
01935   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01936
01937   uint32_t tickstart = HAL_GetTick();
01938
01939   /* Get the status of the Interrupt */
01940   while (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
01941   {
01942     if (Timeout != HAL_MAX_DELAY)
01943     {
01944       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01945       {
01946         return HAL_TIMEOUT;
01947       }
01948     }
01949   }
01950
01951   /* Clear the Tamper Flag */
01952   WRITE_REG(TAMP->SCR, IntTamper);
01953
01954   return HAL_OK;
01955 }
01956 #endif /* TAMP_CR1_ITAMP1E */
01957
01958 /**
01959   * @}
01960   */
01961
01962 /** @addtogroup RTCEx_Exported_Functions_Group2
01963   * @brief    RTC Wake-up functions
01964   *
01965 @verbatim
01966  ===============================================================================
01967                         ##### RTC Wake-up functions #####
01968  ===============================================================================
01969
01970  [..] This section provides functions allowing to configure Wake-up feature
01971
01972 @endverbatim
01973   * @{
01974   */
01975
01976 /**
01977   * @brief  Set wake up timer.
01978   * @param  hrtc RTC handle
01979   * @param  WakeUpCounter Wake up counter
01980   * @param  WakeUpClock Wake up clock
01981   * @retval HAL status
01982   */
01983 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01984 {
01985   uint32_t tickstart;
01986
01987   /* Check the parameters */
01988   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01989   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01990
01991   /* Process Locked */
01992   __HAL_LOCK(hrtc);
01993
01994   hrtc->State = HAL_RTC_STATE_BUSY;
01995
01996   /* Disable the write protection for RTC registers */
01997   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01998
01999   /* Check RTC WUTWF flag is reset only when wake up timer enabled */
02000   if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
02001   {
02002     tickstart = HAL_GetTick();
02003
02004     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
02005   #if defined(RTC_ICSR_WUTWF)
02006     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) != 0U)
02007   #endif /* RTC_ICSR_WUTWF */
02008   #if defined(RTC_ISR_WUTWF)
02009     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
02010   #endif /* RTC_ISR_WUTWF */
02011     {
02012       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02013       {
02014         /* Enable the write protection for RTC registers */
02015         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02016
02017         hrtc->State = HAL_RTC_STATE_TIMEOUT;
02018
02019         /* Process Unlocked */
02020         __HAL_UNLOCK(hrtc);
02021
02022         return HAL_TIMEOUT;
02023       }
02024     }
02025   }
02026
02027   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
02028
02029   tickstart = HAL_GetTick();
02030
02031   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
02032   #if defined(RTC_ICSR_WUTWF)
02033     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
02034   #endif /* RTC_ICSR_WUTWF */
02035   #if defined(RTC_ISR_WUTWF)
02036     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
02037   #endif /* RTC_ISR_WUTWF */
02038   {
02039     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02040     {
02041       /* Enable the write protection for RTC registers */
02042       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02043
02044       hrtc->State = HAL_RTC_STATE_TIMEOUT;
02045
02046       /* Process Unlocked */
02047       __HAL_UNLOCK(hrtc);
02048
02049       return HAL_TIMEOUT;
02050     }
02051   }
02052
02053   /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */
02054   {
02055     uint32_t CR_tmp = hrtc->Instance->CR;
02056     CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL;
02057     CR_tmp |= (uint32_t)WakeUpClock;
02058     hrtc->Instance->CR = CR_tmp;
02059   }
02060
02061   /* Configure the Wakeup Timer counter */
02062   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
02063
02064   /* Enable the Wakeup Timer */
02065   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
02066
02067   /* Enable the write protection for RTC registers */
02068   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02069
02070   hrtc->State = HAL_RTC_STATE_READY;
02071
02072   /* Process Unlocked */
02073   __HAL_UNLOCK(hrtc);
02074
02075   return HAL_OK;
02076 }
02077
02078 /**
02079   * @brief  Set wake up timer with interrupt.
02080   * @param  hrtc RTC handle
02081   * @param  WakeUpCounter Wake up counter
02082   * @param  WakeUpClock Wake up clock
02083   * @retval HAL status
02084   */
02085 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
02086 {
02087   uint32_t tickstart;
02088
02089   /* Check the parameters */
02090   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
02091   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
02092
02093   /* Process Locked */
02094   __HAL_LOCK(hrtc);
02095
02096   hrtc->State = HAL_RTC_STATE_BUSY;
02097
02098   /* Disable the write protection for RTC registers */
02099   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02100
02101   /* Check RTC WUTWF flag is reset only when wake up timer enabled */
02102   if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
02103   {
02104     tickstart = HAL_GetTick();
02105
02106     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
02107   #if defined(RTC_ICSR_WUTWF)
02108     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) != 0U)
02109   #endif /* RTC_ICSR_WUTWF */
02110   #if defined(RTC_ISR_WUTWF)
02111     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
02112   #endif /* RTC_ISR_WUTWF */
02113     {
02114       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02115       {
02116         /* Enable the write protection for RTC registers */
02117         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02118
02119         hrtc->State = HAL_RTC_STATE_TIMEOUT;
02120
02121         /* Process Unlocked */
02122         __HAL_UNLOCK(hrtc);
02123
02124         return HAL_TIMEOUT;
02125       }
02126     }
02127   }
02128   /* Disable the Wake-Up timer */
02129   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
02130
02131   /* Clear flag Wake-Up */
02132   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
02133
02134   tickstart = HAL_GetTick();
02135
02136   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
02137   #if defined(RTC_ICSR_WUTWF)
02138     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
02139   #endif /* RTC_ICSR_WUTWF */
02140   #if defined(RTC_ISR_WUTWF)
02141     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
02142   #endif /* RTC_ISR_WUTWF */
02143   {
02144     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02145     {
02146       /* Enable the write protection for RTC registers */
02147       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02148
02149       hrtc->State = HAL_RTC_STATE_TIMEOUT;
02150
02151       /* Process Unlocked */
02152       __HAL_UNLOCK(hrtc);
02153
02154       return HAL_TIMEOUT;
02155     }
02156   }
02157
02158   /* Configure the Wakeup Timer counter */
02159   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
02160
02161   /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */
02162   {
02163     uint32_t CR_tmp = hrtc->Instance->CR;
02164     CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL;
02165     CR_tmp |= (uint32_t)WakeUpClock;
02166     hrtc->Instance->CR = CR_tmp;
02167   }
02168
02169 #if !defined(DUAL_CORE)
02170   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
02171   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
02172 #endif
02173
02174   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
02175
02176   /* Configure the Interrupt in the RTC_CR register */
02177   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
02178
02179   /* Enable the Wakeup Timer */
02180   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
02181
02182   /* Enable the write protection for RTC registers */
02183   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02184
02185   hrtc->State = HAL_RTC_STATE_READY;
02186
02187   /* Process Unlocked */
02188   __HAL_UNLOCK(hrtc);
02189
02190   return HAL_OK;
02191 }
02192
02193 /**
02194   * @brief  Deactivate wake up timer counter.
02195   * @param  hrtc RTC handle
02196   * @retval HAL status
02197   */
02198 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
02199 {
02200   uint32_t tickstart;
02201
02202   /* Process Locked */
02203   __HAL_LOCK(hrtc);
02204
02205   hrtc->State = HAL_RTC_STATE_BUSY;
02206
02207   /* Disable the write protection for RTC registers */
02208   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02209
02210   /* Disable the Wakeup Timer */
02211   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
02212
02213   /* In case of interrupt mode is used, the interrupt source must disabled */
02214   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
02215
02216   tickstart = HAL_GetTick();
02217   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
02218   #if defined(RTC_ICSR_WUTWF)
02219     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
02220   #endif /* RTC_ICSR_WUTWF */
02221   #if defined(RTC_ISR_WUTWF)
02222     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
02223   #endif /* RTC_ISR_WUTWF */
02224   {
02225     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02226     {
02227       /* Enable the write protection for RTC registers */
02228       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02229
02230       hrtc->State = HAL_RTC_STATE_TIMEOUT;
02231
02232       /* Process Unlocked */
02233       __HAL_UNLOCK(hrtc);
02234
02235       return HAL_TIMEOUT;
02236     }
02237   }
02238
02239   /* Enable the write protection for RTC registers */
02240   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02241
02242   hrtc->State = HAL_RTC_STATE_READY;
02243
02244   /* Process Unlocked */
02245   __HAL_UNLOCK(hrtc);
02246
02247   return HAL_OK;
02248 }
02249
02250 /**
02251   * @brief  Get wake up timer counter.
02252   * @param  hrtc RTC handle
02253   * @retval Counter value
02254   */
02255 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
02256 {
02257   /* Get the counter value */
02258   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
02259 }
02260
02261 /**
02262   * @brief  Handle Wake Up Timer interrupt request.
02263   * @param  hrtc RTC handle
02264   * @retval None
02265   */
02266 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
02267 {
02268   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
02269 #if defined(DUAL_CORE)
02270   if (HAL_GetCurrentCPUID() == CM7_CPUID)
02271   {
02272     __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
02273   }
02274   else
02275   {
02276     __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG();
02277   }
02278 #else  /* SINGLE_CORE */
02279   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
02280 #endif /* DUAL_CORE */
02281
02282 #if defined(RTC_MISR_WUTMF)
02283   /* Get the pending status of the WAKEUPTIMER Interrupt */
02284   if ((hrtc->Instance->MISR & RTC_MISR_WUTMF) != 0u)
02285   {
02286     /* Immediately clear flags */
02287     hrtc->Instance->SCR = RTC_SCR_CWUTF;
02288
02289     /* WAKEUPTIMER callback */
02290   #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
02291     /* Call WakeUpTimerEvent registered Callback */
02292     hrtc->WakeUpTimerEventCallback(hrtc);
02293   #else
02294     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
02295   #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
02296   }
02297 #endif /* RTC_MISR_WUTMF */
02298 #if defined(RTC_ISR_WUTF)
02299   /* Get the pending status of the WAKEUPTIMER Interrupt */
02300   if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
02301   {
02302     /* Clear the WAKEUPTIMER interrupt pending bit */
02303     __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
02304
02305     /* WAKEUPTIMER callback */
02306   #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
02307     /* Call WakeUpTimerEvent registered Callback */
02308     hrtc->WakeUpTimerEventCallback(hrtc);
02309   #else
02310     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
02311   #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
02312   }
02313 #endif /* RTC_ISR_WUTF */
02314
02315   /* Change RTC state */
02316   hrtc->State = HAL_RTC_STATE_READY;
02317 }
02318
02319 /**
02320   * @brief  Wake Up Timer callback.
02321   * @param  hrtc RTC handle
02322   * @retval None
02323   */
02324 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef * hrtc)
02325 {
02326   /* Prevent unused argument(s) compilation warning */
02327   UNUSED(hrtc);
02328
02329   /* NOTE : This function should not be modified, when the callback is needed,
02330             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
02331    */
02332 }
02333
02334
02335 /**
02336   * @brief  Handle Wake Up Timer Polling.
02337   * @param  hrtc RTC handle
02338   * @param  Timeout Timeout duration
02339   * @retval HAL status
02340   */
02341 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef * hrtc, uint32_t Timeout)
02342 {
02343   uint32_t tickstart = HAL_GetTick();
02344
02345   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
02346   {
02347     if (Timeout != HAL_MAX_DELAY)
02348     {
02349       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02350       {
02351         hrtc->State = HAL_RTC_STATE_TIMEOUT;
02352         return HAL_TIMEOUT;
02353       }
02354     }
02355   }
02356
02357   /* Clear the WAKEUPTIMER Flag */
02358   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
02359
02360   /* Change RTC state */
02361   hrtc->State = HAL_RTC_STATE_READY;
02362
02363   return HAL_OK;
02364 }
02365
02366 /**
02367   * @}
02368   */
02369
02370
02371 /** @addtogroup RTCEx_Exported_Functions_Group6
02372   * @brief      Extended RTC Backup register functions
02373   *
02374 @verbatim
02375  ===============================================================================
02376              ##### Extended RTC Backup register functions #####
02377  ===============================================================================
02378   [..]
02379    (+) Before calling any tamper or internal tamper function, you have to call first
02380        HAL_RTC_Init() function.
02381    (+) In that ine you can select to output tamper event on RTC pin.
02382   [..]
02383    This subsection provides functions allowing to
02384    (+) Write a data in a specified RTC Backup data register
02385    (+) Read a data in a specified RTC Backup data register
02386 @endverbatim
02387   * @{
02388   */
02389
02390
02391 /**
02392   * @brief  Write a data in a specified RTC Backup data register.
02393   * @param  hrtc RTC handle
02394   * @param  BackupRegister RTC Backup data Register number.
02395   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to
02396   *                                 specify the register.
02397   * @param  Data Data to be written in the specified Backup data register.
02398   * @retval None
02399   */
02400 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data)
02401 {
02402   uint32_t tmp;
02403
02404   /* Check the parameters */
02405   assert_param(IS_RTC_BKP(BackupRegister));
02406
02407   /* Point on address of first backup register */
02408 #if defined(TAMP_BKP0R)
02409   tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R);
02410 #endif /* TAMP_BKP0R */
02411 #if defined(RTC_BKP0R)
02412   tmp = (uint32_t) & (hrtc->Instance->BKP0R);
02413 #endif /* RTC_BKP0R */
02414
02415   tmp += (BackupRegister * 4U);
02416
02417   /* Write the specified register */
02418   *(__IO uint32_t *)tmp = (uint32_t)Data;
02419 }
02420
02421
02422 /**
02423   * @brief  Read data from the specified RTC Backup data Register.
02424   * @param  hrtc RTC handle
02425   * @param  BackupRegister RTC Backup data Register number.
02426   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to
02427   *                                 specify the register.
02428   * @retval Read value
02429   */
02430 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister)
02431 {
02432   uint32_t tmp;
02433
02434   /* Check the parameters */
02435   assert_param(IS_RTC_BKP(BackupRegister));
02436
02437   /* Point on address of first backup register */
02438 #if defined(TAMP_BKP0R)
02439   tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R);
02440 #endif /* TAMP_BKP0R */
02441 #if defined(RTC_BKP0R)
02442   tmp = (uint32_t) & (hrtc->Instance->BKP0R);
02443 #endif /* RTC_BKP0R */
02444
02445   tmp += (BackupRegister * 4U);
02446
02447   /* Read the specified register */
02448   return (*(__IO uint32_t *)tmp);
02449 }
02450
02451
02452 /**
02453   * @}
02454   */
02455
02456
02457 /** @addtogroup RTCEx_Exported_Functions_Group3
02458   * @brief    Extended Peripheral Control functions
02459   *
02460 @verbatim
02461  ===============================================================================
02462               ##### Extended Peripheral Control functions #####
02463  ===============================================================================
02464     [..]
02465     This subsection provides functions allowing to
02466       (+) Write a data in a specified RTC Backup data register
02467       (+) Read a data in a specified RTC Backup data register
02468       (+) Set the Smooth calibration parameters.
02469       (+) Set Low Power calibration parameter (if feature supported).
02470       (+) Configure the Synchronization Shift Control Settings.
02471       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
02472       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
02473       (+) Enable the RTC reference clock detection.
02474       (+) Disable the RTC reference clock detection.
02475       (+) Enable the Bypass Shadow feature.
02476       (+) Disable the Bypass Shadow feature.
02477
02478 @endverbatim
02479   * @{
02480   */
02481
02482
02483 /**
02484   * @brief  Set the Smooth calibration parameters.
02485   * @param  hrtc RTC handle
02486   * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
02487   *          This parameter can be can be one of the following values :
02488   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
02489   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
02490   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
02491   * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
02492   *          This parameter can be one of the following values:
02493   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
02494   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
02495   * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
02496   *          This parameter can be one any value from 0 to 0x000001FF.
02497   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
02498   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
02499   *         SmoothCalibMinusPulsesValue must be equal to 0.
02500   * @retval HAL status
02501   */
02502 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef * hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
02503 {
02504   uint32_t tickstart;
02505
02506   /* Check the parameters */
02507   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
02508   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
02509   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
02510
02511   /* Process Locked */
02512   __HAL_LOCK(hrtc);
02513
02514   hrtc->State = HAL_RTC_STATE_BUSY;
02515
02516   /* Disable the write protection for RTC registers */
02517   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02518
02519   /* check if a calibration operation is pending */
02520 #if defined(RTC_ICSR_RECALPF)
02521   if ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
02522 #endif /* RTC_ICSR_RECALPF */
02523 #if defined(RTC_ISR_RECALPF)
02524     if ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
02525 #endif /* RTC_ISR_RECALPF */
02526     {
02527       tickstart = HAL_GetTick();
02528
02529       /* Wait for pending calibration operation to finish */
02530 #if defined(RTC_ICSR_RECALPF)
02531       while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
02532 #endif /* RTC_ICSR_RECALPF */
02533 #if defined(RTC_ISR_RECALPF)
02534         while ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
02535 #endif /* RTC_ISR_RECALPF */
02536         {
02537           if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02538           {
02539             /* Enable the write protection for RTC registers */
02540             __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02541
02542             /* Change RTC state */
02543             hrtc->State = HAL_RTC_STATE_TIMEOUT;
02544
02545             /* Process Unlocked */
02546             __HAL_UNLOCK(hrtc);
02547
02548             return HAL_TIMEOUT;
02549           }
02550         }
02551     }
02552
02553   /* Configure the Smooth calibration settings */
02554   MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
02555
02556   /* Enable the write protection for RTC registers */
02557   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02558
02559   /* Change RTC state */
02560   hrtc->State = HAL_RTC_STATE_READY;
02561
02562   /* Process Unlocked */
02563   __HAL_UNLOCK(hrtc);
02564
02565   return HAL_OK;
02566 }
02567
02568 /**
02569   * @brief  Configure the Synchronization Shift Control Settings.
02570   * @note   When REFCKON is set, firmware must not write to Shift control register.
02571   * @param  hrtc RTC handle
02572   * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
02573   *          This parameter can be one of the following values:
02574   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
02575   *             @arg RTC_SHIFTADD1S_RESET: No effect.
02576   * @param  ShiftSubFS Select the number of Second Fractions to substitute.
02577   *          This parameter can be one any value from 0 to 0x7FFF.
02578   * @retval HAL status
02579   */
02580 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef * hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
02581 {
02582   uint32_t tickstart;
02583
02584   /* Check the parameters */
02585   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
02586   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
02587
02588   /* Process Locked */
02589   __HAL_LOCK(hrtc);
02590
02591   hrtc->State = HAL_RTC_STATE_BUSY;
02592
02593   /* Disable the write protection for RTC registers */
02594   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02595
02596   tickstart = HAL_GetTick();
02597
02598   /* Wait until the shift is completed */
02599 #if defined(RTC_ICSR_SHPF)
02600   while ((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U)
02601 #endif /* RTC_ICSR_SHPF */
02602 #if defined(RTC_ISR_SHPF)
02603     while ((hrtc->Instance->ISR  & RTC_ISR_SHPF)  != 0U)
02604 #endif /* RTC_ISR_SHPF */
02605     {
02606       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
02607       {
02608         /* Enable the write protection for RTC registers */
02609         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02610
02611         hrtc->State = HAL_RTC_STATE_TIMEOUT;
02612
02613         /* Process Unlocked */
02614         __HAL_UNLOCK(hrtc);
02615
02616         return HAL_TIMEOUT;
02617       }
02618     }
02619
02620   /* Check if the reference clock detection is disabled */
02621   if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
02622   {
02623     /* Configure the Shift settings */
02624     hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
02625
02626     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
02627     if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
02628     {
02629       if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
02630       {
02631         /* Enable the write protection for RTC registers */
02632         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02633
02634         hrtc->State = HAL_RTC_STATE_ERROR;
02635
02636         /* Process Unlocked */
02637         __HAL_UNLOCK(hrtc);
02638
02639         return HAL_ERROR;
02640       }
02641     }
02642   }
02643   else
02644   {
02645     /* Enable the write protection for RTC registers */
02646     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02647
02648     /* Change RTC state */
02649     hrtc->State = HAL_RTC_STATE_ERROR;
02650
02651     /* Process Unlocked */
02652     __HAL_UNLOCK(hrtc);
02653
02654     return HAL_ERROR;
02655   }
02656
02657   /* Enable the write protection for RTC registers */
02658   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02659
02660   /* Change RTC state */
02661   hrtc->State = HAL_RTC_STATE_READY;
02662
02663   /* Process Unlocked */
02664   __HAL_UNLOCK(hrtc);
02665
02666   return HAL_OK;
02667 }
02668
02669 /**
02670   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
02671   * @param  hrtc RTC handle
02672   * @param  CalibOutput Select the Calibration output Selection.
02673   *          This parameter can be one of the following values:
02674   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
02675   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
02676   * @retval HAL status
02677   */
02678 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef * hrtc, uint32_t CalibOutput)
02679 {
02680   /* Check the parameters */
02681   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
02682
02683   /* Process Locked */
02684   __HAL_LOCK(hrtc);
02685
02686   hrtc->State = HAL_RTC_STATE_BUSY;
02687
02688   /* Disable the write protection for RTC registers */
02689   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02690
02691   /* Clear flags before config */
02692   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
02693
02694   /* Configure the RTC_CR register */
02695   hrtc->Instance->CR |= (uint32_t)CalibOutput;
02696
02697   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
02698
02699   /* Enable the write protection for RTC registers */
02700   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02701
02702   /* Change RTC state */
02703   hrtc->State = HAL_RTC_STATE_READY;
02704
02705   /* Process Unlocked */
02706   __HAL_UNLOCK(hrtc);
02707
02708   return HAL_OK;
02709 }
02710
02711 /**
02712   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
02713   * @param  hrtc RTC handle
02714   * @retval HAL status
02715   */
02716 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef * hrtc)
02717 {
02718   /* Process Locked */
02719   __HAL_LOCK(hrtc);
02720
02721   hrtc->State = HAL_RTC_STATE_BUSY;
02722
02723   /* Disable the write protection for RTC registers */
02724   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02725
02726   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
02727
02728   /* Enable the write protection for RTC registers */
02729   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02730
02731   /* Change RTC state */
02732   hrtc->State = HAL_RTC_STATE_READY;
02733
02734   /* Process Unlocked */
02735   __HAL_UNLOCK(hrtc);
02736
02737   return HAL_OK;
02738 }
02739
02740 /**
02741   * @brief  Enable the RTC reference clock detection.
02742   * @param  hrtc RTC handle
02743   * @retval HAL status
02744   */
02745 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef * hrtc)
02746 {
02747   /* Process Locked */
02748   __HAL_LOCK(hrtc);
02749
02750   hrtc->State = HAL_RTC_STATE_BUSY;
02751
02752   /* Disable the write protection for RTC registers */
02753   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02754
02755   /* Set Initialization mode */
02756   if (RTC_EnterInitMode(hrtc) != HAL_OK)
02757   {
02758     /* Enable the write protection for RTC registers */
02759     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02760
02761     /* Set RTC state*/
02762     hrtc->State = HAL_RTC_STATE_ERROR;
02763
02764     /* Process Unlocked */
02765     __HAL_UNLOCK(hrtc);
02766
02767     return HAL_ERROR;
02768   }
02769   else
02770   {
02771     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
02772
02773     /* Exit Initialization mode */
02774 #if defined(RTC_ICSR_INIT)
02775     hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
02776 #endif /* RTC_ICSR_INIT */
02777 #if defined(RTC_ISR_INIT)
02778     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
02779 #endif /* RTC_ISR_INIT */
02780   }
02781
02782   /* Enable the write protection for RTC registers */
02783   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02784
02785   /* Change RTC state */
02786   hrtc->State = HAL_RTC_STATE_READY;
02787
02788   /* Process Unlocked */
02789   __HAL_UNLOCK(hrtc);
02790
02791   return HAL_OK;
02792 }
02793
02794 /**
02795   * @brief  Disable the RTC reference clock detection.
02796   * @param  hrtc RTC handle
02797   * @retval HAL status
02798   */
02799 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef * hrtc)
02800 {
02801   /* Process Locked */
02802   __HAL_LOCK(hrtc);
02803
02804   hrtc->State = HAL_RTC_STATE_BUSY;
02805
02806   /* Disable the write protection for RTC registers */
02807   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02808
02809   /* Set Initialization mode */
02810   if (RTC_EnterInitMode(hrtc) != HAL_OK)
02811   {
02812     /* Enable the write protection for RTC registers */
02813     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02814
02815     /* Set RTC state*/
02816     hrtc->State = HAL_RTC_STATE_ERROR;
02817
02818     /* Process Unlocked */
02819     __HAL_UNLOCK(hrtc);
02820
02821     return HAL_ERROR;
02822   }
02823   else
02824   {
02825     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
02826
02827     /* Exit Initialization mode */
02828 #if defined(RTC_ICSR_INIT)
02829     hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
02830 #endif /* RTC_ICSR_INIT */
02831 #if defined(RTC_ISR_INIT)
02832     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
02833 #endif /* RTC_ISR_INIT */
02834   }
02835
02836   /* Enable the write protection for RTC registers */
02837   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02838
02839   /* Change RTC state */
02840   hrtc->State = HAL_RTC_STATE_READY;
02841
02842   /* Process Unlocked */
02843   __HAL_UNLOCK(hrtc);
02844
02845   return HAL_OK;
02846 }
02847
02848 /**
02849   * @brief  Enable the Bypass Shadow feature.
02850   * @note   When the Bypass Shadow is enabled the calendar value are taken
02851   *         directly from the Calendar counter.
02852   * @param  hrtc RTC handle
02853   * @retval HAL status
02854   */
02855 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef * hrtc)
02856 {
02857   /* Process Locked */
02858   __HAL_LOCK(hrtc);
02859
02860   hrtc->State = HAL_RTC_STATE_BUSY;
02861
02862   /* Disable the write protection for RTC registers */
02863   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02864
02865   /* Set the BYPSHAD bit */
02866   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
02867
02868   /* Enable the write protection for RTC registers */
02869   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02870
02871   /* Change RTC state */
02872   hrtc->State = HAL_RTC_STATE_READY;
02873
02874   /* Process Unlocked */
02875   __HAL_UNLOCK(hrtc);
02876
02877   return HAL_OK;
02878 }
02879
02880 /**
02881   * @brief  Disable the Bypass Shadow feature.
02882   * @note   When the Bypass Shadow is enabled the calendar value are taken
02883   *         directly from the Calendar counter.
02884   * @param  hrtc RTC handle
02885   * @retval HAL status
02886   */
02887 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc)
02888 {
02889   /* Process Locked */
02890   __HAL_LOCK(hrtc);
02891
02892   hrtc->State = HAL_RTC_STATE_BUSY;
02893
02894   /* Disable the write protection for RTC registers */
02895   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02896
02897   /* Reset the BYPSHAD bit */
02898   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
02899
02900   /* Enable the write protection for RTC registers */
02901   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02902
02903   /* Change RTC state */
02904   hrtc->State = HAL_RTC_STATE_READY;
02905
02906   /* Process Unlocked */
02907   __HAL_UNLOCK(hrtc);
02908
02909   return HAL_OK;
02910 }
02911
02912 #if defined(TAMP_COUNTR)
02913 /**
02914   * @brief  Increment Monotonic counter.
02915   * @param  hrtc RTC handle
02916   * @retval HAL status
02917   */
02918 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc)
02919 {
02920   UNUSED(hrtc);
02921   /* This register is read-only only and is incremented by one when a write access is done to this
02922      register. This register cannot roll-over and is frozen when reaching the maximum value. */
02923   CLEAR_REG(TAMP->COUNTR);
02924
02925   return HAL_OK;
02926 }
02927
02928 /**
02929   * @brief  Monotonic counter incrementation.
02930   * @param  hrtc RTC handle
02931   * @param  Counter monotonic counter value
02932   * @retval HAL status
02933   */
02934 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter)
02935 {
02936   UNUSED(hrtc);
02937   /* This register is read-only only and is incremented by one when a write access is done to this
02938      register. This register cannot roll-over and is frozen when reaching the maximum value. */
02939   *Counter = READ_REG(TAMP->COUNTR);
02940
02941   return HAL_OK;
02942 }
02943 #endif /* TAMP_COUNTR */
02944
02945 /**
02946   * @}
02947   */
02948
02949 /** @addtogroup RTCEx_Exported_Functions_Group4
02950   * @brief    Extended features functions
02951   *
02952 @verbatim
02953  ===============================================================================
02954                  ##### Extended features functions #####
02955  ===============================================================================
02956     [..]  This section provides functions allowing to:
02957       (+) RTC Alarm B callback
02958       (+) RTC Poll for Alarm B request
02959
02960 @endverbatim
02961   * @{
02962   */
02963
02964 /**
02965   * @brief  Alarm B callback.
02966   * @param  hrtc RTC handle
02967   * @retval None
02968   */
02969 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef * hrtc)
02970 {
02971   /* Prevent unused argument(s) compilation warning */
02972   UNUSED(hrtc);
02973
02974   /* NOTE : This function should not be modified, when the callback is needed,
02975             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
02976    */
02977 }
02978
02979 /**
02980   * @brief  Handle Alarm B Polling request.
02981   * @param  hrtc RTC handle
02982   * @param  Timeout Timeout duration
02983   * @retval HAL status
02984   */
02985 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef * hrtc, uint32_t Timeout)
02986 {
02987   uint32_t tickstart = HAL_GetTick();
02988
02989   while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
02990   {
02991     if (Timeout != HAL_MAX_DELAY)
02992     {
02993       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
02994       {
02995         hrtc->State = HAL_RTC_STATE_TIMEOUT;
02996         return HAL_TIMEOUT;
02997       }
02998     }
02999   }
03000
03001   /* Clear the Alarm Flag */
03002   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
03003
03004   /* Change RTC state */
03005   hrtc->State = HAL_RTC_STATE_READY;
03006
03007   return HAL_OK;
03008 }
03009
03010 /**
03011   * @}
03012   */
03013
03014
03015 /**
03016   * @}
03017   */
03018
03019 #endif /* HAL_RTC_MODULE_ENABLED */
03020
03021 /**
03022   * @}
03023   */
03024
03025 /**
03026   * @}
03027   */
03028
03029 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_rtc_ex.h Source File

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stm32h7xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_RTC_EX_H
00022 #define STM32H7xx_HAL_RTC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif /* __cplusplus */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup RTCEx RTCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00042   * @{
00043   */
00044
00045 /** @defgroup RTCEx_Tamper_structure_definition RTC Tamper structure definition
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00051                                              This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
00052
00053   uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
00054                                              This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
00055
00056   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00057                                              This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
00058
00059   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00060                                              This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */
00061
00062   uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
00063                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
00064
00065   uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.
00066                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00067
00068   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00069                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00070
00071   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00072                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00073
00074   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00075                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00076
00077   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00078                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00079 } RTC_TamperTypeDef;
00080 /**
00081   * @}
00082   */
00083
00084 #if defined(TAMP_CR1_ITAMP1E)
00085 /** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
00086   * @{
00087   */
00088 typedef struct
00089 {
00090   uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
00091                                              This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
00092
00093   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00094                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
00095 } RTC_InternalTamperTypeDef;
00096 /**
00097   * @}
00098   */
00099 #endif /* TAMP_CR1_ITAMP1E */
00100
00101 #if defined(TAMP_ATCR1_TAMP1AM)
00102 /** @defgroup RTCEx_Active_Seed_Size Seed size Definitions
00103   * @{
00104   */
00105 #define RTC_ATAMP_SEED_NB_UINT32        4U
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup RTCEx_Active_Tampers_Number Active Tampers number Definitions
00111   * @{
00112   */
00113 #define RTC_TAMP_NB                     3u
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup RTCEx_ActiveTamper_structures_definition RTC Active Tamper structures definitions
00119   * @{
00120   */
00121 typedef struct
00122 {
00123   uint32_t Enable;                      /*!< Specifies the Tamper input is active.
00124                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */
00125
00126   uint32_t Interrupt;                    /*!< Specifies the interrupt mode
00127                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */
00128
00129   uint32_t Output;                      /*!< Specifies the TAMP output to be compared with.
00130                                              The same output can be used for several tamper inputs.
00131                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */
00132
00133   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00134                                              This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
00135
00136   uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
00137                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
00138
00139 } RTC_ATampInputTypeDef;
00140
00141
00142 typedef struct
00143 {
00144   uint32_t ActiveFilter;                /*!< Specifies the Active tamper filter enable.
00145                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */
00146
00147   uint32_t ActiveAsyncPrescaler;        /*!< Specifies the Active Tamper asynchronous Prescaler clock.
00148                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Async_prescaler */
00149
00150   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the timeStamp on tamper detection.
00151                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
00152
00153   uint32_t ActiveOutputChangePeriod;    /*!< Specifies the Active Tamper output change period .
00154                                              This parameter can be a value from 0 to 7. */
00155
00156   uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32];
00157   /*!< Specifies the Active Tamper RNG Seed value .
00158        This parameter can be a value from 0 to (2^32-1) */
00159
00160   RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB];
00161   /*!< Specifies configuration of all active tampers.
00162        The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */
00163 } RTC_ActiveTampersTypeDef;
00164
00165 /**
00166   * @}
00167   */
00168 #endif /* TAMP_ATCR1_TAMP1AM */
00169
00170 /**
00171   * @}
00172   */
00173
00174 /* Exported constants --------------------------------------------------------*/
00175
00176 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00177   * @{
00178   */
00179
00180 /* ========================================================================== */
00181 /*         ##### Extended RTC Backup registers exported constants #####       */
00182 /* ========================================================================== */
00183
00184 /** @defgroup RTCEx_Backup_Registers_Number_Definitions RTC Backup Registers Number Definitions
00185   * @{
00186   */
00187 #if defined(RTC_BKP_NUMBER)
00188 #define BKP_REG_NUMBER                       RTC_BKP_NUMBER
00189 #endif /* RTC_BKP_NUMBER */
00190 #if defined(TAMP_BKP_NUMBER)
00191 #define BKP_REG_NUMBER                       TAMP_BKP_NUMBER
00192 #endif /* TAMP_BKP_NUMBER */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
00198   * @{
00199   */
00200 #define RTC_BKP_DR0                       0x00u
00201 #define RTC_BKP_DR1                       0x01u
00202 #define RTC_BKP_DR2                       0x02u
00203 #define RTC_BKP_DR3                       0x03u
00204 #define RTC_BKP_DR4                       0x04u
00205 #define RTC_BKP_DR5                       0x05u
00206 #define RTC_BKP_DR6                       0x06u
00207 #define RTC_BKP_DR7                       0x07u
00208 #define RTC_BKP_DR8                       0x08u
00209 #define RTC_BKP_DR9                       0x09u
00210 #define RTC_BKP_DR10                      0x0Au
00211 #define RTC_BKP_DR11                      0x0Bu
00212 #define RTC_BKP_DR12                      0x0Cu
00213 #define RTC_BKP_DR13                      0x0Du
00214 #define RTC_BKP_DR14                      0x0Eu
00215 #define RTC_BKP_DR15                      0x0Fu
00216 #define RTC_BKP_DR16                      0x10u
00217 #define RTC_BKP_DR17                      0x11u
00218 #define RTC_BKP_DR18                      0x12u
00219 #define RTC_BKP_DR19                      0x13u
00220 #define RTC_BKP_DR20                      0x14u
00221 #define RTC_BKP_DR21                      0x15u
00222 #define RTC_BKP_DR22                      0x16u
00223 #define RTC_BKP_DR23                      0x17u
00224 #define RTC_BKP_DR24                      0x18u
00225 #define RTC_BKP_DR25                      0x19u
00226 #define RTC_BKP_DR26                      0x1Au
00227 #define RTC_BKP_DR27                      0x1Bu
00228 #define RTC_BKP_DR28                      0x1Cu
00229 #define RTC_BKP_DR29                      0x1Du
00230 #define RTC_BKP_DR30                      0x1Eu
00231 #define RTC_BKP_DR31                      0x1Fu
00232 /**
00233   * @}
00234   */
00235
00236 /* ========================================================================== */
00237 /*                 ##### RTC TimeStamp exported constants #####               */
00238 /* ========================================================================== */
00239
00240 /** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
00241   *
00242   * @{
00243   */
00244 #define RTC_TIMESTAMPEDGE_RISING            0x00000000u
00245 #define RTC_TIMESTAMPEDGE_FALLING           RTC_CR_TSEDGE
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pin Selection
00251   * @{
00252   */
00253 #define RTC_TIMESTAMPPIN_DEFAULT              0x00000000u
00254 /**
00255   * @}
00256   */
00257
00258
00259 /* ========================================================================== */
00260 /*                    ##### RTC Tamper exported constants #####               */
00261 /* ========================================================================== */
00262
00263 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
00264   * @{
00265   */
00266 #if defined(TAMP_CR1_TAMP1E)
00267 #define RTC_TAMPER_1                        TAMP_CR1_TAMP1E
00268 #endif /* TAMP_CR1_TAMP1E */
00269 #if defined(TAMP_CR1_TAMP2E)
00270 #define RTC_TAMPER_2                        TAMP_CR1_TAMP2E
00271 #endif /* TAMP_CR1_TAMP2E */
00272 #if defined(TAMP_CR1_TAMP3E)
00273 #define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
00274 #endif /* TAMP_CR1_TAMP3E */
00275
00276 #if defined(RTC_TAMPCR_TAMP1E)
00277 #define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
00278 #endif /* RTC_TAMPCR_TAMP1E */
00279 #if defined(RTC_TAMPCR_TAMP2E)
00280 #define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
00281 #endif /* RTC_TAMPCR_TAMP2E */
00282 #if defined(RTC_TAMPCR_TAMP3E)
00283 #define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
00284 #endif /* RTC_TAMPCR_TAMP3E */
00285
00286 #define RTC_TAMPER_ALL                     (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
00292   * @{
00293   */
00294 #if defined(TAMP_IER_TAMP1IE)
00295 #define RTC_IT_TAMP1                      TAMP_IER_TAMP1IE    /*!< Enable Tamper 1 Interrupt                */
00296 #endif /* TAMP_IER_TAMP1IE */
00297 #if defined(TAMP_IER_TAMP2IE)
00298 #define RTC_IT_TAMP2                      TAMP_IER_TAMP2IE    /*!< Enable Tamper 2 Interrupt                */
00299 #endif /* TAMP_IER_TAMP2IE */
00300 #if defined(TAMP_IER_TAMP3IE)
00301 #define RTC_IT_TAMP3                      TAMP_IER_TAMP3IE    /*!< Enable Tamper 3 Interrupt                */
00302 #endif /* TAMP_IER_TAMP3IE */
00303
00304 #if defined(RTC_TAMPCR_TAMP1IE)
00305 #define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE  /*!< Enable Tamper 1 Interrupt                */
00306 #endif /* RTC_TAMPCR_TAMP1IE */
00307 #if defined(RTC_TAMPCR_TAMP2IE)
00308 #define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE  /*!< Enable Tamper 2 Interrupt                */
00309 #endif /* RTC_TAMPCR_TAMP2IE */
00310 #if defined(RTC_TAMPCR_TAMP3IE)
00311 #define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE  /*!< Enable Tamper 3 Interrupt                */
00312 #endif /* RTC_TAMPCR_TAMP3IE */
00313
00314 #if defined(RTC_TAMPCR_TAMPIE)
00315 #define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE   /*!< Enable all Tamper Interrupts              */
00316 #define RTC_IT_TAMPALL                    RTC_IT_TAMP
00317 #else /* RTC_TAMPCR_TAMPIE not defined */
00318 #define RTC_IT_TAMP                       0x00000000u         /*!< No such feature in RTC3                   */
00319 #define RTC_IT_TAMPALL                    (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)
00320 #endif /* RTC_TAMPCR_TAMPIE */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RTCEx_Internal_Tamper_Pins_Definitions  RTC Internal Tamper Pins Definition
00326   * @{
00327   */
00328 #if defined(TAMP_CR1_ITAMP1E)
00329 #define RTC_INT_TAMPER_1                    TAMP_CR1_ITAMP1E
00330 #endif /* TAMP_CR1_ITAMP1E */
00331 #if defined(TAMP_CR1_ITAMP2E)
00332 #define RTC_INT_TAMPER_2                    TAMP_CR1_ITAMP2E
00333 #endif /* TAMP_CR1_ITAMP2E */
00334 #if defined(TAMP_CR1_ITAMP3E)
00335 #define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E
00336 #endif /* TAMP_CR1_ITAMP3E */
00337 #if defined(TAMP_CR1_ITAMP4E)
00338 #define RTC_INT_TAMPER_4                    TAMP_CR1_ITAMP4E
00339 #endif /* TAMP_CR1_ITAMP4E */
00340 #if defined(TAMP_CR1_ITAMP5E)
00341 #define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E
00342 #endif /* TAMP_CR1_ITAMP5E */
00343 #if defined(TAMP_CR1_ITAMP6E)
00344 #define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E
00345 #endif /* TAMP_CR1_ITAMP6E */
00346 #if defined(TAMP_CR1_ITAMP8E)
00347 #define RTC_INT_TAMPER_8                    TAMP_CR1_ITAMP8E
00348 #define RTC_INT_TAMPER_ALL                  (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
00349                                              RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
00350                                              RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
00351                                              RTC_INT_TAMPER_8)
00352 #endif /* TAMP_CR1_ITAMP8E */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup RTCEx_Internal_Tamper_Interrupt_Definitions  RTC Internal Tamper Interrupt
00358   * @{
00359   */
00360 #if defined(TAMP_IER_ITAMP1IE)
00361 #define RTC_INTERNAL_TAMPER1_INTERRUPT     TAMP_IER_ITAMP1IE  /*!< Enable Internal Tamper 1 Interrupt   */
00362 #endif /* TAMP_IER_ITAMP1IE */
00363 #if defined(TAMP_IER_ITAMP2IE)
00364 #define RTC_INTERNAL_TAMPER2_INTERRUPT     TAMP_IER_ITAMP2IE  /*!< Enable Internal Tamper 2 Interrupt   */
00365 #endif /* TAMP_IER_ITAMP2IE */
00366 #if defined(TAMP_IER_ITAMP3IE)
00367 #define RTC_INTERNAL_TAMPER3_INTERRUPT     TAMP_IER_ITAMP3IE  /*!< Enable Internal Tamper 3 Interrupt   */
00368 #endif /* TAMP_IER_ITAMP3IE */
00369 #if defined(TAMP_IER_ITAMP4IE)
00370 #define RTC_INTERNAL_TAMPER4_INTERRUPT     TAMP_IER_ITAMP4IE  /*!< Enable Internal Tamper 4 Interrupt   */
00371 #endif /* TAMP_IER_ITAMP4IE */
00372 #if defined(TAMP_IER_ITAMP5IE)
00373 #define RTC_INTERNAL_TAMPER5_INTERRUPT     TAMP_IER_ITAMP5IE  /*!< Enable Internal Tamper 5 Interrupt   */
00374 #endif /* TAMP_IER_ITAMP5IE */
00375 #if defined(TAMP_IER_ITAMP6IE)
00376 #define RTC_INTERNAL_TAMPER6_INTERRUPT     TAMP_IER_ITAMP6IE  /*!< Enable Internal Tamper 6 Interrupt   */
00377 #endif /* TAMP_IER_ITAMP6IE */
00378 #if defined(TAMP_IER_ITAMP8IE)
00379 #define RTC_INTERNAL_TAMPER8_INTERRUPT     TAMP_IER_ITAMP8IE  /*!< Enable Internal Tamper 8 Interrupt   */
00380 #endif /* TAMP_IER_ITAMP8IE */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
00386   * @{
00387   */
00388 #define RTC_TAMPERTRIGGER_RISINGEDGE        0x01u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
00389 #define RTC_TAMPERTRIGGER_FALLINGEDGE       0x02u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
00390 #define RTC_TAMPERTRIGGER_LOWLEVEL          0x04u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
00391 #define RTC_TAMPERTRIGGER_HIGHLEVEL         0x08u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
00392
00393 #if defined(TAMP_CR2_TAMP1TRG)
00394 #define RTC_TAMPER_1_TRIGGER                TAMP_CR2_TAMP1TRG
00395 #endif /* TAMP_CR2_TAMP1TRG */
00396 #if defined(TAMP_CR2_TAMP2TRG)
00397 #define RTC_TAMPER_2_TRIGGER                TAMP_CR2_TAMP2TRG
00398 #endif /* TAMP_CR2_TAMP2TRG */
00399 #if defined(TAMP_CR2_TAMP3TRG)
00400 #define RTC_TAMPER_3_TRIGGER                TAMP_CR2_TAMP3TRG
00401 #endif /* TAMP_CR2_TAMP3TRG */
00402
00403 #if defined(RTC_TAMPCR_TAMP1TRG)
00404 #define RTC_TAMPER_1_TRIGGER                RTC_TAMPCR_TAMP1TRG
00405 #endif /* RTC_TAMPCR_TAMP1TRG */
00406 #if defined(RTC_TAMPCR_TAMP2TRG)
00407 #define RTC_TAMPER_2_TRIGGER                RTC_TAMPCR_TAMP2TRG
00408 #endif /* RTC_TAMPCR_TAMP2TRG */
00409 #if defined(RTC_TAMPCR_TAMP3TRG)
00410 #define RTC_TAMPER_3_TRIGGER                RTC_TAMPCR_TAMP3TRG
00411 #endif /* RTC_TAMPCR_TAMP3TRG */
00412
00413 #define RTC_TAMPER_X_TRIGGER                (RTC_TAMPER_1_TRIGGER |\
00414                                              RTC_TAMPER_2_TRIGGER |\
00415                                              RTC_TAMPER_3_TRIGGER)
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
00421 * @{
00422 */
00423 #if defined(TAMP_CR2_TAMP1NOERASE)
00424 #define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00u
00425 #define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01u
00426 #endif /* TAMP_CR2_TAMP1NOERASE */
00427 #if defined(RTC_TAMPCR_TAMP1NOERASE)
00428 #define RTC_TAMPER_ERASE_BACKUP_ENABLE     0x00000000u
00429 #define RTC_TAMPER_ERASE_BACKUP_DISABLE    RTC_TAMPCR_TAMP1NOERASE
00430 #endif /* RTC_TAMPCR_TAMP1NOERASE */
00431
00432 #if defined(TAMP_CR2_TAMP1NOERASE)
00433 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  TAMP_CR2_TAMP1NOERASE
00434 #endif /* TAMP_CR2_TAMP1NOERASE */
00435 #if defined(TAMP_CR2_TAMP2NOERASE)
00436 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  TAMP_CR2_TAMP2NOERASE
00437 #endif /* TAMP_CR2_TAMP2NOERASE */
00438 #if defined(TAMP_CR2_TAMP3NOERASE)
00439 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  TAMP_CR2_TAMP3NOERASE
00440 #endif /* TAMP_CR2_TAMP3NOERASE */
00441
00442 #if defined(RTC_TAMPCR_TAMP1NOERASE)
00443 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  RTC_TAMPCR_TAMP1NOERASE
00444 #endif /* RTC_TAMPCR_TAMP1NOERASE */
00445 #if defined(RTC_TAMPCR_TAMP2NOERASE)
00446 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  RTC_TAMPCR_TAMP2NOERASE
00447 #endif /* RTC_TAMPCR_TAMP2NOERASE */
00448 #if defined(RTC_TAMPCR_TAMP3NOERASE)
00449 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  RTC_TAMPCR_TAMP3NOERASE
00450 #endif /* RTC_TAMPCR_TAMP3NOERASE */
00451
00452 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\
00453                                               RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\
00454                                               RTC_DISABLE_BKP_ERASE_ON_TAMPER_3)
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
00460 * @{
00461 */
00462 #if defined(TAMP_CR2_TAMP1MSK)
00463 #define RTC_TAMPERMASK_FLAG_DISABLE         0x00u
00464 #define RTC_TAMPERMASK_FLAG_ENABLE          0x01u
00465 #endif /* TAMP_CR2_TAMP1MSK */
00466 #if defined(RTC_TAMPCR_TAMP1MF)
00467 #define RTC_TAMPERMASK_FLAG_DISABLE        0x00000000u
00468 #define RTC_TAMPERMASK_FLAG_ENABLE         RTC_TAMPCR_TAMP1MF
00469 #endif /* RTC_TAMPCR_TAMP1MF */
00470
00471 #if defined(TAMP_CR2_TAMP1MSK)
00472 #define RTC_TAMPER_1_MASK_FLAG             TAMP_CR2_TAMP1MSK
00473 #endif /* TAMP_CR2_TAMP1MSK */
00474 #if defined(TAMP_CR2_TAMP2MSK)
00475 #define RTC_TAMPER_2_MASK_FLAG             TAMP_CR2_TAMP2MSK
00476 #endif /* TAMP_CR2_TAMP2MSK */
00477 #if defined(TAMP_CR2_TAMP3MSK)
00478 #define RTC_TAMPER_3_MASK_FLAG             TAMP_CR2_TAMP3MSK
00479 #endif /* TAMP_CR2_TAMP3MSK */
00480
00481 #if defined(RTC_TAMPCR_TAMP1MF)
00482 #define RTC_TAMPER_1_MASK_FLAG             RTC_TAMPCR_TAMP1MF
00483 #endif /* RTC_TAMPCR_TAMP1MF */
00484 #if defined(RTC_TAMPCR_TAMP2MF)
00485 #define RTC_TAMPER_2_MASK_FLAG             RTC_TAMPCR_TAMP2MF
00486 #endif /* RTC_TAMPCR_TAMP2MF */
00487 #if defined(RTC_TAMPCR_TAMP3MF)
00488 #define RTC_TAMPER_3_MASK_FLAG             RTC_TAMPCR_TAMP3MF
00489 #endif /* RTC_TAMPCR_TAMP3MF */
00490
00491 #define RTC_TAMPER_X_MASK_FLAG             (RTC_TAMPER_1_MASK_FLAG |\
00492                                             RTC_TAMPER_2_MASK_FLAG |\
00493                                             RTC_TAMPER_3_MASK_FLAG)
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
00499   * @{
00500   */
00501 #if defined(TAMP_FLTCR_TAMPFLT)
00502 #define RTC_TAMPERFILTER_DISABLE   0x00000000U             /*!< Tamper filter is disabled */
00503
00504 #define RTC_TAMPERFILTER_2SAMPLE   TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2
00505                                                                  consecutive samples at the active level */
00506 #define RTC_TAMPERFILTER_4SAMPLE   TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4
00507                                                                  consecutive samples at the active level */
00508 #define RTC_TAMPERFILTER_8SAMPLE   TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8
00509                                                                  consecutive samples at the active level */
00510 #define RTC_TAMPERFILTER_MASK      TAMP_FLTCR_TAMPFLT      /*!< Masking all bits except those of
00511                                                                  field TAMPFLT[1:0]. */
00512 #endif /* TAMP_FLTCR_TAMPFLT */
00513 #if defined(RTC_TAMPCR_TAMPFLT)
00514 #define RTC_TAMPERFILTER_DISABLE   0x00000000u             /*!< Tamper filter is disabled */
00515
00516 #define RTC_TAMPERFILTER_2SAMPLE   RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2
00517                                                                  consecutive samples at the active level */
00518 #define RTC_TAMPERFILTER_4SAMPLE   RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4
00519                                                                  consecutive samples at the active level */
00520 #define RTC_TAMPERFILTER_8SAMPLE   RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8
00521                                                                  consecutive samples at the active level. */
00522 #define RTC_TAMPERFILTER_MASK      RTC_TAMPCR_TAMPFLT      /*!< Masking all bits except those of
00523                                                                  field TAMPFLT[1:0]. */
00524 #endif /* RTC_TAMPCR_TAMPFLT */
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
00530   * @{
00531   */
00532 #if defined(TAMP_FLTCR_TAMPFREQ)
00533 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled
00534                                                                                                       with a frequency =  RTCCLK / 32768 */
00535 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
00536                                                                                                       with a frequency =  RTCCLK / 16384 */
00537 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled
00538                                                                                                       with a frequency =  RTCCLK / 8192  */
00539 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
00540                                                                                                       with a frequency =  RTCCLK / 4096  */
00541 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled
00542                                                                                                       with a frequency =  RTCCLK / 2048  */
00543 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00544                                                                                                       with a frequency =  RTCCLK / 1024  */
00545 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00546                                                                                                       with a frequency =  RTCCLK / 512   */
00547 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled
00548                                                                                                       with a frequency =  RTCCLK / 256   */
00549 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      TAMP_FLTCR_TAMPFREQ                             /*!< Masking all bits except those of
00550                                                                                                       field TAMPFREQ[2:0]*/
00551 #endif /* TAMP_FLTCR_TAMPFREQ */
00552 #if defined(RTC_TAMPCR_TAMPFREQ)
00553 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000u                                     /*!< Each of the tamper inputs are sampled
00554                                                                                                       with a frequency =  RTCCLK / 32768 */
00555 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
00556                                                                                                       with a frequency =  RTCCLK / 16384 */
00557 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled
00558                                                                                                       with a frequency =  RTCCLK / 8192  */
00559 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
00560                                                                                                       with a frequency =  RTCCLK / 4096  */
00561 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled
00562                                                                                                       with a frequency =  RTCCLK / 2048  */
00563 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled
00564                                                                                                       with a frequency =  RTCCLK / 1024  */
00565 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled
00566                                                                                                       with a frequency =  RTCCLK / 512   */
00567 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    RTC_TAMPCR_TAMPFREQ                              /*!< Each of the tamper inputs are sampled
00568                                                                                                       with a frequency =  RTCCLK / 256   */
00569 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      RTC_TAMPCR_TAMPFREQ                             /*!< Masking all bits except those of
00570                                                                                                       field TAMPFREQ[2:0]*/
00571 #endif /* RTC_TAMPCR_TAMPFREQ */
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
00577   * @{
00578   */
00579 #if defined(TAMP_FLTCR_TAMPPRCH)
00580 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U             /*!< Tamper pins are pre-charged before
00581                                                                               sampling during 1 RTCCLK cycle  */
00582 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before
00583                                                                               sampling during 2 RTCCLK cycles */
00584 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1   /*!< Tamper pins are pre-charged before
00585                                                                               sampling during 4 RTCCLK cycles */
00586 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH     /*!< Tamper pins are pre-charged before
00587                                                                               sampling during 8 RTCCLK cycles */
00588 #define RTC_TAMPERPRECHARGEDURATION_MASK        TAMP_FLTCR_TAMPPRCH     /*!< Masking all bits except those of
00589                                                                               field TAMPPRCH[1:0] */
00590 #endif /* TAMP_FLTCR_TAMPPRCH */
00591 #if defined(RTC_TAMPCR_TAMPPRCH)
00592 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000u             /*!< Tamper pins are pre-charged before
00593                                                                               sampling during 1 RTCCLK cycle  */
00594 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before
00595                                                                               sampling during 2 RTCCLK cycles */
00596 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1   /*!< Tamper pins are pre-charged before
00597                                                                               sampling during 4 RTCCLK cycles */
00598 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH     /*!< Tamper pins are pre-charged before
00599                                                                               sampling during 8 RTCCLK cycles */
00600 #define RTC_TAMPERPRECHARGEDURATION_MASK        RTC_TAMPCR_TAMPPRCH     /*!< Masking all bits except those of
00601                                                                               field TAMPPRCH[1:0] */
00602 #endif /* RTC_TAMPCR_TAMPPRCH */
00603 /**
00604   * @}
00605   */
00606
00607 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
00608   * @{
00609   */
00610 #if defined(RTC_CR_TAMPTS)
00611 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */
00612 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS                 /*!< TimeStamp on Tamper Detection event saved        */
00613 #define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_CR_TAMPTS                 /*!< Masking all bits except bit TAMPTS               */
00614 #endif  /* RTC_CR_TAMPTS */
00615 #if defined(RTC_TAMPCR_TAMPTS)
00616 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */
00617 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_TAMPCR_TAMPTS             /*!< TimeStamp on Tamper Detection event saved        */
00618 #define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_TAMPCR_TAMPTS             /*!< Masking all bits except bit TAMPTS               */
00619 #endif /* RTC_TAMPCR_TAMPTS */
00620 /**
00621   * @}
00622   */
00623
00624 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
00625   * @{
00626   */
00627 #if defined(TAMP_FLTCR_TAMPPUDIS)
00628 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< Tamper pins are pre-charged before sampling */
00629 #define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS     /*!< Tamper pins pre-charge is disabled          */
00630 #define RTC_TAMPER_PULLUP_MASK             TAMP_FLTCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */
00631 #endif /* TAMP_FLTCR_TAMPPUDIS */
00632 #if defined(RTC_TAMPCR_TAMPPUDIS)
00633 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< TimeStamp on Tamper Detection event saved        */
00634 #define RTC_TAMPER_PULLUP_DISABLE          RTC_TAMPCR_TAMPPUDIS     /*!< TimeStamp on Tamper Detection event is not saved */
00635 #define RTC_TAMPER_PULLUP_MASK             RTC_TAMPCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */
00636 #endif /* RTC_TAMPCR_TAMPPUDIS */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Ouput Definitions
00642   * @{
00643   */
00644 #if defined(RTC_CR_TAMPOE)
00645 #define RTC_TAMPERDETECTIONOUTPUT_DISABLE  0x00000000u                   /*!< The tamper flag is not routed on TAMPALRM */
00646 #define RTC_TAMPERDETECTIONOUTPUT_ENABLE   RTC_CR_TAMPOE                 /*!< The tamper flag is routed on TAMPALRM combined with the signal
00647                                                                                provided by OSEL and with the polarity provided by POL */
00648 #endif  /* RTC_CR_TAMPOE */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup RTC_Tamper_Flags_Definitions RTC Tamper Flags Definitions
00654   * @{
00655   */
00656 #if defined(TAMP_SR_TAMP1F)
00657 #define RTC_FLAG_TAMP1F                   TAMP_SR_TAMP1F
00658 #endif /* TAMP_SR_TAMP1F */
00659 #if defined(TAMP_SR_TAMP2F)
00660 #define RTC_FLAG_TAMP2F                   TAMP_SR_TAMP2F
00661 #endif /* TAMP_SR_TAMP2F */
00662 #if defined(TAMP_SR_TAMP3F)
00663 #define RTC_FLAG_TAMP3F                   TAMP_SR_TAMP3F
00664 #endif /* TAMP_SR_TAMP3F */
00665
00666 #if defined(RTC_ISR_TAMP1F)
00667 #define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
00668 #endif /* RTC_ISR_TAMP1F */
00669 #if defined(RTC_ISR_TAMP2F)
00670 #define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
00671 #endif /* RTC_ISR_TAMP2F */
00672 #if defined(RTC_ISR_TAMP3F)
00673 #define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
00674 #endif /* RTC_ISR_TAMP3F */
00675 /**
00676   * @}
00677   */
00678
00679 /** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions
00680   * @{
00681   */
00682 #define RTC_ATAMP_ENABLE                   1u
00683 #define RTC_ATAMP_DISABLE                  0u
00684 /**
00685   * @}
00686   */
00687
00688 /** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions
00689   * @{
00690   */
00691 #define RTC_ATAMP_INTERRUPT_ENABLE        1u
00692 #define RTC_ATAMP_INTERRUPT_DISABLE       0u
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions
00698   * @{
00699   */
00700 #define RTC_ATAMP_FILTER_ENABLE           TAMP_ATCR1_FLTEN
00701 #define RTC_ATAMP_FILTER_DISABLE          0u
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup RTCEx_ActiveTamper_Async_prescaler RTC Active_Tamper_Asynchronous_Prescaler clock Definitions
00707   * @{
00708   */
00709 #define RTC_ATAMP_ASYNCPRES_RTCCLK        0u                                                                      /*!< RTCCLK */
00710 #define RTC_ATAMP_ASYNCPRES_RTCCLK_2      TAMP_ATCR1_ATCKSEL_0                                                    /*!< RTCCLK/2 */
00711 #define RTC_ATAMP_ASYNCPRES_RTCCLK_4      TAMP_ATCR1_ATCKSEL_1                                                    /*!< RTCCLK/4 */
00712 #define RTC_ATAMP_ASYNCPRES_RTCCLK_8     (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                            /*!< RTCCLK/8 */
00713 #define RTC_ATAMP_ASYNCPRES_RTCCLK_16     TAMP_ATCR1_ATCKSEL_2                                                    /*!< RTCCLK/16 */
00714 #define RTC_ATAMP_ASYNCPRES_RTCCLK_32    (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                            /*!< RTCCLK/32 */
00715 #define RTC_ATAMP_ASYNCPRES_RTCCLK_64    (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                            /*!< RTCCLK/64 */
00716 #define RTC_ATAMP_ASYNCPRES_RTCCLK_128   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)     /*!< RTCCLK/128 */
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup RTCEx_ActiveTamper_Sel  RTC Active Tamper selection Definition
00722   * @{
00723   */
00724 #define RTC_ATAMP_1                       0u   /*!< Tamper 1 */
00725 #define RTC_ATAMP_2                       1u   /*!< Tamper 2 */
00726 #define RTC_ATAMP_3                       2u   /*!< Tamper 3 */
00727 #define RTC_ATAMP_4                       3u   /*!< Tamper 4 */
00728 #define RTC_ATAMP_5                       4u   /*!< Tamper 5 */
00729 #define RTC_ATAMP_6                       5u   /*!< Tamper 6 */
00730 #define RTC_ATAMP_7                       6u   /*!< Tamper 7 */
00731 #define RTC_ATAMP_8                       7u   /*!< Tamper 8 */
00732 /**
00733   * @}
00734   */
00735
00736 /** @defgroup RTCEx_Tamper_Registers_Offset  RTC Tamper Registers Offset
00737   * @{
00738   */
00739 #if defined (TAMP_CR1_TAMP1E)
00740 /* Add this offset to RTC registers base address to reach TAMP registers base address. */
00741 #define TAMP_OFFSET (TAMP_BASE - RTC_BASE)
00742 #endif /* TAMP_CR1_TAMP1E */
00743 /**
00744   * @}
00745   */
00746
00747 /* ========================================================================== */
00748 /*                   ##### RTC Wake-up exported constants #####               */
00749 /* ========================================================================== */
00750
00751 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
00752   * @{
00753   */
00754 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000u
00755 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
00756 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
00757 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
00758 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
00759 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
00760 /**
00761   * @}
00762   */
00763
00764 /* ========================================================================== */
00765 /*        ##### Extended RTC Peripheral Control exported constants #####      */
00766 /* ========================================================================== */
00767
00768 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
00769   * @{
00770   */
00771 #define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000u             /*!< If RTCCLK = 32768 Hz, Smooth calibration
00772                                                                     period is 32s,  else 2exp20 RTCCLK pulses */
00773 #define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16         /*!< If RTCCLK = 32768 Hz, Smooth calibration
00774                                                                     period is 16s, else 2exp19 RTCCLK pulses */
00775 #define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8          /*!< If RTCCLK = 32768 Hz, Smooth calibration
00776                                                                     period is 8s, else 2exp18 RTCCLK pulses */
00777 /**
00778   * @}
00779   */
00780
00781 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus pulses Definitions
00782   * @{
00783   */
00784 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP           /*!< The number of RTCCLK pulses added
00785                                                                        during a X -second window = Y - CALM[8:0]
00786                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
00787 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000u             /*!< The number of RTCCLK pulses subbstited
00788                                                                        during a 32-second window = CALM[8:0] */
00789 /**
00790   * @}
00791   */
00792
00793 /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
00794   * @{
00795   */
00796 #define RTC_CALIBOUTPUT_512HZ            0x00000000u
00797 #define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
00803   * @{
00804   */
00805 #define RTC_SHIFTADD1S_RESET      0x00000000u
00806 #define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
00807 /**
00808   * @}
00809   */
00810
00811 /**
00812   * @}
00813   */
00814
00815 /* Exported macros -----------------------------------------------------------*/
00816
00817 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00818   * @{
00819   */
00820
00821 /* ========================================================================== */
00822 /*                    ##### RTC Wake-up exported macros #####                 */
00823 /* ========================================================================== */
00824
00825 /**
00826   * @brief  Enable the RTC WakeUp Timer peripheral.
00827   * @param  __HANDLE__ specifies the RTC handle.
00828   * @retval None
00829   */
00830 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00831
00832 /**
00833   * @brief  Disable the RTC WakeUp Timer peripheral.
00834   * @param  __HANDLE__ specifies the RTC handle.
00835   * @retval None
00836   */
00837 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00838
00839 /**
00840   * @brief  Enable the RTC WakeUpTimer interrupt.
00841   * @param  __HANDLE__ specifies the RTC handle.
00842   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
00843   *         This parameter can be:
00844   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00845   * @retval None
00846   */
00847 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00848
00849 /**
00850   * @brief  Disable the RTC WakeUpTimer interrupt.
00851   * @param  __HANDLE__ specifies the RTC handle.
00852   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
00853   *         This parameter can be:
00854   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00855   * @retval None
00856   */
00857 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00858
00859 /**
00860   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00861   * @param  __HANDLE__ specifies the RTC handle.
00862   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check.
00863   *         This parameter can be:
00864   *            @arg RTC_FLAG_WUTF WakeUpTimer interrupt flag
00865   * @retval None
00866   */
00867 #if defined(RTC_SR_WUTF)
00868 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->SR)  & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00869 #endif /* RTC_SR_WUTF */
00870 #if defined(RTC_ISR_WUTF)
00871 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00872 #endif /* RTC_ISR_WUTF */
00873
00874 /**
00875   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00876   * @param  __HANDLE__ specifies the RTC handle.
00877   * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
00878   *         This parameter can be:
00879   *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
00880   * @retval None
00881   */
00882 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00883
00884 #if defined(RTC_SR_WUTF)
00885 /**
00886   * @brief  Get the selected RTC WakeUpTimer's flag status.
00887   * @param  __HANDLE__ specifies the RTC handle.
00888   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag sources to check.
00889   *          This parameter can be:
00890   *             @arg @ref RTC_FLAG_WUTF
00891   * @retval Flag status
00892   */
00893 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
00894 #endif /* RTC_SR_WUTF */
00895 #if defined(RTC_ISR_WUTF)
00896 /**
00897   * @brief  Get the selected RTC WakeUpTimer's flag status.
00898   * @param  __HANDLE__ specifies the RTC handle.
00899   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag sources to check.
00900   *          This parameter can be:
00901   *             @arg @ref RTC_FLAG_WUTF
00902   *             @arg @ref RTC_FLAG_WUTWF
00903   * @retval Flag status
00904   */
00905 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00906 #endif /* RTC_ISR_WUTF */
00907
00908 /**
00909   * @brief  Clear the RTC Wake Up timer's pending flags.
00910   * @param  __HANDLE__ specifies the RTC handle.
00911   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
00912   *         This parameter can be:
00913   *            @arg @ref RTC_FLAG_WUTF
00914   * @retval None
00915   */
00916 #if defined(RTC_SCR_CWUTF)
00917 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
00918 #endif /* RTC_SCR_CWUTF */
00919 #if defined(RTC_ISR_WUTF)
00920 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00921 #endif /* RTC_ISR_WUTF */
00922
00923 /* ========================================================================== */
00924 /*                     ##### RTC Tamper exported macros #####                 */
00925 /* ========================================================================== */
00926
00927 /**
00928   * @brief  Enable the RTC Tamper1 input detection.
00929   * @param  __HANDLE__ specifies the RTC handle.
00930   * @retval None
00931   */
00932 #if defined(TAMP_CR1_TAMP1E)
00933 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))
00934 #endif /* TAMP_CR1_TAMP1E */
00935 #if defined(RTC_TAMPCR_TAMP1E)
00936 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
00937 #endif /* RTC_TAMPCR_TAMP1E */
00938
00939 /**
00940   * @brief  Disable the RTC Tamper1 input detection.
00941   * @param  __HANDLE__ specifies the RTC handle.
00942   * @retval None
00943   */
00944 #if defined(TAMP_CR1_TAMP1E)
00945 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))
00946 #endif /* TAMP_CR1_TAMP1E */
00947 #if defined(RTC_TAMPCR_TAMP1E)
00948 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
00949 #endif /* RTC_TAMPCR_TAMP1E */
00950
00951 /**
00952   * @brief  Enable the RTC Tamper2 input detection.
00953   * @param  __HANDLE__ specifies the RTC handle.
00954   * @retval None
00955   */
00956 #if defined(TAMP_CR1_TAMP2E)
00957 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))
00958 #endif /* TAMP_CR1_TAMP2E */
00959 #if defined(RTC_TAMPCR_TAMP2E)
00960 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
00961 #endif /* RTC_TAMPCR_TAMP2E */
00962
00963 /**
00964   * @brief  Disable the RTC Tamper2 input detection.
00965   * @param  __HANDLE__ specifies the RTC handle.
00966   * @retval None
00967   */
00968 #if defined(TAMP_CR1_TAMP2E)
00969 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))
00970 #endif /* TAMP_CR1_TAMP2E */
00971 #if defined(RTC_TAMPCR_TAMP2E)
00972 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
00973 #endif /* RTC_TAMPCR_TAMP2E */
00974
00975 /**
00976   * @brief  Enable the RTC Tamper3 input detection.
00977   * @param  __HANDLE__ specifies the RTC handle.
00978   * @retval None
00979   */
00980 #if defined(TAMP_CR1_TAMP3E)
00981 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))
00982 #endif /* TAMP_CR1_TAMP3E */
00983 #if defined(RTC_TAMPCR_TAMP3E)
00984 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
00985 #endif /* RTC_TAMPCR_TAMP3E */
00986
00987 /**
00988   * @brief  Disable the RTC Tamper3 input detection.
00989   * @param  __HANDLE__ specifies the RTC handle.
00990   * @retval None
00991   */
00992 #if defined(TAMP_CR1_TAMP3E)
00993 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))
00994 #endif /* TAMP_CR1_TAMP3E */
00995 #if defined(RTC_TAMPCR_TAMP3E)
00996 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
00997 #endif /* RTC_TAMPCR_TAMP3E */
00998
00999 /**
01000   * @brief  Enable the RTC Tamper interrupt.
01001   * @param  __HANDLE__ specifies the RTC handle.
01002   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
01003   *          This parameter can be any combination of the following values:
01004   *             @arg  RTC_IT_TAMPALL: All tampers interrupts
01005   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
01006   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
01007   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
01008   * @retval None
01009   */
01010 #if defined(TAMP_IER_TAMP1IE)
01011 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))
01012 #endif /* TAMP_IER_TAMP1IE */
01013 #if defined(RTC_TAMPCR_TAMP1IE)
01014 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
01015 #endif /* RTC_TAMPCR_TAMP1IE */
01016
01017 /**
01018   * @brief  Disable the RTC Tamper interrupt.
01019   * @param  __HANDLE__ specifies the RTC handle.
01020   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
01021   *         This parameter can be any combination of the following values:
01022   *            @arg  RTC_IT_TAMP: All tampers interrupts
01023   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
01024   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
01025   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
01026   * @retval None
01027   */
01028 #if defined(TAMP_IER_TAMP1IE)
01029 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))
01030 #endif /* TAMP_IER_TAMP1IE */
01031 #if defined(RTC_TAMPCR_TAMP1IE)
01032 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
01033 #endif /* RTC_TAMPCR_TAMP1IE */
01034
01035 /**
01036   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
01037   * @param  __HANDLE__ specifies the RTC handle.
01038   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
01039   *         This parameter can be:
01040   *            @arg  RTC_FLAG_TAMP1F: Tamper1 interrupt flag
01041   *            @arg  RTC_FLAG_TAMP2F: Tamper2 interrupt flag
01042   *            @arg  RTC_FLAG_TAMP3F: Tamper3 interrupt flag
01043   * @retval Flag status
01044   */
01045 #if defined(TAMP_SR_TAMP1F)
01046 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01047 #endif /* TAMP_SR_TAMP1F */
01048 #if defined(RTC_ISR_TAMP1F)
01049 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01050 #endif /* RTC_ISR_TAMP1F */
01051
01052 /**
01053   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
01054   * @param  __HANDLE__ specifies the RTC handle.
01055   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
01056   *         This parameter can be:
01057   *            @arg  RTC_IT_TAMPALL: All tampers interrupts
01058   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
01059   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
01060   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
01061   * @retval Flag status
01062   */
01063 #if defined(TAMP_IER_TAMP1IE)
01064 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01065 #endif /* TAMP_IER_TAMP1IE */
01066 #if defined(RTC_TAMPCR_TAMP1IE)
01067 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01068 #endif /* RTC_TAMPCR_TAMP1IE */
01069
01070 /**
01071   * @brief  Get the selected RTC Tamper's flag status.
01072   * @param  __HANDLE__ specifies the RTC handle.
01073   * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
01074   *          This parameter can be:
01075   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
01076   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
01077   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
01078   * @retval Flag status
01079   */
01080 #if defined(TAMP_SR_TAMP1F)
01081 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)   ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
01082 #endif /* TAMP_SR_TAMP1F */
01083 #if defined(RTC_ISR_TAMP1F)
01084 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)                               (((((__HANDLE__)->Instance->ISR)                  & (__FLAG__)) != 0U) ? 1U : 0U)
01085 #endif /* RTC_ISR_TAMP1F */
01086
01087 /**
01088   * @brief  Clear the RTC Tamper's pending flags.
01089   * @param  __HANDLE__ specifies the RTC handle.
01090   * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
01091   *          This parameter can be:
01092   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
01093   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
01094   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
01095   * @retval None
01096   */
01097 #if defined(TAMP_SCR_CTAMP1F)
01098 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))
01099 #endif /* TAMP_SCR_CTAMP1F */
01100 #if defined(RTC_ISR_TAMP1F)
01101 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
01102 #endif /* RTC_ISR_TAMP1F */
01103
01104 /**
01105   * @brief  Get the frequency at which each of the Tamper inputs are sampled.
01106   * @param  __HANDLE__ specifies the RTC handle.
01107   * @retval Sampling frequency
01108   *         This value can be:
01109   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768
01110   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384
01111   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192
01112   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096
01113   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048
01114   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512
01115   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
01116   */
01117 #if defined(TAMP_FLTCR_TAMPFREQ)
01118 #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
01119 #endif /* TAMP_FLTCR_TAMPFREQ */
01120 #if defined(RTC_TAMPCR_TAMPFREQ)
01121 #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
01122 #endif /* RTC_TAMPCR_TAMPFREQ */
01123
01124 /**
01125   * @brief  Get the number of consecutive samples at the specified level needed
01126   *         to activate a Tamper event.
01127   * @param  __HANDLE__ specifies the RTC handle.
01128   * @retval Number of consecutive samples
01129   *         This value can be:
01130   *            @arg RTC_TAMPERFILTER_DISABLE
01131   *            @arg RTC_TAMPERFILTER_2SAMPLE
01132   *            @arg RTC_TAMPERFILTER_4SAMPLE
01133   *            @arg RTC_TAMPERFILTER_8SAMPLE
01134   */
01135 #if defined(TAMP_FLTCR_TAMPFLT)
01136 #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))
01137 #endif /* TAMP_FLTCR_TAMPFLT */
01138 #if defined(RTC_TAMPCR_TAMPFLT)
01139 #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERFILTER_MASK)))
01140 #endif /* RTC_TAMPCR_TAMPFLT */
01141
01142 /**
01143   * @brief  Get the pull-up resistors precharge duration.
01144   * @param  __HANDLE__ specifies the RTC handle.
01145   * @retval Number of consecutive samples
01146   *         This value can be:
01147   *            @arg RTC_TAMPERPRECHARGEDURATION_1RTCCLK
01148   *            @arg RTC_TAMPERPRECHARGEDURATION_2RTCCLK
01149   *            @arg RTC_TAMPERPRECHARGEDURATION_4RTCCLK
01150   *            @arg RTC_TAMPERPRECHARGEDURATION_8RTCCLK
01151   */
01152 #if defined(TAMP_FLTCR_TAMPPRCH)
01153 #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
01154 #endif /* TAMP_FLTCR_TAMPPRCH */
01155 #if defined(RTC_TAMPCR_TAMPPRCH)
01156 #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
01157 #endif /* RTC_TAMPCR_TAMPPRCH */
01158
01159 /**
01160   * @brief  Get the pull-up resistors status.
01161   * @param  __HANDLE__ specifies the RTC handle.
01162   * @retval Pull-up resistors status
01163   *         This value can be:
01164   *            @arg RTC_TAMPER_PULLUP_ENABLE
01165   *            @arg RTC_TAMPER_PULLUP_DISABLE
01166   */
01167 #if defined(TAMP_FLTCR_TAMPPUDIS)
01168 #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))
01169 #endif /* TAMP_FLTCR_TAMPPUDIS */
01170 #if defined(RTC_TAMPCR_TAMPPUDIS)
01171 #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPER_PULLUP_MASK)))
01172 #endif /* RTC_TAMPCR_TAMPPUDIS */
01173
01174 /* ========================================================================== */
01175 /*                  ##### RTC TimeStamp exported macros #####                 */
01176 /* ========================================================================== */
01177
01178 /**
01179   * @brief  Enable the RTC TimeStamp peripheral.
01180   * @param  __HANDLE__ specifies the RTC handle.
01181   * @retval None
01182   */
01183 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
01184
01185 /**
01186   * @brief  Disable the RTC TimeStamp peripheral.
01187   * @param  __HANDLE__ specifies the RTC handle.
01188   * @retval None
01189   */
01190 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
01191
01192 /**
01193   * @brief  Enable the RTC TimeStamp interrupt.
01194   * @param  __HANDLE__ specifies the RTC handle.
01195   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
01196   *         This parameter can be:
01197   *            @arg @ref RTC_IT_TS TimeStamp interrupt
01198   * @retval None
01199   */
01200 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
01201
01202 /**
01203   * @brief  Disable the RTC TimeStamp interrupt.
01204   * @param  __HANDLE__ specifies the RTC handle.
01205   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
01206   *         This parameter can be:
01207   *            @arg @ref RTC_IT_TS TimeStamp interrupt
01208   * @retval None
01209   */
01210 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
01211
01212 /**
01213   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
01214   * @param  __HANDLE__ specifies the RTC handle.
01215   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to check.
01216   *         This parameter can be:
01217   *            @arg @ref RTC_IT_TS TimeStamp interrupt
01218   * @retval None
01219   */
01220 #if defined(RTC_SR_TSF)
01221 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)
01222 #endif /* RTC_SR_TSF */
01223 #if defined(RTC_ISR_TSF)
01224 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01225 #endif /* RTC_ISR_TSF */
01226 /**
01227   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
01228   * @param  __HANDLE__ specifies the RTC handle.
01229   * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
01230   *         This parameter can be:
01231   *            @arg @ref RTC_IT_TS TimeStamp interrupt
01232   * @retval None
01233   */
01234 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
01235
01236 /**
01237   * @brief  Get the selected RTC TimeStamp's flag status.
01238   * @param  __HANDLE__ specifies the RTC handle.
01239   * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
01240   *         This parameter can be:
01241   *            @arg RTC_FLAG_TSF
01242   *            @arg RTC_FLAG_TSOVF
01243   * @retval Flag status
01244   */
01245 #if defined(RTC_SR_TSF)
01246 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
01247 #endif /* RTC_SR_TSF */
01248 #if defined(RTC_ISR_TSF)
01249 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
01250 #endif /* RTC_ISR_TSF */
01251
01252 /**
01253   * @brief  Clear the RTC Time Stamp's pending flags.
01254   * @param  __HANDLE__ specifies the RTC handle.
01255   * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
01256   *          This parameter can be:
01257   *             @arg RTC_FLAG_TSF
01258   *             @arg RTC_FLAG_TSOVF
01259   * @retval None
01260   */
01261 #if defined(RTC_SCR_CTSF)
01262 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->SCR |= __FLAG__)
01263 #endif /* RTC_SCR_CTSF */
01264 #if defined(RTC_ISR_TSF)
01265 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
01266 #endif /* RTC_ISR_TSF */
01267
01268 /**
01269   * @brief  Enable the RTC internal TimeStamp peripheral.
01270   * @param  __HANDLE__ specifies the RTC handle.
01271   * @retval None
01272   */
01273 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
01274
01275 /**
01276   * @brief  Disable the RTC internal TimeStamp peripheral.
01277   * @param  __HANDLE__ specifies the RTC handle.
01278   * @retval None
01279   */
01280 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
01281
01282 /**
01283   * @brief  Get the selected RTC Internal Time Stamp's flag status.
01284   * @param  __HANDLE__ specifies the RTC handle.
01285   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
01286   *         This parameter can be:
01287   *            @arg RTC_FLAG_ITSF
01288   * @retval Flag status
01289   */
01290 #if defined(RTC_SR_ITSF)
01291 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
01292 #endif /* RTC_SR_ITSF */
01293 #if defined(RTC_ISR_ITSF)
01294 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
01295 #endif /* RTC_ISR_ITSF */
01296
01297 /**
01298   * @brief  Clear the RTC Internal Time Stamp's pending flags.
01299   * @param  __HANDLE__ specifies the RTC handle.
01300   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
01301   *          This parameter can be:
01302   *             @arg RTC_FLAG_ITSF
01303   * @note   This flag must be cleared together with TSF flag.
01304   * @retval None
01305   */
01306 #if defined(RTC_SCR_CITSF)
01307 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->SCR |= __FLAG__)
01308 #endif /* RTC_SCR_CITSF */
01309 #if defined(RTC_ISR_ITSF)
01310 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
01311 #endif /* RTC_ISR_ITSF */
01312
01313 /**
01314   * @brief  Enable the RTC TimeStamp on Tamper detection.
01315   * @param  __HANDLE__ specifies the RTC handle.
01316   * @retval None
01317   */
01318 #if defined(RTC_CR_TAMPTS)
01319 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
01320 #endif /* RTC_CR_TAMPTS */
01321 #if defined(RTC_TAMPCR_TAMPTS)
01322 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->TAMPCR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
01323 #endif /* RTC_TAMPCR_TAMPTS */
01324
01325 /**
01326   * @brief  Disable the RTC TimeStamp on Tamper detection.
01327   * @param  __HANDLE__ specifies the RTC handle.
01328   * @retval None
01329   */
01330 #if defined(RTC_CR_TAMPTS)
01331 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
01332 #endif /* RTC_CR_TAMPTS */
01333 #if defined(RTC_TAMPCR_TAMPTS)
01334 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
01335 #endif /* RTC_TAMPCR_TAMPTS */
01336
01337 /**
01338   * @brief  Get activation status of the RTC TimeStamp on Tamper detection.
01339   * @param  __HANDLE__ specifies the RTC handle.
01340   * @retval Activation status of TimeStamp on Tamper detection
01341   *         This value can be:
01342   *            @arg RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
01343   *            @arg RTC_TIMESTAMPONTAMPERDETECTION_DISABLE
01344   */
01345 #if defined(RTC_CR_TAMPTS)
01346 #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
01347 #endif /* RTC_CR_TAMPTS */
01348 #if defined(RTC_TAMPCR_TAMPTS)
01349 #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->TAMPCR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
01350 #endif /* RTC_TAMPCR_TAMPTS */
01351
01352 #if defined(RTC_CR_TAMPOE)
01353 /**
01354   * @brief  Enable the RTC Tamper detection output.
01355   * @param  __HANDLE__ specifies the RTC handle.
01356   * @retval None
01357   */
01358 #define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
01359
01360 /**
01361   * @brief  Disable the RTC Tamper detection output.
01362   * @param  __HANDLE__ specifies the RTC handle.
01363   * @retval None
01364   */
01365 #define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
01366 #endif /* RTC_CR_TAMPOE */
01367
01368 /* ========================================================================== */
01369 /*         ##### Extended RTC Peripheral Control exported macros #####        */
01370 /* ========================================================================== */
01371
01372 /**
01373   * @brief  Enable the RTC calibration output.
01374   * @param  __HANDLE__ specifies the RTC handle.
01375   * @retval None
01376   */
01377 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
01378
01379 /**
01380   * @brief  Disable the calibration output.
01381   * @param  __HANDLE__ specifies the RTC handle.
01382   * @retval None
01383   */
01384 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
01385
01386 /**
01387   * @brief  Enable the clock reference detection.
01388   * @param  __HANDLE__ specifies the RTC handle.
01389   * @retval None
01390   */
01391 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
01392
01393 /**
01394   * @brief  Disable the clock reference detection.
01395   * @param  __HANDLE__ specifies the RTC handle.
01396   * @retval None
01397   */
01398 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
01399
01400 /**
01401   * @brief  Get the selected RTC shift operation's flag status.
01402   * @param  __HANDLE__ specifies the RTC handle.
01403   * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
01404   *          This parameter can be:
01405   *             @arg RTC_FLAG_SHPF
01406   * @retval Flag status
01407   */
01408 #if defined(RTC_ICSR_SHPF)
01409 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)
01410 #endif /* RTC_ICSR_SHPF */
01411 #if defined(RTC_ISR_SHPF)
01412 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR)  & (__FLAG__)) != 0U) ? 1U : 0U)
01413 #endif /* RTC_ISR_SHPF */
01414
01415 /* ========================================================================== */
01416 /*               ##### RTC Wake-up Interrupt exported macros #####            */
01417 /* ========================================================================== */
01418
01419 /**
01420   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
01421   * @retval None
01422   */
01423 #if defined(EXTI_D1)
01424 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01425 #else  /* EXTI */
01426 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1    |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01427 #endif /* EXTI_D1 */
01428 /**
01429   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
01430   * @retval None
01431   */
01432 #if defined(EXTI_D1)
01433 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01434 #else  /* EXTI */
01435 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1    &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01436 #endif /* EXTI_D1 */
01437
01438 /**
01439   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
01440   * @retval None
01441   */
01442 #if defined(EXTI_D1)
01443 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01444 #else  /* EXTI */
01445 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1    |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01446 #endif /* EXTI_D1 */
01447
01448 /**
01449   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
01450   * @retval None
01451   */
01452 #if defined(EXTI_D1)
01453 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01454 #else  /* EXTI */
01455 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1    &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01456 #endif /* EXTI_D1 */
01457
01458 /**
01459   * @brief  Enable event on the RTC WakeUp Timer associated D3 Exti line.
01460   * @retval None
01461   */
01462 #define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT()    (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01463
01464 /**
01465   * @brief  Disable event on the RTC WakeUp Timer associated D3 Exti line.
01466   * @retval None
01467   */
01468 #define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT()   (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01469
01470 #if defined(DUAL_CORE)
01471 /**
01472   * @brief  Enable interrupt on the RTC WakeUp Timer associated D2 Exti line.
01473   * @retval None
01474   */
01475 #define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT()       (EXTI_D2->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01476
01477 /**
01478   * @brief  Disable interrupt on the RTC WakeUp Timer associated D2 Exti line.
01479   * @retval None
01480   */
01481 #define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_IT()      (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01482
01483 /**
01484   * @brief  Enable event on the RTC WakeUp Timer associated D2 Exti line.
01485   * @retval None
01486   */
01487 #define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_EVENT()    (EXTI_D2->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01488
01489 /**
01490   * @brief  Disable event on the RTC WakeUp Timer associated D2 Exti line.
01491   * @retval None
01492   */
01493 #define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_EVENT()   (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01494
01495 #endif /* DUAL_CORE */
01496
01497 /**
01498   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
01499   * @retval None
01500   */
01501 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01502
01503 /**
01504   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
01505   * @retval None
01506   */
01507 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01508
01509 /**
01510   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
01511   * @retval None
01512   */
01513 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01514
01515 /**
01516   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
01517   * @retval None
01518   */
01519 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
01520
01521 /**
01522   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
01523   * @retval None
01524   */
01525 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
01526                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
01527                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
01528                                                                  } while(0)
01529
01530 /**
01531   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
01532   * This parameter can be:
01533   * @retval None
01534   */
01535 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
01536                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
01537                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
01538                                                                   } while(0)
01539
01540 /**
01541   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
01542   * @retval Line Status.
01543   */
01544 #if defined(EXTI_D1)
01545 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01546 #else  /* EXTI */
01547 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1    & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01548 #endif /* EXTI_D1 */
01549
01550 /**
01551   * @brief Clear the RTC WakeUp Timer associated Exti line flag.
01552   * @retval None
01553   */
01554 #if defined(EXTI_D1)
01555 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01556 #else  /* EXTI */
01557 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1    = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01558 #endif /* EXTI_D1 */
01559
01560 /**
01561   * @brief Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
01562   * @retval Line Status
01563   */
01564 #define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG()            (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01565
01566 /**
01567   * @brief Clear the RTC WakeUp Timer associated D3 Exti line flag.
01568   * @retval None.
01569   */
01570 #define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG()          (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01571
01572 /**
01573   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
01574   * @retval None.
01575   */
01576 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01577
01578 #if defined(DUAL_CORE)
01579
01580 /**
01581   * @brief Check whether the RTC WakeUp Timer associated D2 Exti line interrupt flag is set or not.
01582   * @retval Line Status.
01583   */
01584 #define __HAL_RTC_WAKEUPTIMER_EXTID2_GET_FLAG()            (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01585
01586 /**
01587   * @brief Clear the RTC WakeUp Timer associated D2 Exti line flag.
01588   * @retval None.
01589   */
01590 #define __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG()          (EXTI_D2->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01591
01592 #endif /* DUAL_CORE */
01593
01594 /* ========================================================================== */
01595 /*       ##### RTC TimeStamp and Tamper Interrupt exported macros #####       */
01596 /* ========================================================================== */
01597
01598 /**
01599   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
01600   * @retval None
01601   */
01602 #if defined(EXTI_D1)
01603 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01604 #else  /* EXTI */
01605 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1    |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01606 #endif /* EXTI_D1 */
01607
01608 /**
01609   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
01610   * @retval None
01611   */
01612 #if defined(EXTI_D1)
01613 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01614 #else  /* EXTI */
01615 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1    &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01616 #endif /* EXTI_D1 */
01617
01618 /**
01619   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
01620   * @retval None
01621   */
01622 #if defined(EXTI_D1)
01623 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01624 #else  /* EXTI */
01625 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1    |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01626 #endif /* EXTI_D1 */
01627
01628 /**
01629   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
01630   * @retval None
01631   */
01632 #if defined(EXTI_D1)
01633 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01634 #else  /* EXTI */
01635 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1    &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01636 #endif /* EXTI_D1 */
01637
01638 #if defined(DUAL_CORE)
01639 /**
01640   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.
01641   * @retval None
01642   */
01643 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT()      (EXTI_D2->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01644
01645 /**
01646   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.
01647   * @retval None
01648   */
01649 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_IT()     (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01650
01651
01652 /**
01653   * @brief  Enable event on the RTC Tamper and Timestamp associated D2 Exti line.
01654   * @retval None
01655   */
01656 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_EVENT()  (EXTI_D2->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01657
01658
01659 /**
01660   * @brief  Disable event on the RTC Tamper and Timestamp associated D2 Exti line.
01661   * @retval None
01662   */
01663 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01664
01665 #endif /* DUAL_CORE */
01666
01667 /**
01668   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
01669   * @retval None
01670   */
01671 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01672
01673 /**
01674   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
01675   * @retval None
01676   */
01677 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01678
01679 /**
01680   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
01681   * @retval None
01682   */
01683 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01684
01685 /**
01686   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
01687   * @retval None
01688   */
01689 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
01690
01691 /**
01692   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
01693   * @retval None
01694   */
01695 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
01696                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
01697                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
01698                                                                       } while(0)
01699
01700 /**
01701   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
01702   * @retval None
01703   */
01704 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
01705                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
01706                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
01707                                                                        } while(0)
01708
01709 /**
01710   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
01711   * @retval Line Status
01712   */
01713 #if defined(EXTI_D1)
01714 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01715 #else  /* EXTI */
01716 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1    & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01717 #endif /* EXTI_D1 */
01718
01719 /**
01720   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
01721   * @retval None
01722   */
01723 #if defined(EXTI_D1)
01724 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01725 #else  /* EXTI */
01726 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1    = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01727 #endif /* EXTI_D1 */
01728
01729 #if defined(DUAL_CORE)
01730 /**
01731   * @brief Check whether the RTC Tamper and Timestamp associated D2 Exti line interrupt flag is set or not.
01732   * @retval Line Status
01733   */
01734 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_GET_FLAG()       (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
01735
01736 /**
01737   * @brief Clear the RTC Tamper and Timestamp associated D2 Exti line flag.
01738   * @retval None
01739   */
01740 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG()     (EXTI_D2->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01741
01742 #endif  /* DUAL_CORE */
01743
01744 /**
01745   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
01746   * @retval None
01747   */
01748 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01749
01750 /**
01751   * @}
01752   */
01753
01754 /* Exported functions --------------------------------------------------------*/
01755
01756 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
01757   * @{
01758   */
01759
01760 /* ========================================================================== */
01761 /*                  ##### RTC TimeStamp exported functions #####              */
01762 /* ========================================================================== */
01763
01764 /* RTC TimeStamp functions ****************************************************/
01765
01766 /** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
01767   * @{
01768   */
01769 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01770 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01771 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
01772 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01773 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01774 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
01775 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
01776 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
01777 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01778 /**
01779   * @}
01780   */
01781
01782 /* ========================================================================== */
01783 /*                    ##### RTC Tamper exported functions #####               */
01784 /* ========================================================================== */
01785
01786 /* RTC Tamper functions *******************************************************/
01787
01788 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
01789   * @{
01790   */
01791 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
01792 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
01793 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
01794 #if defined(RTC_TAMPER_1)
01795 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01796 #endif /* RTC_TAMPER_1 */
01797 #if defined(RTC_TAMPER_2)
01798 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01799 #endif /* RTC_TAMPER_2 */
01800 #if defined(RTC_TAMPER_3)
01801 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01802 #endif /* RTC_TAMPER_3 */
01803 #if defined(RTC_TAMPER_1)
01804 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
01805 #endif /* RTC_TAMPER_1 */
01806 #if defined(RTC_TAMPER_2)
01807 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
01808 #endif /* RTC_TAMPER_2 */
01809 #if defined(RTC_TAMPER_3)
01810 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
01811 #endif /* RTC_TAMPER_3 */
01812 #if defined(TAMP_CR1_ITAMP1E)
01813 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
01814 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
01815 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
01816 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
01817 #endif /* TAMP_CR1_ITAMP1E */
01818 void              HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
01819 void              HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
01820 void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
01821 void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
01822 void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
01823 void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
01824 void              HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
01825 #if defined(TAMP_ATCR1_TAMP1AM)
01826 HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper);
01827 #endif /* TAMP_ATCR1_TAMP1AM */
01828 #if defined(TAMP_ATSEEDR_SEED)
01829 HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed);
01830 #endif /* TAMP_ATSEEDR_SEED */
01831 #if defined(TAMP_ATCR1_TAMP1AM)
01832 HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc);
01833 #endif /* TAMP_ATCR1_TAMP1AM */
01834 /**
01835   * @}
01836   */
01837
01838 /* ========================================================================== */
01839 /*                   ##### RTC Wake-up exported functions #####               */
01840 /* ========================================================================== */
01841
01842 /* RTC Wake-up functions ******************************************************/
01843
01844 /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
01845   * @{
01846   */
01847 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01848 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01849 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
01850 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
01851 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
01852 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
01853 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01854 /**
01855   * @}
01856   */
01857
01858 /* ========================================================================== */
01859 /*         ##### Extended RTC Backup registers exported functions #####       */
01860 /* ========================================================================== */
01861
01862 /* Extended RTC Backup registers functions ************************************/
01863
01864 /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
01865   * @{
01866   */
01867 void     HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
01868 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
01869 /**
01870   * @}
01871   */
01872
01873 /* ========================================================================== */
01874 /*        ##### Extended RTC Peripheral Control exported functions #####      */
01875 /* ========================================================================== */
01876
01877 /* Extended RTC Peripheral Control functions **********************************/
01878
01879 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
01880   * @{
01881   */
01882 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
01883 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
01884 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
01885 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
01886 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
01887 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
01888 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
01889 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
01890 #if defined(TAMP_COUNTR)
01891 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc);
01892 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter);
01893 #endif /* TAMP_COUNTR */
01894 /**
01895   * @}
01896   */
01897
01898 /* Extended RTC features functions *******************************************/
01899
01900 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01901   * @{
01902   */
01903
01904 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
01905 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01906 /**
01907   * @}
01908   */
01909
01910 /**
01911   * @}
01912   */
01913
01914 /* Private types -------------------------------------------------------------*/
01915 /* Private variables ---------------------------------------------------------*/
01916 /* Private constants ---------------------------------------------------------*/
01917 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
01918   * @{
01919   */
01920 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  EXTI_IMR1_IM18  /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
01921 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR1_IM19  /*!< External interrupt line 19 Connected to the RTC Wakeup event */
01922
01923 /* Masks Definition */
01924 #define RTC_TAMPER_X             ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))
01925 #define RTC_TAMPER_X_INTERRUPT   ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3))
01926
01927 /**
01928   * @}
01929   */
01930
01931 /* Private macros ------------------------------------------------------------*/
01932 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
01933   * @{
01934   */
01935
01936 /* ========================================================================== */
01937 /*          ##### Extended RTC Backup registers private macros #####          */
01938 /* ========================================================================== */
01939
01940 #define IS_RTC_BKP(__BKP__)                   ((__BKP__) < BKP_REG_NUMBER)
01941
01942 /* ========================================================================== */
01943 /*                  ##### RTC TimeStamp private macros #####                  */
01944 /* ========================================================================== */
01945
01946 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01947                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01948
01949 #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01950
01951 /* ========================================================================== */
01952 /*                    ##### RTC Wake-up private macros #####                  */
01953 /* ========================================================================== */
01954
01955 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
01956                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01957                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01958                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01959                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01960                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01961
01962 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
01963
01964 /* ========================================================================== */
01965 /*               ##### RTC Smooth Calibration private macros #####            */
01966 /* ========================================================================== */
01967
01968 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01969                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01970                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01971
01972 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01973                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01974
01975 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
01976
01977 /* ========================================================================== */
01978 /*          ##### Extended RTC Peripheral Control private macros #####        */
01979 /* ========================================================================== */
01980
01981 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01982                                  ((SEL) == RTC_SHIFTADD1S_SET))
01983
01984 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
01985
01986 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01987                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01988
01989 /* ========================================================================== */
01990 /*                    ##### RTC Tamper private macros #####                   */
01991 /* ========================================================================== */
01992
01993 #define IS_RTC_TAMPER(__TAMPER__)  ((((__TAMPER__) &  RTC_TAMPER_X) != 0x00U) &&  \
01994                                     (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U))
01995
01996 #if defined(RTC_ALL_TAMPER_INTERRUPT)
01997 #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                                                           \
01998               ((((__INTERRUPT__) & (  RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT )) != 0x00U) &&  \
01999                (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))) == 0x00U))
02000 #else  /* RTC_ALL_TAMPER_INTERRUPT not defined */
02001 #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                              \
02002               ((((__INTERRUPT__) &   RTC_TAMPER_X_INTERRUPT ) != 0x00U) &&  \
02003                (((__INTERRUPT__) & (~RTC_TAMPER_X_INTERRUPT)) == 0x00U))
02004 #endif /* RTC_ALL_TAMPER_INTERRUPT */
02005
02006 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \
02007                                             ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \
02008                                             ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)      || \
02009                                             ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
02010
02011 #define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
02012                                                         ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
02013
02014 #define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)        (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
02015                                                         ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
02016
02017 #define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
02018                                            ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
02019                                            ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
02020                                            ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
02021
02022 #define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
02023                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
02024                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
02025                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
02026                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
02027                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
02028                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
02029                                                ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
02030
02031 #define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
02032                                                         ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
02033                                                         ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
02034                                                         ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
02035
02036 #define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
02037                                                ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
02038
02039 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
02040                                                                   ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
02041
02042 #if defined(RTC_CR_TAMPOE)
02043 #define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__) (((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
02044                                                        ((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
02045 #endif /* RTC_CR_TAMPOE */
02046
02047 #define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER)            \
02048                   (  (  ((FILTER) != RTC_TAMPERFILTER_DISABLE)          \
02049                      && (  ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL)    \
02050                         || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
02051                   || (  ((FILTER) == RTC_TAMPERFILTER_DISABLE)          \
02052                      && (  ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE)  \
02053                         || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))
02054
02055 #define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) &  RTC_INT_TAMPER_ALL) != 0x00U) && \
02056                                                   (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
02057
02058 /**
02059   * @}
02060   */
02061
02062 /**
02063   * @}
02064   */
02065
02066 /**
02067   * @}
02068   */
02069
02070 #ifdef __cplusplus
02071 }
02072 #endif /* __cplusplus */
02073
02074 #endif /* STM32H7xx_HAL_RTC_EX_H */
02075
02076 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai.c Source File

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stm32h7xx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @brief   SAI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + I/O operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                   ##### How to use this driver #####
00016   ==============================================================================
00017
00018   [..]
00019     The SAI HAL driver can be used as follows:
00020
00021     (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
00022     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00023         (##) Enable the SAI interface clock.
00024         (##) SAI pins configuration:
00025             (+++) Enable the clock for the SAI GPIOs.
00026             (+++) Configure these SAI pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00028              and HAL_SAI_Receive_IT() APIs):
00029             (+++) Configure the SAI interrupt priority.
00030             (+++) Enable the NVIC SAI IRQ handle.
00031
00032         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00033              and HAL_SAI_Receive_DMA() APIs):
00034             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00035             (+++) Enable the DMAx interface clock.
00036             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00037             (+++) Configure the DMA Tx/Rx Stream.
00038             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00039             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00040                 DMA Tx/Rx Stream.
00041
00042     (#) The initialization can be done by two ways
00043         (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
00044         (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
00045
00046   [..]
00047     (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00048         will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
00049         inside the transmit and receive process.
00050   [..]
00051     (@) Make sure that either:
00052         (+@) PLLSAI1CLK output is configured or
00053         (+@) PLLSAI2CLK output is configured or
00054         (+@) PLLSAI3CLK output is configured or
00055         (+@) PLLSAI4ACLK output is configured or
00056         (+@) PLLSAI4BCLK output is configured or
00057         (+@) External clock source is configured after setting correctly
00058              the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
00059
00060   [..]
00061     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00062         for the external slaves even if there is no data in the FIFO, However FS signal
00063         generation is conditioned by the presence of data in the FIFO.
00064
00065   [..]
00066     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00067         and FS signal for the external slaves.
00068
00069   [..]
00070     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00071         (+@) First bit Offset <= (SLOT size - Data size)
00072         (+@) Data size <= SLOT size
00073         (+@) Number of SLOT x SLOT size = Frame length
00074         (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00075
00076   [..]
00077     (@) PDM interface can be activated through HAL_SAI_Init function.
00078         Please note that PDM interface is only available for SAI1 or SAI4 sub-block A.
00079         PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
00080
00081   [..]
00082     Three operation modes are available within this driver :
00083
00084     *** Polling mode IO operation ***
00085     =================================
00086     [..]
00087       (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00088       (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00089
00090     *** Interrupt mode IO operation ***
00091     ===================================
00092     [..]
00093       (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
00094       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00095           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00096       (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
00097       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00098           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00099       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00100           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00101
00102     *** DMA mode IO operation ***
00103     =============================
00104     [..]
00105       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00106       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00107           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00108       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
00109       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00110           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00111       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00112           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00113       (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00114       (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00115       (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00116
00117     *** SAI HAL driver additional function list ***
00118     ===============================================
00119     [..]
00120       Below the list the others API available SAI HAL driver :
00121
00122       (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
00123       (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
00124       (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
00125       (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
00126       (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
00127       (+) HAL_SAI_Abort(): Abort the current transfer
00128
00129     *** SAI HAL driver macros list ***
00130     ==================================
00131     [..]
00132       Below the list of most used macros in SAI HAL driver :
00133
00134       (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
00135       (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
00136       (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
00137       (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
00138       (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
00139           enabled or disabled
00140       (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
00141
00142     *** Callback registration ***
00143     =============================
00144     [..]
00145     The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
00146     allows the user to configure dynamically the driver callbacks.
00147     Use functions HAL_SAI_RegisterCallback() to register a user callback.
00148
00149     [..]
00150     Function HAL_SAI_RegisterCallback() allows to register following callbacks:
00151       (+) RxCpltCallback     : SAI receive complete.
00152       (+) RxHalfCpltCallback : SAI receive half complete.
00153       (+) TxCpltCallback     : SAI transmit complete.
00154       (+) TxHalfCpltCallback : SAI transmit half complete.
00155       (+) ErrorCallback      : SAI error.
00156       (+) MspInitCallback    : SAI MspInit.
00157       (+) MspDeInitCallback  : SAI MspDeInit.
00158     [..]
00159     This function takes as parameters the HAL peripheral handle, the callback ID
00160     and a pointer to the user callback function.
00161
00162     [..]
00163     Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
00164     weak (surcharged) function.
00165     HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00166     and the callback ID.
00167     [..]
00168     This function allows to reset following callbacks:
00169       (+) RxCpltCallback     : SAI receive complete.
00170       (+) RxHalfCpltCallback : SAI receive half complete.
00171       (+) TxCpltCallback     : SAI transmit complete.
00172       (+) TxHalfCpltCallback : SAI transmit half complete.
00173       (+) ErrorCallback      : SAI error.
00174       (+) MspInitCallback    : SAI MspInit.
00175       (+) MspDeInitCallback  : SAI MspDeInit.
00176
00177     [..]
00178     By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
00179     all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00180     examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
00181     Exception done for MspInit and MspDeInit callbacks that are respectively
00182     reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
00183     and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
00184     If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
00185     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00186
00187     [..]
00188     Callbacks can be registered/unregistered in READY state only.
00189     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00190     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00191     during the Init/DeInit.
00192     In that case first register the MspInit/MspDeInit user callbacks
00193     using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
00194     or HAL_SAI_Init function.
00195
00196     [..]
00197     When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
00198     not defined, the callback registering feature is not available
00199     and weak (surcharged) callbacks are used.
00200
00201   @endverbatim
00202   ******************************************************************************
00203   * @attention
00204   *
00205   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00206   * All rights reserved.</center></h2>
00207   *
00208   * This software component is licensed by ST under BSD 3-Clause license,
00209   * the "License"; You may not use this file except in compliance with the
00210   * License. You may obtain a copy of the License at:
00211   *                        opensource.org/licenses/BSD-3-Clause
00212   *
00213   ******************************************************************************
00214   */
00215
00216 /* Includes ------------------------------------------------------------------*/
00217 #include "stm32h7xx_hal.h"
00218
00219 /** @addtogroup STM32H7xx_HAL_Driver
00220   * @{
00221   */
00222
00223 /** @defgroup SAI SAI
00224   * @brief SAI HAL module driver
00225   * @{
00226   */
00227
00228 #ifdef HAL_SAI_MODULE_ENABLED
00229
00230 /* Private typedef -----------------------------------------------------------*/
00231 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00232   * @{
00233   */
00234 typedef enum
00235 {
00236   SAI_MODE_DMA,
00237   SAI_MODE_IT
00238 } SAI_ModeTypedef;
00239 /**
00240   * @}
00241   */
00242
00243 /* Private define ------------------------------------------------------------*/
00244 /** @defgroup SAI_Private_Constants  SAI Private Constants
00245   * @{
00246   */
00247 #define SAI_FIFO_SIZE            8U
00248 #define SAI_DEFAULT_TIMEOUT      4U
00249 #define SAI_LONG_TIMEOUT         1000U
00250 /**
00251   * @}
00252   */
00253
00254 /* Private macro -------------------------------------------------------------*/
00255 /* Private variables ---------------------------------------------------------*/
00256 /* Private function prototypes -----------------------------------------------*/
00257 /** @defgroup SAI_Private_Functions  SAI Private Functions
00258   * @{
00259   */
00260 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00261 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
00262 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00263 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00264
00265 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00266 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00267 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00268 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00269 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00270 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00271 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00272
00273 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00274 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00275 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00276 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00277 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00278 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported functions ---------------------------------------------------------*/
00284 /** @defgroup SAI_Exported_Functions SAI Exported Functions
00285   * @{
00286   */
00287
00288 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00289   * @brief    Initialization and Configuration functions
00290   *
00291 @verbatim
00292  ===============================================================================
00293              ##### Initialization and de-initialization functions #####
00294  ===============================================================================
00295   [..]  This subsection provides a set of functions allowing to initialize and
00296         de-initialize the SAIx peripheral:
00297
00298       (+) User must implement HAL_SAI_MspInit() function in which he configures
00299           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00300
00301       (+) Call the function HAL_SAI_Init() to configure the selected device with
00302           the selected configuration:
00303         (++) Mode (Master/slave TX/RX)
00304         (++) Protocol
00305         (++) Data Size
00306         (++) MCLK Output
00307         (++) Audio frequency
00308         (++) FIFO Threshold
00309         (++) Frame Config
00310         (++) Slot Config
00311         (++) PDM Config
00312
00313       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00314           of the selected SAI peripheral.
00315
00316 @endverbatim
00317   * @{
00318   */
00319
00320 /**
00321   * @brief  Initialize the structure FrameInit, SlotInit and the low part of
00322   *         Init according to the specified parameters and call the function
00323   *         HAL_SAI_Init to initialize the SAI block.
00324   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00325   *              the configuration information for SAI module.
00326   * @param  protocol one of the supported protocol @ref SAI_Protocol
00327   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
00328   *                   the configuration information for SAI module.
00329   * @param  nbslot Number of slot.
00330   * @retval HAL status
00331   */
00332 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00333 {
00334   HAL_StatusTypeDef status;
00335
00336   /* Check the parameters */
00337   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00338   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00339
00340   switch (protocol)
00341   {
00342     case SAI_I2S_STANDARD :
00343     case SAI_I2S_MSBJUSTIFIED :
00344     case SAI_I2S_LSBJUSTIFIED :
00345       status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00346       break;
00347     case SAI_PCM_LONG :
00348     case SAI_PCM_SHORT :
00349       status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00350       break;
00351     default :
00352       status = HAL_ERROR;
00353       break;
00354   }
00355
00356   if (status == HAL_OK)
00357   {
00358     status = HAL_SAI_Init(hsai);
00359   }
00360
00361   return status;
00362 }
00363
00364 /**
00365   * @brief  Initialize the SAI according to the specified parameters.
00366   *         in the SAI_InitTypeDef structure and initialize the associated handle.
00367   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00368   *              the configuration information for SAI module.
00369   * @retval HAL status
00370   */
00371 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00372 {
00373   uint32_t tmpregisterGCR;
00374   uint32_t ckstr_bits;
00375   uint32_t syncen_bits;
00376   SAI_TypeDef *SaiBaseAddress;
00377
00378   /* Check the SAI handle allocation */
00379   if (hsai == NULL)
00380   {
00381     return HAL_ERROR;
00382   }
00383
00384   /* check the instance */
00385   assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
00386
00387   /* Check the SAI Block parameters */
00388   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00389   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00390   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00391   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00392   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00393   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00394   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00395 #if defined(SAI_VER_V2_X)
00396   /* SAI Peripheral version depends on STM32H7 device revision ID */
00397   if (HAL_GetREVID() >= REV_ID_B) /* STM32H7xx Rev.B and above */
00398   {
00399     assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
00400   }
00401 #else /* SAI_VER_V2_1 */
00402   assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
00403 #endif /* SAI_VER_V2_X */
00404   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00405   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00406   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00407   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00408   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00409   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00410   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00411   assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
00412
00413   /* Check the SAI Block Frame parameters */
00414   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00415   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00416   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00417   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00418   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00419
00420   /* Check the SAI Block Slot parameters */
00421   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00422   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00423   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00424   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00425
00426   /* Check the SAI PDM parameters */
00427   assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
00428   if (hsai->Init.PdmInit.Activation == ENABLE)
00429   {
00430     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
00431     assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
00432     /* Check that SAI sub-block is SAI1 or SAI4 sub-block A, in master RX mode with free protocol */
00433 #if defined(SAI4)
00434     if (((hsai->Instance != SAI1_Block_A) && (hsai->Instance != SAI4_Block_A)) ||
00435          (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
00436          (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
00437     {
00438       return HAL_ERROR;
00439     }
00440 #else
00441     if ((hsai->Instance != SAI1_Block_A) ||
00442         (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
00443         (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
00444     {
00445       return HAL_ERROR;
00446     }
00447 #endif /* SAI4 */
00448   }
00449
00450   /* Get the SAI base address according to the SAI handle */
00451   if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00452   {
00453     SaiBaseAddress = SAI1;
00454   }
00455 #if defined(SAI2)
00456   else if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
00457   {
00458     SaiBaseAddress = SAI2;
00459   }
00460 #endif /* SAI2 */
00461 #if defined(SAI3)
00462   else if ((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
00463   {
00464     SaiBaseAddress = SAI3;
00465   }
00466 #endif /* SAI3 */
00467 #if defined(SAI4)
00468   else if ((hsai->Instance == SAI4_Block_A) || (hsai->Instance == SAI4_Block_B))
00469   {
00470     SaiBaseAddress = SAI4;
00471   }
00472 #endif /* SAI4 */
00473   else
00474   {
00475     return HAL_ERROR;
00476   }
00477
00478   if (hsai->State == HAL_SAI_STATE_RESET)
00479   {
00480     /* Allocate lock resource and initialize it */
00481     hsai->Lock = HAL_UNLOCKED;
00482
00483 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00484     /* Reset callback pointers to the weak predefined callbacks */
00485     hsai->RxCpltCallback     = HAL_SAI_RxCpltCallback;
00486     hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00487     hsai->TxCpltCallback     = HAL_SAI_TxCpltCallback;
00488     hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00489     hsai->ErrorCallback      = HAL_SAI_ErrorCallback;
00490
00491     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00492     if (hsai->MspInitCallback == NULL)
00493     {
00494       hsai->MspInitCallback = HAL_SAI_MspInit;
00495     }
00496     hsai->MspInitCallback(hsai);
00497 #else
00498     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00499     HAL_SAI_MspInit(hsai);
00500 #endif
00501   }
00502
00503   /* Disable the selected SAI peripheral */
00504   if(SAI_Disable(hsai) != HAL_OK)
00505   {
00506     return HAL_ERROR;
00507   }
00508
00509   hsai->State = HAL_SAI_STATE_BUSY;
00510
00511   /* SAI Block Synchro Configuration -----------------------------------------*/
00512   /* This setting must be done with both audio block (A & B) disabled         */
00513   switch (hsai->Init.SynchroExt)
00514   {
00515     case SAI_SYNCEXT_DISABLE :
00516       tmpregisterGCR = 0;
00517       break;
00518     case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00519       tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00520       break;
00521     case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00522       tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00523       break;
00524     default:
00525       tmpregisterGCR = 0;
00526       break;
00527   }
00528
00529   switch (hsai->Init.Synchro)
00530   {
00531     case SAI_ASYNCHRONOUS :
00532       syncen_bits = 0;
00533       break;
00534     case SAI_SYNCHRONOUS :
00535       syncen_bits = SAI_xCR1_SYNCEN_0;
00536       break;
00537     case SAI_SYNCHRONOUS_EXT_SAI1 :
00538       syncen_bits = SAI_xCR1_SYNCEN_1;
00539       break;
00540 #if defined(SAI2)
00541     case SAI_SYNCHRONOUS_EXT_SAI2 :
00542       syncen_bits = SAI_xCR1_SYNCEN_1;
00543       tmpregisterGCR |= SAI_GCR_SYNCIN_0;
00544       break;
00545 #endif /* SAI2 */
00546 #if defined(SAI3)
00547     case SAI_SYNCHRONOUS_EXT_SAI3 :
00548       syncen_bits = SAI_xCR1_SYNCEN_1;
00549       tmpregisterGCR |= SAI_GCR_SYNCIN_1;
00550       break;
00551 #endif /* SAI3 */
00552 #if defined(SAI4)
00553     case SAI_SYNCHRONOUS_EXT_SAI4 :
00554       syncen_bits = SAI_xCR1_SYNCEN_1;
00555       tmpregisterGCR |= (SAI_GCR_SYNCIN_1 | SAI_GCR_SYNCIN_0);
00556       break;
00557 #endif /* SAI4 */
00558     default:
00559       syncen_bits = 0;
00560       break;
00561   }
00562
00563   /* Set the SAI Block Synchro Configuration */
00564   SaiBaseAddress->GCR = tmpregisterGCR;
00565
00566   if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00567   {
00568     uint32_t freq = 0;
00569     uint32_t tmpval;
00570
00571     /* In this case, the MCKDIV value is calculated to get AudioFrequency */
00572     if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00573     {
00574       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00575     }
00576
00577 #if defined(SAI2)
00578 #if defined(RCC_PERIPHCLK_SAI2)
00579     if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
00580     {
00581       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
00582     }
00583 #else
00584     if (hsai->Instance == SAI2_Block_A)
00585     {
00586       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2A);
00587     }
00588     if (hsai->Instance == SAI2_Block_B)
00589     {
00590       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2B);
00591     }
00592 #endif /* RCC_PERIPHCLK_SAI2 */
00593 #endif /* SAI2 */
00594
00595 #if defined(SAI3)
00596     if ((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
00597     {
00598       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI3);
00599     }
00600 #endif /* SAI3 */
00601 #if defined(SAI4)
00602     if (hsai->Instance == SAI4_Block_A)
00603     {
00604       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4A);
00605     }
00606     if (hsai->Instance == SAI4_Block_B)
00607     {
00608       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4B);
00609     }
00610 #endif /* SAI4 */
00611
00612     /* Configure Master Clock Divider using the following formula :
00613        - If NODIV = 1 :
00614          MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
00615        - If NODIV = 0 :
00616          MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
00617     if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
00618     {
00619       /* NODIV = 1 */
00620       /* (freq x 10) to keep Significant digits */
00621       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
00622     }
00623     else
00624     {
00625       /* NODIV = 0 */
00626       uint32_t tmposr;
00627       tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
00628       /* (freq x 10) to keep Significant digits */
00629       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
00630     }
00631     hsai->Init.Mckdiv = tmpval / 10U;
00632
00633     /* Round result to the nearest integer */
00634     if ((tmpval % 10U) > 8U)
00635     {
00636       hsai->Init.Mckdiv += 1U;
00637     }
00638   }
00639
00640   /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
00641   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00642   {
00643     /* Transmit */
00644     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
00645   }
00646   else
00647   {
00648     /* Receive */
00649     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
00650   }
00651
00652   /* SAI Block Configuration -------------------------------------------------*/
00653   /* SAI CR1 Configuration */
00654 #if defined(SAI_VER_V2_X) /* SAI Peripheral version depends on STM32H7 device revision ID */
00655
00656   if (HAL_GetREVID() >= REV_ID_B) /* STM32H7xx Rev.B and above */
00657   {
00658     hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00659                              SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
00660                              SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00661                              SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR |     \
00662                              SAI_xCR1_MCKEN);
00663
00664     hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00665                             hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00666                             ckstr_bits | syncen_bits |                             \
00667                             hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00668                             hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00669                             hsai->Init.MckOverSampling | hsai->Init.MckOutput);
00670   }
00671   else /* STM32H7xx Rev.Y */
00672   {
00673     hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00674                              SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
00675                              SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00676                              SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR);
00677
00678     hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00679                             hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00680                             ckstr_bits | syncen_bits |                             \
00681                             hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00682                             hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00683                             hsai->Init.MckOverSampling);
00684   }
00685 #else /* SAI_VER_V2_1*/
00686   hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00687                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
00688                            SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00689                            SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR |     \
00690                            SAI_xCR1_MCKEN);
00691
00692   hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00693                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00694                           ckstr_bits | syncen_bits |                             \
00695                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00696                           hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00697                           hsai->Init.MckOverSampling | hsai->Init.MckOutput);
00698 #endif /* SAI_VER_V2_X */
00699
00700   /* SAI CR2 Configuration */
00701   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00702   hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00703
00704   /* SAI Frame Configuration -----------------------------------------*/
00705   hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00706                              SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
00707   hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
00708                            hsai->FrameInit.FSOffset |
00709                            hsai->FrameInit.FSDefinition |
00710                            hsai->FrameInit.FSPolarity   |
00711                            ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
00712
00713   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00714   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00715   hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |  \
00716                               SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
00717
00718   hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
00719                            (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) <<  8);
00720
00721   /* SAI PDM Configuration ---------------------------------------------------*/
00722 #if defined(SAI4)
00723   if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI4_Block_A))
00724 #else
00725   if (hsai->Instance == SAI1_Block_A)
00726 #endif /* SAI4 */
00727   {
00728     /* Disable PDM interface */
00729     SaiBaseAddress->PDMCR &= ~(SAI_PDMCR_PDMEN);
00730     if (hsai->Init.PdmInit.Activation == ENABLE)
00731     {
00732       /* Configure and enable PDM interface */
00733       SaiBaseAddress->PDMCR = (hsai->Init.PdmInit.ClockEnable |
00734                                ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
00735       SaiBaseAddress->PDMCR |= SAI_PDMCR_PDMEN;
00736     }
00737   }
00738
00739   /* Initialize the error code */
00740   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00741
00742   /* Initialize the SAI state */
00743   hsai->State = HAL_SAI_STATE_READY;
00744
00745   /* Release Lock */
00746   __HAL_UNLOCK(hsai);
00747
00748   return HAL_OK;
00749 }
00750
00751 /**
00752   * @brief  DeInitialize the SAI peripheral.
00753   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00754   *              the configuration information for SAI module.
00755   * @retval HAL status
00756   */
00757 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00758 {
00759   SAI_TypeDef *SaiBaseAddress;
00760
00761   /* Check the SAI handle allocation */
00762   if (hsai == NULL)
00763   {
00764     return HAL_ERROR;
00765   }
00766
00767   hsai->State = HAL_SAI_STATE_BUSY;
00768
00769   /* Disabled All interrupt and clear all the flag */
00770   hsai->Instance->IMR = 0;
00771   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00772
00773   /* Disable the SAI */
00774   if (SAI_Disable(hsai) != HAL_OK)
00775   {
00776     /* Reset SAI state to ready */
00777     hsai->State = HAL_SAI_STATE_READY;
00778
00779     /* Release Lock */
00780     __HAL_UNLOCK(hsai);
00781
00782     return HAL_ERROR;
00783   }
00784
00785   /* Flush the fifo */
00786   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00787
00788   /* Disable SAI PDM interface */
00789 #if defined(SAI4)
00790   if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI4_Block_A))
00791 #else
00792   if (hsai->Instance == SAI1_Block_A)
00793 #endif /* SAI4 */
00794   {
00795     /* Get the SAI base address according to the SAI handle */
00796 #if defined(SAI4)
00797     SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : SAI4;
00798 #else
00799     SaiBaseAddress = SAI1;
00800 #endif /* SAI4 */
00801
00802     /* Reset PDM delays */
00803     SaiBaseAddress->PDMDLY = 0U;
00804
00805     /* Disable PDM interface */
00806     SaiBaseAddress->PDMCR &= ~(SAI_PDMCR_PDMEN);
00807   }
00808
00809   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00810 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00811   if (hsai->MspDeInitCallback == NULL)
00812   {
00813     hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00814   }
00815   hsai->MspDeInitCallback(hsai);
00816 #else
00817   HAL_SAI_MspDeInit(hsai);
00818 #endif
00819
00820   /* Initialize the error code */
00821   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00822
00823   /* Initialize the SAI state */
00824   hsai->State = HAL_SAI_STATE_RESET;
00825
00826   /* Release Lock */
00827   __HAL_UNLOCK(hsai);
00828
00829   return HAL_OK;
00830 }
00831
00832 /**
00833   * @brief Initialize the SAI MSP.
00834   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00835   *              the configuration information for SAI module.
00836   * @retval None
00837   */
00838 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00839 {
00840   /* Prevent unused argument(s) compilation warning */
00841   UNUSED(hsai);
00842
00843   /* NOTE : This function should not be modified, when the callback is needed,
00844             the HAL_SAI_MspInit could be implemented in the user file
00845    */
00846 }
00847
00848 /**
00849   * @brief DeInitialize the SAI MSP.
00850   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00851   *              the configuration information for SAI module.
00852   * @retval None
00853   */
00854 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00855 {
00856   /* Prevent unused argument(s) compilation warning */
00857   UNUSED(hsai);
00858
00859   /* NOTE : This function should not be modified, when the callback is needed,
00860             the HAL_SAI_MspDeInit could be implemented in the user file
00861    */
00862 }
00863
00864 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00865 /**
00866   * @brief  Register a user SAI callback
00867   *         to be used instead of the weak predefined callback.
00868   * @param  hsai SAI handle.
00869   * @param  CallbackID ID of the callback to be registered.
00870   *         This parameter can be one of the following values:
00871   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00872   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00873   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00874   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00875   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00876   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00877   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00878   * @param  pCallback pointer to the callback function.
00879   * @retval HAL status.
00880   */
00881 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00882                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00883                                            pSAI_CallbackTypeDef      pCallback)
00884 {
00885   HAL_StatusTypeDef status = HAL_OK;
00886
00887   if (pCallback == NULL)
00888   {
00889     /* update the error code */
00890     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00891     /* update return status */
00892     status = HAL_ERROR;
00893   }
00894   else
00895   {
00896     if (HAL_SAI_STATE_READY == hsai->State)
00897     {
00898       switch (CallbackID)
00899       {
00900         case HAL_SAI_RX_COMPLETE_CB_ID :
00901           hsai->RxCpltCallback = pCallback;
00902           break;
00903         case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00904           hsai->RxHalfCpltCallback = pCallback;
00905           break;
00906         case HAL_SAI_TX_COMPLETE_CB_ID :
00907           hsai->TxCpltCallback = pCallback;
00908           break;
00909         case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00910           hsai->TxHalfCpltCallback = pCallback;
00911           break;
00912         case HAL_SAI_ERROR_CB_ID :
00913           hsai->ErrorCallback = pCallback;
00914           break;
00915         case HAL_SAI_MSPINIT_CB_ID :
00916           hsai->MspInitCallback = pCallback;
00917           break;
00918         case HAL_SAI_MSPDEINIT_CB_ID :
00919           hsai->MspDeInitCallback = pCallback;
00920           break;
00921         default :
00922           /* update the error code */
00923           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00924           /* update return status */
00925           status = HAL_ERROR;
00926           break;
00927       }
00928     }
00929     else if (HAL_SAI_STATE_RESET == hsai->State)
00930     {
00931       switch (CallbackID)
00932       {
00933         case HAL_SAI_MSPINIT_CB_ID :
00934           hsai->MspInitCallback = pCallback;
00935           break;
00936         case HAL_SAI_MSPDEINIT_CB_ID :
00937           hsai->MspDeInitCallback = pCallback;
00938           break;
00939         default :
00940           /* update the error code */
00941           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00942           /* update return status */
00943           status = HAL_ERROR;
00944           break;
00945       }
00946     }
00947     else
00948     {
00949       /* update the error code */
00950       hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00951       /* update return status */
00952       status = HAL_ERROR;
00953     }
00954   }
00955   return status;
00956 }
00957
00958 /**
00959   * @brief  Unregister a user SAI callback.
00960   *         SAI callback is redirected to the weak predefined callback.
00961   * @param  hsai SAI handle.
00962   * @param  CallbackID ID of the callback to be unregistered.
00963   *         This parameter can be one of the following values:
00964   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00965   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00966   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00967   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00968   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00969   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00970   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00971   * @retval HAL status.
00972   */
00973 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00974                                              HAL_SAI_CallbackIDTypeDef CallbackID)
00975 {
00976   HAL_StatusTypeDef status = HAL_OK;
00977
00978   if (HAL_SAI_STATE_READY == hsai->State)
00979   {
00980     switch (CallbackID)
00981     {
00982       case HAL_SAI_RX_COMPLETE_CB_ID :
00983         hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
00984         break;
00985       case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00986         hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00987         break;
00988       case HAL_SAI_TX_COMPLETE_CB_ID :
00989         hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
00990         break;
00991       case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00992         hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00993         break;
00994       case HAL_SAI_ERROR_CB_ID :
00995         hsai->ErrorCallback = HAL_SAI_ErrorCallback;
00996         break;
00997       case HAL_SAI_MSPINIT_CB_ID :
00998         hsai->MspInitCallback = HAL_SAI_MspInit;
00999         break;
01000       case HAL_SAI_MSPDEINIT_CB_ID :
01001         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
01002         break;
01003       default :
01004         /* update the error code */
01005         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
01006         /* update return status */
01007         status = HAL_ERROR;
01008         break;
01009     }
01010   }
01011   else if (HAL_SAI_STATE_RESET == hsai->State)
01012   {
01013     switch (CallbackID)
01014     {
01015       case HAL_SAI_MSPINIT_CB_ID :
01016         hsai->MspInitCallback = HAL_SAI_MspInit;
01017         break;
01018       case HAL_SAI_MSPDEINIT_CB_ID :
01019         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
01020         break;
01021       default :
01022         /* update the error code */
01023         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
01024         /* update return status */
01025         status = HAL_ERROR;
01026         break;
01027     }
01028   }
01029   else
01030   {
01031     /* update the error code */
01032     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
01033     /* update return status */
01034     status = HAL_ERROR;
01035   }
01036   return status;
01037 }
01038 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01039
01040 /**
01041   * @}
01042   */
01043
01044 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
01045   * @brief    Data transfers functions
01046   *
01047 @verbatim
01048   ==============================================================================
01049                       ##### IO operation functions #####
01050   ==============================================================================
01051   [..]
01052     This subsection provides a set of functions allowing to manage the SAI data
01053     transfers.
01054
01055     (+) There are two modes of transfer:
01056       (++) Blocking mode : The communication is performed in the polling mode.
01057            The status of all data processing is returned by the same function
01058            after finishing transfer.
01059       (++) No-Blocking mode : The communication is performed using Interrupts
01060            or DMA. These functions return the status of the transfer startup.
01061            The end of the data processing will be indicated through the
01062            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
01063            using DMA mode.
01064
01065     (+) Blocking mode functions are :
01066       (++) HAL_SAI_Transmit()
01067       (++) HAL_SAI_Receive()
01068
01069     (+) Non Blocking mode functions with Interrupt are :
01070       (++) HAL_SAI_Transmit_IT()
01071       (++) HAL_SAI_Receive_IT()
01072
01073     (+) Non Blocking mode functions with DMA are :
01074       (++) HAL_SAI_Transmit_DMA()
01075       (++) HAL_SAI_Receive_DMA()
01076
01077     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
01078       (++) HAL_SAI_TxCpltCallback()
01079       (++) HAL_SAI_RxCpltCallback()
01080       (++) HAL_SAI_ErrorCallback()
01081
01082 @endverbatim
01083   * @{
01084   */
01085
01086 /**
01087   * @brief  Transmit an amount of data in blocking mode.
01088   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01089   *              the configuration information for SAI module.
01090   * @param  pData Pointer to data buffer
01091   * @param  Size Amount of data to be sent
01092   * @param  Timeout Timeout duration
01093   * @retval HAL status
01094   */
01095 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01096 {
01097   uint32_t tickstart = HAL_GetTick();
01098   uint32_t temp;
01099
01100   if ((pData == NULL) || (Size == 0U))
01101   {
01102     return  HAL_ERROR;
01103   }
01104
01105   if (hsai->State == HAL_SAI_STATE_READY)
01106   {
01107     /* Process Locked */
01108     __HAL_LOCK(hsai);
01109
01110     hsai->XferSize = Size;
01111     hsai->XferCount = Size;
01112     hsai->pBuffPtr = pData;
01113     hsai->State = HAL_SAI_STATE_BUSY_TX;
01114     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01115
01116     /* Check if the SAI is already enabled */
01117     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01118     {
01119       /* fill the fifo with data before to enabled the SAI */
01120       SAI_FillFifo(hsai);
01121       /* Enable SAI peripheral */
01122       __HAL_SAI_ENABLE(hsai);
01123     }
01124
01125     while (hsai->XferCount > 0U)
01126     {
01127       /* Write data if the FIFO is not full */
01128       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
01129       {
01130         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01131         {
01132           hsai->Instance->DR = *hsai->pBuffPtr;
01133           hsai->pBuffPtr++;
01134         }
01135         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01136         {
01137           temp = (uint32_t)(*hsai->pBuffPtr);
01138           hsai->pBuffPtr++;
01139           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
01140           hsai->pBuffPtr++;
01141           hsai->Instance->DR = temp;
01142         }
01143         else
01144         {
01145           temp = (uint32_t)(*hsai->pBuffPtr);
01146           hsai->pBuffPtr++;
01147           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
01148           hsai->pBuffPtr++;
01149           temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
01150           hsai->pBuffPtr++;
01151           temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
01152           hsai->pBuffPtr++;
01153           hsai->Instance->DR = temp;
01154         }
01155         hsai->XferCount--;
01156       }
01157       else
01158       {
01159         /* Check for the Timeout */
01160         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01161         {
01162           /* Update error code */
01163           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01164
01165           /* Clear all the flags */
01166           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01167
01168           /* Disable SAI peripheral */
01169           /* No need to check return value because state update, unlock and error return will be performed later */
01170           (void) SAI_Disable(hsai);
01171
01172           /* Flush the fifo */
01173           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01174
01175           /* Change the SAI state */
01176           hsai->State = HAL_SAI_STATE_READY;
01177
01178           /* Process Unlocked */
01179           __HAL_UNLOCK(hsai);
01180
01181           return HAL_ERROR;
01182         }
01183       }
01184     }
01185
01186     hsai->State = HAL_SAI_STATE_READY;
01187
01188     /* Process Unlocked */
01189     __HAL_UNLOCK(hsai);
01190
01191     return HAL_OK;
01192   }
01193   else
01194   {
01195     return HAL_BUSY;
01196   }
01197 }
01198
01199 /**
01200   * @brief  Receive an amount of data in blocking mode.
01201   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01202   *              the configuration information for SAI module.
01203   * @param  pData Pointer to data buffer
01204   * @param  Size Amount of data to be received
01205   * @param  Timeout Timeout duration
01206   * @retval HAL status
01207   */
01208 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01209 {
01210   uint32_t tickstart = HAL_GetTick();
01211   uint32_t temp;
01212
01213   if ((pData == NULL) || (Size == 0U))
01214   {
01215     return  HAL_ERROR;
01216   }
01217
01218   if (hsai->State == HAL_SAI_STATE_READY)
01219   {
01220     /* Process Locked */
01221     __HAL_LOCK(hsai);
01222
01223     hsai->pBuffPtr = pData;
01224     hsai->XferSize = Size;
01225     hsai->XferCount = Size;
01226     hsai->State = HAL_SAI_STATE_BUSY_RX;
01227     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01228
01229     /* Check if the SAI is already enabled */
01230     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01231     {
01232       /* Enable SAI peripheral */
01233       __HAL_SAI_ENABLE(hsai);
01234     }
01235
01236     /* Receive data */
01237     while (hsai->XferCount > 0U)
01238     {
01239       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
01240       {
01241         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01242         {
01243           *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
01244           hsai->pBuffPtr++;
01245         }
01246         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01247         {
01248           temp = hsai->Instance->DR;
01249           *hsai->pBuffPtr = (uint8_t)temp;
01250           hsai->pBuffPtr++;
01251           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01252           hsai->pBuffPtr++;
01253         }
01254         else
01255         {
01256           temp = hsai->Instance->DR;
01257           *hsai->pBuffPtr = (uint8_t)temp;
01258           hsai->pBuffPtr++;
01259           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01260           hsai->pBuffPtr++;
01261           *hsai->pBuffPtr = (uint8_t)(temp >> 16);
01262           hsai->pBuffPtr++;
01263           *hsai->pBuffPtr = (uint8_t)(temp >> 24);
01264           hsai->pBuffPtr++;
01265         }
01266         hsai->XferCount--;
01267       }
01268       else
01269       {
01270         /* Check for the Timeout */
01271         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01272         {
01273           /* Update error code */
01274           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01275
01276           /* Clear all the flags */
01277           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01278
01279           /* Disable SAI peripheral */
01280           /* No need to check return value because state update, unlock and error return will be performed later */
01281           (void) SAI_Disable(hsai);
01282
01283           /* Flush the fifo */
01284           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01285
01286           /* Change the SAI state */
01287           hsai->State = HAL_SAI_STATE_READY;
01288
01289           /* Process Unlocked */
01290           __HAL_UNLOCK(hsai);
01291
01292           return HAL_ERROR;
01293         }
01294       }
01295     }
01296
01297     hsai->State = HAL_SAI_STATE_READY;
01298
01299     /* Process Unlocked */
01300     __HAL_UNLOCK(hsai);
01301
01302     return HAL_OK;
01303   }
01304   else
01305   {
01306     return HAL_BUSY;
01307   }
01308 }
01309
01310 /**
01311   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01312   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01313   *              the configuration information for SAI module.
01314   * @param  pData Pointer to data buffer
01315   * @param  Size Amount of data to be sent
01316   * @retval HAL status
01317   */
01318 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01319 {
01320   if ((pData == NULL) || (Size == 0U))
01321   {
01322     return  HAL_ERROR;
01323   }
01324
01325   if (hsai->State == HAL_SAI_STATE_READY)
01326   {
01327     /* Process Locked */
01328     __HAL_LOCK(hsai);
01329
01330     hsai->pBuffPtr = pData;
01331     hsai->XferSize = Size;
01332     hsai->XferCount = Size;
01333     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01334     hsai->State = HAL_SAI_STATE_BUSY_TX;
01335
01336     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01337     {
01338       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
01339     }
01340     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01341     {
01342       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
01343     }
01344     else
01345     {
01346       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
01347     }
01348
01349     /* Fill the fifo before starting the communication */
01350     SAI_FillFifo(hsai);
01351
01352     /* Enable FRQ and OVRUDR interrupts */
01353     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01354
01355     /* Check if the SAI is already enabled */
01356     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01357     {
01358       /* Enable SAI peripheral */
01359       __HAL_SAI_ENABLE(hsai);
01360     }
01361     /* Process Unlocked */
01362     __HAL_UNLOCK(hsai);
01363
01364     return HAL_OK;
01365   }
01366   else
01367   {
01368     return HAL_BUSY;
01369   }
01370 }
01371
01372 /**
01373   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01374   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01375   *              the configuration information for SAI module.
01376   * @param  pData Pointer to data buffer
01377   * @param  Size Amount of data to be received
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01381 {
01382   if ((pData == NULL) || (Size == 0U))
01383   {
01384     return  HAL_ERROR;
01385   }
01386
01387   if (hsai->State == HAL_SAI_STATE_READY)
01388   {
01389     /* Process Locked */
01390     __HAL_LOCK(hsai);
01391
01392     hsai->pBuffPtr = pData;
01393     hsai->XferSize = Size;
01394     hsai->XferCount = Size;
01395     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01396     hsai->State = HAL_SAI_STATE_BUSY_RX;
01397
01398     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01399     {
01400       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
01401     }
01402     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01403     {
01404       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
01405     }
01406     else
01407     {
01408       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
01409     }
01410
01411     /* Enable TXE and OVRUDR interrupts */
01412     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01413
01414     /* Check if the SAI is already enabled */
01415     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01416     {
01417       /* Enable SAI peripheral */
01418       __HAL_SAI_ENABLE(hsai);
01419     }
01420
01421     /* Process Unlocked */
01422     __HAL_UNLOCK(hsai);
01423
01424     return HAL_OK;
01425   }
01426   else
01427   {
01428     return HAL_BUSY;
01429   }
01430 }
01431
01432 /**
01433   * @brief Pause the audio stream playing from the Media.
01434   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01435   *              the configuration information for SAI module.
01436   * @retval HAL status
01437   */
01438 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
01439 {
01440   /* Process Locked */
01441   __HAL_LOCK(hsai);
01442
01443   /* Pause the audio file playing by disabling the SAI DMA requests */
01444   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01445
01446   /* Process Unlocked */
01447   __HAL_UNLOCK(hsai);
01448
01449   return HAL_OK;
01450 }
01451
01452 /**
01453   * @brief Resume the audio stream playing from the Media.
01454   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01455   *              the configuration information for SAI module.
01456   * @retval HAL status
01457   */
01458 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
01459 {
01460   /* Process Locked */
01461   __HAL_LOCK(hsai);
01462
01463   /* Enable the SAI DMA requests */
01464   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01465
01466   /* If the SAI peripheral is still not enabled, enable it */
01467   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01468   {
01469     /* Enable SAI peripheral */
01470     __HAL_SAI_ENABLE(hsai);
01471   }
01472
01473   /* Process Unlocked */
01474   __HAL_UNLOCK(hsai);
01475
01476   return HAL_OK;
01477 }
01478
01479 /**
01480   * @brief Stop the audio stream playing from the Media.
01481   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01482   *              the configuration information for SAI module.
01483   * @retval HAL status
01484   */
01485 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
01486 {
01487   HAL_StatusTypeDef status = HAL_OK;
01488
01489   /* Process Locked */
01490   __HAL_LOCK(hsai);
01491
01492   /* Disable the SAI DMA request */
01493   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01494
01495   /* Abort the SAI Tx DMA Stream */
01496   if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
01497   {
01498     if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01499     {
01500       /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
01501       if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01502       {
01503         status = HAL_ERROR;
01504         hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01505       }
01506     }
01507   }
01508
01509   /* Abort the SAI Rx DMA Stream */
01510   if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01511   {
01512     if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01513     {
01514       /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
01515       if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01516       {
01517         status = HAL_ERROR;
01518         hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01519       }
01520     }
01521   }
01522
01523   /* Disable SAI peripheral */
01524   if (SAI_Disable(hsai) != HAL_OK)
01525   {
01526     status = HAL_ERROR;
01527   }
01528
01529   /* Flush the fifo */
01530   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01531
01532   /* Set hsai state to ready */
01533   hsai->State = HAL_SAI_STATE_READY;
01534
01535   /* Process Unlocked */
01536   __HAL_UNLOCK(hsai);
01537
01538   return status;
01539 }
01540
01541 /**
01542   * @brief Abort the current transfer and disable the SAI.
01543   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01544   *              the configuration information for SAI module.
01545   * @retval HAL status
01546   */
01547 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
01548 {
01549   HAL_StatusTypeDef status = HAL_OK;
01550
01551   /* Process Locked */
01552   __HAL_LOCK(hsai);
01553
01554   /* Check SAI DMA is enabled or not */
01555   if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01556   {
01557     /* Disable the SAI DMA request */
01558     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01559
01560     /* Abort the SAI Tx DMA Stream */
01561     if ((hsai->State == HAL_SAI_STATE_BUSY_TX)&& (hsai->hdmatx != NULL))
01562     {
01563       if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01564       {
01565         /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
01566         if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01567         {
01568           status = HAL_ERROR;
01569           hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01570         }
01571       }
01572     }
01573
01574     /* Abort the SAI Rx DMA Stream */
01575     if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01576     {
01577       if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01578       {
01579         /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
01580         if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01581         {
01582           status = HAL_ERROR;
01583           hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01584         }
01585       }
01586     }
01587   }
01588
01589   /* Disabled All interrupt and clear all the flag */
01590   hsai->Instance->IMR = 0;
01591   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01592
01593   /* Disable SAI peripheral */
01594   if (SAI_Disable(hsai) != HAL_OK)
01595   {
01596     status = HAL_ERROR;
01597   }
01598
01599   /* Flush the fifo */
01600   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01601
01602   /* Set hsai state to ready */
01603   hsai->State = HAL_SAI_STATE_READY;
01604
01605   /* Process Unlocked */
01606   __HAL_UNLOCK(hsai);
01607
01608   return status;
01609 }
01610
01611 /**
01612   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01613   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01614   *              the configuration information for SAI module.
01615   * @param  pData Pointer to data buffer
01616   * @param  Size Amount of data to be sent
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01620 {
01621   uint32_t tickstart = HAL_GetTick();
01622
01623   if ((pData == NULL) || (Size == 0U))
01624   {
01625     return  HAL_ERROR;
01626   }
01627
01628   if (hsai->State == HAL_SAI_STATE_READY)
01629   {
01630     /* Process Locked */
01631     __HAL_LOCK(hsai);
01632
01633     hsai->pBuffPtr = pData;
01634     hsai->XferSize = Size;
01635     hsai->XferCount = Size;
01636     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01637     hsai->State = HAL_SAI_STATE_BUSY_TX;
01638
01639     /* Set the SAI Tx DMA Half transfer complete callback */
01640     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01641
01642     /* Set the SAI TxDMA transfer complete callback */
01643     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01644
01645     /* Set the DMA error callback */
01646     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01647
01648     /* Set the DMA Tx abort callback */
01649     hsai->hdmatx->XferAbortCallback = NULL;
01650
01651     /* Enable the Tx DMA Stream */
01652     if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
01653     {
01654       __HAL_UNLOCK(hsai);
01655       return  HAL_ERROR;
01656     }
01657
01658     /* Enable the interrupts for error handling */
01659     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01660
01661     /* Enable SAI Tx DMA Request */
01662     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01663
01664     /* Wait untill FIFO is not empty */
01665     while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
01666     {
01667       /* Check for the Timeout */
01668       if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
01669       {
01670         /* Update error code */
01671         hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01672
01673         /* Process Unlocked */
01674         __HAL_UNLOCK(hsai);
01675
01676         return HAL_TIMEOUT;
01677       }
01678     }
01679
01680     /* Check if the SAI is already enabled */
01681     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01682     {
01683       /* Enable SAI peripheral */
01684       __HAL_SAI_ENABLE(hsai);
01685     }
01686
01687     /* Process Unlocked */
01688     __HAL_UNLOCK(hsai);
01689
01690     return HAL_OK;
01691   }
01692   else
01693   {
01694     return HAL_BUSY;
01695   }
01696 }
01697
01698 /**
01699   * @brief  Receive an amount of data in non-blocking mode with DMA.
01700   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01701   *              the configuration information for SAI module.
01702   * @param  pData Pointer to data buffer
01703   * @param  Size Amount of data to be received
01704   * @retval HAL status
01705   */
01706 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01707 {
01708
01709   if ((pData == NULL) || (Size == 0U))
01710   {
01711     return  HAL_ERROR;
01712   }
01713
01714   if (hsai->State == HAL_SAI_STATE_READY)
01715   {
01716     /* Process Locked */
01717     __HAL_LOCK(hsai);
01718
01719     hsai->pBuffPtr = pData;
01720     hsai->XferSize = Size;
01721     hsai->XferCount = Size;
01722     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01723     hsai->State = HAL_SAI_STATE_BUSY_RX;
01724
01725     /* Set the SAI Rx DMA Half transfer complete callback */
01726     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01727
01728     /* Set the SAI Rx DMA transfer complete callback */
01729     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01730
01731     /* Set the DMA error callback */
01732     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01733
01734     /* Set the DMA Rx abort callback */
01735     hsai->hdmarx->XferAbortCallback = NULL;
01736
01737     /* Enable the Rx DMA Stream */
01738     if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
01739     {
01740       __HAL_UNLOCK(hsai);
01741       return  HAL_ERROR;
01742     }
01743
01744     /* Enable the interrupts for error handling */
01745     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01746
01747     /* Enable SAI Rx DMA Request */
01748     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01749
01750     /* Check if the SAI is already enabled */
01751     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01752     {
01753       /* Enable SAI peripheral */
01754       __HAL_SAI_ENABLE(hsai);
01755     }
01756
01757     /* Process Unlocked */
01758     __HAL_UNLOCK(hsai);
01759
01760     return HAL_OK;
01761   }
01762   else
01763   {
01764     return HAL_BUSY;
01765   }
01766 }
01767
01768 /**
01769   * @brief  Enable the Tx mute mode.
01770   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01771   *              the configuration information for SAI module.
01772   * @param  val  value sent during the mute @ref SAI_Block_Mute_Value
01773   * @retval HAL status
01774   */
01775 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01776 {
01777   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01778
01779   if (hsai->State != HAL_SAI_STATE_RESET)
01780   {
01781     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01782     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
01783     return HAL_OK;
01784   }
01785   return HAL_ERROR;
01786 }
01787
01788 /**
01789   * @brief  Disable the Tx mute mode.
01790   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01791   *              the configuration information for SAI module.
01792   * @retval HAL status
01793   */
01794 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01795 {
01796   if (hsai->State != HAL_SAI_STATE_RESET)
01797   {
01798     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01799     return HAL_OK;
01800   }
01801   return HAL_ERROR;
01802 }
01803
01804 /**
01805   * @brief  Enable the Rx mute detection.
01806   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01807   *              the configuration information for SAI module.
01808   * @param  callback function called when the mute is detected.
01809   * @param  counter number a data before mute detection max 63.
01810   * @retval HAL status
01811   */
01812 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01813 {
01814   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01815
01816   if (hsai->State != HAL_SAI_STATE_RESET)
01817   {
01818     /* set the mute counter */
01819     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01820     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
01821     hsai->mutecallback = callback;
01822     /* enable the IT interrupt */
01823     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01824     return HAL_OK;
01825   }
01826   return HAL_ERROR;
01827 }
01828
01829 /**
01830   * @brief  Disable the Rx mute detection.
01831   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01832   *              the configuration information for SAI module.
01833   * @retval HAL status
01834   */
01835 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01836 {
01837   if (hsai->State != HAL_SAI_STATE_RESET)
01838   {
01839     /* set the mutecallback to NULL */
01840     hsai->mutecallback = NULL;
01841     /* enable the IT interrupt */
01842     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01843     return HAL_OK;
01844   }
01845   return HAL_ERROR;
01846 }
01847
01848 /**
01849   * @brief  Handle SAI interrupt request.
01850   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01851   *              the configuration information for SAI module.
01852   * @retval None
01853   */
01854 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01855 {
01856   if (hsai->State != HAL_SAI_STATE_RESET)
01857   {
01858     uint32_t itflags = hsai->Instance->SR;
01859     uint32_t itsources = hsai->Instance->IMR;
01860     uint32_t cr1config = hsai->Instance->CR1;
01861     uint32_t tmperror;
01862
01863     /* SAI Fifo request interrupt occured ------------------------------------*/
01864     if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
01865     {
01866       hsai->InterruptServiceRoutine(hsai);
01867     }
01868     /* SAI Overrun error interrupt occurred ----------------------------------*/
01869     else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01870     {
01871       /* Clear the SAI Overrun flag */
01872       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01873       /* Get the SAI error code */
01874       tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01875       /* Change the SAI error code */
01876       hsai->ErrorCode |= tmperror;
01877       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01878 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01879       hsai->ErrorCallback(hsai);
01880 #else
01881       HAL_SAI_ErrorCallback(hsai);
01882 #endif
01883     }
01884     /* SAI mutedet interrupt occurred ----------------------------------*/
01885     else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01886     {
01887       /* Clear the SAI mutedet flag */
01888       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01889       /* call the call back function */
01890       if (hsai->mutecallback != NULL)
01891       {
01892         /* inform the user that an RX mute event has been detected */
01893         hsai->mutecallback();
01894       }
01895     }
01896     /* SAI AFSDET interrupt occurred ----------------------------------*/
01897     else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01898     {
01899       /* Clear the SAI AFSDET flag */
01900       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
01901
01902       /* Change the SAI error code */
01903       hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
01904
01905       /* Check SAI DMA is enabled or not */
01906       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01907       {
01908         /* Abort the SAI DMA Streams */
01909         if (hsai->hdmatx != NULL)
01910         {
01911           /* Set the DMA Tx abort callback */
01912           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01913
01914           /* Abort DMA in IT mode */
01915           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01916           {
01917             /* Update SAI error code */
01918             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01919
01920             /* Call SAI error callback */
01921 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01922             hsai->ErrorCallback(hsai);
01923 #else
01924             HAL_SAI_ErrorCallback(hsai);
01925 #endif
01926           }
01927         }
01928         if (hsai->hdmarx != NULL)
01929         {
01930           /* Set the DMA Rx abort callback */
01931           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01932
01933           /* Abort DMA in IT mode */
01934           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01935           {
01936             /* Update SAI error code */
01937             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01938
01939             /* Call SAI error callback */
01940 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01941             hsai->ErrorCallback(hsai);
01942 #else
01943             HAL_SAI_ErrorCallback(hsai);
01944 #endif
01945           }
01946         }
01947       }
01948       else
01949       {
01950         /* Abort SAI */
01951         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
01952         (void) HAL_SAI_Abort(hsai);
01953
01954         /* Set error callback */
01955 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01956         hsai->ErrorCallback(hsai);
01957 #else
01958         HAL_SAI_ErrorCallback(hsai);
01959 #endif
01960       }
01961     }
01962     /* SAI LFSDET interrupt occurred ----------------------------------*/
01963     else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01964     {
01965       /* Clear the SAI LFSDET flag */
01966       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
01967
01968       /* Change the SAI error code */
01969       hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
01970
01971       /* Check SAI DMA is enabled or not */
01972       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01973       {
01974         /* Abort the SAI DMA Streams */
01975         if (hsai->hdmatx != NULL)
01976         {
01977           /* Set the DMA Tx abort callback */
01978           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01979
01980           /* Abort DMA in IT mode */
01981           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01982           {
01983             /* Update SAI error code */
01984             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01985
01986             /* Call SAI error callback */
01987 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01988             hsai->ErrorCallback(hsai);
01989 #else
01990             HAL_SAI_ErrorCallback(hsai);
01991 #endif
01992           }
01993         }
01994         if (hsai->hdmarx != NULL)
01995         {
01996           /* Set the DMA Rx abort callback */
01997           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01998
01999           /* Abort DMA in IT mode */
02000           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
02001           {
02002             /* Update SAI error code */
02003             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02004
02005             /* Call SAI error callback */
02006 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02007             hsai->ErrorCallback(hsai);
02008 #else
02009             HAL_SAI_ErrorCallback(hsai);
02010 #endif
02011           }
02012         }
02013       }
02014       else
02015       {
02016         /* Abort SAI */
02017         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
02018         (void) HAL_SAI_Abort(hsai);
02019
02020         /* Set error callback */
02021 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02022         hsai->ErrorCallback(hsai);
02023 #else
02024         HAL_SAI_ErrorCallback(hsai);
02025 #endif
02026       }
02027     }
02028     /* SAI WCKCFG interrupt occurred ----------------------------------*/
02029     else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
02030     {
02031       /* Clear the SAI WCKCFG flag */
02032       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
02033
02034       /* Change the SAI error code */
02035       hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
02036
02037       /* Check SAI DMA is enabled or not */
02038       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
02039       {
02040         /* Abort the SAI DMA Streams */
02041         if (hsai->hdmatx != NULL)
02042         {
02043           /* Set the DMA Tx abort callback */
02044           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
02045
02046           /* Abort DMA in IT mode */
02047           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
02048           {
02049             /* Update SAI error code */
02050             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02051
02052             /* Call SAI error callback */
02053 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02054             hsai->ErrorCallback(hsai);
02055 #else
02056             HAL_SAI_ErrorCallback(hsai);
02057 #endif
02058           }
02059         }
02060         if (hsai->hdmarx != NULL)
02061         {
02062           /* Set the DMA Rx abort callback */
02063           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
02064
02065           /* Abort DMA in IT mode */
02066           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
02067           {
02068             /* Update SAI error code */
02069             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02070
02071             /* Call SAI error callback */
02072 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02073             hsai->ErrorCallback(hsai);
02074 #else
02075             HAL_SAI_ErrorCallback(hsai);
02076 #endif
02077           }
02078         }
02079       }
02080       else
02081       {
02082         /* If WCKCFG occurs, SAI audio block is automatically disabled */
02083         /* Disable all interrupts and clear all flags */
02084         hsai->Instance->IMR = 0U;
02085         hsai->Instance->CLRFR = 0xFFFFFFFFU;
02086         /* Set the SAI state to ready to be able to start again the process */
02087         hsai->State = HAL_SAI_STATE_READY;
02088
02089         /* Initialize XferCount */
02090         hsai->XferCount = 0U;
02091
02092         /* SAI error Callback */
02093 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02094         hsai->ErrorCallback(hsai);
02095 #else
02096         HAL_SAI_ErrorCallback(hsai);
02097 #endif
02098       }
02099     }
02100     /* SAI CNRDY interrupt occurred ----------------------------------*/
02101     else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
02102     {
02103       /* Clear the SAI CNRDY flag */
02104       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
02105       /* Change the SAI error code */
02106       hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
02107       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
02108 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02109       hsai->ErrorCallback(hsai);
02110 #else
02111       HAL_SAI_ErrorCallback(hsai);
02112 #endif
02113     }
02114     else
02115     {
02116       /* Nothing to do */
02117     }
02118   }
02119 }
02120
02121 /**
02122   * @brief Tx Transfer completed callback.
02123   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02124   *              the configuration information for SAI module.
02125   * @retval None
02126   */
02127 __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
02128 {
02129   /* Prevent unused argument(s) compilation warning */
02130   UNUSED(hsai);
02131
02132   /* NOTE : This function should not be modified, when the callback is needed,
02133             the HAL_SAI_TxCpltCallback could be implemented in the user file
02134    */
02135 }
02136
02137 /**
02138   * @brief Tx Transfer Half completed callback.
02139   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02140   *              the configuration information for SAI module.
02141   * @retval None
02142   */
02143 __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
02144 {
02145   /* Prevent unused argument(s) compilation warning */
02146   UNUSED(hsai);
02147
02148   /* NOTE : This function should not be modified, when the callback is needed,
02149             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
02150    */
02151 }
02152
02153 /**
02154   * @brief Rx Transfer completed callback.
02155   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02156   *              the configuration information for SAI module.
02157   * @retval None
02158   */
02159 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
02160 {
02161   /* Prevent unused argument(s) compilation warning */
02162   UNUSED(hsai);
02163
02164   /* NOTE : This function should not be modified, when the callback is needed,
02165             the HAL_SAI_RxCpltCallback could be implemented in the user file
02166    */
02167 }
02168
02169 /**
02170   * @brief Rx Transfer half completed callback.
02171   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02172   *              the configuration information for SAI module.
02173   * @retval None
02174   */
02175 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
02176 {
02177   /* Prevent unused argument(s) compilation warning */
02178   UNUSED(hsai);
02179
02180   /* NOTE : This function should not be modified, when the callback is needed,
02181             the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
02182    */
02183 }
02184
02185 /**
02186   * @brief SAI error callback.
02187   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02188   *              the configuration information for SAI module.
02189   * @retval None
02190   */
02191 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
02192 {
02193   /* Prevent unused argument(s) compilation warning */
02194   UNUSED(hsai);
02195
02196   /* NOTE : This function should not be modified, when the callback is needed,
02197             the HAL_SAI_ErrorCallback could be implemented in the user file
02198    */
02199 }
02200
02201 /**
02202   * @}
02203   */
02204
02205 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
02206   * @brief    Peripheral State functions
02207   *
02208 @verbatim
02209   ===============================================================================
02210                 ##### Peripheral State and Errors functions #####
02211   ===============================================================================
02212   [..]
02213     This subsection permits to get in run-time the status of the peripheral
02214     and the data flow.
02215
02216 @endverbatim
02217   * @{
02218   */
02219
02220 /**
02221   * @brief  Return the SAI handle state.
02222   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02223   *              the configuration information for SAI module.
02224   * @retval HAL state
02225   */
02226 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
02227 {
02228   return hsai->State;
02229 }
02230
02231 /**
02232   * @brief  Return the SAI error code.
02233   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02234   *              the configuration information for the specified SAI Block.
02235   * @retval SAI Error Code
02236   */
02237 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
02238 {
02239   return hsai->ErrorCode;
02240 }
02241
02242 /**
02243   * @}
02244   */
02245
02246 /**
02247   * @}
02248   */
02249
02250 /** @addtogroup SAI_Private_Functions
02251   * @brief      Private functions
02252   * @{
02253   */
02254
02255 /**
02256   * @brief  Initialize the SAI I2S protocol according to the specified parameters
02257   *         in the SAI_InitTypeDef and create the associated handle.
02258   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02259   *              the configuration information for SAI module.
02260   * @param  protocol one of the supported protocol.
02261   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize.
02262   * @param  nbslot number of slot minimum value is 2 and max is 16.
02263   *         the value must be a multiple of 2.
02264   * @retval HAL status
02265   */
02266 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02267 {
02268   HAL_StatusTypeDef status = HAL_OK;
02269
02270   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02271   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02272   /* Compute ClockStrobing according AudioMode */
02273   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02274   {
02275     /* Transmit */
02276     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02277   }
02278   else
02279   {
02280     /* Receive */
02281     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02282   }
02283   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
02284   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02285   hsai->SlotInit.FirstBitOffset  = 0;
02286   hsai->SlotInit.SlotNumber      = nbslot;
02287
02288   /* in IS2 the number of slot must be even */
02289   if ((nbslot & 0x1U) != 0U)
02290   {
02291     return HAL_ERROR;
02292   }
02293
02294   if (protocol == SAI_I2S_STANDARD)
02295   {
02296       hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
02297       hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
02298   }
02299   else
02300   {
02301      /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
02302       hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
02303       hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
02304   }
02305
02306   /* Frame definition */
02307   switch (datasize)
02308   {
02309     case SAI_PROTOCOL_DATASIZE_16BIT:
02310       hsai->Init.DataSize = SAI_DATASIZE_16;
02311       hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
02312       hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
02313       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02314       break;
02315     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02316       hsai->Init.DataSize = SAI_DATASIZE_16;
02317       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02318       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02319       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02320       break;
02321     case SAI_PROTOCOL_DATASIZE_24BIT:
02322       hsai->Init.DataSize = SAI_DATASIZE_24;
02323       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02324       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02325       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02326       break;
02327     case SAI_PROTOCOL_DATASIZE_32BIT:
02328       hsai->Init.DataSize = SAI_DATASIZE_32;
02329       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02330       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02331       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02332       break;
02333     default :
02334       status = HAL_ERROR;
02335       break;
02336   }
02337   if (protocol == SAI_I2S_LSBJUSTIFIED)
02338   {
02339     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
02340     {
02341       hsai->SlotInit.FirstBitOffset = 16;
02342     }
02343     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
02344     {
02345       hsai->SlotInit.FirstBitOffset = 8;
02346     }
02347   }
02348   return status;
02349 }
02350
02351 /**
02352   * @brief  Initialize the SAI PCM protocol according to the specified parameters
02353   *         in the SAI_InitTypeDef and create the associated handle.
02354   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02355   *              the configuration information for SAI module.
02356   * @param  protocol one of the supported protocol
02357   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
02358   * @param  nbslot number of slot minimum value is 1 and the max is 16.
02359   * @retval HAL status
02360   */
02361 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02362 {
02363   HAL_StatusTypeDef status = HAL_OK;
02364
02365   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02366   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02367   /* Compute ClockStrobing according AudioMode */
02368   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02369   {
02370     /* Transmit */
02371     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02372   }
02373   else
02374   {
02375     /* Receive */
02376     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02377   }
02378   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
02379   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
02380   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
02381   hsai->SlotInit.FirstBitOffset  = 0;
02382   hsai->SlotInit.SlotNumber      = nbslot;
02383   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02384
02385   if (protocol == SAI_PCM_SHORT)
02386   {
02387       hsai->FrameInit.ActiveFrameLength = 1;
02388   }
02389   else
02390   {
02391     /* SAI_PCM_LONG */
02392       hsai->FrameInit.ActiveFrameLength = 13;
02393   }
02394
02395   switch (datasize)
02396   {
02397     case SAI_PROTOCOL_DATASIZE_16BIT:
02398       hsai->Init.DataSize = SAI_DATASIZE_16;
02399       hsai->FrameInit.FrameLength = 16U * nbslot;
02400       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02401       break;
02402     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02403       hsai->Init.DataSize = SAI_DATASIZE_16;
02404       hsai->FrameInit.FrameLength = 32U * nbslot;
02405       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02406       break;
02407     case SAI_PROTOCOL_DATASIZE_24BIT :
02408       hsai->Init.DataSize = SAI_DATASIZE_24;
02409       hsai->FrameInit.FrameLength = 32U * nbslot;
02410       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02411       break;
02412     case SAI_PROTOCOL_DATASIZE_32BIT:
02413       hsai->Init.DataSize = SAI_DATASIZE_32;
02414       hsai->FrameInit.FrameLength = 32U * nbslot;
02415       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02416       break;
02417     default :
02418       status = HAL_ERROR;
02419       break;
02420   }
02421
02422   return status;
02423 }
02424
02425 /**
02426   * @brief  Fill the fifo.
02427   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02428   *              the configuration information for SAI module.
02429   * @retval None
02430   */
02431 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
02432 {
02433   uint32_t temp;
02434
02435   /* fill the fifo with data before to enabled the SAI */
02436   while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
02437   {
02438     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
02439     {
02440       hsai->Instance->DR = *hsai->pBuffPtr;
02441       hsai->pBuffPtr++;
02442     }
02443     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
02444     {
02445       temp = (uint32_t)(*hsai->pBuffPtr);
02446       hsai->pBuffPtr++;
02447       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02448       hsai->pBuffPtr++;
02449       hsai->Instance->DR = temp;
02450     }
02451     else
02452     {
02453       temp = (uint32_t)(*hsai->pBuffPtr);
02454       hsai->pBuffPtr++;
02455       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02456       hsai->pBuffPtr++;
02457       temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02458       hsai->pBuffPtr++;
02459       temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02460       hsai->pBuffPtr++;
02461       hsai->Instance->DR = temp;
02462     }
02463     hsai->XferCount--;
02464   }
02465 }
02466
02467 /**
02468   * @brief  Return the interrupt flag to set according the SAI setup.
02469   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02470   *              the configuration information for SAI module.
02471   * @param  mode SAI_MODE_DMA or SAI_MODE_IT
02472   * @retval the list of the IT flag to enable
02473   */
02474 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
02475 {
02476   uint32_t tmpIT = SAI_IT_OVRUDR;
02477
02478   if (mode == SAI_MODE_IT)
02479   {
02480     tmpIT |= SAI_IT_FREQ;
02481   }
02482
02483   if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
02484       ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
02485   {
02486     tmpIT |= SAI_IT_CNRDY;
02487   }
02488
02489   if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02490   {
02491     tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
02492   }
02493   else
02494   {
02495     /* hsai has been configured in master mode */
02496     tmpIT |= SAI_IT_WCKCFG;
02497   }
02498   return tmpIT;
02499 }
02500
02501 /**
02502   * @brief  Disable the SAI and wait for the disabling.
02503   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02504   *              the configuration information for SAI module.
02505   * @retval None
02506   */
02507 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
02508 {
02509   register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
02510   HAL_StatusTypeDef status = HAL_OK;
02511
02512   /* Disable the SAI instance */
02513   __HAL_SAI_DISABLE(hsai);
02514
02515   do
02516   {
02517     /* Check for the Timeout */
02518     if (count == 0U)
02519     {
02520       /* Update error code */
02521       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
02522       status = HAL_TIMEOUT;
02523       break;
02524     }
02525     count--;
02526   }
02527   while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
02528
02529   return status;
02530 }
02531
02532 /**
02533   * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
02534   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02535   *              the configuration information for SAI module.
02536   * @retval None
02537   */
02538 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
02539 {
02540   if (hsai->XferCount == 0U)
02541   {
02542     /* Handle the end of the transmission */
02543     /* Disable FREQ and OVRUDR interrupts */
02544     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02545     hsai->State = HAL_SAI_STATE_READY;
02546 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02547     hsai->TxCpltCallback(hsai);
02548 #else
02549     HAL_SAI_TxCpltCallback(hsai);
02550 #endif
02551   }
02552   else
02553   {
02554     /* Write data on DR register */
02555     hsai->Instance->DR = *hsai->pBuffPtr;
02556     hsai->pBuffPtr++;
02557     hsai->XferCount--;
02558   }
02559 }
02560
02561 /**
02562   * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
02563   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02564   *              the configuration information for SAI module.
02565   * @retval None
02566   */
02567 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
02568 {
02569   if (hsai->XferCount == 0U)
02570   {
02571     /* Handle the end of the transmission */
02572     /* Disable FREQ and OVRUDR interrupts */
02573     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02574     hsai->State = HAL_SAI_STATE_READY;
02575 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02576     hsai->TxCpltCallback(hsai);
02577 #else
02578     HAL_SAI_TxCpltCallback(hsai);
02579 #endif
02580   }
02581   else
02582   {
02583     /* Write data on DR register */
02584     uint32_t temp;
02585     temp = (uint32_t)(*hsai->pBuffPtr);
02586     hsai->pBuffPtr++;
02587     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02588     hsai->pBuffPtr++;
02589     hsai->Instance->DR = temp;
02590     hsai->XferCount--;
02591   }
02592 }
02593
02594 /**
02595   * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
02596   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02597   *              the configuration information for SAI module.
02598   * @retval None
02599   */
02600 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
02601 {
02602   if (hsai->XferCount == 0U)
02603   {
02604     /* Handle the end of the transmission */
02605     /* Disable FREQ and OVRUDR interrupts */
02606     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02607     hsai->State = HAL_SAI_STATE_READY;
02608 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02609     hsai->TxCpltCallback(hsai);
02610 #else
02611     HAL_SAI_TxCpltCallback(hsai);
02612 #endif
02613   }
02614   else
02615   {
02616     /* Write data on DR register */
02617     uint32_t temp;
02618     temp = (uint32_t)(*hsai->pBuffPtr);
02619     hsai->pBuffPtr++;
02620     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02621     hsai->pBuffPtr++;
02622     temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02623     hsai->pBuffPtr++;
02624     temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02625     hsai->pBuffPtr++;
02626     hsai->Instance->DR = temp;
02627     hsai->XferCount--;
02628   }
02629 }
02630
02631 /**
02632   * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
02633   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02634   *              the configuration information for SAI module.
02635   * @retval None
02636   */
02637 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
02638 {
02639   /* Receive data */
02640   *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
02641   hsai->pBuffPtr++;
02642   hsai->XferCount--;
02643
02644   /* Check end of the transfer */
02645   if (hsai->XferCount == 0U)
02646   {
02647     /* Disable TXE and OVRUDR interrupts */
02648     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02649
02650     /* Clear the SAI Overrun flag */
02651     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02652
02653     hsai->State = HAL_SAI_STATE_READY;
02654 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02655     hsai->RxCpltCallback(hsai);
02656 #else
02657     HAL_SAI_RxCpltCallback(hsai);
02658 #endif
02659   }
02660 }
02661
02662 /**
02663   * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
02664   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02665   *              the configuration information for SAI module.
02666   * @retval None
02667   */
02668 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
02669 {
02670   uint32_t temp;
02671
02672   /* Receive data */
02673   temp = hsai->Instance->DR;
02674   *hsai->pBuffPtr = (uint8_t)temp;
02675   hsai->pBuffPtr++;
02676   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02677   hsai->pBuffPtr++;
02678   hsai->XferCount--;
02679
02680   /* Check end of the transfer */
02681   if (hsai->XferCount == 0U)
02682   {
02683     /* Disable TXE and OVRUDR interrupts */
02684     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02685
02686     /* Clear the SAI Overrun flag */
02687     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02688
02689     hsai->State = HAL_SAI_STATE_READY;
02690 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02691     hsai->RxCpltCallback(hsai);
02692 #else
02693     HAL_SAI_RxCpltCallback(hsai);
02694 #endif
02695   }
02696 }
02697
02698 /**
02699   * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
02700   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02701   *              the configuration information for SAI module.
02702   * @retval None
02703   */
02704 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
02705 {
02706   uint32_t temp;
02707
02708   /* Receive data */
02709   temp = hsai->Instance->DR;
02710   *hsai->pBuffPtr = (uint8_t)temp;
02711   hsai->pBuffPtr++;
02712   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02713   hsai->pBuffPtr++;
02714   *hsai->pBuffPtr = (uint8_t)(temp >> 16);
02715   hsai->pBuffPtr++;
02716   *hsai->pBuffPtr = (uint8_t)(temp >> 24);
02717   hsai->pBuffPtr++;
02718   hsai->XferCount--;
02719
02720   /* Check end of the transfer */
02721   if (hsai->XferCount == 0U)
02722   {
02723     /* Disable TXE and OVRUDR interrupts */
02724     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02725
02726     /* Clear the SAI Overrun flag */
02727     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02728
02729     hsai->State = HAL_SAI_STATE_READY;
02730 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02731     hsai->RxCpltCallback(hsai);
02732 #else
02733     HAL_SAI_RxCpltCallback(hsai);
02734 #endif
02735   }
02736 }
02737
02738 /**
02739   * @brief  DMA SAI transmit process complete callback.
02740   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02741   *              the configuration information for the specified DMA module.
02742   * @retval None
02743   */
02744 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
02745 {
02746   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02747
02748   if (hdma->Init.Mode != DMA_CIRCULAR)
02749   {
02750     hsai->XferCount = 0;
02751
02752     /* Disable SAI Tx DMA Request */
02753     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02754
02755     /* Stop the interrupts error handling */
02756     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02757
02758     hsai->State = HAL_SAI_STATE_READY;
02759   }
02760 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02761   hsai->TxCpltCallback(hsai);
02762 #else
02763   HAL_SAI_TxCpltCallback(hsai);
02764 #endif
02765 }
02766
02767 /**
02768   * @brief  DMA SAI transmit process half complete callback.
02769   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02770   *              the configuration information for the specified DMA module.
02771   * @retval None
02772   */
02773 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02774 {
02775   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02776
02777 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02778   hsai->TxHalfCpltCallback(hsai);
02779 #else
02780   HAL_SAI_TxHalfCpltCallback(hsai);
02781 #endif
02782 }
02783
02784 /**
02785   * @brief  DMA SAI receive process complete callback.
02786   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02787   *              the configuration information for the specified DMA module.
02788   * @retval None
02789   */
02790 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
02791 {
02792   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02793
02794   if (hdma->Init.Mode != DMA_CIRCULAR)
02795   {
02796     /* Disable Rx DMA Request */
02797     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02798     hsai->XferCount = 0;
02799
02800     /* Stop the interrupts error handling */
02801     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02802
02803     hsai->State = HAL_SAI_STATE_READY;
02804   }
02805 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02806   hsai->RxCpltCallback(hsai);
02807 #else
02808   HAL_SAI_RxCpltCallback(hsai);
02809 #endif
02810 }
02811
02812 /**
02813   * @brief  DMA SAI receive process half complete callback
02814   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02815   *              the configuration information for the specified DMA module.
02816   * @retval None
02817   */
02818 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02819 {
02820   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02821
02822 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02823   hsai->RxHalfCpltCallback(hsai);
02824 #else
02825   HAL_SAI_RxHalfCpltCallback(hsai);
02826 #endif
02827 }
02828
02829 /**
02830   * @brief  DMA SAI communication error callback.
02831   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02832   *              the configuration information for the specified DMA module.
02833   * @retval None
02834   */
02835 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
02836 {
02837   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02838
02839   /* Ignore DMA FIFO error */
02840   if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
02841   {
02842     /* Set SAI error code */
02843     hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02844
02845     /* Disable the SAI DMA request */
02846     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02847
02848     /* Disable SAI peripheral */
02849     /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02850     (void) SAI_Disable(hsai);
02851
02852     /* Set the SAI state ready to be able to start again the process */
02853     hsai->State = HAL_SAI_STATE_READY;
02854
02855     /* Initialize XferCount */
02856     hsai->XferCount = 0U;
02857
02858     /* SAI error Callback */
02859 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02860     hsai->ErrorCallback(hsai);
02861 #else
02862     HAL_SAI_ErrorCallback(hsai);
02863 #endif
02864   }
02865 }
02866
02867 /**
02868   * @brief  DMA SAI Abort callback.
02869   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02870   *              the configuration information for the specified DMA module.
02871   * @retval None
02872   */
02873 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
02874 {
02875   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02876
02877   /* Disable DMA request */
02878   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02879
02880   /* Disable all interrupts and clear all flags */
02881   hsai->Instance->IMR = 0U;
02882   hsai->Instance->CLRFR = 0xFFFFFFFFU;
02883
02884   if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
02885   {
02886     /* Disable SAI peripheral */
02887     /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02888     (void) SAI_Disable(hsai);
02889
02890     /* Flush the fifo */
02891     SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
02892   }
02893   /* Set the SAI state to ready to be able to start again the process */
02894   hsai->State = HAL_SAI_STATE_READY;
02895
02896   /* Initialize XferCount */
02897   hsai->XferCount = 0U;
02898
02899   /* SAI error Callback */
02900 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02901   hsai->ErrorCallback(hsai);
02902 #else
02903   HAL_SAI_ErrorCallback(hsai);
02904 #endif
02905 }
02906
02907 /**
02908   * @}
02909   */
02910
02911 #endif /* HAL_SAI_MODULE_ENABLED */
02912 /**
02913   * @}
02914   */
02915
02916 /**
02917   * @}
02918   */
02919
02920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai.h Source File

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stm32h7xx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SAI_H
00022 #define STM32H7xx_HAL_SAI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SAI
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SAI_Exported_Types SAI Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  HAL State structures definition
00046   */
00047 typedef enum
00048 {
00049   HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
00050   HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
00051   HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
00052   HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
00053   HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
00054 } HAL_SAI_StateTypeDef;
00055
00056 /**
00057   * @brief  SAI Callback prototype
00058   */
00059 typedef void (*SAIcallback)(void);
00060
00061 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
00062   * @brief  SAI PDM Init structure definition
00063   * @{
00064   */
00065 typedef struct
00066 {
00067   FunctionalState  Activation;  /*!< Enable/disable PDM interface */
00068   uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
00069                                      This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00070   uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
00071                                      This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
00072 } SAI_PdmInitTypeDef;
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
00078   * @brief  SAI Init Structure definition
00079   * @{
00080   */
00081 typedef struct
00082 {
00083   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00084                                      This parameter can be a value of @ref SAI_Block_Mode */
00085
00086   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00087                                      This parameter can be a value of @ref SAI_Block_Synchronization */
00088
00089   uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
00090                                      for BlockA and BlockB
00091                                      This parameter can be a value of @ref SAI_Block_SyncExt
00092                                      @note If both audio blocks of same SAI are used, this parameter has
00093                                            to be set to the same value for each audio block */
00094
00095   uint32_t MckOutput;           /*!< Specifies whether master clock output will be generated or not.
00096                                      This parameter can be a value of @ref SAI_Block_MckOutput
00097                                      @note This feature is only available on STM32H7xx Rev.B and above */
00098
00099   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00100                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00101                                      @note This value has to be set before enabling the audio block
00102                                            but after the audio block configuration. */
00103
00104   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00105                                      This parameter can be a value of @ref SAI_Block_NoDivider
00106                                      @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00107                                            should be aligned to a number equal to a power of 2, from 8 to 256.
00108                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can
00109                                            take any of the values from 8 to 256.
00110                                      @note The NODIV bit is the same as NOMCK bit in STM32H7xx rev.Y */
00111
00112   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00113                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
00114
00115   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00116                                      This parameter can be a value of @ref SAI_Audio_Frequency */
00117
00118   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
00119                                      AudioFrequency the user choice
00120                                      This parameter must be a number between Min_Data = 0 and Max_Data = 63. */
00121
00122   uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
00123                                      This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
00124
00125   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00126                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
00127
00128   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00129                                      This parameter can be a value of @ref SAI_Block_Companding_Mode */
00130
00131   uint32_t TriState;            /*!< Specifies the companding mode type.
00132                                      This parameter can be a value of @ref SAI_TRIState_Management */
00133
00134   SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */
00135
00136   /* This part of the structure is automatically filled if your are using the high level initialisation
00137      function HAL_SAI_InitProtocol */
00138
00139   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00140                                  This parameter can be a value of @ref SAI_Block_Protocol */
00141
00142   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00143                                  This parameter can be a value of @ref SAI_Block_Data_Size */
00144
00145   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00146                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
00147
00148   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00149                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing */
00150 } SAI_InitTypeDef;
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
00156   * @brief  SAI Frame Init structure definition
00157   * @{
00158   */
00159 typedef struct
00160 {
00161
00162   uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00163                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00164                                     @note If master clock MCLK_x pin is declared as an output, the frame length
00165                                           should be aligned to a number equal to power of 2 in order to keep
00166                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */
00167
00168   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00169                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00170                                     of the active level of FS signal in audio frame.
00171                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
00172
00173   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00174                                     This parameter can be a value of @ref SAI_Block_FS_Definition */
00175
00176   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00177                                     This parameter can be a value of @ref SAI_Block_FS_Polarity */
00178
00179   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00180                                     This parameter can be a value of @ref SAI_Block_FS_Offset */
00181
00182 } SAI_FrameInitTypeDef;
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
00188   * @brief   SAI Block Slot Init Structure definition
00189   * @{
00190   */
00191 typedef struct
00192 {
00193   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00194                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00195
00196   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00197                                  This parameter can be a value of @ref SAI_Block_Slot_Size */
00198
00199   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00200                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00201
00202   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00203                                  This parameter can be a value of @ref SAI_Block_Slot_Active */
00204 } SAI_SlotInitTypeDef;
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
00210   * @brief  SAI handle Structure definition
00211   * @{
00212   */
00213 typedef struct __SAI_HandleTypeDef
00214 {
00215   SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
00216
00217   SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
00218
00219   SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
00220
00221   SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
00222
00223   uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
00224
00225   uint16_t                  XferSize;     /*!< SAI transfer size */
00226
00227   uint16_t                  XferCount;    /*!< SAI transfer counter */
00228
00229   DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
00230
00231   DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
00232
00233   SAIcallback               mutecallback; /*!< SAI mute callback */
00234
00235   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
00236
00237   HAL_LockTypeDef           Lock;         /*!< SAI locking object */
00238
00239   __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
00240
00241   __IO uint32_t             ErrorCode;    /*!< SAI Error code */
00242
00243 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00244   void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */
00245   void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */
00246   void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */
00247   void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */
00248   void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */
00249   void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */
00250   void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */
00251 #endif
00252 } SAI_HandleTypeDef;
00253 /**
00254   * @}
00255   */
00256
00257 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00258 /**
00259   * @brief  SAI callback ID enumeration definition
00260   */
00261 typedef enum
00262 {
00263   HAL_SAI_RX_COMPLETE_CB_ID       = 0x00U, /*!< SAI receive complete callback ID */
00264   HAL_SAI_RX_HALFCOMPLETE_CB_ID   = 0x01U, /*!< SAI receive half complete callback ID */
00265   HAL_SAI_TX_COMPLETE_CB_ID       = 0x02U, /*!< SAI transmit complete callback ID */
00266   HAL_SAI_TX_HALFCOMPLETE_CB_ID   = 0x03U, /*!< SAI transmit half complete callback ID */
00267   HAL_SAI_ERROR_CB_ID             = 0x04U, /*!< SAI error callback ID */
00268   HAL_SAI_MSPINIT_CB_ID           = 0x05U, /*!< SAI MSP init callback ID */
00269   HAL_SAI_MSPDEINIT_CB_ID         = 0x06U  /*!< SAI MSP de-init callback ID */
00270 } HAL_SAI_CallbackIDTypeDef;
00271
00272 /**
00273   * @brief  SAI callback pointer definition
00274   */
00275 typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
00276 #endif
00277
00278 /**
00279   * @}
00280   */
00281
00282 /* Exported constants --------------------------------------------------------*/
00283 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00284   * @{
00285   */
00286
00287 /** @defgroup SAI_Error_Code SAI Error Code
00288   * @{
00289   */
00290 #define HAL_SAI_ERROR_NONE          0x00000000U  /*!< No error */
00291 #define HAL_SAI_ERROR_OVR           0x00000001U  /*!< Overrun Error */
00292 #define HAL_SAI_ERROR_UDR           0x00000002U  /*!< Underrun error */
00293 #define HAL_SAI_ERROR_AFSDET        0x00000004U  /*!< Anticipated Frame synchronisation detection */
00294 #define HAL_SAI_ERROR_LFSDET        0x00000008U  /*!< Late Frame synchronisation detection */
00295 #define HAL_SAI_ERROR_CNREADY       0x00000010U  /*!< codec not ready */
00296 #define HAL_SAI_ERROR_WCKCFG        0x00000020U  /*!< Wrong clock configuration */
00297 #define HAL_SAI_ERROR_TIMEOUT       0x00000040U  /*!< Timeout error */
00298 #define HAL_SAI_ERROR_DMA           0x00000080U  /*!< DMA error */
00299 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00300 #define HAL_SAI_ERROR_INVALID_CALLBACK   0x00000100U  /*!< Invalid callback error */
00301 #endif
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00307   * @{
00308   */
00309 #define SAI_SYNCEXT_DISABLE           0U
00310 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE  1U
00311 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE  2U
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
00317   * @{
00318   */
00319 #define SAI_MCK_OUTPUT_DISABLE      0x00000000U
00320 #define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup SAI_Protocol SAI Supported protocol
00326   * @{
00327   */
00328 #define SAI_I2S_STANDARD         0U
00329 #define SAI_I2S_MSBJUSTIFIED     1U
00330 #define SAI_I2S_LSBJUSTIFIED     2U
00331 #define SAI_PCM_LONG             3U
00332 #define SAI_PCM_SHORT            4U
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00338   * @{
00339   */
00340 #define SAI_PROTOCOL_DATASIZE_16BIT         0U
00341 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
00342 #define SAI_PROTOCOL_DATASIZE_24BIT         2U
00343 #define SAI_PROTOCOL_DATASIZE_32BIT         3U
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00349   * @{
00350   */
00351 #define SAI_AUDIO_FREQUENCY_192K      192000U
00352 #define SAI_AUDIO_FREQUENCY_96K        96000U
00353 #define SAI_AUDIO_FREQUENCY_48K        48000U
00354 #define SAI_AUDIO_FREQUENCY_44K        44100U
00355 #define SAI_AUDIO_FREQUENCY_32K        32000U
00356 #define SAI_AUDIO_FREQUENCY_22K        22050U
00357 #define SAI_AUDIO_FREQUENCY_16K        16000U
00358 #define SAI_AUDIO_FREQUENCY_11K        11025U
00359 #define SAI_AUDIO_FREQUENCY_8K          8000U
00360 #define SAI_AUDIO_FREQUENCY_MCKDIV         0U
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
00366   * @{
00367   */
00368 #define SAI_MCK_OVERSAMPLING_DISABLE  0x00000000U
00369 #define SAI_MCK_OVERSAMPLING_ENABLE   SAI_xCR1_OSR
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
00375   * @{
00376   */
00377 #define SAI_PDM_CLOCK1_ENABLE         SAI_PDMCR_CKEN1
00378 #define SAI_PDM_CLOCK2_ENABLE         SAI_PDMCR_CKEN2
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup SAI_Block_Mode SAI Block Mode
00384   * @{
00385   */
00386 #define SAI_MODEMASTER_TX             0x00000000U
00387 #define SAI_MODEMASTER_RX             SAI_xCR1_MODE_0
00388 #define SAI_MODESLAVE_TX              SAI_xCR1_MODE_1
00389 #define SAI_MODESLAVE_RX              (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
00390
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00396   * @{
00397   */
00398 #define SAI_FREE_PROTOCOL             0x00000000U
00399 #define SAI_SPDIF_PROTOCOL            SAI_xCR1_PRTCFG_0
00400 #define SAI_AC97_PROTOCOL             SAI_xCR1_PRTCFG_1
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00406   * @{
00407   */
00408 #define SAI_DATASIZE_8                SAI_xCR1_DS_1
00409 #define SAI_DATASIZE_10               (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00410 #define SAI_DATASIZE_16               SAI_xCR1_DS_2
00411 #define SAI_DATASIZE_20               (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
00412 #define SAI_DATASIZE_24               (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
00413 #define SAI_DATASIZE_32               (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00419   * @{
00420   */
00421 #define SAI_FIRSTBIT_MSB              0x00000000U
00422 #define SAI_FIRSTBIT_LSB              SAI_xCR1_LSBFIRST
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00428   * @{
00429   */
00430 #define SAI_CLOCKSTROBING_FALLINGEDGE  0U
00431 #define SAI_CLOCKSTROBING_RISINGEDGE   1U
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00437   * @{
00438   */
00439 #define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
00440 #define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
00441 #define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */
00442 #if defined(SAI2)
00443 #define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */
00444 #endif /* SAI2 */
00445 #if defined(SAI3)
00446 #define SAI_SYNCHRONOUS_EXT_SAI3          4U /*!< Synchronous with other SAI, SAI3 */
00447 #endif /* SAI3 */
00448 #if defined(SAI4)
00449 #define SAI_SYNCHRONOUS_EXT_SAI4          5U /*!< Synchronous with other SAI, SAI4 */
00450 #endif /* SAI4 */
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00456   * @{
00457   */
00458 #define SAI_OUTPUTDRIVE_DISABLE     0x00000000U
00459 #define SAI_OUTPUTDRIVE_ENABLE      SAI_xCR1_OUTDRIV
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00465   * @{
00466   */
00467 #define SAI_MASTERDIVIDER_ENABLE    0x00000000U
00468 #define SAI_MASTERDIVIDER_DISABLE   SAI_xCR1_NODIV
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00474   * @{
00475   */
00476 #define SAI_FS_STARTFRAME               0x00000000U
00477 #define SAI_FS_CHANNEL_IDENTIFICATION   SAI_xFRCR_FSDEF
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00483   * @{
00484   */
00485 #define SAI_FS_ACTIVE_LOW           0x00000000U
00486 #define SAI_FS_ACTIVE_HIGH          SAI_xFRCR_FSPOL
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00492   * @{
00493   */
00494 #define SAI_FS_FIRSTBIT             0x00000000U
00495 #define SAI_FS_BEFOREFIRSTBIT       SAI_xFRCR_FSOFF
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00501   * @{
00502   */
00503 #define SAI_SLOTSIZE_DATASIZE       0x00000000U
00504 #define SAI_SLOTSIZE_16B            SAI_xSLOTR_SLOTSZ_0
00505 #define SAI_SLOTSIZE_32B            SAI_xSLOTR_SLOTSZ_1
00506 /**
00507   * @}
00508   */
00509
00510 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00511   * @{
00512   */
00513 #define SAI_SLOT_NOTACTIVE          0x00000000U
00514 #define SAI_SLOTACTIVE_0            0x00000001U
00515 #define SAI_SLOTACTIVE_1            0x00000002U
00516 #define SAI_SLOTACTIVE_2            0x00000004U
00517 #define SAI_SLOTACTIVE_3            0x00000008U
00518 #define SAI_SLOTACTIVE_4            0x00000010U
00519 #define SAI_SLOTACTIVE_5            0x00000020U
00520 #define SAI_SLOTACTIVE_6            0x00000040U
00521 #define SAI_SLOTACTIVE_7            0x00000080U
00522 #define SAI_SLOTACTIVE_8            0x00000100U
00523 #define SAI_SLOTACTIVE_9            0x00000200U
00524 #define SAI_SLOTACTIVE_10           0x00000400U
00525 #define SAI_SLOTACTIVE_11           0x00000800U
00526 #define SAI_SLOTACTIVE_12           0x00001000U
00527 #define SAI_SLOTACTIVE_13           0x00002000U
00528 #define SAI_SLOTACTIVE_14           0x00004000U
00529 #define SAI_SLOTACTIVE_15           0x00008000U
00530 #define SAI_SLOTACTIVE_ALL          0x0000FFFFU
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00536   * @{
00537   */
00538 #define SAI_STEREOMODE              0x00000000U
00539 #define SAI_MONOMODE                SAI_xCR1_MONO
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00545   * @{
00546   */
00547 #define SAI_OUTPUT_NOTRELEASED      0x00000000U
00548 #define SAI_OUTPUT_RELEASED         SAI_xCR2_TRIS
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00554   * @{
00555   */
00556 #define SAI_FIFOTHRESHOLD_EMPTY     0x00000000U
00557 #define SAI_FIFOTHRESHOLD_1QF       SAI_xCR2_FTH_0
00558 #define SAI_FIFOTHRESHOLD_HF        SAI_xCR2_FTH_1
00559 #define SAI_FIFOTHRESHOLD_3QF       (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
00560 #define SAI_FIFOTHRESHOLD_FULL      SAI_xCR2_FTH_2
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00566   * @{
00567   */
00568 #define SAI_NOCOMPANDING            0x00000000U
00569 #define SAI_ULAW_1CPL_COMPANDING    SAI_xCR2_COMP_1
00570 #define SAI_ALAW_1CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
00571 #define SAI_ULAW_2CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
00572 #define SAI_ALAW_2CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00578   * @{
00579   */
00580 #define SAI_ZERO_VALUE              0x00000000U
00581 #define SAI_LAST_SENT_VALUE         SAI_xCR2_MUTEVAL
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00587   * @{
00588   */
00589 #define SAI_IT_OVRUDR               SAI_xIMR_OVRUDRIE
00590 #define SAI_IT_MUTEDET              SAI_xIMR_MUTEDETIE
00591 #define SAI_IT_WCKCFG               SAI_xIMR_WCKCFGIE
00592 #define SAI_IT_FREQ                 SAI_xIMR_FREQIE
00593 #define SAI_IT_CNRDY                SAI_xIMR_CNRDYIE
00594 #define SAI_IT_AFSDET               SAI_xIMR_AFSDETIE
00595 #define SAI_IT_LFSDET               SAI_xIMR_LFSDETIE
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00601   * @{
00602   */
00603 #define SAI_FLAG_OVRUDR             SAI_xSR_OVRUDR
00604 #define SAI_FLAG_MUTEDET            SAI_xSR_MUTEDET
00605 #define SAI_FLAG_WCKCFG             SAI_xSR_WCKCFG
00606 #define SAI_FLAG_FREQ               SAI_xSR_FREQ
00607 #define SAI_FLAG_CNRDY              SAI_xSR_CNRDY
00608 #define SAI_FLAG_AFSDET             SAI_xSR_AFSDET
00609 #define SAI_FLAG_LFSDET             SAI_xSR_LFSDET
00610 /**
00611   * @}
00612   */
00613
00614 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00615   * @{
00616   */
00617 #define SAI_FIFOSTATUS_EMPTY              0x00000000U
00618 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
00619 #define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
00620 #define SAI_FIFOSTATUS_HALFFULL           0x00030000U
00621 #define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
00622 #define SAI_FIFOSTATUS_FULL               0x00050000U
00623 /**
00624   * @}
00625   */
00626
00627 /**
00628   * @}
00629   */
00630
00631 /* Exported macro ------------------------------------------------------------*/
00632 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00633   * @brief macros to handle interrupts and specific configurations
00634   * @{
00635   */
00636
00637 /** @brief Reset SAI handle state.
00638   * @param  __HANDLE__ specifies the SAI Handle.
00639   * @retval None
00640   */
00641 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00642 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00643                                                      (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
00644                                                      (__HANDLE__)->MspInitCallback = NULL;      \
00645                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
00646                                                    } while(0U)
00647 #else
00648 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00649 #endif
00650
00651 /** @brief  Enable the specified SAI interrupts.
00652   * @param  __HANDLE__ specifies the SAI Handle.
00653   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00654   *         This parameter can be one of the following values:
00655   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00656   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00657   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00658   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00659   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00660   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00661   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00662   * @retval None
00663   */
00664 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00665
00666 /** @brief  Disable the specified SAI interrupts.
00667   * @param  __HANDLE__ specifies the SAI Handle.
00668   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00669   *         This parameter can be one of the following values:
00670   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00671   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00672   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00673   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00674   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00675   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00676   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00677   * @retval None
00678   */
00679 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00680
00681 /** @brief  Check whether the specified SAI interrupt source is enabled or not.
00682   * @param  __HANDLE__ specifies the SAI Handle.
00683   * @param  __INTERRUPT__ specifies the SAI interrupt source to check.
00684   *         This parameter can be one of the following values:
00685   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00686   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00687   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00688   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00689   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00690   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00691   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00692   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00693   */
00694 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00695
00696 /** @brief  Check whether the specified SAI flag is set or not.
00697   * @param  __HANDLE__ specifies the SAI Handle.
00698   * @param  __FLAG__ specifies the flag to check.
00699   *         This parameter can be one of the following values:
00700   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00701   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00702   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00703   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00704   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00705   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00706   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00707   * @retval The new state of __FLAG__ (TRUE or FALSE).
00708   */
00709 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00710
00711 /** @brief  Clear the specified SAI pending flag.
00712   * @param  __HANDLE__ specifies the SAI Handle.
00713   * @param  __FLAG__ specifies the flag to check.
00714   *          This parameter can be any combination of the following values:
00715   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00716   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00717   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00718   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00719   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00720   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00721   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00722   *
00723   * @retval None
00724   */
00725 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00726
00727 /** @brief  Enable SAI.
00728   * @param  __HANDLE__ specifies the SAI Handle.
00729   * @retval None
00730   */
00731 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00732
00733 /** @brief  Disable SAI.
00734   * @param  __HANDLE__ specifies the SAI Handle.
00735   * @retval None
00736   */
00737 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00738
00739 /**
00740   * @}
00741   */
00742
00743 /* Include SAI HAL Extension module */
00744 #include "stm32h7xx_hal_sai_ex.h"
00745
00746 /* Exported functions --------------------------------------------------------*/
00747 /** @addtogroup SAI_Exported_Functions
00748   * @{
00749   */
00750
00751 /* Initialization/de-initialization functions  ********************************/
00752 /** @addtogroup SAI_Exported_Functions_Group1
00753   * @{
00754   */
00755 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00756 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00757 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
00758 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00759 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00760
00761 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00762 /* SAI callbacks register/unregister functions ********************************/
00763 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00764                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00765                                            pSAI_CallbackTypeDef      pCallback);
00766 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00767                                              HAL_SAI_CallbackIDTypeDef CallbackID);
00768 #endif
00769 /**
00770   * @}
00771   */
00772
00773 /* I/O operation functions  ***************************************************/
00774 /** @addtogroup SAI_Exported_Functions_Group2
00775   * @{
00776   */
00777 /* Blocking mode: Polling */
00778 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00779 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00780
00781 /* Non-Blocking mode: Interrupt */
00782 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00783 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00784
00785 /* Non-Blocking mode: DMA */
00786 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00787 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00788 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00789 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00790 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00791
00792 /* Abort function */
00793 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00794
00795 /* Mute management */
00796 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00797 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00798 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00799 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00800
00801 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00802 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00803 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00804 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00805 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00806 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00807 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00808 /**
00809   * @}
00810   */
00811
00812 /** @addtogroup SAI_Exported_Functions_Group3
00813   * @{
00814   */
00815 /* Peripheral State functions  ************************************************/
00816 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00817 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00818 /**
00819   * @}
00820   */
00821
00822 /**
00823   * @}
00824   */
00825
00826 /* Private macros ------------------------------------------------------------*/
00827 /** @addtogroup SAI_Private_Macros
00828   * @{
00829   */
00830 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
00831                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
00832                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00833
00834 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00835                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00836                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00837                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00838                                                ((PROTOCOL) == SAI_PCM_SHORT))
00839
00840 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00841                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00842                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00843                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00844
00845 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00846                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00847                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00848                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00849                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00850
00851 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
00852                                               ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
00853
00854 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))
00855
00856 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
00857                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
00858
00859 #define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
00860                                   ((MODE) == SAI_MODEMASTER_RX) || \
00861                                   ((MODE) == SAI_MODESLAVE_TX)  || \
00862                                   ((MODE) == SAI_MODESLAVE_RX))
00863
00864 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00865                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00866                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00867
00868 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00869                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00870                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00871                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00872                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00873                                          ((DATASIZE) == SAI_DATASIZE_32))
00874
00875 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00876                                      ((BIT) == SAI_FIRSTBIT_LSB))
00877
00878 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00879                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00880 #if defined(SAI2) && defined(SAI3) && defined(SAI4)
00881 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
00882                                        ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
00883                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
00884                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)  || \
00885                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3)  || \
00886                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
00887 #elif defined(SAI2)
00888 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
00889                                        ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
00890                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
00891                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00892 #else
00893 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
00894                                        ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
00895                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
00896                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
00897 #endif
00898
00899 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
00900                                         ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
00901
00902 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00903                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00904
00905 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00906                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00907
00908 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
00909
00910 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00911                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00912
00913 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00914                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00915                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00916                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00917                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00918
00919 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00920                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00921                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00922                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00923                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00924
00925 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00926                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00927
00928 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00929                                        ((MODE) == SAI_STEREOMODE))
00930
00931 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00932
00933 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
00934
00935 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00936                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00937                                       ((SIZE) == SAI_SLOTSIZE_32B))
00938
00939 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
00940
00941 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00942                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00943
00944 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00945                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00946
00947 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00948                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00949
00950 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
00951
00952 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
00953
00954 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
00955
00956 /**
00957   * @}
00958   */
00959
00960 /* Private functions ---------------------------------------------------------*/
00961 /** @defgroup SAI_Private_Functions SAI Private Functions
00962   * @{
00963   */
00964
00965 /**
00966   * @}
00967   */
00968
00969 /**
00970   * @}
00971   */
00972
00973 /**
00974   * @}
00975   */
00976
00977 #ifdef __cplusplus
00978 }
00979 #endif
00980
00981 #endif /* STM32H7xx_HAL_SAI_H */
00982
00983 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai_ex.c Source File

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stm32h7xx_hal_sai_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SAI Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionality of the SAI Peripheral Controller:
00008   *           + Modify PDM microphone delays.
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32h7xx_hal.h"
00026
00027 /** @addtogroup STM32H7xx_HAL_Driver
00028   * @{
00029   */
00030 #ifdef HAL_SAI_MODULE_ENABLED
00031
00032 /** @defgroup SAIEx SAIEx
00033   * @brief SAI Extended HAL module driver
00034   * @{
00035   */
00036
00037 /* Private types -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private constants ---------------------------------------------------------*/
00040 #define SAI_PDM_DELAY_MASK          0x77U
00041 #define SAI_PDM_DELAY_OFFSET        8U
00042 #define SAI_PDM_RIGHT_DELAY_OFFSET  4U
00043
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Private functions ---------------------------------------------------------*/
00046 /* Exported functions --------------------------------------------------------*/
00047 /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00048   * @{
00049   */
00050
00051 /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00052   * @brief    SAIEx control functions
00053   *
00054 @verbatim
00055  ===============================================================================
00056                  ##### Extended features functions #####
00057  ===============================================================================
00058     [..]  This section provides functions allowing to:
00059       (+) Modify PDM microphone delays
00060
00061 @endverbatim
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  Configure PDM microphone delays.
00067   * @param  hsai SAI handle.
00068   * @param  pdmMicDelay Microphone delays configuration.
00069   * @retval HAL status
00070   */
00071 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
00072 {
00073   HAL_StatusTypeDef status = HAL_OK;
00074   uint32_t offset;
00075   SAI_TypeDef *SaiBaseAddress;
00076
00077   /* Get the SAI base address according to the SAI handle */
00078 #if defined(SAI4)
00079   SaiBaseAddress = ((hsai->Instance == SAI1_Block_A) ? SAI1 : \
00080                     (hsai->Instance == SAI4_Block_A) ? SAI4 : \
00081                      NULL);
00082 #else
00083   SaiBaseAddress = ((hsai->Instance == SAI1_Block_A) ? SAI1 : NULL);
00084 #endif /* SAI4 */
00085
00086   /* Check that SAI sub-block is SAI sub-block A */
00087   if (SaiBaseAddress == NULL)
00088   {
00089     status = HAL_ERROR;
00090   }
00091   else
00092   {
00093     /* Check microphone delay parameters */
00094     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
00095     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
00096     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
00097
00098     /* Compute offset on PDMDLY register according mic pair number */
00099     offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
00100
00101     /* Check SAI state and offset */
00102     if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
00103     {
00104       /* Reset current delays for specified microphone */
00105       SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
00106
00107       /* Apply new microphone delays */
00108       SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
00109     }
00110     else
00111     {
00112       status = HAL_ERROR;
00113     }
00114   }
00115   return status;
00116 }
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129
00130 #endif /* HAL_SAI_MODULE_ENABLED */
00131 /**
00132   * @}
00133   */
00134
00135 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sai_ex.h Source File

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stm32h7xx_hal_sai_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SAI_EX_H
00022 #define STM32H7xx_HAL_SAI_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SAIEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  PDM microphone delay structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.
00050                              This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00051
00052   uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.
00053                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00054
00055   uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.
00056                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00057 } SAIEx_PdmMicDelayParamTypeDef;
00058
00059 /**
00060   * @}
00061   */
00062
00063 /* Exported constants --------------------------------------------------------*/
00064 /* Exported macros -----------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00071   * @{
00072   */
00073 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Private macros ------------------------------------------------------------*/
00083 /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
00084   * @{
00085   */
00086 #define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 #ifdef __cplusplus
00100 }
00101 #endif
00102
00103 #endif /* STM32H7xx_HAL_SAI_EX_H */
00104
00105 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd.c Source File

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stm32h7xx_hal_sd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @brief   SD card HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Secure Digital (SD) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     This driver implements a high level communication layer for read and write from/to
00019     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
00020     the user in HAL_SD_MspInit() function (MSP layer).
00021     Basically, the MSP layer configuration should be the same as we provide in the
00022     examples.
00023     You can easily tailor this configuration according to hardware resources.
00024
00025   [..]
00026     This driver is a generic layered driver for SDMMC memories which uses the HAL
00027     SDMMC driver functions to interface with SD and uSD cards devices.
00028     It is used as follows:
00029
00030     (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
00031         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
00032         (##) SDMMC pins configuration for SD card
00033             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00034             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00035                   and according to your pin assignment;
00036         (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
00037              and HAL_SD_WriteBlocks_IT() APIs).
00038             (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
00039             (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00040             (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
00041                   and __HAL_SD_DISABLE_IT() inside the communication process.
00042             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
00043                   and __HAL_SD_CLEAR_IT()
00044         (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
00045
00046     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00047
00048
00049   *** SD Card Initialization and configuration ***
00050   ================================================
00051   [..]
00052     To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
00053     SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
00054     This function provide the following operations:
00055
00056     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
00057         type (Standard Capacity or High Capacity). You can change or adapt this
00058         frequency by adjusting the "ClockDiv" field.
00059         The SD Card frequency (SDMMC_CK) is computed as follows:
00060
00061            SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
00062
00063         In initialization mode and according to the SD Card standard,
00064         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00065
00066         This phase of initialization is done through SDMMC_Init() and
00067         SDMMC_PowerState_ON() SDMMC low level APIs.
00068
00069     (#) Initialize the SD card. The API used is HAL_SD_InitCard().
00070         This phase allows the card initialization and identification
00071         and check the SD Card type (Standard Capacity or High Capacity)
00072         The initialization flow is compatible with SD standard.
00073
00074         This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
00075         of plug-off plug-in.
00076
00077     (#) Configure the SD Card Data transfer frequency. You can change or adapt this
00078         frequency by adjusting the "ClockDiv" field.
00079         In transfer mode and according to the SD Card standard, make sure that the
00080         SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
00081
00082     (#) Select the corresponding SD Card according to the address read with the step 2.
00083
00084     (#) Configure the SD Card in wide bus mode: 4-bits data.
00085
00086   *** SD Card Read operation ***
00087   ==============================
00088   [..]
00089     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00090         This function support only 512-bytes block length (the block size should be
00091         chosen as 512 bytes).
00092         You can choose either one block read operation or multiple block read operation
00093         by adjusting the "NumberOfBlocks" parameter.
00094         After this, you have to ensure that the transfer is done correctly. The check is done
00095         through HAL_SD_GetCardState() function for SD card state.
00096
00097     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00098         This function support only 512-bytes block length (the block size should be
00099         chosen as 512 bytes).
00100         You can choose either one block read operation or multiple block read operation
00101         by adjusting the "NumberOfBlocks" parameter.
00102         After this, you have to ensure that the transfer is done correctly. The check is done
00103         through HAL_SD_GetCardState() function for SD card state.
00104         You could also check the DMA transfer process through the SD Rx interrupt event.
00105
00106     (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
00107         This function support only 512-bytes block length (the block size should be
00108         chosen as 512 bytes).
00109         You can choose either one block read operation or multiple block read operation
00110         by adjusting the "NumberOfBlocks" parameter.
00111         After this, you have to ensure that the transfer is done correctly. The check is done
00112         through HAL_SD_GetCardState() function for SD card state.
00113         You could also check the IT transfer process through the SD Rx interrupt event.
00114
00115   *** SD Card Write operation ***
00116   ===============================
00117   [..]
00118     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00119         This function support only 512-bytes block length (the block size should be
00120         chosen as 512 bytes).
00121         You can choose either one block read operation or multiple block read operation
00122         by adjusting the "NumberOfBlocks" parameter.
00123         After this, you have to ensure that the transfer is done correctly. The check is done
00124         through HAL_SD_GetCardState() function for SD card state.
00125
00126     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00127         This function support only 512-bytes block length (the block size should be
00128         chosen as 512 bytes).
00129         You can choose either one block read operation or multiple block read operation
00130         by adjusting the "NumberOfBlocks" parameter.
00131         After this, you have to ensure that the transfer is done correctly. The check is done
00132         through HAL_SD_GetCardState() function for SD card state.
00133         You could also check the DMA transfer process through the SD Tx interrupt event.
00134
00135     (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
00136         This function support only 512-bytes block length (the block size should be
00137         chosen as 512 bytes).
00138         You can choose either one block read operation or multiple block read operation
00139         by adjusting the "NumberOfBlocks" parameter.
00140         After this, you have to ensure that the transfer is done correctly. The check is done
00141         through HAL_SD_GetCardState() function for SD card state.
00142         You could also check the IT transfer process through the SD Tx interrupt event.
00143
00144   *** SD card status ***
00145   ======================
00146   [..]
00147     (+) The SD Status contains status bits that are related to the SD Memory
00148         Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
00149
00150   *** SD card information ***
00151   ===========================
00152   [..]
00153     (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
00154         It returns useful information about the SD card such as block size, card type,
00155         block number ...
00156
00157   *** SD card CSD register ***
00158   ============================
00159     (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
00160         Some of the CSD parameters are useful for card initialization and identification.
00161
00162   *** SD card CID register ***
00163   ============================
00164     (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
00165         Some of the CSD parameters are useful for card initialization and identification.
00166
00167   *** SD HAL driver macros list ***
00168   ==================================
00169   [..]
00170     Below the list of most used macros in SD HAL driver.
00171
00172     (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
00173     (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
00174     (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
00175     (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
00176
00177     (@) You can refer to the SD HAL driver header file for more useful macros
00178
00179   *** Callback registration ***
00180   =============================================
00181   [..]
00182     The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
00183     allows the user to configure dynamically the driver callbacks.
00184
00185     Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
00186     it allows to register following callbacks:
00187       (+) TxCpltCallback : callback when a transmission transfer is completed.
00188       (+) RxCpltCallback : callback when a reception transfer is completed.
00189       (+) ErrorCallback : callback when error occurs.
00190       (+) AbortCpltCallback : callback when abort is completed.
00191       (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
00192       (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
00193       (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
00194       (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
00195       (+) MspInitCallback    : SD MspInit.
00196       (+) MspDeInitCallback  : SD MspDeInit.
00197     This function takes as parameters the HAL peripheral handle, the Callback ID
00198     and a pointer to the user callback function.
00199     For specific callbacks TransceiverCallback use dedicated register callbacks:
00200     respectively @ref HAL_SD_RegisterTransceiverCallback().
00201
00202     Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
00203     weak (surcharged) function. It allows to reset following callbacks:
00204       (+) TxCpltCallback : callback when a transmission transfer is completed.
00205       (+) RxCpltCallback : callback when a reception transfer is completed.
00206       (+) ErrorCallback : callback when error occurs.
00207       (+) AbortCpltCallback : callback when abort is completed.
00208       (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
00209       (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
00210       (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
00211       (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
00212       (+) MspInitCallback    : SD MspInit.
00213       (+) MspDeInitCallback  : SD MspDeInit.
00214     This function) takes as parameters the HAL peripheral handle and the Callback ID.
00215     For specific callbacks TransceiverCallback use dedicated unregister callbacks:
00216     respectively @ref HAL_SD_UnRegisterTransceiverCallback().
00217
00218     By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
00219     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00220     Exception done for MspInit and MspDeInit callbacks that are respectively
00221     reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
00222     and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
00223     If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
00224     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00225
00226     Callbacks can be registered/unregistered in READY state only.
00227     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00228     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00229     during the Init/DeInit.
00230     In that case first register the MspInit/MspDeInit user callbacks
00231     using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
00232     or @ref HAL_SD_Init function.
00233
00234     When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
00235     not defined, the callback registering feature is not available
00236     and weak (surcharged) callbacks are used.
00237
00238   @endverbatim
00239   ******************************************************************************
00240   * @attention
00241   *
00242   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00243   * All rights reserved.</center></h2>
00244   *
00245   * This software component is licensed by ST under BSD 3-Clause license,
00246   * the "License"; You may not use this file except in compliance with the
00247   * License. You may obtain a copy of the License at:
00248   *                       opensource.org/licenses/BSD-3-Clause
00249   *
00250   ******************************************************************************
00251   */
00252
00253 /* Includes ------------------------------------------------------------------*/
00254 #include "stm32h7xx_hal.h"
00255
00256 /** @addtogroup STM32H7xx_HAL_Driver
00257   * @{
00258   */
00259
00260 /** @addtogroup SD
00261   * @{
00262   */
00263
00264 #ifdef HAL_SD_MODULE_ENABLED
00265
00266 /* Private typedef -----------------------------------------------------------*/
00267 /* Private define ------------------------------------------------------------*/
00268 /** @addtogroup SD_Private_Defines
00269   * @{
00270   */
00271
00272 /**
00273   * @}
00274   */
00275
00276 /* Private macro -------------------------------------------------------------*/
00277 #if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
00278 #define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)?  \
00279                DLYB_SDMMC1 : DLYB_SDMMC2 )
00280 #elif defined (DLYB_SDMMC1)
00281 #define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
00282 #endif
00283 /* Private variables ---------------------------------------------------------*/
00284 /* Private function prototypes -----------------------------------------------*/
00285 /* Private functions ---------------------------------------------------------*/
00286 /** @defgroup SD_Private_Functions SD Private Functions
00287   * @{
00288   */
00289 static uint32_t SD_InitCard       (SD_HandleTypeDef *hsd);
00290 static uint32_t SD_PowerON        (SD_HandleTypeDef *hsd);
00291 static uint32_t SD_SendSDStatus   (SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00292 static uint32_t SD_SendStatus     (SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00293 static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd);
00294 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00295 static uint32_t SD_FindSCR        (SD_HandleTypeDef *hsd, uint32_t *pSCR);
00296 static void     SD_PowerOFF       (SD_HandleTypeDef *hsd);
00297 static void     SD_Write_IT       (SD_HandleTypeDef *hsd);
00298 static void     SD_Read_IT        (SD_HandleTypeDef *hsd);
00299 static uint32_t SD_HighSpeed      (SD_HandleTypeDef *hsd);
00300 #if (USE_SD_TRANSCEIVER != 0U)
00301 static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd);
00302 static uint32_t SD_DDR_Mode       (SD_HandleTypeDef *hsd);
00303 #endif /* USE_SD_TRANSCEIVER */
00304 /**
00305   * @}
00306   */
00307
00308 /* Exported functions --------------------------------------------------------*/
00309 /** @addtogroup SD_Exported_Functions
00310   * @{
00311   */
00312
00313 /** @addtogroup SD_Exported_Functions_Group1
00314  *  @brief   Initialization and de-initialization functions
00315  *
00316 @verbatim
00317   ==============================================================================
00318           ##### Initialization and de-initialization functions #####
00319   ==============================================================================
00320   [..]
00321     This section provides functions allowing to initialize/de-initialize the SD
00322     card device to be ready for use.
00323
00324 @endverbatim
00325   * @{
00326   */
00327
00328 /**
00329   * @brief  Initializes the SD according to the specified parameters in the
00330             SD_HandleTypeDef and create the associated handle.
00331   * @param  hsd: Pointer to the SD handle
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
00335 {
00336   HAL_SD_CardStatusTypeDef CardStatus;
00337   uint32_t speedgrade, unitsize;
00338   uint32_t tickstart;
00339
00340   /* Check the SD handle allocation */
00341   if(hsd == NULL)
00342   {
00343     return HAL_ERROR;
00344   }
00345
00346   /* Check the parameters */
00347   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
00348   assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
00349   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
00350   assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
00351   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
00352   assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
00353
00354   if(hsd->State == HAL_SD_STATE_RESET)
00355   {
00356     /* Allocate lock resource and initialize it */
00357     hsd->Lock = HAL_UNLOCKED;
00358
00359 #if (USE_SD_TRANSCEIVER != 0U)
00360     /* Force  SDMMC_TRANSCEIVER_PRESENT for Legacy usage */
00361     if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN)
00362     {
00363       hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
00364     }
00365 #endif
00366 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00367     /* Reset Callback pointers in HAL_SD_STATE_RESET only */
00368     hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
00369     hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
00370     hsd->ErrorCallback     = HAL_SD_ErrorCallback;
00371     hsd->AbortCpltCallback = HAL_SD_AbortCallback;
00372     hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback;
00373     hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback;
00374     hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback;
00375     hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback;
00376 #if (USE_SD_TRANSCEIVER != 0U)
00377     if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
00378     {
00379       hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
00380     }
00381 #endif /* USE_SD_TRANSCEIVER */
00382
00383     if(hsd->MspInitCallback == NULL)
00384     {
00385       hsd->MspInitCallback = HAL_SD_MspInit;
00386     }
00387
00388     /* Init the low level hardware */
00389     hsd->MspInitCallback(hsd);
00390 #else
00391     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00392     HAL_SD_MspInit(hsd);
00393 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00394   }
00395
00396   hsd->State = HAL_SD_STATE_BUSY;
00397
00398   /* Initialize the Card parameters */
00399   if (HAL_SD_InitCard(hsd) != HAL_OK)
00400   {
00401     return HAL_ERROR;
00402   }
00403
00404   if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
00405   {
00406     return HAL_ERROR;
00407   }
00408   /* Get Initial Card Speed from Card Status*/
00409   speedgrade = CardStatus.UhsSpeedGrade;
00410   unitsize = CardStatus.UhsAllocationUnitSize;
00411   if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
00412   {
00413     hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
00414   }
00415   else
00416   {
00417     if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
00418     {
00419       hsd->SdCard.CardSpeed  = CARD_HIGH_SPEED;
00420     }
00421     else
00422     {
00423       hsd->SdCard.CardSpeed  = CARD_NORMAL_SPEED;
00424     }
00425
00426   }
00427   /* Configure the bus wide */
00428   if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
00429   {
00430     return HAL_ERROR;
00431   }
00432
00433   /* Verify that SD card is ready to use after Initialization */
00434   tickstart = HAL_GetTick();
00435   while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
00436   {
00437     if((HAL_GetTick()-tickstart) >=  SDMMC_DATATIMEOUT)
00438     {
00439       hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
00440       hsd->State= HAL_SD_STATE_READY;
00441       return HAL_TIMEOUT;
00442     }
00443   }
00444
00445   /* Initialize the error code */
00446   hsd->ErrorCode = HAL_SD_ERROR_NONE;
00447
00448   /* Initialize the SD operation */
00449   hsd->Context = SD_CONTEXT_NONE;
00450
00451   /* Initialize the SD state */
00452   hsd->State = HAL_SD_STATE_READY;
00453
00454   return HAL_OK;
00455 }
00456
00457 /**
00458   * @brief  Initializes the SD Card.
00459   * @param  hsd: Pointer to SD handle
00460   * @note   This function initializes the SD card. It could be used when a card
00461             re-initialization is needed.
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
00465 {
00466   uint32_t errorstate;
00467   HAL_StatusTypeDef status;
00468   SD_InitTypeDef Init;
00469   uint32_t sdmmc_clk;
00470
00471   /* Default SDMMC peripheral configuration for SD card initialization */
00472   Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00473   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00474   Init.BusWide             = SDMMC_BUS_WIDE_1B;
00475   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00476   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
00477
00478 #if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
00479   if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
00480   {
00481     /* Set Transceiver polarity */
00482     hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
00483   }
00484 #endif /* USE_SD_TRANSCEIVER  */
00485
00486   /* Initialize SDMMC peripheral interface with default configuration */
00487   status = SDMMC_Init(hsd->Instance, Init);
00488   if(status != HAL_OK)
00489   {
00490     return HAL_ERROR;
00491   }
00492
00493   /* Set Power State to ON */
00494   status = SDMMC_PowerState_ON(hsd->Instance);
00495   if(status != HAL_OK)
00496   {
00497     return HAL_ERROR;
00498   }
00499
00500   /* wait 74 Cycles: required power up waiting time before starting
00501      the SD initialization sequence */
00502   sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)/(2U*SDMMC_INIT_CLK_DIV);
00503
00504   if(sdmmc_clk != 0U)
00505   {
00506     HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
00507   }
00508   else
00509   {
00510     HAL_Delay(2U);
00511   }
00512
00513   /* Identify card operating voltage */
00514   errorstate = SD_PowerON(hsd);
00515   if(errorstate != HAL_SD_ERROR_NONE)
00516   {
00517     hsd->State = HAL_SD_STATE_READY;
00518     hsd->ErrorCode |= errorstate;
00519     return HAL_ERROR;
00520   }
00521
00522   /* Card initialization */
00523   errorstate = SD_InitCard(hsd);
00524   if(errorstate != HAL_SD_ERROR_NONE)
00525   {
00526     hsd->State = HAL_SD_STATE_READY;
00527     hsd->ErrorCode |= errorstate;
00528     return HAL_ERROR;
00529   }
00530
00531   return HAL_OK;
00532 }
00533
00534 /**
00535   * @brief  De-Initializes the SD card.
00536   * @param  hsd: Pointer to SD handle
00537   * @retval HAL status
00538   */
00539 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00540 {
00541   /* Check the SD handle allocation */
00542   if(hsd == NULL)
00543   {
00544     return HAL_ERROR;
00545   }
00546
00547   /* Check the parameters */
00548   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
00549
00550   hsd->State = HAL_SD_STATE_BUSY;
00551
00552 #if (USE_SD_TRANSCEIVER != 0U)
00553   /* Desactivate the 1.8V Mode */
00554   if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
00555   {
00556 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00557     if(hsd->DriveTransceiver_1_8V_Callback == NULL)
00558     {
00559       hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
00560     }
00561     hsd->DriveTransceiver_1_8V_Callback(RESET);
00562 #else
00563     HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
00564 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00565   }
00566 #endif /* USE_SD_TRANSCEIVER   */
00567
00568   /* Set SD power state to off */
00569   SD_PowerOFF(hsd);
00570
00571 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00572   if(hsd->MspDeInitCallback == NULL)
00573   {
00574     hsd->MspDeInitCallback = HAL_SD_MspDeInit;
00575   }
00576
00577   /* DeInit the low level hardware */
00578   hsd->MspDeInitCallback(hsd);
00579 #else
00580   /* De-Initialize the MSP layer */
00581   HAL_SD_MspDeInit(hsd);
00582 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00583
00584   hsd->ErrorCode = HAL_SD_ERROR_NONE;
00585   hsd->State = HAL_SD_STATE_RESET;
00586
00587   return HAL_OK;
00588 }
00589
00590
00591 /**
00592   * @brief  Initializes the SD MSP.
00593   * @param  hsd: Pointer to SD handle
00594   * @retval None
00595   */
00596 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hsd);
00600
00601   /* NOTE : This function should not be modified, when the callback is needed,
00602             the HAL_SD_MspInit could be implemented in the user file
00603    */
00604 }
00605
00606 /**
00607   * @brief  De-Initialize SD MSP.
00608   * @param  hsd: Pointer to SD handle
00609   * @retval None
00610   */
00611 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00612 {
00613   /* Prevent unused argument(s) compilation warning */
00614   UNUSED(hsd);
00615
00616   /* NOTE : This function should not be modified, when the callback is needed,
00617             the HAL_SD_MspDeInit could be implemented in the user file
00618    */
00619 }
00620
00621 /**
00622   * @}
00623   */
00624
00625 /** @addtogroup SD_Exported_Functions_Group2
00626  *  @brief   Data transfer functions
00627  *
00628 @verbatim
00629   ==============================================================================
00630                         ##### IO operation functions #####
00631   ==============================================================================
00632   [..]
00633     This subsection provides a set of functions allowing to manage the data
00634     transfer from/to SD card.
00635
00636 @endverbatim
00637   * @{
00638   */
00639
00640 /**
00641   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00642   *         is managed by polling mode.
00643   * @note   This API should be followed by a check on the card state through
00644   *         HAL_SD_GetCardState().
00645   * @param  hsd: Pointer to SD handle
00646   * @param  pData: pointer to the buffer that will contain the received data
00647   * @param  BlockAdd: Block Address from where data is to be read
00648   * @param  NumberOfBlocks: Number of SD blocks to read
00649   * @param  Timeout: Specify timeout value
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00653 {
00654   SDMMC_DataInitTypeDef config;
00655   uint32_t errorstate;
00656   uint32_t tickstart = HAL_GetTick();
00657   uint32_t count, data, dataremaining;
00658   uint32_t add = BlockAdd;
00659   uint8_t *tempbuff = pData;
00660
00661   if(NULL == pData)
00662   {
00663     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00664     return HAL_ERROR;
00665   }
00666
00667   if(hsd->State == HAL_SD_STATE_READY)
00668   {
00669     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00670
00671     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00672     {
00673       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00674       return HAL_ERROR;
00675     }
00676
00677     hsd->State = HAL_SD_STATE_BUSY;
00678
00679     /* Initialize data control register */
00680     hsd->Instance->DCTRL = 0U;
00681
00682     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00683     {
00684       add *= 512U;
00685     }
00686
00687     /* Set Block Size for Card */
00688     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00689     if(errorstate != HAL_SD_ERROR_NONE)
00690     {
00691       /* Clear all the static flags */
00692       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00693       hsd->ErrorCode |= errorstate;
00694       hsd->State = HAL_SD_STATE_READY;
00695       return HAL_ERROR;
00696     }
00697
00698     /* Configure the SD DPSM (Data Path State Machine) */
00699     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00700     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00701     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00702     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00703     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00704     config.DPSM          = SDMMC_DPSM_DISABLE;
00705     (void)SDMMC_ConfigData(hsd->Instance, &config);
00706     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00707
00708     /* Read block(s) in polling mode */
00709     if(NumberOfBlocks > 1U)
00710     {
00711       hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
00712
00713       /* Read Multi Block command */
00714       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
00715     }
00716     else
00717     {
00718       hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
00719
00720       /* Read Single Block command */
00721       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
00722     }
00723     if(errorstate != HAL_SD_ERROR_NONE)
00724     {
00725       /* Clear all the static flags */
00726       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00727       hsd->ErrorCode |= errorstate;
00728       hsd->State = HAL_SD_STATE_READY;
00729       hsd->Context = SD_CONTEXT_NONE;
00730       return HAL_ERROR;
00731     }
00732
00733     /* Poll on SDMMC flags */
00734     dataremaining = config.DataLength;
00735     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00736     {
00737       if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
00738       {
00739         /* Read data from SDMMC Rx FIFO */
00740         for(count = 0U; count < 8U; count++)
00741         {
00742           data = SDMMC_ReadFIFO(hsd->Instance);
00743           *tempbuff = (uint8_t)(data & 0xFFU);
00744           tempbuff++;
00745           *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
00746           tempbuff++;
00747           *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
00748           tempbuff++;
00749           *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
00750           tempbuff++;
00751         }
00752         dataremaining -= 32U;
00753       }
00754
00755       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
00756       {
00757         /* Clear all the static flags */
00758         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00759         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
00760         hsd->State= HAL_SD_STATE_READY;
00761         hsd->Context = SD_CONTEXT_NONE;
00762         return HAL_TIMEOUT;
00763       }
00764     }
00765     __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
00766
00767     /* Send stop transmission command in case of multiblock read */
00768     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00769     {
00770       if(hsd->SdCard.CardType != CARD_SECURED)
00771       {
00772         /* Send stop transmission command */
00773         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00774         if(errorstate != HAL_SD_ERROR_NONE)
00775         {
00776           /* Clear all the static flags */
00777           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00778           hsd->ErrorCode |= errorstate;
00779           hsd->State = HAL_SD_STATE_READY;
00780           hsd->Context = SD_CONTEXT_NONE;
00781           return HAL_ERROR;
00782         }
00783       }
00784     }
00785
00786     /* Get error state */
00787     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00788     {
00789       /* Clear all the static flags */
00790       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00791       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00792       hsd->State = HAL_SD_STATE_READY;
00793       hsd->Context = SD_CONTEXT_NONE;
00794       return HAL_ERROR;
00795     }
00796     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00797     {
00798       /* Clear all the static flags */
00799       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00800       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00801       hsd->State = HAL_SD_STATE_READY;
00802       hsd->Context = SD_CONTEXT_NONE;
00803       return HAL_ERROR;
00804     }
00805     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
00806     {
00807       /* Clear all the static flags */
00808       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00809       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
00810       hsd->State = HAL_SD_STATE_READY;
00811       hsd->Context = SD_CONTEXT_NONE;
00812       return HAL_ERROR;
00813     }
00814     else
00815     {
00816       /* Nothing to do */
00817     }
00818
00819     /* Clear all the static flags */
00820     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
00821
00822     hsd->State = HAL_SD_STATE_READY;
00823
00824     return HAL_OK;
00825   }
00826   else
00827   {
00828     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
00829     return HAL_ERROR;
00830   }
00831 }
00832
00833 /**
00834   * @brief  Allows to write block(s) to a specified address in a card. The Data
00835   *         transfer is managed by polling mode.
00836   * @note   This API should be followed by a check on the card state through
00837   *         HAL_SD_GetCardState().
00838   * @param  hsd: Pointer to SD handle
00839   * @param  pData: pointer to the buffer that will contain the data to transmit
00840   * @param  BlockAdd: Block Address where data will be written
00841   * @param  NumberOfBlocks: Number of SD blocks to write
00842   * @param  Timeout: Specify timeout value
00843   * @retval HAL status
00844   */
00845 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00846 {
00847   SDMMC_DataInitTypeDef config;
00848   uint32_t errorstate;
00849   uint32_t tickstart = HAL_GetTick();
00850   uint32_t count, data, dataremaining;
00851   uint32_t add = BlockAdd;
00852   uint8_t *tempbuff = pData;
00853
00854   if(NULL == pData)
00855   {
00856     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00857     return HAL_ERROR;
00858   }
00859
00860   if(hsd->State == HAL_SD_STATE_READY)
00861   {
00862     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00863
00864     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00865     {
00866       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00867       return HAL_ERROR;
00868     }
00869
00870     hsd->State = HAL_SD_STATE_BUSY;
00871
00872     /* Initialize data control register */
00873     hsd->Instance->DCTRL = 0U;
00874
00875     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00876     {
00877       add *= 512U;
00878     }
00879
00880     /* Set Block Size for Card */
00881     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00882     if(errorstate != HAL_SD_ERROR_NONE)
00883     {
00884       /* Clear all the static flags */
00885       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00886       hsd->ErrorCode |= errorstate;
00887       hsd->State = HAL_SD_STATE_READY;
00888       return HAL_ERROR;
00889     }
00890
00891     /* Configure the SD DPSM (Data Path State Machine) */
00892     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00893     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00894     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00895     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00896     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00897     config.DPSM          = SDMMC_DPSM_DISABLE;
00898     (void)SDMMC_ConfigData(hsd->Instance, &config);
00899     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00900
00901     /* Write Blocks in Polling mode */
00902     if(NumberOfBlocks > 1U)
00903     {
00904       hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
00905
00906       /* Write Multi Block command */
00907       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
00908     }
00909     else
00910     {
00911       hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
00912
00913       /* Write Single Block command */
00914       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
00915     }
00916     if(errorstate != HAL_SD_ERROR_NONE)
00917     {
00918       /* Clear all the static flags */
00919       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00920       hsd->ErrorCode |= errorstate;
00921       hsd->State = HAL_SD_STATE_READY;
00922       hsd->Context = SD_CONTEXT_NONE;
00923       return HAL_ERROR;
00924     }
00925
00926     /* Write block(s) in polling mode */
00927     dataremaining = config.DataLength;
00928     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00929     {
00930       if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
00931       {
00932         /* Write data to SDMMC Tx FIFO */
00933         for(count = 0U; count < 8U; count++)
00934         {
00935           data = (uint32_t)(*tempbuff);
00936           tempbuff++;
00937           data |= ((uint32_t)(*tempbuff) << 8U);
00938           tempbuff++;
00939           data |= ((uint32_t)(*tempbuff) << 16U);
00940           tempbuff++;
00941           data |= ((uint32_t)(*tempbuff) << 24U);
00942           tempbuff++;
00943           (void)SDMMC_WriteFIFO(hsd->Instance, &data);
00944         }
00945         dataremaining -= 32U;
00946       }
00947
00948       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
00949       {
00950         /* Clear all the static flags */
00951         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00952         hsd->ErrorCode |= errorstate;
00953         hsd->State = HAL_SD_STATE_READY;
00954         hsd->Context = SD_CONTEXT_NONE;
00955         return HAL_TIMEOUT;
00956       }
00957     }
00958     __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
00959
00960     /* Send stop transmission command in case of multiblock write */
00961     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00962     {
00963       if(hsd->SdCard.CardType != CARD_SECURED)
00964       {
00965         /* Send stop transmission command */
00966         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00967         if(errorstate != HAL_SD_ERROR_NONE)
00968         {
00969           /* Clear all the static flags */
00970           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00971           hsd->ErrorCode |= errorstate;
00972           hsd->State = HAL_SD_STATE_READY;
00973           hsd->Context = SD_CONTEXT_NONE;
00974           return HAL_ERROR;
00975         }
00976       }
00977     }
00978
00979     /* Get error state */
00980     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00981     {
00982       /* Clear all the static flags */
00983       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00984       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00985       hsd->State = HAL_SD_STATE_READY;
00986       hsd->Context = SD_CONTEXT_NONE;
00987       return HAL_ERROR;
00988     }
00989     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00990     {
00991       /* Clear all the static flags */
00992       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00993       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00994       hsd->State = HAL_SD_STATE_READY;
00995       hsd->Context = SD_CONTEXT_NONE;
00996       return HAL_ERROR;
00997     }
00998     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
00999     {
01000       /* Clear all the static flags */
01001       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01002       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
01003       hsd->State = HAL_SD_STATE_READY;
01004       hsd->Context = SD_CONTEXT_NONE;
01005       return HAL_ERROR;
01006     }
01007     else
01008     {
01009       /* Nothing to do */
01010     }
01011
01012     /* Clear all the static flags */
01013     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
01014
01015     hsd->State = HAL_SD_STATE_READY;
01016
01017     return HAL_OK;
01018   }
01019   else
01020   {
01021     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
01022     return HAL_ERROR;
01023   }
01024 }
01025
01026 /**
01027   * @brief  Reads block(s) from a specified address in a card. The Data transfer
01028   *         is managed in interrupt mode.
01029   * @note   This API should be followed by a check on the card state through
01030   *         HAL_SD_GetCardState().
01031   * @note   You could also check the IT transfer process through the SD Rx
01032   *         interrupt event.
01033   * @param  hsd: Pointer to SD handle
01034   * @param  pData: Pointer to the buffer that will contain the received data
01035   * @param  BlockAdd: Block Address from where data is to be read
01036   * @param  NumberOfBlocks: Number of blocks to read.
01037   * @retval HAL status
01038   */
01039 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01040 {
01041   SDMMC_DataInitTypeDef config;
01042   uint32_t errorstate;
01043   uint32_t add = BlockAdd;
01044
01045   if(NULL == pData)
01046   {
01047     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01048     return HAL_ERROR;
01049   }
01050
01051   if(hsd->State == HAL_SD_STATE_READY)
01052   {
01053     hsd->ErrorCode = HAL_SD_ERROR_NONE;
01054
01055     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01056     {
01057       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01058       return HAL_ERROR;
01059     }
01060
01061     hsd->State = HAL_SD_STATE_BUSY;
01062
01063     /* Initialize data control register */
01064     hsd->Instance->DCTRL = 0U;
01065
01066     hsd->pRxBuffPtr = pData;
01067     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
01068
01069     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
01070
01071     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01072     {
01073       add *= 512U;
01074     }
01075
01076     /* Set Block Size for Card */
01077     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01078     if(errorstate != HAL_SD_ERROR_NONE)
01079     {
01080       /* Clear all the static flags */
01081       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01082       hsd->ErrorCode |= errorstate;
01083       hsd->State = HAL_SD_STATE_READY;
01084       return HAL_ERROR;
01085     }
01086
01087     /* Configure the SD DPSM (Data Path State Machine) */
01088     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01089     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01090     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01091     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01092     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01093     config.DPSM          = SDMMC_DPSM_DISABLE;
01094     (void)SDMMC_ConfigData(hsd->Instance, &config);
01095     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01096
01097     /* Read Blocks in IT mode */
01098     if(NumberOfBlocks > 1U)
01099     {
01100       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
01101
01102       /* Read Multi Block command */
01103       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
01104     }
01105     else
01106     {
01107       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
01108
01109       /* Read Single Block command */
01110       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
01111     }
01112     if(errorstate != HAL_SD_ERROR_NONE)
01113     {
01114       /* Clear all the static flags */
01115       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01116       hsd->ErrorCode |= errorstate;
01117       hsd->State = HAL_SD_STATE_READY;
01118       hsd->Context = SD_CONTEXT_NONE;
01119       return HAL_ERROR;
01120     }
01121
01122     return HAL_OK;
01123   }
01124   else
01125   {
01126     return HAL_BUSY;
01127   }
01128 }
01129
01130 /**
01131   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01132   *         is managed in interrupt mode.
01133   * @note   This API should be followed by a check on the card state through
01134   *         HAL_SD_GetCardState().
01135   * @note   You could also check the IT transfer process through the SD Tx
01136   *         interrupt event.
01137   * @param  hsd: Pointer to SD handle
01138   * @param  pData: Pointer to the buffer that will contain the data to transmit
01139   * @param  BlockAdd: Block Address where data will be written
01140   * @param  NumberOfBlocks: Number of blocks to write
01141   * @retval HAL status
01142   */
01143 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01144 {
01145   SDMMC_DataInitTypeDef config;
01146   uint32_t errorstate;
01147   uint32_t add = BlockAdd;
01148
01149   if(NULL == pData)
01150   {
01151     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01152     return HAL_ERROR;
01153   }
01154
01155   if(hsd->State == HAL_SD_STATE_READY)
01156   {
01157     hsd->ErrorCode = HAL_SD_ERROR_NONE;
01158
01159     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01160     {
01161       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01162       return HAL_ERROR;
01163     }
01164
01165     hsd->State = HAL_SD_STATE_BUSY;
01166
01167     /* Initialize data control register */
01168     hsd->Instance->DCTRL = 0U;
01169
01170     hsd->pTxBuffPtr = pData;
01171     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
01172
01173     /* Enable transfer interrupts */
01174     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
01175
01176     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01177     {
01178       add *= 512U;
01179     }
01180
01181     /* Set Block Size for Card */
01182     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01183     if(errorstate != HAL_SD_ERROR_NONE)
01184     {
01185       /* Clear all the static flags */
01186       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01187       hsd->ErrorCode |= errorstate;
01188       hsd->State = HAL_SD_STATE_READY;
01189       return HAL_ERROR;
01190     }
01191
01192     /* Configure the SD DPSM (Data Path State Machine) */
01193     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01194     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01195     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01196     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01197     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01198     config.DPSM          = SDMMC_DPSM_DISABLE;
01199     (void)SDMMC_ConfigData(hsd->Instance, &config);
01200
01201     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01202
01203     /* Write Blocks in Polling mode */
01204     if(NumberOfBlocks > 1U)
01205     {
01206       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
01207
01208       /* Write Multi Block command */
01209       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
01210     }
01211     else
01212     {
01213       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
01214
01215       /* Write Single Block command */
01216       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
01217     }
01218     if(errorstate != HAL_SD_ERROR_NONE)
01219     {
01220       /* Clear all the static flags */
01221       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01222       hsd->ErrorCode |= errorstate;
01223       hsd->State = HAL_SD_STATE_READY;
01224       hsd->Context = SD_CONTEXT_NONE;
01225       return HAL_ERROR;
01226     }
01227
01228     return HAL_OK;
01229   }
01230   else
01231   {
01232     return HAL_BUSY;
01233   }
01234 }
01235
01236 /**
01237   * @brief  Reads block(s) from a specified address in a card. The Data transfer
01238   *         is managed by DMA mode.
01239   * @note   This API should be followed by a check on the card state through
01240   *         HAL_SD_GetCardState().
01241   * @note   You could also check the DMA transfer process through the SD Rx
01242   *         interrupt event.
01243   * @param  hsd: Pointer SD handle
01244   * @param  pData: Pointer to the buffer that will contain the received data
01245   * @param  BlockAdd: Block Address from where data is to be read
01246   * @param  NumberOfBlocks: Number of blocks to read.
01247   * @retval HAL status
01248   */
01249 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01250 {
01251   SDMMC_DataInitTypeDef config;
01252   uint32_t errorstate;
01253   uint32_t add = BlockAdd;
01254
01255   if(NULL == pData)
01256   {
01257     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01258     return HAL_ERROR;
01259   }
01260
01261   if(hsd->State == HAL_SD_STATE_READY)
01262   {
01263     hsd->ErrorCode = HAL_SD_ERROR_NONE;
01264
01265     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01266     {
01267       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01268       return HAL_ERROR;
01269     }
01270
01271     hsd->State = HAL_SD_STATE_BUSY;
01272
01273     /* Initialize data control register */
01274     hsd->Instance->DCTRL = 0U;
01275
01276     hsd->pRxBuffPtr = pData;
01277     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
01278
01279     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01280     {
01281       add *= 512U;
01282     }
01283
01284     /* Set Block Size for Card */
01285     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01286     if(errorstate != HAL_SD_ERROR_NONE)
01287     {
01288       /* Clear all the static flags */
01289       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01290       hsd->ErrorCode |= errorstate;
01291       hsd->State = HAL_SD_STATE_READY;
01292       return HAL_ERROR;
01293     }
01294
01295     /* Configure the SD DPSM (Data Path State Machine) */
01296     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01297     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01298     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01299     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01300     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01301     config.DPSM          = SDMMC_DPSM_DISABLE;
01302     (void)SDMMC_ConfigData(hsd->Instance, &config);
01303
01304     /* Enable transfer interrupts */
01305     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01306
01307     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01308     hsd->Instance->IDMABASE0 = (uint32_t) pData ;
01309     hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01310
01311     /* Read Blocks in DMA mode */
01312     if(NumberOfBlocks > 1U)
01313     {
01314       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01315
01316       /* Read Multi Block command */
01317       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
01318     }
01319     else
01320     {
01321       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
01322
01323       /* Read Single Block command */
01324       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
01325     }
01326     if(errorstate != HAL_SD_ERROR_NONE)
01327     {
01328       /* Clear all the static flags */
01329       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01330       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01331       hsd->ErrorCode |= errorstate;
01332       hsd->State = HAL_SD_STATE_READY;
01333       hsd->Context = SD_CONTEXT_NONE;
01334       return HAL_ERROR;
01335     }
01336
01337     return HAL_OK;
01338   }
01339   else
01340   {
01341     return HAL_BUSY;
01342   }
01343 }
01344
01345 /**
01346   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01347   *         is managed by DMA mode.
01348   * @note   This API should be followed by a check on the card state through
01349   *         HAL_SD_GetCardState().
01350   * @note   You could also check the DMA transfer process through the SD Tx
01351   *         interrupt event.
01352   * @param  hsd: Pointer to SD handle
01353   * @param  pData: Pointer to the buffer that will contain the data to transmit
01354   * @param  BlockAdd: Block Address where data will be written
01355   * @param  NumberOfBlocks: Number of blocks to write
01356   * @retval HAL status
01357   */
01358 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01359 {
01360   SDMMC_DataInitTypeDef config;
01361   uint32_t errorstate;
01362   uint32_t add = BlockAdd;
01363
01364   if(NULL == pData)
01365   {
01366     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01367     return HAL_ERROR;
01368   }
01369
01370   if(hsd->State == HAL_SD_STATE_READY)
01371   {
01372     hsd->ErrorCode = HAL_SD_ERROR_NONE;
01373
01374     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01375     {
01376       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01377       return HAL_ERROR;
01378     }
01379
01380     hsd->State = HAL_SD_STATE_BUSY;
01381
01382     /* Initialize data control register */
01383     hsd->Instance->DCTRL = 0U;
01384
01385     hsd->pTxBuffPtr = pData;
01386     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
01387
01388     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01389     {
01390       add *= 512U;
01391     }
01392
01393     /* Set Block Size for Card */
01394     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01395     if(errorstate != HAL_SD_ERROR_NONE)
01396     {
01397       /* Clear all the static flags */
01398       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01399       hsd->ErrorCode |= errorstate;
01400       hsd->State = HAL_SD_STATE_READY;
01401       return HAL_ERROR;
01402     }
01403     /* Configure the SD DPSM (Data Path State Machine) */
01404     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01405     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01406     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01407     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01408     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01409     config.DPSM          = SDMMC_DPSM_DISABLE;
01410     (void)SDMMC_ConfigData(hsd->Instance, &config);
01411
01412     /* Enable transfer interrupts */
01413     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01414
01415     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01416
01417     hsd->Instance->IDMABASE0 = (uint32_t) pData ;
01418     hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01419
01420     /* Write Blocks in Polling mode */
01421     if(NumberOfBlocks > 1U)
01422     {
01423       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01424
01425       /* Write Multi Block command */
01426       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
01427     }
01428     else
01429     {
01430       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
01431
01432       /* Write Single Block command */
01433       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
01434     }
01435     if(errorstate != HAL_SD_ERROR_NONE)
01436     {
01437       /* Clear all the static flags */
01438       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01439       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01440       hsd->ErrorCode |= errorstate;
01441       hsd->State = HAL_SD_STATE_READY;
01442       hsd->Context = SD_CONTEXT_NONE;
01443       return HAL_ERROR;
01444     }
01445
01446     return HAL_OK;
01447   }
01448   else
01449   {
01450     return HAL_BUSY;
01451   }
01452 }
01453
01454 /**
01455   * @brief  Erases the specified memory area of the given SD card.
01456   * @note   This API should be followed by a check on the card state through
01457   *         HAL_SD_GetCardState().
01458   * @param  hsd: Pointer to SD handle
01459   * @param  BlockStartAdd: Start Block address
01460   * @param  BlockEndAdd: End Block address
01461   * @retval HAL status
01462   */
01463 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
01464 {
01465   uint32_t errorstate;
01466   uint32_t start_add = BlockStartAdd;
01467   uint32_t end_add = BlockEndAdd;
01468
01469   if(hsd->State == HAL_SD_STATE_READY)
01470   {
01471     hsd->ErrorCode = HAL_SD_ERROR_NONE;
01472
01473     if(end_add < start_add)
01474     {
01475       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01476       return HAL_ERROR;
01477     }
01478
01479     if(end_add > (hsd->SdCard.LogBlockNbr))
01480     {
01481       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01482       return HAL_ERROR;
01483     }
01484
01485     hsd->State = HAL_SD_STATE_BUSY;
01486
01487     /* Check if the card command class supports erase command */
01488     if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
01489     {
01490       /* Clear all the static flags */
01491       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01492       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
01493       hsd->State = HAL_SD_STATE_READY;
01494       return HAL_ERROR;
01495     }
01496
01497     if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
01498     {
01499       /* Clear all the static flags */
01500       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01501       hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
01502       hsd->State = HAL_SD_STATE_READY;
01503       return HAL_ERROR;
01504     }
01505
01506     /* Get start and end block for high capacity cards */
01507     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01508     {
01509       start_add *= 512U;
01510       end_add   *= 512U;
01511     }
01512
01513     /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01514     if(hsd->SdCard.CardType != CARD_SECURED)
01515     {
01516       /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01517       errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
01518       if(errorstate != HAL_SD_ERROR_NONE)
01519       {
01520         /* Clear all the static flags */
01521         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01522         hsd->ErrorCode |= errorstate;
01523         hsd->State = HAL_SD_STATE_READY;
01524         return HAL_ERROR;
01525       }
01526
01527       /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01528       errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
01529       if(errorstate != HAL_SD_ERROR_NONE)
01530       {
01531         /* Clear all the static flags */
01532         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01533         hsd->ErrorCode |= errorstate;
01534         hsd->State = HAL_SD_STATE_READY;
01535         return HAL_ERROR;
01536       }
01537     }
01538
01539     /* Send CMD38 ERASE */
01540     errorstate = SDMMC_CmdErase(hsd->Instance);
01541     if(errorstate != HAL_SD_ERROR_NONE)
01542     {
01543       /* Clear all the static flags */
01544       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01545       hsd->ErrorCode |= errorstate;
01546       hsd->State = HAL_SD_STATE_READY;
01547       return HAL_ERROR;
01548     }
01549
01550     hsd->State = HAL_SD_STATE_READY;
01551
01552     return HAL_OK;
01553   }
01554   else
01555   {
01556     return HAL_BUSY;
01557   }
01558 }
01559
01560 /**
01561   * @brief  This function handles SD card interrupt request.
01562   * @param  hsd: Pointer to SD handle
01563   * @retval None
01564   */
01565 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01566 {
01567   uint32_t errorstate;
01568   uint32_t context = hsd->Context;
01569
01570   /* Check for SDMMC interrupt flags */
01571   if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
01572   {
01573     SD_Read_IT(hsd);
01574   }
01575
01576   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
01577   {
01578     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
01579
01580     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
01581                              SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE |\
01582                              SDMMC_IT_RXFIFOHF);
01583
01584     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
01585     __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
01586
01587     if((context & SD_CONTEXT_IT) != 0U)
01588     {
01589       if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01590       {
01591         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01592         if(errorstate != HAL_SD_ERROR_NONE)
01593         {
01594           hsd->ErrorCode |= errorstate;
01595 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01596           hsd->ErrorCallback(hsd);
01597 #else
01598           HAL_SD_ErrorCallback(hsd);
01599 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01600         }
01601       }
01602
01603       /* Clear all the static flags */
01604       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
01605
01606       hsd->State = HAL_SD_STATE_READY;
01607       hsd->Context = SD_CONTEXT_NONE;
01608       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
01609       {
01610 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01611         hsd->RxCpltCallback(hsd);
01612 #else
01613         HAL_SD_RxCpltCallback(hsd);
01614 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01615       }
01616       else
01617       {
01618 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01619         hsd->TxCpltCallback(hsd);
01620 #else
01621         HAL_SD_TxCpltCallback(hsd);
01622 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01623       }
01624     }
01625     else if((context & SD_CONTEXT_DMA) != 0U)
01626     {
01627       hsd->Instance->DLEN = 0;
01628       hsd->Instance->DCTRL = 0;
01629       hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
01630
01631       /* Stop Transfer for Write Multi blocks or Read Multi blocks */
01632       if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01633       {
01634         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01635         if(errorstate != HAL_SD_ERROR_NONE)
01636         {
01637           hsd->ErrorCode |= errorstate;
01638 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01639           hsd->ErrorCallback(hsd);
01640 #else
01641           HAL_SD_ErrorCallback(hsd);
01642 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01643         }
01644       }
01645
01646       hsd->State = HAL_SD_STATE_READY;
01647       hsd->Context = SD_CONTEXT_NONE;
01648       if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
01649       {
01650 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01651         hsd->TxCpltCallback(hsd);
01652 #else
01653         HAL_SD_TxCpltCallback(hsd);
01654 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01655       }
01656       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
01657       {
01658 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01659         hsd->RxCpltCallback(hsd);
01660 #else
01661         HAL_SD_RxCpltCallback(hsd);
01662 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01663       }
01664     }
01665     else
01666     {
01667       /* Nothing to do */
01668     }
01669   }
01670
01671   else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
01672   {
01673     SD_Write_IT(hsd);
01674   }
01675
01676   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
01677   {
01678     /* Set Error code */
01679     if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
01680     {
01681       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
01682     }
01683     if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
01684     {
01685       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
01686     }
01687     if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
01688     {
01689       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
01690     }
01691     if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
01692     {
01693       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
01694     }
01695
01696     /* Clear All flags */
01697     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
01698
01699     /* Disable all interrupts */
01700     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
01701                              SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
01702
01703     __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
01704     hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
01705     hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
01706     hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
01707     hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
01708     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
01709
01710     if((context & SD_CONTEXT_IT) != 0U)
01711     {
01712       /* Set the SD state to ready to be able to start again the process */
01713       hsd->State = HAL_SD_STATE_READY;
01714       hsd->Context = SD_CONTEXT_NONE;
01715 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01716       hsd->ErrorCallback(hsd);
01717 #else
01718       HAL_SD_ErrorCallback(hsd);
01719 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01720     }
01721     else if((context & SD_CONTEXT_DMA) != 0U)
01722     {
01723       if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
01724       {
01725         /* Disable Internal DMA */
01726         __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
01727         hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
01728
01729         /* Set the SD state to ready to be able to start again the process */
01730         hsd->State = HAL_SD_STATE_READY;
01731 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01732         hsd->ErrorCallback(hsd);
01733 #else
01734         HAL_SD_ErrorCallback(hsd);
01735 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01736       }
01737     }
01738     else
01739     {
01740       /* Nothing to do */
01741     }
01742   }
01743
01744   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
01745   {
01746     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
01747     if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
01748     {
01749       /* Current buffer is buffer0, Transfer complete for buffer1 */
01750       if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
01751       {
01752 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01753         hsd->Write_DMADblBuf1CpltCallback(hsd);
01754 #else
01755         HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd);
01756 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01757       }
01758       else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
01759       {
01760 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01761         hsd->Read_DMADblBuf1CpltCallback(hsd);
01762 #else
01763         HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd);
01764 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01765       }
01766     }
01767     else /* SD_DMA_BUFFER1 */
01768     {
01769       /* Current buffer is buffer1, Transfer complete for buffer0 */
01770       if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
01771       {
01772 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01773         hsd->Write_DMADblBuf0CpltCallback(hsd);
01774 #else
01775         HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd);
01776 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01777       }
01778       else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
01779       {
01780 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01781         hsd->Read_DMADblBuf0CpltCallback(hsd);
01782 #else
01783         HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd);
01784 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
01785       }
01786     }
01787   }
01788   else
01789   {
01790     /* Nothing to do */
01791   }
01792 }
01793
01794 /**
01795   * @brief return the SD state
01796   * @param hsd: Pointer to sd handle
01797   * @retval HAL state
01798   */
01799 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
01800 {
01801   return hsd->State;
01802 }
01803
01804 /**
01805 * @brief  Return the SD error code
01806 * @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
01807   *              the configuration information.
01808 * @retval SD Error Code
01809 */
01810 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
01811 {
01812   return hsd->ErrorCode;
01813 }
01814
01815 /**
01816   * @brief Tx Transfer completed callbacks
01817   * @param hsd: Pointer to SD handle
01818   * @retval None
01819   */
01820 __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
01821 {
01822   /* Prevent unused argument(s) compilation warning */
01823   UNUSED(hsd);
01824
01825   /* NOTE : This function should not be modified, when the callback is needed,
01826             the HAL_SD_TxCpltCallback can be implemented in the user file
01827    */
01828 }
01829
01830 /**
01831   * @brief Rx Transfer completed callbacks
01832   * @param hsd: Pointer SD handle
01833   * @retval None
01834   */
01835 __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
01836 {
01837   /* Prevent unused argument(s) compilation warning */
01838   UNUSED(hsd);
01839
01840   /* NOTE : This function should not be modified, when the callback is needed,
01841             the HAL_SD_RxCpltCallback can be implemented in the user file
01842    */
01843 }
01844
01845 /**
01846   * @brief SD error callbacks
01847   * @param hsd: Pointer SD handle
01848   * @retval None
01849   */
01850 __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
01851 {
01852   /* Prevent unused argument(s) compilation warning */
01853   UNUSED(hsd);
01854
01855   /* NOTE : This function should not be modified, when the callback is needed,
01856             the HAL_SD_ErrorCallback can be implemented in the user file
01857    */
01858 }
01859
01860 /**
01861   * @brief SD Abort callbacks
01862   * @param hsd: Pointer SD handle
01863   * @retval None
01864   */
01865 __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
01866 {
01867   /* Prevent unused argument(s) compilation warning */
01868   UNUSED(hsd);
01869
01870   /* NOTE : This function should not be modified, when the callback is needed,
01871             the HAL_SD_AbortCallback can be implemented in the user file
01872    */
01873 }
01874
01875 #if (USE_SD_TRANSCEIVER != 0U)
01876 /**
01877   * @brief  Enable/Disable the SD Transceiver 1.8V Mode Callback.
01878   * @param  status: Voltage Switch State
01879   * @retval None
01880   */
01881 __weak  void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
01882 {
01883   /* Prevent unused argument(s) compilation warning */
01884   UNUSED(status);
01885   /* NOTE : This function should not be modified, when the callback is needed,
01886             the HAL_SD_EnableTransceiver could be implemented in the user file
01887    */
01888 }
01889 #endif /* USE_SD_TRANSCEIVER  */
01890
01891 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
01892 /**
01893   * @brief  Register a User SD Callback
01894   *         To be used instead of the weak (surcharged) predefined callback
01895   * @param hsd : SD handle
01896   * @param CallbackID : ID of the callback to be registered
01897   *        This parameter can be one of the following values:
01898   *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
01899   *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
01900   *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
01901   *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
01902   *          @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  SD DMA Rx Double buffer 0 Callback ID
01903   *          @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  SD DMA Rx Double buffer 1 Callback ID
01904   *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
01905   *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
01906   *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
01907   *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
01908   * @param pCallback : pointer to the Callback function
01909   * @retval status
01910   */
01911 HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
01912 {
01913   HAL_StatusTypeDef status = HAL_OK;
01914
01915   if(pCallback == NULL)
01916   {
01917     /* Update the error code */
01918     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
01919     return HAL_ERROR;
01920   }
01921
01922   /* Process locked */
01923   __HAL_LOCK(hsd);
01924
01925   if(hsd->State == HAL_SD_STATE_READY)
01926   {
01927     switch (CallbackID)
01928     {
01929     case HAL_SD_TX_CPLT_CB_ID :
01930       hsd->TxCpltCallback = pCallback;
01931       break;
01932     case HAL_SD_RX_CPLT_CB_ID :
01933       hsd->RxCpltCallback = pCallback;
01934       break;
01935     case HAL_SD_ERROR_CB_ID :
01936       hsd->ErrorCallback = pCallback;
01937       break;
01938     case HAL_SD_ABORT_CB_ID :
01939       hsd->AbortCpltCallback = pCallback;
01940       break;
01941     case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
01942       hsd->Read_DMADblBuf0CpltCallback = pCallback;
01943       break;
01944     case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
01945       hsd->Read_DMADblBuf1CpltCallback = pCallback;
01946       break;
01947     case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
01948       hsd->Write_DMADblBuf0CpltCallback = pCallback;
01949       break;
01950     case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
01951       hsd->Write_DMADblBuf1CpltCallback = pCallback;
01952       break;
01953     case HAL_SD_MSP_INIT_CB_ID :
01954       hsd->MspInitCallback = pCallback;
01955       break;
01956     case HAL_SD_MSP_DEINIT_CB_ID :
01957       hsd->MspDeInitCallback = pCallback;
01958       break;
01959     default :
01960       /* Update the error code */
01961       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
01962       /* update return status */
01963       status =  HAL_ERROR;
01964       break;
01965     }
01966   }
01967   else if (hsd->State == HAL_SD_STATE_RESET)
01968   {
01969     switch (CallbackID)
01970     {
01971     case HAL_SD_MSP_INIT_CB_ID :
01972       hsd->MspInitCallback = pCallback;
01973       break;
01974     case HAL_SD_MSP_DEINIT_CB_ID :
01975       hsd->MspDeInitCallback = pCallback;
01976       break;
01977     default :
01978       /* Update the error code */
01979       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
01980       /* update return status */
01981       status =  HAL_ERROR;
01982       break;
01983     }
01984   }
01985   else
01986   {
01987     /* Update the error code */
01988     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
01989     /* update return status */
01990     status =  HAL_ERROR;
01991   }
01992
01993   /* Release Lock */
01994   __HAL_UNLOCK(hsd);
01995   return status;
01996 }
01997
01998 /**
01999   * @brief  Unregister a User SD Callback
02000   *         SD Callback is redirected to the weak (surcharged) predefined callback
02001   * @param hsd : SD handle
02002   * @param CallbackID : ID of the callback to be unregistered
02003   *        This parameter can be one of the following values:
02004   *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
02005   *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
02006   *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
02007   *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
02008   *          @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  SD DMA Rx Double buffer 0 Callback ID
02009   *          @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  SD DMA Rx Double buffer 1 Callback ID
02010   *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
02011   *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
02012   *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
02013   *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
02014   * @retval status
02015   */
02016 HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
02017 {
02018   HAL_StatusTypeDef status = HAL_OK;
02019
02020   /* Process locked */
02021   __HAL_LOCK(hsd);
02022
02023   if(hsd->State == HAL_SD_STATE_READY)
02024   {
02025     switch (CallbackID)
02026     {
02027     case HAL_SD_TX_CPLT_CB_ID :
02028       hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
02029       break;
02030     case HAL_SD_RX_CPLT_CB_ID :
02031       hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
02032       break;
02033     case HAL_SD_ERROR_CB_ID :
02034       hsd->ErrorCallback = HAL_SD_ErrorCallback;
02035       break;
02036     case HAL_SD_ABORT_CB_ID :
02037       hsd->AbortCpltCallback = HAL_SD_AbortCallback;
02038       break;
02039     case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
02040       hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback;
02041       break;
02042     case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
02043       hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback;
02044       break;
02045     case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
02046       hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback;
02047       break;
02048     case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
02049       hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback;
02050       break;
02051     case HAL_SD_MSP_INIT_CB_ID :
02052       hsd->MspInitCallback = HAL_SD_MspInit;
02053       break;
02054     case HAL_SD_MSP_DEINIT_CB_ID :
02055       hsd->MspDeInitCallback = HAL_SD_MspDeInit;
02056       break;
02057     default :
02058       /* Update the error code */
02059       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02060       /* update return status */
02061       status =  HAL_ERROR;
02062       break;
02063     }
02064   }
02065   else if (hsd->State == HAL_SD_STATE_RESET)
02066   {
02067     switch (CallbackID)
02068     {
02069     case HAL_SD_MSP_INIT_CB_ID :
02070       hsd->MspInitCallback = HAL_SD_MspInit;
02071       break;
02072     case HAL_SD_MSP_DEINIT_CB_ID :
02073       hsd->MspDeInitCallback = HAL_SD_MspDeInit;
02074       break;
02075     default :
02076       /* Update the error code */
02077       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02078       /* update return status */
02079       status =  HAL_ERROR;
02080       break;
02081     }
02082   }
02083   else
02084   {
02085     /* Update the error code */
02086     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02087     /* update return status */
02088     status =  HAL_ERROR;
02089   }
02090
02091   /* Release Lock */
02092   __HAL_UNLOCK(hsd);
02093   return status;
02094 }
02095
02096 #if (USE_SD_TRANSCEIVER != 0U)
02097 /**
02098   * @brief  Register a User SD Transceiver Callback
02099   *         To be used instead of the weak (surcharged) predefined callback
02100   * @param hsd : SD handle
02101   * @param pCallback : pointer to the Callback function
02102   * @retval status
02103   */
02104 HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
02105 {
02106   HAL_StatusTypeDef status = HAL_OK;
02107
02108   if(pCallback == NULL)
02109   {
02110     /* Update the error code */
02111     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02112     return HAL_ERROR;
02113   }
02114
02115   /* Process locked */
02116   __HAL_LOCK(hsd);
02117
02118   if(hsd->State == HAL_SD_STATE_READY)
02119   {
02120     hsd->DriveTransceiver_1_8V_Callback = pCallback;
02121   }
02122   else
02123   {
02124     /* Update the error code */
02125     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02126     /* update return status */
02127     status =  HAL_ERROR;
02128   }
02129
02130   /* Release Lock */
02131   __HAL_UNLOCK(hsd);
02132   return status;
02133 }
02134
02135 /**
02136   * @brief  Unregister a User SD Transceiver Callback
02137   *         SD Callback is redirected to the weak (surcharged) predefined callback
02138   * @param hsd : SD handle
02139   * @retval status
02140   */
02141 HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
02142 {
02143   HAL_StatusTypeDef status = HAL_OK;
02144
02145   /* Process locked */
02146   __HAL_LOCK(hsd);
02147
02148   if(hsd->State == HAL_SD_STATE_READY)
02149   {
02150     hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
02151   }
02152   else
02153   {
02154     /* Update the error code */
02155     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
02156     /* update return status */
02157     status =  HAL_ERROR;
02158   }
02159
02160   /* Release Lock */
02161   __HAL_UNLOCK(hsd);
02162   return status;
02163 }
02164 #endif /* USE_SD_TRANSCEIVER */
02165 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
02166
02167 /**
02168   * @}
02169   */
02170
02171 /** @addtogroup SD_Exported_Functions_Group3
02172  *  @brief   management functions
02173  *
02174 @verbatim
02175   ==============================================================================
02176                       ##### Peripheral Control functions #####
02177   ==============================================================================
02178   [..]
02179     This subsection provides a set of functions allowing to control the SD card
02180     operations and get the related information
02181
02182 @endverbatim
02183   * @{
02184   */
02185
02186 /**
02187   * @brief  Returns information the information of the card which are stored on
02188   *         the CID register.
02189   * @param  hsd: Pointer to SD handle
02190   * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
02191   *         contains all CID register parameters
02192   * @retval HAL status
02193   */
02194 HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
02195 {
02196   pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
02197
02198   pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
02199
02200   pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
02201
02202   pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
02203
02204   pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
02205
02206   pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
02207
02208   pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
02209
02210   pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
02211
02212   pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
02213
02214   pCID->Reserved2 = 1U;
02215
02216   return HAL_OK;
02217 }
02218
02219 /**
02220   * @brief  Returns information the information of the card which are stored on
02221   *         the CSD register.
02222   * @param  hsd: Pointer to SD handle
02223   * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
02224   *         contains all CSD register parameters
02225   * @retval HAL status
02226   */
02227 HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
02228 {
02229   pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
02230
02231   pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
02232
02233   pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
02234
02235   pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
02236
02237   pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
02238
02239   pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
02240
02241   pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
02242
02243   pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
02244
02245   pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
02246
02247   pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
02248
02249   pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
02250
02251   pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
02252
02253   pCSD->Reserved2 = 0U; /*!< Reserved */
02254
02255   if(hsd->SdCard.CardType == CARD_SDSC)
02256   {
02257     pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
02258
02259     pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
02260
02261     pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
02262
02263     pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
02264
02265     pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
02266
02267     pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
02268
02269     hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
02270     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
02271     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
02272
02273     hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
02274     hsd->SdCard.LogBlockSize = 512U;
02275   }
02276   else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
02277   {
02278     /* Byte 7 */
02279     pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
02280
02281     hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
02282     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
02283     hsd->SdCard.BlockSize = 512U;
02284     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
02285   }
02286   else
02287   {
02288     /* Clear all the static flags */
02289     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02290     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02291     hsd->State = HAL_SD_STATE_READY;
02292     return HAL_ERROR;
02293   }
02294
02295   pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
02296
02297   pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
02298
02299   pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
02300
02301   pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
02302
02303   pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
02304
02305   pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
02306
02307   pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
02308
02309   pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
02310
02311   pCSD->Reserved3 = 0;
02312
02313   pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
02314
02315   pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
02316
02317   pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
02318
02319   pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
02320
02321   pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
02322
02323   pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
02324
02325   pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
02326
02327   pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
02328
02329   pCSD->Reserved4 = 1;
02330
02331   return HAL_OK;
02332 }
02333
02334 /**
02335   * @brief  Gets the SD status info.
02336   * @param  hsd: Pointer to SD handle
02337   * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
02338   *         will contain the SD card status information
02339   * @retval HAL status
02340   */
02341 HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
02342 {
02343   uint32_t sd_status[16];
02344   uint32_t errorstate;
02345
02346   errorstate = SD_SendSDStatus(hsd, sd_status);
02347   if(errorstate != HAL_SD_ERROR_NONE)
02348   {
02349     /* Clear all the static flags */
02350     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02351     hsd->ErrorCode |= errorstate;
02352     hsd->State = HAL_SD_STATE_READY;
02353     return HAL_ERROR;
02354   }
02355   else
02356   {
02357     pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
02358
02359     pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
02360
02361     pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
02362
02363     pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
02364                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
02365
02366     pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
02367
02368     pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
02369
02370     pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
02371
02372     pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
02373
02374     pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
02375
02376     pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
02377
02378     pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
02379     pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
02380     pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
02381   }
02382
02383   return HAL_OK;
02384 }
02385
02386 /**
02387   * @brief  Gets the SD card info.
02388   * @param  hsd: Pointer to SD handle
02389   * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
02390   *         will contain the SD card status information
02391   * @retval HAL status
02392   */
02393 HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
02394 {
02395   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
02396   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
02397   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
02398   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
02399   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
02400   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
02401   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
02402   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
02403
02404   return HAL_OK;
02405 }
02406
02407 /**
02408   * @brief  Enables wide bus operation for the requested card if supported by
02409   *         card.
02410   * @param  hsd: Pointer to SD handle
02411   * @param  WideMode: Specifies the SD card wide bus mode
02412   *          This parameter can be one of the following values:
02413   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
02414   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
02415   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
02416   * @retval HAL status
02417   */
02418 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
02419 {
02420   SDMMC_InitTypeDef Init;
02421   uint32_t errorstate;
02422
02423   /* Check the parameters */
02424   assert_param(IS_SDMMC_BUS_WIDE(WideMode));
02425
02426   /* Change State */
02427   hsd->State = HAL_SD_STATE_BUSY;
02428
02429   if(hsd->SdCard.CardType != CARD_SECURED)
02430   {
02431     if(WideMode == SDMMC_BUS_WIDE_8B)
02432     {
02433       hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02434     }
02435     else if(WideMode == SDMMC_BUS_WIDE_4B)
02436     {
02437       errorstate = SD_WideBus_Enable(hsd);
02438
02439       hsd->ErrorCode |= errorstate;
02440     }
02441     else if(WideMode == SDMMC_BUS_WIDE_1B)
02442     {
02443       errorstate = SD_WideBus_Disable(hsd);
02444
02445       hsd->ErrorCode |= errorstate;
02446     }
02447     else
02448     {
02449       /* WideMode is not a valid argument*/
02450       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
02451     }
02452   }
02453   else
02454   {
02455     /* MMC Card does not support this feature */
02456     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02457   }
02458
02459   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02460   {
02461     /* Clear all the static flags */
02462     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02463     hsd->State = HAL_SD_STATE_READY;
02464     return HAL_ERROR;
02465   }
02466   else
02467   {
02468     /* Configure the SDMMC peripheral */
02469     Init.ClockEdge           = hsd->Init.ClockEdge;
02470     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
02471     Init.BusWide             = WideMode;
02472     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
02473
02474     /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
02475     if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
02476     {
02477       Init.ClockDiv = hsd->Init.ClockDiv;
02478     }
02479     else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
02480     {
02481       /* UltraHigh speed SD card,user Clock div */
02482       Init.ClockDiv = hsd->Init.ClockDiv;
02483     }
02484     else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
02485     {
02486       /* High speed SD card, Max Frequency = 50Mhz */
02487       Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
02488     }
02489     else
02490     {
02491       /* No High speed SD card, Max Frequency = 25Mhz */
02492       Init.ClockDiv = SDMMC_NSpeed_CLK_DIV;
02493     }
02494
02495     (void)SDMMC_Init(hsd->Instance, Init);
02496   }
02497
02498   /* Change State */
02499   hsd->State = HAL_SD_STATE_READY;
02500
02501   return HAL_OK;
02502 }
02503
02504 /**
02505   * @brief  Configure the speed bus mode
02506   * @param  hsd: Pointer to the SD handle
02507   * @param  SpeedMode: Specifies the SD card speed bus mode
02508   *          This parameter can be one of the following values:
02509   *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
02510   *            @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode
02511   *            @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode
02512   *            @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode
02513   * @retval HAL status
02514   */
02515
02516 HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
02517 {
02518   uint32_t tickstart;
02519   HAL_StatusTypeDef status = HAL_OK;
02520
02521   /* Check the parameters */
02522   assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
02523   /* Change State */
02524   hsd->State = HAL_SD_STATE_BUSY;
02525
02526 #if (USE_SD_TRANSCEIVER != 0U)
02527   if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
02528   {
02529     switch (SpeedMode)
02530     {
02531     case SDMMC_SPEED_MODE_AUTO:
02532       {
02533         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02534             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02535         {
02536           hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
02537           /* Enable Ultra High Speed */
02538           if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
02539           {
02540             if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02541             {
02542               hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02543               status = HAL_ERROR;
02544             }
02545           }
02546         }
02547         else if (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED)
02548         {
02549           /* Enable High Speed */
02550           if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02551           {
02552             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02553             status = HAL_ERROR;
02554           }
02555         }
02556         else
02557         {
02558           /*Nothing to do, Use defaultSpeed */
02559         }
02560         break;
02561       }
02562     case SDMMC_SPEED_MODE_ULTRA:
02563       {
02564         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02565             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02566         {
02567           /* Enable UltraHigh Speed */
02568           if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
02569           {
02570             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02571             status = HAL_ERROR;
02572           }
02573           hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
02574         }
02575         else
02576         {
02577           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02578           status = HAL_ERROR;
02579         }
02580         break;
02581       }
02582     case SDMMC_SPEED_MODE_DDR:
02583       {
02584         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02585             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02586         {
02587           /* Enable DDR Mode*/
02588           if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
02589           {
02590             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02591             status = HAL_ERROR;
02592           }
02593           hsd->Instance->CLKCR |=  SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR;
02594         }
02595         else
02596         {
02597           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02598           status = HAL_ERROR;
02599         }
02600         break;
02601       }
02602     case SDMMC_SPEED_MODE_HIGH:
02603       {
02604         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02605             (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
02606               (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02607         {
02608           /* Enable High Speed */
02609           if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02610           {
02611             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02612             status = HAL_ERROR;
02613           }
02614         }
02615         else
02616         {
02617           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02618           status = HAL_ERROR;
02619         }
02620         break;
02621       }
02622     case SDMMC_SPEED_MODE_DEFAULT:
02623       break;
02624     default:
02625       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
02626       status = HAL_ERROR;
02627       break;
02628     }
02629   }
02630   else
02631   {
02632     switch (SpeedMode)
02633     {
02634     case SDMMC_SPEED_MODE_AUTO:
02635       {
02636         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02637             (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
02638               (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02639         {
02640           /* Enable High Speed */
02641           if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02642           {
02643             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02644             status = HAL_ERROR;
02645           }
02646         }
02647         else
02648         {
02649           /*Nothing to do, Use defaultSpeed */
02650         }
02651         break;
02652       }
02653     case SDMMC_SPEED_MODE_HIGH:
02654       {
02655         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02656             (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
02657               (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02658         {
02659           /* Enable High Speed */
02660           if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02661           {
02662             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02663             status = HAL_ERROR;
02664           }
02665         }
02666         else
02667         {
02668           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02669           status = HAL_ERROR;
02670         }
02671         break;
02672       }
02673     case SDMMC_SPEED_MODE_DEFAULT:
02674       break;
02675     case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
02676     default:
02677       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
02678       status = HAL_ERROR;
02679       break;
02680     }
02681   }
02682 #else
02683   switch (SpeedMode)
02684   {
02685   case SDMMC_SPEED_MODE_AUTO:
02686     {
02687       if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02688           (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
02689             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02690       {
02691         /* Enable High Speed */
02692         if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02693         {
02694           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02695           status = HAL_ERROR;
02696         }
02697       }
02698       else
02699       {
02700         /*Nothing to do, Use defaultSpeed */
02701       }
02702       break;
02703     }
02704   case SDMMC_SPEED_MODE_HIGH:
02705     {
02706       if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
02707           (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
02708             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
02709       {
02710         /* Enable High Speed */
02711         if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
02712         {
02713           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02714           status = HAL_ERROR;
02715         }
02716       }
02717       else
02718       {
02719         hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02720         status = HAL_ERROR;
02721       }
02722       break;
02723     }
02724   case SDMMC_SPEED_MODE_DEFAULT:
02725     break;
02726   case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
02727   default:
02728     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
02729     status = HAL_ERROR;
02730     break;
02731   }
02732 #endif /* USE_SD_TRANSCEIVER */
02733
02734   /* Verify that SD card is ready to use after Speed mode switch*/
02735   tickstart = HAL_GetTick();
02736   while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
02737   {
02738     if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02739     {
02740       hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
02741       hsd->State = HAL_SD_STATE_READY;
02742       return HAL_TIMEOUT;
02743     }
02744   }
02745
02746   /* Change State */
02747   hsd->State = HAL_SD_STATE_READY;
02748   return status;
02749 }
02750
02751 /**
02752   * @brief  Gets the current sd card data state.
02753   * @param  hsd: pointer to SD handle
02754   * @retval Card state
02755   */
02756 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
02757 {
02758   uint32_t cardstate;
02759   uint32_t errorstate;
02760   uint32_t resp1 = 0;
02761
02762   errorstate = SD_SendStatus(hsd, &resp1);
02763   if(errorstate != HAL_SD_ERROR_NONE)
02764   {
02765     hsd->ErrorCode |= errorstate;
02766   }
02767
02768   cardstate = ((resp1 >> 9U) & 0x0FU);
02769
02770   return (HAL_SD_CardStateTypeDef)cardstate;
02771 }
02772
02773 /**
02774   * @brief  Abort the current transfer and disable the SD.
02775   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02776   *                the configuration information for SD module.
02777   * @retval HAL status
02778   */
02779 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
02780 {
02781   HAL_SD_CardStateTypeDef CardState;
02782
02783   /* DIsable All interrupts */
02784   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02785                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02786
02787   /* Clear All flags */
02788   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
02789
02790   /* If IDMA Context, disable Internal DMA */
02791   hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
02792
02793   hsd->State = HAL_SD_STATE_READY;
02794
02795   /* Initialize the SD operation */
02796   hsd->Context = SD_CONTEXT_NONE;
02797
02798   CardState = HAL_SD_GetCardState(hsd);
02799   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02800   {
02801     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02802   }
02803   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02804   {
02805     return HAL_ERROR;
02806   }
02807   return HAL_OK;
02808 }
02809
02810 /**
02811   * @brief  Abort the current transfer and disable the SD (IT mode).
02812   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02813   *                the configuration information for SD module.
02814   * @retval HAL status
02815   */
02816 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
02817 {
02818   HAL_SD_CardStateTypeDef CardState;
02819
02820   /* Disable All interrupts */
02821   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02822                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02823
02824   /* If IDMA Context, disable Internal DMA */
02825   hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
02826
02827   /* Clear All flags */
02828   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
02829
02830   CardState = HAL_SD_GetCardState(hsd);
02831   hsd->State = HAL_SD_STATE_READY;
02832
02833   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02834   {
02835     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02836   }
02837
02838   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02839   {
02840     return HAL_ERROR;
02841   }
02842   else
02843   {
02844 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
02845     hsd->AbortCpltCallback(hsd);
02846 #else
02847     HAL_SD_AbortCallback(hsd);
02848 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
02849   }
02850
02851   return HAL_OK;
02852 }
02853
02854 /**
02855   * @}
02856   */
02857
02858 /**
02859   * @}
02860   */
02861
02862 /* Private function ----------------------------------------------------------*/
02863 /** @addtogroup SD_Private_Functions
02864   * @{
02865   */
02866
02867
02868 /**
02869   * @brief  Initializes the sd card.
02870   * @param  hsd: Pointer to SD handle
02871   * @retval SD Card error state
02872   */
02873 static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
02874 {
02875   HAL_SD_CardCSDTypeDef CSD;
02876   uint32_t errorstate;
02877   uint16_t sd_rca = 1U;
02878
02879   /* Check the power State */
02880   if(SDMMC_GetPowerState(hsd->Instance) == 0U)
02881   {
02882     /* Power off */
02883     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02884   }
02885
02886   if(hsd->SdCard.CardType != CARD_SECURED)
02887   {
02888     /* Send CMD2 ALL_SEND_CID */
02889     errorstate = SDMMC_CmdSendCID(hsd->Instance);
02890     if(errorstate != HAL_SD_ERROR_NONE)
02891     {
02892       return errorstate;
02893     }
02894     else
02895     {
02896       /* Get Card identification number data */
02897       hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02898       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02899       hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02900       hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02901     }
02902   }
02903
02904   if(hsd->SdCard.CardType != CARD_SECURED)
02905   {
02906     /* Send CMD3 SET_REL_ADDR with argument 0 */
02907     /* SD Card publishes its RCA. */
02908     errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
02909     if(errorstate != HAL_SD_ERROR_NONE)
02910     {
02911       return errorstate;
02912     }
02913   }
02914   if(hsd->SdCard.CardType != CARD_SECURED)
02915   {
02916     /* Get the SD card RCA */
02917     hsd->SdCard.RelCardAdd = sd_rca;
02918
02919     /* Send CMD9 SEND_CSD with argument as card's RCA */
02920     errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02921     if(errorstate != HAL_SD_ERROR_NONE)
02922     {
02923       return errorstate;
02924     }
02925     else
02926     {
02927       /* Get Card Specific Data */
02928       hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02929       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02930       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02931       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02932     }
02933   }
02934
02935   /* Get the Card Class */
02936   hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
02937
02938   /* Get CSD parameters */
02939   if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
02940   {
02941     return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02942   }
02943
02944   /* Select the Card */
02945   errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
02946   if(errorstate != HAL_SD_ERROR_NONE)
02947   {
02948     return errorstate;
02949   }
02950
02951   /* All cards are initialized */
02952   return HAL_SD_ERROR_NONE;
02953 }
02954
02955 /**
02956   * @brief  Enquires cards about their operating voltage and configures clock
02957   *         controls and stores SD information that will be needed in future
02958   *         in the SD handle.
02959   * @param  hsd: Pointer to SD handle
02960   * @retval error state
02961   */
02962 static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
02963 {
02964   __IO uint32_t count = 0U;
02965   uint32_t response = 0U, validvoltage = 0U;
02966   uint32_t errorstate;
02967 #if (USE_SD_TRANSCEIVER != 0U)
02968   uint32_t tickstart = HAL_GetTick();
02969 #endif /* USE_SD_TRANSCEIVER  */
02970
02971   /* CMD0: GO_IDLE_STATE */
02972   errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
02973   if(errorstate != HAL_SD_ERROR_NONE)
02974   {
02975     return errorstate;
02976   }
02977
02978   /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
02979   errorstate = SDMMC_CmdOperCond(hsd->Instance);
02980   if(errorstate != HAL_SD_ERROR_NONE)
02981   {
02982     hsd->SdCard.CardVersion = CARD_V1_X;
02983     /* CMD0: GO_IDLE_STATE */
02984     errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
02985     if(errorstate != HAL_SD_ERROR_NONE)
02986     {
02987       return errorstate;
02988     }
02989
02990   }
02991   else
02992   {
02993     hsd->SdCard.CardVersion = CARD_V2_X;
02994   }
02995
02996   if( hsd->SdCard.CardVersion == CARD_V2_X)
02997   {
02998     /* SEND CMD55 APP_CMD with RCA as 0 */
02999     errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
03000     if(errorstate != HAL_SD_ERROR_NONE)
03001     {
03002       return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
03003     }
03004   }
03005   /* SD CARD */
03006   /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
03007   while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
03008   {
03009     /* SEND CMD55 APP_CMD with RCA as 0 */
03010     errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
03011     if(errorstate != HAL_SD_ERROR_NONE)
03012     {
03013       return errorstate;
03014     }
03015
03016     /* Send CMD41 */
03017     errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
03018     if(errorstate != HAL_SD_ERROR_NONE)
03019     {
03020       return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
03021     }
03022
03023     /* Get command response */
03024     response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
03025
03026     /* Get operating voltage*/
03027     validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
03028
03029     count++;
03030   }
03031
03032   if(count >= SDMMC_MAX_VOLT_TRIAL)
03033   {
03034     return HAL_SD_ERROR_INVALID_VOLTRANGE;
03035   }
03036
03037   if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
03038   {
03039     hsd->SdCard.CardType = CARD_SDHC_SDXC;
03040 #if (USE_SD_TRANSCEIVER != 0U)
03041     if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
03042     {
03043       if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
03044       {
03045         hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
03046
03047         /* Start switching procedue */
03048         hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
03049
03050         /* Send CMD11 to switch 1.8V mode */
03051         errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
03052         if(errorstate != HAL_SD_ERROR_NONE)
03053         {
03054           return errorstate;
03055         }
03056
03057         /* Check to CKSTOP */
03058         while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
03059         {
03060           if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
03061           {
03062             return HAL_SD_ERROR_TIMEOUT;
03063           }
03064         }
03065
03066         /* Clear CKSTOP Flag */
03067         hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
03068
03069         /* Check to BusyD0 */
03070         if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
03071         {
03072           /* Error when activate Voltage Switch in SDMMC Peripheral */
03073           return SDMMC_ERROR_UNSUPPORTED_FEATURE;
03074         }
03075         else
03076         {
03077           /* Enable Transceiver Switch PIN */
03078 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
03079           hsd->DriveTransceiver_1_8V_Callback(SET);
03080 #else
03081           HAL_SD_DriveTransceiver_1_8V_Callback(SET);
03082 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
03083
03084           /* Switch ready */
03085           hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
03086
03087           /* Check VSWEND Flag */
03088           while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
03089           {
03090             if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
03091             {
03092               return HAL_SD_ERROR_TIMEOUT;
03093             }
03094           }
03095
03096           /* Clear VSWEND Flag */
03097           hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
03098
03099           /* Check BusyD0 status */
03100           if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
03101           {
03102             /* Error when enabling 1.8V mode */
03103             return HAL_SD_ERROR_INVALID_VOLTRANGE;
03104           }
03105           /* Switch to 1.8V OK */
03106
03107           /* Disable VSWITCH FLAG from SDMMC Peripheral */
03108           hsd->Instance->POWER = 0x13U;
03109
03110           /* Clean Status flags */
03111           hsd->Instance->ICR = 0xFFFFFFFFU;
03112         }
03113
03114         hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
03115       }
03116     }
03117 #endif /* USE_SD_TRANSCEIVER  */
03118   }
03119
03120   return HAL_SD_ERROR_NONE;
03121 }
03122
03123 /**
03124   * @brief  Turns the SDMMC output signals off.
03125   * @param  hsd: Pointer to SD handle
03126   * @retval None
03127   */
03128 static void SD_PowerOFF(SD_HandleTypeDef *hsd)
03129 {
03130   /* Set Power State to OFF */
03131   (void)SDMMC_PowerState_OFF(hsd->Instance);
03132 }
03133
03134 /**
03135   * @brief  Send Status info command.
03136   * @param  hsd: pointer to SD handle
03137   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
03138   *         SD Status register)
03139   * @retval error state
03140   */
03141 static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
03142 {
03143   SDMMC_DataInitTypeDef config;
03144   uint32_t errorstate;
03145   uint32_t tickstart = HAL_GetTick();
03146   uint32_t count;
03147   uint32_t *pData = pSDstatus;
03148
03149   /* Check SD response */
03150   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
03151   {
03152     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
03153   }
03154
03155   /* Set block size for card if it is not equal to current block size for card */
03156   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
03157   if(errorstate != HAL_SD_ERROR_NONE)
03158   {
03159     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
03160     return errorstate;
03161   }
03162
03163   /* Send CMD55 */
03164   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
03165   if(errorstate != HAL_SD_ERROR_NONE)
03166   {
03167     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
03168     return errorstate;
03169   }
03170
03171   /* Configure the SD DPSM (Data Path State Machine) */
03172   config.DataTimeOut   = SDMMC_DATATIMEOUT;
03173   config.DataLength    = 64U;
03174   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
03175   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03176   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03177   config.DPSM          = SDMMC_DPSM_ENABLE;
03178   (void)SDMMC_ConfigData(hsd->Instance, &config);
03179
03180   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
03181   errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
03182   if(errorstate != HAL_SD_ERROR_NONE)
03183   {
03184     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
03185     return errorstate;
03186   }
03187
03188   /* Get status data */
03189   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
03190   {
03191     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
03192     {
03193       for(count = 0U; count < 8U; count++)
03194       {
03195         *pData = SDMMC_ReadFIFO(hsd->Instance);
03196         pData++;
03197       }
03198     }
03199
03200     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
03201     {
03202       return HAL_SD_ERROR_TIMEOUT;
03203     }
03204   }
03205
03206   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03207   {
03208     return HAL_SD_ERROR_DATA_TIMEOUT;
03209   }
03210   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03211   {
03212     return HAL_SD_ERROR_DATA_CRC_FAIL;
03213   }
03214   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03215   {
03216     return HAL_SD_ERROR_RX_OVERRUN;
03217   }
03218   else
03219   {
03220     /* Nothing to do */
03221   }
03222
03223   while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
03224   {
03225     *pData = SDMMC_ReadFIFO(hsd->Instance);
03226     pData++;
03227
03228     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
03229     {
03230       return HAL_SD_ERROR_TIMEOUT;
03231     }
03232   }
03233
03234   /* Clear all the static status flags*/
03235   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
03236
03237   return HAL_SD_ERROR_NONE;
03238 }
03239
03240 /**
03241   * @brief  Returns the current card's status.
03242   * @param  hsd: Pointer to SD handle
03243   * @param  pCardStatus: pointer to the buffer that will contain the SD card
03244   *         status (Card Status register)
03245   * @retval error state
03246   */
03247 static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
03248 {
03249   uint32_t errorstate;
03250
03251   if(pCardStatus == NULL)
03252   {
03253     return HAL_SD_ERROR_PARAM;
03254   }
03255
03256   /* Send Status command */
03257   errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
03258   if(errorstate != HAL_SD_ERROR_NONE)
03259   {
03260     return errorstate;
03261   }
03262
03263   /* Get SD card status */
03264   *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
03265
03266   return HAL_SD_ERROR_NONE;
03267 }
03268
03269 /**
03270   * @brief  Enables the SDMMC wide bus mode.
03271   * @param  hsd: pointer to SD handle
03272   * @retval error state
03273   */
03274 static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
03275 {
03276   uint32_t scr[2U] = {0UL, 0UL};
03277   uint32_t errorstate;
03278
03279   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
03280   {
03281     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
03282   }
03283
03284   /* Get SCR Register */
03285   errorstate = SD_FindSCR(hsd, scr);
03286   if(errorstate != HAL_SD_ERROR_NONE)
03287   {
03288     return errorstate;
03289   }
03290
03291   /* If requested card supports wide bus operation */
03292   if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
03293   {
03294     /* Send CMD55 APP_CMD with argument as card's RCA.*/
03295     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
03296     if(errorstate != HAL_SD_ERROR_NONE)
03297     {
03298       return errorstate;
03299     }
03300
03301     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
03302     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
03303     if(errorstate != HAL_SD_ERROR_NONE)
03304     {
03305       return errorstate;
03306     }
03307
03308     return HAL_SD_ERROR_NONE;
03309   }
03310   else
03311   {
03312     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
03313   }
03314 }
03315
03316 /**
03317   * @brief  Disables the SDMMC wide bus mode.
03318   * @param  hsd: Pointer to SD handle
03319   * @retval error state
03320   */
03321 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
03322 {
03323   uint32_t scr[2U] = {0UL, 0UL};
03324   uint32_t errorstate;
03325
03326   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
03327   {
03328     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
03329   }
03330
03331   /* Get SCR Register */
03332   errorstate = SD_FindSCR(hsd, scr);
03333   if(errorstate != HAL_SD_ERROR_NONE)
03334   {
03335     return errorstate;
03336   }
03337
03338   /* If requested card supports 1 bit mode operation */
03339   if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
03340   {
03341     /* Send CMD55 APP_CMD with argument as card's RCA */
03342     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
03343     if(errorstate != HAL_SD_ERROR_NONE)
03344     {
03345       return errorstate;
03346     }
03347
03348     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
03349     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
03350     if(errorstate != HAL_SD_ERROR_NONE)
03351     {
03352       return errorstate;
03353     }
03354
03355     return HAL_SD_ERROR_NONE;
03356   }
03357   else
03358   {
03359     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
03360   }
03361 }
03362
03363
03364 /**
03365   * @brief  Finds the SD card SCR register value.
03366   * @param  hsd: Pointer to SD handle
03367   * @param  pSCR: pointer to the buffer that will contain the SCR value
03368   * @retval error state
03369   */
03370 static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
03371 {
03372   SDMMC_DataInitTypeDef config;
03373   uint32_t errorstate;
03374   uint32_t tickstart = HAL_GetTick();
03375   uint32_t index = 0U;
03376   uint32_t tempscr[2U] = {0UL, 0UL};
03377   uint32_t *scr = pSCR;
03378
03379   /* Set Block Size To 8 Bytes */
03380   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
03381   if(errorstate != HAL_SD_ERROR_NONE)
03382   {
03383     return errorstate;
03384   }
03385
03386   /* Send CMD55 APP_CMD with argument as card's RCA */
03387   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
03388   if(errorstate != HAL_SD_ERROR_NONE)
03389   {
03390     return errorstate;
03391   }
03392
03393   config.DataTimeOut   = SDMMC_DATATIMEOUT;
03394   config.DataLength    = 8U;
03395   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
03396   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03397   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03398   config.DPSM          = SDMMC_DPSM_ENABLE;
03399   (void)SDMMC_ConfigData(hsd->Instance, &config);
03400
03401   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
03402   errorstate = SDMMC_CmdSendSCR(hsd->Instance);
03403   if(errorstate != HAL_SD_ERROR_NONE)
03404   {
03405     return errorstate;
03406   }
03407
03408   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
03409   {
03410     if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
03411     {
03412       tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
03413       tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
03414       index++;
03415     }
03416
03417
03418     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
03419     {
03420       return HAL_SD_ERROR_TIMEOUT;
03421     }
03422   }
03423
03424   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03425   {
03426     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03427
03428     return HAL_SD_ERROR_DATA_TIMEOUT;
03429   }
03430   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03431   {
03432     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03433
03434     return HAL_SD_ERROR_DATA_CRC_FAIL;
03435   }
03436   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03437   {
03438     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03439
03440     return HAL_SD_ERROR_RX_OVERRUN;
03441   }
03442   else
03443   {
03444     /* No error flag set */
03445     /* Clear all the static flags */
03446     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
03447
03448     *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
03449             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
03450     scr++;
03451     *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
03452             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
03453
03454   }
03455
03456   return HAL_SD_ERROR_NONE;
03457 }
03458
03459 /**
03460   * @brief  Wrap up reading in non-blocking mode.
03461   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
03462   *              the configuration information.
03463   * @retval None
03464   */
03465 static void SD_Read_IT(SD_HandleTypeDef *hsd)
03466 {
03467   uint32_t count, data;
03468   uint8_t* tmp;
03469
03470   tmp = hsd->pRxBuffPtr;
03471
03472   if (hsd->RxXferSize >= 32U)
03473   {
03474     /* Read data from SDMMC Rx FIFO */
03475     for(count = 0U; count < 8U; count++)
03476     {
03477       data = SDMMC_ReadFIFO(hsd->Instance);
03478       *tmp = (uint8_t)(data & 0xFFU);
03479       tmp++;
03480       *tmp = (uint8_t)((data >> 8U) & 0xFFU);
03481       tmp++;
03482       *tmp = (uint8_t)((data >> 16U) & 0xFFU);
03483       tmp++;
03484       *tmp = (uint8_t)((data >> 24U) & 0xFFU);
03485       tmp++;
03486     }
03487
03488     hsd->pRxBuffPtr = tmp;
03489     hsd->RxXferSize -= 32U;
03490   }
03491 }
03492
03493 /**
03494   * @brief  Wrap up writing in non-blocking mode.
03495   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
03496   *              the configuration information.
03497   * @retval None
03498   */
03499 static void SD_Write_IT(SD_HandleTypeDef *hsd)
03500 {
03501   uint32_t count, data;
03502   uint8_t* tmp;
03503
03504   tmp = hsd->pTxBuffPtr;
03505
03506   if (hsd->TxXferSize >= 32U)
03507   {
03508     /* Write data to SDMMC Tx FIFO */
03509     for(count = 0U; count < 8U; count++)
03510     {
03511       data = (uint32_t)(*tmp);
03512       tmp++;
03513       data |= ((uint32_t)(*tmp) << 8U);
03514       tmp++;
03515       data |= ((uint32_t)(*tmp) << 16U);
03516       tmp++;
03517       data |= ((uint32_t)(*tmp) << 24U);
03518       tmp++;
03519       (void)SDMMC_WriteFIFO(hsd->Instance, &data);
03520     }
03521
03522     hsd->pTxBuffPtr = tmp;
03523     hsd->TxXferSize -= 32U;
03524   }
03525 }
03526
03527 /**
03528   * @brief  Switches the SD card to High Speed mode.
03529   *         This API must be used after "Transfer State"
03530   * @note   This operation should be followed by the configuration
03531   *         of PLL to have SDMMCCK clock between 50 and 120 MHz
03532   * @param  hsd: SD handle
03533   * @retval SD Card error state
03534   */
03535 uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
03536 {
03537   uint32_t errorstate = HAL_SD_ERROR_NONE;
03538   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
03539   uint32_t SD_hs[16]  = {0};
03540   uint32_t count, loop = 0 ;
03541   uint32_t Timeout = HAL_GetTick();
03542
03543   if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
03544   {
03545      /* Standard Speed Card <= 12.5Mhz  */
03546      return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
03547   }
03548
03549   if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
03550   {
03551     /* Initialize the Data control register */
03552     hsd->Instance->DCTRL = 0;
03553     errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
03554
03555     if (errorstate != HAL_SD_ERROR_NONE)
03556     {
03557       return errorstate;
03558     }
03559
03560     /* Configure the SD DPSM (Data Path State Machine) */
03561     sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
03562     sdmmc_datainitstructure.DataLength    = 64;
03563     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
03564     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03565     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03566     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
03567
03568     if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
03569     {
03570       return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
03571     }
03572
03573
03574     errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
03575     if(errorstate != HAL_SD_ERROR_NONE)
03576     {
03577       return errorstate;
03578     }
03579
03580     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
03581     {
03582       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
03583       {
03584         for (count = 0U; count < 8U; count++)
03585         {
03586           SD_hs[(8U*loop)+count]  = SDMMC_ReadFIFO(hsd->Instance);
03587         }
03588         loop ++;
03589       }
03590
03591       if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
03592       {
03593         hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
03594         hsd->State= HAL_SD_STATE_READY;
03595         return HAL_SD_ERROR_TIMEOUT;
03596       }
03597     }
03598
03599     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03600     {
03601       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03602
03603       errorstate = 0;
03604
03605       return errorstate;
03606     }
03607     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03608     {
03609       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03610
03611       errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
03612
03613       return errorstate;
03614     }
03615     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03616     {
03617       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03618
03619       errorstate = SDMMC_ERROR_RX_OVERRUN;
03620
03621       return errorstate;
03622     }
03623     else
03624     {
03625       /* No error flag set */
03626     }
03627
03628     /* Clear all the static flags */
03629     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
03630
03631     /* Test if the switch mode HS is ok */
03632     if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
03633     {
03634       errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
03635     }
03636
03637   }
03638
03639   return errorstate;
03640 }
03641
03642 #if (USE_SD_TRANSCEIVER != 0U)
03643 /**
03644   * @brief  Switches the SD card to Ultra High Speed mode.
03645   *         This API must be used after "Transfer State"
03646   * @note   This operation should be followed by the configuration
03647   *         of PLL to have SDMMCCK clock between 50 and 120 MHz
03648   * @param  hsd: SD handle
03649   * @retval SD Card error state
03650   */
03651 static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
03652 {
03653   uint32_t errorstate = HAL_SD_ERROR_NONE;
03654   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
03655   uint32_t SD_hs[16]  = {0};
03656   uint32_t count, loop = 0 ;
03657   uint32_t Timeout = HAL_GetTick();
03658
03659   if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
03660   {
03661      /* Standard Speed Card <= 12.5Mhz  */
03662      return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
03663   }
03664
03665   if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
03666   {
03667     /* Initialize the Data control register */
03668     hsd->Instance->DCTRL = 0;
03669     errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
03670
03671     if (errorstate != HAL_SD_ERROR_NONE)
03672     {
03673       return errorstate;
03674     }
03675
03676     /* Configure the SD DPSM (Data Path State Machine) */
03677     sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
03678     sdmmc_datainitstructure.DataLength    = 64;
03679     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
03680     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03681     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03682     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
03683
03684     if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
03685     {
03686       return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
03687     }
03688
03689     errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
03690     if(errorstate != HAL_SD_ERROR_NONE)
03691     {
03692       return errorstate;
03693     }
03694
03695     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
03696     {
03697       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
03698       {
03699         for (count = 0U; count < 8U; count++)
03700         {
03701           SD_hs[(8U*loop)+count]  = SDMMC_ReadFIFO(hsd->Instance);
03702         }
03703         loop ++;
03704       }
03705
03706       if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
03707       {
03708         hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
03709         hsd->State= HAL_SD_STATE_READY;
03710         return HAL_SD_ERROR_TIMEOUT;
03711       }
03712     }
03713
03714     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03715     {
03716       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03717
03718       errorstate = 0;
03719
03720       return errorstate;
03721     }
03722     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03723     {
03724       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03725
03726       errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
03727
03728       return errorstate;
03729     }
03730     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03731     {
03732       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03733
03734       errorstate = SDMMC_ERROR_RX_OVERRUN;
03735
03736       return errorstate;
03737     }
03738     else
03739     {
03740       /* No error flag set */
03741     }
03742
03743     /* Clear all the static flags */
03744     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
03745
03746     /* Test if the switch mode HS is ok */
03747     if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
03748     {
03749       errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
03750     }
03751     else
03752     {
03753 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
03754       hsd->DriveTransceiver_1_8V_Callback(SET);
03755 #else
03756       HAL_SD_DriveTransceiver_1_8V_Callback(SET);
03757 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
03758 #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
03759       /* Enable DelayBlock Peripheral */
03760       /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
03761       MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
03762       if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
03763       {
03764         return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
03765       }
03766 #endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
03767     }
03768   }
03769
03770   return errorstate;
03771 }
03772
03773 /**
03774   * @brief  Switches the SD card to Double Data Rate (DDR) mode.
03775   *         This API must be used after "Transfer State"
03776   * @note   This operation should be followed by the configuration
03777   *         of PLL to have SDMMCCK clock less than 50MHz
03778   * @param  hsd: SD handle
03779   * @retval SD Card error state
03780   */
03781 static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
03782 {
03783   uint32_t errorstate = HAL_SD_ERROR_NONE;
03784   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
03785   uint32_t SD_hs[16]  = {0};
03786   uint32_t count, loop = 0 ;
03787   uint32_t Timeout = HAL_GetTick();
03788
03789   if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
03790   {
03791      /* Standard Speed Card <= 12.5Mhz  */
03792      return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
03793   }
03794
03795   if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
03796   {
03797     /* Initialize the Data control register */
03798     hsd->Instance->DCTRL = 0;
03799     errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
03800
03801     if (errorstate != HAL_SD_ERROR_NONE)
03802     {
03803       return errorstate;
03804     }
03805
03806     /* Configure the SD DPSM (Data Path State Machine) */
03807     sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
03808     sdmmc_datainitstructure.DataLength    = 64;
03809     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
03810     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03811     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03812     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
03813
03814     if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
03815     {
03816       return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
03817     }
03818
03819     errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
03820     if(errorstate != HAL_SD_ERROR_NONE)
03821     {
03822       return errorstate;
03823     }
03824
03825     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
03826     {
03827       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
03828       {
03829         for (count = 0U; count < 8U; count++)
03830         {
03831           SD_hs[(8U*loop)+count]  = SDMMC_ReadFIFO(hsd->Instance);
03832         }
03833         loop ++;
03834       }
03835
03836       if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
03837       {
03838         hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
03839         hsd->State= HAL_SD_STATE_READY;
03840         return HAL_SD_ERROR_TIMEOUT;
03841       }
03842     }
03843
03844     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03845     {
03846       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03847
03848       errorstate = 0;
03849
03850       return errorstate;
03851     }
03852     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03853     {
03854       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03855
03856       errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
03857
03858       return errorstate;
03859     }
03860     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03861     {
03862       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03863
03864       errorstate = SDMMC_ERROR_RX_OVERRUN;
03865
03866       return errorstate;
03867     }
03868     else
03869     {
03870       /* No error flag set */
03871     }
03872
03873     /* Clear all the static flags */
03874     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
03875
03876     /* Test if the switch mode  is ok */
03877     if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
03878     {
03879       errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
03880     }
03881     else
03882     {
03883 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
03884       hsd->DriveTransceiver_1_8V_Callback(SET);
03885 #else
03886       HAL_SD_DriveTransceiver_1_8V_Callback(SET);
03887 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
03888 #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
03889       /* Enable DelayBlock Peripheral */
03890       /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
03891       MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0);
03892       if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
03893       {
03894         return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
03895       }
03896 #endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
03897     }
03898   }
03899
03900   return errorstate;
03901 }
03902
03903 #endif /* USE_SD_TRANSCEIVER */
03904
03905 /**
03906   * @brief Read DMA Buffer 0 Transfer completed callbacks
03907   * @param hsd: SD handle
03908   * @retval None
03909   */
03910 __weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
03911 {
03912   /* Prevent unused argument(s) compilation warning */
03913   UNUSED(hsd);
03914
03915   /* NOTE : This function should not be modified, when the callback is needed,
03916             the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
03917    */
03918 }
03919
03920 /**
03921   * @brief Read DMA Buffer 1 Transfer completed callbacks
03922   * @param hsd: SD handle
03923   * @retval None
03924   */
03925 __weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
03926 {
03927   /* Prevent unused argument(s) compilation warning */
03928   UNUSED(hsd);
03929
03930   /* NOTE : This function should not be modified, when the callback is needed,
03931             the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
03932    */
03933 }
03934
03935 /**
03936   * @brief Write DMA Buffer 0 Transfer completed callbacks
03937   * @param hsd: SD handle
03938   * @retval None
03939   */
03940 __weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
03941 {
03942   /* Prevent unused argument(s) compilation warning */
03943   UNUSED(hsd);
03944
03945   /* NOTE : This function should not be modified, when the callback is needed,
03946             the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
03947    */
03948 }
03949
03950 /**
03951   * @brief Write DMA Buffer 1 Transfer completed callbacks
03952   * @param hsd: SD handle
03953   * @retval None
03954   */
03955 __weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
03956 {
03957   /* Prevent unused argument(s) compilation warning */
03958   UNUSED(hsd);
03959
03960   /* NOTE : This function should not be modified, when the callback is needed,
03961             the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
03962    */
03963 }
03964
03965
03966 /**
03967   * @}
03968   */
03969
03970 #endif /* HAL_SD_MODULE_ENABLED */
03971
03972 /**
03973   * @}
03974   */
03975
03976 /**
03977   * @}
03978   */
03979
03980 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd.h Source File

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stm32h7xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SD_H
00022 #define STM32H7xx_HAL_SD_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_sdmmc.h"
00030 #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)
00031 #include "stm32h7xx_ll_delayblock.h"
00032 #endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
00033
00034 /** @addtogroup STM32H7xx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @defgroup SD SD
00039   * @brief SD HAL module driver
00040   * @{
00041   */
00042
00043 /* Exported types ------------------------------------------------------------*/
00044 /** @defgroup SD_Exported_Types SD Exported Types
00045   * @{
00046   */
00047
00048 /** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
00049   * @{
00050   */
00051 typedef enum
00052 {
00053   HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
00054   HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
00055   HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
00056   HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
00057   HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
00058   HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
00059   HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */
00060   HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
00061 }HAL_SD_StateTypeDef;
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
00067   * @{
00068   */
00069 typedef uint32_t HAL_SD_CardStateTypeDef;
00070
00071 #define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
00072 #define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
00073 #define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
00074 #define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
00075 #define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
00076 #define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
00077 #define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
00078 #define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
00079 #define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
00085   * @{
00086   */
00087 #define SD_InitTypeDef      SDMMC_InitTypeDef
00088 #define SD_TypeDef          SDMMC_TypeDef
00089
00090 /**
00091   * @brief  SD Card Information Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t CardType;                     /*!< Specifies the card Type                         */
00096
00097   uint32_t CardVersion;                  /*!< Specifies the card version                      */
00098
00099   uint32_t Class;                        /*!< Specifies the class of the card class           */
00100
00101   uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
00102
00103   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
00104
00105   uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
00106
00107   uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
00108
00109   uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
00110
00111   uint32_t CardSpeed;                    /*!< Specifies the card Speed                        */
00112
00113 }HAL_SD_CardInfoTypeDef;
00114
00115 /**
00116   * @brief  SD handle Structure definition
00117   */
00118 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00119 typedef struct __SD_HandleTypeDef
00120 #else
00121 typedef struct
00122 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00123 {
00124   SD_TypeDef                   *Instance;        /*!< SD registers base address           */
00125
00126   SD_InitTypeDef               Init;             /*!< SD required parameters              */
00127
00128   HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
00129
00130   uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
00131
00132   uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
00133
00134   uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
00135
00136   uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
00137
00138   __IO uint32_t                Context;          /*!< SD transfer context                 */
00139
00140   __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
00141
00142   __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */
00143
00144   HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
00145
00146   uint32_t                     CSD[4];           /*!< SD card specific data table         */
00147
00148   uint32_t                     CID[4];           /*!< SD card identification number table */
00149
00150 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00151   void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
00152   void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
00153   void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
00154   void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
00155   void (* Read_DMADblBuf0CpltCallback)    (struct __SD_HandleTypeDef *hsd);
00156   void (* Read_DMADblBuf1CpltCallback)    (struct __SD_HandleTypeDef *hsd);
00157   void (* Write_DMADblBuf0CpltCallback)   (struct __SD_HandleTypeDef *hsd);
00158   void (* Write_DMADblBuf1CpltCallback)   (struct __SD_HandleTypeDef *hsd);
00159
00160 #if (USE_SD_TRANSCEIVER != 0U)
00161   void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);
00162 #endif /* USE_SD_TRANSCEIVER */
00163
00164   void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
00165   void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
00166 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00167 }SD_HandleTypeDef;
00168
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
00174   * @{
00175   */
00176 typedef struct
00177 {
00178   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00179   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00180   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00181   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00182   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00183   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00184   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00185   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00186   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00187   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00188   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00189   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00190   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00191   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00192   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00193   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00194   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00195   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00196   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00197   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00198   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00199   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00200   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00201   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00202   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00203   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00204   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00205   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00206   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00207   __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
00208   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00209   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00210   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00211   __IO uint8_t  FileFormat;           /*!< File format                           */
00212   __IO uint8_t  ECC;                  /*!< ECC code                              */
00213   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00214   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00215 }HAL_SD_CardCSDTypeDef;
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
00221   * @{
00222   */
00223 typedef struct
00224 {
00225   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00226   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00227   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00228   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00229   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00230   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00231   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00232   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00233   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00234   __IO uint8_t  Reserved2;       /*!< Always 1              */
00235
00236 }HAL_SD_CardCIDTypeDef;
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
00242   * @{
00243   */
00244 typedef struct
00245 {
00246   __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
00247   __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
00248   __IO uint16_t CardType;               /*!< Carries information about card type                        */
00249   __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
00250   __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
00251   __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
00252   __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
00253   __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
00254   __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
00255   __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
00256   __IO uint8_t  UhsSpeedGrade;          /*!< Carries information about the speed grade of UHS card      */
00257   __IO uint8_t  UhsAllocationUnitSize;  /*!< Carries information about the UHS card's allocation unit size  */
00258   __IO uint8_t  VideoSpeedClass;        /*!< Carries information about the Video Speed Class of UHS card    */
00259 }HAL_SD_CardStatusTypeDef;
00260 /**
00261   * @}
00262   */
00263
00264 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00265 /** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
00266   * @{
00267   */
00268 typedef enum
00269 {
00270   HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
00271   HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
00272   HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
00273   HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
00274   HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  = 0x04U,  /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */
00275   HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  = 0x05U,  /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */
00276   HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U,  /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */
00277   HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,  /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */
00278
00279   HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
00280   HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
00281 }HAL_SD_CallbackIDTypeDef;
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
00287   * @{
00288   */
00289 typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
00290 #if (USE_SD_TRANSCEIVER != 0U)
00291 typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
00292 #endif /* USE_SD_TRANSCEIVER */
00293 /**
00294   * @}
00295   */
00296 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00297 /**
00298   * @}
00299   */
00300
00301 /* Exported constants --------------------------------------------------------*/
00302 /** @defgroup SD_Exported_Constants Exported Constants
00303   * @{
00304   */
00305
00306 #define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
00307
00308 /** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
00309   * @{
00310   */
00311 #define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                        /*!< No error                                                     */
00312 #define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL                /*!< Command response received (but CRC check failed)             */
00313 #define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL               /*!< Data block sent/received (CRC check failed)                  */
00314 #define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT             /*!< Command response timeout                                     */
00315 #define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT                /*!< Data timeout                                                 */
00316 #define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN                 /*!< Transmit FIFO underrun                                       */
00317 #define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN                  /*!< Receive FIFO overrun                                         */
00318 #define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED             /*!< Misaligned address                                           */
00319 #define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR               /*!< Transferred block length is not allowed for the card or the
00320                                                                                           number of transferred bytes does not match the block length   */
00321 #define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR               /*!< An error in the sequence of erase command occurs             */
00322 #define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM             /*!< An invalid selection for erase groups                        */
00323 #define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION        /*!< Attempt to program a write protect block                     */
00324 #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED          /*!< Sequence or password error has been detected in unlock
00325                                                                                            command or if there was an attempt to access a locked card   */
00326 #define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED              /*!< CRC check of the previous command failed                     */
00327 #define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD                 /*!< Command is not legal for the card state                      */
00328 #define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED             /*!< Card internal ECC was applied but failed to correct the data */
00329 #define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                      /*!< Internal card controller error                               */
00330 #define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR         /*!< General or unknown error                                     */
00331 #define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN        /*!< The card could not sustain data reading in stream rmode      */
00332 #define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN        /*!< The card could not sustain data programming in stream mode   */
00333 #define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE           /*!< CID/CSD overwrite error                                      */
00334 #define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP               /*!< Only partial address space was erased                        */
00335 #define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED           /*!< Command has been executed without using internal ECC         */
00336 #define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET                 /*!< Erase sequence was cleared before executing because an out
00337                                                                                            of erase sequence command was received                       */
00338 #define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR                 /*!< Error in sequence of authentication                          */
00339 #define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE           /*!< Error in case of invalid voltage range                       */
00340 #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE           /*!< Error when addressed block is out of range                   */
00341 #define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE      /*!< Error when command request is not applicable                 */
00342 #define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER           /*!< the used parameter is not valid                              */
00343 #define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE         /*!< Error when feature is not insupported                        */
00344 #define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                        /*!< Error when transfer process is busy                          */
00345 #define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                         /*!< Error while DMA transfer                                     */
00346 #define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                     /*!< Timeout error                                                 */
00347
00348 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00349 #define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
00350 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
00356   * @{
00357   */
00358 #define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
00359 #define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
00360 #define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
00361 #define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
00362 #define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
00363 #define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
00364 #define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
00371   * @{
00372   */
00373 #define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */
00374 #define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */
00375 #define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
00376                                                                  and <104Mo/s for SDR104, Spec version 3.01          */
00377
00378 #define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
00379 #define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
00380 #define CARD_SECURED               ((uint32_t)0x00000003U)
00381
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
00387   * @{
00388   */
00389 #define CARD_V1_X                  ((uint32_t)0x00000000U)
00390 #define CARD_V2_X                  ((uint32_t)0x00000001U)
00391 /**
00392   * @}
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /* Exported macro ------------------------------------------------------------*/
00400 /** @defgroup SD_Exported_macros SD Exported Macros
00401  *  @brief macros to handle interrupts and specific clock configurations
00402  * @{
00403  */
00404 /** @brief Reset SD handle state.
00405   * @param  __HANDLE__ : SD handle.
00406   * @retval None
00407   */
00408 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00409 #define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00410                                                                (__HANDLE__)->State = HAL_SD_STATE_RESET; \
00411                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00412                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00413                                                              } while(0)
00414 #else
00415 #define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
00416 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00417
00418 /**
00419   * @brief  Enable the SD device interrupt.
00420   * @param  __HANDLE__: SD Handle
00421   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00422   *         This parameter can be one or a combination of the following values:
00423   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00424   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00425   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00426   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00427   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00428   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00429   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00430   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00431   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00432   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00433   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00434   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00435   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00436   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00437   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00438   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00439   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00440   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00441   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00442   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00443   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00444   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00445   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00446   * @retval None
00447   */
00448 #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00449
00450 /**
00451   * @brief  Disable the SD device interrupt.
00452   * @param  __HANDLE__: SD Handle
00453   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00454   *          This parameter can be one or a combination of the following values:
00455   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00456   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00457   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00458   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00459   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00460   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00461   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00462   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00463   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00464   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00465   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00466   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00467   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00468   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00469   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00470   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00471   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00472   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00473   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00474   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00475   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00476   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00477   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00478   * @retval None
00479   */
00480 #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00481
00482 /**
00483   * @brief  Check whether the specified SD flag is set or not.
00484   * @param  __HANDLE__: SD Handle
00485   * @param  __FLAG__: specifies the flag to check.
00486   *          This parameter can be one of the following values:
00487   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00488   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00489   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00490   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00491   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00492   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00493   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00494   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00495   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00496   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00497   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00498   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00499   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
00500   *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
00501   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
00502   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
00503   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
00504   *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
00505   *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
00506   *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
00507   *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00508   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00509   *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
00510   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00511   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00512   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00513   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00514   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00515   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00516   * @retval The new state of SD FLAG (SET or RESET).
00517   */
00518 #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00519
00520 /**
00521   * @brief  Clear the SD's pending flags.
00522   * @param  __HANDLE__: SD Handle
00523   * @param  __FLAG__: specifies the flag to clear.
00524   *          This parameter can be one or a combination of the following values:
00525   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00526   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00527   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00528   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00529   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00530   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00531   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00532   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00533   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00534   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00535   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00536   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00537   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00538   *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
00539   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00540   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00541   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00542   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00543   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00544   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00545   * @retval None
00546   */
00547 #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00548
00549 /**
00550   * @brief  Check whether the specified SD interrupt has occurred or not.
00551   * @param  __HANDLE__: SD Handle
00552   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00553   *          This parameter can be one of the following values:
00554   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00555   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00556   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00557   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00558   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00559   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00560   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00561   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00562   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00563   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00564   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00565   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00566   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00567   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00568   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00569   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00570   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00571   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00572   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00573   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00574   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00575   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00576   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00577   * @retval The new state of SD IT (SET or RESET).
00578   */
00579 #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00580
00581 /**
00582   * @brief  Clear the SD's interrupt pending bits.
00583   * @param  __HANDLE__: SD Handle
00584   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00585   *          This parameter can be one or a combination of the following values:
00586   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00587   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00588   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00589   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00590   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00591   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00592   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00593   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00594   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00595   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00596   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00597   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00598   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00599   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00600   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00601   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00602   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00603   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00604   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00605   * @retval None
00606   */
00607 #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00608
00609 /**
00610   * @}
00611   */
00612
00613 /* Include SD HAL Extension module */
00614 #include "stm32h7xx_hal_sd_ex.h"
00615
00616 /* Exported functions --------------------------------------------------------*/
00617 /** @defgroup SD_Exported_Functions SD Exported Functions
00618   * @{
00619   */
00620
00621 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00622   * @{
00623   */
00624 HAL_StatusTypeDef HAL_SD_Init     (SD_HandleTypeDef *hsd);
00625 HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);
00626 HAL_StatusTypeDef HAL_SD_DeInit   (SD_HandleTypeDef *hsd);
00627 void              HAL_SD_MspInit  (SD_HandleTypeDef *hsd);
00628 void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
00634   * @{
00635   */
00636 /* Blocking mode: Polling */
00637 HAL_StatusTypeDef HAL_SD_ReadBlocks     (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00638 HAL_StatusTypeDef HAL_SD_WriteBlocks    (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00639 HAL_StatusTypeDef HAL_SD_Erase          (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
00640 /* Non-Blocking mode: IT */
00641 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT  (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00642 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00643 /* Non-Blocking mode: DMA */
00644 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00645 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00646
00647 void              HAL_SD_IRQHandler     (SD_HandleTypeDef *hsd);
00648
00649 /* Callback in non blocking modes (DMA) */
00650 void              HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);
00651 void              HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
00652 void              HAL_SD_ErrorCallback  (SD_HandleTypeDef *hsd);
00653 void              HAL_SD_AbortCallback  (SD_HandleTypeDef *hsd);
00654
00655 #if (USE_SD_TRANSCEIVER != 0U)
00656 /* Callback to switch in 1.8V mode */
00657 void              HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
00658 #endif /* USE_SD_TRANSCEIVER */
00659
00660 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
00661 /* SD callback registering/unregistering */
00662 HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback);
00663 HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
00664
00665 #if (USE_SD_TRANSCEIVER != 0U)
00666 HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback  (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
00667 HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
00668 #endif /* USE_SD_TRANSCEIVER */
00669 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
00670
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00676   * @{
00677   */
00678 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
00679 HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup SD_Exported_Functions_Group4 SD card related functions
00685   * @{
00686   */
00687 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
00688 HAL_StatusTypeDef       HAL_SD_GetCardCID   (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
00689 HAL_StatusTypeDef       HAL_SD_GetCardCSD   (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
00690 HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
00691 HAL_StatusTypeDef       HAL_SD_GetCardInfo  (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
00697   * @{
00698   */
00699 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
00700 uint32_t            HAL_SD_GetError(SD_HandleTypeDef *hsd);
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
00706   * @{
00707   */
00708 HAL_StatusTypeDef HAL_SD_Abort   (SD_HandleTypeDef *hsd);
00709 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
00710 /**
00711   * @}
00712   */
00713
00714 /* Private types -------------------------------------------------------------*/
00715 /** @defgroup SD_Private_Types SD Private Types
00716   * @{
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /* Private defines -----------------------------------------------------------*/
00724 /** @defgroup SD_Private_Defines SD Private Defines
00725   * @{
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /* Private variables ---------------------------------------------------------*/
00733 /** @defgroup SD_Private_Variables SD Private Variables
00734   * @{
00735   */
00736
00737 /**
00738   * @}
00739   */
00740
00741 /* Private constants ---------------------------------------------------------*/
00742 /** @defgroup SD_Private_Constants SD Private Constants
00743   * @{
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /* Private macros ------------------------------------------------------------*/
00751 /** @defgroup SD_Private_Macros SD Private Macros
00752   * @{
00753   */
00754
00755 /**
00756   * @}
00757   */
00758
00759 /* Private functions prototypes ----------------------------------------------*/
00760 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00761   * @{
00762   */
00763
00764 /**
00765   * @}
00766   */
00767
00768 /* Private functions ---------------------------------------------------------*/
00769 /** @defgroup SD_Private_Functions SD Private Functions
00770   * @{
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777
00778 /**
00779   * @}
00780   */
00781
00782 /**
00783   * @}
00784   */
00785
00786 /**
00787   * @}
00788   */
00789
00790 #ifdef __cplusplus
00791 }
00792 #endif
00793
00794
00795 #endif /* STM32H7xx_HAL_SD_H */
00796
00797 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd_ex.c Source File

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stm32h7xx_hal_sd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SD card Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Secure Digital (SD) peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015    The SD Extension HAL driver can be used as follows:
00016    (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
00017    (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00024   * All rights reserved.</center></h2>
00025   *
00026   * This software component is licensed by ST under BSD 3-Clause license,
00027   * the "License"; You may not use this file except in compliance with the
00028   * License. You may obtain a copy of the License at:
00029   *                       opensource.org/licenses/BSD-3-Clause
00030   *
00031   ******************************************************************************
00032   */
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32h7xx_hal.h"
00036
00037 /** @addtogroup STM32H7xx_HAL_Driver
00038   * @{
00039   */
00040
00041 /** @defgroup SDEx SDEx
00042   * @brief SD Extended HAL module driver
00043   * @{
00044   */
00045
00046 #ifdef HAL_SD_MODULE_ENABLED
00047
00048 /* Private typedef -----------------------------------------------------------*/
00049 /* Private define ------------------------------------------------------------*/
00050 /* Private macro -------------------------------------------------------------*/
00051 /* Private variables ---------------------------------------------------------*/
00052 /* Private function prototypes -----------------------------------------------*/
00053 /* Private functions ---------------------------------------------------------*/
00054 /* Exported functions --------------------------------------------------------*/
00055 /** @addtogroup SDEx_Exported_Functions
00056   * @{
00057   */
00058
00059 /** @addtogroup SDEx_Exported_Functions_Group1
00060  *  @brief   Multibuffer functions
00061  *
00062 @verbatim
00063   ==============================================================================
00064           ##### Multibuffer functions #####
00065   ==============================================================================
00066   [..]
00067     This section provides functions allowing to configure the multibuffer mode and start read and write
00068     multibuffer mode for SD HAL driver.
00069
00070 @endverbatim
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
00076   * @param  hsd: SD handle
00077   * @param  pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
00078   * @param  pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
00079   * @param  BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
00080   * @retval HAL status
00081   */
00082 HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
00083 {
00084   if(hsd->State == HAL_SD_STATE_READY)
00085   {
00086     hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
00087     hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
00088     hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
00089
00090     return HAL_OK;
00091   }
00092   else
00093   {
00094     return HAL_BUSY;
00095   }
00096 }
00097
00098 /**
00099   * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
00100   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
00101   * @param  hsd: SD handle
00102   * @param  BlockAdd: Block Address from where data is to be read
00103   * @param  NumberOfBlocks: Total number of blocks to read
00104   * @retval HAL status
00105   */
00106 HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00107 {
00108   SDMMC_DataInitTypeDef config;
00109   uint32_t errorstate;
00110   uint32_t DmaBase0_reg, DmaBase1_reg;
00111   uint32_t add = BlockAdd;
00112
00113   if(hsd->State == HAL_SD_STATE_READY)
00114   {
00115     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00116     {
00117       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00118       return HAL_ERROR;
00119     }
00120
00121     DmaBase0_reg = hsd->Instance->IDMABASE0;
00122     DmaBase1_reg = hsd->Instance->IDMABASE1;
00123     if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
00124     {
00125       hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00126       return HAL_ERROR;
00127     }
00128
00129     /* Initialize data control register */
00130     hsd->Instance->DCTRL = 0;
00131     /* Clear old Flags*/
00132     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
00133
00134     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00135     hsd->State = HAL_SD_STATE_BUSY;
00136
00137     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00138     {
00139       add *= 512U;
00140     }
00141
00142     /* Set Block Size for Card */
00143     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00144     if(errorstate != HAL_SD_ERROR_NONE)
00145     {
00146       /* Clear all the static flags */
00147       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00148       hsd->ErrorCode |= errorstate;
00149       hsd->State = HAL_SD_STATE_READY;
00150       return HAL_ERROR;
00151     }
00152
00153     /* Configure the SD DPSM (Data Path State Machine) */
00154     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00155     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00156     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00157     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00158     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00159     config.DPSM          = SDMMC_DPSM_DISABLE;
00160     (void)SDMMC_ConfigData(hsd->Instance, &config);
00161
00162     hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
00163
00164     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00165
00166     hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00167
00168     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
00169
00170     /* Read Blocks in DMA mode */
00171     hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
00172
00173     /* Read Multi Block command */
00174     errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
00175     if(errorstate != HAL_SD_ERROR_NONE)
00176     {
00177       hsd->State = HAL_SD_STATE_READY;
00178       hsd->ErrorCode |= errorstate;
00179       return HAL_ERROR;
00180     }
00181
00182     return HAL_OK;
00183   }
00184   else
00185   {
00186     return HAL_BUSY;
00187   }
00188
00189 }
00190
00191 /**
00192   * @brief  Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
00193   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
00194   * @param  hsd: SD handle
00195   * @param  BlockAdd: Block Address from where data is to be read
00196   * @param  NumberOfBlocks: Total number of blocks to read
00197   * @retval HAL status
00198 */
00199 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00200 {
00201   SDMMC_DataInitTypeDef config;
00202   uint32_t errorstate;
00203   uint32_t DmaBase0_reg, DmaBase1_reg;
00204   uint32_t add = BlockAdd;
00205
00206   if(hsd->State == HAL_SD_STATE_READY)
00207   {
00208     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00209     {
00210       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00211       return HAL_ERROR;
00212     }
00213
00214     DmaBase0_reg = hsd->Instance->IDMABASE0;
00215     DmaBase1_reg = hsd->Instance->IDMABASE1;
00216     if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
00217     {
00218       hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00219       return HAL_ERROR;
00220     }
00221
00222     /* Initialize data control register */
00223     hsd->Instance->DCTRL = 0;
00224
00225     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00226
00227     hsd->State = HAL_SD_STATE_BUSY;
00228
00229     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00230     {
00231       add *= 512U;
00232     }
00233
00234     /* Set Block Size for Card */
00235     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00236     if(errorstate != HAL_SD_ERROR_NONE)
00237     {
00238       /* Clear all the static flags */
00239       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00240       hsd->ErrorCode |= errorstate;
00241       hsd->State = HAL_SD_STATE_READY;
00242       return HAL_ERROR;
00243     }
00244
00245     /* Configure the SD DPSM (Data Path State Machine) */
00246     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00247     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00248     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00249     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00250     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00251     config.DPSM          = SDMMC_DPSM_DISABLE;
00252     (void)SDMMC_ConfigData(hsd->Instance, &config);
00253
00254     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00255
00256     hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00257
00258     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
00259
00260     /* Write Blocks in DMA mode */
00261     hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
00262
00263     /* Write Multi Block command */
00264     errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
00265     if(errorstate != HAL_SD_ERROR_NONE)
00266     {
00267       hsd->State = HAL_SD_STATE_READY;
00268       hsd->ErrorCode |= errorstate;
00269       return HAL_ERROR;
00270     }
00271
00272     return HAL_OK;
00273   }
00274   else
00275   {
00276     return HAL_BUSY;
00277   }
00278 }
00279
00280
00281 /**
00282   * @brief  Change the DMA Buffer0 or Buffer1 address on the fly.
00283   * @param  hsd:           pointer to a SD_HandleTypeDef structure.
00284   * @param  Buffer:        the buffer to be changed, This parameter can be one of
00285   *                        the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
00286   * @param  pDataBuffer:   The new address
00287   * @note   The BUFFER0 address can be changed only when the current transfer use
00288   *         BUFFER1 and the BUFFER1 address can be changed only when the current
00289   *         transfer use BUFFER0.
00290   * @retval HAL status
00291   */
00292 HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
00293 {
00294   if(Buffer == SD_DMA_BUFFER0)
00295   {
00296     /* change the buffer0 address */
00297     hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
00298   }
00299   else
00300   {
00301     /* change the memory1 address */
00302     hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
00303   }
00304
00305   return HAL_OK;
00306 }
00307
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 #endif /* HAL_SD_MODULE_ENABLED */
00318
00319 /**
00320   * @}
00321   */
00322
00323 /**
00324   * @}
00325   */
00326
00327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sd_ex.h Source File

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stm32h7xx_hal_sd_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SD HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                       opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SDEX_H
00022 #define STM32H7xx_HAL_SDEX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SDEx
00036   * @brief SD HAL extended module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup SDEx_Exported_Types SDEx Exported Types
00042   * @{
00043   */
00044
00045 /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
00046   * @{
00047   */
00048 typedef enum
00049 {
00050   SD_DMA_BUFFER0      = 0x00U,    /*!< selects SD internal DMA Buffer 0     */
00051   SD_DMA_BUFFER1      = 0x01U,    /*!< selects SD internal DMA Buffer 1     */
00052
00053 }HAL_SDEx_DMABuffer_MemoryTypeDef;
00054
00055
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063 /* Exported constants --------------------------------------------------------*/
00064 /* Exported macro ------------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @defgroup SDEx_Exported_Functions SDEx Exported Functions
00067   * @{
00068   */
00069
00070 /** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
00071   * @{
00072   */
00073 HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
00074 HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00075 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00076 HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
00077
00078 void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
00079 void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
00080 void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
00081 void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
00082
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Private types -------------------------------------------------------------*/
00092 /* Private defines -----------------------------------------------------------*/
00093 /* Private variables ---------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /* Private macros ------------------------------------------------------------*/
00096 /* Private functions prototypes ----------------------------------------------*/
00097 /* Private functions ---------------------------------------------------------*/
00098
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106 #ifdef __cplusplus
00107 }
00108 #endif
00109
00110
00111 #endif /* stm32h7xx_HAL_SDEX_H */
00112
00113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sdram.c Source File

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stm32h7xx_hal_sdram.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sdram.c
00004   * @author  MCD Application Team
00005   * @brief   SDRAM HAL module driver.
00006   *          This file provides a generic firmware to drive SDRAM memories mounted
00007   *          as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                        ##### How to use this driver #####
00012   ==============================================================================
00013   [..]
00014     This driver is a generic layered driver which contains a set of APIs used to
00015     control SDRAM memories. It uses the FMC layer functions to interface
00016     with SDRAM devices.
00017     The following sequence should be followed to configure the FMC to interface
00018     with SDRAM memories:
00019
00020    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
00021           SDRAM_HandleTypeDef  hsdram
00022
00023        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
00024             values of the structure member.
00025
00026        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
00027             base register instance for NOR or SDRAM device
00028
00029    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
00030           FMC_SDRAM_TimingTypeDef  Timing;
00031       and fill its fields with the allowed values of the structure member.
00032
00033    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
00034        performs the following sequence:
00035
00036        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
00037        (##) Control register configuration using the FMC SDRAM interface function
00038             FMC_SDRAM_Init()
00039        (##) Timing register configuration using the FMC SDRAM interface function
00040             FMC_SDRAM_Timing_Init()
00041        (##) Program the SDRAM external device by applying its initialization sequence
00042             according to the device plugged in your hardware. This step is mandatory
00043             for accessing the SDRAM device.
00044
00045    (#) At this stage you can perform read/write accesses from/to the memory connected
00046        to the SDRAM Bank. You can perform either polling or DMA transfer using the
00047        following APIs:
00048        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
00049        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
00050
00051    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
00052        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
00053        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
00054        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
00055        structure.
00056
00057    (#) You can continuously monitor the SDRAM device HAL state by calling the function
00058        HAL_SDRAM_GetState()
00059
00060    *** Callback registration ***
00061     =============================================
00062     [..]
00063       The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
00064       allows the user to configure dynamically the driver callbacks.
00065
00066       Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
00067       it allows to register following callbacks:
00068         (+) MspInitCallback    : SDRAM MspInit.
00069         (+) MspDeInitCallback  : SDRAM MspDeInit.
00070       This function takes as parameters the HAL peripheral handle, the Callback ID
00071       and a pointer to the user callback function.
00072
00073       Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
00074       weak (surcharged) function. It allows to reset following callbacks:
00075         (+) MspInitCallback    : SDRAM MspInit.
00076         (+) MspDeInitCallback  : SDRAM MspDeInit.
00077       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00078
00079       By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
00080       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00081       Exception done for MspInit and MspDeInit callbacks that are respectively
00082       reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
00083       and @ref  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
00084       If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
00085       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00086
00087       Callbacks can be registered/unregistered in READY state only.
00088       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00089       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00090       during the Init/DeInit.
00091       In that case first register the MspInit/MspDeInit user callbacks
00092       using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
00093       or @ref HAL_SDRAM_Init function.
00094
00095       When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
00096       not defined, the callback registering feature is not available
00097       and weak (surcharged) callbacks are used.
00098
00099   @endverbatim
00100   ******************************************************************************
00101   * @attention
00102   *
00103   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00104   *
00105   * This software component is licensed by ST under BSD 3-Clause license,
00106   * the "License"; You may not use this file except in compliance with the
00107   * License. You may obtain a copy of the License at:
00108   *                       opensource.org/licenses/BSD-3-Clause
00109   *
00110   ******************************************************************************
00111   */
00112
00113 /* Includes ------------------------------------------------------------------*/
00114 #include "stm32h7xx_hal.h"
00115
00116
00117 /** @addtogroup STM32H7xx_HAL_Driver
00118   * @{
00119   */
00120
00121 #ifdef HAL_SDRAM_MODULE_ENABLED
00122
00123 /** @defgroup SDRAM SDRAM
00124   * @brief SDRAM driver modules
00125   * @{
00126   */
00127
00128 /**
00129   @cond 0
00130   */
00131 /* Private typedef -----------------------------------------------------------*/
00132 /* Private define ------------------------------------------------------------*/
00133 /* Private macro -------------------------------------------------------------*/
00134 /* Private variables ---------------------------------------------------------*/
00135 /* Private function prototypes -----------------------------------------------*/
00136 static void SDRAM_DMACplt    (MDMA_HandleTypeDef *hmdma);
00137 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
00138 static void SDRAM_DMAError   (MDMA_HandleTypeDef *hmdma);
00139 /**
00140   @endcond
00141   */
00142
00143 /* Exported functions --------------------------------------------------------*/
00144 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
00145   * @{
00146   */
00147
00148 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00149   * @brief    Initialization and Configuration functions
00150   *
00151   @verbatim
00152   ==============================================================================
00153            ##### SDRAM Initialization and de_initialization functions #####
00154   ==============================================================================
00155   [..]
00156     This section provides functions allowing to initialize/de-initialize
00157     the SDRAM memory
00158
00159 @endverbatim
00160   * @{
00161   */
00162
00163 /**
00164   * @brief  Performs the SDRAM device initialization sequence.
00165   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00166   *                the configuration information for SDRAM module.
00167   * @param  Timing Pointer to SDRAM control timing structure
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
00171 {
00172   /* Check the SDRAM handle parameter */
00173   if (hsdram == NULL)
00174   {
00175     return HAL_ERROR;
00176   }
00177
00178   if (hsdram->State == HAL_SDRAM_STATE_RESET)
00179   {
00180     /* Allocate lock resource and initialize it */
00181     hsdram->Lock = HAL_UNLOCKED;
00182 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00183     if(hsdram->MspInitCallback == NULL)
00184     {
00185       hsdram->MspInitCallback = HAL_SDRAM_MspInit;
00186     }
00187     hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
00188     hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
00189     hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00190
00191     /* Init the low level hardware */
00192     hsdram->MspInitCallback(hsdram);
00193 #else
00194     /* Initialize the low level hardware (MSP) */
00195     HAL_SDRAM_MspInit(hsdram);
00196 #endif
00197   }
00198
00199   /* Initialize the SDRAM controller state */
00200   hsdram->State = HAL_SDRAM_STATE_BUSY;
00201
00202   /* Initialize SDRAM control Interface */
00203   (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
00204
00205   /* Initialize SDRAM timing Interface */
00206   (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
00207
00208   /* Enable FMC Peripheral */
00209   __FMC_ENABLE();
00210   /* Update the SDRAM controller state */
00211   hsdram->State = HAL_SDRAM_STATE_READY;
00212
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  Perform the SDRAM device initialization sequence.
00218   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00219   *                the configuration information for SDRAM module.
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
00223 {
00224 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00225   if(hsdram->MspDeInitCallback == NULL)
00226   {
00227     hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
00228   }
00229
00230   /* DeInit the low level hardware */
00231   hsdram->MspDeInitCallback(hsdram);
00232 #else
00233   /* Initialize the low level hardware (MSP) */
00234   HAL_SDRAM_MspDeInit(hsdram);
00235 #endif
00236
00237   /* Configure the SDRAM registers with their reset values */
00238   (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
00239
00240   /* Reset the SDRAM controller state */
00241   hsdram->State = HAL_SDRAM_STATE_RESET;
00242
00243   /* Release Lock */
00244   __HAL_UNLOCK(hsdram);
00245
00246   return HAL_OK;
00247 }
00248
00249 /**
00250   * @brief  SDRAM MSP Init.
00251   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00252   *                the configuration information for SDRAM module.
00253   * @retval None
00254   */
00255 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
00256 {
00257   /* Prevent unused argument(s) compilation warning */
00258   UNUSED(hsdram);
00259
00260   /* NOTE: This function Should not be modified, when the callback is needed,
00261             the HAL_SDRAM_MspInit could be implemented in the user file
00262    */
00263 }
00264
00265 /**
00266   * @brief  SDRAM MSP DeInit.
00267   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00268   *                the configuration information for SDRAM module.
00269   * @retval None
00270   */
00271 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
00272 {
00273   /* Prevent unused argument(s) compilation warning */
00274   UNUSED(hsdram);
00275
00276   /* NOTE: This function Should not be modified, when the callback is needed,
00277             the HAL_SDRAM_MspDeInit could be implemented in the user file
00278    */
00279 }
00280
00281 /**
00282   * @brief  This function handles SDRAM refresh error interrupt request.
00283   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00284   *                the configuration information for SDRAM module.
00285   * @retval HAL status
00286 */
00287 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
00288 {
00289   /* Check SDRAM interrupt Rising edge flag */
00290   if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
00291   {
00292     /* SDRAM refresh error interrupt callback */
00293 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00294     hsdram->RefreshErrorCallback(hsdram);
00295 #else
00296     HAL_SDRAM_RefreshErrorCallback(hsdram);
00297 #endif
00298
00299     /* Clear SDRAM refresh error interrupt pending bit */
00300     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
00301   }
00302 }
00303
00304 /**
00305   * @brief  SDRAM Refresh error callback.
00306   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00307   *                the configuration information for SDRAM module.
00308   * @retval None
00309   */
00310 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
00311 {
00312   /* Prevent unused argument(s) compilation warning */
00313   UNUSED(hsdram);
00314
00315   /* NOTE: This function Should not be modified, when the callback is needed,
00316             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
00317    */
00318 }
00319
00320 /**
00321   * @brief  DMA transfer complete callback.
00322   * @param  hmdma pointer to a DMA_HandleTypeDef structure that contains
00323   *                the configuration information for the specified DMA module.
00324   * @retval None
00325   */
00326 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
00327 {
00328   /* Prevent unused argument(s) compilation warning */
00329   UNUSED(hmdma);
00330
00331   /* NOTE: This function Should not be modified, when the callback is needed,
00332             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
00333    */
00334 }
00335
00336 /**
00337   * @brief  DMA transfer complete error callback.
00338   * @param  hmdma DMA handle
00339   * @retval None
00340   */
00341 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
00342 {
00343   /* Prevent unused argument(s) compilation warning */
00344   UNUSED(hmdma);
00345
00346   /* NOTE: This function Should not be modified, when the callback is needed,
00347             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
00348    */
00349 }
00350
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
00356   * @brief    Input Output and memory control functions
00357   *
00358   @verbatim
00359   ==============================================================================
00360                     ##### SDRAM Input and Output functions #####
00361   ==============================================================================
00362   [..]
00363     This section provides functions allowing to use and control the SDRAM memory
00364
00365 @endverbatim
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Reads 8-bit data buffer from the SDRAM memory.
00371   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00372   *                the configuration information for SDRAM module.
00373   * @param  pAddress Pointer to read start address
00374   * @param  pDstBuffer Pointer to destination buffer
00375   * @param  BufferSize Size of the buffer to read from memory
00376   * @retval HAL status
00377   */
00378 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00379 {
00380   uint32_t size;
00381   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00382   uint8_t * pdestbuff = pDstBuffer;
00383   HAL_SDRAM_StateTypeDef state = hsdram->State;
00384
00385   /* Check the SDRAM controller state */
00386   if (state == HAL_SDRAM_STATE_BUSY)
00387   {
00388     return HAL_BUSY;
00389   }
00390   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00391   {
00392     /* Process Locked */
00393     __HAL_LOCK(hsdram);
00394
00395     /* Update the SDRAM controller state */
00396     hsdram->State = HAL_SDRAM_STATE_BUSY;
00397
00398     /* Read data from source */
00399     for (size = BufferSize; size != 0U; size--)
00400     {
00401       *pdestbuff = *(__IO uint8_t *)pSdramAddress;
00402       pdestbuff++;
00403       pSdramAddress++;
00404     }
00405
00406     /* Update the SDRAM controller state */
00407     hsdram->State = state;
00408
00409     /* Process Unlocked */
00410     __HAL_UNLOCK(hsdram);
00411   }
00412   else
00413   {
00414     return  HAL_ERROR;
00415   }
00416
00417   return HAL_OK;
00418 }
00419
00420 /**
00421   * @brief  Writes 8-bit data buffer to SDRAM memory.
00422   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00423   *                the configuration information for SDRAM module.
00424   * @param  pAddress Pointer to write start address
00425   * @param  pSrcBuffer Pointer to source buffer to write
00426   * @param  BufferSize Size of the buffer to write to memory
00427   * @retval HAL status
00428   */
00429 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00430 {
00431   uint32_t size;
00432   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00433   uint8_t * psrcbuff = pSrcBuffer;
00434
00435   /* Check the SDRAM controller state */
00436   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
00437   {
00438     return HAL_BUSY;
00439   }
00440   else if (hsdram->State == HAL_SDRAM_STATE_READY)
00441   {
00442     /* Process Locked */
00443     __HAL_LOCK(hsdram);
00444
00445     /* Update the SDRAM controller state */
00446     hsdram->State = HAL_SDRAM_STATE_BUSY;
00447
00448     /* Write data to memory */
00449     for (size = BufferSize; size != 0U; size--)
00450     {
00451       *(__IO uint8_t *)pSdramAddress = *psrcbuff;
00452       psrcbuff++;
00453       pSdramAddress++;
00454     }
00455
00456     /* Update the SDRAM controller state */
00457     hsdram->State = HAL_SDRAM_STATE_READY;
00458
00459     /* Process Unlocked */
00460     __HAL_UNLOCK(hsdram);
00461   }
00462   else
00463   {
00464     return  HAL_ERROR;
00465   }
00466
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  Reads 16-bit data buffer from the SDRAM memory.
00472   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00473   *                the configuration information for SDRAM module.
00474   * @param  pAddress Pointer to read start address
00475   * @param  pDstBuffer Pointer to destination buffer
00476   * @param  BufferSize Size of the buffer to read from memory
00477   * @retval HAL status
00478   */
00479 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00480 {
00481   uint32_t size;
00482   __IO uint32_t *pSdramAddress = pAddress;
00483   uint16_t *pdestbuff = pDstBuffer;
00484   HAL_SDRAM_StateTypeDef state = hsdram->State;
00485
00486   /* Check the SDRAM controller state */
00487   if (state == HAL_SDRAM_STATE_BUSY)
00488   {
00489     return HAL_BUSY;
00490   }
00491   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00492   {
00493     /* Process Locked */
00494     __HAL_LOCK(hsdram);
00495
00496     /* Update the SDRAM controller state */
00497     hsdram->State = HAL_SDRAM_STATE_BUSY;
00498
00499     /* Read data from memory */
00500     for (size = BufferSize; size >= 2U ; size-=2U)
00501     {
00502       *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
00503       pdestbuff++;
00504       *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
00505       pdestbuff++;
00506       pSdramAddress++;
00507     }
00508
00509     /* Read last 16-bits if size is not 32-bits multiple */
00510     if ((BufferSize % 2U)!= 0U)
00511     {
00512       *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
00513     }
00514
00515     /* Update the SDRAM controller state */
00516     hsdram->State = state;
00517
00518     /* Process Unlocked */
00519     __HAL_UNLOCK(hsdram);
00520   }
00521   else
00522   {
00523     return  HAL_ERROR;
00524   }
00525
00526   return HAL_OK;
00527 }
00528
00529 /**
00530   * @brief  Writes 16-bit data buffer to SDRAM memory.
00531   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00532   *                the configuration information for SDRAM module.
00533   * @param  pAddress Pointer to write start address
00534   * @param  pSrcBuffer Pointer to source buffer to write
00535   * @param  BufferSize Size of the buffer to write to memory
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00539 {
00540   uint32_t size;
00541   __IO uint32_t *psdramaddress = pAddress;
00542   uint16_t * psrcbuff = pSrcBuffer;
00543
00544   /* Check the SDRAM controller state */
00545   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
00546   {
00547     return HAL_BUSY;
00548   }
00549   else if (hsdram->State == HAL_SDRAM_STATE_READY)
00550   {
00551     /* Process Locked */
00552     __HAL_LOCK(hsdram);
00553
00554     /* Update the SDRAM controller state */
00555     hsdram->State = HAL_SDRAM_STATE_BUSY;
00556
00557     /* Write data to memory */
00558     for (size = BufferSize; size >= 2U ; size-=2U)
00559     {
00560       *psdramaddress = (uint32_t)(*psrcbuff);
00561       psrcbuff++;
00562       *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
00563       psrcbuff++;
00564       psdramaddress++;
00565     }
00566
00567     /* Write last 16-bits if size is not 32-bits multiple */
00568     if ((BufferSize % 2U)!= 0U)
00569     {
00570       *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
00571     }
00572
00573     /* Update the SDRAM controller state */
00574     hsdram->State = HAL_SDRAM_STATE_READY;
00575
00576     /* Process Unlocked */
00577     __HAL_UNLOCK(hsdram);
00578   }
00579   else
00580   {
00581     return  HAL_ERROR;
00582   }
00583
00584   return HAL_OK;
00585 }
00586
00587 /**
00588   * @brief  Reads 32-bit data buffer from the SDRAM memory.
00589   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00590   *                the configuration information for SDRAM module.
00591   * @param  pAddress Pointer to read start address
00592   * @param  pDstBuffer Pointer to destination buffer
00593   * @param  BufferSize Size of the buffer to read from memory
00594   * @retval HAL status
00595   */
00596 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00597 {
00598   uint32_t size;
00599   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00600   uint32_t * pdestbuff = pDstBuffer;
00601   HAL_SDRAM_StateTypeDef state = hsdram->State;
00602
00603   /* Check the SDRAM controller state */
00604   if (state == HAL_SDRAM_STATE_BUSY)
00605   {
00606     return HAL_BUSY;
00607   }
00608   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00609   {
00610     /* Process Locked */
00611     __HAL_LOCK(hsdram);
00612
00613     /* Update the SDRAM controller state */
00614     hsdram->State = HAL_SDRAM_STATE_BUSY;
00615
00616     /* Read data from source */
00617     for (size = BufferSize; size != 0U; size--)
00618     {
00619       *pdestbuff = *(__IO uint32_t *)pSdramAddress;
00620       pdestbuff++;
00621       pSdramAddress++;
00622     }
00623
00624     /* Update the SDRAM controller state */
00625     hsdram->State = state;
00626
00627     /* Process Unlocked */
00628     __HAL_UNLOCK(hsdram);
00629   }
00630   else
00631   {
00632     return  HAL_ERROR;
00633   }
00634
00635   return HAL_OK;
00636 }
00637
00638 /**
00639   * @brief  Writes 32-bit data buffer to SDRAM memory.
00640   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00641   *                the configuration information for SDRAM module.
00642   * @param  pAddress Pointer to write start address
00643   * @param  pSrcBuffer Pointer to source buffer to write
00644   * @param  BufferSize Size of the buffer to write to memory
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00648 {
00649   uint32_t size;
00650   __IO uint32_t *pSdramAddress = pAddress;
00651   uint32_t * psrcbuff = pSrcBuffer;
00652
00653   /* Check the SDRAM controller state */
00654   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
00655   {
00656     return HAL_BUSY;
00657   }
00658   else if (hsdram->State == HAL_SDRAM_STATE_READY)
00659   {
00660     /* Process Locked */
00661     __HAL_LOCK(hsdram);
00662
00663     /* Update the SDRAM controller state */
00664     hsdram->State = HAL_SDRAM_STATE_BUSY;
00665
00666     /* Write data to memory */
00667     for (size = BufferSize; size != 0U; size--)
00668     {
00669       *pSdramAddress = *psrcbuff;
00670       psrcbuff++;
00671       pSdramAddress++;
00672     }
00673
00674     /* Update the SDRAM controller state */
00675     hsdram->State = HAL_SDRAM_STATE_READY;
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(hsdram);
00679   }
00680   else
00681   {
00682     return  HAL_ERROR;
00683   }
00684
00685   return HAL_OK;
00686 }
00687
00688 /**
00689   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
00690   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00691   *                the configuration information for SDRAM module.
00692   * @param  pAddress Pointer to read start address
00693   * @param  pDstBuffer Pointer to destination buffer
00694   * @param  BufferSize Size of the buffer to read from memory
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00698 {
00699   HAL_StatusTypeDef status;
00700   HAL_SDRAM_StateTypeDef state = hsdram->State;
00701
00702   /* Check the SDRAM controller state */
00703   if (state == HAL_SDRAM_STATE_BUSY)
00704   {
00705     return HAL_BUSY;
00706   }
00707   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00708   {
00709     /* Process Locked */
00710     __HAL_LOCK(hsdram);
00711
00712     /* Update the SDRAM controller state */
00713     hsdram->State = HAL_SDRAM_STATE_BUSY;
00714
00715     /* Configure DMA user callbacks */
00716     if (state == HAL_SDRAM_STATE_READY)
00717     {
00718       hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
00719     }
00720     else
00721     {
00722       hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt;
00723     }
00724     hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
00725
00726         /* Enable the DMA Stream */
00727     status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
00728
00729     /* Process Unlocked */
00730     __HAL_UNLOCK(hsdram);
00731   }
00732   else
00733   {
00734     return HAL_ERROR;
00735   }
00736
00737   return status;
00738 }
00739
00740 /**
00741   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
00742   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
00743   *                the configuration information for SDRAM module.
00744   * @param  pAddress Pointer to write start address
00745   * @param  pSrcBuffer Pointer to source buffer to write
00746   * @param  BufferSize Size of the buffer to write to memory
00747   * @retval HAL status
00748   */
00749 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00750 {
00751   HAL_StatusTypeDef status;
00752
00753   /* Check the SDRAM controller state */
00754   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
00755   {
00756     return HAL_BUSY;
00757   }
00758   else if (hsdram->State == HAL_SDRAM_STATE_READY)
00759   {
00760     /* Process Locked */
00761     __HAL_LOCK(hsdram);
00762
00763     /* Update the SDRAM controller state */
00764     hsdram->State = HAL_SDRAM_STATE_BUSY;
00765
00766     /* Configure DMA user callbacks */
00767     hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
00768     hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
00769
00770         /* Enable the DMA Stream */
00771   status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
00772
00773     /* Process Unlocked */
00774     __HAL_UNLOCK(hsdram);
00775   }
00776   else
00777   {
00778     return HAL_ERROR;
00779   }
00780
00781   return status;
00782 }
00783
00784 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00785 /**
00786   * @brief  Register a User SDRAM Callback
00787   *         To be used instead of the weak (surcharged) predefined callback
00788   * @param hsdram : SDRAM handle
00789   * @param CallbackId : ID of the callback to be registered
00790   *        This parameter can be one of the following values:
00791   *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
00792   *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
00793   *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
00794   * @param pCallback : pointer to the Callback function
00795   * @retval status
00796   */
00797 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
00798 {
00799   HAL_StatusTypeDef status = HAL_OK;
00800   HAL_SDRAM_StateTypeDef state;
00801
00802   if(pCallback == NULL)
00803   {
00804     return HAL_ERROR;
00805   }
00806
00807   /* Process locked */
00808   __HAL_LOCK(hsdram);
00809
00810   state = hsdram->State;
00811   if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00812   {
00813     switch (CallbackId)
00814     {
00815     case HAL_SDRAM_MSP_INIT_CB_ID :
00816       hsdram->MspInitCallback = pCallback;
00817       break;
00818     case HAL_SDRAM_MSP_DEINIT_CB_ID :
00819       hsdram->MspDeInitCallback = pCallback;
00820       break;
00821     case HAL_SDRAM_REFRESH_ERR_CB_ID :
00822       hsdram->RefreshErrorCallback = pCallback;
00823       break;
00824     default :
00825       /* update return status */
00826       status =  HAL_ERROR;
00827       break;
00828     }
00829   }
00830   else if(hsdram->State == HAL_SDRAM_STATE_RESET)
00831   {
00832     switch (CallbackId)
00833     {
00834     case HAL_SDRAM_MSP_INIT_CB_ID :
00835       hsdram->MspInitCallback = pCallback;
00836       break;
00837     case HAL_SDRAM_MSP_DEINIT_CB_ID :
00838       hsdram->MspDeInitCallback = pCallback;
00839       break;
00840     default :
00841       /* update return status */
00842       status =  HAL_ERROR;
00843       break;
00844     }
00845   }
00846   else
00847   {
00848     /* update return status */
00849     status =  HAL_ERROR;
00850   }
00851
00852   /* Release Lock */
00853   __HAL_UNLOCK(hsdram);
00854   return status;
00855 }
00856
00857 /**
00858   * @brief  Unregister a User SDRAM Callback
00859   *         SDRAM Callback is redirected to the weak (surcharged) predefined callback
00860   * @param hsdram : SDRAM handle
00861   * @param CallbackId : ID of the callback to be unregistered
00862   *        This parameter can be one of the following values:
00863   *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
00864   *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
00865   *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
00866   *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
00867   *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
00868   * @retval status
00869   */
00870 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
00871 {
00872   HAL_StatusTypeDef status = HAL_OK;
00873   HAL_SDRAM_StateTypeDef state;
00874
00875   /* Process locked */
00876   __HAL_LOCK(hsdram);
00877
00878   state = hsdram->State;
00879   if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00880   {
00881     switch (CallbackId)
00882     {
00883     case HAL_SDRAM_MSP_INIT_CB_ID :
00884       hsdram->MspInitCallback = HAL_SDRAM_MspInit;
00885       break;
00886     case HAL_SDRAM_MSP_DEINIT_CB_ID :
00887       hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
00888       break;
00889     case HAL_SDRAM_REFRESH_ERR_CB_ID :
00890       hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
00891       break;
00892     case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
00893       hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
00894       break;
00895     case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
00896       hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00897       break;
00898     default :
00899       /* update return status */
00900       status =  HAL_ERROR;
00901       break;
00902     }
00903   }
00904   else if(hsdram->State == HAL_SDRAM_STATE_RESET)
00905   {
00906     switch (CallbackId)
00907     {
00908     case HAL_SDRAM_MSP_INIT_CB_ID :
00909       hsdram->MspInitCallback = HAL_SDRAM_MspInit;
00910       break;
00911     case HAL_SDRAM_MSP_DEINIT_CB_ID :
00912       hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
00913       break;
00914     default :
00915       /* update return status */
00916       status =  HAL_ERROR;
00917       break;
00918     }
00919   }
00920   else
00921   {
00922     /* update return status */
00923     status =  HAL_ERROR;
00924   }
00925
00926   /* Release Lock */
00927   __HAL_UNLOCK(hsdram);
00928   return status;
00929 }
00930
00931 /**
00932   * @brief  Register a User SDRAM Callback for DMA transfers
00933   *         To be used instead of the weak (surcharged) predefined callback
00934   * @param hsdram : SDRAM handle
00935   * @param CallbackId : ID of the callback to be registered
00936   *        This parameter can be one of the following values:
00937   *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
00938   *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
00939   * @param pCallback : pointer to the Callback function
00940   * @retval status
00941   */
00942 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
00943 {
00944   HAL_StatusTypeDef status = HAL_OK;
00945   HAL_SDRAM_StateTypeDef state;
00946
00947   if(pCallback == NULL)
00948   {
00949     return HAL_ERROR;
00950   }
00951
00952   /* Process locked */
00953   __HAL_LOCK(hsdram);
00954
00955   state = hsdram->State;
00956   if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
00957   {
00958     switch (CallbackId)
00959     {
00960     case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
00961       hsdram->DmaXferCpltCallback = pCallback;
00962       break;
00963     case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
00964       hsdram->DmaXferErrorCallback = pCallback;
00965       break;
00966     default :
00967       /* update return status */
00968       status =  HAL_ERROR;
00969       break;
00970     }
00971   }
00972   else
00973   {
00974     /* update return status */
00975     status =  HAL_ERROR;
00976   }
00977
00978   /* Release Lock */
00979   __HAL_UNLOCK(hsdram);
00980   return status;
00981 }
00982 #endif
00983
00984 /**
00985   * @}
00986   */
00987
00988 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
00989  *  @brief   management functions
00990  *
00991 @verbatim
00992   ==============================================================================
00993                          ##### SDRAM Control functions #####
00994   ==============================================================================
00995   [..]
00996     This subsection provides a set of functions allowing to control dynamically
00997     the SDRAM interface.
00998
00999 @endverbatim
01000   * @{
01001   */
01002
01003 /**
01004   * @brief  Enables dynamically SDRAM write protection.
01005   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01006   *                the configuration information for SDRAM module.
01007   * @retval HAL status
01008   */
01009 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
01010 {
01011   /* Check the SDRAM controller state */
01012   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
01013   {
01014     return HAL_BUSY;
01015   }
01016   else if (hsdram->State == HAL_SDRAM_STATE_READY)
01017   {
01018     /* Update the SDRAM state */
01019     hsdram->State = HAL_SDRAM_STATE_BUSY;
01020
01021     /* Enable write protection */
01022     (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
01023
01024     /* Update the SDRAM state */
01025     hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
01026   }
01027   else
01028   {
01029     return HAL_ERROR;
01030   }
01031
01032   return HAL_OK;
01033 }
01034
01035 /**
01036   * @brief  Disables dynamically SDRAM write protection.
01037   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01038   *                the configuration information for SDRAM module.
01039   * @retval HAL status
01040   */
01041 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
01042 {
01043   HAL_SDRAM_StateTypeDef state = hsdram->State;
01044
01045   /* Check the SDRAM controller state */
01046   if (state == HAL_SDRAM_STATE_BUSY)
01047   {
01048     return HAL_BUSY;
01049   }
01050   else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
01051   {
01052     /* Update the SDRAM state */
01053     hsdram->State = HAL_SDRAM_STATE_BUSY;
01054
01055     /* Disable write protection */
01056     (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
01057
01058     /* Update the SDRAM state */
01059     hsdram->State = HAL_SDRAM_STATE_READY;
01060   }
01061   else
01062   {
01063     return HAL_ERROR;
01064   }
01065
01066   return HAL_OK;
01067 }
01068
01069 /**
01070   * @brief  Sends Command to the SDRAM bank.
01071   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01072   *                the configuration information for SDRAM module.
01073   * @param  Command SDRAM command structure
01074   * @param  Timeout Timeout duration
01075   * @retval HAL status
01076   */
01077 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
01078 {
01079   HAL_SDRAM_StateTypeDef state = hsdram->State;
01080
01081   /* Check the SDRAM controller state */
01082   if (state == HAL_SDRAM_STATE_BUSY)
01083   {
01084     return HAL_BUSY;
01085   }
01086   else if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
01087   {
01088     /* Update the SDRAM state */
01089     hsdram->State = HAL_SDRAM_STATE_BUSY;
01090
01091     /* Send SDRAM command */
01092     (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
01093
01094     /* Update the SDRAM controller state state */
01095     if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
01096     {
01097       hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
01098     }
01099     else
01100     {
01101       hsdram->State = HAL_SDRAM_STATE_READY;
01102     }
01103   }
01104   else
01105   {
01106     return HAL_ERROR;
01107   }
01108
01109   return HAL_OK;
01110 }
01111
01112 /**
01113   * @brief  Programs the SDRAM Memory Refresh rate.
01114   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01115   *                the configuration information for SDRAM module.
01116   * @param  RefreshRate The SDRAM refresh rate value
01117   * @retval HAL status
01118   */
01119 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
01120 {
01121   /* Check the SDRAM controller state */
01122   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
01123   {
01124     return HAL_BUSY;
01125   }
01126   else if (hsdram->State == HAL_SDRAM_STATE_READY)
01127   {
01128     /* Update the SDRAM state */
01129     hsdram->State = HAL_SDRAM_STATE_BUSY;
01130
01131     /* Program the refresh rate */
01132     (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
01133
01134     /* Update the SDRAM state */
01135     hsdram->State = HAL_SDRAM_STATE_READY;
01136   }
01137   else
01138   {
01139     return HAL_ERROR;
01140   }
01141
01142   return HAL_OK;
01143 }
01144
01145 /**
01146   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
01147   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01148   *                the configuration information for SDRAM module.
01149   * @param  AutoRefreshNumber The SDRAM auto Refresh number
01150   * @retval HAL status
01151   */
01152 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
01153 {
01154   /* Check the SDRAM controller state */
01155   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
01156   {
01157     return HAL_BUSY;
01158   }
01159   else if (hsdram->State == HAL_SDRAM_STATE_READY)
01160   {
01161     /* Update the SDRAM state */
01162     hsdram->State = HAL_SDRAM_STATE_BUSY;
01163
01164     /* Set the Auto-Refresh number */
01165     (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
01166
01167     /* Update the SDRAM state */
01168     hsdram->State = HAL_SDRAM_STATE_READY;
01169   }
01170   else
01171   {
01172     return HAL_ERROR;
01173   }
01174
01175   return HAL_OK;
01176 }
01177
01178 /**
01179   * @brief  Returns the SDRAM memory current mode.
01180   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01181   *                the configuration information for SDRAM module.
01182   * @retval The SDRAM memory mode.
01183   */
01184 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
01185 {
01186   /* Return the SDRAM memory current mode */
01187   return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
01188 }
01189
01190 /**
01191   * @}
01192   */
01193
01194 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
01195  *  @brief   Peripheral State functions
01196  *
01197 @verbatim
01198   ==============================================================================
01199                       ##### SDRAM State functions #####
01200   ==============================================================================
01201   [..]
01202     This subsection permits to get in run-time the status of the SDRAM controller
01203     and the data flow.
01204
01205 @endverbatim
01206   * @{
01207   */
01208
01209 /**
01210   * @brief  Returns the SDRAM state.
01211   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
01212   *                the configuration information for SDRAM module.
01213   * @retval HAL state
01214   */
01215 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
01216 {
01217   return hsdram->State;
01218 }
01219
01220 /**
01221   * @}
01222   */
01223
01224 /**
01225   * @}
01226   */
01227
01228 /**
01229   @cond 0
01230   */
01231 /**
01232   * @brief  MDMA SDRAM process complete callback.
01233   * @param  hmdma : MDMA handle
01234   * @retval None
01235   */
01236 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
01237 {
01238   SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
01239
01240   /* Disable the MDMA channel */
01241   __HAL_MDMA_DISABLE(hmdma);
01242
01243   /* Update the SDRAM controller state */
01244   hsdram->State = HAL_SDRAM_STATE_READY;
01245
01246 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
01247   hsdram->DmaXferCpltCallback(hmdma);
01248 #else
01249   HAL_SDRAM_DMA_XferCpltCallback(hmdma);
01250 #endif
01251 }
01252
01253 /**
01254   * @brief  MDMA SRAM process complete callback.
01255   * @param  hmdma : MDMA handle
01256   * @retval None
01257   */
01258 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
01259 {
01260   SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
01261
01262   /* Disable the MDMA channel */
01263   __HAL_MDMA_DISABLE(hmdma);
01264
01265   /* Update the SDRAM controller state */
01266   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
01267
01268 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
01269   hsdram->DmaXferCpltCallback(hmdma);
01270 #else
01271   HAL_SDRAM_DMA_XferCpltCallback(hmdma);
01272 #endif
01273 }
01274
01275 /**
01276   * @brief  MDMA SDRAM error callback.
01277   * @param  hmdma : MDMA handle
01278   * @retval None
01279   */
01280 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
01281 {
01282   SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
01283
01284   /* Disable the MDMA channel */
01285   __HAL_MDMA_DISABLE(hmdma);
01286
01287   /* Update the SDRAM controller state */
01288   hsdram->State = HAL_SDRAM_STATE_ERROR;
01289
01290 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
01291   hsdram->DmaXferErrorCallback(hmdma);
01292 #else
01293   HAL_SDRAM_DMA_XferErrorCallback(hmdma);
01294 #endif
01295 }
01296 /**
01297   @endcond
01298   */
01299
01300 /**
01301   * @}
01302   */
01303
01304 #endif /* HAL_SDRAM_MODULE_ENABLED */
01305
01306 /**
01307   * @}
01308   */
01309
01310
01311 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sdram.h Source File

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stm32h7xx_hal_sdram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sdram.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SDRAM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   *
00011   * This software component is licensed by ST under BSD 3-Clause license,
00012   * the "License"; You may not use this file except in compliance with the
00013   * License. You may obtain a copy of the License at:
00014   *                       opensource.org/licenses/BSD-3-Clause
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32H7xx_HAL_SDRAM_H
00021 #define STM32H7xx_HAL_SDRAM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_fmc.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SDRAM
00036   * @{
00037   */
00038
00039 /* Exported typedef ----------------------------------------------------------*/
00040
00041 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL SDRAM State structure definition
00047   */
00048 typedef enum
00049 {
00050   HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */
00051   HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */
00052   HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */
00053   HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */
00054   HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */
00055   HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */
00056
00057 } HAL_SDRAM_StateTypeDef;
00058
00059 /**
00060   * @brief  SDRAM handle Structure definition
00061   */
00062 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00063 typedef struct __SDRAM_HandleTypeDef
00064 #else
00065 typedef struct
00066 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS  */
00067 {
00068   FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
00069
00070   FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
00071
00072   __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
00073
00074   HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
00075
00076   MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                   */
00077
00078 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00079   void  (* MspInitCallback)        ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Msp Init callback              */
00080   void  (* MspDeInitCallback)      ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Msp DeInit callback            */
00081   void  (* RefreshErrorCallback)   ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Refresh Error callback         */
00082   void  (* DmaXferCpltCallback)    ( MDMA_HandleTypeDef * hmdma);                 /*!< SDRAM DMA Xfer Complete callback     */
00083   void  (* DmaXferErrorCallback)   ( MDMA_HandleTypeDef * hmdma);                 /*!< SDRAM DMA Xfer Error callback        */
00084 #endif
00085 } SDRAM_HandleTypeDef;
00086
00087 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00088 /**
00089   * @brief  HAL SDRAM Callback ID enumeration definition
00090   */
00091 typedef enum
00092 {
00093   HAL_SDRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SDRAM MspInit Callback ID           */
00094   HAL_SDRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SDRAM MspDeInit Callback ID         */
00095   HAL_SDRAM_REFRESH_ERR_CB_ID    = 0x02U,  /*!< SDRAM Refresh Error Callback ID     */
00096   HAL_SDRAM_DMA_XFER_CPLT_CB_ID  = 0x03U,  /*!< SDRAM DMA Xfer Complete Callback ID */
00097   HAL_SDRAM_DMA_XFER_ERR_CB_ID   = 0x04U   /*!< SDRAM DMA Xfer Error Callback ID    */
00098 }HAL_SDRAM_CallbackIDTypeDef;
00099
00100 /**
00101   * @brief  HAL SDRAM Callback pointer definition
00102   */
00103 typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
00104 typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
00105 #endif
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported constants --------------------------------------------------------*/
00111 /* Exported macro ------------------------------------------------------------*/
00112
00113 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
00114   * @{
00115   */
00116
00117 /** @brief Reset SDRAM handle state
00118   * @param  __HANDLE__ specifies the SDRAM handle.
00119   * @retval None
00120   */
00121 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00122 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)        do {                                               \
00123                                                                (__HANDLE__)->State = HAL_SDRAM_STATE_RESET;  \
00124                                                                (__HANDLE__)->MspInitCallback = NULL;         \
00125                                                                (__HANDLE__)->MspDeInitCallback = NULL;       \
00126                                                              } while(0)
00127 #else
00128 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
00129 #endif
00130 /**
00131   * @}
00132   */
00133
00134 /* Exported functions --------------------------------------------------------*/
00135
00136 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
00137   * @{
00138   */
00139
00140 /** @addtogroup SDRAM_Exported_Functions_Group1
00141   * @{
00142   */
00143
00144 /* Initialization/de-initialization functions *********************************/
00145 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
00146 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
00147 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
00148 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
00149
00150 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
00151 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
00152 void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
00153 void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
00154
00155 /**
00156   * @}
00157   */
00158
00159 /** @addtogroup SDRAM_Exported_Functions_Group2
00160   * @{
00161   */
00162 /* I/O operation functions ****************************************************/
00163 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00164 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00165 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00166 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00167 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00168 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00169
00170 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00171 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00172
00173 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
00174 /* SDRAM callback registering/unregistering */
00175 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);
00176 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
00177 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);
00178 #endif
00179
00180 /**
00181   * @}
00182   */
00183
00184 /** @addtogroup SDRAM_Exported_Functions_Group3
00185   * @{
00186   */
00187 /* SDRAM Control functions  *****************************************************/
00188 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
00189 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
00190 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
00191 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
00192 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
00193 uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
00194
00195 /**
00196   * @}
00197   */
00198
00199 /** @addtogroup SDRAM_Exported_Functions_Group4
00200   * @{
00201   */
00202 /* SDRAM State functions ********************************************************/
00203 HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
00204 /**
00205   * @}
00206   */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220
00221 #ifdef __cplusplus
00222 }
00223 #endif
00224
00225 #endif /* STM32H7xx_HAL_SDRAM_H */
00226
00227 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:01 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard.c Source File

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stm32h7xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the SMARTCARD peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     The SMARTCARD HAL driver can be used as follows:
00019
00020     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00021     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00022     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00023         (++) Enable the USARTx interface clock.
00024         (++) USART pins configuration:
00025              (+++) Enable the clock for the USART GPIOs.
00026              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00027         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00028              and HAL_SMARTCARD_Receive_IT() APIs):
00029              (+++) Configure the USARTx interrupt priority.
00030              (+++) Enable the NVIC USART IRQ handle.
00031         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00032              and HAL_SMARTCARD_Receive_DMA() APIs):
00033              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034              (+++) Enable the DMAx interface clock.
00035              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036              (+++) Configure the DMA Tx/Rx channel.
00037              (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00038              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00039
00040     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00041         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00042         error enabling or disabling in the hsmartcard handle Init structure.
00043
00044     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00045         in the hsmartcard handle AdvancedInit structure.
00046
00047     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00048         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049              by calling the customized HAL_SMARTCARD_MspInit() API.
00050         [..]
00051         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00052              RXNE interrupt and Error Interrupts) will be managed using the macros
00053              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00054
00055     [..]
00056     [..] Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00068        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00071        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00080        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00083        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00087
00088      *** SMARTCARD HAL driver macros list ***
00089      ========================================
00090      [..]
00091        Below the list of most used macros in SMARTCARD HAL driver.
00092
00093        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00094        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00095        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00096        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00097        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00098
00099      [..]
00100        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00101
00102     ##### Callback registration #####
00103     ==================================
00104
00105     [..]
00106     The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
00107     allows the user to configure dynamically the driver callbacks.
00108
00109     [..]
00110     Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
00111     Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
00112     (+) TxCpltCallback            : Tx Complete Callback.
00113     (+) RxCpltCallback            : Rx Complete Callback.
00114     (+) ErrorCallback             : Error Callback.
00115     (+) AbortCpltCallback         : Abort Complete Callback.
00116     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00117     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00118     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00119     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00120     (+) MspInitCallback           : SMARTCARD MspInit.
00121     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00122     This function takes as parameters the HAL peripheral handle, the Callback ID
00123     and a pointer to the user callback function.
00124
00125     [..]
00126     Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
00127     weak (surcharged) function.
00128     @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00129     and the Callback ID.
00130     This function allows to reset following callbacks:
00131     (+) TxCpltCallback            : Tx Complete Callback.
00132     (+) RxCpltCallback            : Rx Complete Callback.
00133     (+) ErrorCallback             : Error Callback.
00134     (+) AbortCpltCallback         : Abort Complete Callback.
00135     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00136     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00137     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00138     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00139     (+) MspInitCallback           : SMARTCARD MspInit.
00140     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00141
00142     [..]
00143     By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
00144     all callbacks are set to the corresponding weak (surcharged) functions:
00145     examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
00146     Exception done for MspInit and MspDeInit functions that are respectively
00147     reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
00148     and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
00149     If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
00150     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00151
00152     [..]
00153     Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
00154     Exception done MspInit/MspDeInit that can be registered/unregistered
00155     in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
00156     MspInit/DeInit callbacks can be used during the Init/DeInit.
00157     In that case first register the MspInit/MspDeInit user callbacks
00158     using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
00159     or @ref HAL_SMARTCARD_Init() function.
00160
00161     [..]
00162     When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
00163     not defined, the callback registration feature is not available
00164     and weak (surcharged) callbacks are used.
00165
00166
00167   @endverbatim
00168   ******************************************************************************
00169   * @attention
00170   *
00171   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00172   * All rights reserved.</center></h2>
00173   *
00174   * This software component is licensed by ST under BSD 3-Clause license,
00175   * the "License"; You may not use this file except in compliance with the
00176   * License. You may obtain a copy of the License at:
00177   *                        opensource.org/licenses/BSD-3-Clause
00178   *
00179   ******************************************************************************
00180   */
00181
00182 /* Includes ------------------------------------------------------------------*/
00183 #include "stm32h7xx_hal.h"
00184
00185 /** @addtogroup STM32H7xx_HAL_Driver
00186   * @{
00187   */
00188
00189 /** @defgroup SMARTCARD SMARTCARD
00190   * @brief HAL SMARTCARD module driver
00191   * @{
00192   */
00193
00194 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00195
00196 /* Private typedef -----------------------------------------------------------*/
00197 /* Private define ------------------------------------------------------------*/
00198 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00199   * @{
00200   */
00201 #define SMARTCARD_TEACK_REACK_TIMEOUT               1000U      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
00202
00203 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS   | \
00204                                           USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
00205                                           USART_CR1_FIFOEN ))                                         /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00206
00207 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
00208                                           USART_CR2_LBCL))                                            /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00209
00210 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))   /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00211
00212 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
00213                                           USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))                    /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00214
00215 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00216
00217 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00218 /**
00219   * @}
00220   */
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /* Private variables ---------------------------------------------------------*/
00224 /* Private function prototypes -----------------------------------------------*/
00225 /** @addtogroup SMARTCARD_Private_Functions
00226   * @{
00227   */
00228 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00229 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
00230 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00231 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00232 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00233 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00234 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
00235                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00236 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00237 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00238 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00239 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00240 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00241 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00242 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00243 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00244 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00245 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00246 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00247 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00248 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00249 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00250 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00251 /**
00252   * @}
00253   */
00254
00255 /* Exported functions --------------------------------------------------------*/
00256
00257 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00258   * @{
00259   */
00260
00261 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00262   * @brief    Initialization and Configuration functions
00263   *
00264 @verbatim
00265   ==============================================================================
00266               ##### Initialization and Configuration functions #####
00267   ==============================================================================
00268   [..]
00269   This subsection provides a set of functions allowing to initialize the USARTx
00270   associated to the SmartCard.
00271   (+) These parameters can be configured:
00272       (++) Baud Rate
00273       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00274       (++) Receiver/transmitter modes
00275       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00276       (++) Prescaler value
00277       (++) Guard bit time
00278       (++) NACK enabling or disabling on transmission error
00279
00280   (+) The following advanced features can be configured as well:
00281       (++) TX and/or RX pin level inversion
00282       (++) data logical level inversion
00283       (++) RX and TX pins swap
00284       (++) RX overrun detection disabling
00285       (++) DMA disabling on RX error
00286       (++) MSB first on communication line
00287       (++) Time out enabling (and if activated, timeout value)
00288       (++) Block length
00289       (++) Auto-retry counter
00290   [..]
00291   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00292   (details for the procedures are available in reference manual).
00293
00294 @endverbatim
00295
00296   The USART frame format is given in the following table:
00297
00298     Table 1. USART frame format.
00299     +---------------------------------------------------------------+
00300     | M1M0 bits |  PCE bit  |            USART frame                |
00301     |-----------------------|---------------------------------------|
00302     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00303     +---------------------------------------------------------------+
00304
00305
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Initialize the SMARTCARD mode according to the specified
00311   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00312   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00313   *                    the configuration information for the specified SMARTCARD module.
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00317 {
00318   /* Check the SMARTCARD handle allocation */
00319   if (hsmartcard == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the USART associated to the SMARTCARD handle */
00325   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00326
00327   if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00328   {
00329     /* Allocate lock resource and initialize it */
00330     hsmartcard->Lock = HAL_UNLOCKED;
00331
00332 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00333     SMARTCARD_InitCallbacksToDefault(hsmartcard);
00334
00335     if (hsmartcard->MspInitCallback == NULL)
00336     {
00337       hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00338     }
00339
00340     /* Init the low level hardware */
00341     hsmartcard->MspInitCallback(hsmartcard);
00342 #else
00343     /* Init the low level hardware : GPIO, CLOCK */
00344     HAL_SMARTCARD_MspInit(hsmartcard);
00345 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00346   }
00347
00348   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00349
00350   /* Disable the Peripheral to set smartcard mode */
00351   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00352
00353   /* In SmartCard mode, the following bits must be kept cleared:
00354   - LINEN in the USART_CR2 register,
00355   - HDSEL and IREN  bits in the USART_CR3 register.*/
00356   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00357   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00358
00359   /* set the USART in SMARTCARD mode */
00360   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00361
00362   /* Set the SMARTCARD Communication parameters */
00363   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00364   {
00365     return HAL_ERROR;
00366   }
00367
00368   /* Set the SMARTCARD transmission completion indication */
00369   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00370
00371   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00372   {
00373     SMARTCARD_AdvFeatureConfig(hsmartcard);
00374   }
00375
00376   /* Enable the Peripheral */
00377   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00378
00379   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00380   return (SMARTCARD_CheckIdleState(hsmartcard));
00381 }
00382
00383 /**
00384   * @brief  DeInitialize the SMARTCARD peripheral.
00385   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00386   *                    the configuration information for the specified SMARTCARD module.
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00390 {
00391   /* Check the SMARTCARD handle allocation */
00392   if (hsmartcard == NULL)
00393   {
00394     return HAL_ERROR;
00395   }
00396
00397   /* Check the USART/UART associated to the SMARTCARD handle */
00398   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00399
00400   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00401
00402   /* Disable the Peripheral */
00403   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00404
00405   WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
00406   WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
00407   WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
00408   WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
00409   WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
00410
00411   /* DeInit the low level hardware */
00412 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00413   if (hsmartcard->MspDeInitCallback == NULL)
00414   {
00415     hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00416   }
00417   /* DeInit the low level hardware */
00418   hsmartcard->MspDeInitCallback(hsmartcard);
00419 #else
00420   HAL_SMARTCARD_MspDeInit(hsmartcard);
00421 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00422
00423   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00424   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00425   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00426
00427   /* Process Unlock */
00428   __HAL_UNLOCK(hsmartcard);
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief  Initialize the SMARTCARD MSP.
00435   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00436   *                    the configuration information for the specified SMARTCARD module.
00437   * @retval None
00438   */
00439 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00440 {
00441   /* Prevent unused argument(s) compilation warning */
00442   UNUSED(hsmartcard);
00443
00444   /* NOTE : This function should not be modified, when the callback is needed,
00445             the HAL_SMARTCARD_MspInit can be implemented in the user file
00446    */
00447 }
00448
00449 /**
00450   * @brief  DeInitialize the SMARTCARD MSP.
00451   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00452   *                    the configuration information for the specified SMARTCARD module.
00453   * @retval None
00454   */
00455 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00456 {
00457   /* Prevent unused argument(s) compilation warning */
00458   UNUSED(hsmartcard);
00459
00460   /* NOTE : This function should not be modified, when the callback is needed,
00461             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00462    */
00463 }
00464
00465 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00466 /**
00467   * @brief  Register a User SMARTCARD Callback
00468   *         To be used instead of the weak predefined callback
00469   * @param  hsmartcard smartcard handle
00470   * @param  CallbackID ID of the callback to be registered
00471   *         This parameter can be one of the following values:
00472   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00473   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00474   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00475   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00476   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00477   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00478   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00479   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00480   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00481   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00482   * @param  pCallback pointer to the Callback function
00483   * @retval HAL status
00484   */
00485 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00486                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
00487 {
00488   HAL_StatusTypeDef status = HAL_OK;
00489
00490   if (pCallback == NULL)
00491   {
00492     /* Update the error code */
00493     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00494
00495     return HAL_ERROR;
00496   }
00497   /* Process locked */
00498   __HAL_LOCK(hsmartcard);
00499
00500   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00501   {
00502     switch (CallbackID)
00503     {
00504
00505       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00506         hsmartcard->TxCpltCallback = pCallback;
00507         break;
00508
00509       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00510         hsmartcard->RxCpltCallback = pCallback;
00511         break;
00512
00513       case HAL_SMARTCARD_ERROR_CB_ID :
00514         hsmartcard->ErrorCallback = pCallback;
00515         break;
00516
00517       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00518         hsmartcard->AbortCpltCallback = pCallback;
00519         break;
00520
00521       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00522         hsmartcard->AbortTransmitCpltCallback = pCallback;
00523         break;
00524
00525       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00526         hsmartcard->AbortReceiveCpltCallback = pCallback;
00527         break;
00528
00529       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00530         hsmartcard->RxFifoFullCallback = pCallback;
00531         break;
00532
00533       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00534         hsmartcard->TxFifoEmptyCallback = pCallback;
00535         break;
00536
00537       case HAL_SMARTCARD_MSPINIT_CB_ID :
00538         hsmartcard->MspInitCallback = pCallback;
00539         break;
00540
00541       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00542         hsmartcard->MspDeInitCallback = pCallback;
00543         break;
00544
00545       default :
00546         /* Update the error code */
00547         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00548
00549         /* Return error status */
00550         status =  HAL_ERROR;
00551         break;
00552     }
00553   }
00554   else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00555   {
00556     switch (CallbackID)
00557     {
00558       case HAL_SMARTCARD_MSPINIT_CB_ID :
00559         hsmartcard->MspInitCallback = pCallback;
00560         break;
00561
00562       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00563         hsmartcard->MspDeInitCallback = pCallback;
00564         break;
00565
00566       default :
00567         /* Update the error code */
00568         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00569
00570         /* Return error status */
00571         status =  HAL_ERROR;
00572         break;
00573     }
00574   }
00575   else
00576   {
00577     /* Update the error code */
00578     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00579
00580     /* Return error status */
00581     status =  HAL_ERROR;
00582   }
00583
00584   /* Release Lock */
00585   __HAL_UNLOCK(hsmartcard);
00586
00587   return status;
00588 }
00589
00590 /**
00591   * @brief  Unregister an SMARTCARD callback
00592   *         SMARTCARD callback is redirected to the weak predefined callback
00593   * @param  hsmartcard smartcard handle
00594   * @param  CallbackID ID of the callback to be unregistered
00595   *         This parameter can be one of the following values:
00596   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00597   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00598   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00599   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00600   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00601   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00602   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00603   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00604   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00605   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00609                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
00610 {
00611   HAL_StatusTypeDef status = HAL_OK;
00612
00613   /* Process locked */
00614   __HAL_LOCK(hsmartcard);
00615
00616   if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
00617   {
00618     switch (CallbackID)
00619     {
00620       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00621         hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00622         break;
00623
00624       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00625         hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00626         break;
00627
00628       case HAL_SMARTCARD_ERROR_CB_ID :
00629         hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00630         break;
00631
00632       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00633         hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00634         break;
00635
00636       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00637         hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00638         break;
00639
00640       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00641         hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00642         break;
00643
00644       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00645         hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00646         break;
00647
00648       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00649         hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00650         break;
00651
00652       case HAL_SMARTCARD_MSPINIT_CB_ID :
00653         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                             /* Legacy weak MspInitCallback           */
00654         break;
00655
00656       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00657         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00658         break;
00659
00660       default :
00661         /* Update the error code */
00662         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00663
00664         /* Return error status */
00665         status =  HAL_ERROR;
00666         break;
00667     }
00668   }
00669   else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
00670   {
00671     switch (CallbackID)
00672     {
00673       case HAL_SMARTCARD_MSPINIT_CB_ID :
00674         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00675         break;
00676
00677       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00678         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00679         break;
00680
00681       default :
00682         /* Update the error code */
00683         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00684
00685         /* Return error status */
00686         status =  HAL_ERROR;
00687         break;
00688     }
00689   }
00690   else
00691   {
00692     /* Update the error code */
00693     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00694
00695     /* Return error status */
00696     status =  HAL_ERROR;
00697   }
00698
00699   /* Release Lock */
00700   __HAL_UNLOCK(hsmartcard);
00701
00702   return status;
00703 }
00704 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00705
00706 /**
00707   * @}
00708   */
00709
00710 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00711   * @brief    SMARTCARD Transmit and Receive functions
00712   *
00713 @verbatim
00714   ==============================================================================
00715                          ##### IO operation functions #####
00716   ==============================================================================
00717   [..]
00718     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00719
00720   [..]
00721     Smartcard is a single wire half duplex communication protocol.
00722     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00723     defined in the ISO 7816-3 standard. The USART should be configured as:
00724     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00725     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00726
00727   [..]
00728     (+) There are two modes of transfer:
00729         (++) Blocking mode: The communication is performed in polling mode.
00730              The HAL status of all data processing is returned by the same function
00731              after finishing transfer.
00732         (++) Non-Blocking mode: The communication is performed using Interrupts
00733              or DMA, the relevant API's return the HAL status.
00734              The end of the data processing will be indicated through the
00735              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00736              using DMA mode.
00737         (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00738              will be executed respectively at the end of the Transmit or Receive process
00739              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00740              error is detected.
00741
00742     (+) Blocking mode APIs are :
00743         (++) HAL_SMARTCARD_Transmit()
00744         (++) HAL_SMARTCARD_Receive()
00745
00746     (+) Non Blocking mode APIs with Interrupt are :
00747         (++) HAL_SMARTCARD_Transmit_IT()
00748         (++) HAL_SMARTCARD_Receive_IT()
00749         (++) HAL_SMARTCARD_IRQHandler()
00750
00751     (+) Non Blocking mode functions with DMA are :
00752         (++) HAL_SMARTCARD_Transmit_DMA()
00753         (++) HAL_SMARTCARD_Receive_DMA()
00754
00755     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00756         (++) HAL_SMARTCARD_TxCpltCallback()
00757         (++) HAL_SMARTCARD_RxCpltCallback()
00758         (++) HAL_SMARTCARD_ErrorCallback()
00759
00760   [..]
00761     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00762         (++) HAL_SMARTCARD_Abort()
00763         (++) HAL_SMARTCARD_AbortTransmit()
00764         (++) HAL_SMARTCARD_AbortReceive()
00765         (++) HAL_SMARTCARD_Abort_IT()
00766         (++) HAL_SMARTCARD_AbortTransmit_IT()
00767         (++) HAL_SMARTCARD_AbortReceive_IT()
00768
00769     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00770         (++) HAL_SMARTCARD_AbortCpltCallback()
00771         (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
00772         (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
00773
00774     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00775         Errors are handled as follows :
00776        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00777             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00778             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00779             and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00780             If user wants to abort it, Abort services should be called by user.
00781        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00782             This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
00783             Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00784
00785 @endverbatim
00786   * @{
00787   */
00788
00789 /**
00790   * @brief  Send an amount of data in blocking mode.
00791   * @note   When FIFO mode is enabled, writing a data in the TDR register adds one
00792   *         data to the TXFIFO. Write operations to the TDR register are performed
00793   *         when TXFNF flag is set. From hardware perspective, TXFNF flag and
00794   *         TXE are mapped on the same bit-field.
00795   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00796   *                    the configuration information for the specified SMARTCARD module.
00797   * @param  pData pointer to data buffer.
00798   * @param  Size amount of data to be sent.
00799   * @param  Timeout  Timeout duration.
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
00803                                          uint32_t Timeout)
00804 {
00805   uint32_t tickstart;
00806   uint8_t  *ptmpdata = pData;
00807
00808   /* Check that a Tx process is not already ongoing */
00809   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00810   {
00811     if ((ptmpdata == NULL) || (Size == 0U))
00812     {
00813       return  HAL_ERROR;
00814     }
00815
00816     /* Process Locked */
00817     __HAL_LOCK(hsmartcard);
00818
00819     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00820
00821     /* Init tickstart for timeout management */
00822     tickstart = HAL_GetTick();
00823
00824     /* Disable the Peripheral first to update mode for TX master */
00825     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00826
00827     /* Disable Rx, enable Tx */
00828     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00829     SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
00830     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00831
00832     /* Enable the Peripheral */
00833     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00834
00835     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00836     hsmartcard->TxXferSize = Size;
00837     hsmartcard->TxXferCount = Size;
00838
00839     while (hsmartcard->TxXferCount > 0U)
00840     {
00841       hsmartcard->TxXferCount--;
00842       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00843       {
00844         return HAL_TIMEOUT;
00845       }
00846       hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
00847       ptmpdata++;
00848     }
00849     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
00850                                          Timeout) != HAL_OK)
00851     {
00852       return HAL_TIMEOUT;
00853     }
00854     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
00855     if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00856     {
00857       /* Disable the Peripheral first to update modes */
00858       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00859       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00860       /* Enable the Peripheral */
00861       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00862     }
00863
00864     /* At end of Tx process, restore hsmartcard->gState to Ready */
00865     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00866
00867     /* Process Unlocked */
00868     __HAL_UNLOCK(hsmartcard);
00869
00870     return HAL_OK;
00871   }
00872   else
00873   {
00874     return HAL_BUSY;
00875   }
00876 }
00877
00878 /**
00879   * @brief  Receive an amount of data in blocking mode.
00880   * @note   When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00881   *         is not empty. Read operations from the RDR register are performed when
00882   *         RXFNE flag is set. From hardware perspective, RXFNE flag and
00883   *         RXNE are mapped on the same bit-field.
00884   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00885   *                    the configuration information for the specified SMARTCARD module.
00886   * @param  pData pointer to data buffer.
00887   * @param  Size amount of data to be received.
00888   * @param  Timeout Timeout duration.
00889   * @retval HAL status
00890   */
00891 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
00892                                         uint32_t Timeout)
00893 {
00894   uint32_t tickstart;
00895   uint8_t  *ptmpdata = pData;
00896
00897   /* Check that a Rx process is not already ongoing */
00898   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00899   {
00900     if ((ptmpdata == NULL) || (Size == 0U))
00901     {
00902       return  HAL_ERROR;
00903     }
00904
00905     /* Process Locked */
00906     __HAL_LOCK(hsmartcard);
00907
00908     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00909     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00910
00911     /* Init tickstart for timeout management */
00912     tickstart = HAL_GetTick();
00913
00914     hsmartcard->RxXferSize = Size;
00915     hsmartcard->RxXferCount = Size;
00916
00917     /* Check the remain data to be received */
00918     while (hsmartcard->RxXferCount > 0U)
00919     {
00920       hsmartcard->RxXferCount--;
00921
00922       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00923       {
00924         return HAL_TIMEOUT;
00925       }
00926       *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00927       ptmpdata++;
00928     }
00929
00930     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00931     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00932
00933     /* Process Unlocked */
00934     __HAL_UNLOCK(hsmartcard);
00935
00936     return HAL_OK;
00937   }
00938   else
00939   {
00940     return HAL_BUSY;
00941   }
00942 }
00943
00944 /**
00945   * @brief  Send an amount of data in interrupt mode.
00946   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
00947   *         USART_TDR register is empty, i.e one interrupt per data to transmit.
00948   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
00949   *         TXFIFO threshold reached. In that case the interrupt rate depends on
00950   *         TXFIFO threshold configuration.
00951   * @note   This function sets the hsmartcard->TxIsr function pointer according to
00952   *         the FIFO mode (data transmission processing depends on FIFO mode).
00953   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00954   *                    the configuration information for the specified SMARTCARD module.
00955   * @param  pData pointer to data buffer.
00956   * @param  Size amount of data to be sent.
00957   * @retval HAL status
00958   */
00959 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00960 {
00961   /* Check that a Tx process is not already ongoing */
00962   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00963   {
00964     if ((pData == NULL) || (Size == 0U))
00965     {
00966       return HAL_ERROR;
00967     }
00968
00969     /* Process Locked */
00970     __HAL_LOCK(hsmartcard);
00971
00972     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00973     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00974
00975     hsmartcard->pTxBuffPtr  = pData;
00976     hsmartcard->TxXferSize  = Size;
00977     hsmartcard->TxXferCount = Size;
00978     hsmartcard->TxISR       = NULL;
00979
00980     /* Disable the Peripheral first to update mode for TX master */
00981     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00982
00983     /* Disable Rx, enable Tx */
00984     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00985     SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
00986     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00987
00988     /* Enable the Peripheral */
00989     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00990
00991     /* Configure Tx interrupt processing */
00992     if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
00993     {
00994       /* Set the Tx ISR function pointer */
00995       hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
00996
00997       /* Process Unlocked */
00998       __HAL_UNLOCK(hsmartcard);
00999
01000       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01001       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01002
01003       /* Enable the TX FIFO threshold interrupt */
01004       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01005     }
01006     else
01007     {
01008       /* Set the Tx ISR function pointer */
01009       hsmartcard->TxISR = SMARTCARD_TxISR;
01010
01011       /* Process Unlocked */
01012       __HAL_UNLOCK(hsmartcard);
01013
01014       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01015       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01016
01017       /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
01018       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01019     }
01020
01021     return HAL_OK;
01022   }
01023   else
01024   {
01025     return HAL_BUSY;
01026   }
01027 }
01028
01029 /**
01030   * @brief  Receive an amount of data in interrupt mode.
01031   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
01032   *         USART_RDR register can be read, i.e one interrupt per data to receive.
01033   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
01034   *         RXFIFO threshold reached. In that case the interrupt rate depends on
01035   *         RXFIFO threshold configuration.
01036   * @note   This function sets the hsmartcard->RxIsr function pointer according to
01037   *         the FIFO mode (data reception processing depends on FIFO mode).
01038   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01039   *                    the configuration information for the specified SMARTCARD module.
01040   * @param  pData pointer to data buffer.
01041   * @param  Size amount of data to be received.
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01045 {
01046   /* Check that a Rx process is not already ongoing */
01047   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01048   {
01049     if ((pData == NULL) || (Size == 0U))
01050     {
01051       return HAL_ERROR;
01052     }
01053
01054     /* Process Locked */
01055     __HAL_LOCK(hsmartcard);
01056
01057     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01058     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01059
01060     hsmartcard->pRxBuffPtr = pData;
01061     hsmartcard->RxXferSize = Size;
01062     hsmartcard->RxXferCount = Size;
01063
01064     /* Configure Rx interrupt processing */
01065     if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
01066     {
01067       /* Set the Rx ISR function pointer */
01068       hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
01069
01070       /* Process Unlocked */
01071       __HAL_UNLOCK(hsmartcard);
01072
01073       /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
01074       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01075       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
01076     }
01077     else
01078     {
01079       /* Set the Rx ISR function pointer */
01080       hsmartcard->RxISR = SMARTCARD_RxISR;
01081
01082       /* Process Unlocked */
01083       __HAL_UNLOCK(hsmartcard);
01084
01085       /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
01086       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01087     }
01088
01089     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01090     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01091
01092     return HAL_OK;
01093   }
01094   else
01095   {
01096     return HAL_BUSY;
01097   }
01098 }
01099
01100 /**
01101   * @brief  Send an amount of data in DMA mode.
01102   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01103   *                    the configuration information for the specified SMARTCARD module.
01104   * @param  pData pointer to data buffer.
01105   * @param  Size amount of data to be sent.
01106   * @retval HAL status
01107   */
01108 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01109 {
01110   /* Check that a Tx process is not already ongoing */
01111   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01112   {
01113     if ((pData == NULL) || (Size == 0U))
01114     {
01115       return HAL_ERROR;
01116     }
01117
01118     /* Process Locked */
01119     __HAL_LOCK(hsmartcard);
01120
01121     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
01122
01123     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01124     hsmartcard->pTxBuffPtr = pData;
01125     hsmartcard->TxXferSize = Size;
01126     hsmartcard->TxXferCount = Size;
01127
01128     /* Disable the Peripheral first to update mode for TX master */
01129     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01130
01131     /* Disable Rx, enable Tx */
01132     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01133     SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
01134     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01135
01136     /* Enable the Peripheral */
01137     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01138
01139     /* Set the SMARTCARD DMA transfer complete callback */
01140     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
01141
01142     /* Set the SMARTCARD error callback */
01143     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
01144
01145     /* Set the DMA abort callback */
01146     hsmartcard->hdmatx->XferAbortCallback = NULL;
01147
01148     /* Enable the SMARTCARD transmit DMA channel */
01149     if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
01150                          Size) == HAL_OK)
01151     {
01152       /* Clear the TC flag in the ICR register */
01153       CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
01154
01155       /* Process Unlocked */
01156       __HAL_UNLOCK(hsmartcard);
01157
01158       /* Enable the UART Error Interrupt: (Frame error) */
01159       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01160
01161       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01162          in the SMARTCARD associated USART CR3 register */
01163       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01164
01165       return HAL_OK;
01166     }
01167     else
01168     {
01169       /* Set error code to DMA */
01170       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01171
01172       /* Process Unlocked */
01173       __HAL_UNLOCK(hsmartcard);
01174
01175       /* Restore hsmartcard->State to ready */
01176       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01177
01178       return HAL_ERROR;
01179     }
01180   }
01181   else
01182   {
01183     return HAL_BUSY;
01184   }
01185 }
01186
01187 /**
01188   * @brief  Receive an amount of data in DMA mode.
01189   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01190   *                    the configuration information for the specified SMARTCARD module.
01191   * @param  pData pointer to data buffer.
01192   * @param  Size amount of data to be received.
01193   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
01194   *         the received data contain the parity bit (MSB position).
01195   * @retval HAL status
01196   */
01197 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01198 {
01199   /* Check that a Rx process is not already ongoing */
01200   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01201   {
01202     if ((pData == NULL) || (Size == 0U))
01203     {
01204       return HAL_ERROR;
01205     }
01206
01207     /* Process Locked */
01208     __HAL_LOCK(hsmartcard);
01209
01210     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01211     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01212
01213     hsmartcard->pRxBuffPtr = pData;
01214     hsmartcard->RxXferSize = Size;
01215
01216     /* Set the SMARTCARD DMA transfer complete callback */
01217     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
01218
01219     /* Set the SMARTCARD DMA error callback */
01220     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
01221
01222     /* Set the DMA abort callback */
01223     hsmartcard->hdmarx->XferAbortCallback = NULL;
01224
01225     /* Enable the DMA channel */
01226     if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
01227                          Size) == HAL_OK)
01228     {
01229       /* Process Unlocked */
01230       __HAL_UNLOCK(hsmartcard);
01231
01232       /* Enable the SMARTCARD Parity Error Interrupt */
01233       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01234
01235       /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01236       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01237
01238       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01239          in the SMARTCARD associated USART CR3 register */
01240       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01241
01242       return HAL_OK;
01243     }
01244     else
01245     {
01246       /* Set error code to DMA */
01247       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01248
01249       /* Process Unlocked */
01250       __HAL_UNLOCK(hsmartcard);
01251
01252       /* Restore hsmartcard->State to ready */
01253       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01254
01255       return HAL_ERROR;
01256     }
01257   }
01258   else
01259   {
01260     return HAL_BUSY;
01261   }
01262 }
01263
01264 /**
01265   * @brief  Abort ongoing transfers (blocking mode).
01266   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01267   *                    the configuration information for the specified SMARTCARD module.
01268   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01269   *         This procedure performs following operations :
01270   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01271   *           - Disable the DMA transfer in the peripheral register (if enabled)
01272   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01273   *           - Set handle State to READY
01274   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01275   * @retval HAL status
01276   */
01277 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
01278 {
01279   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01280   CLEAR_BIT(hsmartcard->Instance->CR1,
01281             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01282              USART_CR1_EOBIE));
01283   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01284
01285   /* Disable the SMARTCARD DMA Tx request if enabled */
01286   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01287   {
01288     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01289
01290     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01291     if (hsmartcard->hdmatx != NULL)
01292     {
01293       /* Set the SMARTCARD DMA Abort callback to Null.
01294          No call back execution at end of DMA abort procedure */
01295       hsmartcard->hdmatx->XferAbortCallback = NULL;
01296
01297       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01298       {
01299         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01300         {
01301           /* Set error code to DMA */
01302           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01303
01304           return HAL_TIMEOUT;
01305         }
01306       }
01307     }
01308   }
01309
01310   /* Disable the SMARTCARD DMA Rx request if enabled */
01311   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01312   {
01313     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01314
01315     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01316     if (hsmartcard->hdmarx != NULL)
01317     {
01318       /* Set the SMARTCARD DMA Abort callback to Null.
01319          No call back execution at end of DMA abort procedure */
01320       hsmartcard->hdmarx->XferAbortCallback = NULL;
01321
01322       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01323       {
01324         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01325         {
01326           /* Set error code to DMA */
01327           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01328
01329           return HAL_TIMEOUT;
01330         }
01331       }
01332     }
01333   }
01334
01335   /* Reset Tx and Rx transfer counters */
01336   hsmartcard->TxXferCount = 0U;
01337   hsmartcard->RxXferCount = 0U;
01338
01339   /* Clear the Error flags in the ICR register */
01340   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01341                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
01342                              SMARTCARD_CLEAR_EOBF);
01343
01344   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01345   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01346   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01347
01348   /* Reset Handle ErrorCode to No Error */
01349   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01350
01351   return HAL_OK;
01352 }
01353
01354 /**
01355   * @brief  Abort ongoing Transmit transfer (blocking mode).
01356   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01357   *                    the configuration information for the specified SMARTCARD module.
01358   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01359   *         This procedure performs following operations :
01360   *           - Disable SMARTCARD Interrupts (Tx)
01361   *           - Disable the DMA transfer in the peripheral register (if enabled)
01362   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01363   *           - Set handle State to READY
01364   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01365   * @retval HAL status
01366   */
01367 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
01368 {
01369   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01370   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01371   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01372
01373   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01374   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01375   {
01376     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01377     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01378   }
01379
01380   /* Disable the SMARTCARD DMA Tx request if enabled */
01381   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01382   {
01383     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01384
01385     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01386     if (hsmartcard->hdmatx != NULL)
01387     {
01388       /* Set the SMARTCARD DMA Abort callback to Null.
01389          No call back execution at end of DMA abort procedure */
01390       hsmartcard->hdmatx->XferAbortCallback = NULL;
01391
01392       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01393       {
01394         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01395         {
01396           /* Set error code to DMA */
01397           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01398
01399           return HAL_TIMEOUT;
01400         }
01401       }
01402     }
01403   }
01404
01405   /* Reset Tx transfer counter */
01406   hsmartcard->TxXferCount = 0U;
01407
01408   /* Clear the Error flags in the ICR register */
01409   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01410
01411   /* Restore hsmartcard->gState to Ready */
01412   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01413
01414   return HAL_OK;
01415 }
01416
01417 /**
01418   * @brief  Abort ongoing Receive transfer (blocking mode).
01419   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01420   *                    the configuration information for the specified SMARTCARD module.
01421   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01422   *         This procedure performs following operations :
01423   *           - Disable SMARTCARD Interrupts (Rx)
01424   *           - Disable the DMA transfer in the peripheral register (if enabled)
01425   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01426   *           - Set handle State to READY
01427   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01428   * @retval HAL status
01429   */
01430 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
01431 {
01432   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01433   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01434   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01435
01436   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01437   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01438   {
01439     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01440     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01441   }
01442
01443   /* Disable the SMARTCARD DMA Rx request if enabled */
01444   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01445   {
01446     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01447
01448     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01449     if (hsmartcard->hdmarx != NULL)
01450     {
01451       /* Set the SMARTCARD DMA Abort callback to Null.
01452          No call back execution at end of DMA abort procedure */
01453       hsmartcard->hdmarx->XferAbortCallback = NULL;
01454
01455       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01456       {
01457         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01458         {
01459           /* Set error code to DMA */
01460           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01461
01462           return HAL_TIMEOUT;
01463         }
01464       }
01465     }
01466   }
01467
01468   /* Reset Rx transfer counter */
01469   hsmartcard->RxXferCount = 0U;
01470
01471   /* Clear the Error flags in the ICR register */
01472   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01473                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
01474                              SMARTCARD_CLEAR_EOBF);
01475
01476   /* Restore hsmartcard->RxState to Ready */
01477   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01478
01479   return HAL_OK;
01480 }
01481
01482 /**
01483   * @brief  Abort ongoing transfers (Interrupt mode).
01484   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01485   *                    the configuration information for the specified SMARTCARD module.
01486   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01487   *         This procedure performs following operations :
01488   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01489   *           - Disable the DMA transfer in the peripheral register (if enabled)
01490   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01491   *           - Set handle State to READY
01492   *           - At abort completion, call user abort complete callback
01493   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01494   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01495   * @retval HAL status
01496   */
01497 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01498 {
01499   uint32_t abortcplt = 1U;
01500
01501   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01502   CLEAR_BIT(hsmartcard->Instance->CR1,
01503             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01504              USART_CR1_EOBIE));
01505   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01506
01507   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
01508      before any call to DMA Abort functions */
01509   /* DMA Tx Handle is valid */
01510   if (hsmartcard->hdmatx != NULL)
01511   {
01512     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01513        Otherwise, set it to NULL */
01514     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01515     {
01516       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01517     }
01518     else
01519     {
01520       hsmartcard->hdmatx->XferAbortCallback = NULL;
01521     }
01522   }
01523   /* DMA Rx Handle is valid */
01524   if (hsmartcard->hdmarx != NULL)
01525   {
01526     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01527        Otherwise, set it to NULL */
01528     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01529     {
01530       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01531     }
01532     else
01533     {
01534       hsmartcard->hdmarx->XferAbortCallback = NULL;
01535     }
01536   }
01537
01538   /* Disable the SMARTCARD DMA Tx request if enabled */
01539   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01540   {
01541     /* Disable DMA Tx at UART level */
01542     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01543
01544     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01545     if (hsmartcard->hdmatx != NULL)
01546     {
01547       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01548          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01549
01550       /* Abort DMA TX */
01551       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01552       {
01553         hsmartcard->hdmatx->XferAbortCallback = NULL;
01554       }
01555       else
01556       {
01557         abortcplt = 0U;
01558       }
01559     }
01560   }
01561
01562   /* Disable the SMARTCARD DMA Rx request if enabled */
01563   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01564   {
01565     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01566
01567     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01568     if (hsmartcard->hdmarx != NULL)
01569     {
01570       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01571          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01572
01573       /* Abort DMA RX */
01574       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01575       {
01576         hsmartcard->hdmarx->XferAbortCallback = NULL;
01577         abortcplt = 1U;
01578       }
01579       else
01580       {
01581         abortcplt = 0U;
01582       }
01583     }
01584   }
01585
01586   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01587   if (abortcplt == 1U)
01588   {
01589     /* Reset Tx and Rx transfer counters */
01590     hsmartcard->TxXferCount = 0U;
01591     hsmartcard->RxXferCount = 0U;
01592
01593     /* Clear ISR function pointers */
01594     hsmartcard->RxISR = NULL;
01595     hsmartcard->TxISR = NULL;
01596
01597     /* Reset errorCode */
01598     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01599
01600     /* Clear the Error flags in the ICR register */
01601     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01602                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
01603                                SMARTCARD_CLEAR_EOBF);
01604
01605     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01606     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01607     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01608
01609     /* As no DMA to be aborted, call directly user Abort complete callback */
01610 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01611     /* Call registered Abort complete callback */
01612     hsmartcard->AbortCpltCallback(hsmartcard);
01613 #else
01614     /* Call legacy weak Abort complete callback */
01615     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01616 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01617   }
01618
01619   return HAL_OK;
01620 }
01621
01622 /**
01623   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01624   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01625   *                    the configuration information for the specified SMARTCARD module.
01626   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01627   *         This procedure performs following operations :
01628   *           - Disable SMARTCARD Interrupts (Tx)
01629   *           - Disable the DMA transfer in the peripheral register (if enabled)
01630   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01631   *           - Set handle State to READY
01632   *           - At abort completion, call user abort complete callback
01633   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01634   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01635   * @retval HAL status
01636   */
01637 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01638 {
01639   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01640   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01641   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01642
01643   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01644   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01645   {
01646     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01647     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01648   }
01649
01650   /* Disable the SMARTCARD DMA Tx request if enabled */
01651   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01652   {
01653     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01654
01655     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01656     if (hsmartcard->hdmatx != NULL)
01657     {
01658       /* Set the SMARTCARD DMA Abort callback :
01659          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01660       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01661
01662       /* Abort DMA TX */
01663       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01664       {
01665         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01666         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01667       }
01668     }
01669     else
01670     {
01671       /* Reset Tx transfer counter */
01672       hsmartcard->TxXferCount = 0U;
01673
01674       /* Clear TxISR function pointers */
01675       hsmartcard->TxISR = NULL;
01676
01677       /* Restore hsmartcard->gState to Ready */
01678       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01679
01680       /* As no DMA to be aborted, call directly user Abort complete callback */
01681 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01682       /* Call registered Abort Transmit Complete Callback */
01683       hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01684 #else
01685       /* Call legacy weak Abort Transmit Complete Callback */
01686       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01687 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01688     }
01689   }
01690   else
01691   {
01692     /* Reset Tx transfer counter */
01693     hsmartcard->TxXferCount = 0U;
01694
01695     /* Clear TxISR function pointers */
01696     hsmartcard->TxISR = NULL;
01697
01698     /* Clear the Error flags in the ICR register */
01699     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01700
01701     /* Restore hsmartcard->gState to Ready */
01702     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01703
01704     /* As no DMA to be aborted, call directly user Abort complete callback */
01705 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01706     /* Call registered Abort Transmit Complete Callback */
01707     hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01708 #else
01709     /* Call legacy weak Abort Transmit Complete Callback */
01710     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01711 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01712   }
01713
01714   return HAL_OK;
01715 }
01716
01717 /**
01718   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01719   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01720   *                    the configuration information for the specified SMARTCARD module.
01721   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01722   *         This procedure performs following operations :
01723   *           - Disable SMARTCARD Interrupts (Rx)
01724   *           - Disable the DMA transfer in the peripheral register (if enabled)
01725   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01726   *           - Set handle State to READY
01727   *           - At abort completion, call user abort complete callback
01728   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01729   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01730   * @retval HAL status
01731   */
01732 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01733 {
01734   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01735   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01736   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01737
01738   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01739   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01740   {
01741     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01742     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01743   }
01744
01745   /* Disable the SMARTCARD DMA Rx request if enabled */
01746   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01747   {
01748     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01749
01750     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01751     if (hsmartcard->hdmarx != NULL)
01752     {
01753       /* Set the SMARTCARD DMA Abort callback :
01754          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01755       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01756
01757       /* Abort DMA RX */
01758       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01759       {
01760         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01761         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01762       }
01763     }
01764     else
01765     {
01766       /* Reset Rx transfer counter */
01767       hsmartcard->RxXferCount = 0U;
01768
01769       /* Clear RxISR function pointer */
01770       hsmartcard->RxISR = NULL;
01771
01772       /* Clear the Error flags in the ICR register */
01773       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01774                                  SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
01775                                  SMARTCARD_CLEAR_EOBF);
01776
01777       /* Restore hsmartcard->RxState to Ready */
01778       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01779
01780       /* As no DMA to be aborted, call directly user Abort complete callback */
01781 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01782       /* Call registered Abort Receive Complete Callback */
01783       hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01784 #else
01785       /* Call legacy weak Abort Receive Complete Callback */
01786       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01787 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01788     }
01789   }
01790   else
01791   {
01792     /* Reset Rx transfer counter */
01793     hsmartcard->RxXferCount = 0U;
01794
01795     /* Clear RxISR function pointer */
01796     hsmartcard->RxISR = NULL;
01797
01798     /* Clear the Error flags in the ICR register */
01799     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01800                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
01801                                SMARTCARD_CLEAR_EOBF);
01802
01803     /* Restore hsmartcard->RxState to Ready */
01804     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01805
01806     /* As no DMA to be aborted, call directly user Abort complete callback */
01807 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01808     /* Call registered Abort Receive Complete Callback */
01809     hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01810 #else
01811     /* Call legacy weak Abort Receive Complete Callback */
01812     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01813 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01814   }
01815
01816   return HAL_OK;
01817 }
01818
01819 /**
01820   * @brief  Handle SMARTCARD interrupt requests.
01821   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01822   *                    the configuration information for the specified SMARTCARD module.
01823   * @retval None
01824   */
01825 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01826 {
01827   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01828   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01829   uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
01830   uint32_t errorflags;
01831   uint32_t errorcode;
01832
01833   /* If no error occurs */
01834   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01835   if (errorflags == 0U)
01836   {
01837     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01838     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01839         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01840             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01841     {
01842       if (hsmartcard->RxISR != NULL)
01843       {
01844         hsmartcard->RxISR(hsmartcard);
01845       }
01846       return;
01847     }
01848   }
01849
01850   /* If some errors occur */
01851   if ((errorflags != 0U)
01852       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
01853            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
01854   {
01855     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01856     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01857     {
01858       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01859
01860       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01861     }
01862
01863     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01864     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01865     {
01866       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01867
01868       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01869     }
01870
01871     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01872     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01873     {
01874       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01875
01876       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01877     }
01878
01879     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01880     if (((isrflags & USART_ISR_ORE) != 0U)
01881         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01882             || ((cr3its & USART_CR3_RXFTIE) != 0U)
01883             || ((cr3its & USART_CR3_EIE) != 0U)))
01884     {
01885       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01886
01887       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01888     }
01889
01890     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01891     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
01892     {
01893       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01894
01895       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01896     }
01897
01898     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01899     if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01900     {
01901       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01902       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01903           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01904               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01905       {
01906         if (hsmartcard->RxISR != NULL)
01907         {
01908           hsmartcard->RxISR(hsmartcard);
01909         }
01910       }
01911
01912       /* If Error is to be considered as blocking :
01913           - Receiver Timeout error in Reception
01914           - Overrun error in Reception
01915           - any error occurs in DMA mode reception
01916       */
01917       errorcode = hsmartcard->ErrorCode;
01918       if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01919           || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
01920       {
01921         /* Blocking error : transfer is aborted
01922            Set the SMARTCARD state ready to be able to start again the process,
01923            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01924         SMARTCARD_EndRxTransfer(hsmartcard);
01925
01926         /* Disable the SMARTCARD DMA Rx request if enabled */
01927         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01928         {
01929           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01930
01931           /* Abort the SMARTCARD DMA Rx channel */
01932           if (hsmartcard->hdmarx != NULL)
01933           {
01934             /* Set the SMARTCARD DMA Abort callback :
01935                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01936             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01937
01938             /* Abort DMA RX */
01939             if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01940             {
01941               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01942               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01943             }
01944           }
01945           else
01946           {
01947 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01948             /* Call registered user error callback */
01949             hsmartcard->ErrorCallback(hsmartcard);
01950 #else
01951             /* Call legacy weak user error callback */
01952             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01953 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01954           }
01955         }
01956         else
01957         {
01958 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01959           /* Call registered user error callback */
01960           hsmartcard->ErrorCallback(hsmartcard);
01961 #else
01962           /* Call legacy weak user error callback */
01963           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01964 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01965         }
01966       }
01967       /* other error type to be considered as blocking :
01968           - Frame error in Transmission
01969       */
01970       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01971                && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
01972       {
01973         /* Blocking error : transfer is aborted
01974            Set the SMARTCARD state ready to be able to start again the process,
01975            Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
01976         SMARTCARD_EndTxTransfer(hsmartcard);
01977
01978         /* Disable the SMARTCARD DMA Tx request if enabled */
01979         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01980         {
01981           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01982
01983           /* Abort the SMARTCARD DMA Tx channel */
01984           if (hsmartcard->hdmatx != NULL)
01985           {
01986             /* Set the SMARTCARD DMA Abort callback :
01987                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01988             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01989
01990             /* Abort DMA TX */
01991             if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01992             {
01993               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01994               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01995             }
01996           }
01997           else
01998           {
01999 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02000             /* Call registered user error callback */
02001             hsmartcard->ErrorCallback(hsmartcard);
02002 #else
02003             /* Call legacy weak user error callback */
02004             HAL_SMARTCARD_ErrorCallback(hsmartcard);
02005 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02006           }
02007         }
02008         else
02009         {
02010 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02011           /* Call registered user error callback */
02012           hsmartcard->ErrorCallback(hsmartcard);
02013 #else
02014           /* Call legacy weak user error callback */
02015           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02016 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02017         }
02018       }
02019       else
02020       {
02021         /* Non Blocking error : transfer could go on.
02022            Error is notified to user through user error callback */
02023 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02024         /* Call registered user error callback */
02025         hsmartcard->ErrorCallback(hsmartcard);
02026 #else
02027         /* Call legacy weak user error callback */
02028         HAL_SMARTCARD_ErrorCallback(hsmartcard);
02029 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02030         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02031       }
02032     }
02033     return;
02034
02035   } /* End if some error occurs */
02036
02037   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
02038   if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
02039   {
02040     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02041     __HAL_UNLOCK(hsmartcard);
02042 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02043     /* Call registered Rx complete callback */
02044     hsmartcard->RxCpltCallback(hsmartcard);
02045 #else
02046     /* Call legacy weak Rx complete callback */
02047     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02048 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02049     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
02050        to be available during HAL_SMARTCARD_RxCpltCallback() processing */
02051     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
02052     return;
02053   }
02054
02055   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
02056   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02057       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02058           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02059   {
02060     if (hsmartcard->TxISR != NULL)
02061     {
02062       hsmartcard->TxISR(hsmartcard);
02063     }
02064     return;
02065   }
02066
02067   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
02068   if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02069   {
02070     if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02071     {
02072       SMARTCARD_EndTransmit_IT(hsmartcard);
02073       return;
02074     }
02075   }
02076
02077   /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
02078   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02079   {
02080 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02081     /* Call registered Tx Fifo Empty Callback */
02082     hsmartcard->TxFifoEmptyCallback(hsmartcard);
02083 #else
02084     /* Call legacy weak Tx Fifo Empty Callback */
02085     HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
02086 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02087     return;
02088   }
02089
02090   /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
02091   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02092   {
02093 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02094     /* Call registered Rx Fifo Full Callback */
02095     hsmartcard->RxFifoFullCallback(hsmartcard);
02096 #else
02097     /* Call legacy weak Rx Fifo Full Callback */
02098     HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
02099 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02100     return;
02101   }
02102 }
02103
02104 /**
02105   * @brief  Tx Transfer completed callback.
02106   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02107   *                    the configuration information for the specified SMARTCARD module.
02108   * @retval None
02109   */
02110 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02111 {
02112   /* Prevent unused argument(s) compilation warning */
02113   UNUSED(hsmartcard);
02114
02115   /* NOTE : This function should not be modified, when the callback is needed,
02116             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
02117    */
02118 }
02119
02120 /**
02121   * @brief  Rx Transfer completed callback.
02122   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02123   *                    the configuration information for the specified SMARTCARD module.
02124   * @retval None
02125   */
02126 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02127 {
02128   /* Prevent unused argument(s) compilation warning */
02129   UNUSED(hsmartcard);
02130
02131   /* NOTE : This function should not be modified, when the callback is needed,
02132             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
02133    */
02134 }
02135
02136 /**
02137   * @brief  SMARTCARD error callback.
02138   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02139   *                    the configuration information for the specified SMARTCARD module.
02140   * @retval None
02141   */
02142 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02143 {
02144   /* Prevent unused argument(s) compilation warning */
02145   UNUSED(hsmartcard);
02146
02147   /* NOTE : This function should not be modified, when the callback is needed,
02148             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
02149    */
02150 }
02151
02152 /**
02153   * @brief  SMARTCARD Abort Complete callback.
02154   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02155   *                    the configuration information for the specified SMARTCARD module.
02156   * @retval None
02157   */
02158 __weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02159 {
02160   /* Prevent unused argument(s) compilation warning */
02161   UNUSED(hsmartcard);
02162
02163   /* NOTE : This function should not be modified, when the callback is needed,
02164             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
02165    */
02166 }
02167
02168 /**
02169   * @brief  SMARTCARD Abort Complete callback.
02170   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02171   *                    the configuration information for the specified SMARTCARD module.
02172   * @retval None
02173   */
02174 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02175 {
02176   /* Prevent unused argument(s) compilation warning */
02177   UNUSED(hsmartcard);
02178
02179   /* NOTE : This function should not be modified, when the callback is needed,
02180             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
02181    */
02182 }
02183
02184 /**
02185   * @brief  SMARTCARD Abort Receive Complete callback.
02186   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02187   *                    the configuration information for the specified SMARTCARD module.
02188   * @retval None
02189   */
02190 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02191 {
02192   /* Prevent unused argument(s) compilation warning */
02193   UNUSED(hsmartcard);
02194
02195   /* NOTE : This function should not be modified, when the callback is needed,
02196             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
02197    */
02198 }
02199
02200 /**
02201   * @}
02202   */
02203
02204 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
02205   * @brief    SMARTCARD State and Errors functions
02206   *
02207 @verbatim
02208   ==============================================================================
02209                   ##### Peripheral State and Errors functions #####
02210   ==============================================================================
02211   [..]
02212     This subsection provides a set of functions allowing to return the State of SmartCard
02213     handle and also return Peripheral Errors occurred during communication process
02214      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
02215          of the SMARTCARD peripheral.
02216      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
02217          communication.
02218
02219 @endverbatim
02220   * @{
02221   */
02222
02223 /**
02224   * @brief  Return the SMARTCARD handle state.
02225   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02226   *                    the configuration information for the specified SMARTCARD module.
02227   * @retval SMARTCARD handle state
02228   */
02229 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
02230 {
02231   /* Return SMARTCARD handle state */
02232   uint32_t temp1;
02233   uint32_t temp2;
02234   temp1 = (uint32_t)hsmartcard->gState;
02235   temp2 = (uint32_t)hsmartcard->RxState;
02236
02237   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
02238 }
02239
02240 /**
02241   * @brief  Return the SMARTCARD handle error code.
02242   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02243   *                    the configuration information for the specified SMARTCARD module.
02244   * @retval SMARTCARD handle Error Code
02245   */
02246 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
02247 {
02248   return hsmartcard->ErrorCode;
02249 }
02250
02251 /**
02252   * @}
02253   */
02254
02255 /**
02256   * @}
02257   */
02258
02259 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
02260   * @{
02261   */
02262
02263 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02264 /**
02265   * @brief  Initialize the callbacks to their default values.
02266   * @param  hsmartcard SMARTCARD handle.
02267   * @retval none
02268   */
02269 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
02270 {
02271   /* Init the SMARTCARD Callback settings */
02272   hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02273   hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02274   hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback             */
02275   hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02276   hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02277   hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02278   hsmartcard->RxFifoFullCallback        = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02279   hsmartcard->TxFifoEmptyCallback       = HAL_SMARTCARDEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02280
02281 }
02282 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
02283
02284 /**
02285   * @brief  Configure the SMARTCARD associated USART peripheral.
02286   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02287   *                    the configuration information for the specified SMARTCARD module.
02288   * @retval HAL status
02289   */
02290 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02291 {
02292   uint32_t tmpreg;
02293   SMARTCARD_ClockSourceTypeDef clocksource;
02294   HAL_StatusTypeDef ret = HAL_OK;
02295   const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02296   PLL2_ClocksTypeDef pll2_clocks;
02297   PLL3_ClocksTypeDef pll3_clocks;
02298   uint32_t pclk;
02299
02300   /* Check the parameters */
02301   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
02302   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
02303   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
02304   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
02305   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
02306   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
02307   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
02308   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
02309   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
02310   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
02311   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
02312   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
02313   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
02314   assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
02315
02316   /*-------------------------- USART CR1 Configuration -----------------------*/
02317   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
02318    * Oversampling is forced to 16 (OVER8 = 0).
02319    * Configure the Parity and Mode:
02320    *  set PS bit according to hsmartcard->Init.Parity value
02321    *  set TE and RE bits according to hsmartcard->Init.Mode value */
02322   tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
02323   tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
02324   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02325
02326   /*-------------------------- USART CR2 Configuration -----------------------*/
02327   tmpreg = hsmartcard->Init.StopBits;
02328   /* Synchronous mode is activated by default */
02329   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
02330   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
02331   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
02332   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02333
02334   /*-------------------------- USART CR3 Configuration -----------------------*/
02335   /* Configure
02336    * - one-bit sampling method versus three samples' majority rule
02337    *   according to hsmartcard->Init.OneBitSampling
02338    * - NACK transmission in case of parity error according
02339    *   to hsmartcard->Init.NACKEnable
02340    * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
02341
02342   tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
02343   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
02344   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02345
02346   /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
02347   /* Configure
02348   * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
02349   MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
02350
02351   /*-------------------------- USART GTPR Configuration ----------------------*/
02352   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
02353   MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
02354
02355   /*-------------------------- USART RTOR Configuration ----------------------*/
02356   tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
02357   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
02358   {
02359     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
02360     tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
02361   }
02362   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
02363
02364   /*-------------------------- USART BRR Configuration -----------------------*/
02365   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
02366   tmpreg =   0U;
02367   switch (clocksource)
02368   {
02369     case SMARTCARD_CLOCKSOURCE_D2PCLK1:
02370       pclk = HAL_RCC_GetPCLK1Freq();
02371       tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02372       break;
02373     case SMARTCARD_CLOCKSOURCE_D2PCLK2:
02374       pclk = HAL_RCC_GetPCLK2Freq();
02375       tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02376       break;
02377     case SMARTCARD_CLOCKSOURCE_PLL2Q:
02378       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02379       tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02380       break;
02381     case SMARTCARD_CLOCKSOURCE_PLL3Q:
02382       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02383       tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02384       break;
02385     case SMARTCARD_CLOCKSOURCE_HSI:
02386       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02387       {
02388         tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02389       }
02390       else
02391       {
02392         tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02393       }
02394       break;
02395     case SMARTCARD_CLOCKSOURCE_CSI:
02396       tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02397       break;
02398     case SMARTCARD_CLOCKSOURCE_LSE:
02399       tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02400       break;
02401     default:
02402       ret = HAL_ERROR;
02403       break;
02404   }
02405
02406   /* USARTDIV must be greater than or equal to 0d16 */
02407   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02408   {
02409     hsmartcard->Instance->BRR = tmpreg;
02410   }
02411   else
02412   {
02413     ret = HAL_ERROR;
02414   }
02415
02416   /* Initialize the number of data to process during RX/TX ISR execution */
02417   hsmartcard->NbTxDataToProcess = 1U;
02418   hsmartcard->NbRxDataToProcess = 1U;
02419
02420   /* Clear ISR function pointers */
02421   hsmartcard->RxISR   = NULL;
02422   hsmartcard->TxISR   = NULL;
02423
02424   return ret;
02425 }
02426
02427
02428 /**
02429   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
02430   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02431   *                   the configuration information for the specified SMARTCARD module.
02432   * @retval None
02433   */
02434 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02435 {
02436   /* Check whether the set of advanced features to configure is properly set */
02437   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
02438
02439   /* if required, configure TX pin active level inversion */
02440   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
02441   {
02442     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
02443     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
02444   }
02445
02446   /* if required, configure RX pin active level inversion */
02447   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
02448   {
02449     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
02450     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
02451   }
02452
02453   /* if required, configure data inversion */
02454   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
02455   {
02456     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
02457     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
02458   }
02459
02460   /* if required, configure RX/TX pins swap */
02461   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
02462   {
02463     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
02464     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
02465   }
02466
02467   /* if required, configure RX overrun detection disabling */
02468   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02469   {
02470     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
02471     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
02472   }
02473
02474   /* if required, configure DMA disabling on reception error */
02475   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
02476   {
02477     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
02478     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
02479   }
02480
02481   /* if required, configure MSB first on communication line */
02482   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
02483   {
02484     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
02485     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
02486   }
02487
02488 }
02489
02490 /**
02491   * @brief Check the SMARTCARD Idle State.
02492   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02493   *                   the configuration information for the specified SMARTCARD module.
02494   * @retval HAL status
02495   */
02496 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
02497 {
02498   uint32_t tickstart;
02499
02500   /* Initialize the SMARTCARD ErrorCode */
02501   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02502
02503   /* Init tickstart for timeout management */
02504   tickstart = HAL_GetTick();
02505
02506   /* Check if the Transmitter is enabled */
02507   if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02508   {
02509     /* Wait until TEACK flag is set */
02510     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
02511                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02512     {
02513       /* Timeout occurred */
02514       return HAL_TIMEOUT;
02515     }
02516   }
02517   /* Check if the Receiver is enabled */
02518   if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02519   {
02520     /* Wait until REACK flag is set */
02521     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
02522                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02523     {
02524       /* Timeout occurred */
02525       return HAL_TIMEOUT;
02526     }
02527   }
02528
02529   /* Initialize the SMARTCARD states */
02530   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02531   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02532
02533   /* Process Unlocked */
02534   __HAL_UNLOCK(hsmartcard);
02535
02536   return HAL_OK;
02537 }
02538
02539 /**
02540   * @brief  Handle SMARTCARD Communication Timeout.
02541   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02542   *                   the configuration information for the specified SMARTCARD module.
02543   * @param  Flag Specifies the SMARTCARD flag to check.
02544   * @param  Status The new Flag status (SET or RESET).
02545   * @param  Tickstart Tick start value
02546   * @param  Timeout Timeout duration.
02547   * @retval HAL status
02548   */
02549 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
02550                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02551 {
02552   /* Wait until flag is set */
02553   while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
02554   {
02555     /* Check for the Timeout */
02556     if (Timeout != HAL_MAX_DELAY)
02557     {
02558       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02559       {
02560         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02561         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02562         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02563
02564         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02565         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02566
02567         /* Process Unlocked */
02568         __HAL_UNLOCK(hsmartcard);
02569         return HAL_TIMEOUT;
02570       }
02571     }
02572   }
02573   return HAL_OK;
02574 }
02575
02576
02577 /**
02578   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
02579   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02580   *                    the configuration information for the specified SMARTCARD module.
02581   * @retval None
02582   */
02583 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02584 {
02585   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
02586   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02587   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02588
02589   /* At end of Tx process, restore hsmartcard->gState to Ready */
02590   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02591 }
02592
02593
02594 /**
02595   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02596   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02597   *                    the configuration information for the specified SMARTCARD module.
02598   * @retval None
02599   */
02600 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02601 {
02602   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02603   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02604   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02605
02606   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02607   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02608 }
02609
02610
02611 /**
02612   * @brief  DMA SMARTCARD transmit process complete callback.
02613   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02614   *              the configuration information for the specified DMA module.
02615   * @retval None
02616   */
02617 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02618 {
02619   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02620   hsmartcard->TxXferCount = 0U;
02621
02622   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02623   in the SMARTCARD associated USART CR3 register */
02624   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02625
02626   /* Enable the SMARTCARD Transmit Complete Interrupt */
02627   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02628 }
02629
02630 /**
02631   * @brief  DMA SMARTCARD receive process complete callback.
02632   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02633   *              the configuration information for the specified DMA module.
02634   * @retval None
02635   */
02636 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02637 {
02638   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02639   hsmartcard->RxXferCount = 0U;
02640
02641   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02642   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02643   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02644
02645   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02646      in the SMARTCARD associated USART CR3 register */
02647   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
02648
02649   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02650   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02651
02652 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02653   /* Call registered Rx complete callback */
02654   hsmartcard->RxCpltCallback(hsmartcard);
02655 #else
02656   /* Call legacy weak Rx complete callback */
02657   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02658 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02659 }
02660
02661 /**
02662   * @brief  DMA SMARTCARD communication error callback.
02663   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02664   *              the configuration information for the specified DMA module.
02665   * @retval None
02666   */
02667 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
02668 {
02669   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02670
02671   /* Stop SMARTCARD DMA Tx request if ongoing */
02672   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02673   {
02674     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02675     {
02676       hsmartcard->TxXferCount = 0U;
02677       SMARTCARD_EndTxTransfer(hsmartcard);
02678     }
02679   }
02680
02681   /* Stop SMARTCARD DMA Rx request if ongoing */
02682   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02683   {
02684     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
02685     {
02686       hsmartcard->RxXferCount = 0U;
02687       SMARTCARD_EndRxTransfer(hsmartcard);
02688     }
02689   }
02690
02691   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02692 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02693   /* Call registered user error callback */
02694   hsmartcard->ErrorCallback(hsmartcard);
02695 #else
02696   /* Call legacy weak user error callback */
02697   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02698 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02699 }
02700
02701 /**
02702   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02703   *         (To be called at end of DMA Abort procedure following error occurrence).
02704   * @param  hdma DMA handle.
02705   * @retval None
02706   */
02707 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02708 {
02709   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02710   hsmartcard->RxXferCount = 0U;
02711   hsmartcard->TxXferCount = 0U;
02712
02713 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02714   /* Call registered user error callback */
02715   hsmartcard->ErrorCallback(hsmartcard);
02716 #else
02717   /* Call legacy weak user error callback */
02718   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02719 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02720 }
02721
02722 /**
02723   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02724   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02725   * @note   When this callback is executed, User Abort complete call back is called only if no
02726   *         Abort still ongoing for Rx DMA Handle.
02727   * @param  hdma DMA handle.
02728   * @retval None
02729   */
02730 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02731 {
02732   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02733
02734   hsmartcard->hdmatx->XferAbortCallback = NULL;
02735
02736   /* Check if an Abort process is still ongoing */
02737   if (hsmartcard->hdmarx != NULL)
02738   {
02739     if (hsmartcard->hdmarx->XferAbortCallback != NULL)
02740     {
02741       return;
02742     }
02743   }
02744
02745   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02746   hsmartcard->TxXferCount = 0U;
02747   hsmartcard->RxXferCount = 0U;
02748
02749   /* Reset errorCode */
02750   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02751
02752   /* Clear the Error flags in the ICR register */
02753   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02754                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
02755                              SMARTCARD_CLEAR_EOBF);
02756
02757   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02758   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02759   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02760
02761 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02762   /* Call registered Abort complete callback */
02763   hsmartcard->AbortCpltCallback(hsmartcard);
02764 #else
02765   /* Call legacy weak Abort complete callback */
02766   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02767 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02768 }
02769
02770
02771 /**
02772   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02773   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02774   * @note   When this callback is executed, User Abort complete call back is called only if no
02775   *         Abort still ongoing for Tx DMA Handle.
02776   * @param  hdma DMA handle.
02777   * @retval None
02778   */
02779 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02780 {
02781   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02782
02783   hsmartcard->hdmarx->XferAbortCallback = NULL;
02784
02785   /* Check if an Abort process is still ongoing */
02786   if (hsmartcard->hdmatx != NULL)
02787   {
02788     if (hsmartcard->hdmatx->XferAbortCallback != NULL)
02789     {
02790       return;
02791     }
02792   }
02793
02794   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02795   hsmartcard->TxXferCount = 0U;
02796   hsmartcard->RxXferCount = 0U;
02797
02798   /* Reset errorCode */
02799   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02800
02801   /* Clear the Error flags in the ICR register */
02802   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02803                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
02804                              SMARTCARD_CLEAR_EOBF);
02805
02806   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02807   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02808   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02809
02810 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02811   /* Call registered Abort complete callback */
02812   hsmartcard->AbortCpltCallback(hsmartcard);
02813 #else
02814   /* Call legacy weak Abort complete callback */
02815   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02816 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02817 }
02818
02819
02820 /**
02821   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02822   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02823   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02824   *         and leads to user Tx Abort Complete callback execution).
02825   * @param  hdma DMA handle.
02826   * @retval None
02827   */
02828 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02829 {
02830   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02831
02832   hsmartcard->TxXferCount = 0U;
02833
02834   /* Clear the Error flags in the ICR register */
02835   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02836
02837   /* Restore hsmartcard->gState to Ready */
02838   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02839
02840 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02841   /* Call registered Abort Transmit Complete Callback */
02842   hsmartcard->AbortTransmitCpltCallback(hsmartcard);
02843 #else
02844   /* Call legacy weak Abort Transmit Complete Callback */
02845   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02846 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02847 }
02848
02849 /**
02850   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02851   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02852   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02853   *         and leads to user Rx Abort Complete callback execution).
02854   * @param  hdma DMA handle.
02855   * @retval None
02856   */
02857 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02858 {
02859   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02860
02861   hsmartcard->RxXferCount = 0U;
02862
02863   /* Clear the Error flags in the ICR register */
02864   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02865                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
02866                              SMARTCARD_CLEAR_EOBF);
02867
02868   /* Restore hsmartcard->RxState to Ready */
02869   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02870
02871 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02872   /* Call registered Abort Receive Complete Callback */
02873   hsmartcard->AbortReceiveCpltCallback(hsmartcard);
02874 #else
02875   /* Call legacy weak Abort Receive Complete Callback */
02876   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02877 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02878 }
02879
02880 /**
02881   * @brief  Send an amount of data in non-blocking mode.
02882   * @note   Function called under interruption only, once
02883   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02884   *         and when the FIFO mode is disabled.
02885   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02886   *                    the configuration information for the specified SMARTCARD module.
02887   * @retval None
02888   */
02889 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
02890 {
02891   /* Check that a Tx process is ongoing */
02892   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02893   {
02894     if (hsmartcard->TxXferCount == 0U)
02895     {
02896       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02897       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02898
02899       /* Enable the SMARTCARD Transmit Complete Interrupt */
02900       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02901     }
02902     else
02903     {
02904       hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02905       hsmartcard->pTxBuffPtr++;
02906       hsmartcard->TxXferCount--;
02907     }
02908   }
02909 }
02910
02911 /**
02912   * @brief  Send an amount of data in non-blocking mode.
02913   * @note   Function called under interruption only, once
02914   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02915   *         and when the FIFO mode is enabled.
02916   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02917   *                    the configuration information for the specified SMARTCARD module.
02918   * @retval None
02919   */
02920 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
02921 {
02922   uint16_t   nb_tx_data;
02923
02924   /* Check that a Tx process is ongoing */
02925   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02926   {
02927     for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
02928     {
02929       if (hsmartcard->TxXferCount == 0U)
02930       {
02931         /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02932         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02933
02934         /* Enable the SMARTCARD Transmit Complete Interrupt */
02935         __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02936       }
02937       else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
02938       {
02939         hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02940         hsmartcard->pTxBuffPtr++;
02941         hsmartcard->TxXferCount--;
02942       }
02943       else
02944       {
02945         /* Nothing to do */
02946       }
02947     }
02948   }
02949 }
02950
02951 /**
02952   * @brief  Wrap up transmission in non-blocking mode.
02953   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02954   *                    the configuration information for the specified SMARTCARD module.
02955   * @retval None
02956   */
02957 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02958 {
02959   /* Disable the SMARTCARD Transmit Complete Interrupt */
02960   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02961
02962   /* Check if a receive process is ongoing or not. If not disable ERR IT */
02963   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
02964   {
02965     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
02966     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02967   }
02968
02969   /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
02970   if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
02971   {
02972     /* Disable the Peripheral first to update modes */
02973     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02974     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
02975     /* Enable the Peripheral */
02976     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02977   }
02978
02979   /* Tx process is ended, restore hsmartcard->gState to Ready */
02980   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02981
02982   /* Clear TxISR function pointer */
02983   hsmartcard->TxISR = NULL;
02984
02985 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02986   /* Call registered Tx complete callback */
02987   hsmartcard->TxCpltCallback(hsmartcard);
02988 #else
02989   /* Call legacy weak Tx complete callback */
02990   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
02991 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02992 }
02993
02994 /**
02995   * @brief  Receive an amount of data in non-blocking mode.
02996   * @note   Function called under interruption only, once
02997   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
02998   *         and when the FIFO mode is disabled.
02999   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03000   *                    the configuration information for the specified SMARTCARD module.
03001   * @retval None
03002   */
03003 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
03004 {
03005   /* Check that a Rx process is ongoing */
03006   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03007   {
03008     *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03009     hsmartcard->pRxBuffPtr++;
03010
03011     hsmartcard->RxXferCount--;
03012     if (hsmartcard->RxXferCount == 0U)
03013     {
03014       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03015
03016       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03017       if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03018       {
03019         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03020         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03021       }
03022
03023       /* Disable the SMARTCARD Parity Error Interrupt */
03024       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03025
03026       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03027
03028       /* Clear RxISR function pointer */
03029       hsmartcard->RxISR = NULL;
03030
03031 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03032       /* Call registered Rx complete callback */
03033       hsmartcard->RxCpltCallback(hsmartcard);
03034 #else
03035       /* Call legacy weak Rx complete callback */
03036       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03037 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03038     }
03039   }
03040   else
03041   {
03042     /* Clear RXNE interrupt flag */
03043     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03044   }
03045 }
03046
03047 /**
03048   * @brief  Receive an amount of data in non-blocking mode.
03049   * @note   Function called under interruption only, once
03050   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03051   *         and when the FIFO mode is enabled.
03052   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03053   *                    the configuration information for the specified SMARTCARD module.
03054   * @retval None
03055   */
03056 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
03057 {
03058   uint16_t   nb_rx_data;
03059   uint16_t rxdatacount;
03060
03061   /* Check that a Rx process is ongoing */
03062   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03063   {
03064     for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03065     {
03066       *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03067       hsmartcard->pRxBuffPtr++;
03068
03069       hsmartcard->RxXferCount--;
03070       if (hsmartcard->RxXferCount == 0U)
03071       {
03072         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03073
03074         /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03075         if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03076         {
03077           /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03078           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03079         }
03080
03081         /* Disable the SMARTCARD Parity Error Interrupt */
03082         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03083
03084         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03085
03086         /* Clear RxISR function pointer */
03087         hsmartcard->RxISR = NULL;
03088
03089 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03090         /* Call registered Rx complete callback */
03091         hsmartcard->RxCpltCallback(hsmartcard);
03092 #else
03093         /* Call legacy weak Rx complete callback */
03094         HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03095 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03096       }
03097     }
03098
03099     /* When remaining number of bytes to receive is less than the RX FIFO
03100     threshold, next incoming frames are processed as if FIFO mode was
03101     disabled (i.e. one interrupt per received frame).
03102     */
03103     rxdatacount = hsmartcard->RxXferCount;
03104     if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
03105     {
03106       /* Disable the UART RXFT interrupt*/
03107       CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
03108
03109       /* Update the RxISR function pointer */
03110       hsmartcard->RxISR = SMARTCARD_RxISR;
03111
03112       /* Enable the UART Data Register Not Empty interrupt */
03113       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03114     }
03115   }
03116   else
03117   {
03118     /* Clear RXNE interrupt flag */
03119     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03120   }
03121 }
03122
03123 /**
03124   * @}
03125   */
03126
03127 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
03128 /**
03129   * @}
03130   */
03131
03132 /**
03133   * @}
03134   */
03135
03136 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard.h Source File

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stm32h7xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SMARTCARD_H
00022 #define STM32H7xx_HAL_SMARTCARD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMARTCARD
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief SMARTCARD Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051                                               Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
00052                                            where usart_ker_ckpres is the USART input clock divided by a prescaler */
00053
00054   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00055                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00056
00057   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00058                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00059
00060   uint16_t Parity;                    /*!< Specifies the parity mode.
00061                                            This parameter can be a value of @ref SMARTCARD_Parity
00062                                            @note The parity is enabled by default (PCE is forced to 1).
00063                                                  Since the WordLength is forced to 8 bits + parity, M is
00064                                                  forced to 1 and the parity bit is the 9th bit. */
00065
00066   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00067                                            This parameter can be a value of @ref SMARTCARD_Mode */
00068
00069   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00070                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00071
00072   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00073                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00074
00075   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00076                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00077                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00078
00079   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00080                                            Selecting the single sample method increases the receiver tolerance to clock
00081                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
00082
00083   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
00084                                            This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
00085                                            by 2 to give the division factor of the source clock frequency */
00086
00087   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00088
00089   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00090                                            in case of parity error.
00091                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00092
00093   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00094                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00095
00096   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00097                                            it is used to implement the Character Wait Time (CWT) and
00098                                            Block Wait Time (BWT). It is coded over 24 bits. */
00099
00100   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00101                                            This parameter can be any value from 0x0 to 0xFF */
00102
00103   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00104                                             receive and transmit mode). When set to 0, retransmission is
00105                                             disabled. Otherwise, its maximum value is 7 (before signalling
00106                                             an error) */
00107
00108   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00109                                            This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
00110
00111 } SMARTCARD_InitTypeDef;
00112
00113 /**
00114   * @brief  SMARTCARD advanced features initalization structure definition
00115   */
00116 typedef struct
00117 {
00118   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00119                                            advanced features may be initialized at the same time. This parameter
00120                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00121
00122   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00123                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00124
00125   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00126                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00127
00128   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00129                                            vs negative/inverted logic).
00130                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00131
00132   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00133                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00134
00135   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00136                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00137
00138   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00139                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00140
00141   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00142                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00143
00144   uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when
00145                                             relevant flag is available) or once guard time period has elapsed.
00146                                            This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00147 } SMARTCARD_AdvFeatureInitTypeDef;
00148
00149 /**
00150   * @brief HAL SMARTCARD State definition
00151   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
00152   *        - gState contains SMARTCARD state information related to global Handle management
00153   *          and also information related to Tx operations.
00154   *          gState value coding follow below described bitmap :
00155   *          b7-b6  Error information
00156   *             00 : No Error
00157   *             01 : (Not Used)
00158   *             10 : Timeout
00159   *             11 : Error
00160   *          b5     Peripheral initialization status
00161   *             0  : Reset (Peripheral not initialized)
00162   *             1  : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
00163   *          b4-b3  (not used)
00164   *             xx : Should be set to 00
00165   *          b2     Intrinsic process state
00166   *             0  : Ready
00167   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00168   *          b1     (not used)
00169   *             x  : Should be set to 0
00170   *          b0     Tx state
00171   *             0  : Ready (no Tx operation ongoing)
00172   *             1  : Busy (Tx operation ongoing)
00173   *        - RxState contains information related to Rx operations.
00174   *          RxState value coding follow below described bitmap :
00175   *          b7-b6  (not used)
00176   *             xx : Should be set to 00
00177   *          b5     Peripheral initialization status
00178   *             0  : Reset (Peripheral not initialized)
00179   *             1  : Init done (Peripheral not initialized)
00180   *          b4-b2  (not used)
00181   *            xxx : Should be set to 000
00182   *          b1     Rx state
00183   *             0  : Ready (no Rx operation ongoing)
00184   *             1  : Busy (Rx operation ongoing)
00185   *          b0     (not used)
00186   *             x  : Should be set to 0.
00187   */
00188 typedef uint32_t HAL_SMARTCARD_StateTypeDef;
00189
00190 /**
00191   * @brief  SMARTCARD handle Structure definition
00192   */
00193 typedef struct __SMARTCARD_HandleTypeDef
00194 {
00195   USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
00196
00197   SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
00198
00199   SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
00200
00201   uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
00202
00203   uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
00204
00205   __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
00206
00207   uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
00208
00209   uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
00210
00211   __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
00212
00213   uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
00214
00215   uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
00216
00217   uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
00218                                                                 This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
00219
00220   void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
00221
00222   void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
00223
00224   DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
00225
00226   DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
00227
00228   HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
00229
00230   __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global Handle management
00231                                                                 and also related to Tx operations.
00232                                                                 This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00233
00234   __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
00235                                                                 This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00236
00237   __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
00238
00239 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00240   void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
00241
00242   void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
00243
00244   void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
00245
00246   void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
00247
00248   void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
00249
00250   void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
00251
00252   void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
00253
00254   void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
00255
00256   void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
00257
00258   void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
00259 #endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00260
00261 } SMARTCARD_HandleTypeDef;
00262
00263 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00264 /**
00265   * @brief  HAL SMARTCARD Callback ID enumeration definition
00266   */
00267 typedef enum
00268 {
00269   HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
00270   HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
00271   HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
00272   HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
00273   HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
00274   HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
00275   HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
00276   HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
00277
00278   HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
00279   HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
00280
00281 } HAL_SMARTCARD_CallbackIDTypeDef;
00282
00283 /**
00284   * @brief  HAL SMARTCARD Callback pointer definition
00285   */
00286 typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
00287
00288 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00289
00290 /**
00291   * @brief  SMARTCARD clock sources
00292   */
00293 typedef enum
00294 {
00295   SMARTCARD_CLOCKSOURCE_D2PCLK1   = 0x00U, /*!< Domain2 PCLK1 clock source */
00296   SMARTCARD_CLOCKSOURCE_D2PCLK2   = 0x01U, /*!< Domain2 PCLK2 clock source */
00297   SMARTCARD_CLOCKSOURCE_HSI       = 0x04U, /*!< HSI clock source           */
00298   SMARTCARD_CLOCKSOURCE_CSI       = 0x08U, /*!< CSI clock source           */
00299   SMARTCARD_CLOCKSOURCE_LSE       = 0x20U, /*!< LSE clock source           */
00300   SMARTCARD_CLOCKSOURCE_PLL2Q     = 0x40U, /*!< PLL2Q clock source         */
00301   SMARTCARD_CLOCKSOURCE_PLL3Q     = 0x80U, /*!< PLL3Q clock source         */
00302   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */
00303 } SMARTCARD_ClockSourceTypeDef;
00304
00305 /**
00306   * @}
00307   */
00308
00309 /* Exported constants --------------------------------------------------------*/
00310 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00311   * @{
00312   */
00313
00314 /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
00315   * @{
00316   */
00317 #define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized
00318                                                                                   Value is allowed for gState and RxState */
00319 #define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for use
00320                                                                                   Value is allowed for gState and RxState */
00321 #define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
00322                                                                                   Value is allowed for gState only */
00323 #define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
00324                                                                                   Value is allowed for gState only */
00325 #define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
00326                                                                                   Value is allowed for RxState only */
00327 #define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception process is ongoing
00328                                                                                   Not to be used for neither gState nor RxState.
00329                                                                                   Value is result of combination (Or) between gState and RxState values */
00330 #define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
00331                                                                                   Value is allowed for gState only */
00332 #define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
00333                                                                                   Value is allowed for gState only */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
00339   * @{
00340   */
00341 #define HAL_SMARTCARD_ERROR_NONE             ((uint32_t)0x00000000U)         /*!< No error                */
00342 #define HAL_SMARTCARD_ERROR_PE               ((uint32_t)0x00000001U)         /*!< Parity error            */
00343 #define HAL_SMARTCARD_ERROR_NE               ((uint32_t)0x00000002U)         /*!< Noise error             */
00344 #define HAL_SMARTCARD_ERROR_FE               ((uint32_t)0x00000004U)         /*!< frame error             */
00345 #define HAL_SMARTCARD_ERROR_ORE              ((uint32_t)0x00000008U)         /*!< Overrun error           */
00346 #define HAL_SMARTCARD_ERROR_DMA              ((uint32_t)0x00000010U)         /*!< DMA transfer error      */
00347 #define HAL_SMARTCARD_ERROR_RTO              ((uint32_t)0x00000020U)         /*!< Receiver TimeOut error  */
00348 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00349 #define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)         /*!< Invalid Callback error  */
00350 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00356   * @{
00357   */
00358 #define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00364   * @{
00365   */
00366 #define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
00367 #define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00373   * @{
00374   */
00375 #define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
00376 #define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00382   * @{
00383   */
00384 #define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
00385 #define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
00386 #define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00392   * @{
00393   */
00394 #define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
00395 #define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00401   * @{
00402   */
00403 #define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
00404 #define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00410   * @{
00411   */
00412 #define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00413 #define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00419   * @{
00420   */
00421 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
00422 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00428   * @{
00429   */
00430 #define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
00431 #define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00437   * @{
00438   */
00439 #define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
00440 #define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
00446   * @{
00447   */
00448 #define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00449 #define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00450 #define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00451 #define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00452 #define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00453 #define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00454 #define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00455 #define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00456 #define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00457 #define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00458 #define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00459 #define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00465   * @{
00466   */
00467 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
00468 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00474   * @{
00475   */
00476 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
00477 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00483   * @{
00484   */
00485 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
00486 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00492   * @{
00493   */
00494 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
00495 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00501   * @{
00502   */
00503 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
00504 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00510   * @{
00511   */
00512 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
00513 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00519   * @{
00520   */
00521 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
00522 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00528   * @{
00529   */
00530 #define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
00531 #define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00537   * @{
00538   */
00539 #define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
00540 #define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
00541 #define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
00542 #define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
00543 #define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
00544 /**
00545   * @}
00546   */
00547
00548 /**
00549   * @}
00550   */
00551
00552 /* Exported macros -----------------------------------------------------------*/
00553 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00554   * @{
00555   */
00556
00557 /** @brief  Reset SMARTCARD handle states.
00558   * @param  __HANDLE__ SMARTCARD handle.
00559   * @retval None
00560   */
00561 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00562 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00563                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00564                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00565                                                             (__HANDLE__)->MspInitCallback = NULL;                 \
00566                                                             (__HANDLE__)->MspDeInitCallback = NULL;               \
00567                                                           } while(0U)
00568 #else
00569 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00570                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00571                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00572                                                           } while(0U)
00573 #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
00574
00575 /** @brief  Flush the Smartcard Data registers.
00576   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00577   * @retval None
00578   */
00579 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
00580   do{                                                                     \
00581     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00582     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00583   } while(0U)
00584
00585 /** @brief  Clear the specified SMARTCARD pending flag.
00586   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00587   * @param  __FLAG__ specifies the flag to check.
00588   *          This parameter can be any combination of the following values:
00589   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00590   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00591   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00592   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00593   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00594   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00595   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
00596   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00597   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00598   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
00599   * @retval None
00600   */
00601 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00602
00603 /** @brief  Clear the SMARTCARD PE pending flag.
00604   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00605   * @retval None
00606   */
00607 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00608
00609 /** @brief  Clear the SMARTCARD FE pending flag.
00610   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00611   * @retval None
00612   */
00613 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00614
00615 /** @brief  Clear the SMARTCARD NE pending flag.
00616   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00617   * @retval None
00618   */
00619 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00620
00621 /** @brief  Clear the SMARTCARD ORE pending flag.
00622   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00623   * @retval None
00624   */
00625 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00626
00627 /** @brief  Clear the SMARTCARD IDLE pending flag.
00628   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00629   * @retval None
00630   */
00631 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00632
00633 /** @brief  Check whether the specified Smartcard flag is set or not.
00634   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00635   * @param  __FLAG__ specifies the flag to check.
00636   *        This parameter can be one of the following values:
00637   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
00638   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00639   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00640   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00641   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00642   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00643   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00644   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00645   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00646   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00647   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00648   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00649   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00650   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00651   *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
00652   *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
00653   *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
00654   *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
00655   *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
00656   *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
00657   * @retval The new state of __FLAG__ (TRUE or FALSE).
00658   */
00659 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00660
00661 /** @brief  Enable the specified SmartCard interrupt.
00662   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00663   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
00664   *          This parameter can be one of the following values:
00665   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00666   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00667   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00668   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00669   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00670   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00671   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00672   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00673   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00674   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00675   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00676   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00677   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00678   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00679   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00680   * @retval None
00681   */
00682 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00683                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00684                                                                 ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00685
00686 /** @brief  Disable the specified SmartCard interrupt.
00687   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00688   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
00689   *          This parameter can be one of the following values:
00690   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00691   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00692   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00693   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00694   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00695   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00696   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00697   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00698   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00699   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00700   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00701   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00702   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00703   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00704   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00705   * @retval None
00706   */
00707 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00708                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00709                                                                 ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00710
00711 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00712   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00713   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
00714   *          This parameter can be one of the following values:
00715   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00716   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00717   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00718   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00719   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00720   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00721   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00722   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00723   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00724   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00725   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00726   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00727   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00728   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00729   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00730   * @retval The new state of __INTERRUPT__ (SET or RESET).
00731   */
00732 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00733                                                              & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
00734
00735 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00736   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00737   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
00738   *          This parameter can be one of the following values:
00739   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00740   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00741   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00742   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00743   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00744   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00745   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00746   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00747   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00748   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00749   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00750   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00751   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00752   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00753   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00754   * @retval The new state of __INTERRUPT__ (SET or RESET).
00755   */
00756 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
00757                                                                      (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
00758                                                                       (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)
00759
00760 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00761   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00762   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00763   *                       to clear the corresponding interrupt.
00764   *          This parameter can be one of the following values:
00765   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00766   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00767   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00768   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00769   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00770   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
00771   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00772   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00773   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00774   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00775   * @retval None
00776   */
00777 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00778
00779 /** @brief  Set a specific SMARTCARD request flag.
00780   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00781   * @param  __REQ__ specifies the request flag to set
00782   *          This parameter can be one of the following values:
00783   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00784   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00785   * @retval None
00786   */
00787 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00788
00789 /** @brief  Enable the SMARTCARD one bit sample method.
00790   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00791   * @retval None
00792   */
00793 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00794
00795 /** @brief  Disable the SMARTCARD one bit sample method.
00796   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00797   * @retval None
00798   */
00799 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00800                                                             &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00801
00802 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00803   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00804   * @retval None
00805   */
00806 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00807
00808 /** @brief  Disable the USART associated to the SMARTCARD Handle
00809   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00810   * @retval None
00811   */
00812 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00813
00814 /**
00815   * @}
00816   */
00817
00818 /* Private macros -------------------------------------------------------------*/
00819 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00820   * @{
00821   */
00822
00823 /** @brief  Report the SMARTCARD clock source.
00824   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00825   * @param  __CLOCKSOURCE__ output variable.
00826   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00827   */
00828 #if defined(UART9) && defined(USART10)
00829 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00830   do {                                                         \
00831     if ((__HANDLE__)->Instance == USART1)                      \
00832     {                                                          \
00833       switch (__HAL_RCC_GET_USART1_SOURCE())                   \
00834       {                                                        \
00835         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00836           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
00837           break;                                               \
00838         case RCC_USART1CLKSOURCE_PLL2:                         \
00839           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00840           break;                                               \
00841         case RCC_USART1CLKSOURCE_PLL3:                         \
00842           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00843           break;                                               \
00844         case RCC_USART1CLKSOURCE_HSI:                          \
00845           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00846           break;                                               \
00847         case RCC_USART1CLKSOURCE_CSI:                          \
00848           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00849           break;                                               \
00850         case RCC_USART1CLKSOURCE_LSE:                          \
00851           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00852           break;                                               \
00853         default:                                               \
00854           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00855           break;                                               \
00856       }                                                        \
00857     }                                                          \
00858     else if ((__HANDLE__)->Instance == USART2)                 \
00859     {                                                          \
00860       switch (__HAL_RCC_GET_USART2_SOURCE())                   \
00861       {                                                        \
00862         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
00863           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
00864           break;                                               \
00865         case RCC_USART2CLKSOURCE_PLL2:                         \
00866           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00867           break;                                               \
00868         case RCC_USART2CLKSOURCE_PLL3:                         \
00869           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00870           break;                                               \
00871         case RCC_USART2CLKSOURCE_HSI:                          \
00872           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00873           break;                                               \
00874         case RCC_USART2CLKSOURCE_CSI:                          \
00875           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00876           break;                                               \
00877         case RCC_USART2CLKSOURCE_LSE:                          \
00878           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00879           break;                                               \
00880         default:                                               \
00881           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00882           break;                                               \
00883       }                                                        \
00884     }                                                          \
00885     else if ((__HANDLE__)->Instance == USART3)                 \
00886     {                                                          \
00887       switch (__HAL_RCC_GET_USART3_SOURCE())                   \
00888       {                                                        \
00889         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
00890           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
00891           break;                                               \
00892         case RCC_USART3CLKSOURCE_PLL2:                         \
00893           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00894           break;                                               \
00895         case RCC_USART3CLKSOURCE_PLL3:                         \
00896           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00897           break;                                               \
00898         case RCC_USART3CLKSOURCE_HSI:                          \
00899           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00900           break;                                               \
00901         case RCC_USART3CLKSOURCE_CSI:                          \
00902           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00903           break;                                               \
00904         case RCC_USART3CLKSOURCE_LSE:                          \
00905           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00906           break;                                               \
00907         default:                                               \
00908           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00909           break;                                               \
00910       }                                                        \
00911     }                                                          \
00912     else if ((__HANDLE__)->Instance == USART6)                 \
00913     {                                                          \
00914       switch (__HAL_RCC_GET_USART6_SOURCE())                   \
00915       {                                                        \
00916         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
00917           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
00918           break;                                               \
00919         case RCC_USART6CLKSOURCE_PLL2:                         \
00920           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00921           break;                                               \
00922         case RCC_USART6CLKSOURCE_PLL3:                         \
00923           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00924           break;                                               \
00925         case RCC_USART6CLKSOURCE_HSI:                          \
00926           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00927           break;                                               \
00928         case RCC_USART6CLKSOURCE_CSI:                          \
00929           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00930           break;                                               \
00931         case RCC_USART6CLKSOURCE_LSE:                          \
00932           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00933           break;                                               \
00934         default:                                               \
00935           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00936           break;                                               \
00937       }                                                        \
00938     }                                                          \
00939     else if ((__HANDLE__)->Instance == USART10)                \
00940     {                                                          \
00941       switch (__HAL_RCC_GET_USART10_SOURCE())                  \
00942       {                                                        \
00943         case RCC_USART10CLKSOURCE_D2PCLK2:                     \
00944           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
00945           break;                                               \
00946         case RCC_USART10CLKSOURCE_PLL2:                        \
00947           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00948           break;                                               \
00949         case RCC_USART10CLKSOURCE_PLL3:                        \
00950           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00951           break;                                               \
00952         case RCC_USART10CLKSOURCE_HSI:                         \
00953           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00954           break;                                               \
00955         case RCC_USART10CLKSOURCE_CSI:                         \
00956           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00957           break;                                               \
00958         case RCC_USART10CLKSOURCE_LSE:                         \
00959           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00960           break;                                               \
00961         default:                                               \
00962           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00963           break;                                               \
00964       }                                                        \
00965     }                                                          \
00966     else                                                       \
00967     {                                                          \
00968       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00969     }                                                          \
00970   } while(0U)
00971 #else
00972 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00973   do {                                                         \
00974     if ((__HANDLE__)->Instance == USART1)                      \
00975     {                                                          \
00976       switch (__HAL_RCC_GET_USART1_SOURCE())                   \
00977       {                                                        \
00978         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00979           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
00980           break;                                               \
00981         case RCC_USART1CLKSOURCE_PLL2:                         \
00982           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
00983           break;                                               \
00984         case RCC_USART1CLKSOURCE_PLL3:                         \
00985           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
00986           break;                                               \
00987         case RCC_USART1CLKSOURCE_HSI:                          \
00988           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00989           break;                                               \
00990         case RCC_USART1CLKSOURCE_CSI:                          \
00991           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
00992           break;                                               \
00993         case RCC_USART1CLKSOURCE_LSE:                          \
00994           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00995           break;                                               \
00996         default:                                               \
00997           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00998           break;                                               \
00999       }                                                        \
01000     }                                                          \
01001     else if ((__HANDLE__)->Instance == USART2)                 \
01002     {                                                          \
01003       switch (__HAL_RCC_GET_USART2_SOURCE())                   \
01004       {                                                        \
01005         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
01006           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
01007           break;                                               \
01008         case RCC_USART2CLKSOURCE_PLL2:                         \
01009           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;    \
01010           break;                                               \
01011         case RCC_USART2CLKSOURCE_PLL3:                         \
01012           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
01013           break;                                               \
01014         case RCC_USART2CLKSOURCE_HSI:                          \
01015           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
01016           break;                                               \
01017         case RCC_USART2CLKSOURCE_CSI:                          \
01018           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
01019           break;                                               \
01020         case RCC_USART2CLKSOURCE_LSE:                          \
01021           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
01022           break;                                               \
01023         default:                                               \
01024           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
01025           break;                                               \
01026       }                                                        \
01027     }                                                          \
01028     else if ((__HANDLE__)->Instance == USART3)                 \
01029     {                                                          \
01030       switch (__HAL_RCC_GET_USART3_SOURCE())                   \
01031       {                                                        \
01032         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
01033           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
01034           break;                                               \
01035         case RCC_USART3CLKSOURCE_PLL2:                         \
01036           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
01037           break;                                               \
01038         case RCC_USART3CLKSOURCE_PLL3:                         \
01039           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
01040           break;                                               \
01041         case RCC_USART3CLKSOURCE_HSI:                          \
01042           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
01043           break;                                               \
01044         case RCC_USART3CLKSOURCE_CSI:                          \
01045           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
01046           break;                                               \
01047         case RCC_USART3CLKSOURCE_LSE:                          \
01048           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
01049           break;                                               \
01050         default:                                               \
01051           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
01052           break;                                               \
01053       }                                                        \
01054     }                                                          \
01055     else if ((__HANDLE__)->Instance == USART6)                 \
01056     {                                                          \
01057       switch (__HAL_RCC_GET_USART6_SOURCE())                   \
01058       {                                                        \
01059         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
01060           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
01061           break;                                               \
01062         case RCC_USART6CLKSOURCE_PLL2:                         \
01063           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
01064           break;                                               \
01065         case RCC_USART6CLKSOURCE_PLL3:                         \
01066           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
01067           break;                                               \
01068         case RCC_USART6CLKSOURCE_HSI:                          \
01069           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
01070           break;                                               \
01071         case RCC_USART6CLKSOURCE_CSI:                          \
01072           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
01073           break;                                               \
01074         case RCC_USART6CLKSOURCE_LSE:                          \
01075           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
01076           break;                                               \
01077         default:                                               \
01078           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
01079           break;                                               \
01080       }                                                        \
01081     }                                                          \
01082     else                                                       \
01083     {                                                          \
01084       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
01085     }                                                          \
01086   } while(0U)
01087 #endif /* UART9 && USART10 */
01088
01089 /** @brief  Check the Baud rate range.
01090   * @note   The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz)
01091   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
01092   * @param  __BAUDRATE__ Baud rate set by the configuration function.
01093   * @retval Test result (TRUE or FALSE)
01094   */
01095 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U)
01096
01097 /** @brief  Check the block length range.
01098   * @note   The maximum SMARTCARD block length is 0xFF.
01099   * @param  __LENGTH__ block length.
01100   * @retval Test result (TRUE or FALSE)
01101   */
01102 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
01103
01104 /** @brief  Check the receiver timeout value.
01105   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
01106   * @param  __TIMEOUTVALUE__ receiver timeout value.
01107   * @retval Test result (TRUE or FALSE)
01108   */
01109 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
01110
01111 /** @brief  Check the SMARTCARD autoretry counter value.
01112   * @note   The maximum number of retransmissions is 0x7.
01113   * @param  __COUNT__ number of retransmissions.
01114   * @retval Test result (TRUE or FALSE)
01115   */
01116 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
01117
01118 /** @brief Ensure that SMARTCARD frame length is valid.
01119   * @param __LENGTH__ SMARTCARD frame length.
01120   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01121   */
01122 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
01123
01124 /** @brief Ensure that SMARTCARD frame number of stop bits is valid.
01125   * @param __STOPBITS__ SMARTCARD frame number of stop bits.
01126   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01127   */
01128 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
01129                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
01130
01131 /** @brief Ensure that SMARTCARD frame parity is valid.
01132   * @param __PARITY__ SMARTCARD frame parity.
01133   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01134   */
01135 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
01136                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
01137
01138 /** @brief Ensure that SMARTCARD communication mode is valid.
01139   * @param __MODE__ SMARTCARD communication mode.
01140   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01141   */
01142 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
01143
01144 /** @brief Ensure that SMARTCARD frame polarity is valid.
01145   * @param __CPOL__ SMARTCARD frame polarity.
01146   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
01147   */
01148 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
01149                                          || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
01150
01151 /** @brief Ensure that SMARTCARD frame phase is valid.
01152   * @param __CPHA__ SMARTCARD frame phase.
01153   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
01154   */
01155 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
01156
01157 /** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
01158   * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
01159   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
01160   */
01161 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
01162                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
01163
01164 /** @brief Ensure that SMARTCARD frame sampling is valid.
01165   * @param __ONEBIT__ SMARTCARD frame sampling.
01166   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01167   */
01168 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
01169                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
01170
01171 /** @brief Ensure that SMARTCARD NACK transmission setting is valid.
01172   * @param __NACK__ SMARTCARD NACK transmission setting.
01173   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
01174   */
01175 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
01176                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
01177
01178 /** @brief Ensure that SMARTCARD receiver timeout setting is valid.
01179   * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
01180   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01181   */
01182 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
01183                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
01184
01185 /** @brief Ensure that SMARTCARD clock Prescaler is valid.
01186   * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
01187   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01188   */
01189 #define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
01190                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
01191                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
01192                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
01193                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
01194                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
01195                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
01196                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
01197                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
01198                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
01199                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
01200                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
01201
01202 /** @brief Ensure that SMARTCARD advanced features initialization is valid.
01203   * @param __INIT__ SMARTCARD advanced features initialization.
01204   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01205   */
01206 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
01207                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
01208                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
01209                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
01210                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
01211                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01212                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
01213                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01214
01215 /** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
01216   * @param __TXINV__ SMARTCARD frame TX inversion setting.
01217   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01218   */
01219 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
01220                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
01221
01222 /** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
01223   * @param __RXINV__ SMARTCARD frame RX inversion setting.
01224   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01225   */
01226 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
01227                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
01228
01229 /** @brief Ensure that SMARTCARD frame data inversion setting is valid.
01230   * @param __DATAINV__ SMARTCARD frame data inversion setting.
01231   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01232   */
01233 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
01234                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
01235
01236 /** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
01237   * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
01238   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01239   */
01240 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
01241                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
01242
01243 /** @brief Ensure that SMARTCARD frame overrun setting is valid.
01244   * @param __OVERRUN__ SMARTCARD frame overrun setting.
01245   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01246   */
01247 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
01248                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
01249
01250 /** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
01251   * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
01252   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01253   */
01254 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01255                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
01256
01257 /** @brief Ensure that SMARTCARD frame MSB first setting is valid.
01258   * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
01259   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01260   */
01261 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
01262                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
01263
01264 /** @brief Ensure that SMARTCARD request parameter is valid.
01265   * @param __PARAM__ SMARTCARD request parameter.
01266   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01267   */
01268 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
01269                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
01270
01271 /**
01272   * @}
01273   */
01274
01275 /* Include SMARTCARD HAL Extended module */
01276 #include "stm32h7xx_hal_smartcard_ex.h"
01277
01278 /* Exported functions --------------------------------------------------------*/
01279 /** @addtogroup SMARTCARD_Exported_Functions
01280   * @{
01281   */
01282
01283 /* Initialization and de-initialization functions  ****************************/
01284 /** @addtogroup SMARTCARD_Exported_Functions_Group1
01285   * @{
01286   */
01287
01288 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01289 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01290 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01291 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01292
01293 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01294 /* Callbacks Register/UnRegister functions  ***********************************/
01295 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01296                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
01297 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01298                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
01299 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
01300
01301 /**
01302   * @}
01303   */
01304
01305 /* IO operation functions *****************************************************/
01306 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01307   * @{
01308   */
01309
01310 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
01311                                          uint32_t Timeout);
01312 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
01313                                         uint32_t Timeout);
01314 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01315 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01316 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01317 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01318 /* Transfer Abort functions */
01319 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01320 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01321 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01322 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01323 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01324 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01325
01326 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01327 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01328 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01329 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01330 void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01331 void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01332 void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01333
01334 /**
01335   * @}
01336   */
01337
01338 /* Peripheral State and Error functions ***************************************/
01339 /** @addtogroup SMARTCARD_Exported_Functions_Group4
01340   * @{
01341   */
01342
01343 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
01344 uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
01345
01346 /**
01347   * @}
01348   */
01349
01350 /**
01351   * @}
01352   */
01353
01354 /**
01355   * @}
01356   */
01357
01358 /**
01359   * @}
01360   */
01361
01362 #ifdef __cplusplus
01363 }
01364 #endif
01365
01366 #endif /* STM32H7xx_HAL_SMARTCARD_H */
01367
01368 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard_ex.c Source File

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stm32h7xx_hal_smartcard_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides extended firmware functions to manage the following
00007   *          functionalities of the SmartCard.
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   =============================================================================
00013                ##### SMARTCARD peripheral extended features  #####
00014   =============================================================================
00015   [..]
00016   The Extended SMARTCARD HAL driver can be used as follows:
00017
00018     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00019         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00020         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00021
00022     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00023
00024         -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
00025             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00026             configured prior starting RX/TX transfers.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00033   * All rights reserved.</center></h2>
00034   *
00035   * This software component is licensed by ST under BSD 3-Clause license,
00036   * the "License"; You may not use this file except in compliance with the
00037   * License. You may obtain a copy of the License at:
00038   *                        opensource.org/licenses/BSD-3-Clause
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx_hal.h"
00045
00046 /** @addtogroup STM32H7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SMARTCARDEx SMARTCARDEx
00051   * @brief SMARTCARD Extended HAL module driver
00052   * @{
00053   */
00054 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
00059   * @{
00060   */
00061 /* UART RX FIFO depth */
00062 #define RX_FIFO_DEPTH 8U
00063
00064 /* UART TX FIFO depth */
00065 #define TX_FIFO_DEPTH 8U
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
00074
00075 /* Exported functions --------------------------------------------------------*/
00076 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00077   * @{
00078   */
00079
00080 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00081   * @brief    Extended control functions
00082   *
00083 @verbatim
00084   ===============================================================================
00085                       ##### Peripheral Control functions #####
00086   ===============================================================================
00087   [..]
00088   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00089      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00090      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00091      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00092      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /** @brief Update on the fly the SMARTCARD block length in RTOR register.
00099   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00100   *                    the configuration information for the specified SMARTCARD module.
00101   * @param BlockLength SMARTCARD block length (8-bit long at most)
00102   * @retval None
00103   */
00104 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00105 {
00106   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
00107 }
00108
00109 /** @brief Update on the fly the receiver timeout value in RTOR register.
00110   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00111   *                    the configuration information for the specified SMARTCARD module.
00112   * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
00113   *                     value must be less or equal to 0x0FFFFFFFF.
00114   * @retval None
00115   */
00116 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00117 {
00118   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00119   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00120 }
00121
00122 /** @brief Enable the SMARTCARD receiver timeout feature.
00123   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00124   *                    the configuration information for the specified SMARTCARD module.
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00128 {
00129   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00130   {
00131     /* Process Locked */
00132     __HAL_LOCK(hsmartcard);
00133
00134     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00135
00136     /* Set the USART RTOEN bit */
00137     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00138
00139     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00140
00141     /* Process Unlocked */
00142     __HAL_UNLOCK(hsmartcard);
00143
00144     return HAL_OK;
00145   }
00146   else
00147   {
00148     return HAL_BUSY;
00149   }
00150 }
00151
00152 /** @brief Disable the SMARTCARD receiver timeout feature.
00153   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00154   *                    the configuration information for the specified SMARTCARD module.
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00158 {
00159   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00160   {
00161     /* Process Locked */
00162     __HAL_LOCK(hsmartcard);
00163
00164     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00165
00166     /* Clear the USART RTOEN bit */
00167     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00168
00169     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00170
00171     /* Process Unlocked */
00172     __HAL_UNLOCK(hsmartcard);
00173
00174     return HAL_OK;
00175   }
00176   else
00177   {
00178     return HAL_BUSY;
00179   }
00180 }
00181
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
00187   * @brief   SMARTCARD Transmit and Receive functions
00188   *
00189 @verbatim
00190  ===============================================================================
00191                       ##### IO operation functions #####
00192  ===============================================================================
00193     [..]
00194     This subsection provides a set of FIFO mode related callback functions.
00195
00196     (#) TX/RX Fifos Callbacks:
00197         (++) HAL_SMARTCARDEx_RxFifoFullCallback()
00198         (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
00199
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  SMARTCARD RX Fifo full callback.
00206   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00207   *                   the configuration information for the specified SMARTCARD module.
00208   * @retval None
00209   */
00210 __weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hsmartcard);
00214
00215   /* NOTE : This function should not be modified, when the callback is needed,
00216             the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
00217    */
00218 }
00219
00220 /**
00221   * @brief  SMARTCARD TX Fifo empty callback.
00222   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00223   *                   the configuration information for the specified SMARTCARD module.
00224   * @retval None
00225   */
00226 __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00227 {
00228   /* Prevent unused argument(s) compilation warning */
00229   UNUSED(hsmartcard);
00230
00231   /* NOTE : This function should not be modified, when the callback is needed,
00232             the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
00233    */
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
00241   *  @brief   SMARTCARD control functions
00242   *
00243 @verbatim
00244  ===============================================================================
00245                   ##### Peripheral FIFO Control functions #####
00246  ===============================================================================
00247     [..]
00248     This subsection provides a set of functions allowing to control the SMARTCARD
00249     FIFO feature.
00250      (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
00251      (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
00252      (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00253      (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00254 @endverbatim
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Enable the FIFO mode.
00260   * @param hsmartcard SMARTCARD handle.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00264 {
00265   uint32_t tmpcr1;
00266
00267   /* Check parameters */
00268   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00269
00270   /* Process Locked */
00271   __HAL_LOCK(hsmartcard);
00272
00273   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00274
00275   /* Save actual SMARTCARD configuration */
00276   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00277
00278   /* Disable SMARTCARD */
00279   __HAL_SMARTCARD_DISABLE(hsmartcard);
00280
00281   /* Enable FIFO mode */
00282   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00283   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
00284
00285   /* Restore SMARTCARD configuration */
00286   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00287
00288   /* Determine the number of data to process during RX/TX ISR execution */
00289   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00290
00291   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00292
00293   /* Process Unlocked */
00294   __HAL_UNLOCK(hsmartcard);
00295
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Disable the FIFO mode.
00301   * @param hsmartcard SMARTCARD handle.
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00305 {
00306   uint32_t tmpcr1;
00307
00308   /* Check parameters */
00309   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00310
00311   /* Process Locked */
00312   __HAL_LOCK(hsmartcard);
00313
00314   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00315
00316   /* Save actual SMARTCARD configuration */
00317   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00318
00319   /* Disable SMARTCARD */
00320   __HAL_SMARTCARD_DISABLE(hsmartcard);
00321
00322   /* Enable FIFO mode */
00323   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00324   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
00325
00326   /* Restore SMARTCARD configuration */
00327   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00328
00329   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00330
00331   /* Process Unlocked */
00332   __HAL_UNLOCK(hsmartcard);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Set the TXFIFO threshold.
00339   * @param hsmartcard      SMARTCARD handle.
00340   * @param Threshold  TX FIFO threshold value
00341   *          This parameter can be one of the following values:
00342   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
00343   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
00344   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
00345   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
00346   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
00347   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00351 {
00352   uint32_t tmpcr1;
00353
00354   /* Check parameters */
00355   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00356   assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
00357
00358   /* Process Locked */
00359   __HAL_LOCK(hsmartcard);
00360
00361   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00362
00363   /* Save actual SMARTCARD configuration */
00364   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00365
00366   /* Disable SMARTCARD */
00367   __HAL_SMARTCARD_DISABLE(hsmartcard);
00368
00369   /* Update TX threshold configuration */
00370   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00371
00372   /* Determine the number of data to process during RX/TX ISR execution */
00373   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00374
00375   /* Restore SMARTCARD configuration */
00376   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00377
00378   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00379
00380   /* Process Unlocked */
00381   __HAL_UNLOCK(hsmartcard);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Set the RXFIFO threshold.
00388   * @param hsmartcard      SMARTCARD handle.
00389   * @param Threshold  RX FIFO threshold value
00390   *          This parameter can be one of the following values:
00391   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
00392   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
00393   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
00394   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
00395   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
00396   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00400 {
00401   uint32_t tmpcr1;
00402
00403   /* Check parameters */
00404   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00405   assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsmartcard);
00409
00410   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00411
00412   /* Save actual SMARTCARD configuration */
00413   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00414
00415   /* Disable SMARTCARD */
00416   __HAL_SMARTCARD_DISABLE(hsmartcard);
00417
00418   /* Update RX threshold configuration */
00419   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00420
00421   /* Determine the number of data to process during RX/TX ISR execution */
00422   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00423
00424   /* Restore SMARTCARD configuration */
00425   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00426
00427   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00428
00429   /* Process Unlocked */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @}
00437   */
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
00444   * @{
00445   */
00446
00447 /**
00448   * @brief Calculate the number of data to process in RX/TX ISR.
00449   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00450   *       the USART configuration registers.
00451   * @param hsmartcard SMARTCARD handle.
00452   * @retval None
00453   */
00454 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
00455 {
00456   uint8_t rx_fifo_depth;
00457   uint8_t tx_fifo_depth;
00458   uint8_t rx_fifo_threshold;
00459   uint8_t tx_fifo_threshold;
00460   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00461   uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00462   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00463
00464   if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
00465   {
00466     hsmartcard->NbTxDataToProcess = 1U;
00467     hsmartcard->NbRxDataToProcess = 1U;
00468   }
00469   else
00470   {
00471     rx_fifo_depth = RX_FIFO_DEPTH;
00472     tx_fifo_depth = TX_FIFO_DEPTH;
00473     rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00474     tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00475     hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00476     hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00477   }
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00485
00486 /**
00487   * @}
00488   */
00489
00490 /**
00491   * @}
00492   */
00493
00494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smartcard_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_smartcard_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SMARTCARD_EX_H
00022 #define STM32H7xx_HAL_SMARTCARD_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMARTCARDEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00047   * @{
00048   */
00049 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00050 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00056   * @{
00057   */
00058 #define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
00059 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
00060 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
00061 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
00062 #define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
00063 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
00064 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
00065 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
00066 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
00072   * @brief    SMARTCARD FIFO mode
00073   * @{
00074   */
00075 #define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00076 #define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
00082   * @brief    SMARTCARD TXFIFO level
00083   * @{
00084   */
00085 #define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00086 #define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
00087 #define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
00088 #define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
00089 #define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
00090 #define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
00096   * @brief    SMARTCARD RXFIFO level
00097   * @{
00098   */
00099 #define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
00100 #define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
00101 #define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
00102 #define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
00103 #define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
00104 #define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00110   *        Elements values convention: 0xXXXX
00111   *           - 0xXXXX  : Flag mask in the ISR register
00112   * @{
00113   */
00114 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
00115 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
00116 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
00117 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
00118 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
00119 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
00120 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
00121 #define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
00122 #define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
00123 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
00124 #define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
00125 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
00126 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
00127 #define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
00128 #define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
00129 #define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
00130 #define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
00131 #define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
00132 #define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
00133 #define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00139   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00140   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00141   *           - XX  : Interrupt source register (2 bits)
00142   *                 - 01: CR1 register
00143   *                 - 10: CR2 register
00144   *                 - 11: CR3 register
00145   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00146   * @{
00147   */
00148 #define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
00149 #define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
00150 #define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
00151 #define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
00152 #define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
00153 #define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
00154 #define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
00155
00156 #define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
00157 #define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
00158 #define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
00159 #define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
00160
00161 #define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
00162 #define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
00163 #define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
00164
00165 #define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
00166 #define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
00167 #define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
00168 #define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00174   * @{
00175   */
00176 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00177 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00178 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
00179 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00180 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00181 #define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
00182 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00183 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00184 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00185 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193 /* Exported macros -----------------------------------------------------------*/
00194 /* Private macros ------------------------------------------------------------*/
00195 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00196   * @{
00197   */
00198
00199 /** @brief  Set the Transmission Completion flag
00200   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00201   * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
00202   *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
00203   *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
00204   * @retval None
00205   */
00206 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
00207   do {                                                                                                       \
00208     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
00209     {                                                                                                        \
00210       (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
00211     }                                                                                                        \
00212     else                                                                                                     \
00213     {                                                                                                        \
00214       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00215     }                                                                                                        \
00216   } while(0U)
00217
00218 /** @brief  Return the transmission completion flag.
00219   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00220   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00221   *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
00222   *        reported.
00223   * @retval Transmission completion flag
00224   */
00225 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
00226   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00227
00228
00229 /** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00230   * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
00231   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00232   */
00233 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
00234                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00235
00236 /** @brief Ensure that SMARTCARD FIFO mode is valid.
00237   * @param __STATE__ SMARTCARD FIFO mode.
00238   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00239   */
00240 #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
00241                                                 ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
00242
00243 /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
00244   * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
00245   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00246   */
00247 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
00248                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
00249                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
00250                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
00251                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
00252                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
00253
00254 /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
00255   * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
00256   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00257   */
00258 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
00259                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
00260                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
00261                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
00262                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
00263                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
00264
00265 /**
00266   * @}
00267   */
00268
00269 /* Exported functions --------------------------------------------------------*/
00270 /** @addtogroup SMARTCARDEx_Exported_Functions
00271   * @{
00272   */
00273
00274 /* Initialization and de-initialization functions  ****************************/
00275 /* IO operation methods *******************************************************/
00276
00277 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00278   * @{
00279   */
00280
00281 /* Peripheral Control functions ***********************************************/
00282 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00283 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00284 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00285 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00286
00287 /**
00288   * @}
00289   */
00290
00291 /* Exported functions --------------------------------------------------------*/
00292 /** @addtogroup SMARTCARDEx_Exported_Functions_Group2
00293   * @{
00294   */
00295
00296 /* IO operation functions *****************************************************/
00297 void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00298 void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @addtogroup SMARTCARDEx_Exported_Functions_Group3
00305   * @{
00306   */
00307
00308 /* Peripheral Control functions ***********************************************/
00309 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00310 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00311 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00312 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00313
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /* Private functions ---------------------------------------------------------*/
00323
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332 #ifdef __cplusplus
00333 }
00334 #endif
00335
00336 #endif /* STM32H7xx_HAL_SMARTCARD_EX_H */
00337
00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smbus.c Source File

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stm32h7xx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the System Management Bus (SMBus) peripheral,
00008   *          based on I2C principles of operation :
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     The SMBUS HAL driver can be used as follows:
00019
00020     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00021         SMBUS_HandleTypeDef  hsmbus;
00022
00023     (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
00024         (##) Enable the SMBUSx interface clock
00025         (##) SMBUS pins configuration
00026             (+++) Enable the clock for the SMBUS GPIOs
00027             (+++) Configure SMBUS pins as alternate function open-drain
00028         (##) NVIC configuration if you need to use interrupt process
00029             (+++) Configure the SMBUSx interrupt priority
00030             (+++) Enable the NVIC SMBUS IRQ Channel
00031
00032     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
00033         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00034         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00035
00036     (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
00037         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00038              by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
00039
00040     (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
00041
00042     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00043
00044     *** Interrupt mode IO operation ***
00045     ===================================
00046     [..]
00047       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
00048       (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
00049            add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
00050       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
00051       (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
00052            add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
00053       (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
00054       (++) The associated previous transfer callback is called at the end of abort process
00055       (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00056       (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00057       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00058            using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
00059       (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
00060            add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
00061       (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
00062            add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
00063       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
00064       (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
00065            add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
00066       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
00067       (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
00068            add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
00069       (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
00070       (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
00071            add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
00072            to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
00073       (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
00074       (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
00075            add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
00076            to check the Error Code using function @ref HAL_SMBUS_GetError()
00077
00078      *** SMBUS HAL driver macros list ***
00079      ==================================
00080      [..]
00081        Below the list of most used macros in SMBUS HAL driver.
00082
00083       (+) @ref __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
00084       (+) @ref __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
00085       (+) @ref __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
00086       (+) @ref __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
00087       (+) @ref __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
00088       (+) @ref __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
00089
00090      *** Callback registration ***
00091      =============================================
00092     [..]
00093      The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
00094      allows the user to configure dynamically the driver callbacks.
00095      Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
00096      to register an interrupt callback.
00097     [..]
00098      Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
00099        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00100        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00101        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00102        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00103        (+) ListenCpltCallback   : callback for end of listen mode.
00104        (+) ErrorCallback        : callback for error detection.
00105        (+) MspInitCallback      : callback for Msp Init.
00106        (+) MspDeInitCallback    : callback for Msp DeInit.
00107      This function takes as parameters the HAL peripheral handle, the Callback ID
00108      and a pointer to the user callback function.
00109     [..]
00110      For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
00111     [..]
00112      Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
00113      weak function.
00114      @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
00115      and the Callback ID.
00116      This function allows to reset following callbacks:
00117        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00118        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00119        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00120        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00121        (+) ListenCpltCallback   : callback for end of listen mode.
00122        (+) ErrorCallback        : callback for error detection.
00123        (+) MspInitCallback      : callback for Msp Init.
00124        (+) MspDeInitCallback    : callback for Msp DeInit.
00125     [..]
00126      For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
00127     [..]
00128      By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
00129      all callbacks are set to the corresponding weak functions:
00130      examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
00131      Exception done for MspInit and MspDeInit functions that are
00132      reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
00133      these callbacks are null (not registered beforehand).
00134      If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
00135      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00136     [..]
00137      Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
00138      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00139      in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
00140      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00141      Then, the user first registers the MspInit/MspDeInit user callbacks
00142      using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
00143      or @ref HAL_SMBUS_Init() function.
00144     [..]
00145      When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
00146      not defined, the callback registration feature is not available and all callbacks
00147      are set to the corresponding weak functions.
00148
00149      [..]
00150        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00151
00152   @endverbatim
00153   ******************************************************************************
00154   * @attention
00155   *
00156   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00157   * All rights reserved.</center></h2>
00158   *
00159   * This software component is licensed by ST under BSD 3-Clause license,
00160   * the "License"; You may not use this file except in compliance with the
00161   * License. You may obtain a copy of the License at:
00162   *                        opensource.org/licenses/BSD-3-Clause
00163   *
00164   ******************************************************************************
00165   */
00166
00167 /* Includes ------------------------------------------------------------------*/
00168 #include "stm32h7xx_hal.h"
00169
00170 /** @addtogroup STM32H7xx_HAL_Driver
00171   * @{
00172   */
00173
00174 /** @defgroup SMBUS SMBUS
00175   * @brief SMBUS HAL module driver
00176   * @{
00177   */
00178
00179 #ifdef HAL_SMBUS_MODULE_ENABLED
00180
00181 /* Private typedef -----------------------------------------------------------*/
00182 /* Private constants ---------------------------------------------------------*/
00183 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00184   * @{
00185   */
00186 #define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
00187 #define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
00188 #define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
00189 #define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
00190 #define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
00191 #define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
00192 #define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
00193 #define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
00194 #define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
00195 #define MAX_NBYTE_SIZE      255U
00196 /**
00197   * @}
00198   */
00199
00200 /* Private macro -------------------------------------------------------------*/
00201 /* Private variables ---------------------------------------------------------*/
00202 /* Private function prototypes -----------------------------------------------*/
00203 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00204   * @{
00205   */
00206 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00207
00208 static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00209 static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00210 static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00211 static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00212
00213 static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
00214
00215 static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
00216
00217 static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00218 /**
00219   * @}
00220   */
00221
00222 /* Exported functions --------------------------------------------------------*/
00223
00224 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00225   * @{
00226   */
00227
00228 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00229  *  @brief    Initialization and Configuration functions
00230  *
00231 @verbatim
00232  ===============================================================================
00233               ##### Initialization and de-initialization functions #####
00234  ===============================================================================
00235     [..]  This subsection provides a set of functions allowing to initialize and
00236           deinitialize the SMBUSx peripheral:
00237
00238       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00239           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00240
00241       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00242           the selected configuration:
00243         (++) Clock Timing
00244         (++) Bus Timeout
00245         (++) Analog Filer mode
00246         (++) Own Address 1
00247         (++) Addressing mode (Master, Slave)
00248         (++) Dual Addressing mode
00249         (++) Own Address 2
00250         (++) Own Address 2 Mask
00251         (++) General call mode
00252         (++) Nostretch mode
00253         (++) Packet Error Check mode
00254         (++) Peripheral mode
00255
00256
00257       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00258           of the selected SMBUSx peripheral.
00259
00260       (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
00261           HAL_SMBUS_ConfigDigitalFilter().
00262
00263 @endverbatim
00264   * @{
00265   */
00266
00267 /**
00268   * @brief  Initialize the SMBUS according to the specified parameters
00269   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00270   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00271   *                the configuration information for the specified SMBUS.
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00275 {
00276   /* Check the SMBUS handle allocation */
00277   if (hsmbus == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameters */
00283   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00284   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00285   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00286   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00287   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00288   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00289   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00290   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00291   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00292   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00293   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00294
00295   if (hsmbus->State == HAL_SMBUS_STATE_RESET)
00296   {
00297     /* Allocate lock resource and initialize it */
00298     hsmbus->Lock = HAL_UNLOCKED;
00299
00300 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00301     hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00302     hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00303     hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00304     hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00305     hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00306     hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
00307     hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
00308
00309     if (hsmbus->MspInitCallback == NULL)
00310     {
00311       hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
00312     }
00313
00314     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00315     hsmbus->MspInitCallback(hsmbus);
00316 #else
00317     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00318     HAL_SMBUS_MspInit(hsmbus);
00319 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00320   }
00321
00322   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00323
00324   /* Disable the selected SMBUS peripheral */
00325   __HAL_SMBUS_DISABLE(hsmbus);
00326
00327   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00328   /* Configure SMBUSx: Frequency range */
00329   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00330
00331   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00332   /* Configure SMBUSx: Bus Timeout  */
00333   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00334   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00335   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00336
00337   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00338   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00339   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00340
00341   if (hsmbus->Init.OwnAddress1 != 0UL)
00342   {
00343     if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00344     {
00345       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00346     }
00347     else /* SMBUS_ADDRESSINGMODE_10BIT */
00348     {
00349       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00350     }
00351   }
00352
00353   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00354   /* Configure SMBUSx: Addressing Master mode */
00355   if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00356   {
00357     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00358   }
00359   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00360   /* AUTOEND and NACK bit will be manage during Transfer process */
00361   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00362
00363   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00364   /* Configure SMBUSx: Dual mode and Own Address2 */
00365   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
00366
00367   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00368   /* Configure SMBUSx: Generalcall and NoStretch mode */
00369   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
00370
00371   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
00372   if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
00373       && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
00374   {
00375     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00376   }
00377
00378   /* Enable the selected SMBUS peripheral */
00379   __HAL_SMBUS_ENABLE(hsmbus);
00380
00381   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00382   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00383   hsmbus->State = HAL_SMBUS_STATE_READY;
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  DeInitialize the SMBUS peripheral.
00390   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00391   *                the configuration information for the specified SMBUS.
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00395 {
00396   /* Check the SMBUS handle allocation */
00397   if (hsmbus == NULL)
00398   {
00399     return HAL_ERROR;
00400   }
00401
00402   /* Check the parameters */
00403   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00404
00405   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00406
00407   /* Disable the SMBUS Peripheral Clock */
00408   __HAL_SMBUS_DISABLE(hsmbus);
00409
00410 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00411   if (hsmbus->MspDeInitCallback == NULL)
00412   {
00413     hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
00414   }
00415
00416   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00417   hsmbus->MspDeInitCallback(hsmbus);
00418 #else
00419   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00420   HAL_SMBUS_MspDeInit(hsmbus);
00421 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00422
00423   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00424   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00425   hsmbus->State = HAL_SMBUS_STATE_RESET;
00426
00427   /* Release Lock */
00428   __HAL_UNLOCK(hsmbus);
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief Initialize the SMBUS MSP.
00435   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00436   *                the configuration information for the specified SMBUS.
00437   * @retval None
00438   */
00439 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00440 {
00441   /* Prevent unused argument(s) compilation warning */
00442   UNUSED(hsmbus);
00443
00444   /* NOTE : This function should not be modified, when the callback is needed,
00445             the HAL_SMBUS_MspInit could be implemented in the user file
00446    */
00447 }
00448
00449 /**
00450   * @brief DeInitialize the SMBUS MSP.
00451   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00452   *                the configuration information for the specified SMBUS.
00453   * @retval None
00454   */
00455 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00456 {
00457   /* Prevent unused argument(s) compilation warning */
00458   UNUSED(hsmbus);
00459
00460   /* NOTE : This function should not be modified, when the callback is needed,
00461             the HAL_SMBUS_MspDeInit could be implemented in the user file
00462    */
00463 }
00464
00465 /**
00466   * @brief  Configure Analog noise filter.
00467   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00468   *                the configuration information for the specified SMBUS.
00469   * @param  AnalogFilter This parameter can be one of the following values:
00470   *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
00471   *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
00475 {
00476   /* Check the parameters */
00477   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00478   assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
00479
00480   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00481   {
00482     /* Process Locked */
00483     __HAL_LOCK(hsmbus);
00484
00485     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00486
00487     /* Disable the selected SMBUS peripheral */
00488     __HAL_SMBUS_DISABLE(hsmbus);
00489
00490     /* Reset ANOFF bit */
00491     hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00492
00493     /* Set analog filter bit*/
00494     hsmbus->Instance->CR1 |= AnalogFilter;
00495
00496     __HAL_SMBUS_ENABLE(hsmbus);
00497
00498     hsmbus->State = HAL_SMBUS_STATE_READY;
00499
00500     /* Process Unlocked */
00501     __HAL_UNLOCK(hsmbus);
00502
00503     return HAL_OK;
00504   }
00505   else
00506   {
00507     return HAL_BUSY;
00508   }
00509 }
00510
00511 /**
00512   * @brief  Configure Digital noise filter.
00513   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00514   *                the configuration information for the specified SMBUS.
00515   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
00519 {
00520   uint32_t tmpreg;
00521
00522   /* Check the parameters */
00523   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00524   assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
00525
00526   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00527   {
00528     /* Process Locked */
00529     __HAL_LOCK(hsmbus);
00530
00531     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00532
00533     /* Disable the selected SMBUS peripheral */
00534     __HAL_SMBUS_DISABLE(hsmbus);
00535
00536     /* Get the old register value */
00537     tmpreg = hsmbus->Instance->CR1;
00538
00539     /* Reset I2C DNF bits [11:8] */
00540     tmpreg &= ~(I2C_CR1_DNF);
00541
00542     /* Set I2Cx DNF coefficient */
00543     tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
00544
00545     /* Store the new register value */
00546     hsmbus->Instance->CR1 = tmpreg;
00547
00548     __HAL_SMBUS_ENABLE(hsmbus);
00549
00550     hsmbus->State = HAL_SMBUS_STATE_READY;
00551
00552     /* Process Unlocked */
00553     __HAL_UNLOCK(hsmbus);
00554
00555     return HAL_OK;
00556   }
00557   else
00558   {
00559     return HAL_BUSY;
00560   }
00561 }
00562
00563 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00564 /**
00565   * @brief  Register a User SMBUS Callback
00566   *         To be used instead of the weak predefined callback
00567   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00568   *                the configuration information for the specified SMBUS.
00569   * @param  CallbackID ID of the callback to be registered
00570   *         This parameter can be one of the following values:
00571   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00572   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00573   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00574   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00575   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00576   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00577   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00578   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00579   * @param  pCallback pointer to the Callback function
00580   * @retval HAL status
00581   */
00582 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
00583 {
00584   HAL_StatusTypeDef status = HAL_OK;
00585
00586   if (pCallback == NULL)
00587   {
00588     /* Update the error code */
00589     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00590
00591     return HAL_ERROR;
00592   }
00593
00594   /* Process locked */
00595   __HAL_LOCK(hsmbus);
00596
00597   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00598   {
00599     switch (CallbackID)
00600     {
00601       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00602         hsmbus->MasterTxCpltCallback = pCallback;
00603         break;
00604
00605       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00606         hsmbus->MasterRxCpltCallback = pCallback;
00607         break;
00608
00609       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00610         hsmbus->SlaveTxCpltCallback = pCallback;
00611         break;
00612
00613       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00614         hsmbus->SlaveRxCpltCallback = pCallback;
00615         break;
00616
00617       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00618         hsmbus->ListenCpltCallback = pCallback;
00619         break;
00620
00621       case HAL_SMBUS_ERROR_CB_ID :
00622         hsmbus->ErrorCallback = pCallback;
00623         break;
00624
00625       case HAL_SMBUS_MSPINIT_CB_ID :
00626         hsmbus->MspInitCallback = pCallback;
00627         break;
00628
00629       case HAL_SMBUS_MSPDEINIT_CB_ID :
00630         hsmbus->MspDeInitCallback = pCallback;
00631         break;
00632
00633       default :
00634         /* Update the error code */
00635         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00636
00637         /* Return error status */
00638         status =  HAL_ERROR;
00639         break;
00640     }
00641   }
00642   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00643   {
00644     switch (CallbackID)
00645     {
00646       case HAL_SMBUS_MSPINIT_CB_ID :
00647         hsmbus->MspInitCallback = pCallback;
00648         break;
00649
00650       case HAL_SMBUS_MSPDEINIT_CB_ID :
00651         hsmbus->MspDeInitCallback = pCallback;
00652         break;
00653
00654       default :
00655         /* Update the error code */
00656         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00657
00658         /* Return error status */
00659         status =  HAL_ERROR;
00660         break;
00661     }
00662   }
00663   else
00664   {
00665     /* Update the error code */
00666     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00667
00668     /* Return error status */
00669     status =  HAL_ERROR;
00670   }
00671
00672   /* Release Lock */
00673   __HAL_UNLOCK(hsmbus);
00674   return status;
00675 }
00676
00677 /**
00678   * @brief  Unregister an SMBUS Callback
00679   *         SMBUS callback is redirected to the weak predefined callback
00680   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00681   *                the configuration information for the specified SMBUS.
00682   * @param  CallbackID ID of the callback to be unregistered
00683   *         This parameter can be one of the following values:
00684   *         This parameter can be one of the following values:
00685   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00686   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00687   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00688   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00689   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00690   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00691   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00692   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00693   * @retval HAL status
00694   */
00695 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
00696 {
00697   HAL_StatusTypeDef status = HAL_OK;
00698
00699   /* Process locked */
00700   __HAL_LOCK(hsmbus);
00701
00702   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00703   {
00704     switch (CallbackID)
00705     {
00706       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00707         hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00708         break;
00709
00710       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00711         hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00712         break;
00713
00714       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00715         hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00716         break;
00717
00718       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00719         hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00720         break;
00721
00722       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00723         hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00724         break;
00725
00726       case HAL_SMBUS_ERROR_CB_ID :
00727         hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
00728         break;
00729
00730       case HAL_SMBUS_MSPINIT_CB_ID :
00731         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00732         break;
00733
00734       case HAL_SMBUS_MSPDEINIT_CB_ID :
00735         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00736         break;
00737
00738       default :
00739         /* Update the error code */
00740         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00741
00742         /* Return error status */
00743         status =  HAL_ERROR;
00744         break;
00745     }
00746   }
00747   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00748   {
00749     switch (CallbackID)
00750     {
00751       case HAL_SMBUS_MSPINIT_CB_ID :
00752         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00753         break;
00754
00755       case HAL_SMBUS_MSPDEINIT_CB_ID :
00756         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00757         break;
00758
00759       default :
00760         /* Update the error code */
00761         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00762
00763         /* Return error status */
00764         status =  HAL_ERROR;
00765         break;
00766     }
00767   }
00768   else
00769   {
00770     /* Update the error code */
00771     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00772
00773     /* Return error status */
00774     status =  HAL_ERROR;
00775   }
00776
00777   /* Release Lock */
00778   __HAL_UNLOCK(hsmbus);
00779   return status;
00780 }
00781
00782 /**
00783   * @brief  Register the Slave Address Match SMBUS Callback
00784   *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
00785   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00786   *                the configuration information for the specified SMBUS.
00787   * @param  pCallback pointer to the Address Match Callback function
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
00791 {
00792   HAL_StatusTypeDef status = HAL_OK;
00793
00794   if (pCallback == NULL)
00795   {
00796     /* Update the error code */
00797     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00798
00799     return HAL_ERROR;
00800   }
00801   /* Process locked */
00802   __HAL_LOCK(hsmbus);
00803
00804   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00805   {
00806     hsmbus->AddrCallback = pCallback;
00807   }
00808   else
00809   {
00810     /* Update the error code */
00811     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00812
00813     /* Return error status */
00814     status =  HAL_ERROR;
00815   }
00816
00817   /* Release Lock */
00818   __HAL_UNLOCK(hsmbus);
00819   return status;
00820 }
00821
00822 /**
00823   * @brief  UnRegister the Slave Address Match SMBUS Callback
00824   *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
00825   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00826   *                the configuration information for the specified SMBUS.
00827   * @retval HAL status
00828   */
00829 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
00830 {
00831   HAL_StatusTypeDef status = HAL_OK;
00832
00833   /* Process locked */
00834   __HAL_LOCK(hsmbus);
00835
00836   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00837   {
00838     hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
00839   }
00840   else
00841   {
00842     /* Update the error code */
00843     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00844
00845     /* Return error status */
00846     status =  HAL_ERROR;
00847   }
00848
00849   /* Release Lock */
00850   __HAL_UNLOCK(hsmbus);
00851   return status;
00852 }
00853
00854 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00855
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00861  *  @brief   Data transfers functions
00862  *
00863 @verbatim
00864  ===============================================================================
00865                       ##### IO operation functions #####
00866  ===============================================================================
00867     [..]
00868     This subsection provides a set of functions allowing to manage the SMBUS data
00869     transfers.
00870
00871     (#) Blocking mode function to check if device is ready for usage is :
00872         (++) HAL_SMBUS_IsDeviceReady()
00873
00874     (#) There is only one mode of transfer:
00875        (++) Non-Blocking mode : The communication is performed using Interrupts.
00876             These functions return the status of the transfer startup.
00877             The end of the data processing will be indicated through the
00878             dedicated SMBUS IRQ when using Interrupt mode.
00879
00880     (#) Non-Blocking mode functions with Interrupt are :
00881         (++) HAL_SMBUS_Master_Transmit_IT()
00882         (++) HAL_SMBUS_Master_Receive_IT()
00883         (++) HAL_SMBUS_Slave_Transmit_IT()
00884         (++) HAL_SMBUS_Slave_Receive_IT()
00885         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00886         (++) HAL_SMBUS_DisableListen_IT()
00887         (++) HAL_SMBUS_EnableAlert_IT()
00888         (++) HAL_SMBUS_DisableAlert_IT()
00889
00890     (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
00891         (++) HAL_SMBUS_MasterTxCpltCallback()
00892         (++) HAL_SMBUS_MasterRxCpltCallback()
00893         (++) HAL_SMBUS_SlaveTxCpltCallback()
00894         (++) HAL_SMBUS_SlaveRxCpltCallback()
00895         (++) HAL_SMBUS_AddrCallback()
00896         (++) HAL_SMBUS_ListenCpltCallback()
00897         (++) HAL_SMBUS_ErrorCallback()
00898
00899 @endverbatim
00900   * @{
00901   */
00902
00903 /**
00904   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00905   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00906   *                the configuration information for the specified SMBUS.
00907   * @param  DevAddress Target device address: The device 7 bits address value
00908   *         in datasheet must be shifted to the left before calling the interface
00909   * @param  pData Pointer to data buffer
00910   * @param  Size Amount of data to be sent
00911   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00912   * @retval HAL status
00913   */
00914 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00915 {
00916   uint32_t tmp;
00917
00918   /* Check the parameters */
00919   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00920
00921   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00922   {
00923     /* Process Locked */
00924     __HAL_LOCK(hsmbus);
00925
00926     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00927     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00928     /* Prepare transfer parameters */
00929     hsmbus->pBuffPtr = pData;
00930     hsmbus->XferCount = Size;
00931     hsmbus->XferOptions = XferOptions;
00932
00933     /* In case of Quick command, remove autoend mode */
00934     /* Manage the stop generation by software */
00935     if (hsmbus->pBuffPtr == NULL)
00936     {
00937       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00938     }
00939
00940     if (Size > MAX_NBYTE_SIZE)
00941     {
00942       hsmbus->XferSize = MAX_NBYTE_SIZE;
00943     }
00944     else
00945     {
00946       hsmbus->XferSize = Size;
00947     }
00948
00949     /* Send Slave Address */
00950     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00951     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
00952     {
00953       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
00954     }
00955     else
00956     {
00957       /* If transfer direction not change, do not generate Restart Condition */
00958       /* Mean Previous state is same as current state */
00959
00960       /* Store current volatile XferOptions, misra rule */
00961       tmp = hsmbus->XferOptions;
00962
00963       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
00964       {
00965         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00966       }
00967       /* Else transfer direction change, so generate Restart with new transfer direction */
00968       else
00969       {
00970         /* Convert OTHER_xxx XferOptions if any */
00971         SMBUS_ConvertOtherXferOptions(hsmbus);
00972
00973         /* Handle Transfer */
00974         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
00975       }
00976
00977       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00978       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00979       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
00980       {
00981         hsmbus->XferSize--;
00982         hsmbus->XferCount--;
00983       }
00984     }
00985
00986     /* Process Unlocked */
00987     __HAL_UNLOCK(hsmbus);
00988
00989     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00990               to avoid the risk of SMBUS interrupt handle execution before current
00991               process unlock */
00992     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00993
00994     return HAL_OK;
00995   }
00996   else
00997   {
00998     return HAL_BUSY;
00999   }
01000 }
01001
01002 /**
01003   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
01004   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01005   *                the configuration information for the specified SMBUS.
01006   * @param  DevAddress Target device address: The device 7 bits address value
01007   *         in datasheet must be shifted to the left before calling the interface
01008   * @param  pData Pointer to data buffer
01009   * @param  Size Amount of data to be sent
01010   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01011   * @retval HAL status
01012   */
01013 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01014 {
01015   uint32_t tmp;
01016
01017   /* Check the parameters */
01018   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01019
01020   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01021   {
01022     /* Process Locked */
01023     __HAL_LOCK(hsmbus);
01024
01025     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01026     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01027
01028     /* Prepare transfer parameters */
01029     hsmbus->pBuffPtr = pData;
01030     hsmbus->XferCount = Size;
01031     hsmbus->XferOptions = XferOptions;
01032
01033     /* In case of Quick command, remove autoend mode */
01034     /* Manage the stop generation by software */
01035     if (hsmbus->pBuffPtr == NULL)
01036     {
01037       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
01038     }
01039
01040     if (Size > MAX_NBYTE_SIZE)
01041     {
01042       hsmbus->XferSize = MAX_NBYTE_SIZE;
01043     }
01044     else
01045     {
01046       hsmbus->XferSize = Size;
01047     }
01048
01049     /* Send Slave Address */
01050     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01051     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01052     {
01053       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
01054     }
01055     else
01056     {
01057       /* If transfer direction not change, do not generate Restart Condition */
01058       /* Mean Previous state is same as current state */
01059
01060       /* Store current volatile XferOptions, Misra rule */
01061       tmp = hsmbus->XferOptions;
01062
01063       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
01064       {
01065         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01066       }
01067       /* Else transfer direction change, so generate Restart with new transfer direction */
01068       else
01069       {
01070         /* Convert OTHER_xxx XferOptions if any */
01071         SMBUS_ConvertOtherXferOptions(hsmbus);
01072
01073         /* Handle Transfer */
01074         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
01075       }
01076     }
01077
01078     /* Process Unlocked */
01079     __HAL_UNLOCK(hsmbus);
01080
01081     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01082               to avoid the risk of SMBUS interrupt handle execution before current
01083               process unlock */
01084     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01085
01086     return HAL_OK;
01087   }
01088   else
01089   {
01090     return HAL_BUSY;
01091   }
01092 }
01093
01094 /**
01095   * @brief  Abort a master/host SMBUS process communication with Interrupt.
01096   * @note   This abort can be called only if state is ready
01097   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01098   *                the configuration information for the specified SMBUS.
01099   * @param  DevAddress Target device address: The device 7 bits address value
01100   *         in datasheet must be shifted to the left before calling the interface
01101   * @retval HAL status
01102   */
01103 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
01104 {
01105   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01106   {
01107     /* Process Locked */
01108     __HAL_LOCK(hsmbus);
01109
01110     /* Keep the same state as previous */
01111     /* to perform as well the call of the corresponding end of transfer callback */
01112     if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01113     {
01114       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
01115     }
01116     else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01117     {
01118       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01119     }
01120     else
01121     {
01122       /* Wrong usage of abort function */
01123       /* This function should be used only in case of abort monitored by master device */
01124       return HAL_ERROR;
01125     }
01126     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01127
01128     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
01129     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
01130     SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
01131
01132     /* Process Unlocked */
01133     __HAL_UNLOCK(hsmbus);
01134
01135     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01136               to avoid the risk of SMBUS interrupt handle execution before current
01137               process unlock */
01138     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01139     {
01140       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01141     }
01142     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01143     {
01144       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01145     }
01146     else
01147     {
01148       /* Nothing to do */
01149     }
01150
01151     return HAL_OK;
01152   }
01153   else
01154   {
01155     return HAL_BUSY;
01156   }
01157 }
01158
01159 /**
01160   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01161   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01162   *                the configuration information for the specified SMBUS.
01163   * @param  pData Pointer to data buffer
01164   * @param  Size Amount of data to be sent
01165   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01166   * @retval HAL status
01167   */
01168 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01169 {
01170   /* Check the parameters */
01171   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01172
01173   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01174   {
01175     if ((pData == NULL) || (Size == 0UL))
01176     {
01177       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01178       return HAL_ERROR;
01179     }
01180
01181     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01182     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
01183
01184     /* Process Locked */
01185     __HAL_LOCK(hsmbus);
01186
01187     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
01188     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01189
01190     /* Set SBC bit to manage Acknowledge at each bit */
01191     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01192
01193     /* Enable Address Acknowledge */
01194     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01195
01196     /* Prepare transfer parameters */
01197     hsmbus->pBuffPtr = pData;
01198     hsmbus->XferCount = Size;
01199     hsmbus->XferOptions = XferOptions;
01200
01201     /* Convert OTHER_xxx XferOptions if any */
01202     SMBUS_ConvertOtherXferOptions(hsmbus);
01203
01204     if (Size > MAX_NBYTE_SIZE)
01205     {
01206       hsmbus->XferSize = MAX_NBYTE_SIZE;
01207     }
01208     else
01209     {
01210       hsmbus->XferSize = Size;
01211     }
01212
01213     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01214     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01215     {
01216       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
01217     }
01218     else
01219     {
01220       /* Set NBYTE to transmit */
01221       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01222
01223       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01224       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01225       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01226       {
01227         hsmbus->XferSize--;
01228         hsmbus->XferCount--;
01229       }
01230     }
01231
01232     /* Clear ADDR flag after prepare the transfer parameters */
01233     /* This action will generate an acknowledge to the HOST */
01234     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01235
01236     /* Process Unlocked */
01237     __HAL_UNLOCK(hsmbus);
01238
01239     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01240               to avoid the risk of SMBUS interrupt handle execution before current
01241               process unlock */
01242     /* REnable ADDR interrupt */
01243     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
01244
01245     return HAL_OK;
01246   }
01247   else
01248   {
01249     return HAL_BUSY;
01250   }
01251 }
01252
01253 /**
01254   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01255   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01256   *                the configuration information for the specified SMBUS.
01257   * @param  pData Pointer to data buffer
01258   * @param  Size Amount of data to be sent
01259   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01260   * @retval HAL status
01261   */
01262 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01263 {
01264   /* Check the parameters */
01265   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01266
01267   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01268   {
01269     if ((pData == NULL) || (Size == 0UL))
01270     {
01271       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01272       return HAL_ERROR;
01273     }
01274
01275     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01276     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
01277
01278     /* Process Locked */
01279     __HAL_LOCK(hsmbus);
01280
01281     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
01282     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01283
01284     /* Set SBC bit to manage Acknowledge at each bit */
01285     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01286
01287     /* Enable Address Acknowledge */
01288     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01289
01290     /* Prepare transfer parameters */
01291     hsmbus->pBuffPtr = pData;
01292     hsmbus->XferSize = Size;
01293     hsmbus->XferCount = Size;
01294     hsmbus->XferOptions = XferOptions;
01295
01296     /* Convert OTHER_xxx XferOptions if any */
01297     SMBUS_ConvertOtherXferOptions(hsmbus);
01298
01299     /* Set NBYTE to receive */
01300     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
01301     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
01302     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
01303     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
01304     if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
01305     {
01306       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01307     }
01308     else
01309     {
01310       SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
01311     }
01312
01313     /* Clear ADDR flag after prepare the transfer parameters */
01314     /* This action will generate an acknowledge to the HOST */
01315     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01316
01317     /* Process Unlocked */
01318     __HAL_UNLOCK(hsmbus);
01319
01320     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01321               to avoid the risk of SMBUS interrupt handle execution before current
01322               process unlock */
01323     /* REnable ADDR interrupt */
01324     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
01325
01326     return HAL_OK;
01327   }
01328   else
01329   {
01330     return HAL_BUSY;
01331   }
01332 }
01333
01334 /**
01335   * @brief  Enable the Address listen mode with Interrupt.
01336   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01337   *                the configuration information for the specified SMBUS.
01338   * @retval HAL status
01339   */
01340 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01341 {
01342   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01343
01344   /* Enable the Address Match interrupt */
01345   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
01346
01347   return HAL_OK;
01348 }
01349
01350 /**
01351   * @brief  Disable the Address listen mode with Interrupt.
01352   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01353   *                the configuration information for the specified SMBUS.
01354   * @retval HAL status
01355   */
01356 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01357 {
01358   /* Disable Address listen mode only if a transfer is not ongoing */
01359   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01360   {
01361     hsmbus->State = HAL_SMBUS_STATE_READY;
01362
01363     /* Disable the Address Match interrupt */
01364     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01365
01366     return HAL_OK;
01367   }
01368   else
01369   {
01370     return HAL_BUSY;
01371   }
01372 }
01373
01374 /**
01375   * @brief  Enable the SMBUS alert mode with Interrupt.
01376   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01377   *                the configuration information for the specified SMBUSx peripheral.
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01381 {
01382   /* Enable SMBus alert */
01383   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
01384
01385   /* Clear ALERT flag */
01386   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01387
01388   /* Enable Alert Interrupt */
01389   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
01390
01391   return HAL_OK;
01392 }
01393 /**
01394   * @brief  Disable the SMBUS alert mode with Interrupt.
01395   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01396   *                the configuration information for the specified SMBUSx peripheral.
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01400 {
01401   /* Enable SMBus alert */
01402   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
01403
01404   /* Disable Alert Interrupt */
01405   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
01406
01407   return HAL_OK;
01408 }
01409
01410 /**
01411   * @brief  Check if target device is ready for communication.
01412   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01413   *                the configuration information for the specified SMBUS.
01414   * @param  DevAddress Target device address: The device 7 bits address value
01415   *         in datasheet must be shifted to the left before calling the interface
01416   * @param  Trials Number of trials
01417   * @param  Timeout Timeout duration
01418   * @retval HAL status
01419   */
01420 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
01421 {
01422   uint32_t tickstart;
01423
01424   __IO uint32_t SMBUS_Trials = 0UL;
01425
01426   FlagStatus tmp1;
01427   FlagStatus tmp2;
01428
01429   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01430   {
01431     if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
01432     {
01433       return HAL_BUSY;
01434     }
01435
01436     /* Process Locked */
01437     __HAL_LOCK(hsmbus);
01438
01439     hsmbus->State = HAL_SMBUS_STATE_BUSY;
01440     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01441
01442     do
01443     {
01444       /* Generate Start */
01445       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
01446
01447       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01448       /* Wait until STOPF flag is set or a NACK flag is set*/
01449       tickstart = HAL_GetTick();
01450
01451       tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01452       tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01453
01454       while ((tmp1 == RESET) && (tmp2 == RESET))
01455       {
01456         if (Timeout != HAL_MAX_DELAY)
01457         {
01458           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01459           {
01460             /* Device is ready */
01461             hsmbus->State = HAL_SMBUS_STATE_READY;
01462
01463             /* Update SMBUS error code */
01464             hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01465
01466             /* Process Unlocked */
01467             __HAL_UNLOCK(hsmbus);
01468             return HAL_ERROR;
01469           }
01470         }
01471
01472         tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01473         tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01474       }
01475
01476       /* Check if the NACKF flag has not been set */
01477       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
01478       {
01479         /* Wait until STOPF flag is reset */
01480         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01481         {
01482           return HAL_ERROR;
01483         }
01484
01485         /* Clear STOP Flag */
01486         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01487
01488         /* Device is ready */
01489         hsmbus->State = HAL_SMBUS_STATE_READY;
01490
01491         /* Process Unlocked */
01492         __HAL_UNLOCK(hsmbus);
01493
01494         return HAL_OK;
01495       }
01496       else
01497       {
01498         /* Wait until STOPF flag is reset */
01499         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01500         {
01501           return HAL_ERROR;
01502         }
01503
01504         /* Clear NACK Flag */
01505         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01506
01507         /* Clear STOP Flag, auto generated with autoend*/
01508         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01509       }
01510
01511       /* Check if the maximum allowed number of trials has been reached */
01512       if (SMBUS_Trials == Trials)
01513       {
01514         /* Generate Stop */
01515         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01516
01517         /* Wait until STOPF flag is reset */
01518         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01519         {
01520           return HAL_ERROR;
01521         }
01522
01523         /* Clear STOP Flag */
01524         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01525       }
01526
01527       /* Increment Trials */
01528       SMBUS_Trials++;
01529     }
01530     while (SMBUS_Trials < Trials);
01531
01532     hsmbus->State = HAL_SMBUS_STATE_READY;
01533
01534     /* Update SMBUS error code */
01535     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01536
01537     /* Process Unlocked */
01538     __HAL_UNLOCK(hsmbus);
01539
01540     return HAL_ERROR;
01541   }
01542   else
01543   {
01544     return HAL_BUSY;
01545   }
01546 }
01547 /**
01548   * @}
01549   */
01550
01551 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01552  * @{
01553  */
01554
01555 /**
01556   * @brief  Handle SMBUS event interrupt request.
01557   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01558   *                the configuration information for the specified SMBUS.
01559   * @retval None
01560   */
01561 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01562 {
01563   /* Use a local variable to store the current ISR flags */
01564   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01565   uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
01566   uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
01567
01568   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01569   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01570   {
01571     /* Slave mode selected */
01572     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01573     {
01574       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01575     }
01576     /* Master mode selected */
01577     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01578     {
01579       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01580     }
01581     else
01582     {
01583       /* Nothing to do */
01584     }
01585   }
01586
01587   /* SMBUS in mode Receiver ----------------------------------------------------*/
01588   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01589   {
01590     /* Slave mode selected */
01591     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01592     {
01593       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01594     }
01595     /* Master mode selected */
01596     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01597     {
01598       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01599     }
01600     else
01601     {
01602       /* Nothing to do */
01603     }
01604   }
01605
01606   /* SMBUS in mode Listener Only --------------------------------------------------*/
01607   if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01608   {
01609     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01610     {
01611       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01612     }
01613   }
01614 }
01615
01616 /**
01617   * @brief  Handle SMBUS error interrupt request.
01618   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01619   *                the configuration information for the specified SMBUS.
01620   * @retval None
01621   */
01622 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01623 {
01624   SMBUS_ITErrorHandler(hsmbus);
01625 }
01626
01627 /**
01628   * @brief  Master Tx Transfer completed callback.
01629   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01630   *                the configuration information for the specified SMBUS.
01631   * @retval None
01632   */
01633 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01634 {
01635   /* Prevent unused argument(s) compilation warning */
01636   UNUSED(hsmbus);
01637
01638   /* NOTE : This function should not be modified, when the callback is needed,
01639             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01640    */
01641 }
01642
01643 /**
01644   * @brief  Master Rx Transfer completed callback.
01645   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01646   *                the configuration information for the specified SMBUS.
01647   * @retval None
01648   */
01649 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01650 {
01651   /* Prevent unused argument(s) compilation warning */
01652   UNUSED(hsmbus);
01653
01654   /* NOTE : This function should not be modified, when the callback is needed,
01655             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01656    */
01657 }
01658
01659 /** @brief  Slave Tx Transfer completed callback.
01660   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01661   *                the configuration information for the specified SMBUS.
01662   * @retval None
01663   */
01664 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01665 {
01666   /* Prevent unused argument(s) compilation warning */
01667   UNUSED(hsmbus);
01668
01669   /* NOTE : This function should not be modified, when the callback is needed,
01670             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01671    */
01672 }
01673
01674 /**
01675   * @brief  Slave Rx Transfer completed callback.
01676   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01677   *                the configuration information for the specified SMBUS.
01678   * @retval None
01679   */
01680 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01681 {
01682   /* Prevent unused argument(s) compilation warning */
01683   UNUSED(hsmbus);
01684
01685   /* NOTE : This function should not be modified, when the callback is needed,
01686             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01687    */
01688 }
01689
01690 /**
01691   * @brief  Slave Address Match callback.
01692   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01693   *                the configuration information for the specified SMBUS.
01694   * @param  TransferDirection Master request Transfer Direction (Write/Read)
01695   * @param  AddrMatchCode Address Match Code
01696   * @retval None
01697   */
01698 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
01699 {
01700   /* Prevent unused argument(s) compilation warning */
01701   UNUSED(hsmbus);
01702   UNUSED(TransferDirection);
01703   UNUSED(AddrMatchCode);
01704
01705   /* NOTE : This function should not be modified, when the callback is needed,
01706             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01707    */
01708 }
01709
01710 /**
01711   * @brief  Listen Complete callback.
01712   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01713   *                the configuration information for the specified SMBUS.
01714   * @retval None
01715   */
01716 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01717 {
01718   /* Prevent unused argument(s) compilation warning */
01719   UNUSED(hsmbus);
01720
01721   /* NOTE : This function should not be modified, when the callback is needed,
01722             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01723    */
01724 }
01725
01726 /**
01727   * @brief  SMBUS error callback.
01728   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01729   *                the configuration information for the specified SMBUS.
01730   * @retval None
01731   */
01732 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01733 {
01734   /* Prevent unused argument(s) compilation warning */
01735   UNUSED(hsmbus);
01736
01737   /* NOTE : This function should not be modified, when the callback is needed,
01738             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01739    */
01740 }
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01747  *  @brief   Peripheral State and Errors functions
01748  *
01749 @verbatim
01750  ===============================================================================
01751             ##### Peripheral State and Errors functions #####
01752  ===============================================================================
01753     [..]
01754     This subsection permits to get in run-time the status of the peripheral
01755     and the data flow.
01756
01757 @endverbatim
01758   * @{
01759   */
01760
01761 /**
01762   * @brief  Return the SMBUS handle state.
01763   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01764   *                the configuration information for the specified SMBUS.
01765   * @retval HAL state
01766   */
01767 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01768 {
01769   /* Return SMBUS handle state */
01770   return hsmbus->State;
01771 }
01772
01773 /**
01774 * @brief  Return the SMBUS error code.
01775   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01776   *              the configuration information for the specified SMBUS.
01777 * @retval SMBUS Error Code
01778 */
01779 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01780 {
01781   return hsmbus->ErrorCode;
01782 }
01783
01784 /**
01785   * @}
01786   */
01787
01788 /**
01789   * @}
01790   */
01791
01792 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01793  *  @brief   Data transfers Private functions
01794   * @{
01795   */
01796
01797 /**
01798   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01799   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01800   *                the configuration information for the specified SMBUS.
01801   * @param  StatusFlags Value of Interrupt Flags.
01802   * @retval HAL status
01803   */
01804 static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
01805 {
01806   uint16_t DevAddress;
01807
01808   /* Process Locked */
01809   __HAL_LOCK(hsmbus);
01810
01811   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
01812   {
01813     /* Clear NACK Flag */
01814     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01815
01816     /* Set corresponding Error Code */
01817     /* No need to generate STOP, it is automatically done */
01818     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01819
01820     /* Process Unlocked */
01821     __HAL_UNLOCK(hsmbus);
01822
01823     /* Call the Error callback to inform upper layer */
01824 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01825     hsmbus->ErrorCallback(hsmbus);
01826 #else
01827     HAL_SMBUS_ErrorCallback(hsmbus);
01828 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01829   }
01830   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
01831   {
01832     /* Check and treat errors if errors occurs during STOP process */
01833     SMBUS_ITErrorHandler(hsmbus);
01834
01835     /* Call the corresponding callback to inform upper layer of End of Transfer */
01836     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01837     {
01838       /* Disable Interrupt */
01839       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01840
01841       /* Clear STOP Flag */
01842       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01843
01844       /* Clear Configuration Register 2 */
01845       SMBUS_RESET_CR2(hsmbus);
01846
01847       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01848       /* Disable the selected SMBUS peripheral */
01849       __HAL_SMBUS_DISABLE(hsmbus);
01850
01851       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01852       hsmbus->State = HAL_SMBUS_STATE_READY;
01853
01854       /* Process Unlocked */
01855       __HAL_UNLOCK(hsmbus);
01856
01857       /* REenable the selected SMBUS peripheral */
01858       __HAL_SMBUS_ENABLE(hsmbus);
01859
01860       /* Call the corresponding callback to inform upper layer of End of Transfer */
01861 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01862       hsmbus->MasterTxCpltCallback(hsmbus);
01863 #else
01864       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01865 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01866     }
01867     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01868     {
01869       /* Store Last receive data if any */
01870       if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01871       {
01872         /* Read data from RXDR */
01873         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01874
01875         /* Increment Buffer pointer */
01876         hsmbus->pBuffPtr++;
01877
01878         if ((hsmbus->XferSize > 0U))
01879         {
01880           hsmbus->XferSize--;
01881           hsmbus->XferCount--;
01882         }
01883       }
01884
01885       /* Disable Interrupt */
01886       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01887
01888       /* Clear STOP Flag */
01889       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01890
01891       /* Clear Configuration Register 2 */
01892       SMBUS_RESET_CR2(hsmbus);
01893
01894       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01895       hsmbus->State = HAL_SMBUS_STATE_READY;
01896
01897       /* Process Unlocked */
01898       __HAL_UNLOCK(hsmbus);
01899
01900       /* Call the corresponding callback to inform upper layer of End of Transfer */
01901 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01902       hsmbus->MasterRxCpltCallback(hsmbus);
01903 #else
01904       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01905 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01906     }
01907     else
01908     {
01909       /* Nothing to do */
01910     }
01911   }
01912   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01913   {
01914     /* Read data from RXDR */
01915     *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01916
01917     /* Increment Buffer pointer */
01918     hsmbus->pBuffPtr++;
01919
01920     /* Increment Size counter */
01921     hsmbus->XferSize--;
01922     hsmbus->XferCount--;
01923   }
01924   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
01925   {
01926     /* Write data to TXDR */
01927     hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
01928
01929     /* Increment Buffer pointer */
01930     hsmbus->pBuffPtr++;
01931
01932     /* Increment Size counter */
01933     hsmbus->XferSize--;
01934     hsmbus->XferCount--;
01935   }
01936   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
01937   {
01938     if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
01939     {
01940       DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
01941
01942       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
01943       {
01944         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01945         hsmbus->XferSize = MAX_NBYTE_SIZE;
01946       }
01947       else
01948       {
01949         hsmbus->XferSize = hsmbus->XferCount;
01950         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01951         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01952         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01953         if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01954         {
01955           hsmbus->XferSize--;
01956           hsmbus->XferCount--;
01957         }
01958       }
01959     }
01960     else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
01961     {
01962       /* Call TxCpltCallback() if no stop mode is set */
01963       if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01964       {
01965         /* Call the corresponding callback to inform upper layer of End of Transfer */
01966         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01967         {
01968           /* Disable Interrupt */
01969           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01970           hsmbus->PreviousState = hsmbus->State;
01971           hsmbus->State = HAL_SMBUS_STATE_READY;
01972
01973           /* Process Unlocked */
01974           __HAL_UNLOCK(hsmbus);
01975
01976           /* Call the corresponding callback to inform upper layer of End of Transfer */
01977 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01978           hsmbus->MasterTxCpltCallback(hsmbus);
01979 #else
01980           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01981 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01982         }
01983         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01984         {
01985           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01986           hsmbus->PreviousState = hsmbus->State;
01987           hsmbus->State = HAL_SMBUS_STATE_READY;
01988
01989           /* Process Unlocked */
01990           __HAL_UNLOCK(hsmbus);
01991
01992           /* Call the corresponding callback to inform upper layer of End of Transfer */
01993 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01994           hsmbus->MasterRxCpltCallback(hsmbus);
01995 #else
01996           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01997 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01998         }
01999         else
02000         {
02001           /* Nothing to do */
02002         }
02003       }
02004     }
02005     else
02006     {
02007       /* Nothing to do */
02008     }
02009   }
02010   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
02011   {
02012     if (hsmbus->XferCount == 0U)
02013     {
02014       /* Specific use case for Quick command */
02015       if (hsmbus->pBuffPtr == NULL)
02016       {
02017         /* Generate a Stop command */
02018         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
02019       }
02020       /* Call TxCpltCallback() if no stop mode is set */
02021       else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02022       {
02023         /* No Generate Stop, to permit restart mode */
02024         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
02025
02026         /* Call the corresponding callback to inform upper layer of End of Transfer */
02027         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02028         {
02029           /* Disable Interrupt */
02030           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02031           hsmbus->PreviousState = hsmbus->State;
02032           hsmbus->State = HAL_SMBUS_STATE_READY;
02033
02034           /* Process Unlocked */
02035           __HAL_UNLOCK(hsmbus);
02036
02037           /* Call the corresponding callback to inform upper layer of End of Transfer */
02038 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02039           hsmbus->MasterTxCpltCallback(hsmbus);
02040 #else
02041           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02042 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02043         }
02044         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02045         {
02046           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02047           hsmbus->PreviousState = hsmbus->State;
02048           hsmbus->State = HAL_SMBUS_STATE_READY;
02049
02050           /* Process Unlocked */
02051           __HAL_UNLOCK(hsmbus);
02052
02053           /* Call the corresponding callback to inform upper layer of End of Transfer */
02054 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02055           hsmbus->MasterRxCpltCallback(hsmbus);
02056 #else
02057           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02058 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02059         }
02060         else
02061         {
02062           /* Nothing to do */
02063         }
02064       }
02065       else
02066       {
02067         /* Nothing to do */
02068       }
02069     }
02070   }
02071   else
02072   {
02073     /* Nothing to do */
02074   }
02075
02076   /* Process Unlocked */
02077   __HAL_UNLOCK(hsmbus);
02078
02079   return HAL_OK;
02080 }
02081 /**
02082   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
02083   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02084   *                the configuration information for the specified SMBUS.
02085   * @param  StatusFlags Value of Interrupt Flags.
02086   * @retval HAL status
02087   */
02088 static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
02089 {
02090   uint8_t TransferDirection;
02091   uint16_t SlaveAddrCode;
02092
02093   /* Process Locked */
02094   __HAL_LOCK(hsmbus);
02095
02096   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
02097   {
02098     /* Check that SMBUS transfer finished */
02099     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
02100     /* Mean XferCount == 0*/
02101     /* So clear Flag NACKF only */
02102     if (hsmbus->XferCount == 0U)
02103     {
02104       /* Clear NACK Flag */
02105       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02106
02107       /* Process Unlocked */
02108       __HAL_UNLOCK(hsmbus);
02109     }
02110     else
02111     {
02112       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
02113       /* Clear NACK Flag */
02114       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02115
02116       /* Set HAL State to "Idle" State, mean to LISTEN state */
02117       /* So reset Slave Busy state */
02118       hsmbus->PreviousState = hsmbus->State;
02119       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02120       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02121
02122       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
02123       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02124
02125       /* Set ErrorCode corresponding to a Non-Acknowledge */
02126       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
02127
02128       /* Process Unlocked */
02129       __HAL_UNLOCK(hsmbus);
02130
02131       /* Call the Error callback to inform upper layer */
02132 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02133       hsmbus->ErrorCallback(hsmbus);
02134 #else
02135       HAL_SMBUS_ErrorCallback(hsmbus);
02136 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02137     }
02138   }
02139   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
02140   {
02141     TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
02142     SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
02143
02144     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
02145     /* Other ADDRInterrupt will be treat in next Listen usecase */
02146     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
02147
02148     /* Process Unlocked */
02149     __HAL_UNLOCK(hsmbus);
02150
02151     /* Call Slave Addr callback */
02152 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02153     hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02154 #else
02155     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02156 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02157   }
02158   else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
02159   {
02160     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
02161     {
02162       /* Read data from RXDR */
02163       *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02164
02165       /* Increment Buffer pointer */
02166       hsmbus->pBuffPtr++;
02167
02168       hsmbus->XferSize--;
02169       hsmbus->XferCount--;
02170
02171       if (hsmbus->XferCount == 1U)
02172       {
02173         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
02174         /* or only the last Byte of Transfer */
02175         /* So reset the RELOAD bit mode */
02176         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
02177         SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02178       }
02179       else if (hsmbus->XferCount == 0U)
02180       {
02181         /* Last Byte is received, disable Interrupt */
02182         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02183
02184         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
02185         hsmbus->PreviousState = hsmbus->State;
02186         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02187
02188         /* Process Unlocked */
02189         __HAL_UNLOCK(hsmbus);
02190
02191         /* Call the corresponding callback to inform upper layer of End of Transfer */
02192 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02193         hsmbus->SlaveRxCpltCallback(hsmbus);
02194 #else
02195         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
02196 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02197       }
02198       else
02199       {
02200         /* Set Reload for next Bytes */
02201         SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
02202
02203         /* Ack last Byte Read */
02204         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
02205       }
02206     }
02207     else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02208     {
02209       if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
02210       {
02211         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
02212         {
02213           SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
02214           hsmbus->XferSize = MAX_NBYTE_SIZE;
02215         }
02216         else
02217         {
02218           hsmbus->XferSize = hsmbus->XferCount;
02219           SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02220           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02221           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02222           if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02223           {
02224             hsmbus->XferSize--;
02225             hsmbus->XferCount--;
02226           }
02227         }
02228       }
02229     }
02230     else
02231     {
02232       /* Nothing to do */
02233     }
02234   }
02235   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
02236   {
02237     /* Write data to TXDR only if XferCount not reach "0" */
02238     /* A TXIS flag can be set, during STOP treatment      */
02239     /* Check if all Data have already been sent */
02240     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
02241     if (hsmbus->XferCount > 0U)
02242     {
02243       /* Write data to TXDR */
02244       hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
02245
02246       /* Increment Buffer pointer */
02247       hsmbus->pBuffPtr++;
02248
02249       hsmbus->XferCount--;
02250       hsmbus->XferSize--;
02251     }
02252
02253     if (hsmbus->XferCount == 0U)
02254     {
02255       /* Last Byte is Transmitted */
02256       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
02257       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02258       hsmbus->PreviousState = hsmbus->State;
02259       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02260
02261       /* Process Unlocked */
02262       __HAL_UNLOCK(hsmbus);
02263
02264       /* Call the corresponding callback to inform upper layer of End of Transfer */
02265 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02266       hsmbus->SlaveTxCpltCallback(hsmbus);
02267 #else
02268       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
02269 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02270     }
02271   }
02272   else
02273   {
02274     /* Nothing to do */
02275   }
02276
02277   /* Check if STOPF is set */
02278   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
02279   {
02280     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
02281     {
02282       /* Store Last receive data if any */
02283       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
02284       {
02285         /* Read data from RXDR */
02286         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02287
02288         /* Increment Buffer pointer */
02289         hsmbus->pBuffPtr++;
02290
02291         if ((hsmbus->XferSize > 0U))
02292         {
02293           hsmbus->XferSize--;
02294           hsmbus->XferCount--;
02295         }
02296       }
02297
02298       /* Disable RX and TX Interrupts */
02299       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02300
02301       /* Disable ADDR Interrupt */
02302       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
02303
02304       /* Disable Address Acknowledge */
02305       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
02306
02307       /* Clear Configuration Register 2 */
02308       SMBUS_RESET_CR2(hsmbus);
02309
02310       /* Clear STOP Flag */
02311       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
02312
02313       /* Clear ADDR flag */
02314       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
02315
02316       hsmbus->XferOptions = 0;
02317       hsmbus->PreviousState = hsmbus->State;
02318       hsmbus->State = HAL_SMBUS_STATE_READY;
02319
02320       /* Process Unlocked */
02321       __HAL_UNLOCK(hsmbus);
02322
02323       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
02324 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02325       hsmbus->ListenCpltCallback(hsmbus);
02326 #else
02327       HAL_SMBUS_ListenCpltCallback(hsmbus);
02328 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02329     }
02330   }
02331
02332   /* Process Unlocked */
02333   __HAL_UNLOCK(hsmbus);
02334
02335   return HAL_OK;
02336 }
02337 /**
02338   * @brief  Manage the enabling of Interrupts.
02339   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02340   *                the configuration information for the specified SMBUS.
02341   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02342   * @retval HAL status
02343   */
02344 static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02345 {
02346   uint32_t tmpisr = 0UL;
02347
02348   if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
02349   {
02350     /* Enable ERR interrupt */
02351     tmpisr |= SMBUS_IT_ERRI;
02352   }
02353
02354   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02355   {
02356     /* Enable ADDR, STOP interrupt */
02357     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
02358   }
02359
02360   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02361   {
02362     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02363     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
02364   }
02365
02366   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02367   {
02368     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02369     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
02370   }
02371
02372   /* Enable interrupts only at the end */
02373   /* to avoid the risk of SMBUS interrupt handle execution before */
02374   /* all interrupts requested done */
02375   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
02376 }
02377 /**
02378   * @brief  Manage the disabling of Interrupts.
02379   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02380   *                the configuration information for the specified SMBUS.
02381   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02382   * @retval HAL status
02383   */
02384 static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02385 {
02386   uint32_t tmpisr = 0UL;
02387   uint32_t tmpstate = hsmbus->State;
02388
02389   if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
02390   {
02391     /* Disable ERR interrupt */
02392     tmpisr |= SMBUS_IT_ERRI;
02393   }
02394
02395   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02396   {
02397     /* Disable TC, STOP, NACK and TXI interrupt */
02398     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
02399
02400     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02401         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02402     {
02403       /* Disable ERR interrupt */
02404       tmpisr |= SMBUS_IT_ERRI;
02405     }
02406
02407     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02408     {
02409       /* Disable STOP and NACK interrupt */
02410       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02411     }
02412   }
02413
02414   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02415   {
02416     /* Disable TC, STOP, NACK and RXI interrupt */
02417     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
02418
02419     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02420         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02421     {
02422       /* Disable ERR interrupt */
02423       tmpisr |= SMBUS_IT_ERRI;
02424     }
02425
02426     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02427     {
02428       /* Disable STOP and NACK interrupt */
02429       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02430     }
02431   }
02432
02433   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02434   {
02435     /* Disable ADDR, STOP and NACK interrupt */
02436     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02437
02438     if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02439     {
02440       /* Disable ERR interrupt */
02441       tmpisr |= SMBUS_IT_ERRI;
02442     }
02443   }
02444
02445   /* Disable interrupts only at the end */
02446   /* to avoid a breaking situation like at "t" time */
02447   /* all disable interrupts request are not done */
02448   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
02449 }
02450
02451 /**
02452   * @brief  SMBUS interrupts error handler.
02453   * @param  hsmbus SMBUS handle.
02454   * @retval None
02455   */
02456 static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
02457 {
02458   uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
02459   uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
02460   uint32_t tmpstate;
02461   uint32_t tmperror;
02462
02463   /* SMBUS Bus error interrupt occurred ------------------------------------*/
02464   if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02465   {
02466     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
02467
02468     /* Clear BERR flag */
02469     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
02470   }
02471
02472   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02473   if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02474   {
02475     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
02476
02477     /* Clear OVR flag */
02478     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
02479   }
02480
02481   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
02482   if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02483   {
02484     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
02485
02486     /* Clear ARLO flag */
02487     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
02488   }
02489
02490   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
02491   if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02492   {
02493     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
02494
02495     /* Clear TIMEOUT flag */
02496     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
02497   }
02498
02499   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
02500   if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02501   {
02502     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
02503
02504     /* Clear ALERT flag */
02505     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
02506   }
02507
02508   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
02509   if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02510   {
02511     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
02512
02513     /* Clear PEC error flag */
02514     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
02515   }
02516
02517   /* Store current volatile hsmbus->State, misra rule */
02518   tmperror = hsmbus->ErrorCode;
02519
02520   /* Call the Error Callback in case of Error detected */
02521   if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
02522   {
02523     /* Do not Reset the HAL state in case of ALERT error */
02524     if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
02525     {
02526       /* Store current volatile hsmbus->State, misra rule */
02527       tmpstate = hsmbus->State;
02528
02529       if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02530           || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
02531       {
02532         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
02533         /* keep HAL_SMBUS_STATE_LISTEN if set */
02534         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
02535         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
02536       }
02537     }
02538
02539     /* Call the Error callback to inform upper layer */
02540 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02541     hsmbus->ErrorCallback(hsmbus);
02542 #else
02543     HAL_SMBUS_ErrorCallback(hsmbus);
02544 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02545   }
02546 }
02547
02548 /**
02549   * @brief  Handle SMBUS Communication Timeout.
02550   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02551   *                the configuration information for the specified SMBUS.
02552   * @param  Flag Specifies the SMBUS flag to check.
02553   * @param  Status The new Flag status (SET or RESET).
02554   * @param  Timeout Timeout duration
02555   * @retval HAL status
02556   */
02557 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
02558 {
02559   uint32_t tickstart = HAL_GetTick();
02560
02561   /* Wait until flag is set */
02562   while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
02563   {
02564     /* Check for the Timeout */
02565     if (Timeout != HAL_MAX_DELAY)
02566     {
02567       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
02568       {
02569         hsmbus->PreviousState = hsmbus->State;
02570         hsmbus->State = HAL_SMBUS_STATE_READY;
02571
02572         /* Update SMBUS error code */
02573         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
02574
02575         /* Process Unlocked */
02576         __HAL_UNLOCK(hsmbus);
02577
02578         return HAL_ERROR;
02579       }
02580     }
02581   }
02582
02583   return HAL_OK;
02584 }
02585
02586 /**
02587   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
02588   * @param  hsmbus SMBUS handle.
02589   * @param  DevAddress specifies the slave address to be programmed.
02590   * @param  Size specifies the number of bytes to be programmed.
02591   *   This parameter must be a value between 0 and 255.
02592   * @param  Mode New state of the SMBUS START condition generation.
02593   *   This parameter can be one or a combination  of the following values:
02594   *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
02595   *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
02596   *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
02597   *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
02598   * @param  Request New state of the SMBUS START condition generation.
02599   *   This parameter can be one of the following values:
02600   *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
02601   *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
02602   *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
02603   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
02604   * @retval None
02605   */
02606 static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
02607 {
02608   /* Check the parameters */
02609   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
02610   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
02611   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
02612
02613   /* update CR2 register */
02614   MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP  | I2C_CR2_PECBYTE)), \
02615              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
02616 }
02617
02618 /**
02619   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
02620   * @param  hsmbus SMBUS handle.
02621   * @retval None
02622   */
02623 static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
02624 {
02625   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02626   /* it request implicitly to generate a restart condition */
02627   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02628   if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02629   {
02630     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02631   }
02632   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02633   /* it request implicitly to generate a restart condition      */
02634   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02635   else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02636   {
02637     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02638   }
02639   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02640   /* it request implicitly to generate a restart condition             */
02641   /* then generate a stop condition at the end of transfer             */
02642   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02643   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02644   {
02645     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02646   }
02647   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02648   /* it request implicitly to generate a restart condition               */
02649   /* then generate a stop condition at the end of transfer               */
02650   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02651   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02652   {
02653     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02654   }
02655   else
02656   {
02657     /* Nothing to do */
02658   }
02659 }
02660 /**
02661   * @}
02662   */
02663
02664 #endif /* HAL_SMBUS_MODULE_ENABLED */
02665 /**
02666   * @}
02667   */
02668
02669 /**
02670   * @}
02671   */
02672
02673 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_smbus.h Source File

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stm32h7xx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SMBUS_H
00022 #define STM32H7xx_HAL_SMBUS_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMBUS
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00045   * @brief  SMBUS Configuration Structure definition
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00051                                      This parameter calculated by referring to SMBUS initialization
00052                                             section in Reference manual */
00053   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00054                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
00055
00056   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00057                                      This parameter can be a 7-bit or 10-bit address. */
00058
00059   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00060                                      This parameter can be a value of @ref SMBUS_addressing_mode */
00061
00062   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00063                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00064
00065   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00066                                      This parameter can be a 7-bit address. */
00067
00068   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00069                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
00070
00071   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00072                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00073
00074   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00075                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
00076
00077   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00078                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00079
00080   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00081                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
00082
00083   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00084                                       (Enable bits and different timeout values)
00085                                      This parameter calculated by referring to SMBUS initialization
00086                                          section in Reference manual */
00087 } SMBUS_InitTypeDef;
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HAL_state_definition HAL state definition
00093   * @brief  HAL State definition
00094   * @{
00095   */
00096 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00097 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00098 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00099 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00103 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
00104 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
00105 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00111   * @brief  SMBUS Error Code definition
00112   * @{
00113   */
00114 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00115 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00116 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00117 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00118 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00119 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00120 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00121 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00122 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00126 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00132   * @brief  SMBUS handle Structure definition
00133   * @{
00134   */
00135 typedef struct __SMBUS_HandleTypeDef
00136 {
00137   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00138
00139   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00140
00141   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00142
00143   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00144
00145   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00146
00147   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00148
00149   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00150
00151   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00152
00153   __IO uint32_t                State;           /*!< SMBUS communication state          */
00154
00155   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00156
00157 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00158   void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Tx Transfer completed callback */
00159   void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Rx Transfer completed callback */
00160   void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Tx Transfer completed callback  */
00161   void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Rx Transfer completed callback  */
00162   void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);             /*!< SMBUS Listen Complete callback              */
00163   void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                  /*!< SMBUS Error callback                        */
00164
00165   void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< SMBUS Slave Address Match callback */
00166
00167   void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                /*!< SMBUS Msp Init callback                     */
00168   void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);              /*!< SMBUS Msp DeInit callback                   */
00169
00170 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00171 } SMBUS_HandleTypeDef;
00172
00173 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00174 /**
00175   * @brief  HAL SMBUS Callback ID enumeration definition
00176   */
00177 typedef enum
00178 {
00179   HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
00180   HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
00181   HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
00182   HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
00183   HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
00184   HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
00185
00186   HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
00187   HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
00188
00189 } HAL_SMBUS_CallbackIDTypeDef;
00190
00191 /**
00192   * @brief  HAL SMBUS Callback pointer definition
00193   */
00194 typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
00195 typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
00196
00197 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205 /* Exported constants --------------------------------------------------------*/
00206
00207 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00208   * @{
00209   */
00210
00211 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00212   * @{
00213   */
00214 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00215 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00221   * @{
00222   */
00223 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00224 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00230   * @{
00231   */
00232
00233 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00234 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
00240   * @{
00241   */
00242
00243 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00244 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00245 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00246 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00247 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00248 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00249 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00250 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00251 /**
00252   * @}
00253   */
00254
00255
00256 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00257   * @{
00258   */
00259 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00260 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00266   * @{
00267   */
00268 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00269 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00275   * @{
00276   */
00277 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00278 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00284   * @{
00285   */
00286 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00287 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00288 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00294   * @{
00295   */
00296
00297 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00298 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00299 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00300 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00306   * @{
00307   */
00308
00309 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00310 #define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
00311 #define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00312 #define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00318   * @{
00319   */
00320
00321 /* List of XferOptions in usage of :
00322  * 1- Restart condition when direction change
00323  * 2- No Restart condition in other use cases
00324  */
00325 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00326 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00327 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00328 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00329 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00330 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00331
00332 /* List of XferOptions in usage of :
00333  * 1- Restart condition in all use cases (direction change or not)
00334  */
00335 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00336 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00337 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00338 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00344   * @brief SMBUS Interrupt definition
00345   *        Elements values convention: 0xXXXXXXXX
00346   *           - XXXXXXXX  : Interrupt control mask
00347   * @{
00348   */
00349 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00350 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00351 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00352 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00353 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00354 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00355 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00356 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
00357 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
00358 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00359 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00365   * @brief Flag definition
00366   *        Elements values convention: 0xXXXXYYYY
00367   *           - XXXXXXXX  : Flag mask
00368   * @{
00369   */
00370
00371 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00372 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00373 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00374 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00375 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00376 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00377 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00378 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00379 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00380 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00381 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00382 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00383 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00384 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00385 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00386 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00387 /**
00388   * @}
00389   */
00390
00391 /**
00392   * @}
00393   */
00394
00395 /* Exported macros ------------------------------------------------------------*/
00396 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00397   * @{
00398   */
00399
00400 /** @brief  Reset SMBUS handle state.
00401   * @param  __HANDLE__ specifies the SMBUS Handle.
00402   * @retval None
00403   */
00404 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00405 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                                   \
00406                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \
00407                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
00408                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
00409                                                              } while(0)
00410 #else
00411 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00412 #endif
00413
00414 /** @brief  Enable the specified SMBUS interrupts.
00415   * @param  __HANDLE__ specifies the SMBUS Handle.
00416   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00417   *        This parameter can be one of the following values:
00418   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00419   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00420   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00421   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00422   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00423   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00424   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00425   *
00426   * @retval None
00427   */
00428 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00429
00430 /** @brief  Disable the specified SMBUS interrupts.
00431   * @param  __HANDLE__ specifies the SMBUS Handle.
00432   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00433   *        This parameter can be one of the following values:
00434   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00435   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00436   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00437   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00438   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00439   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00440   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00441   *
00442   * @retval None
00443   */
00444 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00445
00446 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00447   * @param  __HANDLE__ specifies the SMBUS Handle.
00448   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
00449   *          This parameter can be one of the following values:
00450   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00451   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00452   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00453   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00454   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00455   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00456   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00457   *
00458   * @retval The new state of __IT__ (SET or RESET).
00459   */
00460 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00461
00462 /** @brief  Check whether the specified SMBUS flag is set or not.
00463   * @param  __HANDLE__ specifies the SMBUS Handle.
00464   * @param  __FLAG__ specifies the flag to check.
00465   *        This parameter can be one of the following values:
00466   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00467   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
00468   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
00469   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00470   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00471   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00472   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
00473   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
00474   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00475   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00476   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00477   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00478   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00479   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00480   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
00481   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
00482   *
00483   * @retval The new state of __FLAG__ (SET or RESET).
00484   */
00485 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00486 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00487
00488 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00489   * @param  __HANDLE__ specifies the SMBUS Handle.
00490   * @param  __FLAG__ specifies the flag to clear.
00491   *          This parameter can be any combination of the following values:
00492   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00493   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00494   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00495   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00496   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00497   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00498   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00499   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00500   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00501   *
00502   * @retval None
00503   */
00504 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00505
00506 /** @brief  Enable the specified SMBUS peripheral.
00507   * @param  __HANDLE__ specifies the SMBUS Handle.
00508   * @retval None
00509   */
00510 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00511
00512 /** @brief  Disable the specified SMBUS peripheral.
00513   * @param  __HANDLE__ specifies the SMBUS Handle.
00514   * @retval None
00515   */
00516 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00517
00518 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00519   * @param  __HANDLE__ specifies the SMBUS Handle.
00520   * @retval None
00521   */
00522 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00523
00524 /**
00525   * @}
00526   */
00527
00528
00529 /* Private constants ---------------------------------------------------------*/
00530
00531 /* Private macros ------------------------------------------------------------*/
00532 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00533   * @{
00534   */
00535
00536 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00537                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00538
00539 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
00540
00541 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00542                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00543
00544 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00545                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00546
00547 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00548                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00549                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00550                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00551                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00552                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00553                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00554                                                          ((MASK) == SMBUS_OA2_MASK07))
00555
00556 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00557                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00558
00559 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00560                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00561
00562 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00563                                                           ((PEC) == SMBUS_PEC_ENABLE))
00564
00565 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
00566                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00567                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00568
00569 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
00570                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00571                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00572                                                           ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00573                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00574                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00575                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00576                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
00577
00578
00579 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00580                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
00581                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
00582                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
00583
00584
00585 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
00586                                                           ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
00587                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00588                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00589                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00590                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00591                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
00592
00593 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
00594                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
00595                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
00596                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00597
00598 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
00599 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00600
00601 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00602                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00603
00604 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
00605 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00606 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00607 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00608 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00609
00610 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00611 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00612
00613 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00614 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00615
00616 /**
00617   * @}
00618   */
00619
00620 /* Exported functions --------------------------------------------------------*/
00621 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00622   * @{
00623   */
00624
00625 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00626  * @{
00627  */
00628
00629 /* Initialization and de-initialization functions  ****************************/
00630 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00631 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
00632 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00633 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00634 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
00635 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
00636
00637 /* Callbacks Register/UnRegister functions  ***********************************/
00638 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00639 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
00640 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
00641
00642 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
00643 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
00644 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00645 /**
00646   * @}
00647   */
00648
00649 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00650  * @{
00651  */
00652
00653 /* IO operation functions  *****************************************************/
00654 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00655  * @{
00656  */
00657 /******* Blocking mode: Polling */
00658 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00664  * @{
00665  */
00666 /******* Non-Blocking mode: Interrupt */
00667 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00668 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00669 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00670 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00671 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00672
00673 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00674 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00675 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00676 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00677 /**
00678   * @}
00679   */
00680
00681 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00682  * @{
00683  */
00684 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00685 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00686 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00687 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00688 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00689 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00690 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00691 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00692 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00693 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00694
00695 /**
00696   * @}
00697   */
00698
00699 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00700  *  @{
00701  */
00702
00703 /* Peripheral State and Errors functions  **************************************************/
00704 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00705 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00706
00707 /**
00708   * @}
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /* Private Functions ---------------------------------------------------------*/
00716 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00717   * @{
00718   */
00719 /* Private functions are defined in stm32h7xx_hal_smbus.c file */
00720 /**
00721   * @}
00722   */
00723
00724 /**
00725   * @}
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 #ifdef __cplusplus
00737 }
00738 #endif
00739
00740
00741 #endif /* STM32H7xx_HAL_SMBUS_H */
00742
00743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spdifrx.c Source File

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stm32h7xx_hal_spdifrx.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spdifrx.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the SPDIFRX audio interface:
00007   *           + Initialization and Configuration
00008   *           + Data transfers functions
00009   *           + DMA transfers management
00010   *           + Interrupts and flags management
00011   @verbatim
00012  ===============================================================================
00013                   ##### How to use this driver #####
00014  ===============================================================================
00015  [..]
00016     The SPDIFRX HAL driver can be used as follow:
00017
00018     (#) Declare SPDIFRX_HandleTypeDef handle structure.
00019     (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
00020         (##) Enable the SPDIFRX interface clock.
00021         (##) SPDIFRX pins configuration:
00022             (+++) Enable the clock for the SPDIFRX GPIOs.
00023             (+++) Configure these SPDIFRX pins as alternate function pull-up.
00024         (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
00025             (+++) Configure the SPDIFRX interrupt priority.
00026             (+++) Enable the NVIC SPDIFRX IRQ handle.
00027         (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
00028             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
00029             (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
00030             (+++) Enable the DMAx interface clock.
00031             (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
00032             (+++) Configure the DMA Channel.
00033             (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
00034             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00035                 DMA CtrlRx/DataRx channel.
00036
00037    (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
00038        using HAL_SPDIFRX_Init() function.
00039
00040    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
00041        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
00042    -@- Make sure that ck_spdif clock is configured.
00043
00044    (#) Three operation modes are available within this driver :
00045
00046    *** Polling mode for reception operation (for debug purpose) ***
00047    ================================================================
00048    [..]
00049      (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
00050      (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow()
00051
00052    *** Interrupt mode for reception operation ***
00053    =========================================
00054    [..]
00055      (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
00056      (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow_IT()
00057      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00058          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00059      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00061      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00062          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00063
00064    *** DMA mode for reception operation ***
00065    ========================================
00066    [..]
00067      (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
00068      (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
00069      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00070          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00071      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00072          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00073      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00074          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00075      (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
00076
00077    *** SPDIFRX HAL driver macros list ***
00078    =============================================
00079    [..]
00080      Below the list of most used macros in SPDIFRX HAL driver.
00081       (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
00082       (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
00083       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
00084       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
00085       (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
00086       (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
00087
00088    [..]
00089       (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
00090
00091   *** Callback registration ***
00092   =============================================
00093
00094   The compilation define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
00095   allows the user to configure dynamically the driver callbacks.
00096   Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.
00097
00098   The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
00099     (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
00100     (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
00101     (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
00102     (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
00103     (+) ErrorCallback       : SPDIFRX error callback.
00104     (+) MspInitCallback     : SPDIFRX MspInit.
00105     (+) MspDeInitCallback   : SPDIFRX MspDeInit.
00106   This function takes as parameters the HAL peripheral handle, the Callback ID
00107   and a pointer to the user callback function.
00108
00109   Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default
00110   weak function.
00111   The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle,
00112   and the Callback ID.
00113   This function allows to reset the following callbacks:
00114     (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
00115     (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
00116     (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
00117     (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
00118     (+) ErrorCallback       : SPDIFRX error callback.
00119     (+) MspInitCallback     : SPDIFRX MspInit.
00120     (+) MspDeInitCallback   : SPDIFRX MspDeInit.
00121
00122   By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET
00123   all callbacks are set to the corresponding weak functions :
00124   HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(),
00125   HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback()
00126   Exception done for MspInit and MspDeInit functions that are
00127   reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when
00128   these callbacks pointers are NULL (not registered beforehand).
00129   If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit()
00130   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00131
00132   Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only.
00133   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00134   in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state,
00135   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00136   In that case first register the MspInit/MspDeInit user callbacks
00137   using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit()
00138   or HAL_SPDIFRX_Init() function.
00139
00140   When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or
00141   not defined, the callback registration feature is not available and all callbacks
00142   are set to the corresponding weak functions.
00143
00144   @endverbatim
00145   ******************************************************************************
00146   * @attention
00147   *
00148   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00149   * All rights reserved.</center></h2>
00150   *
00151   * This software component is licensed by ST under BSD 3-Clause license,
00152   * the "License"; You may not use this file except in compliance with the
00153   * License. You may obtain a copy of the License at:
00154   *                        opensource.org/licenses/BSD-3-Clause
00155   *
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32h7xx_hal.h"
00161
00162 /** @addtogroup STM32H7xx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup SPDIFRX SPDIFRX
00167   * @brief SPDIFRX HAL module driver
00168   * @{
00169   */
00170
00171 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00172 #if defined (SPDIFRX)
00173
00174 /* Private typedef -----------------------------------------------------------*/
00175 /* Private define ------------------------------------------------------------*/
00176 #define SPDIFRX_TIMEOUT_VALUE  0xFFFFU
00177
00178 /* Private macro -------------------------------------------------------------*/
00179 /* Private variables ---------------------------------------------------------*/
00180 /* Private function prototypes -----------------------------------------------*/
00181 /** @addtogroup SPDIFRX_Private_Functions
00182   * @{
00183   */
00184 static void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
00185 static void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00186 static void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
00187 static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
00188 static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
00189 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00190 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00191 static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
00192 /**
00193   * @}
00194   */
00195 /* Exported functions ---------------------------------------------------------*/
00196
00197 /** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
00198   * @{
00199   */
00200
00201 /** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
00202   *  @brief    Initialization and Configuration functions
00203   *
00204   @verbatim
00205   ===============================================================================
00206   ##### Initialization and de-initialization functions #####
00207   ===============================================================================
00208   [..]  This subsection provides a set of functions allowing to initialize and
00209         de-initialize the SPDIFRX peripheral:
00210
00211   (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
00212       all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00213
00214   (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
00215       the selected configuration:
00216   (++) Input Selection (IN0, IN1,...)
00217   (++) Maximum allowed re-tries during synchronization phase
00218   (++) Wait for activity on SPDIF selected input
00219   (++) Channel status selection (from channel A or B)
00220   (++) Data format (LSB, MSB, ...)
00221   (++) Stereo mode
00222   (++) User bits masking (PT,C,U,V,...)
00223
00224   (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
00225       of the selected SPDIFRXx peripheral.
00226   @endverbatim
00227   * @{
00228   */
00229
00230 /**
00231   * @brief Initializes the SPDIFRX according to the specified parameters
00232   *        in the SPDIFRX_InitTypeDef and create the associated handle.
00233   * @param hspdif SPDIFRX handle
00234   * @retval HAL status
00235   */
00236 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
00237 {
00238   uint32_t tmpreg;
00239
00240   /* Check the SPDIFRX handle allocation */
00241   if(hspdif == NULL)
00242   {
00243     return HAL_ERROR;
00244   }
00245
00246   /* Check the SPDIFRX parameters */
00247   assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
00248   assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
00249   assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
00250   assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
00251   assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
00252   assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
00253   assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
00254   assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
00255   assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
00256   assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
00257   assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.SymbolClockGen));
00258   assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen));
00259
00260 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00261   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
00262   {
00263     /* Allocate lock resource and initialize it */
00264     hspdif->Lock = HAL_UNLOCKED;
00265
00266     hspdif->RxHalfCpltCallback  = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
00267     hspdif->RxCpltCallback      = HAL_SPDIFRX_RxCpltCallback;     /* Legacy weak RxCpltCallback     */
00268     hspdif->CxHalfCpltCallback  = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */
00269     hspdif->CxCpltCallback      = HAL_SPDIFRX_CxCpltCallback;     /* Legacy weak CxCpltCallback     */
00270     hspdif->ErrorCallback       = HAL_SPDIFRX_ErrorCallback;      /* Legacy weak ErrorCallback      */
00271
00272     if(hspdif->MspInitCallback == NULL)
00273     {
00274       hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit  */
00275     }
00276
00277     /* Init the low level hardware */
00278     hspdif->MspInitCallback(hspdif);
00279   }
00280 #else
00281   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
00282   {
00283     /* Allocate lock resource and initialize it */
00284     hspdif->Lock = HAL_UNLOCKED;
00285     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00286     HAL_SPDIFRX_MspInit(hspdif);
00287   }
00288 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00289
00290   /* SPDIFRX peripheral state is BUSY */
00291   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00292
00293   /* Disable SPDIFRX interface (IDLE State) */
00294   __HAL_SPDIFRX_IDLE(hspdif);
00295
00296   /* Reset the old SPDIFRX CR configuration */
00297   tmpreg = hspdif->Instance->CR;
00298
00299   tmpreg &= ~(SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00300               SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
00301               SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
00302               SPDIFRX_CR_CKSEN | SPDIFRX_CR_CKSBKPEN |
00303               SPDIFRX_CR_INSEL);
00304
00305   /* Sets the new configuration of the SPDIFRX peripheral */
00306   tmpreg |= (hspdif->Init.StereoMode |
00307              hspdif->Init.InputSelection |
00308              hspdif->Init.Retries |
00309              hspdif->Init.WaitForActivity |
00310              hspdif->Init.ChannelSelection |
00311              hspdif->Init.DataFormat |
00312              hspdif->Init.PreambleTypeMask |
00313              hspdif->Init.ChannelStatusMask |
00314              hspdif->Init.ValidityBitMask |
00315              hspdif->Init.ParityErrorMask
00316              );
00317
00318   if(hspdif->Init.SymbolClockGen == ENABLE)
00319   {
00320     tmpreg |= SPDIFRX_CR_CKSEN;
00321   }
00322
00323   if(hspdif->Init.BackupSymbolClockGen == ENABLE)
00324   {
00325     tmpreg |= SPDIFRX_CR_CKSBKPEN;
00326   }
00327
00328   hspdif->Instance->CR = tmpreg;
00329
00330   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00331
00332   /* SPDIFRX peripheral state is READY*/
00333   hspdif->State = HAL_SPDIFRX_STATE_READY;
00334
00335   return HAL_OK;
00336 }
00337
00338 /**
00339   * @brief DeInitializes the SPDIFRX peripheral
00340   * @param hspdif SPDIFRX handle
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
00344 {
00345   /* Check the SPDIFRX handle allocation */
00346   if(hspdif == NULL)
00347   {
00348     return HAL_ERROR;
00349   }
00350
00351   /* Check the parameters */
00352   assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
00353
00354   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00355
00356   /* Disable SPDIFRX interface (IDLE state) */
00357   __HAL_SPDIFRX_IDLE(hspdif);
00358
00359 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00360   if(hspdif->MspDeInitCallback == NULL)
00361   {
00362     hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit  */
00363   }
00364
00365   /* DeInit the low level hardware */
00366   hspdif->MspDeInitCallback(hspdif);
00367 #else
00368   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00369   HAL_SPDIFRX_MspDeInit(hspdif);
00370 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00371
00372   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00373
00374   /* SPDIFRX peripheral state is RESET*/
00375   hspdif->State = HAL_SPDIFRX_STATE_RESET;
00376
00377   /* Release Lock */
00378   __HAL_UNLOCK(hspdif);
00379
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief SPDIFRX MSP Init
00385   * @param hspdif SPDIFRX handle
00386   * @retval None
00387   */
00388 __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
00389 {
00390   /* Prevent unused argument(s) compilation warning */
00391   UNUSED(hspdif);
00392
00393   /* NOTE : This function Should not be modified, when the callback is needed,
00394   the HAL_SPDIFRX_MspInit could be implemented in the user file
00395   */
00396 }
00397
00398 /**
00399   * @brief SPDIFRX MSP DeInit
00400   * @param hspdif SPDIFRX handle
00401   * @retval None
00402   */
00403 __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
00404 {
00405   /* Prevent unused argument(s) compilation warning */
00406   UNUSED(hspdif);
00407
00408   /* NOTE : This function Should not be modified, when the callback is needed,
00409   the HAL_SPDIFRX_MspDeInit could be implemented in the user file
00410   */
00411 }
00412
00413 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00414 /**
00415   * @brief  Register a User SPDIFRX Callback
00416   *         To be used instead of the weak predefined callback
00417   * @param  hspdif SPDIFRX handle
00418   * @param  CallbackID ID of the callback to be registered
00419   *         This parameter can be one of the following values:
00420   *          @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID    SPDIFRX Data flow half completed callback ID
00421   *          @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID    SPDIFRX Data flow completed callback ID
00422   *          @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID    SPDIFRX Control flow half completed callback ID
00423   *          @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID    SPDIFRX Control flow completed callback ID
00424   *          @arg @ref HAL_SPDIFRX_ERROR_CB_ID      SPDIFRX error callback ID
00425   *          @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID    MspInit callback ID
00426   *          @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID  MspDeInit callback ID
00427   * @param  pCallback pointer to the Callback function
00428   * @retval HAL status
00429   */
00430 HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
00431 {
00432   HAL_StatusTypeDef status = HAL_OK;
00433
00434   if(pCallback == NULL)
00435   {
00436     /* Update the error code */
00437     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00438     return HAL_ERROR;
00439   }
00440   /* Process locked */
00441   __HAL_LOCK(hspdif);
00442
00443   if(HAL_SPDIFRX_STATE_READY == hspdif->State)
00444   {
00445     switch (CallbackID)
00446     {
00447       case HAL_SPDIFRX_RX_HALF_CB_ID :
00448         hspdif->RxHalfCpltCallback = pCallback;
00449         break;
00450
00451       case HAL_SPDIFRX_RX_CPLT_CB_ID :
00452         hspdif->RxCpltCallback = pCallback;
00453         break;
00454
00455       case HAL_SPDIFRX_CX_HALF_CB_ID :
00456         hspdif->CxHalfCpltCallback = pCallback;
00457         break;
00458
00459       case HAL_SPDIFRX_CX_CPLT_CB_ID :
00460         hspdif->CxCpltCallback = pCallback;
00461         break;
00462
00463       case HAL_SPDIFRX_ERROR_CB_ID :
00464         hspdif->ErrorCallback = pCallback;
00465         break;
00466
00467       case HAL_SPDIFRX_MSPINIT_CB_ID :
00468         hspdif->MspInitCallback = pCallback;
00469         break;
00470
00471       case HAL_SPDIFRX_MSPDEINIT_CB_ID :
00472         hspdif->MspDeInitCallback = pCallback;
00473         break;
00474
00475       default :
00476         /* Update the error code */
00477         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00478         /* Return error status */
00479         status =  HAL_ERROR;
00480         break;
00481     }
00482   }
00483   else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
00484   {
00485     switch (CallbackID)
00486     {
00487       case HAL_SPDIFRX_MSPINIT_CB_ID :
00488         hspdif->MspInitCallback = pCallback;
00489         break;
00490
00491       case HAL_SPDIFRX_MSPDEINIT_CB_ID :
00492         hspdif->MspDeInitCallback = pCallback;
00493         break;
00494
00495       default :
00496         /* Update the error code */
00497         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00498        /* Return error status */
00499         status =  HAL_ERROR;
00500         break;
00501     }
00502   }
00503   else
00504   {
00505     /* Update the error code */
00506     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00507     /* Return error status */
00508     status =  HAL_ERROR;
00509   }
00510
00511   /* Release Lock */
00512   __HAL_UNLOCK(hspdif);
00513   return status;
00514 }
00515
00516 /**
00517   * @brief  Unregister a SPDIFRX Callback
00518   *         SPDIFRX callabck is redirected to the weak predefined callback
00519   * @param  hspdif SPDIFRX handle
00520   * @param  CallbackID ID of the callback to be unregistered
00521   *         This parameter can be one of the following values:
00522   *          @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID    SPDIFRX Data flow half completed callback ID
00523   *          @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID    SPDIFRX Data flow completed callback ID
00524   *          @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID    SPDIFRX Control flow half completed callback ID
00525   *          @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID    SPDIFRX Control flow completed callback ID
00526   *          @arg @ref HAL_SPDIFRX_ERROR_CB_ID      SPDIFRX error callback ID
00527   *          @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID    MspInit callback ID
00528   *          @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID  MspDeInit callback ID
00529   * @retval HAL status
00530   */
00531 HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
00532 {
00533 HAL_StatusTypeDef status = HAL_OK;
00534
00535   /* Process locked */
00536   __HAL_LOCK(hspdif);
00537
00538   if(HAL_SPDIFRX_STATE_READY == hspdif->State)
00539   {
00540     switch (CallbackID)
00541     {
00542       case HAL_SPDIFRX_RX_HALF_CB_ID :
00543         hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback;
00544         break;
00545
00546       case HAL_SPDIFRX_RX_CPLT_CB_ID :
00547         hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback;
00548         break;
00549
00550       case HAL_SPDIFRX_CX_HALF_CB_ID :
00551         hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback;
00552         break;
00553
00554       case HAL_SPDIFRX_CX_CPLT_CB_ID :
00555         hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback;
00556         break;
00557
00558       case HAL_SPDIFRX_ERROR_CB_ID :
00559         hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback;
00560         break;
00561
00562       default :
00563         /* Update the error code */
00564         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00565        /* Return error status */
00566         status =  HAL_ERROR;
00567         break;
00568     }
00569   }
00570   else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
00571   {
00572     switch (CallbackID)
00573     {
00574       case HAL_SPDIFRX_MSPINIT_CB_ID :
00575         hspdif->MspInitCallback = HAL_SPDIFRX_MspInit;  /* Legacy weak MspInit  */
00576         break;
00577
00578       case HAL_SPDIFRX_MSPDEINIT_CB_ID :
00579         hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit;  /* Legacy weak MspInit  */
00580         break;
00581
00582       default :
00583         /* Update the error code */
00584         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00585         /* Return error status */
00586         status =  HAL_ERROR;
00587         break;
00588     }
00589   }
00590   else
00591   {
00592     /* Update the error code */
00593     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
00594     /* Return error status */
00595     status =  HAL_ERROR;
00596   }
00597
00598   /* Release Lock */
00599   __HAL_UNLOCK(hspdif);
00600   return status;
00601 }
00602
00603 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00604
00605 /**
00606   * @brief Set the SPDIFRX  data format according to the specified parameters in the SPDIFRX_InitTypeDef.
00607   * @param hspdif SPDIFRX handle
00608   * @param sDataFormat SPDIFRX data format
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
00612 {
00613   uint32_t tmpreg;
00614
00615   /* Check the SPDIFRX handle allocation */
00616   if(hspdif == NULL)
00617   {
00618     return HAL_ERROR;
00619   }
00620
00621   /* Check the SPDIFRX parameters */
00622   assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
00623   assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
00624   assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
00625   assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
00626   assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
00627   assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
00628
00629   /* Reset the old SPDIFRX CR configuration */
00630   tmpreg = hspdif->Instance->CR;
00631
00632   if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
00633      (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
00634       ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
00635   {
00636     return HAL_ERROR;
00637   }
00638
00639   tmpreg &= ~(SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00640               SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
00641
00642   /* Configure the new data format */
00643   tmpreg |= (sDataFormat.StereoMode |
00644              sDataFormat.DataFormat |
00645              sDataFormat.PreambleTypeMask |
00646              sDataFormat.ChannelStatusMask |
00647              sDataFormat.ValidityBitMask |
00648              sDataFormat.ParityErrorMask);
00649
00650   hspdif->Instance->CR = tmpreg;
00651
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
00660   *  @brief Data transfers functions
00661   *
00662 @verbatim
00663 ===============================================================================
00664                      ##### IO operation functions #####
00665 ===============================================================================
00666     [..]
00667     This subsection provides a set of functions allowing to manage the SPDIFRX data
00668     transfers.
00669
00670     (#) There is two mode of transfer:
00671         (++) Blocking mode : The communication is performed in the polling mode.
00672              The status of all data processing is returned by the same function
00673              after finishing transfer.
00674         (++) No-Blocking mode : The communication is performed using Interrupts
00675              or DMA. These functions return the status of the transfer start-up.
00676              The end of the data processing will be indicated through the
00677              dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
00678              using DMA mode.
00679
00680     (#) Blocking mode functions are :
00681         (++) HAL_SPDIFRX_ReceiveDataFlow()
00682         (++) HAL_SPDIFRX_ReceiveCtrlFlow()
00683                 (+@) Do not use blocking mode to receive both control and data flow at the same time.
00684
00685     (#) No-Blocking mode functions with Interrupt are :
00686         (++) HAL_SPDIFRX_ReceiveCtrlFlow_IT()
00687         (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
00688
00689     (#) No-Blocking mode functions with DMA are :
00690         (++) HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
00691         (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
00692
00693     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00694         (++) HAL_SPDIFRX_RxCpltCallback()
00695         (++) HAL_SPDIFRX_CxCpltCallback()
00696
00697 @endverbatim
00698 * @{
00699 */
00700
00701 /**
00702   * @brief  Receives an amount of data (Data Flow) in blocking mode.
00703   * @param  hspdif pointer to SPDIFRX_HandleTypeDef structure that contains
00704   *                 the configuration information for SPDIFRX module.
00705   * @param  pData Pointer to data buffer
00706   * @param  Size Amount of data to be received
00707   * @param  Timeout Timeout duration
00708   * @retval HAL status
00709   */
00710 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00711 {
00712   uint32_t tickstart;
00713   uint16_t sizeCounter = Size;
00714   uint32_t *pTmpBuf = pData;
00715
00716   if((pData == NULL ) || (Size == 0U))
00717   {
00718     return  HAL_ERROR;
00719   }
00720
00721   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00722   {
00723     /* Process Locked */
00724     __HAL_LOCK(hspdif);
00725
00726     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00727
00728     /* Start synchronisation */
00729     __HAL_SPDIFRX_SYNC(hspdif);
00730
00731     /* Get tick */
00732     tickstart = HAL_GetTick();
00733
00734     /* Wait until SYNCD flag is set */
00735     if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
00736     {
00737       return HAL_TIMEOUT;
00738     }
00739
00740     /* Start reception */
00741     __HAL_SPDIFRX_RCV(hspdif);
00742
00743     /* Receive data flow */
00744     while(sizeCounter > 0U)
00745     {
00746       /* Get tick */
00747       tickstart = HAL_GetTick();
00748
00749       /* Wait until RXNE flag is set */
00750       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
00751       {
00752         return HAL_TIMEOUT;
00753       }
00754
00755       (*pTmpBuf) = hspdif->Instance->DR;
00756       pTmpBuf++;
00757       sizeCounter--;
00758     }
00759
00760     /* SPDIFRX ready */
00761     hspdif->State = HAL_SPDIFRX_STATE_READY;
00762
00763     /* Process Unlocked */
00764     __HAL_UNLOCK(hspdif);
00765
00766     return HAL_OK;
00767   }
00768   else
00769   {
00770     return HAL_BUSY;
00771   }
00772 }
00773
00774 /**
00775   * @brief  Receives an amount of data (Control Flow) in blocking mode.
00776   * @param  hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains
00777   *                 the configuration information for SPDIFRX module.
00778   * @param  pData Pointer to data buffer
00779   * @param  Size Amount of data to be received
00780   * @param  Timeout Timeout duration
00781   * @retval HAL status
00782   */
00783 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00784 {
00785   uint32_t tickstart;
00786   uint16_t sizeCounter = Size;
00787   uint32_t *pTmpBuf = pData;
00788
00789   if((pData == NULL ) || (Size == 0U))
00790   {
00791     return  HAL_ERROR;
00792   }
00793
00794   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00795   {
00796     /* Process Locked */
00797     __HAL_LOCK(hspdif);
00798
00799     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00800
00801     /* Start synchronization */
00802     __HAL_SPDIFRX_SYNC(hspdif);
00803
00804     /* Get tick */
00805     tickstart = HAL_GetTick();
00806
00807     /* Wait until SYNCD flag is set */
00808     if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
00809     {
00810       return HAL_TIMEOUT;
00811     }
00812
00813     /* Start reception */
00814     __HAL_SPDIFRX_RCV(hspdif);
00815
00816     /* Receive control flow */
00817     while(sizeCounter > 0U)
00818     {
00819       /* Get tick */
00820       tickstart = HAL_GetTick();
00821
00822       /* Wait until CSRNE flag is set */
00823       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
00824       {
00825         return HAL_TIMEOUT;
00826       }
00827
00828       (*pTmpBuf) = hspdif->Instance->CSR;
00829       pTmpBuf++;
00830       sizeCounter--;
00831     }
00832
00833     /* SPDIFRX ready */
00834     hspdif->State = HAL_SPDIFRX_STATE_READY;
00835
00836     /* Process Unlocked */
00837     __HAL_UNLOCK(hspdif);
00838
00839     return HAL_OK;
00840   }
00841   else
00842   {
00843     return HAL_BUSY;
00844   }
00845 }
00846
00847 /**
00848   * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
00849   * @param hspdif SPDIFRX handle
00850   * @param pData a 32-bit pointer to the Receive data buffer.
00851   * @param Size number of data sample to be received .
00852   * @retval HAL status
00853   */
00854 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00855 {
00856   register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
00857
00858   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
00859
00860   if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
00861   {
00862     if((pData == NULL) || (Size == 0U))
00863     {
00864       return HAL_ERROR;
00865     }
00866
00867     /* Process Locked */
00868     __HAL_LOCK(hspdif);
00869
00870     hspdif->pRxBuffPtr = pData;
00871     hspdif->RxXferSize = Size;
00872     hspdif->RxXferCount = Size;
00873
00874     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00875
00876     /* Check if a receive process is ongoing or not */
00877     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00878
00879     /* Enable the SPDIFRX  PE Error Interrupt */
00880     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00881
00882     /* Enable the SPDIFRX  OVR Error Interrupt */
00883     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00884
00885     /* Enable the SPDIFRX RXNE interrupt */
00886     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00887
00888     if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
00889     {
00890       /* Start synchronization */
00891       __HAL_SPDIFRX_SYNC(hspdif);
00892
00893       /* Wait until SYNCD flag is set */
00894       do
00895       {
00896         if (count == 0U)
00897         {
00898           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
00899           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00900           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00901           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00902           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00903           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
00904           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
00905           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
00906
00907           hspdif->State= HAL_SPDIFRX_STATE_READY;
00908
00909           /* Process Unlocked */
00910           __HAL_UNLOCK(hspdif);
00911
00912           return HAL_TIMEOUT;
00913         }
00914         count--;
00915       } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
00916
00917       /* Start reception */
00918       __HAL_SPDIFRX_RCV(hspdif);
00919     }
00920
00921     /* Process Unlocked */
00922     __HAL_UNLOCK(hspdif);
00923
00924     return HAL_OK;
00925   }
00926   else
00927   {
00928     return HAL_BUSY;
00929   }
00930 }
00931
00932 /**
00933   * @brief Receive an amount of data (Control Flow) with Interrupt
00934   * @param hspdif SPDIFRX handle
00935   * @param pData a 32-bit pointer to the Receive data buffer.
00936   * @param Size number of data sample (Control Flow) to be received
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00940 {
00941   register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
00942
00943   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
00944
00945   if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
00946   {
00947     if((pData == NULL ) || (Size == 0U))
00948     {
00949       return HAL_ERROR;
00950     }
00951
00952     /* Process Locked */
00953     __HAL_LOCK(hspdif);
00954
00955     hspdif->pCsBuffPtr = pData;
00956     hspdif->CsXferSize = Size;
00957     hspdif->CsXferCount = Size;
00958
00959     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00960
00961     /* Check if a receive process is ongoing or not */
00962     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00963
00964     /* Enable the SPDIFRX PE Error Interrupt */
00965     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00966
00967     /* Enable the SPDIFRX OVR Error Interrupt */
00968     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00969
00970     /* Enable the SPDIFRX CSRNE interrupt */
00971     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00972
00973     if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
00974     {
00975       /* Start synchronization */
00976       __HAL_SPDIFRX_SYNC(hspdif);
00977
00978       /* Wait until SYNCD flag is set */
00979       do
00980       {
00981         if (count == 0U)
00982         {
00983           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
00984           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00985           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00986           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00987           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00988           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
00989           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
00990           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
00991
00992           hspdif->State= HAL_SPDIFRX_STATE_READY;
00993
00994           /* Process Unlocked */
00995           __HAL_UNLOCK(hspdif);
00996
00997           return HAL_TIMEOUT;
00998         }
00999         count--;
01000       } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
01001
01002       /* Start reception */
01003       __HAL_SPDIFRX_RCV(hspdif);
01004     }
01005
01006     /* Process Unlocked */
01007     __HAL_UNLOCK(hspdif);
01008
01009     return HAL_OK;
01010   }
01011   else
01012   {
01013     return HAL_BUSY;
01014   }
01015 }
01016
01017 /**
01018   * @brief Receive an amount of data (Data Flow) mode with DMA
01019   * @param hspdif SPDIFRX handle
01020   * @param pData a 32-bit pointer to the Receive data buffer.
01021   * @param Size number of data sample to be received
01022   * @retval HAL status
01023   */
01024 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
01025 {
01026   register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
01027
01028   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
01029
01030   if((pData == NULL) || (Size == 0U))
01031   {
01032     return  HAL_ERROR;
01033   }
01034
01035   if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
01036   {
01037     /* Process Locked */
01038     __HAL_LOCK(hspdif);
01039
01040     hspdif->pRxBuffPtr = pData;
01041     hspdif->RxXferSize = Size;
01042     hspdif->RxXferCount = Size;
01043
01044     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
01045     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
01046
01047     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
01048     hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
01049
01050     /* Set the SPDIFRX Rx DMA transfer complete callback */
01051     hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
01052
01053     /* Set the DMA error callback */
01054     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
01055
01056     /* Enable the DMA request */
01057     if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
01058     {
01059       /* Set SPDIFRX error */
01060       hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
01061
01062       /* Set SPDIFRX state */
01063       hspdif->State = HAL_SPDIFRX_STATE_ERROR;
01064
01065       /* Process Unlocked */
01066       __HAL_UNLOCK(hspdif);
01067
01068       return HAL_ERROR;
01069     }
01070
01071     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
01072     hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
01073
01074     if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
01075     {
01076       /* Start synchronization */
01077       __HAL_SPDIFRX_SYNC(hspdif);
01078
01079       /* Wait until SYNCD flag is set */
01080       do
01081       {
01082         if (count == 0U)
01083         {
01084           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01085           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01086           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01087           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01088           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01089           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01090           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01091           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01092
01093           hspdif->State= HAL_SPDIFRX_STATE_READY;
01094
01095           /* Process Unlocked */
01096           __HAL_UNLOCK(hspdif);
01097
01098           return HAL_TIMEOUT;
01099         }
01100         count--;
01101       } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
01102
01103       /* Start reception */
01104       __HAL_SPDIFRX_RCV(hspdif);
01105     }
01106
01107     /* Process Unlocked */
01108     __HAL_UNLOCK(hspdif);
01109
01110     return HAL_OK;
01111   }
01112   else
01113   {
01114     return HAL_BUSY;
01115   }
01116 }
01117
01118 /**
01119   * @brief Receive an amount of data (Control Flow) with DMA
01120   * @param hspdif SPDIFRX handle
01121   * @param pData a 32-bit pointer to the Receive data buffer.
01122   * @param Size number of data (Control Flow) sample to be received
01123   * @retval HAL status
01124   */
01125 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
01126 {
01127   register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
01128
01129   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
01130
01131   if((pData == NULL) || (Size == 0U))
01132   {
01133     return  HAL_ERROR;
01134   }
01135
01136   if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
01137   {
01138     hspdif->pCsBuffPtr = pData;
01139     hspdif->CsXferSize = Size;
01140     hspdif->CsXferCount = Size;
01141
01142     /* Process Locked */
01143     __HAL_LOCK(hspdif);
01144
01145     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
01146     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
01147
01148     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
01149     hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
01150
01151     /* Set the SPDIFRX Rx DMA transfer complete callback */
01152     hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
01153
01154     /* Set the DMA error callback */
01155     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
01156
01157     /* Enable the DMA request */
01158     if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
01159     {
01160       /* Set SPDIFRX error */
01161       hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
01162
01163       /* Set SPDIFRX state */
01164       hspdif->State = HAL_SPDIFRX_STATE_ERROR;
01165
01166       /* Process Unlocked */
01167       __HAL_UNLOCK(hspdif);
01168
01169       return HAL_ERROR;
01170     }
01171
01172     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
01173     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
01174
01175     if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
01176     {
01177       /* Start synchronization */
01178       __HAL_SPDIFRX_SYNC(hspdif);
01179
01180       /* Wait until SYNCD flag is set */
01181       do
01182       {
01183         if (count == 0U)
01184         {
01185           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01186           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01187           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01188           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01189           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01190           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01191           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01192           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01193
01194           hspdif->State= HAL_SPDIFRX_STATE_READY;
01195
01196           /* Process Unlocked */
01197           __HAL_UNLOCK(hspdif);
01198
01199           return HAL_TIMEOUT;
01200         }
01201         count--;
01202       } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
01203
01204       /* Start reception */
01205       __HAL_SPDIFRX_RCV(hspdif);
01206     }
01207
01208     /* Process Unlocked */
01209     __HAL_UNLOCK(hspdif);
01210
01211     return HAL_OK;
01212   }
01213   else
01214   {
01215     return HAL_BUSY;
01216   }
01217 }
01218
01219 /**
01220   * @brief stop the audio stream receive from the Media.
01221   * @param hspdif SPDIFRX handle
01222   * @retval None
01223   */
01224 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
01225 {
01226   /* Process Locked */
01227   __HAL_LOCK(hspdif);
01228
01229   /* Disable the SPDIFRX DMA requests */
01230   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
01231   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
01232
01233   /* Disable the SPDIFRX DMA channel */
01234   __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
01235   __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
01236
01237   /* Disable SPDIFRX peripheral */
01238   __HAL_SPDIFRX_IDLE(hspdif);
01239
01240   hspdif->State = HAL_SPDIFRX_STATE_READY;
01241
01242   /* Process Unlocked */
01243   __HAL_UNLOCK(hspdif);
01244
01245   return HAL_OK;
01246 }
01247
01248 /**
01249   * @brief  This function handles SPDIFRX interrupt request.
01250   * @param  hspdif SPDIFRX handle
01251   * @retval HAL status
01252   */
01253 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
01254 {
01255   uint32_t itFlag   = hspdif->Instance->SR;
01256   uint32_t itSource = hspdif->Instance->IMR;
01257
01258   /* SPDIFRX in mode Data Flow Reception */
01259   if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource &  SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
01260   {
01261     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
01262     SPDIFRX_ReceiveDataFlow_IT(hspdif);
01263   }
01264
01265   /* SPDIFRX in mode Control Flow Reception */
01266   if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource &  SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
01267   {
01268     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
01269     SPDIFRX_ReceiveControlFlow_IT(hspdif);
01270   }
01271
01272   /* SPDIFRX Overrun error interrupt occurred */
01273   if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource &  SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
01274   {
01275     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
01276
01277     /* Change the SPDIFRX error code */
01278     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
01279
01280     /* the transfer is not stopped */
01281     HAL_SPDIFRX_ErrorCallback(hspdif);
01282   }
01283
01284   /* SPDIFRX Parity error interrupt occurred */
01285   if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource &  SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
01286   {
01287     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
01288
01289     /* Change the SPDIFRX error code */
01290     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
01291
01292     /* the transfer is not stopped */
01293     HAL_SPDIFRX_ErrorCallback(hspdif);
01294   }
01295 }
01296
01297 /**
01298   * @brief Rx Transfer (Data flow) half completed callbacks
01299   * @param hspdif SPDIFRX handle
01300   * @retval None
01301   */
01302 __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
01303 {
01304   /* Prevent unused argument(s) compilation warning */
01305   UNUSED(hspdif);
01306
01307   /* NOTE : This function Should not be modified, when the callback is needed,
01308             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
01309   */
01310 }
01311
01312 /**
01313   * @brief Rx Transfer (Data flow) completed callbacks
01314   * @param hspdif SPDIFRX handle
01315   * @retval None
01316   */
01317 __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
01318 {
01319   /* Prevent unused argument(s) compilation warning */
01320   UNUSED(hspdif);
01321
01322   /* NOTE : This function Should not be modified, when the callback is needed,
01323             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
01324   */
01325 }
01326
01327 /**
01328   * @brief Rx (Control flow) Transfer half completed callbacks
01329   * @param hspdif SPDIFRX handle
01330   * @retval None
01331   */
01332 __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
01333 {
01334   /* Prevent unused argument(s) compilation warning */
01335   UNUSED(hspdif);
01336
01337   /* NOTE : This function Should not be modified, when the callback is needed,
01338             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
01339   */
01340 }
01341
01342 /**
01343   * @brief Rx Transfer (Control flow) completed callbacks
01344   * @param hspdif SPDIFRX handle
01345   * @retval None
01346   */
01347 __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
01348 {
01349   /* Prevent unused argument(s) compilation warning */
01350   UNUSED(hspdif);
01351
01352   /* NOTE : This function Should not be modified, when the callback is needed,
01353             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
01354   */
01355 }
01356
01357 /**
01358   * @brief SPDIFRX error callbacks
01359   * @param hspdif SPDIFRX handle
01360   * @retval None
01361   */
01362 __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
01363 {
01364   /* Prevent unused argument(s) compilation warning */
01365   UNUSED(hspdif);
01366
01367   /* NOTE : This function Should not be modified, when the callback is needed,
01368             the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
01369   */
01370 }
01371
01372 /**
01373   * @}
01374   */
01375
01376 /** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
01377   *  @brief   Peripheral State functions
01378   *
01379 @verbatim
01380 ===============================================================================
01381 ##### Peripheral State and Errors functions #####
01382 ===============================================================================
01383 [..]
01384 This subsection permit to get in run-time the status of the peripheral
01385 and the data flow.
01386
01387 @endverbatim
01388   * @{
01389   */
01390
01391 /**
01392   * @brief  Return the SPDIFRX state
01393   * @param  hspdif SPDIFRX handle
01394   * @retval HAL state
01395   */
01396 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif)
01397 {
01398   return hspdif->State;
01399 }
01400
01401 /**
01402   * @brief  Return the SPDIFRX error code
01403   * @param  hspdif SPDIFRX handle
01404   * @retval SPDIFRX Error Code
01405   */
01406 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
01407 {
01408   return hspdif->ErrorCode;
01409 }
01410
01411 /**
01412   * @}
01413   */
01414
01415 /**
01416   * @brief DMA SPDIFRX receive process (Data flow) complete callback
01417   * @param hdma DMA handle
01418   * @retval None
01419   */
01420 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
01421 {
01422   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01423
01424   /* Disable Rx DMA Request */
01425   if(hdma->Init.Mode != DMA_CIRCULAR)
01426   {
01427     hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
01428     hspdif->RxXferCount = 0;
01429     hspdif->State = HAL_SPDIFRX_STATE_READY;
01430   }
01431 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01432   hspdif->RxCpltCallback(hspdif);
01433 #else
01434   HAL_SPDIFRX_RxCpltCallback(hspdif);
01435 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01436 }
01437
01438 /**
01439   * @brief DMA SPDIFRX receive process (Data flow) half complete callback
01440   * @param hdma DMA handle
01441   * @retval None
01442   */
01443 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01444 {
01445   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01446
01447 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01448   hspdif->RxHalfCpltCallback(hspdif);
01449 #else
01450   HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
01451 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01452 }
01453
01454
01455 /**
01456   * @brief DMA SPDIFRX receive process (Control flow) complete callback
01457   * @param hdma DMA handle
01458   * @retval None
01459   */
01460 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
01461 {
01462   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01463
01464   /* Disable Cb DMA Request */
01465   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
01466   hspdif->CsXferCount = 0;
01467
01468   hspdif->State = HAL_SPDIFRX_STATE_READY;
01469 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01470   hspdif->CxCpltCallback(hspdif);
01471 #else
01472   HAL_SPDIFRX_CxCpltCallback(hspdif);
01473 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01474 }
01475
01476 /**
01477   * @brief DMA SPDIFRX receive process (Control flow) half complete callback
01478   * @param hdma DMA handle
01479   * @retval None
01480   */
01481 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
01482 {
01483   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01484
01485 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01486   hspdif->CxHalfCpltCallback(hspdif);
01487 #else
01488   HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
01489 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01490 }
01491
01492 /**
01493   * @brief DMA SPDIFRX communication error callback
01494   * @param hdma DMA handle
01495   * @retval None
01496   */
01497 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
01498 {
01499   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01500
01501   /* Disable Rx and Cb DMA Request */
01502   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
01503   hspdif->RxXferCount = 0;
01504
01505   hspdif->State= HAL_SPDIFRX_STATE_READY;
01506
01507   /* Set the error code and execute error callback*/
01508   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
01509
01510 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01511   /* The transfer is not stopped */
01512   hspdif->ErrorCallback(hspdif);
01513 #else
01514   /* The transfer is not stopped */
01515   HAL_SPDIFRX_ErrorCallback(hspdif);
01516 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01517 }
01518
01519 /**
01520   * @brief Receive an amount of data (Data Flow) with Interrupt
01521   * @param hspdif SPDIFRX handle
01522   * @retval None
01523   */
01524 static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01525 {
01526   /* Receive data */
01527   (*hspdif->pRxBuffPtr) = hspdif->Instance->DR;
01528   hspdif->pRxBuffPtr++;
01529   hspdif->RxXferCount--;
01530
01531   if(hspdif->RxXferCount == 0U)
01532   {
01533     /* Disable RXNE/PE and OVR interrupts */
01534     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
01535
01536     hspdif->State = HAL_SPDIFRX_STATE_READY;
01537
01538     /* Process Unlocked */
01539     __HAL_UNLOCK(hspdif);
01540
01541 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01542   hspdif->RxCpltCallback(hspdif);
01543 #else
01544   HAL_SPDIFRX_RxCpltCallback(hspdif);
01545 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01546   }
01547 }
01548
01549 /**
01550   * @brief Receive an amount of data (Control Flow) with Interrupt
01551   * @param hspdif SPDIFRX handle
01552   * @retval None
01553   */
01554 static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01555 {
01556   /* Receive data */
01557   (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR;
01558   hspdif->pCsBuffPtr++;
01559   hspdif->CsXferCount--;
01560
01561   if(hspdif->CsXferCount == 0U)
01562   {
01563     /* Disable CSRNE interrupt */
01564     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01565
01566     hspdif->State = HAL_SPDIFRX_STATE_READY;
01567
01568     /* Process Unlocked */
01569     __HAL_UNLOCK(hspdif);
01570
01571 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
01572   hspdif->CxCpltCallback(hspdif);
01573 #else
01574   HAL_SPDIFRX_CxCpltCallback(hspdif);
01575 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
01576   }
01577 }
01578
01579 /**
01580   * @brief This function handles SPDIFRX Communication Timeout.
01581   * @param hspdif SPDIFRX handle
01582   * @param Flag Flag checked
01583   * @param Status Value of the flag expected
01584   * @param Timeout Duration of the timeout
01585   * @param tickstart Tick start value
01586   * @retval HAL status
01587   */
01588 static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
01589 {
01590   /* Wait until flag is set */
01591   while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
01592   {
01593     /* Check for the Timeout */
01594     if(Timeout != HAL_MAX_DELAY)
01595     {
01596       if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
01597       {
01598         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01599         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01600         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01601         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01602         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01603         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01604         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01605         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01606
01607         hspdif->State= HAL_SPDIFRX_STATE_READY;
01608
01609         /* Process Unlocked */
01610         __HAL_UNLOCK(hspdif);
01611
01612         return HAL_TIMEOUT;
01613       }
01614     }
01615   }
01616
01617   return HAL_OK;
01618 }
01619
01620 /**
01621   * @}
01622   */
01623
01624
01625 #endif /* SPDIFRX */
01626 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
01627 /**
01628   * @}
01629   */
01630
01631 /**
01632   * @}
01633   */
01634
01635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spdifrx.h Source File

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stm32h7xx_hal_spdifrx.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spdifrx.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPDIFRX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SPDIFRX_H
00022 #define STM32H7xx_HAL_SPDIFRX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031
00032 /** @addtogroup STM32H7xx_HAL_Driver
00033   * @{
00034   */
00035 #if defined (SPDIFRX)
00036
00037 /** @addtogroup SPDIFRX
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief SPDIFRX Init structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.
00052                                           This parameter can be a value of @ref SPDIFRX_Input_Selection */
00053
00054   uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.
00055                                           This parameter can be a value of @ref SPDIFRX_Max_Retries */
00056
00057   uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
00058                                           This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
00059
00060   uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.
00061                                           This parameter can be a value of @ref SPDIFRX_Channel_Selection */
00062
00063   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00064                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00065
00066   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00067                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00068
00069   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00070                                            This parameter can be a value of @ref SPDIFRX_PT_Mask */
00071
00072   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00073                                           This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00074
00075   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00076                                           This parameter can be a value of @ref SPDIFRX_V_Mask */
00077
00078   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00079                                           This parameter can be a value of @ref SPDIFRX_PE_Mask */
00080   FunctionalState SymbolClockGen;     /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
00081                                           This parameter can be set to Enable or Disable */
00082
00083   FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
00084                                           This parameter can be set to Enable or Disable */
00085 } SPDIFRX_InitTypeDef;
00086
00087 /**
00088   * @brief SPDIFRX SetDataFormat structure definition
00089   */
00090 typedef struct
00091 {
00092   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00093                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00094
00095   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00096                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00097
00098   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00099                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00100
00101   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00102                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00103
00104   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00105                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00106
00107   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00108                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00109
00110 } SPDIFRX_SetDataFormatTypeDef;
00111
00112 /**
00113   * @brief  HAL State structures definition
00114   */
00115 typedef enum
00116 {
00117   HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */
00118   HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */
00119   HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */
00120   HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */
00121   HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */
00122   HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */
00123 } HAL_SPDIFRX_StateTypeDef;
00124
00125 /**
00126   * @brief SPDIFRX handle Structure definition
00127   */
00128 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00129 typedef struct __SPDIFRX_HandleTypeDef
00130 #else
00131 typedef struct
00132 #endif
00133 {
00134   SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
00135
00136   SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */
00137
00138   uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */
00139
00140   uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */
00141
00142   __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */
00143
00144   __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter
00145                                               (This field is initialized at the
00146                                                same value as transfer size at the
00147                                                beginning of the transfer and
00148                                                decremented when a sample is received.
00149                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00150
00151   __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */
00152
00153   __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter
00154                                               (This field is initialized at the
00155                                                same value as transfer size at the
00156                                                beginning of the transfer and
00157                                                decremented when a sample is received.
00158                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00159
00160   DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
00161
00162   DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
00163
00164   __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */
00165
00166   __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */
00167
00168   __IO uint32_t  ErrorCode;                /* SPDIFRX Error code */
00169
00170 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00171   void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Data flow half completed callback */
00172   void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Data flow completed callback */
00173   void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Control flow half completed callback */
00174   void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Control flow completed callback */
00175   void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);        /*!< SPDIFRX error callback */
00176   void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif);   /*!< SPDIFRX Msp Init callback  */
00177   void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback  */
00178 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00179
00180 } SPDIFRX_HandleTypeDef;
00181 /**
00182   * @}
00183   */
00184
00185 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00186 /**
00187   * @brief  HAL SPDIFRX Callback ID enumeration definition
00188   */
00189 typedef enum
00190 {
00191   HAL_SPDIFRX_RX_HALF_CB_ID   = 0x00U,    /*!< SPDIFRX Data flow half completed callback ID */
00192   HAL_SPDIFRX_RX_CPLT_CB_ID   = 0x01U,    /*!< SPDIFRX Data flow completed callback */
00193   HAL_SPDIFRX_CX_HALF_CB_ID   = 0x02U,    /*!< SPDIFRX Control flow half completed callback */
00194   HAL_SPDIFRX_CX_CPLT_CB_ID   = 0x03U,    /*!< SPDIFRX Control flow completed callback */
00195   HAL_SPDIFRX_ERROR_CB_ID     = 0x04U,    /*!< SPDIFRX error callback */
00196   HAL_SPDIFRX_MSPINIT_CB_ID   = 0x05U,    /*!< SPDIFRX Msp Init callback ID     */
00197   HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U     /*!< SPDIFRX Msp DeInit callback ID   */
00198 }HAL_SPDIFRX_CallbackIDTypeDef;
00199
00200 /**
00201   * @brief  HAL SPDIFRX Callback pointer definition
00202   */
00203 typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
00204 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00205
00206 /* Exported constants --------------------------------------------------------*/
00207 /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
00208   * @{
00209   */
00210 /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
00211   * @{
00212   */
00213 #define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */
00214 #define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */
00215 #define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */
00216 #define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */
00217 #define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */
00218 #define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */
00219 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00220 #define  HAL_SPDIFRX_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
00221 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
00227   * @{
00228   */
00229 #define SPDIFRX_INPUT_IN0   ((uint32_t)0x00000000U)
00230 #define SPDIFRX_INPUT_IN1   ((uint32_t)0x00010000U)
00231 #define SPDIFRX_INPUT_IN2   ((uint32_t)0x00020000U)
00232 #define SPDIFRX_INPUT_IN3   ((uint32_t)0x00030000U)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
00238   * @{
00239   */
00240 #define SPDIFRX_MAXRETRIES_NONE   ((uint32_t)0x00000000U)
00241 #define SPDIFRX_MAXRETRIES_3      ((uint32_t)0x00001000U)
00242 #define SPDIFRX_MAXRETRIES_15     ((uint32_t)0x00002000U)
00243 #define SPDIFRX_MAXRETRIES_63     ((uint32_t)0x00003000U)
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
00249   * @{
00250   */
00251 #define SPDIFRX_WAITFORACTIVITY_OFF   ((uint32_t)0x00000000U)
00252 #define SPDIFRX_WAITFORACTIVITY_ON    ((uint32_t)SPDIFRX_CR_WFA)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
00258   * @{
00259   */
00260 #define SPDIFRX_PREAMBLETYPEMASK_OFF    ((uint32_t)0x00000000U)
00261 #define SPDIFRX_PREAMBLETYPEMASK_ON     ((uint32_t)SPDIFRX_CR_PTMSK)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
00267   * @{
00268   */
00269 #define SPDIFRX_CHANNELSTATUS_OFF   ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */
00270 #define SPDIFRX_CHANNELSTATUS_ON    ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
00276 * @{
00277 */
00278 #define SPDIFRX_VALIDITYMASK_OFF    ((uint32_t)0x00000000U)
00279 #define SPDIFRX_VALIDITYMASK_ON     ((uint32_t)SPDIFRX_CR_VMSK)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask
00285   * @{
00286   */
00287 #define SPDIFRX_PARITYERRORMASK_OFF   ((uint32_t)0x00000000U)
00288 #define SPDIFRX_PARITYERRORMASK_ON    ((uint32_t)SPDIFRX_CR_PMSK)
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection
00294   * @{
00295   */
00296 #define SPDIFRX_CHANNEL_A   ((uint32_t)0x00000000U)
00297 #define SPDIFRX_CHANNEL_B   ((uint32_t)SPDIFRX_CR_CHSEL)
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
00303   * @{
00304   */
00305 #define SPDIFRX_DATAFORMAT_LSB      ((uint32_t)0x00000000U)
00306 #define SPDIFRX_DATAFORMAT_MSB      ((uint32_t)0x00000010U)
00307 #define SPDIFRX_DATAFORMAT_32BITS   ((uint32_t)0x00000020U)
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
00313   * @{
00314   */
00315 #define SPDIFRX_STEREOMODE_DISABLE    ((uint32_t)0x00000000U)
00316 #define SPDIFRX_STEREOMODE_ENABLE     ((uint32_t)SPDIFRX_CR_RXSTEO)
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup SPDIFRX_State SPDIFRX State
00322   * @{
00323   */
00324
00325 #define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)
00326 #define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)
00327 #define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
00333   * @{
00334   */
00335 #define SPDIFRX_IT_RXNE       ((uint32_t)SPDIFRX_IMR_RXNEIE)
00336 #define SPDIFRX_IT_CSRNE      ((uint32_t)SPDIFRX_IMR_CSRNEIE)
00337 #define SPDIFRX_IT_PERRIE     ((uint32_t)SPDIFRX_IMR_PERRIE)
00338 #define SPDIFRX_IT_OVRIE      ((uint32_t)SPDIFRX_IMR_OVRIE)
00339 #define SPDIFRX_IT_SBLKIE     ((uint32_t)SPDIFRX_IMR_SBLKIE)
00340 #define SPDIFRX_IT_SYNCDIE    ((uint32_t)SPDIFRX_IMR_SYNCDIE)
00341 #define SPDIFRX_IT_IFEIE      ((uint32_t)SPDIFRX_IMR_IFEIE )
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
00347   * @{
00348   */
00349 #define SPDIFRX_FLAG_RXNE     ((uint32_t)SPDIFRX_SR_RXNE)
00350 #define SPDIFRX_FLAG_CSRNE    ((uint32_t)SPDIFRX_SR_CSRNE)
00351 #define SPDIFRX_FLAG_PERR     ((uint32_t)SPDIFRX_SR_PERR)
00352 #define SPDIFRX_FLAG_OVR      ((uint32_t)SPDIFRX_SR_OVR)
00353 #define SPDIFRX_FLAG_SBD      ((uint32_t)SPDIFRX_SR_SBD)
00354 #define SPDIFRX_FLAG_SYNCD    ((uint32_t)SPDIFRX_SR_SYNCD)
00355 #define SPDIFRX_FLAG_FERR     ((uint32_t)SPDIFRX_SR_FERR)
00356 #define SPDIFRX_FLAG_SERR     ((uint32_t)SPDIFRX_SR_SERR)
00357 #define SPDIFRX_FLAG_TERR     ((uint32_t)SPDIFRX_SR_TERR)
00358 /**
00359   * @}
00360   */
00361
00362 /**
00363   * @}
00364   */
00365
00366 /* Exported macros -----------------------------------------------------------*/
00367 /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
00368   * @{
00369   */
00370
00371 /** @brief  Reset SPDIFRX handle state
00372   * @param  __HANDLE__ SPDIFRX handle.
00373   * @retval None
00374   */
00375 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00376 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
00377                                                       (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
00378                                                       (__HANDLE__)->MspInitCallback = NULL;\
00379                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00380                                                      }while(0)
00381 #else
00382 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
00383 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00384
00385 /** @brief  Disable the specified SPDIFRX peripheral (IDLE State).
00386   * @param  __HANDLE__ specifies the SPDIFRX Handle.
00387   * @retval None
00388   */
00389 #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
00390
00391 /** @brief  Enable the specified SPDIFRX peripheral (SYNC State).
00392   * @param  __HANDLE__ specifies the SPDIFRX Handle.
00393   * @retval None
00394   */
00395 #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
00396
00397
00398 /** @brief  Enable the specified SPDIFRX peripheral (RCV State).
00399   * @param  __HANDLE__ specifies the SPDIFRX Handle.
00400   * @retval None
00401   */
00402 #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
00403
00404
00405 /** @brief  Enable or disable the specified SPDIFRX interrupts.
00406   * @param  __HANDLE__    specifies the SPDIFRX Handle.
00407   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00408   *        This parameter can be one of the following values:
00409   *            @arg SPDIFRX_IT_RXNE
00410   *            @arg SPDIFRX_IT_CSRNE
00411   *            @arg SPDIFRX_IT_PERRIE
00412   *            @arg SPDIFRX_IT_OVRIE
00413   *            @arg SPDIFRX_IT_SBLKIE
00414   *            @arg SPDIFRX_IT_SYNCDIE
00415   *            @arg SPDIFRX_IT_IFEIE
00416   * @retval None
00417   */
00418 #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00419 #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
00420
00421 /** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
00422   * @param  __HANDLE__    specifies the SPDIFRX Handle.
00423   * @param  __INTERRUPT__ specifies the SPDIFRX interrupt source to check.
00424   *          This parameter can be one of the following values:
00425   *            @arg SPDIFRX_IT_RXNE
00426   *            @arg SPDIFRX_IT_CSRNE
00427   *            @arg SPDIFRX_IT_PERRIE
00428   *            @arg SPDIFRX_IT_OVRIE
00429   *            @arg SPDIFRX_IT_SBLKIE
00430   *            @arg SPDIFRX_IT_SYNCDIE
00431   *            @arg SPDIFRX_IT_IFEIE
00432   * @retval The new state of __IT__ (TRUE or FALSE).
00433   */
00434 #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00435
00436 /** @brief  Checks whether the specified SPDIFRX flag is set or not.
00437   * @param  __HANDLE__  specifies the SPDIFRX Handle.
00438   * @param  __FLAG__    specifies the flag to check.
00439   *        This parameter can be one of the following values:
00440   *            @arg SPDIFRX_FLAG_RXNE
00441   *            @arg SPDIFRX_FLAG_CSRNE
00442   *            @arg SPDIFRX_FLAG_PERR
00443   *            @arg SPDIFRX_FLAG_OVR
00444   *            @arg SPDIFRX_FLAG_SBD
00445   *            @arg SPDIFRX_FLAG_SYNCD
00446   *            @arg SPDIFRX_FLAG_FERR
00447   *            @arg SPDIFRX_FLAG_SERR
00448   *            @arg SPDIFRX_FLAG_TERR
00449   * @retval The new state of __FLAG__ (TRUE or FALSE).
00450   */
00451 #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00452
00453 /** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
00454   * @param  __HANDLE__    specifies the USART Handle.
00455   * @param  __IT_CLEAR__  specifies the interrupt clear register flag that needs to be set
00456   *                       to clear the corresponding interrupt
00457   *          This parameter can be one of the following values:
00458   *            @arg SPDIFRX_FLAG_PERR
00459   *            @arg SPDIFRX_FLAG_OVR
00460   *            @arg SPDIFRX_SR_SBD
00461   *            @arg SPDIFRX_SR_SYNCD
00462   * @retval None
00463   */
00464 #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
00465
00466 /**
00467   * @}
00468   */
00469
00470 /* Exported functions --------------------------------------------------------*/
00471 /** @addtogroup SPDIFRX_Exported_Functions
00472   * @{
00473   */
00474
00475 /** @addtogroup SPDIFRX_Exported_Functions_Group1
00476   * @{
00477   */
00478 /* Initialization/de-initialization functions  **********************************/
00479 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
00480 HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
00481 void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
00482 void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
00483 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
00484
00485 /* Callbacks Register/UnRegister functions  ***********************************/
00486 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
00487 HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
00488 HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
00489 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
00490 /**
00491   * @}
00492   */
00493
00494 /** @addtogroup SPDIFRX_Exported_Functions_Group2
00495   * @{
00496   */
00497 /* I/O operation functions  ***************************************************/
00498  /* Blocking mode: Polling */
00499 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00500 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00501
00502 /* Non-Blocking mode: Interrupt */
00503 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00504 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00505 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
00506
00507 /* Non-Blocking mode: DMA */
00508 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00509 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00510 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
00511
00512 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00513 void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00514 void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00515 void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
00516 void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00517 void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00518 /**
00519   * @}
00520   */
00521
00522 /** @addtogroup SPDIFRX_Exported_Functions_Group3
00523   * @{
00524   */
00525 /* Peripheral Control and State functions  ************************************/
00526 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);
00527 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
00528 /**
00529   * @}
00530   */
00531
00532 /**
00533   * @}
00534   */
00535 /* Private types -------------------------------------------------------------*/
00536 /* Private variables ---------------------------------------------------------*/
00537 /* Private constants ---------------------------------------------------------*/
00538 /* Private macros ------------------------------------------------------------*/
00539 /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
00540   * @{
00541   */
00542 #define IS_SPDIFRX_INPUT_SELECT(INPUT)      (((INPUT) == SPDIFRX_INPUT_IN1) || \
00543                                             ((INPUT) == SPDIFRX_INPUT_IN2)  || \
00544                                             ((INPUT) == SPDIFRX_INPUT_IN3)  || \
00545                                             ((INPUT) == SPDIFRX_INPUT_IN0))
00546
00547 #define IS_SPDIFRX_MAX_RETRIES(RET)         (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
00548                                             ((RET) == SPDIFRX_MAXRETRIES_3)     || \
00549                                             ((RET) == SPDIFRX_MAXRETRIES_15)    || \
00550                                             ((RET) == SPDIFRX_MAXRETRIES_63))
00551
00552 #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)   (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
00553                                             ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
00554
00555 #define IS_PREAMBLE_TYPE_MASK(VAL)          (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
00556                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
00557
00558 #define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
00559                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))
00560
00561 #define IS_PARITY_ERROR_MASK(VAL)           (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
00562                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
00563
00564 #define IS_SPDIFRX_CHANNEL(CHANNEL)         (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
00565                                             ((CHANNEL) == SPDIFRX_CHANNEL_B))
00566
00567 #define IS_SPDIFRX_DATA_FORMAT(FORMAT)      (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
00568                                             ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \
00569                                             ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
00570
00571 #define IS_STEREO_MODE(MODE)                (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
00572                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
00573
00574 #define IS_CHANNEL_STATUS_MASK(VAL)         (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
00575                                             ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
00576
00577 #define IS_SYMBOL_CLOCK_GEN(VAL)            (((VAL) == ENABLE) || ((VAL) == DISABLE))
00578 /**
00579   * @}
00580   */
00581
00582 /* Private functions ---------------------------------------------------------*/
00583 /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
00584   * @{
00585   */
00586 /**
00587   * @}
00588   */
00589
00590 /**
00591   * @}
00592   */
00593 #endif /* SPDIFRX */
00594 /**
00595   * @}
00596   */
00597
00598
00599 #ifdef __cplusplus
00600 }
00601 #endif
00602
00603
00604 #endif /* __STM32H7xx_HAL_SPDIFRX_H */
00605
00606 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi.c Source File

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stm32h7xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The SPI HAL driver can be used as follows:
00019
00020       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00021           SPI_HandleTypeDef  hspi;
00022
00023       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00024           (##) Enable the SPIx interface clock
00025           (##) SPI pins configuration
00026               (+++) Enable the clock for the SPI GPIOs
00027               (+++) Configure these SPI pins as alternate function push-pull
00028           (##) NVIC configuration if you need to use interrupt process or DMA process
00029               (+++) Configure the SPIx interrupt priority
00030               (+++) Enable the NVIC SPI IRQ handle
00031           (##) DMA Configuration if you need to use DMA process
00032               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00033               (+++) Enable the DMAx clock
00034               (+++) Configure the DMA handle parameters
00035               (+++) Configure the DMA Tx or Rx Stream/Channel
00036               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00037               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00038
00039       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00040           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00041
00042       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00043           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00044               by calling the customized HAL_SPI_MspInit() API.
00045      [..]
00046        Callback registration:
00047
00048       (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
00049           allows the user to configure dynamically the driver callbacks.
00050           Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
00051
00052           Function HAL_SPI_RegisterCallback() allows to register following callbacks:
00053             (+) TxCpltCallback        : SPI Tx Completed callback
00054             (+) RxCpltCallback        : SPI Rx Completed callback
00055             (+) TxRxCpltCallback      : SPI TxRx Completed callback
00056             (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
00057             (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
00058             (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00059             (+) ErrorCallback         : SPI Error callback
00060             (+) AbortCpltCallback     : SPI Abort callback
00061             (+) MspInitCallback       : SPI Msp Init callback
00062             (+) MspDeInitCallback     : SPI Msp DeInit callback
00063           This function takes as parameters the HAL peripheral handle, the Callback ID
00064           and a pointer to the user callback function.
00065
00066
00067       (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
00068           weak function.
00069           HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00070           and the Callback ID.
00071           This function allows to reset following callbacks:
00072             (+) TxCpltCallback        : SPI Tx Completed callback
00073             (+) RxCpltCallback        : SPI Rx Completed callback
00074             (+) TxRxCpltCallback      : SPI TxRx Completed callback
00075             (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
00076             (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
00077             (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00078             (+) ErrorCallback         : SPI Error callback
00079             (+) AbortCpltCallback     : SPI Abort callback
00080             (+) MspInitCallback       : SPI Msp Init callback
00081             (+) MspDeInitCallback     : SPI Msp DeInit callback
00082
00083        By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
00084        all callbacks are set to the corresponding weak functions:
00085        examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
00086        Exception done for MspInit and MspDeInit functions that are
00087        reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
00088        these callbacks are null (not registered beforehand).
00089        If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
00090        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00091
00092        Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
00093        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00094        in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
00095        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00096        Then, the user first registers the MspInit/MspDeInit user callbacks
00097        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
00098        or HAL_SPI_Init() function.
00099
00100        When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
00101        not defined, the callback registering feature is not available
00102        and weak (surcharged) callbacks are used.
00103
00104
00105     [..]
00106       Circular mode restriction:
00107       (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
00108           (++) Master 2Lines RxOnly
00109           (++) Master 1Line Rx
00110       (+) The CRC feature is not managed when the DMA circular mode is enabled
00111       (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
00112           HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
00113           Those functions are maintained for backward compatibility reasons.
00114
00115   @endverbatim
00116   ******************************************************************************
00117   * @attention
00118   *
00119   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00120   * All rights reserved.</center></h2>
00121   *
00122   * This software component is licensed by ST under BSD 3-Clause license,
00123   * the "License"; You may not use this file except in compliance with the
00124   * License. You may obtain a copy of the License at:
00125   *                        opensource.org/licenses/BSD-3-Clause
00126   *
00127   ******************************************************************************
00128   */
00129
00130 /* Includes ------------------------------------------------------------------*/
00131 #include "stm32h7xx_hal.h"
00132
00133 /** @addtogroup STM32H7xx_HAL_Driver
00134   * @{
00135   */
00136
00137 /** @defgroup SPI SPI
00138   * @brief SPI HAL module driver
00139   * @{
00140   */
00141 #ifdef HAL_SPI_MODULE_ENABLED
00142
00143 /* Private typedef -----------------------------------------------------------*/
00144 /* Private defines -----------------------------------------------------------*/
00145 /** @defgroup SPI_Private_Constants SPI Private Constants
00146   * @{
00147   */
00148 #define SPI_DEFAULT_TIMEOUT 100UL
00149 /**
00150   * @}
00151   */
00152
00153 /* Private macros ------------------------------------------------------------*/
00154 /* Private variables ---------------------------------------------------------*/
00155 /* Private function prototypes -----------------------------------------------*/
00156 /** @defgroup SPI_Private_Functions SPI Private Functions
00157   * @{
00158   */
00159 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00160 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00161 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00162 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00163 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00164 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00165 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00166 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00167 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00168 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00169 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
00170                                                     uint32_t Timeout, uint32_t Tickstart);
00171 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
00172 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
00173 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
00174 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
00175 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
00176 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
00177 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
00178 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
00179 static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
00180
00181
00182 /**
00183   * @}
00184   */
00185
00186 /* Exported functions --------------------------------------------------------*/
00187 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00192  *  @brief    Initialization and Configuration functions
00193  *
00194 @verbatim
00195  ===============================================================================
00196               ##### Initialization and de-initialization functions #####
00197  ===============================================================================
00198     [..]  This subsection provides a set of functions allowing to initialize and
00199           de-initialize the SPIx peripheral:
00200
00201       (+) User must implement HAL_SPI_MspInit() function in which he configures
00202           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00203
00204       (+) Call the function HAL_SPI_Init() to configure the selected device with
00205           the selected configuration:
00206         (++) Mode
00207         (++) Direction
00208         (++) Data Size
00209         (++) Clock Polarity and Phase
00210         (++) NSS Management
00211         (++) BaudRate Prescaler
00212         (++) FirstBit
00213         (++) TIMode
00214         (++) CRC Calculation
00215         (++) CRC Polynomial if CRC enabled
00216         (++) CRC Length, used only with Data8 and Data16
00217         (++) FIFO reception threshold
00218         (++) FIFO transmission threshold
00219
00220       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00221           of the selected SPIx peripheral.
00222
00223 @endverbatim
00224   * @{
00225   */
00226
00227 /**
00228   * @brief  Initialize the SPI according to the specified parameters
00229   *         in the SPI_InitTypeDef and initialize the associated handle.
00230   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00231   *               the configuration information for SPI module.
00232   * @retval HAL status
00233   */
00234 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00235 {
00236   uint32_t crc_length = 0UL;
00237   uint32_t packet_length;
00238
00239   /* Check the SPI handle allocation */
00240   if (hspi == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   /* Check the parameters */
00246   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00247   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00248   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00249   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00250   assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
00251   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00252   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00253   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00254   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00255   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00256   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00257   {
00258     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00259     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00260   }
00261 #if (USE_SPI_CRC != 0UL)
00262   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00263   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00264   {
00265     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00266     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00267     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
00268     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
00269   }
00270 #else
00271   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00272 #endif /* USE_SPI_CRC */
00273
00274   /* Verify that the SPI instance supports Data Size higher than 16bits */
00275   if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
00276   {
00277     return HAL_ERROR;
00278   }
00279
00280   /* Verify that the SPI instance supports requested data packing */
00281   packet_length = SPI_GetPacketSize(hspi);
00282   if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
00283       ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
00284   {
00285     return HAL_ERROR;
00286   }
00287
00288 #if (USE_SPI_CRC != 0UL)
00289   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00290   {
00291     /* Verify that the SPI instance supports CRC Length higher than 16bits */
00292     if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
00293     {
00294       return HAL_ERROR;
00295     }
00296
00297     /* Align the CRC Length on the data size */
00298     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00299     {
00300       crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
00301     }
00302     else
00303     {
00304       crc_length = hspi->Init.CRCLength;
00305     }
00306
00307     /* Verify that the CRC Length is higher than DataSize */
00308     if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
00309     {
00310       return HAL_ERROR;
00311     }
00312   }
00313 #endif /* USE_SPI_CRC */
00314
00315   if (hspi->State == HAL_SPI_STATE_RESET)
00316   {
00317     /* Allocate lock resource and initialize it */
00318     hspi->Lock = HAL_UNLOCKED;
00319
00320 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00321     /* Init the SPI Callback settings */
00322     hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
00323     hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
00324     hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
00325     hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
00326     hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
00327     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00328     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
00329     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00330
00331     if (hspi->MspInitCallback == NULL)
00332     {
00333       hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
00334     }
00335
00336     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00337     hspi->MspInitCallback(hspi);
00338 #else
00339     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00340     HAL_SPI_MspInit(hspi);
00341 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00342   }
00343
00344   hspi->State = HAL_SPI_STATE_BUSY;
00345
00346   /* Disable the selected SPI peripheral */
00347   __HAL_SPI_DISABLE(hspi);
00348
00349   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00350   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00351   Communication speed, First bit, CRC calculation state, CRC Length */
00352
00353   if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
00354   {
00355     SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
00356   }
00357
00358   /* SPIx CFG1 Configuration */
00359   WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
00360                                    hspi->Init.FifoThreshold     | hspi->Init.DataSize));
00361
00362   /* SPIx CFG2 Configuration */
00363   WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode     | hspi->Init.TIMode           | hspi->Init.NSSPolarity             |
00364                                    hspi->Init.NSS          | hspi->Init.CLKPolarity      | hspi->Init.CLKPhase                |
00365                                    hspi->Init.FirstBit     | hspi->Init.Mode             | hspi->Init.MasterInterDataIdleness |
00366                                    hspi->Init.Direction    | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
00367
00368 #if (USE_SPI_CRC != 0UL)
00369   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00370   /* Configure : CRC Polynomial */
00371   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00372   {
00373     /* Initialize TXCRC Pattern Initial Value */
00374     if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
00375     {
00376       SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
00377     }
00378     else
00379     {
00380       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
00381     }
00382
00383     /* Initialize RXCRC Pattern Initial Value */
00384     if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
00385     {
00386       SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
00387     }
00388     else
00389     {
00390       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
00391     }
00392
00393     /* Enable 33/17 bits CRC computation */
00394     if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
00395         ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance))  && (crc_length == SPI_CRC_LENGTH_32BIT)))
00396     {
00397       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
00398     }
00399     else
00400     {
00401       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
00402     }
00403
00404     /* Write CRC polynomial in SPI Register */
00405     WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
00406   }
00407 #endif /* USE_SPI_CRC */
00408
00409   /* Insure that Underrun configuration is managed only by Salve */
00410   if (hspi->Init.Mode == SPI_MODE_SLAVE)
00411   {
00412     /* Set Default Underrun configuration */
00413 #if (USE_SPI_CRC != 0UL)
00414     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
00415 #endif
00416     {
00417       MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
00418     }
00419     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
00420   }
00421
00422 #if defined(SPI_I2SCFGR_I2SMOD)
00423   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00424   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00425 #endif /* SPI_I2SCFGR_I2SMOD */
00426
00427   /* Insure that AFCNTR is managed only by Master */
00428   if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
00429   {
00430     /* Alternate function GPIOs control */
00431     MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
00432   }
00433
00434   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00435   hspi->State     = HAL_SPI_STATE_READY;
00436
00437   return HAL_OK;
00438 }
00439
00440 /**
00441   * @brief  De-Initialize the SPI peripheral.
00442   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00443   *               the configuration information for SPI module.
00444   * @retval HAL status
00445   */
00446 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00447 {
00448   /* Check the SPI handle allocation */
00449   if (hspi == NULL)
00450   {
00451     return HAL_ERROR;
00452   }
00453
00454   /* Check SPI Instance parameter */
00455   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00456
00457   hspi->State = HAL_SPI_STATE_BUSY;
00458
00459   /* Disable the SPI Peripheral Clock */
00460   __HAL_SPI_DISABLE(hspi);
00461
00462 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00463   if (hspi->MspDeInitCallback == NULL)
00464   {
00465     hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
00466   }
00467
00468   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00469   hspi->MspDeInitCallback(hspi);
00470 #else
00471   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00472   HAL_SPI_MspDeInit(hspi);
00473 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00474
00475   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00476   hspi->State = HAL_SPI_STATE_RESET;
00477
00478   /* Release Lock */
00479   __HAL_UNLOCK(hspi);
00480
00481   return HAL_OK;
00482 }
00483
00484 /**
00485   * @brief  Initialize the SPI MSP.
00486   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00487   *               the configuration information for SPI module.
00488   * @retval None
00489   */
00490 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00491 {
00492   /* Prevent unused argument(s) compilation warning */
00493   UNUSED(hspi);
00494
00495   /* NOTE : This function should not be modified, when the callback is needed,
00496             the HAL_SPI_MspInit should be implemented in the user file
00497    */
00498 }
00499
00500 /**
00501   * @brief  De-Initialize the SPI MSP.
00502   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00503   *               the configuration information for SPI module.
00504   * @retval None
00505   */
00506 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00507 {
00508   /* Prevent unused argument(s) compilation warning */
00509   UNUSED(hspi);
00510
00511   /* NOTE : This function should not be modified, when the callback is needed,
00512             the HAL_SPI_MspDeInit should be implemented in the user file
00513    */
00514 }
00515
00516 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00517 /**
00518   * @brief  Register a User SPI Callback
00519   *         To be used instead of the weak predefined callback
00520   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00521   *                the configuration information for the specified SPI.
00522   * @param  CallbackID ID of the callback to be registered
00523   * @param  pCallback pointer to the Callback function
00524   * @retval HAL status
00525   */
00526 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
00527 {
00528   HAL_StatusTypeDef status = HAL_OK;
00529
00530   if (pCallback == NULL)
00531   {
00532     /* Update the error code */
00533     hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
00534
00535     return HAL_ERROR;
00536   }
00537   /* Process locked */
00538   __HAL_LOCK(hspi);
00539
00540   if (HAL_SPI_STATE_READY == hspi->State)
00541   {
00542     switch (CallbackID)
00543     {
00544       case HAL_SPI_TX_COMPLETE_CB_ID :
00545         hspi->TxCpltCallback = pCallback;
00546         break;
00547
00548       case HAL_SPI_RX_COMPLETE_CB_ID :
00549         hspi->RxCpltCallback = pCallback;
00550         break;
00551
00552       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00553         hspi->TxRxCpltCallback = pCallback;
00554         break;
00555
00556       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00557         hspi->TxHalfCpltCallback = pCallback;
00558         break;
00559
00560       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00561         hspi->RxHalfCpltCallback = pCallback;
00562         break;
00563
00564       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00565         hspi->TxRxHalfCpltCallback = pCallback;
00566         break;
00567
00568       case HAL_SPI_ERROR_CB_ID :
00569         hspi->ErrorCallback = pCallback;
00570         break;
00571
00572       case HAL_SPI_ABORT_CB_ID :
00573         hspi->AbortCpltCallback = pCallback;
00574         break;
00575
00576       case HAL_SPI_MSPINIT_CB_ID :
00577         hspi->MspInitCallback = pCallback;
00578         break;
00579
00580       case HAL_SPI_MSPDEINIT_CB_ID :
00581         hspi->MspDeInitCallback = pCallback;
00582         break;
00583
00584       default :
00585         /* Update the error code */
00586         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00587
00588         /* Return error status */
00589         status =  HAL_ERROR;
00590         break;
00591     }
00592   }
00593   else if (HAL_SPI_STATE_RESET == hspi->State)
00594   {
00595     switch (CallbackID)
00596     {
00597       case HAL_SPI_MSPINIT_CB_ID :
00598         hspi->MspInitCallback = pCallback;
00599         break;
00600
00601       case HAL_SPI_MSPDEINIT_CB_ID :
00602         hspi->MspDeInitCallback = pCallback;
00603         break;
00604
00605       default :
00606         /* Update the error code */
00607         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00608
00609         /* Return error status */
00610         status =  HAL_ERROR;
00611         break;
00612     }
00613   }
00614   else
00615   {
00616     /* Update the error code */
00617     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00618
00619     /* Return error status */
00620     status =  HAL_ERROR;
00621   }
00622
00623   /* Release Lock */
00624   __HAL_UNLOCK(hspi);
00625   return status;
00626 }
00627
00628 /**
00629   * @brief  Unregister an SPI Callback
00630   *         SPI callback is redirected to the weak predefined callback
00631   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00632   *                the configuration information for the specified SPI.
00633   * @param  CallbackID ID of the callback to be unregistered
00634   * @retval HAL status
00635   */
00636 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
00637 {
00638   HAL_StatusTypeDef status = HAL_OK;
00639
00640   /* Process locked */
00641   __HAL_LOCK(hspi);
00642
00643   if (HAL_SPI_STATE_READY == hspi->State)
00644   {
00645     switch (CallbackID)
00646     {
00647       case HAL_SPI_TX_COMPLETE_CB_ID :
00648         hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
00649         break;
00650
00651       case HAL_SPI_RX_COMPLETE_CB_ID :
00652         hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
00653         break;
00654
00655       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00656         hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
00657         break;
00658
00659       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00660         hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
00661         break;
00662
00663       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00664         hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
00665         break;
00666
00667       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00668         hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00669         break;
00670
00671       case HAL_SPI_ERROR_CB_ID :
00672         hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
00673         break;
00674
00675       case HAL_SPI_ABORT_CB_ID :
00676         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00677         break;
00678
00679       case HAL_SPI_MSPINIT_CB_ID :
00680         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00681         break;
00682
00683       case HAL_SPI_MSPDEINIT_CB_ID :
00684         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00685         break;
00686
00687       default :
00688         /* Update the error code */
00689         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00690
00691         /* Return error status */
00692         status =  HAL_ERROR;
00693         break;
00694     }
00695   }
00696   else if (HAL_SPI_STATE_RESET == hspi->State)
00697   {
00698     switch (CallbackID)
00699     {
00700       case HAL_SPI_MSPINIT_CB_ID :
00701         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00702         break;
00703
00704       case HAL_SPI_MSPDEINIT_CB_ID :
00705         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00706         break;
00707
00708       default :
00709         /* Update the error code */
00710         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00711
00712         /* Return error status */
00713         status =  HAL_ERROR;
00714         break;
00715     }
00716   }
00717   else
00718   {
00719     /* Update the error code */
00720     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00721
00722     /* Return error status */
00723     status =  HAL_ERROR;
00724   }
00725
00726   /* Release Lock */
00727   __HAL_UNLOCK(hspi);
00728   return status;
00729 }
00730 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00736  *  @brief   Data transfers functions
00737  *
00738 @verbatim
00739   ==============================================================================
00740                       ##### IO operation functions #####
00741  ===============================================================================
00742  [..]
00743     This subsection provides a set of functions allowing to manage the SPI
00744     data transfers.
00745
00746     [..] The SPI supports master and slave mode :
00747
00748     (#) There are two modes of transfer:
00749        (##) Blocking mode: The communication is performed in polling mode.
00750             The HAL status of all data processing is returned by the same function
00751             after finishing transfer.
00752        (##) No-Blocking mode: The communication is performed using Interrupts
00753             or DMA, These APIs return the HAL status.
00754             The end of the data processing will be indicated through the
00755             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00756             using DMA mode.
00757             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00758             will be executed respectively at the end of the transmit or Receive process
00759             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00760
00761     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00762         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00763
00764 @endverbatim
00765   * @{
00766   */
00767
00768 /**
00769   * @brief  Transmit an amount of data in blocking mode.
00770   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
00771   *                  the configuration information for SPI module.
00772   * @param  pData  : pointer to data buffer
00773   * @param  Size   : amount of data to be sent
00774   * @param  Timeout: Timeout duration
00775   * @retval HAL status
00776   */
00777 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00778 {
00779   uint32_t tickstart;
00780   HAL_StatusTypeDef errorcode = HAL_OK;
00781
00782   /* Check Direction parameter */
00783   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
00784
00785   /* Process Locked */
00786   __HAL_LOCK(hspi);
00787
00788   /* Init tickstart for timeout management*/
00789   tickstart = HAL_GetTick();
00790
00791   if (hspi->State != HAL_SPI_STATE_READY)
00792   {
00793     errorcode = HAL_BUSY;
00794     __HAL_UNLOCK(hspi);
00795     return errorcode;
00796   }
00797
00798   if ((pData == NULL) || (Size == 0UL))
00799   {
00800     errorcode = HAL_ERROR;
00801     __HAL_UNLOCK(hspi);
00802     return errorcode;
00803   }
00804
00805   /* Set the transaction information */
00806   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00807   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00808   hspi->pTxBuffPtr  = (uint8_t *)pData;
00809   hspi->TxXferSize  = Size;
00810   hspi->TxXferCount = Size;
00811
00812   /*Init field not used in handle to zero */
00813   hspi->pRxBuffPtr  = NULL;
00814   hspi->RxXferSize  = (uint16_t) 0UL;
00815   hspi->RxXferCount = (uint16_t) 0UL;
00816   hspi->TxISR       = NULL;
00817   hspi->RxISR       = NULL;
00818
00819   /* Configure communication direction : 1Line */
00820   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00821   {
00822     SPI_1LINE_TX(hspi);
00823   }
00824
00825   /* Set the number of data at current transfer */
00826   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
00827
00828   /* Enable SPI peripheral */
00829   __HAL_SPI_ENABLE(hspi);
00830
00831   if (hspi->Init.Mode == SPI_MODE_MASTER)
00832   {
00833     /* Master transfer start */
00834     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
00835   }
00836
00837   /* Transmit data in 32 Bit mode */
00838   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
00839   {
00840     /* Transmit data in 32 Bit mode */
00841     while (hspi->TxXferCount > 0UL)
00842     {
00843       /* Wait until TXP flag is set to send data */
00844       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
00845       {
00846         *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00847         hspi->pTxBuffPtr += sizeof(uint32_t);
00848         hspi->TxXferCount--;
00849       }
00850       else
00851       {
00852         /* Timeout management */
00853         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00854         {
00855           /* Call standard close procedure with error check */
00856           SPI_CloseTransfer(hspi);
00857
00858           /* Process Unlocked */
00859           __HAL_UNLOCK(hspi);
00860
00861           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00862           hspi->State = HAL_SPI_STATE_READY;
00863           return HAL_ERROR;
00864         }
00865       }
00866     }
00867   }
00868   /* Transmit data in 16 Bit mode */
00869   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00870   {
00871     /* Transmit data in 16 Bit mode */
00872     while (hspi->TxXferCount > 0UL)
00873     {
00874       /* Wait until TXP flag is set to send data */
00875       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
00876       {
00877         if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00878         {
00879           *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00880           hspi->pTxBuffPtr += sizeof(uint32_t);
00881           hspi->TxXferCount -= (uint16_t)2UL;
00882         }
00883         else
00884         {
00885           *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
00886           hspi->pTxBuffPtr += sizeof(uint16_t);
00887           hspi->TxXferCount--;
00888         }
00889       }
00890       else
00891       {
00892         /* Timeout management */
00893         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00894         {
00895           /* Call standard close procedure with error check */
00896           SPI_CloseTransfer(hspi);
00897
00898           /* Process Unlocked */
00899           __HAL_UNLOCK(hspi);
00900
00901           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00902           hspi->State = HAL_SPI_STATE_READY;
00903           return HAL_ERROR;
00904         }
00905       }
00906     }
00907   }
00908   /* Transmit data in 8 Bit mode */
00909   else
00910   {
00911     while (hspi->TxXferCount > 0UL)
00912     {
00913       /* Wait until TXP flag is set to send data */
00914       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
00915       {
00916         if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
00917         {
00918           *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00919           hspi->pTxBuffPtr += sizeof(uint32_t);
00920           hspi->TxXferCount -= (uint16_t)4UL;
00921         }
00922         else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00923         {
00924           *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
00925           hspi->pTxBuffPtr += sizeof(uint16_t);
00926           hspi->TxXferCount -= (uint16_t)2UL;
00927         }
00928         else
00929         {
00930           *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
00931           hspi->pTxBuffPtr += sizeof(uint8_t);
00932           hspi->TxXferCount--;
00933         }
00934       }
00935       else
00936       {
00937         /* Timeout management */
00938         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00939         {
00940           /* Call standard close procedure with error check */
00941           SPI_CloseTransfer(hspi);
00942
00943           /* Process Unlocked */
00944           __HAL_UNLOCK(hspi);
00945
00946           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00947           hspi->State = HAL_SPI_STATE_READY;
00948           return HAL_ERROR;
00949         }
00950       }
00951     }
00952   }
00953
00954   /* Wait for Tx (and CRC) data to be sent */
00955   if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
00956   {
00957     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
00958   }
00959
00960   /* Call standard close procedure with error check */
00961   SPI_CloseTransfer(hspi);
00962
00963   /* Process Unlocked */
00964   __HAL_UNLOCK(hspi);
00965
00966   hspi->State = HAL_SPI_STATE_READY;
00967
00968   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00969   {
00970     return HAL_ERROR;
00971   }
00972   return errorcode;
00973 }
00974
00975 /**
00976   * @brief  Receive an amount of data in blocking mode.
00977   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
00978   *                  the configuration information for SPI module.
00979   * @param  pData  : pointer to data buffer
00980   * @param  Size   : amount of data to be received
00981   * @param  Timeout: Timeout duration
00982   * @retval HAL status
00983   */
00984 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00985 {
00986   uint32_t tickstart;
00987   HAL_StatusTypeDef errorcode = HAL_OK;
00988
00989   /* Check Direction parameter */
00990   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
00991
00992   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00993   {
00994     hspi->State = HAL_SPI_STATE_BUSY_RX;
00995     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00996     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
00997   }
00998
00999   /* Process Locked */
01000   __HAL_LOCK(hspi);
01001
01002   /* Init tickstart for timeout management*/
01003   tickstart = HAL_GetTick();
01004
01005   if (hspi->State != HAL_SPI_STATE_READY)
01006   {
01007     errorcode = HAL_BUSY;
01008     __HAL_UNLOCK(hspi);
01009     return errorcode;
01010   }
01011
01012   if ((pData == NULL) || (Size == 0UL))
01013   {
01014     errorcode = HAL_ERROR;
01015     __HAL_UNLOCK(hspi);
01016     return errorcode;
01017   }
01018
01019   /* Set the transaction information */
01020   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01021   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01022   hspi->pRxBuffPtr  = (uint8_t *)pData;
01023   hspi->RxXferSize  = Size;
01024   hspi->RxXferCount = Size;
01025
01026   /*Init field not used in handle to zero */
01027   hspi->pTxBuffPtr  = NULL;
01028   hspi->TxXferSize  = (uint16_t) 0UL;
01029   hspi->TxXferCount = (uint16_t) 0UL;
01030   hspi->RxISR       = NULL;
01031   hspi->TxISR       = NULL;
01032
01033   /* Configure communication direction: 1Line */
01034   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01035   {
01036     SPI_1LINE_RX(hspi);
01037   }
01038
01039   /* Set the number of data at current transfer */
01040   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01041
01042   /* Enable SPI peripheral */
01043   __HAL_SPI_ENABLE(hspi);
01044
01045   if (hspi->Init.Mode == SPI_MODE_MASTER)
01046   {
01047     /* Master transfer start */
01048     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01049   }
01050
01051   /* Receive data in 32 Bit mode */
01052   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01053   {
01054     /* Transfer loop */
01055     while (hspi->RxXferCount > 0UL)
01056     {
01057       /* Check the RXWNE/EOT flag */
01058       if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
01059       {
01060         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01061         hspi->pRxBuffPtr += sizeof(uint32_t);
01062         hspi->RxXferCount--;
01063       }
01064       else
01065       {
01066         /* Timeout management */
01067         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01068         {
01069           /* Call standard close procedure with error check */
01070           SPI_CloseTransfer(hspi);
01071
01072           /* Process Unlocked */
01073           __HAL_UNLOCK(hspi);
01074
01075           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01076           hspi->State = HAL_SPI_STATE_READY;
01077           return HAL_ERROR;
01078         }
01079       }
01080     }
01081   }
01082   /* Receive data in 16 Bit mode */
01083   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01084   {
01085     /* Transfer loop */
01086     while (hspi->RxXferCount > 0UL)
01087     {
01088       /* Check the RXWNE/FRLVL flag */
01089       if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
01090       {
01091         if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
01092         {
01093           *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01094           hspi->pRxBuffPtr += sizeof(uint32_t);
01095           hspi->RxXferCount -= (uint16_t)2UL;
01096         }
01097         else
01098         {
01099           *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01100           hspi->pRxBuffPtr += sizeof(uint16_t);
01101           hspi->RxXferCount--;
01102         }
01103       }
01104       else
01105       {
01106         /* Timeout management */
01107         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01108         {
01109           /* Call standard close procedure with error check */
01110           SPI_CloseTransfer(hspi);
01111
01112           /* Process Unlocked */
01113           __HAL_UNLOCK(hspi);
01114
01115           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01116           hspi->State = HAL_SPI_STATE_READY;
01117           return HAL_ERROR;
01118         }
01119       }
01120     }
01121   }
01122   /* Receive data in 8 Bit mode */
01123   else
01124   {
01125     /* Transfer loop */
01126     while (hspi->RxXferCount > 0UL)
01127     {
01128       /* Check the RXWNE/FRLVL flag */
01129       if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
01130       {
01131         if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
01132         {
01133           *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01134           hspi->pRxBuffPtr += sizeof(uint32_t);
01135           hspi->RxXferCount -= (uint16_t)4UL;
01136         }
01137         else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
01138         {
01139           *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01140           hspi->pRxBuffPtr += sizeof(uint16_t);
01141           hspi->RxXferCount -= (uint16_t)2UL;
01142         }
01143         else
01144         {
01145           *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
01146           hspi->pRxBuffPtr += sizeof(uint8_t);
01147           hspi->RxXferCount--;
01148         }
01149       }
01150       else
01151       {
01152         /* Timeout management */
01153         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01154         {
01155           /* Call standard close procedure with error check */
01156           SPI_CloseTransfer(hspi);
01157
01158           /* Process Unlocked */
01159           __HAL_UNLOCK(hspi);
01160
01161           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01162           hspi->State = HAL_SPI_STATE_READY;
01163           return HAL_ERROR;
01164         }
01165       }
01166     }
01167   }
01168
01169 #if (USE_SPI_CRC != 0UL)
01170   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01171   {
01172     /* Wait for crc data to be received */
01173     if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
01174     {
01175       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01176     }
01177   }
01178 #endif /* USE_SPI_CRC */
01179
01180   /* Call standard close procedure with error check */
01181   SPI_CloseTransfer(hspi);
01182
01183   /* Process Unlocked */
01184   __HAL_UNLOCK(hspi);
01185
01186   hspi->State = HAL_SPI_STATE_READY;
01187
01188   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01189   {
01190     return HAL_ERROR;
01191   }
01192   return errorcode;
01193 }
01194
01195 /**
01196   * @brief  Transmit and Receive an amount of data in blocking mode.
01197   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
01198   *                  the configuration information for SPI module.
01199   * @param  pTxData: pointer to transmission data buffer
01200   * @param  pRxData: pointer to reception data buffer
01201   * @param  Size   : amount of data to be sent and received
01202   * @param  Timeout: Timeout duration
01203   * @retval HAL status
01204   */
01205 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
01206                                           uint32_t Timeout)
01207 {
01208   HAL_SPI_StateTypeDef tmp_state;
01209   HAL_StatusTypeDef errorcode = HAL_OK;
01210
01211   uint32_t   tickstart;
01212   uint32_t   tmp_mode;
01213   uint16_t   initial_TxXferCount;
01214   uint16_t   initial_RxXferCount;
01215
01216   /* Check Direction parameter */
01217   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01218
01219   /* Process Locked */
01220   __HAL_LOCK(hspi);
01221
01222   /* Init tickstart for timeout management*/
01223   tickstart = HAL_GetTick();
01224
01225   initial_TxXferCount = Size;
01226   initial_RxXferCount = Size;
01227   tmp_state           = hspi->State;
01228   tmp_mode            = hspi->Init.Mode;
01229
01230   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01231         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01232   {
01233     errorcode = HAL_BUSY;
01234     __HAL_UNLOCK(hspi);
01235     return errorcode;
01236   }
01237
01238   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
01239   {
01240     errorcode = HAL_ERROR;
01241     __HAL_UNLOCK(hspi);
01242     return errorcode;
01243   }
01244
01245   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01246   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01247   {
01248     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01249   }
01250
01251   /* Set the transaction information */
01252   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01253   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01254   hspi->RxXferCount = Size;
01255   hspi->RxXferSize  = Size;
01256   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01257   hspi->TxXferCount = Size;
01258   hspi->TxXferSize  = Size;
01259
01260   /*Init field not used in handle to zero */
01261   hspi->RxISR       = NULL;
01262   hspi->TxISR       = NULL;
01263
01264   /* Set the number of data at current transfer */
01265   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01266
01267   __HAL_SPI_ENABLE(hspi);
01268
01269   if (hspi->Init.Mode == SPI_MODE_MASTER)
01270   {
01271     /* Master transfer start */
01272     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01273   }
01274
01275   /* Transmit and Receive data in 32 Bit mode */
01276   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01277   {
01278     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
01279     {
01280       /* Check TXP flag */
01281       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
01282       {
01283         *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01284         hspi->pTxBuffPtr += sizeof(uint32_t);
01285         hspi->TxXferCount --;
01286         initial_TxXferCount = hspi->TxXferCount;
01287       }
01288
01289       /* Check RXWNE/EOT flag */
01290       if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
01291       {
01292         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01293         hspi->pRxBuffPtr += sizeof(uint32_t);
01294         hspi->RxXferCount --;
01295         initial_RxXferCount = hspi->RxXferCount;
01296       }
01297     }
01298
01299     /* Timeout management */
01300     if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01301     {
01302       /* Call standard close procedure with error check */
01303       SPI_CloseTransfer(hspi);
01304
01305       /* Process Unlocked */
01306       __HAL_UNLOCK(hspi);
01307
01308       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01309       hspi->State = HAL_SPI_STATE_READY;
01310       return HAL_ERROR;
01311     }
01312   }
01313   /* Transmit and Receive data in 16 Bit mode */
01314   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01315   {
01316     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
01317     {
01318       /* Check TXP flag */
01319       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
01320       {
01321         if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
01322         {
01323           *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01324           hspi->pTxBuffPtr += sizeof(uint32_t);
01325           hspi->TxXferCount -= (uint16_t)2UL;
01326           initial_TxXferCount = hspi->TxXferCount;
01327         }
01328         else
01329         {
01330           *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
01331           hspi->pTxBuffPtr += sizeof(uint16_t);
01332           hspi->TxXferCount--;
01333           initial_TxXferCount = hspi->TxXferCount;
01334         }
01335       }
01336
01337       /* Check RXWNE/FRLVL flag */
01338       if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
01339       {
01340         if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
01341         {
01342           *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01343           hspi->pRxBuffPtr += sizeof(uint32_t);
01344           hspi->RxXferCount -= (uint16_t)2UL;
01345           initial_RxXferCount = hspi->RxXferCount;
01346         }
01347         else
01348         {
01349           *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01350           hspi->pRxBuffPtr += sizeof(uint16_t);
01351           hspi->RxXferCount--;
01352           initial_RxXferCount = hspi->RxXferCount;
01353         }
01354       }
01355
01356       /* Timeout management */
01357       if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01358       {
01359         /* Call standard close procedure with error check */
01360         SPI_CloseTransfer(hspi);
01361
01362         /* Process Unlocked */
01363         __HAL_UNLOCK(hspi);
01364
01365         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01366         hspi->State = HAL_SPI_STATE_READY;
01367         return HAL_ERROR;
01368       }
01369     }
01370   }
01371   /* Transmit and Receive data in 8 Bit mode */
01372   else
01373   {
01374     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
01375     {
01376       /* check TXP flag */
01377       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
01378       {
01379         if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
01380         {
01381           *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01382           hspi->pTxBuffPtr += sizeof(uint32_t);
01383           hspi->TxXferCount -= (uint16_t)4UL;
01384           initial_TxXferCount = hspi->TxXferCount;
01385         }
01386         else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
01387         {
01388           *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
01389           hspi->pTxBuffPtr += sizeof(uint16_t);
01390           hspi->TxXferCount -= (uint16_t)2UL;
01391           initial_TxXferCount = hspi->TxXferCount;
01392         }
01393         else
01394         {
01395           *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
01396           hspi->pTxBuffPtr += sizeof(uint8_t);
01397           hspi->TxXferCount--;
01398           initial_TxXferCount = hspi->TxXferCount;
01399         }
01400       }
01401
01402       /* Wait until RXWNE/FRLVL flag is reset */
01403       if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
01404       {
01405         if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
01406         {
01407           *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01408           hspi->pRxBuffPtr += sizeof(uint32_t);
01409           hspi->RxXferCount -= (uint16_t)4UL;
01410           initial_RxXferCount = hspi->RxXferCount;
01411         }
01412         else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
01413         {
01414           *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01415           hspi->pRxBuffPtr += sizeof(uint16_t);
01416           hspi->RxXferCount -= (uint16_t)2UL;
01417           initial_RxXferCount = hspi->RxXferCount;
01418         }
01419         else
01420         {
01421           *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
01422           hspi->pRxBuffPtr += sizeof(uint8_t);
01423           hspi->RxXferCount--;
01424           initial_RxXferCount = hspi->RxXferCount;
01425         }
01426       }
01427
01428       /* Timeout management */
01429       if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01430       {
01431         /* Call standard close procedure with error check */
01432         SPI_CloseTransfer(hspi);
01433
01434         /* Process Unlocked */
01435         __HAL_UNLOCK(hspi);
01436
01437         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01438         hspi->State = HAL_SPI_STATE_READY;
01439         return HAL_ERROR;
01440       }
01441     }
01442   }
01443
01444   /* Wait for Tx/Rx (and CRC) data to be sent/received */
01445   if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
01446   {
01447     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01448   }
01449
01450   /* Call standard close procedure with error check */
01451   SPI_CloseTransfer(hspi);
01452
01453   /* Process Unlocked */
01454   __HAL_UNLOCK(hspi);
01455
01456   hspi->State = HAL_SPI_STATE_READY;
01457
01458   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01459   {
01460     return HAL_ERROR;
01461   }
01462   return errorcode;
01463 }
01464
01465 /**
01466   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01467   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
01468   *                the configuration information for SPI module.
01469   * @param  pData: pointer to data buffer
01470   * @param  Size : amount of data to be sent
01471   * @retval HAL status
01472   */
01473 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01474 {
01475   HAL_StatusTypeDef errorcode = HAL_OK;
01476
01477   /* Check Direction parameter */
01478   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
01479
01480   /* Process Locked */
01481   __HAL_LOCK(hspi);
01482
01483   if ((pData == NULL) || (Size == 0UL))
01484   {
01485     errorcode = HAL_ERROR;
01486     __HAL_UNLOCK(hspi);
01487     return errorcode;
01488   }
01489
01490   if (hspi->State != HAL_SPI_STATE_READY)
01491   {
01492     errorcode = HAL_BUSY;
01493     __HAL_UNLOCK(hspi);
01494     return errorcode;
01495   }
01496
01497   /* Set the transaction information */
01498   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01499   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01500   hspi->pTxBuffPtr  = (uint8_t *)pData;
01501   hspi->TxXferSize  = Size;
01502   hspi->TxXferCount = Size;
01503
01504   /* Init field not used in handle to zero */
01505   hspi->pRxBuffPtr  = NULL;
01506   hspi->RxXferSize  = (uint16_t) 0UL;
01507   hspi->RxXferCount = (uint16_t) 0UL;
01508   hspi->RxISR       = NULL;
01509
01510   /* Set the function for IT treatment */
01511   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01512   {
01513     hspi->TxISR = SPI_TxISR_32BIT;
01514   }
01515   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01516   {
01517     hspi->TxISR = SPI_TxISR_16BIT;
01518   }
01519   else
01520   {
01521     hspi->TxISR = SPI_TxISR_8BIT;
01522   }
01523
01524   /* Configure communication direction : 1Line */
01525   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01526   {
01527     SPI_1LINE_TX(hspi);
01528   }
01529
01530   /* Set the number of data at current transfer */
01531   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01532
01533   /* Enable SPI peripheral */
01534   __HAL_SPI_ENABLE(hspi);
01535
01536   /* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */
01537   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
01538
01539   if (hspi->Init.Mode == SPI_MODE_MASTER)
01540   {
01541     /* Master transfer start */
01542     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01543   }
01544
01545   __HAL_UNLOCK(hspi);
01546   return errorcode;
01547 }
01548
01549 /**
01550   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01551   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
01552   *                the configuration information for SPI module.
01553   * @param  pData: pointer to data buffer
01554   * @param  Size : amount of data to be sent
01555   * @retval HAL status
01556   */
01557 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01558 {
01559   HAL_StatusTypeDef errorcode = HAL_OK;
01560
01561   /* Check Direction parameter */
01562   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
01563
01564   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01565   {
01566     hspi->State = HAL_SPI_STATE_BUSY_RX;
01567     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01568     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01569   }
01570
01571   /* Process Locked */
01572   __HAL_LOCK(hspi);
01573
01574   if (hspi->State != HAL_SPI_STATE_READY)
01575   {
01576     errorcode = HAL_BUSY;
01577     __HAL_UNLOCK(hspi);
01578     return errorcode;
01579   }
01580
01581   if ((pData == NULL) || (Size == 0UL))
01582   {
01583     errorcode = HAL_ERROR;
01584     __HAL_UNLOCK(hspi);
01585     return errorcode;
01586   }
01587
01588   /* Set the transaction information */
01589   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01590   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01591   hspi->pRxBuffPtr  = (uint8_t *)pData;
01592   hspi->RxXferSize  = Size;
01593   hspi->RxXferCount = Size;
01594
01595   /* Init field not used in handle to zero */
01596   hspi->pTxBuffPtr  = NULL;
01597   hspi->TxXferSize  = (uint16_t) 0UL;
01598   hspi->TxXferCount = (uint16_t) 0UL;
01599   hspi->TxISR       = NULL;
01600
01601   /* Set the function for IT treatment */
01602   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01603   {
01604     hspi->RxISR = SPI_RxISR_32BIT;
01605   }
01606   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01607   {
01608     hspi->RxISR = SPI_RxISR_16BIT;
01609   }
01610   else
01611   {
01612     hspi->RxISR = SPI_RxISR_8BIT;
01613   }
01614
01615   /* Configure communication direction : 1Line */
01616   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01617   {
01618     SPI_1LINE_RX(hspi);
01619   }
01620
01621   /* Note : The SPI must be enabled after unlocking current process
01622             to avoid the risk of SPI interrupt handle execution before current
01623             process unlock */
01624
01625   /* Set the number of data at current transfer */
01626   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01627
01628   /* Enable SPI peripheral */
01629   __HAL_SPI_ENABLE(hspi);
01630
01631   /* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */
01632   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
01633
01634   if (hspi->Init.Mode == SPI_MODE_MASTER)
01635   {
01636     /* Master transfer start */
01637     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01638   }
01639
01640   /* Process Unlocked */
01641   __HAL_UNLOCK(hspi);
01642   return errorcode;
01643 }
01644
01645 /**
01646   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01647   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
01648   *                  the configuration information for SPI module.
01649   * @param  pTxData: pointer to transmission data buffer
01650   * @param  pRxData: pointer to reception data buffer
01651   * @param  Size   : amount of data to be sent and received
01652   * @retval HAL status
01653   */
01654 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01655 {
01656   HAL_SPI_StateTypeDef  tmp_state;
01657   HAL_StatusTypeDef errorcode = HAL_OK;
01658
01659   uint32_t  tmp_mode;
01660
01661   /* Check Direction parameter */
01662   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01663
01664   /* Process locked */
01665   __HAL_LOCK(hspi);
01666
01667   /* Init temporary variables */
01668   tmp_state  = hspi->State;
01669   tmp_mode   = hspi->Init.Mode;
01670
01671   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01672         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01673   {
01674     errorcode = HAL_BUSY;
01675     __HAL_UNLOCK(hspi);
01676     return errorcode;
01677   }
01678
01679   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
01680   {
01681     errorcode = HAL_ERROR;
01682     __HAL_UNLOCK(hspi);
01683     return errorcode;
01684   }
01685
01686   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01687   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01688   {
01689     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01690   }
01691
01692   /* Set the transaction information */
01693   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01694   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01695   hspi->TxXferSize  = Size;
01696   hspi->TxXferCount = Size;
01697   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01698   hspi->RxXferSize  = Size;
01699   hspi->RxXferCount = Size;
01700
01701   /* Set the function for IT treatment */
01702   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01703   {
01704     hspi->TxISR     = SPI_TxISR_32BIT;
01705     hspi->RxISR     = SPI_RxISR_32BIT;
01706   }
01707   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01708   {
01709     hspi->RxISR     = SPI_RxISR_16BIT;
01710     hspi->TxISR     = SPI_TxISR_16BIT;
01711   }
01712   else
01713   {
01714     hspi->RxISR     = SPI_RxISR_8BIT;
01715     hspi->TxISR     = SPI_TxISR_8BIT;
01716   }
01717
01718   /* Set the number of data at current transfer */
01719   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01720
01721   /* Enable SPI peripheral */
01722   __HAL_SPI_ENABLE(hspi);
01723
01724   /* Enable EOT, RXP, TXP, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
01725   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
01726
01727   if (hspi->Init.Mode == SPI_MODE_MASTER)
01728   {
01729     /* Master transfer start */
01730     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01731   }
01732
01733   /* Process Unlocked */
01734   __HAL_UNLOCK(hspi);
01735   return errorcode;
01736 }
01737
01738 #if defined(USE_SPI_RELOAD_TRANSFER)
01739 /**
01740   * @brief  Transmit an additional amount of data in blocking mode.
01741   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
01742   *                the configuration information for SPI module.
01743   * @param  pData: pointer to data buffer
01744   * @param  Size : amount of data to be sent
01745   * @retval HAL status
01746   */
01747 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01748 {
01749   HAL_StatusTypeDef errorcode = HAL_OK;
01750   HAL_SPI_StateTypeDef  tmp_state;
01751
01752   /* Lock the process */
01753   __HAL_LOCK(hspi);
01754
01755   if ((pData == NULL) || (Size == 0UL))
01756   {
01757     errorcode = HAL_ERROR;
01758     __HAL_UNLOCK(hspi);
01759     return errorcode;
01760   }
01761
01762   if (hspi->State == HAL_SPI_STATE_BUSY_TX)
01763   {
01764     /* check if there is already a request to reload */
01765     if (hspi->Reload.Requested == 1UL)
01766     {
01767       errorcode = HAL_ERROR;
01768       __HAL_UNLOCK(hspi);
01769       return errorcode;
01770     }
01771
01772     /* Insert the new number of data to be sent just after the current one */
01773     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
01774
01775     /* Set the transaction information */
01776     hspi->Reload.Requested   = 1UL;
01777     hspi->Reload.pTxBuffPtr  = (uint8_t *)pData;
01778     hspi->Reload.TxXferSize  = Size;
01779
01780     tmp_state = hspi->State;
01781
01782     /* Check if the current transmit is already completed */
01783     if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
01784     {
01785       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
01786       MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
01787       hspi->Reload.Requested = 0UL;
01788       errorcode = HAL_ERROR;
01789       __HAL_UNLOCK(hspi);
01790       return errorcode;
01791     }
01792   }
01793   else
01794   {
01795     errorcode = HAL_ERROR;
01796     return errorcode;
01797   }
01798
01799   __HAL_UNLOCK(hspi);
01800   return errorcode;
01801 }
01802 #endif /* USE_HSPI_RELOAD_TRANSFER */
01803
01804 #if defined(USE_SPI_RELOAD_TRANSFER)
01805 /**
01806   * @brief  Receive an additional amount of data in blocking mode.
01807   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
01808   *                the configuration information for SPI module.
01809   * @param  pData: pointer to data buffer
01810   * @param  Size : amount of data to be sent
01811   * @retval HAL status
01812   */
01813 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01814 {
01815   HAL_StatusTypeDef errorcode = HAL_OK;
01816   HAL_SPI_StateTypeDef  tmp_state;
01817
01818   /* Lock the process */
01819   __HAL_LOCK(hspi);
01820
01821   if ((pData == NULL) || (Size == 0UL))
01822   {
01823     errorcode = HAL_ERROR;
01824     __HAL_UNLOCK(hspi);
01825     return errorcode;
01826   }
01827
01828   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
01829   {
01830     /* check if there is already a request to reload */
01831     if (hspi->Reload.Requested == 1UL)
01832     {
01833       errorcode = HAL_ERROR;
01834       __HAL_UNLOCK(hspi);
01835       return errorcode;
01836     }
01837
01838     /* Insert the new number of data that will be received just after the current one */
01839     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
01840
01841     /* Set the transaction information */
01842     hspi->Reload.Requested   = 1UL;
01843     hspi->Reload.pRxBuffPtr  = (uint8_t *)pData;
01844     hspi->Reload.RxXferSize  = Size;
01845
01846     tmp_state = hspi->State;
01847
01848     /* Check if the current reception is already completed */
01849     if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
01850     {
01851       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
01852       MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
01853       hspi->Reload.Requested = 0UL;
01854       errorcode = HAL_ERROR;
01855       __HAL_UNLOCK(hspi);
01856       return errorcode;
01857     }
01858   }
01859   else
01860   {
01861     errorcode = HAL_ERROR;
01862     return errorcode;
01863   }
01864
01865   __HAL_UNLOCK(hspi);
01866   return errorcode;
01867 }
01868 #endif /* USE_HSPI_RELOAD_TRANSFER */
01869
01870 #if defined(USE_SPI_RELOAD_TRANSFER)
01871 /**
01872   * @brief  Transmit and receive an additional amount of data in blocking mode.
01873   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
01874   *                  the configuration information for SPI module.
01875   * @param  pTxData: pointer to transmission data buffer
01876   * @param  pRxData: pointer to reception data buffer
01877   * @param  Size   : amount of data to be sent and received
01878   * @retval HAL status
01879   */
01880 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01881 {
01882   HAL_StatusTypeDef errorcode = HAL_OK;
01883   HAL_SPI_StateTypeDef  tmp_state;
01884
01885   /* Lock the process */
01886   __HAL_LOCK(hspi);
01887
01888   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
01889   {
01890     errorcode = HAL_ERROR;
01891     __HAL_UNLOCK(hspi);
01892     return errorcode;
01893   }
01894
01895   if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
01896   {
01897     /* check if there is already a request to reload */
01898     if (hspi->Reload.Requested == 1UL)
01899     {
01900       errorcode = HAL_ERROR;
01901       __HAL_UNLOCK(hspi);
01902       return errorcode;
01903     }
01904
01905     /* Insert the new number of data that will be sent and received just after the current one */
01906     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
01907
01908     /* Set the transaction information */
01909     hspi->Reload.Requested   = 1UL;
01910     hspi->Reload.pTxBuffPtr  = (uint8_t *)pTxData;
01911     hspi->Reload.TxXferSize  = Size;
01912     hspi->Reload.pRxBuffPtr  = (uint8_t *)pRxData;
01913     hspi->Reload.RxXferSize  = Size;
01914
01915     tmp_state = hspi->State;
01916
01917     /* Check if the current transmit is already completed */
01918     if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
01919     {
01920       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
01921       MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
01922       hspi->Reload.Requested = 0UL;
01923       errorcode = HAL_ERROR;
01924       __HAL_UNLOCK(hspi);
01925       return errorcode;
01926     }
01927   }
01928   else
01929   {
01930     errorcode = HAL_ERROR;
01931     return errorcode;
01932   }
01933
01934   __HAL_UNLOCK(hspi);
01935   return errorcode;
01936 }
01937 #endif /* USE_HSPI_RELOAD_TRANSFER */
01938
01939 /**
01940   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01941   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
01942   *                the configuration information for SPI module.
01943   * @param  pData: pointer to data buffer
01944   * @param  Size : amount of data to be sent
01945   * @retval HAL status
01946   */
01947 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01948 {
01949   HAL_StatusTypeDef errorcode = HAL_OK;
01950
01951   /* Check Direction parameter */
01952   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
01953
01954   /* Process Locked */
01955   __HAL_LOCK(hspi);
01956
01957   if (hspi->State != HAL_SPI_STATE_READY)
01958   {
01959     errorcode = HAL_BUSY;
01960     __HAL_UNLOCK(hspi);
01961     return errorcode;
01962   }
01963
01964   if ((pData == NULL) || (Size == 0UL))
01965   {
01966     errorcode = HAL_ERROR;
01967     __HAL_UNLOCK(hspi);
01968     return errorcode;
01969   }
01970
01971   /* Set the transaction information */
01972   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01973   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01974   hspi->pTxBuffPtr  = (uint8_t *)pData;
01975   hspi->TxXferSize  = Size;
01976   hspi->TxXferCount = Size;
01977
01978   /* Init field not used in handle to zero */
01979   hspi->pRxBuffPtr  = NULL;
01980   hspi->TxISR       = NULL;
01981   hspi->RxISR       = NULL;
01982   hspi->RxXferSize  = (uint16_t)0UL;
01983   hspi->RxXferCount = (uint16_t)0UL;
01984
01985   /* Configure communication direction : 1Line */
01986   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01987   {
01988     SPI_1LINE_TX(hspi);
01989   }
01990
01991   /* Packing mode management is enabled by the DMA settings */
01992   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
01993       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
01994                                                      (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
01995   {
01996     /* Restriction the DMA data received is not allowed in this mode */
01997     errorcode = HAL_ERROR;
01998     __HAL_UNLOCK(hspi);
01999     return errorcode;
02000   }
02001
02002   /* Adjust XferCount according to DMA alignment / Data size */
02003   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
02004   {
02005     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02006     {
02007       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
02008     }
02009     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02010     {
02011       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
02012     }
02013   }
02014   else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
02015   {
02016     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02017     {
02018       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
02019     }
02020   }
02021   else
02022   {
02023     /* Adjustment done */
02024   }
02025
02026   /* Set the SPI TxDMA Half transfer complete callback */
02027   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
02028
02029   /* Set the SPI TxDMA transfer complete callback */
02030   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
02031
02032   /* Set the DMA error callback */
02033   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
02034
02035   /* Set the DMA AbortCpltCallback */
02036   hspi->hdmatx->XferAbortCallback = NULL;
02037
02038   /* Clear TXDMAEN bit*/
02039   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
02040
02041   /* Enable the Tx DMA Stream/Channel */
02042   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
02043   {
02044     /* Update SPI error code */
02045     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02046     errorcode = HAL_ERROR;
02047     hspi->State = HAL_SPI_STATE_READY;
02048     return errorcode;
02049   }
02050
02051   /* Set the number of data at current transfer */
02052   if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
02053   {
02054     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
02055   }
02056   else
02057   {
02058     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
02059   }
02060
02061   /* Enable Tx DMA Request */
02062   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
02063
02064   /* Enable the SPI Error Interrupt Bit */
02065   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
02066
02067   /* Enable SPI peripheral */
02068   __HAL_SPI_ENABLE(hspi);
02069
02070   if (hspi->Init.Mode == SPI_MODE_MASTER)
02071   {
02072     /* Master transfer start */
02073     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
02074   }
02075
02076   /* Process Unlocked */
02077   __HAL_UNLOCK(hspi);
02078   return errorcode;
02079 }
02080
02081 /**
02082   * @brief  Receive an amount of data in non-blocking mode with DMA.
02083   * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
02084   *                the configuration information for SPI module.
02085   * @param  pData: pointer to data buffer
02086   * @param  Size : amount of data to be sent
02087   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
02088   * @retval HAL status
02089   */
02090 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
02091 {
02092   HAL_StatusTypeDef errorcode = HAL_OK;
02093
02094   /* Check Direction parameter */
02095   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
02096
02097   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
02098   {
02099     hspi->State = HAL_SPI_STATE_BUSY_RX;
02100     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
02101     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
02102   }
02103
02104   /* Process Locked */
02105   __HAL_LOCK(hspi);
02106
02107   if (hspi->State != HAL_SPI_STATE_READY)
02108   {
02109     errorcode = HAL_BUSY;
02110     __HAL_UNLOCK(hspi);
02111     return errorcode;
02112   }
02113
02114   if ((pData == NULL) || (Size == 0UL))
02115   {
02116     errorcode = HAL_ERROR;
02117     __HAL_UNLOCK(hspi);
02118     return errorcode;
02119   }
02120
02121   /* Set the transaction information */
02122   hspi->State       = HAL_SPI_STATE_BUSY_RX;
02123   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02124   hspi->pRxBuffPtr  = (uint8_t *)pData;
02125   hspi->RxXferSize  = Size;
02126   hspi->RxXferCount = Size;
02127
02128   /*Init field not used in handle to zero */
02129   hspi->RxISR       = NULL;
02130   hspi->TxISR       = NULL;
02131   hspi->TxXferSize  = (uint16_t) 0UL;
02132   hspi->TxXferCount = (uint16_t) 0UL;
02133
02134   /* Configure communication direction : 1Line */
02135   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
02136   {
02137     SPI_1LINE_RX(hspi);
02138   }
02139
02140   /* Packing mode management is enabled by the DMA settings */
02141   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
02142       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
02143                                                      (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
02144   {
02145     /* Restriction the DMA data received is not allowed in this mode */
02146     errorcode = HAL_ERROR;
02147     __HAL_UNLOCK(hspi);
02148     return errorcode;
02149   }
02150
02151   /* Clear RXDMAEN bit */
02152   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
02153
02154   /* Adjust XferCount according to DMA alignment / Data size */
02155   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
02156   {
02157     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02158     {
02159       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
02160     }
02161     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02162     {
02163       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
02164     }
02165   }
02166   else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
02167   {
02168     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02169     {
02170       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
02171     }
02172   }
02173   else
02174   {
02175     /* Adjustment done */
02176   }
02177
02178   /* Set the SPI RxDMA Half transfer complete callback */
02179   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02180
02181   /* Set the SPI Rx DMA transfer complete callback */
02182   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
02183
02184   /* Set the DMA error callback */
02185   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02186
02187   /* Set the DMA AbortCpltCallback */
02188   hspi->hdmarx->XferAbortCallback = NULL;
02189
02190   /* Enable the Rx DMA Stream/Channel  */
02191   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
02192   {
02193     /* Update SPI error code */
02194     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02195     errorcode = HAL_ERROR;
02196     hspi->State = HAL_SPI_STATE_READY;
02197     return errorcode;
02198   }
02199
02200   /* Set the number of data at current transfer */
02201   if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
02202   {
02203     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
02204   }
02205   else
02206   {
02207     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
02208   }
02209
02210   /* Enable Rx DMA Request */
02211   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
02212
02213   /* Enable the SPI Error Interrupt Bit */
02214   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
02215
02216   /* Enable SPI peripheral */
02217   __HAL_SPI_ENABLE(hspi);
02218
02219   if (hspi->Init.Mode == SPI_MODE_MASTER)
02220   {
02221     /* Master transfer start */
02222     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
02223   }
02224
02225   /* Process Unlocked */
02226   __HAL_UNLOCK(hspi);
02227   return errorcode;
02228 }
02229
02230 /**
02231   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
02232   * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
02233   *                  the configuration information for SPI module.
02234   * @param  pTxData: pointer to transmission data buffer
02235   * @param  pRxData: pointer to reception data buffer
02236   * @param  Size   : amount of data to be sent
02237   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
02238   * @retval HAL status
02239   */
02240 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
02241                                               uint16_t Size)
02242 {
02243   HAL_SPI_StateTypeDef tmp_state;
02244   HAL_StatusTypeDef errorcode = HAL_OK;
02245
02246   uint32_t             tmp_mode;
02247
02248   /* Check Direction parameter */
02249   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
02250
02251   /* Process locked */
02252   __HAL_LOCK(hspi);
02253
02254   /* Init temporary variables */
02255   tmp_state   = hspi->State;
02256   tmp_mode    = hspi->Init.Mode;
02257
02258   if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY)))
02259   {
02260     errorcode = HAL_BUSY;
02261     __HAL_UNLOCK(hspi);
02262     return errorcode;
02263   }
02264
02265   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
02266   {
02267     errorcode = HAL_ERROR;
02268     __HAL_UNLOCK(hspi);
02269     return errorcode;
02270   }
02271
02272   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
02273   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
02274   {
02275     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
02276   }
02277
02278   /* Set the transaction information */
02279   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02280   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
02281   hspi->TxXferSize  = Size;
02282   hspi->TxXferCount = Size;
02283   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
02284   hspi->RxXferSize  = Size;
02285   hspi->RxXferCount = Size;
02286
02287   /* Init field not used in handle to zero */
02288   hspi->RxISR       = NULL;
02289   hspi->TxISR       = NULL;
02290
02291   /* Reset the Tx/Rx DMA bits */
02292   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02293
02294   /* Packing mode management is enabled by the DMA settings */
02295   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
02296       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
02297                                                      (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
02298   {
02299     /* Restriction the DMA data received is not allowed in this mode */
02300     errorcode = HAL_ERROR;
02301     /* Process Unlocked */
02302     __HAL_UNLOCK(hspi);
02303     return errorcode;
02304   }
02305
02306   /* Adjust XferCount according to DMA alignment / Data size */
02307   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
02308   {
02309     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02310     {
02311       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
02312     }
02313     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02314     {
02315       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
02316     }
02317     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02318     {
02319       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
02320     }
02321     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02322     {
02323       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
02324     }
02325   }
02326   else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
02327   {
02328     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02329     {
02330       hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
02331     }
02332     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
02333     {
02334       hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
02335     }
02336   }
02337   else
02338   {
02339     /* Adjustment done */
02340   }
02341
02342   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
02343   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
02344   {
02345     /* Set the SPI Rx DMA Half transfer complete callback */
02346     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02347     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
02348   }
02349   else
02350   {
02351     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
02352     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
02353     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
02354   }
02355
02356   /* Set the DMA error callback */
02357   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02358
02359   /* Set the DMA AbortCallback */
02360   hspi->hdmarx->XferAbortCallback = NULL;
02361
02362   /* Enable the Rx DMA Stream/Channel  */
02363   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
02364   {
02365     /* Update SPI error code */
02366     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02367     errorcode = HAL_ERROR;
02368     hspi->State = HAL_SPI_STATE_READY;
02369     return errorcode;
02370   }
02371
02372   /* Enable Rx DMA Request */
02373   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
02374
02375   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
02376   is performed in DMA reception complete callback  */
02377   hspi->hdmatx->XferHalfCpltCallback = NULL;
02378   hspi->hdmatx->XferCpltCallback     = NULL;
02379   hspi->hdmatx->XferErrorCallback    = NULL;
02380   hspi->hdmatx->XferAbortCallback    = NULL;
02381
02382   /* Enable the Tx DMA Stream/Channel  */
02383   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
02384   {
02385     /* Update SPI error code */
02386     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02387     errorcode = HAL_ERROR;
02388     hspi->State = HAL_SPI_STATE_READY;
02389     return errorcode;
02390   }
02391
02392   if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
02393   {
02394     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
02395   }
02396   else
02397   {
02398     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
02399   }
02400
02401   /* Enable Tx DMA Request */
02402   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
02403
02404   /* Enable the SPI Error Interrupt Bit */
02405   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
02406
02407   /* Enable SPI peripheral */
02408   __HAL_SPI_ENABLE(hspi);
02409
02410   if (hspi->Init.Mode == SPI_MODE_MASTER)
02411   {
02412     /* Master transfer start */
02413     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
02414   }
02415
02416   /* Process Unlocked */
02417   __HAL_UNLOCK(hspi);
02418   return errorcode;
02419 }
02420
02421 /**
02422   * @brief  Abort ongoing transfer (blocking mode).
02423   * @param  hspi SPI handle.
02424   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02425   *         started in Interrupt or DMA mode.
02426   * @note   This procedure performs following operations :
02427   *          + Disable SPI Interrupts (depending of transfer direction)
02428   *          + Disable the DMA transfer in the peripheral register (if enabled)
02429   *          + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
02430   *          + Set handle State to READY.
02431   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
02432   * @retval HAL status
02433 */
02434 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
02435 {
02436   HAL_StatusTypeDef errorcode;
02437
02438   __IO uint32_t count;
02439
02440   /* Process locked */
02441   __HAL_LOCK(hspi);
02442
02443   /* Set hspi->state to aborting to avoid any interaction */
02444   hspi->State = HAL_SPI_STATE_ABORT;
02445
02446   /* Initialized local variable  */
02447   errorcode = HAL_OK;
02448   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
02449
02450   /* If master communication on going, make sure current frame is done before closing the connection */
02451   if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
02452   {
02453     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
02454     do
02455     {
02456       count--;
02457       if (count == 0UL)
02458       {
02459         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02460         break;
02461       }
02462     }
02463     while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
02464   }
02465
02466   /* Disable the SPI DMA Tx request if enabled */
02467   if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
02468   {
02469     if (hspi->hdmatx != NULL)
02470     {
02471       /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
02472       hspi->hdmatx->XferAbortCallback = NULL;
02473
02474       /* Abort DMA Tx Handle linked to SPI Peripheral */
02475       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02476       {
02477         if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
02478         {
02479           hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02480         }
02481       }
02482     }
02483   }
02484
02485   /* Disable the SPI DMA Rx request if enabled */
02486   if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
02487   {
02488     if (hspi->hdmarx != NULL)
02489     {
02490       /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02491       hspi->hdmarx->XferAbortCallback = NULL;
02492
02493       /* Abort DMA Rx Handle linked to SPI Peripheral */
02494       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02495       {
02496         if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
02497         {
02498           hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02499         }
02500       }
02501     }
02502   }
02503
02504   /* Proceed with abort procedure */
02505   SPI_AbortTransfer(hspi);
02506
02507   /* Check error during Abort procedure */
02508   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02509   {
02510     /* return HAL_Error in case of error during Abort procedure */
02511     errorcode = HAL_ERROR;
02512   }
02513   else
02514   {
02515     /* Reset errorCode */
02516     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02517   }
02518
02519   /* Process Unlocked */
02520   __HAL_UNLOCK(hspi);
02521
02522   /* Restore hspi->state to ready */
02523   hspi->State = HAL_SPI_STATE_READY;
02524
02525   return errorcode;
02526 }
02527
02528 /**
02529   * @brief  Abort ongoing transfer (Interrupt mode).
02530   * @param  hspi SPI handle.
02531   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02532   *         started in Interrupt or DMA mode.
02533   * @note   This procedure performs following operations :
02534   *          + Disable SPI Interrupts (depending of transfer direction)
02535   *          + Disable the DMA transfer in the peripheral register (if enabled)
02536   *          + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02537   *          + Set handle State to READY
02538   *          + At abort completion, call user abort complete callback.
02539   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02540   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02541   * @retval HAL status
02542 */
02543 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02544 {
02545   HAL_StatusTypeDef errorcode;
02546   __IO uint32_t count;
02547   uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL;
02548
02549   /* Set hspi->state to aborting to avoid any interaction */
02550   hspi->State = HAL_SPI_STATE_ABORT;
02551
02552   /* Initialized local variable  */
02553   errorcode = HAL_OK;
02554   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
02555
02556   /* If master communication on going, make sure current frame is done before closing the connection */
02557   if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
02558   {
02559     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
02560     do
02561     {
02562       count--;
02563       if (count == 0UL)
02564       {
02565         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02566         break;
02567       }
02568     }
02569     while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
02570   }
02571
02572   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
02573      before any call to DMA Abort functions */
02574
02575   if(hspi->hdmatx != NULL)
02576   {
02577     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
02578     {
02579       /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
02580       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02581
02582       dma_tx_abort_done = 0UL;
02583
02584       /* Abort DMA Tx Handle linked to SPI Peripheral */
02585       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02586       {
02587         if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
02588         {
02589           dma_tx_abort_done = 1UL;
02590           hspi->hdmatx->XferAbortCallback = NULL;
02591         }
02592       }
02593     }
02594     else
02595     {
02596       hspi->hdmatx->XferAbortCallback = NULL;
02597     }
02598   }
02599
02600   if(hspi->hdmarx != NULL)
02601   {
02602     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
02603     {
02604       /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
02605       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02606
02607       dma_rx_abort_done = 0UL;
02608
02609       /* Abort DMA Rx Handle linked to SPI Peripheral */
02610       if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
02611       {
02612         if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
02613         {
02614           dma_rx_abort_done = 1UL;
02615           hspi->hdmarx->XferAbortCallback = NULL;
02616         }
02617       }
02618     }
02619     else
02620     {
02621       hspi->hdmarx->XferAbortCallback = NULL;
02622     }
02623   }
02624
02625   /* If no running DMA transfer, finish cleanup and call callbacks */
02626   if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
02627   {
02628     /* Proceed with abort procedure */
02629     SPI_AbortTransfer(hspi);
02630
02631     /* Check error during Abort procedure */
02632     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02633     {
02634       /* return HAL_Error in case of error during Abort procedure */
02635       errorcode = HAL_ERROR;
02636     }
02637     else
02638     {
02639       /* Reset errorCode */
02640       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02641     }
02642
02643     /* Restore hspi->state to ready */
02644     hspi->State = HAL_SPI_STATE_READY;
02645
02646     /* Call user Abort complete callback */
02647 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
02648     hspi->AbortCpltCallback(hspi);
02649 #else
02650     HAL_SPI_AbortCpltCallback(hspi);
02651 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02652   }
02653
02654   return errorcode;
02655 }
02656
02657 /**
02658   * @brief  Pause the DMA Transfer.
02659   *         This API is not supported, it is maintained for backward compatibility.
02660   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02661   *               the configuration information for the specified SPI module.
02662   * @retval HAL_ERROR
02663   */
02664 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02665 {
02666   /* Set error code to not supported */
02667   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
02668
02669   return HAL_ERROR;
02670 }
02671
02672 /**
02673   * @brief  Resume the DMA Transfer.
02674   *         This API is not supported, it is maintained for backward compatibility.
02675   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02676   *               the configuration information for the specified SPI module.
02677   * @retval HAL_ERROR
02678   */
02679 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02680 {
02681   /* Set error code to not supported */
02682   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
02683
02684   return HAL_ERROR;
02685 }
02686
02687 /**
02688   * @brief  Stop the DMA Transfer.
02689   *         This API is not supported, it is maintained for backward compatibility.
02690   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02691   *               the configuration information for the specified SPI module.
02692   * @retval HAL_ERROR
02693   */
02694 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02695 {
02696   /* Set error code to not supported */
02697   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
02698
02699   return HAL_ERROR;
02700 }
02701
02702 /**
02703   * @brief  Handle SPI interrupt request.
02704   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02705   *               the configuration information for the specified SPI module.
02706   * @retval None
02707   */
02708 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02709 {
02710   uint32_t itsource = hspi->Instance->IER;
02711   uint32_t itflag   = hspi->Instance->SR;
02712   uint32_t trigger  = itsource & itflag;
02713   uint32_t cfg1     = hspi->Instance->CFG1;
02714   uint32_t handled  = 0UL;
02715
02716   HAL_SPI_StateTypeDef State = hspi->State;
02717
02718
02719   /* SPI in mode Transmitter and Receiver ------------------------------------*/
02720   if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
02721   {
02722     hspi->TxISR(hspi);
02723     hspi->RxISR(hspi);
02724     handled = 1UL;
02725   }
02726
02727   /* SPI in mode Receiver ----------------------------------------------------*/
02728   if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
02729   {
02730     hspi->RxISR(hspi);
02731     handled = 1UL;
02732   }
02733
02734   /* SPI in mode Transmitter -------------------------------------------------*/
02735   if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
02736   {
02737     hspi->TxISR(hspi);
02738     handled = 1UL;
02739   }
02740
02741 #if defined(USE_SPI_RELOAD_TRANSFER)
02742   /* SPI Reload  -------------------------------------------------*/
02743   if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF))
02744   {
02745     hspi->Reload.Requested = 0UL;
02746     __HAL_SPI_CLEAR_TSERFFLAG(hspi);
02747   }
02748 #endif /* USE_HSPI_RELOAD_TRANSFER */
02749
02750   if (handled != 0UL)
02751   {
02752     return;
02753   }
02754
02755   /* SPI End Of Transfer: DMA or IT based transfer */
02756   if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
02757   {
02758     /* Clear EOT/TXTF/SUSP flag */
02759     __HAL_SPI_CLEAR_EOTFLAG(hspi);
02760     __HAL_SPI_CLEAR_TXTFFLAG(hspi);
02761     __HAL_SPI_CLEAR_SUSPFLAG(hspi);
02762
02763     /* Disable EOT interrupt */
02764     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
02765
02766     /* DMA Normal Mode */
02767     if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) ||                    // IT based transfer is done
02768       ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) ||  // DMA is used in normal mode
02769       ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL)))    // DMA is used in normal mode
02770     {
02771       /* For the IT based receive extra polling maybe required for last packet */
02772       if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
02773       {
02774         /* Pooling remaining data */
02775         while (hspi->RxXferCount != 0UL)
02776         {
02777           /* Receive data in 32 Bit mode */
02778           if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
02779           {
02780             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
02781             hspi->pRxBuffPtr += sizeof(uint32_t);
02782           }
02783           /* Receive data in 16 Bit mode */
02784           else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02785           {
02786             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
02787             hspi->pRxBuffPtr += sizeof(uint16_t);
02788           }
02789           /* Receive data in 8 Bit mode */
02790           else
02791           {
02792             *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
02793             hspi->pRxBuffPtr += sizeof(uint8_t);
02794           }
02795
02796           hspi->RxXferCount--;
02797         }
02798       }
02799
02800       /* Call SPI Standard close procedure */
02801       SPI_CloseTransfer(hspi);
02802
02803       hspi->State = HAL_SPI_STATE_READY;
02804       if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02805       {
02806 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
02807         hspi->ErrorCallback(hspi);
02808 #else
02809         HAL_SPI_ErrorCallback(hspi);
02810 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02811         return;
02812       }
02813     }
02814
02815 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
02816     /* Call appropriate user callback */
02817     if (State == HAL_SPI_STATE_BUSY_TX_RX)
02818     {
02819       hspi->TxRxCpltCallback(hspi);
02820     }
02821     else if (State == HAL_SPI_STATE_BUSY_RX)
02822     {
02823       hspi->RxCpltCallback(hspi);
02824     }
02825     else if (State == HAL_SPI_STATE_BUSY_TX)
02826     {
02827       hspi->TxCpltCallback(hspi);
02828     }
02829 #else
02830     /* Call appropriate user callback */
02831     if (State == HAL_SPI_STATE_BUSY_TX_RX)
02832     {
02833       HAL_SPI_TxRxCpltCallback(hspi);
02834     }
02835     else if (State == HAL_SPI_STATE_BUSY_RX)
02836     {
02837       HAL_SPI_RxCpltCallback(hspi);
02838     }
02839     else if (State == HAL_SPI_STATE_BUSY_TX)
02840     {
02841       HAL_SPI_TxCpltCallback(hspi);
02842     }
02843         else
02844     {
02845       /* end of the appropriate call */
02846     }
02847 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02848
02849     return;
02850   }
02851
02852   if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
02853   {
02854     /* Abort on going, clear SUSP flag to avoid infinite looping */
02855     __HAL_SPI_CLEAR_SUSPFLAG(hspi);
02856
02857     return;
02858   }
02859
02860   /* SPI in Error Treatment --------------------------------------------------*/
02861   if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
02862   {
02863     /* SPI Overrun error interrupt occurred ----------------------------------*/
02864     if ((trigger & SPI_FLAG_OVR) != 0UL)
02865     {
02866       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02867       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02868     }
02869
02870     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02871     if ((trigger & SPI_FLAG_MODF) != 0UL)
02872     {
02873       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02874       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02875     }
02876
02877     /* SPI Frame error interrupt occurred ------------------------------------*/
02878     if ((trigger & SPI_FLAG_FRE) != 0UL)
02879     {
02880       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02881       __HAL_SPI_CLEAR_FREFLAG(hspi);
02882     }
02883
02884     /* SPI Underrun error interrupt occurred ------------------------------------*/
02885     if ((trigger & SPI_FLAG_UDR) != 0UL)
02886     {
02887       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
02888       __HAL_SPI_CLEAR_UDRFLAG(hspi);
02889     }
02890
02891     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02892     {
02893       /* Disable SPI peripheral */
02894       __HAL_SPI_DISABLE(hspi);
02895
02896       /* Disable all interrupts */
02897       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
02898
02899       /* Disable the SPI DMA requests if enabled */
02900       if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
02901       {
02902         /* Disable the SPI DMA requests */
02903         CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02904
02905         /* Abort the SPI DMA Rx channel */
02906         if (hspi->hdmarx != NULL)
02907         {
02908           /* Set the SPI DMA Abort callback :
02909           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02910           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02911           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
02912           {
02913             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02914           }
02915         }
02916         /* Abort the SPI DMA Tx channel */
02917         if (hspi->hdmatx != NULL)
02918         {
02919           /* Set the SPI DMA Abort callback :
02920           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02921           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02922           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
02923           {
02924             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02925           }
02926         }
02927       }
02928       else
02929       {
02930         /* Restore hspi->State to Ready */
02931         hspi->State = HAL_SPI_STATE_READY;
02932
02933         /* Call user error callback */
02934 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
02935         hspi->ErrorCallback(hspi);
02936 #else
02937         HAL_SPI_ErrorCallback(hspi);
02938 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02939       }
02940     }
02941     return;
02942   }
02943 }
02944
02945 /**
02946   * @brief Tx Transfer completed callback.
02947   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02948   *               the configuration information for SPI module.
02949   * @retval None
02950   */
02951 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02952 {
02953   /* Prevent unused argument(s) compilation warning */
02954   UNUSED(hspi);
02955
02956   /* NOTE : This function should not be modified, when the callback is needed,
02957             the HAL_SPI_TxCpltCallback should be implemented in the user file
02958    */
02959 }
02960
02961 /**
02962   * @brief Rx Transfer completed callback.
02963   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02964   *               the configuration information for SPI module.
02965   * @retval None
02966   */
02967 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02968 {
02969   /* Prevent unused argument(s) compilation warning */
02970   UNUSED(hspi);
02971
02972   /* NOTE : This function should not be modified, when the callback is needed,
02973             the HAL_SPI_RxCpltCallback should be implemented in the user file
02974    */
02975 }
02976
02977 /**
02978   * @brief Tx and Rx Transfer completed callback.
02979   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02980   *               the configuration information for SPI module.
02981   * @retval None
02982   */
02983 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02984 {
02985   /* Prevent unused argument(s) compilation warning */
02986   UNUSED(hspi);
02987
02988   /* NOTE : This function should not be modified, when the callback is needed,
02989             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02990    */
02991 }
02992
02993 /**
02994   * @brief Tx Half Transfer completed callback.
02995   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02996   *               the configuration information for SPI module.
02997   * @retval None
02998   */
02999 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
03000 {
03001   /* Prevent unused argument(s) compilation warning */
03002   UNUSED(hspi);
03003
03004   /* NOTE : This function should not be modified, when the callback is needed,
03005             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
03006    */
03007 }
03008
03009 /**
03010   * @brief Rx Half Transfer completed callback.
03011   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03012   *               the configuration information for SPI module.
03013   * @retval None
03014   */
03015 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
03016 {
03017   /* Prevent unused argument(s) compilation warning */
03018   UNUSED(hspi);
03019
03020   /* NOTE : This function should not be modified, when the callback is needed,
03021             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
03022    */
03023 }
03024
03025 /**
03026   * @brief Tx and Rx Half Transfer callback.
03027   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03028   *               the configuration information for SPI module.
03029   * @retval None
03030   */
03031 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
03032 {
03033   /* Prevent unused argument(s) compilation warning */
03034   UNUSED(hspi);
03035
03036   /* NOTE : This function should not be modified, when the callback is needed,
03037             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
03038    */
03039 }
03040
03041 /**
03042   * @brief SPI error callback.
03043   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03044   *               the configuration information for SPI module.
03045   * @retval None
03046   */
03047 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
03048 {
03049   /* Prevent unused argument(s) compilation warning */
03050   UNUSED(hspi);
03051
03052   /* NOTE : This function should not be modified, when the callback is needed,
03053             the HAL_SPI_ErrorCallback should be implemented in the user file
03054    */
03055   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
03056             and user can use HAL_SPI_GetError() API to check the latest error occurred
03057    */
03058 }
03059
03060 /**
03061   * @brief  SPI Abort Complete callback.
03062   * @param  hspi SPI handle.
03063   * @retval None
03064   */
03065 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
03066 {
03067   /* Prevent unused argument(s) compilation warning */
03068   UNUSED(hspi);
03069
03070   /* NOTE : This function should not be modified, when the callback is needed,
03071             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
03072    */
03073 }
03074
03075 /**
03076   * @}
03077   */
03078
03079 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
03080   * @brief   SPI control functions
03081   *
03082 @verbatim
03083  ===============================================================================
03084                       ##### Peripheral State and Errors functions #####
03085  ===============================================================================
03086     [..]
03087     This subsection provides a set of functions allowing to control the SPI.
03088      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
03089      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
03090 @endverbatim
03091   * @{
03092   */
03093
03094 /**
03095   * @brief  Return the SPI handle state.
03096   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03097   *               the configuration information for SPI module.
03098   * @retval SPI state
03099   */
03100 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
03101 {
03102   /* Return SPI handle state */
03103   return hspi->State;
03104 }
03105
03106 /**
03107   * @brief  Return the SPI error code.
03108   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03109   *               the configuration information for SPI module.
03110   * @retval SPI error code in bitmap format
03111   */
03112 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
03113 {
03114   /* Return SPI ErrorCode */
03115   return hspi->ErrorCode;
03116 }
03117
03118 /**
03119   * @}
03120   */
03121
03122 /**
03123   * @}
03124   */
03125
03126 /** @addtogroup SPI_Private_Functions
03127   * @brief   Private functions
03128   * @{
03129   */
03130
03131 /**
03132   * @brief DMA SPI transmit process complete callback.
03133   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03134   *               the configuration information for the specified DMA module.
03135   * @retval None
03136   */
03137 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03138 {
03139   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03140
03141   if (hspi->State != HAL_SPI_STATE_ABORT)
03142   {
03143     if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
03144     {
03145 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03146       hspi->TxCpltCallback(hspi);
03147 #else
03148       HAL_SPI_TxCpltCallback(hspi);
03149 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03150     }
03151     else
03152     {
03153       /* Enable EOT interrupt */
03154       __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
03155     }
03156   }
03157 }
03158
03159 /**
03160   * @brief DMA SPI receive process complete callback.
03161   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03162   *               the configuration information for the specified DMA module.
03163   * @retval None
03164   */
03165 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03166 {
03167   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03168
03169   if (hspi->State != HAL_SPI_STATE_ABORT)
03170   {
03171     if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
03172     {
03173 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03174       hspi->RxCpltCallback(hspi);
03175 #else
03176       HAL_SPI_RxCpltCallback(hspi);
03177 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03178     }
03179     else
03180     {
03181       /* Enable EOT interrupt */
03182       __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
03183     }
03184   }
03185 }
03186
03187 /**
03188   * @brief  DMA SPI transmit receive process complete callback.
03189   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03190   *               the configuration information for the specified DMA module.
03191   * @retval None
03192   */
03193 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03194 {
03195   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03196
03197   if (hspi->State != HAL_SPI_STATE_ABORT)
03198   {
03199     if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
03200     {
03201 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03202       hspi->TxRxCpltCallback(hspi);
03203 #else
03204       HAL_SPI_TxRxCpltCallback(hspi);
03205 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03206     }
03207     else
03208     {
03209       /* Enable EOT interrupt */
03210       __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
03211     }
03212   }
03213 }
03214
03215 /**
03216   * @brief  DMA SPI half transmit process complete callback.
03217   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03218   *               the configuration information for the specified DMA module.
03219   * @retval None
03220   */
03221 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
03222 {
03223   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03224
03225 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03226   hspi->TxHalfCpltCallback(hspi);
03227 #else
03228   HAL_SPI_TxHalfCpltCallback(hspi);
03229 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03230 }
03231
03232 /**
03233   * @brief  DMA SPI half receive process complete callback
03234   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03235   *               the configuration information for the specified DMA module.
03236   * @retval None
03237   */
03238 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
03239 {
03240   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03241
03242 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03243   hspi->RxHalfCpltCallback(hspi);
03244 #else
03245   HAL_SPI_RxHalfCpltCallback(hspi);
03246 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03247 }
03248
03249 /**
03250   * @brief  DMA SPI half transmit receive process complete callback.
03251   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03252   *               the configuration information for the specified DMA module.
03253   * @retval None
03254   */
03255 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03256 {
03257   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03258
03259 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03260   hspi->TxRxHalfCpltCallback(hspi);
03261 #else
03262   HAL_SPI_TxRxHalfCpltCallback(hspi);
03263 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03264 }
03265
03266 /**
03267   * @brief  DMA SPI communication error callback.
03268   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
03269   *               the configuration information for the specified DMA module.
03270   * @retval None
03271   */
03272 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
03273 {
03274   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03275
03276   /* if DMA error is FIFO error ignore it */
03277   if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
03278   {
03279     /* Call SPI standard close procedure */
03280     SPI_CloseTransfer(hspi);
03281
03282     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
03283     hspi->State = HAL_SPI_STATE_READY;
03284 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03285     hspi->ErrorCallback(hspi);
03286 #else
03287     HAL_SPI_ErrorCallback(hspi);
03288 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03289   }
03290 }
03291
03292 /**
03293   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
03294   *         (To be called at end of DMA Abort procedure following error occurrence).
03295   * @param  hdma DMA handle.
03296   * @retval None
03297   */
03298 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03299 {
03300   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03301   hspi->RxXferCount = (uint16_t) 0UL;
03302   hspi->TxXferCount = (uint16_t) 0UL;
03303
03304   /* Restore hspi->State to Ready */
03305   hspi->State = HAL_SPI_STATE_READY;
03306
03307 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03308   hspi->ErrorCallback(hspi);
03309 #else
03310   HAL_SPI_ErrorCallback(hspi);
03311 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03312 }
03313
03314 /**
03315   * @brief  DMA SPI Tx communication abort callback, when initiated by user
03316   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03317   * @note   When this callback is executed, User Abort complete call back is called only if no
03318   *         Abort still ongoing for Rx DMA Handle.
03319   * @param  hdma DMA handle.
03320   * @retval None
03321   */
03322 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03323 {
03324   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03325
03326   hspi->hdmatx->XferAbortCallback = NULL;
03327
03328   /* Check if an Abort process is still ongoing */
03329   if (hspi->hdmarx != NULL)
03330   {
03331     if (hspi->hdmarx->XferAbortCallback != NULL)
03332     {
03333       return;
03334     }
03335   }
03336
03337   /* Call the Abort procedure */
03338   SPI_AbortTransfer(hspi);
03339
03340   /* Restore hspi->State to Ready */
03341   hspi->State = HAL_SPI_STATE_READY;
03342
03343   /* Call user Abort complete callback */
03344 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03345   hspi->AbortCpltCallback(hspi);
03346 #else
03347   HAL_SPI_AbortCpltCallback(hspi);
03348 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03349 }
03350
03351 /**
03352   * @brief  DMA SPI Rx communication abort callback, when initiated by user
03353   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03354   * @note   When this callback is executed, User Abort complete call back is called only if no
03355   *         Abort still ongoing for Tx DMA Handle.
03356   * @param  hdma DMA handle.
03357   * @retval None
03358   */
03359 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03360 {
03361   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03362
03363   hspi->hdmarx->XferAbortCallback = NULL;
03364
03365   /* Check if an Abort process is still ongoing */
03366   if (hspi->hdmatx != NULL)
03367   {
03368     if (hspi->hdmatx->XferAbortCallback != NULL)
03369     {
03370       return;
03371     }
03372   }
03373
03374   /* Call the Abort procedure */
03375   SPI_AbortTransfer(hspi);
03376
03377   /* Restore hspi->State to Ready */
03378   hspi->State = HAL_SPI_STATE_READY;
03379
03380   /* Call user Abort complete callback */
03381 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
03382   hspi->AbortCpltCallback(hspi);
03383 #else
03384   HAL_SPI_AbortCpltCallback(hspi);
03385 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03386 }
03387
03388 /**
03389   * @brief  Manage the receive 8-bit in Interrupt context.
03390   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03391   *               the configuration information for SPI module.
03392   * @retval None
03393   */
03394 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
03395 {
03396   /* Receive data in 8 Bit mode */
03397   *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
03398   hspi->pRxBuffPtr += sizeof(uint8_t);
03399   hspi->RxXferCount--;
03400
03401   /* Disable IT if no more data excepted */
03402   if (hspi->RxXferCount == 0UL)
03403   {
03404 #if defined(USE_SPI_RELOAD_TRANSFER)
03405     /* Check if there is any request to reload */
03406     if (hspi->Reload.Requested == 1UL)
03407     {
03408       hspi->RxXferSize  = hspi->Reload.RxXferSize;
03409       hspi->RxXferCount = hspi->Reload.RxXferSize;
03410       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
03411     }
03412     else
03413     {
03414       /* Disable RXP interrupts */
03415       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03416     }
03417 #else
03418     /* Disable RXP interrupts */
03419     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03420 #endif /* USE_HSPI_RELOAD_TRANSFER */
03421   }
03422 }
03423
03424
03425 /**
03426   * @brief  Manage the 16-bit receive in Interrupt context.
03427   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03428   *               the configuration information for SPI module.
03429   * @retval None
03430   */
03431 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
03432 {
03433   /* Receive data in 16 Bit mode */
03434   *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
03435   hspi->pRxBuffPtr += sizeof(uint16_t);
03436   hspi->RxXferCount--;
03437
03438   /* Disable IT if no more data excepted */
03439   if (hspi->RxXferCount == 0UL)
03440   {
03441 #if defined(USE_SPI_RELOAD_TRANSFER)
03442     /* Check if there is any request to reload */
03443     if (hspi->Reload.Requested == 1UL)
03444     {
03445       hspi->RxXferSize  = hspi->Reload.RxXferSize;
03446       hspi->RxXferCount = hspi->Reload.RxXferSize;
03447       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
03448     }
03449     else
03450     {
03451       /* Disable RXP interrupts */
03452       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03453     }
03454 #else
03455     /* Disable RXP interrupts */
03456     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03457 #endif /* USE_HSPI_RELOAD_TRANSFER */
03458   }
03459 }
03460
03461
03462 /**
03463   * @brief  Manage the 32-bit receive in Interrupt context.
03464   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03465   *               the configuration information for SPI module.
03466   * @retval None
03467   */
03468 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
03469 {
03470   /* Receive data in 32 Bit mode */
03471   *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
03472   hspi->pRxBuffPtr += sizeof(uint32_t);
03473   hspi->RxXferCount--;
03474
03475   /* Disable IT if no more data excepted */
03476   if (hspi->RxXferCount == 0UL)
03477   {
03478 #if defined(USE_SPI_RELOAD_TRANSFER)
03479     /* Check if there is any request to reload */
03480     if (hspi->Reload.Requested == 1UL)
03481     {
03482       hspi->RxXferSize  = hspi->Reload.RxXferSize;
03483       hspi->RxXferCount = hspi->Reload.RxXferSize;
03484       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
03485     }
03486     else
03487     {
03488       /* Disable RXP interrupts */
03489       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03490     }
03491 #else
03492     /* Disable RXP interrupts */
03493     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
03494 #endif /* USE_HSPI_RELOAD_TRANSFER */
03495   }
03496 }
03497
03498
03499 /**
03500   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03501   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03502   *               the configuration information for SPI module.
03503   * @retval None
03504   */
03505 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
03506 {
03507   /* Transmit data in 8 Bit mode */
03508   *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
03509   hspi->pTxBuffPtr += sizeof(uint8_t);
03510   hspi->TxXferCount--;
03511
03512   /* Disable IT if no more data excepted */
03513   if (hspi->TxXferCount == 0UL)
03514   {
03515 #if defined(USE_SPI_RELOAD_TRANSFER)
03516     /* Check if there is any request to reload */
03517     if (hspi->Reload.Requested == 1UL)
03518     {
03519       hspi->TxXferSize  = hspi->Reload.TxXferSize;
03520       hspi->TxXferCount = hspi->Reload.TxXferSize;
03521       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
03522     }
03523     else
03524     {
03525       /* Disable TXP interrupts */
03526       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03527     }
03528 #else
03529     /* Disable TXP interrupts */
03530     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03531 #endif /* USE_HSPI_RELOAD_TRANSFER */
03532   }
03533 }
03534
03535 /**
03536   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03537   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03538   *               the configuration information for SPI module.
03539   * @retval None
03540   */
03541 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
03542 {
03543   /* Transmit data in 16 Bit mode */
03544   *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
03545   hspi->pTxBuffPtr += sizeof(uint16_t);
03546   hspi->TxXferCount--;
03547
03548   /* Disable IT if no more data excepted */
03549   if (hspi->TxXferCount == 0UL)
03550   {
03551 #if defined(USE_SPI_RELOAD_TRANSFER)
03552     /* Check if there is any request to reload */
03553     if (hspi->Reload.Requested == 1UL)
03554     {
03555       hspi->TxXferSize  = hspi->Reload.TxXferSize;
03556       hspi->TxXferCount = hspi->Reload.TxXferSize;
03557       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
03558     }
03559     else
03560     {
03561       /* Disable TXP interrupts */
03562       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03563     }
03564 #else
03565     /* Disable TXP interrupts */
03566     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03567 #endif /* USE_HSPI_RELOAD_TRANSFER */
03568   }
03569 }
03570
03571 /**
03572   * @brief  Handle the data 32-bit transmit in Interrupt mode.
03573   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03574   *               the configuration information for SPI module.
03575   * @retval None
03576   */
03577 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
03578 {
03579   /* Transmit data in 32 Bit mode */
03580   *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
03581   hspi->pTxBuffPtr += sizeof(uint32_t);
03582   hspi->TxXferCount--;
03583
03584   /* Disable IT if no more data excepted */
03585   if (hspi->TxXferCount == 0UL)
03586   {
03587 #if defined(USE_SPI_RELOAD_TRANSFER)
03588     /* Check if there is any request to reload */
03589     if (hspi->Reload.Requested == 1UL)
03590     {
03591       hspi->TxXferSize  = hspi->Reload.TxXferSize;
03592       hspi->TxXferCount = hspi->Reload.TxXferSize;
03593       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
03594     }
03595     else
03596     {
03597       /* Disable TXP interrupts */
03598       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03599     }
03600 #else
03601     /* Disable TXP interrupts */
03602     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
03603 #endif /* USE_HSPI_RELOAD_TRANSFER */
03604   }
03605 }
03606
03607 /**
03608   * @brief  Abort Transfer and clear flags.
03609   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03610   *               the configuration information for SPI module.
03611   * @retval None
03612   */
03613 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
03614 {
03615   /* Disable SPI peripheral */
03616   __HAL_SPI_DISABLE(hspi);
03617
03618   /* Disable ITs */
03619   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
03620
03621   /* Clear the Status flags in the SR register */
03622   __HAL_SPI_CLEAR_EOTFLAG(hspi);
03623   __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03624
03625   /* Disable Tx DMA Request */
03626   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
03627
03628   /* Clear the Error flags in the SR register */
03629   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03630   __HAL_SPI_CLEAR_UDRFLAG(hspi);
03631   __HAL_SPI_CLEAR_FREFLAG(hspi);
03632   __HAL_SPI_CLEAR_MODFFLAG(hspi);
03633   __HAL_SPI_CLEAR_SUSPFLAG(hspi);
03634
03635 #if (USE_SPI_CRC != 0U)
03636   __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03637 #endif /* USE_SPI_CRC */
03638
03639   hspi->TxXferCount = (uint16_t)0UL;
03640   hspi->RxXferCount = (uint16_t)0UL;
03641 }
03642
03643
03644 /**
03645   * @brief  Close Transfer and clear flags.
03646   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03647   *               the configuration information for SPI module.
03648   * @retval HAL_ERROR: if any error detected
03649 *         HAL_OK: if nothing detected
03650   */
03651 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
03652 {
03653   uint32_t itflag = hspi->Instance->SR;
03654
03655   __HAL_SPI_CLEAR_EOTFLAG(hspi);
03656   __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03657
03658   /* Disable SPI peripheral */
03659   __HAL_SPI_DISABLE(hspi);
03660
03661   /* Disable ITs */
03662   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
03663
03664   /* Disable Tx DMA Request */
03665   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
03666
03667   /* Report UnderRun error for non RX Only communication */
03668   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
03669   {
03670     if ((itflag & SPI_FLAG_UDR) != 0UL)
03671     {
03672       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
03673       __HAL_SPI_CLEAR_UDRFLAG(hspi);
03674     }
03675   }
03676
03677   /* Report OverRun error for non TX Only communication */
03678   if (hspi->State != HAL_SPI_STATE_BUSY_TX)
03679   {
03680     if ((itflag & SPI_FLAG_OVR) != 0UL)
03681     {
03682       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
03683       __HAL_SPI_CLEAR_OVRFLAG(hspi);
03684     }
03685
03686 #if (USE_SPI_CRC != 0UL)
03687     /* Check if CRC error occurred */
03688     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03689     {
03690       if ((itflag & SPI_FLAG_CRCERR) != 0UL)
03691       {
03692         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03693         __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03694       }
03695     }
03696 #endif /* USE_SPI_CRC */
03697   }
03698
03699   /* SPI Mode Fault error interrupt occurred -------------------------------*/
03700   if ((itflag & SPI_FLAG_MODF) != 0UL)
03701   {
03702     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
03703     __HAL_SPI_CLEAR_MODFFLAG(hspi);
03704   }
03705
03706   /* SPI Frame error interrupt occurred ------------------------------------*/
03707   if ((itflag & SPI_FLAG_FRE) != 0UL)
03708   {
03709     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
03710     __HAL_SPI_CLEAR_FREFLAG(hspi);
03711   }
03712
03713   hspi->TxXferCount = (uint16_t)0UL;
03714   hspi->RxXferCount = (uint16_t)0UL;
03715 }
03716
03717 /**
03718   * @brief Handle SPI Communication Timeout.
03719   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
03720   *              the configuration information for SPI module.
03721   * @param Flag: SPI flag to check
03722   * @param Status: flag state to check
03723   * @param Timeout: Timeout duration
03724   * @param Tickstart: Tick start value
03725   * @retval HAL status
03726   */
03727 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
03728                                                     uint32_t Tickstart, uint32_t Timeout)
03729 {
03730   /* Wait until flag is set */
03731   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
03732   {
03733     /* Check for the Timeout */
03734     if ((((HAL_GetTick() - Tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
03735     {
03736       return HAL_TIMEOUT;
03737     }
03738   }
03739   return HAL_OK;
03740 }
03741
03742 /**
03743   * @brief  Compute configured packet size from fifo perspective.
03744   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03745   *               the configuration information for SPI module.
03746   * @retval Packet size occupied in the fifo
03747   */
03748 static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
03749 {
03750   uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
03751   uint32_t data_size       = (hspi->Init.DataSize      >> SPI_CFG1_DSIZE_Pos) + 1UL;
03752
03753   /* Convert data size to Byte */
03754   data_size = (data_size + 7UL) / 8UL;
03755
03756   return data_size * fifo_threashold;
03757 }
03758
03759
03760 /**
03761   * @}
03762   */
03763
03764 #endif /* HAL_SPI_MODULE_ENABLED */
03765
03766 /**
03767   * @}
03768   */
03769
03770 /**
03771   * @}
03772   */
03773
03774 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi.h Source File

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stm32h7xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SPI_H
00022 #define STM32H7xx_HAL_SPI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SPI
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SPI_Exported_Types SPI Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  SPI Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Mode;                              /*!< Specifies the SPI operating mode.
00050                                                      This parameter can be a value of @ref SPI_Mode */
00051
00052   uint32_t Direction;                         /*!< Specifies the SPI bidirectional mode state.
00053                                                      This parameter can be a value of @ref SPI_Direction */
00054
00055   uint32_t DataSize;                          /*!< Specifies the SPI data size.
00056                                                      This parameter can be a value of @ref SPI_Data_Size */
00057
00058   uint32_t CLKPolarity;                       /*!< Specifies the serial clock steady state.
00059                                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00060
00061   uint32_t CLKPhase;                          /*!< Specifies the clock active edge for the bit capture.
00062                                                      This parameter can be a value of @ref SPI_Clock_Phase */
00063
00064   uint32_t NSS;                               /*!< Specifies whether the NSS signal is managed by
00065                                                      hardware (NSS pin) or by software using the SSI bit.
00066                                                      This parameter can be a value of @ref SPI_Slave_Select_Management */
00067
00068   uint32_t BaudRatePrescaler;                 /*!< Specifies the Baud Rate prescaler value which will be
00069                                                      used to configure the transmit and receive SCK clock.
00070                                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00071                                                      @note The communication clock is derived from the master
00072                                                      clock. The slave clock does not need to be set. */
00073
00074   uint32_t FirstBit;                          /*!< Specifies whether data transfers start from MSB or LSB bit.
00075                                                      This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
00076
00077   uint32_t TIMode;                            /*!< Specifies if the TI mode is enabled or not.
00078                                                      This parameter can be a value of @ref SPI_TI_Mode */
00079
00080   uint32_t CRCCalculation;                    /*!< Specifies if the CRC calculation is enabled or not.
00081                                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00082
00083   uint32_t CRCPolynomial;                     /*!< Specifies the polynomial used for the CRC calculation.
00084                                                      This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
00085
00086   uint32_t CRCLength;                         /*!< Specifies the CRC Length used for the CRC calculation.
00087                                                      This parameter can be a value of @ref SPI_CRC_length */
00088
00089   uint32_t NSSPMode;                          /*!< Specifies whether the NSSP signal is enabled or not .
00090                                                      This parameter can be a value of @ref SPI_NSSP_Mode
00091                                                      This mode is activated by the SSOM bit in the SPIx_CR2 register and
00092                                                      it takes effect only if the SPI interface is configured as Motorola SPI
00093                                                      master (FRF=0). */
00094
00095   uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal (present on SS pin) is
00096                                                      considered as active one.
00097                                                      This parameter can be a value of @ref SPI_NSS_Polarity */
00098
00099   uint32_t FifoThreshold;                     /*!< Specifies the FIFO threshold level.
00100                                                      This parameter can be a value of @ref SPI_Fifo_Threshold */
00101
00102   uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
00103                                                      This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
00104
00105   uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
00106                                                      This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
00107
00108   uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
00109                                                      additionally between active edge of SS and first data transaction start in master mode.
00110                                                      This parameter can be a value of @ref SPI_Master_SS_Idleness */
00111
00112   uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
00113                                                      two consecutive data frames in master mode
00114                                                      This parameter can be a value of @ref SPI_Master_InterData_Idleness */
00115
00116   uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode and automatic management
00117                                                      in order to avoid overrun condition.
00118                                                      This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
00119
00120   uint32_t MasterKeepIOState;                 /*!< Control of Alternate function GPIOs state
00121                                                      This parameter can be a value of @ref SPI_Master_Keep_IO_State */
00122
00123   uint32_t IOSwap;                            /*!< Invert MISO/MOSI alternate functions
00124                                                      This parameter can be a value of @ref SPI_IO_Swap */
00125
00126 } SPI_InitTypeDef;
00127
00128 /**
00129   * @brief  HAL SPI State structure definition
00130   */
00131 typedef enum
00132 {
00133   HAL_SPI_STATE_RESET      = 0x00UL,    /*!< Peripheral not Initialized                         */
00134   HAL_SPI_STATE_READY      = 0x01UL,    /*!< Peripheral Initialized and ready for use           */
00135   HAL_SPI_STATE_BUSY       = 0x02UL,    /*!< an internal process is ongoing                     */
00136   HAL_SPI_STATE_BUSY_TX    = 0x03UL,    /*!< Data Transmission process is ongoing               */
00137   HAL_SPI_STATE_BUSY_RX    = 0x04UL,    /*!< Data Reception process is ongoing                  */
00138   HAL_SPI_STATE_BUSY_TX_RX = 0x05UL,    /*!< Data Transmission and Reception process is ongoing */
00139   HAL_SPI_STATE_ERROR      = 0x06UL,    /*!< SPI error state                                    */
00140   HAL_SPI_STATE_ABORT      = 0x07UL     /*!< SPI abort is ongoing                               */
00141 } HAL_SPI_StateTypeDef;
00142
00143 #if defined(USE_SPI_RELOAD_TRANSFER)
00144 /**
00145   * @brief  SPI Reload Structure definition
00146   */
00147 typedef struct
00148 {
00149   uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
00150
00151   uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size to reload           */
00152
00153   uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */
00154
00155   uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size to reload           */
00156
00157   uint32_t                   Requested;                    /*!< SPI reload request                       */
00158
00159 } SPI_ReloadTypeDef;
00160 #endif /* USE_HSPI_RELOAD_TRANSFER */
00161
00162 /**
00163   * @brief  SPI handle Structure definition
00164   */
00165 typedef struct __SPI_HandleTypeDef
00166 {
00167   SPI_TypeDef                *Instance;                    /*!< SPI registers base address               */
00168
00169   SPI_InitTypeDef            Init;                         /*!< SPI communication parameters             */
00170
00171   uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
00172
00173   uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size                     */
00174
00175   __IO uint16_t              TxXferCount;                  /*!< SPI Tx Transfer Counter                  */
00176
00177   uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */
00178
00179   uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size                     */
00180
00181   __IO uint16_t              RxXferCount;                  /*!< SPI Rx Transfer Counter                  */
00182
00183   uint32_t                   CRCSize;                      /*!< SPI CRC size used for the transfer       */
00184
00185   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Rx ISR               */
00186
00187   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Tx ISR               */
00188
00189   DMA_HandleTypeDef          *hdmatx;                      /*!< SPI Tx DMA Handle parameters             */
00190
00191   DMA_HandleTypeDef          *hdmarx;                      /*!< SPI Rx DMA Handle parameters             */
00192
00193   HAL_LockTypeDef            Lock;                         /*!< Locking object                           */
00194
00195   __IO HAL_SPI_StateTypeDef  State;                        /*!< SPI communication state                  */
00196
00197   __IO uint32_t              ErrorCode;                    /*!< SPI Error code                           */
00198
00199 #if defined(USE_SPI_RELOAD_TRANSFER)
00200
00201   SPI_ReloadTypeDef          Reload;                       /*!< SPI reload parameters                    */
00202
00203 #endif /* USE_HSPI_RELOAD_TRANSFER */
00204
00205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00206   void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Tx Completed callback          */
00207   void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Rx Completed callback          */
00208   void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);     /*!< SPI TxRx Completed callback        */
00209   void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Tx Half Completed callback     */
00210   void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Rx Half Completed callback     */
00211   void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback   */
00212   void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);        /*!< SPI Error callback                 */
00213   void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Abort callback                 */
00214   void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Msp Init callback              */
00215   void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Msp DeInit callback            */
00216
00217 #endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
00218 } SPI_HandleTypeDef;
00219
00220 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00221 /**
00222   * @brief  HAL SPI Callback ID enumeration definition
00223   */
00224 typedef enum
00225 {
00226   HAL_SPI_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< SPI Tx Completed callback ID         */
00227   HAL_SPI_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< SPI Rx Completed callback ID         */
00228   HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02UL,    /*!< SPI TxRx Completed callback ID       */
00229   HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< SPI Tx Half Completed callback ID    */
00230   HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< SPI Rx Half Completed callback ID    */
00231   HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05UL,    /*!< SPI TxRx Half Completed callback ID  */
00232   HAL_SPI_ERROR_CB_ID                   = 0x06UL,    /*!< SPI Error callback ID                */
00233   HAL_SPI_ABORT_CB_ID                   = 0x07UL,    /*!< SPI Abort callback ID                */
00234   HAL_SPI_MSPINIT_CB_ID                 = 0x08UL,    /*!< SPI Msp Init callback ID             */
00235   HAL_SPI_MSPDEINIT_CB_ID               = 0x09UL     /*!< SPI Msp DeInit callback ID           */
00236
00237 } HAL_SPI_CallbackIDTypeDef;
00238
00239 /**
00240   * @brief  HAL SPI Callback pointer definition
00241   */
00242 typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
00243
00244 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00245 /**
00246   * @}
00247   */
00248
00249 /* Exported constants --------------------------------------------------------*/
00250
00251 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00252   * @{
00253   */
00254
00255 /** @defgroup SPI_FIFO_Type SPI FIFO Type
00256   * @{
00257   */
00258 #define SPI_LOWEND_FIFO_SIZE                          8UL
00259 #define SPI_HIGHEND_FIFO_SIZE                         16UL
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SPI_Error_Code SPI Error Codes
00265   * @{
00266   */
00267 #define HAL_SPI_ERROR_NONE                            (0x00000000UL)   /*!< No error                               */
00268 #define HAL_SPI_ERROR_MODF                            (0x00000001UL)   /*!< MODF error                             */
00269 #define HAL_SPI_ERROR_CRC                             (0x00000002UL)   /*!< CRC error                              */
00270 #define HAL_SPI_ERROR_OVR                             (0x00000004UL)   /*!< OVR error                              */
00271 #define HAL_SPI_ERROR_FRE                             (0x00000008UL)   /*!< FRE error                              */
00272 #define HAL_SPI_ERROR_DMA                             (0x00000010UL)   /*!< DMA transfer error                     */
00273 #define HAL_SPI_ERROR_FLAG                            (0x00000020UL)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00274 #define HAL_SPI_ERROR_ABORT                           (0x00000040UL)   /*!< Error during SPI Abort procedure       */
00275 #define HAL_SPI_ERROR_UDR                             (0x00000080UL)   /*!< Underrun error                         */
00276 #define HAL_SPI_ERROR_TIMEOUT                         (0x00000100UL)   /*!< Timeout error                          */
00277 #define HAL_SPI_ERROR_UNKNOW                          (0x00000200UL)   /*!< Unknow error                           */
00278 #define HAL_SPI_ERROR_NOT_SUPPORTED                   (0x00000400UL)   /*!< Requested operation not supported      */
00279 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00280 #define HAL_SPI_ERROR_INVALID_CALLBACK                (0x00000800UL)   /*!< Invalid Callback error                 */
00281 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SPI_Mode SPI Mode
00287   * @{
00288   */
00289 #define SPI_MODE_SLAVE                                (0x00000000UL)
00290 #define SPI_MODE_MASTER                               SPI_CFG2_MASTER
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SPI_Direction SPI Direction Mode
00296   * @{
00297   */
00298 #define SPI_DIRECTION_2LINES                          (0x00000000UL)
00299 #define SPI_DIRECTION_2LINES_TXONLY                   SPI_CFG2_COMM_0
00300 #define SPI_DIRECTION_2LINES_RXONLY                   SPI_CFG2_COMM_1
00301 #define SPI_DIRECTION_1LINE                           SPI_CFG2_COMM
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup SPI_Data_Size SPI Data Size
00307   * @{
00308   */
00309 #define SPI_DATASIZE_4BIT                             (0x00000003UL)
00310 #define SPI_DATASIZE_5BIT                             (0x00000004UL)
00311 #define SPI_DATASIZE_6BIT                             (0x00000005UL)
00312 #define SPI_DATASIZE_7BIT                             (0x00000006UL)
00313 #define SPI_DATASIZE_8BIT                             (0x00000007UL)
00314 #define SPI_DATASIZE_9BIT                             (0x00000008UL)
00315 #define SPI_DATASIZE_10BIT                            (0x00000009UL)
00316 #define SPI_DATASIZE_11BIT                            (0x0000000AUL)
00317 #define SPI_DATASIZE_12BIT                            (0x0000000BUL)
00318 #define SPI_DATASIZE_13BIT                            (0x0000000CUL)
00319 #define SPI_DATASIZE_14BIT                            (0x0000000DUL)
00320 #define SPI_DATASIZE_15BIT                            (0x0000000EUL)
00321 #define SPI_DATASIZE_16BIT                            (0x0000000FUL)
00322 #define SPI_DATASIZE_17BIT                            (0x00000010UL)
00323 #define SPI_DATASIZE_18BIT                            (0x00000011UL)
00324 #define SPI_DATASIZE_19BIT                            (0x00000012UL)
00325 #define SPI_DATASIZE_20BIT                            (0x00000013UL)
00326 #define SPI_DATASIZE_21BIT                            (0x00000014UL)
00327 #define SPI_DATASIZE_22BIT                            (0x00000015UL)
00328 #define SPI_DATASIZE_23BIT                            (0x00000016UL)
00329 #define SPI_DATASIZE_24BIT                            (0x00000017UL)
00330 #define SPI_DATASIZE_25BIT                            (0x00000018UL)
00331 #define SPI_DATASIZE_26BIT                            (0x00000019UL)
00332 #define SPI_DATASIZE_27BIT                            (0x0000001AUL)
00333 #define SPI_DATASIZE_28BIT                            (0x0000001BUL)
00334 #define SPI_DATASIZE_29BIT                            (0x0000001CUL)
00335 #define SPI_DATASIZE_30BIT                            (0x0000001DUL)
00336 #define SPI_DATASIZE_31BIT                            (0x0000001EUL)
00337 #define SPI_DATASIZE_32BIT                            (0x0000001FUL)
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00343   * @{
00344   */
00345 #define SPI_POLARITY_LOW                              (0x00000000UL)
00346 #define SPI_POLARITY_HIGH                             SPI_CFG2_CPOL
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00352   * @{
00353   */
00354 #define SPI_PHASE_1EDGE                               (0x00000000UL)
00355 #define SPI_PHASE_2EDGE                               SPI_CFG2_CPHA
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
00361   * @{
00362   */
00363 #define SPI_NSS_SOFT                                  SPI_CFG2_SSM
00364 #define SPI_NSS_HARD_INPUT                            (0x00000000UL)
00365 #define SPI_NSS_HARD_OUTPUT                           SPI_CFG2_SSOE
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00371   * @{
00372   */
00373 #define SPI_NSS_PULSE_DISABLE                         (0x00000000UL)
00374 #define SPI_NSS_PULSE_ENABLE                          SPI_CFG2_SSOM
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00380   * @{
00381   */
00382 #define SPI_BAUDRATEPRESCALER_2                       (0x00000000UL)
00383 #define SPI_BAUDRATEPRESCALER_4                       (0x10000000UL)
00384 #define SPI_BAUDRATEPRESCALER_8                       (0x20000000UL)
00385 #define SPI_BAUDRATEPRESCALER_16                      (0x30000000UL)
00386 #define SPI_BAUDRATEPRESCALER_32                      (0x40000000UL)
00387 #define SPI_BAUDRATEPRESCALER_64                      (0x50000000UL)
00388 #define SPI_BAUDRATEPRESCALER_128                     (0x60000000UL)
00389 #define SPI_BAUDRATEPRESCALER_256                     (0x70000000UL)
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
00395   * @{
00396   */
00397 #define SPI_FIRSTBIT_MSB                              (0x00000000UL)
00398 #define SPI_FIRSTBIT_LSB                              SPI_CFG2_LSBFRST
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup SPI_TI_Mode SPI TI Mode
00404   * @{
00405   */
00406 #define SPI_TIMODE_DISABLE                            (0x00000000UL)
00407 #define SPI_TIMODE_ENABLE                             SPI_CFG2_SP_0
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00413   * @{
00414   */
00415 #define SPI_CRCCALCULATION_DISABLE                    (0x00000000UL)
00416 #define SPI_CRCCALCULATION_ENABLE                     SPI_CFG1_CRCEN
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup SPI_CRC_length SPI CRC Length
00422   * @{
00423   */
00424 #define SPI_CRC_LENGTH_DATASIZE                       (0x00000000UL)
00425 #define SPI_CRC_LENGTH_4BIT                           (0x00030000UL)
00426 #define SPI_CRC_LENGTH_5BIT                           (0x00040000UL)
00427 #define SPI_CRC_LENGTH_6BIT                           (0x00050000UL)
00428 #define SPI_CRC_LENGTH_7BIT                           (0x00060000UL)
00429 #define SPI_CRC_LENGTH_8BIT                           (0x00070000UL)
00430 #define SPI_CRC_LENGTH_9BIT                           (0x00080000UL)
00431 #define SPI_CRC_LENGTH_10BIT                          (0x00090000UL)
00432 #define SPI_CRC_LENGTH_11BIT                          (0x000A0000UL)
00433 #define SPI_CRC_LENGTH_12BIT                          (0x000B0000UL)
00434 #define SPI_CRC_LENGTH_13BIT                          (0x000C0000UL)
00435 #define SPI_CRC_LENGTH_14BIT                          (0x000D0000UL)
00436 #define SPI_CRC_LENGTH_15BIT                          (0x000E0000UL)
00437 #define SPI_CRC_LENGTH_16BIT                          (0x000F0000UL)
00438 #define SPI_CRC_LENGTH_17BIT                          (0x00100000UL)
00439 #define SPI_CRC_LENGTH_18BIT                          (0x00110000UL)
00440 #define SPI_CRC_LENGTH_19BIT                          (0x00120000UL)
00441 #define SPI_CRC_LENGTH_20BIT                          (0x00130000UL)
00442 #define SPI_CRC_LENGTH_21BIT                          (0x00140000UL)
00443 #define SPI_CRC_LENGTH_22BIT                          (0x00150000UL)
00444 #define SPI_CRC_LENGTH_23BIT                          (0x00160000UL)
00445 #define SPI_CRC_LENGTH_24BIT                          (0x00170000UL)
00446 #define SPI_CRC_LENGTH_25BIT                          (0x00180000UL)
00447 #define SPI_CRC_LENGTH_26BIT                          (0x00190000UL)
00448 #define SPI_CRC_LENGTH_27BIT                          (0x001A0000UL)
00449 #define SPI_CRC_LENGTH_28BIT                          (0x001B0000UL)
00450 #define SPI_CRC_LENGTH_29BIT                          (0x001C0000UL)
00451 #define SPI_CRC_LENGTH_30BIT                          (0x001D0000UL)
00452 #define SPI_CRC_LENGTH_31BIT                          (0x001E0000UL)
00453 #define SPI_CRC_LENGTH_32BIT                          (0x001F0000UL)
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
00459   * @{
00460   */
00461 #define SPI_FIFO_THRESHOLD_01DATA                     (0x00000000UL)
00462 #define SPI_FIFO_THRESHOLD_02DATA                     (0x00000020UL)
00463 #define SPI_FIFO_THRESHOLD_03DATA                     (0x00000040UL)
00464 #define SPI_FIFO_THRESHOLD_04DATA                     (0x00000060UL)
00465 #define SPI_FIFO_THRESHOLD_05DATA                     (0x00000080UL)
00466 #define SPI_FIFO_THRESHOLD_06DATA                     (0x000000A0UL)
00467 #define SPI_FIFO_THRESHOLD_07DATA                     (0x000000C0UL)
00468 #define SPI_FIFO_THRESHOLD_08DATA                     (0x000000E0UL)
00469 #define SPI_FIFO_THRESHOLD_09DATA                     (0x00000100UL)
00470 #define SPI_FIFO_THRESHOLD_10DATA                     (0x00000120UL)
00471 #define SPI_FIFO_THRESHOLD_11DATA                     (0x00000140UL)
00472 #define SPI_FIFO_THRESHOLD_12DATA                     (0x00000160UL)
00473 #define SPI_FIFO_THRESHOLD_13DATA                     (0x00000180UL)
00474 #define SPI_FIFO_THRESHOLD_14DATA                     (0x000001A0UL)
00475 #define SPI_FIFO_THRESHOLD_15DATA                     (0x000001C0UL)
00476 #define SPI_FIFO_THRESHOLD_16DATA                     (0x000001E0UL)
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
00482   * @{
00483   */
00484 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN       (0x00000000UL)
00485 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN        (0x00000001UL)
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity
00491   * @{
00492   */
00493 #define SPI_NSS_POLARITY_LOW                          (0x00000000UL)
00494 #define SPI_NSS_POLARITY_HIGH                          SPI_CFG2_SSIOP
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup SPI_Master_Keep_IO_State Keep IO State
00500   * @{
00501   */
00502 #define SPI_MASTER_KEEP_IO_STATE_DISABLE              (0x00000000UL)
00503 #define SPI_MASTER_KEEP_IO_STATE_ENABLE               SPI_CFG2_AFCNTR
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup SPI_IO_Swap Control SPI IO Swap
00509   * @{
00510   */
00511 #define SPI_IO_SWAP_DISABLE                           (0x00000000UL)
00512 #define SPI_IO_SWAP_ENABLE                            SPI_CFG2_IOSWP
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
00518   * @{
00519   */
00520 #define SPI_MASTER_SS_IDLENESS_00CYCLE                (0x00000000UL)
00521 #define SPI_MASTER_SS_IDLENESS_01CYCLE                (0x00000001UL)
00522 #define SPI_MASTER_SS_IDLENESS_02CYCLE                (0x00000002UL)
00523 #define SPI_MASTER_SS_IDLENESS_03CYCLE                (0x00000003UL)
00524 #define SPI_MASTER_SS_IDLENESS_04CYCLE                (0x00000004UL)
00525 #define SPI_MASTER_SS_IDLENESS_05CYCLE                (0x00000005UL)
00526 #define SPI_MASTER_SS_IDLENESS_06CYCLE                (0x00000006UL)
00527 #define SPI_MASTER_SS_IDLENESS_07CYCLE                (0x00000007UL)
00528 #define SPI_MASTER_SS_IDLENESS_08CYCLE                (0x00000008UL)
00529 #define SPI_MASTER_SS_IDLENESS_09CYCLE                (0x00000009UL)
00530 #define SPI_MASTER_SS_IDLENESS_10CYCLE                (0x0000000AUL)
00531 #define SPI_MASTER_SS_IDLENESS_11CYCLE                (0x0000000BUL)
00532 #define SPI_MASTER_SS_IDLENESS_12CYCLE                (0x0000000CUL)
00533 #define SPI_MASTER_SS_IDLENESS_13CYCLE                (0x0000000DUL)
00534 #define SPI_MASTER_SS_IDLENESS_14CYCLE                (0x0000000EUL)
00535 #define SPI_MASTER_SS_IDLENESS_15CYCLE                (0x0000000FUL)
00536 /**
00537   * @}
00538   */
00539
00540 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
00541   * @{
00542   */
00543 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE         (0x00000000UL)
00544 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE         (0x00000010UL)
00545 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE         (0x00000020UL)
00546 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE         (0x00000030UL)
00547 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE         (0x00000040UL)
00548 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE         (0x00000050UL)
00549 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE         (0x00000060UL)
00550 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE         (0x00000070UL)
00551 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE         (0x00000080UL)
00552 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE         (0x00000090UL)
00553 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE         (0x000000A0UL)
00554 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE         (0x000000B0UL)
00555 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE         (0x000000C0UL)
00556 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE         (0x000000D0UL)
00557 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE         (0x000000E0UL)
00558 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE         (0x000000F0UL)
00559 /**
00560   * @}
00561   */
00562
00563 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
00564   * @{
00565   */
00566 #define SPI_MASTER_RX_AUTOSUSP_DISABLE                (0x00000000UL)
00567 #define SPI_MASTER_RX_AUTOSUSP_ENABLE                 SPI_CR1_MASRX
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup SPI_Underrun_Detection SPI Underrun Detection
00573   * @{
00574   */
00575 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME          (0x00000000UL)
00576 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME            SPI_CFG1_UDRDET_0
00577 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS          SPI_CFG1_UDRDET_1
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
00583   * @{
00584   */
00585 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN           (0x00000000UL)
00586 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED              SPI_CFG1_UDRCFG_0
00587 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED           SPI_CFG1_UDRCFG_1
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00593   * @{
00594   */
00595 #define SPI_IT_RXP                      SPI_IER_RXPIE
00596 #define SPI_IT_TXP                      SPI_IER_TXPIE
00597 #define SPI_IT_DXP                      SPI_IER_DXPIE
00598 #define SPI_IT_EOT                      SPI_IER_EOTIE
00599 #define SPI_IT_TXTF                     SPI_IER_TXTFIE
00600 #define SPI_IT_UDR                      SPI_IER_UDRIE
00601 #define SPI_IT_OVR                      SPI_IER_OVRIE
00602 #define SPI_IT_CRCERR                   SPI_IER_CRCEIE
00603 #define SPI_IT_FRE                      SPI_IER_TIFREIE
00604 #define SPI_IT_MODF                     SPI_IER_MODFIE
00605 #define SPI_IT_TSERF                    SPI_IER_TSERFIE
00606 #define SPI_IT_ERR                      (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup SPI_Flags_definition SPI Flags Definition
00612   * @{
00613   */
00614 #define SPI_FLAG_RXP                    SPI_SR_RXP     /* SPI status flag : Rx-Packet available flag                 */
00615 #define SPI_FLAG_TXP                    SPI_SR_TXP     /* SPI status flag : Tx-Packet space available flag           */
00616 #define SPI_FLAG_DXP                    SPI_SR_DXP     /* SPI status flag : Duplex Packet flag                       */
00617 #define SPI_FLAG_EOT                    SPI_SR_EOT     /* SPI status flag : End of transfer flag                     */
00618 #define SPI_FLAG_TXTF                   SPI_SR_TXTF    /* SPI status flag : Transmission Transfer Filled flag        */
00619 #define SPI_FLAG_UDR                    SPI_SR_UDR     /* SPI Error flag  : Underrun flag                            */
00620 #define SPI_FLAG_OVR                    SPI_SR_OVR     /* SPI Error flag  : Overrun flag                             */
00621 #define SPI_FLAG_CRCERR                 SPI_SR_CRCE    /* SPI Error flag  : CRC error flag                           */
00622 #define SPI_FLAG_FRE                    SPI_SR_TIFRE   /* SPI Error flag  : TI mode frame format error flag          */
00623 #define SPI_FLAG_MODF                   SPI_SR_MODF    /* SPI Error flag  : Mode fault flag                          */
00624 #define SPI_FLAG_TSERF                  SPI_SR_TSERF   /* SPI status flag : Additional number of data reloaded flag  */
00625 #define SPI_FLAG_SUSP                   SPI_SR_SUSP    /* SPI status flag : Transfer suspend complete flag           */
00626 #define SPI_FLAG_TXC                    SPI_SR_TXC     /* SPI status flag : TxFIFO transmission complete flag        */
00627 #define SPI_FLAG_FRLVL                  SPI_SR_RXPLVL  /* SPI status flag : Fifo reception level flag                */
00628 #define SPI_FLAG_RXWNE                  SPI_SR_RXWNE   /* SPI status flag : RxFIFO word not empty flag               */
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00634   * @{
00635   */
00636 #define SPI_RX_FIFO_0PACKET                           (0x00000000UL)                      /* 0 or multiple of 4 packets available in the RxFIFO */
00637 #define SPI_RX_FIFO_1PACKET                           (SPI_SR_RXPLVL_0)
00638 #define SPI_RX_FIFO_2PACKET                           (SPI_SR_RXPLVL_1)
00639 #define SPI_RX_FIFO_3PACKET                           (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
00640 /**
00641   * @}
00642   */
00643
00644 /**
00645   * @}
00646   */
00647
00648 /* Exported macros -----------------------------------------------------------*/
00649 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00650   * @{
00651   */
00652
00653 /** @brief  Reset SPI handle state.
00654   * @param  __HANDLE__: specifies the SPI Handle.
00655   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00656   * @retval None
00657   */
00658 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
00659 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)   do{                                                  \
00660                                                        (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
00661                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00662                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00663                                                      } while(0)
00664 #else
00665 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00666 #endif
00667
00668 /** @brief  Enable the specified SPI interrupts.
00669   * @param  __HANDLE__: specifies the SPI Handle.
00670   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00671   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00672   *         This parameter can be one of the following values:
00673   *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
00674   *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
00675   *            @arg SPI_IT_DXP    : Duplex Packet interrupt
00676   *            @arg SPI_IT_EOT    : End of transfer interrupt
00677   *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
00678   *            @arg SPI_IT_UDR    : Underrun interrupt
00679   *            @arg SPI_IT_OVR    : Overrun  interrupt
00680   *            @arg SPI_IT_CRCERR : CRC error interrupt
00681   *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
00682   *            @arg SPI_IT_MODF   : Mode fault interrupt
00683   *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt
00684   *            @arg SPI_IT_ERR    : Error interrupt
00685   * @retval None
00686   */
00687 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00688
00689 /** @brief  Disable the specified SPI interrupts.
00690   * @param  __HANDLE__: specifies the SPI Handle.
00691   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00692   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00693   *         This parameter can be one of the following values:
00694   *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
00695   *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
00696   *            @arg SPI_IT_DXP    : Duplex Packet interrupt
00697   *            @arg SPI_IT_EOT    : End of transfer interrupt
00698   *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
00699   *            @arg SPI_IT_UDR    : Underrun interrupt
00700   *            @arg SPI_IT_OVR    : Overrun  interrupt
00701   *            @arg SPI_IT_CRCERR : CRC error interrupt
00702   *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
00703   *            @arg SPI_IT_MODF   : Mode fault interrupt
00704   *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt
00705   *            @arg SPI_IT_ERR    : Error interrupt
00706   * @retval None
00707   */
00708 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00709
00710 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00711   * @param  __HANDLE__: specifies the SPI Handle.
00712   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00713   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
00714   *          This parameter can be one of the following values:
00715   *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
00716   *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
00717   *            @arg SPI_IT_DXP    : Duplex Packet interrupt
00718   *            @arg SPI_IT_EOT    : End of transfer interrupt
00719   *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
00720   *            @arg SPI_IT_UDR    : Underrun interrupt
00721   *            @arg SPI_IT_OVR    : Overrun  interrupt
00722   *            @arg SPI_IT_CRCERR : CRC error interrupt
00723   *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
00724   *            @arg SPI_IT_MODF   : Mode fault interrupt
00725   *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt
00726   *            @arg SPI_IT_ERR    : Error interrupt
00727   * @retval The new state of __IT__ (TRUE or FALSE).
00728   */
00729 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00730
00731 /** @brief  Check whether the specified SPI flag is set or not.
00732   * @param  __HANDLE__: specifies the SPI Handle.
00733   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00734   * @param  __FLAG__: specifies the flag to check.
00735   *         This parameter can be one of the following values:
00736   *            @arg SPI_FLAG_RXP    : Rx-Packet available flag
00737   *            @arg SPI_FLAG_TXP    : Tx-Packet space available flag
00738   *            @arg SPI_FLAG_DXP    : Duplex Packet flag
00739   *            @arg SPI_FLAG_EOT    : End of transfer flag
00740   *            @arg SPI_FLAG_TXTF   : Transmission Transfer Filled flag
00741   *            @arg SPI_FLAG_UDR    : Underrun flag
00742   *            @arg SPI_FLAG_OVR    : Overrun flag
00743   *            @arg SPI_FLAG_CRCERR : CRC error flag
00744   *            @arg SPI_FLAG_FRE    : TI mode frame format error flag
00745   *            @arg SPI_FLAG_MODF   : Mode fault flag
00746   *            @arg SPI_FLAG_TSERF  : Additional number of data reloaded flag
00747   *            @arg SPI_FLAG_SUSP   : Transfer suspend complete flag
00748   *            @arg SPI_FLAG_TXC    : TxFIFO transmission complete flag
00749   *            @arg SPI_FLAG_FRLVL  : Fifo reception level flag
00750   *            @arg SPI_FLAG_RXWNE  : RxFIFO word not empty flag
00751   * @retval The new state of __FLAG__ (TRUE or FALSE).
00752   */
00753 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00754
00755 /** @brief  Clear the SPI CRCERR pending flag.
00756   * @param  __HANDLE__: specifies the SPI Handle.
00757   * @retval None
00758   */
00759 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
00760
00761 /** @brief  Clear the SPI MODF pending flag.
00762   * @param  __HANDLE__: specifies the SPI Handle.
00763   * @retval None
00764   */
00765 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
00766
00767 /** @brief  Clear the SPI OVR pending flag.
00768   * @param  __HANDLE__: specifies the SPI Handle.
00769   * @retval None
00770   */
00771 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
00772
00773 /** @brief  Clear the SPI FRE pending flag.
00774   * @param  __HANDLE__: specifies the SPI Handle.
00775   * @retval None
00776   */
00777 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
00778
00779 /** @brief  Clear the SPI UDR pending flag.
00780   * @param  __HANDLE__: specifies the SPI Handle.
00781   * @retval None
00782   */
00783 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
00784
00785 /** @brief  Clear the SPI EOT pending flag.
00786   * @param  __HANDLE__: specifies the SPI Handle.
00787   * @retval None
00788   */
00789 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
00790
00791 /** @brief  Clear the SPI UDR pending flag.
00792   * @param  __HANDLE__: specifies the SPI Handle.
00793   * @retval None
00794   */
00795 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
00796
00797 /** @brief  Clear the SPI SUSP pending flag.
00798   * @param  __HANDLE__: specifies the SPI Handle.
00799   * @retval None
00800   */
00801 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
00802
00803 /** @brief  Clear the SPI TSERF pending flag.
00804   * @param  __HANDLE__: specifies the SPI Handle.
00805   * @retval None
00806   */
00807 #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
00808
00809 /** @brief  Enable the SPI peripheral.
00810   * @param  __HANDLE__: specifies the SPI Handle.
00811   * @retval None
00812   */
00813 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
00814
00815 /** @brief  Disable the SPI peripheral.
00816   * @param  __HANDLE__: specifies the SPI Handle.
00817   * @retval None
00818   */
00819 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
00820 /**
00821   * @}
00822   */
00823
00824
00825 /* Include SPI HAL Extension module */
00826 #include "stm32h7xx_hal_spi_ex.h"
00827
00828
00829 /* Exported functions --------------------------------------------------------*/
00830 /** @addtogroup SPI_Exported_Functions
00831   * @{
00832   */
00833
00834 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00835   * @{
00836   */
00837 /* Initialization/de-initialization functions  ********************************/
00838 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00839 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00840 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00841 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00842
00843 /* Callbacks Register/UnRegister functions  ***********************************/
00844 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00845 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
00846 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
00847 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00848 /**
00849   * @}
00850   */
00851
00852 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
00853   * @{
00854   */
00855 /* I/O operation functions  ***************************************************/
00856 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00857 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00858 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00859                                           uint32_t Timeout);
00860 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00861 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00862 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00863
00864 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00865 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00866 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00867
00868 #if defined(USE_SPI_RELOAD_TRANSFER)
00869 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00870 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00871 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00872 #endif /* USE_HSPI_RELOAD_TRANSFER */
00873
00874 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00875 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00876 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00877
00878 /* Transfer Abort functions */
00879 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00880 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00881
00882 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00883 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00884 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00885 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00886 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00887 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00888 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00889 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00890 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00891 /**
00892   * @}
00893   */
00894
00895 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
00896   * @{
00897   */
00898
00899 /* Peripheral State and Error functions ***************************************/
00900 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00901 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00902 /**
00903   * @}
00904   */
00905
00906 /**
00907   * @}
00908   */
00909
00910 /* Private macros ------------------------------------------------------------*/
00911 /** @defgroup SPI_Private_Macros SPI Private Macros
00912   * @{
00913   */
00914
00915 /** @brief  Set the SPI transmit-only mode.
00916   * @param  __HANDLE__: specifies the SPI Handle.
00917   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00918   * @retval None
00919   */
00920 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
00921
00922 /** @brief  Set the SPI receive-only mode.
00923   * @param  __HANDLE__: specifies the SPI Handle.
00924   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00925   * @retval None
00926   */
00927 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
00928
00929 #define IS_SPI_MODE(MODE)                          (((MODE) == SPI_MODE_SLAVE) || \
00930                                                     ((MODE) == SPI_MODE_MASTER))
00931
00932 #define IS_SPI_DIRECTION(MODE)                     (((MODE) == SPI_DIRECTION_2LINES)        || \
00933                                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
00934                                                     ((MODE) == SPI_DIRECTION_1LINE)         || \
00935                                                     ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
00936
00937 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00938
00939 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (                         \
00940                                                     ((MODE) == SPI_DIRECTION_2LINES)|| \
00941                                                     ((MODE) == SPI_DIRECTION_1LINE) || \
00942                                                     ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
00943
00944 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (                         \
00945                                                     ((MODE) == SPI_DIRECTION_2LINES)|| \
00946                                                     ((MODE) == SPI_DIRECTION_1LINE) || \
00947                                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
00948
00949 #define IS_SPI_DATASIZE(DATASIZE)                  (((DATASIZE) == SPI_DATASIZE_32BIT) || \
00950                                                     ((DATASIZE) == SPI_DATASIZE_31BIT) || \
00951                                                     ((DATASIZE) == SPI_DATASIZE_30BIT) || \
00952                                                     ((DATASIZE) == SPI_DATASIZE_29BIT) || \
00953                                                     ((DATASIZE) == SPI_DATASIZE_28BIT) || \
00954                                                     ((DATASIZE) == SPI_DATASIZE_27BIT) || \
00955                                                     ((DATASIZE) == SPI_DATASIZE_26BIT) || \
00956                                                     ((DATASIZE) == SPI_DATASIZE_25BIT) || \
00957                                                     ((DATASIZE) == SPI_DATASIZE_24BIT) || \
00958                                                     ((DATASIZE) == SPI_DATASIZE_23BIT) || \
00959                                                     ((DATASIZE) == SPI_DATASIZE_22BIT) || \
00960                                                     ((DATASIZE) == SPI_DATASIZE_21BIT) || \
00961                                                     ((DATASIZE) == SPI_DATASIZE_20BIT) || \
00962                                                     ((DATASIZE) == SPI_DATASIZE_22BIT) || \
00963                                                     ((DATASIZE) == SPI_DATASIZE_19BIT) || \
00964                                                     ((DATASIZE) == SPI_DATASIZE_18BIT) || \
00965                                                     ((DATASIZE) == SPI_DATASIZE_17BIT) || \
00966                                                     ((DATASIZE) == SPI_DATASIZE_16BIT) || \
00967                                                     ((DATASIZE) == SPI_DATASIZE_15BIT) || \
00968                                                     ((DATASIZE) == SPI_DATASIZE_14BIT) || \
00969                                                     ((DATASIZE) == SPI_DATASIZE_13BIT) || \
00970                                                     ((DATASIZE) == SPI_DATASIZE_12BIT) || \
00971                                                     ((DATASIZE) == SPI_DATASIZE_11BIT) || \
00972                                                     ((DATASIZE) == SPI_DATASIZE_10BIT) || \
00973                                                     ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
00974                                                     ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
00975                                                     ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
00976                                                     ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
00977                                                     ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
00978                                                     ((DATASIZE) == SPI_DATASIZE_4BIT))
00979
00980 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD)            (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
00981                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
00982                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
00983                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
00984                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
00985                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
00986                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
00987                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
00988                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
00989                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
00990                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
00991                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
00992                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
00993                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
00994                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
00995                                                     ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
00996
00997 #define IS_SPI_CPOL(CPOL)                          (((CPOL) == SPI_POLARITY_LOW) || \
00998                                                     ((CPOL) == SPI_POLARITY_HIGH))
00999
01000 #define IS_SPI_CPHA(CPHA)                          (((CPHA) == SPI_PHASE_1EDGE) || \
01001                                                     ((CPHA) == SPI_PHASE_2EDGE))
01002
01003 #define IS_SPI_NSS(NSS)                            (((NSS) == SPI_NSS_SOFT)       || \
01004                                                     ((NSS) == SPI_NSS_HARD_INPUT) || \
01005                                                     ((NSS) == SPI_NSS_HARD_OUTPUT))
01006
01007 #define IS_SPI_NSSP(NSSP)                          (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
01008                                                     ((NSSP) == SPI_NSS_PULSE_DISABLE))
01009
01010 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)       (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
01011                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
01012                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
01013                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
01014                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
01015                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
01016                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
01017                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
01018
01019 #define IS_SPI_FIRST_BIT(BIT)                      (((BIT) == SPI_FIRSTBIT_MSB) || \
01020                                                     ((BIT) == SPI_FIRSTBIT_LSB))
01021
01022 #define IS_SPI_TIMODE(MODE)                        (((MODE) == SPI_TIMODE_DISABLE) || \
01023                                                     ((MODE) == SPI_TIMODE_ENABLE))
01024
01025 #define IS_SPI_CRC_CALCULATION(CALCULATION)        (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
01026                                                     ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
01027
01028 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
01029                                                     ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
01030
01031 #define IS_SPI_CRC_LENGTH(LENGTH)                  (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
01032                                                     ((LENGTH) == SPI_CRC_LENGTH_32BIT)    || \
01033                                                     ((LENGTH) == SPI_CRC_LENGTH_31BIT)    || \
01034                                                     ((LENGTH) == SPI_CRC_LENGTH_30BIT)    || \
01035                                                     ((LENGTH) == SPI_CRC_LENGTH_29BIT)    || \
01036                                                     ((LENGTH) == SPI_CRC_LENGTH_28BIT)    || \
01037                                                     ((LENGTH) == SPI_CRC_LENGTH_27BIT)    || \
01038                                                     ((LENGTH) == SPI_CRC_LENGTH_26BIT)    || \
01039                                                     ((LENGTH) == SPI_CRC_LENGTH_25BIT)    || \
01040                                                     ((LENGTH) == SPI_CRC_LENGTH_24BIT)    || \
01041                                                     ((LENGTH) == SPI_CRC_LENGTH_23BIT)    || \
01042                                                     ((LENGTH) == SPI_CRC_LENGTH_22BIT)    || \
01043                                                     ((LENGTH) == SPI_CRC_LENGTH_21BIT)    || \
01044                                                     ((LENGTH) == SPI_CRC_LENGTH_20BIT)    || \
01045                                                     ((LENGTH) == SPI_CRC_LENGTH_19BIT)    || \
01046                                                     ((LENGTH) == SPI_CRC_LENGTH_18BIT)    || \
01047                                                     ((LENGTH) == SPI_CRC_LENGTH_17BIT)    || \
01048                                                     ((LENGTH) == SPI_CRC_LENGTH_16BIT)    || \
01049                                                     ((LENGTH) == SPI_CRC_LENGTH_15BIT)    || \
01050                                                     ((LENGTH) == SPI_CRC_LENGTH_14BIT)    || \
01051                                                     ((LENGTH) == SPI_CRC_LENGTH_13BIT)    || \
01052                                                     ((LENGTH) == SPI_CRC_LENGTH_12BIT)    || \
01053                                                     ((LENGTH) == SPI_CRC_LENGTH_11BIT)    || \
01054                                                     ((LENGTH) == SPI_CRC_LENGTH_10BIT)    || \
01055                                                     ((LENGTH) == SPI_CRC_LENGTH_9BIT)     || \
01056                                                     ((LENGTH) == SPI_CRC_LENGTH_8BIT)     || \
01057                                                     ((LENGTH) == SPI_CRC_LENGTH_7BIT)     || \
01058                                                     ((LENGTH) == SPI_CRC_LENGTH_6BIT)     || \
01059                                                     ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
01060                                                     ((LENGTH) == SPI_CRC_LENGTH_4BIT))
01061
01062 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)           ((POLYNOMIAL) >= 0x1UL)
01063
01064 #define IS_SPI_UNDERRUN_DETECTION(MODE)            (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
01065                                                     ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \
01066                                                     ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
01067
01068 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)            (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
01069                                                     ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \
01070                                                     ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
01071 /**
01072   * @}
01073   */
01074
01075 /**
01076   * @}
01077   */
01078
01079 /**
01080   * @}
01081   */
01082
01083 #ifdef __cplusplus
01084 }
01085 #endif
01086
01087 #endif /* STM32H7xx_HAL_SPI_H */
01088
01089 /**
01090   * @}
01091   */
01092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi_ex.c Source File

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stm32h7xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          SPI peripheral extended functionalities :
00008   *           + IO operation functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00015   * All rights reserved.</center></h2>
00016   *
00017   * This software component is licensed by ST under BSD 3-Clause license,
00018   * the "License"; You may not use this file except in compliance with the
00019   * License. You may obtain a copy of the License at:
00020   *                        opensource.org/licenses/BSD-3-Clause
00021   *
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32h7xx_hal.h"
00027
00028 /** @addtogroup STM32H7xx_HAL_Driver
00029   * @{
00030   */
00031
00032 /** @defgroup SPIEx SPIEx
00033   * @brief SPI Extended HAL module driver
00034   * @{
00035   */
00036 #ifdef HAL_SPI_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private defines -----------------------------------------------------------*/
00040 /* Private macros ------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Exported functions --------------------------------------------------------*/
00044
00045 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00046   * @{
00047   */
00048
00049 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00050   *  @brief   Data transfers functions
00051   *
00052 @verbatim
00053   ==============================================================================
00054                       ##### IO operation functions #####
00055  ===============================================================================
00056  [..]
00057     This subsection provides a set of extended functions to manage the SPI
00058     data transfers.
00059
00060     (#) SPIEx function:
00061         (++) HAL_SPIEx_FlushRxFifo()
00062         (++) HAL_SPIEx_FlushRxFifo()
00063         (++) HAL_SPIEx_EnableLockConfiguration()
00064         (++) HAL_SPIEx_ConfigureUnderrun()
00065
00066 @endverbatim
00067   * @{
00068   */
00069
00070 /**
00071   * @brief Flush the RX fifo.
00072   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00073   *               the configuration information for the specified SPI module.
00074   * @retval HAL status
00075   */
00076 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00077 {
00078   uint8_t  count  = 0;
00079   uint32_t itflag = hspi->Instance->SR;
00080   __IO uint32_t tmpreg;
00081
00082   while (((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) !=  0UL))
00083   {
00084     count += (uint8_t)4UL;
00085     tmpreg = hspi->Instance->RXDR;
00086     UNUSED(tmpreg); /* To avoid GCC warning */
00087
00088     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00089     {
00090       if (count > SPI_HIGHEND_FIFO_SIZE)
00091       {
00092         return HAL_TIMEOUT;
00093       }
00094     }
00095     else
00096     {
00097       if (count > SPI_LOWEND_FIFO_SIZE)
00098       {
00099         return HAL_TIMEOUT;
00100       }
00101     }
00102   }
00103   return HAL_OK;
00104 }
00105
00106
00107 /**
00108   * @brief  Enable the Lock for the AF configuration of associated IOs
00109   *         and write protect the Content of Configuration register 2
00110   *         when SPI is enabled
00111   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00112   *               the configuration information for SPI module.
00113   * @retval None
00114   */
00115 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
00116 {
00117   HAL_StatusTypeDef errorcode = HAL_OK;
00118
00119   /* Process Locked */
00120   __HAL_LOCK(hspi);
00121
00122   if (hspi->State != HAL_SPI_STATE_READY)
00123   {
00124     errorcode = HAL_BUSY;
00125     hspi->State = HAL_SPI_STATE_READY;
00126     /* Process Unlocked */
00127     __HAL_UNLOCK(hspi);
00128     return errorcode;
00129   }
00130
00131   /* Check if the SPI is disabled to edit IOLOCK bit */
00132   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00133   {
00134     SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
00135   }
00136   else
00137   {
00138     /* Disable SPI peripheral */
00139     __HAL_SPI_DISABLE(hspi);
00140
00141     SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
00142
00143     /* Enable SPI peripheral */
00144     __HAL_SPI_ENABLE(hspi);
00145   }
00146
00147   hspi->State = HAL_SPI_STATE_READY;
00148   /* Process Unlocked */
00149   __HAL_UNLOCK(hspi);
00150   return errorcode;
00151 }
00152
00153 /**
00154   * @brief  Configure the UNDERRUN condition and behavior of slave transmitter.
00155   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00156   *               the configuration information for SPI module.
00157   * @param  UnderrunDetection : Detection of underrun condition at slave transmitter
00158   *                             This parameter can be a value of @ref SPI_Underrun_Detection.
00159   * @param  UnderrunBehaviour : Behavior of slave transmitter at underrun condition
00160   *                             This parameter can be a value of @ref SPI_Underrun_Behaviour.
00161   * @retval None
00162   */
00163 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
00164 {
00165   HAL_StatusTypeDef errorcode = HAL_OK;
00166
00167   /* Process Locked */
00168   __HAL_LOCK(hspi);
00169
00170   /* Check State and Insure that Underrun configuration is managed only by Salve */
00171   if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
00172   {
00173     errorcode = HAL_BUSY;
00174     hspi->State = HAL_SPI_STATE_READY;
00175     /* Process Unlocked */
00176     __HAL_UNLOCK(hspi);
00177     return errorcode;
00178   }
00179
00180   /* Check the parameters */
00181   assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
00182   assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
00183
00184   /* Check if the SPI is disabled to edit CFG1 register */
00185   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00186   {
00187     /* Configure Underrun fields */
00188     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
00189     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
00190   }
00191   else
00192   {
00193     /* Disable SPI peripheral */
00194     __HAL_SPI_DISABLE(hspi);
00195
00196     /* Configure Underrun fields */
00197     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
00198     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
00199
00200     /* Enable SPI peripheral */
00201     __HAL_SPI_ENABLE(hspi);
00202   }
00203
00204
00205   hspi->State = HAL_SPI_STATE_READY;
00206   /* Process Unlocked */
00207   __HAL_UNLOCK(hspi);
00208   return errorcode;
00209 }
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 #endif /* HAL_SPI_MODULE_ENABLED */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_spi_ex.h Source File

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stm32h7xx_hal_spi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SPI_EX_H
00022 #define STM32H7xx_HAL_SPI_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SPIEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /* Exported functions --------------------------------------------------------*/
00043 /** @addtogroup SPIEx_Exported_Functions
00044   * @{
00045   */
00046
00047 /* Initialization and de-initialization functions  ****************************/
00048 /* IO operation functions *****************************************************/
00049 /** @addtogroup SPIEx_Exported_Functions_Group1
00050   * @{
00051   */
00052 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00053 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
00054 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
00055 /**
00056   * @}
00057   */
00058
00059 /**
00060   * @}
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /**
00068   * @}
00069   */
00070
00071 #ifdef __cplusplus
00072 }
00073 #endif
00074
00075 #endif /* STM32H7xx_HAL_SPI_EX_H */
00076
00077 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sram.c Source File

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stm32h7xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @brief   SRAM HAL module driver.
00006   *          This file provides a generic firmware to drive SRAM memories
00007   *          mounted as external device.
00008   *
00009   @verbatim
00010   ==============================================================================
00011                           ##### How to use this driver #####
00012   ==============================================================================
00013   [..]
00014     This driver is a generic layered driver which contains a set of APIs used to
00015     control SRAM memories. It uses the FMC layer functions to interface
00016     with SRAM devices.
00017     The following sequence should be followed to configure the FMC to interface
00018     with SRAM/PSRAM memories:
00019
00020    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00021           SRAM_HandleTypeDef  hsram; and:
00022
00023        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00024             values of the structure member.
00025
00026        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00027             base register instance for NOR or SRAM device
00028
00029        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00030             base register instance for NOR or SRAM extended mode
00031
00032    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00033        mode timings; for example:
00034           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00035       and fill its fields with the allowed values of the structure member.
00036
00037    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00038        performs the following sequence:
00039
00040        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00041        (##) Control register configuration using the FMC NORSRAM interface function
00042             FMC_NORSRAM_Init()
00043        (##) Timing register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Timing_Init()
00045        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Extended_Timing_Init()
00047        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00048
00049    (#) At this stage you can perform read/write accesses from/to the memory connected
00050        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00051        following APIs:
00052        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00053        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00054
00055    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00056        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00057
00058    (#) You can continuously monitor the SRAM device HAL state by calling the function
00059        HAL_SRAM_GetState()
00060
00061        *** Callback registration ***
00062     =============================================
00063     [..]
00064       The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
00065       allows the user to configure dynamically the driver callbacks.
00066
00067       Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
00068       it allows to register following callbacks:
00069         (+) MspInitCallback    : SRAM MspInit.
00070         (+) MspDeInitCallback  : SRAM MspDeInit.
00071       This function takes as parameters the HAL peripheral handle, the Callback ID
00072       and a pointer to the user callback function.
00073
00074       Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
00075       weak (surcharged) function. It allows to reset following callbacks:
00076         (+) MspInitCallback    : SRAM MspInit.
00077         (+) MspDeInitCallback  : SRAM MspDeInit.
00078       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00079
00080       By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
00081       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00082       Exception done for MspInit and MspDeInit callbacks that are respectively
00083       reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
00084       and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
00085       If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
00086       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00087
00088       Callbacks can be registered/unregistered in READY state only.
00089       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00090       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00091       during the Init/DeInit.
00092       In that case first register the MspInit/MspDeInit user callbacks
00093       using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
00094       or @ref HAL_SRAM_Init function.
00095
00096       When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
00097       not defined, the callback registering feature is not available
00098       and weak (surcharged) callbacks are used.
00099
00100   @endverbatim
00101   ******************************************************************************
00102   * @attention
00103   *
00104   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00105   *
00106   * This software component is licensed by ST under BSD 3-Clause license,
00107   * the "License"; You may not use this file except in compliance with the
00108   * License. You may obtain a copy of the License at:
00109   *                       opensource.org/licenses/BSD-3-Clause
00110   *
00111   ******************************************************************************
00112   */
00113
00114 /* Includes ------------------------------------------------------------------*/
00115 #include "stm32h7xx_hal.h"
00116
00117
00118 /** @addtogroup STM32H7xx_HAL_Driver
00119   * @{
00120   */
00121
00122 #ifdef HAL_SRAM_MODULE_ENABLED
00123
00124 /** @defgroup SRAM SRAM
00125   * @brief SRAM driver modules
00126   * @{
00127   */
00128
00129 /**
00130   @cond 0
00131   */
00132 /* Private typedef -----------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134 /* Private macro -------------------------------------------------------------*/
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private function prototypes -----------------------------------------------*/
00137 static void SRAM_DMACplt    (MDMA_HandleTypeDef *hmdma);
00138 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
00139 static void SRAM_DMAError   (MDMA_HandleTypeDef *hmdma);
00140 /**
00141   @endcond
00142   */
00143
00144 /* Exported functions --------------------------------------------------------*/
00145
00146 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00151   * @brief    Initialization and Configuration functions.
00152   *
00153   @verbatim
00154   ==============================================================================
00155            ##### SRAM Initialization and de_initialization functions #####
00156   ==============================================================================
00157     [..]  This section provides functions allowing to initialize/de-initialize
00158           the SRAM memory
00159
00160 @endverbatim
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Performs the SRAM device initialization sequence
00166   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00167   *                the configuration information for SRAM module.
00168   * @param  Timing Pointer to SRAM control timing structure
00169   * @param  ExtTiming Pointer to SRAM extended mode timing structure
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00173 {
00174   /* Check the SRAM handle parameter */
00175   if (hsram == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179
00180   if (hsram->State == HAL_SRAM_STATE_RESET)
00181   {
00182     /* Allocate lock resource and initialize it */
00183     hsram->Lock = HAL_UNLOCKED;
00184
00185 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00186     if(hsram->MspInitCallback == NULL)
00187     {
00188       hsram->MspInitCallback = HAL_SRAM_MspInit;
00189     }
00190     hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
00191     hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00192
00193     /* Init the low level hardware */
00194     hsram->MspInitCallback(hsram);
00195 #else
00196     /* Initialize the low level hardware (MSP) */
00197     HAL_SRAM_MspInit(hsram);
00198 #endif
00199   }
00200
00201   /* Initialize SRAM control Interface */
00202   (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00203
00204   /* Initialize SRAM timing Interface */
00205   (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00206
00207   /* Initialize SRAM extended mode timing Interface */
00208   (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00209
00210   /* Enable the NORSRAM device */
00211   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00212
00213   /* Enable FMC Peripheral */
00214   __FMC_ENABLE();
00215
00216   /* Initialize the SRAM controller state */
00217   hsram->State = HAL_SRAM_STATE_READY;
00218
00219   return HAL_OK;
00220 }
00221
00222 /**
00223   * @brief  Performs the SRAM device De-initialization sequence.
00224   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00225   *                the configuration information for SRAM module.
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00229 {
00230 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00231   if(hsram->MspDeInitCallback == NULL)
00232   {
00233     hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00234   }
00235
00236   /* DeInit the low level hardware */
00237   hsram->MspDeInitCallback(hsram);
00238 #else
00239   /* De-Initialize the low level hardware (MSP) */
00240   HAL_SRAM_MspDeInit(hsram);
00241 #endif
00242
00243   /* Configure the SRAM registers with their reset values */
00244   (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00245
00246   /* Reset the SRAM controller state */
00247   hsram->State = HAL_SRAM_STATE_RESET;
00248
00249   /* Release Lock */
00250   __HAL_UNLOCK(hsram);
00251
00252   return HAL_OK;
00253 }
00254
00255 /**
00256   * @brief  SRAM MSP Init.
00257   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00258   *                the configuration information for SRAM module.
00259   * @retval None
00260   */
00261 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00262 {
00263   /* Prevent unused argument(s) compilation warning */
00264   UNUSED(hsram);
00265
00266   /* NOTE : This function Should not be modified, when the callback is needed,
00267             the HAL_SRAM_MspInit could be implemented in the user file
00268    */
00269 }
00270
00271 /**
00272   * @brief  SRAM MSP DeInit.
00273   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00274   *                the configuration information for SRAM module.
00275   * @retval None
00276   */
00277 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00278 {
00279   /* Prevent unused argument(s) compilation warning */
00280   UNUSED(hsram);
00281
00282   /* NOTE : This function Should not be modified, when the callback is needed,
00283             the HAL_SRAM_MspDeInit could be implemented in the user file
00284    */
00285 }
00286
00287 /**
00288   * @brief  DMA transfer complete callback.
00289   * @param  hmdma pointer to a SRAM_HandleTypeDef structure that contains
00290   *                the configuration information for SRAM module.
00291   * @retval None
00292   */
00293 __weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(hmdma);
00297
00298   /* NOTE : This function Should not be modified, when the callback is needed,
00299             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @brief  DMA transfer complete error callback.
00305   * @param  hmdma pointer to a SRAM_HandleTypeDef structure that contains
00306   *                the configuration information for SRAM module.
00307   * @retval None
00308   */
00309 __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
00310 {
00311   /* Prevent unused argument(s) compilation warning */
00312   UNUSED(hmdma);
00313
00314   /* NOTE : This function Should not be modified, when the callback is needed,
00315             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00316    */
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00324   * @brief    Input Output and memory control functions
00325   *
00326   @verbatim
00327   ==============================================================================
00328                   ##### SRAM Input and Output functions #####
00329   ==============================================================================
00330   [..]
00331     This section provides functions allowing to use and control the SRAM memory
00332
00333 @endverbatim
00334   * @{
00335   */
00336
00337 /**
00338   * @brief  Reads 8-bit buffer from SRAM memory.
00339   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00340   *                the configuration information for SRAM module.
00341   * @param  pAddress Pointer to read start address
00342   * @param  pDstBuffer Pointer to destination buffer
00343   * @param  BufferSize Size of the buffer to read from memory
00344   * @retval HAL status
00345   */
00346 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00347 {
00348   uint32_t size;
00349   __IO uint8_t *psramaddress = (uint8_t *)pAddress;
00350   uint8_t * pdestbuff = pDstBuffer;
00351   HAL_SRAM_StateTypeDef state = hsram->State;
00352
00353   /* Check the SRAM controller state */
00354   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00355   {
00356     /* Process Locked */
00357     __HAL_LOCK(hsram);
00358
00359     /* Update the SRAM controller state */
00360     hsram->State = HAL_SRAM_STATE_BUSY;
00361
00362     /* Read data from memory */
00363     for (size = BufferSize; size != 0U; size--)
00364     {
00365       *pdestbuff = *psramaddress;
00366       pdestbuff++;
00367       psramaddress++;
00368     }
00369
00370     /* Update the SRAM controller state */
00371     hsram->State = state;
00372
00373     /* Process unlocked */
00374     __HAL_UNLOCK(hsram);
00375   }
00376   else
00377   {
00378     return HAL_ERROR;
00379   }
00380
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief  Writes 8-bit buffer to SRAM memory.
00386   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00387   *                the configuration information for SRAM module.
00388   * @param  pAddress Pointer to write start address
00389   * @param  pSrcBuffer Pointer to source buffer to write
00390   * @param  BufferSize Size of the buffer to write to memory
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00394 {
00395   uint32_t size;
00396   __IO uint8_t *psramaddress = (uint8_t *)pAddress;
00397   uint8_t * psrcbuff = pSrcBuffer;
00398
00399   /* Check the SRAM controller state */
00400   if (hsram->State == HAL_SRAM_STATE_READY)
00401   {
00402     /* Process Locked */
00403     __HAL_LOCK(hsram);
00404
00405     /* Update the SRAM controller state */
00406     hsram->State = HAL_SRAM_STATE_BUSY;
00407
00408     /* Write data to memory */
00409     for (size = BufferSize; size != 0U; size--)
00410     {
00411       *psramaddress = *psrcbuff;
00412       psrcbuff++;
00413       psramaddress++;
00414     }
00415
00416     /* Update the SRAM controller state */
00417     hsram->State = HAL_SRAM_STATE_READY;
00418
00419     /* Process unlocked */
00420     __HAL_UNLOCK(hsram);
00421   }
00422   else
00423   {
00424     return HAL_ERROR;
00425   }
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Reads 16-bit buffer from SRAM memory.
00432   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00433   *                the configuration information for SRAM module.
00434   * @param  pAddress Pointer to read start address
00435   * @param  pDstBuffer Pointer to destination buffer
00436   * @param  BufferSize Size of the buffer to read from memory
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00440 {
00441   uint32_t size;
00442   __IO uint32_t *psramaddress = pAddress;
00443   uint16_t *pdestbuff = pDstBuffer;
00444   uint8_t limit;
00445   HAL_SRAM_StateTypeDef state = hsram->State;
00446
00447   /* Check the SRAM controller state */
00448   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00449   {
00450     /* Process Locked */
00451     __HAL_LOCK(hsram);
00452
00453     /* Update the SRAM controller state */
00454     hsram->State = HAL_SRAM_STATE_BUSY;
00455
00456     /* Check if the size is a 32-bits mulitple */
00457     limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
00458
00459     /* Read data from memory */
00460     for (size = BufferSize; size != limit; size-=2U)
00461     {
00462       *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
00463       pdestbuff++;
00464       *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
00465       pdestbuff++;
00466       psramaddress++;
00467     }
00468
00469     /* Read last 16-bits if size is not 32-bits multiple */
00470     if (limit != 0U)
00471     {
00472       *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
00473     }
00474
00475     /* Update the SRAM controller state */
00476     hsram->State = state;
00477
00478     /* Process unlocked */
00479     __HAL_UNLOCK(hsram);
00480   }
00481   else
00482   {
00483     return HAL_ERROR;
00484   }
00485
00486   return HAL_OK;
00487 }
00488
00489 /**
00490   * @brief  Writes 16-bit buffer to SRAM memory.
00491   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00492   *                the configuration information for SRAM module.
00493   * @param  pAddress Pointer to write start address
00494   * @param  pSrcBuffer Pointer to source buffer to write
00495   * @param  BufferSize Size of the buffer to write to memory
00496   * @retval HAL status
00497   */
00498 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00499 {
00500   uint32_t size;
00501   __IO uint32_t *psramaddress = pAddress;
00502   uint16_t * psrcbuff = pSrcBuffer;
00503   uint8_t limit;
00504
00505   /* Check the SRAM controller state */
00506   if (hsram->State == HAL_SRAM_STATE_READY)
00507   {
00508     /* Process Locked */
00509     __HAL_LOCK(hsram);
00510
00511     /* Update the SRAM controller state */
00512     hsram->State = HAL_SRAM_STATE_BUSY;
00513
00514     /* Check if the size is a 32-bits mulitple */
00515     limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
00516
00517     /* Write data to memory */
00518     for (size = BufferSize; size != limit; size-=2U)
00519     {
00520       *psramaddress = (uint32_t)(*psrcbuff);
00521       psrcbuff++;
00522       *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
00523       psrcbuff++;
00524       psramaddress++;
00525     }
00526
00527     /* Write last 16-bits if size is not 32-bits multiple */
00528     if (limit != 0U)
00529     {
00530       *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
00531     }
00532
00533     /* Update the SRAM controller state */
00534     hsram->State = HAL_SRAM_STATE_READY;
00535
00536     /* Process unlocked */
00537     __HAL_UNLOCK(hsram);
00538   }
00539   else
00540   {
00541     return HAL_ERROR;
00542   }
00543
00544   return HAL_OK;
00545 }
00546
00547 /**
00548   * @brief  Reads 32-bit buffer from SRAM memory.
00549   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00550   *                the configuration information for SRAM module.
00551   * @param  pAddress Pointer to read start address
00552   * @param  pDstBuffer Pointer to destination buffer
00553   * @param  BufferSize Size of the buffer to read from memory
00554   * @retval HAL status
00555   */
00556 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00557 {
00558   uint32_t size;
00559   __IO uint32_t * psramaddress = pAddress;
00560   uint32_t * pdestbuff = pDstBuffer;
00561   HAL_SRAM_StateTypeDef state = hsram->State;
00562
00563   /* Check the SRAM controller state */
00564   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00565   {
00566     /* Process Locked */
00567     __HAL_LOCK(hsram);
00568
00569     /* Update the SRAM controller state */
00570     hsram->State = HAL_SRAM_STATE_BUSY;
00571
00572     /* Read data from memory */
00573     for (size = BufferSize; size != 0U; size--)
00574     {
00575       *pdestbuff = *psramaddress;
00576       pdestbuff++;
00577       psramaddress++;
00578     }
00579
00580     /* Update the SRAM controller state */
00581     hsram->State = state;
00582
00583     /* Process unlocked */
00584     __HAL_UNLOCK(hsram);
00585   }
00586   else
00587   {
00588     return HAL_ERROR;
00589   }
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @brief  Writes 32-bit buffer to SRAM memory.
00596   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00597   *                the configuration information for SRAM module.
00598   * @param  pAddress Pointer to write start address
00599   * @param  pSrcBuffer Pointer to source buffer to write
00600   * @param  BufferSize Size of the buffer to write to memory
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00604 {
00605   uint32_t size;
00606   __IO uint32_t * psramaddress = pAddress;
00607   uint32_t * psrcbuff = pSrcBuffer;
00608
00609   /* Check the SRAM controller state */
00610   if (hsram->State == HAL_SRAM_STATE_READY)
00611   {
00612     /* Process Locked */
00613     __HAL_LOCK(hsram);
00614
00615     /* Update the SRAM controller state */
00616     hsram->State = HAL_SRAM_STATE_BUSY;
00617
00618     /* Write data to memory */
00619     for (size = BufferSize; size != 0U; size--)
00620     {
00621       *psramaddress = *psrcbuff;
00622       psrcbuff++;
00623       psramaddress++;
00624     }
00625
00626     /* Update the SRAM controller state */
00627     hsram->State = HAL_SRAM_STATE_READY;
00628
00629     /* Process unlocked */
00630     __HAL_UNLOCK(hsram);
00631   }
00632   else
00633   {
00634     return HAL_ERROR;
00635   }
00636
00637   return HAL_OK;
00638 }
00639
00640 /**
00641   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00642   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00643   *                the configuration information for SRAM module.
00644   * @param  pAddress Pointer to read start address
00645   * @param  pDstBuffer Pointer to destination buffer
00646   * @param  BufferSize Size of the buffer to read from memory
00647   * @retval HAL status
00648   */
00649 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00650 {
00651   HAL_StatusTypeDef status;
00652   HAL_SRAM_StateTypeDef state = hsram->State;
00653
00654   /* Check the SRAM controller state */
00655   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00656   {
00657     /* Process Locked */
00658     __HAL_LOCK(hsram);
00659
00660     /* Update the SRAM controller state */
00661     hsram->State = HAL_SRAM_STATE_BUSY;
00662
00663     /* Configure DMA user callbacks */
00664     if (state == HAL_SRAM_STATE_READY)
00665     {
00666       hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
00667     }
00668     else
00669     {
00670       hsram->hmdma->XferCpltCallback = SRAM_DMACpltProt;
00671     }
00672     hsram->hmdma->XferErrorCallback = SRAM_DMAError;
00673
00674     /* Enable the DMA Stream */
00675     status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
00676
00677     /* Process unlocked */
00678     __HAL_UNLOCK(hsram);
00679   }
00680   else
00681   {
00682     return HAL_ERROR;
00683   }
00684
00685   return status;
00686 }
00687
00688 /**
00689   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00690   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00691   *                the configuration information for SRAM module.
00692   * @param  pAddress Pointer to write start address
00693   * @param  pSrcBuffer Pointer to source buffer to write
00694   * @param  BufferSize Size of the buffer to write to memory
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00698 {
00699   HAL_StatusTypeDef status;
00700
00701   /* Check the SRAM controller state */
00702   if (hsram->State == HAL_SRAM_STATE_READY)
00703   {
00704     /* Process Locked */
00705     __HAL_LOCK(hsram);
00706
00707     /* Update the SRAM controller state */
00708     hsram->State = HAL_SRAM_STATE_BUSY;
00709
00710     /* Configure DMA user callbacks */
00711     hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
00712     hsram->hmdma->XferErrorCallback = SRAM_DMAError;
00713
00714     /* Enable the DMA Stream */
00715     status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
00716
00717     /* Process unlocked */
00718     __HAL_UNLOCK(hsram);
00719   }
00720   else
00721   {
00722     return HAL_ERROR;
00723   }
00724
00725   return status;
00726 }
00727
00728 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00729 /**
00730   * @brief  Register a User SRAM Callback
00731   *         To be used instead of the weak (surcharged) predefined callback
00732   * @param hsram : SRAM handle
00733   * @param CallbackId : ID of the callback to be registered
00734   *        This parameter can be one of the following values:
00735   *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
00736   *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
00737   * @param pCallback : pointer to the Callback function
00738   * @retval status
00739   */
00740 HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
00741 {
00742   HAL_StatusTypeDef status = HAL_OK;
00743   HAL_SRAM_StateTypeDef state;
00744
00745   if(pCallback == NULL)
00746   {
00747     return HAL_ERROR;
00748   }
00749
00750   /* Process locked */
00751   __HAL_LOCK(hsram);
00752
00753   state = hsram->State;
00754   if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
00755   {
00756     switch (CallbackId)
00757     {
00758     case HAL_SRAM_MSP_INIT_CB_ID :
00759       hsram->MspInitCallback = pCallback;
00760       break;
00761     case HAL_SRAM_MSP_DEINIT_CB_ID :
00762       hsram->MspDeInitCallback = pCallback;
00763       break;
00764     default :
00765       /* update return status */
00766       status =  HAL_ERROR;
00767       break;
00768     }
00769   }
00770   else
00771   {
00772     /* update return status */
00773     status =  HAL_ERROR;
00774   }
00775
00776   /* Release Lock */
00777   __HAL_UNLOCK(hsram);
00778   return status;
00779 }
00780
00781 /**
00782   * @brief  Unregister a User SRAM Callback
00783   *         SRAM Callback is redirected to the weak (surcharged) predefined callback
00784   * @param hsram : SRAM handle
00785   * @param CallbackId : ID of the callback to be unregistered
00786   *        This parameter can be one of the following values:
00787   *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
00788   *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
00789   *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
00790   *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
00791   * @retval status
00792   */
00793 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
00794 {
00795   HAL_StatusTypeDef status = HAL_OK;
00796   HAL_SRAM_StateTypeDef state;
00797
00798   /* Process locked */
00799   __HAL_LOCK(hsram);
00800
00801   state = hsram->State;
00802   if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00803   {
00804     switch (CallbackId)
00805     {
00806     case HAL_SRAM_MSP_INIT_CB_ID :
00807       hsram->MspInitCallback = HAL_SRAM_MspInit;
00808       break;
00809     case HAL_SRAM_MSP_DEINIT_CB_ID :
00810       hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00811       break;
00812     case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
00813       hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
00814       break;
00815     case HAL_SRAM_DMA_XFER_ERR_CB_ID :
00816       hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00817       break;
00818     default :
00819       /* update return status */
00820       status =  HAL_ERROR;
00821       break;
00822     }
00823   }
00824   else if(state == HAL_SRAM_STATE_RESET)
00825   {
00826     switch (CallbackId)
00827     {
00828     case HAL_SRAM_MSP_INIT_CB_ID :
00829       hsram->MspInitCallback = HAL_SRAM_MspInit;
00830       break;
00831     case HAL_SRAM_MSP_DEINIT_CB_ID :
00832       hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00833       break;
00834     default :
00835       /* update return status */
00836       status =  HAL_ERROR;
00837       break;
00838     }
00839   }
00840   else
00841   {
00842     /* update return status */
00843     status =  HAL_ERROR;
00844   }
00845
00846   /* Release Lock */
00847   __HAL_UNLOCK(hsram);
00848   return status;
00849 }
00850
00851 /**
00852   * @brief  Register a User SRAM Callback for DMA transfers
00853   *         To be used instead of the weak (surcharged) predefined callback
00854   * @param hsram : SRAM handle
00855   * @param CallbackId : ID of the callback to be registered
00856   *        This parameter can be one of the following values:
00857   *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
00858   *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
00859   * @param pCallback : pointer to the Callback function
00860   * @retval status
00861   */
00862 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
00863 {
00864   HAL_StatusTypeDef status = HAL_OK;
00865   HAL_SRAM_StateTypeDef state;
00866
00867   if(pCallback == NULL)
00868   {
00869     return HAL_ERROR;
00870   }
00871
00872   /* Process locked */
00873   __HAL_LOCK(hsram);
00874
00875   state = hsram->State;
00876   if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00877   {
00878     switch (CallbackId)
00879     {
00880     case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
00881       hsram->DmaXferCpltCallback = pCallback;
00882       break;
00883     case HAL_SRAM_DMA_XFER_ERR_CB_ID :
00884       hsram->DmaXferErrorCallback = pCallback;
00885       break;
00886     default :
00887       /* update return status */
00888       status =  HAL_ERROR;
00889       break;
00890     }
00891   }
00892   else
00893   {
00894     /* update return status */
00895     status =  HAL_ERROR;
00896   }
00897
00898   /* Release Lock */
00899   __HAL_UNLOCK(hsram);
00900   return status;
00901 }
00902 #endif
00903
00904 /**
00905   * @}
00906   */
00907
00908 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00909  *  @brief   Control functions
00910  *
00911 @verbatim
00912   ==============================================================================
00913                         ##### SRAM Control functions #####
00914   ==============================================================================
00915   [..]
00916     This subsection provides a set of functions allowing to control dynamically
00917     the SRAM interface.
00918
00919 @endverbatim
00920   * @{
00921   */
00922
00923 /**
00924   * @brief  Enables dynamically SRAM write operation.
00925   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00926   *                the configuration information for SRAM module.
00927   * @retval HAL status
00928   */
00929 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00930 {
00931   /* Check the SRAM controller state */
00932   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00933   {
00934     /* Process Locked */
00935     __HAL_LOCK(hsram);
00936
00937     /* Update the SRAM controller state */
00938     hsram->State = HAL_SRAM_STATE_BUSY;
00939
00940     /* Enable write operation */
00941     (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00942
00943     /* Update the SRAM controller state */
00944     hsram->State = HAL_SRAM_STATE_READY;
00945
00946     /* Process unlocked */
00947     __HAL_UNLOCK(hsram);
00948   }
00949   else
00950   {
00951     return HAL_ERROR;
00952   }
00953
00954   return HAL_OK;
00955 }
00956
00957 /**
00958   * @brief  Disables dynamically SRAM write operation.
00959   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00960   *                the configuration information for SRAM module.
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00964 {
00965   /* Check the SRAM controller state */
00966   if(hsram->State == HAL_SRAM_STATE_READY)
00967   {
00968     /* Process Locked */
00969     __HAL_LOCK(hsram);
00970
00971     /* Update the SRAM controller state */
00972     hsram->State = HAL_SRAM_STATE_BUSY;
00973
00974     /* Disable write operation */
00975     (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00976
00977     /* Update the SRAM controller state */
00978     hsram->State = HAL_SRAM_STATE_PROTECTED;
00979
00980     /* Process unlocked */
00981     __HAL_UNLOCK(hsram);
00982   }
00983   else
00984   {
00985     return HAL_ERROR;
00986   }
00987
00988   return HAL_OK;
00989 }
00990
00991 /**
00992   * @}
00993   */
00994
00995 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00996  *  @brief   Peripheral State functions
00997  *
00998 @verbatim
00999   ==============================================================================
01000                       ##### SRAM State functions #####
01001   ==============================================================================
01002   [..]
01003     This subsection permits to get in run-time the status of the SRAM controller
01004     and the data flow.
01005
01006 @endverbatim
01007   * @{
01008   */
01009
01010 /**
01011   * @brief  Returns the SRAM controller state
01012   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
01013   *                the configuration information for SRAM module.
01014   * @retval HAL state
01015   */
01016 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
01017 {
01018   return hsram->State;
01019 }
01020
01021 /**
01022   * @}
01023   */
01024
01025 /**
01026   * @}
01027   */
01028
01029 /**
01030   @cond 0
01031   */
01032 /**
01033   * @brief  MDMA SRAM process complete callback.
01034   * @param  hmdma : MDMA handle
01035   * @retval None
01036   */
01037 static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
01038 {
01039   SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
01040
01041   /* Disable the MDMA channel */
01042   __HAL_MDMA_DISABLE(hmdma);
01043
01044   /* Update the SRAM controller state */
01045   hsram->State = HAL_SRAM_STATE_READY;
01046
01047 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01048   hsram->DmaXferCpltCallback(hmdma);
01049 #else
01050   HAL_SRAM_DMA_XferCpltCallback(hmdma);
01051 #endif
01052 }
01053
01054 /**
01055   * @brief  MDMA SRAM process complete callback.
01056   * @param  hmdma : MDMA handle
01057   * @retval None
01058   */
01059 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
01060 {
01061   SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
01062
01063   /* Disable the MDMA channel */
01064   __HAL_MDMA_DISABLE(hmdma);
01065
01066   /* Update the SRAM controller state */
01067   hsram->State = HAL_SRAM_STATE_PROTECTED;
01068
01069 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01070   hsram->DmaXferCpltCallback(hmdma);
01071 #else
01072   HAL_SRAM_DMA_XferCpltCallback(hmdma);
01073 #endif
01074 }
01075
01076 /**
01077   * @brief  MDMA SRAM error callback.
01078   * @param  hmdma : MDMA handle
01079   * @retval None
01080   */
01081 static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
01082 {
01083   SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
01084
01085   /* Disable the MDMA channel */
01086   __HAL_MDMA_DISABLE(hmdma);
01087
01088   /* Update the SRAM controller state */
01089   hsram->State = HAL_SRAM_STATE_ERROR;
01090
01091 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01092   hsram->DmaXferErrorCallback(hmdma);
01093 #else
01094   HAL_SRAM_DMA_XferErrorCallback(hmdma);
01095 #endif
01096 }
01097 /**
01098   @endcond
01099   */
01100
01101 /**
01102   * @}
01103   */
01104
01105 #endif /* HAL_SRAM_MODULE_ENABLED */
01106
01107 /**
01108   * @}
01109   */
01110
01111
01112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_sram.h Source File

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stm32h7xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SRAM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   *
00011   * This software component is licensed by ST under BSD 3-Clause license,
00012   * the "License"; You may not use this file except in compliance with the
00013   * License. You may obtain a copy of the License at:
00014   *                       opensource.org/licenses/BSD-3-Clause
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32H7xx_HAL_SRAM_H
00021 #define STM32H7xx_HAL_SRAM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_ll_fmc.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034 /** @addtogroup SRAM
00035   * @{
00036   */
00037
00038 /* Exported typedef ----------------------------------------------------------*/
00039
00040 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00041   * @{
00042   */
00043 /**
00044   * @brief  HAL SRAM State structures definition
00045   */
00046 typedef enum
00047 {
00048   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00049   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00050   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00051   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00052   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
00053
00054 } HAL_SRAM_StateTypeDef;
00055
00056 /**
00057   * @brief  SRAM handle Structure definition
00058   */
00059 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00060 typedef struct __SRAM_HandleTypeDef
00061 #else
00062 typedef struct
00063 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00064 {
00065   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00066
00067   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00068
00069   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00070
00071   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00072
00073   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00074
00075   MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                          */
00076
00077 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00078   void  (* MspInitCallback)        ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp Init callback              */
00079   void  (* MspDeInitCallback)      ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp DeInit callback            */
00080   void  (* DmaXferCpltCallback)    ( MDMA_HandleTypeDef * hmdma);               /*!< SRAM DMA Xfer Complete callback     */
00081   void  (* DmaXferErrorCallback)   ( MDMA_HandleTypeDef * hmdma);               /*!< SRAM DMA Xfer Error callback        */
00082 #endif
00083 } SRAM_HandleTypeDef;
00084
00085 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00086 /**
00087   * @brief  HAL SRAM Callback ID enumeration definition
00088   */
00089 typedef enum
00090 {
00091   HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
00092   HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
00093   HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
00094   HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
00095 }HAL_SRAM_CallbackIDTypeDef;
00096
00097 /**
00098   * @brief  HAL SRAM Callback pointer definition
00099   */
00100 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
00101 typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
00102 #endif
00103 /**
00104   * @}
00105   */
00106
00107 /* Exported constants --------------------------------------------------------*/
00108 /* Exported macro ------------------------------------------------------------*/
00109
00110 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00111  * @{
00112  */
00113
00114 /** @brief Reset SRAM handle state
00115   * @param  __HANDLE__ SRAM handle
00116   * @retval None
00117   */
00118 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00119 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
00120                                                                (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
00121                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00122                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00123                                                              } while(0)
00124 #else
00125 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00126 #endif
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00134   * @{
00135   */
00136
00137 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00138  * @{
00139  */
00140
00141 /* Initialization/de-initialization functions  ********************************/
00142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00143 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00144 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00145 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00146
00147 /**
00148   * @}
00149   */
00150
00151 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00152  * @{
00153  */
00154
00155 /* I/O operation functions  ***************************************************/
00156 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00157 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00158 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00159 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00160 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00161 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00162 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00163 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00164
00165 void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
00166 void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
00167
00168 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00169 /* SRAM callback registering/unregistering */
00170 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
00171 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
00172 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
00173 #endif
00174
00175 /**
00176   * @}
00177   */
00178
00179 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00180  * @{
00181  */
00182
00183 /* SRAM Control functions  ****************************************************/
00184 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00185 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00186
00187 /**
00188   * @}
00189   */
00190
00191 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00192  * @{
00193  */
00194
00195 /* SRAM  State functions ******************************************************/
00196 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00197
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /**
00211   * @}
00212   */
00213
00214
00215 #ifdef __cplusplus
00216 }
00217 #endif
00218
00219 #endif /* STM32H7xx_HAL_SRAM_H */
00220
00221 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_swpmi.c Source File

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stm32h7xx_hal_swpmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_swpmi.c
00004   * @author  MCD Application Team
00005   * @brief   SWPMI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Single Wire Protocol Master Interface (SWPMI).
00008   *           + Initialization and Configuration
00009   *           + Data transfers functions
00010   *           + DMA transfers management
00011   *           + Interrupts and flags management
00012   @verbatim
00013  ===============================================================================
00014                         ##### How to use this driver #####
00015  ===============================================================================
00016   [..]
00017      The SWPMI HAL driver can be used as follows:
00018
00019     (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).
00020
00021     (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
00022         (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
00023         (##) SWPMI IO configuration:
00024             (+++) Enable the clock for the SWPMI GPIO.
00025             (+++) Configure these SWPMI pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
00027              and HAL_SWPMI_Receive_IT() APIs):
00028             (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
00029             (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().
00030
00031         (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
00032              and HAL_SWPMI_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx streams.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required
00036                   Tx/Rx parameters.
00037             (+++) Configure the DMA Tx/Rx streams and requests.
00038             (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
00039             (+++) Configure the priority and enable the NVIC for the transfer complete
00040                   interrupt on the DMA Tx/Rx streams.
00041
00042     (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.
00043
00044     (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
00045
00046   [..]
00047     Three operation modes are available within this driver :
00048
00049     *** Polling mode IO operation ***
00050     =================================
00051     [..]
00052       (+) Send an amount of data in blocking mode using HAL_SWPMI_Transmit()
00053       (+) Receive an amount of data in blocking mode using HAL_SWPMI_Receive()
00054
00055     *** Interrupt mode IO operation ***
00056     ===================================
00057     [..]
00058       (+) Send an amount of data in non-blocking mode using HAL_SWPMI_Transmit_IT()
00059       (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can
00060           add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback()
00061       (+) Receive an amount of data in non-blocking mode using HAL_SWPMI_Receive_IT()
00062       (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can
00063           add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback()
00064       (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can
00065           add his own code by customization of function pointer HAL_SWPMI_ErrorCallback()
00066
00067     *** DMA mode IO operation ***
00068     =============================
00069     [..]
00070       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Transmit_DMA()
00071       (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can
00072           add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback()
00073       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Receive_DMA()
00074       (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can
00075           add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback()
00076       (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can
00077           add his own code by customization of function pointer HAL_SWPMI_ErrorCallback()
00078       (+) Stop the DMA Transfer using HAL_SWPMI_DMAStop()
00079
00080     *** SWPMI HAL driver additional function list ***
00081     ===============================================
00082     [..]
00083       Below the list the others API available SWPMI HAL driver :
00084
00085       (+) HAL_SWPMI_EnableLoopback(): Enable the loopback mode for test purpose only
00086       (+) HAL_SWPMI_DisableLoopback(): Disable the loopback mode
00087
00088     *** SWPMI HAL driver macros list ***
00089     ==================================
00090     [..]
00091       Below the list of most used macros in SWPMI HAL driver :
00092
00093       (+) __HAL_SWPMI_ENABLE(): Enable the SWPMI peripheral
00094       (+) __HAL_SWPMI_DISABLE(): Disable the SWPMI peripheral
00095       (+) __HAL_SWPMI_TRANSCEIVER_ENABLE(): Enable the SWPMI peripheral transceiver
00096       (+) __HAL_SWPMI_TRANSCEIVER_DISABLE(): Disable the SWPMI peripheral transceiver
00097       (+) __HAL_SWPMI_ENABLE_IT(): Enable the specified SWPMI interrupts
00098       (+) __HAL_SWPMI_DISABLE_IT(): Disable the specified SWPMI interrupts
00099       (+) __HAL_SWPMI_GET_IT_SOURCE(): Check if the specified SWPMI interrupt source is
00100           enabled or disabled
00101       (+) __HAL_SWPMI_GET_FLAG(): Check whether the specified SWPMI flag is set or not
00102
00103     *** Callback registration ***
00104     =============================
00105     [..]
00106       The compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS when set to 1
00107       allows the user to configure dynamically the driver callbacks.
00108     [..]
00109       Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows
00110       to register the following callbacks:
00111       (+) RxCpltCallback     : SWPMI receive complete.
00112       (+) RxHalfCpltCallback : SWPMI receive half complete.
00113       (+) TxCpltCallback     : SWPMI transmit complete.
00114       (+) TxHalfCpltCallback : SWPMI transmit half complete.
00115       (+) ErrorCallback      : SWPMI error.
00116       (+) MspInitCallback    : SWPMI MspInit.
00117       (+) MspDeInitCallback  : SWPMI MspDeInit.
00118     [..]
00119     This function takes as parameters the HAL peripheral handle, the callback ID
00120     and a pointer to the user callback function.
00121     [..]
00122     Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default
00123     weak (surcharged) function.
00124     HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00125     and the callback ID.
00126     This function allows to reset following callbacks:
00127       (+) RxCpltCallback     : SWPMI receive complete.
00128       (+) RxHalfCpltCallback : SWPMI receive half complete.
00129       (+) TxCpltCallback     : SWPMI transmit complete.
00130       (+) TxHalfCpltCallback : SWPMI transmit half complete.
00131       (+) ErrorCallback      : SWPMI error.
00132       (+) MspInitCallback    : SWPMI MspInit.
00133       (+) MspDeInitCallback  : SWPMI MspDeInit.
00134     [..]
00135     By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET
00136     all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00137     examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback().
00138     Exception done for MspInit and MspDeInit callbacks that are respectively
00139     reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init
00140     and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand).
00141     If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit
00142     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00143     [..]
00144     Callbacks can be registered/unregistered in READY state only.
00145     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00146     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00147     during the Init/DeInit.
00148     In that case first register the MspInit/MspDeInit user callbacks
00149     using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit
00150     or HAL_SWPMI_Init function.
00151     [..]
00152     When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or
00153     not defined, the callback registering feature is not available
00154     and weak (surcharged) callbacks are used.
00155
00156   @endverbatim
00157   ******************************************************************************
00158   * @attention
00159   *
00160   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00161   * All rights reserved.</center></h2>
00162   *
00163   * This software component is licensed by ST under BSD 3-Clause license,
00164   * the "License"; You may not use this file except in compliance with the
00165   * License. You may obtain a copy of the License at:
00166   *                        opensource.org/licenses/BSD-3-Clause
00167   *
00168   ******************************************************************************
00169   */
00170
00171 /* Includes ------------------------------------------------------------------*/
00172 #include "stm32h7xx_hal.h"
00173
00174 /** @addtogroup STM32H7xx_HAL_Driver
00175   * @{
00176   */
00177
00178
00179 /** @defgroup SWPMI SWPMI
00180   * @brief HAL SWPMI module driver
00181   * @{
00182   */
00183 #ifdef HAL_SWPMI_MODULE_ENABLED
00184
00185 /* Private typedef -----------------------------------------------------------*/
00186 /* Private define ------------------------------------------------------------*/
00187 /* Private constants ---------------------------------------------------------*/
00188 /** @addtogroup SWPMI_Private_Constants SWPMI Private Constants
00189   * @{
00190   */
00191 #define SWPMI_TIMEOUT_VALUE                   22000U   /* End of transmission timeout */
00192 #define SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE    2000U   /* Transceiver ready timeout */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /* Private macros ------------------------------------------------------------*/
00199 /* Private variables ---------------------------------------------------------*/
00200 /* Private function prototypes -----------------------------------------------*/
00201 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00202 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00203 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00204 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00205 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
00206 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00207 static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
00208 static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
00209 static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
00210 static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00211 static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00212 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
00213
00214 /* Exported functions --------------------------------------------------------*/
00215
00216 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00217   * @{
00218   */
00219
00220 /** @defgroup SWPMI_Exported_Group1 Initialization/de-initialization methods
00221   *  @brief    Initialization and Configuration functions
00222   *
00223 @verbatim
00224  ===============================================================================
00225             ##### Initialization and Configuration functions #####
00226  ===============================================================================
00227     [..]  This section provides functions allowing to:
00228       (+) Initialize and configure the SWPMI peripheral.
00229       (+) De-initialize the SWPMI peripheral.
00230
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
00237   * @param hswpmi SWPMI handle
00238   * @retval HAL status
00239   */
00240 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
00241 {
00242   HAL_StatusTypeDef status = HAL_OK;
00243   uint32_t tickstart = HAL_GetTick();
00244
00245   /* Check the SWPMI handle allocation */
00246   if(hswpmi == NULL)
00247   {
00248     status = HAL_ERROR;
00249   }
00250   else
00251   {
00252     /* Check the parameters */
00253     assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
00254     assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
00255     assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
00256     assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
00257
00258     if(hswpmi->State == HAL_SWPMI_STATE_RESET)
00259     {
00260       /* Allocate lock resource and initialize it */
00261       hswpmi->Lock = HAL_UNLOCKED;
00262
00263 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00264       /* Reset callback pointers to the weak predefined callbacks */
00265       hswpmi->RxCpltCallback     = HAL_SWPMI_RxCpltCallback;
00266       hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
00267       hswpmi->TxCpltCallback     = HAL_SWPMI_TxCpltCallback;
00268       hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
00269       hswpmi->ErrorCallback      = HAL_SWPMI_ErrorCallback;
00270
00271       /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00272       if(hswpmi->MspInitCallback == NULL)
00273       {
00274         hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
00275       }
00276       hswpmi->MspInitCallback(hswpmi);
00277 #else
00278       /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00279       HAL_SWPMI_MspInit(hswpmi);
00280 #endif
00281     }
00282
00283     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00284
00285     /* Disable SWPMI interface */
00286     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00287
00288     /* Clear all SWPMI interface flags */
00289     WRITE_REG(hswpmi->Instance->ICR, 0x099F);
00290
00291     /* Apply Voltage class selection */
00292     MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
00293
00294
00295     /* Configure the BRR register (Bitrate) */
00296     WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
00297
00298     /* Apply SWPMI CR configuration */
00299     MODIFY_REG(hswpmi->Instance->CR, \
00300                SWPMI_CR_RXDMA | SWPMI_CR_TXDMA  | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
00301                hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
00302
00303     /* Enable the SWPMI transceiver */
00304     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
00305     /* Wait on RDYF flag to activate SWPMI */
00306     if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
00307     {
00308       status = HAL_TIMEOUT;
00309     }
00310
00311     if(status == HAL_OK)
00312     {
00313       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00314       hswpmi->State = HAL_SWPMI_STATE_READY;
00315
00316       /* Enable SWPMI peripheral */
00317       SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00318     }
00319     else
00320     {
00321       hswpmi->ErrorCode = HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY;
00322       hswpmi->State = HAL_SWPMI_STATE_ERROR;
00323     }
00324   }
00325
00326   return status;
00327 }
00328
00329 /**
00330   * @brief De-initialize the SWPMI peripheral.
00331   * @param hswpmi SWPMI handle
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
00335 {
00336   HAL_StatusTypeDef status = HAL_OK;
00337
00338   /* Check the SWPMI handle allocation */
00339   if(hswpmi == NULL)
00340   {
00341     status = HAL_ERROR;
00342   }
00343   else
00344   {
00345     /* Check the parameters */
00346     assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
00347
00348     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00349
00350     /* Disable SWPMI interface */
00351     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00352
00353     /* Disable Loopback mode */
00354     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
00355
00356     /* Disable SWPMI transceiver */
00357     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
00358
00359
00360     /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00361 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00362     if(hswpmi->MspDeInitCallback == NULL)
00363     {
00364       hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
00365     }
00366     hswpmi->MspDeInitCallback(hswpmi);
00367 #else
00368     HAL_SWPMI_MspDeInit(hswpmi);
00369 #endif
00370
00371     hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00372     hswpmi->State = HAL_SWPMI_STATE_RESET;
00373
00374     /* Release Lock */
00375     __HAL_UNLOCK(hswpmi);
00376   }
00377
00378   return status;
00379 }
00380
00381 /**
00382   * @brief Initialize the SWPMI MSP.
00383   * @param hswpmi SWPMI handle
00384   * @retval None
00385   */
00386 __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
00387 {
00388   /* Prevent unused argument(s) compilation warning */
00389   UNUSED(hswpmi);
00390
00391   /* NOTE : This function should not be modified, when the callback is needed,
00392             the HAL_SWPMI_MspInit can be implemented in the user file
00393    */
00394 }
00395
00396 /**
00397   * @brief DeInitialize the SWPMI MSP.
00398   * @param hswpmi SWPMI handle
00399   * @retval None
00400   */
00401 __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
00402 {
00403   /* Prevent unused argument(s) compilation warning */
00404   UNUSED(hswpmi);
00405
00406   /* NOTE : This function should not be modified, when the callback is needed,
00407             the HAL_SWPMI_MspDeInit can be implemented in the user file
00408    */
00409 }
00410
00411 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00412 /**
00413   * @brief  Register a user SWPMI callback
00414   *         to be used instead of the weak predefined callback.
00415   * @param  hswpmi SWPMI handle.
00416   * @param  CallbackID ID of the callback to be registered.
00417   *         This parameter can be one of the following values:
00418   *           @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
00419   *           @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00420   *           @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
00421   *           @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00422   *           @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID.
00423   *           @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
00424   *           @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
00425   * @param  pCallback pointer to the callback function.
00426   * @retval HAL status.
00427   */
00428 HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
00429                                            HAL_SWPMI_CallbackIDTypeDef CallbackID,
00430                                            pSWPMI_CallbackTypeDef      pCallback)
00431 {
00432   HAL_StatusTypeDef status = HAL_OK;
00433
00434   if(pCallback == NULL)
00435   {
00436     /* update the error code */
00437     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00438     /* update return status */
00439     status = HAL_ERROR;
00440   }
00441   else
00442   {
00443     if(hswpmi->State == HAL_SWPMI_STATE_READY)
00444     {
00445       switch (CallbackID)
00446       {
00447       case HAL_SWPMI_RX_COMPLETE_CB_ID :
00448         hswpmi->RxCpltCallback = pCallback;
00449         break;
00450       case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
00451         hswpmi->RxHalfCpltCallback = pCallback;
00452         break;
00453       case HAL_SWPMI_TX_COMPLETE_CB_ID :
00454         hswpmi->TxCpltCallback = pCallback;
00455         break;
00456       case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
00457         hswpmi->TxHalfCpltCallback = pCallback;
00458         break;
00459       case HAL_SWPMI_ERROR_CB_ID :
00460         hswpmi->ErrorCallback = pCallback;
00461         break;
00462       case HAL_SWPMI_MSPINIT_CB_ID :
00463         hswpmi->MspInitCallback = pCallback;
00464         break;
00465       case HAL_SWPMI_MSPDEINIT_CB_ID :
00466         hswpmi->MspDeInitCallback = pCallback;
00467         break;
00468       default :
00469         /* update the error code */
00470         hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00471         /* update return status */
00472         status = HAL_ERROR;
00473         break;
00474       }
00475     }
00476     else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
00477     {
00478       switch (CallbackID)
00479       {
00480       case HAL_SWPMI_MSPINIT_CB_ID :
00481         hswpmi->MspInitCallback = pCallback;
00482         break;
00483       case HAL_SWPMI_MSPDEINIT_CB_ID :
00484         hswpmi->MspDeInitCallback = pCallback;
00485         break;
00486       default :
00487         /* update the error code */
00488         hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00489         /* update return status */
00490         status = HAL_ERROR;
00491         break;
00492       }
00493     }
00494     else
00495     {
00496       /* update the error code */
00497       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00498       /* update return status */
00499       status = HAL_ERROR;
00500     }
00501   }
00502   return status;
00503 }
00504
00505 /**
00506   * @brief  Unregister a user SWPMI callback.
00507   *         SWPMI callback is redirected to the weak predefined callback.
00508   * @param  hswpmi SWPMI handle.
00509   * @param  CallbackID ID of the callback to be unregistered.
00510   *         This parameter can be one of the following values:
00511   *           @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID.
00512   *           @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00513   *           @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID.
00514   *           @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00515   *           @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID.
00516   *           @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID.
00517   *           @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID.
00518   * @retval HAL status.
00519   */
00520 HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
00521                                              HAL_SWPMI_CallbackIDTypeDef CallbackID)
00522 {
00523   HAL_StatusTypeDef status = HAL_OK;
00524
00525   if(hswpmi->State == HAL_SWPMI_STATE_READY)
00526   {
00527     switch (CallbackID)
00528     {
00529     case HAL_SWPMI_RX_COMPLETE_CB_ID :
00530       hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
00531       break;
00532     case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
00533       hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
00534       break;
00535     case HAL_SWPMI_TX_COMPLETE_CB_ID :
00536       hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
00537       break;
00538     case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
00539       hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
00540       break;
00541     case HAL_SWPMI_ERROR_CB_ID :
00542       hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
00543       break;
00544     case HAL_SWPMI_MSPINIT_CB_ID :
00545       hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
00546       break;
00547     case HAL_SWPMI_MSPDEINIT_CB_ID :
00548       hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
00549       break;
00550     default :
00551       /* update the error code */
00552       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00553       /* update return status */
00554       status = HAL_ERROR;
00555       break;
00556     }
00557   }
00558   else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
00559   {
00560     switch (CallbackID)
00561     {
00562     case HAL_SWPMI_MSPINIT_CB_ID :
00563       hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
00564       break;
00565     case HAL_SWPMI_MSPDEINIT_CB_ID :
00566       hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
00567       break;
00568     default :
00569       /* update the error code */
00570       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00571       /* update return status */
00572       status = HAL_ERROR;
00573       break;
00574     }
00575   }
00576   else
00577   {
00578     /* update the error code */
00579     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
00580     /* update return status */
00581     status = HAL_ERROR;
00582   }
00583   return status;
00584 }
00585 #endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */
00586
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup SWPMI_Exported_Group2 IO operation methods
00592   *  @brief SWPMI Transmit/Receive functions
00593   *
00594 @verbatim
00595  ===============================================================================
00596                       ##### IO operation methods #####
00597  ===============================================================================
00598  [..]
00599     This subsection provides a set of functions allowing to manage the SWPMI
00600      data transfers.
00601
00602     (#) There are two modes of transfer:
00603        (++) Blocking mode: The communication is performed in polling mode.
00604             The HAL status of all data processing is returned by the same function
00605             after finishing transfer.
00606        (++) Non-Blocking mode: The communication is performed using Interrupts
00607            or DMA. The end of the data processing will be indicated through the
00608            dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
00609            the selected DMA stream interrupt handler when using DMA mode.
00610            The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
00611            will be executed respectively at the end of the transmit or receive process.
00612            The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.
00613
00614     (#) Blocking mode API's are:
00615         (++) HAL_SWPMI_Transmit()
00616         (++) HAL_SWPMI_Receive()
00617
00618     (#) Non-Blocking mode API's with Interrupt are:
00619         (++) HAL_SWPMI_Transmit_IT()
00620         (++) HAL_SWPMI_Receive_IT()
00621         (++) HAL_SWPMI_IRQHandler()
00622
00623     (#) Non-Blocking mode API's with DMA are:
00624         (++) HAL_SWPMI_Transmit_DMA()
00625         (++) HAL_SWPMI_Receive_DMA()
00626         (++) HAL_SWPMI_DMAPause()
00627         (++) HAL_SWPMI_DMAResume()
00628         (++) HAL_SWPMI_DMAStop()
00629
00630     (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
00631         (++) HAL_SWPMI_TxHalfCpltCallback()
00632         (++) HAL_SWPMI_TxCpltCallback()
00633         (++) HAL_SWPMI_RxHalfCpltCallback()
00634         (++) HAL_SWPMI_RxCpltCallback()
00635         (++) HAL_SWPMI_ErrorCallback()
00636
00637     (#) The capability to launch the above IO operations in loopback mode for
00638         user application verification:
00639         (++) HAL_SWPMI_EnableLoopback()
00640         (++) HAL_SWPMI_DisableLoopback()
00641
00642 @endverbatim
00643   * @{
00644   */
00645
00646 /**
00647   * @brief  Transmit an amount of data in blocking mode.
00648   * @param  hswpmi pointer to a SWPMI_HandleTypeDef structure that contains
00649   *                the configuration information for SWPMI module.
00650   * @param  pData Pointer to data buffer
00651   * @param  Size Amount of data to be sent
00652   * @param  Timeout Timeout duration
00653   * @retval HAL status
00654   */
00655 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
00656 {
00657   uint32_t tickstart = HAL_GetTick();
00658   HAL_StatusTypeDef status = HAL_OK;
00659   HAL_SWPMI_StateTypeDef tmp_state;
00660   uint32_t *ptmp_data;
00661   uint32_t tmp_size;
00662
00663   if((pData == NULL ) || (Size == 0U))
00664   {
00665     status = HAL_ERROR;
00666   }
00667   else
00668   {
00669     /* Process Locked */
00670     __HAL_LOCK(hswpmi);
00671
00672     tmp_state = hswpmi->State;
00673     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
00674     {
00675       /* Check if a non-blocking receive process is ongoing or not */
00676       if(tmp_state == HAL_SWPMI_STATE_READY)
00677       {
00678         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00679
00680         /* Disable any transmitter interrupts */
00681         __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
00682
00683         /* Disable any transmitter flags */
00684         __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
00685
00686         /* Enable SWPMI peripheral if not */
00687         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00688       }
00689       else
00690       {
00691         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00692       }
00693
00694       ptmp_data = pData;
00695       tmp_size = Size;
00696       do
00697       {
00698         /* Wait the TXE to write data */
00699         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
00700         {
00701           hswpmi->Instance->TDR = *ptmp_data;
00702           ptmp_data++;
00703           tmp_size--;
00704         }
00705         else
00706         {
00707           /* Check for the Timeout */
00708           if(Timeout != HAL_MAX_DELAY)
00709           {
00710             if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00711             {
00712               status = HAL_TIMEOUT;
00713               break;
00714             }
00715           }
00716         }
00717       } while(tmp_size != 0U);
00718
00719       /* Wait on TXBEF flag to be able to start a second transfer */
00720       if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
00721       {
00722         /* Timeout occurred */
00723         hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
00724
00725         status = HAL_TIMEOUT;
00726       }
00727
00728       if(status == HAL_OK)
00729       {
00730         /* Check if a non-blocking receive Process is ongoing or not */
00731         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00732         {
00733           hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00734         }
00735         else
00736         {
00737           hswpmi->State = HAL_SWPMI_STATE_READY;
00738         }
00739       }
00740     }
00741     else
00742     {
00743       status = HAL_BUSY;
00744     }
00745   }
00746
00747   if((status != HAL_OK) && (status != HAL_BUSY))
00748   {
00749     hswpmi->State = HAL_SWPMI_STATE_READY;
00750   }
00751   /* Process Unlocked */
00752   __HAL_UNLOCK(hswpmi);
00753
00754   return status;
00755 }
00756
00757 /**
00758   * @brief  Receive an amount of data in blocking mode.
00759   * @param  hswpmi pointer to a SWPMI_HandleTypeDef structure that contains
00760   *                the configuration information for SWPMI module.
00761   * @param  pData Pointer to data buffer
00762   * @param  Size Amount of data to be received
00763   * @param  Timeout Timeout duration
00764   * @retval HAL status
00765   */
00766 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00767 {
00768   uint32_t tickstart = HAL_GetTick();
00769   HAL_StatusTypeDef status = HAL_OK;
00770   HAL_SWPMI_StateTypeDef tmp_state;
00771   uint32_t *ptmp_data;
00772   uint32_t tmp_size;
00773
00774   if((pData == NULL ) || (Size == 0U))
00775   {
00776     status = HAL_ERROR;
00777   }
00778   else
00779   {
00780     /* Process Locked */
00781     __HAL_LOCK(hswpmi);
00782
00783     tmp_state = hswpmi->State;
00784     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
00785     {
00786       /* Check if a non-blocking transmit process is ongoing or not */
00787       if(tmp_state == HAL_SWPMI_STATE_READY)
00788       {
00789         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00790
00791         /* Disable any receiver interrupts */
00792         CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00793
00794         /* Enable SWPMI peripheral if not */
00795         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00796       }
00797       else
00798       {
00799         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00800       }
00801
00802       ptmp_data = pData;
00803       tmp_size = Size;
00804       do
00805       {
00806         /* Wait the RXNE to read data */
00807         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
00808         {
00809           *ptmp_data = hswpmi->Instance->RDR;
00810           ptmp_data++;
00811           tmp_size--;
00812         }
00813         else
00814         {
00815           /* Check for the Timeout */
00816           if(Timeout != HAL_MAX_DELAY)
00817           {
00818             if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00819             {
00820               status = HAL_TIMEOUT;
00821               break;
00822             }
00823           }
00824         }
00825       } while(tmp_size != 0U);
00826
00827       if(status == HAL_OK)
00828       {
00829         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
00830         {
00831           /* Clear RXBFF at end of reception */
00832           WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
00833         }
00834
00835         /* Check if a non-blocking transmit Process is ongoing or not */
00836         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00837         {
00838           hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00839         }
00840         else
00841         {
00842           hswpmi->State = HAL_SWPMI_STATE_READY;
00843         }
00844       }
00845     }
00846     else
00847     {
00848       status = HAL_BUSY;
00849     }
00850   }
00851
00852   if((status != HAL_OK) && (status != HAL_BUSY))
00853   {
00854     hswpmi->State = HAL_SWPMI_STATE_READY;
00855   }
00856   /* Process Unlocked */
00857   __HAL_UNLOCK(hswpmi);
00858
00859   return status;
00860 }
00861
00862 /**
00863   * @brief  Transmit an amount of data in non-blocking mode with interrupt.
00864   * @param  hswpmi pointer to a SWPMI_HandleTypeDef structure that contains
00865   *                the configuration information for SWPMI module.
00866   * @param  pData Pointer to data buffer
00867   * @param  Size Amount of data to be sent
00868   * @retval HAL status
00869   */
00870 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00871 {
00872   HAL_StatusTypeDef status = HAL_OK;
00873   HAL_SWPMI_StateTypeDef tmp_state;
00874
00875   if((pData == NULL ) || (Size == 0U))
00876   {
00877     status =  HAL_ERROR;
00878   }
00879   else
00880   {
00881     /* Process Locked */
00882     __HAL_LOCK(hswpmi);
00883
00884     tmp_state = hswpmi->State;
00885     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
00886     {
00887       /* Update handle */
00888       hswpmi->pTxBuffPtr = pData;
00889       hswpmi->TxXferSize = Size;
00890       hswpmi->TxXferCount = Size;
00891       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00892
00893       /* Check if a receive process is ongoing or not */
00894       if(tmp_state == HAL_SWPMI_STATE_READY)
00895       {
00896         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00897
00898         /* Enable SWPMI peripheral if not */
00899         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00900       }
00901       else
00902       {
00903         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00904       }
00905
00906       /* Enable the SWPMI transmit underrun error */
00907       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
00908
00909       /* Process Unlocked */
00910       __HAL_UNLOCK(hswpmi);
00911
00912       /* Enable the SWPMI interrupts:      */
00913       /* - Transmit data register empty    */
00914       /* - Transmit buffer empty           */
00915       /* - Transmit/Reception completion   */
00916       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
00917     }
00918     else
00919     {
00920       status =  HAL_BUSY;
00921
00922       /* Process Unlocked */
00923       __HAL_UNLOCK(hswpmi);
00924     }
00925   }
00926
00927   return status;
00928 }
00929
00930 /**
00931   * @brief  Receive an amount of data in non-blocking mode with interrupt.
00932   * @param  hswpmi SWPMI handle
00933   * @param  pData Pointer to data buffer
00934   * @param  Size Amount of data to be received
00935   * @retval HAL status
00936   */
00937 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00938 {
00939   HAL_StatusTypeDef status = HAL_OK;
00940   HAL_SWPMI_StateTypeDef tmp_state;
00941
00942   if((pData == NULL ) || (Size == 0U))
00943   {
00944     status =  HAL_ERROR;
00945   }
00946   else
00947   {
00948     /* Process Locked */
00949     __HAL_LOCK(hswpmi);
00950
00951     tmp_state = hswpmi->State;
00952     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
00953     {
00954       /* Update handle */
00955       hswpmi->pRxBuffPtr = pData;
00956       hswpmi->RxXferSize = Size;
00957       hswpmi->RxXferCount = Size;
00958       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00959
00960       /* Check if a transmit process is ongoing or not */
00961       if(tmp_state == HAL_SWPMI_STATE_READY)
00962       {
00963         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00964
00965         /* Enable SWPMI peripheral if not */
00966         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00967       }
00968       else
00969       {
00970         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00971       }
00972
00973       /* Process Unlocked */
00974       __HAL_UNLOCK(hswpmi);
00975
00976       /* Enable the SWPMI slave resume */
00977       /* Enable the SWPMI Data Register not empty Interrupt, receive CRC Error, receive overrun and RxBuf Interrupt */
00978       /*  Enable the SWPMI Transmit/Reception completion   */
00979       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00980     }
00981     else
00982     {
00983       status = HAL_BUSY;
00984
00985       /* Process Unlocked */
00986       __HAL_UNLOCK(hswpmi);
00987     }
00988   }
00989
00990   return status;
00991 }
00992
00993 /**
00994   * @brief  Transmit an amount of data in non-blocking mode with DMA interrupt.
00995   * @param  hswpmi SWPMI handle
00996   * @param  pData Pointer to data buffer
00997   * @param  Size Amount of data to be sent
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
01001 {
01002   HAL_StatusTypeDef status = HAL_OK;
01003   HAL_SWPMI_StateTypeDef tmp_state;
01004
01005   if((pData == NULL ) || (Size == 0U))
01006   {
01007     status =  HAL_ERROR;
01008   }
01009   else
01010   {
01011     /* Process Locked */
01012     __HAL_LOCK(hswpmi);
01013
01014     tmp_state = hswpmi->State;
01015     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
01016     {
01017       /* Update handle */
01018       hswpmi->pTxBuffPtr = pData;
01019       hswpmi->TxXferSize = Size;
01020       hswpmi->TxXferCount = Size;
01021       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
01022
01023       /* Check if a receive process is ongoing or not */
01024       if(tmp_state == HAL_SWPMI_STATE_READY)
01025       {
01026         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01027
01028         /* Enable SWPMI peripheral if not */
01029         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01030       }
01031       else
01032       {
01033         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
01034       }
01035
01036       /* Set the SWPMI DMA transfer complete callback */
01037       hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
01038
01039       /* Set the SWPMI DMA Half transfer complete callback */
01040       hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
01041
01042       /* Set the DMA error callback */
01043       hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
01044
01045       /* Enable the SWPMI transmit DMA stream */
01046       if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
01047       {
01048         hswpmi->State = tmp_state;    /* Back to previous state */
01049         hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
01050         status = HAL_ERROR;
01051
01052         /* Process Unlocked */
01053         __HAL_UNLOCK(hswpmi);
01054       }
01055       else
01056       {
01057         /* Process Unlocked */
01058         __HAL_UNLOCK(hswpmi);
01059
01060         /* Enable the SWPMI transmit underrun error */
01061         __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
01062
01063         /* Enable the DMA transfer for transmit request by setting the TXDMA bit
01064            in the SWPMI CR register */
01065         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
01066       }
01067     }
01068     else
01069     {
01070       status = HAL_BUSY;
01071
01072       /* Process Unlocked */
01073       __HAL_UNLOCK(hswpmi);
01074     }
01075   }
01076
01077   return status;
01078 }
01079
01080 /**
01081   * @brief  Receive an amount of data in non-blocking mode with DMA interrupt.
01082   * @param  hswpmi SWPMI handle
01083   * @param  pData Pointer to data buffer
01084   * @param  Size Amount of data to be received
01085   * @retval HAL status
01086   */
01087 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
01088 {
01089   HAL_StatusTypeDef status = HAL_OK;
01090   HAL_SWPMI_StateTypeDef tmp_state;
01091
01092   if((pData == NULL ) || (Size == 0U))
01093   {
01094     status =  HAL_ERROR;
01095   }
01096   else
01097   {
01098     /* Process Locked */
01099     __HAL_LOCK(hswpmi);
01100
01101     tmp_state = hswpmi->State;
01102     if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
01103     {
01104       /* Update handle */
01105       hswpmi->pRxBuffPtr = pData;
01106       hswpmi->RxXferSize = Size;
01107       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
01108
01109       /* Check if a transmit process is ongoing or not */
01110       if(tmp_state == HAL_SWPMI_STATE_READY)
01111       {
01112         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01113
01114         /* Enable SWPMI peripheral if not */
01115         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01116       }
01117       else
01118       {
01119         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
01120       }
01121
01122       /* Set the SWPMI DMA transfer complete callback */
01123       hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
01124
01125       /* Set the SWPMI DMA Half transfer complete callback */
01126       hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
01127
01128       /* Set the DMA error callback */
01129       hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
01130
01131       /* Enable the DMA request */
01132       if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
01133       {
01134         hswpmi->State = tmp_state;    /* Back to previous state */
01135         hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
01136         status = HAL_ERROR;
01137
01138         /* Process Unlocked */
01139         __HAL_UNLOCK(hswpmi);
01140       }
01141       else
01142       {
01143         /* Process Unlocked */
01144         __HAL_UNLOCK(hswpmi);
01145
01146         /* Enable the SWPMI receive CRC Error and receive overrun interrupts */
01147         __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE);
01148
01149         /* Enable the DMA transfer for the receiver request by setting the RXDMA bit
01150            in the SWPMI CR register */
01151         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01152       }
01153     }
01154     else
01155     {
01156       status = HAL_BUSY;
01157
01158       /* Process Unlocked */
01159       __HAL_UNLOCK(hswpmi);
01160     }
01161   }
01162
01163   return status;
01164 }
01165
01166 /**
01167   * @brief Stop all DMA transfers.
01168   * @param hswpmi SWPMI handle
01169   * @retval HAL status
01170   */
01171 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
01172 {
01173   HAL_StatusTypeDef status = HAL_OK;
01174
01175   /* Process Locked */
01176   __HAL_LOCK(hswpmi);
01177
01178   /* Disable the SWPMI Tx/Rx DMA requests */
01179   CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
01180
01181   /* Abort the SWPMI DMA tx stream */
01182   if(hswpmi->hdmatx != NULL)
01183   {
01184     if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
01185     {
01186       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
01187       status = HAL_ERROR;
01188     }
01189   }
01190   /* Abort the SWPMI DMA rx stream */
01191   if(hswpmi->hdmarx != NULL)
01192   {
01193     if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
01194     {
01195       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
01196       status = HAL_ERROR;
01197     }
01198   }
01199
01200   /* Disable SWPMI interface */
01201   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01202
01203   hswpmi->State = HAL_SWPMI_STATE_READY;
01204
01205   /* Process Unlocked */
01206   __HAL_UNLOCK(hswpmi);
01207
01208   return status;
01209 }
01210
01211
01212 /**
01213   * @brief Enable the Loopback mode.
01214   * @param hswpmi SWPMI handle
01215   * @note  Loopback mode is to be used only for test purposes
01216   * @retval HAL_OK / HAL_BUSY
01217   */
01218 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
01219 {
01220   HAL_StatusTypeDef  status = HAL_OK;
01221
01222   /* Process Locked */
01223   __HAL_LOCK(hswpmi);
01224
01225   /* Make sure the SWPMI interface is not enabled to set the loopback mode */
01226   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01227
01228   /* Set Loopback */
01229   SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
01230
01231   /* Enable SWPMI interface in loopback mode */
01232   SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01233
01234   /* Process Unlocked */
01235   __HAL_UNLOCK(hswpmi);
01236
01237   return status;
01238 }
01239
01240 /**
01241   * @brief Disable the Loopback mode.
01242   * @param hswpmi SWPMI handle
01243   * @note  Loopback mode is to be used only for test purposes
01244   * @retval HAL_OK / HAL_BUSY
01245   */
01246 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
01247 {
01248   HAL_StatusTypeDef  status = HAL_OK;
01249
01250   /* Process Locked */
01251   __HAL_LOCK(hswpmi);
01252
01253   /* Make sure the SWPMI interface is not enabled to reset the loopback mode */
01254   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01255
01256   /* Reset Loopback */
01257   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
01258
01259   /* Re-enable SWPMI interface in normal mode */
01260   SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
01261
01262   /* Process Unlocked */
01263   __HAL_UNLOCK(hswpmi);
01264
01265   return status;
01266 }
01267
01268 /**
01269   * @}
01270   */
01271
01272 /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks
01273  *  @brief  SWPMI  IRQ handler.
01274  *
01275 @verbatim
01276   ==============================================================================
01277                       ##### SWPMI IRQ handler and callbacks  #####
01278   ==============================================================================
01279 [..]  This section provides SWPMI IRQ handler and callback functions called within
01280       the IRQ handler.
01281
01282 @endverbatim
01283   * @{
01284   */
01285
01286 /**
01287   * @brief Handle SWPMI interrupt request.
01288   * @param hswpmi SWPMI handle
01289   * @retval None
01290   */
01291 void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
01292 {
01293   uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
01294   uint32_t regier = READ_REG(hswpmi->Instance->IER);
01295   uint32_t errcode = HAL_SWPMI_ERROR_NONE;
01296
01297   /* SWPMI CRC error interrupt occurred --------------------------------------*/
01298   if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
01299   {
01300     /* Disable Receive CRC interrupt */
01301     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
01302     /* Clear Receive CRC and Receive buffer full flag */
01303     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
01304
01305     errcode |= HAL_SWPMI_ERROR_CRC;
01306   }
01307
01308   /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
01309   if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
01310   {
01311     /* Disable Receive overrun interrupt */
01312     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
01313     /* Clear Receive overrun flag */
01314     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
01315
01316     errcode |= HAL_SWPMI_ERROR_OVR;
01317   }
01318
01319   /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
01320   if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
01321   {
01322     /* Disable Transmit under run interrupt */
01323     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
01324     /* Clear Transmit under run flag */
01325     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
01326
01327     errcode |= HAL_SWPMI_ERROR_UDR;
01328   }
01329
01330    /* Call SWPMI Error Call back function if needed --------------------------*/
01331   if(errcode != HAL_SWPMI_ERROR_NONE)
01332   {
01333     hswpmi->ErrorCode |= errcode;
01334
01335     if((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
01336     {
01337       /* Check TXDMA transfer to abort */
01338       if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
01339       {
01340         /* Disable DMA TX at SWPMI level */
01341         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
01342
01343         /* Abort the USART DMA Tx stream */
01344         if(hswpmi->hdmatx != NULL)
01345         {
01346           /* Set the SWPMI Tx DMA Abort callback :
01347              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
01348           hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
01349           /* Abort DMA TX */
01350           if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
01351           {
01352             /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
01353             hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
01354           }
01355         }
01356         else
01357         {
01358           /* Set the SWPMI state ready to be able to start again the process */
01359           hswpmi->State = HAL_SWPMI_STATE_READY;
01360
01361 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01362           hswpmi->ErrorCallback(hswpmi);
01363 #else
01364           HAL_SWPMI_ErrorCallback(hswpmi);
01365 #endif
01366         }
01367       }
01368       else
01369       {
01370         /* Set the SWPMI state ready to be able to start again the process */
01371         hswpmi->State = HAL_SWPMI_STATE_READY;
01372
01373 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01374         hswpmi->ErrorCallback(hswpmi);
01375 #else
01376         HAL_SWPMI_ErrorCallback(hswpmi);
01377 #endif
01378       }
01379     }
01380     else
01381     {
01382       /* Check RXDMA transfer to abort */
01383       if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
01384       {
01385         /* Disable DMA RX at SWPMI level */
01386         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01387
01388         /* Abort the USART DMA Rx stream */
01389         if(hswpmi->hdmarx != NULL)
01390         {
01391           /* Set the SWPMI Rx DMA Abort callback :
01392              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
01393           hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
01394           /* Abort DMA RX */
01395           if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
01396           {
01397             /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
01398             hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
01399           }
01400         }
01401         else
01402         {
01403           /* Set the SWPMI state ready to be able to start again the process */
01404           hswpmi->State = HAL_SWPMI_STATE_READY;
01405
01406 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01407           hswpmi->ErrorCallback(hswpmi);
01408 #else
01409           HAL_SWPMI_ErrorCallback(hswpmi);
01410 #endif
01411         }
01412       }
01413       else
01414       {
01415         /* Set the SWPMI state ready to be able to start again the process */
01416         hswpmi->State = HAL_SWPMI_STATE_READY;
01417
01418 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01419         hswpmi->ErrorCallback(hswpmi);
01420 #else
01421         HAL_SWPMI_ErrorCallback(hswpmi);
01422 #endif
01423       }
01424     }
01425   }
01426
01427   /* SWPMI in mode Receiver ---------------------------------------------------*/
01428   if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE)  != 0U))
01429   {
01430     SWPMI_Receive_IT(hswpmi);
01431   }
01432
01433   /* SWPMI in mode Transmitter ------------------------------------------------*/
01434   if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
01435   {
01436     SWPMI_Transmit_IT(hswpmi);
01437   }
01438
01439   /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
01440   if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
01441   {
01442     SWPMI_EndTransmit_IT(hswpmi);
01443   }
01444
01445   /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
01446   if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
01447   {
01448     SWPMI_EndReceive_IT(hswpmi);
01449   }
01450
01451   /* Both Transmission and reception complete ---------------------------------*/
01452   if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
01453   {
01454     SWPMI_EndTransmitReceive_IT(hswpmi);
01455   }
01456 }
01457
01458 /**
01459   * @brief Tx Transfer completed callback.
01460   * @param hswpmi SWPMI handle
01461   * @retval None
01462   */
01463 __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01464 {
01465   /* Prevent unused argument(s) compilation warning */
01466   UNUSED(hswpmi);
01467
01468   /* NOTE : This function should not be modified, when the callback is needed,
01469             the HAL_SWPMI_TxCpltCallback is to be implemented in the user file
01470    */
01471 }
01472
01473 /**
01474   * @brief  Tx Half Transfer completed callback.
01475   * @param  hswpmi SWPMI handle
01476   * @retval None
01477   */
01478 __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01479 {
01480   /* Prevent unused argument(s) compilation warning */
01481   UNUSED(hswpmi);
01482
01483   /* NOTE: This function should not be modified, when the callback is needed,
01484            the HAL_SWPMI_TxHalfCpltCallback is to be implemented in the user file
01485    */
01486 }
01487
01488 /**
01489   * @brief Rx Transfer completed callback.
01490   * @param hswpmi SWPMI handle
01491   * @retval None
01492   */
01493 __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01494 {
01495   /* Prevent unused argument(s) compilation warning */
01496   UNUSED(hswpmi);
01497
01498   /* NOTE : This function should not be modified, when the callback is needed,
01499             the HAL_SWPMI_RxCpltCallback is to be implemented in the user file
01500    */
01501 }
01502
01503 /**
01504   * @brief  Rx Half Transfer completed callback.
01505   * @param  hswpmi SWPMI handle
01506   * @retval None
01507   */
01508 __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01509 {
01510   /* Prevent unused argument(s) compilation warning */
01511   UNUSED(hswpmi);
01512
01513   /* NOTE: This function should not be modified, when the callback is needed,
01514            the HAL_SWPMI_RxHalfCpltCallback is to be implemented in the user file
01515    */
01516 }
01517
01518 /**
01519   * @brief SWPMI error callback.
01520   * @param hswpmi SWPMI handle
01521   * @retval None
01522   */
01523 __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
01524 {
01525   /* Prevent unused argument(s) compilation warning */
01526   UNUSED(hswpmi);
01527
01528   /* NOTE : This function should not be modified, when the callback is needed,
01529             the HAL_SWPMI_ErrorCallback is to be implemented in the user file
01530    */
01531 }
01532
01533 /**
01534   * @}
01535   */
01536
01537 /** @defgroup SWPMI_Exported_Group4 Peripheral Control methods
01538   *  @brief   SWPMI control functions
01539   *
01540 @verbatim
01541  ===============================================================================
01542                       ##### Peripheral Control methods #####
01543  ===============================================================================
01544     [..]
01545     This subsection provides a set of functions allowing to control the SWPMI.
01546      (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
01547      (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral
01548 @endverbatim
01549   * @{
01550   */
01551
01552 /**
01553   * @brief Return the SWPMI handle state.
01554   * @param hswpmi SWPMI handle
01555   * @retval HAL state
01556   */
01557 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
01558 {
01559   /* Return SWPMI handle state */
01560   return hswpmi->State;
01561 }
01562
01563 /**
01564 * @brief  Return the SWPMI error code.
01565 * @param  hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains
01566   *              the configuration information for the specified SWPMI.
01567 * @retval SWPMI Error Code
01568 */
01569 uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
01570 {
01571   return hswpmi->ErrorCode;
01572 }
01573
01574 /**
01575   * @}
01576   */
01577
01578 /**
01579   * @}
01580   */
01581
01582 /* Private functions ---------------------------------------------------------*/
01583
01584 /** @defgroup SWPMI_Private_Functions SWPMI Private Functions
01585   * @{
01586   */
01587
01588 /**
01589   * @brief Transmit an amount of data in interrupt mode.
01590   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
01591   * @param  hswpmi SWPMI handle
01592   * @retval None
01593   */
01594 static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
01595 {
01596   HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
01597
01598   if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
01599   {
01600     if(hswpmi->TxXferCount == 0U)
01601     {
01602       /* Disable the SWPMI TXE and Underrun Interrupts */
01603       CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
01604     }
01605     else
01606     {
01607       hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr;
01608       hswpmi->pTxBuffPtr++;
01609       hswpmi->TxXferCount--;
01610     }
01611   }
01612   else
01613   {
01614     /* nothing to do */
01615   }
01616 }
01617
01618 /**
01619   * @brief  Wraps up transmission in non-blocking mode.
01620   * @param  hswpmi SWPMI handle
01621   * @retval None
01622   */
01623 static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
01624 {
01625   /* Clear the SWPMI Transmit buffer empty Flag */
01626   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
01627   /* Disable the all SWPMI Transmit Interrupts  */
01628   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
01629
01630   /* Check if a receive Process is ongoing or not */
01631   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01632   {
01633     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01634   }
01635   else
01636   {
01637     hswpmi->State = HAL_SWPMI_STATE_READY;
01638   }
01639
01640 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01641   hswpmi->TxCpltCallback(hswpmi);
01642 #else
01643   HAL_SWPMI_TxCpltCallback(hswpmi);
01644 #endif
01645 }
01646
01647 /**
01648   * @brief Receive an amount of data in interrupt mode.
01649   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
01650   * @param  hswpmi SWPMI handle
01651   * @retval None
01652   */
01653 static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
01654 {
01655   HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
01656
01657   if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
01658   {
01659     *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR);
01660     hswpmi->pRxBuffPtr++;
01661
01662     --hswpmi->RxXferCount;
01663     if(hswpmi->RxXferCount == 0U)
01664     {
01665       /* Wait for RXBFF flag to update state */
01666 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01667       hswpmi->RxCpltCallback(hswpmi);
01668 #else
01669       HAL_SWPMI_RxCpltCallback(hswpmi);
01670 #endif
01671     }
01672   }
01673   else
01674   {
01675     /* nothing to do */
01676   }
01677 }
01678
01679 /**
01680   * @brief  Wraps up reception in non-blocking mode.
01681   * @param  hswpmi SWPMI handle
01682   * @retval None
01683   */
01684 static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01685 {
01686   /* Clear the SWPMI Receive buffer full Flag */
01687   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
01688   /* Disable the all SWPMI Receive Interrupts  */
01689   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
01690
01691   /* Check if a transmit Process is ongoing or not */
01692   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01693   {
01694     hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01695   }
01696   else
01697   {
01698     hswpmi->State = HAL_SWPMI_STATE_READY;
01699   }
01700 }
01701
01702 /**
01703   * @brief  Wraps up transmission and reception in non-blocking mode.
01704   * @param  hswpmi SWPMI handle
01705   * @retval None
01706   */
01707 static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01708 {
01709   /* Clear the SWPMI Transmission Complete Flag */
01710   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
01711   /* Disable the SWPMI Transmission  Complete Interrupt */
01712   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
01713
01714   /* Check if a receive Process is ongoing or not */
01715   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01716   {
01717     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01718   }
01719   else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
01720   {
01721     hswpmi->State = HAL_SWPMI_STATE_READY;
01722   }
01723   else
01724   {
01725     /* nothing to do */
01726   }
01727 }
01728
01729 /**
01730   * @brief DMA SWPMI transmit process complete callback.
01731   * @param hdma DMA handle
01732   * @retval None
01733   */
01734 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01735 {
01736   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01737   uint32_t tickstart;
01738
01739   /* DMA Normal mode*/
01740   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
01741   {
01742     hswpmi->TxXferCount = 0U;
01743
01744     /* Disable the DMA transfer for transmit request by setting the TXDMA bit
01745     in the SWPMI CR register */
01746     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
01747
01748     /* Init tickstart for timeout managment*/
01749     tickstart = HAL_GetTick();
01750
01751     /* Wait the TXBEF */
01752     if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
01753     {
01754       /* Timeout occurred */
01755       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
01756
01757 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01758       hswpmi->ErrorCallback(hswpmi);
01759 #else
01760       HAL_SWPMI_ErrorCallback(hswpmi);
01761 #endif
01762     }
01763     else
01764     {
01765       /* No Timeout */
01766       /* Check if a receive process is ongoing or not */
01767       if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01768       {
01769         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01770       }
01771       else
01772       {
01773         hswpmi->State = HAL_SWPMI_STATE_READY;
01774       }
01775
01776 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01777       hswpmi->TxCpltCallback(hswpmi);
01778 #else
01779       HAL_SWPMI_TxCpltCallback(hswpmi);
01780 #endif
01781     }
01782   }
01783   /* DMA Circular mode */
01784   else
01785   {
01786 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01787     hswpmi->TxCpltCallback(hswpmi);
01788 #else
01789     HAL_SWPMI_TxCpltCallback(hswpmi);
01790 #endif
01791   }
01792 }
01793
01794 /**
01795   * @brief DMA SWPMI transmit process half complete callback.
01796   * @param hdma DMA handle
01797   * @retval None
01798   */
01799 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01800 {
01801   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01802
01803 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01804   hswpmi->TxHalfCpltCallback(hswpmi);
01805 #else
01806   HAL_SWPMI_TxHalfCpltCallback(hswpmi);
01807 #endif
01808 }
01809
01810
01811 /**
01812   * @brief DMA SWPMI receive process complete callback.
01813   * @param hdma DMA handle
01814   * @retval None
01815   */
01816 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01817 {
01818   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01819
01820   /* DMA Normal mode*/
01821   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
01822   {
01823     hswpmi->RxXferCount = 0U;
01824
01825     /* Disable the DMA transfer for the receiver request by setting the RXDMA bit
01826     in the SWPMI CR register */
01827     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01828
01829     /* Check if a transmit Process is ongoing or not */
01830     if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01831     {
01832       hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01833     }
01834     else
01835     {
01836       hswpmi->State = HAL_SWPMI_STATE_READY;
01837     }
01838   }
01839 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01840   hswpmi->RxCpltCallback(hswpmi);
01841 #else
01842   HAL_SWPMI_RxCpltCallback(hswpmi);
01843 #endif
01844 }
01845
01846 /**
01847   * @brief DMA SWPMI receive process half complete callback.
01848   * @param hdma DMA handle
01849   * @retval None
01850   */
01851 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01852 {
01853   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01854
01855 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01856   hswpmi->RxHalfCpltCallback(hswpmi);
01857 #else
01858   HAL_SWPMI_RxHalfCpltCallback(hswpmi);
01859 #endif
01860 }
01861
01862 /**
01863   * @brief DMA SWPMI communication error callback.
01864   * @param hdma DMA handle
01865   * @retval None
01866   */
01867 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
01868 {
01869   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01870
01871   /* Update handle */
01872   hswpmi->RxXferCount = 0U;
01873   hswpmi->TxXferCount = 0U;
01874   hswpmi->State= HAL_SWPMI_STATE_READY;
01875   hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
01876
01877 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01878   hswpmi->ErrorCallback(hswpmi);
01879 #else
01880   HAL_SWPMI_ErrorCallback(hswpmi);
01881 #endif
01882 }
01883
01884 /**
01885   * @brief DMA SWPMI communication abort callback.
01886   * @param hdma DMA handle
01887   * @retval None
01888   */
01889 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01890 {
01891   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01892
01893   /* Update handle */
01894   hswpmi->RxXferCount = 0U;
01895   hswpmi->TxXferCount = 0U;
01896   hswpmi->State= HAL_SWPMI_STATE_READY;
01897
01898 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
01899   hswpmi->ErrorCallback(hswpmi);
01900 #else
01901   HAL_SWPMI_ErrorCallback(hswpmi);
01902 #endif
01903 }
01904
01905 /**
01906   * @brief  Handle SWPMI Communication Timeout.
01907   * @param  hswpmi SWPMI handle
01908   * @param  Flag: specifies the SWPMI flag to check.
01909   * @param  Tickstart Tick start value
01910   * @param  Timeout timeout duration.
01911   * @retval HAL status
01912   */
01913 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
01914 {
01915   HAL_StatusTypeDef status = HAL_OK;
01916
01917   /* Wait until flag is set */
01918   while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
01919   {
01920     /* Check for the Timeout */
01921     if ((((HAL_GetTick() - Tickstart) >  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01922     {
01923       /* Set the SWPMI state ready to be able to start again the process */
01924       hswpmi->State = HAL_SWPMI_STATE_READY;
01925
01926       status = HAL_TIMEOUT;
01927       break;
01928     }
01929   }
01930
01931   return status;
01932 }
01933
01934 /**
01935   * @}
01936   */
01937
01938 #endif /* HAL_SWPMI_MODULE_ENABLED */
01939
01940 /**
01941   * @}
01942   */
01943
01944
01945 /**
01946   * @}
01947   */
01948
01949 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_swpmi.h Source File

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stm32h7xx_hal_swpmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_swpmi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SWPMI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_SWPMI_H
00022 #define STM32H7xx_HAL_SWPMI_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035
00036 /** @addtogroup SWPMI
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup SWPMI_Exported_Types SWPMI Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief SWPMI Init Structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.
00051                                           This parameter can be a value of @ref SWPMI_Voltage_Class */
00052
00053   uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.
00054                                           This parameter must be a number between 0 and 255U.
00055                                           The Bitrate is computed using the following formula:
00056                                           SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00057                                           */
00058
00059   uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.
00060                                           This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
00061
00062   uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
00063                                           This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
00064
00065 }SWPMI_InitTypeDef;
00066
00067
00068 /**
00069   * @brief HAL SWPMI State structures definition
00070   */
00071 typedef enum
00072 {
00073   HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */
00074   HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
00075   HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
00076   HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
00077   HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
00078   HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00079   HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
00080   HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
00081 }HAL_SWPMI_StateTypeDef;
00082
00083 /**
00084   * @brief  SWPMI handle Structure definition
00085   */
00086 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00087 typedef struct __SWPMI_HandleTypeDef
00088 #else
00089 typedef struct
00090 #endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */
00091 {
00092   SWPMI_TypeDef                  *Instance;     /*!< SWPMI registers base address         */
00093
00094   SWPMI_InitTypeDef              Init;          /*!< SWPMI communication parameters       */
00095
00096   uint32_t                       *pTxBuffPtr;   /*!< Pointer to SWPMI Tx transfer Buffer  */
00097
00098   uint32_t                       TxXferSize;    /*!< SWPMI Tx Transfer size               */
00099
00100   uint32_t                       TxXferCount;   /*!< SWPMI Tx Transfer Counter            */
00101
00102   uint32_t                       *pRxBuffPtr;   /*!< Pointer to SWPMI Rx transfer Buffer  */
00103
00104   uint32_t                       RxXferSize;    /*!< SWPMI Rx Transfer size               */
00105
00106   uint32_t                       RxXferCount;   /*!< SWPMI Rx Transfer Counter            */
00107
00108   DMA_HandleTypeDef              *hdmatx;       /*!< SWPMI Tx DMA Handle parameters       */
00109
00110   DMA_HandleTypeDef              *hdmarx;       /*!< SWPMI Rx DMA Handle parameters       */
00111
00112   HAL_LockTypeDef                Lock;          /*!< SWPMI object                         */
00113
00114   __IO HAL_SWPMI_StateTypeDef    State;         /*!< SWPMI communication state            */
00115
00116   __IO uint32_t                  ErrorCode;     /*!< SWPMI Error code                     */
00117
00118 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00119   void (*RxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
00120   void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
00121   void (*TxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
00122   void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
00123   void (*ErrorCallback)      (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
00124   void (*MspInitCallback)    (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
00125   void (*MspDeInitCallback)  (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
00126 #endif
00127
00128 }SWPMI_HandleTypeDef;
00129
00130 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00131 /**
00132   * @brief  SWPMI callback ID enumeration definition
00133   */
00134 typedef enum
00135 {
00136   HAL_SWPMI_RX_COMPLETE_CB_ID     = 0x00U, /*!< SWPMI receive complete callback ID */
00137   HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SWPMI receive half complete callback ID */
00138   HAL_SWPMI_TX_COMPLETE_CB_ID     = 0x02U, /*!< SWPMI transmit complete callback ID */
00139   HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SWPMI transmit half complete callback ID */
00140   HAL_SWPMI_ERROR_CB_ID           = 0x04U, /*!< SWPMI error callback ID */
00141   HAL_SWPMI_MSPINIT_CB_ID         = 0x05U, /*!< SWPMI MSP init callback ID */
00142   HAL_SWPMI_MSPDEINIT_CB_ID       = 0x06U  /*!< SWPMI MSP de-init callback ID */
00143 }HAL_SWPMI_CallbackIDTypeDef;
00144
00145 /**
00146   * @brief  SWPMI callback pointer definition
00147   */
00148 typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi);
00149 #endif
00150
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported constants --------------------------------------------------------*/
00156 /** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
00157   * @{
00158   */
00159
00160 /**
00161   * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
00162   * @{
00163   */
00164 #define HAL_SWPMI_ERROR_NONE                  ((uint32_t)0x00000000) /*!< No error              */
00165 #define HAL_SWPMI_ERROR_CRC                   ((uint32_t)0x00000004) /*!< frame error           */
00166 #define HAL_SWPMI_ERROR_OVR                   ((uint32_t)0x00000008) /*!< Overrun error         */
00167 #define HAL_SWPMI_ERROR_UDR                   ((uint32_t)0x0000000C) /*!< Underrun error        */
00168 #define HAL_SWPMI_ERROR_DMA                   ((uint32_t)0x00000010) /*!< DMA transfer error    */
00169 #define HAL_SWPMI_ERROR_TIMEOUT               ((uint32_t)0x00000020) /*!< Transfer timeout      */
00170 #define HAL_SWPMI_ERROR_TXBEF_TIMEOUT         ((uint32_t)0x00000040) /*!< End Tx buffer timeout */
00171 #define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */
00172 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00173 #define HAL_SWPMI_ERROR_INVALID_CALLBACK      ((uint32_t)0x00000100) /*!< Invalid callback error */
00174 #endif
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
00180   * @{
00181   */
00182 #define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)
00183 #define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
00189   * @{
00190   */
00191 #define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00192 #define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00193 #define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
00199   * @{
00200   */
00201 #define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00202 #define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00203 #define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup SWPMI_Flags SWPMI Status Flags
00209   *        Elements values convention: 0xXXXXXXXX
00210   *           - 0xXXXXXXXX  : Flag mask in the ISR register
00211   * @{
00212   */
00213 #define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF
00214 #define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF
00215 #define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF
00216 #define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF
00217 #define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF
00218 #define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE
00219 #define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE
00220 #define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF
00221 #define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF
00222 #define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP
00223 #define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF
00224 #define SWPMI_FLAG_RDYF                  SWPMI_ISR_RDYF
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
00230   *        Elements values convention: 0xXXXX
00231   *           - 0xXXXX  : Flag mask in the IER register
00232   * @{
00233   */
00234 #define SWPMI_IT_RDYIE                   SWPMI_IER_RDYIE
00235 #define SWPMI_IT_SRIE                    SWPMI_IER_SRIE
00236 #define SWPMI_IT_TCIE                    SWPMI_IER_TCIE
00237 #define SWPMI_IT_TIE                     SWPMI_IER_TIE
00238 #define SWPMI_IT_RIE                     SWPMI_IER_RIE
00239 #define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE
00240 #define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE
00241 #define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE
00242 #define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE
00243 #define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE
00244 /**
00245   * @}
00246   */
00247
00248 /**
00249   * @}
00250   */
00251
00252 /* Exported macros -----------------------------------------------------------*/
00253 /** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
00254   * @{
00255   */
00256
00257 /** @brief Reset SWPMI handle state.
00258   * @param  __HANDLE__ specifies the SWPMI Handle.
00259   * @retval None
00260   */
00261 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00262 #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00263                                                      (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \
00264                                                      (__HANDLE__)->MspInitCallback = NULL;        \
00265                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
00266                                                    } while(0)
00267 #else
00268 #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
00269 #endif
00270
00271 /**
00272   * @brief  Enable the SWPMI peripheral.
00273   * @param  __HANDLE__ SWPMI handle
00274   * @retval None
00275   */
00276 #define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00277
00278 /**
00279   * @brief  Disable the SWPMI peripheral.
00280   * @param  __HANDLE__ SWPMI handle
00281   * @retval None
00282   */
00283 #define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00284
00285 /**
00286   * @brief  Enable the SWPMI transceiver.
00287   * @param  __HANDLE__ SWPMI handle
00288   * @retval None
00289   */
00290 #define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
00291
00292 /**
00293   * @brief  Disable the SWPMI transceiver.
00294   * @param  __HANDLE__ SWPMI handle
00295   * @retval None
00296   */
00297 #define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
00298
00299 /** @brief  Check whether the specified SWPMI flag is set or not.
00300   * @param  __HANDLE__ specifies the SWPMI Handle.
00301   * @param  __FLAG__: specifies the flag to check.
00302   *        This parameter can be one of the following values:
00303   *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.
00304   *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.
00305   *            @arg SWPMI_FLAG_RXBERF  Receive CRC error flag.
00306   *            @arg SWPMI_FLAG_RXOVRF  Receive overrun error flag.
00307   *            @arg SWPMI_FLAG_TXUNRF  Transmit underrun error flag.
00308   *            @arg SWPMI_FLAG_RXNE  Receive data register not empty.
00309   *            @arg SWPMI_FLAG_TXE  Transmit data register empty.
00310   *            @arg SWPMI_FLAG_TCF  Transfer complete flag.
00311   *            @arg SWPMI_FLAG_SRF  Slave resume flag.
00312   *            @arg SWPMI_FLAG_SUSP  SUSPEND flag.
00313   *            @arg SWPMI_FLAG_DEACTF  DEACTIVATED flag.
00314   *            @arg SWPMI_FLAG_RDYF  Transceiver ready flag.
00315   * @retval The new state of __FLAG__ (TRUE or FALSE).
00316   */
00317 #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
00318
00319 /** @brief  Clear the specified SWPMI ISR flag.
00320   * @param  __HANDLE__ specifies the SWPMI Handle.
00321   * @param  __FLAG__: specifies the flag to clear.
00322   *        This parameter can be one of the following values:
00323   *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.
00324   *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.
00325   *            @arg SWPMI_FLAG_RXBERF  Receive CRC error flag.
00326   *            @arg SWPMI_FLAG_RXOVRF  Receive overrun error flag.
00327   *            @arg SWPMI_FLAG_TXUNRF  Transmit underrun error flag.
00328   *            @arg SWPMI_FLAG_TCF  Transfer complete flag.
00329   *            @arg SWPMI_FLAG_SRF  Slave resume flag.
00330   *            @arg SWPMI_FLAG_RDYF  Transceiver ready flag.
00331   * @retval None
00332   */
00333 #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
00334
00335 /** @brief  Enable the specified SWPMI interrupt.
00336   * @param  __HANDLE__ specifies the SWPMI Handle.
00337   * @param  __INTERRUPT__ specifies the SWPMI interrupt source to enable.
00338   *          This parameter can be one of the following values:
00339   *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.
00340   *            @arg SWPMI_IT_SRIE  Slave resume interrupt.
00341   *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.
00342   *            @arg SWPMI_IT_TIE   Transmit interrupt.
00343   *            @arg SWPMI_IT_RIE   Receive interrupt.
00344   *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.
00345   *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.
00346   *            @arg SWPMI_IT_RXBEIE  Receive CRC error interrupt.
00347   *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.
00348   *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.
00349   * @retval None
00350   */
00351 #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00352
00353 /** @brief  Disable the specified SWPMI interrupt.
00354   * @param  __HANDLE__ specifies the SWPMI Handle.
00355   * @param  __INTERRUPT__ specifies the SWPMI interrupt source to disable.
00356   *          This parameter can be one of the following values:
00357   *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.
00358   *            @arg SWPMI_IT_SRIE  Slave resume interrupt.
00359   *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.
00360   *            @arg SWPMI_IT_TIE   Transmit interrupt.
00361   *            @arg SWPMI_IT_RIE   Receive interrupt.
00362   *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.
00363   *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.
00364   *            @arg SWPMI_IT_RXBEIE  Receive CRC error interrupt.
00365   *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.
00366   *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.
00367   * @retval None
00368   */
00369 #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00370
00371 /** @brief  Check whether the specified SWPMI interrupt has occurred or not.
00372   * @param  __HANDLE__ specifies the SWPMI Handle.
00373   * @param  __IT__ specifies the SWPMI interrupt to check.
00374   *          This parameter can be one of the following values:
00375   *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.
00376   *            @arg SWPMI_IT_SRIE  Slave resume interrupt.
00377   *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.
00378   *            @arg SWPMI_IT_TIE   Transmit interrupt.
00379   *            @arg SWPMI_IT_RIE   Receive interrupt.
00380   *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.
00381   *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.
00382   *            @arg SWPMI_IT_RXBERIE  Receive CRC error interrupt.
00383   *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.
00384   *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.
00385   * @retval The new state of __IT__ (TRUE or FALSE).
00386   */
00387 #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
00388
00389 /** @brief  Check whether the specified SWPMI interrupt source is enabled or not.
00390   * @param  __HANDLE__ specifies the SWPMI Handle.
00391   * @param  __IT__ specifies the SWPMI interrupt source to check.
00392   *          This parameter can be one of the following values:
00393   *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.
00394   *            @arg SWPMI_IT_SRIE  Slave resume interrupt.
00395   *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.
00396   *            @arg SWPMI_IT_TIE   Transmit interrupt.
00397   *            @arg SWPMI_IT_RIE   Receive interrupt.
00398   *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.
00399   *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.
00400   *            @arg SWPMI_IT_RXBERIE  Receive CRC error interrupt.
00401   *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.
00402   *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.
00403   * @retval The new state of __IT__ (TRUE or FALSE).
00404   */
00405 #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
00406
00407 /**
00408   * @}
00409   */
00410
00411 /* Exported functions --------------------------------------------------------*/
00412 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00413   * @{
00414   */
00415 /* Initialization/de-initialization functions  ********************************/
00416 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
00417 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
00418 void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
00419 void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
00420
00421 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
00422 /* SWPMI callbacks register/unregister functions ********************************/
00423 HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
00424                                              HAL_SWPMI_CallbackIDTypeDef CallbackID,
00425                                              pSWPMI_CallbackTypeDef      pCallback);
00426 HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
00427                                                HAL_SWPMI_CallbackIDTypeDef CallbackID);
00428 #endif
00429
00430 /* IO operation functions *****************************************************/
00431 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00432 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00433 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00434 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00435 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00436 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00437 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
00438 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
00439 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
00440 void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
00441 void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00442 void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00443 void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00444 void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00445 void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
00446
00447 /* Peripheral Control and State functions  ************************************/
00448 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
00449 uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
00450
00451 /**
00452   * @}
00453   */
00454
00455 /* Private types -------------------------------------------------------------*/
00456 /** @defgroup SWPMI_Private_Types SWPMI Private Types
00457   * @{
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /* Private variables ---------------------------------------------------------*/
00465 /** @defgroup SWPMI_Private_Variables SWPMI Private Variables
00466   * @{
00467   */
00468
00469 /**
00470   * @}
00471   */
00472
00473 /* Private constants ---------------------------------------------------------*/
00474 /** @defgroup SWPMI_Private_Constants SWPMI Private Constants
00475   * @{
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Private macros ------------------------------------------------------------*/
00483 /** @defgroup SWPMI_Private_Macros SWPMI Private Macros
00484   * @{
00485   */
00486
00487
00488 #define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
00489                                               ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
00490
00491 #define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 255U))
00492
00493
00494 #define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
00495                                               ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
00496
00497
00498 #define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
00499                                               ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
00500
00501 /**
00502   * @}
00503   */
00504
00505 /**
00506   * @}
00507   */
00508
00509
00510 /**
00511   * @}
00512   */
00513
00514 #ifdef __cplusplus
00515 }
00516 #endif
00517
00518 #endif /* STM32H7xx_HAL_SWPMI_H */
00519
00520 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim.c Source File

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stm32h7xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer (TIM) peripheral:
00008   *           + TIM Time Base Initialization
00009   *           + TIM Time Base Start
00010   *           + TIM Time Base Start Interruption
00011   *           + TIM Time Base Start DMA
00012   *           + TIM Output Compare/PWM Initialization
00013   *           + TIM Output Compare/PWM Channel Configuration
00014   *           + TIM Output Compare/PWM  Start
00015   *           + TIM Output Compare/PWM  Start Interruption
00016   *           + TIM Output Compare/PWM Start DMA
00017   *           + TIM Input Capture Initialization
00018   *           + TIM Input Capture Channel Configuration
00019   *           + TIM Input Capture Start
00020   *           + TIM Input Capture Start Interruption
00021   *           + TIM Input Capture Start DMA
00022   *           + TIM One Pulse Initialization
00023   *           + TIM One Pulse Channel Configuration
00024   *           + TIM One Pulse Start
00025   *           + TIM Encoder Interface Initialization
00026   *           + TIM Encoder Interface Start
00027   *           + TIM Encoder Interface Start Interruption
00028   *           + TIM Encoder Interface Start DMA
00029   *           + Commutation Event configuration with Interruption and DMA
00030   *           + TIM OCRef clear configuration
00031   *           + TIM External Clock configuration
00032   @verbatim
00033   ==============================================================================
00034                       ##### TIMER Generic features #####
00035   ==============================================================================
00036   [..] The Timer features include:
00037        (#) 16-bit up, down, up/down auto-reload counter.
00038        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00039            counter clock frequency either by any factor between 1 and 65536.
00040        (#) Up to 4 independent channels for:
00041            (++) Input Capture
00042            (++) Output Compare
00043            (++) PWM generation (Edge and Center-aligned Mode)
00044            (++) One-pulse mode output
00045        (#) Synchronization circuit to control the timer with external signals and to interconnect
00046             several timers together.
00047        (#) Supports incremental encoder for positioning purposes
00048
00049             ##### How to use this driver #####
00050   ==============================================================================
00051     [..]
00052      (#) Initialize the TIM low level resources by implementing the following functions
00053          depending on the selected feature:
00054            (++) Time Base : HAL_TIM_Base_MspInit()
00055            (++) Input Capture : HAL_TIM_IC_MspInit()
00056            (++) Output Compare : HAL_TIM_OC_MspInit()
00057            (++) PWM generation : HAL_TIM_PWM_MspInit()
00058            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00059            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00060
00061      (#) Initialize the TIM low level resources :
00062         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00063         (##) TIM pins configuration
00064             (+++) Enable the clock for the TIM GPIOs using the following function:
00065              __HAL_RCC_GPIOx_CLK_ENABLE();
00066             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00067
00068      (#) The external Clock can be configured, if needed (the default clock is the
00069          internal clock from the APBx), using the following function:
00070          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00071          any start function.
00072
00073      (#) Configure the TIM in the desired functioning mode using one of the
00074        Initialization function of this driver:
00075        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00076        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00077             Output Compare signal.
00078        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00079             PWM signal.
00080        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00081             external signal.
00082        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00083             in One Pulse Mode.
00084        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00085
00086      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00087            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00088            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00089            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00090            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00091            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00092            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00093
00094      (#) The DMA Burst is managed with the two following functions:
00095          HAL_TIM_DMABurst_WriteStart()
00096          HAL_TIM_DMABurst_ReadStart()
00097
00098     *** Callback registration ***
00099   =============================================
00100
00101   [..]
00102   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
00103   allows the user to configure dynamically the driver callbacks.
00104
00105   [..]
00106   Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
00107   @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00108   the Callback ID and a pointer to the user callback function.
00109
00110   [..]
00111   Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
00112   weak function.
00113   @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00114   and the Callback ID.
00115
00116   [..]
00117   These functions allow to register/unregister following callbacks:
00118     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
00119     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
00120     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
00121     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
00122     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
00123     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
00124     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
00125     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
00126     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
00127     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
00128     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
00129     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
00130     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
00131     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
00132     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
00133     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
00134     (+) TriggerCallback                   : TIM Trigger Callback.
00135     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
00136     (+) IC_CaptureCallback                : TIM Input Capture Callback.
00137     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
00138     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
00139     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
00140     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
00141     (+) ErrorCallback                     : TIM Error Callback.
00142     (+) CommutationCallback               : TIM Commutation Callback.
00143     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
00144     (+) BreakCallback                     : TIM Break Callback.
00145     (+) Break2Callback                    : TIM Break2 Callback.
00146
00147   [..]
00148 By default, after the Init and when the state is HAL_TIM_STATE_RESET
00149 all interrupt callbacks are set to the corresponding weak functions:
00150   examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
00151
00152   [..]
00153   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00154   functionalities in the Init / DeInit only when these callbacks are null
00155   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
00156     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
00157
00158   [..]
00159     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
00160     Exception done MspInit / MspDeInit that can be registered / unregistered
00161     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
00162     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
00163   In that case first register the MspInit/MspDeInit user callbacks
00164       using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
00165
00166   [..]
00167       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
00168       not defined, the callback registration feature is not available and all callbacks
00169       are set to the corresponding weak functions.
00170
00171   @endverbatim
00172   ******************************************************************************
00173   * @attention
00174   *
00175   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00176   * All rights reserved.</center></h2>
00177   *
00178   * This software component is licensed by ST under BSD 3-Clause license,
00179   * the "License"; You may not use this file except in compliance with the
00180   * License. You may obtain a copy of the License at:
00181   *                        opensource.org/licenses/BSD-3-Clause
00182   *
00183   ******************************************************************************
00184   */
00185
00186 /* Includes ------------------------------------------------------------------*/
00187 #include "stm32h7xx_hal.h"
00188
00189 /** @addtogroup STM32H7xx_HAL_Driver
00190   * @{
00191   */
00192
00193 /** @defgroup TIM TIM
00194   * @brief TIM HAL module driver
00195   * @{
00196   */
00197
00198 #ifdef HAL_TIM_MODULE_ENABLED
00199
00200 /* Private typedef -----------------------------------------------------------*/
00201 /* Private define ------------------------------------------------------------*/
00202 /* Private macro -------------------------------------------------------------*/
00203 /* Private variables ---------------------------------------------------------*/
00204 /* Private function prototypes -----------------------------------------------*/
00205 /** @addtogroup TIM_Private_Functions
00206   * @{
00207   */
00208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00214 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00215                               uint32_t TIM_ICFilter);
00216 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00217 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00218                               uint32_t TIM_ICFilter);
00219 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00220                               uint32_t TIM_ICFilter);
00221 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
00222 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00223 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
00224 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00225 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
00226 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00227                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
00228 /**
00229   * @}
00230   */
00231 /* Exported functions --------------------------------------------------------*/
00232
00233 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00234   * @{
00235   */
00236
00237 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
00238   *  @brief    Time Base functions
00239   *
00240 @verbatim
00241   ==============================================================================
00242               ##### Time Base functions #####
00243   ==============================================================================
00244   [..]
00245     This section provides functions allowing to:
00246     (+) Initialize and configure the TIM base.
00247     (+) De-initialize the TIM base.
00248     (+) Start the Time Base.
00249     (+) Stop the Time Base.
00250     (+) Start the Time Base and enable interrupt.
00251     (+) Stop the Time Base and disable interrupt.
00252     (+) Start the Time Base and enable DMA transfer.
00253     (+) Stop the Time Base and disable DMA transfer.
00254
00255 @endverbatim
00256   * @{
00257   */
00258 /**
00259   * @brief  Initializes the TIM Time base Unit according to the specified
00260   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00261   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00262   *         requires a timer reset to avoid unexpected direction
00263   *         due to DIR bit readonly in center aligned mode.
00264   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
00265   * @param  htim TIM Base handle
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00269 {
00270   /* Check the TIM handle allocation */
00271   if (htim == NULL)
00272   {
00273     return HAL_ERROR;
00274   }
00275
00276   /* Check the parameters */
00277   assert_param(IS_TIM_INSTANCE(htim->Instance));
00278   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00279   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00280   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00281
00282   if (htim->State == HAL_TIM_STATE_RESET)
00283   {
00284     /* Allocate lock resource and initialize it */
00285     htim->Lock = HAL_UNLOCKED;
00286
00287 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00288     /* Reset interrupt callbacks to legacy weak callbacks */
00289     TIM_ResetCallback(htim);
00290
00291     if (htim->Base_MspInitCallback == NULL)
00292     {
00293       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
00294     }
00295     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00296     htim->Base_MspInitCallback(htim);
00297 #else
00298     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00299     HAL_TIM_Base_MspInit(htim);
00300 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00301   }
00302
00303   /* Set the TIM state */
00304   htim->State = HAL_TIM_STATE_BUSY;
00305
00306   /* Set the Time Base configuration */
00307   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00308
00309   /* Initialize the TIM state*/
00310   htim->State = HAL_TIM_STATE_READY;
00311
00312   return HAL_OK;
00313 }
00314
00315 /**
00316   * @brief  DeInitializes the TIM Base peripheral
00317   * @param  htim TIM Base handle
00318   * @retval HAL status
00319   */
00320 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00321 {
00322   /* Check the parameters */
00323   assert_param(IS_TIM_INSTANCE(htim->Instance));
00324
00325   htim->State = HAL_TIM_STATE_BUSY;
00326
00327   /* Disable the TIM Peripheral Clock */
00328   __HAL_TIM_DISABLE(htim);
00329
00330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00331   if (htim->Base_MspDeInitCallback == NULL)
00332   {
00333     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
00334   }
00335   /* DeInit the low level hardware */
00336   htim->Base_MspDeInitCallback(htim);
00337 #else
00338   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00339   HAL_TIM_Base_MspDeInit(htim);
00340 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00341
00342   /* Change TIM state */
00343   htim->State = HAL_TIM_STATE_RESET;
00344
00345   /* Release Lock */
00346   __HAL_UNLOCK(htim);
00347
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Initializes the TIM Base MSP.
00353   * @param  htim TIM Base handle
00354   * @retval None
00355   */
00356 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00357 {
00358   /* Prevent unused argument(s) compilation warning */
00359   UNUSED(htim);
00360
00361   /* NOTE : This function should not be modified, when the callback is needed,
00362             the HAL_TIM_Base_MspInit could be implemented in the user file
00363    */
00364 }
00365
00366 /**
00367   * @brief  DeInitializes TIM Base MSP.
00368   * @param  htim TIM Base handle
00369   * @retval None
00370   */
00371 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00372 {
00373   /* Prevent unused argument(s) compilation warning */
00374   UNUSED(htim);
00375
00376   /* NOTE : This function should not be modified, when the callback is needed,
00377             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00378    */
00379 }
00380
00381
00382 /**
00383   * @brief  Starts the TIM Base generation.
00384   * @param  htim TIM Base handle
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00388 {
00389   uint32_t tmpsmcr;
00390
00391   /* Check the parameters */
00392   assert_param(IS_TIM_INSTANCE(htim->Instance));
00393
00394   /* Set the TIM state */
00395   htim->State = HAL_TIM_STATE_BUSY;
00396
00397   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00398   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00399   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00400   {
00401     __HAL_TIM_ENABLE(htim);
00402   }
00403
00404   /* Change the TIM state*/
00405   htim->State = HAL_TIM_STATE_READY;
00406
00407   /* Return function status */
00408   return HAL_OK;
00409 }
00410
00411 /**
00412   * @brief  Stops the TIM Base generation.
00413   * @param  htim TIM Base handle
00414   * @retval HAL status
00415   */
00416 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00417 {
00418   /* Check the parameters */
00419   assert_param(IS_TIM_INSTANCE(htim->Instance));
00420
00421   /* Set the TIM state */
00422   htim->State = HAL_TIM_STATE_BUSY;
00423
00424   /* Disable the Peripheral */
00425   __HAL_TIM_DISABLE(htim);
00426
00427   /* Change the TIM state*/
00428   htim->State = HAL_TIM_STATE_READY;
00429
00430   /* Return function status */
00431   return HAL_OK;
00432 }
00433
00434 /**
00435   * @brief  Starts the TIM Base generation in interrupt mode.
00436   * @param  htim TIM Base handle
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00440 {
00441   uint32_t tmpsmcr;
00442
00443   /* Check the parameters */
00444   assert_param(IS_TIM_INSTANCE(htim->Instance));
00445
00446   /* Enable the TIM Update interrupt */
00447   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00448
00449   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00450   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00451   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00452   {
00453     __HAL_TIM_ENABLE(htim);
00454   }
00455
00456   /* Return function status */
00457   return HAL_OK;
00458 }
00459
00460 /**
00461   * @brief  Stops the TIM Base generation in interrupt mode.
00462   * @param  htim TIM Base handle
00463   * @retval HAL status
00464   */
00465 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00466 {
00467   /* Check the parameters */
00468   assert_param(IS_TIM_INSTANCE(htim->Instance));
00469   /* Disable the TIM Update interrupt */
00470   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00471
00472   /* Disable the Peripheral */
00473   __HAL_TIM_DISABLE(htim);
00474
00475   /* Return function status */
00476   return HAL_OK;
00477 }
00478
00479 /**
00480   * @brief  Starts the TIM Base generation in DMA mode.
00481   * @param  htim TIM Base handle
00482   * @param  pData The source Buffer address.
00483   * @param  Length The length of data to be transferred from memory to peripheral.
00484   * @retval HAL status
00485   */
00486 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00487 {
00488   uint32_t tmpsmcr;
00489
00490   /* Check the parameters */
00491   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00492
00493   if (htim->State == HAL_TIM_STATE_BUSY)
00494   {
00495     return HAL_BUSY;
00496   }
00497   else if (htim->State == HAL_TIM_STATE_READY)
00498   {
00499     if ((pData == NULL) && (Length > 0U))
00500     {
00501       return HAL_ERROR;
00502     }
00503     else
00504     {
00505       htim->State = HAL_TIM_STATE_BUSY;
00506     }
00507   }
00508   else
00509   {
00510     /* nothing to do */
00511   }
00512
00513   /* Set the DMA Period elapsed callbacks */
00514   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00515   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
00516
00517   /* Set the DMA error callback */
00518   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00519
00520   /* Enable the DMA stream */
00521   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
00522   {
00523     return HAL_ERROR;
00524   }
00525
00526   /* Enable the TIM Update DMA request */
00527   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00528
00529   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00530   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00531   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00532   {
00533     __HAL_TIM_ENABLE(htim);
00534   }
00535
00536   /* Return function status */
00537   return HAL_OK;
00538 }
00539
00540 /**
00541   * @brief  Stops the TIM Base generation in DMA mode.
00542   * @param  htim TIM Base handle
00543   * @retval HAL status
00544   */
00545 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00546 {
00547   /* Check the parameters */
00548   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00549
00550   /* Disable the TIM Update DMA request */
00551   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00552
00553   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
00554
00555   /* Disable the Peripheral */
00556   __HAL_TIM_DISABLE(htim);
00557
00558   /* Change the htim state */
00559   htim->State = HAL_TIM_STATE_READY;
00560
00561   /* Return function status */
00562   return HAL_OK;
00563 }
00564
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
00570   *  @brief    TIM Output Compare functions
00571   *
00572 @verbatim
00573   ==============================================================================
00574                   ##### TIM Output Compare functions #####
00575   ==============================================================================
00576   [..]
00577     This section provides functions allowing to:
00578     (+) Initialize and configure the TIM Output Compare.
00579     (+) De-initialize the TIM Output Compare.
00580     (+) Start the TIM Output Compare.
00581     (+) Stop the TIM Output Compare.
00582     (+) Start the TIM Output Compare and enable interrupt.
00583     (+) Stop the TIM Output Compare and disable interrupt.
00584     (+) Start the TIM Output Compare and enable DMA transfer.
00585     (+) Stop the TIM Output Compare and disable DMA transfer.
00586
00587 @endverbatim
00588   * @{
00589   */
00590 /**
00591   * @brief  Initializes the TIM Output Compare according to the specified
00592   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
00593   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00594   *         requires a timer reset to avoid unexpected direction
00595   *         due to DIR bit readonly in center aligned mode.
00596   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
00597   * @param  htim TIM Output Compare handle
00598   * @retval HAL status
00599   */
00600 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
00601 {
00602   /* Check the TIM handle allocation */
00603   if (htim == NULL)
00604   {
00605     return HAL_ERROR;
00606   }
00607
00608   /* Check the parameters */
00609   assert_param(IS_TIM_INSTANCE(htim->Instance));
00610   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00611   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00612   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00613
00614   if (htim->State == HAL_TIM_STATE_RESET)
00615   {
00616     /* Allocate lock resource and initialize it */
00617     htim->Lock = HAL_UNLOCKED;
00618
00619 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00620     /* Reset interrupt callbacks to legacy weak callbacks */
00621     TIM_ResetCallback(htim);
00622
00623     if (htim->OC_MspInitCallback == NULL)
00624     {
00625       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
00626     }
00627     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00628     htim->OC_MspInitCallback(htim);
00629 #else
00630     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00631     HAL_TIM_OC_MspInit(htim);
00632 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00633   }
00634
00635   /* Set the TIM state */
00636   htim->State = HAL_TIM_STATE_BUSY;
00637
00638   /* Init the base time for the Output Compare */
00639   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00640
00641   /* Initialize the TIM state*/
00642   htim->State = HAL_TIM_STATE_READY;
00643
00644   return HAL_OK;
00645 }
00646
00647 /**
00648   * @brief  DeInitializes the TIM peripheral
00649   * @param  htim TIM Output Compare handle
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00653 {
00654   /* Check the parameters */
00655   assert_param(IS_TIM_INSTANCE(htim->Instance));
00656
00657   htim->State = HAL_TIM_STATE_BUSY;
00658
00659   /* Disable the TIM Peripheral Clock */
00660   __HAL_TIM_DISABLE(htim);
00661
00662 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00663   if (htim->OC_MspDeInitCallback == NULL)
00664   {
00665     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
00666   }
00667   /* DeInit the low level hardware */
00668   htim->OC_MspDeInitCallback(htim);
00669 #else
00670   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00671   HAL_TIM_OC_MspDeInit(htim);
00672 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00673
00674   /* Change TIM state */
00675   htim->State = HAL_TIM_STATE_RESET;
00676
00677   /* Release Lock */
00678   __HAL_UNLOCK(htim);
00679
00680   return HAL_OK;
00681 }
00682
00683 /**
00684   * @brief  Initializes the TIM Output Compare MSP.
00685   * @param  htim TIM Output Compare handle
00686   * @retval None
00687   */
00688 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00689 {
00690   /* Prevent unused argument(s) compilation warning */
00691   UNUSED(htim);
00692
00693   /* NOTE : This function should not be modified, when the callback is needed,
00694             the HAL_TIM_OC_MspInit could be implemented in the user file
00695    */
00696 }
00697
00698 /**
00699   * @brief  DeInitializes TIM Output Compare MSP.
00700   * @param  htim TIM Output Compare handle
00701   * @retval None
00702   */
00703 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00704 {
00705   /* Prevent unused argument(s) compilation warning */
00706   UNUSED(htim);
00707
00708   /* NOTE : This function should not be modified, when the callback is needed,
00709             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00710    */
00711 }
00712
00713 /**
00714   * @brief  Starts the TIM Output Compare signal generation.
00715   * @param  htim TIM Output Compare handle
00716   * @param  Channel TIM Channel to be enabled
00717   *          This parameter can be one of the following values:
00718   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00719   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00720   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00721   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00722   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00723   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00724   * @retval HAL status
00725   */
00726 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00727 {
00728   uint32_t tmpsmcr;
00729
00730   /* Check the parameters */
00731   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00732
00733   /* Enable the Output compare channel */
00734   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00735
00736   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00737   {
00738     /* Enable the main output */
00739     __HAL_TIM_MOE_ENABLE(htim);
00740   }
00741
00742   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00743   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00744   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00745   {
00746     __HAL_TIM_ENABLE(htim);
00747   }
00748
00749   /* Return function status */
00750   return HAL_OK;
00751 }
00752
00753 /**
00754   * @brief  Stops the TIM Output Compare signal generation.
00755   * @param  htim TIM Output Compare handle
00756   * @param  Channel TIM Channel to be disabled
00757   *          This parameter can be one of the following values:
00758   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00759   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00760   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00761   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00762   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00763   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00764   * @retval HAL status
00765   */
00766 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00767 {
00768   /* Check the parameters */
00769   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00770
00771   /* Disable the Output compare channel */
00772   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00773
00774   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00775   {
00776     /* Disable the Main Output */
00777     __HAL_TIM_MOE_DISABLE(htim);
00778   }
00779
00780   /* Disable the Peripheral */
00781   __HAL_TIM_DISABLE(htim);
00782
00783   /* Return function status */
00784   return HAL_OK;
00785 }
00786
00787 /**
00788   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00789   * @param  htim TIM Output Compare handle
00790   * @param  Channel TIM Channel to be enabled
00791   *          This parameter can be one of the following values:
00792   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00793   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00794   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00795   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00796   * @retval HAL status
00797   */
00798 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00799 {
00800   uint32_t tmpsmcr;
00801
00802   /* Check the parameters */
00803   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00804
00805   switch (Channel)
00806   {
00807     case TIM_CHANNEL_1:
00808     {
00809       /* Enable the TIM Capture/Compare 1 interrupt */
00810       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00811       break;
00812     }
00813
00814     case TIM_CHANNEL_2:
00815     {
00816       /* Enable the TIM Capture/Compare 2 interrupt */
00817       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00818       break;
00819     }
00820
00821     case TIM_CHANNEL_3:
00822     {
00823       /* Enable the TIM Capture/Compare 3 interrupt */
00824       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00825       break;
00826     }
00827
00828     case TIM_CHANNEL_4:
00829     {
00830       /* Enable the TIM Capture/Compare 4 interrupt */
00831       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00832       break;
00833     }
00834
00835     default:
00836       break;
00837   }
00838
00839   /* Enable the Output compare channel */
00840   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00841
00842   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00843   {
00844     /* Enable the main output */
00845     __HAL_TIM_MOE_ENABLE(htim);
00846   }
00847
00848   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00849   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00850   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00851   {
00852     __HAL_TIM_ENABLE(htim);
00853   }
00854
00855   /* Return function status */
00856   return HAL_OK;
00857 }
00858
00859 /**
00860   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00861   * @param  htim TIM Output Compare handle
00862   * @param  Channel TIM Channel to be disabled
00863   *          This parameter can be one of the following values:
00864   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00865   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00866   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00867   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00868   * @retval HAL status
00869   */
00870 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00871 {
00872   /* Check the parameters */
00873   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00874
00875   switch (Channel)
00876   {
00877     case TIM_CHANNEL_1:
00878     {
00879       /* Disable the TIM Capture/Compare 1 interrupt */
00880       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00881       break;
00882     }
00883
00884     case TIM_CHANNEL_2:
00885     {
00886       /* Disable the TIM Capture/Compare 2 interrupt */
00887       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00888       break;
00889     }
00890
00891     case TIM_CHANNEL_3:
00892     {
00893       /* Disable the TIM Capture/Compare 3 interrupt */
00894       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00895       break;
00896     }
00897
00898     case TIM_CHANNEL_4:
00899     {
00900       /* Disable the TIM Capture/Compare 4 interrupt */
00901       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00902       break;
00903     }
00904
00905     default:
00906       break;
00907   }
00908
00909   /* Disable the Output compare channel */
00910   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00911
00912   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00913   {
00914     /* Disable the Main Output */
00915     __HAL_TIM_MOE_DISABLE(htim);
00916   }
00917
00918   /* Disable the Peripheral */
00919   __HAL_TIM_DISABLE(htim);
00920
00921   /* Return function status */
00922   return HAL_OK;
00923 }
00924
00925 /**
00926   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00927   * @param  htim TIM Output Compare handle
00928   * @param  Channel TIM Channel to be enabled
00929   *          This parameter can be one of the following values:
00930   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00931   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00932   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00933   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00934   * @param  pData The source Buffer address.
00935   * @param  Length The length of data to be transferred from memory to TIM peripheral
00936   * @retval HAL status
00937   */
00938 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00939 {
00940   uint32_t tmpsmcr;
00941
00942   /* Check the parameters */
00943   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00944
00945   if (htim->State == HAL_TIM_STATE_BUSY)
00946   {
00947     return HAL_BUSY;
00948   }
00949   else if (htim->State == HAL_TIM_STATE_READY)
00950   {
00951     if ((pData == NULL) && (Length > 0U))
00952     {
00953       return HAL_ERROR;
00954     }
00955     else
00956     {
00957       htim->State = HAL_TIM_STATE_BUSY;
00958     }
00959   }
00960   else
00961   {
00962     /* nothing to do */
00963   }
00964
00965   switch (Channel)
00966   {
00967     case TIM_CHANNEL_1:
00968     {
00969       /* Set the DMA compare callbacks */
00970       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00971       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00972
00973       /* Set the DMA error callback */
00974       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00975
00976       /* Enable the DMA stream */
00977       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
00978       {
00979         return HAL_ERROR;
00980       }
00981
00982       /* Enable the TIM Capture/Compare 1 DMA request */
00983       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00984       break;
00985     }
00986
00987     case TIM_CHANNEL_2:
00988     {
00989       /* Set the DMA compare callbacks */
00990       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00991       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00992
00993       /* Set the DMA error callback */
00994       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00995
00996       /* Enable the DMA stream */
00997       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
00998       {
00999         return HAL_ERROR;
01000       }
01001
01002       /* Enable the TIM Capture/Compare 2 DMA request */
01003       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01004       break;
01005     }
01006
01007     case TIM_CHANNEL_3:
01008     {
01009       /* Set the DMA compare callbacks */
01010       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01011       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01012
01013       /* Set the DMA error callback */
01014       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01015
01016       /* Enable the DMA stream */
01017       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01018       {
01019         return HAL_ERROR;
01020       }
01021       /* Enable the TIM Capture/Compare 3 DMA request */
01022       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01023       break;
01024     }
01025
01026     case TIM_CHANNEL_4:
01027     {
01028       /* Set the DMA compare callbacks */
01029       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01030       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01031
01032       /* Set the DMA error callback */
01033       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01034
01035       /* Enable the DMA stream */
01036       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
01037       {
01038         return HAL_ERROR;
01039       }
01040       /* Enable the TIM Capture/Compare 4 DMA request */
01041       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01042       break;
01043     }
01044
01045     default:
01046       break;
01047   }
01048
01049   /* Enable the Output compare channel */
01050   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01051
01052   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01053   {
01054     /* Enable the main output */
01055     __HAL_TIM_MOE_ENABLE(htim);
01056   }
01057
01058   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01059   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01060   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01061   {
01062     __HAL_TIM_ENABLE(htim);
01063   }
01064
01065   /* Return function status */
01066   return HAL_OK;
01067 }
01068
01069 /**
01070   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
01071   * @param  htim TIM Output Compare handle
01072   * @param  Channel TIM Channel to be disabled
01073   *          This parameter can be one of the following values:
01074   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01075   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01076   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01077   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01078   * @retval HAL status
01079   */
01080 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01081 {
01082   /* Check the parameters */
01083   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01084
01085   switch (Channel)
01086   {
01087     case TIM_CHANNEL_1:
01088     {
01089       /* Disable the TIM Capture/Compare 1 DMA request */
01090       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01091       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01092       break;
01093     }
01094
01095     case TIM_CHANNEL_2:
01096     {
01097       /* Disable the TIM Capture/Compare 2 DMA request */
01098       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01099       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01100       break;
01101     }
01102
01103     case TIM_CHANNEL_3:
01104     {
01105       /* Disable the TIM Capture/Compare 3 DMA request */
01106       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01107       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01108       break;
01109     }
01110
01111     case TIM_CHANNEL_4:
01112     {
01113       /* Disable the TIM Capture/Compare 4 interrupt */
01114       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01115       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01116       break;
01117     }
01118
01119     default:
01120       break;
01121   }
01122
01123   /* Disable the Output compare channel */
01124   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01125
01126   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01127   {
01128     /* Disable the Main Output */
01129     __HAL_TIM_MOE_DISABLE(htim);
01130   }
01131
01132   /* Disable the Peripheral */
01133   __HAL_TIM_DISABLE(htim);
01134
01135   /* Change the htim state */
01136   htim->State = HAL_TIM_STATE_READY;
01137
01138   /* Return function status */
01139   return HAL_OK;
01140 }
01141
01142 /**
01143   * @}
01144   */
01145
01146 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
01147   *  @brief    TIM PWM functions
01148   *
01149 @verbatim
01150   ==============================================================================
01151                           ##### TIM PWM functions #####
01152   ==============================================================================
01153   [..]
01154     This section provides functions allowing to:
01155     (+) Initialize and configure the TIM PWM.
01156     (+) De-initialize the TIM PWM.
01157     (+) Start the TIM PWM.
01158     (+) Stop the TIM PWM.
01159     (+) Start the TIM PWM and enable interrupt.
01160     (+) Stop the TIM PWM and disable interrupt.
01161     (+) Start the TIM PWM and enable DMA transfer.
01162     (+) Stop the TIM PWM and disable DMA transfer.
01163
01164 @endverbatim
01165   * @{
01166   */
01167 /**
01168   * @brief  Initializes the TIM PWM Time Base according to the specified
01169   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01170   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01171   *         requires a timer reset to avoid unexpected direction
01172   *         due to DIR bit readonly in center aligned mode.
01173   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
01174   * @param  htim TIM PWM handle
01175   * @retval HAL status
01176   */
01177 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01178 {
01179   /* Check the TIM handle allocation */
01180   if (htim == NULL)
01181   {
01182     return HAL_ERROR;
01183   }
01184
01185   /* Check the parameters */
01186   assert_param(IS_TIM_INSTANCE(htim->Instance));
01187   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01188   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01189   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01190
01191   if (htim->State == HAL_TIM_STATE_RESET)
01192   {
01193     /* Allocate lock resource and initialize it */
01194     htim->Lock = HAL_UNLOCKED;
01195
01196 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01197     /* Reset interrupt callbacks to legacy weak callbacks */
01198     TIM_ResetCallback(htim);
01199
01200     if (htim->PWM_MspInitCallback == NULL)
01201     {
01202       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
01203     }
01204     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01205     htim->PWM_MspInitCallback(htim);
01206 #else
01207     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01208     HAL_TIM_PWM_MspInit(htim);
01209 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01210   }
01211
01212   /* Set the TIM state */
01213   htim->State = HAL_TIM_STATE_BUSY;
01214
01215   /* Init the base time for the PWM */
01216   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01217
01218   /* Initialize the TIM state*/
01219   htim->State = HAL_TIM_STATE_READY;
01220
01221   return HAL_OK;
01222 }
01223
01224 /**
01225   * @brief  DeInitializes the TIM peripheral
01226   * @param  htim TIM PWM handle
01227   * @retval HAL status
01228   */
01229 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01230 {
01231   /* Check the parameters */
01232   assert_param(IS_TIM_INSTANCE(htim->Instance));
01233
01234   htim->State = HAL_TIM_STATE_BUSY;
01235
01236   /* Disable the TIM Peripheral Clock */
01237   __HAL_TIM_DISABLE(htim);
01238
01239 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01240   if (htim->PWM_MspDeInitCallback == NULL)
01241   {
01242     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
01243   }
01244   /* DeInit the low level hardware */
01245   htim->PWM_MspDeInitCallback(htim);
01246 #else
01247   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01248   HAL_TIM_PWM_MspDeInit(htim);
01249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01250
01251   /* Change TIM state */
01252   htim->State = HAL_TIM_STATE_RESET;
01253
01254   /* Release Lock */
01255   __HAL_UNLOCK(htim);
01256
01257   return HAL_OK;
01258 }
01259
01260 /**
01261   * @brief  Initializes the TIM PWM MSP.
01262   * @param  htim TIM PWM handle
01263   * @retval None
01264   */
01265 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01266 {
01267   /* Prevent unused argument(s) compilation warning */
01268   UNUSED(htim);
01269
01270   /* NOTE : This function should not be modified, when the callback is needed,
01271             the HAL_TIM_PWM_MspInit could be implemented in the user file
01272    */
01273 }
01274
01275 /**
01276   * @brief  DeInitializes TIM PWM MSP.
01277   * @param  htim TIM PWM handle
01278   * @retval None
01279   */
01280 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01281 {
01282   /* Prevent unused argument(s) compilation warning */
01283   UNUSED(htim);
01284
01285   /* NOTE : This function should not be modified, when the callback is needed,
01286             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01287    */
01288 }
01289
01290 /**
01291   * @brief  Starts the PWM signal generation.
01292   * @param  htim TIM handle
01293   * @param  Channel TIM Channels to be enabled
01294   *          This parameter can be one of the following values:
01295   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01296   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01297   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01298   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01299   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01300   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01301   * @retval HAL status
01302   */
01303 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01304 {
01305   uint32_t tmpsmcr;
01306
01307   /* Check the parameters */
01308   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01309
01310   /* Enable the Capture compare channel */
01311   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01312
01313   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01314   {
01315     /* Enable the main output */
01316     __HAL_TIM_MOE_ENABLE(htim);
01317   }
01318
01319   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01320   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01321   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01322   {
01323     __HAL_TIM_ENABLE(htim);
01324   }
01325
01326   /* Return function status */
01327   return HAL_OK;
01328 }
01329
01330 /**
01331   * @brief  Stops the PWM signal generation.
01332   * @param  htim TIM PWM handle
01333   * @param  Channel TIM Channels to be disabled
01334   *          This parameter can be one of the following values:
01335   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01336   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01337   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01338   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01339   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01340   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01341   * @retval HAL status
01342   */
01343 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01344 {
01345   /* Check the parameters */
01346   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01347
01348   /* Disable the Capture compare channel */
01349   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01350
01351   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01352   {
01353     /* Disable the Main Output */
01354     __HAL_TIM_MOE_DISABLE(htim);
01355   }
01356
01357   /* Disable the Peripheral */
01358   __HAL_TIM_DISABLE(htim);
01359
01360   /* Change the htim state */
01361   htim->State = HAL_TIM_STATE_READY;
01362
01363   /* Return function status */
01364   return HAL_OK;
01365 }
01366
01367 /**
01368   * @brief  Starts the PWM signal generation in interrupt mode.
01369   * @param  htim TIM PWM handle
01370   * @param  Channel TIM Channel to be enabled
01371   *          This parameter can be one of the following values:
01372   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01373   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01374   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01375   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01376   * @retval HAL status
01377   */
01378 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01379 {
01380   uint32_t tmpsmcr;
01381   /* Check the parameters */
01382   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01383
01384   switch (Channel)
01385   {
01386     case TIM_CHANNEL_1:
01387     {
01388       /* Enable the TIM Capture/Compare 1 interrupt */
01389       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01390       break;
01391     }
01392
01393     case TIM_CHANNEL_2:
01394     {
01395       /* Enable the TIM Capture/Compare 2 interrupt */
01396       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01397       break;
01398     }
01399
01400     case TIM_CHANNEL_3:
01401     {
01402       /* Enable the TIM Capture/Compare 3 interrupt */
01403       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01404       break;
01405     }
01406
01407     case TIM_CHANNEL_4:
01408     {
01409       /* Enable the TIM Capture/Compare 4 interrupt */
01410       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01411       break;
01412     }
01413
01414     default:
01415       break;
01416   }
01417
01418   /* Enable the Capture compare channel */
01419   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01420
01421   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01422   {
01423     /* Enable the main output */
01424     __HAL_TIM_MOE_ENABLE(htim);
01425   }
01426
01427   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01428   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01429   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01430   {
01431     __HAL_TIM_ENABLE(htim);
01432   }
01433
01434   /* Return function status */
01435   return HAL_OK;
01436 }
01437
01438 /**
01439   * @brief  Stops the PWM signal generation in interrupt mode.
01440   * @param  htim TIM PWM handle
01441   * @param  Channel TIM Channels to be disabled
01442   *          This parameter can be one of the following values:
01443   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01444   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01445   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01446   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01447   * @retval HAL status
01448   */
01449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01450 {
01451   /* Check the parameters */
01452   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01453
01454   switch (Channel)
01455   {
01456     case TIM_CHANNEL_1:
01457     {
01458       /* Disable the TIM Capture/Compare 1 interrupt */
01459       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01460       break;
01461     }
01462
01463     case TIM_CHANNEL_2:
01464     {
01465       /* Disable the TIM Capture/Compare 2 interrupt */
01466       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01467       break;
01468     }
01469
01470     case TIM_CHANNEL_3:
01471     {
01472       /* Disable the TIM Capture/Compare 3 interrupt */
01473       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01474       break;
01475     }
01476
01477     case TIM_CHANNEL_4:
01478     {
01479       /* Disable the TIM Capture/Compare 4 interrupt */
01480       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01481       break;
01482     }
01483
01484     default:
01485       break;
01486   }
01487
01488   /* Disable the Capture compare channel */
01489   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01490
01491   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01492   {
01493     /* Disable the Main Output */
01494     __HAL_TIM_MOE_DISABLE(htim);
01495   }
01496
01497   /* Disable the Peripheral */
01498   __HAL_TIM_DISABLE(htim);
01499
01500   /* Return function status */
01501   return HAL_OK;
01502 }
01503
01504 /**
01505   * @brief  Starts the TIM PWM signal generation in DMA mode.
01506   * @param  htim TIM PWM handle
01507   * @param  Channel TIM Channels to be enabled
01508   *          This parameter can be one of the following values:
01509   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01510   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01511   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01512   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01513   * @param  pData The source Buffer address.
01514   * @param  Length The length of data to be transferred from memory to TIM peripheral
01515   * @retval HAL status
01516   */
01517 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01518 {
01519   uint32_t tmpsmcr;
01520
01521   /* Check the parameters */
01522   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01523
01524   if (htim->State == HAL_TIM_STATE_BUSY)
01525   {
01526     return HAL_BUSY;
01527   }
01528   else if (htim->State == HAL_TIM_STATE_READY)
01529   {
01530     if ((pData == NULL) && (Length > 0U))
01531     {
01532       return HAL_ERROR;
01533     }
01534     else
01535     {
01536       htim->State = HAL_TIM_STATE_BUSY;
01537     }
01538   }
01539   else
01540   {
01541     /* nothing to do */
01542   }
01543
01544   switch (Channel)
01545   {
01546     case TIM_CHANNEL_1:
01547     {
01548       /* Set the DMA compare callbacks */
01549       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01550       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01551
01552       /* Set the DMA error callback */
01553       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01554
01555       /* Enable the DMA stream */
01556       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
01557       {
01558         return HAL_ERROR;
01559       }
01560
01561       /* Enable the TIM Capture/Compare 1 DMA request */
01562       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01563       break;
01564     }
01565
01566     case TIM_CHANNEL_2:
01567     {
01568       /* Set the DMA compare callbacks */
01569       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01570       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01571
01572       /* Set the DMA error callback */
01573       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01574
01575       /* Enable the DMA stream */
01576       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
01577       {
01578         return HAL_ERROR;
01579       }
01580       /* Enable the TIM Capture/Compare 2 DMA request */
01581       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01582       break;
01583     }
01584
01585     case TIM_CHANNEL_3:
01586     {
01587       /* Set the DMA compare callbacks */
01588       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01589       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01590
01591       /* Set the DMA error callback */
01592       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01593
01594       /* Enable the DMA stream */
01595       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01596       {
01597         return HAL_ERROR;
01598       }
01599       /* Enable the TIM Output Capture/Compare 3 request */
01600       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01601       break;
01602     }
01603
01604     case TIM_CHANNEL_4:
01605     {
01606       /* Set the DMA compare callbacks */
01607       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01608       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01609
01610       /* Set the DMA error callback */
01611       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01612
01613       /* Enable the DMA stream */
01614       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
01615       {
01616         return HAL_ERROR;
01617       }
01618       /* Enable the TIM Capture/Compare 4 DMA request */
01619       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01620       break;
01621     }
01622
01623     default:
01624       break;
01625   }
01626
01627   /* Enable the Capture compare channel */
01628   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01629
01630   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01631   {
01632     /* Enable the main output */
01633     __HAL_TIM_MOE_ENABLE(htim);
01634   }
01635
01636   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01637   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01638   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01639   {
01640     __HAL_TIM_ENABLE(htim);
01641   }
01642
01643   /* Return function status */
01644   return HAL_OK;
01645 }
01646
01647 /**
01648   * @brief  Stops the TIM PWM signal generation in DMA mode.
01649   * @param  htim TIM PWM handle
01650   * @param  Channel TIM Channels to be disabled
01651   *          This parameter can be one of the following values:
01652   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01653   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01654   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01655   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01656   * @retval HAL status
01657   */
01658 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01659 {
01660   /* Check the parameters */
01661   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01662
01663   switch (Channel)
01664   {
01665     case TIM_CHANNEL_1:
01666     {
01667       /* Disable the TIM Capture/Compare 1 DMA request */
01668       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01669       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01670       break;
01671     }
01672
01673     case TIM_CHANNEL_2:
01674     {
01675       /* Disable the TIM Capture/Compare 2 DMA request */
01676       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01677       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01678       break;
01679     }
01680
01681     case TIM_CHANNEL_3:
01682     {
01683       /* Disable the TIM Capture/Compare 3 DMA request */
01684       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01685       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01686       break;
01687     }
01688
01689     case TIM_CHANNEL_4:
01690     {
01691       /* Disable the TIM Capture/Compare 4 interrupt */
01692       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01693       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01694       break;
01695     }
01696
01697     default:
01698       break;
01699   }
01700
01701   /* Disable the Capture compare channel */
01702   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01703
01704   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01705   {
01706     /* Disable the Main Output */
01707     __HAL_TIM_MOE_DISABLE(htim);
01708   }
01709
01710   /* Disable the Peripheral */
01711   __HAL_TIM_DISABLE(htim);
01712
01713   /* Change the htim state */
01714   htim->State = HAL_TIM_STATE_READY;
01715
01716   /* Return function status */
01717   return HAL_OK;
01718 }
01719
01720 /**
01721   * @}
01722   */
01723
01724 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
01725   *  @brief    TIM Input Capture functions
01726   *
01727 @verbatim
01728   ==============================================================================
01729               ##### TIM Input Capture functions #####
01730   ==============================================================================
01731  [..]
01732    This section provides functions allowing to:
01733    (+) Initialize and configure the TIM Input Capture.
01734    (+) De-initialize the TIM Input Capture.
01735    (+) Start the TIM Input Capture.
01736    (+) Stop the TIM Input Capture.
01737    (+) Start the TIM Input Capture and enable interrupt.
01738    (+) Stop the TIM Input Capture and disable interrupt.
01739    (+) Start the TIM Input Capture and enable DMA transfer.
01740    (+) Stop the TIM Input Capture and disable DMA transfer.
01741
01742 @endverbatim
01743   * @{
01744   */
01745 /**
01746   * @brief  Initializes the TIM Input Capture Time base according to the specified
01747   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01748   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01749   *         requires a timer reset to avoid unexpected direction
01750   *         due to DIR bit readonly in center aligned mode.
01751   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
01752   * @param  htim TIM Input Capture handle
01753   * @retval HAL status
01754   */
01755 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01756 {
01757   /* Check the TIM handle allocation */
01758   if (htim == NULL)
01759   {
01760     return HAL_ERROR;
01761   }
01762
01763   /* Check the parameters */
01764   assert_param(IS_TIM_INSTANCE(htim->Instance));
01765   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01766   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01767   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01768
01769   if (htim->State == HAL_TIM_STATE_RESET)
01770   {
01771     /* Allocate lock resource and initialize it */
01772     htim->Lock = HAL_UNLOCKED;
01773
01774 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01775     /* Reset interrupt callbacks to legacy weak callbacks */
01776     TIM_ResetCallback(htim);
01777
01778     if (htim->IC_MspInitCallback == NULL)
01779     {
01780       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
01781     }
01782     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01783     htim->IC_MspInitCallback(htim);
01784 #else
01785     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01786     HAL_TIM_IC_MspInit(htim);
01787 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01788   }
01789
01790   /* Set the TIM state */
01791   htim->State = HAL_TIM_STATE_BUSY;
01792
01793   /* Init the base time for the input capture */
01794   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01795
01796   /* Initialize the TIM state*/
01797   htim->State = HAL_TIM_STATE_READY;
01798
01799   return HAL_OK;
01800 }
01801
01802 /**
01803   * @brief  DeInitializes the TIM peripheral
01804   * @param  htim TIM Input Capture handle
01805   * @retval HAL status
01806   */
01807 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01808 {
01809   /* Check the parameters */
01810   assert_param(IS_TIM_INSTANCE(htim->Instance));
01811
01812   htim->State = HAL_TIM_STATE_BUSY;
01813
01814   /* Disable the TIM Peripheral Clock */
01815   __HAL_TIM_DISABLE(htim);
01816
01817 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01818   if (htim->IC_MspDeInitCallback == NULL)
01819   {
01820     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
01821   }
01822   /* DeInit the low level hardware */
01823   htim->IC_MspDeInitCallback(htim);
01824 #else
01825   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01826   HAL_TIM_IC_MspDeInit(htim);
01827 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01828
01829   /* Change TIM state */
01830   htim->State = HAL_TIM_STATE_RESET;
01831
01832   /* Release Lock */
01833   __HAL_UNLOCK(htim);
01834
01835   return HAL_OK;
01836 }
01837
01838 /**
01839   * @brief  Initializes the TIM Input Capture MSP.
01840   * @param  htim TIM Input Capture handle
01841   * @retval None
01842   */
01843 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01844 {
01845   /* Prevent unused argument(s) compilation warning */
01846   UNUSED(htim);
01847
01848   /* NOTE : This function should not be modified, when the callback is needed,
01849             the HAL_TIM_IC_MspInit could be implemented in the user file
01850    */
01851 }
01852
01853 /**
01854   * @brief  DeInitializes TIM Input Capture MSP.
01855   * @param  htim TIM handle
01856   * @retval None
01857   */
01858 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01859 {
01860   /* Prevent unused argument(s) compilation warning */
01861   UNUSED(htim);
01862
01863   /* NOTE : This function should not be modified, when the callback is needed,
01864             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01865    */
01866 }
01867
01868 /**
01869   * @brief  Starts the TIM Input Capture measurement.
01870   * @param  htim TIM Input Capture handle
01871   * @param  Channel TIM Channels to be enabled
01872   *          This parameter can be one of the following values:
01873   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01874   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01875   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01876   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01877   * @retval HAL status
01878   */
01879 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01880 {
01881   uint32_t tmpsmcr;
01882
01883   /* Check the parameters */
01884   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01885
01886   /* Enable the Input Capture channel */
01887   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01888
01889   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01890   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01891   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01892   {
01893     __HAL_TIM_ENABLE(htim);
01894   }
01895
01896   /* Return function status */
01897   return HAL_OK;
01898 }
01899
01900 /**
01901   * @brief  Stops the TIM Input Capture measurement.
01902   * @param  htim TIM Input Capture handle
01903   * @param  Channel TIM Channels to be disabled
01904   *          This parameter can be one of the following values:
01905   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01906   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01907   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01908   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01909   * @retval HAL status
01910   */
01911 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01912 {
01913   /* Check the parameters */
01914   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01915
01916   /* Disable the Input Capture channel */
01917   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01918
01919   /* Disable the Peripheral */
01920   __HAL_TIM_DISABLE(htim);
01921
01922   /* Return function status */
01923   return HAL_OK;
01924 }
01925
01926 /**
01927   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01928   * @param  htim TIM Input Capture handle
01929   * @param  Channel TIM Channels to be enabled
01930   *          This parameter can be one of the following values:
01931   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01932   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01933   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01934   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01935   * @retval HAL status
01936   */
01937 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01938 {
01939   uint32_t tmpsmcr;
01940
01941   /* Check the parameters */
01942   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01943
01944   switch (Channel)
01945   {
01946     case TIM_CHANNEL_1:
01947     {
01948       /* Enable the TIM Capture/Compare 1 interrupt */
01949       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01950       break;
01951     }
01952
01953     case TIM_CHANNEL_2:
01954     {
01955       /* Enable the TIM Capture/Compare 2 interrupt */
01956       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01957       break;
01958     }
01959
01960     case TIM_CHANNEL_3:
01961     {
01962       /* Enable the TIM Capture/Compare 3 interrupt */
01963       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01964       break;
01965     }
01966
01967     case TIM_CHANNEL_4:
01968     {
01969       /* Enable the TIM Capture/Compare 4 interrupt */
01970       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01971       break;
01972     }
01973
01974     default:
01975       break;
01976   }
01977   /* Enable the Input Capture channel */
01978   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01979
01980   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01981   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01982   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01983   {
01984     __HAL_TIM_ENABLE(htim);
01985   }
01986
01987   /* Return function status */
01988   return HAL_OK;
01989 }
01990
01991 /**
01992   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01993   * @param  htim TIM Input Capture handle
01994   * @param  Channel TIM Channels to be disabled
01995   *          This parameter can be one of the following values:
01996   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01997   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01998   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01999   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02000   * @retval HAL status
02001   */
02002 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02003 {
02004   /* Check the parameters */
02005   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02006
02007   switch (Channel)
02008   {
02009     case TIM_CHANNEL_1:
02010     {
02011       /* Disable the TIM Capture/Compare 1 interrupt */
02012       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02013       break;
02014     }
02015
02016     case TIM_CHANNEL_2:
02017     {
02018       /* Disable the TIM Capture/Compare 2 interrupt */
02019       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02020       break;
02021     }
02022
02023     case TIM_CHANNEL_3:
02024     {
02025       /* Disable the TIM Capture/Compare 3 interrupt */
02026       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
02027       break;
02028     }
02029
02030     case TIM_CHANNEL_4:
02031     {
02032       /* Disable the TIM Capture/Compare 4 interrupt */
02033       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
02034       break;
02035     }
02036
02037     default:
02038       break;
02039   }
02040
02041   /* Disable the Input Capture channel */
02042   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02043
02044   /* Disable the Peripheral */
02045   __HAL_TIM_DISABLE(htim);
02046
02047   /* Return function status */
02048   return HAL_OK;
02049 }
02050
02051 /**
02052   * @brief  Starts the TIM Input Capture measurement in DMA mode.
02053   * @param  htim TIM Input Capture handle
02054   * @param  Channel TIM Channels to be enabled
02055   *          This parameter can be one of the following values:
02056   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02057   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02058   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02059   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02060   * @param  pData The destination Buffer address.
02061   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02062   * @retval HAL status
02063   */
02064 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
02065 {
02066   uint32_t tmpsmcr;
02067
02068   /* Check the parameters */
02069   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02070   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02071
02072   if (htim->State == HAL_TIM_STATE_BUSY)
02073   {
02074     return HAL_BUSY;
02075   }
02076   else if (htim->State == HAL_TIM_STATE_READY)
02077   {
02078     if ((pData == NULL) && (Length > 0U))
02079     {
02080       return HAL_ERROR;
02081     }
02082     else
02083     {
02084       htim->State = HAL_TIM_STATE_BUSY;
02085     }
02086   }
02087   else
02088   {
02089     /* nothing to do */
02090   }
02091
02092   switch (Channel)
02093   {
02094     case TIM_CHANNEL_1:
02095     {
02096       /* Set the DMA capture callbacks */
02097       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02098       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02099
02100       /* Set the DMA error callback */
02101       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02102
02103       /* Enable the DMA stream */
02104       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
02105       {
02106         return HAL_ERROR;
02107       }
02108       /* Enable the TIM Capture/Compare 1 DMA request */
02109       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02110       break;
02111     }
02112
02113     case TIM_CHANNEL_2:
02114     {
02115       /* Set the DMA capture callbacks */
02116       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02117       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02118
02119       /* Set the DMA error callback */
02120       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02121
02122       /* Enable the DMA stream */
02123       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
02124       {
02125         return HAL_ERROR;
02126       }
02127       /* Enable the TIM Capture/Compare 2  DMA request */
02128       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02129       break;
02130     }
02131
02132     case TIM_CHANNEL_3:
02133     {
02134       /* Set the DMA capture callbacks */
02135       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
02136       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02137
02138       /* Set the DMA error callback */
02139       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
02140
02141       /* Enable the DMA stream */
02142       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
02143       {
02144         return HAL_ERROR;
02145       }
02146       /* Enable the TIM Capture/Compare 3  DMA request */
02147       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
02148       break;
02149     }
02150
02151     case TIM_CHANNEL_4:
02152     {
02153       /* Set the DMA capture callbacks */
02154       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
02155       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02156
02157       /* Set the DMA error callback */
02158       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
02159
02160       /* Enable the DMA stream */
02161       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
02162       {
02163         return HAL_ERROR;
02164       }
02165       /* Enable the TIM Capture/Compare 4  DMA request */
02166       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
02167       break;
02168     }
02169
02170     default:
02171       break;
02172   }
02173
02174   /* Enable the Input Capture channel */
02175   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02176
02177   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02178   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02179   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02180   {
02181     __HAL_TIM_ENABLE(htim);
02182   }
02183
02184   /* Return function status */
02185   return HAL_OK;
02186 }
02187
02188 /**
02189   * @brief  Stops the TIM Input Capture measurement in DMA mode.
02190   * @param  htim TIM Input Capture handle
02191   * @param  Channel TIM Channels to be disabled
02192   *          This parameter can be one of the following values:
02193   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02194   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02195   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02196   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02197   * @retval HAL status
02198   */
02199 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02200 {
02201   /* Check the parameters */
02202   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02203   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02204
02205   switch (Channel)
02206   {
02207     case TIM_CHANNEL_1:
02208     {
02209       /* Disable the TIM Capture/Compare 1 DMA request */
02210       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02211       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
02212       break;
02213     }
02214
02215     case TIM_CHANNEL_2:
02216     {
02217       /* Disable the TIM Capture/Compare 2 DMA request */
02218       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02219       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
02220       break;
02221     }
02222
02223     case TIM_CHANNEL_3:
02224     {
02225       /* Disable the TIM Capture/Compare 3  DMA request */
02226       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
02227       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
02228       break;
02229     }
02230
02231     case TIM_CHANNEL_4:
02232     {
02233       /* Disable the TIM Capture/Compare 4  DMA request */
02234       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
02235       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
02236       break;
02237     }
02238
02239     default:
02240       break;
02241   }
02242
02243   /* Disable the Input Capture channel */
02244   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02245
02246   /* Disable the Peripheral */
02247   __HAL_TIM_DISABLE(htim);
02248
02249   /* Change the htim state */
02250   htim->State = HAL_TIM_STATE_READY;
02251
02252   /* Return function status */
02253   return HAL_OK;
02254 }
02255 /**
02256   * @}
02257   */
02258
02259 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02260   *  @brief    TIM One Pulse functions
02261   *
02262 @verbatim
02263   ==============================================================================
02264                         ##### TIM One Pulse functions #####
02265   ==============================================================================
02266   [..]
02267     This section provides functions allowing to:
02268     (+) Initialize and configure the TIM One Pulse.
02269     (+) De-initialize the TIM One Pulse.
02270     (+) Start the TIM One Pulse.
02271     (+) Stop the TIM One Pulse.
02272     (+) Start the TIM One Pulse and enable interrupt.
02273     (+) Stop the TIM One Pulse and disable interrupt.
02274     (+) Start the TIM One Pulse and enable DMA transfer.
02275     (+) Stop the TIM One Pulse and disable DMA transfer.
02276
02277 @endverbatim
02278   * @{
02279   */
02280 /**
02281   * @brief  Initializes the TIM One Pulse Time Base according to the specified
02282   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
02283   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02284   *         requires a timer reset to avoid unexpected direction
02285   *         due to DIR bit readonly in center aligned mode.
02286   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
02287   * @param  htim TIM One Pulse handle
02288   * @param  OnePulseMode Select the One pulse mode.
02289   *         This parameter can be one of the following values:
02290   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
02291   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
02292   * @retval HAL status
02293   */
02294 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02295 {
02296   /* Check the TIM handle allocation */
02297   if (htim == NULL)
02298   {
02299     return HAL_ERROR;
02300   }
02301
02302   /* Check the parameters */
02303   assert_param(IS_TIM_INSTANCE(htim->Instance));
02304   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02305   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02306   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02307   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02308
02309   if (htim->State == HAL_TIM_STATE_RESET)
02310   {
02311     /* Allocate lock resource and initialize it */
02312     htim->Lock = HAL_UNLOCKED;
02313
02314 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02315     /* Reset interrupt callbacks to legacy weak callbacks */
02316     TIM_ResetCallback(htim);
02317
02318     if (htim->OnePulse_MspInitCallback == NULL)
02319     {
02320       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
02321     }
02322     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02323     htim->OnePulse_MspInitCallback(htim);
02324 #else
02325     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02326     HAL_TIM_OnePulse_MspInit(htim);
02327 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02328   }
02329
02330   /* Set the TIM state */
02331   htim->State = HAL_TIM_STATE_BUSY;
02332
02333   /* Configure the Time base in the One Pulse Mode */
02334   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02335
02336   /* Reset the OPM Bit */
02337   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02338
02339   /* Configure the OPM Mode */
02340   htim->Instance->CR1 |= OnePulseMode;
02341
02342   /* Initialize the TIM state*/
02343   htim->State = HAL_TIM_STATE_READY;
02344
02345   return HAL_OK;
02346 }
02347
02348 /**
02349   * @brief  DeInitializes the TIM One Pulse
02350   * @param  htim TIM One Pulse handle
02351   * @retval HAL status
02352   */
02353 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02354 {
02355   /* Check the parameters */
02356   assert_param(IS_TIM_INSTANCE(htim->Instance));
02357
02358   htim->State = HAL_TIM_STATE_BUSY;
02359
02360   /* Disable the TIM Peripheral Clock */
02361   __HAL_TIM_DISABLE(htim);
02362
02363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02364   if (htim->OnePulse_MspDeInitCallback == NULL)
02365   {
02366     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
02367   }
02368   /* DeInit the low level hardware */
02369   htim->OnePulse_MspDeInitCallback(htim);
02370 #else
02371   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02372   HAL_TIM_OnePulse_MspDeInit(htim);
02373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02374
02375   /* Change TIM state */
02376   htim->State = HAL_TIM_STATE_RESET;
02377
02378   /* Release Lock */
02379   __HAL_UNLOCK(htim);
02380
02381   return HAL_OK;
02382 }
02383
02384 /**
02385   * @brief  Initializes the TIM One Pulse MSP.
02386   * @param  htim TIM One Pulse handle
02387   * @retval None
02388   */
02389 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02390 {
02391   /* Prevent unused argument(s) compilation warning */
02392   UNUSED(htim);
02393
02394   /* NOTE : This function should not be modified, when the callback is needed,
02395             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02396    */
02397 }
02398
02399 /**
02400   * @brief  DeInitializes TIM One Pulse MSP.
02401   * @param  htim TIM One Pulse handle
02402   * @retval None
02403   */
02404 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02405 {
02406   /* Prevent unused argument(s) compilation warning */
02407   UNUSED(htim);
02408
02409   /* NOTE : This function should not be modified, when the callback is needed,
02410             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02411    */
02412 }
02413
02414 /**
02415   * @brief  Starts the TIM One Pulse signal generation.
02416   * @param  htim TIM One Pulse handle
02417   * @param  OutputChannel TIM Channels to be enabled
02418   *          This parameter can be one of the following values:
02419   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02420   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02421   * @retval HAL status
02422   */
02423 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02424 {
02425   /* Prevent unused argument(s) compilation warning */
02426   UNUSED(OutputChannel);
02427
02428   /* Enable the Capture compare and the Input Capture channels
02429     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02430     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02431     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02432     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02433
02434     No need to enable the counter, it's enabled automatically by hardware
02435     (the counter starts in response to a stimulus and generate a pulse */
02436
02437   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02438   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02439
02440   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02441   {
02442     /* Enable the main output */
02443     __HAL_TIM_MOE_ENABLE(htim);
02444   }
02445
02446   /* Return function status */
02447   return HAL_OK;
02448 }
02449
02450 /**
02451   * @brief  Stops the TIM One Pulse signal generation.
02452   * @param  htim TIM One Pulse handle
02453   * @param  OutputChannel TIM Channels to be disable
02454   *          This parameter can be one of the following values:
02455   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02456   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02457   * @retval HAL status
02458   */
02459 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02460 {
02461   /* Prevent unused argument(s) compilation warning */
02462   UNUSED(OutputChannel);
02463
02464   /* Disable the Capture compare and the Input Capture channels
02465   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02466   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02467   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02468   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02469
02470   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02471   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02472
02473   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02474   {
02475     /* Disable the Main Output */
02476     __HAL_TIM_MOE_DISABLE(htim);
02477   }
02478
02479   /* Disable the Peripheral */
02480   __HAL_TIM_DISABLE(htim);
02481
02482   /* Return function status */
02483   return HAL_OK;
02484 }
02485
02486 /**
02487   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02488   * @param  htim TIM One Pulse handle
02489   * @param  OutputChannel TIM Channels to be enabled
02490   *          This parameter can be one of the following values:
02491   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02492   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02493   * @retval HAL status
02494   */
02495 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02496 {
02497   /* Prevent unused argument(s) compilation warning */
02498   UNUSED(OutputChannel);
02499
02500   /* Enable the Capture compare and the Input Capture channels
02501     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02502     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02503     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02504     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02505
02506     No need to enable the counter, it's enabled automatically by hardware
02507     (the counter starts in response to a stimulus and generate a pulse */
02508
02509   /* Enable the TIM Capture/Compare 1 interrupt */
02510   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02511
02512   /* Enable the TIM Capture/Compare 2 interrupt */
02513   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02514
02515   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02516   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02517
02518   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02519   {
02520     /* Enable the main output */
02521     __HAL_TIM_MOE_ENABLE(htim);
02522   }
02523
02524   /* Return function status */
02525   return HAL_OK;
02526 }
02527
02528 /**
02529   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02530   * @param  htim TIM One Pulse handle
02531   * @param  OutputChannel TIM Channels to be enabled
02532   *          This parameter can be one of the following values:
02533   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02534   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02535   * @retval HAL status
02536   */
02537 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02538 {
02539   /* Prevent unused argument(s) compilation warning */
02540   UNUSED(OutputChannel);
02541
02542   /* Disable the TIM Capture/Compare 1 interrupt */
02543   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02544
02545   /* Disable the TIM Capture/Compare 2 interrupt */
02546   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02547
02548   /* Disable the Capture compare and the Input Capture channels
02549   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02550   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02551   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02552   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02553   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02554   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02555
02556   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02557   {
02558     /* Disable the Main Output */
02559     __HAL_TIM_MOE_DISABLE(htim);
02560   }
02561
02562   /* Disable the Peripheral */
02563   __HAL_TIM_DISABLE(htim);
02564
02565   /* Return function status */
02566   return HAL_OK;
02567 }
02568
02569 /**
02570   * @}
02571   */
02572
02573 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
02574   *  @brief    TIM Encoder functions
02575   *
02576 @verbatim
02577   ==============================================================================
02578                           ##### TIM Encoder functions #####
02579   ==============================================================================
02580   [..]
02581     This section provides functions allowing to:
02582     (+) Initialize and configure the TIM Encoder.
02583     (+) De-initialize the TIM Encoder.
02584     (+) Start the TIM Encoder.
02585     (+) Stop the TIM Encoder.
02586     (+) Start the TIM Encoder and enable interrupt.
02587     (+) Stop the TIM Encoder and disable interrupt.
02588     (+) Start the TIM Encoder and enable DMA transfer.
02589     (+) Stop the TIM Encoder and disable DMA transfer.
02590
02591 @endverbatim
02592   * @{
02593   */
02594 /**
02595   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
02596   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02597   *         requires a timer reset to avoid unexpected direction
02598   *         due to DIR bit readonly in center aligned mode.
02599   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
02600   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
02601   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
02602   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
02603   * @param  htim TIM Encoder Interface handle
02604   * @param  sConfig TIM Encoder Interface configuration structure
02605   * @retval HAL status
02606   */
02607 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
02608 {
02609   uint32_t tmpsmcr;
02610   uint32_t tmpccmr1;
02611   uint32_t tmpccer;
02612
02613   /* Check the TIM handle allocation */
02614   if (htim == NULL)
02615   {
02616     return HAL_ERROR;
02617   }
02618
02619   /* Check the parameters */
02620   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02621   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02622   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02623   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02624   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02625   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02626   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02627   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
02628   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
02629   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02630   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02631   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02632   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02633
02634   if (htim->State == HAL_TIM_STATE_RESET)
02635   {
02636     /* Allocate lock resource and initialize it */
02637     htim->Lock = HAL_UNLOCKED;
02638
02639 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02640     /* Reset interrupt callbacks to legacy weak callbacks */
02641     TIM_ResetCallback(htim);
02642
02643     if (htim->Encoder_MspInitCallback == NULL)
02644     {
02645       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
02646     }
02647     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02648     htim->Encoder_MspInitCallback(htim);
02649 #else
02650     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02651     HAL_TIM_Encoder_MspInit(htim);
02652 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02653   }
02654
02655   /* Set the TIM state */
02656   htim->State = HAL_TIM_STATE_BUSY;
02657
02658   /* Reset the SMS and ECE bits */
02659   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
02660
02661   /* Configure the Time base in the Encoder Mode */
02662   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02663
02664   /* Get the TIMx SMCR register value */
02665   tmpsmcr = htim->Instance->SMCR;
02666
02667   /* Get the TIMx CCMR1 register value */
02668   tmpccmr1 = htim->Instance->CCMR1;
02669
02670   /* Get the TIMx CCER register value */
02671   tmpccer = htim->Instance->CCER;
02672
02673   /* Set the encoder Mode */
02674   tmpsmcr |= sConfig->EncoderMode;
02675
02676   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02677   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02678   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
02679
02680   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02681   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02682   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02683   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
02684   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
02685
02686   /* Set the TI1 and the TI2 Polarities */
02687   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02688   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02689   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
02690
02691   /* Write to TIMx SMCR */
02692   htim->Instance->SMCR = tmpsmcr;
02693
02694   /* Write to TIMx CCMR1 */
02695   htim->Instance->CCMR1 = tmpccmr1;
02696
02697   /* Write to TIMx CCER */
02698   htim->Instance->CCER = tmpccer;
02699
02700   /* Initialize the TIM state*/
02701   htim->State = HAL_TIM_STATE_READY;
02702
02703   return HAL_OK;
02704 }
02705
02706
02707 /**
02708   * @brief  DeInitializes the TIM Encoder interface
02709   * @param  htim TIM Encoder Interface handle
02710   * @retval HAL status
02711   */
02712 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02713 {
02714   /* Check the parameters */
02715   assert_param(IS_TIM_INSTANCE(htim->Instance));
02716
02717   htim->State = HAL_TIM_STATE_BUSY;
02718
02719   /* Disable the TIM Peripheral Clock */
02720   __HAL_TIM_DISABLE(htim);
02721
02722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02723   if (htim->Encoder_MspDeInitCallback == NULL)
02724   {
02725     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
02726   }
02727   /* DeInit the low level hardware */
02728   htim->Encoder_MspDeInitCallback(htim);
02729 #else
02730   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02731   HAL_TIM_Encoder_MspDeInit(htim);
02732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02733
02734   /* Change TIM state */
02735   htim->State = HAL_TIM_STATE_RESET;
02736
02737   /* Release Lock */
02738   __HAL_UNLOCK(htim);
02739
02740   return HAL_OK;
02741 }
02742
02743 /**
02744   * @brief  Initializes the TIM Encoder Interface MSP.
02745   * @param  htim TIM Encoder Interface handle
02746   * @retval None
02747   */
02748 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02749 {
02750   /* Prevent unused argument(s) compilation warning */
02751   UNUSED(htim);
02752
02753   /* NOTE : This function should not be modified, when the callback is needed,
02754             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02755    */
02756 }
02757
02758 /**
02759   * @brief  DeInitializes TIM Encoder Interface MSP.
02760   * @param  htim TIM Encoder Interface handle
02761   * @retval None
02762   */
02763 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02764 {
02765   /* Prevent unused argument(s) compilation warning */
02766   UNUSED(htim);
02767
02768   /* NOTE : This function should not be modified, when the callback is needed,
02769             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02770    */
02771 }
02772
02773 /**
02774   * @brief  Starts the TIM Encoder Interface.
02775   * @param  htim TIM Encoder Interface handle
02776   * @param  Channel TIM Channels to be enabled
02777   *          This parameter can be one of the following values:
02778   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02779   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02780   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02781   * @retval HAL status
02782   */
02783 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02784 {
02785   /* Check the parameters */
02786   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02787
02788   /* Enable the encoder interface channels */
02789   switch (Channel)
02790   {
02791     case TIM_CHANNEL_1:
02792     {
02793       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02794       break;
02795     }
02796
02797     case TIM_CHANNEL_2:
02798     {
02799       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02800       break;
02801     }
02802
02803     default :
02804     {
02805       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02806       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02807       break;
02808     }
02809   }
02810   /* Enable the Peripheral */
02811   __HAL_TIM_ENABLE(htim);
02812
02813   /* Return function status */
02814   return HAL_OK;
02815 }
02816
02817 /**
02818   * @brief  Stops the TIM Encoder Interface.
02819   * @param  htim TIM Encoder Interface handle
02820   * @param  Channel TIM Channels to be disabled
02821   *          This parameter can be one of the following values:
02822   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02823   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02824   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02825   * @retval HAL status
02826   */
02827 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02828 {
02829   /* Check the parameters */
02830   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02831
02832   /* Disable the Input Capture channels 1 and 2
02833     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02834   switch (Channel)
02835   {
02836     case TIM_CHANNEL_1:
02837     {
02838       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02839       break;
02840     }
02841
02842     case TIM_CHANNEL_2:
02843     {
02844       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02845       break;
02846     }
02847
02848     default :
02849     {
02850       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02851       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02852       break;
02853     }
02854   }
02855
02856   /* Disable the Peripheral */
02857   __HAL_TIM_DISABLE(htim);
02858
02859   /* Return function status */
02860   return HAL_OK;
02861 }
02862
02863 /**
02864   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02865   * @param  htim TIM Encoder Interface handle
02866   * @param  Channel TIM Channels to be enabled
02867   *          This parameter can be one of the following values:
02868   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02869   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02870   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02871   * @retval HAL status
02872   */
02873 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02874 {
02875   /* Check the parameters */
02876   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02877
02878   /* Enable the encoder interface channels */
02879   /* Enable the capture compare Interrupts 1 and/or 2 */
02880   switch (Channel)
02881   {
02882     case TIM_CHANNEL_1:
02883     {
02884       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02885       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02886       break;
02887     }
02888
02889     case TIM_CHANNEL_2:
02890     {
02891       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02892       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02893       break;
02894     }
02895
02896     default :
02897     {
02898       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02899       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02900       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02901       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02902       break;
02903     }
02904   }
02905
02906   /* Enable the Peripheral */
02907   __HAL_TIM_ENABLE(htim);
02908
02909   /* Return function status */
02910   return HAL_OK;
02911 }
02912
02913 /**
02914   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02915   * @param  htim TIM Encoder Interface handle
02916   * @param  Channel TIM Channels to be disabled
02917   *          This parameter can be one of the following values:
02918   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02919   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02920   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02921   * @retval HAL status
02922   */
02923 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02924 {
02925   /* Check the parameters */
02926   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02927
02928   /* Disable the Input Capture channels 1 and 2
02929     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02930   if (Channel == TIM_CHANNEL_1)
02931   {
02932     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02933
02934     /* Disable the capture compare Interrupts 1 */
02935     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02936   }
02937   else if (Channel == TIM_CHANNEL_2)
02938   {
02939     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02940
02941     /* Disable the capture compare Interrupts 2 */
02942     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02943   }
02944   else
02945   {
02946     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02947     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02948
02949     /* Disable the capture compare Interrupts 1 and 2 */
02950     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02951     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02952   }
02953
02954   /* Disable the Peripheral */
02955   __HAL_TIM_DISABLE(htim);
02956
02957   /* Change the htim state */
02958   htim->State = HAL_TIM_STATE_READY;
02959
02960   /* Return function status */
02961   return HAL_OK;
02962 }
02963
02964 /**
02965   * @brief  Starts the TIM Encoder Interface in DMA mode.
02966   * @param  htim TIM Encoder Interface handle
02967   * @param  Channel TIM Channels to be enabled
02968   *          This parameter can be one of the following values:
02969   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02970   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02971   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02972   * @param  pData1 The destination Buffer address for IC1.
02973   * @param  pData2 The destination Buffer address for IC2.
02974   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02975   * @retval HAL status
02976   */
02977 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02978                                             uint32_t *pData2, uint16_t Length)
02979 {
02980   /* Check the parameters */
02981   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02982
02983   if (htim->State == HAL_TIM_STATE_BUSY)
02984   {
02985     return HAL_BUSY;
02986   }
02987   else if (htim->State == HAL_TIM_STATE_READY)
02988   {
02989     if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
02990     {
02991       return HAL_ERROR;
02992     }
02993     else
02994     {
02995       htim->State = HAL_TIM_STATE_BUSY;
02996     }
02997   }
02998   else
02999   {
03000     /* nothing to do */
03001   }
03002
03003   switch (Channel)
03004   {
03005     case TIM_CHANNEL_1:
03006     {
03007       /* Set the DMA capture callbacks */
03008       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03009       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03010
03011       /* Set the DMA error callback */
03012       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03013
03014       /* Enable the DMA stream */
03015       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
03016       {
03017         return HAL_ERROR;
03018       }
03019       /* Enable the TIM Input Capture DMA request */
03020       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03021
03022       /* Enable the Peripheral */
03023       __HAL_TIM_ENABLE(htim);
03024
03025       /* Enable the Capture compare channel */
03026       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03027       break;
03028     }
03029
03030     case TIM_CHANNEL_2:
03031     {
03032       /* Set the DMA capture callbacks */
03033       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03034       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03035
03036       /* Set the DMA error callback */
03037       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
03038       /* Enable the DMA stream */
03039       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
03040       {
03041         return HAL_ERROR;
03042       }
03043       /* Enable the TIM Input Capture  DMA request */
03044       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03045
03046       /* Enable the Peripheral */
03047       __HAL_TIM_ENABLE(htim);
03048
03049       /* Enable the Capture compare channel */
03050       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03051       break;
03052     }
03053
03054     case TIM_CHANNEL_ALL:
03055     {
03056       /* Set the DMA capture callbacks */
03057       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03058       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03059
03060       /* Set the DMA error callback */
03061       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03062
03063       /* Enable the DMA stream */
03064       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
03065       {
03066         return HAL_ERROR;
03067       }
03068
03069       /* Set the DMA capture callbacks */
03070       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03071       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03072
03073       /* Set the DMA error callback */
03074       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03075
03076       /* Enable the DMA stream */
03077       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
03078       {
03079         return HAL_ERROR;
03080       }
03081       /* Enable the Peripheral */
03082       __HAL_TIM_ENABLE(htim);
03083
03084       /* Enable the Capture compare channel */
03085       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03086       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03087
03088       /* Enable the TIM Input Capture  DMA request */
03089       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03090       /* Enable the TIM Input Capture  DMA request */
03091       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03092       break;
03093     }
03094
03095     default:
03096       break;
03097   }
03098   /* Return function status */
03099   return HAL_OK;
03100 }
03101
03102 /**
03103   * @brief  Stops the TIM Encoder Interface in DMA mode.
03104   * @param  htim TIM Encoder Interface handle
03105   * @param  Channel TIM Channels to be enabled
03106   *          This parameter can be one of the following values:
03107   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03108   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03109   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03110   * @retval HAL status
03111   */
03112 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
03113 {
03114   /* Check the parameters */
03115   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
03116
03117   /* Disable the Input Capture channels 1 and 2
03118     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03119   if (Channel == TIM_CHANNEL_1)
03120   {
03121     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03122
03123     /* Disable the capture compare DMA Request 1 */
03124     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03125     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03126   }
03127   else if (Channel == TIM_CHANNEL_2)
03128   {
03129     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03130
03131     /* Disable the capture compare DMA Request 2 */
03132     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03133     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03134   }
03135   else
03136   {
03137     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03138     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03139
03140     /* Disable the capture compare DMA Request 1 and 2 */
03141     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03142     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03143     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03144     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03145   }
03146
03147   /* Disable the Peripheral */
03148   __HAL_TIM_DISABLE(htim);
03149
03150   /* Change the htim state */
03151   htim->State = HAL_TIM_STATE_READY;
03152
03153   /* Return function status */
03154   return HAL_OK;
03155 }
03156
03157 /**
03158   * @}
03159   */
03160 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
03161   *  @brief    TIM IRQ handler management
03162   *
03163 @verbatim
03164   ==============================================================================
03165                         ##### IRQ handler management #####
03166   ==============================================================================
03167   [..]
03168     This section provides Timer IRQ handler function.
03169
03170 @endverbatim
03171   * @{
03172   */
03173 /**
03174   * @brief  This function handles TIM interrupts requests.
03175   * @param  htim TIM  handle
03176   * @retval None
03177   */
03178 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
03179 {
03180   /* Capture compare 1 event */
03181   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
03182   {
03183     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
03184     {
03185       {
03186         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
03187         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03188
03189         /* Input capture event */
03190         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
03191         {
03192 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03193           htim->IC_CaptureCallback(htim);
03194 #else
03195           HAL_TIM_IC_CaptureCallback(htim);
03196 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03197         }
03198         /* Output compare event */
03199         else
03200         {
03201 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03202           htim->OC_DelayElapsedCallback(htim);
03203           htim->PWM_PulseFinishedCallback(htim);
03204 #else
03205           HAL_TIM_OC_DelayElapsedCallback(htim);
03206           HAL_TIM_PWM_PulseFinishedCallback(htim);
03207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03208         }
03209         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03210       }
03211     }
03212   }
03213   /* Capture compare 2 event */
03214   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
03215   {
03216     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
03217     {
03218       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
03219       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03220       /* Input capture event */
03221       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
03222       {
03223 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03224         htim->IC_CaptureCallback(htim);
03225 #else
03226         HAL_TIM_IC_CaptureCallback(htim);
03227 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03228       }
03229       /* Output compare event */
03230       else
03231       {
03232 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03233         htim->OC_DelayElapsedCallback(htim);
03234         htim->PWM_PulseFinishedCallback(htim);
03235 #else
03236         HAL_TIM_OC_DelayElapsedCallback(htim);
03237         HAL_TIM_PWM_PulseFinishedCallback(htim);
03238 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03239       }
03240       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03241     }
03242   }
03243   /* Capture compare 3 event */
03244   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
03245   {
03246     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
03247     {
03248       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
03249       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03250       /* Input capture event */
03251       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
03252       {
03253 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03254         htim->IC_CaptureCallback(htim);
03255 #else
03256         HAL_TIM_IC_CaptureCallback(htim);
03257 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03258       }
03259       /* Output compare event */
03260       else
03261       {
03262 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03263         htim->OC_DelayElapsedCallback(htim);
03264         htim->PWM_PulseFinishedCallback(htim);
03265 #else
03266         HAL_TIM_OC_DelayElapsedCallback(htim);
03267         HAL_TIM_PWM_PulseFinishedCallback(htim);
03268 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03269       }
03270       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03271     }
03272   }
03273   /* Capture compare 4 event */
03274   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
03275   {
03276     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
03277     {
03278       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
03279       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03280       /* Input capture event */
03281       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
03282       {
03283 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03284         htim->IC_CaptureCallback(htim);
03285 #else
03286         HAL_TIM_IC_CaptureCallback(htim);
03287 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03288       }
03289       /* Output compare event */
03290       else
03291       {
03292 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03293         htim->OC_DelayElapsedCallback(htim);
03294         htim->PWM_PulseFinishedCallback(htim);
03295 #else
03296         HAL_TIM_OC_DelayElapsedCallback(htim);
03297         HAL_TIM_PWM_PulseFinishedCallback(htim);
03298 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03299       }
03300       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03301     }
03302   }
03303   /* TIM Update event */
03304   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
03305   {
03306     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
03307     {
03308       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
03309 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03310       htim->PeriodElapsedCallback(htim);
03311 #else
03312       HAL_TIM_PeriodElapsedCallback(htim);
03313 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03314     }
03315   }
03316   /* TIM Break input event */
03317   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
03318   {
03319     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03320     {
03321       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
03322 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03323       htim->BreakCallback(htim);
03324 #else
03325       HAL_TIMEx_BreakCallback(htim);
03326 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03327     }
03328   }
03329   /* TIM Break2 input event */
03330   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
03331   {
03332     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03333     {
03334       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
03335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03336       htim->Break2Callback(htim);
03337 #else
03338       HAL_TIMEx_Break2Callback(htim);
03339 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03340     }
03341   }
03342   /* TIM Trigger detection event */
03343   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
03344   {
03345     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
03346     {
03347       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
03348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03349       htim->TriggerCallback(htim);
03350 #else
03351       HAL_TIM_TriggerCallback(htim);
03352 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03353     }
03354   }
03355   /* TIM commutation event */
03356   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
03357   {
03358     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
03359     {
03360       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
03361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03362       htim->CommutationCallback(htim);
03363 #else
03364       HAL_TIMEx_CommutCallback(htim);
03365 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03366     }
03367   }
03368 }
03369
03370 /**
03371   * @}
03372   */
03373
03374 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
03375   *  @brief    TIM Peripheral Control functions
03376   *
03377 @verbatim
03378   ==============================================================================
03379                    ##### Peripheral Control functions #####
03380   ==============================================================================
03381  [..]
03382    This section provides functions allowing to:
03383       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
03384       (+) Configure External Clock source.
03385       (+) Configure Complementary channels, break features and dead time.
03386       (+) Configure Master and the Slave synchronization.
03387       (+) Configure the DMA Burst Mode.
03388
03389 @endverbatim
03390   * @{
03391   */
03392
03393 /**
03394   * @brief  Initializes the TIM Output Compare Channels according to the specified
03395   *         parameters in the TIM_OC_InitTypeDef.
03396   * @param  htim TIM Output Compare handle
03397   * @param  sConfig TIM Output Compare configuration structure
03398   * @param  Channel TIM Channels to configure
03399   *          This parameter can be one of the following values:
03400   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03401   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03402   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03403   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03404   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03405   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03406   * @retval HAL status
03407   */
03408 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
03409                                            TIM_OC_InitTypeDef *sConfig,
03410                                            uint32_t Channel)
03411 {
03412   /* Check the parameters */
03413   assert_param(IS_TIM_CHANNELS(Channel));
03414   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
03415   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03416
03417   /* Process Locked */
03418   __HAL_LOCK(htim);
03419
03420   htim->State = HAL_TIM_STATE_BUSY;
03421
03422   switch (Channel)
03423   {
03424     case TIM_CHANNEL_1:
03425     {
03426       /* Check the parameters */
03427       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03428
03429       /* Configure the TIM Channel 1 in Output Compare */
03430       TIM_OC1_SetConfig(htim->Instance, sConfig);
03431       break;
03432     }
03433
03434     case TIM_CHANNEL_2:
03435     {
03436       /* Check the parameters */
03437       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03438
03439       /* Configure the TIM Channel 2 in Output Compare */
03440       TIM_OC2_SetConfig(htim->Instance, sConfig);
03441       break;
03442     }
03443
03444     case TIM_CHANNEL_3:
03445     {
03446       /* Check the parameters */
03447       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03448
03449       /* Configure the TIM Channel 3 in Output Compare */
03450       TIM_OC3_SetConfig(htim->Instance, sConfig);
03451       break;
03452     }
03453
03454     case TIM_CHANNEL_4:
03455     {
03456       /* Check the parameters */
03457       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03458
03459       /* Configure the TIM Channel 4 in Output Compare */
03460       TIM_OC4_SetConfig(htim->Instance, sConfig);
03461       break;
03462     }
03463
03464     case TIM_CHANNEL_5:
03465     {
03466       /* Check the parameters */
03467       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03468
03469       /* Configure the TIM Channel 5 in Output Compare */
03470       TIM_OC5_SetConfig(htim->Instance, sConfig);
03471       break;
03472     }
03473
03474     case TIM_CHANNEL_6:
03475     {
03476       /* Check the parameters */
03477       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03478
03479       /* Configure the TIM Channel 6 in Output Compare */
03480       TIM_OC6_SetConfig(htim->Instance, sConfig);
03481       break;
03482     }
03483
03484     default:
03485       break;
03486   }
03487
03488   htim->State = HAL_TIM_STATE_READY;
03489
03490   __HAL_UNLOCK(htim);
03491
03492   return HAL_OK;
03493 }
03494
03495 /**
03496   * @brief  Initializes the TIM Input Capture Channels according to the specified
03497   *         parameters in the TIM_IC_InitTypeDef.
03498   * @param  htim TIM IC handle
03499   * @param  sConfig TIM Input Capture configuration structure
03500   * @param  Channel TIM Channel to configure
03501   *          This parameter can be one of the following values:
03502   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03503   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03504   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03505   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03506   * @retval HAL status
03507   */
03508 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
03509 {
03510   /* Check the parameters */
03511   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03512   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03513   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03514   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03515   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03516
03517   /* Process Locked */
03518   __HAL_LOCK(htim);
03519
03520   htim->State = HAL_TIM_STATE_BUSY;
03521
03522   if (Channel == TIM_CHANNEL_1)
03523   {
03524     /* TI1 Configuration */
03525     TIM_TI1_SetConfig(htim->Instance,
03526                       sConfig->ICPolarity,
03527                       sConfig->ICSelection,
03528                       sConfig->ICFilter);
03529
03530     /* Reset the IC1PSC Bits */
03531     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03532
03533     /* Set the IC1PSC value */
03534     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03535   }
03536   else if (Channel == TIM_CHANNEL_2)
03537   {
03538     /* TI2 Configuration */
03539     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03540
03541     TIM_TI2_SetConfig(htim->Instance,
03542                       sConfig->ICPolarity,
03543                       sConfig->ICSelection,
03544                       sConfig->ICFilter);
03545
03546     /* Reset the IC2PSC Bits */
03547     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03548
03549     /* Set the IC2PSC value */
03550     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
03551   }
03552   else if (Channel == TIM_CHANNEL_3)
03553   {
03554     /* TI3 Configuration */
03555     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03556
03557     TIM_TI3_SetConfig(htim->Instance,
03558                       sConfig->ICPolarity,
03559                       sConfig->ICSelection,
03560                       sConfig->ICFilter);
03561
03562     /* Reset the IC3PSC Bits */
03563     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03564
03565     /* Set the IC3PSC value */
03566     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03567   }
03568   else
03569   {
03570     /* TI4 Configuration */
03571     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03572
03573     TIM_TI4_SetConfig(htim->Instance,
03574                       sConfig->ICPolarity,
03575                       sConfig->ICSelection,
03576                       sConfig->ICFilter);
03577
03578     /* Reset the IC4PSC Bits */
03579     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03580
03581     /* Set the IC4PSC value */
03582     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
03583   }
03584
03585   htim->State = HAL_TIM_STATE_READY;
03586
03587   __HAL_UNLOCK(htim);
03588
03589   return HAL_OK;
03590 }
03591
03592 /**
03593   * @brief  Initializes the TIM PWM  channels according to the specified
03594   *         parameters in the TIM_OC_InitTypeDef.
03595   * @param  htim TIM PWM handle
03596   * @param  sConfig TIM PWM configuration structure
03597   * @param  Channel TIM Channels to be configured
03598   *          This parameter can be one of the following values:
03599   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03600   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03601   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03602   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03603   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03604   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03605   * @retval HAL status
03606   */
03607 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
03608                                             TIM_OC_InitTypeDef *sConfig,
03609                                             uint32_t Channel)
03610 {
03611   /* Check the parameters */
03612   assert_param(IS_TIM_CHANNELS(Channel));
03613   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03614   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03615   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03616
03617   /* Process Locked */
03618   __HAL_LOCK(htim);
03619
03620   htim->State = HAL_TIM_STATE_BUSY;
03621
03622   switch (Channel)
03623   {
03624     case TIM_CHANNEL_1:
03625     {
03626       /* Check the parameters */
03627       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03628
03629       /* Configure the Channel 1 in PWM mode */
03630       TIM_OC1_SetConfig(htim->Instance, sConfig);
03631
03632       /* Set the Preload enable bit for channel1 */
03633       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03634
03635       /* Configure the Output Fast mode */
03636       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03637       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03638       break;
03639     }
03640
03641     case TIM_CHANNEL_2:
03642     {
03643       /* Check the parameters */
03644       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03645
03646       /* Configure the Channel 2 in PWM mode */
03647       TIM_OC2_SetConfig(htim->Instance, sConfig);
03648
03649       /* Set the Preload enable bit for channel2 */
03650       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03651
03652       /* Configure the Output Fast mode */
03653       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03654       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
03655       break;
03656     }
03657
03658     case TIM_CHANNEL_3:
03659     {
03660       /* Check the parameters */
03661       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03662
03663       /* Configure the Channel 3 in PWM mode */
03664       TIM_OC3_SetConfig(htim->Instance, sConfig);
03665
03666       /* Set the Preload enable bit for channel3 */
03667       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03668
03669       /* Configure the Output Fast mode */
03670       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03671       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03672       break;
03673     }
03674
03675     case TIM_CHANNEL_4:
03676     {
03677       /* Check the parameters */
03678       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03679
03680       /* Configure the Channel 4 in PWM mode */
03681       TIM_OC4_SetConfig(htim->Instance, sConfig);
03682
03683       /* Set the Preload enable bit for channel4 */
03684       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03685
03686       /* Configure the Output Fast mode */
03687       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03688       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
03689       break;
03690     }
03691
03692     case TIM_CHANNEL_5:
03693     {
03694       /* Check the parameters */
03695       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03696
03697       /* Configure the Channel 5 in PWM mode */
03698       TIM_OC5_SetConfig(htim->Instance, sConfig);
03699
03700       /* Set the Preload enable bit for channel5*/
03701       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
03702
03703       /* Configure the Output Fast mode */
03704       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
03705       htim->Instance->CCMR3 |= sConfig->OCFastMode;
03706       break;
03707     }
03708
03709     case TIM_CHANNEL_6:
03710     {
03711       /* Check the parameters */
03712       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03713
03714       /* Configure the Channel 6 in PWM mode */
03715       TIM_OC6_SetConfig(htim->Instance, sConfig);
03716
03717       /* Set the Preload enable bit for channel6 */
03718       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
03719
03720       /* Configure the Output Fast mode */
03721       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
03722       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
03723       break;
03724     }
03725
03726     default:
03727       break;
03728   }
03729
03730   htim->State = HAL_TIM_STATE_READY;
03731
03732   __HAL_UNLOCK(htim);
03733
03734   return HAL_OK;
03735 }
03736
03737 /**
03738   * @brief  Initializes the TIM One Pulse Channels according to the specified
03739   *         parameters in the TIM_OnePulse_InitTypeDef.
03740   * @param  htim TIM One Pulse handle
03741   * @param  sConfig TIM One Pulse configuration structure
03742   * @param  OutputChannel TIM output channel to configure
03743   *          This parameter can be one of the following values:
03744   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03745   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03746   * @param  InputChannel TIM input Channel to configure
03747   *          This parameter can be one of the following values:
03748   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03749   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03750   * @note  To output a waveform with a minimum delay user can enable the fast
03751   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
03752   *        output is forced in response to the edge detection on TIx input,
03753   *        without taking in account the comparison.
03754   * @retval HAL status
03755   */
03756 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
03757                                                  uint32_t OutputChannel,  uint32_t InputChannel)
03758 {
03759   TIM_OC_InitTypeDef temp1;
03760
03761   /* Check the parameters */
03762   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03763   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03764
03765   if (OutputChannel != InputChannel)
03766   {
03767     /* Process Locked */
03768     __HAL_LOCK(htim);
03769
03770     htim->State = HAL_TIM_STATE_BUSY;
03771
03772     /* Extract the Output compare configuration from sConfig structure */
03773     temp1.OCMode = sConfig->OCMode;
03774     temp1.Pulse = sConfig->Pulse;
03775     temp1.OCPolarity = sConfig->OCPolarity;
03776     temp1.OCNPolarity = sConfig->OCNPolarity;
03777     temp1.OCIdleState = sConfig->OCIdleState;
03778     temp1.OCNIdleState = sConfig->OCNIdleState;
03779
03780     switch (OutputChannel)
03781     {
03782       case TIM_CHANNEL_1:
03783       {
03784         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03785
03786         TIM_OC1_SetConfig(htim->Instance, &temp1);
03787         break;
03788       }
03789       case TIM_CHANNEL_2:
03790       {
03791         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03792
03793         TIM_OC2_SetConfig(htim->Instance, &temp1);
03794         break;
03795       }
03796       default:
03797         break;
03798     }
03799
03800     switch (InputChannel)
03801     {
03802       case TIM_CHANNEL_1:
03803       {
03804         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03805
03806         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03807                           sConfig->ICSelection, sConfig->ICFilter);
03808
03809         /* Reset the IC1PSC Bits */
03810         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03811
03812         /* Select the Trigger source */
03813         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03814         htim->Instance->SMCR |= TIM_TS_TI1FP1;
03815
03816         /* Select the Slave Mode */
03817         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03818         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03819         break;
03820       }
03821       case TIM_CHANNEL_2:
03822       {
03823         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03824
03825         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03826                           sConfig->ICSelection, sConfig->ICFilter);
03827
03828         /* Reset the IC2PSC Bits */
03829         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03830
03831         /* Select the Trigger source */
03832         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03833         htim->Instance->SMCR |= TIM_TS_TI2FP2;
03834
03835         /* Select the Slave Mode */
03836         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03837         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03838         break;
03839       }
03840
03841       default:
03842         break;
03843     }
03844
03845     htim->State = HAL_TIM_STATE_READY;
03846
03847     __HAL_UNLOCK(htim);
03848
03849     return HAL_OK;
03850   }
03851   else
03852   {
03853     return HAL_ERROR;
03854   }
03855 }
03856
03857 /**
03858   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03859   * @param  htim TIM handle
03860   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
03861   *         This parameter can be one of the following values:
03862   *            @arg TIM_DMABASE_CR1
03863   *            @arg TIM_DMABASE_CR2
03864   *            @arg TIM_DMABASE_SMCR
03865   *            @arg TIM_DMABASE_DIER
03866   *            @arg TIM_DMABASE_SR
03867   *            @arg TIM_DMABASE_EGR
03868   *            @arg TIM_DMABASE_CCMR1
03869   *            @arg TIM_DMABASE_CCMR2
03870   *            @arg TIM_DMABASE_CCER
03871   *            @arg TIM_DMABASE_CNT
03872   *            @arg TIM_DMABASE_PSC
03873   *            @arg TIM_DMABASE_ARR
03874   *            @arg TIM_DMABASE_RCR
03875   *            @arg TIM_DMABASE_CCR1
03876   *            @arg TIM_DMABASE_CCR2
03877   *            @arg TIM_DMABASE_CCR3
03878   *            @arg TIM_DMABASE_CCR4
03879   *            @arg TIM_DMABASE_BDTR
03880   *            @arg TIM_DMABASE_CCMR3
03881   *            @arg TIM_DMABASE_CCR5
03882   *            @arg TIM_DMABASE_CCR6
03883   *            @arg TIM_DMABASE_AF1
03884   *            @arg TIM_DMABASE_AF2
03885   *            @arg TIM_DMABASE_TISEL
03886   *
03887   * @param  BurstRequestSrc TIM DMA Request sources
03888   *         This parameter can be one of the following values:
03889   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03890   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03891   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03892   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03893   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03894   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03895   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03896   * @param  BurstBuffer The Buffer address.
03897   * @param  BurstLength DMA Burst length. This parameter can be one value
03898   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03899   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
03900   * @retval HAL status
03901   */
03902 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
03903                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
03904 {
03905   return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
03906                                           ((BurstLength) >> 8U) + 1U);
03907 }
03908
03909 /**
03910   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
03911   * @param  htim TIM handle
03912   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
03913   *         This parameter can be one of the following values:
03914   *            @arg TIM_DMABASE_CR1
03915   *            @arg TIM_DMABASE_CR2
03916   *            @arg TIM_DMABASE_SMCR
03917   *            @arg TIM_DMABASE_DIER
03918   *            @arg TIM_DMABASE_SR
03919   *            @arg TIM_DMABASE_EGR
03920   *            @arg TIM_DMABASE_CCMR1
03921   *            @arg TIM_DMABASE_CCMR2
03922   *            @arg TIM_DMABASE_CCER
03923   *            @arg TIM_DMABASE_CNT
03924   *            @arg TIM_DMABASE_PSC
03925   *            @arg TIM_DMABASE_ARR
03926   *            @arg TIM_DMABASE_RCR
03927   *            @arg TIM_DMABASE_CCR1
03928   *            @arg TIM_DMABASE_CCR2
03929   *            @arg TIM_DMABASE_CCR3
03930   *            @arg TIM_DMABASE_CCR4
03931   *            @arg TIM_DMABASE_BDTR
03932   *            @arg TIM_DMABASE_CCMR3
03933   *            @arg TIM_DMABASE_CCR5
03934   *            @arg TIM_DMABASE_CCR6
03935   *            @arg TIM_DMABASE_AF1
03936   *            @arg TIM_DMABASE_AF2
03937   *            @arg TIM_DMABASE_TISEL
03938   *
03939   * @param  BurstRequestSrc TIM DMA Request sources
03940   *         This parameter can be one of the following values:
03941   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03942   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03943   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03944   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03945   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03946   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03947   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03948   * @param  BurstBuffer The Buffer address.
03949   * @param  BurstLength DMA Burst length. This parameter can be one value
03950   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03951   * @param  DataLength Data length. This parameter can be one value
03952   *         between 1 and 0xFFFF.
03953   * @retval HAL status
03954   */
03955 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
03956                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
03957                                                    uint32_t  BurstLength,  uint32_t  DataLength)
03958 {
03959   /* Check the parameters */
03960   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03961   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03962   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03963   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03964   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
03965
03966   if (htim->State == HAL_TIM_STATE_BUSY)
03967   {
03968     return HAL_BUSY;
03969   }
03970   else if (htim->State == HAL_TIM_STATE_READY)
03971   {
03972     if ((BurstBuffer == NULL) && (BurstLength > 0U))
03973     {
03974       return HAL_ERROR;
03975     }
03976     else
03977     {
03978       htim->State = HAL_TIM_STATE_BUSY;
03979     }
03980   }
03981   else
03982   {
03983     /* nothing to do */
03984   }
03985   switch (BurstRequestSrc)
03986   {
03987     case TIM_DMA_UPDATE:
03988     {
03989       /* Set the DMA Period elapsed callbacks */
03990       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03991       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
03992
03993       /* Set the DMA error callback */
03994       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03995
03996       /* Enable the DMA stream */
03997       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
03998                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
03999       {
04000         return HAL_ERROR;
04001       }
04002       break;
04003     }
04004     case TIM_DMA_CC1:
04005     {
04006       /* Set the DMA compare callbacks */
04007       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
04008       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04009
04010       /* Set the DMA error callback */
04011       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
04012
04013       /* Enable the DMA stream */
04014       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
04015                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04016       {
04017         return HAL_ERROR;
04018       }
04019       break;
04020     }
04021     case TIM_DMA_CC2:
04022     {
04023       /* Set the DMA compare callbacks */
04024       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
04025       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04026
04027       /* Set the DMA error callback */
04028       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
04029
04030       /* Enable the DMA stream */
04031       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
04032                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04033       {
04034         return HAL_ERROR;
04035       }
04036       break;
04037     }
04038     case TIM_DMA_CC3:
04039     {
04040       /* Set the DMA compare callbacks */
04041       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
04042       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04043
04044       /* Set the DMA error callback */
04045       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
04046
04047       /* Enable the DMA stream */
04048       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
04049                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04050       {
04051         return HAL_ERROR;
04052       }
04053       break;
04054     }
04055     case TIM_DMA_CC4:
04056     {
04057       /* Set the DMA compare callbacks */
04058       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
04059       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04060
04061       /* Set the DMA error callback */
04062       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04063
04064       /* Enable the DMA stream */
04065       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
04066                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04067       {
04068         return HAL_ERROR;
04069       }
04070       break;
04071     }
04072     case TIM_DMA_COM:
04073     {
04074       /* Set the DMA commutation callbacks */
04075       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04076       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04077
04078       /* Set the DMA error callback */
04079       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04080
04081       /* Enable the DMA stream */
04082       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
04083                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04084       {
04085         return HAL_ERROR;
04086       }
04087       break;
04088     }
04089     case TIM_DMA_TRIGGER:
04090     {
04091       /* Set the DMA trigger callbacks */
04092       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04093       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04094
04095       /* Set the DMA error callback */
04096       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04097
04098       /* Enable the DMA stream */
04099       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
04100                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04101       {
04102         return HAL_ERROR;
04103       }
04104       break;
04105     }
04106     default:
04107       break;
04108   }
04109
04110   /* Configure the DMA Burst Mode */
04111   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04112   /* Enable the TIM DMA Request */
04113   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04114
04115   htim->State = HAL_TIM_STATE_READY;
04116
04117   /* Return function status */
04118   return HAL_OK;
04119 }
04120
04121 /**
04122   * @brief  Stops the TIM DMA Burst mode
04123   * @param  htim TIM handle
04124   * @param  BurstRequestSrc TIM DMA Request sources to disable
04125   * @retval HAL status
04126   */
04127 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04128 {
04129   HAL_StatusTypeDef status = HAL_OK;
04130   /* Check the parameters */
04131   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04132
04133   /* Abort the DMA transfer (at least disable the DMA stream) */
04134   switch (BurstRequestSrc)
04135   {
04136     case TIM_DMA_UPDATE:
04137     {
04138       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04139       break;
04140     }
04141     case TIM_DMA_CC1:
04142     {
04143       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04144       break;
04145     }
04146     case TIM_DMA_CC2:
04147     {
04148       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04149       break;
04150     }
04151     case TIM_DMA_CC3:
04152     {
04153       status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04154       break;
04155     }
04156     case TIM_DMA_CC4:
04157     {
04158       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04159       break;
04160     }
04161     case TIM_DMA_COM:
04162     {
04163       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04164       break;
04165     }
04166     case TIM_DMA_TRIGGER:
04167     {
04168       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04169       break;
04170     }
04171     default:
04172       break;
04173   }
04174
04175   if (HAL_OK == status)
04176   {
04177     /* Disable the TIM Update DMA request */
04178     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04179   }
04180
04181   /* Return function status */
04182   return status;
04183 }
04184
04185 /**
04186   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04187   * @param  htim TIM handle
04188   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04189   *         This parameter can be one of the following values:
04190   *            @arg TIM_DMABASE_CR1
04191   *            @arg TIM_DMABASE_CR2
04192   *            @arg TIM_DMABASE_SMCR
04193   *            @arg TIM_DMABASE_DIER
04194   *            @arg TIM_DMABASE_SR
04195   *            @arg TIM_DMABASE_EGR
04196   *            @arg TIM_DMABASE_CCMR1
04197   *            @arg TIM_DMABASE_CCMR2
04198   *            @arg TIM_DMABASE_CCER
04199   *            @arg TIM_DMABASE_CNT
04200   *            @arg TIM_DMABASE_PSC
04201   *            @arg TIM_DMABASE_ARR
04202   *            @arg TIM_DMABASE_RCR
04203   *            @arg TIM_DMABASE_CCR1
04204   *            @arg TIM_DMABASE_CCR2
04205   *            @arg TIM_DMABASE_CCR3
04206   *            @arg TIM_DMABASE_CCR4
04207   *            @arg TIM_DMABASE_BDTR
04208   *            @arg TIM_DMABASE_CCMR3
04209   *            @arg TIM_DMABASE_CCR5
04210   *            @arg TIM_DMABASE_CCR6
04211   *            @arg TIM_DMABASE_AF1
04212   *            @arg TIM_DMABASE_AF2
04213   *            @arg TIM_DMABASE_TISEL
04214   *
04215   * @param  BurstRequestSrc TIM DMA Request sources
04216   *         This parameter can be one of the following values:
04217   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04218   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04219   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04220   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04221   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04222   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04223   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04224   * @param  BurstBuffer The Buffer address.
04225   * @param  BurstLength DMA Burst length. This parameter can be one value
04226   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04227   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04228   * @retval HAL status
04229   */
04230 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04231                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
04232 {
04233   return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
04234                                          ((BurstLength) >> 8U) + 1U);
04235 }
04236
04237 /**
04238   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04239   * @param  htim TIM handle
04240   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04241   *         This parameter can be one of the following values:
04242   *            @arg TIM_DMABASE_CR1
04243   *            @arg TIM_DMABASE_CR2
04244   *            @arg TIM_DMABASE_SMCR
04245   *            @arg TIM_DMABASE_DIER
04246   *            @arg TIM_DMABASE_SR
04247   *            @arg TIM_DMABASE_EGR
04248   *            @arg TIM_DMABASE_CCMR1
04249   *            @arg TIM_DMABASE_CCMR2
04250   *            @arg TIM_DMABASE_CCER
04251   *            @arg TIM_DMABASE_CNT
04252   *            @arg TIM_DMABASE_PSC
04253   *            @arg TIM_DMABASE_ARR
04254   *            @arg TIM_DMABASE_RCR
04255   *            @arg TIM_DMABASE_CCR1
04256   *            @arg TIM_DMABASE_CCR2
04257   *            @arg TIM_DMABASE_CCR3
04258   *            @arg TIM_DMABASE_CCR4
04259   *            @arg TIM_DMABASE_BDTR
04260   *            @arg TIM_DMABASE_CCMR3
04261   *            @arg TIM_DMABASE_CCR5
04262   *            @arg TIM_DMABASE_CCR6
04263   *            @arg TIM_DMABASE_AF1
04264   *            @arg TIM_DMABASE_AF2
04265   *            @arg TIM_DMABASE_TISEL
04266   *
04267   * @param  BurstRequestSrc TIM DMA Request sources
04268   *         This parameter can be one of the following values:
04269   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04270   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04271   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04272   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04273   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04274   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04275   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04276   * @param  BurstBuffer The Buffer address.
04277   * @param  BurstLength DMA Burst length. This parameter can be one value
04278   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04279   * @param  DataLength Data length. This parameter can be one value
04280   *         between 1 and 0xFFFF.
04281   * @retval HAL status
04282   */
04283 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04284                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
04285                                                   uint32_t  BurstLength, uint32_t  DataLength)
04286 {
04287   /* Check the parameters */
04288   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
04289   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
04290   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04291   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
04292   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
04293
04294   if (htim->State == HAL_TIM_STATE_BUSY)
04295   {
04296     return HAL_BUSY;
04297   }
04298   else if (htim->State == HAL_TIM_STATE_READY)
04299   {
04300     if ((BurstBuffer == NULL) && (BurstLength > 0U))
04301     {
04302       return HAL_ERROR;
04303     }
04304     else
04305     {
04306       htim->State = HAL_TIM_STATE_BUSY;
04307     }
04308   }
04309   else
04310   {
04311     /* nothing to do */
04312   }
04313   switch (BurstRequestSrc)
04314   {
04315     case TIM_DMA_UPDATE:
04316     {
04317       /* Set the DMA Period elapsed callbacks */
04318       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
04319       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
04320
04321       /* Set the DMA error callback */
04322       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
04323
04324       /* Enable the DMA stream */
04325       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04326                            DataLength) != HAL_OK)
04327       {
04328         return HAL_ERROR;
04329       }
04330       break;
04331     }
04332     case TIM_DMA_CC1:
04333     {
04334       /* Set the DMA capture callbacks */
04335       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
04336       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04337
04338       /* Set the DMA error callback */
04339       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
04340
04341       /* Enable the DMA stream */
04342       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04343                            DataLength) != HAL_OK)
04344       {
04345         return HAL_ERROR;
04346       }
04347       break;
04348     }
04349     case TIM_DMA_CC2:
04350     {
04351       /* Set the DMA capture callbacks */
04352       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
04353       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04354
04355       /* Set the DMA error callback */
04356       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
04357
04358       /* Enable the DMA stream */
04359       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04360                            DataLength) != HAL_OK)
04361       {
04362         return HAL_ERROR;
04363       }
04364       break;
04365     }
04366     case TIM_DMA_CC3:
04367     {
04368       /* Set the DMA capture callbacks */
04369       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
04370       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04371
04372       /* Set the DMA error callback */
04373       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
04374
04375       /* Enable the DMA stream */
04376       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04377                            DataLength) != HAL_OK)
04378       {
04379         return HAL_ERROR;
04380       }
04381       break;
04382     }
04383     case TIM_DMA_CC4:
04384     {
04385       /* Set the DMA capture callbacks */
04386       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
04387       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04388
04389       /* Set the DMA error callback */
04390       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04391
04392       /* Enable the DMA stream */
04393       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04394                            DataLength) != HAL_OK)
04395       {
04396         return HAL_ERROR;
04397       }
04398       break;
04399     }
04400     case TIM_DMA_COM:
04401     {
04402       /* Set the DMA commutation callbacks */
04403       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04404       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04405
04406       /* Set the DMA error callback */
04407       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04408
04409       /* Enable the DMA stream */
04410       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04411                            DataLength) != HAL_OK)
04412       {
04413         return HAL_ERROR;
04414       }
04415       break;
04416     }
04417     case TIM_DMA_TRIGGER:
04418     {
04419       /* Set the DMA trigger callbacks */
04420       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04421       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04422
04423       /* Set the DMA error callback */
04424       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04425
04426       /* Enable the DMA stream */
04427       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
04428                            DataLength) != HAL_OK)
04429       {
04430         return HAL_ERROR;
04431       }
04432       break;
04433     }
04434     default:
04435       break;
04436   }
04437
04438   /* Configure the DMA Burst Mode */
04439   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04440
04441   /* Enable the TIM DMA Request */
04442   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04443
04444   htim->State = HAL_TIM_STATE_READY;
04445
04446   /* Return function status */
04447   return HAL_OK;
04448 }
04449
04450 /**
04451   * @brief  Stop the DMA burst reading
04452   * @param  htim TIM handle
04453   * @param  BurstRequestSrc TIM DMA Request sources to disable.
04454   * @retval HAL status
04455   */
04456 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04457 {
04458   HAL_StatusTypeDef status = HAL_OK;
04459   /* Check the parameters */
04460   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04461
04462   /* Abort the DMA transfer (at least disable the DMA stream) */
04463   switch (BurstRequestSrc)
04464   {
04465     case TIM_DMA_UPDATE:
04466     {
04467       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04468       break;
04469     }
04470     case TIM_DMA_CC1:
04471     {
04472       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04473       break;
04474     }
04475     case TIM_DMA_CC2:
04476     {
04477       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04478       break;
04479     }
04480     case TIM_DMA_CC3:
04481     {
04482       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04483       break;
04484     }
04485     case TIM_DMA_CC4:
04486     {
04487       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04488       break;
04489     }
04490     case TIM_DMA_COM:
04491     {
04492       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04493       break;
04494     }
04495     case TIM_DMA_TRIGGER:
04496     {
04497       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04498       break;
04499     }
04500     default:
04501       break;
04502   }
04503
04504   if (HAL_OK == status)
04505   {
04506     /* Disable the TIM Update DMA request */
04507     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04508   }
04509
04510   /* Return function status */
04511   return status;
04512 }
04513
04514 /**
04515   * @brief  Generate a software event
04516   * @param  htim TIM handle
04517   * @param  EventSource specifies the event source.
04518   *          This parameter can be one of the following values:
04519   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
04520   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
04521   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
04522   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
04523   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
04524   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
04525   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
04526   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
04527   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
04528   * @note   Basic timers can only generate an update event.
04529   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
04530   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
04531   *         only for timer instances supporting break input(s).
04532   * @retval HAL status
04533   */
04534
04535 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
04536 {
04537   /* Check the parameters */
04538   assert_param(IS_TIM_INSTANCE(htim->Instance));
04539   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
04540
04541   /* Process Locked */
04542   __HAL_LOCK(htim);
04543
04544   /* Change the TIM state */
04545   htim->State = HAL_TIM_STATE_BUSY;
04546
04547   /* Set the event sources */
04548   htim->Instance->EGR = EventSource;
04549
04550   /* Change the TIM state */
04551   htim->State = HAL_TIM_STATE_READY;
04552
04553   __HAL_UNLOCK(htim);
04554
04555   /* Return function status */
04556   return HAL_OK;
04557 }
04558
04559 /**
04560   * @brief  Configures the OCRef clear feature
04561   * @param  htim TIM handle
04562   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
04563   *         contains the OCREF clear feature and parameters for the TIM peripheral.
04564   * @param  Channel specifies the TIM Channel
04565   *          This parameter can be one of the following values:
04566   *            @arg TIM_CHANNEL_1: TIM Channel 1
04567   *            @arg TIM_CHANNEL_2: TIM Channel 2
04568   *            @arg TIM_CHANNEL_3: TIM Channel 3
04569   *            @arg TIM_CHANNEL_4: TIM Channel 4
04570   *            @arg TIM_CHANNEL_5: TIM Channel 5
04571   *            @arg TIM_CHANNEL_6: TIM Channel 6
04572   * @retval HAL status
04573   */
04574 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
04575                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
04576                                            uint32_t Channel)
04577 {
04578   /* Check the parameters */
04579   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
04580   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
04581
04582   /* Process Locked */
04583   __HAL_LOCK(htim);
04584
04585   htim->State = HAL_TIM_STATE_BUSY;
04586
04587   switch (sClearInputConfig->ClearInputSource)
04588   {
04589     case TIM_CLEARINPUTSOURCE_NONE:
04590     {
04591       /* Clear the OCREF clear selection bit and the the ETR Bits */
04592       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
04593       break;
04594     }
04595
04596     case TIM_CLEARINPUTSOURCE_ETR:
04597     {
04598       /* Check the parameters */
04599       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
04600       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
04601       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
04602
04603       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
04604       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
04605       {
04606         htim->State = HAL_TIM_STATE_READY;
04607         __HAL_UNLOCK(htim);
04608         return HAL_ERROR;
04609       }
04610
04611       TIM_ETR_SetConfig(htim->Instance,
04612                         sClearInputConfig->ClearInputPrescaler,
04613                         sClearInputConfig->ClearInputPolarity,
04614                         sClearInputConfig->ClearInputFilter);
04615       break;
04616     }
04617
04618     default:
04619       break;
04620   }
04621
04622   switch (Channel)
04623   {
04624     case TIM_CHANNEL_1:
04625     {
04626       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04627       {
04628         /* Enable the OCREF clear feature for Channel 1 */
04629         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
04630       }
04631       else
04632       {
04633         /* Disable the OCREF clear feature for Channel 1 */
04634         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
04635       }
04636       break;
04637     }
04638     case TIM_CHANNEL_2:
04639     {
04640       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04641       {
04642         /* Enable the OCREF clear feature for Channel 2 */
04643         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
04644       }
04645       else
04646       {
04647         /* Disable the OCREF clear feature for Channel 2 */
04648         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
04649       }
04650       break;
04651     }
04652     case TIM_CHANNEL_3:
04653     {
04654       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04655       {
04656         /* Enable the OCREF clear feature for Channel 3 */
04657         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
04658       }
04659       else
04660       {
04661         /* Disable the OCREF clear feature for Channel 3 */
04662         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
04663       }
04664       break;
04665     }
04666     case TIM_CHANNEL_4:
04667     {
04668       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04669       {
04670         /* Enable the OCREF clear feature for Channel 4 */
04671         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
04672       }
04673       else
04674       {
04675         /* Disable the OCREF clear feature for Channel 4 */
04676         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
04677       }
04678       break;
04679     }
04680     case TIM_CHANNEL_5:
04681     {
04682       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04683       {
04684         /* Enable the OCREF clear feature for Channel 5 */
04685         SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
04686       }
04687       else
04688       {
04689         /* Disable the OCREF clear feature for Channel 5 */
04690         CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
04691       }
04692       break;
04693     }
04694     case TIM_CHANNEL_6:
04695     {
04696       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04697       {
04698         /* Enable the OCREF clear feature for Channel 6 */
04699         SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
04700       }
04701       else
04702       {
04703         /* Disable the OCREF clear feature for Channel 6 */
04704         CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
04705       }
04706       break;
04707     }
04708     default:
04709       break;
04710   }
04711
04712   htim->State = HAL_TIM_STATE_READY;
04713
04714   __HAL_UNLOCK(htim);
04715
04716   return HAL_OK;
04717 }
04718
04719 /**
04720   * @brief   Configures the clock source to be used
04721   * @param  htim TIM handle
04722   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
04723   *         contains the clock source information for the TIM peripheral.
04724   * @retval HAL status
04725   */
04726 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
04727 {
04728   uint32_t tmpsmcr;
04729
04730   /* Process Locked */
04731   __HAL_LOCK(htim);
04732
04733   htim->State = HAL_TIM_STATE_BUSY;
04734
04735   /* Check the parameters */
04736   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
04737
04738   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
04739   tmpsmcr = htim->Instance->SMCR;
04740   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04741   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
04742   htim->Instance->SMCR = tmpsmcr;
04743
04744   switch (sClockSourceConfig->ClockSource)
04745   {
04746     case TIM_CLOCKSOURCE_INTERNAL:
04747     {
04748       assert_param(IS_TIM_INSTANCE(htim->Instance));
04749       break;
04750     }
04751
04752     case TIM_CLOCKSOURCE_ETRMODE1:
04753     {
04754       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
04755       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04756
04757       /* Check ETR input conditioning related parameters */
04758       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04759       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04760       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04761
04762       /* Configure the ETR Clock source */
04763       TIM_ETR_SetConfig(htim->Instance,
04764                         sClockSourceConfig->ClockPrescaler,
04765                         sClockSourceConfig->ClockPolarity,
04766                         sClockSourceConfig->ClockFilter);
04767
04768       /* Select the External clock mode1 and the ETRF trigger */
04769       tmpsmcr = htim->Instance->SMCR;
04770       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04771       /* Write to TIMx SMCR */
04772       htim->Instance->SMCR = tmpsmcr;
04773       break;
04774     }
04775
04776     case TIM_CLOCKSOURCE_ETRMODE2:
04777     {
04778       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
04779       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
04780
04781       /* Check ETR input conditioning related parameters */
04782       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04783       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04784       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04785
04786       /* Configure the ETR Clock source */
04787       TIM_ETR_SetConfig(htim->Instance,
04788                         sClockSourceConfig->ClockPrescaler,
04789                         sClockSourceConfig->ClockPolarity,
04790                         sClockSourceConfig->ClockFilter);
04791       /* Enable the External clock mode2 */
04792       htim->Instance->SMCR |= TIM_SMCR_ECE;
04793       break;
04794     }
04795
04796     case TIM_CLOCKSOURCE_TI1:
04797     {
04798       /* Check whether or not the timer instance supports external clock mode 1 */
04799       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04800
04801       /* Check TI1 input conditioning related parameters */
04802       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04803       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04804
04805       TIM_TI1_ConfigInputStage(htim->Instance,
04806                                sClockSourceConfig->ClockPolarity,
04807                                sClockSourceConfig->ClockFilter);
04808       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04809       break;
04810     }
04811
04812     case TIM_CLOCKSOURCE_TI2:
04813     {
04814       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04815       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04816
04817       /* Check TI2 input conditioning related parameters */
04818       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04819       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04820
04821       TIM_TI2_ConfigInputStage(htim->Instance,
04822                                sClockSourceConfig->ClockPolarity,
04823                                sClockSourceConfig->ClockFilter);
04824       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04825       break;
04826     }
04827
04828     case TIM_CLOCKSOURCE_TI1ED:
04829     {
04830       /* Check whether or not the timer instance supports external clock mode 1 */
04831       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04832
04833       /* Check TI1 input conditioning related parameters */
04834       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04835       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04836
04837       TIM_TI1_ConfigInputStage(htim->Instance,
04838                                sClockSourceConfig->ClockPolarity,
04839                                sClockSourceConfig->ClockFilter);
04840       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04841       break;
04842     }
04843
04844     case TIM_CLOCKSOURCE_ITR0:
04845     case TIM_CLOCKSOURCE_ITR1:
04846     case TIM_CLOCKSOURCE_ITR2:
04847     case TIM_CLOCKSOURCE_ITR3:
04848     case TIM_CLOCKSOURCE_ITR4:
04849     case TIM_CLOCKSOURCE_ITR5:
04850     case TIM_CLOCKSOURCE_ITR6:
04851     case TIM_CLOCKSOURCE_ITR7:
04852     case TIM_CLOCKSOURCE_ITR8:
04853     {
04854       /* Check whether or not the timer instance supports internal trigger input */
04855       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04856
04857       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
04858       break;
04859     }
04860
04861     default:
04862       break;
04863   }
04864   htim->State = HAL_TIM_STATE_READY;
04865
04866   __HAL_UNLOCK(htim);
04867
04868   return HAL_OK;
04869 }
04870
04871 /**
04872   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04873   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04874   * @param  htim TIM handle.
04875   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
04876   *         output of a XOR gate.
04877   *          This parameter can be one of the following values:
04878   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04879   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04880   *            pins are connected to the TI1 input (XOR combination)
04881   * @retval HAL status
04882   */
04883 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04884 {
04885   uint32_t tmpcr2;
04886
04887   /* Check the parameters */
04888   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04889   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04890
04891   /* Get the TIMx CR2 register value */
04892   tmpcr2 = htim->Instance->CR2;
04893
04894   /* Reset the TI1 selection */
04895   tmpcr2 &= ~TIM_CR2_TI1S;
04896
04897   /* Set the TI1 selection */
04898   tmpcr2 |= TI1_Selection;
04899
04900   /* Write to TIMxCR2 */
04901   htim->Instance->CR2 = tmpcr2;
04902
04903   return HAL_OK;
04904 }
04905
04906 /**
04907   * @brief  Configures the TIM in Slave mode
04908   * @param  htim TIM handle.
04909   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04910   *         contains the selected trigger (internal trigger input, filtered
04911   *         timer input or external trigger input) and the Slave mode
04912   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04913   * @retval HAL status
04914   */
04915 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
04916 {
04917   /* Check the parameters */
04918   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04919   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04920   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04921
04922   __HAL_LOCK(htim);
04923
04924   htim->State = HAL_TIM_STATE_BUSY;
04925
04926   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
04927   {
04928     htim->State = HAL_TIM_STATE_READY;
04929     __HAL_UNLOCK(htim);
04930     return HAL_ERROR;
04931   }
04932
04933   /* Disable Trigger Interrupt */
04934   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04935
04936   /* Disable Trigger DMA request */
04937   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04938
04939   htim->State = HAL_TIM_STATE_READY;
04940
04941   __HAL_UNLOCK(htim);
04942
04943   return HAL_OK;
04944 }
04945
04946 /**
04947   * @brief  Configures the TIM in Slave mode in interrupt mode
04948   * @param  htim TIM handle.
04949   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04950   *         contains the selected trigger (internal trigger input, filtered
04951   *         timer input or external trigger input) and the Slave mode
04952   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04953   * @retval HAL status
04954   */
04955 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
04956                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
04957 {
04958   /* Check the parameters */
04959   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04960   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04961   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04962
04963   __HAL_LOCK(htim);
04964
04965   htim->State = HAL_TIM_STATE_BUSY;
04966
04967   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
04968   {
04969     htim->State = HAL_TIM_STATE_READY;
04970     __HAL_UNLOCK(htim);
04971     return HAL_ERROR;
04972   }
04973
04974   /* Enable Trigger Interrupt */
04975   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04976
04977   /* Disable Trigger DMA request */
04978   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04979
04980   htim->State = HAL_TIM_STATE_READY;
04981
04982   __HAL_UNLOCK(htim);
04983
04984   return HAL_OK;
04985 }
04986
04987 /**
04988   * @brief  Read the captured value from Capture Compare unit
04989   * @param  htim TIM handle.
04990   * @param  Channel TIM Channels to be enabled
04991   *          This parameter can be one of the following values:
04992   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04993   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04994   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04995   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04996   * @retval Captured value
04997   */
04998 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04999 {
05000   uint32_t tmpreg = 0U;
05001
05002   switch (Channel)
05003   {
05004     case TIM_CHANNEL_1:
05005     {
05006       /* Check the parameters */
05007       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05008
05009       /* Return the capture 1 value */
05010       tmpreg =  htim->Instance->CCR1;
05011
05012       break;
05013     }
05014     case TIM_CHANNEL_2:
05015     {
05016       /* Check the parameters */
05017       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05018
05019       /* Return the capture 2 value */
05020       tmpreg =   htim->Instance->CCR2;
05021
05022       break;
05023     }
05024
05025     case TIM_CHANNEL_3:
05026     {
05027       /* Check the parameters */
05028       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
05029
05030       /* Return the capture 3 value */
05031       tmpreg =   htim->Instance->CCR3;
05032
05033       break;
05034     }
05035
05036     case TIM_CHANNEL_4:
05037     {
05038       /* Check the parameters */
05039       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
05040
05041       /* Return the capture 4 value */
05042       tmpreg =   htim->Instance->CCR4;
05043
05044       break;
05045     }
05046
05047     default:
05048       break;
05049   }
05050
05051   return tmpreg;
05052 }
05053
05054 /**
05055   * @}
05056   */
05057
05058 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
05059   *  @brief    TIM Callbacks functions
05060   *
05061 @verbatim
05062   ==============================================================================
05063                         ##### TIM Callbacks functions #####
05064   ==============================================================================
05065  [..]
05066    This section provides TIM callback functions:
05067    (+) TIM Period elapsed callback
05068    (+) TIM Output Compare callback
05069    (+) TIM Input capture callback
05070    (+) TIM Trigger callback
05071    (+) TIM Error callback
05072
05073 @endverbatim
05074   * @{
05075   */
05076
05077 /**
05078   * @brief  Period elapsed callback in non-blocking mode
05079   * @param  htim TIM handle
05080   * @retval None
05081   */
05082 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
05083 {
05084   /* Prevent unused argument(s) compilation warning */
05085   UNUSED(htim);
05086
05087   /* NOTE : This function should not be modified, when the callback is needed,
05088             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
05089    */
05090 }
05091
05092 /**
05093   * @brief  Period elapsed half complete callback in non-blocking mode
05094   * @param  htim TIM handle
05095   * @retval None
05096   */
05097 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
05098 {
05099   /* Prevent unused argument(s) compilation warning */
05100   UNUSED(htim);
05101
05102   /* NOTE : This function should not be modified, when the callback is needed,
05103             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
05104    */
05105 }
05106
05107 /**
05108   * @brief  Output Compare callback in non-blocking mode
05109   * @param  htim TIM OC handle
05110   * @retval None
05111   */
05112 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
05113 {
05114   /* Prevent unused argument(s) compilation warning */
05115   UNUSED(htim);
05116
05117   /* NOTE : This function should not be modified, when the callback is needed,
05118             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
05119    */
05120 }
05121
05122 /**
05123   * @brief  Input Capture callback in non-blocking mode
05124   * @param  htim TIM IC handle
05125   * @retval None
05126   */
05127 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
05128 {
05129   /* Prevent unused argument(s) compilation warning */
05130   UNUSED(htim);
05131
05132   /* NOTE : This function should not be modified, when the callback is needed,
05133             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
05134    */
05135 }
05136
05137 /**
05138   * @brief  Input Capture half complete callback in non-blocking mode
05139   * @param  htim TIM IC handle
05140   * @retval None
05141   */
05142 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
05143 {
05144   /* Prevent unused argument(s) compilation warning */
05145   UNUSED(htim);
05146
05147   /* NOTE : This function should not be modified, when the callback is needed,
05148             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
05149    */
05150 }
05151
05152 /**
05153   * @brief  PWM Pulse finished callback in non-blocking mode
05154   * @param  htim TIM handle
05155   * @retval None
05156   */
05157 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
05158 {
05159   /* Prevent unused argument(s) compilation warning */
05160   UNUSED(htim);
05161
05162   /* NOTE : This function should not be modified, when the callback is needed,
05163             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
05164    */
05165 }
05166
05167 /**
05168   * @brief  PWM Pulse finished half complete callback in non-blocking mode
05169   * @param  htim TIM handle
05170   * @retval None
05171   */
05172 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
05173 {
05174   /* Prevent unused argument(s) compilation warning */
05175   UNUSED(htim);
05176
05177   /* NOTE : This function should not be modified, when the callback is needed,
05178             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
05179    */
05180 }
05181
05182 /**
05183   * @brief  Hall Trigger detection callback in non-blocking mode
05184   * @param  htim TIM handle
05185   * @retval None
05186   */
05187 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
05188 {
05189   /* Prevent unused argument(s) compilation warning */
05190   UNUSED(htim);
05191
05192   /* NOTE : This function should not be modified, when the callback is needed,
05193             the HAL_TIM_TriggerCallback could be implemented in the user file
05194    */
05195 }
05196
05197 /**
05198   * @brief  Hall Trigger detection half complete callback in non-blocking mode
05199   * @param  htim TIM handle
05200   * @retval None
05201   */
05202 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
05203 {
05204   /* Prevent unused argument(s) compilation warning */
05205   UNUSED(htim);
05206
05207   /* NOTE : This function should not be modified, when the callback is needed,
05208             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
05209    */
05210 }
05211
05212 /**
05213   * @brief  Timer error callback in non-blocking mode
05214   * @param  htim TIM handle
05215   * @retval None
05216   */
05217 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
05218 {
05219   /* Prevent unused argument(s) compilation warning */
05220   UNUSED(htim);
05221
05222   /* NOTE : This function should not be modified, when the callback is needed,
05223             the HAL_TIM_ErrorCallback could be implemented in the user file
05224    */
05225 }
05226
05227 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05228 /**
05229   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
05230   * @param htim tim handle
05231   * @param CallbackID ID of the callback to be registered
05232   *        This parameter can be one of the following values:
05233   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
05234   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
05235   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
05236   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
05237   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
05238   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
05239   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
05240   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
05241   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
05242   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
05243   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
05244   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
05245   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
05246   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
05247   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
05248   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
05249   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
05250   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
05251   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
05252   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
05253   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
05254   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
05255   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
05256   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
05257   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
05258   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
05259   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
05260   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
05261   *          @param pCallback pointer to the callback function
05262   *          @retval status
05263   */
05264 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
05265                                            pTIM_CallbackTypeDef pCallback)
05266 {
05267   HAL_StatusTypeDef status = HAL_OK;
05268
05269   if (pCallback == NULL)
05270   {
05271     return HAL_ERROR;
05272   }
05273   /* Process locked */
05274   __HAL_LOCK(htim);
05275
05276   if (htim->State == HAL_TIM_STATE_READY)
05277   {
05278     switch (CallbackID)
05279     {
05280       case HAL_TIM_BASE_MSPINIT_CB_ID :
05281         htim->Base_MspInitCallback                 = pCallback;
05282         break;
05283
05284       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05285         htim->Base_MspDeInitCallback               = pCallback;
05286         break;
05287
05288       case HAL_TIM_IC_MSPINIT_CB_ID :
05289         htim->IC_MspInitCallback                   = pCallback;
05290         break;
05291
05292       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05293         htim->IC_MspDeInitCallback                 = pCallback;
05294         break;
05295
05296       case HAL_TIM_OC_MSPINIT_CB_ID :
05297         htim->OC_MspInitCallback                   = pCallback;
05298         break;
05299
05300       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05301         htim->OC_MspDeInitCallback                 = pCallback;
05302         break;
05303
05304       case HAL_TIM_PWM_MSPINIT_CB_ID :
05305         htim->PWM_MspInitCallback                  = pCallback;
05306         break;
05307
05308       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05309         htim->PWM_MspDeInitCallback                = pCallback;
05310         break;
05311
05312       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05313         htim->OnePulse_MspInitCallback             = pCallback;
05314         break;
05315
05316       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05317         htim->OnePulse_MspDeInitCallback           = pCallback;
05318         break;
05319
05320       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05321         htim->Encoder_MspInitCallback              = pCallback;
05322         break;
05323
05324       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05325         htim->Encoder_MspDeInitCallback            = pCallback;
05326         break;
05327
05328       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05329         htim->HallSensor_MspInitCallback           = pCallback;
05330         break;
05331
05332       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05333         htim->HallSensor_MspDeInitCallback         = pCallback;
05334         break;
05335
05336       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
05337         htim->PeriodElapsedCallback                = pCallback;
05338         break;
05339
05340       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
05341         htim->PeriodElapsedHalfCpltCallback        = pCallback;
05342         break;
05343
05344       case HAL_TIM_TRIGGER_CB_ID :
05345         htim->TriggerCallback                      = pCallback;
05346         break;
05347
05348       case HAL_TIM_TRIGGER_HALF_CB_ID :
05349         htim->TriggerHalfCpltCallback              = pCallback;
05350         break;
05351
05352       case HAL_TIM_IC_CAPTURE_CB_ID :
05353         htim->IC_CaptureCallback                   = pCallback;
05354         break;
05355
05356       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
05357         htim->IC_CaptureHalfCpltCallback           = pCallback;
05358         break;
05359
05360       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
05361         htim->OC_DelayElapsedCallback              = pCallback;
05362         break;
05363
05364       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
05365         htim->PWM_PulseFinishedCallback            = pCallback;
05366         break;
05367
05368       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
05369         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
05370         break;
05371
05372       case HAL_TIM_ERROR_CB_ID :
05373         htim->ErrorCallback                        = pCallback;
05374         break;
05375
05376       case HAL_TIM_COMMUTATION_CB_ID :
05377         htim->CommutationCallback                  = pCallback;
05378         break;
05379
05380       case HAL_TIM_COMMUTATION_HALF_CB_ID :
05381         htim->CommutationHalfCpltCallback          = pCallback;
05382         break;
05383
05384       case HAL_TIM_BREAK_CB_ID :
05385         htim->BreakCallback                        = pCallback;
05386         break;
05387
05388       case HAL_TIM_BREAK2_CB_ID :
05389         htim->Break2Callback                       = pCallback;
05390         break;
05391
05392       default :
05393         /* Return error status */
05394         status =  HAL_ERROR;
05395         break;
05396     }
05397   }
05398   else if (htim->State == HAL_TIM_STATE_RESET)
05399   {
05400     switch (CallbackID)
05401     {
05402       case HAL_TIM_BASE_MSPINIT_CB_ID :
05403         htim->Base_MspInitCallback         = pCallback;
05404         break;
05405
05406       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05407         htim->Base_MspDeInitCallback       = pCallback;
05408         break;
05409
05410       case HAL_TIM_IC_MSPINIT_CB_ID :
05411         htim->IC_MspInitCallback           = pCallback;
05412         break;
05413
05414       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05415         htim->IC_MspDeInitCallback         = pCallback;
05416         break;
05417
05418       case HAL_TIM_OC_MSPINIT_CB_ID :
05419         htim->OC_MspInitCallback           = pCallback;
05420         break;
05421
05422       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05423         htim->OC_MspDeInitCallback         = pCallback;
05424         break;
05425
05426       case HAL_TIM_PWM_MSPINIT_CB_ID :
05427         htim->PWM_MspInitCallback          = pCallback;
05428         break;
05429
05430       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05431         htim->PWM_MspDeInitCallback        = pCallback;
05432         break;
05433
05434       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05435         htim->OnePulse_MspInitCallback     = pCallback;
05436         break;
05437
05438       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05439         htim->OnePulse_MspDeInitCallback   = pCallback;
05440         break;
05441
05442       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05443         htim->Encoder_MspInitCallback      = pCallback;
05444         break;
05445
05446       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05447         htim->Encoder_MspDeInitCallback    = pCallback;
05448         break;
05449
05450       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05451         htim->HallSensor_MspInitCallback   = pCallback;
05452         break;
05453
05454       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05455         htim->HallSensor_MspDeInitCallback = pCallback;
05456         break;
05457
05458       default :
05459         /* Return error status */
05460         status =  HAL_ERROR;
05461         break;
05462     }
05463   }
05464   else
05465   {
05466     /* Return error status */
05467     status =  HAL_ERROR;
05468   }
05469
05470   /* Release Lock */
05471   __HAL_UNLOCK(htim);
05472
05473   return status;
05474 }
05475
05476 /**
05477   * @brief  Unregister a TIM callback
05478   *         TIM callback is redirected to the weak predefined callback
05479   * @param htim tim handle
05480   * @param CallbackID ID of the callback to be unregistered
05481   *        This parameter can be one of the following values:
05482   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
05483   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
05484   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
05485   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
05486   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
05487   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
05488   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
05489   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
05490   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
05491   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
05492   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
05493   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
05494   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
05495   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
05496   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
05497   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
05498   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
05499   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
05500   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
05501   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
05502   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
05503   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
05504   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
05505   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
05506   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
05507   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
05508   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
05509   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
05510   *          @retval status
05511   */
05512 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
05513 {
05514   HAL_StatusTypeDef status = HAL_OK;
05515
05516   /* Process locked */
05517   __HAL_LOCK(htim);
05518
05519   if (htim->State == HAL_TIM_STATE_READY)
05520   {
05521     switch (CallbackID)
05522     {
05523       case HAL_TIM_BASE_MSPINIT_CB_ID :
05524         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
05525         break;
05526
05527       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05528         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
05529         break;
05530
05531       case HAL_TIM_IC_MSPINIT_CB_ID :
05532         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
05533         break;
05534
05535       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05536         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
05537         break;
05538
05539       case HAL_TIM_OC_MSPINIT_CB_ID :
05540         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
05541         break;
05542
05543       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05544         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
05545         break;
05546
05547       case HAL_TIM_PWM_MSPINIT_CB_ID :
05548         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
05549         break;
05550
05551       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05552         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
05553         break;
05554
05555       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05556         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
05557         break;
05558
05559       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05560         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
05561         break;
05562
05563       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05564         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
05565         break;
05566
05567       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05568         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
05569         break;
05570
05571       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05572         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
05573         break;
05574
05575       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05576         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
05577         break;
05578
05579       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
05580         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
05581         break;
05582
05583       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
05584         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
05585         break;
05586
05587       case HAL_TIM_TRIGGER_CB_ID :
05588         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
05589         break;
05590
05591       case HAL_TIM_TRIGGER_HALF_CB_ID :
05592         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
05593         break;
05594
05595       case HAL_TIM_IC_CAPTURE_CB_ID :
05596         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
05597         break;
05598
05599       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
05600         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
05601         break;
05602
05603       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
05604         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
05605         break;
05606
05607       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
05608         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
05609         break;
05610
05611       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
05612         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
05613         break;
05614
05615       case HAL_TIM_ERROR_CB_ID :
05616         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
05617         break;
05618
05619       case HAL_TIM_COMMUTATION_CB_ID :
05620         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
05621         break;
05622
05623       case HAL_TIM_COMMUTATION_HALF_CB_ID :
05624         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
05625         break;
05626
05627       case HAL_TIM_BREAK_CB_ID :
05628         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
05629         break;
05630
05631       case HAL_TIM_BREAK2_CB_ID :
05632         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
05633         break;
05634
05635       default :
05636         /* Return error status */
05637         status =  HAL_ERROR;
05638         break;
05639     }
05640   }
05641   else if (htim->State == HAL_TIM_STATE_RESET)
05642   {
05643     switch (CallbackID)
05644     {
05645       case HAL_TIM_BASE_MSPINIT_CB_ID :
05646         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
05647         break;
05648
05649       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05650         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
05651         break;
05652
05653       case HAL_TIM_IC_MSPINIT_CB_ID :
05654         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
05655         break;
05656
05657       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05658         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
05659         break;
05660
05661       case HAL_TIM_OC_MSPINIT_CB_ID :
05662         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
05663         break;
05664
05665       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05666         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
05667         break;
05668
05669       case HAL_TIM_PWM_MSPINIT_CB_ID :
05670         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
05671         break;
05672
05673       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05674         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
05675         break;
05676
05677       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05678         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
05679         break;
05680
05681       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05682         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
05683         break;
05684
05685       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05686         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
05687         break;
05688
05689       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05690         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
05691         break;
05692
05693       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05694         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
05695         break;
05696
05697       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05698         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
05699         break;
05700
05701       default :
05702         /* Return error status */
05703         status =  HAL_ERROR;
05704         break;
05705     }
05706   }
05707   else
05708   {
05709     /* Return error status */
05710     status =  HAL_ERROR;
05711   }
05712
05713   /* Release Lock */
05714   __HAL_UNLOCK(htim);
05715
05716   return status;
05717 }
05718 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05719
05720 /**
05721   * @}
05722   */
05723
05724 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
05725   *  @brief   TIM Peripheral State functions
05726   *
05727 @verbatim
05728   ==============================================================================
05729                         ##### Peripheral State functions #####
05730   ==============================================================================
05731     [..]
05732     This subsection permits to get in run-time the status of the peripheral
05733     and the data flow.
05734
05735 @endverbatim
05736   * @{
05737   */
05738
05739 /**
05740   * @brief  Return the TIM Base handle state.
05741   * @param  htim TIM Base handle
05742   * @retval HAL state
05743   */
05744 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
05745 {
05746   return htim->State;
05747 }
05748
05749 /**
05750   * @brief  Return the TIM OC handle state.
05751   * @param  htim TIM Output Compare handle
05752   * @retval HAL state
05753   */
05754 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
05755 {
05756   return htim->State;
05757 }
05758
05759 /**
05760   * @brief  Return the TIM PWM handle state.
05761   * @param  htim TIM handle
05762   * @retval HAL state
05763   */
05764 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
05765 {
05766   return htim->State;
05767 }
05768
05769 /**
05770   * @brief  Return the TIM Input Capture handle state.
05771   * @param  htim TIM IC handle
05772   * @retval HAL state
05773   */
05774 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
05775 {
05776   return htim->State;
05777 }
05778
05779 /**
05780   * @brief  Return the TIM One Pulse Mode handle state.
05781   * @param  htim TIM OPM handle
05782   * @retval HAL state
05783   */
05784 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
05785 {
05786   return htim->State;
05787 }
05788
05789 /**
05790   * @brief  Return the TIM Encoder Mode handle state.
05791   * @param  htim TIM Encoder Interface handle
05792   * @retval HAL state
05793   */
05794 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
05795 {
05796   return htim->State;
05797 }
05798
05799 /**
05800   * @}
05801   */
05802
05803 /**
05804   * @}
05805   */
05806
05807 /** @defgroup TIM_Private_Functions TIM Private Functions
05808   * @{
05809   */
05810
05811 /**
05812   * @brief  TIM DMA error callback
05813   * @param  hdma pointer to DMA handle.
05814   * @retval None
05815   */
05816 void TIM_DMAError(DMA_HandleTypeDef *hdma)
05817 {
05818   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05819
05820   htim->State = HAL_TIM_STATE_READY;
05821
05822 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05823   htim->ErrorCallback(htim);
05824 #else
05825   HAL_TIM_ErrorCallback(htim);
05826 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05827 }
05828
05829 /**
05830   * @brief  TIM DMA Delay Pulse complete callback.
05831   * @param  hdma pointer to DMA handle.
05832   * @retval None
05833   */
05834 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
05835 {
05836   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05837
05838   htim->State = HAL_TIM_STATE_READY;
05839
05840   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05841   {
05842     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05843   }
05844   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05845   {
05846     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05847   }
05848   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05849   {
05850     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05851   }
05852   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05853   {
05854     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05855   }
05856   else
05857   {
05858     /* nothing to do */
05859   }
05860
05861 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05862   htim->PWM_PulseFinishedCallback(htim);
05863 #else
05864   HAL_TIM_PWM_PulseFinishedCallback(htim);
05865 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05866
05867   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05868 }
05869
05870 /**
05871   * @brief  TIM DMA Delay Pulse half complete callback.
05872   * @param  hdma pointer to DMA handle.
05873   * @retval None
05874   */
05875 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
05876 {
05877   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05878
05879   htim->State = HAL_TIM_STATE_READY;
05880
05881   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05882   {
05883     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05884   }
05885   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05886   {
05887     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05888   }
05889   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05890   {
05891     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05892   }
05893   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05894   {
05895     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05896   }
05897   else
05898   {
05899     /* nothing to do */
05900   }
05901
05902 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05903   htim->PWM_PulseFinishedHalfCpltCallback(htim);
05904 #else
05905   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
05906 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05907
05908   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05909 }
05910
05911 /**
05912   * @brief  TIM DMA Capture complete callback.
05913   * @param  hdma pointer to DMA handle.
05914   * @retval None
05915   */
05916 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
05917 {
05918   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05919
05920   htim->State = HAL_TIM_STATE_READY;
05921
05922   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05923   {
05924     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05925   }
05926   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05927   {
05928     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05929   }
05930   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05931   {
05932     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05933   }
05934   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05935   {
05936     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05937   }
05938   else
05939   {
05940     /* nothing to do */
05941   }
05942
05943 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05944   htim->IC_CaptureCallback(htim);
05945 #else
05946   HAL_TIM_IC_CaptureCallback(htim);
05947 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05948
05949   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05950 }
05951
05952 /**
05953   * @brief  TIM DMA Capture half complete callback.
05954   * @param  hdma pointer to DMA handle.
05955   * @retval None
05956   */
05957 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
05958 {
05959   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05960
05961   htim->State = HAL_TIM_STATE_READY;
05962
05963   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05964   {
05965     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05966   }
05967   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05968   {
05969     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05970   }
05971   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05972   {
05973     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05974   }
05975   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05976   {
05977     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05978   }
05979   else
05980   {
05981     /* nothing to do */
05982   }
05983
05984 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05985   htim->IC_CaptureHalfCpltCallback(htim);
05986 #else
05987   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
05988 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05989
05990   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05991 }
05992
05993 /**
05994   * @brief  TIM DMA Period Elapse complete callback.
05995   * @param  hdma pointer to DMA handle.
05996   * @retval None
05997   */
05998 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
05999 {
06000   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06001
06002   htim->State = HAL_TIM_STATE_READY;
06003
06004 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06005   htim->PeriodElapsedCallback(htim);
06006 #else
06007   HAL_TIM_PeriodElapsedCallback(htim);
06008 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06009 }
06010
06011 /**
06012   * @brief  TIM DMA Period Elapse half complete callback.
06013   * @param  hdma pointer to DMA handle.
06014   * @retval None
06015   */
06016 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
06017 {
06018   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06019
06020   htim->State = HAL_TIM_STATE_READY;
06021
06022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06023   htim->PeriodElapsedHalfCpltCallback(htim);
06024 #else
06025   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
06026 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06027 }
06028
06029 /**
06030   * @brief  TIM DMA Trigger callback.
06031   * @param  hdma pointer to DMA handle.
06032   * @retval None
06033   */
06034 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
06035 {
06036   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06037
06038   htim->State = HAL_TIM_STATE_READY;
06039
06040 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06041   htim->TriggerCallback(htim);
06042 #else
06043   HAL_TIM_TriggerCallback(htim);
06044 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06045 }
06046
06047 /**
06048   * @brief  TIM DMA Trigger half complete callback.
06049   * @param  hdma pointer to DMA handle.
06050   * @retval None
06051   */
06052 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
06053 {
06054   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06055
06056   htim->State = HAL_TIM_STATE_READY;
06057
06058 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06059   htim->TriggerHalfCpltCallback(htim);
06060 #else
06061   HAL_TIM_TriggerHalfCpltCallback(htim);
06062 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06063 }
06064
06065 /**
06066   * @brief  Time Base configuration
06067   * @param  TIMx TIM peripheral
06068   * @param  Structure TIM Base configuration structure
06069   * @retval None
06070   */
06071 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
06072 {
06073   uint32_t tmpcr1;
06074   tmpcr1 = TIMx->CR1;
06075
06076   /* Set TIM Time Base Unit parameters ---------------------------------------*/
06077   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
06078   {
06079     /* Select the Counter Mode */
06080     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
06081     tmpcr1 |= Structure->CounterMode;
06082   }
06083
06084   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
06085   {
06086     /* Set the clock division */
06087     tmpcr1 &= ~TIM_CR1_CKD;
06088     tmpcr1 |= (uint32_t)Structure->ClockDivision;
06089   }
06090
06091   /* Set the auto-reload preload */
06092   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
06093
06094   TIMx->CR1 = tmpcr1;
06095
06096   /* Set the Autoreload value */
06097   TIMx->ARR = (uint32_t)Structure->Period ;
06098
06099   /* Set the Prescaler value */
06100   TIMx->PSC = Structure->Prescaler;
06101
06102   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
06103   {
06104     /* Set the Repetition Counter value */
06105     TIMx->RCR = Structure->RepetitionCounter;
06106   }
06107
06108   /* Generate an update event to reload the Prescaler
06109      and the repetition counter (only for advanced timer) value immediately */
06110   TIMx->EGR = TIM_EGR_UG;
06111 }
06112
06113 /**
06114   * @brief  Timer Output Compare 1 configuration
06115   * @param  TIMx to select the TIM peripheral
06116   * @param  OC_Config The ouput configuration structure
06117   * @retval None
06118   */
06119 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06120 {
06121   uint32_t tmpccmrx;
06122   uint32_t tmpccer;
06123   uint32_t tmpcr2;
06124
06125   /* Disable the Channel 1: Reset the CC1E Bit */
06126   TIMx->CCER &= ~TIM_CCER_CC1E;
06127
06128   /* Get the TIMx CCER register value */
06129   tmpccer = TIMx->CCER;
06130   /* Get the TIMx CR2 register value */
06131   tmpcr2 =  TIMx->CR2;
06132
06133   /* Get the TIMx CCMR1 register value */
06134   tmpccmrx = TIMx->CCMR1;
06135
06136   /* Reset the Output Compare Mode Bits */
06137   tmpccmrx &= ~TIM_CCMR1_OC1M;
06138   tmpccmrx &= ~TIM_CCMR1_CC1S;
06139   /* Select the Output Compare Mode */
06140   tmpccmrx |= OC_Config->OCMode;
06141
06142   /* Reset the Output Polarity level */
06143   tmpccer &= ~TIM_CCER_CC1P;
06144   /* Set the Output Compare Polarity */
06145   tmpccer |= OC_Config->OCPolarity;
06146
06147   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
06148   {
06149     /* Check parameters */
06150     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06151
06152     /* Reset the Output N Polarity level */
06153     tmpccer &= ~TIM_CCER_CC1NP;
06154     /* Set the Output N Polarity */
06155     tmpccer |= OC_Config->OCNPolarity;
06156     /* Reset the Output N State */
06157     tmpccer &= ~TIM_CCER_CC1NE;
06158   }
06159
06160   if (IS_TIM_BREAK_INSTANCE(TIMx))
06161   {
06162     /* Check parameters */
06163     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06164     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06165
06166     /* Reset the Output Compare and Output Compare N IDLE State */
06167     tmpcr2 &= ~TIM_CR2_OIS1;
06168     tmpcr2 &= ~TIM_CR2_OIS1N;
06169     /* Set the Output Idle state */
06170     tmpcr2 |= OC_Config->OCIdleState;
06171     /* Set the Output N Idle state */
06172     tmpcr2 |= OC_Config->OCNIdleState;
06173   }
06174
06175   /* Write to TIMx CR2 */
06176   TIMx->CR2 = tmpcr2;
06177
06178   /* Write to TIMx CCMR1 */
06179   TIMx->CCMR1 = tmpccmrx;
06180
06181   /* Set the Capture Compare Register value */
06182   TIMx->CCR1 = OC_Config->Pulse;
06183
06184   /* Write to TIMx CCER */
06185   TIMx->CCER = tmpccer;
06186 }
06187
06188 /**
06189   * @brief  Timer Output Compare 2 configuration
06190   * @param  TIMx to select the TIM peripheral
06191   * @param  OC_Config The ouput configuration structure
06192   * @retval None
06193   */
06194 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06195 {
06196   uint32_t tmpccmrx;
06197   uint32_t tmpccer;
06198   uint32_t tmpcr2;
06199
06200   /* Disable the Channel 2: Reset the CC2E Bit */
06201   TIMx->CCER &= ~TIM_CCER_CC2E;
06202
06203   /* Get the TIMx CCER register value */
06204   tmpccer = TIMx->CCER;
06205   /* Get the TIMx CR2 register value */
06206   tmpcr2 =  TIMx->CR2;
06207
06208   /* Get the TIMx CCMR1 register value */
06209   tmpccmrx = TIMx->CCMR1;
06210
06211   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06212   tmpccmrx &= ~TIM_CCMR1_OC2M;
06213   tmpccmrx &= ~TIM_CCMR1_CC2S;
06214
06215   /* Select the Output Compare Mode */
06216   tmpccmrx |= (OC_Config->OCMode << 8U);
06217
06218   /* Reset the Output Polarity level */
06219   tmpccer &= ~TIM_CCER_CC2P;
06220   /* Set the Output Compare Polarity */
06221   tmpccer |= (OC_Config->OCPolarity << 4U);
06222
06223   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
06224   {
06225     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06226
06227     /* Reset the Output N Polarity level */
06228     tmpccer &= ~TIM_CCER_CC2NP;
06229     /* Set the Output N Polarity */
06230     tmpccer |= (OC_Config->OCNPolarity << 4U);
06231     /* Reset the Output N State */
06232     tmpccer &= ~TIM_CCER_CC2NE;
06233
06234   }
06235
06236   if (IS_TIM_BREAK_INSTANCE(TIMx))
06237   {
06238     /* Check parameters */
06239     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06240     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06241
06242     /* Reset the Output Compare and Output Compare N IDLE State */
06243     tmpcr2 &= ~TIM_CR2_OIS2;
06244     tmpcr2 &= ~TIM_CR2_OIS2N;
06245     /* Set the Output Idle state */
06246     tmpcr2 |= (OC_Config->OCIdleState << 2U);
06247     /* Set the Output N Idle state */
06248     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
06249   }
06250
06251   /* Write to TIMx CR2 */
06252   TIMx->CR2 = tmpcr2;
06253
06254   /* Write to TIMx CCMR1 */
06255   TIMx->CCMR1 = tmpccmrx;
06256
06257   /* Set the Capture Compare Register value */
06258   TIMx->CCR2 = OC_Config->Pulse;
06259
06260   /* Write to TIMx CCER */
06261   TIMx->CCER = tmpccer;
06262 }
06263
06264 /**
06265   * @brief  Timer Output Compare 3 configuration
06266   * @param  TIMx to select the TIM peripheral
06267   * @param  OC_Config The ouput configuration structure
06268   * @retval None
06269   */
06270 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06271 {
06272   uint32_t tmpccmrx;
06273   uint32_t tmpccer;
06274   uint32_t tmpcr2;
06275
06276   /* Disable the Channel 3: Reset the CC2E Bit */
06277   TIMx->CCER &= ~TIM_CCER_CC3E;
06278
06279   /* Get the TIMx CCER register value */
06280   tmpccer = TIMx->CCER;
06281   /* Get the TIMx CR2 register value */
06282   tmpcr2 =  TIMx->CR2;
06283
06284   /* Get the TIMx CCMR2 register value */
06285   tmpccmrx = TIMx->CCMR2;
06286
06287   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06288   tmpccmrx &= ~TIM_CCMR2_OC3M;
06289   tmpccmrx &= ~TIM_CCMR2_CC3S;
06290   /* Select the Output Compare Mode */
06291   tmpccmrx |= OC_Config->OCMode;
06292
06293   /* Reset the Output Polarity level */
06294   tmpccer &= ~TIM_CCER_CC3P;
06295   /* Set the Output Compare Polarity */
06296   tmpccer |= (OC_Config->OCPolarity << 8U);
06297
06298   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
06299   {
06300     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06301
06302     /* Reset the Output N Polarity level */
06303     tmpccer &= ~TIM_CCER_CC3NP;
06304     /* Set the Output N Polarity */
06305     tmpccer |= (OC_Config->OCNPolarity << 8U);
06306     /* Reset the Output N State */
06307     tmpccer &= ~TIM_CCER_CC3NE;
06308   }
06309
06310   if (IS_TIM_BREAK_INSTANCE(TIMx))
06311   {
06312     /* Check parameters */
06313     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06314     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06315
06316     /* Reset the Output Compare and Output Compare N IDLE State */
06317     tmpcr2 &= ~TIM_CR2_OIS3;
06318     tmpcr2 &= ~TIM_CR2_OIS3N;
06319     /* Set the Output Idle state */
06320     tmpcr2 |= (OC_Config->OCIdleState << 4U);
06321     /* Set the Output N Idle state */
06322     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
06323   }
06324
06325   /* Write to TIMx CR2 */
06326   TIMx->CR2 = tmpcr2;
06327
06328   /* Write to TIMx CCMR2 */
06329   TIMx->CCMR2 = tmpccmrx;
06330
06331   /* Set the Capture Compare Register value */
06332   TIMx->CCR3 = OC_Config->Pulse;
06333
06334   /* Write to TIMx CCER */
06335   TIMx->CCER = tmpccer;
06336 }
06337
06338 /**
06339   * @brief  Timer Output Compare 4 configuration
06340   * @param  TIMx to select the TIM peripheral
06341   * @param  OC_Config The ouput configuration structure
06342   * @retval None
06343   */
06344 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06345 {
06346   uint32_t tmpccmrx;
06347   uint32_t tmpccer;
06348   uint32_t tmpcr2;
06349
06350   /* Disable the Channel 4: Reset the CC4E Bit */
06351   TIMx->CCER &= ~TIM_CCER_CC4E;
06352
06353   /* Get the TIMx CCER register value */
06354   tmpccer = TIMx->CCER;
06355   /* Get the TIMx CR2 register value */
06356   tmpcr2 =  TIMx->CR2;
06357
06358   /* Get the TIMx CCMR2 register value */
06359   tmpccmrx = TIMx->CCMR2;
06360
06361   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06362   tmpccmrx &= ~TIM_CCMR2_OC4M;
06363   tmpccmrx &= ~TIM_CCMR2_CC4S;
06364
06365   /* Select the Output Compare Mode */
06366   tmpccmrx |= (OC_Config->OCMode << 8U);
06367
06368   /* Reset the Output Polarity level */
06369   tmpccer &= ~TIM_CCER_CC4P;
06370   /* Set the Output Compare Polarity */
06371   tmpccer |= (OC_Config->OCPolarity << 12U);
06372
06373   if (IS_TIM_BREAK_INSTANCE(TIMx))
06374   {
06375     /* Check parameters */
06376     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06377
06378     /* Reset the Output Compare IDLE State */
06379     tmpcr2 &= ~TIM_CR2_OIS4;
06380
06381     /* Set the Output Idle state */
06382     tmpcr2 |= (OC_Config->OCIdleState << 6U);
06383   }
06384
06385   /* Write to TIMx CR2 */
06386   TIMx->CR2 = tmpcr2;
06387
06388   /* Write to TIMx CCMR2 */
06389   TIMx->CCMR2 = tmpccmrx;
06390
06391   /* Set the Capture Compare Register value */
06392   TIMx->CCR4 = OC_Config->Pulse;
06393
06394   /* Write to TIMx CCER */
06395   TIMx->CCER = tmpccer;
06396 }
06397
06398 /**
06399   * @brief  Timer Output Compare 5 configuration
06400   * @param  TIMx to select the TIM peripheral
06401   * @param  OC_Config The ouput configuration structure
06402   * @retval None
06403   */
06404 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
06405                               TIM_OC_InitTypeDef *OC_Config)
06406 {
06407   uint32_t tmpccmrx;
06408   uint32_t tmpccer;
06409   uint32_t tmpcr2;
06410
06411   /* Disable the output: Reset the CCxE Bit */
06412   TIMx->CCER &= ~TIM_CCER_CC5E;
06413
06414   /* Get the TIMx CCER register value */
06415   tmpccer = TIMx->CCER;
06416   /* Get the TIMx CR2 register value */
06417   tmpcr2 =  TIMx->CR2;
06418   /* Get the TIMx CCMR1 register value */
06419   tmpccmrx = TIMx->CCMR3;
06420
06421   /* Reset the Output Compare Mode Bits */
06422   tmpccmrx &= ~(TIM_CCMR3_OC5M);
06423   /* Select the Output Compare Mode */
06424   tmpccmrx |= OC_Config->OCMode;
06425
06426   /* Reset the Output Polarity level */
06427   tmpccer &= ~TIM_CCER_CC5P;
06428   /* Set the Output Compare Polarity */
06429   tmpccer |= (OC_Config->OCPolarity << 16U);
06430
06431   if (IS_TIM_BREAK_INSTANCE(TIMx))
06432   {
06433     /* Reset the Output Compare IDLE State */
06434     tmpcr2 &= ~TIM_CR2_OIS5;
06435     /* Set the Output Idle state */
06436     tmpcr2 |= (OC_Config->OCIdleState << 8U);
06437   }
06438   /* Write to TIMx CR2 */
06439   TIMx->CR2 = tmpcr2;
06440
06441   /* Write to TIMx CCMR3 */
06442   TIMx->CCMR3 = tmpccmrx;
06443
06444   /* Set the Capture Compare Register value */
06445   TIMx->CCR5 = OC_Config->Pulse;
06446
06447   /* Write to TIMx CCER */
06448   TIMx->CCER = tmpccer;
06449 }
06450
06451 /**
06452   * @brief  Timer Output Compare 6 configuration
06453   * @param  TIMx to select the TIM peripheral
06454   * @param  OC_Config The ouput configuration structure
06455   * @retval None
06456   */
06457 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
06458                               TIM_OC_InitTypeDef *OC_Config)
06459 {
06460   uint32_t tmpccmrx;
06461   uint32_t tmpccer;
06462   uint32_t tmpcr2;
06463
06464   /* Disable the output: Reset the CCxE Bit */
06465   TIMx->CCER &= ~TIM_CCER_CC6E;
06466
06467   /* Get the TIMx CCER register value */
06468   tmpccer = TIMx->CCER;
06469   /* Get the TIMx CR2 register value */
06470   tmpcr2 =  TIMx->CR2;
06471   /* Get the TIMx CCMR1 register value */
06472   tmpccmrx = TIMx->CCMR3;
06473
06474   /* Reset the Output Compare Mode Bits */
06475   tmpccmrx &= ~(TIM_CCMR3_OC6M);
06476   /* Select the Output Compare Mode */
06477   tmpccmrx |= (OC_Config->OCMode << 8U);
06478
06479   /* Reset the Output Polarity level */
06480   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
06481   /* Set the Output Compare Polarity */
06482   tmpccer |= (OC_Config->OCPolarity << 20U);
06483
06484   if (IS_TIM_BREAK_INSTANCE(TIMx))
06485   {
06486     /* Reset the Output Compare IDLE State */
06487     tmpcr2 &= ~TIM_CR2_OIS6;
06488     /* Set the Output Idle state */
06489     tmpcr2 |= (OC_Config->OCIdleState << 10U);
06490   }
06491
06492   /* Write to TIMx CR2 */
06493   TIMx->CR2 = tmpcr2;
06494
06495   /* Write to TIMx CCMR3 */
06496   TIMx->CCMR3 = tmpccmrx;
06497
06498   /* Set the Capture Compare Register value */
06499   TIMx->CCR6 = OC_Config->Pulse;
06500
06501   /* Write to TIMx CCER */
06502   TIMx->CCER = tmpccer;
06503 }
06504
06505 /**
06506   * @brief  Slave Timer configuration function
06507   * @param  htim TIM handle
06508   * @param  sSlaveConfig Slave timer configuration
06509   * @retval None
06510   */
06511 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
06512                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
06513 {
06514   uint32_t tmpsmcr;
06515   uint32_t tmpccmr1;
06516   uint32_t tmpccer;
06517
06518   /* Get the TIMx SMCR register value */
06519   tmpsmcr = htim->Instance->SMCR;
06520
06521   /* Reset the Trigger Selection Bits */
06522   tmpsmcr &= ~TIM_SMCR_TS;
06523   /* Set the Input Trigger source */
06524   tmpsmcr |= sSlaveConfig->InputTrigger;
06525
06526   /* Reset the slave mode Bits */
06527   tmpsmcr &= ~TIM_SMCR_SMS;
06528   /* Set the slave mode */
06529   tmpsmcr |= sSlaveConfig->SlaveMode;
06530
06531   /* Write to TIMx SMCR */
06532   htim->Instance->SMCR = tmpsmcr;
06533
06534   /* Configure the trigger prescaler, filter, and polarity */
06535   switch (sSlaveConfig->InputTrigger)
06536   {
06537     case TIM_TS_ETRF:
06538     {
06539       /* Check the parameters */
06540       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
06541       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
06542       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06543       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06544       /* Configure the ETR Trigger source */
06545       TIM_ETR_SetConfig(htim->Instance,
06546                         sSlaveConfig->TriggerPrescaler,
06547                         sSlaveConfig->TriggerPolarity,
06548                         sSlaveConfig->TriggerFilter);
06549       break;
06550     }
06551
06552     case TIM_TS_TI1F_ED:
06553     {
06554       /* Check the parameters */
06555       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
06556       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06557
06558       if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
06559       {
06560         return HAL_ERROR;
06561       }
06562
06563       /* Disable the Channel 1: Reset the CC1E Bit */
06564       tmpccer = htim->Instance->CCER;
06565       htim->Instance->CCER &= ~TIM_CCER_CC1E;
06566       tmpccmr1 = htim->Instance->CCMR1;
06567
06568       /* Set the filter */
06569       tmpccmr1 &= ~TIM_CCMR1_IC1F;
06570       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
06571
06572       /* Write to TIMx CCMR1 and CCER registers */
06573       htim->Instance->CCMR1 = tmpccmr1;
06574       htim->Instance->CCER = tmpccer;
06575       break;
06576     }
06577
06578     case TIM_TS_TI1FP1:
06579     {
06580       /* Check the parameters */
06581       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
06582       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06583       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06584
06585       /* Configure TI1 Filter and Polarity */
06586       TIM_TI1_ConfigInputStage(htim->Instance,
06587                                sSlaveConfig->TriggerPolarity,
06588                                sSlaveConfig->TriggerFilter);
06589       break;
06590     }
06591
06592     case TIM_TS_TI2FP2:
06593     {
06594       /* Check the parameters */
06595       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
06596       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06597       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06598
06599       /* Configure TI2 Filter and Polarity */
06600       TIM_TI2_ConfigInputStage(htim->Instance,
06601                                sSlaveConfig->TriggerPolarity,
06602                                sSlaveConfig->TriggerFilter);
06603       break;
06604     }
06605
06606     case TIM_TS_ITR0:
06607     case TIM_TS_ITR1:
06608     case TIM_TS_ITR2:
06609     case TIM_TS_ITR3:
06610     case TIM_TS_ITR4:
06611     case TIM_TS_ITR5:
06612     case TIM_TS_ITR6:
06613     case TIM_TS_ITR7:
06614     case TIM_TS_ITR8:
06615     case TIM_TS_ITR9:
06616     case TIM_TS_ITR10:
06617     case TIM_TS_ITR11:
06618     case TIM_TS_ITR12:
06619     case TIM_TS_ITR13:
06620     {
06621       /* Check the parameter */
06622       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
06623       break;
06624     }
06625
06626     default:
06627       break;
06628   }
06629   return HAL_OK;
06630 }
06631
06632 /**
06633   * @brief  Configure the TI1 as Input.
06634   * @param  TIMx to select the TIM peripheral.
06635   * @param  TIM_ICPolarity The Input Polarity.
06636   *          This parameter can be one of the following values:
06637   *            @arg TIM_ICPOLARITY_RISING
06638   *            @arg TIM_ICPOLARITY_FALLING
06639   *            @arg TIM_ICPOLARITY_BOTHEDGE
06640   * @param  TIM_ICSelection specifies the input to be used.
06641   *          This parameter can be one of the following values:
06642   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
06643   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
06644   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
06645   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06646   *          This parameter must be a value between 0x00 and 0x0F.
06647   * @retval None
06648   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
06649   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
06650   *        protected against un-initialized filter and polarity values.
06651   */
06652 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06653                        uint32_t TIM_ICFilter)
06654 {
06655   uint32_t tmpccmr1;
06656   uint32_t tmpccer;
06657
06658   /* Disable the Channel 1: Reset the CC1E Bit */
06659   TIMx->CCER &= ~TIM_CCER_CC1E;
06660   tmpccmr1 = TIMx->CCMR1;
06661   tmpccer = TIMx->CCER;
06662
06663   /* Select the Input */
06664   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
06665   {
06666     tmpccmr1 &= ~TIM_CCMR1_CC1S;
06667     tmpccmr1 |= TIM_ICSelection;
06668   }
06669   else
06670   {
06671     tmpccmr1 |= TIM_CCMR1_CC1S_0;
06672   }
06673
06674   /* Set the filter */
06675   tmpccmr1 &= ~TIM_CCMR1_IC1F;
06676   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
06677
06678   /* Select the Polarity and set the CC1E Bit */
06679   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
06680   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
06681
06682   /* Write to TIMx CCMR1 and CCER registers */
06683   TIMx->CCMR1 = tmpccmr1;
06684   TIMx->CCER = tmpccer;
06685 }
06686
06687 /**
06688   * @brief  Configure the Polarity and Filter for TI1.
06689   * @param  TIMx to select the TIM peripheral.
06690   * @param  TIM_ICPolarity The Input Polarity.
06691   *          This parameter can be one of the following values:
06692   *            @arg TIM_ICPOLARITY_RISING
06693   *            @arg TIM_ICPOLARITY_FALLING
06694   *            @arg TIM_ICPOLARITY_BOTHEDGE
06695   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06696   *          This parameter must be a value between 0x00 and 0x0F.
06697   * @retval None
06698   */
06699 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
06700 {
06701   uint32_t tmpccmr1;
06702   uint32_t tmpccer;
06703
06704   /* Disable the Channel 1: Reset the CC1E Bit */
06705   tmpccer = TIMx->CCER;
06706   TIMx->CCER &= ~TIM_CCER_CC1E;
06707   tmpccmr1 = TIMx->CCMR1;
06708
06709   /* Set the filter */
06710   tmpccmr1 &= ~TIM_CCMR1_IC1F;
06711   tmpccmr1 |= (TIM_ICFilter << 4U);
06712
06713   /* Select the Polarity and set the CC1E Bit */
06714   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
06715   tmpccer |= TIM_ICPolarity;
06716
06717   /* Write to TIMx CCMR1 and CCER registers */
06718   TIMx->CCMR1 = tmpccmr1;
06719   TIMx->CCER = tmpccer;
06720 }
06721
06722 /**
06723   * @brief  Configure the TI2 as Input.
06724   * @param  TIMx to select the TIM peripheral
06725   * @param  TIM_ICPolarity The Input Polarity.
06726   *          This parameter can be one of the following values:
06727   *            @arg TIM_ICPOLARITY_RISING
06728   *            @arg TIM_ICPOLARITY_FALLING
06729   *            @arg TIM_ICPOLARITY_BOTHEDGE
06730   * @param  TIM_ICSelection specifies the input to be used.
06731   *          This parameter can be one of the following values:
06732   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
06733   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
06734   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
06735   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06736   *          This parameter must be a value between 0x00 and 0x0F.
06737   * @retval None
06738   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
06739   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
06740   *        protected against un-initialized filter and polarity values.
06741   */
06742 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06743                               uint32_t TIM_ICFilter)
06744 {
06745   uint32_t tmpccmr1;
06746   uint32_t tmpccer;
06747
06748   /* Disable the Channel 2: Reset the CC2E Bit */
06749   TIMx->CCER &= ~TIM_CCER_CC2E;
06750   tmpccmr1 = TIMx->CCMR1;
06751   tmpccer = TIMx->CCER;
06752
06753   /* Select the Input */
06754   tmpccmr1 &= ~TIM_CCMR1_CC2S;
06755   tmpccmr1 |= (TIM_ICSelection << 8U);
06756
06757   /* Set the filter */
06758   tmpccmr1 &= ~TIM_CCMR1_IC2F;
06759   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
06760
06761   /* Select the Polarity and set the CC2E Bit */
06762   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
06763   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
06764
06765   /* Write to TIMx CCMR1 and CCER registers */
06766   TIMx->CCMR1 = tmpccmr1 ;
06767   TIMx->CCER = tmpccer;
06768 }
06769
06770 /**
06771   * @brief  Configure the Polarity and Filter for TI2.
06772   * @param  TIMx to select the TIM peripheral.
06773   * @param  TIM_ICPolarity The Input Polarity.
06774   *          This parameter can be one of the following values:
06775   *            @arg TIM_ICPOLARITY_RISING
06776   *            @arg TIM_ICPOLARITY_FALLING
06777   *            @arg TIM_ICPOLARITY_BOTHEDGE
06778   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06779   *          This parameter must be a value between 0x00 and 0x0F.
06780   * @retval None
06781   */
06782 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
06783 {
06784   uint32_t tmpccmr1;
06785   uint32_t tmpccer;
06786
06787   /* Disable the Channel 2: Reset the CC2E Bit */
06788   TIMx->CCER &= ~TIM_CCER_CC2E;
06789   tmpccmr1 = TIMx->CCMR1;
06790   tmpccer = TIMx->CCER;
06791
06792   /* Set the filter */
06793   tmpccmr1 &= ~TIM_CCMR1_IC2F;
06794   tmpccmr1 |= (TIM_ICFilter << 12U);
06795
06796   /* Select the Polarity and set the CC2E Bit */
06797   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
06798   tmpccer |= (TIM_ICPolarity << 4U);
06799
06800   /* Write to TIMx CCMR1 and CCER registers */
06801   TIMx->CCMR1 = tmpccmr1 ;
06802   TIMx->CCER = tmpccer;
06803 }
06804
06805 /**
06806   * @brief  Configure the TI3 as Input.
06807   * @param  TIMx to select the TIM peripheral
06808   * @param  TIM_ICPolarity The Input Polarity.
06809   *          This parameter can be one of the following values:
06810   *            @arg TIM_ICPOLARITY_RISING
06811   *            @arg TIM_ICPOLARITY_FALLING
06812   *            @arg TIM_ICPOLARITY_BOTHEDGE
06813   * @param  TIM_ICSelection specifies the input to be used.
06814   *          This parameter can be one of the following values:
06815   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
06816   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
06817   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
06818   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06819   *          This parameter must be a value between 0x00 and 0x0F.
06820   * @retval None
06821   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
06822   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
06823   *        protected against un-initialized filter and polarity values.
06824   */
06825 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06826                               uint32_t TIM_ICFilter)
06827 {
06828   uint32_t tmpccmr2;
06829   uint32_t tmpccer;
06830
06831   /* Disable the Channel 3: Reset the CC3E Bit */
06832   TIMx->CCER &= ~TIM_CCER_CC3E;
06833   tmpccmr2 = TIMx->CCMR2;
06834   tmpccer = TIMx->CCER;
06835
06836   /* Select the Input */
06837   tmpccmr2 &= ~TIM_CCMR2_CC3S;
06838   tmpccmr2 |= TIM_ICSelection;
06839
06840   /* Set the filter */
06841   tmpccmr2 &= ~TIM_CCMR2_IC3F;
06842   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
06843
06844   /* Select the Polarity and set the CC3E Bit */
06845   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
06846   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
06847
06848   /* Write to TIMx CCMR2 and CCER registers */
06849   TIMx->CCMR2 = tmpccmr2;
06850   TIMx->CCER = tmpccer;
06851 }
06852
06853 /**
06854   * @brief  Configure the TI4 as Input.
06855   * @param  TIMx to select the TIM peripheral
06856   * @param  TIM_ICPolarity The Input Polarity.
06857   *          This parameter can be one of the following values:
06858   *            @arg TIM_ICPOLARITY_RISING
06859   *            @arg TIM_ICPOLARITY_FALLING
06860   *            @arg TIM_ICPOLARITY_BOTHEDGE
06861   * @param  TIM_ICSelection specifies the input to be used.
06862   *          This parameter can be one of the following values:
06863   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
06864   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
06865   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
06866   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06867   *          This parameter must be a value between 0x00 and 0x0F.
06868   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
06869   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
06870   *        protected against un-initialized filter and polarity values.
06871   * @retval None
06872   */
06873 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06874                               uint32_t TIM_ICFilter)
06875 {
06876   uint32_t tmpccmr2;
06877   uint32_t tmpccer;
06878
06879   /* Disable the Channel 4: Reset the CC4E Bit */
06880   TIMx->CCER &= ~TIM_CCER_CC4E;
06881   tmpccmr2 = TIMx->CCMR2;
06882   tmpccer = TIMx->CCER;
06883
06884   /* Select the Input */
06885   tmpccmr2 &= ~TIM_CCMR2_CC4S;
06886   tmpccmr2 |= (TIM_ICSelection << 8U);
06887
06888   /* Set the filter */
06889   tmpccmr2 &= ~TIM_CCMR2_IC4F;
06890   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
06891
06892   /* Select the Polarity and set the CC4E Bit */
06893   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
06894   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
06895
06896   /* Write to TIMx CCMR2 and CCER registers */
06897   TIMx->CCMR2 = tmpccmr2;
06898   TIMx->CCER = tmpccer ;
06899 }
06900
06901 /**
06902   * @brief  Selects the Input Trigger source
06903   * @param  TIMx to select the TIM peripheral
06904   * @param  InputTriggerSource The Input Trigger source.
06905   *          This parameter can be one of the following values:
06906   *            @arg TIM_TS_ITR0: Internal Trigger 0
06907   *            @arg TIM_TS_ITR1: Internal Trigger 1
06908   *            @arg TIM_TS_ITR2: Internal Trigger 2
06909   *            @arg TIM_TS_ITR3: Internal Trigger 3
06910   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
06911   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
06912   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
06913   *            @arg TIM_TS_ETRF: External Trigger input
06914   *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
06915   *            @arg TIM_TS_ITR5: Internal Trigger 5
06916   *            @arg TIM_TS_ITR6: Internal Trigger 6
06917   *            @arg TIM_TS_ITR7: Internal Trigger 7
06918   *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
06919   *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
06920   *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
06921   *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
06922   *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
06923   *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
06924   *
06925   *       (*)  Value not defined in all devices.
06926   *
06927   * @retval None
06928   */
06929 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
06930 {
06931   uint32_t tmpsmcr;
06932
06933   /* Get the TIMx SMCR register value */
06934   tmpsmcr = TIMx->SMCR;
06935   /* Reset the TS Bits */
06936   tmpsmcr &= ~TIM_SMCR_TS;
06937   /* Set the Input Trigger source and the slave mode*/
06938   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
06939   /* Write to TIMx SMCR */
06940   TIMx->SMCR = tmpsmcr;
06941 }
06942 /**
06943   * @brief  Configures the TIMx External Trigger (ETR).
06944   * @param  TIMx to select the TIM peripheral
06945   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
06946   *          This parameter can be one of the following values:
06947   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
06948   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
06949   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
06950   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
06951   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
06952   *          This parameter can be one of the following values:
06953   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
06954   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
06955   * @param  ExtTRGFilter External Trigger Filter.
06956   *          This parameter must be a value between 0x00 and 0x0F
06957   * @retval None
06958   */
06959 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
06960                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
06961 {
06962   uint32_t tmpsmcr;
06963
06964   tmpsmcr = TIMx->SMCR;
06965
06966   /* Reset the ETR Bits */
06967   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
06968
06969   /* Set the Prescaler, the Filter value and the Polarity */
06970   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
06971
06972   /* Write to TIMx SMCR */
06973   TIMx->SMCR = tmpsmcr;
06974 }
06975
06976 /**
06977   * @brief  Enables or disables the TIM Capture Compare Channel x.
06978   * @param  TIMx to select the TIM peripheral
06979   * @param  Channel specifies the TIM Channel
06980   *          This parameter can be one of the following values:
06981   *            @arg TIM_CHANNEL_1: TIM Channel 1
06982   *            @arg TIM_CHANNEL_2: TIM Channel 2
06983   *            @arg TIM_CHANNEL_3: TIM Channel 3
06984   *            @arg TIM_CHANNEL_4: TIM Channel 4
06985   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
06986   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
06987   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
06988   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
06989   * @retval None
06990   */
06991 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
06992 {
06993   uint32_t tmp;
06994
06995   /* Check the parameters */
06996   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
06997   assert_param(IS_TIM_CHANNELS(Channel));
06998
06999   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
07000
07001   /* Reset the CCxE Bit */
07002   TIMx->CCER &= ~tmp;
07003
07004   /* Set or reset the CCxE Bit */
07005   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
07006 }
07007
07008 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07009 /**
07010   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
07011   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
07012   *                the configuration information for TIM module.
07013   * @retval None
07014   */
07015 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
07016 {
07017   /* Reset the TIM callback to the legacy weak callbacks */
07018   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
07019   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
07020   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
07021   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
07022   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
07023   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
07024   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
07025   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
07026   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
07027   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
07028   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
07029   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
07030   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
07031   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
07032 }
07033 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07034
07035 /**
07036   * @}
07037   */
07038
07039 #endif /* HAL_TIM_MODULE_ENABLED */
07040 /**
07041   * @}
07042   */
07043
07044 /**
07045   * @}
07046   */
07047 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim.h Source File

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stm32h7xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_TIM_H
00022 #define STM32H7xx_HAL_TIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup TIM
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup TIM_Exported_Types TIM Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  TIM Time base Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00050                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00051
00052   uint32_t CounterMode;       /*!< Specifies the counter mode.
00053                                    This parameter can be a value of @ref TIM_Counter_Mode */
00054
00055   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00056                                    Auto-Reload Register at the next update event.
00057                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00058
00059   uint32_t ClockDivision;     /*!< Specifies the clock division.
00060                                    This parameter can be a value of @ref TIM_ClockDivision */
00061
00062   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00063                                     reaches zero, an update event is generated and counting restarts
00064                                     from the RCR value (N).
00065                                     This means in PWM mode that (N+1) corresponds to:
00066                                         - the number of PWM periods in edge-aligned mode
00067                                         - the number of half PWM period in center-aligned mode
00068                                      GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00069                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00070
00071   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00072                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00073 } TIM_Base_InitTypeDef;
00074
00075 /**
00076   * @brief  TIM Output Compare Configuration Structure definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t OCMode;        /*!< Specifies the TIM mode.
00081                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00082
00083   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00084                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00085
00086   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00087                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00088
00089   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00090                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00091                                @note This parameter is valid only for timer instances supporting break feature. */
00092
00093   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
00094                                This parameter can be a value of @ref TIM_Output_Fast_State
00095                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00096
00097
00098   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00099                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00100                                @note This parameter is valid only for timer instances supporting break feature. */
00101
00102   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00103                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00104                                @note This parameter is valid only for timer instances supporting break feature. */
00105 } TIM_OC_InitTypeDef;
00106
00107 /**
00108   * @brief  TIM One Pulse Mode Configuration Structure definition
00109   */
00110 typedef struct
00111 {
00112   uint32_t OCMode;        /*!< Specifies the TIM mode.
00113                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00114
00115   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00116                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00117
00118   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00119                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00120
00121   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00122                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00123                                @note This parameter is valid only for timer instances supporting break feature. */
00124
00125   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00126                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00127                                @note This parameter is valid only for timer instances supporting break feature. */
00128
00129   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00130                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00131                                @note This parameter is valid only for timer instances supporting break feature. */
00132
00133   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00134                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00135
00136   uint32_t ICSelection;   /*!< Specifies the input.
00137                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00138
00139   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00140                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00141 } TIM_OnePulse_InitTypeDef;
00142
00143 /**
00144   * @brief  TIM Input Capture Configuration Structure definition
00145   */
00146 typedef struct
00147 {
00148   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
00149                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00150
00151   uint32_t ICSelection;  /*!< Specifies the input.
00152                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00153
00154   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00155                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00156
00157   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00158                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00159 } TIM_IC_InitTypeDef;
00160
00161 /**
00162   * @brief  TIM Encoder Configuration Structure definition
00163   */
00164 typedef struct
00165 {
00166   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Encoder_Mode */
00168
00169   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00170                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00171
00172   uint32_t IC1Selection;  /*!< Specifies the input.
00173                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00174
00175   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00176                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00177
00178   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00179                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00180
00181   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00182                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00183
00184   uint32_t IC2Selection;  /*!< Specifies the input.
00185                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00186
00187   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00188                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00189
00190   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00191                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00192 } TIM_Encoder_InitTypeDef;
00193
00194 /**
00195   * @brief  Clock Configuration Handle Structure definition
00196   */
00197 typedef struct
00198 {
00199   uint32_t ClockSource;     /*!< TIM clock sources
00200                                  This parameter can be a value of @ref TIM_Clock_Source */
00201   uint32_t ClockPolarity;   /*!< TIM clock polarity
00202                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00203   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00204                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00205   uint32_t ClockFilter;     /*!< TIM clock filter
00206                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00207 } TIM_ClockConfigTypeDef;
00208
00209 /**
00210   * @brief  TIM Clear Input Configuration Handle Structure definition
00211   */
00212 typedef struct
00213 {
00214   uint32_t ClearInputState;      /*!< TIM clear Input state
00215                                       This parameter can be ENABLE or DISABLE */
00216   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00217                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00218   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00219                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00220   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00221                                       This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
00222   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
00223                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00224 } TIM_ClearInputConfigTypeDef;
00225
00226 /**
00227   * @brief  TIM Master configuration Structure definition
00228   * @note   Advanced timers provide TRGO2 internal line which is redirected
00229   *         to the ADC
00230   */
00231 typedef struct
00232 {
00233   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00234                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
00235   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00236                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00237   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00238                                         This parameter can be a value of @ref TIM_Master_Slave_Mode
00239                                         @note When the Master/slave mode is enabled, the effect of
00240                                         an event on the trigger input (TRGI) is delayed to allow a
00241                                         perfect synchronization between the current timer and its
00242                                         slaves (through TRGO). It is not mandatory in case of timer
00243                                         synchronization mode. */
00244 } TIM_MasterConfigTypeDef;
00245
00246 /**
00247   * @brief  TIM Slave configuration Structure definition
00248   */
00249 typedef struct
00250 {
00251   uint32_t  SlaveMode;         /*!< Slave mode selection
00252                                     This parameter can be a value of @ref TIM_Slave_Mode */
00253   uint32_t  InputTrigger;      /*!< Input Trigger source
00254                                     This parameter can be a value of @ref TIM_Trigger_Selection */
00255   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00256                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
00257   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00258                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
00259   uint32_t  TriggerFilter;     /*!< Input trigger filter
00260                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00261
00262 } TIM_SlaveConfigTypeDef;
00263
00264 /**
00265   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00266   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00267   *        filter and polarity.
00268   */
00269 typedef struct
00270 {
00271   uint32_t OffStateRunMode;      /*!< TIM off state in run mode
00272                                       This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00273   uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
00274                                       This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00275   uint32_t LockLevel;            /*!< TIM Lock level
00276                                       This parameter can be a value of @ref TIM_Lock_level */
00277   uint32_t DeadTime;             /*!< TIM dead Time
00278                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00279   uint32_t BreakState;           /*!< TIM Break State
00280                                       This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00281   uint32_t BreakPolarity;        /*!< TIM Break input polarity
00282                                       This parameter can be a value of @ref TIM_Break_Polarity */
00283   uint32_t BreakFilter;          /*!< Specifies the break input filter.
00284                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00285   uint32_t Break2State;          /*!< TIM Break2 State
00286                                       This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00287   uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
00288                                       This parameter can be a value of @ref TIM_Break2_Polarity */
00289   uint32_t Break2Filter;         /*!< TIM break2 input filter.
00290                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00291   uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
00292                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00293 } TIM_BreakDeadTimeConfigTypeDef;
00294
00295 /**
00296   * @brief  HAL State structures definition
00297   */
00298 typedef enum
00299 {
00300   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00301   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00302   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00303   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00304   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00305 } HAL_TIM_StateTypeDef;
00306
00307 /**
00308   * @brief  HAL Active channel structures definition
00309   */
00310 typedef enum
00311 {
00312   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00313   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00314   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00315   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00316   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
00317   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
00318   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00319 } HAL_TIM_ActiveChannel;
00320
00321 /**
00322   * @brief  TIM Time Base Handle Structure definition
00323   */
00324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00325 typedef struct __TIM_HandleTypeDef
00326 #else
00327 typedef struct
00328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00329 {
00330   TIM_TypeDef                 *Instance;     /*!< Register base address             */
00331   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
00332   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
00333   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
00334                                                   This array is accessed by a @ref DMA_Handle_index */
00335   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
00336   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00337
00338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00339   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
00340   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
00341   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
00342   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
00343   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
00344   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
00345   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
00346   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
00347   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
00348   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
00349   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
00350   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
00351   void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
00352   void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
00353   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
00354   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
00355   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
00356   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
00357   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
00358   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
00359   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
00360   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
00361   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
00362   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
00363   void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
00364   void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
00365   void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
00366   void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
00367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00368 } TIM_HandleTypeDef;
00369
00370 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00371 /**
00372   * @brief  HAL TIM Callback ID enumeration definition
00373   */
00374 typedef enum
00375 {
00376    HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
00377   ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
00378   ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
00379   ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
00380   ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
00381   ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
00382   ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
00383   ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
00384   ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
00385   ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
00386   ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
00387   ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
00388   ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00389   ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00390   ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
00391   ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
00392   ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
00393   ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
00394
00395   ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
00396   ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
00397   ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
00398   ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
00399   ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
00400   ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
00401   ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
00402   ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
00403   ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
00404   ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
00405 } HAL_TIM_CallbackIDTypeDef;
00406
00407 /**
00408   * @brief  HAL TIM Callback pointer definition
00409   */
00410 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
00411
00412 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00413
00414 /**
00415   * @}
00416   */
00417 /* End of exported types -----------------------------------------------------*/
00418
00419 /* Exported constants --------------------------------------------------------*/
00420 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00421   * @{
00422   */
00423
00424 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00425   * @{
00426   */
00427 #define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
00428 #define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00434   * @{
00435   */
00436 #define TIM_DMABASE_CR1                    0x00000000U
00437 #define TIM_DMABASE_CR2                    0x00000001U
00438 #define TIM_DMABASE_SMCR                   0x00000002U
00439 #define TIM_DMABASE_DIER                   0x00000003U
00440 #define TIM_DMABASE_SR                     0x00000004U
00441 #define TIM_DMABASE_EGR                    0x00000005U
00442 #define TIM_DMABASE_CCMR1                  0x00000006U
00443 #define TIM_DMABASE_CCMR2                  0x00000007U
00444 #define TIM_DMABASE_CCER                   0x00000008U
00445 #define TIM_DMABASE_CNT                    0x00000009U
00446 #define TIM_DMABASE_PSC                    0x0000000AU
00447 #define TIM_DMABASE_ARR                    0x0000000BU
00448 #define TIM_DMABASE_RCR                    0x0000000CU
00449 #define TIM_DMABASE_CCR1                   0x0000000DU
00450 #define TIM_DMABASE_CCR2                   0x0000000EU
00451 #define TIM_DMABASE_CCR3                   0x0000000FU
00452 #define TIM_DMABASE_CCR4                   0x00000010U
00453 #define TIM_DMABASE_BDTR                   0x00000011U
00454 #define TIM_DMABASE_DCR                    0x00000012U
00455 #define TIM_DMABASE_DMAR                   0x00000013U
00456 #define TIM_DMABASE_CCMR3                  0x00000015U
00457 #define TIM_DMABASE_CCR5                   0x00000016U
00458 #define TIM_DMABASE_CCR6                   0x00000017U
00459 #if   defined(TIM_BREAK_INPUT_SUPPORT)
00460 #define TIM_DMABASE_AF1                    0x00000018U
00461 #define TIM_DMABASE_AF2                    0x00000019U
00462 #endif /* TIM_BREAK_INPUT_SUPPORT */
00463 #define TIM_DMABASE_TISEL                  0x00000020U
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup TIM_Event_Source TIM Event Source
00469   * @{
00470   */
00471 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00472 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00473 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00474 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00475 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00476 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00477 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00478 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00479 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00485   * @{
00486   */
00487 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
00488 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
00489 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00495   * @{
00496   */
00497 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
00498 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00504   * @{
00505   */
00506 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
00507 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
00508 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
00509 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00515   * @{
00516   */
00517 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
00518 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
00519 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
00520 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
00521 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_ClockDivision TIM Clock Division
00527   * @{
00528   */
00529 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
00530 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
00531 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00537   * @{
00538   */
00539 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
00540 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00546   * @{
00547   */
00548 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
00549 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00556   * @{
00557   */
00558 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
00559 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
00560 /**
00561   * @}
00562   */
00563
00564 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00565   * @{
00566   */
00567 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
00568 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00574   * @{
00575   */
00576 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
00577 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00583   * @{
00584   */
00585 #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
00586 #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00592   * @{
00593   */
00594 #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
00595 #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00601   * @{
00602   */
00603 #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
00604 #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00610   * @{
00611   */
00612 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
00613 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
00614 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
00620   * @{
00621   */
00622 #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
00623 #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00629   * @{
00630   */
00631 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
00632                                                                                      connected to IC1, IC2, IC3 or IC4, respectively */
00633 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
00634                                                                                      connected to IC2, IC1, IC4 or IC3, respectively */
00635 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00641   * @{
00642   */
00643 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
00644 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
00645 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
00646 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00652   * @{
00653   */
00654 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
00655 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00661   * @{
00662   */
00663 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
00664 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
00665 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00671   * @{
00672   */
00673 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
00674 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
00675 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
00676 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
00677 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
00678 #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
00679 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
00680 #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00686   * @{
00687   */
00688 #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
00689 #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup TIM_DMA_sources TIM DMA Sources
00695   * @{
00696   */
00697 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
00698 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
00699 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
00700 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
00701 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
00702 #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
00703 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
00704 /**
00705   * @}
00706   */
00707
00708 /** @defgroup TIM_Flag_definition TIM Flag Definition
00709   * @{
00710   */
00711 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
00712 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
00713 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
00714 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
00715 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
00716 #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
00717 #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
00718 #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
00719 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
00720 #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
00721 #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
00722 #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
00723 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
00724 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
00725 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
00726 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup TIM_Channel TIM Channel
00732   * @{
00733   */
00734 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
00735 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
00736 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
00737 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
00738 #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
00739 #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
00740 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
00741 /**
00742   * @}
00743   */
00744
00745 /** @defgroup TIM_Clock_Source TIM Clock Source
00746   * @{
00747   */
00748 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
00749 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
00750 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
00751 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
00752 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
00753 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
00754 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
00755 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
00756 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
00757 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
00758 #define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
00759 #define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
00760 #define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
00761 #define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
00762 #define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
00763 /**
00764   * @}
00765   */
00766
00767 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00768   * @{
00769   */
00770 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
00771 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
00772 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
00773 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00774 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00780   * @{
00781   */
00782 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
00783 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00784 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00785 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00791   * @{
00792   */
00793 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
00794 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00800   * @{
00801   */
00802 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
00803 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00804 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00805 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00806 /**
00807   * @}
00808   */
00809
00810 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00811   * @{
00812   */
00813 #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00814 #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00820   * @{
00821   */
00822 #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00823 #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00824 /**
00825   * @}
00826   */
00827 /** @defgroup TIM_Lock_level  TIM Lock level
00828   * @{
00829   */
00830 #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
00831 #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
00832 #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
00833 #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00839   * @{
00840   */
00841 #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
00842 #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00848   * @{
00849   */
00850 #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
00851 #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
00852 /**
00853   * @}
00854   */
00855
00856 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00857   * @{
00858   */
00859 #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
00860 #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
00861 /**
00862   * @}
00863   */
00864
00865 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00866   * @{
00867   */
00868 #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
00869 #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00875   * @{
00876   */
00877 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
00878 #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event
00879                                                                                     (if none of the break inputs BRK and BRK2 is active) */
00880 /**
00881   * @}
00882   */
00883
00884 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
00885   * @{
00886   */
00887 #define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00888 #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
00889 #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
00890 #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00896   * @{
00897   */
00898 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
00899 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
00900 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
00901 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
00902 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
00903 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
00904 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
00905 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00911   * @{
00912   */
00913 #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
00914 #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
00915 #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
00916 #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
00917 #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
00918 #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
00919 #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
00920 #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
00921 #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
00922 #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
00923 #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
00924 #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
00925 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
00926 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
00927 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00928 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
00934   * @{
00935   */
00936 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
00937 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup TIM_Slave_Mode TIM Slave mode
00943   * @{
00944   */
00945 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
00946 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
00947 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
00948 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
00949 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
00950 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
00956   * @{
00957   */
00958 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
00959 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
00960 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
00961 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
00962 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
00963 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
00964 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
00965 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
00966 #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
00967 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
00968 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
00969 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
00970 #define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
00971 #define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00977   * @{
00978   */
00979 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
00980 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
00981 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
00982 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
00983 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
00984 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
00985 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
00986 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
00987 #define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
00988 #define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
00989 #define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
00990 #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
00991 #define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
00992 #define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
00993 #define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
00994 #define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
00995 #define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
00996 #define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
00997 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
00998 /**
00999   * @}
01000   */
01001
01002 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
01003   * @{
01004   */
01005 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
01006 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
01007 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01008 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01009 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01010 /**
01011   * @}
01012   */
01013
01014 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
01015   * @{
01016   */
01017 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
01018 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
01019 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
01020 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
01021 /**
01022   * @}
01023   */
01024
01025 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
01026   * @{
01027   */
01028 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
01029 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
01030 /**
01031   * @}
01032   */
01033
01034 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
01035   * @{
01036   */
01037 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
01038 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01039 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01040 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01041 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01042 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01043 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01044 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01045 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01046 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01047 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01048 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01049 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01050 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01051 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01052 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01053 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01054 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01055 /**
01056   * @}
01057   */
01058
01059 /** @defgroup DMA_Handle_index TIM DMA Handle Index
01060   * @{
01061   */
01062 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
01063 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
01064 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
01065 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
01066 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
01067 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
01068 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
01074   * @{
01075   */
01076 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
01077 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
01078 #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
01079 #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
01080 /**
01081   * @}
01082   */
01083
01084 /** @defgroup TIM_Break_System TIM Break System
01085   * @{
01086   */
01087 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
01088 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
01089 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
01090 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
01091 /**
01092   * @}
01093   */
01094
01095 /**
01096   * @}
01097   */
01098 /* End of exported constants -------------------------------------------------*/
01099
01100 /* Exported macros -----------------------------------------------------------*/
01101 /** @defgroup TIM_Exported_Macros TIM Exported Macros
01102   * @{
01103   */
01104
01105 /** @brief  Reset TIM handle state.
01106   * @param  __HANDLE__ TIM handle.
01107   * @retval None
01108   */
01109 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01110 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
01111                                                       (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
01112                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;     \
01113                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
01114                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;     \
01115                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
01116                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;     \
01117                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
01118                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
01119                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
01120                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
01121                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
01122                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
01123                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
01124                                                       (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
01125                                                       (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
01126                                                      } while(0)
01127 #else
01128 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
01129 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01130
01131 /**
01132   * @brief  Enable the TIM peripheral.
01133   * @param  __HANDLE__ TIM handle
01134   * @retval None
01135   */
01136 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01137
01138 /**
01139   * @brief  Enable the TIM main Output.
01140   * @param  __HANDLE__ TIM handle
01141   * @retval None
01142   */
01143 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01144
01145 /**
01146   * @brief  Disable the TIM peripheral.
01147   * @param  __HANDLE__ TIM handle
01148   * @retval None
01149   */
01150 #define __HAL_TIM_DISABLE(__HANDLE__) \
01151   do { \
01152     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01153     { \
01154       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01155       { \
01156         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01157       } \
01158     } \
01159   } while(0)
01160
01161 /**
01162   * @brief  Disable the TIM main Output.
01163   * @param  __HANDLE__ TIM handle
01164   * @retval None
01165   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
01166   */
01167 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01168   do { \
01169     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01170     { \
01171       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01172       { \
01173         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01174       } \
01175     } \
01176   } while(0)
01177
01178 /**
01179   * @brief  Disable the TIM main Output.
01180   * @param  __HANDLE__ TIM handle
01181   * @retval None
01182   * @note The Main Output Enable of a timer instance is disabled unconditionally
01183   */
01184 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
01185
01186 /** @brief  Enable the specified TIM interrupt.
01187   * @param  __HANDLE__ specifies the TIM Handle.
01188   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
01189   *          This parameter can be one of the following values:
01190   *            @arg TIM_IT_UPDATE: Update interrupt
01191   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01192   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01193   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01194   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01195   *            @arg TIM_IT_COM:   Commutation interrupt
01196   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01197   *            @arg TIM_IT_BREAK: Break interrupt
01198   * @retval None
01199   */
01200 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01201
01202 /** @brief  Disable the specified TIM interrupt.
01203   * @param  __HANDLE__ specifies the TIM Handle.
01204   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
01205   *          This parameter can be one of the following values:
01206   *            @arg TIM_IT_UPDATE: Update interrupt
01207   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01208   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01209   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01210   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01211   *            @arg TIM_IT_COM:   Commutation interrupt
01212   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01213   *            @arg TIM_IT_BREAK: Break interrupt
01214   * @retval None
01215   */
01216 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01217
01218 /** @brief  Enable the specified DMA request.
01219   * @param  __HANDLE__ specifies the TIM Handle.
01220   * @param  __DMA__ specifies the TIM DMA request to enable.
01221   *          This parameter can be one of the following values:
01222   *            @arg TIM_DMA_UPDATE: Update DMA request
01223   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01224   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01225   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01226   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01227   *            @arg TIM_DMA_COM:   Commutation DMA request
01228   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01229   * @retval None
01230   */
01231 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01232
01233 /** @brief  Disable the specified DMA request.
01234   * @param  __HANDLE__ specifies the TIM Handle.
01235   * @param  __DMA__ specifies the TIM DMA request to disable.
01236   *          This parameter can be one of the following values:
01237   *            @arg TIM_DMA_UPDATE: Update DMA request
01238   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01239   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01240   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01241   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01242   *            @arg TIM_DMA_COM:   Commutation DMA request
01243   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01244   * @retval None
01245   */
01246 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01247
01248 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01249   * @param  __HANDLE__ specifies the TIM Handle.
01250   * @param  __FLAG__ specifies the TIM interrupt flag to check.
01251   *        This parameter can be one of the following values:
01252   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01253   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01254   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01255   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01256   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01257   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01258   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01259   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01260   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01261   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01262   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01263   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01264   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01265   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01266   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01267   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01268   * @retval The new state of __FLAG__ (TRUE or FALSE).
01269   */
01270 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01271
01272 /** @brief  Clear the specified TIM interrupt flag.
01273   * @param  __HANDLE__ specifies the TIM Handle.
01274   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
01275   *        This parameter can be one of the following values:
01276   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01277   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01278   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01279   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01280   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01281   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01282   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01283   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01284   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01285   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01286   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01287   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01288   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01289   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01290   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01291   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01292   * @retval The new state of __FLAG__ (TRUE or FALSE).
01293   */
01294 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01295
01296 /**
01297   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01298   * @param  __HANDLE__ TIM handle
01299   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
01300   *          This parameter can be one of the following values:
01301   *            @arg TIM_IT_UPDATE: Update interrupt
01302   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01303   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01304   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01305   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01306   *            @arg TIM_IT_COM:   Commutation interrupt
01307   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01308   *            @arg TIM_IT_BREAK: Break interrupt
01309   * @retval The state of TIM_IT (SET or RESET).
01310   */
01311 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
01312                                                              == (__INTERRUPT__)) ? SET : RESET)
01313
01314 /** @brief Clear the TIM interrupt pending bits.
01315   * @param  __HANDLE__ TIM handle
01316   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01317   *          This parameter can be one of the following values:
01318   *            @arg TIM_IT_UPDATE: Update interrupt
01319   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01320   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01321   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01322   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01323   *            @arg TIM_IT_COM:   Commutation interrupt
01324   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01325   *            @arg TIM_IT_BREAK: Break interrupt
01326   * @retval None
01327   */
01328 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01329
01330 /**
01331   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01332   * @param  __HANDLE__ TIM handle.
01333   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01334   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
01335 mode.
01336   */
01337 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01338
01339 /**
01340   * @brief  Set the TIM Prescaler on runtime.
01341   * @param  __HANDLE__ TIM handle.
01342   * @param  __PRESC__ specifies the Prescaler new value.
01343   * @retval None
01344   */
01345 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01346
01347 /**
01348   * @brief  Set the TIM Counter Register value on runtime.
01349   * @param  __HANDLE__ TIM handle.
01350   * @param  __COUNTER__ specifies the Counter register new value.
01351   * @retval None
01352   */
01353 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01354
01355 /**
01356   * @brief  Get the TIM Counter Register value on runtime.
01357   * @param  __HANDLE__ TIM handle.
01358   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01359   */
01360 #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
01361
01362 /**
01363   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01364   * @param  __HANDLE__ TIM handle.
01365   * @param  __AUTORELOAD__ specifies the Counter register new value.
01366   * @retval None
01367   */
01368 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01369   do{                                                    \
01370     (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01371     (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01372   } while(0)
01373
01374 /**
01375   * @brief  Get the TIM Autoreload Register value on runtime.
01376   * @param  __HANDLE__ TIM handle.
01377   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01378   */
01379 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
01380
01381 /**
01382   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01383   * @param  __HANDLE__ TIM handle.
01384   * @param  __CKD__ specifies the clock division value.
01385   *          This parameter can be one of the following value:
01386   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01387   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01388   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01389   * @retval None
01390   */
01391 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01392   do{                                                   \
01393     (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
01394     (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
01395     (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
01396   } while(0)
01397
01398 /**
01399   * @brief  Get the TIM Clock Division value on runtime.
01400   * @param  __HANDLE__ TIM handle.
01401   * @retval The clock division can be one of the following values:
01402   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01403   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01404   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01405   */
01406 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01407
01408 /**
01409   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
01410   * @param  __HANDLE__ TIM handle.
01411   * @param  __CHANNEL__ TIM Channels to be configured.
01412   *          This parameter can be one of the following values:
01413   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01414   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01415   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01416   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01417   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
01418   *          This parameter can be one of the following values:
01419   *            @arg TIM_ICPSC_DIV1: no prescaler
01420   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01421   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01422   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01423   * @retval None
01424   */
01425 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01426   do{                                                    \
01427     TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01428     TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01429   } while(0)
01430
01431 /**
01432   * @brief  Get the TIM Input Capture prescaler on runtime.
01433   * @param  __HANDLE__ TIM handle.
01434   * @param  __CHANNEL__ TIM Channels to be configured.
01435   *          This parameter can be one of the following values:
01436   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01437   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01438   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01439   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01440   * @retval The input capture prescaler can be one of the following values:
01441   *            @arg TIM_ICPSC_DIV1: no prescaler
01442   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01443   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01444   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01445   */
01446 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01447   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01448    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01449    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01450    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01451
01452 /**
01453   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01454   * @param  __HANDLE__ TIM handle.
01455   * @param  __CHANNEL__ TIM Channels to be configured.
01456   *          This parameter can be one of the following values:
01457   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01458   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01459   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01460   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01461   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01462   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01463   * @param  __COMPARE__ specifies the Capture Compare register new value.
01464   * @retval None
01465   */
01466 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01467   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01468    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01469    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01470    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01471    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01472    ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01473
01474 /**
01475   * @brief  Get the TIM Capture Compare Register value on runtime.
01476   * @param  __HANDLE__ TIM handle.
01477   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
01478   *          This parameter can be one of the following values:
01479   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01480   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01481   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01482   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01483   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01484   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01485   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01486   */
01487 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01488   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01489    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01490    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01491    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01492    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01493    ((__HANDLE__)->Instance->CCR6))
01494
01495 /**
01496   * @brief  Set the TIM Output compare preload.
01497   * @param  __HANDLE__ TIM handle.
01498   * @param  __CHANNEL__ TIM Channels to be configured.
01499   *          This parameter can be one of the following values:
01500   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01501   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01502   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01503   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01504   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01505   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01506   * @retval None
01507   */
01508 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01509   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
01510    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
01511    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
01512    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
01513    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
01514    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
01515
01516 /**
01517   * @brief  Reset the TIM Output compare preload.
01518   * @param  __HANDLE__ TIM handle.
01519   * @param  __CHANNEL__ TIM Channels to be configured.
01520   *          This parameter can be one of the following values:
01521   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01522   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01523   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01524   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01525   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01526   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01527   * @retval None
01528   */
01529 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01530   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
01531    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
01532    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
01533    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
01534    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
01535    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
01536
01537 /**
01538   * @brief  Enable fast mode for a given channel.
01539   * @param  __HANDLE__ TIM handle.
01540   * @param  __CHANNEL__ TIM Channels to be configured.
01541   *          This parameter can be one of the following values:
01542   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01543   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01544   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01545   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01546   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01547   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01548   * @note  When fast mode is enabled an active edge on the trigger input acts
01549   *        like a compare match on CCx output. Delay to sample the trigger
01550   *        input and to activate CCx output is reduced to 3 clock cycles.
01551   * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
01552   * @retval None
01553   */
01554 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01555   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
01556    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
01557    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
01558    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
01559    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
01560    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
01561
01562 /**
01563   * @brief  Disable fast mode for a given channel.
01564   * @param  __HANDLE__ TIM handle.
01565   * @param  __CHANNEL__ TIM Channels to be configured.
01566   *          This parameter can be one of the following values:
01567   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01568   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01569   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01570   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01571   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01572   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01573   * @note  When fast mode is disabled CCx output behaves normally depending
01574   *        on counter and CCRx values even when the trigger is ON. The minimum
01575   *        delay to activate CCx output when an active edge occurs on the
01576   *        trigger input is 5 clock cycles.
01577   * @retval None
01578   */
01579 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01580   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
01581    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
01582    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
01583    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
01584    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
01585    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
01586
01587 /**
01588   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01589   * @param  __HANDLE__ TIM handle.
01590   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
01591   *        overflow/underflow generates an update interrupt or DMA request (if
01592   *        enabled)
01593   * @retval None
01594   */
01595 #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
01596
01597 /**
01598   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01599   * @param  __HANDLE__ TIM handle.
01600   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
01601   *        following events generate an update interrupt or DMA request (if
01602   *        enabled):
01603   *           _ Counter overflow underflow
01604   *           _ Setting the UG bit
01605   *           _ Update generation through the slave mode controller
01606   * @retval None
01607   */
01608 #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
01609
01610 /**
01611   * @brief  Set the TIM Capture x input polarity on runtime.
01612   * @param  __HANDLE__ TIM handle.
01613   * @param  __CHANNEL__ TIM Channels to be configured.
01614   *          This parameter can be one of the following values:
01615   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01616   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01617   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01618   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01619   * @param  __POLARITY__ Polarity for TIx source
01620   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01621   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01622   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01623   * @retval None
01624   */
01625 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01626   do{                                                                     \
01627     TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01628     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01629   }while(0)
01630
01631 /**
01632   * @}
01633   */
01634 /* End of exported macros ----------------------------------------------------*/
01635
01636 /* Private constants ---------------------------------------------------------*/
01637 /** @defgroup TIM_Private_Constants TIM Private Constants
01638   * @{
01639   */
01640 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01641    channels have been disabled */
01642 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01643 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01644 /**
01645   * @}
01646   */
01647 /* End of private constants --------------------------------------------------*/
01648
01649 /* Private macros ------------------------------------------------------------*/
01650 /** @defgroup TIM_Private_Macros TIM Private Macros
01651   * @{
01652   */
01653 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
01654                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
01655
01656 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01657                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01658                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01659                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01660                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01661                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01662                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01663                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01664                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01665                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01666                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01667                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01668                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01669                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01670                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01671                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01672                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01673                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01674                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01675                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01676                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01677                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
01678                                    ((__BASE__) == TIM_DMABASE_AF2)   || \
01679                                    ((__BASE__) == TIM_DMABASE_TISEL))
01680
01681
01682 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01683
01684 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01685                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01686                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01687                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01688                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01689
01690 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01691                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01692                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01693
01694 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01695                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01696
01697 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01698                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01699
01700 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01701                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01702
01703 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01704                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01705
01706 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01707                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01708
01709 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01710                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01711
01712 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
01713                                                       ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
01714
01715 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01716                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01717                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01718
01719 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01720                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01721                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01722
01723 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01724                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01725                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01726                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01727
01728 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01729                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01730
01731 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01732                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01733                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01734
01735 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01736
01737 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01738                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01739                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01740                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01741                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01742                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01743                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01744
01745 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01746                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01747
01748 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01749                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01750                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01751
01752 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01753                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01754                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01755                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01756                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01757                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01758                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01759                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01760                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01761                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01762
01763 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01764                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01765                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01766                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01767                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01768
01769 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01770                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01771                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01772                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01773
01774 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
01775
01776 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01777                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01778
01779 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01780                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01781                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01782                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01783
01784 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01785
01786 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01787                                             ((__STATE__) == TIM_OSSR_DISABLE))
01788
01789 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01790                                             ((__STATE__) == TIM_OSSI_DISABLE))
01791
01792 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01793                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01794                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01795                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01796
01797 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
01798
01799
01800 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01801                                             ((__STATE__) == TIM_BREAK_DISABLE))
01802
01803 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01804                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01805
01806 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01807                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01808
01809 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01810                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01811
01812 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01813                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01814
01815 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
01816
01817 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01818                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01819                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01820                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01821                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01822                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01823                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01824                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01825
01826 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01827                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01828                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01829                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01830                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01831                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01832                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01833                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01834                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01835                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01836                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01837                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01838                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01839                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01840                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01841                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01842                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01843
01844 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01845                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01846
01847 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
01848                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
01849                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
01850                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
01851                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
01852                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01853
01854 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
01855                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
01856                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
01857                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
01858                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
01859                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
01860
01861 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
01862                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
01863                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
01864                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
01865                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
01866                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
01867                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
01868                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
01869
01870 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01871                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01872                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01873                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01874                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01875                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01876                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01877                                                  ((__SELECTION__) == TIM_TS_ETRF) || \
01878                                                  ((__SELECTION__) == TIM_TS_ITR4) || \
01879                                                  ((__SELECTION__) == TIM_TS_ITR5) || \
01880                                                  ((__SELECTION__) == TIM_TS_ITR6) || \
01881                                                  ((__SELECTION__) == TIM_TS_ITR7) || \
01882                                                  ((__SELECTION__) == TIM_TS_ITR8) || \
01883                                                  ((__SELECTION__) == TIM_TS_ITR12) || \
01884                                                  ((__SELECTION__) == TIM_TS_ITR13))
01885
01886 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01887                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01888                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01889                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01890                                                                ((__SELECTION__) == TIM_TS_ITR4) || \
01891                                                                ((__SELECTION__) == TIM_TS_ITR5) || \
01892                                                                ((__SELECTION__) == TIM_TS_ITR6) || \
01893                                                                ((__SELECTION__) == TIM_TS_ITR7) || \
01894                                                                ((__SELECTION__) == TIM_TS_ITR8) || \
01895                                                                ((__SELECTION__) == TIM_TS_ITR12) || \
01896                                                                ((__SELECTION__) == TIM_TS_ITR13) || \
01897                                                                ((__SELECTION__) == TIM_TS_NONE))
01898
01899 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01900                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01901                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01902                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01903                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01904
01905 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01906                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01907                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01908                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01909
01910 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01911
01912 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01913                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01914
01915 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01916                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01917                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01918                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01919                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01920                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01921                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01922                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01923                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01924                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01925                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01926                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01927                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01928                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01929                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01930                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01931                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01932                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01933
01934 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
01935
01936 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
01937
01938 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
01939
01940 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
01941                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
01942                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
01943                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
01944
01945 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
01946                                                        ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01947
01948 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01949   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01950    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
01951    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01952    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
01953
01954 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01955   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
01956    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
01957    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
01958    ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
01959
01960 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01961   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01962    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
01963    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
01964    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
01965
01966 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01967   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01968    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01969    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01970    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01971
01972 /**
01973   * @}
01974   */
01975 /* End of private macros -----------------------------------------------------*/
01976
01977 /* Include TIM HAL Extended module */
01978 #include "stm32h7xx_hal_tim_ex.h"
01979
01980 /* Exported functions --------------------------------------------------------*/
01981 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
01982   * @{
01983   */
01984
01985 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
01986   *  @brief   Time Base functions
01987   * @{
01988   */
01989 /* Time Base functions ********************************************************/
01990 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01991 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01992 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01993 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01994 /* Blocking mode: Polling */
01995 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01996 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01997 /* Non-Blocking mode: Interrupt */
01998 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01999 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
02000 /* Non-Blocking mode: DMA */
02001 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
02002 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
02003 /**
02004   * @}
02005   */
02006
02007 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
02008   *  @brief   TIM Output Compare functions
02009   * @{
02010   */
02011 /* Timer Output Compare functions *********************************************/
02012 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
02013 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
02014 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
02015 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
02016 /* Blocking mode: Polling */
02017 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02018 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02019 /* Non-Blocking mode: Interrupt */
02020 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02021 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02022 /* Non-Blocking mode: DMA */
02023 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02024 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02025 /**
02026   * @}
02027   */
02028
02029 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
02030   *  @brief   TIM PWM functions
02031   * @{
02032   */
02033 /* Timer PWM functions ********************************************************/
02034 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
02035 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
02036 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
02037 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
02038 /* Blocking mode: Polling */
02039 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02040 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02041 /* Non-Blocking mode: Interrupt */
02042 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02043 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02044 /* Non-Blocking mode: DMA */
02045 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02046 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02047 /**
02048   * @}
02049   */
02050
02051 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
02052   *  @brief   TIM Input Capture functions
02053   * @{
02054   */
02055 /* Timer Input Capture functions **********************************************/
02056 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
02057 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
02058 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
02059 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
02060 /* Blocking mode: Polling */
02061 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02062 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02063 /* Non-Blocking mode: Interrupt */
02064 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02065 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02066 /* Non-Blocking mode: DMA */
02067 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02068 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02069 /**
02070   * @}
02071   */
02072
02073 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02074   *  @brief   TIM One Pulse functions
02075   * @{
02076   */
02077 /* Timer One Pulse functions **************************************************/
02078 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
02079 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
02080 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
02081 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
02082 /* Blocking mode: Polling */
02083 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02084 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02085 /* Non-Blocking mode: Interrupt */
02086 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02087 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02088 /**
02089   * @}
02090   */
02091
02092 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
02093   *  @brief   TIM Encoder functions
02094   * @{
02095   */
02096 /* Timer Encoder functions ****************************************************/
02097 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
02098 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
02099 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
02100 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
02101 /* Blocking mode: Polling */
02102 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02103 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02104 /* Non-Blocking mode: Interrupt */
02105 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02106 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02107 /* Non-Blocking mode: DMA */
02108 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02109                                             uint32_t *pData2, uint16_t Length);
02110 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02111 /**
02112   * @}
02113   */
02114
02115 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02116   *  @brief   IRQ handler management
02117   * @{
02118   */
02119 /* Interrupt Handler functions  ***********************************************/
02120 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
02121 /**
02122   * @}
02123   */
02124
02125 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
02126   *  @brief   Peripheral Control functions
02127   * @{
02128   */
02129 /* Control functions  *********************************************************/
02130 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
02131 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
02132 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
02133 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
02134                                                  uint32_t OutputChannel,  uint32_t InputChannel);
02135 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
02136                                            uint32_t Channel);
02137 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
02138 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
02139 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
02140 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
02141 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02142                                               uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02143 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02144                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
02145                                                    uint32_t DataLength);
02146 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02147 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02148                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02149 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02150                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
02151                                                   uint32_t  DataLength);
02152 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02153 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
02154 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
02155 /**
02156   * @}
02157   */
02158
02159 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
02160   *  @brief   TIM Callbacks functions
02161   * @{
02162   */
02163 /* Callback in non blocking modes (Interrupt and DMA) *************************/
02164 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
02165 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
02166 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
02167 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
02168 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
02169 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
02170 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
02171 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
02172 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
02173 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
02174
02175 /* Callbacks Register/UnRegister functions  ***********************************/
02176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02177 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
02178                                            pTIM_CallbackTypeDef pCallback);
02179 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
02180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02181
02182 /**
02183   * @}
02184   */
02185
02186 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
02187   *  @brief  Peripheral State functions
02188   * @{
02189   */
02190 /* Peripheral State functions  ************************************************/
02191 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
02192 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
02193 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
02194 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
02195 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
02196 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
02197 /**
02198   * @}
02199   */
02200
02201 /**
02202   * @}
02203   */
02204 /* End of exported functions -------------------------------------------------*/
02205
02206 /* Private functions----------------------------------------------------------*/
02207 /** @defgroup TIM_Private_Functions TIM Private Functions
02208   * @{
02209   */
02210 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
02211 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
02212 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
02213 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
02214                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
02215
02216 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
02217 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
02218 void TIM_DMAError(DMA_HandleTypeDef *hdma);
02219 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
02220 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
02221 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
02222
02223 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02224 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
02225 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02226
02227 /**
02228   * @}
02229   */
02230 /* End of private functions --------------------------------------------------*/
02231
02232 /**
02233   * @}
02234   */
02235
02236 /**
02237   * @}
02238   */
02239
02240 #ifdef __cplusplus
02241 }
02242 #endif
02243
02244 #endif /* STM32H7xx_HAL_TIM_H */
02245
02246 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim_ex.c Source File

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stm32h7xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer Extended peripheral:
00008   *           + Time Hall Sensor Interface Initialization
00009   *           + Time Hall Sensor Interface Start
00010   *           + Time Complementary signal break and dead time configuration
00011   *           + Time Master and Slave synchronization configuration
00012   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00013   *           + Timer remapping capabilities configuration
00014   @verbatim
00015   ==============================================================================
00016                       ##### TIMER Extended features #####
00017   ==============================================================================
00018   [..]
00019     The Timer Extended features include:
00020     (#) Complementary outputs with programmable dead-time for :
00021         (++) Output Compare
00022         (++) PWM generation (Edge and Center-aligned Mode)
00023         (++) One-pulse mode output
00024     (#) Synchronization circuit to control the timer with external signals and to
00025         interconnect several timers together.
00026     (#) Break input to put the timer output signals in reset state or in a known state.
00027     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00028         positioning purposes
00029
00030             ##### How to use this driver #####
00031   ==============================================================================
00032     [..]
00033      (#) Initialize the TIM low level resources by implementing the following functions
00034          depending on the selected feature:
00035            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00036
00037      (#) Initialize the TIM low level resources :
00038         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00039         (##) TIM pins configuration
00040             (+++) Enable the clock for the TIM GPIOs using the following function:
00041               __HAL_RCC_GPIOx_CLK_ENABLE();
00042             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00043
00044      (#) The external Clock can be configured, if needed (the default clock is the
00045          internal clock from the APBx), using the following function:
00046          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00047          any start function.
00048
00049      (#) Configure the TIM in the desired functioning mode using one of the
00050          initialization function of this driver:
00051           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
00052                Timer Hall Sensor Interface and the commutation event with the corresponding
00053                Interrupt and DMA request if needed (Note that One Timer is used to interface
00054                with the Hall sensor Interface and another Timer should be used to use
00055                the commutation event).
00056
00057      (#) Activate the TIM peripheral using one of the start functions:
00058            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00059            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00060            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00061            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00068   * All rights reserved.</center></h2>
00069   *
00070   * This software component is licensed by ST under BSD 3-Clause license,
00071   * the "License"; You may not use this file except in compliance with the
00072   * License. You may obtain a copy of the License at:
00073   *                        opensource.org/licenses/BSD-3-Clause
00074   *
00075   ******************************************************************************
00076   */
00077
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32h7xx_hal.h"
00080
00081 /** @addtogroup STM32H7xx_HAL_Driver
00082   * @{
00083   */
00084
00085 /** @defgroup TIMEx TIMEx
00086   * @brief TIM Extended HAL module driver
00087   * @{
00088   */
00089
00090 #ifdef HAL_TIM_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /* Private macro -------------------------------------------------------------*/
00095 /* Private variables ---------------------------------------------------------*/
00096 /* Private function prototypes -----------------------------------------------*/
00097 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
00098
00099 /* Exported functions --------------------------------------------------------*/
00100 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00101   * @{
00102   */
00103
00104 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00105   * @brief    Timer Hall Sensor functions
00106   *
00107 @verbatim
00108   ==============================================================================
00109                       ##### Timer Hall Sensor functions #####
00110   ==============================================================================
00111   [..]
00112     This section provides functions allowing to:
00113     (+) Initialize and configure TIM HAL Sensor.
00114     (+) De-initialize TIM HAL Sensor.
00115     (+) Start the Hall Sensor Interface.
00116     (+) Stop the Hall Sensor Interface.
00117     (+) Start the Hall Sensor Interface and enable interrupts.
00118     (+) Stop the Hall Sensor Interface and disable interrupts.
00119     (+) Start the Hall Sensor Interface and enable DMA transfers.
00120     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00121
00122 @endverbatim
00123   * @{
00124   */
00125 /**
00126   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00127   * @param  htim TIM Hall Sensor Interface handle
00128   * @param  sConfig TIM Hall Sensor configuration structure
00129   * @retval HAL status
00130   */
00131 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
00132 {
00133   TIM_OC_InitTypeDef OC_Config;
00134
00135   /* Check the TIM handle allocation */
00136   if (htim == NULL)
00137   {
00138     return HAL_ERROR;
00139   }
00140
00141   /* Check the parameters */
00142   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00143   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00144   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00145   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00146   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00147   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00148   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00149
00150   if (htim->State == HAL_TIM_STATE_RESET)
00151   {
00152     /* Allocate lock resource and initialize it */
00153     htim->Lock = HAL_UNLOCKED;
00154
00155 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00156     /* Reset interrupt callbacks to legacy week callbacks */
00157     TIM_ResetCallback(htim);
00158
00159     if (htim->HallSensor_MspInitCallback == NULL)
00160     {
00161       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
00162     }
00163     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00164     htim->HallSensor_MspInitCallback(htim);
00165 #else
00166     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00167     HAL_TIMEx_HallSensor_MspInit(htim);
00168 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00169   }
00170
00171   /* Set the TIM state */
00172   htim->State = HAL_TIM_STATE_BUSY;
00173
00174   /* Configure the Time base in the Encoder Mode */
00175   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00176
00177   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00178   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00179
00180   /* Reset the IC1PSC Bits */
00181   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00182   /* Set the IC1PSC value */
00183   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00184
00185   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00186   htim->Instance->CR2 |= TIM_CR2_TI1S;
00187
00188   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00189   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00190   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00191
00192   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00193   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00194   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00195
00196   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00197   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00198   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00199   OC_Config.OCMode = TIM_OCMODE_PWM2;
00200   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00201   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00202   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00203   OC_Config.Pulse = sConfig->Commutation_Delay;
00204
00205   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00206
00207   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00208     register to 101 */
00209   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00210   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00211
00212   /* Initialize the TIM state*/
00213   htim->State = HAL_TIM_STATE_READY;
00214
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  DeInitializes the TIM Hall Sensor interface
00220   * @param  htim TIM Hall Sensor Interface handle
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00224 {
00225   /* Check the parameters */
00226   assert_param(IS_TIM_INSTANCE(htim->Instance));
00227
00228   htim->State = HAL_TIM_STATE_BUSY;
00229
00230   /* Disable the TIM Peripheral Clock */
00231   __HAL_TIM_DISABLE(htim);
00232
00233 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00234   if (htim->HallSensor_MspDeInitCallback == NULL)
00235   {
00236     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
00237   }
00238   /* DeInit the low level hardware */
00239   htim->HallSensor_MspDeInitCallback(htim);
00240 #else
00241   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00242   HAL_TIMEx_HallSensor_MspDeInit(htim);
00243 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00244
00245   /* Change TIM state */
00246   htim->State = HAL_TIM_STATE_RESET;
00247
00248   /* Release Lock */
00249   __HAL_UNLOCK(htim);
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  Initializes the TIM Hall Sensor MSP.
00256   * @param  htim TIM Hall Sensor Interface handle
00257   * @retval None
00258   */
00259 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00260 {
00261   /* Prevent unused argument(s) compilation warning */
00262   UNUSED(htim);
00263
00264   /* NOTE : This function should not be modified, when the callback is needed,
00265             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00266    */
00267 }
00268
00269 /**
00270   * @brief  DeInitializes TIM Hall Sensor MSP.
00271   * @param  htim TIM Hall Sensor Interface handle
00272   * @retval None
00273   */
00274 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00275 {
00276   /* Prevent unused argument(s) compilation warning */
00277   UNUSED(htim);
00278
00279   /* NOTE : This function should not be modified, when the callback is needed,
00280             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00281    */
00282 }
00283
00284 /**
00285   * @brief  Starts the TIM Hall Sensor Interface.
00286   * @param  htim TIM Hall Sensor Interface handle
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00290 {
00291   uint32_t tmpsmcr;
00292
00293   /* Check the parameters */
00294   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00295
00296   /* Enable the Input Capture channel 1
00297     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00298   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00299
00300   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00301   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00302   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00303   {
00304     __HAL_TIM_ENABLE(htim);
00305   }
00306
00307   /* Return function status */
00308   return HAL_OK;
00309 }
00310
00311 /**
00312   * @brief  Stops the TIM Hall sensor Interface.
00313   * @param  htim TIM Hall Sensor Interface handle
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00317 {
00318   /* Check the parameters */
00319   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00320
00321   /* Disable the Input Capture channels 1, 2 and 3
00322     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00323   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00324
00325   /* Disable the Peripheral */
00326   __HAL_TIM_DISABLE(htim);
00327
00328   /* Return function status */
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00334   * @param  htim TIM Hall Sensor Interface handle
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00338 {
00339   uint32_t tmpsmcr;
00340
00341   /* Check the parameters */
00342   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00343
00344   /* Enable the capture compare Interrupts 1 event */
00345   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00346
00347   /* Enable the Input Capture channel 1
00348     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00349   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00350
00351   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00352   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00353   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00354   {
00355     __HAL_TIM_ENABLE(htim);
00356   }
00357
00358   /* Return function status */
00359   return HAL_OK;
00360 }
00361
00362 /**
00363   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00364   * @param  htim TIM Hall Sensor Interface handle
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00368 {
00369   /* Check the parameters */
00370   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00371
00372   /* Disable the Input Capture channel 1
00373     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00374   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00375
00376   /* Disable the capture compare Interrupts event */
00377   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00378
00379   /* Disable the Peripheral */
00380   __HAL_TIM_DISABLE(htim);
00381
00382   /* Return function status */
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00388   * @param  htim TIM Hall Sensor Interface handle
00389   * @param  pData The destination Buffer address.
00390   * @param  Length The length of data to be transferred from TIM peripheral to memory.
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00394 {
00395   uint32_t tmpsmcr;
00396
00397   /* Check the parameters */
00398   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00399
00400   if (htim->State == HAL_TIM_STATE_BUSY)
00401   {
00402     return HAL_BUSY;
00403   }
00404   else if (htim->State == HAL_TIM_STATE_READY)
00405   {
00406     if (((uint32_t)pData == 0U) && (Length > 0U))
00407     {
00408       return HAL_ERROR;
00409     }
00410     else
00411     {
00412       htim->State = HAL_TIM_STATE_BUSY;
00413     }
00414   }
00415   else
00416   {
00417     /* nothing to do */
00418   }
00419   /* Enable the Input Capture channel 1
00420     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00421   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00422
00423   /* Set the DMA Input Capture 1 Callbacks */
00424   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00425   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
00426   /* Set the DMA error callback */
00427   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00428
00429   /* Enable the DMA stream for Capture 1*/
00430   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
00431   {
00432     return HAL_ERROR;
00433   }
00434   /* Enable the capture compare 1 Interrupt */
00435   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00436
00437   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00438   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00439   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00440   {
00441     __HAL_TIM_ENABLE(htim);
00442   }
00443
00444   /* Return function status */
00445   return HAL_OK;
00446 }
00447
00448 /**
00449   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00450   * @param  htim TIM Hall Sensor Interface handle
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00454 {
00455   /* Check the parameters */
00456   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00457
00458   /* Disable the Input Capture channel 1
00459     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00460   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00461
00462
00463   /* Disable the capture compare Interrupts 1 event */
00464   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00465
00466   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00467   /* Disable the Peripheral */
00468   __HAL_TIM_DISABLE(htim);
00469
00470   /* Return function status */
00471   return HAL_OK;
00472 }
00473
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00479   *  @brief   Timer Complementary Output Compare functions
00480   *
00481 @verbatim
00482   ==============================================================================
00483               ##### Timer Complementary Output Compare functions #####
00484   ==============================================================================
00485   [..]
00486     This section provides functions allowing to:
00487     (+) Start the Complementary Output Compare/PWM.
00488     (+) Stop the Complementary Output Compare/PWM.
00489     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00490     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00491     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00492     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00493
00494 @endverbatim
00495   * @{
00496   */
00497
00498 /**
00499   * @brief  Starts the TIM Output Compare signal generation on the complementary
00500   *         output.
00501   * @param  htim TIM Output Compare handle
00502   * @param  Channel TIM Channel to be enabled
00503   *          This parameter can be one of the following values:
00504   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00505   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00506   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00507   * @retval HAL status
00508   */
00509 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00510 {
00511   uint32_t tmpsmcr;
00512
00513   /* Check the parameters */
00514   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00515
00516   /* Enable the Capture compare channel N */
00517   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00518
00519   /* Enable the Main Output */
00520   __HAL_TIM_MOE_ENABLE(htim);
00521
00522   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00523   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00524   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00525   {
00526     __HAL_TIM_ENABLE(htim);
00527   }
00528
00529   /* Return function status */
00530   return HAL_OK;
00531 }
00532
00533 /**
00534   * @brief  Stops the TIM Output Compare signal generation on the complementary
00535   *         output.
00536   * @param  htim TIM handle
00537   * @param  Channel TIM Channel to be disabled
00538   *          This parameter can be one of the following values:
00539   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00540   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00541   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00542   * @retval HAL status
00543   */
00544 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00545 {
00546   /* Check the parameters */
00547   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00548
00549   /* Disable the Capture compare channel N */
00550   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00551
00552   /* Disable the Main Output */
00553   __HAL_TIM_MOE_DISABLE(htim);
00554
00555   /* Disable the Peripheral */
00556   __HAL_TIM_DISABLE(htim);
00557
00558   /* Return function status */
00559   return HAL_OK;
00560 }
00561
00562 /**
00563   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00564   *         on the complementary output.
00565   * @param  htim TIM OC handle
00566   * @param  Channel TIM Channel to be enabled
00567   *          This parameter can be one of the following values:
00568   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00569   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00570   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00571   * @retval HAL status
00572   */
00573 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00574 {
00575   uint32_t tmpsmcr;
00576
00577   /* Check the parameters */
00578   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00579
00580   switch (Channel)
00581   {
00582     case TIM_CHANNEL_1:
00583     {
00584       /* Enable the TIM Output Compare interrupt */
00585       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00586       break;
00587     }
00588
00589     case TIM_CHANNEL_2:
00590     {
00591       /* Enable the TIM Output Compare interrupt */
00592       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00593       break;
00594     }
00595
00596     case TIM_CHANNEL_3:
00597     {
00598       /* Enable the TIM Output Compare interrupt */
00599       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00600       break;
00601     }
00602
00603
00604     default:
00605       break;
00606   }
00607
00608   /* Enable the TIM Break interrupt */
00609   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00610
00611   /* Enable the Capture compare channel N */
00612   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00613
00614   /* Enable the Main Output */
00615   __HAL_TIM_MOE_ENABLE(htim);
00616
00617   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00618   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00619   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00620   {
00621     __HAL_TIM_ENABLE(htim);
00622   }
00623
00624   /* Return function status */
00625   return HAL_OK;
00626 }
00627
00628 /**
00629   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00630   *         on the complementary output.
00631   * @param  htim TIM Output Compare handle
00632   * @param  Channel TIM Channel to be disabled
00633   *          This parameter can be one of the following values:
00634   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00635   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00636   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00637   * @retval HAL status
00638   */
00639 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00640 {
00641   uint32_t tmpccer;
00642   /* Check the parameters */
00643   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00644
00645   switch (Channel)
00646   {
00647     case TIM_CHANNEL_1:
00648     {
00649       /* Disable the TIM Output Compare interrupt */
00650       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00651       break;
00652     }
00653
00654     case TIM_CHANNEL_2:
00655     {
00656       /* Disable the TIM Output Compare interrupt */
00657       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00658       break;
00659     }
00660
00661     case TIM_CHANNEL_3:
00662     {
00663       /* Disable the TIM Output Compare interrupt */
00664       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00665       break;
00666     }
00667
00668     default:
00669       break;
00670   }
00671
00672   /* Disable the Capture compare channel N */
00673   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00674
00675   /* Disable the TIM Break interrupt (only if no more channel is active) */
00676   tmpccer = htim->Instance->CCER;
00677   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
00678   {
00679     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00680   }
00681
00682   /* Disable the Main Output */
00683   __HAL_TIM_MOE_DISABLE(htim);
00684
00685   /* Disable the Peripheral */
00686   __HAL_TIM_DISABLE(htim);
00687
00688   /* Return function status */
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00694   *         on the complementary output.
00695   * @param  htim TIM Output Compare handle
00696   * @param  Channel TIM Channel to be enabled
00697   *          This parameter can be one of the following values:
00698   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00699   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00700   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00701   * @param  pData The source Buffer address.
00702   * @param  Length The length of data to be transferred from memory to TIM peripheral
00703   * @retval HAL status
00704   */
00705 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00706 {
00707   uint32_t tmpsmcr;
00708
00709   /* Check the parameters */
00710   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00711
00712   if (htim->State == HAL_TIM_STATE_BUSY)
00713   {
00714     return HAL_BUSY;
00715   }
00716   else if (htim->State == HAL_TIM_STATE_READY)
00717   {
00718     if (((uint32_t)pData == 0U) && (Length > 0U))
00719     {
00720       return HAL_ERROR;
00721     }
00722     else
00723     {
00724       htim->State = HAL_TIM_STATE_BUSY;
00725     }
00726   }
00727   else
00728   {
00729     /* nothing to do  */
00730   }
00731
00732   switch (Channel)
00733   {
00734     case TIM_CHANNEL_1:
00735     {
00736       /* Set the DMA compare callbacks */
00737       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00738       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00739
00740       /* Set the DMA error callback */
00741       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00742
00743       /* Enable the DMA stream */
00744       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
00745       {
00746         return HAL_ERROR;
00747       }
00748       /* Enable the TIM Output Compare DMA request */
00749       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00750       break;
00751     }
00752
00753     case TIM_CHANNEL_2:
00754     {
00755       /* Set the DMA compare callbacks */
00756       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00757       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00758
00759       /* Set the DMA error callback */
00760       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00761
00762       /* Enable the DMA stream */
00763       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
00764       {
00765         return HAL_ERROR;
00766       }
00767       /* Enable the TIM Output Compare DMA request */
00768       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00769       break;
00770     }
00771
00772     case TIM_CHANNEL_3:
00773     {
00774       /* Set the DMA compare callbacks */
00775       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00776       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00777
00778       /* Set the DMA error callback */
00779       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00780
00781       /* Enable the DMA stream */
00782       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
00783       {
00784         return HAL_ERROR;
00785       }
00786       /* Enable the TIM Output Compare DMA request */
00787       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00788       break;
00789     }
00790
00791     default:
00792       break;
00793   }
00794
00795   /* Enable the Capture compare channel N */
00796   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00797
00798   /* Enable the Main Output */
00799   __HAL_TIM_MOE_ENABLE(htim);
00800
00801   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00802   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00803   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00804   {
00805     __HAL_TIM_ENABLE(htim);
00806   }
00807
00808   /* Return function status */
00809   return HAL_OK;
00810 }
00811
00812 /**
00813   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00814   *         on the complementary output.
00815   * @param  htim TIM Output Compare handle
00816   * @param  Channel TIM Channel to be disabled
00817   *          This parameter can be one of the following values:
00818   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00819   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00820   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00821   * @retval HAL status
00822   */
00823 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00824 {
00825   /* Check the parameters */
00826   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00827
00828   switch (Channel)
00829   {
00830     case TIM_CHANNEL_1:
00831     {
00832       /* Disable the TIM Output Compare DMA request */
00833       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00834       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00835       break;
00836     }
00837
00838     case TIM_CHANNEL_2:
00839     {
00840       /* Disable the TIM Output Compare DMA request */
00841       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00842       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
00843       break;
00844     }
00845
00846     case TIM_CHANNEL_3:
00847     {
00848       /* Disable the TIM Output Compare DMA request */
00849       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00850       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
00851       break;
00852     }
00853
00854     default:
00855       break;
00856   }
00857
00858   /* Disable the Capture compare channel N */
00859   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00860
00861   /* Disable the Main Output */
00862   __HAL_TIM_MOE_DISABLE(htim);
00863
00864   /* Disable the Peripheral */
00865   __HAL_TIM_DISABLE(htim);
00866
00867   /* Change the htim state */
00868   htim->State = HAL_TIM_STATE_READY;
00869
00870   /* Return function status */
00871   return HAL_OK;
00872 }
00873
00874 /**
00875   * @}
00876   */
00877
00878 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00879   * @brief    Timer Complementary PWM functions
00880   *
00881 @verbatim
00882   ==============================================================================
00883                  ##### Timer Complementary PWM functions #####
00884   ==============================================================================
00885   [..]
00886     This section provides functions allowing to:
00887     (+) Start the Complementary PWM.
00888     (+) Stop the Complementary PWM.
00889     (+) Start the Complementary PWM and enable interrupts.
00890     (+) Stop the Complementary PWM and disable interrupts.
00891     (+) Start the Complementary PWM and enable DMA transfers.
00892     (+) Stop the Complementary PWM and disable DMA transfers.
00893     (+) Start the Complementary Input Capture measurement.
00894     (+) Stop the Complementary Input Capture.
00895     (+) Start the Complementary Input Capture and enable interrupts.
00896     (+) Stop the Complementary Input Capture and disable interrupts.
00897     (+) Start the Complementary Input Capture and enable DMA transfers.
00898     (+) Stop the Complementary Input Capture and disable DMA transfers.
00899     (+) Start the Complementary One Pulse generation.
00900     (+) Stop the Complementary One Pulse.
00901     (+) Start the Complementary One Pulse and enable interrupts.
00902     (+) Stop the Complementary One Pulse and disable interrupts.
00903
00904 @endverbatim
00905   * @{
00906   */
00907
00908 /**
00909   * @brief  Starts the PWM signal generation on the complementary output.
00910   * @param  htim TIM handle
00911   * @param  Channel TIM Channel to be enabled
00912   *          This parameter can be one of the following values:
00913   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00914   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00915   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00916   * @retval HAL status
00917   */
00918 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00919 {
00920   uint32_t tmpsmcr;
00921
00922   /* Check the parameters */
00923   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00924
00925   /* Enable the complementary PWM output  */
00926   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00927
00928   /* Enable the Main Output */
00929   __HAL_TIM_MOE_ENABLE(htim);
00930
00931   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00932   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00933   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00934   {
00935     __HAL_TIM_ENABLE(htim);
00936   }
00937
00938   /* Return function status */
00939   return HAL_OK;
00940 }
00941
00942 /**
00943   * @brief  Stops the PWM signal generation on the complementary output.
00944   * @param  htim TIM handle
00945   * @param  Channel TIM Channel to be disabled
00946   *          This parameter can be one of the following values:
00947   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00948   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00949   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00953 {
00954   /* Check the parameters */
00955   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00956
00957   /* Disable the complementary PWM output  */
00958   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00959
00960   /* Disable the Main Output */
00961   __HAL_TIM_MOE_DISABLE(htim);
00962
00963   /* Disable the Peripheral */
00964   __HAL_TIM_DISABLE(htim);
00965
00966   /* Return function status */
00967   return HAL_OK;
00968 }
00969
00970 /**
00971   * @brief  Starts the PWM signal generation in interrupt mode on the
00972   *         complementary output.
00973   * @param  htim TIM handle
00974   * @param  Channel TIM Channel to be disabled
00975   *          This parameter can be one of the following values:
00976   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00977   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00978   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00982 {
00983   uint32_t tmpsmcr;
00984
00985   /* Check the parameters */
00986   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00987
00988   switch (Channel)
00989   {
00990     case TIM_CHANNEL_1:
00991     {
00992       /* Enable the TIM Capture/Compare 1 interrupt */
00993       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00994       break;
00995     }
00996
00997     case TIM_CHANNEL_2:
00998     {
00999       /* Enable the TIM Capture/Compare 2 interrupt */
01000       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01001       break;
01002     }
01003
01004     case TIM_CHANNEL_3:
01005     {
01006       /* Enable the TIM Capture/Compare 3 interrupt */
01007       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01008       break;
01009     }
01010
01011     default:
01012       break;
01013   }
01014
01015   /* Enable the TIM Break interrupt */
01016   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01017
01018   /* Enable the complementary PWM output  */
01019   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01020
01021   /* Enable the Main Output */
01022   __HAL_TIM_MOE_ENABLE(htim);
01023
01024   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01025   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01026   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01027   {
01028     __HAL_TIM_ENABLE(htim);
01029   }
01030
01031   /* Return function status */
01032   return HAL_OK;
01033 }
01034
01035 /**
01036   * @brief  Stops the PWM signal generation in interrupt mode on the
01037   *         complementary output.
01038   * @param  htim TIM handle
01039   * @param  Channel TIM Channel to be disabled
01040   *          This parameter can be one of the following values:
01041   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01042   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01043   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01044   * @retval HAL status
01045   */
01046 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01047 {
01048   uint32_t tmpccer;
01049
01050   /* Check the parameters */
01051   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01052
01053   switch (Channel)
01054   {
01055     case TIM_CHANNEL_1:
01056     {
01057       /* Disable the TIM Capture/Compare 1 interrupt */
01058       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01059       break;
01060     }
01061
01062     case TIM_CHANNEL_2:
01063     {
01064       /* Disable the TIM Capture/Compare 2 interrupt */
01065       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01066       break;
01067     }
01068
01069     case TIM_CHANNEL_3:
01070     {
01071       /* Disable the TIM Capture/Compare 3 interrupt */
01072       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01073       break;
01074     }
01075
01076     default:
01077       break;
01078   }
01079
01080   /* Disable the complementary PWM output  */
01081   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01082
01083   /* Disable the TIM Break interrupt (only if no more channel is active) */
01084   tmpccer = htim->Instance->CCER;
01085   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
01086   {
01087     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01088   }
01089
01090   /* Disable the Main Output */
01091   __HAL_TIM_MOE_DISABLE(htim);
01092
01093   /* Disable the Peripheral */
01094   __HAL_TIM_DISABLE(htim);
01095
01096   /* Return function status */
01097   return HAL_OK;
01098 }
01099
01100 /**
01101   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01102   *         complementary output
01103   * @param  htim TIM handle
01104   * @param  Channel TIM Channel to be enabled
01105   *          This parameter can be one of the following values:
01106   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01107   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01108   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01109   * @param  pData The source Buffer address.
01110   * @param  Length The length of data to be transferred from memory to TIM peripheral
01111   * @retval HAL status
01112   */
01113 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01114 {
01115   uint32_t tmpsmcr;
01116
01117   /* Check the parameters */
01118   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01119
01120   if (htim->State == HAL_TIM_STATE_BUSY)
01121   {
01122     return HAL_BUSY;
01123   }
01124   else if (htim->State == HAL_TIM_STATE_READY)
01125   {
01126     if (((uint32_t)pData == 0U) && (Length > 0U))
01127     {
01128       return HAL_ERROR;
01129     }
01130     else
01131     {
01132       htim->State = HAL_TIM_STATE_BUSY;
01133     }
01134   }
01135   else
01136   {
01137     /* nothing to do */
01138   }
01139   switch (Channel)
01140   {
01141     case TIM_CHANNEL_1:
01142     {
01143       /* Set the DMA compare callbacks */
01144       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01145       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01146
01147       /* Set the DMA error callback */
01148       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01149
01150       /* Enable the DMA stream */
01151       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
01152       {
01153         return HAL_ERROR;
01154       }
01155       /* Enable the TIM Capture/Compare 1 DMA request */
01156       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01157       break;
01158     }
01159
01160     case TIM_CHANNEL_2:
01161     {
01162       /* Set the DMA compare callbacks */
01163       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01164       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01165
01166       /* Set the DMA error callback */
01167       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01168
01169       /* Enable the DMA stream */
01170       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
01171       {
01172         return HAL_ERROR;
01173       }
01174       /* Enable the TIM Capture/Compare 2 DMA request */
01175       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01176       break;
01177     }
01178
01179     case TIM_CHANNEL_3:
01180     {
01181       /* Set the DMA compare callbacks */
01182       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01183       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01184
01185       /* Set the DMA error callback */
01186       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01187
01188       /* Enable the DMA stream */
01189       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01190       {
01191         return HAL_ERROR;
01192       }
01193       /* Enable the TIM Capture/Compare 3 DMA request */
01194       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01195       break;
01196     }
01197
01198     default:
01199       break;
01200   }
01201
01202   /* Enable the complementary PWM output  */
01203   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01204
01205   /* Enable the Main Output */
01206   __HAL_TIM_MOE_ENABLE(htim);
01207
01208   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01209   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01210   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01211   {
01212     __HAL_TIM_ENABLE(htim);
01213   }
01214
01215   /* Return function status */
01216   return HAL_OK;
01217 }
01218
01219 /**
01220   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01221   *         output
01222   * @param  htim TIM handle
01223   * @param  Channel TIM Channel to be disabled
01224   *          This parameter can be one of the following values:
01225   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01226   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01227   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01228   * @retval HAL status
01229   */
01230 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01231 {
01232   /* Check the parameters */
01233   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01234
01235   switch (Channel)
01236   {
01237     case TIM_CHANNEL_1:
01238     {
01239       /* Disable the TIM Capture/Compare 1 DMA request */
01240       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01241       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01242       break;
01243     }
01244
01245     case TIM_CHANNEL_2:
01246     {
01247       /* Disable the TIM Capture/Compare 2 DMA request */
01248       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01249       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01250       break;
01251     }
01252
01253     case TIM_CHANNEL_3:
01254     {
01255       /* Disable the TIM Capture/Compare 3 DMA request */
01256       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01257       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01258       break;
01259     }
01260
01261     default:
01262       break;
01263   }
01264
01265   /* Disable the complementary PWM output */
01266   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01267
01268   /* Disable the Main Output */
01269   __HAL_TIM_MOE_DISABLE(htim);
01270
01271   /* Disable the Peripheral */
01272   __HAL_TIM_DISABLE(htim);
01273
01274   /* Change the htim state */
01275   htim->State = HAL_TIM_STATE_READY;
01276
01277   /* Return function status */
01278   return HAL_OK;
01279 }
01280
01281 /**
01282   * @}
01283   */
01284
01285 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01286   * @brief    Timer Complementary One Pulse functions
01287   *
01288 @verbatim
01289   ==============================================================================
01290                 ##### Timer Complementary One Pulse functions #####
01291   ==============================================================================
01292   [..]
01293     This section provides functions allowing to:
01294     (+) Start the Complementary One Pulse generation.
01295     (+) Stop the Complementary One Pulse.
01296     (+) Start the Complementary One Pulse and enable interrupts.
01297     (+) Stop the Complementary One Pulse and disable interrupts.
01298
01299 @endverbatim
01300   * @{
01301   */
01302
01303 /**
01304   * @brief  Starts the TIM One Pulse signal generation on the complementary
01305   *         output.
01306   * @param  htim TIM One Pulse handle
01307   * @param  OutputChannel TIM Channel to be enabled
01308   *          This parameter can be one of the following values:
01309   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01310   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01311   * @retval HAL status
01312   */
01313 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01314 {
01315   /* Check the parameters */
01316   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01317
01318   /* Enable the complementary One Pulse output */
01319   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01320
01321   /* Enable the Main Output */
01322   __HAL_TIM_MOE_ENABLE(htim);
01323
01324   /* Return function status */
01325   return HAL_OK;
01326 }
01327
01328 /**
01329   * @brief  Stops the TIM One Pulse signal generation on the complementary
01330   *         output.
01331   * @param  htim TIM One Pulse handle
01332   * @param  OutputChannel TIM Channel to be disabled
01333   *          This parameter can be one of the following values:
01334   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01335   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01336   * @retval HAL status
01337   */
01338 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01339 {
01340
01341   /* Check the parameters */
01342   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01343
01344   /* Disable the complementary One Pulse output */
01345   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01346
01347   /* Disable the Main Output */
01348   __HAL_TIM_MOE_DISABLE(htim);
01349
01350   /* Disable the Peripheral */
01351   __HAL_TIM_DISABLE(htim);
01352
01353   /* Return function status */
01354   return HAL_OK;
01355 }
01356
01357 /**
01358   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01359   *         complementary channel.
01360   * @param  htim TIM One Pulse handle
01361   * @param  OutputChannel TIM Channel to be enabled
01362   *          This parameter can be one of the following values:
01363   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01364   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01365   * @retval HAL status
01366   */
01367 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01368 {
01369   /* Check the parameters */
01370   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01371
01372   /* Enable the TIM Capture/Compare 1 interrupt */
01373   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01374
01375   /* Enable the TIM Capture/Compare 2 interrupt */
01376   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01377
01378   /* Enable the complementary One Pulse output */
01379   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01380
01381   /* Enable the Main Output */
01382   __HAL_TIM_MOE_ENABLE(htim);
01383
01384   /* Return function status */
01385   return HAL_OK;
01386 }
01387
01388 /**
01389   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01390   *         complementary channel.
01391   * @param  htim TIM One Pulse handle
01392   * @param  OutputChannel TIM Channel to be disabled
01393   *          This parameter can be one of the following values:
01394   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01395   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01396   * @retval HAL status
01397   */
01398 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01399 {
01400   /* Check the parameters */
01401   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01402
01403   /* Disable the TIM Capture/Compare 1 interrupt */
01404   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01405
01406   /* Disable the TIM Capture/Compare 2 interrupt */
01407   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01408
01409   /* Disable the complementary One Pulse output */
01410   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01411
01412   /* Disable the Main Output */
01413   __HAL_TIM_MOE_DISABLE(htim);
01414
01415   /* Disable the Peripheral */
01416   __HAL_TIM_DISABLE(htim);
01417
01418   /* Return function status */
01419   return HAL_OK;
01420 }
01421
01422 /**
01423   * @}
01424   */
01425
01426 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01427   * @brief    Peripheral Control functions
01428   *
01429 @verbatim
01430   ==============================================================================
01431                     ##### Peripheral Control functions #####
01432   ==============================================================================
01433   [..]
01434     This section provides functions allowing to:
01435       (+) Configure the commutation event in case of use of the Hall sensor interface.
01436       (+) Configure Output channels for OC and PWM mode.
01437
01438       (+) Configure Complementary channels, break features and dead time.
01439       (+) Configure Master synchronization.
01440       (+) Configure timer remapping capabilities.
01441       (+) Select timer input source.
01442       (+) Enable or disable channel grouping.
01443
01444 @endverbatim
01445   * @{
01446   */
01447
01448 /**
01449   * @brief  Configure the TIM commutation event sequence.
01450   * @note  This function is mandatory to use the commutation event in order to
01451   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01452   *        the typical use of this feature is with the use of another Timer(interface Timer)
01453   *        configured in Hall sensor interface, this interface Timer will generate the
01454   *        commutation at its TRGO output (connected to Timer used in this function) each time
01455   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01456   * @param  htim TIM handle
01457   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01458   *          This parameter can be one of the following values:
01459   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01460   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01461   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01462   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01463   *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
01464   *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
01465   *            @arg TIM_TS_NONE: No trigger is needed
01466   * @param  CommutationSource the Commutation Event source
01467   *          This parameter can be one of the following values:
01468   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01469   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01470   * @retval HAL status
01471   */
01472 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01473                                               uint32_t  CommutationSource)
01474 {
01475   /* Check the parameters */
01476   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01477   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01478
01479   __HAL_LOCK(htim);
01480
01481   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01482       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01483       (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
01484   {
01485     /* Select the Input trigger */
01486     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01487     htim->Instance->SMCR |= InputTrigger;
01488   }
01489
01490   /* Select the Capture Compare preload feature */
01491   htim->Instance->CR2 |= TIM_CR2_CCPC;
01492   /* Select the Commutation event source */
01493   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01494   htim->Instance->CR2 |= CommutationSource;
01495
01496   /* Disable Commutation Interrupt */
01497   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01498
01499   /* Disable Commutation DMA request */
01500   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01501
01502   __HAL_UNLOCK(htim);
01503
01504   return HAL_OK;
01505 }
01506
01507 /**
01508   * @brief  Configure the TIM commutation event sequence with interrupt.
01509   * @note  This function is mandatory to use the commutation event in order to
01510   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01511   *        the typical use of this feature is with the use of another Timer(interface Timer)
01512   *        configured in Hall sensor interface, this interface Timer will generate the
01513   *        commutation at its TRGO output (connected to Timer used in this function) each time
01514   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01515   * @param  htim TIM handle
01516   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01517   *          This parameter can be one of the following values:
01518   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01519   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01520   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01521   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01522   *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
01523   *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
01524   *            @arg TIM_TS_NONE: No trigger is needed
01525   * @param  CommutationSource the Commutation Event source
01526   *          This parameter can be one of the following values:
01527   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01528   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01529   * @retval HAL status
01530   */
01531 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01532                                                  uint32_t  CommutationSource)
01533 {
01534   /* Check the parameters */
01535   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01536   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01537
01538   __HAL_LOCK(htim);
01539
01540   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01541       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01542       (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
01543   {
01544     /* Select the Input trigger */
01545     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01546     htim->Instance->SMCR |= InputTrigger;
01547   }
01548
01549   /* Select the Capture Compare preload feature */
01550   htim->Instance->CR2 |= TIM_CR2_CCPC;
01551   /* Select the Commutation event source */
01552   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01553   htim->Instance->CR2 |= CommutationSource;
01554
01555   /* Disable Commutation DMA request */
01556   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01557
01558   /* Enable the Commutation Interrupt */
01559   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01560
01561   __HAL_UNLOCK(htim);
01562
01563   return HAL_OK;
01564 }
01565
01566 /**
01567   * @brief  Configure the TIM commutation event sequence with DMA.
01568   * @note  This function is mandatory to use the commutation event in order to
01569   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01570   *        the typical use of this feature is with the use of another Timer(interface Timer)
01571   *        configured in Hall sensor interface, this interface Timer will generate the
01572   *        commutation at its TRGO output (connected to Timer used in this function) each time
01573   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01574   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
01575   * @param  htim TIM handle
01576   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01577   *          This parameter can be one of the following values:
01578   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01579   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01580   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01581   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01582   *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
01583   *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
01584   *            @arg TIM_TS_NONE: No trigger is needed
01585   *
01586   *         (*)  Value not defined in all devices.
01587   *
01588   * @param  CommutationSource the Commutation Event source
01589   *          This parameter can be one of the following values:
01590   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01591   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01592   * @retval HAL status
01593   */
01594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01595                                                   uint32_t  CommutationSource)
01596 {
01597   /* Check the parameters */
01598   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01599   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01600
01601   __HAL_LOCK(htim);
01602
01603   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01604       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01605       (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
01606   {
01607     /* Select the Input trigger */
01608     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01609     htim->Instance->SMCR |= InputTrigger;
01610   }
01611
01612   /* Select the Capture Compare preload feature */
01613   htim->Instance->CR2 |= TIM_CR2_CCPC;
01614   /* Select the Commutation event source */
01615   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01616   htim->Instance->CR2 |= CommutationSource;
01617
01618   /* Enable the Commutation DMA Request */
01619   /* Set the DMA Commutation Callback */
01620   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01621   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
01622   /* Set the DMA error callback */
01623   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01624
01625   /* Disable Commutation Interrupt */
01626   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01627
01628   /* Enable the Commutation DMA Request */
01629   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01630
01631   __HAL_UNLOCK(htim);
01632
01633   return HAL_OK;
01634 }
01635
01636 /**
01637   * @brief  Configures the TIM in master mode.
01638   * @param  htim TIM handle.
01639   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
01640   *         contains the selected trigger output (TRGO) and the Master/Slave
01641   *         mode.
01642   * @retval HAL status
01643   */
01644 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01645                                                         TIM_MasterConfigTypeDef *sMasterConfig)
01646 {
01647   uint32_t tmpcr2;
01648   uint32_t tmpsmcr;
01649
01650   /* Check the parameters */
01651   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01652   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01653   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01654
01655   /* Check input state */
01656   __HAL_LOCK(htim);
01657
01658   /* Change the handler state */
01659   htim->State = HAL_TIM_STATE_BUSY;
01660
01661   /* Get the TIMx CR2 register value */
01662   tmpcr2 = htim->Instance->CR2;
01663
01664   /* Get the TIMx SMCR register value */
01665   tmpsmcr = htim->Instance->SMCR;
01666
01667   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
01668   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01669   {
01670     /* Check the parameters */
01671     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01672
01673     /* Clear the MMS2 bits */
01674     tmpcr2 &= ~TIM_CR2_MMS2;
01675     /* Select the TRGO2 source*/
01676     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01677   }
01678
01679   /* Reset the MMS Bits */
01680   tmpcr2 &= ~TIM_CR2_MMS;
01681   /* Select the TRGO source */
01682   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01683
01684   /* Update TIMx CR2 */
01685   htim->Instance->CR2 = tmpcr2;
01686
01687   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01688   {
01689     /* Reset the MSM Bit */
01690     tmpsmcr &= ~TIM_SMCR_MSM;
01691     /* Set master mode */
01692     tmpsmcr |= sMasterConfig->MasterSlaveMode;
01693
01694     /* Update TIMx SMCR */
01695     htim->Instance->SMCR = tmpsmcr;
01696   }
01697
01698   /* Change the htim state */
01699   htim->State = HAL_TIM_STATE_READY;
01700
01701   __HAL_UNLOCK(htim);
01702
01703   return HAL_OK;
01704 }
01705
01706 /**
01707   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01708   *         and the AOE(automatic output enable).
01709   * @param  htim TIM handle
01710   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01711   *         contains the BDTR Register configuration  information for the TIM peripheral.
01712   * @note   Interrupts can be generated when an active level is detected on the
01713   *         break input, the break 2 input or the system break input. Break
01714   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
01715   * @retval HAL status
01716   */
01717 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01718                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
01719 {
01720   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
01721   uint32_t tmpbdtr = 0U;
01722
01723   /* Check the parameters */
01724   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01725   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01726   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01727   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01728   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01729   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01730   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01731   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
01732   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01733
01734   /* Check input state */
01735   __HAL_LOCK(htim);
01736
01737   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01738      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01739
01740   /* Set the BDTR bits */
01741   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
01742   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
01743   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
01744   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
01745   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
01746   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
01747   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
01748   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
01749
01750   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
01751   {
01752     /* Check the parameters */
01753     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
01754     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
01755     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
01756
01757     /* Set the BREAK2 input related BDTR bits */
01758     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
01759     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
01760     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
01761   }
01762
01763   /* Set TIMx_BDTR */
01764   htim->Instance->BDTR = tmpbdtr;
01765
01766   __HAL_UNLOCK(htim);
01767
01768   return HAL_OK;
01769 }
01770 #if defined(TIM_BREAK_INPUT_SUPPORT)
01771
01772 /**
01773   * @brief  Configures the break input source.
01774   * @param  htim TIM handle.
01775   * @param  BreakInput Break input to configure
01776   *          This parameter can be one of the following values:
01777   *            @arg TIM_BREAKINPUT_BRK: Timer break input
01778   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
01779   * @param  sBreakInputConfig Break input source configuration
01780   * @retval HAL status
01781   */
01782 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
01783                                              uint32_t BreakInput,
01784                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
01785
01786 {
01787   uint32_t tmporx;
01788   uint32_t bkin_enable_mask;
01789   uint32_t bkin_polarity_mask;
01790   uint32_t bkin_enable_bitpos;
01791   uint32_t bkin_polarity_bitpos;
01792
01793   /* Check the parameters */
01794   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01795   assert_param(IS_TIM_BREAKINPUT(BreakInput));
01796   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
01797   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
01798   if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01799   {
01800     assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01801   }
01802
01803   /* Check input state */
01804   __HAL_LOCK(htim);
01805
01806   switch (sBreakInputConfig->Source)
01807   {
01808     case TIM_BREAKINPUTSOURCE_BKIN:
01809     {
01810       bkin_enable_mask = TIM1_AF1_BKINE;
01811       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
01812       bkin_polarity_mask = TIM1_AF1_BKINP;
01813       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
01814       break;
01815     }
01816     case TIM_BREAKINPUTSOURCE_COMP1:
01817     {
01818       bkin_enable_mask = TIM1_AF1_BKCMP1E;
01819       bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
01820       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
01821       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
01822       break;
01823     }
01824     case TIM_BREAKINPUTSOURCE_COMP2:
01825     {
01826       bkin_enable_mask = TIM1_AF1_BKCMP2E;
01827       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
01828       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
01829       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
01830       break;
01831     }
01832     case TIM_BREAKINPUTSOURCE_DFSDM1:
01833     {
01834       bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
01835       bkin_enable_bitpos = 8U;
01836       bkin_polarity_mask = 0U;
01837       bkin_polarity_bitpos = 0U;
01838       break;
01839     }
01840
01841     default:
01842     {
01843       bkin_enable_mask = 0U;
01844       bkin_polarity_mask = 0U;
01845       bkin_enable_bitpos = 0U;
01846       bkin_polarity_bitpos = 0U;
01847       break;
01848     }
01849   }
01850
01851   switch (BreakInput)
01852   {
01853     case TIM_BREAKINPUT_BRK:
01854     {
01855       /* Get the TIMx_AF1 register value */
01856       tmporx = htim->Instance->AF1;
01857
01858       /* Enable the break input */
01859       tmporx &= ~bkin_enable_mask;
01860       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01861
01862       /* Set the break input polarity */
01863       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01864       {
01865         tmporx &= ~bkin_polarity_mask;
01866         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01867       }
01868
01869       /* Set TIMx_AF1 */
01870       htim->Instance->AF1 = tmporx;
01871       break;
01872     }
01873     case TIM_BREAKINPUT_BRK2:
01874     {
01875       /* Get the TIMx_AF2 register value */
01876       tmporx = htim->Instance->AF2;
01877
01878       /* Enable the break input */
01879       tmporx &= ~bkin_enable_mask;
01880       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01881
01882       /* Set the break input polarity */
01883       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01884       {
01885         tmporx &= ~bkin_polarity_mask;
01886         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01887       }
01888
01889       /* Set TIMx_AF2 */
01890       htim->Instance->AF2 = tmporx;
01891       break;
01892     }
01893     default:
01894       break;
01895   }
01896
01897   __HAL_UNLOCK(htim);
01898
01899   return HAL_OK;
01900 }
01901 #endif /*TIM_BREAK_INPUT_SUPPORT */
01902
01903 /**
01904   * @brief  Configures the TIMx Remapping input capabilities.
01905   * @param  htim TIM handle.
01906   * @param  Remap specifies the TIM remapping source.
01907   *         For TIM1, the parameter is one of the following values:
01908   *            @arg TIM_TIM1_ETR_GPIO:               TIM1_ETR is connected to GPIO
01909   *            @arg TIM_TIM1_ETR_COMP1:              TIM1_ETR is connected to COMP1 output
01910   *            @arg TIM_TIM1_ETR_COMP2:              TIM1_ETR is connected to COMP2 output
01911   *            @arg TIM_TIM1_ETR_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
01912   *            @arg TIM_TIM1_ETR_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
01913   *            @arg TIM_TIM1_ETR_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
01914   *            @arg TIM_TIM1_ETR_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
01915   *            @arg TIM_TIM1_ETR_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
01916   *            @arg TIM_TIM1_ETR_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
01917   *
01918   *         For TIM2, the parameter is one of the following values:
01919   *            @arg TIM_TIM2_ETR_GPIO:               TIM2_ETR is connected to GPIO
01920   *            @arg TIM_TIM2_ETR_COMP1:              TIM2_ETR is connected to COMP1 output
01921   *            @arg TIM_TIM2_ETR_COMP2:              TIM2_ETR is connected to COMP2 output
01922   *            @arg TIM_TIM2_ETR_LSE:                TIM2_ETR is connected to LSE
01923   *            @arg TIM_TIM2_ETR_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
01924   *            @arg TIM_TIM2_ETR_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
01925   *
01926   *         For TIM3, the parameter is one of the following values:
01927   *            @arg TIM_TIM3_ETR_GPIO:               TIM3_ETR is connected to GPIO
01928   *            @arg TIM_TIM3_ETR_COMP1:              TIM3_ETR is connected to COMP1 output
01929   *
01930   *         For TIM5, the parameter is one of the following values:
01931   *            @arg TIM_TIM5_ETR_GPIO:               TIM5_ETR is connected to GPIO
01932   *            @arg TIM_TIM5_ETR_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
01933   *            @arg TIM_TIM5_ETR_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
01934   *            @arg TIM_TIM5_ETR_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
01935   *            @arg TIM_TIM5_ETR_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
01936   *
01937   *         For TIM8, the parameter is one of the following values:
01938   *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
01939   *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
01940   *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
01941   *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
01942   *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
01943   *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
01944   *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
01945   *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
01946   *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
01947   *
01948   *         For TIM23, the parameter is one of the following values: (*)
01949   *            @arg TIM_TIM23_ETR_GPIO               TIM23_ETR is connected to GPIO
01950   *            @arg TIM_TIM23_ETR_COMP1              TIM23_ETR is connected to COMP1 output
01951   *            @arg TIM_TIM23_ETR_COMP2              TIM23_ETR is connected to COMP2 output
01952   *
01953   *         For TIM24, the parameter is one of the following values: (*)
01954   *           @arg TIM_TIM24_ETR_GPIO                TIM24_ETR is connected to GPIO
01955   *           @arg TIM_TIM24_ETR_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
01956   *           @arg TIM_TIM24_ETR_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
01957   *           @arg TIM_TIM24_ETR_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
01958   *           @arg TIM_TIM24_ETR_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
01959   *
01960   *         (*)  Value not defined in all devices.
01961   *
01962   * @retval HAL status
01963   */
01964 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
01965 {
01966   /* Check parameters */
01967   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
01968   assert_param(IS_TIM_REMAP(Remap));
01969
01970   __HAL_LOCK(htim);
01971
01972   MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
01973
01974   __HAL_UNLOCK(htim);
01975
01976   return HAL_OK;
01977 }
01978
01979 /**
01980   * @brief  Select the timer input source
01981   * @param  htim TIM handle.
01982   * @param  Channel specifies the TIM Channel
01983   *          This parameter can be one of the following values:
01984   *            @arg TIM_CHANNEL_1: TI1 input channel
01985   *            @arg TIM_CHANNEL_2: TI2 input channel
01986   *            @arg TIM_CHANNEL_3: TIM Channel 3
01987   *            @arg TIM_CHANNEL_4: TIM Channel 4
01988   * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
01989   *         For TIM1, the parameter is one of the following values:
01990   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01991   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01992   *
01993   *         For TIM2, the parameter is one of the following values:
01994   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01995   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01996   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01997   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01998   *
01999   *         For TIM3, the parameter is one of the following values:
02000   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
02001   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
02002   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
02003   *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
02004   *
02005   *         For TIM5, the parameter is one of the following values:
02006   *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
02007   *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
02008   *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
02009   *
02010   *         For TIM8, the parameter is one of the following values:
02011   *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
02012   *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
02013   *
02014   *         For TIM12, the parameter can have the following values: (*)
02015   *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
02016   *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
02017   *
02018   *         For TIM15, the parameter is one of the following values:
02019   *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
02020   *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
02021   *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
02022   *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
02023   *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
02024   *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
02025   *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
02026   *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
02027   *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
02028   *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
02029   *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
02030   *
02031   *         For TIM16, the parameter can have the following values:
02032   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
02033   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
02034   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
02035   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
02036   *
02037   *         For TIM17, the parameter can have the following values:
02038   *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
02039   *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
02040   *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
02041   *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
02042   *
02043   *         For TIM23, the parameter can have the following values: (*)
02044   *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
02045   *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
02046   *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
02047   *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
02048   *
02049   *         For TIM24, the parameter can have the following values: (*)
02050   *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
02051   *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
02052   *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
02053   *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
02054   *
02055   *         (*)  Value not defined in all devices. \n
02056   * @retval HAL status
02057   */
02058 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
02059 {
02060   HAL_StatusTypeDef status = HAL_OK;
02061
02062   /* Check parameters */
02063   assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
02064   assert_param(IS_TIM_TISEL(TISelection));
02065
02066   __HAL_LOCK(htim);
02067
02068   switch (Channel)
02069   {
02070     case TIM_CHANNEL_1:
02071       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
02072       break;
02073     case TIM_CHANNEL_2:
02074       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
02075       break;
02076     case TIM_CHANNEL_3:
02077       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
02078       break;
02079     case TIM_CHANNEL_4:
02080       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
02081       break;
02082     default:
02083       status = HAL_ERROR;
02084       break;
02085   }
02086
02087   __HAL_UNLOCK(htim);
02088
02089   return status;
02090 }
02091
02092 /**
02093   * @brief  Group channel 5 and channel 1, 2 or 3
02094   * @param  htim TIM handle.
02095   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
02096   *         This parameter can be any combination of the following values:
02097   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02098   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02099   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02100   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02101   * @retval HAL status
02102   */
02103 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02104 {
02105   /* Check parameters */
02106   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02107   assert_param(IS_TIM_GROUPCH5(Channels));
02108
02109   /* Process Locked */
02110   __HAL_LOCK(htim);
02111
02112   htim->State = HAL_TIM_STATE_BUSY;
02113
02114   /* Clear GC5Cx bit fields */
02115   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
02116
02117   /* Set GC5Cx bit fields */
02118   htim->Instance->CCR5 |= Channels;
02119
02120   /* Change the htim state */
02121   htim->State = HAL_TIM_STATE_READY;
02122
02123   __HAL_UNLOCK(htim);
02124
02125   return HAL_OK;
02126 }
02127
02128 /**
02129   * @}
02130   */
02131
02132 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02133   * @brief    Extended Callbacks functions
02134   *
02135 @verbatim
02136   ==============================================================================
02137                     ##### Extended Callbacks functions #####
02138   ==============================================================================
02139   [..]
02140     This section provides Extended TIM callback functions:
02141     (+) Timer Commutation callback
02142     (+) Timer Break callback
02143
02144 @endverbatim
02145   * @{
02146   */
02147
02148 /**
02149   * @brief  Hall commutation changed callback in non-blocking mode
02150   * @param  htim TIM handle
02151   * @retval None
02152   */
02153 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
02154 {
02155   /* Prevent unused argument(s) compilation warning */
02156   UNUSED(htim);
02157
02158   /* NOTE : This function should not be modified, when the callback is needed,
02159             the HAL_TIMEx_CommutCallback could be implemented in the user file
02160    */
02161 }
02162 /**
02163   * @brief  Hall commutation changed half complete callback in non-blocking mode
02164   * @param  htim TIM handle
02165   * @retval None
02166   */
02167 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
02168 {
02169   /* Prevent unused argument(s) compilation warning */
02170   UNUSED(htim);
02171
02172   /* NOTE : This function should not be modified, when the callback is needed,
02173             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
02174    */
02175 }
02176
02177 /**
02178   * @brief  Hall Break detection callback in non-blocking mode
02179   * @param  htim TIM handle
02180   * @retval None
02181   */
02182 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02183 {
02184   /* Prevent unused argument(s) compilation warning */
02185   UNUSED(htim);
02186
02187   /* NOTE : This function should not be modified, when the callback is needed,
02188             the HAL_TIMEx_BreakCallback could be implemented in the user file
02189    */
02190 }
02191
02192 /**
02193   * @brief  Hall Break2 detection callback in non blocking mode
02194   * @param  htim: TIM handle
02195   * @retval None
02196   */
02197 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
02198 {
02199   /* Prevent unused argument(s) compilation warning */
02200   UNUSED(htim);
02201
02202   /* NOTE : This function Should not be modified, when the callback is needed,
02203             the HAL_TIMEx_Break2Callback could be implemented in the user file
02204    */
02205 }
02206 /**
02207   * @}
02208   */
02209
02210 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02211   * @brief    Extended Peripheral State functions
02212   *
02213 @verbatim
02214   ==============================================================================
02215                 ##### Extended Peripheral State functions #####
02216   ==============================================================================
02217   [..]
02218     This subsection permits to get in run-time the status of the peripheral
02219     and the data flow.
02220
02221 @endverbatim
02222   * @{
02223   */
02224
02225 /**
02226   * @brief  Return the TIM Hall Sensor interface handle state.
02227   * @param  htim TIM Hall Sensor handle
02228   * @retval HAL state
02229   */
02230 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02231 {
02232   return htim->State;
02233 }
02234
02235 /**
02236   * @}
02237   */
02238
02239 /**
02240   * @}
02241   */
02242
02243 /* Private functions ---------------------------------------------------------*/
02244 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
02245   * @{
02246   */
02247
02248 /**
02249   * @brief  TIM DMA Commutation callback.
02250   * @param  hdma pointer to DMA handle.
02251   * @retval None
02252   */
02253 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02254 {
02255   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02256
02257   /* Change the htim state */
02258   htim->State = HAL_TIM_STATE_READY;
02259
02260 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02261   htim->CommutationCallback(htim);
02262 #else
02263   HAL_TIMEx_CommutCallback(htim);
02264 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02265 }
02266
02267 /**
02268   * @brief  TIM DMA Commutation half complete callback.
02269   * @param  hdma pointer to DMA handle.
02270   * @retval None
02271   */
02272 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
02273 {
02274   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02275
02276   /* Change the htim state */
02277   htim->State = HAL_TIM_STATE_READY;
02278
02279 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02280   htim->CommutationHalfCpltCallback(htim);
02281 #else
02282   HAL_TIMEx_CommutHalfCpltCallback(htim);
02283 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02284 }
02285
02286
02287 /**
02288   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02289   * @param  TIMx to select the TIM peripheral
02290   * @param  Channel specifies the TIM Channel
02291   *          This parameter can be one of the following values:
02292   *            @arg TIM_CHANNEL_1: TIM Channel 1
02293   *            @arg TIM_CHANNEL_2: TIM Channel 2
02294   *            @arg TIM_CHANNEL_3: TIM Channel 3
02295   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
02296   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02297   * @retval None
02298   */
02299 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
02300 {
02301   uint32_t tmp;
02302
02303   tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
02304
02305   /* Reset the CCxNE Bit */
02306   TIMx->CCER &=  ~tmp;
02307
02308   /* Set or reset the CCxNE Bit */
02309   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
02310 }
02311 /**
02312   * @}
02313   */
02314
02315 #endif /* HAL_TIM_MODULE_ENABLED */
02316 /**
02317   * @}
02318   */
02319
02320 /**
02321   * @}
02322   */
02323
02324 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_tim_ex.h Source File

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stm32h7xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_TIM_EX_H
00022 #define STM32H7xx_HAL_TIM_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup TIMEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  TIM Hall sensor Configuration Structure definition
00046   */
00047
00048 typedef struct
00049 {
00050   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00051                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00052
00053   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00054                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00055
00056   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00057                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00058
00059   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00060                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00061 } TIM_HallSensor_InitTypeDef;
00062 #if defined(TIM_BREAK_INPUT_SUPPORT)
00063
00064 /**
00065   * @brief  TIM Break/Break2 input configuration
00066   */
00067 typedef struct
00068 {
00069   uint32_t Source;         /*!< Specifies the source of the timer break input.
00070                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00071   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00072                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00073   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00074                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
00075                                 Not relevant when analog watchdog output of the DFSDM1 used as break input source */
00076 }
00077 TIMEx_BreakInputConfigTypeDef;
00078
00079 #endif /* TIM_BREAK_INPUT_SUPPORT */
00080 /**
00081   * @}
00082   */
00083 /* End of exported types -----------------------------------------------------*/
00084
00085 /* Exported constants --------------------------------------------------------*/
00086 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00087   * @{
00088   */
00089
00090 /** @defgroup TIMEx_Remap TIM Extended Remapping
00091   * @{
00092   */
00093 #define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
00094 #define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
00095 #define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
00096 #define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
00097 #define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
00098 #define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
00099 #define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
00100 #define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
00101 #define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
00102
00103 #define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
00104 #define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
00105 #define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
00106 #define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
00107 #define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
00108 #define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
00109 #define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
00110 #define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
00111 #define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
00112
00113 #define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
00114 #define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
00115 #define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
00116 #define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
00117 #define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
00118 #define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
00119
00120 #define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
00121 #define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
00122
00123 #define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
00124 #define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
00125 #define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
00126 #define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
00127 #define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
00128
00129 #define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
00130 #define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
00131 #define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
00132
00133 #define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
00134 #define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
00135 #define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
00136 #define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
00137 #define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
00138 /**
00139   * @}
00140   */
00141 #if defined(TIM_BREAK_INPUT_SUPPORT)
00142
00143 /** @defgroup TIMEx_Break_Input TIM Extended Break input
00144   * @{
00145   */
00146 #define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
00147 #define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
00153   * @{
00154   */
00155 #define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
00156 #define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
00157 #define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
00158 #define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00164   * @{
00165   */
00166 #define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
00167 #define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
00173   * @{
00174   */
00175 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
00176 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
00177 /**
00178   * @}
00179   */
00180 #endif /* TIM_BREAK_INPUT_SUPPORT */
00181
00182 /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
00183   * @{
00184   */
00185 #define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
00186 #define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
00187
00188 #define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
00189 #define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
00190
00191 #define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
00192 #define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
00193 #define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
00194 #define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
00195
00196 #define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
00197 #define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
00198 #define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
00199 #define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
00200
00201 #define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
00202 #define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
00203 #define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
00204
00205 #define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
00206 #define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
00207
00208 #define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
00209 #define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
00210 #define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
00211 #define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
00212 #define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
00213 #define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
00214 #define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
00215
00216 #define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
00217 #define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
00218 #define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
00219 #define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
00220
00221 #define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
00222 #define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
00223 #define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
00224 #define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
00225
00226 #define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
00227 #define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
00228 #define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
00229 #define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
00230
00231 #define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
00232 #define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
00233 #define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
00234 #define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
00235
00236 #define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
00237 #define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
00238 #define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
00239 #define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
00240 /**
00241   * @}
00242   */
00243
00244 /**
00245   * @}
00246   */
00247 /* End of exported constants -------------------------------------------------*/
00248
00249 /* Exported macro ------------------------------------------------------------*/
00250 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00251   * @{
00252   */
00253
00254 /**
00255   * @}
00256   */
00257 /* End of exported macro -----------------------------------------------------*/
00258
00259 /* Private macro -------------------------------------------------------------*/
00260 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00261   * @{
00262   */
00263 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00264                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00265
00266 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00267                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00268                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00269                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
00270
00271 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00272                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00273
00274 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00275                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00276
00277 #define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\
00278                                   ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\
00279                                   ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\
00280                                   ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\
00281                                   ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\
00282                                   ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\
00283                                   ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\
00284                                   ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\
00285                                   ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\
00286                                   ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\
00287                                   ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\
00288                                   ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\
00289                                   ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
00290                                   ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
00291                                   ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
00292                                   ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
00293                                   ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
00294                                   ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
00295                                   ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
00296                                   ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
00297                                   ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\
00298                                   ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\
00299                                   ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\
00300                                   ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\
00301                                   ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\
00302                                   ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\
00303                                   ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\
00304                                   ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\
00305                                   ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\
00306                                   ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\
00307                                   ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\
00308                                   ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\
00309                                   ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
00310                                   ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
00311                                   ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
00312                                   ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
00313                                   ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
00314                                   ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
00315                                   ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
00316                                   ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
00317                                   ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
00318                                   ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
00319                                   ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
00320                                   ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
00321
00322 #define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
00323                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
00324                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
00325                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
00326                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
00327                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
00328                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
00329                                       ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
00330                                       ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
00331                                       ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
00332                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
00333                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
00334                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
00335                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
00336                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
00337                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
00338                                       ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\
00339                                       ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\
00340                                       ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\
00341                                       ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\
00342                                       ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\
00343                                       ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\
00344                                       ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\
00345                                       ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\
00346                                       ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\
00347                                       ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
00348                                       ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
00349                                       ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
00350                                       ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
00351                                       ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
00352                                       ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
00353                                       ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
00354                                       ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
00355                                       ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
00356                                       ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
00357                                       ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
00358                                       ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
00359
00360 /**
00361   * @}
00362   */
00363 /* End of private macro ------------------------------------------------------*/
00364
00365 /* Exported functions --------------------------------------------------------*/
00366 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
00367   * @{
00368   */
00369
00370 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00371   *  @brief    Timer Hall Sensor functions
00372   * @{
00373   */
00374 /*  Timer Hall Sensor functions  **********************************************/
00375 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
00376 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00377
00378 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00379 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00380
00381 /* Blocking mode: Polling */
00382 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00383 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00384 /* Non-Blocking mode: Interrupt */
00385 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00386 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00387 /* Non-Blocking mode: DMA */
00388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00389 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00390 /**
00391   * @}
00392   */
00393
00394 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00395   *  @brief   Timer Complementary Output Compare functions
00396   * @{
00397   */
00398 /*  Timer Complementary Output Compare functions  *****************************/
00399 /* Blocking mode: Polling */
00400 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00401 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00402
00403 /* Non-Blocking mode: Interrupt */
00404 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00405 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00406
00407 /* Non-Blocking mode: DMA */
00408 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00409 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00410 /**
00411   * @}
00412   */
00413
00414 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00415   *  @brief    Timer Complementary PWM functions
00416   * @{
00417   */
00418 /*  Timer Complementary PWM functions  ****************************************/
00419 /* Blocking mode: Polling */
00420 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00421 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00422
00423 /* Non-Blocking mode: Interrupt */
00424 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00425 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00426 /* Non-Blocking mode: DMA */
00427 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00429 /**
00430   * @}
00431   */
00432
00433 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
00434   *  @brief    Timer Complementary One Pulse functions
00435   * @{
00436   */
00437 /*  Timer Complementary One Pulse functions  **********************************/
00438 /* Blocking mode: Polling */
00439 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00440 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00441
00442 /* Non-Blocking mode: Interrupt */
00443 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00444 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00445 /**
00446   * @}
00447   */
00448
00449 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
00450   *  @brief    Peripheral Control functions
00451   * @{
00452   */
00453 /* Extended Control functions  ************************************************/
00454 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00455                                               uint32_t  CommutationSource);
00456 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00457                                                  uint32_t  CommutationSource);
00458 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00459                                                   uint32_t  CommutationSource);
00460 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
00461                                                         TIM_MasterConfigTypeDef *sMasterConfig);
00462 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
00463                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00464 #if defined(TIM_BREAK_INPUT_SUPPORT)
00465 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
00466                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
00467 #endif /* TIM_BREAK_INPUT_SUPPORT */
00468 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
00469 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
00470 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
00471 /**
00472   * @}
00473   */
00474
00475 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
00476   * @brief    Extended Callbacks functions
00477   * @{
00478   */
00479 /* Extended Callback **********************************************************/
00480 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
00481 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
00482 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00483 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
00484 /**
00485   * @}
00486   */
00487
00488 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
00489   * @brief    Extended Peripheral State functions
00490   * @{
00491   */
00492 /* Extended Peripheral State functions  ***************************************/
00493 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
00494 /**
00495   * @}
00496   */
00497
00498 /**
00499   * @}
00500   */
00501 /* End of exported functions -------------------------------------------------*/
00502
00503 /* Private functions----------------------------------------------------------*/
00504 /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
00505   * @{
00506   */
00507 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00508 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
00509 /**
00510   * @}
00511   */
00512 /* End of private functions --------------------------------------------------*/
00513
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 #ifdef __cplusplus
00523 }
00524 #endif
00525
00526
00527 #endif /* STM32H7xx_HAL_TIM_EX_H */
00528
00529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart.c Source File

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stm32h7xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @brief   UART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *
00012   *
00013   @verbatim
00014  ===============================================================================
00015                         ##### How to use this driver #####
00016  ===============================================================================
00017   [..]
00018     The UART HAL driver can be used as follows:
00019
00020     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00021     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00022         (++) Enable the USARTx interface clock.
00023         (++) UART pins configuration:
00024             (+++) Enable the clock for the UART GPIOs.
00025             (+++) Configure these UART pins as alternate function pull-up.
00026         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00027              and HAL_UART_Receive_IT() APIs):
00028             (+++) Configure the USARTx interrupt priority.
00029             (+++) Enable the NVIC USART IRQ handle.
00030         (++) UART interrupts handling:
00031               -@@-  The specific UART interrupts (Transmission complete interrupt,
00032                 RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
00033                 are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
00034                 inside the transmit and receive processes.
00035         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00036              and HAL_UART_Receive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx channel.
00041             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00043
00044     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
00045         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00046
00047     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00048         in the huart handle AdvancedInit structure.
00049
00050     (#) For the UART asynchronous mode, initialize the UART registers by calling
00051         the HAL_UART_Init() API.
00052
00053     (#) For the UART Half duplex mode, initialize the UART registers by calling
00054         the HAL_HalfDuplex_Init() API.
00055
00056     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00057         by calling the HAL_LIN_Init() API.
00058
00059     (#) For the UART Multiprocessor mode, initialize the UART registers
00060         by calling the HAL_MultiProcessor_Init() API.
00061
00062     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00063         by calling the HAL_RS485Ex_Init() API.
00064
00065     [..]
00066     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00067         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00068         calling the customized HAL_UART_MspInit() API.
00069
00070     ##### Callback registration #####
00071     ==================================
00072
00073     [..]
00074     The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
00075     allows the user to configure dynamically the driver callbacks.
00076
00077     [..]
00078     Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
00079     Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
00080     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00081     (+) TxCpltCallback            : Tx Complete Callback.
00082     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00083     (+) RxCpltCallback            : Rx Complete Callback.
00084     (+) ErrorCallback             : Error Callback.
00085     (+) AbortCpltCallback         : Abort Complete Callback.
00086     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00087     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00088     (+) WakeupCallback            : Wakeup Callback.
00089     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00090     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00091     (+) MspInitCallback           : UART MspInit.
00092     (+) MspDeInitCallback         : UART MspDeInit.
00093     This function takes as parameters the HAL peripheral handle, the Callback ID
00094     and a pointer to the user callback function.
00095
00096     [..]
00097     Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
00098     weak (surcharged) function.
00099     @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00100     and the Callback ID.
00101     This function allows to reset following callbacks:
00102     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00103     (+) TxCpltCallback            : Tx Complete Callback.
00104     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00105     (+) RxCpltCallback            : Rx Complete Callback.
00106     (+) ErrorCallback             : Error Callback.
00107     (+) AbortCpltCallback         : Abort Complete Callback.
00108     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00109     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00110     (+) WakeupCallback            : Wakeup Callback.
00111     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00112     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00113     (+) MspInitCallback           : UART MspInit.
00114     (+) MspDeInitCallback         : UART MspDeInit.
00115
00116     [..]
00117     By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
00118     all callbacks are set to the corresponding weak (surcharged) functions:
00119     examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
00120     Exception done for MspInit and MspDeInit functions that are respectively
00121     reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
00122     and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
00123     If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
00124     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00125
00126     [..]
00127     Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
00128     Exception done MspInit/MspDeInit that can be registered/unregistered
00129     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
00130     MspInit/DeInit callbacks can be used during the Init/DeInit.
00131     In that case first register the MspInit/MspDeInit user callbacks
00132     using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
00133     or @ref HAL_UART_Init() function.
00134
00135     [..]
00136     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
00137     not defined, the callback registration feature is not available
00138     and weak (surcharged) callbacks are used.
00139
00140
00141   @endverbatim
00142   ******************************************************************************
00143   * @attention
00144   *
00145   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00146   * All rights reserved.</center></h2>
00147   *
00148   * This software component is licensed by ST under BSD 3-Clause license,
00149   * the "License"; You may not use this file except in compliance with the
00150   * License. You may obtain a copy of the License at:
00151   *                        opensource.org/licenses/BSD-3-Clause
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32h7xx_hal.h"
00158
00159 /** @addtogroup STM32H7xx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup UART UART
00164   * @brief HAL UART module driver
00165   * @{
00166   */
00167
00168 #ifdef HAL_UART_MODULE_ENABLED
00169
00170 /* Private typedef -----------------------------------------------------------*/
00171 /* Private define ------------------------------------------------------------*/
00172 /** @defgroup UART_Private_Constants UART Private Constants
00173   * @{
00174   */
00175 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00176                                       USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
00177                                       USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00178
00179 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
00180                                       USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
00181
00182 #define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
00183 #define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
00184
00185 #define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
00186 #define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macros ------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private function prototypes -----------------------------------------------*/
00195 /** @addtogroup UART_Private_Functions
00196   * @{
00197   */
00198 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00199 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00200 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00201 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00202 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00203 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00204 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00205 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00206 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00207 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00208 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00209 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00210 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
00211 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
00212 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00213 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00214 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00215 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
00216 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
00217 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00218 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported functions --------------------------------------------------------*/
00224
00225 /** @defgroup UART_Exported_Functions UART Exported Functions
00226   * @{
00227   */
00228
00229 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00230   *  @brief    Initialization and Configuration functions
00231   *
00232 @verbatim
00233 ===============================================================================
00234             ##### Initialization and Configuration functions #####
00235  ===============================================================================
00236     [..]
00237     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00238     in asynchronous mode.
00239       (+) For the asynchronous mode the parameters below can be configured:
00240         (++) Baud Rate
00241         (++) Word Length
00242         (++) Stop Bit
00243         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00244              in the data register is transmitted but is changed by the parity bit.
00245         (++) Hardware flow control
00246         (++) Receiver/transmitter modes
00247         (++) Over Sampling Method
00248         (++) One-Bit Sampling Method
00249       (+) For the asynchronous mode, the following advanced features can be configured as well:
00250         (++) TX and/or RX pin level inversion
00251         (++) data logical level inversion
00252         (++) RX and TX pins swap
00253         (++) RX overrun detection disabling
00254         (++) DMA disabling on RX error
00255         (++) MSB first on communication line
00256         (++) auto Baud rate detection
00257     [..]
00258     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00259     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00260     and UART multiprocessor mode configuration procedures (details for the procedures
00261     are available in reference manual).
00262
00263 @endverbatim
00264
00265   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00266   8-bit or 9-bit), the possible UART formats are listed in the
00267   following table.
00268
00269   Table 1. UART frame format.
00270     +-----------------------------------------------------------------------+
00271     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00272     |---------|---------|-----------|---------------------------------------|
00273     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00274     |---------|---------|-----------|---------------------------------------|
00275     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00276     |---------|---------|-----------|---------------------------------------|
00277     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00278     |---------|---------|-----------|---------------------------------------|
00279     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00280     |---------|---------|-----------|---------------------------------------|
00281     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00282     |---------|---------|-----------|---------------------------------------|
00283     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00284     +-----------------------------------------------------------------------+
00285
00286   * @{
00287   */
00288
00289 /**
00290   * @brief Initialize the UART mode according to the specified
00291   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00292   * @param huart UART handle.
00293   * @retval HAL status
00294   */
00295 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00296 {
00297   /* Check the UART handle allocation */
00298   if (huart == NULL)
00299   {
00300     return HAL_ERROR;
00301   }
00302
00303   if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00304   {
00305     /* Check the parameters */
00306     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00307   }
00308   else
00309   {
00310     /* Check the parameters */
00311     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00312   }
00313
00314   if (huart->gState == HAL_UART_STATE_RESET)
00315   {
00316     /* Allocate lock resource and initialize it */
00317     huart->Lock = HAL_UNLOCKED;
00318
00319 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00320     UART_InitCallbacksToDefault(huart);
00321
00322     if (huart->MspInitCallback == NULL)
00323     {
00324       huart->MspInitCallback = HAL_UART_MspInit;
00325     }
00326
00327     /* Init the low level hardware */
00328     huart->MspInitCallback(huart);
00329 #else
00330     /* Init the low level hardware : GPIO, CLOCK */
00331     HAL_UART_MspInit(huart);
00332 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00333   }
00334
00335   huart->gState = HAL_UART_STATE_BUSY;
00336
00337   __HAL_UART_DISABLE(huart);
00338
00339   /* Set the UART Communication parameters */
00340   if (UART_SetConfig(huart) == HAL_ERROR)
00341   {
00342     return HAL_ERROR;
00343   }
00344
00345   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00346   {
00347     UART_AdvFeatureConfig(huart);
00348   }
00349
00350   /* In asynchronous mode, the following bits must be kept cleared:
00351   - LINEN and CLKEN bits in the USART_CR2 register,
00352   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00353   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00354   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00355
00356   __HAL_UART_ENABLE(huart);
00357
00358   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00359   return (UART_CheckIdleState(huart));
00360 }
00361
00362 /**
00363   * @brief Initialize the half-duplex mode according to the specified
00364   *        parameters in the UART_InitTypeDef and creates the associated handle.
00365   * @param huart UART handle.
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00369 {
00370   /* Check the UART handle allocation */
00371   if (huart == NULL)
00372   {
00373     return HAL_ERROR;
00374   }
00375
00376   /* Check UART instance */
00377   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00378
00379   if (huart->gState == HAL_UART_STATE_RESET)
00380   {
00381     /* Allocate lock resource and initialize it */
00382     huart->Lock = HAL_UNLOCKED;
00383
00384 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00385     UART_InitCallbacksToDefault(huart);
00386
00387     if (huart->MspInitCallback == NULL)
00388     {
00389       huart->MspInitCallback = HAL_UART_MspInit;
00390     }
00391
00392     /* Init the low level hardware */
00393     huart->MspInitCallback(huart);
00394 #else
00395     /* Init the low level hardware : GPIO, CLOCK */
00396     HAL_UART_MspInit(huart);
00397 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00398   }
00399
00400   huart->gState = HAL_UART_STATE_BUSY;
00401
00402   __HAL_UART_DISABLE(huart);
00403
00404   /* Set the UART Communication parameters */
00405   if (UART_SetConfig(huart) == HAL_ERROR)
00406   {
00407     return HAL_ERROR;
00408   }
00409
00410   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00411   {
00412     UART_AdvFeatureConfig(huart);
00413   }
00414
00415   /* In half-duplex mode, the following bits must be kept cleared:
00416   - LINEN and CLKEN bits in the USART_CR2 register,
00417   - SCEN and IREN bits in the USART_CR3 register.*/
00418   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00419   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00420
00421   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00422   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00423
00424   __HAL_UART_ENABLE(huart);
00425
00426   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00427   return (UART_CheckIdleState(huart));
00428 }
00429
00430
00431 /**
00432   * @brief Initialize the LIN mode according to the specified
00433   *        parameters in the UART_InitTypeDef and creates the associated handle.
00434   * @param huart             UART handle.
00435   * @param BreakDetectLength Specifies the LIN break detection length.
00436   *        This parameter can be one of the following values:
00437   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00438   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00442 {
00443   /* Check the UART handle allocation */
00444   if (huart == NULL)
00445   {
00446     return HAL_ERROR;
00447   }
00448
00449   /* Check the LIN UART instance */
00450   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00451   /* Check the Break detection length parameter */
00452   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00453
00454   /* LIN mode limited to 16-bit oversampling only */
00455   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
00456   {
00457     return HAL_ERROR;
00458   }
00459   /* LIN mode limited to 8-bit data length */
00460   if (huart->Init.WordLength != UART_WORDLENGTH_8B)
00461   {
00462     return HAL_ERROR;
00463   }
00464
00465   if (huart->gState == HAL_UART_STATE_RESET)
00466   {
00467     /* Allocate lock resource and initialize it */
00468     huart->Lock = HAL_UNLOCKED;
00469
00470 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00471     UART_InitCallbacksToDefault(huart);
00472
00473     if (huart->MspInitCallback == NULL)
00474     {
00475       huart->MspInitCallback = HAL_UART_MspInit;
00476     }
00477
00478     /* Init the low level hardware */
00479     huart->MspInitCallback(huart);
00480 #else
00481     /* Init the low level hardware : GPIO, CLOCK */
00482     HAL_UART_MspInit(huart);
00483 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00484   }
00485
00486   huart->gState = HAL_UART_STATE_BUSY;
00487
00488   __HAL_UART_DISABLE(huart);
00489
00490   /* Set the UART Communication parameters */
00491   if (UART_SetConfig(huart) == HAL_ERROR)
00492   {
00493     return HAL_ERROR;
00494   }
00495
00496   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00497   {
00498     UART_AdvFeatureConfig(huart);
00499   }
00500
00501   /* In LIN mode, the following bits must be kept cleared:
00502   - LINEN and CLKEN bits in the USART_CR2 register,
00503   - SCEN and IREN bits in the USART_CR3 register.*/
00504   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00505   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00506
00507   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00508   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00509
00510   /* Set the USART LIN Break detection length. */
00511   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00512
00513   __HAL_UART_ENABLE(huart);
00514
00515   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00516   return (UART_CheckIdleState(huart));
00517 }
00518
00519
00520 /**
00521   * @brief Initialize the multiprocessor mode according to the specified
00522   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00523   * @param huart        UART handle.
00524   * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
00525   * @param WakeUpMethod Specifies the UART wakeup method.
00526   *        This parameter can be one of the following values:
00527   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00528   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00529   * @note  If the user resorts to idle line detection wake up, the Address parameter
00530   *        is useless and ignored by the initialization function.
00531   * @note  If the user resorts to address mark wake up, the address length detection
00532   *        is configured by default to 4 bits only. For the UART to be able to
00533   *        manage 6-, 7- or 8-bit long addresses detection, the API
00534   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00535   *        HAL_MultiProcessor_Init().
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00539 {
00540   /* Check the UART handle allocation */
00541   if (huart == NULL)
00542   {
00543     return HAL_ERROR;
00544   }
00545
00546   /* Check the wake up method parameter */
00547   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00548
00549   if (huart->gState == HAL_UART_STATE_RESET)
00550   {
00551     /* Allocate lock resource and initialize it */
00552     huart->Lock = HAL_UNLOCKED;
00553
00554 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00555     UART_InitCallbacksToDefault(huart);
00556
00557     if (huart->MspInitCallback == NULL)
00558     {
00559       huart->MspInitCallback = HAL_UART_MspInit;
00560     }
00561
00562     /* Init the low level hardware */
00563     huart->MspInitCallback(huart);
00564 #else
00565     /* Init the low level hardware : GPIO, CLOCK */
00566     HAL_UART_MspInit(huart);
00567 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00568   }
00569
00570   huart->gState = HAL_UART_STATE_BUSY;
00571
00572   __HAL_UART_DISABLE(huart);
00573
00574   /* Set the UART Communication parameters */
00575   if (UART_SetConfig(huart) == HAL_ERROR)
00576   {
00577     return HAL_ERROR;
00578   }
00579
00580   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00581   {
00582     UART_AdvFeatureConfig(huart);
00583   }
00584
00585   /* In multiprocessor mode, the following bits must be kept cleared:
00586   - LINEN and CLKEN bits in the USART_CR2 register,
00587   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00588   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00589   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00590
00591   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00592   {
00593     /* If address mark wake up method is chosen, set the USART address node */
00594     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00595   }
00596
00597   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00598   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00599
00600   __HAL_UART_ENABLE(huart);
00601
00602   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00603   return (UART_CheckIdleState(huart));
00604 }
00605
00606
00607 /**
00608   * @brief DeInitialize the UART peripheral.
00609   * @param huart UART handle.
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00613 {
00614   /* Check the UART handle allocation */
00615   if (huart == NULL)
00616   {
00617     return HAL_ERROR;
00618   }
00619
00620   /* Check the parameters */
00621   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00622
00623   huart->gState = HAL_UART_STATE_BUSY;
00624
00625   __HAL_UART_DISABLE(huart);
00626
00627   huart->Instance->CR1 = 0x0U;
00628   huart->Instance->CR2 = 0x0U;
00629   huart->Instance->CR3 = 0x0U;
00630
00631 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00632   if (huart->MspDeInitCallback == NULL)
00633   {
00634     huart->MspDeInitCallback = HAL_UART_MspDeInit;
00635   }
00636   /* DeInit the low level hardware */
00637   huart->MspDeInitCallback(huart);
00638 #else
00639   /* DeInit the low level hardware */
00640   HAL_UART_MspDeInit(huart);
00641 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00642
00643   huart->ErrorCode = HAL_UART_ERROR_NONE;
00644   huart->gState = HAL_UART_STATE_RESET;
00645   huart->RxState = HAL_UART_STATE_RESET;
00646
00647   __HAL_UNLOCK(huart);
00648
00649   return HAL_OK;
00650 }
00651
00652 /**
00653   * @brief Initialize the UART MSP.
00654   * @param huart UART handle.
00655   * @retval None
00656   */
00657 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00658 {
00659   /* Prevent unused argument(s) compilation warning */
00660   UNUSED(huart);
00661
00662   /* NOTE : This function should not be modified, when the callback is needed,
00663             the HAL_UART_MspInit can be implemented in the user file
00664    */
00665 }
00666
00667 /**
00668   * @brief DeInitialize the UART MSP.
00669   * @param huart UART handle.
00670   * @retval None
00671   */
00672 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00673 {
00674   /* Prevent unused argument(s) compilation warning */
00675   UNUSED(huart);
00676
00677   /* NOTE : This function should not be modified, when the callback is needed,
00678             the HAL_UART_MspDeInit can be implemented in the user file
00679    */
00680 }
00681
00682 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00683 /**
00684   * @brief  Register a User UART Callback
00685   *         To be used instead of the weak predefined callback
00686   * @param  huart uart handle
00687   * @param  CallbackID ID of the callback to be registered
00688   *         This parameter can be one of the following values:
00689   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00690   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00691   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00692   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00693   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00694   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00695   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00696   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00697   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00698   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00699   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00700   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00701   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00702   * @param  pCallback pointer to the Callback function
00703   * @retval HAL status
00704   */
00705 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
00706                                             pUART_CallbackTypeDef pCallback)
00707 {
00708   HAL_StatusTypeDef status = HAL_OK;
00709
00710   if (pCallback == NULL)
00711   {
00712     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00713
00714     return HAL_ERROR;
00715   }
00716
00717   __HAL_LOCK(huart);
00718
00719   if (huart->gState == HAL_UART_STATE_READY)
00720   {
00721     switch (CallbackID)
00722     {
00723       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00724         huart->TxHalfCpltCallback = pCallback;
00725         break;
00726
00727       case HAL_UART_TX_COMPLETE_CB_ID :
00728         huart->TxCpltCallback = pCallback;
00729         break;
00730
00731       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00732         huart->RxHalfCpltCallback = pCallback;
00733         break;
00734
00735       case HAL_UART_RX_COMPLETE_CB_ID :
00736         huart->RxCpltCallback = pCallback;
00737         break;
00738
00739       case HAL_UART_ERROR_CB_ID :
00740         huart->ErrorCallback = pCallback;
00741         break;
00742
00743       case HAL_UART_ABORT_COMPLETE_CB_ID :
00744         huart->AbortCpltCallback = pCallback;
00745         break;
00746
00747       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00748         huart->AbortTransmitCpltCallback = pCallback;
00749         break;
00750
00751       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00752         huart->AbortReceiveCpltCallback = pCallback;
00753         break;
00754
00755       case HAL_UART_WAKEUP_CB_ID :
00756         huart->WakeupCallback = pCallback;
00757         break;
00758
00759       case HAL_UART_RX_FIFO_FULL_CB_ID :
00760         huart->RxFifoFullCallback = pCallback;
00761         break;
00762
00763       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00764         huart->TxFifoEmptyCallback = pCallback;
00765         break;
00766
00767       case HAL_UART_MSPINIT_CB_ID :
00768         huart->MspInitCallback = pCallback;
00769         break;
00770
00771       case HAL_UART_MSPDEINIT_CB_ID :
00772         huart->MspDeInitCallback = pCallback;
00773         break;
00774
00775       default :
00776         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00777
00778         status =  HAL_ERROR;
00779         break;
00780     }
00781   }
00782   else if (huart->gState == HAL_UART_STATE_RESET)
00783   {
00784     switch (CallbackID)
00785     {
00786       case HAL_UART_MSPINIT_CB_ID :
00787         huart->MspInitCallback = pCallback;
00788         break;
00789
00790       case HAL_UART_MSPDEINIT_CB_ID :
00791         huart->MspDeInitCallback = pCallback;
00792         break;
00793
00794       default :
00795         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00796
00797         status =  HAL_ERROR;
00798         break;
00799     }
00800   }
00801   else
00802   {
00803     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00804
00805     status =  HAL_ERROR;
00806   }
00807
00808   __HAL_UNLOCK(huart);
00809
00810   return status;
00811 }
00812
00813 /**
00814   * @brief  Unregister an UART Callback
00815   *         UART callaback is redirected to the weak predefined callback
00816   * @param  huart uart handle
00817   * @param  CallbackID ID of the callback to be unregistered
00818   *         This parameter can be one of the following values:
00819   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00820   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00821   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00822   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00823   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00824   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00825   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00826   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00827   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00828   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00829   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00830   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00831   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
00835 {
00836   HAL_StatusTypeDef status = HAL_OK;
00837
00838   __HAL_LOCK(huart);
00839
00840   if (HAL_UART_STATE_READY == huart->gState)
00841   {
00842     switch (CallbackID)
00843     {
00844       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00845         huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00846         break;
00847
00848       case HAL_UART_TX_COMPLETE_CB_ID :
00849         huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00850         break;
00851
00852       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00853         huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00854         break;
00855
00856       case HAL_UART_RX_COMPLETE_CB_ID :
00857         huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00858         break;
00859
00860       case HAL_UART_ERROR_CB_ID :
00861         huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00862         break;
00863
00864       case HAL_UART_ABORT_COMPLETE_CB_ID :
00865         huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00866         break;
00867
00868       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00869         huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00870         break;
00871
00872       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00873         huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00874         break;
00875
00876       case HAL_UART_WAKEUP_CB_ID :
00877         huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */
00878         break;
00879
00880       case HAL_UART_RX_FIFO_FULL_CB_ID :
00881         huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00882         break;
00883
00884       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00885         huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00886         break;
00887
00888       case HAL_UART_MSPINIT_CB_ID :
00889         huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
00890         break;
00891
00892       case HAL_UART_MSPDEINIT_CB_ID :
00893         huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00894         break;
00895
00896       default :
00897         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00898
00899         status =  HAL_ERROR;
00900         break;
00901     }
00902   }
00903   else if (HAL_UART_STATE_RESET == huart->gState)
00904   {
00905     switch (CallbackID)
00906     {
00907       case HAL_UART_MSPINIT_CB_ID :
00908         huart->MspInitCallback = HAL_UART_MspInit;
00909         break;
00910
00911       case HAL_UART_MSPDEINIT_CB_ID :
00912         huart->MspDeInitCallback = HAL_UART_MspDeInit;
00913         break;
00914
00915       default :
00916         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00917
00918         status =  HAL_ERROR;
00919         break;
00920     }
00921   }
00922   else
00923   {
00924     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00925
00926     status =  HAL_ERROR;
00927   }
00928
00929   __HAL_UNLOCK(huart);
00930
00931   return status;
00932 }
00933 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00934
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00940   * @brief UART Transmit/Receive functions
00941   *
00942 @verbatim
00943  ===============================================================================
00944                       ##### IO operation functions #####
00945  ===============================================================================
00946     This subsection provides a set of functions allowing to manage the UART asynchronous
00947     and Half duplex data transfers.
00948
00949     (#) There are two mode of transfer:
00950        (+) Blocking mode: The communication is performed in polling mode.
00951            The HAL status of all data processing is returned by the same function
00952            after finishing transfer.
00953        (+) Non-Blocking mode: The communication is performed using Interrupts
00954            or DMA, These API's return the HAL status.
00955            The end of the data processing will be indicated through the
00956            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00957            using DMA mode.
00958            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00959            will be executed respectively at the end of the transmit or Receive process
00960            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00961
00962     (#) Blocking mode API's are :
00963         (+) HAL_UART_Transmit()
00964         (+) HAL_UART_Receive()
00965
00966     (#) Non-Blocking mode API's with Interrupt are :
00967         (+) HAL_UART_Transmit_IT()
00968         (+) HAL_UART_Receive_IT()
00969         (+) HAL_UART_IRQHandler()
00970
00971     (#) Non-Blocking mode API's with DMA are :
00972         (+) HAL_UART_Transmit_DMA()
00973         (+) HAL_UART_Receive_DMA()
00974         (+) HAL_UART_DMAPause()
00975         (+) HAL_UART_DMAResume()
00976         (+) HAL_UART_DMAStop()
00977
00978     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00979         (+) HAL_UART_TxHalfCpltCallback()
00980         (+) HAL_UART_TxCpltCallback()
00981         (+) HAL_UART_RxHalfCpltCallback()
00982         (+) HAL_UART_RxCpltCallback()
00983         (+) HAL_UART_ErrorCallback()
00984
00985     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00986         (+) HAL_UART_Abort()
00987         (+) HAL_UART_AbortTransmit()
00988         (+) HAL_UART_AbortReceive()
00989         (+) HAL_UART_Abort_IT()
00990         (+) HAL_UART_AbortTransmit_IT()
00991         (+) HAL_UART_AbortReceive_IT()
00992
00993     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00994         (+) HAL_UART_AbortCpltCallback()
00995         (+) HAL_UART_AbortTransmitCpltCallback()
00996         (+) HAL_UART_AbortReceiveCpltCallback()
00997
00998     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00999         Errors are handled as follows :
01000        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
01001            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
01002            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
01003            and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
01004            If user wants to abort it, Abort services should be called by user.
01005        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
01006            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
01007            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
01008
01009     -@- In the Half duplex communication, it is forbidden to run the transmit
01010         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
01011
01012 @endverbatim
01013   * @{
01014   */
01015
01016 /**
01017   * @brief Send an amount of data in blocking mode.
01018   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01019   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01020   *         of u16 provided through pData.
01021   * @note When FIFO mode is enabled, writing a data in the TDR register adds one
01022   *       data to the TXFIFO. Write operations to the TDR register are performed
01023   *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
01024   *       TXE are mapped on the same bit-field.
01025   * @param huart   UART handle.
01026   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01027   * @param Size    Amount of data elements (u8 or u16) to be sent.
01028   * @param Timeout Timeout duration.
01029   * @retval HAL status
01030   */
01031 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01032 {
01033   uint8_t  *pdata8bits;
01034   uint16_t *pdata16bits;
01035   uint32_t tickstart;
01036
01037   /* Check that a Tx process is not already ongoing */
01038   if (huart->gState == HAL_UART_STATE_READY)
01039   {
01040     if ((pData == NULL) || (Size == 0U))
01041     {
01042       return  HAL_ERROR;
01043     }
01044
01045     __HAL_LOCK(huart);
01046
01047     huart->ErrorCode = HAL_UART_ERROR_NONE;
01048     huart->gState = HAL_UART_STATE_BUSY_TX;
01049
01050     /* Init tickstart for timeout managment*/
01051     tickstart = HAL_GetTick();
01052
01053     huart->TxXferSize  = Size;
01054     huart->TxXferCount = Size;
01055
01056     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
01057     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01058     {
01059       pdata8bits  = NULL;
01060       pdata16bits = (uint16_t *) pData;
01061     }
01062     else
01063     {
01064       pdata8bits  = pData;
01065       pdata16bits = NULL;
01066     }
01067
01068     while (huart->TxXferCount > 0U)
01069     {
01070       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01071       {
01072         return HAL_TIMEOUT;
01073       }
01074       if (pdata8bits == NULL)
01075       {
01076         huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
01077         pdata16bits++;
01078       }
01079       else
01080       {
01081         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
01082         pdata8bits++;
01083       }
01084       huart->TxXferCount--;
01085     }
01086
01087     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
01088     {
01089       return HAL_TIMEOUT;
01090     }
01091
01092     /* At end of Tx process, restore huart->gState to Ready */
01093     huart->gState = HAL_UART_STATE_READY;
01094
01095     __HAL_UNLOCK(huart);
01096
01097     return HAL_OK;
01098   }
01099   else
01100   {
01101     return HAL_BUSY;
01102   }
01103 }
01104
01105 /**
01106   * @brief Receive an amount of data in blocking mode.
01107   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01108   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01109   *         of u16 available through pData.
01110   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
01111   *       is not empty. Read operations from the RDR register are performed when
01112   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
01113   *       RXNE are mapped on the same bit-field.
01114   * @param huart   UART handle.
01115   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01116   * @param Size    Amount of data elements (u8 or u16) to be received.
01117   * @param Timeout Timeout duration.
01118   * @retval HAL status
01119   */
01120 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01121 {
01122   uint8_t  *pdata8bits;
01123   uint16_t *pdata16bits;
01124   uint16_t uhMask;
01125   uint32_t tickstart;
01126
01127   /* Check that a Rx process is not already ongoing */
01128   if (huart->RxState == HAL_UART_STATE_READY)
01129   {
01130     if ((pData == NULL) || (Size == 0U))
01131     {
01132       return  HAL_ERROR;
01133     }
01134
01135     __HAL_LOCK(huart);
01136
01137     huart->ErrorCode = HAL_UART_ERROR_NONE;
01138     huart->RxState = HAL_UART_STATE_BUSY_RX;
01139
01140     /* Init tickstart for timeout managment*/
01141     tickstart = HAL_GetTick();
01142
01143     huart->RxXferSize  = Size;
01144     huart->RxXferCount = Size;
01145
01146     /* Computation of UART mask to apply to RDR register */
01147     UART_MASK_COMPUTATION(huart);
01148     uhMask = huart->Mask;
01149
01150     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
01151     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01152     {
01153       pdata8bits  = NULL;
01154       pdata16bits = (uint16_t *) pData;
01155     }
01156     else
01157     {
01158       pdata8bits  = pData;
01159       pdata16bits = NULL;
01160     }
01161
01162     /* as long as data have to be received */
01163     while (huart->RxXferCount > 0U)
01164     {
01165       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01166       {
01167         return HAL_TIMEOUT;
01168       }
01169       if (pdata8bits == NULL)
01170       {
01171         *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
01172         pdata16bits++;
01173       }
01174       else
01175       {
01176         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
01177         pdata8bits++;
01178       }
01179       huart->RxXferCount--;
01180     }
01181
01182     /* At end of Rx process, restore huart->RxState to Ready */
01183     huart->RxState = HAL_UART_STATE_READY;
01184
01185     __HAL_UNLOCK(huart);
01186
01187     return HAL_OK;
01188   }
01189   else
01190   {
01191     return HAL_BUSY;
01192   }
01193 }
01194
01195 /**
01196   * @brief Send an amount of data in interrupt mode.
01197   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01198   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01199   *         of u16 provided through pData.
01200   * @param huart UART handle.
01201   * @param pData Pointer to data buffer (u8 or u16 data elements).
01202   * @param Size  Amount of data elements (u8 or u16) to be sent.
01203   * @retval HAL status
01204   */
01205 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01206 {
01207   /* Check that a Tx process is not already ongoing */
01208   if (huart->gState == HAL_UART_STATE_READY)
01209   {
01210     if ((pData == NULL) || (Size == 0U))
01211     {
01212       return HAL_ERROR;
01213     }
01214
01215     __HAL_LOCK(huart);
01216
01217     huart->pTxBuffPtr  = pData;
01218     huart->TxXferSize  = Size;
01219     huart->TxXferCount = Size;
01220     huart->TxISR       = NULL;
01221
01222     huart->ErrorCode = HAL_UART_ERROR_NONE;
01223     huart->gState = HAL_UART_STATE_BUSY_TX;
01224
01225     /* Configure Tx interrupt processing */
01226     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01227     {
01228       /* Set the Tx ISR function pointer according to the data word length */
01229       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01230       {
01231         huart->TxISR = UART_TxISR_16BIT_FIFOEN;
01232       }
01233       else
01234       {
01235         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
01236       }
01237
01238       __HAL_UNLOCK(huart);
01239
01240       /* Enable the TX FIFO threshold interrupt */
01241       SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01242     }
01243     else
01244     {
01245       /* Set the Tx ISR function pointer according to the data word length */
01246       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01247       {
01248         huart->TxISR = UART_TxISR_16BIT;
01249       }
01250       else
01251       {
01252         huart->TxISR = UART_TxISR_8BIT;
01253       }
01254
01255       __HAL_UNLOCK(huart);
01256
01257       /* Enable the Transmit Data Register Empty interrupt */
01258       SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01259     }
01260
01261     return HAL_OK;
01262   }
01263   else
01264   {
01265     return HAL_BUSY;
01266   }
01267 }
01268
01269 /**
01270   * @brief Receive an amount of data in interrupt mode.
01271   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01272   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01273   *         of u16 available through pData.
01274   * @param huart UART handle.
01275   * @param pData Pointer to data buffer (u8 or u16 data elements).
01276   * @param Size  Amount of data elements (u8 or u16) to be received.
01277   * @retval HAL status
01278   */
01279 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01280 {
01281   /* Check that a Rx process is not already ongoing */
01282   if (huart->RxState == HAL_UART_STATE_READY)
01283   {
01284     if ((pData == NULL) || (Size == 0U))
01285     {
01286       return HAL_ERROR;
01287     }
01288
01289     __HAL_LOCK(huart);
01290
01291     huart->pRxBuffPtr  = pData;
01292     huart->RxXferSize  = Size;
01293     huart->RxXferCount = Size;
01294     huart->RxISR       = NULL;
01295
01296     /* Computation of UART mask to apply to RDR register */
01297     UART_MASK_COMPUTATION(huart);
01298
01299     huart->ErrorCode = HAL_UART_ERROR_NONE;
01300     huart->RxState = HAL_UART_STATE_BUSY_RX;
01301
01302     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01303     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01304
01305     /* Configure Rx interrupt processing*/
01306     if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
01307     {
01308       /* Set the Rx ISR function pointer according to the data word length */
01309       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01310       {
01311         huart->RxISR = UART_RxISR_16BIT_FIFOEN;
01312       }
01313       else
01314       {
01315         huart->RxISR = UART_RxISR_8BIT_FIFOEN;
01316       }
01317
01318       __HAL_UNLOCK(huart);
01319
01320       /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
01321       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01322       SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
01323     }
01324     else
01325     {
01326       /* Set the Rx ISR function pointer according to the data word length */
01327       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01328       {
01329         huart->RxISR = UART_RxISR_16BIT;
01330       }
01331       else
01332       {
01333         huart->RxISR = UART_RxISR_8BIT;
01334       }
01335
01336       __HAL_UNLOCK(huart);
01337
01338       /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
01339       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01340     }
01341
01342     return HAL_OK;
01343   }
01344   else
01345   {
01346     return HAL_BUSY;
01347   }
01348 }
01349
01350 /**
01351   * @brief Send an amount of data in DMA mode.
01352   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01353   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01354   *         of u16 provided through pData.
01355   * @param huart UART handle.
01356   * @param pData Pointer to data buffer (u8 or u16 data elements).
01357   * @param Size  Amount of data elements (u8 or u16) to be sent.
01358   * @retval HAL status
01359   */
01360 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01361 {
01362   /* Check that a Tx process is not already ongoing */
01363   if (huart->gState == HAL_UART_STATE_READY)
01364   {
01365     if ((pData == NULL) || (Size == 0U))
01366     {
01367       return HAL_ERROR;
01368     }
01369
01370     __HAL_LOCK(huart);
01371
01372     huart->pTxBuffPtr  = pData;
01373     huart->TxXferSize  = Size;
01374     huart->TxXferCount = Size;
01375
01376     huart->ErrorCode = HAL_UART_ERROR_NONE;
01377     huart->gState = HAL_UART_STATE_BUSY_TX;
01378
01379     if (huart->hdmatx != NULL)
01380     {
01381       /* Set the UART DMA transfer complete callback */
01382       huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
01383
01384       /* Set the UART DMA Half transfer complete callback */
01385       huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
01386
01387       /* Set the DMA error callback */
01388       huart->hdmatx->XferErrorCallback = UART_DMAError;
01389
01390       /* Set the DMA abort callback */
01391       huart->hdmatx->XferAbortCallback = NULL;
01392
01393       /* Enable the UART transmit DMA channel */
01394       if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
01395       {
01396         /* Set error code to DMA */
01397         huart->ErrorCode = HAL_UART_ERROR_DMA;
01398
01399         __HAL_UNLOCK(huart);
01400
01401         /* Restore huart->gState to ready */
01402         huart->gState = HAL_UART_STATE_READY;
01403
01404         return HAL_ERROR;
01405       }
01406     }
01407     /* Clear the TC flag in the ICR register */
01408     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
01409
01410     __HAL_UNLOCK(huart);
01411
01412     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01413     in the UART CR3 register */
01414     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01415
01416     return HAL_OK;
01417   }
01418   else
01419   {
01420     return HAL_BUSY;
01421   }
01422 }
01423
01424 /**
01425   * @brief Receive an amount of data in DMA mode.
01426   * @note   When the UART parity is enabled (PCE = 1), the received data contain
01427   *         the parity bit (MSB position).
01428   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01429   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01430   *         of u16 available through pData.
01431   * @param huart UART handle.
01432   * @param pData Pointer to data buffer (u8 or u16 data elements).
01433   * @param Size  Amount of data elements (u8 or u16) to be received.
01434   * @retval HAL status
01435   */
01436 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01437 {
01438   /* Check that a Rx process is not already ongoing */
01439   if (huart->RxState == HAL_UART_STATE_READY)
01440   {
01441     if ((pData == NULL) || (Size == 0U))
01442     {
01443       return HAL_ERROR;
01444     }
01445
01446     __HAL_LOCK(huart);
01447
01448     huart->pRxBuffPtr = pData;
01449     huart->RxXferSize = Size;
01450
01451     huart->ErrorCode = HAL_UART_ERROR_NONE;
01452     huart->RxState = HAL_UART_STATE_BUSY_RX;
01453
01454     if (huart->hdmarx != NULL)
01455     {
01456       /* Set the UART DMA transfer complete callback */
01457       huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
01458
01459       /* Set the UART DMA Half transfer complete callback */
01460       huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
01461
01462       /* Set the DMA error callback */
01463       huart->hdmarx->XferErrorCallback = UART_DMAError;
01464
01465       /* Set the DMA abort callback */
01466       huart->hdmarx->XferAbortCallback = NULL;
01467
01468       /* Enable the DMA channel */
01469       if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
01470       {
01471         /* Set error code to DMA */
01472         huart->ErrorCode = HAL_UART_ERROR_DMA;
01473
01474         __HAL_UNLOCK(huart);
01475
01476         /* Restore huart->gState to ready */
01477         huart->gState = HAL_UART_STATE_READY;
01478
01479         return HAL_ERROR;
01480       }
01481     }
01482     __HAL_UNLOCK(huart);
01483
01484     /* Enable the UART Parity Error Interrupt */
01485     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01486
01487     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01488     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01489
01490     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01491     in the UART CR3 register */
01492     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01493
01494     return HAL_OK;
01495   }
01496   else
01497   {
01498     return HAL_BUSY;
01499   }
01500 }
01501
01502 /**
01503   * @brief Pause the DMA Transfer.
01504   * @param huart UART handle.
01505   * @retval HAL status
01506   */
01507 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01508 {
01509   const HAL_UART_StateTypeDef gstate = huart->gState;
01510   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01511
01512   __HAL_LOCK(huart);
01513
01514   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01515       (gstate == HAL_UART_STATE_BUSY_TX))
01516   {
01517     /* Disable the UART DMA Tx request */
01518     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01519   }
01520   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01521       (rxstate == HAL_UART_STATE_BUSY_RX))
01522   {
01523     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01524     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01525     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01526
01527     /* Disable the UART DMA Rx request */
01528     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01529   }
01530
01531   __HAL_UNLOCK(huart);
01532
01533   return HAL_OK;
01534 }
01535
01536 /**
01537   * @brief Resume the DMA Transfer.
01538   * @param huart UART handle.
01539   * @retval HAL status
01540   */
01541 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01542 {
01543   __HAL_LOCK(huart);
01544
01545   if (huart->gState == HAL_UART_STATE_BUSY_TX)
01546   {
01547     /* Enable the UART DMA Tx request */
01548     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01549   }
01550   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
01551   {
01552     /* Clear the Overrun flag before resuming the Rx transfer */
01553     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01554
01555     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01556     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01557     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01558
01559     /* Enable the UART DMA Rx request */
01560     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01561   }
01562
01563   __HAL_UNLOCK(huart);
01564
01565   return HAL_OK;
01566 }
01567
01568 /**
01569   * @brief Stop the DMA Transfer.
01570   * @param huart UART handle.
01571   * @retval HAL status
01572   */
01573 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01574 {
01575   /* The Lock is not implemented on this API to allow the user application
01576      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01577      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01578      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01579      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01580      the stream and the corresponding call back is executed. */
01581
01582   const HAL_UART_StateTypeDef gstate = huart->gState;
01583   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01584
01585   /* Stop UART DMA Tx request if ongoing */
01586   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01587       (gstate == HAL_UART_STATE_BUSY_TX))
01588   {
01589     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01590
01591     /* Abort the UART DMA Tx channel */
01592     if (huart->hdmatx != NULL)
01593     {
01594       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01595       {
01596         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01597         {
01598           /* Set error code to DMA */
01599           huart->ErrorCode = HAL_UART_ERROR_DMA;
01600
01601           return HAL_TIMEOUT;
01602         }
01603       }
01604     }
01605
01606     UART_EndTxTransfer(huart);
01607   }
01608
01609   /* Stop UART DMA Rx request if ongoing */
01610   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01611       (rxstate == HAL_UART_STATE_BUSY_RX))
01612   {
01613     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01614
01615     /* Abort the UART DMA Rx channel */
01616     if (huart->hdmarx != NULL)
01617     {
01618       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01619       {
01620         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01621         {
01622           /* Set error code to DMA */
01623           huart->ErrorCode = HAL_UART_ERROR_DMA;
01624
01625           return HAL_TIMEOUT;
01626         }
01627       }
01628     }
01629
01630     UART_EndRxTransfer(huart);
01631   }
01632
01633   return HAL_OK;
01634 }
01635
01636 /**
01637   * @brief  Abort ongoing transfers (blocking mode).
01638   * @param  huart UART handle.
01639   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01640   *         This procedure performs following operations :
01641   *           - Disable UART Interrupts (Tx and Rx)
01642   *           - Disable the DMA transfer in the peripheral register (if enabled)
01643   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01644   *           - Set handle State to READY
01645   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01646   * @retval HAL status
01647   */
01648 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01649 {
01650   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01651   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01652   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01653
01654   /* Disable the UART DMA Tx request if enabled */
01655   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01656   {
01657     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01658
01659     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01660     if (huart->hdmatx != NULL)
01661     {
01662       /* Set the UART DMA Abort callback to Null.
01663          No call back execution at end of DMA abort procedure */
01664       huart->hdmatx->XferAbortCallback = NULL;
01665
01666       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01667       {
01668         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01669         {
01670           /* Set error code to DMA */
01671           huart->ErrorCode = HAL_UART_ERROR_DMA;
01672
01673           return HAL_TIMEOUT;
01674         }
01675       }
01676     }
01677   }
01678
01679   /* Disable the UART DMA Rx request if enabled */
01680   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01681   {
01682     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01683
01684     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01685     if (huart->hdmarx != NULL)
01686     {
01687       /* Set the UART DMA Abort callback to Null.
01688          No call back execution at end of DMA abort procedure */
01689       huart->hdmarx->XferAbortCallback = NULL;
01690
01691       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01692       {
01693         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01694         {
01695           /* Set error code to DMA */
01696           huart->ErrorCode = HAL_UART_ERROR_DMA;
01697
01698           return HAL_TIMEOUT;
01699         }
01700       }
01701     }
01702   }
01703
01704   /* Reset Tx and Rx transfer counters */
01705   huart->TxXferCount = 0U;
01706   huart->RxXferCount = 0U;
01707
01708   /* Clear the Error flags in the ICR register */
01709   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01710
01711   /* Flush the whole TX FIFO (if needed) */
01712   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01713   {
01714     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01715   }
01716
01717   /* Discard the received data */
01718   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01719
01720   /* Restore huart->gState and huart->RxState to Ready */
01721   huart->gState  = HAL_UART_STATE_READY;
01722   huart->RxState = HAL_UART_STATE_READY;
01723
01724   huart->ErrorCode = HAL_UART_ERROR_NONE;
01725
01726   return HAL_OK;
01727 }
01728
01729 /**
01730   * @brief  Abort ongoing Transmit transfer (blocking mode).
01731   * @param  huart UART handle.
01732   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01733   *         This procedure performs following operations :
01734   *           - Disable UART Interrupts (Tx)
01735   *           - Disable the DMA transfer in the peripheral register (if enabled)
01736   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01737   *           - Set handle State to READY
01738   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01739   * @retval HAL status
01740   */
01741 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01742 {
01743   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01744   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
01745   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01746
01747   /* Disable the UART DMA Tx request if enabled */
01748   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01749   {
01750     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01751
01752     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01753     if (huart->hdmatx != NULL)
01754     {
01755       /* Set the UART DMA Abort callback to Null.
01756          No call back execution at end of DMA abort procedure */
01757       huart->hdmatx->XferAbortCallback = NULL;
01758
01759       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01760       {
01761         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01762         {
01763           /* Set error code to DMA */
01764           huart->ErrorCode = HAL_UART_ERROR_DMA;
01765
01766           return HAL_TIMEOUT;
01767         }
01768       }
01769     }
01770   }
01771
01772   /* Reset Tx transfer counter */
01773   huart->TxXferCount = 0U;
01774
01775   /* Flush the whole TX FIFO (if needed) */
01776   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01777   {
01778     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01779   }
01780
01781   /* Restore huart->gState to Ready */
01782   huart->gState = HAL_UART_STATE_READY;
01783
01784   return HAL_OK;
01785 }
01786
01787 /**
01788   * @brief  Abort ongoing Receive transfer (blocking mode).
01789   * @param  huart UART handle.
01790   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01791   *         This procedure performs following operations :
01792   *           - Disable UART Interrupts (Rx)
01793   *           - Disable the DMA transfer in the peripheral register (if enabled)
01794   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01795   *           - Set handle State to READY
01796   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01797   * @retval HAL status
01798   */
01799 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01800 {
01801   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
01802   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
01803   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01804
01805   /* Disable the UART DMA Rx request if enabled */
01806   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01807   {
01808     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01809
01810     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01811     if (huart->hdmarx != NULL)
01812     {
01813       /* Set the UART DMA Abort callback to Null.
01814          No call back execution at end of DMA abort procedure */
01815       huart->hdmarx->XferAbortCallback = NULL;
01816
01817       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01818       {
01819         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01820         {
01821           /* Set error code to DMA */
01822           huart->ErrorCode = HAL_UART_ERROR_DMA;
01823
01824           return HAL_TIMEOUT;
01825         }
01826       }
01827     }
01828   }
01829
01830   /* Reset Rx transfer counter */
01831   huart->RxXferCount = 0U;
01832
01833   /* Clear the Error flags in the ICR register */
01834   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01835
01836   /* Discard the received data */
01837   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01838
01839   /* Restore huart->RxState to Ready */
01840   huart->RxState = HAL_UART_STATE_READY;
01841
01842   return HAL_OK;
01843 }
01844
01845 /**
01846   * @brief  Abort ongoing transfers (Interrupt mode).
01847   * @param  huart UART handle.
01848   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01849   *         This procedure performs following operations :
01850   *           - Disable UART Interrupts (Tx and Rx)
01851   *           - Disable the DMA transfer in the peripheral register (if enabled)
01852   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01853   *           - Set handle State to READY
01854   *           - At abort completion, call user abort complete callback
01855   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01856   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01857   * @retval HAL status
01858   */
01859 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01860 {
01861   uint32_t abortcplt = 1U;
01862
01863   /* Disable interrupts */
01864   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
01865   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01866
01867   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01868      before any call to DMA Abort functions */
01869   /* DMA Tx Handle is valid */
01870   if (huart->hdmatx != NULL)
01871   {
01872     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01873        Otherwise, set it to NULL */
01874     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01875     {
01876       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01877     }
01878     else
01879     {
01880       huart->hdmatx->XferAbortCallback = NULL;
01881     }
01882   }
01883   /* DMA Rx Handle is valid */
01884   if (huart->hdmarx != NULL)
01885   {
01886     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01887        Otherwise, set it to NULL */
01888     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01889     {
01890       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01891     }
01892     else
01893     {
01894       huart->hdmarx->XferAbortCallback = NULL;
01895     }
01896   }
01897
01898   /* Disable the UART DMA Tx request if enabled */
01899   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01900   {
01901     /* Disable DMA Tx at UART level */
01902     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01903
01904     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01905     if (huart->hdmatx != NULL)
01906     {
01907       /* UART Tx DMA Abort callback has already been initialised :
01908          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01909
01910       /* Abort DMA TX */
01911       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01912       {
01913         huart->hdmatx->XferAbortCallback = NULL;
01914       }
01915       else
01916       {
01917         abortcplt = 0U;
01918       }
01919     }
01920   }
01921
01922   /* Disable the UART DMA Rx request if enabled */
01923   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01924   {
01925     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01926
01927     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01928     if (huart->hdmarx != NULL)
01929     {
01930       /* UART Rx DMA Abort callback has already been initialised :
01931          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01932
01933       /* Abort DMA RX */
01934       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01935       {
01936         huart->hdmarx->XferAbortCallback = NULL;
01937         abortcplt = 1U;
01938       }
01939       else
01940       {
01941         abortcplt = 0U;
01942       }
01943     }
01944   }
01945
01946   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01947   if (abortcplt == 1U)
01948   {
01949     /* Reset Tx and Rx transfer counters */
01950     huart->TxXferCount = 0U;
01951     huart->RxXferCount = 0U;
01952
01953     /* Clear ISR function pointers */
01954     huart->RxISR = NULL;
01955     huart->TxISR = NULL;
01956
01957     /* Reset errorCode */
01958     huart->ErrorCode = HAL_UART_ERROR_NONE;
01959
01960     /* Clear the Error flags in the ICR register */
01961     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01962
01963     /* Flush the whole TX FIFO (if needed) */
01964     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01965     {
01966       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01967     }
01968
01969     /* Discard the received data */
01970     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01971
01972     /* Restore huart->gState and huart->RxState to Ready */
01973     huart->gState  = HAL_UART_STATE_READY;
01974     huart->RxState = HAL_UART_STATE_READY;
01975
01976     /* As no DMA to be aborted, call directly user Abort complete callback */
01977 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01978     /* Call registered Abort complete callback */
01979     huart->AbortCpltCallback(huart);
01980 #else
01981     /* Call legacy weak Abort complete callback */
01982     HAL_UART_AbortCpltCallback(huart);
01983 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01984   }
01985
01986   return HAL_OK;
01987 }
01988
01989 /**
01990   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01991   * @param  huart UART handle.
01992   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01993   *         This procedure performs following operations :
01994   *           - Disable UART Interrupts (Tx)
01995   *           - Disable the DMA transfer in the peripheral register (if enabled)
01996   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01997   *           - Set handle State to READY
01998   *           - At abort completion, call user abort complete callback
01999   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02000   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02001   * @retval HAL status
02002   */
02003 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
02004 {
02005   /* Disable interrupts */
02006   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
02007   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
02008
02009   /* Disable the UART DMA Tx request if enabled */
02010   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
02011   {
02012     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02013
02014     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
02015     if (huart->hdmatx != NULL)
02016     {
02017       /* Set the UART DMA Abort callback :
02018          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02019       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
02020
02021       /* Abort DMA TX */
02022       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
02023       {
02024         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
02025         huart->hdmatx->XferAbortCallback(huart->hdmatx);
02026       }
02027     }
02028     else
02029     {
02030       /* Reset Tx transfer counter */
02031       huart->TxXferCount = 0U;
02032
02033       /* Clear TxISR function pointers */
02034       huart->TxISR = NULL;
02035
02036       /* Restore huart->gState to Ready */
02037       huart->gState = HAL_UART_STATE_READY;
02038
02039       /* As no DMA to be aborted, call directly user Abort complete callback */
02040 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02041       /* Call registered Abort Transmit Complete Callback */
02042       huart->AbortTransmitCpltCallback(huart);
02043 #else
02044       /* Call legacy weak Abort Transmit Complete Callback */
02045       HAL_UART_AbortTransmitCpltCallback(huart);
02046 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02047     }
02048   }
02049   else
02050   {
02051     /* Reset Tx transfer counter */
02052     huart->TxXferCount = 0U;
02053
02054     /* Clear TxISR function pointers */
02055     huart->TxISR = NULL;
02056
02057     /* Flush the whole TX FIFO (if needed) */
02058     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
02059     {
02060       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
02061     }
02062
02063     /* Restore huart->gState to Ready */
02064     huart->gState = HAL_UART_STATE_READY;
02065
02066     /* As no DMA to be aborted, call directly user Abort complete callback */
02067 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02068     /* Call registered Abort Transmit Complete Callback */
02069     huart->AbortTransmitCpltCallback(huart);
02070 #else
02071     /* Call legacy weak Abort Transmit Complete Callback */
02072     HAL_UART_AbortTransmitCpltCallback(huart);
02073 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02074   }
02075
02076   return HAL_OK;
02077 }
02078
02079 /**
02080   * @brief  Abort ongoing Receive transfer (Interrupt mode).
02081   * @param  huart UART handle.
02082   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
02083   *         This procedure performs following operations :
02084   *           - Disable UART Interrupts (Rx)
02085   *           - Disable the DMA transfer in the peripheral register (if enabled)
02086   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02087   *           - Set handle State to READY
02088   *           - At abort completion, call user abort complete callback
02089   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02090   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02091   * @retval HAL status
02092   */
02093 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
02094 {
02095   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02096   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
02097   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02098
02099   /* Disable the UART DMA Rx request if enabled */
02100   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02101   {
02102     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02103
02104     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
02105     if (huart->hdmarx != NULL)
02106     {
02107       /* Set the UART DMA Abort callback :
02108          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02109       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
02110
02111       /* Abort DMA RX */
02112       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02113       {
02114         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02115         huart->hdmarx->XferAbortCallback(huart->hdmarx);
02116       }
02117     }
02118     else
02119     {
02120       /* Reset Rx transfer counter */
02121       huart->RxXferCount = 0U;
02122
02123       /* Clear RxISR function pointer */
02124       huart->pRxBuffPtr = NULL;
02125
02126       /* Clear the Error flags in the ICR register */
02127       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02128
02129       /* Discard the received data */
02130       __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02131
02132       /* Restore huart->RxState to Ready */
02133       huart->RxState = HAL_UART_STATE_READY;
02134
02135       /* As no DMA to be aborted, call directly user Abort complete callback */
02136 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02137       /* Call registered Abort Receive Complete Callback */
02138       huart->AbortReceiveCpltCallback(huart);
02139 #else
02140       /* Call legacy weak Abort Receive Complete Callback */
02141       HAL_UART_AbortReceiveCpltCallback(huart);
02142 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02143     }
02144   }
02145   else
02146   {
02147     /* Reset Rx transfer counter */
02148     huart->RxXferCount = 0U;
02149
02150     /* Clear RxISR function pointer */
02151     huart->pRxBuffPtr = NULL;
02152
02153     /* Clear the Error flags in the ICR register */
02154     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02155
02156     /* Restore huart->RxState to Ready */
02157     huart->RxState = HAL_UART_STATE_READY;
02158
02159     /* As no DMA to be aborted, call directly user Abort complete callback */
02160 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02161     /* Call registered Abort Receive Complete Callback */
02162     huart->AbortReceiveCpltCallback(huart);
02163 #else
02164     /* Call legacy weak Abort Receive Complete Callback */
02165     HAL_UART_AbortReceiveCpltCallback(huart);
02166 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02167   }
02168
02169   return HAL_OK;
02170 }
02171
02172 /**
02173   * @brief Handle UART interrupt request.
02174   * @param huart UART handle.
02175   * @retval None
02176   */
02177 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
02178 {
02179   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
02180   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
02181   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
02182
02183   uint32_t errorflags;
02184   uint32_t errorcode;
02185
02186   /* If no error occurs */
02187   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
02188   if (errorflags == 0U)
02189   {
02190     /* UART in mode Receiver ---------------------------------------------------*/
02191     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02192         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02193             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02194     {
02195       if (huart->RxISR != NULL)
02196       {
02197         huart->RxISR(huart);
02198       }
02199       return;
02200     }
02201   }
02202
02203   /* If some errors occur */
02204   if ((errorflags != 0U)
02205       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02206            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
02207   {
02208     /* UART parity error interrupt occurred -------------------------------------*/
02209     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02210     {
02211       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
02212
02213       huart->ErrorCode |= HAL_UART_ERROR_PE;
02214     }
02215
02216     /* UART frame error interrupt occurred --------------------------------------*/
02217     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02218     {
02219       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
02220
02221       huart->ErrorCode |= HAL_UART_ERROR_FE;
02222     }
02223
02224     /* UART noise error interrupt occurred --------------------------------------*/
02225     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02226     {
02227       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
02228
02229       huart->ErrorCode |= HAL_UART_ERROR_NE;
02230     }
02231
02232     /* UART Over-Run interrupt occurred -----------------------------------------*/
02233     if (((isrflags & USART_ISR_ORE) != 0U)
02234         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02235             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02236     {
02237       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
02238
02239       huart->ErrorCode |= HAL_UART_ERROR_ORE;
02240     }
02241
02242     /* UART Receiver Timeout interrupt occurred ---------------------------------*/
02243     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02244     {
02245       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
02246
02247       huart->ErrorCode |= HAL_UART_ERROR_RTO;
02248     }
02249
02250     /* Call UART Error Call back function if need be ----------------------------*/
02251     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
02252     {
02253       /* UART in mode Receiver --------------------------------------------------*/
02254       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02255           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02256               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02257       {
02258         if (huart->RxISR != NULL)
02259         {
02260           huart->RxISR(huart);
02261         }
02262       }
02263
02264       /* If Error is to be considered as blocking :
02265           - Receiver Timeout error in Reception
02266           - Overrun error in Reception
02267           - any error occurs in DMA mode reception
02268       */
02269       errorcode = huart->ErrorCode;
02270       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
02271           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
02272       {
02273         /* Blocking error : transfer is aborted
02274            Set the UART state ready to be able to start again the process,
02275            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
02276         UART_EndRxTransfer(huart);
02277
02278         /* Disable the UART DMA Rx request if enabled */
02279         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02280         {
02281           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02282
02283           /* Abort the UART DMA Rx channel */
02284           if (huart->hdmarx != NULL)
02285           {
02286             /* Set the UART DMA Abort callback :
02287                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
02288             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
02289
02290             /* Abort DMA RX */
02291             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02292             {
02293               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02294               huart->hdmarx->XferAbortCallback(huart->hdmarx);
02295             }
02296           }
02297           else
02298           {
02299             /* Call user error callback */
02300 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02301             /*Call registered error callback*/
02302             huart->ErrorCallback(huart);
02303 #else
02304             /*Call legacy weak error callback*/
02305             HAL_UART_ErrorCallback(huart);
02306 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02307
02308           }
02309         }
02310         else
02311         {
02312           /* Call user error callback */
02313 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02314           /*Call registered error callback*/
02315           huart->ErrorCallback(huart);
02316 #else
02317           /*Call legacy weak error callback*/
02318           HAL_UART_ErrorCallback(huart);
02319 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02320         }
02321       }
02322       else
02323       {
02324         /* Non Blocking error : transfer could go on.
02325            Error is notified to user through user error callback */
02326 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02327         /*Call registered error callback*/
02328         huart->ErrorCallback(huart);
02329 #else
02330         /*Call legacy weak error callback*/
02331         HAL_UART_ErrorCallback(huart);
02332 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02333         huart->ErrorCode = HAL_UART_ERROR_NONE;
02334       }
02335     }
02336     return;
02337
02338   } /* End if some error occurs */
02339
02340   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
02341   if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
02342   {
02343     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
02344
02345     /* UART Rx state is not reset as a reception process might be ongoing.
02346        If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
02347
02348 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02349     /* Call registered Wakeup Callback */
02350     huart->WakeupCallback(huart);
02351 #else
02352     /* Call legacy weak Wakeup Callback */
02353     HAL_UARTEx_WakeupCallback(huart);
02354 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02355     return;
02356   }
02357
02358   /* UART in mode Transmitter ------------------------------------------------*/
02359   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02360       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02361           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02362   {
02363     if (huart->TxISR != NULL)
02364     {
02365       huart->TxISR(huart);
02366     }
02367     return;
02368   }
02369
02370   /* UART in mode Transmitter (transmission end) -----------------------------*/
02371   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02372   {
02373     UART_EndTransmit_IT(huart);
02374     return;
02375   }
02376
02377   /* UART TX Fifo Empty occurred ----------------------------------------------*/
02378   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02379   {
02380 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02381     /* Call registered Tx Fifo Empty Callback */
02382     huart->TxFifoEmptyCallback(huart);
02383 #else
02384     /* Call legacy weak Tx Fifo Empty Callback */
02385     HAL_UARTEx_TxFifoEmptyCallback(huart);
02386 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02387     return;
02388   }
02389
02390   /* UART RX Fifo Full occurred ----------------------------------------------*/
02391   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02392   {
02393 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02394     /* Call registered Rx Fifo Full Callback */
02395     huart->RxFifoFullCallback(huart);
02396 #else
02397     /* Call legacy weak Rx Fifo Full Callback */
02398     HAL_UARTEx_RxFifoFullCallback(huart);
02399 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02400     return;
02401   }
02402 }
02403
02404 /**
02405   * @brief Tx Transfer completed callback.
02406   * @param huart UART handle.
02407   * @retval None
02408   */
02409 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
02410 {
02411   /* Prevent unused argument(s) compilation warning */
02412   UNUSED(huart);
02413
02414   /* NOTE : This function should not be modified, when the callback is needed,
02415             the HAL_UART_TxCpltCallback can be implemented in the user file.
02416    */
02417 }
02418
02419 /**
02420   * @brief  Tx Half Transfer completed callback.
02421   * @param  huart UART handle.
02422   * @retval None
02423   */
02424 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
02425 {
02426   /* Prevent unused argument(s) compilation warning */
02427   UNUSED(huart);
02428
02429   /* NOTE: This function should not be modified, when the callback is needed,
02430            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
02431    */
02432 }
02433
02434 /**
02435   * @brief  Rx Transfer completed callback.
02436   * @param  huart UART handle.
02437   * @retval None
02438   */
02439 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
02440 {
02441   /* Prevent unused argument(s) compilation warning */
02442   UNUSED(huart);
02443
02444   /* NOTE : This function should not be modified, when the callback is needed,
02445             the HAL_UART_RxCpltCallback can be implemented in the user file.
02446    */
02447 }
02448
02449 /**
02450   * @brief  Rx Half Transfer completed callback.
02451   * @param  huart UART handle.
02452   * @retval None
02453   */
02454 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
02455 {
02456   /* Prevent unused argument(s) compilation warning */
02457   UNUSED(huart);
02458
02459   /* NOTE: This function should not be modified, when the callback is needed,
02460            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
02461    */
02462 }
02463
02464 /**
02465   * @brief  UART error callback.
02466   * @param  huart UART handle.
02467   * @retval None
02468   */
02469 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
02470 {
02471   /* Prevent unused argument(s) compilation warning */
02472   UNUSED(huart);
02473
02474   /* NOTE : This function should not be modified, when the callback is needed,
02475             the HAL_UART_ErrorCallback can be implemented in the user file.
02476    */
02477 }
02478
02479 /**
02480   * @brief  UART Abort Complete callback.
02481   * @param  huart UART handle.
02482   * @retval None
02483   */
02484 __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
02485 {
02486   /* Prevent unused argument(s) compilation warning */
02487   UNUSED(huart);
02488
02489   /* NOTE : This function should not be modified, when the callback is needed,
02490             the HAL_UART_AbortCpltCallback can be implemented in the user file.
02491    */
02492 }
02493
02494 /**
02495   * @brief  UART Abort Complete callback.
02496   * @param  huart UART handle.
02497   * @retval None
02498   */
02499 __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
02500 {
02501   /* Prevent unused argument(s) compilation warning */
02502   UNUSED(huart);
02503
02504   /* NOTE : This function should not be modified, when the callback is needed,
02505             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
02506    */
02507 }
02508
02509 /**
02510   * @brief  UART Abort Receive Complete callback.
02511   * @param  huart UART handle.
02512   * @retval None
02513   */
02514 __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
02515 {
02516   /* Prevent unused argument(s) compilation warning */
02517   UNUSED(huart);
02518
02519   /* NOTE : This function should not be modified, when the callback is needed,
02520             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
02521    */
02522 }
02523
02524 /**
02525   * @}
02526   */
02527
02528 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
02529   *  @brief   UART control functions
02530   *
02531 @verbatim
02532  ===============================================================================
02533                       ##### Peripheral Control functions #####
02534  ===============================================================================
02535     [..]
02536     This subsection provides a set of functions allowing to control the UART.
02537      (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
02538      (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
02539      (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
02540      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
02541      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
02542      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
02543      (+) UART_SetConfig() API configures the UART peripheral
02544      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
02545      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
02546      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
02547      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
02548      (+) HAL_LIN_SendBreak() API transmits the break characters
02549 @endverbatim
02550   * @{
02551   */
02552
02553 /**
02554   * @brief  Update on the fly the receiver timeout value in RTOR register.
02555   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02556   *                    the configuration information for the specified UART module.
02557   * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
02558   *                     value must be less or equal to 0x0FFFFFFFF.
02559   * @retval None
02560   */
02561 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
02562 {
02563   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02564   {
02565     assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
02566     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
02567   }
02568 }
02569
02570 /**
02571   * @brief  Enable the UART receiver timeout feature.
02572   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02573   *                    the configuration information for the specified UART module.
02574   * @retval HAL status
02575   */
02576 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
02577 {
02578   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02579   {
02580     if (huart->gState == HAL_UART_STATE_READY)
02581     {
02582       /* Process Locked */
02583       __HAL_LOCK(huart);
02584
02585       huart->gState = HAL_UART_STATE_BUSY;
02586
02587       /* Set the USART RTOEN bit */
02588       SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02589
02590       huart->gState = HAL_UART_STATE_READY;
02591
02592       /* Process Unlocked */
02593       __HAL_UNLOCK(huart);
02594
02595       return HAL_OK;
02596     }
02597     else
02598     {
02599       return HAL_BUSY;
02600     }
02601   }
02602   else
02603   {
02604     return HAL_ERROR;
02605   }
02606 }
02607
02608 /**
02609   * @brief  Disable the UART receiver timeout feature.
02610   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02611   *                    the configuration information for the specified UART module.
02612   * @retval HAL status
02613   */
02614 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
02615 {
02616   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02617   {
02618     if (huart->gState == HAL_UART_STATE_READY)
02619     {
02620       /* Process Locked */
02621       __HAL_LOCK(huart);
02622
02623       huart->gState = HAL_UART_STATE_BUSY;
02624
02625       /* Clear the USART RTOEN bit */
02626       CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02627
02628       huart->gState = HAL_UART_STATE_READY;
02629
02630       /* Process Unlocked */
02631       __HAL_UNLOCK(huart);
02632
02633       return HAL_OK;
02634     }
02635     else
02636     {
02637       return HAL_BUSY;
02638     }
02639   }
02640   else
02641   {
02642     return HAL_ERROR;
02643   }
02644 }
02645
02646 /**
02647   * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
02648   *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
02649   * @param  huart UART handle.
02650   * @retval HAL status
02651   */
02652 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
02653 {
02654   __HAL_LOCK(huart);
02655
02656   huart->gState = HAL_UART_STATE_BUSY;
02657
02658   /* Enable USART mute mode by setting the MME bit in the CR1 register */
02659   SET_BIT(huart->Instance->CR1, USART_CR1_MME);
02660
02661   huart->gState = HAL_UART_STATE_READY;
02662
02663   return (UART_CheckIdleState(huart));
02664 }
02665
02666 /**
02667   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
02668   *         as it may not have been in mute mode at this very moment).
02669   * @param  huart UART handle.
02670   * @retval HAL status
02671   */
02672 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
02673 {
02674   __HAL_LOCK(huart);
02675
02676   huart->gState = HAL_UART_STATE_BUSY;
02677
02678   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
02679   CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
02680
02681   huart->gState = HAL_UART_STATE_READY;
02682
02683   return (UART_CheckIdleState(huart));
02684 }
02685
02686 /**
02687   * @brief Enter UART mute mode (means UART actually enters mute mode).
02688   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
02689   * @param huart UART handle.
02690   * @retval None
02691   */
02692 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
02693 {
02694   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
02695 }
02696
02697 /**
02698   * @brief  Enable the UART transmitter and disable the UART receiver.
02699   * @param  huart UART handle.
02700   * @retval HAL status
02701   */
02702 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
02703 {
02704   __HAL_LOCK(huart);
02705   huart->gState = HAL_UART_STATE_BUSY;
02706
02707   /* Clear TE and RE bits */
02708   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02709
02710   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
02711   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
02712
02713   huart->gState = HAL_UART_STATE_READY;
02714
02715   __HAL_UNLOCK(huart);
02716
02717   return HAL_OK;
02718 }
02719
02720 /**
02721   * @brief  Enable the UART receiver and disable the UART transmitter.
02722   * @param  huart UART handle.
02723   * @retval HAL status.
02724   */
02725 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
02726 {
02727   __HAL_LOCK(huart);
02728   huart->gState = HAL_UART_STATE_BUSY;
02729
02730   /* Clear TE and RE bits */
02731   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02732
02733   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
02734   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
02735
02736   huart->gState = HAL_UART_STATE_READY;
02737
02738   __HAL_UNLOCK(huart);
02739
02740   return HAL_OK;
02741 }
02742
02743
02744 /**
02745   * @brief  Transmit break characters.
02746   * @param  huart UART handle.
02747   * @retval HAL status
02748   */
02749 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
02750 {
02751   /* Check the parameters */
02752   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
02753
02754   __HAL_LOCK(huart);
02755
02756   huart->gState = HAL_UART_STATE_BUSY;
02757
02758   /* Send break characters */
02759   __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
02760
02761   huart->gState = HAL_UART_STATE_READY;
02762
02763   __HAL_UNLOCK(huart);
02764
02765   return HAL_OK;
02766 }
02767
02768 /**
02769   * @}
02770   */
02771
02772 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
02773   *  @brief   UART Peripheral State functions
02774   *
02775 @verbatim
02776   ==============================================================================
02777             ##### Peripheral State and Error functions #####
02778   ==============================================================================
02779     [..]
02780     This subsection provides functions allowing to :
02781       (+) Return the UART handle state.
02782       (+) Return the UART handle error code
02783
02784 @endverbatim
02785   * @{
02786   */
02787
02788 /**
02789   * @brief Return the UART handle state.
02790   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02791   *               the configuration information for the specified UART.
02792   * @retval HAL state
02793   */
02794 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
02795 {
02796   uint32_t temp1;
02797   uint32_t temp2;
02798   temp1 = huart->gState;
02799   temp2 = huart->RxState;
02800
02801   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02802 }
02803
02804 /**
02805   * @brief  Return the UART handle error code.
02806   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02807   *               the configuration information for the specified UART.
02808   * @retval UART Error Code
02809   */
02810 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
02811 {
02812   return huart->ErrorCode;
02813 }
02814 /**
02815   * @}
02816   */
02817
02818 /**
02819   * @}
02820   */
02821
02822 /** @defgroup UART_Private_Functions UART Private Functions
02823   * @{
02824   */
02825
02826 /**
02827   * @brief  Initialize the callbacks to their default values.
02828   * @param  huart UART handle.
02829   * @retval none
02830   */
02831 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02832 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
02833 {
02834   /* Init the UART Callback settings */
02835   huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02836   huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02837   huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02838   huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02839   huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02840   huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02841   huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02842   huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02843   huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
02844   huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02845   huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02846
02847 }
02848 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02849
02850 /**
02851   * @brief Configure the UART peripheral.
02852   * @param huart UART handle.
02853   * @retval HAL status
02854   */
02855 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
02856 {
02857   uint32_t tmpreg;
02858   uint16_t brrtemp;
02859   UART_ClockSourceTypeDef clocksource;
02860   uint32_t usartdiv                   = 0x00000000U;
02861   HAL_StatusTypeDef ret               = HAL_OK;
02862   uint32_t lpuart_ker_ck_pres         = 0x00000000U;
02863   PLL2_ClocksTypeDef pll2_clocks;
02864   PLL3_ClocksTypeDef pll3_clocks;
02865   uint32_t pclk;
02866
02867   /* Check the parameters */
02868   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
02869   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
02870   if (UART_INSTANCE_LOWPOWER(huart))
02871   {
02872     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
02873   }
02874   else
02875   {
02876     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02877     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
02878   }
02879
02880   assert_param(IS_UART_PARITY(huart->Init.Parity));
02881   assert_param(IS_UART_MODE(huart->Init.Mode));
02882   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
02883   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
02884   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
02885
02886   /*-------------------------- USART CR1 Configuration -----------------------*/
02887   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
02888   *  the UART Word Length, Parity, Mode and oversampling:
02889   *  set the M bits according to huart->Init.WordLength value
02890   *  set PCE and PS bits according to huart->Init.Parity value
02891   *  set TE and RE bits according to huart->Init.Mode value
02892   *  set OVER8 bit according to huart->Init.OverSampling value */
02893   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
02894   tmpreg |= (uint32_t)huart->FifoMode;
02895   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02896
02897   /*-------------------------- USART CR2 Configuration -----------------------*/
02898   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
02899   * to huart->Init.StopBits value */
02900   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
02901
02902   /*-------------------------- USART CR3 Configuration -----------------------*/
02903   /* Configure
02904   * - UART HardWare Flow Control: set CTSE and RTSE bits according
02905   *   to huart->Init.HwFlowCtl value
02906   * - one-bit sampling method versus three samples' majority rule according
02907   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
02908   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
02909
02910   if (!(UART_INSTANCE_LOWPOWER(huart)))
02911   {
02912     tmpreg |= huart->Init.OneBitSampling;
02913   }
02914   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02915
02916   /*-------------------------- USART PRESC Configuration -----------------------*/
02917   /* Configure
02918   * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
02919   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
02920
02921   /*-------------------------- USART BRR Configuration -----------------------*/
02922   UART_GETCLOCKSOURCE(huart, clocksource);
02923
02924   /* Check LPUART instance */
02925   if (UART_INSTANCE_LOWPOWER(huart))
02926   {
02927     /* Retrieve frequency clock */
02928     switch (clocksource)
02929     {
02930       case UART_CLOCKSOURCE_D3PCLK1:
02931         lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02932         break;
02933       case UART_CLOCKSOURCE_PLL2:
02934         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02935         lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02936         break;
02937       case UART_CLOCKSOURCE_PLL3:
02938         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02939         lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02940         break;
02941       case UART_CLOCKSOURCE_HSI:
02942         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02943         {
02944           lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02945         }
02946         else
02947         {
02948           lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02949         }
02950         break;
02951       case UART_CLOCKSOURCE_CSI:
02952         lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02953         break;
02954       case UART_CLOCKSOURCE_LSE:
02955         lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02956         break;
02957       default:
02958         ret = HAL_ERROR;
02959         break;
02960     }
02961
02962     /* if proper clock source reported */
02963     if (lpuart_ker_ck_pres != 0U)
02964     {
02965       /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
02966       if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
02967           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
02968       {
02969         ret = HAL_ERROR;
02970       }
02971       else
02972       {
02973         switch (clocksource)
02974         {
02975           case UART_CLOCKSOURCE_D3PCLK1:
02976             pclk = HAL_RCCEx_GetD3PCLK1Freq();
02977             usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02978             break;
02979           case UART_CLOCKSOURCE_PLL2:
02980             HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02981             usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02982             break;
02983           case UART_CLOCKSOURCE_PLL3:
02984             HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02985             usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02986             break;
02987           case UART_CLOCKSOURCE_HSI:
02988             if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02989             {
02990               usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
02991             }
02992             else
02993             {
02994               usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02995             }
02996             break;
02997           case UART_CLOCKSOURCE_CSI:
02998             usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02999             break;
03000           case UART_CLOCKSOURCE_LSE:
03001             usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03002             break;
03003           default:
03004             ret = HAL_ERROR;
03005             break;
03006         }
03007
03008         /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
03009         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
03010         {
03011           huart->Instance->BRR = usartdiv;
03012         }
03013         else
03014         {
03015           ret = HAL_ERROR;
03016         }
03017       } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
03018     } /* if (lpuart_ker_ck_pres != 0) */
03019   }
03020   /* Check UART Over Sampling to set Baud Rate Register */
03021   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
03022   {
03023     switch (clocksource)
03024     {
03025       case UART_CLOCKSOURCE_D2PCLK1:
03026         pclk = HAL_RCC_GetPCLK1Freq();
03027         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03028         break;
03029       case UART_CLOCKSOURCE_D2PCLK2:
03030         pclk = HAL_RCC_GetPCLK2Freq();
03031         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03032         break;
03033       case UART_CLOCKSOURCE_PLL2:
03034         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
03035         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03036         break;
03037       case UART_CLOCKSOURCE_PLL3:
03038         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
03039         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03040         break;
03041       case UART_CLOCKSOURCE_HSI:
03042         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
03043         {
03044           usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
03045         }
03046         else
03047         {
03048           usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03049         }
03050         break;
03051       case UART_CLOCKSOURCE_CSI:
03052         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03053         break;
03054       case UART_CLOCKSOURCE_LSE:
03055         usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03056         break;
03057       default:
03058         ret = HAL_ERROR;
03059         break;
03060     }
03061
03062     /* USARTDIV must be greater than or equal to 0d16 */
03063     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03064     {
03065       brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
03066       brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
03067       huart->Instance->BRR = brrtemp;
03068     }
03069     else
03070     {
03071       ret = HAL_ERROR;
03072     }
03073   }
03074   else
03075   {
03076     switch (clocksource)
03077     {
03078       case UART_CLOCKSOURCE_D2PCLK1:
03079         pclk = HAL_RCC_GetPCLK1Freq();
03080         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03081         break;
03082       case UART_CLOCKSOURCE_D2PCLK2:
03083         pclk = HAL_RCC_GetPCLK2Freq();
03084         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03085         break;
03086       case UART_CLOCKSOURCE_PLL2:
03087         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
03088         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03089         break;
03090       case UART_CLOCKSOURCE_PLL3:
03091         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
03092         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03093         break;
03094       case UART_CLOCKSOURCE_HSI:
03095         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
03096         {
03097           usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
03098         }
03099         else
03100         {
03101           usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03102         }
03103         break;
03104       case UART_CLOCKSOURCE_CSI:
03105         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03106         break;
03107       case UART_CLOCKSOURCE_LSE:
03108         usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03109         break;
03110       default:
03111         ret = HAL_ERROR;
03112         break;
03113     }
03114
03115     /* USARTDIV must be greater than or equal to 0d16 */
03116     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03117     {
03118       huart->Instance->BRR = usartdiv;
03119     }
03120     else
03121     {
03122       ret = HAL_ERROR;
03123     }
03124   }
03125
03126   /* Initialize the number of data to process during RX/TX ISR execution */
03127   huart->NbTxDataToProcess = 1;
03128   huart->NbRxDataToProcess = 1;
03129
03130   /* Clear ISR function pointers */
03131   huart->RxISR = NULL;
03132   huart->TxISR = NULL;
03133
03134   return ret;
03135 }
03136
03137 /**
03138   * @brief Configure the UART peripheral advanced features.
03139   * @param huart UART handle.
03140   * @retval None
03141   */
03142 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
03143 {
03144   /* Check whether the set of advanced features to configure is properly set */
03145   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
03146
03147   /* if required, configure TX pin active level inversion */
03148   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
03149   {
03150     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
03151     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
03152   }
03153
03154   /* if required, configure RX pin active level inversion */
03155   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
03156   {
03157     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
03158     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
03159   }
03160
03161   /* if required, configure data inversion */
03162   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
03163   {
03164     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
03165     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
03166   }
03167
03168   /* if required, configure RX/TX pins swap */
03169   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
03170   {
03171     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
03172     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
03173   }
03174
03175   /* if required, configure RX overrun detection disabling */
03176   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
03177   {
03178     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
03179     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
03180   }
03181
03182   /* if required, configure DMA disabling on reception error */
03183   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
03184   {
03185     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
03186     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
03187   }
03188
03189   /* if required, configure auto Baud rate detection scheme */
03190   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
03191   {
03192     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
03193     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
03194     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
03195     /* set auto Baudrate detection parameters if detection is enabled */
03196     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
03197     {
03198       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
03199       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
03200     }
03201   }
03202
03203   /* if required, configure MSB first on communication line */
03204   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
03205   {
03206     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
03207     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
03208   }
03209 }
03210
03211 /**
03212   * @brief Check the UART Idle State.
03213   * @param huart UART handle.
03214   * @retval HAL status
03215   */
03216 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
03217 {
03218   uint32_t tickstart;
03219
03220   /* Initialize the UART ErrorCode */
03221   huart->ErrorCode = HAL_UART_ERROR_NONE;
03222
03223   /* Init tickstart for timeout managment*/
03224   tickstart = HAL_GetTick();
03225
03226   /* Check if the Transmitter is enabled */
03227   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
03228   {
03229     /* Wait until TEACK flag is set */
03230     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03231     {
03232       /* Timeout occurred */
03233       return HAL_TIMEOUT;
03234     }
03235   }
03236
03237   /* Check if the Receiver is enabled */
03238   if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03239   {
03240     /* Wait until REACK flag is set */
03241     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03242     {
03243       /* Timeout occurred */
03244       return HAL_TIMEOUT;
03245     }
03246   }
03247
03248   /* Initialize the UART State */
03249   huart->gState = HAL_UART_STATE_READY;
03250   huart->RxState = HAL_UART_STATE_READY;
03251
03252   __HAL_UNLOCK(huart);
03253
03254   return HAL_OK;
03255 }
03256
03257 /**
03258   * @brief  Handle UART Communication Timeout.
03259   * @param huart     UART handle.
03260   * @param Flag      Specifies the UART flag to check
03261   * @param Status    Flag status (SET or RESET)
03262   * @param Tickstart Tick start value
03263   * @param Timeout   Timeout duration
03264   * @retval HAL status
03265   */
03266 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
03267                                               uint32_t Tickstart, uint32_t Timeout)
03268 {
03269   /* Wait until flag is set */
03270   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
03271   {
03272     /* Check for the Timeout */
03273     if (Timeout != HAL_MAX_DELAY)
03274     {
03275       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
03276       {
03277         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
03278         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
03279         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03280
03281         huart->gState = HAL_UART_STATE_READY;
03282         huart->RxState = HAL_UART_STATE_READY;
03283
03284         __HAL_UNLOCK(huart);
03285
03286         return HAL_TIMEOUT;
03287       }
03288
03289       if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
03290       {
03291         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
03292         {
03293           /* Clear Receiver Timeout flag*/
03294           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
03295
03296           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
03297           CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
03298           CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03299
03300           huart->gState = HAL_UART_STATE_READY;
03301           huart->RxState = HAL_UART_STATE_READY;
03302           huart->ErrorCode = HAL_UART_ERROR_RTO;
03303
03304           /* Process Unlocked */
03305           __HAL_UNLOCK(huart);
03306
03307           return HAL_TIMEOUT;
03308         }
03309       }
03310     }
03311   }
03312   return HAL_OK;
03313 }
03314
03315
03316 /**
03317   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
03318   * @param  huart UART handle.
03319   * @retval None
03320   */
03321 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
03322 {
03323   /* Disable TXEIE, TCIE, TXFT interrupts */
03324   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
03325   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
03326
03327   /* At end of Tx process, restore huart->gState to Ready */
03328   huart->gState = HAL_UART_STATE_READY;
03329 }
03330
03331
03332 /**
03333   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
03334   * @param  huart UART handle.
03335   * @retval None
03336   */
03337 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
03338 {
03339   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
03340   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03341   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03342
03343   /* At end of Rx process, restore huart->RxState to Ready */
03344   huart->RxState = HAL_UART_STATE_READY;
03345
03346   /* Reset RxIsr function pointer */
03347   huart->RxISR = NULL;
03348 }
03349
03350
03351 /**
03352   * @brief DMA UART transmit process complete callback.
03353   * @param hdma DMA handle.
03354   * @retval None
03355   */
03356 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03357 {
03358   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03359
03360   /* DMA Normal mode */
03361   if (hdma->Init.Mode != DMA_CIRCULAR)
03362   {
03363     huart->TxXferCount = 0U;
03364
03365     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
03366        in the UART CR3 register */
03367     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
03368
03369     /* Enable the UART Transmit Complete Interrupt */
03370     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03371   }
03372   /* DMA Circular mode */
03373   else
03374   {
03375 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03376     /*Call registered Tx complete callback*/
03377     huart->TxCpltCallback(huart);
03378 #else
03379     /*Call legacy weak Tx complete callback*/
03380     HAL_UART_TxCpltCallback(huart);
03381 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03382   }
03383 }
03384
03385 /**
03386   * @brief DMA UART transmit process half complete callback.
03387   * @param hdma DMA handle.
03388   * @retval None
03389   */
03390 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
03391 {
03392   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03393
03394 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03395   /*Call registered Tx Half complete callback*/
03396   huart->TxHalfCpltCallback(huart);
03397 #else
03398   /*Call legacy weak Tx Half complete callback*/
03399   HAL_UART_TxHalfCpltCallback(huart);
03400 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03401 }
03402
03403 /**
03404   * @brief DMA UART receive process complete callback.
03405   * @param hdma DMA handle.
03406   * @retval None
03407   */
03408 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03409 {
03410   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03411
03412   /* DMA Normal mode */
03413   if (hdma->Init.Mode != DMA_CIRCULAR)
03414   {
03415     huart->RxXferCount = 0U;
03416
03417     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
03418     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03419     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03420
03421     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
03422        in the UART CR3 register */
03423     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03424
03425     /* At end of Rx process, restore huart->RxState to Ready */
03426     huart->RxState = HAL_UART_STATE_READY;
03427   }
03428
03429 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03430   /*Call registered Rx complete callback*/
03431   huart->RxCpltCallback(huart);
03432 #else
03433   /*Call legacy weak Rx complete callback*/
03434   HAL_UART_RxCpltCallback(huart);
03435 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03436 }
03437
03438 /**
03439   * @brief DMA UART receive process half complete callback.
03440   * @param hdma DMA handle.
03441   * @retval None
03442   */
03443 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
03444 {
03445   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03446
03447 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03448   /*Call registered Rx Half complete callback*/
03449   huart->RxHalfCpltCallback(huart);
03450 #else
03451   /*Call legacy weak Rx Half complete callback*/
03452   HAL_UART_RxHalfCpltCallback(huart);
03453 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03454 }
03455
03456 /**
03457   * @brief DMA UART communication error callback.
03458   * @param hdma DMA handle.
03459   * @retval None
03460   */
03461 static void UART_DMAError(DMA_HandleTypeDef *hdma)
03462 {
03463   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03464
03465   const HAL_UART_StateTypeDef gstate = huart->gState;
03466   const HAL_UART_StateTypeDef rxstate = huart->RxState;
03467
03468   /* Stop UART DMA Tx request if ongoing */
03469   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
03470       (gstate == HAL_UART_STATE_BUSY_TX))
03471   {
03472     huart->TxXferCount = 0U;
03473     UART_EndTxTransfer(huart);
03474   }
03475
03476   /* Stop UART DMA Rx request if ongoing */
03477   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
03478       (rxstate == HAL_UART_STATE_BUSY_RX))
03479   {
03480     huart->RxXferCount = 0U;
03481     UART_EndRxTransfer(huart);
03482   }
03483
03484   huart->ErrorCode |= HAL_UART_ERROR_DMA;
03485
03486 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03487   /*Call registered error callback*/
03488   huart->ErrorCallback(huart);
03489 #else
03490   /*Call legacy weak error callback*/
03491   HAL_UART_ErrorCallback(huart);
03492 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03493 }
03494
03495 /**
03496   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
03497   *         (To be called at end of DMA Abort procedure following error occurrence).
03498   * @param  hdma DMA handle.
03499   * @retval None
03500   */
03501 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03502 {
03503   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03504   huart->RxXferCount = 0U;
03505   huart->TxXferCount = 0U;
03506
03507 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03508   /*Call registered error callback*/
03509   huart->ErrorCallback(huart);
03510 #else
03511   /*Call legacy weak error callback*/
03512   HAL_UART_ErrorCallback(huart);
03513 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03514 }
03515
03516 /**
03517   * @brief  DMA UART Tx communication abort callback, when initiated by user
03518   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03519   * @note   When this callback is executed, User Abort complete call back is called only if no
03520   *         Abort still ongoing for Rx DMA Handle.
03521   * @param  hdma DMA handle.
03522   * @retval None
03523   */
03524 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03525 {
03526   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03527
03528   huart->hdmatx->XferAbortCallback = NULL;
03529
03530   /* Check if an Abort process is still ongoing */
03531   if (huart->hdmarx != NULL)
03532   {
03533     if (huart->hdmarx->XferAbortCallback != NULL)
03534     {
03535       return;
03536     }
03537   }
03538
03539   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03540   huart->TxXferCount = 0U;
03541   huart->RxXferCount = 0U;
03542
03543   /* Reset errorCode */
03544   huart->ErrorCode = HAL_UART_ERROR_NONE;
03545
03546   /* Clear the Error flags in the ICR register */
03547   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03548
03549   /* Flush the whole TX FIFO (if needed) */
03550   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03551   {
03552     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03553   }
03554
03555   /* Restore huart->gState and huart->RxState to Ready */
03556   huart->gState  = HAL_UART_STATE_READY;
03557   huart->RxState = HAL_UART_STATE_READY;
03558
03559   /* Call user Abort complete callback */
03560 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03561   /* Call registered Abort complete callback */
03562   huart->AbortCpltCallback(huart);
03563 #else
03564   /* Call legacy weak Abort complete callback */
03565   HAL_UART_AbortCpltCallback(huart);
03566 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03567 }
03568
03569
03570 /**
03571   * @brief  DMA UART Rx communication abort callback, when initiated by user
03572   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03573   * @note   When this callback is executed, User Abort complete call back is called only if no
03574   *         Abort still ongoing for Tx DMA Handle.
03575   * @param  hdma DMA handle.
03576   * @retval None
03577   */
03578 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03579 {
03580   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03581
03582   huart->hdmarx->XferAbortCallback = NULL;
03583
03584   /* Check if an Abort process is still ongoing */
03585   if (huart->hdmatx != NULL)
03586   {
03587     if (huart->hdmatx->XferAbortCallback != NULL)
03588     {
03589       return;
03590     }
03591   }
03592
03593   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03594   huart->TxXferCount = 0U;
03595   huart->RxXferCount = 0U;
03596
03597   /* Reset errorCode */
03598   huart->ErrorCode = HAL_UART_ERROR_NONE;
03599
03600   /* Clear the Error flags in the ICR register */
03601   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03602
03603   /* Discard the received data */
03604   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03605
03606   /* Restore huart->gState and huart->RxState to Ready */
03607   huart->gState  = HAL_UART_STATE_READY;
03608   huart->RxState = HAL_UART_STATE_READY;
03609
03610   /* Call user Abort complete callback */
03611 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03612   /* Call registered Abort complete callback */
03613   huart->AbortCpltCallback(huart);
03614 #else
03615   /* Call legacy weak Abort complete callback */
03616   HAL_UART_AbortCpltCallback(huart);
03617 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03618 }
03619
03620
03621 /**
03622   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
03623   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
03624   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
03625   *         and leads to user Tx Abort Complete callback execution).
03626   * @param  hdma DMA handle.
03627   * @retval None
03628   */
03629 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03630 {
03631   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03632
03633   huart->TxXferCount = 0U;
03634
03635   /* Flush the whole TX FIFO (if needed) */
03636   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03637   {
03638     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03639   }
03640
03641   /* Restore huart->gState to Ready */
03642   huart->gState = HAL_UART_STATE_READY;
03643
03644   /* Call user Abort complete callback */
03645 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03646   /* Call registered Abort Transmit Complete Callback */
03647   huart->AbortTransmitCpltCallback(huart);
03648 #else
03649   /* Call legacy weak Abort Transmit Complete Callback */
03650   HAL_UART_AbortTransmitCpltCallback(huart);
03651 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03652 }
03653
03654 /**
03655   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
03656   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
03657   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
03658   *         and leads to user Rx Abort Complete callback execution).
03659   * @param  hdma DMA handle.
03660   * @retval None
03661   */
03662 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03663 {
03664   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03665
03666   huart->RxXferCount = 0U;
03667
03668   /* Clear the Error flags in the ICR register */
03669   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03670
03671   /* Discard the received data */
03672   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03673
03674   /* Restore huart->RxState to Ready */
03675   huart->RxState = HAL_UART_STATE_READY;
03676
03677   /* Call user Abort complete callback */
03678 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03679   /* Call registered Abort Receive Complete Callback */
03680   huart->AbortReceiveCpltCallback(huart);
03681 #else
03682   /* Call legacy weak Abort Receive Complete Callback */
03683   HAL_UART_AbortReceiveCpltCallback(huart);
03684 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03685 }
03686
03687 /**
03688   * @brief TX interrrupt handler for 7 or 8 bits data word length .
03689   * @note   Function is called under interruption only, once
03690   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03691   * @param huart UART handle.
03692   * @retval None
03693   */
03694 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
03695 {
03696   /* Check that a Tx process is ongoing */
03697   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03698   {
03699     if (huart->TxXferCount == 0U)
03700     {
03701       /* Disable the UART Transmit Data Register Empty Interrupt */
03702       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
03703
03704       /* Enable the UART Transmit Complete Interrupt */
03705       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03706     }
03707     else
03708     {
03709       huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
03710       huart->pTxBuffPtr++;
03711       huart->TxXferCount--;
03712     }
03713   }
03714 }
03715
03716 /**
03717   * @brief TX interrrupt handler for 9 bits data word length.
03718   * @note   Function is called under interruption only, once
03719   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03720   * @param huart UART handle.
03721   * @retval None
03722   */
03723 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
03724 {
03725   uint16_t *tmp;
03726
03727   /* Check that a Tx process is ongoing */
03728   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03729   {
03730     if (huart->TxXferCount == 0U)
03731     {
03732       /* Disable the UART Transmit Data Register Empty Interrupt */
03733       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
03734
03735       /* Enable the UART Transmit Complete Interrupt */
03736       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03737     }
03738     else
03739     {
03740       tmp = (uint16_t *) huart->pTxBuffPtr;
03741       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
03742       huart->pTxBuffPtr += 2U;
03743       huart->TxXferCount--;
03744     }
03745   }
03746 }
03747
03748 /**
03749   * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
03750   * @note   Function is called under interruption only, once
03751   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03752   * @param huart UART handle.
03753   * @retval None
03754   */
03755 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
03756 {
03757   uint16_t  nb_tx_data;
03758
03759   /* Check that a Tx process is ongoing */
03760   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03761   {
03762     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03763     {
03764       if (huart->TxXferCount == 0U)
03765       {
03766         /* Disable the TX FIFO threshold interrupt */
03767         CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
03768
03769         /* Enable the UART Transmit Complete Interrupt */
03770         SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03771
03772         break; /* force exit loop */
03773       }
03774       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
03775       {
03776         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
03777         huart->pTxBuffPtr++;
03778         huart->TxXferCount--;
03779       }
03780       else
03781       {
03782         /* Nothing to do */
03783       }
03784     }
03785   }
03786 }
03787
03788 /**
03789   * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
03790   * @note   Function is called under interruption only, once
03791   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03792   * @param huart UART handle.
03793   * @retval None
03794   */
03795 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
03796 {
03797   uint16_t *tmp;
03798   uint16_t  nb_tx_data;
03799
03800   /* Check that a Tx process is ongoing */
03801   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03802   {
03803     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03804     {
03805       if (huart->TxXferCount == 0U)
03806       {
03807         /* Disable the TX FIFO threshold interrupt */
03808         CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
03809
03810         /* Enable the UART Transmit Complete Interrupt */
03811         SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03812
03813         break; /* force exit loop */
03814       }
03815       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
03816       {
03817         tmp = (uint16_t *) huart->pTxBuffPtr;
03818         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
03819         huart->pTxBuffPtr += 2U;
03820         huart->TxXferCount--;
03821       }
03822       else
03823       {
03824         /* Nothing to do */
03825       }
03826     }
03827   }
03828 }
03829
03830 /**
03831   * @brief  Wrap up transmission in non-blocking mode.
03832   * @param  huart pointer to a UART_HandleTypeDef structure that contains
03833   *                the configuration information for the specified UART module.
03834   * @retval None
03835   */
03836 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
03837 {
03838   /* Disable the UART Transmit Complete Interrupt */
03839   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03840
03841   /* Tx process is ended, restore huart->gState to Ready */
03842   huart->gState = HAL_UART_STATE_READY;
03843
03844   /* Cleat TxISR function pointer */
03845   huart->TxISR = NULL;
03846
03847 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03848   /*Call registered Tx complete callback*/
03849   huart->TxCpltCallback(huart);
03850 #else
03851   /*Call legacy weak Tx complete callback*/
03852   HAL_UART_TxCpltCallback(huart);
03853 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03854 }
03855
03856 /**
03857   * @brief RX interrrupt handler for 7 or 8 bits data word length .
03858   * @param huart UART handle.
03859   * @retval None
03860   */
03861 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
03862 {
03863   uint16_t uhMask = huart->Mask;
03864   uint16_t  uhdata;
03865
03866   /* Check that a Rx process is ongoing */
03867   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03868   {
03869     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03870     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
03871     huart->pRxBuffPtr++;
03872     huart->RxXferCount--;
03873
03874     if (huart->RxXferCount == 0U)
03875     {
03876       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
03877       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03878
03879       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03880       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03881
03882       /* Rx process is completed, restore huart->RxState to Ready */
03883       huart->RxState = HAL_UART_STATE_READY;
03884
03885       /* Clear RxISR function pointer */
03886       huart->RxISR = NULL;
03887
03888 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03889       /*Call registered Rx complete callback*/
03890       huart->RxCpltCallback(huart);
03891 #else
03892       /*Call legacy weak Rx complete callback*/
03893       HAL_UART_RxCpltCallback(huart);
03894 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03895     }
03896   }
03897   else
03898   {
03899     /* Clear RXNE interrupt flag */
03900     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03901   }
03902 }
03903
03904 /**
03905   * @brief RX interrrupt handler for 9 bits data word length .
03906   * @note   Function is called under interruption only, once
03907   *         interruptions have been enabled by HAL_UART_Receive_IT()
03908   * @param huart UART handle.
03909   * @retval None
03910   */
03911 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
03912 {
03913   uint16_t *tmp;
03914   uint16_t uhMask = huart->Mask;
03915   uint16_t  uhdata;
03916
03917   /* Check that a Rx process is ongoing */
03918   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03919   {
03920     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03921     tmp = (uint16_t *) huart->pRxBuffPtr ;
03922     *tmp = (uint16_t)(uhdata & uhMask);
03923     huart->pRxBuffPtr += 2U;
03924     huart->RxXferCount--;
03925
03926     if (huart->RxXferCount == 0U)
03927     {
03928       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
03929       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03930
03931       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03932       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03933
03934       /* Rx process is completed, restore huart->RxState to Ready */
03935       huart->RxState = HAL_UART_STATE_READY;
03936
03937       /* Clear RxISR function pointer */
03938       huart->RxISR = NULL;
03939
03940 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03941       /*Call registered Rx complete callback*/
03942       huart->RxCpltCallback(huart);
03943 #else
03944       /*Call legacy weak Rx complete callback*/
03945       HAL_UART_RxCpltCallback(huart);
03946 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03947     }
03948   }
03949   else
03950   {
03951     /* Clear RXNE interrupt flag */
03952     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03953   }
03954 }
03955
03956 /**
03957   * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
03958   * @note   Function is called under interruption only, once
03959   *         interruptions have been enabled by HAL_UART_Receive_IT()
03960   * @param huart UART handle.
03961   * @retval None
03962   */
03963 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
03964 {
03965   uint16_t  uhMask = huart->Mask;
03966   uint16_t  uhdata;
03967   uint16_t   nb_rx_data;
03968   uint16_t  rxdatacount;
03969
03970   /* Check that a Rx process is ongoing */
03971   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03972   {
03973     for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03974     {
03975       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03976       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
03977       huart->pRxBuffPtr++;
03978       huart->RxXferCount--;
03979
03980       if (huart->RxXferCount == 0U)
03981       {
03982         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
03983         CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03984
03985         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03986         CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03987
03988         /* Rx process is completed, restore huart->RxState to Ready */
03989         huart->RxState = HAL_UART_STATE_READY;
03990
03991         /* Clear RxISR function pointer */
03992         huart->RxISR = NULL;
03993
03994 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03995         /*Call registered Rx complete callback*/
03996         huart->RxCpltCallback(huart);
03997 #else
03998         /*Call legacy weak Rx complete callback*/
03999         HAL_UART_RxCpltCallback(huart);
04000 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04001       }
04002     }
04003
04004     /* When remaining number of bytes to receive is less than the RX FIFO
04005     threshold, next incoming frames are processed as if FIFO mode was
04006     disabled (i.e. one interrupt per received frame).
04007     */
04008     rxdatacount = huart->RxXferCount;
04009     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04010     {
04011       /* Disable the UART RXFT interrupt*/
04012       CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04013
04014       /* Update the RxISR function pointer */
04015       huart->RxISR = UART_RxISR_8BIT;
04016
04017       /* Enable the UART Data Register Not Empty interrupt */
04018       SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04019     }
04020   }
04021   else
04022   {
04023     /* Clear RXNE interrupt flag */
04024     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04025   }
04026 }
04027
04028 /**
04029   * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
04030   * @note   Function is called under interruption only, once
04031   *         interruptions have been enabled by HAL_UART_Receive_IT()
04032   * @param huart UART handle.
04033   * @retval None
04034   */
04035 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
04036 {
04037   uint16_t *tmp;
04038   uint16_t  uhMask = huart->Mask;
04039   uint16_t  uhdata;
04040   uint16_t   nb_rx_data;
04041   uint16_t  rxdatacount;
04042
04043   /* Check that a Rx process is ongoing */
04044   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04045   {
04046     for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
04047     {
04048       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04049       tmp = (uint16_t *) huart->pRxBuffPtr ;
04050       *tmp = (uint16_t)(uhdata & uhMask);
04051       huart->pRxBuffPtr += 2U;
04052       huart->RxXferCount--;
04053
04054       if (huart->RxXferCount == 0U)
04055       {
04056         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04057         CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04058
04059         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
04060         CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04061
04062         /* Rx process is completed, restore huart->RxState to Ready */
04063         huart->RxState = HAL_UART_STATE_READY;
04064
04065         /* Clear RxISR function pointer */
04066         huart->RxISR = NULL;
04067
04068 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04069         /*Call registered Rx complete callback*/
04070         huart->RxCpltCallback(huart);
04071 #else
04072         /*Call legacy weak Rx complete callback*/
04073         HAL_UART_RxCpltCallback(huart);
04074 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04075       }
04076     }
04077
04078     /* When remaining number of bytes to receive is less than the RX FIFO
04079     threshold, next incoming frames are processed as if FIFO mode was
04080     disabled (i.e. one interrupt per received frame).
04081     */
04082     rxdatacount = huart->RxXferCount;
04083     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04084     {
04085       /* Disable the UART RXFT interrupt*/
04086       CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04087
04088       /* Update the RxISR function pointer */
04089       huart->RxISR = UART_RxISR_16BIT;
04090
04091       /* Enable the UART Data Register Not Empty interrupt */
04092       SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04093     }
04094   }
04095   else
04096   {
04097     /* Clear RXNE interrupt flag */
04098     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04099   }
04100 }
04101
04102 /**
04103   * @}
04104   */
04105
04106 #endif /* HAL_UART_MODULE_ENABLED */
04107 /**
04108   * @}
04109   */
04110
04111 /**
04112   * @}
04113   */
04114
04115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart.h Source File

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stm32h7xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_UART_H
00022 #define STM32H7xx_HAL_UART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup UART
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup UART_Exported_Types UART Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief UART Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051                                            LPUART:
00052                                            =======
00053                                               Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
00054                                            where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
00055                                            UART:
00056                                            =====
00057                                            - If oversampling is 16 or in LIN mode,
00058                                               Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
00059                                            - If oversampling is 8,
00060                                               Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
00061                                               Baud Rate Register[3] =  0
00062                                               Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
00063                                            where uart_ker_ck_pres is the UART input clock divided by a prescaler */
00064
00065   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00066                                            This parameter can be a value of @ref UARTEx_Word_Length. */
00067
00068   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00069                                            This parameter can be a value of @ref UART_Stop_Bits. */
00070
00071   uint32_t Parity;                    /*!< Specifies the parity mode.
00072                                            This parameter can be a value of @ref UART_Parity
00073                                            @note When parity is enabled, the computed parity is inserted
00074                                                  at the MSB position of the transmitted data (9th bit when
00075                                                  the word length is set to 9 data bits; 8th bit when the
00076                                                  word length is set to 8 data bits). */
00077
00078   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00079                                            This parameter can be a value of @ref UART_Mode. */
00080
00081   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00082                                            or disabled.
00083                                            This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00084
00085   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
00086                                            This parameter can be a value of @ref UART_Over_Sampling. */
00087
00088   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00089                                            Selecting the single sample method increases the receiver tolerance to clock
00090                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00091
00092   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.
00093                                            This parameter can be a value of @ref UART_ClockPrescaler. */
00094
00095 } UART_InitTypeDef;
00096
00097 /**
00098   * @brief  UART Advanced Features initialization structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00103                                        Advanced Features may be initialized at the same time .
00104                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
00105
00106   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00107                                        This parameter can be a value of @ref UART_Tx_Inv. */
00108
00109   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00110                                        This parameter can be a value of @ref UART_Rx_Inv. */
00111
00112   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00113                                        vs negative/inverted logic).
00114                                        This parameter can be a value of @ref UART_Data_Inv. */
00115
00116   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00117                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00118
00119   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00120                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00121
00122   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00123                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00124
00125   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00126                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
00127
00128   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00129                                        detection is carried out.
00130                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00131
00132   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00133                                        This parameter can be a value of @ref UART_MSB_First. */
00134 } UART_AdvFeatureInitTypeDef;
00135
00136 /**
00137   * @brief HAL UART State definition
00138   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
00139   *        - gState contains UART state information related to global Handle management
00140   *          and also information related to Tx operations.
00141   *          gState value coding follow below described bitmap :
00142   *          b7-b6  Error information
00143   *             00 : No Error
00144   *             01 : (Not Used)
00145   *             10 : Timeout
00146   *             11 : Error
00147   *          b5     Peripheral initialization status
00148   *             0  : Reset (Peripheral not initialized)
00149   *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
00150   *          b4-b3  (not used)
00151   *             xx : Should be set to 00
00152   *          b2     Intrinsic process state
00153   *             0  : Ready
00154   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00155   *          b1     (not used)
00156   *             x  : Should be set to 0
00157   *          b0     Tx state
00158   *             0  : Ready (no Tx operation ongoing)
00159   *             1  : Busy (Tx operation ongoing)
00160   *        - RxState contains information related to Rx operations.
00161   *          RxState value coding follow below described bitmap :
00162   *          b7-b6  (not used)
00163   *             xx : Should be set to 00
00164   *          b5     Peripheral initialization status
00165   *             0  : Reset (Peripheral not initialized)
00166   *             1  : Init done (Peripheral not initialized)
00167   *          b4-b2  (not used)
00168   *            xxx : Should be set to 000
00169   *          b1     Rx state
00170   *             0  : Ready (no Rx operation ongoing)
00171   *             1  : Busy (Rx operation ongoing)
00172   *          b0     (not used)
00173   *             x  : Should be set to 0.
00174   */
00175 typedef uint32_t HAL_UART_StateTypeDef;
00176
00177 /**
00178   * @brief UART clock sources definition
00179   */
00180 typedef enum
00181 {
00182   UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
00183   UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
00184   UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
00185   UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
00186   UART_CLOCKSOURCE_PLL3       = 0x08U,    /*!< PLL3Q clock source         */
00187   UART_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source           */
00188   UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */
00189   UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */
00190   UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
00191 } UART_ClockSourceTypeDef;
00192
00193 /**
00194   * @brief  UART handle Structure definition
00195   */
00196 typedef struct __UART_HandleTypeDef
00197 {
00198   USART_TypeDef            *Instance;                /*!< UART registers base address        */
00199
00200   UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
00201
00202   UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
00203
00204   uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
00205
00206   uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
00207
00208   __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
00209
00210   uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
00211
00212   uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
00213
00214   __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
00215
00216   uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
00217
00218   uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
00219                                                           This parameter can be a value of @ref UARTEx_FIFO_mode. */
00220
00221   uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
00222
00223   uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
00224
00225   void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
00226
00227   void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
00228
00229   DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
00230
00231   DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
00232
00233   HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
00234
00235   __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
00236                                                           and also related to Tx operations.
00237                                                           This parameter can be a value of @ref HAL_UART_StateTypeDef */
00238
00239   __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.
00240                                                           This parameter can be a value of @ref HAL_UART_StateTypeDef */
00241
00242   __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
00243
00244 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00245   void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
00246   void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
00247   void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
00248   void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
00249   void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
00250   void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
00251   void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
00252   void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
00253   void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
00254   void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
00255   void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
00256
00257   void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
00258   void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
00259 #endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
00260
00261 } UART_HandleTypeDef;
00262
00263 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00264 /**
00265   * @brief  HAL UART Callback ID enumeration definition
00266   */
00267 typedef enum
00268 {
00269   HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
00270   HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
00271   HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
00272   HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
00273   HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
00274   HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
00275   HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
00276   HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
00277   HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
00278   HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
00279   HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
00280
00281   HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
00282   HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
00283
00284 } HAL_UART_CallbackIDTypeDef;
00285
00286 /**
00287   * @brief  HAL UART Callback pointer definition
00288   */
00289 typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
00290
00291 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00292
00293 /**
00294   * @}
00295   */
00296
00297 /* Exported constants --------------------------------------------------------*/
00298 /** @defgroup UART_Exported_Constants UART Exported Constants
00299   * @{
00300   */
00301
00302 /** @defgroup UART_State_Definition UART State Code Definition
00303   * @{
00304   */
00305 #define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
00306                                                           Value is allowed for gState and RxState */
00307 #define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
00308                                                           Value is allowed for gState and RxState */
00309 #define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
00310                                                           Value is allowed for gState only */
00311 #define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
00312                                                           Value is allowed for gState only */
00313 #define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
00314                                                           Value is allowed for RxState only */
00315 #define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
00316                                                           Not to be used for neither gState nor RxState.
00317                                                           Value is result of combination (Or) between gState and RxState values */
00318 #define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
00319                                                           Value is allowed for gState only */
00320 #define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
00321                                                           Value is allowed for gState only */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup UART_Error_Definition   UART Error Definition
00327   * @{
00328   */
00329 #define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */
00330 #define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */
00331 #define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */
00332 #define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */
00333 #define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */
00334 #define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */
00335 #define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */
00336
00337 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00338 #define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */
00339 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00345   * @{
00346   */
00347 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00348 #define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
00349 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00350 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup UART_Parity  UART Parity
00356   * @{
00357   */
00358 #define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
00359 #define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
00360 #define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00366   * @{
00367   */
00368 #define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
00369 #define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
00370 #define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
00371 #define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup UART_Mode UART Transfer Mode
00377   * @{
00378   */
00379 #define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
00380 #define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
00381 #define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup UART_State  UART State
00387   * @{
00388   */
00389 #define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
00390 #define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup UART_Over_Sampling UART Over Sampling
00396   * @{
00397   */
00398 #define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
00399 #define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00405   * @{
00406   */
00407 #define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
00408 #define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup UART_ClockPrescaler  UART Clock Prescaler
00414   * @{
00415   */
00416 #define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00417 #define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00418 #define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00419 #define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00420 #define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00421 #define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00422 #define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00423 #define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00424 #define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00425 #define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00426 #define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00427 #define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00433   * @{
00434   */
00435 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */
00436 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */
00437 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */
00438 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup UART_Receiver_Timeout UART Receiver Timeout
00444   * @{
00445   */
00446 #define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
00447 #define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00453   * @{
00454   */
00455 #define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
00456 #define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00462   * @{
00463   */
00464 #define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
00465 #define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup UART_DMA_Tx    UART DMA Tx
00471   * @{
00472   */
00473 #define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
00474 #define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup UART_DMA_Rx   UART DMA Rx
00480   * @{
00481   */
00482 #define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
00483 #define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00489   * @{
00490   */
00491 #define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
00492 #define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00498   * @{
00499   */
00500 #define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
00501 #define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup UART_Request_Parameters UART Request Parameters
00507   * @{
00508   */
00509 #define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00510 #define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
00511 #define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
00512 #define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00513 #define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00519   * @{
00520   */
00521 #define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
00522 #define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
00523 #define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
00524 #define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
00525 #define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
00526 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
00527 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
00528 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
00529 #define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00535   * @{
00536   */
00537 #define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
00538 #define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00544   * @{
00545   */
00546 #define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
00547 #define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00553   * @{
00554   */
00555 #define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
00556 #define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00562   * @{
00563   */
00564 #define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
00565 #define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00571   * @{
00572   */
00573 #define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
00574 #define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00580   * @{
00581   */
00582 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
00583 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00589   * @{
00590   */
00591 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
00592 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00598   * @{
00599   */
00600 #define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */
00601 #define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00607   * @{
00608   */
00609 #define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
00610 #define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
00611 /**
00612   * @}
00613   */
00614
00615 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00616   * @{
00617   */
00618 #define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
00619 #define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
00620 /**
00621   * @}
00622   */
00623
00624 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00625   * @{
00626   */
00627 #define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */
00628 /**
00629   * @}
00630   */
00631
00632 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00633   * @{
00634   */
00635 #define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */
00636 #define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */
00637 #define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00643   * @{
00644   */
00645 #define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
00646 #define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00652   * @{
00653   */
00654 #define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00660   * @{
00661   */
00662 #define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00668   * @{
00669   */
00670 #define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00676   * @{
00677   */
00678 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup UART_Flags     UART Status Flags
00684   *        Elements values convention: 0xXXXX
00685   *           - 0xXXXX  : Flag mask in the ISR register
00686   * @{
00687   */
00688 #define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
00689 #define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
00690 #define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
00691 #define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
00692 #define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
00693 #define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
00694 #define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
00695 #define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
00696 #define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
00697 #define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
00698 #define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
00699 #define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
00700 #define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
00701 #define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
00702 #define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
00703 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
00704 #define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
00705 #define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
00706 #define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
00707 #define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
00708 #define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
00709 #define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
00710 #define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
00711 #define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
00712 #define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
00713 #define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
00714 #define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00720   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00721   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00722   *           - XX  : Interrupt source register (2bits)
00723   *                 - 01: CR1 register
00724   *                 - 10: CR2 register
00725   *                 - 11: CR3 register
00726   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00727   *        Elements values convention: 000000000XXYYYYYb
00728   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00729   *           - XX  : Interrupt source register (2bits)
00730   *                 - 01: CR1 register
00731   *                 - 10: CR2 register
00732   *                 - 11: CR3 register
00733   *        Elements values convention: 0000ZZZZ00000000b
00734   *           - ZZZZ  : Flag position in the ISR register(4bits)
00735   * @{
00736   */
00737 #define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */
00738 #define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */
00739 #define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */
00740 #define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */
00741 #define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */
00742 #define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */
00743 #define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */
00744 #define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */
00745 #define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */
00746 #define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */
00747 #define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */
00748 #define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */
00749 #define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */
00750 #define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */
00751 #define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */
00752 #define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */
00753
00754 #define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */
00755
00756 #define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */
00757 #define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */
00758 #define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */
00759 /**
00760   * @}
00761   */
00762
00763 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00764   * @{
00765   */
00766 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00767 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00768 #define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
00769 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00770 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00771 #define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
00772 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00773 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00774 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00775 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00776 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00777 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
00778 /**
00779   * @}
00780   */
00781
00782
00783 /**
00784   * @}
00785   */
00786
00787 /* Exported macros -----------------------------------------------------------*/
00788 /** @defgroup UART_Exported_Macros UART Exported Macros
00789   * @{
00790   */
00791
00792 /** @brief  Reset UART handle states.
00793   * @param  __HANDLE__ UART handle.
00794   * @retval None
00795   */
00796 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00797 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00798                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00799                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00800                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00801                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00802                                                      } while(0U)
00803 #else
00804 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00805                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00806                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00807                                                      } while(0U)
00808 #endif /*USE_HAL_UART_REGISTER_CALLBACKS */
00809
00810 /** @brief  Flush the UART Data registers.
00811   * @param  __HANDLE__ specifies the UART Handle.
00812   * @retval None
00813   */
00814 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00815   do{                \
00816     SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00817     SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00818   }  while(0U)
00819
00820 /** @brief  Clear the specified UART pending flag.
00821   * @param  __HANDLE__ specifies the UART Handle.
00822   * @param  __FLAG__ specifies the flag to check.
00823   *          This parameter can be any combination of the following values:
00824   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00825   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00826   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00827   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00828   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00829   *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
00830   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00831   *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
00832   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
00833   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00834   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00835   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
00836   * @retval None
00837   */
00838 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00839
00840 /** @brief  Clear the UART PE pending flag.
00841   * @param  __HANDLE__ specifies the UART Handle.
00842   * @retval None
00843   */
00844 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00845
00846 /** @brief  Clear the UART FE pending flag.
00847   * @param  __HANDLE__ specifies the UART Handle.
00848   * @retval None
00849   */
00850 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00851
00852 /** @brief  Clear the UART NE pending flag.
00853   * @param  __HANDLE__ specifies the UART Handle.
00854   * @retval None
00855   */
00856 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00857
00858 /** @brief  Clear the UART ORE pending flag.
00859   * @param  __HANDLE__ specifies the UART Handle.
00860   * @retval None
00861   */
00862 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00863
00864 /** @brief  Clear the UART IDLE pending flag.
00865   * @param  __HANDLE__ specifies the UART Handle.
00866   * @retval None
00867   */
00868 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00869
00870 /** @brief  Clear the UART TX FIFO empty clear flag.
00871   * @param  __HANDLE__ specifies the UART Handle.
00872   * @retval None
00873   */
00874 #define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
00875
00876 /** @brief  Check whether the specified UART flag is set or not.
00877   * @param  __HANDLE__ specifies the UART Handle.
00878   * @param  __FLAG__ specifies the flag to check.
00879   *        This parameter can be one of the following values:
00880   *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
00881   *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
00882   *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
00883   *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
00884   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00885   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00886   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00887   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
00888   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00889   *            @arg @ref UART_FLAG_CMF   Character match flag
00890   *            @arg @ref UART_FLAG_BUSY  Busy flag
00891   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00892   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00893   *            @arg @ref UART_FLAG_CTS   CTS Change flag
00894   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00895   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00896   *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
00897   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00898   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00899   *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
00900   *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
00901   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00902   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00903   *            @arg @ref UART_FLAG_NE    Noise Error flag
00904   *            @arg @ref UART_FLAG_FE    Framing Error flag
00905   *            @arg @ref UART_FLAG_PE    Parity Error flag
00906   * @retval The new state of __FLAG__ (TRUE or FALSE).
00907   */
00908 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00909
00910 /** @brief  Enable the specified UART interrupt.
00911   * @param  __HANDLE__ specifies the UART Handle.
00912   * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
00913   *          This parameter can be one of the following values:
00914   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00915   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00916   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00917   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00918   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00919   *            @arg @ref UART_IT_CM    Character match interrupt
00920   *            @arg @ref UART_IT_CTS   CTS change interrupt
00921   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00922   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00923   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00924   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00925   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00926   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00927   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00928   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00929   *            @arg @ref UART_IT_PE    Parity Error interrupt
00930   *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
00931   * @retval None
00932   */
00933 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00934                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00935                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00936
00937
00938 /** @brief  Disable the specified UART interrupt.
00939   * @param  __HANDLE__ specifies the UART Handle.
00940   * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
00941   *          This parameter can be one of the following values:
00942   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00943   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00944   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00945   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00946   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00947   *            @arg @ref UART_IT_CM    Character match interrupt
00948   *            @arg @ref UART_IT_CTS   CTS change interrupt
00949   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00950   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00951   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00952   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00953   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00954   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00955   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00956   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00957   *            @arg @ref UART_IT_PE    Parity Error interrupt
00958   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
00959   * @retval None
00960   */
00961 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00962                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00963                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00964
00965 /** @brief  Check whether the specified UART interrupt has occurred or not.
00966   * @param  __HANDLE__ specifies the UART Handle.
00967   * @param  __INTERRUPT__ specifies the UART interrupt to check.
00968   *          This parameter can be one of the following values:
00969   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00970   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00971   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00972   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00973   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00974   *            @arg @ref UART_IT_CM    Character match interrupt
00975   *            @arg @ref UART_IT_CTS   CTS change interrupt
00976   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00977   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00978   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00979   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00980   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00981   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00982   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00983   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00984   *            @arg @ref UART_IT_PE    Parity Error interrupt
00985   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
00986   * @retval The new state of __INTERRUPT__ (SET or RESET).
00987   */
00988 #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00989                                                         & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
00990
00991 /** @brief  Check whether the specified UART interrupt source is enabled or not.
00992   * @param  __HANDLE__ specifies the UART Handle.
00993   * @param  __INTERRUPT__ specifies the UART interrupt source to check.
00994   *          This parameter can be one of the following values:
00995   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00996   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00997   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00998   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00999   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01000   *            @arg @ref UART_IT_CM    Character match interrupt
01001   *            @arg @ref UART_IT_CTS   CTS change interrupt
01002   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01003   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01004   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01005   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01006   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01007   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01008   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01009   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01010   *            @arg @ref UART_IT_PE    Parity Error interrupt
01011   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01012   * @retval The new state of __INTERRUPT__ (SET or RESET).
01013   */
01014 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
01015                                                                 (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
01016                                                                  (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
01017
01018 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
01019   * @param  __HANDLE__ specifies the UART Handle.
01020   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
01021   *                       to clear the corresponding interrupt
01022   *          This parameter can be one of the following values:
01023   *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
01024   *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
01025   *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
01026   *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
01027   *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
01028   *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
01029   *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
01030   *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
01031   *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
01032   *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
01033   *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
01034   *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
01035   * @retval None
01036   */
01037 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
01038
01039 /** @brief  Set a specific UART request flag.
01040   * @param  __HANDLE__ specifies the UART Handle.
01041   * @param  __REQ__ specifies the request flag to set
01042   *          This parameter can be one of the following values:
01043   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
01044   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
01045   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
01046   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
01047   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
01048   * @retval None
01049   */
01050 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
01051
01052 /** @brief  Enable the UART one bit sample method.
01053   * @param  __HANDLE__ specifies the UART Handle.
01054   * @retval None
01055   */
01056 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
01057
01058 /** @brief  Disable the UART one bit sample method.
01059   * @param  __HANDLE__ specifies the UART Handle.
01060   * @retval None
01061   */
01062 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
01063
01064 /** @brief  Enable UART.
01065   * @param  __HANDLE__ specifies the UART Handle.
01066   * @retval None
01067   */
01068 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
01069
01070 /** @brief  Disable UART.
01071   * @param  __HANDLE__ specifies the UART Handle.
01072   * @retval None
01073   */
01074 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
01075
01076 /** @brief  Enable CTS flow control.
01077   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
01078   *         without need to call HAL_UART_Init() function.
01079   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01080   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01081   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01082   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01083   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01084   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01085   * @param  __HANDLE__ specifies the UART Handle.
01086   * @retval None
01087   */
01088 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
01089   do{                                                      \
01090     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
01091     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
01092   } while(0U)
01093
01094 /** @brief  Disable CTS flow control.
01095   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
01096   *         without need to call HAL_UART_Init() function.
01097   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01098   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01099   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01100   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01101   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01102   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01103   * @param  __HANDLE__ specifies the UART Handle.
01104   * @retval None
01105   */
01106 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
01107   do{                                                       \
01108     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
01109     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
01110   } while(0U)
01111
01112 /** @brief  Enable RTS flow control.
01113   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
01114   *         without need to call HAL_UART_Init() function.
01115   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01116   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01117   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01118   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01119   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01120   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01121   * @param  __HANDLE__ specifies the UART Handle.
01122   * @retval None
01123   */
01124 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
01125   do{                                                     \
01126     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
01127     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
01128   } while(0U)
01129
01130 /** @brief  Disable RTS flow control.
01131   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01132   *         without need to call HAL_UART_Init() function.
01133   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01134   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01135   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01136   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01137   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01138   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01139   * @param  __HANDLE__ specifies the UART Handle.
01140   * @retval None
01141   */
01142 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
01143   do{                                                      \
01144     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01145     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
01146   } while(0U)
01147 /**
01148   * @}
01149   */
01150
01151 /* Private macros --------------------------------------------------------*/
01152 /** @defgroup UART_Private_Macros   UART Private Macros
01153   * @{
01154   */
01155 /** @brief  Get UART clok division factor from clock prescaler value.
01156   * @param  __CLOCKPRESCALER__ UART prescaler value.
01157   * @retval UART clock division factor
01158   */
01159 #define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
01160   (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
01161    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
01162    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
01163    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
01164    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
01165    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
01166    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
01167    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
01168    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
01169    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
01170    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
01171    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
01172
01173 /** @brief  BRR division operation to set BRR register with LPUART.
01174   * @param  __PCLK__ LPUART clock.
01175   * @param  __BAUD__ Baud rate set by the user.
01176   * @param  __CLOCKPRESCALER__ UART prescaler value.
01177   * @retval Division result
01178   */
01179 #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
01180                                                                       + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
01181
01182 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01183   * @param  __PCLK__ UART clock.
01184   * @param  __BAUD__ Baud rate set by the user.
01185   * @param  __CLOCKPRESCALER__ UART prescaler value.
01186   * @retval Division result
01187   */
01188 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
01189                                                                        + ((__BAUD__)/2U)) / (__BAUD__))
01190
01191 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01192   * @param  __PCLK__ UART clock.
01193   * @param  __BAUD__ Baud rate set by the user.
01194   * @param  __CLOCKPRESCALER__ UART prescaler value.
01195   * @retval Division result
01196   */
01197 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
01198                                                                        + ((__BAUD__)/2U)) / (__BAUD__))
01199
01200 /** @brief  Check whether or not UART instance is Low Power UART.
01201   * @param  __HANDLE__ specifies the UART Handle.
01202   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01203   */
01204 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
01205
01206 /** @brief  Check UART Baud rate.
01207   * @param  __BAUDRATE__ Baudrate specified by the user.
01208   *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
01209   *         divided by the smallest oversampling used on the USART (i.e. 8)
01210   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01211   */
01212 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
01213
01214 /** @brief  Check UART assertion time.
01215   * @param  __TIME__ 5-bit value assertion time.
01216   * @retval Test result (TRUE or FALSE).
01217   */
01218 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01219
01220 /** @brief  Check UART deassertion time.
01221   * @param  __TIME__ 5-bit value deassertion time.
01222   * @retval Test result (TRUE or FALSE).
01223   */
01224 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01225
01226 /**
01227   * @brief Ensure that UART frame number of stop bits is valid.
01228   * @param __STOPBITS__ UART frame number of stop bits.
01229   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01230   */
01231 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01232                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01233                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01234                                         ((__STOPBITS__) == UART_STOPBITS_2))
01235
01236 /**
01237   * @brief Ensure that LPUART frame number of stop bits is valid.
01238   * @param __STOPBITS__ LPUART frame number of stop bits.
01239   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01240   */
01241 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01242                                           ((__STOPBITS__) == UART_STOPBITS_2))
01243
01244 /**
01245   * @brief Ensure that UART frame parity is valid.
01246   * @param __PARITY__ UART frame parity.
01247   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01248   */
01249 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01250                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01251                                     ((__PARITY__) == UART_PARITY_ODD))
01252
01253 /**
01254   * @brief Ensure that UART hardware flow control is valid.
01255   * @param __CONTROL__ UART hardware flow control.
01256   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01257   */
01258 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01259   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01260    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01261    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01262    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01263
01264 /**
01265   * @brief Ensure that UART communication mode is valid.
01266   * @param __MODE__ UART communication mode.
01267   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01268   */
01269 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
01270
01271 /**
01272   * @brief Ensure that UART state is valid.
01273   * @param __STATE__ UART state.
01274   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01275   */
01276 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01277                                   ((__STATE__) == UART_STATE_ENABLE))
01278
01279 /**
01280   * @brief Ensure that UART oversampling is valid.
01281   * @param __SAMPLING__ UART oversampling.
01282   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01283   */
01284 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01285                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01286
01287 /**
01288   * @brief Ensure that UART frame sampling is valid.
01289   * @param __ONEBIT__ UART frame sampling.
01290   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01291   */
01292 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01293                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01294
01295 /**
01296   * @brief Ensure that UART auto Baud rate detection mode is valid.
01297   * @param __MODE__ UART auto Baud rate detection mode.
01298   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01299   */
01300 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01301                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01302                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01303                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01304
01305 /**
01306   * @brief Ensure that UART receiver timeout setting is valid.
01307   * @param __TIMEOUT__ UART receiver timeout setting.
01308   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01309   */
01310 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01311                                                 ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01312
01313 /** @brief  Check the receiver timeout value.
01314   * @note   The maximum UART receiver timeout value is 0xFFFFFF.
01315   * @param  __TIMEOUTVALUE__ receiver timeout value.
01316   * @retval Test result (TRUE or FALSE)
01317   */
01318 #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
01319
01320 /**
01321   * @brief Ensure that UART LIN state is valid.
01322   * @param __LIN__ UART LIN state.
01323   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01324   */
01325 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01326                                      ((__LIN__) == UART_LIN_ENABLE))
01327
01328 /**
01329   * @brief Ensure that UART LIN break detection length is valid.
01330   * @param __LENGTH__ UART LIN break detection length.
01331   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01332   */
01333 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01334                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01335
01336 /**
01337   * @brief Ensure that UART DMA TX state is valid.
01338   * @param __DMATX__ UART DMA TX state.
01339   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01340   */
01341 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01342                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01343
01344 /**
01345   * @brief Ensure that UART DMA RX state is valid.
01346   * @param __DMARX__ UART DMA RX state.
01347   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01348   */
01349 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01350                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01351
01352 /**
01353   * @brief Ensure that UART half-duplex state is valid.
01354   * @param __HDSEL__ UART half-duplex state.
01355   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01356   */
01357 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01358                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01359
01360 /**
01361   * @brief Ensure that UART wake-up method is valid.
01362   * @param __WAKEUP__ UART wake-up method .
01363   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01364   */
01365 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01366                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01367
01368 /**
01369   * @brief Ensure that UART request parameter is valid.
01370   * @param __PARAM__ UART request parameter.
01371   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01372   */
01373 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01374                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01375                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01376                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01377                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01378
01379 /**
01380   * @brief Ensure that UART advanced features initialization is valid.
01381   * @param __INIT__ UART advanced features initialization.
01382   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01383   */
01384 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01385                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01386                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01387                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01388                                                             UART_ADVFEATURE_SWAP_INIT              | \
01389                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01390                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01391                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01392                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01393
01394 /**
01395   * @brief Ensure that UART frame TX inversion setting is valid.
01396   * @param __TXINV__ UART frame TX inversion setting.
01397   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01398   */
01399 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01400                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01401
01402 /**
01403   * @brief Ensure that UART frame RX inversion setting is valid.
01404   * @param __RXINV__ UART frame RX inversion setting.
01405   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01406   */
01407 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01408                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01409
01410 /**
01411   * @brief Ensure that UART frame data inversion setting is valid.
01412   * @param __DATAINV__ UART frame data inversion setting.
01413   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01414   */
01415 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01416                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01417
01418 /**
01419   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01420   * @param __SWAP__ UART frame RX/TX pins swap setting.
01421   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01422   */
01423 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01424                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01425
01426 /**
01427   * @brief Ensure that UART frame overrun setting is valid.
01428   * @param __OVERRUN__ UART frame overrun setting.
01429   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01430   */
01431 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01432                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01433
01434 /**
01435   * @brief Ensure that UART auto Baud rate state is valid.
01436   * @param __AUTOBAUDRATE__ UART auto Baud rate state.
01437   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01438   */
01439 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01440                                                             ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01441
01442 /**
01443   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01444   * @param __DMA__ UART DMA enabling or disabling on error setting.
01445   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01446   */
01447 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01448                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01449
01450 /**
01451   * @brief Ensure that UART frame MSB first setting is valid.
01452   * @param __MSBFIRST__ UART frame MSB first setting.
01453   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01454   */
01455 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01456                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01457
01458 /**
01459   * @brief Ensure that UART stop mode state is valid.
01460   * @param __STOPMODE__ UART stop mode state.
01461   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01462   */
01463 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01464                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01465
01466 /**
01467   * @brief Ensure that UART mute mode state is valid.
01468   * @param __MUTE__ UART mute mode state.
01469   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01470   */
01471 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01472                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01473
01474 /**
01475   * @brief Ensure that UART wake-up selection is valid.
01476   * @param __WAKE__ UART wake-up selection.
01477   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01478   */
01479 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
01480                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
01481                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01482
01483 /**
01484   * @brief Ensure that UART driver enable polarity is valid.
01485   * @param __POLARITY__ UART driver enable polarity.
01486   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01487   */
01488 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01489                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01490
01491 /**
01492   * @brief Ensure that UART Prescaler is valid.
01493   * @param __CLOCKPRESCALER__ UART Prescaler value.
01494   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01495   */
01496 #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
01497                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
01498                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
01499                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
01500                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
01501                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
01502                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
01503                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
01504                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
01505                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
01506                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
01507                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
01508
01509 /**
01510   * @}
01511   */
01512
01513 /* Include UART HAL Extended module */
01514 #include "stm32h7xx_hal_uart_ex.h"
01515
01516
01517 /* Exported functions --------------------------------------------------------*/
01518 /** @addtogroup UART_Exported_Functions UART Exported Functions
01519   * @{
01520   */
01521
01522 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01523   * @{
01524   */
01525
01526 /* Initialization and de-initialization functions  ****************************/
01527 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01528 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01529 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01530 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01531 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
01532 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01533 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01534
01535 /* Callbacks Register/UnRegister functions  ***********************************/
01536 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01537 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
01538                                             pUART_CallbackTypeDef pCallback);
01539 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
01540 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01541
01542 /**
01543   * @}
01544   */
01545
01546 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01547   * @{
01548   */
01549
01550 /* IO operation functions *****************************************************/
01551 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01552 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01553 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01554 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01555 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01556 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01557 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01558 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01559 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01560 /* Transfer Abort functions */
01561 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01562 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01563 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01564 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01565 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01566 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01567
01568 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01569 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01570 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01571 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01572 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01573 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01574 void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
01575 void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
01576 void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
01577
01578 /**
01579   * @}
01580   */
01581
01582 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01583   * @{
01584   */
01585
01586 /* Peripheral Control functions  ************************************************/
01587 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
01588 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
01589 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
01590
01591 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01592 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01593 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01594 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01595 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01596 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01597
01598 /**
01599   * @}
01600   */
01601
01602 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01603   * @{
01604   */
01605
01606 /* Peripheral State and Errors functions  **************************************************/
01607 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01608 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
01609
01610 /**
01611   * @}
01612   */
01613
01614 /**
01615   * @}
01616   */
01617
01618 /* Private functions -----------------------------------------------------------*/
01619 /** @addtogroup UART_Private_Functions UART Private Functions
01620   * @{
01621   */
01622 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01623 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
01624 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01625 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01626 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01627 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
01628                                               uint32_t Tickstart, uint32_t Timeout);
01629 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01630
01631 /**
01632   * @}
01633   */
01634
01635 /**
01636   * @}
01637   */
01638
01639 /**
01640   * @}
01641   */
01642
01643 #ifdef __cplusplus
01644 }
01645 #endif
01646
01647 #endif /* STM32H7xx_HAL_UART_H */
01648
01649 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart_ex.c Source File

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stm32h7xx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended UART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### UART peripheral extended features  #####
00015   ==============================================================================
00016
00017     (#) Declare a UART_HandleTypeDef handle structure.
00018
00019     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00020         by calling the HAL_RS485Ex_Init() API.
00021
00022     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00023
00024         -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
00025             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00026             configured prior starting RX/TX transfers.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00033   * All rights reserved.</center></h2>
00034   *
00035   * This software component is licensed by ST under BSD 3-Clause license,
00036   * the "License"; You may not use this file except in compliance with the
00037   * License. You may obtain a copy of the License at:
00038   *                        opensource.org/licenses/BSD-3-Clause
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx_hal.h"
00045
00046 /** @addtogroup STM32H7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup UARTEx UARTEx
00051   * @brief UART Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_UART_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
00060   * @{
00061   */
00062 /* UART RX FIFO depth */
00063 #define RX_FIFO_DEPTH 8U
00064
00065 /* UART TX FIFO depth */
00066 #define TX_FIFO_DEPTH 8U
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00075   * @{
00076   */
00077 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00078 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart            UART handle.
00151   * @param Polarity         Select the driver enable polarity.
00152   *          This parameter can be one of the following values:
00153   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00154   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00155   * @param AssertionTime    Driver Enable assertion time:
00156   *       5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *       signal and the beginning of the start bit. It is expressed in sample time
00158   *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime  Driver Enable deassertion time:
00160   *       5-bit value defining the time between the end of the last stop bit, in a
00161   *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *       oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00167                                    uint32_t DeassertionTime)
00168 {
00169   uint32_t temp;
00170
00171   /* Check the UART handle allocation */
00172   if (huart == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176   /* Check the Driver Enable UART instance */
00177   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00178
00179   /* Check the Driver Enable polarity */
00180   assert_param(IS_UART_DE_POLARITY(Polarity));
00181
00182   /* Check the Driver Enable assertion time */
00183   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00184
00185   /* Check the Driver Enable deassertion time */
00186   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00187
00188   if (huart->gState == HAL_UART_STATE_RESET)
00189   {
00190     /* Allocate lock resource and initialize it */
00191     huart->Lock = HAL_UNLOCKED;
00192
00193 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00194     UART_InitCallbacksToDefault(huart);
00195
00196     if (huart->MspInitCallback == NULL)
00197     {
00198       huart->MspInitCallback = HAL_UART_MspInit;
00199     }
00200
00201     /* Init the low level hardware */
00202     huart->MspInitCallback(huart);
00203 #else
00204     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00205     HAL_UART_MspInit(huart);
00206 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00207   }
00208
00209   huart->gState = HAL_UART_STATE_BUSY;
00210
00211   /* Disable the Peripheral */
00212   __HAL_UART_DISABLE(huart);
00213
00214   /* Set the UART Communication parameters */
00215   if (UART_SetConfig(huart) == HAL_ERROR)
00216   {
00217     return HAL_ERROR;
00218   }
00219
00220   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00221   {
00222     UART_AdvFeatureConfig(huart);
00223   }
00224
00225   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00226   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00227
00228   /* Set the Driver Enable polarity */
00229   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00230
00231   /* Set the Driver Enable assertion and deassertion times */
00232   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00233   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00234   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
00235
00236   /* Enable the Peripheral */
00237   __HAL_UART_ENABLE(huart);
00238
00239   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00240   return (UART_CheckIdleState(huart));
00241 }
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
00248   *  @brief Extended functions
00249   *
00250 @verbatim
00251  ===============================================================================
00252                       ##### IO operation functions #####
00253  ===============================================================================
00254     This subsection provides a set of Wakeup and FIFO mode related callback functions.
00255
00256     (#) Wakeup from Stop mode Callback:
00257         (+) HAL_UARTEx_WakeupCallback()
00258
00259     (#) TX/RX Fifos Callbacks:
00260         (+) HAL_UARTEx_RxFifoFullCallback()
00261         (+) HAL_UARTEx_TxFifoEmptyCallback()
00262
00263 @endverbatim
00264   * @{
00265   */
00266
00267 /**
00268   * @brief UART wakeup from Stop mode callback.
00269   * @param huart UART handle.
00270   * @retval None
00271   */
00272 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(huart);
00276
00277   /* NOTE : This function should not be modified, when the callback is needed,
00278             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00279    */
00280 }
00281
00282 /**
00283   * @brief  UART RX Fifo full callback.
00284   * @param  huart UART handle.
00285   * @retval None
00286   */
00287 __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(huart);
00291
00292   /* NOTE : This function should not be modified, when the callback is needed,
00293             the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
00294    */
00295 }
00296
00297 /**
00298   * @brief  UART TX Fifo empty callback.
00299   * @param  huart UART handle.
00300   * @retval None
00301   */
00302 __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(huart);
00306
00307   /* NOTE : This function should not be modified, when the callback is needed,
00308             the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
00309    */
00310 }
00311
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00317   * @brief    Extended Peripheral Control functions
00318   *
00319 @verbatim
00320  ===============================================================================
00321                       ##### Peripheral Control functions #####
00322  ===============================================================================
00323     [..] This section provides the following functions:
00324      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00325          detection length to more than 4 bits for multiprocessor address mark wake up.
00326      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00327          trigger: address match, Start Bit detection or RXNE bit status.
00328      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00329      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00330      (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
00331      (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
00332      (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00333      (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00334
00335 @endverbatim
00336   * @{
00337   */
00338
00339 /**
00340   * @brief By default in multiprocessor mode, when the wake up method is set
00341   *        to address mark, the UART handles only 4-bit long addresses detection;
00342   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00343   *        long).
00344   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00345   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00346   * @param huart         UART handle.
00347   * @param AddressLength This parameter can be one of the following values:
00348   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00349   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00350   * @retval HAL status
00351   */
00352 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00353 {
00354   /* Check the UART handle allocation */
00355   if (huart == NULL)
00356   {
00357     return HAL_ERROR;
00358   }
00359
00360   /* Check the address length parameter */
00361   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00362
00363   huart->gState = HAL_UART_STATE_BUSY;
00364
00365   /* Disable the Peripheral */
00366   __HAL_UART_DISABLE(huart);
00367
00368   /* Set the address length */
00369   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00370
00371   /* Enable the Peripheral */
00372   __HAL_UART_ENABLE(huart);
00373
00374   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00375   return (UART_CheckIdleState(huart));
00376 }
00377
00378 /**
00379   * @brief Set Wakeup from Stop mode interrupt flag selection.
00380   * @note It is the application responsibility to enable the interrupt used as
00381   *       usart_wkup interrupt source before entering low-power mode.
00382   * @param huart           UART handle.
00383   * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
00384   *          This parameter can be one of the following values:
00385   *          @arg @ref UART_WAKEUP_ON_ADDRESS
00386   *          @arg @ref UART_WAKEUP_ON_STARTBIT
00387   *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00391 {
00392   HAL_StatusTypeDef status = HAL_OK;
00393   uint32_t tickstart;
00394
00395   /* check the wake-up from stop mode UART instance */
00396   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00397   /* check the wake-up selection parameter */
00398   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00399
00400   /* Process Locked */
00401   __HAL_LOCK(huart);
00402
00403   huart->gState = HAL_UART_STATE_BUSY;
00404
00405   /* Disable the Peripheral */
00406   __HAL_UART_DISABLE(huart);
00407
00408   /* Set the wake-up selection scheme */
00409   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00410
00411   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00412   {
00413     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00414   }
00415
00416   /* Enable the Peripheral */
00417   __HAL_UART_ENABLE(huart);
00418
00419   /* Init tickstart for timeout managment*/
00420   tickstart = HAL_GetTick();
00421
00422   /* Wait until REACK flag is set */
00423   if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00424   {
00425     status = HAL_TIMEOUT;
00426   }
00427   else
00428   {
00429     /* Initialize the UART State */
00430     huart->gState = HAL_UART_STATE_READY;
00431   }
00432
00433   /* Process Unlocked */
00434   __HAL_UNLOCK(huart);
00435
00436   return status;
00437 }
00438
00439 /**
00440   * @brief Enable UART Stop Mode.
00441   * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
00442   * @param huart UART handle.
00443   * @retval HAL status
00444   */
00445 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00446 {
00447   /* Process Locked */
00448   __HAL_LOCK(huart);
00449
00450   /* Set UESM bit */
00451   SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00452
00453   /* Process Unlocked */
00454   __HAL_UNLOCK(huart);
00455
00456   return HAL_OK;
00457 }
00458
00459 /**
00460   * @brief Disable UART Stop Mode.
00461   * @param huart UART handle.
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00465 {
00466   /* Process Locked */
00467   __HAL_LOCK(huart);
00468
00469   /* Clear UESM bit */
00470   CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00471
00472   /* Process Unlocked */
00473   __HAL_UNLOCK(huart);
00474
00475   return HAL_OK;
00476 }
00477
00478 /**
00479   * @brief  Enable the FIFO mode.
00480   * @param huart      UART handle.
00481   * @retval HAL status
00482   */
00483 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
00484 {
00485   uint32_t tmpcr1;
00486
00487   /* Check parameters */
00488   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00489
00490   /* Process Locked */
00491   __HAL_LOCK(huart);
00492
00493   huart->gState = HAL_UART_STATE_BUSY;
00494
00495   /* Save actual UART configuration */
00496   tmpcr1 = READ_REG(huart->Instance->CR1);
00497
00498   /* Disable UART */
00499   __HAL_UART_DISABLE(huart);
00500
00501   /* Enable FIFO mode */
00502   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00503   huart->FifoMode = UART_FIFOMODE_ENABLE;
00504
00505   /* Restore UART configuration */
00506   WRITE_REG(huart->Instance->CR1, tmpcr1);
00507
00508   /* Determine the number of data to process during RX/TX ISR execution */
00509   UARTEx_SetNbDataToProcess(huart);
00510
00511   huart->gState = HAL_UART_STATE_READY;
00512
00513   /* Process Unlocked */
00514   __HAL_UNLOCK(huart);
00515
00516   return HAL_OK;
00517 }
00518
00519 /**
00520   * @brief  Disable the FIFO mode.
00521   * @param huart      UART handle.
00522   * @retval HAL status
00523   */
00524 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
00525 {
00526   uint32_t tmpcr1;
00527
00528   /* Check parameters */
00529   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00530
00531   /* Process Locked */
00532   __HAL_LOCK(huart);
00533
00534   huart->gState = HAL_UART_STATE_BUSY;
00535
00536   /* Save actual UART configuration */
00537   tmpcr1 = READ_REG(huart->Instance->CR1);
00538
00539   /* Disable UART */
00540   __HAL_UART_DISABLE(huart);
00541
00542   /* Enable FIFO mode */
00543   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00544   huart->FifoMode = UART_FIFOMODE_DISABLE;
00545
00546   /* Restore UART configuration */
00547   WRITE_REG(huart->Instance->CR1, tmpcr1);
00548
00549   huart->gState = HAL_UART_STATE_READY;
00550
00551   /* Process Unlocked */
00552   __HAL_UNLOCK(huart);
00553
00554   return HAL_OK;
00555 }
00556
00557 /**
00558   * @brief  Set the TXFIFO threshold.
00559   * @param huart      UART handle.
00560   * @param Threshold  TX FIFO threshold value
00561   *          This parameter can be one of the following values:
00562   *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
00563   *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
00564   *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
00565   *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
00566   *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
00567   *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
00568   * @retval HAL status
00569   */
00570 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00571 {
00572   uint32_t tmpcr1;
00573
00574   /* Check parameters */
00575   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00576   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
00577
00578   /* Process Locked */
00579   __HAL_LOCK(huart);
00580
00581   huart->gState = HAL_UART_STATE_BUSY;
00582
00583   /* Save actual UART configuration */
00584   tmpcr1 = READ_REG(huart->Instance->CR1);
00585
00586   /* Disable UART */
00587   __HAL_UART_DISABLE(huart);
00588
00589   /* Update TX threshold configuration */
00590   MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00591
00592   /* Determine the number of data to process during RX/TX ISR execution */
00593   UARTEx_SetNbDataToProcess(huart);
00594
00595   /* Restore UART configuration */
00596   WRITE_REG(huart->Instance->CR1, tmpcr1);
00597
00598   huart->gState = HAL_UART_STATE_READY;
00599
00600   /* Process Unlocked */
00601   __HAL_UNLOCK(huart);
00602
00603   return HAL_OK;
00604 }
00605
00606 /**
00607   * @brief  Set the RXFIFO threshold.
00608   * @param huart      UART handle.
00609   * @param Threshold  RX FIFO threshold value
00610   *          This parameter can be one of the following values:
00611   *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
00612   *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
00613   *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
00614   *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
00615   *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
00616   *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
00617   * @retval HAL status
00618   */
00619 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00620 {
00621   uint32_t tmpcr1;
00622
00623   /* Check the parameters */
00624   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00625   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
00626
00627   /* Process Locked */
00628   __HAL_LOCK(huart);
00629
00630   huart->gState = HAL_UART_STATE_BUSY;
00631
00632   /* Save actual UART configuration */
00633   tmpcr1 = READ_REG(huart->Instance->CR1);
00634
00635   /* Disable UART */
00636   __HAL_UART_DISABLE(huart);
00637
00638   /* Update RX threshold configuration */
00639   MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00640
00641   /* Determine the number of data to process during RX/TX ISR execution */
00642   UARTEx_SetNbDataToProcess(huart);
00643
00644   /* Restore UART configuration */
00645   WRITE_REG(huart->Instance->CR1, tmpcr1);
00646
00647   huart->gState = HAL_UART_STATE_READY;
00648
00649   /* Process Unlocked */
00650   __HAL_UNLOCK(huart);
00651
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @}
00657   */
00658
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup UARTEx_Private_Functions
00664   * @{
00665   */
00666
00667 /**
00668   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
00669   * @param huart           UART handle.
00670   * @param WakeUpSelection UART wake up from stop mode parameters.
00671   * @retval None
00672   */
00673 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00674 {
00675   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
00676
00677   /* Set the USART address length */
00678   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
00679
00680   /* Set the USART address node */
00681   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
00682 }
00683
00684 /**
00685   * @brief Calculate the number of data to process in RX/TX ISR.
00686   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00687   *       the UART configuration registers.
00688   * @param huart UART handle.
00689   * @retval None
00690   */
00691 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
00692 {
00693   uint8_t rx_fifo_depth;
00694   uint8_t tx_fifo_depth;
00695   uint8_t rx_fifo_threshold;
00696   uint8_t tx_fifo_threshold;
00697   uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00698   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00699
00700   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
00701   {
00702     huart->NbTxDataToProcess = 1U;
00703     huart->NbRxDataToProcess = 1U;
00704   }
00705   else
00706   {
00707     rx_fifo_depth = RX_FIFO_DEPTH;
00708     tx_fifo_depth = TX_FIFO_DEPTH;
00709     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00710     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00711     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00712     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00713   }
00714 }
00715 /**
00716   * @}
00717   */
00718
00719 #endif /* HAL_UART_MODULE_ENABLED */
00720
00721 /**
00722   * @}
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_uart_ex.h Source File

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stm32h7xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_UART_EX_H
00022 #define STM32H7xx_HAL_UART_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup UARTEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  UART wake up from stop mode parameters
00046   */
00047 typedef struct
00048 {
00049   uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
00050                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00051                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00052                                     be filled up. */
00053
00054   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00055                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00056
00057   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00058 } UART_WakeUpTypeDef;
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported constants --------------------------------------------------------*/
00065 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00070   * @{
00071   */
00072 #define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
00073 #define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
00074 #define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
00080   * @{
00081   */
00082 #define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
00083 #define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
00089   * @brief    UART FIFO mode
00090   * @{
00091   */
00092 #define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
00093 #define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
00099   * @brief    UART TXFIFO threshold level
00100   * @{
00101   */
00102 #define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00103 #define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00104 #define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00105 #define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00106 #define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00107 #define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
00113   * @brief    UART RXFIFO threshold level
00114   * @{
00115   */
00116 #define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00117 #define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00118 #define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00119 #define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00120 #define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00121 #define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported macros -----------------------------------------------------------*/
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @addtogroup UARTEx_Exported_Functions
00133   * @{
00134   */
00135
00136 /** @addtogroup UARTEx_Exported_Functions_Group1
00137   * @{
00138   */
00139
00140 /* Initialization and de-initialization functions  ****************************/
00141 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00142                                    uint32_t DeassertionTime);
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @addtogroup UARTEx_Exported_Functions_Group2
00149   * @{
00150   */
00151
00152 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00153
00154 void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
00155 void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @addtogroup UARTEx_Exported_Functions_Group3
00162   * @{
00163   */
00164
00165 /* Peripheral Control functions  **********************************************/
00166 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00167 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00168 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00169
00170 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00171
00172 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
00173 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
00174 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00175 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Private macros ------------------------------------------------------------*/
00186 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00187   * @{
00188   */
00189
00190 /** @brief  Report the UART clock source.
00191   * @param  __HANDLE__ specifies the UART Handle.
00192   * @param  __CLOCKSOURCE__ output variable.
00193   * @retval UART clocking source, written in __CLOCKSOURCE__.
00194   */
00195 #if defined(UART9) && defined(USART10)
00196 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00197   do {                                                        \
00198     if((__HANDLE__)->Instance == USART1)                      \
00199     {                                                         \
00200       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00201       {                                                       \
00202         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00203           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00204           break;                                              \
00205         case RCC_USART1CLKSOURCE_PLL2:                        \
00206           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00207           break;                                              \
00208         case RCC_USART1CLKSOURCE_PLL3:                        \
00209           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00210           break;                                              \
00211         case RCC_USART1CLKSOURCE_HSI:                         \
00212           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00213           break;                                              \
00214         case RCC_USART1CLKSOURCE_CSI:                         \
00215           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00216           break;                                              \
00217         case RCC_USART1CLKSOURCE_LSE:                         \
00218           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00219           break;                                              \
00220         default:                                              \
00221           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00222           break;                                              \
00223       }                                                       \
00224     }                                                         \
00225     else if((__HANDLE__)->Instance == USART2)                 \
00226     {                                                         \
00227       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00228       {                                                       \
00229         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00230           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00231           break;                                              \
00232         case RCC_USART2CLKSOURCE_PLL2:                        \
00233           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00234           break;                                              \
00235         case RCC_USART2CLKSOURCE_PLL3:                        \
00236           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00237           break;                                              \
00238         case RCC_USART2CLKSOURCE_HSI:                         \
00239           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00240           break;                                              \
00241         case RCC_USART2CLKSOURCE_CSI:                         \
00242           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00243           break;                                              \
00244         case RCC_USART2CLKSOURCE_LSE:                         \
00245           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00246           break;                                              \
00247         default:                                              \
00248           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00249           break;                                              \
00250       }                                                       \
00251     }                                                         \
00252     else if((__HANDLE__)->Instance == USART3)                 \
00253     {                                                         \
00254       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00255       {                                                       \
00256         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00257           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00258           break;                                              \
00259         case RCC_USART3CLKSOURCE_PLL2:                        \
00260           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00261           break;                                              \
00262         case RCC_USART3CLKSOURCE_PLL3:                        \
00263           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00264           break;                                              \
00265         case RCC_USART3CLKSOURCE_HSI:                         \
00266           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00267           break;                                              \
00268         case RCC_USART3CLKSOURCE_CSI:                         \
00269           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00270           break;                                              \
00271         case RCC_USART3CLKSOURCE_LSE:                         \
00272           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00273           break;                                              \
00274         default:                                              \
00275           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00276           break;                                              \
00277       }                                                       \
00278     }                                                         \
00279     else if((__HANDLE__)->Instance == UART4)                  \
00280     {                                                         \
00281       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00282       {                                                       \
00283         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00284           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00285           break;                                              \
00286         case RCC_UART4CLKSOURCE_PLL2:                         \
00287           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00288           break;                                              \
00289         case RCC_UART4CLKSOURCE_PLL3:                         \
00290           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00291           break;                                              \
00292         case RCC_UART4CLKSOURCE_HSI:                          \
00293           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00294           break;                                              \
00295         case RCC_UART4CLKSOURCE_CSI:                          \
00296           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00297           break;                                              \
00298         case RCC_UART4CLKSOURCE_LSE:                          \
00299           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00300           break;                                              \
00301         default:                                              \
00302           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00303           break;                                              \
00304       }                                                       \
00305     }                                                         \
00306     else if ((__HANDLE__)->Instance == UART5)                 \
00307     {                                                         \
00308       switch(__HAL_RCC_GET_UART5_SOURCE())                    \
00309       {                                                       \
00310         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00311           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00312           break;                                              \
00313         case RCC_UART5CLKSOURCE_PLL2:                         \
00314           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00315           break;                                              \
00316         case RCC_UART5CLKSOURCE_PLL3:                         \
00317           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00318           break;                                              \
00319         case RCC_UART5CLKSOURCE_HSI:                          \
00320           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00321           break;                                              \
00322         case RCC_UART5CLKSOURCE_CSI:                          \
00323           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00324           break;                                              \
00325         case RCC_UART5CLKSOURCE_LSE:                          \
00326           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00327           break;                                              \
00328         default:                                              \
00329           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00330           break;                                              \
00331       }                                                       \
00332     }                                                         \
00333     else if((__HANDLE__)->Instance == USART6)                 \
00334     {                                                         \
00335       switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00336       {                                                       \
00337         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00338           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00339           break;                                              \
00340         case RCC_USART6CLKSOURCE_PLL2:                        \
00341           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00342           break;                                              \
00343         case RCC_USART6CLKSOURCE_PLL3:                        \
00344           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00345           break;                                              \
00346         case RCC_USART6CLKSOURCE_HSI:                         \
00347           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00348           break;                                              \
00349         case RCC_USART6CLKSOURCE_CSI:                         \
00350           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00351           break;                                              \
00352         case RCC_USART6CLKSOURCE_LSE:                         \
00353           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00354           break;                                              \
00355         default:                                              \
00356           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00357           break;                                              \
00358       }                                                       \
00359     }                                                         \
00360     else if((__HANDLE__)->Instance == UART7)                  \
00361     {                                                         \
00362       switch(__HAL_RCC_GET_UART7_SOURCE())                    \
00363       {                                                       \
00364         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00365           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00366           break;                                              \
00367         case RCC_UART7CLKSOURCE_PLL2:                         \
00368           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00369           break;                                              \
00370         case RCC_UART7CLKSOURCE_PLL3:                         \
00371           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00372           break;                                              \
00373         case RCC_UART7CLKSOURCE_HSI:                          \
00374           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00375           break;                                              \
00376         case RCC_UART7CLKSOURCE_CSI:                          \
00377           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00378           break;                                              \
00379         case RCC_UART7CLKSOURCE_LSE:                          \
00380           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00381           break;                                              \
00382         default:                                              \
00383           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00384           break;                                              \
00385       }                                                       \
00386     }                                                         \
00387     else if((__HANDLE__)->Instance == UART8)                  \
00388     {                                                         \
00389       switch(__HAL_RCC_GET_UART8_SOURCE())                    \
00390       {                                                       \
00391         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00392           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00393           break;                                              \
00394         case RCC_UART8CLKSOURCE_PLL2:                         \
00395           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00396           break;                                              \
00397         case RCC_UART8CLKSOURCE_PLL3:                         \
00398           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00399           break;                                              \
00400         case RCC_UART8CLKSOURCE_HSI:                          \
00401           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00402           break;                                              \
00403         case RCC_UART8CLKSOURCE_CSI:                          \
00404           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00405           break;                                              \
00406         case RCC_UART8CLKSOURCE_LSE:                          \
00407           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00408           break;                                              \
00409         default:                                              \
00410           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00411           break;                                              \
00412       }                                                       \
00413     }                                                         \
00414     else if((__HANDLE__)->Instance == UART9)                  \
00415     {                                                         \
00416       switch(__HAL_RCC_GET_UART9_SOURCE())                    \
00417       {                                                       \
00418         case RCC_UART9CLKSOURCE_D2PCLK2:                      \
00419           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00420           break;                                              \
00421         case RCC_UART9CLKSOURCE_PLL2:                         \
00422           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00423           break;                                              \
00424         case RCC_UART9CLKSOURCE_PLL3:                         \
00425           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00426           break;                                              \
00427         case RCC_UART9CLKSOURCE_HSI:                          \
00428           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00429           break;                                              \
00430         case RCC_UART9CLKSOURCE_CSI:                          \
00431           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00432           break;                                              \
00433         case RCC_UART9CLKSOURCE_LSE:                          \
00434           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00435           break;                                              \
00436         default:                                              \
00437           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00438           break;                                              \
00439       }                                                       \
00440     }                                                         \
00441     else if((__HANDLE__)->Instance == USART10)                \
00442     {                                                         \
00443       switch(__HAL_RCC_GET_USART10_SOURCE())                  \
00444       {                                                       \
00445         case RCC_USART10CLKSOURCE_D2PCLK2:                    \
00446           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00447           break;                                              \
00448         case RCC_USART10CLKSOURCE_PLL2:                       \
00449           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00450           break;                                              \
00451         case RCC_USART10CLKSOURCE_PLL3:                       \
00452           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00453           break;                                              \
00454         case RCC_USART10CLKSOURCE_HSI:                        \
00455           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00456           break;                                              \
00457         case RCC_USART10CLKSOURCE_CSI:                        \
00458           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00459           break;                                              \
00460         case RCC_USART10CLKSOURCE_LSE:                        \
00461           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00462           break;                                              \
00463         default:                                              \
00464           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00465           break;                                              \
00466       }                                                       \
00467     }                                                         \
00468     else if((__HANDLE__)->Instance == LPUART1)                \
00469     {                                                         \
00470       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00471       {                                                       \
00472         case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
00473           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
00474           break;                                              \
00475         case RCC_LPUART1CLKSOURCE_PLL2:                       \
00476           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00477           break;                                              \
00478         case RCC_LPUART1CLKSOURCE_PLL3:                       \
00479           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00480           break;                                              \
00481         case RCC_LPUART1CLKSOURCE_HSI:                        \
00482           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00483           break;                                              \
00484         case RCC_LPUART1CLKSOURCE_CSI:                        \
00485           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00486           break;                                              \
00487         case RCC_LPUART1CLKSOURCE_LSE:                        \
00488           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00489           break;                                              \
00490         default:                                              \
00491           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00492           break;                                              \
00493       }                                                       \
00494     }                                                         \
00495     else                                                      \
00496     {                                                         \
00497       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00498     }                                                         \
00499   } while(0U)
00500 #else
00501 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00502   do {                                                        \
00503     if((__HANDLE__)->Instance == USART1)                      \
00504     {                                                         \
00505       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00506       {                                                       \
00507         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00508           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00509           break;                                              \
00510         case RCC_USART1CLKSOURCE_PLL2:                        \
00511           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00512           break;                                              \
00513         case RCC_USART1CLKSOURCE_PLL3:                        \
00514           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00515           break;                                              \
00516         case RCC_USART1CLKSOURCE_HSI:                         \
00517           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00518           break;                                              \
00519         case RCC_USART1CLKSOURCE_CSI:                         \
00520           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00521           break;                                              \
00522         case RCC_USART1CLKSOURCE_LSE:                         \
00523           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00524           break;                                              \
00525         default:                                              \
00526           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00527           break;                                              \
00528       }                                                       \
00529     }                                                         \
00530     else if((__HANDLE__)->Instance == USART2)                 \
00531     {                                                         \
00532       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00533       {                                                       \
00534         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00535           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00536           break;                                              \
00537         case RCC_USART2CLKSOURCE_PLL2:                        \
00538           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00539           break;                                              \
00540         case RCC_USART2CLKSOURCE_PLL3:                        \
00541           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00542           break;                                              \
00543         case RCC_USART2CLKSOURCE_HSI:                         \
00544           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00545           break;                                              \
00546         case RCC_USART2CLKSOURCE_CSI:                         \
00547           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00548           break;                                              \
00549         case RCC_USART2CLKSOURCE_LSE:                         \
00550           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00551           break;                                              \
00552         default:                                              \
00553           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00554           break;                                              \
00555       }                                                       \
00556     }                                                         \
00557     else if((__HANDLE__)->Instance == USART3)                 \
00558     {                                                         \
00559       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00560       {                                                       \
00561         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00562           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00563           break;                                              \
00564         case RCC_USART3CLKSOURCE_PLL2:                        \
00565           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00566           break;                                              \
00567         case RCC_USART3CLKSOURCE_PLL3:                        \
00568           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00569           break;                                              \
00570         case RCC_USART3CLKSOURCE_HSI:                         \
00571           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00572           break;                                              \
00573         case RCC_USART3CLKSOURCE_CSI:                         \
00574           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00575           break;                                              \
00576         case RCC_USART3CLKSOURCE_LSE:                         \
00577           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00578           break;                                              \
00579         default:                                              \
00580           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00581           break;                                              \
00582       }                                                       \
00583     }                                                         \
00584     else if((__HANDLE__)->Instance == UART4)                  \
00585     {                                                         \
00586       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00587       {                                                       \
00588         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00589           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00590           break;                                              \
00591         case RCC_UART4CLKSOURCE_PLL2:                         \
00592           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00593           break;                                              \
00594         case RCC_UART4CLKSOURCE_PLL3:                         \
00595           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00596           break;                                              \
00597         case RCC_UART4CLKSOURCE_HSI:                          \
00598           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00599           break;                                              \
00600         case RCC_UART4CLKSOURCE_CSI:                          \
00601           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00602           break;                                              \
00603         case RCC_UART4CLKSOURCE_LSE:                          \
00604           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00605           break;                                              \
00606         default:                                              \
00607           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00608           break;                                              \
00609       }                                                       \
00610     }                                                         \
00611     else if ((__HANDLE__)->Instance == UART5)                 \
00612     {                                                         \
00613       switch(__HAL_RCC_GET_UART5_SOURCE())                    \
00614       {                                                       \
00615         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00616           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00617           break;                                              \
00618         case RCC_UART5CLKSOURCE_PLL2:                         \
00619           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00620           break;                                              \
00621         case RCC_UART5CLKSOURCE_PLL3:                         \
00622           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00623           break;                                              \
00624         case RCC_UART5CLKSOURCE_HSI:                          \
00625           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00626           break;                                              \
00627         case RCC_UART5CLKSOURCE_CSI:                          \
00628           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00629           break;                                              \
00630         case RCC_UART5CLKSOURCE_LSE:                          \
00631           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00632           break;                                              \
00633         default:                                              \
00634           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00635           break;                                              \
00636       }                                                       \
00637     }                                                         \
00638     else if((__HANDLE__)->Instance == USART6)                 \
00639     {                                                         \
00640       switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00641       {                                                       \
00642         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00643           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00644           break;                                              \
00645         case RCC_USART6CLKSOURCE_PLL2:                        \
00646           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00647           break;                                              \
00648         case RCC_USART6CLKSOURCE_PLL3:                        \
00649           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00650           break;                                              \
00651         case RCC_USART6CLKSOURCE_HSI:                         \
00652           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00653           break;                                              \
00654         case RCC_USART6CLKSOURCE_CSI:                         \
00655           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00656           break;                                              \
00657         case RCC_USART6CLKSOURCE_LSE:                         \
00658           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00659           break;                                              \
00660         default:                                              \
00661           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00662           break;                                              \
00663       }                                                       \
00664     }                                                         \
00665     else if((__HANDLE__)->Instance == UART7)                  \
00666     {                                                         \
00667       switch(__HAL_RCC_GET_UART7_SOURCE())                    \
00668       {                                                       \
00669         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00670           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00671           break;                                              \
00672         case RCC_UART7CLKSOURCE_PLL2:                         \
00673           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00674           break;                                              \
00675         case RCC_UART7CLKSOURCE_PLL3:                         \
00676           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00677           break;                                              \
00678         case RCC_UART7CLKSOURCE_HSI:                          \
00679           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00680           break;                                              \
00681         case RCC_UART7CLKSOURCE_CSI:                          \
00682           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00683           break;                                              \
00684         case RCC_UART7CLKSOURCE_LSE:                          \
00685           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00686           break;                                              \
00687         default:                                              \
00688           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00689           break;                                              \
00690       }                                                       \
00691     }                                                         \
00692     else if((__HANDLE__)->Instance == UART8)                  \
00693     {                                                         \
00694       switch(__HAL_RCC_GET_UART8_SOURCE())                    \
00695       {                                                       \
00696         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00697           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00698           break;                                              \
00699         case RCC_UART8CLKSOURCE_PLL2:                         \
00700           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00701           break;                                              \
00702         case RCC_UART8CLKSOURCE_PLL3:                         \
00703           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00704           break;                                              \
00705         case RCC_UART8CLKSOURCE_HSI:                          \
00706           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00707           break;                                              \
00708         case RCC_UART8CLKSOURCE_CSI:                          \
00709           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00710           break;                                              \
00711         case RCC_UART8CLKSOURCE_LSE:                          \
00712           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00713           break;                                              \
00714         default:                                              \
00715           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00716           break;                                              \
00717       }                                                       \
00718     }                                                         \
00719     else if((__HANDLE__)->Instance == LPUART1)                \
00720     {                                                         \
00721       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00722       {                                                       \
00723         case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
00724           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
00725           break;                                              \
00726         case RCC_LPUART1CLKSOURCE_PLL2:                       \
00727           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00728           break;                                              \
00729         case RCC_LPUART1CLKSOURCE_PLL3:                       \
00730           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00731           break;                                              \
00732         case RCC_LPUART1CLKSOURCE_HSI:                        \
00733           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00734           break;                                              \
00735         case RCC_LPUART1CLKSOURCE_CSI:                        \
00736           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00737           break;                                              \
00738         case RCC_LPUART1CLKSOURCE_LSE:                        \
00739           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00740           break;                                              \
00741         default:                                              \
00742           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00743           break;                                              \
00744       }                                                       \
00745     }                                                         \
00746     else                                                      \
00747     {                                                         \
00748       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00749     }                                                         \
00750   } while(0U)
00751 #endif  /* UART9 && USART10 */
00752
00753 /** @brief  Report the UART mask to apply to retrieve the received data
00754   *         according to the word length and to the parity bits activation.
00755   * @note   If PCE = 1, the parity bit is not included in the data extracted
00756   *         by the reception API().
00757   *         This masking operation is not carried out in the case of
00758   *         DMA transfers.
00759   * @param  __HANDLE__ specifies the UART Handle.
00760   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00761   */
00762 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00763   do {                                                                \
00764     if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
00765     {                                                                 \
00766       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00767       {                                                               \
00768         (__HANDLE__)->Mask = 0x01FFU ;                                \
00769       }                                                               \
00770       else                                                            \
00771       {                                                               \
00772         (__HANDLE__)->Mask = 0x00FFU ;                                \
00773       }                                                               \
00774     }                                                                 \
00775     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
00776     {                                                                 \
00777       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00778       {                                                               \
00779         (__HANDLE__)->Mask = 0x00FFU ;                                \
00780       }                                                               \
00781       else                                                            \
00782       {                                                               \
00783         (__HANDLE__)->Mask = 0x007FU ;                                \
00784       }                                                               \
00785     }                                                                 \
00786     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
00787     {                                                                 \
00788       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00789       {                                                               \
00790         (__HANDLE__)->Mask = 0x007FU ;                                \
00791       }                                                               \
00792       else                                                            \
00793       {                                                               \
00794         (__HANDLE__)->Mask = 0x003FU ;                                \
00795       }                                                               \
00796     }                                                                 \
00797     else                                                              \
00798     {                                                                 \
00799       (__HANDLE__)->Mask = 0x0000U;                                   \
00800     }                                                                 \
00801   } while(0U)
00802
00803 /**
00804   * @brief Ensure that UART frame length is valid.
00805   * @param __LENGTH__ UART frame length.
00806   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00807   */
00808 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00809                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00810                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00811
00812 /**
00813   * @brief Ensure that UART wake-up address length is valid.
00814   * @param __ADDRESS__ UART wake-up address length.
00815   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00816   */
00817 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00818                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00819
00820 /**
00821   * @brief Ensure that UART TXFIFO threshold level is valid.
00822   * @param __THRESHOLD__ UART TXFIFO threshold level.
00823   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00824   */
00825 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
00826                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
00827                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
00828                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
00829                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
00830                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
00831
00832 /**
00833   * @brief Ensure that UART RXFIFO threshold level is valid.
00834   * @param __THRESHOLD__ UART RXFIFO threshold level.
00835   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00836   */
00837 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
00838                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
00839                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
00840                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
00841                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
00842                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
00843
00844 /**
00845   * @}
00846   */
00847
00848 /* Private functions ---------------------------------------------------------*/
00849
00850 /**
00851   * @}
00852   */
00853
00854 /**
00855   * @}
00856   */
00857
00858 #ifdef __cplusplus
00859 }
00860 #endif
00861
00862 #endif /* STM32H7xx_HAL_UART_EX_H */
00863
00864 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart.c Source File

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stm32h7xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00008   *          Peripheral (USART).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019       The USART HAL driver can be used as follows:
00020
00021       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00022       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00023           (++) Enable the USARTx interface clock.
00024           (++) USART pins configuration:
00025             (+++) Enable the clock for the USART GPIOs.
00026             (+++) Configure these USART pins as alternate function pull-up.
00027           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00028                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031             (++) USART interrupts handling:
00032               -@@-   The specific USART interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00035           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00036                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx channel.
00041             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00043
00044       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
00045           (Receiver/Transmitter) in the husart handle Init structure.
00046
00047       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00048           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049                by calling the customized HAL_USART_MspInit(&husart) API.
00050
00051     [..]
00052      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00053         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00054         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00055
00056     ##### Callback registration #####
00057     ==================================
00058
00059     [..]
00060     The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
00061     allows the user to configure dynamically the driver callbacks.
00062
00063     [..]
00064     Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
00065     Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
00066     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00067     (+) TxCpltCallback            : Tx Complete Callback.
00068     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00069     (+) RxCpltCallback            : Rx Complete Callback.
00070     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00071     (+) ErrorCallback             : Error Callback.
00072     (+) AbortCpltCallback         : Abort Complete Callback.
00073     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00074     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00075     (+) MspInitCallback           : USART MspInit.
00076     (+) MspDeInitCallback         : USART MspDeInit.
00077     This function takes as parameters the HAL peripheral handle, the Callback ID
00078     and a pointer to the user callback function.
00079
00080     [..]
00081     Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
00082     weak (surcharged) function.
00083     @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00084     and the Callback ID.
00085     This function allows to reset following callbacks:
00086     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00087     (+) TxCpltCallback            : Tx Complete Callback.
00088     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00089     (+) RxCpltCallback            : Rx Complete Callback.
00090     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00091     (+) ErrorCallback             : Error Callback.
00092     (+) AbortCpltCallback         : Abort Complete Callback.
00093     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00094     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00095     (+) MspInitCallback           : USART MspInit.
00096     (+) MspDeInitCallback         : USART MspDeInit.
00097
00098     [..]
00099     By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
00100     all callbacks are set to the corresponding weak (surcharged) functions:
00101     examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
00102     Exception done for MspInit and MspDeInit functions that are respectively
00103     reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
00104     and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
00105     If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
00106     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00107
00108     [..]
00109     Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
00110     Exception done MspInit/MspDeInit that can be registered/unregistered
00111     in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
00112     MspInit/DeInit callbacks can be used during the Init/DeInit.
00113     In that case first register the MspInit/MspDeInit user callbacks
00114     using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
00115     or @ref HAL_USART_Init() function.
00116
00117     [..]
00118     When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
00119     not defined, the callback registration feature is not available
00120     and weak (surcharged) callbacks are used.
00121
00122
00123   @endverbatim
00124   ******************************************************************************
00125   * @attention
00126   *
00127   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00128   * All rights reserved.</center></h2>
00129   *
00130   * This software component is licensed by ST under BSD 3-Clause license,
00131   * the "License"; You may not use this file except in compliance with the
00132   * License. You may obtain a copy of the License at:
00133   *                        opensource.org/licenses/BSD-3-Clause
00134   *
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32h7xx_hal.h"
00140
00141 /** @addtogroup STM32H7xx_HAL_Driver
00142   * @{
00143   */
00144
00145 /** @defgroup USART USART
00146   * @brief HAL USART Synchronous module driver
00147   * @{
00148   */
00149
00150 #ifdef HAL_USART_MODULE_ENABLED
00151
00152 /* Private typedef -----------------------------------------------------------*/
00153 /* Private define ------------------------------------------------------------*/
00154 /** @defgroup USART_Private_Constants USART Private Constants
00155   * @{
00156   */
00157 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00158 #define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
00159 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
00160                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
00161                                               USART_CR1_FIFOEN ))                                  /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00162
00163 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
00164                                               USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
00165                                               USART_CR2_DIS_NSS))                                  /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00166
00167 #define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))             /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
00168
00169 #define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
00170 #define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
00171 /**
00172   * @}
00173   */
00174
00175 /* Private macros ------------------------------------------------------------*/
00176 /* Private variables ---------------------------------------------------------*/
00177 /* Private function prototypes -----------------------------------------------*/
00178 /** @addtogroup USART_Private_Functions
00179   * @{
00180   */
00181 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00182 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
00183 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00184 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00185 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00186 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00187 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00188 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00190 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00191 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00192 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
00194                                                       uint32_t Tickstart, uint32_t Timeout);
00195 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00196 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00197 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
00198 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
00199 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00200 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00201 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00202 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
00203 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
00204 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00205 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00206
00207
00208 /**
00209   * @}
00210   */
00211
00212 /* Exported functions --------------------------------------------------------*/
00213
00214 /** @defgroup USART_Exported_Functions USART Exported Functions
00215   * @{
00216   */
00217
00218 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00219   * @brief    Initialization and Configuration functions
00220   *
00221 @verbatim
00222  ===============================================================================
00223             ##### Initialization and Configuration functions #####
00224  ===============================================================================
00225     [..]
00226     This subsection provides a set of functions allowing to initialize the USART
00227     in asynchronous and in synchronous modes.
00228       (+) For the asynchronous mode only these parameters can be configured:
00229         (++) Baud Rate
00230         (++) Word Length
00231         (++) Stop Bit
00232         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00233              in the data register is transmitted but is changed by the parity bit.
00234         (++) USART polarity
00235         (++) USART phase
00236         (++) USART LastBit
00237         (++) Receiver/transmitter modes
00238
00239     [..]
00240     The HAL_USART_Init() function follows the USART  synchronous configuration
00241     procedure (details for the procedure are available in reference manual).
00242
00243 @endverbatim
00244
00245   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00246   8-bit or 9-bit), the possible USART formats are listed in the
00247   following table.
00248
00249     Table 1. USART frame format.
00250     +-----------------------------------------------------------------------+
00251     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00252     |---------|---------|-----------|---------------------------------------|
00253     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00254     |---------|---------|-----------|---------------------------------------|
00255     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00256     |---------|---------|-----------|---------------------------------------|
00257     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00258     |---------|---------|-----------|---------------------------------------|
00259     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00260     |---------|---------|-----------|---------------------------------------|
00261     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00262     |---------|---------|-----------|---------------------------------------|
00263     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00264     +-----------------------------------------------------------------------+
00265
00266   * @{
00267   */
00268
00269 /**
00270   * @brief  Initialize the USART mode according to the specified
00271   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00272   * @param  husart USART handle.
00273   * @retval HAL status
00274   */
00275 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00276 {
00277   /* Check the USART handle allocation */
00278   if (husart == NULL)
00279   {
00280     return HAL_ERROR;
00281   }
00282
00283   /* Check the parameters */
00284   assert_param(IS_USART_INSTANCE(husart->Instance));
00285
00286   if (husart->State == HAL_USART_STATE_RESET)
00287   {
00288     /* Allocate lock resource and initialize it */
00289     husart->Lock = HAL_UNLOCKED;
00290
00291 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00292     USART_InitCallbacksToDefault(husart);
00293
00294     if (husart->MspInitCallback == NULL)
00295     {
00296       husart->MspInitCallback = HAL_USART_MspInit;
00297     }
00298
00299     /* Init the low level hardware */
00300     husart->MspInitCallback(husart);
00301 #else
00302     /* Init the low level hardware : GPIO, CLOCK */
00303     HAL_USART_MspInit(husart);
00304 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00305   }
00306
00307   husart->State = HAL_USART_STATE_BUSY;
00308
00309   /* Disable the Peripheral */
00310   __HAL_USART_DISABLE(husart);
00311
00312   /* Set the Usart Communication parameters */
00313   if (USART_SetConfig(husart) == HAL_ERROR)
00314   {
00315     return HAL_ERROR;
00316   }
00317
00318   /* In Synchronous mode, the following bits must be kept cleared:
00319   - LINEN bit in the USART_CR2 register
00320   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00321   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00322   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00323
00324   /* Enable the Peripheral */
00325   __HAL_USART_ENABLE(husart);
00326
00327   /* TEACK and/or REACK to check before moving husart->State to Ready */
00328   return (USART_CheckIdleState(husart));
00329 }
00330
00331 /**
00332   * @brief DeInitialize the USART peripheral.
00333   * @param  husart USART handle.
00334   * @retval HAL status
00335   */
00336 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00337 {
00338   /* Check the USART handle allocation */
00339   if (husart == NULL)
00340   {
00341     return HAL_ERROR;
00342   }
00343
00344   /* Check the parameters */
00345   assert_param(IS_USART_INSTANCE(husart->Instance));
00346
00347   husart->State = HAL_USART_STATE_BUSY;
00348
00349   husart->Instance->CR1 = 0x0U;
00350   husart->Instance->CR2 = 0x0U;
00351   husart->Instance->CR3 = 0x0U;
00352
00353 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00354   if (husart->MspDeInitCallback == NULL)
00355   {
00356     husart->MspDeInitCallback = HAL_USART_MspDeInit;
00357   }
00358   /* DeInit the low level hardware */
00359   husart->MspDeInitCallback(husart);
00360 #else
00361   /* DeInit the low level hardware */
00362   HAL_USART_MspDeInit(husart);
00363 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00364
00365   husart->ErrorCode = HAL_USART_ERROR_NONE;
00366   husart->State = HAL_USART_STATE_RESET;
00367
00368   /* Process Unlock */
00369   __HAL_UNLOCK(husart);
00370
00371   return HAL_OK;
00372 }
00373
00374 /**
00375   * @brief Initialize the USART MSP.
00376   * @param husart USART handle.
00377   * @retval None
00378   */
00379 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00380 {
00381   /* Prevent unused argument(s) compilation warning */
00382   UNUSED(husart);
00383
00384   /* NOTE : This function should not be modified, when the callback is needed,
00385             the HAL_USART_MspInit can be implemented in the user file
00386    */
00387 }
00388
00389 /**
00390   * @brief DeInitialize the USART MSP.
00391   * @param husart USART handle.
00392   * @retval None
00393   */
00394 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00395 {
00396   /* Prevent unused argument(s) compilation warning */
00397   UNUSED(husart);
00398
00399   /* NOTE : This function should not be modified, when the callback is needed,
00400             the HAL_USART_MspDeInit can be implemented in the user file
00401    */
00402 }
00403
00404 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00405 /**
00406   * @brief  Register a User USART Callback
00407   *         To be used instead of the weak predefined callback
00408   * @param  husart usart handle
00409   * @param  CallbackID ID of the callback to be registered
00410   *         This parameter can be one of the following values:
00411   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00412   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00413   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00414   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00415   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00416   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00417   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00418   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00419   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00420   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00421   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00422   * @param  pCallback pointer to the Callback function
00423   * @retval HAL status
00424 +  */
00425 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
00426                                              pUSART_CallbackTypeDef pCallback)
00427 {
00428   HAL_StatusTypeDef status = HAL_OK;
00429
00430   if (pCallback == NULL)
00431   {
00432     /* Update the error code */
00433     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00434
00435     return HAL_ERROR;
00436   }
00437   /* Process locked */
00438   __HAL_LOCK(husart);
00439
00440   if (husart->State == HAL_USART_STATE_READY)
00441   {
00442     switch (CallbackID)
00443     {
00444       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00445         husart->TxHalfCpltCallback = pCallback;
00446         break;
00447
00448       case HAL_USART_TX_COMPLETE_CB_ID :
00449         husart->TxCpltCallback = pCallback;
00450         break;
00451
00452       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00453         husart->RxHalfCpltCallback = pCallback;
00454         break;
00455
00456       case HAL_USART_RX_COMPLETE_CB_ID :
00457         husart->RxCpltCallback = pCallback;
00458         break;
00459
00460       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00461         husart->TxRxCpltCallback = pCallback;
00462         break;
00463
00464       case HAL_USART_ERROR_CB_ID :
00465         husart->ErrorCallback = pCallback;
00466         break;
00467
00468       case HAL_USART_ABORT_COMPLETE_CB_ID :
00469         husart->AbortCpltCallback = pCallback;
00470         break;
00471
00472       case HAL_USART_RX_FIFO_FULL_CB_ID :
00473         husart->RxFifoFullCallback = pCallback;
00474         break;
00475
00476       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00477         husart->TxFifoEmptyCallback = pCallback;
00478         break;
00479
00480       case HAL_USART_MSPINIT_CB_ID :
00481         husart->MspInitCallback = pCallback;
00482         break;
00483
00484       case HAL_USART_MSPDEINIT_CB_ID :
00485         husart->MspDeInitCallback = pCallback;
00486         break;
00487
00488       default :
00489         /* Update the error code */
00490         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00491
00492         /* Return error status */
00493         status =  HAL_ERROR;
00494         break;
00495     }
00496   }
00497   else if (husart->State == HAL_USART_STATE_RESET)
00498   {
00499     switch (CallbackID)
00500     {
00501       case HAL_USART_MSPINIT_CB_ID :
00502         husart->MspInitCallback = pCallback;
00503         break;
00504
00505       case HAL_USART_MSPDEINIT_CB_ID :
00506         husart->MspDeInitCallback = pCallback;
00507         break;
00508
00509       default :
00510         /* Update the error code */
00511         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00512
00513         /* Return error status */
00514         status =  HAL_ERROR;
00515         break;
00516     }
00517   }
00518   else
00519   {
00520     /* Update the error code */
00521     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00522
00523     /* Return error status */
00524     status =  HAL_ERROR;
00525   }
00526
00527   /* Release Lock */
00528   __HAL_UNLOCK(husart);
00529
00530   return status;
00531 }
00532
00533 /**
00534   * @brief  Unregister an UART Callback
00535   *         UART callaback is redirected to the weak predefined callback
00536   * @param  husart uart handle
00537   * @param  CallbackID ID of the callback to be unregistered
00538   *         This parameter can be one of the following values:
00539   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00540   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00541   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00542   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00543   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00544   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00545   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00546   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00547   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00548   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00549   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00550   * @retval HAL status
00551   */
00552 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
00553 {
00554   HAL_StatusTypeDef status = HAL_OK;
00555
00556   /* Process locked */
00557   __HAL_LOCK(husart);
00558
00559   if (HAL_USART_STATE_READY == husart->State)
00560   {
00561     switch (CallbackID)
00562     {
00563       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00564         husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00565         break;
00566
00567       case HAL_USART_TX_COMPLETE_CB_ID :
00568         husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00569         break;
00570
00571       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00572         husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00573         break;
00574
00575       case HAL_USART_RX_COMPLETE_CB_ID :
00576         husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00577         break;
00578
00579       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00580         husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback            */
00581         break;
00582
00583       case HAL_USART_ERROR_CB_ID :
00584         husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00585         break;
00586
00587       case HAL_USART_ABORT_COMPLETE_CB_ID :
00588         husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00589         break;
00590
00591       case HAL_USART_RX_FIFO_FULL_CB_ID :
00592         husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00593         break;
00594
00595       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00596         husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00597         break;
00598
00599       case HAL_USART_MSPINIT_CB_ID :
00600         husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback           */
00601         break;
00602
00603       case HAL_USART_MSPDEINIT_CB_ID :
00604         husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00605         break;
00606
00607       default :
00608         /* Update the error code */
00609         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00610
00611         /* Return error status */
00612         status =  HAL_ERROR;
00613         break;
00614     }
00615   }
00616   else if (HAL_USART_STATE_RESET == husart->State)
00617   {
00618     switch (CallbackID)
00619     {
00620       case HAL_USART_MSPINIT_CB_ID :
00621         husart->MspInitCallback = HAL_USART_MspInit;
00622         break;
00623
00624       case HAL_USART_MSPDEINIT_CB_ID :
00625         husart->MspDeInitCallback = HAL_USART_MspDeInit;
00626         break;
00627
00628       default :
00629         /* Update the error code */
00630         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00631
00632         /* Return error status */
00633         status =  HAL_ERROR;
00634         break;
00635     }
00636   }
00637   else
00638   {
00639     /* Update the error code */
00640     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00641
00642     /* Return error status */
00643     status =  HAL_ERROR;
00644   }
00645
00646   /* Release Lock */
00647   __HAL_UNLOCK(husart);
00648
00649   return status;
00650 }
00651 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00652
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00659   * @brief   USART Transmit and Receive functions
00660   *
00661 @verbatim
00662  ===============================================================================
00663                       ##### IO operation functions #####
00664  ===============================================================================
00665     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00666     data transfers.
00667
00668     [..] The USART supports master mode only: it cannot receive or send data related to an input
00669          clock (SCLK is always an output).
00670
00671     [..]
00672
00673     (#) There are two modes of transfer:
00674         (++) Blocking mode: The communication is performed in polling mode.
00675              The HAL status of all data processing is returned by the same function
00676              after finishing transfer.
00677         (++) No-Blocking mode: The communication is performed using Interrupts
00678              or DMA, These API's return the HAL status.
00679              The end of the data processing will be indicated through the
00680              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00681              using DMA mode.
00682              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00683              will be executed respectively at the end of the transmit or Receive process
00684              The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00685
00686     (#) Blocking mode API's are :
00687         (++) HAL_USART_Transmit() in simplex mode
00688         (++) HAL_USART_Receive() in full duplex receive only
00689         (++) HAL_USART_TransmitReceive() in full duplex mode
00690
00691     (#) Non-Blocking mode API's with Interrupt are :
00692         (++) HAL_USART_Transmit_IT() in simplex mode
00693         (++) HAL_USART_Receive_IT() in full duplex receive only
00694         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00695         (++) HAL_USART_IRQHandler()
00696
00697     (#) No-Blocking mode API's  with DMA are :
00698         (++) HAL_USART_Transmit_DMA() in simplex mode
00699         (++) HAL_USART_Receive_DMA() in full duplex receive only
00700         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00701         (++) HAL_USART_DMAPause()
00702         (++) HAL_USART_DMAResume()
00703         (++) HAL_USART_DMAStop()
00704
00705     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00706         (++) HAL_USART_TxCpltCallback()
00707         (++) HAL_USART_RxCpltCallback()
00708         (++) HAL_USART_TxHalfCpltCallback()
00709         (++) HAL_USART_RxHalfCpltCallback()
00710         (++) HAL_USART_ErrorCallback()
00711         (++) HAL_USART_TxRxCpltCallback()
00712
00713     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00714         (++) HAL_USART_Abort()
00715         (++) HAL_USART_Abort_IT()
00716
00717     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00718         (++) HAL_USART_AbortCpltCallback()
00719
00720     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00721         Errors are handled as follows :
00722         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00723              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00724              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00725              and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
00726              If user wants to abort it, Abort services should be called by user.
00727         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00728              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00729              Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
00730
00731 @endverbatim
00732   * @{
00733   */
00734
00735 /**
00736   * @brief  Simplex send an amount of data in blocking mode.
00737   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00738   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
00739   *         of u16 provided through pTxData.
00740   * @param  husart USART handle.
00741   * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
00742   * @param  Size Amount of data elements (u8 or u16) to be sent.
00743   * @param  Timeout Timeout duration.
00744   * @retval HAL status
00745   */
00746 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00747 {
00748   uint8_t  *ptxdata8bits;
00749   uint16_t *ptxdata16bits;
00750   uint32_t tickstart;
00751
00752   if (husart->State == HAL_USART_STATE_READY)
00753   {
00754     if ((pTxData == NULL) || (Size == 0U))
00755     {
00756       return  HAL_ERROR;
00757     }
00758
00759     /* Process Locked */
00760     __HAL_LOCK(husart);
00761
00762     husart->ErrorCode = HAL_USART_ERROR_NONE;
00763     husart->State = HAL_USART_STATE_BUSY_TX;
00764
00765     /* Init tickstart for timeout managment*/
00766     tickstart = HAL_GetTick();
00767
00768     husart->TxXferSize = Size;
00769     husart->TxXferCount = Size;
00770
00771     /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
00772     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00773     {
00774       ptxdata8bits  = NULL;
00775       ptxdata16bits = (uint16_t *) pTxData;
00776     }
00777     else
00778     {
00779       ptxdata8bits  = pTxData;
00780       ptxdata16bits = NULL;
00781     }
00782
00783     /* Check the remaining data to be sent */
00784     while (husart->TxXferCount > 0U)
00785     {
00786       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00787       {
00788         return HAL_TIMEOUT;
00789       }
00790       if (ptxdata8bits == NULL)
00791       {
00792         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
00793         ptxdata16bits++;
00794       }
00795       else
00796       {
00797         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
00798         ptxdata8bits++;
00799       }
00800
00801       husart->TxXferCount--;
00802     }
00803
00804     if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00805     {
00806       return HAL_TIMEOUT;
00807     }
00808
00809     /* Clear Transmission Complete Flag */
00810     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00811
00812     /* Clear overrun flag and discard the received data */
00813     __HAL_USART_CLEAR_OREFLAG(husart);
00814     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
00815     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00816
00817     /* At end of Tx process, restore husart->State to Ready */
00818     husart->State = HAL_USART_STATE_READY;
00819
00820     /* Process Unlocked */
00821     __HAL_UNLOCK(husart);
00822
00823     return HAL_OK;
00824   }
00825   else
00826   {
00827     return HAL_BUSY;
00828   }
00829 }
00830
00831 /**
00832   * @brief Receive an amount of data in blocking mode.
00833   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00834   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00835   *         the received data is handled as a set of u16. In this case, Size must indicate the number
00836   *         of u16 available through pRxData.
00837   * @param husart USART handle.
00838   * @param pRxData Pointer to data buffer (u8 or u16 data elements).
00839   * @param Size Amount of data elements (u8 or u16) to be received.
00840   * @param Timeout Timeout duration.
00841   * @retval HAL status
00842   */
00843 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00844 {
00845   uint8_t  *prxdata8bits;
00846   uint16_t *prxdata16bits;
00847   uint16_t uhMask;
00848   uint32_t tickstart;
00849
00850   if (husart->State == HAL_USART_STATE_READY)
00851   {
00852     if ((pRxData == NULL) || (Size == 0U))
00853     {
00854       return  HAL_ERROR;
00855     }
00856
00857     /* Process Locked */
00858     __HAL_LOCK(husart);
00859
00860     husart->ErrorCode = HAL_USART_ERROR_NONE;
00861     husart->State = HAL_USART_STATE_BUSY_RX;
00862
00863     /* Init tickstart for timeout managment*/
00864     tickstart = HAL_GetTick();
00865
00866     husart->RxXferSize = Size;
00867     husart->RxXferCount = Size;
00868
00869     /* Computation of USART mask to apply to RDR register */
00870     USART_MASK_COMPUTATION(husart);
00871     uhMask = husart->Mask;
00872
00873     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00874     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00875     {
00876       prxdata8bits  = NULL;
00877       prxdata16bits = (uint16_t *) pRxData;
00878     }
00879     else
00880     {
00881       prxdata8bits  = pRxData;
00882       prxdata16bits = NULL;
00883     }
00884
00885     /* as long as data have to be received */
00886     while (husart->RxXferCount > 0U)
00887     {
00888       if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
00889       {
00890         /* Wait until TXE flag is set to send dummy byte in order to generate the
00891         * clock for the slave to send data.
00892         * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00893         * can be written for all the cases. */
00894         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00895         {
00896           return HAL_TIMEOUT;
00897         }
00898         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
00899       }
00900
00901       /* Wait for RXNE Flag */
00902       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00903       {
00904         return HAL_TIMEOUT;
00905       }
00906
00907       if (prxdata8bits == NULL)
00908       {
00909         *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
00910         prxdata16bits++;
00911       }
00912       else
00913       {
00914         *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
00915         prxdata8bits++;
00916       }
00917
00918       husart->RxXferCount--;
00919
00920     }
00921
00922     /* Clear SPI slave underrun flag and discard transmit data */
00923     if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
00924     {
00925       __HAL_USART_CLEAR_UDRFLAG(husart);
00926       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00927     }
00928
00929     /* At end of Rx process, restore husart->State to Ready */
00930     husart->State = HAL_USART_STATE_READY;
00931
00932     /* Process Unlocked */
00933     __HAL_UNLOCK(husart);
00934
00935     return HAL_OK;
00936   }
00937   else
00938   {
00939     return HAL_BUSY;
00940   }
00941 }
00942
00943 /**
00944   * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
00945   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00946   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
00947   *         of u16 available through pTxData and through pRxData.
00948   * @param  husart USART handle.
00949   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
00950   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
00951   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
00952   * @param  Timeout Timeout duration.
00953   * @retval HAL status
00954   */
00955 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
00956                                             uint16_t Size, uint32_t Timeout)
00957 {
00958   uint8_t  *prxdata8bits;
00959   uint16_t *prxdata16bits;
00960   uint8_t  *ptxdata8bits;
00961   uint16_t *ptxdata16bits;
00962   uint16_t uhMask;
00963   uint16_t rxdatacount;
00964   uint32_t tickstart;
00965
00966   if (husart->State == HAL_USART_STATE_READY)
00967   {
00968     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00969     {
00970       return  HAL_ERROR;
00971     }
00972
00973     /* Process Locked */
00974     __HAL_LOCK(husart);
00975
00976     husart->ErrorCode = HAL_USART_ERROR_NONE;
00977     husart->State = HAL_USART_STATE_BUSY_RX;
00978
00979     /* Init tickstart for timeout managment*/
00980     tickstart = HAL_GetTick();
00981
00982     husart->RxXferSize = Size;
00983     husart->TxXferSize = Size;
00984     husart->TxXferCount = Size;
00985     husart->RxXferCount = Size;
00986
00987     /* Computation of USART mask to apply to RDR register */
00988     USART_MASK_COMPUTATION(husart);
00989     uhMask = husart->Mask;
00990
00991     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00992     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00993     {
00994       prxdata8bits  = NULL;
00995       ptxdata8bits  = NULL;
00996       ptxdata16bits = (uint16_t *) pTxData;
00997       prxdata16bits = (uint16_t *) pRxData;
00998     }
00999     else
01000     {
01001       prxdata8bits  = pRxData;
01002       ptxdata8bits  = pTxData;
01003       ptxdata16bits = NULL;
01004       prxdata16bits = NULL;
01005     }
01006
01007     if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
01008     {
01009       /* Wait until TXE flag is set to send data */
01010       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01011       {
01012         return HAL_TIMEOUT;
01013       }
01014       if (ptxdata8bits == NULL)
01015       {
01016         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01017         ptxdata16bits++;
01018       }
01019       else
01020       {
01021         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01022         ptxdata8bits++;
01023       }
01024
01025       husart->TxXferCount--;
01026     }
01027
01028     /* Check the remain data to be sent */
01029     /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
01030     rxdatacount = husart->RxXferCount;
01031     while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
01032     {
01033       if (husart->TxXferCount > 0U)
01034       {
01035         /* Wait until TXE flag is set to send data */
01036         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01037         {
01038           return HAL_TIMEOUT;
01039         }
01040         if (ptxdata8bits == NULL)
01041         {
01042           husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01043           ptxdata16bits++;
01044         }
01045         else
01046         {
01047           husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01048           ptxdata8bits++;
01049         }
01050
01051         husart->TxXferCount--;
01052       }
01053
01054       if (husart->RxXferCount > 0U)
01055       {
01056         /* Wait for RXNE Flag */
01057         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01058         {
01059           return HAL_TIMEOUT;
01060         }
01061
01062         if (prxdata8bits == NULL)
01063         {
01064           *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
01065           prxdata16bits++;
01066         }
01067         else
01068         {
01069           *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
01070           prxdata8bits++;
01071         }
01072
01073         husart->RxXferCount--;
01074       }
01075       rxdatacount = husart->RxXferCount;
01076     }
01077
01078     /* At end of TxRx process, restore husart->State to Ready */
01079     husart->State = HAL_USART_STATE_READY;
01080
01081     /* Process Unlocked */
01082     __HAL_UNLOCK(husart);
01083
01084     return HAL_OK;
01085   }
01086   else
01087   {
01088     return HAL_BUSY;
01089   }
01090 }
01091
01092 /**
01093   * @brief  Send an amount of data in interrupt mode.
01094   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01095   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01096   *         of u16 provided through pTxData.
01097   * @param  husart USART handle.
01098   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01099   * @param  Size amount of data elements (u8 or u16) to be sent.
01100   * @retval HAL status
01101   */
01102 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
01103 {
01104   if (husart->State == HAL_USART_STATE_READY)
01105   {
01106     if ((pTxData == NULL) || (Size == 0U))
01107     {
01108       return HAL_ERROR;
01109     }
01110
01111     /* Process Locked */
01112     __HAL_LOCK(husart);
01113
01114     husart->pTxBuffPtr  = pTxData;
01115     husart->TxXferSize  = Size;
01116     husart->TxXferCount = Size;
01117     husart->TxISR       = NULL;
01118
01119     husart->ErrorCode = HAL_USART_ERROR_NONE;
01120     husart->State     = HAL_USART_STATE_BUSY_TX;
01121
01122     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
01123     are not managed by the USART Transmit Process to avoid the overrun interrupt
01124     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
01125     to benefit for the frame error and noise interrupts the usart mode should be
01126     configured only for transmit "USART_MODE_TX" */
01127
01128     /* Configure Tx interrupt processing */
01129     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01130     {
01131       /* Set the Tx ISR function pointer according to the data word length */
01132       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01133       {
01134         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01135       }
01136       else
01137       {
01138         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01139       }
01140
01141       /* Process Unlocked */
01142       __HAL_UNLOCK(husart);
01143
01144       /* Enable the TX FIFO threshold interrupt */
01145       __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
01146     }
01147     else
01148     {
01149       /* Set the Tx ISR function pointer according to the data word length */
01150       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01151       {
01152         husart->TxISR = USART_TxISR_16BIT;
01153       }
01154       else
01155       {
01156         husart->TxISR = USART_TxISR_8BIT;
01157       }
01158
01159       /* Process Unlocked */
01160       __HAL_UNLOCK(husart);
01161
01162       /* Enable the USART Transmit Data Register Empty Interrupt */
01163       __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
01164     }
01165
01166     return HAL_OK;
01167   }
01168   else
01169   {
01170     return HAL_BUSY;
01171   }
01172 }
01173
01174 /**
01175   * @brief Receive an amount of data in interrupt mode.
01176   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
01177   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01178   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01179   *         of u16 available through pRxData.
01180   * @param  husart USART handle.
01181   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01182   * @param  Size amount of data elements (u8 or u16) to be received.
01183   * @retval HAL status
01184   */
01185 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01186 {
01187   uint16_t nb_dummy_data;
01188
01189   if (husart->State == HAL_USART_STATE_READY)
01190   {
01191     if ((pRxData == NULL) || (Size == 0U))
01192     {
01193       return HAL_ERROR;
01194     }
01195
01196     /* Process Locked */
01197     __HAL_LOCK(husart);
01198
01199     husart->pRxBuffPtr  = pRxData;
01200     husart->RxXferSize  = Size;
01201     husart->RxXferCount = Size;
01202     husart->RxISR       = NULL;
01203
01204     USART_MASK_COMPUTATION(husart);
01205
01206     husart->ErrorCode = HAL_USART_ERROR_NONE;
01207     husart->State = HAL_USART_STATE_BUSY_RX;
01208
01209     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01210     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01211
01212     /* Configure Rx interrupt processing */
01213     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01214     {
01215       /* Set the Rx ISR function pointer according to the data word length */
01216       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01217       {
01218         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01219       }
01220       else
01221       {
01222         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01223       }
01224
01225       /* Process Unlocked */
01226       __HAL_UNLOCK(husart);
01227
01228       /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
01229       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01230       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
01231     }
01232     else
01233     {
01234       /* Set the Rx ISR function pointer according to the data word length */
01235       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01236       {
01237         husart->RxISR = USART_RxISR_16BIT;
01238       }
01239       else
01240       {
01241         husart->RxISR = USART_RxISR_8BIT;
01242       }
01243
01244       /* Process Unlocked */
01245       __HAL_UNLOCK(husart);
01246
01247       /* Enable the USART Parity Error and Data Register not empty Interrupts */
01248       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01249     }
01250
01251     if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
01252     {
01253       /* Send dummy data in order to generate the clock for the Slave to send the next data.
01254          When FIFO mode is disabled only one data must be transferred.
01255          When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
01256       */
01257       if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01258       {
01259         for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
01260         {
01261           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01262         }
01263       }
01264       else
01265       {
01266         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01267       }
01268     }
01269
01270     return HAL_OK;
01271   }
01272   else
01273   {
01274     return HAL_BUSY;
01275   }
01276 }
01277
01278 /**
01279   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
01280   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01281   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01282   *         of u16 available through pTxData and through pRxData.
01283   * @param  husart USART handle.
01284   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01285   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01286   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
01287   * @retval HAL status
01288   */
01289 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
01290                                                uint16_t Size)
01291 {
01292
01293   if (husart->State == HAL_USART_STATE_READY)
01294   {
01295     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01296     {
01297       return HAL_ERROR;
01298     }
01299
01300     /* Process Locked */
01301     __HAL_LOCK(husart);
01302
01303     husart->pRxBuffPtr = pRxData;
01304     husart->RxXferSize = Size;
01305     husart->RxXferCount = Size;
01306     husart->pTxBuffPtr = pTxData;
01307     husart->TxXferSize = Size;
01308     husart->TxXferCount = Size;
01309
01310     /* Computation of USART mask to apply to RDR register */
01311     USART_MASK_COMPUTATION(husart);
01312
01313     husart->ErrorCode = HAL_USART_ERROR_NONE;
01314     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01315
01316     /* Configure TxRx interrupt processing */
01317     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01318     {
01319       /* Set the Rx ISR function pointer according to the data word length */
01320       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01321       {
01322         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01323         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01324       }
01325       else
01326       {
01327         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01328         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01329       }
01330
01331       /* Process Locked */
01332       __HAL_UNLOCK(husart);
01333
01334       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01335       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01336
01337       /* Enable the USART Parity Error interrupt  */
01338       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01339
01340       /* Enable the TX and  RX FIFO Threshold interrupts */
01341       SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
01342     }
01343     else
01344     {
01345       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01346       {
01347         husart->TxISR = USART_TxISR_16BIT;
01348         husart->RxISR = USART_RxISR_16BIT;
01349       }
01350       else
01351       {
01352         husart->TxISR = USART_TxISR_8BIT;
01353         husart->RxISR = USART_RxISR_8BIT;
01354       }
01355
01356       /* Process Locked */
01357       __HAL_UNLOCK(husart);
01358
01359       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01360       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01361
01362       /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
01363       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01364
01365       /* Enable the USART Transmit Data Register Empty Interrupt */
01366       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01367     }
01368
01369     return HAL_OK;
01370   }
01371   else
01372   {
01373     return HAL_BUSY;
01374   }
01375 }
01376
01377 /**
01378   * @brief Send an amount of data in DMA mode.
01379   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01380   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01381   *         of u16 provided through pTxData.
01382   * @param  husart USART handle.
01383   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01384   * @param  Size amount of data elements (u8 or u16) to be sent.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
01388 {
01389   HAL_StatusTypeDef status = HAL_OK;
01390   uint32_t *tmp;
01391
01392   if (husart->State == HAL_USART_STATE_READY)
01393   {
01394     if ((pTxData == NULL) || (Size == 0U))
01395     {
01396       return HAL_ERROR;
01397     }
01398
01399     /* Process Locked */
01400     __HAL_LOCK(husart);
01401
01402     husart->pTxBuffPtr = pTxData;
01403     husart->TxXferSize = Size;
01404     husart->TxXferCount = Size;
01405
01406     husart->ErrorCode = HAL_USART_ERROR_NONE;
01407     husart->State = HAL_USART_STATE_BUSY_TX;
01408
01409     if (husart->hdmatx != NULL)
01410     {
01411       /* Set the USART DMA transfer complete callback */
01412       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01413
01414       /* Set the USART DMA Half transfer complete callback */
01415       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01416
01417       /* Set the DMA error callback */
01418       husart->hdmatx->XferErrorCallback = USART_DMAError;
01419
01420       /* Enable the USART transmit DMA channel */
01421       tmp = (uint32_t *)&pTxData;
01422       status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01423     }
01424
01425     if (status == HAL_OK)
01426     {
01427       /* Clear the TC flag in the ICR register */
01428       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01429
01430       /* Process Unlocked */
01431       __HAL_UNLOCK(husart);
01432
01433       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01434          in the USART CR3 register */
01435       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01436
01437       return HAL_OK;
01438     }
01439     else
01440     {
01441       /* Set error code to DMA */
01442       husart->ErrorCode = HAL_USART_ERROR_DMA;
01443
01444       /* Process Unlocked */
01445       __HAL_UNLOCK(husart);
01446
01447       /* Restore husart->State to ready */
01448       husart->State = HAL_USART_STATE_READY;
01449
01450       return HAL_ERROR;
01451     }
01452   }
01453   else
01454   {
01455     return HAL_BUSY;
01456   }
01457 }
01458
01459 /**
01460   * @brief Receive an amount of data in DMA mode.
01461   * @note   When the USART parity is enabled (PCE = 1), the received data contain
01462   *         the parity bit (MSB position).
01463   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
01464   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01465   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01466   *         of u16 available through pRxData.
01467   * @param  husart USART handle.
01468   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01469   * @param  Size amount of data elements (u8 or u16) to be received.
01470   * @retval HAL status
01471   */
01472 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01473 {
01474   HAL_StatusTypeDef status = HAL_OK;
01475   uint32_t *tmp = (uint32_t *)&pRxData;
01476
01477   /* Check that a Rx process is not already ongoing */
01478   if (husart->State == HAL_USART_STATE_READY)
01479   {
01480     if ((pRxData == NULL) || (Size == 0U))
01481     {
01482       return HAL_ERROR;
01483     }
01484
01485     /* Process Locked */
01486     __HAL_LOCK(husart);
01487
01488     husart->pRxBuffPtr = pRxData;
01489     husart->RxXferSize = Size;
01490     husart->pTxBuffPtr = pRxData;
01491     husart->TxXferSize = Size;
01492
01493     husart->ErrorCode = HAL_USART_ERROR_NONE;
01494     husart->State = HAL_USART_STATE_BUSY_RX;
01495
01496     if (husart->hdmarx != NULL)
01497     {
01498       /* Set the USART DMA Rx transfer complete callback */
01499       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01500
01501       /* Set the USART DMA Half transfer complete callback */
01502       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01503
01504       /* Set the USART DMA Rx transfer error callback */
01505       husart->hdmarx->XferErrorCallback = USART_DMAError;
01506
01507       /* Enable the USART receive DMA channel */
01508       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01509     }
01510
01511     if ((status == HAL_OK) &&
01512         (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
01513     {
01514       /* Enable the USART transmit DMA channel: the transmit channel is used in order
01515          to generate in the non-blocking mode the clock to the slave device,
01516          this mode isn't a simplex receive mode but a full-duplex receive mode */
01517
01518       /* Set the USART DMA Tx Complete and Error callback to Null */
01519       if (husart->hdmatx != NULL)
01520       {
01521         husart->hdmatx->XferErrorCallback = NULL;
01522         husart->hdmatx->XferHalfCpltCallback = NULL;
01523         husart->hdmatx->XferCpltCallback = NULL;
01524         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01525       }
01526     }
01527
01528     if (status == HAL_OK)
01529     {
01530       /* Process Unlocked */
01531       __HAL_UNLOCK(husart);
01532
01533       /* Enable the USART Parity Error Interrupt */
01534       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01535
01536       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01537       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01538
01539       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01540          in the USART CR3 register */
01541       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01542
01543       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01544          in the USART CR3 register */
01545       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01546
01547       return HAL_OK;
01548     }
01549     else
01550     {
01551       if (husart->hdmarx != NULL)
01552       {
01553         status = HAL_DMA_Abort(husart->hdmarx);
01554       }
01555
01556       /* No need to check on error code */
01557       UNUSED(status);
01558
01559       /* Set error code to DMA */
01560       husart->ErrorCode = HAL_USART_ERROR_DMA;
01561
01562       /* Process Unlocked */
01563       __HAL_UNLOCK(husart);
01564
01565       /* Restore husart->State to ready */
01566       husart->State = HAL_USART_STATE_READY;
01567
01568       return HAL_ERROR;
01569     }
01570   }
01571   else
01572   {
01573     return HAL_BUSY;
01574   }
01575 }
01576
01577 /**
01578   * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01579   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01580   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01581   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01582   *         of u16 available through pTxData and through pRxData.
01583   * @param  husart USART handle.
01584   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01585   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01586   * @param  Size amount of data elements (u8 or u16) to be received/sent.
01587   * @retval HAL status
01588   */
01589 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
01590                                                 uint16_t Size)
01591 {
01592   HAL_StatusTypeDef status;
01593   uint32_t *tmp;
01594
01595   if (husart->State == HAL_USART_STATE_READY)
01596   {
01597     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01598     {
01599       return HAL_ERROR;
01600     }
01601
01602     /* Process Locked */
01603     __HAL_LOCK(husart);
01604
01605     husart->pRxBuffPtr = pRxData;
01606     husart->RxXferSize = Size;
01607     husart->pTxBuffPtr = pTxData;
01608     husart->TxXferSize = Size;
01609
01610     husart->ErrorCode = HAL_USART_ERROR_NONE;
01611     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01612
01613     if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
01614     {
01615       /* Set the USART DMA Rx transfer complete callback */
01616       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01617
01618       /* Set the USART DMA Half transfer complete callback */
01619       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01620
01621       /* Set the USART DMA Tx transfer complete callback */
01622       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01623
01624       /* Set the USART DMA Half transfer complete callback */
01625       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01626
01627       /* Set the USART DMA Tx transfer error callback */
01628       husart->hdmatx->XferErrorCallback = USART_DMAError;
01629
01630       /* Set the USART DMA Rx transfer error callback */
01631       husart->hdmarx->XferErrorCallback = USART_DMAError;
01632
01633       /* Enable the USART receive DMA channel */
01634       tmp = (uint32_t *)&pRxData;
01635       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01636
01637       /* Enable the USART transmit DMA channel */
01638       if (status == HAL_OK)
01639       {
01640         tmp = (uint32_t *)&pTxData;
01641         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01642       }
01643     }
01644     else
01645     {
01646       status = HAL_ERROR;
01647     }
01648
01649     if (status == HAL_OK)
01650     {
01651       /* Process Unlocked */
01652       __HAL_UNLOCK(husart);
01653
01654       /* Enable the USART Parity Error Interrupt */
01655       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01656
01657       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01658       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01659
01660       /* Clear the TC flag in the ICR register */
01661       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01662
01663       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01664          in the USART CR3 register */
01665       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01666
01667       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01668          in the USART CR3 register */
01669       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01670
01671       return HAL_OK;
01672     }
01673     else
01674     {
01675       if (husart->hdmarx != NULL)
01676       {
01677         status = HAL_DMA_Abort(husart->hdmarx);
01678       }
01679
01680       /* No need to check on error code */
01681       UNUSED(status);
01682
01683       /* Set error code to DMA */
01684       husart->ErrorCode = HAL_USART_ERROR_DMA;
01685
01686       /* Process Unlocked */
01687       __HAL_UNLOCK(husart);
01688
01689       /* Restore husart->State to ready */
01690       husart->State = HAL_USART_STATE_READY;
01691
01692       return HAL_ERROR;
01693     }
01694   }
01695   else
01696   {
01697     return HAL_BUSY;
01698   }
01699 }
01700
01701 /**
01702   * @brief Pause the DMA Transfer.
01703   * @param  husart USART handle.
01704   * @retval HAL status
01705   */
01706 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01707 {
01708   const HAL_USART_StateTypeDef state = husart->State;
01709
01710   /* Process Locked */
01711   __HAL_LOCK(husart);
01712
01713   if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
01714       (state == HAL_USART_STATE_BUSY_TX))
01715   {
01716     /* Disable the USART DMA Tx request */
01717     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01718   }
01719   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01720            (state == HAL_USART_STATE_BUSY_TX_RX))
01721   {
01722     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01723     {
01724       /* Disable the USART DMA Tx request */
01725       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01726     }
01727     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01728     {
01729       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01730       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01731       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01732
01733       /* Disable the USART DMA Rx request */
01734       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01735     }
01736   }
01737   else
01738   {
01739     /* Nothing to do */
01740   }
01741
01742   /* Process Unlocked */
01743   __HAL_UNLOCK(husart);
01744
01745   return HAL_OK;
01746 }
01747
01748 /**
01749   * @brief Resume the DMA Transfer.
01750   * @param  husart USART handle.
01751   * @retval HAL status
01752   */
01753 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01754 {
01755   const HAL_USART_StateTypeDef state = husart->State;
01756
01757   /* Process Locked */
01758   __HAL_LOCK(husart);
01759
01760   if (state == HAL_USART_STATE_BUSY_TX)
01761   {
01762     /* Enable the USART DMA Tx request */
01763     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01764   }
01765   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01766            (state == HAL_USART_STATE_BUSY_TX_RX))
01767   {
01768     /* Clear the Overrun flag before resuming the Rx transfer*/
01769     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01770
01771     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01772     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01773     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01774
01775     /* Enable the USART DMA Rx request  before the DMA Tx request */
01776     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01777
01778     /* Enable the USART DMA Tx request */
01779     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01780   }
01781   else
01782   {
01783     /* Nothing to do */
01784   }
01785
01786   /* Process Unlocked */
01787   __HAL_UNLOCK(husart);
01788
01789   return HAL_OK;
01790 }
01791
01792 /**
01793   * @brief Stop the DMA Transfer.
01794   * @param  husart USART handle.
01795   * @retval HAL status
01796   */
01797 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01798 {
01799   /* The Lock is not implemented on this API to allow the user application
01800      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01801      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01802      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01803      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01804      the stream and the corresponding call back is executed. */
01805
01806   /* Disable the USART Tx/Rx DMA requests */
01807   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01808   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01809
01810   /* Abort the USART DMA tx channel */
01811   if (husart->hdmatx != NULL)
01812   {
01813     if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01814     {
01815       if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01816       {
01817         /* Set error code to DMA */
01818         husart->ErrorCode = HAL_USART_ERROR_DMA;
01819
01820         return HAL_TIMEOUT;
01821       }
01822     }
01823   }
01824   /* Abort the USART DMA rx channel */
01825   if (husart->hdmarx != NULL)
01826   {
01827     if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01828     {
01829       if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01830       {
01831         /* Set error code to DMA */
01832         husart->ErrorCode = HAL_USART_ERROR_DMA;
01833
01834         return HAL_TIMEOUT;
01835       }
01836     }
01837   }
01838
01839   USART_EndTransfer(husart);
01840   husart->State = HAL_USART_STATE_READY;
01841
01842   return HAL_OK;
01843 }
01844
01845 /**
01846   * @brief  Abort ongoing transfers (blocking mode).
01847   * @param  husart USART handle.
01848   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01849   *         This procedure performs following operations :
01850   *           - Disable USART Interrupts (Tx and Rx)
01851   *           - Disable the DMA transfer in the peripheral register (if enabled)
01852   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01853   *           - Set handle State to READY
01854   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01855   * @retval HAL status
01856   */
01857 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01858 {
01859   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01860   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
01861                                     USART_CR1_TCIE));
01862   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01863
01864   /* Disable the USART DMA Tx request if enabled */
01865   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01866   {
01867     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01868
01869     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01870     if (husart->hdmatx != NULL)
01871     {
01872       /* Set the USART DMA Abort callback to Null.
01873          No call back execution at end of DMA abort procedure */
01874       husart->hdmatx->XferAbortCallback = NULL;
01875
01876       if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01877       {
01878         if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01879         {
01880           /* Set error code to DMA */
01881           husart->ErrorCode = HAL_USART_ERROR_DMA;
01882
01883           return HAL_TIMEOUT;
01884         }
01885       }
01886     }
01887   }
01888
01889   /* Disable the USART DMA Rx request if enabled */
01890   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01891   {
01892     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01893
01894     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01895     if (husart->hdmarx != NULL)
01896     {
01897       /* Set the USART DMA Abort callback to Null.
01898          No call back execution at end of DMA abort procedure */
01899       husart->hdmarx->XferAbortCallback = NULL;
01900
01901       if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01902       {
01903         if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01904         {
01905           /* Set error code to DMA */
01906           husart->ErrorCode = HAL_USART_ERROR_DMA;
01907
01908           return HAL_TIMEOUT;
01909         }
01910       }
01911     }
01912   }
01913
01914   /* Reset Tx and Rx transfer counters */
01915   husart->TxXferCount = 0U;
01916   husart->RxXferCount = 0U;
01917
01918   /* Clear the Error flags in the ICR register */
01919   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01920
01921   /* Flush the whole TX FIFO (if needed) */
01922   if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01923   {
01924     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
01925   }
01926
01927   /* Discard the received data */
01928   __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
01929
01930   /* Restore husart->State to Ready */
01931   husart->State  = HAL_USART_STATE_READY;
01932
01933   /* Reset Handle ErrorCode to No Error */
01934   husart->ErrorCode = HAL_USART_ERROR_NONE;
01935
01936   return HAL_OK;
01937 }
01938
01939 /**
01940   * @brief  Abort ongoing transfers (Interrupt mode).
01941   * @param  husart USART handle.
01942   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01943   *         This procedure performs following operations :
01944   *           - Disable USART Interrupts (Tx and Rx)
01945   *           - Disable the DMA transfer in the peripheral register (if enabled)
01946   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01947   *           - Set handle State to READY
01948   *           - At abort completion, call user abort complete callback
01949   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01950   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01951   * @retval HAL status
01952   */
01953 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01954 {
01955   uint32_t abortcplt = 1U;
01956
01957   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01958   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
01959                                     USART_CR1_TCIE));
01960   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01961
01962   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01963      before any call to DMA Abort functions */
01964   /* DMA Tx Handle is valid */
01965   if (husart->hdmatx != NULL)
01966   {
01967     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01968        Otherwise, set it to NULL */
01969     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01970     {
01971       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
01972     }
01973     else
01974     {
01975       husart->hdmatx->XferAbortCallback = NULL;
01976     }
01977   }
01978   /* DMA Rx Handle is valid */
01979   if (husart->hdmarx != NULL)
01980   {
01981     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
01982        Otherwise, set it to NULL */
01983     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01984     {
01985       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
01986     }
01987     else
01988     {
01989       husart->hdmarx->XferAbortCallback = NULL;
01990     }
01991   }
01992
01993   /* Disable the USART DMA Tx request if enabled */
01994   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01995   {
01996     /* Disable DMA Tx at USART level */
01997     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01998
01999     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
02000     if (husart->hdmatx != NULL)
02001     {
02002       /* USART Tx DMA Abort callback has already been initialised :
02003          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02004
02005       /* Abort DMA TX */
02006       if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
02007       {
02008         husart->hdmatx->XferAbortCallback = NULL;
02009       }
02010       else
02011       {
02012         abortcplt = 0U;
02013       }
02014     }
02015   }
02016
02017   /* Disable the USART DMA Rx request if enabled */
02018   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02019   {
02020     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02021
02022     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
02023     if (husart->hdmarx != NULL)
02024     {
02025       /* USART Rx DMA Abort callback has already been initialised :
02026          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02027
02028       /* Abort DMA RX */
02029       if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02030       {
02031         husart->hdmarx->XferAbortCallback = NULL;
02032         abortcplt = 1U;
02033       }
02034       else
02035       {
02036         abortcplt = 0U;
02037       }
02038     }
02039   }
02040
02041   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
02042   if (abortcplt == 1U)
02043   {
02044     /* Reset Tx and Rx transfer counters */
02045     husart->TxXferCount = 0U;
02046     husart->RxXferCount = 0U;
02047
02048     /* Reset errorCode */
02049     husart->ErrorCode = HAL_USART_ERROR_NONE;
02050
02051     /* Clear the Error flags in the ICR register */
02052     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02053
02054     /* Flush the whole TX FIFO (if needed) */
02055     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
02056     {
02057       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
02058     }
02059
02060     /* Discard the received data */
02061     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
02062
02063     /* Restore husart->State to Ready */
02064     husart->State  = HAL_USART_STATE_READY;
02065
02066     /* As no DMA to be aborted, call directly user Abort complete callback */
02067 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02068     /* Call registered Abort Complete Callback */
02069     husart->AbortCpltCallback(husart);
02070 #else
02071     /* Call legacy weak Abort Complete Callback */
02072     HAL_USART_AbortCpltCallback(husart);
02073 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02074   }
02075
02076   return HAL_OK;
02077 }
02078
02079 /**
02080   * @brief  Handle USART interrupt request.
02081   * @param  husart USART handle.
02082   * @retval None
02083   */
02084 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
02085 {
02086   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
02087   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
02088   uint32_t cr3its     = READ_REG(husart->Instance->CR3);
02089
02090   uint32_t errorflags;
02091   uint32_t errorcode;
02092
02093   /* If no error occurs */
02094   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
02095   if (errorflags == 0U)
02096   {
02097     /* USART in mode Receiver ---------------------------------------------------*/
02098     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02099         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02100             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02101     {
02102       if (husart->RxISR != NULL)
02103       {
02104         husart->RxISR(husart);
02105       }
02106       return;
02107     }
02108   }
02109
02110   /* If some errors occur */
02111   if ((errorflags != 0U)
02112       && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02113           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
02114   {
02115     /* USART parity error interrupt occurred -------------------------------------*/
02116     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02117     {
02118       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
02119
02120       husart->ErrorCode |= HAL_USART_ERROR_PE;
02121     }
02122
02123     /* USART frame error interrupt occurred --------------------------------------*/
02124     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02125     {
02126       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
02127
02128       husart->ErrorCode |= HAL_USART_ERROR_FE;
02129     }
02130
02131     /* USART noise error interrupt occurred --------------------------------------*/
02132     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02133     {
02134       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
02135
02136       husart->ErrorCode |= HAL_USART_ERROR_NE;
02137     }
02138
02139     /* USART Over-Run interrupt occurred -----------------------------------------*/
02140     if (((isrflags & USART_ISR_ORE) != 0U)
02141         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02142             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02143     {
02144       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
02145
02146       husart->ErrorCode |= HAL_USART_ERROR_ORE;
02147     }
02148
02149     /* USART SPI slave underrun error interrupt occurred -------------------------*/
02150     if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02151     {
02152       /* Ignore SPI slave underrun errors when reception is going on */
02153       if (husart->State == HAL_USART_STATE_BUSY_RX)
02154       {
02155         __HAL_USART_CLEAR_UDRFLAG(husart);
02156         return;
02157       }
02158       else
02159       {
02160         __HAL_USART_CLEAR_UDRFLAG(husart);
02161         husart->ErrorCode |= HAL_USART_ERROR_UDR;
02162       }
02163     }
02164
02165     /* Call USART Error Call back function if need be --------------------------*/
02166     if (husart->ErrorCode != HAL_USART_ERROR_NONE)
02167     {
02168       /* USART in mode Receiver ---------------------------------------------------*/
02169       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02170           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02171               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02172       {
02173         if (husart->RxISR != NULL)
02174         {
02175           husart->RxISR(husart);
02176         }
02177       }
02178
02179       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
02180          consider error as blocking */
02181       errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
02182       if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
02183           (errorcode != 0U))
02184       {
02185         /* Blocking error : transfer is aborted
02186            Set the USART state ready to be able to start again the process,
02187            Disable Interrupts, and disable DMA requests, if ongoing */
02188         USART_EndTransfer(husart);
02189
02190         /* Disable the USART DMA Rx request if enabled */
02191         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02192         {
02193           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
02194
02195           /* Abort the USART DMA Tx channel */
02196           if (husart->hdmatx != NULL)
02197           {
02198             /* Set the USART Tx DMA Abort callback to NULL : no callback
02199                executed at end of DMA abort procedure */
02200             husart->hdmatx->XferAbortCallback = NULL;
02201
02202             /* Abort DMA TX */
02203             (void)HAL_DMA_Abort_IT(husart->hdmatx);
02204           }
02205
02206           /* Abort the USART DMA Rx channel */
02207           if (husart->hdmarx != NULL)
02208           {
02209             /* Set the USART Rx DMA Abort callback :
02210                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
02211             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
02212
02213             /* Abort DMA RX */
02214             if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02215             {
02216               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
02217               husart->hdmarx->XferAbortCallback(husart->hdmarx);
02218             }
02219           }
02220           else
02221           {
02222             /* Call user error callback */
02223 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02224             /* Call registered Error Callback */
02225             husart->ErrorCallback(husart);
02226 #else
02227             /* Call legacy weak Error Callback */
02228             HAL_USART_ErrorCallback(husart);
02229 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02230           }
02231         }
02232         else
02233         {
02234           /* Call user error callback */
02235 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02236           /* Call registered Error Callback */
02237           husart->ErrorCallback(husart);
02238 #else
02239           /* Call legacy weak Error Callback */
02240           HAL_USART_ErrorCallback(husart);
02241 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02242         }
02243       }
02244       else
02245       {
02246         /* Non Blocking error : transfer could go on.
02247            Error is notified to user through user error callback */
02248 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02249         /* Call registered Error Callback */
02250         husart->ErrorCallback(husart);
02251 #else
02252         /* Call legacy weak Error Callback */
02253         HAL_USART_ErrorCallback(husart);
02254 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02255         husart->ErrorCode = HAL_USART_ERROR_NONE;
02256       }
02257     }
02258     return;
02259
02260   } /* End if some error occurs */
02261
02262
02263   /* USART in mode Transmitter ------------------------------------------------*/
02264   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02265       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02266           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02267   {
02268     if (husart->TxISR != NULL)
02269     {
02270       husart->TxISR(husart);
02271     }
02272     return;
02273   }
02274
02275   /* USART in mode Transmitter (transmission end) -----------------------------*/
02276   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02277   {
02278     USART_EndTransmit_IT(husart);
02279     return;
02280   }
02281
02282   /* USART TX Fifo Empty occurred ----------------------------------------------*/
02283   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02284   {
02285 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02286     /* Call registered Tx Fifo Empty Callback */
02287     husart->TxFifoEmptyCallback(husart);
02288 #else
02289     /* Call legacy weak Tx Fifo Empty Callback */
02290     HAL_USARTEx_TxFifoEmptyCallback(husart);
02291 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02292     return;
02293   }
02294
02295   /* USART RX Fifo Full occurred ----------------------------------------------*/
02296   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02297   {
02298 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02299     /* Call registered Rx Fifo Full Callback */
02300     husart->RxFifoFullCallback(husart);
02301 #else
02302     /* Call legacy weak Rx Fifo Full Callback */
02303     HAL_USARTEx_RxFifoFullCallback(husart);
02304 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02305     return;
02306   }
02307 }
02308
02309 /**
02310   * @brief Tx Transfer completed callback.
02311   * @param husart USART handle.
02312   * @retval None
02313   */
02314 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
02315 {
02316   /* Prevent unused argument(s) compilation warning */
02317   UNUSED(husart);
02318
02319   /* NOTE : This function should not be modified, when the callback is needed,
02320             the HAL_USART_TxCpltCallback can be implemented in the user file.
02321    */
02322 }
02323
02324 /**
02325   * @brief  Tx Half Transfer completed callback.
02326   * @param husart USART handle.
02327   * @retval None
02328   */
02329 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
02330 {
02331   /* Prevent unused argument(s) compilation warning */
02332   UNUSED(husart);
02333
02334   /* NOTE: This function should not be modified, when the callback is needed,
02335            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
02336    */
02337 }
02338
02339 /**
02340   * @brief  Rx Transfer completed callback.
02341   * @param husart USART handle.
02342   * @retval None
02343   */
02344 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
02345 {
02346   /* Prevent unused argument(s) compilation warning */
02347   UNUSED(husart);
02348
02349   /* NOTE: This function should not be modified, when the callback is needed,
02350            the HAL_USART_RxCpltCallback can be implemented in the user file.
02351    */
02352 }
02353
02354 /**
02355   * @brief Rx Half Transfer completed callback.
02356   * @param husart USART handle.
02357   * @retval None
02358   */
02359 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
02360 {
02361   /* Prevent unused argument(s) compilation warning */
02362   UNUSED(husart);
02363
02364   /* NOTE : This function should not be modified, when the callback is needed,
02365             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
02366    */
02367 }
02368
02369 /**
02370   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
02371   * @param husart USART handle.
02372   * @retval None
02373   */
02374 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
02375 {
02376   /* Prevent unused argument(s) compilation warning */
02377   UNUSED(husart);
02378
02379   /* NOTE : This function should not be modified, when the callback is needed,
02380             the HAL_USART_TxRxCpltCallback can be implemented in the user file
02381    */
02382 }
02383
02384 /**
02385   * @brief USART error callback.
02386   * @param husart USART handle.
02387   * @retval None
02388   */
02389 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
02390 {
02391   /* Prevent unused argument(s) compilation warning */
02392   UNUSED(husart);
02393
02394   /* NOTE : This function should not be modified, when the callback is needed,
02395             the HAL_USART_ErrorCallback can be implemented in the user file.
02396    */
02397 }
02398
02399 /**
02400   * @brief  USART Abort Complete callback.
02401   * @param  husart USART handle.
02402   * @retval None
02403   */
02404 __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
02405 {
02406   /* Prevent unused argument(s) compilation warning */
02407   UNUSED(husart);
02408
02409   /* NOTE : This function should not be modified, when the callback is needed,
02410             the HAL_USART_AbortCpltCallback can be implemented in the user file.
02411    */
02412 }
02413
02414 /**
02415   * @}
02416   */
02417
02418 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
02419   *  @brief   USART Peripheral State and Error functions
02420   *
02421 @verbatim
02422   ==============================================================================
02423             ##### Peripheral State and Error functions #####
02424   ==============================================================================
02425     [..]
02426     This subsection provides functions allowing to :
02427       (+) Return the USART handle state
02428       (+) Return the USART handle error code
02429
02430 @endverbatim
02431   * @{
02432   */
02433
02434
02435 /**
02436   * @brief Return the USART handle state.
02437   * @param husart pointer to a USART_HandleTypeDef structure that contains
02438   *              the configuration information for the specified USART.
02439   * @retval USART handle state
02440   */
02441 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
02442 {
02443   return husart->State;
02444 }
02445
02446 /**
02447   * @brief Return the USART error code.
02448   * @param husart pointer to a USART_HandleTypeDef structure that contains
02449   *              the configuration information for the specified USART.
02450   * @retval USART handle Error Code
02451   */
02452 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
02453 {
02454   return husart->ErrorCode;
02455 }
02456
02457 /**
02458   * @}
02459   */
02460
02461 /**
02462   * @}
02463   */
02464
02465 /** @defgroup USART_Private_Functions USART Private Functions
02466   * @{
02467   */
02468
02469 /**
02470   * @brief  Initialize the callbacks to their default values.
02471   * @param  husart USART handle.
02472   * @retval none
02473   */
02474 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02475 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
02476 {
02477   /* Init the USART Callback settings */
02478   husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02479   husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02480   husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02481   husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02482   husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
02483   husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02484   husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02485   husart->RxFifoFullCallback        = HAL_USARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02486   husart->TxFifoEmptyCallback       = HAL_USARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02487 }
02488 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02489
02490 /**
02491   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
02492   * @param  husart USART handle.
02493   * @retval None
02494   */
02495 static void USART_EndTransfer(USART_HandleTypeDef *husart)
02496 {
02497   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02498   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
02499                                     USART_CR1_TCIE));
02500   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02501
02502   /* At end of process, restore husart->State to Ready */
02503   husart->State = HAL_USART_STATE_READY;
02504 }
02505
02506 /**
02507   * @brief DMA USART transmit process complete callback.
02508   * @param  hdma DMA handle.
02509   * @retval None
02510   */
02511 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02512 {
02513   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02514
02515   /* DMA Normal mode */
02516   if (hdma->Init.Mode != DMA_CIRCULAR)
02517   {
02518     husart->TxXferCount = 0U;
02519
02520     if (husart->State == HAL_USART_STATE_BUSY_TX)
02521     {
02522       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02523          in the USART CR3 register */
02524       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02525
02526       /* Enable the USART Transmit Complete Interrupt */
02527       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02528     }
02529   }
02530   /* DMA Circular mode */
02531   else
02532   {
02533     if (husart->State == HAL_USART_STATE_BUSY_TX)
02534     {
02535 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02536       /* Call registered Tx Complete Callback */
02537       husart->TxCpltCallback(husart);
02538 #else
02539       /* Call legacy weak Tx Complete Callback */
02540       HAL_USART_TxCpltCallback(husart);
02541 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02542     }
02543   }
02544 }
02545
02546 /**
02547   * @brief DMA USART transmit process half complete callback.
02548   * @param  hdma DMA handle.
02549   * @retval None
02550   */
02551 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02552 {
02553   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02554
02555 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02556   /* Call registered Tx Half Complete Callback */
02557   husart->TxHalfCpltCallback(husart);
02558 #else
02559   /* Call legacy weak Tx Half Complete Callback */
02560   HAL_USART_TxHalfCpltCallback(husart);
02561 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02562 }
02563
02564 /**
02565   * @brief DMA USART receive process complete callback.
02566   * @param  hdma DMA handle.
02567   * @retval None
02568   */
02569 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02570 {
02571   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02572
02573   /* DMA Normal mode */
02574   if (hdma->Init.Mode != DMA_CIRCULAR)
02575   {
02576     husart->RxXferCount = 0U;
02577
02578     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02579     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02580     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02581
02582     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
02583        in USART CR3 register */
02584     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02585     /* similarly, disable the DMA TX transfer that was started to provide the
02586        clock to the slave device */
02587     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02588
02589     if (husart->State == HAL_USART_STATE_BUSY_RX)
02590     {
02591 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02592       /* Call registered Rx Complete Callback */
02593       husart->RxCpltCallback(husart);
02594 #else
02595       /* Call legacy weak Rx Complete Callback */
02596       HAL_USART_RxCpltCallback(husart);
02597 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02598     }
02599     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02600     else
02601     {
02602 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02603       /* Call registered Tx Rx Complete Callback */
02604       husart->TxRxCpltCallback(husart);
02605 #else
02606       /* Call legacy weak Tx Rx Complete Callback */
02607       HAL_USART_TxRxCpltCallback(husart);
02608 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02609     }
02610     husart->State = HAL_USART_STATE_READY;
02611   }
02612   /* DMA circular mode */
02613   else
02614   {
02615     if (husart->State == HAL_USART_STATE_BUSY_RX)
02616     {
02617 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02618       /* Call registered Rx Complete Callback */
02619       husart->RxCpltCallback(husart);
02620 #else
02621       /* Call legacy weak Rx Complete Callback */
02622       HAL_USART_RxCpltCallback(husart);
02623 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02624     }
02625     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02626     else
02627     {
02628 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02629       /* Call registered Tx Rx Complete Callback */
02630       husart->TxRxCpltCallback(husart);
02631 #else
02632       /* Call legacy weak Tx Rx Complete Callback */
02633       HAL_USART_TxRxCpltCallback(husart);
02634 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02635     }
02636   }
02637 }
02638
02639 /**
02640   * @brief DMA USART receive process half complete callback.
02641   * @param  hdma DMA handle.
02642   * @retval None
02643   */
02644 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02645 {
02646   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02647
02648 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02649   /* Call registered Rx Half Complete Callback */
02650   husart->RxHalfCpltCallback(husart);
02651 #else
02652   /* Call legacy weak Rx Half Complete Callback */
02653   HAL_USART_RxHalfCpltCallback(husart);
02654 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02655 }
02656
02657 /**
02658   * @brief DMA USART communication error callback.
02659   * @param  hdma DMA handle.
02660   * @retval None
02661   */
02662 static void USART_DMAError(DMA_HandleTypeDef *hdma)
02663 {
02664   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02665
02666   husart->RxXferCount = 0U;
02667   husart->TxXferCount = 0U;
02668   USART_EndTransfer(husart);
02669
02670   husart->ErrorCode |= HAL_USART_ERROR_DMA;
02671   husart->State = HAL_USART_STATE_READY;
02672
02673 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02674   /* Call registered Error Callback */
02675   husart->ErrorCallback(husart);
02676 #else
02677   /* Call legacy weak Error Callback */
02678   HAL_USART_ErrorCallback(husart);
02679 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02680 }
02681
02682 /**
02683   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
02684   *         (To be called at end of DMA Abort procedure following error occurrence).
02685   * @param  hdma DMA handle.
02686   * @retval None
02687   */
02688 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02689 {
02690   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02691   husart->RxXferCount = 0U;
02692   husart->TxXferCount = 0U;
02693
02694 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02695   /* Call registered Error Callback */
02696   husart->ErrorCallback(husart);
02697 #else
02698   /* Call legacy weak Error Callback */
02699   HAL_USART_ErrorCallback(husart);
02700 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02701 }
02702
02703 /**
02704   * @brief  DMA USART Tx communication abort callback, when initiated by user
02705   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02706   * @note   When this callback is executed, User Abort complete call back is called only if no
02707   *         Abort still ongoing for Rx DMA Handle.
02708   * @param  hdma DMA handle.
02709   * @retval None
02710   */
02711 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02712 {
02713   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02714
02715   husart->hdmatx->XferAbortCallback = NULL;
02716
02717   /* Check if an Abort process is still ongoing */
02718   if (husart->hdmarx != NULL)
02719   {
02720     if (husart->hdmarx->XferAbortCallback != NULL)
02721     {
02722       return;
02723     }
02724   }
02725
02726   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02727   husart->TxXferCount = 0U;
02728   husart->RxXferCount = 0U;
02729
02730   /* Reset errorCode */
02731   husart->ErrorCode = HAL_USART_ERROR_NONE;
02732
02733   /* Clear the Error flags in the ICR register */
02734   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02735
02736   /* Restore husart->State to Ready */
02737   husart->State = HAL_USART_STATE_READY;
02738
02739   /* Call user Abort complete callback */
02740 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02741   /* Call registered Abort Complete Callback */
02742   husart->AbortCpltCallback(husart);
02743 #else
02744   /* Call legacy weak Abort Complete Callback */
02745   HAL_USART_AbortCpltCallback(husart);
02746 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02747
02748 }
02749
02750
02751 /**
02752   * @brief  DMA USART Rx communication abort callback, when initiated by user
02753   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02754   * @note   When this callback is executed, User Abort complete call back is called only if no
02755   *         Abort still ongoing for Tx DMA Handle.
02756   * @param  hdma DMA handle.
02757   * @retval None
02758   */
02759 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02760 {
02761   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02762
02763   husart->hdmarx->XferAbortCallback = NULL;
02764
02765   /* Check if an Abort process is still ongoing */
02766   if (husart->hdmatx != NULL)
02767   {
02768     if (husart->hdmatx->XferAbortCallback != NULL)
02769     {
02770       return;
02771     }
02772   }
02773
02774   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02775   husart->TxXferCount = 0U;
02776   husart->RxXferCount = 0U;
02777
02778   /* Reset errorCode */
02779   husart->ErrorCode = HAL_USART_ERROR_NONE;
02780
02781   /* Clear the Error flags in the ICR register */
02782   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02783
02784   /* Restore husart->State to Ready */
02785   husart->State  = HAL_USART_STATE_READY;
02786
02787   /* Call user Abort complete callback */
02788 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02789   /* Call registered Abort Complete Callback */
02790   husart->AbortCpltCallback(husart);
02791 #else
02792   /* Call legacy weak Abort Complete Callback */
02793   HAL_USART_AbortCpltCallback(husart);
02794 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02795 }
02796
02797
02798 /**
02799   * @brief  Handle USART Communication Timeout.
02800   * @param  husart USART handle.
02801   * @param  Flag Specifies the USART flag to check.
02802   * @param  Status the Flag status (SET or RESET).
02803   * @param  Tickstart Tick start value
02804   * @param  Timeout timeout duration.
02805   * @retval HAL status
02806   */
02807 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
02808                                                       uint32_t Tickstart, uint32_t Timeout)
02809 {
02810   /* Wait until flag is set */
02811   while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
02812   {
02813     /* Check for the Timeout */
02814     if (Timeout != HAL_MAX_DELAY)
02815     {
02816       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02817       {
02818         husart->State = HAL_USART_STATE_READY;
02819
02820         /* Process Unlocked */
02821         __HAL_UNLOCK(husart);
02822
02823         return HAL_TIMEOUT;
02824       }
02825     }
02826   }
02827   return HAL_OK;
02828 }
02829
02830 /**
02831   * @brief Configure the USART peripheral.
02832   * @param husart USART handle.
02833   * @retval HAL status
02834   */
02835 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
02836 {
02837   uint32_t tmpreg;
02838   USART_ClockSourceTypeDef clocksource;
02839   HAL_StatusTypeDef ret                = HAL_OK;
02840   uint16_t brrtemp;
02841   uint32_t usartdiv                    = 0x00000000;
02842   PLL2_ClocksTypeDef pll2_clocks;
02843   PLL3_ClocksTypeDef pll3_clocks;
02844   uint32_t pclk;
02845
02846   /* Check the parameters */
02847   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02848   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02849   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02850   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02851   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02852   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02853   assert_param(IS_USART_PARITY(husart->Init.Parity));
02854   assert_param(IS_USART_MODE(husart->Init.Mode));
02855   assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
02856
02857   /*-------------------------- USART CR1 Configuration -----------------------*/
02858   /* Clear M, PCE, PS, TE and RE bits and configure
02859   *  the USART Word Length, Parity and Mode:
02860   *  set the M bits according to husart->Init.WordLength value
02861   *  set PCE and PS bits according to husart->Init.Parity value
02862   *  set TE and RE bits according to husart->Init.Mode value
02863   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
02864   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
02865   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02866
02867   /*---------------------------- USART CR2 Configuration ---------------------*/
02868   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
02869    * set CPOL bit according to husart->Init.CLKPolarity value
02870    * set CPHA bit according to husart->Init.CLKPhase value
02871    * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
02872    * set STOP[13:12] bits according to husart->Init.StopBits value */
02873   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
02874   tmpreg |= (uint32_t)husart->Init.CLKLastBit;
02875   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
02876   tmpreg |= (uint32_t)husart->Init.StopBits;
02877   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02878
02879   /*-------------------------- USART PRESC Configuration -----------------------*/
02880   /* Configure
02881    * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
02882   MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
02883
02884   /*-------------------------- USART BRR Configuration -----------------------*/
02885   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
02886   USART_GETCLOCKSOURCE(husart, clocksource);
02887
02888   switch (clocksource)
02889   {
02890     case USART_CLOCKSOURCE_D2PCLK1:
02891       pclk = HAL_RCC_GetPCLK1Freq();
02892       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02893       break;
02894     case USART_CLOCKSOURCE_D2PCLK2:
02895       pclk = HAL_RCC_GetPCLK2Freq();
02896       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02897       break;
02898     case USART_CLOCKSOURCE_PLL2:
02899       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02900       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02901       break;
02902     case USART_CLOCKSOURCE_PLL3:
02903       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02904       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02905       break;
02906     case USART_CLOCKSOURCE_HSI:
02907       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02908       {
02909         usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), husart->Init.BaudRate, husart->Init.ClockPrescaler));
02910       }
02911       else
02912       {
02913         usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02914       }
02915       break;
02916     case USART_CLOCKSOURCE_CSI:
02917       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02918       break;
02919     case USART_CLOCKSOURCE_LSE:
02920       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02921       break;
02922     default:
02923       ret = HAL_ERROR;
02924       break;
02925   }
02926
02927   /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
02928   if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
02929   {
02930     brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
02931     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02932     husart->Instance->BRR = brrtemp;
02933   }
02934   else
02935   {
02936     ret = HAL_ERROR;
02937   }
02938
02939   /* Initialize the number of data to process during RX/TX ISR execution */
02940   husart->NbTxDataToProcess = 1U;
02941   husart->NbRxDataToProcess = 1U;
02942
02943   /* Clear ISR function pointers */
02944   husart->RxISR   = NULL;
02945   husart->TxISR   = NULL;
02946
02947   return ret;
02948 }
02949
02950 /**
02951   * @brief Check the USART Idle State.
02952   * @param husart USART handle.
02953   * @retval HAL status
02954   */
02955 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
02956 {
02957   uint32_t tickstart;
02958
02959   /* Initialize the USART ErrorCode */
02960   husart->ErrorCode = HAL_USART_ERROR_NONE;
02961
02962   /* Init tickstart for timeout managment*/
02963   tickstart = HAL_GetTick();
02964
02965   /* Check if the Transmitter is enabled */
02966   if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02967   {
02968     /* Wait until TEACK flag is set */
02969     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02970     {
02971       /* Timeout occurred */
02972       return HAL_TIMEOUT;
02973     }
02974   }
02975   /* Check if the Receiver is enabled */
02976   if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02977   {
02978     /* Wait until REACK flag is set */
02979     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02980     {
02981       /* Timeout occurred */
02982       return HAL_TIMEOUT;
02983     }
02984   }
02985
02986   /* Initialize the USART state*/
02987   husart->State = HAL_USART_STATE_READY;
02988
02989   /* Process Unlocked */
02990   __HAL_UNLOCK(husart);
02991
02992   return HAL_OK;
02993 }
02994
02995 /**
02996   * @brief  Simplex send an amount of data in non-blocking mode.
02997   * @note   Function called under interruption only, once
02998   *         interruptions have been enabled by HAL_USART_Transmit_IT().
02999   * @note   The USART errors are not managed to avoid the overrun error.
03000   * @note   ISR function executed when FIFO mode is disabled and when the
03001   *         data word length is less than 9 bits long.
03002   * @param  husart USART handle.
03003   * @retval None
03004   */
03005 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
03006 {
03007   const HAL_USART_StateTypeDef state = husart->State;
03008
03009   /* Check that a Tx process is ongoing */
03010   if ((state == HAL_USART_STATE_BUSY_TX) ||
03011       (state == HAL_USART_STATE_BUSY_TX_RX))
03012   {
03013     if (husart->TxXferCount == 0U)
03014     {
03015       /* Disable the USART Transmit data register empty interrupt */
03016       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03017
03018       /* Enable the USART Transmit Complete Interrupt */
03019       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03020     }
03021     else
03022     {
03023       husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03024       husart->pTxBuffPtr++;
03025       husart->TxXferCount--;
03026     }
03027   }
03028 }
03029
03030 /**
03031   * @brief  Simplex send an amount of data in non-blocking mode.
03032   * @note   Function called under interruption only, once
03033   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03034   * @note   The USART errors are not managed to avoid the overrun error.
03035   * @note   ISR function executed when FIFO mode is disabled and when the
03036   *         data word length is 9 bits long.
03037   * @param  husart USART handle.
03038   * @retval None
03039   */
03040 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
03041 {
03042   const HAL_USART_StateTypeDef state = husart->State;
03043   uint16_t *tmp;
03044
03045   if ((state == HAL_USART_STATE_BUSY_TX) ||
03046       (state == HAL_USART_STATE_BUSY_TX_RX))
03047   {
03048     if (husart->TxXferCount == 0U)
03049     {
03050       /* Disable the USART Transmit data register empty interrupt */
03051       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03052
03053       /* Enable the USART Transmit Complete Interrupt */
03054       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03055     }
03056     else
03057     {
03058       tmp = (uint16_t *) husart->pTxBuffPtr;
03059       husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03060       husart->pTxBuffPtr += 2U;
03061       husart->TxXferCount--;
03062     }
03063   }
03064 }
03065
03066 /**
03067   * @brief  Simplex send an amount of data in non-blocking mode.
03068   * @note   Function called under interruption only, once
03069   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03070   * @note   The USART errors are not managed to avoid the overrun error.
03071   * @note   ISR function executed when FIFO mode is enabled and when the
03072   *         data word length is less than 9 bits long.
03073   * @param  husart USART handle.
03074   * @retval None
03075   */
03076 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03077 {
03078   const HAL_USART_StateTypeDef state = husart->State;
03079   uint16_t  nb_tx_data;
03080
03081   /* Check that a Tx process is ongoing */
03082   if ((state == HAL_USART_STATE_BUSY_TX) ||
03083       (state == HAL_USART_STATE_BUSY_TX_RX))
03084   {
03085     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03086     {
03087       if (husart->TxXferCount == 0U)
03088       {
03089         /* Disable the TX FIFO threshold interrupt */
03090         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03091
03092         /* Enable the USART Transmit Complete Interrupt */
03093         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03094
03095         break; /* force exit loop */
03096       }
03097       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03098       {
03099         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03100         husart->pTxBuffPtr++;
03101         husart->TxXferCount--;
03102       }
03103       else
03104       {
03105         /* Nothing to do */
03106       }
03107     }
03108   }
03109 }
03110
03111 /**
03112   * @brief  Simplex send an amount of data in non-blocking mode.
03113   * @note   Function called under interruption only, once
03114   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03115   * @note   The USART errors are not managed to avoid the overrun error.
03116   * @note   ISR function executed when FIFO mode is enabled and when the
03117   *         data word length is 9 bits long.
03118   * @param  husart USART handle.
03119   * @retval None
03120   */
03121 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03122 {
03123   const HAL_USART_StateTypeDef state = husart->State;
03124   uint16_t *tmp;
03125   uint16_t  nb_tx_data;
03126
03127   /* Check that a Tx process is ongoing */
03128   if ((state == HAL_USART_STATE_BUSY_TX) ||
03129       (state == HAL_USART_STATE_BUSY_TX_RX))
03130   {
03131     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03132     {
03133       if (husart->TxXferCount == 0U)
03134       {
03135         /* Disable the TX FIFO threshold interrupt */
03136         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03137
03138         /* Enable the USART Transmit Complete Interrupt */
03139         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03140
03141         break; /* force exit loop */
03142       }
03143       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03144       {
03145         tmp = (uint16_t *) husart->pTxBuffPtr;
03146         husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03147         husart->pTxBuffPtr += 2U;
03148         husart->TxXferCount--;
03149       }
03150       else
03151       {
03152         /* Nothing to do */
03153       }
03154     }
03155   }
03156 }
03157
03158 /**
03159   * @brief  Wraps up transmission in non-blocking mode.
03160   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
03161   *                the configuration information for the specified USART module.
03162   * @retval None
03163   */
03164 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
03165 {
03166   /* Disable the USART Transmit Complete Interrupt */
03167   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
03168
03169   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03170   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
03171
03172   /* Clear TxISR function pointer */
03173   husart->TxISR = NULL;
03174
03175   if (husart->State == HAL_USART_STATE_BUSY_TX)
03176   {
03177     /* Clear overrun flag and discard the received data */
03178     __HAL_USART_CLEAR_OREFLAG(husart);
03179     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03180
03181     /* Tx process is completed, restore husart->State to Ready */
03182     husart->State = HAL_USART_STATE_READY;
03183
03184 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03185     /* Call registered Tx Complete Callback */
03186     husart->TxCpltCallback(husart);
03187 #else
03188     /* Call legacy weak Tx Complete Callback */
03189     HAL_USART_TxCpltCallback(husart);
03190 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03191   }
03192   else if (husart->RxXferCount == 0U)
03193   {
03194     /* TxRx process is completed, restore husart->State to Ready */
03195     husart->State = HAL_USART_STATE_READY;
03196
03197 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03198     /* Call registered Tx Rx Complete Callback */
03199     husart->TxRxCpltCallback(husart);
03200 #else
03201     /* Call legacy weak Tx Rx Complete Callback */
03202     HAL_USART_TxRxCpltCallback(husart);
03203 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03204   }
03205   else
03206   {
03207     /* Nothing to do */
03208   }
03209 }
03210
03211
03212 /**
03213   * @brief  Simplex receive an amount of data in non-blocking mode.
03214   * @note   Function called under interruption only, once
03215   *         interruptions have been enabled by HAL_USART_Receive_IT().
03216   * @note   ISR function executed when FIFO mode is disabled and when the
03217   *         data word length is less than 9 bits long.
03218   * @param  husart USART handle
03219   * @retval None
03220   */
03221 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
03222 {
03223   const HAL_USART_StateTypeDef state = husart->State;
03224   uint16_t txdatacount;
03225   uint16_t uhMask = husart->Mask;
03226   uint32_t txftie;
03227
03228   if ((state == HAL_USART_STATE_BUSY_RX) ||
03229       (state == HAL_USART_STATE_BUSY_TX_RX))
03230   {
03231     *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
03232     husart->pRxBuffPtr++;
03233     husart->RxXferCount--;
03234
03235     if (husart->RxXferCount == 0U)
03236     {
03237       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03238       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03239
03240       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03241       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03242
03243       /* Clear RxISR function pointer */
03244       husart->RxISR = NULL;
03245
03246       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03247       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03248       txdatacount = husart->TxXferCount;
03249
03250       if (state == HAL_USART_STATE_BUSY_RX)
03251       {
03252         /* Clear SPI slave underrun flag and discard transmit data */
03253         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03254         {
03255           __HAL_USART_CLEAR_UDRFLAG(husart);
03256           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03257         }
03258
03259         /* Rx process is completed, restore husart->State to Ready */
03260         husart->State = HAL_USART_STATE_READY;
03261
03262 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03263         /* Call registered Rx Complete Callback */
03264         husart->RxCpltCallback(husart);
03265 #else
03266         /* Call legacy weak Rx Complete Callback */
03267         HAL_USART_RxCpltCallback(husart);
03268 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03269       }
03270       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03271                (txftie != USART_CR3_TXFTIE) &&
03272                (txdatacount == 0U))
03273       {
03274         /* TxRx process is completed, restore husart->State to Ready */
03275         husart->State = HAL_USART_STATE_READY;
03276
03277 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03278         /* Call registered Tx Rx Complete Callback */
03279         husart->TxRxCpltCallback(husart);
03280 #else
03281         /* Call legacy weak Tx Rx Complete Callback */
03282         HAL_USART_TxRxCpltCallback(husart);
03283 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03284       }
03285       else
03286       {
03287         /* Nothing to do */
03288       }
03289     }
03290     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03291              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03292     {
03293       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03294       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03295     }
03296     else
03297     {
03298       /* Nothing to do */
03299     }
03300   }
03301 }
03302
03303 /**
03304   * @brief  Simplex receive an amount of data in non-blocking mode.
03305   * @note   Function called under interruption only, once
03306   *         interruptions have been enabled by HAL_USART_Receive_IT().
03307   * @note   ISR function executed when FIFO mode is disabled and when the
03308   *         data word length is 9 bits long.
03309   * @param  husart USART handle
03310   * @retval None
03311   */
03312 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
03313 {
03314   const HAL_USART_StateTypeDef state = husart->State;
03315   uint16_t txdatacount;
03316   uint16_t *tmp;
03317   uint16_t uhMask = husart->Mask;
03318   uint32_t txftie;
03319
03320   if ((state == HAL_USART_STATE_BUSY_RX) ||
03321       (state == HAL_USART_STATE_BUSY_TX_RX))
03322   {
03323     tmp = (uint16_t *) husart->pRxBuffPtr;
03324     *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03325     husart->pRxBuffPtr += 2U;
03326     husart->RxXferCount--;
03327
03328     if (husart->RxXferCount == 0U)
03329     {
03330       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03331       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03332
03333       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03334       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03335
03336       /* Clear RxISR function pointer */
03337       husart->RxISR = NULL;
03338
03339       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03340       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03341       txdatacount = husart->TxXferCount;
03342
03343       if (state == HAL_USART_STATE_BUSY_RX)
03344       {
03345         /* Clear SPI slave underrun flag and discard transmit data */
03346         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03347         {
03348           __HAL_USART_CLEAR_UDRFLAG(husart);
03349           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03350         }
03351
03352         /* Rx process is completed, restore husart->State to Ready */
03353         husart->State = HAL_USART_STATE_READY;
03354
03355 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03356         /* Call registered Rx Complete Callback */
03357         husart->RxCpltCallback(husart);
03358 #else
03359         /* Call legacy weak Rx Complete Callback */
03360         HAL_USART_RxCpltCallback(husart);
03361 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03362       }
03363       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03364                (txftie != USART_CR3_TXFTIE) &&
03365                (txdatacount == 0U))
03366       {
03367         /* TxRx process is completed, restore husart->State to Ready */
03368         husart->State = HAL_USART_STATE_READY;
03369
03370 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03371         /* Call registered Tx Rx Complete Callback */
03372         husart->TxRxCpltCallback(husart);
03373 #else
03374         /* Call legacy weak Tx Rx Complete Callback */
03375         HAL_USART_TxRxCpltCallback(husart);
03376 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03377       }
03378       else
03379       {
03380         /* Nothing to do */
03381       }
03382     }
03383     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03384              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03385     {
03386       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03387       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03388     }
03389     else
03390     {
03391       /* Nothing to do */
03392     }
03393   }
03394 }
03395
03396 /**
03397   * @brief  Simplex receive an amount of data in non-blocking mode.
03398   * @note   Function called under interruption only, once
03399   *         interruptions have been enabled by HAL_USART_Receive_IT().
03400   * @note   ISR function executed when FIFO mode is enabled and when the
03401   *         data word length is less than 9 bits long.
03402   * @param  husart USART handle
03403   * @retval None
03404   */
03405 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03406 {
03407   HAL_USART_StateTypeDef state = husart->State;
03408   uint16_t txdatacount;
03409   uint16_t rxdatacount;
03410   uint16_t uhMask = husart->Mask;
03411   uint16_t nb_rx_data;
03412   uint32_t txftie;
03413
03414   /* Check that a Rx process is ongoing */
03415   if ((state == HAL_USART_STATE_BUSY_RX) ||
03416       (state == HAL_USART_STATE_BUSY_TX_RX))
03417   {
03418     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03419     {
03420       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03421       {
03422         *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
03423         husart->pRxBuffPtr++;
03424         husart->RxXferCount--;
03425
03426         if (husart->RxXferCount == 0U)
03427         {
03428           /* Disable the USART Parity Error Interrupt */
03429           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03430
03431           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03432           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03433
03434           /* Clear RxISR function pointer */
03435           husart->RxISR = NULL;
03436
03437           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03438           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03439           txdatacount = husart->TxXferCount;
03440
03441           if (state == HAL_USART_STATE_BUSY_RX)
03442           {
03443             /* Clear SPI slave underrun flag and discard transmit data */
03444             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03445             {
03446               __HAL_USART_CLEAR_UDRFLAG(husart);
03447               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03448             }
03449
03450             /* Rx process is completed, restore husart->State to Ready */
03451             husart->State = HAL_USART_STATE_READY;
03452             state = HAL_USART_STATE_READY;
03453
03454 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03455             /* Call registered Rx Complete Callback */
03456             husart->RxCpltCallback(husart);
03457 #else
03458             /* Call legacy weak Rx Complete Callback */
03459             HAL_USART_RxCpltCallback(husart);
03460 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03461           }
03462           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03463                    (txftie != USART_CR3_TXFTIE) &&
03464                    (txdatacount == 0U))
03465           {
03466             /* TxRx process is completed, restore husart->State to Ready */
03467             husart->State = HAL_USART_STATE_READY;
03468             state = HAL_USART_STATE_READY;
03469
03470 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03471             /* Call registered Tx Rx Complete Callback */
03472             husart->TxRxCpltCallback(husart);
03473 #else
03474             /* Call legacy weak Tx Rx Complete Callback */
03475             HAL_USART_TxRxCpltCallback(husart);
03476 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03477           }
03478           else
03479           {
03480             /* Nothing to do */
03481           }
03482         }
03483         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03484                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03485         {
03486           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03487           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03488         }
03489         else
03490         {
03491           /* Nothing to do */
03492         }
03493       }
03494     }
03495
03496     /* When remaining number of bytes to receive is less than the RX FIFO
03497     threshold, next incoming frames are processed as if FIFO mode was
03498     disabled (i.e. one interrupt per received frame).
03499     */
03500     rxdatacount = husart->RxXferCount;
03501     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03502     {
03503       /* Disable the USART RXFT interrupt*/
03504       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03505
03506       /* Update the RxISR function pointer */
03507       husart->RxISR = USART_RxISR_8BIT;
03508
03509       /* Enable the USART Data Register Not Empty interrupt */
03510       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03511
03512       if ((husart->TxXferCount == 0U) &&
03513           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03514           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03515       {
03516         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03517         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03518       }
03519     }
03520   }
03521   else
03522   {
03523     /* Clear RXNE interrupt flag */
03524     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03525   }
03526 }
03527
03528 /**
03529   * @brief  Simplex receive an amount of data in non-blocking mode.
03530   * @note   Function called under interruption only, once
03531   *         interruptions have been enabled by HAL_USART_Receive_IT().
03532   * @note   ISR function executed when FIFO mode is enabled and when the
03533   *         data word length is 9 bits long.
03534   * @param  husart USART handle
03535   * @retval None
03536   */
03537 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03538 {
03539   HAL_USART_StateTypeDef state = husart->State;
03540   uint16_t txdatacount;
03541   uint16_t rxdatacount;
03542   uint16_t *tmp;
03543   uint16_t uhMask = husart->Mask;
03544   uint16_t nb_rx_data;
03545   uint32_t txftie;
03546
03547   /* Check that a Tx process is ongoing */
03548   if ((state == HAL_USART_STATE_BUSY_RX) ||
03549       (state == HAL_USART_STATE_BUSY_TX_RX))
03550   {
03551     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03552     {
03553       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03554       {
03555         tmp = (uint16_t *) husart->pRxBuffPtr;
03556         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03557         husart->pRxBuffPtr += 2U;
03558         husart->RxXferCount--;
03559
03560         if (husart->RxXferCount == 0U)
03561         {
03562           /* Disable the USART Parity Error Interrupt */
03563           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03564
03565           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03566           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03567
03568           /* Clear RxISR function pointer */
03569           husart->RxISR = NULL;
03570
03571           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03572           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03573           txdatacount = husart->TxXferCount;
03574
03575           if (state == HAL_USART_STATE_BUSY_RX)
03576           {
03577             /* Clear SPI slave underrun flag and discard transmit data */
03578             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03579             {
03580               __HAL_USART_CLEAR_UDRFLAG(husart);
03581               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03582             }
03583
03584             /* Rx process is completed, restore husart->State to Ready */
03585             husart->State = HAL_USART_STATE_READY;
03586             state = HAL_USART_STATE_READY;
03587
03588 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03589             /* Call registered Rx Complete Callback */
03590             husart->RxCpltCallback(husart);
03591 #else
03592             /* Call legacy weak Rx Complete Callback */
03593             HAL_USART_RxCpltCallback(husart);
03594 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03595           }
03596           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03597                    (txftie != USART_CR3_TXFTIE) &&
03598                    (txdatacount == 0U))
03599           {
03600             /* TxRx process is completed, restore husart->State to Ready */
03601             husart->State = HAL_USART_STATE_READY;
03602             state = HAL_USART_STATE_READY;
03603
03604 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03605             /* Call registered Tx Rx Complete Callback */
03606             husart->TxRxCpltCallback(husart);
03607 #else
03608             /* Call legacy weak Tx Rx Complete Callback */
03609             HAL_USART_TxRxCpltCallback(husart);
03610 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03611           }
03612           else
03613           {
03614             /* Nothing to do */
03615           }
03616         }
03617         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03618                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03619         {
03620           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03621           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03622         }
03623         else
03624         {
03625           /* Nothing to do */
03626         }
03627       }
03628     }
03629
03630     /* When remaining number of bytes to receive is less than the RX FIFO
03631     threshold, next incoming frames are processed as if FIFO mode was
03632     disabled (i.e. one interrupt per received frame).
03633     */
03634     rxdatacount = husart->RxXferCount;
03635     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03636     {
03637       /* Disable the USART RXFT interrupt*/
03638       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03639
03640       /* Update the RxISR function pointer */
03641       husart->RxISR = USART_RxISR_16BIT;
03642
03643       /* Enable the USART Data Register Not Empty interrupt */
03644       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03645
03646       if ((husart->TxXferCount == 0U) &&
03647           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03648           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03649       {
03650         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03651         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03652       }
03653     }
03654   }
03655   else
03656   {
03657     /* Clear RXNE interrupt flag */
03658     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03659   }
03660 }
03661
03662 /**
03663   * @}
03664   */
03665
03666 #endif /* HAL_USART_MODULE_ENABLED */
03667 /**
03668   * @}
03669   */
03670
03671 /**
03672   * @}
03673   */
03674
03675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart.h Source File

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stm32h7xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_USART_H
00022 #define STM32H7xx_HAL_USART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup USART
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup USART_Exported_Types USART Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief USART Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00050                                            The baud rate is computed using the following formula:
00051                                               Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
00052                                               Baud Rate Register[3]    = 0
00053                                               Baud Rate Register[2:0]  =  (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
00054                                               where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
00055                                            @note  Oversampling by 8 is systematically applied to achieve high baud rates. */
00056
00057   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00058                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00059
00060   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00061                                            This parameter can be a value of @ref USART_Stop_Bits. */
00062
00063   uint32_t Parity;                   /*!< Specifies the parity mode.
00064                                            This parameter can be a value of @ref USART_Parity
00065                                            @note When parity is enabled, the computed parity is inserted
00066                                                  at the MSB position of the transmitted data (9th bit when
00067                                                  the word length is set to 9 data bits; 8th bit when the
00068                                                  word length is set to 8 data bits). */
00069
00070   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00071                                            This parameter can be a value of @ref USART_Mode. */
00072
00073   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00074                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00075
00076   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00077                                            This parameter can be a value of @ref USART_Clock_Phase. */
00078
00079   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00080                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00081                                            This parameter can be a value of @ref USART_Last_Bit. */
00082
00083   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00084                                            This parameter can be a value of @ref USART_ClockPrescaler. */
00085 } USART_InitTypeDef;
00086
00087 /**
00088   * @brief HAL USART State structures definition
00089   */
00090 typedef enum
00091 {
00092   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00093   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00094   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00095   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00096   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00097   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00098   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00099   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00100 } HAL_USART_StateTypeDef;
00101
00102 /**
00103   * @brief  USART clock sources definitions
00104   */
00105 typedef enum
00106 {
00107   USART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
00108   USART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
00109   USART_CLOCKSOURCE_PLL2       = 0x02U,    /*!< PLL2Q clock source         */
00110   USART_CLOCKSOURCE_PLL3       = 0x04U,    /*!< PLL3Q clock source         */
00111   USART_CLOCKSOURCE_HSI        = 0x08U,    /*!< HSI clock source           */
00112   USART_CLOCKSOURCE_CSI        = 0x10U,    /*!< CSI clock source           */
00113   USART_CLOCKSOURCE_LSE        = 0x20U,    /*!< LSE clock source           */
00114   USART_CLOCKSOURCE_UNDEFINED  = 0x40U     /*!< Undefined clock source     */
00115 } USART_ClockSourceTypeDef;
00116
00117 /**
00118   * @brief  USART handle Structure definition
00119   */
00120 typedef struct __USART_HandleTypeDef
00121 {
00122   USART_TypeDef                 *Instance;               /*!< USART registers base address        */
00123
00124   USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
00125
00126   uint8_t                       *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
00127
00128   uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
00129
00130   __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
00131
00132   uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
00133
00134   uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
00135
00136   __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
00137
00138   uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
00139
00140   uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */
00141
00142   uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
00143
00144   uint32_t                      SlaveMode;               /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
00145                                                               of @ref USARTEx_Slave_Mode */
00146
00147   uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00148                                                               of @ref USARTEx_FIFO_mode. */
00149
00150   void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
00151
00152   void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
00153
00154   DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
00155
00156   DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
00157
00158   HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
00159
00160   __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
00161
00162   __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
00163
00164 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00165   void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
00166   void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
00167   void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
00168   void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
00169   void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
00170   void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
00171   void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
00172   void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */
00173   void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */
00174
00175   void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
00176   void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
00177 #endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
00178
00179 } USART_HandleTypeDef;
00180
00181 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00182 /**
00183   * @brief  HAL USART Callback ID enumeration definition
00184   */
00185 typedef enum
00186 {
00187   HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
00188   HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
00189   HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
00190   HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
00191   HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
00192   HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
00193   HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
00194   HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */
00195   HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */
00196
00197   HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
00198   HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
00199
00200 } HAL_USART_CallbackIDTypeDef;
00201
00202 /**
00203   * @brief  HAL USART Callback pointer definition
00204   */
00205 typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
00206
00207 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported constants --------------------------------------------------------*/
00214 /** @defgroup USART_Exported_Constants USART Exported Constants
00215   * @{
00216   */
00217
00218 /** @defgroup USART_Error_Definition   USART Error Definition
00219   * @{
00220   */
00221 #define HAL_USART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                  */
00222 #define HAL_USART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error              */
00223 #define HAL_USART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error               */
00224 #define HAL_USART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error               */
00225 #define HAL_USART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error             */
00226 #define HAL_USART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error        */
00227 #define HAL_USART_ERROR_UDR              ((uint32_t)0x00000020U)    /*!< SPI slave underrun error  */
00228 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00229 #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error    */
00230 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00236   * @{
00237   */
00238 #define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
00239 #define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
00240 #define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
00241 #define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup USART_Parity    USART Parity
00247   * @{
00248   */
00249 #define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
00250 #define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
00251 #define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup USART_Mode   USART Mode
00257   * @{
00258   */
00259 #define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
00260 #define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
00261 #define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup USART_Over_Sampling USART Over Sampling
00267   * @{
00268   */
00269 #define USART_OVERSAMPLING_16               0x00000000U         /*!< Oversampling by 16 */
00270 #define USART_OVERSAMPLING_8                USART_CR1_OVER8     /*!< Oversampling by 8  */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup USART_Clock  USART Clock
00276   * @{
00277   */
00278 #define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
00279 #define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00285   * @{
00286   */
00287 #define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
00288 #define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup USART_Clock_Phase   USART Clock Phase
00294   * @{
00295   */
00296 #define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
00297 #define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup USART_Last_Bit  USART Last Bit
00303   * @{
00304   */
00305 #define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
00306 #define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup USART_ClockPrescaler  USART Clock Prescaler
00312   * @{
00313   */
00314 #define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00315 #define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00316 #define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00317 #define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00318 #define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00319 #define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00320 #define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00321 #define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00322 #define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00323 #define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00324 #define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00325 #define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup USART_Request_Parameters  USART Request Parameters
00332   * @{
00333   */
00334 #define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00335 #define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup USART_Flags      USART Flags
00341   *        Elements values convention: 0xXXXX
00342   *           - 0xXXXX  : Flag mask in the ISR register
00343   * @{
00344   */
00345 #define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */
00346 #define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */
00347 #define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */
00348 #define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */
00349 #define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
00350 #define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
00351 #define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
00352 #define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */
00353 #define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */
00354 #define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */
00355 #define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
00356 #define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */
00357 #define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */
00358 #define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
00359 #define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
00360 #define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
00361 #define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
00362 #define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00368   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00369   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00370   *           - XX  : Interrupt source register (2bits)
00371   *                 - 01: CR1 register
00372   *                 - 10: CR2 register
00373   *                 - 11: CR3 register
00374   *           - ZZZZ  : Flag position in the ISR register(4bits)
00375   * @{
00376   */
00377
00378 #define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
00379 #define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
00380 #define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */
00381 #define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
00382 #define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
00383 #define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */
00384 #define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
00385 #define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
00386 #define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
00387 #define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
00388 #define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
00389 #define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */
00390 #define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */
00391 #define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */
00392 #define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */
00393
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00399   * @{
00400   */
00401 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
00402 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
00403 #define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */
00404 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
00405 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
00406 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
00407 #define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */
00408 #define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00414   * @{
00415   */
00416 #define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
00417 #define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
00418 #define USART_CR_POS                              5U          /*!< USART control register position */
00419 #define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */
00420 #define USART_ISR_POS                             8U          /*!< USART ISR register position     */
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /* Exported macros -----------------------------------------------------------*/
00430 /** @defgroup USART_Exported_Macros USART Exported Macros
00431   * @{
00432   */
00433
00434 /** @brief Reset USART handle state.
00435   * @param  __HANDLE__ USART handle.
00436   * @retval None
00437   */
00438 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00439 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
00440                                                         (__HANDLE__)->State = HAL_USART_STATE_RESET; \
00441                                                         (__HANDLE__)->MspInitCallback = NULL;        \
00442                                                         (__HANDLE__)->MspDeInitCallback = NULL;      \
00443                                                       } while(0U)
00444 #else
00445 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00446 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00447
00448 /** @brief  Check whether the specified USART flag is set or not.
00449   * @param  __HANDLE__ specifies the USART Handle
00450   * @param  __FLAG__ specifies the flag to check.
00451   *        This parameter can be one of the following values:
00452   *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag
00453   *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag
00454   *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag
00455   *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag
00456   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00457   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00458   *            @arg @ref USART_FLAG_BUSY  Busy flag
00459   *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag
00460   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00461   *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
00462   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00463   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00464   *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
00465   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00466   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00467   *            @arg @ref USART_FLAG_NE    Noise Error flag
00468   *            @arg @ref USART_FLAG_FE    Framing Error flag
00469   *            @arg @ref USART_FLAG_PE    Parity Error flag
00470   * @retval The new state of __FLAG__ (TRUE or FALSE).
00471   */
00472 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00473
00474 /** @brief  Clear the specified USART pending flag.
00475   * @param  __HANDLE__ specifies the USART Handle.
00476   * @param  __FLAG__ specifies the flag to check.
00477   *          This parameter can be any combination of the following values:
00478   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00479   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00480   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00481   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00482   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00483   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00484   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00485   *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag
00486   * @retval None
00487   */
00488 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00489
00490 /** @brief  Clear the USART PE pending flag.
00491   * @param  __HANDLE__ specifies the USART Handle.
00492   * @retval None
00493   */
00494 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00495
00496 /** @brief  Clear the USART FE pending flag.
00497   * @param  __HANDLE__ specifies the USART Handle.
00498   * @retval None
00499   */
00500 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00501
00502 /** @brief  Clear the USART NE pending flag.
00503   * @param  __HANDLE__ specifies the USART Handle.
00504   * @retval None
00505   */
00506 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00507
00508 /** @brief  Clear the USART ORE pending flag.
00509   * @param  __HANDLE__ specifies the USART Handle.
00510   * @retval None
00511   */
00512 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00513
00514 /** @brief  Clear the USART IDLE pending flag.
00515   * @param  __HANDLE__ specifies the USART Handle.
00516   * @retval None
00517   */
00518 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00519
00520 /** @brief  Clear the USART TX FIFO empty clear flag.
00521   * @param  __HANDLE__ specifies the USART Handle.
00522   * @retval None
00523   */
00524 #define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
00525
00526 /** @brief  Clear SPI slave underrun error flag.
00527   * @param  __HANDLE__ specifies the USART Handle.
00528   * @retval None
00529   */
00530 #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
00531
00532 /** @brief  Enable the specified USART interrupt.
00533   * @param  __HANDLE__ specifies the USART Handle.
00534   * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
00535   *          This parameter can be one of the following values:
00536   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00537   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00538   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00539   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00540   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00541   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00542   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00543   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00544   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00545   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00546   *            @arg @ref USART_IT_PE    Parity Error interrupt
00547   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00548   * @retval None
00549   */
00550 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00551                                                             ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00552                                                             ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
00553
00554 /** @brief  Disable the specified USART interrupt.
00555   * @param  __HANDLE__ specifies the USART Handle.
00556   * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
00557   *          This parameter can be one of the following values:
00558   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00559   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00560   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00561   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00562   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00563   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00564   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00565   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00566   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00567   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00568   *            @arg @ref USART_IT_PE    Parity Error interrupt
00569   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00570   * @retval None
00571   */
00572 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00573                                                             ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00574                                                             ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
00575
00576
00577 /** @brief  Check whether the specified USART interrupt has occurred or not.
00578   * @param  __HANDLE__ specifies the USART Handle.
00579   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00580   *          This parameter can be one of the following values:
00581   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00582   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00583   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00584   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00585   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00586   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00587   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00588   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00589   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00590   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00591   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00592   *            @arg @ref USART_IT_NE    Noise Error interrupt
00593   *            @arg @ref USART_IT_FE    Framing Error interrupt
00594   *            @arg @ref USART_IT_PE    Parity Error interrupt
00595   * @retval The new state of __INTERRUPT__ (SET or RESET).
00596   */
00597 #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00598                                                          & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
00599
00600 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00601   * @param  __HANDLE__ specifies the USART Handle.
00602   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00603   *          This parameter can be one of the following values:
00604   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00605   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00606   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00607   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00608   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00609   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00610   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00611   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00612   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00613   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00614   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00615   *            @arg @ref USART_IT_NE    Noise Error interrupt
00616   *            @arg @ref USART_IT_FE    Framing Error interrupt
00617   *            @arg @ref USART_IT_PE    Parity Error interrupt
00618   * @retval The new state of __INTERRUPT__ (SET or RESET).
00619   */
00620 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
00621                                                                  (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
00622                                                                   (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != 0U) ? SET : RESET)
00623
00624
00625 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00626   * @param  __HANDLE__ specifies the USART Handle.
00627   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00628   *                       to clear the corresponding interrupt.
00629   *          This parameter can be one of the following values:
00630   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00631   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00632   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00633   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00634   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00635   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00636   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00637   * @retval None
00638   */
00639 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00640
00641 /** @brief  Set a specific USART request flag.
00642   * @param  __HANDLE__ specifies the USART Handle.
00643   * @param  __REQ__ specifies the request flag to set.
00644   *          This parameter can be one of the following values:
00645   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00646   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00647   *
00648   * @retval None
00649   */
00650 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00651
00652 /** @brief  Enable the USART one bit sample method.
00653   * @param  __HANDLE__ specifies the USART Handle.
00654   * @retval None
00655   */
00656 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00657
00658 /** @brief  Disable the USART one bit sample method.
00659   * @param  __HANDLE__ specifies the USART Handle.
00660   * @retval None
00661   */
00662 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
00663
00664 /** @brief  Enable USART.
00665   * @param  __HANDLE__ specifies the USART Handle.
00666   * @retval None
00667   */
00668 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
00669
00670 /** @brief  Disable USART.
00671   * @param  __HANDLE__ specifies the USART Handle.
00672   * @retval None
00673   */
00674 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
00675
00676 /**
00677   * @}
00678   */
00679
00680 /* Private macros --------------------------------------------------------*/
00681 /** @defgroup USART_Private_Macros   USART Private Macros
00682   * @{
00683   */
00684
00685 /** @brief  Get USART clock division factor from clock prescaler value.
00686   * @param  __CLOCKPRESCALER__ USART prescaler value.
00687   * @retval USART clock division factor
00688   */
00689 #define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
00690   (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
00691    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
00692    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
00693    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
00694    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
00695    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
00696    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
00697    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
00698    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
00699    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
00700    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
00701    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
00702
00703 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
00704   * @param  __PCLK__ USART clock.
00705   * @param  __BAUD__ Baud rate set by the user.
00706   * @param  __CLOCKPRESCALER__ UART prescaler value.
00707   * @retval Division result
00708   */
00709 #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
00710                                                                         + ((__BAUD__)/2U)) / (__BAUD__))
00711
00712 /** @brief  Report the USART clock source.
00713   * @param  __HANDLE__ specifies the USART Handle.
00714   * @param  __CLOCKSOURCE__ output variable.
00715   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00716   */
00717 #if defined(UART9) && defined(USART10)
00718 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00719   do {                                                         \
00720     if((__HANDLE__)->Instance == USART1)                       \
00721     {                                                          \
00722       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00723       {                                                        \
00724         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00725           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00726           break;                                               \
00727         case RCC_USART1CLKSOURCE_PLL2:                         \
00728           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00729           break;                                               \
00730         case RCC_USART1CLKSOURCE_PLL3:                         \
00731           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00732           break;                                               \
00733         case RCC_USART1CLKSOURCE_HSI:                          \
00734           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00735           break;                                               \
00736         case RCC_USART1CLKSOURCE_CSI:                          \
00737           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00738           break;                                               \
00739         case RCC_USART1CLKSOURCE_LSE:                          \
00740           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00741           break;                                               \
00742         default:                                               \
00743           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00744           break;                                               \
00745       }                                                        \
00746     }                                                          \
00747     else if((__HANDLE__)->Instance == USART2)                  \
00748     {                                                          \
00749       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00750       {                                                        \
00751         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
00752           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00753           break;                                               \
00754         case RCC_USART2CLKSOURCE_PLL2:                         \
00755           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00756           break;                                               \
00757         case RCC_USART2CLKSOURCE_PLL3:                         \
00758           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00759           break;                                               \
00760         case RCC_USART2CLKSOURCE_HSI:                          \
00761           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00762           break;                                               \
00763         case RCC_USART2CLKSOURCE_CSI:                          \
00764           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00765           break;                                               \
00766         case RCC_USART2CLKSOURCE_LSE:                          \
00767           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00768           break;                                               \
00769         default:                                               \
00770           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00771           break;                                               \
00772       }                                                        \
00773     }                                                          \
00774     else if((__HANDLE__)->Instance == USART3)                  \
00775     {                                                          \
00776       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00777       {                                                        \
00778         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
00779           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00780           break;                                               \
00781         case RCC_USART3CLKSOURCE_PLL2:                         \
00782           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00783           break;                                               \
00784         case RCC_USART3CLKSOURCE_PLL3:                         \
00785           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00786           break;                                               \
00787         case RCC_USART3CLKSOURCE_HSI:                          \
00788           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00789           break;                                               \
00790         case RCC_USART3CLKSOURCE_CSI:                          \
00791           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00792           break;                                               \
00793         case RCC_USART3CLKSOURCE_LSE:                          \
00794           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00795           break;                                               \
00796         default:                                               \
00797           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00798           break;                                               \
00799       }                                                        \
00800     }                                                          \
00801     else if((__HANDLE__)->Instance == USART6)                  \
00802     {                                                          \
00803       switch(__HAL_RCC_GET_USART6_SOURCE())                    \
00804       {                                                        \
00805         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
00806           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00807           break;                                               \
00808         case RCC_USART6CLKSOURCE_PLL2:                         \
00809           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00810           break;                                               \
00811         case RCC_USART6CLKSOURCE_PLL3:                         \
00812           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00813           break;                                               \
00814         case RCC_USART6CLKSOURCE_HSI:                          \
00815           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00816           break;                                               \
00817         case RCC_USART6CLKSOURCE_CSI:                          \
00818           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00819           break;                                               \
00820         case RCC_USART6CLKSOURCE_LSE:                          \
00821           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00822           break;                                               \
00823         default:                                               \
00824           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00825           break;                                               \
00826       }                                                        \
00827     }                                                          \
00828     else if((__HANDLE__)->Instance == USART10)                 \
00829     {                                                          \
00830       switch(__HAL_RCC_GET_USART10_SOURCE())                   \
00831       {                                                        \
00832         case RCC_USART10CLKSOURCE_D2PCLK2:                     \
00833           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00834           break;                                               \
00835         case RCC_USART10CLKSOURCE_PLL2:                        \
00836           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00837           break;                                               \
00838         case RCC_USART10CLKSOURCE_PLL3:                        \
00839           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00840           break;                                               \
00841         case RCC_USART10CLKSOURCE_HSI:                         \
00842           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00843           break;                                               \
00844         case RCC_USART10CLKSOURCE_CSI:                         \
00845           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00846           break;                                               \
00847         case RCC_USART10CLKSOURCE_LSE:                         \
00848           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00849           break;                                               \
00850         default:                                               \
00851           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00852           break;                                               \
00853       }                                                        \
00854     }                                                          \
00855     else                                                       \
00856     {                                                          \
00857       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00858     }                                                          \
00859   } while(0U)
00860 #else
00861 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00862   do {                                                         \
00863     if((__HANDLE__)->Instance == USART1)                       \
00864     {                                                          \
00865       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00866       {                                                        \
00867         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00868           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00869           break;                                               \
00870         case RCC_USART1CLKSOURCE_PLL2:                         \
00871           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00872           break;                                               \
00873         case RCC_USART1CLKSOURCE_PLL3:                         \
00874           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00875           break;                                               \
00876         case RCC_USART1CLKSOURCE_HSI:                          \
00877           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00878           break;                                               \
00879         case RCC_USART1CLKSOURCE_CSI:                          \
00880           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00881           break;                                               \
00882         case RCC_USART1CLKSOURCE_LSE:                          \
00883           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00884           break;                                               \
00885         default:                                               \
00886           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00887           break;                                               \
00888       }                                                        \
00889     }                                                          \
00890     else if((__HANDLE__)->Instance == USART2)                  \
00891     {                                                          \
00892       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00893       {                                                        \
00894         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
00895           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00896           break;                                               \
00897         case RCC_USART2CLKSOURCE_PLL2:                         \
00898           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00899           break;                                               \
00900         case RCC_USART2CLKSOURCE_PLL3:                         \
00901           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00902           break;                                               \
00903         case RCC_USART2CLKSOURCE_HSI:                          \
00904           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00905           break;                                               \
00906         case RCC_USART2CLKSOURCE_CSI:                          \
00907           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00908           break;                                               \
00909         case RCC_USART2CLKSOURCE_LSE:                          \
00910           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00911           break;                                               \
00912         default:                                               \
00913           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00914           break;                                               \
00915       }                                                        \
00916     }                                                          \
00917     else if((__HANDLE__)->Instance == USART3)                  \
00918     {                                                          \
00919       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00920       {                                                        \
00921         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
00922           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00923           break;                                               \
00924         case RCC_USART3CLKSOURCE_PLL2:                         \
00925           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00926           break;                                               \
00927         case RCC_USART3CLKSOURCE_PLL3:                         \
00928           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00929           break;                                               \
00930         case RCC_USART3CLKSOURCE_HSI:                          \
00931           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00932           break;                                               \
00933         case RCC_USART3CLKSOURCE_CSI:                          \
00934           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00935           break;                                               \
00936         case RCC_USART3CLKSOURCE_LSE:                          \
00937           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00938           break;                                               \
00939         default:                                               \
00940           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00941           break;                                               \
00942       }                                                        \
00943     }                                                          \
00944     else if((__HANDLE__)->Instance == USART6)                  \
00945     {                                                          \
00946       switch(__HAL_RCC_GET_USART6_SOURCE())                    \
00947       {                                                        \
00948         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
00949           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00950           break;                                               \
00951         case RCC_USART6CLKSOURCE_PLL2:                         \
00952           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00953           break;                                               \
00954         case RCC_USART6CLKSOURCE_PLL3:                         \
00955           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00956           break;                                               \
00957         case RCC_USART6CLKSOURCE_HSI:                          \
00958           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00959           break;                                               \
00960         case RCC_USART6CLKSOURCE_CSI:                          \
00961           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00962           break;                                               \
00963         case RCC_USART6CLKSOURCE_LSE:                          \
00964           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00965           break;                                               \
00966         default:                                               \
00967           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00968           break;                                               \
00969       }                                                        \
00970     }                                                          \
00971     else                                                       \
00972     {                                                          \
00973       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00974     }                                                          \
00975   } while(0U)
00976 #endif  /* UART9 && USART10 */
00977
00978 /** @brief  Check USART Baud rate.
00979   * @param  __BAUDRATE__ Baudrate specified by the user.
00980   *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
00981   *         divided by the smallest oversampling used on the USART (i.e. 8)
00982   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
00983 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
00984
00985 /**
00986   * @brief Ensure that USART frame number of stop bits is valid.
00987   * @param __STOPBITS__ USART frame number of stop bits.
00988   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00989   */
00990 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00991                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00992                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00993                                          ((__STOPBITS__) == USART_STOPBITS_2))
00994
00995 /**
00996   * @brief Ensure that USART frame parity is valid.
00997   * @param __PARITY__ USART frame parity.
00998   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00999   */
01000 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
01001                                      ((__PARITY__) == USART_PARITY_EVEN) || \
01002                                      ((__PARITY__) == USART_PARITY_ODD))
01003
01004 /**
01005   * @brief Ensure that USART communication mode is valid.
01006   * @param __MODE__ USART communication mode.
01007   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01008   */
01009 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
01010
01011 /**
01012   * @brief Ensure that USART oversampling is valid.
01013   * @param __SAMPLING__ USART oversampling.
01014   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01015   */
01016 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
01017                                              ((__SAMPLING__) == USART_OVERSAMPLING_8))
01018
01019 /**
01020   * @brief Ensure that USART clock state is valid.
01021   * @param __CLOCK__ USART clock state.
01022   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
01023   */
01024 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
01025                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
01026
01027 /**
01028   * @brief Ensure that USART frame polarity is valid.
01029   * @param __CPOL__ USART frame polarity.
01030   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
01031   */
01032 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
01033
01034 /**
01035   * @brief Ensure that USART frame phase is valid.
01036   * @param __CPHA__ USART frame phase.
01037   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
01038   */
01039 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
01040
01041 /**
01042   * @brief Ensure that USART frame last bit clock pulse setting is valid.
01043   * @param __LASTBIT__ USART frame last bit clock pulse setting.
01044   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
01045   */
01046 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
01047                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
01048
01049 /**
01050   * @brief Ensure that USART request parameter is valid.
01051   * @param __PARAM__ USART request parameter.
01052   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01053   */
01054 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
01055                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
01056
01057 /**
01058   * @brief Ensure that USART Prescaler is valid.
01059   * @param __CLOCKPRESCALER__ USART Prescaler value.
01060   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01061   */
01062 #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
01063                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
01064                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
01065                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
01066                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
01067                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
01068                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
01069                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
01070                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
01071                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
01072                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
01073                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
01074
01075 /**
01076   * @}
01077   */
01078
01079 /* Include USART HAL Extended module */
01080 #include "stm32h7xx_hal_usart_ex.h"
01081
01082 /* Exported functions --------------------------------------------------------*/
01083 /** @addtogroup USART_Exported_Functions USART Exported Functions
01084   * @{
01085   */
01086
01087 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
01088   * @{
01089   */
01090
01091 /* Initialization and de-initialization functions  ****************************/
01092 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
01093 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
01094 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
01095 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
01096
01097 /* Callbacks Register/UnRegister functions  ***********************************/
01098 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
01099 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
01100                                              pUSART_CallbackTypeDef pCallback);
01101 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
01102 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
01103
01104 /**
01105   * @}
01106   */
01107
01108 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
01109   * @{
01110   */
01111
01112 /* IO operation functions *****************************************************/
01113 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
01114 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
01115 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
01116                                             uint16_t Size, uint32_t Timeout);
01117 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
01118 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
01119 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
01120                                                uint16_t Size);
01121 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
01122 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
01123 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
01124                                                 uint16_t Size);
01125 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
01126 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
01127 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
01128 /* Transfer Abort functions */
01129 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
01130 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
01131
01132 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
01133 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
01134 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
01135 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
01136 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
01137 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
01138 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
01139 void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
01140
01141 /**
01142   * @}
01143   */
01144
01145 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
01146   * @{
01147   */
01148
01149 /* Peripheral State and Error functions ***************************************/
01150 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
01151 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
01152
01153 /**
01154   * @}
01155   */
01156
01157 /**
01158   * @}
01159   */
01160
01161 /**
01162   * @}
01163   */
01164
01165 /**
01166   * @}
01167   */
01168
01169 #ifdef __cplusplus
01170 }
01171 #endif
01172
01173 #endif /* STM32H7xx_HAL_USART_H */
01174
01175 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart_ex.c Source File

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stm32h7xx_hal_usart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended USART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
00008   *           + Peripheral Control functions
00009   *
00010   *
00011   @verbatim
00012   ==============================================================================
00013                ##### USART peripheral extended features  #####
00014   ==============================================================================
00015
00016     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00017
00018         -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
00019             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00020             configured prior starting RX/TX transfers.
00021
00022     (#) Slave mode enabling/disabling and NSS pin configuration.
00023
00024         -@- When USART operates in Slave mode, Slave mode must be enabled prior
00025             starting RX/TX transfers.
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00032   * All rights reserved.</center></h2>
00033   *
00034   * This software component is licensed by ST under BSD 3-Clause license,
00035   * the "License"; You may not use this file except in compliance with the
00036   * License. You may obtain a copy of the License at:
00037   *                        opensource.org/licenses/BSD-3-Clause
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup USARTEx USARTEx
00050   * @brief USART Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_USART_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /** @defgroup USARTEx_Private_Constants USARTEx Private Constants
00058   * @{
00059   */
00060 /* UART RX FIFO depth */
00061 #define RX_FIFO_DEPTH 8U
00062
00063 /* UART TX FIFO depth */
00064 #define TX_FIFO_DEPTH 8U
00065 /**
00066   * @}
00067   */
00068
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /** @defgroup USARTEx_Private_Functions USARTEx Private Functions
00074   * @{
00075   */
00076 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported functions --------------------------------------------------------*/
00082
00083 /** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
00088   * @brief Extended USART Transmit/Receive functions
00089   *
00090 @verbatim
00091  ===============================================================================
00092                       ##### IO operation functions #####
00093  ===============================================================================
00094     This subsection provides a set of FIFO mode related callback functions.
00095
00096     (#) TX/RX Fifos Callbacks:
00097         (+) HAL_USARTEx_RxFifoFullCallback()
00098         (+) HAL_USARTEx_TxFifoEmptyCallback()
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  USART RX Fifo full callback.
00106   * @param  husart USART handle.
00107   * @retval None
00108   */
00109 __weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
00110 {
00111   /* Prevent unused argument(s) compilation warning */
00112   UNUSED(husart);
00113
00114   /* NOTE : This function should not be modified, when the callback is needed,
00115             the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
00116    */
00117 }
00118
00119 /**
00120   * @brief  USART TX Fifo empty callback.
00121   * @param  husart USART handle.
00122   * @retval None
00123   */
00124 __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
00125 {
00126   /* Prevent unused argument(s) compilation warning */
00127   UNUSED(husart);
00128
00129   /* NOTE : This function should not be modified, when the callback is needed,
00130             the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
00131    */
00132 }
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
00139   * @brief    Extended Peripheral Control functions
00140   *
00141 @verbatim
00142  ===============================================================================
00143                       ##### Peripheral Control functions #####
00144  ===============================================================================
00145     [..] This section provides the following functions:
00146      (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
00147      (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
00148      (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
00149      (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
00150      (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
00151      (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00152      (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00153
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Enable the SPI slave mode.
00161   * @note When the USART operates in SPI slave mode, it handles data flow using
00162   *       the serial interface clock derived from the external SCLK signal
00163   *       provided by the external master SPI device.
00164   * @note In SPI slave mode, the USART must be enabled before starting the master
00165   *       communications (or between frames while the clock is stable). Otherwise,
00166   *       if the USART slave is enabled while the master is in the middle of a
00167   *       frame, it will become desynchronized with the master.
00168   * @note The data register of the slave needs to be ready before the first edge
00169   *       of the communication clock or before the end of the ongoing communication,
00170   *       otherwise the SPI slave will transmit zeros.
00171   * @param husart      USART handle.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
00175 {
00176   uint32_t tmpcr1;
00177
00178   /* Check parameters */
00179   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00180
00181   /* Process Locked */
00182   __HAL_LOCK(husart);
00183
00184   husart->State = HAL_USART_STATE_BUSY;
00185
00186   /* Save actual USART configuration */
00187   tmpcr1 = READ_REG(husart->Instance->CR1);
00188
00189   /* Disable USART */
00190   __HAL_USART_DISABLE(husart);
00191
00192   /* In SPI slave mode mode, the following bits must be kept cleared:
00193   - LINEN and CLKEN bit in the USART_CR2 register
00194   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00195   CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00196   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00197
00198   /* Enable SPI slave mode */
00199   SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00200
00201   /* Restore USART configuration */
00202   WRITE_REG(husart->Instance->CR1, tmpcr1);
00203
00204   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00205
00206   husart->State = HAL_USART_STATE_READY;
00207
00208   /* Enable USART */
00209   __HAL_USART_ENABLE(husart);
00210
00211   /* Process Unlocked */
00212   __HAL_UNLOCK(husart);
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Disable the SPI slave mode.
00219   * @param husart      USART handle.
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
00223 {
00224   uint32_t tmpcr1;
00225
00226   /* Check parameters */
00227   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00228
00229   /* Process Locked */
00230   __HAL_LOCK(husart);
00231
00232   husart->State = HAL_USART_STATE_BUSY;
00233
00234   /* Save actual USART configuration */
00235   tmpcr1 = READ_REG(husart->Instance->CR1);
00236
00237   /* Disable USART */
00238   __HAL_USART_DISABLE(husart);
00239
00240   /* Disable SPI slave mode */
00241   CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00242
00243   /* Restore USART configuration */
00244   WRITE_REG(husart->Instance->CR1, tmpcr1);
00245
00246   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00247
00248   husart->State = HAL_USART_STATE_READY;
00249
00250   /* Process Unlocked */
00251   __HAL_UNLOCK(husart);
00252
00253   return HAL_OK;
00254 }
00255
00256 /**
00257   * @brief  Configure the Slave Select input pin (NSS).
00258   * @note Software NSS management: SPI slave will always be selected and NSS
00259   *       input pin will be ignored.
00260   * @note Hardware NSS management: the SPI slave selection depends on NSS
00261   *       input pin. The slave is selected when NSS is low and deselected when
00262   *       NSS is high.
00263   * @param husart      USART handle.
00264   * @param NSSConfig   NSS configuration.
00265   *          This parameter can be one of the following values:
00266   *            @arg @ref USART_NSS_HARD
00267   *            @arg @ref USART_NSS_SOFT
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
00271 {
00272   uint32_t tmpcr1;
00273
00274   /* Check parameters */
00275   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00276   assert_param(IS_USART_NSS(NSSConfig));
00277
00278   /* Process Locked */
00279   __HAL_LOCK(husart);
00280
00281   husart->State = HAL_USART_STATE_BUSY;
00282
00283   /* Save actual USART configuration */
00284   tmpcr1 = READ_REG(husart->Instance->CR1);
00285
00286   /* Disable USART */
00287   __HAL_USART_DISABLE(husart);
00288
00289   /* Program DIS_NSS bit in the USART_CR2 register */
00290   MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
00291
00292   /* Restore USART configuration */
00293   WRITE_REG(husart->Instance->CR1, tmpcr1);
00294
00295   husart->State = HAL_USART_STATE_READY;
00296
00297   /* Process Unlocked */
00298   __HAL_UNLOCK(husart);
00299
00300   return HAL_OK;
00301 }
00302
00303 /**
00304   * @brief  Enable the FIFO mode.
00305   * @param husart      USART handle.
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
00309 {
00310   uint32_t tmpcr1;
00311
00312   /* Check parameters */
00313   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00314
00315   /* Process Locked */
00316   __HAL_LOCK(husart);
00317
00318   husart->State = HAL_USART_STATE_BUSY;
00319
00320   /* Save actual USART configuration */
00321   tmpcr1 = READ_REG(husart->Instance->CR1);
00322
00323   /* Disable USART */
00324   __HAL_USART_DISABLE(husart);
00325
00326   /* Enable FIFO mode */
00327   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00328   husart->FifoMode = USART_FIFOMODE_ENABLE;
00329
00330   /* Restore USART configuration */
00331   WRITE_REG(husart->Instance->CR1, tmpcr1);
00332
00333   /* Determine the number of data to process during RX/TX ISR execution */
00334   USARTEx_SetNbDataToProcess(husart);
00335
00336   husart->State = HAL_USART_STATE_READY;
00337
00338   /* Process Unlocked */
00339   __HAL_UNLOCK(husart);
00340
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Disable the FIFO mode.
00346   * @param husart      USART handle.
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
00350 {
00351   uint32_t tmpcr1;
00352
00353   /* Check parameters */
00354   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00355
00356   /* Process Locked */
00357   __HAL_LOCK(husart);
00358
00359   husart->State = HAL_USART_STATE_BUSY;
00360
00361   /* Save actual USART configuration */
00362   tmpcr1 = READ_REG(husart->Instance->CR1);
00363
00364   /* Disable USART */
00365   __HAL_USART_DISABLE(husart);
00366
00367   /* Enable FIFO mode */
00368   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00369   husart->FifoMode = USART_FIFOMODE_DISABLE;
00370
00371   /* Restore USART configuration */
00372   WRITE_REG(husart->Instance->CR1, tmpcr1);
00373
00374   husart->State = HAL_USART_STATE_READY;
00375
00376   /* Process Unlocked */
00377   __HAL_UNLOCK(husart);
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  Set the TXFIFO threshold.
00384   * @param husart      USART handle.
00385   * @param Threshold  TX FIFO threshold value
00386   *          This parameter can be one of the following values:
00387   *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
00388   *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
00389   *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
00390   *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
00391   *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
00392   *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00396 {
00397   uint32_t tmpcr1;
00398
00399   /* Check parameters */
00400   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00401   assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
00402
00403   /* Process Locked */
00404   __HAL_LOCK(husart);
00405
00406   husart->State = HAL_USART_STATE_BUSY;
00407
00408   /* Save actual USART configuration */
00409   tmpcr1 = READ_REG(husart->Instance->CR1);
00410
00411   /* Disable USART */
00412   __HAL_USART_DISABLE(husart);
00413
00414   /* Update TX threshold configuration */
00415   MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00416
00417   /* Determine the number of data to process during RX/TX ISR execution */
00418   USARTEx_SetNbDataToProcess(husart);
00419
00420   /* Restore USART configuration */
00421   WRITE_REG(husart->Instance->CR1, tmpcr1);
00422
00423   husart->State = HAL_USART_STATE_READY;
00424
00425   /* Process Unlocked */
00426   __HAL_UNLOCK(husart);
00427
00428   return HAL_OK;
00429 }
00430
00431 /**
00432   * @brief  Set the RXFIFO threshold.
00433   * @param husart      USART handle.
00434   * @param Threshold  RX FIFO threshold value
00435   *          This parameter can be one of the following values:
00436   *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
00437   *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
00438   *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
00439   *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
00440   *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
00441   *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00445 {
00446   uint32_t tmpcr1;
00447
00448   /* Check the parameters */
00449   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00450   assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
00451
00452   /* Process Locked */
00453   __HAL_LOCK(husart);
00454
00455   husart->State = HAL_USART_STATE_BUSY;
00456
00457   /* Save actual USART configuration */
00458   tmpcr1 = READ_REG(husart->Instance->CR1);
00459
00460   /* Disable USART */
00461   __HAL_USART_DISABLE(husart);
00462
00463   /* Update RX threshold configuration */
00464   MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00465
00466   /* Determine the number of data to process during RX/TX ISR execution */
00467   USARTEx_SetNbDataToProcess(husart);
00468
00469   /* Restore USART configuration */
00470   WRITE_REG(husart->Instance->CR1, tmpcr1);
00471
00472   husart->State = HAL_USART_STATE_READY;
00473
00474   /* Process Unlocked */
00475   __HAL_UNLOCK(husart);
00476
00477   return HAL_OK;
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @addtogroup USARTEx_Private_Functions
00489   * @{
00490   */
00491
00492 /**
00493   * @brief Calculate the number of data to process in RX/TX ISR.
00494   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00495   *       the USART configuration registers.
00496   * @param husart USART handle.
00497   * @retval None
00498   */
00499 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
00500 {
00501   uint8_t rx_fifo_depth;
00502   uint8_t tx_fifo_depth;
00503   uint8_t rx_fifo_threshold;
00504   uint8_t tx_fifo_threshold;
00505   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00506   uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00507   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00508
00509   if (husart->FifoMode == USART_FIFOMODE_DISABLE)
00510   {
00511     husart->NbTxDataToProcess = 1U;
00512     husart->NbRxDataToProcess = 1U;
00513   }
00514   else
00515   {
00516     rx_fifo_depth = RX_FIFO_DEPTH;
00517     tx_fifo_depth = TX_FIFO_DEPTH;
00518     rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
00519     tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
00520     husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00521     husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00522   }
00523 }
00524 /**
00525   * @}
00526   */
00527
00528 #endif /* HAL_USART_MODULE_ENABLED */
00529
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_usart_ex.h Source File

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stm32h7xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_USART_EX_H
00022 #define STM32H7xx_HAL_USART_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup USARTEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00046   * @{
00047   */
00048 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
00049 #define USART_WORDLENGTH_8B                  0x00000000U                /*!< 8-bit long USART frame */
00050 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
00056   * @{
00057   */
00058 #define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */
00059 #define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */
00060 /**
00061   * @}
00062   */
00063
00064
00065 /** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
00066   * @brief    USART SLAVE mode
00067   * @{
00068   */
00069 #define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */
00070 #define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode
00076   * @brief    USART FIFO  mode
00077   * @{
00078   */
00079 #define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00080 #define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
00086   * @brief    USART TXFIFO level
00087   * @{
00088   */
00089 #define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00090 #define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00091 #define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00092 #define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00093 #define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00094 #define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
00100   * @brief    USART RXFIFO level
00101   * @{
00102   */
00103 #define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00104 #define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00105 #define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00106 #define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00107 #define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00108 #define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros ------------------------------------------------------------*/
00118 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00119   * @{
00120   */
00121
00122 /** @brief  Compute the USART mask to apply to retrieve the received data
00123   *         according to the word length and to the parity bits activation.
00124   * @note   If PCE = 1, the parity bit is not included in the data extracted
00125   *         by the reception API().
00126   *         This masking operation is not carried out in the case of
00127   *         DMA transfers.
00128   * @param  __HANDLE__ specifies the USART Handle.
00129   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00130   */
00131 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00132   do {                                                                \
00133     if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \
00134     {                                                                 \
00135       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00136       {                                                               \
00137         (__HANDLE__)->Mask = 0x01FFU;                                 \
00138       }                                                               \
00139       else                                                            \
00140       {                                                               \
00141         (__HANDLE__)->Mask = 0x00FFU;                                 \
00142       }                                                               \
00143     }                                                                 \
00144     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \
00145     {                                                                 \
00146       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00147       {                                                               \
00148         (__HANDLE__)->Mask = 0x00FFU;                                 \
00149       }                                                               \
00150       else                                                            \
00151       {                                                               \
00152         (__HANDLE__)->Mask = 0x007FU;                                 \
00153       }                                                               \
00154     }                                                                 \
00155     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \
00156     {                                                                 \
00157       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00158       {                                                               \
00159         (__HANDLE__)->Mask = 0x007FU;                                 \
00160       }                                                               \
00161       else                                                            \
00162       {                                                               \
00163         (__HANDLE__)->Mask = 0x003FU;                                 \
00164       }                                                               \
00165     }                                                                 \
00166     else                                                              \
00167     {                                                                 \
00168       (__HANDLE__)->Mask = 0x0000U;                                   \
00169     }                                                                 \
00170   } while(0U)
00171
00172
00173 /**
00174   * @brief Ensure that USART frame length is valid.
00175   * @param __LENGTH__ USART frame length.
00176   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00177   */
00178 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00179                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00180                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00181
00182 /**
00183   * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
00184   * @param __NSS__ USART Negative Slave Select pin management.
00185   * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
00186   */
00187 #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
00188                                ((__NSS__) == USART_NSS_SOFT))
00189
00190 /**
00191   * @brief Ensure that USART Slave Mode is valid.
00192   * @param __STATE__ USART Slave Mode.
00193   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00194   */
00195 #define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
00196                                          ((__STATE__) == USART_SLAVEMODE_ENABLE))
00197
00198 /**
00199   * @brief Ensure that USART FIFO mode is valid.
00200   * @param __STATE__ USART FIFO mode.
00201   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00202   */
00203 #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
00204                                              ((__STATE__) == USART_FIFOMODE_ENABLE))
00205
00206 /**
00207   * @brief Ensure that USART TXFIFO threshold level is valid.
00208   * @param __THRESHOLD__ USART TXFIFO threshold level.
00209   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00210   */
00211 #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
00212                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
00213                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
00214                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
00215                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
00216                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
00217
00218 /**
00219   * @brief Ensure that USART RXFIFO threshold level is valid.
00220   * @param __THRESHOLD__ USART RXFIFO threshold level.
00221   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00222   */
00223 #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
00224                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
00225                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
00226                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
00227                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
00228                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
00229 /**
00230   * @}
00231   */
00232
00233 /* Exported functions --------------------------------------------------------*/
00234 /** @addtogroup USARTEx_Exported_Functions
00235   * @{
00236   */
00237
00238 /** @addtogroup USARTEx_Exported_Functions_Group1
00239   * @{
00240   */
00241
00242 /* IO operation functions *****************************************************/
00243 void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
00244 void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @addtogroup USARTEx_Exported_Functions_Group2
00251   * @{
00252   */
00253
00254 /* Peripheral Control functions ***********************************************/
00255 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
00256 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
00257 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
00258 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
00259 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
00260 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00261 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #ifdef __cplusplus
00280 }
00281 #endif
00282
00283 #endif /* STM32H7xx_HAL_USART_EX_H */
00284
00285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_wwdg.c Source File

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stm32h7xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @brief   WWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Window Watchdog (WWDG) peripheral:
00008   *           + Initialization and Configuration functions
00009   *           + IO operation functions
00010   @verbatim
00011   ==============================================================================
00012                       ##### WWDG Specific features #####
00013   ==============================================================================
00014   [..]
00015     Once enabled the WWDG generates a system reset on expiry of a programmed
00016     time period, unless the program refreshes the counter (T[6;0] downcounter)
00017     before reaching 0x3F value (i.e. a reset is generated when the counter
00018     value rolls down from 0x40 to 0x3F).
00019
00020     (+) An MCU reset is also generated if the counter value is refreshed
00021         before the counter has reached the refresh window value. This
00022         implies that the counter must be refreshed in a limited window.
00023     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00024     (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
00025         reset occurs.
00026     (+) The WWDG counter input clock is derived from the APB clock divided
00027         by a programmable prescaler.
00028     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00029     (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
00030         where T[5;0] are the lowest 6 bits of Counter.
00031     (+) WWDG Counter refresh is allowed between the following limits :
00032         (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
00033         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
00034     (+) Typical values:
00035         (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
00036              max timeout before reset: approximately 73.14µs
00037         (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
00038              max timeout before reset: approximately 599.18ms
00039
00040   ==============================================================================
00041                      ##### How to use this driver #####
00042   ==============================================================================
00043
00044     *** Common driver usage ***
00045     ===========================
00046
00047   [..]
00048     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00049     (+) Set the WWDG prescaler, refresh window and counter value
00050         using HAL_WWDG_Init() function.
00051     (+) Start the WWDG using HAL_WWDG_Start() function.
00052         When the WWDG is enabled the counter value should be configured to
00053         a value greater than 0x40 to prevent generating an immediate reset.
00054     (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
00055         generated when the counter reaches 0x40, and then start the WWDG using
00056         HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
00057         add his own code by customization of callback HAL_WWDG_WakeupCallback.
00058         Once enabled, EWI interrupt cannot be disabled except by a system reset.
00059     (+) Then the application program must refresh the WWDG counter at regular
00060         intervals during normal operation to prevent an MCU reset, using
00061         HAL_WWDG_Refresh() function. This operation must occur only when
00062         the counter is lower than the refresh window value already programmed.
00063
00064     *** Callback registration ***
00065     =============================
00066
00067   [..]
00068     The compilation define  USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
00069     the user to configure dynamically the driver callbacks. Use Functions
00070     @ref HAL_WWDG_RegisterCallback() to register a user callback.
00071
00072     (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
00073         callbacks:
00074         (++) EwiCallback : callback for Early WakeUp Interrupt.
00075         (++) MspInitCallback : WWDG MspInit.
00076     This function takes as parameters the HAL peripheral handle, the Callback ID
00077     and a pointer to the user callback function.
00078
00079     (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
00080     the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
00081     takes as parameters the HAL peripheral handle and the Callback ID.
00082     This function allows to reset following callbacks:
00083         (++) EwiCallback : callback for  Early WakeUp Interrupt.
00084         (++) MspInitCallback : WWDG MspInit.
00085
00086     [..]
00087     When calling @ref HAL_WWDG_Init function, callbacks are reset to the
00088     corresponding legacy weak (surcharged) functions:
00089     @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
00090     not been registered before.
00091
00092     [..]
00093     When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
00094     not defined, the callback registering feature is not available
00095     and weak (surcharged) callbacks are used.
00096
00097     *** WWDG HAL driver macros list ***
00098     ===================================
00099     [..]
00100       Below the list of most used macros in WWDG HAL driver.
00101       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00102       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00103       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00104       (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
00105
00106   @endverbatim
00107   ******************************************************************************
00108   * @attention
00109   *
00110   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00111   * All rights reserved.</center></h2>
00112   *
00113   * This software component is licensed by ST under BSD 3-Clause license,
00114   * the "License"; You may not use this file except in compliance with the
00115   * License. You may obtain a copy of the License at:
00116   *                        opensource.org/licenses/BSD-3-Clause
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32h7xx_hal.h"
00123
00124 /** @addtogroup STM32H7xx_HAL_Driver
00125   * @{
00126   */
00127
00128 #ifdef HAL_WWDG_MODULE_ENABLED
00129 /** @defgroup WWDG WWDG
00130   * @brief WWDG HAL module driver.
00131   * @{
00132   */
00133
00134 /* Private typedef -----------------------------------------------------------*/
00135 /* Private define ------------------------------------------------------------*/
00136 /* Private macro -------------------------------------------------------------*/
00137 /* Private variables ---------------------------------------------------------*/
00138 /* Private function prototypes -----------------------------------------------*/
00139 /* Exported functions --------------------------------------------------------*/
00140
00141 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00142   * @{
00143   */
00144
00145 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00146   *  @brief    Initialization and Configuration functions.
00147   *
00148 @verbatim
00149   ==============================================================================
00150           ##### Initialization and Configuration functions #####
00151   ==============================================================================
00152   [..]
00153     This section provides functions allowing to:
00154       (+) Initialize and start the WWDG according to the specified parameters
00155           in the WWDG_InitTypeDef of associated handle.
00156       (+) Initialize the WWDG MSP.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initialize the WWDG according to the specified.
00164   *         parameters in the WWDG_InitTypeDef of  associated handle.
00165   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00166   *                the configuration information for the specified WWDG module.
00167   * @retval HAL status
00168   */
00169 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00170 {
00171   /* Check the WWDG handle allocation */
00172   if (hwwdg == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176
00177   /* Check the parameters */
00178   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00179   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00180   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00181   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00182   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00183
00184 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00185   /* Reset Callback pointers */
00186   if (hwwdg->EwiCallback == NULL)
00187   {
00188     hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00189   }
00190
00191   if (hwwdg->MspInitCallback == NULL)
00192   {
00193     hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00194   }
00195
00196   /* Init the low level hardware */
00197   hwwdg->MspInitCallback(hwwdg);
00198 #else
00199   /* Init the low level hardware */
00200   HAL_WWDG_MspInit(hwwdg);
00201 #endif
00202
00203   /* Set WWDG Counter */
00204   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00205
00206   /* Set WWDG Prescaler and Window */
00207   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213
00214 /**
00215   * @brief  Initialize the WWDG MSP.
00216   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00217   *                the configuration information for the specified WWDG module.
00218   * @note   When rewriting this function in user file, mechanism may be added
00219   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00220   *         again to change parameters.
00221   * @retval None
00222   */
00223 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hwwdg);
00227
00228   /* NOTE: This function should not be modified, when the callback is needed,
00229            the HAL_WWDG_MspInit could be implemented in the user file
00230    */
00231 }
00232
00233
00234 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00235 /**
00236   * @brief  Register a User WWDG Callback
00237   *         To be used instead of the weak (surcharged) predefined callback
00238   * @param  hwwdg WWDG handle
00239   * @param  CallbackID ID of the callback to be registered
00240   *         This parameter can be one of the following values:
00241   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00242   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00243   * @param  pCallback pointer to the Callback function
00244   * @retval status
00245   */
00246 HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
00247 {
00248   HAL_StatusTypeDef status = HAL_OK;
00249
00250   if (pCallback == NULL)
00251   {
00252     status = HAL_ERROR;
00253   }
00254   else
00255   {
00256     switch (CallbackID)
00257     {
00258       case HAL_WWDG_EWI_CB_ID:
00259         hwwdg->EwiCallback = pCallback;
00260         break;
00261
00262       case HAL_WWDG_MSPINIT_CB_ID:
00263         hwwdg->MspInitCallback = pCallback;
00264         break;
00265
00266       default:
00267         status = HAL_ERROR;
00268         break;
00269     }
00270   }
00271
00272   return status;
00273 }
00274
00275
00276 /**
00277   * @brief  Unregister a WWDG Callback
00278   *         WWDG Callback is redirected to the weak (surcharged) predefined callback
00279   * @param  hwwdg WWDG handle
00280   * @param  CallbackID ID of the callback to be registered
00281   *         This parameter can be one of the following values:
00282   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00283   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00284   * @retval status
00285   */
00286 HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
00287 {
00288   HAL_StatusTypeDef status = HAL_OK;
00289
00290   switch (CallbackID)
00291   {
00292     case HAL_WWDG_EWI_CB_ID:
00293       hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00294       break;
00295
00296     case HAL_WWDG_MSPINIT_CB_ID:
00297       hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00298       break;
00299
00300     default:
00301       status = HAL_ERROR;
00302       break;
00303   }
00304
00305   return status;
00306 }
00307 #endif
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00314   *  @brief    IO operation functions
00315   *
00316 @verbatim
00317   ==============================================================================
00318                       ##### IO operation functions #####
00319   ==============================================================================
00320   [..]
00321     This section provides functions allowing to:
00322     (+) Refresh the WWDG.
00323     (+) Handle WWDG interrupt request and associated function callback.
00324
00325 @endverbatim
00326   * @{
00327   */
00328
00329 /**
00330   * @brief  Refresh the WWDG.
00331   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00332   *                the configuration information for the specified WWDG module.
00333   * @retval HAL status
00334   */
00335 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00336 {
00337   /* Write to WWDG CR the WWDG Counter value to refresh with */
00338   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00339
00340   /* Return function status */
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Handle WWDG interrupt request.
00346   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00347   *         or data logging must be performed before the actual reset is generated.
00348   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00349   *         EWIMode set to WWDG_EWI_ENABLE.
00350   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00351   *         generated and the corresponding Interrupt Service Routine (ISR) can
00352   *         be used to trigger specific actions (such as communications or data
00353   *         logging), before resetting the device.
00354   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00355   *                the configuration information for the specified WWDG module.
00356   * @retval None
00357   */
00358 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00359 {
00360   /* Check if Early Wakeup Interrupt is enable */
00361   if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00362   {
00363     /* Check if WWDG Early Wakeup Interrupt occurred */
00364     if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00365     {
00366       /* Clear the WWDG Early Wakeup flag */
00367       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00368
00369 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00370       /* Early Wakeup registered callback */
00371       hwwdg->EwiCallback(hwwdg);
00372 #else
00373       /* Early Wakeup callback */
00374       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00375 #endif
00376     }
00377   }
00378 }
00379
00380
00381 /**
00382   * @brief  WWDG Early Wakeup callback.
00383   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00384   *                the configuration information for the specified WWDG module.
00385   * @retval None
00386   */
00387 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
00388 {
00389   /* Prevent unused argument(s) compilation warning */
00390   UNUSED(hwwdg);
00391
00392   /* NOTE: This function should not be modified, when the callback is needed,
00393            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00394    */
00395 }
00396
00397 /**
00398   * @}
00399   */
00400
00401 /**
00402   * @}
00403   */
00404
00405 #endif /* HAL_WWDG_MODULE_ENABLED */
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_hal_wwdg.h Source File

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stm32h7xx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_HAL_WWDG_H
00022 #define STM32H7xx_HAL_WWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup WWDG
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  WWDG Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00051                                This parameter can be a value of @ref WWDG_Prescaler */
00052
00053   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00054                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00055
00056   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00057                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00058
00059   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00060                                This parameter can be a value of @ref WWDG_EWI_Mode */
00061
00062 } WWDG_InitTypeDef;
00063
00064 /**
00065   * @brief  WWDG handle Structure definition
00066   */
00067 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00068 typedef struct __WWDG_HandleTypeDef
00069 #else
00070 typedef struct
00071 #endif
00072 {
00073   WWDG_TypeDef      *Instance;  /*!< Register base address */
00074
00075   WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
00076
00077 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00078   void              (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);     /*!< WWDG Early WakeUp Interrupt callback */
00079
00080   void              (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
00081 #endif
00082 } WWDG_HandleTypeDef;
00083
00084 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00085 /**
00086   * @brief  HAL WWDG common Callback ID enumeration definition
00087   */
00088 typedef enum
00089 {
00090   HAL_WWDG_EWI_CB_ID          = 0x00u,    /*!< WWDG EWI callback ID */
00091   HAL_WWDG_MSPINIT_CB_ID      = 0x01u,    /*!< WWDG MspInit callback ID */
00092 } HAL_WWDG_CallbackIDTypeDef;
00093
00094 /**
00095   * @brief  HAL WWDG Callback pointer definition
00096   */
00097 typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
00098
00099 #endif
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105
00106 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00107   * @{
00108   */
00109
00110 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00111   * @{
00112   */
00113 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00119   * @brief WWDG Flag definition
00120   * @{
00121   */
00122 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup WWDG_Prescaler WWDG Prescaler
00128   * @{
00129   */
00130 #define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
00131 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
00132 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
00133 #define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
00134 #define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */
00135 #define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */
00136 #define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */
00137 #define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00143   * @{
00144   */
00145 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00146 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00147 /**
00148   * @}
00149   */
00150
00151 /**
00152   * @}
00153   */
00154
00155 /* Private macros ------------------------------------------------------------*/
00156
00157 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00158   * @{
00159   */
00160 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
00161                                              ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
00162                                              ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
00163                                              ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
00164                                              ((__PRESCALER__) == WWDG_PRESCALER_16) || \
00165                                              ((__PRESCALER__) == WWDG_PRESCALER_32) || \
00166                                              ((__PRESCALER__) == WWDG_PRESCALER_64) || \
00167                                              ((__PRESCALER__) == WWDG_PRESCALER_128))
00168
00169 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00170
00171 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00172
00173 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00174                                              ((__MODE__) == WWDG_EWI_DISABLE))
00175 /**
00176   * @}
00177   */
00178
00179
00180 /* Exported macros ------------------------------------------------------------*/
00181
00182 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Enable the WWDG peripheral.
00188   * @param  __HANDLE__  WWDG handle
00189   * @retval None
00190   */
00191 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00192
00193 /**
00194   * @brief  Enable the WWDG early wakeup interrupt.
00195   * @param  __HANDLE__: WWDG handle
00196   * @param  __INTERRUPT__  specifies the interrupt to enable.
00197   *         This parameter can be one of the following values:
00198   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00199   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00200   * @retval None
00201   */
00202 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00203
00204 /**
00205   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00206   * @param  __HANDLE__  WWDG handle
00207   * @param  __INTERRUPT__  specifies the it to check.
00208   *        This parameter can be one of the following values:
00209   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00210   * @retval The new state of WWDG_FLAG (SET or RESET).
00211   */
00212 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00213
00214 /** @brief  Clear the WWDG interrupt pending bits.
00215   *         bits to clear the selected interrupt pending bits.
00216   * @param  __HANDLE__  WWDG handle
00217   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00218   *         This parameter can be one of the following values:
00219   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00220   */
00221 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00222
00223 /**
00224   * @brief  Check whether the specified WWDG flag is set or not.
00225   * @param  __HANDLE__  WWDG handle
00226   * @param  __FLAG__  specifies the flag to check.
00227   *         This parameter can be one of the following values:
00228   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00229   * @retval The new state of WWDG_FLAG (SET or RESET).
00230   */
00231 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00232
00233 /**
00234   * @brief  Clear the WWDG's pending flags.
00235   * @param  __HANDLE__  WWDG handle
00236   * @param  __FLAG__  specifies the flag to clear.
00237   *         This parameter can be one of the following values:
00238   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00239   * @retval None
00240   */
00241 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00242
00243 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00244   * @param  __HANDLE__  WWDG Handle.
00245   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00246   *         This parameter can be one of the following values:
00247   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00248   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00249   */
00250 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
00251                                                               & (__INTERRUPT__)) == (__INTERRUPT__))
00252
00253 /**
00254   * @}
00255   */
00256
00257 /* Exported functions --------------------------------------------------------*/
00258
00259 /** @addtogroup WWDG_Exported_Functions
00260   * @{
00261   */
00262
00263 /** @addtogroup WWDG_Exported_Functions_Group1
00264   * @{
00265   */
00266 /* Initialization/de-initialization functions  **********************************/
00267 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00268 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00269 /* Callbacks Register/UnRegister functions  ***********************************/
00270 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00271 HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
00272 HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
00273 #endif
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup WWDG_Exported_Functions_Group2
00280   * @{
00281   */
00282 /* I/O operation functions ******************************************************/
00283 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00284 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00285 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 #ifdef __cplusplus
00303 }
00304 #endif
00305
00306 #endif /* STM32H7xx_HAL_WWDG_H */
00307
00308 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_adc.c Source File

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stm32h7xx_ll_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @brief   ADC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_adc.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00036
00037 /** @addtogroup ADC_LL ADC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup ADC_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /* Definitions of ADC hardware constraints delays */
00049 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
00050 /*       not timeout values:                                                  */
00051 /*       Timeout values for ADC operations are dependent to device clock      */
00052 /*       configuration (system clock versus ADC clock),                       */
00053 /*       and therefore must be defined in user application.                   */
00054 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00055 /*       values definition.                                                   */
00056 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00057 /*       of device clock setting.                                             */
00058 /*       In user application, ADC timeout values should be defined with       */
00059 /*       temporal values, in function of device clock settings.               */
00060 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00061 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00062 /*          APB prescaler 16, ADC prescaler 4.                                */
00063 /*        - ADC clock from asynchronous clock (PLL) with prescaler 1,         */
00064 /*          with highest ratio CPU clock frequency vs HSI clock frequency     */
00065 /* Unit: CPU cycles.                                                          */
00066 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (512UL * 16UL * 4UL)
00067 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00068 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075
00076 /** @addtogroup ADC_LL_Private_Macros
00077   * @{
00078   */
00079
00080 /* Check of parameters for configuration of ADC hierarchical scope:           */
00081 /* common to several ADC instances.                                           */
00082 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00083   (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
00084    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00085    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
00086    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
00087    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
00088    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
00089    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
00090    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
00091    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
00092    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
00093    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
00094    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
00095    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
00096    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
00097    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
00098   )
00099
00100 /* Check of parameters for configuration of ADC hierarchical scope:           */
00101 /* ADC instance.                                                              */
00102 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00103   (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B)                              \
00104    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B)                              \
00105    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
00106    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00107    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00108   )
00109
00110 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__)                           \
00111   (   ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE)                     \
00112    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1)                        \
00113    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2)                        \
00114    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3)                        \
00115    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4)                        \
00116    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5)                        \
00117    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6)                        \
00118    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7)                        \
00119    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8)                        \
00120    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9)                        \
00121    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10)                       \
00122    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11)                       \
00123    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12)                       \
00124    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13)                       \
00125    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14)                       \
00126    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15)                       \
00127   )
00128
00129 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00130   (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
00131    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00132   )
00133
00134 /* Check of parameters for configuration of ADC hierarchical scope:           */
00135 /* ADC group regular                                                          */
00136 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00137   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00138    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00139    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00140    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00141    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00142    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00143    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00144    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00145    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00146    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00147    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00148    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00149    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00150    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00151    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00152    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00153    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00154    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
00155    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
00156    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)                \
00157    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)                \
00158    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)                \
00159   )
00160
00161 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00162   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
00163    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00164   )
00165
00166 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__)           \
00167   (   ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER)                 \
00168    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)        \
00169    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)      \
00170    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER)              \
00171   )
00172
00173 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00174   (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
00175    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00176   )
00177
00178 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00179   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
00180    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00181    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00182    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00183    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00184    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00185    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00186    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00187    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00188    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00189    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00190    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00191    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00192    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00193    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00194    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00195   )
00196
00197 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00198   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
00199    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00200    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00201    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00202    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00203    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00204    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00205    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00206    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00207   )
00208
00209 /* Check of parameters for configuration of ADC hierarchical scope:           */
00210 /* ADC group injected                                                         */
00211 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00212   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00213    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00214    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00215    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00216    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00217    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00218    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00219    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00220    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00221    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00222    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00223    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00224    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00225    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00226    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00227    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00228    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00229    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
00230    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
00231    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)                \
00232    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)                \
00233    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)                \
00234   )
00235
00236 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
00237   (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
00238    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
00239    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
00240   )
00241
00242 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00243   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
00244    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00245   )
00246
00247 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00248   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
00249    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00250    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00251    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00252   )
00253
00254 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00255   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
00256    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00257   )
00258
00259 /* Check of parameters for configuration of ADC hierarchical scope:           */
00260 /* multimode.                                                                 */
00261 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
00262   (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
00263    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
00264    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
00265    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
00266    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
00267    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
00268    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
00269    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
00270   )
00271
00272 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
00273   (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
00274    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B)            \
00275    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B)                \
00276   )
00277 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                    \
00278   (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)          \
00279    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)         \
00280    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)         \
00281    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)         \
00282    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS)  \
00283    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)         \
00284    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
00285    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)           \
00286    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)         \
00287    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
00288    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)         \
00289    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)           \
00290    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)           \
00291   )
00292
00293 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
00294   (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
00295    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
00296    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
00297   )
00298
00299 /**
00300   * @}
00301   */
00302
00303
00304 /* Private function prototypes -----------------------------------------------*/
00305
00306 /* Exported functions --------------------------------------------------------*/
00307 /** @addtogroup ADC_LL_Exported_Functions
00308   * @{
00309   */
00310
00311 /** @addtogroup ADC_LL_EF_Init
00312   * @{
00313   */
00314
00315 /**
00316   * @brief  De-initialize registers of all ADC instances belonging to
00317   *         the same ADC common instance to their default reset values.
00318   * @note   This function is performing a hard reset, using high level
00319   *         clock source RCC ADC reset.
00320   *         Caution: On this STM32 serie, if several ADC instances are available
00321   *         on the selected device, RCC ADC reset will reset
00322   *         all ADC instances belonging to the common ADC instance.
00323   *         To de-initialize only 1 ADC instance, use
00324   *         function @ref LL_ADC_DeInit().
00325   * @param  ADCxy_COMMON ADC common instance
00326   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00327   * @retval An ErrorStatus enumeration value:
00328   *          - SUCCESS: ADC common registers are de-initialized
00329   *          - ERROR: not applicable
00330   */
00331 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00332 {
00333   /* Check the parameters */
00334   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00335
00336   if(ADCxy_COMMON == ADC12_COMMON)
00337   {
00338     /* Force reset of ADC clock (core clock) */
00339     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
00340
00341     /* Release reset of ADC clock (core clock) */
00342     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
00343   }
00344   else
00345   {
00346 #if defined (ADC3)
00347     /* Force reset of ADC clock (core clock) */
00348     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_ADC3);
00349
00350     /* Release reset of ADC clock (core clock) */
00351     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3);
00352 #endif
00353   }
00354
00355   return SUCCESS;
00356 }
00357
00358 /**
00359   * @brief  Initialize some features of ADC common parameters
00360   *         (all ADC instances belonging to the same ADC common instance)
00361   *         and multimode (for devices with several ADC instances available).
00362   * @note   The setting of ADC common parameters is conditioned to
00363   *         ADC instances state:
00364   *         All ADC instances belonging to the same ADC common instance
00365   *         must be disabled.
00366   * @param  ADCxy_COMMON ADC common instance
00367   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00368   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00369   * @retval An ErrorStatus enumeration value:
00370   *          - SUCCESS: ADC common registers are initialized
00371   *          - ERROR: ADC common registers are not initialized
00372   */
00373 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00374 {
00375   ErrorStatus status = SUCCESS;
00376
00377   /* Check the parameters */
00378   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00379   assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
00380
00381   assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
00382   if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00383   {
00384     assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
00385     assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
00386   }
00387
00388   /* Note: Hardware constraint (refer to description of functions             */
00389   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
00390   /*       On this STM32 serie, setting of these features is conditioned to   */
00391   /*       ADC state:                                                         */
00392   /*       All ADC instances of the ADC common group must be disabled.        */
00393   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
00394   {
00395     /* Configuration of ADC hierarchical scope:                               */
00396     /*  - common to several ADC                                               */
00397     /*    (all ADC instances belonging to the same ADC common instance)       */
00398     /*    - Set ADC clock (conversion clock)                                  */
00399     /*  - multimode (if several ADC instances available on the                */
00400     /*    selected device)                                                    */
00401     /*    - Set ADC multimode configuration                                   */
00402     /*    - Set ADC multimode DMA transfer                                    */
00403     /*    - Set ADC multimode: delay between 2 sampling phases                */
00404     if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00405     {
00406       MODIFY_REG(ADCxy_COMMON->CCR,
00407                  ADC_CCR_CKMODE
00408                  | ADC_CCR_PRESC
00409                  | ADC_CCR_DUAL
00410                  | ADC_CCR_DAMDF
00411                  | ADC_CCR_DELAY
00412                  ,
00413                  ADC_CommonInitStruct->CommonClock
00414                  | ADC_CommonInitStruct->Multimode
00415                  | ADC_CommonInitStruct->MultiDMATransfer
00416                  | ADC_CommonInitStruct->MultiTwoSamplingDelay
00417                 );
00418     }
00419     else
00420     {
00421       MODIFY_REG(ADCxy_COMMON->CCR,
00422                  ADC_CCR_CKMODE
00423                  | ADC_CCR_PRESC
00424                  | ADC_CCR_DUAL
00425                  | ADC_CCR_DAMDF
00426                  | ADC_CCR_DELAY
00427                  ,
00428                  ADC_CommonInitStruct->CommonClock
00429                  | LL_ADC_MULTI_INDEPENDENT
00430                 );
00431     }
00432   }
00433   else
00434   {
00435     /* Initialization error: One or several ADC instances belonging to        */
00436     /* the same ADC common instance are not disabled.                         */
00437     status = ERROR;
00438   }
00439
00440   return status;
00441 }
00442
00443 /**
00444   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00445   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00446   *                              whose fields will be set to default values.
00447   * @retval None
00448   */
00449 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00450 {
00451   /* Set ADC_CommonInitStruct fields to default values */
00452   /* Set fields of ADC common */
00453   /* (all ADC instances belonging to the same ADC common instance) */
00454   ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00455
00456   /* Set fields of ADC multimode */
00457   ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
00458   ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
00459   ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
00460 }
00461
00462 /**
00463   * @brief  De-initialize registers of the selected ADC instance
00464   *         to their default reset values.
00465   * @note   To reset all ADC instances quickly (perform a hard reset),
00466   *         use function @ref LL_ADC_CommonDeInit().
00467   * @note   If this functions returns error status, it means that ADC instance
00468   *         is in an unknown state.
00469   *         In this case, perform a hard reset using high level
00470   *         clock source RCC ADC reset.
00471   *         Caution: On this STM32 serie, if several ADC instances are available
00472   *         on the selected device, RCC ADC reset will reset
00473   *         all ADC instances belonging to the common ADC instance.
00474   *         Refer to function @ref LL_ADC_CommonDeInit().
00475   * @param  ADCx ADC instance
00476   * @retval An ErrorStatus enumeration value:
00477   *          - SUCCESS: ADC registers are de-initialized
00478   *          - ERROR: ADC registers are not de-initialized
00479   */
00480 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00481 {
00482   ErrorStatus status = SUCCESS;
00483
00484   __IO uint32_t timeout_cpu_cycles = 0UL;
00485
00486   /* Check the parameters */
00487   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00488
00489   /* Disable ADC instance if not already disabled.                            */
00490   if (LL_ADC_IsEnabled(ADCx) == 1UL)
00491   {
00492     /* Set ADC group regular trigger source to SW start to ensure to not      */
00493     /* have an external trigger event occurring during the conversion stop    */
00494     /* ADC disable process.                                                   */
00495     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00496
00497     /* Stop potential ADC conversion on going on ADC group regular.           */
00498     if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
00499     {
00500       if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
00501       {
00502         LL_ADC_REG_StopConversion(ADCx);
00503       }
00504     }
00505
00506     /* Set ADC group injected trigger source to SW start to ensure to not     */
00507     /* have an external trigger event occurring during the conversion stop    */
00508     /* ADC disable process.                                                   */
00509     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
00510
00511     /* Stop potential ADC conversion on going on ADC group injected.          */
00512     if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
00513     {
00514       if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
00515       {
00516         LL_ADC_INJ_StopConversion(ADCx);
00517       }
00518     }
00519
00520     /* Wait for ADC conversions are effectively stopped                       */
00521     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00522     while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
00523             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
00524     {
00525       timeout_cpu_cycles--;
00526       if (timeout_cpu_cycles == 0UL)
00527       {
00528         /* Time-out error */
00529         status = ERROR;
00530         break;
00531       }
00532     }
00533
00534     /* Flush group injected contexts queue (register JSQR):                   */
00535     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
00536     /*       contexts queue is maintained with the last active context).      */
00537     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
00538
00539     /* Disable the ADC instance */
00540     LL_ADC_Disable(ADCx);
00541
00542     /* Wait for ADC instance is effectively disabled */
00543     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00544     while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
00545     {
00546       timeout_cpu_cycles--;
00547       if (timeout_cpu_cycles == 0UL)
00548       {
00549         /* Time-out error */
00550         status = ERROR;
00551         break;
00552       }
00553     }
00554   }
00555
00556   /* Check whether ADC state is compliant with expected state */
00557   if (READ_BIT(ADCx->CR,
00558                (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
00559                 | ADC_CR_ADDIS | ADC_CR_ADEN)
00560               )
00561       == 0UL)
00562   {
00563     /* ========== Reset ADC registers ========== */
00564     /* Reset register IER */
00565     CLEAR_BIT(ADCx->IER,
00566               (LL_ADC_IT_ADRDY
00567                | LL_ADC_IT_EOC
00568                | LL_ADC_IT_EOS
00569                | LL_ADC_IT_OVR
00570                | LL_ADC_IT_EOSMP
00571                | LL_ADC_IT_JEOC
00572                | LL_ADC_IT_JEOS
00573                | LL_ADC_IT_JQOVF
00574                | LL_ADC_IT_AWD1
00575                | LL_ADC_IT_AWD2
00576                | LL_ADC_IT_AWD3
00577               )
00578              );
00579
00580     /* Reset register ISR */
00581     SET_BIT(ADCx->ISR,
00582             (LL_ADC_FLAG_ADRDY
00583              | LL_ADC_FLAG_EOC
00584              | LL_ADC_FLAG_EOS
00585              | LL_ADC_FLAG_OVR
00586              | LL_ADC_FLAG_EOSMP
00587              | LL_ADC_FLAG_JEOC
00588              | LL_ADC_FLAG_JEOS
00589              | LL_ADC_FLAG_JQOVF
00590              | LL_ADC_FLAG_AWD1
00591              | LL_ADC_FLAG_AWD2
00592              | LL_ADC_FLAG_AWD3
00593             )
00594            );
00595
00596     /* Reset register CR */
00597     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
00598     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
00599     /*    access mode "read-set": no direct reset applicable.                 */
00600     /*  - Reset Calibration mode to default setting (single ended).           */
00601     /*  - Disable ADC internal voltage regulator.                             */
00602     /*  - Enable ADC deep power down.                                         */
00603     /*    Note: ADC internal voltage regulator disable and ADC deep power     */
00604     /*          down enable are conditioned to ADC state disabled:            */
00605     /*          already done above.                                           */
00606     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00607     SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
00608
00609     /* Reset register CFGR */
00610     CLEAR_BIT(ADCx->CFGR,
00611               (  ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
00612                | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
00613                | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
00614                | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
00615                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_RES
00616                | ADC_CFGR_DMNGT  )
00617              );
00618
00619     SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
00620
00621     /* Reset register CFGR2 */
00622     CLEAR_BIT(ADCx->CFGR2,
00623               (  ADC_CFGR2_LSHIFT  | ADC_CFGR2_OVSR    | ADC_CFGR2_RSHIFT1
00624                | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
00625                | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM   | ADC_CFGR2_TROVS
00626                | ADC_CFGR2_OVSS    | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
00627              );
00628
00629     /* Reset register SMPR1 */
00630     CLEAR_BIT(ADCx->SMPR1,
00631               (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
00632                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
00633                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
00634              );
00635
00636     /* Reset register SMPR2 */
00637     CLEAR_BIT(ADCx->SMPR2,
00638               (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
00639                | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
00640                | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
00641                | ADC_SMPR2_SMP10)
00642              );
00643
00644     /* Reset register TR1 */
00645     CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT);
00646     SET_BIT(ADCx->HTR1, ADC_HTR_HT);
00647
00648     CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT);
00649     SET_BIT(ADCx->HTR2, ADC_HTR_HT);
00650     CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT);
00651     SET_BIT(ADCx->HTR3, ADC_HTR_HT);
00652
00653     /* Reset register SQR1 */
00654     CLEAR_BIT(ADCx->SQR1,
00655               (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
00656                | ADC_SQR1_SQ1 | ADC_SQR1_L)
00657              );
00658
00659     /* Reset register SQR2 */
00660     CLEAR_BIT(ADCx->SQR2,
00661               (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
00662                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
00663              );
00664
00665     /* Reset register SQR3 */
00666     CLEAR_BIT(ADCx->SQR3,
00667               (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
00668                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
00669              );
00670
00671     /* Reset register SQR4 */
00672     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00673
00674     /* Reset register JSQR */
00675     CLEAR_BIT(ADCx->JSQR,
00676               (ADC_JSQR_JL
00677                | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
00678                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
00679                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
00680              );
00681
00682     /* Reset register DR */
00683     /* Note: bits in access mode read only, no direct reset applicable */
00684
00685     /* Reset register OFR1 */
00686     CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
00687     /* Reset register OFR2 */
00688     CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
00689     /* Reset register OFR3 */
00690     CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
00691     /* Reset register OFR4 */
00692     CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
00693
00694     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00695     /* Note: bits in access mode read only, no direct reset applicable */
00696
00697     /* Reset register AWD2CR */
00698     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
00699
00700     /* Reset register AWD3CR */
00701     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
00702
00703     /* Reset register DIFSEL */
00704     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
00705
00706     /* Reset register CALFACT */
00707     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00708
00709     /* Reset register CALFACT2 */
00710     CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
00711   }
00712   else
00713   {
00714     /* ADC instance is in an unknown state */
00715     /* Need to performing a hard reset of ADC instance, using high level      */
00716     /* clock source RCC ADC reset.                                            */
00717     /* Caution: On this STM32 serie, if several ADC instances are available   */
00718     /*          on the selected device, RCC ADC reset will reset              */
00719     /*          all ADC instances belonging to the common ADC instance.       */
00720     /* Caution: On this STM32 serie, if several ADC instances are available   */
00721     /*          on the selected device, RCC ADC reset will reset              */
00722     /*          all ADC instances belonging to the common ADC instance.       */
00723     status = ERROR;
00724   }
00725
00726   return status;
00727 }
00728
00729 /**
00730   * @brief  Initialize some features of ADC instance.
00731   * @note   These parameters have an impact on ADC scope: ADC instance.
00732   *         Affects both group regular and group injected (availability
00733   *         of ADC group injected depends on STM32 families).
00734   *         Refer to corresponding unitary functions into
00735   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00736   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00737   *         is conditioned to ADC state:
00738   *         ADC instance must be disabled.
00739   *         This condition is applied to all ADC features, for efficiency
00740   *         and compatibility over all STM32 families. However, the different
00741   *         features can be set under different ADC state conditions
00742   *         (setting possible with ADC enabled without conversion on going,
00743   *         ADC enabled with conversion on going, ...)
00744   *         Each feature can be updated afterwards with a unitary function
00745   *         and potentially with ADC in a different state than disabled,
00746   *         refer to description of each function for setting
00747   *         conditioned to ADC state.
00748   * @note   After using this function, some other features must be configured
00749   *         using LL unitary functions.
00750   *         The minimum configuration remaining to be done is:
00751   *          - Set ADC group regular or group injected sequencer:
00752   *            map channel on the selected sequencer rank.
00753   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00754   *          - Set ADC channel sampling time
00755   *            Refer to function LL_ADC_SetChannelSamplingTime();
00756   * @param  ADCx ADC instance
00757   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00758   * @retval An ErrorStatus enumeration value:
00759   *          - SUCCESS: ADC registers are initialized
00760   *          - ERROR: ADC registers are not initialized
00761   */
00762 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
00763 {
00764   ErrorStatus status = SUCCESS;
00765
00766   /* Check the parameters */
00767   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00768
00769   assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
00770   assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift));
00771   assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
00772
00773   /* Note: Hardware constraint (refer to description of this function):       */
00774   /*       ADC instance must be disabled.                                     */
00775   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00776   {
00777     /* Configuration of ADC hierarchical scope:                               */
00778     /*  - ADC instance                                                        */
00779     /*    - Set ADC data resolution                                           */
00780     /*    - Set ADC conversion data alignment                                 */
00781     /*    - Set ADC low power mode                                            */
00782     MODIFY_REG(ADCx->CFGR,
00783                ADC_CFGR_RES
00784                | ADC_CFGR_AUTDLY
00785                ,
00786                ADC_InitStruct->Resolution
00787                | ADC_InitStruct->LowPowerMode
00788               );
00789
00790     MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
00791   }
00792   else
00793   {
00794     /* Initialization error: ADC instance is not disabled. */
00795     status = ERROR;
00796   }
00797   return status;
00798 }
00799
00800 /**
00801   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
00802   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
00803   *                        whose fields will be set to default values.
00804   * @retval None
00805   */
00806 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
00807 {
00808   /* Set ADC_InitStruct fields to default values */
00809   /* Set fields of ADC instance */
00810   ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_16B;
00811   ADC_InitStruct->LeftBitShift  = LL_ADC_LEFT_BIT_SHIFT_NONE;
00812   ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
00813
00814 }
00815
00816 /**
00817   * @brief  Initialize some features of ADC group regular.
00818   * @note   These parameters have an impact on ADC scope: ADC group regular.
00819   *         Refer to corresponding unitary functions into
00820   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00821   *         (functions with prefix "REG").
00822   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00823   *         is conditioned to ADC state:
00824   *         ADC instance must be disabled.
00825   *         This condition is applied to all ADC features, for efficiency
00826   *         and compatibility over all STM32 families. However, the different
00827   *         features can be set under different ADC state conditions
00828   *         (setting possible with ADC enabled without conversion on going,
00829   *         ADC enabled with conversion on going, ...)
00830   *         Each feature can be updated afterwards with a unitary function
00831   *         and potentially with ADC in a different state than disabled,
00832   *         refer to description of each function for setting
00833   *         conditioned to ADC state.
00834   * @note   After using this function, other features must be configured
00835   *         using LL unitary functions.
00836   *         The minimum configuration remaining to be done is:
00837   *          - Set ADC group regular or group injected sequencer:
00838   *            map channel on the selected sequencer rank.
00839   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00840   *          - Set ADC channel sampling time
00841   *            Refer to function LL_ADC_SetChannelSamplingTime();
00842   * @param  ADCx ADC instance
00843   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00844   * @retval An ErrorStatus enumeration value:
00845   *          - SUCCESS: ADC registers are initialized
00846   *          - ERROR: ADC registers are not initialized
00847   */
00848 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00849 {
00850   ErrorStatus status = SUCCESS;
00851
00852   /* Check the parameters */
00853   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00854   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
00855   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
00856   if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00857   {
00858     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
00859   }
00860   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
00861   assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
00862   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
00863
00864   /* Note: Hardware constraint (refer to description of this function):       */
00865   /*       ADC instance must be disabled.                                     */
00866   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00867   {
00868     /* Configuration of ADC hierarchical scope:                               */
00869     /*  - ADC group regular                                                   */
00870     /*    - Set ADC group regular trigger source                              */
00871     /*    - Set ADC group regular sequencer length                            */
00872     /*    - Set ADC group regular sequencer discontinuous mode                */
00873     /*    - Set ADC group regular continuous mode                             */
00874     /*    - Set ADC group regular conversion data transfer: no transfer or    */
00875     /*      transfer by DMA, and DMA requests mode                            */
00876     /*    - Set ADC group regular overrun behavior                            */
00877     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
00878     /*       setting of trigger source to SW start.                           */
00879     if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00880     {
00881       MODIFY_REG(ADCx->CFGR,
00882                  ADC_CFGR_EXTSEL
00883                  | ADC_CFGR_EXTEN
00884                  | ADC_CFGR_DISCEN
00885                  | ADC_CFGR_DISCNUM
00886                  | ADC_CFGR_CONT
00887                  | ADC_CFGR_DMNGT
00888                  | ADC_CFGR_OVRMOD
00889                  ,
00890                  ADC_REG_InitStruct->TriggerSource
00891                  | ADC_REG_InitStruct->SequencerDiscont
00892                  | ADC_REG_InitStruct->ContinuousMode
00893                  | ADC_REG_InitStruct->DataTransferMode
00894                  | ADC_REG_InitStruct->Overrun
00895                 );
00896     }
00897     else
00898     {
00899       MODIFY_REG(ADCx->CFGR,
00900                  ADC_CFGR_EXTSEL
00901                  | ADC_CFGR_EXTEN
00902                  | ADC_CFGR_DISCEN
00903                  | ADC_CFGR_DISCNUM
00904                  | ADC_CFGR_CONT
00905                  | ADC_CFGR_DMNGT
00906                  | ADC_CFGR_OVRMOD
00907                  ,
00908                  ADC_REG_InitStruct->TriggerSource
00909                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
00910                  | ADC_REG_InitStruct->ContinuousMode
00911                  | ADC_REG_InitStruct->DataTransferMode
00912                  | ADC_REG_InitStruct->Overrun
00913                 );
00914     }
00915
00916     /* Set ADC group regular sequencer length and scan direction */
00917     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
00918   }
00919   else
00920   {
00921     /* Initialization error: ADC instance is not disabled. */
00922     status = ERROR;
00923   }
00924   return status;
00925 }
00926
00927 /**
00928   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
00929   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00930   *                            whose fields will be set to default values.
00931   * @retval None
00932   */
00933 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00934 {
00935   /* Set ADC_REG_InitStruct fields to default values */
00936   /* Set fields of ADC group regular */
00937   /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
00938   /*       setting of trigger source to SW start.                             */
00939   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
00940   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
00941   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
00942   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
00943   ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
00944   ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
00945 }
00946
00947 /**
00948   * @brief  Initialize some features of ADC group injected.
00949   * @note   These parameters have an impact on ADC scope: ADC group injected.
00950   *         Refer to corresponding unitary functions into
00951   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00952   *         (functions with prefix "INJ").
00953   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00954   *         is conditioned to ADC state:
00955   *         ADC instance must be disabled.
00956   *         This condition is applied to all ADC features, for efficiency
00957   *         and compatibility over all STM32 families. However, the different
00958   *         features can be set under different ADC state conditions
00959   *         (setting possible with ADC enabled without conversion on going,
00960   *         ADC enabled with conversion on going, ...)
00961   *         Each feature can be updated afterwards with a unitary function
00962   *         and potentially with ADC in a different state than disabled,
00963   *         refer to description of each function for setting
00964   *         conditioned to ADC state.
00965   * @note   After using this function, other features must be configured
00966   *         using LL unitary functions.
00967   *         The minimum configuration remaining to be done is:
00968   *          - Set ADC group injected sequencer:
00969   *            map channel on the selected sequencer rank.
00970   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
00971   *          - Set ADC channel sampling time
00972   *            Refer to function LL_ADC_SetChannelSamplingTime();
00973   * @param  ADCx ADC instance
00974   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00975   * @retval An ErrorStatus enumeration value:
00976   *          - SUCCESS: ADC registers are initialized
00977   *          - ERROR: ADC registers are not initialized
00978   */
00979 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00980 {
00981   ErrorStatus status = SUCCESS;
00982
00983   /* Check the parameters */
00984   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00985   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
00986   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
00987   if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
00988   {
00989     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
00990   }
00991   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
00992
00993   /* Note: Hardware constraint (refer to description of this function):       */
00994   /*       ADC instance must be disabled.                                     */
00995   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00996   {
00997     /* Configuration of ADC hierarchical scope:                               */
00998     /*  - ADC group injected                                                  */
00999     /*    - Set ADC group injected trigger source                             */
01000     /*    - Set ADC group injected sequencer length                           */
01001     /*    - Set ADC group injected sequencer discontinuous mode               */
01002     /*    - Set ADC group injected conversion trigger: independent or         */
01003     /*      from ADC group regular                                            */
01004     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
01005     /*       setting of trigger source to SW start.                           */
01006     if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01007     {
01008       MODIFY_REG(ADCx->CFGR,
01009                  ADC_CFGR_JDISCEN
01010                  | ADC_CFGR_JAUTO
01011                  ,
01012                  ADC_INJ_InitStruct->SequencerDiscont
01013                  | ADC_INJ_InitStruct->TrigAuto
01014                 );
01015     }
01016     else
01017     {
01018       MODIFY_REG(ADCx->CFGR,
01019                  ADC_CFGR_JDISCEN
01020                  | ADC_CFGR_JAUTO
01021                  ,
01022                  LL_ADC_REG_SEQ_DISCONT_DISABLE
01023                  | ADC_INJ_InitStruct->TrigAuto
01024                 );
01025     }
01026
01027     MODIFY_REG(ADCx->JSQR,
01028                ADC_JSQR_JEXTSEL
01029                | ADC_JSQR_JEXTEN
01030                | ADC_JSQR_JL
01031                ,
01032                ADC_INJ_InitStruct->TriggerSource
01033                | ADC_INJ_InitStruct->SequencerLength
01034               );
01035   }
01036   else
01037   {
01038     /* Initialization error: ADC instance is not disabled. */
01039     status = ERROR;
01040   }
01041   return status;
01042 }
01043
01044 /**
01045   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
01046   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01047   *                            whose fields will be set to default values.
01048   * @retval None
01049   */
01050 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01051 {
01052   /* Set ADC_INJ_InitStruct fields to default values */
01053   /* Set fields of ADC group injected */
01054   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
01055   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
01056   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
01057   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
01058 }
01059
01060 /**
01061   * @}
01062   */
01063
01064 /**
01065   * @}
01066   */
01067
01068 /**
01069   * @}
01070   */
01071
01072 #endif /* ADC1 || ADC2 || ADC3 */
01073
01074 /**
01075   * @}
01076   */
01077
01078 #endif /* USE_FULL_LL_DRIVER */
01079
01080 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:02 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_adc.h Source File

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stm32h7xx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_ADC_H
00022 #define STM32H7xx_LL_ADC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00036
00037 /** @defgroup ADC_LL ADC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00046   * @{
00047   */
00048
00049 /* Internal mask for ADC calibration:                                         */
00050 /* Internal register offset for ADC calibration factors configuration */
00051
00052 /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ...   */
00053 /* the relevant bits for:                                                     */
00054 /* (concatenation of multiple bits used in different registers)               */
00055 /* - ADC calibration configuration: configuration before calibration start    */
00056 /* - ADC calibration factors: register offset                                 */
00057 #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET    (0x00000000UL) /* Register CALFACT defined as reference register */
00058 #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
00059 #define ADC_CALIB_FACTOR_REGOFFSET_MASK      (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
00060 #define ADC_CALIB_MODE_MASK                  (ADC_CR_ADCALLIN)
00061 #define ADC_CALIB_MODE_BINARY_MASK           (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
00062
00063
00064 /* Internal mask for ADC group regular sequencer:                             */
00065 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00066 /* - sequencer register offset                                                */
00067 /* - sequencer rank bits position into the selected register                  */
00068
00069 /* Internal register offset for ADC group regular sequencer configuration */
00070 /* (offset placed into a spare area of literal definition) */
00071 #define ADC_SQR1_REGOFFSET                 (0x00000000UL)
00072 #define ADC_SQR2_REGOFFSET                 (0x00000100UL)
00073 #define ADC_SQR3_REGOFFSET                 (0x00000200UL)
00074 #define ADC_SQR4_REGOFFSET                 (0x00000300UL)
00075
00076 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00077 #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
00078 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00079
00080 /* Definition of ADC group regular sequencer bits information to be inserted  */
00081 /* into ADC group regular sequencer ranks literals definition.                */
00082 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
00083 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
00084 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
00085 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
00086 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
00087 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
00088 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
00089 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
00090 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
00091 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
00092 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
00093 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
00094 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
00095 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
00096 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
00097 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
00098
00099
00100
00101 /* Internal mask for ADC group injected sequencer:                            */
00102 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00103 /* - data register offset                                                     */
00104 /* - sequencer rank bits position into the selected register                  */
00105
00106 /* Internal register offset for ADC group injected data register */
00107 /* (offset placed into a spare area of literal definition) */
00108 #define ADC_JDR1_REGOFFSET                 (0x00000000UL)
00109 #define ADC_JDR2_REGOFFSET                 (0x00000100UL)
00110 #define ADC_JDR3_REGOFFSET                 (0x00000200UL)
00111 #define ADC_JDR4_REGOFFSET                 (0x00000300UL)
00112
00113 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00114 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00115 #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
00116
00117 /* Definition of ADC group injected sequencer bits information to be inserted */
00118 /* into ADC group injected sequencer ranks literals definition.               */
00119 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
00120 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
00121 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
00122 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
00123
00124
00125
00126 /* Internal mask for ADC group regular trigger:                               */
00127 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00128 /* - regular trigger source                                                   */
00129 /* - regular trigger edge                                                     */
00130 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00131
00132 /* Mask containing trigger source masks for each of possible                  */
00133 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00134 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00135 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
00136                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
00137                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
00138                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )
00139
00140 /* Mask containing trigger edge masks for each of possible                    */
00141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00143 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
00144                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
00145                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
00146                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )
00147
00148 /* Definition of ADC group regular trigger bits information.                  */
00149 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
00150 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
00151
00152
00153
00154 /* Internal mask for ADC group injected trigger:                              */
00155 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00156 /* - injected trigger source                                                  */
00157 /* - injected trigger edge                                                    */
00158 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00159
00160 /* Mask containing trigger source masks for each of possible                  */
00161 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00162 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00163 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
00164                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
00165                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
00166                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
00167
00168 /* Mask containing trigger edge masks for each of possible                    */
00169 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00170 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00171 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
00172                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
00173                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
00174                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
00175
00176 /* Definition of ADC group injected trigger bits information.                 */
00177 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
00178 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
00179
00180
00181
00182
00183
00184
00185 /* Internal mask for ADC channel:                                             */
00186 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00187 /* - channel identifier defined by number                                     */
00188 /* - channel identifier defined by bitfield                                   */
00189 /* - channel differentiation between external channels (connected to          */
00190 /*   GPIO pins) and internal channels (connected to internal paths)           */
00191 /* - channel sampling time defined by SMPRx register offset                   */
00192 /*   and SMPx bits positions into SMPRx register                              */
00193 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00194 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00195 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
00196 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00197 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00198 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
00199
00200 /* Channel differentiation between external and internal channels */
00201 #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
00202 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
00203
00204 /* Internal register offset for ADC channel sampling time configuration */
00205 /* (offset placed into a spare area of literal definition) */
00206 #define ADC_SMPR1_REGOFFSET                (0x00000000UL)
00207 #define ADC_SMPR2_REGOFFSET                (0x02000000UL)
00208 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00209 #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
00210
00211 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
00212 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
00213
00214 /* Definition of channels ID number information to be inserted into           */
00215 /* channels literals definition.                                              */
00216 #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
00217 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
00218 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
00219 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00220 #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
00221 #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00222 #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00223 #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00224 #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
00225 #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
00226 #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
00227 #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00228 #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
00229 #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00230 #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00231 #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00232 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
00233 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
00234 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
00235 #define ADC_CHANNEL_19_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00236
00237 /* Definition of channels ID bitfield information to be inserted into         */
00238 /* channels literals definition.                                              */
00239 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00240 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00241 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00242 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00243 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00244 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00245 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00246 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00247 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00248 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00249 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00250 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00251 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00252 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00253 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00254 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00255 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00256 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00257 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00258 #define ADC_CHANNEL_19_BITFIELD            (ADC_AWD2CR_AWD2CH_19)
00259
00260 /* Definition of channels sampling time information to be inserted into       */
00261 /* channels literals definition.                                              */
00262 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
00263 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
00264 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
00265 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
00266 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
00267 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
00268 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
00269 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
00270 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
00271 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
00272 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
00273 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
00274 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
00275 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
00276 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
00277 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
00278 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
00279 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
00280 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
00281 #define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
00282
00283
00284 /* Internal mask for ADC mode single or differential ended:                   */
00285 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00286 /* the relevant bits for:                                                     */
00287 /* (concatenation of multiple bits used in different registers)               */
00288 /* - ADC calibration: calibration start, calibration factor get or set        */
00289 /* - ADC channels: set each ADC channel ending mode                           */
00290 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00291 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00292 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00293 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
00294 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */
00295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */
00296 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
00297
00298 /* Internal mask for ADC analog watchdog:                                     */
00299 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00300 /* (concatenation of multiple bits used in different analog watchdogs,        */
00301 /* (feature of several watchdogs not available on all STM32 families)).       */
00302 /* - analog watchdog 1: monitored channel defined by number,                  */
00303 /*   selection of ADC group (ADC groups regular and-or injected).             */
00304 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00305 /*   selection on groups.                                                     */
00306
00307 /* Internal register offset for ADC analog watchdog channel configuration */
00308 #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
00309 #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
00310 #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
00311
00312 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00313 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00314 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00315 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
00316
00317 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00318
00319 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00320 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00321 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00322
00323 #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
00324
00325 /* Internal register offset for ADC analog watchdog threshold configuration */
00326 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00327 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00328 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00329 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00330 #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
00331
00332 /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
00333 /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
00334 #define ADC_AWD_TR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00335 #define ADC_AWD_TR12_REGOFFSETGAP_VAL      (0x00000022UL)
00336
00337 /* Legacy literals */
00338 #define LL_ADC_AWD1_TR                      LL_ADC_AWD1
00339 #define LL_ADC_AWD2_TR                      LL_ADC_AWD2
00340 #define LL_ADC_AWD3_TR                      LL_ADC_AWD3
00341
00342 /* Internal mask for ADC offset:                                              */
00343 /* Internal register offset for ADC offset number configuration */
00344 #define ADC_OFR1_REGOFFSET                 (0x00000000UL)
00345 #define ADC_OFR2_REGOFFSET                 (0x00000001UL)
00346 #define ADC_OFR3_REGOFFSET                 (0x00000002UL)
00347 #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
00348 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00349
00350
00351 /* ADC registers bits positions */
00352 #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
00353 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
00354 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
00355 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
00356
00357
00358 /* ADC registers bits groups */
00359 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00360
00361
00362 /* ADC internal channels related definitions */
00363 /* Internal voltage reference VrefInt */
00364 #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00365 #define VREFINT_CAL_VREF                   (3300UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00366 /* Temperature sensor */
00367 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00368 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
00369 #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00370 #define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00371 #define TEMPSENSOR_CAL_VREFANALOG          (3300UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
00372
00373
00374 /* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
00375 #define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
00376 #define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
00377 #define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
00378 #define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
00379 #define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
00380 #define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
00381 #define ADC_LINEAR_CALIB_REG_COUNT  (6UL)
00382 /**
00383   * @}
00384   */
00385
00386
00387 /* Private macros ------------------------------------------------------------*/
00388 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00389   * @{
00390   */
00391
00392 /**
00393   * @brief  Driver macro reserved for internal use: set a pointer to
00394   *         a register from a register basis from which an offset
00395   *         is applied.
00396   * @param  __REG__ Register basis from which the offset is applied.
00397   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00398   * @retval Pointer to register address
00399   */
00400 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00401   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00402
00403 /**
00404   * @}
00405   */
00406
00407
00408 /* Exported types ------------------------------------------------------------*/
00409 #if defined(USE_FULL_LL_DRIVER)
00410 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00411   * @{
00412   */
00413
00414 /**
00415   * @brief  Structure definition of some features of ADC common parameters
00416   *         and multimode
00417   *         (all ADC instances belonging to the same ADC common instance).
00418   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00419   *         is conditioned to ADC instances state (all ADC instances
00420   *         sharing the same ADC common instance):
00421   *         All ADC instances sharing the same ADC common instance must be
00422   *         disabled.
00423   */
00424 typedef struct
00425 {
00426   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00427                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00428                                              @note On this STM32 serie, if ADC group injected is used, some
00429                                                    clock ratio constraints between ADC clock and AHB clock
00430                                                    must be respected. Refer to reference manual.
00431
00432                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
00433
00434   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
00435                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
00436
00437                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
00438
00439   uint32_t MultiDMATransfer;            /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.
00440                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
00441
00442                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
00443
00444   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
00445                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
00446
00447                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
00448
00449 } LL_ADC_CommonInitTypeDef;
00450
00451 /**
00452   * @brief  Structure definition of some features of ADC instance.
00453   * @note   These parameters have an impact on ADC scope: ADC instance.
00454   *         Affects both group regular and group injected (availability
00455   *         of ADC group injected depends on STM32 families).
00456   *         Refer to corresponding unitary functions into
00457   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00458   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00459   *         is conditioned to ADC state:
00460   *         ADC instance must be disabled.
00461   *         This condition is applied to all ADC features, for efficiency
00462   *         and compatibility over all STM32 families. However, the different
00463   *         features can be set under different ADC state conditions
00464   *         (setting possible with ADC enabled without conversion on going,
00465   *         ADC enabled with conversion on going, ...)
00466   *         Each feature can be updated afterwards with a unitary function
00467   *         and potentially with ADC in a different state than disabled,
00468   *         refer to description of each function for setting
00469   *         conditioned to ADC state.
00470   */
00471 typedef struct
00472 {
00473   uint32_t Resolution;                  /*!< Set ADC resolution.
00474                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00475
00476                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
00477
00478   uint32_t LeftBitShift;                /*!< Configures the left shifting applied to the final result with or without oversampling.
00479                                              This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
00480
00481   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00482                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00483
00484                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
00485
00486 } LL_ADC_InitTypeDef;
00487
00488 /**
00489   * @brief  Structure definition of some features of ADC group regular.
00490   * @note   These parameters have an impact on ADC scope: ADC group regular.
00491   *         Refer to corresponding unitary functions into
00492   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00493   *         (functions with prefix "REG").
00494   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00495   *         is conditioned to ADC state:
00496   *         ADC instance must be disabled.
00497   *         This condition is applied to all ADC features, for efficiency
00498   *         and compatibility over all STM32 families. However, the different
00499   *         features can be set under different ADC state conditions
00500   *         (setting possible with ADC enabled without conversion on going,
00501   *         ADC enabled with conversion on going, ...)
00502   *         Each feature can be updated afterwards with a unitary function
00503   *         and potentially with ADC in a different state than disabled,
00504   *         refer to description of each function for setting
00505   *         conditioned to ADC state.
00506   */
00507 typedef struct
00508 {
00509   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
00510                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00511                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00512                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00513                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
00514
00515                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00516
00517   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00518                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00519
00520                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00521
00522   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00523                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00524                                              @note This parameter has an effect only if group regular sequencer is enabled
00525                                                    (scan length of 2 ranks or more).
00526
00527                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00528
00529   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00530                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00531                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00532
00533                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00534
00535   uint32_t DataTransferMode;            /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.
00536                                              This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
00537
00538                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */
00539
00540   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00541                                              data preserved or overwritten.
00542                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00543
00544                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
00545
00546 } LL_ADC_REG_InitTypeDef;
00547
00548 /**
00549   * @brief  Structure definition of some features of ADC group injected.
00550   * @note   These parameters have an impact on ADC scope: ADC group injected.
00551   *         Refer to corresponding unitary functions into
00552   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00553   *         (functions with prefix "INJ").
00554   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00555   *         is conditioned to ADC state:
00556   *         ADC instance must be disabled.
00557   *         This condition is applied to all ADC features, for efficiency
00558   *         and compatibility over all STM32 families. However, the different
00559   *         features can be set under different ADC state conditions
00560   *         (setting possible with ADC enabled without conversion on going,
00561   *         ADC enabled with conversion on going, ...)
00562   *         Each feature can be updated afterwards with a unitary function
00563   *         and potentially with ADC in a different state than disabled,
00564   *         refer to description of each function for setting
00565   *         conditioned to ADC state.
00566   */
00567 typedef struct
00568 {
00569   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
00570                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00571                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00572                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00573                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
00574
00575                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
00576
00577   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00578                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00579
00580                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
00581
00582   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00583                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00584                                              @note This parameter has an effect only if group injected sequencer is enabled
00585                                                    (scan length of 2 ranks or more).
00586
00587                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
00588
00589   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
00590                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00591                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
00592
00593                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
00594
00595 } LL_ADC_INJ_InitTypeDef;
00596
00597 /**
00598   * @}
00599   */
00600 #endif /* USE_FULL_LL_DRIVER */
00601
00602 /* Exported constants --------------------------------------------------------*/
00603 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00604   * @{
00605   */
00606
00607 /** @defgroup ADC_LL_EC_FLAG ADC flags
00608   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00609   * @{
00610   */
00611 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00612 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00613 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00614 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00615 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00616 #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
00617 #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
00618 #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
00619 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00620 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00621 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00622 #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
00623 #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
00624 #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
00625 #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
00626 #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */
00627 #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
00628 #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */
00629 #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */
00630 #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */
00631 #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */
00632 #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */
00633 #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
00634 #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */
00635 #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
00636 #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */
00637 #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
00638 #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
00639 #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
00640 #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
00641 #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
00642 #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
00643 #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00649   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00650   * @{
00651   */
00652 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00653 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
00654 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
00655 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00656 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
00657 #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
00658 #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
00659 #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
00660 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00661 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00662 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00668   * @{
00669   */
00670 /* List of ADC registers intended to be used (most commonly) with             */
00671 /* DMA transfer.                                                              */
00672 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00673 #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00674 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
00675 /**
00676   * @}
00677   */
00678
00679 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00680   * @{
00681   */
00682 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
00683 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00684 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00685 #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */
00686 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
00687 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
00688 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */
00689 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */
00690 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */
00691 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */
00692 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */
00693 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */
00694 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */
00695 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */
00696 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00702   * @{
00703   */
00704 /* Note: Other measurement paths to internal channels may be available        */
00705 /*       (connections to other peripherals).                                  */
00706 /*       If they are not listed below, they do not require any specific       */
00707 /*       path enable. In this case, Access to measurement path is done        */
00708 /*       only by selecting the corresponding ADC internal channel.            */
00709 #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement pathes all disabled */
00710 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00711 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00712 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00713 /**
00714   * @}
00715   */
00716
00717 /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
00718   * @{
00719   */
00720 #define LL_ADC_BOOST_MODE_6MHZ25   (0x00000000UL)                                            /*!< Boost mode is configured for frequency <= 6.25Mhz           */
00721 #define LL_ADC_BOOST_MODE_12MHZ5   (                                        ADC_CR_BOOST_0)  /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */
00722 #define LL_ADC_BOOST_MODE_20MHZ    (                       ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz   */
00723 #define LL_ADC_BOOST_MODE_25MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 20Mhz   < frequency <= 25Mhz   */
00724 #define LL_ADC_BOOST_MODE_50MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)  /*!< Boost mode is configured for frequency > 25Mhz              */
00725 /**
00726   * @}
00727   */
00728
00729 /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY  ADC instance - Calibration mode for offset and linearity
00730   * @{
00731   */
00732 #define LL_ADC_CALIB_OFFSET                (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)                      /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */
00733 #define LL_ADC_CALIB_LINEARITY             (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)                   /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */
00734 #define LL_ADC_CALIB_OFFSET_LINEARITY      (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */
00735 /**
00736   * @}
00737   */
00738
00739 /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD  ADC instance - Calibration linearity words
00740   * @{
00741   */
00742 #define LL_ADC_CALIB_LINEARITY_WORD1       (ADC_CR_LINCALRDYW1)    /*!< ADC calibration linearity word 1 */
00743 #define LL_ADC_CALIB_LINEARITY_WORD2       (ADC_CR_LINCALRDYW2)    /*!< ADC calibration linearity word 2 */
00744 #define LL_ADC_CALIB_LINEARITY_WORD3       (ADC_CR_LINCALRDYW3)    /*!< ADC calibration linearity word 3 */
00745 #define LL_ADC_CALIB_LINEARITY_WORD4       (ADC_CR_LINCALRDYW4)    /*!< ADC calibration linearity word 4 */
00746 #define LL_ADC_CALIB_LINEARITY_WORD5       (ADC_CR_LINCALRDYW5)    /*!< ADC calibration linearity word 5 */
00747 #define LL_ADC_CALIB_LINEARITY_WORD6       (ADC_CR_LINCALRDYW6)    /*!< ADC calibration linearity word 6 */
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00753   * @{
00754   */
00755 #define LL_ADC_RESOLUTION_16B              (0x00000000UL)                                   /*!< ADC resolution 16 bits */
00756 #define LL_ADC_RESOLUTION_14B              (                                ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
00757 #define LL_ADC_RESOLUTION_12B              (               ADC_CFGR_RES_1                 ) /*!< ADC resolution 12 bits */
00758 #define LL_ADC_RESOLUTION_10B              (               ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
00759 #if defined (ADC_VER_V5_3)
00760 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution  8 bits */
00761 #else
00762 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2                                ) /*!< ADC resolution  8 bits */
00763 #endif
00764 /**
00765   * @}
00766   */
00767
00768 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT   ADC left Shift
00769   * @{
00770   */
00771 #define LL_ADC_LEFT_BIT_SHIFT_NONE  (0x00000000UL)                                                                       /*!< ADC no bit shift left applied on the final ADC convesion data */
00772 #define LL_ADC_LEFT_BIT_SHIFT_1     (ADC_CFGR2_LSHIFT_0)                                                                 /*!< ADC 1 bit shift left applied on the final ADC convesion data */
00773 #define LL_ADC_LEFT_BIT_SHIFT_2     (ADC_CFGR2_LSHIFT_1)                                                                 /*!< ADC 2 bits shift left applied on the final ADC convesion data */
00774 #define LL_ADC_LEFT_BIT_SHIFT_3     (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 3 bits shift left applied on the final ADC convesion data */
00775 #define LL_ADC_LEFT_BIT_SHIFT_4     (ADC_CFGR2_LSHIFT_2)                                                                 /*!< ADC 4 bits shift left applied on the final ADC convesion data */
00776 #define LL_ADC_LEFT_BIT_SHIFT_5     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 5 bits shift left applied on the final ADC convesion data */
00777 #define LL_ADC_LEFT_BIT_SHIFT_6     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 6 bits shift left applied on the final ADC convesion data */
00778 #define LL_ADC_LEFT_BIT_SHIFT_7     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 7 bits shift left applied on the final ADC convesion data */
00779 #define LL_ADC_LEFT_BIT_SHIFT_8     (ADC_CFGR2_LSHIFT_3)                                                                 /*!< ADC 8 bits shift left applied on the final ADC convesion data */
00780 #define LL_ADC_LEFT_BIT_SHIFT_9     (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 9 bits shift left applied on the final ADC convesion data */
00781 #define LL_ADC_LEFT_BIT_SHIFT_10    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 10 bits shift left applied on the final ADC convesion data */
00782 #define LL_ADC_LEFT_BIT_SHIFT_11    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 11 bits shift left applied on the final ADC convesion data */
00783 #define LL_ADC_LEFT_BIT_SHIFT_12    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)                                            /*!< ADC 12 bits shift left applied on the final ADC convesion data */
00784 #define LL_ADC_LEFT_BIT_SHIFT_13    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 13 bits shift left applied on the final ADC convesion data */
00785 #define LL_ADC_LEFT_BIT_SHIFT_14    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                       /*!< ADC 14 bits shift left applied on the final ADC convesion data */
00786 #define LL_ADC_LEFT_BIT_SHIFT_15    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)  /*!< ADC 15 bits shift left applied on the final ADC convesion data */
00787 /**
00788   * @}
00789   */
00790
00791 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00792   * @{
00793   */
00794 #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */
00795 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
00801   * @{
00802   */
00803 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00804 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00805 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00806 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
00812   * @{
00813   */
00814 #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE   (0x00000000UL)   /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
00815 #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE    (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift
00821   * @{
00822   */
00823 #define LL_ADC_OFFSET_RSHIFT_DISABLE   (0x00000000UL)      /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
00824 #define LL_ADC_OFFSET_RSHIFT_ENABLE    (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */
00825 /**
00826   * @}
00827   */
00828 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00829   * @{
00830   */
00831 #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
00832 #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
00833 #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00839   * @{
00840   */
00841 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00842 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00843 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00844 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00845 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00846 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00847 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00848 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00849 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00850 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00851 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00852 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00853 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00854 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00855 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00856 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00857 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00858 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00859 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00860 #define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
00861 #if defined(ADC3)
00862 /*!< ADC3 is defined only in the case of STM32H7XX */
00863 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
00864 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
00865 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
00866 #else
00867 /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
00868 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */
00869 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2. */
00870 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2. */
00871 #endif
00872 #define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
00873 #define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
00874 #if defined(DAC2)
00875 /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
00876 #define LL_ADC_CHANNEL_DAC2CH1_ADC2        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
00877 #endif
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00883   * @{
00884   */
00885 #define LL_ADC_REG_TRIG_SOFTWARE          (0x00000000UL)                                                                                                    /*!< ADC group regular conversion trigger internal: SW start. */
00886 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                   /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00887 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2      (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00888 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3      (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00889 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2      (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00890 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
00891 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00892 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
00893 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
00894 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
00895 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
00896 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
00897 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
00898 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
00899 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
00900 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
00901 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00902 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1    (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
00903 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
00904 #define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
00905 #define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
00906 #define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00912   * @{
00913   */
00914 #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
00915 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
00916 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00917 /**
00918   * @}
00919   */
00920
00921 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00922   * @{
00923   */
00924 #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */
00925 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00926 /**
00927   * @}
00928   */
00929
00930 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE  ADC group regular - Data transfer mode of ADC conversion data
00931   * @{
00932   */
00933 #define LL_ADC_REG_DR_TRANSFER             (0x00000000UL)                        /*!< ADC conversions are transferred to DR rigister */
00934 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00935 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00936 #define LL_ADC_REG_DFSDM_TRANSFER          (ADC_CFGR_DMNGT_1                   ) /*!< ADC conversion data are transferred to DFSDM */
00937 /**
00938   * @}
00939   */
00940
00941 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00942   * @{
00943   */
00944 #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */
00945 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
00951   * @{
00952   */
00953 #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00954 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00955 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00956 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00957 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00958 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00959 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00960 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00961 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
00962 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
00963 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
00964 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
00965 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
00966 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
00967 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
00968 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
00969 /**
00970   * @}
00971   */
00972
00973 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
00974   * @{
00975   */
00976 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */
00977 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00978 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
00979 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
00980 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
00981 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
00982 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
00983 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
00984 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
00985 /**
00986   * @}
00987   */
00988
00989 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00990   * @{
00991   */
00992 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00993 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00994 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00995 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00996 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00997 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00998 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00999 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
01000 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
01001 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
01002 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
01003 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
01004 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
01005 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
01006 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
01007 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
01008 /**
01009   * @}
01010   */
01011
01012 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
01013   * @{
01014   */
01015 #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                         /*!< ADC group injected conversion trigger internal: SW start. */
01016 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                        /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
01017 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01018 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
01019 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01020 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01021 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
01022 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
01023 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01024 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
01025 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
01026 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
01027 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01028 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                            /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
01029 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01030 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
01031 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
01032 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                                   /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
01033 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
01034 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
01035 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
01036 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
01037 /**
01038   * @}
01039   */
01040
01041 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
01042   * @{
01043   */
01044 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
01045 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
01046 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
01047 /**
01048   * @}
01049   */
01050
01051 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
01052   * @{
01053   */
01054 #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
01055 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
01056 /**
01057   * @}
01058   */
01059
01060 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
01061   * @{
01062   */
01063 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
01064 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
01065 #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
01066 /**
01067   * @}
01068   */
01069
01070 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
01071   * @{
01072   */
01073 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
01074 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
01075 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
01076 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
01077 /**
01078   * @}
01079   */
01080
01081 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
01082   * @{
01083   */
01084 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */
01085 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
01086 /**
01087   * @}
01088   */
01089
01090 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
01091   * @{
01092   */
01093 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
01094 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
01095 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
01096 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
01097 /**
01098   * @}
01099   */
01100
01101 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
01102   * @{
01103   */
01104 #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                              /*!< Sampling time 1.5 ADC clock cycles */
01105 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
01106 #define LL_ADC_SAMPLINGTIME_8CYCLES_5      (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 8.5 ADC clock cycles */
01107 #define LL_ADC_SAMPLINGTIME_16CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */
01108 #define LL_ADC_SAMPLINGTIME_32CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 32.5 ADC clock cycles */
01109 #define LL_ADC_SAMPLINGTIME_64CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */
01110 #define LL_ADC_SAMPLINGTIME_387CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 387.5 ADC clock cycles */
01111 #define LL_ADC_SAMPLINGTIME_810CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */
01112 /**
01113   * @}
01114   */
01115
01116 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
01117   * @{
01118   */
01119 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
01120 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
01121 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
01122 /**
01123   * @}
01124   */
01125
01126 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
01127   * @{
01128   */
01129 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
01130 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
01131 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
01132 /**
01133   * @}
01134   */
01135
01136 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
01137   * @{
01138   */
01139 #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */
01140 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
01141 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
01142 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
01143 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
01144 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
01145 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
01146 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
01147 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
01148 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
01149 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
01150 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
01151 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
01152 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
01153 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
01154 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
01155 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
01156 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
01157 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
01158 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
01159 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
01160 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
01161 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
01162 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
01163 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
01164 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
01165 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
01166 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
01167 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
01168 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
01169 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
01170 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
01171 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
01172 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
01173 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
01174 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
01175 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
01176 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
01177 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
01178 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
01179 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
01180 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
01181 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
01182 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
01183 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
01184 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
01185 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
01186 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
01187 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
01188 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
01189 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
01190 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
01191 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
01192 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
01193 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
01194 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
01195 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
01196 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
01197 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
01198 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
01199 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
01200 #define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
01201 #define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
01202 #define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
01203 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
01204 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
01205 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
01206 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
01207 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
01208 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
01209 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
01210 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
01211 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
01212 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01213 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01214 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01215 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01216 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01217 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01218 /**
01219   * @}
01220   */
01221
01222 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
01223   * @{
01224   */
01225 #define LL_ADC_AWD_THRESHOLD_HIGH          (0x1UL)                     /*!< ADC analog watchdog threshold high */
01226 #define LL_ADC_AWD_THRESHOLD_LOW           (0x0UL)                     /*!< ADC analog watchdog threshold low */
01227 /**
01228   * @}
01229   */
01230
01231 /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
01232   * @{
01233   */
01234 #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */
01235 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
01236 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01237 #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
01238 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01239 /**
01240   * @}
01241   */
01242
01243 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
01244   * @{
01245   */
01246 #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
01247 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
01253   * @{
01254   */
01255 #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
01256 #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
01257 #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
01258 #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
01259 #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
01260 #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
01261 #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
01262 #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
01263 #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
01264 #define LL_ADC_OVS_SHIFT_RIGHT_9           (ADC_CFGR2_OVSS_3                                       | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
01265 #define LL_ADC_OVS_SHIFT_RIGHT_10          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
01266 #define LL_ADC_OVS_SHIFT_RIGHT_11          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
01267 /**
01268   * @}
01269   */
01270
01271 /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
01272   * @{
01273   */
01274 #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                                      /*!< ADC dual mode disabled (ADC independent mode) */
01275 #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
01276 #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
01277 #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
01278 #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
01279 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
01280 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
01281 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
01282 /**
01283   * @}
01284   */
01285
01286 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
01287   * @{
01288   */
01289 #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                      /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
01290 #define LL_ADC_MULTI_REG_DMA_RES_32_10B      (ADC_CCR_DAMDF_1                  ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
01291 #define LL_ADC_MULTI_REG_DMA_RES_8B          (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
01292 /**
01293   * @}
01294   */
01295
01296 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
01297   * @{
01298   */
01299 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5           (0x00000000UL)                                                          /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution                    */
01300 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5          (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution                   */
01301 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5          (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution                   */
01302 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5          (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
01303 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS   (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles  for 8 bits resolution               */
01304 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5          (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution       */
01305 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution               */
01306 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution            */
01307 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5          (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution         */
01308 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution               */
01309 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5          (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution               */
01310 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution                 */
01311 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution           */
01312 /**
01313   * @}
01314   */
01315
01316 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
01317   * @{
01318   */
01319 #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
01320 #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
01321 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
01322 /**
01323   * @}
01324   */
01325
01326
01327
01328 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
01329   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
01330   *         not timeout values.
01331   *         For details on delays values, refer to descriptions in source code
01332   *         above each literal definition.
01333   * @{
01334   */
01335
01336 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
01337 /*       not timeout values.                                                  */
01338 /*       Timeout values for ADC operations are dependent to device clock      */
01339 /*       configuration (system clock versus ADC clock),                       */
01340 /*       and therefore must be defined in user application.                   */
01341 /*       Indications for estimation of ADC timeout delays, for this           */
01342 /*       STM32 serie:                                                         */
01343 /*       - ADC calibration time: maximum delay is 16384/fADC.                   */
01344 /*         (refer to device datasheet, parameter "tCAL")                      */
01345 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
01346 /*         (refer to device datasheet, parameter "tSTAB")                     */
01347 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
01348 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
01349 /*         cycles                                                             */
01350 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
01351 /*         configuration.                                                     */
01352 /*         (refer to device reference manual, section "Timing")               */
01353
01354 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
01355 /* Delay set to maximum value (refer to device datasheet,                     */
01356 /* parameter "tADCVREG_STUP").                                                */
01357 /* Unit: us                                                                   */
01358 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
01359
01360 /* Delay for internal voltage reference stabilization time.                   */
01361 /* Delay set to maximum value (refer to device datasheet,                     */
01362 /* parameter "ts_vrefint").                                                   */
01363 /* Unit: us                                                                   */
01364 #define LL_ADC_DELAY_VREFINT_STAB_US       (5UL)  /*!< Delay for internal voltage reference stabilization time */
01365
01366 /* Delay for temperature sensor stabilization time.                           */
01367 /* Literal set to maximum value (refer to device datasheet,                   */
01368 /* parameter "tSTART_RUN").                                                   */
01369 /* Unit: us                                                                   */
01370 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 26UL)  /*!< Delay for temperature sensor stabilization time */
01371
01372 /* Delay required between ADC end of calibration and ADC enable.              */
01373 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
01374 /*       are required between ADC end of calibration and ADC enable.          */
01375 /*       Wait time can be computed in user application by waiting for the     */
01376 /*       equivalent number of CPU cycles, by taking into account              */
01377 /*       ratio of CPU clock versus ADC clock prescalers.                      */
01378 /* Unit: ADC clock cycles.                                                    */
01379 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */
01380
01381 /* Fixed timeout value for ADC linearity word bit set/clear delay.                         */
01382 /* Values defined to be higher than worst cases: low clock frequency,                      */
01383 /* maximum prescalers.                                                                     */
01384 /* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value                         */
01385 /* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB  */
01386 /*           6 / 4577 = 1,311ms                                                            */
01387 /* At maximum CPU speed (400 MHz), this means                                              */
01388 /*    3.58 * 400 MHz = 524400 CPU cycles                                                   */
01389 #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT         (524400UL)      /*!< ADC linearity set/clear bit delay */
01390
01391 /**
01392   * @}
01393   */
01394
01395 /**
01396   * @}
01397   */
01398
01399
01400 /* Exported macro ------------------------------------------------------------*/
01401 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
01402   * @{
01403   */
01404
01405 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
01406   * @{
01407   */
01408
01409 /**
01410   * @brief  Write a value in ADC register
01411   * @param  __INSTANCE__ ADC Instance
01412   * @param  __REG__ Register to be written
01413   * @param  __VALUE__ Value to be written in the register
01414   * @retval None
01415   */
01416 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01417
01418 /**
01419   * @brief  Read a value in ADC register
01420   * @param  __INSTANCE__ ADC Instance
01421   * @param  __REG__ Register to be read
01422   * @retval Register value
01423   */
01424 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01425 /**
01426   * @}
01427   */
01428
01429 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
01430   * @{
01431   */
01432
01433 /**
01434   * @brief  Helper macro to get ADC channel number in decimal format
01435   *         from literals LL_ADC_CHANNEL_x.
01436   * @note   Example:
01437   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
01438   *           will return decimal number "4".
01439   * @note   The input can be a value from functions where a channel
01440   *         number is returned, either defined with number
01441   *         or with bitfield (only one bit must be set).
01442   * @param  __CHANNEL__ This parameter can be one of the following values:
01443   *         @arg @ref LL_ADC_CHANNEL_0           (3)
01444   *         @arg @ref LL_ADC_CHANNEL_1           (3)
01445   *         @arg @ref LL_ADC_CHANNEL_2           (3)
01446   *         @arg @ref LL_ADC_CHANNEL_3           (3)
01447   *         @arg @ref LL_ADC_CHANNEL_4           (3)
01448   *         @arg @ref LL_ADC_CHANNEL_5           (3)
01449   *         @arg @ref LL_ADC_CHANNEL_6
01450   *         @arg @ref LL_ADC_CHANNEL_7
01451   *         @arg @ref LL_ADC_CHANNEL_8
01452   *         @arg @ref LL_ADC_CHANNEL_9
01453   *         @arg @ref LL_ADC_CHANNEL_10
01454   *         @arg @ref LL_ADC_CHANNEL_11
01455   *         @arg @ref LL_ADC_CHANNEL_12
01456   *         @arg @ref LL_ADC_CHANNEL_13
01457   *         @arg @ref LL_ADC_CHANNEL_14
01458   *         @arg @ref LL_ADC_CHANNEL_15
01459   *         @arg @ref LL_ADC_CHANNEL_16
01460   *         @arg @ref LL_ADC_CHANNEL_17
01461   *         @arg @ref LL_ADC_CHANNEL_18
01462   *         @arg @ref LL_ADC_CHANNEL_19
01463   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01464   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01465   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01466   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01467   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01468   *
01469   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01470   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01471   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01472   *             Other channels are slow channels (conversion rate: refer to reference manual).
01473   * @retval Value between Min_Data=0 and Max_Data=18
01474   */
01475 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
01476   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \
01477    ? (                                                                                     \
01478        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
01479      )                                                                                     \
01480    :                                                                                       \
01481    (                                                                                       \
01482        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
01483    )                                                                                       \
01484   )
01485
01486 /**
01487   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01488   *         from number in decimal format.
01489   * @note   Example:
01490   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01491   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01492   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01493   * @retval Returned value can be one of the following values:
01494   *         @arg @ref LL_ADC_CHANNEL_0           (3)
01495   *         @arg @ref LL_ADC_CHANNEL_1           (3)
01496   *         @arg @ref LL_ADC_CHANNEL_2           (3)
01497   *         @arg @ref LL_ADC_CHANNEL_3           (3)
01498   *         @arg @ref LL_ADC_CHANNEL_4           (3)
01499   *         @arg @ref LL_ADC_CHANNEL_5           (3)
01500   *         @arg @ref LL_ADC_CHANNEL_6
01501   *         @arg @ref LL_ADC_CHANNEL_7
01502   *         @arg @ref LL_ADC_CHANNEL_8
01503   *         @arg @ref LL_ADC_CHANNEL_9
01504   *         @arg @ref LL_ADC_CHANNEL_10
01505   *         @arg @ref LL_ADC_CHANNEL_11
01506   *         @arg @ref LL_ADC_CHANNEL_12
01507   *         @arg @ref LL_ADC_CHANNEL_13
01508   *         @arg @ref LL_ADC_CHANNEL_14
01509   *         @arg @ref LL_ADC_CHANNEL_15
01510   *         @arg @ref LL_ADC_CHANNEL_16
01511   *         @arg @ref LL_ADC_CHANNEL_17
01512   *         @arg @ref LL_ADC_CHANNEL_18
01513   *         @arg @ref LL_ADC_CHANNEL_19
01514   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01515   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01516   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01517   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01518   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01519   *
01520   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01521   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01522   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01523   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
01524   *         (1, 2) For ADC channel read back from ADC register,
01525   *                comparison with internal channel parameter to be done
01526   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01527   */
01528 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \
01529   (((__DECIMAL_NB__) <= 9UL)                                                                            \
01530    ? (                                                                                                  \
01531        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
01532        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \
01533        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
01534      )                                                                                                  \
01535    :                                                                                                    \
01536    (                                                                                                    \
01537        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
01538        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \
01539        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
01540    )                                                                                                    \
01541   )
01542
01543 /**
01544   * @brief  Helper macro to determine whether the selected channel
01545   *         corresponds to literal definitions of driver.
01546   * @note   The different literal definitions of ADC channels are:
01547   *         - ADC internal channel:
01548   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01549   *         - ADC external channel (channel connected to a GPIO pin):
01550   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01551   * @note   The channel parameter must be a value defined from literal
01552   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01553   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01554   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01555   *         must not be a value from functions where a channel number is
01556   *         returned from ADC registers,
01557   *         because internal and external channels share the same channel
01558   *         number in ADC registers. The differentiation is made only with
01559   *         parameters definitions of driver.
01560   * @param  __CHANNEL__ This parameter can be one of the following values:
01561   *         @arg @ref LL_ADC_CHANNEL_0           (3)
01562   *         @arg @ref LL_ADC_CHANNEL_1           (3)
01563   *         @arg @ref LL_ADC_CHANNEL_2           (3)
01564   *         @arg @ref LL_ADC_CHANNEL_3           (3)
01565   *         @arg @ref LL_ADC_CHANNEL_4           (3)
01566   *         @arg @ref LL_ADC_CHANNEL_5           (3)
01567   *         @arg @ref LL_ADC_CHANNEL_6
01568   *         @arg @ref LL_ADC_CHANNEL_7
01569   *         @arg @ref LL_ADC_CHANNEL_8
01570   *         @arg @ref LL_ADC_CHANNEL_9
01571   *         @arg @ref LL_ADC_CHANNEL_10
01572   *         @arg @ref LL_ADC_CHANNEL_11
01573   *         @arg @ref LL_ADC_CHANNEL_12
01574   *         @arg @ref LL_ADC_CHANNEL_13
01575   *         @arg @ref LL_ADC_CHANNEL_14
01576   *         @arg @ref LL_ADC_CHANNEL_15
01577   *         @arg @ref LL_ADC_CHANNEL_16
01578   *         @arg @ref LL_ADC_CHANNEL_17
01579   *         @arg @ref LL_ADC_CHANNEL_18
01580   *         @arg @ref LL_ADC_CHANNEL_19
01581   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01582   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01583   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01584   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01585   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01586   *
01587   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01588   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01589   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01590   *             Other channels are slow channels (conversion rate: refer to reference manual).
01591   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01592   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01593   */
01594 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01595   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
01596
01597 /**
01598   * @brief  Helper macro to convert a channel defined from parameter
01599   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01600   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01601   *         to its equivalent parameter definition of a ADC external channel
01602   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01603   * @note   The channel parameter can be, additionally to a value
01604   *         defined from parameter definition of a ADC internal channel
01605   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01606   *         a value defined from parameter definition of
01607   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01608   *         or a value from functions where a channel number is returned
01609   *         from ADC registers.
01610   * @param  __CHANNEL__ This parameter can be one of the following values:
01611   *         @arg @ref LL_ADC_CHANNEL_0           (3)
01612   *         @arg @ref LL_ADC_CHANNEL_1           (3)
01613   *         @arg @ref LL_ADC_CHANNEL_2           (3)
01614   *         @arg @ref LL_ADC_CHANNEL_3           (3)
01615   *         @arg @ref LL_ADC_CHANNEL_4           (3)
01616   *         @arg @ref LL_ADC_CHANNEL_5           (3)
01617   *         @arg @ref LL_ADC_CHANNEL_6
01618   *         @arg @ref LL_ADC_CHANNEL_7
01619   *         @arg @ref LL_ADC_CHANNEL_8
01620   *         @arg @ref LL_ADC_CHANNEL_9
01621   *         @arg @ref LL_ADC_CHANNEL_10
01622   *         @arg @ref LL_ADC_CHANNEL_11
01623   *         @arg @ref LL_ADC_CHANNEL_12
01624   *         @arg @ref LL_ADC_CHANNEL_13
01625   *         @arg @ref LL_ADC_CHANNEL_14
01626   *         @arg @ref LL_ADC_CHANNEL_15
01627   *         @arg @ref LL_ADC_CHANNEL_16
01628   *         @arg @ref LL_ADC_CHANNEL_17
01629   *         @arg @ref LL_ADC_CHANNEL_18
01630   *         @arg @ref LL_ADC_CHANNEL_19
01631   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01632   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01633   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01634   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01635   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01636   *
01637   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01638   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01639   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01640   *             Other channels are slow channels (conversion rate: refer to reference manual).
01641   * @retval Returned value can be one of the following values:
01642   *         @arg @ref LL_ADC_CHANNEL_0
01643   *         @arg @ref LL_ADC_CHANNEL_1
01644   *         @arg @ref LL_ADC_CHANNEL_2
01645   *         @arg @ref LL_ADC_CHANNEL_3
01646   *         @arg @ref LL_ADC_CHANNEL_4
01647   *         @arg @ref LL_ADC_CHANNEL_5
01648   *         @arg @ref LL_ADC_CHANNEL_6
01649   *         @arg @ref LL_ADC_CHANNEL_7
01650   *         @arg @ref LL_ADC_CHANNEL_8
01651   *         @arg @ref LL_ADC_CHANNEL_9
01652   *         @arg @ref LL_ADC_CHANNEL_10
01653   *         @arg @ref LL_ADC_CHANNEL_11
01654   *         @arg @ref LL_ADC_CHANNEL_12
01655   *         @arg @ref LL_ADC_CHANNEL_13
01656   *         @arg @ref LL_ADC_CHANNEL_14
01657   *         @arg @ref LL_ADC_CHANNEL_15
01658   *         @arg @ref LL_ADC_CHANNEL_16
01659   *         @arg @ref LL_ADC_CHANNEL_17
01660   *         @arg @ref LL_ADC_CHANNEL_18
01661   *         @arg @ref LL_ADC_CHANNEL_19
01662   */
01663 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01664   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01665
01666 /**
01667   * @brief  Helper macro to determine whether the internal channel
01668   *         selected is available on the ADC instance selected.
01669   * @note   The channel parameter must be a value defined from parameter
01670   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01671   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01672   *         must not be a value defined from parameter definition of
01673   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01674   *         or a value from functions where a channel number is
01675   *         returned from ADC registers,
01676   *         because internal and external channels share the same channel
01677   *         number in ADC registers. The differentiation is made only with
01678   *         parameters definitions of driver.
01679   * @param  __ADC_INSTANCE__ ADC instance
01680   * @param  __CHANNEL__ This parameter can be one of the following values:
01681   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01682   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01683   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01684   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01685   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01686   *
01687   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01688   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.
01689   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01690   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01691   */
01692 #if defined(ADC3)
01693 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01694   ((((__ADC_INSTANCE__) == ADC2)                                               \
01695     &&(                                                                        \
01696        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \
01697        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                          \
01698       )                                                                        \
01699    )                                                                           \
01700    ||                                                                          \
01701    (((__ADC_INSTANCE__) == ADC3)                                               \
01702     &&(                                                                        \
01703        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \
01704        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \
01705        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
01706       )                                                                        \
01707    )                                                                           \
01708   )
01709 #else
01710 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01711   ((((__ADC_INSTANCE__) == ADC2)                                               \
01712     &&(                                                                        \
01713        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \
01714        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) ||                       \
01715        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \
01716        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \
01717        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
01718       )                                                                        \
01719    )                                                                           \
01720   )
01721 #endif
01722
01723 /**
01724   * @brief  Helper macro to define ADC analog watchdog parameter:
01725   *         define a single channel to monitor with analog watchdog
01726   *         from sequencer channel and groups definition.
01727   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01728   *         Example:
01729   *           LL_ADC_SetAnalogWDMonitChannels(
01730   *             ADC1, LL_ADC_AWD1,
01731   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01732   * @param  __CHANNEL__ This parameter can be one of the following values:
01733   *         @arg @ref LL_ADC_CHANNEL_0           (3)
01734   *         @arg @ref LL_ADC_CHANNEL_1           (3)
01735   *         @arg @ref LL_ADC_CHANNEL_2           (3)
01736   *         @arg @ref LL_ADC_CHANNEL_3           (3)
01737   *         @arg @ref LL_ADC_CHANNEL_4           (3)
01738   *         @arg @ref LL_ADC_CHANNEL_5           (3)
01739   *         @arg @ref LL_ADC_CHANNEL_6
01740   *         @arg @ref LL_ADC_CHANNEL_7
01741   *         @arg @ref LL_ADC_CHANNEL_8
01742   *         @arg @ref LL_ADC_CHANNEL_9
01743   *         @arg @ref LL_ADC_CHANNEL_10
01744   *         @arg @ref LL_ADC_CHANNEL_11
01745   *         @arg @ref LL_ADC_CHANNEL_12
01746   *         @arg @ref LL_ADC_CHANNEL_13
01747   *         @arg @ref LL_ADC_CHANNEL_14
01748   *         @arg @ref LL_ADC_CHANNEL_15
01749   *         @arg @ref LL_ADC_CHANNEL_16
01750   *         @arg @ref LL_ADC_CHANNEL_17
01751   *         @arg @ref LL_ADC_CHANNEL_18
01752   *         @arg @ref LL_ADC_CHANNEL_19
01753   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01754   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01755   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
01756   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01757   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01758   *
01759   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01760   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
01761   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
01762   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
01763   *         (1, 2) For ADC channel read back from ADC register,
01764   *                comparison with internal channel parameter to be done
01765   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01766   * @param  __GROUP__ This parameter can be one of the following values:
01767   *         @arg @ref LL_ADC_GROUP_REGULAR
01768   *         @arg @ref LL_ADC_GROUP_INJECTED
01769   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01770   * @retval Returned value can be one of the following values:
01771   *         @arg @ref LL_ADC_AWD_DISABLE
01772   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
01773   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
01774   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01775   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
01776   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
01777   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01778   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
01779   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
01780   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01781   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
01782   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
01783   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01784   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
01785   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
01786   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01787   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
01788   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
01789   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01790   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
01791   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
01792   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01793   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
01794   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
01795   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01796   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
01797   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
01798   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
01799   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
01800   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
01801   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
01802   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
01803   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
01804   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
01805   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
01806   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
01807   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
01808   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
01809   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
01810   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
01811   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
01812   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
01813   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
01814   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
01815   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
01816   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
01817   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
01818   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
01819   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
01820   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
01821   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
01822   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
01823   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
01824   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
01825   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
01826   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
01827   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
01828   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
01829   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
01830   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
01831   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
01832   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
01833   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
01834   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
01835   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
01836   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
01837   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
01838   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)
01839   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)
01840   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)
01841   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
01842   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
01843   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
01844   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)
01845   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)
01846   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)
01847   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)
01848   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)
01849   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)
01850   *
01851   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
01852   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
01853   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.
01854   */
01855 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01856   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
01857    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
01858    :                                                                                                      \
01859    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
01860    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
01861    :                                                                                                      \
01862    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
01863   )
01864
01865 /**
01866   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
01867   *         or low in function of ADC resolution, when ADC resolution is
01868   *         different of 16 bits.
01869   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
01870   *         Example, with a ADC resolution of 8 bits, to set the value of
01871   *         analog watchdog threshold high (on 18 bits):
01872   *           LL_ADC_SetAnalogWDThresholds
01873   *            (< ADCx param >,
01874   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)
01875   *            );
01876   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01877   *         @arg @ref LL_ADC_RESOLUTION_16B
01878   *         @arg @ref LL_ADC_RESOLUTION_14B
01879   *         @arg @ref LL_ADC_RESOLUTION_12B
01880   *         @arg @ref LL_ADC_RESOLUTION_10B
01881   *         @arg @ref LL_ADC_RESOLUTION_8B
01882   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
01883   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
01884   */
01885 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
01886   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01887
01888 /**
01889   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
01890   *         or low in function of ADC resolution, when ADC resolution is
01891   *         different of 16 bits.
01892   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01893   *         Example, with a ADC resolution of 8 bits, to get the value of
01894   *         analog watchdog threshold high (on 18 bits):
01895   *           < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
01896   *            (LL_ADC_RESOLUTION_8B,
01897   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
01898   *            );
01899   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01900   *         @arg @ref LL_ADC_RESOLUTION_16B
01901   *         @arg @ref LL_ADC_RESOLUTION_14B
01902   *         @arg @ref LL_ADC_RESOLUTION_12B
01903   *         @arg @ref LL_ADC_RESOLUTION_10B
01904   *         @arg @ref LL_ADC_RESOLUTION_8B
01905   * @param  __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
01906   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
01907   */
01908 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
01909   ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01910
01911 /**
01912   * @brief  Helper macro to set the ADC calibration value with both single ended
01913   *         and differential modes calibration factors concatenated.
01914   * @note   To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
01915   *         Example, to set calibration factors single ended to 0x55
01916   *         and differential ended to 0x2A:
01917   *           LL_ADC_SetCalibrationOffsetFactor(
01918   *             ADC1,
01919   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
01920   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
01921   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
01922   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01923   */
01924 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
01925   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
01926
01927 /**
01928   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01929   *         or ADC slave from raw value with both ADC conversion data concatenated.
01930   * @note   This macro is intended to be used when multimode transfer by DMA
01931   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
01932   *         In this case the transferred data need to processed with this macro
01933   *         to separate the conversion data of ADC master and ADC slave.
01934   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
01935   *         @arg @ref LL_ADC_MULTI_MASTER
01936   *         @arg @ref LL_ADC_MULTI_SLAVE
01937   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
01938   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01939   */
01940 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
01941   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
01942
01943 /**
01944   * @brief  Helper macro to select, from a ADC instance, to which ADC instance
01945   *         it has a dependence in multimode (ADC master of the corresponding
01946   *         ADC common instance).
01947   * @note   In case of device with multimode available and a mix of
01948   *         ADC instances compliant and not compliant with multimode feature,
01949   *         ADC instances not compliant with multimode feature are
01950   *         considered as master instances (do not depend to
01951   *         any other ADC instance).
01952   * @param  __ADCx__ ADC instance
01953   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
01954   */
01955 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
01956   ( ( ((__ADCx__) == ADC2)                                                     \
01957     )?                                                                         \
01958      (ADC1)                                                                    \
01959      :                                                                         \
01960      (__ADCx__)                                                                \
01961   )
01962
01963 /**
01964   * @brief  Helper macro to select the ADC common instance
01965   *         to which is belonging the selected ADC instance.
01966   * @note   ADC common register instance can be used for:
01967   *         - Set parameters common to several ADC instances
01968   *         - Multimode (for devices with several ADC instances)
01969   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01970   * @param  __ADCx__ ADC instance
01971   * @retval ADC common register instance
01972   */
01973 #if defined(ADC3_COMMON)
01974 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01975   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
01976     ? (                                                                        \
01977        (ADC12_COMMON)                                                          \
01978       )                                                                        \
01979       :                                                                        \
01980       (                                                                        \
01981        (ADC3_COMMON)                                                           \
01982       )                                                                        \
01983   )
01984 #else
01985 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)   (ADC12_COMMON)
01986 #endif
01987
01988 /**
01989   * @brief  Helper macro to check if all ADC instances sharing the same
01990   *         ADC common instance are disabled.
01991   * @note   This check is required by functions with setting conditioned to
01992   *         ADC state:
01993   *         All ADC instances of the ADC common group must be disabled.
01994   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01995   * @note   On devices with only 1 ADC common instance, parameter of this macro
01996   *         is useless and can be ignored (parameter kept for compatibility
01997   *         with devices featuring several ADC common instances).
01998   * @param  __ADCXY_COMMON__ ADC common instance
01999   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02000   * @retval Value "0" if all ADC instances sharing the same ADC common instance
02001   *         are disabled.
02002   *         Value "1" if at least one ADC instance sharing the same ADC common instance
02003   *         is enabled.
02004   */
02005 #if defined(ADC3_COMMON)
02006 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02007   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
02008     ? (                                                                        \
02009        (LL_ADC_IsEnabled(ADC1) |                                               \
02010         LL_ADC_IsEnabled(ADC2)  )                                              \
02011       )                                                                        \
02012       :                                                                        \
02013       (                                                                        \
02014        (LL_ADC_IsEnabled(ADC3))                                                \
02015       )                                                                        \
02016   )
02017 #else
02018 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02019                         (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
02020 #endif
02021
02022 /**
02023   * @brief  Helper macro to define the ADC conversion data full-scale digital
02024   *         value corresponding to the selected ADC resolution.
02025   * @note   ADC conversion data full-scale corresponds to voltage range
02026   *         determined by analog voltage references Vref+ and Vref-
02027   *         (refer to reference manual).
02028   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02029   *         @arg @ref LL_ADC_RESOLUTION_16B
02030   *         @arg @ref LL_ADC_RESOLUTION_14B
02031   *         @arg @ref LL_ADC_RESOLUTION_12B
02032   *         @arg @ref LL_ADC_RESOLUTION_10B
02033   *         @arg @ref LL_ADC_RESOLUTION_8B
02034   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
02035   */
02036 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
02037   (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
02038
02039 /**
02040   * @brief  Helper macro to convert the ADC conversion data from
02041   *         a resolution to another resolution.
02042   * @param  __DATA__ ADC conversion data to be converted
02043   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
02044   *         This parameter can be one of the following values:
02045   *         @arg @ref LL_ADC_RESOLUTION_16B
02046   *         @arg @ref LL_ADC_RESOLUTION_14B
02047   *         @arg @ref LL_ADC_RESOLUTION_12B
02048   *         @arg @ref LL_ADC_RESOLUTION_10B
02049   *         @arg @ref LL_ADC_RESOLUTION_8B
02050   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
02051   *         This parameter can be one of the following values:
02052   *         @arg @ref LL_ADC_RESOLUTION_16B
02053   *         @arg @ref LL_ADC_RESOLUTION_14B
02054   *         @arg @ref LL_ADC_RESOLUTION_12B
02055   *         @arg @ref LL_ADC_RESOLUTION_10B
02056   *         @arg @ref LL_ADC_RESOLUTION_8B
02057   * @retval ADC conversion data to the requested resolution
02058   */
02059 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
02060                                          __ADC_RESOLUTION_CURRENT__,\
02061                                          __ADC_RESOLUTION_TARGET__)            \
02062   (((__DATA__)                                                                 \
02063     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
02064    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
02065   )
02066
02067 /**
02068   * @brief  Helper macro to calculate the voltage (unit: mVolt)
02069   *         corresponding to a ADC conversion data (unit: digital value).
02070   * @note   Analog reference voltage (Vref+) must be either known from
02071   *         user board environment or can be calculated using ADC measurement
02072   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02073   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
02074   * @param  __ADC_DATA__ ADC conversion data (resolution 16 bits)
02075   *                       (unit: digital value).
02076   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02077   *         @arg @ref LL_ADC_RESOLUTION_16B
02078   *         @arg @ref LL_ADC_RESOLUTION_14B
02079   *         @arg @ref LL_ADC_RESOLUTION_12B
02080   *         @arg @ref LL_ADC_RESOLUTION_10B
02081   *         @arg @ref LL_ADC_RESOLUTION_8B
02082   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02083   */
02084 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
02085                                       __ADC_DATA__,\
02086                                       __ADC_RESOLUTION__)                      \
02087   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
02088    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
02089   )
02090
02091 /**
02092   * @brief  Helper macro to calculate analog reference voltage (Vref+)
02093   *         (unit: mVolt) from ADC conversion data of internal voltage
02094   *         reference VrefInt.
02095   * @note   Computation is using VrefInt calibration value
02096   *         stored in system memory for each device during production.
02097   * @note   This voltage depends on user board environment: voltage level
02098   *         connected to pin Vref+.
02099   *         On devices with small package, the pin Vref+ is not present
02100   *         and internally bonded to pin Vdda.
02101   * @note   On this STM32 serie, calibration data of internal voltage reference
02102   *         VrefInt corresponds to a resolution of 16 bits,
02103   *         this is the recommended ADC resolution to convert voltage of
02104   *         internal voltage reference VrefInt.
02105   *         Otherwise, this macro performs the processing to scale
02106   *         ADC conversion data to 16 bits.
02107   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
02108   *         of internal voltage reference VrefInt (unit: digital value).
02109   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02110   *         @arg @ref LL_ADC_RESOLUTION_16B
02111   *         @arg @ref LL_ADC_RESOLUTION_14B
02112   *         @arg @ref LL_ADC_RESOLUTION_12B
02113   *         @arg @ref LL_ADC_RESOLUTION_10B
02114   *         @arg @ref LL_ADC_RESOLUTION_8B
02115   * @retval Analog reference voltage (unit: mV)
02116   */
02117 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
02118                                          __ADC_RESOLUTION__)                   \
02119   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
02120    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
02121                                       (__ADC_RESOLUTION__),                    \
02122                                       LL_ADC_RESOLUTION_16B))
02123
02124 /**
02125   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02126   *         from ADC conversion data of internal temperature sensor.
02127   * @note   Computation is using temperature sensor calibration values
02128   *         stored in system memory for each device during production.
02129   * @note   Calculation formula:
02130   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
02131   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
02132   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
02133   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
02134   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
02135   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
02136   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
02137   *                            TEMP_DEGC_CAL1 (calibrated in factory)
02138   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
02139   *                            TEMP_DEGC_CAL2 (calibrated in factory)
02140   *         Caution: Calculation relevancy under reserve that calibration
02141   *                  parameters are correct (address and data).
02142   *                  To calculate temperature using temperature sensor
02143   *                  datasheet typical values (generic values less, therefore
02144   *                  less accurate than calibrated values),
02145   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
02146   * @note   As calculation input, the analog reference voltage (Vref+) must be
02147   *         defined as it impacts the ADC LSB equivalent voltage.
02148   * @note   Analog reference voltage (Vref+) must be either known from
02149   *         user board environment or can be calculated using ADC measurement
02150   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02151   * @note   On this STM32 serie, calibration data of temperature sensor
02152   *         corresponds to a resolution of 16 bits,
02153   *         this is the recommended ADC resolution to convert voltage of
02154   *         temperature sensor.
02155   *         Otherwise, this macro performs the processing to scale
02156   *         ADC conversion data to 16 bits.
02157   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
02158   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
02159   *                                 temperature sensor (unit: digital value).
02160   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
02161   *                                 sensor voltage has been measured.
02162   *         This parameter can be one of the following values:
02163   *         @arg @ref LL_ADC_RESOLUTION_16B
02164   *         @arg @ref LL_ADC_RESOLUTION_14B
02165   *         @arg @ref LL_ADC_RESOLUTION_12B
02166   *         @arg @ref LL_ADC_RESOLUTION_10B
02167   *         @arg @ref LL_ADC_RESOLUTION_8B
02168   * @retval Temperature (unit: degree Celsius)
02169   */
02170 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
02171                                   __TEMPSENSOR_ADC_DATA__,\
02172                                   __ADC_RESOLUTION__)                              \
02173   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
02174                                                     (__ADC_RESOLUTION__),          \
02175                                                     LL_ADC_RESOLUTION_16B)         \
02176                    * (__VREFANALOG_VOLTAGE__))                                     \
02177                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
02178         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
02179      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
02180     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
02181    ) + TEMPSENSOR_CAL1_TEMP                                                        \
02182   )
02183
02184 /**
02185   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02186   *         from ADC conversion data of internal temperature sensor.
02187   * @note   Computation is using temperature sensor typical values
02188   *         (refer to device datasheet).
02189   * @note   Calculation formula:
02190   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
02191   *                         / Avg_Slope + CALx_TEMP
02192   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
02193   *                                   (unit: digital value)
02194   *                Avg_Slope        = temperature sensor slope
02195   *                                   (unit: uV/Degree Celsius)
02196   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
02197   *                                   temperature CALx_TEMP (unit: mV)
02198   *         Caution: Calculation relevancy under reserve the temperature sensor
02199   *                  of the current device has characteristics in line with
02200   *                  datasheet typical values.
02201   *                  If temperature sensor calibration values are available on
02202   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
02203   *                  temperature calculation will be more accurate using
02204   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
02205   * @note   As calculation input, the analog reference voltage (Vref+) must be
02206   *         defined as it impacts the ADC LSB equivalent voltage.
02207   * @note   Analog reference voltage (Vref+) must be either known from
02208   *         user board environment or can be calculated using ADC measurement
02209   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02210   * @note   ADC measurement data must correspond to a resolution of 16 bits
02211   *         (full scale digital value 4095). If not the case, the data must be
02212   *         preliminarily rescaled to an equivalent resolution of 16 bits.
02213   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
02214   *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".
02215   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
02216   *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
02217   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
02218   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
02219   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
02220   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
02221   *         This parameter can be one of the following values:
02222   *         @arg @ref LL_ADC_RESOLUTION_16B
02223   *         @arg @ref LL_ADC_RESOLUTION_14B
02224   *         @arg @ref LL_ADC_RESOLUTION_12B
02225   *         @arg @ref LL_ADC_RESOLUTION_10B
02226   *         @arg @ref LL_ADC_RESOLUTION_8B
02227   * @retval Temperature (unit: degree Celsius)
02228   */
02229 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
02230                                              __TEMPSENSOR_TYP_CALX_V__,\
02231                                              __TEMPSENSOR_CALX_TEMP__,\
02232                                              __VREFANALOG_VOLTAGE__,\
02233                                              __TEMPSENSOR_ADC_DATA__,\
02234                                              __ADC_RESOLUTION__)               \
02235   ((( (                                                                        \
02236        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
02237                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
02238                  * 1000UL)                                                     \
02239        -                                                                       \
02240        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
02241                  * 1000UL)                                                     \
02242       )                                                                        \
02243     ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \
02244    ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \
02245   )
02246
02247 /**
02248   * @}
02249   */
02250
02251 /**
02252   * @}
02253   */
02254
02255
02256 /* Exported functions --------------------------------------------------------*/
02257 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
02258   * @{
02259   */
02260
02261 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
02262   * @{
02263   */
02264
02265 /**
02266   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
02267   *         ADC register address from ADC instance and a list of ADC registers
02268   *         intended to be used (most commonly) with DMA transfer.
02269   * @note   These ADC registers are data registers:
02270   *         when ADC conversion data is available in ADC data registers,
02271   *         ADC generates a DMA transfer request.
02272   * @note   This macro is intended to be used with LL DMA driver, refer to
02273   *         function "LL_DMA_ConfigAddresses()".
02274   *         Example:
02275   *           LL_DMA_ConfigAddresses(DMA1,
02276   *                                  LL_DMA_CHANNEL_1,
02277   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
02278   *                                  (uint32_t)&< array or variable >,
02279   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
02280   * @note   For devices with several ADC: in multimode, some devices
02281   *         use a different data register outside of ADC instance scope
02282   *         (common data register). This macro manages this register difference,
02283   *         only ADC instance has to be set as parameter.
02284   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
02285   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
02286   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
02287   * @param  ADCx ADC instance
02288   * @param  Register This parameter can be one of the following values:
02289   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
02290   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
02291   *
02292   *         (1) Available on devices with several ADC instances.
02293   * @retval ADC register address
02294   */
02295 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
02296 {
02297   register uint32_t data_reg_addr;
02298
02299   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
02300   {
02301     /* Retrieve address of register DR */
02302     data_reg_addr = (uint32_t) &(ADCx->DR);
02303   }
02304   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
02305   {
02306     /* Retrieve address of register CDR */
02307     data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
02308   }
02309
02310   return data_reg_addr;
02311 }
02312
02313 /**
02314   * @}
02315   */
02316
02317 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
02318   * @{
02319   */
02320
02321 /**
02322   * @brief  Set parameter common to several ADC: Clock source and prescaler.
02323   * @note   On this STM32 serie, if ADC group injected is used, some
02324   *         clock ratio constraints between ADC clock and AHB clock
02325   *         must be respected.
02326   *         Refer to reference manual.
02327   * @note   On this STM32 serie, setting of this feature is conditioned to
02328   *         ADC state:
02329   *         All ADC instances of the ADC common group must be disabled.
02330   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02331   *         ADC instance or by using helper macro helper macro
02332   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02333   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
02334   *         CCR      PRESC          LL_ADC_SetCommonClock
02335   * @param  ADCxy_COMMON ADC common instance
02336   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02337   * @param  CommonClock This parameter can be one of the following values:
02338   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02339   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02340   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02341   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02342   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02343   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02344   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02345   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02346   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02347   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02348   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02349   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02350   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02351   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02352   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02353   * @retval None
02354   */
02355 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
02356 {
02357   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
02358 }
02359
02360 /**
02361   * @brief  Get parameter common to several ADC: Clock source and prescaler.
02362   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
02363   *         CCR      PRESC          LL_ADC_GetCommonClock
02364   * @param  ADCxy_COMMON ADC common instance
02365   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02366   * @retval Returned value can be one of the following values:
02367   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02368   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02369   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02370   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02371   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02372   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02373   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02374   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02375   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02376   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02377   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02378   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02379   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02380   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02381   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02382   */
02383 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
02384 {
02385   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
02386 }
02387
02388 /**
02389   * @brief  Set parameter common to several ADC: measurement path to internal
02390   *         channels (VrefInt, temperature sensor, ...).
02391   * @note   One or several values can be selected.
02392   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02393   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02394   * @note   Stabilization time of measurement path to internal channel:
02395   *         After enabling internal paths, before starting ADC conversion,
02396   *         a delay is required for internal voltage reference and
02397   *         temperature sensor stabilization time.
02398   *         Refer to device datasheet.
02399   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
02400   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
02401   * @note   ADC internal channel sampling time constraint:
02402   *         For ADC conversion of internal channels,
02403   *         a sampling time minimum value is required.
02404   *         Refer to device datasheet.
02405   * @note   On this STM32 serie, setting of this feature is conditioned to
02406   *         ADC state:
02407   *         All ADC instances of the ADC common group must be disabled.
02408   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02409   *         ADC instance or by using helper macro helper macro
02410   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02411   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
02412   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
02413   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
02414   * @param  ADCxy_COMMON ADC common instance
02415   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02416   * @param  PathInternal This parameter can be a combination of the following values:
02417   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02418   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02419   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02420   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02421   * @retval None
02422   */
02423 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
02424 {
02425   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
02426 }
02427
02428 /**
02429   * @brief  Get parameter common to several ADC: measurement path to internal
02430   *         channels (VrefInt, temperature sensor, ...).
02431   * @note   One or several values can be selected.
02432   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02433   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02434   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
02435   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
02436   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
02437   * @param  ADCxy_COMMON ADC common instance
02438   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02439   * @retval Returned value can be a combination of the following values:
02440   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02441   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02442   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02443   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02444   */
02445 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
02446 {
02447   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
02448 }
02449
02450 /**
02451   * @}
02452   */
02453
02454 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
02455   * @{
02456   */
02457
02458 /**
02459   * @brief  Set ADC calibration factor in the mode single-ended
02460   *         or differential (for devices with differential mode available).
02461   * @note   This function is intended to set calibration parameters
02462   *         without having to perform a new calibration using
02463   *         @ref LL_ADC_StartCalibration().
02464   * @note   For devices with differential mode available:
02465   *         Calibration of offset is specific to each of
02466   *         single-ended and differential modes
02467   *         (calibration factor must be specified for each of these
02468   *         differential modes, if used afterwards and if the application
02469   *         requires their calibration).
02470   *         Calibration of linearity is common to both
02471   *         single-ended and differential modes
02472   *         (calibration factor can be specified only once).
02473   * @note   In case of setting calibration factors of both modes single ended
02474   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
02475   *         both calibration factors must be concatenated.
02476   *         To perform this processing, use helper macro
02477   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
02478   * @note   On this STM32 serie, setting of this feature is conditioned to
02479   *         ADC state:
02480   *         ADC must be enabled, without calibration on going, without conversion
02481   *         on going on group regular.
02482   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationOffsetFactor\n
02483   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationOffsetFactor
02484   * @param  ADCx ADC instance
02485   * @param  SingleDiff This parameter can be one of the following values:
02486   *         @arg @ref LL_ADC_SINGLE_ENDED
02487   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02488   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
02489   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
02490   * @retval None
02491   */
02492 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
02493 {
02494   MODIFY_REG(ADCx->CALFACT,
02495              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
02496              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
02497 }
02498
02499 /**
02500   * @brief  Get ADC calibration factor in the mode single-ended
02501   *         or differential (for devices with differential mode available).
02502   * @note   Calibration factors are set by hardware after performing
02503   *         a calibration run using function @ref LL_ADC_StartCalibration().
02504   * @note   For devices with differential mode available:
02505   *         Calibration of offset is specific to each of
02506   *         single-ended and differential modes
02507   *         Calibration of linearity is common to both
02508   *         single-ended and differential modes
02509   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationOffsetFactor\n
02510   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationOffsetFactor
02511   * @param  ADCx ADC instance
02512   * @param  SingleDiff This parameter can be one of the following values:
02513   *         @arg @ref LL_ADC_SINGLE_ENDED
02514   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02515   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
02516   */
02517 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
02518 {
02519   /* Retrieve bits with position in register depending on parameter           */
02520   /* "SingleDiff".                                                            */
02521   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
02522   /* containing other bits reserved for other purpose.                        */
02523   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
02524 }
02525
02526 /**
02527   * @brief  Set ADC Linear calibration factor in the mode single-ended.
02528   * @note   This function is intended to set linear calibration parameters
02529   *         without having to perform a new calibration using
02530   *         @ref LL_ADC_StartCalibration().
02531   * @note   On this STM32 serie, setting of this feature is conditioned to
02532   *         ADC state:
02533   *         ADC must be enabled, without calibration on going, without conversion
02534   *         on going on group regular.
02535   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor\n
02536   *         CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor
02537   * @param  ADCx ADC instance
02538   * @param  LinearityWord This parameter can be one of the following values:
02539   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
02540   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
02541   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
02542   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
02543   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
02544   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
02545   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
02546   * @retval None
02547   */
02548 __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
02549 {
02550   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
02551   MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
02552   MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
02553   while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))
02554   {
02555     timeout_cpu_cycles--;
02556   }
02557 }
02558
02559 /**
02560   * @brief  Get ADC Linear calibration factor in the mode single-ended.
02561   * @note   Calibration factors are set by hardware after performing
02562   *         a calibration run using function @ref LL_ADC_StartCalibration().
02563   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor\n
02564   *         CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor
02565   * @param  ADCx ADC instance
02566   * @param  LinearityWord This parameter can be one of the following values:
02567   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
02568   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
02569   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
02570   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
02571   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
02572   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
02573   * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
02574   */
02575 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
02576 {
02577   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
02578   CLEAR_BIT(ADCx->CR, LinearityWord);
02579   while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))
02580   {
02581     timeout_cpu_cycles--;
02582   }
02583   return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
02584 }
02585 /**
02586   * @brief  Set ADC resolution.
02587   *         Refer to reference manual for alignments formats
02588   *         dependencies to ADC resolutions.
02589   * @note   On this STM32 serie, setting of this feature is conditioned to
02590   *         ADC state:
02591   *         ADC must be disabled or enabled without conversion on going
02592   *         on either groups regular or injected.
02593   * @rmtoll CFGR     RES            LL_ADC_SetResolution
02594   * @param  ADCx ADC instance
02595   * @param  Resolution This parameter can be one of the following values:
02596   *         @arg @ref LL_ADC_RESOLUTION_16B
02597   *         @arg @ref LL_ADC_RESOLUTION_14B
02598   *         @arg @ref LL_ADC_RESOLUTION_12B
02599   *         @arg @ref LL_ADC_RESOLUTION_10B
02600   *         @arg @ref LL_ADC_RESOLUTION_8B
02601   * @retval None
02602   */
02603 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
02604 {
02605 #if defined (ADC_VER_V5_3)
02606   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02607 #else
02608   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
02609   {
02610     MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02611   }
02612   else /* Rev.V */
02613   {
02614     if(LL_ADC_RESOLUTION_8B == Resolution)
02615     {
02616       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
02617     }
02618     else
02619     {
02620       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02621     }
02622   }
02623 #endif /* ADC_VER_V5_3*/
02624 }
02625
02626 /**
02627   * @brief  Get ADC resolution.
02628   *         Refer to reference manual for alignments formats
02629   *         dependencies to ADC resolutions.
02630   * @rmtoll CFGR     RES            LL_ADC_GetResolution
02631   * @param  ADCx ADC instance
02632   * @retval Returned value can be one of the following values:
02633   *         @arg @ref LL_ADC_RESOLUTION_16B
02634   *         @arg @ref LL_ADC_RESOLUTION_14B
02635   *         @arg @ref LL_ADC_RESOLUTION_12B
02636   *         @arg @ref LL_ADC_RESOLUTION_10B
02637   *         @arg @ref LL_ADC_RESOLUTION_8B
02638   */
02639 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02640 {
02641 #if defined (ADC_VER_V5_3)
02642     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02643 #else
02644   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
02645   {
02646     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02647   }
02648   else /* Rev.V */
02649   {
02650     if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
02651     {
02652       return (LL_ADC_RESOLUTION_8B);
02653     }
02654     else
02655     {
02656       return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02657     }
02658   }
02659 #endif /* ADC_VER_V5_3 */
02660 }
02661
02662 /**
02663   * @brief  Set ADC low power mode.
02664   * @note   Description of ADC low power modes:
02665   *         - ADC low power mode "auto wait": Dynamic low power mode,
02666   *           ADC conversions occurrences are limited to the minimum necessary
02667   *           in order to reduce power consumption.
02668   *           New ADC conversion starts only when the previous
02669   *           unitary conversion data (for ADC group regular)
02670   *           or previous sequence conversions data (for ADC group injected)
02671   *           has been retrieved by user software.
02672   *           In the meantime, ADC remains idle: does not performs any
02673   *           other conversion.
02674   *           This mode allows to automatically adapt the ADC conversions
02675   *           triggers to the speed of the software that reads the data.
02676   *           Moreover, this avoids risk of overrun for low frequency
02677   *           applications.
02678   *           How to use this low power mode:
02679   *           - Do not use with interruption or DMA since these modes
02680   *             have to clear immediately the EOC flag to free the
02681   *             IRQ vector sequencer.
02682   *           - Do use with polling: 1. Start conversion,
02683   *             2. Later on, when conversion data is needed: poll for end of
02684   *             conversion  to ensure that conversion is completed and
02685   *             retrieve ADC conversion data. This will trig another
02686   *             ADC conversion start.
02687   *         - ADC low power mode "auto power-off" (feature available on
02688   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02689   *           the ADC automatically powers-off after a conversion and
02690   *           automatically wakes up when a new conversion is triggered
02691   *           (with startup time between trigger and start of sampling).
02692   *           This feature can be combined with low power mode "auto wait".
02693   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02694   *         is corresponding to previous ADC conversion start, independently
02695   *         of delay during which ADC was idle.
02696   *         Therefore, the ADC conversion data may be outdated: does not
02697   *         correspond to the current voltage level on the selected
02698   *         ADC channel.
02699   * @note   On this STM32 serie, setting of this feature is conditioned to
02700   *         ADC state:
02701   *         ADC must be disabled or enabled without conversion on going
02702   *         on either groups regular or injected.
02703   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
02704   * @param  ADCx ADC instance
02705   * @param  LowPowerMode This parameter can be one of the following values:
02706   *         @arg @ref LL_ADC_LP_MODE_NONE
02707   *         @arg @ref LL_ADC_LP_AUTOWAIT
02708   * @retval None
02709   */
02710 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02711 {
02712   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
02713 }
02714
02715 /**
02716   * @brief  Get ADC low power mode:
02717   * @note   Description of ADC low power modes:
02718   *         - ADC low power mode "auto wait": Dynamic low power mode,
02719   *           ADC conversions occurrences are limited to the minimum necessary
02720   *           in order to reduce power consumption.
02721   *           New ADC conversion starts only when the previous
02722   *           unitary conversion data (for ADC group regular)
02723   *           or previous sequence conversions data (for ADC group injected)
02724   *           has been retrieved by user software.
02725   *           In the meantime, ADC remains idle: does not performs any
02726   *           other conversion.
02727   *           This mode allows to automatically adapt the ADC conversions
02728   *           triggers to the speed of the software that reads the data.
02729   *           Moreover, this avoids risk of overrun for low frequency
02730   *           applications.
02731   *           How to use this low power mode:
02732   *           - Do not use with interruption or DMA since these modes
02733   *             have to clear immediately the EOC flag to free the
02734   *             IRQ vector sequencer.
02735   *           - Do use with polling: 1. Start conversion,
02736   *             2. Later on, when conversion data is needed: poll for end of
02737   *             conversion  to ensure that conversion is completed and
02738   *             retrieve ADC conversion data. This will trig another
02739   *             ADC conversion start.
02740   *         - ADC low power mode "auto power-off" (feature available on
02741   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02742   *           the ADC automatically powers-off after a conversion and
02743   *           automatically wakes up when a new conversion is triggered
02744   *           (with startup time between trigger and start of sampling).
02745   *           This feature can be combined with low power mode "auto wait".
02746   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02747   *         is corresponding to previous ADC conversion start, independently
02748   *         of delay during which ADC was idle.
02749   *         Therefore, the ADC conversion data may be outdated: does not
02750   *         correspond to the current voltage level on the selected
02751   *         ADC channel.
02752   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
02753   * @param  ADCx ADC instance
02754   * @retval Returned value can be one of the following values:
02755   *         @arg @ref LL_ADC_LP_MODE_NONE
02756   *         @arg @ref LL_ADC_LP_AUTOWAIT
02757   */
02758 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02759 {
02760   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
02761 }
02762
02763 /**
02764   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
02765   * @note   This function set the 2 items of offset configuration:
02766   *         - ADC channel to which the offset programmed will be applied
02767   *           (independently of channel mapped on ADC group regular
02768   *           or group injected)
02769   *         - Offset level (offset to be subtracted from the raw
02770   *           converted data).
02771   * @note   Caution: Offset format is dependent to ADC resolution:
02772   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02773   *         are set to 0.
02774   * @note   This function enables the offset, by default. It can be forced
02775   *         to disable state using function LL_ADC_SetOffsetState().
02776   * @note   If a channel is mapped on several offsets numbers, only the offset
02777   *         with the lowest value is considered for the subtraction.
02778   * @note   On this STM32 serie, setting of this feature is conditioned to
02779   *         ADC state:
02780   *         ADC must be disabled or enabled without conversion on going
02781   *         on either groups regular or injected.
02782   * @note   On STM32H7, some fast channels are available: fast analog inputs
02783   *         coming from GPIO pads (ADC_IN0..5).
02784   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
02785   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
02786   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
02787   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
02788   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
02789   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
02790   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
02791   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
02792   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
02793   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
02794   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
02795   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
02796   * @param  ADCx ADC instance
02797   * @param  Offsety This parameter can be one of the following values:
02798   *         @arg @ref LL_ADC_OFFSET_1
02799   *         @arg @ref LL_ADC_OFFSET_2
02800   *         @arg @ref LL_ADC_OFFSET_3
02801   *         @arg @ref LL_ADC_OFFSET_4
02802   * @param  Channel This parameter can be one of the following values:
02803   *         @arg @ref LL_ADC_CHANNEL_0           (3)
02804   *         @arg @ref LL_ADC_CHANNEL_1           (3)
02805   *         @arg @ref LL_ADC_CHANNEL_2           (3)
02806   *         @arg @ref LL_ADC_CHANNEL_3           (3)
02807   *         @arg @ref LL_ADC_CHANNEL_4           (3)
02808   *         @arg @ref LL_ADC_CHANNEL_5           (3)
02809   *         @arg @ref LL_ADC_CHANNEL_6
02810   *         @arg @ref LL_ADC_CHANNEL_7
02811   *         @arg @ref LL_ADC_CHANNEL_8
02812   *         @arg @ref LL_ADC_CHANNEL_9
02813   *         @arg @ref LL_ADC_CHANNEL_10
02814   *         @arg @ref LL_ADC_CHANNEL_11
02815   *         @arg @ref LL_ADC_CHANNEL_12
02816   *         @arg @ref LL_ADC_CHANNEL_13
02817   *         @arg @ref LL_ADC_CHANNEL_14
02818   *         @arg @ref LL_ADC_CHANNEL_15
02819   *         @arg @ref LL_ADC_CHANNEL_16
02820   *         @arg @ref LL_ADC_CHANNEL_17
02821   *         @arg @ref LL_ADC_CHANNEL_18
02822   *         @arg @ref LL_ADC_CHANNEL_19
02823   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02824   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02825   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
02826   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
02827   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
02828   *
02829   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
02830   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
02831   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
02832   *             Other channels are slow channels (conversion rate: refer to reference manual).
02833   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
02834   * @retval None
02835   */
02836 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
02837 {
02838   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02839
02840   MODIFY_REG(*preg,
02841              ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
02842              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
02843 }
02844
02845 /**
02846   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02847   *         Channel to which the offset programmed will be applied
02848   *         (independently of channel mapped on ADC group regular
02849   *         or group injected)
02850   * @note   Usage of the returned channel number:
02851   *         - To reinject this channel into another function LL_ADC_xxx:
02852   *           the returned channel number is only partly formatted on definition
02853   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02854   *           with parts of literals LL_ADC_CHANNEL_x or using
02855   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02856   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02857   *           as parameter for another function.
02858   *         - To get the channel number in decimal format:
02859   *           process the returned value with the helper macro
02860   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02861   * @note   On STM32H7, some fast channels are available: fast analog inputs
02862   *         coming from GPIO pads (ADC_IN0..5).
02863   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
02864   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
02865   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
02866   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
02867   * @param  ADCx ADC instance
02868   * @param  Offsety This parameter can be one of the following values:
02869   *         @arg @ref LL_ADC_OFFSET_1
02870   *         @arg @ref LL_ADC_OFFSET_2
02871   *         @arg @ref LL_ADC_OFFSET_3
02872   *         @arg @ref LL_ADC_OFFSET_4
02873   * @retval Returned value can be one of the following values:
02874   *         @arg @ref LL_ADC_CHANNEL_0           (3)
02875   *         @arg @ref LL_ADC_CHANNEL_1           (3)
02876   *         @arg @ref LL_ADC_CHANNEL_2           (3)
02877   *         @arg @ref LL_ADC_CHANNEL_3           (3)
02878   *         @arg @ref LL_ADC_CHANNEL_4           (3)
02879   *         @arg @ref LL_ADC_CHANNEL_5           (3)
02880   *         @arg @ref LL_ADC_CHANNEL_6
02881   *         @arg @ref LL_ADC_CHANNEL_7
02882   *         @arg @ref LL_ADC_CHANNEL_8
02883   *         @arg @ref LL_ADC_CHANNEL_9
02884   *         @arg @ref LL_ADC_CHANNEL_10
02885   *         @arg @ref LL_ADC_CHANNEL_11
02886   *         @arg @ref LL_ADC_CHANNEL_12
02887   *         @arg @ref LL_ADC_CHANNEL_13
02888   *         @arg @ref LL_ADC_CHANNEL_14
02889   *         @arg @ref LL_ADC_CHANNEL_15
02890   *         @arg @ref LL_ADC_CHANNEL_16
02891   *         @arg @ref LL_ADC_CHANNEL_17
02892   *         @arg @ref LL_ADC_CHANNEL_18
02893   *         @arg @ref LL_ADC_CHANNEL_19
02894   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02895   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02896   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
02897   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
02898   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
02899   *
02900   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
02901   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
02902   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
02903   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
02904   *         (1, 2) For ADC channel read back from ADC register,
02905   *                comparison with internal channel parameter to be done
02906   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02907   */
02908 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
02909 {
02910   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02911
02912   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
02913 }
02914
02915 /**
02916   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02917   *         Offset level (offset to be subtracted from the raw
02918   *         converted data).
02919   * @note   Caution: Offset format is dependent to ADC resolution:
02920   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02921   *         are set to 0.
02922   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
02923   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
02924   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
02925   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
02926   * @param  ADCx ADC instance
02927   * @param  Offsety This parameter can be one of the following values:
02928   *         @arg @ref LL_ADC_OFFSET_1
02929   *         @arg @ref LL_ADC_OFFSET_2
02930   *         @arg @ref LL_ADC_OFFSET_3
02931   *         @arg @ref LL_ADC_OFFSET_4
02932   * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
02933   */
02934 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
02935 {
02936   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02937
02938   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
02939 }
02940
02941
02942 /**
02943   * @brief  Set data right shift for the ADC selected offset number 1, 2, 3 or 4:
02944   *         signed offset saturation if enabled or disabled.
02945   * @rmtoll CFGR2    RSHIFT          LL_ADC_SetDataRightShift\n
02946   * @param  ADCx ADC instance
02947   * @param  Offsety This parameter can be one of the following values:
02948   *         @arg @ref LL_ADC_OFFSET_1
02949   *         @arg @ref LL_ADC_OFFSET_2
02950   *         @arg @ref LL_ADC_OFFSET_3
02951   *         @arg @ref LL_ADC_OFFSET_4
02952   * @param  RigthShift This parameter can be one of the following values:
02953   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
02954   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
02955   * @retval Returned None
02956   */
02957 __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
02958 {
02959   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
02960 }
02961
02962 /**
02963   * @brief  Get data right shift for the ADC selected offset number 1, 2, 3 or 4:
02964   *         signed offset saturation if enabled or disabled.
02965   * @rmtoll CFGR2    RSHIFT          LL_ADC_GetDataRightShift\n
02966   * @param  ADCx ADC instance
02967   * @param  Offsety This parameter can be one of the following values:
02968   *         @arg @ref LL_ADC_OFFSET_1
02969   *         @arg @ref LL_ADC_OFFSET_2
02970   *         @arg @ref LL_ADC_OFFSET_3
02971   *         @arg @ref LL_ADC_OFFSET_4
02972   * @retval Returned value can be one of the following values:
02973   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
02974   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
02975   */
02976 __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
02977 {
02978   return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
02979 }
02980
02981 /**
02982   * @brief  Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:
02983   *         signed offset saturation if enabled or disabled.
02984   * @rmtoll OFR1     SSATE          LL_ADC_SetOffsetSignedSaturation\n
02985   *         OFR2     SSATE          LL_ADC_SetOffsetSignedSaturation\n
02986   *         OFR3     SSATE          LL_ADC_SetOffsetSignedSaturation\n
02987   *         OFR4     SSATE          LL_ADC_SetOffsetSignedSaturation
02988   * @param  ADCx ADC instance
02989   * @param  Offsety This parameter can be one of the following values:
02990   *         @arg @ref LL_ADC_OFFSET_1
02991   *         @arg @ref LL_ADC_OFFSET_2
02992   *         @arg @ref LL_ADC_OFFSET_3
02993   *         @arg @ref LL_ADC_OFFSET_4
02994   * @param  OffsetSignedSaturation This parameter can be one of the following values:
02995   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
02996   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
02997   * @retval Returned None
02998   */
02999 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
03000 {
03001    register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
03002    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
03003 }
03004
03005 /**
03006   * @brief  Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:
03007   *         signed offset saturation if enabled or disabled.
03008   * @rmtoll OFR1     SSATE          LL_ADC_GetOffsetSignedSaturation\n
03009   *         OFR2     SSATE          LL_ADC_GetOffsetSignedSaturation\n
03010   *         OFR3     SSATE          LL_ADC_GetOffsetSignedSaturation\n
03011   *         OFR4     SSATE          LL_ADC_GetOffsetSignedSaturation
03012   * @param  ADCx ADC instance
03013   * @param  Offsety This parameter can be one of the following values:
03014   *         @arg @ref LL_ADC_OFFSET_1
03015   *         @arg @ref LL_ADC_OFFSET_2
03016   *         @arg @ref LL_ADC_OFFSET_3
03017   *         @arg @ref LL_ADC_OFFSET_4
03018   * @retval Returned value can be one of the following values:
03019   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
03020   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
03021   */
03022 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
03023 {
03024   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
03025   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
03026 }
03027
03028 /**
03029   * @}
03030   */
03031
03032 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
03033   * @{
03034   */
03035
03036 /**
03037   * @brief  Set ADC group regular conversion trigger source:
03038   *         internal (SW start) or from external peripheral (timer event,
03039   *         external interrupt line).
03040   * @note   On this STM32 serie, setting trigger source to external trigger
03041   *         also set trigger polarity to rising edge
03042   *         (default setting for compatibility with some ADC on other
03043   *         STM32 families having this setting set by HW default value).
03044   *         In case of need to modify trigger edge, use
03045   *         function @ref LL_ADC_REG_SetTriggerEdge().
03046   * @note   Availability of parameters of trigger sources from timer
03047   *         depends on timers availability on the selected device.
03048   * @note   On this STM32 serie, setting of this feature is conditioned to
03049   *         ADC state:
03050   *         ADC must be disabled or enabled without conversion on going
03051   *         on group regular.
03052   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
03053   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
03054   * @param  ADCx ADC instance
03055   * @param  TriggerSource This parameter can be one of the following values:
03056   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03057   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
03058   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
03059   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03060   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
03061   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
03062   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
03063   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
03064   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
03065   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
03066   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03067   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03068   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
03069   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
03070   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
03071   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
03072   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
03073   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
03074   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
03075   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
03076   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
03077   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
03078   * @retval None
03079   */
03080 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03081 {
03082   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
03083 }
03084
03085 /**
03086   * @brief  Get ADC group regular conversion trigger source:
03087   *         internal (SW start) or from external peripheral (timer event,
03088   *         external interrupt line).
03089   * @note   To determine whether group regular trigger source is
03090   *         internal (SW start) or external, without detail
03091   *         of which peripheral is selected as external trigger,
03092   *         (equivalent to
03093   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
03094   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
03095   * @note   Availability of parameters of trigger sources from timer
03096   *         depends on timers availability on the selected device.
03097   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
03098   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
03099   * @param  ADCx ADC instance
03100   * @retval Returned value can be one of the following values:
03101   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03102   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
03103   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
03104   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03105   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
03106   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
03107   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
03108   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
03109   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
03110   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
03111   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03112   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03113   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
03114   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
03115   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
03116   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
03117   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
03118   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
03119   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
03120   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
03121   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
03122   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
03123   */
03124 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
03125 {
03126   register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
03127
03128   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03129   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
03130   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
03131
03132   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
03133   /* to match with triggers literals definition.                              */
03134   return ((TriggerSource
03135            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
03136           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
03137          );
03138 }
03139
03140 /**
03141   * @brief  Get ADC group regular conversion trigger source internal (SW start)
03142   *         or external.
03143   * @note   In case of group regular trigger source set to external trigger,
03144   *         to determine which peripheral is selected as external trigger,
03145   *         use function @ref LL_ADC_REG_GetTriggerSource().
03146   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
03147   * @param  ADCx ADC instance
03148   * @retval Value "0" if trigger source external trigger
03149   *         Value "1" if trigger source SW start.
03150   */
03151 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03152 {
03153   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
03154 }
03155
03156 /**
03157   * @brief  Set ADC group regular conversion trigger polarity.
03158   * @note   Applicable only for trigger source set to external trigger.
03159   * @note   On this STM32 serie, setting of this feature is conditioned to
03160   *         ADC state:
03161   *         ADC must be disabled or enabled without conversion on going
03162   *         on group regular.
03163   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
03164   * @param  ADCx ADC instance
03165   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03166   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03167   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03168   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03169   * @retval None
03170   */
03171 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03172 {
03173   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
03174 }
03175
03176 /**
03177   * @brief  Get ADC group regular conversion trigger polarity.
03178   * @note   Applicable only for trigger source set to external trigger.
03179   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
03180   * @param  ADCx ADC instance
03181   * @retval Returned value can be one of the following values:
03182   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03183   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03184   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03185   */
03186 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
03187 {
03188   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
03189 }
03190
03191 /**
03192   * @brief  Set ADC group regular sequencer length and scan direction.
03193   * @note   Description of ADC group regular sequencer features:
03194   *         - For devices with sequencer fully configurable
03195   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03196   *           sequencer length and each rank affectation to a channel
03197   *           are configurable.
03198   *           This function performs configuration of:
03199   *           - Sequence length: Number of ranks in the scan sequence.
03200   *           - Sequence direction: Unless specified in parameters, sequencer
03201   *             scan direction is forward (from rank 1 to rank n).
03202   *           Sequencer ranks are selected using
03203   *           function "LL_ADC_REG_SetSequencerRanks()".
03204   *         - For devices with sequencer not fully configurable
03205   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03206   *           sequencer length and each rank affectation to a channel
03207   *           are defined by channel number.
03208   *           This function performs configuration of:
03209   *           - Sequence length: Number of ranks in the scan sequence is
03210   *             defined by number of channels set in the sequence,
03211   *             rank of each channel is fixed by channel HW number.
03212   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03213   *           - Sequence direction: Unless specified in parameters, sequencer
03214   *             scan direction is forward (from lowest channel number to
03215   *             highest channel number).
03216   *           Sequencer ranks are selected using
03217   *           function "LL_ADC_REG_SetSequencerChannels()".
03218   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03219   *         ADC conversion on only 1 channel.
03220   * @note   On this STM32 serie, setting of this feature is conditioned to
03221   *         ADC state:
03222   *         ADC must be disabled or enabled without conversion on going
03223   *         on group regular.
03224   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
03225   * @param  ADCx ADC instance
03226   * @param  SequencerNbRanks This parameter can be one of the following values:
03227   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03228   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03229   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03230   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03231   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03232   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03233   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03234   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03235   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03236   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03237   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03238   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03239   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03240   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03241   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03242   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03243   * @retval None
03244   */
03245 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03246 {
03247   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
03248 }
03249
03250 /**
03251   * @brief  Get ADC group regular sequencer length and scan direction.
03252   * @note   Description of ADC group regular sequencer features:
03253   *         - For devices with sequencer fully configurable
03254   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03255   *           sequencer length and each rank affectation to a channel
03256   *           are configurable.
03257   *           This function retrieves:
03258   *           - Sequence length: Number of ranks in the scan sequence.
03259   *           - Sequence direction: Unless specified in parameters, sequencer
03260   *             scan direction is forward (from rank 1 to rank n).
03261   *           Sequencer ranks are selected using
03262   *           function "LL_ADC_REG_SetSequencerRanks()".
03263   *         - For devices with sequencer not fully configurable
03264   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03265   *           sequencer length and each rank affectation to a channel
03266   *           are defined by channel number.
03267   *           This function retrieves:
03268   *           - Sequence length: Number of ranks in the scan sequence is
03269   *             defined by number of channels set in the sequence,
03270   *             rank of each channel is fixed by channel HW number.
03271   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03272   *           - Sequence direction: Unless specified in parameters, sequencer
03273   *             scan direction is forward (from lowest channel number to
03274   *             highest channel number).
03275   *           Sequencer ranks are selected using
03276   *           function "LL_ADC_REG_SetSequencerChannels()".
03277   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03278   *         ADC conversion on only 1 channel.
03279   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
03280   * @param  ADCx ADC instance
03281   * @retval Returned value can be one of the following values:
03282   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03283   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03284   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03285   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03286   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03287   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03288   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03289   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03290   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03291   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03292   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03293   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03294   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03295   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03296   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03297   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03298   */
03299 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
03300 {
03301   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
03302 }
03303
03304 /**
03305   * @brief  Set ADC group regular sequencer discontinuous mode:
03306   *         sequence subdivided and scan conversions interrupted every selected
03307   *         number of ranks.
03308   * @note   It is not possible to enable both ADC group regular
03309   *         continuous mode and sequencer discontinuous mode.
03310   * @note   It is not possible to enable both ADC auto-injected mode
03311   *         and ADC group regular sequencer discontinuous mode.
03312   * @note   On this STM32 serie, setting of this feature is conditioned to
03313   *         ADC state:
03314   *         ADC must be disabled or enabled without conversion on going
03315   *         on group regular.
03316   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
03317   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
03318   * @param  ADCx ADC instance
03319   * @param  SeqDiscont This parameter can be one of the following values:
03320   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03321   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03322   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03323   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03324   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03325   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03326   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03327   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03328   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03329   * @retval None
03330   */
03331 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03332 {
03333   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
03334 }
03335
03336 /**
03337   * @brief  Get ADC group regular sequencer discontinuous mode:
03338   *         sequence subdivided and scan conversions interrupted every selected
03339   *         number of ranks.
03340   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
03341   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
03342   * @param  ADCx ADC instance
03343   * @retval Returned value can be one of the following values:
03344   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03345   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03346   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03347   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03348   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03349   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03350   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03351   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03352   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03353   */
03354 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
03355 {
03356   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
03357 }
03358
03359 /**
03360   * @brief  Set ADC group regular sequence: channel on the selected
03361   *         scan sequence rank.
03362   * @note   This function performs configuration of:
03363   *         - Channels ordering into each rank of scan sequence:
03364   *           whatever channel can be placed into whatever rank.
03365   * @note   On this STM32 serie, ADC group regular sequencer is
03366   *         fully configurable: sequencer length and each rank
03367   *         affectation to a channel are configurable.
03368   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03369   * @note   Depending on devices and packages, some channels may not be available.
03370   *         Refer to device datasheet for channels availability.
03371   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03372   *         TempSensor, ...), measurement paths to internal channels must be
03373   *         enabled separately.
03374   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03375   * @note   On this STM32 serie, setting of this feature is conditioned to
03376   *         ADC state:
03377   *         ADC must be disabled or enabled without conversion on going
03378   *         on group regular.
03379   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
03380   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
03381   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
03382   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
03383   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
03384   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
03385   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
03386   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
03387   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
03388   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
03389   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
03390   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
03391   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
03392   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
03393   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
03394   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
03395   * @param  ADCx ADC instance
03396   * @param  Rank This parameter can be one of the following values:
03397   *         @arg @ref LL_ADC_REG_RANK_1
03398   *         @arg @ref LL_ADC_REG_RANK_2
03399   *         @arg @ref LL_ADC_REG_RANK_3
03400   *         @arg @ref LL_ADC_REG_RANK_4
03401   *         @arg @ref LL_ADC_REG_RANK_5
03402   *         @arg @ref LL_ADC_REG_RANK_6
03403   *         @arg @ref LL_ADC_REG_RANK_7
03404   *         @arg @ref LL_ADC_REG_RANK_8
03405   *         @arg @ref LL_ADC_REG_RANK_9
03406   *         @arg @ref LL_ADC_REG_RANK_10
03407   *         @arg @ref LL_ADC_REG_RANK_11
03408   *         @arg @ref LL_ADC_REG_RANK_12
03409   *         @arg @ref LL_ADC_REG_RANK_13
03410   *         @arg @ref LL_ADC_REG_RANK_14
03411   *         @arg @ref LL_ADC_REG_RANK_15
03412   *         @arg @ref LL_ADC_REG_RANK_16
03413   * @param  Channel This parameter can be one of the following values:
03414   *         @arg @ref LL_ADC_CHANNEL_0           (3)
03415   *         @arg @ref LL_ADC_CHANNEL_1           (3)
03416   *         @arg @ref LL_ADC_CHANNEL_2           (3)
03417   *         @arg @ref LL_ADC_CHANNEL_3           (3)
03418   *         @arg @ref LL_ADC_CHANNEL_4           (3)
03419   *         @arg @ref LL_ADC_CHANNEL_5           (3)
03420   *         @arg @ref LL_ADC_CHANNEL_6
03421   *         @arg @ref LL_ADC_CHANNEL_7
03422   *         @arg @ref LL_ADC_CHANNEL_8
03423   *         @arg @ref LL_ADC_CHANNEL_9
03424   *         @arg @ref LL_ADC_CHANNEL_10
03425   *         @arg @ref LL_ADC_CHANNEL_11
03426   *         @arg @ref LL_ADC_CHANNEL_12
03427   *         @arg @ref LL_ADC_CHANNEL_13
03428   *         @arg @ref LL_ADC_CHANNEL_14
03429   *         @arg @ref LL_ADC_CHANNEL_15
03430   *         @arg @ref LL_ADC_CHANNEL_16
03431   *         @arg @ref LL_ADC_CHANNEL_17
03432   *         @arg @ref LL_ADC_CHANNEL_18
03433   *         @arg @ref LL_ADC_CHANNEL_19
03434   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03435   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03436   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03437   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03438   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03439   *
03440   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
03441   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
03442   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
03443   *             Other channels are slow channels (conversion rate: refer to reference manual).
03444   * @retval None
03445   */
03446 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03447 {
03448   /* Set bits with content of parameter "Channel" with bits position          */
03449   /* in register and register position depending on parameter "Rank".         */
03450   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03451   /* other bits reserved for other purpose.                                   */
03452   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
03453
03454   MODIFY_REG(*preg,
03455              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
03456              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
03457 }
03458
03459 /**
03460   * @brief  Get ADC group regular sequence: channel on the selected
03461   *         scan sequence rank.
03462   * @note   On this STM32 serie, ADC group regular sequencer is
03463   *         fully configurable: sequencer length and each rank
03464   *         affectation to a channel are configurable.
03465   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03466   * @note   Depending on devices and packages, some channels may not be available.
03467   *         Refer to device datasheet for channels availability.
03468   * @note   Usage of the returned channel number:
03469   *         - To reinject this channel into another function LL_ADC_xxx:
03470   *           the returned channel number is only partly formatted on definition
03471   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03472   *           with parts of literals LL_ADC_CHANNEL_x or using
03473   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03474   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03475   *           as parameter for another function.
03476   *         - To get the channel number in decimal format:
03477   *           process the returned value with the helper macro
03478   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03479   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
03480   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
03481   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
03482   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
03483   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
03484   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
03485   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
03486   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
03487   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
03488   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
03489   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
03490   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
03491   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
03492   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
03493   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
03494   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
03495   * @param  ADCx ADC instance
03496   * @param  Rank This parameter can be one of the following values:
03497   *         @arg @ref LL_ADC_REG_RANK_1
03498   *         @arg @ref LL_ADC_REG_RANK_2
03499   *         @arg @ref LL_ADC_REG_RANK_3
03500   *         @arg @ref LL_ADC_REG_RANK_4
03501   *         @arg @ref LL_ADC_REG_RANK_5
03502   *         @arg @ref LL_ADC_REG_RANK_6
03503   *         @arg @ref LL_ADC_REG_RANK_7
03504   *         @arg @ref LL_ADC_REG_RANK_8
03505   *         @arg @ref LL_ADC_REG_RANK_9
03506   *         @arg @ref LL_ADC_REG_RANK_10
03507   *         @arg @ref LL_ADC_REG_RANK_11
03508   *         @arg @ref LL_ADC_REG_RANK_12
03509   *         @arg @ref LL_ADC_REG_RANK_13
03510   *         @arg @ref LL_ADC_REG_RANK_14
03511   *         @arg @ref LL_ADC_REG_RANK_15
03512   *         @arg @ref LL_ADC_REG_RANK_16
03513   * @retval Returned value can be one of the following values:
03514   *         @arg @ref LL_ADC_CHANNEL_0           (3)
03515   *         @arg @ref LL_ADC_CHANNEL_1           (3)
03516   *         @arg @ref LL_ADC_CHANNEL_2           (3)
03517   *         @arg @ref LL_ADC_CHANNEL_3           (3)
03518   *         @arg @ref LL_ADC_CHANNEL_4           (3)
03519   *         @arg @ref LL_ADC_CHANNEL_5           (3)
03520   *         @arg @ref LL_ADC_CHANNEL_6
03521   *         @arg @ref LL_ADC_CHANNEL_7
03522   *         @arg @ref LL_ADC_CHANNEL_8
03523   *         @arg @ref LL_ADC_CHANNEL_9
03524   *         @arg @ref LL_ADC_CHANNEL_10
03525   *         @arg @ref LL_ADC_CHANNEL_11
03526   *         @arg @ref LL_ADC_CHANNEL_12
03527   *         @arg @ref LL_ADC_CHANNEL_13
03528   *         @arg @ref LL_ADC_CHANNEL_14
03529   *         @arg @ref LL_ADC_CHANNEL_15
03530   *         @arg @ref LL_ADC_CHANNEL_16
03531   *         @arg @ref LL_ADC_CHANNEL_17
03532   *         @arg @ref LL_ADC_CHANNEL_18
03533   *         @arg @ref LL_ADC_CHANNEL_19
03534   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03535   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03536   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03537   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03538   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03539   *
03540   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
03541   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
03542   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
03543   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
03544   *         (1, 2) For ADC channel read back from ADC register,
03545   *                comparison with internal channel parameter to be done
03546   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03547   */
03548 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03549 {
03550   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
03551
03552   return (uint32_t)((READ_BIT(*preg,
03553                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03554                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
03555                    );
03556 }
03557
03558 /**
03559   * @brief  Set ADC continuous conversion mode on ADC group regular.
03560   * @note   Description of ADC continuous conversion mode:
03561   *         - single mode: one conversion per trigger
03562   *         - continuous mode: after the first trigger, following
03563   *           conversions launched successively automatically.
03564   * @note   It is not possible to enable both ADC group regular
03565   *         continuous mode and sequencer discontinuous mode.
03566   * @note   On this STM32 serie, setting of this feature is conditioned to
03567   *         ADC state:
03568   *         ADC must be disabled or enabled without conversion on going
03569   *         on group regular.
03570   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
03571   * @param  ADCx ADC instance
03572   * @param  Continuous This parameter can be one of the following values:
03573   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03574   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03575   * @retval None
03576   */
03577 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
03578 {
03579   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
03580 }
03581
03582 /**
03583   * @brief  Get ADC continuous conversion mode on ADC group regular.
03584   * @note   Description of ADC continuous conversion mode:
03585   *         - single mode: one conversion per trigger
03586   *         - continuous mode: after the first trigger, following
03587   *           conversions launched successively automatically.
03588   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
03589   * @param  ADCx ADC instance
03590   * @retval Returned value can be one of the following values:
03591   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03592   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03593   */
03594 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
03595 {
03596   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
03597 }
03598 /**
03599   * @brief  Set ADC data transfer mode
03600   * @note   Conversion data can be either:
03601   *            - Available in Data Register
03602   *            - Transfered by DMA in one shot mode
03603   *            - Transfered by DMA in circular mode
03604   *            - Transfered to DFSDM data register
03605   * @rmtoll CFGR     DMNGT           LL_ADC_REG_SetDataTransferMode
03606   * @param  ADCx ADC instance
03607   * @param  DataTransferMode This parameter can be one of the following values:
03608   *         @arg @ref LL_ADC_REG_DR_TRANSFER
03609   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03610   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03611   *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER
03612   * @retval None
03613   */
03614 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
03615 {
03616   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
03617 }
03618
03619
03620 /**
03621   * @brief  Get ADC data transfer mode
03622   * @note   Conversion data can be either:
03623   *            - Available in Data Register
03624   *            - Transfered by DMA in one shot mode
03625   *            - Transfered by DMA in circular mode
03626   *            - Transfered to DFSDM data register
03627   * @rmtoll CFGR     DMNGT           LL_ADC_REG_GetDataTransferMode
03628   * @param  ADCx ADC instance
03629   * @retval Returned value can be one of the following values:
03630   *         @arg @ref LL_ADC_REG_DR_TRANSFER
03631   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03632   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03633   *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER
03634   */
03635 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
03636 {
03637   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
03638 }
03639
03640
03641 /**
03642   * @brief  Set ADC group regular behavior in case of overrun:
03643   *         data preserved or overwritten.
03644   * @note   Compatibility with devices without feature overrun:
03645   *         other devices without this feature have a behavior
03646   *         equivalent to data overwritten.
03647   *         The default setting of overrun is data preserved.
03648   *         Therefore, for compatibility with all devices, parameter
03649   *         overrun should be set to data overwritten.
03650   * @note   On this STM32 serie, setting of this feature is conditioned to
03651   *         ADC state:
03652   *         ADC must be disabled or enabled without conversion on going
03653   *         on group regular.
03654   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
03655   * @param  ADCx ADC instance
03656   * @param  Overrun This parameter can be one of the following values:
03657   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03658   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03659   * @retval None
03660   */
03661 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
03662 {
03663   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
03664 }
03665
03666 /**
03667   * @brief  Get ADC group regular behavior in case of overrun:
03668   *         data preserved or overwritten.
03669   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
03670   * @param  ADCx ADC instance
03671   * @retval Returned value can be one of the following values:
03672   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03673   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03674   */
03675 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
03676 {
03677   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
03678 }
03679
03680 /**
03681   * @}
03682   */
03683
03684 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
03685   * @{
03686   */
03687
03688 /**
03689   * @brief  Set ADC group injected conversion trigger source:
03690   *         internal (SW start) or from external peripheral (timer event,
03691   *         external interrupt line).
03692   * @note   On this STM32 serie, setting trigger source to external trigger
03693   *         also set trigger polarity to rising edge
03694   *         (default setting for compatibility with some ADC on other
03695   *         STM32 families having this setting set by HW default value).
03696   *         In case of need to modify trigger edge, use
03697   *         function @ref LL_ADC_INJ_SetTriggerEdge().
03698   * @note   Availability of parameters of trigger sources from timer
03699   *         depends on timers availability on the selected device.
03700   * @note   On this STM32 serie, setting of this feature is conditioned to
03701   *         ADC state:
03702   *         ADC must not be disabled. Can be enabled with or without conversion
03703   *         on going on either groups regular or injected.
03704   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
03705   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
03706   * @param  ADCx ADC instance
03707   * @param  TriggerSource This parameter can be one of the following values:
03708   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03709   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03710   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03711   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03712   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03713   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
03714   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03715   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03716   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
03717   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03718   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03719   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03720   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
03721   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03722   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
03723   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03724   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03725   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
03726   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
03727   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
03728   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
03729   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
03730   * @retval None
03731   */
03732 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03733 {
03734   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
03735 }
03736
03737 /**
03738   * @brief  Get ADC group injected conversion trigger source:
03739   *         internal (SW start) or from external peripheral (timer event,
03740   *         external interrupt line).
03741   * @note   To determine whether group injected trigger source is
03742   *         internal (SW start) or external, without detail
03743   *         of which peripheral is selected as external trigger,
03744   *         (equivalent to
03745   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
03746   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
03747   * @note   Availability of parameters of trigger sources from timer
03748   *         depends on timers availability on the selected device.
03749   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
03750   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
03751   * @param  ADCx ADC instance
03752   * @retval Returned value can be one of the following values:
03753   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03754   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03755   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03756   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03757   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03758   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
03759   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03760   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03761   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
03762   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03763   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03764   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03765   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
03766   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03767   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
03768   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03769   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03770   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
03771   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
03772   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
03773   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
03774   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
03775   */
03776 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
03777 {
03778   register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
03779
03780   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03781   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
03782   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
03783
03784   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
03785   /* to match with triggers literals definition.                              */
03786   return ((TriggerSource
03787            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
03788           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
03789          );
03790 }
03791
03792 /**
03793   * @brief  Get ADC group injected conversion trigger source internal (SW start)
03794             or external
03795   * @note   In case of group injected trigger source set to external trigger,
03796   *         to determine which peripheral is selected as external trigger,
03797   *         use function @ref LL_ADC_INJ_GetTriggerSource.
03798   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
03799   * @param  ADCx ADC instance
03800   * @retval Value "0" if trigger source external trigger
03801   *         Value "1" if trigger source SW start.
03802   */
03803 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03804 {
03805   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
03806 }
03807
03808 /**
03809   * @brief  Set ADC group injected conversion trigger polarity.
03810   *         Applicable only for trigger source set to external trigger.
03811   * @note   On this STM32 serie, setting of this feature is conditioned to
03812   *         ADC state:
03813   *         ADC must not be disabled. Can be enabled with or without conversion
03814   *         on going on either groups regular or injected.
03815   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
03816   * @param  ADCx ADC instance
03817   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03818   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03819   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03820   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03821   * @retval None
03822   */
03823 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03824 {
03825   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
03826 }
03827
03828 /**
03829   * @brief  Get ADC group injected conversion trigger polarity.
03830   *         Applicable only for trigger source set to external trigger.
03831   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
03832   * @param  ADCx ADC instance
03833   * @retval Returned value can be one of the following values:
03834   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03835   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03836   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03837   */
03838 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
03839 {
03840   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
03841 }
03842
03843 /**
03844   * @brief  Set ADC group injected sequencer length and scan direction.
03845   * @note   This function performs configuration of:
03846   *         - Sequence length: Number of ranks in the scan sequence.
03847   *         - Sequence direction: Unless specified in parameters, sequencer
03848   *           scan direction is forward (from rank 1 to rank n).
03849   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03850   *         ADC conversion on only 1 channel.
03851   * @note   On this STM32 serie, setting of this feature is conditioned to
03852   *         ADC state:
03853   *         ADC must not be disabled. Can be enabled with or without conversion
03854   *         on going on either groups regular or injected.
03855   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
03856   * @param  ADCx ADC instance
03857   * @param  SequencerNbRanks This parameter can be one of the following values:
03858   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03859   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03860   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03861   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03862   * @retval None
03863   */
03864 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03865 {
03866   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
03867 }
03868
03869 /**
03870   * @brief  Get ADC group injected sequencer length and scan direction.
03871   * @note   This function retrieves:
03872   *         - Sequence length: Number of ranks in the scan sequence.
03873   *         - Sequence direction: Unless specified in parameters, sequencer
03874   *           scan direction is forward (from rank 1 to rank n).
03875   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03876   *         ADC conversion on only 1 channel.
03877   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
03878   * @param  ADCx ADC instance
03879   * @retval Returned value can be one of the following values:
03880   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03881   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03882   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03883   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03884   */
03885 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
03886 {
03887   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
03888 }
03889
03890 /**
03891   * @brief  Set ADC group injected sequencer discontinuous mode:
03892   *         sequence subdivided and scan conversions interrupted every selected
03893   *         number of ranks.
03894   * @note   It is not possible to enable both ADC group injected
03895   *         auto-injected mode and sequencer discontinuous mode.
03896   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
03897   * @param  ADCx ADC instance
03898   * @param  SeqDiscont This parameter can be one of the following values:
03899   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03900   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03901   * @retval None
03902   */
03903 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03904 {
03905   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
03906 }
03907
03908 /**
03909   * @brief  Get ADC group injected sequencer discontinuous mode:
03910   *         sequence subdivided and scan conversions interrupted every selected
03911   *         number of ranks.
03912   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
03913   * @param  ADCx ADC instance
03914   * @retval Returned value can be one of the following values:
03915   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03916   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03917   */
03918 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
03919 {
03920   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
03921 }
03922
03923 /**
03924   * @brief  Set ADC group injected sequence: channel on the selected
03925   *         sequence rank.
03926   * @note   Depending on devices and packages, some channels may not be available.
03927   *         Refer to device datasheet for channels availability.
03928   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03929   *         TempSensor, ...), measurement paths to internal channels must be
03930   *         enabled separately.
03931   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03932   * @note   On STM32H7, some fast channels are available: fast analog inputs
03933   *         coming from GPIO pads (ADC_IN0..5).
03934   * @note   On this STM32 serie, setting of this feature is conditioned to
03935   *         ADC state:
03936   *         ADC must not be disabled. Can be enabled with or without conversion
03937   *         on going on either groups regular or injected.
03938   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
03939   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
03940   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
03941   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
03942   * @param  ADCx ADC instance
03943   * @param  Rank This parameter can be one of the following values:
03944   *         @arg @ref LL_ADC_INJ_RANK_1
03945   *         @arg @ref LL_ADC_INJ_RANK_2
03946   *         @arg @ref LL_ADC_INJ_RANK_3
03947   *         @arg @ref LL_ADC_INJ_RANK_4
03948   * @param  Channel This parameter can be one of the following values:
03949   *         @arg @ref LL_ADC_CHANNEL_0           (3)
03950   *         @arg @ref LL_ADC_CHANNEL_1           (3)
03951   *         @arg @ref LL_ADC_CHANNEL_2           (3)
03952   *         @arg @ref LL_ADC_CHANNEL_3           (3)
03953   *         @arg @ref LL_ADC_CHANNEL_4           (3)
03954   *         @arg @ref LL_ADC_CHANNEL_5           (3)
03955   *         @arg @ref LL_ADC_CHANNEL_6
03956   *         @arg @ref LL_ADC_CHANNEL_7
03957   *         @arg @ref LL_ADC_CHANNEL_8
03958   *         @arg @ref LL_ADC_CHANNEL_9
03959   *         @arg @ref LL_ADC_CHANNEL_10
03960   *         @arg @ref LL_ADC_CHANNEL_11
03961   *         @arg @ref LL_ADC_CHANNEL_12
03962   *         @arg @ref LL_ADC_CHANNEL_13
03963   *         @arg @ref LL_ADC_CHANNEL_14
03964   *         @arg @ref LL_ADC_CHANNEL_15
03965   *         @arg @ref LL_ADC_CHANNEL_16
03966   *         @arg @ref LL_ADC_CHANNEL_17
03967   *         @arg @ref LL_ADC_CHANNEL_18
03968   *         @arg @ref LL_ADC_CHANNEL_19
03969   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03970   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
03971   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
03972   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03973   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03974   *
03975   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
03976   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
03977   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
03978   *             Other channels are slow channels (conversion rate: refer to reference manual).
03979   * @retval None
03980   */
03981 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03982 {
03983   /* Set bits with content of parameter "Channel" with bits position          */
03984   /* in register depending on parameter "Rank".                               */
03985   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03986   /* other bits reserved for other purpose.                                   */
03987   MODIFY_REG(ADCx->JSQR,
03988              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
03989              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
03990 }
03991
03992 /**
03993   * @brief  Get ADC group injected sequence: channel on the selected
03994   *         sequence rank.
03995   * @note   Depending on devices and packages, some channels may not be available.
03996   *         Refer to device datasheet for channels availability.
03997   * @note   Usage of the returned channel number:
03998   *         - To reinject this channel into another function LL_ADC_xxx:
03999   *           the returned channel number is only partly formatted on definition
04000   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04001   *           with parts of literals LL_ADC_CHANNEL_x or using
04002   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04003   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04004   *           as parameter for another function.
04005   *         - To get the channel number in decimal format:
04006   *           process the returned value with the helper macro
04007   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04008   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
04009   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
04010   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
04011   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
04012   * @param  ADCx ADC instance
04013   * @param  Rank This parameter can be one of the following values:
04014   *         @arg @ref LL_ADC_INJ_RANK_1
04015   *         @arg @ref LL_ADC_INJ_RANK_2
04016   *         @arg @ref LL_ADC_INJ_RANK_3
04017   *         @arg @ref LL_ADC_INJ_RANK_4
04018   * @retval Returned value can be one of the following values:
04019   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04020   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04021   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04022   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04023   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04024   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04025   *         @arg @ref LL_ADC_CHANNEL_6
04026   *         @arg @ref LL_ADC_CHANNEL_7
04027   *         @arg @ref LL_ADC_CHANNEL_8
04028   *         @arg @ref LL_ADC_CHANNEL_9
04029   *         @arg @ref LL_ADC_CHANNEL_10
04030   *         @arg @ref LL_ADC_CHANNEL_11
04031   *         @arg @ref LL_ADC_CHANNEL_12
04032   *         @arg @ref LL_ADC_CHANNEL_13
04033   *         @arg @ref LL_ADC_CHANNEL_14
04034   *         @arg @ref LL_ADC_CHANNEL_15
04035   *         @arg @ref LL_ADC_CHANNEL_16
04036   *         @arg @ref LL_ADC_CHANNEL_17
04037   *         @arg @ref LL_ADC_CHANNEL_18
04038   *         @arg @ref LL_ADC_CHANNEL_19
04039   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04040   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04041   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04042   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04043   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04044   *
04045   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04046   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04047   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04048   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
04049   *         (1, 2) For ADC channel read back from ADC register,
04050   *                comparison with internal channel parameter to be done
04051   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
04052   */
04053 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
04054 {
04055   return (uint32_t)((READ_BIT(ADCx->JSQR,
04056                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
04057                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
04058                    );
04059 }
04060
04061 /**
04062   * @brief  Set ADC group injected conversion trigger:
04063   *         independent or from ADC group regular.
04064   * @note   This mode can be used to extend number of data registers
04065   *         updated after one ADC conversion trigger and with data
04066   *         permanently kept (not erased by successive conversions of scan of
04067   *         ADC sequencer ranks), up to 5 data registers:
04068   *         1 data register on ADC group regular, 4 data registers
04069   *         on ADC group injected.
04070   * @note   If ADC group injected injected trigger source is set to an
04071   *         external trigger, this feature must be must be set to
04072   *         independent trigger.
04073   *         ADC group injected automatic trigger is compliant only with
04074   *         group injected trigger source set to SW start, without any
04075   *         further action on  ADC group injected conversion start or stop:
04076   *         in this case, ADC group injected is controlled only
04077   *         from ADC group regular.
04078   * @note   It is not possible to enable both ADC group injected
04079   *         auto-injected mode and sequencer discontinuous mode.
04080   * @note   On this STM32 serie, setting of this feature is conditioned to
04081   *         ADC state:
04082   *         ADC must be disabled or enabled without conversion on going
04083   *         on either groups regular or injected.
04084   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
04085   * @param  ADCx ADC instance
04086   * @param  TrigAuto This parameter can be one of the following values:
04087   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04088   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04089   * @retval None
04090   */
04091 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
04092 {
04093   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
04094 }
04095
04096 /**
04097   * @brief  Get ADC group injected conversion trigger:
04098   *         independent or from ADC group regular.
04099   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
04100   * @param  ADCx ADC instance
04101   * @retval Returned value can be one of the following values:
04102   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04103   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04104   */
04105 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
04106 {
04107   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
04108 }
04109
04110 /**
04111   * @brief  Set ADC group injected contexts queue mode.
04112   * @note   A context is a setting of group injected sequencer:
04113   *         - group injected trigger
04114   *         - sequencer length
04115   *         - sequencer ranks
04116   *         If contexts queue is disabled:
04117   *         - only 1 sequence can be configured
04118   *           and is active perpetually.
04119   *         If contexts queue is enabled:
04120   *         - up to 2 contexts can be queued
04121   *           and are checked in and out as a FIFO stack (first-in, first-out).
04122   *         - If a new context is set when queues is full, error is triggered
04123   *           by interruption "Injected Queue Overflow".
04124   *         - Two behaviors are possible when all contexts have been processed:
04125   *           the contexts queue can maintain the last context active perpetually
04126   *           or can be empty and injected group triggers are disabled.
04127   *         - Triggers can be only external (not internal SW start)
04128   *         - Caution: The sequence must be fully configured in one time
04129   *           (one write of register JSQR makes a check-in of a new context
04130   *           into the queue).
04131   *           Therefore functions to set separately injected trigger and
04132   *           sequencer channels cannot be used, register JSQR must be set
04133   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
04134   * @note   This parameter can be modified only when no conversion is on going
04135   *         on either groups regular or injected.
04136   * @note   A modification of the context mode (bit JQDIS) causes the contexts
04137   *         queue to be flushed and the register JSQR is cleared.
04138   * @note   On this STM32 serie, setting of this feature is conditioned to
04139   *         ADC state:
04140   *         ADC must be disabled or enabled without conversion on going
04141   *         on either groups regular or injected.
04142   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
04143   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
04144   * @param  ADCx ADC instance
04145   * @param  QueueMode This parameter can be one of the following values:
04146   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
04147   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04148   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04149   * @retval None
04150   */
04151 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
04152 {
04153   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
04154 }
04155
04156 /**
04157   * @brief  Get ADC group injected context queue mode.
04158   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
04159   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
04160   * @param  ADCx ADC instance
04161   * @retval Returned value can be one of the following values:
04162   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
04163   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04164   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04165   */
04166 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
04167 {
04168   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
04169 }
04170
04171 /**
04172   * @brief  Set one context on ADC group injected that will be checked in
04173   *         contexts queue.
04174   * @note   A context is a setting of group injected sequencer:
04175   *         - group injected trigger
04176   *         - sequencer length
04177   *         - sequencer ranks
04178   *         This function is intended to be used when contexts queue is enabled,
04179   *         because the sequence must be fully configured in one time
04180   *         (functions to set separately injected trigger and sequencer channels
04181   *         cannot be used):
04182   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
04183   * @note   In the contexts queue, only the active context can be read.
04184   *         The parameters of this function can be read using functions:
04185   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
04186   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
04187   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
04188   * @note   On this STM32 serie, to measure internal channels (VrefInt,
04189   *         TempSensor, ...), measurement paths to internal channels must be
04190   *         enabled separately.
04191   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
04192   * @note   On STM32H7, some fast channels are available: fast analog inputs
04193   *         coming from GPIO pads (ADC_IN0..5).
04194   * @note   On this STM32 serie, setting of this feature is conditioned to
04195   *         ADC state:
04196   *         ADC must not be disabled. Can be enabled with or without conversion
04197   *         on going on either groups regular or injected.
04198   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
04199   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
04200   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
04201   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
04202   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
04203   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
04204   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
04205   * @param  ADCx ADC instance
04206   * @param  TriggerSource This parameter can be one of the following values:
04207   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
04208   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
04209   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
04210   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
04211   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
04212   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
04213   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
04214   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
04215   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
04216   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
04217   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
04218   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
04219   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
04220   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
04221   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
04222   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
04223   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
04224   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
04225   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
04226   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
04227   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
04228   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
04229   * @param  ExternalTriggerEdge This parameter can be one of the following values:
04230   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
04231   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
04232   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
04233   *
04234   *         Note: This parameter is discarded in case of SW start:
04235   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
04236   * @param  SequencerNbRanks This parameter can be one of the following values:
04237   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
04238   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
04239   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
04240   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
04241   * @param  Rank1_Channel This parameter can be one of the following values:
04242   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04243   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04244   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04245   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04246   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04247   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04248   *         @arg @ref LL_ADC_CHANNEL_6
04249   *         @arg @ref LL_ADC_CHANNEL_7
04250   *         @arg @ref LL_ADC_CHANNEL_8
04251   *         @arg @ref LL_ADC_CHANNEL_9
04252   *         @arg @ref LL_ADC_CHANNEL_10
04253   *         @arg @ref LL_ADC_CHANNEL_11
04254   *         @arg @ref LL_ADC_CHANNEL_12
04255   *         @arg @ref LL_ADC_CHANNEL_13
04256   *         @arg @ref LL_ADC_CHANNEL_14
04257   *         @arg @ref LL_ADC_CHANNEL_15
04258   *         @arg @ref LL_ADC_CHANNEL_16
04259   *         @arg @ref LL_ADC_CHANNEL_17
04260   *         @arg @ref LL_ADC_CHANNEL_18
04261   *         @arg @ref LL_ADC_CHANNEL_19
04262   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04263   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04264   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04265   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04266   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04267   *
04268   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04269   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04270   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04271   *             Other channels are slow channels (conversion rate: refer to reference manual).
04272   * @param  Rank2_Channel This parameter can be one of the following values:
04273   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04274   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04275   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04276   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04277   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04278   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04279   *         @arg @ref LL_ADC_CHANNEL_6
04280   *         @arg @ref LL_ADC_CHANNEL_7
04281   *         @arg @ref LL_ADC_CHANNEL_8
04282   *         @arg @ref LL_ADC_CHANNEL_9
04283   *         @arg @ref LL_ADC_CHANNEL_10
04284   *         @arg @ref LL_ADC_CHANNEL_11
04285   *         @arg @ref LL_ADC_CHANNEL_12
04286   *         @arg @ref LL_ADC_CHANNEL_13
04287   *         @arg @ref LL_ADC_CHANNEL_14
04288   *         @arg @ref LL_ADC_CHANNEL_15
04289   *         @arg @ref LL_ADC_CHANNEL_16
04290   *         @arg @ref LL_ADC_CHANNEL_17
04291   *         @arg @ref LL_ADC_CHANNEL_18
04292   *         @arg @ref LL_ADC_CHANNEL_19
04293   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04294   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04295   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04296   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04297   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04298   *
04299   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04300   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04301   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04302   *             Other channels are slow channels (conversion rate: refer to reference manual).
04303   * @param  Rank3_Channel This parameter can be one of the following values:
04304   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04305   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04306   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04307   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04308   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04309   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04310   *         @arg @ref LL_ADC_CHANNEL_6
04311   *         @arg @ref LL_ADC_CHANNEL_7
04312   *         @arg @ref LL_ADC_CHANNEL_8
04313   *         @arg @ref LL_ADC_CHANNEL_9
04314   *         @arg @ref LL_ADC_CHANNEL_10
04315   *         @arg @ref LL_ADC_CHANNEL_11
04316   *         @arg @ref LL_ADC_CHANNEL_12
04317   *         @arg @ref LL_ADC_CHANNEL_13
04318   *         @arg @ref LL_ADC_CHANNEL_14
04319   *         @arg @ref LL_ADC_CHANNEL_15
04320   *         @arg @ref LL_ADC_CHANNEL_16
04321   *         @arg @ref LL_ADC_CHANNEL_17
04322   *         @arg @ref LL_ADC_CHANNEL_18
04323   *         @arg @ref LL_ADC_CHANNEL_19
04324   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04325   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04326   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04327   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04328   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04329   *
04330   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04331   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04332   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04333   *             Other channels are slow channels (conversion rate: refer to reference manual).
04334   * @param  Rank4_Channel This parameter can be one of the following values:
04335   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04336   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04337   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04338   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04339   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04340   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04341   *         @arg @ref LL_ADC_CHANNEL_6
04342   *         @arg @ref LL_ADC_CHANNEL_7
04343   *         @arg @ref LL_ADC_CHANNEL_8
04344   *         @arg @ref LL_ADC_CHANNEL_9
04345   *         @arg @ref LL_ADC_CHANNEL_10
04346   *         @arg @ref LL_ADC_CHANNEL_11
04347   *         @arg @ref LL_ADC_CHANNEL_12
04348   *         @arg @ref LL_ADC_CHANNEL_13
04349   *         @arg @ref LL_ADC_CHANNEL_14
04350   *         @arg @ref LL_ADC_CHANNEL_15
04351   *         @arg @ref LL_ADC_CHANNEL_16
04352   *         @arg @ref LL_ADC_CHANNEL_17
04353   *         @arg @ref LL_ADC_CHANNEL_18
04354   *         @arg @ref LL_ADC_CHANNEL_19
04355   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04356   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04357   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04358   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04359   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04360   *
04361   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04362   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04363   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04364   *             Other channels are slow channels (conversion rate: refer to reference manual).
04365   * @retval None
04366   */
04367 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
04368                                                    uint32_t TriggerSource,
04369                                                    uint32_t ExternalTriggerEdge,
04370                                                    uint32_t SequencerNbRanks,
04371                                                    uint32_t Rank1_Channel,
04372                                                    uint32_t Rank2_Channel,
04373                                                    uint32_t Rank3_Channel,
04374                                                    uint32_t Rank4_Channel)
04375 {
04376   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
04377   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
04378   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
04379   /* because containing other bits reserved for other purpose.                */
04380   /* If parameter "TriggerSource" is set to SW start, then parameter          */
04381   /* "ExternalTriggerEdge" is discarded.                                      */
04382   register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
04383   MODIFY_REG(ADCx->JSQR,
04384              ADC_JSQR_JEXTSEL |
04385              ADC_JSQR_JEXTEN  |
04386              ADC_JSQR_JSQ4    |
04387              ADC_JSQR_JSQ3    |
04388              ADC_JSQR_JSQ2    |
04389              ADC_JSQR_JSQ1    |
04390              ADC_JSQR_JL,
04391              (TriggerSource & ADC_JSQR_JEXTSEL)          |
04392              (ExternalTriggerEdge * (is_trigger_not_sw)) |
04393              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
04394              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
04395              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
04396              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
04397              SequencerNbRanks
04398             );
04399 }
04400
04401 /**
04402   * @}
04403   */
04404
04405 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
04406   * @{
04407   */
04408
04409 /**
04410   * @brief  Set sampling time of the selected ADC channel
04411   *         Unit: ADC clock cycles.
04412   * @note   On this device, sampling time is on channel scope: independently
04413   *         of channel mapped on ADC group regular or injected.
04414   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
04415   *         converted:
04416   *         sampling time constraints must be respected (sampling time can be
04417   *         adjusted in function of ADC clock frequency and sampling time
04418   *         setting).
04419   *         Refer to device datasheet for timings values (parameters TS_vrefint,
04420   *         TS_temp, ...).
04421   * @note   Conversion time is the addition of sampling time and processing time.
04422   *         On this STM32 serie, ADC processing time is:
04423   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04424   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04425   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04426   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04427   * @note   In case of ADC conversion of internal channel (VrefInt,
04428   *         temperature sensor, ...), a sampling time minimum value
04429   *         is required.
04430   *         Refer to device datasheet.
04431   * @note   On this STM32 serie, setting of this feature is conditioned to
04432   *         ADC state:
04433   *         ADC must be disabled or enabled without conversion on going
04434   *         on either groups regular or injected.
04435   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
04436   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
04437   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
04438   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
04439   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
04440   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
04441   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
04442   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
04443   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
04444   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
04445   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
04446   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
04447   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
04448   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
04449   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
04450   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
04451   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
04452   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
04453   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
04454   * @param  ADCx ADC instance
04455   * @param  Channel This parameter can be one of the following values:
04456   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04457   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04458   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04459   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04460   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04461   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04462   *         @arg @ref LL_ADC_CHANNEL_6
04463   *         @arg @ref LL_ADC_CHANNEL_7
04464   *         @arg @ref LL_ADC_CHANNEL_8
04465   *         @arg @ref LL_ADC_CHANNEL_9
04466   *         @arg @ref LL_ADC_CHANNEL_10
04467   *         @arg @ref LL_ADC_CHANNEL_11
04468   *         @arg @ref LL_ADC_CHANNEL_12
04469   *         @arg @ref LL_ADC_CHANNEL_13
04470   *         @arg @ref LL_ADC_CHANNEL_14
04471   *         @arg @ref LL_ADC_CHANNEL_15
04472   *         @arg @ref LL_ADC_CHANNEL_16
04473   *         @arg @ref LL_ADC_CHANNEL_17
04474   *         @arg @ref LL_ADC_CHANNEL_18
04475   *         @arg @ref LL_ADC_CHANNEL_19
04476   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04477   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04478   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04479   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04480   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04481   *
04482   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04483   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04484   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04485   *             Other channels are slow channels (conversion rate: refer to reference manual).
04486   * @param  SamplingTime This parameter can be one of the following values:
04487   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
04488   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04489   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
04490   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
04491   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
04492   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
04493   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
04494   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
04495   * @retval None
04496   */
04497 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
04498 {
04499   /* Set bits with content of parameter "SamplingTime" with bits position     */
04500   /* in register and register position depending on parameter "Channel".      */
04501   /* Parameter "Channel" is used with masks because containing                */
04502   /* other bits reserved for other purpose.                                   */
04503   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
04504
04505   MODIFY_REG(*preg,
04506              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
04507              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
04508 }
04509
04510 /**
04511   * @brief  Get sampling time of the selected ADC channel
04512   *         Unit: ADC clock cycles.
04513   * @note   On this device, sampling time is on channel scope: independently
04514   *         of channel mapped on ADC group regular or injected.
04515   * @note   Conversion time is the addition of sampling time and processing time.
04516   *         On this STM32 serie, ADC processing time is:
04517   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04518   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04519   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04520   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04521   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
04522   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
04523   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
04524   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
04525   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
04526   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
04527   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
04528   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
04529   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
04530   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
04531   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
04532   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
04533   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
04534   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
04535   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
04536   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
04537   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
04538   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
04539   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
04540   * @param  ADCx ADC instance
04541   * @param  Channel This parameter can be one of the following values:
04542   *         @arg @ref LL_ADC_CHANNEL_0           (3)
04543   *         @arg @ref LL_ADC_CHANNEL_1           (3)
04544   *         @arg @ref LL_ADC_CHANNEL_2           (3)
04545   *         @arg @ref LL_ADC_CHANNEL_3           (3)
04546   *         @arg @ref LL_ADC_CHANNEL_4           (3)
04547   *         @arg @ref LL_ADC_CHANNEL_5           (3)
04548   *         @arg @ref LL_ADC_CHANNEL_6
04549   *         @arg @ref LL_ADC_CHANNEL_7
04550   *         @arg @ref LL_ADC_CHANNEL_8
04551   *         @arg @ref LL_ADC_CHANNEL_9
04552   *         @arg @ref LL_ADC_CHANNEL_10
04553   *         @arg @ref LL_ADC_CHANNEL_11
04554   *         @arg @ref LL_ADC_CHANNEL_12
04555   *         @arg @ref LL_ADC_CHANNEL_13
04556   *         @arg @ref LL_ADC_CHANNEL_14
04557   *         @arg @ref LL_ADC_CHANNEL_15
04558   *         @arg @ref LL_ADC_CHANNEL_16
04559   *         @arg @ref LL_ADC_CHANNEL_17
04560   *         @arg @ref LL_ADC_CHANNEL_18
04561   *         @arg @ref LL_ADC_CHANNEL_19
04562   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04563   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
04564   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
04565   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04566   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04567   *
04568   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04569   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
04570   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
04571   *             Other channels are slow channels (conversion rate: refer to reference manual).
04572   * @retval Returned value can be one of the following values:
04573   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
04574   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04575   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
04576   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
04577   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
04578   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
04579   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
04580   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
04581   */
04582 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
04583 {
04584   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
04585
04586   return (uint32_t)(READ_BIT(*preg,
04587                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
04588                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
04589                    );
04590 }
04591
04592 /**
04593   * @brief  Set mode single-ended or differential input of the selected
04594   *         ADC channel.
04595   * @note   Channel ending is on channel scope: independently of channel mapped
04596   *         on ADC group regular or injected.
04597   *         In differential mode: Differential measurement is carried out
04598   *         between the selected channel 'i' (positive input) and
04599   *         channel 'i+1' (negative input). Only channel 'i' has to be
04600   *         configured, channel 'i+1' is configured automatically.
04601   * @note   Refer to Reference Manual to ensure the selected channel is
04602   *         available in differential mode.
04603   *         For example, internal channels (VrefInt, TempSensor, ...) are
04604   *         not available in differential mode.
04605   * @note   When configuring a channel 'i' in differential mode,
04606   *         the channel 'i+1' is not usable separately.
04607   * @note   On STM32H7, some channels are internally fixed to single-ended inputs
04608   *         configuration:
04609   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
04610   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
04611   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
04612   * @note   For ADC channels configured in differential mode, both inputs
04613   *         should be biased at (Vref+)/2 +/-200mV.
04614   *         (Vref+ is the analog voltage reference)
04615   * @note   On this STM32 serie, setting of this feature is conditioned to
04616   *         ADC state:
04617   *         ADC must be ADC disabled.
04618   * @note   One or several values can be selected.
04619   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04620   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
04621   * @param  ADCx ADC instance
04622   * @param  Channel This parameter can be one of the following values:
04623   *         @arg @ref LL_ADC_CHANNEL_1
04624   *         @arg @ref LL_ADC_CHANNEL_2
04625   *         @arg @ref LL_ADC_CHANNEL_3
04626   *         @arg @ref LL_ADC_CHANNEL_4
04627   *         @arg @ref LL_ADC_CHANNEL_5
04628   *         @arg @ref LL_ADC_CHANNEL_10
04629   *         @arg @ref LL_ADC_CHANNEL_11
04630   *         @arg @ref LL_ADC_CHANNEL_12
04631   *         @arg @ref LL_ADC_CHANNEL_13
04632   *         @arg @ref LL_ADC_CHANNEL_14
04633   *         @arg @ref LL_ADC_CHANNEL_15
04634   *         @arg @ref LL_ADC_CHANNEL_16
04635   *         @arg @ref LL_ADC_CHANNEL_17
04636   *         @arg @ref LL_ADC_CHANNEL_18
04637   *         @arg @ref LL_ADC_CHANNEL_19
04638   * @param  SingleDiff This parameter can be a combination of the following values:
04639   *         @arg @ref LL_ADC_SINGLE_ENDED
04640   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
04641   * @retval None
04642   */
04643 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
04644 {
04645   /* Bits of channels in single or differential mode are set only for         */
04646   /* differential mode (for single mode, mask of bits allowed to be set is    */
04647   /* shifted out of range of bits of channels in single or differential mode. */
04648   MODIFY_REG(ADCx->DIFSEL,
04649              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
04650              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
04651 }
04652
04653 /**
04654   * @brief  Get mode single-ended or differential input of the selected
04655   *         ADC channel.
04656   * @note   When configuring a channel 'i' in differential mode,
04657   *         the channel 'i+1' is not usable separately.
04658   *         Therefore, to ensure a channel is configured in single-ended mode,
04659   *         the configuration of channel itself and the channel 'i-1' must be
04660   *         read back (to ensure that the selected channel channel has not been
04661   *         configured in differential mode by the previous channel).
04662   * @note   Refer to Reference Manual to ensure the selected channel is
04663   *         available in differential mode.
04664   *         For example, internal channels (VrefInt, TempSensor, ...) are
04665   *         not available in differential mode.
04666   * @note   When configuring a channel 'i' in differential mode,
04667   *         the channel 'i+1' is not usable separately.
04668   * @note   On STM32H7, some channels are internally fixed to single-ended inputs
04669   *         configuration:
04670   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
04671   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
04672   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
04673   * @note   One or several values can be selected. In this case, the value
04674   *         returned is null if all channels are in single ended-mode.
04675   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04676   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
04677   * @param  ADCx ADC instance
04678   * @param  Channel This parameter can be a combination of the following values:
04679   *         @arg @ref LL_ADC_CHANNEL_1
04680   *         @arg @ref LL_ADC_CHANNEL_2
04681   *         @arg @ref LL_ADC_CHANNEL_3
04682   *         @arg @ref LL_ADC_CHANNEL_4
04683   *         @arg @ref LL_ADC_CHANNEL_5
04684   *         @arg @ref LL_ADC_CHANNEL_10
04685   *         @arg @ref LL_ADC_CHANNEL_11
04686   *         @arg @ref LL_ADC_CHANNEL_12
04687   *         @arg @ref LL_ADC_CHANNEL_13
04688   *         @arg @ref LL_ADC_CHANNEL_14
04689   *         @arg @ref LL_ADC_CHANNEL_15
04690   *         @arg @ref LL_ADC_CHANNEL_16
04691   *         @arg @ref LL_ADC_CHANNEL_17
04692   *         @arg @ref LL_ADC_CHANNEL_18
04693   *         @arg @ref LL_ADC_CHANNEL_19
04694   * @retval 0: channel in single-ended mode, else: channel in differential mode
04695   */
04696 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
04697 {
04698   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
04699 }
04700
04701 /**
04702   * @}
04703   */
04704
04705 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
04706   * @{
04707   */
04708
04709 /**
04710   * @brief  Set ADC analog watchdog monitored channels:
04711   *         a single channel, multiple channels or all channels,
04712   *         on ADC groups regular and-or injected.
04713   * @note   Once monitored channels are selected, analog watchdog
04714   *         is enabled.
04715   * @note   In case of need to define a single channel to monitor
04716   *         with analog watchdog from sequencer channel definition,
04717   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
04718   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04719   *         instance:
04720   *         - AWD standard (instance AWD1):
04721   *           - channels monitored: can monitor 1 channel or all channels.
04722   *           - groups monitored: ADC groups regular and-or injected.
04723   *           - resolution: resolution is not limited (corresponds to
04724   *             ADC resolution configured).
04725   *         - AWD flexible (instances AWD2, AWD3):
04726   *           - channels monitored: flexible on channels monitored, selection is
04727   *             channel wise, from from 1 to all channels.
04728   *             Specificity of this analog watchdog: Multiple channels can
04729   *             be selected. For example:
04730   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04731   *           - groups monitored: not selection possible (monitoring on both
04732   *             groups regular and injected).
04733   *             Channels selected are monitored on groups regular and injected:
04734   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04735   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04736   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04737   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04738   *             the 2 LSB are ignored.
04739   * @note   On this STM32 serie, setting of this feature is conditioned to
04740   *         ADC state:
04741   *         ADC must be disabled or enabled without conversion on going
04742   *         on either groups regular or injected.
04743   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
04744   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
04745   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
04746   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
04747   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
04748   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
04749   * @param  ADCx ADC instance
04750   * @param  AWDy This parameter can be one of the following values:
04751   *         @arg @ref LL_ADC_AWD1
04752   *         @arg @ref LL_ADC_AWD2
04753   *         @arg @ref LL_ADC_AWD3
04754   * @param  AWDChannelGroup This parameter can be one of the following values:
04755   *         @arg @ref LL_ADC_AWD_DISABLE
04756   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04757   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04758   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04759   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04760   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04761   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04762   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04763   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04764   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04765   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04766   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04767   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04768   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04769   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04770   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04771   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04772   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04773   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04774   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04775   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04776   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04777   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04778   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04779   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04780   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04781   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04782   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04783   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04784   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04785   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04786   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04787   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04788   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04789   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04790   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04791   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04792   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04793   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04794   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04795   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04796   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04797   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04798   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04799   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04800   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04801   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04802   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04803   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04804   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04805   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04806   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04807   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04808   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04809   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04810   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04811   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04812   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04813   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04814   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04815   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04816   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
04817   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
04818   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
04819   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
04820   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
04821   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
04822   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)
04823   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)
04824   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)
04825   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
04826   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
04827   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
04828   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)
04829   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)
04830   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)
04831   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)
04832   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)
04833   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)
04834   *
04835   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
04836   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
04837   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.
04838   * @retval None
04839   */
04840 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
04841 {
04842   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
04843   /* in register and register position depending on parameter "AWDy".         */
04844   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
04845   /* containing other bits reserved for other purpose.                        */
04846   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
04847                                                       + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04848
04849   MODIFY_REG(*preg,
04850              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
04851              AWDChannelGroup & AWDy);
04852 }
04853
04854 /**
04855   * @brief  Get ADC analog watchdog monitored channel.
04856   * @note   Usage of the returned channel number:
04857   *         - To reinject this channel into another function LL_ADC_xxx:
04858   *           the returned channel number is only partly formatted on definition
04859   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04860   *           with parts of literals LL_ADC_CHANNEL_x or using
04861   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04862   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04863   *           as parameter for another function.
04864   *         - To get the channel number in decimal format:
04865   *           process the returned value with the helper macro
04866   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04867   *           Applicable only when the analog watchdog is set to monitor
04868   *           one channel.
04869   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04870   *         instance:
04871   *         - AWD standard (instance AWD1):
04872   *           - channels monitored: can monitor 1 channel or all channels.
04873   *           - groups monitored: ADC groups regular and-or injected.
04874   *           - resolution: resolution is not limited (corresponds to
04875   *             ADC resolution configured).
04876   *         - AWD flexible (instances AWD2, AWD3):
04877   *           - channels monitored: flexible on channels monitored, selection is
04878   *             channel wise, from from 1 to all channels.
04879   *             Specificity of this analog watchdog: Multiple channels can
04880   *             be selected. For example:
04881   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04882   *           - groups monitored: not selection possible (monitoring on both
04883   *             groups regular and injected).
04884   *             Channels selected are monitored on groups regular and injected:
04885   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04886   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04887   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04888   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04889   *             the 2 LSB are ignored.
04890   * @note   On this STM32 serie, setting of this feature is conditioned to
04891   *         ADC state:
04892   *         ADC must be disabled or enabled without conversion on going
04893   *         on either groups regular or injected.
04894   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
04895   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
04896   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
04897   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
04898   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
04899   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
04900   * @param  ADCx ADC instance
04901   * @param  AWDy This parameter can be one of the following values:
04902   *         @arg @ref LL_ADC_AWD1
04903   *         @arg @ref LL_ADC_AWD2 (1)
04904   *         @arg @ref LL_ADC_AWD3 (1)
04905   *
04906   *         (1) On this AWD number, monitored channel can be retrieved
04907   *             if only 1 channel is programmed (or none or all channels).
04908   *             This function cannot retrieve monitored channel if
04909   *             multiple channels are programmed simultaneously
04910   *             by bitfield.
04911   * @retval Returned value can be one of the following values:
04912   *         @arg @ref LL_ADC_AWD_DISABLE
04913   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04914   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04915   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04916   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04917   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04918   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04919   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04920   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04921   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04922   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04923   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04924   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04925   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04926   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04927   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04928   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04929   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04930   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04931   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04932   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04933   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04934   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04935   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04936   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04937   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04938   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04939   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04940   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04941   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04942   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04943   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04944   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04945   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04946   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04947   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04948   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04949   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04950   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04951   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04952   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04953   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04954   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04955   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04956   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04957   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04958   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04959   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04960   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04961   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04962   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04963   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04964   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04965   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04966   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04967   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04968   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04969   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04970   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04971   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04972   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04973   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
04974   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
04975   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
04976   *
04977   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.
04978   */
04979 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
04980 {
04981   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
04982                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04983
04984   register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
04985
04986   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
04987   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
04988   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
04989   /* or a single channel.                                                     */
04990   if (AnalogWDMonitChannels != 0UL)
04991   {
04992     if (AWDy == LL_ADC_AWD1)
04993     {
04994       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
04995       {
04996         /* AWD monitoring a group of channels */
04997         AnalogWDMonitChannels = ((AnalogWDMonitChannels
04998                                   | (ADC_AWD_CR23_CHANNEL_MASK)
04999                                  )
05000                                  & (~(ADC_CFGR_AWD1CH))
05001                                 );
05002       }
05003       else
05004       {
05005         /* AWD monitoring a single channel */
05006         AnalogWDMonitChannels = (AnalogWDMonitChannels
05007                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
05008                                 );
05009       }
05010     }
05011     else
05012     {
05013       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
05014       {
05015         /* AWD monitoring a group of channels */
05016         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
05017                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
05018                                 );
05019       }
05020       else
05021       {
05022         /* AWD monitoring a single channel */
05023         /* AWD monitoring a group of channels */
05024         AnalogWDMonitChannels = (AnalogWDMonitChannels
05025                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
05026                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
05027                                 );
05028       }
05029     }
05030   }
05031
05032   return AnalogWDMonitChannels;
05033 }
05034
05035 /**
05036   * @brief  Set ADC analog watchdog threshold value of threshold
05037   *         high or low.
05038   * @note   In case of ADC resolution different of 12 bits,
05039   *         analog watchdog thresholds data require a specific shift.
05040   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
05041   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05042   *         instance:
05043   *         - AWD standard (instance AWD1):
05044   *           - channels monitored: can monitor 1 channel or all channels.
05045   *           - groups monitored: ADC groups regular and-or injected.
05046   *           - resolution: resolution is not limited (corresponds to
05047   *             ADC resolution configured).
05048   *         - AWD flexible (instances AWD2, AWD3):
05049   *           - channels monitored: flexible on channels monitored, selection is
05050   *             channel wise, from from 1 to all channels.
05051   *             Specificity of this analog watchdog: Multiple channels can
05052   *             be selected. For example:
05053   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05054   *           - groups monitored: not selection possible (monitoring on both
05055   *             groups regular and injected).
05056   *             Channels selected are monitored on groups regular and injected:
05057   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05058   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05059   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05060   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05061   *             the 2 LSB are ignored.
05062   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
05063   *         impacted: the comparison of analog watchdog thresholds is done
05064   *         on oversampling intermediate computation (after ratio, before shift
05065   *         application): intermediate register bitfield [32:7]
05066   *         (26 most significant bits).
05067   * @note   On this STM32 serie, setting of this feature is conditioned to
05068   *         ADC state:
05069   *         ADC must be disabled or enabled without conversion on going
05070   *         on either ADC groups regular or injected.
05071   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
05072   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
05073   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
05074   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
05075   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
05076   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
05077   * @param  ADCx ADC instance
05078   * @param  AWDy This parameter can be one of the following values:
05079   *         @arg @ref LL_ADC_AWD1
05080   *         @arg @ref LL_ADC_AWD2
05081   *         @arg @ref LL_ADC_AWD3
05082   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05083   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05084   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05085   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
05086   * @retval None
05087   */
05088 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
05089                                                   uint32_t AWDThresholdValue)
05090 {
05091   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
05092   /* position in register and register position depending on parameters       */
05093   /* "AWDThresholdsHighLow" and "AWDy".                                       */
05094   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
05095   /* containing other bits reserved for other purpose.                        */
05096   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
05097                                                              + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
05098                                                              + (AWDThresholdsHighLow));
05099
05100   MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
05101 }
05102
05103 /**
05104   * @brief  Get ADC analog watchdog threshold value of threshold high,
05105   *         threshold low or raw data with ADC thresholds high and low
05106   *         concatenated.
05107   * @note   In case of ADC resolution different of 12 bits,
05108   *         analog watchdog thresholds data require a specific shift.
05109   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
05110   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
05111   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
05112   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
05113   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
05114   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
05115   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
05116   * @param  ADCx ADC instance
05117   * @param  AWDy This parameter can be one of the following values:
05118   *         @arg @ref LL_ADC_AWD1
05119   *         @arg @ref LL_ADC_AWD2
05120   *         @arg @ref LL_ADC_AWD3
05121   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05122   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05123   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05124   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
05125   */
05126 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
05127 {
05128   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
05129                                                                    + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
05130                                                                    + (AWDThresholdsHighLow));
05131
05132   return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
05133 }
05134
05135 /**
05136   * @}
05137   */
05138
05139 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
05140   * @{
05141   */
05142
05143 /**
05144   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
05145   *         (availability of ADC group injected depends on STM32 families).
05146   * @note   If both groups regular and injected are selected,
05147   *         specify behavior of ADC group injected interrupting
05148   *         group regular: when ADC group injected is triggered,
05149   *         the oversampling on ADC group regular is either
05150   *         temporary stopped and continued, or resumed from start
05151   *         (oversampler buffer reset).
05152   * @note   On this STM32 serie, setting of this feature is conditioned to
05153   *         ADC state:
05154   *         ADC must be disabled or enabled without conversion on going
05155   *         on either groups regular or injected.
05156   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
05157   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
05158   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
05159   * @param  ADCx ADC instance
05160   * @param  OvsScope This parameter can be one of the following values:
05161   *         @arg @ref LL_ADC_OVS_DISABLE
05162   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
05163   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
05164   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
05165   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
05166   * @retval None
05167   */
05168 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
05169 {
05170   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
05171 }
05172
05173 /**
05174   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
05175   *         (availability of ADC group injected depends on STM32 families).
05176   * @note   If both groups regular and injected are selected,
05177   *         specify behavior of ADC group injected interrupting
05178   *         group regular: when ADC group injected is triggered,
05179   *         the oversampling on ADC group regular is either
05180   *         temporary stopped and continued, or resumed from start
05181   *         (oversampler buffer reset).
05182   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
05183   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
05184   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
05185   * @param  ADCx ADC instance
05186   * @retval Returned value can be one of the following values:
05187   *         @arg @ref LL_ADC_OVS_DISABLE
05188   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
05189   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
05190   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
05191   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
05192   */
05193 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
05194 {
05195   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
05196 }
05197
05198 /**
05199   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
05200   *         on the selected ADC group.
05201   * @note   Number of oversampled conversions are done either in:
05202   *         - continuous mode (all conversions of oversampling ratio
05203   *           are done from 1 trigger)
05204   *         - discontinuous mode (each conversion of oversampling ratio
05205   *           needs a trigger)
05206   * @note   On this STM32 serie, setting of this feature is conditioned to
05207   *         ADC state:
05208   *         ADC must be disabled or enabled without conversion on going
05209   *         on group regular.
05210   * @note   On this STM32 serie, oversampling discontinuous mode
05211   *         (triggered mode) can be used only when oversampling is
05212   *         set on group regular only and in resumed mode.
05213   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
05214   * @param  ADCx ADC instance
05215   * @param  OverSamplingDiscont This parameter can be one of the following values:
05216   *         @arg @ref LL_ADC_OVS_REG_CONT
05217   *         @arg @ref LL_ADC_OVS_REG_DISCONT
05218   * @retval None
05219   */
05220 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
05221 {
05222   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
05223 }
05224
05225 /**
05226   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
05227   *         on the selected ADC group.
05228   * @note   Number of oversampled conversions are done either in:
05229   *         - continuous mode (all conversions of oversampling ratio
05230   *           are done from 1 trigger)
05231   *         - discontinuous mode (each conversion of oversampling ratio
05232   *           needs a trigger)
05233   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
05234   * @param  ADCx ADC instance
05235   * @retval Returned value can be one of the following values:
05236   *         @arg @ref LL_ADC_OVS_REG_CONT
05237   *         @arg @ref LL_ADC_OVS_REG_DISCONT
05238   */
05239 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
05240 {
05241   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
05242 }
05243
05244 /**
05245   * @brief  Set ADC oversampling
05246   *         (impacting both ADC groups regular and injected)
05247   * @note   This function set the 2 items of oversampling configuration:
05248   *         - ratio
05249   *         - shift
05250   * @note   On this STM32 serie, setting of this feature is conditioned to
05251   *         ADC state:
05252   *         ADC must be disabled or enabled without conversion on going
05253   *         on either groups regular or injected.
05254   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
05255   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
05256   * @param  ADCx ADC instance
05257   * @param  Ratio This parameter can be in the range from 1 to 1024.
05258   * @param  Shift This parameter can be one of the following values:
05259   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
05260   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
05261   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
05262   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
05263   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
05264   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
05265   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
05266   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
05267   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
05268   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
05269   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
05270   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
05271   * @retval None
05272   */
05273 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
05274 {
05275   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
05276 }
05277
05278 /**
05279   * @brief  Get ADC oversampling ratio
05280   *        (impacting both ADC groups regular and injected)
05281   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
05282   * @param  ADCx ADC instance
05283   * @retval Ratio This parameter can be in the from 1 to 1024.
05284   */
05285 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
05286 {
05287   return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
05288 }
05289
05290 /**
05291   * @brief  Get ADC oversampling shift
05292   *        (impacting both ADC groups regular and injected)
05293   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
05294   * @param  ADCx ADC instance
05295   * @retval Shift This parameter can be one of the following values:
05296   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
05297   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
05298   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
05299   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
05300   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
05301   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
05302   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
05303   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
05304   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
05305   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
05306   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
05307   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
05308   */
05309 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
05310 {
05311   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
05312 }
05313
05314 /**
05315   * @}
05316   */
05317
05318 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
05319   * @{
05320   */
05321 /**
05322   * @brief  Set ADC boost mode.
05323   * @note   On this STM32 serie, setting of this feature is conditioned to
05324   *         ADC state:
05325   *         ADC boost must be configured, without calibration on going, without conversion
05326   *         on going on group regular.
05327   * @rmtoll CR  BOOST      LL_ADC_SetBoostMode
05328   * @param  ADCx ADC instance
05329   * @param  BoostMode This parameter can be one of the following values:
05330   *         @arg @ref LL_ADC_BOOST_MODE_6MHZ25
05331   *         @arg @ref LL_ADC_BOOST_MODE_12MHZ5
05332   *         @arg @ref LL_ADC_BOOST_MODE_20MHZ
05333   *         @arg @ref LL_ADC_BOOST_MODE_25MHZ
05334   *         @arg @ref LL_ADC_BOOST_MODE_50MHZ
05335   * @retval None
05336   */
05337 __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
05338 {
05339   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
05340   {
05341     MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
05342   }
05343   else /* Cut 2.x */
05344   {
05345     MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
05346   }
05347 }
05348
05349 /**
05350   * @brief  Get ADC boost mode.
05351   * @note   On this STM32 serie, setting of this feature is conditioned to
05352   *         ADC state:
05353   *         ADC boost must be configured, without calibration on going, without conversion
05354   *         on going on group regular.
05355   * @rmtoll CR  BOOST      LL_ADC_GetBoostMode
05356   * @param  ADCx ADC instance
05357   * @retval 0: Boost disabled 1: Boost enabled
05358   */
05359 __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
05360 {
05361   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
05362   {
05363     return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
05364   }
05365   else /* Cut 2.x */
05366   {
05367     return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
05368   }
05369 }
05370
05371 /**
05372   * @brief  Set ADC multimode configuration to operate in independent mode
05373   *         or multimode (for devices with several ADC instances).
05374   * @note   If multimode configuration: the selected ADC instance is
05375   *         either master or slave depending on hardware.
05376   *         Refer to reference manual.
05377   * @note   On this STM32 serie, setting of this feature is conditioned to
05378   *         ADC state:
05379   *         All ADC instances of the ADC common group must be disabled.
05380   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05381   *         ADC instance or by using helper macro
05382   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05383   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
05384   * @param  ADCxy_COMMON ADC common instance
05385   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05386   * @param  Multimode This parameter can be one of the following values:
05387   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05388   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05389   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05390   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05391   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05392   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05393   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05394   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05395   * @retval None
05396   */
05397 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
05398 {
05399   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
05400 }
05401
05402 /**
05403   * @brief  Get ADC multimode configuration to operate in independent mode
05404   *         or multimode (for devices with several ADC instances).
05405   * @note   If multimode configuration: the selected ADC instance is
05406   *         either master or slave depending on hardware.
05407   *         Refer to reference manual.
05408   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
05409   * @param  ADCxy_COMMON ADC common instance
05410   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05411   * @retval Returned value can be one of the following values:
05412   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05413   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05414   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05415   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05416   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05417   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05418   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05419   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05420   */
05421 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
05422 {
05423   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
05424 }
05425
05426 /**
05427   * @brief  Set ADC multimode conversion data transfer: no transfer
05428   *         or transfer by DMA.
05429   * @note   If ADC multimode transfer by DMA is not selected:
05430   *         each ADC uses its own DMA channel, with its individual
05431   *         DMA transfer settings.
05432   *         If ADC multimode transfer by DMA is selected:
05433   *         One DMA channel is used for both ADC (DMA of ADC master)
05434   *         Specifies the DMA requests mode:
05435   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05436   *           when number of DMA data transfers (number of
05437   *           ADC conversions) is reached.
05438   *           This ADC mode is intended to be used with DMA mode non-circular.
05439   *         - Unlimited mode: DMA transfer requests are unlimited,
05440   *           whatever number of DMA data transfers (number of
05441   *           ADC conversions).
05442   *           This ADC mode is intended to be used with DMA mode circular.
05443   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05444   *         mode non-circular:
05445   *         when DMA transfers size will be reached, DMA will stop transfers of
05446   *         ADC conversions data ADC will raise an overrun error
05447   *         (overrun flag and interruption if enabled).
05448   * @note   How to retrieve multimode conversion data:
05449   *         Whatever multimode transfer by DMA setting: using function
05450   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05451   *         If ADC multimode transfer by DMA is selected: conversion data
05452   *         is a raw data with ADC master and slave concatenated.
05453   *         A macro is available to get the conversion data of
05454   *         ADC master or ADC slave: see helper macro
05455   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05456   * @note   On this STM32 serie, setting of this feature is conditioned to
05457   *         ADC state:
05458   *         All ADC instances of the ADC common group must be disabled
05459   *         or enabled without conversion on going on group regular.
05460   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n
05461   * @param  ADCxy_COMMON ADC common instance
05462   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05463   * @param  MultiDMATransfer This parameter can be one of the following values:
05464   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05465   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
05466   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
05467   * @retval None
05468   */
05469 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
05470 {
05471   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
05472 }
05473
05474 /**
05475   * @brief  Get ADC multimode conversion data transfer: no transfer
05476   *         or transfer by DMA.
05477   * @note   If ADC multimode transfer by DMA is not selected:
05478   *         each ADC uses its own DMA channel, with its individual
05479   *         DMA transfer settings.
05480   *         If ADC multimode transfer by DMA is selected:
05481   *         One DMA channel is used for both ADC (DMA of ADC master)
05482   *         Specifies the DMA requests mode:
05483   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05484   *           when number of DMA data transfers (number of
05485   *           ADC conversions) is reached.
05486   *           This ADC mode is intended to be used with DMA mode non-circular.
05487   *         - Unlimited mode: DMA transfer requests are unlimited,
05488   *           whatever number of DMA data transfers (number of
05489   *           ADC conversions).
05490   *           This ADC mode is intended to be used with DMA mode circular.
05491   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05492   *         mode non-circular:
05493   *         when DMA transfers size will be reached, DMA will stop transfers of
05494   *         ADC conversions data ADC will raise an overrun error
05495   *         (overrun flag and interruption if enabled).
05496   * @note   How to retrieve multimode conversion data:
05497   *         Whatever multimode transfer by DMA setting: using function
05498   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05499   *         If ADC multimode transfer by DMA is selected: conversion data
05500   *         is a raw data with ADC master and slave concatenated.
05501   *         A macro is available to get the conversion data of
05502   *         ADC master or ADC slave: see helper macro
05503   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05504   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n
05505   * @param  ADCxy_COMMON ADC common instance
05506   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05507   * @retval Returned value can be one of the following values:
05508   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05509   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
05510   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
05511   */
05512 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
05513 {
05514   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
05515 }
05516
05517 /**
05518   * @brief  Set ADC multimode delay between 2 sampling phases.
05519   * @note   The sampling delay range depends on ADC resolution:
05520   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
05521   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
05522   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
05523   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
05524   * @note   On this STM32 serie, setting of this feature is conditioned to
05525   *         ADC state:
05526   *         All ADC instances of the ADC common group must be disabled.
05527   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05528   *         ADC instance or by using helper macro helper macro
05529   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05530   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
05531   * @param  ADCxy_COMMON ADC common instance
05532   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05533   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
05534   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
05535   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
05536   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
05537   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
05538   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
05539   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
05540   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
05541   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)
05542   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
05543   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
05544   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
05545   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)
05546   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)
05547   *
05548   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
05549   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.
05550   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.
05551   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.
05552   *         (5) Parameter available only if ADC resolution is 16 bits.
05553   *         (6) Parameter available only if ADC resolution is 12 bits.
05554   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.
05555   * @retval None
05556   */
05557 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
05558 {
05559   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
05560 }
05561
05562 /**
05563   * @brief  Get ADC multimode delay between 2 sampling phases.
05564   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
05565   * @param  ADCxy_COMMON ADC common instance
05566   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05567   * @retval Returned value can be one of the following values:
05568   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
05569   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
05570   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
05571   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
05572   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
05573   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
05574   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
05575   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)
05576   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
05577   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
05578   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
05579   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)
05580   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)
05581   *
05582   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
05583   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.
05584   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.
05585   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.
05586   *         (5) Parameter available only if ADC resolution is 16 bits.
05587   *         (6) Parameter available only if ADC resolution is 12 bits.
05588   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.
05589   */
05590 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
05591 {
05592   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
05593 }
05594
05595 /**
05596   * @}
05597   */
05598 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
05599   * @{
05600   */
05601
05602 /**
05603   * @brief  Put ADC instance in deep power down state.
05604   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05605   *         state, the internal analog calibration is lost. After exiting from
05606   *         deep power down, calibration must be relaunched or calibration factor
05607   *         (preliminarily saved) must be set back into calibration register.
05608   * @note   On this STM32 serie, setting of this feature is conditioned to
05609   *         ADC state:
05610   *         ADC must be ADC disabled.
05611   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
05612   * @param  ADCx ADC instance
05613   * @retval None
05614   */
05615 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
05616 {
05617   /* Note: Write register with some additional bits forced to state reset     */
05618   /*       instead of modifying only the selected bit for this function,      */
05619   /*       to not interfere with bits with HW property "rs".                  */
05620   MODIFY_REG(ADCx->CR,
05621              ADC_CR_BITS_PROPERTY_RS,
05622              ADC_CR_DEEPPWD);
05623 }
05624
05625 /**
05626   * @brief  Disable ADC deep power down mode.
05627   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05628   *         state, the internal analog calibration is lost. After exiting from
05629   *         deep power down, calibration must be relaunched or calibration factor
05630   *         (preliminarily saved) must be set back into calibration register.
05631   * @note   On this STM32 serie, setting of this feature is conditioned to
05632   *         ADC state:
05633   *         ADC must be ADC disabled.
05634   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
05635   * @param  ADCx ADC instance
05636   * @retval None
05637   */
05638 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
05639 {
05640   /* Note: Write register with some additional bits forced to state reset     */
05641   /*       instead of modifying only the selected bit for this function,      */
05642   /*       to not interfere with bits with HW property "rs".                  */
05643   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
05644 }
05645
05646 /**
05647   * @brief  Get the selected ADC instance deep power down state.
05648   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
05649   * @param  ADCx ADC instance
05650   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
05651   */
05652 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
05653 {
05654   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
05655 }
05656
05657 /**
05658   * @brief  Enable ADC instance internal voltage regulator.
05659   * @note   On this STM32 serie, after ADC internal voltage regulator enable,
05660   *         a delay for ADC internal voltage regulator stabilization
05661   *         is required before performing a ADC calibration or ADC enable.
05662   *         Refer to device datasheet, parameter tADCVREG_STUP.
05663   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
05664   * @note   On this STM32 serie, setting of this feature is conditioned to
05665   *         ADC state:
05666   *         ADC must be ADC disabled.
05667   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
05668   * @param  ADCx ADC instance
05669   * @retval None
05670   */
05671 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
05672 {
05673   /* Note: Write register with some additional bits forced to state reset     */
05674   /*       instead of modifying only the selected bit for this function,      */
05675   /*       to not interfere with bits with HW property "rs".                  */
05676   MODIFY_REG(ADCx->CR,
05677              ADC_CR_BITS_PROPERTY_RS,
05678              ADC_CR_ADVREGEN);
05679 }
05680
05681 /**
05682   * @brief  Disable ADC internal voltage regulator.
05683   * @note   On this STM32 serie, setting of this feature is conditioned to
05684   *         ADC state:
05685   *         ADC must be ADC disabled.
05686   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
05687   * @param  ADCx ADC instance
05688   * @retval None
05689   */
05690 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
05691 {
05692   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
05693 }
05694
05695 /**
05696   * @brief  Get the selected ADC instance internal voltage regulator state.
05697   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
05698   * @param  ADCx ADC instance
05699   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
05700   */
05701 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
05702 {
05703   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
05704 }
05705
05706 /**
05707   * @brief  Enable the selected ADC instance.
05708   * @note   On this STM32 serie, after ADC enable, a delay for
05709   *         ADC internal analog stabilization is required before performing a
05710   *         ADC conversion start.
05711   *         Refer to device datasheet, parameter tSTAB.
05712   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05713   *         is enabled and when conversion clock is active.
05714   *         (not only core clock: this ADC has a dual clock domain)
05715   * @note   On this STM32 serie, setting of this feature is conditioned to
05716   *         ADC state:
05717   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
05718   * @rmtoll CR       ADEN           LL_ADC_Enable
05719   * @param  ADCx ADC instance
05720   * @retval None
05721   */
05722 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
05723 {
05724   /* Note: Write register with some additional bits forced to state reset     */
05725   /*       instead of modifying only the selected bit for this function,      */
05726   /*       to not interfere with bits with HW property "rs".                  */
05727   MODIFY_REG(ADCx->CR,
05728              ADC_CR_BITS_PROPERTY_RS,
05729              ADC_CR_ADEN);
05730 }
05731
05732 /**
05733   * @brief  Disable the selected ADC instance.
05734   * @note   On this STM32 serie, setting of this feature is conditioned to
05735   *         ADC state:
05736   *         ADC must be not disabled. Must be enabled without conversion on going
05737   *         on either groups regular or injected.
05738   * @rmtoll CR       ADDIS          LL_ADC_Disable
05739   * @param  ADCx ADC instance
05740   * @retval None
05741   */
05742 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
05743 {
05744   /* Note: Write register with some additional bits forced to state reset     */
05745   /*       instead of modifying only the selected bit for this function,      */
05746   /*       to not interfere with bits with HW property "rs".                  */
05747   MODIFY_REG(ADCx->CR,
05748              ADC_CR_BITS_PROPERTY_RS,
05749              ADC_CR_ADDIS);
05750 }
05751
05752 /**
05753   * @brief  Get the selected ADC instance enable state.
05754   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05755   *         is enabled and when conversion clock is active.
05756   *         (not only core clock: this ADC has a dual clock domain)
05757   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
05758   * @param  ADCx ADC instance
05759   * @retval 0: ADC is disabled, 1: ADC is enabled.
05760   */
05761 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
05762 {
05763   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
05764 }
05765
05766 /**
05767   * @brief  Get the selected ADC instance disable state.
05768   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
05769   * @param  ADCx ADC instance
05770   * @retval 0: no ADC disable command on going.
05771   */
05772 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
05773 {
05774   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
05775 }
05776
05777 /**
05778   * @brief  Start ADC calibration in the mode single-ended
05779   *         or differential (for devices with differential mode available).
05780   * @note   On this STM32 serie, a minimum number of ADC clock cycles
05781   *         are required between ADC end of calibration and ADC enable.
05782   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
05783   * @note   Calibration duration:
05784   *         - Calibration of offset: 520 ADC clock cycles
05785   *         - Calibration of linearity: 131072 ADC clock cycles
05786   * @note   For devices with differential mode available:
05787   *         Calibration of offset is specific to each of
05788   *         single-ended and differential modes
05789   *         (calibration run must be performed for each of these
05790   *         differential modes, if used afterwards and if the application
05791   *         requires their calibration).
05792   *         Calibration of linearity is common to both
05793   *         single-ended and differential modes
05794   *         (calibration run can be performed only once).
05795   * @note   On this STM32 serie, setting of this feature is conditioned to
05796   *         ADC state:
05797   *         ADC must be ADC disabled.
05798   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
05799   *         CR       ADCALDIF       LL_ADC_StartCalibration\n
05800   *         CR       ADCALLIN       LL_ADC_StartCalibration
05801   * @param  ADCx ADC instance
05802   * @param  CalibrationMode This parameter can be one of the following values:
05803   *         @arg @ref LL_ADC_CALIB_OFFSET
05804   *         @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
05805   * @param  SingleDiff This parameter can be one of the following values:
05806   *         @arg @ref LL_ADC_SINGLE_ENDED
05807   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
05808   * @retval None
05809   */
05810 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
05811 {
05812   /* Note: Write register with some additional bits forced to state reset     */
05813   /*       instead of modifying only the selected bit for this function,      */
05814   /*       to not interfere with bits with HW property "rs".                  */
05815   MODIFY_REG(ADCx->CR,
05816              ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
05817              ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
05818 }
05819
05820 /**
05821   * @brief  Get ADC calibration state.
05822   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
05823   * @param  ADCx ADC instance
05824   * @retval 0: calibration complete, 1: calibration in progress.
05825   */
05826 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
05827 {
05828   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
05829 }
05830
05831 /**
05832   * @}
05833   */
05834
05835 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
05836   * @{
05837   */
05838
05839 /**
05840   * @brief  Start ADC group regular conversion.
05841   * @note   On this STM32 serie, this function is relevant for both
05842   *         internal trigger (SW start) and external trigger:
05843   *         - If ADC trigger has been set to software start, ADC conversion
05844   *           starts immediately.
05845   *         - If ADC trigger has been set to external trigger, ADC conversion
05846   *           will start at next trigger event (on the selected trigger edge)
05847   *           following the ADC start conversion command.
05848   * @note   On this STM32 serie, setting of this feature is conditioned to
05849   *         ADC state:
05850   *         ADC must be enabled without conversion on going on group regular,
05851   *         without conversion stop command on going on group regular,
05852   *         without ADC disable command on going.
05853   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
05854   * @param  ADCx ADC instance
05855   * @retval None
05856   */
05857 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
05858 {
05859   /* Note: Write register with some additional bits forced to state reset     */
05860   /*       instead of modifying only the selected bit for this function,      */
05861   /*       to not interfere with bits with HW property "rs".                  */
05862   MODIFY_REG(ADCx->CR,
05863              ADC_CR_BITS_PROPERTY_RS,
05864              ADC_CR_ADSTART);
05865 }
05866
05867 /**
05868   * @brief  Stop ADC group regular conversion.
05869   * @note   On this STM32 serie, setting of this feature is conditioned to
05870   *         ADC state:
05871   *         ADC must be enabled with conversion on going on group regular,
05872   *         without ADC disable command on going.
05873   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
05874   * @param  ADCx ADC instance
05875   * @retval None
05876   */
05877 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
05878 {
05879   /* Note: Write register with some additional bits forced to state reset     */
05880   /*       instead of modifying only the selected bit for this function,      */
05881   /*       to not interfere with bits with HW property "rs".                  */
05882   MODIFY_REG(ADCx->CR,
05883              ADC_CR_BITS_PROPERTY_RS,
05884              ADC_CR_ADSTP);
05885 }
05886
05887 /**
05888   * @brief  Get ADC group regular conversion state.
05889   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
05890   * @param  ADCx ADC instance
05891   * @retval 0: no conversion is on going on ADC group regular.
05892   */
05893 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
05894 {
05895   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
05896 }
05897
05898 /**
05899   * @brief  Get ADC group regular command of conversion stop state
05900   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
05901   * @param  ADCx ADC instance
05902   * @retval 0: no command of conversion stop is on going on ADC group regular.
05903   */
05904 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05905 {
05906   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
05907 }
05908
05909 /**
05910   * @brief  Get ADC group regular conversion data, range fit for
05911   *         all ADC configurations: all ADC resolutions and
05912   *         all oversampling increased data width (for devices
05913   *         with feature oversampling).
05914   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
05915   * @param  ADCx ADC instance
05916   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
05917   */
05918 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
05919 {
05920   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05921 }
05922
05923 /**
05924   * @brief  Get ADC group regular conversion data, range fit for
05925   *         ADC resolution 16 bits.
05926   * @note   For devices with feature oversampling: Oversampling
05927   *         can increase data width, function for extended range
05928   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05929   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData16
05930   * @param  ADCx ADC instance
05931   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
05932   */
05933 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
05934 {
05935   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05936 }
05937
05938 /**
05939   * @brief  Get ADC group regular conversion data, range fit for
05940   *         ADC resolution 14 bits.
05941   * @note   For devices with feature oversampling: Oversampling
05942   *         can increase data width, function for extended range
05943   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05944   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData14
05945   * @param  ADCx ADC instance
05946   * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
05947   */
05948 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
05949 {
05950   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05951 }
05952
05953 /**
05954   * @brief  Get ADC group regular conversion data, range fit for
05955   *         ADC resolution 12 bits.
05956   * @note   For devices with feature oversampling: Oversampling
05957   *         can increase data width, function for extended range
05958   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05959   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
05960   * @param  ADCx ADC instance
05961   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
05962   */
05963 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
05964 {
05965   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05966 }
05967
05968 /**
05969   * @brief  Get ADC group regular conversion data, range fit for
05970   *         ADC resolution 10 bits.
05971   * @note   For devices with feature oversampling: Oversampling
05972   *         can increase data width, function for extended range
05973   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05974   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
05975   * @param  ADCx ADC instance
05976   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
05977   */
05978 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
05979 {
05980   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05981 }
05982
05983 /**
05984   * @brief  Get ADC group regular conversion data, range fit for
05985   *         ADC resolution 8 bits.
05986   * @note   For devices with feature oversampling: Oversampling
05987   *         can increase data width, function for extended range
05988   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05989   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
05990   * @param  ADCx ADC instance
05991   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
05992   */
05993 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
05994 {
05995   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05996 }
05997 /**
05998   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
05999   *         or raw data with ADC master and slave concatenated.
06000   * @note   If raw data with ADC master and slave concatenated is retrieved,
06001   *         a macro is available to get the conversion data of
06002   *         ADC master or ADC slave: see helper macro
06003   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
06004   *         (however this macro is mainly intended for multimode
06005   *         transfer by DMA, because this function can do the same
06006   *         by getting multimode conversion data of ADC master or ADC slave
06007   *         separately).
06008   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
06009   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
06010   * @param  ADCxy_COMMON ADC common instance
06011   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06012   * @param  ConversionData This parameter can be one of the following values:
06013   *         @arg @ref LL_ADC_MULTI_MASTER
06014   *         @arg @ref LL_ADC_MULTI_SLAVE
06015   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
06016   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06017   */
06018 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
06019 {
06020   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
06021                              ConversionData)
06022                     >> (POSITION_VAL(ConversionData) & 0x1FUL)
06023                    );
06024 }
06025
06026 /**
06027   * @}
06028   */
06029
06030 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
06031   * @{
06032   */
06033
06034 /**
06035   * @brief  Start ADC group injected conversion.
06036   * @note   On this STM32 serie, this function is relevant for both
06037   *         internal trigger (SW start) and external trigger:
06038   *         - If ADC trigger has been set to software start, ADC conversion
06039   *           starts immediately.
06040   *         - If ADC trigger has been set to external trigger, ADC conversion
06041   *           will start at next trigger event (on the selected trigger edge)
06042   *           following the ADC start conversion command.
06043   * @note   On this STM32 serie, setting of this feature is conditioned to
06044   *         ADC state:
06045   *         ADC must be enabled without conversion on going on group injected,
06046   *         without conversion stop command on going on group injected,
06047   *         without ADC disable command on going.
06048   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
06049   * @param  ADCx ADC instance
06050   * @retval None
06051   */
06052 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
06053 {
06054   /* Note: Write register with some additional bits forced to state reset     */
06055   /*       instead of modifying only the selected bit for this function,      */
06056   /*       to not interfere with bits with HW property "rs".                  */
06057   MODIFY_REG(ADCx->CR,
06058              ADC_CR_BITS_PROPERTY_RS,
06059              ADC_CR_JADSTART);
06060 }
06061
06062 /**
06063   * @brief  Stop ADC group injected conversion.
06064   * @note   On this STM32 serie, setting of this feature is conditioned to
06065   *         ADC state:
06066   *         ADC must be enabled with conversion on going on group injected,
06067   *         without ADC disable command on going.
06068   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
06069   * @param  ADCx ADC instance
06070   * @retval None
06071   */
06072 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
06073 {
06074   /* Note: Write register with some additional bits forced to state reset     */
06075   /*       instead of modifying only the selected bit for this function,      */
06076   /*       to not interfere with bits with HW property "rs".                  */
06077   MODIFY_REG(ADCx->CR,
06078              ADC_CR_BITS_PROPERTY_RS,
06079              ADC_CR_JADSTP);
06080 }
06081
06082 /**
06083   * @brief  Get ADC group injected conversion state.
06084   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
06085   * @param  ADCx ADC instance
06086   * @retval 0: no conversion is on going on ADC group injected.
06087   */
06088 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
06089 {
06090   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
06091 }
06092
06093 /**
06094   * @brief  Get ADC group injected command of conversion stop state
06095   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
06096   * @param  ADCx ADC instance
06097   * @retval 0: no command of conversion stop is on going on ADC group injected.
06098   */
06099 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
06100 {
06101   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
06102 }
06103
06104 /**
06105   * @brief  Get ADC group injected conversion data, range fit for
06106   *         all ADC configurations: all ADC resolutions and
06107   *         all oversampling increased data width (for devices
06108   *         with feature oversampling).
06109   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
06110   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
06111   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
06112   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
06113   * @param  ADCx ADC instance
06114   * @param  Rank This parameter can be one of the following values:
06115   *         @arg @ref LL_ADC_INJ_RANK_1
06116   *         @arg @ref LL_ADC_INJ_RANK_2
06117   *         @arg @ref LL_ADC_INJ_RANK_3
06118   *         @arg @ref LL_ADC_INJ_RANK_4
06119   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06120   */
06121 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
06122 {
06123   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06124
06125   return (uint32_t)(READ_BIT(*preg,
06126                              ADC_JDR1_JDATA)
06127                    );
06128 }
06129
06130 /**
06131   * @brief  Get ADC group injected conversion data, range fit for
06132   *         ADC resolution 16 bits.
06133   * @note   For devices with feature oversampling: Oversampling
06134   *         can increase data width, function for extended range
06135   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06136   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData16\n
06137   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData16\n
06138   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData16\n
06139   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData16
06140   * @param  ADCx ADC instance
06141   * @param  Rank This parameter can be one of the following values:
06142   *         @arg @ref LL_ADC_INJ_RANK_1
06143   *         @arg @ref LL_ADC_INJ_RANK_2
06144   *         @arg @ref LL_ADC_INJ_RANK_3
06145   *         @arg @ref LL_ADC_INJ_RANK_4
06146   * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
06147   */
06148 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
06149 {
06150   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06151
06152   return (uint16_t)(READ_BIT(*preg,
06153                              ADC_JDR1_JDATA)
06154                    );
06155 }
06156
06157 /**
06158   * @brief  Get ADC group injected conversion data, range fit for
06159   *         ADC resolution 14 bits.
06160   * @note   For devices with feature oversampling: Oversampling
06161   *         can increase data width, function for extended range
06162   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06163   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData14\n
06164   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData14\n
06165   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData14\n
06166   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData14
06167   * @param  ADCx ADC instance
06168   * @param  Rank This parameter can be one of the following values:
06169   *         @arg @ref LL_ADC_INJ_RANK_1
06170   *         @arg @ref LL_ADC_INJ_RANK_2
06171   *         @arg @ref LL_ADC_INJ_RANK_3
06172   *         @arg @ref LL_ADC_INJ_RANK_4
06173   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
06174   */
06175 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
06176 {
06177   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06178
06179   return (uint16_t)(READ_BIT(*preg,
06180                              ADC_JDR1_JDATA)
06181                    );
06182 }
06183
06184 /**
06185   * @brief  Get ADC group injected conversion data, range fit for
06186   *         ADC resolution 12 bits.
06187   * @note   For devices with feature oversampling: Oversampling
06188   *         can increase data width, function for extended range
06189   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06190   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
06191   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
06192   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
06193   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
06194   * @param  ADCx ADC instance
06195   * @param  Rank This parameter can be one of the following values:
06196   *         @arg @ref LL_ADC_INJ_RANK_1
06197   *         @arg @ref LL_ADC_INJ_RANK_2
06198   *         @arg @ref LL_ADC_INJ_RANK_3
06199   *         @arg @ref LL_ADC_INJ_RANK_4
06200   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
06201   */
06202 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
06203 {
06204   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06205
06206   return (uint16_t)(READ_BIT(*preg,
06207                              ADC_JDR1_JDATA)
06208                    );
06209 }
06210
06211 /**
06212   * @brief  Get ADC group injected conversion data, range fit for
06213   *         ADC resolution 10 bits.
06214   * @note   For devices with feature oversampling: Oversampling
06215   *         can increase data width, function for extended range
06216   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06217   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
06218   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
06219   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
06220   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
06221   * @param  ADCx ADC instance
06222   * @param  Rank This parameter can be one of the following values:
06223   *         @arg @ref LL_ADC_INJ_RANK_1
06224   *         @arg @ref LL_ADC_INJ_RANK_2
06225   *         @arg @ref LL_ADC_INJ_RANK_3
06226   *         @arg @ref LL_ADC_INJ_RANK_4
06227   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
06228   */
06229 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
06230 {
06231   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06232
06233   return (uint16_t)(READ_BIT(*preg,
06234                              ADC_JDR1_JDATA)
06235                    );
06236 }
06237
06238 /**
06239   * @brief  Get ADC group injected conversion data, range fit for
06240   *         ADC resolution 8 bits.
06241   * @note   For devices with feature oversampling: Oversampling
06242   *         can increase data width, function for extended range
06243   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06244   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
06245   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
06246   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
06247   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
06248   * @param  ADCx ADC instance
06249   * @param  Rank This parameter can be one of the following values:
06250   *         @arg @ref LL_ADC_INJ_RANK_1
06251   *         @arg @ref LL_ADC_INJ_RANK_2
06252   *         @arg @ref LL_ADC_INJ_RANK_3
06253   *         @arg @ref LL_ADC_INJ_RANK_4
06254   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
06255   */
06256 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
06257 {
06258   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
06259
06260   return (uint8_t)(READ_BIT(*preg,
06261                             ADC_JDR1_JDATA)
06262                   );
06263 }
06264
06265 /**
06266   * @}
06267   */
06268
06269 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
06270   * @{
06271   */
06272
06273 /**
06274   * @brief  Get flag ADC ready.
06275   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06276   *         is enabled and when conversion clock is active.
06277   *         (not only core clock: this ADC has a dual clock domain)
06278   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
06279   * @param  ADCx ADC instance
06280   * @retval State of bit (1 or 0).
06281   */
06282 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
06283 {
06284   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
06285 }
06286
06287 /**
06288   * @brief  Get flag ADC group regular end of unitary conversion.
06289   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
06290   * @param  ADCx ADC instance
06291   * @retval State of bit (1 or 0).
06292   */
06293 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
06294 {
06295   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
06296 }
06297
06298 /**
06299   * @brief  Get flag ADC group regular end of sequence conversions.
06300   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
06301   * @param  ADCx ADC instance
06302   * @retval State of bit (1 or 0).
06303   */
06304 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
06305 {
06306   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
06307 }
06308
06309 /**
06310   * @brief  Get flag ADC group regular overrun.
06311   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
06312   * @param  ADCx ADC instance
06313   * @retval State of bit (1 or 0).
06314   */
06315 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
06316 {
06317   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
06318 }
06319
06320 /**
06321   * @brief  Get flag ADC group regular end of sampling phase.
06322   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
06323   * @param  ADCx ADC instance
06324   * @retval State of bit (1 or 0).
06325   */
06326 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
06327 {
06328   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
06329 }
06330
06331 /**
06332   * @brief  Get flag ADC group injected end of unitary conversion.
06333   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
06334   * @param  ADCx ADC instance
06335   * @retval State of bit (1 or 0).
06336   */
06337 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
06338 {
06339   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
06340 }
06341
06342 /**
06343   * @brief  Get flag ADC group injected end of sequence conversions.
06344   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
06345   * @param  ADCx ADC instance
06346   * @retval State of bit (1 or 0).
06347   */
06348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
06349 {
06350   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
06351 }
06352
06353 /**
06354   * @brief  Get flag ADC group injected contexts queue overflow.
06355   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
06356   * @param  ADCx ADC instance
06357   * @retval State of bit (1 or 0).
06358   */
06359 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
06360 {
06361   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
06362 }
06363
06364 /**
06365   * @brief  Get flag ADC analog watchdog 1 flag
06366   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
06367   * @param  ADCx ADC instance
06368   * @retval State of bit (1 or 0).
06369   */
06370 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
06371 {
06372   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
06373 }
06374
06375 /**
06376   * @brief  Get flag ADC analog watchdog 2.
06377   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
06378   * @param  ADCx ADC instance
06379   * @retval State of bit (1 or 0).
06380   */
06381 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
06382 {
06383   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
06384 }
06385
06386 /**
06387   * @brief  Get flag ADC analog watchdog 3.
06388   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
06389   * @param  ADCx ADC instance
06390   * @retval State of bit (1 or 0).
06391   */
06392 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
06393 {
06394   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
06395 }
06396
06397 /**
06398   * @brief  Clear flag ADC ready.
06399   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06400   *         is enabled and when conversion clock is active.
06401   *         (not only core clock: this ADC has a dual clock domain)
06402   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
06403   * @param  ADCx ADC instance
06404   * @retval None
06405   */
06406 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
06407 {
06408   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
06409 }
06410
06411 /**
06412   * @brief  Clear flag ADC group regular end of unitary conversion.
06413   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
06414   * @param  ADCx ADC instance
06415   * @retval None
06416   */
06417 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
06418 {
06419   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
06420 }
06421
06422 /**
06423   * @brief  Clear flag ADC group regular end of sequence conversions.
06424   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
06425   * @param  ADCx ADC instance
06426   * @retval None
06427   */
06428 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
06429 {
06430   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
06431 }
06432
06433 /**
06434   * @brief  Clear flag ADC group regular overrun.
06435   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
06436   * @param  ADCx ADC instance
06437   * @retval None
06438   */
06439 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
06440 {
06441   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
06442 }
06443
06444 /**
06445   * @brief  Clear flag ADC group regular end of sampling phase.
06446   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
06447   * @param  ADCx ADC instance
06448   * @retval None
06449   */
06450 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
06451 {
06452   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
06453 }
06454
06455 /**
06456   * @brief  Clear flag ADC group injected end of unitary conversion.
06457   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
06458   * @param  ADCx ADC instance
06459   * @retval None
06460   */
06461 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
06462 {
06463   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
06464 }
06465
06466 /**
06467   * @brief  Clear flag ADC group injected end of sequence conversions.
06468   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
06469   * @param  ADCx ADC instance
06470   * @retval None
06471   */
06472 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
06473 {
06474   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
06475 }
06476
06477 /**
06478   * @brief  Clear flag ADC group injected contexts queue overflow.
06479   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
06480   * @param  ADCx ADC instance
06481   * @retval None
06482   */
06483 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
06484 {
06485   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
06486 }
06487
06488 /**
06489   * @brief  Clear flag ADC analog watchdog 1.
06490   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
06491   * @param  ADCx ADC instance
06492   * @retval None
06493   */
06494 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
06495 {
06496   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
06497 }
06498
06499 /**
06500   * @brief  Clear flag ADC analog watchdog 2.
06501   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
06502   * @param  ADCx ADC instance
06503   * @retval None
06504   */
06505 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
06506 {
06507   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
06508 }
06509
06510 /**
06511   * @brief  Clear flag ADC analog watchdog 3.
06512   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
06513   * @param  ADCx ADC instance
06514   * @retval None
06515   */
06516 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
06517 {
06518   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
06519 }
06520
06521 /**
06522   * @brief  Get flag multimode ADC ready of the ADC master.
06523   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
06524   * @param  ADCxy_COMMON ADC common instance
06525   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06526   * @retval State of bit (1 or 0).
06527   */
06528 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06529 {
06530   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
06531 }
06532
06533 /**
06534   * @brief  Get flag multimode ADC ready of the ADC slave.
06535   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
06536   * @param  ADCxy_COMMON ADC common instance
06537   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06538   * @retval State of bit (1 or 0).
06539   */
06540 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06541 {
06542   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
06543 }
06544
06545 /**
06546   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
06547   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
06548   * @param  ADCxy_COMMON ADC common instance
06549   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06550   * @retval State of bit (1 or 0).
06551   */
06552 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06553 {
06554   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
06555 }
06556
06557 /**
06558   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
06559   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
06560   * @param  ADCxy_COMMON ADC common instance
06561   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06562   * @retval State of bit (1 or 0).
06563   */
06564 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06565 {
06566   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
06567 }
06568
06569 /**
06570   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
06571   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
06572   * @param  ADCxy_COMMON ADC common instance
06573   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06574   * @retval State of bit (1 or 0).
06575   */
06576 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06577 {
06578   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
06579 }
06580
06581 /**
06582   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
06583   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
06584   * @param  ADCxy_COMMON ADC common instance
06585   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06586   * @retval State of bit (1 or 0).
06587   */
06588 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06589 {
06590   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
06591 }
06592
06593 /**
06594   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
06595   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
06596   * @param  ADCxy_COMMON ADC common instance
06597   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06598   * @retval State of bit (1 or 0).
06599   */
06600 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06601 {
06602   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
06603 }
06604
06605 /**
06606   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
06607   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
06608   * @param  ADCxy_COMMON ADC common instance
06609   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06610   * @retval State of bit (1 or 0).
06611   */
06612 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06613 {
06614   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
06615 }
06616
06617 /**
06618   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
06619   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
06620   * @param  ADCxy_COMMON ADC common instance
06621   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06622   * @retval State of bit (1 or 0).
06623   */
06624 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06625 {
06626   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
06627 }
06628
06629 /**
06630   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
06631   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
06632   * @param  ADCxy_COMMON ADC common instance
06633   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06634   * @retval State of bit (1 or 0).
06635   */
06636 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06637 {
06638   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
06639 }
06640
06641 /**
06642   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
06643   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
06644   * @param  ADCxy_COMMON ADC common instance
06645   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06646   * @retval State of bit (1 or 0).
06647   */
06648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06649 {
06650   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
06651 }
06652
06653 /**
06654   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
06655   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
06656   * @param  ADCxy_COMMON ADC common instance
06657   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06658   * @retval State of bit (1 or 0).
06659   */
06660 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06661 {
06662   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
06663 }
06664
06665 /**
06666   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
06667   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
06668   * @param  ADCxy_COMMON ADC common instance
06669   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06670   * @retval State of bit (1 or 0).
06671   */
06672 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06673 {
06674   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
06675 }
06676
06677 /**
06678   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
06679   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
06680   * @param  ADCxy_COMMON ADC common instance
06681   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06682   * @retval State of bit (1 or 0).
06683   */
06684 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06685 {
06686   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
06687 }
06688
06689 /**
06690   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
06691   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
06692   * @param  ADCxy_COMMON ADC common instance
06693   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06694   * @retval State of bit (1 or 0).
06695   */
06696 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06697 {
06698   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
06699 }
06700
06701 /**
06702   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
06703   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
06704   * @param  ADCxy_COMMON ADC common instance
06705   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06706   * @retval State of bit (1 or 0).
06707   */
06708 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06709 {
06710   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
06711 }
06712
06713 /**
06714   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
06715   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
06716   * @param  ADCxy_COMMON ADC common instance
06717   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06718   * @retval State of bit (1 or 0).
06719   */
06720 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06721 {
06722   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
06723 }
06724
06725 /**
06726   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
06727   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
06728   * @param  ADCxy_COMMON ADC common instance
06729   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06730   * @retval State of bit (1 or 0).
06731   */
06732 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06733 {
06734   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
06735 }
06736
06737 /**
06738   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
06739   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
06740   * @param  ADCxy_COMMON ADC common instance
06741   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06742   * @retval State of bit (1 or 0).
06743   */
06744 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06745 {
06746   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
06747 }
06748
06749 /**
06750   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
06751   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
06752   * @param  ADCxy_COMMON ADC common instance
06753   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06754   * @retval State of bit (1 or 0).
06755   */
06756 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06757 {
06758   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
06759 }
06760
06761 /**
06762   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
06763   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
06764   * @param  ADCxy_COMMON ADC common instance
06765   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06766   * @retval State of bit (1 or 0).
06767   */
06768 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06769 {
06770   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
06771 }
06772
06773 /**
06774   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
06775   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
06776   * @param  ADCxy_COMMON ADC common instance
06777   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06778   * @retval State of bit (1 or 0).
06779   */
06780 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06781 {
06782   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
06783 }
06784
06785 /**
06786   * @}
06787   */
06788
06789 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
06790   * @{
06791   */
06792
06793 /**
06794   * @brief  Enable ADC ready.
06795   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
06796   * @param  ADCx ADC instance
06797   * @retval None
06798   */
06799 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
06800 {
06801   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06802 }
06803
06804 /**
06805   * @brief  Enable interruption ADC group regular end of unitary conversion.
06806   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
06807   * @param  ADCx ADC instance
06808   * @retval None
06809   */
06810 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
06811 {
06812   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
06813 }
06814
06815 /**
06816   * @brief  Enable interruption ADC group regular end of sequence conversions.
06817   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
06818   * @param  ADCx ADC instance
06819   * @retval None
06820   */
06821 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
06822 {
06823   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
06824 }
06825
06826 /**
06827   * @brief  Enable ADC group regular interruption overrun.
06828   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
06829   * @param  ADCx ADC instance
06830   * @retval None
06831   */
06832 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
06833 {
06834   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
06835 }
06836
06837 /**
06838   * @brief  Enable interruption ADC group regular end of sampling.
06839   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
06840   * @param  ADCx ADC instance
06841   * @retval None
06842   */
06843 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
06844 {
06845   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
06846 }
06847
06848 /**
06849   * @brief  Enable interruption ADC group injected end of unitary conversion.
06850   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
06851   * @param  ADCx ADC instance
06852   * @retval None
06853   */
06854 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
06855 {
06856   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
06857 }
06858
06859 /**
06860   * @brief  Enable interruption ADC group injected end of sequence conversions.
06861   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
06862   * @param  ADCx ADC instance
06863   * @retval None
06864   */
06865 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
06866 {
06867   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
06868 }
06869
06870 /**
06871   * @brief  Enable interruption ADC group injected context queue overflow.
06872   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
06873   * @param  ADCx ADC instance
06874   * @retval None
06875   */
06876 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
06877 {
06878   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
06879 }
06880
06881 /**
06882   * @brief  Enable interruption ADC analog watchdog 1.
06883   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
06884   * @param  ADCx ADC instance
06885   * @retval None
06886   */
06887 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
06888 {
06889   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
06890 }
06891
06892 /**
06893   * @brief  Enable interruption ADC analog watchdog 2.
06894   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
06895   * @param  ADCx ADC instance
06896   * @retval None
06897   */
06898 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
06899 {
06900   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
06901 }
06902
06903 /**
06904   * @brief  Enable interruption ADC analog watchdog 3.
06905   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
06906   * @param  ADCx ADC instance
06907   * @retval None
06908   */
06909 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
06910 {
06911   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
06912 }
06913
06914 /**
06915   * @brief  Disable interruption ADC ready.
06916   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
06917   * @param  ADCx ADC instance
06918   * @retval None
06919   */
06920 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
06921 {
06922   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06923 }
06924
06925 /**
06926   * @brief  Disable interruption ADC group regular end of unitary conversion.
06927   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
06928   * @param  ADCx ADC instance
06929   * @retval None
06930   */
06931 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
06932 {
06933   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
06934 }
06935
06936 /**
06937   * @brief  Disable interruption ADC group regular end of sequence conversions.
06938   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
06939   * @param  ADCx ADC instance
06940   * @retval None
06941   */
06942 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
06943 {
06944   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
06945 }
06946
06947 /**
06948   * @brief  Disable interruption ADC group regular overrun.
06949   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
06950   * @param  ADCx ADC instance
06951   * @retval None
06952   */
06953 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
06954 {
06955   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
06956 }
06957
06958 /**
06959   * @brief  Disable interruption ADC group regular end of sampling.
06960   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
06961   * @param  ADCx ADC instance
06962   * @retval None
06963   */
06964 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
06965 {
06966   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
06967 }
06968
06969 /**
06970   * @brief  Disable interruption ADC group regular end of unitary conversion.
06971   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
06972   * @param  ADCx ADC instance
06973   * @retval None
06974   */
06975 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
06976 {
06977   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
06978 }
06979
06980 /**
06981   * @brief  Disable interruption ADC group injected end of sequence conversions.
06982   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
06983   * @param  ADCx ADC instance
06984   * @retval None
06985   */
06986 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
06987 {
06988   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
06989 }
06990
06991 /**
06992   * @brief  Disable interruption ADC group injected context queue overflow.
06993   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
06994   * @param  ADCx ADC instance
06995   * @retval None
06996   */
06997 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
06998 {
06999   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
07000 }
07001
07002 /**
07003   * @brief  Disable interruption ADC analog watchdog 1.
07004   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
07005   * @param  ADCx ADC instance
07006   * @retval None
07007   */
07008 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
07009 {
07010   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
07011 }
07012
07013 /**
07014   * @brief  Disable interruption ADC analog watchdog 2.
07015   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
07016   * @param  ADCx ADC instance
07017   * @retval None
07018   */
07019 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
07020 {
07021   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
07022 }
07023
07024 /**
07025   * @brief  Disable interruption ADC analog watchdog 3.
07026   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
07027   * @param  ADCx ADC instance
07028   * @retval None
07029   */
07030 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
07031 {
07032   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
07033 }
07034
07035 /**
07036   * @brief  Get state of interruption ADC ready
07037   *         (0: interrupt disabled, 1: interrupt enabled).
07038   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
07039   * @param  ADCx ADC instance
07040   * @retval State of bit (1 or 0).
07041   */
07042 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
07043 {
07044   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
07045 }
07046
07047 /**
07048   * @brief  Get state of interruption ADC group regular end of unitary conversion
07049   *         (0: interrupt disabled, 1: interrupt enabled).
07050   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
07051   * @param  ADCx ADC instance
07052   * @retval State of bit (1 or 0).
07053   */
07054 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
07055 {
07056   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
07057 }
07058
07059 /**
07060   * @brief  Get state of interruption ADC group regular end of sequence conversions
07061   *         (0: interrupt disabled, 1: interrupt enabled).
07062   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
07063   * @param  ADCx ADC instance
07064   * @retval State of bit (1 or 0).
07065   */
07066 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
07067 {
07068   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
07069 }
07070
07071 /**
07072   * @brief  Get state of interruption ADC group regular overrun
07073   *         (0: interrupt disabled, 1: interrupt enabled).
07074   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
07075   * @param  ADCx ADC instance
07076   * @retval State of bit (1 or 0).
07077   */
07078 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
07079 {
07080   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
07081 }
07082
07083 /**
07084   * @brief  Get state of interruption ADC group regular end of sampling
07085   *         (0: interrupt disabled, 1: interrupt enabled).
07086   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
07087   * @param  ADCx ADC instance
07088   * @retval State of bit (1 or 0).
07089   */
07090 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
07091 {
07092   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
07093 }
07094
07095 /**
07096   * @brief  Get state of interruption ADC group injected end of unitary conversion
07097   *         (0: interrupt disabled, 1: interrupt enabled).
07098   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
07099   * @param  ADCx ADC instance
07100   * @retval State of bit (1 or 0).
07101   */
07102 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
07103 {
07104   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
07105 }
07106
07107 /**
07108   * @brief  Get state of interruption ADC group injected end of sequence conversions
07109   *         (0: interrupt disabled, 1: interrupt enabled).
07110   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
07111   * @param  ADCx ADC instance
07112   * @retval State of bit (1 or 0).
07113   */
07114 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
07115 {
07116   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
07117 }
07118
07119 /**
07120   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
07121   *         (0: interrupt disabled, 1: interrupt enabled).
07122   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
07123   * @param  ADCx ADC instance
07124   * @retval State of bit (1 or 0).
07125   */
07126 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
07127 {
07128   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
07129 }
07130
07131 /**
07132   * @brief  Get state of interruption ADC analog watchdog 1
07133   *         (0: interrupt disabled, 1: interrupt enabled).
07134   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
07135   * @param  ADCx ADC instance
07136   * @retval State of bit (1 or 0).
07137   */
07138 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
07139 {
07140   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
07141 }
07142
07143 /**
07144   * @brief  Get state of interruption Get ADC analog watchdog 2
07145   *         (0: interrupt disabled, 1: interrupt enabled).
07146   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
07147   * @param  ADCx ADC instance
07148   * @retval State of bit (1 or 0).
07149   */
07150 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
07151 {
07152   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
07153 }
07154
07155 /**
07156   * @brief  Get state of interruption Get ADC analog watchdog 3
07157   *         (0: interrupt disabled, 1: interrupt enabled).
07158   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
07159   * @param  ADCx ADC instance
07160   * @retval State of bit (1 or 0).
07161   */
07162 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
07163 {
07164   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
07165 }
07166
07167 /**
07168   * @}
07169   */
07170
07171 #if defined(USE_FULL_LL_DRIVER)
07172 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
07173   * @{
07174   */
07175
07176 /* Initialization of some features of ADC common parameters and multimode */
07177 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
07178 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07179 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07180
07181 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
07182 /* (availability of ADC group injected depends on STM32 families) */
07183 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
07184
07185 /* Initialization of some features of ADC instance */
07186 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
07187 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
07188
07189 /* Initialization of some features of ADC instance and ADC group regular */
07190 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07191 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07192
07193 /* Initialization of some features of ADC instance and ADC group injected */
07194 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07195 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07196
07197 /**
07198   * @}
07199   */
07200 #endif /* USE_FULL_LL_DRIVER */
07201
07202 /**
07203   * @}
07204   */
07205
07206 /**
07207   * @}
07208   */
07209
07210 #endif /* ADC1 || ADC2 || ADC3 */
07211
07212 /**
07213   * @}
07214   */
07215
07216 #ifdef __cplusplus
07217 }
07218 #endif
07219
07220 #endif /* STM32H7xx_LL_ADC_H */
07221
07222 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bdma.c Source File

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stm32h7xx_ll_bdma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_bdma.c
00004   * @author  MCD Application Team
00005   * @brief   BDMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 #if defined(USE_FULL_LL_DRIVER)
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32h7xx_ll_bdma.h"
00024 #include "stm32h7xx_ll_bus.h"
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
00036
00037 /** @addtogroup BDMA_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup BDMA_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_BDMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
00049                                                   ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
00050                                                   ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
00051
00052 #define IS_LL_BDMA_MODE(__VALUE__)               (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
00053                                                   ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
00054
00055 #define IS_LL_BDMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
00056                                                   ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
00057
00058 #define IS_LL_BDMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
00059                                                   ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
00060
00061 #define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE)      || \
00062                                                   ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD)  || \
00063                                                   ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
00064
00065 #define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE)      || \
00066                                                   ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD)  || \
00067                                                   ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
00068
00069 #define IS_LL_BDMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00070
00071 #if defined(ADC3)
00072 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
00073 #else
00074 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2)
00075 #endif /* ADC3 */
00076
00077 #define IS_LL_BDMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_BDMA_PRIORITY_LOW)    || \
00078                                                   ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
00079                                                   ((__VALUE__) == LL_BDMA_PRIORITY_HIGH)   || \
00080                                                   ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
00081
00082 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == BDMA) && \
00083                                                              (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
00084                                                               ((CHANNEL) == LL_BDMA_CHANNEL_1) || \
00085                                                               ((CHANNEL) == LL_BDMA_CHANNEL_2) || \
00086                                                               ((CHANNEL) == LL_BDMA_CHANNEL_3) || \
00087                                                               ((CHANNEL) == LL_BDMA_CHANNEL_4) || \
00088                                                               ((CHANNEL) == LL_BDMA_CHANNEL_5) || \
00089                                                               ((CHANNEL) == LL_BDMA_CHANNEL_6) || \
00090                                                               ((CHANNEL) == LL_BDMA_CHANNEL_7))))
00091
00092 /**
00093   * @}
00094   */
00095
00096 /* Private function prototypes -----------------------------------------------*/
00097
00098 /* Exported functions --------------------------------------------------------*/
00099 /** @addtogroup BDMA_LL_Exported_Functions
00100   * @{
00101   */
00102
00103 /** @addtogroup BDMA_LL_EF_Init
00104   * @{
00105   */
00106
00107 /**
00108   * @brief  De-initialize the DMA registers to their default reset values.
00109   * @param  BDMAx BDMAx Instance
00110   * @param  Channel This parameter can be one of the following values:
00111   *         @arg @ref LL_BDMA_CHANNEL_0
00112   *         @arg @ref LL_BDMA_CHANNEL_1
00113   *         @arg @ref LL_BDMA_CHANNEL_2
00114   *         @arg @ref LL_BDMA_CHANNEL_3
00115   *         @arg @ref LL_BDMA_CHANNEL_4
00116   *         @arg @ref LL_BDMA_CHANNEL_5
00117   *         @arg @ref LL_BDMA_CHANNEL_6
00118   *         @arg @ref LL_BDMA_CHANNEL_7
00119   *         @arg @ref LL_BDMA_CHANNEL_ALL
00120   * @retval An ErrorStatus enumeration value:
00121   *          - SUCCESS: DMA registers are de-initialized
00122   *          - ERROR: DMA registers are not de-initialized
00123   */
00124 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel)
00125 {
00126   BDMA_Channel_TypeDef *tmp ;
00127   ErrorStatus status = SUCCESS;
00128
00129   /* Check the DMA Instance DMAx and Channel parameters */
00130   assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL));
00131
00132   if (Channel == LL_BDMA_CHANNEL_ALL)
00133   {
00134     if (BDMAx == BDMA)
00135     {
00136       /* Force reset of BDMA clock */
00137       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00138
00139       /* Release reset of BDMA clock */
00140       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00141     }
00142     else
00143     {
00144       status = ERROR;
00145     }
00146   }
00147   else
00148   {
00149     tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel));
00150
00151     /* Disable the selected DMAx_Channely */
00152     CLEAR_BIT(tmp->CCR, BDMA_CCR_EN);
00153
00154     /* Reset DMAx_Channely control register */
00155     LL_BDMA_WriteReg(tmp, CCR, 0U);
00156
00157     /* Reset DMAx_Channely remaining bytes register */
00158     LL_BDMA_WriteReg(tmp, CNDTR, 0U);
00159
00160     /* Reset DMAx_Channely peripheral address register */
00161     LL_BDMA_WriteReg(tmp, CPAR, 0U);
00162
00163     /* Reset DMAx_Channely memory 0 address register */
00164     LL_BDMA_WriteReg(tmp, CM0AR, 0U);
00165
00166     /* Reset DMAx_Channely memory 1 address register */
00167     LL_BDMA_WriteReg(tmp, CM1AR, 0U);
00168
00169     /* Reset Request register field for BDMAx Channel */
00170     LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM);
00171
00172     if (Channel == LL_BDMA_CHANNEL_0)
00173     {
00174       /* Reset interrupt pending bits for DMAx Channel0 */
00175       LL_BDMA_ClearFlag_GI0(BDMAx);
00176     }
00177     else if (Channel == LL_BDMA_CHANNEL_1)
00178     {
00179       /* Reset interrupt pending bits for DMAx Channel1 */
00180       LL_BDMA_ClearFlag_GI1(BDMAx);
00181     }
00182     else if (Channel == LL_BDMA_CHANNEL_2)
00183     {
00184       /* Reset interrupt pending bits for DMAx Channel2 */
00185       LL_BDMA_ClearFlag_GI2(BDMAx);
00186     }
00187     else if (Channel == LL_BDMA_CHANNEL_3)
00188     {
00189       /* Reset interrupt pending bits for DMAx Channel3 */
00190       LL_BDMA_ClearFlag_GI3(BDMAx);
00191     }
00192     else if (Channel == LL_BDMA_CHANNEL_4)
00193     {
00194       /* Reset interrupt pending bits for DMAx Channel4 */
00195       LL_BDMA_ClearFlag_GI4(BDMAx);
00196     }
00197     else if (Channel == LL_BDMA_CHANNEL_5)
00198     {
00199       /* Reset interrupt pending bits for DMAx Channel5 */
00200       LL_BDMA_ClearFlag_GI5(BDMAx);
00201     }
00202
00203     else if (Channel == LL_BDMA_CHANNEL_6)
00204     {
00205       /* Reset interrupt pending bits for DMAx Channel6 */
00206       LL_BDMA_ClearFlag_GI6(BDMAx);
00207     }
00208     else if (Channel == LL_BDMA_CHANNEL_7)
00209     {
00210       /* Reset interrupt pending bits for DMAx Channel7 */
00211       LL_BDMA_ClearFlag_GI7(BDMAx);
00212     }
00213     else
00214     {
00215       status = ERROR;
00216     }
00217   }
00218
00219   return (uint32_t)status;
00220 }
00221
00222 /**
00223   * @brief  Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
00224   * @note   To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros :
00225   *         @arg @ref __LL_BDMA_GET_INSTANCE
00226   *         @arg @ref __LL_BDMA_GET_CHANNEL
00227   * @param  BDMAx BDMAx Instance
00228   * @param  Channel This parameter can be one of the following values:
00229   *         @arg @ref LL_BDMA_CHANNEL_0
00230   *         @arg @ref LL_BDMA_CHANNEL_1
00231   *         @arg @ref LL_BDMA_CHANNEL_2
00232   *         @arg @ref LL_BDMA_CHANNEL_3
00233   *         @arg @ref LL_BDMA_CHANNEL_4
00234   *         @arg @ref LL_BDMA_CHANNEL_5
00235   *         @arg @ref LL_BDMA_CHANNEL_6
00236   *         @arg @ref LL_BDMA_CHANNEL_7
00237   * @param  BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure.
00238   * @retval An ErrorStatus enumeration value:
00239   *          - SUCCESS: DMA registers are initialized
00240   *          - ERROR: Not applicable
00241   */
00242 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
00243 {
00244   /* Check the DMA Instance DMAx and Channel parameters */
00245   assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel));
00246
00247   /* Check the DMA parameters from BDMA_InitStruct */
00248   assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction));
00249   assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode));
00250   assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode));
00251   assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode));
00252   assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize));
00253   assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize));
00254   assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
00255   assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
00256   assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
00257
00258   /*---------------------------- DMAx CCR Configuration ------------------------
00259    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00260    *                          peripheral and memory increment mode,
00261    *                          data size alignment and  priority level with parameters :
00262    * - Direction:      BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
00263    * - Mode:           BDMA_CCR_CIRC bit
00264    * - PeriphOrM2MSrcIncMode:  BDMA_CCR_PINC bit
00265    * - MemoryOrM2MDstIncMode:  BDMA_CCR_MINC bit
00266    * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
00267    * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
00268    * - Priority:               BDMA_CCR_PL[1:0] bits
00269    */
00270   LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction              | \
00271                          BDMA_InitStruct->Mode                   | \
00272                          BDMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00273                          BDMA_InitStruct->MemoryOrM2MDstIncMode  | \
00274                          BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
00275                          BDMA_InitStruct->MemoryOrM2MDstDataSize | \
00276                          BDMA_InitStruct->Priority);
00277
00278   /*-------------------------- DMAx CMAR Configuration -------------------------
00279    * Configure the memory or destination base address with parameter :
00280    * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits
00281    */
00282   LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress);
00283
00284   /*-------------------------- DMAx CPAR Configuration -------------------------
00285    * Configure the peripheral or source base address with parameter :
00286    * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits
00287    */
00288   LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress);
00289
00290   /*--------------------------- DMAx CNDTR Configuration -----------------------
00291    * Configure the peripheral base address with parameter :
00292    * - NbData: BDMA_CNDTR_NDT[15:0] bits
00293    */
00294   LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData);
00295
00296   /*--------------------------- DMAMUXx CCR Configuration ----------------------
00297    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
00298    * - PeriphRequest: BDMA_CxCR[7:0] bits
00299    */
00300   LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest);
00301
00302   return (uint32_t)SUCCESS;
00303 }
00304
00305 /**
00306   * @brief  Set each @ref LL_BDMA_InitTypeDef field to default value.
00307   * @param  BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure.
00308   * @retval None
00309   */
00310 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
00311 {
00312   /* Set BDMA_InitStruct fields to default values */
00313   BDMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00314   BDMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00315   BDMA_InitStruct->Direction              = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
00316   BDMA_InitStruct->Mode                   = LL_BDMA_MODE_NORMAL;
00317   BDMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_BDMA_PERIPH_NOINCREMENT;
00318   BDMA_InitStruct->MemoryOrM2MDstIncMode  = LL_BDMA_MEMORY_NOINCREMENT;
00319   BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
00320   BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
00321   BDMA_InitStruct->NbData                 = 0x00000000U;
00322   BDMA_InitStruct->PeriphRequest          = LL_DMAMUX2_REQ_MEM2MEM;
00323   BDMA_InitStruct->Priority               = LL_BDMA_PRIORITY_LOW;
00324 }
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #endif /* BDMA || BDMA1 || BDMA2 */
00339
00340 /**
00341   * @}
00342   */
00343
00344 #endif /* USE_FULL_LL_DRIVER */
00345
00346 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bdma.h Source File

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stm32h7xx_ll_bdma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_bdma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of BDMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_BDMA_H
00022 #define STM32H7xx_LL_BDMA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030 #include "stm32h7xx_ll_dmamux.h"
00031
00032 /** @addtogroup STM32H7xx_LL_Driver
00033   * @{
00034   */
00035
00036 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
00037
00038 /** @defgroup BDMA_LL BDMA
00039   * @{
00040   */
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables
00045   * @{
00046   */
00047 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
00048 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
00049 {
00050   (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
00051   (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
00052   (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
00053   (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
00054   (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
00055   (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
00056   (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
00057   (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
00058 };
00059 /**
00060   * @}
00061   */
00062
00063 /* Private constants ---------------------------------------------------------*/
00064 /* Private macros ------------------------------------------------------------*/
00065 #if !defined(UNUSED)
00066 #define UNUSED(x) ((void)(x))
00067 #endif
00068
00069 /* Exported types ------------------------------------------------------------*/
00070 #if defined(USE_FULL_LL_DRIVER)
00071 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure
00072   * @{
00073   */
00074 typedef struct
00075 {
00076   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for BDMA transfer
00077                                         or as Source base address in case of memory to memory transfer direction.
00078
00079                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00080
00081   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00082                                         or as Destination base address in case of memory to memory transfer direction.
00083
00084                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00085
00086   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00087                                         from memory to memory or from peripheral to memory.
00088                                         This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
00089
00090                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
00091
00092   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00093                                         This parameter can be a value of @ref BDMA_LL_EC_MODE
00094                                         @note: The circular buffer mode cannot be used if the memory to memory
00095                                                data transfer direction is configured on the selected Channel
00096
00097                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
00098
00099   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00100                                         is incremented or not.
00101                                         This parameter can be a value of @ref BDMA_LL_EC_PERIPH
00102
00103                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
00104
00105   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00106                                         is incremented or not.
00107                                         This parameter can be a value of @ref BDMA_LL_EC_MEMORY
00108
00109                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
00110
00111   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00112                                         in case of memory to memory transfer direction.
00113                                         This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
00114
00115                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
00116
00117   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00118                                         in case of memory to memory transfer direction.
00119                                         This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
00120
00121                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
00122
00123   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00124                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00125                                         or MemorySize parameters depending in the transfer direction.
00126                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00127
00128                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
00129
00130   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00131                                         This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
00132
00133                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
00134
00135   uint32_t Priority;               /*!< Specifies the channel priority level.
00136                                         This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
00137
00138                                         This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
00139
00140 } LL_BDMA_InitTypeDef;
00141 /**
00142   * @}
00143   */
00144 #endif /* USE_FULL_LL_DRIVER */
00145
00146 /* Exported constants --------------------------------------------------------*/
00147 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants
00148   * @{
00149   */
00150 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00151   * @brief    Flags defines which can be used with LL_BDMA_WriteReg function
00152   * @{
00153   */
00154 #define LL_BDMA_IFCR_CGIF1                 BDMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00155 #define LL_BDMA_IFCR_CTCIF1                BDMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00156 #define LL_BDMA_IFCR_CHTIF1                BDMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00157 #define LL_BDMA_IFCR_CTEIF1                BDMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00158 #define LL_BDMA_IFCR_CGIF2                 BDMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00159 #define LL_BDMA_IFCR_CTCIF2                BDMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00160 #define LL_BDMA_IFCR_CHTIF2                BDMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00161 #define LL_BDMA_IFCR_CTEIF2                BDMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00162 #define LL_BDMA_IFCR_CGIF3                 BDMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00163 #define LL_BDMA_IFCR_CTCIF3                BDMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00164 #define LL_BDMA_IFCR_CHTIF3                BDMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00165 #define LL_BDMA_IFCR_CTEIF3                BDMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00166 #define LL_BDMA_IFCR_CGIF4                 BDMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00167 #define LL_BDMA_IFCR_CTCIF4                BDMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00168 #define LL_BDMA_IFCR_CHTIF4                BDMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00169 #define LL_BDMA_IFCR_CTEIF4                BDMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00170 #define LL_BDMA_IFCR_CGIF5                 BDMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00171 #define LL_BDMA_IFCR_CTCIF5                BDMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00172 #define LL_BDMA_IFCR_CHTIF5                BDMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00173 #define LL_BDMA_IFCR_CTEIF5                BDMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00174 #define LL_BDMA_IFCR_CGIF6                 BDMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00175 #define LL_BDMA_IFCR_CTCIF6                BDMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00176 #define LL_BDMA_IFCR_CHTIF6                BDMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00177 #define LL_BDMA_IFCR_CTEIF6                BDMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00178 #define LL_BDMA_IFCR_CGIF7                 BDMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00179 #define LL_BDMA_IFCR_CTCIF7                BDMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00180 #define LL_BDMA_IFCR_CHTIF7                BDMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00181 #define LL_BDMA_IFCR_CTEIF7                BDMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines
00187   * @brief    Flags defines which can be used with LL_BDMA_ReadReg function
00188   * @{
00189   */
00190 #define LL_BDMA_ISR_GIF0                   BDMA_ISR_GIF0          /*!< Channel 1 global flag            */
00191 #define LL_BDMA_ISR_TCIF0                  BDMA_ISR_TCIF0         /*!< Channel 1 transfer complete flag */
00192 #define LL_BDMA_ISR_HTIF0                  BDMA_ISR_HTIF0         /*!< Channel 1 half transfer flag     */
00193 #define LL_BDMA_ISR_TEIF0                  BDMA_ISR_TEIF0         /*!< Channel 1 transfer error flag    */
00194 #define LL_BDMA_ISR_GIF1                   BDMA_ISR_GIF1          /*!< Channel 1 global flag            */
00195 #define LL_BDMA_ISR_TCIF1                  BDMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00196 #define LL_BDMA_ISR_HTIF1                  BDMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00197 #define LL_BDMA_ISR_TEIF1                  BDMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00198 #define LL_BDMA_ISR_GIF2                   BDMA_ISR_GIF2          /*!< Channel 2 global flag            */
00199 #define LL_BDMA_ISR_TCIF2                  BDMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00200 #define LL_BDMA_ISR_HTIF2                  BDMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00201 #define LL_BDMA_ISR_TEIF2                  BDMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00202 #define LL_BDMA_ISR_GIF3                   BDMA_ISR_GIF3          /*!< Channel 3 global flag            */
00203 #define LL_BDMA_ISR_TCIF3                  BDMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00204 #define LL_BDMA_ISR_HTIF3                  BDMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00205 #define LL_BDMA_ISR_TEIF3                  BDMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00206 #define LL_BDMA_ISR_GIF4                   BDMA_ISR_GIF4          /*!< Channel 4 global flag            */
00207 #define LL_BDMA_ISR_TCIF4                  BDMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00208 #define LL_BDMA_ISR_HTIF4                  BDMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00209 #define LL_BDMA_ISR_TEIF4                  BDMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00210 #define LL_BDMA_ISR_GIF5                   BDMA_ISR_GIF5          /*!< Channel 5 global flag            */
00211 #define LL_BDMA_ISR_TCIF5                  BDMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00212 #define LL_BDMA_ISR_HTIF5                  BDMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00213 #define LL_BDMA_ISR_TEIF5                  BDMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00214 #define LL_BDMA_ISR_GIF6                   BDMA_ISR_GIF6          /*!< Channel 6 global flag            */
00215 #define LL_BDMA_ISR_TCIF6                  BDMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00216 #define LL_BDMA_ISR_HTIF6                  BDMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00217 #define LL_BDMA_ISR_TEIF6                  BDMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00218 #define LL_BDMA_ISR_GIF7                   BDMA_ISR_GIF7          /*!< Channel 7 global flag            */
00219 #define LL_BDMA_ISR_TCIF7                  BDMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00220 #define LL_BDMA_ISR_HTIF7                  BDMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00221 #define LL_BDMA_ISR_TEIF7                  BDMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup BDMA_LL_EC_IT IT Defines
00227   * @brief    IT defines which can be used with LL_BDMA_ReadReg and  LL_BDMA_WriteReg functions
00228   * @{
00229   */
00230 #define LL_BDMA_CCR_TCIE                   BDMA_CCR_TCIE          /*!< Transfer complete interrupt */
00231 #define LL_BDMA_CCR_HTIE                   BDMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00232 #define LL_BDMA_CCR_TEIE                   BDMA_CCR_TEIE          /*!< Transfer error interrupt    */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL
00238   * @{
00239   */
00240 #define LL_BDMA_CHANNEL_0                  0x00000000U /*!< DMA Channel 0  */
00241 #define LL_BDMA_CHANNEL_1                  0x00000001U /*!< BDMA Channel 1 */
00242 #define LL_BDMA_CHANNEL_2                  0x00000002U /*!< BDMA Channel 2 */
00243 #define LL_BDMA_CHANNEL_3                  0x00000003U /*!< BDMA Channel 3 */
00244 #define LL_BDMA_CHANNEL_4                  0x00000004U /*!< BDMA Channel 4 */
00245 #define LL_BDMA_CHANNEL_5                  0x00000005U /*!< BDMA Channel 5 */
00246 #define LL_BDMA_CHANNEL_6                  0x00000006U /*!< BDMA Channel 6 */
00247 #define LL_BDMA_CHANNEL_7                  0x00000007U /*!< BDMA Channel 7 */
00248 #if defined(USE_FULL_LL_DRIVER)
00249 #define LL_BDMA_CHANNEL_ALL                0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */
00250 #endif /*USE_FULL_LL_DRIVER*/
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction
00256   * @{
00257   */
00258 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U              /*!< Peripheral to memory direction       */
00259 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR             /*!< Memory to peripheral direction       */
00260 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM         /*!< Memory to memory direction           */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup BDMA_LL_EC_MODE Transfer mode
00266   * @{
00267   */
00268 #define LL_BDMA_MODE_NORMAL                0x00000000U              /*!< Normal Mode                          */
00269 #define LL_BDMA_MODE_CIRCULAR              BDMA_CCR_CIRC            /*!< Circular Mode                        */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
00275   * @{
00276   */
00277 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U              /*!< Disable double buffering mode        */
00278 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE   BDMA_CCR_DBM             /*!< Enable double buffering mode         */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
00284   * @{
00285   */
00286 #define LL_BDMA_PERIPH_INCREMENT           BDMA_CCR_PINC            /*!< Peripheral increment mode Enable     */
00287 #define LL_BDMA_PERIPH_NOINCREMENT         0x00000000U              /*!< Peripheral increment mode Disable    */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode
00293   * @{
00294   */
00295 #define LL_BDMA_MEMORY_INCREMENT           BDMA_CCR_MINC            /*!< Memory increment mode Enable         */
00296 #define LL_BDMA_MEMORY_NOINCREMENT         0x00000000U              /*!< Memory increment mode Disable        */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment
00302   * @{
00303   */
00304 #define LL_BDMA_PDATAALIGN_BYTE            0x00000000U              /*!< Peripheral data alignment : Byte     */
00305 #define LL_BDMA_PDATAALIGN_HALFWORD        BDMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00306 #define LL_BDMA_PDATAALIGN_WORD            BDMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment
00312   * @{
00313   */
00314 #define LL_BDMA_MDATAALIGN_BYTE            0x00000000U              /*!< Memory data alignment : Byte         */
00315 #define LL_BDMA_MDATAALIGN_HALFWORD        BDMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord     */
00316 #define LL_BDMA_MDATAALIGN_WORD            BDMA_CCR_MSIZE_1         /*!< Memory data alignment : Word         */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level
00322   * @{
00323   */
00324 #define LL_BDMA_PRIORITY_LOW               0x00000000U              /*!< Priority level : Low                 */
00325 #define LL_BDMA_PRIORITY_MEDIUM            BDMA_CCR_PL_0            /*!< Priority level : Medium              */
00326 #define LL_BDMA_PRIORITY_HIGH              BDMA_CCR_PL_1            /*!< Priority level : High                */
00327 #define LL_BDMA_PRIORITY_VERYHIGH          BDMA_CCR_PL              /*!< Priority level : Very_High           */
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
00333   * @{
00334   */
00335 #define LL_BDMA_CURRENTTARGETMEM0          0x00000000U              /*!< Set CurrentTarget Memory to Memory 0 */
00336 #define LL_BDMA_CURRENTTARGETMEM1          BDMA_CCR_CT              /*!< Set CurrentTarget Memory to Memory 1 */
00337 /**
00338   * @}
00339   */
00340
00341 /* Exported macro ------------------------------------------------------------*/
00342 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros
00343   * @{
00344   */
00345
00346 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros
00347   * @{
00348   */
00349 /**
00350   * @brief  Write a value in BDMA register
00351   * @param  __INSTANCE__ BDMA Instance
00352   * @param  __REG__ Register to be written
00353   * @param  __VALUE__ Value to be written in the register
00354   * @retval None
00355   */
00356 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00357
00358 /**
00359   * @brief  Read a value in BDMA register
00360   * @param  __INSTANCE__ BDMA Instance
00361   * @param  __REG__ Register to be read
00362   * @retval Register value
00363   */
00364 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely
00370   * @{
00371   */
00372 /**
00373   * @brief  Convert BDMAx_Channely into BDMAx
00374   * @param  __CHANNEL_INSTANCE__ BDMAx_Channely
00375   * @retval BDMAx
00376   */
00377 #if defined (BDMA1)
00378 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
00379 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
00380 #else
00381 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (BDMA)
00382 #endif /* BDMA1 */
00383
00384 /**
00385   * @brief  Convert BDMAx_Channely into LL_BDMA_CHANNEL_y
00386   * @param  __CHANNEL_INSTANCE__ BDMAx_Channely
00387   * @retval LL_BDMA_CHANNEL_y
00388   */
00389 #if defined (BDMA1)
00390 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
00391 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0))  ? LL_BDMA_CHANNEL_0 : \
00392  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
00393  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1))  ? LL_BDMA_CHANNEL_1 : \
00394  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
00395  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2))  ? LL_BDMA_CHANNEL_2 : \
00396  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
00397  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3))  ? LL_BDMA_CHANNEL_3 : \
00398  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
00399  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4))  ? LL_BDMA_CHANNEL_4 : \
00400  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
00401  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5))  ? LL_BDMA_CHANNEL_5 : \
00402  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
00403  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6))  ? LL_BDMA_CHANNEL_6 : \
00404  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
00405  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7))  ? LL_BDMA_CHANNEL_7 : \
00406 LL_BDMA_CHANNEL_7)
00407 #else
00408 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
00409 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
00410  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
00411  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
00412  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
00413  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
00414  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
00415  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
00416  LL_BDMA_CHANNEL_7)
00417 #endif /* BDMA1 */
00418
00419 /**
00420   * @brief  Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely
00421   * @param  __BDMA_INSTANCE__ BDMAx
00422   * @param  __CHANNEL__ LL_BDMA_CHANNEL_y
00423   * @retval BDMAx_Channely
00424   */
00425 #if defined (BDMA1)
00426 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)   \
00427 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0  : \
00428  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
00429  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1  : \
00430  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
00431  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2  : \
00432  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
00433  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3  : \
00434  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
00435  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4  : \
00436  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
00437  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5  : \
00438  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
00439  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6  : \
00440  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
00441  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7  : \
00442  BDMA1_Channel7)
00443 #else
00444 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)   \
00445 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
00446  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
00447  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
00448  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
00449  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
00450  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
00451  (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
00452  BDMA_Channel7)
00453 #endif /* BDMA1 */
00454 /**
00455   * @}
00456   */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /* Exported functions --------------------------------------------------------*/
00463 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions
00464  * @{
00465  */
00466
00467 /** @defgroup BDMA_LL_EF_Configuration Configuration
00468   * @{
00469   */
00470 /**
00471   * @brief  Enable BDMA channel.
00472   * @rmtoll CCR          EN            LL_BDMA_EnableChannel
00473   * @param  BDMAx BDMA Instance
00474   * @param  Channel This parameter can be one of the following values:
00475   *         @arg @ref LL_BDMA_CHANNEL_0
00476   *         @arg @ref LL_BDMA_CHANNEL_1
00477   *         @arg @ref LL_BDMA_CHANNEL_2
00478   *         @arg @ref LL_BDMA_CHANNEL_3
00479   *         @arg @ref LL_BDMA_CHANNEL_4
00480   *         @arg @ref LL_BDMA_CHANNEL_5
00481   *         @arg @ref LL_BDMA_CHANNEL_6
00482   *         @arg @ref LL_BDMA_CHANNEL_7
00483   * @retval None
00484   */
00485 __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
00486 {
00487   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00488
00489   SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
00490 }
00491
00492 /**
00493   * @brief  Disable BDMA channel.
00494   * @rmtoll CCR          EN            LL_BDMA_DisableChannel
00495   * @param  BDMAx BDMA Instance
00496   * @param  Channel This parameter can be one of the following values:
00497   *         @arg @ref LL_BDMA_CHANNEL_0
00498   *         @arg @ref LL_BDMA_CHANNEL_1
00499   *         @arg @ref LL_BDMA_CHANNEL_2
00500   *         @arg @ref LL_BDMA_CHANNEL_3
00501   *         @arg @ref LL_BDMA_CHANNEL_4
00502   *         @arg @ref LL_BDMA_CHANNEL_5
00503   *         @arg @ref LL_BDMA_CHANNEL_6
00504   *         @arg @ref LL_BDMA_CHANNEL_7
00505   * @retval None
00506   */
00507 __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
00508 {
00509   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00510
00511   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
00512 }
00513
00514 /**
00515   * @brief  Check if BDMA channel is enabled or disabled.
00516   * @rmtoll CCR          EN            LL_BDMA_IsEnabledChannel
00517   * @param  BDMAx BDMA Instance
00518   * @param  Channel This parameter can be one of the following values:
00519   *         @arg @ref LL_BDMA_CHANNEL_0
00520   *         @arg @ref LL_BDMA_CHANNEL_1
00521   *         @arg @ref LL_BDMA_CHANNEL_2
00522   *         @arg @ref LL_BDMA_CHANNEL_3
00523   *         @arg @ref LL_BDMA_CHANNEL_4
00524   *         @arg @ref LL_BDMA_CHANNEL_5
00525   *         @arg @ref LL_BDMA_CHANNEL_6
00526   *         @arg @ref LL_BDMA_CHANNEL_7
00527   * @retval State of bit (1 or 0).
00528   */
00529 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
00530 {
00531   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00532
00533   return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
00534 }
00535
00536 /**
00537   * @brief  Configure all parameters link to BDMA transfer.
00538   * @rmtoll CCR          DIR           LL_BDMA_ConfigTransfer\n
00539   *         CCR          MEM2MEM       LL_BDMA_ConfigTransfer\n
00540   *         CCR          CIRC          LL_BDMA_ConfigTransfer\n
00541   *         CCR          PINC          LL_BDMA_ConfigTransfer\n
00542   *         CCR          MINC          LL_BDMA_ConfigTransfer\n
00543   *         CCR          PSIZE         LL_BDMA_ConfigTransfer\n
00544   *         CCR          MSIZE         LL_BDMA_ConfigTransfer\n
00545   *         CCR          PL            LL_BDMA_ConfigTransfer
00546   * @param  BDMAx BDMA Instance
00547   * @param  Channel This parameter can be one of the following values:
00548   *         @arg @ref LL_BDMA_CHANNEL_0
00549   *         @arg @ref LL_BDMA_CHANNEL_1
00550   *         @arg @ref LL_BDMA_CHANNEL_2
00551   *         @arg @ref LL_BDMA_CHANNEL_3
00552   *         @arg @ref LL_BDMA_CHANNEL_4
00553   *         @arg @ref LL_BDMA_CHANNEL_5
00554   *         @arg @ref LL_BDMA_CHANNEL_6
00555   *         @arg @ref LL_BDMA_CHANNEL_7
00556   * @param  Configuration This parameter must be a combination of all the following values:
00557   *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
00558   *         @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR
00559   *         @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT
00560   *         @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT
00561   *         @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
00562   *         @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
00563   *         @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
00564   * @retval None
00565   */
00566 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
00567 {
00568   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00569
00570   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00571              BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
00572              Configuration);
00573 }
00574
00575 /**
00576   * @brief  Set Data transfer direction (read from peripheral or from memory).
00577   * @rmtoll CCR          DIR           LL_BDMA_SetDataTransferDirection\n
00578   *         CCR          MEM2MEM       LL_BDMA_SetDataTransferDirection
00579   * @param  BDMAx BDMA Instance
00580   * @param  Channel This parameter can be one of the following values:
00581   *         @arg @ref LL_BDMA_CHANNEL_0
00582   *         @arg @ref LL_BDMA_CHANNEL_1
00583   *         @arg @ref LL_BDMA_CHANNEL_2
00584   *         @arg @ref LL_BDMA_CHANNEL_3
00585   *         @arg @ref LL_BDMA_CHANNEL_4
00586   *         @arg @ref LL_BDMA_CHANNEL_5
00587   *         @arg @ref LL_BDMA_CHANNEL_6
00588   *         @arg @ref LL_BDMA_CHANNEL_7
00589   * @param  Direction This parameter can be one of the following values:
00590   *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
00591   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
00592   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
00593   * @retval None
00594   */
00595 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
00596 {
00597   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00598
00599   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00600              BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
00601 }
00602
00603 /**
00604   * @brief  Get Data transfer direction (read from peripheral or from memory).
00605   * @rmtoll CCR          DIR           LL_BDMA_GetDataTransferDirection\n
00606   *         CCR          MEM2MEM       LL_BDMA_GetDataTransferDirection
00607   * @param  BDMAx BDMA Instance
00608   * @param  Channel This parameter can be one of the following values:
00609   *         @arg @ref LL_BDMA_CHANNEL_0
00610   *         @arg @ref LL_BDMA_CHANNEL_1
00611   *         @arg @ref LL_BDMA_CHANNEL_2
00612   *         @arg @ref LL_BDMA_CHANNEL_3
00613   *         @arg @ref LL_BDMA_CHANNEL_4
00614   *         @arg @ref LL_BDMA_CHANNEL_5
00615   *         @arg @ref LL_BDMA_CHANNEL_6
00616   *         @arg @ref LL_BDMA_CHANNEL_7
00617   * @retval Returned value can be one of the following values:
00618   *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
00619   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
00620   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
00621   */
00622 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
00623 {
00624   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00625
00626   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00627                    BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
00628 }
00629
00630 /**
00631   * @brief  Set BDMA mode circular or normal.
00632   * @note The circular buffer mode cannot be used if the memory-to-memory
00633   * data transfer is configured on the selected Channel.
00634   * @rmtoll CCR          CIRC          LL_BDMA_SetMode
00635   * @param  BDMAx BDMA Instance
00636   * @param  Channel This parameter can be one of the following values:
00637   *         @arg @ref LL_BDMA_CHANNEL_0
00638   *         @arg @ref LL_BDMA_CHANNEL_1
00639   *         @arg @ref LL_BDMA_CHANNEL_2
00640   *         @arg @ref LL_BDMA_CHANNEL_3
00641   *         @arg @ref LL_BDMA_CHANNEL_4
00642   *         @arg @ref LL_BDMA_CHANNEL_5
00643   *         @arg @ref LL_BDMA_CHANNEL_6
00644   *         @arg @ref LL_BDMA_CHANNEL_7
00645   * @param  Mode This parameter can be one of the following values:
00646   *         @arg @ref LL_BDMA_MODE_NORMAL
00647   *         @arg @ref LL_BDMA_MODE_CIRCULAR
00648   * @retval None
00649   */
00650 __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
00651 {
00652   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00653
00654   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
00655              Mode);
00656 }
00657
00658 /**
00659   * @brief  Get BDMA mode circular or normal.
00660   * @rmtoll CCR          CIRC          LL_BDMA_GetMode
00661   * @param  BDMAx BDMA Instance
00662   * @param  Channel This parameter can be one of the following values:
00663   *         @arg @ref LL_BDMA_CHANNEL_0
00664   *         @arg @ref LL_BDMA_CHANNEL_1
00665   *         @arg @ref LL_BDMA_CHANNEL_2
00666   *         @arg @ref LL_BDMA_CHANNEL_3
00667   *         @arg @ref LL_BDMA_CHANNEL_4
00668   *         @arg @ref LL_BDMA_CHANNEL_5
00669   *         @arg @ref LL_BDMA_CHANNEL_6
00670   *         @arg @ref LL_BDMA_CHANNEL_7
00671   * @retval Returned value can be one of the following values:
00672   *         @arg @ref LL_BDMA_MODE_NORMAL
00673   *         @arg @ref LL_BDMA_MODE_CIRCULAR
00674   */
00675 __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
00676 {
00677   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00678
00679   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00680                    BDMA_CCR_CIRC));
00681 }
00682
00683 /**
00684   * @brief  Set Peripheral increment mode.
00685   * @rmtoll CCR          PINC          LL_BDMA_SetPeriphIncMode
00686   * @param  BDMAx BDMA Instance
00687   * @param  Channel This parameter can be one of the following values:
00688   *         @arg @ref LL_BDMA_CHANNEL_0
00689   *         @arg @ref LL_BDMA_CHANNEL_1
00690   *         @arg @ref LL_BDMA_CHANNEL_2
00691   *         @arg @ref LL_BDMA_CHANNEL_3
00692   *         @arg @ref LL_BDMA_CHANNEL_4
00693   *         @arg @ref LL_BDMA_CHANNEL_5
00694   *         @arg @ref LL_BDMA_CHANNEL_6
00695   *         @arg @ref LL_BDMA_CHANNEL_7
00696   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00697   *         @arg @ref LL_BDMA_PERIPH_INCREMENT
00698   *         @arg @ref LL_BDMA_PERIPH_NOINCREMENT
00699   * @retval None
00700   */
00701 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00702 {
00703   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00704
00705   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
00706              PeriphOrM2MSrcIncMode);
00707 }
00708
00709 /**
00710   * @brief  Get Peripheral increment mode.
00711   * @rmtoll CCR          PINC          LL_BDMA_GetPeriphIncMode
00712   * @param  BDMAx BDMA Instance
00713   * @param  Channel This parameter can be one of the following values:
00714   *         @arg @ref LL_BDMA_CHANNEL_0
00715   *         @arg @ref LL_BDMA_CHANNEL_1
00716   *         @arg @ref LL_BDMA_CHANNEL_2
00717   *         @arg @ref LL_BDMA_CHANNEL_3
00718   *         @arg @ref LL_BDMA_CHANNEL_4
00719   *         @arg @ref LL_BDMA_CHANNEL_5
00720   *         @arg @ref LL_BDMA_CHANNEL_6
00721   *         @arg @ref LL_BDMA_CHANNEL_7
00722   * @retval Returned value can be one of the following values:
00723   *         @arg @ref LL_BDMA_PERIPH_INCREMENT
00724   *         @arg @ref LL_BDMA_PERIPH_NOINCREMENT
00725   */
00726 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
00727 {
00728   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00729
00730   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00731                    BDMA_CCR_PINC));
00732 }
00733
00734 /**
00735   * @brief  Set Memory increment mode.
00736   * @rmtoll CCR          MINC          LL_BDMA_SetMemoryIncMode
00737   * @param  BDMAx BDMA Instance
00738   * @param  Channel This parameter can be one of the following values:
00739   *         @arg @ref LL_BDMA_CHANNEL_0
00740   *         @arg @ref LL_BDMA_CHANNEL_1
00741   *         @arg @ref LL_BDMA_CHANNEL_2
00742   *         @arg @ref LL_BDMA_CHANNEL_3
00743   *         @arg @ref LL_BDMA_CHANNEL_4
00744   *         @arg @ref LL_BDMA_CHANNEL_5
00745   *         @arg @ref LL_BDMA_CHANNEL_6
00746   *         @arg @ref LL_BDMA_CHANNEL_7
00747   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00748   *         @arg @ref LL_BDMA_MEMORY_INCREMENT
00749   *         @arg @ref LL_BDMA_MEMORY_NOINCREMENT
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00753 {
00754   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00755
00756   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
00757              MemoryOrM2MDstIncMode);
00758 }
00759
00760 /**
00761   * @brief  Get Memory increment mode.
00762   * @rmtoll CCR          MINC          LL_BDMA_GetMemoryIncMode
00763   * @param  BDMAx BDMA Instance
00764   * @param  Channel This parameter can be one of the following values:
00765   *         @arg @ref LL_BDMA_CHANNEL_0
00766   *         @arg @ref LL_BDMA_CHANNEL_1
00767   *         @arg @ref LL_BDMA_CHANNEL_2
00768   *         @arg @ref LL_BDMA_CHANNEL_3
00769   *         @arg @ref LL_BDMA_CHANNEL_4
00770   *         @arg @ref LL_BDMA_CHANNEL_5
00771   *         @arg @ref LL_BDMA_CHANNEL_6
00772   *         @arg @ref LL_BDMA_CHANNEL_7
00773   * @retval Returned value can be one of the following values:
00774   *         @arg @ref LL_BDMA_MEMORY_INCREMENT
00775   *         @arg @ref LL_BDMA_MEMORY_NOINCREMENT
00776   */
00777 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
00778 {
00779   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00780
00781   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00782                    BDMA_CCR_MINC));
00783 }
00784
00785 /**
00786   * @brief  Set Peripheral size.
00787   * @rmtoll CCR          PSIZE         LL_BDMA_SetPeriphSize
00788   * @param  BDMAx BDMA Instance
00789   * @param  Channel This parameter can be one of the following values:
00790   *         @arg @ref LL_BDMA_CHANNEL_0
00791   *         @arg @ref LL_BDMA_CHANNEL_1
00792   *         @arg @ref LL_BDMA_CHANNEL_2
00793   *         @arg @ref LL_BDMA_CHANNEL_3
00794   *         @arg @ref LL_BDMA_CHANNEL_4
00795   *         @arg @ref LL_BDMA_CHANNEL_5
00796   *         @arg @ref LL_BDMA_CHANNEL_6
00797   *         @arg @ref LL_BDMA_CHANNEL_7
00798   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00799   *         @arg @ref LL_BDMA_PDATAALIGN_BYTE
00800   *         @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
00801   *         @arg @ref LL_BDMA_PDATAALIGN_WORD
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00805 {
00806   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00807
00808   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
00809              PeriphOrM2MSrcDataSize);
00810 }
00811
00812 /**
00813   * @brief  Get Peripheral size.
00814   * @rmtoll CCR          PSIZE         LL_BDMA_GetPeriphSize
00815   * @param  BDMAx BDMA Instance
00816   * @param  Channel This parameter can be one of the following values:
00817   *         @arg @ref LL_BDMA_CHANNEL_0
00818   *         @arg @ref LL_BDMA_CHANNEL_1
00819   *         @arg @ref LL_BDMA_CHANNEL_2
00820   *         @arg @ref LL_BDMA_CHANNEL_3
00821   *         @arg @ref LL_BDMA_CHANNEL_4
00822   *         @arg @ref LL_BDMA_CHANNEL_5
00823   *         @arg @ref LL_BDMA_CHANNEL_6
00824   *         @arg @ref LL_BDMA_CHANNEL_7
00825   * @retval Returned value can be one of the following values:
00826   *         @arg @ref LL_BDMA_PDATAALIGN_BYTE
00827   *         @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
00828   *         @arg @ref LL_BDMA_PDATAALIGN_WORD
00829   */
00830 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
00831 {
00832   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00833
00834   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00835                    BDMA_CCR_PSIZE));
00836 }
00837
00838 /**
00839   * @brief  Set Memory size.
00840   * @rmtoll CCR          MSIZE         LL_BDMA_SetMemorySize
00841   * @param  BDMAx BDMA Instance
00842   * @param  Channel This parameter can be one of the following values:
00843   *         @arg @ref LL_BDMA_CHANNEL_0
00844   *         @arg @ref LL_BDMA_CHANNEL_1
00845   *         @arg @ref LL_BDMA_CHANNEL_2
00846   *         @arg @ref LL_BDMA_CHANNEL_3
00847   *         @arg @ref LL_BDMA_CHANNEL_4
00848   *         @arg @ref LL_BDMA_CHANNEL_5
00849   *         @arg @ref LL_BDMA_CHANNEL_6
00850   *         @arg @ref LL_BDMA_CHANNEL_7
00851   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00852   *         @arg @ref LL_BDMA_MDATAALIGN_BYTE
00853   *         @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
00854   *         @arg @ref LL_BDMA_MDATAALIGN_WORD
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00858 {
00859   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00860
00861   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
00862              MemoryOrM2MDstDataSize);
00863 }
00864
00865 /**
00866   * @brief  Get Memory size.
00867   * @rmtoll CCR          MSIZE         LL_BDMA_GetMemorySize
00868   * @param  BDMAx BDMA Instance
00869   * @param  Channel This parameter can be one of the following values:
00870   *         @arg @ref LL_BDMA_CHANNEL_0
00871   *         @arg @ref LL_BDMA_CHANNEL_1
00872   *         @arg @ref LL_BDMA_CHANNEL_2
00873   *         @arg @ref LL_BDMA_CHANNEL_3
00874   *         @arg @ref LL_BDMA_CHANNEL_4
00875   *         @arg @ref LL_BDMA_CHANNEL_5
00876   *         @arg @ref LL_BDMA_CHANNEL_6
00877   *         @arg @ref LL_BDMA_CHANNEL_7
00878   * @retval Returned value can be one of the following values:
00879   *         @arg @ref LL_BDMA_MDATAALIGN_BYTE
00880   *         @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
00881   *         @arg @ref LL_BDMA_MDATAALIGN_WORD
00882   */
00883 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
00884 {
00885   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00886
00887   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00888                    BDMA_CCR_MSIZE));
00889 }
00890
00891 /**
00892   * @brief  Set Channel priority level.
00893   * @rmtoll CCR          PL            LL_BDMA_SetChannelPriorityLevel
00894   * @param  BDMAx BDMA Instance
00895   * @param  Channel This parameter can be one of the following values:
00896   *         @arg @ref LL_BDMA_CHANNEL_0
00897   *         @arg @ref LL_BDMA_CHANNEL_1
00898   *         @arg @ref LL_BDMA_CHANNEL_2
00899   *         @arg @ref LL_BDMA_CHANNEL_3
00900   *         @arg @ref LL_BDMA_CHANNEL_4
00901   *         @arg @ref LL_BDMA_CHANNEL_5
00902   *         @arg @ref LL_BDMA_CHANNEL_6
00903   *         @arg @ref LL_BDMA_CHANNEL_7
00904   * @param  Priority This parameter can be one of the following values:
00905   *         @arg @ref LL_BDMA_PRIORITY_LOW
00906   *         @arg @ref LL_BDMA_PRIORITY_MEDIUM
00907   *         @arg @ref LL_BDMA_PRIORITY_HIGH
00908   *         @arg @ref LL_BDMA_PRIORITY_VERYHIGH
00909   * @retval None
00910   */
00911 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
00912 {
00913   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00914
00915   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
00916              Priority);
00917 }
00918
00919 /**
00920   * @brief  Get Channel priority level.
00921   * @rmtoll CCR          PL            LL_BDMA_GetChannelPriorityLevel
00922   * @param  BDMAx BDMA Instance
00923   * @param  Channel This parameter can be one of the following values:
00924   *         @arg @ref LL_BDMA_CHANNEL_0
00925   *         @arg @ref LL_BDMA_CHANNEL_1
00926   *         @arg @ref LL_BDMA_CHANNEL_2
00927   *         @arg @ref LL_BDMA_CHANNEL_3
00928   *         @arg @ref LL_BDMA_CHANNEL_4
00929   *         @arg @ref LL_BDMA_CHANNEL_5
00930   *         @arg @ref LL_BDMA_CHANNEL_6
00931   *         @arg @ref LL_BDMA_CHANNEL_7
00932   * @retval Returned value can be one of the following values:
00933   *         @arg @ref LL_BDMA_PRIORITY_LOW
00934   *         @arg @ref LL_BDMA_PRIORITY_MEDIUM
00935   *         @arg @ref LL_BDMA_PRIORITY_HIGH
00936   *         @arg @ref LL_BDMA_PRIORITY_VERYHIGH
00937   */
00938 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
00939 {
00940   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00941
00942   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
00943                    BDMA_CCR_PL));
00944 }
00945
00946 /**
00947   * @brief  Set Number of data to transfer.
00948   * @note   This action has no effect if
00949   *         channel is enabled.
00950   * @rmtoll CNDTR        NDT           LL_BDMA_SetDataLength
00951   * @param  BDMAx BDMA Instance
00952   * @param  Channel This parameter can be one of the following values:
00953   *         @arg @ref LL_BDMA_CHANNEL_0
00954   *         @arg @ref LL_BDMA_CHANNEL_1
00955   *         @arg @ref LL_BDMA_CHANNEL_2
00956   *         @arg @ref LL_BDMA_CHANNEL_3
00957   *         @arg @ref LL_BDMA_CHANNEL_4
00958   *         @arg @ref LL_BDMA_CHANNEL_5
00959   *         @arg @ref LL_BDMA_CHANNEL_6
00960   *         @arg @ref LL_BDMA_CHANNEL_7
00961   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00962   * @retval None
00963   */
00964 __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
00965 {
00966   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00967
00968   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
00969              BDMA_CNDTR_NDT, NbData);
00970 }
00971
00972 /**
00973   * @brief  Get Number of data to transfer.
00974   * @note   Once the channel is enabled, the return value indicate the
00975   *         remaining bytes to be transmitted.
00976   * @rmtoll CNDTR        NDT           LL_BDMA_GetDataLength
00977   * @param  BDMAx BDMA Instance
00978   * @param  Channel This parameter can be one of the following values:
00979   *         @arg @ref LL_BDMA_CHANNEL_0
00980   *         @arg @ref LL_BDMA_CHANNEL_1
00981   *         @arg @ref LL_BDMA_CHANNEL_2
00982   *         @arg @ref LL_BDMA_CHANNEL_3
00983   *         @arg @ref LL_BDMA_CHANNEL_4
00984   *         @arg @ref LL_BDMA_CHANNEL_5
00985   *         @arg @ref LL_BDMA_CHANNEL_6
00986   *         @arg @ref LL_BDMA_CHANNEL_7
00987   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00988   */
00989 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
00990 {
00991   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
00992
00993   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
00994                    BDMA_CNDTR_NDT));
00995 }
00996
00997 /**
00998   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
00999   * @rmtoll CR          CT           LL_BDMA_SetCurrentTargetMem
01000   * @param  BDMAx BDMAx Instance
01001   * @param  Channel This parameter can be one of the following values:
01002   *         @arg @ref LL_BDMA_CHANNEL_0
01003   *         @arg @ref LL_BDMA_CHANNEL_1
01004   *         @arg @ref LL_BDMA_CHANNEL_2
01005   *         @arg @ref LL_BDMA_CHANNEL_3
01006   *         @arg @ref LL_BDMA_CHANNEL_4
01007   *         @arg @ref LL_BDMA_CHANNEL_5
01008   *         @arg @ref LL_BDMA_CHANNEL_6
01009   *         @arg @ref LL_BDMA_CHANNEL_7
01010   * @param CurrentMemory This parameter can be one of the following values:
01011   *         @arg @ref LL_BDMA_CURRENTTARGETMEM0
01012   *         @arg @ref LL_BDMA_CURRENTTARGETMEM1
01013   * @retval None
01014   */
01015 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
01016 {
01017   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01018
01019   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
01020 }
01021
01022 /**
01023   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
01024   * @rmtoll CR          CT           LL_BDMA_GetCurrentTargetMem
01025   * @param  BDMAx BDMAx Instance
01026   * @param  Channel This parameter can be one of the following values:
01027   *         @arg @ref LL_BDMA_CHANNEL_0
01028   *         @arg @ref LL_BDMA_CHANNEL_1
01029   *         @arg @ref LL_BDMA_CHANNEL_2
01030   *         @arg @ref LL_BDMA_CHANNEL_3
01031   *         @arg @ref LL_BDMA_CHANNEL_4
01032   *         @arg @ref LL_BDMA_CHANNEL_5
01033   *         @arg @ref LL_BDMA_CHANNEL_6
01034   *         @arg @ref LL_BDMA_CHANNEL_7
01035   * @retval Returned value can be one of the following values:
01036   *         @arg @ref LL_BDMA_CURRENTTARGETMEM0
01037   *         @arg @ref LL_BDMA_CURRENTTARGETMEM1
01038   */
01039 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
01040 {
01041   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01042
01043   return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
01044 }
01045
01046 /**
01047   * @brief Enable the double buffer mode.
01048   * @rmtoll CR          DBM           LL_BDMA_EnableDoubleBufferMode
01049   * @param  BDMAx BDMAx Instance
01050   * @param  Channel This parameter can be one of the following values:
01051   *         @arg @ref LL_BDMA_CHANNEL_0
01052   *         @arg @ref LL_BDMA_CHANNEL_1
01053   *         @arg @ref LL_BDMA_CHANNEL_2
01054   *         @arg @ref LL_BDMA_CHANNEL_3
01055   *         @arg @ref LL_BDMA_CHANNEL_4
01056   *         @arg @ref LL_BDMA_CHANNEL_5
01057   *         @arg @ref LL_BDMA_CHANNEL_6
01058   *         @arg @ref LL_BDMA_CHANNEL_7
01059   * @retval None
01060   */
01061 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
01062 {
01063   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01064
01065   SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
01066 }
01067
01068 /**
01069   * @brief Disable the double buffer mode.
01070   * @rmtoll CR          DBM           LL_BDMA_DisableDoubleBufferMode
01071   * @param  BDMAx BDMAx Instance
01072   * @param  Channel This parameter can be one of the following values:
01073   *         @arg @ref LL_BDMA_CHANNEL_0
01074   *         @arg @ref LL_BDMA_CHANNEL_1
01075   *         @arg @ref LL_BDMA_CHANNEL_2
01076   *         @arg @ref LL_BDMA_CHANNEL_3
01077   *         @arg @ref LL_BDMA_CHANNEL_4
01078   *         @arg @ref LL_BDMA_CHANNEL_5
01079   *         @arg @ref LL_BDMA_CHANNEL_6
01080   *         @arg @ref LL_BDMA_CHANNEL_7
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
01084 {
01085   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01086
01087   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
01088 }
01089
01090 /**
01091   * @brief  Configure the Source and Destination addresses.
01092   * @note   This API must not be called when the BDMA channel is enabled.
01093   * @note   Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr).
01094   * @rmtoll CPAR         PA            LL_BDMA_ConfigAddresses\n
01095   *         CMAR         MA            LL_BDMA_ConfigAddresses
01096   * @param  BDMAx BDMA Instance
01097   * @param  Channel This parameter can be one of the following values:
01098   *         @arg @ref LL_BDMA_CHANNEL_0
01099   *         @arg @ref LL_BDMA_CHANNEL_1
01100   *         @arg @ref LL_BDMA_CHANNEL_2
01101   *         @arg @ref LL_BDMA_CHANNEL_3
01102   *         @arg @ref LL_BDMA_CHANNEL_4
01103   *         @arg @ref LL_BDMA_CHANNEL_5
01104   *         @arg @ref LL_BDMA_CHANNEL_6
01105   *         @arg @ref LL_BDMA_CHANNEL_7
01106   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01107   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01108   * @param  Direction This parameter can be one of the following values:
01109   *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
01110   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
01111   *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
01112   * @retval None
01113   */
01114 __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
01115                                              uint32_t DstAddress, uint32_t Direction)
01116 {
01117   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01118
01119   /* Direction Memory to Periph */
01120   if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
01121   {
01122     WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
01123     WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
01124   }
01125   /* Direction Periph to Memory and Memory to Memory */
01126   else
01127   {
01128     WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
01129     WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
01130   }
01131 }
01132
01133 /**
01134   * @brief  Set the Memory address.
01135   * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
01136   * @note   This API must not be called when the BDMA channel is enabled.
01137   * @rmtoll CMAR         MA            LL_BDMA_SetMemoryAddress
01138   * @param  BDMAx BDMA Instance
01139   * @param  Channel This parameter can be one of the following values:
01140   *         @arg @ref LL_BDMA_CHANNEL_0
01141   *         @arg @ref LL_BDMA_CHANNEL_1
01142   *         @arg @ref LL_BDMA_CHANNEL_2
01143   *         @arg @ref LL_BDMA_CHANNEL_3
01144   *         @arg @ref LL_BDMA_CHANNEL_4
01145   *         @arg @ref LL_BDMA_CHANNEL_5
01146   *         @arg @ref LL_BDMA_CHANNEL_6
01147   *         @arg @ref LL_BDMA_CHANNEL_7
01148   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01149   * @retval None
01150   */
01151 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
01152 {
01153   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01154
01155   WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
01156 }
01157
01158 /**
01159   * @brief  Set the Peripheral address.
01160   * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
01161   * @note   This API must not be called when the BDMA channel is enabled.
01162   * @rmtoll CPAR         PA            LL_BDMA_SetPeriphAddress
01163   * @param  BDMAx BDMA Instance
01164   * @param  Channel This parameter can be one of the following values:
01165   *         @arg @ref LL_BDMA_CHANNEL_0
01166   *         @arg @ref LL_BDMA_CHANNEL_1
01167   *         @arg @ref LL_BDMA_CHANNEL_2
01168   *         @arg @ref LL_BDMA_CHANNEL_3
01169   *         @arg @ref LL_BDMA_CHANNEL_4
01170   *         @arg @ref LL_BDMA_CHANNEL_5
01171   *         @arg @ref LL_BDMA_CHANNEL_6
01172   *         @arg @ref LL_BDMA_CHANNEL_7
01173   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01174   * @retval None
01175   */
01176 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
01177 {
01178   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01179
01180   WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
01181 }
01182
01183 /**
01184   * @brief  Get Memory address.
01185   * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
01186   * @rmtoll CMAR         MA            LL_BDMA_GetMemoryAddress
01187   * @param  BDMAx BDMA Instance
01188   * @param  Channel This parameter can be one of the following values:
01189   *         @arg @ref LL_BDMA_CHANNEL_0
01190   *         @arg @ref LL_BDMA_CHANNEL_1
01191   *         @arg @ref LL_BDMA_CHANNEL_2
01192   *         @arg @ref LL_BDMA_CHANNEL_3
01193   *         @arg @ref LL_BDMA_CHANNEL_4
01194   *         @arg @ref LL_BDMA_CHANNEL_5
01195   *         @arg @ref LL_BDMA_CHANNEL_6
01196   *         @arg @ref LL_BDMA_CHANNEL_7
01197   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01198   */
01199 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
01200 {
01201   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01202
01203   return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
01204 }
01205
01206 /**
01207   * @brief  Get Peripheral address.
01208   * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
01209   * @rmtoll CPAR         PA            LL_BDMA_GetPeriphAddress
01210   * @param  BDMAx BDMA Instance
01211   * @param  Channel This parameter can be one of the following values:
01212   *         @arg @ref LL_BDMA_CHANNEL_0
01213   *         @arg @ref LL_BDMA_CHANNEL_1
01214   *         @arg @ref LL_BDMA_CHANNEL_2
01215   *         @arg @ref LL_BDMA_CHANNEL_3
01216   *         @arg @ref LL_BDMA_CHANNEL_4
01217   *         @arg @ref LL_BDMA_CHANNEL_5
01218   *         @arg @ref LL_BDMA_CHANNEL_6
01219   *         @arg @ref LL_BDMA_CHANNEL_7
01220   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01221   */
01222 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
01223 {
01224   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01225
01226   return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
01227 }
01228
01229 /**
01230   * @brief  Set the Memory to Memory Source address.
01231   * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
01232   * @note   This API must not be called when the BDMA channel is enabled.
01233   * @rmtoll CPAR         PA            LL_BDMA_SetM2MSrcAddress
01234   * @param  BDMAx BDMA Instance
01235   * @param  Channel This parameter can be one of the following values:
01236   *         @arg @ref LL_BDMA_CHANNEL_0
01237   *         @arg @ref LL_BDMA_CHANNEL_1
01238   *         @arg @ref LL_BDMA_CHANNEL_2
01239   *         @arg @ref LL_BDMA_CHANNEL_3
01240   *         @arg @ref LL_BDMA_CHANNEL_4
01241   *         @arg @ref LL_BDMA_CHANNEL_5
01242   *         @arg @ref LL_BDMA_CHANNEL_6
01243   *         @arg @ref LL_BDMA_CHANNEL_7
01244   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01245   * @retval None
01246   */
01247 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
01248 {
01249   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01250
01251   WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
01252 }
01253
01254 /**
01255   * @brief  Set the Memory to Memory Destination address.
01256   * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
01257   * @note   This API must not be called when the BDMA channel is enabled.
01258   * @rmtoll CMAR         MA            LL_BDMA_SetM2MDstAddress
01259   * @param  BDMAx BDMA Instance
01260   * @param  Channel This parameter can be one of the following values:
01261   *         @arg @ref LL_BDMA_CHANNEL_0
01262   *         @arg @ref LL_BDMA_CHANNEL_1
01263   *         @arg @ref LL_BDMA_CHANNEL_2
01264   *         @arg @ref LL_BDMA_CHANNEL_3
01265   *         @arg @ref LL_BDMA_CHANNEL_4
01266   *         @arg @ref LL_BDMA_CHANNEL_5
01267   *         @arg @ref LL_BDMA_CHANNEL_6
01268   *         @arg @ref LL_BDMA_CHANNEL_7
01269   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01270   * @retval None
01271   */
01272 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
01273 {
01274   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01275
01276   WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
01277 }
01278
01279 /**
01280   * @brief  Get the Memory to Memory Source address.
01281   * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
01282   * @rmtoll CPAR         PA            LL_BDMA_GetM2MSrcAddress
01283   * @param  BDMAx BDMA Instance
01284   * @param  Channel This parameter can be one of the following values:
01285   *         @arg @ref LL_BDMA_CHANNEL_0
01286   *         @arg @ref LL_BDMA_CHANNEL_1
01287   *         @arg @ref LL_BDMA_CHANNEL_2
01288   *         @arg @ref LL_BDMA_CHANNEL_3
01289   *         @arg @ref LL_BDMA_CHANNEL_4
01290   *         @arg @ref LL_BDMA_CHANNEL_5
01291   *         @arg @ref LL_BDMA_CHANNEL_6
01292   *         @arg @ref LL_BDMA_CHANNEL_7
01293   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01294   */
01295 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
01296 {
01297   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01298
01299   return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
01300 }
01301
01302 /**
01303   * @brief  Get the Memory to Memory Destination address.
01304   * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
01305   * @rmtoll CMAR         MA            LL_BDMA_GetM2MDstAddress
01306   * @param  BDMAx BDMA Instance
01307   * @param  Channel This parameter can be one of the following values:
01308   *         @arg @ref LL_BDMA_CHANNEL_0
01309   *         @arg @ref LL_BDMA_CHANNEL_1
01310   *         @arg @ref LL_BDMA_CHANNEL_2
01311   *         @arg @ref LL_BDMA_CHANNEL_3
01312   *         @arg @ref LL_BDMA_CHANNEL_4
01313   *         @arg @ref LL_BDMA_CHANNEL_5
01314   *         @arg @ref LL_BDMA_CHANNEL_6
01315   *         @arg @ref LL_BDMA_CHANNEL_7
01316   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01317   */
01318 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
01319 {
01320   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01321
01322   return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
01323 }
01324
01325 /**
01326   * @brief Set Memory 1 address (used in case of Double buffer mode).
01327   * @rmtoll M1AR        M1A         LL_BDMA_SetMemory1Address
01328   * @param  BDMAx BDMAx Instance
01329   * @param  Channel This parameter can be one of the following values:
01330   *         @arg @ref LL_BDMA_CHANNEL_0
01331   *         @arg @ref LL_BDMA_CHANNEL_1
01332   *         @arg @ref LL_BDMA_CHANNEL_2
01333   *         @arg @ref LL_BDMA_CHANNEL_3
01334   *         @arg @ref LL_BDMA_CHANNEL_4
01335   *         @arg @ref LL_BDMA_CHANNEL_5
01336   *         @arg @ref LL_BDMA_CHANNEL_6
01337   *         @arg @ref LL_BDMA_CHANNEL_7
01338   * @param  Address Between 0 to 0xFFFFFFFF
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
01342 {
01343   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01344
01345   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
01346 }
01347
01348 /**
01349   * @brief Get Memory 1 address (used in case of Double buffer mode).
01350   * @rmtoll M1AR        M1A         LL_BDMA_GetMemory1Address
01351   * @param  BDMAx BDMAx Instance
01352   * @param  Channel This parameter can be one of the following values:
01353   *         @arg @ref LL_BDMA_CHANNEL_0
01354   *         @arg @ref LL_BDMA_CHANNEL_1
01355   *         @arg @ref LL_BDMA_CHANNEL_2
01356   *         @arg @ref LL_BDMA_CHANNEL_3
01357   *         @arg @ref LL_BDMA_CHANNEL_4
01358   *         @arg @ref LL_BDMA_CHANNEL_5
01359   *         @arg @ref LL_BDMA_CHANNEL_6
01360   *         @arg @ref LL_BDMA_CHANNEL_7
01361   * @retval Between 0 to 0xFFFFFFFF
01362   */
01363 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
01364 {
01365   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
01366
01367   return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
01368 }
01369
01370 /**
01371   * @brief  Set BDMA request for BDMA Channels on DMAMUX Channel x.
01372   * @note   DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
01373   * @rmtoll CxCR         DMAREQ_ID     LL_BDMA_SetPeriphRequest
01374   * @param  BDMAx BDMAx Instance
01375   * @param  Channel This parameter can be one of the following values:
01376   *         @arg @ref LL_BDMA_CHANNEL_0
01377   *         @arg @ref LL_BDMA_CHANNEL_1
01378   *         @arg @ref LL_BDMA_CHANNEL_2
01379   *         @arg @ref LL_BDMA_CHANNEL_3
01380   *         @arg @ref LL_BDMA_CHANNEL_4
01381   *         @arg @ref LL_BDMA_CHANNEL_5
01382   *         @arg @ref LL_BDMA_CHANNEL_6
01383   *         @arg @ref LL_BDMA_CHANNEL_7
01384   * @param  Request This parameter can be one of the following values:
01385   *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
01386   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
01387   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
01388   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
01389   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
01390   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
01391   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
01392   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
01393   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
01394   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
01395   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
01396   *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
01397   *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
01398   *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
01399   *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
01400   *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
01401   *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
01402   *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
01403   *         @arg @ref LL_DMAMUX2_REQ_DAC3 (*)
01404   *         @arg @ref LL_DMAMUX2_REQ_DFSDM2 (*)
01405   * @note   (*) Availability depends on devices.
01406   * @retval None
01407   */
01408 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
01409 {
01410   UNUSED(BDMAx);
01411   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
01412 }
01413
01414 /**
01415   * @brief  Get BDMA request for BDMA Channels on DMAMUX Channel x.
01416   * @note   DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.
01417   * @rmtoll CxCR         DMAREQ_ID     LL_BDMA_GetPeriphRequest
01418   * @param  BDMAx BDMAx Instance
01419   * @param  Channel This parameter can be one of the following values:
01420   *         @arg @ref LL_BDMA_CHANNEL_0
01421   *         @arg @ref LL_BDMA_CHANNEL_1
01422   *         @arg @ref LL_BDMA_CHANNEL_2
01423   *         @arg @ref LL_BDMA_CHANNEL_3
01424   *         @arg @ref LL_BDMA_CHANNEL_4
01425   *         @arg @ref LL_BDMA_CHANNEL_5
01426   *         @arg @ref LL_BDMA_CHANNEL_6
01427   *         @arg @ref LL_BDMA_CHANNEL_7
01428   * @retval Returned value can be one of the following values:
01429   *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
01430   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
01431   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
01432   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
01433   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
01434   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
01435   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
01436   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
01437   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
01438   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
01439   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
01440   *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
01441   *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
01442   *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
01443   *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
01444   *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
01445   *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
01446   *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
01447   *         @arg @ref LL_DMAMUX2_REQ_DAC3 (*)
01448   *         @arg @ref LL_DMAMUX2_REQ_DFSDM2 (*)
01449   * @note   (*) Availability depends on devices.
01450   */
01451 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
01452 {
01453   UNUSED(BDMAx);
01454   return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
01455 }
01456
01457 /**
01458   * @}
01459   */
01460
01461
01462 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management
01463   * @{
01464   */
01465 /**
01466   * @brief  Get Channel 0 global interrupt flag.
01467   * @rmtoll ISR          GIF0          LL_BDMA_IsActiveFlag_GI0
01468   * @param  BDMAx BDMA Instance
01469   * @retval State of bit (1 or 0).
01470   */
01471 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)
01472 {
01473   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
01474 }
01475
01476 /**
01477   * @brief  Get Channel 1 global interrupt flag.
01478   * @rmtoll ISR          GIF1          LL_BDMA_IsActiveFlag_GI1
01479   * @param  BDMAx BDMA Instance
01480   * @retval State of bit (1 or 0).
01481   */
01482 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)
01483 {
01484   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
01485 }
01486
01487 /**
01488   * @brief  Get Channel 2 global interrupt flag.
01489   * @rmtoll ISR          GIF2          LL_BDMA_IsActiveFlag_GI2
01490   * @param  BDMAx BDMA Instance
01491   * @retval State of bit (1 or 0).
01492   */
01493 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)
01494 {
01495   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
01496 }
01497
01498 /**
01499   * @brief  Get Channel 3 global interrupt flag.
01500   * @rmtoll ISR          GIF3          LL_BDMA_IsActiveFlag_GI3
01501   * @param  BDMAx BDMA Instance
01502   * @retval State of bit (1 or 0).
01503   */
01504 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)
01505 {
01506   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
01507 }
01508
01509 /**
01510   * @brief  Get Channel 4 global interrupt flag.
01511   * @rmtoll ISR          GIF4          LL_BDMA_IsActiveFlag_GI4
01512   * @param  BDMAx BDMA Instance
01513   * @retval State of bit (1 or 0).
01514   */
01515 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)
01516 {
01517   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
01518 }
01519
01520 /**
01521   * @brief  Get Channel 5 global interrupt flag.
01522   * @rmtoll ISR          GIF5          LL_BDMA_IsActiveFlag_GI5
01523   * @param  BDMAx BDMA Instance
01524   * @retval State of bit (1 or 0).
01525   */
01526 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)
01527 {
01528   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
01529 }
01530
01531 /**
01532   * @brief  Get Channel 6 global interrupt flag.
01533   * @rmtoll ISR          GIF6          LL_BDMA_IsActiveFlag_GI6
01534   * @param  BDMAx BDMA Instance
01535   * @retval State of bit (1 or 0).
01536   */
01537 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)
01538 {
01539   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
01540 }
01541
01542 /**
01543   * @brief  Get Channel 7 global interrupt flag.
01544   * @rmtoll ISR          GIF7          LL_BDMA_IsActiveFlag_GI7
01545   * @param  BDMAx BDMA Instance
01546   * @retval State of bit (1 or 0).
01547   */
01548 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)
01549 {
01550   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
01551 }
01552
01553 /**
01554   * @brief  Get Channel 0 transfer complete flag.
01555   * @rmtoll ISR          TCIF0         LL_BDMA_IsActiveFlag_TC0
01556   * @param  BDMAx BDMA Instance
01557   * @retval State of bit (1 or 0).
01558   */
01559 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)
01560 {
01561   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
01562 }
01563 /**
01564   * @brief  Get Channel 1 transfer complete flag.
01565   * @rmtoll ISR          TCIF1         LL_BDMA_IsActiveFlag_TC1
01566   * @param  BDMAx BDMA Instance
01567   * @retval State of bit (1 or 0).
01568   */
01569 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)
01570 {
01571   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
01572 }
01573
01574 /**
01575   * @brief  Get Channel 2 transfer complete flag.
01576   * @rmtoll ISR          TCIF2         LL_BDMA_IsActiveFlag_TC2
01577   * @param  BDMAx BDMA Instance
01578   * @retval State of bit (1 or 0).
01579   */
01580 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)
01581 {
01582   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
01583 }
01584
01585 /**
01586   * @brief  Get Channel 3 transfer complete flag.
01587   * @rmtoll ISR          TCIF3         LL_BDMA_IsActiveFlag_TC3
01588   * @param  BDMAx BDMA Instance
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)
01592 {
01593   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Get Channel 4 transfer complete flag.
01598   * @rmtoll ISR          TCIF4         LL_BDMA_IsActiveFlag_TC4
01599   * @param  BDMAx BDMA Instance
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)
01603 {
01604   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Get Channel 5 transfer complete flag.
01609   * @rmtoll ISR          TCIF5         LL_BDMA_IsActiveFlag_TC5
01610   * @param  BDMAx BDMA Instance
01611   * @retval State of bit (1 or 0).
01612   */
01613 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)
01614 {
01615   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
01616 }
01617
01618 /**
01619   * @brief  Get Channel 6 transfer complete flag.
01620   * @rmtoll ISR          TCIF6         LL_BDMA_IsActiveFlag_TC6
01621   * @param  BDMAx BDMA Instance
01622   * @retval State of bit (1 or 0).
01623   */
01624 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)
01625 {
01626   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
01627 }
01628
01629 /**
01630   * @brief  Get Channel 7 transfer complete flag.
01631   * @rmtoll ISR          TCIF7         LL_BDMA_IsActiveFlag_TC7
01632   * @param  BDMAx BDMA Instance
01633   * @retval State of bit (1 or 0).
01634   */
01635 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)
01636 {
01637   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
01638 }
01639
01640 /**
01641   * @brief  Get Channel 0 half transfer flag.
01642   * @rmtoll ISR          HTIF0         LL_BDMA_IsActiveFlag_HT0
01643   * @param  BDMAx BDMA Instance
01644   * @retval State of bit (1 or 0).
01645   */
01646 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)
01647 {
01648   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
01649 }
01650
01651 /**
01652   * @brief  Get Channel 1 half transfer flag.
01653   * @rmtoll ISR          HTIF1         LL_BDMA_IsActiveFlag_HT1
01654   * @param  BDMAx BDMA Instance
01655   * @retval State of bit (1 or 0).
01656   */
01657 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)
01658 {
01659   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
01660 }
01661
01662 /**
01663   * @brief  Get Channel 2 half transfer flag.
01664   * @rmtoll ISR          HTIF2         LL_BDMA_IsActiveFlag_HT2
01665   * @param  BDMAx BDMA Instance
01666   * @retval State of bit (1 or 0).
01667   */
01668 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)
01669 {
01670   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
01671 }
01672
01673 /**
01674   * @brief  Get Channel 3 half transfer flag.
01675   * @rmtoll ISR          HTIF3         LL_BDMA_IsActiveFlag_HT3
01676   * @param  BDMAx BDMA Instance
01677   * @retval State of bit (1 or 0).
01678   */
01679 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)
01680 {
01681   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
01682 }
01683
01684 /**
01685   * @brief  Get Channel 4 half transfer flag.
01686   * @rmtoll ISR          HTIF4         LL_BDMA_IsActiveFlag_HT4
01687   * @param  BDMAx BDMA Instance
01688   * @retval State of bit (1 or 0).
01689   */
01690 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)
01691 {
01692   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
01693 }
01694
01695 /**
01696   * @brief  Get Channel 5 half transfer flag.
01697   * @rmtoll ISR          HTIF5         LL_BDMA_IsActiveFlag_HT5
01698   * @param  BDMAx BDMA Instance
01699   * @retval State of bit (1 or 0).
01700   */
01701 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)
01702 {
01703   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
01704 }
01705
01706 /**
01707   * @brief  Get Channel 6 half transfer flag.
01708   * @rmtoll ISR          HTIF6         LL_BDMA_IsActiveFlag_HT6
01709   * @param  BDMAx BDMA Instance
01710   * @retval State of bit (1 or 0).
01711   */
01712 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)
01713 {
01714   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
01715 }
01716
01717 /**
01718   * @brief  Get Channel 7 half transfer flag.
01719   * @rmtoll ISR          HTIF7         LL_BDMA_IsActiveFlag_HT7
01720   * @param  BDMAx BDMA Instance
01721   * @retval State of bit (1 or 0).
01722   */
01723 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)
01724 {
01725   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
01726 }
01727
01728 /**
01729   * @brief  Get Channel 0 transfer error flag.
01730   * @rmtoll ISR          TEIF0         LL_BDMA_IsActiveFlag_TE0
01731   * @param  BDMAx BDMA Instance
01732   * @retval State of bit (1 or 0).
01733   */
01734 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)
01735 {
01736   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
01737 }
01738
01739 /**
01740   * @brief  Get Channel 1 transfer error flag.
01741   * @rmtoll ISR          TEIF1         LL_BDMA_IsActiveFlag_TE1
01742   * @param  BDMAx BDMA Instance
01743   * @retval State of bit (1 or 0).
01744   */
01745 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)
01746 {
01747   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
01748 }
01749
01750 /**
01751   * @brief  Get Channel 2 transfer error flag.
01752   * @rmtoll ISR          TEIF2         LL_BDMA_IsActiveFlag_TE2
01753   * @param  BDMAx BDMA Instance
01754   * @retval State of bit (1 or 0).
01755   */
01756 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)
01757 {
01758   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
01759 }
01760
01761 /**
01762   * @brief  Get Channel 3 transfer error flag.
01763   * @rmtoll ISR          TEIF3         LL_BDMA_IsActiveFlag_TE3
01764   * @param  BDMAx BDMA Instance
01765   * @retval State of bit (1 or 0).
01766   */
01767 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)
01768 {
01769   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
01770 }
01771
01772 /**
01773   * @brief  Get Channel 4 transfer error flag.
01774   * @rmtoll ISR          TEIF4         LL_BDMA_IsActiveFlag_TE4
01775   * @param  BDMAx BDMA Instance
01776   * @retval State of bit (1 or 0).
01777   */
01778 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)
01779 {
01780   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
01781 }
01782
01783 /**
01784   * @brief  Get Channel 5 transfer error flag.
01785   * @rmtoll ISR          TEIF5         LL_BDMA_IsActiveFlag_TE5
01786   * @param  BDMAx BDMA Instance
01787   * @retval State of bit (1 or 0).
01788   */
01789 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)
01790 {
01791   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
01792 }
01793
01794 /**
01795   * @brief  Get Channel 6 transfer error flag.
01796   * @rmtoll ISR          TEIF6         LL_BDMA_IsActiveFlag_TE6
01797   * @param  BDMAx BDMA Instance
01798   * @retval State of bit (1 or 0).
01799   */
01800 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)
01801 {
01802   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
01803 }
01804
01805 /**
01806   * @brief  Get Channel 7 transfer error flag.
01807   * @rmtoll ISR          TEIF7         LL_BDMA_IsActiveFlag_TE7
01808   * @param  BDMAx BDMA Instance
01809   * @retval State of bit (1 or 0).
01810   */
01811 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
01812 {
01813   return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
01814 }
01815
01816 /**
01817   * @brief  Clear Channel 0 global interrupt flag.
01818   * @rmtoll IFCR         CGIF0         LL_BDMA_ClearFlag_GI0
01819   * @param  BDMAx BDMA Instance
01820   * @retval None
01821   */
01822 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
01823 {
01824   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
01825 }
01826
01827 /**
01828   * @brief  Clear Channel 1 global interrupt flag.
01829   * @rmtoll IFCR         CGIF1         LL_BDMA_ClearFlag_GI1
01830   * @param  BDMAx BDMA Instance
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
01834 {
01835   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
01836 }
01837
01838 /**
01839   * @brief  Clear Channel 2 global interrupt flag.
01840   * @rmtoll IFCR         CGIF2         LL_BDMA_ClearFlag_GI2
01841   * @param  BDMAx BDMA Instance
01842   * @retval None
01843   */
01844 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
01845 {
01846   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
01847 }
01848
01849 /**
01850   * @brief  Clear Channel 3 global interrupt flag.
01851   * @rmtoll IFCR         CGIF3         LL_BDMA_ClearFlag_GI3
01852   * @param  BDMAx BDMA Instance
01853   * @retval None
01854   */
01855 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
01856 {
01857   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
01858 }
01859
01860 /**
01861   * @brief  Clear Channel 4 global interrupt flag.
01862   * @rmtoll IFCR         CGIF4         LL_BDMA_ClearFlag_GI4
01863   * @param  BDMAx BDMA Instance
01864   * @retval None
01865   */
01866 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
01867 {
01868   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
01869 }
01870
01871 /**
01872   * @brief  Clear Channel 5 global interrupt flag.
01873   * @rmtoll IFCR         CGIF5         LL_BDMA_ClearFlag_GI5
01874   * @param  BDMAx BDMA Instance
01875   * @retval None
01876   */
01877 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
01878 {
01879   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
01880 }
01881
01882 /**
01883   * @brief  Clear Channel 6 global interrupt flag.
01884   * @rmtoll IFCR         CGIF6         LL_BDMA_ClearFlag_GI6
01885   * @param  BDMAx BDMA Instance
01886   * @retval None
01887   */
01888 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
01889 {
01890   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
01891 }
01892
01893 /**
01894   * @brief  Clear Channel 7 global interrupt flag.
01895   * @rmtoll IFCR         CGIF7         LL_BDMA_ClearFlag_GI7
01896   * @param  BDMAx BDMA Instance
01897   * @retval None
01898   */
01899 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
01900 {
01901   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
01902 }
01903
01904 /**
01905   * @brief  Clear Channel 0  transfer complete flag.
01906   * @rmtoll IFCR         CTCIF0        LL_BDMA_ClearFlag_TC0
01907   * @param  BDMAx BDMA Instance
01908   * @retval None
01909   */
01910 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
01911 {
01912   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
01913 }
01914
01915 /**
01916   * @brief  Clear Channel 1  transfer complete flag.
01917   * @rmtoll IFCR         CTCIF1        LL_BDMA_ClearFlag_TC1
01918   * @param  BDMAx BDMA Instance
01919   * @retval None
01920   */
01921 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
01922 {
01923   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
01924 }
01925
01926 /**
01927   * @brief  Clear Channel 2  transfer complete flag.
01928   * @rmtoll IFCR         CTCIF2        LL_BDMA_ClearFlag_TC2
01929   * @param  BDMAx BDMA Instance
01930   * @retval None
01931   */
01932 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
01933 {
01934   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
01935 }
01936
01937 /**
01938   * @brief  Clear Channel 3  transfer complete flag.
01939   * @rmtoll IFCR         CTCIF3        LL_BDMA_ClearFlag_TC3
01940   * @param  BDMAx BDMA Instance
01941   * @retval None
01942   */
01943 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
01944 {
01945   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
01946 }
01947
01948 /**
01949   * @brief  Clear Channel 4  transfer complete flag.
01950   * @rmtoll IFCR         CTCIF4        LL_BDMA_ClearFlag_TC4
01951   * @param  BDMAx BDMA Instance
01952   * @retval None
01953   */
01954 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
01955 {
01956   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
01957 }
01958
01959 /**
01960   * @brief  Clear Channel 5  transfer complete flag.
01961   * @rmtoll IFCR         CTCIF5        LL_BDMA_ClearFlag_TC5
01962   * @param  BDMAx BDMA Instance
01963   * @retval None
01964   */
01965 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
01966 {
01967   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
01968 }
01969
01970 /**
01971   * @brief  Clear Channel 6  transfer complete flag.
01972   * @rmtoll IFCR         CTCIF6        LL_BDMA_ClearFlag_TC6
01973   * @param  BDMAx BDMA Instance
01974   * @retval None
01975   */
01976 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
01977 {
01978   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
01979 }
01980
01981 /**
01982   * @brief  Clear Channel 7  transfer complete flag.
01983   * @rmtoll IFCR         CTCIF7        LL_BDMA_ClearFlag_TC7
01984   * @param  BDMAx BDMA Instance
01985   * @retval None
01986   */
01987 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
01988 {
01989   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
01990 }
01991
01992 /**
01993   * @brief  Clear Channel 0  half transfer flag.
01994   * @rmtoll IFCR         CHTIF0        LL_BDMA_ClearFlag_HT0
01995   * @param  BDMAx BDMA Instance
01996   * @retval None
01997   */
01998 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
01999 {
02000   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
02001 }
02002
02003 /**
02004   * @brief  Clear Channel 1  half transfer flag.
02005   * @rmtoll IFCR         CHTIF1        LL_BDMA_ClearFlag_HT1
02006   * @param  BDMAx BDMA Instance
02007   * @retval None
02008   */
02009 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
02010 {
02011   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
02012 }
02013
02014 /**
02015   * @brief  Clear Channel 2  half transfer flag.
02016   * @rmtoll IFCR         CHTIF2        LL_BDMA_ClearFlag_HT2
02017   * @param  BDMAx BDMA Instance
02018   * @retval None
02019   */
02020 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
02021 {
02022   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
02023 }
02024
02025 /**
02026   * @brief  Clear Channel 3  half transfer flag.
02027   * @rmtoll IFCR         CHTIF3        LL_BDMA_ClearFlag_HT3
02028   * @param  BDMAx BDMA Instance
02029   * @retval None
02030   */
02031 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
02032 {
02033   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
02034 }
02035
02036 /**
02037   * @brief  Clear Channel 4  half transfer flag.
02038   * @rmtoll IFCR         CHTIF4        LL_BDMA_ClearFlag_HT4
02039   * @param  BDMAx BDMA Instance
02040   * @retval None
02041   */
02042 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
02043 {
02044   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
02045 }
02046
02047 /**
02048   * @brief  Clear Channel 5  half transfer flag.
02049   * @rmtoll IFCR         CHTIF5        LL_BDMA_ClearFlag_HT5
02050   * @param  BDMAx BDMA Instance
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
02054 {
02055   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
02056 }
02057
02058 /**
02059   * @brief  Clear Channel 6  half transfer flag.
02060   * @rmtoll IFCR         CHTIF6        LL_BDMA_ClearFlag_HT6
02061   * @param  BDMAx BDMA Instance
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
02065 {
02066   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
02067 }
02068
02069 /**
02070   * @brief  Clear Channel 7  half transfer flag.
02071   * @rmtoll IFCR         CHTIF7        LL_BDMA_ClearFlag_HT7
02072   * @param  BDMAx BDMA Instance
02073   * @retval None
02074   */
02075 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
02076 {
02077   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
02078 }
02079
02080 /**
02081   * @brief  Clear Channel 0 transfer error flag.
02082   * @rmtoll IFCR         CTEIF0        LL_BDMA_ClearFlag_TE0
02083   * @param  BDMAx BDMA Instance
02084   * @retval None
02085   */
02086 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
02087 {
02088   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
02089 }
02090
02091 /**
02092   * @brief  Clear Channel 1 transfer error flag.
02093   * @rmtoll IFCR         CTEIF1        LL_BDMA_ClearFlag_TE1
02094   * @param  BDMAx BDMA Instance
02095   * @retval None
02096   */
02097 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
02098 {
02099   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
02100 }
02101
02102 /**
02103   * @brief  Clear Channel 2 transfer error flag.
02104   * @rmtoll IFCR         CTEIF2        LL_BDMA_ClearFlag_TE2
02105   * @param  BDMAx BDMA Instance
02106   * @retval None
02107   */
02108 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
02109 {
02110   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
02111 }
02112
02113 /**
02114   * @brief  Clear Channel 3 transfer error flag.
02115   * @rmtoll IFCR         CTEIF3        LL_BDMA_ClearFlag_TE3
02116   * @param  BDMAx BDMA Instance
02117   * @retval None
02118   */
02119 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
02120 {
02121   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
02122 }
02123
02124 /**
02125   * @brief  Clear Channel 4 transfer error flag.
02126   * @rmtoll IFCR         CTEIF4        LL_BDMA_ClearFlag_TE4
02127   * @param  BDMAx BDMA Instance
02128   * @retval None
02129   */
02130 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
02131 {
02132   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
02133 }
02134
02135 /**
02136   * @brief  Clear Channel 5 transfer error flag.
02137   * @rmtoll IFCR         CTEIF5        LL_BDMA_ClearFlag_TE5
02138   * @param  BDMAx BDMA Instance
02139   * @retval None
02140   */
02141 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
02142 {
02143   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
02144 }
02145
02146 /**
02147   * @brief  Clear Channel 6 transfer error flag.
02148   * @rmtoll IFCR         CTEIF6        LL_BDMA_ClearFlag_TE6
02149   * @param  BDMAx BDMA Instance
02150   * @retval None
02151   */
02152 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
02153 {
02154   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
02155 }
02156
02157 /**
02158   * @brief  Clear Channel 7 transfer error flag.
02159   * @rmtoll IFCR         CTEIF7        LL_BDMA_ClearFlag_TE7
02160   * @param  BDMAx BDMA Instance
02161   * @retval None
02162   */
02163 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
02164 {
02165   WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
02166 }
02167
02168 /**
02169   * @}
02170   */
02171
02172 /** @defgroup BDMA_LL_EF_IT_Management IT_Management
02173   * @{
02174   */
02175 /**
02176   * @brief  Enable Transfer complete interrupt.
02177   * @rmtoll CCR          TCIE          LL_BDMA_EnableIT_TC
02178   * @param  BDMAx BDMA Instance
02179   * @param  Channel This parameter can be one of the following values:
02180   *         @arg @ref LL_BDMA_CHANNEL_0
02181   *         @arg @ref LL_BDMA_CHANNEL_1
02182   *         @arg @ref LL_BDMA_CHANNEL_2
02183   *         @arg @ref LL_BDMA_CHANNEL_3
02184   *         @arg @ref LL_BDMA_CHANNEL_4
02185   *         @arg @ref LL_BDMA_CHANNEL_5
02186   *         @arg @ref LL_BDMA_CHANNEL_6
02187   *         @arg @ref LL_BDMA_CHANNEL_7
02188   * @retval None
02189   */
02190 __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
02191 {
02192   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02193
02194   SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
02195 }
02196
02197 /**
02198   * @brief  Enable Half transfer interrupt.
02199   * @rmtoll CCR          HTIE          LL_BDMA_EnableIT_HT
02200   * @param  BDMAx BDMA Instance
02201   * @param  Channel This parameter can be one of the following values:
02202   *         @arg @ref LL_BDMA_CHANNEL_0
02203   *         @arg @ref LL_BDMA_CHANNEL_1
02204   *         @arg @ref LL_BDMA_CHANNEL_2
02205   *         @arg @ref LL_BDMA_CHANNEL_3
02206   *         @arg @ref LL_BDMA_CHANNEL_4
02207   *         @arg @ref LL_BDMA_CHANNEL_5
02208   *         @arg @ref LL_BDMA_CHANNEL_6
02209   *         @arg @ref LL_BDMA_CHANNEL_7
02210   * @retval None
02211   */
02212 __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
02213 {
02214   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02215
02216   SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
02217 }
02218
02219 /**
02220   * @brief  Enable Transfer error interrupt.
02221   * @rmtoll CCR          TEIE          LL_BDMA_EnableIT_TE
02222   * @param  BDMAx BDMA Instance
02223   * @param  Channel This parameter can be one of the following values:
02224   *         @arg @ref LL_BDMA_CHANNEL_0
02225   *         @arg @ref LL_BDMA_CHANNEL_1
02226   *         @arg @ref LL_BDMA_CHANNEL_2
02227   *         @arg @ref LL_BDMA_CHANNEL_3
02228   *         @arg @ref LL_BDMA_CHANNEL_4
02229   *         @arg @ref LL_BDMA_CHANNEL_5
02230   *         @arg @ref LL_BDMA_CHANNEL_6
02231   *         @arg @ref LL_BDMA_CHANNEL_7
02232   * @retval None
02233   */
02234 __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
02235 {
02236   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02237
02238   SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
02239 }
02240
02241 /**
02242   * @brief  Disable Transfer complete interrupt.
02243   * @rmtoll CCR          TCIE          LL_BDMA_DisableIT_TC
02244   * @param  BDMAx BDMA Instance
02245   * @param  Channel This parameter can be one of the following values:
02246   *         @arg @ref LL_BDMA_CHANNEL_0
02247   *         @arg @ref LL_BDMA_CHANNEL_1
02248   *         @arg @ref LL_BDMA_CHANNEL_2
02249   *         @arg @ref LL_BDMA_CHANNEL_3
02250   *         @arg @ref LL_BDMA_CHANNEL_4
02251   *         @arg @ref LL_BDMA_CHANNEL_5
02252   *         @arg @ref LL_BDMA_CHANNEL_6
02253   *         @arg @ref LL_BDMA_CHANNEL_7
02254   * @retval None
02255   */
02256 __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
02257 {
02258   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02259
02260   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
02261 }
02262
02263 /**
02264   * @brief  Disable Half transfer interrupt.
02265   * @rmtoll CCR          HTIE          LL_BDMA_DisableIT_HT
02266   * @param  BDMAx BDMA Instance
02267   * @param  Channel This parameter can be one of the following values:
02268   *         @arg @ref LL_BDMA_CHANNEL_0
02269   *         @arg @ref LL_BDMA_CHANNEL_1
02270   *         @arg @ref LL_BDMA_CHANNEL_2
02271   *         @arg @ref LL_BDMA_CHANNEL_3
02272   *         @arg @ref LL_BDMA_CHANNEL_4
02273   *         @arg @ref LL_BDMA_CHANNEL_5
02274   *         @arg @ref LL_BDMA_CHANNEL_6
02275   *         @arg @ref LL_BDMA_CHANNEL_7
02276   * @retval None
02277   */
02278 __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
02279 {
02280   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02281
02282   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
02283 }
02284
02285 /**
02286   * @brief  Disable Transfer error interrupt.
02287   * @rmtoll CCR          TEIE          LL_BDMA_DisableIT_TE
02288   * @param  BDMAx BDMA Instance
02289   * @param  Channel This parameter can be one of the following values:
02290   *         @arg @ref LL_BDMA_CHANNEL_0
02291   *         @arg @ref LL_BDMA_CHANNEL_1
02292   *         @arg @ref LL_BDMA_CHANNEL_2
02293   *         @arg @ref LL_BDMA_CHANNEL_3
02294   *         @arg @ref LL_BDMA_CHANNEL_4
02295   *         @arg @ref LL_BDMA_CHANNEL_5
02296   *         @arg @ref LL_BDMA_CHANNEL_6
02297   *         @arg @ref LL_BDMA_CHANNEL_7
02298   * @retval None
02299   */
02300 __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
02301 {
02302   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02303
02304   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
02305 }
02306
02307 /**
02308   * @brief  Check if Transfer complete Interrupt is enabled.
02309   * @rmtoll CCR          TCIE          LL_BDMA_IsEnabledIT_TC
02310   * @param  BDMAx BDMA Instance
02311   * @param  Channel This parameter can be one of the following values:
02312   *         @arg @ref LL_BDMA_CHANNEL_0
02313   *         @arg @ref LL_BDMA_CHANNEL_1
02314   *         @arg @ref LL_BDMA_CHANNEL_2
02315   *         @arg @ref LL_BDMA_CHANNEL_3
02316   *         @arg @ref LL_BDMA_CHANNEL_4
02317   *         @arg @ref LL_BDMA_CHANNEL_5
02318   *         @arg @ref LL_BDMA_CHANNEL_6
02319   *         @arg @ref LL_BDMA_CHANNEL_7
02320   * @retval State of bit (1 or 0).
02321   */
02322 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
02323 {
02324   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02325
02326   return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
02327 }
02328
02329 /**
02330   * @brief  Check if Half transfer Interrupt is enabled.
02331   * @rmtoll CCR          HTIE          LL_BDMA_IsEnabledIT_HT
02332   * @param  BDMAx BDMA Instance
02333   * @param  Channel This parameter can be one of the following values:
02334   *         @arg @ref LL_BDMA_CHANNEL_0
02335   *         @arg @ref LL_BDMA_CHANNEL_1
02336   *         @arg @ref LL_BDMA_CHANNEL_2
02337   *         @arg @ref LL_BDMA_CHANNEL_3
02338   *         @arg @ref LL_BDMA_CHANNEL_4
02339   *         @arg @ref LL_BDMA_CHANNEL_5
02340   *         @arg @ref LL_BDMA_CHANNEL_6
02341   *         @arg @ref LL_BDMA_CHANNEL_7
02342   * @retval State of bit (1 or 0).
02343   */
02344 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
02345 {
02346   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02347
02348   return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
02349 }
02350
02351 /**
02352   * @brief  Check if Transfer error Interrupt is enabled.
02353   * @rmtoll CCR          TEIE          LL_BDMA_IsEnabledIT_TE
02354   * @param  BDMAx BDMA Instance
02355   * @param  Channel This parameter can be one of the following values:
02356   *         @arg @ref LL_BDMA_CHANNEL_0
02357   *         @arg @ref LL_BDMA_CHANNEL_1
02358   *         @arg @ref LL_BDMA_CHANNEL_2
02359   *         @arg @ref LL_BDMA_CHANNEL_3
02360   *         @arg @ref LL_BDMA_CHANNEL_4
02361   *         @arg @ref LL_BDMA_CHANNEL_5
02362   *         @arg @ref LL_BDMA_CHANNEL_6
02363   *         @arg @ref LL_BDMA_CHANNEL_7
02364   * @retval State of bit (1 or 0).
02365   */
02366 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
02367 {
02368   register uint32_t bdma_base_addr = (uint32_t)BDMAx;
02369
02370   return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
02371 }
02372
02373 /**
02374   * @}
02375   */
02376
02377 #if defined(USE_FULL_LL_DRIVER)
02378 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions
02379   * @{
02380   */
02381
02382 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
02383 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
02384 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
02385
02386 /**
02387   * @}
02388   */
02389 #endif /* USE_FULL_LL_DRIVER */
02390
02391 /**
02392   * @}
02393   */
02394
02395 /**
02396   * @}
02397   */
02398
02399 #endif /* BDMA || BDMA1 || BDMA2 */
02400
02401 /**
02402   * @}
02403   */
02404
02405 /**
02406   * @}
02407   */
02408
02409 #ifdef __cplusplus
02410 }
02411 #endif
02412
02413 #endif /* STM32H7xx_LL_BDMA_H */
02414
02415 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_bus.h Source File

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stm32h7xx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of BUS LL module.
00008
00009   @verbatim
00010                       ##### RCC Limitations #####
00011   ==============================================================================
00012     [..]
00013       A delay between an RCC peripheral clock enable and the effective peripheral
00014       enabling should be taken into account in order to manage the peripheral read/write
00015       from/to registers.
00016       (+) This delay depends on the peripheral mapping.
00017         (++) AHB & APB peripherals, 1 dummy read is necessary
00018
00019     [..]
00020       Workarounds:
00021       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00022           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00023
00024   @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00029   * All rights reserved.</center></h2>
00030   *
00031   * This software component is licensed by ST under BSD 3-Clause license,
00032   * the "License"; You may not use this file except in compliance with the
00033   * License. You may obtain a copy of the License at:
00034   *                        opensource.org/licenses/BSD-3-Clause
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef STM32H7xx_LL_BUS_H
00041 #define STM32H7xx_LL_BUS_H
00042
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx.h"
00049
00050 /** @addtogroup STM32H7xx_LL_Driver
00051   * @{
00052   */
00053
00054 #if defined(RCC)
00055
00056 /** @defgroup BUS_LL BUS
00057   * @{
00058   */
00059
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063
00064 /* Private macros ------------------------------------------------------------*/
00065
00066 /* Exported types ------------------------------------------------------------*/
00067
00068 /* Exported constants --------------------------------------------------------*/
00069 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00070   * @{
00071   */
00072
00073 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
00074   * @{
00075   */
00076 #define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN
00077 #define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN
00078
00079 #if defined(JPEG)
00080 #define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN
00081 #endif /* JPEG */
00082
00083 #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
00084 #if defined(QUADSPI)
00085 #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
00086 #endif /* QUADSPI */
00087 #if defined(OCTOSPI1) || defined(OCTOSPI2)
00088 #define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN
00089 #define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN
00090 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
00091 #if defined(OCTOSPIM)
00092 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN
00093 #endif /* OCTOSPIM */
00094 #if defined(OTFDEC1) || defined(OTFDEC2)
00095 #define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN
00096 #define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN
00097 #endif /* (OTFDEC1) || (OTFDEC2) */
00098 #if defined(GFXMMU)
00099 #define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN
00100 #endif /* GFXMMU */
00101 #define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN
00102 #define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN
00103 #define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN
00104 #define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN
00105 #define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN
00106 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
00107 #define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN
00108 #else
00109 #define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN
00110 #define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/
00111 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
00112 #if defined(CD_AXISRAM2_BASE)
00113 #define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN
00114 #endif /* CD_AXISRAM2_BASE */
00115 #if defined(CD_AXISRAM3_BASE)
00116 #define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN
00117 #endif /* CD_AXISRAM3_BASE */
00118 /**
00119   * @}
00120   */
00121
00122
00123 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00124   * @{
00125   */
00126 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
00127 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
00128 #define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
00129 #if defined(DUAL_CORE)
00130 #define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN
00131 #endif /* DUAL_CORE */
00132 #if defined(RCC_AHB1ENR_CRCEN)
00133 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
00134 #endif /* RCC_AHB1ENR_CRCEN */
00135 #if defined(ETH)
00136 #define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN
00137 #define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN
00138 #define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN
00139 #endif /* ETH */
00140 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN
00141 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN
00142 #if defined(USB2_OTG_FS)
00143 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN
00144 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN
00145 #endif /* USB2_OTG_FS */
00146 /**
00147   * @}
00148   */
00149
00150
00151 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
00152   * @{
00153   */
00154 #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
00155 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
00156 #define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN
00157 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */
00158 #if defined(CRYP)
00159 #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
00160 #endif /* CRYP */
00161 #if defined(HASH)
00162 #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
00163 #endif /* HASH */
00164 #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
00165 #define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN
00166 #if defined(BDMA1)
00167 #define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN
00168 #endif /* BDMA1 */
00169 #if defined(RCC_AHB2ENR_D2SRAM1EN)
00170 #define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN
00171 #else
00172 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN
00173 #define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/
00174 #endif /* RCC_AHB2ENR_D2SRAM1EN */
00175 #if defined(RCC_AHB2ENR_D2SRAM2EN)
00176 #define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN
00177 #else
00178 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN
00179 #define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/
00180 #endif /* RCC_AHB2ENR_D2SRAM2EN */
00181 #if defined(RCC_AHB2ENR_D2SRAM3EN)
00182 #define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN
00183 #endif /* RCC_AHB2ENR_D2SRAM3EN */
00184 /**
00185   * @}
00186   */
00187
00188
00189 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
00190   * @{
00191   */
00192 #define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
00193 #define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
00194 #define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
00195 #define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
00196 #define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
00197 #define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
00198 #define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
00199 #define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
00200 #define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN
00201 #define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN
00202 #define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN
00203 #if defined(RCC_AHB4ENR_CRCEN)
00204 #define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
00205 #endif /* RCC_AHB4ENR_CRCEN */
00206 #if defined(BDMA2)
00207 #define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN
00208 #define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/
00209 #else
00210 #define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN
00211 #endif /* BDMA2 */
00212 #if defined(ADC3)
00213 #define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN
00214 #endif /* ADC3 */
00215 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
00216 #define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN
00217 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
00218 #define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN
00219 #if defined(RCC_AHB4LPENR_SRAM4LPEN)
00220 #define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN
00221 #define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4
00222 #else
00223 #define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN
00224 #define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
00225 #define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
00226 #endif /* RCC_AHB4ENR_D3SRAM1EN */
00227 /**
00228   * @}
00229   */
00230
00231
00232 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
00233   * @{
00234   */
00235 #define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN
00236 #if defined(DSI)
00237 #define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN
00238 #endif /* DSI */
00239 #define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
00240 #if defined(RCC_APB3ENR_WWDGEN)
00241 #define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
00242 #endif
00243 /**
00244   * @}
00245   */
00246
00247
00248 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00249   * @{
00250   */
00251 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN
00252 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN
00253 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN
00254 #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN
00255 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN
00256 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN
00257 #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN
00258 #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN
00259 #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN
00260 #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN
00261 #if defined(DUAL_CORE)
00262 #define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN
00263 #endif /*DUAL_CORE*/
00264 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN
00265 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN
00266 #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN
00267 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN
00268 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN
00269 #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN
00270 #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN
00271 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN
00272 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN
00273 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN
00274 #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN
00275 #define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN
00276 #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN
00277 #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN
00278 /**
00279   * @}
00280   */
00281
00282
00283 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
00284   * @{
00285   */
00286 #define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN
00287 #define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN
00288 #define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN
00289 #define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN
00290 #define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN
00291 /**
00292   * @}
00293   */
00294
00295
00296 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00297   * @{
00298   */
00299 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00300 #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
00301 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00302 #define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
00303 #if defined(UART9)
00304 #define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
00305 #endif /* UART9 */
00306 #if defined(USART10)
00307 #define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
00308 #endif /* USART10 */
00309 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00310 #define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
00311 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
00312 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00313 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00314 #define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
00315 #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
00316 #define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
00317 #if defined(SAI3)
00318 #define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN
00319 #endif /* SAI3 */
00320 #define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
00321 #if defined(HRTIM1)
00322 #define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN
00323 #endif /* HRTIM1 */
00324 /**
00325   * @}
00326   */
00327
00328
00329 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
00330   * @{
00331   */
00332 #define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN
00333 #define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN
00334 #define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN
00335 #define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN
00336 #define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN
00337 #define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN
00338 #if defined(LPTIM4)
00339 #define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN
00340 #endif /* LPTIM4 */
00341 #if defined(LPTIM5)
00342 #define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN
00343 #endif /* LPTIM5 */
00344 #if defined(DAC2)
00345 #define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN
00346 #endif /* DAC2 */
00347 #define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN
00348 #define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN
00349 #define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN
00350 #if defined(SAI4)
00351 #define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN
00352 #endif /* SAI4 */
00353 #if defined(DTS)
00354 #define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN
00355 #endif /*DTS*/
00356 #if defined(DFSDM2_BASE)
00357 #define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN
00358 #endif /* DFSDM2_BASE */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH
00364   * @{
00365   */
00366 #if defined(RCC_D3AMR_BDMAAMEN)
00367 #define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN
00368 #else
00369 #define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN
00370 #define LL_CLKAM_PERIPH_BDMA          LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
00371 #endif /* RCC_D3AMR_BDMAAMEN */
00372 #if defined(RCC_SRDAMR_GPIOAMEN)
00373 #define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN
00374 #endif /* RCC_SRDAMR_GPIOAMEN */
00375 #if defined(RCC_D3AMR_LPUART1AMEN)
00376 #define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN
00377 #else
00378 #define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN
00379 #endif /* RCC_D3AMR_LPUART1AMEN */
00380 #if defined(RCC_D3AMR_SPI6AMEN)
00381 #define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN
00382 #else
00383 #define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN
00384 #endif /* RCC_D3AMR_SPI6AMEN */
00385 #if defined(RCC_D3AMR_I2C4AMEN)
00386 #define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN
00387 #else
00388 #define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN
00389 #endif /* RCC_D3AMR_I2C4AMEN */
00390 #if defined(RCC_D3AMR_LPTIM2AMEN)
00391 #define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN
00392 #else
00393 #define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN
00394 #endif /* RCC_D3AMR_LPTIM2AMEN */
00395 #if defined(RCC_D3AMR_LPTIM3AMEN)
00396 #define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN
00397 #else
00398 #define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN
00399 #endif /* RCC_D3AMR_LPTIM3AMEN */
00400 #if defined(RCC_D3AMR_LPTIM4AMEN)
00401 #define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN
00402 #endif /* RCC_D3AMR_LPTIM4AMEN */
00403 #if defined(RCC_D3AMR_LPTIM5AMEN)
00404 #define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN
00405 #endif /* RCC_D3AMR_LPTIM5AMEN */
00406 #if defined(DAC2)
00407 #define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN
00408 #endif /* DAC2 */
00409 #if defined(RCC_D3AMR_COMP12AMEN)
00410 #define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN
00411 #else
00412 #define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN
00413 #endif /* RCC_D3AMR_COMP12AMEN */
00414 #if defined(RCC_D3AMR_VREFAMEN)
00415 #define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN
00416 #else
00417 #define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN
00418 #endif /* RCC_D3AMR_VREFAMEN */
00419 #if defined(RCC_D3AMR_RTCAMEN)
00420 #define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN
00421 #else
00422 #define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN
00423 #endif /* RCC_D3AMR_RTCAMEN */
00424 #if defined(RCC_D3AMR_CRCAMEN)
00425 #define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN
00426 #endif /* RCC_D3AMR_CRCAMEN */
00427 #if defined(SAI4)
00428 #define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN
00429 #endif /* SAI4 */
00430 #if defined(ADC3)
00431 #define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN
00432 #endif /* ADC3 */
00433 #if defined(DTS)
00434 #define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN
00435 #endif /* DTS */
00436 #if defined(DFSDM2_BASE)
00437 #define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN
00438 #endif /* DFSDM2_BASE */
00439 #if defined(RCC_D3AMR_BKPRAMAMEN)
00440 #define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN
00441 #else
00442 #define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN
00443 #endif /* RCC_D3AMR_BKPRAMAMEN */
00444 #if defined(RCC_D3AMR_SRAM4AMEN)
00445 #define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN
00446 #else
00447 #define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN
00448 #define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM
00449 #endif /* RCC_D3AMR_SRAM4AMEN */
00450 /**
00451   * @}
00452   */
00453
00454 #if defined(RCC_CKGAENR_AXICKG)
00455 /** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH
00456   * @{
00457   */
00458 #define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG
00459 #define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG
00460 #define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG
00461 #define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG
00462 #define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG
00463 #define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG
00464 #define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG
00465 #define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG
00466 #define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG
00467 #define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG
00468 #define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG
00469 #define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG
00470 #define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG
00471 #define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG
00472 #define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG
00473 #define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG
00474 #define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG
00475 #define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG
00476 #define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG
00477 #define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG
00478 #define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG
00479 /**
00480   * @}
00481   */
00482 #endif /* RCC_CKGAENR_AXICKG */
00483
00484 /* Exported macro ------------------------------------------------------------*/
00485
00486 /* Exported functions --------------------------------------------------------*/
00487
00488 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00489   * @{
00490   */
00491
00492 /** @defgroup BUS_LL_EF_AHB3 AHB3
00493   * @{
00494   */
00495
00496 /**
00497   * @brief  Enable AHB3 peripherals clock.
00498   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n
00499   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n
00500   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n
00501   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
00502   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)
00503   *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)
00504   *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)
00505   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
00506   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
00507   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
00508   *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
00509   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
00510   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
00511   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
00512   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)
00513   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)
00514   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)
00515   * @param  Periphs This parameter can be a combination of the following values:
00516   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
00517   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00518   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00519   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00520   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00521   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
00522   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
00523   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
00524   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
00525   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
00526   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
00527   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00528   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
00529   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
00530   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
00531   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
00532   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
00533   *
00534   *         (*) value not defined in all devices.
00535   * @retval None
00536 */
00537 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
00538 {
00539   __IO uint32_t tmpreg;
00540   SET_BIT(RCC->AHB3ENR, Periphs);
00541   /* Delay after an RCC peripheral clock enabling */
00542   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
00543   (void)tmpreg;
00544 }
00545
00546 /**
00547   * @brief  Check if AHB3 peripheral clock is enabled or not
00548   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n
00549   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n
00550   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n
00551   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
00552   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
00553   *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
00554   *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
00555   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
00556   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
00557   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
00558   *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
00559   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
00560   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
00561   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
00562   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
00563   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
00564   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)
00565   * @param  Periphs This parameter can be a combination of the following values:
00566   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
00567   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00568   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00569   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00570   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
00571   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
00572   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
00573   *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
00574   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
00575   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
00576   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
00577   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00578   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
00579   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
00580   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
00581   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
00582   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
00583   *
00584   *         (*) value not defined in all devices.
00585   * @retval uint32_t
00586 */
00587 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
00588 {
00589   return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
00590 }
00591
00592 /**
00593   * @brief  Disable AHB3 peripherals clock.
00594   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n
00595   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n
00596   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n
00597   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
00598   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)
00599   *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)
00600   *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)
00601   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
00602   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
00603   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
00604   *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
00605   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
00606   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
00607   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
00608   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)
00609   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)
00610   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock
00611   * @param  Periphs This parameter can be a combination of the following values:
00612   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
00613   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00614   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00615   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00616   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
00617   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
00618   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
00619   *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
00620   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
00621   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
00622   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
00623   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00624   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
00625   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
00626   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
00627   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
00628   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
00629   *
00630   *         (*) value not defined in all devices.
00631   * @retval None
00632 */
00633 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
00634 {
00635   CLEAR_BIT(RCC->AHB3ENR, Periphs);
00636 }
00637
00638 /**
00639   * @brief  Force AHB3 peripherals reset.
00640   * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
00641   *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
00642   *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
00643   *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
00644   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
00645   *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
00646   *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
00647   *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)
00648   *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)
00649   *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)
00650   *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)
00651   *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset
00652   * @param  Periphs This parameter can be a combination of the following values:
00653   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
00654   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00655   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00656   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00657   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
00658   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
00659   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
00660   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
00661   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
00662   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
00663   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
00664   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00665   *
00666   *         (*) value not defined in all devices.
00667   * @retval None
00668 */
00669 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
00670 {
00671   SET_BIT(RCC->AHB3RSTR, Periphs);
00672 }
00673
00674 /**
00675   * @brief  Release AHB3 peripherals reset.
00676   * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n
00677   *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n
00678   *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n
00679   *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
00680   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n
00681   *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)
00682   *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)
00683   *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)
00684   *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)
00685   *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)
00686   *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)
00687   *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset
00688   * @param  Periphs This parameter can be a combination of the following values:
00689   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
00690   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00691   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00692   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00693   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
00694   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
00695   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
00696   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
00697   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
00698   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
00699   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
00700   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00701   *
00702   *         (*) value not defined in all devices.
00703   * @retval None
00704 */
00705 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
00706 {
00707   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
00708 }
00709
00710 /**
00711   * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
00712   * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n
00713   *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n
00714   *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n
00715   *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n
00716   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)
00717   *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
00718   *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
00719   *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
00720   *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
00721   *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
00722   *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
00723   *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n
00724   *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n
00725   *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n
00726   *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n
00727   *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n
00728   *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep
00729   * @param  Periphs This parameter can be a combination of the following values:
00730   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00731   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00732   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00733   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
00734   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
00735   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
00736   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
00737   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
00738   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
00739   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
00740   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00741   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00742   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
00743   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
00744   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
00745   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
00746   *
00747   *         (*) value not defined in all devices.
00748   * @retval None
00749 */
00750 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
00751 {
00752   __IO uint32_t tmpreg;
00753   SET_BIT(RCC->AHB3LPENR, Periphs);
00754   /* Delay after an RCC peripheral clock enabling */
00755   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
00756   (void)tmpreg;
00757 }
00758
00759 /**
00760   * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
00761   * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n
00762   *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n
00763   *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n
00764   *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n
00765   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n
00766   *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
00767   *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
00768   *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
00769   *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
00770   *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
00771   *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
00772   *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n
00773   *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n
00774   *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n
00775   *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n
00776   *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n
00777   *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep
00778   * @param  Periphs This parameter can be a combination of the following values:
00779   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
00780   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
00781   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
00782   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
00783   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
00784   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
00785   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
00786   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
00787   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
00788   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
00789   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
00790   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00791   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
00792   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
00793   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
00794   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
00795   *
00796   *         (*) value not defined in all devices.
00797   * @retval None
00798 */
00799 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
00800 {
00801   CLEAR_BIT(RCC->AHB3LPENR, Periphs);
00802 }
00803
00804 /**
00805   * @}
00806   */
00807
00808 /** @defgroup BUS_LL_EF_AHB1 AHB1
00809   * @{
00810   */
00811
00812 /**
00813   * @brief  Enable AHB1 peripherals clock.
00814   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
00815   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
00816   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
00817   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
00818   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
00819   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
00820   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
00821   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n
00822   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n
00823   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)
00824   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)
00825   * @param  Periphs This parameter can be a combination of the following values:
00826   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00827   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00828   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00829   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00830   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00831   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
00832   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
00833   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
00834   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
00835   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
00836   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
00837   *
00838   *         (*) value not defined in all devices.
00839   * @retval None
00840 */
00841 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00842 {
00843   __IO uint32_t tmpreg;
00844   SET_BIT(RCC->AHB1ENR, Periphs);
00845   /* Delay after an RCC peripheral clock enabling */
00846   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
00847   (void)tmpreg;
00848 }
00849
00850 /**
00851   * @brief  Check if AHB1 peripheral clock is enabled or not
00852   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00853   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00854   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
00855   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
00856   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
00857   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)
00858   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
00859   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
00860   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n
00861   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n
00862   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)
00863   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)
00864   * @param  Periphs This parameter can be a combination of the following values:
00865   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00866   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00867   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00868   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00869   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
00870   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00871   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
00872   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
00873   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
00874   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
00875   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
00876   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
00877   *
00878   *         (*) value not defined in all devices.
00879   * @retval uint32_t
00880 */
00881 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00882 {
00883   return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
00884 }
00885
00886 /**
00887   * @brief  Disable AHB1 peripherals clock.
00888   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
00889   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
00890   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
00891   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
00892   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
00893   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
00894   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
00895   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n
00896   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n
00897   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)
00898   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)
00899   * @param  Periphs This parameter can be a combination of the following values:
00900   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00901   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00902   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00903   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00904   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
00905   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00906   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
00907   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
00908   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
00909   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
00910   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
00911   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
00912   *
00913   *         (*) value not defined in all devices.
00914   * @retval None
00915 */
00916 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00917 {
00918   CLEAR_BIT(RCC->AHB1ENR, Periphs);
00919 }
00920
00921 /**
00922   * @brief  Force AHB1 peripherals reset.
00923   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
00924   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
00925   *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n
00926   *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)
00927   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)
00928   *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)
00929   *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n
00930   *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)
00931   * @param  Periphs This parameter can be a combination of the following values:
00932   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00933   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00934   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00935   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00936   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
00937   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00938   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
00939   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
00940   *
00941   *         (*) value not defined in all devices.
00942   * @retval None
00943 */
00944 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00945 {
00946   SET_BIT(RCC->AHB1RSTR, Periphs);
00947 }
00948
00949 /**
00950   * @brief  Release AHB1 peripherals reset.
00951   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
00952   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
00953   *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
00954   *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)
00955   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)
00956   *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)
00957   *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n
00958   *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)
00959   * @param  Periphs This parameter can be a combination of the following values:
00960   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00961   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00962   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00963   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00964   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
00965   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00966   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
00967   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
00968   *
00969   *         (*) value not defined in all devices.
00970   * @retval None
00971 */
00972 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00973 {
00974   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
00975 }
00976
00977 /**
00978   * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
00979   * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
00980   *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
00981   *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n
00982   *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
00983   *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
00984   *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)
00985   *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)
00986   *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n
00987   *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n
00988   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n
00989   *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)
00990   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)
00991   * @param  Periphs This parameter can be a combination of the following values:
00992   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00993   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00994   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
00995   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
00996   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
00997   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
00998   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
00999   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
01000   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
01001   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
01002   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
01003   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
01004   *
01005   *         (*) value not defined in all devices.
01006   * @retval None
01007 */
01008 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
01009 {
01010   __IO uint32_t tmpreg;
01011   SET_BIT(RCC->AHB1LPENR, Periphs);
01012   /* Delay after an RCC peripheral clock enabling */
01013   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
01014   (void)tmpreg;
01015 }
01016
01017 /**
01018   * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
01019   * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
01020   *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
01021   *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n
01022   *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
01023   *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
01024   *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)
01025   *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
01026   *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
01027   *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n
01028   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n
01029   *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)
01030   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)
01031   * @param  Periphs This parameter can be a combination of the following values:
01032   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
01033   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
01034   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
01035   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
01036   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
01037   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
01038   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
01039   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
01040   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
01041   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
01042   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
01043   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
01044   *
01045   *         (*) value not defined in all devices.
01046   * @retval None
01047 */
01048 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
01049 {
01050   CLEAR_BIT(RCC->AHB1LPENR, Periphs);
01051 }
01052
01053 /**
01054   * @}
01055   */
01056
01057 /** @defgroup BUS_LL_EF_AHB2 AHB2
01058   * @{
01059   */
01060
01061 /**
01062   * @brief  Enable AHB2 peripherals clock.
01063   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
01064   *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)
01065   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)
01066   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)
01067   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n
01068   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n
01069   *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)
01070   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n
01071   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n
01072   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)
01073   * @param  Periphs This parameter can be a combination of the following values:
01074   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01075   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
01076   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01077   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01078   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01079   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01080   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
01081   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
01082   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
01083   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
01084   *
01085   *         (*) value not defined in all devices.
01086   * @retval None
01087 */
01088 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
01089 {
01090   __IO uint32_t tmpreg;
01091   SET_BIT(RCC->AHB2ENR, Periphs);
01092   /* Delay after an RCC peripheral clock enabling */
01093   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
01094   (void)tmpreg;
01095 }
01096
01097 /**
01098   * @brief  Check if AHB2 peripheral clock is enabled or not
01099   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
01100   *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
01101   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
01102   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
01103   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n
01104   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n
01105   *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)
01106   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n
01107   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n
01108   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)
01109   * @param  Periphs This parameter can be a combination of the following values:
01110   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01111   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
01112   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01113   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01114   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01115   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01116   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
01117   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
01118   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
01119   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
01120   *
01121   *         (*) value not defined in all devices.
01122   * @retval uint32_t
01123 */
01124 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
01125 {
01126   return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
01127 }
01128
01129 /**
01130   * @brief  Disable AHB2 peripherals clock.
01131   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
01132   *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)
01133   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)
01134   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)
01135   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n
01136   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n
01137   *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)
01138   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n
01139   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n
01140   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)
01141   * @param  Periphs This parameter can be a combination of the following values:
01142   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01143   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
01144   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01145   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01146   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01147   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01148   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
01149   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
01150   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
01151   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
01152   *
01153   *         (*) value not defined in all devices.
01154   * @retval None
01155 */
01156 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
01157 {
01158   CLEAR_BIT(RCC->AHB2ENR, Periphs);
01159 }
01160
01161 /**
01162   * @brief  Force AHB2 peripherals reset.
01163   * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
01164   *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)
01165   *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)
01166   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
01167   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
01168   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
01169   *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
01170   * @param  Periphs This parameter can be a combination of the following values:
01171   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01172   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
01173   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01174   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01175   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01176   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01177   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
01178   *
01179   *         (*) value not defined in all devices.
01180   * @retval None
01181 */
01182 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
01183 {
01184   SET_BIT(RCC->AHB2RSTR, Periphs);
01185 }
01186
01187 /**
01188   * @brief  Release AHB2 peripherals reset.
01189   * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
01190   *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)
01191   *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)
01192   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
01193   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
01194   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
01195   *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
01196   * @param  Periphs This parameter can be a combination of the following values:
01197   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
01198   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01199   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01200   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01201   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01202   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
01203   *
01204   *         (*) value not defined in all devices.
01205   * @retval None
01206 */
01207 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
01208 {
01209   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
01210 }
01211
01212 /**
01213   * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
01214   * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n
01215   *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
01216   *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
01217   *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n
01218   *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n
01219   *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)
01220   *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n
01221   *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n
01222   *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep   (*)
01223   * @param  Periphs This parameter can be a combination of the following values:
01224   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01225   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01226   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01227   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01228   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01229   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
01230   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
01231   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
01232   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
01233   *
01234   *         (*) value not defined in all devices.
01235   * @retval None
01236 */
01237 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
01238 {
01239   __IO uint32_t tmpreg;
01240   SET_BIT(RCC->AHB2LPENR, Periphs);
01241   /* Delay after an RCC peripheral clock enabling */
01242   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
01243   (void)tmpreg;
01244 }
01245
01246 /**
01247   * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
01248   * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n
01249   *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
01250   *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
01251   *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n
01252   *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n
01253   *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)
01254   *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n
01255   *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n
01256   *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)
01257   * @param  Periphs This parameter can be a combination of the following values:
01258   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
01259   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
01260   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
01261   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
01262   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
01263   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
01264   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
01265   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
01266   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
01267   *
01268   *         (*) value not defined in all devices.
01269   * @retval None
01270 */
01271 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
01272 {
01273   CLEAR_BIT(RCC->AHB2LPENR, Periphs);
01274 }
01275
01276 /**
01277   * @}
01278   */
01279
01280 /** @defgroup BUS_LL_EF_AHB4 AHB4
01281   * @{
01282   */
01283
01284 /**
01285   * @brief  Enable AHB4 peripherals clock.
01286   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n
01287   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n
01288   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n
01289   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n
01290   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n
01291   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n
01292   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n
01293   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n
01294   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n
01295   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n
01296   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n
01297   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)
01298   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n
01299   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)
01300   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)
01301   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n
01302   *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock
01303   * @param  Periphs This parameter can be a combination of the following values:
01304   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01305   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01306   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01307   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01308   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01309   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01310   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01311   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01312   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01313   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01314   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01315   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
01316   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01317   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)
01318   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
01319   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
01320   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
01321   *
01322   *         (*) value not defined in all devices.
01323   * @retval None
01324 */
01325 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
01326 {
01327   __IO uint32_t tmpreg;
01328   SET_BIT(RCC->AHB4ENR, Periphs);
01329   /* Delay after an RCC peripheral clock enabling */
01330   tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
01331   (void)tmpreg;
01332 }
01333
01334 /**
01335   * @brief  Check if AHB4 peripheral clock is enabled or not
01336   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
01337   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
01338   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
01339   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
01340   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
01341   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
01342   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
01343   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
01344   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n
01345   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n
01346   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n
01347   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)
01348   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n
01349   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)
01350   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)
01351   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n
01352   *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock
01353   * @param  Periphs This parameter can be a combination of the following values:
01354   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01355   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01356   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01357   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01358   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01359   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01360   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01361   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01362   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01363   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01364   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01365   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01366   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01367   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01368   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
01369   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
01370   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
01371   *
01372   *         (*) value not defined in all devices.
01373   * @retval uint32_t
01374 */
01375 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
01376 {
01377   return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
01378 }
01379
01380 /**
01381   * @brief  Disable AHB4 peripherals clock.
01382   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n
01383   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n
01384   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n
01385   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n
01386   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n
01387   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n
01388   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n
01389   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n
01390   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n
01391   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n
01392   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n
01393   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)
01394   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n
01395   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)
01396   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)
01397   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n
01398   *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock
01399   * @param  Periphs This parameter can be a combination of the following values:
01400   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01401   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01402   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01403   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01404   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01405   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01406   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01407   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01408   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01409   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01410   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01411   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01412   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01413   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01414   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
01415   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
01416   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
01417   *
01418   *         (*) value not defined in all devices.
01419   * @retval None
01420 */
01421 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
01422 {
01423   CLEAR_BIT(RCC->AHB4ENR, Periphs);
01424 }
01425
01426 /**
01427   * @brief  Force AHB4 peripherals reset.
01428   * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n
01429   *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n
01430   *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n
01431   *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n
01432   *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n
01433   *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n
01434   *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n
01435   *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n
01436   *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n
01437   *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n
01438   *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n
01439   *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)
01440   *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n
01441   *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)
01442   *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)
01443   * @param  Periphs This parameter can be a combination of the following values:
01444   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01445   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01446   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01447   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01448   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01449   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01450   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01451   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01452   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01453   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01454   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01455   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01456   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01457   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01458   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
01459   *
01460   *         (*) value not defined in all devices.
01461   * @retval None
01462 */
01463 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
01464 {
01465   SET_BIT(RCC->AHB4RSTR, Periphs);
01466 }
01467
01468 /**
01469   * @brief  Release AHB4 peripherals reset.
01470   * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n
01471   *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n
01472   *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n
01473   *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n
01474   *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n
01475   *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n
01476   *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n
01477   *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n
01478   *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n
01479   *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n
01480   *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n
01481   *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)
01482   *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n
01483   *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)
01484   *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)
01485   * @param  Periphs This parameter can be a combination of the following values:
01486   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01487   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01488   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01489   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01490   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01491   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01492   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01493   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01494   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01495   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01496   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01497   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01498   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01499   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01500   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
01501   *
01502   *         (*) value not defined in all devices.
01503   * @retval None
01504 */
01505 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
01506 {
01507   CLEAR_BIT(RCC->AHB4RSTR, Periphs);
01508 }
01509
01510 /**
01511   * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.
01512   * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n
01513   *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01514   *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01515   *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01516   *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n
01517   *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01518   *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01519   *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01520   *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n
01521   *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01522   *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n
01523   *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)
01524   *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n
01525   *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)
01526   *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n
01527   *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep
01528   * @param  Periphs This parameter can be a combination of the following values:
01529   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01530   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01531   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01532   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01533   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01534   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01535   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01536   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01537   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01538   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01539   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01540   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01541   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01542   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01543   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
01544   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
01545   * @retval None
01546 */
01547 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
01548 {
01549   __IO uint32_t tmpreg;
01550   SET_BIT(RCC->AHB4LPENR, Periphs);
01551   /* Delay after an RCC peripheral clock enabling */
01552   tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
01553   (void)tmpreg;
01554 }
01555
01556 /**
01557   * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.
01558   * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n
01559   *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01560   *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01561   *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01562   *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n
01563   *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01564   *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01565   *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01566   *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n
01567   *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01568   *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n
01569   *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)
01570   *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n
01571   *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)
01572   *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n
01573   *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep
01574   * @param  Periphs This parameter can be a combination of the following values:
01575   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
01576   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
01577   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
01578   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
01579   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
01580   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
01581   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
01582   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
01583   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
01584   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
01585   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
01586   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
01587   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
01588   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
01589   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
01590   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
01591   * @retval None
01592 */
01593 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
01594 {
01595   CLEAR_BIT(RCC->AHB4LPENR, Periphs);
01596 }
01597
01598 /**
01599   * @}
01600   */
01601
01602 /** @defgroup BUS_LL_EF_APB3 APB3
01603   * @{
01604   */
01605
01606 /**
01607   * @brief  Enable APB3 peripherals clock.
01608   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)
01609   *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)
01610   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock
01611   * @param  Periphs This parameter can be a combination of the following values:
01612   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01613   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01614   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
01615   *
01616   *         (*) value not defined in all devices.
01617   * @retval None
01618 */
01619 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
01620 {
01621   __IO uint32_t tmpreg;
01622   SET_BIT(RCC->APB3ENR, Periphs);
01623   /* Delay after an RCC peripheral clock enabling */
01624   tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
01625   (void)tmpreg;
01626 }
01627
01628 /**
01629   * @brief  Check if APB3 peripheral clock is enabled or not
01630   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)
01631   *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)
01632   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock
01633   * @param  Periphs This parameter can be a combination of the following values:
01634   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01635   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01636   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
01637   *
01638   *         (*) value not defined in all devices.
01639   * @retval uint32_t
01640 */
01641 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
01642 {
01643   return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
01644 }
01645
01646 /**
01647   * @brief  Disable APB3 peripherals clock.
01648   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n
01649   *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n
01650   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock
01651   * @param  Periphs This parameter can be a combination of the following values:
01652   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01653   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01654   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
01655   *
01656   *         (*) value not defined in all devices.
01657   * @retval None
01658 */
01659 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
01660 {
01661   CLEAR_BIT(RCC->APB3ENR, Periphs);
01662 }
01663
01664 /**
01665   * @brief  Force APB3 peripherals reset.
01666   * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)
01667   *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)
01668   * @param  Periphs This parameter can be a combination of the following values:
01669   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01670   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01671   *
01672   *         (*) value not defined in all devices.
01673   * @retval None
01674 */
01675 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
01676 {
01677   SET_BIT(RCC->APB3RSTR, Periphs);
01678 }
01679
01680 /**
01681   * @brief  Release APB3 peripherals reset.
01682   * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n
01683   *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset
01684   * @param  Periphs This parameter can be a combination of the following values:
01685   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01686   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01687   *
01688   *         (*) value not defined in all devices.
01689   * @retval None
01690 */
01691 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
01692 {
01693   CLEAR_BIT(RCC->APB3RSTR, Periphs);
01694 }
01695
01696 /**
01697   * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.
01698   * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)
01699   *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)
01700   *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep
01701   * @param  Periphs This parameter can be a combination of the following values:
01702   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01703   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01704   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
01705   *
01706   *         (*) value not defined in all devices.
01707   * @retval None
01708 */
01709 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
01710 {
01711   __IO uint32_t tmpreg;
01712   SET_BIT(RCC->APB3LPENR, Periphs);
01713   /* Delay after an RCC peripheral clock enabling */
01714   tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
01715   (void)tmpreg;
01716 }
01717
01718 /**
01719   * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.
01720   * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)
01721   *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)
01722   *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep
01723   * @param  Periphs This parameter can be a combination of the following values:
01724   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
01725   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
01726   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
01727   *
01728   *         (*) value not defined in all devices.
01729   * @retval None
01730 */
01731 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
01732 {
01733   CLEAR_BIT(RCC->APB3LPENR, Periphs);
01734 }
01735
01736 /**
01737   * @}
01738   */
01739
01740 /** @defgroup BUS_LL_EF_APB1 APB1
01741   * @{
01742   */
01743
01744 /**
01745   * @brief  Enable APB1 peripherals clock.
01746   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
01747   *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
01748   *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
01749   *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
01750   *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
01751   *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
01752   *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
01753   *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
01754   *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
01755   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
01756   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)
01757   *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
01758   *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
01759   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
01760   *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n
01761   *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n
01762   *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n
01763   *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n
01764   *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
01765   *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
01766   *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
01767   *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n
01768   *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n
01769   *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n
01770   *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock
01771   * @param  Periphs This parameter can be a combination of the following values:
01772   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01773   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01774   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01775   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
01776   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01777   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01778   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
01779   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
01780   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
01781   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01782   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
01783   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01784   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01785   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
01786   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01787   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01788   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
01789   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
01790   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01791   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01792   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01793   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
01794   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
01795   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
01796   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
01797   *
01798   *         (*) value not defined in all devices.
01799   * @retval None
01800 */
01801 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
01802 {
01803   __IO uint32_t tmpreg;
01804   SET_BIT(RCC->APB1LENR, Periphs);
01805   /* Delay after an RCC peripheral clock enabling */
01806   tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
01807   (void)tmpreg;
01808 }
01809
01810 /**
01811   * @brief  Check if APB1 peripheral clock is enabled or not
01812   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
01813   *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
01814   *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
01815   *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
01816   *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
01817   *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
01818   *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
01819   *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
01820   *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
01821   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
01822   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)
01823   *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
01824   *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
01825   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
01826   *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
01827   *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
01828   *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
01829   *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
01830   *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
01831   *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
01832   *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
01833   *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
01834   *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n
01835   *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
01836   *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock
01837   * @param  Periphs This parameter can be a combination of the following values:
01838   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01839   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01840   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01841   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
01842   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01843   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01844   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
01845   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
01846   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
01847   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01848   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
01849   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01850   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01851   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
01852   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01853   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01854   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
01855   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
01856   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01857   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01858   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01859   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
01860   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
01861   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
01862   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
01863   *
01864   *         (*) value not defined in all devices.
01865   * @retval uint32_t
01866 */
01867 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
01868 {
01869   return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
01870 }
01871
01872 /**
01873   * @brief  Disable APB1 peripherals clock.
01874   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
01875   *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
01876   *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
01877   *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
01878   *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
01879   *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
01880   *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
01881   *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
01882   *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
01883   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
01884   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)
01885   *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
01886   *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
01887   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
01888   *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n
01889   *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n
01890   *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n
01891   *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n
01892   *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
01893   *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
01894   *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
01895   *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n
01896   *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n
01897   *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n
01898   *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock
01899   * @param  Periphs This parameter can be a combination of the following values:
01900   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01901   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01902   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01903   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
01904   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01905   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01906   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
01907   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
01908   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
01909   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01910   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
01911   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01912   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01913   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
01914   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01915   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01916   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
01917   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
01918   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01919   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01920   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01921   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
01922   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
01923   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
01924   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
01925   *
01926   *         (*) value not defined in all devices.
01927   * @retval None
01928 */
01929 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
01930 {
01931   CLEAR_BIT(RCC->APB1LENR, Periphs);
01932 }
01933
01934 /**
01935   * @brief  Force APB1 peripherals reset.
01936   * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n
01937   *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n
01938   *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n
01939   *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n
01940   *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n
01941   *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n
01942   *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n
01943   *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n
01944   *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n
01945   *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n
01946   *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n
01947   *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n
01948   *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n
01949   *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n
01950   *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n
01951   *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n
01952   *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n
01953   *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n
01954   *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n
01955   *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n
01956   *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n
01957   *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n
01958   *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n
01959   *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset
01960   * @param  Periphs This parameter can be a combination of the following values:
01961   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01962   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01963   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01964   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
01965   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01966   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01967   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
01968   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
01969   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
01970   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01971   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01972   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01973   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
01974   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01975   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01976   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
01977   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
01978   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01979   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01980   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01981   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
01982   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
01983   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
01984   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
01985   * @retval None
01986 */
01987 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
01988 {
01989   SET_BIT(RCC->APB1LRSTR, Periphs);
01990 }
01991
01992 /**
01993   * @brief  Release APB1 peripherals reset.
01994   * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
01995   *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
01996   *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
01997   *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
01998   *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
01999   *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
02000   *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n
02001   *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n
02002   *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n
02003   *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n
02004   *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
02005   *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
02006   *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n
02007   *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n
02008   *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n
02009   *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n
02010   *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n
02011   *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
02012   *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
02013   *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
02014   *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n
02015   *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n
02016   *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n
02017   *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset
02018   * @param  Periphs This parameter can be a combination of the following values:
02019   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
02020   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
02021   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
02022   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
02023   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
02024   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
02025   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
02026   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
02027   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
02028   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
02029   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
02030   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
02031   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
02032   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
02033   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
02034   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
02035   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
02036   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
02037   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
02038   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
02039   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
02040   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
02041   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
02042   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
02043   * @retval None
02044 */
02045 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
02046 {
02047   CLEAR_BIT(RCC->APB1LRSTR, Periphs);
02048 }
02049
02050 /**
02051   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
02052   * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
02053   *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
02054   *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
02055   *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
02056   *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
02057   *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
02058   *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n
02059   *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n
02060   *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n
02061   *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n
02062   *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)
02063   *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
02064   *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
02065   *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n
02066   *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
02067   *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
02068   *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
02069   *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
02070   *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
02071   *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
02072   *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n
02073   *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n
02074   *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n
02075   *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n
02076   *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep
02077   * @param  Periphs This parameter can be a combination of the following values:
02078   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
02079   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
02080   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
02081   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
02082   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
02083   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
02084   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
02085   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
02086   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
02087   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
02088   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
02089   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
02090   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
02091   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
02092   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
02093   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
02094   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
02095   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
02096   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
02097   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
02098   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
02099   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
02100   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
02101   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
02102   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
02103   *
02104   *         (*) value not defined in all devices.
02105   * @retval None
02106 */
02107 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
02108 {
02109   __IO uint32_t tmpreg;
02110   SET_BIT(RCC->APB1LLPENR, Periphs);
02111   /* Delay after an RCC peripheral clock enabling */
02112   tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
02113   (void)tmpreg;
02114 }
02115
02116 /**
02117   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
02118   * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
02119   *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
02120   *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
02121   *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
02122   *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
02123   *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
02124   *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n
02125   *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n
02126   *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n
02127   *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n
02128   *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)
02129   *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
02130   *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
02131   *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n
02132   *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
02133   *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
02134   *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
02135   *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
02136   *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
02137   *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
02138   *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n
02139   *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n
02140   *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n
02141   *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n
02142   *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep
02143   * @param  Periphs This parameter can be a combination of the following values:
02144   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
02145   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
02146   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
02147   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
02148   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
02149   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
02150   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
02151   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
02152   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
02153   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
02154   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
02155   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
02156   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
02157   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
02158   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
02159   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
02160   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
02161   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
02162   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
02163   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
02164   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
02165   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
02166   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
02167   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
02168   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
02169   *
02170   *         (*) value not defined in all devices.
02171   * @retval None
02172 */
02173 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
02174 {
02175   CLEAR_BIT(RCC->APB1LLPENR, Periphs);
02176 }
02177
02178 /**
02179   * @brief  Enable APB1 peripherals clock.
02180   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n
02181   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n
02182   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n
02183   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n
02184   *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock
02185   * @param  Periphs This parameter can be a combination of the following values:
02186   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02187   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02188   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02189   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02190   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02191   * @retval None
02192 */
02193 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
02194 {
02195   __IO uint32_t tmpreg;
02196   SET_BIT(RCC->APB1HENR, Periphs);
02197   /* Delay after an RCC peripheral clock enabling */
02198   tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
02199   (void)tmpreg;
02200 }
02201
02202 /**
02203   * @brief  Check if APB1 peripheral clock is enabled or not
02204   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n
02205   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n
02206   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n
02207   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
02208   *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock
02209   * @param  Periphs This parameter can be a combination of the following values:
02210   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02211   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02212   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02213   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02214   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02215   * @retval uint32_t
02216 */
02217 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
02218 {
02219   return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
02220 }
02221
02222 /**
02223   * @brief  Disable APB1 peripherals clock.
02224   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n
02225   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n
02226   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n
02227   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n
02228   *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock
02229   * @param  Periphs This parameter can be a combination of the following values:
02230   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02231   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02232   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02233   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02234   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02235   * @retval None
02236 */
02237 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
02238 {
02239   CLEAR_BIT(RCC->APB1HENR, Periphs);
02240 }
02241
02242 /**
02243   * @brief  Force APB1 peripherals reset.
02244   * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n
02245   *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n
02246   *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n
02247   *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n
02248   *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset
02249   * @param  Periphs This parameter can be a combination of the following values:
02250   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02251   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02252   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02253   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02254   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02255   * @retval None
02256 */
02257 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
02258 {
02259   SET_BIT(RCC->APB1HRSTR, Periphs);
02260 }
02261
02262 /**
02263   * @brief  Release APB1 peripherals reset.
02264   * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n
02265   *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n
02266   *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n
02267   *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n
02268   *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset
02269   * @param  Periphs This parameter can be a combination of the following values:
02270   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02271   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02272   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02273   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02274   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02275   * @retval None
02276 */
02277 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
02278 {
02279   CLEAR_BIT(RCC->APB1HRSTR, Periphs);
02280 }
02281
02282 /**
02283   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
02284   * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n
02285   *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n
02286   *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n
02287   *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n
02288   *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep
02289   * @param  Periphs This parameter can be a combination of the following values:
02290   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02291   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02292   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02293   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02294   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02295   * @retval None
02296 */
02297 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
02298 {
02299   __IO uint32_t tmpreg;
02300   SET_BIT(RCC->APB1HLPENR, Periphs);
02301   /* Delay after an RCC peripheral clock enabling */
02302   tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
02303   (void)tmpreg;
02304 }
02305
02306 /**
02307   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
02308   * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n
02309   *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n
02310   *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n
02311   *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n
02312   *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep
02313   * @param  Periphs This parameter can be a combination of the following values:
02314   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
02315   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
02316   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
02317   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
02318   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
02319   * @retval None
02320 */
02321 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
02322 {
02323   CLEAR_BIT(RCC->APB1HLPENR, Periphs);
02324 }
02325
02326 /**
02327   * @}
02328   */
02329
02330 /** @defgroup BUS_LL_EF_APB2 APB2
02331   * @{
02332   */
02333
02334 /**
02335   * @brief  Enable APB2 peripherals clock.
02336   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
02337   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
02338   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
02339   *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n
02340   *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)
02341   *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)
02342   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
02343   *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
02344   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
02345   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
02346   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
02347   *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n
02348   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
02349   *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
02350   *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)
02351   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n
02352   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)
02353   * @param  Periphs This parameter can be a combination of the following values:
02354   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02355   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02356   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02357   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02358   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02359   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02360   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02361   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02362   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02363   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02364   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02365   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02366   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02367   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02368   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
02369   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02370   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
02371   *
02372   *         (*) value not defined in all devices.
02373   * @retval None
02374 */
02375 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
02376 {
02377   __IO uint32_t tmpreg;
02378   SET_BIT(RCC->APB2ENR, Periphs);
02379   /* Delay after an RCC peripheral clock enabling */
02380   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
02381   (void)tmpreg;
02382 }
02383
02384 /**
02385   * @brief  Check if APB2 peripheral clock is enabled or not
02386   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
02387   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
02388   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
02389   *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
02390   *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)
02391   *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)
02392   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
02393   *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
02394   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
02395   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
02396   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
02397   *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
02398   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
02399   *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
02400   *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n
02401   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
02402   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock
02403   * @param  Periphs This parameter can be a combination of the following values:
02404   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02405   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02406   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02407   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02408   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02409   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02410   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02411   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02412   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02413   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02414   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02415   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02416   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02417   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02418   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
02419   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02420   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
02421   *
02422   *         (*) value not defined in all devices.
02423   * @retval uint32_t
02424 */
02425 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
02426 {
02427   return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
02428 }
02429
02430 /**
02431   * @brief  Disable APB2 peripherals clock.
02432   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
02433   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
02434   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
02435   *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n
02436   *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)
02437   *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)
02438   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
02439   *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
02440   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
02441   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
02442   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
02443   *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n
02444   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
02445   *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
02446   *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)
02447   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n
02448   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)
02449   * @param  Periphs This parameter can be a combination of the following values:
02450   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02451   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02452   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02453   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02454   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02455   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02456   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02457   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02458   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02459   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02460   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02461   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02462   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02463   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02464   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
02465   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02466   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
02467   *
02468   *         (*) value not defined in all devices.
02469   * @retval None
02470 */
02471 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
02472 {
02473   CLEAR_BIT(RCC->APB2ENR, Periphs);
02474 }
02475
02476 /**
02477   * @brief  Force APB2 peripherals reset.
02478   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
02479   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
02480   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
02481   *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n
02482   *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)
02483   *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)
02484   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
02485   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
02486   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
02487   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
02488   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
02489   *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n
02490   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
02491   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
02492   *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)
02493   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n
02494   *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)
02495   * @param  Periphs This parameter can be a combination of the following values:
02496   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02497   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02498   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02499   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02500   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02501   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02502   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02503   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02504   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02505   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02506   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02507   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02508   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02509   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02510   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
02511   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02512   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
02513   *
02514   *         (*) value not defined in all devices.
02515   * @retval None
02516 */
02517 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
02518 {
02519   SET_BIT(RCC->APB2RSTR, Periphs);
02520 }
02521
02522 /**
02523   * @brief  Release APB2 peripherals reset.
02524   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
02525   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
02526   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
02527   *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n
02528   *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)
02529   *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)
02530   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
02531   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
02532   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
02533   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
02534   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
02535   *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n
02536   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
02537   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
02538   *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)
02539   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n
02540   *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)
02541   * @param  Periphs This parameter can be a combination of the following values:
02542   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02543   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02544   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02545   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02546   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02547   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02548   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02549   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02550   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02551   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02552   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02553   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02554   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02555   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02556   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
02557   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02558   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
02559   *
02560   *         (*) value not defined in all devices.
02561   * @retval None
02562 */
02563 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
02564 {
02565   CLEAR_BIT(RCC->APB2RSTR, Periphs);
02566 }
02567
02568 /**
02569   * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
02570   * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n
02571   *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n
02572   *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n
02573   *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n
02574   *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)
02575   *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)
02576   *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
02577   *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n
02578   *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n
02579   *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n
02580   *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n
02581   *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n
02582   *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
02583   *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n
02584   *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)
02585   *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n
02586   *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)
02587   * @param  Periphs This parameter can be a combination of the following values:
02588   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02589   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02590   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02591   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02592   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02593   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02594   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02595   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02596   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02597   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02598   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02599   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02600   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02601   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02602   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
02603   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02604   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
02605   * @retval None
02606 */
02607 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
02608 {
02609   __IO uint32_t tmpreg;
02610   SET_BIT(RCC->APB2LPENR, Periphs);
02611   /* Delay after an RCC peripheral clock enabling */
02612   tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
02613   (void)tmpreg;
02614 }
02615
02616 /**
02617   * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
02618   * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n
02619   *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n
02620   *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n
02621   *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n
02622   *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)
02623   *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)
02624   *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
02625   *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n
02626   *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n
02627   *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n
02628   *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n
02629   *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n
02630   *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
02631   *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n
02632   *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)
02633   *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n
02634   *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)
02635   * @param  Periphs This parameter can be a combination of the following values:
02636   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
02637   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
02638   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
02639   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
02640   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
02641   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
02642   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
02643   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
02644   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
02645   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
02646   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
02647   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
02648   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
02649   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
02650   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
02651   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
02652   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
02653   * @retval None
02654 */
02655 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
02656 {
02657   CLEAR_BIT(RCC->APB2LPENR, Periphs);
02658 }
02659
02660 /**
02661   * @}
02662   */
02663
02664 /** @defgroup BUS_LL_EF_APB4 APB4
02665   * @{
02666   */
02667
02668 /**
02669   * @brief  Enable APB4 peripherals clock.
02670   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n
02671   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n
02672   *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n
02673   *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n
02674   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n
02675   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n
02676   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)
02677   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)
02678   *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)
02679   *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n
02680   *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n
02681   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n
02682   *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)
02683   *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)
02684   *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)
02685   * @param  Periphs This parameter can be a combination of the following values:
02686   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02687   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02688   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02689   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02690   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02691   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02692   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02693   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02694   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02695   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02696   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02697   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
02698   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02699   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02700   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02701   *
02702   *         (*) value not defined in all devices.
02703   * @retval None
02704 */
02705 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
02706 {
02707   __IO uint32_t tmpreg;
02708   SET_BIT(RCC->APB4ENR, Periphs);
02709   /* Delay after an RCC peripheral clock enabling */
02710   tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
02711   (void)tmpreg;
02712 }
02713
02714 /**
02715   * @brief  Check if APB4 peripheral clock is enabled or not
02716   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n
02717   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
02718   *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
02719   *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
02720   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
02721   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
02722   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)
02723   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)
02724   *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)
02725   *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n
02726   *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n
02727   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n
02728   *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)
02729   *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)
02730   *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)
02731   * @param  Periphs This parameter can be a combination of the following values:
02732   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02733   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02734   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02735   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02736   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02737   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02738   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02739   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02740   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02741   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02742   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02743   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
02744   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02745   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02746   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02747   *
02748   *         (*) value not defined in all devices.
02749   * @retval uint32_t
02750 */
02751 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
02752 {
02753   return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
02754 }
02755
02756 /**
02757   * @brief  Disable APB4 peripherals clock.
02758   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n
02759   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n
02760   *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n
02761   *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n
02762   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n
02763   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n
02764   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)
02765   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)
02766   *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)
02767   *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n
02768   *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n
02769   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n
02770   *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)
02771   *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)
02772   *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)
02773   * @param  Periphs This parameter can be a combination of the following values:
02774   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02775   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02776   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02777   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02778   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02779   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02780   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02781   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02782   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02783   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02784   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02785   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
02786   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02787   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02788   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02789   *
02790   *         (*) value not defined in all devices.
02791   * @retval None
02792 */
02793 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
02794 {
02795   CLEAR_BIT(RCC->APB4ENR, Periphs);
02796 }
02797
02798 /**
02799   * @brief  Force APB4 peripherals reset.
02800   * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n
02801   *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n
02802   *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n
02803   *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n
02804   *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n
02805   *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n
02806   *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)
02807   *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)
02808   *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)
02809   *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n
02810   *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n
02811   *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)
02812   *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)
02813   *         APB4RSTR      DFSDM2RST    LL_APB4_GRP1_ForceReset    (*)
02814   * @param  Periphs This parameter can be a combination of the following values:
02815   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02816   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02817   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02818   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02819   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02820   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02821   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02822   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02823   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02824   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02825   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02826   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02827   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02828   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02829   *
02830   *         (*) value not defined in all devices.
02831   * @retval None
02832 */
02833 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
02834 {
02835   SET_BIT(RCC->APB4RSTR, Periphs);
02836 }
02837
02838 /**
02839   * @brief  Release APB4 peripherals reset.
02840   * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n
02841   *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n
02842   *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n
02843   *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n
02844   *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n
02845   *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n
02846   *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)
02847   *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)
02848   *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)
02849   *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n
02850   *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n
02851   *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n
02852   *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)
02853   *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)
02854   * @param  Periphs This parameter can be a combination of the following values:
02855   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02856   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02857   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02858   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02859   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02860   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02861   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02862   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02863   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02864   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02865   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02866   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02867   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02868   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02869   *
02870   *         (*) value not defined in all devices.
02871   * @retval None
02872 */
02873 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
02874 {
02875   CLEAR_BIT(RCC->APB4RSTR, Periphs);
02876 }
02877
02878 /**
02879   * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.
02880   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n
02881   *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n
02882   *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n
02883   *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n
02884   *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n
02885   *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n
02886   *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
02887   *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
02888   *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
02889   *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n
02890   *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n
02891   *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n
02892   *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
02893   *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)
02894   *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)
02895   * @param  Periphs This parameter can be a combination of the following values:
02896   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02897   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02898   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02899   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02900   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02901   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02902   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02903   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02904   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02905   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02906   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02907   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
02908   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02909   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02910   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02911   *
02912   *         (*) value not defined in all devices.
02913   * @retval None
02914 */
02915 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
02916 {
02917   __IO uint32_t tmpreg;
02918   SET_BIT(RCC->APB4LPENR, Periphs);
02919   /* Delay after an RCC peripheral clock enabling */
02920   tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
02921   (void)tmpreg;
02922 }
02923
02924 /**
02925   * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.
02926   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n
02927   *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n
02928   *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n
02929   *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n
02930   *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n
02931   *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n
02932   *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
02933   *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
02934   *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
02935   *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n
02936   *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n
02937   *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n
02938   *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
02939   *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)
02940   *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)
02941   * @param  Periphs This parameter can be a combination of the following values:
02942   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
02943   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
02944   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
02945   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
02946   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
02947   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
02948   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
02949   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
02950   *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
02951   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
02952   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
02953   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
02954   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
02955   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
02956   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
02957   *
02958   *         (*) value not defined in all devices.
02959   * @retval None
02960 */
02961 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
02962 {
02963   CLEAR_BIT(RCC->APB4LPENR, Periphs);
02964 }
02965
02966 /**
02967   * @}
02968   */
02969
02970 /** @defgroup BUS_LL_EF_CLKAM
02971   * @{
02972   */
02973
02974 /**
02975   * @brief  Enable peripherals clock for CLKAM Mode.
02976   * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n
02977   *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n
02978   *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n
02979   *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n
02980   *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n
02981   *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n
02982   *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)
02983   *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)
02984   *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)
02985   *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n
02986   *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n
02987   *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n
02988   *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n
02989   *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)
02990   *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)
02991   *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)
02992   *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)
02993   *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n
02994   *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable
02995   * @param  Periphs This parameter can be a combination of the following values:
02996   *         @arg @ref LL_CLKAM_PERIPH_BDMA
02997   *         @arg @ref LL_CLKAM_PERIPH_LPUART1
02998   *         @arg @ref LL_CLKAM_PERIPH_SPI6
02999   *         @arg @ref LL_CLKAM_PERIPH_I2C4
03000   *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
03001   *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
03002   *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
03003   *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
03004   *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
03005   *         @arg @ref LL_CLKAM_PERIPH_COMP12
03006   *         @arg @ref LL_CLKAM_PERIPH_VREF
03007   *         @arg @ref LL_CLKAM_PERIPH_RTC
03008   *         @arg @ref LL_CLKAM_PERIPH_CRC
03009   *         @arg @ref LL_CLKAM_PERIPH_SAI4   (*)
03010   *         @arg @ref LL_CLKAM_PERIPH_ADC3   (*)
03011   *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
03012   *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
03013   *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
03014   *         @arg @ref LL_CLKAM_PERIPH_SRAM4
03015   *
03016   *         (*) value not defined in all devices.
03017   * @retval None
03018 */
03019 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
03020 {
03021   __IO uint32_t tmpreg;
03022
03023 #if defined(RCC_D3AMR_BDMAAMEN)
03024   SET_BIT(RCC->D3AMR, Periphs);
03025   /* Delay after an RCC peripheral clock enabling */
03026   tmpreg = READ_BIT(RCC->D3AMR, Periphs);
03027 #else
03028   SET_BIT(RCC->SRDAMR, Periphs);
03029   /* Delay after an RCC peripheral clock enabling */
03030   tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
03031 #endif /* RCC_D3AMR_BDMAAMEN */
03032   (void)tmpreg;
03033 }
03034
03035 /**
03036   * @brief  Disable peripherals clock for CLKAM Mode.
03037   * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n
03038   *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n
03039   *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n
03040   *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n
03041   *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n
03042   *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n
03043   *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)
03044   *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)
03045   *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)
03046   *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n
03047   *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n
03048   *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n
03049   *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n
03050   *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)
03051   *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)
03052   *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)
03053   *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)
03054   *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n
03055   *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable
03056   * @param  Periphs This parameter can be a combination of the following values:
03057   *         @arg @ref LL_CLKAM_PERIPH_BDMA
03058   *         @arg @ref LL_CLKAM_PERIPH_LPUART1
03059   *         @arg @ref LL_CLKAM_PERIPH_SPI6
03060   *         @arg @ref LL_CLKAM_PERIPH_I2C4
03061   *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
03062   *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
03063   *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
03064   *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
03065   *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
03066   *         @arg @ref LL_CLKAM_PERIPH_COMP12
03067   *         @arg @ref LL_CLKAM_PERIPH_VREF
03068   *         @arg @ref LL_CLKAM_PERIPH_RTC
03069   *         @arg @ref LL_CLKAM_PERIPH_CRC
03070   *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
03071   *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
03072   *         @arg @ref LL_CLKAM_PERIPH_DTS  (*)
03073   *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)
03074   *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
03075   *         @arg @ref LL_CLKAM_PERIPH_SRAM4
03076   *
03077   *         (*) value not defined in all devices.
03078   * @retval None
03079 */
03080 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
03081 {
03082 #if defined(RCC_D3AMR_BDMAAMEN)
03083   CLEAR_BIT(RCC->D3AMR, Periphs);
03084 #else
03085   CLEAR_BIT(RCC->SRDAMR, Periphs);
03086 #endif /* RCC_D3AMR_BDMAAMEN */
03087 }
03088
03089 #if defined(RCC_CKGAENR_AXICKG)
03090 /**
03091   * @}
03092   */
03093
03094 /**
03095   * @brief  Enable clock gating for AXI bus peripherals.
03096   * @rmtoll
03097   * @param :
03098   * @retval None
03099 */
03100 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
03101 {
03102   __IO uint32_t tmpreg;
03103   SET_BIT(RCC->CKGAENR, Periphs);
03104   /* Delay after an RCC peripheral clock enabling */
03105   tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
03106   (void)tmpreg;
03107 }
03108 /**
03109   * @}
03110   */
03111 #endif /* RCC_CKGAENR_AXICKG */
03112
03113 #if defined(RCC_CKGAENR_AXICKG)
03114 /**
03115   * @}
03116   */
03117
03118 /**
03119   * @brief  Disable  clock gating for AXI bus peripherals.
03120   * @rmtoll
03121   * @param :
03122   * @retval None
03123 */
03124 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
03125 {
03126   CLEAR_BIT(RCC->CKGAENR, Periphs);
03127 }
03128 /**
03129   * @}
03130   */
03131 #endif /* RCC_CKGAENR_AXICKG */
03132
03133
03134 #if defined(DUAL_CORE)
03135 /** @defgroup BUS_LL_EF_AHB3 AHB3
03136   * @{
03137   */
03138
03139 /**
03140   * @brief  Enable C1 AHB3 peripherals clock.
03141   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n
03142   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n
03143   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n
03144   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n
03145   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)
03146   *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
03147   *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
03148   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
03149   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
03150   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
03151   *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
03152   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
03153   * @param  Periphs This parameter can be a combination of the following values:
03154   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
03155   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
03156   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
03157   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
03158   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
03159   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
03160   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
03161   *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
03162   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
03163   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
03164   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
03165   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
03166   *
03167   *         (*) value not defined in all devices.
03168   * @retval None
03169 */
03170 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
03171 {
03172   __IO uint32_t tmpreg;
03173   SET_BIT(RCC_C1->AHB3ENR, Periphs);
03174   /* Delay after an RCC peripheral clock enabling */
03175   tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
03176   (void)tmpreg;
03177 }
03178
03179 /**
03180   * @brief  Check if C1 AHB3 peripheral clock is enabled or not
03181   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n
03182   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n
03183   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n
03184   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n
03185   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03186   *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03187   *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03188   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03189   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03190   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03191   *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
03192   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
03193   * @param  Periphs This parameter can be a combination of the following values:
03194   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
03195   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
03196   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
03197   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
03198   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
03199   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
03200   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
03201   *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
03202   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
03203   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
03204   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
03205   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
03206   *
03207   *         (*) value not defined in all devices.
03208   * @retval uint32_t
03209 */
03210 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
03211 {
03212   return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
03213 }
03214
03215 /**
03216   * @brief  Disable C1 AHB3 peripherals clock.
03217   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n
03218   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n
03219   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n
03220   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n
03221   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)
03222   *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
03223   *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
03224   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
03225   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
03226   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
03227   *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
03228   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
03229   * @param  Periphs This parameter can be a combination of the following values:
03230   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
03231   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
03232   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
03233   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
03234   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
03235   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
03236   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
03237   *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
03238   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
03239   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
03240   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
03241   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
03242   *
03243   *         (*) value not defined in all devices.
03244   * @retval None
03245 */
03246 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
03247 {
03248   CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
03249 }
03250
03251 /**
03252   * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
03253   * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
03254   *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
03255   *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
03256   *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n
03257   *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03258   *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03259   *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03260   *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03261   *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03262   *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03263   *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
03264   *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
03265   *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
03266   *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
03267   *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
03268   *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
03269   *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep
03270   * @param  Periphs This parameter can be a combination of the following values:
03271   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
03272   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
03273   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
03274   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
03275   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
03276   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
03277   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
03278   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
03279   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
03280   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
03281   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
03282   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
03283   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
03284   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
03285   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
03286   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
03287   *
03288   *         (*) value not defined in all devices.
03289   * @retval None
03290 */
03291 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
03292 {
03293   __IO uint32_t tmpreg;
03294   SET_BIT(RCC_C1->AHB3LPENR, Periphs);
03295   /* Delay after an RCC peripheral clock enabling */
03296   tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
03297   (void)tmpreg;
03298 }
03299
03300 /**
03301   * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
03302   * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
03303   *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
03304   *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
03305   *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n
03306   *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03307   *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03308   *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03309   *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03310   *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03311   *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03312   *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
03313   *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
03314   *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
03315   *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
03316   *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
03317   *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
03318   *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep
03319   * @param  Periphs This parameter can be a combination of the following values:
03320   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
03321   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
03322   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
03323   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
03324   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
03325   *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
03326   *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
03327   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
03328   *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
03329   *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
03330   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
03331   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
03332   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
03333   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
03334   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
03335   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
03336   *
03337   *         (*) value not defined in all devices.
03338   * @retval None
03339 */
03340 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
03341 {
03342   CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
03343 }
03344
03345 /**
03346   * @}
03347   */
03348
03349 /** @defgroup BUS_LL_EF_AHB1 AHB1
03350   * @{
03351   */
03352
03353 /**
03354   * @brief  Enable C1 AHB1 peripherals clock.
03355   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n
03356   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n
03357   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n
03358   *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
03359   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
03360   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)
03361   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
03362   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
03363   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n
03364   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n
03365   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)
03366   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)
03367   * @param  Periphs This parameter can be a combination of the following values:
03368   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
03369   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
03370   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
03371   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
03372   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
03373   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
03374   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
03375   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
03376   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
03377   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
03378   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
03379   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
03380   *
03381   *         (*) value not defined in all devices.
03382   * @retval None
03383 */
03384 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
03385 {
03386   __IO uint32_t tmpreg;
03387   SET_BIT(RCC_C1->AHB1ENR, Periphs);
03388   /* Delay after an RCC peripheral clock enabling */
03389   tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
03390   (void)tmpreg;
03391 }
03392
03393 /**
03394   * @brief  Check if C1 AHB1 peripheral clock is enabled or not
03395   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
03396   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
03397   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n
03398   *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03399   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03400   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03401   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03402   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03403   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n
03404   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n
03405   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
03406   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)
03407   * @param  Periphs This parameter can be a combination of the following values:
03408   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
03409   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
03410   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
03411   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
03412   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
03413   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
03414   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
03415   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
03416   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
03417   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
03418   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
03419   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
03420   *
03421   *         (*) value not defined in all devices.
03422   * @retval uint32_t
03423 */
03424 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
03425 {
03426   return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
03427 }
03428
03429 /**
03430   * @brief  Disable C1 AHB1 peripherals clock.
03431   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n
03432   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n
03433   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n
03434   *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
03435   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
03436   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)
03437   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
03438   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
03439   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n
03440   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n
03441   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)
03442   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)
03443   * @param  Periphs This parameter can be a combination of the following values:
03444   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
03445   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
03446   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
03447   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
03448   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
03449   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
03450   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
03451   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
03452   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
03453   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
03454   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
03455   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
03456   *
03457   *         (*) value not defined in all devices.
03458   * @retval None
03459 */
03460 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
03461 {
03462   CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
03463 }
03464
03465 /**
03466   * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
03467   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
03468   *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
03469   *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n
03470   *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
03471   *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
03472   *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
03473   *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
03474   *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
03475   *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
03476   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
03477   *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)
03478   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)
03479   * @param  Periphs This parameter can be a combination of the following values:
03480   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
03481   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
03482   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
03483   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
03484   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
03485   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
03486   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
03487   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
03488   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
03489   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
03490   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
03491   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
03492   *
03493   *         (*) value not defined in all devices.
03494   * @retval None
03495 */
03496 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
03497 {
03498   __IO uint32_t tmpreg;
03499   SET_BIT(RCC_C1->AHB1LPENR, Periphs);
03500   /* Delay after an RCC peripheral clock enabling */
03501   tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
03502   (void)tmpreg;
03503 }
03504
03505 /**
03506   * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
03507   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
03508   *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
03509   *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n
03510   *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
03511   *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
03512   *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
03513   *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
03514   *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
03515   *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
03516   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
03517   *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)
03518   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)
03519   * @param  Periphs This parameter can be a combination of the following values:
03520   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
03521   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
03522   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
03523   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
03524   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
03525   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
03526   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
03527   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
03528   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
03529   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
03530   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
03531   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
03532   *
03533   *         (*) value not defined in all devices.
03534   * @retval None
03535 */
03536 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
03537 {
03538   CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
03539 }
03540
03541 /**
03542   * @}
03543   */
03544
03545 /** @defgroup BUS_LL_EF_AHB2 AHB2
03546   * @{
03547   */
03548
03549 /**
03550   * @brief  Enable C1 AHB2 peripherals clock.
03551   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n
03552   *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
03553   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
03554   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
03555   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n
03556   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n
03557   *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)
03558   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n
03559   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n
03560   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)
03561   * @param  Periphs This parameter can be a combination of the following values:
03562   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
03563   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
03564   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
03565   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
03566   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
03567   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
03568   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
03569   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
03570   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
03571   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
03572   *
03573   *         (*) value not defined in all devices.
03574   * @retval None
03575 */
03576 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
03577 {
03578   __IO uint32_t tmpreg;
03579   SET_BIT(RCC_C1->AHB2ENR, Periphs);
03580   /* Delay after an RCC peripheral clock enabling */
03581   tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
03582   (void)tmpreg;
03583 }
03584
03585 /**
03586   * @brief  Check if C1 AHB2 peripheral clock is enabled or not
03587   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n
03588   *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
03589   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
03590   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
03591   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n
03592   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n
03593   *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
03594   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
03595   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
03596   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)
03597   * @param  Periphs This parameter can be a combination of the following values:
03598   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
03599   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
03600   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
03601   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
03602   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
03603   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
03604   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
03605   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
03606   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
03607   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
03608   *
03609   *         (*) value not defined in all devices.
03610   * @retval uint32_t
03611 */
03612 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
03613 {
03614   return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
03615 }
03616
03617 /**
03618   * @brief  Disable C1 AHB2 peripherals clock.
03619   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n
03620   *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
03621   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
03622   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
03623   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n
03624   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n
03625   *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)
03626   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n
03627   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n
03628   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)
03629   * @param  Periphs This parameter can be a combination of the following values:
03630   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
03631   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
03632   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
03633   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
03634   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
03635   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
03636   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
03637   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
03638   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
03639   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
03640   *
03641   *         (*) value not defined in all devices.
03642   * @retval None
03643 */
03644 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
03645 {
03646   CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
03647 }
03648
03649 /**
03650   * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
03651   * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n
03652   *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
03653   *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
03654   *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n
03655   *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
03656   *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
03657   *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
03658   *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
03659   *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)
03660   * @param  Periphs This parameter can be a combination of the following values:
03661   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
03662   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
03663   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
03664   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
03665   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
03666   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
03667   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
03668   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
03669   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
03670   *
03671   *         (*) value not defined in all devices.
03672   * @retval None
03673 */
03674 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
03675 {
03676   __IO uint32_t tmpreg;
03677   SET_BIT(RCC_C1->AHB2LPENR, Periphs);
03678   /* Delay after an RCC peripheral clock enabling */
03679   tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
03680   (void)tmpreg;
03681 }
03682
03683 /**
03684   * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
03685   * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n
03686   *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
03687   *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
03688   *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n
03689   *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n
03690   *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
03691   *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
03692   *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
03693   *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep
03694   * @param  Periphs This parameter can be a combination of the following values:
03695   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
03696   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
03697   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
03698   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
03699   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
03700   *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
03701   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
03702   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
03703   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
03704   *
03705   *         (*) value not defined in all devices.
03706   * @retval None
03707 */
03708 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
03709 {
03710   CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
03711 }
03712
03713 /**
03714   * @}
03715   */
03716
03717 /** @defgroup BUS_LL_EF_AHB4 AHB4
03718   * @{
03719   */
03720
03721 /**
03722   * @brief  Enable C1 AHB4 peripherals clock.
03723   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n
03724   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n
03725   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n
03726   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n
03727   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n
03728   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n
03729   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n
03730   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n
03731   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n
03732   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n
03733   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n
03734   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)
03735   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n
03736   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)
03737   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)
03738   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n
03739   *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock
03740   * @param  Periphs This parameter can be a combination of the following values:
03741   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
03742   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
03743   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
03744   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
03745   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
03746   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
03747   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
03748   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
03749   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
03750   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
03751   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
03752   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
03753   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
03754   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
03755   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
03756   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
03757   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
03758   *
03759   *         (*) value not defined in all devices.
03760   * @retval None
03761 */
03762 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
03763 {
03764   __IO uint32_t tmpreg;
03765   SET_BIT(RCC_C1->AHB4ENR, Periphs);
03766   /* Delay after an RCC peripheral clock enabling */
03767   tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
03768   (void)tmpreg;
03769 }
03770
03771 /**
03772   * @brief  Check if C1 AHB4 peripheral clock is enabled or not
03773   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03774   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03775   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03776   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03777   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03778   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03779   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03780   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03781   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03782   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03783   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
03784   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
03785   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n
03786   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
03787   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
03788   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n
03789   *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock
03790   * @param  Periphs This parameter can be a combination of the following values:
03791   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
03792   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
03793   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
03794   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
03795   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
03796   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
03797   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
03798   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
03799   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
03800   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
03801   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
03802   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
03803   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
03804   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
03805   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
03806   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
03807   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
03808   *
03809   *         (*) value not defined in all devices.
03810   * @retval uint32_t
03811 */
03812 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
03813 {
03814   return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
03815 }
03816
03817 /**
03818   * @brief  Disable C1 AHB4 peripherals clock.
03819   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n
03820   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n
03821   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n
03822   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n
03823   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n
03824   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n
03825   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n
03826   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n
03827   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n
03828   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n
03829   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n
03830   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)
03831   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n
03832   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)
03833   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)
03834   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n
03835   *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock
03836   * @param  Periphs This parameter can be a combination of the following values:
03837   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
03838   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
03839   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
03840   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
03841   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
03842   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
03843   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
03844   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
03845   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
03846   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
03847   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
03848   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
03849   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
03850   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
03851   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
03852   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
03853   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
03854   *
03855   *         (*) value not defined in all devices.
03856   * @retval None
03857 */
03858 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
03859 {
03860   CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
03861 }
03862
03863 /**
03864   * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
03865   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03866   *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03867   *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03868   *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03869   *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03870   *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03871   *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03872   *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03873   *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03874   *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03875   *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
03876   *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
03877   *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n
03878   *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
03879   *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n
03880   *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep
03881   * @param  Periphs This parameter can be a combination of the following values:
03882   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
03883   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
03884   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
03885   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
03886   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
03887   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
03888   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
03889   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
03890   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
03891   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
03892   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
03893   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
03894   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
03895   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
03896   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
03897   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
03898   * @retval None
03899 */
03900 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
03901 {
03902   __IO uint32_t tmpreg;
03903   SET_BIT(RCC_C1->AHB4LPENR, Periphs);
03904   /* Delay after an RCC peripheral clock enabling */
03905   tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
03906   (void)tmpreg;
03907 }
03908
03909 /**
03910   * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
03911   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03912   *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03913   *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03914   *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03915   *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03916   *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03917   *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03918   *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03919   *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03920   *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03921   *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
03922   *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
03923   *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n
03924   *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
03925   *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n
03926   *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep
03927   * @param  Periphs This parameter can be a combination of the following values:
03928   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
03929   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
03930   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
03931   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
03932   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
03933   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
03934   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
03935   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
03936   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
03937   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
03938   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
03939   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
03940   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
03941   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
03942   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
03943   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
03944   * @retval None
03945 */
03946 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
03947 {
03948   CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
03949 }
03950
03951 /**
03952   * @}
03953   */
03954
03955 /** @defgroup BUS_LL_EF_APB3 APB3
03956   * @{
03957   */
03958
03959 /**
03960   * @brief  Enable C1 APB3 peripherals clock.
03961   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)
03962   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)
03963   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock
03964   * @param  Periphs This parameter can be a combination of the following values:
03965   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
03966   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
03967   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
03968   *
03969   *         (*) value not defined in all devices.
03970   * @retval None
03971 */
03972 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
03973 {
03974   __IO uint32_t tmpreg;
03975   SET_BIT(RCC_C1->APB3ENR, Periphs);
03976   /* Delay after an RCC peripheral clock enabling */
03977   tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
03978   (void)tmpreg;
03979 }
03980
03981 /**
03982   * @brief  Check if C1 APB3 peripheral clock is enabled or not
03983   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)
03984   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)
03985   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock
03986   * @param  Periphs This parameter can be a combination of the following values:
03987   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
03988   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
03989   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
03990   *
03991   *         (*) value not defined in all devices.
03992   * @retval uint32_t
03993 */
03994 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
03995 {
03996   return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
03997 }
03998
03999 /**
04000   * @brief  Disable C1 APB3 peripherals clock.
04001   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)
04002   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)
04003   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock
04004   * @param  Periphs This parameter can be a combination of the following values:
04005   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
04006   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
04007   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
04008   *
04009   *         (*) value not defined in all devices.
04010   * @retval None
04011 */
04012 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
04013 {
04014   CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
04015 }
04016
04017 /**
04018   * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
04019   * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)
04020   *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)
04021   *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep
04022   * @param  Periphs This parameter can be a combination of the following values:
04023   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
04024   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
04025   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
04026   *
04027   *         (*) value not defined in all devices.
04028   * @retval None
04029 */
04030 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
04031 {
04032   __IO uint32_t tmpreg;
04033   SET_BIT(RCC_C1->APB3LPENR, Periphs);
04034   /* Delay after an RCC peripheral clock enabling */
04035   tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
04036   (void)tmpreg;
04037 }
04038
04039 /**
04040   * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
04041   * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)
04042   *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)
04043   *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep
04044   * @param  Periphs This parameter can be a combination of the following values:
04045   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
04046   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
04047   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
04048   *
04049   *         (*) value not defined in all devices.
04050   * @retval None
04051 */
04052 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
04053 {
04054   CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
04055 }
04056
04057 /**
04058   * @}
04059   */
04060
04061 /** @defgroup BUS_LL_EF_APB1 APB1
04062   * @{
04063   */
04064
04065 /**
04066   * @brief  Enable C1 APB1 peripherals clock.
04067   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n
04068   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n
04069   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n
04070   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n
04071   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n
04072   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n
04073   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n
04074   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n
04075   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n
04076   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n
04077   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)
04078   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n
04079   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n
04080   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n
04081   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n
04082   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n
04083   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n
04084   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n
04085   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n
04086   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n
04087   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n
04088   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n
04089   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n
04090   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n
04091   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock
04092   * @param  Periphs This parameter can be a combination of the following values:
04093   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
04094   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
04095   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
04096   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
04097   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
04098   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
04099   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
04100   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
04101   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
04102   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
04103   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
04104   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
04105   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
04106   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
04107   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
04108   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
04109   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
04110   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
04111   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
04112   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
04113   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
04114   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
04115   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
04116   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
04117   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
04118   *
04119   *         (*) value not defined in all devices.
04120   * @retval None
04121 */
04122 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
04123 {
04124   __IO uint32_t tmpreg;
04125   SET_BIT(RCC_C1->APB1LENR, Periphs);
04126   /* Delay after an RCC peripheral clock enabling */
04127   tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
04128   (void)tmpreg;
04129 }
04130
04131 /**
04132   * @brief  Check if C1 APB1 peripheral clock is enabled or not
04133   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04134   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04135   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04136   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04137   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04138   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04139   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04140   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04141   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04142   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n
04143   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)
04144   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04145   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04146   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n
04147   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n
04148   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n
04149   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04150   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04151   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04152   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04153   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
04154   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n
04155   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04156   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n
04157   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock
04158   * @param  Periphs This parameter can be a combination of the following values:
04159   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
04160   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
04161   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
04162   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
04163   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
04164   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
04165   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
04166   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
04167   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
04168   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
04169   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
04170   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
04171   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
04172   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
04173   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
04174   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
04175   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
04176   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
04177   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
04178   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
04179   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
04180   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
04181   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
04182   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
04183   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
04184   *
04185   *         (*) value not defined in all devices.
04186   * @retval uint32_t
04187 */
04188 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
04189 {
04190   return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
04191 }
04192
04193 /**
04194   * @brief  Disable C1 APB1 peripherals clock.
04195   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n
04196   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n
04197   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n
04198   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n
04199   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n
04200   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n
04201   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n
04202   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n
04203   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n
04204   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n
04205   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)
04206   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n
04207   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n
04208   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n
04209   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n
04210   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n
04211   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n
04212   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n
04213   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n
04214   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n
04215   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n
04216   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n
04217   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n
04218   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n
04219   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock
04220   * @param  Periphs This parameter can be a combination of the following values:
04221   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
04222   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
04223   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
04224   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
04225   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
04226   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
04227   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
04228   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
04229   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
04230   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
04231   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
04232   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
04233   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
04234   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
04235   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
04236   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
04237   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
04238   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
04239   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
04240   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
04241   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
04242   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
04243   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
04244   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
04245   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
04246   *
04247   *         (*) value not defined in all devices.
04248   * @retval uint32_t
04249 */
04250 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
04251 {
04252   CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
04253 }
04254
04255 /**
04256   * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
04257   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04258   *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04259   *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04260   *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04261   *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04262   *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04263   *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04264   *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04265   *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04266   *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
04267   *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)
04268   *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04269   *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04270   *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n
04271   *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
04272   *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
04273   *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04274   *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04275   *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04276   *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04277   *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
04278   *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n
04279   *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04280   *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
04281   *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep
04282   * @param  Periphs This parameter can be a combination of the following values:
04283   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
04284   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
04285   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
04286   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
04287   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
04288   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
04289   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
04290   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
04291   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
04292   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
04293   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
04294   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
04295   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
04296   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
04297   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
04298   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
04299   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
04300   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
04301   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
04302   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
04303   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
04304   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
04305   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
04306   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
04307   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
04308   *
04309   *         (*) value not defined in all devices.
04310   * @retval None
04311 */
04312 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
04313 {
04314   __IO uint32_t tmpreg;
04315   SET_BIT(RCC_C1->APB1LLPENR, Periphs);
04316   /* Delay after an RCC peripheral clock enabling */
04317   tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
04318   (void)tmpreg;
04319 }
04320
04321 /**
04322   * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
04323   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04324   *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04325   *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04326   *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04327   *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04328   *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04329   *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04330   *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04331   *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04332   *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
04333   *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)
04334   *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04335   *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04336   *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n
04337   *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
04338   *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
04339   *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04340   *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04341   *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04342   *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04343   *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
04344   *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n
04345   *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04346   *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
04347   *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep
04348   * @param  Periphs This parameter can be a combination of the following values:
04349   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
04350   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
04351   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
04352   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
04353   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
04354   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
04355   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
04356   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
04357   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
04358   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
04359   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
04360   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
04361   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
04362   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
04363   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
04364   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
04365   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
04366   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
04367   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
04368   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
04369   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
04370   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
04371   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
04372   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
04373   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
04374   *
04375   *         (*) value not defined in all devices.
04376   * @retval None
04377 */
04378 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
04379 {
04380   CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
04381 }
04382
04383 /**
04384   * @brief  Enable C1 APB1 peripherals clock.
04385   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n
04386   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n
04387   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n
04388   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n
04389   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock
04390   * @param  Periphs This parameter can be a combination of the following values:
04391   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
04392   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
04393   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
04394   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
04395   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
04396   * @retval None
04397 */
04398 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
04399 {
04400   __IO uint32_t tmpreg;
04401   SET_BIT(RCC_C1->APB1HENR, Periphs);
04402   /* Delay after an RCC peripheral clock enabling */
04403   tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
04404   (void)tmpreg;
04405 }
04406
04407 /**
04408   * @brief  Check if C1 APB1 peripheral clock is enabled or not
04409   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n
04410   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n
04411   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n
04412   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n
04413   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock
04414   * @param  Periphs This parameter can be a combination of the following values:
04415   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
04416   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
04417   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
04418   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
04419   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
04420   * @retval uint32_t
04421 */
04422 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
04423 {
04424   return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
04425 }
04426
04427 /**
04428   * @brief  Disable C1 APB1 peripherals clock.
04429   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n
04430   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n
04431   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n
04432   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n
04433   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock
04434   * @param  Periphs This parameter can be a combination of the following values:
04435   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
04436   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
04437   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
04438   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
04439   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
04440   * @retval None
04441 */
04442 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
04443 {
04444   CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
04445 }
04446
04447 /**
04448   * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
04449   * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n
04450   *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
04451   *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
04452   *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
04453   *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep
04454   * @param  Periphs This parameter can be a combination of the following values:
04455   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
04456   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
04457   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
04458   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
04459   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
04460   * @retval None
04461 */
04462 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
04463 {
04464   __IO uint32_t tmpreg;
04465   SET_BIT(RCC_C1->APB1HLPENR, Periphs);
04466   /* Delay after an RCC peripheral clock enabling */
04467   tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
04468   (void)tmpreg;
04469 }
04470
04471 /**
04472   * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
04473   * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n
04474   *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
04475   *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
04476   *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
04477   *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep
04478   * @param  Periphs This parameter can be a combination of the following values:
04479   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
04480   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
04481   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
04482   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
04483   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
04484   * @retval None
04485 */
04486 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
04487 {
04488   CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
04489 }
04490
04491 /**
04492   * @}
04493   */
04494
04495 /** @defgroup BUS_LL_EF_APB2 APB2
04496   * @{
04497   */
04498
04499 /**
04500   * @brief  Enable C1 APB2 peripherals clock.
04501   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n
04502   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n
04503   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n
04504   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n
04505   *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)
04506   *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)
04507   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n
04508   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n
04509   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n
04510   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n
04511   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n
04512   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n
04513   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n
04514   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n
04515   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)
04516   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n
04517   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)
04518   * @param  Periphs This parameter can be a combination of the following values:
04519   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
04520   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
04521   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
04522   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
04523   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
04524   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
04525   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
04526   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
04527   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
04528   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
04529   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
04530   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
04531   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
04532   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
04533   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
04534   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
04535   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
04536   *
04537   *         (*) value not defined in all devices.
04538   * @retval None
04539 */
04540 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
04541 {
04542   __IO uint32_t tmpreg;
04543   SET_BIT(RCC_C1->APB2ENR, Periphs);
04544   /* Delay after an RCC peripheral clock enabling */
04545   tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
04546   (void)tmpreg;
04547 }
04548
04549 /**
04550   * @brief  Check if C1 APB2 peripheral clock is enabled or not
04551   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04552   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04553   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
04554   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n
04555   *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)
04556   *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)
04557   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04558   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04559   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n
04560   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n
04561   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n
04562   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04563   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04564   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n
04565   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)
04566   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
04567   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)
04568   * @param  Periphs This parameter can be a combination of the following values:
04569   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
04570   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
04571   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
04572   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
04573   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
04574   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
04575   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
04576   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
04577   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
04578   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
04579   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
04580   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
04581   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
04582   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
04583   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
04584   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
04585   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
04586   *
04587   *         (*) value not defined in all devices.
04588   * @retval None
04589 */
04590 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
04591 {
04592   return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
04593 }
04594
04595 /**
04596   * @brief  Disable C1 APB2 peripherals clock.
04597   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n
04598   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n
04599   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n
04600   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n
04601   *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)
04602   *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)
04603   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n
04604   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n
04605   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n
04606   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n
04607   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n
04608   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n
04609   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n
04610   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n
04611   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)
04612   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n
04613   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)
04614   * @param  Periphs This parameter can be a combination of the following values:
04615   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
04616   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
04617   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
04618   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
04619   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
04620   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
04621   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
04622   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
04623   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
04624   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
04625   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
04626   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
04627   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
04628   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
04629   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
04630   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
04631   *
04632   *         (*) value not defined in all devices.
04633   * @retval None
04634 */
04635 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
04636 {
04637   CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
04638 }
04639
04640 /**
04641   * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
04642   * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04643   *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04644   *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
04645   *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
04646   *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)
04647   *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)
04648   *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04649   *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04650   *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
04651   *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
04652   *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
04653   *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04654   *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04655   *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
04656   *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)
04657   *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
04658   *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)
04659   * @param  Periphs This parameter can be a combination of the following values:
04660   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
04661   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
04662   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
04663   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
04664   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
04665   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
04666   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
04667   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
04668   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
04669   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
04670   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
04671   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
04672   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
04673   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
04674   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
04675   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
04676   *
04677   *         (*) value not defined in all devices.
04678   * @retval None
04679 */
04680 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
04681 {
04682   __IO uint32_t tmpreg;
04683   SET_BIT(RCC_C1->APB2LPENR, Periphs);
04684   /* Delay after an RCC peripheral clock enabling */
04685   tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
04686   (void)tmpreg;
04687 }
04688
04689 /**
04690   * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
04691   * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04692   *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04693   *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
04694   *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)
04695   *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)
04696   *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
04697   *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04698   *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04699   *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
04700   *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
04701   *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
04702   *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04703   *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04704   *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
04705   *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)
04706   *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
04707   *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)
04708   * @param  Periphs This parameter can be a combination of the following values:
04709   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
04710   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
04711   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
04712   *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
04713   *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
04714   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
04715   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
04716   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
04717   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
04718   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
04719   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
04720   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
04721   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
04722   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
04723   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
04724   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
04725   *
04726   *         (*) value not defined in all devices.
04727   * @retval None
04728 */
04729 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
04730 {
04731   CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
04732 }
04733
04734 /**
04735   * @}
04736   */
04737
04738 /** @defgroup BUS_LL_EF_APB4 APB4
04739   * @{
04740   */
04741
04742 /**
04743   * @brief  Enable C1 APB4 peripherals clock.
04744   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n
04745   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n
04746   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n
04747   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n
04748   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n
04749   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n
04750   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)
04751   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)
04752   *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)
04753   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n
04754   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n
04755   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n
04756   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)
04757   *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)
04758   *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)
04759   * @param  Periphs This parameter can be a combination of the following values:
04760   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
04761   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
04762   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
04763   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
04764   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
04765   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
04766   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
04767   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
04768   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
04769   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
04770   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
04771   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
04772   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
04773   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
04774   *
04775   *         (*) value not defined in all devices.
04776   * @retval None
04777 */
04778 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
04779 {
04780   __IO uint32_t tmpreg;
04781   SET_BIT(RCC_C1->APB4ENR, Periphs);
04782   /* Delay after an RCC peripheral clock enabling */
04783   tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
04784   (void)tmpreg;
04785 }
04786
04787 /**
04788   * @brief  Check if C1 APB4 peripheral clock is enabled or not
04789   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n
04790   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n
04791   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n
04792   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n
04793   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n
04794   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n
04795   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
04796   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
04797   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n
04798   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n
04799   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n
04800   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)
04801   *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)
04802   *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)
04803   * @param  Periphs This parameter can be a combination of the following values:
04804   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
04805   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
04806   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
04807   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
04808   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
04809   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
04810   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
04811   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
04812   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
04813   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
04814   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
04815   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
04816   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
04817   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
04818   *
04819   *         (*) value not defined in all devices.
04820   * @retval uint32_t
04821 */
04822 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
04823 {
04824   return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
04825 }
04826
04827 /**
04828   * @brief  Disable C1 APB4 peripherals clock.
04829   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n
04830   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n
04831   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n
04832   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n
04833   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n
04834   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n
04835   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)
04836   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)
04837   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n
04838   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n
04839   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n
04840   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)
04841   *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)
04842   *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)
04843   * @param  Periphs This parameter can be a combination of the following values:
04844   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
04845   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
04846   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
04847   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
04848   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
04849   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
04850   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
04851   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
04852   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
04853   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
04854   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
04855   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
04856   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
04857   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
04858   *
04859   *         (*) value not defined in all devices.
04860   * @retval None
04861 */
04862 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
04863 {
04864   CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
04865 }
04866
04867 /**
04868   * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
04869   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
04870   *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n
04871   *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
04872   *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
04873   *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
04874   *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
04875   *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
04876   *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
04877   *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
04878   *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
04879   *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
04880   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClockSleep\n (*)
04881   *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClockSleep\n (*)
04882   *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClockSleep   (*)
04883   * @param  Periphs This parameter can be a combination of the following values:
04884   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
04885   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
04886   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
04887   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
04888   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
04889   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
04890   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
04891   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
04892   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
04893   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
04894   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
04895   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
04896   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
04897   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
04898   *
04899   *         (*) value not defined in all devices.
04900   * @retval None
04901 */
04902 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
04903 {
04904   __IO uint32_t tmpreg;
04905   SET_BIT(RCC_C1->APB4LPENR, Periphs);
04906   /* Delay after an RCC peripheral clock enabling */
04907   tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
04908   (void)tmpreg;
04909 }
04910
04911 /**
04912   * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
04913   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04914   *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n
04915   *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
04916   *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
04917   *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04918   *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04919   *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04920   *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04921   *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04922   *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
04923   *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
04924   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClockSleep\n (*)
04925   *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClockSleep\n (*)
04926   *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClockSleep   (*)
04927   * @param  Periphs This parameter can be a combination of the following values:
04928   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
04929   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
04930   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
04931   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
04932   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
04933   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
04934   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
04935   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
04936   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
04937   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
04938   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
04939   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
04940   *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
04941   *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
04942   *
04943   *         (*) value not defined in all devices.
04944   * @retval None
04945 */
04946 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
04947 {
04948   CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
04949 }
04950
04951 /**
04952   * @}
04953   */
04954
04955 /** @defgroup BUS_LL_EF_AHB3 AHB3
04956   * @{
04957   */
04958
04959 /**
04960   * @brief  Enable C2 AHB3 peripherals clock.
04961   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n
04962   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n
04963   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n
04964   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n
04965   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n
04966   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n
04967   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n
04968   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n
04969   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n
04970   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n
04971   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock
04972   * @param  Periphs This parameter can be a combination of the following values:
04973   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
04974   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
04975   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
04976   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
04977   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
04978   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
04979   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
04980   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
04981   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
04982   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
04983   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
04984   * @retval None
04985 */
04986 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
04987 {
04988   __IO uint32_t tmpreg;
04989   SET_BIT(RCC_C2->AHB3ENR, Periphs);
04990   /* Delay after an RCC peripheral clock enabling */
04991   tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
04992   (void)tmpreg;
04993 }
04994
04995 /**
04996   * @brief  Check if C2 AHB3 peripheral clock is enabled or not
04997   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
04998   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
04999   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n
05000   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
05001   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
05002   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n
05003   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
05004   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
05005   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
05006   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
05007   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock
05008   * @param  Periphs This parameter can be a combination of the following values:
05009   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
05010   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
05011   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
05012   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
05013   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
05014   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
05015   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
05016   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
05017   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
05018   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
05019   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
05020   * @retval uint32_t
05021 */
05022 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
05023 {
05024   return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
05025 }
05026
05027 /**
05028   * @brief  Disable C2 AHB3 peripherals clock.
05029   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n
05030   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n
05031   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n
05032   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n
05033   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n
05034   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n
05035   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n
05036   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n
05037   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n
05038   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n
05039   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock
05040   * @param  Periphs This parameter can be a combination of the following values:
05041   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
05042   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
05043   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
05044   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
05045   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
05046   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
05047   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
05048   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
05049   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
05050   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
05051   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
05052   * @retval None
05053 */
05054 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
05055 {
05056   CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
05057 }
05058
05059 /**
05060   * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
05061   * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
05062   *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
05063   *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
05064   *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
05065   *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
05066   *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
05067   *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
05068   *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
05069   *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
05070   *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
05071   *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep
05072   * @param  Periphs This parameter can be a combination of the following values:
05073   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
05074   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
05075   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
05076   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
05077   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
05078   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
05079   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
05080   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
05081   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
05082   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
05083   * @retval None
05084 */
05085 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
05086 {
05087   __IO uint32_t tmpreg;
05088   SET_BIT(RCC_C2->AHB3LPENR, Periphs);
05089   /* Delay after an RCC peripheral clock enabling */
05090   tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
05091   (void)tmpreg;
05092 }
05093
05094 /**
05095   * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
05096   * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
05097   *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
05098   *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
05099   *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
05100   *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
05101   *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
05102   *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
05103   *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
05104   *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
05105   *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
05106   *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep
05107   * @param  Periphs This parameter can be a combination of the following values:
05108   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
05109   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
05110   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
05111   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
05112   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
05113   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
05114   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
05115   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
05116   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
05117   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
05118   * @retval None
05119 */
05120 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
05121 {
05122   CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
05123 }
05124
05125 /**
05126   * @}
05127   */
05128
05129 /** @defgroup BUS_LL_EF_AHB1 AHB1
05130   * @{
05131   */
05132
05133 /**
05134   * @brief  Enable C2 AHB1 peripherals clock.
05135   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
05136   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
05137   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n
05138   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n
05139   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n
05140   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n
05141   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n
05142   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
05143   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n
05144   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
05145   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock
05146   * @param  Periphs This parameter can be a combination of the following values:
05147   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
05148   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
05149   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
05150   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
05151   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
05152   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
05153   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
05154   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
05155   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
05156   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
05157   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
05158   * @retval None
05159 */
05160 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
05161 {
05162   __IO uint32_t tmpreg;
05163   SET_BIT(RCC_C2->AHB1ENR, Periphs);
05164   /* Delay after an RCC peripheral clock enabling */
05165   tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
05166   (void)tmpreg;
05167 }
05168
05169 /**
05170   * @brief  Check if C2 AHB1 peripheral clock is enabled or not
05171   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
05172   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
05173   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
05174   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
05175   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n
05176   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
05177   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
05178   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
05179   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n
05180   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
05181   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock
05182   * @param  Periphs This parameter can be a combination of the following values:
05183   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
05184   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
05185   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
05186   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
05187   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
05188   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
05189   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
05190   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
05191   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
05192   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
05193   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
05194   * @retval uint32_t
05195 */
05196 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
05197 {
05198   return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
05199 }
05200
05201 /**
05202   * @brief  Disable C2 AHB1 peripherals clock.
05203   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
05204   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
05205   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n
05206   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n
05207   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n
05208   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n
05209   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n
05210   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
05211   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n
05212   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
05213   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock
05214   * @param  Periphs This parameter can be a combination of the following values:
05215   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
05216   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
05217   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
05218   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
05219   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
05220   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
05221   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
05222   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
05223   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
05224   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
05225   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
05226   * @retval None
05227 */
05228 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
05229 {
05230   CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
05231 }
05232
05233 /**
05234   * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
05235   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
05236   *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
05237   *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
05238   *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
05239   *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
05240   *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
05241   *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
05242   *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
05243   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
05244   *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
05245   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep
05246   * @param  Periphs This parameter can be a combination of the following values:
05247   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
05248   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
05249   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
05250   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
05251   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
05252   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
05253   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
05254   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
05255   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
05256   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
05257   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
05258   * @retval None
05259 */
05260 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
05261 {
05262   __IO uint32_t tmpreg;
05263   SET_BIT(RCC_C2->AHB1LPENR, Periphs);
05264   /* Delay after an RCC peripheral clock enabling */
05265   tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
05266   (void)tmpreg;
05267 }
05268
05269 /**
05270   * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
05271   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
05272   *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
05273   *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
05274   *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
05275   *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n
05276   *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
05277   *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
05278   *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
05279   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
05280   *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
05281   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep
05282   * @param  Periphs This parameter can be a combination of the following values:
05283   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
05284   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
05285   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
05286   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
05287   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
05288   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
05289   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
05290   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
05291   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
05292   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
05293   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
05294   * @retval None
05295 */
05296 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
05297 {
05298   CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
05299 }
05300
05301 /**
05302   * @}
05303   */
05304
05305 /** @defgroup BUS_LL_EF_AHB2 AHB2
05306   * @{
05307   */
05308
05309 /**
05310   * @brief  Enable C2 AHB2 peripherals clock.
05311   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n
05312   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n
05313   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n
05314   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n
05315   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock
05316   * @param  Periphs This parameter can be a combination of the following values:
05317   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
05318   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
05319   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
05320   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
05321   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
05322   *
05323   *         (*) value not defined in all devices.
05324   * @retval None
05325 */
05326 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
05327 {
05328   __IO uint32_t tmpreg;
05329   SET_BIT(RCC_C2->AHB2ENR, Periphs);
05330   /* Delay after an RCC peripheral clock enabling */
05331   tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
05332   (void)tmpreg;
05333 }
05334
05335 /**
05336   * @brief  Check if C2 AHB2 peripheral clock is enabled or not
05337   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
05338   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
05339   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
05340   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
05341   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock
05342   * @param  Periphs This parameter can be a combination of the following values:
05343   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
05344   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
05345   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
05346   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
05347   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
05348   *
05349   *         (*) value not defined in all devices.
05350   * @retval uint32_t
05351 */
05352 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
05353 {
05354   return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
05355 }
05356
05357 /**
05358   * @brief  Disable C2 AHB2 peripherals clock.
05359   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n
05360   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n
05361   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n
05362   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n
05363   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock
05364   * @param  Periphs This parameter can be a combination of the following values:
05365   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
05366   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
05367   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
05368   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
05369   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
05370   *
05371   *         (*) value not defined in all devices.
05372   * @retval None
05373 */
05374 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
05375 {
05376   CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
05377 }
05378
05379 /**
05380   * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
05381   * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
05382   *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
05383   *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
05384   *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
05385   *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n
05386   *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
05387   *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
05388   *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep
05389   * @param  Periphs This parameter can be a combination of the following values:
05390   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
05391   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
05392   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
05393   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
05394   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
05395   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
05396   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
05397   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
05398   *
05399   *         (*) value not defined in all devices.
05400   * @retval None
05401 */
05402 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
05403 {
05404   __IO uint32_t tmpreg;
05405   SET_BIT(RCC_C2->AHB2LPENR, Periphs);
05406   /* Delay after an RCC peripheral clock enabling */
05407   tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
05408   (void)tmpreg;
05409 }
05410
05411 /**
05412   * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
05413   * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
05414   *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
05415   *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
05416   *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
05417   *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n
05418   *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
05419   *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
05420   *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep
05421   * @param  Periphs This parameter can be a combination of the following values:
05422   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
05423   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
05424   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
05425   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
05426   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
05427   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
05428   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
05429   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
05430   *
05431   *         (*) value not defined in all devices.
05432   * @retval None
05433 */
05434 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
05435 {
05436   CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
05437 }
05438
05439 /**
05440   * @}
05441   */
05442
05443 /** @defgroup BUS_LL_EF_AHB4 AHB4
05444   * @{
05445   */
05446
05447 /**
05448   * @brief  Enable C2 AHB4 peripherals clock.
05449   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n
05450   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n
05451   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n
05452   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n
05453   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n
05454   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n
05455   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n
05456   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n
05457   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n
05458   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n
05459   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n
05460   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n
05461   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n
05462   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n
05463   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n
05464   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n
05465   *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock
05466   * @param  Periphs This parameter can be a combination of the following values:
05467   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
05468   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
05469   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
05470   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
05471   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
05472   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
05473   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
05474   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
05475   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
05476   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
05477   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
05478   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
05479   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
05480   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
05481   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
05482   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
05483   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
05484   *
05485   *         (*) value not defined in all devices.
05486   * @retval None
05487 */
05488 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
05489 {
05490   __IO uint32_t tmpreg;
05491   SET_BIT(RCC_C2->AHB4ENR, Periphs);
05492   /* Delay after an RCC peripheral clock enabling */
05493   tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
05494   (void)tmpreg;
05495 }
05496
05497 /**
05498   * @brief  Check if C2 AHB4 peripheral clock is enabled or not
05499   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05500   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05501   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05502   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05503   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05504   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05505   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05506   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05507   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05508   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05509   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
05510   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n
05511   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
05512   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n
05513   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
05514   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n
05515   *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock
05516   * @param  Periphs This parameter can be a combination of the following values:
05517   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
05518   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
05519   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
05520   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
05521   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
05522   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
05523   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
05524   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
05525   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
05526   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
05527   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
05528   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
05529   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
05530   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
05531   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
05532   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
05533   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
05534   *
05535   *         (*) value not defined in all devices.
05536   * @retval uint32_t
05537 */
05538 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
05539 {
05540   return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
05541 }
05542
05543 /**
05544   * @brief  Disable C2 AHB4 peripherals clock.
05545   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n
05546   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n
05547   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n
05548   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n
05549   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n
05550   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n
05551   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n
05552   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n
05553   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n
05554   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n
05555   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n
05556   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n
05557   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n
05558   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n
05559   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n
05560   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n
05561   *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock
05562   * @param  Periphs This parameter can be a combination of the following values:
05563   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
05564   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
05565   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
05566   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
05567   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
05568   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
05569   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
05570   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
05571   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
05572   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
05573   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
05574   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
05575   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
05576   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
05577   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
05578   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
05579   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
05580   *
05581   *         (*) value not defined in all devices.
05582   * @retval None
05583 */
05584 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
05585 {
05586   CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
05587 }
05588
05589 /**
05590   * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
05591   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05592   *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05593   *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05594   *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05595   *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05596   *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05597   *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05598   *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05599   *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05600   *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05601   *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
05602   *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n
05603   *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
05604   *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
05605   *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n
05606   *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep
05607   * @param  Periphs This parameter can be a combination of the following values:
05608   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
05609   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
05610   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
05611   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
05612   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
05613   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
05614   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
05615   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
05616   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
05617   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
05618   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
05619   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
05620   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
05621   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
05622   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
05623   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
05624   * @retval None
05625 */
05626 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
05627 {
05628   __IO uint32_t tmpreg;
05629   SET_BIT(RCC_C2->AHB4LPENR, Periphs);
05630   /* Delay after an RCC peripheral clock enabling */
05631   tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
05632   (void)tmpreg;
05633 }
05634
05635 /**
05636   * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
05637   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05638   *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05639   *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05640   *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05641   *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05642   *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05643   *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05644   *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05645   *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05646   *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05647   *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
05648   *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n
05649   *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
05650   *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
05651   *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n
05652   *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep
05653   * @param  Periphs This parameter can be a combination of the following values:
05654   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
05655   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
05656   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
05657   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
05658   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
05659   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
05660   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
05661   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
05662   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
05663   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
05664   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
05665   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
05666   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
05667   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
05668   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
05669   *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
05670   * @retval None
05671 */
05672 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
05673 {
05674   CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
05675 }
05676
05677 /**
05678   * @}
05679   */
05680
05681 /** @defgroup BUS_LL_EF_APB3 APB3
05682   * @{
05683   */
05684
05685 /**
05686   * @brief  Enable C2 APB3 peripherals clock.
05687   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n
05688   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n
05689   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock
05690   * @param  Periphs This parameter can be a combination of the following values:
05691   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
05692   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
05693   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
05694   *
05695   *         (*) value not defined in all devices.
05696   * @retval None
05697 */
05698 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
05699 {
05700   __IO uint32_t tmpreg;
05701   SET_BIT(RCC_C2->APB3ENR, Periphs);
05702   /* Delay after an RCC peripheral clock enabling */
05703   tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
05704   (void)tmpreg;
05705 }
05706
05707 /**
05708   * @brief  Check if C2 APB3 peripheral clock is enabled or not
05709   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n
05710   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n
05711   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock
05712   * @param  Periphs This parameter can be a combination of the following values:
05713   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
05714   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
05715   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
05716   *
05717   *         (*) value not defined in all devices.
05718   * @retval uint32_t
05719 */
05720 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
05721 {
05722   return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
05723 }
05724
05725 /**
05726   * @brief  Disable C2 APB3 peripherals clock.
05727   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n
05728   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n
05729   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock
05730   * @param  Periphs This parameter can be a combination of the following values:
05731   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
05732   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
05733   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
05734   *
05735   *         (*) value not defined in all devices.
05736   * @retval None
05737 */
05738 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
05739 {
05740   CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
05741 }
05742
05743 /**
05744   * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
05745   * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n
05746   *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n
05747   *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep
05748   * @param  Periphs This parameter can be a combination of the following values:
05749   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
05750   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
05751   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
05752   *
05753   *         (*) value not defined in all devices.
05754   * @retval None
05755 */
05756 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
05757 {
05758   __IO uint32_t tmpreg;
05759   SET_BIT(RCC_C2->APB3LPENR, Periphs);
05760   /* Delay after an RCC peripheral clock enabling */
05761   tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
05762   (void)tmpreg;
05763 }
05764
05765 /**
05766   * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
05767   * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n
05768   *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n
05769   *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep
05770   * @param  Periphs This parameter can be a combination of the following values:
05771   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
05772   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
05773   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
05774   *
05775   *         (*) value not defined in all devices.
05776   * @retval None
05777 */
05778 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
05779 {
05780   CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
05781 }
05782
05783 /**
05784   * @}
05785   */
05786
05787 /** @defgroup BUS_LL_EF_APB1 APB1
05788   * @{
05789   */
05790
05791 /**
05792   * @brief  Enable C2 APB1 peripherals clock.
05793   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
05794   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n
05795   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n
05796   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n
05797   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n
05798   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n
05799   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n
05800   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n
05801   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n
05802   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n
05803   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n
05804   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
05805   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n
05806   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n
05807   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n
05808   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n
05809   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n
05810   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n
05811   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
05812   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n
05813   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
05814   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n
05815   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n
05816   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n
05817   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock
05818   * @param  Periphs This parameter can be a combination of the following values:
05819   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
05820   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
05821   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
05822   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
05823   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
05824   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
05825   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
05826   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
05827   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
05828   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
05829   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
05830   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
05831   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
05832   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
05833   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
05834   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
05835   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
05836   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
05837   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
05838   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
05839   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
05840   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
05841   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
05842   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
05843   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
05844   * @retval None
05845 */
05846 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
05847 {
05848   __IO uint32_t tmpreg;
05849   SET_BIT(RCC_C2->APB1LENR, Periphs);
05850   /* Delay after an RCC peripheral clock enabling */
05851   tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
05852   (void)tmpreg;
05853 }
05854
05855 /**
05856   * @brief  Check if C2 APB1 peripheral clock is enabled or not
05857   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05858   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05859   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05860   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05861   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05862   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05863   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05864   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05865   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05866   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n
05867   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05868   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05869   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05870   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n
05871   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n
05872   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n
05873   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05874   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05875   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05876   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05877   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
05878   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n
05879   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05880   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n
05881   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock
05882   * @param  Periphs This parameter can be a combination of the following values:
05883   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
05884   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
05885   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
05886   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
05887   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
05888   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
05889   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
05890   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
05891   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
05892   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
05893   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
05894   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
05895   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
05896   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
05897   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
05898   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
05899   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
05900   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
05901   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
05902   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
05903   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
05904   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
05905   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
05906   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
05907   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
05908   * @retval uint32_t
05909 */
05910 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
05911 {
05912   return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
05913 }
05914
05915 /**
05916   * @brief  Disable C2 APB1 peripherals clock.
05917   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
05918   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n
05919   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n
05920   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n
05921   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n
05922   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n
05923   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n
05924   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n
05925   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n
05926   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n
05927   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n
05928   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
05929   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n
05930   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n
05931   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n
05932   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n
05933   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n
05934   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n
05935   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
05936   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n
05937   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
05938   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n
05939   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n
05940   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n
05941   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock
05942   * @param  Periphs This parameter can be a combination of the following values:
05943   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
05944   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
05945   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
05946   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
05947   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
05948   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
05949   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
05950   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
05951   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
05952   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
05953   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
05954   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
05955   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
05956   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
05957   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
05958   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
05959   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
05960   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
05961   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
05962   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
05963   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
05964   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
05965   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
05966   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
05967   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
05968   * @retval None
05969 */
05970 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
05971 {
05972   CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
05973 }
05974
05975 /**
05976   * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
05977   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05978   *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05979   *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05980   *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05981   *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05982   *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05983   *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05984   *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05985   *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05986   *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
05987   *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05988   *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05989   *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05990   *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n
05991   *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
05992   *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
05993   *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05994   *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
05995   *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05996   *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05997   *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
05998   *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n
05999   *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
06000   *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
06001   *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep
06002   * @param  Periphs This parameter can be a combination of the following values:
06003   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
06004   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
06005   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
06006   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
06007   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
06008   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
06009   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
06010   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
06011   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
06012   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
06013   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
06014   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
06015   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
06016   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
06017   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
06018   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
06019   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
06020   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
06021   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
06022   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
06023   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
06024   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
06025   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
06026   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
06027   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
06028   * @retval None
06029 */
06030 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
06031 {
06032   __IO uint32_t tmpreg;
06033   SET_BIT(RCC_C2->APB1LLPENR, Periphs);
06034   /* Delay after an RCC peripheral clock enabling */
06035   tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
06036   (void)tmpreg;
06037 }
06038
06039 /**
06040   * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
06041   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06042   *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06043   *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06044   *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06045   *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06046   *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06047   *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06048   *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06049   *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06050   *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
06051   *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06052   *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06053   *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06054   *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n
06055   *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
06056   *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
06057   *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06058   *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06059   *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06060   *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06061   *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
06062   *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n
06063   *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06064   *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
06065   *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep
06066   * @param  Periphs This parameter can be a combination of the following values:
06067   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
06068   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
06069   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
06070   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
06071   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
06072   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
06073   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
06074   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
06075   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
06076   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
06077   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
06078   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
06079   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
06080   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
06081   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
06082   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
06083   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
06084   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
06085   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
06086   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
06087   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
06088   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
06089   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
06090   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
06091   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
06092   * @retval None
06093 */
06094 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
06095 {
06096   CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
06097 }
06098
06099 /**
06100   * @brief  Enable C2 APB1 peripherals clock.
06101   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n
06102   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n
06103   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n
06104   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n
06105   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock
06106   * @param  Periphs This parameter can be a combination of the following values:
06107   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
06108   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
06109   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
06110   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
06111   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
06112   * @retval None
06113 */
06114 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
06115 {
06116   __IO uint32_t tmpreg;
06117   SET_BIT(RCC_C2->APB1HENR, Periphs);
06118   /* Delay after an RCC peripheral clock enabling */
06119   tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
06120   (void)tmpreg;
06121 }
06122
06123 /**
06124   * @brief  Check if C2 APB1 peripheral clock is enabled or not
06125   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n
06126   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n
06127   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n
06128   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n
06129   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock
06130   * @param  Periphs This parameter can be a combination of the following values:
06131   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
06132   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
06133   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
06134   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
06135   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
06136   * @retval uint32_t
06137 */
06138 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
06139 {
06140   return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
06141 }
06142
06143 /**
06144   * @brief  Disable C2 APB1 peripherals clock.
06145   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n
06146   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n
06147   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n
06148   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n
06149   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock
06150   * @param  Periphs This parameter can be a combination of the following values:
06151   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
06152   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
06153   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
06154   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
06155   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
06156   * @retval None
06157 */
06158 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
06159 {
06160   CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
06161 }
06162
06163 /**
06164   * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
06165   * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n
06166   *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
06167   *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
06168   *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
06169   *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep
06170   * @param  Periphs This parameter can be a combination of the following values:
06171   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
06172   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
06173   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
06174   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
06175   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
06176   * @retval None
06177 */
06178 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
06179 {
06180   __IO uint32_t tmpreg;
06181   SET_BIT(RCC_C2->APB1HLPENR, Periphs);
06182   /* Delay after an RCC peripheral clock enabling */
06183   tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
06184   (void)tmpreg;
06185 }
06186
06187 /**
06188   * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
06189   * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n
06190   *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
06191   *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
06192   *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
06193   *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep
06194   * @param  Periphs This parameter can be a combination of the following values:
06195   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
06196   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
06197   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
06198   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
06199   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
06200   * @retval None
06201 */
06202 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
06203 {
06204   CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
06205 }
06206
06207 /**
06208   * @}
06209   */
06210
06211 /** @defgroup BUS_LL_EF_APB2 APB2
06212   * @{
06213   */
06214
06215 /**
06216   * @brief  Enable C2 APB2 peripherals clock.
06217   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
06218   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n
06219   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n
06220   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n
06221   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
06222   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n
06223   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n
06224   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
06225   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
06226   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n
06227   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n
06228   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n
06229   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n
06230   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n
06231   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock
06232   * @param  Periphs This parameter can be a combination of the following values:
06233   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
06234   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
06235   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
06236   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
06237   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
06238   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
06239   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
06240   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
06241   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
06242   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
06243   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
06244   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
06245   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
06246   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
06247   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
06248   * @retval None
06249 */
06250 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
06251 {
06252   __IO uint32_t tmpreg;
06253   SET_BIT(RCC_C2->APB2ENR, Periphs);
06254   /* Delay after an RCC peripheral clock enabling */
06255   tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
06256   (void)tmpreg;
06257 }
06258
06259 /**
06260   * @brief  Check if C2 APB2 peripheral clock is enabled or not
06261   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06262   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06263   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
06264   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n
06265   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06266   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06267   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n
06268   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
06269   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
06270   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06271   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06272   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06273   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n
06274   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
06275   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock
06276   * @param  Periphs This parameter can be a combination of the following values:
06277   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
06278   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
06279   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
06280   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
06281   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
06282   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
06283   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
06284   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
06285   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
06286   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
06287   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
06288   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
06289   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
06290   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
06291   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
06292   * @retval uint32_t
06293 */
06294 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
06295 {
06296   return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
06297 }
06298
06299 /**
06300   * @brief  Disable C2 APB2 peripherals clock.
06301   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
06302   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n
06303   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n
06304   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n
06305   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
06306   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n
06307   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n
06308   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
06309   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
06310   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n
06311   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n
06312   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n
06313   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n
06314   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n
06315   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock
06316   * @param  Periphs This parameter can be a combination of the following values:
06317   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
06318   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
06319   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
06320   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
06321   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
06322   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
06323   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
06324   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
06325   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
06326   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
06327   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
06328   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
06329   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
06330   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
06331   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
06332   * @retval None
06333 */
06334 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
06335 {
06336   CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
06337 }
06338
06339 /**
06340   * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
06341   * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06342   *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06343   *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
06344   *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
06345   *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06346   *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06347   *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
06348   *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
06349   *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
06350   *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06351   *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06352   *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06353   *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
06354   *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
06355   *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep
06356   * @param  Periphs This parameter can be a combination of the following values:
06357   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
06358   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
06359   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
06360   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
06361   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
06362   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
06363   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
06364   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
06365   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
06366   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
06367   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
06368   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
06369   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
06370   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
06371   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
06372   * @retval None
06373 */
06374 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
06375 {
06376   __IO uint32_t tmpreg;
06377   SET_BIT(RCC_C2->APB2LPENR, Periphs);
06378   /* Delay after an RCC peripheral clock enabling */
06379   tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
06380   (void)tmpreg;
06381 }
06382
06383 /**
06384   * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
06385   * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06386   *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06387   *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
06388   *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
06389   *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06390   *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06391   *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
06392   *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
06393   *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
06394   *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06395   *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06396   *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06397   *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
06398   *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
06399   *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep
06400   * @param  Periphs This parameter can be a combination of the following values:
06401   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
06402   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
06403   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
06404   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
06405   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
06406   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
06407   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
06408   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
06409   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
06410   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
06411   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
06412   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
06413   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
06414   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
06415   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
06416   * @retval None
06417 */
06418 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
06419 {
06420   CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
06421 }
06422
06423 /**
06424   * @}
06425   */
06426
06427 /** @defgroup BUS_LL_EF_APB4 APB4
06428   * @{
06429   */
06430
06431 /**
06432   * @brief  Enable C2 APB4 peripherals clock.
06433   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n
06434   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n
06435   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n
06436   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n
06437   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n
06438   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n
06439   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n
06440   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n
06441   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n
06442   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n
06443   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n
06444   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock
06445   * @param  Periphs This parameter can be a combination of the following values:
06446   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
06447   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
06448   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
06449   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
06450   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
06451   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
06452   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
06453   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
06454   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
06455   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
06456   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
06457   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
06458   * @retval None
06459 */
06460 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
06461 {
06462   __IO uint32_t tmpreg;
06463   SET_BIT(RCC_C2->APB4ENR, Periphs);
06464   /* Delay after an RCC peripheral clock enabling */
06465   tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
06466   (void)tmpreg;
06467 }
06468
06469 /**
06470   * @brief  Check if C2 APB4 peripheral clock is enabled or not
06471   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n
06472   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n
06473   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n
06474   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n
06475   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n
06476   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n
06477   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n
06478   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n
06479   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n
06480   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n
06481   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n
06482   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock
06483   * @param  Periphs This parameter can be a combination of the following values:
06484   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
06485   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
06486   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
06487   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
06488   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
06489   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
06490   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
06491   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
06492   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
06493   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
06494   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
06495   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
06496   * @retval uint32_t
06497 */
06498 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
06499 {
06500   return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
06501 }
06502
06503 /**
06504   * @brief  Disable C2 APB4 peripherals clock.
06505   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n
06506   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n
06507   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n
06508   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n
06509   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n
06510   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n
06511   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n
06512   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n
06513   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n
06514   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n
06515   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n
06516   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock
06517   * @param  Periphs This parameter can be a combination of the following values:
06518   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
06519   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
06520   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
06521   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
06522   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
06523   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
06524   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
06525   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
06526   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
06527   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
06528   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
06529   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
06530   * @retval None
06531 */
06532 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
06533 {
06534   CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
06535 }
06536
06537 /**
06538   * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
06539   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06540   *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n
06541   *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
06542   *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
06543   *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06544   *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06545   *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06546   *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06547   *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06548   *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
06549   *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
06550   *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep
06551   * @param  Periphs This parameter can be a combination of the following values:
06552   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
06553   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
06554   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
06555   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
06556   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
06557   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
06558   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
06559   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
06560   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
06561   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
06562   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
06563   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
06564   * @retval None
06565 */
06566 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
06567 {
06568   __IO uint32_t tmpreg;
06569   SET_BIT(RCC_C2->APB4LPENR, Periphs);
06570   /* Delay after an RCC peripheral clock enabling */
06571   tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
06572   (void)tmpreg;
06573 }
06574
06575 /**
06576   * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
06577   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06578   *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n
06579   *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
06580   *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
06581   *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06582   *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06583   *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06584   *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06585   *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06586   *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
06587   *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
06588   *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep
06589   * @param  Periphs This parameter can be a combination of the following values:
06590   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
06591   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
06592   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
06593   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
06594   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
06595   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
06596   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
06597   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
06598   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
06599   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
06600   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
06601   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
06602   * @retval None
06603 */
06604 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
06605 {
06606   CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
06607 }
06608
06609 /**
06610   * @}
06611   */
06612
06613 #endif /*DUAL_CORE*/
06614
06615 /**
06616   * @}
06617   */
06618
06619 /**
06620   * @}
06621   */
06622
06623 #endif /* defined(RCC) */
06624
06625 /**
06626   * @}
06627   */
06628
06629 #ifdef __cplusplus
06630 }
06631 #endif
06632
06633 #endif /* STM32H7xx_LL_BUS_H */
06634
06635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_comp.c Source File

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stm32h7xx_ll_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_comp.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025  #include "stm32_assert.h"
00026 #else
00027  #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (COMP1) || defined (COMP2)
00035
00036 /** @addtogroup COMP_LL COMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /** @addtogroup COMP_LL_Private_Macros
00046   * @{
00047   */
00048
00049 /* Check of parameters for configuration of COMP hierarchical scope:          */
00050 /* COMP instance.                                                             */
00051
00052 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00053   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00054    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00055    || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
00056   )
00057
00058 /* Note: On this STM32 serie, comparator input plus parameters are            */
00059 /*       the same on all COMP instances.                                      */
00060 /*       However, comparator instance kept as macro parameter for             */
00061 /*       compatibility with other STM32 families.                             */
00062 #if defined (COMP_CFGRx_INP2SEL)
00063 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00064   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00065    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00066    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC2_CH1))
00067 #else
00068 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00069   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00070    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2))
00071 #endif
00072
00073 /* Note: On this STM32 serie, comparator input minus parameters are           */
00074 /*       the same on all COMP instances.                                      */
00075 /*       However, comparator instance kept as macro parameter for             */
00076 /*       compatibility with other STM32 families.                             */
00077 #if defined (COMP_CFGRx_INMSEL_3)
00078 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00079   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00080    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00081    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00082    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00083    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00084    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00085    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00086    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00087    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1)                \
00088    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VBAT_VDDAP))
00089 #else
00090 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00091   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00092    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00093    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00094    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00095    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00096    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00097    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00098    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2))
00099 #endif
00100
00101 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00102   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00103    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00104    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00105    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00106   )
00107
00108 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00109   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00110    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00111   )
00112
00113 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
00114   (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
00115    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
00116    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
00117    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3)           \
00118    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4)           \
00119    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5)           \
00120    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)          \
00121   )
00122
00123 /**
00124   * @}
00125   */
00126
00127
00128 /* Private function prototypes -----------------------------------------------*/
00129
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @addtogroup COMP_LL_Exported_Functions
00132   * @{
00133   */
00134
00135 /** @addtogroup COMP_LL_EF_Init
00136   * @{
00137   */
00138
00139 /**
00140   * @brief  De-initialize registers of the selected COMP instance
00141   *         to their default reset values.
00142   * @note   If comparator is locked, de-initialization by software is
00143   *         not possible.
00144   *         The only way to unlock the comparator is a device hardware reset.
00145   * @param  COMPx COMP instance
00146   * @retval An ErrorStatus enumeration value:
00147   *          - SUCCESS: COMP registers are de-initialized
00148   *          - ERROR: COMP registers are not de-initialized
00149   */
00150 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00151 {
00152   ErrorStatus status = SUCCESS;
00153
00154   /* Check the parameters */
00155   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00156
00157   /* Note: Hardware constraint (refer to description of this function):       */
00158   /*       COMP instance must not be locked.                                  */
00159   if(LL_COMP_IsLocked(COMPx) == 0UL)
00160   {
00161     LL_COMP_WriteReg((COMPx), CFGR, 0x00000000UL);
00162
00163   }
00164   else
00165   {
00166     /* Comparator instance is locked: de-initialization by software is         */
00167     /* not possible.                                                           */
00168     /* The only way to unlock the comparator is a device hardware reset.       */
00169     status = ERROR;
00170   }
00171
00172   return status;
00173 }
00174
00175 /**
00176   * @brief  Initialize some features of COMP instance.
00177   * @note   This function configures features of the selected COMP instance.
00178   *         Some features are also available at scope COMP common instance
00179   *         (common to several COMP instances).
00180   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00181   * @param  COMPx COMP instance
00182   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00183   * @retval An ErrorStatus enumeration value:
00184   *          - SUCCESS: COMP registers are initialized
00185   *          - ERROR: COMP registers are not initialized
00186   */
00187 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00188 {
00189   ErrorStatus status = SUCCESS;
00190
00191   /* Check the parameters */
00192   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00193   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00194   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00195   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00196   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00197   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00198   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
00199
00200   /* Note: Hardware constraint (refer to description of this function)        */
00201   /*       COMP instance must not be locked.                                  */
00202   if(LL_COMP_IsLocked(COMPx) == 0UL)
00203   {
00204     /* Configuration of comparator instance :                                 */
00205     /*  - PowerMode                                                           */
00206     /*  - InputPlus                                                           */
00207     /*  - InputMinus                                                          */
00208     /*  - InputHysteresis                                                     */
00209     /*  - OutputPolarity                                                      */
00210     /*  - OutputBlankingSource                                                */
00211 #if defined (COMP_CFGRx_INP2SEL)
00212     MODIFY_REG(COMPx->CFGR,
00213                  COMP_CFGRx_PWRMODE
00214                | COMP_CFGRx_INPSEL
00215                | COMP_CFGRx_INP2SEL
00216                | COMP_CFGRx_SCALEN
00217                | COMP_CFGRx_BRGEN
00218                | COMP_CFGRx_INMSEL
00219                | COMP_CFGRx_HYST
00220                | COMP_CFGRx_POLARITY
00221                | COMP_CFGRx_BLANKING
00222               ,
00223                  COMP_InitStruct->PowerMode
00224                | COMP_InitStruct->InputPlus
00225                | COMP_InitStruct->InputMinus
00226                | COMP_InitStruct->InputHysteresis
00227                | COMP_InitStruct->OutputPolarity
00228                | COMP_InitStruct->OutputBlankingSource
00229               );
00230 #else
00231     MODIFY_REG(COMPx->CFGR,
00232                  COMP_CFGRx_PWRMODE
00233                | COMP_CFGRx_INPSEL
00234                | COMP_CFGRx_SCALEN
00235                | COMP_CFGRx_BRGEN
00236                | COMP_CFGRx_INMSEL
00237                | COMP_CFGRx_HYST
00238                | COMP_CFGRx_POLARITY
00239                | COMP_CFGRx_BLANKING
00240               ,
00241                  COMP_InitStruct->PowerMode
00242                | COMP_InitStruct->InputPlus
00243                | COMP_InitStruct->InputMinus
00244                | COMP_InitStruct->InputHysteresis
00245                | COMP_InitStruct->OutputPolarity
00246                | COMP_InitStruct->OutputBlankingSource
00247               );
00248 #endif
00249   }
00250   else
00251   {
00252     /* Initialization error: COMP instance is locked.                         */
00253     status = ERROR;
00254   }
00255
00256   return status;
00257 }
00258
00259 /**
00260   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00261   * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00262   *                        whose fields will be set to default values.
00263   * @retval None
00264   */
00265 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00266 {
00267   /* Set COMP_InitStruct fields to default values */
00268   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
00269   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00270   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00271   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00272   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00273   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00274 }
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 #endif /* COMP1 || COMP2 */
00289
00290 /**
00291   * @}
00292   */
00293
00294 #endif /* USE_FULL_LL_DRIVER */
00295
00296 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_comp.h Source File

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stm32h7xx_ll_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_LL_COMP_H
00022 #define __STM32H7xx_LL_COMP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (COMP1) || defined (COMP2)
00036
00037 /** @defgroup COMP_LL COMP
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
00045   * @{
00046   */
00047
00048 /* COMP registers bits positions */
00049 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
00050
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056 /* Exported types ------------------------------------------------------------*/
00057 #if defined(USE_FULL_LL_DRIVER)
00058 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Structure definition of some features of COMP instance.
00064   */
00065 typedef struct
00066 {
00067   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
00068                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
00069
00070                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
00071
00072   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00073                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00074
00075                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
00076
00077   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00078                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00079
00080                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
00081
00082   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00083                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00084
00085                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
00086
00087   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00088                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00089
00090                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
00091
00092   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00093                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00094
00095                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
00096
00097 } LL_COMP_InitTypeDef;
00098
00099 /**
00100   * @}
00101   */
00102 #endif /* USE_FULL_LL_DRIVER */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
00110   * @{
00111   */
00112 #define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000UL)          /*!< Window mode disable: Comparators 1 and 2 are independent */
00113 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)    /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
00119   * @{
00120   */
00121 #define LL_COMP_POWERMODE_HIGHSPEED     (0x00000000UL)                                /*!< COMP power mode to high speed */
00122 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CFGRx_PWRMODE_0)                        /*!< COMP power mode to medium speed */
00123 #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE_1 | COMP_CFGRx_PWRMODE_0) /*!< COMP power mode to ultra-low power */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00129   * @{
00130   */
00131 #define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                           /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
00132 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CFGRx_INPSEL)                      /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
00133 #if defined (COMP_CFGRx_INP2SEL)
00134 #define LL_COMP_INPUT_PLUS_DAC2_CH1     (COMP_CFGRx_INP2SEL)                     /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1)                      */
00135 #endif
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00141   * @{
00142   */
00143 #define LL_COMP_INPUT_MINUS_1_4VREFINT      (                                                                                        COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 1/4 VrefInt  */
00144 #define LL_COMP_INPUT_MINUS_1_2VREFINT      (                                                                  COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 1/2 VrefInt  */
00145 #define LL_COMP_INPUT_MINUS_3_4VREFINT      (                                            COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 3/4 VrefInt  */
00146 #define LL_COMP_INPUT_MINUS_VREFINT         (                                            COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                   )   /*!< Comparator input minus connected to VrefInt */
00147 #define LL_COMP_INPUT_MINUS_DAC1_CH1        (                      COMP_CFGRx_INMSEL_2                                                                                   )   /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
00148 #define LL_COMP_INPUT_MINUS_DAC1_CH2        (                      COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
00149 #define LL_COMP_INPUT_MINUS_IO1             (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                                                             )   /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
00150 #define LL_COMP_INPUT_MINUS_IO2             (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
00151 #if defined (COMP_CFGRx_INMSEL_3)
00152 #define LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1  (COMP_CFGRx_INMSEL_3                                                                                                         )   /*!< Comparator input minus connected to  (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */
00153 #define LL_COMP_INPUT_MINUS_VBAT_VDDAP      (COMP_CFGRx_INMSEL_3                                             | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to  (VBAT/4 for COMP1, VDDAP for COMP2) */
00154 #endif
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00160   * @{
00161   */
00162 #define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                            /*!< No hysteresis */
00163 #define LL_COMP_HYSTERESIS_LOW          (                    COMP_CFGRx_HYST_0)   /*!< Hysteresis level low */
00164 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CFGRx_HYST_1                    )   /*!< Hysteresis level medium */
00165 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CFGRx_HYST_1 | COMP_CFGRx_HYST_0)   /*!< Hysteresis level high */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00171   * @{
00172   */
00173 #define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00174 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CFGRx_POLARITY)   /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00180   * @{
00181   */
00182 #define LL_COMP_BLANKINGSRC_NONE      (0x00000000UL)                                  /*!<Comparator output without blanking */
00183 #define LL_COMP_BLANKINGSRC_TIM1_OC5  (COMP_CFGRx_BLANKING_0)                         /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
00184 #define LL_COMP_BLANKINGSRC_TIM2_OC3  (COMP_CFGRx_BLANKING_1)                         /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
00185 #define LL_COMP_BLANKINGSRC_TIM3_OC3  (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)  /*!< Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2) */
00186 #define LL_COMP_BLANKINGSRC_TIM3_OC4  (COMP_CFGRx_BLANKING_2)                         /*!< Comparator output blanking source TIM3 OC4 (common to all COMP instances: COMP1, COMP2) */
00187 #define LL_COMP_BLANKINGSRC_TIM8_OC5  (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (common to all COMP instances: COMP1, COMP2) */
00188 #define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)   /*!< Comparator output blanking source TIM15 OC1 (common to all COMP instances: COMP1, COMP2) */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00194   * @{
00195   */
00196 #define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)           /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00197 #define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)           /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00198 /**
00199   * @}
00200   */
00201 /** @defgroup COMP_LL_EC_OUTPUT_BKIN_TIMER Comparator output - Output to BKIN timer
00202   * @{
00203   */
00204 #define LL_COMP_AF_PA6          COMP_OR_AFOPA6       /*!< Comparator Alternate Function PA6 source selected to timer BKIN input  */
00205 #define LL_COMP_AF_PA8          COMP_OR_AFOPA8       /*!< Comparator Alternate Function PA8 source selected to timer BKIN input  */
00206 #define LL_COMP_AF_PB12         COMP_OR_AFOPB12      /*!< Comparator Alternate Function PB12 source selected to timer BKIN input */
00207 #define LL_COMP_AF_PE6          COMP_OR_AFOPE6       /*!< Comparator Alternate Function PE6 source selected to timer BKIN input  */
00208 #define LL_COMP_AF_PE15         COMP_OR_AFOPE15      /*!< Comparator Alternate Function PE15 source selected to timer BKIN input */
00209 #define LL_COMP_AF_PG2          COMP_OR_AFOPG2       /*!< Comparator Alternate Function PG2 source selected to timer BKIN input  */
00210 #define LL_COMP_AF_PG3          COMP_OR_AFOPG3       /*!< Comparator Alternate Function PG3 source selected to timer BKIN input  */
00211 #define LL_COMP_AF_PG4          COMP_OR_AFOPG4       /*!< Comparator Alternate Function PG4 source selected to timer BKIN input  */
00212 #define LL_COMP_AF_PI1          COMP_OR_AFOPI1       /*!< Comparator Alternate Function PI1 source selected to timer BKIN input  */
00213 #define LL_COMP_AF_PI4          COMP_OR_AFOPI4       /*!< Comparator Alternate Function PI4 source selected to timer BKIN input  */
00214 #define LL_COMP_AF_PK2          COMP_OR_AFOPK2       /*!< Comparator Alternate Function PK2 source selected to timer BKIN input  */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00220   * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
00221   *         not timeout values.
00222   *         For details on delays values, refer to descriptions in source code
00223   *         above each literal definition.
00224   * @{
00225   */
00226
00227 /* Delay for comparator startup time.                                         */
00228 /* Note: Delay required to reach propagation delay specification.             */
00229 /* Literal set to maximum value (refer to device datasheet,                   */
00230 /* parameter "tSTART").                                                       */
00231 /* Unit: us                                                                   */
00232 #define LL_COMP_DELAY_STARTUP_US          ( 80UL)  /*!< Delay for COMP startup time */
00233
00234 /* Delay for comparator voltage scaler stabilization time.                    */
00235 /* Note: Voltage scaler is used when selecting comparator input               */
00236 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00237 /* Literal set to maximum value (refer to device datasheet,                   */
00238 /* parameter "tSTART_SCALER").                                                */
00239 /* Unit: us                                                                   */
00240 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)  /*!< Delay for COMP voltage scaler stabilization time */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /* Exported macro ------------------------------------------------------------*/
00251 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00252   * @{
00253   */
00254 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Write a value in COMP register
00260   * @param  __INSTANCE__ comparator instance
00261   * @param  __REG__ Register to be written
00262   * @param  __VALUE__ Value to be written in the register
00263   * @retval None
00264   */
00265 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00266
00267 /**
00268   * @brief  Read a value in COMP register
00269   * @param  __INSTANCE__ comparator instance
00270   * @param  __REG__ Register to be read
00271   * @retval Register value
00272   */
00273 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00279   * @{
00280   */
00281
00282 /**
00283   * @brief  Helper macro to select the COMP common instance
00284   *         to which is belonging the selected COMP instance.
00285   * @note   COMP common register instance can be used to
00286   *         set parameters common to several COMP instances.
00287   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00288   * @param  __COMPx__ COMP instance
00289   * @retval COMP common instance or value "0" if there is no COMP common instance.
00290   */
00291 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00292   (COMP12_COMMON)
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /* Exported functions --------------------------------------------------------*/
00303 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00304   * @{
00305   */
00306
00307 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
00308   * @{
00309   */
00310
00311 /**
00312   * @brief  Set window mode of a pair of comparators instances
00313   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00314   * @rmtoll CFGRx    WINMODE        LL_COMP_SetCommonWindowMode
00315   * @param  COMPxy_COMMON Comparator common instance
00316   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00317   * @param  WindowMode This parameter can be one of the following values:
00318   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00319   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00320   * @retval None
00321   */
00322 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
00323 {
00324   /* Note: On this STM32 serie, window mode can be set only                   */
00325   /*       from COMP instance: COMP2.                                         */
00326   MODIFY_REG(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE, WindowMode);
00327 }
00328
00329 /**
00330   * @brief  Get window mode of a pair of comparators instances
00331   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00332   * @rmtoll CFGRx    WINMODE        LL_COMP_GetCommonWindowMode
00333   * @param  COMPxy_COMMON Comparator common instance
00334   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00335   * @retval Returned value can be one of the following values:
00336   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00337   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00338   */
00339 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
00340 {
00341   return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE));
00342 }
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Set comparator instance operating mode to adjust power and speed.
00354   * @rmtoll CFGRx    PWRMODE        LL_COMP_SetPowerMode
00355   * @param  COMPx Comparator instance
00356   * @param  PowerMode This parameter can be one of the following values:
00357   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00358   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00359   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00360   * @retval None
00361   */
00362 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
00363 {
00364   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_PWRMODE, PowerMode);
00365 }
00366
00367 /**
00368   * @brief  Get comparator instance operating mode to adjust power and speed.
00369   * @rmtoll CFGRx    PWRMODE        LL_COMP_GetPowerMode
00370   * @param  COMPx Comparator instance
00371   * @retval Returned value can be one of the following values:
00372   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00373   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00374   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00375   */
00376 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
00377 {
00378   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE));
00379 }
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00386   * @{
00387   */
00388
00389 /**
00390   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00391   * @note   In case of comparator input selected to be connected to IO:
00392   *         GPIO pins are specific to each comparator instance.
00393   *         Refer to description of parameters or to reference manual.
00394   * @note   On this STM32 serie, scaler bridge is configurable:
00395   *         to optimize power consumption, this function enables the
00396   *         voltage scaler bridge only when required
00397   *         (when selecting comparator input based on VrefInt: VrefInt or
00398   *         subdivision of VrefInt).
00399   *         - For scaler bridge power consumption values,
00400   *           refer to device datasheet, parameter "IDDA(SCALER)".
00401   *         - Voltage scaler requires a delay for voltage stabilization.
00402   *           Refer to device datasheet, parameter "tSTART_SCALER".
00403   *         - Scaler bridge is common for all comparator instances,
00404   *           therefore if at least one of the comparator instance
00405   *           is requiring the scaler bridge, it remains enabled.
00406   * @rmtoll CFGRx      INMSEL         LL_COMP_ConfigInputs\n
00407   *         CFGRx      INPSEL         LL_COMP_ConfigInputs\n
00408   *         CFGRx      BRGEN          LL_COMP_ConfigInputs\n
00409   *         CFGRx      SCALEN         LL_COMP_ConfigInputs
00410   * @param  COMPx Comparator instance
00411   * @param  InputMinus This parameter can be one of the following values:
00412   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00413   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00414   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00415   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00416   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00417   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00418   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00419   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00420 #if defined (COMP_CFGRx_INMSEL_3)
00421   *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
00422   *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
00423 #endif
00424   * @param  InputPlus This parameter can be one of the following values:
00425   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00426   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00427 #if defined (COMP_CFGRx_INP2SEL)
00428   *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
00429 #endif
00430   * @retval None
00431   */
00432 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00433 {
00434 #if defined (COMP_CFGRx_INP2SEL)
00435   MODIFY_REG(COMPx->CFGR,
00436              COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
00437              COMP_CFGRx_INP2SEL |
00438              COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN,
00439              InputMinus | InputPlus);
00440 #else
00441   MODIFY_REG(COMPx->CFGR,
00442              COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
00443              COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN,
00444              InputMinus | InputPlus);
00445 #endif
00446 }
00447
00448 /**
00449   * @brief  Set comparator input plus (non-inverting).
00450   * @note   In case of comparator input selected to be connected to IO:
00451   *         GPIO pins are specific to each comparator instance.
00452   *         Refer to description of parameters or to reference manual.
00453   * @rmtoll CFGRx    INPSEL         LL_COMP_SetInputPlus
00454   * @param  COMPx Comparator instance
00455   * @param  InputPlus This parameter can be one of the following values:
00456   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00457   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00458 #if defined (COMP_CFGRx_INP2SEL)
00459   *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
00460 #endif
00461   * @retval None
00462   */
00463 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00464 {
00465 #if defined (COMP_CFGRx_INP2SEL)
00466   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL , InputPlus);
00467 #else
00468   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INPSEL , InputPlus);
00469 #endif
00470 }
00471
00472 /**
00473   * @brief  Get comparator input plus (non-inverting).
00474   * @note   In case of comparator input selected to be connected to IO:
00475   *         GPIO pins are specific to each comparator instance.
00476   *         Refer to description of parameters or to reference manual.
00477   * @rmtoll CFGRx    INPSEL         LL_COMP_GetInputPlus
00478   * @param  COMPx Comparator instance
00479   * @retval Returned value can be one of the following values:
00480   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00481   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00482 #if defined (COMP_CFGRx_INP2SEL)
00483   *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
00484 #endif
00485   */
00486 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
00487 {
00488 #if defined (COMP_CFGRx_INP2SEL)
00489   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL));
00490 #else
00491   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL));
00492 #endif
00493 }
00494
00495 /**
00496   * @brief  Set comparator input minus (inverting).
00497   * @note   In case of comparator input selected to be connected to IO:
00498   *         GPIO pins are specific to each comparator instance.
00499   *         Refer to description of parameters or to reference manual.
00500   * @note   On this STM32 serie, scaler bridge is configurable:
00501   *         to optimize power consumption, this function enables the
00502   *         voltage scaler bridge only when required
00503   *         (when selecting comparator input based on VrefInt: VrefInt or
00504   *         subdivision of VrefInt).
00505   *         - For scaler bridge power consumption values,
00506   *           refer to device datasheet, parameter "IDDA(SCALER)".
00507   *         - Voltage scaler requires a delay for voltage stabilization.
00508   *           Refer to device datasheet, parameter "tSTART_SCALER".
00509   *         - Scaler bridge is common for all comparator instances,
00510   *           therefore if at least one of the comparator instance
00511   *           is requiring the scaler bridge, it remains enabled.
00512   * @rmtoll CFGRx     INMSEL         LL_COMP_SetInputMinus\n
00513   *         CFGRx     BRGEN          LL_COMP_SetInputMinus\n
00514   *         CFGRx     SCALEN         LL_COMP_SetInputMinus
00515   * @param  COMPx Comparator instance
00516   * @param  InputMinus This parameter can be one of the following values:
00517   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00518   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00519   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00520   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00521   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00522   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00523   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00524   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00525 #if defined (COMP_CFGRx_INMSEL_3)
00526   *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
00527   *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
00528 #endif
00529   * @retval None
00530   */
00531 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00532 {
00533   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN, InputMinus);
00534 }
00535
00536 /**
00537   * @brief  Get comparator input minus (inverting).
00538   * @note   In case of comparator input selected to be connected to IO:
00539   *         GPIO pins are specific to each comparator instance.
00540   *         Refer to description of parameters or to reference manual.
00541   * @rmtoll CFGRx     INMSEL         LL_COMP_GetInputMinus\n
00542   *         CFGRx     BRGEN          LL_COMP_GetInputMinus\n
00543   *         CFGRx     SCALEN         LL_COMP_GetInputMinus
00544   * @param  COMPx Comparator instance
00545   * @retval Returned value can be one of the following values:
00546   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00547   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00548   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00549   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00550   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00551   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00552   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00553   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00554 #if defined (COMP_CFGRx_INMSEL_3)
00555   *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
00556   *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
00557 #endif
00558   */
00559 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
00560 {
00561   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN));
00562 }
00563
00564 /**
00565   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
00566   * @rmtoll CFGRx    HYST           LL_COMP_SetInputHysteresis
00567   * @param  COMPx Comparator instance
00568   * @param  InputHysteresis This parameter can be one of the following values:
00569   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00570   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00571   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00572   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00573   * @retval None
00574   */
00575 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
00576 {
00577   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_HYST, InputHysteresis);
00578 }
00579
00580 /**
00581   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
00582   * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
00583   * @param  COMPx Comparator instance
00584   * @retval Returned value can be one of the following values:
00585   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00586   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00587   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00588   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00589   */
00590 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
00591 {
00592   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST));
00593 }
00594
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
00600   * @{
00601   */
00602
00603 /**
00604   * @brief  Set comparator instance output polarity.
00605   * @rmtoll CFGRx    POLARITY       LL_COMP_SetOutputPolarity
00606   * @param  COMPx Comparator instance
00607   * @param  OutputPolarity This parameter can be one of the following values:
00608   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00609   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00610   * @retval None
00611   */
00612 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
00613 {
00614   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_POLARITY, OutputPolarity);
00615 }
00616
00617 /**
00618   * @brief  Get comparator instance output polarity.
00619   * @rmtoll CFGRx    POLARITY       LL_COMP_GetOutputPolarity
00620   * @param  COMPx Comparator instance
00621   * @retval Returned value can be one of the following values:
00622   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00623   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00624   */
00625 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
00626 {
00627   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY));
00628 }
00629
00630 /**
00631   * @brief  Set comparator instance blanking source.
00632   * @note   Blanking source may be specific to each comparator instance.
00633   *         Refer to description of parameters or to reference manual.
00634   * @note   Availability of parameters of blanking source from timer
00635   *         depends on timers availability on the selected device.
00636   * @rmtoll CFGR     BLANKING       LL_COMP_SetOutputBlankingSource
00637   * @param  COMPx Comparator instance
00638   * @param  BlankingSource This parameter can be one of the following values:
00639   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00640   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
00641   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
00642   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
00643   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
00644   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
00645   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
00646   * @retval None
00647   */
00648 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
00649 {
00650   MODIFY_REG(COMPx->CFGR, COMP_CFGRx_BLANKING, BlankingSource);
00651 }
00652
00653 /**
00654   * @brief  Get comparator instance blanking source.
00655   * @note   Availability of parameters of blanking source from timer
00656   *         depends on timers availability on the selected device.
00657   * @note   Blanking source may be specific to each comparator instance.
00658   *         Refer to description of parameters or to reference manual.
00659   * @rmtoll CFGR     BLANKING       LL_COMP_GetOutputBlankingSource
00660   * @param  COMPx Comparator instance
00661   * @retval Returned value can be one of the following values:
00662   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00663   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
00664   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
00665   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
00666   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
00667   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
00668   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
00669   */
00670 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
00671 {
00672   return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING));
00673 }
00674
00675 /** @brief  Set the output alternate function in the Option register
00676   *         in order to be used with the alternate function
00677   *         of the timer break input.
00678   * @rmtoll OR    AFOP       COMP_LL_EC_OUTPUT_BKIN_TIMER
00679   * @param  COMPx specifies the instance.
00680   * @param  CompAFx specifies the Alternate Function source selection.
00681   *          This parameter can be one of the following values:
00682   *            @arg @ref LL_COMP_AF_PA6
00683   *            @arg @ref LL_COMP_AF_PA8
00684   *            @arg @ref LL_COMP_AF_PB12
00685   *            @arg @ref LL_COMP_AF_PE6
00686   *            @arg @ref LL_COMP_AF_PE15
00687   *            @arg @ref LL_COMP_AF_PG2
00688   *            @arg @ref LL_COMP_AF_PG3
00689   *            @arg @ref LL_COMP_AF_PG4
00690   *            @arg @ref LL_COMP_AF_PI1
00691   *            @arg @ref LL_COMP_AF_PI4
00692   *            @arg @ref LL_COMP_AF_PK2
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx)
00696 {
00697   MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx);
00698 }
00699
00700 /** @brief  Get the output alternate function from the Option register.
00701   * @rmtoll OR     AFOP       COMP_LL_EC_OUTPUT_BKIN_TIMER
00702   * @param  COMPx specifies the Comparator instance.
00703   * @retval Returned value can be one of the following values:
00704   *            @arg @ref LL_COMP_AF_PA6
00705   *            @arg @ref LL_COMP_AF_PA8
00706   *            @arg @ref LL_COMP_AF_PB12
00707   *            @arg @ref LL_COMP_AF_PE6
00708   *            @arg @ref LL_COMP_AF_PE15
00709   *            @arg @ref LL_COMP_AF_PG2
00710   *            @arg @ref LL_COMP_AF_PG3
00711   *            @arg @ref LL_COMP_AF_PG4
00712   *            @arg @ref LL_COMP_AF_PI1
00713   *            @arg @ref LL_COMP_AF_PI4
00714   *            @arg @ref LL_COMP_AF_PK2
00715   */
00716 __STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx )
00717 {
00718   return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR &  0x7FFUL));
00719 }
00720
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
00726   * @{
00727   */
00728
00729 /**
00730   * @brief  Enable comparator instance.
00731   * @note   After enable from off state, comparator requires a delay
00732   *         to reach reach propagation delay specification.
00733   *         Refer to device datasheet, parameter "tSTART".
00734   * @rmtoll CFGR     EN             LL_COMP_Enable
00735   * @param  COMPx Comparator instance
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
00739 {
00740   SET_BIT(COMPx->CFGR, COMP_CFGRx_EN);
00741 }
00742
00743 /**
00744   * @brief  Disable comparator instance.
00745   * @rmtoll CFGR     EN             LL_COMP_Disable
00746   * @param  COMPx Comparator instance
00747   * @retval None
00748   */
00749 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
00750 {
00751   CLEAR_BIT(COMPx->CFGR, COMP_CFGRx_EN);
00752 }
00753
00754 /**
00755   * @brief  Get comparator enable state
00756   *         (0: COMP is disabled, 1: COMP is enabled)
00757   * @rmtoll CFGR     EN             LL_COMP_IsEnabled
00758   * @param  COMPx Comparator instance
00759   * @retval State of bit (1 or 0).
00760   */
00761 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
00762 {
00763   return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL);
00764 }
00765
00766 /**
00767   * @brief  Lock comparator instance.
00768   * @note   Once locked, comparator configuration can be accessed in read-only.
00769   * @note   The only way to unlock the comparator is a device hardware reset.
00770   * @rmtoll CFGR     LOCK           LL_COMP_Lock
00771   * @param  COMPx Comparator instance
00772   * @retval None
00773   */
00774 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
00775 {
00776   SET_BIT(COMPx->CFGR, COMP_CFGRx_LOCK);
00777 }
00778
00779 /**
00780   * @brief  Get comparator lock state
00781   *         (0: COMP is unlocked, 1: COMP is locked).
00782   * @note   Once locked, comparator configuration can be accessed in read-only.
00783   * @note   The only way to unlock the comparator is a device hardware reset.
00784   * @rmtoll CFGR     LOCK           LL_COMP_IsLocked
00785   * @param  COMPx Comparator instance
00786   * @retval State of bit (1 or 0).
00787   */
00788 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
00789 {
00790   return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL);
00791 }
00792
00793 /**
00794   * @brief  Read comparator instance output level.
00795   * @note   The comparator output level depends on the selected polarity
00796   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
00797   *         If the comparator polarity is not inverted:
00798   *          - Comparator output is low when the input plus
00799   *            is at a lower voltage than the input minus
00800   *          - Comparator output is high when the input plus
00801   *            is at a higher voltage than the input minus
00802   *         If the comparator polarity is inverted:
00803   *          - Comparator output is high when the input plus
00804   *            is at a lower voltage than the input minus
00805   *          - Comparator output is low when the input plus
00806   *            is at a higher voltage than the input minus
00807   * @rmtoll CFGR     VALUE          LL_COMP_ReadOutputLevel
00808   * @param  COMPx Comparator instance
00809   * @retval Returned value can be one of the following values:
00810   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
00811   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
00812   */
00813 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
00814 {
00815   if (COMPx == COMP1)
00816   {
00817     return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
00818   }
00819   else
00820   {
00821     return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1);
00822   }
00823 }
00824
00825 /**
00826   * @}
00827   */
00828
00829 #if defined(USE_FULL_LL_DRIVER)
00830 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
00831   * @{
00832   */
00833
00834 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
00835 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
00836 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
00837
00838 /**
00839   * @}
00840   */
00841 #endif /* USE_FULL_LL_DRIVER */
00842
00843 /**
00844   * @}
00845   */
00846
00847 /**
00848   * @}
00849   */
00850
00851 #endif /* COMP1 || COMP2 */
00852
00853 /**
00854   * @}
00855   */
00856
00857 #ifdef __cplusplus
00858 }
00859 #endif
00860
00861 #endif /* __STM32H7xx_LL_COMP_H */
00862
00863 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_cortex.h Source File

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stm32h7xx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL CORTEX driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
00014           functions
00015       (+) Low power mode configuration (SCB register of Cortex-MCU)
00016       (+) MPU API to configure and enable regions
00017       (+) API to access to MCU info (CPUID register)
00018       (+) API to enable fault handler (SHCSR accesses)
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00025   * All rights reserved.</center></h2>
00026   *
00027   * This software component is licensed by ST under BSD 3-Clause license,
00028   * the "License"; You may not use this file except in compliance with the
00029   * License. You may obtain a copy of the License at:
00030   *                        opensource.org/licenses/BSD-3-Clause
00031   *
00032   ******************************************************************************
00033   */
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef STM32H7xx_LL_CORTEX_H
00037 #define STM32H7xx_LL_CORTEX_H
00038
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx.h"
00045
00046 /** @addtogroup STM32H7xx_LL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup CORTEX_LL CORTEX
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056
00057 /* Private constants ---------------------------------------------------------*/
00058
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /* Exported constants --------------------------------------------------------*/
00063 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00068   * @{
00069   */
00070 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00071 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00077   * @{
00078   */
00079 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00080 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00081 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00082 /**
00083   * @}
00084   */
00085
00086 #if __MPU_PRESENT
00087
00088 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00089   * @{
00090   */
00091 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
00092 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00093 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00094 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00100   * @{
00101   */
00102 #define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
00103 #define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
00104 #define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
00105 #define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
00106 #define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
00107 #define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
00108 #define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
00109 #define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
00110 #if !defined(CORE_CM4)
00111 #define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
00112 #define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
00113 #define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
00114 #define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
00115 #define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
00116 #define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
00117 #define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
00118 #define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
00119 #endif /* !defined(CORE_CM4) */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00125   * @{
00126   */
00127 #define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
00128 #define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
00129 #define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
00130 #define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00131 #define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00132 #define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00133 #define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00134 #define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00135 #define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00136 #define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00144 #define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00145 #define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00146 #define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00147 #define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00148 #define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00149 #define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00150 #define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00151 #define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00152 #define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00153 #define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00154 #define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00160   * @{
00161   */
00162 #define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
00163 #define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00164 #define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00165 #define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00166 #define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00167 #define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00173   * @{
00174   */
00175 #define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00176 #define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00177 #define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00178 #define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00184   * @{
00185   */
00186 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
00187 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00193   * @{
00194   */
00195 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00196 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00202   * @{
00203   */
00204 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00205 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00211   * @{
00212   */
00213 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00214 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
00215 /**
00216   * @}
00217   */
00218 #endif /* __MPU_PRESENT */
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported macro ------------------------------------------------------------*/
00224
00225 /* Exported functions --------------------------------------------------------*/
00226 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00227   * @{
00228   */
00229
00230 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00231   * @{
00232   */
00233
00234 /**
00235   * @brief  This function checks if the Systick counter flag is active or not.
00236   * @note   It can be used in timeout function on application side.
00237   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00238   * @retval State of bit (1 or 0).
00239   */
00240 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00241 {
00242   return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
00243 }
00244
00245 /**
00246   * @brief  Configures the SysTick clock source
00247   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00248   * @param  Source This parameter can be one of the following values:
00249   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00250   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00251   * @retval None
00252   */
00253 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00254 {
00255   MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
00256 }
00257
00258 /**
00259   * @brief  Get the SysTick clock source
00260   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00261   * @retval Returned value can be one of the following values:
00262   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00263   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00264   */
00265 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00266 {
00267   return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
00268 }
00269
00270 /**
00271   * @brief  Enable SysTick exception request
00272   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00273   * @retval None
00274   */
00275 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00276 {
00277   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00278 }
00279
00280 /**
00281   * @brief  Disable SysTick exception request
00282   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00286 {
00287   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00288 }
00289
00290 /**
00291   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00292   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00293   * @retval State of bit (1 or 0).
00294   */
00295 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00296 {
00297   return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Processor uses sleep as its low power mode
00310   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00311   * @retval None
00312   */
00313 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00314 {
00315   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00316   CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00317 }
00318
00319 /**
00320   * @brief  Processor uses deep sleep as its low power mode
00321   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00322   * @retval None
00323   */
00324 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00325 {
00326   /* Set SLEEPDEEP bit of Cortex System Control Register */
00327   SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
00328 }
00329
00330 /**
00331   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00332   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00333   *         empty main application.
00334   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00335   * @retval None
00336   */
00337 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00338 {
00339   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00340   SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
00341 }
00342
00343 /**
00344   * @brief  Do not sleep when returning to Thread mode.
00345   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00346   * @retval None
00347   */
00348 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00349 {
00350   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00351   CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
00352 }
00353
00354 /**
00355   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00356   *         processor.
00357   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00358   * @retval None
00359   */
00360 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00361 {
00362   /* Set SEVEONPEND bit of Cortex System Control Register */
00363   SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
00364 }
00365
00366 /**
00367   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00368   *         excluded
00369   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00370   * @retval None
00371   */
00372 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00373 {
00374   /* Clear SEVEONPEND bit of Cortex System Control Register */
00375   CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
00376 }
00377
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00383   * @{
00384   */
00385
00386 /**
00387   * @brief  Enable a fault in System handler control register (SHCSR)
00388   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00389   * @param  Fault This parameter can be a combination of the following values:
00390   *         @arg @ref LL_HANDLER_FAULT_USG
00391   *         @arg @ref LL_HANDLER_FAULT_BUS
00392   *         @arg @ref LL_HANDLER_FAULT_MEM
00393   * @retval None
00394   */
00395 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00396 {
00397   /* Enable the system handler fault */
00398   SET_BIT(SCB->SHCSR, Fault);
00399 }
00400
00401 /**
00402   * @brief  Disable a fault in System handler control register (SHCSR)
00403   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00404   * @param  Fault This parameter can be a combination of the following values:
00405   *         @arg @ref LL_HANDLER_FAULT_USG
00406   *         @arg @ref LL_HANDLER_FAULT_BUS
00407   *         @arg @ref LL_HANDLER_FAULT_MEM
00408   * @retval None
00409   */
00410 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00411 {
00412   /* Disable the system handler fault */
00413   CLEAR_BIT(SCB->SHCSR, Fault);
00414 }
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Get Implementer code
00426   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00427   * @retval Value should be equal to 0x41 for ARM
00428   */
00429 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00430 {
00431   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00432 }
00433
00434 /**
00435   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00436   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00437   * @retval Value between 0 and 255 (0x0: revision 0)
00438   */
00439 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00440 {
00441   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00442 }
00443
00444 /**
00445   * @brief  Get Constant number
00446   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
00447   * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
00448   */
00449 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
00450 {
00451   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00452 }
00453
00454 /**
00455   * @brief  Get Part number
00456   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00457   * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
00458   */
00459 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00460 {
00461   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00462 }
00463
00464 /**
00465   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00466   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00467   * @retval Value between 0 and 255 (0x1: patch 1)
00468   */
00469 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00470 {
00471   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00472 }
00473
00474 /**
00475   * @}
00476   */
00477
00478 #if __MPU_PRESENT
00479 /** @defgroup CORTEX_LL_EF_MPU MPU
00480   * @{
00481   */
00482
00483 /**
00484   * @brief  Enable MPU with input options
00485   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00486   * @param  Options This parameter can be one of the following values:
00487   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00488   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00489   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00490   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00491   * @retval None
00492   */
00493 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00494 {
00495   /* Enable the MPU*/
00496   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00497   /* Ensure MPU settings take effects */
00498   __DSB();
00499   /* Sequence instruction fetches using update settings */
00500   __ISB();
00501 }
00502
00503 /**
00504   * @brief  Disable MPU
00505   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00506   * @retval None
00507   */
00508 __STATIC_INLINE void LL_MPU_Disable(void)
00509 {
00510   /* Make sure outstanding transfers are done */
00511   __DMB();
00512   /* Disable MPU*/
00513   WRITE_REG(MPU->CTRL, 0U);
00514 }
00515
00516 /**
00517   * @brief  Check if MPU is enabled or not
00518   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00519   * @retval State of bit (1 or 0).
00520   */
00521 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00522 {
00523   return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
00524 }
00525
00526 /**
00527   * @brief  Enable a MPU region
00528   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00529   * @param  Region This parameter can be one of the following values:
00530   *         @arg @ref LL_MPU_REGION_NUMBER0
00531   *         @arg @ref LL_MPU_REGION_NUMBER1
00532   *         @arg @ref LL_MPU_REGION_NUMBER2
00533   *         @arg @ref LL_MPU_REGION_NUMBER3
00534   *         @arg @ref LL_MPU_REGION_NUMBER4
00535   *         @arg @ref LL_MPU_REGION_NUMBER5
00536   *         @arg @ref LL_MPU_REGION_NUMBER6
00537   *         @arg @ref LL_MPU_REGION_NUMBER7
00538   *         @arg @ref LL_MPU_REGION_NUMBER8
00539   *         @arg @ref LL_MPU_REGION_NUMBER9
00540   *         @arg @ref LL_MPU_REGION_NUMBER10
00541   *         @arg @ref LL_MPU_REGION_NUMBER11
00542   *         @arg @ref LL_MPU_REGION_NUMBER12
00543   *         @arg @ref LL_MPU_REGION_NUMBER13
00544   *         @arg @ref LL_MPU_REGION_NUMBER14
00545   *         @arg @ref LL_MPU_REGION_NUMBER15
00546   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
00547   * @retval None
00548   */
00549 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00550 {
00551   /* Set Region number */
00552   WRITE_REG(MPU->RNR, Region);
00553   /* Enable the MPU region */
00554   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00555 }
00556
00557 /**
00558   * @brief  Configure and enable a region
00559   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00560   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00561   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00562   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00563   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00564   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00565   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00566   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00567   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00568   * @param  Region This parameter can be one of the following values:
00569   *         @arg @ref LL_MPU_REGION_NUMBER0
00570   *         @arg @ref LL_MPU_REGION_NUMBER1
00571   *         @arg @ref LL_MPU_REGION_NUMBER2
00572   *         @arg @ref LL_MPU_REGION_NUMBER3
00573   *         @arg @ref LL_MPU_REGION_NUMBER4
00574   *         @arg @ref LL_MPU_REGION_NUMBER5
00575   *         @arg @ref LL_MPU_REGION_NUMBER6
00576   *         @arg @ref LL_MPU_REGION_NUMBER7
00577   *         @arg @ref LL_MPU_REGION_NUMBER8
00578   *         @arg @ref LL_MPU_REGION_NUMBER9
00579   *         @arg @ref LL_MPU_REGION_NUMBER10
00580   *         @arg @ref LL_MPU_REGION_NUMBER11
00581   *         @arg @ref LL_MPU_REGION_NUMBER12
00582   *         @arg @ref LL_MPU_REGION_NUMBER13
00583   *         @arg @ref LL_MPU_REGION_NUMBER14
00584   *         @arg @ref LL_MPU_REGION_NUMBER15
00585   * @param  Address Value of region base address
00586   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00587   * @param  Attributes This parameter can be a combination of the following values:
00588   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00589   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00590   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00591   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00592   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00593   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00594   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00595   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00596   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00597   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00598   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00599   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00600   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00601   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00605 {
00606   /* Set Region number */
00607   WRITE_REG(MPU->RNR, Region);
00608   /* Set base address */
00609   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00610   /* Configure MPU */
00611   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
00612 }
00613
00614 /**
00615   * @brief  Disable a region
00616   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00617   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00618   * @param  Region This parameter can be one of the following values:
00619   *         @arg @ref LL_MPU_REGION_NUMBER0
00620   *         @arg @ref LL_MPU_REGION_NUMBER1
00621   *         @arg @ref LL_MPU_REGION_NUMBER2
00622   *         @arg @ref LL_MPU_REGION_NUMBER3
00623   *         @arg @ref LL_MPU_REGION_NUMBER4
00624   *         @arg @ref LL_MPU_REGION_NUMBER5
00625   *         @arg @ref LL_MPU_REGION_NUMBER6
00626   *         @arg @ref LL_MPU_REGION_NUMBER7
00627   *         @arg @ref LL_MPU_REGION_NUMBER8
00628   *         @arg @ref LL_MPU_REGION_NUMBER9
00629   *         @arg @ref LL_MPU_REGION_NUMBER10
00630   *         @arg @ref LL_MPU_REGION_NUMBER11
00631   *         @arg @ref LL_MPU_REGION_NUMBER12
00632   *         @arg @ref LL_MPU_REGION_NUMBER13
00633   *         @arg @ref LL_MPU_REGION_NUMBER14
00634   *         @arg @ref LL_MPU_REGION_NUMBER15
00635   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00639 {
00640   /* Set Region number */
00641   WRITE_REG(MPU->RNR, Region);
00642   /* Disable the MPU region */
00643   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00644 }
00645
00646 /**
00647   * @}
00648   */
00649
00650 #endif /* __MPU_PRESENT */
00651 /**
00652   * @}
00653   */
00654
00655 /**
00656   * @}
00657   */
00658
00659 /**
00660   * @}
00661   */
00662
00663 #ifdef __cplusplus
00664 }
00665 #endif
00666
00667 #endif /* STM32H7xx_LL_CORTEX_H */
00668
00669 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crc.c Source File

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stm32h7xx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_crc.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (CRC)
00036
00037 /** @addtogroup CRC_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046
00047 /* Exported functions --------------------------------------------------------*/
00048 /** @addtogroup CRC_LL_Exported_Functions
00049   * @{
00050   */
00051
00052 /** @addtogroup CRC_LL_EF_Init
00053   * @{
00054   */
00055
00056 /**
00057   * @brief  De-initialize CRC registers (Registers restored to their default values).
00058   * @param  CRCx CRC Instance
00059   * @retval An ErrorStatus enumeration value:
00060   *          - SUCCESS: CRC registers are de-initialized
00061   *          - ERROR: CRC registers are not de-initialized
00062   */
00063 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00064 {
00065   ErrorStatus status = SUCCESS;
00066
00067   /* Check the parameters */
00068   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00069
00070   if (CRCx == CRC)
00071   {
00072 #if defined(LL_AHB4_GRP1_PERIPH_CRC)
00073     /* Force CRC reset */
00074     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC);
00075
00076     /* Release CRC reset */
00077     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC);
00078 #else
00079     /* Force CRC reset */
00080     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
00081
00082     /* Release CRC reset */
00083     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
00084 #endif/*LL_AHB4_GRP1_PERIPH_CRC)*/
00085   }
00086   else
00087   {
00088     status = ERROR;
00089   }
00090
00091   return (status);
00092 }
00093
00094 /**
00095   * @}
00096   */
00097
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 #endif /* defined (CRC) */
00107
00108 /**
00109   * @}
00110   */
00111
00112 #endif /* USE_FULL_LL_DRIVER */
00113
00114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00115
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crc.h Source File

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stm32h7xx_ll_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_CRC_H
00022 #define STM32H7xx_LL_CRC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(CRC)
00036
00037 /** @defgroup CRC_LL CRC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 /* Exported constants --------------------------------------------------------*/
00048 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00049   * @{
00050   */
00051
00052 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00053   * @{
00054   */
00055 #define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
00056 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00057 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00058 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00064   * @{
00065   */
00066 #define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
00067 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00068 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00069 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00075   * @{
00076   */
00077 #define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
00078 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00084   * @brief    Normal representation of this polynomial value is
00085   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00086   * @{
00087   */
00088 #define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00094   * @{
00095   */
00096 #define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported macro ------------------------------------------------------------*/
00106 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00107   * @{
00108   */
00109
00110 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00111   * @{
00112   */
00113
00114 /**
00115   * @brief  Write a value in CRC register
00116   * @param  __INSTANCE__ CRC Instance
00117   * @param  __REG__ Register to be written
00118   * @param  __VALUE__ Value to be written in the register
00119   * @retval None
00120   */
00121 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
00122
00123 /**
00124   * @brief  Read a value in CRC register
00125   * @param  __INSTANCE__ CRC Instance
00126   * @param  __REG__ Register to be read
00127   * @retval Register value
00128   */
00129 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138
00139 /* Exported functions --------------------------------------------------------*/
00140 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00145   * @{
00146   */
00147
00148 /**
00149   * @brief  Reset the CRC calculation unit.
00150   * @note   If Programmable Initial CRC value feature
00151   *         is available, also set the Data Register to the value stored in the
00152   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00153   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00154   * @param  CRCx CRC Instance
00155   * @retval None
00156   */
00157 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00158 {
00159   SET_BIT(CRCx->CR, CRC_CR_RESET);
00160 }
00161
00162 /**
00163   * @brief  Configure size of the polynomial.
00164   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00165   * @param  CRCx CRC Instance
00166   * @param  PolySize This parameter can be one of the following values:
00167   *         @arg @ref LL_CRC_POLYLENGTH_32B
00168   *         @arg @ref LL_CRC_POLYLENGTH_16B
00169   *         @arg @ref LL_CRC_POLYLENGTH_8B
00170   *         @arg @ref LL_CRC_POLYLENGTH_7B
00171   * @retval None
00172   */
00173 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00174 {
00175   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00176 }
00177
00178 /**
00179   * @brief  Return size of the polynomial.
00180   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00181   * @param  CRCx CRC Instance
00182   * @retval Returned value can be one of the following values:
00183   *         @arg @ref LL_CRC_POLYLENGTH_32B
00184   *         @arg @ref LL_CRC_POLYLENGTH_16B
00185   *         @arg @ref LL_CRC_POLYLENGTH_8B
00186   *         @arg @ref LL_CRC_POLYLENGTH_7B
00187   */
00188 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
00189 {
00190   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00191 }
00192
00193 /**
00194   * @brief  Configure the reversal of the bit order of the input data
00195   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00196   * @param  CRCx CRC Instance
00197   * @param  ReverseMode This parameter can be one of the following values:
00198   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00199   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00200   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00201   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00202   * @retval None
00203   */
00204 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00205 {
00206   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00207 }
00208
00209 /**
00210   * @brief  Return type of reversal for input data bit order
00211   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00212   * @param  CRCx CRC Instance
00213   * @retval Returned value can be one of the following values:
00214   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00215   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00217   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00218   */
00219 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
00220 {
00221   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00222 }
00223
00224 /**
00225   * @brief  Configure the reversal of the bit order of the Output data
00226   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00227   * @param  CRCx CRC Instance
00228   * @param  ReverseMode This parameter can be one of the following values:
00229   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00230   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00231   * @retval None
00232   */
00233 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00234 {
00235   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00236 }
00237
00238 /**
00239   * @brief  Configure the reversal of the bit order of the Output data
00240   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00241   * @param  CRCx CRC Instance
00242   * @retval Returned value can be one of the following values:
00243   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00244   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00245   */
00246 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
00247 {
00248   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00249 }
00250
00251 /**
00252   * @brief  Initialize the Programmable initial CRC value.
00253   * @note   If the CRC size is less than 32 bits, the least significant bits
00254   *         are used to write the correct value
00255   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00256   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00257   * @param  CRCx CRC Instance
00258   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00259   * @retval None
00260   */
00261 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00262 {
00263   WRITE_REG(CRCx->INIT, InitCrc);
00264 }
00265
00266 /**
00267   * @brief  Return current Initial CRC value.
00268   * @note   If the CRC size is less than 32 bits, the least significant bits
00269   *         are used to read the correct value
00270   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00271   * @param  CRCx CRC Instance
00272   * @retval Value programmed in Programmable initial CRC value register
00273   */
00274 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
00275 {
00276   return (uint32_t)(READ_REG(CRCx->INIT));
00277 }
00278
00279 /**
00280   * @brief  Initialize the Programmable polynomial value
00281   *         (coefficients of the polynomial to be used for CRC calculation).
00282   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00283   * @note   Please check Reference Manual and existing Errata Sheets,
00284   *         regarding possible limitations for Polynomial values usage.
00285   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00286   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00287   * @param  CRCx CRC Instance
00288   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00292 {
00293   WRITE_REG(CRCx->POL, PolynomCoef);
00294 }
00295
00296 /**
00297   * @brief  Return current Programmable polynomial value
00298   * @note   Please check Reference Manual and existing Errata Sheets,
00299   *         regarding possible limitations for Polynomial values usage.
00300   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00301   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00302   * @param  CRCx CRC Instance
00303   * @retval Value programmed in Programmable Polynomial value register
00304   */
00305 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
00306 {
00307   return (uint32_t)(READ_REG(CRCx->POL));
00308 }
00309
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00315   * @{
00316   */
00317
00318 /**
00319   * @brief  Write given 32-bit data to the CRC calculator
00320   * @rmtoll DR           DR            LL_CRC_FeedData32
00321   * @param  CRCx CRC Instance
00322   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00323   * @retval None
00324   */
00325 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00326 {
00327   WRITE_REG(CRCx->DR, InData);
00328 }
00329
00330 /**
00331   * @brief  Write given 16-bit data to the CRC calculator
00332   * @rmtoll DR           DR            LL_CRC_FeedData16
00333   * @param  CRCx CRC Instance
00334   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00335   * @retval None
00336   */
00337 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00338 {
00339   __IO uint16_t *pReg;
00340
00341   pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
00342   *pReg = InData;
00343 }
00344
00345 /**
00346   * @brief  Write given 8-bit data to the CRC calculator
00347   * @rmtoll DR           DR            LL_CRC_FeedData8
00348   * @param  CRCx CRC Instance
00349   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00350   * @retval None
00351   */
00352 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00353 {
00354   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00355 }
00356
00357 /**
00358   * @brief  Return current CRC calculation result. 32 bits value is returned.
00359   * @rmtoll DR           DR            LL_CRC_ReadData32
00360   * @param  CRCx CRC Instance
00361   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00362   */
00363 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00364 {
00365   return (uint32_t)(READ_REG(CRCx->DR));
00366 }
00367
00368 /**
00369   * @brief  Return current CRC calculation result. 16 bits value is returned.
00370   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00371   * @rmtoll DR           DR            LL_CRC_ReadData16
00372   * @param  CRCx CRC Instance
00373   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00374   */
00375 __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
00376 {
00377   return (uint16_t)READ_REG(CRCx->DR);
00378 }
00379
00380 /**
00381   * @brief  Return current CRC calculation result. 8 bits value is returned.
00382   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00383   * @rmtoll DR           DR            LL_CRC_ReadData8
00384   * @param  CRCx CRC Instance
00385   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00386   */
00387 __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
00388 {
00389   return (uint8_t)READ_REG(CRCx->DR);
00390 }
00391
00392 /**
00393   * @brief  Return current CRC calculation result. 7 bits value is returned.
00394   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00395   * @rmtoll DR           DR            LL_CRC_ReadData7
00396   * @param  CRCx CRC Instance
00397   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00398   */
00399 __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
00400 {
00401   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00402 }
00403
00404 /**
00405   * @brief  Return data stored in the Independent Data(IDR) register.
00406   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00407   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00408   * @param  CRCx CRC Instance
00409   * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
00410   */
00411 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00412 {
00413   return (uint32_t)(READ_REG(CRCx->IDR));
00414 }
00415
00416 /**
00417   * @brief  Store data in the Independent Data(IDR) register.
00418   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00419   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00420   * @param  CRCx CRC Instance
00421   * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
00422   * @retval None
00423   */
00424 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00425 {
00426   *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
00427 }
00428 /**
00429   * @}
00430   */
00431
00432 #if defined(USE_FULL_LL_DRIVER)
00433 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00434   * @{
00435   */
00436
00437 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00438
00439 /**
00440   * @}
00441   */
00442 #endif /* USE_FULL_LL_DRIVER */
00443
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 #endif /* defined(CRC) */
00453
00454 /**
00455   * @}
00456   */
00457
00458 #ifdef __cplusplus
00459 }
00460 #endif
00461
00462 #endif /* STM32H7xx_LL_CRC_H */
00463
00464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crs.c Source File

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stm32h7xx_ll_crs.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   CRS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_crs.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 /** @addtogroup STM32H7xx_LL_Driver
00026   * @{
00027   */
00028
00029 #if defined(CRS)
00030
00031 /** @defgroup CRS_LL CRS
00032   * @{
00033   */
00034
00035 /* Private types -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 /* Private constants ---------------------------------------------------------*/
00038 /* Private macros ------------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup CRS_LL_Exported_Functions
00043   * @{
00044   */
00045
00046 /** @addtogroup CRS_LL_EF_Init
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  De-Initializes CRS peripheral registers to their default reset values.
00052   * @retval An ErrorStatus enumeration value:
00053   *          - SUCCESS: CRS registers are de-initialized
00054   *          - ERROR: not applicable
00055   */
00056 ErrorStatus LL_CRS_DeInit(void)
00057 {
00058   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
00059   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
00060
00061   return  SUCCESS;
00062 }
00063
00064
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 #endif /* defined(CRS) */
00079
00080 /**
00081   * @}
00082   */
00083
00084 #endif /* USE_FULL_LL_DRIVER */
00085
00086 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_crs.h Source File

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stm32h7xx_ll_crs.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_CRS_H
00022 #define STM32H7xx_LL_CRS_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(CRS)
00036
00037 /** @defgroup CRS_LL CRS
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 /* Exported constants --------------------------------------------------------*/
00048 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00049   * @{
00050   */
00051
00052 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00053   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00054   * @{
00055   */
00056 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00057 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00058 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00059 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00060 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00061 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00062 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00063 /**
00064   * @}
00065   */
00066
00067 /** @defgroup CRS_LL_EC_IT IT Defines
00068   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00069   * @{
00070   */
00071 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00072 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00073 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00074 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00080   * @{
00081   */
00082 #define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
00083 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00084 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00085 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00086 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00087 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00088 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00089 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00095   * @{
00096   */
00097 #define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal soucre GPIO */
00098 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00099 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00105   * @{
00106   */
00107 #define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
00108 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00114   * @{
00115   */
00116 #define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
00117 #define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00123   * @{
00124   */
00125 /**
00126   * @brief Reset value of the RELOAD field
00127   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00128   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00129   */
00130 #define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
00131
00132 /**
00133   * @brief Reset value of Frequency error limit.
00134   */
00135 #define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
00136
00137 /**
00138   * @brief Reset value of the HSI48 Calibration field
00139   * @note The default value is 64, which corresponds to the middle of the trimming interval.
00140   *       The trimming step is specified in the product datasheet.
00141   *       A higher TRIM value corresponds to a higher output frequency.
00142   */
00143 #define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000040U
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /* Exported macro ------------------------------------------------------------*/
00153 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00154   * @{
00155   */
00156
00157 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Write a value in CRS register
00163   * @param  __INSTANCE__ CRS Instance
00164   * @param  __REG__ Register to be written
00165   * @param  __VALUE__ Value to be written in the register
00166   * @retval None
00167   */
00168 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00169
00170 /**
00171   * @brief  Read a value in CRS register
00172   * @param  __INSTANCE__ CRS Instance
00173   * @param  __REG__ Register to be read
00174   * @retval Register value
00175   */
00176 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00182   * @{
00183   */
00184
00185 /**
00186   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00187   * @note   The RELOAD value should be selected according to the ratio between
00188   *         the target frequency and the frequency of the synchronization source after
00189   *         prescaling. It is then decreased by one in order to reach the expected
00190   *         synchronization on the zero value. The formula is the following:
00191   *              RELOAD = (fTARGET / fSYNC) -1
00192   * @param  __FTARGET__ Target frequency (value in Hz)
00193   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00194   * @retval Reload value (in Hz)
00195   */
00196 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00197
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00208   * @{
00209   */
00210
00211 /** @defgroup CRS_LL_EF_Configuration Configuration
00212   * @{
00213   */
00214
00215 /**
00216   * @brief  Enable Frequency error counter
00217   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00218   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00219   * @retval None
00220   */
00221 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00222 {
00223   SET_BIT(CRS->CR, CRS_CR_CEN);
00224 }
00225
00226 /**
00227   * @brief  Disable Frequency error counter
00228   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00229   * @retval None
00230   */
00231 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00232 {
00233   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00234 }
00235
00236 /**
00237   * @brief  Check if Frequency error counter is enabled or not
00238   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00239   * @retval State of bit (1 or 0).
00240   */
00241 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00242 {
00243   return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
00244 }
00245
00246 /**
00247   * @brief  Enable Automatic trimming counter
00248   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00249   * @retval None
00250   */
00251 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00252 {
00253   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00254 }
00255
00256 /**
00257   * @brief  Disable Automatic trimming counter
00258   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00259   * @retval None
00260   */
00261 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00262 {
00263   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00264 }
00265
00266 /**
00267   * @brief  Check if Automatic trimming is enabled or not
00268   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00269   * @retval State of bit (1 or 0).
00270   */
00271 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00272 {
00273   return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
00274 }
00275
00276 /**
00277   * @brief  Set HSI48 oscillator smooth trimming
00278   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00279   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00280   * @param  Value a number between Min_Data = 0 and Max_Data = 127
00281   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00285 {
00286   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
00287 }
00288
00289 /**
00290   * @brief  Get HSI48 oscillator smooth trimming
00291   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00292   * @retval a number between Min_Data = 0 and Max_Data = 127
00293   */
00294 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00295 {
00296   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
00297 }
00298
00299 /**
00300   * @brief  Set counter reload value
00301   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00302   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00303   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
00304   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00305   * @retval None
00306   */
00307 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00308 {
00309   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00310 }
00311
00312 /**
00313   * @brief  Get counter reload value
00314   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00315   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00316   */
00317 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00318 {
00319   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00320 }
00321
00322 /**
00323   * @brief  Set frequency error limit
00324   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00325   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00326   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
00327   * @retval None
00328   */
00329 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00330 {
00331   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
00332 }
00333
00334 /**
00335   * @brief  Get frequency error limit
00336   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00337   * @retval A number between Min_Data = 0 and Max_Data = 255
00338   */
00339 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00340 {
00341   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
00342 }
00343
00344 /**
00345   * @brief  Set division factor for SYNC signal
00346   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00347   * @param  Divider This parameter can be one of the following values:
00348   *         @arg @ref LL_CRS_SYNC_DIV_1
00349   *         @arg @ref LL_CRS_SYNC_DIV_2
00350   *         @arg @ref LL_CRS_SYNC_DIV_4
00351   *         @arg @ref LL_CRS_SYNC_DIV_8
00352   *         @arg @ref LL_CRS_SYNC_DIV_16
00353   *         @arg @ref LL_CRS_SYNC_DIV_32
00354   *         @arg @ref LL_CRS_SYNC_DIV_64
00355   *         @arg @ref LL_CRS_SYNC_DIV_128
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00359 {
00360   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00361 }
00362
00363 /**
00364   * @brief  Get division factor for SYNC signal
00365   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00366   * @retval Returned value can be one of the following values:
00367   *         @arg @ref LL_CRS_SYNC_DIV_1
00368   *         @arg @ref LL_CRS_SYNC_DIV_2
00369   *         @arg @ref LL_CRS_SYNC_DIV_4
00370   *         @arg @ref LL_CRS_SYNC_DIV_8
00371   *         @arg @ref LL_CRS_SYNC_DIV_16
00372   *         @arg @ref LL_CRS_SYNC_DIV_32
00373   *         @arg @ref LL_CRS_SYNC_DIV_64
00374   *         @arg @ref LL_CRS_SYNC_DIV_128
00375   */
00376 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00377 {
00378   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00379 }
00380
00381 /**
00382   * @brief  Set SYNC signal source
00383   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00384   * @param  Source This parameter can be one of the following values:
00385   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00386   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00387   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00391 {
00392   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00393 }
00394
00395 /**
00396   * @brief  Get SYNC signal source
00397   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00398   * @retval Returned value can be one of the following values:
00399   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00400   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00401   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00402   */
00403 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00404 {
00405   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00406 }
00407
00408 /**
00409   * @brief  Set input polarity for the SYNC signal source
00410   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00411   * @param  Polarity This parameter can be one of the following values:
00412   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00413   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00414   * @retval None
00415   */
00416 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00417 {
00418   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00419 }
00420
00421 /**
00422   * @brief  Get input polarity for the SYNC signal source
00423   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00424   * @retval Returned value can be one of the following values:
00425   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00426   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00427   */
00428 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00429 {
00430   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00431 }
00432
00433 /**
00434   * @brief  Configure CRS for the synchronization
00435   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00436   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00437   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00438   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00439   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00440   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00441   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
00442   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00443   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00444   * @param  Settings This parameter can be a combination of the following values:
00445   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00446   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00447   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00448   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00449   * @retval None
00450   */
00451 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
00452 {
00453   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00454   MODIFY_REG(CRS->CFGR,
00455              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
00456              ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
00457 }
00458
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00464   * @{
00465   */
00466
00467 /**
00468   * @brief  Generate software SYNC event
00469   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00470   * @retval None
00471   */
00472 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00473 {
00474   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00475 }
00476
00477 /**
00478   * @brief  Get the frequency error direction latched in the time of the last
00479   * SYNC event
00480   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00481   * @retval Returned value can be one of the following values:
00482   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00483   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00484   */
00485 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00486 {
00487   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00488 }
00489
00490 /**
00491   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00492   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00493   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00494   */
00495 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00496 {
00497   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
00498 }
00499
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00505   * @{
00506   */
00507
00508 /**
00509   * @brief  Check if SYNC event OK signal occurred or not
00510   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00511   * @retval State of bit (1 or 0).
00512   */
00513 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00514 {
00515   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
00516 }
00517
00518 /**
00519   * @brief  Check if SYNC warning signal occurred or not
00520   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00521   * @retval State of bit (1 or 0).
00522   */
00523 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00524 {
00525   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
00526 }
00527
00528 /**
00529   * @brief  Check if Synchronization or trimming error signal occurred or not
00530   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00531   * @retval State of bit (1 or 0).
00532   */
00533 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00534 {
00535   return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
00536 }
00537
00538 /**
00539   * @brief  Check if Expected SYNC signal occurred or not
00540   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00541   * @retval State of bit (1 or 0).
00542   */
00543 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00544 {
00545   return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
00546 }
00547
00548 /**
00549   * @brief  Check if SYNC error signal occurred or not
00550   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00551   * @retval State of bit (1 or 0).
00552   */
00553 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00554 {
00555   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
00556 }
00557
00558 /**
00559   * @brief  Check if SYNC missed error signal occurred or not
00560   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00561   * @retval State of bit (1 or 0).
00562   */
00563 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00564 {
00565   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
00566 }
00567
00568 /**
00569   * @brief  Check if Trimming overflow or underflow occurred or not
00570   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00571   * @retval State of bit (1 or 0).
00572   */
00573 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00574 {
00575   return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
00576 }
00577
00578 /**
00579   * @brief  Clear the SYNC event OK flag
00580   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00584 {
00585   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00586 }
00587
00588 /**
00589   * @brief  Clear the  SYNC warning flag
00590   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00591   * @retval None
00592   */
00593 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00594 {
00595   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00596 }
00597
00598 /**
00599   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
00600   * the ERR flag
00601   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00605 {
00606   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00607 }
00608
00609 /**
00610   * @brief  Clear Expected SYNC flag
00611   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00612   * @retval None
00613   */
00614 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00615 {
00616   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00617 }
00618
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00624   * @{
00625   */
00626
00627 /**
00628   * @brief  Enable SYNC event OK interrupt
00629   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00633 {
00634   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00635 }
00636
00637 /**
00638   * @brief  Disable SYNC event OK interrupt
00639   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00643 {
00644   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00645 }
00646
00647 /**
00648   * @brief  Check if SYNC event OK interrupt is enabled or not
00649   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00650   * @retval State of bit (1 or 0).
00651   */
00652 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00653 {
00654   return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
00655 }
00656
00657 /**
00658   * @brief  Enable SYNC warning interrupt
00659   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00660   * @retval None
00661   */
00662 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00663 {
00664   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00665 }
00666
00667 /**
00668   * @brief  Disable SYNC warning interrupt
00669   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00673 {
00674   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00675 }
00676
00677 /**
00678   * @brief  Check if SYNC warning interrupt is enabled or not
00679   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00680   * @retval State of bit (1 or 0).
00681   */
00682 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00683 {
00684   return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
00685 }
00686
00687 /**
00688   * @brief  Enable Synchronization or trimming error interrupt
00689   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00690   * @retval None
00691   */
00692 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00693 {
00694   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00695 }
00696
00697 /**
00698   * @brief  Disable Synchronization or trimming error interrupt
00699   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00703 {
00704   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00705 }
00706
00707 /**
00708   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00709   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00710   * @retval State of bit (1 or 0).
00711   */
00712 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00713 {
00714   return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
00715 }
00716
00717 /**
00718   * @brief  Enable Expected SYNC interrupt
00719   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00720   * @retval None
00721   */
00722 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00723 {
00724   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00725 }
00726
00727 /**
00728   * @brief  Disable Expected SYNC interrupt
00729   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00733 {
00734   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00735 }
00736
00737 /**
00738   * @brief  Check if Expected SYNC interrupt is enabled or not
00739   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00740   * @retval State of bit (1 or 0).
00741   */
00742 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00743 {
00744   return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
00745 }
00746
00747 /**
00748   * @}
00749   */
00750
00751 #if defined(USE_FULL_LL_DRIVER)
00752 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00753   * @{
00754   */
00755
00756 ErrorStatus LL_CRS_DeInit(void);
00757
00758 /**
00759   * @}
00760   */
00761 #endif /* USE_FULL_LL_DRIVER */
00762
00763 /**
00764   * @}
00765   */
00766
00767 /**
00768   * @}
00769   */
00770
00771 #endif /* defined(CRS) */
00772
00773 /**
00774   * @}
00775   */
00776
00777 #ifdef __cplusplus
00778 }
00779 #endif
00780
00781 #endif /* STM32H7xx_LL_CRS_H */
00782
00783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dac.c Source File

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stm32h7xx_ll_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_dac.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(DAC1) || defined(DAC2)
00036
00037 /** @addtogroup DAC_LL DAC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /** @addtogroup DAC_LL_Private_Macros
00047   * @{
00048   */
00049 #define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)                                     \
00050   (                                                                            \
00051       ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
00052    || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
00053   )
00054
00055 #if defined (HRTIM1)
00056 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00057   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00058    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
00059    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00060    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00061    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00062    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00063    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00064    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
00065    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00066    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO1)                    \
00067    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO2)                    \
00068    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
00069    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
00070    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00071   )
00072 #elif defined (DAC2)
00073 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00074   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00075    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
00076    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00077    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00078    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00079    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00080    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00081    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
00082    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00083    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
00084    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
00085    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00086    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_OUT)                     \
00087   )
00088 #else
00089 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00090   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00091    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
00092    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00093    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00094    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00095    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00096    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00097    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
00098    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00099    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
00100    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
00101    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00102    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM23_TRGO)                     \
00103    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM24_TRGO)                     \
00104   )
00105 #endif
00106
00107 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
00108   (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
00109    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00110    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00111   )
00112
00113 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)  \
00114   ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
00115     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                            \
00116        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                         \
00117        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                         \
00118        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                         \
00119        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                         \
00120        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                         \
00121        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                         \
00122        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                         \
00123        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                         \
00124        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                         \
00125        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                        \
00126        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                       \
00127     )                                                                                                     \
00128   ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                            \
00129     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                              \
00130        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                              \
00131        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                              \
00132        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                             \
00133        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                             \
00134        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                             \
00135        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                            \
00136        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                            \
00137        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                            \
00138        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                           \
00139        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                           \
00140        || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                          \
00141     )                                                                                                     \
00142   )
00143
00144 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00145   (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
00146    || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
00147   )
00148
00149 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
00150   (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
00151    || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
00152   )
00153
00154 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
00155   (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
00156    || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
00157   )
00158
00159 /**
00160   * @}
00161   */
00162
00163
00164 /* Private function prototypes -----------------------------------------------*/
00165
00166 /* Exported functions --------------------------------------------------------*/
00167 /** @addtogroup DAC_LL_Exported_Functions
00168   * @{
00169   */
00170
00171 /** @addtogroup DAC_LL_EF_Init
00172   * @{
00173   */
00174
00175 /**
00176   * @brief  De-initialize registers of the selected DAC instance
00177   *         to their default reset values.
00178   * @param  DACx DAC instance
00179   * @retval An ErrorStatus enumeration value:
00180   *          - SUCCESS: DAC registers are de-initialized
00181   *          - ERROR: not applicable
00182   */
00183 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
00184 {
00185   /* Check the parameters */
00186   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00187
00188   if(DACx == DAC1)
00189   {
00190     /* Force reset of DAC clock */
00191     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC12);
00192
00193     /* Release reset of DAC clock */
00194     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC12);
00195  }
00196 #if defined (DAC2)
00197   else
00198   {
00199     /* Force reset of DAC clock */
00200     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_DAC2);
00201
00202     /* Release reset of DAC clock */
00203     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_DAC2);
00204   }
00205 #endif
00206
00207
00208   return SUCCESS;
00209 }
00210
00211 /**
00212   * @brief  Initialize some features of DAC channel.
00213   * @note   @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
00214   *         Leaving it ready to be enabled and output:
00215   *         a level by calling one of
00216   *           @ref LL_DAC_ConvertData12RightAligned
00217   *           @ref LL_DAC_ConvertData12LeftAligned
00218   *           @ref LL_DAC_ConvertData8RightAligned
00219   *         or one of the supported autogenerated wave.
00220   * @note   This function allows configuration of:
00221   *          - Output mode
00222   *          - Trigger
00223   *          - Wave generation
00224   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00225   *         is conditioned to DAC state:
00226   *         DAC channel must be disabled.
00227   * @param  DACx DAC instance
00228   * @param  DAC_Channel This parameter can be one of the following values:
00229   *         @arg @ref LL_DAC_CHANNEL_1
00230   *         @arg @ref LL_DAC_CHANNEL_2
00231   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00232   * @retval An ErrorStatus enumeration value:
00233   *          - SUCCESS: DAC registers are initialized
00234   *          - ERROR: DAC registers are not initialized
00235   */
00236 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
00237 {
00238   ErrorStatus status = SUCCESS;
00239
00240   /* Check the parameters */
00241   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00242   assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
00243   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
00244   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00245   assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
00246   assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
00247   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00248   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00249   {
00250     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
00251                                                   DAC_InitStruct->WaveAutoGenerationConfig));
00252   }
00253
00254   /* Note: Hardware constraint (refer to description of this function)        */
00255   /*       DAC instance must be disabled.                                     */
00256   if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
00257   {
00258     /* Configuration of DAC channel:                                          */
00259     /*  - TriggerSource                                                       */
00260     /*  - WaveAutoGeneration                                                  */
00261     /*  - OutputBuffer                                                        */
00262     /*  - OutputConnection                                                    */
00263     /*  - OutputMode                                                          */
00264     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00265     {
00266       MODIFY_REG(DACx->CR,
00267                  (DAC_CR_TSEL1
00268                   | DAC_CR_WAVE1
00269                   | DAC_CR_MAMP1
00270                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00271                  ,
00272                  (DAC_InitStruct->TriggerSource
00273                   | DAC_InitStruct->WaveAutoGeneration
00274                   | DAC_InitStruct->WaveAutoGenerationConfig
00275                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00276                 );
00277     }
00278     else
00279     {
00280       MODIFY_REG(DACx->CR,
00281                  (DAC_CR_TSEL1
00282                   | DAC_CR_WAVE1
00283                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00284                  ,
00285                  (DAC_InitStruct->TriggerSource
00286                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00287                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00288                 );
00289     }
00290     MODIFY_REG(DACx->MCR,
00291                (DAC_MCR_MODE1_1
00292                 | DAC_MCR_MODE1_0
00293                 | DAC_MCR_MODE1_2
00294                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00295                ,
00296                (DAC_InitStruct->OutputBuffer
00297                 | DAC_InitStruct->OutputConnection
00298                 | DAC_InitStruct->OutputMode
00299                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00300               );
00301   }
00302   else
00303   {
00304     /* Initialization error: DAC instance is not disabled.                    */
00305     status = ERROR;
00306   }
00307   return status;
00308 }
00309
00310 /**
00311   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00312   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00313   *                       whose fields will be set to default values.
00314   * @retval None
00315   */
00316 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00317 {
00318   /* Set DAC_InitStruct fields to default values */
00319   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00320   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00321   /* Note: Parameter discarded if wave auto generation is disabled,           */
00322   /*       set anyway to its default value.                                   */
00323   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00324   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00325   DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
00326   DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
00327 }
00328
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 #endif /* DAC1 || DAC2 */
00342
00343 /**
00344   * @}
00345   */
00346
00347 #endif /* USE_FULL_LL_DRIVER */
00348
00349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dac.h Source File

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stm32h7xx_ll_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_DAC_H
00022 #define STM32H7xx_LL_DAC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(DAC1) || defined(DAC2)
00036
00037 /** @defgroup DAC_LL DAC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00046   * @{
00047   */
00048
00049 /* Internal masks for DAC channels definition */
00050 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00051 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
00052 /* - channel bits position into register SWTRIG                               */
00053 /* - channel register offset of data holding register DHRx                    */
00054 /* - channel register offset of data output register DORx                     */
00055 /* - channel register offset of sample-and-hold sample time register SHSRx    */
00056 #define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
00057 #define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
00058 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00059
00060 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
00061 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
00062 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00063
00064 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
00065 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00066 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00067 #define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
00068 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00069 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00070 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
00071 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
00072 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
00073 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00074
00075 #define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
00076 #define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
00077 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00078 #define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
00079 #define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
00080 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
00081
00082
00083 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
00084 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
00085 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
00086
00087 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
00088 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00089 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00090 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
00091 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
00092
00093 /* DAC registers bits positions */
00094 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
00095 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
00096 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
00097
00098 /* Miscellaneous data */
00099 #define DAC_DIGITAL_SCALE_12BITS                        4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
00100
00101 /**
00102   * @}
00103   */
00104
00105
00106 /* Private macros ------------------------------------------------------------*/
00107 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00108   * @{
00109   */
00110
00111 /**
00112   * @brief  Driver macro reserved for internal use: set a pointer to
00113   *         a register from a register basis from which an offset
00114   *         is applied.
00115   * @param  __REG__ Register basis from which the offset is applied.
00116   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00117   * @retval Pointer to register address
00118 */
00119 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00120   ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00121
00122 /**
00123   * @}
00124   */
00125
00126
00127 /* Exported types ------------------------------------------------------------*/
00128 #if defined(USE_FULL_LL_DRIVER)
00129 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Structure definition of some features of DAC instance.
00135   */
00136 typedef struct
00137 {
00138   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
00139                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00140
00141                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
00142
00143   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00144                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00145
00146                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
00147
00148   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00149                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00150                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00151                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
00152
00153                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
00154                                              depending on the wave automatic generation selected. */
00155
00156   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00157                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00158
00159                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
00160
00161   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
00162                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
00163
00164                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
00165
00166   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
00167                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
00168
00169                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
00170 } LL_DAC_InitTypeDef;
00171
00172 /**
00173   * @}
00174   */
00175 #endif /* USE_FULL_LL_DRIVER */
00176
00177 /* Exported constants --------------------------------------------------------*/
00178 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00179   * @{
00180   */
00181
00182 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00183   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00184   * @{
00185   */
00186 /* DAC channel 1 flags */
00187 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00188 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
00189 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
00190
00191 /* DAC channel 2 flags */
00192 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00193 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
00194 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup DAC_LL_EC_IT DAC interruptions
00200   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00201   * @{
00202   */
00203 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00204 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00210   * @{
00211   */
00212 #define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00213 #define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
00219   * @{
00220   */
00221 #define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */
00222 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00228   * @{
00229   */
00230 #define LL_DAC_TRIG_SOFTWARE               0x00000000U                                                         /*!< DAC channel conversion trigger internal (SW start) */
00231 #define LL_DAC_TRIG_EXT_TIM1_TRGO          (                                                   DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
00232 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (                                  DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
00233 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
00234 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
00235 #define LL_DAC_TRIG_EXT_TIM6_TRGO          (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
00236 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
00237 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
00238 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (DAC_CR_TSEL1_3                                                   ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
00239 #if defined (HRTIM1)
00240 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
00241 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
00242 #endif
00243 #define LL_DAC_TRIG_EXT_LPTIM1_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
00244 #define LL_DAC_TRIG_EXT_LPTIM2_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_2                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
00245 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
00246 #if defined(TIM23)
00247 #define LL_DAC_TRIG_EXT_TIM23_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
00248 #endif
00249 #if defined(TIM24)
00250 #define LL_DAC_TRIG_EXT_TIM24_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
00251 #endif
00252 #if defined (DAC2)
00253 #define LL_DAC_TRIG_EXT_LPTIM3_OUT         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
00254 #endif
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00260   * @{
00261   */
00262 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
00263 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00264 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00270   * @{
00271   */
00272 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00289   * @{
00290   */
00291 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00292 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00293 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00294 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00295 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00296 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00297 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00298 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00299 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00300 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00301 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00302 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
00308   * @{
00309   */
00310 #define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */
00311 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00317   * @{
00318   */
00319 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00320 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
00326   * @{
00327   */
00328 #define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */
00329 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
00335   * @{
00336   */
00337 #define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)
00338 #define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)
00339 #define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)
00340 #define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)
00341 #define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)
00342 #define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)
00343 #define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)
00344
00345 #define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)
00346 #define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
00347 #define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
00348
00349 #define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)
00350 #define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)
00351 /**
00352   * @}
00353   */
00354 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00355   * @{
00356   */
00357 #define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
00358 #define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00364   * @{
00365   */
00366 /* List of DAC registers intended to be used (most commonly) with             */
00367 /* DMA transfer.                                                              */
00368 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00369 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
00370 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
00371 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00377   * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
00378   *         not timeout values.
00379   *         For details on delays values, refer to descriptions in source code
00380   *         above each literal definition.
00381   * @{
00382   */
00383
00384 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00385 /* (transition from disable to enable).                                       */
00386 /* Note: DAC channel startup time depends on board application environment:   */
00387 /*       impedance connected to DAC channel output.                           */
00388 /*       The delay below is specified under conditions:                       */
00389 /*        - voltage maximum transition (lowest to highest value)              */
00390 /*        - until voltage reaches final value +-1LSB                          */
00391 /*        - DAC channel output buffer enabled                                 */
00392 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00393 /* Literal set to maximum value (refer to device datasheet,                   */
00394 /* parameter "tWAKEUP").                                                      */
00395 /* Unit: us                                                                   */
00396 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00397
00398 /* Delay for DAC channel voltage settling time.                               */
00399 /* Note: DAC channel startup time depends on board application environment:   */
00400 /*       impedance connected to DAC channel output.                           */
00401 /*       The delay below is specified under conditions:                       */
00402 /*        - voltage maximum transition (lowest to highest value)              */
00403 /*        - until voltage reaches final value +-1LSB                          */
00404 /*        - DAC channel output buffer enabled                                 */
00405 /*        - load impedance of 5kOhm min, 50pF max                             */
00406 /* Literal set to maximum value (refer to device datasheet,                   */
00407 /* parameter "tSETTLING").                                                    */
00408 /* Unit: us                                                                   */
00409 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /* Exported macro ------------------------------------------------------------*/
00420 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00421   * @{
00422   */
00423
00424 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00425   * @{
00426   */
00427
00428 /**
00429   * @brief  Write a value in DAC register
00430   * @param  __INSTANCE__ DAC Instance
00431   * @param  __REG__ Register to be written
00432   * @param  __VALUE__ Value to be written in the register
00433   * @retval None
00434   */
00435 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00436
00437 /**
00438   * @brief  Read a value in DAC register
00439   * @param  __INSTANCE__ DAC Instance
00440   * @param  __REG__ Register to be read
00441   * @retval Register value
00442   */
00443 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00444
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00450   * @{
00451   */
00452
00453 /**
00454   * @brief  Helper macro to get DAC channel number in decimal format
00455   *         from literals LL_DAC_CHANNEL_x.
00456   *         Example:
00457   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00458   *            will return decimal number "1".
00459   * @note   The input can be a value from functions where a channel
00460   *         number is returned.
00461   * @param  __CHANNEL__ This parameter can be one of the following values:
00462   *         @arg @ref LL_DAC_CHANNEL_1
00463   *         @arg @ref LL_DAC_CHANNEL_2
00464   * @retval 1...2
00465   */
00466 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00467   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00468
00469 /**
00470   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00471   *         from number in decimal format.
00472   *         Example:
00473   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00474   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00475   * @note  If the input parameter does not correspond to a DAC channel,
00476   *        this macro returns value '0'.
00477   * @param  __DECIMAL_NB__ 1...2
00478   * @retval Returned value can be one of the following values:
00479   *         @arg @ref LL_DAC_CHANNEL_1
00480   *         @arg @ref LL_DAC_CHANNEL_2
00481   */
00482 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00483   (((__DECIMAL_NB__) == 1UL)                                                   \
00484     ? (                                                                        \
00485        LL_DAC_CHANNEL_1                                                        \
00486       )                                                                        \
00487       :                                                                        \
00488       (((__DECIMAL_NB__) == 2UL)                                               \
00489         ? (                                                                    \
00490            LL_DAC_CHANNEL_2                                                    \
00491           )                                                                    \
00492           :                                                                    \
00493           (                                                                    \
00494            0UL                                                                 \
00495           )                                                                    \
00496       )                                                                        \
00497   )
00498
00499 /**
00500   * @brief  Helper macro to define the DAC conversion data full-scale digital
00501   *         value corresponding to the selected DAC resolution.
00502   * @note   DAC conversion data full-scale corresponds to voltage range
00503   *         determined by analog voltage references Vref+ and Vref-
00504   *         (refer to reference manual).
00505   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00506   *         @arg @ref LL_DAC_RESOLUTION_12B
00507   *         @arg @ref LL_DAC_RESOLUTION_8B
00508   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00509   */
00510 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00511   ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
00512
00513 /**
00514   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00515   *         value) corresponding to a voltage (unit: mVolt).
00516   * @note   This helper macro is intended to provide input data in voltage
00517   *         rather than digital value,
00518   *         to be used with LL DAC functions such as
00519   *         @ref LL_DAC_ConvertData12RightAligned().
00520   * @note   Analog reference voltage (Vref+) must be either known from
00521   *         user board environment or can be calculated using ADC measurement
00522   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00523   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00524   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00525   *                         (unit: mVolt).
00526   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00527   *         @arg @ref LL_DAC_RESOLUTION_12B
00528   *         @arg @ref LL_DAC_RESOLUTION_8B
00529   * @retval DAC conversion data (unit: digital value)
00530   */
00531 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00532                                       __DAC_VOLTAGE__,\
00533                                       __DAC_RESOLUTION__)                      \
00534   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00535    / (__VREFANALOG_VOLTAGE__)                                                  \
00536   )
00537
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546
00547 /* Exported functions --------------------------------------------------------*/
00548 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00549   * @{
00550   */
00551 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00552   * @{
00553   */
00554
00555 /**
00556   * @brief  Set the operating mode for the selected DAC channel:
00557   *         calibration or normal operating mode.
00558   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
00559   *         CR       CEN2           LL_DAC_SetMode
00560   * @param  DACx DAC instance
00561   * @param  DAC_Channel This parameter can be one of the following values:
00562   *         @arg @ref LL_DAC_CHANNEL_1
00563   *         @arg @ref LL_DAC_CHANNEL_2
00564   * @param  ChannelMode This parameter can be one of the following values:
00565   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00566   *         @arg @ref LL_DAC_MODE_CALIBRATION
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
00570 {
00571   MODIFY_REG(DACx->CR,
00572              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00573              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00574 }
00575
00576 /**
00577   * @brief  Get the operating mode for the selected DAC channel:
00578   *         calibration or normal operating mode.
00579   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
00580   *         CR       CEN2           LL_DAC_GetMode
00581   * @param  DACx DAC instance
00582   * @param  DAC_Channel This parameter can be one of the following values:
00583   *         @arg @ref LL_DAC_CHANNEL_1
00584   *         @arg @ref LL_DAC_CHANNEL_2
00585   * @retval Returned value can be one of the following values:
00586   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00587   *         @arg @ref LL_DAC_MODE_CALIBRATION
00588   */
00589 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00590 {
00591   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00592                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00593                    );
00594 }
00595
00596 /**
00597   * @brief  Set the offset trimming value for the selected DAC channel.
00598   *         Trimming has an impact when output buffer is enabled
00599   *         and is intended to replace factory calibration default values.
00600   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
00601   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
00602   * @param  DACx DAC instance
00603   * @param  DAC_Channel This parameter can be one of the following values:
00604   *         @arg @ref LL_DAC_CHANNEL_1
00605   *         @arg @ref LL_DAC_CHANNEL_2
00606   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
00610 {
00611   MODIFY_REG(DACx->CCR,
00612              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00613              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00614 }
00615
00616 /**
00617   * @brief  Get the offset trimming value for the selected DAC channel.
00618   *         Trimming has an impact when output buffer is enabled
00619   *         and is intended to replace factory calibration default values.
00620   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
00621   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
00622   * @param  DACx DAC instance
00623   * @param  DAC_Channel This parameter can be one of the following values:
00624   *         @arg @ref LL_DAC_CHANNEL_1
00625   *         @arg @ref LL_DAC_CHANNEL_2
00626   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00627   */
00628 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00629 {
00630   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00631                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00632                    );
00633 }
00634
00635 /**
00636   * @brief  Set the conversion trigger source for the selected DAC channel.
00637   * @note   For conversion trigger source to be effective, DAC trigger
00638   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00639   * @note   To set conversion trigger source, DAC channel must be disabled.
00640   *         Otherwise, the setting is discarded.
00641   * @note   Availability of parameters of trigger sources from timer
00642   *         depends on timers availability on the selected device.
00643   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00644   *         CR       TSEL2          LL_DAC_SetTriggerSource
00645   * @param  DACx DAC instance
00646   * @param  DAC_Channel This parameter can be one of the following values:
00647   *         @arg @ref LL_DAC_CHANNEL_1
00648   *         @arg @ref LL_DAC_CHANNEL_2
00649   * @param  TriggerSource This parameter can be one of the following values:
00650   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00651   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
00652   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00653   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00654   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00655   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00656   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00657   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00658   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00659   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)
00660   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)
00661   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
00662   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
00663   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)
00664   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00665   *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)
00666   *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)
00667   *
00668   *         (1) On this STM32 serie, parameter not available on all devices.
00669   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
00670   *         (2) On this STM32 serie, parameter only available on DAC2.
00671   *         (3) On this STM32 serie, parameter not available on all devices.
00672   *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
00673   *         (4) On this STM32 serie, parameter not available on all devices.
00674   *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00678 {
00679   MODIFY_REG(DACx->CR,
00680              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00681              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00682 }
00683
00684 /**
00685   * @brief  Get the conversion trigger source for the selected DAC channel.
00686   * @note   For conversion trigger source to be effective, DAC trigger
00687   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00688   * @note   Availability of parameters of trigger sources from timer
00689   *         depends on timers availability on the selected device.
00690   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00691   *         CR       TSEL2          LL_DAC_GetTriggerSource
00692   * @param  DACx DAC instance
00693   * @param  DAC_Channel This parameter can be one of the following values:
00694   *         @arg @ref LL_DAC_CHANNEL_1
00695   *         @arg @ref LL_DAC_CHANNEL_2
00696   * @retval Returned value can be one of the following values:
00697   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00698   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
00699   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00700   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00701   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00702   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00703   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00704   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00705   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00706   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)
00707   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)
00708   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
00709   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
00710   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)
00711   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00712   *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)
00713   *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)
00714   *
00715   *         (1) On this STM32 serie, parameter not available on all devices.
00716   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
00717   *         (2) On this STM32 serie, parameter only available on DAC2.
00718   *         (3) On this STM32 serie, parameter not available on all devices.
00719   *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
00720   *         (4) On this STM32 serie, parameter not available on all devices.
00721   *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
00722   */
00723 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00724 {
00725   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00726                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00727                    );
00728 }
00729
00730 /**
00731   * @brief  Set the waveform automatic generation mode
00732   *         for the selected DAC channel.
00733   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00734   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00735   * @param  DACx DAC instance
00736   * @param  DAC_Channel This parameter can be one of the following values:
00737   *         @arg @ref LL_DAC_CHANNEL_1
00738   *         @arg @ref LL_DAC_CHANNEL_2
00739   * @param  WaveAutoGeneration This parameter can be one of the following values:
00740   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00741   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00742   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00743   * @retval None
00744   */
00745 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00746 {
00747   MODIFY_REG(DACx->CR,
00748              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00749              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00750 }
00751
00752 /**
00753   * @brief  Get the waveform automatic generation mode
00754   *         for the selected DAC channel.
00755   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00756   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00757   * @param  DACx DAC instance
00758   * @param  DAC_Channel This parameter can be one of the following values:
00759   *         @arg @ref LL_DAC_CHANNEL_1
00760   *         @arg @ref LL_DAC_CHANNEL_2
00761   * @retval Returned value can be one of the following values:
00762   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00763   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00764   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00765   */
00766 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00767 {
00768   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00769                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00770                    );
00771 }
00772
00773 /**
00774   * @brief  Set the noise waveform generation for the selected DAC channel:
00775   *         Noise mode and parameters LFSR (linear feedback shift register).
00776   * @note   For wave generation to be effective, DAC channel
00777   *         wave generation mode must be enabled using
00778   *         function @ref LL_DAC_SetWaveAutoGeneration().
00779   * @note   This setting can be set when the selected DAC channel is disabled
00780   *         (otherwise, the setting operation is ignored).
00781   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00782   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00783   * @param  DACx DAC instance
00784   * @param  DAC_Channel This parameter can be one of the following values:
00785   *         @arg @ref LL_DAC_CHANNEL_1
00786   *         @arg @ref LL_DAC_CHANNEL_2
00787   * @param  NoiseLFSRMask This parameter can be one of the following values:
00788   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00789   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00790   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00791   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00792   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00793   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00794   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00795   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00796   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00797   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00798   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00799   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00800   * @retval None
00801   */
00802 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00803 {
00804   MODIFY_REG(DACx->CR,
00805              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00806              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00807 }
00808
00809 /**
00810   * @brief  Get the noise waveform generation for the selected DAC channel:
00811   *         Noise mode and parameters LFSR (linear feedback shift register).
00812   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00813   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00814   * @param  DACx DAC instance
00815   * @param  DAC_Channel This parameter can be one of the following values:
00816   *         @arg @ref LL_DAC_CHANNEL_1
00817   *         @arg @ref LL_DAC_CHANNEL_2
00818   * @retval Returned value can be one of the following values:
00819   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00820   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00821   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00822   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00823   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00824   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00825   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00826   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00827   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00828   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00829   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00830   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00831   */
00832 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00833 {
00834   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00835                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00836                    );
00837 }
00838
00839 /**
00840   * @brief  Set the triangle waveform generation for the selected DAC channel:
00841   *         triangle mode and amplitude.
00842   * @note   For wave generation to be effective, DAC channel
00843   *         wave generation mode must be enabled using
00844   *         function @ref LL_DAC_SetWaveAutoGeneration().
00845   * @note   This setting can be set when the selected DAC channel is disabled
00846   *         (otherwise, the setting operation is ignored).
00847   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00848   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00849   * @param  DACx DAC instance
00850   * @param  DAC_Channel This parameter can be one of the following values:
00851   *         @arg @ref LL_DAC_CHANNEL_1
00852   *         @arg @ref LL_DAC_CHANNEL_2
00853   * @param  TriangleAmplitude This parameter can be one of the following values:
00854   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00855   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00856   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00857   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00858   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00859   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00860   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00861   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00862   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00863   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00864   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00865   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00866   * @retval None
00867   */
00868 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
00869                                                      uint32_t TriangleAmplitude)
00870 {
00871   MODIFY_REG(DACx->CR,
00872              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00873              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00874 }
00875
00876 /**
00877   * @brief  Get the triangle waveform generation for the selected DAC channel:
00878   *         triangle mode and amplitude.
00879   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00880   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00881   * @param  DACx DAC instance
00882   * @param  DAC_Channel This parameter can be one of the following values:
00883   *         @arg @ref LL_DAC_CHANNEL_1
00884   *         @arg @ref LL_DAC_CHANNEL_2
00885   * @retval Returned value can be one of the following values:
00886   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00887   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00888   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00889   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00890   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00891   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00892   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00893   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00894   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00895   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00896   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00897   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00898   */
00899 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00900 {
00901   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00902                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00903                    );
00904 }
00905
00906 /**
00907   * @brief  Set the output for the selected DAC channel.
00908   * @note   This function set several features:
00909   *         - mode normal or sample-and-hold
00910   *         - buffer
00911   *         - connection to GPIO or internal path.
00912   *         These features can also be set individually using
00913   *         dedicated functions:
00914   *         - @ref LL_DAC_SetOutputBuffer()
00915   *         - @ref LL_DAC_SetOutputMode()
00916   *         - @ref LL_DAC_SetOutputConnection()
00917   * @note   On this STM32 serie, output connection depends on output mode
00918   *         (normal or sample and hold) and output buffer state.
00919   *         - if output connection is set to internal path and output buffer
00920   *           is enabled (whatever output mode):
00921   *           output connection is also connected to GPIO pin
00922   *           (both connections to GPIO pin and internal path).
00923   *         - if output connection is set to GPIO pin, output buffer
00924   *           is disabled, output mode set to sample and hold:
00925   *           output connection is also connected to internal path
00926   *           (both connections to GPIO pin and internal path).
00927   * @note   Mode sample-and-hold requires an external capacitor
00928   *         to be connected between DAC channel output and ground.
00929   *         Capacitor value depends on load on DAC channel output and
00930   *         sample-and-hold timings configured.
00931   *         As indication, capacitor typical value is 100nF
00932   *         (refer to device datasheet, parameter "CSH").
00933   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
00934   *         CR       MODE2          LL_DAC_ConfigOutput
00935   * @param  DACx DAC instance
00936   * @param  DAC_Channel This parameter can be one of the following values:
00937   *         @arg @ref LL_DAC_CHANNEL_1
00938   *         @arg @ref LL_DAC_CHANNEL_2
00939   * @param  OutputMode This parameter can be one of the following values:
00940   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00941   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00942   * @param  OutputBuffer This parameter can be one of the following values:
00943   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00944   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00945   * @param  OutputConnection This parameter can be one of the following values:
00946   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
00947   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
00948   * @retval None
00949   */
00950 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
00951                                          uint32_t OutputBuffer, uint32_t OutputConnection)
00952 {
00953   MODIFY_REG(DACx->MCR,
00954              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00955              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00956 }
00957
00958 /**
00959   * @brief  Set the output mode normal or sample-and-hold
00960   *         for the selected DAC channel.
00961   * @note   Mode sample-and-hold requires an external capacitor
00962   *         to be connected between DAC channel output and ground.
00963   *         Capacitor value depends on load on DAC channel output and
00964   *         sample-and-hold timings configured.
00965   *         As indication, capacitor typical value is 100nF
00966   *         (refer to device datasheet, parameter "CSH").
00967   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
00968   *         CR       MODE2          LL_DAC_SetOutputMode
00969   * @param  DACx DAC instance
00970   * @param  DAC_Channel This parameter can be one of the following values:
00971   *         @arg @ref LL_DAC_CHANNEL_1
00972   *         @arg @ref LL_DAC_CHANNEL_2
00973   * @param  OutputMode This parameter can be one of the following values:
00974   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00975   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00976   * @retval None
00977   */
00978 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
00979 {
00980   MODIFY_REG(DACx->MCR,
00981              (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00982              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00983 }
00984
00985 /**
00986   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
00987   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
00988   *         CR       MODE2          LL_DAC_GetOutputMode
00989   * @param  DACx DAC instance
00990   * @param  DAC_Channel This parameter can be one of the following values:
00991   *         @arg @ref LL_DAC_CHANNEL_1
00992   *         @arg @ref LL_DAC_CHANNEL_2
00993   * @retval Returned value can be one of the following values:
00994   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00995   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00996   */
00997 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00998 {
00999   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01000                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01001                    );
01002 }
01003
01004 /**
01005   * @brief  Set the output buffer for the selected DAC channel.
01006   * @note   On this STM32 serie, when buffer is enabled, its offset can be
01007   *         trimmed: factory calibration default values can be
01008   *         replaced by user trimming values, using function
01009   *         @ref LL_DAC_SetTrimmingValue().
01010   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
01011   *         CR       MODE2          LL_DAC_SetOutputBuffer
01012   * @param  DACx DAC instance
01013   * @param  DAC_Channel This parameter can be one of the following values:
01014   *         @arg @ref LL_DAC_CHANNEL_1
01015   *         @arg @ref LL_DAC_CHANNEL_2
01016   * @param  OutputBuffer This parameter can be one of the following values:
01017   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01018   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01019   * @retval None
01020   */
01021 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
01022 {
01023   MODIFY_REG(DACx->MCR,
01024              (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01025              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01026 }
01027
01028 /**
01029   * @brief  Get the output buffer state for the selected DAC channel.
01030   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
01031   *         CR       MODE2          LL_DAC_GetOutputBuffer
01032   * @param  DACx DAC instance
01033   * @param  DAC_Channel This parameter can be one of the following values:
01034   *         @arg @ref LL_DAC_CHANNEL_1
01035   *         @arg @ref LL_DAC_CHANNEL_2
01036   * @retval Returned value can be one of the following values:
01037   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01038   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01039   */
01040 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01041 {
01042   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01043                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01044                    );
01045 }
01046
01047 /**
01048   * @brief  Set the output connection for the selected DAC channel.
01049   * @note   On this STM32 serie, output connection depends on output mode (normal or
01050   *         sample and hold) and output buffer state.
01051   *         - if output connection is set to internal path and output buffer
01052   *           is enabled (whatever output mode):
01053   *           output connection is also connected to GPIO pin
01054   *           (both connections to GPIO pin and internal path).
01055   *         - if output connection is set to GPIO pin, output buffer
01056   *           is disabled, output mode set to sample and hold:
01057   *           output connection is also connected to internal path
01058   *           (both connections to GPIO pin and internal path).
01059   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
01060   *         CR       MODE2          LL_DAC_SetOutputConnection
01061   * @param  DACx DAC instance
01062   * @param  DAC_Channel This parameter can be one of the following values:
01063   *         @arg @ref LL_DAC_CHANNEL_1
01064   *         @arg @ref LL_DAC_CHANNEL_2
01065   * @param  OutputConnection This parameter can be one of the following values:
01066   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01067   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01068   * @retval None
01069   */
01070 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
01071 {
01072   MODIFY_REG(DACx->MCR,
01073              (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01074              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01075 }
01076
01077 /**
01078   * @brief  Get the output connection for the selected DAC channel.
01079   * @note   On this STM32 serie, output connection depends on output mode (normal or
01080   *         sample and hold) and output buffer state.
01081   *         - if output connection is set to internal path and output buffer
01082   *           is enabled (whatever output mode):
01083   *           output connection is also connected to GPIO pin
01084   *           (both connections to GPIO pin and internal path).
01085   *         - if output connection is set to GPIO pin, output buffer
01086   *           is disabled, output mode set to sample and hold:
01087   *           output connection is also connected to internal path
01088   *           (both connections to GPIO pin and internal path).
01089   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
01090   *         CR       MODE2          LL_DAC_GetOutputConnection
01091   * @param  DACx DAC instance
01092   * @param  DAC_Channel This parameter can be one of the following values:
01093   *         @arg @ref LL_DAC_CHANNEL_1
01094   *         @arg @ref LL_DAC_CHANNEL_2
01095   * @retval Returned value can be one of the following values:
01096   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01097   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01098   */
01099 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01100 {
01101   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01102                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01103                    );
01104 }
01105
01106 /**
01107   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01108   *         sample time
01109   * @note   Sample time must be set when DAC channel is disabled
01110   *         or during DAC operation when DAC channel flag BWSTx is reset,
01111   *         otherwise the setting is ignored.
01112   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
01113   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
01114   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
01115   * @param  DACx DAC instance
01116   * @param  DAC_Channel This parameter can be one of the following values:
01117   *         @arg @ref LL_DAC_CHANNEL_1
01118   *         @arg @ref LL_DAC_CHANNEL_2
01119   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
01120   * @retval None
01121   */
01122 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
01123 {
01124   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01125
01126   MODIFY_REG(*preg,
01127              DAC_SHSR1_TSAMPLE1,
01128              SampleTime);
01129 }
01130
01131 /**
01132   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01133   *         sample time
01134   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
01135   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
01136   * @param  DACx DAC instance
01137   * @param  DAC_Channel This parameter can be one of the following values:
01138   *         @arg @ref LL_DAC_CHANNEL_1
01139   *         @arg @ref LL_DAC_CHANNEL_2
01140   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01141   */
01142 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01143 {
01144   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01145
01146   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
01147 }
01148
01149 /**
01150   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01151   *         hold time
01152   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
01153   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
01154   * @param  DACx DAC instance
01155   * @param  DAC_Channel This parameter can be one of the following values:
01156   *         @arg @ref LL_DAC_CHANNEL_1
01157   *         @arg @ref LL_DAC_CHANNEL_2
01158   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
01159   * @retval None
01160   */
01161 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
01162 {
01163   MODIFY_REG(DACx->SHHR,
01164              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01165              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01166 }
01167
01168 /**
01169   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01170   *         hold time
01171   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
01172   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
01173   * @param  DACx DAC instance
01174   * @param  DAC_Channel This parameter can be one of the following values:
01175   *         @arg @ref LL_DAC_CHANNEL_1
01176   *         @arg @ref LL_DAC_CHANNEL_2
01177   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01178   */
01179 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01180 {
01181   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01182                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01183                    );
01184 }
01185
01186 /**
01187   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01188   *         refresh time
01189   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
01190   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
01191   * @param  DACx DAC instance
01192   * @param  DAC_Channel This parameter can be one of the following values:
01193   *         @arg @ref LL_DAC_CHANNEL_1
01194   *         @arg @ref LL_DAC_CHANNEL_2
01195   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
01196   * @retval None
01197   */
01198 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
01199 {
01200   MODIFY_REG(DACx->SHRR,
01201              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01202              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01203 }
01204
01205 /**
01206   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01207   *         refresh time
01208   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
01209   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
01210   * @param  DACx DAC instance
01211   * @param  DAC_Channel This parameter can be one of the following values:
01212   *         @arg @ref LL_DAC_CHANNEL_1
01213   *         @arg @ref LL_DAC_CHANNEL_2
01214   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01215   */
01216 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01217 {
01218   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01219                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01220                    );
01221 }
01222
01223 /**
01224   * @}
01225   */
01226
01227 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
01228   * @{
01229   */
01230
01231 /**
01232   * @brief  Enable DAC DMA transfer request of the selected channel.
01233   * @note   To configure DMA source address (peripheral address),
01234   *         use function @ref LL_DAC_DMA_GetRegAddr().
01235   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
01236   *         CR       DMAEN2         LL_DAC_EnableDMAReq
01237   * @param  DACx DAC instance
01238   * @param  DAC_Channel This parameter can be one of the following values:
01239   *         @arg @ref LL_DAC_CHANNEL_1
01240   *         @arg @ref LL_DAC_CHANNEL_2
01241   * @retval None
01242   */
01243 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01244 {
01245   SET_BIT(DACx->CR,
01246           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01247 }
01248
01249 /**
01250   * @brief  Disable DAC DMA transfer request of the selected channel.
01251   * @note   To configure DMA source address (peripheral address),
01252   *         use function @ref LL_DAC_DMA_GetRegAddr().
01253   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
01254   *         CR       DMAEN2         LL_DAC_DisableDMAReq
01255   * @param  DACx DAC instance
01256   * @param  DAC_Channel This parameter can be one of the following values:
01257   *         @arg @ref LL_DAC_CHANNEL_1
01258   *         @arg @ref LL_DAC_CHANNEL_2
01259   * @retval None
01260   */
01261 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01262 {
01263   CLEAR_BIT(DACx->CR,
01264             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01265 }
01266
01267 /**
01268   * @brief  Get DAC DMA transfer request state of the selected channel.
01269   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
01270   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
01271   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
01272   * @param  DACx DAC instance
01273   * @param  DAC_Channel This parameter can be one of the following values:
01274   *         @arg @ref LL_DAC_CHANNEL_1
01275   *         @arg @ref LL_DAC_CHANNEL_2
01276   * @retval State of bit (1 or 0).
01277   */
01278 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01279 {
01280   return ((READ_BIT(DACx->CR,
01281                     DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01282            == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01283 }
01284
01285 /**
01286   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
01287   *         DAC register address from DAC instance and a list of DAC registers
01288   *         intended to be used (most commonly) with DMA transfer.
01289   * @note   These DAC registers are data holding registers:
01290   *         when DAC conversion is requested, DAC generates a DMA transfer
01291   *         request to have data available in DAC data holding registers.
01292   * @note   This macro is intended to be used with LL DMA driver, refer to
01293   *         function "LL_DMA_ConfigAddresses()".
01294   *         Example:
01295   *           LL_DMA_ConfigAddresses(DMA1,
01296   *                                  LL_DMA_CHANNEL_1,
01297   *                                  (uint32_t)&< array or variable >,
01298   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
01299   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
01300   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01301   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01302   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01303   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01304   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01305   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
01306   * @param  DACx DAC instance
01307   * @param  DAC_Channel This parameter can be one of the following values:
01308   *         @arg @ref LL_DAC_CHANNEL_1
01309   *         @arg @ref LL_DAC_CHANNEL_2
01310   * @param  Register This parameter can be one of the following values:
01311   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
01312   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
01313   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
01314   * @retval DAC register address
01315   */
01316 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
01317 {
01318   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
01319   /* DAC channel selected.                                                    */
01320   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
01321                                           ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
01322 }
01323 /**
01324   * @}
01325   */
01326
01327 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
01328   * @{
01329   */
01330
01331 /**
01332   * @brief  Enable DAC selected channel.
01333   * @rmtoll CR       EN1            LL_DAC_Enable\n
01334   *         CR       EN2            LL_DAC_Enable
01335   * @note   After enable from off state, DAC channel requires a delay
01336   *         for output voltage to reach accuracy +/- 1 LSB.
01337   *         Refer to device datasheet, parameter "tWAKEUP".
01338   * @param  DACx DAC instance
01339   * @param  DAC_Channel This parameter can be one of the following values:
01340   *         @arg @ref LL_DAC_CHANNEL_1
01341   *         @arg @ref LL_DAC_CHANNEL_2
01342   * @retval None
01343   */
01344 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01345 {
01346   SET_BIT(DACx->CR,
01347           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01348 }
01349
01350 /**
01351   * @brief  Disable DAC selected channel.
01352   * @rmtoll CR       EN1            LL_DAC_Disable\n
01353   *         CR       EN2            LL_DAC_Disable
01354   * @param  DACx DAC instance
01355   * @param  DAC_Channel This parameter can be one of the following values:
01356   *         @arg @ref LL_DAC_CHANNEL_1
01357   *         @arg @ref LL_DAC_CHANNEL_2
01358   * @retval None
01359   */
01360 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01361 {
01362   CLEAR_BIT(DACx->CR,
01363             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01364 }
01365
01366 /**
01367   * @brief  Get DAC enable state of the selected channel.
01368   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
01369   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
01370   *         CR       EN2            LL_DAC_IsEnabled
01371   * @param  DACx DAC instance
01372   * @param  DAC_Channel This parameter can be one of the following values:
01373   *         @arg @ref LL_DAC_CHANNEL_1
01374   *         @arg @ref LL_DAC_CHANNEL_2
01375   * @retval State of bit (1 or 0).
01376   */
01377 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01378 {
01379   return ((READ_BIT(DACx->CR,
01380                     DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01381            == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01382 }
01383
01384 /**
01385   * @brief  Enable DAC trigger of the selected channel.
01386   * @note   - If DAC trigger is disabled, DAC conversion is performed
01387   *           automatically once the data holding register is updated,
01388   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01389   *           @ref LL_DAC_ConvertData12RightAligned(), ...
01390   *         - If DAC trigger is enabled, DAC conversion is performed
01391   *           only when a hardware of software trigger event is occurring.
01392   *           Select trigger source using
01393   *           function @ref LL_DAC_SetTriggerSource().
01394   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
01395   *         CR       TEN2           LL_DAC_EnableTrigger
01396   * @param  DACx DAC instance
01397   * @param  DAC_Channel This parameter can be one of the following values:
01398   *         @arg @ref LL_DAC_CHANNEL_1
01399   *         @arg @ref LL_DAC_CHANNEL_2
01400   * @retval None
01401   */
01402 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01403 {
01404   SET_BIT(DACx->CR,
01405           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01406 }
01407
01408 /**
01409   * @brief  Disable DAC trigger of the selected channel.
01410   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
01411   *         CR       TEN2           LL_DAC_DisableTrigger
01412   * @param  DACx DAC instance
01413   * @param  DAC_Channel This parameter can be one of the following values:
01414   *         @arg @ref LL_DAC_CHANNEL_1
01415   *         @arg @ref LL_DAC_CHANNEL_2
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01419 {
01420   CLEAR_BIT(DACx->CR,
01421             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01422 }
01423
01424 /**
01425   * @brief  Get DAC trigger state of the selected channel.
01426   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
01427   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
01428   *         CR       TEN2           LL_DAC_IsTriggerEnabled
01429   * @param  DACx DAC instance
01430   * @param  DAC_Channel This parameter can be one of the following values:
01431   *         @arg @ref LL_DAC_CHANNEL_1
01432   *         @arg @ref LL_DAC_CHANNEL_2
01433   * @retval State of bit (1 or 0).
01434   */
01435 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01436 {
01437   return ((READ_BIT(DACx->CR,
01438                     DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01439            == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01440 }
01441
01442 /**
01443   * @brief  Trig DAC conversion by software for the selected DAC channel.
01444   * @note   Preliminarily, DAC trigger must be set to software trigger
01445   *         using function
01446   *           @ref LL_DAC_Init()
01447   *           @ref LL_DAC_SetTriggerSource()
01448   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01449   *         and DAC trigger must be enabled using
01450   *         function @ref LL_DAC_EnableTrigger().
01451   * @note   For devices featuring DAC with 2 channels: this function
01452   *         can perform a SW start of both DAC channels simultaneously.
01453   *         Two channels can be selected as parameter.
01454   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01455   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01456   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01457   * @param  DACx DAC instance
01458   * @param  DAC_Channel  This parameter can a combination of the following values:
01459   *         @arg @ref LL_DAC_CHANNEL_1
01460   *         @arg @ref LL_DAC_CHANNEL_2
01461   * @retval None
01462   */
01463 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01464 {
01465   SET_BIT(DACx->SWTRIGR,
01466           (DAC_Channel & DAC_SWTR_CHX_MASK));
01467 }
01468
01469 /**
01470   * @brief  Set the data to be loaded in the data holding register
01471   *         in format 12 bits left alignment (LSB aligned on bit 0),
01472   *         for the selected DAC channel.
01473   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01474   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01475   * @param  DACx DAC instance
01476   * @param  DAC_Channel This parameter can be one of the following values:
01477   *         @arg @ref LL_DAC_CHANNEL_1
01478   *         @arg @ref LL_DAC_CHANNEL_2
01479   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01480   * @retval None
01481   */
01482 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01483 {
01484   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01485
01486   MODIFY_REG(*preg,
01487              DAC_DHR12R1_DACC1DHR,
01488              Data);
01489 }
01490
01491 /**
01492   * @brief  Set the data to be loaded in the data holding register
01493   *         in format 12 bits left alignment (MSB aligned on bit 15),
01494   *         for the selected DAC channel.
01495   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01496   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01497   * @param  DACx DAC instance
01498   * @param  DAC_Channel This parameter can be one of the following values:
01499   *         @arg @ref LL_DAC_CHANNEL_1
01500   *         @arg @ref LL_DAC_CHANNEL_2
01501   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01502   * @retval None
01503   */
01504 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01505 {
01506   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01507
01508   MODIFY_REG(*preg,
01509              DAC_DHR12L1_DACC1DHR,
01510              Data);
01511 }
01512
01513 /**
01514   * @brief  Set the data to be loaded in the data holding register
01515   *         in format 8 bits left alignment (LSB aligned on bit 0),
01516   *         for the selected DAC channel.
01517   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01518   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01519   * @param  DACx DAC instance
01520   * @param  DAC_Channel This parameter can be one of the following values:
01521   *         @arg @ref LL_DAC_CHANNEL_1
01522   *         @arg @ref LL_DAC_CHANNEL_2
01523   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01524   * @retval None
01525   */
01526 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01527 {
01528   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01529
01530   MODIFY_REG(*preg,
01531              DAC_DHR8R1_DACC1DHR,
01532              Data);
01533 }
01534
01535
01536 /**
01537   * @brief  Set the data to be loaded in the data holding register
01538   *         in format 12 bits left alignment (LSB aligned on bit 0),
01539   *         for both DAC channels.
01540   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01541   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01542   * @param  DACx DAC instance
01543   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01544   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01545   * @retval None
01546   */
01547 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01548                                                           uint32_t DataChannel2)
01549 {
01550   MODIFY_REG(DACx->DHR12RD,
01551              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01552              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01553 }
01554
01555 /**
01556   * @brief  Set the data to be loaded in the data holding register
01557   *         in format 12 bits left alignment (MSB aligned on bit 15),
01558   *         for both DAC channels.
01559   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01560   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01561   * @param  DACx DAC instance
01562   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01563   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01564   * @retval None
01565   */
01566 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01567                                                          uint32_t DataChannel2)
01568 {
01569   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01570   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01571   /*       the 4 LSB must be taken into account for the shift value.          */
01572   MODIFY_REG(DACx->DHR12LD,
01573              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01574              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01575 }
01576
01577 /**
01578   * @brief  Set the data to be loaded in the data holding register
01579   *         in format 8 bits left alignment (LSB aligned on bit 0),
01580   *         for both DAC channels.
01581   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01582   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01583   * @param  DACx DAC instance
01584   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01585   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01586   * @retval None
01587   */
01588 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01589                                                          uint32_t DataChannel2)
01590 {
01591   MODIFY_REG(DACx->DHR8RD,
01592              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01593              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01594 }
01595
01596
01597 /**
01598   * @brief  Retrieve output data currently generated for the selected DAC channel.
01599   * @note   Whatever alignment and resolution settings
01600   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01601   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01602   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01603   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01604   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01605   * @param  DACx DAC instance
01606   * @param  DAC_Channel This parameter can be one of the following values:
01607   *         @arg @ref LL_DAC_CHANNEL_1
01608   *         @arg @ref LL_DAC_CHANNEL_2
01609   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01610   */
01611 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01612 {
01613   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
01614
01615   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01616 }
01617
01618 /**
01619   * @}
01620   */
01621
01622 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01623   * @{
01624   */
01625 /**
01626   * @brief  Get DAC calibration offset flag for DAC channel 1
01627   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
01628   * @param  DACx DAC instance
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
01632 {
01633   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
01634 }
01635
01636
01637 /**
01638   * @brief  Get DAC calibration offset flag for DAC channel 2
01639   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
01640   * @param  DACx DAC instance
01641   * @retval State of bit (1 or 0).
01642   */
01643 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
01644 {
01645   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
01646 }
01647
01648
01649 /**
01650   * @brief  Get DAC busy writing sample time flag for DAC channel 1
01651   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
01652   * @param  DACx DAC instance
01653   * @retval State of bit (1 or 0).
01654   */
01655 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
01656 {
01657   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
01658 }
01659
01660
01661 /**
01662   * @brief  Get DAC busy writing sample time flag for DAC channel 2
01663   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
01664   * @param  DACx DAC instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
01668 {
01669   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
01670 }
01671
01672
01673 /**
01674   * @brief  Get DAC underrun flag for DAC channel 1
01675   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01676   * @param  DACx DAC instance
01677   * @retval State of bit (1 or 0).
01678   */
01679 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01680 {
01681   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
01682 }
01683
01684
01685 /**
01686   * @brief  Get DAC underrun flag for DAC channel 2
01687   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01688   * @param  DACx DAC instance
01689   * @retval State of bit (1 or 0).
01690   */
01691 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01692 {
01693   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
01694 }
01695
01696
01697 /**
01698   * @brief  Clear DAC underrun flag for DAC channel 1
01699   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01700   * @param  DACx DAC instance
01701   * @retval None
01702   */
01703 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01704 {
01705   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01706 }
01707
01708
01709 /**
01710   * @brief  Clear DAC underrun flag for DAC channel 2
01711   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01712   * @param  DACx DAC instance
01713   * @retval None
01714   */
01715 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01716 {
01717   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01718 }
01719
01720
01721 /**
01722   * @}
01723   */
01724
01725 /** @defgroup DAC_LL_EF_IT_Management IT management
01726   * @{
01727   */
01728
01729 /**
01730   * @brief  Enable DMA underrun interrupt for DAC channel 1
01731   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01732   * @param  DACx DAC instance
01733   * @retval None
01734   */
01735 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01736 {
01737   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01738 }
01739
01740
01741 /**
01742   * @brief  Enable DMA underrun interrupt for DAC channel 2
01743   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01744   * @param  DACx DAC instance
01745   * @retval None
01746   */
01747 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01748 {
01749   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01750 }
01751
01752
01753 /**
01754   * @brief  Disable DMA underrun interrupt for DAC channel 1
01755   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01756   * @param  DACx DAC instance
01757   * @retval None
01758   */
01759 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01760 {
01761   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01762 }
01763
01764
01765 /**
01766   * @brief  Disable DMA underrun interrupt for DAC channel 2
01767   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01768   * @param  DACx DAC instance
01769   * @retval None
01770   */
01771 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01772 {
01773   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01774 }
01775
01776
01777 /**
01778   * @brief  Get DMA underrun interrupt for DAC channel 1
01779   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01780   * @param  DACx DAC instance
01781   * @retval State of bit (1 or 0).
01782   */
01783 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01784 {
01785   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
01786 }
01787
01788
01789 /**
01790   * @brief  Get DMA underrun interrupt for DAC channel 2
01791   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01792   * @param  DACx DAC instance
01793   * @retval State of bit (1 or 0).
01794   */
01795 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01796 {
01797   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
01798 }
01799
01800
01801 /**
01802   * @}
01803   */
01804
01805 #if defined(USE_FULL_LL_DRIVER)
01806 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01807   * @{
01808   */
01809
01810 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
01811 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
01812 void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
01813
01814 /**
01815   * @}
01816   */
01817 #endif /* USE_FULL_LL_DRIVER */
01818
01819 /**
01820   * @}
01821   */
01822
01823 /**
01824   * @}
01825   */
01826
01827 #endif /* DAC1 || DAC2 */
01828
01829 /**
01830   * @}
01831   */
01832
01833 #ifdef __cplusplus
01834 }
01835 #endif
01836
01837 #endif /* STM32H7xx_LL_DAC_H */
01838
01839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_delayblock.c Source File

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stm32h7xx_ll_delayblock.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_delayblock.c
00004   * @author  MCD Application Team
00005   * @brief   DelayBlock Low Layer HAL module driver.
00006   *
00007   *          This file provides firmware functions to manage the following
00008   *          functionalities of the Delay Block peripheral:
00009   *           + input clock frequency range 25MHz to 208MHz
00010   *           + up to 12 oversampling phases
00011   *
00012   @verbatim
00013   ==============================================================================
00014                        ##### DelayBlock peripheral features #####
00015   ==============================================================================
00016     [..] The Delay block is used to generate an Output clock which is de-phased from the Input
00017           clock. The phase of the Output clock is programmed by FW. The Output clock is then used
00018           to clock the receive data in i.e. a SDMMC or QSPI interface.
00019          The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
00020           and recenter the Output clock phase to the receive data.
00021
00022     [..] The Delay Block features include the following:
00023          (+) Input clock frequency range 25MHz to 208MHz.
00024          (+) Up to 12 oversampling phases.
00025
00026                            ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029       This driver is a considered as a driver of service for external devices drivers
00030       that interfaces with the DELAY peripheral.
00031       The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
00032       and configure the Output clock phase.
00033       The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
00034
00035
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00041   * All rights reserved.</center></h2>
00042   *
00043   * This software component is licensed by ST under BSD 3-Clause license,
00044   * the "License"; You may not use this file except in compliance with the
00045   * License. You may obtain a copy of the License at:
00046   *                        opensource.org/licenses/BSD-3-Clause
00047   *
00048   ******************************************************************************
00049   */
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32h7xx_hal.h"
00053
00054 /** @addtogroup STM32H7xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @defgroup DELAYBLOCK_LL DELAYBLOCK_LL
00059   * @brief Low layer module for Delay Block
00060   * @{
00061   */
00062
00063 #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 #define DLYB_TIMEOUT 0xFFU
00068 /* Private macro -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private function prototypes -----------------------------------------------*/
00071 /* Exported functions --------------------------------------------------------*/
00072
00073 /** @defgroup DelayBlock_LL_Exported_Functions Delay Block Low Layer Exported Functions
00074   * @{
00075   */
00076
00077 /** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
00078  *  @brief    Initialization and Configuration functions
00079  *
00080 @verbatim
00081  ===============================================================================
00082               ##### Initialization and de-initialization functions #####
00083  ===============================================================================
00084     [..]  This section provides functions allowing to:
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090
00091 /**
00092   * @brief  Enable the Delay Block instance.
00093   * @param  DLYBx: Pointer to DLYB instance.
00094   * @retval HAL status
00095   */
00096 HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx)
00097 {
00098   uint32_t unit = 0U;
00099   uint32_t sel = 0U;
00100   uint32_t sel_current;
00101   uint32_t unit_current;
00102   uint32_t tuning;
00103   uint32_t lng_mask;
00104   uint32_t tickstart;
00105
00106   DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN;
00107
00108   for (sel_current = 0U; sel_current < DLYB_MAX_SELECT; sel_current++)
00109   {
00110     /* lng_mask is the mask bit for the LNG field to check the output of the UNITx*/
00111     lng_mask = DLYB_CFGR_LNG_0 << sel_current;
00112     tuning = 0U;
00113     for (unit_current = 0U; unit_current < DLYB_MAX_UNIT; unit_current++)
00114     {
00115       /* Set the Delay of the UNIT(s)*/
00116       DLYBx->CFGR = DLYB_MAX_SELECT | (unit_current << DLYB_CFGR_UNIT_Pos);
00117
00118       /* Waiting for a LNG valid value */
00119       tickstart =  HAL_GetTick();
00120       while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
00121       {
00122         if((HAL_GetTick() - tickstart) >=  DLYB_TIMEOUT)
00123         {
00124           return HAL_TIMEOUT;
00125         }
00126       }
00127       if (tuning == 0U)
00128       {
00129         if ((DLYBx->CFGR & lng_mask) != 0U)
00130         {
00131           /* 1/2 period HIGH is detected */
00132           tuning = 1U;
00133         }
00134       }
00135       else
00136       {
00137         /* 1/2 period LOW detected after the HIGH 1/2 period => FULL PERIOD passed*/
00138         if((DLYBx->CFGR & lng_mask ) == 0U)
00139         {
00140           /* Save the first result */
00141           if( unit == 0U )
00142           {
00143             unit = unit_current;
00144             sel  = sel_current + 1U;
00145           }
00146           break;
00147         }
00148       }
00149     }
00150   }
00151
00152   /* Apply the Tuning settings */
00153   DLYBx->CR   = 0U;
00154   DLYBx->CR   = DLYB_CR_DEN | DLYB_CR_SEN;
00155   DLYBx->CFGR = sel | (unit << DLYB_CFGR_UNIT_Pos);
00156   DLYBx->CR   = DLYB_CR_DEN;
00157
00158   return HAL_OK;
00159 }
00160
00161 /**
00162   * @brief  Disable the Delay Block instance.
00163   * @param  DLYBx: Pointer to DLYB instance.
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx)
00167 {
00168   /* Disable DLYB */
00169   DLYBx->CR = 0U;
00170   return HAL_OK;
00171 }
00172
00173 /**
00174   * @brief  Configure the Delay Block instance.
00175   * @param  DLYBx: Pointer to DLYB instance.
00176   * @param  PhaseSel: Phase selection [0..11].
00177   * @param  Units: Delay units[0..127].
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx,uint32_t PhaseSel, uint32_t Units )
00181 {
00182   /* Apply the delay settings */
00183
00184   DLYBx->CR   = 0U;
00185   DLYBx->CR   = DLYB_CR_DEN | DLYB_CR_SEN;
00186   DLYBx->CFGR = PhaseSel | (Units << DLYB_CFGR_UNIT_Pos);
00187   DLYBx->CR   = DLYB_CR_DEN;
00188
00189   return HAL_OK;
00190 }
00191
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 #endif /* (HAL_SD_MODULE_ENABLED) & (HAL_QSPI_MODULE_ENABLED)*/
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_delayblock.h Source File

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stm32h7xx_ll_delayblock.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_delayblock.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of Delay Block module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_DLYB_H
00022 #define STM32H7xx_LL_DLYB_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx_hal_def.h"
00030
00031 /** @addtogroup STM32H7xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DELAYBLOCK_LL
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
00041   * @{
00042   */
00043
00044
00045 /**
00046   * @}
00047   */
00048
00049 /* Exported constants --------------------------------------------------------*/
00050 /** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
00051   * @{
00052   */
00053
00054
00055 #define DLYB_MAX_UNIT   ((uint32_t)0x00000080U) /*!< Max UNIT value (128)  */
00056 #define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12)  */
00057
00058 /**
00059   * @}
00060   */
00061
00062 /* Peripheral Control functions  ************************************************/
00063 /** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions
00064   * @{
00065   */
00066 HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx);
00067 HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx);
00068 HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units);
00069
00070 /**
00071   * @}
00072   */
00073
00074
00075 /**
00076   * @}
00077   */
00078
00079   /**
00080   * @}
00081   */
00082 #ifdef __cplusplus
00083 }
00084 #endif
00085
00086 #endif /* STM32H7xx_LL_DLYB_H */
00087
00088 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma2d.c Source File

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stm32h7xx_ll_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dma2d.c
00004   * @author  MCD Application Team
00005   * @brief   DMA2D LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_dma2d.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMA2D)
00035
00036 /** @addtogroup DMA2D_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
00044   * @{
00045   */
00046 #define LL_DMA2D_COLOR            0xFFU                                      /*!< Maximum output color setting                   */
00047 #define LL_DMA2D_NUMBEROFLINES    DMA2D_NLR_NL                               /*!< Maximum number of lines                        */
00048 #define LL_DMA2D_NUMBEROFPIXELS   (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)         /*!< Maximum number of pixels per lines             */
00049 #define LL_DMA2D_OFFSET_MAX       0x3FFFU                                    /*!< Maximum output line offset expressed in pixels */
00050 #define LL_DMA2D_CLUTSIZE_MAX     0xFFU                                      /*!< Maximum CLUT size                              */
00051 /**
00052   * @}
00053   */
00054 /* Private macros ------------------------------------------------------------*/
00055 /** @addtogroup DMA2D_LL_Private_Macros
00056   * @{
00057   */
00058 #define IS_LL_DMA2D_MODE(MODE)          (((MODE) == LL_DMA2D_MODE_M2M)                      || \
00059                                          ((MODE) == LL_DMA2D_MODE_M2M_PFC)                  || \
00060                                          ((MODE) == LL_DMA2D_MODE_M2M_BLEND)                || \
00061                                          ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \
00062                                          ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \
00063                                          ((MODE) == LL_DMA2D_MODE_R2M))
00064
00065 #define IS_LL_DMA2D_OCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
00066                                          ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888)   || \
00067                                          ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565)   || \
00068                                          ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
00069                                          ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
00070
00071 #define IS_LL_DMA2D_GREEN(GREEN)        ((GREEN) <= LL_DMA2D_COLOR)
00072 #define IS_LL_DMA2D_RED(RED)            ((RED)   <= LL_DMA2D_COLOR)
00073 #define IS_LL_DMA2D_BLUE(BLUE)          ((BLUE)  <= LL_DMA2D_COLOR)
00074 #define IS_LL_DMA2D_ALPHA(ALPHA)        ((ALPHA) <= LL_DMA2D_COLOR)
00075
00076 #define IS_LL_DMA2D_OFFSET_MODE(MODE)   (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \
00077                                          ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES))
00078
00079 #define IS_LL_DMA2D_OFFSET(OFFSET)      ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
00080
00081 #define IS_LL_DMA2D_LINE(LINES)         ((LINES)  <= LL_DMA2D_NUMBEROFLINES)
00082 #define IS_LL_DMA2D_PIXEL(PIXELS)       ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
00083
00084 #define IS_LL_DMA2D_SWAP_MODE(MODE)     (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \
00085                                          ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO))
00086
00087 #define IS_LL_DMA2D_ALPHAINV(ALPHA)     (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
00088                                          ((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
00089
00090 #define IS_LL_DMA2D_RBSWAP(RBSWAP)      (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
00091                                          ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
00092
00093 #define IS_LL_DMA2D_LCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
00094                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888)   || \
00095                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565)   || \
00096                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
00097                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
00098                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8)       || \
00099                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44)     || \
00100                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88)     || \
00101                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4)       || \
00102                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8)       || \
00103                                          ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
00104
00105 #define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
00106                                           ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
00107
00108 #define IS_LL_DMA2D_CLUTSIZE(SIZE)      ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
00109
00110 #define IS_LL_DMA2D_ALPHAMODE(MODE)     (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
00111                                          ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE)  || \
00112                                          ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
00113
00114 #define IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == LL_DMA2D_CSS_444) || \
00115                                               ((CSS) == LL_DMA2D_CSS_422) || \
00116                                               ((CSS) == LL_DMA2D_CSS_420))
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private function prototypes -----------------------------------------------*/
00123
00124 /* Exported functions --------------------------------------------------------*/
00125 /** @addtogroup DMA2D_LL_Exported_Functions
00126   * @{
00127   */
00128
00129 /** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  De-initialize DMA2D registers (registers restored to their default values).
00135   * @param  DMA2Dx DMA2D Instance
00136   * @retval An ErrorStatus enumeration value:
00137   *          - SUCCESS: DMA2D registers are de-initialized
00138   *          - ERROR: DMA2D registers are not de-initialized
00139   */
00140 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
00141 {
00142   ErrorStatus status = SUCCESS;
00143
00144   /* Check the parameters */
00145   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00146
00147   if (DMA2Dx == DMA2D)
00148   {
00149     /* Force reset of DMA2D clock */
00150     LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_DMA2D);
00151
00152     /* Release reset of DMA2D clock */
00153     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_DMA2D);
00154
00155   }
00156   else
00157   {
00158     status = ERROR;
00159   }
00160
00161   return (status);
00162 }
00163
00164 /**
00165   * @brief  Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
00166   * @note   DMA2D transfers must be disabled to set initialization bits in configuration registers,
00167   *         otherwise ERROR result is returned.
00168   * @param  DMA2Dx DMA2D Instance
00169   * @param  DMA2D_InitStruct  pointer to a LL_DMA2D_InitTypeDef structure
00170   *         that contains the configuration information for the specified DMA2D peripheral.
00171   * @retval An ErrorStatus enumeration value:
00172   *          - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
00173   *          - ERROR: Issue occurred during DMA2D registers initialization
00174   */
00175 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
00176 {
00177   ErrorStatus status = ERROR;
00178   LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
00179   uint32_t tmp, tmp1, tmp2;
00180   uint32_t regMask, regValue;
00181
00182   /* Check the parameters */
00183   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00184   assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
00185   assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
00186   assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
00187   assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
00188   assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
00189   assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
00190   assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
00191   assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
00192   assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode));
00193   assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode));
00194   assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
00195   assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
00196   assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
00197
00198   /* DMA2D transfers must be disabled to configure bits in initialization registers */
00199   tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
00200   tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
00201   tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
00202   if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
00203   {
00204     /* DMA2D CR register configuration -------------------------------------------*/
00205     MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \
00206                (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode));
00207
00208     /* DMA2D OPFCCR register configuration ---------------------------------------*/
00209     regMask = DMA2D_OPFCCR_CM;
00210     regValue = DMA2D_InitStruct->ColorMode;
00211
00212     regMask |= DMA2D_OPFCCR_SB;
00213     regValue |= DMA2D_InitStruct->OutputSwapMode;
00214
00215     regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI);
00216     regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode);
00217
00218
00219     MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue);
00220
00221     /* DMA2D OOR register configuration ------------------------------------------*/
00222     LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
00223
00224     /* DMA2D NLR register configuration ------------------------------------------*/
00225     LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
00226
00227     /* DMA2D OMAR register configuration ------------------------------------------*/
00228     LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
00229
00230     /* DMA2D OCOLR register configuration ------------------------------------------*/
00231     DMA2D_ColorStruct.ColorMode   = DMA2D_InitStruct->ColorMode;
00232     DMA2D_ColorStruct.OutputBlue  = DMA2D_InitStruct->OutputBlue;
00233     DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
00234     DMA2D_ColorStruct.OutputRed   = DMA2D_InitStruct->OutputRed;
00235     DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
00236     LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
00237
00238     status = SUCCESS;
00239   }
00240   /* If DMA2D transfers are not disabled, return ERROR */
00241
00242   return (status);
00243 }
00244
00245 /**
00246   * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
00247   * @param DMA2D_InitStruct  pointer to a @ref LL_DMA2D_InitTypeDef structure
00248   *                          whose fields will be set to default values.
00249   * @retval None
00250   */
00251 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
00252 {
00253   /* Set DMA2D_InitStruct fields to default values */
00254   DMA2D_InitStruct->Mode                = LL_DMA2D_MODE_M2M;
00255   DMA2D_InitStruct->ColorMode           = LL_DMA2D_OUTPUT_MODE_ARGB8888;
00256   DMA2D_InitStruct->NbrOfLines          = 0x0U;
00257   DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
00258   DMA2D_InitStruct->LineOffsetMode      = LL_DMA2D_LINE_OFFSET_PIXELS;
00259   DMA2D_InitStruct->LineOffset          = 0x0U;
00260   DMA2D_InitStruct->OutputBlue          = 0x0U;
00261   DMA2D_InitStruct->OutputGreen         = 0x0U;
00262   DMA2D_InitStruct->OutputRed           = 0x0U;
00263   DMA2D_InitStruct->OutputAlpha         = 0x0U;
00264   DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
00265   DMA2D_InitStruct->OutputSwapMode      = LL_DMA2D_SWAP_MODE_REGULAR;
00266   DMA2D_InitStruct->AlphaInversionMode  = LL_DMA2D_ALPHA_REGULAR;
00267   DMA2D_InitStruct->RBSwapMode          = LL_DMA2D_RB_MODE_REGULAR;
00268 }
00269
00270 /**
00271   * @brief  Configure the foreground or background according to the specified parameters
00272   *         in the LL_DMA2D_LayerCfgTypeDef structure.
00273   * @param  DMA2Dx DMA2D Instance
00274   * @param  DMA2D_LayerCfg  pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
00275   *         the configuration information for the specified layer.
00276   * @param  LayerIdx  DMA2D Layer index.
00277   *                   This parameter can be one of the following values:
00278   *                   0(background) / 1(foreground)
00279   * @retval None
00280   */
00281 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
00282 {
00283   /* Check the parameters */
00284   assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
00285   assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
00286   assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
00287   assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
00288   assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
00289   assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
00290   assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
00291   assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
00292   assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
00293   assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode));
00294   assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
00295   assert_param(IS_LL_DMA2D_CHROMA_SUB_SAMPLING(DMA2D_LayerCfg->ChromaSubSampling));
00296
00297
00298   if (LayerIdx == 0U)
00299   {
00300     /* Configure the background memory address */
00301     LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
00302
00303     /* Configure the background line offset */
00304     LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
00305
00306     /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion
00307        CLUT size, CLUT Color mode and Color mode */
00308     MODIFY_REG(DMA2Dx->BGPFCCR, \
00309                (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \
00310                 DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
00311                ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
00312                 DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
00313                 (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
00314                 DMA2D_LayerCfg->ColorMode));
00315
00316     /* Configure the background color */
00317     LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
00318
00319     /* Configure the background CLUT memory address */
00320     LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
00321   }
00322   else
00323   {
00324     /* Configure the foreground memory address */
00325     LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
00326
00327     /* Configure the foreground line offset */
00328     LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
00329
00330     /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion
00331        CLUT size, CLUT Color mode and Color mode */
00332     MODIFY_REG(DMA2Dx->FGPFCCR, \
00333                (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \
00334                 DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
00335                ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
00336                  DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \
00337                  DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \
00338                  DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode));
00339
00340     /* Configure the foreground color */
00341     LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
00342
00343     /* Configure the foreground CLUT memory address */
00344     LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
00345   }
00346 }
00347
00348 /**
00349   * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
00350   * @param DMA2D_LayerCfg  pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
00351   *                        whose fields will be set to default values.
00352   * @retval None
00353   */
00354 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
00355 {
00356   /* Set DMA2D_LayerCfg fields to default values */
00357   DMA2D_LayerCfg->MemoryAddress      = 0x0U;
00358   DMA2D_LayerCfg->ColorMode          = LL_DMA2D_INPUT_MODE_ARGB8888;
00359   DMA2D_LayerCfg->LineOffset         = 0x0U;
00360   DMA2D_LayerCfg->CLUTColorMode      = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
00361   DMA2D_LayerCfg->CLUTSize           = 0x0U;
00362   DMA2D_LayerCfg->AlphaMode          = LL_DMA2D_ALPHA_MODE_NO_MODIF;
00363   DMA2D_LayerCfg->Alpha              = 0x0U;
00364   DMA2D_LayerCfg->Blue               = 0x0U;
00365   DMA2D_LayerCfg->Green              = 0x0U;
00366   DMA2D_LayerCfg->Red                = 0x0U;
00367   DMA2D_LayerCfg->CLUTMemoryAddress  = 0x0U;
00368   DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
00369   DMA2D_LayerCfg->RBSwapMode         = LL_DMA2D_RB_MODE_REGULAR;
00370   DMA2D_LayerCfg->ChromaSubSampling  = LL_DMA2D_CSS_444;
00371 }
00372
00373 /**
00374   * @brief  Initialize DMA2D output color register according to the specified parameters
00375   *         in DMA2D_ColorStruct.
00376   * @param  DMA2Dx DMA2D Instance
00377   * @param  DMA2D_ColorStruct  pointer to a LL_DMA2D_ColorTypeDef structure that contains
00378   *         the color configuration information for the specified DMA2D peripheral.
00379   * @retval None
00380   */
00381 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
00382 {
00383   uint32_t outgreen;
00384   uint32_t outred;
00385   uint32_t outalpha;
00386
00387   /* Check the parameters */
00388   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00389   assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
00390   assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
00391   assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
00392   assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
00393   assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
00394
00395   /* DMA2D OCOLR register configuration ------------------------------------------*/
00396   if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
00397   {
00398     outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
00399     outred = DMA2D_ColorStruct->OutputRed << 16U;
00400     outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
00401   }
00402   else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
00403   {
00404     outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
00405     outred = DMA2D_ColorStruct->OutputRed << 16U;
00406     outalpha = 0x00000000U;
00407   }
00408   else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
00409   {
00410     outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
00411     outred = DMA2D_ColorStruct->OutputRed << 11U;
00412     outalpha = 0x00000000U;
00413   }
00414   else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
00415   {
00416     outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
00417     outred = DMA2D_ColorStruct->OutputRed << 10U;
00418     outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
00419   }
00420   else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
00421   {
00422     outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
00423     outred = DMA2D_ColorStruct->OutputRed << 8U;
00424     outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
00425   }
00426   LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
00427 }
00428
00429 /**
00430   * @brief  Return DMA2D output Blue color.
00431   * @param  DMA2Dx DMA2D Instance.
00432   * @param  ColorMode This parameter can be one of the following values:
00433   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00434   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00435   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00436   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00437   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00438   * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
00439   */
00440 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
00441 {
00442   uint32_t color;
00443
00444   /* Check the parameters */
00445   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00446   assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
00447
00448   /* DMA2D OCOLR register reading ------------------------------------------*/
00449   if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
00450   {
00451     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
00452   }
00453   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
00454   {
00455     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
00456   }
00457   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
00458   {
00459     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
00460   }
00461   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
00462   {
00463     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
00464   }
00465   else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
00466   {
00467     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
00468   }
00469
00470   return color;
00471 }
00472
00473 /**
00474   * @brief  Return DMA2D output Green color.
00475   * @param  DMA2Dx DMA2D Instance.
00476   * @param  ColorMode This parameter can be one of the following values:
00477   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00478   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00479   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00480   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00481   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00482   * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
00483   */
00484 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
00485 {
00486   uint32_t color;
00487
00488   /* Check the parameters */
00489   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00490   assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
00491
00492   /* DMA2D OCOLR register reading ------------------------------------------*/
00493   if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
00494   {
00495     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
00496   }
00497   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
00498   {
00499     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
00500   }
00501   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
00502   {
00503     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
00504   }
00505   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
00506   {
00507     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
00508   }
00509   else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
00510   {
00511     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
00512   }
00513
00514   return color;
00515 }
00516
00517 /**
00518   * @brief  Return DMA2D output Red color.
00519   * @param  DMA2Dx DMA2D Instance.
00520   * @param  ColorMode This parameter can be one of the following values:
00521   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00522   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00523   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00524   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00525   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00526   * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
00527   */
00528 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
00529 {
00530   uint32_t color;
00531
00532   /* Check the parameters */
00533   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00534   assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
00535
00536   /* DMA2D OCOLR register reading ------------------------------------------*/
00537   if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
00538   {
00539     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
00540   }
00541   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
00542   {
00543     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
00544   }
00545   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
00546   {
00547     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
00548   }
00549   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
00550   {
00551     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
00552   }
00553   else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
00554   {
00555     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
00556   }
00557
00558   return color;
00559 }
00560
00561 /**
00562   * @brief  Return DMA2D output Alpha color.
00563   * @param  DMA2Dx DMA2D Instance.
00564   * @param  ColorMode This parameter can be one of the following values:
00565   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00566   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00567   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00568   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00569   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00570   * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
00571   */
00572 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
00573 {
00574   uint32_t color;
00575
00576   /* Check the parameters */
00577   assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
00578   assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
00579
00580   /* DMA2D OCOLR register reading ------------------------------------------*/
00581   if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
00582   {
00583     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
00584   }
00585   else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
00586   {
00587     color = 0x0U;
00588   }
00589   else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
00590   {
00591     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
00592   }
00593   else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
00594   {
00595     color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
00596   }
00597
00598   return color;
00599 }
00600
00601 /**
00602   * @brief  Configure DMA2D transfer size.
00603   * @param  DMA2Dx DMA2D Instance
00604   * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
00605   * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
00606   * @retval None
00607   */
00608 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
00609 {
00610   MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
00611              ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
00612 }
00613
00614 /**
00615   * @}
00616   */
00617
00618 /**
00619   * @}
00620   */
00621
00622 /**
00623   * @}
00624   */
00625
00626 #endif /* defined (DMA2D) */
00627
00628 /**
00629   * @}
00630   */
00631
00632 #endif /* USE_FULL_LL_DRIVER */
00633
00634 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00635
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma2d.h Source File

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stm32h7xx_ll_dma2d.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dma2d.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA2D LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_DMA2D_H
00022 #define STM32H7xx_LL_DMA2D_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (DMA2D)
00036
00037 /** @defgroup DMA2D_LL DMA2D
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
00047   * @{
00048   */
00049
00050 /**
00051   * @}
00052   */
00053 #endif /*USE_FULL_LL_DRIVER*/
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 #if defined(USE_FULL_LL_DRIVER)
00057 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
00058   * @{
00059   */
00060
00061 /**
00062   * @brief LL DMA2D Init Structure Definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Mode;                 /*!< Specifies the DMA2D transfer mode.
00067                                       - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
00068
00069                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
00070
00071   uint32_t ColorMode;            /*!< Specifies the color format of the output image.
00072                                       - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
00073
00074                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
00075
00076   uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
00077                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00078                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00079                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
00080                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00081                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00082
00083                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00084                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00085
00086   uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
00087                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00088                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00089                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
00090                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00091                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00092
00093                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00094                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00095
00096   uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
00097                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00098                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00099                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
00100                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00101                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00102
00103                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00104                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00105
00106   uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
00107                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00108                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
00109                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00110                                       - This parameter is not considered if RGB888 or RGB565 color mode is selected.
00111
00112                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00113                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00114
00115   uint32_t OutputMemoryAddress;  /*!< Specifies the memory address.
00116                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
00117
00118                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
00119
00120   uint32_t OutputSwapMode;             /*!< Specifies the output swap mode color format of the output image.
00121                                       - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
00122
00123                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
00124
00125   uint32_t LineOffsetMode;       /*!< Specifies the output line offset mode.
00126                                       - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
00127
00128                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
00129
00130   uint32_t LineOffset;           /*!< Specifies the output line offset value.
00131                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00132
00133                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
00134
00135   uint32_t NbrOfLines;           /*!< Specifies the number of lines of the area to be transferred.
00136                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00137
00138                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
00139
00140   uint32_t NbrOfPixelsPerLines;  /*!< Specifies the number of pixels per lines of the area to be transfered.
00141                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
00142
00143                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
00144
00145   uint32_t AlphaInversionMode;   /*!< Specifies the output alpha inversion mode.
00146                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
00147
00148                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
00149
00150   uint32_t RBSwapMode;           /*!< Specifies the output Red Blue swap mode.
00151                                       - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
00152
00153                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
00154
00155 } LL_DMA2D_InitTypeDef;
00156
00157 /**
00158   * @brief LL DMA2D Layer Configuration Structure Definition
00159   */
00160 typedef struct
00161 {
00162   uint32_t MemoryAddress;        /*!< Specifies the foreground or background memory address.
00163                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
00164
00165                                       This parameter can be modified afterwards using unitary functions
00166                                       - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
00167                                       - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
00168
00169   uint32_t LineOffset;           /*!< Specifies the foreground or background line offset value.
00170                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
00171
00172                                       This parameter can be modified afterwards using unitary functions
00173                                       - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
00174                                       - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
00175
00176   uint32_t ColorMode;            /*!< Specifies the foreground or background color mode.
00177                                       - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
00178
00179                                       This parameter can be modified afterwards using unitary functions
00180                                       - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
00181                                       - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
00182
00183   uint32_t CLUTColorMode;        /*!< Specifies the foreground or background CLUT color mode.
00184                                        - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
00185
00186                                       This parameter can be modified afterwards using unitary functions
00187                                       - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
00188                                       - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
00189
00190   uint32_t CLUTSize;             /*!< Specifies the foreground or background CLUT size.
00191                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00192
00193                                       This parameter can be modified afterwards using unitary functions
00194                                       - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
00195                                       - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
00196
00197   uint32_t AlphaMode;            /*!< Specifies the foreground or background alpha mode.
00198                                        - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
00199
00200                                       This parameter can be modified afterwards using unitary functions
00201                                       - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
00202                                       - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
00203
00204   uint32_t Alpha;                /*!< Specifies the foreground or background Alpha value.
00205                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00206
00207                                       This parameter can be modified afterwards using unitary functions
00208                                       - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
00209                                       - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
00210
00211   uint32_t Blue;                 /*!< Specifies the foreground or background Blue color value.
00212                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00213
00214                                       This parameter can be modified afterwards using unitary functions
00215                                       - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
00216                                       - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
00217
00218   uint32_t Green;                /*!< Specifies the foreground or background Green color value.
00219                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00220
00221                                       This parameter can be modified afterwards using unitary functions
00222                                       - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
00223                                       - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
00224
00225   uint32_t Red;                  /*!< Specifies the foreground or background Red color value.
00226                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00227
00228                                       This parameter can be modified afterwards using unitary functions
00229                                       - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
00230                                       - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
00231
00232   uint32_t CLUTMemoryAddress;    /*!< Specifies the foreground or background CLUT memory address.
00233                                       - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
00234
00235                                       This parameter can be modified afterwards using unitary functions
00236                                       - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
00237                                       - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
00238
00239   uint32_t AlphaInversionMode;   /*!< Specifies the foreground or background alpha inversion mode.
00240                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
00241
00242                                       This parameter can be modified afterwards using unitary functions
00243                                       - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
00244                                       - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
00245
00246   uint32_t RBSwapMode;           /*!< Specifies the foreground or background Red Blue swap mode.
00247                                       This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
00248
00249                                       This parameter can be modified afterwards using unitary functions
00250                                       - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
00251                                       - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
00252
00253   uint32_t ChromaSubSampling;   /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
00254                                      This parameter is applicable for foreground layer only.
00255                                      This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
00256
00257                                      This parameter can be modified afterwards using unitary functions
00258                                      - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
00259
00260 } LL_DMA2D_LayerCfgTypeDef;
00261
00262 /**
00263   * @brief LL DMA2D Output Color Structure Definition
00264   */
00265 typedef struct
00266 {
00267   uint32_t ColorMode;            /*!< Specifies the color format of the output image.
00268                                       - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
00269
00270                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
00271
00272   uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
00273                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00274                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00275                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
00276                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00277                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00278
00279                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00280                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00281
00282   uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
00283                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00284                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00285                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
00286                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00287                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00288
00289                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00290                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00291
00292   uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
00293                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00294                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
00295                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
00296                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
00297                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00298
00299                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00300                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00301
00302   uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
00303                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
00304                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
00305                                       - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
00306                                       - This parameter is not considered if RGB888 or RGB565 color mode is selected.
00307
00308                                       This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
00309                                       function @ref LL_DMA2D_ConfigOutputColor(). */
00310
00311 } LL_DMA2D_ColorTypeDef;
00312
00313 /**
00314   * @}
00315   */
00316 #endif /* USE_FULL_LL_DRIVER */
00317
00318 /* Exported constants --------------------------------------------------------*/
00319 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
00320   * @{
00321   */
00322
00323 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
00324   * @brief    Flags defines which can be used with LL_DMA2D_ReadReg function
00325   * @{
00326   */
00327 #define LL_DMA2D_FLAG_CEIF          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
00328 #define LL_DMA2D_FLAG_CTCIF         DMA2D_ISR_CTCIF    /*!< CLUT Transfer Complete Interrupt Flag */
00329 #define LL_DMA2D_FLAG_CAEIF         DMA2D_ISR_CAEIF    /*!< CLUT Access Error Interrupt Flag */
00330 #define LL_DMA2D_FLAG_TWIF          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
00331 #define LL_DMA2D_FLAG_TCIF          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
00332 #define LL_DMA2D_FLAG_TEIF          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup DMA2D_LL_EC_IT IT Defines
00338   * @brief    IT defines which can be used with LL_DMA2D_ReadReg and  LL_DMA2D_WriteReg functions
00339   * @{
00340   */
00341 #define LL_DMA2D_IT_CEIE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
00342 #define LL_DMA2D_IT_CTCIE            DMA2D_CR_CTCIE   /*!< CLUT Transfer Complete Interrupt */
00343 #define LL_DMA2D_IT_CAEIE            DMA2D_CR_CAEIE   /*!< CLUT Access Error Interrupt */
00344 #define LL_DMA2D_IT_TWIE             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
00345 #define LL_DMA2D_IT_TCIE             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
00346 #define LL_DMA2D_IT_TEIE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup DMA2D_LL_EC_MODE Mode
00352   * @{
00353   */
00354 #define LL_DMA2D_MODE_M2M                       0x00000000U                       /*!< DMA2D memory to memory transfer mode */
00355 #define LL_DMA2D_MODE_M2M_PFC                   DMA2D_CR_MODE_0                   /*!< DMA2D memory to memory with pixel format conversion transfer mode */
00356 #define LL_DMA2D_MODE_M2M_BLEND                 DMA2D_CR_MODE_1                   /*!< DMA2D memory to memory with blending transfer mode */
00357 #define LL_DMA2D_MODE_R2M                       (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
00358 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG  DMA2D_CR_MODE_2                   /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
00359 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG  (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
00365   * @{
00366   */
00367 #define LL_DMA2D_OUTPUT_MODE_ARGB8888     0x00000000U                           /*!< ARGB8888 */
00368 #define LL_DMA2D_OUTPUT_MODE_RGB888       DMA2D_OPFCCR_CM_0                     /*!< RGB888   */
00369 #define LL_DMA2D_OUTPUT_MODE_RGB565       DMA2D_OPFCCR_CM_1                     /*!< RGB565   */
00370 #define LL_DMA2D_OUTPUT_MODE_ARGB1555     (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
00371 #define LL_DMA2D_OUTPUT_MODE_ARGB4444     DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
00377   * @{
00378   */
00379 #define LL_DMA2D_INPUT_MODE_ARGB8888      0x00000000U                                                /*!< ARGB8888 */
00380 #define LL_DMA2D_INPUT_MODE_RGB888        DMA2D_FGPFCCR_CM_0                                         /*!< RGB888   */
00381 #define LL_DMA2D_INPUT_MODE_RGB565        DMA2D_FGPFCCR_CM_1                                         /*!< RGB565   */
00382 #define LL_DMA2D_INPUT_MODE_ARGB1555      (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)                    /*!< ARGB1555 */
00383 #define LL_DMA2D_INPUT_MODE_ARGB4444      DMA2D_FGPFCCR_CM_2                                         /*!< ARGB4444 */
00384 #define LL_DMA2D_INPUT_MODE_L8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)                    /*!< L8       */
00385 #define LL_DMA2D_INPUT_MODE_AL44          (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)                    /*!< AL44     */
00386 #define LL_DMA2D_INPUT_MODE_AL88          (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88     */
00387 #define LL_DMA2D_INPUT_MODE_L4            DMA2D_FGPFCCR_CM_3                                         /*!< L4       */
00388 #define LL_DMA2D_INPUT_MODE_A8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)                    /*!< A8       */
00389 #define LL_DMA2D_INPUT_MODE_A4            (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)                    /*!< A4       */
00390 #define LL_DMA2D_INPUT_MODE_YCBCR         (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr    */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
00396   * @{
00397   */
00398 #define LL_DMA2D_ALPHA_MODE_NO_MODIF       0x00000000U             /*!< No modification of the alpha channel value */
00399 #define LL_DMA2D_ALPHA_MODE_REPLACE        DMA2D_FGPFCCR_AM_0      /*!< Replace original alpha channel value by programmed alpha value */
00400 #define LL_DMA2D_ALPHA_MODE_COMBINE        DMA2D_FGPFCCR_AM_1      /*!< Replace original alpha channel value by programmed alpha value
00401                                                                    with original alpha channel value                              */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
00407   * @{
00408   */
00409 #define LL_DMA2D_SWAP_MODE_REGULAR        0x00000000U                      /*!< Regular order */
00410 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO     DMA2D_OPFCCR_SB                  /*!< Bytes swapped two by two */
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
00416   * @{
00417   */
00418 #define LL_DMA2D_RB_MODE_REGULAR          0x00000000U                      /*!< RGB or ARGB */
00419 #define LL_DMA2D_RB_MODE_SWAP             DMA2D_FGPFCCR_RBS                /*!< BGR or ABGR */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
00425   * @{
00426   */
00427 #define LL_DMA2D_ALPHA_REGULAR          0x00000000U                     /*!< Regular alpha  */
00428 #define LL_DMA2D_ALPHA_INVERTED         DMA2D_FGPFCCR_AI                /*!< Inverted alpha */
00429 /**
00430   * @}
00431   */
00432
00433
00434 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
00435   * @{
00436   */
00437 #define LL_DMA2D_LINE_OFFSET_PIXELS     0x00000000U                     /*!< Line offsets are expressed in pixels  */
00438 #define LL_DMA2D_LINE_OFFSET_BYTES      DMA2D_CR_LOM                    /*!< Line offsets are expressed in bytes   */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
00444   * @{
00445   */
00446 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888          0x00000000U                     /*!< ARGB8888 */
00447 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888            DMA2D_FGPFCCR_CCM               /*!< RGB888   */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
00453   * @{
00454   */
00455 #define LL_DMA2D_CSS_444              0x00000000U             /*!< No chroma sub-sampling 4:4:4 */
00456 #define LL_DMA2D_CSS_422              DMA2D_FGPFCCR_CSS_0     /*!< chroma sub-sampling 4:2:2 */
00457 #define LL_DMA2D_CSS_420              DMA2D_FGPFCCR_CSS_1     /*!< chroma sub-sampling 4:2:0 */
00458 /**
00459   * @}
00460   */
00461
00462 /**
00463   * @}
00464   */
00465
00466 /* Exported macro ------------------------------------------------------------*/
00467 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
00468   * @{
00469   */
00470
00471 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
00472   * @{
00473   */
00474
00475 /**
00476   * @brief  Write a value in DMA2D register.
00477   * @param  __INSTANCE__ DMA2D Instance
00478   * @param  __REG__ Register to be written
00479   * @param  __VALUE__ Value to be written in the register
00480   * @retval None
00481   */
00482 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00483
00484 /**
00485   * @brief  Read a value in DMA2D register.
00486   * @param  __INSTANCE__ DMA2D Instance
00487   * @param  __REG__ Register to be read
00488   * @retval Register value
00489   */
00490 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00491 /**
00492   * @}
00493   */
00494
00495 /**
00496   * @}
00497   */
00498
00499 /* Exported functions --------------------------------------------------------*/
00500 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
00501   * @{
00502   */
00503
00504 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
00505   * @{
00506   */
00507
00508 /**
00509   * @brief  Start a DMA2D transfer.
00510   * @rmtoll CR          START            LL_DMA2D_Start
00511   * @param  DMA2Dx DMA2D Instance
00512   * @retval None
00513   */
00514 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
00515 {
00516   SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
00517 }
00518
00519 /**
00520   * @brief  Indicate if a DMA2D transfer is ongoing.
00521   * @rmtoll CR          START            LL_DMA2D_IsTransferOngoing
00522   * @param  DMA2Dx DMA2D Instance
00523   * @retval State of bit (1 or 0).
00524   */
00525 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
00526 {
00527   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
00528 }
00529
00530 /**
00531   * @brief  Suspend DMA2D transfer.
00532   * @note   This API can be used to suspend automatic foreground or background CLUT loading.
00533   * @rmtoll CR          SUSP            LL_DMA2D_Suspend
00534   * @param  DMA2Dx DMA2D Instance
00535   * @retval None
00536   */
00537 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
00538 {
00539   MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
00540 }
00541
00542 /**
00543   * @brief  Resume DMA2D transfer.
00544   * @note   This API can be used to resume automatic foreground or background CLUT loading.
00545   * @rmtoll CR          SUSP            LL_DMA2D_Resume
00546   * @param  DMA2Dx DMA2D Instance
00547   * @retval None
00548   */
00549 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
00550 {
00551   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
00552 }
00553
00554 /**
00555   * @brief  Indicate if DMA2D transfer is suspended.
00556   * @note   This API can be used to indicate whether or not automatic foreground or
00557   *         background CLUT loading is suspended.
00558   * @rmtoll CR          SUSP            LL_DMA2D_IsSuspended
00559   * @param  DMA2Dx DMA2D Instance
00560   * @retval State of bit (1 or 0).
00561   */
00562 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
00563 {
00564   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
00565 }
00566
00567 /**
00568   * @brief  Abort DMA2D transfer.
00569   * @note   This API can be used to abort automatic foreground or background CLUT loading.
00570   * @rmtoll CR          ABORT            LL_DMA2D_Abort
00571   * @param  DMA2Dx DMA2D Instance
00572   * @retval None
00573   */
00574 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
00575 {
00576   MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
00577 }
00578
00579 /**
00580   * @brief  Indicate if DMA2D transfer is aborted.
00581   * @note   This API can be used to indicate whether or not automatic foreground or
00582   *         background CLUT loading is aborted.
00583   * @rmtoll CR          ABORT            LL_DMA2D_IsAborted
00584   * @param  DMA2Dx DMA2D Instance
00585   * @retval State of bit (1 or 0).
00586   */
00587 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
00588 {
00589   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
00590 }
00591
00592 /**
00593   * @brief  Set DMA2D mode.
00594   * @rmtoll CR          MODE          LL_DMA2D_SetMode
00595   * @param  DMA2Dx DMA2D Instance
00596   * @param  Mode This parameter can be one of the following values:
00597   *         @arg @ref LL_DMA2D_MODE_M2M
00598   *         @arg @ref LL_DMA2D_MODE_M2M_PFC
00599   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
00600   *         @arg @ref LL_DMA2D_MODE_R2M
00601   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
00602   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
00606 {
00607   MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
00608 }
00609
00610 /**
00611   * @brief  Return DMA2D mode
00612   * @rmtoll CR          MODE         LL_DMA2D_GetMode
00613   * @param  DMA2Dx DMA2D Instance
00614   * @retval Returned value can be one of the following values:
00615   *         @arg @ref LL_DMA2D_MODE_M2M
00616   *         @arg @ref LL_DMA2D_MODE_M2M_PFC
00617   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
00618   *         @arg @ref LL_DMA2D_MODE_R2M
00619   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
00620   *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
00621   */
00622 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
00623 {
00624   return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
00625 }
00626
00627 /**
00628   * @brief  Set DMA2D output color mode.
00629   * @rmtoll OPFCCR          CM          LL_DMA2D_SetOutputColorMode
00630   * @param  DMA2Dx DMA2D Instance
00631   * @param  ColorMode This parameter can be one of the following values:
00632   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00633   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00634   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00635   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00636   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00637   * @retval None
00638   */
00639 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
00640 {
00641   MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
00642 }
00643
00644 /**
00645   * @brief  Return DMA2D output color mode.
00646   * @rmtoll OPFCCR          CM         LL_DMA2D_GetOutputColorMode
00647   * @param  DMA2Dx DMA2D Instance
00648   * @retval Returned value can be one of the following values:
00649   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
00650   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
00651   *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
00652   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
00653   *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
00654   */
00655 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
00656 {
00657   return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
00658 }
00659
00660 /**
00661   * @brief  Set DMA2D output Red Blue swap mode.
00662   * @rmtoll OPFCCR          RBS          LL_DMA2D_SetOutputRBSwapMode
00663   * @param  DMA2Dx DMA2D Instance
00664   * @param  RBSwapMode This parameter can be one of the following values:
00665   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
00666   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
00667   * @retval None
00668   */
00669 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
00670 {
00671   MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
00672 }
00673
00674 /**
00675   * @brief  Return DMA2D output Red Blue swap mode.
00676   * @rmtoll OPFCCR          RBS         LL_DMA2D_GetOutputRBSwapMode
00677   * @param  DMA2Dx DMA2D Instance
00678   * @retval Returned value can be one of the following values:
00679   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
00680   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
00681   */
00682 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
00683 {
00684   return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
00685 }
00686
00687 /**
00688   * @brief  Set DMA2D output alpha inversion mode.
00689   * @rmtoll OPFCCR          AI          LL_DMA2D_SetOutputAlphaInvMode
00690   * @param  DMA2Dx DMA2D Instance
00691   * @param  AlphaInversionMode This parameter can be one of the following values:
00692   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
00693   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
00694   * @retval None
00695   */
00696 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
00697 {
00698   MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
00699 }
00700
00701 /**
00702   * @brief  Return DMA2D output alpha inversion mode.
00703   * @rmtoll OPFCCR          AI         LL_DMA2D_GetOutputAlphaInvMode
00704   * @param  DMA2Dx DMA2D Instance
00705   * @retval Returned value can be one of the following values:
00706   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
00707   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
00708   */
00709 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
00710 {
00711   return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
00712 }
00713
00714
00715 /**
00716   * @brief  Set DMA2D output swap mode.
00717   * @rmtoll OPFCCR          SB          LL_DMA2D_SetOutputSwapMode
00718   * @param  DMA2Dx DMA2D Instance
00719   * @param  OutputSwapMode This parameter can be one of the following values:
00720   *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
00721   *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
00722   * @retval None
00723   */
00724 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
00725 {
00726   MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
00727 }
00728
00729 /**
00730   * @brief  Return DMA2D output swap mode.
00731   * @rmtoll OPFCCR          SB         LL_DMA2D_GetOutputSwapMode
00732   * @param  DMA2Dx DMA2D Instance
00733   * @retval Returned value can be one of the following values:
00734   *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
00735   *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
00736   */
00737 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
00738 {
00739   return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
00740 }
00741
00742 /**
00743   * @brief  Set DMA2D line offset mode.
00744   * @rmtoll CR          LOM          LL_DMA2D_SetLineOffsetMode
00745   * @param  DMA2Dx DMA2D Instance
00746   * @param  LineOffsetMode This parameter can be one of the following values:
00747   *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
00748   *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
00749   * @retval None
00750   */
00751 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
00752 {
00753   MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
00754 }
00755
00756 /**
00757   * @brief  Return DMA2D line offset mode.
00758   * @rmtoll CR          LOM         LL_DMA2D_GetLineOffsetMode
00759   * @param  DMA2Dx DMA2D Instance
00760   * @retval Returned value can be one of the following values:
00761   *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
00762   *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
00763   */
00764 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
00765 {
00766   return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
00767 }
00768
00769 /**
00770   * @brief  Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
00771   * @rmtoll OOR          LO          LL_DMA2D_SetLineOffset
00772   * @param  DMA2Dx DMA2D Instance
00773   * @param  LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
00774   * @retval None
00775   */
00776 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
00777 {
00778   MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
00779 }
00780
00781 /**
00782   * @brief  Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
00783   * @rmtoll OOR          LO         LL_DMA2D_GetLineOffset
00784   * @param  DMA2Dx DMA2D Instance
00785   * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
00786   @endif
00787   */
00788 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
00789 {
00790   return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
00791 }
00792
00793 /**
00794   * @brief  Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
00795   * @rmtoll NLR          PL          LL_DMA2D_SetNbrOfPixelsPerLines
00796   * @param  DMA2Dx DMA2D Instance
00797   * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
00801 {
00802   MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
00803 }
00804
00805 /**
00806   * @brief  Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
00807   * @rmtoll NLR          PL          LL_DMA2D_GetNbrOfPixelsPerLines
00808   * @param  DMA2Dx DMA2D Instance
00809   * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
00810   */
00811 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
00812 {
00813   return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
00814 }
00815
00816 /**
00817   * @brief  Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
00818   * @rmtoll NLR          NL          LL_DMA2D_SetNbrOfLines
00819   * @param  DMA2Dx DMA2D Instance
00820   * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
00821   * @retval None
00822   */
00823 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
00824 {
00825   MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
00826 }
00827
00828 /**
00829   * @brief  Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
00830   * @rmtoll NLR          NL          LL_DMA2D_GetNbrOfLines
00831   * @param  DMA2Dx DMA2D Instance
00832   * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
00833   */
00834 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
00835 {
00836   return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
00837 }
00838
00839 /**
00840   * @brief  Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
00841   * @rmtoll OMAR          MA          LL_DMA2D_SetOutputMemAddr
00842   * @param  DMA2Dx DMA2D Instance
00843   * @param  OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
00847 {
00848   LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
00849 }
00850
00851 /**
00852   * @brief  Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
00853   * @rmtoll OMAR          MA          LL_DMA2D_GetOutputMemAddr
00854   * @param  DMA2Dx DMA2D Instance
00855   * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
00856   */
00857 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
00858 {
00859   return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
00860 }
00861
00862 /**
00863   * @brief  Set DMA2D output color, expressed on 32 bits ([31:0] bits).
00864   * @note   Output color format depends on output color mode, ARGB8888, RGB888,
00865   *         RGB565, ARGB1555 or ARGB4444.
00866   * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
00867   *       with respect to color mode is not done by the user code.
00868   * @rmtoll OCOLR        BLUE        LL_DMA2D_SetOutputColor\n
00869   *         OCOLR        GREEN       LL_DMA2D_SetOutputColor\n
00870   *         OCOLR        RED         LL_DMA2D_SetOutputColor\n
00871   *         OCOLR        ALPHA       LL_DMA2D_SetOutputColor
00872   * @param  DMA2Dx DMA2D Instance
00873   * @param  OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00874   * @retval None
00875   */
00876 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
00877 {
00878   MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
00879              OutputColor);
00880 }
00881
00882 /**
00883   * @brief  Get DMA2D output color, expressed on 32 bits ([31:0] bits).
00884   * @note   Alpha channel and red, green, blue color values must be retrieved from the returned
00885   *         value based on the output color mode (ARGB8888, RGB888,  RGB565, ARGB1555 or ARGB4444)
00886   *         as set by @ref LL_DMA2D_SetOutputColorMode.
00887   * @rmtoll OCOLR        BLUE        LL_DMA2D_GetOutputColor\n
00888   *         OCOLR        GREEN       LL_DMA2D_GetOutputColor\n
00889   *         OCOLR        RED         LL_DMA2D_GetOutputColor\n
00890   *         OCOLR        ALPHA       LL_DMA2D_GetOutputColor
00891   * @param  DMA2Dx DMA2D Instance
00892   * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
00893   */
00894 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
00895 {
00896   return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
00897                              (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
00898 }
00899
00900 /**
00901   * @brief  Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
00902   * @rmtoll LWR          LW          LL_DMA2D_SetLineWatermark
00903   * @param  DMA2Dx DMA2D Instance
00904   * @param  LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
00905   * @retval None
00906   */
00907 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
00908 {
00909   MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
00910 }
00911
00912 /**
00913   * @brief  Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
00914   * @rmtoll LWR          LW          LL_DMA2D_GetLineWatermark
00915   * @param  DMA2Dx DMA2D Instance
00916   * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
00917   */
00918 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
00919 {
00920   return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
00921 }
00922
00923 /**
00924   * @brief  Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
00925   * @rmtoll AMTCR          DT          LL_DMA2D_SetDeadTime
00926   * @param  DMA2Dx DMA2D Instance
00927   * @param  DeadTime Value between Min_Data=0 and Max_Data=0xFF
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
00931 {
00932   MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
00933 }
00934
00935 /**
00936   * @brief  Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
00937   * @rmtoll AMTCR          DT          LL_DMA2D_GetDeadTime
00938   * @param  DMA2Dx DMA2D Instance
00939   * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
00940   */
00941 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
00942 {
00943   return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
00944 }
00945
00946 /**
00947   * @brief  Enable DMA2D dead time functionality.
00948   * @rmtoll AMTCR          EN            LL_DMA2D_EnableDeadTime
00949   * @param  DMA2Dx DMA2D Instance
00950   * @retval None
00951   */
00952 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
00953 {
00954   SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
00955 }
00956
00957 /**
00958   * @brief  Disable DMA2D dead time functionality.
00959   * @rmtoll AMTCR          EN            LL_DMA2D_DisableDeadTime
00960   * @param  DMA2Dx DMA2D Instance
00961   * @retval None
00962   */
00963 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
00964 {
00965   CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
00966 }
00967
00968 /**
00969   * @brief  Indicate if DMA2D dead time functionality is enabled.
00970   * @rmtoll AMTCR          EN            LL_DMA2D_IsEnabledDeadTime
00971   * @param  DMA2Dx DMA2D Instance
00972   * @retval State of bit (1 or 0).
00973   */
00974 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
00975 {
00976   return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
00977 }
00978
00979 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
00980   * @{
00981   */
00982
00983 /**
00984   * @brief  Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
00985   * @rmtoll FGMAR          MA          LL_DMA2D_FGND_SetMemAddr
00986   * @param  DMA2Dx DMA2D Instance
00987   * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00988   * @retval None
00989   */
00990 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
00991 {
00992   LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
00993 }
00994
00995 /**
00996   * @brief  Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
00997   * @rmtoll FGMAR          MA          LL_DMA2D_FGND_GetMemAddr
00998   * @param  DMA2Dx DMA2D Instance
00999   * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
01000   */
01001 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
01002 {
01003   return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
01004 }
01005
01006 /**
01007   * @brief  Enable DMA2D foreground CLUT loading.
01008   * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_EnableCLUTLoad
01009   * @param  DMA2Dx DMA2D Instance
01010   * @retval None
01011   */
01012 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
01013 {
01014   SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
01015 }
01016
01017 /**
01018   * @brief  Indicate if DMA2D foreground CLUT loading is enabled.
01019   * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_IsEnabledCLUTLoad
01020   * @param  DMA2Dx DMA2D Instance
01021   * @retval State of bit (1 or 0).
01022   */
01023 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
01024 {
01025   return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
01026 }
01027
01028 /**
01029   * @brief  Set DMA2D foreground color mode.
01030   * @rmtoll FGPFCCR          CM          LL_DMA2D_FGND_SetColorMode
01031   * @param  DMA2Dx DMA2D Instance
01032   * @param  ColorMode This parameter can be one of the following values:
01033   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
01034   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
01035   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
01036   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
01037   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
01038   *         @arg @ref LL_DMA2D_INPUT_MODE_L8
01039   *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
01040   *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
01041   *         @arg @ref LL_DMA2D_INPUT_MODE_L4
01042   *         @arg @ref LL_DMA2D_INPUT_MODE_A8
01043   *         @arg @ref LL_DMA2D_INPUT_MODE_A4
01044   * @retval None
01045   */
01046 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
01047 {
01048   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
01049 }
01050
01051 /**
01052   * @brief  Return DMA2D foreground color mode.
01053   * @rmtoll FGPFCCR          CM         LL_DMA2D_FGND_GetColorMode
01054   * @param  DMA2Dx DMA2D Instance
01055   * @retval Returned value can be one of the following values:
01056   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
01057   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
01058   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
01059   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
01060   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
01061   *         @arg @ref LL_DMA2D_INPUT_MODE_L8
01062   *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
01063   *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
01064   *         @arg @ref LL_DMA2D_INPUT_MODE_L4
01065   *         @arg @ref LL_DMA2D_INPUT_MODE_A8
01066   *         @arg @ref LL_DMA2D_INPUT_MODE_A4
01067   */
01068 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
01069 {
01070   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
01071 }
01072
01073 /**
01074   * @brief  Set DMA2D foreground alpha mode.
01075   * @rmtoll FGPFCCR          AM          LL_DMA2D_FGND_SetAlphaMode
01076   * @param  DMA2Dx DMA2D Instance
01077   * @param  AphaMode This parameter can be one of the following values:
01078   *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
01079   *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
01080   *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
01084 {
01085   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
01086 }
01087
01088 /**
01089   * @brief  Return DMA2D foreground alpha mode.
01090   * @rmtoll FGPFCCR          AM         LL_DMA2D_FGND_GetAlphaMode
01091   * @param  DMA2Dx DMA2D Instance
01092   * @retval Returned value can be one of the following values:
01093   *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
01094   *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
01095   *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
01096   */
01097 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
01098 {
01099   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
01100 }
01101
01102 /**
01103   * @brief  Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
01104   * @rmtoll FGPFCCR          ALPHA          LL_DMA2D_FGND_SetAlpha
01105   * @param  DMA2Dx DMA2D Instance
01106   * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
01107   * @retval None
01108   */
01109 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
01110 {
01111   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
01112 }
01113
01114 /**
01115   * @brief  Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
01116   * @rmtoll FGPFCCR          ALPHA         LL_DMA2D_FGND_GetAlpha
01117   * @param  DMA2Dx DMA2D Instance
01118   * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
01119   */
01120 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
01121 {
01122   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
01123 }
01124
01125 /**
01126   * @brief  Set DMA2D foreground Red Blue swap mode.
01127   * @rmtoll FGPFCCR          RBS          LL_DMA2D_FGND_SetRBSwapMode
01128   * @param  DMA2Dx DMA2D Instance
01129   * @param  RBSwapMode This parameter can be one of the following values:
01130   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
01131   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
01132   * @retval None
01133   */
01134 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
01135 {
01136   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
01137 }
01138
01139 /**
01140   * @brief  Return DMA2D foreground Red Blue swap mode.
01141   * @rmtoll FGPFCCR          RBS         LL_DMA2D_FGND_GetRBSwapMode
01142   * @param  DMA2Dx DMA2D Instance
01143   * @retval Returned value can be one of the following values:
01144   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
01145   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
01146   */
01147 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
01148 {
01149   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
01150 }
01151
01152 /**
01153   * @brief  Set DMA2D foreground alpha inversion mode.
01154   * @rmtoll FGPFCCR          AI          LL_DMA2D_FGND_SetAlphaInvMode
01155   * @param  DMA2Dx DMA2D Instance
01156   * @param  AlphaInversionMode This parameter can be one of the following values:
01157   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
01158   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
01159   * @retval None
01160   */
01161 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
01162 {
01163   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
01164 }
01165
01166 /**
01167   * @brief  Return DMA2D foreground alpha inversion mode.
01168   * @rmtoll FGPFCCR          AI         LL_DMA2D_FGND_GetAlphaInvMode
01169   * @param  DMA2Dx DMA2D Instance
01170   * @retval Returned value can be one of the following values:
01171   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
01172   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
01173   */
01174 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
01175 {
01176   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
01177 }
01178
01179 /**
01180   * @brief  Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
01181   * @rmtoll FGOR          LO          LL_DMA2D_FGND_SetLineOffset
01182   * @param  DMA2Dx DMA2D Instance
01183   * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
01184   * @retval None
01185   */
01186 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
01187 {
01188   MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
01189 }
01190
01191 /**
01192   * @brief  Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
01193   * @rmtoll FGOR          LO         LL_DMA2D_FGND_GetLineOffset
01194   * @param  DMA2Dx DMA2D Instance
01195   * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
01196   */
01197 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
01198 {
01199   return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
01200 }
01201
01202 /**
01203   * @brief  Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
01204   * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetColor
01205   * @rmtoll FGCOLR          GREEN        LL_DMA2D_FGND_SetColor
01206   * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_SetColor
01207   * @param  DMA2Dx DMA2D Instance
01208   * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
01209   * @param  Green Value between Min_Data=0 and Max_Data=0xFF
01210   * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
01211   * @retval None
01212   */
01213 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
01214 {
01215   MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
01216              ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
01217 }
01218
01219 /**
01220   * @brief  Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
01221   * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetRedColor
01222   * @param  DMA2Dx DMA2D Instance
01223   * @param  Red Value between Min_Data=0 and Max_Data=0xFF
01224   * @retval None
01225   */
01226 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
01227 {
01228   MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
01229 }
01230
01231 /**
01232   * @brief  Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
01233   * @rmtoll FGCOLR          RED         LL_DMA2D_FGND_GetRedColor
01234   * @param  DMA2Dx DMA2D Instance
01235   * @retval Red color value between Min_Data=0 and Max_Data=0xFF
01236   */
01237 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
01238 {
01239   return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
01240 }
01241
01242 /**
01243   * @brief  Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
01244   * @rmtoll FGCOLR          GREEN          LL_DMA2D_FGND_SetGreenColor
01245   * @param  DMA2Dx DMA2D Instance
01246   * @param  Green Value between Min_Data=0 and Max_Data=0xFF
01247   * @retval None
01248   */
01249 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
01250 {
01251   MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
01252 }
01253
01254 /**
01255   * @brief  Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
01256   * @rmtoll FGCOLR          GREEN         LL_DMA2D_FGND_GetGreenColor
01257   * @param  DMA2Dx DMA2D Instance
01258   * @retval Green color value between Min_Data=0 and Max_Data=0xFF
01259   */
01260 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
01261 {
01262   return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
01263 }
01264
01265 /**
01266   * @brief  Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
01267   * @rmtoll FGCOLR          BLUE          LL_DMA2D_FGND_SetBlueColor
01268   * @param  DMA2Dx DMA2D Instance
01269   * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
01270   * @retval None
01271   */
01272 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
01273 {
01274   MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
01275 }
01276
01277 /**
01278   * @brief  Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
01279   * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_GetBlueColor
01280   * @param  DMA2Dx DMA2D Instance
01281   * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
01282   */
01283 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
01284 {
01285   return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
01286 }
01287
01288 /**
01289   * @brief  Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
01290   * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_SetCLUTMemAddr
01291   * @param  DMA2Dx DMA2D Instance
01292   * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
01293   * @retval None
01294   */
01295 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
01296 {
01297   LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
01298 }
01299
01300 /**
01301   * @brief  Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
01302   * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_GetCLUTMemAddr
01303   * @param  DMA2Dx DMA2D Instance
01304   * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
01305   */
01306 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
01307 {
01308   return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
01309 }
01310
01311 /**
01312   * @brief  Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
01313   * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_SetCLUTSize
01314   * @param  DMA2Dx DMA2D Instance
01315   * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
01316   * @retval None
01317   */
01318 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
01319 {
01320   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
01321 }
01322
01323 /**
01324   * @brief  Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
01325   * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_GetCLUTSize
01326   * @param  DMA2Dx DMA2D Instance
01327   * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
01328   */
01329 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
01330 {
01331   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
01332 }
01333
01334 /**
01335   * @brief  Set DMA2D foreground CLUT color mode.
01336   * @rmtoll FGPFCCR          CCM          LL_DMA2D_FGND_SetCLUTColorMode
01337   * @param  DMA2Dx DMA2D Instance
01338   * @param  CLUTColorMode This parameter can be one of the following values:
01339   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
01340   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
01341   * @retval None
01342   */
01343 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
01344 {
01345   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
01346 }
01347
01348 /**
01349   * @brief  Return DMA2D foreground CLUT color mode.
01350   * @rmtoll FGPFCCR          CCM         LL_DMA2D_FGND_GetCLUTColorMode
01351   * @param  DMA2Dx DMA2D Instance
01352   * @retval Returned value can be one of the following values:
01353   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
01354   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
01355   */
01356 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
01357 {
01358   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
01359 }
01360
01361 /**
01362   * @brief  Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
01363   * @rmtoll FGPFCCR          CSS          LL_DMA2D_FGND_SetChrSubSampling
01364   * @param  DMA2Dx DMA2D Instance
01365   * @param  ChromaSubSampling This parameter can be one of the following values:
01366   *         @arg @ref LL_DMA2D_CSS_444
01367   *         @arg @ref LL_DMA2D_CSS_422
01368   *         @arg @ref LL_DMA2D_CSS_420
01369   * @retval None
01370   */
01371 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
01372 {
01373   MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
01374 }
01375
01376 /**
01377   * @brief  Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
01378   * @rmtoll FGPFCCR          CSS         LL_DMA2D_FGND_GetChrSubSampling
01379   * @param  DMA2Dx DMA2D Instance
01380   * @retval Returned value can be one of the following values:
01381   *         @arg @ref LL_DMA2D_CSS_444
01382   *         @arg @ref LL_DMA2D_CSS_422
01383   *         @arg @ref LL_DMA2D_CSS_420
01384   */
01385 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx)
01386 {
01387   return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
01388 }
01389 /**
01390   * @}
01391   */
01392
01393 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
01394   * @{
01395   */
01396
01397 /**
01398   * @brief  Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
01399   * @rmtoll BGMAR          MA          LL_DMA2D_BGND_SetMemAddr
01400   * @param  DMA2Dx DMA2D Instance
01401   * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
01402   * @retval None
01403   */
01404 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
01405 {
01406   LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
01407 }
01408
01409 /**
01410   * @brief  Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
01411   * @rmtoll BGMAR          MA          LL_DMA2D_BGND_GetMemAddr
01412   * @param  DMA2Dx DMA2D Instance
01413   * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
01414   */
01415 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
01416 {
01417   return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
01418 }
01419
01420 /**
01421   * @brief  Enable DMA2D background CLUT loading.
01422   * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_EnableCLUTLoad
01423   * @param  DMA2Dx DMA2D Instance
01424   * @retval None
01425   */
01426 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
01427 {
01428   SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
01429 }
01430
01431 /**
01432   * @brief  Indicate if DMA2D background CLUT loading is enabled.
01433   * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_IsEnabledCLUTLoad
01434   * @param  DMA2Dx DMA2D Instance
01435   * @retval State of bit (1 or 0).
01436   */
01437 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
01438 {
01439   return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
01440 }
01441
01442 /**
01443   * @brief  Set DMA2D background color mode.
01444   * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_SetColorMode
01445   * @param  DMA2Dx DMA2D Instance
01446   * @param  ColorMode This parameter can be one of the following values:
01447   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
01448   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
01449   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
01450   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
01451   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
01452   *         @arg @ref LL_DMA2D_INPUT_MODE_L8
01453   *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
01454   *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
01455   *         @arg @ref LL_DMA2D_INPUT_MODE_L4
01456   *         @arg @ref LL_DMA2D_INPUT_MODE_A8
01457   *         @arg @ref LL_DMA2D_INPUT_MODE_A4
01458   * @retval None
01459   */
01460 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
01461 {
01462   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
01463 }
01464
01465 /**
01466   * @brief  Return DMA2D background color mode.
01467   * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_GetColorMode
01468   * @param  DMA2Dx DMA2D Instance
01469   * @retval Returned value can be one of the following values:
01470   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
01471   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
01472   *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
01473   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
01474   *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
01475   *         @arg @ref LL_DMA2D_INPUT_MODE_L8
01476   *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
01477   *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
01478   *         @arg @ref LL_DMA2D_INPUT_MODE_L4
01479   *         @arg @ref LL_DMA2D_INPUT_MODE_A8
01480   *         @arg @ref LL_DMA2D_INPUT_MODE_A4
01481   */
01482 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
01483 {
01484   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
01485 }
01486
01487 /**
01488   * @brief  Set DMA2D background alpha mode.
01489   * @rmtoll BGPFCCR          AM         LL_DMA2D_BGND_SetAlphaMode
01490   * @param  DMA2Dx DMA2D Instance
01491   * @param  AphaMode This parameter can be one of the following values:
01492   *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
01493   *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
01494   *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
01495   * @retval None
01496   */
01497 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
01498 {
01499   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
01500 }
01501
01502 /**
01503   * @brief  Return DMA2D background alpha mode.
01504   * @rmtoll BGPFCCR          AM          LL_DMA2D_BGND_GetAlphaMode
01505   * @param  DMA2Dx DMA2D Instance
01506   * @retval Returned value can be one of the following values:
01507   *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
01508   *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
01509   *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
01510   */
01511 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
01512 {
01513   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
01514 }
01515
01516 /**
01517   * @brief  Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
01518   * @rmtoll BGPFCCR          ALPHA         LL_DMA2D_BGND_SetAlpha
01519   * @param  DMA2Dx DMA2D Instance
01520   * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
01521   * @retval None
01522   */
01523 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
01524 {
01525   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
01526 }
01527
01528 /**
01529   * @brief  Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
01530   * @rmtoll BGPFCCR          ALPHA          LL_DMA2D_BGND_GetAlpha
01531   * @param  DMA2Dx DMA2D Instance
01532   * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
01533   */
01534 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
01535 {
01536   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
01537 }
01538
01539 /**
01540   * @brief  Set DMA2D background Red Blue swap mode.
01541   * @rmtoll BGPFCCR          RBS         LL_DMA2D_BGND_SetRBSwapMode
01542   * @param  DMA2Dx DMA2D Instance
01543   * @param  RBSwapMode This parameter can be one of the following values:
01544   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
01545   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
01546   * @retval None
01547   */
01548 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
01549 {
01550   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
01551 }
01552
01553 /**
01554   * @brief  Return DMA2D background Red Blue swap mode.
01555   * @rmtoll BGPFCCR          RBS          LL_DMA2D_BGND_GetRBSwapMode
01556   * @param  DMA2Dx DMA2D Instance
01557   * @retval Returned value can be one of the following values:
01558   *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
01559   *         @arg @ref LL_DMA2D_RB_MODE_SWAP
01560   */
01561 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
01562 {
01563   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
01564 }
01565
01566 /**
01567   * @brief  Set DMA2D background alpha inversion mode.
01568   * @rmtoll BGPFCCR          AI         LL_DMA2D_BGND_SetAlphaInvMode
01569   * @param  DMA2Dx DMA2D Instance
01570   * @param  AlphaInversionMode This parameter can be one of the following values:
01571   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
01572   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
01573   * @retval None
01574   */
01575 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
01576 {
01577   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
01578 }
01579
01580 /**
01581   * @brief  Return DMA2D background alpha inversion mode.
01582   * @rmtoll BGPFCCR          AI          LL_DMA2D_BGND_GetAlphaInvMode
01583   * @param  DMA2Dx DMA2D Instance
01584   * @retval Returned value can be one of the following values:
01585   *         @arg @ref LL_DMA2D_ALPHA_REGULAR
01586   *         @arg @ref LL_DMA2D_ALPHA_INVERTED
01587   */
01588 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
01589 {
01590   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
01591 }
01592
01593 /**
01594   * @brief  Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
01595   * @rmtoll BGOR          LO         LL_DMA2D_BGND_SetLineOffset
01596   * @param  DMA2Dx DMA2D Instance
01597   * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
01598   * @retval None
01599   */
01600 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
01601 {
01602   MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
01603 }
01604
01605 /**
01606   * @brief  Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
01607   * @rmtoll BGOR          LO          LL_DMA2D_BGND_GetLineOffset
01608   * @param  DMA2Dx DMA2D Instance
01609   * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
01610   */
01611 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
01612 {
01613   return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
01614 }
01615
01616 /**
01617   * @brief  Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
01618   * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_SetColor
01619   * @rmtoll BGCOLR          GREEN        LL_DMA2D_BGND_SetColor
01620   * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetColor
01621   * @param  DMA2Dx DMA2D Instance
01622   * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
01623   * @param  Green Value between Min_Data=0 and Max_Data=0xFF
01624   * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
01625   * @retval None
01626   */
01627 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
01628 {
01629   MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
01630              ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
01631 }
01632
01633 /**
01634   * @brief  Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
01635   * @rmtoll BGCOLR          RED         LL_DMA2D_BGND_SetRedColor
01636   * @param  DMA2Dx DMA2D Instance
01637   * @param  Red Value between Min_Data=0 and Max_Data=0xFF
01638   * @retval None
01639   */
01640 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
01641 {
01642   MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
01643 }
01644
01645 /**
01646   * @brief  Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
01647   * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_GetRedColor
01648   * @param  DMA2Dx DMA2D Instance
01649   * @retval Red color value between Min_Data=0 and Max_Data=0xFF
01650   */
01651 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
01652 {
01653   return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
01654 }
01655
01656 /**
01657   * @brief  Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
01658   * @rmtoll BGCOLR          GREEN         LL_DMA2D_BGND_SetGreenColor
01659   * @param  DMA2Dx DMA2D Instance
01660   * @param  Green Value between Min_Data=0 and Max_Data=0xFF
01661   * @retval None
01662   */
01663 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
01664 {
01665   MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
01666 }
01667
01668 /**
01669   * @brief  Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
01670   * @rmtoll BGCOLR          GREEN          LL_DMA2D_BGND_GetGreenColor
01671   * @param  DMA2Dx DMA2D Instance
01672   * @retval Green color value between Min_Data=0 and Max_Data=0xFF
01673   */
01674 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
01675 {
01676   return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
01677 }
01678
01679 /**
01680   * @brief  Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
01681   * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetBlueColor
01682   * @param  DMA2Dx DMA2D Instance
01683   * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
01684   * @retval None
01685   */
01686 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
01687 {
01688   MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
01689 }
01690
01691 /**
01692   * @brief  Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
01693   * @rmtoll BGCOLR          BLUE          LL_DMA2D_BGND_GetBlueColor
01694   * @param  DMA2Dx DMA2D Instance
01695   * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
01696   */
01697 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
01698 {
01699   return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
01700 }
01701
01702 /**
01703   * @brief  Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
01704   * @rmtoll BGCMAR          MA         LL_DMA2D_BGND_SetCLUTMemAddr
01705   * @param  DMA2Dx DMA2D Instance
01706   * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
01707   * @retval None
01708   */
01709 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
01710 {
01711   LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
01712 }
01713
01714 /**
01715   * @brief  Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
01716   * @rmtoll BGCMAR          MA           LL_DMA2D_BGND_GetCLUTMemAddr
01717   * @param  DMA2Dx DMA2D Instance
01718   * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
01719   */
01720 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
01721 {
01722   return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
01723 }
01724
01725 /**
01726   * @brief  Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
01727   * @rmtoll BGPFCCR          CS         LL_DMA2D_BGND_SetCLUTSize
01728   * @param  DMA2Dx DMA2D Instance
01729   * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
01733 {
01734   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
01735 }
01736
01737 /**
01738   * @brief  Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
01739   * @rmtoll BGPFCCR          CS           LL_DMA2D_BGND_GetCLUTSize
01740   * @param  DMA2Dx DMA2D Instance
01741   * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
01742   */
01743 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
01744 {
01745   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
01746 }
01747
01748 /**
01749   * @brief  Set DMA2D background CLUT color mode.
01750   * @rmtoll BGPFCCR          CCM         LL_DMA2D_BGND_SetCLUTColorMode
01751   * @param  DMA2Dx DMA2D Instance
01752   * @param  CLUTColorMode This parameter can be one of the following values:
01753   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
01754   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
01755   * @retval None
01756   */
01757 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
01758 {
01759   MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
01760 }
01761
01762 /**
01763   * @brief  Return DMA2D background CLUT color mode.
01764   * @rmtoll BGPFCCR          CCM          LL_DMA2D_BGND_GetCLUTColorMode
01765   * @param  DMA2Dx DMA2D Instance
01766   * @retval Returned value can be one of the following values:
01767   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
01768   *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
01769   */
01770 __STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
01771 {
01772   return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
01773 }
01774
01775 /**
01776   * @}
01777   */
01778
01779 /**
01780   * @}
01781   */
01782
01783
01784 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
01785   * @{
01786   */
01787
01788 /**
01789   * @brief  Check if the DMA2D Configuration Error Interrupt Flag is set or not
01790   * @rmtoll ISR          CEIF            LL_DMA2D_IsActiveFlag_CE
01791   * @param  DMA2Dx DMA2D Instance
01792   * @retval State of bit (1 or 0).
01793   */
01794 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
01795 {
01796   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
01797 }
01798
01799 /**
01800   * @brief  Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
01801   * @rmtoll ISR          CTCIF            LL_DMA2D_IsActiveFlag_CTC
01802   * @param  DMA2Dx DMA2D Instance
01803   * @retval State of bit (1 or 0).
01804   */
01805 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
01806 {
01807   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
01808 }
01809
01810 /**
01811   * @brief  Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
01812   * @rmtoll ISR          CAEIF            LL_DMA2D_IsActiveFlag_CAE
01813   * @param  DMA2Dx DMA2D Instance
01814   * @retval State of bit (1 or 0).
01815   */
01816 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
01817 {
01818   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
01819 }
01820
01821 /**
01822   * @brief  Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
01823   * @rmtoll ISR          TWIF            LL_DMA2D_IsActiveFlag_TW
01824   * @param  DMA2Dx DMA2D Instance
01825   * @retval State of bit (1 or 0).
01826   */
01827 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
01828 {
01829   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
01830 }
01831
01832 /**
01833   * @brief  Check if the DMA2D Transfer Complete Interrupt Flag is set or not
01834   * @rmtoll ISR          TCIF            LL_DMA2D_IsActiveFlag_TC
01835   * @param  DMA2Dx DMA2D Instance
01836   * @retval State of bit (1 or 0).
01837   */
01838 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
01839 {
01840   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
01841 }
01842
01843 /**
01844   * @brief  Check if the DMA2D Transfer Error Interrupt Flag is set or not
01845   * @rmtoll ISR          TEIF            LL_DMA2D_IsActiveFlag_TE
01846   * @param  DMA2Dx DMA2D Instance
01847   * @retval State of bit (1 or 0).
01848   */
01849 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
01850 {
01851   return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
01852 }
01853
01854 /**
01855   * @brief  Clear DMA2D Configuration Error Interrupt Flag
01856   * @rmtoll IFCR          CCEIF          LL_DMA2D_ClearFlag_CE
01857   * @param  DMA2Dx DMA2D Instance
01858   * @retval None
01859   */
01860 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
01861 {
01862   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
01863 }
01864
01865 /**
01866   * @brief  Clear DMA2D CLUT Transfer Complete Interrupt Flag
01867   * @rmtoll IFCR          CCTCIF          LL_DMA2D_ClearFlag_CTC
01868   * @param  DMA2Dx DMA2D Instance
01869   * @retval None
01870   */
01871 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
01872 {
01873   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
01874 }
01875
01876 /**
01877   * @brief  Clear DMA2D CLUT Access Error Interrupt Flag
01878   * @rmtoll IFCR          CAECIF          LL_DMA2D_ClearFlag_CAE
01879   * @param  DMA2Dx DMA2D Instance
01880   * @retval None
01881   */
01882 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
01883 {
01884   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
01885 }
01886
01887 /**
01888   * @brief  Clear DMA2D Transfer Watermark Interrupt Flag
01889   * @rmtoll IFCR          CTWIF          LL_DMA2D_ClearFlag_TW
01890   * @param  DMA2Dx DMA2D Instance
01891   * @retval None
01892   */
01893 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
01894 {
01895   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
01896 }
01897
01898 /**
01899   * @brief  Clear DMA2D Transfer Complete Interrupt Flag
01900   * @rmtoll IFCR          CTCIF          LL_DMA2D_ClearFlag_TC
01901   * @param  DMA2Dx DMA2D Instance
01902   * @retval None
01903   */
01904 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
01905 {
01906   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
01907 }
01908
01909 /**
01910   * @brief  Clear DMA2D Transfer Error Interrupt Flag
01911   * @rmtoll IFCR          CTEIF          LL_DMA2D_ClearFlag_TE
01912   * @param  DMA2Dx DMA2D Instance
01913   * @retval None
01914   */
01915 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
01916 {
01917   WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
01918 }
01919
01920 /**
01921   * @}
01922   */
01923
01924 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
01925   * @{
01926   */
01927
01928 /**
01929   * @brief  Enable Configuration Error Interrupt
01930   * @rmtoll CR          CEIE        LL_DMA2D_EnableIT_CE
01931   * @param  DMA2Dx DMA2D Instance
01932   * @retval None
01933   */
01934 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
01935 {
01936   SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
01937 }
01938
01939 /**
01940   * @brief  Enable CLUT Transfer Complete Interrupt
01941   * @rmtoll CR          CTCIE        LL_DMA2D_EnableIT_CTC
01942   * @param  DMA2Dx DMA2D Instance
01943   * @retval None
01944   */
01945 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
01946 {
01947   SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
01948 }
01949
01950 /**
01951   * @brief  Enable CLUT Access Error Interrupt
01952   * @rmtoll CR          CAEIE        LL_DMA2D_EnableIT_CAE
01953   * @param  DMA2Dx DMA2D Instance
01954   * @retval None
01955   */
01956 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
01957 {
01958   SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
01959 }
01960
01961 /**
01962   * @brief  Enable Transfer Watermark Interrupt
01963   * @rmtoll CR          TWIE        LL_DMA2D_EnableIT_TW
01964   * @param  DMA2Dx DMA2D Instance
01965   * @retval None
01966   */
01967 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
01968 {
01969   SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
01970 }
01971
01972 /**
01973   * @brief  Enable Transfer Complete Interrupt
01974   * @rmtoll CR          TCIE        LL_DMA2D_EnableIT_TC
01975   * @param  DMA2Dx DMA2D Instance
01976   * @retval None
01977   */
01978 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
01979 {
01980   SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
01981 }
01982
01983 /**
01984   * @brief  Enable Transfer Error Interrupt
01985   * @rmtoll CR          TEIE        LL_DMA2D_EnableIT_TE
01986   * @param  DMA2Dx DMA2D Instance
01987   * @retval None
01988   */
01989 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
01990 {
01991   SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
01992 }
01993
01994 /**
01995   * @brief  Disable Configuration Error Interrupt
01996   * @rmtoll CR          CEIE        LL_DMA2D_DisableIT_CE
01997   * @param  DMA2Dx DMA2D Instance
01998   * @retval None
01999   */
02000 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
02001 {
02002   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
02003 }
02004
02005 /**
02006   * @brief  Disable CLUT Transfer Complete Interrupt
02007   * @rmtoll CR          CTCIE        LL_DMA2D_DisableIT_CTC
02008   * @param  DMA2Dx DMA2D Instance
02009   * @retval None
02010   */
02011 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
02012 {
02013   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
02014 }
02015
02016 /**
02017   * @brief  Disable CLUT Access Error Interrupt
02018   * @rmtoll CR          CAEIE        LL_DMA2D_DisableIT_CAE
02019   * @param  DMA2Dx DMA2D Instance
02020   * @retval None
02021   */
02022 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
02023 {
02024   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
02025 }
02026
02027 /**
02028   * @brief  Disable Transfer Watermark Interrupt
02029   * @rmtoll CR          TWIE        LL_DMA2D_DisableIT_TW
02030   * @param  DMA2Dx DMA2D Instance
02031   * @retval None
02032   */
02033 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
02034 {
02035   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
02036 }
02037
02038 /**
02039   * @brief  Disable Transfer Complete Interrupt
02040   * @rmtoll CR          TCIE        LL_DMA2D_DisableIT_TC
02041   * @param  DMA2Dx DMA2D Instance
02042   * @retval None
02043   */
02044 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
02045 {
02046   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
02047 }
02048
02049 /**
02050   * @brief  Disable Transfer Error Interrupt
02051   * @rmtoll CR          TEIE        LL_DMA2D_DisableIT_TE
02052   * @param  DMA2Dx DMA2D Instance
02053   * @retval None
02054   */
02055 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
02056 {
02057   CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
02058 }
02059
02060 /**
02061   * @brief  Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
02062   * @rmtoll CR          CEIE        LL_DMA2D_IsEnabledIT_CE
02063   * @param  DMA2Dx DMA2D Instance
02064   * @retval State of bit (1 or 0).
02065   */
02066 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
02067 {
02068   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
02069 }
02070
02071 /**
02072   * @brief  Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
02073   * @rmtoll CR          CTCIE        LL_DMA2D_IsEnabledIT_CTC
02074   * @param  DMA2Dx DMA2D Instance
02075   * @retval State of bit (1 or 0).
02076   */
02077 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
02078 {
02079   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
02080 }
02081
02082 /**
02083   * @brief  Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
02084   * @rmtoll CR          CAEIE        LL_DMA2D_IsEnabledIT_CAE
02085   * @param  DMA2Dx DMA2D Instance
02086   * @retval State of bit (1 or 0).
02087   */
02088 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
02089 {
02090   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
02091 }
02092
02093 /**
02094   * @brief  Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
02095   * @rmtoll CR          TWIE        LL_DMA2D_IsEnabledIT_TW
02096   * @param  DMA2Dx DMA2D Instance
02097   * @retval State of bit (1 or 0).
02098   */
02099 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
02100 {
02101   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
02102 }
02103
02104 /**
02105   * @brief  Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
02106   * @rmtoll CR          TCIE        LL_DMA2D_IsEnabledIT_TC
02107   * @param  DMA2Dx DMA2D Instance
02108   * @retval State of bit (1 or 0).
02109   */
02110 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
02111 {
02112   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
02113 }
02114
02115 /**
02116   * @brief  Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
02117   * @rmtoll CR          TEIE        LL_DMA2D_IsEnabledIT_TE
02118   * @param  DMA2Dx DMA2D Instance
02119   * @retval State of bit (1 or 0).
02120   */
02121 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
02122 {
02123   return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
02124 }
02125
02126
02127
02128 /**
02129   * @}
02130   */
02131
02132 #if defined(USE_FULL_LL_DRIVER)
02133 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
02134   * @{
02135   */
02136
02137 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
02138 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
02139 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
02140 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
02141 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
02142 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
02143 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
02144 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
02145 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
02146 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
02147 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
02148
02149 /**
02150   * @}
02151   */
02152 #endif /* USE_FULL_LL_DRIVER */
02153
02154 /**
02155   * @}
02156   */
02157
02158 /**
02159   * @}
02160   */
02161
02162 #endif /* defined (DMA2D) */
02163
02164 /**
02165   * @}
02166   */
02167
02168 #ifdef __cplusplus
02169 }
02170 #endif
02171
02172 #endif /* STM32H7xx_LL_DMA2D_H */
02173
02174 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma.c Source File

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stm32h7xx_ll_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_dma.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMA1) || defined (DMA2)
00035
00036 /** @addtogroup DMA_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup DMA_LL_Private_Macros
00045   * @{
00046   */
00047 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00048                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00049                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00050
00051 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
00052                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
00053                                                  ((__VALUE__) == LL_DMA_MODE_PFCTRL))
00054
00055 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00056                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00057
00058 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00059                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00060
00061 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00062                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00063                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00064
00065 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00066                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00067                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00068
00069 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00070
00071 #if defined(ADC3)
00072 #define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
00073 #else
00074 #define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
00075 #endif /* ADC3 */
00076
00077 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00078                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00079                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00080                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00081
00082 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
00083                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
00084                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
00085                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
00086                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
00087                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
00088                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
00089                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
00090                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
00091                                                             ((STREAM) == LL_DMA_STREAM_ALL))) || \
00092                                                            (((INSTANCE) == DMA2) && \
00093                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
00094                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
00095                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
00096                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
00097                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
00098                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
00099                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
00100                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
00101                                                             ((STREAM) == LL_DMA_STREAM_ALL))))
00102
00103 #define IS_LL_DMA_FIFO_MODE_STATE(STATE)    (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
00104                                              ((STATE) == LL_DMA_FIFOMODE_ENABLE))
00105
00106 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
00107                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
00108                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
00109                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
00110
00111 #define IS_LL_DMA_MEMORY_BURST(BURST)       (((BURST) == LL_DMA_MBURST_SINGLE) || \
00112                                              ((BURST) == LL_DMA_MBURST_INC4)   || \
00113                                              ((BURST) == LL_DMA_MBURST_INC8)   || \
00114                                              ((BURST) == LL_DMA_MBURST_INC16))
00115
00116 #define IS_LL_DMA_PERIPHERAL_BURST(BURST)  (((BURST) == LL_DMA_PBURST_SINGLE) || \
00117                                             ((BURST) == LL_DMA_PBURST_INC4)   || \
00118                                             ((BURST) == LL_DMA_PBURST_INC8)   || \
00119                                             ((BURST) == LL_DMA_PBURST_INC16))
00120
00121 /**
00122   * @}
00123   */
00124
00125 /* Private function prototypes -----------------------------------------------*/
00126
00127 /* Exported functions --------------------------------------------------------*/
00128 /** @addtogroup DMA_LL_Exported_Functions
00129   * @{
00130   */
00131
00132 /** @addtogroup DMA_LL_EF_Init
00133   * @{
00134   */
00135
00136 /**
00137   * @brief  De-initialize the DMA registers to their default reset values.
00138   * @param  DMAx DMAx Instance
00139   * @param  Stream This parameter can be one of the following values:
00140   *         @arg @ref LL_DMA_STREAM_0
00141   *         @arg @ref LL_DMA_STREAM_1
00142   *         @arg @ref LL_DMA_STREAM_2
00143   *         @arg @ref LL_DMA_STREAM_3
00144   *         @arg @ref LL_DMA_STREAM_4
00145   *         @arg @ref LL_DMA_STREAM_5
00146   *         @arg @ref LL_DMA_STREAM_6
00147   *         @arg @ref LL_DMA_STREAM_7
00148   *         @arg @ref LL_DMA_STREAM_ALL
00149   * @retval An ErrorStatus enumeration value:
00150   *          - SUCCESS: DMA registers are de-initialized
00151   *          - ERROR: DMA registers are not de-initialized
00152   */
00153 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
00154 {
00155   DMA_Stream_TypeDef *tmp;
00156   ErrorStatus status = SUCCESS;
00157
00158   /* Check the DMA Instance DMAx and Stream parameters */
00159   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
00160
00161   if (Stream == LL_DMA_STREAM_ALL)
00162   {
00163     if (DMAx == DMA1)
00164     {
00165       /* Force reset of DMA clock */
00166       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00167
00168       /* Release reset of DMA clock */
00169       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00170     }
00171     else if (DMAx == DMA2)
00172     {
00173       /* Force reset of DMA clock */
00174        LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
00175
00176       /* Release reset of DMA clock */
00177       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
00178     }
00179     else
00180     {
00181       status = ERROR;
00182     }
00183   }
00184   else
00185   {
00186     /* Disable the selected Stream */
00187     LL_DMA_DisableStream(DMAx, Stream);
00188
00189     /* Get the DMA Stream Instance */
00190     tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
00191
00192     /* Reset DMAx_Streamy configuration register */
00193     LL_DMA_WriteReg(tmp, CR, 0U);
00194
00195     /* Reset DMAx_Streamy remaining bytes register */
00196     LL_DMA_WriteReg(tmp, NDTR, 0U);
00197
00198     /* Reset DMAx_Streamy peripheral address register */
00199     LL_DMA_WriteReg(tmp, PAR, 0U);
00200
00201     /* Reset DMAx_Streamy memory address register */
00202     LL_DMA_WriteReg(tmp, M0AR, 0U);
00203
00204     /* Reset DMAx_Streamy memory address register */
00205     LL_DMA_WriteReg(tmp, M1AR, 0U);
00206
00207     /* Reset DMAx_Streamy FIFO control register */
00208     LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
00209
00210     /* Reset Channel register field for DMAx Stream */
00211     LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
00212
00213     if (Stream == LL_DMA_STREAM_0)
00214     {
00215       /* Reset the Stream0 pending flags */
00216       DMAx->LIFCR = 0x0000003FU;
00217     }
00218     else if (Stream == LL_DMA_STREAM_1)
00219     {
00220       /* Reset the Stream1 pending flags */
00221       DMAx->LIFCR = 0x00000F40U;
00222     }
00223     else if (Stream == LL_DMA_STREAM_2)
00224     {
00225       /* Reset the Stream2 pending flags */
00226       DMAx->LIFCR = 0x003F0000U;
00227     }
00228     else if (Stream == LL_DMA_STREAM_3)
00229     {
00230       /* Reset the Stream3 pending flags */
00231       DMAx->LIFCR = 0x0F400000U;
00232     }
00233     else if (Stream == LL_DMA_STREAM_4)
00234     {
00235       /* Reset the Stream4 pending flags */
00236       DMAx->HIFCR = 0x0000003FU;
00237     }
00238     else if (Stream == LL_DMA_STREAM_5)
00239     {
00240       /* Reset the Stream5 pending flags */
00241       DMAx->HIFCR = 0x00000F40U;
00242     }
00243     else if (Stream == LL_DMA_STREAM_6)
00244     {
00245       /* Reset the Stream6 pending flags */
00246       DMAx->HIFCR = 0x003F0000U;
00247     }
00248     else if (Stream == LL_DMA_STREAM_7)
00249     {
00250       /* Reset the Stream7 pending flags */
00251       DMAx->HIFCR = 0x0F400000U;
00252     }
00253     else
00254     {
00255       status = ERROR;
00256     }
00257   }
00258
00259   return (uint32_t)status;
00260 }
00261
00262 /**
00263   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00264   * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
00265   *         @arg @ref __LL_DMA_GET_INSTANCE
00266   *         @arg @ref __LL_DMA_GET_STREAM
00267   * @param  DMAx DMAx Instance
00268   * @param  Stream This parameter can be one of the following values:
00269   *         @arg @ref LL_DMA_STREAM_0
00270   *         @arg @ref LL_DMA_STREAM_1
00271   *         @arg @ref LL_DMA_STREAM_2
00272   *         @arg @ref LL_DMA_STREAM_3
00273   *         @arg @ref LL_DMA_STREAM_4
00274   *         @arg @ref LL_DMA_STREAM_5
00275   *         @arg @ref LL_DMA_STREAM_6
00276   *         @arg @ref LL_DMA_STREAM_7
00277   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00278   * @retval An ErrorStatus enumeration value:
00279   *          - SUCCESS: DMA registers are initialized
00280   *          - ERROR: Not applicable
00281   */
00282 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
00283 {
00284   /* Check the DMA Instance DMAx and Stream parameters */
00285   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
00286
00287   /* Check the DMA parameters from DMA_InitStruct */
00288   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00289   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00290   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00291   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00292   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00293   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00294   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00295   assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
00296   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00297   assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
00298
00299   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
00300      when FIFO mode is enabled */
00301   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
00302   {
00303     assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
00304     assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
00305     assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
00306   }
00307
00308   /*---------------------------- DMAx SxCR Configuration ------------------------
00309    * Configure DMAx_Streamy: data transfer direction, data transfer mode,
00310    *                          peripheral and memory increment mode,
00311    *                          data size alignment and  priority level with parameters :
00312    * - Direction:      DMA_SxCR_DIR[1:0] bits
00313    * - Mode:           DMA_SxCR_CIRC bit
00314    * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
00315    * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
00316    * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
00317    * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
00318    * - Priority:               DMA_SxCR_PL[1:0] bits
00319    */
00320   LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
00321                         DMA_InitStruct->Mode                    | \
00322                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
00323                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
00324                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
00325                         DMA_InitStruct->MemoryOrM2MDstDataSize  | \
00326                         DMA_InitStruct->Priority
00327                        );
00328
00329   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
00330   {
00331     /*---------------------------- DMAx SxFCR Configuration ------------------------
00332      * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
00333      * - FIFOMode:                DMA_SxFCR_DMDIS bit
00334      * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
00335      */
00336     LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
00337
00338     /*---------------------------- DMAx SxCR Configuration --------------------------
00339      * Configure DMAx_Streamy:  memory burst transfer with parameters :
00340      * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
00341      */
00342     LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
00343
00344     /*---------------------------- DMAx SxCR Configuration --------------------------
00345      * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
00346      * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
00347      */
00348     LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
00349   }
00350
00351   /*-------------------------- DMAx SxM0AR Configuration --------------------------
00352    * Configure the memory or destination base address with parameter :
00353    * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
00354    */
00355   LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
00356
00357   /*-------------------------- DMAx SxPAR Configuration ---------------------------
00358    * Configure the peripheral or source base address with parameter :
00359    * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
00360    */
00361   LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
00362
00363   /*--------------------------- DMAx SxNDTR Configuration -------------------------
00364    * Configure the peripheral base address with parameter :
00365    * - NbData:                    DMA_SxNDT[15:0] bits
00366    */
00367   LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
00368
00369   /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
00370    * Configure the peripheral base address with parameter :
00371    * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
00372    */
00373   LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
00374
00375   return (uint32_t)SUCCESS;
00376 }
00377
00378 /**
00379   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00380   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00381   * @retval None
00382   */
00383 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00384 {
00385   /* Set DMA_InitStruct fields to default values */
00386   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00387   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00388   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00389   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00390   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00391   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00392   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00393   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00394   DMA_InitStruct->NbData                 = 0x00000000U;
00395   DMA_InitStruct->PeriphRequest          = LL_DMAMUX1_REQ_MEM2MEM;
00396   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00397   DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
00398   DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
00399   DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
00400   DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
00401 }
00402
00403 /**
00404   * @}
00405   */
00406
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 #endif /* DMA1 || DMA2 */
00416
00417 /**
00418   * @}
00419   */
00420
00421 #endif /* USE_FULL_LL_DRIVER */
00422
00423 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dma.h Source File

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stm32h7xx_ll_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_DMA_H
00022 #define STM32H7xx_LL_DMA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030 #include "stm32h7xx_ll_dmamux.h"
00031
00032 /** @addtogroup STM32H7xx_LL_Driver
00033   * @{
00034   */
00035
00036 #if defined (DMA1) || defined (DMA2)
00037
00038 /** @defgroup DMA_LL DMA
00039   * @{
00040   */
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00045   * @{
00046   */
00047 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
00048 static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
00049 {
00050   (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
00051   (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
00052   (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
00053   (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
00054   (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
00055   (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
00056   (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
00057   (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
00058 };
00059
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macros ------------------------------------------------------------*/
00066
00067 /**
00068   * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
00069   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
00070   *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
00071   * @param  __DMA_INSTANCE__ DMAx
00072   * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
00073   */
00074 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
00075 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
00076
00077 /* Exported types ------------------------------------------------------------*/
00078 #if defined(USE_FULL_LL_DRIVER)
00079 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00080   * @{
00081   */
00082 typedef struct
00083 {
00084   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00085                                         or as Source base address in case of memory to memory transfer direction.
00086
00087                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00088
00089   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00090                                         or as Destination base address in case of memory to memory transfer direction.
00091
00092                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00093
00094   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00095                                         from memory to memory or from peripheral to memory.
00096                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00097
00098                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00099
00100   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00101                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00102                                         @note The circular buffer mode cannot be used if the memory to memory
00103                                               data transfer direction is configured on the selected Stream
00104
00105                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00106
00107   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00108                                         is incremented or not.
00109                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00110
00111                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00112
00113   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00114                                         is incremented or not.
00115                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00116
00117                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00118
00119   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00120                                         in case of memory to memory transfer direction.
00121                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00122
00123                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00124
00125   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00126                                         in case of memory to memory transfer direction.
00127                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00128
00129                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00130
00131   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00132                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00133                                         or MemorySize parameters depending in the transfer direction.
00134                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00135
00136                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00137
00138   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00139                                         This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
00140
00141                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
00142
00143   uint32_t Priority;               /*!< Specifies the channel priority level.
00144                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00145
00146                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
00147
00148   uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
00149                                         This parameter can be a value of @ref DMA_LL_FIFOMODE
00150                                         @note The Direct mode (FIFO mode disabled) cannot be used if the
00151                                         memory-to-memory data transfer is configured on the selected stream
00152
00153                                         This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
00154
00155   uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
00156                                         This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
00157
00158                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
00159
00160   uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
00161                                         It specifies the amount of data to be transferred in a single non interruptible
00162                                         transaction.
00163                                         This parameter can be a value of @ref DMA_LL_EC_MBURST
00164                                         @note The burst mode is possible only if the address Increment mode is enabled.
00165
00166                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
00167
00168   uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
00169                                         It specifies the amount of data to be transferred in a single non interruptible
00170                                         transaction.
00171                                         This parameter can be a value of @ref DMA_LL_EC_PBURST
00172                                         @note The burst mode is possible only if the address Increment mode is enabled.
00173
00174                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
00175
00176 } LL_DMA_InitTypeDef;
00177 /**
00178   * @}
00179   */
00180 #endif /*USE_FULL_LL_DRIVER*/
00181 /* Exported constants --------------------------------------------------------*/
00182 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00183   * @{
00184   */
00185
00186 /** @defgroup DMA_LL_EC_STREAM STREAM
00187   * @{
00188   */
00189 #define LL_DMA_STREAM_0                   0x00000000U
00190 #define LL_DMA_STREAM_1                   0x00000001U
00191 #define LL_DMA_STREAM_2                   0x00000002U
00192 #define LL_DMA_STREAM_3                   0x00000003U
00193 #define LL_DMA_STREAM_4                   0x00000004U
00194 #define LL_DMA_STREAM_5                   0x00000005U
00195 #define LL_DMA_STREAM_6                   0x00000006U
00196 #define LL_DMA_STREAM_7                   0x00000007U
00197 #define LL_DMA_STREAM_ALL                 0xFFFF0000U
00198 /**
00199   * @}
00200   */
00201
00202
00203 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
00204   * @{
00205   */
00206 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
00207 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
00208 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup DMA_LL_EC_MODE MODE
00214   * @{
00215   */
00216 #define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
00217 #define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
00218 #define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
00224   * @{
00225   */
00226 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
00227 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup DMA_LL_EC_PERIPH PERIPH
00233   * @{
00234   */
00235 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
00236 #define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup DMA_LL_EC_MEMORY MEMORY
00242   * @{
00243   */
00244 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
00245 #define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
00251   * @{
00252   */
00253 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
00254 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
00255 #define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
00261   * @{
00262   */
00263 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
00264 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
00265 #define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
00271   * @{
00272   */
00273 #define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */
00274 #define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
00280   * @{
00281   */
00282 #define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
00283 #define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
00284 #define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
00285 #define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
00286 /**
00287   * @}
00288   */
00289
00290
00291 /** @defgroup DMA_LL_EC_MBURST MBURST
00292   * @{
00293   */
00294 #define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */
00295 #define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */
00296 #define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */
00297 #define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup DMA_LL_EC_PBURST PBURST
00303   * @{
00304   */
00305 #define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */
00306 #define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */
00307 #define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */
00308 #define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
00314   * @{
00315   */
00316 #define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
00317 #define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
00323   * @{
00324   */
00325 #define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
00326 #define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
00327 #define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
00328 #define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
00329 #define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
00330 #define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
00336   * @{
00337   */
00338 #define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
00339 #define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
00340 #define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
00341 #define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
00347   * @{
00348   */
00349 #define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
00350 #define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
00351 /**
00352   * @}
00353   */
00354
00355 /**
00356   * @}
00357   */
00358
00359 /* Exported macro ------------------------------------------------------------*/
00360 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00361   * @{
00362   */
00363
00364 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00365   * @{
00366   */
00367 /**
00368   * @brief  Write a value in DMA register
00369   * @param  __INSTANCE__ DMA Instance
00370   * @param  __REG__ Register to be written
00371   * @param  __VALUE__ Value to be written in the register
00372   * @retval None
00373   */
00374 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00375
00376 /**
00377   * @brief  Read a value in DMA register
00378   * @param  __INSTANCE__ DMA Instance
00379   * @param  __REG__ Register to be read
00380   * @retval Register value
00381   */
00382 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
00388   * @{
00389   */
00390 /**
00391   * @brief  Convert DMAx_Streamy into DMAx
00392   * @param  __STREAM_INSTANCE__ DMAx_Streamy
00393   * @retval DMAx
00394   */
00395 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
00396 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
00397
00398 /**
00399   * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
00400   * @param  __STREAM_INSTANCE__ DMAx_Streamy
00401   * @retval LL_DMA_STREAM_y
00402   */
00403 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
00404 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
00405  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
00406  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
00407  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
00408  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
00409  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
00410  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
00411  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
00412  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
00413  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
00414  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
00415  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
00416  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
00417  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
00418  LL_DMA_STREAM_7)
00419
00420 /**
00421   * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
00422   * @param  __DMA_INSTANCE__ DMAx
00423   * @param  __STREAM__ LL_DMA_STREAM_y
00424   * @retval DMAx_Streamy
00425   */
00426 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
00427 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
00428  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
00429  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
00430  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
00431  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
00432  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
00433  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
00434  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
00435  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
00436  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
00437  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
00438  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
00439  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
00440  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
00441  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
00442  DMA2_Stream7)
00443
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452
00453 /* Exported functions --------------------------------------------------------*/
00454 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00455  * @{
00456  */
00457
00458 /** @defgroup DMA_LL_EF_Configuration Configuration
00459   * @{
00460   */
00461 /**
00462   * @brief Enable DMA stream.
00463   * @rmtoll CR          EN            LL_DMA_EnableStream
00464   * @param  DMAx DMAx Instance
00465   * @param  Stream This parameter can be one of the following values:
00466   *         @arg @ref LL_DMA_STREAM_0
00467   *         @arg @ref LL_DMA_STREAM_1
00468   *         @arg @ref LL_DMA_STREAM_2
00469   *         @arg @ref LL_DMA_STREAM_3
00470   *         @arg @ref LL_DMA_STREAM_4
00471   *         @arg @ref LL_DMA_STREAM_5
00472   *         @arg @ref LL_DMA_STREAM_6
00473   *         @arg @ref LL_DMA_STREAM_7
00474   * @retval None
00475   */
00476 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
00477 {
00478   register uint32_t dma_base_addr = (uint32_t)DMAx;
00479
00480   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
00481 }
00482
00483 /**
00484   * @brief Disable DMA stream.
00485   * @rmtoll CR          EN            LL_DMA_DisableStream
00486   * @param  DMAx DMAx Instance
00487   * @param  Stream This parameter can be one of the following values:
00488   *         @arg @ref LL_DMA_STREAM_0
00489   *         @arg @ref LL_DMA_STREAM_1
00490   *         @arg @ref LL_DMA_STREAM_2
00491   *         @arg @ref LL_DMA_STREAM_3
00492   *         @arg @ref LL_DMA_STREAM_4
00493   *         @arg @ref LL_DMA_STREAM_5
00494   *         @arg @ref LL_DMA_STREAM_6
00495   *         @arg @ref LL_DMA_STREAM_7
00496   * @retval None
00497   */
00498 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
00499 {
00500   register uint32_t dma_base_addr = (uint32_t)DMAx;
00501
00502   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
00503 }
00504
00505 /**
00506   * @brief Check if DMA stream is enabled or disabled.
00507   * @rmtoll CR          EN            LL_DMA_IsEnabledStream
00508   * @param  DMAx DMAx Instance
00509   * @param  Stream This parameter can be one of the following values:
00510   *         @arg @ref LL_DMA_STREAM_0
00511   *         @arg @ref LL_DMA_STREAM_1
00512   *         @arg @ref LL_DMA_STREAM_2
00513   *         @arg @ref LL_DMA_STREAM_3
00514   *         @arg @ref LL_DMA_STREAM_4
00515   *         @arg @ref LL_DMA_STREAM_5
00516   *         @arg @ref LL_DMA_STREAM_6
00517   *         @arg @ref LL_DMA_STREAM_7
00518   * @retval State of bit (1 or 0).
00519   */
00520 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
00521 {
00522   register uint32_t dma_base_addr = (uint32_t)DMAx;
00523
00524   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
00525 }
00526
00527 /**
00528   * @brief  Configure all parameters linked to DMA transfer.
00529   * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
00530   *         CR          CIRC          LL_DMA_ConfigTransfer\n
00531   *         CR          PINC          LL_DMA_ConfigTransfer\n
00532   *         CR          MINC          LL_DMA_ConfigTransfer\n
00533   *         CR          PSIZE         LL_DMA_ConfigTransfer\n
00534   *         CR          MSIZE         LL_DMA_ConfigTransfer\n
00535   *         CR          PL            LL_DMA_ConfigTransfer\n
00536   *         CR          PFCTRL        LL_DMA_ConfigTransfer
00537   * @param  DMAx DMAx Instance
00538   * @param  Stream This parameter can be one of the following values:
00539   *         @arg @ref LL_DMA_STREAM_0
00540   *         @arg @ref LL_DMA_STREAM_1
00541   *         @arg @ref LL_DMA_STREAM_2
00542   *         @arg @ref LL_DMA_STREAM_3
00543   *         @arg @ref LL_DMA_STREAM_4
00544   *         @arg @ref LL_DMA_STREAM_5
00545   *         @arg @ref LL_DMA_STREAM_6
00546   *         @arg @ref LL_DMA_STREAM_7
00547   * @param  Configuration This parameter must be a combination of all the following values:
00548   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00549   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
00550   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00551   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00552   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00553   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00554   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00555   *@retval None
00556   */
00557 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
00558 {
00559   register uint32_t dma_base_addr = (uint32_t)DMAx;
00560
00561   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
00562              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
00563              Configuration);
00564 }
00565
00566 /**
00567   * @brief Set Data transfer direction (read from peripheral or from memory).
00568   * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
00569   * @param  DMAx DMAx Instance
00570   * @param  Stream This parameter can be one of the following values:
00571   *         @arg @ref LL_DMA_STREAM_0
00572   *         @arg @ref LL_DMA_STREAM_1
00573   *         @arg @ref LL_DMA_STREAM_2
00574   *         @arg @ref LL_DMA_STREAM_3
00575   *         @arg @ref LL_DMA_STREAM_4
00576   *         @arg @ref LL_DMA_STREAM_5
00577   *         @arg @ref LL_DMA_STREAM_6
00578   *         @arg @ref LL_DMA_STREAM_7
00579   * @param  Direction This parameter can be one of the following values:
00580   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00581   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00582   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00583   * @retval None
00584   */
00585 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
00586 {
00587   register uint32_t dma_base_addr = (uint32_t)DMAx;
00588
00589   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
00590 }
00591
00592 /**
00593   * @brief Get Data transfer direction (read from peripheral or from memory).
00594   * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
00595   * @param  DMAx DMAx Instance
00596   * @param  Stream This parameter can be one of the following values:
00597   *         @arg @ref LL_DMA_STREAM_0
00598   *         @arg @ref LL_DMA_STREAM_1
00599   *         @arg @ref LL_DMA_STREAM_2
00600   *         @arg @ref LL_DMA_STREAM_3
00601   *         @arg @ref LL_DMA_STREAM_4
00602   *         @arg @ref LL_DMA_STREAM_5
00603   *         @arg @ref LL_DMA_STREAM_6
00604   *         @arg @ref LL_DMA_STREAM_7
00605   * @retval Returned value can be one of the following values:
00606   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00607   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00608   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00609   */
00610 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
00611 {
00612   register uint32_t dma_base_addr = (uint32_t)DMAx;
00613
00614   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
00615 }
00616
00617 /**
00618   * @brief Set DMA mode normal, circular or peripheral flow control.
00619   * @rmtoll CR          CIRC           LL_DMA_SetMode\n
00620   *         CR          PFCTRL         LL_DMA_SetMode
00621   * @param  DMAx DMAx Instance
00622   * @param  Stream This parameter can be one of the following values:
00623   *         @arg @ref LL_DMA_STREAM_0
00624   *         @arg @ref LL_DMA_STREAM_1
00625   *         @arg @ref LL_DMA_STREAM_2
00626   *         @arg @ref LL_DMA_STREAM_3
00627   *         @arg @ref LL_DMA_STREAM_4
00628   *         @arg @ref LL_DMA_STREAM_5
00629   *         @arg @ref LL_DMA_STREAM_6
00630   *         @arg @ref LL_DMA_STREAM_7
00631   * @param  Mode This parameter can be one of the following values:
00632   *         @arg @ref LL_DMA_MODE_NORMAL
00633   *         @arg @ref LL_DMA_MODE_CIRCULAR
00634   *         @arg @ref LL_DMA_MODE_PFCTRL
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
00638 {
00639   register uint32_t dma_base_addr = (uint32_t)DMAx;
00640
00641   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
00642 }
00643
00644 /**
00645   * @brief Get DMA mode normal, circular or peripheral flow control.
00646   * @rmtoll CR          CIRC           LL_DMA_GetMode\n
00647   *         CR          PFCTRL         LL_DMA_GetMode
00648   * @param  DMAx DMAx Instance
00649   * @param  Stream This parameter can be one of the following values:
00650   *         @arg @ref LL_DMA_STREAM_0
00651   *         @arg @ref LL_DMA_STREAM_1
00652   *         @arg @ref LL_DMA_STREAM_2
00653   *         @arg @ref LL_DMA_STREAM_3
00654   *         @arg @ref LL_DMA_STREAM_4
00655   *         @arg @ref LL_DMA_STREAM_5
00656   *         @arg @ref LL_DMA_STREAM_6
00657   *         @arg @ref LL_DMA_STREAM_7
00658   * @retval Returned value can be one of the following values:
00659   *         @arg @ref LL_DMA_MODE_NORMAL
00660   *         @arg @ref LL_DMA_MODE_CIRCULAR
00661   *         @arg @ref LL_DMA_MODE_PFCTRL
00662   */
00663 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
00664 {
00665   register uint32_t dma_base_addr = (uint32_t)DMAx;
00666
00667   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
00668 }
00669
00670 /**
00671   * @brief Set Peripheral increment mode.
00672   * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
00673   * @param  DMAx DMAx Instance
00674   * @param  Stream This parameter can be one of the following values:
00675   *         @arg @ref LL_DMA_STREAM_0
00676   *         @arg @ref LL_DMA_STREAM_1
00677   *         @arg @ref LL_DMA_STREAM_2
00678   *         @arg @ref LL_DMA_STREAM_3
00679   *         @arg @ref LL_DMA_STREAM_4
00680   *         @arg @ref LL_DMA_STREAM_5
00681   *         @arg @ref LL_DMA_STREAM_6
00682   *         @arg @ref LL_DMA_STREAM_7
00683   * @param  IncrementMode This parameter can be one of the following values:
00684   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00685   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00686   * @retval None
00687   */
00688 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
00689 {
00690   register uint32_t dma_base_addr = (uint32_t)DMAx;
00691
00692   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
00693 }
00694
00695 /**
00696   * @brief Get Peripheral increment mode.
00697   * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
00698   * @param  DMAx DMAx Instance
00699   * @param  Stream This parameter can be one of the following values:
00700   *         @arg @ref LL_DMA_STREAM_0
00701   *         @arg @ref LL_DMA_STREAM_1
00702   *         @arg @ref LL_DMA_STREAM_2
00703   *         @arg @ref LL_DMA_STREAM_3
00704   *         @arg @ref LL_DMA_STREAM_4
00705   *         @arg @ref LL_DMA_STREAM_5
00706   *         @arg @ref LL_DMA_STREAM_6
00707   *         @arg @ref LL_DMA_STREAM_7
00708   * @retval Returned value can be one of the following values:
00709   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00710   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00711   */
00712 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
00713 {
00714   register uint32_t dma_base_addr = (uint32_t)DMAx;
00715
00716   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
00717 }
00718
00719 /**
00720   * @brief Set Memory increment mode.
00721   * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
00722   * @param  DMAx DMAx Instance
00723   * @param  Stream This parameter can be one of the following values:
00724   *         @arg @ref LL_DMA_STREAM_0
00725   *         @arg @ref LL_DMA_STREAM_1
00726   *         @arg @ref LL_DMA_STREAM_2
00727   *         @arg @ref LL_DMA_STREAM_3
00728   *         @arg @ref LL_DMA_STREAM_4
00729   *         @arg @ref LL_DMA_STREAM_5
00730   *         @arg @ref LL_DMA_STREAM_6
00731   *         @arg @ref LL_DMA_STREAM_7
00732   * @param  IncrementMode This parameter can be one of the following values:
00733   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00734   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
00738 {
00739   register uint32_t dma_base_addr = (uint32_t)DMAx;
00740
00741   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
00742 }
00743
00744 /**
00745   * @brief Get Memory increment mode.
00746   * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
00747   * @param  DMAx DMAx Instance
00748   * @param  Stream This parameter can be one of the following values:
00749   *         @arg @ref LL_DMA_STREAM_0
00750   *         @arg @ref LL_DMA_STREAM_1
00751   *         @arg @ref LL_DMA_STREAM_2
00752   *         @arg @ref LL_DMA_STREAM_3
00753   *         @arg @ref LL_DMA_STREAM_4
00754   *         @arg @ref LL_DMA_STREAM_5
00755   *         @arg @ref LL_DMA_STREAM_6
00756   *         @arg @ref LL_DMA_STREAM_7
00757   * @retval Returned value can be one of the following values:
00758   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00759   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00760   */
00761 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
00762 {
00763   register uint32_t dma_base_addr = (uint32_t)DMAx;
00764
00765   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
00766 }
00767
00768 /**
00769   * @brief Set Peripheral size.
00770   * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
00771   * @param  DMAx DMAx Instance
00772   * @param  Stream This parameter can be one of the following values:
00773   *         @arg @ref LL_DMA_STREAM_0
00774   *         @arg @ref LL_DMA_STREAM_1
00775   *         @arg @ref LL_DMA_STREAM_2
00776   *         @arg @ref LL_DMA_STREAM_3
00777   *         @arg @ref LL_DMA_STREAM_4
00778   *         @arg @ref LL_DMA_STREAM_5
00779   *         @arg @ref LL_DMA_STREAM_6
00780   *         @arg @ref LL_DMA_STREAM_7
00781   * @param  Size This parameter can be one of the following values:
00782   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00783   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00784   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00785   * @retval None
00786   */
00787 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
00788 {
00789   register uint32_t dma_base_addr = (uint32_t)DMAx;
00790
00791   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
00792 }
00793
00794 /**
00795   * @brief Get Peripheral size.
00796   * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
00797   * @param  DMAx DMAx Instance
00798   * @param  Stream This parameter can be one of the following values:
00799   *         @arg @ref LL_DMA_STREAM_0
00800   *         @arg @ref LL_DMA_STREAM_1
00801   *         @arg @ref LL_DMA_STREAM_2
00802   *         @arg @ref LL_DMA_STREAM_3
00803   *         @arg @ref LL_DMA_STREAM_4
00804   *         @arg @ref LL_DMA_STREAM_5
00805   *         @arg @ref LL_DMA_STREAM_6
00806   *         @arg @ref LL_DMA_STREAM_7
00807   * @retval Returned value can be one of the following values:
00808   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00809   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00810   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00811   */
00812 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
00813 {
00814   register uint32_t dma_base_addr = (uint32_t)DMAx;
00815
00816   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
00817 }
00818
00819 /**
00820   * @brief Set Memory size.
00821   * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
00822   * @param  DMAx DMAx Instance
00823   * @param  Stream This parameter can be one of the following values:
00824   *         @arg @ref LL_DMA_STREAM_0
00825   *         @arg @ref LL_DMA_STREAM_1
00826   *         @arg @ref LL_DMA_STREAM_2
00827   *         @arg @ref LL_DMA_STREAM_3
00828   *         @arg @ref LL_DMA_STREAM_4
00829   *         @arg @ref LL_DMA_STREAM_5
00830   *         @arg @ref LL_DMA_STREAM_6
00831   *         @arg @ref LL_DMA_STREAM_7
00832   * @param  Size This parameter can be one of the following values:
00833   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00834   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00835   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00836   * @retval None
00837   */
00838 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
00839 {
00840   register uint32_t dma_base_addr = (uint32_t)DMAx;
00841
00842   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
00843 }
00844
00845 /**
00846   * @brief Get Memory size.
00847   * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
00848   * @param  DMAx DMAx Instance
00849   * @param  Stream This parameter can be one of the following values:
00850   *         @arg @ref LL_DMA_STREAM_0
00851   *         @arg @ref LL_DMA_STREAM_1
00852   *         @arg @ref LL_DMA_STREAM_2
00853   *         @arg @ref LL_DMA_STREAM_3
00854   *         @arg @ref LL_DMA_STREAM_4
00855   *         @arg @ref LL_DMA_STREAM_5
00856   *         @arg @ref LL_DMA_STREAM_6
00857   *         @arg @ref LL_DMA_STREAM_7
00858   * @retval Returned value can be one of the following values:
00859   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00860   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00861   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00862   */
00863 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
00864 {
00865   register uint32_t dma_base_addr = (uint32_t)DMAx;
00866
00867   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
00868 }
00869
00870 /**
00871   * @brief Set Peripheral increment offset size.
00872   * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
00873   * @param  DMAx DMAx Instance
00874   * @param  Stream This parameter can be one of the following values:
00875   *         @arg @ref LL_DMA_STREAM_0
00876   *         @arg @ref LL_DMA_STREAM_1
00877   *         @arg @ref LL_DMA_STREAM_2
00878   *         @arg @ref LL_DMA_STREAM_3
00879   *         @arg @ref LL_DMA_STREAM_4
00880   *         @arg @ref LL_DMA_STREAM_5
00881   *         @arg @ref LL_DMA_STREAM_6
00882   *         @arg @ref LL_DMA_STREAM_7
00883   * @param  OffsetSize This parameter can be one of the following values:
00884   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
00885   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
00886   * @retval None
00887   */
00888 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
00889 {
00890   register uint32_t dma_base_addr = (uint32_t)DMAx;
00891
00892   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
00893 }
00894
00895 /**
00896   * @brief Get Peripheral increment offset size.
00897   * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
00898   * @param  DMAx DMAx Instance
00899   * @param  Stream This parameter can be one of the following values:
00900   *         @arg @ref LL_DMA_STREAM_0
00901   *         @arg @ref LL_DMA_STREAM_1
00902   *         @arg @ref LL_DMA_STREAM_2
00903   *         @arg @ref LL_DMA_STREAM_3
00904   *         @arg @ref LL_DMA_STREAM_4
00905   *         @arg @ref LL_DMA_STREAM_5
00906   *         @arg @ref LL_DMA_STREAM_6
00907   *         @arg @ref LL_DMA_STREAM_7
00908   * @retval Returned value can be one of the following values:
00909   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
00910   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
00911   */
00912 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
00913 {
00914   register uint32_t dma_base_addr = (uint32_t)DMAx;
00915
00916   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
00917 }
00918
00919 /**
00920   * @brief Set Stream priority level.
00921   * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
00922   * @param  DMAx DMAx Instance
00923   * @param  Stream This parameter can be one of the following values:
00924   *         @arg @ref LL_DMA_STREAM_0
00925   *         @arg @ref LL_DMA_STREAM_1
00926   *         @arg @ref LL_DMA_STREAM_2
00927   *         @arg @ref LL_DMA_STREAM_3
00928   *         @arg @ref LL_DMA_STREAM_4
00929   *         @arg @ref LL_DMA_STREAM_5
00930   *         @arg @ref LL_DMA_STREAM_6
00931   *         @arg @ref LL_DMA_STREAM_7
00932   * @param  Priority This parameter can be one of the following values:
00933   *         @arg @ref LL_DMA_PRIORITY_LOW
00934   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00935   *         @arg @ref LL_DMA_PRIORITY_HIGH
00936   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00937   * @retval None
00938   */
00939 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
00940 {
00941   register uint32_t dma_base_addr = (uint32_t)DMAx;
00942
00943   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
00944 }
00945
00946 /**
00947   * @brief Get Stream priority level.
00948   * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
00949   * @param  DMAx DMAx Instance
00950   * @param  Stream This parameter can be one of the following values:
00951   *         @arg @ref LL_DMA_STREAM_0
00952   *         @arg @ref LL_DMA_STREAM_1
00953   *         @arg @ref LL_DMA_STREAM_2
00954   *         @arg @ref LL_DMA_STREAM_3
00955   *         @arg @ref LL_DMA_STREAM_4
00956   *         @arg @ref LL_DMA_STREAM_5
00957   *         @arg @ref LL_DMA_STREAM_6
00958   *         @arg @ref LL_DMA_STREAM_7
00959   * @retval Returned value can be one of the following values:
00960   *         @arg @ref LL_DMA_PRIORITY_LOW
00961   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00962   *         @arg @ref LL_DMA_PRIORITY_HIGH
00963   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00964   */
00965 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
00966 {
00967   register uint32_t dma_base_addr = (uint32_t)DMAx;
00968
00969   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
00970 }
00971
00972 /**
00973   * @brief Set Number of data to transfer.
00974   * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
00975   * @note   This action has no effect if
00976   *         stream is enabled.
00977   * @param  DMAx DMAx Instance
00978   * @param  Stream This parameter can be one of the following values:
00979   *         @arg @ref LL_DMA_STREAM_0
00980   *         @arg @ref LL_DMA_STREAM_1
00981   *         @arg @ref LL_DMA_STREAM_2
00982   *         @arg @ref LL_DMA_STREAM_3
00983   *         @arg @ref LL_DMA_STREAM_4
00984   *         @arg @ref LL_DMA_STREAM_5
00985   *         @arg @ref LL_DMA_STREAM_6
00986   *         @arg @ref LL_DMA_STREAM_7
00987   * @param  NbData Between 0 to 0xFFFFFFFF
00988   * @retval None
00989   */
00990 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
00991 {
00992   register uint32_t dma_base_addr = (uint32_t)DMAx;
00993
00994   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
00995 }
00996
00997 /**
00998   * @brief Get Number of data to transfer.
00999   * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
01000   * @note   Once the stream is enabled, the return value indicate the
01001   *         remaining bytes to be transmitted.
01002   * @param  DMAx DMAx Instance
01003   * @param  Stream This parameter can be one of the following values:
01004   *         @arg @ref LL_DMA_STREAM_0
01005   *         @arg @ref LL_DMA_STREAM_1
01006   *         @arg @ref LL_DMA_STREAM_2
01007   *         @arg @ref LL_DMA_STREAM_3
01008   *         @arg @ref LL_DMA_STREAM_4
01009   *         @arg @ref LL_DMA_STREAM_5
01010   *         @arg @ref LL_DMA_STREAM_6
01011   *         @arg @ref LL_DMA_STREAM_7
01012   * @retval Between 0 to 0xFFFFFFFF
01013   */
01014 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
01015 {
01016   register uint32_t dma_base_addr = (uint32_t)DMAx;
01017
01018   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
01019 }
01020 /**
01021   * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.
01022   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
01023   *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
01024   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
01025   * @param  DMAx DMAx Instance
01026   * @param  Stream This parameter can be one of the following values:
01027   *         @arg @ref LL_DMA_STREAM_0
01028   *         @arg @ref LL_DMA_STREAM_1
01029   *         @arg @ref LL_DMA_STREAM_2
01030   *         @arg @ref LL_DMA_STREAM_3
01031   *         @arg @ref LL_DMA_STREAM_4
01032   *         @arg @ref LL_DMA_STREAM_5
01033   *         @arg @ref LL_DMA_STREAM_6
01034   *         @arg @ref LL_DMA_STREAM_7
01035   * @param  Request This parameter can be one of the following values:
01036   *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
01037   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
01038   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
01039   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
01040   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
01041   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
01042   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
01043   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
01044   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
01045   *         @arg @ref LL_DMAMUX1_REQ_ADC1
01046   *         @arg @ref LL_DMAMUX1_REQ_ADC2
01047   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
01048   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
01049   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
01050   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
01051   *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
01052   *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
01053   *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
01054   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
01055   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
01056   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
01057   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
01058   *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
01059   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
01060   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
01061   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
01062   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
01063   *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
01064   *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
01065   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
01066   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
01067   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
01068   *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
01069   *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
01070   *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
01071   *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
01072   *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
01073   *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
01074   *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
01075   *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
01076   *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
01077   *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
01078   *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
01079   *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
01080   *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
01081   *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
01082   *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
01083   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
01084   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
01085   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
01086   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
01087   *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
01088   *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
01089   *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
01090   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
01091   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
01092   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
01093   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
01094   *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
01095   *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
01096   *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
01097   *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
01098   *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
01099   *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
01100   *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
01101   *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
01102   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
01103   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
01104   *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
01105   *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
01106   *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
01107   *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
01108   *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
01109   *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
01110   *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
01111   *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
01112   *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
01113   *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
01114   *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
01115   *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
01116   *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
01117   *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
01118   *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
01119   *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
01120   *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
01121   *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
01122   *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
01123   *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
01124   *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
01125   *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
01126   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
01127   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
01128   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
01129   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
01130   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
01131   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
01132   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
01133   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
01134   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
01135   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
01136   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
01137   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
01138   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
01139   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
01140   *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
01141   *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
01142   *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
01143   *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
01144   *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
01145   *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
01146   *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
01147   *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
01148   *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
01149   *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
01150   *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
01151   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
01152   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
01153   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
01154   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
01155   * @note   (*) Availability depends on devices.
01156   * @retval None
01157   */
01158 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
01159 {
01160   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
01161 }
01162
01163 /**
01164   * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
01165   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
01166   *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
01167   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
01168   * @param  DMAx DMAx Instance
01169   * @param  Stream This parameter can be one of the following values:
01170   *         @arg @ref LL_DMA_STREAM_0
01171   *         @arg @ref LL_DMA_STREAM_1
01172   *         @arg @ref LL_DMA_STREAM_2
01173   *         @arg @ref LL_DMA_STREAM_3
01174   *         @arg @ref LL_DMA_STREAM_4
01175   *         @arg @ref LL_DMA_STREAM_5
01176   *         @arg @ref LL_DMA_STREAM_6
01177   *         @arg @ref LL_DMA_STREAM_7
01178   * @retval Returned value can be one of the following values:
01179   *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
01180   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
01181   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
01182   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
01183   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
01184   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
01185   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
01186   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
01187   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
01188   *         @arg @ref LL_DMAMUX1_REQ_ADC1
01189   *         @arg @ref LL_DMAMUX1_REQ_ADC2
01190   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
01191   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
01192   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
01193   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
01194   *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
01195   *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
01196   *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
01197   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
01198   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
01199   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
01200   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
01201   *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
01202   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
01203   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
01204   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
01205   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
01206   *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
01207   *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
01208   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
01209   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
01210   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
01211   *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
01212   *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
01213   *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
01214   *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
01215   *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
01216   *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
01217   *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
01218   *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
01219   *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
01220   *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
01221   *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
01222   *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
01223   *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
01224   *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
01225   *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
01226   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
01227   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
01228   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
01229   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
01230   *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
01231   *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
01232   *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
01233   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
01234   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
01235   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
01236   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
01237   *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
01238   *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
01239   *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
01240   *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
01241   *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
01242   *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
01243   *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
01244   *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
01245   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
01246   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
01247   *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
01248   *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
01249   *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
01250   *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
01251   *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
01252   *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
01253   *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
01254   *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
01255   *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
01256   *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
01257   *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
01258   *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
01259   *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
01260   *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
01261   *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
01262   *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
01263   *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
01264   *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
01265   *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
01266   *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
01267   *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
01268   *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
01269   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
01270   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
01271   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
01272   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
01273   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
01274   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
01275   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
01276   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
01277   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
01278   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
01279   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
01280   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
01281   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
01282   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
01283   *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
01284   *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
01285   *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
01286   *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
01287   *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
01288   *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
01289   *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
01290   *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
01291   *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
01292   *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
01293   *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
01294   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
01295   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
01296   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
01297   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
01298   * @note   (*) Availability depends on devices.
01299   */
01300 __STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
01301 {
01302   return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
01303 }
01304
01305 /**
01306   * @brief Set Memory burst transfer configuration.
01307   * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
01308   * @param  DMAx DMAx Instance
01309   * @param  Stream This parameter can be one of the following values:
01310   *         @arg @ref LL_DMA_STREAM_0
01311   *         @arg @ref LL_DMA_STREAM_1
01312   *         @arg @ref LL_DMA_STREAM_2
01313   *         @arg @ref LL_DMA_STREAM_3
01314   *         @arg @ref LL_DMA_STREAM_4
01315   *         @arg @ref LL_DMA_STREAM_5
01316   *         @arg @ref LL_DMA_STREAM_6
01317   *         @arg @ref LL_DMA_STREAM_7
01318   * @param  Mburst This parameter can be one of the following values:
01319   *         @arg @ref LL_DMA_MBURST_SINGLE
01320   *         @arg @ref LL_DMA_MBURST_INC4
01321   *         @arg @ref LL_DMA_MBURST_INC8
01322   *         @arg @ref LL_DMA_MBURST_INC16
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
01326 {
01327   register uint32_t dma_base_addr = (uint32_t)DMAx;
01328
01329   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
01330 }
01331
01332 /**
01333   * @brief Get Memory burst transfer configuration.
01334   * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
01335   * @param  DMAx DMAx Instance
01336   * @param  Stream This parameter can be one of the following values:
01337   *         @arg @ref LL_DMA_STREAM_0
01338   *         @arg @ref LL_DMA_STREAM_1
01339   *         @arg @ref LL_DMA_STREAM_2
01340   *         @arg @ref LL_DMA_STREAM_3
01341   *         @arg @ref LL_DMA_STREAM_4
01342   *         @arg @ref LL_DMA_STREAM_5
01343   *         @arg @ref LL_DMA_STREAM_6
01344   *         @arg @ref LL_DMA_STREAM_7
01345   * @retval Returned value can be one of the following values:
01346   *         @arg @ref LL_DMA_MBURST_SINGLE
01347   *         @arg @ref LL_DMA_MBURST_INC4
01348   *         @arg @ref LL_DMA_MBURST_INC8
01349   *         @arg @ref LL_DMA_MBURST_INC16
01350   */
01351 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
01352 {
01353   register uint32_t dma_base_addr = (uint32_t)DMAx;
01354
01355   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
01356 }
01357
01358 /**
01359   * @brief Set  Peripheral burst transfer configuration.
01360   * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
01361   * @param  DMAx DMAx Instance
01362   * @param  Stream This parameter can be one of the following values:
01363   *         @arg @ref LL_DMA_STREAM_0
01364   *         @arg @ref LL_DMA_STREAM_1
01365   *         @arg @ref LL_DMA_STREAM_2
01366   *         @arg @ref LL_DMA_STREAM_3
01367   *         @arg @ref LL_DMA_STREAM_4
01368   *         @arg @ref LL_DMA_STREAM_5
01369   *         @arg @ref LL_DMA_STREAM_6
01370   *         @arg @ref LL_DMA_STREAM_7
01371   * @param  Pburst This parameter can be one of the following values:
01372   *         @arg @ref LL_DMA_PBURST_SINGLE
01373   *         @arg @ref LL_DMA_PBURST_INC4
01374   *         @arg @ref LL_DMA_PBURST_INC8
01375   *         @arg @ref LL_DMA_PBURST_INC16
01376   * @retval None
01377   */
01378 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
01379 {
01380   register uint32_t dma_base_addr = (uint32_t)DMAx;
01381
01382   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
01383 }
01384
01385 /**
01386   * @brief Get Peripheral burst transfer configuration.
01387   * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
01388   * @param  DMAx DMAx Instance
01389   * @param  Stream This parameter can be one of the following values:
01390   *         @arg @ref LL_DMA_STREAM_0
01391   *         @arg @ref LL_DMA_STREAM_1
01392   *         @arg @ref LL_DMA_STREAM_2
01393   *         @arg @ref LL_DMA_STREAM_3
01394   *         @arg @ref LL_DMA_STREAM_4
01395   *         @arg @ref LL_DMA_STREAM_5
01396   *         @arg @ref LL_DMA_STREAM_6
01397   *         @arg @ref LL_DMA_STREAM_7
01398   * @retval Returned value can be one of the following values:
01399   *         @arg @ref LL_DMA_PBURST_SINGLE
01400   *         @arg @ref LL_DMA_PBURST_INC4
01401   *         @arg @ref LL_DMA_PBURST_INC8
01402   *         @arg @ref LL_DMA_PBURST_INC16
01403   */
01404 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
01405 {
01406   register uint32_t dma_base_addr = (uint32_t)DMAx;
01407
01408   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
01409 }
01410
01411 /**
01412   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
01413   * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem
01414   * @param  DMAx DMAx Instance
01415   * @param  Stream This parameter can be one of the following values:
01416   *         @arg @ref LL_DMA_STREAM_0
01417   *         @arg @ref LL_DMA_STREAM_1
01418   *         @arg @ref LL_DMA_STREAM_2
01419   *         @arg @ref LL_DMA_STREAM_3
01420   *         @arg @ref LL_DMA_STREAM_4
01421   *         @arg @ref LL_DMA_STREAM_5
01422   *         @arg @ref LL_DMA_STREAM_6
01423   *         @arg @ref LL_DMA_STREAM_7
01424   * @param CurrentMemory This parameter can be one of the following values:
01425   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
01426   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
01427   * @retval None
01428   */
01429 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
01430 {
01431   register uint32_t dma_base_addr = (uint32_t)DMAx;
01432
01433   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
01434 }
01435
01436 /**
01437   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
01438   * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem
01439   * @param  DMAx DMAx Instance
01440   * @param  Stream This parameter can be one of the following values:
01441   *         @arg @ref LL_DMA_STREAM_0
01442   *         @arg @ref LL_DMA_STREAM_1
01443   *         @arg @ref LL_DMA_STREAM_2
01444   *         @arg @ref LL_DMA_STREAM_3
01445   *         @arg @ref LL_DMA_STREAM_4
01446   *         @arg @ref LL_DMA_STREAM_5
01447   *         @arg @ref LL_DMA_STREAM_6
01448   *         @arg @ref LL_DMA_STREAM_7
01449   * @retval Returned value can be one of the following values:
01450   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
01451   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
01452   */
01453 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
01454 {
01455   register uint32_t dma_base_addr = (uint32_t)DMAx;
01456
01457   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
01458 }
01459
01460 /**
01461   * @brief Enable the double buffer mode.
01462   * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
01463   * @param  DMAx DMAx Instance
01464   * @param  Stream This parameter can be one of the following values:
01465   *         @arg @ref LL_DMA_STREAM_0
01466   *         @arg @ref LL_DMA_STREAM_1
01467   *         @arg @ref LL_DMA_STREAM_2
01468   *         @arg @ref LL_DMA_STREAM_3
01469   *         @arg @ref LL_DMA_STREAM_4
01470   *         @arg @ref LL_DMA_STREAM_5
01471   *         @arg @ref LL_DMA_STREAM_6
01472   *         @arg @ref LL_DMA_STREAM_7
01473   * @retval None
01474   */
01475 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
01476 {
01477   register uint32_t dma_base_addr = (uint32_t)DMAx;
01478
01479   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
01480 }
01481
01482 /**
01483   * @brief Disable the double buffer mode.
01484   * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode
01485   * @param  DMAx DMAx Instance
01486   * @param  Stream This parameter can be one of the following values:
01487   *         @arg @ref LL_DMA_STREAM_0
01488   *         @arg @ref LL_DMA_STREAM_1
01489   *         @arg @ref LL_DMA_STREAM_2
01490   *         @arg @ref LL_DMA_STREAM_3
01491   *         @arg @ref LL_DMA_STREAM_4
01492   *         @arg @ref LL_DMA_STREAM_5
01493   *         @arg @ref LL_DMA_STREAM_6
01494   *         @arg @ref LL_DMA_STREAM_7
01495   * @retval None
01496   */
01497 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
01498 {
01499   register uint32_t dma_base_addr = (uint32_t)DMAx;
01500
01501   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
01502 }
01503
01504 /**
01505   * @brief Get FIFO status.
01506   * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
01507   * @param  DMAx DMAx Instance
01508   * @param  Stream This parameter can be one of the following values:
01509   *         @arg @ref LL_DMA_STREAM_0
01510   *         @arg @ref LL_DMA_STREAM_1
01511   *         @arg @ref LL_DMA_STREAM_2
01512   *         @arg @ref LL_DMA_STREAM_3
01513   *         @arg @ref LL_DMA_STREAM_4
01514   *         @arg @ref LL_DMA_STREAM_5
01515   *         @arg @ref LL_DMA_STREAM_6
01516   *         @arg @ref LL_DMA_STREAM_7
01517   * @retval Returned value can be one of the following values:
01518   *         @arg @ref LL_DMA_FIFOSTATUS_0_25
01519   *         @arg @ref LL_DMA_FIFOSTATUS_25_50
01520   *         @arg @ref LL_DMA_FIFOSTATUS_50_75
01521   *         @arg @ref LL_DMA_FIFOSTATUS_75_100
01522   *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
01523   *         @arg @ref LL_DMA_FIFOSTATUS_FULL
01524   */
01525 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
01526 {
01527   register uint32_t dma_base_addr = (uint32_t)DMAx;
01528
01529   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
01530 }
01531
01532 /**
01533   * @brief Disable Fifo mode.
01534   * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
01535   * @param  DMAx DMAx Instance
01536   * @param  Stream This parameter can be one of the following values:
01537   *         @arg @ref LL_DMA_STREAM_0
01538   *         @arg @ref LL_DMA_STREAM_1
01539   *         @arg @ref LL_DMA_STREAM_2
01540   *         @arg @ref LL_DMA_STREAM_3
01541   *         @arg @ref LL_DMA_STREAM_4
01542   *         @arg @ref LL_DMA_STREAM_5
01543   *         @arg @ref LL_DMA_STREAM_6
01544   *         @arg @ref LL_DMA_STREAM_7
01545   * @retval None
01546   */
01547 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
01548 {
01549   register uint32_t dma_base_addr = (uint32_t)DMAx;
01550
01551   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
01552 }
01553
01554 /**
01555   * @brief Enable Fifo mode.
01556   * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode
01557   * @param  DMAx DMAx Instance
01558   * @param  Stream This parameter can be one of the following values:
01559   *         @arg @ref LL_DMA_STREAM_0
01560   *         @arg @ref LL_DMA_STREAM_1
01561   *         @arg @ref LL_DMA_STREAM_2
01562   *         @arg @ref LL_DMA_STREAM_3
01563   *         @arg @ref LL_DMA_STREAM_4
01564   *         @arg @ref LL_DMA_STREAM_5
01565   *         @arg @ref LL_DMA_STREAM_6
01566   *         @arg @ref LL_DMA_STREAM_7
01567   * @retval None
01568   */
01569 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
01570 {
01571   register uint32_t dma_base_addr = (uint32_t)DMAx;
01572
01573   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
01574 }
01575
01576 /**
01577   * @brief Select FIFO threshold.
01578   * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
01579   * @param  DMAx DMAx Instance
01580   * @param  Stream This parameter can be one of the following values:
01581   *         @arg @ref LL_DMA_STREAM_0
01582   *         @arg @ref LL_DMA_STREAM_1
01583   *         @arg @ref LL_DMA_STREAM_2
01584   *         @arg @ref LL_DMA_STREAM_3
01585   *         @arg @ref LL_DMA_STREAM_4
01586   *         @arg @ref LL_DMA_STREAM_5
01587   *         @arg @ref LL_DMA_STREAM_6
01588   *         @arg @ref LL_DMA_STREAM_7
01589   * @param  Threshold This parameter can be one of the following values:
01590   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
01591   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
01592   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
01593   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
01594   * @retval None
01595   */
01596 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
01597 {
01598   register uint32_t dma_base_addr = (uint32_t)DMAx;
01599
01600   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
01601 }
01602
01603 /**
01604   * @brief Get FIFO threshold.
01605   * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
01606   * @param  DMAx DMAx Instance
01607   * @param  Stream This parameter can be one of the following values:
01608   *         @arg @ref LL_DMA_STREAM_0
01609   *         @arg @ref LL_DMA_STREAM_1
01610   *         @arg @ref LL_DMA_STREAM_2
01611   *         @arg @ref LL_DMA_STREAM_3
01612   *         @arg @ref LL_DMA_STREAM_4
01613   *         @arg @ref LL_DMA_STREAM_5
01614   *         @arg @ref LL_DMA_STREAM_6
01615   *         @arg @ref LL_DMA_STREAM_7
01616   * @retval Returned value can be one of the following values:
01617   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
01618   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
01619   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
01620   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
01621   */
01622 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
01623 {
01624   register uint32_t dma_base_addr = (uint32_t)DMAx;
01625
01626   return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
01627 }
01628
01629 /**
01630   * @brief Configure the FIFO .
01631   * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
01632   *         FCR         DMDIS        LL_DMA_ConfigFifo
01633   * @param  DMAx DMAx Instance
01634   * @param  Stream This parameter can be one of the following values:
01635   *         @arg @ref LL_DMA_STREAM_0
01636   *         @arg @ref LL_DMA_STREAM_1
01637   *         @arg @ref LL_DMA_STREAM_2
01638   *         @arg @ref LL_DMA_STREAM_3
01639   *         @arg @ref LL_DMA_STREAM_4
01640   *         @arg @ref LL_DMA_STREAM_5
01641   *         @arg @ref LL_DMA_STREAM_6
01642   *         @arg @ref LL_DMA_STREAM_7
01643   * @param  FifoMode This parameter can be one of the following values:
01644   *         @arg @ref LL_DMA_FIFOMODE_ENABLE
01645   *         @arg @ref LL_DMA_FIFOMODE_DISABLE
01646   * @param  FifoThreshold This parameter can be one of the following values:
01647   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
01648   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
01649   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
01650   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
01651   * @retval None
01652   */
01653 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
01654 {
01655   register uint32_t dma_base_addr = (uint32_t)DMAx;
01656
01657   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
01658 }
01659
01660 /**
01661   * @brief Configure the Source and Destination addresses.
01662   * @note   This API must not be called when the DMA stream is enabled.
01663   * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n
01664   *         PAR         PA          LL_DMA_ConfigAddresses
01665   * @param  DMAx DMAx Instance
01666   * @param  Stream This parameter can be one of the following values:
01667   *         @arg @ref LL_DMA_STREAM_0
01668   *         @arg @ref LL_DMA_STREAM_1
01669   *         @arg @ref LL_DMA_STREAM_2
01670   *         @arg @ref LL_DMA_STREAM_3
01671   *         @arg @ref LL_DMA_STREAM_4
01672   *         @arg @ref LL_DMA_STREAM_5
01673   *         @arg @ref LL_DMA_STREAM_6
01674   *         @arg @ref LL_DMA_STREAM_7
01675   * @param  SrcAddress Between 0 to 0xFFFFFFFF
01676   * @param  DstAddress Between 0 to 0xFFFFFFFF
01677   * @param  Direction This parameter can be one of the following values:
01678   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
01679   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
01680   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
01681   * @retval None
01682   */
01683 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
01684 {
01685   register uint32_t dma_base_addr = (uint32_t)DMAx;
01686
01687   /* Direction Memory to Periph */
01688   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
01689   {
01690     WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
01691     WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
01692   }
01693   /* Direction Periph to Memory and Memory to Memory */
01694   else
01695   {
01696     WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
01697     WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
01698   }
01699 }
01700
01701 /**
01702   * @brief  Set the Memory address.
01703   * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
01704   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01705   * @note   This API must not be called when the DMA stream is enabled.
01706   * @param  DMAx DMAx Instance
01707   * @param  Stream This parameter can be one of the following values:
01708   *         @arg @ref LL_DMA_STREAM_0
01709   *         @arg @ref LL_DMA_STREAM_1
01710   *         @arg @ref LL_DMA_STREAM_2
01711   *         @arg @ref LL_DMA_STREAM_3
01712   *         @arg @ref LL_DMA_STREAM_4
01713   *         @arg @ref LL_DMA_STREAM_5
01714   *         @arg @ref LL_DMA_STREAM_6
01715   *         @arg @ref LL_DMA_STREAM_7
01716   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
01720 {
01721   register uint32_t dma_base_addr = (uint32_t)DMAx;
01722
01723   WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
01724 }
01725
01726 /**
01727   * @brief  Set the Peripheral address.
01728   * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
01729   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01730   * @note   This API must not be called when the DMA stream is enabled.
01731   * @param  DMAx DMAx Instance
01732   * @param  Stream This parameter can be one of the following values:
01733   *         @arg @ref LL_DMA_STREAM_0
01734   *         @arg @ref LL_DMA_STREAM_1
01735   *         @arg @ref LL_DMA_STREAM_2
01736   *         @arg @ref LL_DMA_STREAM_3
01737   *         @arg @ref LL_DMA_STREAM_4
01738   *         @arg @ref LL_DMA_STREAM_5
01739   *         @arg @ref LL_DMA_STREAM_6
01740   *         @arg @ref LL_DMA_STREAM_7
01741   * @param  PeriphAddress Between 0 to 0xFFFFFFFF
01742   * @retval None
01743   */
01744 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
01745 {
01746   register uint32_t dma_base_addr = (uint32_t)DMAx;
01747
01748   WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
01749 }
01750
01751 /**
01752   * @brief  Get the Memory address.
01753   * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
01754   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01755   * @param  DMAx DMAx Instance
01756   * @param  Stream This parameter can be one of the following values:
01757   *         @arg @ref LL_DMA_STREAM_0
01758   *         @arg @ref LL_DMA_STREAM_1
01759   *         @arg @ref LL_DMA_STREAM_2
01760   *         @arg @ref LL_DMA_STREAM_3
01761   *         @arg @ref LL_DMA_STREAM_4
01762   *         @arg @ref LL_DMA_STREAM_5
01763   *         @arg @ref LL_DMA_STREAM_6
01764   *         @arg @ref LL_DMA_STREAM_7
01765   * @retval Between 0 to 0xFFFFFFFF
01766   */
01767 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
01768 {
01769   register uint32_t dma_base_addr = (uint32_t)DMAx;
01770
01771   return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
01772 }
01773
01774 /**
01775   * @brief  Get the Peripheral address.
01776   * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
01777   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01778   * @param  DMAx DMAx Instance
01779   * @param  Stream This parameter can be one of the following values:
01780   *         @arg @ref LL_DMA_STREAM_0
01781   *         @arg @ref LL_DMA_STREAM_1
01782   *         @arg @ref LL_DMA_STREAM_2
01783   *         @arg @ref LL_DMA_STREAM_3
01784   *         @arg @ref LL_DMA_STREAM_4
01785   *         @arg @ref LL_DMA_STREAM_5
01786   *         @arg @ref LL_DMA_STREAM_6
01787   *         @arg @ref LL_DMA_STREAM_7
01788   * @retval Between 0 to 0xFFFFFFFF
01789   */
01790 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
01791 {
01792   register uint32_t dma_base_addr = (uint32_t)DMAx;
01793
01794   return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
01795 }
01796
01797 /**
01798   * @brief  Set the Memory to Memory Source address.
01799   * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
01800   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01801   * @note   This API must not be called when the DMA stream is enabled.
01802   * @param  DMAx DMAx Instance
01803   * @param  Stream This parameter can be one of the following values:
01804   *         @arg @ref LL_DMA_STREAM_0
01805   *         @arg @ref LL_DMA_STREAM_1
01806   *         @arg @ref LL_DMA_STREAM_2
01807   *         @arg @ref LL_DMA_STREAM_3
01808   *         @arg @ref LL_DMA_STREAM_4
01809   *         @arg @ref LL_DMA_STREAM_5
01810   *         @arg @ref LL_DMA_STREAM_6
01811   *         @arg @ref LL_DMA_STREAM_7
01812   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
01813   * @retval None
01814   */
01815 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
01816 {
01817   register uint32_t dma_base_addr = (uint32_t)DMAx;
01818
01819   WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
01820 }
01821
01822 /**
01823   * @brief  Set the Memory to Memory Destination address.
01824   * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
01825   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01826   * @note   This API must not be called when the DMA stream is enabled.
01827   * @param  DMAx DMAx Instance
01828   * @param  Stream This parameter can be one of the following values:
01829   *         @arg @ref LL_DMA_STREAM_0
01830   *         @arg @ref LL_DMA_STREAM_1
01831   *         @arg @ref LL_DMA_STREAM_2
01832   *         @arg @ref LL_DMA_STREAM_3
01833   *         @arg @ref LL_DMA_STREAM_4
01834   *         @arg @ref LL_DMA_STREAM_5
01835   *         @arg @ref LL_DMA_STREAM_6
01836   *         @arg @ref LL_DMA_STREAM_7
01837   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
01841 {
01842   register uint32_t dma_base_addr = (uint32_t)DMAx;
01843
01844   WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
01845 }
01846
01847 /**
01848   * @brief  Get the Memory to Memory Source address.
01849   * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
01850   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01851   * @param  DMAx DMAx Instance
01852   * @param  Stream This parameter can be one of the following values:
01853   *         @arg @ref LL_DMA_STREAM_0
01854   *         @arg @ref LL_DMA_STREAM_1
01855   *         @arg @ref LL_DMA_STREAM_2
01856   *         @arg @ref LL_DMA_STREAM_3
01857   *         @arg @ref LL_DMA_STREAM_4
01858   *         @arg @ref LL_DMA_STREAM_5
01859   *         @arg @ref LL_DMA_STREAM_6
01860   *         @arg @ref LL_DMA_STREAM_7
01861   * @retval Between 0 to 0xFFFFFFFF
01862   */
01863 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
01864 {
01865   register uint32_t dma_base_addr = (uint32_t)DMAx;
01866
01867   return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
01868 }
01869
01870 /**
01871   * @brief  Get the Memory to Memory Destination address.
01872   * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
01873   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01874   * @param  DMAx DMAx Instance
01875   * @param  Stream This parameter can be one of the following values:
01876   *         @arg @ref LL_DMA_STREAM_0
01877   *         @arg @ref LL_DMA_STREAM_1
01878   *         @arg @ref LL_DMA_STREAM_2
01879   *         @arg @ref LL_DMA_STREAM_3
01880   *         @arg @ref LL_DMA_STREAM_4
01881   *         @arg @ref LL_DMA_STREAM_5
01882   *         @arg @ref LL_DMA_STREAM_6
01883   *         @arg @ref LL_DMA_STREAM_7
01884   * @retval Between 0 to 0xFFFFFFFF
01885   */
01886 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
01887 {
01888   register uint32_t dma_base_addr = (uint32_t)DMAx;
01889
01890   return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
01891 }
01892
01893 /**
01894   * @brief Set Memory 1 address (used in case of Double buffer mode).
01895   * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
01896   * @param  DMAx DMAx Instance
01897   * @param  Stream This parameter can be one of the following values:
01898   *         @arg @ref LL_DMA_STREAM_0
01899   *         @arg @ref LL_DMA_STREAM_1
01900   *         @arg @ref LL_DMA_STREAM_2
01901   *         @arg @ref LL_DMA_STREAM_3
01902   *         @arg @ref LL_DMA_STREAM_4
01903   *         @arg @ref LL_DMA_STREAM_5
01904   *         @arg @ref LL_DMA_STREAM_6
01905   *         @arg @ref LL_DMA_STREAM_7
01906   * @param  Address Between 0 to 0xFFFFFFFF
01907   * @retval None
01908   */
01909 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
01910 {
01911   register uint32_t dma_base_addr = (uint32_t)DMAx;
01912
01913   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
01914 }
01915
01916 /**
01917   * @brief Get Memory 1 address (used in case of Double buffer mode).
01918   * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
01919   * @param  DMAx DMAx Instance
01920   * @param  Stream This parameter can be one of the following values:
01921   *         @arg @ref LL_DMA_STREAM_0
01922   *         @arg @ref LL_DMA_STREAM_1
01923   *         @arg @ref LL_DMA_STREAM_2
01924   *         @arg @ref LL_DMA_STREAM_3
01925   *         @arg @ref LL_DMA_STREAM_4
01926   *         @arg @ref LL_DMA_STREAM_5
01927   *         @arg @ref LL_DMA_STREAM_6
01928   *         @arg @ref LL_DMA_STREAM_7
01929   * @retval Between 0 to 0xFFFFFFFF
01930   */
01931 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
01932 {
01933   register uint32_t dma_base_addr = (uint32_t)DMAx;
01934
01935   return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
01936 }
01937
01938 /**
01939   * @}
01940   */
01941
01942 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01943   * @{
01944   */
01945
01946 /**
01947   * @brief Get Stream 0 half transfer flag.
01948   * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
01949   * @param  DMAx DMAx Instance
01950   * @retval State of bit (1 or 0).
01951   */
01952 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
01953 {
01954   return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
01955 }
01956
01957 /**
01958   * @brief Get Stream 1 half transfer flag.
01959   * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
01960   * @param  DMAx DMAx Instance
01961   * @retval State of bit (1 or 0).
01962   */
01963 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01964 {
01965   return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
01966 }
01967
01968 /**
01969   * @brief Get Stream 2 half transfer flag.
01970   * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
01971   * @param  DMAx DMAx Instance
01972   * @retval State of bit (1 or 0).
01973   */
01974 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01975 {
01976   return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
01977 }
01978
01979 /**
01980   * @brief Get Stream 3 half transfer flag.
01981   * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
01982   * @param  DMAx DMAx Instance
01983   * @retval State of bit (1 or 0).
01984   */
01985 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01986 {
01987   return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
01988 }
01989
01990 /**
01991   * @brief Get Stream 4 half transfer flag.
01992   * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
01993   * @param  DMAx DMAx Instance
01994   * @retval State of bit (1 or 0).
01995   */
01996 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01997 {
01998   return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
01999 }
02000
02001 /**
02002   * @brief Get Stream 5 half transfer flag.
02003   * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
02004   * @param  DMAx DMAx Instance
02005   * @retval State of bit (1 or 0).
02006   */
02007 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
02008 {
02009   return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
02010 }
02011
02012 /**
02013   * @brief Get Stream 6 half transfer flag.
02014   * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
02015   * @param  DMAx DMAx Instance
02016   * @retval State of bit (1 or 0).
02017   */
02018 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
02019 {
02020   return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
02021 }
02022
02023 /**
02024   * @brief Get Stream 7 half transfer flag.
02025   * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
02026   * @param  DMAx DMAx Instance
02027   * @retval State of bit (1 or 0).
02028   */
02029 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
02030 {
02031   return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
02032 }
02033
02034 /**
02035   * @brief Get Stream 0 transfer complete flag.
02036   * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
02037   * @param  DMAx DMAx Instance
02038   * @retval State of bit (1 or 0).
02039   */
02040 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
02041 {
02042   return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
02043 }
02044
02045 /**
02046   * @brief Get Stream 1 transfer complete flag.
02047   * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
02048   * @param  DMAx DMAx Instance
02049   * @retval State of bit (1 or 0).
02050   */
02051 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
02052 {
02053   return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
02054 }
02055
02056 /**
02057   * @brief Get Stream 2 transfer complete flag.
02058   * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
02059   * @param  DMAx DMAx Instance
02060   * @retval State of bit (1 or 0).
02061   */
02062 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
02063 {
02064   return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
02065 }
02066
02067 /**
02068   * @brief Get Stream 3 transfer complete flag.
02069   * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
02070   * @param  DMAx DMAx Instance
02071   * @retval State of bit (1 or 0).
02072   */
02073 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
02074 {
02075   return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
02076 }
02077
02078 /**
02079   * @brief Get Stream 4 transfer complete flag.
02080   * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
02081   * @param  DMAx DMAx Instance
02082   * @retval State of bit (1 or 0).
02083   */
02084 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
02085 {
02086   return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
02087 }
02088
02089 /**
02090   * @brief Get Stream 5 transfer complete flag.
02091   * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
02092   * @param  DMAx DMAx Instance
02093   * @retval State of bit (1 or 0).
02094   */
02095 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
02096 {
02097   return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
02098 }
02099
02100 /**
02101   * @brief Get Stream 6 transfer complete flag.
02102   * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
02103   * @param  DMAx DMAx Instance
02104   * @retval State of bit (1 or 0).
02105   */
02106 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
02107 {
02108   return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
02109 }
02110
02111 /**
02112   * @brief Get Stream 7 transfer complete flag.
02113   * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
02114   * @param  DMAx DMAx Instance
02115   * @retval State of bit (1 or 0).
02116   */
02117 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
02118 {
02119   return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
02120 }
02121
02122 /**
02123   * @brief Get Stream 0 transfer error flag.
02124   * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
02125   * @param  DMAx DMAx Instance
02126   * @retval State of bit (1 or 0).
02127   */
02128 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
02129 {
02130   return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
02131 }
02132
02133 /**
02134   * @brief Get Stream 1 transfer error flag.
02135   * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
02136   * @param  DMAx DMAx Instance
02137   * @retval State of bit (1 or 0).
02138   */
02139 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
02140 {
02141   return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
02142 }
02143
02144 /**
02145   * @brief Get Stream 2 transfer error flag.
02146   * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
02147   * @param  DMAx DMAx Instance
02148   * @retval State of bit (1 or 0).
02149   */
02150 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
02151 {
02152   return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
02153 }
02154
02155 /**
02156   * @brief Get Stream 3 transfer error flag.
02157   * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
02158   * @param  DMAx DMAx Instance
02159   * @retval State of bit (1 or 0).
02160   */
02161 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
02162 {
02163   return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
02164 }
02165
02166 /**
02167   * @brief Get Stream 4 transfer error flag.
02168   * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
02169   * @param  DMAx DMAx Instance
02170   * @retval State of bit (1 or 0).
02171   */
02172 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
02173 {
02174   return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
02175 }
02176
02177 /**
02178   * @brief Get Stream 5 transfer error flag.
02179   * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
02180   * @param  DMAx DMAx Instance
02181   * @retval State of bit (1 or 0).
02182   */
02183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
02184 {
02185   return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
02186 }
02187
02188 /**
02189   * @brief Get Stream 6 transfer error flag.
02190   * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
02191   * @param  DMAx DMAx Instance
02192   * @retval State of bit (1 or 0).
02193   */
02194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
02195 {
02196   return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
02197 }
02198
02199 /**
02200   * @brief Get Stream 7 transfer error flag.
02201   * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
02202   * @param  DMAx DMAx Instance
02203   * @retval State of bit (1 or 0).
02204   */
02205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
02206 {
02207   return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
02208 }
02209
02210 /**
02211   * @brief Get Stream 0 direct mode error flag.
02212   * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
02213   * @param  DMAx DMAx Instance
02214   * @retval State of bit (1 or 0).
02215   */
02216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
02217 {
02218   return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
02219 }
02220
02221 /**
02222   * @brief Get Stream 1 direct mode error flag.
02223   * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
02224   * @param  DMAx DMAx Instance
02225   * @retval State of bit (1 or 0).
02226   */
02227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
02228 {
02229   return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
02230 }
02231
02232 /**
02233   * @brief Get Stream 2 direct mode error flag.
02234   * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
02235   * @param  DMAx DMAx Instance
02236   * @retval State of bit (1 or 0).
02237   */
02238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
02239 {
02240   return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
02241 }
02242
02243 /**
02244   * @brief Get Stream 3 direct mode error flag.
02245   * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
02246   * @param  DMAx DMAx Instance
02247   * @retval State of bit (1 or 0).
02248   */
02249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
02250 {
02251   return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
02252 }
02253
02254 /**
02255   * @brief Get Stream 4 direct mode error flag.
02256   * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
02257   * @param  DMAx DMAx Instance
02258   * @retval State of bit (1 or 0).
02259   */
02260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
02261 {
02262   return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
02263 }
02264
02265 /**
02266   * @brief Get Stream 5 direct mode error flag.
02267   * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
02268   * @param  DMAx DMAx Instance
02269   * @retval State of bit (1 or 0).
02270   */
02271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
02272 {
02273   return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
02274 }
02275
02276 /**
02277   * @brief Get Stream 6 direct mode error flag.
02278   * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
02279   * @param  DMAx DMAx Instance
02280   * @retval State of bit (1 or 0).
02281   */
02282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
02283 {
02284   return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
02285 }
02286
02287 /**
02288   * @brief Get Stream 7 direct mode error flag.
02289   * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
02290   * @param  DMAx DMAx Instance
02291   * @retval State of bit (1 or 0).
02292   */
02293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
02294 {
02295   return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
02296 }
02297
02298 /**
02299   * @brief Get Stream 0 FIFO error flag.
02300   * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
02301   * @param  DMAx DMAx Instance
02302   * @retval State of bit (1 or 0).
02303   */
02304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
02305 {
02306   return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
02307 }
02308
02309 /**
02310   * @brief Get Stream 1 FIFO error flag.
02311   * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
02312   * @param  DMAx DMAx Instance
02313   * @retval State of bit (1 or 0).
02314   */
02315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
02316 {
02317   return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
02318 }
02319
02320 /**
02321   * @brief Get Stream 2 FIFO error flag.
02322   * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
02323   * @param  DMAx DMAx Instance
02324   * @retval State of bit (1 or 0).
02325   */
02326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
02327 {
02328   return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
02329 }
02330
02331 /**
02332   * @brief Get Stream 3 FIFO error flag.
02333   * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
02334   * @param  DMAx DMAx Instance
02335   * @retval State of bit (1 or 0).
02336   */
02337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
02338 {
02339   return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
02340 }
02341
02342 /**
02343   * @brief Get Stream 4 FIFO error flag.
02344   * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
02345   * @param  DMAx DMAx Instance
02346   * @retval State of bit (1 or 0).
02347   */
02348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
02349 {
02350   return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
02351 }
02352
02353 /**
02354   * @brief Get Stream 5 FIFO error flag.
02355   * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
02356   * @param  DMAx DMAx Instance
02357   * @retval State of bit (1 or 0).
02358   */
02359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
02360 {
02361   return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
02362 }
02363
02364 /**
02365   * @brief Get Stream 6 FIFO error flag.
02366   * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
02367   * @param  DMAx DMAx Instance
02368   * @retval State of bit (1 or 0).
02369   */
02370 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
02371 {
02372   return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
02373 }
02374
02375 /**
02376   * @brief Get Stream 7 FIFO error flag.
02377   * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
02378   * @param  DMAx DMAx Instance
02379   * @retval State of bit (1 or 0).
02380   */
02381 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
02382 {
02383   return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
02384 }
02385
02386 /**
02387   * @brief Clear Stream 0 half transfer flag.
02388   * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
02389   * @param  DMAx DMAx Instance
02390   * @retval None
02391   */
02392 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
02393 {
02394   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
02395 }
02396
02397 /**
02398   * @brief Clear Stream 1 half transfer flag.
02399   * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
02400   * @param  DMAx DMAx Instance
02401   * @retval None
02402   */
02403 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
02404 {
02405   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
02406 }
02407
02408 /**
02409   * @brief Clear Stream 2 half transfer flag.
02410   * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
02411   * @param  DMAx DMAx Instance
02412   * @retval None
02413   */
02414 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
02415 {
02416   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
02417 }
02418
02419 /**
02420   * @brief Clear Stream 3 half transfer flag.
02421   * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
02422   * @param  DMAx DMAx Instance
02423   * @retval None
02424   */
02425 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
02426 {
02427   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
02428 }
02429
02430 /**
02431   * @brief Clear Stream 4 half transfer flag.
02432   * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
02433   * @param  DMAx DMAx Instance
02434   * @retval None
02435   */
02436 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
02437 {
02438   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
02439 }
02440
02441 /**
02442   * @brief Clear Stream 5 half transfer flag.
02443   * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
02444   * @param  DMAx DMAx Instance
02445   * @retval None
02446   */
02447 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
02448 {
02449   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
02450 }
02451
02452 /**
02453   * @brief Clear Stream 6 half transfer flag.
02454   * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
02455   * @param  DMAx DMAx Instance
02456   * @retval None
02457   */
02458 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
02459 {
02460   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
02461 }
02462
02463 /**
02464   * @brief Clear Stream 7 half transfer flag.
02465   * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
02466   * @param  DMAx DMAx Instance
02467   * @retval None
02468   */
02469 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
02470 {
02471   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
02472 }
02473
02474 /**
02475   * @brief Clear Stream 0 transfer complete flag.
02476   * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
02477   * @param  DMAx DMAx Instance
02478   * @retval None
02479   */
02480 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
02481 {
02482   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
02483 }
02484
02485 /**
02486   * @brief Clear Stream 1 transfer complete flag.
02487   * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
02488   * @param  DMAx DMAx Instance
02489   * @retval None
02490   */
02491 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
02492 {
02493   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
02494 }
02495
02496 /**
02497   * @brief Clear Stream 2 transfer complete flag.
02498   * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
02499   * @param  DMAx DMAx Instance
02500   * @retval None
02501   */
02502 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
02503 {
02504   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
02505 }
02506
02507 /**
02508   * @brief Clear Stream 3 transfer complete flag.
02509   * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
02510   * @param  DMAx DMAx Instance
02511   * @retval None
02512   */
02513 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
02514 {
02515   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
02516 }
02517
02518 /**
02519   * @brief Clear Stream 4 transfer complete flag.
02520   * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
02521   * @param  DMAx DMAx Instance
02522   * @retval None
02523   */
02524 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
02525 {
02526   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
02527 }
02528
02529 /**
02530   * @brief Clear Stream 5 transfer complete flag.
02531   * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
02532   * @param  DMAx DMAx Instance
02533   * @retval None
02534   */
02535 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
02536 {
02537   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
02538 }
02539
02540 /**
02541   * @brief Clear Stream 6 transfer complete flag.
02542   * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
02543   * @param  DMAx DMAx Instance
02544   * @retval None
02545   */
02546 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
02547 {
02548   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
02549 }
02550
02551 /**
02552   * @brief Clear Stream 7 transfer complete flag.
02553   * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
02554   * @param  DMAx DMAx Instance
02555   * @retval None
02556   */
02557 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
02558 {
02559   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
02560 }
02561
02562 /**
02563   * @brief Clear Stream 0 transfer error flag.
02564   * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
02565   * @param  DMAx DMAx Instance
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
02569 {
02570   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
02571 }
02572
02573 /**
02574   * @brief Clear Stream 1 transfer error flag.
02575   * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
02576   * @param  DMAx DMAx Instance
02577   * @retval None
02578   */
02579 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
02580 {
02581   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
02582 }
02583
02584 /**
02585   * @brief Clear Stream 2 transfer error flag.
02586   * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
02587   * @param  DMAx DMAx Instance
02588   * @retval None
02589   */
02590 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
02591 {
02592   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
02593 }
02594
02595 /**
02596   * @brief Clear Stream 3 transfer error flag.
02597   * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
02598   * @param  DMAx DMAx Instance
02599   * @retval None
02600   */
02601 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
02602 {
02603   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
02604 }
02605
02606 /**
02607   * @brief Clear Stream 4 transfer error flag.
02608   * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
02609   * @param  DMAx DMAx Instance
02610   * @retval None
02611   */
02612 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
02613 {
02614   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
02615 }
02616
02617 /**
02618   * @brief Clear Stream 5 transfer error flag.
02619   * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
02620   * @param  DMAx DMAx Instance
02621   * @retval None
02622   */
02623 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
02624 {
02625   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
02626 }
02627
02628 /**
02629   * @brief Clear Stream 6 transfer error flag.
02630   * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
02631   * @param  DMAx DMAx Instance
02632   * @retval None
02633   */
02634 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
02635 {
02636   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
02637 }
02638
02639 /**
02640   * @brief Clear Stream 7 transfer error flag.
02641   * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
02642   * @param  DMAx DMAx Instance
02643   * @retval None
02644   */
02645 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
02646 {
02647   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
02648 }
02649
02650 /**
02651   * @brief Clear Stream 0 direct mode error flag.
02652   * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
02653   * @param  DMAx DMAx Instance
02654   * @retval None
02655   */
02656 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
02657 {
02658   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
02659 }
02660
02661 /**
02662   * @brief Clear Stream 1 direct mode error flag.
02663   * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
02664   * @param  DMAx DMAx Instance
02665   * @retval None
02666   */
02667 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
02668 {
02669   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
02670 }
02671
02672 /**
02673   * @brief Clear Stream 2 direct mode error flag.
02674   * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
02675   * @param  DMAx DMAx Instance
02676   * @retval None
02677   */
02678 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
02679 {
02680   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
02681 }
02682
02683 /**
02684   * @brief Clear Stream 3 direct mode error flag.
02685   * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
02686   * @param  DMAx DMAx Instance
02687   * @retval None
02688   */
02689 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
02690 {
02691   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
02692 }
02693
02694 /**
02695   * @brief Clear Stream 4 direct mode error flag.
02696   * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
02697   * @param  DMAx DMAx Instance
02698   * @retval None
02699   */
02700 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
02701 {
02702   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
02703 }
02704
02705 /**
02706   * @brief Clear Stream 5 direct mode error flag.
02707   * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
02708   * @param  DMAx DMAx Instance
02709   * @retval None
02710   */
02711 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
02712 {
02713   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
02714 }
02715
02716 /**
02717   * @brief Clear Stream 6 direct mode error flag.
02718   * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
02719   * @param  DMAx DMAx Instance
02720   * @retval None
02721   */
02722 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
02723 {
02724   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
02725 }
02726
02727 /**
02728   * @brief Clear Stream 7 direct mode error flag.
02729   * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
02730   * @param  DMAx DMAx Instance
02731   * @retval None
02732   */
02733 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
02734 {
02735   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
02736 }
02737
02738 /**
02739   * @brief Clear Stream 0 FIFO error flag.
02740   * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
02741   * @param  DMAx DMAx Instance
02742   * @retval None
02743   */
02744 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
02745 {
02746   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
02747 }
02748
02749 /**
02750   * @brief Clear Stream 1 FIFO error flag.
02751   * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
02752   * @param  DMAx DMAx Instance
02753   * @retval None
02754   */
02755 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
02756 {
02757   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
02758 }
02759
02760 /**
02761   * @brief Clear Stream 2 FIFO error flag.
02762   * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
02763   * @param  DMAx DMAx Instance
02764   * @retval None
02765   */
02766 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
02767 {
02768   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
02769 }
02770
02771 /**
02772   * @brief Clear Stream 3 FIFO error flag.
02773   * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
02774   * @param  DMAx DMAx Instance
02775   * @retval None
02776   */
02777 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
02778 {
02779   WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
02780 }
02781
02782 /**
02783   * @brief Clear Stream 4 FIFO error flag.
02784   * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
02785   * @param  DMAx DMAx Instance
02786   * @retval None
02787   */
02788 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
02789 {
02790   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
02791 }
02792
02793 /**
02794   * @brief Clear Stream 5 FIFO error flag.
02795   * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
02796   * @param  DMAx DMAx Instance
02797   * @retval None
02798   */
02799 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
02800 {
02801   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
02802 }
02803
02804 /**
02805   * @brief Clear Stream 6 FIFO error flag.
02806   * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
02807   * @param  DMAx DMAx Instance
02808   * @retval None
02809   */
02810 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
02811 {
02812   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
02813 }
02814
02815 /**
02816   * @brief Clear Stream 7 FIFO error flag.
02817   * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
02818   * @param  DMAx DMAx Instance
02819   * @retval None
02820   */
02821 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
02822 {
02823   WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
02824 }
02825
02826 /**
02827   * @}
02828   */
02829
02830 /** @defgroup DMA_LL_EF_IT_Management IT_Management
02831   * @{
02832   */
02833
02834 /**
02835   * @brief Enable Half transfer interrupt.
02836   * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
02837   * @param  DMAx DMAx Instance
02838   * @param  Stream This parameter can be one of the following values:
02839   *         @arg @ref LL_DMA_STREAM_0
02840   *         @arg @ref LL_DMA_STREAM_1
02841   *         @arg @ref LL_DMA_STREAM_2
02842   *         @arg @ref LL_DMA_STREAM_3
02843   *         @arg @ref LL_DMA_STREAM_4
02844   *         @arg @ref LL_DMA_STREAM_5
02845   *         @arg @ref LL_DMA_STREAM_6
02846   *         @arg @ref LL_DMA_STREAM_7
02847   * @retval None
02848   */
02849 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
02850 {
02851   register uint32_t dma_base_addr = (uint32_t)DMAx;
02852
02853   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
02854 }
02855
02856 /**
02857   * @brief Enable Transfer error interrupt.
02858   * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
02859   * @param  DMAx DMAx Instance
02860   * @param  Stream This parameter can be one of the following values:
02861   *         @arg @ref LL_DMA_STREAM_0
02862   *         @arg @ref LL_DMA_STREAM_1
02863   *         @arg @ref LL_DMA_STREAM_2
02864   *         @arg @ref LL_DMA_STREAM_3
02865   *         @arg @ref LL_DMA_STREAM_4
02866   *         @arg @ref LL_DMA_STREAM_5
02867   *         @arg @ref LL_DMA_STREAM_6
02868   *         @arg @ref LL_DMA_STREAM_7
02869   * @retval None
02870   */
02871 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
02872 {
02873   register uint32_t dma_base_addr = (uint32_t)DMAx;
02874
02875   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
02876 }
02877
02878 /**
02879   * @brief Enable Transfer complete interrupt.
02880   * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
02881   * @param  DMAx DMAx Instance
02882   * @param  Stream This parameter can be one of the following values:
02883   *         @arg @ref LL_DMA_STREAM_0
02884   *         @arg @ref LL_DMA_STREAM_1
02885   *         @arg @ref LL_DMA_STREAM_2
02886   *         @arg @ref LL_DMA_STREAM_3
02887   *         @arg @ref LL_DMA_STREAM_4
02888   *         @arg @ref LL_DMA_STREAM_5
02889   *         @arg @ref LL_DMA_STREAM_6
02890   *         @arg @ref LL_DMA_STREAM_7
02891   * @retval None
02892   */
02893 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
02894 {
02895   register uint32_t dma_base_addr = (uint32_t)DMAx;
02896
02897   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
02898 }
02899
02900 /**
02901   * @brief Enable Direct mode error interrupt.
02902   * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
02903   * @param  DMAx DMAx Instance
02904   * @param  Stream This parameter can be one of the following values:
02905   *         @arg @ref LL_DMA_STREAM_0
02906   *         @arg @ref LL_DMA_STREAM_1
02907   *         @arg @ref LL_DMA_STREAM_2
02908   *         @arg @ref LL_DMA_STREAM_3
02909   *         @arg @ref LL_DMA_STREAM_4
02910   *         @arg @ref LL_DMA_STREAM_5
02911   *         @arg @ref LL_DMA_STREAM_6
02912   *         @arg @ref LL_DMA_STREAM_7
02913   * @retval None
02914   */
02915 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
02916 {
02917   register uint32_t dma_base_addr = (uint32_t)DMAx;
02918
02919   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
02920 }
02921
02922 /**
02923   * @brief Enable FIFO error interrupt.
02924   * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
02925   * @param  DMAx DMAx Instance
02926   * @param  Stream This parameter can be one of the following values:
02927   *         @arg @ref LL_DMA_STREAM_0
02928   *         @arg @ref LL_DMA_STREAM_1
02929   *         @arg @ref LL_DMA_STREAM_2
02930   *         @arg @ref LL_DMA_STREAM_3
02931   *         @arg @ref LL_DMA_STREAM_4
02932   *         @arg @ref LL_DMA_STREAM_5
02933   *         @arg @ref LL_DMA_STREAM_6
02934   *         @arg @ref LL_DMA_STREAM_7
02935   * @retval None
02936   */
02937 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
02938 {
02939   register uint32_t dma_base_addr = (uint32_t)DMAx;
02940
02941   SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
02942 }
02943
02944 /**
02945   * @brief Disable Half transfer interrupt.
02946   * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
02947   * @param  DMAx DMAx Instance
02948   * @param  Stream This parameter can be one of the following values:
02949   *         @arg @ref LL_DMA_STREAM_0
02950   *         @arg @ref LL_DMA_STREAM_1
02951   *         @arg @ref LL_DMA_STREAM_2
02952   *         @arg @ref LL_DMA_STREAM_3
02953   *         @arg @ref LL_DMA_STREAM_4
02954   *         @arg @ref LL_DMA_STREAM_5
02955   *         @arg @ref LL_DMA_STREAM_6
02956   *         @arg @ref LL_DMA_STREAM_7
02957   * @retval None
02958   */
02959 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
02960 {
02961   register uint32_t dma_base_addr = (uint32_t)DMAx;
02962
02963   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
02964 }
02965
02966 /**
02967   * @brief Disable Transfer error interrupt.
02968   * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
02969   * @param  DMAx DMAx Instance
02970   * @param  Stream This parameter can be one of the following values:
02971   *         @arg @ref LL_DMA_STREAM_0
02972   *         @arg @ref LL_DMA_STREAM_1
02973   *         @arg @ref LL_DMA_STREAM_2
02974   *         @arg @ref LL_DMA_STREAM_3
02975   *         @arg @ref LL_DMA_STREAM_4
02976   *         @arg @ref LL_DMA_STREAM_5
02977   *         @arg @ref LL_DMA_STREAM_6
02978   *         @arg @ref LL_DMA_STREAM_7
02979   * @retval None
02980   */
02981 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
02982 {
02983   register uint32_t dma_base_addr = (uint32_t)DMAx;
02984
02985   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
02986 }
02987
02988 /**
02989   * @brief Disable Transfer complete interrupt.
02990   * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
02991   * @param  DMAx DMAx Instance
02992   * @param  Stream This parameter can be one of the following values:
02993   *         @arg @ref LL_DMA_STREAM_0
02994   *         @arg @ref LL_DMA_STREAM_1
02995   *         @arg @ref LL_DMA_STREAM_2
02996   *         @arg @ref LL_DMA_STREAM_3
02997   *         @arg @ref LL_DMA_STREAM_4
02998   *         @arg @ref LL_DMA_STREAM_5
02999   *         @arg @ref LL_DMA_STREAM_6
03000   *         @arg @ref LL_DMA_STREAM_7
03001   * @retval None
03002   */
03003 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
03004 {
03005   register uint32_t dma_base_addr = (uint32_t)DMAx;
03006
03007   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
03008 }
03009
03010 /**
03011   * @brief Disable Direct mode error interrupt.
03012   * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
03013   * @param  DMAx DMAx Instance
03014   * @param  Stream This parameter can be one of the following values:
03015   *         @arg @ref LL_DMA_STREAM_0
03016   *         @arg @ref LL_DMA_STREAM_1
03017   *         @arg @ref LL_DMA_STREAM_2
03018   *         @arg @ref LL_DMA_STREAM_3
03019   *         @arg @ref LL_DMA_STREAM_4
03020   *         @arg @ref LL_DMA_STREAM_5
03021   *         @arg @ref LL_DMA_STREAM_6
03022   *         @arg @ref LL_DMA_STREAM_7
03023   * @retval None
03024   */
03025 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
03026 {
03027   register uint32_t dma_base_addr = (uint32_t)DMAx;
03028
03029   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
03030 }
03031
03032 /**
03033   * @brief Disable FIFO error interrupt.
03034   * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
03035   * @param  DMAx DMAx Instance
03036   * @param  Stream This parameter can be one of the following values:
03037   *         @arg @ref LL_DMA_STREAM_0
03038   *         @arg @ref LL_DMA_STREAM_1
03039   *         @arg @ref LL_DMA_STREAM_2
03040   *         @arg @ref LL_DMA_STREAM_3
03041   *         @arg @ref LL_DMA_STREAM_4
03042   *         @arg @ref LL_DMA_STREAM_5
03043   *         @arg @ref LL_DMA_STREAM_6
03044   *         @arg @ref LL_DMA_STREAM_7
03045   * @retval None
03046   */
03047 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
03048 {
03049   register uint32_t dma_base_addr = (uint32_t)DMAx;
03050
03051   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
03052 }
03053
03054 /**
03055   * @brief Check if Half transfer interrup is enabled.
03056   * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
03057   * @param  DMAx DMAx Instance
03058   * @param  Stream This parameter can be one of the following values:
03059   *         @arg @ref LL_DMA_STREAM_0
03060   *         @arg @ref LL_DMA_STREAM_1
03061   *         @arg @ref LL_DMA_STREAM_2
03062   *         @arg @ref LL_DMA_STREAM_3
03063   *         @arg @ref LL_DMA_STREAM_4
03064   *         @arg @ref LL_DMA_STREAM_5
03065   *         @arg @ref LL_DMA_STREAM_6
03066   *         @arg @ref LL_DMA_STREAM_7
03067   * @retval State of bit (1 or 0).
03068   */
03069 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
03070 {
03071   register uint32_t dma_base_addr = (uint32_t)DMAx;
03072
03073   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
03074 }
03075
03076 /**
03077   * @brief Check if Transfer error nterrup is enabled.
03078   * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
03079   * @param  DMAx DMAx Instance
03080   * @param  Stream This parameter can be one of the following values:
03081   *         @arg @ref LL_DMA_STREAM_0
03082   *         @arg @ref LL_DMA_STREAM_1
03083   *         @arg @ref LL_DMA_STREAM_2
03084   *         @arg @ref LL_DMA_STREAM_3
03085   *         @arg @ref LL_DMA_STREAM_4
03086   *         @arg @ref LL_DMA_STREAM_5
03087   *         @arg @ref LL_DMA_STREAM_6
03088   *         @arg @ref LL_DMA_STREAM_7
03089   * @retval State of bit (1 or 0).
03090   */
03091 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
03092 {
03093   register uint32_t dma_base_addr = (uint32_t)DMAx;
03094
03095   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
03096 }
03097
03098 /**
03099   * @brief Check if Transfer complete interrup is enabled.
03100   * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
03101   * @param  DMAx DMAx Instance
03102   * @param  Stream This parameter can be one of the following values:
03103   *         @arg @ref LL_DMA_STREAM_0
03104   *         @arg @ref LL_DMA_STREAM_1
03105   *         @arg @ref LL_DMA_STREAM_2
03106   *         @arg @ref LL_DMA_STREAM_3
03107   *         @arg @ref LL_DMA_STREAM_4
03108   *         @arg @ref LL_DMA_STREAM_5
03109   *         @arg @ref LL_DMA_STREAM_6
03110   *         @arg @ref LL_DMA_STREAM_7
03111   * @retval State of bit (1 or 0).
03112   */
03113 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
03114 {
03115   register uint32_t dma_base_addr = (uint32_t)DMAx;
03116
03117   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
03118 }
03119
03120 /**
03121   * @brief Check if Direct mode error interrupt is enabled.
03122   * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
03123   * @param  DMAx DMAx Instance
03124   * @param  Stream This parameter can be one of the following values:
03125   *         @arg @ref LL_DMA_STREAM_0
03126   *         @arg @ref LL_DMA_STREAM_1
03127   *         @arg @ref LL_DMA_STREAM_2
03128   *         @arg @ref LL_DMA_STREAM_3
03129   *         @arg @ref LL_DMA_STREAM_4
03130   *         @arg @ref LL_DMA_STREAM_5
03131   *         @arg @ref LL_DMA_STREAM_6
03132   *         @arg @ref LL_DMA_STREAM_7
03133   * @retval State of bit (1 or 0).
03134   */
03135 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
03136 {
03137   register uint32_t dma_base_addr = (uint32_t)DMAx;
03138
03139   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
03140 }
03141
03142 /**
03143   * @brief Check if FIFO error interrup is enabled.
03144   * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
03145   * @param  DMAx DMAx Instance
03146   * @param  Stream This parameter can be one of the following values:
03147   *         @arg @ref LL_DMA_STREAM_0
03148   *         @arg @ref LL_DMA_STREAM_1
03149   *         @arg @ref LL_DMA_STREAM_2
03150   *         @arg @ref LL_DMA_STREAM_3
03151   *         @arg @ref LL_DMA_STREAM_4
03152   *         @arg @ref LL_DMA_STREAM_5
03153   *         @arg @ref LL_DMA_STREAM_6
03154   *         @arg @ref LL_DMA_STREAM_7
03155   * @retval State of bit (1 or 0).
03156   */
03157 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
03158 {
03159   register uint32_t dma_base_addr = (uint32_t)DMAx;
03160
03161   return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
03162 }
03163
03164 /**
03165   * @}
03166   */
03167
03168 #if defined(USE_FULL_LL_DRIVER)
03169 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
03170   * @{
03171   */
03172
03173 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
03174 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
03175 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
03176
03177 /**
03178   * @}
03179   */
03180 #endif /* USE_FULL_LL_DRIVER */
03181
03182 /**
03183   * @}
03184   */
03185
03186 /**
03187   * @}
03188   */
03189
03190 #endif /* DMA1 || DMA2 */
03191
03192 /**
03193   * @}
03194   */
03195
03196 #ifdef __cplusplus
03197 }
03198 #endif
03199
03200 #endif /* __STM32H7xx_LL_DMA_H */
03201
03202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_dmamux.h Source File

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stm32h7xx_ll_dmamux.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_dmamux.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMAMUX LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_DMAMUX_H
00022 #define STM32H7xx_LL_DMAMUX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (DMAMUX1) || defined (DMAMUX2)
00036
00037 /** @defgroup DMAMUX_LL DMAMUX
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
00045   * @{
00046   */
00047 /* Define used to get DMAMUX CCR register size */
00048 #define DMAMUX_CCR_SIZE                   0x00000004U
00049
00050 /* Define used to get DMAMUX RGCR register size */
00051 #define DMAMUX_RGCR_SIZE                  0x00000004U
00052
00053 /* Define used to get DMAMUX RequestGenerator offset */
00054 #define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
00055 /* Define used to get DMAMUX Channel Status offset */
00056 #define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
00057 /* Define used to get DMAMUX RequestGenerator status offset */
00058 #define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private macros ------------------------------------------------------------*/
00065 /* Exported types ------------------------------------------------------------*/
00066 /* Exported constants --------------------------------------------------------*/
00067 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
00068   * @{
00069   */
00070 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
00071   * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
00072   * @{
00073   */
00074 #define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
00075 #define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
00076 #define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
00077 #define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
00078 #define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
00079 #define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
00080 #define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
00081 #define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
00082 #define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
00083 #define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
00084 #define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
00085 #define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
00086 #define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
00087 #define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
00088 #define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
00089 #define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
00090 #define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
00091 #define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
00092 #define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
00093 #define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
00094 #define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */
00095 #define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */
00096 #define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */
00097 #define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
00103   * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
00104   * @{
00105   */
00106 #define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
00107 #define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
00108 #define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
00109 #define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
00110 #define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
00111 #define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
00112 #define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
00113 #define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
00114 #define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
00115 #define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
00116 #define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
00117 #define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
00118 #define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
00119 #define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
00120 #define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
00121 #define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
00122 #define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
00123 #define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
00124 #define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
00125 #define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
00126 #define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */
00127 #define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */
00128 #define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */
00129 #define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup DMAMUX_LL_EC_IT IT Defines
00135   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
00136   * @{
00137   */
00138 #define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */
00139 #define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup DMAMUX_Request_selection DMAMUX Request selection
00145   * @brief    DMA Request selection
00146   * @{
00147   */
00148 /* DMAMUX1 requests */
00149 #define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */
00150 #define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */
00151 #define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */
00152 #define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */
00153 #define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */
00154 #define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */
00155 #define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */
00156 #define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */
00157 #define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */
00158 #define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */
00159 #define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */
00160 #define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */
00161 #define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */
00162 #define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */
00163 #define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */
00164 #define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */
00165 #define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */
00166 #define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */
00167 #define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */
00168 #define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */
00169 #define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */
00170 #define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */
00171 #define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */
00172 #define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */
00173 #define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */
00174 #define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */
00175 #define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */
00176 #define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */
00177 #define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */
00178 #define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */
00179 #define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */
00180 #define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */
00181 #define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */
00182 #define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */
00183 #define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */
00184 #define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */
00185 #define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */
00186 #define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */
00187 #define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */
00188 #define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */
00189 #define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */
00190 #define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */
00191 #define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */
00192 #define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */
00193 #define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */
00194 #define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */
00195 #define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */
00196 #define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */
00197 #define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */
00198 #define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */
00199 #define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */
00200 #define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */
00201 #define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */
00202 #define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */
00203 #define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */
00204 #define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */
00205 #define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */
00206 #define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */
00207 #define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */
00208 #define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */
00209 #define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */
00210 #define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */
00211 #define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */
00212 #define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */
00213 #define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */
00214 #define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */
00215 #define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */
00216 #define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */
00217 #define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */
00218 #define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */
00219 #define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */
00220 #define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */
00221 #define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */
00222 #define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */
00223 #if defined (PSSI)
00224 #define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */
00225 #define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
00226 #else
00227 #define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */
00228 #endif /* PSSI */
00229 #define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */
00230 #define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */
00231 #define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */
00232 #define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */
00233 #define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */
00234 #define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */
00235 #define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */
00236 #define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */
00237 #define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */
00238 #define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */
00239 #define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */
00240 #define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */
00241 #define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */
00242 #define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */
00243 #define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */
00244 #define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */
00245 #define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */
00246 #define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */
00247 #define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */
00248 #if defined (HRTIM1)
00249 #define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
00250 #define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
00251 #define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
00252 #define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
00253 #define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
00254 #define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
00255 #endif /* HRTIM1 */
00256 #define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */
00257 #define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */
00258 #define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */
00259 #define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */
00260 #define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */
00261 #define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */
00262 #define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */
00263 #define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */
00264 #define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */
00265 #define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */
00266 #define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */
00267 #define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */
00268 #if defined (SAI3)
00269 #define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */
00270 #define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */
00271 #endif /* SAI3 */
00272 #if defined (ADC3)
00273 #define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */
00274 #endif /* ADC3 */
00275 #if defined (UART9)
00276 #define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */
00277 #define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */
00278 #endif /* UART9 */
00279 #if defined (USART10)
00280 #define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */
00281 #define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */
00282 #endif /* USART10 */
00283
00284 /* DMAMUX2 requests */
00285 #define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */
00286 #define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */
00287 #define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */
00288 #define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */
00289 #define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */
00290 #define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */
00291 #define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */
00292 #define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */
00293 #define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */
00294 #define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */
00295 #define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */
00296 #define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */
00297 #define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */
00298 #define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */
00299 #define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */
00300 #if defined (SAI4)
00301 #define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */
00302 #define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */
00303 #endif /* SAI4 */
00304 #if defined (ADC3)
00305 #define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */
00306 #endif /* ADC3 */
00307 #if defined (DAC2)
00308 #define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */
00309 #endif /* DAC2 */
00310 #if defined (DFSDM2_Channel0)
00311 #define LL_DMAMUX2_REQ_DFSDM2          18U  /*!< DMAMUX2 DFSDM2 request           */
00312 #endif /* DFSDM2_Channel0 */
00313 /**
00314   * @}
00315   */
00316
00317
00318 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
00319   * @{
00320   */
00321 #define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
00322 #define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
00323 #define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
00324 #define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
00325 #define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
00326 #define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
00327 #define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
00328 #define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
00329 #define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */
00330 #define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */
00331 #define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
00332 #define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
00333 #define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
00334 #define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
00335 #define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
00336 #define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
00342   * @{
00343   */
00344 #define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */
00345 #define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */
00346 #define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */
00347 #define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
00353   * @{
00354   */
00355 #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
00356 #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
00357 #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
00358 #define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
00359 #define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
00360 #define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
00361 #define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
00362 #define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
00363
00364 #define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
00365 #define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
00366 #define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
00367 #define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
00368 #define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
00369 #define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
00370 #define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
00371 #define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
00372 #define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
00373 #define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
00374 #define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
00375 #define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
00376 #define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
00377 #define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
00378 #define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
00379 #define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
00386   * @{
00387   */
00388 #define LL_DMAMUX_REQ_GEN_0           0x00000000U
00389 #define LL_DMAMUX_REQ_GEN_1           0x00000001U
00390 #define LL_DMAMUX_REQ_GEN_2           0x00000002U
00391 #define LL_DMAMUX_REQ_GEN_3           0x00000003U
00392 #define LL_DMAMUX_REQ_GEN_4           0x00000004U
00393 #define LL_DMAMUX_REQ_GEN_5           0x00000005U
00394 #define LL_DMAMUX_REQ_GEN_6           0x00000006U
00395 #define LL_DMAMUX_REQ_GEN_7           0x00000007U
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
00401   * @{
00402   */
00403 #define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */
00404 #define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */
00405 #define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */
00406 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
00412   * @{
00413   */
00414 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */
00415 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */
00416 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */
00417 #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */
00418 #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */
00419 #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */
00420 #define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */
00421 #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */
00422
00423 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */
00424 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */
00425 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */
00426 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */
00427 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */
00428 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */
00429 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */
00430 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */
00431 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */
00432 #define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */
00433 #define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */
00434 #define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */
00435 #define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */
00436 #if defined (LPTIM4)
00437 #define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */
00438 #endif /* LPTIM4 */
00439 #if defined (LPTIM5)
00440 #define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */
00441 #endif /* LPTIM5 */
00442 #define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */
00443 #define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */
00444 #define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */
00445 #define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */
00446 #define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */
00447 #define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */
00448 #define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */
00449 #define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */
00450 #define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */
00451 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */
00452 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */
00453 #if defined (ADC3)
00454 #define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */
00455 #define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
00456 #endif /* ADC3 */
00457 #define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */
00458 #define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */
00459 /**
00460   * @}
00461   */
00462
00463 /**
00464   * @}
00465   */
00466
00467 /* Exported macro ------------------------------------------------------------*/
00468 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
00469   * @{
00470   */
00471
00472 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
00473   * @{
00474   */
00475 /**
00476   * @brief  Write a value in DMAMUX register
00477   * @param  __INSTANCE__ DMAMUX Instance
00478   * @param  __REG__ Register to be written
00479   * @param  __VALUE__ Value to be written in the register
00480   * @retval None
00481   */
00482 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00483
00484 /**
00485   * @brief  Read a value in DMAMUX register
00486   * @param  __INSTANCE__ DMAMUX Instance
00487   * @param  __REG__ Register to be read
00488   * @retval Register value
00489   */
00490 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00491 /**
00492   * @}
00493   */
00494
00495 /**
00496   * @}
00497   */
00498
00499 /* Exported functions --------------------------------------------------------*/
00500 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
00501  * @{
00502  */
00503
00504 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
00505   * @{
00506   */
00507 /**
00508   * @brief  Set DMAMUX request ID for DMAMUX Channel x.
00509   * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
00510   *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
00511   *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.
00512   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
00513   * @param  DMAMUXx DMAMUXx Instance
00514   * @param  Channel This parameter can be one of the following values:
00515   *         @arg @ref LL_DMAMUX_CHANNEL_0
00516   *         @arg @ref LL_DMAMUX_CHANNEL_1
00517   *         @arg @ref LL_DMAMUX_CHANNEL_2
00518   *         @arg @ref LL_DMAMUX_CHANNEL_3
00519   *         @arg @ref LL_DMAMUX_CHANNEL_4
00520   *         @arg @ref LL_DMAMUX_CHANNEL_5
00521   *         @arg @ref LL_DMAMUX_CHANNEL_6
00522   *         @arg @ref LL_DMAMUX_CHANNEL_7
00523   *         @arg @ref LL_DMAMUX_CHANNEL_8
00524   *         @arg @ref LL_DMAMUX_CHANNEL_9
00525   *         @arg @ref LL_DMAMUX_CHANNEL_10
00526   *         @arg @ref LL_DMAMUX_CHANNEL_11
00527   *         @arg @ref LL_DMAMUX_CHANNEL_12
00528   *         @arg @ref LL_DMAMUX_CHANNEL_13
00529   *         @arg @ref LL_DMAMUX_CHANNEL_14
00530   *         @arg @ref LL_DMAMUX_CHANNEL_15
00531   * @param  Request This parameter can be one of the following values:
00532   *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
00533   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
00534   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
00535   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
00536   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
00537   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
00538   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
00539   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
00540   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
00541   *         @arg @ref LL_DMAMUX1_REQ_ADC1
00542   *         @arg @ref LL_DMAMUX1_REQ_ADC2
00543   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
00544   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
00545   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
00546   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
00547   *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
00548   *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
00549   *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
00550   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
00551   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
00552   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
00553   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
00554   *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
00555   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
00556   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
00557   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
00558   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
00559   *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
00560   *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
00561   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
00562   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
00563   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
00564   *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
00565   *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
00566   *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
00567   *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
00568   *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
00569   *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
00570   *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
00571   *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
00572   *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
00573   *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
00574   *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
00575   *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
00576   *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
00577   *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
00578   *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
00579   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
00580   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
00581   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
00582   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
00583   *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
00584   *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
00585   *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
00586   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
00587   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
00588   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
00589   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
00590   *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
00591   *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
00592   *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
00593   *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
00594   *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
00595   *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
00596   *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
00597   *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
00598   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
00599   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
00600   *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
00601   *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
00602   *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
00603   *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
00604   *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
00605   *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
00606   *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
00607   *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
00608   *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
00609   *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
00610   *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
00611   *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
00612   *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
00613   *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
00614   *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
00615   *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
00616   *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
00617   *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
00618   *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
00619   *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
00620   *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
00621   *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
00622   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
00623   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
00624   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
00625   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
00626   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
00627   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
00628   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
00629   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
00630   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
00631   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
00632   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
00633   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
00634   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
00635   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
00636   *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
00637   *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
00638   *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
00639   *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
00640   *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
00641   *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
00642   *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
00643   *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
00644   *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
00645   *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
00646   *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
00647   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
00648   *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
00649   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
00650   *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
00651   *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
00652   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
00653   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
00654   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
00655   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
00656   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
00657   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
00658   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
00659   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
00660   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
00661   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
00662   *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
00663   *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
00664   *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
00665   *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
00666   *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
00667   *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
00668   *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
00669   *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
00670   *         @arg @ref LL_DMAMUX2_REQ_DFSDM2 (*)
00671   * @note   (*) Availability depends on devices.
00672   * @retval None
00673   */
00674 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
00675 {
00676   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00677
00678   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
00679 }
00680
00681 /**
00682   * @brief  Get DMAMUX request ID for DMAMUX Channel x.
00683   * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.
00684   *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
00685   *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.
00686   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
00687   * @param  DMAMUXx DMAMUXx Instance
00688   * @param  Channel This parameter can be one of the following values:
00689   *         @arg @ref LL_DMAMUX_CHANNEL_0
00690   *         @arg @ref LL_DMAMUX_CHANNEL_1
00691   *         @arg @ref LL_DMAMUX_CHANNEL_2
00692   *         @arg @ref LL_DMAMUX_CHANNEL_3
00693   *         @arg @ref LL_DMAMUX_CHANNEL_4
00694   *         @arg @ref LL_DMAMUX_CHANNEL_5
00695   *         @arg @ref LL_DMAMUX_CHANNEL_6
00696   *         @arg @ref LL_DMAMUX_CHANNEL_7
00697   *         @arg @ref LL_DMAMUX_CHANNEL_8
00698   *         @arg @ref LL_DMAMUX_CHANNEL_9
00699   *         @arg @ref LL_DMAMUX_CHANNEL_10
00700   *         @arg @ref LL_DMAMUX_CHANNEL_11
00701   *         @arg @ref LL_DMAMUX_CHANNEL_12
00702   *         @arg @ref LL_DMAMUX_CHANNEL_13
00703   *         @arg @ref LL_DMAMUX_CHANNEL_14
00704   *         @arg @ref LL_DMAMUX_CHANNEL_15
00705   * @retval Returned value can be one of the following values:
00706   *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
00707   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
00708   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
00709   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
00710   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
00711   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
00712   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
00713   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
00714   *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
00715   *         @arg @ref LL_DMAMUX1_REQ_ADC1
00716   *         @arg @ref LL_DMAMUX1_REQ_ADC2
00717   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
00718   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
00719   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
00720   *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
00721   *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
00722   *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
00723   *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
00724   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
00725   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
00726   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
00727   *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
00728   *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
00729   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
00730   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
00731   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
00732   *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
00733   *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
00734   *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
00735   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
00736   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
00737   *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
00738   *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
00739   *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
00740   *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
00741   *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
00742   *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
00743   *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
00744   *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
00745   *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
00746   *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
00747   *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
00748   *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
00749   *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
00750   *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
00751   *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
00752   *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
00753   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
00754   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
00755   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
00756   *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
00757   *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
00758   *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
00759   *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
00760   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
00761   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
00762   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
00763   *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
00764   *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
00765   *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
00766   *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
00767   *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
00768   *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
00769   *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
00770   *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
00771   *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
00772   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
00773   *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
00774   *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
00775   *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
00776   *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
00777   *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
00778   *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
00779   *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
00780   *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
00781   *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
00782   *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
00783   *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
00784   *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
00785   *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
00786   *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
00787   *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
00788   *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
00789   *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
00790   *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
00791   *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
00792   *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
00793   *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
00794   *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
00795   *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
00796   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
00797   *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
00798   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
00799   *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
00800   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
00801   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
00802   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
00803   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
00804   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
00805   *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
00806   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
00807   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
00808   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
00809   *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
00810   *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
00811   *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
00812   *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
00813   *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
00814   *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
00815   *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
00816   *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
00817   *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
00818   *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
00819   *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
00820   *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
00821   *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
00822   *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
00823   *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
00824   *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
00825   *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
00826   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
00827   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
00828   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
00829   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
00830   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
00831   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
00832   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
00833   *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
00834   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
00835   *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
00836   *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
00837   *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
00838   *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
00839   *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
00840   *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
00841   *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
00842   *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
00843   *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
00844   *         @arg @ref LL_DMAMUX2_REQ_DFSDM2 (*)
00845   * @note   (*) Availability depends on devices.
00846   * @retval None
00847   */
00848 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00849 {
00850   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00851
00852   return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
00853 }
00854
00855 /**
00856   * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00857   * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
00858   * @param  DMAMUXx DMAMUXx Instance
00859   * @param  Channel This parameter can be one of the following values:
00860   *         @arg @ref LL_DMAMUX_CHANNEL_0
00861   *         @arg @ref LL_DMAMUX_CHANNEL_1
00862   *         @arg @ref LL_DMAMUX_CHANNEL_2
00863   *         @arg @ref LL_DMAMUX_CHANNEL_3
00864   *         @arg @ref LL_DMAMUX_CHANNEL_4
00865   *         @arg @ref LL_DMAMUX_CHANNEL_5
00866   *         @arg @ref LL_DMAMUX_CHANNEL_6
00867   *         @arg @ref LL_DMAMUX_CHANNEL_7
00868   *         @arg @ref LL_DMAMUX_CHANNEL_8
00869   *         @arg @ref LL_DMAMUX_CHANNEL_9
00870   *         @arg @ref LL_DMAMUX_CHANNEL_10
00871   *         @arg @ref LL_DMAMUX_CHANNEL_11
00872   *         @arg @ref LL_DMAMUX_CHANNEL_12
00873   *         @arg @ref LL_DMAMUX_CHANNEL_13
00874   *         @arg @ref LL_DMAMUX_CHANNEL_14
00875   *         @arg @ref LL_DMAMUX_CHANNEL_15
00876   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
00877   * @retval None
00878   */
00879 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
00880 {
00881   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00882
00883   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
00884 }
00885
00886 /**
00887   * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00888   * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
00889   * @param  DMAMUXx DMAMUXx Instance
00890   * @param  Channel This parameter can be one of the following values:
00891   *         @arg @ref LL_DMAMUX_CHANNEL_0
00892   *         @arg @ref LL_DMAMUX_CHANNEL_1
00893   *         @arg @ref LL_DMAMUX_CHANNEL_2
00894   *         @arg @ref LL_DMAMUX_CHANNEL_3
00895   *         @arg @ref LL_DMAMUX_CHANNEL_4
00896   *         @arg @ref LL_DMAMUX_CHANNEL_5
00897   *         @arg @ref LL_DMAMUX_CHANNEL_6
00898   *         @arg @ref LL_DMAMUX_CHANNEL_7
00899   *         @arg @ref LL_DMAMUX_CHANNEL_8
00900   *         @arg @ref LL_DMAMUX_CHANNEL_9
00901   *         @arg @ref LL_DMAMUX_CHANNEL_10
00902   *         @arg @ref LL_DMAMUX_CHANNEL_11
00903   *         @arg @ref LL_DMAMUX_CHANNEL_12
00904   *         @arg @ref LL_DMAMUX_CHANNEL_13
00905   *         @arg @ref LL_DMAMUX_CHANNEL_14
00906   *         @arg @ref LL_DMAMUX_CHANNEL_15
00907   * @retval Between Min_Data = 1 and Max_Data = 32
00908   */
00909 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00910 {
00911   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00912
00913   return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
00914 }
00915
00916 /**
00917   * @brief  Set the polarity of the signal on which the DMA request is synchronized.
00918   * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
00919   * @param  DMAMUXx DMAMUXx Instance
00920   * @param  Channel This parameter can be one of the following values:
00921   *         @arg @ref LL_DMAMUX_CHANNEL_0
00922   *         @arg @ref LL_DMAMUX_CHANNEL_1
00923   *         @arg @ref LL_DMAMUX_CHANNEL_2
00924   *         @arg @ref LL_DMAMUX_CHANNEL_3
00925   *         @arg @ref LL_DMAMUX_CHANNEL_4
00926   *         @arg @ref LL_DMAMUX_CHANNEL_5
00927   *         @arg @ref LL_DMAMUX_CHANNEL_6
00928   *         @arg @ref LL_DMAMUX_CHANNEL_7
00929   *         @arg @ref LL_DMAMUX_CHANNEL_8
00930   *         @arg @ref LL_DMAMUX_CHANNEL_9
00931   *         @arg @ref LL_DMAMUX_CHANNEL_10
00932   *         @arg @ref LL_DMAMUX_CHANNEL_11
00933   *         @arg @ref LL_DMAMUX_CHANNEL_12
00934   *         @arg @ref LL_DMAMUX_CHANNEL_13
00935   *         @arg @ref LL_DMAMUX_CHANNEL_14
00936   *         @arg @ref LL_DMAMUX_CHANNEL_15
00937   * @param  Polarity This parameter can be one of the following values:
00938   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00939   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00940   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00941   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
00945 {
00946   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00947
00948   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
00949 }
00950
00951 /**
00952   * @brief  Get the polarity of the signal on which the DMA request is synchronized.
00953   * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
00954   * @param  DMAMUXx DMAMUXx Instance
00955   * @param  Channel This parameter can be one of the following values:
00956   *         @arg @ref LL_DMAMUX_CHANNEL_0
00957   *         @arg @ref LL_DMAMUX_CHANNEL_1
00958   *         @arg @ref LL_DMAMUX_CHANNEL_2
00959   *         @arg @ref LL_DMAMUX_CHANNEL_3
00960   *         @arg @ref LL_DMAMUX_CHANNEL_4
00961   *         @arg @ref LL_DMAMUX_CHANNEL_5
00962   *         @arg @ref LL_DMAMUX_CHANNEL_6
00963   *         @arg @ref LL_DMAMUX_CHANNEL_7
00964   *         @arg @ref LL_DMAMUX_CHANNEL_8
00965   *         @arg @ref LL_DMAMUX_CHANNEL_9
00966   *         @arg @ref LL_DMAMUX_CHANNEL_10
00967   *         @arg @ref LL_DMAMUX_CHANNEL_11
00968   *         @arg @ref LL_DMAMUX_CHANNEL_12
00969   *         @arg @ref LL_DMAMUX_CHANNEL_13
00970   *         @arg @ref LL_DMAMUX_CHANNEL_14
00971   *         @arg @ref LL_DMAMUX_CHANNEL_15
00972   * @retval Returned value can be one of the following values:
00973   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00974   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00975   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00976   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00977   */
00978 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00979 {
00980   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
00981
00982   return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
00983 }
00984
00985 /**
00986   * @brief  Enable the Event Generation on DMAMUX channel x.
00987   * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
00988   * @param  DMAMUXx DMAMUXx Instance
00989   * @param  Channel This parameter can be one of the following values:
00990   *         @arg @ref LL_DMAMUX_CHANNEL_0
00991   *         @arg @ref LL_DMAMUX_CHANNEL_1
00992   *         @arg @ref LL_DMAMUX_CHANNEL_2
00993   *         @arg @ref LL_DMAMUX_CHANNEL_3
00994   *         @arg @ref LL_DMAMUX_CHANNEL_4
00995   *         @arg @ref LL_DMAMUX_CHANNEL_5
00996   *         @arg @ref LL_DMAMUX_CHANNEL_6
00997   *         @arg @ref LL_DMAMUX_CHANNEL_7
00998   *         @arg @ref LL_DMAMUX_CHANNEL_8
00999   *         @arg @ref LL_DMAMUX_CHANNEL_9
01000   *         @arg @ref LL_DMAMUX_CHANNEL_10
01001   *         @arg @ref LL_DMAMUX_CHANNEL_11
01002   *         @arg @ref LL_DMAMUX_CHANNEL_12
01003   *         @arg @ref LL_DMAMUX_CHANNEL_13
01004   *         @arg @ref LL_DMAMUX_CHANNEL_14
01005   *         @arg @ref LL_DMAMUX_CHANNEL_15
01006   * @retval None
01007   */
01008 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01009 {
01010   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01011
01012   SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
01013 }
01014
01015 /**
01016   * @brief  Disable the Event Generation on DMAMUX channel x.
01017   * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
01018   * @param  DMAMUXx DMAMUXx Instance
01019   * @param  Channel This parameter can be one of the following values:
01020   *         @arg @ref LL_DMAMUX_CHANNEL_0
01021   *         @arg @ref LL_DMAMUX_CHANNEL_1
01022   *         @arg @ref LL_DMAMUX_CHANNEL_2
01023   *         @arg @ref LL_DMAMUX_CHANNEL_3
01024   *         @arg @ref LL_DMAMUX_CHANNEL_4
01025   *         @arg @ref LL_DMAMUX_CHANNEL_5
01026   *         @arg @ref LL_DMAMUX_CHANNEL_6
01027   *         @arg @ref LL_DMAMUX_CHANNEL_7
01028   *         @arg @ref LL_DMAMUX_CHANNEL_8
01029   *         @arg @ref LL_DMAMUX_CHANNEL_9
01030   *         @arg @ref LL_DMAMUX_CHANNEL_10
01031   *         @arg @ref LL_DMAMUX_CHANNEL_11
01032   *         @arg @ref LL_DMAMUX_CHANNEL_12
01033   *         @arg @ref LL_DMAMUX_CHANNEL_13
01034   *         @arg @ref LL_DMAMUX_CHANNEL_14
01035   *         @arg @ref LL_DMAMUX_CHANNEL_15
01036   * @retval None
01037   */
01038 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01039 {
01040   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01041
01042   CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
01043 }
01044
01045 /**
01046   * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
01047   * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
01048   * @param  DMAMUXx DMAMUXx Instance
01049   * @param  Channel This parameter can be one of the following values:
01050   *         @arg @ref LL_DMAMUX_CHANNEL_0
01051   *         @arg @ref LL_DMAMUX_CHANNEL_1
01052   *         @arg @ref LL_DMAMUX_CHANNEL_2
01053   *         @arg @ref LL_DMAMUX_CHANNEL_3
01054   *         @arg @ref LL_DMAMUX_CHANNEL_4
01055   *         @arg @ref LL_DMAMUX_CHANNEL_5
01056   *         @arg @ref LL_DMAMUX_CHANNEL_6
01057   *         @arg @ref LL_DMAMUX_CHANNEL_7
01058   *         @arg @ref LL_DMAMUX_CHANNEL_8
01059   *         @arg @ref LL_DMAMUX_CHANNEL_9
01060   *         @arg @ref LL_DMAMUX_CHANNEL_10
01061   *         @arg @ref LL_DMAMUX_CHANNEL_11
01062   *         @arg @ref LL_DMAMUX_CHANNEL_12
01063   *         @arg @ref LL_DMAMUX_CHANNEL_13
01064   *         @arg @ref LL_DMAMUX_CHANNEL_14
01065   *         @arg @ref LL_DMAMUX_CHANNEL_15
01066   * @retval State of bit (1 or 0).
01067   */
01068 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01069 {
01070   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01071
01072   return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
01073 }
01074
01075 /**
01076   * @brief  Enable the synchronization mode.
01077   * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
01078   * @param  DMAMUXx DMAMUXx Instance
01079   * @param  Channel This parameter can be one of the following values:
01080   *         @arg @ref LL_DMAMUX_CHANNEL_0
01081   *         @arg @ref LL_DMAMUX_CHANNEL_1
01082   *         @arg @ref LL_DMAMUX_CHANNEL_2
01083   *         @arg @ref LL_DMAMUX_CHANNEL_3
01084   *         @arg @ref LL_DMAMUX_CHANNEL_4
01085   *         @arg @ref LL_DMAMUX_CHANNEL_5
01086   *         @arg @ref LL_DMAMUX_CHANNEL_6
01087   *         @arg @ref LL_DMAMUX_CHANNEL_7
01088   *         @arg @ref LL_DMAMUX_CHANNEL_8
01089   *         @arg @ref LL_DMAMUX_CHANNEL_9
01090   *         @arg @ref LL_DMAMUX_CHANNEL_10
01091   *         @arg @ref LL_DMAMUX_CHANNEL_11
01092   *         @arg @ref LL_DMAMUX_CHANNEL_12
01093   *         @arg @ref LL_DMAMUX_CHANNEL_13
01094   *         @arg @ref LL_DMAMUX_CHANNEL_14
01095   *         @arg @ref LL_DMAMUX_CHANNEL_15
01096   * @retval None
01097   */
01098 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01099 {
01100   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01101
01102   SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
01103 }
01104
01105 /**
01106   * @brief  Disable the synchronization mode.
01107   * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
01108   * @param  DMAMUXx DMAMUXx Instance
01109   * @param  Channel This parameter can be one of the following values:
01110   *         @arg @ref LL_DMAMUX_CHANNEL_0
01111   *         @arg @ref LL_DMAMUX_CHANNEL_1
01112   *         @arg @ref LL_DMAMUX_CHANNEL_2
01113   *         @arg @ref LL_DMAMUX_CHANNEL_3
01114   *         @arg @ref LL_DMAMUX_CHANNEL_4
01115   *         @arg @ref LL_DMAMUX_CHANNEL_5
01116   *         @arg @ref LL_DMAMUX_CHANNEL_6
01117   *         @arg @ref LL_DMAMUX_CHANNEL_7
01118   *         @arg @ref LL_DMAMUX_CHANNEL_8
01119   *         @arg @ref LL_DMAMUX_CHANNEL_9
01120   *         @arg @ref LL_DMAMUX_CHANNEL_10
01121   *         @arg @ref LL_DMAMUX_CHANNEL_11
01122   *         @arg @ref LL_DMAMUX_CHANNEL_12
01123   *         @arg @ref LL_DMAMUX_CHANNEL_13
01124   *         @arg @ref LL_DMAMUX_CHANNEL_14
01125   *         @arg @ref LL_DMAMUX_CHANNEL_15
01126   * @retval None
01127   */
01128 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01129 {
01130   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01131
01132   CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
01133 }
01134
01135 /**
01136   * @brief  Check if the synchronization mode is enabled or disabled.
01137   * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
01138   * @param  DMAMUXx DMAMUXx Instance
01139   * @param  Channel This parameter can be one of the following values:
01140   *         @arg @ref LL_DMAMUX_CHANNEL_0
01141   *         @arg @ref LL_DMAMUX_CHANNEL_1
01142   *         @arg @ref LL_DMAMUX_CHANNEL_2
01143   *         @arg @ref LL_DMAMUX_CHANNEL_3
01144   *         @arg @ref LL_DMAMUX_CHANNEL_4
01145   *         @arg @ref LL_DMAMUX_CHANNEL_5
01146   *         @arg @ref LL_DMAMUX_CHANNEL_6
01147   *         @arg @ref LL_DMAMUX_CHANNEL_7
01148   *         @arg @ref LL_DMAMUX_CHANNEL_8
01149   *         @arg @ref LL_DMAMUX_CHANNEL_9
01150   *         @arg @ref LL_DMAMUX_CHANNEL_10
01151   *         @arg @ref LL_DMAMUX_CHANNEL_11
01152   *         @arg @ref LL_DMAMUX_CHANNEL_12
01153   *         @arg @ref LL_DMAMUX_CHANNEL_13
01154   *         @arg @ref LL_DMAMUX_CHANNEL_14
01155   *         @arg @ref LL_DMAMUX_CHANNEL_15
01156   * @retval State of bit (1 or 0).
01157   */
01158 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01159 {
01160   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01161
01162   return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
01163 }
01164
01165 /**
01166   * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
01167   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
01168   * @param  DMAMUXx DMAMUXx Instance
01169   * @param  Channel This parameter can be one of the following values:
01170   *         @arg @ref LL_DMAMUX_CHANNEL_0
01171   *         @arg @ref LL_DMAMUX_CHANNEL_1
01172   *         @arg @ref LL_DMAMUX_CHANNEL_2
01173   *         @arg @ref LL_DMAMUX_CHANNEL_3
01174   *         @arg @ref LL_DMAMUX_CHANNEL_4
01175   *         @arg @ref LL_DMAMUX_CHANNEL_5
01176   *         @arg @ref LL_DMAMUX_CHANNEL_6
01177   *         @arg @ref LL_DMAMUX_CHANNEL_7
01178   *         @arg @ref LL_DMAMUX_CHANNEL_8
01179   *         @arg @ref LL_DMAMUX_CHANNEL_9
01180   *         @arg @ref LL_DMAMUX_CHANNEL_10
01181   *         @arg @ref LL_DMAMUX_CHANNEL_11
01182   *         @arg @ref LL_DMAMUX_CHANNEL_12
01183   *         @arg @ref LL_DMAMUX_CHANNEL_13
01184   *         @arg @ref LL_DMAMUX_CHANNEL_14
01185   *         @arg @ref LL_DMAMUX_CHANNEL_15
01186   * @param  SyncID This parameter can be one of the following values:
01187   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
01188   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
01189   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
01190   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
01191   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
01192   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
01193   *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
01194   *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
01195   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
01196   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
01197   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
01198   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
01199   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
01200   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
01201   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
01202   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
01203   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
01204   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
01205   *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
01206   *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
01207   *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
01208   *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
01209   *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
01210   *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
01211   * @retval None
01212   */
01213 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
01214 {
01215   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01216
01217   MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
01218 }
01219
01220 /**
01221   * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
01222   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
01223   * @param  DMAMUXx DMAMUXx Instance
01224   * @param  Channel This parameter can be one of the following values:
01225   *         @arg @ref LL_DMAMUX_CHANNEL_0
01226   *         @arg @ref LL_DMAMUX_CHANNEL_1
01227   *         @arg @ref LL_DMAMUX_CHANNEL_2
01228   *         @arg @ref LL_DMAMUX_CHANNEL_3
01229   *         @arg @ref LL_DMAMUX_CHANNEL_4
01230   *         @arg @ref LL_DMAMUX_CHANNEL_5
01231   *         @arg @ref LL_DMAMUX_CHANNEL_6
01232   *         @arg @ref LL_DMAMUX_CHANNEL_7
01233   *         @arg @ref LL_DMAMUX_CHANNEL_8
01234   *         @arg @ref LL_DMAMUX_CHANNEL_9
01235   *         @arg @ref LL_DMAMUX_CHANNEL_10
01236   *         @arg @ref LL_DMAMUX_CHANNEL_11
01237   *         @arg @ref LL_DMAMUX_CHANNEL_12
01238   *         @arg @ref LL_DMAMUX_CHANNEL_13
01239   *         @arg @ref LL_DMAMUX_CHANNEL_14
01240   *         @arg @ref LL_DMAMUX_CHANNEL_15
01241   * @retval Returned value can be one of the following values:
01242   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
01243   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
01244   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
01245   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
01246   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
01247   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
01248   *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
01249   *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
01250   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
01251   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
01252   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
01253   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
01254   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
01255   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
01256   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
01257   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
01258   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
01259   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
01260   *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
01261   *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
01262   *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
01263   *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
01264   *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
01265   *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
01266   */
01267 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01268 {
01269   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01270
01271   return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
01272 }
01273
01274 /**
01275   * @brief  Enable the Request Generator.
01276   * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
01277   * @param  DMAMUXx DMAMUXx Instance
01278   * @param  RequestGenChannel This parameter can be one of the following values:
01279   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01280   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01281   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01282   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01283   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01284   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01285   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01286   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01287   * @retval None
01288   */
01289 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01290 {
01291   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01292
01293   SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
01294 }
01295
01296 /**
01297   * @brief  Disable the Request Generator.
01298   * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
01299   * @param  DMAMUXx DMAMUXx Instance
01300   * @param  RequestGenChannel This parameter can be one of the following values:
01301   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01302   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01303   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01304   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01305   * @retval None
01306   */
01307 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01308 {
01309   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01310
01311   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
01312 }
01313
01314 /**
01315   * @brief  Check if the Request Generator is enabled or disabled.
01316   * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
01317   * @param  DMAMUXx DMAMUXx Instance
01318   * @param  RequestGenChannel This parameter can be one of the following values:
01319   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01320   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01321   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01322   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01323   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01324   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01325   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01326   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01327   * @retval State of bit (1 or 0).
01328   */
01329 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01330 {
01331   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01332
01333   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
01334 }
01335
01336 /**
01337   * @brief  Set the polarity of the signal on which the DMA request is generated.
01338   * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
01339   * @param  DMAMUXx DMAMUXx Instance
01340   * @param  RequestGenChannel This parameter can be one of the following values:
01341   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01342   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01343   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01344   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01345   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01346   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01347   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01348   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01349   * @param  Polarity This parameter can be one of the following values:
01350   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01351   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01352   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01353   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
01357 {
01358   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01359
01360   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
01361 }
01362
01363 /**
01364   * @brief  Get the polarity of the signal on which the DMA request is generated.
01365   * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
01366   * @param  DMAMUXx DMAMUXx Instance
01367   * @param  RequestGenChannel This parameter can be one of the following values:
01368   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01369   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01370   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01371   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01372   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01373   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01374   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01375   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01376   * @retval Returned value can be one of the following values:
01377   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01378   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01379   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01380   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01381   */
01382 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01383 {
01384   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01385
01386   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
01387 }
01388
01389 /**
01390   * @brief  Set the number of DMA request that will be autorized after a generation event.
01391   * @note   This field can only be written when Generator is disabled.
01392   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
01393   * @param  DMAMUXx DMAMUXx Instance
01394   * @param  RequestGenChannel This parameter can be one of the following values:
01395   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01396   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01397   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01398   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01399   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01400   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01401   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01402   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01403   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
01404   * @retval None
01405   */
01406 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
01407 {
01408   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01409
01410   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
01411 }
01412
01413 /**
01414   * @brief  Get the number of DMA request that will be autorized after a generation event.
01415   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
01416   * @param  DMAMUXx DMAMUXx Instance
01417   * @param  RequestGenChannel This parameter can be one of the following values:
01418   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01419   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01420   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01421   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01422   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01423   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01424   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01425   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01426   * @retval Between Min_Data = 1 and Max_Data = 32
01427   */
01428 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01429 {
01430   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01431
01432   return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
01433 }
01434
01435 /**
01436   * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
01437   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
01438   * @param  DMAMUXx DMAMUXx Instance
01439   * @param  RequestGenChannel This parameter can be one of the following values:
01440   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01441   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01442   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01443   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01444   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01445   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01446   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01447   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01448   * @param  RequestSignalID This parameter can be one of the following values:
01449   *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
01450   *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
01451   *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
01452   *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
01453   *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
01454   *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
01455   *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
01456   *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
01457   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
01458   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
01459   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
01460   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
01461   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
01462   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
01463   *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
01464   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
01465   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
01466   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
01467   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
01468   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
01469   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
01470   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
01471   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
01472   *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
01473   *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
01474   *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
01475   *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
01476   *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
01477   *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
01478   *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
01479   *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
01480   *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
01481   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
01482   *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
01483   *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
01484   *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
01485   *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
01486   *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
01487   * @note   (*) Availability depends on devices.
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
01491 {
01492   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01493
01494   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
01495 }
01496
01497 /**
01498   * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
01499   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
01500   * @param  DMAMUXx DMAMUXx Instance
01501   * @param  RequestGenChannel This parameter can be one of the following values:
01502   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01503   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01504   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01505   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01506   *         @arg @ref LL_DMAMUX_REQ_GEN_4
01507   *         @arg @ref LL_DMAMUX_REQ_GEN_5
01508   *         @arg @ref LL_DMAMUX_REQ_GEN_6
01509   *         @arg @ref LL_DMAMUX_REQ_GEN_7
01510   * @retval Returned value can be one of the following values:
01511   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
01512   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
01513   *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
01514   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
01515   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
01516   *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
01517   *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
01518   *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
01519   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
01520   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
01521   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
01522   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
01523   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
01524   *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
01525   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
01526   *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
01527   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
01528   *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
01529   *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
01530   *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
01531   *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
01532   *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
01533   *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
01534   *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
01535   */
01536 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01537 {
01538   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01539
01540   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
01541 }
01542
01543 /**
01544   * @}
01545   */
01546
01547 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
01548   * @{
01549   */
01550
01551 /**
01552   * @brief  Get Synchronization Event Overrun Flag Channel 0.
01553   * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
01554   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01555   * @retval State of bit (1 or 0).
01556   */
01557 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01558 {
01559   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01560
01561   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
01562 }
01563
01564 /**
01565   * @brief  Get Synchronization Event Overrun Flag Channel 1.
01566   * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
01567   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01568   * @retval State of bit (1 or 0).
01569   */
01570 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01571 {
01572   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01573
01574   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
01575 }
01576
01577 /**
01578   * @brief  Get Synchronization Event Overrun Flag Channel 2.
01579   * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
01580   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01581   * @retval State of bit (1 or 0).
01582   */
01583 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01584 {
01585   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01586
01587   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
01588 }
01589
01590 /**
01591   * @brief  Get Synchronization Event Overrun Flag Channel 3.
01592   * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
01593   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01594   * @retval State of bit (1 or 0).
01595   */
01596 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01597 {
01598   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01599
01600   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
01601 }
01602
01603 /**
01604   * @brief  Get Synchronization Event Overrun Flag Channel 4.
01605   * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
01606   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01607   * @retval State of bit (1 or 0).
01608   */
01609 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01610 {
01611   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01612
01613   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
01614 }
01615
01616 /**
01617   * @brief  Get Synchronization Event Overrun Flag Channel 5.
01618   * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
01619   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01620   * @retval State of bit (1 or 0).
01621   */
01622 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01623 {
01624   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01625
01626   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
01627 }
01628
01629 /**
01630   * @brief  Get Synchronization Event Overrun Flag Channel 6.
01631   * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
01632   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01633   * @retval State of bit (1 or 0).
01634   */
01635 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01636 {
01637   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01638
01639   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
01640 }
01641
01642 /**
01643   * @brief  Get Synchronization Event Overrun Flag Channel 7.
01644   * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
01645   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01646   * @retval State of bit (1 or 0).
01647   */
01648 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01649 {
01650   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01651
01652   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
01653 }
01654
01655 /**
01656   * @brief  Get Synchronization Event Overrun Flag Channel 8.
01657   * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
01658   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01659   * @retval State of bit (1 or 0).
01660   */
01661 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01662 {
01663   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01664
01665   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
01666 }
01667
01668 /**
01669   * @brief  Get Synchronization Event Overrun Flag Channel 9.
01670   * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
01671   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01672   * @retval State of bit (1 or 0).
01673   */
01674 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01675 {
01676   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01677
01678   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
01679 }
01680
01681 /**
01682   * @brief  Get Synchronization Event Overrun Flag Channel 10.
01683   * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
01684   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01685   * @retval State of bit (1 or 0).
01686   */
01687 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01688 {
01689   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01690
01691   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
01692 }
01693
01694 /**
01695   * @brief  Get Synchronization Event Overrun Flag Channel 11.
01696   * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
01697   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01698   * @retval State of bit (1 or 0).
01699   */
01700 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01701 {
01702   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01703
01704   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
01705 }
01706
01707 /**
01708   * @brief  Get Synchronization Event Overrun Flag Channel 12.
01709   * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
01710   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01711   * @retval State of bit (1 or 0).
01712   */
01713 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
01714 {
01715   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01716
01717   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
01718 }
01719
01720 /**
01721   * @brief  Get Synchronization Event Overrun Flag Channel 13.
01722   * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
01723   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01724   * @retval State of bit (1 or 0).
01725   */
01726 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
01727 {
01728   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01729
01730   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
01731 }
01732
01733 /**
01734   * @brief  Get Synchronization Event Overrun Flag Channel 14.
01735   * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14
01736   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01737   * @retval State of bit (1 or 0).
01738   */
01739 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
01740 {
01741   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01742
01743   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
01744 }
01745
01746 /**
01747   * @brief  Get Synchronization Event Overrun Flag Channel 15.
01748   * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15
01749   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01750   * @retval State of bit (1 or 0).
01751   */
01752 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
01753 {
01754   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01755
01756   return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
01757 }
01758
01759 /**
01760   * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
01761   * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
01762   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01763   * @retval State of bit (1 or 0).
01764   */
01765 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01766 {
01767   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01768
01769   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
01770 }
01771
01772 /**
01773   * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
01774   * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
01775   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01776   * @retval State of bit (1 or 0).
01777   */
01778 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01779 {
01780   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01781
01782   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
01783 }
01784
01785 /**
01786   * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
01787   * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
01788   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01789   * @retval State of bit (1 or 0).
01790   */
01791 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01792 {
01793   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01794
01795   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
01796 }
01797
01798 /**
01799   * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
01800   * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
01801   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01802   * @retval State of bit (1 or 0).
01803   */
01804 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01805 {
01806   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01807
01808   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
01809 }
01810
01811 /**
01812   * @brief  Get Request Generator 4 Trigger Event Overrun Flag.
01813   * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4
01814   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01815   * @retval State of bit (1 or 0).
01816   */
01817 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01818 {
01819   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01820
01821   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
01822 }
01823
01824 /**
01825   * @brief  Get Request Generator 5 Trigger Event Overrun Flag.
01826   * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5
01827   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01828   * @retval State of bit (1 or 0).
01829   */
01830 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01831 {
01832   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01833
01834   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
01835 }
01836
01837 /**
01838   * @brief  Get Request Generator 6 Trigger Event Overrun Flag.
01839   * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6
01840   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01841   * @retval State of bit (1 or 0).
01842   */
01843 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01844 {
01845   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01846
01847   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
01848 }
01849
01850 /**
01851   * @brief  Get Request Generator 7 Trigger Event Overrun Flag.
01852   * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7
01853   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01854   * @retval State of bit (1 or 0).
01855   */
01856 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01857 {
01858   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01859
01860   return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
01861 }
01862
01863 /**
01864   * @brief  Clear Synchronization Event Overrun Flag Channel 0.
01865   * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
01866   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01867   * @retval None
01868   */
01869 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01870 {
01871   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01872
01873   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
01874 }
01875
01876 /**
01877   * @brief  Clear Synchronization Event Overrun Flag Channel 1.
01878   * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
01879   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01880   * @retval None
01881   */
01882 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01883 {
01884   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01885
01886   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
01887 }
01888
01889 /**
01890   * @brief  Clear Synchronization Event Overrun Flag Channel 2.
01891   * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
01892   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01893   * @retval None
01894   */
01895 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01896 {
01897   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01898
01899   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
01900 }
01901
01902 /**
01903   * @brief  Clear Synchronization Event Overrun Flag Channel 3.
01904   * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
01905   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01906   * @retval None
01907   */
01908 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01909 {
01910   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01911
01912   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
01913 }
01914
01915 /**
01916   * @brief  Clear Synchronization Event Overrun Flag Channel 4.
01917   * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
01918   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01919   * @retval None
01920   */
01921 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01922 {
01923   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01924
01925   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
01926 }
01927
01928 /**
01929   * @brief  Clear Synchronization Event Overrun Flag Channel 5.
01930   * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
01931   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01932   * @retval None
01933   */
01934 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01935 {
01936   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01937
01938   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
01939 }
01940
01941 /**
01942   * @brief  Clear Synchronization Event Overrun Flag Channel 6.
01943   * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
01944   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01945   * @retval None
01946   */
01947 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01948 {
01949   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01950
01951   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
01952 }
01953
01954 /**
01955   * @brief  Clear Synchronization Event Overrun Flag Channel 7.
01956   * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
01957   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01958   * @retval None
01959   */
01960 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01961 {
01962   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01963
01964   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
01965 }
01966
01967 /**
01968   * @brief  Clear Synchronization Event Overrun Flag Channel 8.
01969   * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
01970   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01974 {
01975   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01976
01977   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
01978 }
01979
01980 /**
01981   * @brief  Clear Synchronization Event Overrun Flag Channel 9.
01982   * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
01983   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01984   * @retval None
01985   */
01986 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01987 {
01988   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
01989
01990   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
01991 }
01992
01993 /**
01994   * @brief  Clear Synchronization Event Overrun Flag Channel 10.
01995   * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
01996   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01997   * @retval None
01998   */
01999 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
02000 {
02001   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02002
02003   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
02004 }
02005
02006 /**
02007   * @brief  Clear Synchronization Event Overrun Flag Channel 11.
02008   * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
02009   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02010   * @retval None
02011   */
02012 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
02013 {
02014   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02015
02016   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
02017 }
02018
02019 /**
02020   * @brief  Clear Synchronization Event Overrun Flag Channel 12.
02021   * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
02022   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
02026 {
02027   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02028
02029   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
02030 }
02031
02032 /**
02033   * @brief  Clear Synchronization Event Overrun Flag Channel 13.
02034   * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
02035   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02036   * @retval None
02037   */
02038 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
02039 {
02040   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02041
02042   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
02043 }
02044
02045 /**
02046   * @brief  Clear Synchronization Event Overrun Flag Channel 14.
02047   * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
02048   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02049   * @retval None
02050   */
02051 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
02052 {
02053   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02054
02055   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
02056 }
02057
02058 /**
02059   * @brief  Clear Synchronization Event Overrun Flag Channel 15.
02060   * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
02061   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
02065 {
02066   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02067
02068   SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
02069 }
02070
02071 /**
02072   * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
02073   * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
02074   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02075   * @retval None
02076   */
02077 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
02078 {
02079   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02080
02081   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
02082 }
02083
02084 /**
02085   * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
02086   * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
02087   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
02091 {
02092   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02093
02094   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
02095 }
02096
02097 /**
02098   * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
02099   * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
02100   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02101   * @retval None
02102   */
02103 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
02104 {
02105   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02106
02107   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
02108 }
02109
02110 /**
02111   * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
02112   * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
02113   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02114   * @retval None
02115   */
02116 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
02117 {
02118   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02119
02120   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
02121 }
02122
02123 /**
02124   * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.
02125   * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4
02126   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02127   * @retval None
02128   */
02129 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
02130 {
02131   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02132
02133   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
02134 }
02135
02136 /**
02137   * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.
02138   * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5
02139   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02140   * @retval None
02141   */
02142 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
02143 {
02144   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02145
02146   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
02147 }
02148
02149 /**
02150   * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.
02151   * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6
02152   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02153   * @retval None
02154   */
02155 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
02156 {
02157   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02158
02159   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
02160 }
02161
02162 /**
02163   * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.
02164   * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7
02165   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
02169 {
02170   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02171
02172   SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
02173 }
02174
02175 /**
02176   * @}
02177   */
02178
02179 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
02180   * @{
02181   */
02182
02183 /**
02184   * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
02185   * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
02186   * @param  DMAMUXx DMAMUXx Instance
02187   * @param  Channel This parameter can be one of the following values:
02188   *         @arg @ref LL_DMAMUX_CHANNEL_0
02189   *         @arg @ref LL_DMAMUX_CHANNEL_1
02190   *         @arg @ref LL_DMAMUX_CHANNEL_2
02191   *         @arg @ref LL_DMAMUX_CHANNEL_3
02192   *         @arg @ref LL_DMAMUX_CHANNEL_4
02193   *         @arg @ref LL_DMAMUX_CHANNEL_5
02194   *         @arg @ref LL_DMAMUX_CHANNEL_6
02195   *         @arg @ref LL_DMAMUX_CHANNEL_7
02196   *         @arg @ref LL_DMAMUX_CHANNEL_8
02197   *         @arg @ref LL_DMAMUX_CHANNEL_9
02198   *         @arg @ref LL_DMAMUX_CHANNEL_10
02199   *         @arg @ref LL_DMAMUX_CHANNEL_11
02200   *         @arg @ref LL_DMAMUX_CHANNEL_12
02201   *         @arg @ref LL_DMAMUX_CHANNEL_13
02202   *         @arg @ref LL_DMAMUX_CHANNEL_14
02203   *         @arg @ref LL_DMAMUX_CHANNEL_15
02204   * @retval None
02205   */
02206 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
02207 {
02208   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02209
02210   SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
02211 }
02212
02213 /**
02214   * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
02215   * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
02216   * @param  DMAMUXx DMAMUXx Instance
02217   * @param  Channel This parameter can be one of the following values:
02218   *         @arg @ref LL_DMAMUX_CHANNEL_0
02219   *         @arg @ref LL_DMAMUX_CHANNEL_1
02220   *         @arg @ref LL_DMAMUX_CHANNEL_2
02221   *         @arg @ref LL_DMAMUX_CHANNEL_3
02222   *         @arg @ref LL_DMAMUX_CHANNEL_4
02223   *         @arg @ref LL_DMAMUX_CHANNEL_5
02224   *         @arg @ref LL_DMAMUX_CHANNEL_6
02225   *         @arg @ref LL_DMAMUX_CHANNEL_7
02226   *         @arg @ref LL_DMAMUX_CHANNEL_8
02227   *         @arg @ref LL_DMAMUX_CHANNEL_9
02228   *         @arg @ref LL_DMAMUX_CHANNEL_10
02229   *         @arg @ref LL_DMAMUX_CHANNEL_11
02230   *         @arg @ref LL_DMAMUX_CHANNEL_12
02231   *         @arg @ref LL_DMAMUX_CHANNEL_13
02232   *         @arg @ref LL_DMAMUX_CHANNEL_14
02233   *         @arg @ref LL_DMAMUX_CHANNEL_15
02234   * @retval None
02235   */
02236 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
02237 {
02238   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02239
02240   CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
02241 }
02242
02243 /**
02244   * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
02245   * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
02246   * @param  DMAMUXx DMAMUXx Instance
02247   * @param  Channel This parameter can be one of the following values:
02248   *         @arg @ref LL_DMAMUX_CHANNEL_0
02249   *         @arg @ref LL_DMAMUX_CHANNEL_1
02250   *         @arg @ref LL_DMAMUX_CHANNEL_2
02251   *         @arg @ref LL_DMAMUX_CHANNEL_3
02252   *         @arg @ref LL_DMAMUX_CHANNEL_4
02253   *         @arg @ref LL_DMAMUX_CHANNEL_5
02254   *         @arg @ref LL_DMAMUX_CHANNEL_6
02255   *         @arg @ref LL_DMAMUX_CHANNEL_7
02256   *         @arg @ref LL_DMAMUX_CHANNEL_8
02257   *         @arg @ref LL_DMAMUX_CHANNEL_9
02258   *         @arg @ref LL_DMAMUX_CHANNEL_10
02259   *         @arg @ref LL_DMAMUX_CHANNEL_11
02260   *         @arg @ref LL_DMAMUX_CHANNEL_12
02261   *         @arg @ref LL_DMAMUX_CHANNEL_13
02262   *         @arg @ref LL_DMAMUX_CHANNEL_14
02263   *         @arg @ref LL_DMAMUX_CHANNEL_15
02264   * @retval State of bit (1 or 0).
02265   */
02266 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
02267 {
02268   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02269
02270   return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
02271 }
02272
02273 /**
02274   * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
02275   * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
02276   * @param  DMAMUXx DMAMUXx Instance
02277   * @param  RequestGenChannel This parameter can be one of the following values:
02278   *         @arg @ref LL_DMAMUX_REQ_GEN_0
02279   *         @arg @ref LL_DMAMUX_REQ_GEN_1
02280   *         @arg @ref LL_DMAMUX_REQ_GEN_2
02281   *         @arg @ref LL_DMAMUX_REQ_GEN_3
02282   *         @arg @ref LL_DMAMUX_REQ_GEN_4
02283   *         @arg @ref LL_DMAMUX_REQ_GEN_5
02284   *         @arg @ref LL_DMAMUX_REQ_GEN_6
02285   *         @arg @ref LL_DMAMUX_REQ_GEN_7
02286   * @retval None
02287   */
02288 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
02289 {
02290   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02291
02292   SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
02293 }
02294
02295 /**
02296   * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
02297   * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
02298   * @param  DMAMUXx DMAMUXx Instance
02299   * @param  RequestGenChannel This parameter can be one of the following values:
02300   *         @arg @ref LL_DMAMUX_REQ_GEN_0
02301   *         @arg @ref LL_DMAMUX_REQ_GEN_1
02302   *         @arg @ref LL_DMAMUX_REQ_GEN_2
02303   *         @arg @ref LL_DMAMUX_REQ_GEN_3
02304   *         @arg @ref LL_DMAMUX_REQ_GEN_4
02305   *         @arg @ref LL_DMAMUX_REQ_GEN_5
02306   *         @arg @ref LL_DMAMUX_REQ_GEN_6
02307   *         @arg @ref LL_DMAMUX_REQ_GEN_7
02308   * @retval None
02309   */
02310 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
02311 {
02312   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02313
02314   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
02315 }
02316
02317 /**
02318   * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
02319   * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
02320   * @param  DMAMUXx DMAMUXx Instance
02321   * @param  RequestGenChannel This parameter can be one of the following values:
02322   *         @arg @ref LL_DMAMUX_REQ_GEN_0
02323   *         @arg @ref LL_DMAMUX_REQ_GEN_1
02324   *         @arg @ref LL_DMAMUX_REQ_GEN_2
02325   *         @arg @ref LL_DMAMUX_REQ_GEN_3
02326   *         @arg @ref LL_DMAMUX_REQ_GEN_4
02327   *         @arg @ref LL_DMAMUX_REQ_GEN_5
02328   *         @arg @ref LL_DMAMUX_REQ_GEN_6
02329   *         @arg @ref LL_DMAMUX_REQ_GEN_7
02330   * @retval State of bit (1 or 0).
02331   */
02332 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
02333 {
02334   register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
02335
02336   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
02337 }
02338
02339 /**
02340   * @}
02341   */
02342
02343 /**
02344   * @}
02345   */
02346
02347 /**
02348   * @}
02349   */
02350
02351 #endif /* DMAMUX1 || DMAMUX2 */
02352
02353 /**
02354   * @}
02355   */
02356
02357 #ifdef __cplusplus
02358 }
02359 #endif
02360
02361 #endif /* __STM32H7xx_LL_DMAMUX_H */
02362
02363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_exti.c Source File

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stm32h7xx_ll_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_exti.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif
00028
00029 /** @addtogroup STM32H7xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (EXTI)
00034
00035 /** @defgroup EXTI_LL EXTI
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup EXTI_LL_Private_Macros
00044   * @{
00045   */
00046
00047 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31)  == 0x00000000U)
00048 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00049 #define IS_LL_EXTI_LINE_64_95(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
00050
00051 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00052                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00053                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00054
00055
00056 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00057                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00058                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00059                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Private function prototypes -----------------------------------------------*/
00066
00067 /* Exported functions --------------------------------------------------------*/
00068 /** @addtogroup EXTI_LL_Exported_Functions
00069   * @{
00070   */
00071
00072 /** @addtogroup EXTI_LL_EF_Init
00073   * @{
00074   */
00075
00076 /**
00077   * @brief  De-initialize the EXTI registers to their default reset values.
00078   * @retval An ErrorStatus enumeration value:
00079   *          - SUCCESS: EXTI registers are de-initialized
00080   *          - ERROR: not applicable
00081   */
00082 ErrorStatus LL_EXTI_DeInit(void)
00083 {
00084   /* Rising Trigger selection register set to default reset values */
00085   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
00086   LL_EXTI_WriteReg(RTSR2,  0x00000000U);
00087   LL_EXTI_WriteReg(RTSR3,  0x00000000U);
00088
00089   /* Falling Trigger selection register set to default reset values */
00090   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
00091   LL_EXTI_WriteReg(FTSR2,  0x00000000U);
00092   LL_EXTI_WriteReg(FTSR3,  0x00000000U);
00093
00094   /* Software interrupt event register set to default reset values */
00095   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
00096   LL_EXTI_WriteReg(SWIER2, 0x00000000U);
00097   LL_EXTI_WriteReg(SWIER3, 0x00000000U);
00098
00099   /* D3 Pending register set to default reset values */
00100   LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
00101   LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
00102   LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
00103
00104   /* D3 Pending clear selection register low to default reset values */
00105   LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
00106   LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
00107   LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
00108
00109   /* D3 Pending clear selection register high to default reset values */
00110   LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
00111   LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
00112   LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
00113
00114   /* Interrupt mask register set to default reset values */
00115   LL_EXTI_WriteReg(IMR1, 0x00000000U);
00116   LL_EXTI_WriteReg(IMR2, 0x00000000U);
00117   LL_EXTI_WriteReg(IMR3, 0x00000000U);
00118
00119   /*  Event mask register set to default reset values */
00120   LL_EXTI_WriteReg(EMR1, 0x00000000U);
00121   LL_EXTI_WriteReg(EMR2, 0x00000000U);
00122   LL_EXTI_WriteReg(EMR3, 0x00000000U);
00123
00124   /* Clear Pending requests */
00125   LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
00126   LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
00127   LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
00128
00129 #if defined(DUAL_CORE)
00130   /* Interrupt mask register set to default reset values  for Core 2 (Coretx-M4)*/
00131   LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
00132   LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
00133   LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
00134
00135   /*  Event mask register set to default reset values */
00136   LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
00137   LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
00138   LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
00139
00140   /* Clear Pending requests */
00141   LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
00142   LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
00143   LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
00144
00145 #endif /* DUAL_CORE*/
00146   return SUCCESS;
00147 }
00148
00149 /**
00150   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00151   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00152   * @retval An ErrorStatus enumeration value:
00153   *          - SUCCESS: EXTI registers are initialized
00154   *          - ERROR: not applicable
00155   */
00156 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00157 {
00158   ErrorStatus status = SUCCESS;
00159   /* Check the parameters */
00160   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00161   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00162   assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
00163   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00164   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00165
00166   /* ENABLE LineCommand */
00167   if (EXTI_InitStruct->LineCommand != DISABLE)
00168   {
00169     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00170
00171     /* Configure EXTI Lines in range from 0 to 31 */
00172     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00173     {
00174       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
00175       {
00176         /* Enable IT on provided Lines for Cortex-M7*/
00177         LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00178       }
00179       else
00180       {
00181         /* Disable IT on provided Lines for Cortex-M7*/
00182         LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00183       }
00184
00185       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
00186       {
00187         /* Enable event on provided Lines for Cortex-M7 */
00188         LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00189       }
00190       else
00191       {
00192         /* Disable event on provided Lines for Cortex-M7 */
00193         LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00194       }
00195 #if defined(DUAL_CORE)
00196       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
00197       {
00198         /* Enable IT on provided Lines for Cortex-M4 */
00199         LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
00200       }
00201       else
00202       {
00203         /* Disable IT on provided Lines for Cortex-M4*/
00204         LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00205       }
00206
00207       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
00208       {
00209         /* Enable event on provided Lines for Cortex-M4 */
00210         LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00211       }
00212       else
00213       {
00214         /* Disable event on provided Lines for Cortex-M4*/
00215         LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00216       }
00217 #endif /* DUAL_CORE */
00218
00219       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00220       {
00221         switch (EXTI_InitStruct->Trigger)
00222         {
00223           case LL_EXTI_TRIGGER_RISING:
00224             /* First Disable Falling Trigger on provided Lines */
00225             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00226             /* Then Enable Rising Trigger on provided Lines */
00227             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00228             break;
00229           case LL_EXTI_TRIGGER_FALLING:
00230             /* First Disable Rising Trigger on provided Lines */
00231             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00232             /* Then Enable Falling Trigger on provided Lines */
00233             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00234             break;
00235           case LL_EXTI_TRIGGER_RISING_FALLING:
00236             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00237             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00238             break;
00239           default:
00240             status = ERROR;
00241             break;
00242         }
00243       }
00244     }
00245     /* Configure EXTI Lines in range from 32 to 63 */
00246     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00247     {
00248       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
00249       {
00250         /* Enable IT on provided Lines for Cortex-M7*/
00251         LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00252       }
00253       else
00254       {
00255         /* Disable IT on provided Lines for Cortex-M7*/
00256         LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00257       }
00258
00259       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
00260       {
00261         /* Enable event on provided Lines for Cortex-M7 */
00262         LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00263       }
00264       else
00265       {
00266         /* Disable event on provided Lines for Cortex-M7 */
00267         LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00268       }
00269 #if defined(DUAL_CORE)
00270       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
00271       {
00272         /* Enable IT on provided Lines for Cortex-M4 */
00273         LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
00274       }
00275       else
00276       {
00277         /* Disable IT on provided Lines for Cortex-M4 */
00278         LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
00279       }
00280
00281       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
00282       {
00283         /* Enable event on provided Lines for Cortex-M4 */
00284         LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00285       }
00286       else
00287       {
00288         /* Disable event on provided Lines for Cortex-M4 */
00289         LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00290       }
00291 #endif /* DUAL_CORE */
00292
00293       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00294       {
00295         switch (EXTI_InitStruct->Trigger)
00296         {
00297           case LL_EXTI_TRIGGER_RISING:
00298             /* First Disable Falling Trigger on provided Lines */
00299             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00300             /* Then Enable IT on provided Lines */
00301             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00302             break;
00303           case LL_EXTI_TRIGGER_FALLING:
00304             /* First Disable Rising Trigger on provided Lines */
00305             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00306             /* Then Enable Falling Trigger on provided Lines */
00307             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00308             break;
00309           case LL_EXTI_TRIGGER_RISING_FALLING:
00310             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00311             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00312             break;
00313           default:
00314             status = ERROR;
00315             break;
00316         }
00317       }
00318     }
00319     /* Configure EXTI Lines in range from 64 to 95 */
00320     if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
00321     {
00322       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
00323       {
00324         /* Enable IT on provided Lines for Cortex-M7*/
00325         LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
00326       }
00327       else
00328       {
00329         /* Disable IT on provided Lines for Cortex-M7*/
00330         LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
00331       }
00332
00333       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
00334       {
00335         /* Enable event on provided Lines for Cortex-M7 */
00336         LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
00337       }
00338       else
00339       {
00340         /* Disable event on provided Lines for Cortex-M7 */
00341         LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
00342       }
00343
00344 #if defined(DUAL_CORE)
00345       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
00346       {
00347         /* Enable IT on provided Lines for Cortex-M4 */
00348         LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
00349       }
00350       else
00351       {
00352         /* Disable IT on provided Lines for Cortex-M4 */
00353         LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
00354       }
00355
00356       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
00357       {
00358         /* Enable event on provided Lines for Cortex-M4 */
00359         LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
00360       }
00361       else
00362       {
00363         /* Disable event on provided Lines for Cortex-M4 */
00364         LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
00365       }
00366 #endif /* DUAL_CORE */
00367
00368       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00369       {
00370         switch (EXTI_InitStruct->Trigger)
00371         {
00372           case LL_EXTI_TRIGGER_RISING:
00373             /* First Disable Falling Trigger on provided Lines */
00374             LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
00375             /* Then Enable IT on provided Lines */
00376             LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
00377             break;
00378           case LL_EXTI_TRIGGER_FALLING:
00379             /* First Disable Rising Trigger on provided Lines */
00380             LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
00381             /* Then Enable Falling Trigger on provided Lines */
00382             LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
00383             break;
00384           case LL_EXTI_TRIGGER_RISING_FALLING:
00385             LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
00386             LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
00387             break;
00388           default:
00389             status = ERROR;
00390             break;
00391         }
00392       }
00393     }
00394   }
00395   else /* DISABLE LineCommand */
00396   {
00397     /* Disable IT on provided Lines for Cortex-M7*/
00398     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00399     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00400     LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
00401
00402     /* Disable event on provided Lines for Cortex-M7 */
00403     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00404     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00405     LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
00406
00407 #if defined(DUAL_CORE)
00408     /* Disable IT on provided Lines for Cortex-M4*/
00409     LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00410     LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00411     LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
00412
00413     /* Disable event on provided Lines for Cortex-M4 */
00414     LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00415     LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00416     LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
00417 #endif /* DUAL_CORE */
00418   }
00419
00420   return status;
00421 }
00422
00423 /**
00424   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00425   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00426   * @retval None
00427   */
00428 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00429 {
00430   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00431   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00432   EXTI_InitStruct->Line_64_95     = LL_EXTI_LINE_NONE;
00433   EXTI_InitStruct->LineCommand    = DISABLE;
00434   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00435   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00436 }
00437
00438 /**
00439   * @}
00440   */
00441
00442 /**
00443   * @}
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 #endif /* defined (EXTI) */
00451
00452 /**
00453   * @}
00454   */
00455
00456 #endif /* USE_FULL_LL_DRIVER */
00457
00458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_exti.h Source File

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stm32h7xx_ll_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_LL_EXTI_H
00022 #define __STM32H7xx_LL_EXTI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (EXTI)
00036
00037 /** @defgroup EXTI_LL EXTI
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private Macros ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00047   * @{
00048   */
00049 /**
00050   * @}
00051   */
00052 #endif /*USE_FULL_LL_DRIVER*/
00053 /* Exported types ------------------------------------------------------------*/
00054 #if defined(USE_FULL_LL_DRIVER)
00055 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00056   * @{
00057   */
00058 typedef struct
00059 {
00060
00061   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00062                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00063
00064   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00065                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00066
00067   uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
00068                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00069
00070   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00071                                      This parameter can be set either to ENABLE or DISABLE */
00072
00073   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00074                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00075
00076   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00077                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00078 } LL_EXTI_InitTypeDef;
00079
00080 /**
00081   * @}
00082   */
00083 #endif /*USE_FULL_LL_DRIVER*/
00084
00085 /* Exported constants --------------------------------------------------------*/
00086 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00087   * @{
00088   */
00089
00090 /** @defgroup EXTI_LL_EC_LINE LINE
00091   * @{
00092   */
00093 #define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
00094 #define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
00095 #define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
00096 #define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
00097 #define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
00098 #define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
00099 #define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
00100 #define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
00101 #define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
00102 #define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
00103 #define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
00104 #define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
00105 #define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
00106 #define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
00107 #define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
00108 #define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
00109 #define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
00110 #define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
00111 #define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
00112 #define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
00113 #define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
00114 #define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
00115 #define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
00116 #define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
00117 #define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
00118 #define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
00119 #define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
00120 #define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
00121 #define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
00122 #define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
00123 #define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
00124 #define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
00125 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
00126
00127 #define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
00128 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00129 #define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
00130 #define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
00131 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00132 #define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
00133 #define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
00134 #define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
00135 #define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
00136 #define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
00137 #define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
00138 #define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
00139 #if defined(USB2_OTG_FS)
00140 #define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
00141 #endif /* USB2_OTG_FS */
00142 #if defined(DSI)
00143 #define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
00144 #endif /* DSI */
00145 #define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
00146 #define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
00147 #define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
00148 #define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
00149 #define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
00150 #define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
00151 #define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
00152 #define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
00153 #define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
00154 #define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
00155 #define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
00156 #define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
00157 #define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */
00158 #define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
00159 #define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
00160 #define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
00161 #define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
00162 #define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
00163
00164 #define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
00165 #define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
00166 #define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
00167 #define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */
00168 #define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
00169 #define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
00170 #define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
00171 #define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
00172 #define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
00173 #define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
00174 #define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
00175 #if defined(ADC3)
00176 #define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */
00177 #endif /* ADC3 */
00178 #if defined(SAI4)
00179 #define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */
00180 #endif /* SAI4 */
00181 #if defined(DUAL_CORE)
00182 #define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
00183 #define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */
00184 #define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */
00185 #define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */
00186 #define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */
00187 #define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */
00188 #endif /* DUAL_CORE */
00189 #define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */
00190 #if defined(ETH)
00191 #define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */
00192 #endif /* ETH */
00193 #define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */
00194 #if defined(DTS)
00195 #define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 87 */
00196 #endif /* DTS */
00197 #define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
00198
00199
00200 #define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
00201
00202 #if defined(USE_FULL_LL_DRIVER)
00203 #define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
00204 #endif /*USE_FULL_LL_DRIVER*/
00205
00206 /**
00207   * @}
00208   */
00209 #if defined(USE_FULL_LL_DRIVER)
00210
00211 /** @defgroup EXTI_LL_EC_MODE Mode
00212   * @{
00213   */
00214 #define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */
00215 #define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */
00216 #define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */
00217
00218 #if defined(DUAL_CORE)
00219 #define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */
00220 #define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */
00221 #define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
00222
00223 #define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */
00224 #define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */
00225 #define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */
00226 #endif /* DUAL_CORE */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00233   * @{
00234   */
00235 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00236 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00237 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00238 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source
00245   * @{
00246   */
00247 #define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */
00248 #define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */
00249 #if defined (LPTIM4)
00250 #define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */
00251 #else
00252 #define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */
00253 #endif /*LPTIM4*/
00254 #if defined (LPTIM5)
00255 #define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */
00256 #else
00257 #define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */
00258 #endif /*LPTIM5*/
00259 /**
00260   * @}
00261   */
00262
00263
00264 #endif /*USE_FULL_LL_DRIVER*/
00265
00266
00267 /**
00268   * @}
00269   */
00270
00271 /* Exported macro ------------------------------------------------------------*/
00272 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00273   * @{
00274   */
00275
00276 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00277   * @{
00278   */
00279
00280 /**
00281   * @brief  Write a value in EXTI register
00282   * @param  __REG__ Register to be written
00283   * @param  __VALUE__ Value to be written in the register
00284   * @retval None
00285   */
00286 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00287
00288 /**
00289   * @brief  Read a value in EXTI register
00290   * @param  __REG__ Register to be read
00291   * @retval Register value
00292   */
00293 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00294
00295 /**
00296   * @}
00297   */
00298
00299
00300 /**
00301   * @}
00302   */
00303
00304
00305
00306 /* Exported functions --------------------------------------------------------*/
00307 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00308  * @{
00309  */
00310 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00311   * @{
00312   */
00313
00314 /**
00315   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00316   * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
00317   * @param  ExtiLine This parameter can be one of the following values:
00318   *         @arg @ref LL_EXTI_LINE_0
00319   *         @arg @ref LL_EXTI_LINE_1
00320   *         @arg @ref LL_EXTI_LINE_2
00321   *         @arg @ref LL_EXTI_LINE_3
00322   *         @arg @ref LL_EXTI_LINE_4
00323   *         @arg @ref LL_EXTI_LINE_5
00324   *         @arg @ref LL_EXTI_LINE_6
00325   *         @arg @ref LL_EXTI_LINE_7
00326   *         @arg @ref LL_EXTI_LINE_8
00327   *         @arg @ref LL_EXTI_LINE_9
00328   *         @arg @ref LL_EXTI_LINE_10
00329   *         @arg @ref LL_EXTI_LINE_11
00330   *         @arg @ref LL_EXTI_LINE_12
00331   *         @arg @ref LL_EXTI_LINE_13
00332   *         @arg @ref LL_EXTI_LINE_14
00333   *         @arg @ref LL_EXTI_LINE_15
00334   *         @arg @ref LL_EXTI_LINE_16
00335   *         @arg @ref LL_EXTI_LINE_17
00336   *         @arg @ref LL_EXTI_LINE_18
00337   *         @arg @ref LL_EXTI_LINE_19
00338   *         @arg @ref LL_EXTI_LINE_20
00339   *         @arg @ref LL_EXTI_LINE_21
00340   *         @arg @ref LL_EXTI_LINE_22
00341   *         @arg @ref LL_EXTI_LINE_23
00342   *         @arg @ref LL_EXTI_LINE_24
00343   *         @arg @ref LL_EXTI_LINE_25
00344   *         @arg @ref LL_EXTI_LINE_26
00345   *         @arg @ref LL_EXTI_LINE_27
00346   *         @arg @ref LL_EXTI_LINE_28
00347   *         @arg @ref LL_EXTI_LINE_29
00348   *         @arg @ref LL_EXTI_LINE_30
00349   *         @arg @ref LL_EXTI_LINE_31
00350   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00351   * @retval None
00352   */
00353 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00354 {
00355   SET_BIT(EXTI->IMR1, ExtiLine);
00356 }
00357
00358 /**
00359   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00360   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00361   * @param  ExtiLine This parameter can be one of the following values:
00362   *         @arg @ref LL_EXTI_LINE_32
00363   *         @arg @ref LL_EXTI_LINE_33
00364   *         @arg @ref LL_EXTI_LINE_34
00365   *         @arg @ref LL_EXTI_LINE_35
00366   *         @arg @ref LL_EXTI_LINE_36
00367   *         @arg @ref LL_EXTI_LINE_37
00368   *         @arg @ref LL_EXTI_LINE_38
00369   *         @arg @ref LL_EXTI_LINE_39
00370   *         @arg @ref LL_EXTI_LINE_40
00371   *         @arg @ref LL_EXTI_LINE_41
00372   *         @arg @ref LL_EXTI_LINE_42
00373   *         @arg @ref LL_EXTI_LINE_43
00374   *         @arg @ref LL_EXTI_LINE_44
00375   *         @arg @ref LL_EXTI_LINE_46
00376   *         @arg @ref LL_EXTI_LINE_47
00377   *         @arg @ref LL_EXTI_LINE_48
00378   *         @arg @ref LL_EXTI_LINE_49
00379   *         @arg @ref LL_EXTI_LINE_50
00380   *         @arg @ref LL_EXTI_LINE_51
00381   *         @arg @ref LL_EXTI_LINE_52
00382   *         @arg @ref LL_EXTI_LINE_53
00383   *         @arg @ref LL_EXTI_LINE_54
00384   *         @arg @ref LL_EXTI_LINE_55
00385   *         @arg @ref LL_EXTI_LINE_56
00386   *         @arg @ref LL_EXTI_LINE_57
00387   *         @arg @ref LL_EXTI_LINE_58
00388   *         @arg @ref LL_EXTI_LINE_59
00389   *         @arg @ref LL_EXTI_LINE_60
00390   *         @arg @ref LL_EXTI_LINE_61
00391   *         @arg @ref LL_EXTI_LINE_62
00392   *         @arg @ref LL_EXTI_LINE_63
00393   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00394   * @retval None
00395   */
00396 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00397 {
00398   SET_BIT(EXTI->IMR2, ExtiLine);
00399 }
00400
00401
00402 /**
00403   * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
00404   * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
00405   * @param  ExtiLine This parameter can be one of the following values:
00406   *         @arg @ref LL_EXTI_LINE_64
00407   *         @arg @ref LL_EXTI_LINE_65
00408   *         @arg @ref LL_EXTI_LINE_66
00409   *         @arg @ref LL_EXTI_LINE_67
00410   *         @arg @ref LL_EXTI_LINE_68
00411   *         @arg @ref LL_EXTI_LINE_69
00412   *         @arg @ref LL_EXTI_LINE_70
00413   *         @arg @ref LL_EXTI_LINE_71
00414   *         @arg @ref LL_EXTI_LINE_72
00415   *         @arg @ref LL_EXTI_LINE_73
00416   *         @arg @ref LL_EXTI_LINE_74
00417   *         @arg @ref LL_EXTI_LINE_75
00418   *         @arg @ref LL_EXTI_LINE_76
00419   *         @arg @ref LL_EXTI_LINE_77
00420   *         @arg @ref LL_EXTI_LINE_78
00421   *         @arg @ref LL_EXTI_LINE_79
00422   *         @arg @ref LL_EXTI_LINE_80
00423   *         @arg @ref LL_EXTI_LINE_82
00424   *         @arg @ref LL_EXTI_LINE_84
00425   *         @arg @ref LL_EXTI_LINE_85
00426   *         @arg @ref LL_EXTI_LINE_86
00427   *         @arg @ref LL_EXTI_LINE_87
00428   *         @arg @ref LL_EXTI_LINE_ALL_64_95
00429   * @retval None
00430   */
00431 __STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
00432 {
00433   SET_BIT(EXTI->IMR3, ExtiLine);
00434 }
00435
00436
00437 /**
00438   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00439   * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
00440   * @param  ExtiLine This parameter can be one of the following values:
00441   *         @arg @ref LL_EXTI_LINE_0
00442   *         @arg @ref LL_EXTI_LINE_1
00443   *         @arg @ref LL_EXTI_LINE_2
00444   *         @arg @ref LL_EXTI_LINE_3
00445   *         @arg @ref LL_EXTI_LINE_4
00446   *         @arg @ref LL_EXTI_LINE_5
00447   *         @arg @ref LL_EXTI_LINE_6
00448   *         @arg @ref LL_EXTI_LINE_7
00449   *         @arg @ref LL_EXTI_LINE_8
00450   *         @arg @ref LL_EXTI_LINE_9
00451   *         @arg @ref LL_EXTI_LINE_10
00452   *         @arg @ref LL_EXTI_LINE_11
00453   *         @arg @ref LL_EXTI_LINE_12
00454   *         @arg @ref LL_EXTI_LINE_13
00455   *         @arg @ref LL_EXTI_LINE_14
00456   *         @arg @ref LL_EXTI_LINE_15
00457   *         @arg @ref LL_EXTI_LINE_16
00458   *         @arg @ref LL_EXTI_LINE_17
00459   *         @arg @ref LL_EXTI_LINE_18
00460   *         @arg @ref LL_EXTI_LINE_19
00461   *         @arg @ref LL_EXTI_LINE_20
00462   *         @arg @ref LL_EXTI_LINE_21
00463   *         @arg @ref LL_EXTI_LINE_22
00464   *         @arg @ref LL_EXTI_LINE_23
00465   *         @arg @ref LL_EXTI_LINE_24
00466   *         @arg @ref LL_EXTI_LINE_25
00467   *         @arg @ref LL_EXTI_LINE_26
00468   *         @arg @ref LL_EXTI_LINE_27
00469   *         @arg @ref LL_EXTI_LINE_28
00470   *         @arg @ref LL_EXTI_LINE_29
00471   *         @arg @ref LL_EXTI_LINE_30
00472   *         @arg @ref LL_EXTI_LINE_31
00473   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00474   * @retval None
00475   */
00476 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00477 {
00478   CLEAR_BIT(EXTI->IMR1, ExtiLine);
00479 }
00480
00481
00482 /**
00483   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00484   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00485   * @param  ExtiLine This parameter can be one of the following values:
00486   *         @arg @ref LL_EXTI_LINE_32
00487   *         @arg @ref LL_EXTI_LINE_33
00488   *         @arg @ref LL_EXTI_LINE_34
00489   *         @arg @ref LL_EXTI_LINE_35
00490   *         @arg @ref LL_EXTI_LINE_36
00491   *         @arg @ref LL_EXTI_LINE_37
00492   *         @arg @ref LL_EXTI_LINE_38
00493   *         @arg @ref LL_EXTI_LINE_39
00494   *         @arg @ref LL_EXTI_LINE_40
00495   *         @arg @ref LL_EXTI_LINE_41
00496   *         @arg @ref LL_EXTI_LINE_42
00497   *         @arg @ref LL_EXTI_LINE_43
00498   *         @arg @ref LL_EXTI_LINE_44
00499   *         @arg @ref LL_EXTI_LINE_46
00500   *         @arg @ref LL_EXTI_LINE_47
00501   *         @arg @ref LL_EXTI_LINE_48
00502   *         @arg @ref LL_EXTI_LINE_49
00503   *         @arg @ref LL_EXTI_LINE_50
00504   *         @arg @ref LL_EXTI_LINE_51
00505   *         @arg @ref LL_EXTI_LINE_52
00506   *         @arg @ref LL_EXTI_LINE_53
00507   *         @arg @ref LL_EXTI_LINE_54
00508   *         @arg @ref LL_EXTI_LINE_55
00509   *         @arg @ref LL_EXTI_LINE_56
00510   *         @arg @ref LL_EXTI_LINE_57
00511   *         @arg @ref LL_EXTI_LINE_58
00512   *         @arg @ref LL_EXTI_LINE_59
00513   *         @arg @ref LL_EXTI_LINE_60
00514   *         @arg @ref LL_EXTI_LINE_61
00515   *         @arg @ref LL_EXTI_LINE_62
00516   *         @arg @ref LL_EXTI_LINE_63
00517   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00521 {
00522   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00523 }
00524
00525 /**
00526   * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
00527   * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
00528   * @param  ExtiLine This parameter can be one of the following values:
00529   *         @arg @ref LL_EXTI_LINE_64
00530   *         @arg @ref LL_EXTI_LINE_65
00531   *         @arg @ref LL_EXTI_LINE_66
00532   *         @arg @ref LL_EXTI_LINE_67
00533   *         @arg @ref LL_EXTI_LINE_68
00534   *         @arg @ref LL_EXTI_LINE_69
00535   *         @arg @ref LL_EXTI_LINE_70
00536   *         @arg @ref LL_EXTI_LINE_71
00537   *         @arg @ref LL_EXTI_LINE_72
00538   *         @arg @ref LL_EXTI_LINE_73
00539   *         @arg @ref LL_EXTI_LINE_74
00540   *         @arg @ref LL_EXTI_LINE_75
00541   *         @arg @ref LL_EXTI_LINE_76
00542   *         @arg @ref LL_EXTI_LINE_77
00543   *         @arg @ref LL_EXTI_LINE_78
00544   *         @arg @ref LL_EXTI_LINE_79
00545   *         @arg @ref LL_EXTI_LINE_80
00546   *         @arg @ref LL_EXTI_LINE_82
00547   *         @arg @ref LL_EXTI_LINE_84
00548   *         @arg @ref LL_EXTI_LINE_85
00549   *         @arg @ref LL_EXTI_LINE_86
00550   *         @arg @ref LL_EXTI_LINE_87
00551   *         @arg @ref LL_EXTI_LINE_ALL_64_95
00552   * @retval None
00553   */
00554 __STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
00555 {
00556   CLEAR_BIT(EXTI->IMR3, ExtiLine);
00557 }
00558
00559
00560 /**
00561   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00562   * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
00563   * @param  ExtiLine This parameter can be one of the following values:
00564   *         @arg @ref LL_EXTI_LINE_0
00565   *         @arg @ref LL_EXTI_LINE_1
00566   *         @arg @ref LL_EXTI_LINE_2
00567   *         @arg @ref LL_EXTI_LINE_3
00568   *         @arg @ref LL_EXTI_LINE_4
00569   *         @arg @ref LL_EXTI_LINE_5
00570   *         @arg @ref LL_EXTI_LINE_6
00571   *         @arg @ref LL_EXTI_LINE_7
00572   *         @arg @ref LL_EXTI_LINE_8
00573   *         @arg @ref LL_EXTI_LINE_9
00574   *         @arg @ref LL_EXTI_LINE_10
00575   *         @arg @ref LL_EXTI_LINE_11
00576   *         @arg @ref LL_EXTI_LINE_12
00577   *         @arg @ref LL_EXTI_LINE_13
00578   *         @arg @ref LL_EXTI_LINE_14
00579   *         @arg @ref LL_EXTI_LINE_15
00580   *         @arg @ref LL_EXTI_LINE_16
00581   *         @arg @ref LL_EXTI_LINE_17
00582   *         @arg @ref LL_EXTI_LINE_18
00583   *         @arg @ref LL_EXTI_LINE_19
00584   *         @arg @ref LL_EXTI_LINE_20
00585   *         @arg @ref LL_EXTI_LINE_21
00586   *         @arg @ref LL_EXTI_LINE_22
00587   *         @arg @ref LL_EXTI_LINE_23
00588   *         @arg @ref LL_EXTI_LINE_24
00589   *         @arg @ref LL_EXTI_LINE_25
00590   *         @arg @ref LL_EXTI_LINE_26
00591   *         @arg @ref LL_EXTI_LINE_27
00592   *         @arg @ref LL_EXTI_LINE_28
00593   *         @arg @ref LL_EXTI_LINE_29
00594   *         @arg @ref LL_EXTI_LINE_30
00595   *         @arg @ref LL_EXTI_LINE_31
00596   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00597   * @retval State of bit (1 or 0).
00598   */
00599 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00600 {
00601   return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
00602 }
00603
00604
00605 /**
00606   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00607   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00608   * @param  ExtiLine This parameter can be one of the following values:
00609   *         @arg @ref LL_EXTI_LINE_32
00610   *         @arg @ref LL_EXTI_LINE_33
00611   *         @arg @ref LL_EXTI_LINE_34
00612   *         @arg @ref LL_EXTI_LINE_35
00613   *         @arg @ref LL_EXTI_LINE_36
00614   *         @arg @ref LL_EXTI_LINE_37
00615   *         @arg @ref LL_EXTI_LINE_38
00616   *         @arg @ref LL_EXTI_LINE_39
00617   *         @arg @ref LL_EXTI_LINE_40
00618   *         @arg @ref LL_EXTI_LINE_41
00619   *         @arg @ref LL_EXTI_LINE_42
00620   *         @arg @ref LL_EXTI_LINE_43
00621   *         @arg @ref LL_EXTI_LINE_44
00622   *         @arg @ref LL_EXTI_LINE_46
00623   *         @arg @ref LL_EXTI_LINE_47
00624   *         @arg @ref LL_EXTI_LINE_48
00625   *         @arg @ref LL_EXTI_LINE_49
00626   *         @arg @ref LL_EXTI_LINE_50
00627   *         @arg @ref LL_EXTI_LINE_51
00628   *         @arg @ref LL_EXTI_LINE_52
00629   *         @arg @ref LL_EXTI_LINE_53
00630   *         @arg @ref LL_EXTI_LINE_54
00631   *         @arg @ref LL_EXTI_LINE_55
00632   *         @arg @ref LL_EXTI_LINE_56
00633   *         @arg @ref LL_EXTI_LINE_57
00634   *         @arg @ref LL_EXTI_LINE_58
00635   *         @arg @ref LL_EXTI_LINE_59
00636   *         @arg @ref LL_EXTI_LINE_60
00637   *         @arg @ref LL_EXTI_LINE_61
00638   *         @arg @ref LL_EXTI_LINE_62
00639   *         @arg @ref LL_EXTI_LINE_63
00640   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00641   * @retval State of bit (1 or 0).
00642   */
00643 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00644 {
00645   return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
00646 }
00647
00648
00649 /**
00650   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
00651   * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
00652   * @param  ExtiLine This parameter can be one of the following values:
00653   *         @arg @ref LL_EXTI_LINE_64
00654   *         @arg @ref LL_EXTI_LINE_65
00655   *         @arg @ref LL_EXTI_LINE_66
00656   *         @arg @ref LL_EXTI_LINE_67
00657   *         @arg @ref LL_EXTI_LINE_68
00658   *         @arg @ref LL_EXTI_LINE_69
00659   *         @arg @ref LL_EXTI_LINE_70
00660   *         @arg @ref LL_EXTI_LINE_71
00661   *         @arg @ref LL_EXTI_LINE_72
00662   *         @arg @ref LL_EXTI_LINE_73
00663   *         @arg @ref LL_EXTI_LINE_74
00664   *         @arg @ref LL_EXTI_LINE_75
00665   *         @arg @ref LL_EXTI_LINE_76
00666   *         @arg @ref LL_EXTI_LINE_77
00667   *         @arg @ref LL_EXTI_LINE_78
00668   *         @arg @ref LL_EXTI_LINE_79
00669   *         @arg @ref LL_EXTI_LINE_80
00670   *         @arg @ref LL_EXTI_LINE_82
00671   *         @arg @ref LL_EXTI_LINE_84
00672   *         @arg @ref LL_EXTI_LINE_85
00673   *         @arg @ref LL_EXTI_LINE_86
00674   *         @arg @ref LL_EXTI_LINE_87
00675   *         @arg @ref LL_EXTI_LINE_ALL_64_95
00676   * @retval State of bit (1 or 0).
00677   */
00678 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
00679 {
00680   return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
00681 }
00682
00683 #if defined(DUAL_CORE)
00684 /**
00685   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
00686   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
00687   * @param  ExtiLine This parameter can be one of the following values:
00688   *         @arg @ref LL_EXTI_LINE_0
00689   *         @arg @ref LL_EXTI_LINE_1
00690   *         @arg @ref LL_EXTI_LINE_2
00691   *         @arg @ref LL_EXTI_LINE_3
00692   *         @arg @ref LL_EXTI_LINE_4
00693   *         @arg @ref LL_EXTI_LINE_5
00694   *         @arg @ref LL_EXTI_LINE_6
00695   *         @arg @ref LL_EXTI_LINE_7
00696   *         @arg @ref LL_EXTI_LINE_8
00697   *         @arg @ref LL_EXTI_LINE_9
00698   *         @arg @ref LL_EXTI_LINE_10
00699   *         @arg @ref LL_EXTI_LINE_11
00700   *         @arg @ref LL_EXTI_LINE_12
00701   *         @arg @ref LL_EXTI_LINE_13
00702   *         @arg @ref LL_EXTI_LINE_14
00703   *         @arg @ref LL_EXTI_LINE_15
00704   *         @arg @ref LL_EXTI_LINE_16
00705   *         @arg @ref LL_EXTI_LINE_17
00706   *         @arg @ref LL_EXTI_LINE_18
00707   *         @arg @ref LL_EXTI_LINE_19
00708   *         @arg @ref LL_EXTI_LINE_20
00709   *         @arg @ref LL_EXTI_LINE_21
00710   *         @arg @ref LL_EXTI_LINE_22
00711   *         @arg @ref LL_EXTI_LINE_23
00712   *         @arg @ref LL_EXTI_LINE_24
00713   *         @arg @ref LL_EXTI_LINE_25
00714   *         @arg @ref LL_EXTI_LINE_26
00715   *         @arg @ref LL_EXTI_LINE_27
00716   *         @arg @ref LL_EXTI_LINE_28
00717   *         @arg @ref LL_EXTI_LINE_29
00718   *         @arg @ref LL_EXTI_LINE_30
00719   *         @arg @ref LL_EXTI_LINE_31
00720   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00721   * @retval None
00722   */
00723 __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00724 {
00725   SET_BIT(EXTI->C2IMR1, ExtiLine);
00726 }
00727
00728
00729 /**
00730   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
00731   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
00732   * @param  ExtiLine This parameter can be one of the following values:
00733   *         @arg @ref LL_EXTI_LINE_32
00734   *         @arg @ref LL_EXTI_LINE_33
00735   *         @arg @ref LL_EXTI_LINE_34
00736   *         @arg @ref LL_EXTI_LINE_35
00737   *         @arg @ref LL_EXTI_LINE_36
00738   *         @arg @ref LL_EXTI_LINE_37
00739   *         @arg @ref LL_EXTI_LINE_38
00740   *         @arg @ref LL_EXTI_LINE_39
00741   *         @arg @ref LL_EXTI_LINE_40
00742   *         @arg @ref LL_EXTI_LINE_41
00743   *         @arg @ref LL_EXTI_LINE_42
00744   *         @arg @ref LL_EXTI_LINE_43
00745   *         @arg @ref LL_EXTI_LINE_44
00746   *         @arg @ref LL_EXTI_LINE_46
00747   *         @arg @ref LL_EXTI_LINE_47
00748   *         @arg @ref LL_EXTI_LINE_48
00749   *         @arg @ref LL_EXTI_LINE_49
00750   *         @arg @ref LL_EXTI_LINE_50
00751   *         @arg @ref LL_EXTI_LINE_51
00752   *         @arg @ref LL_EXTI_LINE_52
00753   *         @arg @ref LL_EXTI_LINE_53
00754   *         @arg @ref LL_EXTI_LINE_54
00755   *         @arg @ref LL_EXTI_LINE_55
00756   *         @arg @ref LL_EXTI_LINE_56
00757   *         @arg @ref LL_EXTI_LINE_57
00758   *         @arg @ref LL_EXTI_LINE_58
00759   *         @arg @ref LL_EXTI_LINE_59
00760   *         @arg @ref LL_EXTI_LINE_60
00761   *         @arg @ref LL_EXTI_LINE_61
00762   *         @arg @ref LL_EXTI_LINE_62
00763   *         @arg @ref LL_EXTI_LINE_63
00764   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00765   * @retval None
00766   */
00767 __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00768 {
00769   SET_BIT(EXTI->C2IMR2, ExtiLine);
00770 }
00771
00772
00773 /**
00774   * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
00775   * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95
00776   * @param  ExtiLine This parameter can be one of the following values:
00777   *         @arg @ref LL_EXTI_LINE_64
00778   *         @arg @ref LL_EXTI_LINE_65
00779   *         @arg @ref LL_EXTI_LINE_66
00780   *         @arg @ref LL_EXTI_LINE_67
00781   *         @arg @ref LL_EXTI_LINE_68
00782   *         @arg @ref LL_EXTI_LINE_69
00783   *         @arg @ref LL_EXTI_LINE_70
00784   *         @arg @ref LL_EXTI_LINE_71
00785   *         @arg @ref LL_EXTI_LINE_72
00786   *         @arg @ref LL_EXTI_LINE_73
00787   *         @arg @ref LL_EXTI_LINE_74
00788   *         @arg @ref LL_EXTI_LINE_75
00789   *         @arg @ref LL_EXTI_LINE_76
00790   *         @arg @ref LL_EXTI_LINE_77
00791   *         @arg @ref LL_EXTI_LINE_78
00792   *         @arg @ref LL_EXTI_LINE_79
00793   *         @arg @ref LL_EXTI_LINE_80
00794   *         @arg @ref LL_EXTI_LINE_82
00795   *         @arg @ref LL_EXTI_LINE_84
00796   *         @arg @ref LL_EXTI_LINE_85
00797   *         @arg @ref LL_EXTI_LINE_86
00798   *         @arg @ref LL_EXTI_LINE_87
00799   *         @arg @ref LL_EXTI_LINE_ALL_64_95
00800   * @retval None
00801   */
00802 __STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
00803 {
00804   SET_BIT(EXTI->C2IMR3, ExtiLine);
00805 }
00806
00807
00808 /**
00809   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
00810   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
00811   * @param  ExtiLine This parameter can be one of the following values:
00812   *         @arg @ref LL_EXTI_LINE_0
00813   *         @arg @ref LL_EXTI_LINE_1
00814   *         @arg @ref LL_EXTI_LINE_2
00815   *         @arg @ref LL_EXTI_LINE_3
00816   *         @arg @ref LL_EXTI_LINE_4
00817   *         @arg @ref LL_EXTI_LINE_5
00818   *         @arg @ref LL_EXTI_LINE_6
00819   *         @arg @ref LL_EXTI_LINE_7
00820   *         @arg @ref LL_EXTI_LINE_8
00821   *         @arg @ref LL_EXTI_LINE_9
00822   *         @arg @ref LL_EXTI_LINE_10
00823   *         @arg @ref LL_EXTI_LINE_11
00824   *         @arg @ref LL_EXTI_LINE_12
00825   *         @arg @ref LL_EXTI_LINE_13
00826   *         @arg @ref LL_EXTI_LINE_14
00827   *         @arg @ref LL_EXTI_LINE_15
00828   *         @arg @ref LL_EXTI_LINE_16
00829   *         @arg @ref LL_EXTI_LINE_17
00830   *         @arg @ref LL_EXTI_LINE_18
00831   *         @arg @ref LL_EXTI_LINE_19
00832   *         @arg @ref LL_EXTI_LINE_20
00833   *         @arg @ref LL_EXTI_LINE_21
00834   *         @arg @ref LL_EXTI_LINE_22
00835   *         @arg @ref LL_EXTI_LINE_23
00836   *         @arg @ref LL_EXTI_LINE_24
00837   *         @arg @ref LL_EXTI_LINE_25
00838   *         @arg @ref LL_EXTI_LINE_26
00839   *         @arg @ref LL_EXTI_LINE_27
00840   *         @arg @ref LL_EXTI_LINE_28
00841   *         @arg @ref LL_EXTI_LINE_29
00842   *         @arg @ref LL_EXTI_LINE_30
00843   *         @arg @ref LL_EXTI_LINE_31
00844   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00845   * @retval None
00846   */
00847 __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00848 {
00849   CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
00850 }
00851
00852
00853
00854 /**
00855   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
00856   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
00857   * @param  ExtiLine This parameter can be one of the following values:
00858   *         @arg @ref LL_EXTI_LINE_32
00859   *         @arg @ref LL_EXTI_LINE_33
00860   *         @arg @ref LL_EXTI_LINE_34
00861   *         @arg @ref LL_EXTI_LINE_35
00862   *         @arg @ref LL_EXTI_LINE_36
00863   *         @arg @ref LL_EXTI_LINE_37
00864   *         @arg @ref LL_EXTI_LINE_38
00865   *         @arg @ref LL_EXTI_LINE_39
00866   *         @arg @ref LL_EXTI_LINE_40
00867   *         @arg @ref LL_EXTI_LINE_41
00868   *         @arg @ref LL_EXTI_LINE_42
00869   *         @arg @ref LL_EXTI_LINE_43
00870   *         @arg @ref LL_EXTI_LINE_44
00871   *         @arg @ref LL_EXTI_LINE_46
00872   *         @arg @ref LL_EXTI_LINE_47
00873   *         @arg @ref LL_EXTI_LINE_48
00874   *         @arg @ref LL_EXTI_LINE_49
00875   *         @arg @ref LL_EXTI_LINE_50
00876   *         @arg @ref LL_EXTI_LINE_51
00877   *         @arg @ref LL_EXTI_LINE_52
00878   *         @arg @ref LL_EXTI_LINE_53
00879   *         @arg @ref LL_EXTI_LINE_54
00880   *         @arg @ref LL_EXTI_LINE_55
00881   *         @arg @ref LL_EXTI_LINE_56
00882   *         @arg @ref LL_EXTI_LINE_57
00883   *         @arg @ref LL_EXTI_LINE_58
00884   *         @arg @ref LL_EXTI_LINE_59
00885   *         @arg @ref LL_EXTI_LINE_60
00886   *         @arg @ref LL_EXTI_LINE_61
00887   *         @arg @ref LL_EXTI_LINE_62
00888   *         @arg @ref LL_EXTI_LINE_63
00889   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00890   * @retval None
00891   */
00892 __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00893 {
00894   CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
00895 }
00896
00897
00898 /**
00899   * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
00900   * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95
00901   * @param  ExtiLine This parameter can be one of the following values:
00902   *         @arg @ref LL_EXTI_LINE_64
00903   *         @arg @ref LL_EXTI_LINE_65
00904   *         @arg @ref LL_EXTI_LINE_66
00905   *         @arg @ref LL_EXTI_LINE_67
00906   *         @arg @ref LL_EXTI_LINE_68
00907   *         @arg @ref LL_EXTI_LINE_69
00908   *         @arg @ref LL_EXTI_LINE_70
00909   *         @arg @ref LL_EXTI_LINE_71
00910   *         @arg @ref LL_EXTI_LINE_72
00911   *         @arg @ref LL_EXTI_LINE_73
00912   *         @arg @ref LL_EXTI_LINE_74
00913   *         @arg @ref LL_EXTI_LINE_75
00914   *         @arg @ref LL_EXTI_LINE_76
00915   *         @arg @ref LL_EXTI_LINE_77
00916   *         @arg @ref LL_EXTI_LINE_78
00917   *         @arg @ref LL_EXTI_LINE_79
00918   *         @arg @ref LL_EXTI_LINE_80
00919   *         @arg @ref LL_EXTI_LINE_82
00920   *         @arg @ref LL_EXTI_LINE_84
00921   *         @arg @ref LL_EXTI_LINE_85
00922   *         @arg @ref LL_EXTI_LINE_86
00923   *         @arg @ref LL_EXTI_LINE_87
00924   *         @arg @ref LL_EXTI_LINE_ALL_64_95
00925   * @retval None
00926   */
00927 __STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
00928 {
00929   CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
00930 }
00931
00932
00933 /**
00934   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
00935   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
00936   * @param  ExtiLine This parameter can be one of the following values:
00937   *         @arg @ref LL_EXTI_LINE_0
00938   *         @arg @ref LL_EXTI_LINE_1
00939   *         @arg @ref LL_EXTI_LINE_2
00940   *         @arg @ref LL_EXTI_LINE_3
00941   *         @arg @ref LL_EXTI_LINE_4
00942   *         @arg @ref LL_EXTI_LINE_5
00943   *         @arg @ref LL_EXTI_LINE_6
00944   *         @arg @ref LL_EXTI_LINE_7
00945   *         @arg @ref LL_EXTI_LINE_8
00946   *         @arg @ref LL_EXTI_LINE_9
00947   *         @arg @ref LL_EXTI_LINE_10
00948   *         @arg @ref LL_EXTI_LINE_11
00949   *         @arg @ref LL_EXTI_LINE_12
00950   *         @arg @ref LL_EXTI_LINE_13
00951   *         @arg @ref LL_EXTI_LINE_14
00952   *         @arg @ref LL_EXTI_LINE_15
00953   *         @arg @ref LL_EXTI_LINE_16
00954   *         @arg @ref LL_EXTI_LINE_17
00955   *         @arg @ref LL_EXTI_LINE_18
00956   *         @arg @ref LL_EXTI_LINE_19
00957   *         @arg @ref LL_EXTI_LINE_20
00958   *         @arg @ref LL_EXTI_LINE_21
00959   *         @arg @ref LL_EXTI_LINE_22
00960   *         @arg @ref LL_EXTI_LINE_23
00961   *         @arg @ref LL_EXTI_LINE_24
00962   *         @arg @ref LL_EXTI_LINE_25
00963   *         @arg @ref LL_EXTI_LINE_26
00964   *         @arg @ref LL_EXTI_LINE_27
00965   *         @arg @ref LL_EXTI_LINE_28
00966   *         @arg @ref LL_EXTI_LINE_29
00967   *         @arg @ref LL_EXTI_LINE_30
00968   *         @arg @ref LL_EXTI_LINE_31
00969   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00970   * @retval State of bit (1 or 0).
00971   */
00972 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00973 {
00974   return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
00975 }
00976
00977
00978 /**
00979   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
00980   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
00981   * @param  ExtiLine This parameter can be one of the following values:
00982   *         @arg @ref LL_EXTI_LINE_32
00983   *         @arg @ref LL_EXTI_LINE_33
00984   *         @arg @ref LL_EXTI_LINE_34
00985   *         @arg @ref LL_EXTI_LINE_35
00986   *         @arg @ref LL_EXTI_LINE_36
00987   *         @arg @ref LL_EXTI_LINE_37
00988   *         @arg @ref LL_EXTI_LINE_38
00989   *         @arg @ref LL_EXTI_LINE_39
00990   *         @arg @ref LL_EXTI_LINE_40
00991   *         @arg @ref LL_EXTI_LINE_41
00992   *         @arg @ref LL_EXTI_LINE_42
00993   *         @arg @ref LL_EXTI_LINE_43
00994   *         @arg @ref LL_EXTI_LINE_44
00995   *         @arg @ref LL_EXTI_LINE_46
00996   *         @arg @ref LL_EXTI_LINE_47
00997   *         @arg @ref LL_EXTI_LINE_48
00998   *         @arg @ref LL_EXTI_LINE_49
00999   *         @arg @ref LL_EXTI_LINE_50
01000   *         @arg @ref LL_EXTI_LINE_51
01001   *         @arg @ref LL_EXTI_LINE_52
01002   *         @arg @ref LL_EXTI_LINE_53
01003   *         @arg @ref LL_EXTI_LINE_54
01004   *         @arg @ref LL_EXTI_LINE_55
01005   *         @arg @ref LL_EXTI_LINE_56
01006   *         @arg @ref LL_EXTI_LINE_57
01007   *         @arg @ref LL_EXTI_LINE_58
01008   *         @arg @ref LL_EXTI_LINE_59
01009   *         @arg @ref LL_EXTI_LINE_60
01010   *         @arg @ref LL_EXTI_LINE_61
01011   *         @arg @ref LL_EXTI_LINE_62
01012   *         @arg @ref LL_EXTI_LINE_63
01013   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01014   * @retval State of bit (1 or 0).
01015   */
01016 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
01017 {
01018   return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
01019 }
01020
01021
01022 /**
01023   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
01024   * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95
01025   * @param  ExtiLine This parameter can be one of the following values:
01026   *         @arg @ref LL_EXTI_LINE_64
01027   *         @arg @ref LL_EXTI_LINE_65
01028   *         @arg @ref LL_EXTI_LINE_66
01029   *         @arg @ref LL_EXTI_LINE_67
01030   *         @arg @ref LL_EXTI_LINE_68
01031   *         @arg @ref LL_EXTI_LINE_69
01032   *         @arg @ref LL_EXTI_LINE_70
01033   *         @arg @ref LL_EXTI_LINE_71
01034   *         @arg @ref LL_EXTI_LINE_72
01035   *         @arg @ref LL_EXTI_LINE_73
01036   *         @arg @ref LL_EXTI_LINE_74
01037   *         @arg @ref LL_EXTI_LINE_75
01038   *         @arg @ref LL_EXTI_LINE_76
01039   *         @arg @ref LL_EXTI_LINE_77
01040   *         @arg @ref LL_EXTI_LINE_78
01041   *         @arg @ref LL_EXTI_LINE_79
01042   *         @arg @ref LL_EXTI_LINE_80
01043   *         @arg @ref LL_EXTI_LINE_82
01044   *         @arg @ref LL_EXTI_LINE_84
01045   *         @arg @ref LL_EXTI_LINE_85
01046   *         @arg @ref LL_EXTI_LINE_86
01047   *         @arg @ref LL_EXTI_LINE_87
01048   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01049   * @retval State of bit (1 or 0).
01050   */
01051 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
01052 {
01053   return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01054 }
01055
01056 #endif /* DUAL_CORE */
01057
01058
01059 /**
01060   * @}
01061   */
01062
01063 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
01064   * @{
01065   */
01066
01067 /**
01068   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
01069   * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
01070   * @param  ExtiLine This parameter can be one of the following values:
01071   *         @arg @ref LL_EXTI_LINE_0
01072   *         @arg @ref LL_EXTI_LINE_1
01073   *         @arg @ref LL_EXTI_LINE_2
01074   *         @arg @ref LL_EXTI_LINE_3
01075   *         @arg @ref LL_EXTI_LINE_4
01076   *         @arg @ref LL_EXTI_LINE_5
01077   *         @arg @ref LL_EXTI_LINE_6
01078   *         @arg @ref LL_EXTI_LINE_7
01079   *         @arg @ref LL_EXTI_LINE_8
01080   *         @arg @ref LL_EXTI_LINE_9
01081   *         @arg @ref LL_EXTI_LINE_10
01082   *         @arg @ref LL_EXTI_LINE_11
01083   *         @arg @ref LL_EXTI_LINE_12
01084   *         @arg @ref LL_EXTI_LINE_13
01085   *         @arg @ref LL_EXTI_LINE_14
01086   *         @arg @ref LL_EXTI_LINE_15
01087   *         @arg @ref LL_EXTI_LINE_16
01088   *         @arg @ref LL_EXTI_LINE_17
01089   *         @arg @ref LL_EXTI_LINE_18
01090   *         @arg @ref LL_EXTI_LINE_19
01091   *         @arg @ref LL_EXTI_LINE_20
01092   *         @arg @ref LL_EXTI_LINE_21
01093   *         @arg @ref LL_EXTI_LINE_22
01094   *         @arg @ref LL_EXTI_LINE_23
01095   *         @arg @ref LL_EXTI_LINE_24
01096   *         @arg @ref LL_EXTI_LINE_25
01097   *         @arg @ref LL_EXTI_LINE_26
01098   *         @arg @ref LL_EXTI_LINE_27
01099   *         @arg @ref LL_EXTI_LINE_28
01100   *         @arg @ref LL_EXTI_LINE_29
01101   *         @arg @ref LL_EXTI_LINE_30
01102   *         @arg @ref LL_EXTI_LINE_31
01103   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01104   * @retval None
01105   */
01106 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
01107 {
01108   SET_BIT(EXTI->EMR1, ExtiLine);
01109 }
01110
01111 /**
01112   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
01113   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
01114   * @param  ExtiLine This parameter can be a combination of the following values:
01115   *         @arg @ref LL_EXTI_LINE_32
01116   *         @arg @ref LL_EXTI_LINE_33
01117   *         @arg @ref LL_EXTI_LINE_34
01118   *         @arg @ref LL_EXTI_LINE_35
01119   *         @arg @ref LL_EXTI_LINE_36
01120   *         @arg @ref LL_EXTI_LINE_37
01121   *         @arg @ref LL_EXTI_LINE_38
01122   *         @arg @ref LL_EXTI_LINE_39
01123   *         @arg @ref LL_EXTI_LINE_40
01124   *         @arg @ref LL_EXTI_LINE_41
01125   *         @arg @ref LL_EXTI_LINE_42
01126   *         @arg @ref LL_EXTI_LINE_43
01127   *         @arg @ref LL_EXTI_LINE_44
01128   *         @arg @ref LL_EXTI_LINE_46
01129   *         @arg @ref LL_EXTI_LINE_47
01130   *         @arg @ref LL_EXTI_LINE_48
01131   *         @arg @ref LL_EXTI_LINE_49
01132   *         @arg @ref LL_EXTI_LINE_50
01133   *         @arg @ref LL_EXTI_LINE_51
01134   *         @arg @ref LL_EXTI_LINE_52
01135   *         @arg @ref LL_EXTI_LINE_53
01136   *         @arg @ref LL_EXTI_LINE_54
01137   *         @arg @ref LL_EXTI_LINE_55
01138   *         @arg @ref LL_EXTI_LINE_56
01139   *         @arg @ref LL_EXTI_LINE_57
01140   *         @arg @ref LL_EXTI_LINE_58
01141   *         @arg @ref LL_EXTI_LINE_59
01142   *         @arg @ref LL_EXTI_LINE_60
01143   *         @arg @ref LL_EXTI_LINE_61
01144   *         @arg @ref LL_EXTI_LINE_62
01145   *         @arg @ref LL_EXTI_LINE_63
01146   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01147   * @retval None
01148   */
01149 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
01150 {
01151   SET_BIT(EXTI->EMR2, ExtiLine);
01152 }
01153
01154 /**
01155   * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
01156   * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
01157   * @param  ExtiLine This parameter can be a combination of the following values:
01158   *         @arg @ref LL_EXTI_LINE_64
01159   *         @arg @ref LL_EXTI_LINE_65
01160   *         @arg @ref LL_EXTI_LINE_66
01161   *         @arg @ref LL_EXTI_LINE_67
01162   *         @arg @ref LL_EXTI_LINE_68
01163   *         @arg @ref LL_EXTI_LINE_69
01164   *         @arg @ref LL_EXTI_LINE_70
01165   *         @arg @ref LL_EXTI_LINE_71
01166   *         @arg @ref LL_EXTI_LINE_72
01167   *         @arg @ref LL_EXTI_LINE_73
01168   *         @arg @ref LL_EXTI_LINE_74
01169   *         @arg @ref LL_EXTI_LINE_75
01170   *         @arg @ref LL_EXTI_LINE_76
01171   *         @arg @ref LL_EXTI_LINE_77
01172   *         @arg @ref LL_EXTI_LINE_78
01173   *         @arg @ref LL_EXTI_LINE_79
01174   *         @arg @ref LL_EXTI_LINE_80
01175   *         @arg @ref LL_EXTI_LINE_82
01176   *         @arg @ref LL_EXTI_LINE_84
01177   *         @arg @ref LL_EXTI_LINE_85
01178   *         @arg @ref LL_EXTI_LINE_86
01179   *         @arg @ref LL_EXTI_LINE_87
01180   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
01184 {
01185   SET_BIT(EXTI->EMR3, ExtiLine);
01186 }
01187
01188 /**
01189   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
01190   * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
01191   * @param  ExtiLine This parameter can be one of the following values:
01192   *         @arg @ref LL_EXTI_LINE_0
01193   *         @arg @ref LL_EXTI_LINE_1
01194   *         @arg @ref LL_EXTI_LINE_2
01195   *         @arg @ref LL_EXTI_LINE_3
01196   *         @arg @ref LL_EXTI_LINE_4
01197   *         @arg @ref LL_EXTI_LINE_5
01198   *         @arg @ref LL_EXTI_LINE_6
01199   *         @arg @ref LL_EXTI_LINE_7
01200   *         @arg @ref LL_EXTI_LINE_8
01201   *         @arg @ref LL_EXTI_LINE_9
01202   *         @arg @ref LL_EXTI_LINE_10
01203   *         @arg @ref LL_EXTI_LINE_11
01204   *         @arg @ref LL_EXTI_LINE_12
01205   *         @arg @ref LL_EXTI_LINE_13
01206   *         @arg @ref LL_EXTI_LINE_14
01207   *         @arg @ref LL_EXTI_LINE_15
01208   *         @arg @ref LL_EXTI_LINE_16
01209   *         @arg @ref LL_EXTI_LINE_17
01210   *         @arg @ref LL_EXTI_LINE_18
01211   *         @arg @ref LL_EXTI_LINE_19
01212   *         @arg @ref LL_EXTI_LINE_20
01213   *         @arg @ref LL_EXTI_LINE_21
01214   *         @arg @ref LL_EXTI_LINE_22
01215   *         @arg @ref LL_EXTI_LINE_23
01216   *         @arg @ref LL_EXTI_LINE_24
01217   *         @arg @ref LL_EXTI_LINE_25
01218   *         @arg @ref LL_EXTI_LINE_26
01219   *         @arg @ref LL_EXTI_LINE_27
01220   *         @arg @ref LL_EXTI_LINE_28
01221   *         @arg @ref LL_EXTI_LINE_29
01222   *         @arg @ref LL_EXTI_LINE_30
01223   *         @arg @ref LL_EXTI_LINE_31
01224   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01225   * @retval None
01226   */
01227 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
01228 {
01229   CLEAR_BIT(EXTI->EMR1, ExtiLine);
01230 }
01231
01232 /**
01233   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
01234   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
01235   * @param  ExtiLine This parameter can be a combination of the following values:
01236   *         @arg @ref LL_EXTI_LINE_32
01237   *         @arg @ref LL_EXTI_LINE_33
01238   *         @arg @ref LL_EXTI_LINE_34
01239   *         @arg @ref LL_EXTI_LINE_35
01240   *         @arg @ref LL_EXTI_LINE_36
01241   *         @arg @ref LL_EXTI_LINE_37
01242   *         @arg @ref LL_EXTI_LINE_38
01243   *         @arg @ref LL_EXTI_LINE_39
01244   *         @arg @ref LL_EXTI_LINE_40
01245   *         @arg @ref LL_EXTI_LINE_41
01246   *         @arg @ref LL_EXTI_LINE_42
01247   *         @arg @ref LL_EXTI_LINE_43
01248   *         @arg @ref LL_EXTI_LINE_44
01249   *         @arg @ref LL_EXTI_LINE_46
01250   *         @arg @ref LL_EXTI_LINE_47
01251   *         @arg @ref LL_EXTI_LINE_48
01252   *         @arg @ref LL_EXTI_LINE_49
01253   *         @arg @ref LL_EXTI_LINE_50
01254   *         @arg @ref LL_EXTI_LINE_51
01255   *         @arg @ref LL_EXTI_LINE_52
01256   *         @arg @ref LL_EXTI_LINE_53
01257   *         @arg @ref LL_EXTI_LINE_54
01258   *         @arg @ref LL_EXTI_LINE_55
01259   *         @arg @ref LL_EXTI_LINE_56
01260   *         @arg @ref LL_EXTI_LINE_57
01261   *         @arg @ref LL_EXTI_LINE_58
01262   *         @arg @ref LL_EXTI_LINE_59
01263   *         @arg @ref LL_EXTI_LINE_60
01264   *         @arg @ref LL_EXTI_LINE_61
01265   *         @arg @ref LL_EXTI_LINE_62
01266   *         @arg @ref LL_EXTI_LINE_63
01267   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01268   * @retval None
01269   */
01270 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
01271 {
01272   CLEAR_BIT(EXTI->EMR2, ExtiLine);
01273 }
01274
01275 /**
01276   * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
01277   * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
01278   * @param  ExtiLine This parameter can be a combination of the following values:
01279   *         @arg @ref LL_EXTI_LINE_64
01280   *         @arg @ref LL_EXTI_LINE_65
01281   *         @arg @ref LL_EXTI_LINE_66
01282   *         @arg @ref LL_EXTI_LINE_67
01283   *         @arg @ref LL_EXTI_LINE_68
01284   *         @arg @ref LL_EXTI_LINE_69
01285   *         @arg @ref LL_EXTI_LINE_70
01286   *         @arg @ref LL_EXTI_LINE_71
01287   *         @arg @ref LL_EXTI_LINE_72
01288   *         @arg @ref LL_EXTI_LINE_73
01289   *         @arg @ref LL_EXTI_LINE_74
01290   *         @arg @ref LL_EXTI_LINE_75
01291   *         @arg @ref LL_EXTI_LINE_76
01292   *         @arg @ref LL_EXTI_LINE_77
01293   *         @arg @ref LL_EXTI_LINE_78
01294   *         @arg @ref LL_EXTI_LINE_79
01295   *         @arg @ref LL_EXTI_LINE_80
01296   *         @arg @ref LL_EXTI_LINE_82
01297   *         @arg @ref LL_EXTI_LINE_84
01298   *         @arg @ref LL_EXTI_LINE_85
01299   *         @arg @ref LL_EXTI_LINE_86
01300   *         @arg @ref LL_EXTI_LINE_87
01301   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01302   * @retval None
01303   */
01304 __STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
01305 {
01306   CLEAR_BIT(EXTI->EMR3, ExtiLine);
01307 }
01308
01309 /**
01310   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
01311   * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
01312   * @param  ExtiLine This parameter can be one of the following values:
01313   *         @arg @ref LL_EXTI_LINE_0
01314   *         @arg @ref LL_EXTI_LINE_1
01315   *         @arg @ref LL_EXTI_LINE_2
01316   *         @arg @ref LL_EXTI_LINE_3
01317   *         @arg @ref LL_EXTI_LINE_4
01318   *         @arg @ref LL_EXTI_LINE_5
01319   *         @arg @ref LL_EXTI_LINE_6
01320   *         @arg @ref LL_EXTI_LINE_7
01321   *         @arg @ref LL_EXTI_LINE_8
01322   *         @arg @ref LL_EXTI_LINE_9
01323   *         @arg @ref LL_EXTI_LINE_10
01324   *         @arg @ref LL_EXTI_LINE_11
01325   *         @arg @ref LL_EXTI_LINE_12
01326   *         @arg @ref LL_EXTI_LINE_13
01327   *         @arg @ref LL_EXTI_LINE_14
01328   *         @arg @ref LL_EXTI_LINE_15
01329   *         @arg @ref LL_EXTI_LINE_16
01330   *         @arg @ref LL_EXTI_LINE_17
01331   *         @arg @ref LL_EXTI_LINE_18
01332   *         @arg @ref LL_EXTI_LINE_19
01333   *         @arg @ref LL_EXTI_LINE_20
01334   *         @arg @ref LL_EXTI_LINE_21
01335   *         @arg @ref LL_EXTI_LINE_22
01336   *         @arg @ref LL_EXTI_LINE_23
01337   *         @arg @ref LL_EXTI_LINE_24
01338   *         @arg @ref LL_EXTI_LINE_25
01339   *         @arg @ref LL_EXTI_LINE_26
01340   *         @arg @ref LL_EXTI_LINE_27
01341   *         @arg @ref LL_EXTI_LINE_28
01342   *         @arg @ref LL_EXTI_LINE_29
01343   *         @arg @ref LL_EXTI_LINE_30
01344   *         @arg @ref LL_EXTI_LINE_31
01345   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01346   * @note   Please check each device line mapping for EXTI Line availability
01347   * @retval State of bit (1 or 0).
01348   */
01349 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
01350 {
01351   return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01352 }
01353
01354 /**
01355   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
01356   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
01357   * @param  ExtiLine This parameter can be a combination of the following values:
01358   *         @arg @ref LL_EXTI_LINE_32
01359   *         @arg @ref LL_EXTI_LINE_33
01360   *         @arg @ref LL_EXTI_LINE_34
01361   *         @arg @ref LL_EXTI_LINE_35
01362   *         @arg @ref LL_EXTI_LINE_36
01363   *         @arg @ref LL_EXTI_LINE_37
01364   *         @arg @ref LL_EXTI_LINE_38
01365   *         @arg @ref LL_EXTI_LINE_39
01366   *         @arg @ref LL_EXTI_LINE_40
01367   *         @arg @ref LL_EXTI_LINE_41
01368   *         @arg @ref LL_EXTI_LINE_42
01369   *         @arg @ref LL_EXTI_LINE_43
01370   *         @arg @ref LL_EXTI_LINE_44
01371   *         @arg @ref LL_EXTI_LINE_46
01372   *         @arg @ref LL_EXTI_LINE_47
01373   *         @arg @ref LL_EXTI_LINE_48
01374   *         @arg @ref LL_EXTI_LINE_49
01375   *         @arg @ref LL_EXTI_LINE_50
01376   *         @arg @ref LL_EXTI_LINE_51
01377   *         @arg @ref LL_EXTI_LINE_52
01378   *         @arg @ref LL_EXTI_LINE_53
01379   *         @arg @ref LL_EXTI_LINE_54
01380   *         @arg @ref LL_EXTI_LINE_55
01381   *         @arg @ref LL_EXTI_LINE_56
01382   *         @arg @ref LL_EXTI_LINE_57
01383   *         @arg @ref LL_EXTI_LINE_58
01384   *         @arg @ref LL_EXTI_LINE_59
01385   *         @arg @ref LL_EXTI_LINE_60
01386   *         @arg @ref LL_EXTI_LINE_61
01387   *         @arg @ref LL_EXTI_LINE_62
01388   *         @arg @ref LL_EXTI_LINE_63
01389   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01390   * @retval State of bit (1 or 0).
01391   */
01392 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
01393 {
01394   return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01395 }
01396
01397 /**
01398   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
01399   * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
01400   * @param  ExtiLine This parameter can be a combination of the following values:
01401   *         @arg @ref LL_EXTI_LINE_64
01402   *         @arg @ref LL_EXTI_LINE_65
01403   *         @arg @ref LL_EXTI_LINE_66
01404   *         @arg @ref LL_EXTI_LINE_67
01405   *         @arg @ref LL_EXTI_LINE_68
01406   *         @arg @ref LL_EXTI_LINE_69
01407   *         @arg @ref LL_EXTI_LINE_70
01408   *         @arg @ref LL_EXTI_LINE_71
01409   *         @arg @ref LL_EXTI_LINE_72
01410   *         @arg @ref LL_EXTI_LINE_73
01411   *         @arg @ref LL_EXTI_LINE_74
01412   *         @arg @ref LL_EXTI_LINE_75
01413   *         @arg @ref LL_EXTI_LINE_76
01414   *         @arg @ref LL_EXTI_LINE_77
01415   *         @arg @ref LL_EXTI_LINE_78
01416   *         @arg @ref LL_EXTI_LINE_79
01417   *         @arg @ref LL_EXTI_LINE_80
01418   *         @arg @ref LL_EXTI_LINE_82
01419   *         @arg @ref LL_EXTI_LINE_84
01420   *         @arg @ref LL_EXTI_LINE_85
01421   *         @arg @ref LL_EXTI_LINE_86
01422   *         @arg @ref LL_EXTI_LINE_87
01423   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01424   * @retval State of bit (1 or 0).
01425   */
01426 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
01427 {
01428   return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01429 }
01430
01431 #if defined(DUAL_CORE)
01432
01433 /**
01434   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
01435   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
01436   * @param  ExtiLine This parameter can be one of the following values:
01437   *         @arg @ref LL_EXTI_LINE_0
01438   *         @arg @ref LL_EXTI_LINE_1
01439   *         @arg @ref LL_EXTI_LINE_2
01440   *         @arg @ref LL_EXTI_LINE_3
01441   *         @arg @ref LL_EXTI_LINE_4
01442   *         @arg @ref LL_EXTI_LINE_5
01443   *         @arg @ref LL_EXTI_LINE_6
01444   *         @arg @ref LL_EXTI_LINE_7
01445   *         @arg @ref LL_EXTI_LINE_8
01446   *         @arg @ref LL_EXTI_LINE_9
01447   *         @arg @ref LL_EXTI_LINE_10
01448   *         @arg @ref LL_EXTI_LINE_11
01449   *         @arg @ref LL_EXTI_LINE_12
01450   *         @arg @ref LL_EXTI_LINE_13
01451   *         @arg @ref LL_EXTI_LINE_14
01452   *         @arg @ref LL_EXTI_LINE_15
01453   *         @arg @ref LL_EXTI_LINE_16
01454   *         @arg @ref LL_EXTI_LINE_17
01455   *         @arg @ref LL_EXTI_LINE_18
01456   *         @arg @ref LL_EXTI_LINE_19
01457   *         @arg @ref LL_EXTI_LINE_20
01458   *         @arg @ref LL_EXTI_LINE_21
01459   *         @arg @ref LL_EXTI_LINE_22
01460   *         @arg @ref LL_EXTI_LINE_23
01461   *         @arg @ref LL_EXTI_LINE_24
01462   *         @arg @ref LL_EXTI_LINE_25
01463   *         @arg @ref LL_EXTI_LINE_26
01464   *         @arg @ref LL_EXTI_LINE_27
01465   *         @arg @ref LL_EXTI_LINE_28
01466   *         @arg @ref LL_EXTI_LINE_29
01467   *         @arg @ref LL_EXTI_LINE_30
01468   *         @arg @ref LL_EXTI_LINE_31
01469   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01470   * @retval None
01471   */
01472 __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
01473 {
01474   SET_BIT(EXTI->C2EMR1, ExtiLine);
01475 }
01476
01477
01478 /**
01479   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
01480   * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
01481   * @param  ExtiLine This parameter can be a combination of the following values:
01482   *         @arg @ref LL_EXTI_LINE_32
01483   *         @arg @ref LL_EXTI_LINE_33
01484   *         @arg @ref LL_EXTI_LINE_34
01485   *         @arg @ref LL_EXTI_LINE_35
01486   *         @arg @ref LL_EXTI_LINE_36
01487   *         @arg @ref LL_EXTI_LINE_37
01488   *         @arg @ref LL_EXTI_LINE_38
01489   *         @arg @ref LL_EXTI_LINE_39
01490   *         @arg @ref LL_EXTI_LINE_40
01491   *         @arg @ref LL_EXTI_LINE_41
01492   *         @arg @ref LL_EXTI_LINE_42
01493   *         @arg @ref LL_EXTI_LINE_43
01494   *         @arg @ref LL_EXTI_LINE_44
01495   *         @arg @ref LL_EXTI_LINE_46
01496   *         @arg @ref LL_EXTI_LINE_47
01497   *         @arg @ref LL_EXTI_LINE_48
01498   *         @arg @ref LL_EXTI_LINE_49
01499   *         @arg @ref LL_EXTI_LINE_50
01500   *         @arg @ref LL_EXTI_LINE_51
01501   *         @arg @ref LL_EXTI_LINE_52
01502   *         @arg @ref LL_EXTI_LINE_53
01503   *         @arg @ref LL_EXTI_LINE_54
01504   *         @arg @ref LL_EXTI_LINE_55
01505   *         @arg @ref LL_EXTI_LINE_56
01506   *         @arg @ref LL_EXTI_LINE_57
01507   *         @arg @ref LL_EXTI_LINE_58
01508   *         @arg @ref LL_EXTI_LINE_59
01509   *         @arg @ref LL_EXTI_LINE_60
01510   *         @arg @ref LL_EXTI_LINE_61
01511   *         @arg @ref LL_EXTI_LINE_62
01512   *         @arg @ref LL_EXTI_LINE_63
01513   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01514   * @retval None
01515   */
01516 __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
01517 {
01518   SET_BIT(EXTI->C2EMR2, ExtiLine);
01519 }
01520
01521 /**
01522   * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
01523   * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95
01524   * @param  ExtiLine This parameter can be a combination of the following values:
01525   *         @arg @ref LL_EXTI_LINE_64
01526   *         @arg @ref LL_EXTI_LINE_65
01527   *         @arg @ref LL_EXTI_LINE_66
01528   *         @arg @ref LL_EXTI_LINE_67
01529   *         @arg @ref LL_EXTI_LINE_68
01530   *         @arg @ref LL_EXTI_LINE_69
01531   *         @arg @ref LL_EXTI_LINE_70
01532   *         @arg @ref LL_EXTI_LINE_71
01533   *         @arg @ref LL_EXTI_LINE_72
01534   *         @arg @ref LL_EXTI_LINE_73
01535   *         @arg @ref LL_EXTI_LINE_74
01536   *         @arg @ref LL_EXTI_LINE_75
01537   *         @arg @ref LL_EXTI_LINE_76
01538   *         @arg @ref LL_EXTI_LINE_77
01539   *         @arg @ref LL_EXTI_LINE_78
01540   *         @arg @ref LL_EXTI_LINE_79
01541   *         @arg @ref LL_EXTI_LINE_80
01542   *         @arg @ref LL_EXTI_LINE_82
01543   *         @arg @ref LL_EXTI_LINE_84
01544   *         @arg @ref LL_EXTI_LINE_85
01545   *         @arg @ref LL_EXTI_LINE_86
01546   *         @arg @ref LL_EXTI_LINE_87
01547   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01548   * @retval None
01549   */
01550 __STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
01551 {
01552   SET_BIT(EXTI->C2EMR3, ExtiLine);
01553 }
01554
01555
01556 /**
01557   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
01558   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
01559   * @param  ExtiLine This parameter can be one of the following values:
01560   *         @arg @ref LL_EXTI_LINE_0
01561   *         @arg @ref LL_EXTI_LINE_1
01562   *         @arg @ref LL_EXTI_LINE_2
01563   *         @arg @ref LL_EXTI_LINE_3
01564   *         @arg @ref LL_EXTI_LINE_4
01565   *         @arg @ref LL_EXTI_LINE_5
01566   *         @arg @ref LL_EXTI_LINE_6
01567   *         @arg @ref LL_EXTI_LINE_7
01568   *         @arg @ref LL_EXTI_LINE_8
01569   *         @arg @ref LL_EXTI_LINE_9
01570   *         @arg @ref LL_EXTI_LINE_10
01571   *         @arg @ref LL_EXTI_LINE_11
01572   *         @arg @ref LL_EXTI_LINE_12
01573   *         @arg @ref LL_EXTI_LINE_13
01574   *         @arg @ref LL_EXTI_LINE_14
01575   *         @arg @ref LL_EXTI_LINE_15
01576   *         @arg @ref LL_EXTI_LINE_16
01577   *         @arg @ref LL_EXTI_LINE_17
01578   *         @arg @ref LL_EXTI_LINE_18
01579   *         @arg @ref LL_EXTI_LINE_19
01580   *         @arg @ref LL_EXTI_LINE_20
01581   *         @arg @ref LL_EXTI_LINE_21
01582   *         @arg @ref LL_EXTI_LINE_22
01583   *         @arg @ref LL_EXTI_LINE_23
01584   *         @arg @ref LL_EXTI_LINE_24
01585   *         @arg @ref LL_EXTI_LINE_25
01586   *         @arg @ref LL_EXTI_LINE_26
01587   *         @arg @ref LL_EXTI_LINE_27
01588   *         @arg @ref LL_EXTI_LINE_28
01589   *         @arg @ref LL_EXTI_LINE_29
01590   *         @arg @ref LL_EXTI_LINE_30
01591   *         @arg @ref LL_EXTI_LINE_31
01592   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01593   * @retval None
01594   */
01595 __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
01596 {
01597   CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
01598 }
01599
01600
01601 /**
01602   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
01603   * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
01604   * @param  ExtiLine This parameter can be a combination of the following values:
01605   *         @arg @ref LL_EXTI_LINE_32
01606   *         @arg @ref LL_EXTI_LINE_33
01607   *         @arg @ref LL_EXTI_LINE_34
01608   *         @arg @ref LL_EXTI_LINE_35
01609   *         @arg @ref LL_EXTI_LINE_36
01610   *         @arg @ref LL_EXTI_LINE_37
01611   *         @arg @ref LL_EXTI_LINE_38
01612   *         @arg @ref LL_EXTI_LINE_39
01613   *         @arg @ref LL_EXTI_LINE_40
01614   *         @arg @ref LL_EXTI_LINE_41
01615   *         @arg @ref LL_EXTI_LINE_42
01616   *         @arg @ref LL_EXTI_LINE_43
01617   *         @arg @ref LL_EXTI_LINE_44
01618   *         @arg @ref LL_EXTI_LINE_46
01619   *         @arg @ref LL_EXTI_LINE_47
01620   *         @arg @ref LL_EXTI_LINE_48
01621   *         @arg @ref LL_EXTI_LINE_49
01622   *         @arg @ref LL_EXTI_LINE_50
01623   *         @arg @ref LL_EXTI_LINE_51
01624   *         @arg @ref LL_EXTI_LINE_52
01625   *         @arg @ref LL_EXTI_LINE_53
01626   *         @arg @ref LL_EXTI_LINE_54
01627   *         @arg @ref LL_EXTI_LINE_55
01628   *         @arg @ref LL_EXTI_LINE_56
01629   *         @arg @ref LL_EXTI_LINE_57
01630   *         @arg @ref LL_EXTI_LINE_58
01631   *         @arg @ref LL_EXTI_LINE_59
01632   *         @arg @ref LL_EXTI_LINE_60
01633   *         @arg @ref LL_EXTI_LINE_61
01634   *         @arg @ref LL_EXTI_LINE_62
01635   *         @arg @ref LL_EXTI_LINE_63
01636   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01637   * @retval None
01638   */
01639 __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
01640 {
01641   CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
01642 }
01643
01644
01645 /**
01646   * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
01647   * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95
01648   * @param  ExtiLine This parameter can be a combination of the following values:
01649   *         @arg @ref LL_EXTI_LINE_64
01650   *         @arg @ref LL_EXTI_LINE_65
01651   *         @arg @ref LL_EXTI_LINE_66
01652   *         @arg @ref LL_EXTI_LINE_67
01653   *         @arg @ref LL_EXTI_LINE_68
01654   *         @arg @ref LL_EXTI_LINE_69
01655   *         @arg @ref LL_EXTI_LINE_70
01656   *         @arg @ref LL_EXTI_LINE_71
01657   *         @arg @ref LL_EXTI_LINE_72
01658   *         @arg @ref LL_EXTI_LINE_73
01659   *         @arg @ref LL_EXTI_LINE_74
01660   *         @arg @ref LL_EXTI_LINE_75
01661   *         @arg @ref LL_EXTI_LINE_76
01662   *         @arg @ref LL_EXTI_LINE_77
01663   *         @arg @ref LL_EXTI_LINE_78
01664   *         @arg @ref LL_EXTI_LINE_79
01665   *         @arg @ref LL_EXTI_LINE_80
01666   *         @arg @ref LL_EXTI_LINE_82
01667   *         @arg @ref LL_EXTI_LINE_84
01668   *         @arg @ref LL_EXTI_LINE_85
01669   *         @arg @ref LL_EXTI_LINE_86
01670   *         @arg @ref LL_EXTI_LINE_87
01671   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01672   * @retval None
01673   */
01674 __STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
01675 {
01676   CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
01677 }
01678
01679
01680 /**
01681   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
01682   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
01683   * @param  ExtiLine This parameter can be one of the following values:
01684   *         @arg @ref LL_EXTI_LINE_0
01685   *         @arg @ref LL_EXTI_LINE_1
01686   *         @arg @ref LL_EXTI_LINE_2
01687   *         @arg @ref LL_EXTI_LINE_3
01688   *         @arg @ref LL_EXTI_LINE_4
01689   *         @arg @ref LL_EXTI_LINE_5
01690   *         @arg @ref LL_EXTI_LINE_6
01691   *         @arg @ref LL_EXTI_LINE_7
01692   *         @arg @ref LL_EXTI_LINE_8
01693   *         @arg @ref LL_EXTI_LINE_9
01694   *         @arg @ref LL_EXTI_LINE_10
01695   *         @arg @ref LL_EXTI_LINE_11
01696   *         @arg @ref LL_EXTI_LINE_12
01697   *         @arg @ref LL_EXTI_LINE_13
01698   *         @arg @ref LL_EXTI_LINE_14
01699   *         @arg @ref LL_EXTI_LINE_15
01700   *         @arg @ref LL_EXTI_LINE_16
01701   *         @arg @ref LL_EXTI_LINE_17
01702   *         @arg @ref LL_EXTI_LINE_18
01703   *         @arg @ref LL_EXTI_LINE_19
01704   *         @arg @ref LL_EXTI_LINE_20
01705   *         @arg @ref LL_EXTI_LINE_21
01706   *         @arg @ref LL_EXTI_LINE_22
01707   *         @arg @ref LL_EXTI_LINE_23
01708   *         @arg @ref LL_EXTI_LINE_24
01709   *         @arg @ref LL_EXTI_LINE_25
01710   *         @arg @ref LL_EXTI_LINE_26
01711   *         @arg @ref LL_EXTI_LINE_27
01712   *         @arg @ref LL_EXTI_LINE_28
01713   *         @arg @ref LL_EXTI_LINE_29
01714   *         @arg @ref LL_EXTI_LINE_30
01715   *         @arg @ref LL_EXTI_LINE_31
01716   *         @arg @ref LL_EXTI_LINE_ALL_0_31
01717   * @note   Please check each device line mapping for EXTI Line availability
01718   * @retval State of bit (1 or 0).
01719   */
01720 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
01721 {
01722   return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01723 }
01724
01725
01726 /**
01727   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
01728   * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
01729   * @param  ExtiLine This parameter can be a combination of the following values:
01730   *         @arg @ref LL_EXTI_LINE_32
01731   *         @arg @ref LL_EXTI_LINE_33
01732   *         @arg @ref LL_EXTI_LINE_34
01733   *         @arg @ref LL_EXTI_LINE_35
01734   *         @arg @ref LL_EXTI_LINE_36
01735   *         @arg @ref LL_EXTI_LINE_37
01736   *         @arg @ref LL_EXTI_LINE_38
01737   *         @arg @ref LL_EXTI_LINE_39
01738   *         @arg @ref LL_EXTI_LINE_40
01739   *         @arg @ref LL_EXTI_LINE_41
01740   *         @arg @ref LL_EXTI_LINE_42
01741   *         @arg @ref LL_EXTI_LINE_43
01742   *         @arg @ref LL_EXTI_LINE_44
01743   *         @arg @ref LL_EXTI_LINE_46
01744   *         @arg @ref LL_EXTI_LINE_47
01745   *         @arg @ref LL_EXTI_LINE_48
01746   *         @arg @ref LL_EXTI_LINE_49
01747   *         @arg @ref LL_EXTI_LINE_50
01748   *         @arg @ref LL_EXTI_LINE_51
01749   *         @arg @ref LL_EXTI_LINE_52
01750   *         @arg @ref LL_EXTI_LINE_53
01751   *         @arg @ref LL_EXTI_LINE_54
01752   *         @arg @ref LL_EXTI_LINE_55
01753   *         @arg @ref LL_EXTI_LINE_56
01754   *         @arg @ref LL_EXTI_LINE_57
01755   *         @arg @ref LL_EXTI_LINE_58
01756   *         @arg @ref LL_EXTI_LINE_59
01757   *         @arg @ref LL_EXTI_LINE_60
01758   *         @arg @ref LL_EXTI_LINE_61
01759   *         @arg @ref LL_EXTI_LINE_62
01760   *         @arg @ref LL_EXTI_LINE_63
01761   *         @arg @ref LL_EXTI_LINE_ALL_32_63
01762   * @retval State of bit (1 or 0).
01763   */
01764 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
01765 {
01766   return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01767 }
01768
01769
01770 /**
01771   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
01772   * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95
01773   * @param  ExtiLine This parameter can be a combination of the following values:
01774   *         @arg @ref LL_EXTI_LINE_64
01775   *         @arg @ref LL_EXTI_LINE_65
01776   *         @arg @ref LL_EXTI_LINE_66
01777   *         @arg @ref LL_EXTI_LINE_67
01778   *         @arg @ref LL_EXTI_LINE_68
01779   *         @arg @ref LL_EXTI_LINE_69
01780   *         @arg @ref LL_EXTI_LINE_70
01781   *         @arg @ref LL_EXTI_LINE_71
01782   *         @arg @ref LL_EXTI_LINE_72
01783   *         @arg @ref LL_EXTI_LINE_73
01784   *         @arg @ref LL_EXTI_LINE_74
01785   *         @arg @ref LL_EXTI_LINE_75
01786   *         @arg @ref LL_EXTI_LINE_76
01787   *         @arg @ref LL_EXTI_LINE_77
01788   *         @arg @ref LL_EXTI_LINE_78
01789   *         @arg @ref LL_EXTI_LINE_79
01790   *         @arg @ref LL_EXTI_LINE_80
01791   *         @arg @ref LL_EXTI_LINE_82
01792   *         @arg @ref LL_EXTI_LINE_84
01793   *         @arg @ref LL_EXTI_LINE_85
01794   *         @arg @ref LL_EXTI_LINE_86
01795   *         @arg @ref LL_EXTI_LINE_87
01796   *         @arg @ref LL_EXTI_LINE_ALL_64_95
01797   * @retval State of bit (1 or 0).
01798   */
01799 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
01800 {
01801   return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
01802 }
01803
01804
01805 #endif /* DUAL_CORE */
01806
01807 /**
01808   * @}
01809   */
01810
01811 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
01812   * @{
01813   */
01814
01815 /**
01816   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
01817   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01818   *       generated on these lines. If a rising edge on a configurable interrupt
01819   *       line occurs during a write operation in the EXTI_RTSR register, the
01820   *       pending bit is not set.
01821   *       Rising and falling edge triggers can be set for
01822   *       the same interrupt line. In this case, both generate a trigger
01823   *       condition.
01824   * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
01825   * @param  ExtiLine This parameter can be a combination of the following values:
01826   *         @arg @ref LL_EXTI_LINE_0
01827   *         @arg @ref LL_EXTI_LINE_1
01828   *         @arg @ref LL_EXTI_LINE_2
01829   *         @arg @ref LL_EXTI_LINE_3
01830   *         @arg @ref LL_EXTI_LINE_4
01831   *         @arg @ref LL_EXTI_LINE_5
01832   *         @arg @ref LL_EXTI_LINE_6
01833   *         @arg @ref LL_EXTI_LINE_7
01834   *         @arg @ref LL_EXTI_LINE_8
01835   *         @arg @ref LL_EXTI_LINE_9
01836   *         @arg @ref LL_EXTI_LINE_10
01837   *         @arg @ref LL_EXTI_LINE_11
01838   *         @arg @ref LL_EXTI_LINE_12
01839   *         @arg @ref LL_EXTI_LINE_13
01840   *         @arg @ref LL_EXTI_LINE_14
01841   *         @arg @ref LL_EXTI_LINE_15
01842   *         @arg @ref LL_EXTI_LINE_16
01843   *         @arg @ref LL_EXTI_LINE_17
01844   *         @arg @ref LL_EXTI_LINE_18
01845   *         @arg @ref LL_EXTI_LINE_19
01846   *         @arg @ref LL_EXTI_LINE_20
01847   *         @arg @ref LL_EXTI_LINE_21
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
01851 {
01852   SET_BIT(EXTI->RTSR1, ExtiLine);
01853
01854 }
01855
01856 /**
01857   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
01858   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01859   *       generated on these lines. If a rising edge on a configurable interrupt
01860   *       line occurs during a write operation in the EXTI_RTSR register, the
01861   *       pending bit is not set.Rising and falling edge triggers can be set for
01862   *       the same interrupt line. In this case, both generate a trigger
01863   *       condition.
01864   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
01865   * @param  ExtiLine This parameter can be a combination of the following values:
01866   *         @arg @ref LL_EXTI_LINE_49
01867   *         @arg @ref LL_EXTI_LINE_51
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
01871 {
01872   SET_BIT(EXTI->RTSR2, ExtiLine);
01873 }
01874
01875 /**
01876   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
01877   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01878   *       generated on these lines. If a rising edge on a configurable interrupt
01879   *       line occurs during a write operation in the EXTI_RTSR register, the
01880   *       pending bit is not set.Rising and falling edge triggers can be set for
01881   *       the same interrupt line. In this case, both generate a trigger
01882   *       condition.
01883   * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
01884   * @param  ExtiLine This parameter can be a combination of the following values:
01885   *         @arg @ref LL_EXTI_LINE_82
01886   *         @arg @ref LL_EXTI_LINE_84
01887   *         @arg @ref LL_EXTI_LINE_85
01888   *         @arg @ref LL_EXTI_LINE_86
01889   * @retval None
01890   */
01891 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
01892 {
01893   SET_BIT(EXTI->RTSR3, ExtiLine);
01894 }
01895
01896 /**
01897   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
01898   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01899   *       generated on these lines. If a rising edge on a configurable interrupt
01900   *       line occurs during a write operation in the EXTI_RTSR register, the
01901   *       pending bit is not set.
01902   *       Rising and falling edge triggers can be set for
01903   *       the same interrupt line. In this case, both generate a trigger
01904   *       condition.
01905   * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
01906   * @param  ExtiLine This parameter can be a combination of the following values:
01907   *         @arg @ref LL_EXTI_LINE_0
01908   *         @arg @ref LL_EXTI_LINE_1
01909   *         @arg @ref LL_EXTI_LINE_2
01910   *         @arg @ref LL_EXTI_LINE_3
01911   *         @arg @ref LL_EXTI_LINE_4
01912   *         @arg @ref LL_EXTI_LINE_5
01913   *         @arg @ref LL_EXTI_LINE_6
01914   *         @arg @ref LL_EXTI_LINE_7
01915   *         @arg @ref LL_EXTI_LINE_8
01916   *         @arg @ref LL_EXTI_LINE_9
01917   *         @arg @ref LL_EXTI_LINE_10
01918   *         @arg @ref LL_EXTI_LINE_11
01919   *         @arg @ref LL_EXTI_LINE_12
01920   *         @arg @ref LL_EXTI_LINE_13
01921   *         @arg @ref LL_EXTI_LINE_14
01922   *         @arg @ref LL_EXTI_LINE_15
01923   *         @arg @ref LL_EXTI_LINE_16
01924   *         @arg @ref LL_EXTI_LINE_17
01925   *         @arg @ref LL_EXTI_LINE_18
01926   *         @arg @ref LL_EXTI_LINE_19
01927   *         @arg @ref LL_EXTI_LINE_20
01928   *         @arg @ref LL_EXTI_LINE_21
01929   * @retval None
01930   */
01931 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
01932 {
01933   CLEAR_BIT(EXTI->RTSR1, ExtiLine);
01934
01935 }
01936
01937 /**
01938   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
01939   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01940   *       generated on these lines. If a rising edge on a configurable interrupt
01941   *       line occurs during a write operation in the EXTI_RTSR register, the
01942   *       pending bit is not set.
01943   *       Rising and falling edge triggers can be set for
01944   *       the same interrupt line. In this case, both generate a trigger
01945   *       condition.
01946   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
01947   * @param  ExtiLine This parameter can be a combination of the following values:
01948   *         @arg @ref LL_EXTI_LINE_49
01949   *         @arg @ref LL_EXTI_LINE_51
01950   * @retval None
01951   */
01952 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
01953 {
01954   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
01955 }
01956
01957 /**
01958   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
01959   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01960   *       generated on these lines. If a rising edge on a configurable interrupt
01961   *       line occurs during a write operation in the EXTI_RTSR register, the
01962   *       pending bit is not set.
01963   *       Rising and falling edge triggers can be set for
01964   *       the same interrupt line. In this case, both generate a trigger
01965   *       condition.
01966   * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
01967   * @param  ExtiLine This parameter can be a combination of the following values:
01968   *         @arg @ref LL_EXTI_LINE_82
01969   *         @arg @ref LL_EXTI_LINE_84
01970   *         @arg @ref LL_EXTI_LINE_85
01971   *         @arg @ref LL_EXTI_LINE_86
01972   * @retval None
01973   */
01974 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
01975 {
01976   CLEAR_BIT(EXTI->RTSR3, ExtiLine);
01977 }
01978
01979 /**
01980   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
01981   * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
01982   * @param  ExtiLine This parameter can be a combination of the following values:
01983   *         @arg @ref LL_EXTI_LINE_0
01984   *         @arg @ref LL_EXTI_LINE_1
01985   *         @arg @ref LL_EXTI_LINE_2
01986   *         @arg @ref LL_EXTI_LINE_3
01987   *         @arg @ref LL_EXTI_LINE_4
01988   *         @arg @ref LL_EXTI_LINE_5
01989   *         @arg @ref LL_EXTI_LINE_6
01990   *         @arg @ref LL_EXTI_LINE_7
01991   *         @arg @ref LL_EXTI_LINE_8
01992   *         @arg @ref LL_EXTI_LINE_9
01993   *         @arg @ref LL_EXTI_LINE_10
01994   *         @arg @ref LL_EXTI_LINE_11
01995   *         @arg @ref LL_EXTI_LINE_12
01996   *         @arg @ref LL_EXTI_LINE_13
01997   *         @arg @ref LL_EXTI_LINE_14
01998   *         @arg @ref LL_EXTI_LINE_15
01999   *         @arg @ref LL_EXTI_LINE_16
02000   *         @arg @ref LL_EXTI_LINE_17
02001   *         @arg @ref LL_EXTI_LINE_18
02002   *         @arg @ref LL_EXTI_LINE_19
02003   *         @arg @ref LL_EXTI_LINE_20
02004   *         @arg @ref LL_EXTI_LINE_21
02005   * @retval State of bit (1 or 0).
02006   */
02007 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
02008 {
02009   return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02010 }
02011
02012
02013 /**
02014   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
02015   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
02016   * @param  ExtiLine This parameter can be a combination of the following values:
02017   *         @arg @ref LL_EXTI_LINE_49
02018   *         @arg @ref LL_EXTI_LINE_51
02019   * @retval State of bit (1 or 0).
02020   */
02021 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
02022 {
02023   return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02024 }
02025
02026 /**
02027   * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
02028   * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
02029   * @param  ExtiLine This parameter can be a combination of the following values:
02030   *         @arg @ref LL_EXTI_LINE_82
02031   *         @arg @ref LL_EXTI_LINE_84
02032   *         @arg @ref LL_EXTI_LINE_85
02033   *         @arg @ref LL_EXTI_LINE_86
02034   * @retval State of bit (1 or 0).
02035   */
02036 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
02037 {
02038   return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02039 }
02040
02041 /**
02042   * @}
02043   */
02044
02045 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
02046   * @{
02047   */
02048
02049 /**
02050   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
02051   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02052   *       generated on these lines. If a falling edge on a configurable interrupt
02053   *       line occurs during a write operation in the EXTI_FTSR register, the
02054   *       pending bit is not set.
02055   *       Rising and falling edge triggers can be set for
02056   *       the same interrupt line. In this case, both generate a trigger
02057   *       condition.
02058   * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
02059   * @param  ExtiLine This parameter can be a combination of the following values:
02060   *         @arg @ref LL_EXTI_LINE_0
02061   *         @arg @ref LL_EXTI_LINE_1
02062   *         @arg @ref LL_EXTI_LINE_2
02063   *         @arg @ref LL_EXTI_LINE_3
02064   *         @arg @ref LL_EXTI_LINE_4
02065   *         @arg @ref LL_EXTI_LINE_5
02066   *         @arg @ref LL_EXTI_LINE_6
02067   *         @arg @ref LL_EXTI_LINE_7
02068   *         @arg @ref LL_EXTI_LINE_8
02069   *         @arg @ref LL_EXTI_LINE_9
02070   *         @arg @ref LL_EXTI_LINE_10
02071   *         @arg @ref LL_EXTI_LINE_11
02072   *         @arg @ref LL_EXTI_LINE_12
02073   *         @arg @ref LL_EXTI_LINE_13
02074   *         @arg @ref LL_EXTI_LINE_14
02075   *         @arg @ref LL_EXTI_LINE_15
02076   *         @arg @ref LL_EXTI_LINE_16
02077   *         @arg @ref LL_EXTI_LINE_18
02078   *         @arg @ref LL_EXTI_LINE_19
02079   *         @arg @ref LL_EXTI_LINE_20
02080   *         @arg @ref LL_EXTI_LINE_21
02081   * @note   Please check each device line mapping for EXTI Line availability
02082   * @retval None
02083   */
02084 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
02085 {
02086   SET_BIT(EXTI->FTSR1, ExtiLine);
02087 }
02088
02089 /**
02090   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
02091   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02092   *       generated on these lines. If a Falling edge on a configurable interrupt
02093   *       line occurs during a write operation in the EXTI_FTSR register, the
02094   *       pending bit is not set.
02095   *       Rising and falling edge triggers can be set for
02096   *       the same interrupt line. In this case, both generate a trigger
02097   *       condition.
02098   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
02099   * @param  ExtiLine This parameter can be a combination of the following values:
02100   *         @arg @ref LL_EXTI_LINE_49
02101   *         @arg @ref LL_EXTI_LINE_51
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
02105 {
02106   SET_BIT(EXTI->FTSR2, ExtiLine);
02107 }
02108
02109 /**
02110   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
02111   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02112   *       generated on these lines. If a Falling edge on a configurable interrupt
02113   *       line occurs during a write operation in the EXTI_FTSR register, the
02114   *       pending bit is not set.
02115   *       Rising and falling edge triggers can be set for
02116   *       the same interrupt line. In this case, both generate a trigger
02117   *       condition.
02118   * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
02119   * @param  ExtiLine This parameter can be a combination of the following values:
02120   *         @arg @ref LL_EXTI_LINE_82
02121   *         @arg @ref LL_EXTI_LINE_84
02122   *         @arg @ref LL_EXTI_LINE_85
02123   *         @arg @ref LL_EXTI_LINE_86
02124   * @retval None
02125   */
02126 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
02127 {
02128   SET_BIT(EXTI->FTSR3, ExtiLine);
02129 }
02130
02131
02132 /**
02133   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
02134   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02135   *       generated on these lines. If a Falling edge on a configurable interrupt
02136   *       line occurs during a write operation in the EXTI_FTSR register, the
02137   *       pending bit is not set.
02138   *       Rising and falling edge triggers can be set for the same interrupt line.
02139   *       In this case, both generate a trigger condition.
02140   * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
02141   * @param  ExtiLine This parameter can be a combination of the following values:
02142   *         @arg @ref LL_EXTI_LINE_0
02143   *         @arg @ref LL_EXTI_LINE_1
02144   *         @arg @ref LL_EXTI_LINE_2
02145   *         @arg @ref LL_EXTI_LINE_3
02146   *         @arg @ref LL_EXTI_LINE_4
02147   *         @arg @ref LL_EXTI_LINE_5
02148   *         @arg @ref LL_EXTI_LINE_6
02149   *         @arg @ref LL_EXTI_LINE_7
02150   *         @arg @ref LL_EXTI_LINE_8
02151   *         @arg @ref LL_EXTI_LINE_9
02152   *         @arg @ref LL_EXTI_LINE_10
02153   *         @arg @ref LL_EXTI_LINE_11
02154   *         @arg @ref LL_EXTI_LINE_12
02155   *         @arg @ref LL_EXTI_LINE_13
02156   *         @arg @ref LL_EXTI_LINE_14
02157   *         @arg @ref LL_EXTI_LINE_15
02158   *         @arg @ref LL_EXTI_LINE_16
02159   *         @arg @ref LL_EXTI_LINE_18
02160   *         @arg @ref LL_EXTI_LINE_19
02161   *         @arg @ref LL_EXTI_LINE_20
02162   *         @arg @ref LL_EXTI_LINE_21
02163   * @note   Please check each device line mapping for EXTI Line availability
02164   * @retval None
02165   */
02166 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
02167 {
02168   CLEAR_BIT(EXTI->FTSR1, ExtiLine);
02169 }
02170
02171 /**
02172   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
02173   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02174   *       generated on these lines. If a Falling edge on a configurable interrupt
02175   *       line occurs during a write operation in the EXTI_FTSR register, the
02176   *       pending bit is not set.
02177   *       Rising and falling edge triggers can be set for the same interrupt line.
02178   *       In this case, both generate a trigger condition.
02179   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
02180   * @param  ExtiLine This parameter can be a combination of the following values:
02181   *         @arg @ref LL_EXTI_LINE_49
02182   *         @arg @ref LL_EXTI_LINE_51
02183   * @retval None
02184   */
02185 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
02186 {
02187   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
02188 }
02189
02190 /**
02191   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
02192   * @note The configurable wakeup lines are edge-triggered. No glitch must be
02193   *       generated on these lines. If a Falling edge on a configurable interrupt
02194   *       line occurs during a write operation in the EXTI_FTSR register, the
02195   *       pending bit is not set.
02196   *       Rising and falling edge triggers can be set for the same interrupt line.
02197   *       In this case, both generate a trigger condition.
02198   * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
02199   * @param  ExtiLine This parameter can be a combination of the following values:
02200   *         @arg @ref LL_EXTI_LINE_82
02201   *         @arg @ref LL_EXTI_LINE_84
02202   *         @arg @ref LL_EXTI_LINE_85
02203   *         @arg @ref LL_EXTI_LINE_86
02204   * @retval None
02205   */
02206 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
02207 {
02208   CLEAR_BIT(EXTI->FTSR3, ExtiLine);
02209 }
02210
02211
02212 /**
02213   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
02214   * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
02215   * @param  ExtiLine This parameter can be a combination of the following values:
02216   *         @arg @ref LL_EXTI_LINE_0
02217   *         @arg @ref LL_EXTI_LINE_1
02218   *         @arg @ref LL_EXTI_LINE_2
02219   *         @arg @ref LL_EXTI_LINE_3
02220   *         @arg @ref LL_EXTI_LINE_4
02221   *         @arg @ref LL_EXTI_LINE_5
02222   *         @arg @ref LL_EXTI_LINE_6
02223   *         @arg @ref LL_EXTI_LINE_7
02224   *         @arg @ref LL_EXTI_LINE_8
02225   *         @arg @ref LL_EXTI_LINE_9
02226   *         @arg @ref LL_EXTI_LINE_10
02227   *         @arg @ref LL_EXTI_LINE_11
02228   *         @arg @ref LL_EXTI_LINE_12
02229   *         @arg @ref LL_EXTI_LINE_13
02230   *         @arg @ref LL_EXTI_LINE_14
02231   *         @arg @ref LL_EXTI_LINE_15
02232   *         @arg @ref LL_EXTI_LINE_16
02233   *         @arg @ref LL_EXTI_LINE_18
02234   *         @arg @ref LL_EXTI_LINE_19
02235   *         @arg @ref LL_EXTI_LINE_20
02236   *         @arg @ref LL_EXTI_LINE_21
02237   * @note   Please check each device line mapping for EXTI Line availability
02238   * @retval State of bit (1 or 0).
02239   */
02240 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
02241 {
02242   return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02243 }
02244
02245 /**
02246   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
02247   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
02248   * @param  ExtiLine This parameter can be a combination of the following values:
02249   *         @arg @ref LL_EXTI_LINE_49
02250   *         @arg @ref LL_EXTI_LINE_51
02251   * @retval State of bit (1 or 0).
02252   */
02253 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
02254 {
02255   return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02256 }
02257
02258 /**
02259   * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
02260   * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
02261   * @param  ExtiLine This parameter can be a combination of the following values:
02262   *         @arg @ref LL_EXTI_LINE_82
02263   *         @arg @ref LL_EXTI_LINE_84
02264   *         @arg @ref LL_EXTI_LINE_85
02265   *         @arg @ref LL_EXTI_LINE_86
02266   * @retval State of bit (1 or 0).
02267   */
02268 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
02269 {
02270   return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02271 }
02272
02273
02274 /**
02275   * @}
02276   */
02277
02278 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
02279   * @{
02280   */
02281
02282 /**
02283   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
02284   * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to
02285   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
02286   *       resulting in an interrupt request generation.
02287   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
02288   *       register (by writing a 1 into the bit)
02289   * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
02290   * @param  ExtiLine This parameter can be a combination of the following values:
02291   *         @arg @ref LL_EXTI_LINE_0
02292   *         @arg @ref LL_EXTI_LINE_1
02293   *         @arg @ref LL_EXTI_LINE_2
02294   *         @arg @ref LL_EXTI_LINE_3
02295   *         @arg @ref LL_EXTI_LINE_4
02296   *         @arg @ref LL_EXTI_LINE_5
02297   *         @arg @ref LL_EXTI_LINE_6
02298   *         @arg @ref LL_EXTI_LINE_7
02299   *         @arg @ref LL_EXTI_LINE_8
02300   *         @arg @ref LL_EXTI_LINE_9
02301   *         @arg @ref LL_EXTI_LINE_10
02302   *         @arg @ref LL_EXTI_LINE_11
02303   *         @arg @ref LL_EXTI_LINE_12
02304   *         @arg @ref LL_EXTI_LINE_13
02305   *         @arg @ref LL_EXTI_LINE_14
02306   *         @arg @ref LL_EXTI_LINE_15
02307   *         @arg @ref LL_EXTI_LINE_16
02308   *         @arg @ref LL_EXTI_LINE_18
02309   *         @arg @ref LL_EXTI_LINE_19
02310   *         @arg @ref LL_EXTI_LINE_20
02311   *         @arg @ref LL_EXTI_LINE_21
02312   * @note   Please check each device line mapping for EXTI Line availability
02313   * @retval None
02314   */
02315 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
02316 {
02317   SET_BIT(EXTI->SWIER1, ExtiLine);
02318 }
02319
02320 /**
02321   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
02322   * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
02323   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
02324   *       resulting in an interrupt request generation.
02325   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
02326   *       register (by writing a 1 into the bit)
02327   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
02328   * @param  ExtiLine This parameter can be a combination of the following values:
02329   *         @arg @ref LL_EXTI_LINE_49
02330   *         @arg @ref LL_EXTI_LINE_51
02331   * @retval None
02332   */
02333 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
02334 {
02335   SET_BIT(EXTI->SWIER2, ExtiLine);
02336 }
02337
02338 /**
02339   * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
02340   * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
02341   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
02342   *       resulting in an interrupt request generation.
02343   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
02344   *       register (by writing a 1 into the bit)
02345   * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95
02346   * @param  ExtiLine This parameter can be a combination of the following values:
02347   *         @arg @ref LL_EXTI_LINE_82
02348   *         @arg @ref LL_EXTI_LINE_84
02349   *         @arg @ref LL_EXTI_LINE_85
02350   *         @arg @ref LL_EXTI_LINE_86
02351   * @retval None
02352   */
02353 __STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
02354 {
02355   SET_BIT(EXTI->SWIER3, ExtiLine);
02356 }
02357
02358
02359 /**
02360   * @}
02361   */
02362
02363 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
02364   * @{
02365   */
02366
02367 /**
02368   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
02369   * @note This bit is set when the selected edge event arrives on the interrupt
02370   *       line. This bit is cleared by writing a 1 to the bit.
02371   * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
02372   * @param  ExtiLine This parameter can be a combination of the following values:
02373   *         @arg @ref LL_EXTI_LINE_0
02374   *         @arg @ref LL_EXTI_LINE_1
02375   *         @arg @ref LL_EXTI_LINE_2
02376   *         @arg @ref LL_EXTI_LINE_3
02377   *         @arg @ref LL_EXTI_LINE_4
02378   *         @arg @ref LL_EXTI_LINE_5
02379   *         @arg @ref LL_EXTI_LINE_6
02380   *         @arg @ref LL_EXTI_LINE_7
02381   *         @arg @ref LL_EXTI_LINE_8
02382   *         @arg @ref LL_EXTI_LINE_9
02383   *         @arg @ref LL_EXTI_LINE_10
02384   *         @arg @ref LL_EXTI_LINE_11
02385   *         @arg @ref LL_EXTI_LINE_12
02386   *         @arg @ref LL_EXTI_LINE_13
02387   *         @arg @ref LL_EXTI_LINE_14
02388   *         @arg @ref LL_EXTI_LINE_15
02389   *         @arg @ref LL_EXTI_LINE_16
02390   *         @arg @ref LL_EXTI_LINE_17
02391   *         @arg @ref LL_EXTI_LINE_18
02392   *         @arg @ref LL_EXTI_LINE_19
02393   *         @arg @ref LL_EXTI_LINE_20
02394   *         @arg @ref LL_EXTI_LINE_21
02395   *         @arg @ref LL_EXTI_LINE_ALL_0_31
02396   * @retval State of bit (1 or 0).
02397   */
02398 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
02399 {
02400   return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02401 }
02402
02403 /**
02404   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
02405   * @note This bit is set when the selected edge event arrives on the interrupt
02406   *       line. This bit is cleared by writing a 1 to the bit.
02407   * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
02408   * @param  ExtiLine This parameter can be a combination of the following values:
02409   *         @arg @ref LL_EXTI_LINE_49
02410   *         @arg @ref LL_EXTI_LINE_51
02411   *         @arg @ref LL_EXTI_LINE_ALL_32_63
02412   * @retval State of bit (1 or 0).
02413   */
02414 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
02415 {
02416   return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02417 }
02418
02419 /**
02420   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95
02421   * @note This bit is set when the selected edge event arrives on the interrupt
02422   *       line. This bit is cleared by writing a 1 to the bit.
02423   * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95
02424   * @param  ExtiLine This parameter can be a combination of the following values:
02425   *         @arg @ref LL_EXTI_LINE_82
02426   *         @arg @ref LL_EXTI_LINE_84
02427   *         @arg @ref LL_EXTI_LINE_85
02428   *         @arg @ref LL_EXTI_LINE_86
02429   *         @arg @ref LL_EXTI_LINE_ALL_64_95
02430   * @retval State of bit (1 or 0).
02431   */
02432 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
02433 {
02434   return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02435 }
02436
02437
02438 /**
02439   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
02440   * @note This bit is set when the selected edge event arrives on the interrupt
02441   *       line. This bit is cleared by writing a 1 to the bit.
02442   * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
02443   * @param  ExtiLine This parameter can be a combination of the following values:
02444   *         @arg @ref LL_EXTI_LINE_0
02445   *         @arg @ref LL_EXTI_LINE_1
02446   *         @arg @ref LL_EXTI_LINE_2
02447   *         @arg @ref LL_EXTI_LINE_3
02448   *         @arg @ref LL_EXTI_LINE_4
02449   *         @arg @ref LL_EXTI_LINE_5
02450   *         @arg @ref LL_EXTI_LINE_6
02451   *         @arg @ref LL_EXTI_LINE_7
02452   *         @arg @ref LL_EXTI_LINE_8
02453   *         @arg @ref LL_EXTI_LINE_9
02454   *         @arg @ref LL_EXTI_LINE_10
02455   *         @arg @ref LL_EXTI_LINE_11
02456   *         @arg @ref LL_EXTI_LINE_12
02457   *         @arg @ref LL_EXTI_LINE_13
02458   *         @arg @ref LL_EXTI_LINE_14
02459   *         @arg @ref LL_EXTI_LINE_15
02460   *         @arg @ref LL_EXTI_LINE_16
02461   *         @arg @ref LL_EXTI_LINE_17
02462   *         @arg @ref LL_EXTI_LINE_18
02463   *         @arg @ref LL_EXTI_LINE_19
02464   *         @arg @ref LL_EXTI_LINE_20
02465   *         @arg @ref LL_EXTI_LINE_21
02466   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02467   */
02468 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
02469 {
02470   return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
02471 }
02472
02473
02474 /**
02475   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
02476   * @note This bit is set when the selected edge event arrives on the interrupt
02477   *       line. This bit is cleared by writing a 1 to the bit.
02478   * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
02479   * @param  ExtiLine This parameter can be a combination of the following values:
02480   *         @arg @ref LL_EXTI_LINE_49
02481   *         @arg @ref LL_EXTI_LINE_51
02482   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02483   */
02484 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
02485 {
02486   return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
02487 }
02488
02489
02490 /**
02491   * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95
02492   * @note This bit is set when the selected edge event arrives on the interrupt
02493   *       line. This bit is cleared by writing a 1 to the bit.
02494   * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95
02495   * @param  ExtiLine This parameter can be a combination of the following values:
02496   *         @arg @ref LL_EXTI_LINE_82
02497   *         @arg @ref LL_EXTI_LINE_84
02498   *         @arg @ref LL_EXTI_LINE_85
02499   *         @arg @ref LL_EXTI_LINE_86
02500   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02501   */
02502 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
02503 {
02504   return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));
02505 }
02506
02507 /**
02508   * @brief  Clear ExtLine Flags for Lines in range 0 to 31
02509   * @note This bit is set when the selected edge event arrives on the interrupt
02510   *       line. This bit is cleared by writing a 1 to the bit.
02511   * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
02512   * @param  ExtiLine This parameter can be a combination of the following values:
02513   *         @arg @ref LL_EXTI_LINE_0
02514   *         @arg @ref LL_EXTI_LINE_1
02515   *         @arg @ref LL_EXTI_LINE_2
02516   *         @arg @ref LL_EXTI_LINE_3
02517   *         @arg @ref LL_EXTI_LINE_4
02518   *         @arg @ref LL_EXTI_LINE_5
02519   *         @arg @ref LL_EXTI_LINE_6
02520   *         @arg @ref LL_EXTI_LINE_7
02521   *         @arg @ref LL_EXTI_LINE_8
02522   *         @arg @ref LL_EXTI_LINE_9
02523   *         @arg @ref LL_EXTI_LINE_10
02524   *         @arg @ref LL_EXTI_LINE_11
02525   *         @arg @ref LL_EXTI_LINE_12
02526   *         @arg @ref LL_EXTI_LINE_13
02527   *         @arg @ref LL_EXTI_LINE_14
02528   *         @arg @ref LL_EXTI_LINE_15
02529   *         @arg @ref LL_EXTI_LINE_16
02530   *         @arg @ref LL_EXTI_LINE_17
02531   *         @arg @ref LL_EXTI_LINE_18
02532   *         @arg @ref LL_EXTI_LINE_19
02533   *         @arg @ref LL_EXTI_LINE_20
02534   *         @arg @ref LL_EXTI_LINE_21
02535   * @retval None
02536   */
02537 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
02538 {
02539   WRITE_REG(EXTI->PR1, ExtiLine);
02540 }
02541
02542 /**
02543   * @brief  Clear ExtLine Flags for Lines in range 32 to 63
02544   * @note This bit is set when the selected edge event arrives on the interrupt
02545   *       line. This bit is cleared by writing a 1 to the bit.
02546   * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
02547   * @param  ExtiLine This parameter can be a combination of the following values:
02548   *         @arg @ref LL_EXTI_LINE_49
02549   *         @arg @ref LL_EXTI_LINE_51
02550   * @retval None
02551   */
02552 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
02553 {
02554   WRITE_REG(EXTI->PR2, ExtiLine);
02555 }
02556
02557 /**
02558   * @brief  Clear ExtLine Flags for Lines in range 64 to 95
02559   * @note This bit is set when the selected edge event arrives on the interrupt
02560   *       line. This bit is cleared by writing a 1 to the bit.
02561   * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95
02562   * @param  ExtiLine This parameter can be a combination of the following values:
02563   *         @arg @ref LL_EXTI_LINE_82
02564   *         @arg @ref LL_EXTI_LINE_84
02565   *         @arg @ref LL_EXTI_LINE_85
02566   *         @arg @ref LL_EXTI_LINE_86
02567   * @retval None
02568   */
02569 __STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
02570 {
02571   WRITE_REG(EXTI->PR3, ExtiLine);
02572 }
02573
02574 #if defined(DUAL_CORE)
02575
02576 /**
02577   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
02578   * @note This bit is set when the selected edge event arrives on the interrupt
02579   *       line. This bit is cleared by writing a 1 to the bit.
02580   * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31
02581   * @param  ExtiLine This parameter can be a combination of the following values:
02582   *         @arg @ref LL_EXTI_LINE_0
02583   *         @arg @ref LL_EXTI_LINE_1
02584   *         @arg @ref LL_EXTI_LINE_2
02585   *         @arg @ref LL_EXTI_LINE_3
02586   *         @arg @ref LL_EXTI_LINE_4
02587   *         @arg @ref LL_EXTI_LINE_5
02588   *         @arg @ref LL_EXTI_LINE_6
02589   *         @arg @ref LL_EXTI_LINE_7
02590   *         @arg @ref LL_EXTI_LINE_8
02591   *         @arg @ref LL_EXTI_LINE_9
02592   *         @arg @ref LL_EXTI_LINE_10
02593   *         @arg @ref LL_EXTI_LINE_11
02594   *         @arg @ref LL_EXTI_LINE_12
02595   *         @arg @ref LL_EXTI_LINE_13
02596   *         @arg @ref LL_EXTI_LINE_14
02597   *         @arg @ref LL_EXTI_LINE_15
02598   *         @arg @ref LL_EXTI_LINE_16
02599   *         @arg @ref LL_EXTI_LINE_17
02600   *         @arg @ref LL_EXTI_LINE_18
02601   *         @arg @ref LL_EXTI_LINE_19
02602   *         @arg @ref LL_EXTI_LINE_20
02603   *         @arg @ref LL_EXTI_LINE_21
02604   *         @arg @ref LL_EXTI_LINE_ALL_0_31
02605   * @retval State of bit (1 or 0).
02606   */
02607 __STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
02608 {
02609   return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02610 }
02611
02612 /**
02613   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2
02614   * @note This bit is set when the selected edge event arrives on the interrupt
02615   *       line. This bit is cleared by writing a 1 to the bit.
02616   * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63
02617   * @param  ExtiLine This parameter can be a combination of the following values:
02618   *         @arg @ref LL_EXTI_LINE_49
02619   *         @arg @ref LL_EXTI_LINE_51
02620   *         @arg @ref LL_EXTI_LINE_ALL_32_63
02621   * @retval State of bit (1 or 0).
02622   */
02623 __STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
02624 {
02625   return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02626 }
02627
02628 /**
02629   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2
02630   * @note This bit is set when the selected edge event arrives on the interrupt
02631   *       line. This bit is cleared by writing a 1 to the bit.
02632   * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95
02633   * @param  ExtiLine This parameter can be a combination of the following values:
02634   *         @arg @ref LL_EXTI_LINE_82
02635   *         @arg @ref LL_EXTI_LINE_84
02636   *         @arg @ref LL_EXTI_LINE_85
02637   *         @arg @ref LL_EXTI_LINE_86
02638   *         @arg @ref LL_EXTI_LINE_ALL_64_95
02639   * @retval State of bit (1 or 0).
02640   */
02641 __STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
02642 {
02643   return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02644 }
02645
02646 /**
02647   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
02648   * @note This bit is set when the selected edge event arrives on the interrupt
02649   *       line. This bit is cleared by writing a 1 to the bit.
02650   * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31
02651   * @param  ExtiLine This parameter can be a combination of the following values:
02652   *         @arg @ref LL_EXTI_LINE_0
02653   *         @arg @ref LL_EXTI_LINE_1
02654   *         @arg @ref LL_EXTI_LINE_2
02655   *         @arg @ref LL_EXTI_LINE_3
02656   *         @arg @ref LL_EXTI_LINE_4
02657   *         @arg @ref LL_EXTI_LINE_5
02658   *         @arg @ref LL_EXTI_LINE_6
02659   *         @arg @ref LL_EXTI_LINE_7
02660   *         @arg @ref LL_EXTI_LINE_8
02661   *         @arg @ref LL_EXTI_LINE_9
02662   *         @arg @ref LL_EXTI_LINE_10
02663   *         @arg @ref LL_EXTI_LINE_11
02664   *         @arg @ref LL_EXTI_LINE_12
02665   *         @arg @ref LL_EXTI_LINE_13
02666   *         @arg @ref LL_EXTI_LINE_14
02667   *         @arg @ref LL_EXTI_LINE_15
02668   *         @arg @ref LL_EXTI_LINE_16
02669   *         @arg @ref LL_EXTI_LINE_17
02670   *         @arg @ref LL_EXTI_LINE_18
02671   *         @arg @ref LL_EXTI_LINE_19
02672   *         @arg @ref LL_EXTI_LINE_20
02673   *         @arg @ref LL_EXTI_LINE_21
02674   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02675   */
02676 __STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
02677 {
02678   return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
02679 }
02680
02681 /**
02682   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2
02683   * @note This bit is set when the selected edge event arrives on the interrupt
02684   *       line. This bit is cleared by writing a 1 to the bit.
02685   * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63
02686   * @param  ExtiLine This parameter can be a combination of the following values:
02687   *         @arg @ref LL_EXTI_LINE_49
02688   *         @arg @ref LL_EXTI_LINE_51
02689   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02690   */
02691 __STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
02692 {
02693   return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
02694 }
02695
02696
02697 /**
02698   * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2
02699   * @note This bit is set when the selected edge event arrives on the interrupt
02700   *       line. This bit is cleared by writing a 1 to the bit.
02701   * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95
02702   * @param  ExtiLine This parameter can be a combination of the following values:
02703   *         @arg @ref LL_EXTI_LINE_82
02704   *         @arg @ref LL_EXTI_LINE_84
02705   *         @arg @ref LL_EXTI_LINE_85
02706   *         @arg @ref LL_EXTI_LINE_86
02707   * @retval @note This bit is set when the selected edge event arrives on the interrupt
02708   */
02709 __STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
02710 {
02711   return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
02712 }
02713 /**
02714   * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
02715   * @note This bit is set when the selected edge event arrives on the interrupt
02716   *       line. This bit is cleared by writing a 1 to the bit.
02717   * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31
02718   * @param  ExtiLine This parameter can be a combination of the following values:
02719   *         @arg @ref LL_EXTI_LINE_0
02720   *         @arg @ref LL_EXTI_LINE_1
02721   *         @arg @ref LL_EXTI_LINE_2
02722   *         @arg @ref LL_EXTI_LINE_3
02723   *         @arg @ref LL_EXTI_LINE_4
02724   *         @arg @ref LL_EXTI_LINE_5
02725   *         @arg @ref LL_EXTI_LINE_6
02726   *         @arg @ref LL_EXTI_LINE_7
02727   *         @arg @ref LL_EXTI_LINE_8
02728   *         @arg @ref LL_EXTI_LINE_9
02729   *         @arg @ref LL_EXTI_LINE_10
02730   *         @arg @ref LL_EXTI_LINE_11
02731   *         @arg @ref LL_EXTI_LINE_12
02732   *         @arg @ref LL_EXTI_LINE_13
02733   *         @arg @ref LL_EXTI_LINE_14
02734   *         @arg @ref LL_EXTI_LINE_15
02735   *         @arg @ref LL_EXTI_LINE_16
02736   *         @arg @ref LL_EXTI_LINE_17
02737   *         @arg @ref LL_EXTI_LINE_18
02738   *         @arg @ref LL_EXTI_LINE_19
02739   *         @arg @ref LL_EXTI_LINE_20
02740   *         @arg @ref LL_EXTI_LINE_21
02741   * @retval None
02742   */
02743 __STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
02744 {
02745   WRITE_REG(EXTI->C2PR1, ExtiLine);
02746 }
02747
02748 /**
02749   * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
02750   * @note This bit is set when the selected edge event arrives on the interrupt
02751   *       line. This bit is cleared by writing a 1 to the bit.
02752   * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63
02753   * @param  ExtiLine This parameter can be a combination of the following values:
02754   *         @arg @ref LL_EXTI_LINE_49
02755   *         @arg @ref LL_EXTI_LINE_51
02756   * @retval None
02757   */
02758 __STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
02759 {
02760   WRITE_REG(EXTI->C2PR2, ExtiLine);
02761 }
02762
02763 /**
02764   * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
02765   * @note This bit is set when the selected edge event arrives on the interrupt
02766   *       line. This bit is cleared by writing a 1 to the bit.
02767   * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95
02768   * @param  ExtiLine This parameter can be a combination of the following values:
02769   *         @arg @ref LL_EXTI_LINE_82
02770   *         @arg @ref LL_EXTI_LINE_84
02771   *         @arg @ref LL_EXTI_LINE_85
02772   *         @arg @ref LL_EXTI_LINE_86
02773   * @retval None
02774   */
02775 __STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
02776 {
02777   WRITE_REG(EXTI->C2PR3, ExtiLine);
02778 }
02779
02780 #endif /* DUAL_CORE */
02781
02782 /**
02783   * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
02784   * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31
02785   * @param  ExtiLine This parameter can be one of the following values:
02786   *         @arg @ref LL_EXTI_LINE_0
02787   *         @arg @ref LL_EXTI_LINE_1
02788   *         @arg @ref LL_EXTI_LINE_2
02789   *         @arg @ref LL_EXTI_LINE_3
02790   *         @arg @ref LL_EXTI_LINE_4
02791   *         @arg @ref LL_EXTI_LINE_5
02792   *         @arg @ref LL_EXTI_LINE_6
02793   *         @arg @ref LL_EXTI_LINE_7
02794   *         @arg @ref LL_EXTI_LINE_8
02795   *         @arg @ref LL_EXTI_LINE_9
02796   *         @arg @ref LL_EXTI_LINE_10
02797   *         @arg @ref LL_EXTI_LINE_11
02798   *         @arg @ref LL_EXTI_LINE_12
02799   *         @arg @ref LL_EXTI_LINE_13
02800   *         @arg @ref LL_EXTI_LINE_14
02801   *         @arg @ref LL_EXTI_LINE_15
02802   *         @arg @ref LL_EXTI_LINE_19
02803   *         @arg @ref LL_EXTI_LINE_20
02804   *         @arg @ref LL_EXTI_LINE_21
02805   *         @arg @ref LL_EXTI_LINE_25
02806   * @retval None
02807   */
02808 __STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)
02809 {
02810   SET_BIT(EXTI->D3PMR1, ExtiLine);
02811 }
02812
02813 /**
02814   * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63
02815   * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63
02816   * @param  ExtiLine This parameter can be one of the following values:
02817   *         @arg @ref LL_EXTI_LINE_34
02818   *         @arg @ref LL_EXTI_LINE_35
02819   *         @arg @ref LL_EXTI_LINE_41
02820   *         @arg @ref LL_EXTI_LINE_48
02821   *         @arg @ref LL_EXTI_LINE_49
02822   *         @arg @ref LL_EXTI_LINE_50
02823   *         @arg @ref LL_EXTI_LINE_51
02824   *         @arg @ref LL_EXTI_LINE_52
02825   *         @arg @ref LL_EXTI_LINE_53
02826   * @retval None
02827   */
02828 __STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)
02829 {
02830   SET_BIT(EXTI->D3PMR2, ExtiLine);
02831 }
02832
02833 /**
02834   * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31
02835   * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31
02836   * @param  ExtiLine This parameter can be one of the following values:
02837   *         @arg @ref LL_EXTI_LINE_0
02838   *         @arg @ref LL_EXTI_LINE_1
02839   *         @arg @ref LL_EXTI_LINE_2
02840   *         @arg @ref LL_EXTI_LINE_3
02841   *         @arg @ref LL_EXTI_LINE_4
02842   *         @arg @ref LL_EXTI_LINE_5
02843   *         @arg @ref LL_EXTI_LINE_6
02844   *         @arg @ref LL_EXTI_LINE_7
02845   *         @arg @ref LL_EXTI_LINE_8
02846   *         @arg @ref LL_EXTI_LINE_9
02847   *         @arg @ref LL_EXTI_LINE_10
02848   *         @arg @ref LL_EXTI_LINE_11
02849   *         @arg @ref LL_EXTI_LINE_12
02850   *         @arg @ref LL_EXTI_LINE_13
02851   *         @arg @ref LL_EXTI_LINE_14
02852   *         @arg @ref LL_EXTI_LINE_15
02853   *         @arg @ref LL_EXTI_LINE_19
02854   *         @arg @ref LL_EXTI_LINE_20
02855   *         @arg @ref LL_EXTI_LINE_21
02856   *         @arg @ref LL_EXTI_LINE_25
02857   * @retval None
02858   */
02859 __STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)
02860 {
02861   CLEAR_BIT(EXTI->D3PMR1, ExtiLine);
02862 }
02863
02864 /**
02865   * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63
02866   * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63
02867   * @param  ExtiLine This parameter can be one of the following values:
02868   *         @arg @ref LL_EXTI_LINE_34
02869   *         @arg @ref LL_EXTI_LINE_35
02870   *         @arg @ref LL_EXTI_LINE_41
02871   *         @arg @ref LL_EXTI_LINE_48
02872   *         @arg @ref LL_EXTI_LINE_49
02873   *         @arg @ref LL_EXTI_LINE_50
02874   *         @arg @ref LL_EXTI_LINE_51
02875   *         @arg @ref LL_EXTI_LINE_52
02876   *         @arg @ref LL_EXTI_LINE_53
02877   * @retval None
02878   */
02879 __STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)
02880 {
02881   CLEAR_BIT(EXTI->D3PMR2, ExtiLine);
02882 }
02883
02884 /**
02885   * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31
02886   * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31
02887   * @param  ExtiLine This parameter can be one of the following values:
02888   *         @arg @ref LL_EXTI_LINE_0
02889   *         @arg @ref LL_EXTI_LINE_1
02890   *         @arg @ref LL_EXTI_LINE_2
02891   *         @arg @ref LL_EXTI_LINE_3
02892   *         @arg @ref LL_EXTI_LINE_4
02893   *         @arg @ref LL_EXTI_LINE_5
02894   *         @arg @ref LL_EXTI_LINE_6
02895   *         @arg @ref LL_EXTI_LINE_7
02896   *         @arg @ref LL_EXTI_LINE_8
02897   *         @arg @ref LL_EXTI_LINE_9
02898   *         @arg @ref LL_EXTI_LINE_10
02899   *         @arg @ref LL_EXTI_LINE_11
02900   *         @arg @ref LL_EXTI_LINE_12
02901   *         @arg @ref LL_EXTI_LINE_13
02902   *         @arg @ref LL_EXTI_LINE_14
02903   *         @arg @ref LL_EXTI_LINE_15
02904   *         @arg @ref LL_EXTI_LINE_19
02905   *         @arg @ref LL_EXTI_LINE_20
02906   *         @arg @ref LL_EXTI_LINE_21
02907   *         @arg @ref LL_EXTI_LINE_25
02908   * @retval State of bit (1 or 0).
02909   */
02910 __STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)
02911 {
02912   return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02913 }
02914
02915 /**
02916   * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63
02917   * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63
02918   * @param  ExtiLine This parameter can be one of the following values:
02919   *         @arg @ref LL_EXTI_LINE_34
02920   *         @arg @ref LL_EXTI_LINE_35
02921   *         @arg @ref LL_EXTI_LINE_41
02922   *         @arg @ref LL_EXTI_LINE_48
02923   *         @arg @ref LL_EXTI_LINE_49
02924   *         @arg @ref LL_EXTI_LINE_50
02925   *         @arg @ref LL_EXTI_LINE_51
02926   *         @arg @ref LL_EXTI_LINE_52
02927   *         @arg @ref LL_EXTI_LINE_53
02928   * @retval State of bit (1 or 0).
02929   */
02930 __STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)
02931 {
02932   return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
02933 }
02934
02935 /**
02936   * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
02937   * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15
02938   * @param  ExtiLine This parameter can be one of the following values:
02939   *         @arg @ref LL_EXTI_LINE_0
02940   *         @arg @ref LL_EXTI_LINE_1
02941   *         @arg @ref LL_EXTI_LINE_2
02942   *         @arg @ref LL_EXTI_LINE_3
02943   *         @arg @ref LL_EXTI_LINE_4
02944   *         @arg @ref LL_EXTI_LINE_5
02945   *         @arg @ref LL_EXTI_LINE_6
02946   *         @arg @ref LL_EXTI_LINE_7
02947   *         @arg @ref LL_EXTI_LINE_8
02948   *         @arg @ref LL_EXTI_LINE_9
02949   *         @arg @ref LL_EXTI_LINE_10
02950   *         @arg @ref LL_EXTI_LINE_11
02951   *         @arg @ref LL_EXTI_LINE_12
02952   *         @arg @ref LL_EXTI_LINE_13
02953   *         @arg @ref LL_EXTI_LINE_14
02954   *         @arg @ref LL_EXTI_LINE_15
02955   * @param  ClrSrc This parameter can be one of the following values:
02956   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
02957   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
02958   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
02959   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
02960   * @retval None
02961   */
02962 __STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
02963 {
02964   MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
02965 }
02966
02967 /**
02968   * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
02969   * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31
02970   * @param  ExtiLine This parameter can be one of the following values:
02971   *         @arg @ref LL_EXTI_LINE_19
02972   *         @arg @ref LL_EXTI_LINE_20
02973   *         @arg @ref LL_EXTI_LINE_21
02974   *         @arg @ref LL_EXTI_LINE_25
02975   * @param  ClrSrc This parameter can be one of the following values:
02976   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
02977   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
02978   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
02979   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
02980   * @retval None
02981   */
02982 __STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
02983 {
02984   MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));
02985 }
02986
02987
02988 /**
02989   * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
02990   * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47
02991   * @param  ExtiLine This parameter can be one of the following values:
02992   *         @arg @ref LL_EXTI_LINE_34
02993   *         @arg @ref LL_EXTI_LINE_35
02994   *         @arg @ref LL_EXTI_LINE_41
02995   * @param  ClrSrc This parameter can be one of the following values:
02996   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
02997   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
02998   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
02999   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03000   * @retval None
03001   */
03002 __STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
03003 {
03004   MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
03005 }
03006
03007 /**
03008   * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
03009   * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63
03010   * @param  ExtiLine This parameter can be one of the following values:
03011   *         @arg @ref LL_EXTI_LINE_48
03012   *         @arg @ref LL_EXTI_LINE_49
03013   *         @arg @ref LL_EXTI_LINE_50
03014   *         @arg @ref LL_EXTI_LINE_51
03015   *         @arg @ref LL_EXTI_LINE_52
03016   *         @arg @ref LL_EXTI_LINE_53
03017   * @param  ClrSrc This parameter can be one of the following values:
03018   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
03019   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
03020   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
03021   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03022   * @retval None
03023   */
03024 __STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
03025 {
03026   MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));
03027 }
03028
03029 /**
03030   * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
03031   * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15
03032   * @param  ExtiLine This parameter can be one of the following values:
03033   *         @arg @ref LL_EXTI_LINE_0
03034   *         @arg @ref LL_EXTI_LINE_1
03035   *         @arg @ref LL_EXTI_LINE_2
03036   *         @arg @ref LL_EXTI_LINE_3
03037   *         @arg @ref LL_EXTI_LINE_4
03038   *         @arg @ref LL_EXTI_LINE_5
03039   *         @arg @ref LL_EXTI_LINE_6
03040   *         @arg @ref LL_EXTI_LINE_7
03041   *         @arg @ref LL_EXTI_LINE_8
03042   *         @arg @ref LL_EXTI_LINE_9
03043   *         @arg @ref LL_EXTI_LINE_10
03044   *         @arg @ref LL_EXTI_LINE_11
03045   *         @arg @ref LL_EXTI_LINE_12
03046   *         @arg @ref LL_EXTI_LINE_13
03047   *         @arg @ref LL_EXTI_LINE_14
03048   *         @arg @ref LL_EXTI_LINE_15
03049   * @retval Returned value can be one of the following values:
03050   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
03051   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
03052   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
03053   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03054   */
03055 __STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
03056 {
03057   return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
03058 }
03059
03060 /**
03061   * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
03062   * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31
03063   * @param  ExtiLine This parameter can be one of the following values:
03064   *         @arg @ref LL_EXTI_LINE_19
03065   *         @arg @ref LL_EXTI_LINE_20
03066   *         @arg @ref LL_EXTI_LINE_21
03067   *         @arg @ref LL_EXTI_LINE_25
03068   * @retval Returned value can be one of the following values:
03069   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
03070   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
03071   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
03072   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03073   */
03074 __STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
03075 {
03076   return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));
03077 }
03078
03079 /**
03080   * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
03081   * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47
03082   * @param  ExtiLine This parameter can be one of the following values:
03083   *         @arg @ref LL_EXTI_LINE_34
03084   *         @arg @ref LL_EXTI_LINE_35
03085   *         @arg @ref LL_EXTI_LINE_41
03086   * @retval Returned value can be one of the following values:
03087   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
03088   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
03089   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
03090   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03091   */
03092 __STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
03093 {
03094   return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
03095 }
03096
03097 /**
03098   * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
03099   * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63
03100   * @param  ExtiLine This parameter can be one of the following values:
03101   *         @arg @ref LL_EXTI_LINE_48
03102   *         @arg @ref LL_EXTI_LINE_49
03103   *         @arg @ref LL_EXTI_LINE_50
03104   *         @arg @ref LL_EXTI_LINE_51
03105   *         @arg @ref LL_EXTI_LINE_52
03106   *         @arg @ref LL_EXTI_LINE_53
03107   * @retval Returned value can be one of the following values:
03108   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
03109   *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
03110   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
03111   *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
03112   */
03113 __STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
03114 {
03115   return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));
03116 }
03117
03118
03119
03120 /**
03121   * @}
03122   */
03123
03124 #if defined(USE_FULL_LL_DRIVER)
03125 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
03126   * @{,
03127   */
03128
03129 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
03130 ErrorStatus LL_EXTI_DeInit(void);
03131 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
03132
03133
03134 /**
03135   * @}
03136   */
03137 #endif /* USE_FULL_LL_DRIVER */
03138
03139 /**
03140   * @}
03141   */
03142
03143 /**
03144   * @}
03145   */
03146
03147 #endif /* EXTI */
03148
03149 /**
03150   * @}
03151   */
03152
03153 #ifdef __cplusplus
03154 }
03155 #endif
03156
03157 #endif /* __STM32H7xx_LL_EXTI_H */
03158
03159 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_gpio.c Source File

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stm32h7xx_ll_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 #if defined(USE_FULL_LL_DRIVER)
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32h7xx_ll_gpio.h"
00024 #include "stm32h7xx_ll_bus.h"
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
00036
00037 /** @addtogroup GPIO_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup GPIO_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00049
00050 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00051                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00052                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00053                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00054
00055 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00056                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00057
00058 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00059                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00060                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
00061                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
00062
00063 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00064                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00065                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00066
00067 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00068                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00069                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00070                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00071                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00072                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00073                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00074                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00075                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00076                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00077                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
00078                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
00079                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
00080                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
00081                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
00082                                             ((__VALUE__) == LL_GPIO_AF_15 ))
00083 /**
00084   * @}
00085   */
00086
00087 /* Private function prototypes -----------------------------------------------*/
00088
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @addtogroup GPIO_LL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup GPIO_LL_EF_Init
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00100   * @param  GPIOx GPIO Port
00101   * @retval An ErrorStatus enumeration value:
00102   *          - SUCCESS: GPIO registers are de-initialized
00103   *          - ERROR:   Wrong GPIO Port
00104   */
00105 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00106 {
00107   ErrorStatus status = SUCCESS;
00108
00109   /* Check the parameters */
00110   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00111
00112   /* Force and Release reset on clock of GPIOx Port */
00113   if (GPIOx == GPIOA)
00114   {
00115     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA);
00116     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA);
00117   }
00118   else if (GPIOx == GPIOB)
00119   {
00120     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB);
00121     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB);
00122   }
00123   else if (GPIOx == GPIOC)
00124   {
00125     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC);
00126     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC);
00127   }
00128 #if defined(GPIOD)
00129   else if (GPIOx == GPIOD)
00130   {
00131     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD);
00132     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD);
00133   }
00134 #endif /* GPIOD */
00135 #if defined(GPIOE)
00136   else if (GPIOx == GPIOE)
00137   {
00138     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE);
00139     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE);
00140   }
00141 #endif /* GPIOE */
00142 #if defined(GPIOF)
00143   else if (GPIOx == GPIOF)
00144   {
00145     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF);
00146     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF);
00147   }
00148 #endif /* GPIOF */
00149 #if defined(GPIOG)
00150   else if (GPIOx == GPIOG)
00151   {
00152     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG);
00153     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG);
00154   }
00155 #endif /* GPIOG */
00156 #if defined(GPIOH)
00157   else if (GPIOx == GPIOH)
00158   {
00159     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH);
00160     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH);
00161   }
00162 #endif /* GPIOH */
00163 #if defined(GPIOI)
00164   else if (GPIOx == GPIOI)
00165   {
00166     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOI);
00167     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOI);
00168   }
00169 #endif /* GPIOI */
00170 #if defined(GPIOJ)
00171   else if (GPIOx == GPIOJ)
00172   {
00173     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
00174     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
00175   }
00176 #endif /* GPIOJ */
00177 #if defined(GPIOK)
00178   else if (GPIOx == GPIOK)
00179   {
00180     LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOK);
00181     LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOK);
00182   }
00183 #endif /* GPIOK */
00184   else
00185   {
00186     status = ERROR;
00187   }
00188
00189   return (status);
00190 }
00191
00192 /**
00193   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00194   * @param  GPIOx GPIO Port
00195   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00196   *         that contains the configuration information for the specified GPIO peripheral.
00197   * @retval An ErrorStatus enumeration value:
00198   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00199   *          - ERROR:   Not applicable
00200   */
00201 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00202 {
00203   uint32_t pinpos, currentpin;
00204
00205   /* Check the parameters */
00206   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00207   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00208   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00209   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00210
00211   /* ------------------------- Configure the port pins ---------------- */
00212   /* Initialize  pinpos on first pin set */
00213   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00214
00215   /* Configure the port pins */
00216   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
00217   {
00218     /* Get current io position */
00219     currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
00220
00221     if (currentpin != 0x00000000U)
00222     {
00223       /* Pin Mode configuration */
00224       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00225
00226       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00227       {
00228         /* Check Speed mode parameters */
00229         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00230
00231         /* Speed mode configuration */
00232         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00233       }
00234
00235       /* Pull-up Pull down resistor configuration*/
00236       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00237
00238       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00239       {
00240         /* Check Alternate parameter */
00241         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00242
00243         /* Speed mode configuration */
00244         if (currentpin < LL_GPIO_PIN_8)
00245         {
00246           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00247         }
00248         else
00249         {
00250           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00251         }
00252       }
00253     }
00254     pinpos++;
00255   }
00256
00257   if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00258   {
00259     /* Check Output mode parameters */
00260     assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00261
00262     /* Output mode configuration*/
00263     LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00264
00265   }
00266   return (SUCCESS);
00267 }
00268
00269 /**
00270   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00271   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00272   *                          whose fields will be set to default values.
00273   * @retval None
00274   */
00275
00276 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00277 {
00278   /* Reset GPIO init structure parameters values */
00279   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00280   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00281   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00282   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00283   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00284   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00285 }
00286
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
00300
00301 /**
00302   * @}
00303   */
00304
00305 #endif /* USE_FULL_LL_DRIVER */
00306
00307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00308
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_gpio.h Source File

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stm32h7xx_ll_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_GPIO_H
00022 #define STM32H7xx_LL_GPIO_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
00036
00037 /** @defgroup GPIO_LL GPIO
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00047   * @{
00048   */
00049
00050 /**
00051   * @}
00052   */
00053 #endif /*USE_FULL_LL_DRIVER*/
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 #if defined(USE_FULL_LL_DRIVER)
00057 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00058   * @{
00059   */
00060
00061 /**
00062   * @brief LL GPIO Init Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00067                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00068
00069   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00070                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00071
00072                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00073
00074   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00075                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00076
00077                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00078
00079   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00080                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00081
00082                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00083
00084   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00085                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00086
00087                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00088
00089   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00090                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00091
00092                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00093 } LL_GPIO_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098 #endif /* USE_FULL_LL_DRIVER */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup GPIO_LL_EC_PIN PIN
00106   * @{
00107   */
00108 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
00109 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
00110 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
00111 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
00112 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
00113 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
00114 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
00115 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
00116 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
00117 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
00118 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
00119 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
00120 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
00121 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
00122 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
00123 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
00124 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
00125                                            GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
00126                                            GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
00127                                            GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
00128                                            GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
00129                                            GPIO_BSRR_BS15) /*!< Select all pins */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup GPIO_LL_EC_MODE Mode
00135   * @{
00136   */
00137 #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
00138 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
00139 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
00140 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00146   * @{
00147   */
00148 #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
00149 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00155   * @{
00156   */
00157 #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
00158 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
00159 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
00160 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
00161 /**
00162   * @}
00163   */
00164 #define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
00165 #define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
00166 #define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
00167 #define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
00168
00169
00170 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00171   * @{
00172   */
00173 #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
00174 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
00175 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup GPIO_LL_EC_AF Alternate Function
00181   * @{
00182   */
00183 #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
00184 #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
00185 #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
00186 #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
00187 #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
00188 #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
00189 #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
00190 #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
00191 #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
00192 #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
00193 #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
00194 #define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
00195 #define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
00196 #define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
00197 #define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
00198 #define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
00199 /**
00200   * @}
00201   */
00202
00203 /**
00204   * @}
00205   */
00206
00207 /* Exported macro ------------------------------------------------------------*/
00208 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00209   * @{
00210   */
00211
00212 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00213   * @{
00214   */
00215
00216 /**
00217   * @brief  Write a value in GPIO register
00218   * @param  __INSTANCE__ GPIO Instance
00219   * @param  __REG__ Register to be written
00220   * @param  __VALUE__ Value to be written in the register
00221   * @retval None
00222   */
00223 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00224
00225 /**
00226   * @brief  Read a value in GPIO register
00227   * @param  __INSTANCE__ GPIO Instance
00228   * @param  __REG__ Register to be read
00229   * @retval Register value
00230   */
00231 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported functions --------------------------------------------------------*/
00241 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00242   * @{
00243   */
00244
00245 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00246   * @{
00247   */
00248
00249 /**
00250   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00251   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00252   * @note   Warning: only one pin can be passed as parameter.
00253   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00254   * @param  GPIOx GPIO Port
00255   * @param  Pin This parameter can be one of the following values:
00256   *         @arg @ref LL_GPIO_PIN_0
00257   *         @arg @ref LL_GPIO_PIN_1
00258   *         @arg @ref LL_GPIO_PIN_2
00259   *         @arg @ref LL_GPIO_PIN_3
00260   *         @arg @ref LL_GPIO_PIN_4
00261   *         @arg @ref LL_GPIO_PIN_5
00262   *         @arg @ref LL_GPIO_PIN_6
00263   *         @arg @ref LL_GPIO_PIN_7
00264   *         @arg @ref LL_GPIO_PIN_8
00265   *         @arg @ref LL_GPIO_PIN_9
00266   *         @arg @ref LL_GPIO_PIN_10
00267   *         @arg @ref LL_GPIO_PIN_11
00268   *         @arg @ref LL_GPIO_PIN_12
00269   *         @arg @ref LL_GPIO_PIN_13
00270   *         @arg @ref LL_GPIO_PIN_14
00271   *         @arg @ref LL_GPIO_PIN_15
00272   * @param  Mode This parameter can be one of the following values:
00273   *         @arg @ref LL_GPIO_MODE_INPUT
00274   *         @arg @ref LL_GPIO_MODE_OUTPUT
00275   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00276   *         @arg @ref LL_GPIO_MODE_ANALOG
00277   * @retval None
00278   */
00279 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00280 {
00281   MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
00282 }
00283
00284 /**
00285   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00286   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00287   * @note   Warning: only one pin can be passed as parameter.
00288   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00289   * @param  GPIOx GPIO Port
00290   * @param  Pin This parameter can be one of the following values:
00291   *         @arg @ref LL_GPIO_PIN_0
00292   *         @arg @ref LL_GPIO_PIN_1
00293   *         @arg @ref LL_GPIO_PIN_2
00294   *         @arg @ref LL_GPIO_PIN_3
00295   *         @arg @ref LL_GPIO_PIN_4
00296   *         @arg @ref LL_GPIO_PIN_5
00297   *         @arg @ref LL_GPIO_PIN_6
00298   *         @arg @ref LL_GPIO_PIN_7
00299   *         @arg @ref LL_GPIO_PIN_8
00300   *         @arg @ref LL_GPIO_PIN_9
00301   *         @arg @ref LL_GPIO_PIN_10
00302   *         @arg @ref LL_GPIO_PIN_11
00303   *         @arg @ref LL_GPIO_PIN_12
00304   *         @arg @ref LL_GPIO_PIN_13
00305   *         @arg @ref LL_GPIO_PIN_14
00306   *         @arg @ref LL_GPIO_PIN_15
00307   * @retval Returned value can be one of the following values:
00308   *         @arg @ref LL_GPIO_MODE_INPUT
00309   *         @arg @ref LL_GPIO_MODE_OUTPUT
00310   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00311   *         @arg @ref LL_GPIO_MODE_ANALOG
00312   */
00313 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00314 {
00315   return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
00316 }
00317
00318 /**
00319   * @brief  Configure gpio output type for several pins on dedicated port.
00320   * @note   Output type as to be set when gpio pin is in output or
00321   *         alternate modes. Possible type are Push-pull or Open-drain.
00322   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00323   * @param  GPIOx GPIO Port
00324   * @param  PinMask This parameter can be a combination of the following values:
00325   *         @arg @ref LL_GPIO_PIN_0
00326   *         @arg @ref LL_GPIO_PIN_1
00327   *         @arg @ref LL_GPIO_PIN_2
00328   *         @arg @ref LL_GPIO_PIN_3
00329   *         @arg @ref LL_GPIO_PIN_4
00330   *         @arg @ref LL_GPIO_PIN_5
00331   *         @arg @ref LL_GPIO_PIN_6
00332   *         @arg @ref LL_GPIO_PIN_7
00333   *         @arg @ref LL_GPIO_PIN_8
00334   *         @arg @ref LL_GPIO_PIN_9
00335   *         @arg @ref LL_GPIO_PIN_10
00336   *         @arg @ref LL_GPIO_PIN_11
00337   *         @arg @ref LL_GPIO_PIN_12
00338   *         @arg @ref LL_GPIO_PIN_13
00339   *         @arg @ref LL_GPIO_PIN_14
00340   *         @arg @ref LL_GPIO_PIN_15
00341   *         @arg @ref LL_GPIO_PIN_ALL
00342   * @param  OutputType This parameter can be one of the following values:
00343   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00344   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00345   * @retval None
00346   */
00347 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00348 {
00349   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00350 }
00351
00352 /**
00353   * @brief  Return gpio output type for several pins on dedicated port.
00354   * @note   Output type as to be set when gpio pin is in output or
00355   *         alternate modes. Possible type are Push-pull or Open-drain.
00356   * @note   Warning: only one pin can be passed as parameter.
00357   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00358   * @param  GPIOx GPIO Port
00359   * @param  Pin This parameter can be one of the following values:
00360   *         @arg @ref LL_GPIO_PIN_0
00361   *         @arg @ref LL_GPIO_PIN_1
00362   *         @arg @ref LL_GPIO_PIN_2
00363   *         @arg @ref LL_GPIO_PIN_3
00364   *         @arg @ref LL_GPIO_PIN_4
00365   *         @arg @ref LL_GPIO_PIN_5
00366   *         @arg @ref LL_GPIO_PIN_6
00367   *         @arg @ref LL_GPIO_PIN_7
00368   *         @arg @ref LL_GPIO_PIN_8
00369   *         @arg @ref LL_GPIO_PIN_9
00370   *         @arg @ref LL_GPIO_PIN_10
00371   *         @arg @ref LL_GPIO_PIN_11
00372   *         @arg @ref LL_GPIO_PIN_12
00373   *         @arg @ref LL_GPIO_PIN_13
00374   *         @arg @ref LL_GPIO_PIN_14
00375   *         @arg @ref LL_GPIO_PIN_15
00376   *         @arg @ref LL_GPIO_PIN_ALL
00377   * @retval Returned value can be one of the following values:
00378   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00379   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00380   */
00381 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00382 {
00383   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
00384 }
00385
00386 /**
00387   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00388   * @note   I/O speed can be Low, Medium, Fast or High speed.
00389   * @note   Warning: only one pin can be passed as parameter.
00390   * @note   Refer to datasheet for frequency specifications and the power
00391   *         supply and load conditions for each speed.
00392   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00393   * @param  GPIOx GPIO Port
00394   * @param  Pin This parameter can be one of the following values:
00395   *         @arg @ref LL_GPIO_PIN_0
00396   *         @arg @ref LL_GPIO_PIN_1
00397   *         @arg @ref LL_GPIO_PIN_2
00398   *         @arg @ref LL_GPIO_PIN_3
00399   *         @arg @ref LL_GPIO_PIN_4
00400   *         @arg @ref LL_GPIO_PIN_5
00401   *         @arg @ref LL_GPIO_PIN_6
00402   *         @arg @ref LL_GPIO_PIN_7
00403   *         @arg @ref LL_GPIO_PIN_8
00404   *         @arg @ref LL_GPIO_PIN_9
00405   *         @arg @ref LL_GPIO_PIN_10
00406   *         @arg @ref LL_GPIO_PIN_11
00407   *         @arg @ref LL_GPIO_PIN_12
00408   *         @arg @ref LL_GPIO_PIN_13
00409   *         @arg @ref LL_GPIO_PIN_14
00410   *         @arg @ref LL_GPIO_PIN_15
00411   * @param  Speed This parameter can be one of the following values:
00412   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00413   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00414   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00415   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00416   * @retval None
00417   */
00418 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00419 {
00420   MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
00421 }
00422
00423 /**
00424   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00425   * @note   I/O speed can be Low, Medium, Fast or High speed.
00426   * @note   Warning: only one pin can be passed as parameter.
00427   * @note   Refer to datasheet for frequency specifications and the power
00428   *         supply and load conditions for each speed.
00429   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00430   * @param  GPIOx GPIO Port
00431   * @param  Pin This parameter can be one of the following values:
00432   *         @arg @ref LL_GPIO_PIN_0
00433   *         @arg @ref LL_GPIO_PIN_1
00434   *         @arg @ref LL_GPIO_PIN_2
00435   *         @arg @ref LL_GPIO_PIN_3
00436   *         @arg @ref LL_GPIO_PIN_4
00437   *         @arg @ref LL_GPIO_PIN_5
00438   *         @arg @ref LL_GPIO_PIN_6
00439   *         @arg @ref LL_GPIO_PIN_7
00440   *         @arg @ref LL_GPIO_PIN_8
00441   *         @arg @ref LL_GPIO_PIN_9
00442   *         @arg @ref LL_GPIO_PIN_10
00443   *         @arg @ref LL_GPIO_PIN_11
00444   *         @arg @ref LL_GPIO_PIN_12
00445   *         @arg @ref LL_GPIO_PIN_13
00446   *         @arg @ref LL_GPIO_PIN_14
00447   *         @arg @ref LL_GPIO_PIN_15
00448   * @retval Returned value can be one of the following values:
00449   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00450   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00451   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00452   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00453   */
00454 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00455 {
00456   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
00457 }
00458
00459 /**
00460   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00461   * @note   Warning: only one pin can be passed as parameter.
00462   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00463   * @param  GPIOx GPIO Port
00464   * @param  Pin This parameter can be one of the following values:
00465   *         @arg @ref LL_GPIO_PIN_0
00466   *         @arg @ref LL_GPIO_PIN_1
00467   *         @arg @ref LL_GPIO_PIN_2
00468   *         @arg @ref LL_GPIO_PIN_3
00469   *         @arg @ref LL_GPIO_PIN_4
00470   *         @arg @ref LL_GPIO_PIN_5
00471   *         @arg @ref LL_GPIO_PIN_6
00472   *         @arg @ref LL_GPIO_PIN_7
00473   *         @arg @ref LL_GPIO_PIN_8
00474   *         @arg @ref LL_GPIO_PIN_9
00475   *         @arg @ref LL_GPIO_PIN_10
00476   *         @arg @ref LL_GPIO_PIN_11
00477   *         @arg @ref LL_GPIO_PIN_12
00478   *         @arg @ref LL_GPIO_PIN_13
00479   *         @arg @ref LL_GPIO_PIN_14
00480   *         @arg @ref LL_GPIO_PIN_15
00481   * @param  Pull This parameter can be one of the following values:
00482   *         @arg @ref LL_GPIO_PULL_NO
00483   *         @arg @ref LL_GPIO_PULL_UP
00484   *         @arg @ref LL_GPIO_PULL_DOWN
00485   * @retval None
00486   */
00487 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00488 {
00489   MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
00490 }
00491
00492 /**
00493   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00494   * @note   Warning: only one pin can be passed as parameter.
00495   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00496   * @param  GPIOx GPIO Port
00497   * @param  Pin This parameter can be one of the following values:
00498   *         @arg @ref LL_GPIO_PIN_0
00499   *         @arg @ref LL_GPIO_PIN_1
00500   *         @arg @ref LL_GPIO_PIN_2
00501   *         @arg @ref LL_GPIO_PIN_3
00502   *         @arg @ref LL_GPIO_PIN_4
00503   *         @arg @ref LL_GPIO_PIN_5
00504   *         @arg @ref LL_GPIO_PIN_6
00505   *         @arg @ref LL_GPIO_PIN_7
00506   *         @arg @ref LL_GPIO_PIN_8
00507   *         @arg @ref LL_GPIO_PIN_9
00508   *         @arg @ref LL_GPIO_PIN_10
00509   *         @arg @ref LL_GPIO_PIN_11
00510   *         @arg @ref LL_GPIO_PIN_12
00511   *         @arg @ref LL_GPIO_PIN_13
00512   *         @arg @ref LL_GPIO_PIN_14
00513   *         @arg @ref LL_GPIO_PIN_15
00514   * @retval Returned value can be one of the following values:
00515   *         @arg @ref LL_GPIO_PULL_NO
00516   *         @arg @ref LL_GPIO_PULL_UP
00517   *         @arg @ref LL_GPIO_PULL_DOWN
00518   */
00519 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00520 {
00521   return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
00522 }
00523
00524 /**
00525   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00526   * @note   Possible values are from AF0 to AF15 depending on target.
00527   * @note   Warning: only one pin can be passed as parameter.
00528   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00529   * @param  GPIOx GPIO Port
00530   * @param  Pin This parameter can be one of the following values:
00531   *         @arg @ref LL_GPIO_PIN_0
00532   *         @arg @ref LL_GPIO_PIN_1
00533   *         @arg @ref LL_GPIO_PIN_2
00534   *         @arg @ref LL_GPIO_PIN_3
00535   *         @arg @ref LL_GPIO_PIN_4
00536   *         @arg @ref LL_GPIO_PIN_5
00537   *         @arg @ref LL_GPIO_PIN_6
00538   *         @arg @ref LL_GPIO_PIN_7
00539   * @param  Alternate This parameter can be one of the following values:
00540   *         @arg @ref LL_GPIO_AF_0
00541   *         @arg @ref LL_GPIO_AF_1
00542   *         @arg @ref LL_GPIO_AF_2
00543   *         @arg @ref LL_GPIO_AF_3
00544   *         @arg @ref LL_GPIO_AF_4
00545   *         @arg @ref LL_GPIO_AF_5
00546   *         @arg @ref LL_GPIO_AF_6
00547   *         @arg @ref LL_GPIO_AF_7
00548   *         @arg @ref LL_GPIO_AF_8
00549   *         @arg @ref LL_GPIO_AF_9
00550   *         @arg @ref LL_GPIO_AF_10
00551   *         @arg @ref LL_GPIO_AF_11
00552   *         @arg @ref LL_GPIO_AF_12
00553   *         @arg @ref LL_GPIO_AF_13
00554   *         @arg @ref LL_GPIO_AF_14
00555   *         @arg @ref LL_GPIO_AF_15
00556   * @retval None
00557   */
00558 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00559 {
00560   MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
00561              ((((Pin * Pin) * Pin) * Pin) * Alternate));
00562 }
00563
00564 /**
00565   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00566   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00567   * @param  GPIOx GPIO Port
00568   * @param  Pin This parameter can be one of the following values:
00569   *         @arg @ref LL_GPIO_PIN_0
00570   *         @arg @ref LL_GPIO_PIN_1
00571   *         @arg @ref LL_GPIO_PIN_2
00572   *         @arg @ref LL_GPIO_PIN_3
00573   *         @arg @ref LL_GPIO_PIN_4
00574   *         @arg @ref LL_GPIO_PIN_5
00575   *         @arg @ref LL_GPIO_PIN_6
00576   *         @arg @ref LL_GPIO_PIN_7
00577   * @retval Returned value can be one of the following values:
00578   *         @arg @ref LL_GPIO_AF_0
00579   *         @arg @ref LL_GPIO_AF_1
00580   *         @arg @ref LL_GPIO_AF_2
00581   *         @arg @ref LL_GPIO_AF_3
00582   *         @arg @ref LL_GPIO_AF_4
00583   *         @arg @ref LL_GPIO_AF_5
00584   *         @arg @ref LL_GPIO_AF_6
00585   *         @arg @ref LL_GPIO_AF_7
00586   *         @arg @ref LL_GPIO_AF_8
00587   *         @arg @ref LL_GPIO_AF_9
00588   *         @arg @ref LL_GPIO_AF_10
00589   *         @arg @ref LL_GPIO_AF_11
00590   *         @arg @ref LL_GPIO_AF_12
00591   *         @arg @ref LL_GPIO_AF_13
00592   *         @arg @ref LL_GPIO_AF_14
00593   *         @arg @ref LL_GPIO_AF_15
00594   */
00595 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00596 {
00597   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00598                              ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
00599 }
00600
00601 /**
00602   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00603   * @note   Possible values are from AF0 to AF15 depending on target.
00604   * @note   Warning: only one pin can be passed as parameter.
00605   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00606   * @param  GPIOx GPIO Port
00607   * @param  Pin This parameter can be one of the following values:
00608   *         @arg @ref LL_GPIO_PIN_8
00609   *         @arg @ref LL_GPIO_PIN_9
00610   *         @arg @ref LL_GPIO_PIN_10
00611   *         @arg @ref LL_GPIO_PIN_11
00612   *         @arg @ref LL_GPIO_PIN_12
00613   *         @arg @ref LL_GPIO_PIN_13
00614   *         @arg @ref LL_GPIO_PIN_14
00615   *         @arg @ref LL_GPIO_PIN_15
00616   * @param  Alternate This parameter can be one of the following values:
00617   *         @arg @ref LL_GPIO_AF_0
00618   *         @arg @ref LL_GPIO_AF_1
00619   *         @arg @ref LL_GPIO_AF_2
00620   *         @arg @ref LL_GPIO_AF_3
00621   *         @arg @ref LL_GPIO_AF_4
00622   *         @arg @ref LL_GPIO_AF_5
00623   *         @arg @ref LL_GPIO_AF_6
00624   *         @arg @ref LL_GPIO_AF_7
00625   *         @arg @ref LL_GPIO_AF_8
00626   *         @arg @ref LL_GPIO_AF_9
00627   *         @arg @ref LL_GPIO_AF_10
00628   *         @arg @ref LL_GPIO_AF_11
00629   *         @arg @ref LL_GPIO_AF_12
00630   *         @arg @ref LL_GPIO_AF_13
00631   *         @arg @ref LL_GPIO_AF_14
00632   *         @arg @ref LL_GPIO_AF_15
00633   * @retval None
00634   */
00635 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00636 {
00637   MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
00638              (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
00639 }
00640
00641 /**
00642   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00643   * @note   Possible values are from AF0 to AF15 depending on target.
00644   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00645   * @param  GPIOx GPIO Port
00646   * @param  Pin This parameter can be one of the following values:
00647   *         @arg @ref LL_GPIO_PIN_8
00648   *         @arg @ref LL_GPIO_PIN_9
00649   *         @arg @ref LL_GPIO_PIN_10
00650   *         @arg @ref LL_GPIO_PIN_11
00651   *         @arg @ref LL_GPIO_PIN_12
00652   *         @arg @ref LL_GPIO_PIN_13
00653   *         @arg @ref LL_GPIO_PIN_14
00654   *         @arg @ref LL_GPIO_PIN_15
00655   * @retval Returned value can be one of the following values:
00656   *         @arg @ref LL_GPIO_AF_0
00657   *         @arg @ref LL_GPIO_AF_1
00658   *         @arg @ref LL_GPIO_AF_2
00659   *         @arg @ref LL_GPIO_AF_3
00660   *         @arg @ref LL_GPIO_AF_4
00661   *         @arg @ref LL_GPIO_AF_5
00662   *         @arg @ref LL_GPIO_AF_6
00663   *         @arg @ref LL_GPIO_AF_7
00664   *         @arg @ref LL_GPIO_AF_8
00665   *         @arg @ref LL_GPIO_AF_9
00666   *         @arg @ref LL_GPIO_AF_10
00667   *         @arg @ref LL_GPIO_AF_11
00668   *         @arg @ref LL_GPIO_AF_12
00669   *         @arg @ref LL_GPIO_AF_13
00670   *         @arg @ref LL_GPIO_AF_14
00671   *         @arg @ref LL_GPIO_AF_15
00672   */
00673 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00674 {
00675   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00676                              (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
00677                                  (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
00678 }
00679
00680
00681 /**
00682   * @brief  Lock configuration of several pins for a dedicated port.
00683   * @note   When the lock sequence has been applied on a port bit, the
00684   *         value of this port bit can no longer be modified until the
00685   *         next reset.
00686   * @note   Each lock bit freezes a specific configuration register
00687   *         (control and alternate function registers).
00688   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00689   * @param  GPIOx GPIO Port
00690   * @param  PinMask This parameter can be a combination of the following values:
00691   *         @arg @ref LL_GPIO_PIN_0
00692   *         @arg @ref LL_GPIO_PIN_1
00693   *         @arg @ref LL_GPIO_PIN_2
00694   *         @arg @ref LL_GPIO_PIN_3
00695   *         @arg @ref LL_GPIO_PIN_4
00696   *         @arg @ref LL_GPIO_PIN_5
00697   *         @arg @ref LL_GPIO_PIN_6
00698   *         @arg @ref LL_GPIO_PIN_7
00699   *         @arg @ref LL_GPIO_PIN_8
00700   *         @arg @ref LL_GPIO_PIN_9
00701   *         @arg @ref LL_GPIO_PIN_10
00702   *         @arg @ref LL_GPIO_PIN_11
00703   *         @arg @ref LL_GPIO_PIN_12
00704   *         @arg @ref LL_GPIO_PIN_13
00705   *         @arg @ref LL_GPIO_PIN_14
00706   *         @arg @ref LL_GPIO_PIN_15
00707   *         @arg @ref LL_GPIO_PIN_ALL
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00711 {
00712   __IO uint32_t temp;
00713   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00714   WRITE_REG(GPIOx->LCKR, PinMask);
00715   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00716   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00717   temp = READ_REG(GPIOx->LCKR);
00718   (void) temp;
00719 }
00720
00721 /**
00722   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00723   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00724   * @param  GPIOx GPIO Port
00725   * @param  PinMask This parameter can be a combination of the following values:
00726   *         @arg @ref LL_GPIO_PIN_0
00727   *         @arg @ref LL_GPIO_PIN_1
00728   *         @arg @ref LL_GPIO_PIN_2
00729   *         @arg @ref LL_GPIO_PIN_3
00730   *         @arg @ref LL_GPIO_PIN_4
00731   *         @arg @ref LL_GPIO_PIN_5
00732   *         @arg @ref LL_GPIO_PIN_6
00733   *         @arg @ref LL_GPIO_PIN_7
00734   *         @arg @ref LL_GPIO_PIN_8
00735   *         @arg @ref LL_GPIO_PIN_9
00736   *         @arg @ref LL_GPIO_PIN_10
00737   *         @arg @ref LL_GPIO_PIN_11
00738   *         @arg @ref LL_GPIO_PIN_12
00739   *         @arg @ref LL_GPIO_PIN_13
00740   *         @arg @ref LL_GPIO_PIN_14
00741   *         @arg @ref LL_GPIO_PIN_15
00742   *         @arg @ref LL_GPIO_PIN_ALL
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00746 {
00747   return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
00748 }
00749
00750 /**
00751   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00752   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00753   * @param  GPIOx GPIO Port
00754   * @retval State of bit (1 or 0).
00755   */
00756 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00757 {
00758   return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
00759 }
00760
00761 /**
00762   * @}
00763   */
00764
00765 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00766   * @{
00767   */
00768
00769 /**
00770   * @brief  Return full input data register value for a dedicated port.
00771   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00772   * @param  GPIOx GPIO Port
00773   * @retval Input data register value of port
00774   */
00775 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00776 {
00777   return (uint32_t)(READ_REG(GPIOx->IDR));
00778 }
00779
00780 /**
00781   * @brief  Return if input data level for several pins of dedicated port is high or low.
00782   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00783   * @param  GPIOx GPIO Port
00784   * @param  PinMask This parameter can be a combination of the following values:
00785   *         @arg @ref LL_GPIO_PIN_0
00786   *         @arg @ref LL_GPIO_PIN_1
00787   *         @arg @ref LL_GPIO_PIN_2
00788   *         @arg @ref LL_GPIO_PIN_3
00789   *         @arg @ref LL_GPIO_PIN_4
00790   *         @arg @ref LL_GPIO_PIN_5
00791   *         @arg @ref LL_GPIO_PIN_6
00792   *         @arg @ref LL_GPIO_PIN_7
00793   *         @arg @ref LL_GPIO_PIN_8
00794   *         @arg @ref LL_GPIO_PIN_9
00795   *         @arg @ref LL_GPIO_PIN_10
00796   *         @arg @ref LL_GPIO_PIN_11
00797   *         @arg @ref LL_GPIO_PIN_12
00798   *         @arg @ref LL_GPIO_PIN_13
00799   *         @arg @ref LL_GPIO_PIN_14
00800   *         @arg @ref LL_GPIO_PIN_15
00801   *         @arg @ref LL_GPIO_PIN_ALL
00802   * @retval State of bit (1 or 0).
00803   */
00804 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00805 {
00806   return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
00807 }
00808
00809 /**
00810   * @brief  Write output data register for the port.
00811   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00812   * @param  GPIOx GPIO Port
00813   * @param  PortValue Level value for each pin of the port
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00817 {
00818   WRITE_REG(GPIOx->ODR, PortValue);
00819 }
00820
00821 /**
00822   * @brief  Return full output data register value for a dedicated port.
00823   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00824   * @param  GPIOx GPIO Port
00825   * @retval Output data register value of port
00826   */
00827 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00828 {
00829   return (uint32_t)(READ_REG(GPIOx->ODR));
00830 }
00831
00832 /**
00833   * @brief  Return if input data level for several pins of dedicated port is high or low.
00834   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00835   * @param  GPIOx GPIO Port
00836   * @param  PinMask This parameter can be a combination of the following values:
00837   *         @arg @ref LL_GPIO_PIN_0
00838   *         @arg @ref LL_GPIO_PIN_1
00839   *         @arg @ref LL_GPIO_PIN_2
00840   *         @arg @ref LL_GPIO_PIN_3
00841   *         @arg @ref LL_GPIO_PIN_4
00842   *         @arg @ref LL_GPIO_PIN_5
00843   *         @arg @ref LL_GPIO_PIN_6
00844   *         @arg @ref LL_GPIO_PIN_7
00845   *         @arg @ref LL_GPIO_PIN_8
00846   *         @arg @ref LL_GPIO_PIN_9
00847   *         @arg @ref LL_GPIO_PIN_10
00848   *         @arg @ref LL_GPIO_PIN_11
00849   *         @arg @ref LL_GPIO_PIN_12
00850   *         @arg @ref LL_GPIO_PIN_13
00851   *         @arg @ref LL_GPIO_PIN_14
00852   *         @arg @ref LL_GPIO_PIN_15
00853   *         @arg @ref LL_GPIO_PIN_ALL
00854   * @retval State of bit (1 or 0).
00855   */
00856 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00857 {
00858   return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
00859 }
00860
00861 /**
00862   * @brief  Set several pins to high level on dedicated gpio port.
00863   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00864   * @param  GPIOx GPIO Port
00865   * @param  PinMask This parameter can be a combination of the following values:
00866   *         @arg @ref LL_GPIO_PIN_0
00867   *         @arg @ref LL_GPIO_PIN_1
00868   *         @arg @ref LL_GPIO_PIN_2
00869   *         @arg @ref LL_GPIO_PIN_3
00870   *         @arg @ref LL_GPIO_PIN_4
00871   *         @arg @ref LL_GPIO_PIN_5
00872   *         @arg @ref LL_GPIO_PIN_6
00873   *         @arg @ref LL_GPIO_PIN_7
00874   *         @arg @ref LL_GPIO_PIN_8
00875   *         @arg @ref LL_GPIO_PIN_9
00876   *         @arg @ref LL_GPIO_PIN_10
00877   *         @arg @ref LL_GPIO_PIN_11
00878   *         @arg @ref LL_GPIO_PIN_12
00879   *         @arg @ref LL_GPIO_PIN_13
00880   *         @arg @ref LL_GPIO_PIN_14
00881   *         @arg @ref LL_GPIO_PIN_15
00882   *         @arg @ref LL_GPIO_PIN_ALL
00883   * @retval None
00884   */
00885 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00886 {
00887   WRITE_REG(GPIOx->BSRR, PinMask);
00888 }
00889
00890 /**
00891   * @brief  Set several pins to low level on dedicated gpio port.
00892   * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
00893   * @param  GPIOx GPIO Port
00894   * @param  PinMask This parameter can be a combination of the following values:
00895   *         @arg @ref LL_GPIO_PIN_0
00896   *         @arg @ref LL_GPIO_PIN_1
00897   *         @arg @ref LL_GPIO_PIN_2
00898   *         @arg @ref LL_GPIO_PIN_3
00899   *         @arg @ref LL_GPIO_PIN_4
00900   *         @arg @ref LL_GPIO_PIN_5
00901   *         @arg @ref LL_GPIO_PIN_6
00902   *         @arg @ref LL_GPIO_PIN_7
00903   *         @arg @ref LL_GPIO_PIN_8
00904   *         @arg @ref LL_GPIO_PIN_9
00905   *         @arg @ref LL_GPIO_PIN_10
00906   *         @arg @ref LL_GPIO_PIN_11
00907   *         @arg @ref LL_GPIO_PIN_12
00908   *         @arg @ref LL_GPIO_PIN_13
00909   *         @arg @ref LL_GPIO_PIN_14
00910   *         @arg @ref LL_GPIO_PIN_15
00911   *         @arg @ref LL_GPIO_PIN_ALL
00912   * @retval None
00913   */
00914 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00915 {
00916   WRITE_REG(GPIOx->BSRR, PinMask << 16U);
00917 }
00918
00919 /**
00920   * @brief  Toggle data value for several pin of dedicated port.
00921   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00922   * @param  GPIOx GPIO Port
00923   * @param  PinMask This parameter can be a combination of the following values:
00924   *         @arg @ref LL_GPIO_PIN_0
00925   *         @arg @ref LL_GPIO_PIN_1
00926   *         @arg @ref LL_GPIO_PIN_2
00927   *         @arg @ref LL_GPIO_PIN_3
00928   *         @arg @ref LL_GPIO_PIN_4
00929   *         @arg @ref LL_GPIO_PIN_5
00930   *         @arg @ref LL_GPIO_PIN_6
00931   *         @arg @ref LL_GPIO_PIN_7
00932   *         @arg @ref LL_GPIO_PIN_8
00933   *         @arg @ref LL_GPIO_PIN_9
00934   *         @arg @ref LL_GPIO_PIN_10
00935   *         @arg @ref LL_GPIO_PIN_11
00936   *         @arg @ref LL_GPIO_PIN_12
00937   *         @arg @ref LL_GPIO_PIN_13
00938   *         @arg @ref LL_GPIO_PIN_14
00939   *         @arg @ref LL_GPIO_PIN_15
00940   *         @arg @ref LL_GPIO_PIN_ALL
00941   * @retval None
00942   */
00943 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00944 {
00945   WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
00946 }
00947
00948 /**
00949   * @}
00950   */
00951
00952 #if defined(USE_FULL_LL_DRIVER)
00953 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
00954   * @{
00955   */
00956
00957 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
00958 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
00959 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
00960
00961 /**
00962   * @}
00963   */
00964 #endif /* USE_FULL_LL_DRIVER */
00965
00966 /**
00967   * @}
00968   */
00969
00970 /**
00971   * @}
00972   */
00973
00974 #endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
00975 /**
00976   * @}
00977   */
00978
00979 #ifdef __cplusplus
00980 }
00981 #endif
00982
00983 #endif /* STM32H7xx_LL_GPIO_H */
00984
00985 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hrtim.c Source File

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stm32h7xx_ll_hrtim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   HRTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_hrtim.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (HRTIM1)
00036
00037 /** @addtogroup HRTIM_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Exported functions --------------------------------------------------------*/
00047 /** @addtogroup HRTIM_LL_Exported_Functions
00048   * @{
00049   */
00050 /**
00051   * @brief  Set HRTIM instance registers to their reset values.
00052   * @param  HRTIMx High Resolution Timer instance
00053   * @retval ErrorStatus enumeration value:
00054   *          - SUCCESS: HRTIMx registers are de-initialized
00055   *          - ERROR: invalid HRTIMx instance
00056   */
00057 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
00058 {
00059   ErrorStatus result = SUCCESS;
00060
00061   /* Check the parameters */
00062   assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
00063   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM);
00064   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM);
00065   return result;
00066 }
00067 /**
00068   * @}
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 #endif /* HRTIM1 */
00076
00077 /**
00078   * @}
00079   */
00080
00081 #endif /* USE_FULL_LL_DRIVER */
00082
00083 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:03 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hrtim.h Source File

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stm32h7xx_ll_hrtim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_HRTIM_H
00022 #define STM32H7xx_LL_HRTIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (HRTIM1)
00036
00037 /** @defgroup HRTIM_LL HRTIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
00044   * @{
00045   */
00046 static const uint16_t REG_OFFSET_TAB_TIMER[] =
00047 {
00048   0x00U,   /* 0: MASTER  */
00049   0x80U,   /* 1: TIMER A */
00050   0x100U,  /* 2: TIMER B */
00051   0x180U,  /* 3: TIMER C */
00052   0x200U,  /* 4: TIMER D */
00053   0x280U   /* 5: TIMER E */
00054 };
00055
00056 static const uint8_t REG_OFFSET_TAB_ADCxR[] =
00057 {
00058   0x00U,   /* 0: HRTIM_ADC1R */
00059   0x04U,   /* 1: HRTIM_ADC2R */
00060   0x08U,   /* 2: HRTIM_ADC3R */
00061   0x0CU,   /* 3: HRTIM_ADC4R */
00062 };
00063
00064 static const uint16_t REG_OFFSET_TAB_SETxR[] =
00065 {
00066   0x00U,   /* 0: TA1 */
00067   0x08U,   /* 1: TA2 */
00068   0x80U,   /* 2: TB1 */
00069   0x88U,   /* 3: TB2 */
00070   0x100U,  /* 4: TC1 */
00071   0x108U,  /* 5: TC2 */
00072   0x180U,  /* 6: TD1 */
00073   0x188U,  /* 7: TD2 */
00074   0x200U,  /* 8: TE1 */
00075   0x208U   /* 9: TE2 */
00076 };
00077
00078 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
00079 {
00080   0x00U,   /*  0: TA1 */
00081   0x00U,   /*  1: TA2 */
00082   0x80U,   /*  2: TB1 */
00083   0x80U,   /*  3: TB2 */
00084   0x100U,  /*  4: TC1 */
00085   0x100U,  /*  5: TC2 */
00086   0x180U,  /*  6: TD1 */
00087   0x180U,  /*  7: TD2 */
00088   0x200U,  /*  8: TE1 */
00089   0x200U   /*  9: TE2 */
00090 };
00091
00092 static const uint8_t REG_OFFSET_TAB_EECR[] =
00093 {
00094   0x00U, /* LL_HRTIM_EVENT_1 */
00095   0x00U, /* LL_HRTIM_EVENT_2 */
00096   0x00U, /* LL_HRTIM_EVENT_3 */
00097   0x00U, /* LL_HRTIM_EVENT_4 */
00098   0x00U, /* LL_HRTIM_EVENT_5 */
00099   0x04U, /* LL_HRTIM_EVENT_6 */
00100   0x04U, /* LL_HRTIM_EVENT_7 */
00101   0x04U, /* LL_HRTIM_EVENT_8 */
00102   0x04U, /* LL_HRTIM_EVENT_9 */
00103   0x04U  /* LL_HRTIM_EVENT_10 */
00104 };
00105
00106 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
00107 {
00108   0x00U, /* LL_HRTIM_FAULT_1 */
00109   0x00U, /* LL_HRTIM_FAULT_2 */
00110   0x00U, /* LL_HRTIM_FAULT_3 */
00111   0x00U, /* LL_HRTIM_FAULT_4 */
00112   0x04U  /* LL_HRTIM_FAULT_5 */
00113 };
00114
00115 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
00116 {
00117   0x20000000U,  /* 0: MASTER  */
00118   0x01FE0000U,  /* 1: TIMER A */
00119   0x01FE0000U,  /* 2: TIMER B */
00120   0x01FE0000U,  /* 3: TIMER C */
00121   0x01FE0000U,  /* 4: TIMER D */
00122   0x01FE0000U   /* 5: TIMER E */
00123 };
00124
00125 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
00126 {
00127   12U, /* 0: MASTER  */
00128   0U,  /* 1: TIMER A */
00129   0U,  /* 2: TIMER B  */
00130   0U,  /* 3: TIMER C */
00131   0U,  /* 4: TIMER D  */
00132   0U   /* 5: TIMER E */
00133 };
00134
00135 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
00136 {
00137   0U,  /* LL_HRTIM_EVENT_1  */
00138   6U,  /* LL_HRTIM_EVENT_2  */
00139   12U, /* LL_HRTIM_EVENT_3  */
00140   18U, /* LL_HRTIM_EVENT_4  */
00141   24U, /* LL_HRTIM_EVENT_5  */
00142   0U,  /* LL_HRTIM_EVENT_6  */
00143   6U,  /* LL_HRTIM_EVENT_7  */
00144   12U, /* LL_HRTIM_EVENT_8  */
00145   18U, /* LL_HRTIM_EVENT_9  */
00146   24U  /* LL_HRTIM_EVENT_10 */
00147 };
00148
00149 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
00150 {
00151   HRTIM_MCR_BRSTDMA,   /* 0: MASTER  */
00152   HRTIM_TIMCR_UPDGAT,  /* 1: TIMER A */
00153   HRTIM_TIMCR_UPDGAT,  /* 2: TIMER B  */
00154   HRTIM_TIMCR_UPDGAT,  /* 3: TIMER C */
00155   HRTIM_TIMCR_UPDGAT,  /* 4: TIMER D  */
00156   HRTIM_TIMCR_UPDGAT   /* 5: TIMER E */
00157 };
00158
00159 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
00160 {
00161   2U, /* 0: MASTER  */
00162   0U, /* 1: TIMER A */
00163   0U, /* 2: TIMER B  */
00164   0U, /* 3: TIMER C */
00165   0U, /* 4: TIMER D  */
00166   0U  /* 5: TIMER E */
00167 };
00168
00169 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
00170 {
00171   0U,  /* 0: TA1  */
00172   16U, /* 1: TA2 */
00173   0U,  /* 2: TB1  */
00174   16U, /* 3: TB2 */
00175   0U,  /* 4: TC1  */
00176   16U, /* 5: TC2 */
00177   0U,  /* 6: TD1  */
00178   16U, /* 7: TD2 */
00179   0U,  /* 8: TE1  */
00180   16U  /* 9: TE2 */
00181 };
00182
00183 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
00184 {
00185   0U,  /* 0: TA1  */
00186   1U,  /* 1: TA2 */
00187   0U,  /* 2: TB1  */
00188   1U,  /* 3: TB2 */
00189   0U,  /* 4: TC1  */
00190   1U,  /* 5: TC2 */
00191   0U,  /* 6: TD1  */
00192   1U,  /* 7: TD2 */
00193   0U,  /* 8: TE1  */
00194   1U   /* 9: TE2 */
00195 };
00196
00197 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
00198 {
00199   0U,   /* LL_HRTIM_FAULT_1 */
00200   8U,   /* LL_HRTIM_FAULT_2 */
00201   16U,  /* LL_HRTIM_FAULT_3 */
00202   24U,  /* LL_HRTIM_FAULT_4 */
00203   0U    /* LL_HRTIM_FAULT_5 */
00204 };
00205
00206 /**
00207   * @}
00208   */
00209
00210
00211 /* Private constants ---------------------------------------------------------*/
00212 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
00213   * @{
00214   */
00215 #define HRTIM_CR1_UDIS_MASK   ((uint32_t)(HRTIM_CR1_MUDIS  |\
00216                                           HRTIM_CR1_TAUDIS |\
00217                                           HRTIM_CR1_TBUDIS |\
00218                                           HRTIM_CR1_TCUDIS |\
00219                                           HRTIM_CR1_TDUDIS |\
00220                                           HRTIM_CR1_TEUDIS))
00221
00222 #define HRTIM_CR2_SWUPD_MASK   ((uint32_t)(HRTIM_CR2_MSWU |\
00223                                            HRTIM_CR2_TASWU |\
00224                                            HRTIM_CR2_TBSWU |\
00225                                            HRTIM_CR2_TCSWU |\
00226                                            HRTIM_CR2_TDSWU |\
00227                                            HRTIM_CR2_TESWU))
00228
00229 #define HRTIM_CR2_SWRST_MASK   ((uint32_t)(HRTIM_CR2_MRST |\
00230                                            HRTIM_CR2_TARST |\
00231                                            HRTIM_CR2_TBRST |\
00232                                            HRTIM_CR2_TCRST |\
00233                                            HRTIM_CR2_TDRST |\
00234                                            HRTIM_CR2_TERST))
00235
00236 #define HRTIM_OENR_OEN_MASK   ((uint32_t)(HRTIM_OENR_TA1OEN |\
00237                                           HRTIM_OENR_TA2OEN |\
00238                                           HRTIM_OENR_TB1OEN |\
00239                                           HRTIM_OENR_TB2OEN |\
00240                                           HRTIM_OENR_TC1OEN |\
00241                                           HRTIM_OENR_TC2OEN |\
00242                                           HRTIM_OENR_TD1OEN |\
00243                                           HRTIM_OENR_TD2OEN |\
00244                                           HRTIM_OENR_TE1OEN |\
00245                                           HRTIM_OENR_TE2OEN))
00246
00247 #define HRTIM_OENR_ODIS_MASK  ((uint32_t)(HRTIM_ODISR_TA1ODIS  |\
00248                                           HRTIM_ODISR_TA2ODIS  |\
00249                                           HRTIM_ODISR_TB1ODIS  |\
00250                                           HRTIM_ODISR_TB2ODIS  |\
00251                                           HRTIM_ODISR_TC1ODIS  |\
00252                                           HRTIM_ODISR_TC2ODIS  |\
00253                                           HRTIM_ODISR_TD1ODIS  |\
00254                                           HRTIM_ODISR_TD2ODIS  |\
00255                                           HRTIM_ODISR_TE1ODIS  |\
00256                                           HRTIM_ODISR_TE2ODIS))
00257
00258 #define HRTIM_OUT_CONFIG_MASK  ((uint32_t)(HRTIM_OUTR_POL1   |\
00259                                            HRTIM_OUTR_IDLM1  |\
00260                                            HRTIM_OUTR_IDLES1 |\
00261                                            HRTIM_OUTR_FAULT1 |\
00262                                            HRTIM_OUTR_CHP1   |\
00263                                            HRTIM_OUTR_DIDL1))
00264
00265 #define HRTIM_EE_CONFIG_MASK   ((uint32_t)(HRTIM_EECR1_EE1SRC |\
00266                                            HRTIM_EECR1_EE1POL |\
00267                                            HRTIM_EECR1_EE1SNS |\
00268                                            HRTIM_EECR1_EE1FAST))
00269
00270 #define HRTIM_FLT_CONFIG_MASK   ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
00271                                             HRTIM_FLTINR1_FLT1SRC))
00272
00273 #define HRTIM_BM_CONFIG_MASK   ((uint32_t)( HRTIM_BMCR_BMPRSC |\
00274                                             HRTIM_BMCR_BMCLK  |\
00275                                             HRTIM_BMCR_BMOM))
00276
00277 /**
00278   * @}
00279   */
00280
00281
00282 /* Private macros ------------------------------------------------------------*/
00283 /* Exported types ------------------------------------------------------------*/
00284 /* Exported constants --------------------------------------------------------*/
00285 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
00286   * @{
00287   */
00288
00289 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
00290   * @brief    Flags defines which can be used with LL_HRTIM_ReadReg function
00291   * @{
00292   */
00293 #define LL_HRTIM_ISR_FLT1                  HRTIM_ISR_FLT1
00294 #define LL_HRTIM_ISR_FLT2                  HRTIM_ISR_FLT2
00295 #define LL_HRTIM_ISR_FLT3                  HRTIM_ISR_FLT3
00296 #define LL_HRTIM_ISR_FLT4                  HRTIM_ISR_FLT4
00297 #define LL_HRTIM_ISR_FLT5                  HRTIM_ISR_FLT5
00298 #define LL_HRTIM_ISR_SYSFLT                HRTIM_ISR_SYSFLT
00299 #define LL_HRTIM_ISR_BMPER                 HRTIM_ISR_BMPER
00300
00301 #define LL_HRTIM_MISR_MCMP1                HRTIM_MISR_MCMP1
00302 #define LL_HRTIM_MISR_MCMP2                HRTIM_MISR_MCMP2
00303 #define LL_HRTIM_MISR_MCMP3                HRTIM_MISR_MCMP3
00304 #define LL_HRTIM_MISR_MCMP4                HRTIM_MISR_MCMP4
00305 #define LL_HRTIM_MISR_MREP                 HRTIM_MISR_MREP
00306 #define LL_HRTIM_MISR_SYNC                 HRTIM_MISR_SYNC
00307 #define LL_HRTIM_MISR_MUPD                 HRTIM_MISR_MUPD
00308
00309 #define LL_HRTIM_TIMISR_CMP1               HRTIM_TIMISR_CMP1
00310 #define LL_HRTIM_TIMISR_CMP2               HRTIM_TIMISR_CMP2
00311 #define LL_HRTIM_TIMISR_CMP3               HRTIM_TIMISR_CMP3
00312 #define LL_HRTIM_TIMISR_CMP4               HRTIM_TIMISR_CMP4
00313 #define LL_HRTIM_TIMISR_REP                HRTIM_TIMISR_REP
00314 #define LL_HRTIM_TIMISR_UPD                HRTIM_TIMISR_UPD
00315 #define LL_HRTIM_TIMISR_CPT1               HRTIM_TIMISR_CPT1
00316 #define LL_HRTIM_TIMISR_CPT2               HRTIM_TIMISR_CPT2
00317 #define LL_HRTIM_TIMISR_SET1               HRTIM_TIMISR_SET1
00318 #define LL_HRTIM_TIMISR_RST1               HRTIM_TIMISR_RST1
00319 #define LL_HRTIM_TIMISR_SET2               HRTIM_TIMISR_SET2
00320 #define LL_HRTIM_TIMISR_RST2               HRTIM_TIMISR_RST2
00321 #define LL_HRTIM_TIMISR_RST                HRTIM_TIMISR_RST
00322 #define LL_HRTIM_TIMISR_DLYPRT             HRTIM_TIMISR_DLYPRT
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup HRTIM_LL_EC_IT IT Defines
00328   * @brief    IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
00329   * @{
00330   */
00331 #define LL_HRTIM_IER_FLT1IE                HRTIM_IER_FLT1IE
00332 #define LL_HRTIM_IER_FLT2IE                HRTIM_IER_FLT2IE
00333 #define LL_HRTIM_IER_FLT3IE                HRTIM_IER_FLT3IE
00334 #define LL_HRTIM_IER_FLT4IE                HRTIM_IER_FLT4IE
00335 #define LL_HRTIM_IER_FLT5IE                HRTIM_IER_FLT5IE
00336 #define LL_HRTIM_IER_SYSFLTIE              HRTIM_IER_SYSFLTIE
00337 #define LL_HRTIM_IER_BMPERIE               HRTIM_IER_BMPERIE
00338
00339 #define LL_HRTIM_MDIER_MCMP1IE             HRTIM_MDIER_MCMP1IE
00340 #define LL_HRTIM_MDIER_MCMP2IE             HRTIM_MDIER_MCMP2IE
00341 #define LL_HRTIM_MDIER_MCMP3IE             HRTIM_MDIER_MCMP3IE
00342 #define LL_HRTIM_MDIER_MCMP4IE             HRTIM_MDIER_MCMP4IE
00343 #define LL_HRTIM_MDIER_MREPIE              HRTIM_MDIER_MREPIE
00344 #define LL_HRTIM_MDIER_SYNCIE              HRTIM_MDIER_SYNCIE
00345 #define LL_HRTIM_MDIER_MUPDIE              HRTIM_MDIER_MUPDIE
00346
00347 #define LL_HRTIM_TIMDIER_CMP1IE            HRTIM_TIMDIER_CMP1IE
00348 #define LL_HRTIM_TIMDIER_CMP2IE            HRTIM_TIMDIER_CMP2IE
00349 #define LL_HRTIM_TIMDIER_CMP3IE            HRTIM_TIMDIER_CMP3IE
00350 #define LL_HRTIM_TIMDIER_CMP4IE            HRTIM_TIMDIER_CMP4IE
00351 #define LL_HRTIM_TIMDIER_REPIE             HRTIM_TIMDIER_REPIE
00352 #define LL_HRTIM_TIMDIER_UPDIE             HRTIM_TIMDIER_UPDIE
00353 #define LL_HRTIM_TIMDIER_CPT1IE            HRTIM_TIMDIER_CPT1IE
00354 #define LL_HRTIM_TIMDIER_CPT2IE            HRTIM_TIMDIER_CPT2IE
00355 #define LL_HRTIM_TIMDIER_SET1IE            HRTIM_TIMDIER_SET1IE
00356 #define LL_HRTIM_TIMDIER_RST1IE            HRTIM_TIMDIER_RST1IE
00357 #define LL_HRTIM_TIMDIER_SET2IE            HRTIM_TIMDIER_SET2IE
00358 #define LL_HRTIM_TIMDIER_RST2IE            HRTIM_TIMDIER_RST2IE
00359 #define LL_HRTIM_TIMDIER_RSTIE             HRTIM_TIMDIER_RSTIE
00360 #define LL_HRTIM_TIMDIER_DLYPRTIE          HRTIM_TIMDIER_DLYPRTIE
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC  SYNCHRONIZATION INPUT SOURCE
00366   * @{
00367   * @brief Constants defining defining the synchronization input source.
00368   */
00369 #define LL_HRTIM_SYNCIN_SRC_NONE            0x00000000U                      /*!< HRTIM is not synchronized and runs in standalone mode */
00370 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT       (HRTIM_MCR_SYNC_IN_1)                        /*!< The HRTIM is synchronized with the on-chip timer */
00371 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC  SYNCHRONIZATION OUTPUT SOURCE
00377   * @{
00378   * @brief Constants defining the source and event to be sent on the synchronization output.
00379   */
00380 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                        /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
00381 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
00382 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
00383 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY  SYNCHRONIZATION OUTPUT POLARITY
00389   * @{
00390   * @brief Constants defining the routing and conditioning of the synchronization output event.
00391   */
00392 #define LL_HRTIM_SYNCOUT_DISABLED     0x00000000U                         /*!< Synchronization output event is disabled */
00393 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
00394 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup HRTIM_LL_EC_TIMER  TIMER ID
00400   * @{
00401   * @brief Constants identifying a timing unit.
00402   */
00403 #define LL_HRTIM_TIMER_NONE                0U   /*!< Master timer identifier */
00404 #define LL_HRTIM_TIMER_MASTER              HRTIM_MCR_MCEN   /*!< Master timer identifier */
00405 #define LL_HRTIM_TIMER_A                   HRTIM_MCR_TACEN  /*!< Timer A identifier */
00406 #define LL_HRTIM_TIMER_B                   HRTIM_MCR_TBCEN  /*!< Timer B identifier */
00407 #define LL_HRTIM_TIMER_C                   HRTIM_MCR_TCCEN  /*!< Timer C identifier */
00408 #define LL_HRTIM_TIMER_D                   HRTIM_MCR_TDCEN  /*!< Timer D identifier */
00409 #define LL_HRTIM_TIMER_E                   HRTIM_MCR_TECEN  /*!< Timer E identifier */
00410 #define LL_HRTIM_TIMER_X                  (HRTIM_MCR_TACEN |\
00411                                            HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
00412                                            HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
00413 #define LL_HRTIM_TIMER_ALL                (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
00414
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup HRTIM_LL_EC_OUTPUT  OUTPUT ID
00420   * @{
00421   * @brief Constants identifying an HRTIM output.
00422   */
00423 #define LL_HRTIM_OUTPUT_TA1                HRTIM_OENR_TA1OEN  /*!< Timer A - Output 1 identifier */
00424 #define LL_HRTIM_OUTPUT_TA2                HRTIM_OENR_TA2OEN  /*!< Timer A - Output 2 identifier */
00425 #define LL_HRTIM_OUTPUT_TB1                HRTIM_OENR_TB1OEN  /*!< Timer B - Output 1 identifier */
00426 #define LL_HRTIM_OUTPUT_TB2                HRTIM_OENR_TB2OEN  /*!< Timer B - Output 2 identifier */
00427 #define LL_HRTIM_OUTPUT_TC1                HRTIM_OENR_TC1OEN  /*!< Timer C - Output 1 identifier */
00428 #define LL_HRTIM_OUTPUT_TC2                HRTIM_OENR_TC2OEN  /*!< Timer C - Output 2 identifier */
00429 #define LL_HRTIM_OUTPUT_TD1                HRTIM_OENR_TD1OEN  /*!< Timer D - Output 1 identifier */
00430 #define LL_HRTIM_OUTPUT_TD2                HRTIM_OENR_TD2OEN  /*!< Timer D - Output 2 identifier */
00431 #define LL_HRTIM_OUTPUT_TE1                HRTIM_OENR_TE1OEN  /*!< Timer E - Output 1 identifier */
00432 #define LL_HRTIM_OUTPUT_TE2                HRTIM_OENR_TE2OEN  /*!< Timer E - Output 2 identifier */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup HRTIM_LL_EC_COMPAREUNIT  COMPARE UNIT ID
00438   * @{
00439   * @brief Constants identifying a compare unit.
00440   */
00441 #define LL_HRTIM_COMPAREUNIT_2             HRTIM_TIMCR_DELCMP2  /*!< Compare unit 2 identifier */
00442 #define LL_HRTIM_COMPAREUNIT_4             HRTIM_TIMCR_DELCMP4  /*!< Compare unit 4 identifier */
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT  CAPTURE UNIT ID
00448   * @{
00449   * @brief Constants identifying a capture unit.
00450   */
00451 #define LL_HRTIM_CAPTUREUNIT_1             0  /*!< Capture unit 1 identifier */
00452 #define LL_HRTIM_CAPTUREUNIT_2             1  /*!< Capture unit 2 identifier */
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup HRTIM_LL_EC_FAULT  FAULT ID
00458   * @{
00459   * @brief Constants identifying a fault channel.
00460   */
00461 #define LL_HRTIM_FAULT_1      HRTIM_FLTR_FLT1EN     /*!< Fault channel 1 identifier */
00462 #define LL_HRTIM_FAULT_2      HRTIM_FLTR_FLT2EN     /*!< Fault channel 2 identifier */
00463 #define LL_HRTIM_FAULT_3      HRTIM_FLTR_FLT3EN     /*!< Fault channel 3 identifier */
00464 #define LL_HRTIM_FAULT_4      HRTIM_FLTR_FLT4EN     /*!< Fault channel 4 identifier */
00465 #define LL_HRTIM_FAULT_5      HRTIM_FLTR_FLT5EN     /*!< Fault channel 5 identifier */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup HRTIM_LL_EC_EVENT  EXTERNAL EVENT ID
00471   * @{
00472   * @brief Constants identifying an external event channel.
00473   */
00474 #define LL_HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier */
00475 #define LL_HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier */
00476 #define LL_HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier */
00477 #define LL_HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier */
00478 #define LL_HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier */
00479 #define LL_HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier */
00480 #define LL_HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier */
00481 #define LL_HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier */
00482 #define LL_HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier */
00483 #define LL_HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier */
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE  OUTPUT STATE
00489   * @{
00490   * @brief Constants defining the state of an HRTIM output.
00491   */
00492 #define LL_HRTIM_OUTPUTSTATE_IDLE          ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
00493 #define LL_HRTIM_OUTPUTSTATE_RUN           ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
00494 #define LL_HRTIM_OUTPUTSTATE_FAULT         ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup HRTIM_LL_EC_ADCTRIG  ADC TRIGGER
00500   * @{
00501   * @brief Constants identifying an ADC trigger.
00502   */
00503 #define LL_HRTIM_ADCTRIG_1              ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
00504 #define LL_HRTIM_ADCTRIG_2              ((uint32_t)0x00000001U)  /*!< ADC trigger 2 identifier */
00505 #define LL_HRTIM_ADCTRIG_3              ((uint32_t)0x00000002U)  /*!< ADC trigger 3 identifier */
00506 #define LL_HRTIM_ADCTRIG_4              ((uint32_t)0x00000003U)  /*!< ADC trigger 4 identifier */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
00512   * @{
00513   * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
00514   */
00515 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER  0x00000000U                       /*!< HRTIM_ADCxR register update is triggered by the Master timer */
00516 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< HRTIM_ADCxR register update is triggered by the Timer A */
00517 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< HRTIM_ADCxR register update is triggered by the Timer B */
00518 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
00519 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< HRTIM_ADCxR register update is triggered by the Timer D */
00520 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13  ADC TRIGGER 1/3 SOURCE
00526   * @{
00527   * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
00528   */
00529 #define LL_HRTIM_ADCTRIG_SRC13_NONE           0x00000000U              /*!< No ADC trigger event */
00530 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1          HRTIM_ADC1R_AD1MC1       /*!< ADC Trigger on master compare 1 */
00531 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2          HRTIM_ADC1R_AD1MC2       /*!< ADC Trigger on master compare 2 */
00532 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3          HRTIM_ADC1R_AD1MC3       /*!< ADC Trigger on master compare 3 */
00533 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4          HRTIM_ADC1R_AD1MC4       /*!< ADC Trigger on master compare 4 */
00534 #define LL_HRTIM_ADCTRIG_SRC13_MPER           HRTIM_ADC1R_AD1MPER      /*!< ADC Trigger on master period */
00535 #define LL_HRTIM_ADCTRIG_SRC13_EEV1           HRTIM_ADC1R_AD1EEV1      /*!< ADC Trigger on external event 1 */
00536 #define LL_HRTIM_ADCTRIG_SRC13_EEV2           HRTIM_ADC1R_AD1EEV2      /*!< ADC Trigger on external event 2 */
00537 #define LL_HRTIM_ADCTRIG_SRC13_EEV3           HRTIM_ADC1R_AD1EEV3      /*!< ADC Trigger on external event 3 */
00538 #define LL_HRTIM_ADCTRIG_SRC13_EEV4           HRTIM_ADC1R_AD1EEV4      /*!< ADC Trigger on external event 4 */
00539 #define LL_HRTIM_ADCTRIG_SRC13_EEV5           HRTIM_ADC1R_AD1EEV5      /*!< ADC Trigger on external event 5 */
00540 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2       HRTIM_ADC1R_AD1TAC2      /*!< ADC Trigger on Timer A compare 2 */
00541 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3       HRTIM_ADC1R_AD1TAC3      /*!< ADC Trigger on Timer A compare 3 */
00542 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4       HRTIM_ADC1R_AD1TAC4      /*!< ADC Trigger on Timer A compare 4 */
00543 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER        HRTIM_ADC1R_AD1TAPER     /*!< ADC Trigger on Timer A period */
00544 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST        HRTIM_ADC1R_AD1TARST     /*!< ADC Trigger on Timer A reset */
00545 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2       HRTIM_ADC1R_AD1TBC2      /*!< ADC Trigger on Timer B compare 2 */
00546 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3       HRTIM_ADC1R_AD1TBC3      /*!< ADC Trigger on Timer B compare 3 */
00547 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4       HRTIM_ADC1R_AD1TBC4      /*!< ADC Trigger on Timer B compare 4 */
00548 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER        HRTIM_ADC1R_AD1TBPER     /*!< ADC Trigger on Timer B period */
00549 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST        HRTIM_ADC1R_AD1TBRST     /*!< ADC Trigger on Timer B reset */
00550 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2       HRTIM_ADC1R_AD1TCC2      /*!< ADC Trigger on Timer C compare 2 */
00551 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3       HRTIM_ADC1R_AD1TCC3      /*!< ADC Trigger on Timer C compare 3 */
00552 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4       HRTIM_ADC1R_AD1TCC4      /*!< ADC Trigger on Timer C compare 4 */
00553 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER        HRTIM_ADC1R_AD1TCPER     /*!< ADC Trigger on Timer C period */
00554 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2       HRTIM_ADC1R_AD1TDC2      /*!< ADC Trigger on Timer D compare 2 */
00555 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3       HRTIM_ADC1R_AD1TDC3      /*!< ADC Trigger on Timer D compare 3 */
00556 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4       HRTIM_ADC1R_AD1TDC4      /*!< ADC Trigger on Timer D compare 4 */
00557 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER        HRTIM_ADC1R_AD1TDPER     /*!< ADC Trigger on Timer D period */
00558 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2       HRTIM_ADC1R_AD1TEC2      /*!< ADC Trigger on Timer E compare 2 */
00559 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3       HRTIM_ADC1R_AD1TEC3      /*!< ADC Trigger on Timer E compare 3 */
00560 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4       HRTIM_ADC1R_AD1TEC4      /*!< ADC Trigger on Timer E compare 4 */
00561 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER        HRTIM_ADC1R_AD1TEPER     /*!< ADC Trigger on Timer E period */
00562 /**
00563   * @}
00564   */
00565
00566 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24  ADC TRIGGER 2/4 SOURCE
00567   * @{
00568   * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
00569   */
00570 #define LL_HRTIM_ADCTRIG_SRC24_NONE           0x00000000U            /*!< No ADC trigger event */
00571 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1          HRTIM_ADC2R_AD2MC1     /*!< ADC Trigger on master compare 1 */
00572 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2          HRTIM_ADC2R_AD2MC2     /*!< ADC Trigger on master compare 2 */
00573 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3          HRTIM_ADC2R_AD2MC3     /*!< ADC Trigger on master compare 3 */
00574 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4          HRTIM_ADC2R_AD2MC4     /*!< ADC Trigger on master compare 4 */
00575 #define LL_HRTIM_ADCTRIG_SRC24_MPER           HRTIM_ADC2R_AD2MPER    /*!< ADC Trigger on master period */
00576 #define LL_HRTIM_ADCTRIG_SRC24_EEV6           HRTIM_ADC2R_AD2EEV6    /*!< ADC Trigger on external event 6 */
00577 #define LL_HRTIM_ADCTRIG_SRC24_EEV7           HRTIM_ADC2R_AD2EEV7    /*!< ADC Trigger on external event 7 */
00578 #define LL_HRTIM_ADCTRIG_SRC24_EEV8           HRTIM_ADC2R_AD2EEV8    /*!< ADC Trigger on external event 8 */
00579 #define LL_HRTIM_ADCTRIG_SRC24_EEV9           HRTIM_ADC2R_AD2EEV9    /*!< ADC Trigger on external event 9 */
00580 #define LL_HRTIM_ADCTRIG_SRC24_EEV10          HRTIM_ADC2R_AD2EEV10   /*!< ADC Trigger on external event 10 */
00581 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2       HRTIM_ADC2R_AD2TAC2    /*!< ADC Trigger on Timer A compare 2 */
00582 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3       HRTIM_ADC2R_AD2TAC3    /*!< ADC Trigger on Timer A compare 3 */
00583 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4       HRTIM_ADC2R_AD2TAC4    /*!< ADC Trigger on Timer A compare 4 */
00584 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER        HRTIM_ADC2R_AD2TAPER   /*!< ADC Trigger on Timer A period */
00585 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2       HRTIM_ADC2R_AD2TBC2    /*!< ADC Trigger on Timer B compare 2 */
00586 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3       HRTIM_ADC2R_AD2TBC3    /*!< ADC Trigger on Timer B compare 3 */
00587 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4       HRTIM_ADC2R_AD2TBC4    /*!< ADC Trigger on Timer B compare 4 */
00588 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER        HRTIM_ADC2R_AD2TBPER   /*!< ADC Trigger on Timer B period */
00589 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2       HRTIM_ADC2R_AD2TCC2    /*!< ADC Trigger on Timer C compare 2 */
00590 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3       HRTIM_ADC2R_AD2TCC3    /*!< ADC Trigger on Timer C compare 3 */
00591 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4       HRTIM_ADC2R_AD2TCC4    /*!< ADC Trigger on Timer C compare 4 */
00592 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER        HRTIM_ADC2R_AD2TCPER   /*!< ADC Trigger on Timer C period */
00593 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST        HRTIM_ADC2R_AD2TCRST   /*!< ADC Trigger on Timer C reset */
00594 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2       HRTIM_ADC2R_AD2TDC2    /*!< ADC Trigger on Timer D compare 2 */
00595 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3       HRTIM_ADC2R_AD2TDC3    /*!< ADC Trigger on Timer D compare 3 */
00596 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4       HRTIM_ADC2R_AD2TDC4    /*!< ADC Trigger on Timer D compare 4 */
00597 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER        HRTIM_ADC2R_AD2TDPER   /*!< ADC Trigger on Timer D period */
00598 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST        HRTIM_ADC2R_AD2TDRST   /*!< ADC Trigger on Timer D reset */
00599 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2       HRTIM_ADC2R_AD2TEC2    /*!< ADC Trigger on Timer E compare 2 */
00600 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3       HRTIM_ADC2R_AD2TEC3    /*!< ADC Trigger on Timer E compare 3 */
00601 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4       HRTIM_ADC2R_AD2TEC4    /*!< ADC Trigger on Timer E compare 4 */
00602 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST        HRTIM_ADC2R_AD2TERST   /*!< ADC Trigger on Timer E reset */
00603 /**
00604   * @}
00605   */
00606
00607 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO  PRESCALER RATIO
00608   * @{
00609   * @brief Constants defining timer high-resolution clock prescaler ratio.
00610   */
00611 #define LL_HRTIM_PRESCALERRATIO_MUL32      0x00000000U              /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)      */
00612 #define LL_HRTIM_PRESCALERRATIO_MUL16      ((uint32_t)0x00000001U)  /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)      */
00613 #define LL_HRTIM_PRESCALERRATIO_MUL8       ((uint32_t)0x00000002U)  /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)      */
00614 #define LL_HRTIM_PRESCALERRATIO_MUL4       ((uint32_t)0x00000003U)  /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)      */
00615 #define LL_HRTIM_PRESCALERRATIO_MUL2       ((uint32_t)0x00000004U)  /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)      */
00616 #define LL_HRTIM_PRESCALERRATIO_DIV1       ((uint32_t)0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */
00617 #define LL_HRTIM_PRESCALERRATIO_DIV2       ((uint32_t)0x00000006U)  /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */
00618 #define LL_HRTIM_PRESCALERRATIO_DIV4       ((uint32_t)0x00000007U)  /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup HRTIM_LL_EC_MODE  COUNTER MODE
00624   * @{
00625   * @brief Constants defining timer counter operating mode.
00626   */
00627 #define LL_HRTIM_MODE_CONTINUOUS           ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00628 #define LL_HRTIM_MODE_SINGLESHOT           0x00000000U              /*!< The timer operates in non retriggerable single-shot mode */
00629 #define LL_HRTIM_MODE_RETRIGGERABLE        ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00630 /**
00631   * @}
00632   */
00633
00634 /** @defgroup HRTIM_LL_EC_DACTRIG  DAC TRIGGER
00635   * @{
00636   * @brief Constants defining on which output the DAC synchronization event is sent.
00637   */
00638 #define LL_HRTIM_DACTRIG_NONE           0x00000000U                     /*!< No DAC synchronization event generated */
00639 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1   (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00640 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2   (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00641 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3   (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
00642 /**
00643   * @}
00644   */
00645
00646 /** @defgroup HRTIM_LL_EC_UPDATETRIG  UPDATE TRIGGER
00647   * @{
00648   * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
00649   */
00650 #define LL_HRTIM_UPDATETRIG_NONE        0x00000000U            /*!< Register update is disabled */
00651 #define LL_HRTIM_UPDATETRIG_MASTER      HRTIM_TIMCR_MSTU       /*!< Register update is triggered by the master timer update */
00652 #define LL_HRTIM_UPDATETRIG_TIMER_A     HRTIM_TIMCR_TAU        /*!< Register update is triggered by the timer A update */
00653 #define LL_HRTIM_UPDATETRIG_TIMER_B     HRTIM_TIMCR_TBU        /*!< Register update is triggered by the timer B update */
00654 #define LL_HRTIM_UPDATETRIG_TIMER_C     HRTIM_TIMCR_TCU        /*!< Register update is triggered by the timer C update*/
00655 #define LL_HRTIM_UPDATETRIG_TIMER_D     HRTIM_TIMCR_TDU        /*!< Register update is triggered by the timer D update */
00656 #define LL_HRTIM_UPDATETRIG_TIMER_E     HRTIM_TIMCR_TEU        /*!< Register update is triggered by the timer E update */
00657 #define LL_HRTIM_UPDATETRIG_REPETITION  HRTIM_TIMCR_TREPU      /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
00658 #define LL_HRTIM_UPDATETRIG_RESET       HRTIM_TIMCR_TRSTU      /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
00659 /**
00660   * @}
00661   */
00662
00663 /** @defgroup HRTIM_LL_EC_UPDATEGATING  UPDATE GATING
00664   * @{
00665   * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
00666   */
00667 #define LL_HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                               /*!< Update done independently from the DMA burst transfer completion */
00668 #define LL_HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00669 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00670 #define LL_HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
00671 #define LL_HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
00672 #define LL_HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
00673 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1 */
00674 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
00675 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup HRTIM_LL_EC_COMPAREMODE  COMPARE MODE
00681   * @{
00682   * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
00683   */
00684 #define LL_HRTIM_COMPAREMODE_REGULAR          0x00000000U                         /*!< standard compare mode */
00685 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT  (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
00686 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1       (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
00687 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3       (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup HRTIM_LL_EC_RESETTRIG  RESET TRIGGER
00693   * @{
00694   * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
00695   */
00696 #define LL_HRTIM_RESETTRIG_NONE        0x00000000U            /*!< No counter reset trigger */
00697 #define LL_HRTIM_RESETTRIG_UPDATE      HRTIM_RSTR_UPDATE      /*!< The timer counter is reset upon update event */
00698 #define LL_HRTIM_RESETTRIG_CMP2        HRTIM_RSTR_CMP2        /*!< The timer counter is reset upon Timer Compare 2 event */
00699 #define LL_HRTIM_RESETTRIG_CMP4        HRTIM_RSTR_CMP4        /*!< The timer counter is reset upon Timer Compare 4 event */
00700 #define LL_HRTIM_RESETTRIG_MASTER_PER  HRTIM_RSTR_MSTPER      /*!< The timer counter is reset upon master timer period event */
00701 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1     /*!< The timer counter is reset upon master timer Compare 1 event */
00702 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2     /*!< The timer counter is reset upon master timer Compare 2 event */
00703 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3     /*!< The timer counter is reset upon master timer Compare 3 event */
00704 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4     /*!< The timer counter is reset upon master timer Compare 4 event */
00705 #define LL_HRTIM_RESETTRIG_EEV_1       HRTIM_RSTR_EXTEVNT1    /*!< The timer counter is reset upon external event 1 */
00706 #define LL_HRTIM_RESETTRIG_EEV_2       HRTIM_RSTR_EXTEVNT2    /*!< The timer counter is reset upon external event 2 */
00707 #define LL_HRTIM_RESETTRIG_EEV_3       HRTIM_RSTR_EXTEVNT3    /*!< The timer counter is reset upon external event 3 */
00708 #define LL_HRTIM_RESETTRIG_EEV_4       HRTIM_RSTR_EXTEVNT4    /*!< The timer counter is reset upon external event 4 */
00709 #define LL_HRTIM_RESETTRIG_EEV_5       HRTIM_RSTR_EXTEVNT5    /*!< The timer counter is reset upon external event 5 */
00710 #define LL_HRTIM_RESETTRIG_EEV_6       HRTIM_RSTR_EXTEVNT6    /*!< The timer counter is reset upon external event 6 */
00711 #define LL_HRTIM_RESETTRIG_EEV_7       HRTIM_RSTR_EXTEVNT7    /*!< The timer counter is reset upon external event 7 */
00712 #define LL_HRTIM_RESETTRIG_EEV_8       HRTIM_RSTR_EXTEVNT8    /*!< The timer counter is reset upon external event 8 */
00713 #define LL_HRTIM_RESETTRIG_EEV_9       HRTIM_RSTR_EXTEVNT9    /*!< The timer counter is reset upon external event 9 */
00714 #define LL_HRTIM_RESETTRIG_EEV_10      HRTIM_RSTR_EXTEVNT10   /*!< The timer counter is reset upon external event 10 */
00715 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00716 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00717 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00718 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00719 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00720 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00721 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00722 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00723 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00724 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
00725 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
00726 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup HRTIM_LL_EC_CAPTURETRIG  CAPTURE TRIGGER
00732   * @{
00733   * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
00734   */
00735 #define LL_HRTIM_CAPTURETRIG_NONE         ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
00736 #define LL_HRTIM_CAPTURETRIG_UPDATE       HRTIM_CPT1CR_UPDCPT    /*!< The update event triggers the Capture */
00737 #define LL_HRTIM_CAPTURETRIG_EEV_1        HRTIM_CPT1CR_EXEV1CPT  /*!< The External event 1 triggers the Capture */
00738 #define LL_HRTIM_CAPTURETRIG_EEV_2        HRTIM_CPT1CR_EXEV2CPT  /*!< The External event 2 triggers the Capture */
00739 #define LL_HRTIM_CAPTURETRIG_EEV_3        HRTIM_CPT1CR_EXEV3CPT  /*!< The External event 3 triggers the Capture */
00740 #define LL_HRTIM_CAPTURETRIG_EEV_4        HRTIM_CPT1CR_EXEV4CPT  /*!< The External event 4 triggers the Capture */
00741 #define LL_HRTIM_CAPTURETRIG_EEV_5        HRTIM_CPT1CR_EXEV5CPT  /*!< The External event 5 triggers the Capture */
00742 #define LL_HRTIM_CAPTURETRIG_EEV_6        HRTIM_CPT1CR_EXEV6CPT  /*!< The External event 6 triggers the Capture */
00743 #define LL_HRTIM_CAPTURETRIG_EEV_7        HRTIM_CPT1CR_EXEV7CPT  /*!< The External event 7 triggers the Capture */
00744 #define LL_HRTIM_CAPTURETRIG_EEV_8        HRTIM_CPT1CR_EXEV8CPT  /*!< The External event 8 triggers the Capture */
00745 #define LL_HRTIM_CAPTURETRIG_EEV_9        HRTIM_CPT1CR_EXEV9CPT  /*!< The External event 9 triggers the Capture */
00746 #define LL_HRTIM_CAPTURETRIG_EEV_10       HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
00747 #define LL_HRTIM_CAPTURETRIG_TA1_SET      HRTIM_CPT1CR_TA1SET    /*!< Capture is triggered by TA1 output inactive to active transition */
00748 #define LL_HRTIM_CAPTURETRIG_TA1_RESET    HRTIM_CPT1CR_TA1RST    /*!< Capture is triggered by TA1 output active to inactive transition */
00749 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1    HRTIM_CPT1CR_TIMACMP1  /*!< Timer A Compare 1 triggers Capture */
00750 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2    HRTIM_CPT1CR_TIMACMP2  /*!< Timer A Compare 2 triggers Capture */
00751 #define LL_HRTIM_CAPTURETRIG_TB1_SET      HRTIM_CPT1CR_TB1SET    /*!< Capture is triggered by TB1 output inactive to active transition */
00752 #define LL_HRTIM_CAPTURETRIG_TB1_RESET    HRTIM_CPT1CR_TB1RST    /*!< Capture is triggered by TB1 output active to inactive transition */
00753 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1    HRTIM_CPT1CR_TIMBCMP1  /*!< Timer B Compare 1 triggers Capture */
00754 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2    HRTIM_CPT1CR_TIMBCMP2  /*!< Timer B Compare 2 triggers Capture */
00755 #define LL_HRTIM_CAPTURETRIG_TC1_SET      HRTIM_CPT1CR_TC1SET    /*!< Capture is triggered by TC1 output inactive to active transition */
00756 #define LL_HRTIM_CAPTURETRIG_TC1_RESET    HRTIM_CPT1CR_TC1RST    /*!< Capture is triggered by TC1 output active to inactive transition */
00757 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1    HRTIM_CPT1CR_TIMCCMP1  /*!< Timer C Compare 1 triggers Capture */
00758 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2    HRTIM_CPT1CR_TIMCCMP2  /*!< Timer C Compare 2 triggers Capture */
00759 #define LL_HRTIM_CAPTURETRIG_TD1_SET      HRTIM_CPT1CR_TD1SET    /*!< Capture is triggered by TD1 output inactive to active transition */
00760 #define LL_HRTIM_CAPTURETRIG_TD1_RESET    HRTIM_CPT1CR_TD1RST    /*!< Capture is triggered by TD1 output active to inactive transition */
00761 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1    HRTIM_CPT1CR_TIMDCMP1  /*!< Timer D Compare 1 triggers Capture */
00762 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2    HRTIM_CPT1CR_TIMDCMP2  /*!< Timer D Compare 2 triggers Capture */
00763 #define LL_HRTIM_CAPTURETRIG_TE1_SET      HRTIM_CPT1CR_TE1SET    /*!< Capture is triggered by TE1 output inactive to active transition */
00764 #define LL_HRTIM_CAPTURETRIG_TE1_RESET    HRTIM_CPT1CR_TE1RST    /*!< Capture is triggered by TE1 output active to inactive transition */
00765 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1    HRTIM_CPT1CR_TIMECMP1  /*!< Timer E Compare 1 triggers Capture */
00766 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2    HRTIM_CPT1CR_TIMECMP2  /*!< Timer E Compare 2 triggers Capture */
00767 /**
00768   * @}
00769   */
00770
00771 /** @defgroup HRTIM_LL_EC_DLYPRT  DELAYED PROTECTION (DLYPRT) MODE
00772   * @{
00773   * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
00774   */
00775 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6  0x00000000U                                            /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
00776 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
00777 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
00778 #define LL_HRTIM_DLYPRT_BALANCED_EEV6   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Balanced Idle on external Event 6 */
00779 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7  (HRTIM_OUTR_DLYPRT_2)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
00780 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
00781 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
00782 #define LL_HRTIM_DLYPRT_BALANCED_EEV7   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
00783
00784 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8  0x00000000U                                             /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
00785 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
00786 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
00787 #define LL_HRTIM_DLYPRT_BALANCED_EEV8   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Balanced Idle on external Event 8 */
00788 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9  (HRTIM_OUTR_DLYPRT_2)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
00789 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
00790 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
00791 #define LL_HRTIM_DLYPRT_BALANCED_EEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)   /*!< Timers D, E: Balanced Idle on external Event 9 */
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup HRTIM_LL_EC_BURSTMODE  BURST MODE
00797   * @{
00798   * @brief Constants defining how the timer behaves during a burst mode operation.
00799   */
00800 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
00801 #define LL_HRTIM_BURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */
00802 /**
00803   * @}
00804   */
00805
00806 /** @defgroup HRTIM_LL_EC_BURSTDMA  BURST DMA
00807   * @{
00808   * @brief Constants defining the registers that can be written during a burst DMA operation.
00809   */
00810 #define LL_HRTIM_BURSTDMA_NONE     0x00000000U               /*!< No register is updated by Burst DMA accesses */
00811 #define LL_HRTIM_BURSTDMA_MCR      (HRTIM_BDMUPR_MCR)        /*!< MCR  register is updated by Burst DMA accesses */
00812 #define LL_HRTIM_BURSTDMA_MICR     (HRTIM_BDMUPR_MICR)       /*!< MICR register is updated by Burst DMA accesses */
00813 #define LL_HRTIM_BURSTDMA_MDIER    (HRTIM_BDMUPR_MDIER)      /*!< MDIER register is updated by Burst DMA accesses */
00814 #define LL_HRTIM_BURSTDMA_MCNT     (HRTIM_BDMUPR_MCNT)       /*!< MCNTR register is updated by Burst DMA accesses */
00815 #define LL_HRTIM_BURSTDMA_MPER     (HRTIM_BDMUPR_MPER)       /*!< MPER register is updated by Burst DMA accesses */
00816 #define LL_HRTIM_BURSTDMA_MREP     (HRTIM_BDMUPR_MREP)       /*!< MREPR register is updated by Burst DMA accesses */
00817 #define LL_HRTIM_BURSTDMA_MCMP1    (HRTIM_BDMUPR_MCMP1)      /*!< MCMP1R register is updated by Burst DMA accesses */
00818 #define LL_HRTIM_BURSTDMA_MCMP2    (HRTIM_BDMUPR_MCMP2)      /*!< MCMP2R register is updated by Burst DMA accesses */
00819 #define LL_HRTIM_BURSTDMA_MCMP3    (HRTIM_BDMUPR_MCMP3)      /*!< MCMP3R register is updated by Burst DMA accesses */
00820 #define LL_HRTIM_BURSTDMA_MCMP4    (HRTIM_BDMUPR_MCMP4)      /*!< MCMP4R register is updated by Burst DMA accesses */
00821 #define LL_HRTIM_BURSTDMA_TIMMCR   (HRTIM_BDTUPR_TIMCR)      /*!< TIMxCR register is updated by Burst DMA accesses */
00822 #define LL_HRTIM_BURSTDMA_TIMICR   (HRTIM_BDTUPR_TIMICR)     /*!< TIMxICR register is updated by Burst DMA accesses */
00823 #define LL_HRTIM_BURSTDMA_TIMDIER  (HRTIM_BDTUPR_TIMDIER)    /*!< TIMxDIER register is updated by Burst DMA accesses */
00824 #define LL_HRTIM_BURSTDMA_TIMCNT   (HRTIM_BDTUPR_TIMCNT)     /*!< CNTxCR register is updated by Burst DMA accesses */
00825 #define LL_HRTIM_BURSTDMA_TIMPER   (HRTIM_BDTUPR_TIMPER)     /*!< PERxR register is updated by Burst DMA accesses */
00826 #define LL_HRTIM_BURSTDMA_TIMREP   (HRTIM_BDTUPR_TIMREP)     /*!< REPxR register is updated by Burst DMA accesses */
00827 #define LL_HRTIM_BURSTDMA_TIMCMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< CMP1xR register is updated by Burst DMA accesses */
00828 #define LL_HRTIM_BURSTDMA_TIMCMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< CMP2xR register is updated by Burst DMA accesses */
00829 #define LL_HRTIM_BURSTDMA_TIMCMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< CMP3xR register is updated by Burst DMA accesses */
00830 #define LL_HRTIM_BURSTDMA_TIMCMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< CMP4xR register is updated by Burst DMA accesses */
00831 #define LL_HRTIM_BURSTDMA_TIMDTR   (HRTIM_BDTUPR_TIMDTR)     /*!< DTxR register is updated by Burst DMA accesses */
00832 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
00833 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
00834 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
00835 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
00836 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
00837 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
00838 #define LL_HRTIM_BURSTDMA_TIMRSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
00839 #define LL_HRTIM_BURSTDMA_TIMCHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
00840 #define LL_HRTIM_BURSTDMA_TIMOUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
00841 #define LL_HRTIM_BURSTDMA_TIMFLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
00842 /**
00843   * @}
00844   */
00845
00846 /** @defgroup HRTIM_LL_EC_CPPSTAT  CURRENT PUSH-PULL STATUS
00847   * @{
00848   * @brief Constants defining on which output the signal is currently applied in push-pull mode.
00849   */
00850 #define LL_HRTIM_CPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
00851 #define LL_HRTIM_CPPSTAT_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
00852 /**
00853   * @}
00854   */
00855
00856 /** @defgroup HRTIM_LL_EC_IPPSTAT  IDLE PUSH-PULL STATUS
00857   * @{
00858   * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
00859   */
00860 #define LL_HRTIM_IPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U)    /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
00861 #define LL_HRTIM_IPPSTAT_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
00862 /**
00863   * @}
00864   */
00865
00866 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
00867   * @{
00868   * @brief Constants defining the event filtering applied to external events by a timer.
00869   */
00870 #define LL_HRTIM_EEFLTR_NONE             (0x00000000U)
00871 #define LL_HRTIM_EEFLTR_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                         /*!< Blanking from counter reset/roll-over to Compare 1 */
00872 #define LL_HRTIM_EEFLTR_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                         /*!< Blanking from counter reset/roll-over to Compare 2 */
00873 #define LL_HRTIM_EEFLTR_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from counter reset/roll-over to Compare 3 */
00874 #define LL_HRTIM_EEFLTR_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                         /*!< Blanking from counter reset/roll-over to Compare 4 */
00875 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from another timing unit: TIMFLTR1 source */
00876 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                 /*!< Blanking from another timing unit: TIMFLTR2 source */
00877 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Blanking from another timing unit: TIMFLTR3 source */
00878 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                         /*!< Blanking from another timing unit: TIMFLTR4 source */
00879 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from another timing unit: TIMFLTR5 source */
00880 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                 /*!< Blanking from another timing unit: TIMFLTR6 source */
00881 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Blanking from another timing unit: TIMFLTR7 source */
00882 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                 /*!< Blanking from another timing unit: TIMFLTR8 source */
00883 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Windowing from counter reset/roll-over to Compare 2 */
00884 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                         /*!< Windowing from counter reset/roll-over to Compare 3 */
00885 #define LL_HRTIM_EEFLTR_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
00891   * @{
00892   * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
00893   */
00894 #define LL_HRTIM_EELATCH_DISABLED    0x00000000U             /*!< Event is ignored if it happens during a blank, or passed through during a window */
00895 #define LL_HRTIM_EELATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
00896 /**
00897   * @}
00898   */
00899
00900 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
00901   * @{
00902   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
00903   */
00904 #define LL_HRTIM_DT_PRESCALER_MUL8    0x00000000U                                         /*!< fDTG = fHRTIM * 8 */
00905 #define LL_HRTIM_DT_PRESCALER_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4 */
00906 #define LL_HRTIM_DT_PRESCALER_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2 */
00907 #define LL_HRTIM_DT_PRESCALER_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
00908 #define LL_HRTIM_DT_PRESCALER_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2 */
00909 #define LL_HRTIM_DT_PRESCALER_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4 */
00910 #define LL_HRTIM_DT_PRESCALER_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8 */
00911 #define LL_HRTIM_DT_PRESCALER_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16 */
00912 /**
00913   * @}
00914   */
00915
00916 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
00917   * @{
00918   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
00919   */
00920 #define LL_HRTIM_DT_RISING_POSITIVE    0x00000000U             /*!< Positive deadtime on rising edge */
00921 #define LL_HRTIM_DT_RISING_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */
00922 /**
00923   * @}
00924   */
00925
00926 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
00927   * @{
00928   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
00929   */
00930 #define LL_HRTIM_DT_FALLING_POSITIVE    0x00000000U             /*!< Positive deadtime on falling edge */
00931 #define LL_HRTIM_DT_FALLING_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */
00932 /**
00933   * @}
00934   */
00935
00936 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
00937   * @{
00938   * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
00939   */
00940 #define LL_HRTIM_CHP_PRESCALER_DIV16  0x00000000U                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
00941 #define LL_HRTIM_CHP_PRESCALER_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
00942 #define LL_HRTIM_CHP_PRESCALER_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
00943 #define LL_HRTIM_CHP_PRESCALER_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
00944 #define LL_HRTIM_CHP_PRESCALER_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
00945 #define LL_HRTIM_CHP_PRESCALER_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
00946 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
00947 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
00948 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
00949 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
00950 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
00951 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
00952 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
00953 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
00954 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
00955 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
00961   * @{
00962   * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
00963   */
00964 #define LL_HRTIM_CHP_DUTYCYCLE_0    0x00000000U                                              /*!< Only 1st pulse is present */
00965 #define LL_HRTIM_CHP_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 % */
00966 #define LL_HRTIM_CHP_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 % */
00967 #define LL_HRTIM_CHP_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 % */
00968 #define LL_HRTIM_CHP_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 % */
00969 #define LL_HRTIM_CHP_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 % */
00970 #define LL_HRTIM_CHP_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 % */
00971 #define LL_HRTIM_CHP_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
00977   * @{
00978   * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
00979   */
00980 #define LL_HRTIM_CHP_PULSEWIDTH_16   0x00000000U                                                                 /*!< tSTPW = tHRTIM x 16  */
00981 #define LL_HRTIM_CHP_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
00982 #define LL_HRTIM_CHP_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
00983 #define LL_HRTIM_CHP_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
00984 #define LL_HRTIM_CHP_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
00985 #define LL_HRTIM_CHP_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
00986 #define LL_HRTIM_CHP_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
00987 #define LL_HRTIM_CHP_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
00988 #define LL_HRTIM_CHP_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
00989 #define LL_HRTIM_CHP_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
00990 #define LL_HRTIM_CHP_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
00991 #define LL_HRTIM_CHP_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
00992 #define LL_HRTIM_CHP_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
00993 #define LL_HRTIM_CHP_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
00994 #define LL_HRTIM_CHP_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
00995 #define LL_HRTIM_CHP_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
00996 /**
00997   * @}
00998   */
00999
01000 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT
01001   * @{
01002   * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
01003   */
01004 #define LL_HRTIM_CROSSBAR_NONE       0x00000000U             /*!< Reset the output set crossbar */
01005 #define LL_HRTIM_CROSSBAR_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
01006 #define LL_HRTIM_CROSSBAR_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces an output level transision */
01007 #define LL_HRTIM_CROSSBAR_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces an output level transision */
01008 #define LL_HRTIM_CROSSBAR_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces an output level transision */
01009 #define LL_HRTIM_CROSSBAR_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces an output level transision */
01010 #define LL_HRTIM_CROSSBAR_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces an output level transision */
01011 #define LL_HRTIM_CROSSBAR_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces an output level transision */
01012 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces an output level transision */
01013 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces an output level transision */
01014 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces an output level transision */
01015 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces an output level transision */
01016 #define LL_HRTIM_CROSSBAR_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces an output level transision */
01017 #define LL_HRTIM_CROSSBAR_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces an output level transision */
01018 #define LL_HRTIM_CROSSBAR_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces an output level transision */
01019 #define LL_HRTIM_CROSSBAR_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces an output level transision */
01020 #define LL_HRTIM_CROSSBAR_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces an output level transision */
01021 #define LL_HRTIM_CROSSBAR_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces an output level transision */
01022 #define LL_HRTIM_CROSSBAR_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces an output level transision */
01023 #define LL_HRTIM_CROSSBAR_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces an output level transision */
01024 #define LL_HRTIM_CROSSBAR_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces an output level transision */
01025 #define LL_HRTIM_CROSSBAR_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces an output level transision */
01026 #define LL_HRTIM_CROSSBAR_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces an output level transision */
01027 #define LL_HRTIM_CROSSBAR_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces an output level transision */
01028 #define LL_HRTIM_CROSSBAR_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces an output level transision */
01029 #define LL_HRTIM_CROSSBAR_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces an output level transision */
01030 #define LL_HRTIM_CROSSBAR_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces an output level transision */
01031 #define LL_HRTIM_CROSSBAR_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces an output level transision */
01032 #define LL_HRTIM_CROSSBAR_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces an output level transision */
01033 #define LL_HRTIM_CROSSBAR_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces an output level transision */
01034 #define LL_HRTIM_CROSSBAR_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces an output level transision */
01035 #define LL_HRTIM_CROSSBAR_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces an output level transision */
01036 /**
01037   * @}
01038   */
01039
01040 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
01041   * @{
01042   * @brief Constants defining the polarity of a timer output.
01043   */
01044 #define LL_HRTIM_OUT_POSITIVE_POLARITY    0x00000000U             /*!< Output is acitve HIGH */
01045 #define LL_HRTIM_OUT_NEGATIVE_POLARITY    (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
01046 /**
01047   * @}
01048   */
01049
01050 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
01051   * @{
01052   * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
01053   */
01054 #define LL_HRTIM_OUT_NO_IDLE             0x00000000U            /*!< The output is not affected by the burst mode operation */
01055 #define LL_HRTIM_OUT_IDLE_WHEN_BURST     (HRTIM_OUTR_IDLM1)     /*!< The output is in idle state when requested by the burst mode controller */
01056 /**
01057   * @}
01058   */
01059
01060 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
01061   * @{
01062   * @brief Constants defining the half mode of an HRTIM Timer instance.
01063   */
01064 #define LL_HRTIM_HALF_MODE_DISABLED          0x000U              /*!< HRTIM Half Mode is disabled */
01065 #define LL_HRTIM_HALF_MODE_ENABLE            HRTIM_MCR_HALF      /*!< HRTIM Half Mode is Half */
01066 /**
01067   * @}
01068   */
01069
01070 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
01071   * @{
01072   * @brief Constants defining the output level when output is in IDLE state
01073   */
01074 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
01075 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
01076 /**
01077   * @}
01078   */
01079
01080 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
01081   * @{
01082   * @brief Constants defining the output level when output is in FAULT state.
01083   */
01084 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U                      /*!< The output is not affected by the fault input */
01085 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
01086 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
01087 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
01088 /**
01089   * @}
01090   */
01091
01092 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
01093   * @{
01094   * @brief Constants defining whether or not chopper mode is enabled for a timer output.
01095   */
01096 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED   0x00000000U             /*!< Output signal is not altered  */
01097 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)       /*!< Output signal is chopped by a carrier signal  */
01098 /**
01099   * @}
01100   */
01101
01102 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
01103   * @{
01104   * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
01105 during a programmable period before the output takes its idle state.
01106   */
01107 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR   0x00000000U            /*!< The programmed Idle state is applied immediately to the Output */
01108 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED   (HRTIM_OUTR_DIDL1)     /*!< Deadtime is inserted on output before entering the idle mode */
01109 /**
01110   * @}
01111   */
01112 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
01113   * @{
01114   * @brief Constants defining the level of a timer output.
01115   */
01116 #define LL_HRTIM_OUT_LEVEL_INACTIVE   0x00000000U            /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
01117 #define LL_HRTIM_OUT_LEVEL_ACTIVE     ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
01118 /**
01119   * @}
01120   */
01121
01122 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
01123   * @{
01124   * @brief Constants defining available sources associated to external events.
01125   */
01126 #define LL_HRTIM_EE_SRC_1         0x00000000U                                    /*!< External event source 1 (EExSrc1)*/
01127 #define LL_HRTIM_EE_SRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2 (EExSrc2) */
01128 #define LL_HRTIM_EE_SRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3 (EExSrc3) */
01129 #define LL_HRTIM_EE_SRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4 (EExSrc4) */
01130 /**
01131   * @}
01132   */
01133 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
01134   * @{
01135   * @brief Constants defining the polarity of an external event.
01136   */
01137 #define LL_HRTIM_EE_POLARITY_HIGH    0x00000000U             /*!< External event is active high */
01138 #define LL_HRTIM_EE_POLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01139 /**
01140   * @}
01141   */
01142
01143 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
01144   * @{
01145   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
01146   */
01147 #define LL_HRTIM_EE_SENSITIVITY_LEVEL          0x00000000U                        /*!< External event is active on level */
01148 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01149 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01150 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01151 /**
01152   * @}
01153   */
01154
01155 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
01156   * @{
01157   * @brief Constants defining whether or not an external event is programmed in fast mode.
01158   */
01159 #define LL_HRTIM_EE_FASTMODE_DISABLE         0x00000000U              /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01160 #define LL_HRTIM_EE_FASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is acting asynchronously on outputs (low latency mode) */
01161 /**
01162   * @}
01163   */
01164
01165 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
01166   * @{
01167   * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
01168   */
01169 #define LL_HRTIM_EE_FILTER_NONE      0x00000000U                                                               /*!< Filter disabled */
01170 #define LL_HRTIM_EE_FILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING = fHRTIM, N=2 */
01171 #define LL_HRTIM_EE_FILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING = fHRTIM, N=4 */
01172 #define LL_HRTIM_EE_FILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fHRTIM, N=8 */
01173 #define LL_HRTIM_EE_FILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING = fEEVS/2, N=6 */
01174 #define LL_HRTIM_EE_FILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/2, N=8 */
01175 #define LL_HRTIM_EE_FILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/4, N=6 */
01176 #define LL_HRTIM_EE_FILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/4, N=8 */
01177 #define LL_HRTIM_EE_FILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING = fEEVS/8, N=6 */
01178 #define LL_HRTIM_EE_FILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/8, N=8 */
01179 #define LL_HRTIM_EE_FILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/16, N=5 */
01180 #define LL_HRTIM_EE_FILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/16, N=6 */
01181 #define LL_HRTIM_EE_FILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING = fEEVS/16, N=8 */
01182 #define LL_HRTIM_EE_FILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING = fEEVS/32, N=5 */
01183 #define LL_HRTIM_EE_FILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING = fEEVS/32, N=6 */
01184 #define LL_HRTIM_EE_FILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING = fEEVS/32, N=8 */
01185 /**
01186   * @}
01187   */
01188
01189 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
01190   * @{
01191   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
01192   */
01193 #define LL_HRTIM_EE_PRESCALER_DIV1    0x00000000U                     /*!< fEEVS = fHRTIM */
01194 #define LL_HRTIM_EE_PRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                       /*!< fEEVS = fHRTIM / 2 */
01195 #define LL_HRTIM_EE_PRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                       /*!< fEEVS = fHRTIM / 4 */
01196 #define LL_HRTIM_EE_PRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
01197 /**
01198   * @}
01199   */
01200
01201 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
01202   * @{
01203   * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
01204   */
01205 #define LL_HRTIM_FLT_SRC_DIGITALINPUT         0x00000000U                /*!< Fault input is FLT input pin */
01206 #define LL_HRTIM_FLT_SRC_INTERNAL             HRTIM_FLTINR1_FLT1SRC      /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01207 /**
01208   * @}
01209   */
01210
01211 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
01212   * @{
01213   * @brief Constants defining the polarity of a fault event.
01214   */
01215 #define LL_HRTIM_FLT_POLARITY_LOW     0x00000000U                /*!< Fault input is active low */
01216 #define LL_HRTIM_FLT_POLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)      /*!< Fault input is active high */
01217 /**
01218   * @}
01219   */
01220
01221 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
01222   * @{
01223   * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
01224   */
01225 #define LL_HRTIM_FLT_FILTER_NONE      0x00000000U                                                                          /*!< Filter disabled */
01226 #define LL_HRTIM_FLT_FILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2 */
01227 #define LL_HRTIM_FLT_FILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4 */
01228 #define LL_HRTIM_FLT_FILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8 */
01229 #define LL_HRTIM_FLT_FILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6 */
01230 #define LL_HRTIM_FLT_FILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8 */
01231 #define LL_HRTIM_FLT_FILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6 */
01232 #define LL_HRTIM_FLT_FILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8 */
01233 #define LL_HRTIM_FLT_FILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6 */
01234 #define LL_HRTIM_FLT_FILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8 */
01235 #define LL_HRTIM_FLT_FILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5 */
01236 #define LL_HRTIM_FLT_FILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6 */
01237 #define LL_HRTIM_FLT_FILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8 */
01238 #define LL_HRTIM_FLT_FILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5 */
01239 #define LL_HRTIM_FLT_FILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6 */
01240 #define LL_HRTIM_FLT_FILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8 */
01241 /**
01242   * @}
01243   */
01244
01245 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
01246   * @{
01247   * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used  by the digital filters.
01248   */
01249 #define LL_HRTIM_FLT_PRESCALER_DIV1    0x00000000U                                     /*!< fFLTS = fHRTIM */
01250 #define LL_HRTIM_FLT_PRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                         /*!< fFLTS = fHRTIM / 2 */
01251 #define LL_HRTIM_FLT_PRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                         /*!< fFLTS = fHRTIM / 4 */
01252 #define LL_HRTIM_FLT_PRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
01253 /**
01254   * @}
01255   */
01256
01257 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
01258   * @{
01259   * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
01260   */
01261 #define LL_HRTIM_BM_MODE_SINGLESHOT  0x00000000U            /*!< Burst mode operates in single shot mode */
01262 #define LL_HRTIM_BM_MODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
01263 /**
01264   * @}
01265   */
01266
01267 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
01268   * @{
01269   * @brief Constants defining the clock source for the burst mode counter.
01270   */
01271 #define LL_HRTIM_BM_CLKSRC_MASTER     0x00000000U                                         /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
01272 #define LL_HRTIM_BM_CLKSRC_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
01273 #define LL_HRTIM_BM_CLKSRC_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
01274 #define LL_HRTIM_BM_CLKSRC_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
01275 #define LL_HRTIM_BM_CLKSRC_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
01276 #define LL_HRTIM_BM_CLKSRC_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
01277 #define LL_HRTIM_BM_CLKSRC_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
01278 #define LL_HRTIM_BM_CLKSRC_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
01279 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
01280 #define LL_HRTIM_BM_CLKSRC_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
01281 /**
01282   * @}
01283   */
01284
01285 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
01286   * @{
01287   * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
01288   */
01289 #define LL_HRTIM_BM_PRESCALER_DIV1     0x00000000U                                                                 /*!< fBRST = fHRTIM */
01290 #define LL_HRTIM_BM_PRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2 */
01291 #define LL_HRTIM_BM_PRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4 */
01292 #define LL_HRTIM_BM_PRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8 */
01293 #define LL_HRTIM_BM_PRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16 */
01294 #define LL_HRTIM_BM_PRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32 */
01295 #define LL_HRTIM_BM_PRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64 */
01296 #define LL_HRTIM_BM_PRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128 */
01297 #define LL_HRTIM_BM_PRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256 */
01298 #define LL_HRTIM_BM_PRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512 */
01299 #define LL_HRTIM_BM_PRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024 */
01300 #define LL_HRTIM_BM_PRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048*/
01301 #define LL_HRTIM_BM_PRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096 */
01302 #define LL_HRTIM_BM_PRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192 */
01303 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384 */
01304 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
01305 /**
01306   * @}
01307   */
01308
01309 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
01310   * @{
01311   * @brief Constants defining the events that can be used to trig the burst mode operation.
01312   */
01313 #define LL_HRTIM_BM_TRIG_NONE               0x00000000U             /*!<  No trigger */
01314 #define LL_HRTIM_BM_TRIG_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master timer reset event is starting the burst mode operation */
01315 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master timer repetition event is starting the burst mode operation */
01316 #define LL_HRTIM_BM_TRIG_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master timer compare 1 event is starting the burst mode operation */
01317 #define LL_HRTIM_BM_TRIG_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master timer compare 2 event is starting the burst mode operation */
01318 #define LL_HRTIM_BM_TRIG_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master timer compare 3 event is starting the burst mode operation */
01319 #define LL_HRTIM_BM_TRIG_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master timer compare 4 event is starting the burst mode operation */
01320 #define LL_HRTIM_BM_TRIG_TIMA_RESET         (HRTIM_BMTRGR_TARST)    /*!< Timer A reset event is starting the burst mode operation */
01321 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION    (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition event is starting the burst mode operation */
01322 #define LL_HRTIM_BM_TRIG_TIMA_CMP1          (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1 event is starting the burst mode operation */
01323 #define LL_HRTIM_BM_TRIG_TIMA_CMP2          (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2 event is starting the burst mode operation */
01324 #define LL_HRTIM_BM_TRIG_TIMB_RESET         (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset event is starting the burst mode operation */
01325 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION    (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition event is starting the burst mode operation */
01326 #define LL_HRTIM_BM_TRIG_TIMB_CMP1          (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1 event is starting the burst mode operation */
01327 #define LL_HRTIM_BM_TRIG_TIMB_CMP2          (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2 event is starting the burst mode operation */
01328 #define LL_HRTIM_BM_TRIG_TIMC_RESET         (HRTIM_BMTRGR_TCRST)    /*!< Timer C resetevent is starting the burst mode operation  */
01329 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION    (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition event is starting the burst mode operation */
01330 #define LL_HRTIM_BM_TRIG_TIMC_CMP1          (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1 event is starting the burst mode operation */
01331 #define LL_HRTIM_BM_TRIG_TIMC_CMP2          (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2 event is starting the burst mode operation */
01332 #define LL_HRTIM_BM_TRIG_TIMD_RESET         (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset event is starting the burst mode operation */
01333 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION    (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition event is starting the burst mode operation */
01334 #define LL_HRTIM_BM_TRIG_TIMD_CMP1          (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1 event is starting the burst mode operation */
01335 #define LL_HRTIM_BM_TRIG_TIMD_CMP2          (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2 event is starting the burst mode operation */
01336 #define LL_HRTIM_BM_TRIG_TIME_RESET         (HRTIM_BMTRGR_TERST)    /*!< Timer E reset event is starting the burst mode operation */
01337 #define LL_HRTIM_BM_TRIG_TIME_REPETITION    (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition event is starting the burst mode operation */
01338 #define LL_HRTIM_BM_TRIG_TIME_CMP1          (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1 event is starting the burst mode operation */
01339 #define LL_HRTIM_BM_TRIG_TIME_CMP2          (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2 event is starting the burst mode operation */
01340 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7        (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation  */
01341 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8        (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation  */
01342 #define LL_HRTIM_BM_TRIG_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
01343 #define LL_HRTIM_BM_TRIG_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
01344 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
01345 /**
01346   * @}
01347   */
01348
01349 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
01350   * @{
01351   * @brief Constants defining the operating state of the burst mode controller.
01352   */
01353 #define LL_HRTIM_BM_STATUS_NORMAL             0x00000000U           /*!< Normal operation */
01354 #define LL_HRTIM_BM_STATUS_BURST_ONGOING      HRTIM_BMCR_BMSTAT     /*!< Burst operation on-going */
01355 /**
01356   * @}
01357   */
01358
01359 /**
01360   * @}
01361   */
01362
01363 /* Exported macro ------------------------------------------------------------*/
01364 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
01365   * @{
01366   */
01367
01368 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
01369   * @{
01370   */
01371
01372 /**
01373   * @brief  Write a value in HRTIM register
01374   * @param  __INSTANCE__ HRTIM Instance
01375   * @param  __REG__ Register to be written
01376   * @param  __VALUE__ Value to be written in the register
01377   * @retval None
01378   */
01379 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01380
01381 /**
01382   * @brief  Read a value in HRTIM register
01383   * @param  __INSTANCE__ HRTIM Instance
01384   * @param  __REG__ Register to be read
01385   * @retval Register value
01386   */
01387 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01388 /**
01389   * @}
01390   */
01391
01392 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
01393   * @{
01394   */
01395 /**
01396   * @brief  HELPER macro returning the output state from output enable/disable status
01397   * @param  __OUTPUT_STATUS_EN__ output enable status
01398   * @param  __OUTPUT_STATUS_DIS__ output Disable status
01399   * @retval Returned value can be one of the following values:
01400   *         @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
01401   *         @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
01402   *         @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
01403   */
01404 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
01405   (((__OUTPUT_STATUS_EN__) == 1) ?  LL_HRTIM_OUTPUTSTATE_RUN :\
01406    ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
01407 /**
01408   * @}
01409   */
01410
01411 /**
01412   * @}
01413   */
01414
01415 /* Exported functions --------------------------------------------------------*/
01416 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
01417   * @{
01418   */
01419 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
01420   * @{
01421   */
01422
01423 /**
01424   * @brief  Select the HRTIM synchronization input source.
01425   * @note This function must not be called when  the concerned timer(s) is (are) enabled .
01426   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
01427   * @param  HRTIMx High Resolution Timer instance
01428   * @param  SyncInSrc This parameter can be one of the following values:
01429   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
01430   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
01431   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
01432   * @retval None
01433   */
01434 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
01435 {
01436   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
01437 }
01438
01439 /**
01440   * @brief  Get actual HRTIM synchronization input source.
01441   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
01442   * @param  HRTIMx High Resolution Timer instance
01443   * @retval SyncInSrc Returned value can be one of the following values:
01444   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
01445   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
01446   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
01447   */
01448 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
01449 {
01450   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
01451 }
01452
01453 /**
01454   * @brief  Configure the HRTIM synchronization output.
01455   * @rmtoll MCR          SYNCSRC      LL_HRTIM_ConfigSyncOut\n
01456   *         MCR          SYNCOUT      LL_HRTIM_ConfigSyncOut
01457   * @param  HRTIMx High Resolution Timer instance
01458   * @param  Config This parameter can be one of the following values:
01459   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01460   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01461   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01462   * @param  Src This parameter can be one of the following values:
01463   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01464   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01465   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01466   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01467   * @retval None
01468   */
01469 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
01470 {
01471   MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
01472 }
01473
01474 /**
01475   * @brief  Set the routing and conditioning of the synchronization output event.
01476   * @rmtoll MCR          SYNCOUT      LL_HRTIM_SetSyncOutConfig
01477   * @note This function can be called only when the master timer is enabled.
01478   * @param  HRTIMx High Resolution Timer instance
01479   * @param  SyncOutConfig This parameter can be one of the following values:
01480   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01481   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01482   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01483   * @retval None
01484   */
01485 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
01486 {
01487   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
01488 }
01489
01490 /**
01491   * @brief  Get actual routing and conditioning of the synchronization output event.
01492   * @rmtoll MCR          SYNCOUT      LL_HRTIM_GetSyncOutConfig
01493   * @param  HRTIMx High Resolution Timer instance
01494   * @retval SyncOutConfig Returned value can be one of the following values:
01495   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
01496   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
01497   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
01498   */
01499 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
01500 {
01501   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
01502 }
01503
01504 /**
01505   * @brief  Set the source and event to be sent on the HRTIM synchronization output.
01506   * @rmtoll MCR          SYNCSRC      LL_HRTIM_SetSyncOutSrc
01507   * @param  HRTIMx High Resolution Timer instance
01508   * @param  SyncOutSrc This parameter can be one of the following values:
01509   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01510   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01511   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01512   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01513   * @retval None
01514   */
01515 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
01516 {
01517   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
01518 }
01519
01520 /**
01521   * @brief  Get actual  source and event sent on the HRTIM synchronization output.
01522   * @rmtoll MCR          SYNCSRC      LL_HRTIM_GetSyncOutSrc
01523   * @param  HRTIMx High Resolution Timer instance
01524   * @retval SyncOutSrc Returned value can be one of the following values:
01525   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
01526   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
01527   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
01528   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
01529   */
01530 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
01531 {
01532   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
01533 }
01534
01535 /**
01536   * @brief  Disable (temporarily) update event generation.
01537   * @rmtoll CR1          MUDIS         LL_HRTIM_SuspendUpdate\n
01538   *         CR1          TAUDIS        LL_HRTIM_SuspendUpdate\n
01539   *         CR1          TBUDIS        LL_HRTIM_SuspendUpdate\n
01540   *         CR1          TCUDIS        LL_HRTIM_SuspendUpdate\n
01541   *         CR1          TDUDIS        LL_HRTIM_SuspendUpdate\n
01542   *         CR1          TEUDIS        LL_HRTIM_SuspendUpdate
01543   * @note Allow to temporarily disable the transfer from preload to active
01544   *      registers, whatever the selected update event. This allows to modify
01545   *      several registers in multiple timers.
01546   * @param  HRTIMx High Resolution Timer instance
01547   * @param  Timers This parameter can be a combination of the following values:
01548   *         @arg @ref LL_HRTIM_TIMER_MASTER
01549   *         @arg @ref LL_HRTIM_TIMER_A
01550   *         @arg @ref LL_HRTIM_TIMER_B
01551   *         @arg @ref LL_HRTIM_TIMER_C
01552   *         @arg @ref LL_HRTIM_TIMER_D
01553   *         @arg @ref LL_HRTIM_TIMER_E
01554   * @retval None
01555   */
01556 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01557 {
01558   SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
01559 }
01560
01561 /**
01562   * @brief  Enable update event generation.
01563   * @rmtoll CR1          MUDIS         LL_HRTIM_ResumeUpdate\n
01564   *         CR1          TAUDIS        LL_HRTIM_ResumeUpdate\n
01565   *         CR1          TBUDIS        LL_HRTIM_ResumeUpdate\n
01566   *         CR1          TCUDIS        LL_HRTIM_ResumeUpdate\n
01567   *         CR1          TDUDIS        LL_HRTIM_ResumeUpdate\n
01568   *         CR1          TEUDIS        LL_HRTIM_ResumeUpdate
01569   * @note The regular update event takes place.
01570   * @param  HRTIMx High Resolution Timer instance
01571   * @param  Timers This parameter can be a combination of the following values:
01572   *         @arg @ref LL_HRTIM_TIMER_MASTER
01573   *         @arg @ref LL_HRTIM_TIMER_A
01574   *         @arg @ref LL_HRTIM_TIMER_B
01575   *         @arg @ref LL_HRTIM_TIMER_C
01576   *         @arg @ref LL_HRTIM_TIMER_D
01577   *         @arg @ref LL_HRTIM_TIMER_E
01578   * @retval None
01579   */
01580 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01581 {
01582   CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
01583 }
01584
01585 /**
01586   * @brief  Force an immediate transfer from the preload to the active register .
01587   * @rmtoll CR2          MSWU          LL_HRTIM_ForceUpdate\n
01588   *         CR2          TASWU         LL_HRTIM_ForceUpdate\n
01589   *         CR2          TBSWU         LL_HRTIM_ForceUpdate\n
01590   *         CR2          TCSWU         LL_HRTIM_ForceUpdate\n
01591   *         CR2          TDSWU         LL_HRTIM_ForceUpdate\n
01592   *         CR2          TESWU         LL_HRTIM_ForceUpdate
01593   * @note Any pending update request is cancelled.
01594   * @param  HRTIMx High Resolution Timer instance
01595   * @param  Timers This parameter can be a combination of the following values:
01596   *         @arg @ref LL_HRTIM_TIMER_MASTER
01597   *         @arg @ref LL_HRTIM_TIMER_A
01598   *         @arg @ref LL_HRTIM_TIMER_B
01599   *         @arg @ref LL_HRTIM_TIMER_C
01600   *         @arg @ref LL_HRTIM_TIMER_D
01601   *         @arg @ref LL_HRTIM_TIMER_E
01602   * @retval None
01603   */
01604 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01605 {
01606   SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
01607 }
01608
01609 /**
01610   * @brief  Reset the HRTIM timer(s) counter.
01611   * @rmtoll CR2          MRST          LL_HRTIM_CounterReset\n
01612   *         CR2          TARST         LL_HRTIM_CounterReset\n
01613   *         CR2          TBRST         LL_HRTIM_CounterReset\n
01614   *         CR2          TCRST         LL_HRTIM_CounterReset\n
01615   *         CR2          TDRST         LL_HRTIM_CounterReset\n
01616   *         CR2          TERST         LL_HRTIM_CounterReset
01617   * @param  HRTIMx High Resolution Timer instance
01618   * @param  Timers This parameter can be a combination of the following values:
01619   *         @arg @ref LL_HRTIM_TIMER_MASTER
01620   *         @arg @ref LL_HRTIM_TIMER_A
01621   *         @arg @ref LL_HRTIM_TIMER_B
01622   *         @arg @ref LL_HRTIM_TIMER_C
01623   *         @arg @ref LL_HRTIM_TIMER_D
01624   *         @arg @ref LL_HRTIM_TIMER_E
01625   * @retval None
01626   */
01627 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
01628 {
01629   SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
01630 }
01631
01632 /**
01633   * @brief  Enable the HRTIM timer(s) output(s) .
01634   * @rmtoll OENR         TA1OEN        LL_HRTIM_EnableOutput\n
01635   *         OENR         TA2OEN        LL_HRTIM_EnableOutput\n
01636   *         OENR         TB1OEN        LL_HRTIM_EnableOutput\n
01637   *         OENR         TB2OEN        LL_HRTIM_EnableOutput\n
01638   *         OENR         TC1OEN        LL_HRTIM_EnableOutput\n
01639   *         OENR         TC2OEN        LL_HRTIM_EnableOutput\n
01640   *         OENR         TD1OEN        LL_HRTIM_EnableOutput\n
01641   *         OENR         TD2OEN        LL_HRTIM_EnableOutput\n
01642   *         OENR         TE1OEN        LL_HRTIM_EnableOutput\n
01643   *         OENR         TE2OEN        LL_HRTIM_EnableOutput
01644   * @param  HRTIMx High Resolution Timer instance
01645   * @param  Outputs This parameter can be a combination of the following values:
01646   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01647   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01648   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01649   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01650   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01651   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01652   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01653   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01654   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01655   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01656   * @retval None
01657   */
01658 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
01659 {
01660   SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
01661 }
01662
01663 /**
01664   * @brief  Disable the HRTIM timer(s) output(s) .
01665   * @rmtoll OENR         TA1OEN        LL_HRTIM_DisableOutput\n
01666   *         OENR         TA2OEN        LL_HRTIM_DisableOutput\n
01667   *         OENR         TB1OEN        LL_HRTIM_DisableOutput\n
01668   *         OENR         TB2OEN        LL_HRTIM_DisableOutput\n
01669   *         OENR         TC1OEN        LL_HRTIM_DisableOutput\n
01670   *         OENR         TC2OEN        LL_HRTIM_DisableOutput\n
01671   *         OENR         TD1OEN        LL_HRTIM_DisableOutput\n
01672   *         OENR         TD2OEN        LL_HRTIM_DisableOutput\n
01673   *         OENR         TE1OEN        LL_HRTIM_DisableOutput\n
01674   *         OENR         TE2OEN        LL_HRTIM_DisableOutput
01675   * @param  HRTIMx High Resolution Timer instance
01676   * @param  Outputs This parameter can be a combination of the following values:
01677   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01678   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01679   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01680   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01681   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01682   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01683   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01684   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01685   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01686   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
01690 {
01691   SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
01692 }
01693
01694 /**
01695   * @brief  Indicates whether the HRTIM timer output is enabled.
01696   * @rmtoll OENR         TA1OEN        LL_HRTIM_IsEnabledOutput\n
01697   *         OENR         TA2OEN        LL_HRTIM_IsEnabledOutput\n
01698   *         OENR         TB1OEN        LL_HRTIM_IsEnabledOutput\n
01699   *         OENR         TB2OEN        LL_HRTIM_IsEnabledOutput\n
01700   *         OENR         TC1OEN        LL_HRTIM_IsEnabledOutput\n
01701   *         OENR         TC2OEN        LL_HRTIM_IsEnabledOutput\n
01702   *         OENR         TD1OEN        LL_HRTIM_IsEnabledOutput\n
01703   *         OENR         TD2OEN        LL_HRTIM_IsEnabledOutput\n
01704   *         OENR         TE1OEN        LL_HRTIM_IsEnabledOutput\n
01705   *         OENR         TE2OEN        LL_HRTIM_IsEnabledOutput
01706   * @param  HRTIMx High Resolution Timer instance
01707   * @param  Output This parameter can be one of the following values:
01708   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01709   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01710   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01711   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01712   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01713   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01714   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01715   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01716   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01717   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01718   * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
01719   */
01720 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
01721 {
01722   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
01723 }
01724
01725 /**
01726   * @brief  Indicates whether the HRTIM timer output is disabled.
01727   * @rmtoll ODISR        TA1ODIS        LL_HRTIM_IsDisabledOutput\n
01728   *         ODISR        TA2ODIS        LL_HRTIM_IsDisabledOutput\n
01729   *         ODISR        TB1ODIS        LL_HRTIM_IsDisabledOutput\n
01730   *         ODISR        TB2ODIS        LL_HRTIM_IsDisabledOutput\n
01731   *         ODISR        TC1ODIS        LL_HRTIM_IsDisabledOutput\n
01732   *         ODISR        TC2ODIS        LL_HRTIM_IsDisabledOutput\n
01733   *         ODISR        TD1ODIS        LL_HRTIM_IsDisabledOutput\n
01734   *         ODISR        TD2ODIS        LL_HRTIM_IsDisabledOutput\n
01735   *         ODISR        TE1ODIS        LL_HRTIM_IsDisabledOutput\n
01736   *         ODISR        TE2ODIS        LL_HRTIM_IsDisabledOutput
01737   * @param  HRTIMx High Resolution Timer instance
01738   * @param  Output This parameter can be one of the following values:
01739   *         @arg @ref LL_HRTIM_OUTPUT_TA1
01740   *         @arg @ref LL_HRTIM_OUTPUT_TA2
01741   *         @arg @ref LL_HRTIM_OUTPUT_TB1
01742   *         @arg @ref LL_HRTIM_OUTPUT_TB2
01743   *         @arg @ref LL_HRTIM_OUTPUT_TC1
01744   *         @arg @ref LL_HRTIM_OUTPUT_TC2
01745   *         @arg @ref LL_HRTIM_OUTPUT_TD1
01746   *         @arg @ref LL_HRTIM_OUTPUT_TD2
01747   *         @arg @ref LL_HRTIM_OUTPUT_TE1
01748   *         @arg @ref LL_HRTIM_OUTPUT_TE2
01749   * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
01750   */
01751 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
01752 {
01753   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
01754 }
01755
01756 /**
01757   * @brief  Configure an ADC trigger.
01758   * @rmtoll CR1          ADC1USRC        LL_HRTIM_ConfigADCTrig\n
01759   *         CR1          ADC2USRC        LL_HRTIM_ConfigADCTrig\n
01760   *         CR1          ADC3USRC        LL_HRTIM_ConfigADCTrig\n
01761   *         CR1          ADC4USRC        LL_HRTIM_ConfigADCTrig\n
01762   *         ADC1R        ADC1MC1         LL_HRTIM_ConfigADCTrig\n
01763   *         ADC1R        ADC1MC2         LL_HRTIM_ConfigADCTrig\n
01764   *         ADC1R        ADC1MC3         LL_HRTIM_ConfigADCTrig\n
01765   *         ADC1R        ADC1MC4         LL_HRTIM_ConfigADCTrig\n
01766   *         ADC1R        ADC1MPER        LL_HRTIM_ConfigADCTrig\n
01767   *         ADC1R        ADC1EEV1        LL_HRTIM_ConfigADCTrig\n
01768   *         ADC1R        ADC1EEV2        LL_HRTIM_ConfigADCTrig\n
01769   *         ADC1R        ADC1EEV3        LL_HRTIM_ConfigADCTrig\n
01770   *         ADC1R        ADC1EEV4        LL_HRTIM_ConfigADCTrig\n
01771   *         ADC1R        ADC1EEV5        LL_HRTIM_ConfigADCTrig\n
01772   *         ADC1R        ADC1TAC2        LL_HRTIM_ConfigADCTrig\n
01773   *         ADC1R        ADC1TAC3        LL_HRTIM_ConfigADCTrig\n
01774   *         ADC1R        ADC1TAC4        LL_HRTIM_ConfigADCTrig\n
01775   *         ADC1R        ADC1TAPER       LL_HRTIM_ConfigADCTrig\n
01776   *         ADC1R        ADC1TARST       LL_HRTIM_ConfigADCTrig\n
01777   *         ADC1R        ADC1TBC2        LL_HRTIM_ConfigADCTrig\n
01778   *         ADC1R        ADC1TBC3        LL_HRTIM_ConfigADCTrig\n
01779   *         ADC1R        ADC1TBC4        LL_HRTIM_ConfigADCTrig\n
01780   *         ADC1R        ADC1TBPER       LL_HRTIM_ConfigADCTrig\n
01781   *         ADC1R        ADC1TBRST       LL_HRTIM_ConfigADCTrig\n
01782   *         ADC1R        ADC1TCC2        LL_HRTIM_ConfigADCTrig\n
01783   *         ADC1R        ADC1TCC3        LL_HRTIM_ConfigADCTrig\n
01784   *         ADC1R        ADC1TCC4        LL_HRTIM_ConfigADCTrig\n
01785   *         ADC1R        ADC1TCPER       LL_HRTIM_ConfigADCTrig\n
01786   *         ADC1R        ADC1TDC2        LL_HRTIM_ConfigADCTrig\n
01787   *         ADC1R        ADC1TDC3        LL_HRTIM_ConfigADCTrig\n
01788   *         ADC1R        ADC1TDC4        LL_HRTIM_ConfigADCTrig\n
01789   *         ADC1R        ADC1TDPER       LL_HRTIM_ConfigADCTrig\n
01790   *         ADC1R        ADC1TEC2        LL_HRTIM_ConfigADCTrig\n
01791   *         ADC1R        ADC1TEC3        LL_HRTIM_ConfigADCTrig\n
01792   *         ADC1R        ADC1TEC4        LL_HRTIM_ConfigADCTrig\n
01793   *         ADC1R        ADC1TEPER       LL_HRTIM_ConfigADCTrig\n
01794   *         ADC2R        ADC2MC1         LL_HRTIM_ConfigADCTrig\n
01795   *         ADC2R        ADC2MC2         LL_HRTIM_ConfigADCTrig\n
01796   *         ADC2R        ADC2MC3         LL_HRTIM_ConfigADCTrig\n
01797   *         ADC2R        ADC2MC4         LL_HRTIM_ConfigADCTrig\n
01798   *         ADC2R        ADC2MPER        LL_HRTIM_ConfigADCTrig\n
01799   *         ADC2R        ADC2EEV6        LL_HRTIM_ConfigADCTrig\n
01800   *         ADC2R        ADC2EEV7        LL_HRTIM_ConfigADCTrig\n
01801   *         ADC2R        ADC2EEV8        LL_HRTIM_ConfigADCTrig\n
01802   *         ADC2R        ADC2EEV9        LL_HRTIM_ConfigADCTrig\n
01803   *         ADC2R        ADC2EEV10       LL_HRTIM_ConfigADCTrig\n
01804   *         ADC2R        ADC2TAC2        LL_HRTIM_ConfigADCTrig\n
01805   *         ADC2R        ADC2TAC3        LL_HRTIM_ConfigADCTrig\n
01806   *         ADC2R        ADC2TAC4        LL_HRTIM_ConfigADCTrig\n
01807   *         ADC2R        ADC2TAPER       LL_HRTIM_ConfigADCTrig\n
01808   *         ADC2R        ADC2TBC2        LL_HRTIM_ConfigADCTrig\n
01809   *         ADC2R        ADC2TBC3        LL_HRTIM_ConfigADCTrig\n
01810   *         ADC2R        ADC2TBC4        LL_HRTIM_ConfigADCTrig\n
01811   *         ADC2R        ADC2TBPER       LL_HRTIM_ConfigADCTrig\n
01812   *         ADC2R        ADC2TCC2        LL_HRTIM_ConfigADCTrig\n
01813   *         ADC2R        ADC2TCC3        LL_HRTIM_ConfigADCTrig\n
01814   *         ADC2R        ADC2TCC4        LL_HRTIM_ConfigADCTrig\n
01815   *         ADC2R        ADC2TCPER       LL_HRTIM_ConfigADCTrig\n
01816   *         ADC2R        ADC2TCRST       LL_HRTIM_ConfigADCTrig\n
01817   *         ADC2R        ADC2TDC2        LL_HRTIM_ConfigADCTrig\n
01818   *         ADC2R        ADC2TDC3        LL_HRTIM_ConfigADCTrig\n
01819   *         ADC2R        ADC2TDC4        LL_HRTIM_ConfigADCTrig\n
01820   *         ADC2R        ADC2TDPER       LL_HRTIM_ConfigADCTrig\n
01821   *         ADC2R        ADC2TDRST       LL_HRTIM_ConfigADCTrig\n
01822   *         ADC2R        ADC2TEC2        LL_HRTIM_ConfigADCTrig\n
01823   *         ADC2R        ADC2TEC3        LL_HRTIM_ConfigADCTrig\n
01824   *         ADC2R        ADC2TEC4        LL_HRTIM_ConfigADCTrig\n
01825   *         ADC2R        ADC2TERST       LL_HRTIM_ConfigADCTrig\n
01826   *         ADC3R        ADC3MC1         LL_HRTIM_ConfigADCTrig\n
01827   *         ADC3R        ADC3MC2         LL_HRTIM_ConfigADCTrig\n
01828   *         ADC3R        ADC3MC3         LL_HRTIM_ConfigADCTrig\n
01829   *         ADC3R        ADC3MC4         LL_HRTIM_ConfigADCTrig\n
01830   *         ADC3R        ADC3MPER        LL_HRTIM_ConfigADCTrig\n
01831   *         ADC3R        ADC3EEV1        LL_HRTIM_ConfigADCTrig\n
01832   *         ADC3R        ADC3EEV2        LL_HRTIM_ConfigADCTrig\n
01833   *         ADC3R        ADC3EEV3        LL_HRTIM_ConfigADCTrig\n
01834   *         ADC3R        ADC3EEV4        LL_HRTIM_ConfigADCTrig\n
01835   *         ADC3R        ADC3EEV5        LL_HRTIM_ConfigADCTrig\n
01836   *         ADC3R        ADC3TAC2        LL_HRTIM_ConfigADCTrig\n
01837   *         ADC3R        ADC3TAC3        LL_HRTIM_ConfigADCTrig\n
01838   *         ADC3R        ADC3TAC4        LL_HRTIM_ConfigADCTrig\n
01839   *         ADC3R        ADC3TAPER       LL_HRTIM_ConfigADCTrig\n
01840   *         ADC3R        ADC3TARST       LL_HRTIM_ConfigADCTrig\n
01841   *         ADC3R        ADC3TBC2        LL_HRTIM_ConfigADCTrig\n
01842   *         ADC3R        ADC3TBC3        LL_HRTIM_ConfigADCTrig\n
01843   *         ADC3R        ADC3TBC4        LL_HRTIM_ConfigADCTrig\n
01844   *         ADC3R        ADC3TBPER       LL_HRTIM_ConfigADCTrig\n
01845   *         ADC3R        ADC3TBRST       LL_HRTIM_ConfigADCTrig\n
01846   *         ADC3R        ADC3TCC2        LL_HRTIM_ConfigADCTrig\n
01847   *         ADC3R        ADC3TCC3        LL_HRTIM_ConfigADCTrig\n
01848   *         ADC3R        ADC3TCC4        LL_HRTIM_ConfigADCTrig\n
01849   *         ADC3R        ADC3TCPER       LL_HRTIM_ConfigADCTrig\n
01850   *         ADC3R        ADC3TDC2        LL_HRTIM_ConfigADCTrig\n
01851   *         ADC3R        ADC3TDC3        LL_HRTIM_ConfigADCTrig\n
01852   *         ADC3R        ADC3TDC4        LL_HRTIM_ConfigADCTrig\n
01853   *         ADC3R        ADC3TDPER       LL_HRTIM_ConfigADCTrig\n
01854   *         ADC3R        ADC3TEC2        LL_HRTIM_ConfigADCTrig\n
01855   *         ADC3R        ADC3TEC3        LL_HRTIM_ConfigADCTrig\n
01856   *         ADC3R        ADC3TEC4        LL_HRTIM_ConfigADCTrig\n
01857   *         ADC3R        ADC3TEPER       LL_HRTIM_ConfigADCTrig\n
01858   *         ADC4R        ADC4MC1         LL_HRTIM_ConfigADCTrig\n
01859   *         ADC4R        ADC4MC2         LL_HRTIM_ConfigADCTrig\n
01860   *         ADC4R        ADC4MC3         LL_HRTIM_ConfigADCTrig\n
01861   *         ADC4R        ADC4MC4         LL_HRTIM_ConfigADCTrig\n
01862   *         ADC4R        ADC4MPER        LL_HRTIM_ConfigADCTrig\n
01863   *         ADC4R        ADC4EEV6        LL_HRTIM_ConfigADCTrig\n
01864   *         ADC4R        ADC4EEV7        LL_HRTIM_ConfigADCTrig\n
01865   *         ADC4R        ADC4EEV8        LL_HRTIM_ConfigADCTrig\n
01866   *         ADC4R        ADC4EEV9        LL_HRTIM_ConfigADCTrig\n
01867   *         ADC4R        ADC4EEV10       LL_HRTIM_ConfigADCTrig\n
01868   *         ADC4R        ADC4TAC2        LL_HRTIM_ConfigADCTrig\n
01869   *         ADC4R        ADC4TAC3        LL_HRTIM_ConfigADCTrig\n
01870   *         ADC4R        ADC4TAC4        LL_HRTIM_ConfigADCTrig\n
01871   *         ADC4R        ADC4TAPER       LL_HRTIM_ConfigADCTrig\n
01872   *         ADC4R        ADC4TBC2        LL_HRTIM_ConfigADCTrig\n
01873   *         ADC4R        ADC4TBC3        LL_HRTIM_ConfigADCTrig\n
01874   *         ADC4R        ADC4TBC4        LL_HRTIM_ConfigADCTrig\n
01875   *         ADC4R        ADC4TBPER       LL_HRTIM_ConfigADCTrig\n
01876   *         ADC4R        ADC4TCC2        LL_HRTIM_ConfigADCTrig\n
01877   *         ADC4R        ADC4TCC3        LL_HRTIM_ConfigADCTrig\n
01878   *         ADC4R        ADC4TCC4        LL_HRTIM_ConfigADCTrig\n
01879   *         ADC4R        ADC4TCPER       LL_HRTIM_ConfigADCTrig\n
01880   *         ADC4R        ADC4TCRST       LL_HRTIM_ConfigADCTrig\n
01881   *         ADC4R        ADC4TDC2        LL_HRTIM_ConfigADCTrig\n
01882   *         ADC4R        ADC4TDC3        LL_HRTIM_ConfigADCTrig\n
01883   *         ADC4R        ADC4TDC4        LL_HRTIM_ConfigADCTrig\n
01884   *         ADC4R        ADC4TDPER       LL_HRTIM_ConfigADCTrig\n
01885   *         ADC4R        ADC4TDRST       LL_HRTIM_ConfigADCTrig\n
01886   *         ADC4R        ADC4TEC2        LL_HRTIM_ConfigADCTrig\n
01887   *         ADC4R        ADC4TEC3        LL_HRTIM_ConfigADCTrig\n
01888   *         ADC4R        ADC4TEC4        LL_HRTIM_ConfigADCTrig\n
01889   *         ADC4R        ADC4TERST       LL_HRTIM_ConfigADCTrig
01890   * @param  HRTIMx High Resolution Timer instance
01891   * @param  ADCTrig This parameter can be one of the following values:
01892   *         @arg @ref LL_HRTIM_ADCTRIG_1
01893   *         @arg @ref LL_HRTIM_ADCTRIG_2
01894   *         @arg @ref LL_HRTIM_ADCTRIG_3
01895   *         @arg @ref LL_HRTIM_ADCTRIG_4
01896   * @param  Update This parameter can be one of the following values:
01897   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
01898   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
01899   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
01900   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
01901   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
01902   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
01903   * @param  Src This parameter can be a combination of the following values:
01904   *
01905   *         For ADC trigger 1 and ADC trigger 3:
01906   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
01907   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
01908   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
01909   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
01910   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
01911   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
01912   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
01913   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
01914   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
01915   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
01916   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
01917   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
01918   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
01919   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
01920   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
01921   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
01922   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
01923   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
01924   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
01925   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
01926   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
01927   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
01928   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
01929   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
01930   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
01931   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
01932   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
01933   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
01934   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
01935   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
01936   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
01937   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
01938   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
01939   *
01940   *         For ADC trigger 2 and ADC trigger 4:
01941   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
01942   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
01943   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
01944   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
01945   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
01946   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
01947   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
01948   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
01949   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
01950   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
01951   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
01952   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
01953   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
01954   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
01955   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
01956   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
01957   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
01958   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
01959   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
01960   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
01961   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
01962   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
01963   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
01964   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
01965   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
01966   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
01967   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
01968   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
01969   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
01970   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
01971   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
01972   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
01973   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
01974   *
01975   * @retval None
01976   */
01977 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
01978 {
01979   register uint32_t shift = ((3U * ADCTrig) & 0x1FU);
01980   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
01981                                                               REG_OFFSET_TAB_ADCxR[ADCTrig]));
01982   MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
01983   WRITE_REG(*pReg, Src);
01984 }
01985
01986 /**
01987   * @brief  Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
01988   * @rmtoll CR1          ADC1USRC         LL_HRTIM_SetADCTrigUpdate\n
01989   *         CR1          ADC2USRC         LL_HRTIM_SetADCTrigUpdate\n
01990   *         CR1          ADC3USRC         LL_HRTIM_SetADCTrigUpdate\n
01991   *         CR1          ADC4USRC         LL_HRTIM_SetADCTrigUpdate\n
01992   * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
01993   *       registers are not preloaded either: a write access will result in an
01994   *       immediate update of the trigger source.
01995   * @param  HRTIMx High Resolution Timer instance
01996   * @param  ADCTrig This parameter can be one of the following values:
01997   *         @arg @ref LL_HRTIM_ADCTRIG_1
01998   *         @arg @ref LL_HRTIM_ADCTRIG_2
01999   *         @arg @ref LL_HRTIM_ADCTRIG_3
02000   *         @arg @ref LL_HRTIM_ADCTRIG_4
02001   * @param  Update This parameter can be one of the following values:
02002   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02003   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02004   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02005   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02006   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02007   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02008   * @retval None
02009   */
02010 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
02011 {
02012   register uint32_t shift = ((3U * ADCTrig) & 0x1FU);
02013   MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
02014 }
02015
02016 /**
02017   * @brief  Get the source timer triggering the update of the HRTIM_ADCxR register.
02018   * @rmtoll CR1          ADC1USRC        LL_HRTIM_GetADCTrigUpdate\n
02019   *         CR1          ADC2USRC        LL_HRTIM_GetADCTrigUpdate\n
02020   *         CR1          ADC3USRC        LL_HRTIM_GetADCTrigUpdate\n
02021   *         CR1          ADC4USRC        LL_HRTIM_GetADCTrigUpdate\n
02022   * @param  HRTIMx High Resolution Timer instance
02023   * @param  ADCTrig This parameter can be one of the following values:
02024   *         @arg @ref LL_HRTIM_ADCTRIG_1
02025   *         @arg @ref LL_HRTIM_ADCTRIG_2
02026   *         @arg @ref LL_HRTIM_ADCTRIG_3
02027   *         @arg @ref LL_HRTIM_ADCTRIG_4
02028   * @retval Update Returned value can be one of the following values:
02029   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02030   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02031   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02032   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02033   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02034   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02035   */
02036 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
02037 {
02038   register const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
02039   return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
02040 }
02041
02042 /**
02043   * @brief  Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
02044   * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_SetADCTrigSrc\n
02045   *         ADC1R        ADC1MC2         LL_HRTIM_SetADCTrigSrc\n
02046   *         ADC1R        ADC1MC3         LL_HRTIM_SetADCTrigSrc\n
02047   *         ADC1R        ADC1MC4         LL_HRTIM_SetADCTrigSrc\n
02048   *         ADC1R        ADC1MPER        LL_HRTIM_SetADCTrigSrc\n
02049   *         ADC1R        ADC1EEV1        LL_HRTIM_SetADCTrigSrc\n
02050   *         ADC1R        ADC1EEV2        LL_HRTIM_SetADCTrigSrc\n
02051   *         ADC1R        ADC1EEV3        LL_HRTIM_SetADCTrigSrc\n
02052   *         ADC1R        ADC1EEV4        LL_HRTIM_SetADCTrigSrc\n
02053   *         ADC1R        ADC1EEV5        LL_HRTIM_SetADCTrigSrc\n
02054   *         ADC1R        ADC1TAC2        LL_HRTIM_SetADCTrigSrc\n
02055   *         ADC1R        ADC1TAC3        LL_HRTIM_SetADCTrigSrc\n
02056   *         ADC1R        ADC1TAC4        LL_HRTIM_SetADCTrigSrc\n
02057   *         ADC1R        ADC1TAPER       LL_HRTIM_SetADCTrigSrc\n
02058   *         ADC1R        ADC1TARST       LL_HRTIM_SetADCTrigSrc\n
02059   *         ADC1R        ADC1TBC2        LL_HRTIM_SetADCTrigSrc\n
02060   *         ADC1R        ADC1TBC3        LL_HRTIM_SetADCTrigSrc\n
02061   *         ADC1R        ADC1TBC4        LL_HRTIM_SetADCTrigSrc\n
02062   *         ADC1R        ADC1TBPER       LL_HRTIM_SetADCTrigSrc\n
02063   *         ADC1R        ADC1TBRST       LL_HRTIM_SetADCTrigSrc\n
02064   *         ADC1R        ADC1TCC2        LL_HRTIM_SetADCTrigSrc\n
02065   *         ADC1R        ADC1TCC3        LL_HRTIM_SetADCTrigSrc\n
02066   *         ADC1R        ADC1TCC4        LL_HRTIM_SetADCTrigSrc\n
02067   *         ADC1R        ADC1TCPER       LL_HRTIM_SetADCTrigSrc\n
02068   *         ADC1R        ADC1TDC2        LL_HRTIM_SetADCTrigSrc\n
02069   *         ADC1R        ADC1TDC3        LL_HRTIM_SetADCTrigSrc\n
02070   *         ADC1R        ADC1TDC4        LL_HRTIM_SetADCTrigSrc\n
02071   *         ADC1R        ADC1TDPER       LL_HRTIM_SetADCTrigSrc\n
02072   *         ADC1R        ADC1TEC2        LL_HRTIM_SetADCTrigSrc\n
02073   *         ADC1R        ADC1TEC3        LL_HRTIM_SetADCTrigSrc\n
02074   *         ADC1R        ADC1TEC4        LL_HRTIM_SetADCTrigSrc\n
02075   *         ADC1R        ADC1TEPER       LL_HRTIM_SetADCTrigSrc\n
02076   *         ADC2R        ADC2MC1         LL_HRTIM_SetADCTrigSrc\n
02077   *         ADC2R        ADC2MC2         LL_HRTIM_SetADCTrigSrc\n
02078   *         ADC2R        ADC2MC3         LL_HRTIM_SetADCTrigSrc\n
02079   *         ADC2R        ADC2MC4         LL_HRTIM_SetADCTrigSrc\n
02080   *         ADC2R        ADC2MPER        LL_HRTIM_SetADCTrigSrc\n
02081   *         ADC2R        ADC2EEV6        LL_HRTIM_SetADCTrigSrc\n
02082   *         ADC2R        ADC2EEV7        LL_HRTIM_SetADCTrigSrc\n
02083   *         ADC2R        ADC2EEV8        LL_HRTIM_SetADCTrigSrc\n
02084   *         ADC2R        ADC2EEV9        LL_HRTIM_SetADCTrigSrc\n
02085   *         ADC2R        ADC2EEV10       LL_HRTIM_SetADCTrigSrc\n
02086   *         ADC2R        ADC2TAC2        LL_HRTIM_SetADCTrigSrc\n
02087   *         ADC2R        ADC2TAC3        LL_HRTIM_SetADCTrigSrc\n
02088   *         ADC2R        ADC2TAC4        LL_HRTIM_SetADCTrigSrc\n
02089   *         ADC2R        ADC2TAPER       LL_HRTIM_SetADCTrigSrc\n
02090   *         ADC2R        ADC2TBC2        LL_HRTIM_SetADCTrigSrc\n
02091   *         ADC2R        ADC2TBC3        LL_HRTIM_SetADCTrigSrc\n
02092   *         ADC2R        ADC2TBC4        LL_HRTIM_SetADCTrigSrc\n
02093   *         ADC2R        ADC2TBPER       LL_HRTIM_SetADCTrigSrc\n
02094   *         ADC2R        ADC2TCC2        LL_HRTIM_SetADCTrigSrc\n
02095   *         ADC2R        ADC2TCC3        LL_HRTIM_SetADCTrigSrc\n
02096   *         ADC2R        ADC2TCC4        LL_HRTIM_SetADCTrigSrc\n
02097   *         ADC2R        ADC2TCPER       LL_HRTIM_SetADCTrigSrc\n
02098   *         ADC2R        ADC2TCRST       LL_HRTIM_SetADCTrigSrc\n
02099   *         ADC2R        ADC2TDC2        LL_HRTIM_SetADCTrigSrc\n
02100   *         ADC2R        ADC2TDC3        LL_HRTIM_SetADCTrigSrc\n
02101   *         ADC2R        ADC2TDC4        LL_HRTIM_SetADCTrigSrc\n
02102   *         ADC2R        ADC2TDPER       LL_HRTIM_SetADCTrigSrc\n
02103   *         ADC2R        ADC2TDRST       LL_HRTIM_SetADCTrigSrc\n
02104   *         ADC2R        ADC2TEC2        LL_HRTIM_SetADCTrigSrc\n
02105   *         ADC2R        ADC2TEC3        LL_HRTIM_SetADCTrigSrc\n
02106   *         ADC2R        ADC2TEC4        LL_HRTIM_SetADCTrigSrc\n
02107   *         ADC2R        ADC2TERST       LL_HRTIM_SetADCTrigSrc\n
02108   *         ADC3R        ADC3MC1         LL_HRTIM_SetADCTrigSrc\n
02109   *         ADC3R        ADC3MC2         LL_HRTIM_SetADCTrigSrc\n
02110   *         ADC3R        ADC3MC3         LL_HRTIM_SetADCTrigSrc\n
02111   *         ADC3R        ADC3MC4         LL_HRTIM_SetADCTrigSrc\n
02112   *         ADC3R        ADC3MPER        LL_HRTIM_SetADCTrigSrc\n
02113   *         ADC3R        ADC3EEV1        LL_HRTIM_SetADCTrigSrc\n
02114   *         ADC3R        ADC3EEV2        LL_HRTIM_SetADCTrigSrc\n
02115   *         ADC3R        ADC3EEV3        LL_HRTIM_SetADCTrigSrc\n
02116   *         ADC3R        ADC3EEV4        LL_HRTIM_SetADCTrigSrc\n
02117   *         ADC3R        ADC3EEV5        LL_HRTIM_SetADCTrigSrc\n
02118   *         ADC3R        ADC3TAC2        LL_HRTIM_SetADCTrigSrc\n
02119   *         ADC3R        ADC3TAC3        LL_HRTIM_SetADCTrigSrc\n
02120   *         ADC3R        ADC3TAC4        LL_HRTIM_SetADCTrigSrc\n
02121   *         ADC3R        ADC3TAPER       LL_HRTIM_SetADCTrigSrc\n
02122   *         ADC3R        ADC3TARST       LL_HRTIM_SetADCTrigSrc\n
02123   *         ADC3R        ADC3TBC2        LL_HRTIM_SetADCTrigSrc\n
02124   *         ADC3R        ADC3TBC3        LL_HRTIM_SetADCTrigSrc\n
02125   *         ADC3R        ADC3TBC4        LL_HRTIM_SetADCTrigSrc\n
02126   *         ADC3R        ADC3TBPER       LL_HRTIM_SetADCTrigSrc\n
02127   *         ADC3R        ADC3TBRST       LL_HRTIM_SetADCTrigSrc\n
02128   *         ADC3R        ADC3TCC2        LL_HRTIM_SetADCTrigSrc\n
02129   *         ADC3R        ADC3TCC3        LL_HRTIM_SetADCTrigSrc\n
02130   *         ADC3R        ADC3TCC4        LL_HRTIM_SetADCTrigSrc\n
02131   *         ADC3R        ADC3TCPER       LL_HRTIM_SetADCTrigSrc\n
02132   *         ADC3R        ADC3TDC2        LL_HRTIM_SetADCTrigSrc\n
02133   *         ADC3R        ADC3TDC3        LL_HRTIM_SetADCTrigSrc\n
02134   *         ADC3R        ADC3TDC4        LL_HRTIM_SetADCTrigSrc\n
02135   *         ADC3R        ADC3TDPER       LL_HRTIM_SetADCTrigSrc\n
02136   *         ADC3R        ADC3TEC2        LL_HRTIM_SetADCTrigSrc\n
02137   *         ADC3R        ADC3TEC3        LL_HRTIM_SetADCTrigSrc\n
02138   *         ADC3R        ADC3TEC4        LL_HRTIM_SetADCTrigSrc\n
02139   *         ADC3R        ADC3TEPER       LL_HRTIM_SetADCTrigSrc\n
02140   *         ADC4R        ADC4MC1         LL_HRTIM_SetADCTrigSrc\n
02141   *         ADC4R        ADC4MC2         LL_HRTIM_SetADCTrigSrc\n
02142   *         ADC4R        ADC4MC3         LL_HRTIM_SetADCTrigSrc\n
02143   *         ADC4R        ADC4MC4         LL_HRTIM_SetADCTrigSrc\n
02144   *         ADC4R        ADC4MPER        LL_HRTIM_SetADCTrigSrc\n
02145   *         ADC4R        ADC4EEV6        LL_HRTIM_SetADCTrigSrc\n
02146   *         ADC4R        ADC4EEV7        LL_HRTIM_SetADCTrigSrc\n
02147   *         ADC4R        ADC4EEV8        LL_HRTIM_SetADCTrigSrc\n
02148   *         ADC4R        ADC4EEV9        LL_HRTIM_SetADCTrigSrc\n
02149   *         ADC4R        ADC4EEV10       LL_HRTIM_SetADCTrigSrc\n
02150   *         ADC4R        ADC4TAC2        LL_HRTIM_SetADCTrigSrc\n
02151   *         ADC4R        ADC4TAC3        LL_HRTIM_SetADCTrigSrc\n
02152   *         ADC4R        ADC4TAC4        LL_HRTIM_SetADCTrigSrc\n
02153   *         ADC4R        ADC4TAPER       LL_HRTIM_SetADCTrigSrc\n
02154   *         ADC4R        ADC4TBC2        LL_HRTIM_SetADCTrigSrc\n
02155   *         ADC4R        ADC4TBC3        LL_HRTIM_SetADCTrigSrc\n
02156   *         ADC4R        ADC4TBC4        LL_HRTIM_SetADCTrigSrc\n
02157   *         ADC4R        ADC4TBPER       LL_HRTIM_SetADCTrigSrc\n
02158   *         ADC4R        ADC4TCC2        LL_HRTIM_SetADCTrigSrc\n
02159   *         ADC4R        ADC4TCC3        LL_HRTIM_SetADCTrigSrc\n
02160   *         ADC4R        ADC4TCC4        LL_HRTIM_SetADCTrigSrc\n
02161   *         ADC4R        ADC4TCPER       LL_HRTIM_SetADCTrigSrc\n
02162   *         ADC4R        ADC4TCRST       LL_HRTIM_SetADCTrigSrc\n
02163   *         ADC4R        ADC4TDC2        LL_HRTIM_SetADCTrigSrc\n
02164   *         ADC4R        ADC4TDC3        LL_HRTIM_SetADCTrigSrc\n
02165   *         ADC4R        ADC4TDC4        LL_HRTIM_SetADCTrigSrc\n
02166   *         ADC4R        ADC4TDPER       LL_HRTIM_SetADCTrigSrc\n
02167   *         ADC4R        ADC4TDRST       LL_HRTIM_SetADCTrigSrc\n
02168   *         ADC4R        ADC4TEC2        LL_HRTIM_SetADCTrigSrc\n
02169   *         ADC4R        ADC4TEC3        LL_HRTIM_SetADCTrigSrc\n
02170   *         ADC4R        ADC4TEC4        LL_HRTIM_SetADCTrigSrc\n
02171   *         ADC4R        ADC4TERST       LL_HRTIM_SetADCTrigSrc\n
02172   * @param  HRTIMx High Resolution Timer instance
02173   * @param  ADCTrig This parameter can be one of the following values:
02174   *         @arg @ref LL_HRTIM_ADCTRIG_1
02175   *         @arg @ref LL_HRTIM_ADCTRIG_2
02176   *         @arg @ref LL_HRTIM_ADCTRIG_3
02177   *         @arg @ref LL_HRTIM_ADCTRIG_4
02178   * @param  Src
02179   *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
02180   *         combination of the following values:
02181   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
02182   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
02183   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
02184   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
02185   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
02186   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
02187   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
02188   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
02189   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
02190   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
02191   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
02192   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
02193   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
02194   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
02195   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
02196   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
02197   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
02198   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
02199   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
02200   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
02201   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
02202   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
02203   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
02204   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
02205   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
02206   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
02207   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
02208   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
02209   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
02210   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
02211   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
02212   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
02213   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
02214   *
02215   *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
02216   *         combination of the following values:
02217   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
02218   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
02219   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
02220   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
02221   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
02222   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
02223   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
02224   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
02225   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
02226   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
02227   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
02228   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
02229   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
02230   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02231   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02232   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02233   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
02234   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02235   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02236   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02237   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
02238   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02239   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02240   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02241   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02242   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
02243   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02244   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02245   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02246   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02247   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02248   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02249   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02250   *
02251   * @retval None
02252   */
02253 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
02254 {
02255   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02256                                                               REG_OFFSET_TAB_ADCxR[ADCTrig]));
02257   WRITE_REG(*pReg, Src);
02258 }
02259
02260 /**
02261   * @brief  Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
02262   * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_GetADCTrigSrc\n
02263   *         ADC1R        ADC1MC2         LL_HRTIM_GetADCTrigSrc\n
02264   *         ADC1R        ADC1MC3         LL_HRTIM_GetADCTrigSrc\n
02265   *         ADC1R        ADC1MC4         LL_HRTIM_GetADCTrigSrc\n
02266   *         ADC1R        ADC1MPER        LL_HRTIM_GetADCTrigSrc\n
02267   *         ADC1R        ADC1EEV1        LL_HRTIM_GetADCTrigSrc\n
02268   *         ADC1R        ADC1EEV2        LL_HRTIM_GetADCTrigSrc\n
02269   *         ADC1R        ADC1EEV3        LL_HRTIM_GetADCTrigSrc\n
02270   *         ADC1R        ADC1EEV4        LL_HRTIM_GetADCTrigSrc\n
02271   *         ADC1R        ADC1EEV5        LL_HRTIM_GetADCTrigSrc\n
02272   *         ADC1R        ADC1TAC2        LL_HRTIM_GetADCTrigSrc\n
02273   *         ADC1R        ADC1TAC3        LL_HRTIM_GetADCTrigSrc\n
02274   *         ADC1R        ADC1TAC4        LL_HRTIM_GetADCTrigSrc\n
02275   *         ADC1R        ADC1TAPER       LL_HRTIM_GetADCTrigSrc\n
02276   *         ADC1R        ADC1TARST       LL_HRTIM_GetADCTrigSrc\n
02277   *         ADC1R        ADC1TBC2        LL_HRTIM_GetADCTrigSrc\n
02278   *         ADC1R        ADC1TBC3        LL_HRTIM_GetADCTrigSrc\n
02279   *         ADC1R        ADC1TBC4        LL_HRTIM_GetADCTrigSrc\n
02280   *         ADC1R        ADC1TBPER       LL_HRTIM_GetADCTrigSrc\n
02281   *         ADC1R        ADC1TBRST       LL_HRTIM_GetADCTrigSrc\n
02282   *         ADC1R        ADC1TCC2        LL_HRTIM_GetADCTrigSrc\n
02283   *         ADC1R        ADC1TCC3        LL_HRTIM_GetADCTrigSrc\n
02284   *         ADC1R        ADC1TCC4        LL_HRTIM_GetADCTrigSrc\n
02285   *         ADC1R        ADC1TCPER       LL_HRTIM_GetADCTrigSrc\n
02286   *         ADC1R        ADC1TDC2        LL_HRTIM_GetADCTrigSrc\n
02287   *         ADC1R        ADC1TDC3        LL_HRTIM_GetADCTrigSrc\n
02288   *         ADC1R        ADC1TDC4        LL_HRTIM_GetADCTrigSrc\n
02289   *         ADC1R        ADC1TDPER       LL_HRTIM_GetADCTrigSrc\n
02290   *         ADC1R        ADC1TEC2        LL_HRTIM_GetADCTrigSrc\n
02291   *         ADC1R        ADC1TEC3        LL_HRTIM_GetADCTrigSrc\n
02292   *         ADC1R        ADC1TEC4        LL_HRTIM_GetADCTrigSrc\n
02293   *         ADC1R        ADC1TEPER       LL_HRTIM_GetADCTrigSrc\n
02294   *         ADC2R        ADC2MC1         LL_HRTIM_GetADCTrigSrc\n
02295   *         ADC2R        ADC2MC2         LL_HRTIM_GetADCTrigSrc\n
02296   *         ADC2R        ADC2MC3         LL_HRTIM_GetADCTrigSrc\n
02297   *         ADC2R        ADC2MC4         LL_HRTIM_GetADCTrigSrc\n
02298   *         ADC2R        ADC2MPER        LL_HRTIM_GetADCTrigSrc\n
02299   *         ADC2R        ADC2EEV6        LL_HRTIM_GetADCTrigSrc\n
02300   *         ADC2R        ADC2EEV7        LL_HRTIM_GetADCTrigSrc\n
02301   *         ADC2R        ADC2EEV8        LL_HRTIM_GetADCTrigSrc\n
02302   *         ADC2R        ADC2EEV9        LL_HRTIM_GetADCTrigSrc\n
02303   *         ADC2R        ADC2EEV10       LL_HRTIM_GetADCTrigSrc\n
02304   *         ADC2R        ADC2TAC2        LL_HRTIM_GetADCTrigSrc\n
02305   *         ADC2R        ADC2TAC3        LL_HRTIM_GetADCTrigSrc\n
02306   *         ADC2R        ADC2TAC4        LL_HRTIM_GetADCTrigSrc\n
02307   *         ADC2R        ADC2TAPER       LL_HRTIM_GetADCTrigSrc\n
02308   *         ADC2R        ADC2TBC2        LL_HRTIM_GetADCTrigSrc\n
02309   *         ADC2R        ADC2TBC3        LL_HRTIM_GetADCTrigSrc\n
02310   *         ADC2R        ADC2TBC4        LL_HRTIM_GetADCTrigSrc\n
02311   *         ADC2R        ADC2TBPER       LL_HRTIM_GetADCTrigSrc\n
02312   *         ADC2R        ADC2TCC2        LL_HRTIM_GetADCTrigSrc\n
02313   *         ADC2R        ADC2TCC3        LL_HRTIM_GetADCTrigSrc\n
02314   *         ADC2R        ADC2TCC4        LL_HRTIM_GetADCTrigSrc\n
02315   *         ADC2R        ADC2TCPER       LL_HRTIM_GetADCTrigSrc\n
02316   *         ADC2R        ADC2TCRST       LL_HRTIM_GetADCTrigSrc\n
02317   *         ADC2R        ADC2TDC2        LL_HRTIM_GetADCTrigSrc\n
02318   *         ADC2R        ADC2TDC3        LL_HRTIM_GetADCTrigSrc\n
02319   *         ADC2R        ADC2TDC4        LL_HRTIM_GetADCTrigSrc\n
02320   *         ADC2R        ADC2TDPER       LL_HRTIM_GetADCTrigSrc\n
02321   *         ADC2R        ADC2TDRST       LL_HRTIM_GetADCTrigSrc\n
02322   *         ADC2R        ADC2TEC2        LL_HRTIM_GetADCTrigSrc\n
02323   *         ADC2R        ADC2TEC3        LL_HRTIM_GetADCTrigSrc\n
02324   *         ADC2R        ADC2TEC4        LL_HRTIM_GetADCTrigSrc\n
02325   *         ADC2R        ADC2TERST       LL_HRTIM_GetADCTrigSrc\n
02326   *         ADC3R        ADC3MC1         LL_HRTIM_GetADCTrigSrc\n
02327   *         ADC3R        ADC3MC2         LL_HRTIM_GetADCTrigSrc\n
02328   *         ADC3R        ADC3MC3         LL_HRTIM_GetADCTrigSrc\n
02329   *         ADC3R        ADC3MC4         LL_HRTIM_GetADCTrigSrc\n
02330   *         ADC3R        ADC3MPER        LL_HRTIM_GetADCTrigSrc\n
02331   *         ADC3R        ADC3EEV1        LL_HRTIM_GetADCTrigSrc\n
02332   *         ADC3R        ADC3EEV2        LL_HRTIM_GetADCTrigSrc\n
02333   *         ADC3R        ADC3EEV3        LL_HRTIM_GetADCTrigSrc\n
02334   *         ADC3R        ADC3EEV4        LL_HRTIM_GetADCTrigSrc\n
02335   *         ADC3R        ADC3EEV5        LL_HRTIM_GetADCTrigSrc\n
02336   *         ADC3R        ADC3TAC2        LL_HRTIM_GetADCTrigSrc\n
02337   *         ADC3R        ADC3TAC3        LL_HRTIM_GetADCTrigSrc\n
02338   *         ADC3R        ADC3TAC4        LL_HRTIM_GetADCTrigSrc\n
02339   *         ADC3R        ADC3TAPER       LL_HRTIM_GetADCTrigSrc\n
02340   *         ADC3R        ADC3TARST       LL_HRTIM_GetADCTrigSrc\n
02341   *         ADC3R        ADC3TBC2        LL_HRTIM_GetADCTrigSrc\n
02342   *         ADC3R        ADC3TBC3        LL_HRTIM_GetADCTrigSrc\n
02343   *         ADC3R        ADC3TBC4        LL_HRTIM_GetADCTrigSrc\n
02344   *         ADC3R        ADC3TBPER       LL_HRTIM_GetADCTrigSrc\n
02345   *         ADC3R        ADC3TBRST       LL_HRTIM_GetADCTrigSrc\n
02346   *         ADC3R        ADC3TCC2        LL_HRTIM_GetADCTrigSrc\n
02347   *         ADC3R        ADC3TCC3        LL_HRTIM_GetADCTrigSrc\n
02348   *         ADC3R        ADC3TCC4        LL_HRTIM_GetADCTrigSrc\n
02349   *         ADC3R        ADC3TCPER       LL_HRTIM_GetADCTrigSrc\n
02350   *         ADC3R        ADC3TDC2        LL_HRTIM_GetADCTrigSrc\n
02351   *         ADC3R        ADC3TDC3        LL_HRTIM_GetADCTrigSrc\n
02352   *         ADC3R        ADC3TDC4        LL_HRTIM_GetADCTrigSrc\n
02353   *         ADC3R        ADC3TDPER       LL_HRTIM_GetADCTrigSrc\n
02354   *         ADC3R        ADC3TEC2        LL_HRTIM_GetADCTrigSrc\n
02355   *         ADC3R        ADC3TEC3        LL_HRTIM_GetADCTrigSrc\n
02356   *         ADC3R        ADC3TEC4        LL_HRTIM_GetADCTrigSrc\n
02357   *         ADC3R        ADC3TEPER       LL_HRTIM_GetADCTrigSrc\n
02358   *         ADC4R        ADC4MC1         LL_HRTIM_GetADCTrigSrc\n
02359   *         ADC4R        ADC4MC2         LL_HRTIM_GetADCTrigSrc\n
02360   *         ADC4R        ADC4MC3         LL_HRTIM_GetADCTrigSrc\n
02361   *         ADC4R        ADC4MC4         LL_HRTIM_GetADCTrigSrc\n
02362   *         ADC4R        ADC4MPER        LL_HRTIM_GetADCTrigSrc\n
02363   *         ADC4R        ADC4EEV6        LL_HRTIM_GetADCTrigSrc\n
02364   *         ADC4R        ADC4EEV7        LL_HRTIM_GetADCTrigSrc\n
02365   *         ADC4R        ADC4EEV8        LL_HRTIM_GetADCTrigSrc\n
02366   *         ADC4R        ADC4EEV9        LL_HRTIM_GetADCTrigSrc\n
02367   *         ADC4R        ADC4EEV10       LL_HRTIM_GetADCTrigSrc\n
02368   *         ADC4R        ADC4TAC2        LL_HRTIM_GetADCTrigSrc\n
02369   *         ADC4R        ADC4TAC3        LL_HRTIM_GetADCTrigSrc\n
02370   *         ADC4R        ADC4TAC4        LL_HRTIM_GetADCTrigSrc\n
02371   *         ADC4R        ADC4TAPER       LL_HRTIM_GetADCTrigSrc\n
02372   *         ADC4R        ADC4TBC2        LL_HRTIM_GetADCTrigSrc\n
02373   *         ADC4R        ADC4TBC3        LL_HRTIM_GetADCTrigSrc\n
02374   *         ADC4R        ADC4TBC4        LL_HRTIM_GetADCTrigSrc\n
02375   *         ADC4R        ADC4TBPER       LL_HRTIM_GetADCTrigSrc\n
02376   *         ADC4R        ADC4TCC2        LL_HRTIM_GetADCTrigSrc\n
02377   *         ADC4R        ADC4TCC3        LL_HRTIM_GetADCTrigSrc\n
02378   *         ADC4R        ADC4TCC4        LL_HRTIM_GetADCTrigSrc\n
02379   *         ADC4R        ADC4TCPER       LL_HRTIM_GetADCTrigSrc\n
02380   *         ADC4R        ADC4TCRST       LL_HRTIM_GetADCTrigSrc\n
02381   *         ADC4R        ADC4TDC2        LL_HRTIM_GetADCTrigSrc\n
02382   *         ADC4R        ADC4TDC3        LL_HRTIM_GetADCTrigSrc\n
02383   *         ADC4R        ADC4TDC4        LL_HRTIM_GetADCTrigSrc\n
02384   *         ADC4R        ADC4TDPER       LL_HRTIM_GetADCTrigSrc\n
02385   *         ADC4R        ADC4TDRST       LL_HRTIM_GetADCTrigSrc\n
02386   *         ADC4R        ADC4TEC2        LL_HRTIM_GetADCTrigSrc\n
02387   *         ADC4R        ADC4TEC3        LL_HRTIM_GetADCTrigSrc\n
02388   *         ADC4R        ADC4TEC4        LL_HRTIM_GetADCTrigSrc\n
02389   *         ADC4R        ADC4TERST       LL_HRTIM_GetADCTrigSrc
02390   * @param  HRTIMx High Resolution Timer instance
02391   * @param  ADCTrig This parameter can be one of the following values:
02392   *         @arg @ref LL_HRTIM_ADCTRIG_1
02393   *         @arg @ref LL_HRTIM_ADCTRIG_2
02394   *         @arg @ref LL_HRTIM_ADCTRIG_3
02395   *         @arg @ref LL_HRTIM_ADCTRIG_4
02396   * @retval Src This parameter can be a combination of the following values:
02397   *
02398   *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
02399   *         combination of the following values:
02400   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
02401   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
02402   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
02403   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
02404   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
02405   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
02406   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
02407   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
02408   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
02409   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
02410   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
02411   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
02412   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
02413   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
02414   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
02415   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
02416   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
02417   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
02418   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
02419   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
02420   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
02421   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
02422   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
02423   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
02424   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
02425   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
02426   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
02427   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
02428   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
02429   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
02430   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
02431   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
02432   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
02433   *
02434   *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
02435   *         combination of the following values:
02436   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
02437   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
02438   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
02439   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
02440   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
02441   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
02442   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
02443   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
02444   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
02445   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
02446   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
02447   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
02448   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
02449   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02450   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02451   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02452   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
02453   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02454   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02455   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02456   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
02457   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02458   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02459   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02460   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02461   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
02462   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02463   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02464   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02465   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02466   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02467   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02468   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02469   */
02470 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
02471 {
02472   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02473                                                                     REG_OFFSET_TAB_ADCxR[ADCTrig]));
02474   return (*pReg);
02475
02476 }
02477
02478
02479 /**
02480   * @}
02481   */
02482
02483 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
02484   * @{
02485   */
02486
02487 /**
02488   * @brief  Enable timer(s) counter.
02489   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterEnable\n
02490   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterEnable\n
02491   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterEnable\n
02492   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterEnable\n
02493   *         MDIER        TACEN         LL_HRTIM_TIM_CounterEnable\n
02494   *         MDIER        MCEN          LL_HRTIM_TIM_CounterEnable
02495   * @param  HRTIMx High Resolution Timer instance
02496   * @param  Timers This parameter can be a combination of the following values:
02497   *         @arg @ref LL_HRTIM_TIMER_MASTER
02498   *         @arg @ref LL_HRTIM_TIMER_A
02499   *         @arg @ref LL_HRTIM_TIMER_B
02500   *         @arg @ref LL_HRTIM_TIMER_C
02501   *         @arg @ref LL_HRTIM_TIMER_D
02502   *         @arg @ref LL_HRTIM_TIMER_E
02503   * @retval None
02504   */
02505 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02506 {
02507   SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
02508 }
02509
02510 /**
02511   * @brief  Disable timer(s) counter.
02512   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterDisable\n
02513   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterDisable\n
02514   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterDisable\n
02515   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterDisable\n
02516   *         MDIER        TACEN         LL_HRTIM_TIM_CounterDisable\n
02517   *         MDIER        MCEN          LL_HRTIM_TIM_CounterDisable
02518   * @param  HRTIMx High Resolution Timer instance
02519   * @param  Timers This parameter can be a combination of the following values:
02520   *         @arg @ref LL_HRTIM_TIMER_MASTER
02521   *         @arg @ref LL_HRTIM_TIMER_A
02522   *         @arg @ref LL_HRTIM_TIMER_B
02523   *         @arg @ref LL_HRTIM_TIMER_C
02524   *         @arg @ref LL_HRTIM_TIMER_D
02525   *         @arg @ref LL_HRTIM_TIMER_E
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02529 {
02530   CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
02531 }
02532
02533 /**
02534   * @brief  Indicate whether the timer counter is enabled.
02535   * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_IsCounterEnabled\n
02536   *         MDIER        TDCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02537   *         MDIER        TCCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02538   *         MDIER        TBCEN         LL_HRTIM_TIM_IsCounterEnabled\n
02539   *         MDIER        TACEN         LL_HRTIM_TIM_IsCounterEnabled\n
02540   *         MDIER        MCEN          LL_HRTIM_TIM_IsCounterEnabled
02541   * @param  HRTIMx High Resolution Timer instance
02542   * @param  Timer This parameter can be one of the following values:
02543   *         @arg @ref LL_HRTIM_TIMER_MASTER
02544   *         @arg @ref LL_HRTIM_TIMER_A
02545   *         @arg @ref LL_HRTIM_TIMER_B
02546   *         @arg @ref LL_HRTIM_TIMER_C
02547   *         @arg @ref LL_HRTIM_TIMER_D
02548   *         @arg @ref LL_HRTIM_TIMER_E
02549   * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
02550   */
02551 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02552 {
02553   return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
02554 }
02555
02556 /**
02557   * @brief  Set the timer clock prescaler ratio.
02558   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_SetPrescaler\n
02559   *         TIMxCR     CKPSC         LL_HRTIM_TIM_SetPrescaler
02560   * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
02561   * @note The prescaling ratio cannot be modified once the timer counter is enabled.
02562   * @param  HRTIMx High Resolution Timer instance
02563   * @param  Timer This parameter can be one of the following values:
02564   *         @arg @ref LL_HRTIM_TIMER_MASTER
02565   *         @arg @ref LL_HRTIM_TIMER_A
02566   *         @arg @ref LL_HRTIM_TIMER_B
02567   *         @arg @ref LL_HRTIM_TIMER_C
02568   *         @arg @ref LL_HRTIM_TIMER_D
02569   *         @arg @ref LL_HRTIM_TIMER_E
02570   * @param  Prescaler This parameter can be one of the following values:
02571   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
02572   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
02573   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
02574   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
02575   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
02576   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
02577   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
02578   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
02579   * @retval None
02580   */
02581 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
02582 {
02583   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02584   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02585   MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
02586 }
02587
02588 /**
02589   * @brief  Get the timer clock prescaler ratio
02590   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_GetPrescaler\n
02591   *         TIMxCR     CKPSC         LL_HRTIM_TIM_GetPrescaler
02592   * @param  HRTIMx High Resolution Timer instance
02593   * @param  Timer This parameter can be one of the following values:
02594   *         @arg @ref LL_HRTIM_TIMER_MASTER
02595   *         @arg @ref LL_HRTIM_TIMER_A
02596   *         @arg @ref LL_HRTIM_TIMER_B
02597   *         @arg @ref LL_HRTIM_TIMER_C
02598   *         @arg @ref LL_HRTIM_TIMER_D
02599   *         @arg @ref LL_HRTIM_TIMER_E
02600   * @retval Prescaler Returned value can be one of the following values:
02601   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
02602   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
02603   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
02604   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
02605   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
02606   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
02607   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
02608   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
02609   */
02610 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02611 {
02612   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02613   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02614   return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
02615 }
02616
02617 /**
02618   * @brief  Set the counter operating mode mode (single-shot, continuous or re-triggerable).
02619   * @rmtoll MCR        CONT         LL_HRTIM_TIM_SetCounterMode\n
02620   *         MCR        RETRIG       LL_HRTIM_TIM_SetCounterMode\n
02621   *         TIMxCR     CONT         LL_HRTIM_TIM_SetCounterMode\n
02622   *         TIMxCR     RETRIG       LL_HRTIM_TIM_SetCounterMode
02623   * @param  HRTIMx High Resolution Timer instance
02624   * @param  Timer This parameter can be one of the following values:
02625   *         @arg @ref LL_HRTIM_TIMER_MASTER
02626   *         @arg @ref LL_HRTIM_TIMER_A
02627   *         @arg @ref LL_HRTIM_TIMER_B
02628   *         @arg @ref LL_HRTIM_TIMER_C
02629   *         @arg @ref LL_HRTIM_TIMER_D
02630   *         @arg @ref LL_HRTIM_TIMER_E
02631   * @param  Mode This parameter can be one of the following values:
02632   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
02633   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
02634   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
02635   * @retval None
02636   */
02637 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
02638 {
02639   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02640   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02641   MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
02642 }
02643
02644 /**
02645   * @brief  Get the counter operating mode mode
02646   * @rmtoll MCR        CONT         LL_HRTIM_TIM_GetCounterMode\n
02647   *         MCR        RETRIG       LL_HRTIM_TIM_GetCounterMode\n
02648   *         TIMxCR     CONT         LL_HRTIM_TIM_GetCounterMode\n
02649   *         TIMxCR     RETRIG       LL_HRTIM_TIM_GetCounterMode
02650   * @param  HRTIMx High Resolution Timer instance
02651   * @param  Timer This parameter can be one of the following values:
02652   *         @arg @ref LL_HRTIM_TIMER_MASTER
02653   *         @arg @ref LL_HRTIM_TIMER_A
02654   *         @arg @ref LL_HRTIM_TIMER_B
02655   *         @arg @ref LL_HRTIM_TIMER_C
02656   *         @arg @ref LL_HRTIM_TIMER_D
02657   *         @arg @ref LL_HRTIM_TIMER_E
02658   * @retval Mode Returned value can be one of the following values:
02659   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
02660   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
02661   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
02662   */
02663 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02664 {
02665   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02666   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02667   return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
02668 }
02669
02670 /**
02671   * @brief  Enable the half duty-cycle mode.
02672   * @rmtoll MCR        HALF         LL_HRTIM_TIM_EnableHalfMode\n
02673   *         TIMxCR     HALF         LL_HRTIM_TIM_EnableHalfMode
02674   * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
02675   *       active register is automatically updated with HRTIM_MPER/2
02676   *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
02677   * @param  HRTIMx High Resolution Timer instance
02678   * @param  Timer This parameter can be one of the following values:
02679   *         @arg @ref LL_HRTIM_TIMER_MASTER
02680   *         @arg @ref LL_HRTIM_TIMER_A
02681   *         @arg @ref LL_HRTIM_TIMER_B
02682   *         @arg @ref LL_HRTIM_TIMER_C
02683   *         @arg @ref LL_HRTIM_TIMER_D
02684   *         @arg @ref LL_HRTIM_TIMER_E
02685   * @retval None
02686   */
02687 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02688 {
02689   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02690   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02691   SET_BIT(*pReg, HRTIM_MCR_HALF);
02692 }
02693
02694 /**
02695   * @brief  Disable the half duty-cycle mode.
02696   * @rmtoll MCR        HALF         LL_HRTIM_TIM_DisableHalfMode\n
02697   *         TIMxCR     HALF         LL_HRTIM_TIM_DisableHalfMode
02698   * @param  HRTIMx High Resolution Timer instance
02699   * @param  Timer This parameter can be one of the following values:
02700   *         @arg @ref LL_HRTIM_TIMER_MASTER
02701   *         @arg @ref LL_HRTIM_TIMER_A
02702   *         @arg @ref LL_HRTIM_TIMER_B
02703   *         @arg @ref LL_HRTIM_TIMER_C
02704   *         @arg @ref LL_HRTIM_TIMER_D
02705   *         @arg @ref LL_HRTIM_TIMER_E
02706   * @retval None
02707   */
02708 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02709 {
02710   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02711   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02712   CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
02713 }
02714
02715 /**
02716   * @brief  Indicate whether half duty-cycle mode is enabled for a given timer.
02717   * @rmtoll MCR        HALF         LL_HRTIM_TIM_IsEnabledHalfMode\n
02718   *         TIMxCR     HALF         LL_HRTIM_TIM_IsEnabledHalfMode
02719   * @param  HRTIMx High Resolution Timer instance
02720   * @param  Timer This parameter can be one of the following values:
02721   *         @arg @ref LL_HRTIM_TIMER_MASTER
02722   *         @arg @ref LL_HRTIM_TIMER_A
02723   *         @arg @ref LL_HRTIM_TIMER_B
02724   *         @arg @ref LL_HRTIM_TIMER_C
02725   *         @arg @ref LL_HRTIM_TIMER_D
02726   *         @arg @ref LL_HRTIM_TIMER_E
02727   * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
02728   */
02729 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02730 {
02731   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02732   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02733
02734   return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
02735 }
02736 /**
02737   * @brief  Enable the timer start when receiving a synchronization input event.
02738   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_EnableStartOnSync\n
02739   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_EnableStartOnSync
02740   * @param  HRTIMx High Resolution Timer instance
02741   * @param  Timer This parameter can be one of the following values:
02742   *         @arg @ref LL_HRTIM_TIMER_MASTER
02743   *         @arg @ref LL_HRTIM_TIMER_A
02744   *         @arg @ref LL_HRTIM_TIMER_B
02745   *         @arg @ref LL_HRTIM_TIMER_C
02746   *         @arg @ref LL_HRTIM_TIMER_D
02747   *         @arg @ref LL_HRTIM_TIMER_E
02748   * @retval None
02749   */
02750 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02751 {
02752   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02753   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02754   SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
02755 }
02756
02757 /**
02758   * @brief  Disable the timer start when receiving a synchronization input event.
02759   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_DisableStartOnSync\n
02760   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_DisableStartOnSync
02761   * @param  HRTIMx High Resolution Timer instance
02762   * @param  Timer This parameter can be one of the following values:
02763   *         @arg @ref LL_HRTIM_TIMER_MASTER
02764   *         @arg @ref LL_HRTIM_TIMER_A
02765   *         @arg @ref LL_HRTIM_TIMER_B
02766   *         @arg @ref LL_HRTIM_TIMER_C
02767   *         @arg @ref LL_HRTIM_TIMER_D
02768   *         @arg @ref LL_HRTIM_TIMER_E
02769   * @retval None
02770   */
02771 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02772 {
02773   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02774   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02775   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
02776 }
02777
02778 /**
02779   * @brief  Indicate whether the timer start when receiving a synchronization input event.
02780   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_IsEnabledStartOnSync\n
02781   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_IsEnabledStartOnSync
02782   * @param  HRTIMx High Resolution Timer instance
02783   * @param  Timer This parameter can be one of the following values:
02784   *         @arg @ref LL_HRTIM_TIMER_MASTER
02785   *         @arg @ref LL_HRTIM_TIMER_A
02786   *         @arg @ref LL_HRTIM_TIMER_B
02787   *         @arg @ref LL_HRTIM_TIMER_C
02788   *         @arg @ref LL_HRTIM_TIMER_D
02789   *         @arg @ref LL_HRTIM_TIMER_E
02790   * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
02791   */
02792 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02793 {
02794   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02795   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02796
02797   return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
02798 }
02799
02800 /**
02801   * @brief  Enable the timer reset when receiving a synchronization input event.
02802   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_EnableResetOnSync\n
02803   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_EnableResetOnSync
02804   * @param  HRTIMx High Resolution Timer instance
02805   * @param  Timer This parameter can be one of the following values:
02806   *         @arg @ref LL_HRTIM_TIMER_MASTER
02807   *         @arg @ref LL_HRTIM_TIMER_A
02808   *         @arg @ref LL_HRTIM_TIMER_B
02809   *         @arg @ref LL_HRTIM_TIMER_C
02810   *         @arg @ref LL_HRTIM_TIMER_D
02811   *         @arg @ref LL_HRTIM_TIMER_E
02812   * @retval None
02813   */
02814 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02815 {
02816   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02817   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02818   SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
02819 }
02820
02821 /**
02822   * @brief  Disable the timer reset when receiving a synchronization input event.
02823   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_DisableResetOnSync\n
02824   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_DisableResetOnSync
02825   * @param  HRTIMx High Resolution Timer instance
02826   * @param  Timer This parameter can be one of the following values:
02827   *         @arg @ref LL_HRTIM_TIMER_MASTER
02828   *         @arg @ref LL_HRTIM_TIMER_A
02829   *         @arg @ref LL_HRTIM_TIMER_B
02830   *         @arg @ref LL_HRTIM_TIMER_C
02831   *         @arg @ref LL_HRTIM_TIMER_D
02832   *         @arg @ref LL_HRTIM_TIMER_E
02833   * @retval None
02834   */
02835 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02836 {
02837   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02838   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02839   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
02840 }
02841
02842 /**
02843   * @brief  Indicate whether the timer reset when receiving a synchronization input event.
02844   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_IsEnabledResetOnSync\n
02845   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_IsEnabledResetOnSync
02846   * @param  HRTIMx High Resolution Timer instance
02847   * @param  Timer This parameter can be one of the following values:
02848   *         @arg @ref LL_HRTIM_TIMER_MASTER
02849   *         @arg @ref LL_HRTIM_TIMER_A
02850   *         @arg @ref LL_HRTIM_TIMER_B
02851   *         @arg @ref LL_HRTIM_TIMER_C
02852   *         @arg @ref LL_HRTIM_TIMER_D
02853   *         @arg @ref LL_HRTIM_TIMER_E
02854   * @retval None
02855   */
02856 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02857 {
02858   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02859   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02860
02861   return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
02862 }
02863
02864 /**
02865   * @brief  Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
02866   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_SetDACTrig\n
02867   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_SetDACTrig
02868   * @param  HRTIMx High Resolution Timer instance
02869   * @param  Timer This parameter can be one of the following values:
02870   *         @arg @ref LL_HRTIM_TIMER_MASTER
02871   *         @arg @ref LL_HRTIM_TIMER_A
02872   *         @arg @ref LL_HRTIM_TIMER_B
02873   *         @arg @ref LL_HRTIM_TIMER_C
02874   *         @arg @ref LL_HRTIM_TIMER_D
02875   *         @arg @ref LL_HRTIM_TIMER_E
02876   * @param  DACTrig This parameter can be one of the following values:
02877   *         @arg @ref LL_HRTIM_DACTRIG_NONE
02878   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
02879   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
02880   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
02881   * @retval None
02882   */
02883 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
02884 {
02885   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02886   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02887   MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
02888 }
02889
02890 /**
02891   * @brief  Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
02892   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_GetDACTrig\n
02893   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_GetDACTrig
02894   * @param  HRTIMx High Resolution Timer instance
02895   * @param  Timer This parameter can be one of the following values:
02896   *         @arg @ref LL_HRTIM_TIMER_MASTER
02897   *         @arg @ref LL_HRTIM_TIMER_A
02898   *         @arg @ref LL_HRTIM_TIMER_B
02899   *         @arg @ref LL_HRTIM_TIMER_C
02900   *         @arg @ref LL_HRTIM_TIMER_D
02901   *         @arg @ref LL_HRTIM_TIMER_E
02902   * @retval DACTrig Returned value can be one of the following values:
02903   *         @arg @ref LL_HRTIM_DACTRIG_NONE
02904   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
02905   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
02906   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
02907   */
02908 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02909 {
02910   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02911   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02912   return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
02913 }
02914
02915 /**
02916   * @brief  Enable the timer registers preload mechanism.
02917   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_EnablePreload\n
02918   *         TIMxCR     PREEN        LL_HRTIM_TIM_EnablePreload
02919   * @note When the preload mode is enabled, accessed registers are shadow registers.
02920   *       Their content is transferred into the active register after an update request,
02921   *       either software or synchronized with an event.
02922   * @param  HRTIMx High Resolution Timer instance
02923   * @param  Timer This parameter can be one of the following values:
02924   *         @arg @ref LL_HRTIM_TIMER_MASTER
02925   *         @arg @ref LL_HRTIM_TIMER_A
02926   *         @arg @ref LL_HRTIM_TIMER_B
02927   *         @arg @ref LL_HRTIM_TIMER_C
02928   *         @arg @ref LL_HRTIM_TIMER_D
02929   *         @arg @ref LL_HRTIM_TIMER_E
02930   * @retval None
02931   */
02932 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02933 {
02934   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02935   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02936   SET_BIT(*pReg, HRTIM_MCR_PREEN);
02937 }
02938
02939 /**
02940   * @brief  Disable the timer registers preload mechanism.
02941   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_DisablePreload\n
02942   *         TIMxCR     PREEN        LL_HRTIM_TIM_DisablePreload
02943   * @param  HRTIMx High Resolution Timer instance
02944   * @param  Timer This parameter can be one of the following values:
02945   *         @arg @ref LL_HRTIM_TIMER_MASTER
02946   *         @arg @ref LL_HRTIM_TIMER_A
02947   *         @arg @ref LL_HRTIM_TIMER_B
02948   *         @arg @ref LL_HRTIM_TIMER_C
02949   *         @arg @ref LL_HRTIM_TIMER_D
02950   *         @arg @ref LL_HRTIM_TIMER_E
02951   * @retval None
02952   */
02953 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02954 {
02955   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02956   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02957   CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
02958 }
02959
02960 /**
02961   * @brief  Indicate whether the timer registers preload mechanism is enabled.
02962   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_IsEnabledPreload\n
02963   *         TIMxCR     PREEN        LL_HRTIM_TIM_IsEnabledPreload
02964   * @param  HRTIMx High Resolution Timer instance
02965   * @param  Timer This parameter can be one of the following values:
02966   *         @arg @ref LL_HRTIM_TIMER_MASTER
02967   *         @arg @ref LL_HRTIM_TIMER_A
02968   *         @arg @ref LL_HRTIM_TIMER_B
02969   *         @arg @ref LL_HRTIM_TIMER_C
02970   *         @arg @ref LL_HRTIM_TIMER_D
02971   *         @arg @ref LL_HRTIM_TIMER_E
02972   * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
02973   */
02974 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02975 {
02976   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
02977   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
02978
02979   return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
02980 }
02981
02982 /**
02983   * @brief  Set the timer register update trigger.
02984   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_SetUpdateTrig\n
02985   *         TIMxCR        TAU        LL_HRTIM_TIM_SetUpdateTrig\n
02986   *         TIMxCR        TBU        LL_HRTIM_TIM_SetUpdateTrig\n
02987   *         TIMxCR        TCU        LL_HRTIM_TIM_SetUpdateTrig\n
02988   *         TIMxCR        TDU        LL_HRTIM_TIM_SetUpdateTrig\n
02989   *         TIMxCR        TEU        LL_HRTIM_TIM_SetUpdateTrig\n
02990   *         TIMxCR        MSTU       LL_HRTIM_TIM_SetUpdateTrig
02991   * @param  HRTIMx High Resolution Timer instance
02992   * @param  Timer This parameter can be one of the following values:
02993   *         @arg @ref LL_HRTIM_TIMER_MASTER
02994   *         @arg @ref LL_HRTIM_TIMER_A
02995   *         @arg @ref LL_HRTIM_TIMER_B
02996   *         @arg @ref LL_HRTIM_TIMER_C
02997   *         @arg @ref LL_HRTIM_TIMER_D
02998   *         @arg @ref LL_HRTIM_TIMER_E
02999   * @param  UpdateTrig This parameter can be one of the following values:
03000   *
03001   *         For the master timer this parameter can be one of the following values:
03002   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03003   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03004   *
03005   *         For timer A..E this parameter can be:
03006   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03007   *         or a combination of the following values:
03008   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
03009   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
03010   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
03011   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
03012   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
03013   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
03014   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03015   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
03016   * @retval None
03017   */
03018 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
03019 {
03020   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03021   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03022   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
03023 }
03024
03025 /**
03026   * @brief  Get the timer register update trigger.
03027   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_GetUpdateTrig\n
03028   *         TIMxCR        TBU        LL_HRTIM_TIM_GetUpdateTrig\n
03029   *         TIMxCR        TCU        LL_HRTIM_TIM_GetUpdateTrig\n
03030   *         TIMxCR        TDU        LL_HRTIM_TIM_GetUpdateTrig\n
03031   *         TIMxCR        TEU        LL_HRTIM_TIM_GetUpdateTrig\n
03032   *         TIMxCR        MSTU       LL_HRTIM_TIM_GetUpdateTrig
03033   * @param  HRTIMx High Resolution Timer instance
03034   * @param  Timer This parameter can be one of the following values:
03035   *         @arg @ref LL_HRTIM_TIMER_MASTER
03036   *         @arg @ref LL_HRTIM_TIMER_A
03037   *         @arg @ref LL_HRTIM_TIMER_B
03038   *         @arg @ref LL_HRTIM_TIMER_C
03039   *         @arg @ref LL_HRTIM_TIMER_D
03040   *         @arg @ref LL_HRTIM_TIMER_E
03041   * @retval UpdateTrig Returned value can be one of the following values:
03042   *
03043   *         For the master timer this parameter can be one of the following values:
03044   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03045   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03046   *
03047   *         For timer A..E this parameter can be:
03048   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
03049   *         or a combination of the following values:
03050   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
03051   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
03052   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
03053   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
03054   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
03055   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
03056   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
03057   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
03058   */
03059 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03060 {
03061   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03062   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03063   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >>  REG_SHIFT_TAB_UPDATETRIG[iTimer]);
03064 }
03065
03066 /**
03067   * @brief  Set  the timer registers update condition (how the registers update occurs relatively to the burst DMA  transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
03068   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_SetUpdateGating\n
03069   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_SetUpdateGating
03070   * @param  HRTIMx High Resolution Timer instance
03071   * @param  Timer This parameter can be one of the following values:
03072   *         @arg @ref LL_HRTIM_TIMER_MASTER
03073   *         @arg @ref LL_HRTIM_TIMER_A
03074   *         @arg @ref LL_HRTIM_TIMER_B
03075   *         @arg @ref LL_HRTIM_TIMER_C
03076   *         @arg @ref LL_HRTIM_TIMER_D
03077   *         @arg @ref LL_HRTIM_TIMER_E
03078   * @param  UpdateGating This parameter can be one of the following values:
03079   *
03080   *         For the master timer this parameter can be one of the following values:
03081   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03082   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03083   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03084   *
03085   *         For the timer A..E this parameter can be one of the following values:
03086   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03087   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03088   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03089   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
03090   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
03091   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
03092   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
03093   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
03094   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
03095   * @retval None
03096   */
03097 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
03098 {
03099   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03100   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03101   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
03102 }
03103
03104 /**
03105   * @brief  Get  the timer registers update condition.
03106   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_GetUpdateGating\n
03107   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_GetUpdateGating
03108   * @param  HRTIMx High Resolution Timer instance
03109   * @param  Timer This parameter can be one of the following values:
03110   *         @arg @ref LL_HRTIM_TIMER_MASTER
03111   *         @arg @ref LL_HRTIM_TIMER_A
03112   *         @arg @ref LL_HRTIM_TIMER_B
03113   *         @arg @ref LL_HRTIM_TIMER_C
03114   *         @arg @ref LL_HRTIM_TIMER_D
03115   *         @arg @ref LL_HRTIM_TIMER_E
03116   * @retval UpdateGating Returned value can be one of the following values:
03117   *
03118   *         For the master timer this parameter can be one of the following values:
03119   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03120   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03121   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03122   *
03123   *         For the timer A..E this parameter can be one of the following values:
03124   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
03125   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
03126   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
03127   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
03128   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
03129   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
03130   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
03131   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
03132   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
03133   */
03134 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03135 {
03136   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03137   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03138   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >>  REG_SHIFT_TAB_UPDATEGATING[iTimer]);
03139 }
03140
03141 /**
03142   * @brief  Enable the push-pull mode.
03143   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_EnablePushPullMode
03144   * @param  HRTIMx High Resolution Timer instance
03145   * @param  Timer This parameter can be one of the following values:
03146   *         @arg @ref LL_HRTIM_TIMER_A
03147   *         @arg @ref LL_HRTIM_TIMER_B
03148   *         @arg @ref LL_HRTIM_TIMER_C
03149   *         @arg @ref LL_HRTIM_TIMER_D
03150   *         @arg @ref LL_HRTIM_TIMER_E
03151   * @retval None
03152   */
03153 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03154 {
03155   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03156   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03157                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03158   SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
03159 }
03160
03161 /**
03162   * @brief  Disable the push-pull mode.
03163   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_DisablePushPullMode
03164   * @param  HRTIMx High Resolution Timer instance
03165   * @param  Timer This parameter can be one of the following values:
03166   *         @arg @ref LL_HRTIM_TIMER_A
03167   *         @arg @ref LL_HRTIM_TIMER_B
03168   *         @arg @ref LL_HRTIM_TIMER_C
03169   *         @arg @ref LL_HRTIM_TIMER_D
03170   *         @arg @ref LL_HRTIM_TIMER_E
03171   * @retval None
03172   */
03173 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03174 {
03175   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03176   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03177                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03178   CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
03179 }
03180
03181 /**
03182   * @brief  Indicate whether the push-pull mode is enabled.
03183   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_IsEnabledPushPullMode\n
03184   * @param  HRTIMx High Resolution Timer instance
03185   * @param  Timer This parameter can be one of the following values:
03186   *         @arg @ref LL_HRTIM_TIMER_A
03187   *         @arg @ref LL_HRTIM_TIMER_B
03188   *         @arg @ref LL_HRTIM_TIMER_C
03189   *         @arg @ref LL_HRTIM_TIMER_D
03190   *         @arg @ref LL_HRTIM_TIMER_E
03191   * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
03192   */
03193 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03194 {
03195   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03196   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03197                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03198   return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
03199 }
03200
03201 /**
03202   * @brief  Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
03203   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_SetCompareMode\n
03204   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_SetCompareMode
03205   * @note In auto-delayed mode  the compare match occurs independently from the timer counter value.
03206   * @param  HRTIMx High Resolution Timer instance
03207   * @param  Timer This parameter can be one of the following values:
03208   *         @arg @ref LL_HRTIM_TIMER_A
03209   *         @arg @ref LL_HRTIM_TIMER_B
03210   *         @arg @ref LL_HRTIM_TIMER_C
03211   *         @arg @ref LL_HRTIM_TIMER_D
03212   *         @arg @ref LL_HRTIM_TIMER_E
03213   * @param  CompareUnit This parameter can be one of the following values:
03214   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
03215   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
03216   * @param  Mode This parameter can be one of the following values:
03217   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
03218   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
03219   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
03220   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
03221   * @retval None
03222   */
03223 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
03224                                                  uint32_t Mode)
03225 {
03226   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03227   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03228                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03229   register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
03230   MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
03231 }
03232
03233 /**
03234   * @brief  Get the functioning mode of the compare unit.
03235   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_GetCompareMode\n
03236   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_GetCompareMode
03237   * @param  HRTIMx High Resolution Timer instance
03238   * @param  Timer This parameter can be one of the following values:
03239   *         @arg @ref LL_HRTIM_TIMER_A
03240   *         @arg @ref LL_HRTIM_TIMER_B
03241   *         @arg @ref LL_HRTIM_TIMER_C
03242   *         @arg @ref LL_HRTIM_TIMER_D
03243   *         @arg @ref LL_HRTIM_TIMER_E
03244   * @param  CompareUnit This parameter can be one of the following values:
03245   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
03246   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
03247   * @retval Mode Returned value can be one of the following values:
03248   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
03249   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
03250   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
03251   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
03252   */
03253 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
03254 {
03255   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03256   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03257                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03258   register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
03259   return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >>  shift);
03260 }
03261
03262 /**
03263   * @brief  Set the timer counter value.
03264   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_SetCounter\n
03265   *         CNTxR        CNTx       LL_HRTIM_TIM_SetCounter
03266   * @note  This function can only be called when the timer is stopped.
03267   * @note  For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
03268   *        significant bits of the counter are not significant. They cannot be
03269   *        written and return 0 when read.
03270   * @note The timer behavior is not guaranteed if the counter value is set above
03271   *       the period.
03272   * @param  HRTIMx High Resolution Timer instance
03273   * @param  Timer This parameter can be one of the following values:
03274   *         @arg @ref LL_HRTIM_TIMER_MASTER
03275   *         @arg @ref LL_HRTIM_TIMER_A
03276   *         @arg @ref LL_HRTIM_TIMER_B
03277   *         @arg @ref LL_HRTIM_TIMER_C
03278   *         @arg @ref LL_HRTIM_TIMER_D
03279   *         @arg @ref LL_HRTIM_TIMER_E
03280   * @param  Counter Value between 0 and 0xFFFF
03281   * @retval None
03282   */
03283 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
03284 {
03285   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03286   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
03287                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03288   MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
03289 }
03290
03291 /**
03292   * @brief  Get actual timer counter value.
03293   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_GetCounter\n
03294   *         CNTxR        CNTx       LL_HRTIM_TIM_GetCounter
03295   * @param  HRTIMx High Resolution Timer instance
03296   * @param  Timer This parameter can be one of the following values:
03297   *         @arg @ref LL_HRTIM_TIMER_MASTER
03298   *         @arg @ref LL_HRTIM_TIMER_A
03299   *         @arg @ref LL_HRTIM_TIMER_B
03300   *         @arg @ref LL_HRTIM_TIMER_C
03301   *         @arg @ref LL_HRTIM_TIMER_D
03302   *         @arg @ref LL_HRTIM_TIMER_E
03303   * @retval Counter Value between 0 and 0xFFFF
03304   */
03305 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03306 {
03307   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03308   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
03309                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03310   return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
03311 }
03312
03313 /**
03314   * @brief  Set the timer period value.
03315   * @rmtoll MPER        MPER       LL_HRTIM_TIM_SetPeriod\n
03316   *         PERxR       PERx       LL_HRTIM_TIM_SetPeriod
03317   * @param  HRTIMx High Resolution Timer instance
03318   * @param  Timer This parameter can be one of the following values:
03319   *         @arg @ref LL_HRTIM_TIMER_MASTER
03320   *         @arg @ref LL_HRTIM_TIMER_A
03321   *         @arg @ref LL_HRTIM_TIMER_B
03322   *         @arg @ref LL_HRTIM_TIMER_C
03323   *         @arg @ref LL_HRTIM_TIMER_D
03324   *         @arg @ref LL_HRTIM_TIMER_E
03325   * @param  Period Value between 0 and 0xFFFF
03326   * @retval None
03327   */
03328 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
03329 {
03330   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03331   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
03332                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03333   MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
03334 }
03335
03336 /**
03337   * @brief  Get actual timer period value.
03338   * @rmtoll MPER        MPER       LL_HRTIM_TIM_GetPeriod\n
03339   *         PERxR       PERx       LL_HRTIM_TIM_GetPeriod
03340   * @param  HRTIMx High Resolution Timer instance
03341   * @param  Timer This parameter can be one of the following values:
03342   *         @arg @ref LL_HRTIM_TIMER_MASTER
03343   *         @arg @ref LL_HRTIM_TIMER_A
03344   *         @arg @ref LL_HRTIM_TIMER_B
03345   *         @arg @ref LL_HRTIM_TIMER_C
03346   *         @arg @ref LL_HRTIM_TIMER_D
03347   *         @arg @ref LL_HRTIM_TIMER_E
03348   * @retval Period Value between 0 and 0xFFFF
03349   */
03350 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03351 {
03352   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03353   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
03354                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03355   return (READ_BIT(*pReg, HRTIM_MPER_MPER));
03356 }
03357
03358 /**
03359   * @brief  Set the timer repetition period value.
03360   * @rmtoll MREP        MREP       LL_HRTIM_TIM_SetRepetition\n
03361   *         REPxR       REPx       LL_HRTIM_TIM_SetRepetition
03362   * @param  HRTIMx High Resolution Timer instance
03363   * @param  Timer This parameter can be one of the following values:
03364   *         @arg @ref LL_HRTIM_TIMER_MASTER
03365   *         @arg @ref LL_HRTIM_TIMER_A
03366   *         @arg @ref LL_HRTIM_TIMER_B
03367   *         @arg @ref LL_HRTIM_TIMER_C
03368   *         @arg @ref LL_HRTIM_TIMER_D
03369   *         @arg @ref LL_HRTIM_TIMER_E
03370   * @param  Repetition Value between 0 and 0xFF
03371   * @retval None
03372   */
03373 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
03374 {
03375   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03376   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
03377                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03378   MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
03379 }
03380
03381 /**
03382   * @brief  Get actual timer repetition period value.
03383   * @rmtoll MREP        MREP       LL_HRTIM_TIM_GetRepetition\n
03384   *         REPxR       REPx       LL_HRTIM_TIM_GetRepetition
03385   * @param  HRTIMx High Resolution Timer instance
03386   * @param  Timer This parameter can be one of the following values:
03387   *         @arg @ref LL_HRTIM_TIMER_MASTER
03388   *         @arg @ref LL_HRTIM_TIMER_A
03389   *         @arg @ref LL_HRTIM_TIMER_B
03390   *         @arg @ref LL_HRTIM_TIMER_C
03391   *         @arg @ref LL_HRTIM_TIMER_D
03392   *         @arg @ref LL_HRTIM_TIMER_E
03393   * @retval Repetition Value between 0 and 0xFF
03394   */
03395 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03396 {
03397   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03398   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
03399                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03400   return (READ_BIT(*pReg, HRTIM_MREP_MREP));
03401 }
03402
03403 /**
03404   * @brief  Set the compare value of the compare unit 1.
03405   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_SetCompare1\n
03406   *         CMP1xR      CMP1x       LL_HRTIM_TIM_SetCompare1
03407   * @param  HRTIMx High Resolution Timer instance
03408   * @param  Timer This parameter can be one of the following values:
03409   *         @arg @ref LL_HRTIM_TIMER_MASTER
03410   *         @arg @ref LL_HRTIM_TIMER_A
03411   *         @arg @ref LL_HRTIM_TIMER_B
03412   *         @arg @ref LL_HRTIM_TIMER_C
03413   *         @arg @ref LL_HRTIM_TIMER_D
03414   *         @arg @ref LL_HRTIM_TIMER_E
03415   * @param  CompareValue Compare value must be above or equal to 3
03416   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03417   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03418   * @retval None
03419   */
03420 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03421 {
03422   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03423   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
03424                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03425   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
03426 }
03427
03428 /**
03429   * @brief  Get actual compare value of the compare unit 1.
03430   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_GetCompare1\n
03431   *         CMP1xR      CMP1x       LL_HRTIM_TIM_GetCompare1
03432   * @param  HRTIMx High Resolution Timer instance
03433   * @param  Timer This parameter can be one of the following values:
03434   *         @arg @ref LL_HRTIM_TIMER_MASTER
03435   *         @arg @ref LL_HRTIM_TIMER_A
03436   *         @arg @ref LL_HRTIM_TIMER_B
03437   *         @arg @ref LL_HRTIM_TIMER_C
03438   *         @arg @ref LL_HRTIM_TIMER_D
03439   *         @arg @ref LL_HRTIM_TIMER_E
03440   * @retval CompareValue Compare value must be above or equal to 3
03441   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03442   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03443   */
03444 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03445 {
03446   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03447   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
03448                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03449   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
03450 }
03451
03452 /**
03453   * @brief  Set the compare value of the compare unit 2.
03454   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_SetCompare2\n
03455   *         CMP2xR      CMP2x       LL_HRTIM_TIM_SetCompare2
03456   * @param  HRTIMx High Resolution Timer instance
03457   * @param  Timer This parameter can be one of the following values:
03458   *         @arg @ref LL_HRTIM_TIMER_MASTER
03459   *         @arg @ref LL_HRTIM_TIMER_A
03460   *         @arg @ref LL_HRTIM_TIMER_B
03461   *         @arg @ref LL_HRTIM_TIMER_C
03462   *         @arg @ref LL_HRTIM_TIMER_D
03463   *         @arg @ref LL_HRTIM_TIMER_E
03464   * @param  CompareValue Compare value must be above or equal to 3
03465   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03466   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03467   * @retval None
03468   */
03469 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03470 {
03471   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03472   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
03473                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03474   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
03475 }
03476
03477 /**
03478   * @brief  Get actual compare value of the compare unit 2.
03479   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_GetCompare2\n
03480   *         CMP2xR      CMP2x       LL_HRTIM_TIM_GetCompare2\n
03481   * @param  HRTIMx High Resolution Timer instance
03482   * @param  Timer This parameter can be one of the following values:
03483   *         @arg @ref LL_HRTIM_TIMER_MASTER
03484   *         @arg @ref LL_HRTIM_TIMER_A
03485   *         @arg @ref LL_HRTIM_TIMER_B
03486   *         @arg @ref LL_HRTIM_TIMER_C
03487   *         @arg @ref LL_HRTIM_TIMER_D
03488   *         @arg @ref LL_HRTIM_TIMER_E
03489   * @retval CompareValue Compare value must be above or equal to 3
03490   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03491   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03492   */
03493 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03494 {
03495   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03496   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
03497                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03498   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
03499 }
03500
03501 /**
03502   * @brief  Set the compare value of the compare unit 3.
03503   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_SetCompare3\n
03504   *         CMP3xR      CMP3x       LL_HRTIM_TIM_SetCompare3
03505   * @param  HRTIMx High Resolution Timer instance
03506   * @param  Timer This parameter can be one of the following values:
03507   *         @arg @ref LL_HRTIM_TIMER_MASTER
03508   *         @arg @ref LL_HRTIM_TIMER_A
03509   *         @arg @ref LL_HRTIM_TIMER_B
03510   *         @arg @ref LL_HRTIM_TIMER_C
03511   *         @arg @ref LL_HRTIM_TIMER_D
03512   *         @arg @ref LL_HRTIM_TIMER_E
03513   * @param  CompareValue Compare value must be above or equal to 3
03514   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03515   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03516   * @retval None
03517   */
03518 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03519 {
03520   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03521   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
03522                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03523   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
03524 }
03525
03526 /**
03527   * @brief  Get actual compare value of the compare unit 3.
03528   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_GetCompare3\n
03529   *         CMP3xR      CMP3x       LL_HRTIM_TIM_GetCompare3
03530   * @param  HRTIMx High Resolution Timer instance
03531   * @param  Timer This parameter can be one of the following values:
03532   *         @arg @ref LL_HRTIM_TIMER_MASTER
03533   *         @arg @ref LL_HRTIM_TIMER_A
03534   *         @arg @ref LL_HRTIM_TIMER_B
03535   *         @arg @ref LL_HRTIM_TIMER_C
03536   *         @arg @ref LL_HRTIM_TIMER_D
03537   *         @arg @ref LL_HRTIM_TIMER_E
03538   * @retval CompareValue Compare value must be above or equal to 3
03539   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03540   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03541   */
03542 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03543 {
03544   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03545   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
03546                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03547   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
03548 }
03549
03550 /**
03551   * @brief  Set the compare value of the compare unit 4.
03552   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_SetCompare4\n
03553   *         CMP4xR      CMP4x       LL_HRTIM_TIM_SetCompare4
03554   * @param  HRTIMx High Resolution Timer instance
03555   * @param  Timer This parameter can be one of the following values:
03556   *         @arg @ref LL_HRTIM_TIMER_MASTER
03557   *         @arg @ref LL_HRTIM_TIMER_A
03558   *         @arg @ref LL_HRTIM_TIMER_B
03559   *         @arg @ref LL_HRTIM_TIMER_C
03560   *         @arg @ref LL_HRTIM_TIMER_D
03561   *         @arg @ref LL_HRTIM_TIMER_E
03562   * @param  CompareValue Compare value must be above or equal to 3
03563   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03564   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03565   * @retval None
03566   */
03567 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
03568 {
03569   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03570   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
03571                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03572   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
03573 }
03574
03575 /**
03576   * @brief  Get actual compare value of the compare unit 4.
03577   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_GetCompare4\n
03578   *         CMP4xR      CMP4x       LL_HRTIM_TIM_GetCompare4
03579   * @param  HRTIMx High Resolution Timer instance
03580   * @param  Timer This parameter can be one of the following values:
03581   *         @arg @ref LL_HRTIM_TIMER_MASTER
03582   *         @arg @ref LL_HRTIM_TIMER_A
03583   *         @arg @ref LL_HRTIM_TIMER_B
03584   *         @arg @ref LL_HRTIM_TIMER_C
03585   *         @arg @ref LL_HRTIM_TIMER_D
03586   *         @arg @ref LL_HRTIM_TIMER_E
03587   * @retval CompareValue Compare value must be above or equal to 3
03588   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
03589   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
03590   */
03591 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03592 {
03593   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03594   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
03595                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03596   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
03597 }
03598
03599 /**
03600   * @brief  Set the reset trigger of a timer counter.
03601   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_SetResetTrig\n
03602   *         RSTxR      CMP2           LL_HRTIM_TIM_SetResetTrig\n
03603   *         RSTxR      CMP4           LL_HRTIM_TIM_SetResetTrig\n
03604   *         RSTxR      MSTPER         LL_HRTIM_TIM_SetResetTrig\n
03605   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_SetResetTrig\n
03606   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_SetResetTrig\n
03607   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_SetResetTrig\n
03608   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_SetResetTrig\n
03609   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_SetResetTrig\n
03610   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_SetResetTrig\n
03611   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_SetResetTrig\n
03612   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_SetResetTrig\n
03613   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_SetResetTrig\n
03614   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_SetResetTrig\n
03615   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_SetResetTrig\n
03616   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_SetResetTrig\n
03617   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_SetResetTrig\n
03618   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_SetResetTrig\n
03619   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_SetResetTrig\n
03620   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_SetResetTrig\n
03621   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_SetResetTrig\n
03622   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_SetResetTrig\n
03623   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_SetResetTrig\n
03624   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_SetResetTrig\n
03625   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_SetResetTrig\n
03626   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_SetResetTrig\n
03627   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_SetResetTrig\n
03628   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_SetResetTrig\n
03629   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_SetResetTrig\n
03630   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_SetResetTrig
03631   * @note The reset of the timer counter can be triggered by up to 30 events
03632   *       that can be selected among the following sources:
03633   *         @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
03634   *         @arg The master timer: Reset and Compare 1..4 (5 events).
03635   *         @arg The external events EXTEVNT1..10 (10 events).
03636   *         @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
03637   * @param  HRTIMx High Resolution Timer instance
03638   * @param  Timer This parameter can be one of the following values:
03639   *         @arg @ref LL_HRTIM_TIMER_A
03640   *         @arg @ref LL_HRTIM_TIMER_B
03641   *         @arg @ref LL_HRTIM_TIMER_C
03642   *         @arg @ref LL_HRTIM_TIMER_D
03643   *         @arg @ref LL_HRTIM_TIMER_E
03644   * @param  ResetTrig This parameter can be a combination of the following values:
03645   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
03646   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
03647   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
03648   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
03649   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
03650   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
03651   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
03652   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
03653   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
03654   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
03655   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
03656   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
03657   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
03658   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
03659   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
03660   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
03661   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
03662   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
03663   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
03664   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
03665   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
03666   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
03667   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
03668   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
03669   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
03670   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
03671   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
03672   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
03673   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
03674   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
03675   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
03676   * @retval None
03677   */
03678 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
03679 {
03680   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03681   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
03682                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03683   WRITE_REG(*pReg, ResetTrig);
03684 }
03685
03686 /**
03687   * @brief  Get actual reset trigger of a timer counter.
03688   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_GetResetTrig\n
03689   *         RSTxR      CMP2           LL_HRTIM_TIM_GetResetTrig\n
03690   *         RSTxR      CMP4           LL_HRTIM_TIM_GetResetTrig\n
03691   *         RSTxR      MSTPER         LL_HRTIM_TIM_GetResetTrig\n
03692   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_GetResetTrig\n
03693   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_GetResetTrig\n
03694   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_GetResetTrig\n
03695   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_GetResetTrig\n
03696   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_GetResetTrig\n
03697   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_GetResetTrig\n
03698   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_GetResetTrig\n
03699   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_GetResetTrig\n
03700   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_GetResetTrig\n
03701   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_GetResetTrig\n
03702   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_GetResetTrig\n
03703   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_GetResetTrig\n
03704   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_GetResetTrig\n
03705   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_GetResetTrig\n
03706   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_GetResetTrig\n
03707   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_GetResetTrig\n
03708   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_GetResetTrig\n
03709   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_GetResetTrig\n
03710   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_GetResetTrig\n
03711   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_GetResetTrig\n
03712   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_GetResetTrig\n
03713   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_GetResetTrig\n
03714   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_GetResetTrig\n
03715   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_GetResetTrig\n
03716   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_GetResetTrig\n
03717   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_GetResetTrig
03718   * @param  HRTIMx High Resolution Timer instance
03719   * @param  Timer This parameter can be one of the following values:
03720   *         @arg @ref LL_HRTIM_TIMER_A
03721   *         @arg @ref LL_HRTIM_TIMER_B
03722   *         @arg @ref LL_HRTIM_TIMER_C
03723   *         @arg @ref LL_HRTIM_TIMER_D
03724   *         @arg @ref LL_HRTIM_TIMER_E
03725   * @retval ResetTrig Returned value can be one of the following values:
03726   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
03727   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
03728   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
03729   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
03730   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
03731   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
03732   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
03733   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
03734   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
03735   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
03736   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
03737   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
03738   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
03739   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
03740   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
03741   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
03742   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
03743   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
03744   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
03745   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
03746   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
03747   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
03748   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
03749   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
03750   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
03751   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
03752   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
03753   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
03754   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
03755   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
03756   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
03757   */
03758 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03759 {
03760   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03761   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
03762                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03763   return (READ_REG(*pReg));
03764 }
03765
03766 /**
03767   * @brief  Get captured value for capture unit 1.
03768   * @rmtoll CPT1xR      CPT1x           LL_HRTIM_TIM_GetCapture1
03769   * @param  HRTIMx High Resolution Timer instance
03770   * @param  Timer This parameter can be one of the following values:
03771   *         @arg @ref LL_HRTIM_TIMER_A
03772   *         @arg @ref LL_HRTIM_TIMER_B
03773   *         @arg @ref LL_HRTIM_TIMER_C
03774   *         @arg @ref LL_HRTIM_TIMER_D
03775   *         @arg @ref LL_HRTIM_TIMER_E
03776   * @retval Captured value
03777   */
03778 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03779 {
03780   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03781   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
03782                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03783   return (READ_REG(*pReg));
03784 }
03785
03786 /**
03787   * @brief  Get captured value for capture unit 2.
03788   * @rmtoll CPT2xR      CPT2x           LL_HRTIM_TIM_GetCapture2
03789   * @param  HRTIMx High Resolution Timer instance
03790   * @param  Timer This parameter can be one of the following values:
03791   *         @arg @ref LL_HRTIM_TIMER_A
03792   *         @arg @ref LL_HRTIM_TIMER_B
03793   *         @arg @ref LL_HRTIM_TIMER_C
03794   *         @arg @ref LL_HRTIM_TIMER_D
03795   *         @arg @ref LL_HRTIM_TIMER_E
03796   * @retval Captured value
03797   */
03798 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03799 {
03800   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03801   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
03802                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03803   return (READ_REG(*pReg));
03804 }
03805
03806 /**
03807   * @brief  Set the trigger of a capture unit for a given timer.
03808   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_SetCaptureTrig\n
03809   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_SetCaptureTrig\n
03810   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03811   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03812   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03813   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03814   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03815   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03816   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03817   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03818   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_SetCaptureTrig\n
03819   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_SetCaptureTrig\n
03820   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03821   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03822   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03823   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03824   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03825   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03826   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03827   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03828   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03829   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03830   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03831   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03832   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03833   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03834   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03835   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
03836   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_SetCaptureTrig\n
03837   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_SetCaptureTrig\n
03838   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_SetCaptureTrig\n
03839   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_SetCaptureTrig
03840   * @param  HRTIMx High Resolution Timer instance
03841   * @param  Timer This parameter can be one of the following values:
03842   *         @arg @ref LL_HRTIM_TIMER_A
03843   *         @arg @ref LL_HRTIM_TIMER_B
03844   *         @arg @ref LL_HRTIM_TIMER_C
03845   *         @arg @ref LL_HRTIM_TIMER_D
03846   *         @arg @ref LL_HRTIM_TIMER_E
03847   * @param  CaptureUnit This parameter can be one of the following values:
03848   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
03849   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
03850   * @param  CaptureTrig This parameter can be a combination of the following values:
03851   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
03852   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
03853   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
03854   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
03855   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
03856   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
03857   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
03858   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
03859   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
03860   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
03861   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
03862   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
03863   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
03864   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
03865   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
03866   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
03867   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
03868   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
03869   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
03870   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
03871   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
03872   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
03873   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
03874   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
03875   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
03876   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
03877   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
03878   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
03879   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
03880   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
03881   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
03882   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
03883   * @retval None
03884   */
03885 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
03886                                                  uint32_t CaptureTrig)
03887 {
03888   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03889   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
03890                                                               REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
03891   WRITE_REG(*pReg, CaptureTrig);
03892 }
03893
03894 /**
03895   * @brief  Get actual trigger of a capture unit for a given timer.
03896   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_GetCaptureTrig\n
03897   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_GetCaptureTrig\n
03898   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03899   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03900   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03901   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03902   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03903   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03904   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03905   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03906   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_GetCaptureTrig\n
03907   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_GetCaptureTrig\n
03908   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03909   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03910   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03911   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03912   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03913   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03914   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03915   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03916   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03917   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03918   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03919   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03920   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03921   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03922   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03923   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
03924   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_GetCaptureTrig\n
03925   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_GetCaptureTrig\n
03926   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_GetCaptureTrig\n
03927   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_GetCaptureTrig
03928   * @param  HRTIMx High Resolution Timer instance
03929   * @param  Timer This parameter can be one of the following values:
03930   *         @arg @ref LL_HRTIM_TIMER_A
03931   *         @arg @ref LL_HRTIM_TIMER_B
03932   *         @arg @ref LL_HRTIM_TIMER_C
03933   *         @arg @ref LL_HRTIM_TIMER_D
03934   *         @arg @ref LL_HRTIM_TIMER_E
03935   * @param  CaptureUnit This parameter can be one of the following values:
03936   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
03937   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
03938   * @retval CaptureTrig This parameter can be a combination of the following values:
03939   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
03940   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
03941   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
03942   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
03943   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
03944   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
03945   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
03946   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
03947   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
03948   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
03949   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
03950   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
03951   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
03952   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
03953   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
03954   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
03955   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
03956   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
03957   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
03958   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
03959   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
03960   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
03961   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
03962   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
03963   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
03964   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
03965   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
03966   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
03967   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
03968   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
03969   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
03970   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
03971   */
03972 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
03973 {
03974   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03975   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
03976                                                                     REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
03977   return (READ_REG(*pReg));
03978 }
03979
03980 /**
03981   * @brief  Enable deadtime insertion for a given timer.
03982   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_EnableDeadTime
03983   * @param  HRTIMx High Resolution Timer instance
03984   * @param  Timer This parameter can be one of the following values:
03985   *         @arg @ref LL_HRTIM_TIMER_A
03986   *         @arg @ref LL_HRTIM_TIMER_B
03987   *         @arg @ref LL_HRTIM_TIMER_C
03988   *         @arg @ref LL_HRTIM_TIMER_D
03989   *         @arg @ref LL_HRTIM_TIMER_E
03990   * @retval None
03991   */
03992 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03993 {
03994   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03995   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
03996                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03997   SET_BIT(*pReg, HRTIM_OUTR_DTEN);
03998 }
03999
04000 /**
04001   * @brief  Disable deadtime insertion for a given timer.
04002   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_DisableDeadTime
04003   * @param  HRTIMx High Resolution Timer instance
04004   * @param  Timer This parameter can be one of the following values:
04005   *         @arg @ref LL_HRTIM_TIMER_A
04006   *         @arg @ref LL_HRTIM_TIMER_B
04007   *         @arg @ref LL_HRTIM_TIMER_C
04008   *         @arg @ref LL_HRTIM_TIMER_D
04009   *         @arg @ref LL_HRTIM_TIMER_E
04010   * @retval None
04011   */
04012 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04013 {
04014   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04015   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04016                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04017   CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
04018 }
04019
04020 /**
04021   * @brief  Indicate whether deadtime insertion is enabled for a given timer.
04022   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_IsEnabledDeadTime
04023   * @param  HRTIMx High Resolution Timer instance
04024   * @param  Timer This parameter can be one of the following values:
04025   *         @arg @ref LL_HRTIM_TIMER_A
04026   *         @arg @ref LL_HRTIM_TIMER_B
04027   *         @arg @ref LL_HRTIM_TIMER_C
04028   *         @arg @ref LL_HRTIM_TIMER_D
04029   *         @arg @ref LL_HRTIM_TIMER_E
04030   * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
04031   */
04032 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04033 {
04034   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04035   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04036                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04037
04038   return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
04039 }
04040
04041 /**
04042   * @brief  Set the delayed protection (DLYPRT) mode.
04043   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_SetDLYPRTMode\n
04044   *         OUTxR      DLYPRT         LL_HRTIM_TIM_SetDLYPRTMode
04045   * @note   This function must be called prior enabling the delayed protection
04046   * @note   Balanced Idle mode is only available in push-pull mode
04047   * @param  HRTIMx High Resolution Timer instance
04048   * @param  Timer This parameter can be one of the following values:
04049   *         @arg @ref LL_HRTIM_TIMER_A
04050   *         @arg @ref LL_HRTIM_TIMER_B
04051   *         @arg @ref LL_HRTIM_TIMER_C
04052   *         @arg @ref LL_HRTIM_TIMER_D
04053   *         @arg @ref LL_HRTIM_TIMER_E
04054   * @param  DLYPRTMode Delayed protection (DLYPRT) mode
04055   *
04056   *         For timers A, B and C this parameter can be one of the following values:
04057   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
04058   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
04059   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
04060   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
04061   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
04062   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
04063   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
04064   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
04065   *
04066   *         For timers D and E this parameter can be one of the following values:
04067   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
04068   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
04069   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
04070   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
04071   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
04072   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
04073   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
04074   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
04075   * @retval None
04076   */
04077 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
04078 {
04079   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04080   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04081                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04082   MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
04083 }
04084
04085 /**
04086   * @brief  Get the delayed protection (DLYPRT) mode.
04087   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_GetDLYPRTMode\n
04088   *         OUTxR      DLYPRT         LL_HRTIM_TIM_GetDLYPRTMode
04089   * @param  HRTIMx High Resolution Timer instance
04090   * @param  Timer This parameter can be one of the following values:
04091   *         @arg @ref LL_HRTIM_TIMER_A
04092   *         @arg @ref LL_HRTIM_TIMER_B
04093   *         @arg @ref LL_HRTIM_TIMER_C
04094   *         @arg @ref LL_HRTIM_TIMER_D
04095   *         @arg @ref LL_HRTIM_TIMER_E
04096   * @retval DLYPRTMode Delayed protection (DLYPRT) mode
04097   *
04098   *         For timers A, B and C this parameter can be one of the following values:
04099   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
04100   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
04101   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
04102   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
04103   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
04104   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
04105   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
04106   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
04107   *
04108   *         For timers D and E this parameter can be one of the following values:
04109   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
04110   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
04111   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
04112   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
04113   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
04114   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
04115   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
04116   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
04117   */
04118 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04119 {
04120   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04121   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04122                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04123   return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
04124 }
04125
04126 /**
04127   * @brief  Enable delayed protection (DLYPRT) for a given timer.
04128   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_EnableDLYPRT
04129   * @note   This function must not be called once the concerned timer is enabled
04130   * @param  HRTIMx High Resolution Timer instance
04131   * @param  Timer This parameter can be one of the following values:
04132   *         @arg @ref LL_HRTIM_TIMER_A
04133   *         @arg @ref LL_HRTIM_TIMER_B
04134   *         @arg @ref LL_HRTIM_TIMER_C
04135   *         @arg @ref LL_HRTIM_TIMER_D
04136   *         @arg @ref LL_HRTIM_TIMER_E
04137   * @retval None
04138   */
04139 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04140 {
04141   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04142   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04143                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04144   SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
04145 }
04146
04147 /**
04148   * @brief  Disable delayed protection (DLYPRT) for a given timer.
04149   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_DisableDLYPRT
04150   * @note   This function must not be called once the concerned timer is enabled
04151   * @param  HRTIMx High Resolution Timer instance
04152   * @param  Timer This parameter can be one of the following values:
04153   *         @arg @ref LL_HRTIM_TIMER_A
04154   *         @arg @ref LL_HRTIM_TIMER_B
04155   *         @arg @ref LL_HRTIM_TIMER_C
04156   *         @arg @ref LL_HRTIM_TIMER_D
04157   *         @arg @ref LL_HRTIM_TIMER_E
04158   * @retval None
04159   */
04160 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04161 {
04162   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04163   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04164                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04165   CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
04166 }
04167
04168 /**
04169   * @brief  Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
04170   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_IsEnabledDLYPRT
04171   * @param  HRTIMx High Resolution Timer instance
04172   * @param  Timer This parameter can be one of the following values:
04173   *         @arg @ref LL_HRTIM_TIMER_A
04174   *         @arg @ref LL_HRTIM_TIMER_B
04175   *         @arg @ref LL_HRTIM_TIMER_C
04176   *         @arg @ref LL_HRTIM_TIMER_D
04177   *         @arg @ref LL_HRTIM_TIMER_E
04178   * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
04179   */
04180 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04181 {
04182   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04183   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
04184                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04185   return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
04186 }
04187
04188 /**
04189   * @brief  Enable the fault channel(s) for a given timer.
04190   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_EnableFault\n
04191   *         FLTxR      FLT2EN       LL_HRTIM_TIM_EnableFault\n
04192   *         FLTxR      FLT3EN       LL_HRTIM_TIM_EnableFault\n
04193   *         FLTxR      FLT4EN       LL_HRTIM_TIM_EnableFault\n
04194   *         FLTxR      FLT5EN       LL_HRTIM_TIM_EnableFault
04195   * @param  HRTIMx High Resolution Timer instance
04196   * @param  Timer This parameter can be one of the following values:
04197   *         @arg @ref LL_HRTIM_TIMER_A
04198   *         @arg @ref LL_HRTIM_TIMER_B
04199   *         @arg @ref LL_HRTIM_TIMER_C
04200   *         @arg @ref LL_HRTIM_TIMER_D
04201   *         @arg @ref LL_HRTIM_TIMER_E
04202   * @param  Faults This parameter can be a combination of the following values:
04203   *         @arg @ref LL_HRTIM_FAULT_1
04204   *         @arg @ref LL_HRTIM_FAULT_2
04205   *         @arg @ref LL_HRTIM_FAULT_3
04206   *         @arg @ref LL_HRTIM_FAULT_4
04207   *         @arg @ref LL_HRTIM_FAULT_5
04208   * @retval None
04209   */
04210 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
04211 {
04212   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04213   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04214                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04215   SET_BIT(*pReg, Faults);
04216 }
04217
04218 /**
04219   * @brief  Disable the fault channel(s) for a given timer.
04220   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_DisableFault\n
04221   *         FLTxR      FLT2EN       LL_HRTIM_TIM_DisableFault\n
04222   *         FLTxR      FLT3EN       LL_HRTIM_TIM_DisableFault\n
04223   *         FLTxR      FLT4EN       LL_HRTIM_TIM_DisableFault\n
04224   *         FLTxR      FLT5EN       LL_HRTIM_TIM_DisableFault
04225   * @param  HRTIMx High Resolution Timer instance
04226   * @param  Timer This parameter can be one of the following values:
04227   *         @arg @ref LL_HRTIM_TIMER_A
04228   *         @arg @ref LL_HRTIM_TIMER_B
04229   *         @arg @ref LL_HRTIM_TIMER_C
04230   *         @arg @ref LL_HRTIM_TIMER_D
04231   *         @arg @ref LL_HRTIM_TIMER_E
04232   * @param  Faults This parameter can be a combination of the following values:
04233   *         @arg @ref LL_HRTIM_FAULT_1
04234   *         @arg @ref LL_HRTIM_FAULT_2
04235   *         @arg @ref LL_HRTIM_FAULT_3
04236   *         @arg @ref LL_HRTIM_FAULT_4
04237   *         @arg @ref LL_HRTIM_FAULT_5
04238   * @retval None
04239   */
04240 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
04241 {
04242   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04243   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04244                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04245   CLEAR_BIT(*pReg, Faults);
04246 }
04247
04248 /**
04249   * @brief  Indicate whether the fault channel is enabled for a given timer.
04250   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_IsEnabledFault\n
04251   *         FLTxR      FLT2EN       LL_HRTIM_TIM_IsEnabledFault\n
04252   *         FLTxR      FLT3EN       LL_HRTIM_TIM_IsEnabledFault\n
04253   *         FLTxR      FLT4EN       LL_HRTIM_TIM_IsEnabledFault\n
04254   *         FLTxR      FLT5EN       LL_HRTIM_TIM_IsEnabledFault
04255   * @param  HRTIMx High Resolution Timer instance
04256   * @param  Timer This parameter can be one of the following values:
04257   *         @arg @ref LL_HRTIM_TIMER_A
04258   *         @arg @ref LL_HRTIM_TIMER_B
04259   *         @arg @ref LL_HRTIM_TIMER_C
04260   *         @arg @ref LL_HRTIM_TIMER_D
04261   *         @arg @ref LL_HRTIM_TIMER_E
04262   * @param  Fault This parameter can be one of the following values:
04263   *         @arg @ref LL_HRTIM_FAULT_1
04264   *         @arg @ref LL_HRTIM_FAULT_2
04265   *         @arg @ref LL_HRTIM_FAULT_3
04266   *         @arg @ref LL_HRTIM_FAULT_4
04267   *         @arg @ref LL_HRTIM_FAULT_5
04268   * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
04269   */
04270 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
04271 {
04272   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04273   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04274                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04275
04276   return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
04277 }
04278
04279 /**
04280   * @brief  Lock the fault conditioning set-up for a given timer.
04281   * @rmtoll FLTxR      FLTLCK       LL_HRTIM_TIM_LockFault
04282   * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
04283   * @param  HRTIMx High Resolution Timer instance
04284   * @param  Timer This parameter can be one of the following values:
04285   *         @arg @ref LL_HRTIM_TIMER_A
04286   *         @arg @ref LL_HRTIM_TIMER_B
04287   *         @arg @ref LL_HRTIM_TIMER_C
04288   *         @arg @ref LL_HRTIM_TIMER_D
04289   *         @arg @ref LL_HRTIM_TIMER_E
04290   * @retval None
04291   */
04292 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04293 {
04294   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04295   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
04296                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04297   SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
04298 }
04299
04300 /**
04301   * @brief  Define how the timer behaves during a burst mode operation.
04302   * @rmtoll BMCR      MTBM       LL_HRTIM_TIM_SetBurstModeOption\n
04303   *         BMCR      TABM       LL_HRTIM_TIM_SetBurstModeOption\n
04304   *         BMCR      TBBM       LL_HRTIM_TIM_SetBurstModeOption\n
04305   *         BMCR      TCBM       LL_HRTIM_TIM_SetBurstModeOption\n
04306   *         BMCR      TDBM       LL_HRTIM_TIM_SetBurstModeOption\n
04307   *         BMCR      TEBM       LL_HRTIM_TIM_SetBurstModeOption
04308   * @note This function must not be called when the burst mode is enabled
04309   * @param  HRTIMx High Resolution Timer instance
04310   * @param  Timer This parameter can be one of the following values:
04311   *         @arg @ref LL_HRTIM_TIMER_MASTER
04312   *         @arg @ref LL_HRTIM_TIMER_A
04313   *         @arg @ref LL_HRTIM_TIMER_B
04314   *         @arg @ref LL_HRTIM_TIMER_C
04315   *         @arg @ref LL_HRTIM_TIMER_D
04316   *         @arg @ref LL_HRTIM_TIMER_E
04317   * @param  BurtsModeOption This parameter can be one of the following values:
04318   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
04319   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
04320   * @retval None
04321   */
04322 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
04323 {
04324   register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
04325   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
04326 }
04327
04328 /**
04329   * @brief  Retrieve how the timer behaves during a burst mode operation.
04330   * @rmtoll BMCR      MCR        LL_HRTIM_TIM_GetBurstModeOption\n
04331   *         BMCR      TABM       LL_HRTIM_TIM_GetBurstModeOption\n
04332   *         BMCR      TBBM       LL_HRTIM_TIM_GetBurstModeOption\n
04333   *         BMCR      TCBM       LL_HRTIM_TIM_GetBurstModeOption\n
04334   *         BMCR      TDBM       LL_HRTIM_TIM_GetBurstModeOption\n
04335   *         BMCR      TEBM       LL_HRTIM_TIM_GetBurstModeOption
04336   * @param  HRTIMx High Resolution Timer instance
04337   * @param  Timer This parameter can be one of the following values:
04338   *         @arg @ref LL_HRTIM_TIMER_MASTER
04339   *         @arg @ref LL_HRTIM_TIMER_A
04340   *         @arg @ref LL_HRTIM_TIMER_B
04341   *         @arg @ref LL_HRTIM_TIMER_C
04342   *         @arg @ref LL_HRTIM_TIMER_D
04343   *         @arg @ref LL_HRTIM_TIMER_E
04344   * @retval BurtsMode This parameter can be one of the following values:
04345   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
04346   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
04347   */
04348 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04349 {
04350   register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
04351   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
04352 }
04353
04354 /**
04355   * @brief  Program which registers are to be written by Burst DMA transfers.
04356   * @rmtoll BDMUPDR      MTBM        LL_HRTIM_TIM_ConfigBurstDMA\n
04357   *         BDMUPDR      MICR        LL_HRTIM_TIM_ConfigBurstDMA\n
04358   *         BDMUPDR      MDIER       LL_HRTIM_TIM_ConfigBurstDMA\n
04359   *         BDMUPDR      MCNT        LL_HRTIM_TIM_ConfigBurstDMA\n
04360   *         BDMUPDR      MPER        LL_HRTIM_TIM_ConfigBurstDMA\n
04361   *         BDMUPDR      MREP        LL_HRTIM_TIM_ConfigBurstDMA\n
04362   *         BDMUPDR      MCMP1       LL_HRTIM_TIM_ConfigBurstDMA\n
04363   *         BDMUPDR      MCMP2       LL_HRTIM_TIM_ConfigBurstDMA\n
04364   *         BDMUPDR      MCMP3       LL_HRTIM_TIM_ConfigBurstDMA\n
04365   *         BDMUPDR      MCMP4       LL_HRTIM_TIM_ConfigBurstDMA\n
04366   *         BDTxUPDR     TIMxCR      LL_HRTIM_TIM_ConfigBurstDMA\n
04367   *         BDTxUPDR     TIMxICR     LL_HRTIM_TIM_ConfigBurstDMA\n
04368   *         BDTxUPDR     TIMxDIER    LL_HRTIM_TIM_ConfigBurstDMA\n
04369   *         BDTxUPDR     TIMxCNT     LL_HRTIM_TIM_ConfigBurstDMA\n
04370   *         BDTxUPDR     TIMxPER     LL_HRTIM_TIM_ConfigBurstDMA\n
04371   *         BDTxUPDR     TIMxREP     LL_HRTIM_TIM_ConfigBurstDMA\n
04372   *         BDTxUPDR     TIMxCMP1    LL_HRTIM_TIM_ConfigBurstDMA\n
04373   *         BDTxUPDR     TIMxCMP2    LL_HRTIM_TIM_ConfigBurstDMA\n
04374   *         BDTxUPDR     TIMxCMP3    LL_HRTIM_TIM_ConfigBurstDMA\n
04375   *         BDTxUPDR     TIMxCMP4    LL_HRTIM_TIM_ConfigBurstDMA\n
04376   *         BDTxUPDR     TIMxDTR     LL_HRTIM_TIM_ConfigBurstDMA\n
04377   *         BDTxUPDR     TIMxSET1R   LL_HRTIM_TIM_ConfigBurstDMA\n
04378   *         BDTxUPDR     TIMxRST1R   LL_HRTIM_TIM_ConfigBurstDMA\n
04379   *         BDTxUPDR     TIMxSET2R   LL_HRTIM_TIM_ConfigBurstDMA\n
04380   *         BDTxUPDR     TIMxRST2R   LL_HRTIM_TIM_ConfigBurstDMA\n
04381   *         BDTxUPDR     TIMxEEFR1   LL_HRTIM_TIM_ConfigBurstDMA\n
04382   *         BDTxUPDR     TIMxEEFR2   LL_HRTIM_TIM_ConfigBurstDMA\n
04383   *         BDTxUPDR     TIMxRSTR    LL_HRTIM_TIM_ConfigBurstDMA\n
04384   *         BDTxUPDR     TIMxOUTR    LL_HRTIM_TIM_ConfigBurstDMA\n
04385   *         BDTxUPDR     TIMxLTCH    LL_HRTIM_TIM_ConfigBurstDMA
04386   * @param  HRTIMx High Resolution Timer instance
04387   * @param  Timer This parameter can be one of the following values:
04388   *         @arg @ref LL_HRTIM_TIMER_MASTER
04389   *         @arg @ref LL_HRTIM_TIMER_A
04390   *         @arg @ref LL_HRTIM_TIMER_B
04391   *         @arg @ref LL_HRTIM_TIMER_C
04392   *         @arg @ref LL_HRTIM_TIMER_D
04393   *         @arg @ref LL_HRTIM_TIMER_E
04394   * @param  Registers Registers to be updated by the DMA request
04395   *
04396   *         For Master timer this parameter can be can be a combination of the following values:
04397   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
04398   *         @arg @ref LL_HRTIM_BURSTDMA_MCR
04399   *         @arg @ref LL_HRTIM_BURSTDMA_MICR
04400   *         @arg @ref LL_HRTIM_BURSTDMA_MDIER
04401   *         @arg @ref LL_HRTIM_BURSTDMA_MCNT
04402   *         @arg @ref LL_HRTIM_BURSTDMA_MPER
04403   *         @arg @ref LL_HRTIM_BURSTDMA_MREP
04404   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP1
04405   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP2
04406   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP3
04407   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP4
04408   *
04409   *         For Timers A..E this parameter can be can be a combination of the following values:
04410   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
04411   *         @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
04412   *         @arg @ref LL_HRTIM_BURSTDMA_TIMICR
04413   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
04414   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
04415   *         @arg @ref LL_HRTIM_BURSTDMA_TIMPER
04416   *         @arg @ref LL_HRTIM_BURSTDMA_TIMREP
04417   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
04418   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
04419   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
04420   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
04421   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
04422   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
04423   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
04424   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
04425   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
04426   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
04427   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
04428   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
04429   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
04430   *         @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
04431   *         @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
04432   * @retval None
04433   */
04434 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
04435 {
04436
04437   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04438   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
04439   WRITE_REG(*pReg, Registers);
04440 }
04441
04442 /**
04443   * @brief  Indicate on which output the signal is currently applied.
04444   * @rmtoll TIMxISR      CPPSTAT        LL_HRTIM_TIM_GetCurrentPushPullStatus
04445   * @note Only significant when the timer operates in push-pull mode.
04446   * @param  HRTIMx High Resolution Timer instance
04447   * @param  Timer This parameter can be one of the following values:
04448   *         @arg @ref LL_HRTIM_TIMER_A
04449   *         @arg @ref LL_HRTIM_TIMER_B
04450   *         @arg @ref LL_HRTIM_TIMER_C
04451   *         @arg @ref LL_HRTIM_TIMER_D
04452   *         @arg @ref LL_HRTIM_TIMER_E
04453   * @retval CPPSTAT This parameter can be one of the following values:
04454   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
04455   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
04456   */
04457 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04458 {
04459   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04460   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
04461                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04462   return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
04463 }
04464
04465 /**
04466   * @brief  Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
04467   * @rmtoll TIMxISR      IPPSTAT        LL_HRTIM_TIM_GetIdlePushPullStatus
04468   * @param  HRTIMx High Resolution Timer instance
04469   * @param  Timer This parameter can be one of the following values:
04470   *         @arg @ref LL_HRTIM_TIMER_A
04471   *         @arg @ref LL_HRTIM_TIMER_B
04472   *         @arg @ref LL_HRTIM_TIMER_C
04473   *         @arg @ref LL_HRTIM_TIMER_D
04474   *         @arg @ref LL_HRTIM_TIMER_E
04475   * @retval IPPSTAT This parameter can be one of the following values:
04476   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
04477   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
04478   */
04479 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04480 {
04481   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04482   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
04483                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04484   return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
04485 }
04486
04487 /**
04488   * @brief  Set the event filter for a given timer.
04489   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventFilter\n
04490   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventFilter\n
04491   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventFilter\n
04492   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventFilter\n
04493   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventFilter\n
04494   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventFilter\n
04495   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventFilter\n
04496   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventFilter\n
04497   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventFilter\n
04498   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventFilter
04499   * @note This function must not be called when the timer counter is enabled.
04500   * @param  HRTIMx High Resolution Timer instance
04501   * @param  Timer This parameter can be one of the following values:
04502   *         @arg @ref LL_HRTIM_TIMER_A
04503   *         @arg @ref LL_HRTIM_TIMER_B
04504   *         @arg @ref LL_HRTIM_TIMER_C
04505   *         @arg @ref LL_HRTIM_TIMER_D
04506   *         @arg @ref LL_HRTIM_TIMER_E
04507   * @param  Event This parameter can be one of the following values:
04508   *         @arg @ref LL_HRTIM_EVENT_1
04509   *         @arg @ref LL_HRTIM_EVENT_2
04510   *         @arg @ref LL_HRTIM_EVENT_3
04511   *         @arg @ref LL_HRTIM_EVENT_4
04512   *         @arg @ref LL_HRTIM_EVENT_5
04513   *         @arg @ref LL_HRTIM_EVENT_6
04514   *         @arg @ref LL_HRTIM_EVENT_7
04515   *         @arg @ref LL_HRTIM_EVENT_8
04516   *         @arg @ref LL_HRTIM_EVENT_9
04517   *         @arg @ref LL_HRTIM_EVENT_10
04518   * @param  Filter This parameter can be one of the following values:
04519   *         @arg @ref LL_HRTIM_EEFLTR_NONE
04520   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
04521   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
04522   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
04523   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
04524   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
04525   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
04526   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
04527   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
04528   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
04529   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
04530   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
04531   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
04532   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
04533   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
04534   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
04535
04536   * @retval None
04537   */
04538 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
04539 {
04540   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04541   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04542   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04543                                                               REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04544   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
04545 }
04546
04547 /**
04548   * @brief  Get actual event filter settings for a given timer.
04549   * @rmtoll EEFxR1      EE1FLTR        LL_HRTIM_TIM_GetEventFilter\n
04550   *         EEFxR1      EE2FLTR        LL_HRTIM_TIM_GetEventFilter\n
04551   *         EEFxR1      EE3FLTR        LL_HRTIM_TIM_GetEventFilter\n
04552   *         EEFxR1      EE4FLTR        LL_HRTIM_TIM_GetEventFilter\n
04553   *         EEFxR1      EE5FLTR        LL_HRTIM_TIM_GetEventFilter\n
04554   *         EEFxR2      EE6FLTR        LL_HRTIM_TIM_GetEventFilter\n
04555   *         EEFxR2      EE7FLTR        LL_HRTIM_TIM_GetEventFilter\n
04556   *         EEFxR2      EE8FLTR        LL_HRTIM_TIM_GetEventFilter\n
04557   *         EEFxR2      EE9FLTR        LL_HRTIM_TIM_GetEventFilter\n
04558   *         EEFxR2      EE10FLTR       LL_HRTIM_TIM_GetEventFilter
04559   * @param  HRTIMx High Resolution Timer instance
04560   * @param  Timer This parameter can be one of the following values:
04561   *         @arg @ref LL_HRTIM_TIMER_A
04562   *         @arg @ref LL_HRTIM_TIMER_B
04563   *         @arg @ref LL_HRTIM_TIMER_C
04564   *         @arg @ref LL_HRTIM_TIMER_D
04565   *         @arg @ref LL_HRTIM_TIMER_E
04566   * @param  Event This parameter can be one of the following values:
04567   *         @arg @ref LL_HRTIM_EVENT_1
04568   *         @arg @ref LL_HRTIM_EVENT_2
04569   *         @arg @ref LL_HRTIM_EVENT_3
04570   *         @arg @ref LL_HRTIM_EVENT_4
04571   *         @arg @ref LL_HRTIM_EVENT_5
04572   *         @arg @ref LL_HRTIM_EVENT_6
04573   *         @arg @ref LL_HRTIM_EVENT_7
04574   *         @arg @ref LL_HRTIM_EVENT_8
04575   *         @arg @ref LL_HRTIM_EVENT_9
04576   *         @arg @ref LL_HRTIM_EVENT_10
04577   * @retval Filter This parameter can be one of the following values:
04578   *         @arg @ref LL_HRTIM_EEFLTR_NONE
04579   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
04580   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
04581   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
04582   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
04583   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
04584   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
04585   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
04586   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
04587   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
04588   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
04589   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
04590   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
04591   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
04592   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
04593   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
04594   */
04595 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
04596 {
04597   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04598   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04599   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04600                                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04601   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
04602 }
04603
04604 /**
04605   * @brief  Enable or disable event latch mechanism for a given timer.
04606   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04607   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04608   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04609   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04610   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04611   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04612   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04613   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04614   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
04615   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventLatchStatus
04616   * @note This function must not be called when the timer counter is enabled.
04617   * @param  HRTIMx High Resolution Timer instance
04618   * @param  Timer This parameter can be one of the following values:
04619   *         @arg @ref LL_HRTIM_TIMER_A
04620   *         @arg @ref LL_HRTIM_TIMER_B
04621   *         @arg @ref LL_HRTIM_TIMER_C
04622   *         @arg @ref LL_HRTIM_TIMER_D
04623   *         @arg @ref LL_HRTIM_TIMER_E
04624   * @param  Event This parameter can be one of the following values:
04625   *         @arg @ref LL_HRTIM_EVENT_1
04626   *         @arg @ref LL_HRTIM_EVENT_2
04627   *         @arg @ref LL_HRTIM_EVENT_3
04628   *         @arg @ref LL_HRTIM_EVENT_4
04629   *         @arg @ref LL_HRTIM_EVENT_5
04630   *         @arg @ref LL_HRTIM_EVENT_6
04631   *         @arg @ref LL_HRTIM_EVENT_7
04632   *         @arg @ref LL_HRTIM_EVENT_8
04633   *         @arg @ref LL_HRTIM_EVENT_9
04634   *         @arg @ref LL_HRTIM_EVENT_10
04635   * @param  LatchStatus This parameter can be one of the following values:
04636   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
04637   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
04638   * @retval None
04639   */
04640 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
04641                                                       uint32_t LatchStatus)
04642 {
04643   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04644   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04645   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04646                                                               REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04647   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
04648 }
04649
04650 /**
04651   * @brief  Get actual event latch status for a given timer.
04652   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04653   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04654   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04655   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04656   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04657   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04658   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04659   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04660   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
04661   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_GetEventLatchStatus
04662   * @param  HRTIMx High Resolution Timer instance
04663   * @param  Timer This parameter can be one of the following values:
04664   *         @arg @ref LL_HRTIM_TIMER_A
04665   *         @arg @ref LL_HRTIM_TIMER_B
04666   *         @arg @ref LL_HRTIM_TIMER_C
04667   *         @arg @ref LL_HRTIM_TIMER_D
04668   *         @arg @ref LL_HRTIM_TIMER_E
04669   * @param  Event This parameter can be one of the following values:
04670   *         @arg @ref LL_HRTIM_EVENT_1
04671   *         @arg @ref LL_HRTIM_EVENT_2
04672   *         @arg @ref LL_HRTIM_EVENT_3
04673   *         @arg @ref LL_HRTIM_EVENT_4
04674   *         @arg @ref LL_HRTIM_EVENT_5
04675   *         @arg @ref LL_HRTIM_EVENT_6
04676   *         @arg @ref LL_HRTIM_EVENT_7
04677   *         @arg @ref LL_HRTIM_EVENT_8
04678   *         @arg @ref LL_HRTIM_EVENT_9
04679   *         @arg @ref LL_HRTIM_EVENT_10
04680   * @retval LatchStatus This parameter can be one of the following values:
04681   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
04682   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
04683   */
04684 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
04685 {
04686   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
04687   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
04688   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
04689                                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
04690   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
04691 }
04692
04693 /**
04694   * @}
04695   */
04696
04697 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
04698   * @{
04699   */
04700
04701 /**
04702   * @brief  Configure the dead time insertion feature for a given timer.
04703   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_Config\n
04704   *         DTxR      SDTF       LL_HRTIM_DT_Config\n
04705   *         DTxR      SDRT       LL_HRTIM_DT_Config
04706   * @param  HRTIMx High Resolution Timer instance
04707   * @param  Timer This parameter can be one of the following values:
04708   *         @arg @ref LL_HRTIM_TIMER_A
04709   *         @arg @ref LL_HRTIM_TIMER_B
04710   *         @arg @ref LL_HRTIM_TIMER_C
04711   *         @arg @ref LL_HRTIM_TIMER_D
04712   *         @arg @ref LL_HRTIM_TIMER_E
04713   * @param  Configuration This parameter must be a combination of all the following values:
04714   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
04715   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
04716   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
04717   * @retval None
04718   */
04719 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
04720 {
04721   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04722   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04723                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04724   MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
04725 }
04726
04727 /**
04728   * @brief  Set the deadtime prescaler value.
04729   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_SetPrescaler
04730   * @param  HRTIMx High Resolution Timer instance
04731   * @param  Timer This parameter can be one of the following values:
04732   *         @arg @ref LL_HRTIM_TIMER_A
04733   *         @arg @ref LL_HRTIM_TIMER_B
04734   *         @arg @ref LL_HRTIM_TIMER_C
04735   *         @arg @ref LL_HRTIM_TIMER_D
04736   *         @arg @ref LL_HRTIM_TIMER_E
04737   * @param  Prescaler This parameter can be one of the following values:
04738   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
04739   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
04740   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
04741   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
04742   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
04743   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
04744   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
04745   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
04746   * @retval None
04747   */
04748 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
04749 {
04750   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04751   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04752                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04753   MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
04754 }
04755
04756 /**
04757   * @brief  Get actual deadtime prescaler value.
04758   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_GetPrescaler
04759   * @param  HRTIMx High Resolution Timer instance
04760   * @param  Timer This parameter can be one of the following values:
04761   *         @arg @ref LL_HRTIM_TIMER_A
04762   *         @arg @ref LL_HRTIM_TIMER_B
04763   *         @arg @ref LL_HRTIM_TIMER_C
04764   *         @arg @ref LL_HRTIM_TIMER_D
04765   *         @arg @ref LL_HRTIM_TIMER_E
04766   * @retval Prescaler This parameter can be one of the following values:
04767   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
04768   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
04769   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
04770   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
04771   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
04772   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
04773   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
04774   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
04775   */
04776 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04777 {
04778   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04779   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04780                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04781   return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
04782 }
04783
04784 /**
04785   * @brief  Set the deadtime rising value.
04786   * @rmtoll DTxR      DTR       LL_HRTIM_DT_SetRisingValue
04787   * @param  HRTIMx High Resolution Timer instance
04788   * @param  Timer This parameter can be one of the following values:
04789   *         @arg @ref LL_HRTIM_TIMER_A
04790   *         @arg @ref LL_HRTIM_TIMER_B
04791   *         @arg @ref LL_HRTIM_TIMER_C
04792   *         @arg @ref LL_HRTIM_TIMER_D
04793   *         @arg @ref LL_HRTIM_TIMER_E
04794   * @param  RisingValue Value between 0 and 0x1FF
04795   * @retval None
04796   */
04797 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
04798 {
04799   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04800   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04801                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04802   MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
04803 }
04804
04805 /**
04806   * @brief  Get actual deadtime rising value.
04807   * @rmtoll DTxR      DTR       LL_HRTIM_DT_GetRisingValue
04808   * @param  HRTIMx High Resolution Timer instance
04809   * @param  Timer This parameter can be one of the following values:
04810   *         @arg @ref LL_HRTIM_TIMER_A
04811   *         @arg @ref LL_HRTIM_TIMER_B
04812   *         @arg @ref LL_HRTIM_TIMER_C
04813   *         @arg @ref LL_HRTIM_TIMER_D
04814   *         @arg @ref LL_HRTIM_TIMER_E
04815   * @retval RisingValue Value between 0 and 0x1FF
04816   */
04817 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04818 {
04819   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04820   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04821                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04822   return (READ_BIT(*pReg, HRTIM_DTR_DTR));
04823 }
04824
04825 /**
04826   * @brief  Set the deadtime sign on rising edge.
04827   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_SetRisingSign
04828   * @param  HRTIMx High Resolution Timer instance
04829   * @param  Timer This parameter can be one of the following values:
04830   *         @arg @ref LL_HRTIM_TIMER_A
04831   *         @arg @ref LL_HRTIM_TIMER_B
04832   *         @arg @ref LL_HRTIM_TIMER_C
04833   *         @arg @ref LL_HRTIM_TIMER_D
04834   *         @arg @ref LL_HRTIM_TIMER_E
04835   * @param  RisingSign This parameter can be one of the following values:
04836   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
04837   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
04838   * @retval None
04839   */
04840 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
04841 {
04842   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04843   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04844                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04845   MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
04846 }
04847
04848 /**
04849   * @brief  Get actual deadtime sign on rising edge.
04850   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_GetRisingSign
04851   * @param  HRTIMx High Resolution Timer instance
04852   * @param  Timer This parameter can be one of the following values:
04853   *         @arg @ref LL_HRTIM_TIMER_A
04854   *         @arg @ref LL_HRTIM_TIMER_B
04855   *         @arg @ref LL_HRTIM_TIMER_C
04856   *         @arg @ref LL_HRTIM_TIMER_D
04857   *         @arg @ref LL_HRTIM_TIMER_E
04858   * @retval RisingSign This parameter can be one of the following values:
04859   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
04860   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
04861   */
04862 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04863 {
04864   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04865   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04866                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04867   return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
04868 }
04869
04870 /**
04871   * @brief  Set the deadime falling value.
04872   * @rmtoll DTxR      DTF       LL_HRTIM_DT_SetFallingValue
04873   * @param  HRTIMx High Resolution Timer instance
04874   * @param  Timer This parameter can be one of the following values:
04875   *         @arg @ref LL_HRTIM_TIMER_A
04876   *         @arg @ref LL_HRTIM_TIMER_B
04877   *         @arg @ref LL_HRTIM_TIMER_C
04878   *         @arg @ref LL_HRTIM_TIMER_D
04879   *         @arg @ref LL_HRTIM_TIMER_E
04880   * @param  FallingValue Value between 0 and 0x1FF
04881   * @retval None
04882   */
04883 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
04884 {
04885   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04886   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04887                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04888   MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
04889 }
04890
04891 /**
04892   * @brief  Get actual deadtime falling value
04893   * @rmtoll DTxR      DTF       LL_HRTIM_DT_GetFallingValue
04894   * @param  HRTIMx High Resolution Timer instance
04895   * @param  Timer This parameter can be one of the following values:
04896   *         @arg @ref LL_HRTIM_TIMER_A
04897   *         @arg @ref LL_HRTIM_TIMER_B
04898   *         @arg @ref LL_HRTIM_TIMER_C
04899   *         @arg @ref LL_HRTIM_TIMER_D
04900   *         @arg @ref LL_HRTIM_TIMER_E
04901   * @retval FallingValue Value between 0 and 0x1FF
04902   */
04903 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04904 {
04905   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04906   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04907                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04908   return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
04909 }
04910
04911 /**
04912   * @brief  Set the deadtime sign on falling edge.
04913   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_SetFallingSign
04914   * @param  HRTIMx High Resolution Timer instance
04915   * @param  Timer This parameter can be one of the following values:
04916   *         @arg @ref LL_HRTIM_TIMER_A
04917   *         @arg @ref LL_HRTIM_TIMER_B
04918   *         @arg @ref LL_HRTIM_TIMER_C
04919   *         @arg @ref LL_HRTIM_TIMER_D
04920   *         @arg @ref LL_HRTIM_TIMER_E
04921   * @param  FallingSign This parameter can be one of the following values:
04922   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
04923   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
04924   * @retval None
04925   */
04926 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
04927 {
04928   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04929   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04930                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04931   MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
04932 }
04933
04934 /**
04935   * @brief  Get actual deadtime sign on falling edge.
04936   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_GetFallingSign
04937   * @param  HRTIMx High Resolution Timer instance
04938   * @param  Timer This parameter can be one of the following values:
04939   *         @arg @ref LL_HRTIM_TIMER_A
04940   *         @arg @ref LL_HRTIM_TIMER_B
04941   *         @arg @ref LL_HRTIM_TIMER_C
04942   *         @arg @ref LL_HRTIM_TIMER_D
04943   *         @arg @ref LL_HRTIM_TIMER_E
04944   * @retval FallingSign This parameter can be one of the following values:
04945   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
04946   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
04947   */
04948 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04949 {
04950   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04951   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04952                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04953   return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
04954 }
04955
04956 /**
04957   * @brief  Lock the deadtime value and sign on rising edge.
04958   * @rmtoll DTxR      DTRLK       LL_HRTIM_DT_LockRising
04959   * @param  HRTIMx High Resolution Timer instance
04960   * @param  Timer This parameter can be one of the following values:
04961   *         @arg @ref LL_HRTIM_TIMER_A
04962   *         @arg @ref LL_HRTIM_TIMER_B
04963   *         @arg @ref LL_HRTIM_TIMER_C
04964   *         @arg @ref LL_HRTIM_TIMER_D
04965   *         @arg @ref LL_HRTIM_TIMER_E
04966   * @retval None
04967   */
04968 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04969 {
04970   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04971   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04972                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04973   SET_BIT(*pReg, HRTIM_DTR_DTRLK);
04974 }
04975
04976 /**
04977   * @brief  Lock the deadtime sign on rising edge.
04978   * @rmtoll DTxR      DTRSLK       LL_HRTIM_DT_LockRisingSign
04979   * @param  HRTIMx High Resolution Timer instance
04980   * @param  Timer This parameter can be one of the following values:
04981   *         @arg @ref LL_HRTIM_TIMER_A
04982   *         @arg @ref LL_HRTIM_TIMER_B
04983   *         @arg @ref LL_HRTIM_TIMER_C
04984   *         @arg @ref LL_HRTIM_TIMER_D
04985   *         @arg @ref LL_HRTIM_TIMER_E
04986   * @retval None
04987   */
04988 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04989 {
04990   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04991   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
04992                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04993   SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
04994 }
04995
04996 /**
04997   * @brief  Lock the deadtime value and sign on falling edge.
04998   * @rmtoll DTxR      DTFLK       LL_HRTIM_DT_LockFalling
04999   * @param  HRTIMx High Resolution Timer instance
05000   * @param  Timer This parameter can be one of the following values:
05001   *         @arg @ref LL_HRTIM_TIMER_A
05002   *         @arg @ref LL_HRTIM_TIMER_B
05003   *         @arg @ref LL_HRTIM_TIMER_C
05004   *         @arg @ref LL_HRTIM_TIMER_D
05005   *         @arg @ref LL_HRTIM_TIMER_E
05006   * @retval None
05007   */
05008 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05009 {
05010   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05011   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05012                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05013   SET_BIT(*pReg, HRTIM_DTR_DTFLK);
05014 }
05015
05016 /**
05017   * @brief  Lock the deadtime sign on falling edge.
05018   * @rmtoll DTxR      DTFSLK       LL_HRTIM_DT_LockFallingSign
05019   * @param  HRTIMx High Resolution Timer instance
05020   * @param  Timer This parameter can be one of the following values:
05021   *         @arg @ref LL_HRTIM_TIMER_A
05022   *         @arg @ref LL_HRTIM_TIMER_B
05023   *         @arg @ref LL_HRTIM_TIMER_C
05024   *         @arg @ref LL_HRTIM_TIMER_D
05025   *         @arg @ref LL_HRTIM_TIMER_E
05026   * @retval None
05027   */
05028 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05029 {
05030   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05031   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
05032                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05033   SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
05034 }
05035
05036 /**
05037   * @}
05038   */
05039
05040 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
05041   * @{
05042   */
05043
05044 /**
05045   * @brief  Configure the chopper stage for a given timer.
05046   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_Config\n
05047   *         CHPxR      CARDTY       LL_HRTIM_CHP_Config\n
05048   *         CHPxR      STRTPW       LL_HRTIM_CHP_Config
05049   * @note This function must not be called if the chopper mode is already
05050   *       enabled for one of the timer outputs.
05051   * @param  HRTIMx High Resolution Timer instance
05052   * @param  Timer This parameter can be one of the following values:
05053   *         @arg @ref LL_HRTIM_TIMER_A
05054   *         @arg @ref LL_HRTIM_TIMER_B
05055   *         @arg @ref LL_HRTIM_TIMER_C
05056   *         @arg @ref LL_HRTIM_TIMER_D
05057   *         @arg @ref LL_HRTIM_TIMER_E
05058   * @param  Configuration This parameter must be a combination of all the following values:
05059   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
05060   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
05061   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
05062   * @retval None
05063   */
05064 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
05065 {
05066   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05067   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05068                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05069   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
05070 }
05071
05072 /**
05073   * @brief  Set prescaler determining the carrier frequency to be added on top
05074   *         of the timer output signals when chopper mode is enabled.
05075   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_SetPrescaler
05076   * @note This function must not be called if the chopper mode is already
05077   *       enabled for one of the timer outputs.
05078   * @param  HRTIMx High Resolution Timer instance
05079   * @param  Timer This parameter can be one of the following values:
05080   *         @arg @ref LL_HRTIM_TIMER_A
05081   *         @arg @ref LL_HRTIM_TIMER_B
05082   *         @arg @ref LL_HRTIM_TIMER_C
05083   *         @arg @ref LL_HRTIM_TIMER_D
05084   *         @arg @ref LL_HRTIM_TIMER_E
05085   * @param  Prescaler This parameter can be one of the following values:
05086   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
05087   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
05088   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
05089   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
05090   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
05091   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
05092   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
05093   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
05094   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
05095   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
05096   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
05097   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
05098   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
05099   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
05100   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
05101   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
05102   * @retval None
05103   */
05104 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
05105 {
05106   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05107   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05108                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05109   MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
05110 }
05111
05112 /**
05113   * @brief  Get actual chopper stage prescaler value.
05114   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_GetPrescaler
05115   * @param  HRTIMx High Resolution Timer instance
05116   * @param  Timer This parameter can be one of the following values:
05117   *         @arg @ref LL_HRTIM_TIMER_A
05118   *         @arg @ref LL_HRTIM_TIMER_B
05119   *         @arg @ref LL_HRTIM_TIMER_C
05120   *         @arg @ref LL_HRTIM_TIMER_D
05121   *         @arg @ref LL_HRTIM_TIMER_E
05122   * @retval Prescaler This parameter can be one of the following values:
05123   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
05124   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
05125   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
05126   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
05127   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
05128   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
05129   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
05130   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
05131   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
05132   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
05133   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
05134   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
05135   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
05136   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
05137   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
05138   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
05139   */
05140 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05141 {
05142   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05143   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05144                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05145   return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
05146 }
05147
05148 /**
05149   * @brief  Set the chopper duty cycle.
05150   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_SetDutyCycle
05151   * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
05152   * @note This function must not be called if the chopper mode is already
05153   *       enabled for one of the timer outputs.
05154   * @param  HRTIMx High Resolution Timer instance
05155   * @param  Timer This parameter can be one of the following values:
05156   *         @arg @ref LL_HRTIM_TIMER_A
05157   *         @arg @ref LL_HRTIM_TIMER_B
05158   *         @arg @ref LL_HRTIM_TIMER_C
05159   *         @arg @ref LL_HRTIM_TIMER_D
05160   *         @arg @ref LL_HRTIM_TIMER_E
05161   * @param  DutyCycle This parameter can be one of the following values:
05162   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
05163   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
05164   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
05165   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
05166   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
05167   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
05168   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
05169   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
05170   * @retval None
05171   */
05172 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
05173 {
05174   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05175   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05176                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05177   MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
05178 }
05179
05180 /**
05181   * @brief  Get actual chopper duty cycle.
05182   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_GetDutyCycle
05183   * @param  HRTIMx High Resolution Timer instance
05184   * @param  Timer This parameter can be one of the following values:
05185   *         @arg @ref LL_HRTIM_TIMER_A
05186   *         @arg @ref LL_HRTIM_TIMER_B
05187   *         @arg @ref LL_HRTIM_TIMER_C
05188   *         @arg @ref LL_HRTIM_TIMER_D
05189   *         @arg @ref LL_HRTIM_TIMER_E
05190   * @retval DutyCycle This parameter can be one of the following values:
05191   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
05192   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
05193   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
05194   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
05195   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
05196   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
05197   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
05198   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
05199   */
05200 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05201 {
05202   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05203   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05204                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05205   return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
05206 }
05207
05208 /**
05209   * @brief  Set the start pulse width.
05210   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_SetPulseWidth
05211   * @note This function must not be called if the chopper mode is already
05212   *       enabled for one of the timer outputs.
05213   * @param  HRTIMx High Resolution Timer instance
05214   * @param  Timer This parameter can be one of the following values:
05215   *         @arg @ref LL_HRTIM_TIMER_A
05216   *         @arg @ref LL_HRTIM_TIMER_B
05217   *         @arg @ref LL_HRTIM_TIMER_C
05218   *         @arg @ref LL_HRTIM_TIMER_D
05219   *         @arg @ref LL_HRTIM_TIMER_E
05220   * @param  PulseWidth This parameter can be one of the following values:
05221   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
05222   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
05223   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
05224   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
05225   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
05226   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
05227   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
05228   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
05229   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
05230   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
05231   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
05232   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
05233   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
05234   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
05235   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
05236   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
05237   * @retval None
05238   */
05239 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
05240 {
05241   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05242   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05243                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05244   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
05245 }
05246
05247 /**
05248   * @brief  Get actual start pulse width.
05249   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_GetPulseWidth
05250   * @param  HRTIMx High Resolution Timer instance
05251   * @param  Timer This parameter can be one of the following values:
05252   *         @arg @ref LL_HRTIM_TIMER_A
05253   *         @arg @ref LL_HRTIM_TIMER_B
05254   *         @arg @ref LL_HRTIM_TIMER_C
05255   *         @arg @ref LL_HRTIM_TIMER_D
05256   *         @arg @ref LL_HRTIM_TIMER_E
05257   * @retval PulseWidth This parameter can be one of the following values:
05258   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
05259   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
05260   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
05261   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
05262   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
05263   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
05264   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
05265   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
05266   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
05267   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
05268   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
05269   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
05270   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
05271   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
05272   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
05273   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
05274   */
05275 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05276 {
05277   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05278   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
05279                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05280   return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
05281 }
05282
05283 /**
05284   * @}
05285   */
05286
05287 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
05288   * @{
05289   */
05290
05291 /**
05292   * @brief  Set the timer output set source.
05293   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
05294   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
05295   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
05296   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
05297   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
05298   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
05299   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
05300   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
05301   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
05302   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
05303   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
05304   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
05305   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
05306   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
05307   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
05308   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
05309   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
05310   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
05311   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
05312   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
05313   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
05314   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
05315   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
05316   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
05317   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
05318   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
05319   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
05320   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
05321   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
05322   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
05323   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
05324   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc\n
05325   *         SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
05326   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
05327   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
05328   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
05329   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
05330   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
05331   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
05332   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
05333   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
05334   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
05335   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
05336   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
05337   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
05338   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
05339   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
05340   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
05341   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
05342   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
05343   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
05344   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
05345   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
05346   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
05347   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
05348   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
05349   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
05350   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
05351   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
05352   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
05353   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
05354   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
05355   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
05356   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc
05357   * @param  HRTIMx High Resolution Timer instance
05358   * @param  Output This parameter can be one of the following values:
05359   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05360   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05361   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05362   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05363   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05364   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05365   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05366   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05367   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05368   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05369   * @param SetSrc This parameter can be a combination of the following values:
05370   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05371   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05372   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05373   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05374   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05375   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05376   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05377   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05378   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05379   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05380   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05381   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05382   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05383   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05384   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05385   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05386   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05387   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05388   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05389   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05390   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05391   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05392   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05393   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05394   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05395   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05396   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05397   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05398   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05399   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05400   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05401   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05402   * @retval None
05403   */
05404 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
05405 {
05406   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05407   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
05408                                                               REG_OFFSET_TAB_SETxR[iOutput]));
05409   WRITE_REG(*pReg, SetSrc);
05410 }
05411
05412 /**
05413   * @brief  Get the timer output set source.
05414   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
05415   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
05416   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
05417   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
05418   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
05419   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
05420   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
05421   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
05422   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
05423   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
05424   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
05425   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
05426   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
05427   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
05428   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
05429   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
05430   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
05431   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
05432   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
05433   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
05434   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
05435   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
05436   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
05437   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
05438   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
05439   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
05440   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
05441   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
05442   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
05443   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
05444   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
05445   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc\n
05446   *         SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
05447   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
05448   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
05449   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
05450   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
05451   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
05452   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
05453   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
05454   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
05455   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
05456   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
05457   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
05458   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
05459   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
05460   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
05461   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
05462   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
05463   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
05464   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
05465   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
05466   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
05467   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
05468   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
05469   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
05470   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
05471   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
05472   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
05473   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
05474   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
05475   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
05476   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
05477   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc
05478   * @param  HRTIMx High Resolution Timer instance
05479   * @param  Output This parameter can be one of the following values:
05480   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05481   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05482   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05483   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05484   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05485   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05486   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05487   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05488   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05489   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05490   * @retval SetSrc This parameter can be a combination of the following values:
05491   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05492   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05493   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05494   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05495   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05496   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05497   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05498   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05499   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05500   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05501   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05502   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05503   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05504   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05505   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05506   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05507   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05508   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05509   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05510   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05511   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05512   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05513   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05514   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05515   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05516   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05517   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05518   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05519   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05520   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05521   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05522   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05523   */
05524 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05525 {
05526   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05527   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
05528                                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05529   return (uint32_t) READ_REG(*pReg);
05530 }
05531
05532 /**
05533   * @brief  Set the timer output reset source.
05534   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
05535   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
05536   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
05537   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
05538   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
05539   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
05540   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
05541   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
05542   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
05543   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
05544   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
05545   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
05546   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
05547   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
05548   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
05549   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
05550   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
05551   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
05552   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
05553   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
05554   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
05555   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
05556   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
05557   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
05558   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
05559   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
05560   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
05561   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
05562   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
05563   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
05564   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
05565   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc\n
05566   *         RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
05567   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
05568   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
05569   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
05570   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
05571   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
05572   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
05573   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
05574   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
05575   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
05576   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
05577   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
05578   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
05579   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
05580   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
05581   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
05582   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
05583   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
05584   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
05585   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
05586   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
05587   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
05588   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
05589   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
05590   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
05591   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
05592   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
05593   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
05594   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
05595   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
05596   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
05597   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc
05598   * @param  HRTIMx High Resolution Timer instance
05599   * @param  Output This parameter can be one of the following values:
05600   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05601   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05602   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05603   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05604   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05605   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05606   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05607   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05608   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05609   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05610   * @param ResetSrc This parameter can be a combination of the following values:
05611   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05612   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05613   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05614   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05615   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05616   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05617   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05618   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05619   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05620   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05621   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05622   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05623   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05624   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05625   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05626   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05627   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05628   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05629   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05630   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05631   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05632   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05633   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05634   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05635   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05636   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05637   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05638   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05639   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05640   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05641   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05642   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05643   * @retval None
05644   */
05645 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
05646 {
05647   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05648   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
05649                                                               REG_OFFSET_TAB_SETxR[iOutput]));
05650   WRITE_REG(*pReg, ResetSrc);
05651 }
05652
05653 /**
05654   * @brief  Get the timer output set source.
05655   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
05656   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
05657   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
05658   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
05659   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
05660   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
05661   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
05662   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
05663   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
05664   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
05665   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
05666   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
05667   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
05668   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
05669   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
05670   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
05671   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
05672   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
05673   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
05674   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
05675   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
05676   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
05677   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
05678   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
05679   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
05680   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
05681   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
05682   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
05683   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
05684   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
05685   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
05686   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc\n
05687   *         RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
05688   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
05689   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
05690   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
05691   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
05692   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
05693   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
05694   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
05695   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
05696   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
05697   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
05698   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
05699   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
05700   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
05701   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
05702   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
05703   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
05704   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
05705   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
05706   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
05707   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
05708   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
05709   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
05710   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
05711   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
05712   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
05713   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
05714   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
05715   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
05716   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
05717   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
05718   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc
05719   * @param  HRTIMx High Resolution Timer instance
05720   * @param  Output This parameter can be one of the following values:
05721   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05722   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05723   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05724   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05725   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05726   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05727   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05728   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05729   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05730   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05731   * @retval ResetSrc This parameter can be a combination of the following values:
05732   *         @arg @ref LL_HRTIM_CROSSBAR_NONE
05733   *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC
05734   *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER
05735   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
05736   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
05737   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
05738   *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
05739   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
05740   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
05741   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
05742   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
05743   *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
05744   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
05745   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
05746   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
05747   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
05748   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
05749   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
05750   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
05751   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
05752   *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
05753   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1
05754   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2
05755   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3
05756   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4
05757   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5
05758   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6
05759   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7
05760   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8
05761   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9
05762   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
05763   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
05764   */
05765 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05766 {
05767   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05768   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
05769                                                                     REG_OFFSET_TAB_SETxR[iOutput]));
05770   return (uint32_t) READ_REG(*pReg);
05771 }
05772
05773 /**
05774   * @brief  Configure a timer output.
05775   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_Config\n
05776   *         OUTxR      IDLEM1        LL_HRTIM_OUT_Config\n
05777   *         OUTxR      IDLES1        LL_HRTIM_OUT_Config\n
05778   *         OUTxR      FAULT1        LL_HRTIM_OUT_Config\n
05779   *         OUTxR      CHP1          LL_HRTIM_OUT_Config\n
05780   *         OUTxR      DIDL1         LL_HRTIM_OUT_Config\n
05781   *         OUTxR      POL2          LL_HRTIM_OUT_Config\n
05782   *         OUTxR      IDLEM2        LL_HRTIM_OUT_Config\n
05783   *         OUTxR      IDLES2        LL_HRTIM_OUT_Config\n
05784   *         OUTxR      FAULT2        LL_HRTIM_OUT_Config\n
05785   *         OUTxR      CHP2          LL_HRTIM_OUT_Config\n
05786   *         OUTxR      DIDL2         LL_HRTIM_OUT_Config
05787   * @param  HRTIMx High Resolution Timer instance
05788   * @param  Output This parameter can be one of the following values:
05789   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05790   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05791   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05792   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05793   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05794   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05795   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05796   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05797   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05798   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05799   * @param  Configuration This parameter must be a combination of all the following values:
05800   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05801   *         @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05802   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
05803   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
05804   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
05805   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
05806   * @retval None
05807   */
05808 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
05809 {
05810   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05811   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05812                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
05813   MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
05814              (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
05815 }
05816
05817 /**
05818   * @brief  Set the polarity of a timer output.
05819   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_SetPolarity\n
05820   *         OUTxR      POL2          LL_HRTIM_OUT_SetPolarity
05821   * @param  HRTIMx High Resolution Timer instance
05822   * @param  Output This parameter can be one of the following values:
05823   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05824   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05825   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05826   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05827   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05828   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05829   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05830   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05831   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05832   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05833   * @param  Polarity This parameter can be one of the following values:
05834   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
05835   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05836   * @retval None
05837   */
05838 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
05839 {
05840   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05841   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05842                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
05843   MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
05844 }
05845
05846 /**
05847   * @brief  Get actual polarity of the timer output.
05848   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_GetPolarity\n
05849   *         OUTxR      POL2          LL_HRTIM_OUT_GetPolarity
05850   * @param  HRTIMx High Resolution Timer instance
05851   * @param  Output This parameter can be one of the following values:
05852   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05853   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05854   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05855   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05856   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05857   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05858   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05859   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05860   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05861   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05862   * @retval Polarity This parameter can be one of the following values:
05863   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
05864   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
05865   */
05866 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05867 {
05868   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05869   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05870                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05871   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
05872 }
05873
05874 /**
05875   * @brief  Set the output IDLE mode.
05876   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_SetIdleMode\n
05877   *         OUTxR      IDLEM2          LL_HRTIM_OUT_SetIdleMode
05878   * @note This function must not be called when the burst mode is active
05879   * @param  HRTIMx High Resolution Timer instance
05880   * @param  Output This parameter can be one of the following values:
05881   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05882   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05883   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05884   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05885   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05886   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05887   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05888   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05889   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05890   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05891   * @param  IdleMode This parameter can be one of the following values:
05892   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
05893   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05894   * @retval None
05895   */
05896 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
05897 {
05898   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05899   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05900                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
05901   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
05902 }
05903
05904 /**
05905   * @brief  Get actual output IDLE mode.
05906   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_GetIdleMode\n
05907   *         OUTxR      IDLEM2          LL_HRTIM_OUT_GetIdleMode
05908   * @param  HRTIMx High Resolution Timer instance
05909   * @param  Output This parameter can be one of the following values:
05910   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05911   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05912   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05913   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05914   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05915   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05916   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05917   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05918   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05919   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05920   * @retval IdleMode This parameter can be one of the following values:
05921   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
05922   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
05923   */
05924 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05925 {
05926   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05927   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05928                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05929   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
05930 }
05931
05932 /**
05933   * @brief  Set the output IDLE level.
05934   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_SetIdleLevel\n
05935   *         OUTxR      IDLES2          LL_HRTIM_OUT_SetIdleLevel
05936   * @note This function must be called prior enabling the timer.
05937   * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
05938   * @param  HRTIMx High Resolution Timer instance
05939   * @param  Output This parameter can be one of the following values:
05940   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05941   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05942   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05943   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05944   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05945   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05946   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05947   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05948   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05949   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05950   * @param  IdleLevel This parameter can be one of the following values:
05951   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
05952   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
05953   * @retval None
05954   */
05955 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
05956 {
05957   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05958   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05959                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
05960   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
05961 }
05962
05963 /**
05964   * @brief  Get actual output IDLE level.
05965   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_GetIdleLevel\n
05966   *         OUTxR      IDLES2          LL_HRTIM_OUT_GetIdleLevel
05967   * @param  HRTIMx High Resolution Timer instance
05968   * @param  Output This parameter can be one of the following values:
05969   *         @arg @ref LL_HRTIM_OUTPUT_TA1
05970   *         @arg @ref LL_HRTIM_OUTPUT_TA2
05971   *         @arg @ref LL_HRTIM_OUTPUT_TB1
05972   *         @arg @ref LL_HRTIM_OUTPUT_TB2
05973   *         @arg @ref LL_HRTIM_OUTPUT_TC1
05974   *         @arg @ref LL_HRTIM_OUTPUT_TC2
05975   *         @arg @ref LL_HRTIM_OUTPUT_TD1
05976   *         @arg @ref LL_HRTIM_OUTPUT_TD2
05977   *         @arg @ref LL_HRTIM_OUTPUT_TE1
05978   *         @arg @ref LL_HRTIM_OUTPUT_TE2
05979   * @retval IdleLevel This parameter can be one of the following values:
05980   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
05981   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
05982   */
05983 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
05984 {
05985   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
05986   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05987                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
05988   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
05989 }
05990
05991 /**
05992   * @brief  Set the output FAULT state.
05993   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_SetFaultState\n
05994   *         OUTxR      FAULT2          LL_HRTIM_OUT_SetFaultState
05995   * @note This function must not called when the timer is enabled and a fault
05996   *       channel is enabled at timer level.
05997   * @param  HRTIMx High Resolution Timer instance
05998   * @param  Output This parameter can be one of the following values:
05999   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06000   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06001   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06002   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06003   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06004   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06005   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06006   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06007   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06008   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06009   * @param  FaultState This parameter can be one of the following values:
06010   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
06011   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
06012   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
06013   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
06014   * @retval None
06015   */
06016 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
06017 {
06018   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06019   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06020                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
06021   MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
06022 }
06023
06024 /**
06025   * @brief  Get actual FAULT state.
06026   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_GetFaultState\n
06027   *         OUTxR      FAULT2          LL_HRTIM_OUT_GetFaultState
06028   * @param  HRTIMx High Resolution Timer instance
06029   * @param  Output This parameter can be one of the following values:
06030   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06031   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06032   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06033   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06034   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06035   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06036   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06037   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06038   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06039   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06040   * @retval FaultState This parameter can be one of the following values:
06041   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
06042   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
06043   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
06044   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
06045   */
06046 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06047 {
06048   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06049   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06050                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06051   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06052 }
06053
06054 /**
06055   * @brief  Set the output chopper mode.
06056   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_SetChopperMode\n
06057   *         OUTxR      CHP2          LL_HRTIM_OUT_SetChopperMode
06058   * @note This function must not called when the timer is enabled.
06059   * @param  HRTIMx High Resolution Timer instance
06060   * @param  Output This parameter can be one of the following values:
06061   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06062   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06063   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06064   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06065   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06066   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06067   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06068   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06069   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06070   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06071   * @param  ChopperMode This parameter can be one of the following values:
06072   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
06073   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
06074   * @retval None
06075   */
06076 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
06077 {
06078   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06079   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06080                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
06081   MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
06082 }
06083
06084 /**
06085   * @brief  Get actual output chopper mode
06086   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_GetChopperMode\n
06087   *         OUTxR      CHP2          LL_HRTIM_OUT_GetChopperMode
06088   * @param  HRTIMx High Resolution Timer instance
06089   * @param  Output This parameter can be one of the following values:
06090   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06091   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06092   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06093   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06094   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06095   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06096   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06097   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06098   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06099   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06100   * @retval ChopperMode This parameter can be one of the following values:
06101   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
06102   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
06103   */
06104 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06105 {
06106   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06107   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06108                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06109   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06110 }
06111
06112 /**
06113   * @brief  Set the output burst mode entry mode.
06114   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_SetBMEntryMode\n
06115   *         OUTxR      DIDL2          LL_HRTIM_OUT_SetBMEntryMode
06116   * @note This function must not called when the timer is enabled.
06117   * @param  HRTIMx High Resolution Timer instance
06118   * @param  Output This parameter can be one of the following values:
06119   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06120   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06121   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06122   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06123   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06124   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06125   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06126   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06127   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06128   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06129   * @param  BMEntryMode This parameter can be one of the following values:
06130   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
06131   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
06132   * @retval None
06133   */
06134 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
06135 {
06136   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06137   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06138                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
06139   MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
06140 }
06141
06142 /**
06143   * @brief  Get actual output burst mode entry mode.
06144   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_GetBMEntryMode\n
06145   *         OUTxR      DIDL2          LL_HRTIM_OUT_GetBMEntryMode
06146   * @param  HRTIMx High Resolution Timer instance
06147   * @param  Output This parameter can be one of the following values:
06148   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06149   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06150   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06151   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06152   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06153   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06154   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06155   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06156   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06157   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06158   * @retval BMEntryMode This parameter can be one of the following values:
06159   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
06160   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
06161   */
06162 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06163 {
06164   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06165   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
06166                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06167   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
06168 }
06169
06170 /**
06171   * @brief  Get the level (active or inactive) of the designated output when the
06172   *         delayed protection was triggered.
06173   * @rmtoll TIMxISR      O1SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus\n
06174   *         TIMxISR      O2SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus
06175   * @param  HRTIMx High Resolution Timer instance
06176   * @param  Output This parameter can be one of the following values:
06177   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06178   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06179   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06180   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06181   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06182   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06183   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06184   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06185   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06186   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06187   * @retval OutputLevel This parameter can be one of the following values:
06188   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06189   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06190   */
06191 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06192 {
06193   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06194   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
06195                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06196   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
06197           HRTIM_TIMISR_O1STAT_Pos);
06198 }
06199
06200 /**
06201   * @brief  Force the timer output to its active or inactive level.
06202   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_ForceLevel\n
06203   *         RSTx1R      SRT          LL_HRTIM_OUT_ForceLevel\n
06204   *         SETx2R      SST          LL_HRTIM_OUT_ForceLevel\n
06205   *         RSTx2R      SRT          LL_HRTIM_OUT_ForceLevel
06206   * @param  HRTIMx High Resolution Timer instance
06207   * @param  Output This parameter can be one of the following values:
06208   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06209   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06210   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06211   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06212   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06213   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06214   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06215   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06216   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06217   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06218   * @param  OutputLevel This parameter can be one of the following values:
06219   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06220   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06221   * @retval None
06222   */
06223 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
06224 {
06225   const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
06226   {
06227     0x04U,   /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE  */
06228     0x00U    /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE  */
06229   };
06230
06231   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06232   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
06233                                                               REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
06234   SET_BIT(*pReg, HRTIM_SET1R_SST);
06235 }
06236
06237 /**
06238   * @brief  Get actual output level, before the output stage (chopper, polarity).
06239   * @rmtoll TIMxISR     O1CPY          LL_HRTIM_OUT_GetLevel\n
06240   *         TIMxISR     O2CPY          LL_HRTIM_OUT_GetLevel
06241   * @param  HRTIMx High Resolution Timer instance
06242   * @param  Output This parameter can be one of the following values:
06243   *         @arg @ref LL_HRTIM_OUTPUT_TA1
06244   *         @arg @ref LL_HRTIM_OUTPUT_TA2
06245   *         @arg @ref LL_HRTIM_OUTPUT_TB1
06246   *         @arg @ref LL_HRTIM_OUTPUT_TB2
06247   *         @arg @ref LL_HRTIM_OUTPUT_TC1
06248   *         @arg @ref LL_HRTIM_OUTPUT_TC2
06249   *         @arg @ref LL_HRTIM_OUTPUT_TD1
06250   *         @arg @ref LL_HRTIM_OUTPUT_TD2
06251   *         @arg @ref LL_HRTIM_OUTPUT_TE1
06252   *         @arg @ref LL_HRTIM_OUTPUT_TE2
06253   * @retval OutputLevel This parameter can be one of the following values:
06254   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
06255   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
06256   */
06257 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
06258 {
06259   register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
06260   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
06261                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
06262   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
06263           HRTIM_TIMISR_O1CPY_Pos);
06264 }
06265
06266 /**
06267   * @}
06268   */
06269
06270 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
06271   * @{
06272   */
06273
06274 /**
06275   * @brief  Configure external event conditioning.
06276   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_Config\n
06277   *         EECR1     EE1POL          LL_HRTIM_EE_Config\n
06278   *         EECR1     EE1SNS          LL_HRTIM_EE_Config\n
06279   *         EECR1     EE1FAST         LL_HRTIM_EE_Config\n
06280   *         EECR1     EE2SRC          LL_HRTIM_EE_Config\n
06281   *         EECR1     EE2POL          LL_HRTIM_EE_Config\n
06282   *         EECR1     EE2SNS          LL_HRTIM_EE_Config\n
06283   *         EECR1     EE2FAST         LL_HRTIM_EE_Config\n
06284   *         EECR1     EE3SRC          LL_HRTIM_EE_Config\n
06285   *         EECR1     EE3POL          LL_HRTIM_EE_Config\n
06286   *         EECR1     EE3SNS          LL_HRTIM_EE_Config\n
06287   *         EECR1     EE3FAST         LL_HRTIM_EE_Config\n
06288   *         EECR1     EE4SRC          LL_HRTIM_EE_Config\n
06289   *         EECR1     EE4POL          LL_HRTIM_EE_Config\n
06290   *         EECR1     EE4SNS          LL_HRTIM_EE_Config\n
06291   *         EECR1     EE4FAST         LL_HRTIM_EE_Config\n
06292   *         EECR1     EE5SRC          LL_HRTIM_EE_Config\n
06293   *         EECR1     EE5POL          LL_HRTIM_EE_Config\n
06294   *         EECR1     EE5SNS          LL_HRTIM_EE_Config\n
06295   *         EECR1     EE5FAST         LL_HRTIM_EE_Config\n
06296   *         EECR2     EE6SRC          LL_HRTIM_EE_Config\n
06297   *         EECR2     EE6POL          LL_HRTIM_EE_Config\n
06298   *         EECR2     EE6SNS          LL_HRTIM_EE_Config\n
06299   *         EECR2     EE6FAST         LL_HRTIM_EE_Config\n
06300   *         EECR2     EE7SRC          LL_HRTIM_EE_Config\n
06301   *         EECR2     EE7POL          LL_HRTIM_EE_Config\n
06302   *         EECR2     EE7SNS          LL_HRTIM_EE_Config\n
06303   *         EECR2     EE7FAST         LL_HRTIM_EE_Config\n
06304   *         EECR2     EE8SRC          LL_HRTIM_EE_Config\n
06305   *         EECR2     EE8POL          LL_HRTIM_EE_Config\n
06306   *         EECR2     EE8SNS          LL_HRTIM_EE_Config\n
06307   *         EECR2     EE8FAST         LL_HRTIM_EE_Config\n
06308   *         EECR2     EE9SRC          LL_HRTIM_EE_Config\n
06309   *         EECR2     EE9POL          LL_HRTIM_EE_Config\n
06310   *         EECR2     EE9SNS          LL_HRTIM_EE_Config\n
06311   *         EECR2     EE9FAST         LL_HRTIM_EE_Config\n
06312   *         EECR2     EE10SRC         LL_HRTIM_EE_Config\n
06313   *         EECR2     EE10POL         LL_HRTIM_EE_Config\n
06314   *         EECR2     EE10SNS         LL_HRTIM_EE_Config\n
06315   *         EECR2     EE10FAST        LL_HRTIM_EE_Config
06316   * @note This function must not be called when the timer counter is enabled.
06317   * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
06318   * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
06319   * @param  HRTIMx High Resolution Timer instance
06320   * @param  Event This parameter can be one of the following values:
06321   *         @arg @ref LL_HRTIM_EVENT_1
06322   *         @arg @ref LL_HRTIM_EVENT_2
06323   *         @arg @ref LL_HRTIM_EVENT_3
06324   *         @arg @ref LL_HRTIM_EVENT_4
06325   *         @arg @ref LL_HRTIM_EVENT_5
06326   *         @arg @ref LL_HRTIM_EVENT_6
06327   *         @arg @ref LL_HRTIM_EVENT_7
06328   *         @arg @ref LL_HRTIM_EVENT_8
06329   *         @arg @ref LL_HRTIM_EVENT_9
06330   *         @arg @ref LL_HRTIM_EVENT_10
06331   * @param  Configuration This parameter must be a combination of all the following values:
06332   *         @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
06333   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
06334   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06335   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
06336   * @retval None
06337   */
06338 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
06339 {
06340   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06341   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06342                                                               REG_OFFSET_TAB_EECR[iEvent]));
06343   MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
06344              (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
06345 }
06346
06347 /**
06348   * @brief  Set the external event source.
06349   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_SetSrc\n
06350   *         EECR1     EE2SRC          LL_HRTIM_EE_SetSrc\n
06351   *         EECR1     EE3SRC          LL_HRTIM_EE_SetSrc\n
06352   *         EECR1     EE4SRC          LL_HRTIM_EE_SetSrc\n
06353   *         EECR1     EE5SRC          LL_HRTIM_EE_SetSrc\n
06354   *         EECR2     EE6SRC          LL_HRTIM_EE_SetSrc\n
06355   *         EECR2     EE7SRC          LL_HRTIM_EE_SetSrc\n
06356   *         EECR2     EE8SRC          LL_HRTIM_EE_SetSrc\n
06357   *         EECR2     EE9SRC          LL_HRTIM_EE_SetSrc\n
06358   *         EECR2     EE10SRC         LL_HRTIM_EE_SetSrc
06359   * @param  HRTIMx High Resolution Timer instance
06360   * @param  Event This parameter can be one of the following values:
06361   *         @arg @ref LL_HRTIM_EVENT_1
06362   *         @arg @ref LL_HRTIM_EVENT_2
06363   *         @arg @ref LL_HRTIM_EVENT_3
06364   *         @arg @ref LL_HRTIM_EVENT_4
06365   *         @arg @ref LL_HRTIM_EVENT_5
06366   *         @arg @ref LL_HRTIM_EVENT_6
06367   *         @arg @ref LL_HRTIM_EVENT_7
06368   *         @arg @ref LL_HRTIM_EVENT_8
06369   *         @arg @ref LL_HRTIM_EVENT_9
06370   *         @arg @ref LL_HRTIM_EVENT_10
06371   * @param  Src This parameter can be one of the following values:
06372   *         @arg External event source 1
06373   *         @arg External event source 2
06374   *         @arg External event source 3
06375   *         @arg External event source 4
06376   * @retval None
06377   */
06378 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
06379 {
06380   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06381   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06382                                                               REG_OFFSET_TAB_EECR[iEvent]));
06383   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
06384 }
06385
06386 /**
06387   * @brief  Get actual external event source.
06388   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_GetSrc\n
06389   *         EECR1     EE2SRC          LL_HRTIM_EE_GetSrc\n
06390   *         EECR1     EE3SRC          LL_HRTIM_EE_GetSrc\n
06391   *         EECR1     EE4SRC          LL_HRTIM_EE_GetSrc\n
06392   *         EECR1     EE5SRC          LL_HRTIM_EE_GetSrc\n
06393   *         EECR2     EE6SRC          LL_HRTIM_EE_GetSrc\n
06394   *         EECR2     EE7SRC          LL_HRTIM_EE_GetSrc\n
06395   *         EECR2     EE8SRC          LL_HRTIM_EE_GetSrc\n
06396   *         EECR2     EE9SRC          LL_HRTIM_EE_GetSrc\n
06397   *         EECR2     EE10SRC         LL_HRTIM_EE_GetSrc
06398   * @param  HRTIMx High Resolution Timer instance
06399   * @param  Event This parameter can be one of the following values:
06400   *         @arg @ref LL_HRTIM_EVENT_1
06401   *         @arg @ref LL_HRTIM_EVENT_2
06402   *         @arg @ref LL_HRTIM_EVENT_3
06403   *         @arg @ref LL_HRTIM_EVENT_4
06404   *         @arg @ref LL_HRTIM_EVENT_5
06405   *         @arg @ref LL_HRTIM_EVENT_6
06406   *         @arg @ref LL_HRTIM_EVENT_7
06407   *         @arg @ref LL_HRTIM_EVENT_8
06408   *         @arg @ref LL_HRTIM_EVENT_9
06409   *         @arg @ref LL_HRTIM_EVENT_10
06410   * @retval EventSrc This parameter can be one of the following values:
06411   *         @arg External event source 1
06412   *         @arg External event source 2
06413   *         @arg External event source 3
06414   *         @arg External event source 4
06415   */
06416 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06417 {
06418   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06419   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06420                                                                     REG_OFFSET_TAB_EECR[iEvent]));
06421   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06422 }
06423
06424 /**
06425   * @brief  Set the polarity of an external event.
06426   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_SetPolarity\n
06427   *         EECR1     EE2POL          LL_HRTIM_EE_SetPolarity\n
06428   *         EECR1     EE3POL          LL_HRTIM_EE_SetPolarity\n
06429   *         EECR1     EE4POL          LL_HRTIM_EE_SetPolarity\n
06430   *         EECR1     EE5POL          LL_HRTIM_EE_SetPolarity\n
06431   *         EECR2     EE6POL          LL_HRTIM_EE_SetPolarity\n
06432   *         EECR2     EE7POL          LL_HRTIM_EE_SetPolarity\n
06433   *         EECR2     EE8POL          LL_HRTIM_EE_SetPolarity\n
06434   *         EECR2     EE9POL          LL_HRTIM_EE_SetPolarity\n
06435   *         EECR2     EE10POL         LL_HRTIM_EE_SetPolarity
06436   * @note This function must not be called when the timer counter is enabled.
06437   * @note Event polarity is only significant when event detection is level-sensitive.
06438   * @param  HRTIMx High Resolution Timer instance
06439   * @param  Event This parameter can be one of the following values:
06440   *         @arg @ref LL_HRTIM_EVENT_1
06441   *         @arg @ref LL_HRTIM_EVENT_2
06442   *         @arg @ref LL_HRTIM_EVENT_3
06443   *         @arg @ref LL_HRTIM_EVENT_4
06444   *         @arg @ref LL_HRTIM_EVENT_5
06445   *         @arg @ref LL_HRTIM_EVENT_6
06446   *         @arg @ref LL_HRTIM_EVENT_7
06447   *         @arg @ref LL_HRTIM_EVENT_8
06448   *         @arg @ref LL_HRTIM_EVENT_9
06449   *         @arg @ref LL_HRTIM_EVENT_10
06450   * @param  Polarity This parameter can be one of the following values:
06451   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
06452   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
06453   * @retval None
06454   */
06455 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
06456 {
06457   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06458   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06459                                                               REG_OFFSET_TAB_EECR[iEvent]));
06460   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
06461 }
06462
06463 /**
06464   * @brief  Get actual polarity setting of an external event.
06465   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_GetPolarity\n
06466   *         EECR1     EE2POL          LL_HRTIM_EE_GetPolarity\n
06467   *         EECR1     EE3POL          LL_HRTIM_EE_GetPolarity\n
06468   *         EECR1     EE4POL          LL_HRTIM_EE_GetPolarity\n
06469   *         EECR1     EE5POL          LL_HRTIM_EE_GetPolarity\n
06470   *         EECR2     EE6POL          LL_HRTIM_EE_GetPolarity\n
06471   *         EECR2     EE7POL          LL_HRTIM_EE_GetPolarity\n
06472   *         EECR2     EE8POL          LL_HRTIM_EE_GetPolarity\n
06473   *         EECR2     EE9POL          LL_HRTIM_EE_GetPolarity\n
06474   *         EECR2     EE10POL         LL_HRTIM_EE_GetPolarity
06475   * @param  HRTIMx High Resolution Timer instance
06476   * @param  Event This parameter can be one of the following values:
06477   *         @arg @ref LL_HRTIM_EVENT_1
06478   *         @arg @ref LL_HRTIM_EVENT_2
06479   *         @arg @ref LL_HRTIM_EVENT_3
06480   *         @arg @ref LL_HRTIM_EVENT_4
06481   *         @arg @ref LL_HRTIM_EVENT_5
06482   *         @arg @ref LL_HRTIM_EVENT_6
06483   *         @arg @ref LL_HRTIM_EVENT_7
06484   *         @arg @ref LL_HRTIM_EVENT_8
06485   *         @arg @ref LL_HRTIM_EVENT_9
06486   *         @arg @ref LL_HRTIM_EVENT_10
06487   * @retval Polarity This parameter can be one of the following values:
06488   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
06489   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
06490   */
06491 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06492 {
06493   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06494   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06495                                                                     REG_OFFSET_TAB_EECR[iEvent]));
06496   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06497 }
06498
06499 /**
06500   * @brief  Set the sensitivity of an external event.
06501   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_SetSensitivity\n
06502   *         EECR1     EE2SNS          LL_HRTIM_EE_SetSensitivity\n
06503   *         EECR1     EE3SNS          LL_HRTIM_EE_SetSensitivity\n
06504   *         EECR1     EE4SNS          LL_HRTIM_EE_SetSensitivity\n
06505   *         EECR1     EE5SNS          LL_HRTIM_EE_SetSensitivity\n
06506   *         EECR2     EE6SNS          LL_HRTIM_EE_SetSensitivity\n
06507   *         EECR2     EE7SNS          LL_HRTIM_EE_SetSensitivity\n
06508   *         EECR2     EE8SNS          LL_HRTIM_EE_SetSensitivity\n
06509   *         EECR2     EE9SNS          LL_HRTIM_EE_SetSensitivity\n
06510   *         EECR2     EE10SNS         LL_HRTIM_EE_SetSensitivity
06511   * @param  HRTIMx High Resolution Timer instance
06512   * @param  Event This parameter can be one of the following values:
06513   *         @arg @ref LL_HRTIM_EVENT_1
06514   *         @arg @ref LL_HRTIM_EVENT_2
06515   *         @arg @ref LL_HRTIM_EVENT_3
06516   *         @arg @ref LL_HRTIM_EVENT_4
06517   *         @arg @ref LL_HRTIM_EVENT_5
06518   *         @arg @ref LL_HRTIM_EVENT_6
06519   *         @arg @ref LL_HRTIM_EVENT_7
06520   *         @arg @ref LL_HRTIM_EVENT_8
06521   *         @arg @ref LL_HRTIM_EVENT_9
06522   *         @arg @ref LL_HRTIM_EVENT_10
06523   * @param  Sensitivity This parameter can be one of the following values:
06524   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
06525   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
06526   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
06527   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06528   * @retval None
06529   */
06530
06531 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
06532 {
06533   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06534   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06535                                                               REG_OFFSET_TAB_EECR[iEvent]));
06536   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
06537 }
06538
06539 /**
06540   * @brief  Get actual sensitivity setting of an external event.
06541   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_GetSensitivity\n
06542   *         EECR1     EE2SNS          LL_HRTIM_EE_GetSensitivity\n
06543   *         EECR1     EE3SNS          LL_HRTIM_EE_GetSensitivity\n
06544   *         EECR1     EE4SNS          LL_HRTIM_EE_GetSensitivity\n
06545   *         EECR1     EE5SNS          LL_HRTIM_EE_GetSensitivity\n
06546   *         EECR2     EE6SNS          LL_HRTIM_EE_GetSensitivity\n
06547   *         EECR2     EE7SNS          LL_HRTIM_EE_GetSensitivity\n
06548   *         EECR2     EE8SNS          LL_HRTIM_EE_GetSensitivity\n
06549   *         EECR2     EE9SNS          LL_HRTIM_EE_GetSensitivity\n
06550   *         EECR2     EE10SNS         LL_HRTIM_EE_GetSensitivity
06551   * @param  HRTIMx High Resolution Timer instance
06552   * @param  Event This parameter can be one of the following values:
06553   *         @arg @ref LL_HRTIM_EVENT_1
06554   *         @arg @ref LL_HRTIM_EVENT_2
06555   *         @arg @ref LL_HRTIM_EVENT_3
06556   *         @arg @ref LL_HRTIM_EVENT_4
06557   *         @arg @ref LL_HRTIM_EVENT_5
06558   *         @arg @ref LL_HRTIM_EVENT_6
06559   *         @arg @ref LL_HRTIM_EVENT_7
06560   *         @arg @ref LL_HRTIM_EVENT_8
06561   *         @arg @ref LL_HRTIM_EVENT_9
06562   *         @arg @ref LL_HRTIM_EVENT_10
06563   * @retval Polarity This parameter can be one of the following values:
06564   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
06565   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
06566   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
06567   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
06568   */
06569 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06570 {
06571   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06572   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06573                                                                     REG_OFFSET_TAB_EECR[iEvent]));
06574   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06575 }
06576
06577 /**
06578   * @brief  Set the fast mode of an external event.
06579   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_SetFastMode\n
06580   *         EECR1     EE2FAST         LL_HRTIM_EE_SetFastMode\n
06581   *         EECR1     EE3FAST         LL_HRTIM_EE_SetFastMode\n
06582   *         EECR1     EE4FAST         LL_HRTIM_EE_SetFastMode\n
06583   *         EECR1     EE5FAST         LL_HRTIM_EE_SetFastMode\n
06584   *         EECR2     EE6FAST         LL_HRTIM_EE_SetFastMode\n
06585   *         EECR2     EE7FAST         LL_HRTIM_EE_SetFastMode\n
06586   *         EECR2     EE8FAST         LL_HRTIM_EE_SetFastMode\n
06587   *         EECR2     EE9FAST         LL_HRTIM_EE_SetFastMode\n
06588   *         EECR2     EE10FAST        LL_HRTIM_EE_SetFastMode
06589   * @note This function must not be called when the timer counter is enabled.
06590   * @param  HRTIMx High Resolution Timer instance
06591   * @param  Event This parameter can be one of the following values:
06592   *         @arg @ref LL_HRTIM_EVENT_1
06593   *         @arg @ref LL_HRTIM_EVENT_2
06594   *         @arg @ref LL_HRTIM_EVENT_3
06595   *         @arg @ref LL_HRTIM_EVENT_4
06596   *         @arg @ref LL_HRTIM_EVENT_5
06597   * @param  FastMode This parameter can be one of the following values:
06598   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
06599   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
06600   * @retval None
06601   */
06602 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
06603 {
06604   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06605   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06606                                                               REG_OFFSET_TAB_EECR[iEvent]));
06607   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
06608 }
06609
06610 /**
06611   * @brief  Get actual fast mode setting of an external event.
06612   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_GetFastMode\n
06613   *         EECR1     EE2FAST         LL_HRTIM_EE_GetFastMode\n
06614   *         EECR1     EE3FAST         LL_HRTIM_EE_GetFastMode\n
06615   *         EECR1     EE4FAST         LL_HRTIM_EE_GetFastMode\n
06616   *         EECR1     EE5FAST         LL_HRTIM_EE_GetFastMode\n
06617   *         EECR2     EE6FAST         LL_HRTIM_EE_GetFastMode\n
06618   *         EECR2     EE7FAST         LL_HRTIM_EE_GetFastMode\n
06619   *         EECR2     EE8FAST         LL_HRTIM_EE_GetFastMode\n
06620   *         EECR2     EE9FAST         LL_HRTIM_EE_GetFastMode\n
06621   *         EECR2     EE10FAST        LL_HRTIM_EE_GetFastMode
06622   * @param  HRTIMx High Resolution Timer instance
06623   * @param  Event This parameter can be one of the following values:
06624   *         @arg @ref LL_HRTIM_EVENT_1
06625   *         @arg @ref LL_HRTIM_EVENT_2
06626   *         @arg @ref LL_HRTIM_EVENT_3
06627   *         @arg @ref LL_HRTIM_EVENT_4
06628   *         @arg @ref LL_HRTIM_EVENT_5
06629   * @retval FastMode This parameter can be one of the following values:
06630   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
06631   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
06632   */
06633 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06634 {
06635   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06636   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
06637                                                                     REG_OFFSET_TAB_EECR[iEvent]));
06638   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06639 }
06640
06641 /**
06642   * @brief  Set the digital noise filter of a external event.
06643   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_SetFilter\n
06644   *         EECR3     EE7F         LL_HRTIM_EE_SetFilter\n
06645   *         EECR3     EE8F         LL_HRTIM_EE_SetFilter\n
06646   *         EECR3     EE9F         LL_HRTIM_EE_SetFilter\n
06647   *         EECR3     EE10F        LL_HRTIM_EE_SetFilter
06648   * @param  HRTIMx High Resolution Timer instance
06649   * @param  Event This parameter can be one of the following values:
06650   *         @arg @ref LL_HRTIM_EVENT_6
06651   *         @arg @ref LL_HRTIM_EVENT_7
06652   *         @arg @ref LL_HRTIM_EVENT_8
06653   *         @arg @ref LL_HRTIM_EVENT_9
06654   *         @arg @ref LL_HRTIM_EVENT_10
06655   * @param  Filter This parameter can be one of the following values:
06656   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
06657   *         @arg @ref LL_HRTIM_EE_FILTER_1
06658   *         @arg @ref LL_HRTIM_EE_FILTER_2
06659   *         @arg @ref LL_HRTIM_EE_FILTER_3
06660   *         @arg @ref LL_HRTIM_EE_FILTER_4
06661   *         @arg @ref LL_HRTIM_EE_FILTER_5
06662   *         @arg @ref LL_HRTIM_EE_FILTER_6
06663   *         @arg @ref LL_HRTIM_EE_FILTER_7
06664   *         @arg @ref LL_HRTIM_EE_FILTER_8
06665   *         @arg @ref LL_HRTIM_EE_FILTER_9
06666   *         @arg @ref LL_HRTIM_EE_FILTER_10
06667   *         @arg @ref LL_HRTIM_EE_FILTER_11
06668   *         @arg @ref LL_HRTIM_EE_FILTER_12
06669   *         @arg @ref LL_HRTIM_EE_FILTER_13
06670   *         @arg @ref LL_HRTIM_EE_FILTER_14
06671   *         @arg @ref LL_HRTIM_EE_FILTER_15
06672   * @retval None
06673   */
06674 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
06675 {
06676   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06677   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
06678              (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
06679 }
06680
06681 /**
06682   * @brief  Get actual digital noise filter setting of a external event.
06683   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_GetFilter\n
06684   *         EECR3     EE7F         LL_HRTIM_EE_GetFilter\n
06685   *         EECR3     EE8F         LL_HRTIM_EE_GetFilter\n
06686   *         EECR3     EE9F         LL_HRTIM_EE_GetFilter\n
06687   *         EECR3     EE10F        LL_HRTIM_EE_GetFilter
06688   * @param  HRTIMx High Resolution Timer instance
06689   * @param  Event This parameter can be one of the following values:
06690   *         @arg @ref LL_HRTIM_EVENT_6
06691   *         @arg @ref LL_HRTIM_EVENT_7
06692   *         @arg @ref LL_HRTIM_EVENT_8
06693   *         @arg @ref LL_HRTIM_EVENT_9
06694   *         @arg @ref LL_HRTIM_EVENT_10
06695   * @retval Filter This parameter can be one of the following values:
06696   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
06697   *         @arg @ref LL_HRTIM_EE_FILTER_1
06698   *         @arg @ref LL_HRTIM_EE_FILTER_2
06699   *         @arg @ref LL_HRTIM_EE_FILTER_3
06700   *         @arg @ref LL_HRTIM_EE_FILTER_4
06701   *         @arg @ref LL_HRTIM_EE_FILTER_5
06702   *         @arg @ref LL_HRTIM_EE_FILTER_6
06703   *         @arg @ref LL_HRTIM_EE_FILTER_7
06704   *         @arg @ref LL_HRTIM_EE_FILTER_8
06705   *         @arg @ref LL_HRTIM_EE_FILTER_9
06706   *         @arg @ref LL_HRTIM_EE_FILTER_10
06707   *         @arg @ref LL_HRTIM_EE_FILTER_11
06708   *         @arg @ref LL_HRTIM_EE_FILTER_12
06709   *         @arg @ref LL_HRTIM_EE_FILTER_13
06710   *         @arg @ref LL_HRTIM_EE_FILTER_14
06711   *         @arg @ref LL_HRTIM_EE_FILTER_15
06712   */
06713 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
06714 {
06715   register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
06716   return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
06717                    (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
06718 }
06719
06720 /**
06721   * @brief  Set the external event prescaler.
06722   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_SetPrescaler
06723   * @param  HRTIMx High Resolution Timer instance
06724   * @param  Prescaler This parameter can be one of the following values:
06725   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
06726   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
06727   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
06728   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
06729   * @retval None
06730   */
06731
06732 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
06733 {
06734   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
06735 }
06736
06737 /**
06738   * @brief  Get actual external event prescaler setting.
06739   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_GetPrescaler
06740   * @param  HRTIMx High Resolution Timer instance
06741   * @retval Prescaler This parameter can be one of the following values:
06742   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
06743   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
06744   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
06745   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
06746   */
06747
06748 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
06749 {
06750   return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
06751 }
06752
06753 /**
06754   * @}
06755   */
06756
06757 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
06758   * @{
06759   */
06760 /**
06761   * @brief  Configure fault signal conditioning Polarity and Source.
06762   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_Config\n
06763   *         FLTINR1     FLT1SRC      LL_HRTIM_FLT_Config\n
06764   *         FLTINR1     FLT2P        LL_HRTIM_FLT_Config\n
06765   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_Config\n
06766   *         FLTINR1     FLT3P        LL_HRTIM_FLT_Config\n
06767   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_Config\n
06768   *         FLTINR1     FLT4P        LL_HRTIM_FLT_Config\n
06769   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_Config\n
06770   *         FLTINR2     FLT5P        LL_HRTIM_FLT_Config\n
06771   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_Config
06772   * @note This function must not be called when the fault channel is enabled.
06773   * @param  HRTIMx High Resolution Timer instance
06774   * @param  Fault This parameter can be one of the following values:
06775   *         @arg @ref LL_HRTIM_FAULT_1
06776   *         @arg @ref LL_HRTIM_FAULT_2
06777   *         @arg @ref LL_HRTIM_FAULT_3
06778   *         @arg @ref LL_HRTIM_FAULT_4
06779   *         @arg @ref LL_HRTIM_FAULT_5
06780   * @param  Configuration This parameter must be a combination of all the following values:
06781   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL
06782   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
06783   * @retval None
06784   */
06785 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
06786 {
06787   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06788   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06789                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06790   MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
06791              (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
06792 }
06793
06794 /**
06795   * @brief  Set the source of a fault signal.
06796   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_SetSrc\n
06797   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_SetSrc\n
06798   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_SetSrc\n
06799   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_SetSrc\n
06800   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_SetSrc
06801   * @note This function must not be called when the fault channel is enabled.
06802   * @param  HRTIMx High Resolution Timer instance
06803   * @param  Fault This parameter can be one of the following values:
06804   *         @arg @ref LL_HRTIM_FAULT_1
06805   *         @arg @ref LL_HRTIM_FAULT_2
06806   *         @arg @ref LL_HRTIM_FAULT_3
06807   *         @arg @ref LL_HRTIM_FAULT_4
06808   *         @arg @ref LL_HRTIM_FAULT_5
06809   * @param  Src This parameter can be one of the following values:
06810   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
06811   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
06812   * @retval None
06813   */
06814 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
06815 {
06816   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06817   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06818                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06819   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
06820 }
06821
06822 /**
06823   * @brief  Get actual source of a fault signal.
06824   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_GetSrc\n
06825   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_GetSrc\n
06826   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_GetSrc\n
06827   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_GetSrc\n
06828   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_GetSrc
06829   * @param  HRTIMx High Resolution Timer instance
06830   * @param  Fault This parameter can be one of the following values:
06831   *         @arg @ref LL_HRTIM_FAULT_1
06832   *         @arg @ref LL_HRTIM_FAULT_2
06833   *         @arg @ref LL_HRTIM_FAULT_3
06834   *         @arg @ref LL_HRTIM_FAULT_4
06835   *         @arg @ref LL_HRTIM_FAULT_5
06836   * @retval Source This parameter can be one of the following values:
06837   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
06838   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
06839   */
06840 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
06841 {
06842   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06843   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06844                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06845   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
06846 }
06847
06848 /**
06849   * @brief  Set the polarity of a fault signal.
06850   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_SetPolarity\n
06851   *         FLTINR1     FLT2P        LL_HRTIM_FLT_SetPolarity\n
06852   *         FLTINR1     FLT3P        LL_HRTIM_FLT_SetPolarity\n
06853   *         FLTINR1     FLT4P        LL_HRTIM_FLT_SetPolarity\n
06854   *         FLTINR2     FLT5P        LL_HRTIM_FLT_SetPolarity
06855   * @note This function must not be called when the fault channel is enabled.
06856   * @param  HRTIMx High Resolution Timer instance
06857   * @param  Fault This parameter can be one of the following values:
06858   *         @arg @ref LL_HRTIM_FAULT_1
06859   *         @arg @ref LL_HRTIM_FAULT_2
06860   *         @arg @ref LL_HRTIM_FAULT_3
06861   *         @arg @ref LL_HRTIM_FAULT_4
06862   *         @arg @ref LL_HRTIM_FAULT_5
06863   * @param  Polarity This parameter can be one of the following values:
06864   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
06865   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
06866   * @retval None
06867   */
06868 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
06869 {
06870   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06871   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06872                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06873   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
06874 }
06875
06876 /**
06877   * @brief  Get actual polarity of a fault signal.
06878   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_GetPolarity\n
06879   *         FLTINR1     FLT2P        LL_HRTIM_FLT_GetPolarity\n
06880   *         FLTINR1     FLT3P        LL_HRTIM_FLT_GetPolarity\n
06881   *         FLTINR1     FLT4P        LL_HRTIM_FLT_GetPolarity\n
06882   *         FLTINR2     FLT5P        LL_HRTIM_FLT_GetPolarity
06883   * @param  HRTIMx High Resolution Timer instance
06884   * @param  Fault This parameter can be one of the following values:
06885   *         @arg @ref LL_HRTIM_FAULT_1
06886   *         @arg @ref LL_HRTIM_FAULT_2
06887   *         @arg @ref LL_HRTIM_FAULT_3
06888   *         @arg @ref LL_HRTIM_FAULT_4
06889   *         @arg @ref LL_HRTIM_FAULT_5
06890   * @retval Polarity This parameter can be one of the following values:
06891   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
06892   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
06893   */
06894 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
06895 {
06896   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06897   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06898                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06899   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
06900 }
06901
06902 /**
06903   * @brief  Set the digital noise filter of a fault signal.
06904   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_SetFilter\n
06905   *         FLTINR1     FLT2F      LL_HRTIM_FLT_SetFilter\n
06906   *         FLTINR1     FLT3F      LL_HRTIM_FLT_SetFilter\n
06907   *         FLTINR1     FLT4F      LL_HRTIM_FLT_SetFilter\n
06908   *         FLTINR2     FLT5F      LL_HRTIM_FLT_SetFilter
06909   * @note This function must not be called when the fault channel is enabled.
06910   * @param  HRTIMx High Resolution Timer instance
06911   * @param  Fault This parameter can be one of the following values:
06912   *         @arg @ref LL_HRTIM_FAULT_1
06913   *         @arg @ref LL_HRTIM_FAULT_2
06914   *         @arg @ref LL_HRTIM_FAULT_3
06915   *         @arg @ref LL_HRTIM_FAULT_4
06916   *         @arg @ref LL_HRTIM_FAULT_5
06917   * @param  Filter This parameter can be one of the following values:
06918   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
06919   *         @arg @ref LL_HRTIM_FLT_FILTER_1
06920   *         @arg @ref LL_HRTIM_FLT_FILTER_2
06921   *         @arg @ref LL_HRTIM_FLT_FILTER_3
06922   *         @arg @ref LL_HRTIM_FLT_FILTER_4
06923   *         @arg @ref LL_HRTIM_FLT_FILTER_5
06924   *         @arg @ref LL_HRTIM_FLT_FILTER_6
06925   *         @arg @ref LL_HRTIM_FLT_FILTER_7
06926   *         @arg @ref LL_HRTIM_FLT_FILTER_8
06927   *         @arg @ref LL_HRTIM_FLT_FILTER_9
06928   *         @arg @ref LL_HRTIM_FLT_FILTER_10
06929   *         @arg @ref LL_HRTIM_FLT_FILTER_11
06930   *         @arg @ref LL_HRTIM_FLT_FILTER_12
06931   *         @arg @ref LL_HRTIM_FLT_FILTER_13
06932   *         @arg @ref LL_HRTIM_FLT_FILTER_14
06933   *         @arg @ref LL_HRTIM_FLT_FILTER_15
06934   * @retval None
06935   */
06936 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
06937 {
06938   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06939   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06940                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06941   MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
06942 }
06943
06944 /**
06945   * @brief  Get actual digital noise filter setting of a fault signal.
06946   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_GetFilter\n
06947   *         FLTINR1     FLT2F      LL_HRTIM_FLT_GetFilter\n
06948   *         FLTINR1     FLT3F      LL_HRTIM_FLT_GetFilter\n
06949   *         FLTINR1     FLT4F      LL_HRTIM_FLT_GetFilter\n
06950   *         FLTINR2     FLT5F      LL_HRTIM_FLT_GetFilter
06951   * @param  HRTIMx High Resolution Timer instance
06952   * @param  Fault This parameter can be one of the following values:
06953   *         @arg @ref LL_HRTIM_FAULT_1
06954   *         @arg @ref LL_HRTIM_FAULT_2
06955   *         @arg @ref LL_HRTIM_FAULT_3
06956   *         @arg @ref LL_HRTIM_FAULT_4
06957   *         @arg @ref LL_HRTIM_FAULT_5
06958   * @retval Filter This parameter can be one of the following values:
06959   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
06960   *         @arg @ref LL_HRTIM_FLT_FILTER_1
06961   *         @arg @ref LL_HRTIM_FLT_FILTER_2
06962   *         @arg @ref LL_HRTIM_FLT_FILTER_3
06963   *         @arg @ref LL_HRTIM_FLT_FILTER_4
06964   *         @arg @ref LL_HRTIM_FLT_FILTER_5
06965   *         @arg @ref LL_HRTIM_FLT_FILTER_6
06966   *         @arg @ref LL_HRTIM_FLT_FILTER_7
06967   *         @arg @ref LL_HRTIM_FLT_FILTER_8
06968   *         @arg @ref LL_HRTIM_FLT_FILTER_9
06969   *         @arg @ref LL_HRTIM_FLT_FILTER_10
06970   *         @arg @ref LL_HRTIM_FLT_FILTER_11
06971   *         @arg @ref LL_HRTIM_FLT_FILTER_12
06972   *         @arg @ref LL_HRTIM_FLT_FILTER_13
06973   *         @arg @ref LL_HRTIM_FLT_FILTER_14
06974   *         @arg @ref LL_HRTIM_FLT_FILTER_15
06975   */
06976 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
06977 {
06978   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
06979   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
06980                                                               REG_OFFSET_TAB_FLTINR[iFault]));
06981   return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);
06982
06983 }
06984
06985 /**
06986   * @brief  Set the fault circuitry prescaler.
06987   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_SetPrescaler
06988   * @param  HRTIMx High Resolution Timer instance
06989   * @param  Prescaler This parameter can be one of the following values:
06990   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
06991   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
06992   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
06993   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
06994   * @retval None
06995   */
06996 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
06997 {
06998   MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
06999 }
07000
07001 /**
07002   * @brief  Get actual fault circuitry prescaler setting.
07003   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_GetPrescaler
07004   * @param  HRTIMx High Resolution Timer instance
07005   * @retval Prescaler This parameter can be one of the following values:
07006   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
07007   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
07008   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
07009   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
07010   */
07011 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
07012 {
07013   return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
07014 }
07015
07016 /**
07017   * @brief  Lock the fault signal conditioning settings.
07018   * @rmtoll FLTINR1     FLT1LCK      LL_HRTIM_FLT_Lock\n
07019   *         FLTINR1     FLT2LCK      LL_HRTIM_FLT_Lock\n
07020   *         FLTINR1     FLT3LCK      LL_HRTIM_FLT_Lock\n
07021   *         FLTINR1     FLT4LCK      LL_HRTIM_FLT_Lock\n
07022   *         FLTINR2     FLT5LCK      LL_HRTIM_FLT_Lock
07023   * @param  HRTIMx High Resolution Timer instance
07024   * @param  Fault This parameter can be one of the following values:
07025   *         @arg @ref LL_HRTIM_FAULT_1
07026   *         @arg @ref LL_HRTIM_FAULT_2
07027   *         @arg @ref LL_HRTIM_FAULT_3
07028   *         @arg @ref LL_HRTIM_FAULT_4
07029   *         @arg @ref LL_HRTIM_FAULT_5
07030   * @retval None
07031   */
07032 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07033 {
07034   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07035   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07036                                                               REG_OFFSET_TAB_FLTINR[iFault]));
07037   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
07038 }
07039
07040 /**
07041   * @brief  Enable the fault circuitry for the designated fault input.
07042   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Enable\n
07043   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Enable\n
07044   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Enable\n
07045   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Enable\n
07046   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Enable
07047   * @param  HRTIMx High Resolution Timer instance
07048   * @param  Fault This parameter can be one of the following values:
07049   *         @arg @ref LL_HRTIM_FAULT_1
07050   *         @arg @ref LL_HRTIM_FAULT_2
07051   *         @arg @ref LL_HRTIM_FAULT_3
07052   *         @arg @ref LL_HRTIM_FAULT_4
07053   *         @arg @ref LL_HRTIM_FAULT_5
07054   * @retval None
07055   */
07056 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07057 {
07058   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07059   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07060                                                               REG_OFFSET_TAB_FLTINR[iFault]));
07061   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
07062 }
07063
07064 /**
07065   * @brief  Disable the fault circuitry for for the designated fault input.
07066   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Disable\n
07067   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Disable\n
07068   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Disable\n
07069   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Disable\n
07070   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Disable
07071   * @param  HRTIMx High Resolution Timer instance
07072   * @param  Fault This parameter can be one of the following values:
07073   *         @arg @ref LL_HRTIM_FAULT_1
07074   *         @arg @ref LL_HRTIM_FAULT_2
07075   *         @arg @ref LL_HRTIM_FAULT_3
07076   *         @arg @ref LL_HRTIM_FAULT_4
07077   *         @arg @ref LL_HRTIM_FAULT_5
07078   * @retval None
07079   */
07080 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07081 {
07082   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07083   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07084                                                               REG_OFFSET_TAB_FLTINR[iFault]));
07085   CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
07086 }
07087
07088 /**
07089   * @brief  Indicate whether the fault circuitry is enabled for a given fault input.
07090   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_IsEnabled\n
07091   *         FLTINR1     FLT2E      LL_HRTIM_FLT_IsEnabled\n
07092   *         FLTINR1     FLT3E      LL_HRTIM_FLT_IsEnabled\n
07093   *         FLTINR1     FLT4E      LL_HRTIM_FLT_IsEnabled\n
07094   *         FLTINR2     FLT5E      LL_HRTIM_FLT_IsEnabled
07095   * @param  HRTIMx High Resolution Timer instance
07096   * @param  Fault This parameter can be one of the following values:
07097   *         @arg @ref LL_HRTIM_FAULT_1
07098   *         @arg @ref LL_HRTIM_FAULT_2
07099   *         @arg @ref LL_HRTIM_FAULT_3
07100   *         @arg @ref LL_HRTIM_FAULT_4
07101   *         @arg @ref LL_HRTIM_FAULT_5
07102   * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
07103   */
07104 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
07105 {
07106   register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
07107   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
07108                                                                     REG_OFFSET_TAB_FLTINR[iFault]));
07109   return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
07110            (HRTIM_IER_FLT1)) ? 1UL : 0UL);
07111 }
07112
07113 /**
07114   * @}
07115   */
07116
07117 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
07118   * @{
07119   */
07120
07121 /**
07122   * @brief  Configure the burst mode controller.
07123   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_Config\n
07124   *         BMCR     BMCLK       LL_HRTIM_BM_Config\n
07125   *         BMCR     BMPRSC      LL_HRTIM_BM_Config
07126   * @param  HRTIMx High Resolution Timer instance
07127   * @param  Configuration This parameter must be a combination of all the following values:
07128   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
07129   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07130   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
07131   * @retval None
07132   */
07133 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
07134 {
07135   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
07136 }
07137
07138 /**
07139   * @brief  Set the burst mode controller operating mode.
07140   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_SetMode
07141   * @param  HRTIMx High Resolution Timer instance
07142   * @param  Mode This parameter can be one of the following values:
07143   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
07144   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
07145   * @retval None
07146   */
07147 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
07148 {
07149   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
07150 }
07151
07152 /**
07153   * @brief  Get actual burst mode controller operating mode.
07154   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_GetMode
07155   * @param  HRTIMx High Resolution Timer instance
07156   * @retval Mode This parameter can be one of the following values:
07157   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
07158   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
07159   */
07160 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
07161 {
07162   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
07163 }
07164
07165 /**
07166   * @brief  Set the burst mode controller clock source.
07167   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_SetClockSrc
07168   * @param  HRTIMx High Resolution Timer instance
07169   * @param  ClockSrc This parameter can be one of the following values:
07170   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
07171   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
07172   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
07173   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
07174   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
07175   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
07176   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
07177   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
07178   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
07179   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07180   * @retval None
07181   */
07182 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
07183 {
07184   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
07185 }
07186
07187 /**
07188   * @brief  Get actual burst mode controller clock source.
07189   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_GetClockSrc
07190   * @param  HRTIMx High Resolution Timer instance
07191   * @retval ClockSrc This parameter can be one of the following values:
07192   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
07193   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
07194   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
07195   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
07196   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
07197   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
07198   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
07199   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
07200   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
07201   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07202   * @retval ClockSrc This parameter can be one of the following values:
07203   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
07204   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
07205   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
07206   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
07207   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
07208   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
07209   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
07210   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
07211   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
07212   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
07213   */
07214 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
07215 {
07216   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
07217 }
07218
07219 /**
07220   * @brief  Set the burst mode controller prescaler.
07221   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_SetPrescaler
07222   * @param  HRTIMx High Resolution Timer instance
07223   * @param  Prescaler This parameter can be one of the following values:
07224   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
07225   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
07226   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
07227   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
07228   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
07229   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
07230   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
07231   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
07232   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
07233   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
07234   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
07235   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
07236   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
07237   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
07238   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
07239   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
07240   * @retval None
07241   */
07242 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
07243 {
07244   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
07245 }
07246
07247 /**
07248   * @brief  Get actual burst mode controller prescaler setting.
07249   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_GetPrescaler
07250   * @param  HRTIMx High Resolution Timer instance
07251   * @retval Prescaler This parameter can be one of the following values:
07252   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
07253   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
07254   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
07255   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
07256   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
07257   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
07258   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
07259   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
07260   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
07261   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
07262   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
07263   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
07264   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
07265   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
07266   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
07267   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
07268   */
07269 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
07270 {
07271   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
07272 }
07273
07274 /**
07275   * @brief  Enable burst mode compare and period registers preload.
07276   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_EnablePreload
07277   * @param  HRTIMx High Resolution Timer instance
07278   * @retval None
07279   */
07280 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
07281 {
07282   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
07283 }
07284
07285 /**
07286   * @brief  Disable burst mode compare and period registers preload.
07287   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_DisablePreload
07288   * @param  HRTIMx High Resolution Timer instance
07289   * @retval None
07290   */
07291 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
07292 {
07293   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
07294 }
07295
07296 /**
07297   * @brief  Indicate whether burst mode compare and period registers are preloaded.
07298   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_IsEnabledPreload
07299   * @param  HRTIMx High Resolution Timer instance
07300   * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
07301   */
07302 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
07303 {
07304   uint32_t temp; /* MISRAC-2012 compliancy */
07305   temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
07306
07307   return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
07308 }
07309
07310 /**
07311   * @brief  Set the burst mode controller trigger
07312   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_SetTrig\n
07313   *         BMTRGR     MSTRST       LL_HRTIM_BM_SetTrig\n
07314   *         BMTRGR     MSTREP       LL_HRTIM_BM_SetTrig\n
07315   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_SetTrig\n
07316   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_SetTrig\n
07317   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_SetTrig\n
07318   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_SetTrig\n
07319   *         BMTRGR     TARST        LL_HRTIM_BM_SetTrig\n
07320   *         BMTRGR     TAREP        LL_HRTIM_BM_SetTrig\n
07321   *         BMTRGR     TACMP1       LL_HRTIM_BM_SetTrig\n
07322   *         BMTRGR     TACMP2       LL_HRTIM_BM_SetTrig\n
07323   *         BMTRGR     TBRST        LL_HRTIM_BM_SetTrig\n
07324   *         BMTRGR     TBREP        LL_HRTIM_BM_SetTrig\n
07325   *         BMTRGR     TBCMP1       LL_HRTIM_BM_SetTrig\n
07326   *         BMTRGR     TBCMP2       LL_HRTIM_BM_SetTrig\n
07327   *         BMTRGR     TCRST        LL_HRTIM_BM_SetTrig\n
07328   *         BMTRGR     TCREP        LL_HRTIM_BM_SetTrig\n
07329   *         BMTRGR     TCCMP1       LL_HRTIM_BM_SetTrig\n
07330   *         BMTRGR     TCCMP2       LL_HRTIM_BM_SetTrig\n
07331   *         BMTRGR     TDRST        LL_HRTIM_BM_SetTrig\n
07332   *         BMTRGR     TDREP        LL_HRTIM_BM_SetTrig\n
07333   *         BMTRGR     TDCMP1       LL_HRTIM_BM_SetTrig\n
07334   *         BMTRGR     TDCMP2       LL_HRTIM_BM_SetTrig\n
07335   *         BMTRGR     TERST        LL_HRTIM_BM_SetTrig\n
07336   *         BMTRGR     TEREP        LL_HRTIM_BM_SetTrig\n
07337   *         BMTRGR     TECMP1       LL_HRTIM_BM_SetTrig\n
07338   *         BMTRGR     TECMP2       LL_HRTIM_BM_SetTrig\n
07339   *         BMTRGR     TAEEV7       LL_HRTIM_BM_SetTrig\n
07340   *         BMTRGR     TAEEV8       LL_HRTIM_BM_SetTrig\n
07341   *         BMTRGR     EEV7         LL_HRTIM_BM_SetTrig\n
07342   *         BMTRGR     EEV8         LL_HRTIM_BM_SetTrig\n
07343   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_SetTrig
07344   * @param  HRTIMx High Resolution Timer instance
07345   * @param  Trig This parameter can be a combination of the following values:
07346   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
07347   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
07348   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
07349   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
07350   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
07351   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
07352   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
07353   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
07354   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
07355   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
07356   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
07357   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
07358   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
07359   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
07360   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
07361   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
07362   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
07363   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
07364   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
07365   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
07366   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
07367   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
07368   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
07369   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
07370   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
07371   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
07372   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
07373   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
07374   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
07375   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
07376   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
07377   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
07378     * @retval None
07379   */
07380 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
07381 {
07382   WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
07383 }
07384
07385 /**
07386   * @brief  Get actual burst mode controller trigger.
07387   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_GetTrig\n
07388   *         BMTRGR     MSTRST       LL_HRTIM_BM_GetTrig\n
07389   *         BMTRGR     MSTREP       LL_HRTIM_BM_GetTrig\n
07390   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_GetTrig\n
07391   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_GetTrig\n
07392   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_GetTrig\n
07393   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_GetTrig\n
07394   *         BMTRGR     TARST        LL_HRTIM_BM_GetTrig\n
07395   *         BMTRGR     TAREP        LL_HRTIM_BM_GetTrig\n
07396   *         BMTRGR     TACMP1       LL_HRTIM_BM_GetTrig\n
07397   *         BMTRGR     TACMP2       LL_HRTIM_BM_GetTrig\n
07398   *         BMTRGR     TBRST        LL_HRTIM_BM_GetTrig\n
07399   *         BMTRGR     TBREP        LL_HRTIM_BM_GetTrig\n
07400   *         BMTRGR     TBCMP1       LL_HRTIM_BM_GetTrig\n
07401   *         BMTRGR     TBCMP2       LL_HRTIM_BM_GetTrig\n
07402   *         BMTRGR     TCRST        LL_HRTIM_BM_GetTrig\n
07403   *         BMTRGR     TCREP        LL_HRTIM_BM_GetTrig\n
07404   *         BMTRGR     TCCMP1       LL_HRTIM_BM_GetTrig\n
07405   *         BMTRGR     TCCMP2       LL_HRTIM_BM_GetTrig\n
07406   *         BMTRGR     TDRST        LL_HRTIM_BM_GetTrig\n
07407   *         BMTRGR     TDREP        LL_HRTIM_BM_GetTrig\n
07408   *         BMTRGR     TDCMP1       LL_HRTIM_BM_GetTrig\n
07409   *         BMTRGR     TDCMP2       LL_HRTIM_BM_GetTrig\n
07410   *         BMTRGR     TERST        LL_HRTIM_BM_GetTrig\n
07411   *         BMTRGR     TEREP        LL_HRTIM_BM_GetTrig\n
07412   *         BMTRGR     TECMP1       LL_HRTIM_BM_GetTrig\n
07413   *         BMTRGR     TECMP2       LL_HRTIM_BM_GetTrig\n
07414   *         BMTRGR     TAEEV7       LL_HRTIM_BM_GetTrig\n
07415   *         BMTRGR     TAEEV8       LL_HRTIM_BM_GetTrig\n
07416   *         BMTRGR     EEV7         LL_HRTIM_BM_GetTrig\n
07417   *         BMTRGR     EEV8         LL_HRTIM_BM_GetTrig\n
07418   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_GetTrig
07419   * @param  HRTIMx High Resolution Timer instance
07420   * @retval Trig This parameter can be a combination of the following values:
07421   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
07422   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
07423   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
07424   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
07425   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
07426   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
07427   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
07428   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
07429   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
07430   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
07431   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
07432   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
07433   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
07434   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
07435   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
07436   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
07437   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
07438   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
07439   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
07440   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
07441   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
07442   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
07443   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
07444   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
07445   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
07446   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
07447   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
07448   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
07449   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
07450   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
07451   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
07452   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
07453   */
07454 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
07455 {
07456   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
07457 }
07458
07459 /**
07460   * @brief  Set the burst mode controller compare value.
07461   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_SetCompare
07462   * @param  HRTIMx High Resolution Timer instance
07463   * @param  CompareValue Compare value must be above or equal to 3
07464   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
07465   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07466   * @retval None
07467   */
07468 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
07469 {
07470   WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
07471 }
07472
07473 /**
07474   * @brief  Get actual burst mode controller compare value.
07475   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_GetCompare
07476   * @param  HRTIMx High Resolution Timer instance
07477   * @retval CompareValue Compare value must be above or equal to 3
07478   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
07479   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07480   */
07481 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
07482 {
07483   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
07484 }
07485
07486 /**
07487   * @brief  Set the burst mode controller period.
07488   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_SetPeriod
07489   * @param  HRTIMx High Resolution Timer instance
07490   * @param  Period The period value must be above or equal to 3 periods of the fHRTIM clock,
07491   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07492   *         The maximum value is 0x0000 FFDF.
07493   * @retval None
07494   */
07495 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
07496 {
07497   WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
07498 }
07499
07500 /**
07501   * @brief  Get actual burst mode controller period.
07502   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_GetPeriod
07503   * @param  HRTIMx High Resolution Timer instance
07504   * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
07505   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
07506   *         The maximum value is 0x0000 FFDF.
07507   */
07508 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
07509 {
07510   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
07511 }
07512
07513 /**
07514   * @brief  Enable the burst mode controller
07515   * @rmtoll BMCR     BME      LL_HRTIM_BM_Enable
07516   * @param  HRTIMx High Resolution Timer instance
07517   * @retval None
07518   */
07519 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
07520 {
07521   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
07522 }
07523
07524 /**
07525   * @brief  Disable the burst mode controller
07526   * @rmtoll BMCR     BME      LL_HRTIM_BM_Disable
07527   * @param  HRTIMx High Resolution Timer instance
07528   * @retval None
07529   */
07530 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
07531 {
07532   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
07533 }
07534
07535 /**
07536   * @brief  Indicate whether the burst mode controller is enabled.
07537   * @rmtoll BMCR     BME      LL_HRTIM_BM_IsEnabled
07538   * @param  HRTIMx High Resolution Timer instance
07539   * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
07540   */
07541 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
07542 {
07543   return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
07544 }
07545
07546 /**
07547   * @brief  Trigger the burst operation (software trigger)
07548   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_Start
07549   * @param  HRTIMx High Resolution Timer instance
07550   * @retval None
07551   */
07552 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
07553 {
07554   SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
07555 }
07556
07557 /**
07558   * @brief  Stop the burst mode operation.
07559   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_Stop
07560   * @note Causes a burst mode early termination.
07561   * @param  HRTIMx High Resolution Timer instance
07562   * @retval None
07563   */
07564 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
07565 {
07566   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
07567 }
07568
07569 /**
07570   * @brief  Get actual burst mode status
07571   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_GetStatus
07572   * @param  HRTIMx High Resolution Timer instance
07573   * @retval Status This parameter can be one of the following values:
07574   *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL
07575   *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
07576   */
07577 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
07578 {
07579   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
07580 }
07581
07582 /**
07583   * @}
07584   */
07585
07586 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
07587   * @{
07588   */
07589
07590 /**
07591   * @brief  Clear the Fault 1 interrupt flag.
07592   * @rmtoll ICR     FLT1C           LL_HRTIM_ClearFlag_FLT1
07593   * @param  HRTIMx High Resolution Timer instance
07594   * @retval None
07595   */
07596 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
07597 {
07598   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
07599 }
07600
07601 /**
07602   * @brief  Indicate whether Fault 1 interrupt occurred.
07603   * @rmtoll ICR     FLT1           LL_HRTIM_IsActiveFlag_FLT1
07604   * @param  HRTIMx High Resolution Timer instance
07605   * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
07606   */
07607 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
07608 {
07609   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
07610 }
07611
07612 /**
07613   * @brief  Clear the Fault 2 interrupt flag.
07614   * @rmtoll ICR     FLT2C           LL_HRTIM_ClearFlag_FLT2
07615   * @param  HRTIMx High Resolution Timer instance
07616   * @retval None
07617   */
07618 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
07619 {
07620   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
07621 }
07622
07623 /**
07624   * @brief  Indicate whether Fault 2 interrupt occurred.
07625   * @rmtoll ICR     FLT2           LL_HRTIM_IsActiveFlag_FLT2
07626   * @param  HRTIMx High Resolution Timer instance
07627   * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
07628   */
07629 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
07630 {
07631   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
07632 }
07633
07634 /**
07635   * @brief  Clear the Fault 3 interrupt flag.
07636   * @rmtoll ICR     FLT3C           LL_HRTIM_ClearFlag_FLT3
07637   * @param  HRTIMx High Resolution Timer instance
07638   * @retval None
07639   */
07640 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
07641 {
07642   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
07643 }
07644
07645 /**
07646   * @brief  Indicate whether Fault 3 interrupt occurred.
07647   * @rmtoll ICR     FLT3           LL_HRTIM_IsActiveFlag_FLT3
07648   * @param  HRTIMx High Resolution Timer instance
07649   * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
07650   */
07651 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
07652 {
07653   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
07654 }
07655
07656 /**
07657   * @brief  Clear the Fault 4 interrupt flag.
07658   * @rmtoll ICR     FLT4C           LL_HRTIM_ClearFlag_FLT4
07659   * @param  HRTIMx High Resolution Timer instance
07660   * @retval None
07661   */
07662 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
07663 {
07664   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
07665 }
07666
07667 /**
07668   * @brief  Indicate whether Fault 4 interrupt occurred.
07669   * @rmtoll ICR     FLT4           LL_HRTIM_IsActiveFlag_FLT4
07670   * @param  HRTIMx High Resolution Timer instance
07671   * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
07672   */
07673 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
07674 {
07675   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
07676 }
07677
07678 /**
07679   * @brief  Clear the Fault 5 interrupt flag.
07680   * @rmtoll ICR     FLT5C           LL_HRTIM_ClearFlag_FLT5
07681   * @param  HRTIMx High Resolution Timer instance
07682   * @retval None
07683   */
07684 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
07685 {
07686   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
07687 }
07688
07689 /**
07690   * @brief  Indicate whether Fault 5 interrupt occurred.
07691   * @rmtoll ICR     FLT5           LL_HRTIM_IsActiveFlag_FLT5
07692   * @param  HRTIMx High Resolution Timer instance
07693   * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
07694   */
07695 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
07696 {
07697   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
07698 }
07699
07700 /**
07701   * @brief  Clear the System Fault interrupt flag.
07702   * @rmtoll ICR     SYSFLTC           LL_HRTIM_ClearFlag_SYSFLT
07703   * @param  HRTIMx High Resolution Timer instance
07704   * @retval None
07705   */
07706 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
07707 {
07708   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
07709 }
07710
07711 /**
07712   * @brief  Indicate whether System Fault interrupt occurred.
07713   * @rmtoll ISR     SYSFLT           LL_HRTIM_IsActiveFlag_SYSFLT
07714   * @param  HRTIMx High Resolution Timer instance
07715   * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
07716   */
07717 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
07718 {
07719   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
07720 }
07721
07722 /**
07723   * @brief  Clear the Burst Mode period interrupt flag.
07724   * @rmtoll ICR     BMPERC           LL_HRTIM_ClearFlag_BMPER
07725   * @param  HRTIMx High Resolution Timer instance
07726   * @retval None
07727   */
07728 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
07729 {
07730   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
07731 }
07732
07733 /**
07734   * @brief  Indicate whether Burst Mode period interrupt occurred.
07735   * @rmtoll ISR     BMPER           LL_HRTIM_IsActiveFlag_BMPER
07736   * @param  HRTIMx High Resolution Timer instance
07737   * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
07738   */
07739 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
07740 {
07741   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
07742 }
07743
07744 /**
07745   * @brief  Clear the Synchronization Input interrupt flag.
07746   * @rmtoll MICR     SYNCC           LL_HRTIM_ClearFlag_SYNC
07747   * @param  HRTIMx High Resolution Timer instance
07748   * @retval None
07749   */
07750 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
07751 {
07752   SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
07753 }
07754
07755 /**
07756   * @brief  Indicate whether the Synchronization Input interrupt occurred.
07757   * @rmtoll MISR     SYNC           LL_HRTIM_IsActiveFlag_SYNC
07758   * @param  HRTIMx High Resolution Timer instance
07759   * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).
07760   */
07761 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
07762 {
07763   return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
07764 }
07765
07766 /**
07767   * @brief  Clear the update interrupt flag for a given timer (including the master timer) .
07768   * @rmtoll MICR        MUPDC          LL_HRTIM_ClearFlag_UPDATE\n
07769   *         TIMxICR     UPDC           LL_HRTIM_ClearFlag_UPDATE
07770   * @param  HRTIMx High Resolution Timer instance
07771   * @param  Timer This parameter can be one of the following values:
07772   *         @arg @ref LL_HRTIM_TIMER_MASTER
07773   *         @arg @ref LL_HRTIM_TIMER_A
07774   *         @arg @ref LL_HRTIM_TIMER_B
07775   *         @arg @ref LL_HRTIM_TIMER_C
07776   *         @arg @ref LL_HRTIM_TIMER_D
07777   *         @arg @ref LL_HRTIM_TIMER_E
07778   * @retval None
07779   */
07780 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07781 {
07782   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07783   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07784                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07785   SET_BIT(*pReg, HRTIM_MICR_MUPD);
07786 }
07787
07788 /**
07789   * @brief  Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
07790   * @rmtoll MISR        MUPD          LL_HRTIM_IsActiveFlag_UPDATE\n
07791   *         TIMxISR     UPD           LL_HRTIM_IsActiveFlag_UPDATE
07792   * @param  HRTIMx High Resolution Timer instance
07793   * @param  Timer This parameter can be one of the following values:
07794   *         @arg @ref LL_HRTIM_TIMER_MASTER
07795   *         @arg @ref LL_HRTIM_TIMER_A
07796   *         @arg @ref LL_HRTIM_TIMER_B
07797   *         @arg @ref LL_HRTIM_TIMER_C
07798   *         @arg @ref LL_HRTIM_TIMER_D
07799   *         @arg @ref LL_HRTIM_TIMER_E
07800   * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07801   */
07802 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07803 {
07804   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07805   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07806                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07807
07808   return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
07809 }
07810
07811 /**
07812   * @brief  Clear the repetition interrupt flag for a given timer (including the master timer) .
07813   * @rmtoll MICR        MREPC          LL_HRTIM_ClearFlag_REP\n
07814   *         TIMxICR     REPC           LL_HRTIM_ClearFlag_REP
07815   * @param  HRTIMx High Resolution Timer instance
07816   * @param  Timer This parameter can be one of the following values:
07817   *         @arg @ref LL_HRTIM_TIMER_MASTER
07818   *         @arg @ref LL_HRTIM_TIMER_A
07819   *         @arg @ref LL_HRTIM_TIMER_B
07820   *         @arg @ref LL_HRTIM_TIMER_C
07821   *         @arg @ref LL_HRTIM_TIMER_D
07822   *         @arg @ref LL_HRTIM_TIMER_E
07823   * @retval None
07824   */
07825 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07826 {
07827   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07828   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07829                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07830   SET_BIT(*pReg, HRTIM_MICR_MREP);
07831
07832 }
07833
07834 /**
07835   * @brief  Indicate whether the repetition  interrupt has occurred for a given timer (including the master timer) .
07836   * @rmtoll MISR        MREP          LL_HRTIM_IsActiveFlag_REP\n
07837   *         TIMxISR     REP           LL_HRTIM_IsActiveFlag_REP
07838   * @param  HRTIMx High Resolution Timer instance
07839   * @param  Timer This parameter can be one of the following values:
07840   *         @arg @ref LL_HRTIM_TIMER_MASTER
07841   *         @arg @ref LL_HRTIM_TIMER_A
07842   *         @arg @ref LL_HRTIM_TIMER_B
07843   *         @arg @ref LL_HRTIM_TIMER_C
07844   *         @arg @ref LL_HRTIM_TIMER_D
07845   *         @arg @ref LL_HRTIM_TIMER_E
07846   * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07847   */
07848 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07849 {
07850   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07851   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07852                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07853
07854   return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
07855 }
07856
07857 /**
07858   * @brief  Clear the compare 1 match interrupt for a given timer (including the master timer).
07859   * @rmtoll MICR        MCMP1C          LL_HRTIM_ClearFlag_CMP1\n
07860   *         TIMxICR     CMP1C           LL_HRTIM_ClearFlag_CMP1
07861   * @param  HRTIMx High Resolution Timer instance
07862   * @param  Timer This parameter can be one of the following values:
07863   *         @arg @ref LL_HRTIM_TIMER_MASTER
07864   *         @arg @ref LL_HRTIM_TIMER_A
07865   *         @arg @ref LL_HRTIM_TIMER_B
07866   *         @arg @ref LL_HRTIM_TIMER_C
07867   *         @arg @ref LL_HRTIM_TIMER_D
07868   *         @arg @ref LL_HRTIM_TIMER_E
07869   * @retval None
07870   */
07871 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07872 {
07873   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07874   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07875                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07876   SET_BIT(*pReg, HRTIM_MICR_MCMP1);
07877 }
07878
07879 /**
07880   * @brief  Indicate whether the compare match 1  interrupt has occurred for a given timer (including the master timer) .
07881   * @rmtoll MISR        MCMP1          LL_HRTIM_IsActiveFlag_CMP1\n
07882   *         TIMxISR     CMP1           LL_HRTIM_IsActiveFlag_CMP1
07883   * @param  HRTIMx High Resolution Timer instance
07884   * @param  Timer This parameter can be one of the following values:
07885   *         @arg @ref LL_HRTIM_TIMER_MASTER
07886   *         @arg @ref LL_HRTIM_TIMER_A
07887   *         @arg @ref LL_HRTIM_TIMER_B
07888   *         @arg @ref LL_HRTIM_TIMER_C
07889   *         @arg @ref LL_HRTIM_TIMER_D
07890   *         @arg @ref LL_HRTIM_TIMER_E
07891   * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07892   */
07893 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07894 {
07895   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07896   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07897                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07898
07899   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
07900 }
07901
07902 /**
07903   * @brief  Clear the compare 2 match interrupt for a given timer (including the master timer).
07904   * @rmtoll MICR        MCMP2C          LL_HRTIM_ClearFlag_CMP2\n
07905   *         TIMxICR     CMP2C           LL_HRTIM_ClearFlag_CMP2
07906   * @param  HRTIMx High Resolution Timer instance
07907   * @param  Timer This parameter can be one of the following values:
07908   *         @arg @ref LL_HRTIM_TIMER_MASTER
07909   *         @arg @ref LL_HRTIM_TIMER_A
07910   *         @arg @ref LL_HRTIM_TIMER_B
07911   *         @arg @ref LL_HRTIM_TIMER_C
07912   *         @arg @ref LL_HRTIM_TIMER_D
07913   *         @arg @ref LL_HRTIM_TIMER_E
07914   * @retval None
07915   */
07916 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07917 {
07918   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07919   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07920                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07921   SET_BIT(*pReg, HRTIM_MICR_MCMP2);
07922 }
07923
07924 /**
07925   * @brief  Indicate whether the compare match 2  interrupt has occurred for a given timer (including the master timer) .
07926   * @rmtoll MISR        MCMP2          LL_HRTIM_IsActiveFlag_CMP2\n
07927   *         TIMxISR     CMP2           LL_HRTIM_IsActiveFlag_CMP2
07928   * @param  HRTIMx High Resolution Timer instance
07929   * @param  Timer This parameter can be one of the following values:
07930   *         @arg @ref LL_HRTIM_TIMER_MASTER
07931   *         @arg @ref LL_HRTIM_TIMER_A
07932   *         @arg @ref LL_HRTIM_TIMER_B
07933   *         @arg @ref LL_HRTIM_TIMER_C
07934   *         @arg @ref LL_HRTIM_TIMER_D
07935   *         @arg @ref LL_HRTIM_TIMER_E
07936   * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07937   */
07938 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07939 {
07940   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07941   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07942                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07943
07944   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
07945 }
07946
07947 /**
07948   * @brief  Clear the compare 3 match interrupt for a given timer (including the master timer).
07949   * @rmtoll MICR        MCMP3C          LL_HRTIM_ClearFlag_CMP3\n
07950   *         TIMxICR     CMP3C           LL_HRTIM_ClearFlag_CMP3
07951   * @param  HRTIMx High Resolution Timer instance
07952   * @param  Timer This parameter can be one of the following values:
07953   *         @arg @ref LL_HRTIM_TIMER_MASTER
07954   *         @arg @ref LL_HRTIM_TIMER_A
07955   *         @arg @ref LL_HRTIM_TIMER_B
07956   *         @arg @ref LL_HRTIM_TIMER_C
07957   *         @arg @ref LL_HRTIM_TIMER_D
07958   *         @arg @ref LL_HRTIM_TIMER_E
07959   * @retval None
07960   */
07961 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07962 {
07963   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07964   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
07965                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07966   SET_BIT(*pReg, HRTIM_MICR_MCMP3);
07967 }
07968
07969 /**
07970   * @brief  Indicate whether the compare match 3  interrupt has occurred for a given timer (including the master timer) .
07971   * @rmtoll MISR        MCMP3          LL_HRTIM_IsActiveFlag_CMP3\n
07972   *         TIMxISR     CMP3           LL_HRTIM_IsActiveFlag_CMP3
07973   * @param  HRTIMx High Resolution Timer instance
07974   * @param  Timer This parameter can be one of the following values:
07975   *         @arg @ref LL_HRTIM_TIMER_MASTER
07976   *         @arg @ref LL_HRTIM_TIMER_A
07977   *         @arg @ref LL_HRTIM_TIMER_B
07978   *         @arg @ref LL_HRTIM_TIMER_C
07979   *         @arg @ref LL_HRTIM_TIMER_D
07980   *         @arg @ref LL_HRTIM_TIMER_E
07981   * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
07982   */
07983 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07984 {
07985   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
07986   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
07987                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07988
07989   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
07990 }
07991
07992 /**
07993   * @brief  Clear the compare 4 match interrupt for a given timer (including the master timer).
07994   * @rmtoll MICR        MCMP4C          LL_HRTIM_ClearFlag_CMP4\n
07995   *         TIMxICR     CMP4C           LL_HRTIM_ClearFlag_CMP4
07996   * @param  HRTIMx High Resolution Timer instance
07997   * @param  Timer This parameter can be one of the following values:
07998   *         @arg @ref LL_HRTIM_TIMER_MASTER
07999   *         @arg @ref LL_HRTIM_TIMER_A
08000   *         @arg @ref LL_HRTIM_TIMER_B
08001   *         @arg @ref LL_HRTIM_TIMER_C
08002   *         @arg @ref LL_HRTIM_TIMER_D
08003   *         @arg @ref LL_HRTIM_TIMER_E
08004   * @retval None
08005   */
08006 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08007 {
08008   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08009   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08010                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08011   SET_BIT(*pReg, HRTIM_MICR_MCMP4);
08012 }
08013
08014 /**
08015   * @brief  Indicate whether the compare match 4  interrupt has occurred for a given timer (including the master timer) .
08016   * @rmtoll MISR        MCMP4          LL_HRTIM_IsActiveFlag_CMP4\n
08017   *         TIMxISR     CMP4           LL_HRTIM_IsActiveFlag_CMP4
08018   * @param  HRTIMx High Resolution Timer instance
08019   * @param  Timer This parameter can be one of the following values:
08020   *         @arg @ref LL_HRTIM_TIMER_MASTER
08021   *         @arg @ref LL_HRTIM_TIMER_A
08022   *         @arg @ref LL_HRTIM_TIMER_B
08023   *         @arg @ref LL_HRTIM_TIMER_C
08024   *         @arg @ref LL_HRTIM_TIMER_D
08025   *         @arg @ref LL_HRTIM_TIMER_E
08026   * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
08027   */
08028 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08029 {
08030   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08031   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08032                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08033
08034   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
08035 }
08036
08037 /**
08038   * @brief  Clear the capture 1 interrupt flag for a given timer.
08039   * @rmtoll TIMxICR     CPT1C           LL_HRTIM_ClearFlag_CPT1
08040   * @param  HRTIMx High Resolution Timer instance
08041   * @param  Timer This parameter can be one of the following values:
08042   *         @arg @ref LL_HRTIM_TIMER_A
08043   *         @arg @ref LL_HRTIM_TIMER_B
08044   *         @arg @ref LL_HRTIM_TIMER_C
08045   *         @arg @ref LL_HRTIM_TIMER_D
08046   *         @arg @ref LL_HRTIM_TIMER_E
08047   * @retval None
08048   */
08049 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08050 {
08051   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08052   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08053                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08054   SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
08055 }
08056
08057 /**
08058   * @brief  Indicate whether the capture 1 interrupt occurred for a given timer.
08059   * @rmtoll TIMxISR     CPT1           LL_HRTIM_IsActiveFlag_CPT1
08060   * @param  HRTIMx High Resolution Timer instance
08061   * @param  Timer This parameter can be one of the following values:
08062   *         @arg @ref LL_HRTIM_TIMER_A
08063   *         @arg @ref LL_HRTIM_TIMER_B
08064   *         @arg @ref LL_HRTIM_TIMER_C
08065   *         @arg @ref LL_HRTIM_TIMER_D
08066   *         @arg @ref LL_HRTIM_TIMER_E
08067   * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
08068   */
08069 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08070 {
08071   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08072   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08073                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08074
08075   return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
08076 }
08077
08078 /**
08079   * @brief  Clear the capture 2 interrupt flag for a given timer.
08080   * @rmtoll TIMxICR     CPT2C           LL_HRTIM_ClearFlag_CPT2
08081   * @param  HRTIMx High Resolution Timer instance
08082   * @param  Timer This parameter can be one of the following values:
08083   *         @arg @ref LL_HRTIM_TIMER_A
08084   *         @arg @ref LL_HRTIM_TIMER_B
08085   *         @arg @ref LL_HRTIM_TIMER_C
08086   *         @arg @ref LL_HRTIM_TIMER_D
08087   *         @arg @ref LL_HRTIM_TIMER_E
08088   * @retval None
08089   */
08090 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08091 {
08092   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08093   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08094                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08095   SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
08096 }
08097
08098 /**
08099   * @brief  Indicate whether the capture 2 interrupt occurred for a given timer.
08100   * @rmtoll TIMxISR     CPT2           LL_HRTIM_IsActiveFlag_CPT2
08101   * @param  HRTIMx High Resolution Timer instance
08102   * @param  Timer This parameter can be one of the following values:
08103   *         @arg @ref LL_HRTIM_TIMER_A
08104   *         @arg @ref LL_HRTIM_TIMER_B
08105   *         @arg @ref LL_HRTIM_TIMER_C
08106   *         @arg @ref LL_HRTIM_TIMER_D
08107   *         @arg @ref LL_HRTIM_TIMER_E
08108   * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
08109   */
08110 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08111 {
08112   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08113   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08114                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08115
08116   return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
08117 }
08118
08119 /**
08120   * @brief  Clear the output 1 set interrupt flag for a given timer.
08121   * @rmtoll TIMxICR     SET1C           LL_HRTIM_ClearFlag_SET1
08122   * @param  HRTIMx High Resolution Timer instance
08123   * @param  Timer This parameter can be one of the following values:
08124   *         @arg @ref LL_HRTIM_TIMER_A
08125   *         @arg @ref LL_HRTIM_TIMER_B
08126   *         @arg @ref LL_HRTIM_TIMER_C
08127   *         @arg @ref LL_HRTIM_TIMER_D
08128   *         @arg @ref LL_HRTIM_TIMER_E
08129   * @retval None
08130   */
08131 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08132 {
08133   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08134   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08135                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08136   SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
08137 }
08138
08139 /**
08140   * @brief  Indicate whether the output 1 set interrupt occurred for a given timer.
08141   * @rmtoll TIMxISR     SET1           LL_HRTIM_IsActiveFlag_SET1
08142   * @param  HRTIMx High Resolution Timer instance
08143   * @param  Timer This parameter can be one of the following values:
08144   *         @arg @ref LL_HRTIM_TIMER_A
08145   *         @arg @ref LL_HRTIM_TIMER_B
08146   *         @arg @ref LL_HRTIM_TIMER_C
08147   *         @arg @ref LL_HRTIM_TIMER_D
08148   *         @arg @ref LL_HRTIM_TIMER_E
08149   * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
08150   */
08151 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08152 {
08153   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08154   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08155                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08156
08157   return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
08158 }
08159
08160 /**
08161   * @brief  Clear the output 1 reset interrupt flag for a given timer.
08162   * @rmtoll TIMxICR     RST1C           LL_HRTIM_ClearFlag_RST1
08163   * @param  HRTIMx High Resolution Timer instance
08164   * @param  Timer This parameter can be one of the following values:
08165   *         @arg @ref LL_HRTIM_TIMER_A
08166   *         @arg @ref LL_HRTIM_TIMER_B
08167   *         @arg @ref LL_HRTIM_TIMER_C
08168   *         @arg @ref LL_HRTIM_TIMER_D
08169   *         @arg @ref LL_HRTIM_TIMER_E
08170   * @retval None
08171   */
08172 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08173 {
08174   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08175   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08176                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08177   SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
08178 }
08179
08180 /**
08181   * @brief  Indicate whether the output 1 reset interrupt occurred for a given timer.
08182   * @rmtoll TIMxISR     RST1           LL_HRTIM_IsActiveFlag_RST1
08183   * @param  HRTIMx High Resolution Timer instance
08184   * @param  Timer This parameter can be one of the following values:
08185   *         @arg @ref LL_HRTIM_TIMER_A
08186   *         @arg @ref LL_HRTIM_TIMER_B
08187   *         @arg @ref LL_HRTIM_TIMER_C
08188   *         @arg @ref LL_HRTIM_TIMER_D
08189   *         @arg @ref LL_HRTIM_TIMER_E
08190   * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
08191   */
08192 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08193 {
08194   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08195   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08196                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08197
08198   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
08199 }
08200
08201 /**
08202   * @brief  Clear the output 2 set interrupt flag for a given timer.
08203   * @rmtoll TIMxICR     SET2C           LL_HRTIM_ClearFlag_SET2
08204   * @param  HRTIMx High Resolution Timer instance
08205   * @param  Timer This parameter can be one of the following values:
08206   *         @arg @ref LL_HRTIM_TIMER_A
08207   *         @arg @ref LL_HRTIM_TIMER_B
08208   *         @arg @ref LL_HRTIM_TIMER_C
08209   *         @arg @ref LL_HRTIM_TIMER_D
08210   *         @arg @ref LL_HRTIM_TIMER_E
08211   * @retval None
08212   */
08213 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08214 {
08215   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08216   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08217                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08218   SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
08219 }
08220
08221 /**
08222   * @brief  Indicate whether the output 2 set interrupt occurred for a given timer.
08223   * @rmtoll TIMxISR     SET2           LL_HRTIM_IsActiveFlag_SET2
08224   * @param  HRTIMx High Resolution Timer instance
08225   * @param  Timer This parameter can be one of the following values:
08226   *         @arg @ref LL_HRTIM_TIMER_A
08227   *         @arg @ref LL_HRTIM_TIMER_B
08228   *         @arg @ref LL_HRTIM_TIMER_C
08229   *         @arg @ref LL_HRTIM_TIMER_D
08230   *         @arg @ref LL_HRTIM_TIMER_E
08231   * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
08232   */
08233 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08234 {
08235   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08236   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08237                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08238
08239   return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
08240 }
08241
08242 /**
08243   * @brief  Clear the output 2reset interrupt flag for a given timer.
08244   * @rmtoll TIMxICR     RST2C           LL_HRTIM_ClearFlag_RST2
08245   * @param  HRTIMx High Resolution Timer instance
08246   * @param  Timer This parameter can be one of the following values:
08247   *         @arg @ref LL_HRTIM_TIMER_A
08248   *         @arg @ref LL_HRTIM_TIMER_B
08249   *         @arg @ref LL_HRTIM_TIMER_C
08250   *         @arg @ref LL_HRTIM_TIMER_D
08251   *         @arg @ref LL_HRTIM_TIMER_E
08252   * @retval None
08253   */
08254 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08255 {
08256   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08257   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08258                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08259   SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
08260 }
08261
08262 /**
08263   * @brief  Indicate whether the output 2 reset interrupt occurred for a given timer.
08264   * @rmtoll TIMxISR     RST2           LL_HRTIM_IsActiveFlag_RST2
08265   * @param  HRTIMx High Resolution Timer instance
08266   * @param  Timer This parameter can be one of the following values:
08267   *         @arg @ref LL_HRTIM_TIMER_A
08268   *         @arg @ref LL_HRTIM_TIMER_B
08269   *         @arg @ref LL_HRTIM_TIMER_C
08270   *         @arg @ref LL_HRTIM_TIMER_D
08271   *         @arg @ref LL_HRTIM_TIMER_E
08272   * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
08273   */
08274 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08275 {
08276   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08277   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08278                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08279
08280   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
08281 }
08282
08283 /**
08284   * @brief  Clear the reset and/or roll-over interrupt flag for a given timer.
08285   * @rmtoll TIMxICR     RSTC           LL_HRTIM_ClearFlag_RST
08286   * @param  HRTIMx High Resolution Timer instance
08287   * @param  Timer This parameter can be one of the following values:
08288   *         @arg @ref LL_HRTIM_TIMER_A
08289   *         @arg @ref LL_HRTIM_TIMER_B
08290   *         @arg @ref LL_HRTIM_TIMER_C
08291   *         @arg @ref LL_HRTIM_TIMER_D
08292   *         @arg @ref LL_HRTIM_TIMER_E
08293   * @retval None
08294   */
08295 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08296 {
08297   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08298   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08299                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08300   SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
08301 }
08302
08303 /**
08304   * @brief  Indicate whether the  reset and/or roll-over interrupt occurred for a given timer.
08305   * @rmtoll TIMxISR     RST           LL_HRTIM_IsActiveFlag_RST
08306   * @param  HRTIMx High Resolution Timer instance
08307   * @param  Timer This parameter can be one of the following values:
08308   *         @arg @ref LL_HRTIM_TIMER_A
08309   *         @arg @ref LL_HRTIM_TIMER_B
08310   *         @arg @ref LL_HRTIM_TIMER_C
08311   *         @arg @ref LL_HRTIM_TIMER_D
08312   *         @arg @ref LL_HRTIM_TIMER_E
08313   * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
08314   */
08315 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08316 {
08317   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08318   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08319                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08320
08321   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
08322 }
08323
08324 /**
08325   * @brief  Clear the delayed protection interrupt flag for a given timer.
08326   * @rmtoll TIMxICR     DLYPRTC           LL_HRTIM_ClearFlag_DLYPRT
08327   * @param  HRTIMx High Resolution Timer instance
08328   * @param  Timer This parameter can be one of the following values:
08329   *         @arg @ref LL_HRTIM_TIMER_A
08330   *         @arg @ref LL_HRTIM_TIMER_B
08331   *         @arg @ref LL_HRTIM_TIMER_C
08332   *         @arg @ref LL_HRTIM_TIMER_D
08333   *         @arg @ref LL_HRTIM_TIMER_E
08334   * @retval None
08335   */
08336 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08337 {
08338   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08339   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
08340                                                               REG_OFFSET_TAB_TIMER[iTimer]));
08341   SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
08342 }
08343
08344 /**
08345   * @brief  Indicate whether the  delayed protection interrupt occurred for a given timer.
08346   * @rmtoll TIMxISR     DLYPRT           LL_HRTIM_IsActiveFlag_DLYPRT
08347   * @param  HRTIMx High Resolution Timer instance
08348   * @param  Timer This parameter can be one of the following values:
08349   *         @arg @ref LL_HRTIM_TIMER_A
08350   *         @arg @ref LL_HRTIM_TIMER_B
08351   *         @arg @ref LL_HRTIM_TIMER_C
08352   *         @arg @ref LL_HRTIM_TIMER_D
08353   *         @arg @ref LL_HRTIM_TIMER_E
08354   * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
08355   */
08356 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08357 {
08358   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08359   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
08360                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08361
08362   return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
08363 }
08364
08365 /**
08366   * @}
08367   */
08368
08369 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
08370   * @{
08371   */
08372
08373 /**
08374   * @brief  Enable the fault 1 interrupt.
08375   * @rmtoll IER     FLT1IE           LL_HRTIM_EnableIT_FLT1
08376   * @param  HRTIMx High Resolution Timer instance
08377   * @retval None
08378   */
08379 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
08380 {
08381   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
08382 }
08383
08384 /**
08385   * @brief  Disable the fault 1 interrupt.
08386   * @rmtoll IER     FLT1IE           LL_HRTIM_DisableIT_FLT1
08387   * @param  HRTIMx High Resolution Timer instance
08388   * @retval None
08389   */
08390 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
08391 {
08392   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
08393 }
08394
08395 /**
08396   * @brief  Indicate whether the fault 1 interrupt is enabled.
08397   * @rmtoll IER     FLT1IE           LL_HRTIM_IsEnabledIT_FLT1
08398   * @param  HRTIMx High Resolution Timer instance
08399   * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
08400   */
08401 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
08402 {
08403   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
08404 }
08405
08406 /**
08407   * @brief  Enable the fault 2 interrupt.
08408   * @rmtoll IER     FLT2IE           LL_HRTIM_EnableIT_FLT2
08409   * @param  HRTIMx High Resolution Timer instance
08410   * @retval None
08411   */
08412 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
08413 {
08414   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
08415 }
08416
08417 /**
08418   * @brief  Disable the fault 2 interrupt.
08419   * @rmtoll IER     FLT2IE           LL_HRTIM_DisableIT_FLT2
08420   * @param  HRTIMx High Resolution Timer instance
08421   * @retval None
08422   */
08423 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
08424 {
08425   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
08426 }
08427
08428 /**
08429   * @brief  Indicate whether the fault 2 interrupt is enabled.
08430   * @rmtoll IER     FLT2IE           LL_HRTIM_IsEnabledIT_FLT2
08431   * @param  HRTIMx High Resolution Timer instance
08432   * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
08433   */
08434 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
08435 {
08436   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
08437 }
08438
08439 /**
08440   * @brief  Enable the fault 3 interrupt.
08441   * @rmtoll IER     FLT3IE           LL_HRTIM_EnableIT_FLT3
08442   * @param  HRTIMx High Resolution Timer instance
08443   * @retval None
08444   */
08445 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
08446 {
08447   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
08448 }
08449
08450 /**
08451   * @brief  Disable the fault 3 interrupt.
08452   * @rmtoll IER     FLT3IE           LL_HRTIM_DisableIT_FLT3
08453   * @param  HRTIMx High Resolution Timer instance
08454   * @retval None
08455   */
08456 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
08457 {
08458   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
08459 }
08460
08461 /**
08462   * @brief  Indicate whether the fault 3 interrupt is enabled.
08463   * @rmtoll IER     FLT3IE           LL_HRTIM_IsEnabledIT_FLT3
08464   * @param  HRTIMx High Resolution Timer instance
08465   * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
08466   */
08467 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
08468 {
08469   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
08470 }
08471
08472 /**
08473   * @brief  Enable the fault 4 interrupt.
08474   * @rmtoll IER     FLT4IE           LL_HRTIM_EnableIT_FLT4
08475   * @param  HRTIMx High Resolution Timer instance
08476   * @retval None
08477   */
08478 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
08479 {
08480   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
08481 }
08482
08483 /**
08484   * @brief  Disable the fault 4 interrupt.
08485   * @rmtoll IER     FLT4IE           LL_HRTIM_DisableIT_FLT4
08486   * @param  HRTIMx High Resolution Timer instance
08487   * @retval None
08488   */
08489 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
08490 {
08491   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
08492 }
08493
08494 /**
08495   * @brief  Indicate whether the fault 4 interrupt is enabled.
08496   * @rmtoll IER     FLT4IE           LL_HRTIM_IsEnabledIT_FLT4
08497   * @param  HRTIMx High Resolution Timer instance
08498   * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
08499   */
08500 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
08501 {
08502   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
08503 }
08504
08505 /**
08506   * @brief  Enable the fault 5 interrupt.
08507   * @rmtoll IER     FLT5IE           LL_HRTIM_EnableIT_FLT5
08508   * @param  HRTIMx High Resolution Timer instance
08509   * @retval None
08510   */
08511 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
08512 {
08513   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
08514 }
08515
08516 /**
08517   * @brief  Disable the fault 5 interrupt.
08518   * @rmtoll IER     FLT5IE           LL_HRTIM_DisableIT_FLT5
08519   * @param  HRTIMx High Resolution Timer instance
08520   * @retval None
08521   */
08522 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
08523 {
08524   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
08525 }
08526
08527 /**
08528   * @brief  Indicate whether the fault 5 interrupt is enabled.
08529   * @rmtoll IER     FLT5IE           LL_HRTIM_IsEnabledIT_FLT5
08530   * @param  HRTIMx High Resolution Timer instance
08531   * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
08532   */
08533 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
08534 {
08535   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
08536 }
08537
08538 /**
08539   * @brief  Enable the system fault interrupt.
08540   * @rmtoll IER     SYSFLTIE           LL_HRTIM_EnableIT_SYSFLT
08541   * @param  HRTIMx High Resolution Timer instance
08542   * @retval None
08543   */
08544 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08545 {
08546   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
08547 }
08548
08549 /**
08550   * @brief  Disable the system fault interrupt.
08551   * @rmtoll IER     SYSFLTIE           LL_HRTIM_DisableIT_SYSFLT
08552   * @param  HRTIMx High Resolution Timer instance
08553   * @retval None
08554   */
08555 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08556 {
08557   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
08558 }
08559
08560 /**
08561   * @brief  Indicate whether the system fault interrupt is enabled.
08562   * @rmtoll IER     SYSFLTIE           LL_HRTIM_IsEnabledIT_SYSFLT
08563   * @param  HRTIMx High Resolution Timer instance
08564   * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
08565   */
08566 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
08567 {
08568   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
08569 }
08570
08571 /**
08572   * @brief  Enable the burst mode period interrupt.
08573   * @rmtoll IER     BMPERIE           LL_HRTIM_EnableIT_BMPER
08574   * @param  HRTIMx High Resolution Timer instance
08575   * @retval None
08576   */
08577 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
08578 {
08579   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
08580 }
08581
08582 /**
08583   * @brief  Disable the burst mode period interrupt.
08584   * @rmtoll IER     BMPERIE           LL_HRTIM_DisableIT_BMPER
08585   * @param  HRTIMx High Resolution Timer instance
08586   * @retval None
08587   */
08588 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
08589 {
08590   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
08591 }
08592
08593 /**
08594   * @brief  Indicate whether the burst mode period interrupt is enabled.
08595   * @rmtoll IER     BMPERIE           LL_HRTIM_IsEnabledIT_BMPER
08596   * @param  HRTIMx High Resolution Timer instance
08597   * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
08598   */
08599 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
08600 {
08601   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
08602 }
08603
08604 /**
08605   * @brief  Enable the synchronization input interrupt.
08606   * @rmtoll MDIER     SYNCIE           LL_HRTIM_EnableIT_SYNC
08607   * @param  HRTIMx High Resolution Timer instance
08608   * @retval None
08609   */
08610 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
08611 {
08612   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
08613 }
08614
08615 /**
08616   * @brief  Disable the synchronization input interrupt.
08617   * @rmtoll MDIER     SYNCIE           LL_HRTIM_DisableIT_SYNC
08618   * @param  HRTIMx High Resolution Timer instance
08619   * @retval None
08620   */
08621 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
08622 {
08623   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
08624 }
08625
08626 /**
08627   * @brief  Indicate whether the synchronization input interrupt is enabled.
08628   * @rmtoll MDIER     SYNCIE           LL_HRTIM_IsEnabledIT_SYNC
08629   * @param  HRTIMx High Resolution Timer instance
08630   * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
08631   */
08632 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
08633 {
08634   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
08635 }
08636
08637 /**
08638   * @brief  Enable the update interrupt for a given timer.
08639   * @rmtoll MDIER        MUPDIE           LL_HRTIM_EnableIT_UPDATE\n
08640   *         TIMxDIER     UPDIE            LL_HRTIM_EnableIT_UPDATE
08641   * @param  HRTIMx High Resolution Timer instance
08642   * @param  Timer This parameter can be one of the following values:
08643   *         @arg @ref LL_HRTIM_TIMER_MASTER
08644   *         @arg @ref LL_HRTIM_TIMER_A
08645   *         @arg @ref LL_HRTIM_TIMER_B
08646   *         @arg @ref LL_HRTIM_TIMER_C
08647   *         @arg @ref LL_HRTIM_TIMER_D
08648   *         @arg @ref LL_HRTIM_TIMER_E
08649   * @retval None
08650   */
08651 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08652 {
08653   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08654   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08655                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08656   SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
08657 }
08658
08659 /**
08660   * @brief  Disable the update interrupt for a given timer.
08661   * @rmtoll MDIER        MUPDIE           LL_HRTIM_DisableIT_UPDATE\n
08662   *         TIMxDIER     UPDIE            LL_HRTIM_DisableIT_UPDATE
08663   * @param  HRTIMx High Resolution Timer instance
08664   * @param  Timer This parameter can be one of the following values:
08665   *         @arg @ref LL_HRTIM_TIMER_MASTER
08666   *         @arg @ref LL_HRTIM_TIMER_A
08667   *         @arg @ref LL_HRTIM_TIMER_B
08668   *         @arg @ref LL_HRTIM_TIMER_C
08669   *         @arg @ref LL_HRTIM_TIMER_D
08670   *         @arg @ref LL_HRTIM_TIMER_E
08671   * @retval None
08672   */
08673 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08674 {
08675   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08676   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08677                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08678   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
08679 }
08680
08681 /**
08682   * @brief  Indicate whether the update interrupt is enabled for a given timer.
08683   * @rmtoll MDIER        MUPDIE           LL_HRTIM_IsEnabledIT_UPDATE\n
08684   *         TIMxDIER     UPDIE            LL_HRTIM_IsEnabledIT_UPDATE
08685   * @param  HRTIMx High Resolution Timer instance
08686   * @param  Timer This parameter can be one of the following values:
08687   *         @arg @ref LL_HRTIM_TIMER_MASTER
08688   *         @arg @ref LL_HRTIM_TIMER_A
08689   *         @arg @ref LL_HRTIM_TIMER_B
08690   *         @arg @ref LL_HRTIM_TIMER_C
08691   *         @arg @ref LL_HRTIM_TIMER_D
08692   *         @arg @ref LL_HRTIM_TIMER_E
08693   * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08694   */
08695 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08696 {
08697   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08698   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08699                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08700
08701   return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
08702 }
08703
08704 /**
08705   * @brief  Enable the repetition interrupt for a given timer.
08706   * @rmtoll MDIER        MREPIE           LL_HRTIM_EnableIT_REP\n
08707   *         TIMxDIER     REPIE            LL_HRTIM_EnableIT_REP
08708   * @param  HRTIMx High Resolution Timer instance
08709   * @param  Timer This parameter can be one of the following values:
08710   *         @arg @ref LL_HRTIM_TIMER_MASTER
08711   *         @arg @ref LL_HRTIM_TIMER_A
08712   *         @arg @ref LL_HRTIM_TIMER_B
08713   *         @arg @ref LL_HRTIM_TIMER_C
08714   *         @arg @ref LL_HRTIM_TIMER_D
08715   *         @arg @ref LL_HRTIM_TIMER_E
08716   * @retval None
08717   */
08718 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08719 {
08720   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08721   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08722                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08723   SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
08724 }
08725
08726 /**
08727   * @brief  Disable the repetition interrupt for a given timer.
08728   * @rmtoll MDIER        MREPIE           LL_HRTIM_DisableIT_REP\n
08729   *         TIMxDIER     REPIE            LL_HRTIM_DisableIT_REP
08730   * @param  HRTIMx High Resolution Timer instance
08731   * @param  Timer This parameter can be one of the following values:
08732   *         @arg @ref LL_HRTIM_TIMER_MASTER
08733   *         @arg @ref LL_HRTIM_TIMER_A
08734   *         @arg @ref LL_HRTIM_TIMER_B
08735   *         @arg @ref LL_HRTIM_TIMER_C
08736   *         @arg @ref LL_HRTIM_TIMER_D
08737   *         @arg @ref LL_HRTIM_TIMER_E
08738   * @retval None
08739   */
08740 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08741 {
08742   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08743   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08744                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08745   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
08746 }
08747
08748 /**
08749   * @brief  Indicate whether the repetition interrupt is enabled for a given timer.
08750   * @rmtoll MDIER        MREPIE           LL_HRTIM_IsEnabledIT_REP\n
08751   *         TIMxDIER     REPIE            LL_HRTIM_IsEnabledIT_REP
08752   * @param  HRTIMx High Resolution Timer instance
08753   * @param  Timer This parameter can be one of the following values:
08754   *         @arg @ref LL_HRTIM_TIMER_MASTER
08755   *         @arg @ref LL_HRTIM_TIMER_A
08756   *         @arg @ref LL_HRTIM_TIMER_B
08757   *         @arg @ref LL_HRTIM_TIMER_C
08758   *         @arg @ref LL_HRTIM_TIMER_D
08759   *         @arg @ref LL_HRTIM_TIMER_E
08760   * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08761   */
08762 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08763 {
08764   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08765   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08766                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08767
08768   return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
08769 }
08770
08771 /**
08772   * @brief  Enable the compare 1 interrupt for a given timer.
08773   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_EnableIT_CMP1\n
08774   *         TIMxDIER     CMP1IE            LL_HRTIM_EnableIT_CMP1
08775   * @param  HRTIMx High Resolution Timer instance
08776   * @param  Timer This parameter can be one of the following values:
08777   *         @arg @ref LL_HRTIM_TIMER_MASTER
08778   *         @arg @ref LL_HRTIM_TIMER_A
08779   *         @arg @ref LL_HRTIM_TIMER_B
08780   *         @arg @ref LL_HRTIM_TIMER_C
08781   *         @arg @ref LL_HRTIM_TIMER_D
08782   *         @arg @ref LL_HRTIM_TIMER_E
08783   * @retval None
08784   */
08785 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08786 {
08787   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08788   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08789                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08790   SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
08791 }
08792
08793 /**
08794   * @brief  Disable the compare 1 interrupt for a given timer.
08795   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_DisableIT_CMP1\n
08796   *         TIMxDIER     CMP1IE            LL_HRTIM_DisableIT_CMP1
08797   * @param  HRTIMx High Resolution Timer instance
08798   * @param  Timer This parameter can be one of the following values:
08799   *         @arg @ref LL_HRTIM_TIMER_MASTER
08800   *         @arg @ref LL_HRTIM_TIMER_A
08801   *         @arg @ref LL_HRTIM_TIMER_B
08802   *         @arg @ref LL_HRTIM_TIMER_C
08803   *         @arg @ref LL_HRTIM_TIMER_D
08804   *         @arg @ref LL_HRTIM_TIMER_E
08805   * @retval None
08806   */
08807 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08808 {
08809   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08810   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08811                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08812   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
08813 }
08814
08815 /**
08816   * @brief  Indicate whether the compare 1 interrupt is enabled for a given timer.
08817   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_IsEnabledIT_CMP1\n
08818   *         TIMxDIER     CMP1IE            LL_HRTIM_IsEnabledIT_CMP1
08819   * @param  HRTIMx High Resolution Timer instance
08820   * @param  Timer This parameter can be one of the following values:
08821   *         @arg @ref LL_HRTIM_TIMER_MASTER
08822   *         @arg @ref LL_HRTIM_TIMER_A
08823   *         @arg @ref LL_HRTIM_TIMER_B
08824   *         @arg @ref LL_HRTIM_TIMER_C
08825   *         @arg @ref LL_HRTIM_TIMER_D
08826   *         @arg @ref LL_HRTIM_TIMER_E
08827   * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08828   */
08829 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08830 {
08831   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08832   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08833                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08834
08835   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
08836 }
08837
08838 /**
08839   * @brief  Enable the compare 2 interrupt for a given timer.
08840   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_EnableIT_CMP2\n
08841   *         TIMxDIER     CMP2IE            LL_HRTIM_EnableIT_CMP2
08842   * @param  HRTIMx High Resolution Timer instance
08843   * @param  Timer This parameter can be one of the following values:
08844   *         @arg @ref LL_HRTIM_TIMER_MASTER
08845   *         @arg @ref LL_HRTIM_TIMER_A
08846   *         @arg @ref LL_HRTIM_TIMER_B
08847   *         @arg @ref LL_HRTIM_TIMER_C
08848   *         @arg @ref LL_HRTIM_TIMER_D
08849   *         @arg @ref LL_HRTIM_TIMER_E
08850   * @retval None
08851   */
08852 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08853 {
08854   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08855   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08856                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08857   SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
08858 }
08859
08860 /**
08861   * @brief  Disable the compare 2 interrupt for a given timer.
08862   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_DisableIT_CMP2\n
08863   *         TIMxDIER     CMP2IE            LL_HRTIM_DisableIT_CMP2
08864   * @param  HRTIMx High Resolution Timer instance
08865   * @param  Timer This parameter can be one of the following values:
08866   *         @arg @ref LL_HRTIM_TIMER_MASTER
08867   *         @arg @ref LL_HRTIM_TIMER_A
08868   *         @arg @ref LL_HRTIM_TIMER_B
08869   *         @arg @ref LL_HRTIM_TIMER_C
08870   *         @arg @ref LL_HRTIM_TIMER_D
08871   *         @arg @ref LL_HRTIM_TIMER_E
08872   * @retval None
08873   */
08874 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08875 {
08876   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08877   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08878                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08879   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
08880 }
08881
08882 /**
08883   * @brief  Indicate whether the compare 2 interrupt is enabled for a given timer.
08884   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_IsEnabledIT_CMP2\n
08885   *         TIMxDIER     CMP2IE            LL_HRTIM_IsEnabledIT_CMP2
08886   * @param  HRTIMx High Resolution Timer instance
08887   * @param  Timer This parameter can be one of the following values:
08888   *         @arg @ref LL_HRTIM_TIMER_MASTER
08889   *         @arg @ref LL_HRTIM_TIMER_A
08890   *         @arg @ref LL_HRTIM_TIMER_B
08891   *         @arg @ref LL_HRTIM_TIMER_C
08892   *         @arg @ref LL_HRTIM_TIMER_D
08893   *         @arg @ref LL_HRTIM_TIMER_E
08894   * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08895   */
08896 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08897 {
08898   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08899   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08900                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08901
08902   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
08903 }
08904
08905 /**
08906   * @brief  Enable the compare 3 interrupt for a given timer.
08907   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_EnableIT_CMP3\n
08908   *         TIMxDIER     CMP3IE            LL_HRTIM_EnableIT_CMP3
08909   * @param  HRTIMx High Resolution Timer instance
08910   * @param  Timer This parameter can be one of the following values:
08911   *         @arg @ref LL_HRTIM_TIMER_MASTER
08912   *         @arg @ref LL_HRTIM_TIMER_A
08913   *         @arg @ref LL_HRTIM_TIMER_B
08914   *         @arg @ref LL_HRTIM_TIMER_C
08915   *         @arg @ref LL_HRTIM_TIMER_D
08916   *         @arg @ref LL_HRTIM_TIMER_E
08917   * @retval None
08918   */
08919 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08920 {
08921   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08922   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08923                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08924   SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
08925 }
08926
08927 /**
08928   * @brief  Disable the compare 3 interrupt for a given timer.
08929   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_DisableIT_CMP3\n
08930   *         TIMxDIER     CMP3IE            LL_HRTIM_DisableIT_CMP3
08931   * @param  HRTIMx High Resolution Timer instance
08932   * @param  Timer This parameter can be one of the following values:
08933   *         @arg @ref LL_HRTIM_TIMER_MASTER
08934   *         @arg @ref LL_HRTIM_TIMER_A
08935   *         @arg @ref LL_HRTIM_TIMER_B
08936   *         @arg @ref LL_HRTIM_TIMER_C
08937   *         @arg @ref LL_HRTIM_TIMER_D
08938   *         @arg @ref LL_HRTIM_TIMER_E
08939   * @retval None
08940   */
08941 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08942 {
08943   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08944   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08945                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08946   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
08947 }
08948
08949 /**
08950   * @brief  Indicate whether the compare 3 interrupt is enabled for a given timer.
08951   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_IsEnabledIT_CMP3\n
08952   *         TIMxDIER     CMP3IE            LL_HRTIM_IsEnabledIT_CMP3
08953   * @param  HRTIMx High Resolution Timer instance
08954   * @param  Timer This parameter can be one of the following values:
08955   *         @arg @ref LL_HRTIM_TIMER_MASTER
08956   *         @arg @ref LL_HRTIM_TIMER_A
08957   *         @arg @ref LL_HRTIM_TIMER_B
08958   *         @arg @ref LL_HRTIM_TIMER_C
08959   *         @arg @ref LL_HRTIM_TIMER_D
08960   *         @arg @ref LL_HRTIM_TIMER_E
08961   * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
08962   */
08963 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08964 {
08965   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08966   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08967                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08968
08969   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
08970 }
08971
08972 /**
08973   * @brief  Enable the compare 4 interrupt for a given timer.
08974   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_EnableIT_CMP4\n
08975   *         TIMxDIER     CMP4IE            LL_HRTIM_EnableIT_CMP4
08976   * @param  HRTIMx High Resolution Timer instance
08977   * @param  Timer This parameter can be one of the following values:
08978   *         @arg @ref LL_HRTIM_TIMER_MASTER
08979   *         @arg @ref LL_HRTIM_TIMER_A
08980   *         @arg @ref LL_HRTIM_TIMER_B
08981   *         @arg @ref LL_HRTIM_TIMER_C
08982   *         @arg @ref LL_HRTIM_TIMER_D
08983   *         @arg @ref LL_HRTIM_TIMER_E
08984   * @retval None
08985   */
08986 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
08987 {
08988   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
08989   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
08990                                                     REG_OFFSET_TAB_TIMER[iTimer]));
08991   SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
08992 }
08993
08994 /**
08995   * @brief  Disable the compare 4 interrupt for a given timer.
08996   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_DisableIT_CMP4\n
08997   *         TIMxDIER     CMP4IE            LL_HRTIM_DisableIT_CMP4
08998   * @param  HRTIMx High Resolution Timer instance
08999   * @param  Timer This parameter can be one of the following values:
09000   *         @arg @ref LL_HRTIM_TIMER_MASTER
09001   *         @arg @ref LL_HRTIM_TIMER_A
09002   *         @arg @ref LL_HRTIM_TIMER_B
09003   *         @arg @ref LL_HRTIM_TIMER_C
09004   *         @arg @ref LL_HRTIM_TIMER_D
09005   *         @arg @ref LL_HRTIM_TIMER_E
09006   * @retval None
09007   */
09008 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09009 {
09010   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09011   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09012                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09013   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
09014 }
09015
09016 /**
09017   * @brief  Indicate whether the compare 4 interrupt is enabled for a given timer.
09018   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_IsEnabledIT_CMP4\n
09019   *         TIMxDIER     CMP4IE            LL_HRTIM_IsEnabledIT_CMP4
09020   * @param  HRTIMx High Resolution Timer instance
09021   * @param  Timer This parameter can be one of the following values:
09022   *         @arg @ref LL_HRTIM_TIMER_MASTER
09023   *         @arg @ref LL_HRTIM_TIMER_A
09024   *         @arg @ref LL_HRTIM_TIMER_B
09025   *         @arg @ref LL_HRTIM_TIMER_C
09026   *         @arg @ref LL_HRTIM_TIMER_D
09027   *         @arg @ref LL_HRTIM_TIMER_E
09028   * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09029   */
09030 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09031 {
09032   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09033   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09034                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09035
09036   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
09037 }
09038
09039 /**
09040   * @brief  Enable the capture 1 interrupt for a given timer.
09041   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_EnableIT_CPT1
09042   * @param  HRTIMx High Resolution Timer instance
09043   * @param  Timer This parameter can be one of the following values:
09044   *         @arg @ref LL_HRTIM_TIMER_A
09045   *         @arg @ref LL_HRTIM_TIMER_B
09046   *         @arg @ref LL_HRTIM_TIMER_C
09047   *         @arg @ref LL_HRTIM_TIMER_D
09048   *         @arg @ref LL_HRTIM_TIMER_E
09049   * @retval None
09050   */
09051 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09052 {
09053   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09054   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09055                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09056   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
09057 }
09058
09059 /**
09060   * @brief  Enable the capture 1 interrupt for a given timer.
09061   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_DisableIT_CPT1
09062   * @param  HRTIMx High Resolution Timer instance
09063   * @param  Timer This parameter can be one of the following values:
09064   *         @arg @ref LL_HRTIM_TIMER_A
09065   *         @arg @ref LL_HRTIM_TIMER_B
09066   *         @arg @ref LL_HRTIM_TIMER_C
09067   *         @arg @ref LL_HRTIM_TIMER_D
09068   *         @arg @ref LL_HRTIM_TIMER_E
09069   * @retval None
09070   */
09071 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09072 {
09073   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09074   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09075                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09076   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
09077 }
09078
09079 /**
09080   * @brief  Indicate whether the capture 1 interrupt is enabled for a given timer.
09081   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_IsEnabledIT_CPT1
09082   * @param  HRTIMx High Resolution Timer instance
09083   * @param  Timer This parameter can be one of the following values:
09084   *         @arg @ref LL_HRTIM_TIMER_A
09085   *         @arg @ref LL_HRTIM_TIMER_B
09086   *         @arg @ref LL_HRTIM_TIMER_C
09087   *         @arg @ref LL_HRTIM_TIMER_D
09088   *         @arg @ref LL_HRTIM_TIMER_E
09089   * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
09090   */
09091 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09092 {
09093   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09094   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09095                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09096
09097   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
09098 }
09099
09100 /**
09101   * @brief  Enable the capture 2 interrupt for a given timer.
09102   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_EnableIT_CPT2
09103   * @param  HRTIMx High Resolution Timer instance
09104   * @param  Timer This parameter can be one of the following values:
09105   *         @arg @ref LL_HRTIM_TIMER_A
09106   *         @arg @ref LL_HRTIM_TIMER_B
09107   *         @arg @ref LL_HRTIM_TIMER_C
09108   *         @arg @ref LL_HRTIM_TIMER_D
09109   *         @arg @ref LL_HRTIM_TIMER_E
09110   * @retval None
09111   */
09112 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09113 {
09114   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09115   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09116                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09117   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
09118 }
09119
09120 /**
09121   * @brief  Enable the capture 2 interrupt for a given timer.
09122   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_DisableIT_CPT2
09123   * @param  HRTIMx High Resolution Timer instance
09124   * @param  Timer This parameter can be one of the following values:
09125   *         @arg @ref LL_HRTIM_TIMER_A
09126   *         @arg @ref LL_HRTIM_TIMER_B
09127   *         @arg @ref LL_HRTIM_TIMER_C
09128   *         @arg @ref LL_HRTIM_TIMER_D
09129   *         @arg @ref LL_HRTIM_TIMER_E
09130   * @retval None
09131   */
09132 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09133 {
09134   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09135   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09136                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09137   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
09138 }
09139
09140 /**
09141   * @brief  Indicate whether the capture 2 interrupt is enabled for a given timer.
09142   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_IsEnabledIT_CPT2
09143   * @param  HRTIMx High Resolution Timer instance
09144   * @param  Timer This parameter can be one of the following values:
09145   *         @arg @ref LL_HRTIM_TIMER_A
09146   *         @arg @ref LL_HRTIM_TIMER_B
09147   *         @arg @ref LL_HRTIM_TIMER_C
09148   *         @arg @ref LL_HRTIM_TIMER_D
09149   *         @arg @ref LL_HRTIM_TIMER_E
09150   * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
09151   */
09152 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09153 {
09154   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09155   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09156                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09157
09158   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
09159 }
09160
09161 /**
09162   * @brief  Enable the output 1 set interrupt for a given timer.
09163   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_EnableIT_SET1
09164   * @param  HRTIMx High Resolution Timer instance
09165   * @param  Timer This parameter can be one of the following values:
09166   *         @arg @ref LL_HRTIM_TIMER_A
09167   *         @arg @ref LL_HRTIM_TIMER_B
09168   *         @arg @ref LL_HRTIM_TIMER_C
09169   *         @arg @ref LL_HRTIM_TIMER_D
09170   *         @arg @ref LL_HRTIM_TIMER_E
09171   * @retval None
09172   */
09173 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09174 {
09175   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09176   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09177                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09178   SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
09179 }
09180
09181 /**
09182   * @brief  Disable the output 1 set interrupt for a given timer.
09183   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_DisableIT_SET1
09184   * @param  HRTIMx High Resolution Timer instance
09185   * @param  Timer This parameter can be one of the following values:
09186   *         @arg @ref LL_HRTIM_TIMER_A
09187   *         @arg @ref LL_HRTIM_TIMER_B
09188   *         @arg @ref LL_HRTIM_TIMER_C
09189   *         @arg @ref LL_HRTIM_TIMER_D
09190   *         @arg @ref LL_HRTIM_TIMER_E
09191   * @retval None
09192   */
09193 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09194 {
09195   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09196   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09197                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09198   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
09199 }
09200
09201 /**
09202   * @brief  Indicate whether the output 1 set interrupt is enabled for a given timer.
09203   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_IsEnabledIT_SET1
09204   * @param  HRTIMx High Resolution Timer instance
09205   * @param  Timer This parameter can be one of the following values:
09206   *         @arg @ref LL_HRTIM_TIMER_A
09207   *         @arg @ref LL_HRTIM_TIMER_B
09208   *         @arg @ref LL_HRTIM_TIMER_C
09209   *         @arg @ref LL_HRTIM_TIMER_D
09210   *         @arg @ref LL_HRTIM_TIMER_E
09211   * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
09212   */
09213 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09214 {
09215   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09216   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09217                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09218
09219   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
09220 }
09221
09222 /**
09223   * @brief  Enable the output 1 reset interrupt for a given timer.
09224   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_EnableIT_RST1
09225   * @param  HRTIMx High Resolution Timer instance
09226   * @param  Timer This parameter can be one of the following values:
09227   *         @arg @ref LL_HRTIM_TIMER_A
09228   *         @arg @ref LL_HRTIM_TIMER_B
09229   *         @arg @ref LL_HRTIM_TIMER_C
09230   *         @arg @ref LL_HRTIM_TIMER_D
09231   *         @arg @ref LL_HRTIM_TIMER_E
09232   * @retval None
09233   */
09234 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09235 {
09236   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09237   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09238                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09239   SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
09240 }
09241
09242 /**
09243   * @brief  Disable the output 1 reset interrupt for a given timer.
09244   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_DisableIT_RST1
09245   * @param  HRTIMx High Resolution Timer instance
09246   * @param  Timer This parameter can be one of the following values:
09247   *         @arg @ref LL_HRTIM_TIMER_A
09248   *         @arg @ref LL_HRTIM_TIMER_B
09249   *         @arg @ref LL_HRTIM_TIMER_C
09250   *         @arg @ref LL_HRTIM_TIMER_D
09251   *         @arg @ref LL_HRTIM_TIMER_E
09252   * @retval None
09253   */
09254 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09255 {
09256   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09257   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09258                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09259   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
09260 }
09261
09262 /**
09263   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
09264   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_IsEnabledIT_RST1
09265   * @param  HRTIMx High Resolution Timer instance
09266   * @param  Timer This parameter can be one of the following values:
09267   *         @arg @ref LL_HRTIM_TIMER_A
09268   *         @arg @ref LL_HRTIM_TIMER_B
09269   *         @arg @ref LL_HRTIM_TIMER_C
09270   *         @arg @ref LL_HRTIM_TIMER_D
09271   *         @arg @ref LL_HRTIM_TIMER_E
09272   * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
09273   */
09274 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09275 {
09276   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09277   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09278                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09279
09280   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
09281 }
09282
09283 /**
09284   * @brief  Enable the output 2 set interrupt for a given timer.
09285   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_EnableIT_SET2
09286   * @param  HRTIMx High Resolution Timer instance
09287   * @param  Timer This parameter can be one of the following values:
09288   *         @arg @ref LL_HRTIM_TIMER_A
09289   *         @arg @ref LL_HRTIM_TIMER_B
09290   *         @arg @ref LL_HRTIM_TIMER_C
09291   *         @arg @ref LL_HRTIM_TIMER_D
09292   *         @arg @ref LL_HRTIM_TIMER_E
09293   * @retval None
09294   */
09295 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09296 {
09297   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09298   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09299                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09300   SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
09301 }
09302
09303 /**
09304   * @brief  Disable the output 2 set interrupt for a given timer.
09305   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_DisableIT_SET2
09306   * @param  HRTIMx High Resolution Timer instance
09307   * @param  Timer This parameter can be one of the following values:
09308   *         @arg @ref LL_HRTIM_TIMER_A
09309   *         @arg @ref LL_HRTIM_TIMER_B
09310   *         @arg @ref LL_HRTIM_TIMER_C
09311   *         @arg @ref LL_HRTIM_TIMER_D
09312   *         @arg @ref LL_HRTIM_TIMER_E
09313   * @retval None
09314   */
09315 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09316 {
09317   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09318   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09319                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09320   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
09321 }
09322
09323 /**
09324   * @brief  Indicate whether the output 2 set interrupt is enabled for a given timer.
09325   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_IsEnabledIT_SET2
09326   * @param  HRTIMx High Resolution Timer instance
09327   * @param  Timer This parameter can be one of the following values:
09328   *         @arg @ref LL_HRTIM_TIMER_A
09329   *         @arg @ref LL_HRTIM_TIMER_B
09330   *         @arg @ref LL_HRTIM_TIMER_C
09331   *         @arg @ref LL_HRTIM_TIMER_D
09332   *         @arg @ref LL_HRTIM_TIMER_E
09333   * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
09334   */
09335 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09336 {
09337   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09338   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09339                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09340
09341   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
09342 }
09343
09344 /**
09345   * @brief  Enable the output 2 reset interrupt for a given timer.
09346   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_EnableIT_RST2
09347   * @param  HRTIMx High Resolution Timer instance
09348   * @param  Timer This parameter can be one of the following values:
09349   *         @arg @ref LL_HRTIM_TIMER_A
09350   *         @arg @ref LL_HRTIM_TIMER_B
09351   *         @arg @ref LL_HRTIM_TIMER_C
09352   *         @arg @ref LL_HRTIM_TIMER_D
09353   *         @arg @ref LL_HRTIM_TIMER_E
09354   * @retval None
09355   */
09356 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09357 {
09358   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09359   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09360                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09361   SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
09362 }
09363
09364 /**
09365   * @brief  Disable the output 2 reset interrupt for a given timer.
09366   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
09367   * @param  HRTIMx High Resolution Timer instance
09368   * @param  Timer This parameter can be one of the following values:
09369   *         @arg @ref LL_HRTIM_TIMER_A
09370   *         @arg @ref LL_HRTIM_TIMER_B
09371   *         @arg @ref LL_HRTIM_TIMER_C
09372   *         @arg @ref LL_HRTIM_TIMER_D
09373   *         @arg @ref LL_HRTIM_TIMER_E
09374   * @retval None
09375   */
09376 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09377 {
09378   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09379   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09380                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09381   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
09382 }
09383
09384 /**
09385   * @brief  Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
09386   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
09387   * @param  HRTIMx High Resolution Timer instance
09388   * @param  Timer This parameter can be one of the following values:
09389   *         @arg @ref LL_HRTIM_TIMER_A
09390   *         @arg @ref LL_HRTIM_TIMER_B
09391   *         @arg @ref LL_HRTIM_TIMER_C
09392   *         @arg @ref LL_HRTIM_TIMER_D
09393   *         @arg @ref LL_HRTIM_TIMER_E
09394   * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
09395   */
09396 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09397 {
09398   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09399   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09400                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09401
09402   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
09403 }
09404
09405 /**
09406   * @brief  Enable the reset/roll-over interrupt for a given timer.
09407   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_EnableIT_RST
09408   * @param  HRTIMx High Resolution Timer instance
09409   * @param  Timer This parameter can be one of the following values:
09410   *         @arg @ref LL_HRTIM_TIMER_A
09411   *         @arg @ref LL_HRTIM_TIMER_B
09412   *         @arg @ref LL_HRTIM_TIMER_C
09413   *         @arg @ref LL_HRTIM_TIMER_D
09414   *         @arg @ref LL_HRTIM_TIMER_E
09415   * @retval None
09416   */
09417 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09418 {
09419   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09420   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09421                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09422   SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
09423 }
09424
09425 /**
09426   * @brief  Disable the reset/roll-over interrupt for a given timer.
09427   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_DisableIT_RST
09428   * @param  HRTIMx High Resolution Timer instance
09429   * @param  Timer This parameter can be one of the following values:
09430   *         @arg @ref LL_HRTIM_TIMER_A
09431   *         @arg @ref LL_HRTIM_TIMER_B
09432   *         @arg @ref LL_HRTIM_TIMER_C
09433   *         @arg @ref LL_HRTIM_TIMER_D
09434   *         @arg @ref LL_HRTIM_TIMER_E
09435   * @retval None
09436   */
09437 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09438 {
09439   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09440   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09441                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09442   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
09443 }
09444
09445 /**
09446   * @brief  Indicate whether the reset/roll-over interrupt is enabled for a given timer.
09447   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_IsEnabledIT_RST
09448   * @param  HRTIMx High Resolution Timer instance
09449   * @param  Timer This parameter can be one of the following values:
09450   *         @arg @ref LL_HRTIM_TIMER_A
09451   *         @arg @ref LL_HRTIM_TIMER_B
09452   *         @arg @ref LL_HRTIM_TIMER_C
09453   *         @arg @ref LL_HRTIM_TIMER_D
09454   *         @arg @ref LL_HRTIM_TIMER_E
09455   * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
09456   */
09457 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09458 {
09459   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09460   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09461                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09462
09463   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
09464 }
09465
09466 /**
09467   * @brief  Enable the delayed protection interrupt for a given timer.
09468   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_EnableIT_DLYPRT
09469   * @param  HRTIMx High Resolution Timer instance
09470   * @param  Timer This parameter can be one of the following values:
09471   *         @arg @ref LL_HRTIM_TIMER_A
09472   *         @arg @ref LL_HRTIM_TIMER_B
09473   *         @arg @ref LL_HRTIM_TIMER_C
09474   *         @arg @ref LL_HRTIM_TIMER_D
09475   *         @arg @ref LL_HRTIM_TIMER_E
09476   * @retval None
09477   */
09478 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09479 {
09480   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09481   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09482                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09483   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
09484 }
09485
09486 /**
09487   * @brief  Disable the delayed protection interrupt for a given timer.
09488   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_DisableIT_DLYPRT
09489   * @param  HRTIMx High Resolution Timer instance
09490   * @param  Timer This parameter can be one of the following values:
09491   *         @arg @ref LL_HRTIM_TIMER_A
09492   *         @arg @ref LL_HRTIM_TIMER_B
09493   *         @arg @ref LL_HRTIM_TIMER_C
09494   *         @arg @ref LL_HRTIM_TIMER_D
09495   *         @arg @ref LL_HRTIM_TIMER_E
09496   * @retval None
09497   */
09498 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09499 {
09500   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09501   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09502                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09503   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
09504 }
09505
09506 /**
09507   * @brief  Indicate whether the delayed protection interrupt is enabled for a given timer.
09508   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_IsEnabledIT_DLYPRT
09509   * @param  HRTIMx High Resolution Timer instance
09510   * @param  Timer This parameter can be one of the following values:
09511   *         @arg @ref LL_HRTIM_TIMER_A
09512   *         @arg @ref LL_HRTIM_TIMER_B
09513   *         @arg @ref LL_HRTIM_TIMER_C
09514   *         @arg @ref LL_HRTIM_TIMER_D
09515   *         @arg @ref LL_HRTIM_TIMER_E
09516   * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
09517   */
09518 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09519 {
09520   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09521   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09522                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09523
09524   return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
09525 }
09526
09527 /**
09528   * @}
09529   */
09530
09531 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
09532   * @{
09533   */
09534
09535 /**
09536   * @brief  Enable the synchronization input DMA request.
09537   * @rmtoll MDIER     SYNCDE            LL_HRTIM_EnableDMAReq_SYNC
09538   * @param  HRTIMx High Resolution Timer instance
09539   * @retval None
09540   */
09541 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09542 {
09543   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
09544 }
09545
09546 /**
09547   * @brief  Disable the synchronization input DMA request
09548   * @rmtoll MDIER     SYNCDE            LL_HRTIM_DisableDMAReq_SYNC
09549   * @param  HRTIMx High Resolution Timer instance
09550   * @retval None
09551   */
09552 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09553 {
09554   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
09555 }
09556
09557 /**
09558   * @brief  Indicate whether the synchronization input DMA request is enabled.
09559   * @rmtoll MDIER     SYNCDE            LL_HRTIM_IsEnabledDMAReq_SYNC
09560   * @param  HRTIMx High Resolution Timer instance
09561   * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
09562   */
09563 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
09564 {
09565   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
09566 }
09567
09568 /**
09569   * @brief  Enable the update DMA request for a given timer.
09570   * @rmtoll MDIER        MUPDDE            LL_HRTIM_EnableDMAReq_UPDATE\n
09571   *         TIMxDIER     UPDDE             LL_HRTIM_EnableDMAReq_UPDATE
09572   * @param  HRTIMx High Resolution Timer instance
09573   * @param  Timer This parameter can be one of the following values:
09574   *         @arg @ref LL_HRTIM_TIMER_MASTER
09575   *         @arg @ref LL_HRTIM_TIMER_A
09576   *         @arg @ref LL_HRTIM_TIMER_B
09577   *         @arg @ref LL_HRTIM_TIMER_C
09578   *         @arg @ref LL_HRTIM_TIMER_D
09579   *         @arg @ref LL_HRTIM_TIMER_E
09580   * @retval None
09581   */
09582 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09583 {
09584   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09585   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09586                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09587   SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
09588 }
09589
09590 /**
09591   * @brief  Disable the update DMA request for a given timer.
09592   * @rmtoll MDIER        MUPDDE            LL_HRTIM_DisableDMAReq_UPDATE\n
09593   *         TIMxDIER     UPDDE             LL_HRTIM_DisableDMAReq_UPDATE
09594   * @param  HRTIMx High Resolution Timer instance
09595   * @param  Timer This parameter can be one of the following values:
09596   *         @arg @ref LL_HRTIM_TIMER_MASTER
09597   *         @arg @ref LL_HRTIM_TIMER_A
09598   *         @arg @ref LL_HRTIM_TIMER_B
09599   *         @arg @ref LL_HRTIM_TIMER_C
09600   *         @arg @ref LL_HRTIM_TIMER_D
09601   *         @arg @ref LL_HRTIM_TIMER_E
09602   * @retval None
09603   */
09604 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09605 {
09606   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09607   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09608                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09609   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
09610 }
09611
09612 /**
09613   * @brief  Indicate whether the update DMA request is enabled for a given timer.
09614   * @rmtoll MDIER        MUPDDE            LL_HRTIM_IsEnabledDMAReq_UPDATE\n
09615   *         TIMxDIER     UPDDE             LL_HRTIM_IsEnabledDMAReq_UPDATE
09616   * @param  HRTIMx High Resolution Timer instance
09617   * @param  Timer This parameter can be one of the following values:
09618   *         @arg @ref LL_HRTIM_TIMER_MASTER
09619   *         @arg @ref LL_HRTIM_TIMER_A
09620   *         @arg @ref LL_HRTIM_TIMER_B
09621   *         @arg @ref LL_HRTIM_TIMER_C
09622   *         @arg @ref LL_HRTIM_TIMER_D
09623   *         @arg @ref LL_HRTIM_TIMER_E
09624   * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09625   */
09626 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09627 {
09628   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09629   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09630                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09631
09632   return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
09633 }
09634
09635 /**
09636   * @brief  Enable the repetition DMA request for a given timer.
09637   * @rmtoll MDIER        MREPDE            LL_HRTIM_EnableDMAReq_REP\n
09638   *         TIMxDIER     REPDE             LL_HRTIM_EnableDMAReq_REP
09639   * @param  HRTIMx High Resolution Timer instance
09640   * @param  Timer This parameter can be one of the following values:
09641   *         @arg @ref LL_HRTIM_TIMER_MASTER
09642   *         @arg @ref LL_HRTIM_TIMER_A
09643   *         @arg @ref LL_HRTIM_TIMER_B
09644   *         @arg @ref LL_HRTIM_TIMER_C
09645   *         @arg @ref LL_HRTIM_TIMER_D
09646   *         @arg @ref LL_HRTIM_TIMER_E
09647   * @retval None
09648   */
09649 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09650 {
09651   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09652   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09653                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09654   SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
09655 }
09656
09657 /**
09658   * @brief  Disable the repetition DMA request for a given timer.
09659   * @rmtoll MDIER        MREPDE            LL_HRTIM_DisableDMAReq_REP\n
09660   *         TIMxDIER     REPDE             LL_HRTIM_DisableDMAReq_REP
09661   * @param  HRTIMx High Resolution Timer instance
09662   * @param  Timer This parameter can be one of the following values:
09663   *         @arg @ref LL_HRTIM_TIMER_MASTER
09664   *         @arg @ref LL_HRTIM_TIMER_A
09665   *         @arg @ref LL_HRTIM_TIMER_B
09666   *         @arg @ref LL_HRTIM_TIMER_C
09667   *         @arg @ref LL_HRTIM_TIMER_D
09668   *         @arg @ref LL_HRTIM_TIMER_E
09669   * @retval None
09670   */
09671 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09672 {
09673   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09674   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09675                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09676   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
09677 }
09678
09679 /**
09680   * @brief  Indicate whether the repetition DMA request is enabled for a given timer.
09681   * @rmtoll MDIER        MREPDE            LL_HRTIM_IsEnabledDMAReq_REP\n
09682   *         TIMxDIER     REPDE             LL_HRTIM_IsEnabledDMAReq_REP
09683   * @param  HRTIMx High Resolution Timer instance
09684   * @param  Timer This parameter can be one of the following values:
09685   *         @arg @ref LL_HRTIM_TIMER_MASTER
09686   *         @arg @ref LL_HRTIM_TIMER_A
09687   *         @arg @ref LL_HRTIM_TIMER_B
09688   *         @arg @ref LL_HRTIM_TIMER_C
09689   *         @arg @ref LL_HRTIM_TIMER_D
09690   *         @arg @ref LL_HRTIM_TIMER_E
09691   * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09692   */
09693 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09694 {
09695   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09696   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09697                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09698
09699   return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
09700 }
09701
09702 /**
09703   * @brief  Enable the compare 1 DMA request for a given timer.
09704   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_EnableDMAReq_CMP1\n
09705   *         TIMxDIER     CMP1DE             LL_HRTIM_EnableDMAReq_CMP1
09706   * @param  HRTIMx High Resolution Timer instance
09707   * @param  Timer This parameter can be one of the following values:
09708   *         @arg @ref LL_HRTIM_TIMER_MASTER
09709   *         @arg @ref LL_HRTIM_TIMER_A
09710   *         @arg @ref LL_HRTIM_TIMER_B
09711   *         @arg @ref LL_HRTIM_TIMER_C
09712   *         @arg @ref LL_HRTIM_TIMER_D
09713   *         @arg @ref LL_HRTIM_TIMER_E
09714   * @retval None
09715   */
09716 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09717 {
09718   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09719   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09720                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09721   SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
09722 }
09723
09724 /**
09725   * @brief  Disable the compare 1 DMA request for a given timer.
09726   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_DisableDMAReq_CMP1\n
09727   *         TIMxDIER     CMP1DE             LL_HRTIM_DisableDMAReq_CMP1
09728   * @param  HRTIMx High Resolution Timer instance
09729   * @param  Timer This parameter can be one of the following values:
09730   *         @arg @ref LL_HRTIM_TIMER_MASTER
09731   *         @arg @ref LL_HRTIM_TIMER_A
09732   *         @arg @ref LL_HRTIM_TIMER_B
09733   *         @arg @ref LL_HRTIM_TIMER_C
09734   *         @arg @ref LL_HRTIM_TIMER_D
09735   *         @arg @ref LL_HRTIM_TIMER_E
09736   * @retval None
09737   */
09738 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09739 {
09740   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09741   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09742                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09743   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
09744 }
09745
09746 /**
09747   * @brief  Indicate whether the compare 1 DMA request is enabled for a given timer.
09748   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_IsEnabledDMAReq_CMP1\n
09749   *         TIMxDIER     CMP1DE             LL_HRTIM_IsEnabledDMAReq_CMP1
09750   * @param  HRTIMx High Resolution Timer instance
09751   * @param  Timer This parameter can be one of the following values:
09752   *         @arg @ref LL_HRTIM_TIMER_MASTER
09753   *         @arg @ref LL_HRTIM_TIMER_A
09754   *         @arg @ref LL_HRTIM_TIMER_B
09755   *         @arg @ref LL_HRTIM_TIMER_C
09756   *         @arg @ref LL_HRTIM_TIMER_D
09757   *         @arg @ref LL_HRTIM_TIMER_E
09758   * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09759   */
09760 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09761 {
09762   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09763   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09764                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09765
09766   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
09767 }
09768
09769 /**
09770   * @brief  Enable the compare 2 DMA request for a given timer.
09771   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_EnableDMAReq_CMP2\n
09772   *         TIMxDIER     CMP2DE             LL_HRTIM_EnableDMAReq_CMP2
09773   * @param  HRTIMx High Resolution Timer instance
09774   * @param  Timer This parameter can be one of the following values:
09775   *         @arg @ref LL_HRTIM_TIMER_MASTER
09776   *         @arg @ref LL_HRTIM_TIMER_A
09777   *         @arg @ref LL_HRTIM_TIMER_B
09778   *         @arg @ref LL_HRTIM_TIMER_C
09779   *         @arg @ref LL_HRTIM_TIMER_D
09780   *         @arg @ref LL_HRTIM_TIMER_E
09781   * @retval None
09782   */
09783 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09784 {
09785   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09786   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09787                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09788   SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
09789 }
09790
09791 /**
09792   * @brief  Disable the compare 2 DMA request for a given timer.
09793   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_DisableDMAReq_CMP2\n
09794   *         TIMxDIER     CMP2DE             LL_HRTIM_DisableDMAReq_CMP2
09795   * @param  HRTIMx High Resolution Timer instance
09796   * @param  Timer This parameter can be one of the following values:
09797   *         @arg @ref LL_HRTIM_TIMER_MASTER
09798   *         @arg @ref LL_HRTIM_TIMER_A
09799   *         @arg @ref LL_HRTIM_TIMER_B
09800   *         @arg @ref LL_HRTIM_TIMER_C
09801   *         @arg @ref LL_HRTIM_TIMER_D
09802   *         @arg @ref LL_HRTIM_TIMER_E
09803   * @retval None
09804   */
09805 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09806 {
09807   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09808   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09809                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09810   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
09811 }
09812
09813 /**
09814   * @brief  Indicate whether the compare 2 DMA request is enabled for a given timer.
09815   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_IsEnabledDMAReq_CMP2\n
09816   *         TIMxDIER     CMP2DE             LL_HRTIM_IsEnabledDMAReq_CMP2
09817   * @param  HRTIMx High Resolution Timer instance
09818   * @param  Timer This parameter can be one of the following values:
09819   *         @arg @ref LL_HRTIM_TIMER_MASTER
09820   *         @arg @ref LL_HRTIM_TIMER_A
09821   *         @arg @ref LL_HRTIM_TIMER_B
09822   *         @arg @ref LL_HRTIM_TIMER_C
09823   *         @arg @ref LL_HRTIM_TIMER_D
09824   *         @arg @ref LL_HRTIM_TIMER_E
09825   * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09826   */
09827 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09828 {
09829   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09830   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09831                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09832
09833   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
09834 }
09835
09836 /**
09837   * @brief  Enable the compare 3 DMA request for a given timer.
09838   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_EnableDMAReq_CMP3\n
09839   *         TIMxDIER     CMP3DE             LL_HRTIM_EnableDMAReq_CMP3
09840   * @param  HRTIMx High Resolution Timer instance
09841   * @param  Timer This parameter can be one of the following values:
09842   *         @arg @ref LL_HRTIM_TIMER_MASTER
09843   *         @arg @ref LL_HRTIM_TIMER_A
09844   *         @arg @ref LL_HRTIM_TIMER_B
09845   *         @arg @ref LL_HRTIM_TIMER_C
09846   *         @arg @ref LL_HRTIM_TIMER_D
09847   *         @arg @ref LL_HRTIM_TIMER_E
09848   * @retval None
09849   */
09850 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09851 {
09852   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09853   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09854                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09855   SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
09856 }
09857
09858 /**
09859   * @brief  Disable the compare 3 DMA request for a given timer.
09860   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_DisableDMAReq_CMP3\n
09861   *         TIMxDIER     CMP3DE             LL_HRTIM_DisableDMAReq_CMP3
09862   * @param  HRTIMx High Resolution Timer instance
09863   * @param  Timer This parameter can be one of the following values:
09864   *         @arg @ref LL_HRTIM_TIMER_MASTER
09865   *         @arg @ref LL_HRTIM_TIMER_A
09866   *         @arg @ref LL_HRTIM_TIMER_B
09867   *         @arg @ref LL_HRTIM_TIMER_C
09868   *         @arg @ref LL_HRTIM_TIMER_D
09869   *         @arg @ref LL_HRTIM_TIMER_E
09870   * @retval None
09871   */
09872 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09873 {
09874   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09875   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09876                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09877   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
09878 }
09879
09880 /**
09881   * @brief  Indicate whether the compare 3 DMA request is enabled for a given timer.
09882   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_IsEnabledDMAReq_CMP3\n
09883   *         TIMxDIER     CMP3DE             LL_HRTIM_IsEnabledDMAReq_CMP3
09884   * @param  HRTIMx High Resolution Timer instance
09885   * @param  Timer This parameter can be one of the following values:
09886   *         @arg @ref LL_HRTIM_TIMER_MASTER
09887   *         @arg @ref LL_HRTIM_TIMER_A
09888   *         @arg @ref LL_HRTIM_TIMER_B
09889   *         @arg @ref LL_HRTIM_TIMER_C
09890   *         @arg @ref LL_HRTIM_TIMER_D
09891   *         @arg @ref LL_HRTIM_TIMER_E
09892   * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09893   */
09894 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09895 {
09896   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09897   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09898                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09899
09900   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
09901 }
09902
09903 /**
09904   * @brief  Enable the compare 4 DMA request for a given timer.
09905   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_EnableDMAReq_CMP4\n
09906   *         TIMxDIER     CMP4DE             LL_HRTIM_EnableDMAReq_CMP4
09907   * @param  HRTIMx High Resolution Timer instance
09908   * @param  Timer This parameter can be one of the following values:
09909   *         @arg @ref LL_HRTIM_TIMER_MASTER
09910   *         @arg @ref LL_HRTIM_TIMER_A
09911   *         @arg @ref LL_HRTIM_TIMER_B
09912   *         @arg @ref LL_HRTIM_TIMER_C
09913   *         @arg @ref LL_HRTIM_TIMER_D
09914   *         @arg @ref LL_HRTIM_TIMER_E
09915   * @retval None
09916   */
09917 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09918 {
09919   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09920   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09921                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09922   SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
09923 }
09924
09925 /**
09926   * @brief  Disable the compare 4 DMA request for a given timer.
09927   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_DisableDMAReq_CMP4\n
09928   *         TIMxDIER     CMP4DE             LL_HRTIM_DisableDMAReq_CMP4
09929   * @param  HRTIMx High Resolution Timer instance
09930   * @param  Timer This parameter can be one of the following values:
09931   *         @arg @ref LL_HRTIM_TIMER_MASTER
09932   *         @arg @ref LL_HRTIM_TIMER_A
09933   *         @arg @ref LL_HRTIM_TIMER_B
09934   *         @arg @ref LL_HRTIM_TIMER_C
09935   *         @arg @ref LL_HRTIM_TIMER_D
09936   *         @arg @ref LL_HRTIM_TIMER_E
09937   * @retval None
09938   */
09939 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09940 {
09941   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09942   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09943                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09944   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
09945 }
09946
09947 /**
09948   * @brief  Indicate whether the compare 4 DMA request is enabled for a given timer.
09949   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_IsEnabledDMAReq_CMP4\n
09950   *         TIMxDIER     CMP4DE             LL_HRTIM_IsEnabledDMAReq_CMP4
09951   * @param  HRTIMx High Resolution Timer instance
09952   * @param  Timer This parameter can be one of the following values:
09953   *         @arg @ref LL_HRTIM_TIMER_MASTER
09954   *         @arg @ref LL_HRTIM_TIMER_A
09955   *         @arg @ref LL_HRTIM_TIMER_B
09956   *         @arg @ref LL_HRTIM_TIMER_C
09957   *         @arg @ref LL_HRTIM_TIMER_D
09958   *         @arg @ref LL_HRTIM_TIMER_E
09959   * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
09960   */
09961 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09962 {
09963   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09964   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09965                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09966
09967   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
09968 }
09969
09970 /**
09971   * @brief  Enable the capture 1 DMA request for a given timer.
09972   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_EnableDMAReq_CPT1
09973   * @param  HRTIMx High Resolution Timer instance
09974   * @param  Timer This parameter can be one of the following values:
09975   *         @arg @ref LL_HRTIM_TIMER_A
09976   *         @arg @ref LL_HRTIM_TIMER_B
09977   *         @arg @ref LL_HRTIM_TIMER_C
09978   *         @arg @ref LL_HRTIM_TIMER_D
09979   *         @arg @ref LL_HRTIM_TIMER_E
09980   * @retval None
09981   */
09982 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
09983 {
09984   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
09985   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
09986                                                     REG_OFFSET_TAB_TIMER[iTimer]));
09987   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
09988 }
09989
09990 /**
09991   * @brief  Disable the capture 1 DMA request for a given timer.
09992   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_DisableDMAReq_CPT1
09993   * @param  HRTIMx High Resolution Timer instance
09994   * @param  Timer This parameter can be one of the following values:
09995   *         @arg @ref LL_HRTIM_TIMER_A
09996   *         @arg @ref LL_HRTIM_TIMER_B
09997   *         @arg @ref LL_HRTIM_TIMER_C
09998   *         @arg @ref LL_HRTIM_TIMER_D
09999   *         @arg @ref LL_HRTIM_TIMER_E
10000   * @retval None
10001   */
10002 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10003 {
10004   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10005   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10006                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10007   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
10008 }
10009
10010 /**
10011   * @brief  Indicate whether the capture 1 DMA request is enabled for a given timer.
10012   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_IsEnabledDMAReq_CPT1
10013   * @param  HRTIMx High Resolution Timer instance
10014   * @param  Timer This parameter can be one of the following values:
10015   *         @arg @ref LL_HRTIM_TIMER_A
10016   *         @arg @ref LL_HRTIM_TIMER_B
10017   *         @arg @ref LL_HRTIM_TIMER_C
10018   *         @arg @ref LL_HRTIM_TIMER_D
10019   *         @arg @ref LL_HRTIM_TIMER_E
10020   * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
10021   */
10022 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10023 {
10024   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10025   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10026                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10027
10028   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
10029 }
10030
10031 /**
10032   * @brief  Enable the capture 2 DMA request for a given timer.
10033   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_EnableDMAReq_CPT2
10034   * @param  HRTIMx High Resolution Timer instance
10035   * @param  Timer This parameter can be one of the following values:
10036   *         @arg @ref LL_HRTIM_TIMER_A
10037   *         @arg @ref LL_HRTIM_TIMER_B
10038   *         @arg @ref LL_HRTIM_TIMER_C
10039   *         @arg @ref LL_HRTIM_TIMER_D
10040   *         @arg @ref LL_HRTIM_TIMER_E
10041   * @retval None
10042   */
10043 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10044 {
10045   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10046   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10047                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10048   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10049 }
10050
10051 /**
10052   * @brief  Disable the capture 2 DMA request for a given timer.
10053   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_DisableDMAReq_CPT2
10054   * @param  HRTIMx High Resolution Timer instance
10055   * @param  Timer This parameter can be one of the following values:
10056   *         @arg @ref LL_HRTIM_TIMER_A
10057   *         @arg @ref LL_HRTIM_TIMER_B
10058   *         @arg @ref LL_HRTIM_TIMER_C
10059   *         @arg @ref LL_HRTIM_TIMER_D
10060   *         @arg @ref LL_HRTIM_TIMER_E
10061   * @retval None
10062   */
10063 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10064 {
10065   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10066   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10067                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10068   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10069 }
10070
10071 /**
10072   * @brief  Indicate whether the capture 2 DMA request is enabled for a given timer.
10073   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_IsEnabledDMAReq_CPT2
10074   * @param  HRTIMx High Resolution Timer instance
10075   * @param  Timer This parameter can be one of the following values:
10076   *         @arg @ref LL_HRTIM_TIMER_A
10077   *         @arg @ref LL_HRTIM_TIMER_B
10078   *         @arg @ref LL_HRTIM_TIMER_C
10079   *         @arg @ref LL_HRTIM_TIMER_D
10080   *         @arg @ref LL_HRTIM_TIMER_E
10081   * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
10082   */
10083 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10084 {
10085   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10086   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10087                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10088
10089   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
10090 }
10091
10092 /**
10093   * @brief  Enable the output 1 set  DMA request for a given timer.
10094   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_EnableDMAReq_SET1
10095   * @param  HRTIMx High Resolution Timer instance
10096   * @param  Timer This parameter can be one of the following values:
10097   *         @arg @ref LL_HRTIM_TIMER_A
10098   *         @arg @ref LL_HRTIM_TIMER_B
10099   *         @arg @ref LL_HRTIM_TIMER_C
10100   *         @arg @ref LL_HRTIM_TIMER_D
10101   *         @arg @ref LL_HRTIM_TIMER_E
10102   * @retval None
10103   */
10104 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10105 {
10106   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10107   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10108                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10109   SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10110 }
10111
10112 /**
10113   * @brief  Disable the output 1 set  DMA request for a given timer.
10114   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_DisableDMAReq_SET1
10115   * @param  HRTIMx High Resolution Timer instance
10116   * @param  Timer This parameter can be one of the following values:
10117   *         @arg @ref LL_HRTIM_TIMER_A
10118   *         @arg @ref LL_HRTIM_TIMER_B
10119   *         @arg @ref LL_HRTIM_TIMER_C
10120   *         @arg @ref LL_HRTIM_TIMER_D
10121   *         @arg @ref LL_HRTIM_TIMER_E
10122   * @retval None
10123   */
10124 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10125 {
10126   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10127   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10128                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10129   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10130 }
10131
10132 /**
10133   * @brief  Indicate whether the output 1 set  DMA request is enabled for a given timer.
10134   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_IsEnabledDMAReq_SET1
10135   * @param  HRTIMx High Resolution Timer instance
10136   * @param  Timer This parameter can be one of the following values:
10137   *         @arg @ref LL_HRTIM_TIMER_A
10138   *         @arg @ref LL_HRTIM_TIMER_B
10139   *         @arg @ref LL_HRTIM_TIMER_C
10140   *         @arg @ref LL_HRTIM_TIMER_D
10141   *         @arg @ref LL_HRTIM_TIMER_E
10142   * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10143   */
10144 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10145 {
10146   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10147   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10148                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10149
10150   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
10151 }
10152
10153 /**
10154   * @brief  Enable the output 1 reset  DMA request for a given timer.
10155   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_EnableDMAReq_RST1
10156   * @param  HRTIMx High Resolution Timer instance
10157   * @param  Timer This parameter can be one of the following values:
10158   *         @arg @ref LL_HRTIM_TIMER_A
10159   *         @arg @ref LL_HRTIM_TIMER_B
10160   *         @arg @ref LL_HRTIM_TIMER_C
10161   *         @arg @ref LL_HRTIM_TIMER_D
10162   *         @arg @ref LL_HRTIM_TIMER_E
10163   * @retval None
10164   */
10165 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10166 {
10167   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10168   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10169                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10170   SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10171 }
10172
10173 /**
10174   * @brief  Disable the output 1 reset  DMA request for a given timer.
10175   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_DisableDMAReq_RST1
10176   * @param  HRTIMx High Resolution Timer instance
10177   * @param  Timer This parameter can be one of the following values:
10178   *         @arg @ref LL_HRTIM_TIMER_A
10179   *         @arg @ref LL_HRTIM_TIMER_B
10180   *         @arg @ref LL_HRTIM_TIMER_C
10181   *         @arg @ref LL_HRTIM_TIMER_D
10182   *         @arg @ref LL_HRTIM_TIMER_E
10183   * @retval None
10184   */
10185 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10186 {
10187   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10188   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10189                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10190   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10191 }
10192
10193 /**
10194   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
10195   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_IsEnabledDMAReq_RST1
10196   * @param  HRTIMx High Resolution Timer instance
10197   * @param  Timer This parameter can be one of the following values:
10198   *         @arg @ref LL_HRTIM_TIMER_A
10199   *         @arg @ref LL_HRTIM_TIMER_B
10200   *         @arg @ref LL_HRTIM_TIMER_C
10201   *         @arg @ref LL_HRTIM_TIMER_D
10202   *         @arg @ref LL_HRTIM_TIMER_E
10203   * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10204   */
10205 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10206 {
10207   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10208   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10209                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10210
10211   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
10212 }
10213
10214 /**
10215   * @brief  Enable the output 2 set  DMA request for a given timer.
10216   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_EnableDMAReq_SET2
10217   * @param  HRTIMx High Resolution Timer instance
10218   * @param  Timer This parameter can be one of the following values:
10219   *         @arg @ref LL_HRTIM_TIMER_A
10220   *         @arg @ref LL_HRTIM_TIMER_B
10221   *         @arg @ref LL_HRTIM_TIMER_C
10222   *         @arg @ref LL_HRTIM_TIMER_D
10223   *         @arg @ref LL_HRTIM_TIMER_E
10224   * @retval None
10225   */
10226 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10227 {
10228   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10229   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10230                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10231   SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10232 }
10233
10234 /**
10235   * @brief  Disable the output 2 set  DMA request for a given timer.
10236   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_DisableDMAReq_SET2
10237   * @param  HRTIMx High Resolution Timer instance
10238   * @param  Timer This parameter can be one of the following values:
10239   *         @arg @ref LL_HRTIM_TIMER_A
10240   *         @arg @ref LL_HRTIM_TIMER_B
10241   *         @arg @ref LL_HRTIM_TIMER_C
10242   *         @arg @ref LL_HRTIM_TIMER_D
10243   *         @arg @ref LL_HRTIM_TIMER_E
10244   * @retval None
10245   */
10246 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10247 {
10248   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10249   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10250                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10251   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10252 }
10253
10254 /**
10255   * @brief  Indicate whether the output 2 set  DMA request is enabled for a given timer.
10256   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_IsEnabledDMAReq_SET2
10257   * @param  HRTIMx High Resolution Timer instance
10258   * @param  Timer This parameter can be one of the following values:
10259   *         @arg @ref LL_HRTIM_TIMER_A
10260   *         @arg @ref LL_HRTIM_TIMER_B
10261   *         @arg @ref LL_HRTIM_TIMER_C
10262   *         @arg @ref LL_HRTIM_TIMER_D
10263   *         @arg @ref LL_HRTIM_TIMER_E
10264   * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10265   */
10266 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10267 {
10268   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10269   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10270                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10271
10272   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
10273 }
10274
10275 /**
10276   * @brief  Enable the output 2 reset  DMA request for a given timer.
10277   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_EnableDMAReq_RST2
10278   * @param  HRTIMx High Resolution Timer instance
10279   * @param  Timer This parameter can be one of the following values:
10280   *         @arg @ref LL_HRTIM_TIMER_A
10281   *         @arg @ref LL_HRTIM_TIMER_B
10282   *         @arg @ref LL_HRTIM_TIMER_C
10283   *         @arg @ref LL_HRTIM_TIMER_D
10284   *         @arg @ref LL_HRTIM_TIMER_E
10285   * @retval None
10286   */
10287 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10288 {
10289   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10290   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10291                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10292   SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10293 }
10294
10295 /**
10296   * @brief  Disable the output 2 reset  DMA request for a given timer.
10297   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_DisableDMAReq_RST2
10298   * @param  HRTIMx High Resolution Timer instance
10299   * @param  Timer This parameter can be one of the following values:
10300   *         @arg @ref LL_HRTIM_TIMER_A
10301   *         @arg @ref LL_HRTIM_TIMER_B
10302   *         @arg @ref LL_HRTIM_TIMER_C
10303   *         @arg @ref LL_HRTIM_TIMER_D
10304   *         @arg @ref LL_HRTIM_TIMER_E
10305   * @retval None
10306   */
10307 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10308 {
10309   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10310   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10311                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10312   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10313 }
10314
10315 /**
10316   * @brief  Indicate whether the output 2 reset  DMA request is enabled for a given timer.
10317   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_IsEnabledDMAReq_RST2
10318   * @param  HRTIMx High Resolution Timer instance
10319   * @param  Timer This parameter can be one of the following values:
10320   *         @arg @ref LL_HRTIM_TIMER_A
10321   *         @arg @ref LL_HRTIM_TIMER_B
10322   *         @arg @ref LL_HRTIM_TIMER_C
10323   *         @arg @ref LL_HRTIM_TIMER_D
10324   *         @arg @ref LL_HRTIM_TIMER_E
10325   * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10326   */
10327 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10328 {
10329   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10330   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10331                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10332
10333   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
10334 }
10335
10336 /**
10337   * @brief  Enable the reset/roll-over DMA request for a given timer.
10338   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_EnableDMAReq_RST
10339   * @param  HRTIMx High Resolution Timer instance
10340   * @param  Timer This parameter can be one of the following values:
10341   *         @arg @ref LL_HRTIM_TIMER_A
10342   *         @arg @ref LL_HRTIM_TIMER_B
10343   *         @arg @ref LL_HRTIM_TIMER_C
10344   *         @arg @ref LL_HRTIM_TIMER_D
10345   *         @arg @ref LL_HRTIM_TIMER_E
10346   * @retval None
10347   */
10348 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10349 {
10350   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10351   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10352                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10353   SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10354 }
10355
10356 /**
10357   * @brief  Disable the reset/roll-over DMA request for a given timer.
10358   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_DisableDMAReq_RST
10359   * @param  HRTIMx High Resolution Timer instance
10360   * @param  Timer This parameter can be one of the following values:
10361   *         @arg @ref LL_HRTIM_TIMER_A
10362   *         @arg @ref LL_HRTIM_TIMER_B
10363   *         @arg @ref LL_HRTIM_TIMER_C
10364   *         @arg @ref LL_HRTIM_TIMER_D
10365   *         @arg @ref LL_HRTIM_TIMER_E
10366   * @retval None
10367   */
10368 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10369 {
10370   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10371   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10372                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10373   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10374 }
10375
10376 /**
10377   * @brief  Indicate whether the reset/roll-over DMA request is enabled for a given timer.
10378   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_IsEnabledDMAReq_RST
10379   * @param  HRTIMx High Resolution Timer instance
10380   * @param  Timer This parameter can be one of the following values:
10381   *         @arg @ref LL_HRTIM_TIMER_A
10382   *         @arg @ref LL_HRTIM_TIMER_B
10383   *         @arg @ref LL_HRTIM_TIMER_C
10384   *         @arg @ref LL_HRTIM_TIMER_D
10385   *         @arg @ref LL_HRTIM_TIMER_E
10386   * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
10387   */
10388 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10389 {
10390   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10391   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10392                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10393
10394   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
10395 }
10396
10397 /**
10398   * @brief  Enable the delayed protection DMA request for a given timer.
10399   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_EnableDMAReq_DLYPRT
10400   * @param  HRTIMx High Resolution Timer instance
10401   * @param  Timer This parameter can be one of the following values:
10402   *         @arg @ref LL_HRTIM_TIMER_A
10403   *         @arg @ref LL_HRTIM_TIMER_B
10404   *         @arg @ref LL_HRTIM_TIMER_C
10405   *         @arg @ref LL_HRTIM_TIMER_D
10406   *         @arg @ref LL_HRTIM_TIMER_E
10407   * @retval None
10408   */
10409 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10410 {
10411   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10412   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10413                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10414   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10415 }
10416
10417 /**
10418   * @brief  Disable the delayed protection DMA request for a given timer.
10419   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_DisableDMAReq_DLYPRT
10420   * @param  HRTIMx High Resolution Timer instance
10421   * @param  Timer This parameter can be one of the following values:
10422   *         @arg @ref LL_HRTIM_TIMER_A
10423   *         @arg @ref LL_HRTIM_TIMER_B
10424   *         @arg @ref LL_HRTIM_TIMER_C
10425   *         @arg @ref LL_HRTIM_TIMER_D
10426   *         @arg @ref LL_HRTIM_TIMER_E
10427   * @retval None
10428   */
10429 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10430 {
10431   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10432   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10433                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10434   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10435 }
10436
10437 /**
10438   * @brief  Indicate whether the delayed protection DMA request is enabled for a given timer.
10439   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_IsEnabledDMAReq_DLYPRT
10440   * @param  HRTIMx High Resolution Timer instance
10441   * @param  Timer This parameter can be one of the following values:
10442   *         @arg @ref LL_HRTIM_TIMER_A
10443   *         @arg @ref LL_HRTIM_TIMER_B
10444   *         @arg @ref LL_HRTIM_TIMER_C
10445   *         @arg @ref LL_HRTIM_TIMER_D
10446   *         @arg @ref LL_HRTIM_TIMER_E
10447   * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
10448   */
10449 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10450 {
10451   register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10452   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10453                                                     REG_OFFSET_TAB_TIMER[iTimer]));
10454
10455   return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
10456 }
10457
10458 /**
10459   * @}
10460   */
10461
10462 #if defined(USE_FULL_LL_DRIVER)
10463 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
10464   * @{
10465   */
10466 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
10467 /**
10468   * @}
10469   */
10470 #endif /* USE_FULL_LL_DRIVER */
10471
10472 /**
10473   * @}
10474   */
10475
10476 /**
10477   * @}
10478   */
10479
10480 #endif /* HRTIM1 */
10481
10482 /**
10483   * @}
10484   */
10485
10486 #ifdef __cplusplus
10487 }
10488 #endif
10489
10490 #endif /* STM32H7xx_LL_HRTIM_H */
10491
10492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
10493
10494
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_hsem.h Source File

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stm32h7xx_ll_hsem.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_hsem.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HSEM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_HSEM_H
00022 #define STM32H7xx_LL_HSEM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(HSEM)
00036
00037 /** @defgroup HSEM_LL HSEM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 /* Exported constants --------------------------------------------------------*/
00048
00049 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup HSEM_LL_EC_COREID COREID Defines
00054   * @{
00055   */
00056 #define LL_HSEM_COREID_NONE             0U
00057 #define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1
00058 #if defined(DUAL_CORE)
00059 #define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2
00060 #endif /* DUAL_CORE */
00061 #define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
00067   * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
00068   * @{
00069   */
00070
00071 #define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0
00072 #define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1
00073 #define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2
00074 #define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3
00075 #define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4
00076 #define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5
00077 #define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6
00078 #define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7
00079 #define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8
00080 #define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9
00081 #define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10
00082 #define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11
00083 #define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12
00084 #define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13
00085 #define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14
00086 #define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15
00087 #if (HSEM_SEMID_MAX == 15)
00088 #define LL_HSEM_SEMAPHORE_ALL              0x0000FFFFU
00089 #else /* HSEM_SEMID_MAX == 31 */
00090 #define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16
00091 #define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17
00092 #define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18
00093 #define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19
00094 #define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20
00095 #define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21
00096 #define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22
00097 #define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23
00098 #define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24
00099 #define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25
00100 #define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26
00101 #define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27
00102 #define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28
00103 #define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29
00104 #define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30
00105 #define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31
00106 #define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU
00107 #endif /* HSEM_SEMID_MAX == 15 */
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported macro ------------------------------------------------------------*/
00117 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
00118   * @{
00119   */
00120
00121 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  Write a value in HSEM register
00127   * @param  __INSTANCE__ HSEM Instance
00128   * @param  __REG__ Register to be written
00129   * @param  __VALUE__ Value to be written in the register
00130   * @retval None
00131   */
00132 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00133
00134 /**
00135   * @brief  Read a value in HSEM register
00136   * @param  __INSTANCE__ HSEM Instance
00137   * @param  __REG__ Register to be read
00138   * @retval Register value
00139   */
00140 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00141 /**
00142   * @}
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /* Exported functions --------------------------------------------------------*/
00150 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
00151   * @{
00152   */
00153
00154 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
00155   * @{
00156   */
00157
00158
00159 /**
00160   * @brief  Return 1 if the semaphore is locked, else return 0.
00161   * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked
00162   * @param  HSEMx HSEM Instance.
00163   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00164   * @retval State of bit (1 or 0).
00165   */
00166 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00167 {
00168   return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
00169 }
00170
00171 /**
00172   * @brief  Get core id.
00173   * @rmtoll R            COREID        LL_HSEM_GetCoreId
00174   * @param  HSEMx HSEM Instance.
00175   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00176   * @retval Returned value can be one of the following values:
00177   *         @arg @ref LL_HSEM_COREID_NONE
00178   *         @arg @ref LL_HSEM_COREID_CPU1
00179   *         @arg @ref LL_HSEM_COREID_CPU2
00180   */
00181 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00182 {
00183   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
00184 }
00185
00186 /**
00187   * @brief  Get process id.
00188   * @rmtoll R            PROCID        LL_HSEM_GetProcessId
00189   * @param  HSEMx HSEM Instance.
00190   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00191   * @retval Process number. Value between Min_Data=0 and Max_Data=255
00192   */
00193 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00194 {
00195   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
00196 }
00197
00198 /**
00199   * @brief  Get the lock by writing in R register.
00200   * @note The R register has to be read to determined if the lock is taken.
00201   * @rmtoll R            LOCK          LL_HSEM_SetLock
00202   * @rmtoll R            COREID        LL_HSEM_SetLock
00203   * @rmtoll R            PROCID        LL_HSEM_SetLock
00204   * @param  HSEMx HSEM Instance.
00205   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00206   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
00207   * @retval None
00208   */
00209 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00210 {
00211   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
00212 }
00213
00214 /**
00215   * @brief  Get the lock with 2-step lock.
00216   * @rmtoll R            LOCK          LL_HSEM_2StepLock
00217   * @rmtoll R            COREID        LL_HSEM_2StepLock
00218   * @rmtoll R            PROCID        LL_HSEM_2StepLock
00219   * @param  HSEMx HSEM Instance.
00220   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00221   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
00222   * @retval 1 lock fail, 0 lock successful or already locked by same process and core
00223   */
00224 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00225 {
00226   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
00227   return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
00228 }
00229
00230 /**
00231   * @brief  Get the lock with 1-step lock.
00232   * @rmtoll RLR          LOCK          LL_HSEM_1StepLock
00233   * @rmtoll RLR          COREID        LL_HSEM_1StepLock
00234   * @rmtoll RLR          PROCID        LL_HSEM_1StepLock
00235   * @param  HSEMx HSEM Instance.
00236   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00237   * @retval 1 lock fail, 0 lock successful or already locked by same core
00238   */
00239 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00240 {
00241   return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
00242 }
00243
00244 /**
00245   * @brief  Release the lock of the semaphore.
00246   * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
00247   * @rmtoll R            LOCK          LL_HSEM_ReleaseLock
00248   * @param  HSEMx HSEM Instance.
00249   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00250   * @param  process Process number. Value between Min_Data=0 and Max_Data=255
00251   * @retval None
00252   */
00253 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00254 {
00255   WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
00256 }
00257
00258 /**
00259   * @brief  Get the lock status of the semaphore.
00260   * @rmtoll R            LOCK          LL_HSEM_GetStatus
00261   * @param  HSEMx HSEM Instance.
00262   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00263   * @retval 0 semaphore is free, 1 semaphore is locked  */
00264 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00265 {
00266   return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
00267 }
00268
00269 /**
00270   * @brief  Set the key.
00271   * @rmtoll KEYR         KEY           LL_HSEM_SetKey
00272   * @param  HSEMx HSEM Instance.
00273   * @param  key Key value.
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
00277 {
00278   WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
00279 }
00280
00281 /**
00282   * @brief  Get the key.
00283   * @rmtoll KEYR         KEY           LL_HSEM_GetKey
00284   * @param  HSEMx HSEM Instance.
00285   * @retval key to unlock all semaphore from the same core
00286   */
00287 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
00288 {
00289   return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
00290 }
00291
00292 /**
00293   * @brief  Release all semaphore with the same core id.
00294   * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
00295   * @param  HSEMx HSEM Instance.
00296   * @param  key Key value.
00297   * @param  core This parameter can be one of the following values:
00298   *         @arg @ref LL_HSEM_COREID_CPU1
00299   *         @arg @ref LL_HSEM_COREID_CPU2
00300   * @retval None
00301   */
00302 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
00303 {
00304   WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
00312   * @{
00313   */
00314
00315 /**
00316   * @brief  Enable interrupt.
00317   * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER
00318   * @param  HSEMx HSEM Instance.
00319   * @param  SemaphoreMask This parameter can be a combination of the following values:
00320   *         @arg @ref LL_HSEM_SEMAPHORE_0
00321   *         @arg @ref LL_HSEM_SEMAPHORE_1
00322   *         @arg @ref LL_HSEM_SEMAPHORE_2
00323   *         @arg @ref LL_HSEM_SEMAPHORE_3
00324   *         @arg @ref LL_HSEM_SEMAPHORE_4
00325   *         @arg @ref LL_HSEM_SEMAPHORE_5
00326   *         @arg @ref LL_HSEM_SEMAPHORE_6
00327   *         @arg @ref LL_HSEM_SEMAPHORE_7
00328   *         @arg @ref LL_HSEM_SEMAPHORE_8
00329   *         @arg @ref LL_HSEM_SEMAPHORE_9
00330   *         @arg @ref LL_HSEM_SEMAPHORE_10
00331   *         @arg @ref LL_HSEM_SEMAPHORE_11
00332   *         @arg @ref LL_HSEM_SEMAPHORE_12
00333   *         @arg @ref LL_HSEM_SEMAPHORE_13
00334   *         @arg @ref LL_HSEM_SEMAPHORE_14
00335   *         @arg @ref LL_HSEM_SEMAPHORE_15
00336   *         @arg @ref LL_HSEM_SEMAPHORE_16
00337   *         @arg @ref LL_HSEM_SEMAPHORE_17
00338   *         @arg @ref LL_HSEM_SEMAPHORE_18
00339   *         @arg @ref LL_HSEM_SEMAPHORE_19
00340   *         @arg @ref LL_HSEM_SEMAPHORE_20
00341   *         @arg @ref LL_HSEM_SEMAPHORE_21
00342   *         @arg @ref LL_HSEM_SEMAPHORE_22
00343   *         @arg @ref LL_HSEM_SEMAPHORE_23
00344   *         @arg @ref LL_HSEM_SEMAPHORE_24
00345   *         @arg @ref LL_HSEM_SEMAPHORE_25
00346   *         @arg @ref LL_HSEM_SEMAPHORE_26
00347   *         @arg @ref LL_HSEM_SEMAPHORE_27
00348   *         @arg @ref LL_HSEM_SEMAPHORE_28
00349   *         @arg @ref LL_HSEM_SEMAPHORE_29
00350   *         @arg @ref LL_HSEM_SEMAPHORE_30
00351   *         @arg @ref LL_HSEM_SEMAPHORE_31
00352   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00353   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00354   *         depends on devices.
00355   * @retval None
00356   */
00357 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00358 {
00359   SET_BIT(HSEMx->C1IER, SemaphoreMask);
00360 }
00361
00362 /**
00363   * @brief  Disable interrupt.
00364   * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER
00365   * @param  HSEMx HSEM Instance.
00366   * @param  SemaphoreMask This parameter can be a combination of the following values:
00367   *         @arg @ref LL_HSEM_SEMAPHORE_0
00368   *         @arg @ref LL_HSEM_SEMAPHORE_1
00369   *         @arg @ref LL_HSEM_SEMAPHORE_2
00370   *         @arg @ref LL_HSEM_SEMAPHORE_3
00371   *         @arg @ref LL_HSEM_SEMAPHORE_4
00372   *         @arg @ref LL_HSEM_SEMAPHORE_5
00373   *         @arg @ref LL_HSEM_SEMAPHORE_6
00374   *         @arg @ref LL_HSEM_SEMAPHORE_7
00375   *         @arg @ref LL_HSEM_SEMAPHORE_8
00376   *         @arg @ref LL_HSEM_SEMAPHORE_9
00377   *         @arg @ref LL_HSEM_SEMAPHORE_10
00378   *         @arg @ref LL_HSEM_SEMAPHORE_11
00379   *         @arg @ref LL_HSEM_SEMAPHORE_12
00380   *         @arg @ref LL_HSEM_SEMAPHORE_13
00381   *         @arg @ref LL_HSEM_SEMAPHORE_14
00382   *         @arg @ref LL_HSEM_SEMAPHORE_15
00383   *         @arg @ref LL_HSEM_SEMAPHORE_16
00384   *         @arg @ref LL_HSEM_SEMAPHORE_17
00385   *         @arg @ref LL_HSEM_SEMAPHORE_18
00386   *         @arg @ref LL_HSEM_SEMAPHORE_19
00387   *         @arg @ref LL_HSEM_SEMAPHORE_20
00388   *         @arg @ref LL_HSEM_SEMAPHORE_21
00389   *         @arg @ref LL_HSEM_SEMAPHORE_22
00390   *         @arg @ref LL_HSEM_SEMAPHORE_23
00391   *         @arg @ref LL_HSEM_SEMAPHORE_24
00392   *         @arg @ref LL_HSEM_SEMAPHORE_25
00393   *         @arg @ref LL_HSEM_SEMAPHORE_26
00394   *         @arg @ref LL_HSEM_SEMAPHORE_27
00395   *         @arg @ref LL_HSEM_SEMAPHORE_28
00396   *         @arg @ref LL_HSEM_SEMAPHORE_29
00397   *         @arg @ref LL_HSEM_SEMAPHORE_30
00398   *         @arg @ref LL_HSEM_SEMAPHORE_31
00399   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00400   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00401   *         depends on devices.
00402   * @retval None
00403   */
00404 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00405 {
00406   CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
00407 }
00408
00409 /**
00410   * @brief  Check if interrupt is enabled.
00411   * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER
00412   * @param  HSEMx HSEM Instance.
00413   * @param  SemaphoreMask This parameter can be a combination of the following values:
00414   *         @arg @ref LL_HSEM_SEMAPHORE_0
00415   *         @arg @ref LL_HSEM_SEMAPHORE_1
00416   *         @arg @ref LL_HSEM_SEMAPHORE_2
00417   *         @arg @ref LL_HSEM_SEMAPHORE_3
00418   *         @arg @ref LL_HSEM_SEMAPHORE_4
00419   *         @arg @ref LL_HSEM_SEMAPHORE_5
00420   *         @arg @ref LL_HSEM_SEMAPHORE_6
00421   *         @arg @ref LL_HSEM_SEMAPHORE_7
00422   *         @arg @ref LL_HSEM_SEMAPHORE_8
00423   *         @arg @ref LL_HSEM_SEMAPHORE_9
00424   *         @arg @ref LL_HSEM_SEMAPHORE_10
00425   *         @arg @ref LL_HSEM_SEMAPHORE_11
00426   *         @arg @ref LL_HSEM_SEMAPHORE_12
00427   *         @arg @ref LL_HSEM_SEMAPHORE_13
00428   *         @arg @ref LL_HSEM_SEMAPHORE_14
00429   *         @arg @ref LL_HSEM_SEMAPHORE_15
00430   *         @arg @ref LL_HSEM_SEMAPHORE_16
00431   *         @arg @ref LL_HSEM_SEMAPHORE_17
00432   *         @arg @ref LL_HSEM_SEMAPHORE_18
00433   *         @arg @ref LL_HSEM_SEMAPHORE_19
00434   *         @arg @ref LL_HSEM_SEMAPHORE_20
00435   *         @arg @ref LL_HSEM_SEMAPHORE_21
00436   *         @arg @ref LL_HSEM_SEMAPHORE_22
00437   *         @arg @ref LL_HSEM_SEMAPHORE_23
00438   *         @arg @ref LL_HSEM_SEMAPHORE_24
00439   *         @arg @ref LL_HSEM_SEMAPHORE_25
00440   *         @arg @ref LL_HSEM_SEMAPHORE_26
00441   *         @arg @ref LL_HSEM_SEMAPHORE_27
00442   *         @arg @ref LL_HSEM_SEMAPHORE_28
00443   *         @arg @ref LL_HSEM_SEMAPHORE_29
00444   *         @arg @ref LL_HSEM_SEMAPHORE_30
00445   *         @arg @ref LL_HSEM_SEMAPHORE_31
00446   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00447   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00448   *         depends on devices.
00449   * @retval State of bit (1 or 0).
00450   */
00451 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00452 {
00453   return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00454 }
00455
00456 #if defined(DUAL_CORE)
00457 /**
00458   * @brief  Enable interrupt.
00459   * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER
00460   * @param  HSEMx HSEM Instance.
00461   * @param  SemaphoreMask This parameter can be a combination of the following values:
00462   *         @arg @ref LL_HSEM_SEMAPHORE_0
00463   *         @arg @ref LL_HSEM_SEMAPHORE_1
00464   *         @arg @ref LL_HSEM_SEMAPHORE_2
00465   *         @arg @ref LL_HSEM_SEMAPHORE_3
00466   *         @arg @ref LL_HSEM_SEMAPHORE_4
00467   *         @arg @ref LL_HSEM_SEMAPHORE_5
00468   *         @arg @ref LL_HSEM_SEMAPHORE_6
00469   *         @arg @ref LL_HSEM_SEMAPHORE_7
00470   *         @arg @ref LL_HSEM_SEMAPHORE_8
00471   *         @arg @ref LL_HSEM_SEMAPHORE_9
00472   *         @arg @ref LL_HSEM_SEMAPHORE_10
00473   *         @arg @ref LL_HSEM_SEMAPHORE_11
00474   *         @arg @ref LL_HSEM_SEMAPHORE_12
00475   *         @arg @ref LL_HSEM_SEMAPHORE_13
00476   *         @arg @ref LL_HSEM_SEMAPHORE_14
00477   *         @arg @ref LL_HSEM_SEMAPHORE_15
00478   *         @arg @ref LL_HSEM_SEMAPHORE_16
00479   *         @arg @ref LL_HSEM_SEMAPHORE_17
00480   *         @arg @ref LL_HSEM_SEMAPHORE_18
00481   *         @arg @ref LL_HSEM_SEMAPHORE_19
00482   *         @arg @ref LL_HSEM_SEMAPHORE_20
00483   *         @arg @ref LL_HSEM_SEMAPHORE_21
00484   *         @arg @ref LL_HSEM_SEMAPHORE_22
00485   *         @arg @ref LL_HSEM_SEMAPHORE_23
00486   *         @arg @ref LL_HSEM_SEMAPHORE_24
00487   *         @arg @ref LL_HSEM_SEMAPHORE_25
00488   *         @arg @ref LL_HSEM_SEMAPHORE_26
00489   *         @arg @ref LL_HSEM_SEMAPHORE_27
00490   *         @arg @ref LL_HSEM_SEMAPHORE_28
00491   *         @arg @ref LL_HSEM_SEMAPHORE_29
00492   *         @arg @ref LL_HSEM_SEMAPHORE_30
00493   *         @arg @ref LL_HSEM_SEMAPHORE_31
00494   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00495   * @retval None
00496   */
00497 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00498 {
00499   SET_BIT(HSEMx->C2IER, SemaphoreMask);
00500 }
00501
00502 /**
00503   * @brief  Disable interrupt.
00504   * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER
00505   * @param  HSEMx HSEM Instance.
00506   * @param  SemaphoreMask This parameter can be a combination of the following values:
00507   *         @arg @ref LL_HSEM_SEMAPHORE_0
00508   *         @arg @ref LL_HSEM_SEMAPHORE_1
00509   *         @arg @ref LL_HSEM_SEMAPHORE_2
00510   *         @arg @ref LL_HSEM_SEMAPHORE_3
00511   *         @arg @ref LL_HSEM_SEMAPHORE_4
00512   *         @arg @ref LL_HSEM_SEMAPHORE_5
00513   *         @arg @ref LL_HSEM_SEMAPHORE_6
00514   *         @arg @ref LL_HSEM_SEMAPHORE_7
00515   *         @arg @ref LL_HSEM_SEMAPHORE_8
00516   *         @arg @ref LL_HSEM_SEMAPHORE_9
00517   *         @arg @ref LL_HSEM_SEMAPHORE_10
00518   *         @arg @ref LL_HSEM_SEMAPHORE_11
00519   *         @arg @ref LL_HSEM_SEMAPHORE_12
00520   *         @arg @ref LL_HSEM_SEMAPHORE_13
00521   *         @arg @ref LL_HSEM_SEMAPHORE_14
00522   *         @arg @ref LL_HSEM_SEMAPHORE_15
00523   *         @arg @ref LL_HSEM_SEMAPHORE_16
00524   *         @arg @ref LL_HSEM_SEMAPHORE_17
00525   *         @arg @ref LL_HSEM_SEMAPHORE_18
00526   *         @arg @ref LL_HSEM_SEMAPHORE_19
00527   *         @arg @ref LL_HSEM_SEMAPHORE_20
00528   *         @arg @ref LL_HSEM_SEMAPHORE_21
00529   *         @arg @ref LL_HSEM_SEMAPHORE_22
00530   *         @arg @ref LL_HSEM_SEMAPHORE_23
00531   *         @arg @ref LL_HSEM_SEMAPHORE_24
00532   *         @arg @ref LL_HSEM_SEMAPHORE_25
00533   *         @arg @ref LL_HSEM_SEMAPHORE_26
00534   *         @arg @ref LL_HSEM_SEMAPHORE_27
00535   *         @arg @ref LL_HSEM_SEMAPHORE_28
00536   *         @arg @ref LL_HSEM_SEMAPHORE_29
00537   *         @arg @ref LL_HSEM_SEMAPHORE_30
00538   *         @arg @ref LL_HSEM_SEMAPHORE_31
00539   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00543 {
00544   CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
00545 }
00546
00547 /**
00548   * @brief  Check if interrupt is enabled.
00549   * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER
00550   * @param  HSEMx HSEM Instance.
00551   * @param  SemaphoreMask This parameter can be a combination of the following values:
00552   *         @arg @ref LL_HSEM_SEMAPHORE_0
00553   *         @arg @ref LL_HSEM_SEMAPHORE_1
00554   *         @arg @ref LL_HSEM_SEMAPHORE_2
00555   *         @arg @ref LL_HSEM_SEMAPHORE_3
00556   *         @arg @ref LL_HSEM_SEMAPHORE_4
00557   *         @arg @ref LL_HSEM_SEMAPHORE_5
00558   *         @arg @ref LL_HSEM_SEMAPHORE_6
00559   *         @arg @ref LL_HSEM_SEMAPHORE_7
00560   *         @arg @ref LL_HSEM_SEMAPHORE_8
00561   *         @arg @ref LL_HSEM_SEMAPHORE_9
00562   *         @arg @ref LL_HSEM_SEMAPHORE_10
00563   *         @arg @ref LL_HSEM_SEMAPHORE_11
00564   *         @arg @ref LL_HSEM_SEMAPHORE_12
00565   *         @arg @ref LL_HSEM_SEMAPHORE_13
00566   *         @arg @ref LL_HSEM_SEMAPHORE_14
00567   *         @arg @ref LL_HSEM_SEMAPHORE_15
00568   *         @arg @ref LL_HSEM_SEMAPHORE_16
00569   *         @arg @ref LL_HSEM_SEMAPHORE_17
00570   *         @arg @ref LL_HSEM_SEMAPHORE_18
00571   *         @arg @ref LL_HSEM_SEMAPHORE_19
00572   *         @arg @ref LL_HSEM_SEMAPHORE_20
00573   *         @arg @ref LL_HSEM_SEMAPHORE_21
00574   *         @arg @ref LL_HSEM_SEMAPHORE_22
00575   *         @arg @ref LL_HSEM_SEMAPHORE_23
00576   *         @arg @ref LL_HSEM_SEMAPHORE_24
00577   *         @arg @ref LL_HSEM_SEMAPHORE_25
00578   *         @arg @ref LL_HSEM_SEMAPHORE_26
00579   *         @arg @ref LL_HSEM_SEMAPHORE_27
00580   *         @arg @ref LL_HSEM_SEMAPHORE_28
00581   *         @arg @ref LL_HSEM_SEMAPHORE_29
00582   *         @arg @ref LL_HSEM_SEMAPHORE_30
00583   *         @arg @ref LL_HSEM_SEMAPHORE_31
00584   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00585   * @retval State of bit (1 or 0).
00586   */
00587 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00588 {
00589   return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00590 }
00591 #endif /* DUAL_CORE */
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
00597   * @{
00598   */
00599
00600 /**
00601   * @brief  Clear interrupt status.
00602   * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR
00603   * @param  HSEMx HSEM Instance.
00604   * @param  SemaphoreMask This parameter can be a combination of the following values:
00605   *         @arg @ref LL_HSEM_SEMAPHORE_0
00606   *         @arg @ref LL_HSEM_SEMAPHORE_1
00607   *         @arg @ref LL_HSEM_SEMAPHORE_2
00608   *         @arg @ref LL_HSEM_SEMAPHORE_3
00609   *         @arg @ref LL_HSEM_SEMAPHORE_4
00610   *         @arg @ref LL_HSEM_SEMAPHORE_5
00611   *         @arg @ref LL_HSEM_SEMAPHORE_6
00612   *         @arg @ref LL_HSEM_SEMAPHORE_7
00613   *         @arg @ref LL_HSEM_SEMAPHORE_8
00614   *         @arg @ref LL_HSEM_SEMAPHORE_9
00615   *         @arg @ref LL_HSEM_SEMAPHORE_10
00616   *         @arg @ref LL_HSEM_SEMAPHORE_11
00617   *         @arg @ref LL_HSEM_SEMAPHORE_12
00618   *         @arg @ref LL_HSEM_SEMAPHORE_13
00619   *         @arg @ref LL_HSEM_SEMAPHORE_14
00620   *         @arg @ref LL_HSEM_SEMAPHORE_15
00621   *         @arg @ref LL_HSEM_SEMAPHORE_16
00622   *         @arg @ref LL_HSEM_SEMAPHORE_17
00623   *         @arg @ref LL_HSEM_SEMAPHORE_18
00624   *         @arg @ref LL_HSEM_SEMAPHORE_19
00625   *         @arg @ref LL_HSEM_SEMAPHORE_20
00626   *         @arg @ref LL_HSEM_SEMAPHORE_21
00627   *         @arg @ref LL_HSEM_SEMAPHORE_22
00628   *         @arg @ref LL_HSEM_SEMAPHORE_23
00629   *         @arg @ref LL_HSEM_SEMAPHORE_24
00630   *         @arg @ref LL_HSEM_SEMAPHORE_25
00631   *         @arg @ref LL_HSEM_SEMAPHORE_26
00632   *         @arg @ref LL_HSEM_SEMAPHORE_27
00633   *         @arg @ref LL_HSEM_SEMAPHORE_28
00634   *         @arg @ref LL_HSEM_SEMAPHORE_29
00635   *         @arg @ref LL_HSEM_SEMAPHORE_30
00636   *         @arg @ref LL_HSEM_SEMAPHORE_31
00637   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00638   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00639   *         depends on devices.
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00643 {
00644   WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
00645 }
00646
00647 /**
00648   * @brief  Get interrupt status from ISR register.
00649   * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR
00650   * @param  HSEMx HSEM Instance.
00651   * @param  SemaphoreMask This parameter can be a combination of the following values:
00652   *         @arg @ref LL_HSEM_SEMAPHORE_0
00653   *         @arg @ref LL_HSEM_SEMAPHORE_1
00654   *         @arg @ref LL_HSEM_SEMAPHORE_2
00655   *         @arg @ref LL_HSEM_SEMAPHORE_3
00656   *         @arg @ref LL_HSEM_SEMAPHORE_4
00657   *         @arg @ref LL_HSEM_SEMAPHORE_5
00658   *         @arg @ref LL_HSEM_SEMAPHORE_6
00659   *         @arg @ref LL_HSEM_SEMAPHORE_7
00660   *         @arg @ref LL_HSEM_SEMAPHORE_8
00661   *         @arg @ref LL_HSEM_SEMAPHORE_9
00662   *         @arg @ref LL_HSEM_SEMAPHORE_10
00663   *         @arg @ref LL_HSEM_SEMAPHORE_11
00664   *         @arg @ref LL_HSEM_SEMAPHORE_12
00665   *         @arg @ref LL_HSEM_SEMAPHORE_13
00666   *         @arg @ref LL_HSEM_SEMAPHORE_14
00667   *         @arg @ref LL_HSEM_SEMAPHORE_15
00668   *         @arg @ref LL_HSEM_SEMAPHORE_16
00669   *         @arg @ref LL_HSEM_SEMAPHORE_17
00670   *         @arg @ref LL_HSEM_SEMAPHORE_18
00671   *         @arg @ref LL_HSEM_SEMAPHORE_19
00672   *         @arg @ref LL_HSEM_SEMAPHORE_20
00673   *         @arg @ref LL_HSEM_SEMAPHORE_21
00674   *         @arg @ref LL_HSEM_SEMAPHORE_22
00675   *         @arg @ref LL_HSEM_SEMAPHORE_23
00676   *         @arg @ref LL_HSEM_SEMAPHORE_24
00677   *         @arg @ref LL_HSEM_SEMAPHORE_25
00678   *         @arg @ref LL_HSEM_SEMAPHORE_26
00679   *         @arg @ref LL_HSEM_SEMAPHORE_27
00680   *         @arg @ref LL_HSEM_SEMAPHORE_28
00681   *         @arg @ref LL_HSEM_SEMAPHORE_29
00682   *         @arg @ref LL_HSEM_SEMAPHORE_30
00683   *         @arg @ref LL_HSEM_SEMAPHORE_31
00684   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00685   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00686   *         depends on devices.
00687   * @retval State of bit (1 or 0).
00688   */
00689 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00690 {
00691   return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00692 }
00693
00694 /**
00695   * @brief  Get interrupt status from MISR register.
00696   * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR
00697   * @param  HSEMx HSEM Instance.
00698   * @param  SemaphoreMask This parameter can be a combination of the following values:
00699   *         @arg @ref LL_HSEM_SEMAPHORE_0
00700   *         @arg @ref LL_HSEM_SEMAPHORE_1
00701   *         @arg @ref LL_HSEM_SEMAPHORE_2
00702   *         @arg @ref LL_HSEM_SEMAPHORE_3
00703   *         @arg @ref LL_HSEM_SEMAPHORE_4
00704   *         @arg @ref LL_HSEM_SEMAPHORE_5
00705   *         @arg @ref LL_HSEM_SEMAPHORE_6
00706   *         @arg @ref LL_HSEM_SEMAPHORE_7
00707   *         @arg @ref LL_HSEM_SEMAPHORE_8
00708   *         @arg @ref LL_HSEM_SEMAPHORE_9
00709   *         @arg @ref LL_HSEM_SEMAPHORE_10
00710   *         @arg @ref LL_HSEM_SEMAPHORE_11
00711   *         @arg @ref LL_HSEM_SEMAPHORE_12
00712   *         @arg @ref LL_HSEM_SEMAPHORE_13
00713   *         @arg @ref LL_HSEM_SEMAPHORE_14
00714   *         @arg @ref LL_HSEM_SEMAPHORE_15
00715   *         @arg @ref LL_HSEM_SEMAPHORE_16
00716   *         @arg @ref LL_HSEM_SEMAPHORE_17
00717   *         @arg @ref LL_HSEM_SEMAPHORE_18
00718   *         @arg @ref LL_HSEM_SEMAPHORE_19
00719   *         @arg @ref LL_HSEM_SEMAPHORE_20
00720   *         @arg @ref LL_HSEM_SEMAPHORE_21
00721   *         @arg @ref LL_HSEM_SEMAPHORE_22
00722   *         @arg @ref LL_HSEM_SEMAPHORE_23
00723   *         @arg @ref LL_HSEM_SEMAPHORE_24
00724   *         @arg @ref LL_HSEM_SEMAPHORE_25
00725   *         @arg @ref LL_HSEM_SEMAPHORE_26
00726   *         @arg @ref LL_HSEM_SEMAPHORE_27
00727   *         @arg @ref LL_HSEM_SEMAPHORE_28
00728   *         @arg @ref LL_HSEM_SEMAPHORE_29
00729   *         @arg @ref LL_HSEM_SEMAPHORE_30
00730   *         @arg @ref LL_HSEM_SEMAPHORE_31
00731   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00732   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
00733   *         depends on devices.
00734   * @retval State of bit (1 or 0).
00735   */
00736 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00737 {
00738   return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00739 }
00740
00741 #if defined(DUAL_CORE)
00742 /**
00743   * @brief  Clear interrupt status.
00744   * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR
00745   * @param  HSEMx HSEM Instance.
00746   * @param  SemaphoreMask This parameter can be a combination of the following values:
00747   *         @arg @ref LL_HSEM_SEMAPHORE_0
00748   *         @arg @ref LL_HSEM_SEMAPHORE_1
00749   *         @arg @ref LL_HSEM_SEMAPHORE_2
00750   *         @arg @ref LL_HSEM_SEMAPHORE_3
00751   *         @arg @ref LL_HSEM_SEMAPHORE_4
00752   *         @arg @ref LL_HSEM_SEMAPHORE_5
00753   *         @arg @ref LL_HSEM_SEMAPHORE_6
00754   *         @arg @ref LL_HSEM_SEMAPHORE_7
00755   *         @arg @ref LL_HSEM_SEMAPHORE_8
00756   *         @arg @ref LL_HSEM_SEMAPHORE_9
00757   *         @arg @ref LL_HSEM_SEMAPHORE_10
00758   *         @arg @ref LL_HSEM_SEMAPHORE_11
00759   *         @arg @ref LL_HSEM_SEMAPHORE_12
00760   *         @arg @ref LL_HSEM_SEMAPHORE_13
00761   *         @arg @ref LL_HSEM_SEMAPHORE_14
00762   *         @arg @ref LL_HSEM_SEMAPHORE_15
00763   *         @arg @ref LL_HSEM_SEMAPHORE_16
00764   *         @arg @ref LL_HSEM_SEMAPHORE_17
00765   *         @arg @ref LL_HSEM_SEMAPHORE_18
00766   *         @arg @ref LL_HSEM_SEMAPHORE_19
00767   *         @arg @ref LL_HSEM_SEMAPHORE_20
00768   *         @arg @ref LL_HSEM_SEMAPHORE_21
00769   *         @arg @ref LL_HSEM_SEMAPHORE_22
00770   *         @arg @ref LL_HSEM_SEMAPHORE_23
00771   *         @arg @ref LL_HSEM_SEMAPHORE_24
00772   *         @arg @ref LL_HSEM_SEMAPHORE_25
00773   *         @arg @ref LL_HSEM_SEMAPHORE_26
00774   *         @arg @ref LL_HSEM_SEMAPHORE_27
00775   *         @arg @ref LL_HSEM_SEMAPHORE_28
00776   *         @arg @ref LL_HSEM_SEMAPHORE_29
00777   *         @arg @ref LL_HSEM_SEMAPHORE_30
00778   *         @arg @ref LL_HSEM_SEMAPHORE_31
00779   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00783 {
00784   WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
00785 }
00786
00787 /**
00788   * @brief  Get interrupt status from ISR register.
00789   * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR
00790   * @param  HSEMx HSEM Instance.
00791   * @param  SemaphoreMask This parameter can be a combination of the following values:
00792   *         @arg @ref LL_HSEM_SEMAPHORE_0
00793   *         @arg @ref LL_HSEM_SEMAPHORE_1
00794   *         @arg @ref LL_HSEM_SEMAPHORE_2
00795   *         @arg @ref LL_HSEM_SEMAPHORE_3
00796   *         @arg @ref LL_HSEM_SEMAPHORE_4
00797   *         @arg @ref LL_HSEM_SEMAPHORE_5
00798   *         @arg @ref LL_HSEM_SEMAPHORE_6
00799   *         @arg @ref LL_HSEM_SEMAPHORE_7
00800   *         @arg @ref LL_HSEM_SEMAPHORE_8
00801   *         @arg @ref LL_HSEM_SEMAPHORE_9
00802   *         @arg @ref LL_HSEM_SEMAPHORE_10
00803   *         @arg @ref LL_HSEM_SEMAPHORE_11
00804   *         @arg @ref LL_HSEM_SEMAPHORE_12
00805   *         @arg @ref LL_HSEM_SEMAPHORE_13
00806   *         @arg @ref LL_HSEM_SEMAPHORE_14
00807   *         @arg @ref LL_HSEM_SEMAPHORE_15
00808   *         @arg @ref LL_HSEM_SEMAPHORE_16
00809   *         @arg @ref LL_HSEM_SEMAPHORE_17
00810   *         @arg @ref LL_HSEM_SEMAPHORE_18
00811   *         @arg @ref LL_HSEM_SEMAPHORE_19
00812   *         @arg @ref LL_HSEM_SEMAPHORE_20
00813   *         @arg @ref LL_HSEM_SEMAPHORE_21
00814   *         @arg @ref LL_HSEM_SEMAPHORE_22
00815   *         @arg @ref LL_HSEM_SEMAPHORE_23
00816   *         @arg @ref LL_HSEM_SEMAPHORE_24
00817   *         @arg @ref LL_HSEM_SEMAPHORE_25
00818   *         @arg @ref LL_HSEM_SEMAPHORE_26
00819   *         @arg @ref LL_HSEM_SEMAPHORE_27
00820   *         @arg @ref LL_HSEM_SEMAPHORE_28
00821   *         @arg @ref LL_HSEM_SEMAPHORE_29
00822   *         @arg @ref LL_HSEM_SEMAPHORE_30
00823   *         @arg @ref LL_HSEM_SEMAPHORE_31
00824   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00825   * @retval State of bit (1 or 0).
00826   */
00827 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00828 {
00829   return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00830 }
00831
00832 /**
00833   * @brief  Get interrupt status from MISR register.
00834   * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR
00835   * @param  HSEMx HSEM Instance.
00836   * @param  SemaphoreMask This parameter can be a combination of the following values:
00837   *         @arg @ref LL_HSEM_SEMAPHORE_0
00838   *         @arg @ref LL_HSEM_SEMAPHORE_1
00839   *         @arg @ref LL_HSEM_SEMAPHORE_2
00840   *         @arg @ref LL_HSEM_SEMAPHORE_3
00841   *         @arg @ref LL_HSEM_SEMAPHORE_4
00842   *         @arg @ref LL_HSEM_SEMAPHORE_5
00843   *         @arg @ref LL_HSEM_SEMAPHORE_6
00844   *         @arg @ref LL_HSEM_SEMAPHORE_7
00845   *         @arg @ref LL_HSEM_SEMAPHORE_8
00846   *         @arg @ref LL_HSEM_SEMAPHORE_9
00847   *         @arg @ref LL_HSEM_SEMAPHORE_10
00848   *         @arg @ref LL_HSEM_SEMAPHORE_11
00849   *         @arg @ref LL_HSEM_SEMAPHORE_12
00850   *         @arg @ref LL_HSEM_SEMAPHORE_13
00851   *         @arg @ref LL_HSEM_SEMAPHORE_14
00852   *         @arg @ref LL_HSEM_SEMAPHORE_15
00853   *         @arg @ref LL_HSEM_SEMAPHORE_16
00854   *         @arg @ref LL_HSEM_SEMAPHORE_17
00855   *         @arg @ref LL_HSEM_SEMAPHORE_18
00856   *         @arg @ref LL_HSEM_SEMAPHORE_19
00857   *         @arg @ref LL_HSEM_SEMAPHORE_20
00858   *         @arg @ref LL_HSEM_SEMAPHORE_21
00859   *         @arg @ref LL_HSEM_SEMAPHORE_22
00860   *         @arg @ref LL_HSEM_SEMAPHORE_23
00861   *         @arg @ref LL_HSEM_SEMAPHORE_24
00862   *         @arg @ref LL_HSEM_SEMAPHORE_25
00863   *         @arg @ref LL_HSEM_SEMAPHORE_26
00864   *         @arg @ref LL_HSEM_SEMAPHORE_27
00865   *         @arg @ref LL_HSEM_SEMAPHORE_28
00866   *         @arg @ref LL_HSEM_SEMAPHORE_29
00867   *         @arg @ref LL_HSEM_SEMAPHORE_30
00868   *         @arg @ref LL_HSEM_SEMAPHORE_31
00869   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00870   * @retval State of bit (1 or 0).
00871   */
00872 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00873 {
00874   return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00875 }
00876 #endif /* DUAL_CORE */
00877 /**
00878   * @}
00879   */
00880
00881 /**
00882   * @}
00883   */
00884
00885 /**
00886   * @}
00887   */
00888
00889 #endif /* defined(HSEM) */
00890
00891 /**
00892   * @}
00893   */
00894
00895 #ifdef __cplusplus
00896 }
00897 #endif
00898
00899 #endif /* __STM32H7xx_LL_HSEM_H */
00900
00901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_i2c.c Source File

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stm32h7xx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_i2c.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
00035
00036 /** @defgroup I2C_LL I2C
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup I2C_LL_Private_Macros
00045   * @{
00046   */
00047
00048 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00049                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00050                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00051                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00052
00053 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00054                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00055
00056 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00057
00058 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00059
00060 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00061                                                  ((__VALUE__) == LL_I2C_NACK))
00062
00063 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00064                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00065 /**
00066   * @}
00067   */
00068
00069 /* Private function prototypes -----------------------------------------------*/
00070
00071 /* Exported functions --------------------------------------------------------*/
00072 /** @addtogroup I2C_LL_Exported_Functions
00073   * @{
00074   */
00075
00076 /** @addtogroup I2C_LL_EF_Init
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  De-initialize the I2C registers to their default reset values.
00082   * @param  I2Cx I2C Instance.
00083   * @retval An ErrorStatus enumeration value:
00084   *          - SUCCESS: I2C registers are de-initialized
00085   *          - ERROR: I2C registers are not de-initialized
00086   */
00087 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00088 {
00089   ErrorStatus status = SUCCESS;
00090
00091   /* Check the I2C Instance I2Cx */
00092   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00093
00094   if (I2Cx == I2C1)
00095   {
00096     /* Force reset of I2C clock */
00097     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00098
00099     /* Release reset of I2C clock */
00100     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00101   }
00102   else if (I2Cx == I2C2)
00103   {
00104     /* Force reset of I2C clock */
00105     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00106
00107     /* Release reset of I2C clock */
00108     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00109
00110   }
00111   else if (I2Cx == I2C3)
00112   {
00113     /* Force reset of I2C clock */
00114     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00115
00116     /* Release reset of I2C clock */
00117     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00118   }
00119   else if (I2Cx == I2C4)
00120   {
00121     /* Force reset of I2C clock */
00122     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_I2C4);
00123
00124     /* Release reset of I2C clock */
00125     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4);
00126   }
00127   else
00128   {
00129     status = ERROR;
00130   }
00131
00132   return status;
00133 }
00134
00135 /**
00136   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00137   * @param  I2Cx I2C Instance.
00138   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00139   * @retval An ErrorStatus enumeration value:
00140   *          - SUCCESS: I2C registers are initialized
00141   *          - ERROR: Not applicable
00142   */
00143 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00144 {
00145   /* Check the I2C Instance I2Cx */
00146   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00147
00148   /* Check the I2C parameters from I2C_InitStruct */
00149   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00150   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00151   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00152   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00153   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00154   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00155
00156   /* Disable the selected I2Cx Peripheral */
00157   LL_I2C_Disable(I2Cx);
00158
00159   /*---------------------------- I2Cx CR1 Configuration ------------------------
00160    * Configure the analog and digital noise filters with parameters :
00161    * - AnalogFilter: I2C_CR1_ANFOFF bit
00162    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00163    */
00164   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00165
00166   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00167    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00168    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00169    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00170    */
00171   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00172
00173   /* Enable the selected I2Cx Peripheral */
00174   LL_I2C_Enable(I2Cx);
00175
00176   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00177    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00178    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00179    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00180    */
00181   LL_I2C_DisableOwnAddress1(I2Cx);
00182   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00183
00184   /* OwnAdress1 == 0 is reserved for General Call address */
00185   if (I2C_InitStruct->OwnAddress1 != 0U)
00186   {
00187     LL_I2C_EnableOwnAddress1(I2Cx);
00188   }
00189
00190   /*---------------------------- I2Cx MODE Configuration -----------------------
00191   * Configure I2Cx peripheral mode with parameter :
00192    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00193    */
00194   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00195
00196   /*---------------------------- I2Cx CR2 Configuration ------------------------
00197    * Configure the ACKnowledge or Non ACKnowledge condition
00198    * after the address receive match code or next received byte with parameter :
00199    * - TypeAcknowledge: I2C_CR2_NACK bit
00200    */
00201   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00202
00203   return SUCCESS;
00204 }
00205
00206 /**
00207   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00208   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00209   * @retval None
00210   */
00211 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00212 {
00213   /* Set I2C_InitStruct fields to default values */
00214   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00215   I2C_InitStruct->Timing          = 0U;
00216   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00217   I2C_InitStruct->DigitalFilter   = 0U;
00218   I2C_InitStruct->OwnAddress1     = 0U;
00219   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00220   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00221 }
00222
00223 /**
00224   * @}
00225   */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
00236
00237 /**
00238   * @}
00239   */
00240
00241 #endif /* USE_FULL_LL_DRIVER */
00242
00243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_i2c.h Source File

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stm32h7xx_ll_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_I2C_H
00022 #define STM32H7xx_LL_I2C_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
00036
00037 /** @defgroup I2C_LL I2C
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00046   * @{
00047   */
00048 /**
00049   * @}
00050   */
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 #if defined(USE_FULL_LL_DRIVER)
00054 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00055   * @{
00056   */
00057 /**
00058   * @}
00059   */
00060 #endif /*USE_FULL_LL_DRIVER*/
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00065   * @{
00066   */
00067 typedef struct
00068 {
00069   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00070                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00071
00072                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00073
00074   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00075                                      This parameter must be set by referring to the STM32CubeMX Tool and
00076                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
00077
00078                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
00079
00080   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00081                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
00082
00083                                      This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00084
00085   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00086                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
00087
00088                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
00089
00090   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00091                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00092
00093                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00094
00095   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00096                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00097
00098                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00099
00100   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00101                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00102
00103                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00104 } LL_I2C_InitTypeDef;
00105 /**
00106   * @}
00107   */
00108 #endif /*USE_FULL_LL_DRIVER*/
00109
00110 /* Exported constants --------------------------------------------------------*/
00111 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00112   * @{
00113   */
00114
00115 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00116   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00117   * @{
00118   */
00119 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00120 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00121 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00122 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00123 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00124 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00125 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00126 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00127 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00133   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00134   * @{
00135   */
00136 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00137 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00138 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00139 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00140 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00141 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00142 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00143 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00144 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00145 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00146 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00147 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00148 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00149 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00150 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup I2C_LL_EC_IT IT Defines
00156   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00157   * @{
00158   */
00159 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00160 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00161 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00162 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00163 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00164 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00165 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00171   * @{
00172   */
00173 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
00174 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
00175 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
00176 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00182   * @{
00183   */
00184 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
00185 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00191   * @{
00192   */
00193 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
00194 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00200   * @{
00201   */
00202 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
00203 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00209   * @{
00210   */
00211 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
00212 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
00213 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
00214 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
00215 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
00216 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
00217 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
00218 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00224   * @{
00225   */
00226 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
00227 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00233   * @{
00234   */
00235 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
00236 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00242   * @{
00243   */
00244 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
00245 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00251   * @{
00252   */
00253 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
00254 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
00255 #define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
00256 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00257 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00258 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00259 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00260 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00266   * @{
00267   */
00268 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                                /*!< Don't Generate Stop and Start condition.                */
00269 #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)                                     /*!< Generate Stop condition (Size should be set to 0).      */
00270 #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
00271 #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Start for write request.                       */
00272 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
00273 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 7Bit address. */
00274 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
00275 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 10Bit address.*/
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00281   * @{
00282   */
00283 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
00284 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00290   * @{
00291   */
00292 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
00293 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00299   * @{
00300   */
00301 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
00302 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00308   * @{
00309   */
00310 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
00311 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
00312 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Exported macro ------------------------------------------------------------*/
00322 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00323   * @{
00324   */
00325
00326 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00327   * @{
00328   */
00329
00330 /**
00331   * @brief  Write a value in I2C register
00332   * @param  __INSTANCE__ I2C Instance
00333   * @param  __REG__ Register to be written
00334   * @param  __VALUE__ Value to be written in the register
00335   * @retval None
00336   */
00337 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00338
00339 /**
00340   * @brief  Read a value in I2C register
00341   * @param  __INSTANCE__ I2C Instance
00342   * @param  __REG__ Register to be read
00343   * @retval Register value
00344   */
00345 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00351   * @{
00352   */
00353 /**
00354   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00355   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
00356   * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
00357   * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
00358   * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
00359   * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
00360   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00361   */
00362 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
00363         ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
00364          (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
00365          (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
00366          (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
00367          (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
00368 /**
00369   * @}
00370   */
00371
00372 /**
00373   * @}
00374   */
00375
00376 /* Exported functions --------------------------------------------------------*/
00377 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00378   * @{
00379   */
00380
00381 /** @defgroup I2C_LL_EF_Configuration Configuration
00382   * @{
00383   */
00384
00385 /**
00386   * @brief  Enable I2C peripheral (PE = 1).
00387   * @rmtoll CR1          PE            LL_I2C_Enable
00388   * @param  I2Cx I2C Instance.
00389   * @retval None
00390   */
00391 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00392 {
00393   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00394 }
00395
00396 /**
00397   * @brief  Disable I2C peripheral (PE = 0).
00398   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00399   *         Internal state machines and status bits are put back to their reset value.
00400   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00401   * @rmtoll CR1          PE            LL_I2C_Disable
00402   * @param  I2Cx I2C Instance.
00403   * @retval None
00404   */
00405 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00406 {
00407   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00408 }
00409
00410 /**
00411   * @brief  Check if the I2C peripheral is enabled or disabled.
00412   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00413   * @param  I2Cx I2C Instance.
00414   * @retval State of bit (1 or 0).
00415   */
00416 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00417 {
00418   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
00419 }
00420
00421 /**
00422   * @brief  Configure Noise Filters (Analog and Digital).
00423   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00424   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00425   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00426   *         CR1          DNF           LL_I2C_ConfigFilters
00427   * @param  I2Cx I2C Instance.
00428   * @param  AnalogFilter This parameter can be one of the following values:
00429   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00430   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00431   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00432   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00433   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00434   * @retval None
00435   */
00436 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00437 {
00438   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
00439 }
00440
00441 /**
00442   * @brief  Configure Digital Noise Filter.
00443   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00444   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00445   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00446   * @param  I2Cx I2C Instance.
00447   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00448   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00449   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00450   * @retval None
00451   */
00452 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00453 {
00454   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
00455 }
00456
00457 /**
00458   * @brief  Get the current Digital Noise Filter configuration.
00459   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00460   * @param  I2Cx I2C Instance.
00461   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00462   */
00463 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00464 {
00465   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
00466 }
00467
00468 /**
00469   * @brief  Enable Analog Noise Filter.
00470   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00471   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00472   * @param  I2Cx I2C Instance.
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00476 {
00477   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00478 }
00479
00480 /**
00481   * @brief  Disable Analog Noise Filter.
00482   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00483   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00484   * @param  I2Cx I2C Instance.
00485   * @retval None
00486   */
00487 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00488 {
00489   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00490 }
00491
00492 /**
00493   * @brief  Check if Analog Noise Filter is enabled or disabled.
00494   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00495   * @param  I2Cx I2C Instance.
00496   * @retval State of bit (1 or 0).
00497   */
00498 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00499 {
00500   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
00501 }
00502
00503 /**
00504   * @brief  Enable DMA transmission requests.
00505   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00506   * @param  I2Cx I2C Instance.
00507   * @retval None
00508   */
00509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00510 {
00511   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00512 }
00513
00514 /**
00515   * @brief  Disable DMA transmission requests.
00516   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00517   * @param  I2Cx I2C Instance.
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00521 {
00522   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00523 }
00524
00525 /**
00526   * @brief  Check if DMA transmission requests are enabled or disabled.
00527   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00528   * @param  I2Cx I2C Instance.
00529   * @retval State of bit (1 or 0).
00530   */
00531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00532 {
00533   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
00534 }
00535
00536 /**
00537   * @brief  Enable DMA reception requests.
00538   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00539   * @param  I2Cx I2C Instance.
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00543 {
00544   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00545 }
00546
00547 /**
00548   * @brief  Disable DMA reception requests.
00549   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00550   * @param  I2Cx I2C Instance.
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00554 {
00555   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00556 }
00557
00558 /**
00559   * @brief  Check if DMA reception requests are enabled or disabled.
00560   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00561   * @param  I2Cx I2C Instance.
00562   * @retval State of bit (1 or 0).
00563   */
00564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00565 {
00566   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
00567 }
00568
00569 /**
00570   * @brief  Get the data register address used for DMA transfer
00571   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00572   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00573   * @param  I2Cx I2C Instance
00574   * @param  Direction This parameter can be one of the following values:
00575   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00576   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00577   * @retval Address of data register
00578   */
00579 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00580 {
00581   register uint32_t data_reg_addr;
00582
00583   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00584   {
00585     /* return address of TXDR register */
00586     data_reg_addr = (uint32_t) & (I2Cx->TXDR);
00587   }
00588   else
00589   {
00590     /* return address of RXDR register */
00591     data_reg_addr = (uint32_t) & (I2Cx->RXDR);
00592   }
00593
00594   return data_reg_addr;
00595 }
00596
00597 /**
00598   * @brief  Enable Clock stretching.
00599   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00600   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00601   * @param  I2Cx I2C Instance.
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00605 {
00606   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00607 }
00608
00609 /**
00610   * @brief  Disable Clock stretching.
00611   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00612   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00613   * @param  I2Cx I2C Instance.
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00617 {
00618   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00619 }
00620
00621 /**
00622   * @brief  Check if Clock stretching is enabled or disabled.
00623   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00624   * @param  I2Cx I2C Instance.
00625   * @retval State of bit (1 or 0).
00626   */
00627 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00628 {
00629   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
00630 }
00631
00632 /**
00633   * @brief  Enable hardware byte control in slave mode.
00634   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00635   * @param  I2Cx I2C Instance.
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00639 {
00640   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00641 }
00642
00643 /**
00644   * @brief  Disable hardware byte control in slave mode.
00645   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00646   * @param  I2Cx I2C Instance.
00647   * @retval None
00648   */
00649 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00650 {
00651   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00652 }
00653
00654 /**
00655   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00656   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00657   * @param  I2Cx I2C Instance.
00658   * @retval State of bit (1 or 0).
00659   */
00660 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00661 {
00662   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
00663 }
00664
00665 /**
00666   * @brief  Enable Wakeup from STOP.
00667   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00668   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00669   * @note   This bit can only be programmed when Digital Filter is disabled.
00670   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00671   * @param  I2Cx I2C Instance.
00672   * @retval None
00673   */
00674 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00675 {
00676   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00677 }
00678
00679 /**
00680   * @brief  Disable Wakeup from STOP.
00681   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00682   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00683   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00684   * @param  I2Cx I2C Instance.
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00688 {
00689   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00690 }
00691
00692 /**
00693   * @brief  Check if Wakeup from STOP is enabled or disabled.
00694   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00695   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00696   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00697   * @param  I2Cx I2C Instance.
00698   * @retval State of bit (1 or 0).
00699   */
00700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00701 {
00702   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
00703 }
00704
00705 /**
00706   * @brief  Enable General Call.
00707   * @note   When enabled the Address 0x00 is ACKed.
00708   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00709   * @param  I2Cx I2C Instance.
00710   * @retval None
00711   */
00712 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00713 {
00714   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00715 }
00716
00717 /**
00718   * @brief  Disable General Call.
00719   * @note   When disabled the Address 0x00 is NACKed.
00720   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00721   * @param  I2Cx I2C Instance.
00722   * @retval None
00723   */
00724 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00725 {
00726   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00727 }
00728
00729 /**
00730   * @brief  Check if General Call is enabled or disabled.
00731   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00732   * @param  I2Cx I2C Instance.
00733   * @retval State of bit (1 or 0).
00734   */
00735 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00736 {
00737   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
00738 }
00739
00740 /**
00741   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00742   * @note   Changing this bit is not allowed, when the START bit is set.
00743   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00744   * @param  I2Cx I2C Instance.
00745   * @param  AddressingMode This parameter can be one of the following values:
00746   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00747   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00748   * @retval None
00749   */
00750 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00751 {
00752   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00753 }
00754
00755 /**
00756   * @brief  Get the Master addressing mode.
00757   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00758   * @param  I2Cx I2C Instance.
00759   * @retval Returned value can be one of the following values:
00760   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00761   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00762   */
00763 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00764 {
00765   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00766 }
00767
00768 /**
00769   * @brief  Set the Own Address1.
00770   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00771   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00772   * @param  I2Cx I2C Instance.
00773   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00774   * @param  OwnAddrSize This parameter can be one of the following values:
00775   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00776   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00780 {
00781   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00782 }
00783
00784 /**
00785   * @brief  Enable acknowledge on Own Address1 match address.
00786   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00787   * @param  I2Cx I2C Instance.
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00791 {
00792   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00793 }
00794
00795 /**
00796   * @brief  Disable acknowledge on Own Address1 match address.
00797   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00798   * @param  I2Cx I2C Instance.
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00802 {
00803   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00804 }
00805
00806 /**
00807   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00808   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00809   * @param  I2Cx I2C Instance.
00810   * @retval State of bit (1 or 0).
00811   */
00812 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00813 {
00814   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
00815 }
00816
00817 /**
00818   * @brief  Set the 7bits Own Address2.
00819   * @note   This action has no effect if own address2 is enabled.
00820   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00821   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00822   * @param  I2Cx I2C Instance.
00823   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
00824   * @param  OwnAddrMask This parameter can be one of the following values:
00825   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00826   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00827   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00828   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00829   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00830   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00831   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00832   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00833   * @retval None
00834   */
00835 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00836 {
00837   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00838 }
00839
00840 /**
00841   * @brief  Enable acknowledge on Own Address2 match address.
00842   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00843   * @param  I2Cx I2C Instance.
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00847 {
00848   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00849 }
00850
00851 /**
00852   * @brief  Disable  acknowledge on Own Address2 match address.
00853   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00854   * @param  I2Cx I2C Instance.
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00858 {
00859   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00860 }
00861
00862 /**
00863   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00864   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00865   * @param  I2Cx I2C Instance.
00866   * @retval State of bit (1 or 0).
00867   */
00868 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00869 {
00870   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
00871 }
00872
00873 /**
00874   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00875   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00876   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00877   * @param  I2Cx I2C Instance.
00878   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
00879   * @note   This parameter is computed with the STM32CubeMX Tool.
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00883 {
00884   WRITE_REG(I2Cx->TIMINGR, Timing);
00885 }
00886
00887 /**
00888   * @brief  Get the Timing Prescaler setting.
00889   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00890   * @param  I2Cx I2C Instance.
00891   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00892   */
00893 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00894 {
00895   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
00896 }
00897
00898 /**
00899   * @brief  Get the SCL low period setting.
00900   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00901   * @param  I2Cx I2C Instance.
00902   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00903   */
00904 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00905 {
00906   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
00907 }
00908
00909 /**
00910   * @brief  Get the SCL high period setting.
00911   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00912   * @param  I2Cx I2C Instance.
00913   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00914   */
00915 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00916 {
00917   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
00918 }
00919
00920 /**
00921   * @brief  Get the SDA hold time.
00922   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00923   * @param  I2Cx I2C Instance.
00924   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00925   */
00926 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00927 {
00928   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
00929 }
00930
00931 /**
00932   * @brief  Get the SDA setup time.
00933   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00934   * @param  I2Cx I2C Instance.
00935   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00936   */
00937 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00938 {
00939   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
00940 }
00941
00942 /**
00943   * @brief  Configure peripheral mode.
00944   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00945   *         SMBus feature is supported by the I2Cx Instance.
00946   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00947   *         CR1          SMBDEN        LL_I2C_SetMode
00948   * @param  I2Cx I2C Instance.
00949   * @param  PeripheralMode This parameter can be one of the following values:
00950   *         @arg @ref LL_I2C_MODE_I2C
00951   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00952   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00953   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00954   * @retval None
00955   */
00956 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00957 {
00958   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00959 }
00960
00961 /**
00962   * @brief  Get peripheral mode.
00963   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00964   *         SMBus feature is supported by the I2Cx Instance.
00965   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
00966   *         CR1          SMBDEN        LL_I2C_GetMode
00967   * @param  I2Cx I2C Instance.
00968   * @retval Returned value can be one of the following values:
00969   *         @arg @ref LL_I2C_MODE_I2C
00970   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00971   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00972   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00973   */
00974 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
00975 {
00976   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
00977 }
00978
00979 /**
00980   * @brief  Enable SMBus alert (Host or Device mode)
00981   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00982   *         SMBus feature is supported by the I2Cx Instance.
00983   * @note   SMBus Device mode:
00984   *         - SMBus Alert pin is drived low and
00985   *           Alert Response Address Header acknowledge is enabled.
00986   *         SMBus Host mode:
00987   *         - SMBus Alert pin management is supported.
00988   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
00989   * @param  I2Cx I2C Instance.
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
00993 {
00994   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
00995 }
00996
00997 /**
00998   * @brief  Disable SMBus alert (Host or Device mode)
00999   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01000   *         SMBus feature is supported by the I2Cx Instance.
01001   * @note   SMBus Device mode:
01002   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01003   *           Alert Response Address Header acknowledge is disabled.
01004   *         SMBus Host mode:
01005   *         - SMBus Alert pin management is not supported.
01006   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01007   * @param  I2Cx I2C Instance.
01008   * @retval None
01009   */
01010 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01011 {
01012   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01013 }
01014
01015 /**
01016   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01017   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01018   *         SMBus feature is supported by the I2Cx Instance.
01019   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01020   * @param  I2Cx I2C Instance.
01021   * @retval State of bit (1 or 0).
01022   */
01023 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01024 {
01025   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
01026 }
01027
01028 /**
01029   * @brief  Enable SMBus Packet Error Calculation (PEC).
01030   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01031   *         SMBus feature is supported by the I2Cx Instance.
01032   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01033   * @param  I2Cx I2C Instance.
01034   * @retval None
01035   */
01036 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01037 {
01038   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01039 }
01040
01041 /**
01042   * @brief  Disable SMBus Packet Error Calculation (PEC).
01043   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01044   *         SMBus feature is supported by the I2Cx Instance.
01045   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01046   * @param  I2Cx I2C Instance.
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01050 {
01051   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01052 }
01053
01054 /**
01055   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01056   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01057   *         SMBus feature is supported by the I2Cx Instance.
01058   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01059   * @param  I2Cx I2C Instance.
01060   * @retval State of bit (1 or 0).
01061   */
01062 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01063 {
01064   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
01065 }
01066
01067 /**
01068   * @brief  Configure the SMBus Clock Timeout.
01069   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01070   *         SMBus feature is supported by the I2Cx Instance.
01071   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01072   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01073   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01074   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01075   * @param  I2Cx I2C Instance.
01076   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01077   * @param  TimeoutAMode This parameter can be one of the following values:
01078   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01079   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01080   * @param  TimeoutB
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01084                                                uint32_t TimeoutB)
01085 {
01086   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01087              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
01088 }
01089
01090 /**
01091   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01092   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01093   *         SMBus feature is supported by the I2Cx Instance.
01094   * @note   These bits can only be programmed when TimeoutA is disabled.
01095   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01096   * @param  I2Cx I2C Instance.
01097   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01101 {
01102   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01103 }
01104
01105 /**
01106   * @brief  Get the SMBus Clock TimeoutA setting.
01107   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01108   *         SMBus feature is supported by the I2Cx Instance.
01109   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01110   * @param  I2Cx I2C Instance.
01111   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01112   */
01113 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01114 {
01115   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01116 }
01117
01118 /**
01119   * @brief  Set the SMBus Clock TimeoutA mode.
01120   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01121   *         SMBus feature is supported by the I2Cx Instance.
01122   * @note   This bit can only be programmed when TimeoutA is disabled.
01123   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01124   * @param  I2Cx I2C Instance.
01125   * @param  TimeoutAMode This parameter can be one of the following values:
01126   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01127   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01128   * @retval None
01129   */
01130 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01131 {
01132   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01133 }
01134
01135 /**
01136   * @brief  Get the SMBus Clock TimeoutA mode.
01137   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01138   *         SMBus feature is supported by the I2Cx Instance.
01139   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01140   * @param  I2Cx I2C Instance.
01141   * @retval Returned value can be one of the following values:
01142   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01143   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01144   */
01145 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01146 {
01147   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01148 }
01149
01150 /**
01151   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01152   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01153   *         SMBus feature is supported by the I2Cx Instance.
01154   * @note   These bits can only be programmed when TimeoutB is disabled.
01155   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01156   * @param  I2Cx I2C Instance.
01157   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01161 {
01162   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
01163 }
01164
01165 /**
01166   * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
01167   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01168   *         SMBus feature is supported by the I2Cx Instance.
01169   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01170   * @param  I2Cx I2C Instance.
01171   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01172   */
01173 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01174 {
01175   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
01176 }
01177
01178 /**
01179   * @brief  Enable the SMBus Clock Timeout.
01180   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01181   *         SMBus feature is supported by the I2Cx Instance.
01182   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01183   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01184   * @param  I2Cx I2C Instance.
01185   * @param  ClockTimeout This parameter can be one of the following values:
01186   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01187   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01188   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01189   * @retval None
01190   */
01191 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01192 {
01193   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01194 }
01195
01196 /**
01197   * @brief  Disable the SMBus Clock Timeout.
01198   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01199   *         SMBus feature is supported by the I2Cx Instance.
01200   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01201   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01202   * @param  I2Cx I2C Instance.
01203   * @param  ClockTimeout This parameter can be one of the following values:
01204   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01205   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01206   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01207   * @retval None
01208   */
01209 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01210 {
01211   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01212 }
01213
01214 /**
01215   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01216   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01217   *         SMBus feature is supported by the I2Cx Instance.
01218   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01219   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01220   * @param  I2Cx I2C Instance.
01221   * @param  ClockTimeout This parameter can be one of the following values:
01222   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01223   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01224   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01225   * @retval State of bit (1 or 0).
01226   */
01227 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01228 {
01229   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
01230 }
01231
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01237   * @{
01238   */
01239
01240 /**
01241   * @brief  Enable TXIS interrupt.
01242   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01243   * @param  I2Cx I2C Instance.
01244   * @retval None
01245   */
01246 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01247 {
01248   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01249 }
01250
01251 /**
01252   * @brief  Disable TXIS interrupt.
01253   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01254   * @param  I2Cx I2C Instance.
01255   * @retval None
01256   */
01257 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01258 {
01259   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01260 }
01261
01262 /**
01263   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01264   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01265   * @param  I2Cx I2C Instance.
01266   * @retval State of bit (1 or 0).
01267   */
01268 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01269 {
01270   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
01271 }
01272
01273 /**
01274   * @brief  Enable RXNE interrupt.
01275   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01276   * @param  I2Cx I2C Instance.
01277   * @retval None
01278   */
01279 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01280 {
01281   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01282 }
01283
01284 /**
01285   * @brief  Disable RXNE interrupt.
01286   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01287   * @param  I2Cx I2C Instance.
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01291 {
01292   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01293 }
01294
01295 /**
01296   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01297   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01298   * @param  I2Cx I2C Instance.
01299   * @retval State of bit (1 or 0).
01300   */
01301 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01302 {
01303   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
01304 }
01305
01306 /**
01307   * @brief  Enable Address match interrupt (slave mode only).
01308   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01309   * @param  I2Cx I2C Instance.
01310   * @retval None
01311   */
01312 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01313 {
01314   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01315 }
01316
01317 /**
01318   * @brief  Disable Address match interrupt (slave mode only).
01319   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01320   * @param  I2Cx I2C Instance.
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01324 {
01325   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01326 }
01327
01328 /**
01329   * @brief  Check if Address match interrupt is enabled or disabled.
01330   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01331   * @param  I2Cx I2C Instance.
01332   * @retval State of bit (1 or 0).
01333   */
01334 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01335 {
01336   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
01337 }
01338
01339 /**
01340   * @brief  Enable Not acknowledge received interrupt.
01341   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01342   * @param  I2Cx I2C Instance.
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01346 {
01347   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01348 }
01349
01350 /**
01351   * @brief  Disable Not acknowledge received interrupt.
01352   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01353   * @param  I2Cx I2C Instance.
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01357 {
01358   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01359 }
01360
01361 /**
01362   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01363   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01364   * @param  I2Cx I2C Instance.
01365   * @retval State of bit (1 or 0).
01366   */
01367 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01368 {
01369   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
01370 }
01371
01372 /**
01373   * @brief  Enable STOP detection interrupt.
01374   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01375   * @param  I2Cx I2C Instance.
01376   * @retval None
01377   */
01378 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01379 {
01380   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01381 }
01382
01383 /**
01384   * @brief  Disable STOP detection interrupt.
01385   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01386   * @param  I2Cx I2C Instance.
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01390 {
01391   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01392 }
01393
01394 /**
01395   * @brief  Check if STOP detection interrupt is enabled or disabled.
01396   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01397   * @param  I2Cx I2C Instance.
01398   * @retval State of bit (1 or 0).
01399   */
01400 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01401 {
01402   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
01403 }
01404
01405 /**
01406   * @brief  Enable Transfer Complete interrupt.
01407   * @note   Any of these events will generate interrupt :
01408   *         Transfer Complete (TC)
01409   *         Transfer Complete Reload (TCR)
01410   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01411   * @param  I2Cx I2C Instance.
01412   * @retval None
01413   */
01414 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01415 {
01416   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01417 }
01418
01419 /**
01420   * @brief  Disable Transfer Complete interrupt.
01421   * @note   Any of these events will generate interrupt :
01422   *         Transfer Complete (TC)
01423   *         Transfer Complete Reload (TCR)
01424   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01425   * @param  I2Cx I2C Instance.
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01429 {
01430   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01431 }
01432
01433 /**
01434   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01435   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01436   * @param  I2Cx I2C Instance.
01437   * @retval State of bit (1 or 0).
01438   */
01439 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01440 {
01441   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
01442 }
01443
01444 /**
01445   * @brief  Enable Error interrupts.
01446   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01447   *         SMBus feature is supported by the I2Cx Instance.
01448   * @note   Any of these errors will generate interrupt :
01449   *         Arbitration Loss (ARLO)
01450   *         Bus Error detection (BERR)
01451   *         Overrun/Underrun (OVR)
01452   *         SMBus Timeout detection (TIMEOUT)
01453   *         SMBus PEC error detection (PECERR)
01454   *         SMBus Alert pin event detection (ALERT)
01455   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01456   * @param  I2Cx I2C Instance.
01457   * @retval None
01458   */
01459 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01460 {
01461   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01462 }
01463
01464 /**
01465   * @brief  Disable Error interrupts.
01466   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01467   *         SMBus feature is supported by the I2Cx Instance.
01468   * @note   Any of these errors will generate interrupt :
01469   *         Arbitration Loss (ARLO)
01470   *         Bus Error detection (BERR)
01471   *         Overrun/Underrun (OVR)
01472   *         SMBus Timeout detection (TIMEOUT)
01473   *         SMBus PEC error detection (PECERR)
01474   *         SMBus Alert pin event detection (ALERT)
01475   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01476   * @param  I2Cx I2C Instance.
01477   * @retval None
01478   */
01479 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01480 {
01481   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01482 }
01483
01484 /**
01485   * @brief  Check if Error interrupts are enabled or disabled.
01486   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01487   * @param  I2Cx I2C Instance.
01488   * @retval State of bit (1 or 0).
01489   */
01490 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01491 {
01492   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
01493 }
01494
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01500   * @{
01501   */
01502
01503 /**
01504   * @brief  Indicate the status of Transmit data register empty flag.
01505   * @note   RESET: When next data is written in Transmit data register.
01506   *         SET: When Transmit data register is empty.
01507   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01508   * @param  I2Cx I2C Instance.
01509   * @retval State of bit (1 or 0).
01510   */
01511 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01512 {
01513   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
01514 }
01515
01516 /**
01517   * @brief  Indicate the status of Transmit interrupt flag.
01518   * @note   RESET: When next data is written in Transmit data register.
01519   *         SET: When Transmit data register is empty.
01520   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01521   * @param  I2Cx I2C Instance.
01522   * @retval State of bit (1 or 0).
01523   */
01524 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01525 {
01526   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
01527 }
01528
01529 /**
01530   * @brief  Indicate the status of Receive data register not empty flag.
01531   * @note   RESET: When Receive data register is read.
01532   *         SET: When the received data is copied in Receive data register.
01533   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01534   * @param  I2Cx I2C Instance.
01535   * @retval State of bit (1 or 0).
01536   */
01537 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01538 {
01539   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
01540 }
01541
01542 /**
01543   * @brief  Indicate the status of Address matched flag (slave mode).
01544   * @note   RESET: Clear default value.
01545   *         SET: When the received slave address matched with one of the enabled slave address.
01546   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01547   * @param  I2Cx I2C Instance.
01548   * @retval State of bit (1 or 0).
01549   */
01550 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01551 {
01552   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
01553 }
01554
01555 /**
01556   * @brief  Indicate the status of Not Acknowledge received flag.
01557   * @note   RESET: Clear default value.
01558   *         SET: When a NACK is received after a byte transmission.
01559   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01560   * @param  I2Cx I2C Instance.
01561   * @retval State of bit (1 or 0).
01562   */
01563 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01564 {
01565   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
01566 }
01567
01568 /**
01569   * @brief  Indicate the status of Stop detection flag.
01570   * @note   RESET: Clear default value.
01571   *         SET: When a Stop condition is detected.
01572   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01573   * @param  I2Cx I2C Instance.
01574   * @retval State of bit (1 or 0).
01575   */
01576 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01577 {
01578   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
01579 }
01580
01581 /**
01582   * @brief  Indicate the status of Transfer complete flag (master mode).
01583   * @note   RESET: Clear default value.
01584   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01585   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01586   * @param  I2Cx I2C Instance.
01587   * @retval State of bit (1 or 0).
01588   */
01589 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01590 {
01591   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
01592 }
01593
01594 /**
01595   * @brief  Indicate the status of Transfer complete flag (master mode).
01596   * @note   RESET: Clear default value.
01597   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01598   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01599   * @param  I2Cx I2C Instance.
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01603 {
01604   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Indicate the status of Bus error flag.
01609   * @note   RESET: Clear default value.
01610   *         SET: When a misplaced Start or Stop condition is detected.
01611   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01612   * @param  I2Cx I2C Instance.
01613   * @retval State of bit (1 or 0).
01614   */
01615 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01616 {
01617   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
01618 }
01619
01620 /**
01621   * @brief  Indicate the status of Arbitration lost flag.
01622   * @note   RESET: Clear default value.
01623   *         SET: When arbitration lost.
01624   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01625   * @param  I2Cx I2C Instance.
01626   * @retval State of bit (1 or 0).
01627   */
01628 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01629 {
01630   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
01631 }
01632
01633 /**
01634   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01635   * @note   RESET: Clear default value.
01636   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01637   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01638   * @param  I2Cx I2C Instance.
01639   * @retval State of bit (1 or 0).
01640   */
01641 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01642 {
01643   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
01644 }
01645
01646 /**
01647   * @brief  Indicate the status of SMBus PEC error flag in reception.
01648   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01649   *         SMBus feature is supported by the I2Cx Instance.
01650   * @note   RESET: Clear default value.
01651   *         SET: When the received PEC does not match with the PEC register content.
01652   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01653   * @param  I2Cx I2C Instance.
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01657 {
01658   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Indicate the status of SMBus Timeout detection flag.
01663   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01664   *         SMBus feature is supported by the I2Cx Instance.
01665   * @note   RESET: Clear default value.
01666   *         SET: When a timeout or extended clock timeout occurs.
01667   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01668   * @param  I2Cx I2C Instance.
01669   * @retval State of bit (1 or 0).
01670   */
01671 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01672 {
01673   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
01674 }
01675
01676 /**
01677   * @brief  Indicate the status of SMBus alert flag.
01678   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01679   *         SMBus feature is supported by the I2Cx Instance.
01680   * @note   RESET: Clear default value.
01681   *         SET: When SMBus host configuration, SMBus alert enabled and
01682   *              a falling edge event occurs on SMBA pin.
01683   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01684   * @param  I2Cx I2C Instance.
01685   * @retval State of bit (1 or 0).
01686   */
01687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01688 {
01689   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
01690 }
01691
01692 /**
01693   * @brief  Indicate the status of Bus Busy flag.
01694   * @note   RESET: Clear default value.
01695   *         SET: When a Start condition is detected.
01696   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01697   * @param  I2Cx I2C Instance.
01698   * @retval State of bit (1 or 0).
01699   */
01700 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01701 {
01702   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
01703 }
01704
01705 /**
01706   * @brief  Clear Address Matched flag.
01707   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01708   * @param  I2Cx I2C Instance.
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01712 {
01713   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01714 }
01715
01716 /**
01717   * @brief  Clear Not Acknowledge flag.
01718   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01719   * @param  I2Cx I2C Instance.
01720   * @retval None
01721   */
01722 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01723 {
01724   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01725 }
01726
01727 /**
01728   * @brief  Clear Stop detection flag.
01729   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01730   * @param  I2Cx I2C Instance.
01731   * @retval None
01732   */
01733 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01734 {
01735   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01736 }
01737
01738 /**
01739   * @brief  Clear Transmit data register empty flag (TXE).
01740   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01741   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01742   * @param  I2Cx I2C Instance.
01743   * @retval None
01744   */
01745 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01746 {
01747   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01748 }
01749
01750 /**
01751   * @brief  Clear Bus error flag.
01752   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01753   * @param  I2Cx I2C Instance.
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01757 {
01758   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01759 }
01760
01761 /**
01762   * @brief  Clear Arbitration lost flag.
01763   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01764   * @param  I2Cx I2C Instance.
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01768 {
01769   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01770 }
01771
01772 /**
01773   * @brief  Clear Overrun/Underrun flag.
01774   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01775   * @param  I2Cx I2C Instance.
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01779 {
01780   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01781 }
01782
01783 /**
01784   * @brief  Clear SMBus PEC error flag.
01785   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01786   *         SMBus feature is supported by the I2Cx Instance.
01787   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01788   * @param  I2Cx I2C Instance.
01789   * @retval None
01790   */
01791 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01792 {
01793   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01794 }
01795
01796 /**
01797   * @brief  Clear SMBus Timeout detection flag.
01798   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01799   *         SMBus feature is supported by the I2Cx Instance.
01800   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01801   * @param  I2Cx I2C Instance.
01802   * @retval None
01803   */
01804 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01805 {
01806   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01807 }
01808
01809 /**
01810   * @brief  Clear SMBus Alert flag.
01811   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01812   *         SMBus feature is supported by the I2Cx Instance.
01813   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01814   * @param  I2Cx I2C Instance.
01815   * @retval None
01816   */
01817 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01818 {
01819   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01820 }
01821
01822 /**
01823   * @}
01824   */
01825
01826 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01827   * @{
01828   */
01829
01830 /**
01831   * @brief  Enable automatic STOP condition generation (master mode).
01832   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01833   *         This bit has no effect in slave mode or when RELOAD bit is set.
01834   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01835   * @param  I2Cx I2C Instance.
01836   * @retval None
01837   */
01838 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01839 {
01840   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01841 }
01842
01843 /**
01844   * @brief  Disable automatic STOP condition generation (master mode).
01845   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01846   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01847   * @param  I2Cx I2C Instance.
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01851 {
01852   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01853 }
01854
01855 /**
01856   * @brief  Check if automatic STOP condition is enabled or disabled.
01857   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01858   * @param  I2Cx I2C Instance.
01859   * @retval State of bit (1 or 0).
01860   */
01861 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01862 {
01863   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
01864 }
01865
01866 /**
01867   * @brief  Enable reload mode (master mode).
01868   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01869   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01870   * @param  I2Cx I2C Instance.
01871   * @retval None
01872   */
01873 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01874 {
01875   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01876 }
01877
01878 /**
01879   * @brief  Disable reload mode (master mode).
01880   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01881   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01882   * @param  I2Cx I2C Instance.
01883   * @retval None
01884   */
01885 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01886 {
01887   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01888 }
01889
01890 /**
01891   * @brief  Check if reload mode is enabled or disabled.
01892   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01893   * @param  I2Cx I2C Instance.
01894   * @retval State of bit (1 or 0).
01895   */
01896 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01897 {
01898   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
01899 }
01900
01901 /**
01902   * @brief  Configure the number of bytes for transfer.
01903   * @note   Changing these bits when START bit is set is not allowed.
01904   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01905   * @param  I2Cx I2C Instance.
01906   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01907   * @retval None
01908   */
01909 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01910 {
01911   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
01912 }
01913
01914 /**
01915   * @brief  Get the number of bytes configured for transfer.
01916   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01917   * @param  I2Cx I2C Instance.
01918   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01919   */
01920 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01921 {
01922   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
01923 }
01924
01925 /**
01926   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01927   * @note   Usage in Slave mode only.
01928   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01929   * @param  I2Cx I2C Instance.
01930   * @param  TypeAcknowledge This parameter can be one of the following values:
01931   *         @arg @ref LL_I2C_ACK
01932   *         @arg @ref LL_I2C_NACK
01933   * @retval None
01934   */
01935 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01936 {
01937   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01938 }
01939
01940 /**
01941   * @brief  Generate a START or RESTART condition
01942   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01943   *         This action has no effect when RELOAD is set.
01944   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01945   * @param  I2Cx I2C Instance.
01946   * @retval None
01947   */
01948 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01949 {
01950   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01951 }
01952
01953 /**
01954   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01955   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01956   * @param  I2Cx I2C Instance.
01957   * @retval None
01958   */
01959 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01960 {
01961   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
01962 }
01963
01964 /**
01965   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
01966   * @note   The master sends the complete 10bit slave address read sequence :
01967   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
01968   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
01969   * @param  I2Cx I2C Instance.
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
01973 {
01974   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
01975 }
01976
01977 /**
01978   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
01979   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
01980   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
01981   * @param  I2Cx I2C Instance.
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
01985 {
01986   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
01987 }
01988
01989 /**
01990   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
01991   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
01992   * @param  I2Cx I2C Instance.
01993   * @retval State of bit (1 or 0).
01994   */
01995 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
01996 {
01997   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
01998 }
01999
02000 /**
02001   * @brief  Configure the transfer direction (master mode).
02002   * @note   Changing these bits when START bit is set is not allowed.
02003   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02004   * @param  I2Cx I2C Instance.
02005   * @param  TransferRequest This parameter can be one of the following values:
02006   *         @arg @ref LL_I2C_REQUEST_WRITE
02007   *         @arg @ref LL_I2C_REQUEST_READ
02008   * @retval None
02009   */
02010 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02011 {
02012   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02013 }
02014
02015 /**
02016   * @brief  Get the transfer direction requested (master mode).
02017   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02018   * @param  I2Cx I2C Instance.
02019   * @retval Returned value can be one of the following values:
02020   *         @arg @ref LL_I2C_REQUEST_WRITE
02021   *         @arg @ref LL_I2C_REQUEST_READ
02022   */
02023 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02024 {
02025   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02026 }
02027
02028 /**
02029   * @brief  Configure the slave address for transfer (master mode).
02030   * @note   Changing these bits when START bit is set is not allowed.
02031   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02032   * @param  I2Cx I2C Instance.
02033   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02034   * @retval None
02035   */
02036 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02037 {
02038   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02039 }
02040
02041 /**
02042   * @brief  Get the slave address programmed for transfer.
02043   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02044   * @param  I2Cx I2C Instance.
02045   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02046   */
02047 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02048 {
02049   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02050 }
02051
02052 /**
02053   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02054   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02055   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02056   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02057   *         CR2          START         LL_I2C_HandleTransfer\n
02058   *         CR2          STOP          LL_I2C_HandleTransfer\n
02059   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02060   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02061   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02062   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02063   * @param  I2Cx I2C Instance.
02064   * @param  SlaveAddr Specifies the slave address to be programmed.
02065   * @param  SlaveAddrSize This parameter can be one of the following values:
02066   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02067   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02068   * @param  TransferSize Specifies the number of bytes to be programmed.
02069   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
02070   * @param  EndMode This parameter can be one of the following values:
02071   *         @arg @ref LL_I2C_MODE_RELOAD
02072   *         @arg @ref LL_I2C_MODE_AUTOEND
02073   *         @arg @ref LL_I2C_MODE_SOFTEND
02074   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02075   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02076   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02077   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02078   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02079   * @param  Request This parameter can be one of the following values:
02080   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02081   *         @arg @ref LL_I2C_GENERATE_STOP
02082   *         @arg @ref LL_I2C_GENERATE_START_READ
02083   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02084   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02085   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02086   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02087   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02091                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02092 {
02093   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02094              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02095              SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
02096 }
02097
02098 /**
02099   * @brief  Indicate the value of transfer direction (slave mode).
02100   * @note   RESET: Write transfer, Slave enters in receiver mode.
02101   *         SET: Read transfer, Slave enters in transmitter mode.
02102   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02103   * @param  I2Cx I2C Instance.
02104   * @retval Returned value can be one of the following values:
02105   *         @arg @ref LL_I2C_DIRECTION_WRITE
02106   *         @arg @ref LL_I2C_DIRECTION_READ
02107   */
02108 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02109 {
02110   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02111 }
02112
02113 /**
02114   * @brief  Return the slave matched address.
02115   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02116   * @param  I2Cx I2C Instance.
02117   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02118   */
02119 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02120 {
02121   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
02122 }
02123
02124 /**
02125   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
02126   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02127   *         SMBus feature is supported by the I2Cx Instance.
02128   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
02129   *         This bit has no effect when RELOAD bit is set.
02130   *         This bit has no effect in device mode when SBC bit is not set.
02131   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02132   * @param  I2Cx I2C Instance.
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02136 {
02137   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02138 }
02139
02140 /**
02141   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
02142   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02143   *         SMBus feature is supported by the I2Cx Instance.
02144   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02145   * @param  I2Cx I2C Instance.
02146   * @retval State of bit (1 or 0).
02147   */
02148 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02149 {
02150   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
02151 }
02152
02153 /**
02154   * @brief  Get the SMBus Packet Error byte calculated.
02155   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02156   *         SMBus feature is supported by the I2Cx Instance.
02157   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02158   * @param  I2Cx I2C Instance.
02159   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02160 */
02161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02162 {
02163   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02164 }
02165
02166 /**
02167   * @brief  Read Receive Data register.
02168   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02169   * @param  I2Cx I2C Instance.
02170   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02171   */
02172 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02173 {
02174   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02175 }
02176
02177 /**
02178   * @brief  Write in Transmit Data Register .
02179   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02180   * @param  I2Cx I2C Instance.
02181   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02182   * @retval None
02183   */
02184 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02185 {
02186   WRITE_REG(I2Cx->TXDR, Data);
02187 }
02188
02189 /**
02190   * @}
02191   */
02192
02193 #if defined(USE_FULL_LL_DRIVER)
02194 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02195   * @{
02196   */
02197
02198 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02199 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02200 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02201
02202
02203 /**
02204   * @}
02205   */
02206 #endif /* USE_FULL_LL_DRIVER */
02207
02208 /**
02209   * @}
02210   */
02211
02212 /**
02213   * @}
02214   */
02215
02216 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
02217
02218 /**
02219   * @}
02220   */
02221
02222 #ifdef __cplusplus
02223 }
02224 #endif
02225
02226 #endif /* STM32H7xx_LL_I2C_H */
02227
02228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_iwdg.h Source File

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stm32h7xx_ll_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_IWDG_H
00022 #define STM32H7xx_LL_IWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(IWDG1) || defined(IWDG2)
00036
00037 /** @defgroup IWDG_LL IWDG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00046   * @{
00047   */
00048 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00049 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00050 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00051 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00065   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00066   * @{
00067   */
00068 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00069 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00070 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00076   * @{
00077   */
00078 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00079 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00080 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00081 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00082 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00083 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00084 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported macro ------------------------------------------------------------*/
00094 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00095   * @{
00096   */
00097
00098 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Write a value in IWDG register
00104   * @param  __INSTANCE__ IWDG Instance
00105   * @param  __REG__ Register to be written
00106   * @param  __VALUE__ Value to be written in the register
00107   * @retval None
00108   */
00109 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00110
00111 /**
00112   * @brief  Read a value in IWDG register
00113   * @param  __INSTANCE__ IWDG Instance
00114   * @param  __REG__ Register to be read
00115   * @retval Register value
00116   */
00117 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126
00127 /* Exported functions --------------------------------------------------------*/
00128 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00129   * @{
00130   */
00131 /** @defgroup IWDG_LL_EF_Configuration Configuration
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  Start the Independent Watchdog
00137   * @note   Except if the hardware watchdog option is selected
00138   * @rmtoll KR           KEY           LL_IWDG_Enable
00139   * @param  IWDGx IWDG Instance
00140   * @retval None
00141   */
00142 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00143 {
00144   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
00145 }
00146
00147 /**
00148   * @brief  Reloads IWDG counter with value defined in the reload register
00149   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00150   * @param  IWDGx IWDG Instance
00151   * @retval None
00152   */
00153 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00154 {
00155   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
00156 }
00157
00158 /**
00159   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00160   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00161   * @param  IWDGx IWDG Instance
00162   * @retval None
00163   */
00164 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00165 {
00166   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00167 }
00168
00169 /**
00170   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00171   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00172   * @param  IWDGx IWDG Instance
00173   * @retval None
00174   */
00175 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00176 {
00177   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00178 }
00179
00180 /**
00181   * @brief  Select the prescaler of the IWDG
00182   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00183   * @param  IWDGx IWDG Instance
00184   * @param  Prescaler This parameter can be one of the following values:
00185   *         @arg @ref LL_IWDG_PRESCALER_4
00186   *         @arg @ref LL_IWDG_PRESCALER_8
00187   *         @arg @ref LL_IWDG_PRESCALER_16
00188   *         @arg @ref LL_IWDG_PRESCALER_32
00189   *         @arg @ref LL_IWDG_PRESCALER_64
00190   *         @arg @ref LL_IWDG_PRESCALER_128
00191   *         @arg @ref LL_IWDG_PRESCALER_256
00192   * @retval None
00193   */
00194 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00195 {
00196   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00197 }
00198
00199 /**
00200   * @brief  Get the selected prescaler of the IWDG
00201   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00202   * @param  IWDGx IWDG Instance
00203   * @retval Returned value can be one of the following values:
00204   *         @arg @ref LL_IWDG_PRESCALER_4
00205   *         @arg @ref LL_IWDG_PRESCALER_8
00206   *         @arg @ref LL_IWDG_PRESCALER_16
00207   *         @arg @ref LL_IWDG_PRESCALER_32
00208   *         @arg @ref LL_IWDG_PRESCALER_64
00209   *         @arg @ref LL_IWDG_PRESCALER_128
00210   *         @arg @ref LL_IWDG_PRESCALER_256
00211   */
00212 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00213 {
00214   return (READ_REG(IWDGx->PR));
00215 }
00216
00217 /**
00218   * @brief  Specify the IWDG down-counter reload value
00219   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00220   * @param  IWDGx IWDG Instance
00221   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00222   * @retval None
00223   */
00224 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00225 {
00226   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00227 }
00228
00229 /**
00230   * @brief  Get the specified IWDG down-counter reload value
00231   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00232   * @param  IWDGx IWDG Instance
00233   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00234   */
00235 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00236 {
00237   return (READ_REG(IWDGx->RLR));
00238 }
00239
00240 /**
00241   * @brief  Specify high limit of the window value to be compared to the down-counter.
00242   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00243   * @param  IWDGx IWDG Instance
00244   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00245   * @retval None
00246   */
00247 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00248 {
00249   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00250 }
00251
00252 /**
00253   * @brief  Get the high limit of the window value specified.
00254   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00255   * @param  IWDGx IWDG Instance
00256   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00257   */
00258 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
00259 {
00260   return (READ_REG(IWDGx->WINR));
00261 }
00262
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00268   * @{
00269   */
00270
00271 /**
00272   * @brief  Check if flag Prescaler Value Update is set or not
00273   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00274   * @param  IWDGx IWDG Instance
00275   * @retval State of bit (1 or 0).
00276   */
00277 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00278 {
00279   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
00280 }
00281
00282 /**
00283   * @brief  Check if flag Reload Value Update is set or not
00284   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00285   * @param  IWDGx IWDG Instance
00286   * @retval State of bit (1 or 0).
00287   */
00288 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00289 {
00290   return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
00291 }
00292
00293 /**
00294   * @brief  Check if flag Window Value Update is set or not
00295   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00296   * @param  IWDGx IWDG Instance
00297   * @retval State of bit (1 or 0).
00298   */
00299 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
00300 {
00301   return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
00302 }
00303
00304 /**
00305   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00306   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00307   *         SR           WVU           LL_IWDG_IsReady\n
00308   *         SR           RVU           LL_IWDG_IsReady
00309   * @param  IWDGx IWDG Instance
00310   * @retval State of bits (1 or 0).
00311   */
00312 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00313 {
00314   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
00315 }
00316
00317 /**
00318   * @}
00319   */
00320
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 #endif /* IWDG1 || IWDG2 */
00331
00332 /**
00333   * @}
00334   */
00335
00336 #ifdef __cplusplus
00337 }
00338 #endif
00339
00340 #endif /* STM32H7xx_LL_IWDG_H */
00341
00342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lptim.c Source File

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stm32h7xx_ll_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_lptim.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #include "stm32h7xx_ll_rcc.h"
00025
00026
00027 #ifdef  USE_FULL_ASSERT
00028 #include "stm32_assert.h"
00029 #else
00030 #define assert_param(expr) ((void)0U)
00031 #endif
00032
00033 /** @addtogroup STM32H7xx_LL_Driver
00034   * @{
00035   */
00036
00037 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
00038
00039 /** @addtogroup LPTIM_LL
00040   * @{
00041   */
00042
00043 /* Private types -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 /* Private constants ---------------------------------------------------------*/
00046 /* Private macros ------------------------------------------------------------*/
00047 /** @addtogroup LPTIM_LL_Private_Macros
00048   * @{
00049   */
00050 #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
00051                                           || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
00052
00053 #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
00054                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
00055                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
00056                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
00057                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
00058                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
00059                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
00060                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
00061
00062 #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
00063                                       || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
00064
00065 #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
00066                                              || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
00067 /**
00068   * @}
00069   */
00070
00071
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Private functions ---------------------------------------------------------*/
00074 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080 /* Exported functions --------------------------------------------------------*/
00081 /** @addtogroup LPTIM_LL_Exported_Functions
00082   * @{
00083   */
00084
00085 /** @addtogroup LPTIM_LL_EF_Init
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Set LPTIMx registers to their reset values.
00091   * @param  LPTIMx LP Timer instance
00092   * @retval An ErrorStatus enumeration value:
00093   *          - SUCCESS: LPTIMx registers are de-initialized
00094   *          - ERROR: invalid LPTIMx instance
00095   */
00096 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
00097 {
00098   ErrorStatus result = SUCCESS;
00099
00100   /* Check the parameters */
00101   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00102
00103   if (LPTIMx == LPTIM1)
00104   {
00105     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00106     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00107   }
00108   else if (LPTIMx == LPTIM2)
00109   {
00110     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2);
00111     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2);
00112   }
00113 #if defined(LPTIM3)
00114   else if (LPTIMx == LPTIM3)
00115   {
00116     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3);
00117     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3);
00118   }
00119 #endif /* LPTIM3 */
00120 #if defined(LPTIM4)
00121   else if (LPTIMx == LPTIM4)
00122   {
00123     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4);
00124     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4);
00125   }
00126 #endif /* LPTIM4 */
00127 #if defined(LPTIM5)
00128   else if (LPTIMx == LPTIM5)
00129   {
00130     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5);
00131     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5);
00132   }
00133 #endif /* LPTIM5 */
00134   else
00135   {
00136     result = ERROR;
00137   }
00138
00139   return result;
00140 }
00141
00142 /**
00143   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
00144   *         value.
00145   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00146   * @retval None
00147   */
00148 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00149 {
00150   /* Set the default configuration */
00151   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
00152   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
00153   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
00154   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
00155 }
00156
00157 /**
00158   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
00159   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
00160   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
00161   * @param  LPTIMx LP Timer Instance
00162   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00163   * @retval An ErrorStatus enumeration value:
00164   *          - SUCCESS: LPTIMx instance has been initialized
00165   *          - ERROR: LPTIMx instance hasn't been initialized
00166   */
00167 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00168 {
00169   ErrorStatus result = SUCCESS;
00170   /* Check the parameters */
00171   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00172   assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
00173   assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
00174   assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
00175   assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
00176
00177   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
00178      (ENABLE bit is reset to 0).
00179   */
00180   if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
00181   {
00182     result = ERROR;
00183   }
00184   else
00185   {
00186     /* Set CKSEL bitfield according to ClockSource value */
00187     /* Set PRESC bitfield according to Prescaler value */
00188     /* Set WAVE bitfield according to Waveform value */
00189     /* Set WAVEPOL bitfield according to Polarity value */
00190     MODIFY_REG(LPTIMx->CFGR,
00191                (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
00192                LPTIM_InitStruct->ClockSource | \
00193                LPTIM_InitStruct->Prescaler | \
00194                LPTIM_InitStruct->Waveform | \
00195                LPTIM_InitStruct->Polarity);
00196   }
00197
00198   return result;
00199 }
00200
00201 /**
00202   * @brief  Disable the LPTIM instance
00203   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
00204   * @param  LPTIMx Low-Power Timer instance
00205   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00206   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00207   *         stuck in LPTIM interrupt when entering Stop mode" section.
00208   * @retval None
00209   */
00210 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
00211 {
00212   LL_RCC_ClocksTypeDef rcc_clock;
00213   uint32_t tmpclksource = 0;
00214   uint32_t tmpIER;
00215   uint32_t tmpCFGR;
00216   uint32_t tmpCMP;
00217   uint32_t tmpARR;
00218   uint32_t tmpCFGR2;
00219
00220   /* Check the parameters */
00221   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00222
00223   __disable_irq();
00224
00225   /********** Save LPTIM Config *********/
00226   /* Save LPTIM source clock */
00227   switch ((uint32_t)LPTIMx)
00228   {
00229      case LPTIM1_BASE:
00230        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
00231        break;
00232      case LPTIM2_BASE:
00233        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
00234        break;
00235 #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
00236      case LPTIM3_BASE:
00237      case LPTIM4_BASE:
00238      case LPTIM5_BASE:
00239        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
00240        break;
00241 #elif defined(LPTIM3)
00242      case LPTIM3_BASE:
00243        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
00244        break;
00245 #endif /* LPTIM3 && LPTIM4 && LPTIM5 */
00246      default:
00247        break;
00248   }
00249
00250   /* Save LPTIM configuration registers */
00251   tmpIER = LPTIMx->IER;
00252   tmpCFGR = LPTIMx->CFGR;
00253   tmpCMP = LPTIMx->CMP;
00254   tmpARR = LPTIMx->ARR;
00255   tmpCFGR2 = LPTIMx->CFGR2;
00256
00257   /************* Reset LPTIM ************/
00258   (void)LL_LPTIM_DeInit(LPTIMx);
00259
00260   /********* Restore LPTIM Config *******/
00261   LL_RCC_GetSystemClocksFreq(&rcc_clock);
00262
00263   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
00264   {
00265     /* Force LPTIM source kernel clock from APB */
00266     switch ((uint32_t)LPTIMx)
00267     {
00268        case LPTIM1_BASE:
00269          LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
00270          break;
00271        case LPTIM2_BASE:
00272          LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
00273          break;
00274 #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
00275        case LPTIM3_BASE:
00276        case LPTIM4_BASE:
00277        case LPTIM5_BASE:
00278          LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
00279          break;
00280 #elif defined(LPTIM3)
00281      case LPTIM3_BASE:
00282        LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
00283        break;
00284 #endif /* LPTIM3 && LPTIM4 && LPTIM5*/
00285        default:
00286          break;
00287     }
00288
00289     if (tmpCMP != 0UL)
00290     {
00291       /* Restore CMP and ARR registers (LPTIM should be enabled first) */
00292       LPTIMx->CR |= LPTIM_CR_ENABLE;
00293       LPTIMx->CMP = tmpCMP;
00294
00295       /* Polling on CMP write ok status after above restore operation */
00296       do
00297       {
00298         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00299       } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00300
00301       LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
00302     }
00303
00304     if (tmpARR != 0UL)
00305     {
00306       LPTIMx->CR |= LPTIM_CR_ENABLE;
00307       LPTIMx->ARR = tmpARR;
00308
00309       LL_RCC_GetSystemClocksFreq(&rcc_clock);
00310       /* Polling on ARR write ok status after above restore operation */
00311       do
00312       {
00313         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00314       } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00315
00316       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
00317     }
00318
00319
00320     /* Restore LPTIM source kernel clock */
00321     LL_RCC_SetLPTIMClockSource(tmpclksource);
00322   }
00323
00324   /* Restore configuration registers (LPTIM should be disabled first) */
00325   LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
00326   LPTIMx->IER = tmpIER;
00327   LPTIMx->CFGR = tmpCFGR;
00328   LPTIMx->CFGR2 = tmpCFGR2;
00329
00330   __enable_irq();
00331 }
00332
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 #endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */
00346
00347 /**
00348   * @}
00349   */
00350
00351 #endif /* USE_FULL_LL_DRIVER */
00352
00353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lptim.h Source File

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stm32h7xx_ll_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_LPTIM_H
00022 #define STM32H7xx_LL_LPTIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
00036
00037 /** @defgroup LPTIM_LL LPTIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045
00046 /* Private macros ------------------------------------------------------------*/
00047 #if defined(USE_FULL_LL_DRIVER)
00048 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
00049   * @{
00050   */
00051 /**
00052   * @}
00053   */
00054 #endif /*USE_FULL_LL_DRIVER*/
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 #if defined(USE_FULL_LL_DRIVER)
00058 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  LPTIM Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
00068                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
00069
00070                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
00071
00072   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
00073                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
00074
00075                                 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
00076
00077   uint32_t Waveform;       /*!< Specifies the waveform shape.
00078                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
00079
00080                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00081
00082   uint32_t Polarity;       /*!< Specifies waveform polarity.
00083                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
00084
00085                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00086 } LL_LPTIM_InitTypeDef;
00087
00088 /**
00089   * @}
00090   */
00091 #endif /* USE_FULL_LL_DRIVER */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
00099   * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
00100   * @{
00101   */
00102 #define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
00103 #define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
00104 #define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
00105 #define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
00106 #define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
00107 #define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
00108 #define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup LPTIM_LL_EC_IT IT Defines
00114   * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
00115   * @{
00116   */
00117 #define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */
00118 #define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */
00119 #define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */
00120 #define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */
00121 #define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */
00122 #define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */
00123 #define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
00129   * @{
00130   */
00131 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
00132 #define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
00138   * @{
00139   */
00140 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
00141 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
00147   * @{
00148   */
00149 #define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
00150 #define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
00156   * @{
00157   */
00158 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
00159 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
00165   * @{
00166   */
00167 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00168 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
00174   * @{
00175   */
00176 #define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
00177 #define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
00178 #define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
00179 #define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
00180 #define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
00181 #define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
00182 #define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
00183 #define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
00189   * @{
00190   */
00191 #define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
00192 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
00193 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
00194 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
00195 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
00196 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
00197 #define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/
00198 #define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/
00199 #define LL_LPTIM_TRIG_SOURCE_LPTIM2           0x00000000U                                                          /*!<External input trigger is connected to LPTIM2 output*/
00200 #define LL_LPTIM_TRIG_SOURCE_LPTIM3           LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to LPTIM3 output*/
00201 #define LL_LPTIM_TRIG_SOURCE_LPTIM4           LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to LPTIM4 output*/
00202 #define LL_LPTIM_TRIG_SOURCE_LPTIM5           (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to LPTIM5 output*/
00203 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI1 FS A output*/
00204 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI1 FS B output*/
00205 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI2 FS A output*/
00206 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI2 FS B output*/
00207 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A        (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI4 FS A output*/
00208 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI4 FS B output*/
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
00214   * @{
00215   */
00216 #define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
00217 #define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
00218 #define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
00219 #define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
00225   * @{
00226   */
00227 #define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
00228 #define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
00229 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
00235   * @{
00236   */
00237 #define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
00238 #define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
00244   * @{
00245   */
00246 #define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
00247 #define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
00248 #define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
00249 #define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
00255   * @{
00256   */
00257 #define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00258 #define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00259 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
00265   * @{
00266   */
00267 #define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00268 #define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00269 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
00275   * @{
00276   */
00277 #define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U                                            /*!< For LPTIM1 and LPTIM2 */
00278 #define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_CFGR2_IN1SEL_0                                   /*!< For LPTIM1 and LPTIM2 */
00279 #define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_CFGR2_IN1SEL_1                                   /*!< For LPTIM2 */
00280 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)          /*!< For LPTIM2 */
00281 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_A    LPTIM_CFGR2_IN1SEL_0                                   /*!< For LPTIM3 */
00282 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_B    LPTIM_CFGR2_IN1SEL_1                                   /*!< For LPTIM3 */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
00288   * @{
00289   */
00290 #define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U                   /*!< For LPTIM1 */
00291 #define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_CFGR2_IN2SEL_0          /*!< For LPTIM1 */
00292 /**
00293   * @}
00294   */
00295
00296 /**
00297   * @}
00298   */
00299
00300 /* Exported macro ------------------------------------------------------------*/
00301 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
00302   * @{
00303   */
00304
00305 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Write a value in LPTIM register
00311   * @param  __INSTANCE__ LPTIM Instance
00312   * @param  __REG__ Register to be written
00313   * @param  __VALUE__ Value to be written in the register
00314   * @retval None
00315   */
00316 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00317
00318 /**
00319   * @brief  Read a value in LPTIM register
00320   * @param  __INSTANCE__ LPTIM Instance
00321   * @param  __REG__ Register to be read
00322   * @retval Register value
00323   */
00324 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /* Exported functions --------------------------------------------------------*/
00334 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
00335   * @{
00336   */
00337
00338 #if defined(USE_FULL_LL_DRIVER)
00339 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
00340   * @{
00341   */
00342
00343 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
00344 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00345 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00346 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
00347 /**
00348   * @}
00349   */
00350 #endif /* USE_FULL_LL_DRIVER */
00351
00352 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
00353   * @{
00354   */
00355
00356 /**
00357   * @brief  Enable the LPTIM instance
00358   * @note After setting the ENABLE bit, a delay of two counter clock is needed
00359   *       before the LPTIM instance is actually enabled.
00360   * @rmtoll CR           ENABLE        LL_LPTIM_Enable
00361   * @param  LPTIMx Low-Power Timer instance
00362   * @retval None
00363   */
00364 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
00365 {
00366   SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00367 }
00368
00369 /**
00370   * @brief  Indicates whether the LPTIM instance is enabled.
00371   * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
00372   * @param  LPTIMx Low-Power Timer instance
00373   * @retval State of bit (1 or 0).
00374   */
00375 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
00376 {
00377   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
00378 }
00379
00380 /**
00381   * @brief  Starts the LPTIM counter in the desired mode.
00382   * @note LPTIM instance must be enabled before starting the counter.
00383   * @note It is possible to change on the fly from One Shot mode to
00384   *       Continuous mode.
00385   * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
00386   *         CR           SNGSTRT       LL_LPTIM_StartCounter
00387   * @param  LPTIMx Low-Power Timer instance
00388   * @param  OperatingMode This parameter can be one of the following values:
00389   *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
00390   *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
00391   * @retval None
00392   */
00393 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
00394 {
00395   MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
00396 }
00397
00398 /**
00399   * @brief  Enable reset after read.
00400   * @note After calling this function any read access to LPTIM_CNT
00401   *        register will asynchronously reset the LPTIM_CNT register content.
00402   * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead
00403   * @param  LPTIMx Low-Power Timer instance
00404   * @retval None
00405   */
00406 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00407 {
00408   SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00409 }
00410
00411 /**
00412   * @brief  Disable reset after read.
00413   * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead
00414   * @param  LPTIMx Low-Power Timer instance
00415   * @retval None
00416   */
00417 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00418 {
00419   CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00420 }
00421
00422 /**
00423   * @brief  Indicate whether the reset after read feature is enabled.
00424   * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead
00425   * @param  LPTIMx Low-Power Timer instance
00426   * @retval State of bit (1 or 0).
00427   */
00428 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
00429 {
00430   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
00431 }
00432
00433 /**
00434   * @brief  Reset of the LPTIM_CNT counter register (synchronous).
00435   * @note Due to the synchronous nature of this reset, it only takes
00436   *       place after a synchronization delay of 3 LPTIM core clock cycles
00437   *      (LPTIM core clock may be different from APB clock).
00438   * @note COUNTRST is automatically cleared by hardware
00439   * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n
00440   * @param  LPTIMx Low-Power Timer instance
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
00444 {
00445   SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
00446 }
00447
00448 /**
00449   * @brief  Set the LPTIM registers update mode (enable/disable register preload)
00450   * @note This function must be called when the LPTIM instance is disabled.
00451   * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
00452   * @param  LPTIMx Low-Power Timer instance
00453   * @param  UpdateMode This parameter can be one of the following values:
00454   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00455   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00456   * @retval None
00457   */
00458 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
00459 {
00460   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
00461 }
00462
00463 /**
00464   * @brief  Get the LPTIM registers update mode
00465   * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
00466   * @param  LPTIMx Low-Power Timer instance
00467   * @retval Returned value can be one of the following values:
00468   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00469   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00470   */
00471 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
00472 {
00473   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
00474 }
00475
00476 /**
00477   * @brief  Set the auto reload value
00478   * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
00479   * @note After a write to the LPTIMx_ARR register a new write operation to the
00480   *       same register can only be performed when the previous write operation
00481   *       is completed. Any successive write before  the ARROK flag is set, will
00482   *       lead to unpredictable results.
00483   * @note autoreload value be strictly greater than the compare value.
00484   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
00485   * @param  LPTIMx Low-Power Timer instance
00486   * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00487   * @retval None
00488   */
00489 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
00490 {
00491   MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
00492 }
00493
00494 /**
00495   * @brief  Get actual auto reload value
00496   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
00497   * @param  LPTIMx Low-Power Timer instance
00498   * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00499   */
00500 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
00501 {
00502   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
00503 }
00504
00505 /**
00506   * @brief  Set the compare value
00507   * @note After a write to the LPTIMx_CMP register a new write operation to the
00508   *       same register can only be performed when the previous write operation
00509   *       is completed. Any successive write before the CMPOK flag is set, will
00510   *       lead to unpredictable results.
00511   * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
00512   * @param  LPTIMx Low-Power Timer instance
00513   * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00514   * @retval None
00515   */
00516 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
00517 {
00518   MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
00519 }
00520
00521 /**
00522   * @brief  Get actual compare value
00523   * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
00524   * @param  LPTIMx Low-Power Timer instance
00525   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00526   */
00527 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
00528 {
00529   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
00530 }
00531
00532 /**
00533   * @brief  Get actual counter value
00534   * @note When the LPTIM instance is running with an asynchronous clock, reading
00535   *       the LPTIMx_CNT register may return unreliable values. So in this case
00536   *       it is necessary to perform two consecutive read accesses and verify
00537   *       that the two returned values are identical.
00538   * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
00539   * @param  LPTIMx Low-Power Timer instance
00540   * @retval Counter value
00541   */
00542 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
00543 {
00544   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
00545 }
00546
00547 /**
00548   * @brief  Set the counter mode (selection of the LPTIM counter clock source).
00549   * @note The counter mode can be set only when the LPTIM instance is disabled.
00550   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
00551   * @param  LPTIMx Low-Power Timer instance
00552   * @param  CounterMode This parameter can be one of the following values:
00553   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00554   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00555   * @retval None
00556   */
00557 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
00558 {
00559   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
00560 }
00561
00562 /**
00563   * @brief  Get the counter mode
00564   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
00565   * @param  LPTIMx Low-Power Timer instance
00566   * @retval Returned value can be one of the following values:
00567   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00568   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00569   */
00570 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
00571 {
00572   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
00573 }
00574
00575 /**
00576   * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
00577   * @note This function must be called when the LPTIM instance is disabled.
00578   * @note Regarding the LPTIM output polarity the change takes effect
00579   *       immediately, so the output default value will change immediately after
00580   *       the polarity is re-configured, even before the timer is enabled.
00581   * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
00582   *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
00583   * @param  LPTIMx Low-Power Timer instance
00584   * @param  Waveform This parameter can be one of the following values:
00585   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00586   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00587   * @param  Polarity This parameter can be one of the following values:
00588   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00589   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00590   * @retval None
00591   */
00592 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
00593 {
00594   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
00595 }
00596
00597 /**
00598   * @brief  Set  waveform shape
00599   * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
00600   * @param  LPTIMx Low-Power Timer instance
00601   * @param  Waveform This parameter can be one of the following values:
00602   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00603   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00604   * @retval None
00605   */
00606 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
00607 {
00608   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
00609 }
00610
00611 /**
00612   * @brief  Get actual waveform shape
00613   * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
00614   * @param  LPTIMx Low-Power Timer instance
00615   * @retval Returned value can be one of the following values:
00616   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00617   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00618   */
00619 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
00620 {
00621   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
00622 }
00623
00624 /**
00625   * @brief  Set  output polarity
00626   * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
00627   * @param  LPTIMx Low-Power Timer instance
00628   * @param  Polarity This parameter can be one of the following values:
00629   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00630   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00631   * @retval None
00632   */
00633 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
00634 {
00635   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
00636 }
00637
00638 /**
00639   * @brief  Get actual output polarity
00640   * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
00641   * @param  LPTIMx Low-Power Timer instance
00642   * @retval Returned value can be one of the following values:
00643   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00644   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00645   */
00646 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
00647 {
00648   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
00649 }
00650
00651 /**
00652   * @brief  Set actual prescaler division ratio.
00653   * @note This function must be called when the LPTIM instance is disabled.
00654   * @note When the LPTIM is configured to be clocked by an internal clock source
00655   *       and the LPTIM counter is configured to be updated by active edges
00656   *       detected on the LPTIM external Input1, the internal clock provided to
00657   *       the LPTIM must be not be prescaled.
00658   * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
00659   * @param  LPTIMx Low-Power Timer instance
00660   * @param  Prescaler This parameter can be one of the following values:
00661   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00662   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00663   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00664   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00665   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00666   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00667   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00668   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00669   * @retval None
00670   */
00671 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
00672 {
00673   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
00674 }
00675
00676 /**
00677   * @brief  Get actual prescaler division ratio.
00678   * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
00679   * @param  LPTIMx Low-Power Timer instance
00680   * @retval Returned value can be one of the following values:
00681   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00682   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00683   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00684   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00685   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00686   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00687   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00688   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00689   */
00690 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
00691 {
00692   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
00693 }
00694
00695 /**
00696   * @brief  Set LPTIM input 1 source (default GPIO).
00697   * @rmtoll CFGR2      IN1SEL       LL_LPTIM_SetInput1Src
00698   * @param  LPTIMx Low-Power Timer instance
00699   * @param  Src This parameter can be one of the following values:
00700   *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
00701   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
00702   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
00703   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
00704   *         @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A
00705   *         @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B
00706   * @retval None
00707   */
00708 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00709 {
00710   MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
00711 }
00712
00713 /**
00714   * @brief  Set LPTIM input 2 source (default GPIO).
00715   * @rmtoll CFGR2      IN2SEL       LL_LPTIM_SetInput2Src
00716   * @param  LPTIMx Low-Power Timer instance
00717   * @param  Src This parameter can be one of the following values:
00718   *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
00719   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
00720   * @retval None
00721   */
00722 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00723 {
00724   MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
00725 }
00726
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
00732   * @{
00733   */
00734
00735 /**
00736   * @brief  Enable the timeout function
00737   * @note This function must be called when the LPTIM instance is disabled.
00738   * @note The first trigger event will start the timer, any successive trigger
00739   *       event will reset the counter and the timer will restart.
00740   * @note The timeout value corresponds to the compare value; if no trigger
00741   *       occurs within the expected time frame, the MCU is waked-up by the
00742   *       compare match event.
00743   * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
00744   * @param  LPTIMx Low-Power Timer instance
00745   * @retval None
00746   */
00747 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
00748 {
00749   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00750 }
00751
00752 /**
00753   * @brief  Disable the timeout function
00754   * @note This function must be called when the LPTIM instance is disabled.
00755   * @note A trigger event arriving when the timer is already started will be
00756   *       ignored.
00757   * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
00758   * @param  LPTIMx Low-Power Timer instance
00759   * @retval None
00760   */
00761 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
00762 {
00763   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00764 }
00765
00766 /**
00767   * @brief  Indicate whether the timeout function is enabled.
00768   * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
00769   * @param  LPTIMx Low-Power Timer instance
00770   * @retval State of bit (1 or 0).
00771   */
00772 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
00773 {
00774   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
00775 }
00776
00777 /**
00778   * @brief  Start the LPTIM counter
00779   * @note This function must be called when the LPTIM instance is disabled.
00780   * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
00781   * @param  LPTIMx Low-Power Timer instance
00782   * @retval None
00783   */
00784 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
00785 {
00786   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
00787 }
00788
00789 /**
00790   * @brief  Configure the external trigger used as a trigger event for the LPTIM.
00791   * @note This function must be called when the LPTIM instance is disabled.
00792   * @note An internal clock source must be present when a digital filter is
00793   *       required for the trigger.
00794   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
00795   *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
00796   *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
00797   * @param  LPTIMx Low-Power Timer instance
00798   * @param  Source This parameter can be one of the following values:
00799   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00800   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00801   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00802   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00803   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00804   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00805   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00806   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00807   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2     (*)
00808   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3     (*)
00809   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4     (*)
00810   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5     (*)
00811   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A  (*)
00812   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B  (*)
00813   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A  (*)
00814   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B  (*)
00815   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A  (*)
00816   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B  (*)
00817   *
00818   *         (*)  Value not defined in all devices. \n
00819   *
00820   * @param  Filter This parameter can be one of the following values:
00821   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00822   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00823   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00824   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00825   * @param  Polarity This parameter can be one of the following values:
00826   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00827   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00828   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00829   * @retval None
00830   */
00831 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
00832 {
00833   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
00834 }
00835
00836 /**
00837   * @brief  Get actual external trigger source.
00838   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
00839   * @param  LPTIMx Low-Power Timer instance
00840   * @retval Returned value can be one of the following values:
00841   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00842   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00843   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00844   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00845   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00846   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00847   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00848   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00849   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2     (*)
00850   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3     (*)
00851   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4     (*)
00852   *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5     (*)
00853   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A  (*)
00854   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B  (*)
00855   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A  (*)
00856   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B  (*)
00857   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A  (*)
00858   *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B  (*)
00859   *
00860   *         (*)  Value not defined in all devices. \n
00861   *
00862   */
00863 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
00864 {
00865   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
00866 }
00867
00868 /**
00869   * @brief  Get actual external trigger filter.
00870   * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
00871   * @param  LPTIMx Low-Power Timer instance
00872   * @retval Returned value can be one of the following values:
00873   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00874   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00875   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00876   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00877   */
00878 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
00879 {
00880   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
00881 }
00882
00883 /**
00884   * @brief  Get actual external trigger polarity.
00885   * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
00886   * @param  LPTIMx Low-Power Timer instance
00887   * @retval Returned value can be one of the following values:
00888   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00889   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00890   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00891   */
00892 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
00893 {
00894   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
00895 }
00896
00897 /**
00898   * @}
00899   */
00900
00901 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
00902   * @{
00903   */
00904
00905 /**
00906   * @brief  Set the source of the clock used by the LPTIM instance.
00907   * @note This function must be called when the LPTIM instance is disabled.
00908   * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
00909   * @param  LPTIMx Low-Power Timer instance
00910   * @param  ClockSource This parameter can be one of the following values:
00911   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00912   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00913   * @retval None
00914   */
00915 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
00916 {
00917   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
00918 }
00919
00920 /**
00921   * @brief  Get actual LPTIM instance clock source.
00922   * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
00923   * @param  LPTIMx Low-Power Timer instance
00924   * @retval Returned value can be one of the following values:
00925   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00926   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00927   */
00928 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
00929 {
00930   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
00931 }
00932
00933 /**
00934   * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
00935   * @note This function must be called when the LPTIM instance is disabled.
00936   * @note When both external clock signal edges are considered active ones,
00937   *       the LPTIM must also be clocked by an internal clock source with a
00938   *       frequency equal to at least four times the external clock frequency.
00939   * @note An internal clock source must be present when a digital filter is
00940   *       required for external clock.
00941   * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
00942   *         CFGR         CKPOL         LL_LPTIM_ConfigClock
00943   * @param  LPTIMx Low-Power Timer instance
00944   * @param  ClockFilter This parameter can be one of the following values:
00945   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00946   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00947   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00948   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00949   * @param  ClockPolarity This parameter can be one of the following values:
00950   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00951   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00952   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00953   * @retval None
00954   */
00955 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
00956 {
00957   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
00958 }
00959
00960 /**
00961   * @brief  Get actual clock polarity
00962   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
00963   * @param  LPTIMx Low-Power Timer instance
00964   * @retval Returned value can be one of the following values:
00965   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00966   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00967   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00968   */
00969 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
00970 {
00971   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00972 }
00973
00974 /**
00975   * @brief  Get actual clock digital filter
00976   * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
00977   * @param  LPTIMx Low-Power Timer instance
00978   * @retval Returned value can be one of the following values:
00979   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00980   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00981   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00982   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00983   */
00984 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
00985 {
00986   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
00987 }
00988
00989 /**
00990   * @}
00991   */
00992
00993 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
00994   * @{
00995   */
00996
00997 /**
00998   * @brief  Configure the encoder mode.
00999   * @note This function must be called when the LPTIM instance is disabled.
01000   * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
01001   * @param  LPTIMx Low-Power Timer instance
01002   * @param  EncoderMode This parameter can be one of the following values:
01003   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
01004   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
01005   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
01006   * @retval None
01007   */
01008 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
01009 {
01010   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
01011 }
01012
01013 /**
01014   * @brief  Get actual encoder mode.
01015   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
01016   * @param  LPTIMx Low-Power Timer instance
01017   * @retval Returned value can be one of the following values:
01018   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
01019   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
01020   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
01021   */
01022 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
01023 {
01024   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
01025 }
01026
01027 /**
01028   * @brief  Enable the encoder mode
01029   * @note This function must be called when the LPTIM instance is disabled.
01030   * @note In this mode the LPTIM instance must be clocked by an internal clock
01031   *       source. Also, the prescaler division ratio must be equal to 1.
01032   * @note LPTIM instance must be configured in continuous mode prior enabling
01033   *       the encoder mode.
01034   * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
01035   * @param  LPTIMx Low-Power Timer instance
01036   * @retval None
01037   */
01038 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
01039 {
01040   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01041 }
01042
01043 /**
01044   * @brief  Disable the encoder mode
01045   * @note This function must be called when the LPTIM instance is disabled.
01046   * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
01047   * @param  LPTIMx Low-Power Timer instance
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
01051 {
01052   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01053 }
01054
01055 /**
01056   * @brief  Indicates whether the LPTIM operates in encoder mode.
01057   * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
01058   * @param  LPTIMx Low-Power Timer instance
01059   * @retval State of bit (1 or 0).
01060   */
01061 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
01062 {
01063   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
01064 }
01065
01066 /**
01067   * @}
01068   */
01069
01070 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
01071   * @{
01072   */
01073
01074 /**
01075   * @brief  Clear the compare match flag (CMPMCF)
01076   * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
01077   * @param  LPTIMx Low-Power Timer instance
01078   * @retval None
01079   */
01080 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
01081 {
01082   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
01083 }
01084
01085 /**
01086   * @brief  Inform application whether a compare match interrupt has occurred.
01087   * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
01088   * @param  LPTIMx Low-Power Timer instance
01089   * @retval State of bit (1 or 0).
01090   */
01091 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
01092 {
01093   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
01094 }
01095
01096 /**
01097   * @brief  Clear the autoreload match flag (ARRMCF)
01098   * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
01099   * @param  LPTIMx Low-Power Timer instance
01100   * @retval None
01101   */
01102 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
01103 {
01104   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
01105 }
01106
01107 /**
01108   * @brief  Inform application whether a autoreload match interrupt has occurred.
01109   * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
01110   * @param  LPTIMx Low-Power Timer instance
01111   * @retval State of bit (1 or 0).
01112   */
01113 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
01114 {
01115   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
01116 }
01117
01118 /**
01119   * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
01120   * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
01121   * @param  LPTIMx Low-Power Timer instance
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01125 {
01126   SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
01127 }
01128
01129 /**
01130   * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
01131   * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
01132   * @param  LPTIMx Low-Power Timer instance
01133   * @retval State of bit (1 or 0).
01134   */
01135 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01136 {
01137   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
01138 }
01139
01140 /**
01141   * @brief  Clear the compare register update interrupt flag (CMPOKCF).
01142   * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
01143   * @param  LPTIMx Low-Power Timer instance
01144   * @retval None
01145   */
01146 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01147 {
01148   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
01149 }
01150
01151 /**
01152   * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
01153   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
01154   * @param  LPTIMx Low-Power Timer instance
01155   * @retval State of bit (1 or 0).
01156   */
01157 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01158 {
01159   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
01160 }
01161
01162 /**
01163   * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
01164   * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
01165   * @param  LPTIMx Low-Power Timer instance
01166   * @retval None
01167   */
01168 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01169 {
01170   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
01171 }
01172
01173 /**
01174   * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
01175   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
01176   * @param  LPTIMx Low-Power Timer instance
01177   * @retval State of bit (1 or 0).
01178   */
01179 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01180 {
01181   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
01182 }
01183
01184 /**
01185   * @brief  Clear the counter direction change to up interrupt flag (UPCF).
01186   * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
01187   * @param  LPTIMx Low-Power Timer instance
01188   * @retval None
01189   */
01190 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
01191 {
01192   SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
01193 }
01194
01195 /**
01196   * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
01197   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
01198   * @param  LPTIMx Low-Power Timer instance
01199   * @retval State of bit (1 or 0).
01200   */
01201 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
01202 {
01203   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
01204 }
01205
01206 /**
01207   * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
01208   * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
01209   * @param  LPTIMx Low-Power Timer instance
01210   * @retval None
01211   */
01212 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01213 {
01214   SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
01215 }
01216
01217 /**
01218   * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
01219   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
01220   * @param  LPTIMx Low-Power Timer instance
01221   * @retval State of bit (1 or 0).
01222   */
01223 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01224 {
01225   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
01226 }
01227
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
01233   * @{
01234   */
01235
01236 /**
01237   * @brief  Enable compare match interrupt (CMPMIE).
01238   * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
01239   * @param  LPTIMx Low-Power Timer instance
01240   * @retval None
01241   */
01242 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01243 {
01244   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01245 }
01246
01247 /**
01248   * @brief  Disable compare match interrupt (CMPMIE).
01249   * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
01250   * @param  LPTIMx Low-Power Timer instance
01251   * @retval None
01252   */
01253 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01254 {
01255   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01256 }
01257
01258 /**
01259   * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
01260   * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
01261   * @param  LPTIMx Low-Power Timer instance
01262   * @retval State of bit (1 or 0).
01263   */
01264 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
01265 {
01266   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
01267 }
01268
01269 /**
01270   * @brief  Enable autoreload match interrupt (ARRMIE).
01271   * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
01272   * @param  LPTIMx Low-Power Timer instance
01273   * @retval None
01274   */
01275 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01276 {
01277   SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01278 }
01279
01280 /**
01281   * @brief  Disable autoreload match interrupt (ARRMIE).
01282   * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
01283   * @param  LPTIMx Low-Power Timer instance
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01287 {
01288   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01289 }
01290
01291 /**
01292   * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
01293   * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
01294   * @param  LPTIMx Low-Power Timer instance
01295   * @retval State of bit (1 or 0).
01296   */
01297 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
01298 {
01299   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
01300 }
01301
01302 /**
01303   * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
01304   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
01305   * @param  LPTIMx Low-Power Timer instance
01306   * @retval None
01307   */
01308 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01309 {
01310   SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01311 }
01312
01313 /**
01314   * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
01315   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
01316   * @param  LPTIMx Low-Power Timer instance
01317   * @retval None
01318   */
01319 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01320 {
01321   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01322 }
01323
01324 /**
01325   * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
01326   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
01327   * @param  LPTIMx Low-Power Timer instance
01328   * @retval State of bit (1 or 0).
01329   */
01330 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01331 {
01332   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
01333 }
01334
01335 /**
01336   * @brief  Enable compare register write completed interrupt (CMPOKIE).
01337   * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
01338   * @param  LPTIMx Low-Power Timer instance
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01342 {
01343   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01344 }
01345
01346 /**
01347   * @brief  Disable compare register write completed interrupt (CMPOKIE).
01348   * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
01349   * @param  LPTIMx Low-Power Timer instance
01350   * @retval None
01351   */
01352 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01353 {
01354   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01355 }
01356
01357 /**
01358   * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
01359   * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
01360   * @param  LPTIMx Low-Power Timer instance
01361   * @retval State of bit (1 or 0).
01362   */
01363 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01364 {
01365   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
01366 }
01367
01368 /**
01369   * @brief  Enable autoreload register write completed interrupt (ARROKIE).
01370   * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK
01371   * @param  LPTIMx Low-Power Timer instance
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01375 {
01376   SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01377 }
01378
01379 /**
01380   * @brief  Disable autoreload register write completed interrupt (ARROKIE).
01381   * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK
01382   * @param  LPTIMx Low-Power Timer instance
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01386 {
01387   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01388 }
01389
01390 /**
01391   * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
01392   * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
01393   * @param  LPTIMx Low-Power Timer instance
01394   * @retval State of bit (1 or 0).
01395   */
01396 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
01397 {
01398   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
01399 }
01400
01401 /**
01402   * @brief  Enable direction change to up interrupt (UPIE).
01403   * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP
01404   * @param  LPTIMx Low-Power Timer instance
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
01408 {
01409   SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01410 }
01411
01412 /**
01413   * @brief  Disable direction change to up interrupt (UPIE).
01414   * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP
01415   * @param  LPTIMx Low-Power Timer instance
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
01419 {
01420   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01421 }
01422
01423 /**
01424   * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
01425   * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP
01426   * @param  LPTIMx Low-Power Timer instance
01427   * @retval State of bit (1 or 0).
01428   */
01429 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
01430 {
01431   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
01432 }
01433
01434 /**
01435   * @brief  Enable direction change to down interrupt (DOWNIE).
01436   * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN
01437   * @param  LPTIMx Low-Power Timer instance
01438   * @retval None
01439   */
01440 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01441 {
01442   SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01443 }
01444
01445 /**
01446   * @brief  Disable direction change to down interrupt (DOWNIE).
01447   * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN
01448   * @param  LPTIMx Low-Power Timer instance
01449   * @retval None
01450   */
01451 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01452 {
01453   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01454 }
01455
01456 /**
01457   * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
01458   * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
01459   * @param  LPTIMx Low-Power Timer instance
01460   * @retval State of bit (1 or 0).
01461   */
01462 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
01463 {
01464   return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
01465 }
01466
01467 /**
01468   * @}
01469   */
01470
01471 /**
01472   * @}
01473   */
01474
01475 /**
01476   * @}
01477   */
01478
01479 #endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */
01480
01481 /**
01482   * @}
01483   */
01484
01485 #ifdef __cplusplus
01486 }
01487 #endif
01488
01489 #endif /* STM32H7xx_LL_LPTIM_H */
01490
01491 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lpuart.c Source File

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stm32h7xx_ll_lpuart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_lpuart.c
00004   * @author  MCD Application Team
00005   * @brief   LPUART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_lpuart.h"
00023 #include "stm32h7xx_ll_rcc.h"
00024 #include "stm32h7xx_ll_bus.h"
00025 #ifdef USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPUART1)
00036
00037 /** @addtogroup LPUART_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup LPUART_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052
00053 /* Private macros ------------------------------------------------------------*/
00054 /** @addtogroup LPUART_LL_Private_Macros
00055   * @{
00056   */
00057
00058 /* Check of parameters for configuration of LPUART registers                  */
00059
00060 #define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
00061                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
00062                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
00063                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
00064                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
00065                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
00066                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
00067                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
00068                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
00069                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
00070                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
00071                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
00072
00073 /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
00074 /*              value :                                                       */
00075 /*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
00076 /*                - LPUART_BRR register value should be >= 0x300              */
00077 /*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
00078 /*              Baudrate specified by the user should belong to [8, 33000000].*/
00079 #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))
00080
00081 /* __VALUE__ BRR content must be greater than or equal to 0x300. */
00082 #define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
00083
00084 /* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
00085 #define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
00086
00087 #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
00088                                            || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
00089                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
00090                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
00091
00092 #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
00093                                         || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
00094                                         || ((__VALUE__) == LL_LPUART_PARITY_ODD))
00095
00096 #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
00097                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
00098                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
00099
00100 #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
00101                                           || ((__VALUE__) == LL_LPUART_STOPBITS_2))
00102
00103 #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
00104                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
00105                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
00106                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Private function prototypes -----------------------------------------------*/
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup LPUART_LL_Exported_Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup LPUART_LL_EF_Init
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  De-initialize LPUART registers (Registers restored to their default values).
00125   * @param  LPUARTx LPUART Instance
00126   * @retval An ErrorStatus enumeration value:
00127   *          - SUCCESS: LPUART registers are de-initialized
00128   *          - ERROR: not applicable
00129   */
00130 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
00131 {
00132   ErrorStatus status = SUCCESS;
00133
00134   /* Check the parameters */
00135   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00136
00137   if (LPUARTx == LPUART1)
00138   {
00139     /* Force reset of LPUART peripheral */
00140     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1);
00141
00142     /* Release reset of LPUART peripheral */
00143     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1);
00144   }
00145   else
00146   {
00147     status = ERROR;
00148   }
00149
00150   return (status);
00151 }
00152
00153 /**
00154   * @brief  Initialize LPUART registers according to the specified
00155   *         parameters in LPUART_InitStruct.
00156   * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
00157   *         LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00158   * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
00159   * @param  LPUARTx LPUART Instance
00160   * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00161   *         that contains the configuration information for the specified LPUART peripheral.
00162   * @retval An ErrorStatus enumeration value:
00163   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
00164   *          - ERROR: Problem occurred during LPUART Registers initialization
00165   */
00166 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
00167 {
00168   ErrorStatus status = ERROR;
00169   uint32_t periphclk;
00170
00171   /* Check the parameters */
00172   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00173   assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
00174   assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
00175   assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
00176   assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
00177   assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
00178   assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
00179   assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
00180
00181   /* LPUART needs to be in disabled state, in order to be able to configure some bits in
00182      CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
00183   if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
00184   {
00185     /*---------------------------- LPUART CR1 Configuration -----------------------
00186      * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
00187      * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
00188      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
00189      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
00190      */
00191     MODIFY_REG(LPUARTx->CR1,
00192                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
00193                (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
00194
00195     /*---------------------------- LPUART CR2 Configuration -----------------------
00196      * Configure LPUARTx CR2 (Stop bits) with parameters:
00197      * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
00198      */
00199     LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
00200
00201     /*---------------------------- LPUART CR3 Configuration -----------------------
00202      * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
00203      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
00204      */
00205     LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
00206
00207     /*---------------------------- LPUART BRR Configuration -----------------------
00208      * Retrieve Clock frequency used for LPUART Peripheral
00209      */
00210     periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00211
00212     /* Configure the LPUART Baud Rate :
00213        - prescaler value is required
00214        - valid baud rate value (different from 0) is required
00215        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00216     */
00217     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00218         && (LPUART_InitStruct->BaudRate != 0U))
00219     {
00220       status = SUCCESS;
00221       LL_LPUART_SetBaudRate(LPUARTx,
00222                             periphclk,
00223                             LPUART_InitStruct->PrescalerValue,
00224                             LPUART_InitStruct->BaudRate);
00225
00226       /* Check BRR is greater than or equal to 0x300 */
00227       assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
00228
00229       /* Check BRR is lower than or equal to 0xFFFFF */
00230       assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
00231     }
00232
00233     /*---------------------------- LPUART PRESC Configuration -----------------------
00234      * Configure LPUARTx PRESC (Prescaler) with parameters:
00235      * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
00236      */
00237     LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
00238   }
00239
00240   return (status);
00241 }
00242
00243 /**
00244   * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
00245   * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00246   *                          whose fields will be set to default values.
00247   * @retval None
00248   */
00249
00250 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
00251 {
00252   /* Set LPUART_InitStruct fields to default values */
00253   LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
00254   LPUART_InitStruct->BaudRate            = 9600U;
00255   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
00256   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
00257   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
00258   LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
00259   LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 #endif /* defined (LPUART1) */
00275
00276 /**
00277   * @}
00278   */
00279
00280 #endif /* USE_FULL_LL_DRIVER */
00281
00282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00283
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_lpuart.h Source File

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stm32h7xx_ll_lpuart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPUART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_LPUART_H
00022 #define STM32H7xx_LL_LPUART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPUART1)
00036
00037 /** @defgroup LPUART_LL LPUART
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
00044   * @{
00045   */
00046 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
00047 static const uint16_t LPUART_PRESCALER_TAB[] =
00048 {
00049   (uint16_t)1,
00050   (uint16_t)2,
00051   (uint16_t)4,
00052   (uint16_t)6,
00053   (uint16_t)8,
00054   (uint16_t)10,
00055   (uint16_t)12,
00056   (uint16_t)16,
00057   (uint16_t)32,
00058   (uint16_t)64,
00059   (uint16_t)128,
00060   (uint16_t)256
00061 };
00062 /**
00063   * @}
00064   */
00065
00066 /* Private constants ---------------------------------------------------------*/
00067 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00068   * @{
00069   */
00070 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00071 #define LPUART_LPUARTDIV_FREQ_MUL     256U
00072 #define LPUART_BRR_MASK               0x000FFFFFU
00073 #define LPUART_BRR_MIN_VALUE          0x00000300U
00074 /**
00075   * @}
00076   */
00077
00078
00079 /* Private macros ------------------------------------------------------------*/
00080 #if defined(USE_FULL_LL_DRIVER)
00081 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087 #endif /*USE_FULL_LL_DRIVER*/
00088
00089 /* Exported types ------------------------------------------------------------*/
00090 #if defined(USE_FULL_LL_DRIVER)
00091 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00092   * @{
00093   */
00094
00095 /**
00096   * @brief LL LPUART Init Structure definition
00097   */
00098 typedef struct
00099 {
00100   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00101                                            This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
00102
00103                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
00104
00105   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00106
00107                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
00108
00109   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00110                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00111
00112                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
00113
00114   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00115                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00116
00117                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
00118
00119   uint32_t Parity;                    /*!< Specifies the parity mode.
00120                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00121
00122                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
00123
00124   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00125                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00126
00127                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
00128
00129   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00130                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00131
00132                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
00133
00134 } LL_LPUART_InitTypeDef;
00135
00136 /**
00137   * @}
00138   */
00139 #endif /* USE_FULL_LL_DRIVER */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00143   * @{
00144   */
00145
00146 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00147   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00148   * @{
00149   */
00150 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
00151 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
00152 #define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected flag */
00153 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
00154 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
00155 #define LL_LPUART_ICR_TXFECF               USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
00156 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
00157 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
00158 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
00159 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00165   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00166   * @{
00167   */
00168 #define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
00169 #define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
00170 #define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
00171 #define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
00172 #define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
00173 #define LL_LPUART_ISR_RXNE_RXFNE           USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00174 #define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
00175 #define LL_LPUART_ISR_TXE_TXFNF            USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00176 #define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
00177 #define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
00178 #define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
00179 #define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
00180 #define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
00181 #define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00182 #define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00183 #define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00184 #define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00185 #define LL_LPUART_ISR_TXFE                 USART_ISR_TXFE                /*!< TX FIFO empty flag */
00186 #define LL_LPUART_ISR_RXFF                 USART_ISR_RXFF                /*!< RX FIFO full flag */
00187 #define LL_LPUART_ISR_RXFT                 USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00188 #define LL_LPUART_ISR_TXFT                 USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup LPUART_LL_EC_IT IT Defines
00194   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00195   * @{
00196   */
00197 #define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00198 #define LL_LPUART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00199 #define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00200 #define LL_LPUART_CR1_TXEIE_TXFNFIE        USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00201 #define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
00202 #define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
00203 #define LL_LPUART_CR1_TXFEIE               USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00204 #define LL_LPUART_CR1_RXFFIE               USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00205 #define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
00206 #define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
00207 #define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00208 #define LL_LPUART_CR3_TXFTIE               USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00209 #define LL_LPUART_CR3_RXFTIE               USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00215   * @{
00216   */
00217 #define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
00218 #define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
00219 #define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
00220 #define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
00221 #define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
00222 #define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00228   * @{
00229   */
00230 #define LL_LPUART_DIRECTION_NONE           0x00000000U                        /*!< Transmitter and Receiver are disabled */
00231 #define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00232 #define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00233 #define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00239   * @{
00240   */
00241 #define LL_LPUART_PARITY_NONE              0x00000000U                        /*!< Parity control disabled */
00242 #define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
00243 #define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00249   * @{
00250   */
00251 #define LL_LPUART_WAKEUP_IDLELINE          0x00000000U                        /*!<  LPUART wake up from Mute mode on Idle Line */
00252 #define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00258   * @{
00259   */
00260 #define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00261 #define LL_LPUART_DATAWIDTH_8B             0x00000000U                        /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00262 #define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
00268   * @{
00269   */
00270 #define LL_LPUART_PRESCALER_DIV1           0x00000000U                                                                   /*!< Input clock not devided   */
00271 #define LL_LPUART_PRESCALER_DIV2           (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
00272 #define LL_LPUART_PRESCALER_DIV4           (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
00273 #define LL_LPUART_PRESCALER_DIV6           (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
00274 #define LL_LPUART_PRESCALER_DIV8           (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
00275 #define LL_LPUART_PRESCALER_DIV10          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
00276 #define LL_LPUART_PRESCALER_DIV12          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
00277 #define LL_LPUART_PRESCALER_DIV16          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
00278 #define LL_LPUART_PRESCALER_DIV32          (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
00279 #define LL_LPUART_PRESCALER_DIV64          (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
00280 #define LL_LPUART_PRESCALER_DIV128         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
00281 #define LL_LPUART_PRESCALER_DIV256         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00287   * @{
00288   */
00289 #define LL_LPUART_STOPBITS_1               0x00000000U                        /*!< 1 stop bit */
00290 #define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00296   * @{
00297   */
00298 #define LL_LPUART_TXRX_STANDARD            0x00000000U                        /*!< TX/RX pins are used as defined in standard pinout */
00299 #define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00305   * @{
00306   */
00307 #define LL_LPUART_RXPIN_LEVEL_STANDARD     0x00000000U                        /*!< RX pin signal works using the standard logic levels */
00308 #define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00314   * @{
00315   */
00316 #define LL_LPUART_TXPIN_LEVEL_STANDARD     0x00000000U                        /*!< TX pin signal works using the standard logic levels */
00317 #define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00323   * @{
00324   */
00325 #define LL_LPUART_BINARY_LOGIC_POSITIVE    0x00000000U                        /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00326 #define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00332   * @{
00333   */
00334 #define LL_LPUART_BITORDER_LSBFIRST        0x00000000U                        /*!< data is transmitted/received with data bit 0 first, following the start bit */
00335 #define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00341   * @{
00342   */
00343 #define LL_LPUART_ADDRESS_DETECT_4B        0x00000000U                        /*!< 4-bit address detection method selected */
00344 #define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00350   * @{
00351   */
00352 #define LL_LPUART_HWCONTROL_NONE           0x00000000U                        /*!< CTS and RTS hardware flow control disabled */
00353 #define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00354 #define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00355 #define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00361   * @{
00362   */
00363 #define LL_LPUART_WAKEUP_ON_ADDRESS        0x00000000U                             /*!< Wake up active on address match */
00364 #define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00365 #define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00371   * @{
00372   */
00373 #define LL_LPUART_DE_POLARITY_HIGH         0x00000000U                        /*!< DE signal is active high */
00374 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00380   * @{
00381   */
00382 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U                       /*!< Get address of data register used for transmission */
00383 #define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U                       /*!< Get address of data register used for reception */
00384 /**
00385   * @}
00386   */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /* Exported macro ------------------------------------------------------------*/
00393 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00394   * @{
00395   */
00396
00397 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Write a value in LPUART register
00403   * @param  __INSTANCE__ LPUART Instance
00404   * @param  __REG__ Register to be written
00405   * @param  __VALUE__ Value to be written in the register
00406   * @retval None
00407   */
00408 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00409
00410 /**
00411   * @brief  Read a value in LPUART register
00412   * @param  __INSTANCE__ LPUART Instance
00413   * @param  __REG__ Register to be read
00414   * @retval Register value
00415   */
00416 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00422   * @{
00423   */
00424
00425 /**
00426   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00427   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00428   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00429   * @param  __PRESCALER__ This parameter can be one of the following values:
00430   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00431   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00432   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00433   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00434   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00435   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00436   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00437   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00438   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00439   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00440   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00441   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00442   * @param  __BAUDRATE__ Baud Rate value to achieve
00443   * @retval LPUARTDIV value to be used for BRR register filling
00444   */
00445 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
00446                                                                                 + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /* Exported functions --------------------------------------------------------*/
00457 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00458   * @{
00459   */
00460
00461 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00462   * @{
00463   */
00464
00465 /**
00466   * @brief  LPUART Enable
00467   * @rmtoll CR1          UE            LL_LPUART_Enable
00468   * @param  LPUARTx LPUART Instance
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00472 {
00473   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00474 }
00475
00476 /**
00477   * @brief  LPUART Disable
00478   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00479   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00480   *         flags, in the LPUARTx_ISR are set to their default values.
00481   * @note   In order to go into low-power mode without generating errors on the line,
00482   *         the TE bit must be reset before and the software must wait
00483   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00484   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00485   *         be disabled before resetting the UE bit.
00486   * @rmtoll CR1          UE            LL_LPUART_Disable
00487   * @param  LPUARTx LPUART Instance
00488   * @retval None
00489   */
00490 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00491 {
00492   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00493 }
00494
00495 /**
00496   * @brief  Indicate if LPUART is enabled
00497   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00498   * @param  LPUARTx LPUART Instance
00499   * @retval State of bit (1 or 0).
00500   */
00501 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
00502 {
00503   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00504 }
00505
00506 /**
00507   * @brief  FIFO Mode Enable
00508   * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
00509   * @param  LPUARTx LPUART Instance
00510   * @retval None
00511   */
00512 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
00513 {
00514   SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00515 }
00516
00517 /**
00518   * @brief  FIFO Mode Disable
00519   * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
00520   * @param  LPUARTx LPUART Instance
00521   * @retval None
00522   */
00523 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
00524 {
00525   CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00526 }
00527
00528 /**
00529   * @brief  Indicate if FIFO Mode is enabled
00530   * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
00531   * @param  LPUARTx LPUART Instance
00532   * @retval State of bit (1 or 0).
00533   */
00534 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
00535 {
00536   return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00537 }
00538
00539 /**
00540   * @brief  Configure TX FIFO Threshold
00541   * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
00542   * @param  LPUARTx LPUART Instance
00543   * @param  Threshold This parameter can be one of the following values:
00544   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00545   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00546   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00547   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00548   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00549   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00550   * @retval None
00551   */
00552 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00553 {
00554   MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00555 }
00556
00557 /**
00558   * @brief  Return TX FIFO Threshold Configuration
00559   * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
00560   * @param  LPUARTx LPUART Instance
00561   * @retval Returned value can be one of the following values:
00562   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00563   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00564   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00565   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00566   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00567   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00568   */
00569 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
00570 {
00571   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00572 }
00573
00574 /**
00575   * @brief  Configure RX FIFO Threshold
00576   * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
00577   * @param  LPUARTx LPUART Instance
00578   * @param  Threshold This parameter can be one of the following values:
00579   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00580   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00581   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00582   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00583   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00584   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00588 {
00589   MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00590 }
00591
00592 /**
00593   * @brief  Return RX FIFO Threshold Configuration
00594   * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
00595   * @param  LPUARTx LPUART Instance
00596   * @retval Returned value can be one of the following values:
00597   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00598   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00599   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00600   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00601   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00602   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00603   */
00604 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
00605 {
00606   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00607 }
00608
00609 /**
00610   * @brief  Configure TX and RX FIFOs Threshold
00611   * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
00612   *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
00613   * @param  LPUARTx LPUART Instance
00614   * @param  TXThreshold This parameter can be one of the following values:
00615   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00616   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00617   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00618   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00619   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00620   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00621   * @param  RXThreshold This parameter can be one of the following values:
00622   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00623   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00624   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00625   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00626   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00627   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00631 {
00632   MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
00633 }
00634
00635 /**
00636   * @brief  LPUART enabled in STOP Mode
00637   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00638   *         LPUART clock selection is HSI or LSE in RCC.
00639   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00640   * @param  LPUARTx LPUART Instance
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00644 {
00645   SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00646 }
00647
00648 /**
00649   * @brief  LPUART disabled in STOP Mode
00650   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00651   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00652   * @param  LPUARTx LPUART Instance
00653   * @retval None
00654   */
00655 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00656 {
00657   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00658 }
00659
00660 /**
00661   * @brief  Indicate if LPUART is enabled in STOP Mode
00662   *         (able to wake up MCU from Stop mode or not)
00663   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00664   * @param  LPUARTx LPUART Instance
00665   * @retval State of bit (1 or 0).
00666   */
00667 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
00668 {
00669   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00670 }
00671
00672 /**
00673   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00674   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00675   * @param  LPUARTx LPUART Instance
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00679 {
00680   SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00681 }
00682
00683 /**
00684   * @brief  Receiver Disable
00685   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00686   * @param  LPUARTx LPUART Instance
00687   * @retval None
00688   */
00689 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00690 {
00691   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00692 }
00693
00694 /**
00695   * @brief  Transmitter Enable
00696   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00697   * @param  LPUARTx LPUART Instance
00698   * @retval None
00699   */
00700 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00701 {
00702   SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00703 }
00704
00705 /**
00706   * @brief  Transmitter Disable
00707   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00708   * @param  LPUARTx LPUART Instance
00709   * @retval None
00710   */
00711 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00712 {
00713   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00714 }
00715
00716 /**
00717   * @brief  Configure simultaneously enabled/disabled states
00718   *         of Transmitter and Receiver
00719   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00720   *         CR1          TE            LL_LPUART_SetTransferDirection
00721   * @param  LPUARTx LPUART Instance
00722   * @param  TransferDirection This parameter can be one of the following values:
00723   *         @arg @ref LL_LPUART_DIRECTION_NONE
00724   *         @arg @ref LL_LPUART_DIRECTION_RX
00725   *         @arg @ref LL_LPUART_DIRECTION_TX
00726   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00727   * @retval None
00728   */
00729 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00730 {
00731   MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00732 }
00733
00734 /**
00735   * @brief  Return enabled/disabled states of Transmitter and Receiver
00736   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00737   *         CR1          TE            LL_LPUART_GetTransferDirection
00738   * @param  LPUARTx LPUART Instance
00739   * @retval Returned value can be one of the following values:
00740   *         @arg @ref LL_LPUART_DIRECTION_NONE
00741   *         @arg @ref LL_LPUART_DIRECTION_RX
00742   *         @arg @ref LL_LPUART_DIRECTION_TX
00743   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00744   */
00745 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
00746 {
00747   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00748 }
00749
00750 /**
00751   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00752   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00753   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00754   *         (depending on data width) and parity is checked on the received data.
00755   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00756   *         CR1          PCE           LL_LPUART_SetParity
00757   * @param  LPUARTx LPUART Instance
00758   * @param  Parity This parameter can be one of the following values:
00759   *         @arg @ref LL_LPUART_PARITY_NONE
00760   *         @arg @ref LL_LPUART_PARITY_EVEN
00761   *         @arg @ref LL_LPUART_PARITY_ODD
00762   * @retval None
00763   */
00764 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00765 {
00766   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00767 }
00768
00769 /**
00770   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00771   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00772   *         CR1          PCE           LL_LPUART_GetParity
00773   * @param  LPUARTx LPUART Instance
00774   * @retval Returned value can be one of the following values:
00775   *         @arg @ref LL_LPUART_PARITY_NONE
00776   *         @arg @ref LL_LPUART_PARITY_EVEN
00777   *         @arg @ref LL_LPUART_PARITY_ODD
00778   */
00779 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
00780 {
00781   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00782 }
00783
00784 /**
00785   * @brief  Set Receiver Wake Up method from Mute mode.
00786   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00787   * @param  LPUARTx LPUART Instance
00788   * @param  Method This parameter can be one of the following values:
00789   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00790   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00794 {
00795   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00796 }
00797
00798 /**
00799   * @brief  Return Receiver Wake Up method from Mute mode
00800   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00801   * @param  LPUARTx LPUART Instance
00802   * @retval Returned value can be one of the following values:
00803   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00804   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00805   */
00806 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
00807 {
00808   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00809 }
00810
00811 /**
00812   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00813   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00814   * @param  LPUARTx LPUART Instance
00815   * @param  DataWidth This parameter can be one of the following values:
00816   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00817   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00818   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00819   * @retval None
00820   */
00821 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00822 {
00823   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00824 }
00825
00826 /**
00827   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00828   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00829   * @param  LPUARTx LPUART Instance
00830   * @retval Returned value can be one of the following values:
00831   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00832   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00833   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00834   */
00835 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
00836 {
00837   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00838 }
00839
00840 /**
00841   * @brief  Allow switch between Mute Mode and Active mode
00842   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00843   * @param  LPUARTx LPUART Instance
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00847 {
00848   SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00849 }
00850
00851 /**
00852   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00853   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00854   * @param  LPUARTx LPUART Instance
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00858 {
00859   CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00860 }
00861
00862 /**
00863   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00864   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00865   * @param  LPUARTx LPUART Instance
00866   * @retval State of bit (1 or 0).
00867   */
00868 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
00869 {
00870   return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
00871 }
00872
00873 /**
00874   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
00875   * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
00876   * @param  LPUARTx LPUART Instance
00877   * @param  PrescalerValue This parameter can be one of the following values:
00878   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00879   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00880   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00881   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00882   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00883   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00884   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00885   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00886   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00887   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00888   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00889   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00890   * @retval None
00891   */
00892 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
00893 {
00894   MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
00895 }
00896
00897 /**
00898   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
00899   * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
00900   * @param  LPUARTx LPUART Instance
00901   * @retval Returned value can be one of the following values:
00902   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00903   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00904   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00905   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00906   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00907   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00908   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00909   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00910   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00911   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00912   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00913   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00914   */
00915 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
00916 {
00917   return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
00918 }
00919
00920 /**
00921   * @brief  Set the length of the stop bits
00922   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00923   * @param  LPUARTx LPUART Instance
00924   * @param  StopBits This parameter can be one of the following values:
00925   *         @arg @ref LL_LPUART_STOPBITS_1
00926   *         @arg @ref LL_LPUART_STOPBITS_2
00927   * @retval None
00928   */
00929 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00930 {
00931   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00932 }
00933
00934 /**
00935   * @brief  Retrieve the length of the stop bits
00936   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00937   * @param  LPUARTx LPUART Instance
00938   * @retval Returned value can be one of the following values:
00939   *         @arg @ref LL_LPUART_STOPBITS_1
00940   *         @arg @ref LL_LPUART_STOPBITS_2
00941   */
00942 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
00943 {
00944   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00945 }
00946
00947 /**
00948   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00949   * @note   Call of this function is equivalent to following function call sequence :
00950   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00951   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00952   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00953   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00954   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00955   *         CR1          M             LL_LPUART_ConfigCharacter\n
00956   *         CR2          STOP          LL_LPUART_ConfigCharacter
00957   * @param  LPUARTx LPUART Instance
00958   * @param  DataWidth This parameter can be one of the following values:
00959   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00960   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00961   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00962   * @param  Parity This parameter can be one of the following values:
00963   *         @arg @ref LL_LPUART_PARITY_NONE
00964   *         @arg @ref LL_LPUART_PARITY_EVEN
00965   *         @arg @ref LL_LPUART_PARITY_ODD
00966   * @param  StopBits This parameter can be one of the following values:
00967   *         @arg @ref LL_LPUART_STOPBITS_1
00968   *         @arg @ref LL_LPUART_STOPBITS_2
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00972                                                uint32_t StopBits)
00973 {
00974   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
00975   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00976 }
00977
00978 /**
00979   * @brief  Configure TX/RX pins swapping setting.
00980   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
00981   * @param  LPUARTx LPUART Instance
00982   * @param  SwapConfig This parameter can be one of the following values:
00983   *         @arg @ref LL_LPUART_TXRX_STANDARD
00984   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
00988 {
00989   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
00990 }
00991
00992 /**
00993   * @brief  Retrieve TX/RX pins swapping configuration.
00994   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
00995   * @param  LPUARTx LPUART Instance
00996   * @retval Returned value can be one of the following values:
00997   *         @arg @ref LL_LPUART_TXRX_STANDARD
00998   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00999   */
01000 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
01001 {
01002   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
01003 }
01004
01005 /**
01006   * @brief  Configure RX pin active level logic
01007   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
01008   * @param  LPUARTx LPUART Instance
01009   * @param  PinInvMethod This parameter can be one of the following values:
01010   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01011   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01012   * @retval None
01013   */
01014 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01015 {
01016   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01017 }
01018
01019 /**
01020   * @brief  Retrieve RX pin active level logic configuration
01021   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
01022   * @param  LPUARTx LPUART Instance
01023   * @retval Returned value can be one of the following values:
01024   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01025   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01026   */
01027 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
01028 {
01029   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
01030 }
01031
01032 /**
01033   * @brief  Configure TX pin active level logic
01034   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
01035   * @param  LPUARTx LPUART Instance
01036   * @param  PinInvMethod This parameter can be one of the following values:
01037   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01038   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01042 {
01043   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01044 }
01045
01046 /**
01047   * @brief  Retrieve TX pin active level logic configuration
01048   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
01049   * @param  LPUARTx LPUART Instance
01050   * @retval Returned value can be one of the following values:
01051   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01052   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01053   */
01054 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
01055 {
01056   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
01057 }
01058
01059 /**
01060   * @brief  Configure Binary data logic.
01061   *
01062   * @note   Allow to define how Logical data from the data register are send/received :
01063   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01064   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
01065   * @param  LPUARTx LPUART Instance
01066   * @param  DataLogic This parameter can be one of the following values:
01067   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01068   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
01072 {
01073   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
01074 }
01075
01076 /**
01077   * @brief  Retrieve Binary data configuration
01078   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
01079   * @param  LPUARTx LPUART Instance
01080   * @retval Returned value can be one of the following values:
01081   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01082   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01083   */
01084 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
01085 {
01086   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
01087 }
01088
01089 /**
01090   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01091   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01092   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01093   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
01094   * @param  LPUARTx LPUART Instance
01095   * @param  BitOrder This parameter can be one of the following values:
01096   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01097   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
01101 {
01102   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01103 }
01104
01105 /**
01106   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01107   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01108   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01109   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
01110   * @param  LPUARTx LPUART Instance
01111   * @retval Returned value can be one of the following values:
01112   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01113   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01114   */
01115 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
01116 {
01117   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
01118 }
01119
01120 /**
01121   * @brief  Set Address of the LPUART node.
01122   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01123   *         for wake up with address mark detection.
01124   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01125   *         (b7-b4 should be set to 0)
01126   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01127   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01128   *         for wake up with 7-bit address mark detection.
01129   *         The MSB of the character sent by the transmitter should be equal to 1.
01130   *         It may also be used for character detection during normal reception,
01131   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01132   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01133   *         value and CMF flag is set on match)
01134   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
01135   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
01136   * @param  LPUARTx LPUART Instance
01137   * @param  AddressLen This parameter can be one of the following values:
01138   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01139   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01140   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
01144 {
01145   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01146              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01147 }
01148
01149 /**
01150   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
01151   * @note   If 4-bit Address Detection is selected in ADDM7,
01152   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01153   *         If 7-bit Address Detection is selected in ADDM7,
01154   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01155   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
01156   * @param  LPUARTx LPUART Instance
01157   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
01158   */
01159 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
01160 {
01161   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01162 }
01163
01164 /**
01165   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01166   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
01167   * @param  LPUARTx LPUART Instance
01168   * @retval Returned value can be one of the following values:
01169   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01170   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01171   */
01172 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
01173 {
01174   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
01175 }
01176
01177 /**
01178   * @brief  Enable RTS HW Flow Control
01179   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
01180   * @param  LPUARTx LPUART Instance
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01184 {
01185   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01186 }
01187
01188 /**
01189   * @brief  Disable RTS HW Flow Control
01190   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
01191   * @param  LPUARTx LPUART Instance
01192   * @retval None
01193   */
01194 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01195 {
01196   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01197 }
01198
01199 /**
01200   * @brief  Enable CTS HW Flow Control
01201   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
01202   * @param  LPUARTx LPUART Instance
01203   * @retval None
01204   */
01205 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01206 {
01207   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01208 }
01209
01210 /**
01211   * @brief  Disable CTS HW Flow Control
01212   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
01213   * @param  LPUARTx LPUART Instance
01214   * @retval None
01215   */
01216 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01217 {
01218   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01219 }
01220
01221 /**
01222   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01223   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
01224   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
01225   * @param  LPUARTx LPUART Instance
01226   * @param  HardwareFlowControl This parameter can be one of the following values:
01227   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01228   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01229   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01230   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01231   * @retval None
01232   */
01233 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01234 {
01235   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01236 }
01237
01238 /**
01239   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01240   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01241   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01242   * @param  LPUARTx LPUART Instance
01243   * @retval Returned value can be one of the following values:
01244   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01245   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01246   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01247   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01248   */
01249 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
01250 {
01251   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01252 }
01253
01254 /**
01255   * @brief  Enable Overrun detection
01256   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01257   * @param  LPUARTx LPUART Instance
01258   * @retval None
01259   */
01260 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01261 {
01262   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01263 }
01264
01265 /**
01266   * @brief  Disable Overrun detection
01267   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01268   * @param  LPUARTx LPUART Instance
01269   * @retval None
01270   */
01271 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01272 {
01273   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01274 }
01275
01276 /**
01277   * @brief  Indicate if Overrun detection is enabled
01278   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01279   * @param  LPUARTx LPUART Instance
01280   * @retval State of bit (1 or 0).
01281   */
01282 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
01283 {
01284   return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01285 }
01286
01287 /**
01288   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01289   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01290   * @param  LPUARTx LPUART Instance
01291   * @param  Type This parameter can be one of the following values:
01292   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01293   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01294   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01295   * @retval None
01296   */
01297 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01298 {
01299   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01300 }
01301
01302 /**
01303   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01304   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01305   * @param  LPUARTx LPUART Instance
01306   * @retval Returned value can be one of the following values:
01307   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01308   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01309   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01310   */
01311 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
01312 {
01313   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01314 }
01315
01316 /**
01317   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01318   *
01319   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01320   *         according to used Peripheral Clock and expected Baud Rate values
01321   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01322   *         (Baud rate value != 0).
01323   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01324   *         a care should be taken when generating high baud rates using high PeriphClk
01325   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01326   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01327   * @param  LPUARTx LPUART Instance
01328   * @param  PeriphClk Peripheral Clock
01329   * @param  PrescalerValue This parameter can be one of the following values:
01330   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01331   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01332   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01333   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01334   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01335   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01336   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01337   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01338   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01339   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01340   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01341   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01342   * @param  BaudRate Baud Rate
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01346                                            uint32_t BaudRate)
01347 {
01348   LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
01349 }
01350
01351 /**
01352   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01353   *         (full BRR content), and to used Peripheral Clock values
01354   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01355   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01356   * @param  LPUARTx LPUART Instance
01357   * @param  PeriphClk Peripheral Clock
01358   * @param  PrescalerValue This parameter can be one of the following values:
01359   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01360   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01361   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01362   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01363   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01364   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01365   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01366   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01367   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01368   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01369   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01370   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01371   * @retval Baud Rate
01372   */
01373 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
01374 {
01375   register uint32_t lpuartdiv;
01376   register uint32_t brrresult;
01377   register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01378
01379   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01380
01381   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01382   {
01383     brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01384   }
01385   else
01386   {
01387     brrresult = 0x0UL;
01388   }
01389
01390   return (brrresult);
01391 }
01392
01393 /**
01394   * @}
01395   */
01396
01397 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01398   * @{
01399   */
01400
01401 /**
01402   * @brief  Enable Single Wire Half-Duplex mode
01403   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01404   * @param  LPUARTx LPUART Instance
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01408 {
01409   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01410 }
01411
01412 /**
01413   * @brief  Disable Single Wire Half-Duplex mode
01414   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01415   * @param  LPUARTx LPUART Instance
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01419 {
01420   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01421 }
01422
01423 /**
01424   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01425   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01426   * @param  LPUARTx LPUART Instance
01427   * @retval State of bit (1 or 0).
01428   */
01429 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
01430 {
01431   return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
01432 }
01433
01434 /**
01435   * @}
01436   */
01437
01438 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01439   * @{
01440   */
01441
01442 /**
01443   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01444   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01445   * @param  LPUARTx LPUART Instance
01446   * @param  Time Value between Min_Data=0 and Max_Data=31
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01450 {
01451   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
01452 }
01453
01454 /**
01455   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01456   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01457   * @param  LPUARTx LPUART Instance
01458   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01459   */
01460 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
01461 {
01462   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
01463 }
01464
01465 /**
01466   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01467   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01468   * @param  LPUARTx LPUART Instance
01469   * @param  Time Value between Min_Data=0 and Max_Data=31
01470   * @retval None
01471   */
01472 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01473 {
01474   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
01475 }
01476
01477 /**
01478   * @brief  Return DEAT (Driver Enable Assertion Time)
01479   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01480   * @param  LPUARTx LPUART Instance
01481   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01482   */
01483 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
01484 {
01485   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
01486 }
01487
01488 /**
01489   * @brief  Enable Driver Enable (DE) Mode
01490   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01491   * @param  LPUARTx LPUART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01495 {
01496   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01497 }
01498
01499 /**
01500   * @brief  Disable Driver Enable (DE) Mode
01501   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01502   * @param  LPUARTx LPUART Instance
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01506 {
01507   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01508 }
01509
01510 /**
01511   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01512   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01513   * @param  LPUARTx LPUART Instance
01514   * @retval State of bit (1 or 0).
01515   */
01516 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
01517 {
01518   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
01519 }
01520
01521 /**
01522   * @brief  Select Driver Enable Polarity
01523   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01524   * @param  LPUARTx LPUART Instance
01525   * @param  Polarity This parameter can be one of the following values:
01526   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01527   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01528   * @retval None
01529   */
01530 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01531 {
01532   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01533 }
01534
01535 /**
01536   * @brief  Return Driver Enable Polarity
01537   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01538   * @param  LPUARTx LPUART Instance
01539   * @retval Returned value can be one of the following values:
01540   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01541   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01542   */
01543 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
01544 {
01545   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01546 }
01547
01548 /**
01549   * @}
01550   */
01551
01552 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01553   * @{
01554   */
01555
01556 /**
01557   * @brief  Check if the LPUART Parity Error Flag is set or not
01558   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01559   * @param  LPUARTx LPUART Instance
01560   * @retval State of bit (1 or 0).
01561   */
01562 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
01563 {
01564   return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
01565 }
01566
01567 /**
01568   * @brief  Check if the LPUART Framing Error Flag is set or not
01569   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01570   * @param  LPUARTx LPUART Instance
01571   * @retval State of bit (1 or 0).
01572   */
01573 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
01574 {
01575   return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
01576 }
01577
01578 /**
01579   * @brief  Check if the LPUART Noise error detected Flag is set or not
01580   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01581   * @param  LPUARTx LPUART Instance
01582   * @retval State of bit (1 or 0).
01583   */
01584 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
01585 {
01586   return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
01587 }
01588
01589 /**
01590   * @brief  Check if the LPUART OverRun Error Flag is set or not
01591   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01592   * @param  LPUARTx LPUART Instance
01593   * @retval State of bit (1 or 0).
01594   */
01595 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
01596 {
01597   return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
01598 }
01599
01600 /**
01601   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01602   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01603   * @param  LPUARTx LPUART Instance
01604   * @retval State of bit (1 or 0).
01605   */
01606 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
01607 {
01608   return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
01609 }
01610
01611 /* Legacy define */
01612 #define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
01613
01614 /**
01615   * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
01616   * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
01617   * @param  LPUARTx LPUART Instance
01618   * @retval State of bit (1 or 0).
01619   */
01620 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01621 {
01622   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
01623 }
01624
01625 /**
01626   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01627   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01628   * @param  LPUARTx LPUART Instance
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
01632 {
01633   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
01634 }
01635
01636 /* Legacy define */
01637 #define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
01638
01639 /**
01640   * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
01641   * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
01642   * @param  LPUARTx LPUART Instance
01643   * @retval State of bit (1 or 0).
01644   */
01645 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
01646 {
01647   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
01648 }
01649
01650 /**
01651   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01652   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01653   * @param  LPUARTx LPUART Instance
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
01657 {
01658   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Check if the LPUART CTS Flag is set or not
01663   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01664   * @param  LPUARTx LPUART Instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
01668 {
01669   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
01670 }
01671
01672 /**
01673   * @brief  Check if the LPUART Busy Flag is set or not
01674   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01675   * @param  LPUARTx LPUART Instance
01676   * @retval State of bit (1 or 0).
01677   */
01678 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
01679 {
01680   return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
01681 }
01682
01683 /**
01684   * @brief  Check if the LPUART Character Match Flag is set or not
01685   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01686   * @param  LPUARTx LPUART Instance
01687   * @retval State of bit (1 or 0).
01688   */
01689 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
01690 {
01691   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
01692 }
01693
01694 /**
01695   * @brief  Check if the LPUART Send Break Flag is set or not
01696   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01697   * @param  LPUARTx LPUART Instance
01698   * @retval State of bit (1 or 0).
01699   */
01700 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
01701 {
01702   return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
01703 }
01704
01705 /**
01706   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01707   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01708   * @param  LPUARTx LPUART Instance
01709   * @retval State of bit (1 or 0).
01710   */
01711 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
01712 {
01713   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
01714 }
01715
01716 /**
01717   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01718   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01719   * @param  LPUARTx LPUART Instance
01720   * @retval State of bit (1 or 0).
01721   */
01722 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
01723 {
01724   return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
01725 }
01726
01727 /**
01728   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01729   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01730   * @param  LPUARTx LPUART Instance
01731   * @retval State of bit (1 or 0).
01732   */
01733 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
01734 {
01735   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
01736 }
01737
01738 /**
01739   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01740   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01741   * @param  LPUARTx LPUART Instance
01742   * @retval State of bit (1 or 0).
01743   */
01744 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
01745 {
01746   return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
01747 }
01748
01749 /**
01750   * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
01751   * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
01752   * @param  LPUARTx LPUART Instance
01753   * @retval State of bit (1 or 0).
01754   */
01755 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
01756 {
01757   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
01758 }
01759
01760 /**
01761   * @brief  Check if the LPUART RX FIFO Full Flag is set or not
01762   * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
01763   * @param  LPUARTx LPUART Instance
01764   * @retval State of bit (1 or 0).
01765   */
01766 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
01767 {
01768   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
01769 }
01770
01771 /**
01772   * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
01773   * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
01774   * @param  LPUARTx LPUART Instance
01775   * @retval State of bit (1 or 0).
01776   */
01777 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
01778 {
01779   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
01780 }
01781
01782 /**
01783   * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
01784   * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
01785   * @param  LPUARTx LPUART Instance
01786   * @retval State of bit (1 or 0).
01787   */
01788 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
01789 {
01790   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
01791 }
01792
01793 /**
01794   * @brief  Clear Parity Error Flag
01795   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01796   * @param  LPUARTx LPUART Instance
01797   * @retval None
01798   */
01799 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01800 {
01801   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01802 }
01803
01804 /**
01805   * @brief  Clear Framing Error Flag
01806   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01807   * @param  LPUARTx LPUART Instance
01808   * @retval None
01809   */
01810 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01811 {
01812   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01813 }
01814
01815 /**
01816   * @brief  Clear Noise detected Flag
01817   * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
01818   * @param  LPUARTx LPUART Instance
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01822 {
01823   WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
01824 }
01825
01826 /**
01827   * @brief  Clear OverRun Error Flag
01828   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01829   * @param  LPUARTx LPUART Instance
01830   * @retval None
01831   */
01832 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01833 {
01834   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01835 }
01836
01837 /**
01838   * @brief  Clear IDLE line detected Flag
01839   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01840   * @param  LPUARTx LPUART Instance
01841   * @retval None
01842   */
01843 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01844 {
01845   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01846 }
01847
01848 /**
01849   * @brief  Clear TX FIFO Empty Flag
01850   * @rmtoll ICR          TXFECF        LL_LPUART_ClearFlag_TXFE
01851   * @param  LPUARTx LPUART Instance
01852   * @retval None
01853   */
01854 __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
01855 {
01856   WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
01857 }
01858
01859 /**
01860   * @brief  Clear Transmission Complete Flag
01861   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01862   * @param  LPUARTx LPUART Instance
01863   * @retval None
01864   */
01865 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01866 {
01867   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01868 }
01869
01870 /**
01871   * @brief  Clear CTS Interrupt Flag
01872   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01873   * @param  LPUARTx LPUART Instance
01874   * @retval None
01875   */
01876 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01877 {
01878   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01879 }
01880
01881 /**
01882   * @brief  Clear Character Match Flag
01883   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01884   * @param  LPUARTx LPUART Instance
01885   * @retval None
01886   */
01887 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01888 {
01889   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01890 }
01891
01892 /**
01893   * @brief  Clear Wake Up from stop mode Flag
01894   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01895   * @param  LPUARTx LPUART Instance
01896   * @retval None
01897   */
01898 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01899 {
01900   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01901 }
01902
01903 /**
01904   * @}
01905   */
01906
01907 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01908   * @{
01909   */
01910
01911 /**
01912   * @brief  Enable IDLE Interrupt
01913   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01914   * @param  LPUARTx LPUART Instance
01915   * @retval None
01916   */
01917 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01918 {
01919   SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01920 }
01921
01922 /* Legacy define */
01923 #define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
01924
01925 /**
01926   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
01927   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
01928   * @param  LPUARTx LPUART Instance
01929   * @retval None
01930   */
01931 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01932 {
01933   SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
01934 }
01935
01936 /**
01937   * @brief  Enable Transmission Complete Interrupt
01938   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01939   * @param  LPUARTx LPUART Instance
01940   * @retval None
01941   */
01942 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01943 {
01944   SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01945 }
01946
01947 /* Legacy define */
01948 #define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
01949
01950 /**
01951   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
01952   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
01953   * @param  LPUARTx LPUART Instance
01954   * @retval None
01955   */
01956 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
01957 {
01958   SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
01959 }
01960
01961 /**
01962   * @brief  Enable Parity Error Interrupt
01963   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01964   * @param  LPUARTx LPUART Instance
01965   * @retval None
01966   */
01967 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01968 {
01969   SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01970 }
01971
01972 /**
01973   * @brief  Enable Character Match Interrupt
01974   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01975   * @param  LPUARTx LPUART Instance
01976   * @retval None
01977   */
01978 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01979 {
01980   SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01981 }
01982
01983 /**
01984   * @brief  Enable TX FIFO Empty Interrupt
01985   * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
01986   * @param  LPUARTx LPUART Instance
01987   * @retval None
01988   */
01989 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
01990 {
01991   SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
01992 }
01993
01994 /**
01995   * @brief  Enable RX FIFO Full Interrupt
01996   * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
01997   * @param  LPUARTx LPUART Instance
01998   * @retval None
01999   */
02000 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
02001 {
02002   SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02003 }
02004
02005 /**
02006   * @brief  Enable Error Interrupt
02007   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02008   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02009   *         - 0: Interrupt is inhibited
02010   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02011   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
02012   * @param  LPUARTx LPUART Instance
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
02016 {
02017   SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
02018 }
02019
02020 /**
02021   * @brief  Enable CTS Interrupt
02022   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
02023   * @param  LPUARTx LPUART Instance
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
02027 {
02028   SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02029 }
02030
02031 /**
02032   * @brief  Enable Wake Up from Stop Mode Interrupt
02033   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
02034   * @param  LPUARTx LPUART Instance
02035   * @retval None
02036   */
02037 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
02038 {
02039   SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02040 }
02041
02042 /**
02043   * @brief  Enable TX FIFO Threshold Interrupt
02044   * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
02045   * @param  LPUARTx LPUART Instance
02046   * @retval None
02047   */
02048 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
02049 {
02050   SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02051 }
02052
02053 /**
02054   * @brief  Enable RX FIFO Threshold Interrupt
02055   * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
02056   * @param  LPUARTx LPUART Instance
02057   * @retval None
02058   */
02059 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
02060 {
02061   SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02062 }
02063
02064 /**
02065   * @brief  Disable IDLE Interrupt
02066   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
02067   * @param  LPUARTx LPUART Instance
02068   * @retval None
02069   */
02070 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
02071 {
02072   CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
02073 }
02074
02075 /* Legacy define */
02076 #define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
02077
02078 /**
02079   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
02080   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
02081   * @param  LPUARTx LPUART Instance
02082   * @retval None
02083   */
02084 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02085 {
02086   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
02087 }
02088
02089 /**
02090   * @brief  Disable Transmission Complete Interrupt
02091   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
02092   * @param  LPUARTx LPUART Instance
02093   * @retval None
02094   */
02095 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
02096 {
02097   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
02098 }
02099
02100 /* Legacy define */
02101 #define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
02102
02103 /**
02104   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
02105   * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
02106   * @param  LPUARTx LPUART Instance
02107   * @retval None
02108   */
02109 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02110 {
02111   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
02112 }
02113
02114 /**
02115   * @brief  Disable Parity Error Interrupt
02116   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
02117   * @param  LPUARTx LPUART Instance
02118   * @retval None
02119   */
02120 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
02121 {
02122   CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
02123 }
02124
02125 /**
02126   * @brief  Disable Character Match Interrupt
02127   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
02128   * @param  LPUARTx LPUART Instance
02129   * @retval None
02130   */
02131 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
02132 {
02133   CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
02134 }
02135
02136 /**
02137   * @brief  Disable TX FIFO Empty Interrupt
02138   * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
02139   * @param  LPUARTx LPUART Instance
02140   * @retval None
02141   */
02142 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
02143 {
02144   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02145 }
02146
02147 /**
02148   * @brief  Disable RX FIFO Full Interrupt
02149   * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
02150   * @param  LPUARTx LPUART Instance
02151   * @retval None
02152   */
02153 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
02154 {
02155   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02156 }
02157
02158 /**
02159   * @brief  Disable Error Interrupt
02160   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02161   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02162   *         - 0: Interrupt is inhibited
02163   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02164   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
02165   * @param  LPUARTx LPUART Instance
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
02169 {
02170   CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
02171 }
02172
02173 /**
02174   * @brief  Disable CTS Interrupt
02175   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
02176   * @param  LPUARTx LPUART Instance
02177   * @retval None
02178   */
02179 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
02180 {
02181   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02182 }
02183
02184 /**
02185   * @brief  Disable Wake Up from Stop Mode Interrupt
02186   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
02187   * @param  LPUARTx LPUART Instance
02188   * @retval None
02189   */
02190 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
02191 {
02192   CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02193 }
02194
02195 /**
02196   * @brief  Disable TX FIFO Threshold Interrupt
02197   * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
02198   * @param  LPUARTx LPUART Instance
02199   * @retval None
02200   */
02201 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
02202 {
02203   CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02204 }
02205
02206 /**
02207   * @brief  Disable RX FIFO Threshold Interrupt
02208   * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
02209   * @param  LPUARTx LPUART Instance
02210   * @retval None
02211   */
02212 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
02213 {
02214   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02215 }
02216
02217 /**
02218   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
02219   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
02220   * @param  LPUARTx LPUART Instance
02221   * @retval State of bit (1 or 0).
02222   */
02223 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
02224 {
02225   return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
02226 }
02227
02228 /* Legacy define */
02229 #define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02230
02231 /**
02232   * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
02233   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02234   * @param  LPUARTx LPUART Instance
02235   * @retval State of bit (1 or 0).
02236   */
02237 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02238 {
02239   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
02240 }
02241
02242 /**
02243   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
02244   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
02245   * @param  LPUARTx LPUART Instance
02246   * @retval State of bit (1 or 0).
02247   */
02248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
02249 {
02250   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
02251 }
02252
02253 /* Legacy define */
02254 #define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02255
02256 /**
02257   * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
02258   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02259   * @param  LPUARTx LPUART Instance
02260   * @retval State of bit (1 or 0).
02261   */
02262 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02263 {
02264   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
02265 }
02266
02267 /**
02268   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
02269   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
02270   * @param  LPUARTx LPUART Instance
02271   * @retval State of bit (1 or 0).
02272   */
02273 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
02274 {
02275   return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
02276 }
02277
02278 /**
02279   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
02280   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
02281   * @param  LPUARTx LPUART Instance
02282   * @retval State of bit (1 or 0).
02283   */
02284 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
02285 {
02286   return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
02287 }
02288
02289 /**
02290   * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
02291   * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
02292   * @param  LPUARTx LPUART Instance
02293   * @retval State of bit (1 or 0).
02294   */
02295 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
02296 {
02297   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
02298 }
02299
02300 /**
02301   * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
02302   * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
02303   * @param  LPUARTx LPUART Instance
02304   * @retval State of bit (1 or 0).
02305   */
02306 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
02307 {
02308   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
02309 }
02310
02311 /**
02312   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
02313   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
02314   * @param  LPUARTx LPUART Instance
02315   * @retval State of bit (1 or 0).
02316   */
02317 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
02318 {
02319   return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
02320 }
02321
02322 /**
02323   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
02324   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
02325   * @param  LPUARTx LPUART Instance
02326   * @retval State of bit (1 or 0).
02327   */
02328 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
02329 {
02330   return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
02331 }
02332
02333 /**
02334   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
02335   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
02336   * @param  LPUARTx LPUART Instance
02337   * @retval State of bit (1 or 0).
02338   */
02339 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
02340 {
02341   return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
02342 }
02343
02344 /**
02345   * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
02346   * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
02347   * @param  LPUARTx LPUART Instance
02348   * @retval State of bit (1 or 0).
02349   */
02350 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
02351 {
02352   return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
02353 }
02354
02355 /**
02356   * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
02357   * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
02358   * @param  LPUARTx LPUART Instance
02359   * @retval State of bit (1 or 0).
02360   */
02361 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
02362 {
02363   return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
02364 }
02365
02366 /**
02367   * @}
02368   */
02369
02370 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
02371   * @{
02372   */
02373
02374 /**
02375   * @brief  Enable DMA Mode for reception
02376   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
02377   * @param  LPUARTx LPUART Instance
02378   * @retval None
02379   */
02380 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
02381 {
02382   SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02383 }
02384
02385 /**
02386   * @brief  Disable DMA Mode for reception
02387   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
02388   * @param  LPUARTx LPUART Instance
02389   * @retval None
02390   */
02391 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
02392 {
02393   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02394 }
02395
02396 /**
02397   * @brief  Check if DMA Mode is enabled for reception
02398   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
02399   * @param  LPUARTx LPUART Instance
02400   * @retval State of bit (1 or 0).
02401   */
02402 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
02403 {
02404   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
02405 }
02406
02407 /**
02408   * @brief  Enable DMA Mode for transmission
02409   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
02410   * @param  LPUARTx LPUART Instance
02411   * @retval None
02412   */
02413 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
02414 {
02415   SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02416 }
02417
02418 /**
02419   * @brief  Disable DMA Mode for transmission
02420   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
02421   * @param  LPUARTx LPUART Instance
02422   * @retval None
02423   */
02424 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
02425 {
02426   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02427 }
02428
02429 /**
02430   * @brief  Check if DMA Mode is enabled for transmission
02431   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
02432   * @param  LPUARTx LPUART Instance
02433   * @retval State of bit (1 or 0).
02434   */
02435 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
02436 {
02437   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
02438 }
02439
02440 /**
02441   * @brief  Enable DMA Disabling on Reception Error
02442   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
02443   * @param  LPUARTx LPUART Instance
02444   * @retval None
02445   */
02446 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02447 {
02448   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02449 }
02450
02451 /**
02452   * @brief  Disable DMA Disabling on Reception Error
02453   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
02454   * @param  LPUARTx LPUART Instance
02455   * @retval None
02456   */
02457 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02458 {
02459   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02460 }
02461
02462 /**
02463   * @brief  Indicate if DMA Disabling on Reception Error is disabled
02464   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
02465   * @param  LPUARTx LPUART Instance
02466   * @retval State of bit (1 or 0).
02467   */
02468 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02469 {
02470   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
02471 }
02472
02473 /**
02474   * @brief  Get the LPUART data register address used for DMA transfer
02475   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
02476   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02477   * @param  LPUARTx LPUART Instance
02478   * @param  Direction This parameter can be one of the following values:
02479   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02480   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02481   * @retval Address of data register
02482   */
02483 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
02484 {
02485   register uint32_t data_reg_addr;
02486
02487   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02488   {
02489     /* return address of TDR register */
02490     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02491   }
02492   else
02493   {
02494     /* return address of RDR register */
02495     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02496   }
02497
02498   return data_reg_addr;
02499 }
02500
02501 /**
02502   * @}
02503   */
02504
02505 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02506   * @{
02507   */
02508
02509 /**
02510   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02511   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02512   * @param  LPUARTx LPUART Instance
02513   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02514   */
02515 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
02516 {
02517   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
02518 }
02519
02520 /**
02521   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02522   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02523   * @param  LPUARTx LPUART Instance
02524   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02525   */
02526 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
02527 {
02528   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02529 }
02530
02531 /**
02532   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02533   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02534   * @param  LPUARTx LPUART Instance
02535   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02536   * @retval None
02537   */
02538 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02539 {
02540   LPUARTx->TDR = Value;
02541 }
02542
02543 /**
02544   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02545   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02546   * @param  LPUARTx LPUART Instance
02547   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02548   * @retval None
02549   */
02550 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02551 {
02552   LPUARTx->TDR = Value & 0x1FFUL;
02553 }
02554
02555 /**
02556   * @}
02557   */
02558
02559 /** @defgroup LPUART_LL_EF_Execution Execution
02560   * @{
02561   */
02562
02563 /**
02564   * @brief  Request Break sending
02565   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02566   * @param  LPUARTx LPUART Instance
02567   * @retval None
02568   */
02569 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02570 {
02571   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
02572 }
02573
02574 /**
02575   * @brief  Put LPUART in mute mode and set the RWU flag
02576   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02577   * @param  LPUARTx LPUART Instance
02578   * @retval None
02579   */
02580 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02581 {
02582   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
02583 }
02584
02585 /**
02586   * @brief  Request a Receive Data and FIFO flush
02587   * @note   Allows to discard the received data without reading them, and avoid an overrun
02588   *         condition.
02589   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02590   * @param  LPUARTx LPUART Instance
02591   * @retval None
02592   */
02593 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02594 {
02595   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
02596 }
02597
02598 /**
02599   * @}
02600   */
02601
02602 #if defined(USE_FULL_LL_DRIVER)
02603 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02604   * @{
02605   */
02606 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
02607 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
02608 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02609 /**
02610   * @}
02611   */
02612 #endif /* USE_FULL_LL_DRIVER */
02613
02614 /**
02615   * @}
02616   */
02617
02618 /**
02619   * @}
02620   */
02621
02622 #endif /* LPUART1 */
02623
02624 /**
02625   * @}
02626   */
02627
02628 #ifdef __cplusplus
02629 }
02630 #endif
02631
02632 #endif /* STM32H7xx_LL_LPUART_H */
02633
02634 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_mdma.c Source File

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stm32h7xx_ll_mdma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_mdma.c
00004   * @author  MCD Application Team
00005   * @brief   MDMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_mdma.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (MDMA)
00035
00036 /** @defgroup MDMA_LL MDMA
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup MDMA_LL_Private_Macros
00045   * @{
00046   */
00047
00048 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \
00049                                                             (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
00050                                                              ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
00051                                                              ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
00052                                                              ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
00053                                                              ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
00054                                                              ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
00055                                                              ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
00056                                                              ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
00057                                                              ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
00058                                                              ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
00059                                                              ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
00060                                                              ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
00061                                                              ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
00062                                                              ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
00063                                                              ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
00064                                                              ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
00065                                                              ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))
00066
00067 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__)              ((__VALUE__)  <= 0x00010000U)
00068
00069 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__)             ((__VALUE__)  <= 0x00000FFFU)
00070
00071 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__)               (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
00072                                                            ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))
00073
00074 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__)           (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
00075                                                            ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))
00076
00077 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__)               (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
00078                                                            ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))
00079
00080 #define IS_LL_MDMA_PRIORITY(__VALUE__)                    (((__VALUE__) == LL_MDMA_PRIORITY_LOW)    || \
00081                                                            ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
00082                                                            ((__VALUE__) == LL_MDMA_PRIORITY_HIGH)   || \
00083                                                            ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))
00084
00085 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__)               (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
00086                                                            ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))
00087
00088 #define IS_LL_MDMA_REQUESTMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
00089                                                            ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))
00090
00091 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER)       || \
00092                                                            ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER)        || \
00093                                                            ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
00094                                                            ((__VALUE__) == LL_MDMA_FULL_TRANSFER))
00095
00096 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__)           (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT)        || \
00097                                                            ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
00098                                                            ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))
00099
00100 #define IS_LL_MDMA_PACKMODE(__VALUE__)                    (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
00101                                                            ((__VALUE__) == LL_MDMA_PACK_ENABLE))
00102
00103 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__)           ((__VALUE__)  <= 0x0000007FU)
00104
00105 #define IS_LL_MDMA_DESTBURST(__VALUE__)                   (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
00106                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
00107                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
00108                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
00109                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
00110                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
00111                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
00112                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))
00113
00114 #define IS_LL_MDMA_SRCTBURST(__VALUE__)                   (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
00115                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
00116                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
00117                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
00118                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
00119                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
00120                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
00121                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))
00122
00123 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__)                 (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
00124                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
00125                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
00126                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))
00127
00128 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__)                  (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE)     || \
00129                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
00130                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD)     || \
00131                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))
00132
00133 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__)                (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
00134                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
00135                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
00136                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))
00137
00138 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__)                 (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
00139                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
00140                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
00141                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))
00142
00143 #define IS_LL_MDMA_DESTINCMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_DEST_FIXED) || \
00144                                                            ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
00145                                                            ((__VALUE__) == LL_MDMA_DEST_DECREMENT))
00146
00147 #define IS_LL_MDMA_SRCINCMODE(__VALUE__)                  (((__VALUE__) == LL_MDMA_SRC_FIXED) || \
00148                                                            ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
00149                                                            ((__VALUE__) == LL_MDMA_SRC_DECREMENT))
00150
00151 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__)  (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
00152                                                            ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))
00153
00154
00155 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__)   (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
00156                                                            ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))
00157
00158 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__)   ((__VALUE__)  <= 0x0000FFFFU)
00159
00160 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__)    ((__VALUE__)  <= 0x0000FFFFU)
00161
00162 #define IS_LL_MDMA_DEST_BUS(__VALUE__)                    (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
00163                                                            ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))
00164
00165 #define IS_LL_MDMA_SRC_BUS(__VALUE__)                     (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
00166                                                            ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))
00167 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */
00168 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
00169                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
00170                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
00171                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
00172                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
00173                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
00174                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
00175                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
00176                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
00177                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
00178                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
00179                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
00180                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
00181                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
00182                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
00183                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
00184                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
00185                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
00186                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
00187                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
00188                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
00189                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
00190                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
00191                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
00192                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
00193                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
00194                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
00195                                                            ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT)   || \
00196                                                            ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH)      || \
00197                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
00198                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
00199                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
00200 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */
00201 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
00202                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
00203                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
00204                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
00205                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
00206                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
00207                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
00208                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
00209                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
00210                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
00211                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
00212                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
00213                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
00214                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
00215                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
00216                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
00217                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
00218                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
00219                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
00220                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
00221                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
00222                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
00223                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
00224                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
00225                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
00226                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
00227                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
00228                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
00229                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
00230                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
00231 #elif defined (QUADSPI) /* STM32H742 devices */
00232 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
00233                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
00234                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
00235                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
00236                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
00237                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
00238                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
00239                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
00240                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
00241                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
00242                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
00243                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
00244                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
00245                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
00246                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
00247                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
00248                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
00249                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
00250                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
00251                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
00252                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
00253                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
00254                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
00255                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
00256
00257 #else /* STM32H7A3/B3 devices */
00258 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
00259                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
00260                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
00261                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
00262                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
00263                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
00264                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
00265                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
00266                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
00267                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
00268                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
00269                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
00270                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
00271                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
00272                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
00273                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
00274                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
00275                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
00276                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
00277                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
00278                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
00279                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
00280                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH)     || \
00281                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC)          || \
00282                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
00283                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
00284                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
00285                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
00286                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
00287                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)   || \
00288                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH)     || \
00289                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
00290
00291 #endif /* QUADSPI && JPEG && DSI */
00292 /**
00293   * @}
00294   */
00295
00296 /* Private function prototypes -----------------------------------------------*/
00297
00298 /* Exported functions --------------------------------------------------------*/
00299 /** @addtogroup MDMA_LL_Exported_Functions
00300   * @{
00301   */
00302
00303 /** @addtogroup MDMA_LL_EF_Init
00304   * @{
00305   */
00306
00307 /**
00308   * @brief  De-initialize the MDMA registers to their default reset values.
00309   * @param  MDMAx MDMAx Instance
00310   * @param  Channel This parameter can be one of the following values:
00311   *         @arg @ref LL_MDMA_CHANNEL_0
00312   *         @arg @ref LL_MDMA_CHANNEL_1
00313   *         @arg @ref LL_MDMA_CHANNEL_2
00314   *         @arg @ref LL_MDMA_CHANNEL_3
00315   *         @arg @ref LL_MDMA_CHANNEL_4
00316   *         @arg @ref LL_MDMA_CHANNEL_5
00317   *         @arg @ref LL_MDMA_CHANNEL_6
00318   *         @arg @ref LL_MDMA_CHANNEL_7
00319   *         @arg @ref LL_MDMA_CHANNEL_8
00320   *         @arg @ref LL_MDMA_CHANNEL_9
00321   *         @arg @ref LL_MDMA_CHANNEL_10
00322   *         @arg @ref LL_MDMA_CHANNEL_11
00323   *         @arg @ref LL_MDMA_CHANNEL_12
00324   *         @arg @ref LL_MDMA_CHANNEL_13
00325   *         @arg @ref LL_MDMA_CHANNEL_14
00326   *         @arg @ref LL_MDMA_CHANNEL_15
00327   *         @arg @ref LL_MDMA_CHANNEL_ALL
00328   * @retval An ErrorStatus enumeration value:
00329   *          - SUCCESS: MDMA registers are de-initialized
00330   *          - ERROR: Not applicable
00331   */
00332 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel)
00333 {
00334   MDMA_Channel_TypeDef *tmp;
00335   ErrorStatus status = SUCCESS;
00336
00337   /* Check the MDMA Instance MDMAx and Channel parameters*/
00338   assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
00339
00340   if (Channel == LL_MDMA_CHANNEL_ALL)
00341   {
00342     LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA);
00343     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA);
00344   }
00345   else
00346   {
00347     /* Disable the selected Channel */
00348     LL_MDMA_DisableChannel(MDMAx,Channel);
00349
00350     /* Get the MDMA Channel Instance */
00351     tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel));
00352
00353     /* Reset MDMAx_Channely control register */
00354     LL_MDMA_WriteReg(tmp, CCR, 0U);
00355
00356     /* Reset MDMAx_Channely Configuration register */
00357     LL_MDMA_WriteReg(tmp, CTCR, 0U);
00358
00359     /* Reset MDMAx_Channely block number of data register */
00360     LL_MDMA_WriteReg(tmp, CBNDTR, 0U);
00361
00362     /* Reset MDMAx_Channely source address register */
00363     LL_MDMA_WriteReg(tmp, CSAR, 0U);
00364
00365     /* Reset MDMAx_Channely destination address register */
00366     LL_MDMA_WriteReg(tmp, CDAR, 0U);
00367
00368     /* Reset MDMAx_Channely Block Repeat address Update register */
00369     LL_MDMA_WriteReg(tmp, CBRUR, 0U);
00370
00371     /* Reset MDMAx_Channely Link Address register */
00372     LL_MDMA_WriteReg(tmp, CLAR, 0U);
00373
00374     /* Reset MDMAx_Channely Trigger and Bus selection register */
00375     LL_MDMA_WriteReg(tmp, CTBR, 0U);
00376
00377     /* Reset MDMAx_Channely Mask address register */
00378     LL_MDMA_WriteReg(tmp, CMAR, 0U);
00379
00380     /* Reset MDMAx_Channely Mask Data register */
00381     LL_MDMA_WriteReg(tmp, CMDR, 0U);
00382
00383     /* Reset the Channel pending flags */
00384     LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU);
00385   }
00386
00387   return (uint32_t)status;
00388 }
00389
00390 /**
00391   * @brief  Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
00392   * @note   To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
00393   *         @arg @ref LL_MDMA_GET_INSTANCE
00394   *         @arg @ref LL_MDMA_GET_CHANNEL
00395   * @param  MDMAx MDMAx Instance
00396   * @param  Channel This parameter can be one of the following values:
00397   *         @arg @ref LL_MDMA_CHANNEL_0
00398   *         @arg @ref LL_MDMA_CHANNEL_1
00399   *         @arg @ref LL_MDMA_CHANNEL_2
00400   *         @arg @ref LL_MDMA_CHANNEL_3
00401   *         @arg @ref LL_MDMA_CHANNEL_4
00402   *         @arg @ref LL_MDMA_CHANNEL_5
00403   *         @arg @ref LL_MDMA_CHANNEL_6
00404   *         @arg @ref LL_MDMA_CHANNEL_7
00405   *         @arg @ref LL_MDMA_CHANNEL_8
00406   *         @arg @ref LL_MDMA_CHANNEL_9
00407   *         @arg @ref LL_MDMA_CHANNEL_10
00408   *         @arg @ref LL_MDMA_CHANNEL_11
00409   *         @arg @ref LL_MDMA_CHANNEL_12
00410   *         @arg @ref LL_MDMA_CHANNEL_13
00411   *         @arg @ref LL_MDMA_CHANNEL_14
00412   *         @arg @ref LL_MDMA_CHANNEL_15
00413   * @param  MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure.
00414   * @retval An ErrorStatus enumeration value:
00415   *          - SUCCESS: MDMA registers are initialized
00416   *          - ERROR: Not applicable
00417   */
00418 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
00419 {
00420   /* Check the MDMA Instance MDMAx and Channel parameters*/
00421   assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
00422
00423   /* Check the MDMA parameters from MDMA_InitStruct */
00424   assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
00425   assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
00426   assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess));
00427   assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess));
00428   assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess));
00429   assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority));
00430   assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
00431   assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
00432   assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
00433   assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
00434   assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
00435   assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
00436   assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
00437   assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
00438   assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
00439   assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
00440   assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
00441   assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
00442   assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
00443   assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
00444   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
00445   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
00446   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
00447   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
00448   assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
00449   assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
00450   assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
00451
00452
00453   /*-------------------------- MDMAx CCR Configuration --------------------------
00454    * Configure the Transfer endianness na priority with parameter :
00455    * - WordEndianess:     MDMA_CCR_WEX[14] bit
00456    * - HalfWordEndianess: MDMA_CCR_HEX[13] bit
00457    * - WordEndianess:     MDMA_CCR_BEX[12] bit
00458    * - Priority:          MDMA_CCR_BEX[7:6] bits
00459    */
00460   LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess     | \
00461                                                MDMA_InitStruct->HalfWordEndianess | \
00462                                                MDMA_InitStruct->ByteEndianess);
00463
00464   LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority);
00465
00466   /*-------------------------- MDMAx CTCR Configuration --------------------------
00467    * Configure the Transfer  parameter :
00468    * - BufferableWriteMode:     MDMA_CTCR_BWM[31] bit
00469    * - RequestMode:             MDMA_CTCR_SWRM[30] bit
00470    * - TriggerMode:             MDMA_CTCR_TRGM[29:28] bits
00471    * - PaddingAlignment:       MDMA_CTCR_PAM[27:26] bits
00472    * - PackMode:                MDMA_CTCR_PKE[25] bit
00473    * - BufferTransferLength:    MDMA_CTCR_TLEN[24:18] bits
00474    * - DestBurst:               MDMA_CTCR_DBURST[17:15] bits
00475    * - SrctBurst:               MDMA_CTCR_SBURST[14:12] bits
00476    * - DestIncSize:             MDMA_CTCR_DINCOS[11:10] bits
00477    * - SrcIncSize:              MDMA_CTCR_SINCOS[9:8] bits
00478    * - DestDataSize:            MDMA_CTCR_DSIZE[7:6] bits
00479    * - SrcDataSize:             MDMA_CTCR_SSIZE[5:4] bits
00480    * - DestIncMode:             MDMA_CTCR_DINC[3:2] bits
00481    * - SrcIncMode:              MDMA_CTCR_SINC[1:0] bits
00482    */
00483   LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \
00484                                          MDMA_InitStruct->RequestMode         | \
00485                                          MDMA_InitStruct->TriggerMode         | \
00486                                          MDMA_InitStruct->PaddingAlignment    | \
00487                                          MDMA_InitStruct->PackMode            | \
00488                                          MDMA_InitStruct->DestBurst           | \
00489                                          MDMA_InitStruct->SrctBurst           | \
00490                                          MDMA_InitStruct->DestIncSize         | \
00491                                          MDMA_InitStruct->SrcIncSize          | \
00492                                          MDMA_InitStruct->DestDataSize        | \
00493                                          MDMA_InitStruct->SrcDataSize         | \
00494                                          MDMA_InitStruct->DestIncMode         | \
00495                                          MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength);
00496
00497   /*-------------------------- MDMAx CBNDTR Configuration --------------------------
00498    * Configure the Transfer Block counters and update mode with parameter :
00499    * - BlockRepeatCount:                MDMA_CBNDTR_BRC[31:20] bits
00500    * - BlockDataLength:                 MDMA_CBNDTR_BNDT[16:0] bits
00501    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRDUM[19] bit
00502    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRSUM[18] bit
00503    */
00504   LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength);
00505
00506   LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
00507                                                    MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode);
00508
00509
00510
00511   /*-------------------------- MDMAx CSAR Configuration --------------------------
00512    * Configure the Transfer source address with parameter :
00513    * - SrcAddress:     MDMA_CSAR_SAR[31:0] bits
00514    */
00515   LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress);
00516
00517   /*-------------------------- MDMAx CDAR Configuration --------------------------
00518    * Configure the Transfer destination address with parameter :
00519    * - DstAddress:     MDMA_CDAR_DAR[31:0] bits
00520    */
00521   LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress);
00522
00523   /*-------------------------- MDMAx CBRUR Configuration --------------------------
00524    * Configure the Transfer Block repeat address update value with parameter :
00525    * - BlockRepeatDestAddrUpdateVal:    MDMA_CBRUR_DUV[31:16] bits
00526    * - BlockRepeatSrcAddrUpdateVal:     MDMA_CBRUR_SUV[15:0] bits
00527    */
00528   LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \
00529                                                MDMA_InitStruct->BlockRepeatDestAddrUpdateVal);
00530
00531   /*-------------------------- MDMAx CLAR Configuration --------------------------
00532    * Configure the Transfer linked list address with parameter :
00533    * - LinkAddress:     MDMA_CLAR_LAR[31:0] bits
00534    */
00535   LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress);
00536
00537   /*-------------------------- MDMAx CTBR Configuration --------------------------
00538    * Configure the Transfer HW trigger and bus selection with parameter :
00539    * - DestBus:     MDMA_TBR_DBUS[17] bit
00540    * - SrcBus:      MDMA_TBR_SBUS[16] bit
00541    * - HWTrigger:   MDMA_TBR_TSEL[5:0] bits
00542    */
00543   LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus);
00544
00545   LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger);
00546
00547   /*-------------------------- MDMAx CMAR Configuration --------------------------
00548    * Configure the mask address with parameter :
00549    * - MaskAddress:     MDMA_CMAR_MAR[31:0] bits
00550    */
00551   LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress);
00552
00553   /*-------------------------- MDMAx CMDR Configuration --------------------------
00554    * Configure the mask data with parameter :
00555    * - MaskData:     MDMA_CMDR_MDR[31:0] bits
00556    */
00557   LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData);
00558
00559   return (uint32_t)SUCCESS;
00560 }
00561
00562 /**
00563   * @brief  Set each @ref LL_MDMA_InitTypeDef field to default value.
00564   * @param  MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure.
00565   * @retval None
00566   */
00567 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct)
00568 {
00569   /* Set DMA_InitStruct fields to default values */
00570   MDMA_InitStruct->SrcAddress                     = 0x00000000U;
00571   MDMA_InitStruct->DstAddress                     = 0x00000000U;
00572   MDMA_InitStruct->BlockDataLength                = 0x00000000U;
00573   MDMA_InitStruct->BlockRepeatCount               = 0x00000000U;
00574   MDMA_InitStruct->WordEndianess                  = LL_MDMA_WORD_ENDIANNESS_PRESERVE;
00575   MDMA_InitStruct->HalfWordEndianess              = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE;
00576   MDMA_InitStruct->ByteEndianess                  = LL_MDMA_BYTE_ENDIANNESS_PRESERVE;
00577   MDMA_InitStruct->Priority                       = LL_MDMA_PRIORITY_LOW;
00578   MDMA_InitStruct->BufferableWriteMode            = LL_MDMA_BUFF_WRITE_DISABLE;
00579   MDMA_InitStruct->RequestMode                    = LL_MDMA_REQUEST_MODE_HW;
00580   MDMA_InitStruct->TriggerMode                    = LL_MDMA_BUFFER_TRANSFER;
00581   MDMA_InitStruct->PaddingAlignment               = LL_MDMA_DATAALIGN_RIGHT;
00582   MDMA_InitStruct->PackMode                       = LL_MDMA_PACK_DISABLE;
00583   MDMA_InitStruct->BufferTransferLength           = 0x00000000U;
00584   MDMA_InitStruct->DestBurst                      = LL_MDMA_DEST_BURST_SINGLE;
00585   MDMA_InitStruct->SrctBurst                      = LL_MDMA_SRC_BURST_SINGLE;
00586   MDMA_InitStruct->DestIncSize                    = LL_MDMA_DEST_INC_OFFSET_BYTE;
00587   MDMA_InitStruct->SrcIncSize                     = LL_MDMA_SRC_INC_OFFSET_BYTE;
00588   MDMA_InitStruct->DestDataSize                   = LL_MDMA_DEST_DATA_SIZE_BYTE;
00589   MDMA_InitStruct->SrcDataSize                    = LL_MDMA_SRC_DATA_SIZE_BYTE;
00590   MDMA_InitStruct->DestIncMode                    = LL_MDMA_DEST_FIXED;
00591   MDMA_InitStruct->SrcIncMode                     = LL_MDMA_SRC_FIXED;
00592   MDMA_InitStruct->BlockRepeatDestAddrUpdateMode  = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT;
00593   MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode   = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT;
00594   MDMA_InitStruct->BlockRepeatDestAddrUpdateVal   = 0x00000000U;
00595   MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal    = 0x00000000U;
00596   MDMA_InitStruct->LinkAddress                    = 0x00000000U;
00597   MDMA_InitStruct->DestBus                        = LL_MDMA_DEST_BUS_SYSTEM_AXI;
00598   MDMA_InitStruct->SrcBus                         = LL_MDMA_SRC_BUS_SYSTEM_AXI;
00599   MDMA_InitStruct->HWTrigger                      = LL_MDMA_REQ_DMA1_STREAM0_TC;
00600   MDMA_InitStruct->MaskAddress                    = 0x00000000U;
00601   MDMA_InitStruct->MaskData                       = 0x00000000U;
00602 }
00603
00604 /**
00605   * @brief  Initializes MDMA linked list node according to the specified
00606   *         parameters in the MDMA_InitStruct.
00607   * @param  MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains
00608   *         linked list node registers configurations.
00609   * @param  pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters.
00610   * @retval None
00611   */
00612 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
00613 {
00614
00615   /* Check the MDMA parameters from MDMA_InitStruct */
00616   assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
00617   assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
00618
00619   assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
00620   assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
00621   assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
00622   assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
00623   assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
00624   assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
00625   assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
00626   assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
00627   assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
00628   assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
00629   assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
00630   assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
00631   assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
00632   assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
00633   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
00634   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
00635   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
00636   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
00637   assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
00638   assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
00639   assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
00640
00641
00642   /*-------------------------- MDMAx CTCR Configuration --------------------------
00643    * Configure the Transfer  parameter :
00644    * - BufferableWriteMode:     MDMA_CTCR_BWM[31] bit
00645    * - RequestMode:             MDMA_CTCR_SWRM[30] bit
00646    * - TriggerMode:             MDMA_CTCR_TRGM[29:28] bits
00647    * - PaddingAlignment:       MDMA_CTCR_PAM[27:26] bits
00648    * - PackMode:                MDMA_CTCR_PKE[25] bit
00649    * - BufferTransferLength:    MDMA_CTCR_TLEN[24:18] bits
00650    * - DestBurst:               MDMA_CTCR_DBURST[17:15] bits
00651    * - SrctBurst:               MDMA_CTCR_SBURST[14:12] bits
00652    * - DestIncSize:             MDMA_CTCR_DINCOS[11:10] bits
00653    * - SrcIncSize:              MDMA_CTCR_SINCOS[9:8] bits
00654    * - DestDataSize:            MDMA_CTCR_DSIZE[7:6] bits
00655    * - SrcDataSize:             MDMA_CTCR_SSIZE[5:4] bits
00656    * - DestIncMode:             MDMA_CTCR_DINC[3:2] bits
00657    * - SrcIncMode:              MDMA_CTCR_SINC[1:0] bits
00658    */
00659   pNode->CTCR =  MDMA_InitStruct->BufferableWriteMode | \
00660                  MDMA_InitStruct->RequestMode         | \
00661                  MDMA_InitStruct->TriggerMode         | \
00662                  MDMA_InitStruct->PaddingAlignment    | \
00663                  MDMA_InitStruct->PackMode            | \
00664                  MDMA_InitStruct->DestBurst           | \
00665                  MDMA_InitStruct->SrctBurst           | \
00666                  MDMA_InitStruct->DestIncSize         | \
00667                  MDMA_InitStruct->SrcIncSize          | \
00668                  MDMA_InitStruct->DestDataSize        | \
00669                  MDMA_InitStruct->SrcDataSize         | \
00670                  MDMA_InitStruct->DestIncMode         | \
00671                  MDMA_InitStruct->SrcIncMode          | \
00672                 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
00673
00674
00675
00676   /*-------------------------- MDMAx CBNDTR Configuration --------------------------
00677    * Configure the Transfer Block counters and update mode with parameter :
00678    * - BlockRepeatCount:                MDMA_CBNDTR_BRC[31:20] bits
00679    * - BlockDataLength:                 MDMA_CBNDTR_BNDT[16:0] bits
00680    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRDUM[19] bit
00681    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRSUM[18] bit
00682    */
00683   pNode->CBNDTR =  ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \
00684                     MDMA_InitStruct->BlockRepeatDestAddrUpdateMode                                    | \
00685                     MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode                                     | \
00686                    (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk);
00687
00688
00689   /*-------------------------- MDMAx CSAR Configuration --------------------------
00690    * Configure the Transfer source address with parameter :
00691    * - SrcAddress:     MDMA_CSAR_SAR[31:0] bits
00692    */
00693   pNode->CSAR =  MDMA_InitStruct->SrcAddress;
00694
00695
00696   /*-------------------------- MDMAx CDAR Configuration --------------------------
00697    * Configure the Transfer destination address with parameter :
00698    * - DstAddress:     MDMA_CDAR_DAR[31:0] bits
00699    */
00700   pNode->CDAR =  MDMA_InitStruct->DstAddress;
00701
00702   /*-------------------------- MDMAx CBRUR Configuration --------------------------
00703    * Configure the Transfer Block repeat address update value with parameter :
00704    * - BlockRepeatDestAddrUpdateVal:    MDMA_CBRUR_DUV[31:16] bits
00705    * - BlockRepeatSrcAddrUpdateVal:     MDMA_CBRUR_SUV[15:0] bits
00706    */
00707   pNode->CBRUR =  (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk)  | \
00708                   ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ;
00709
00710   /*-------------------------- MDMAx CLAR Configuration --------------------------
00711    * Configure the Transfer linked list address with parameter :
00712    * - LinkAddress:     MDMA_CLAR_LAR[31:0] bits
00713    */
00714   pNode->CLAR = MDMA_InitStruct->LinkAddress;
00715
00716   /*-------------------------- MDMAx CTBR Configuration --------------------------
00717    * Configure the Transfer HW trigger and bus selection with parameter :
00718    * - DestBus:     MDMA_TBR_DBUS[17] bit
00719    * - SrcBus:      MDMA_TBR_SBUS[16] bit
00720    * - HWTrigger:   MDMA_TBR_TSEL[5:0] bits
00721    */
00722   pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger;
00723
00724   /*-------------------------- MDMAx CMAR Configuration --------------------------
00725    * Configure the mask address with parameter :
00726    * - MaskAddress:     MDMA_CMAR_MAR[31:0] bits
00727    */
00728   pNode->CMAR = MDMA_InitStruct->MaskAddress;
00729
00730   /*-------------------------- MDMAx CMDR Configuration --------------------------
00731    * Configure the mask data with parameter :
00732    * - MaskData:     MDMA_CMDR_MDR[31:0] bits
00733    */
00734   pNode->CMDR = MDMA_InitStruct->MaskData;
00735
00736
00737   pNode->Reserved = 0;
00738
00739 }
00740
00741 /**
00742   * @brief  Connect Linked list Nodes.
00743   * @param  pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node.
00744   * @param  pNewLinkNode Pointer to new Linked list.
00745   * @retval None
00746   */
00747 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
00748 {
00749   pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode;
00750 }
00751
00752 /**
00753   * @brief  Disconnect the next linked list node.
00754   * @param  pLinkNode Pointer to linked list node to be disconnected from the next one.
00755   * @retval None
00756   */
00757 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
00758 {
00759   pLinkNode->CLAR = 0;
00760 }
00761
00762 /**
00763   * @}
00764   */
00765
00766 /**
00767   * @}
00768   */
00769
00770 /**
00771   * @}
00772   */
00773
00774 #endif /* MDMA */
00775
00776 /**
00777   * @}
00778   */
00779
00780 #endif /* USE_FULL_LL_DRIVER */
00781
00782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_mdma.h Source File

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stm32h7xx_ll_mdma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_mdma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of MDMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_MDMA_H
00022 #define STM32H7xx_LL_MDMA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (MDMA)
00036
00037 /** @defgroup MDMA_LL MDMA
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup MDMA_LL_Private_Variables MDMA Private Variables
00044   * @{
00045   */
00046 /* Array used to get the MDMA channel register offset versus channel index LL_MDMA_CHANNEL_x */
00047 static const uint32_t LL_MDMA_CH_OFFSET_TAB[] =
00048 {
00049   (uint32_t)(MDMA_Channel0_BASE - MDMA_BASE),
00050   (uint32_t)(MDMA_Channel1_BASE - MDMA_BASE),
00051   (uint32_t)(MDMA_Channel2_BASE - MDMA_BASE),
00052   (uint32_t)(MDMA_Channel3_BASE - MDMA_BASE),
00053   (uint32_t)(MDMA_Channel4_BASE - MDMA_BASE),
00054   (uint32_t)(MDMA_Channel5_BASE - MDMA_BASE),
00055   (uint32_t)(MDMA_Channel6_BASE - MDMA_BASE),
00056   (uint32_t)(MDMA_Channel7_BASE - MDMA_BASE),
00057   (uint32_t)(MDMA_Channel8_BASE - MDMA_BASE),
00058   (uint32_t)(MDMA_Channel9_BASE - MDMA_BASE),
00059   (uint32_t)(MDMA_Channel10_BASE - MDMA_BASE),
00060   (uint32_t)(MDMA_Channel11_BASE - MDMA_BASE),
00061   (uint32_t)(MDMA_Channel12_BASE - MDMA_BASE),
00062   (uint32_t)(MDMA_Channel13_BASE - MDMA_BASE),
00063   (uint32_t)(MDMA_Channel14_BASE - MDMA_BASE),
00064   (uint32_t)(MDMA_Channel15_BASE - MDMA_BASE)
00065 };
00066
00067 /**
00068   * @}
00069   */
00070
00071 /* Private constants ---------------------------------------------------------*/
00072 /** @defgroup MDMA_LL_Private_Constants MDMA Private Constants
00073   * @{
00074   */
00075 /**
00076   * @}
00077   */
00078
00079
00080 /* Private macros ------------------------------------------------------------*/
00081 /* Exported types ------------------------------------------------------------*/
00082 #if defined(USE_FULL_LL_DRIVER)
00083 /** @defgroup MDMA_LL_ES_INIT MDMA Exported Init structure
00084   * @{
00085   */
00086 typedef struct
00087 {
00088   uint32_t SrcAddress;            /*!< Specifies the transfer source address
00089                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
00090                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceAddress() */
00091
00092   uint32_t DstAddress;            /*!< Specifies the transfer destination address
00093                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
00094                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationAddress() */
00095
00096   uint32_t RequestMode;           /*!< Specifies the request mode Hardware or Software.
00097                                        This parameter can be a value of @ref MDMA_LL_EC_REQUEST_MODE
00098                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetRequestMode() */
00099
00100   uint32_t TriggerMode;           /*!< Specifies the transfer trigger mode.
00101                                        This parameter can be a value of @ref MDMA_LL_EC_TRIGGER_MODE
00102                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetTriggerMode() */
00103
00104   uint32_t HWTrigger;             /*!< Specifies the HW transfer trigger used when RequestMode is HW.
00105                                        This parameter can be a value of @ref MDMA_LL_EC_HW_TRIGGER_SELCTION
00106                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetHWTrigger() */
00107
00108   uint32_t BlockDataLength;       /*!< Specifies the length of a block transfer in bytes
00109                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x00010000.
00110                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkDataLength() */
00111
00112   uint32_t BlockRepeatCount;      /*!< Specifies the Block Repeat Count
00113                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x00000FFF.
00114                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatCount() */
00115
00116   uint32_t BlockRepeatDestAddrUpdateMode; /*!< Specifies the block repeat destination address update mode.
00117                                                This parameter can be a value of @ref MDMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE
00118                                                This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatDestAddrUpdate() */
00119
00120   uint32_t BlockRepeatSrcAddrUpdateMode;  /*!< Specifies the block repeat source address update mode.
00121                                                This parameter can be a value of @ref MDMA_LL_EC_SRC_BLK_RPT_ADDR_UPDATE_MODE
00122                                                This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatSrcAddrUpdate() */
00123
00124   uint32_t BlockRepeatDestAddrUpdateVal;  /*!< Specifies the block repeat destination address update value.
00125                                                This parameter can be a value Between 0 to 0x0000FFFF
00126                                                This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRptDestAddrUpdateValue() */
00127
00128   uint32_t BlockRepeatSrcAddrUpdateVal;   /*!< Specifies the block repeat source address update value.
00129                                                This parameter can be a value Between 0 to 0x0000FFFF
00130                                                This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRptSrcAddrUpdateValue() */
00131
00132   uint32_t LinkAddress;                   /*!< Specifies the linked list next transfer node address.
00133                                                This parameter can be a value Between 0 to 0xFFFFFFFF
00134                                                This feature can be modified afterwards using unitary function @ref LL_MDMA_SetLinkAddress() */
00135
00136   uint32_t WordEndianess;         /*!< Specifies the Word transfer endianness
00137                                        This parameter can be a value of @ref MDMA_LL_EC_WORD_ENDIANNESS.
00138                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetWordEndianness() */
00139
00140   uint32_t HalfWordEndianess;     /*!< Specifies the Half Word transfer endianness
00141                                        This parameter can be a value of @ref MDMA_LL_EC_HALFWORD_ENDIANNESS.
00142                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetHalfWordEndianness() */
00143
00144   uint32_t ByteEndianess;         /*!< Specifies the Byte transfer endianness
00145                                        This parameter can be a value of @ref MDMA_LL_EC_BYTE_ENDIANNESS.
00146                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetByteEndianness() */
00147
00148   uint32_t Priority;              /*!< Specifies the channel priority level.
00149                                        This parameter can be a value of @ref MDMA_LL_EC_PRIORITY
00150                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetChannelPriorityLevel() */
00151
00152   uint32_t BufferableWriteMode;   /*!< Specifies the transfer Bufferable Write Mode.
00153                                        This parameter can be a value of @ref MDMA_LL_EC_BUFF_WRITE_MODE
00154                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_EnableBufferableWrMode()
00155                                        and LL_MDMA_DisableBufferableWrMode */
00156
00157
00158   uint32_t PaddingAlignment;     /*!< Specifies the transfer Padding and Alignment.
00159                                        This parameter can be a value of @ref MDMA_LL_EC_PADDING_ALIGNMENT_MODE
00160                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetPaddingAlignment() */
00161
00162   uint32_t PackMode;              /*!< Specifies the transfer Packing enabled or disabled.
00163                                        This parameter can be a value of @ref MDMA_LL_EC_PACKING_MODE
00164                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_EnablePacking()
00165                                        and LL_MDMA_DisablePacking() */
00166
00167   uint32_t BufferTransferLength;  /*!< Specifies the length of a buffer transfer in bytes
00168                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000007F.
00169                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBufferTransferLength() */
00170
00171   uint32_t DestBurst;             /*!< Specifies the destination burst size.
00172                                        This parameter can be a value of @ref MDMA_LL_EC_DEST_BURST
00173                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationBurstSize() */
00174
00175   uint32_t SrctBurst;             /*!< Specifies the source burst size.
00176                                        This parameter can be a value of @ref MDMA_LL_EC_SRC_BURST
00177                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceBurstSize() */
00178
00179   uint32_t DestIncSize;           /*!< Specifies the destination increment size.
00180                                        This parameter can be a value of @ref MDMA_LL_EC_DEST_INC_OFFSET_SIZE
00181                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationIncSize() */
00182
00183   uint32_t SrcIncSize;            /*!< Specifies the source increment size.
00184                                        This parameter can be a value of @ref MDMA_LL_EC_SRC_INC_OFFSET_SIZE
00185                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceIncSize() */
00186
00187   uint32_t DestDataSize;          /*!< Specifies the destination data size.
00188                                        This parameter can be a value of @ref MDMA_LL_EC_DEST_DATA_SIZE
00189                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationDataSize() */
00190
00191   uint32_t SrcDataSize;           /*!< Specifies the source data size.
00192                                        This parameter can be a value of @ref MDMA_LL_EC_SRC_DATA_SIZE
00193                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceDataSize() */
00194
00195   uint32_t DestIncMode;           /*!< Specifies the destination increment mode.
00196                                        This parameter can be a value of @ref MDMA_LL_EC_DEST_INC_MODE
00197                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationIncMode() */
00198
00199   uint32_t SrcIncMode;            /*!< Specifies the source increment mode.
00200                                        This parameter can be a value of @ref MDMA_LL_EC_SRC_INC_MODE
00201                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceIncMode() */
00202
00203
00204   uint32_t DestBus;               /*!< Specifies the destination transfer bus, System AXI or AHB/TCM bus.
00205                                        This parameter can be a value of @ref MDMA_LL_EC_DEST_BUS
00206                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestBusSelection() */
00207
00208   uint32_t SrcBus;                /*!< Specifies the source transfer bus, System AXI or AHB/TCM bus.
00209                                        This parameter can be a value of @ref MDMA_LL_EC_SRC_BUS
00210                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSrcBusSelection() */
00211
00212   uint32_t MaskAddress;           /*!< Specifies the address to be updated (written) with MaskData after a request is served.
00213                                        MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served
00214                                        This parameter can be a value Between 0 to 0xFFFFFFFF
00215                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetMaskAddress() */
00216
00217   uint32_t MaskData;              /*!< Specifies the value to be written to MaskAddress after a request is served.
00218                                        MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served
00219                                        This parameter can be a value Between 0 to 0xFFFFFFFF
00220                                        This feature can be modified afterwards using unitary function @ref LL_MDMA_SetMaskData() */
00221
00222 } LL_MDMA_InitTypeDef;
00223
00224 /**
00225   * @brief  LL MDMA linked list node structure definition
00226   * @note   The Linked list node allows to define a new MDMA configuration
00227   *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
00228   *         When CLAR register is configured to a non NULL value , each time a transfer ends,
00229   *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
00230   */
00231 typedef struct
00232 {
00233   __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
00234   __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
00235   __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
00236   __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
00237   __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
00238   __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
00239   __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
00240   __IO uint32_t Reserved; /*!< Reserved register*/
00241   __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
00242   __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
00243
00244 }LL_MDMA_LinkNodeTypeDef;
00245
00246 /**
00247   * @}
00248   */
00249 #endif /*USE_FULL_LL_DRIVER*/
00250 /* Exported constants --------------------------------------------------------*/
00251 /** @defgroup MDMA_LL_Exported_Constants MDMA Exported Constants
00252   * @{
00253   */
00254
00255 /** @defgroup MDMA_LL_EC_CHANNEL CHANNEL
00256   * @{
00257   */
00258 #define LL_MDMA_CHANNEL_0                   0x00000000U
00259 #define LL_MDMA_CHANNEL_1                   0x00000001U
00260 #define LL_MDMA_CHANNEL_2                   0x00000002U
00261 #define LL_MDMA_CHANNEL_3                   0x00000003U
00262 #define LL_MDMA_CHANNEL_4                   0x00000004U
00263 #define LL_MDMA_CHANNEL_5                   0x00000005U
00264 #define LL_MDMA_CHANNEL_6                   0x00000006U
00265 #define LL_MDMA_CHANNEL_7                   0x00000007U
00266 #define LL_MDMA_CHANNEL_8                   0x00000008U
00267 #define LL_MDMA_CHANNEL_9                   0x00000009U
00268 #define LL_MDMA_CHANNEL_10                  0x0000000AU
00269 #define LL_MDMA_CHANNEL_11                  0x0000000BU
00270 #define LL_MDMA_CHANNEL_12                  0x0000000CU
00271 #define LL_MDMA_CHANNEL_13                  0x0000000DU
00272 #define LL_MDMA_CHANNEL_14                  0x0000000EU
00273 #define LL_MDMA_CHANNEL_15                  0x0000000FU
00274 #define LL_MDMA_CHANNEL_ALL                 0xFFFF0000U
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup MDMA_LL_EC_WORD_ENDIANNESS Word Endianness
00280   * @{
00281   */
00282 #define LL_MDMA_WORD_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for words */
00283 #define LL_MDMA_WORD_ENDIANNESS_EXCHANGE     MDMA_CCR_WEX /*!< word order exchanged when destination data size is double word  */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup MDMA_LL_EC_HALFWORD_ENDIANNESS Half Word Endianness
00290   * @{
00291   */
00292 #define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for half words */
00293 #define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE     MDMA_CCR_HEX /*!< half word order exchanged when destination data size is word or double word  */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup MDMA_LL_EC_BYTE_ENDIANNESS Byte Endianness
00300   * @{
00301   */
00302 #define LL_MDMA_BYTE_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for bytes */
00303 #define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE     MDMA_CCR_BEX /*!< byte order exchanged when destination data size is half word , word or double word  */
00304
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup MDMA_LL_EC_PRIORITY Transfer Priority level
00310   * @{
00311   */
00312 #define LL_MDMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
00313 #define LL_MDMA_PRIORITY_MEDIUM            MDMA_CCR_PL_0             /*!< Priority level : Medium    */
00314 #define LL_MDMA_PRIORITY_HIGH              MDMA_CCR_PL_1             /*!< Priority level : High      */
00315 #define LL_MDMA_PRIORITY_VERYHIGH          MDMA_CCR_PL               /*!< Priority level : Very_High */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup MDMA_LL_EC_BUFF_WRITE_MODE Bufferable Write Mode
00321   * @{
00322   */
00323 #define LL_MDMA_BUFF_WRITE_DISABLE         0x00000000U               /*!< destination write operation is non-bufferable */
00324 #define LL_MDMA_BUFF_WRITE_ENABLE          MDMA_CTCR_BWM             /*!< destination write operation is bufferable     */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup MDMA_LL_EC_REQUEST_MODE Request Mode
00330   * @{
00331   */
00332 #define LL_MDMA_REQUEST_MODE_HW            0x00000000U               /*!< Request mode is Hardware    */
00333 #define LL_MDMA_REQUEST_MODE_SW            MDMA_CTCR_SWRM            /*!< Request mode is Software    */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup MDMA_LL_EC_TRIGGER_MODE Trigger Mode
00339   * @{
00340   */
00341 #define LL_MDMA_BUFFER_TRANSFER          0x00000000U               /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
00342 #define LL_MDMA_BLOCK_TRANSFER           MDMA_CTCR_TRGM_0          /*!< Each MDMA request (SW or HW) triggers a block transfer */
00343 #define LL_MDMA_REPEAT_BLOCK_TRANSFER    MDMA_CTCR_TRGM_1          /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
00344 #define LL_MDMA_FULL_TRANSFER            MDMA_CTCR_TRGM            /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup MDMA_LL_EC_PADDING_ALIGNMENT_MODE Padding Alignment Mode
00350   * @{
00351   */
00352 #define LL_MDMA_DATAALIGN_RIGHT          0x00000000U              /*!< Right Aligned, padded w/ 0s (default) */
00353 #define LL_MDMA_DATAALIGN_RIGHT_SIGNED   MDMA_CTCR_PAM_0          /*!< Right Aligned, Sign extended ,
00354                                                                        Note : this mode is allowed only if the Source data size smaller than Destination data size  */
00355 #define LL_MDMA_DATAALIGN_LEFT           MDMA_CTCR_PAM_1          /*!< Left Aligned (padded with 0s) */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup MDMA_LL_EC_PACKING_MODE Transfer Packing
00361   * @{
00362   */
00363 #define LL_MDMA_PACK_DISABLE          0x00000000U              /*!< Packing disabled */
00364 #define LL_MDMA_PACK_ENABLE           MDMA_CTCR_PKE            /*!< Packing enabled  */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup MDMA_LL_EC_DEST_BURST Transfer Destination Burst
00370   * @{
00371   */
00372 #define LL_MDMA_DEST_BURST_SINGLE        0x00000000U                               /*!< Single transfer */
00373 #define LL_MDMA_DEST_BURST_2BEATS        MDMA_CTCR_DBURST_0                        /*!< Burst 2 beats   */
00374 #define LL_MDMA_DEST_BURST_4BEATS        MDMA_CTCR_DBURST_1                        /*!< Burst 4 beats   */
00375 #define LL_MDMA_DEST_BURST_8BEATS       (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
00376 #define LL_MDMA_DEST_BURST_16BEATS       MDMA_CTCR_DBURST_2                        /*!< Burst 16 beats  */
00377 #define LL_MDMA_DEST_BURST_32BEATS      (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
00378 #define LL_MDMA_DEST_BURST_64BEATS      (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
00379 #define LL_MDMA_DEST_BURST_128BEATS     (MDMA_CTCR_DBURST)                         /*!< Burst 128 beats */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup MDMA_LL_EC_SRC_BURST Transfer Source Burst
00385   * @{
00386   */
00387 #define LL_MDMA_SRC_BURST_SINGLE        0x00000000U                                /*!< Single transfer */
00388 #define LL_MDMA_SRC_BURST_2BEATS        MDMA_CTCR_SBURST_0                         /*!< Burst 2 beats   */
00389 #define LL_MDMA_SRC_BURST_4BEATS        MDMA_CTCR_SBURST_1                         /*!< Burst 4 beats   */
00390 #define LL_MDMA_SRC_BURST_8BEATS       (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)   /*!< Burst 8 beats   */
00391 #define LL_MDMA_SRC_BURST_16BEATS       MDMA_CTCR_SBURST_2                         /*!< Burst 16 beats  */
00392 #define LL_MDMA_SRC_BURST_32BEATS      (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)   /*!< Burst 32 beats  */
00393 #define LL_MDMA_SRC_BURST_64BEATS      (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)   /*!< Burst 64 beats  */
00394 #define LL_MDMA_SRC_BURST_128BEATS      MDMA_CTCR_SBURST                           /*!< Burst 128 beats */
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup MDMA_LL_EC_DEST_INC_OFFSET_SIZE Destination Increment Offset Size
00400   * @{
00401   */
00402 #define LL_MDMA_DEST_INC_OFFSET_BYTE        0x00000000U                           /*!< offset is Byte (8-bit)         */
00403 #define LL_MDMA_DEST_INC_OFFSET_HALFWORD    MDMA_CTCR_DINCOS_0                    /*!< offset is Half Word (16-bit)   */
00404 #define LL_MDMA_DEST_INC_OFFSET_WORD        MDMA_CTCR_DINCOS_1                    /*!< offset is Word (32-bit)        */
00405 #define LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD  MDMA_CTCR_DINCOS                      /*!< offset is Double Word (64-bit) */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup MDMA_LL_EC_SRC_INC_OFFSET_SIZE Source Increment Offset Size
00411   * @{
00412   */
00413 #define LL_MDMA_SRC_INC_OFFSET_BYTE        0x00000000U                           /*!< offset is Byte (8-bit)         */
00414 #define LL_MDMA_SRC_INC_OFFSET_HALFWORD    MDMA_CTCR_SINCOS_0                    /*!< offset is Half Word (16-bit)   */
00415 #define LL_MDMA_SRC_INC_OFFSET_WORD        MDMA_CTCR_SINCOS_1                    /*!< offset is Word (32-bit)        */
00416 #define LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD  MDMA_CTCR_SINCOS                      /*!< offset is Double Word (64-bit) */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup MDMA_LL_EC_DEST_DATA_SIZE Destination Data Size
00422   * @{
00423   */
00424 #define LL_MDMA_DEST_DATA_SIZE_BYTE       0x00000000U                            /*!< Destination data size is Byte        */
00425 #define LL_MDMA_DEST_DATA_SIZE_HALFWORD   MDMA_CTCR_DSIZE_0                      /*!< Destination data size is half word   */
00426 #define LL_MDMA_DEST_DATA_SIZE_WORD       MDMA_CTCR_DSIZE_1                      /*!< Destination data size is word        */
00427 #define LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE                        /*!< Destination data size is double word */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup MDMA_LL_EC_SRC_DATA_SIZE Source Data Size
00433   * @{
00434   */
00435 #define LL_MDMA_SRC_DATA_SIZE_BYTE       0x00000000U                            /*!< Source data size is Byte        */
00436 #define LL_MDMA_SRC_DATA_SIZE_HALFWORD   MDMA_CTCR_SSIZE_0                      /*!< Source data size is half word   */
00437 #define LL_MDMA_SRC_DATA_SIZE_WORD       MDMA_CTCR_SSIZE_1                      /*!< Source data size is word        */
00438 #define LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE                        /*!< Source data size is double word */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup MDMA_LL_EC_DEST_INC_MODE Destination Increment Mode
00444   * @{
00445   */
00446 #define LL_MDMA_DEST_FIXED               0x00000000U                            /*!< Destination address pointer is fixed */
00447 #define LL_MDMA_DEST_INCREMENT           MDMA_CTCR_DINC_1                       /*!< Destination address pointer is incremented after each data transfer */
00448 #define LL_MDMA_DEST_DECREMENT           MDMA_CTCR_DINC                         /*!< Destination address pointer is decremented after each data transfer */
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup MDMA_LL_EC_SRC_INC_MODE Source Increment Mode
00454   * @{
00455   */
00456 #define LL_MDMA_SRC_FIXED                0x00000000U                            /*!< Destination address pointer is fixed */
00457 #define LL_MDMA_SRC_INCREMENT            MDMA_CTCR_SINC_1                       /*!< Destination address pointer is incremented after each data transfer */
00458 #define LL_MDMA_SRC_DECREMENT            MDMA_CTCR_SINC                         /*!< Destination address pointer is decremented after each data transfer */
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup MDMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination address Update Mode
00464   * @{
00465   */
00466 #define LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT   0x00000000U                       /*!< Destination address pointer is incremented after each block transfer by Destination Update Value */
00467 #define LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT   MDMA_CBNDTR_BRDUM                 /*!< Destination address pointer is decremented after each block transfer by Destination Update Value */
00468 /**
00469   * @}
00470   */
00471
00472 /** @defgroup MDMA_LL_EC_SRC_BLK_RPT_ADDR_UPDATE_MODE Source Block Repeat address Update Mode
00473   * @{
00474   */
00475 #define LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT   0x00000000U                        /*!< Source address pointer is incremented after each block transfer by Source Update Value */
00476 #define LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT   MDMA_CBNDTR_BRSUM                  /*!< Source address pointer is decremented after each block transfer by Source Update Value */
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup MDMA_LL_EC_DEST_BUS Destination BUS Selection
00482   * @{
00483   */
00484 #define  LL_MDMA_DEST_BUS_SYSTEM_AXI    0x00000000U                             /*!< System/AXI bus is used as destination */
00485 #define  LL_MDMA_DEST_BUS_AHB_TCM       MDMA_CTBR_DBUS                          /*!< AHB bus/TCM is used as destination    */
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup MDMA_LL_EC_SRC_BUS Source BUS Selection
00491   * @{
00492   */
00493 #define LL_MDMA_SRC_BUS_SYSTEM_AXI     0x00000000U                             /*!< System/AXI bus is used as source */
00494 #define LL_MDMA_SRC_BUS_AHB_TCM        MDMA_CTBR_SBUS                          /*!< AHB bus/TCM is used as source    */
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup MDMA_LL_EC_HW_TRIGGER_SELCTION HW Trigger Selection
00500   * @{
00501   */
00502 #define LL_MDMA_REQ_DMA1_STREAM0_TC          0x00000000U    /*!< MDMA HW Trigger (request) is DMA1 Stream 0 Transfer Complete Flag   */
00503 #define LL_MDMA_REQ_DMA1_STREAM1_TC          0x00000001U    /*!< MDMA HW Trigger (request) is DMA1 Stream 1 Transfer Complete Flag   */
00504 #define LL_MDMA_REQ_DMA1_STREAM2_TC          0x00000002U    /*!< MDMA HW Trigger (request) is DMA1 Stream 2 Transfer Complete Flag   */
00505 #define LL_MDMA_REQ_DMA1_STREAM3_TC          0x00000003U    /*!< MDMA HW Trigger (request) is DMA1 Stream 3 Transfer Complete Flag   */
00506 #define LL_MDMA_REQ_DMA1_STREAM4_TC          0x00000004U    /*!< MDMA HW Trigger (request) is DMA1 Stream 4 Transfer Complete Flag   */
00507 #define LL_MDMA_REQ_DMA1_STREAM5_TC          0x00000005U    /*!< MDMA HW Trigger (request) is DMA1 Stream 5 Transfer Complete Flag   */
00508 #define LL_MDMA_REQ_DMA1_STREAM6_TC          0x00000006U    /*!< MDMA HW Trigger (request) is DMA1 Stream 6 Transfer Complete Flag   */
00509 #define LL_MDMA_REQ_DMA1_STREAM7_TC          0x00000007U    /*!< MDMA HW Trigger (request) is DMA1 Stream 7 Transfer Complete Flag   */
00510 #define LL_MDMA_REQ_DMA2_STREAM0_TC          0x00000008U    /*!< MDMA HW Trigger (request) is DMA2 Stream 0 Transfer Complete Flag   */
00511 #define LL_MDMA_REQ_DMA2_STREAM1_TC          0x00000009U    /*!< MDMA HW Trigger (request) is DMA2 Stream 1 Transfer Complete Flag   */
00512 #define LL_MDMA_REQ_DMA2_STREAM2_TC          0x0000000AU    /*!< MDMA HW Trigger (request) is DMA2 Stream 2 Transfer Complete Flag   */
00513 #define LL_MDMA_REQ_DMA2_STREAM3_TC          0x0000000BU    /*!< MDMA HW Trigger (request) is DMA2 Stream 3 Transfer Complete Flag   */
00514 #define LL_MDMA_REQ_DMA2_STREAM4_TC          0x0000000CU    /*!< MDMA HW Trigger (request) is DMA2 Stream 4 Transfer Complete Flag   */
00515 #define LL_MDMA_REQ_DMA2_STREAM5_TC          0x0000000DU    /*!< MDMA HW Trigger (request) is DMA2 Stream 5 Transfer Complete Flag   */
00516 #define LL_MDMA_REQ_DMA2_STREAM6_TC          0x0000000EU    /*!< MDMA HW Trigger (request) is DMA2 Stream 6 Transfer Complete Flag   */
00517 #define LL_MDMA_REQ_DMA2_STREAM7_TC          0x0000000FU    /*!< MDMA HW Trigger (request) is DMA2 Stream 7 Transfer Complete Flag   */
00518 #if defined (LTDC)
00519 #define LL_MDMA_REQ_LTDC_LINE_IT             0x00000010U    /*!< MDMA HW Trigger (request) is LTDC Line interrupt Flag               */
00520 #endif /* LTDC */
00521 #if defined (JPEG)
00522 #define LL_MDMA_REQ_JPEG_INFIFO_TH           0x00000011U    /*!< MDMA HW Trigger (request) is JPEG Input FIFO threshold Flag         */
00523 #define LL_MDMA_REQ_JPEG_INFIFO_NF           0x00000012U    /*!< MDMA HW Trigger (request) is JPEG Input FIFO not full Flag          */
00524 #define LL_MDMA_REQ_JPEG_OUTFIFO_TH          0x00000013U    /*!< MDMA HW Trigger (request) is JPEG Output FIFO threshold Flag        */
00525 #define LL_MDMA_REQ_JPEG_OUTFIFO_NE          0x00000014U    /*!< MDMA HW Trigger (request) is JPEG Output FIFO not empty Flag        */
00526 #define LL_MDMA_REQ_JPEG_END_CONVERSION      0x00000015U    /*!< MDMA HW Trigger (request) is JPEG End of conversion Flag            */
00527 #endif /* JPEG */
00528 #if defined (QUADSPI)
00529 #define LL_MDMA_REQ_QUADSPI_FIFO_TH          0x00000016U    /*!< MDMA HW Trigger (request) is QSPI FIFO threshold Flag               */
00530 #define LL_MDMA_REQ_QUADSPI_TC               0x00000017U    /*!< MDMA HW Trigger (request) is QSPI Transfer complete Flag            */
00531 #endif /* QUADSPI */
00532 #if defined (OCTOSPI1)
00533 #define LL_MDMA_REQ_OCTOSPI1_FIFO_TH         0x00000016U    /*!< MDMA HW Trigger (request) is OCTOSPI1 FIFO threshold Flag           */
00534 #define LL_MDMA_REQ_OCTOSPI1_TC              0x00000017U    /*!< MDMA HW Trigger (request) is OCTOSPI1 Transfer complete Flag        */
00535 #endif /* OCTOSPI1 */
00536 #define LL_MDMA_REQ_DMA2D_CLUT_TC            0x00000018U    /*!< MDMA HW Trigger (request) is DMA2D CLUT Transfer Complete Flag      */
00537 #define LL_MDMA_REQ_DMA2D_TC                 0x00000019U    /*!< MDMA HW Trigger (request) is DMA2D Transfer Complete Flag           */
00538 #define LL_MDMA_REQ_DMA2D_TW                 0x0000001AU    /*!< MDMA HW Trigger (request) is DMA2D Transfer Watermark Flag          */
00539 #if defined (DSI)
00540 #define LL_MDMA_REQ_DSI_TEARING_EFFECT       0x0000001BU    /*!< MDMA HW Trigger (request) is DSI Tearing Effect Flag                */
00541 #define LL_MDMA_REQ_DSI_END_REFRESH          0x0000001CU    /*!< MDMA HW Trigger (request) is DSI End of refresh  Flag               */
00542 #endif /* DSI */
00543 #define LL_MDMA_REQ_SDMMC1_END_DATA          0x0000001DU    /*!< MDMA HW Trigger (request) is SDMMC1 End of Data Flag                */
00544 #define LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER     0x0000001EU    /*!< MDMA HW Trigger (request) is SDMMC1 Internal DMA buffer End Flag : This trigger is available starting from STM32H7 Rev.B devices */
00545 #define LL_MDMA_REQ_SDMMC1_COMMAND_END       0x0000001FU    /*!< MDMA HW Trigger (request) is SDMMC1 Command End Flag : This trigger is available starting from STM32H7 Rev.B devices */
00546 #if defined (OCTOSPI2)
00547 #define LL_MDMA_REQ_OCTOSPI2_FIFO_TH         0x00000020U    /*!< MDMA HW Trigger (request) is OCTOSPI2 FIFO threshold Flag           */
00548 #define LL_MDMA_REQ_OCTOSPI2_TC              0x00000021U    /*!< MDMA HW Trigger (request) is OCTOSPI2 Transfer complete Flag        */
00549 #endif /* OCTOSPI2 */
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup MDMA_LL_EC_XFER_ERROR_DIRECTION Transfer Error Direction
00555   * @{
00556   */
00557 #define LL_MDMA_READ_ERROR                       0x00000000U                /*!< Last transfer error on the channel was a related to a read access    */
00558 #define LL_MDMA_WRITE_ERROR                      MDMA_CESR_TED              /*!< Last transfer error on the channel was a related to a write access   */
00559 /**
00560   * @}
00561   */
00562
00563 /**
00564   * @}
00565   */
00566
00567 /* Exported macro ------------------------------------------------------------*/
00568 /** @defgroup MDMA_LL_Exported_Macros MDMA Exported Macros
00569   * @{
00570   */
00571
00572 /** @defgroup MDMA_LL_EM_WRITE_READ Common Write and read registers macros
00573   * @{
00574   */
00575 /**
00576   * @brief  Write a value in MDMA register
00577   * @param  __INSTANCE__ MDMA Instance
00578   * @param  __REG__ Register to be written
00579   * @param  __VALUE__ Value to be written in the register
00580   * @retval None
00581   */
00582 #define LL_MDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00583
00584 /**
00585   * @brief  Read a value in MDMA register
00586   * @param  __INSTANCE__ MDMA Instance
00587   * @param  __REG__ Register to be read
00588   * @retval Register value
00589   */
00590 #define LL_MDMA_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup MDMA_LL_EM_CONVERT_DMAxCHANNELy Convert MDMAxChannely
00596   * @{
00597   */
00598 /**
00599   * @brief  Convert MDMAx_Channely into MDMAx
00600   * @param  __CHANNEL_INSTANCE__ MDMAx_Channely
00601   * @retval MDMAx
00602   */
00603 #define LL_MDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (MDMA)
00604
00605 /**
00606   * @brief  Convert MDMAx_Channely into LL_MDMA_CHANNEL_y
00607   * @param  __CHANNEL_INSTANCE__ MDMAx_Channely
00608   * @retval LL_MDMA_CHANNEL_y
00609   */
00610 #define LL_MDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00611 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel0 )) ? LL_MDMA_CHANNEL_0  : \
00612  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel1 )) ? LL_MDMA_CHANNEL_1  : \
00613  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel2 )) ? LL_MDMA_CHANNEL_2  : \
00614  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel3 )) ? LL_MDMA_CHANNEL_3  : \
00615  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel4 )) ? LL_MDMA_CHANNEL_4  : \
00616  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel5 )) ? LL_MDMA_CHANNEL_5  : \
00617  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel6 )) ? LL_MDMA_CHANNEL_6  : \
00618  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel7 )) ? LL_MDMA_CHANNEL_7  : \
00619  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel8 )) ? LL_MDMA_CHANNEL_8  : \
00620  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel9 )) ? LL_MDMA_CHANNEL_9  : \
00621  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel10)) ? LL_MDMA_CHANNEL_10 : \
00622  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel11)) ? LL_MDMA_CHANNEL_11 : \
00623  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel12)) ? LL_MDMA_CHANNEL_12 : \
00624  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel13)) ? LL_MDMA_CHANNEL_13 : \
00625  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel14)) ? LL_MDMA_CHANNEL_14 : \
00626  LL_MDMA_CHANNEL_15)
00627
00628 /**
00629   * @brief  Convert MDMA Instance MDMAx and LL_MDMA_CHANNEL_y into MDMAx_Channely
00630   * @param  __MDMA_INSTANCE__ MDMAx
00631   * @param  __CHANNEL__ LL_MDMA_CHANNEL_y
00632   * @retval MDMAx_Channely
00633   */
00634 #define LL_MDMA_GET_CHANNEL_INSTANCE(__MDMA_INSTANCE__, __CHANNEL__)   \
00635 (((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_0 )) ? MDMA_Channel0  : \
00636  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_1 )) ? MDMA_Channel1  : \
00637  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_2 )) ? MDMA_Channel2  : \
00638  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_3 )) ? MDMA_Channel3  : \
00639  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_4 )) ? MDMA_Channel4  : \
00640  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_5 )) ? MDMA_Channel5  : \
00641  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_6 )) ? MDMA_Channel6  : \
00642  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_7 )) ? MDMA_Channel7  : \
00643  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_8 )) ? MDMA_Channel8  : \
00644  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_9 )) ? MDMA_Channel9  : \
00645  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_10)) ? MDMA_Channel10 : \
00646  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_11)) ? MDMA_Channel11 : \
00647  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_12)) ? MDMA_Channel12 : \
00648  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_13)) ? MDMA_Channel13 : \
00649  ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_14)) ? MDMA_Channel14 : \
00650  MDMA_Channel15)
00651
00652 /**
00653   * @}
00654   */
00655
00656 /**
00657   * @}
00658   */
00659
00660
00661 /* Exported functions --------------------------------------------------------*/
00662  /** @defgroup MDMA_LL_Exported_Functions MDMA Exported Functions
00663   * @{
00664   */
00665
00666 /** @defgroup MDMA_LL_EF_Configuration Configuration
00667   * @{
00668   */
00669 /**
00670   * @brief Enable MDMA channel.
00671   * @rmtoll CCR          EN            LL_MDMA_EnableChannel
00672   * @param  MDMAx MDMAx Instance
00673   * @param  Channel This parameter can be one of the following values:
00674   *         @arg @ref LL_MDMA_CHANNEL_0
00675   *         @arg @ref LL_MDMA_CHANNEL_1
00676   *         @arg @ref LL_MDMA_CHANNEL_2
00677   *         @arg @ref LL_MDMA_CHANNEL_3
00678   *         @arg @ref LL_MDMA_CHANNEL_4
00679   *         @arg @ref LL_MDMA_CHANNEL_5
00680   *         @arg @ref LL_MDMA_CHANNEL_6
00681   *         @arg @ref LL_MDMA_CHANNEL_7
00682   *         @arg @ref LL_MDMA_CHANNEL_8
00683   *         @arg @ref LL_MDMA_CHANNEL_9
00684   *         @arg @ref LL_MDMA_CHANNEL_10
00685   *         @arg @ref LL_MDMA_CHANNEL_11
00686   *         @arg @ref LL_MDMA_CHANNEL_12
00687   *         @arg @ref LL_MDMA_CHANNEL_13
00688   *         @arg @ref LL_MDMA_CHANNEL_14
00689   *         @arg @ref LL_MDMA_CHANNEL_15
00690   * @retval None
00691   */
00692 __STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
00693 {
00694   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00695
00696   SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
00697 }
00698
00699 /**
00700   * @brief Disable MDMA channel.
00701   * @rmtoll CCR          EN            LL_MDMA_DisableChannel
00702   * @param  MDMAx MDMAx Instance
00703   * @param  Channel This parameter can be one of the following values:
00704   *         @arg @ref LL_MDMA_CHANNEL_0
00705   *         @arg @ref LL_MDMA_CHANNEL_1
00706   *         @arg @ref LL_MDMA_CHANNEL_2
00707   *         @arg @ref LL_MDMA_CHANNEL_3
00708   *         @arg @ref LL_MDMA_CHANNEL_4
00709   *         @arg @ref LL_MDMA_CHANNEL_5
00710   *         @arg @ref LL_MDMA_CHANNEL_6
00711   *         @arg @ref LL_MDMA_CHANNEL_7
00712   *         @arg @ref LL_MDMA_CHANNEL_8
00713   *         @arg @ref LL_MDMA_CHANNEL_9
00714   *         @arg @ref LL_MDMA_CHANNEL_10
00715   *         @arg @ref LL_MDMA_CHANNEL_11
00716   *         @arg @ref LL_MDMA_CHANNEL_12
00717   *         @arg @ref LL_MDMA_CHANNEL_13
00718   *         @arg @ref LL_MDMA_CHANNEL_14
00719   *         @arg @ref LL_MDMA_CHANNEL_15
00720   * @retval None
00721   */
00722 __STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
00723 {
00724   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00725
00726   CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
00727 }
00728
00729 /**
00730   * @brief Check if MDMA channel is enabled or disabled.
00731   * @rmtoll CCR          EN            LL_MDMA_IsEnabledChannel
00732   * @param  MDMAx MDMAx Instance
00733   * @param  Channel This parameter can be one of the following values:
00734   *         @arg @ref LL_MDMA_CHANNEL_0
00735   *         @arg @ref LL_MDMA_CHANNEL_1
00736   *         @arg @ref LL_MDMA_CHANNEL_2
00737   *         @arg @ref LL_MDMA_CHANNEL_3
00738   *         @arg @ref LL_MDMA_CHANNEL_4
00739   *         @arg @ref LL_MDMA_CHANNEL_5
00740   *         @arg @ref LL_MDMA_CHANNEL_6
00741   *         @arg @ref LL_MDMA_CHANNEL_7
00742   *         @arg @ref LL_MDMA_CHANNEL_8
00743   *         @arg @ref LL_MDMA_CHANNEL_9
00744   *         @arg @ref LL_MDMA_CHANNEL_10
00745   *         @arg @ref LL_MDMA_CHANNEL_11
00746   *         @arg @ref LL_MDMA_CHANNEL_12
00747   *         @arg @ref LL_MDMA_CHANNEL_13
00748   *         @arg @ref LL_MDMA_CHANNEL_14
00749   *         @arg @ref LL_MDMA_CHANNEL_15
00750   * @retval State of bit (1 or 0).
00751   */
00752 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
00753 {
00754   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00755
00756   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN) == (MDMA_CCR_EN)) ? 1UL : 0UL);
00757 }
00758
00759 /**
00760   * @brief Generate a SW transfer request on the MDMA channel.
00761   * @rmtoll CCR          SWRQ            LL_MDMA_GenerateSWRequest
00762   * @param  MDMAx MDMAx Instance
00763   * @param  Channel This parameter can be one of the following values:
00764   *         @arg @ref LL_MDMA_CHANNEL_0
00765   *         @arg @ref LL_MDMA_CHANNEL_1
00766   *         @arg @ref LL_MDMA_CHANNEL_2
00767   *         @arg @ref LL_MDMA_CHANNEL_3
00768   *         @arg @ref LL_MDMA_CHANNEL_4
00769   *         @arg @ref LL_MDMA_CHANNEL_5
00770   *         @arg @ref LL_MDMA_CHANNEL_6
00771   *         @arg @ref LL_MDMA_CHANNEL_7
00772   *         @arg @ref LL_MDMA_CHANNEL_8
00773   *         @arg @ref LL_MDMA_CHANNEL_9
00774   *         @arg @ref LL_MDMA_CHANNEL_10
00775   *         @arg @ref LL_MDMA_CHANNEL_11
00776   *         @arg @ref LL_MDMA_CHANNEL_12
00777   *         @arg @ref LL_MDMA_CHANNEL_13
00778   *         @arg @ref LL_MDMA_CHANNEL_14
00779   *         @arg @ref LL_MDMA_CHANNEL_15
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel)
00783 {
00784   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00785
00786   SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_SWRQ);
00787 }
00788
00789 /**
00790   * @brief Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.
00791   * @rmtoll CCR          WEX            LL_MDMA_ConfigXferEndianness\n
00792   * @rmtoll CCR          HEX            LL_MDMA_ConfigXferEndianness\n
00793   * @rmtoll CCR          BEX            LL_MDMA_ConfigXferEndianness
00794   * @param  MDMAx MDMAx Instance
00795   * @param  Channel This parameter can be one of the following values:
00796   *         @arg @ref LL_MDMA_CHANNEL_0
00797   *         @arg @ref LL_MDMA_CHANNEL_1
00798   *         @arg @ref LL_MDMA_CHANNEL_2
00799   *         @arg @ref LL_MDMA_CHANNEL_3
00800   *         @arg @ref LL_MDMA_CHANNEL_4
00801   *         @arg @ref LL_MDMA_CHANNEL_5
00802   *         @arg @ref LL_MDMA_CHANNEL_6
00803   *         @arg @ref LL_MDMA_CHANNEL_7
00804   *         @arg @ref LL_MDMA_CHANNEL_8
00805   *         @arg @ref LL_MDMA_CHANNEL_9
00806   *         @arg @ref LL_MDMA_CHANNEL_10
00807   *         @arg @ref LL_MDMA_CHANNEL_11
00808   *         @arg @ref LL_MDMA_CHANNEL_12
00809   *         @arg @ref LL_MDMA_CHANNEL_13
00810   *         @arg @ref LL_MDMA_CHANNEL_14
00811   *         @arg @ref LL_MDMA_CHANNEL_15
00812   * @param  Configuration This parameter must be a combination of all the following values:
00813   *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE or @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE
00814   *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE or @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
00815   *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
00819 {
00820   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00821
00822   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,
00823              MDMA_CCR_WEX | MDMA_CCR_HEX | MDMA_CCR_BEX, Configuration);
00824 }
00825
00826 /**
00827   * @brief Set Words Endianess.
00828   * @rmtoll CCR          WEX            LL_MDMA_SetWordEndianness
00829   * @param  MDMAx MDMAx Instance
00830   * @param  Channel This parameter can be one of the following values:
00831   *         @arg @ref LL_MDMA_CHANNEL_0
00832   *         @arg @ref LL_MDMA_CHANNEL_1
00833   *         @arg @ref LL_MDMA_CHANNEL_2
00834   *         @arg @ref LL_MDMA_CHANNEL_3
00835   *         @arg @ref LL_MDMA_CHANNEL_4
00836   *         @arg @ref LL_MDMA_CHANNEL_5
00837   *         @arg @ref LL_MDMA_CHANNEL_6
00838   *         @arg @ref LL_MDMA_CHANNEL_7
00839   *         @arg @ref LL_MDMA_CHANNEL_8
00840   *         @arg @ref LL_MDMA_CHANNEL_9
00841   *         @arg @ref LL_MDMA_CHANNEL_10
00842   *         @arg @ref LL_MDMA_CHANNEL_11
00843   *         @arg @ref LL_MDMA_CHANNEL_12
00844   *         @arg @ref LL_MDMA_CHANNEL_13
00845   *         @arg @ref LL_MDMA_CHANNEL_14
00846   *         @arg @ref LL_MDMA_CHANNEL_15
00847   * @param  Endianness This parameter can be one of the following values:
00848   *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE
00849   *         @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE
00850   * @retval None
00851   */
00852 __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
00853 {
00854   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00855
00856   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX, Endianness);
00857 }
00858
00859 /**
00860   * @brief Get Words Endianess.
00861   * @rmtoll CCR          WEX            LL_MDMA_GetWordEndianness
00862   * @param  MDMAx MDMAx Instance
00863   * @param  Channel This parameter can be one of the following values:
00864   *         @arg @ref LL_MDMA_CHANNEL_0
00865   *         @arg @ref LL_MDMA_CHANNEL_1
00866   *         @arg @ref LL_MDMA_CHANNEL_2
00867   *         @arg @ref LL_MDMA_CHANNEL_3
00868   *         @arg @ref LL_MDMA_CHANNEL_4
00869   *         @arg @ref LL_MDMA_CHANNEL_5
00870   *         @arg @ref LL_MDMA_CHANNEL_6
00871   *         @arg @ref LL_MDMA_CHANNEL_7
00872   *         @arg @ref LL_MDMA_CHANNEL_8
00873   *         @arg @ref LL_MDMA_CHANNEL_9
00874   *         @arg @ref LL_MDMA_CHANNEL_10
00875   *         @arg @ref LL_MDMA_CHANNEL_11
00876   *         @arg @ref LL_MDMA_CHANNEL_12
00877   *         @arg @ref LL_MDMA_CHANNEL_13
00878   *         @arg @ref LL_MDMA_CHANNEL_14
00879   *         @arg @ref LL_MDMA_CHANNEL_15
00880   * @retval Returned value can be one of the following values:
00881   *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE
00882   *         @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE
00883   * @retval None
00884   */
00885 __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
00886 {
00887   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00888
00889   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX));
00890 }
00891
00892 /**
00893   * @brief Set Half Words Endianess.
00894   * @rmtoll CCR          HEX            LL_MDMA_SetHalfWordEndianness
00895   * @param  MDMAx MDMAx Instance
00896   * @param  Channel This parameter can be one of the following values:
00897   *         @arg @ref LL_MDMA_CHANNEL_0
00898   *         @arg @ref LL_MDMA_CHANNEL_1
00899   *         @arg @ref LL_MDMA_CHANNEL_2
00900   *         @arg @ref LL_MDMA_CHANNEL_3
00901   *         @arg @ref LL_MDMA_CHANNEL_4
00902   *         @arg @ref LL_MDMA_CHANNEL_5
00903   *         @arg @ref LL_MDMA_CHANNEL_6
00904   *         @arg @ref LL_MDMA_CHANNEL_7
00905   *         @arg @ref LL_MDMA_CHANNEL_8
00906   *         @arg @ref LL_MDMA_CHANNEL_9
00907   *         @arg @ref LL_MDMA_CHANNEL_10
00908   *         @arg @ref LL_MDMA_CHANNEL_11
00909   *         @arg @ref LL_MDMA_CHANNEL_12
00910   *         @arg @ref LL_MDMA_CHANNEL_13
00911   *         @arg @ref LL_MDMA_CHANNEL_14
00912   *         @arg @ref LL_MDMA_CHANNEL_15
00913   * @param  Endianness This parameter can be one of the following values:
00914   *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE
00915   *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
00916   * @retval None
00917   */
00918 __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
00919 {
00920   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00921
00922   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX, Endianness);
00923 }
00924
00925 /**
00926   * @brief Get Half Words Endianess.
00927   * @rmtoll CCR          HEX            LL_MDMA_GetHalfWordEndianness
00928   * @param  MDMAx MDMAx Instance
00929   * @param  Channel This parameter can be one of the following values:
00930   *         @arg @ref LL_MDMA_CHANNEL_0
00931   *         @arg @ref LL_MDMA_CHANNEL_1
00932   *         @arg @ref LL_MDMA_CHANNEL_2
00933   *         @arg @ref LL_MDMA_CHANNEL_3
00934   *         @arg @ref LL_MDMA_CHANNEL_4
00935   *         @arg @ref LL_MDMA_CHANNEL_5
00936   *         @arg @ref LL_MDMA_CHANNEL_6
00937   *         @arg @ref LL_MDMA_CHANNEL_7
00938   *         @arg @ref LL_MDMA_CHANNEL_8
00939   *         @arg @ref LL_MDMA_CHANNEL_9
00940   *         @arg @ref LL_MDMA_CHANNEL_10
00941   *         @arg @ref LL_MDMA_CHANNEL_11
00942   *         @arg @ref LL_MDMA_CHANNEL_12
00943   *         @arg @ref LL_MDMA_CHANNEL_13
00944   *         @arg @ref LL_MDMA_CHANNEL_14
00945   *         @arg @ref LL_MDMA_CHANNEL_15
00946   * @retval Returned value can be one of the following values:
00947   *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE
00948   *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE
00949   * @retval None
00950   */
00951 __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
00952 {
00953   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00954
00955   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX));
00956 }
00957
00958 /**
00959   * @brief Set Bytes Endianess.
00960   * @rmtoll CCR          BEX            LL_MDMA_SetByteEndianness
00961   * @param  MDMAx MDMAx Instance
00962   * @param  Channel This parameter can be one of the following values:
00963   *         @arg @ref LL_MDMA_CHANNEL_0
00964   *         @arg @ref LL_MDMA_CHANNEL_1
00965   *         @arg @ref LL_MDMA_CHANNEL_2
00966   *         @arg @ref LL_MDMA_CHANNEL_3
00967   *         @arg @ref LL_MDMA_CHANNEL_4
00968   *         @arg @ref LL_MDMA_CHANNEL_5
00969   *         @arg @ref LL_MDMA_CHANNEL_6
00970   *         @arg @ref LL_MDMA_CHANNEL_7
00971   *         @arg @ref LL_MDMA_CHANNEL_8
00972   *         @arg @ref LL_MDMA_CHANNEL_9
00973   *         @arg @ref LL_MDMA_CHANNEL_10
00974   *         @arg @ref LL_MDMA_CHANNEL_11
00975   *         @arg @ref LL_MDMA_CHANNEL_12
00976   *         @arg @ref LL_MDMA_CHANNEL_13
00977   *         @arg @ref LL_MDMA_CHANNEL_14
00978   *         @arg @ref LL_MDMA_CHANNEL_15
00979   * @param  Endianness This parameter can be one of the following values:
00980   *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE
00981   *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
00985 {
00986   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
00987
00988   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX, Endianness);
00989 }
00990
00991 /**
00992   * @brief Get Bytes Endianess.
00993   * @rmtoll CCR          BEX            LL_MDMA_GetByteEndianness
00994   * @param  MDMAx MDMAx Instance
00995   * @param  Channel This parameter can be one of the following values:
00996   *         @arg @ref LL_MDMA_CHANNEL_0
00997   *         @arg @ref LL_MDMA_CHANNEL_1
00998   *         @arg @ref LL_MDMA_CHANNEL_2
00999   *         @arg @ref LL_MDMA_CHANNEL_3
01000   *         @arg @ref LL_MDMA_CHANNEL_4
01001   *         @arg @ref LL_MDMA_CHANNEL_5
01002   *         @arg @ref LL_MDMA_CHANNEL_6
01003   *         @arg @ref LL_MDMA_CHANNEL_7
01004   *         @arg @ref LL_MDMA_CHANNEL_8
01005   *         @arg @ref LL_MDMA_CHANNEL_9
01006   *         @arg @ref LL_MDMA_CHANNEL_10
01007   *         @arg @ref LL_MDMA_CHANNEL_11
01008   *         @arg @ref LL_MDMA_CHANNEL_12
01009   *         @arg @ref LL_MDMA_CHANNEL_13
01010   *         @arg @ref LL_MDMA_CHANNEL_14
01011   *         @arg @ref LL_MDMA_CHANNEL_15
01012   * @retval Returned value can be one of the following values:
01013   *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE
01014   *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE
01015   * @retval None
01016   */
01017 __STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
01018 {
01019   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01020
01021   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX));
01022 }
01023
01024 /**
01025   * @brief Set Channel priority level.
01026   * @rmtoll CCR          PL            LL_MDMA_SetChannelPriorityLevel
01027   * @param  MDMAx MDMAx Instance
01028   * @param  Channel This parameter can be one of the following values:
01029   *         @arg @ref LL_MDMA_CHANNEL_0
01030   *         @arg @ref LL_MDMA_CHANNEL_1
01031   *         @arg @ref LL_MDMA_CHANNEL_2
01032   *         @arg @ref LL_MDMA_CHANNEL_3
01033   *         @arg @ref LL_MDMA_CHANNEL_4
01034   *         @arg @ref LL_MDMA_CHANNEL_5
01035   *         @arg @ref LL_MDMA_CHANNEL_6
01036   *         @arg @ref LL_MDMA_CHANNEL_7
01037   *         @arg @ref LL_MDMA_CHANNEL_8
01038   *         @arg @ref LL_MDMA_CHANNEL_9
01039   *         @arg @ref LL_MDMA_CHANNEL_10
01040   *         @arg @ref LL_MDMA_CHANNEL_11
01041   *         @arg @ref LL_MDMA_CHANNEL_12
01042   *         @arg @ref LL_MDMA_CHANNEL_13
01043   *         @arg @ref LL_MDMA_CHANNEL_14
01044   *         @arg @ref LL_MDMA_CHANNEL_15
01045   * @param  Priority This parameter can be one of the following values:
01046   *         @arg @ref LL_MDMA_PRIORITY_LOW
01047   *         @arg @ref LL_MDMA_PRIORITY_MEDIUM
01048   *         @arg @ref LL_MDMA_PRIORITY_HIGH
01049   *         @arg @ref LL_MDMA_PRIORITY_VERYHIGH
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)
01053 {
01054   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01055
01056   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL, Priority);
01057 }
01058
01059 /**
01060   * @brief Get Channel priority level.
01061   * @rmtoll CCR          PL            LL_MDMA_GetChannelPriorityLevel
01062   * @param  MDMAx MDMAx Instance
01063   * @param  Channel This parameter can be one of the following values:
01064   *         @arg @ref LL_MDMA_CHANNEL_0
01065   *         @arg @ref LL_MDMA_CHANNEL_1
01066   *         @arg @ref LL_MDMA_CHANNEL_2
01067   *         @arg @ref LL_MDMA_CHANNEL_3
01068   *         @arg @ref LL_MDMA_CHANNEL_4
01069   *         @arg @ref LL_MDMA_CHANNEL_5
01070   *         @arg @ref LL_MDMA_CHANNEL_6
01071   *         @arg @ref LL_MDMA_CHANNEL_7
01072   *         @arg @ref LL_MDMA_CHANNEL_8
01073   *         @arg @ref LL_MDMA_CHANNEL_9
01074   *         @arg @ref LL_MDMA_CHANNEL_10
01075   *         @arg @ref LL_MDMA_CHANNEL_11
01076   *         @arg @ref LL_MDMA_CHANNEL_12
01077   *         @arg @ref LL_MDMA_CHANNEL_13
01078   *         @arg @ref LL_MDMA_CHANNEL_14
01079   *         @arg @ref LL_MDMA_CHANNEL_15
01080   * @retval Returned value can be one of the following values:
01081   *         @arg @ref LL_MDMA_PRIORITY_LOW
01082   *         @arg @ref LL_MDMA_PRIORITY_MEDIUM
01083   *         @arg @ref LL_MDMA_PRIORITY_HIGH
01084   *         @arg @ref LL_MDMA_PRIORITY_VERYHIGH
01085   * @retval None
01086   */
01087 __STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel)
01088 {
01089   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01090
01091   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL));
01092 }
01093
01094 /**
01095   * @brief Configure MDMA transfer parameters.
01096   * @rmtoll CTCR          BWM            LL_MDMA_ConfigTransfer\n
01097   * @rmtoll CTCR          SWRM           LL_MDMA_ConfigTransfer\n
01098   * @rmtoll CTCR          TRGM           LL_MDMA_ConfigTransfer\n
01099   * @rmtoll CTCR          PAM            LL_MDMA_ConfigTransfer\n
01100   * @rmtoll CTCR          PKE            LL_MDMA_ConfigTransfer\n
01101   * @rmtoll CTCR          TLEN           LL_MDMA_ConfigTransfer\n
01102   * @rmtoll CTCR          DBURST         LL_MDMA_ConfigTransfer\n
01103   * @rmtoll CTCR          SBURST         LL_MDMA_ConfigTransfer\n
01104   * @rmtoll CTCR          DINCOS         LL_MDMA_ConfigTransfer\n
01105   * @rmtoll CTCR          SINCOS         LL_MDMA_ConfigTransfer\n
01106   * @rmtoll CTCR          DSIZE          LL_MDMA_ConfigTransfer\n
01107   * @rmtoll CTCR          SSIZE          LL_MDMA_ConfigTransfer\n
01108   * @rmtoll CTCR          DINC           LL_MDMA_ConfigTransfer\n
01109   * @rmtoll CTCR          SINC           LL_MDMA_ConfigTransfer
01110   * @param  MDMAx MDMAx Instance
01111   * @param  Channel This parameter can be one of the following values:
01112   *         @arg @ref LL_MDMA_CHANNEL_0
01113   *         @arg @ref LL_MDMA_CHANNEL_1
01114   *         @arg @ref LL_MDMA_CHANNEL_2
01115   *         @arg @ref LL_MDMA_CHANNEL_3
01116   *         @arg @ref LL_MDMA_CHANNEL_4
01117   *         @arg @ref LL_MDMA_CHANNEL_5
01118   *         @arg @ref LL_MDMA_CHANNEL_6
01119   *         @arg @ref LL_MDMA_CHANNEL_7
01120   *         @arg @ref LL_MDMA_CHANNEL_8
01121   *         @arg @ref LL_MDMA_CHANNEL_9
01122   *         @arg @ref LL_MDMA_CHANNEL_10
01123   *         @arg @ref LL_MDMA_CHANNEL_11
01124   *         @arg @ref LL_MDMA_CHANNEL_12
01125   *         @arg @ref LL_MDMA_CHANNEL_13
01126   *         @arg @ref LL_MDMA_CHANNEL_14
01127   *         @arg @ref LL_MDMA_CHANNEL_15
01128   * @param  Configuration This parameter must be a combination of all the following values:
01129   *         @arg @ref LL_MDMA_BUFF_WRITE_DISABLE or @ref LL_MDMA_BUFF_WRITE_ENABLE
01130   *         @arg @ref LL_MDMA_REQUEST_MODE_HW or @ref LL_MDMA_REQUEST_MODE_SW
01131   *         @arg @ref LL_MDMA_BUFFER_TRANSFER or @ref LL_MDMA_BLOCK_TRANSFER or @ref LL_MDMA_REPEAT_BLOCK_TRANSFER or @ref LL_MDMA_FULL_TRANSFER
01132   *         @arg @ref LL_MDMA_DATAALIGN_RIGHT or @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED or @ref LL_MDMA_DATAALIGN_LEFT
01133   *         @arg @ref LL_MDMA_PACK_DISABLE or @ref LL_MDMA_PACK_ENABLE
01134   *         @arg @ref LL_MDMA_DEST_BURST_SINGLE or @ref LL_MDMA_DEST_BURST_2BEATS or @ref LL_MDMA_DEST_BURST_4BEATS or @ref LL_MDMA_DEST_BURST_8BEATS
01135   *              or @ref LL_MDMA_DEST_BURST_16BEATS or @ref LL_MDMA_DEST_BURST_32BEATS or @ref LL_MDMA_DEST_BURST_64BEATS or @ref LL_MDMA_DEST_BURST_128BEATS
01136   *         @arg @ref LL_MDMA_SRC_BURST_SINGLE or @ref LL_MDMA_SRC_BURST_2BEATS or @ref LL_MDMA_SRC_BURST_4BEATS or @ref LL_MDMA_SRC_BURST_8BEATS
01137   *              or @ref LL_MDMA_SRC_BURST_16BEATS or @ref LL_MDMA_SRC_BURST_32BEATS or @ref LL_MDMA_SRC_BURST_64BEATS or @ref LL_MDMA_SRC_BURST_128BEATS
01138   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE or @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD or @ref LL_MDMA_DEST_INC_OFFSET_WORD or @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
01139   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE or @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD or @ref LL_MDMA_SRC_INC_OFFSET_WORD or @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
01140   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE or @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD or @ref LL_MDMA_DEST_DATA_SIZE_WORD or @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
01141   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE or @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD or @ref LL_MDMA_SRC_DATA_SIZE_WORD or @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
01142   *         @arg @ref LL_MDMA_DEST_FIXED or @ref LL_MDMA_DEST_INCREMENT or @ref LL_MDMA_DEST_DECREMENT
01143   *         @arg @ref LL_MDMA_SRC_FIXED or @ref LL_MDMA_SRC_INCREMENT or @ref LL_MDMA_SRC_DECREMENT
01144   * @param  BufferXferLength This parameter can be a value Between 0 to 0x0000007F
01145   * @retval None
01146   */
01147 __STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)
01148 {
01149   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01150
01151   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR,
01152   Configuration | ((BufferXferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk));
01153 }
01154
01155 /**
01156   * @brief Enable Bufferable Write Mode.
01157   * @rmtoll CTCR          BWM            LL_MDMA_EnableBufferableWrMode
01158   * @param  MDMAx MDMAx Instance
01159   * @param  Channel This parameter can be one of the following values:
01160   *         @arg @ref LL_MDMA_CHANNEL_0
01161   *         @arg @ref LL_MDMA_CHANNEL_1
01162   *         @arg @ref LL_MDMA_CHANNEL_2
01163   *         @arg @ref LL_MDMA_CHANNEL_3
01164   *         @arg @ref LL_MDMA_CHANNEL_4
01165   *         @arg @ref LL_MDMA_CHANNEL_5
01166   *         @arg @ref LL_MDMA_CHANNEL_6
01167   *         @arg @ref LL_MDMA_CHANNEL_7
01168   *         @arg @ref LL_MDMA_CHANNEL_8
01169   *         @arg @ref LL_MDMA_CHANNEL_9
01170   *         @arg @ref LL_MDMA_CHANNEL_10
01171   *         @arg @ref LL_MDMA_CHANNEL_11
01172   *         @arg @ref LL_MDMA_CHANNEL_12
01173   *         @arg @ref LL_MDMA_CHANNEL_13
01174   *         @arg @ref LL_MDMA_CHANNEL_14
01175   *         @arg @ref LL_MDMA_CHANNEL_15
01176   * @retval None
01177   */
01178 __STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
01179 {
01180   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01181
01182   SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
01183 }
01184
01185 /**
01186   * @brief Disable Bufferable Write Mode.
01187   * @rmtoll CTCR          BWM            LL_MDMA_DisableBufferableWrMode
01188   * @param  MDMAx MDMAx Instance
01189   * @param  Channel This parameter can be one of the following values:
01190   *         @arg @ref LL_MDMA_CHANNEL_0
01191   *         @arg @ref LL_MDMA_CHANNEL_1
01192   *         @arg @ref LL_MDMA_CHANNEL_2
01193   *         @arg @ref LL_MDMA_CHANNEL_3
01194   *         @arg @ref LL_MDMA_CHANNEL_4
01195   *         @arg @ref LL_MDMA_CHANNEL_5
01196   *         @arg @ref LL_MDMA_CHANNEL_6
01197   *         @arg @ref LL_MDMA_CHANNEL_7
01198   *         @arg @ref LL_MDMA_CHANNEL_8
01199   *         @arg @ref LL_MDMA_CHANNEL_9
01200   *         @arg @ref LL_MDMA_CHANNEL_10
01201   *         @arg @ref LL_MDMA_CHANNEL_11
01202   *         @arg @ref LL_MDMA_CHANNEL_12
01203   *         @arg @ref LL_MDMA_CHANNEL_13
01204   *         @arg @ref LL_MDMA_CHANNEL_14
01205   *         @arg @ref LL_MDMA_CHANNEL_15
01206   * @retval None
01207   */
01208 __STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
01209 {
01210   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01211
01212   CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
01213 }
01214
01215 /**
01216   * @brief Check if Bufferable Write Mode is enabled or disabled.
01217   * @rmtoll CTCR          BWM            LL_MDMA_IsEnabledBufferableWrMode
01218   * @param  MDMAx MDMAx Instance
01219   * @param  Channel This parameter can be one of the following values:
01220   *         @arg @ref LL_MDMA_CHANNEL_0
01221   *         @arg @ref LL_MDMA_CHANNEL_1
01222   *         @arg @ref LL_MDMA_CHANNEL_2
01223   *         @arg @ref LL_MDMA_CHANNEL_3
01224   *         @arg @ref LL_MDMA_CHANNEL_4
01225   *         @arg @ref LL_MDMA_CHANNEL_5
01226   *         @arg @ref LL_MDMA_CHANNEL_6
01227   *         @arg @ref LL_MDMA_CHANNEL_7
01228   *         @arg @ref LL_MDMA_CHANNEL_8
01229   *         @arg @ref LL_MDMA_CHANNEL_9
01230   *         @arg @ref LL_MDMA_CHANNEL_10
01231   *         @arg @ref LL_MDMA_CHANNEL_11
01232   *         @arg @ref LL_MDMA_CHANNEL_12
01233   *         @arg @ref LL_MDMA_CHANNEL_13
01234   *         @arg @ref LL_MDMA_CHANNEL_14
01235   *         @arg @ref LL_MDMA_CHANNEL_15
01236   * @retval State of bit (1 or 0).
01237   */
01238 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
01239 {
01240   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01241
01242   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM) == (MDMA_CTCR_BWM)) ? 1UL : 0UL);
01243 }
01244
01245 /**
01246   * @brief Set Request Mode.
01247   * @rmtoll CTCR          SWRM            LL_MDMA_SetRequestMode
01248   * @param  MDMAx MDMAx Instance
01249   * @param  Channel This parameter can be one of the following values:
01250   *         @arg @ref LL_MDMA_CHANNEL_0
01251   *         @arg @ref LL_MDMA_CHANNEL_1
01252   *         @arg @ref LL_MDMA_CHANNEL_2
01253   *         @arg @ref LL_MDMA_CHANNEL_3
01254   *         @arg @ref LL_MDMA_CHANNEL_4
01255   *         @arg @ref LL_MDMA_CHANNEL_5
01256   *         @arg @ref LL_MDMA_CHANNEL_6
01257   *         @arg @ref LL_MDMA_CHANNEL_7
01258   *         @arg @ref LL_MDMA_CHANNEL_8
01259   *         @arg @ref LL_MDMA_CHANNEL_9
01260   *         @arg @ref LL_MDMA_CHANNEL_10
01261   *         @arg @ref LL_MDMA_CHANNEL_11
01262   *         @arg @ref LL_MDMA_CHANNEL_12
01263   *         @arg @ref LL_MDMA_CHANNEL_13
01264   *         @arg @ref LL_MDMA_CHANNEL_14
01265   *         @arg @ref LL_MDMA_CHANNEL_15
01266   * @param  RequestMode This parameter can be one of the following values:
01267   *         @arg @ref LL_MDMA_REQUEST_MODE_HW
01268   *         @arg @ref LL_MDMA_REQUEST_MODE_SW
01269   * @retval None
01270   */
01271 __STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)
01272 {
01273   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01274
01275   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM, RequestMode);
01276 }
01277
01278 /**
01279   * @brief Get Request Mode.
01280   * @rmtoll CTCR          SWRM            LL_MDMA_GetRequestMode
01281   * @param  MDMAx MDMAx Instance
01282   * @param  Channel This parameter can be one of the following values:
01283   *         @arg @ref LL_MDMA_CHANNEL_0
01284   *         @arg @ref LL_MDMA_CHANNEL_1
01285   *         @arg @ref LL_MDMA_CHANNEL_2
01286   *         @arg @ref LL_MDMA_CHANNEL_3
01287   *         @arg @ref LL_MDMA_CHANNEL_4
01288   *         @arg @ref LL_MDMA_CHANNEL_5
01289   *         @arg @ref LL_MDMA_CHANNEL_6
01290   *         @arg @ref LL_MDMA_CHANNEL_7
01291   *         @arg @ref LL_MDMA_CHANNEL_8
01292   *         @arg @ref LL_MDMA_CHANNEL_9
01293   *         @arg @ref LL_MDMA_CHANNEL_10
01294   *         @arg @ref LL_MDMA_CHANNEL_11
01295   *         @arg @ref LL_MDMA_CHANNEL_12
01296   *         @arg @ref LL_MDMA_CHANNEL_13
01297   *         @arg @ref LL_MDMA_CHANNEL_14
01298   *         @arg @ref LL_MDMA_CHANNEL_15
01299   * @retval Returned value can be one of the following values:
01300   *         @arg @ref LL_MDMA_REQUEST_MODE_HW
01301   *         @arg @ref LL_MDMA_REQUEST_MODE_SW
01302   * @retval None
01303   */
01304 __STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
01305 {
01306   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01307
01308   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM));
01309 }
01310
01311 /**
01312   * @brief Set Trigger Mode.
01313   * @rmtoll CTCR          TRGM            LL_MDMA_SetTriggerMode
01314   * @param  MDMAx MDMAx Instance
01315   * @param  Channel This parameter can be one of the following values:
01316   *         @arg @ref LL_MDMA_CHANNEL_0
01317   *         @arg @ref LL_MDMA_CHANNEL_1
01318   *         @arg @ref LL_MDMA_CHANNEL_2
01319   *         @arg @ref LL_MDMA_CHANNEL_3
01320   *         @arg @ref LL_MDMA_CHANNEL_4
01321   *         @arg @ref LL_MDMA_CHANNEL_5
01322   *         @arg @ref LL_MDMA_CHANNEL_6
01323   *         @arg @ref LL_MDMA_CHANNEL_7
01324   *         @arg @ref LL_MDMA_CHANNEL_8
01325   *         @arg @ref LL_MDMA_CHANNEL_9
01326   *         @arg @ref LL_MDMA_CHANNEL_10
01327   *         @arg @ref LL_MDMA_CHANNEL_11
01328   *         @arg @ref LL_MDMA_CHANNEL_12
01329   *         @arg @ref LL_MDMA_CHANNEL_13
01330   *         @arg @ref LL_MDMA_CHANNEL_14
01331   *         @arg @ref LL_MDMA_CHANNEL_15
01332   * @param  TriggerMode This parameter can be one of the following values:
01333   *         @arg @ref LL_MDMA_BUFFER_TRANSFER
01334   *         @arg @ref LL_MDMA_BLOCK_TRANSFER
01335   *         @arg @ref LL_MDMA_REPEAT_BLOCK_TRANSFER
01336   *         @arg @ref LL_MDMA_FULL_TRANSFER
01337   * @retval None
01338   */
01339 __STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)
01340 {
01341   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01342
01343   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM, TriggerMode);
01344 }
01345
01346 /**
01347   * @brief Get Trigger Mode.
01348   * @rmtoll CTCR          TRGM            LL_MDMA_GetTriggerMode
01349   * @param  MDMAx MDMAx Instance
01350   * @param  Channel This parameter can be one of the following values:
01351   *         @arg @ref LL_MDMA_CHANNEL_0
01352   *         @arg @ref LL_MDMA_CHANNEL_1
01353   *         @arg @ref LL_MDMA_CHANNEL_2
01354   *         @arg @ref LL_MDMA_CHANNEL_3
01355   *         @arg @ref LL_MDMA_CHANNEL_4
01356   *         @arg @ref LL_MDMA_CHANNEL_5
01357   *         @arg @ref LL_MDMA_CHANNEL_6
01358   *         @arg @ref LL_MDMA_CHANNEL_7
01359   *         @arg @ref LL_MDMA_CHANNEL_8
01360   *         @arg @ref LL_MDMA_CHANNEL_9
01361   *         @arg @ref LL_MDMA_CHANNEL_10
01362   *         @arg @ref LL_MDMA_CHANNEL_11
01363   *         @arg @ref LL_MDMA_CHANNEL_12
01364   *         @arg @ref LL_MDMA_CHANNEL_13
01365   *         @arg @ref LL_MDMA_CHANNEL_14
01366   *         @arg @ref LL_MDMA_CHANNEL_15
01367   * @retval Returned value can be one of the following values:
01368   *         @arg @ref LL_MDMA_BUFFER_TRANSFER
01369   *         @arg @ref LL_MDMA_BLOCK_TRANSFER
01370   *         @arg @ref LL_MDMA_REPEAT_BLOCK_TRANSFER
01371   *         @arg @ref LL_MDMA_FULL_TRANSFER
01372   * @retval None
01373   */
01374 __STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
01375 {
01376   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01377
01378   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM));
01379 }
01380
01381 /**
01382   * @brief Set Padding Alignment.
01383   * @rmtoll CTCR          PAM            LL_MDMA_SetPaddingAlignment
01384   * @param  MDMAx MDMAx Instance
01385   * @param  Channel This parameter can be one of the following values:
01386   *         @arg @ref LL_MDMA_CHANNEL_0
01387   *         @arg @ref LL_MDMA_CHANNEL_1
01388   *         @arg @ref LL_MDMA_CHANNEL_2
01389   *         @arg @ref LL_MDMA_CHANNEL_3
01390   *         @arg @ref LL_MDMA_CHANNEL_4
01391   *         @arg @ref LL_MDMA_CHANNEL_5
01392   *         @arg @ref LL_MDMA_CHANNEL_6
01393   *         @arg @ref LL_MDMA_CHANNEL_7
01394   *         @arg @ref LL_MDMA_CHANNEL_8
01395   *         @arg @ref LL_MDMA_CHANNEL_9
01396   *         @arg @ref LL_MDMA_CHANNEL_10
01397   *         @arg @ref LL_MDMA_CHANNEL_11
01398   *         @arg @ref LL_MDMA_CHANNEL_12
01399   *         @arg @ref LL_MDMA_CHANNEL_13
01400   *         @arg @ref LL_MDMA_CHANNEL_14
01401   *         @arg @ref LL_MDMA_CHANNEL_15
01402   * @param  PaddingAlignment This parameter can be one of the following values:
01403   *         @arg @ref LL_MDMA_DATAALIGN_RIGHT
01404   *         @arg @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED
01405   *         @arg @ref LL_MDMA_DATAALIGN_LEFT
01406   * @retval None
01407   */
01408 __STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)
01409 {
01410   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01411
01412   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM, PaddingAlignment);
01413 }
01414
01415 /**
01416   * @brief Get Padding Alignment.
01417   * @rmtoll CTCR          PAM            LL_MDMA_GetPaddingAlignment
01418   * @param  MDMAx MDMAx Instance
01419   * @param  Channel This parameter can be one of the following values:
01420   *         @arg @ref LL_MDMA_CHANNEL_0
01421   *         @arg @ref LL_MDMA_CHANNEL_1
01422   *         @arg @ref LL_MDMA_CHANNEL_2
01423   *         @arg @ref LL_MDMA_CHANNEL_3
01424   *         @arg @ref LL_MDMA_CHANNEL_4
01425   *         @arg @ref LL_MDMA_CHANNEL_5
01426   *         @arg @ref LL_MDMA_CHANNEL_6
01427   *         @arg @ref LL_MDMA_CHANNEL_7
01428   *         @arg @ref LL_MDMA_CHANNEL_8
01429   *         @arg @ref LL_MDMA_CHANNEL_9
01430   *         @arg @ref LL_MDMA_CHANNEL_10
01431   *         @arg @ref LL_MDMA_CHANNEL_11
01432   *         @arg @ref LL_MDMA_CHANNEL_12
01433   *         @arg @ref LL_MDMA_CHANNEL_13
01434   *         @arg @ref LL_MDMA_CHANNEL_14
01435   *         @arg @ref LL_MDMA_CHANNEL_15
01436   * @retval Returned value can be one of the following values:
01437   *         @arg @ref LL_MDMA_DATAALIGN_RIGHT
01438   *         @arg @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED
01439   *         @arg @ref LL_MDMA_DATAALIGN_LEFT
01440   * @retval None
01441   */
01442 __STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel)
01443 {
01444   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01445
01446   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM));
01447 }
01448
01449
01450 /**
01451   * @brief Enable Packing.
01452   * @rmtoll CTCR          PKE            LL_MDMA_EnablePacking
01453   * @param  MDMAx MDMAx Instance
01454   * @param  Channel This parameter can be one of the following values:
01455   *         @arg @ref LL_MDMA_CHANNEL_0
01456   *         @arg @ref LL_MDMA_CHANNEL_1
01457   *         @arg @ref LL_MDMA_CHANNEL_2
01458   *         @arg @ref LL_MDMA_CHANNEL_3
01459   *         @arg @ref LL_MDMA_CHANNEL_4
01460   *         @arg @ref LL_MDMA_CHANNEL_5
01461   *         @arg @ref LL_MDMA_CHANNEL_6
01462   *         @arg @ref LL_MDMA_CHANNEL_7
01463   *         @arg @ref LL_MDMA_CHANNEL_8
01464   *         @arg @ref LL_MDMA_CHANNEL_9
01465   *         @arg @ref LL_MDMA_CHANNEL_10
01466   *         @arg @ref LL_MDMA_CHANNEL_11
01467   *         @arg @ref LL_MDMA_CHANNEL_12
01468   *         @arg @ref LL_MDMA_CHANNEL_13
01469   *         @arg @ref LL_MDMA_CHANNEL_14
01470   *         @arg @ref LL_MDMA_CHANNEL_15
01471   * @retval None
01472   */
01473 __STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
01474 {
01475   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01476
01477   SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
01478 }
01479
01480 /**
01481   * @brief Disable Packing.
01482   * @rmtoll CTCR          PKE            LL_MDMA_DisablePacking
01483   * @param  MDMAx MDMAx Instance
01484   * @param  Channel This parameter can be one of the following values:
01485   *         @arg @ref LL_MDMA_CHANNEL_0
01486   *         @arg @ref LL_MDMA_CHANNEL_1
01487   *         @arg @ref LL_MDMA_CHANNEL_2
01488   *         @arg @ref LL_MDMA_CHANNEL_3
01489   *         @arg @ref LL_MDMA_CHANNEL_4
01490   *         @arg @ref LL_MDMA_CHANNEL_5
01491   *         @arg @ref LL_MDMA_CHANNEL_6
01492   *         @arg @ref LL_MDMA_CHANNEL_7
01493   *         @arg @ref LL_MDMA_CHANNEL_8
01494   *         @arg @ref LL_MDMA_CHANNEL_9
01495   *         @arg @ref LL_MDMA_CHANNEL_10
01496   *         @arg @ref LL_MDMA_CHANNEL_11
01497   *         @arg @ref LL_MDMA_CHANNEL_12
01498   *         @arg @ref LL_MDMA_CHANNEL_13
01499   *         @arg @ref LL_MDMA_CHANNEL_14
01500   *         @arg @ref LL_MDMA_CHANNEL_15
01501   * @retval None
01502   */
01503 __STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
01504 {
01505   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01506
01507   CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
01508 }
01509
01510 /**
01511   * @brief Check if packing is enabled or disabled.
01512   * @rmtoll CTCR          PKE            LL_MDMA_IsEnabledPacking
01513   * @param  MDMAx MDMAx Instance
01514   * @param  Channel This parameter can be one of the following values:
01515   *         @arg @ref LL_MDMA_CHANNEL_0
01516   *         @arg @ref LL_MDMA_CHANNEL_1
01517   *         @arg @ref LL_MDMA_CHANNEL_2
01518   *         @arg @ref LL_MDMA_CHANNEL_3
01519   *         @arg @ref LL_MDMA_CHANNEL_4
01520   *         @arg @ref LL_MDMA_CHANNEL_5
01521   *         @arg @ref LL_MDMA_CHANNEL_6
01522   *         @arg @ref LL_MDMA_CHANNEL_7
01523   *         @arg @ref LL_MDMA_CHANNEL_8
01524   *         @arg @ref LL_MDMA_CHANNEL_9
01525   *         @arg @ref LL_MDMA_CHANNEL_10
01526   *         @arg @ref LL_MDMA_CHANNEL_11
01527   *         @arg @ref LL_MDMA_CHANNEL_12
01528   *         @arg @ref LL_MDMA_CHANNEL_13
01529   *         @arg @ref LL_MDMA_CHANNEL_14
01530   *         @arg @ref LL_MDMA_CHANNEL_15
01531   * @retval State of bit (1 or 0).
01532   */
01533 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
01534 {
01535   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01536
01537   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE) == (MDMA_CTCR_PKE)) ? 1UL : 0UL);
01538 }
01539
01540 /**
01541   * @brief Set Buffer Transfer Length.
01542   * @rmtoll CTCR          TLEN            LL_MDMA_SetBufferTransferLength
01543   * @param  MDMAx MDMAx Instance
01544   * @param  Channel This parameter can be one of the following values:
01545   *         @arg @ref LL_MDMA_CHANNEL_0
01546   *         @arg @ref LL_MDMA_CHANNEL_1
01547   *         @arg @ref LL_MDMA_CHANNEL_2
01548   *         @arg @ref LL_MDMA_CHANNEL_3
01549   *         @arg @ref LL_MDMA_CHANNEL_4
01550   *         @arg @ref LL_MDMA_CHANNEL_5
01551   *         @arg @ref LL_MDMA_CHANNEL_6
01552   *         @arg @ref LL_MDMA_CHANNEL_7
01553   *         @arg @ref LL_MDMA_CHANNEL_8
01554   *         @arg @ref LL_MDMA_CHANNEL_9
01555   *         @arg @ref LL_MDMA_CHANNEL_10
01556   *         @arg @ref LL_MDMA_CHANNEL_11
01557   *         @arg @ref LL_MDMA_CHANNEL_12
01558   *         @arg @ref LL_MDMA_CHANNEL_13
01559   *         @arg @ref LL_MDMA_CHANNEL_14
01560   *         @arg @ref LL_MDMA_CHANNEL_15
01561   * @param  Length Between 0 to 0x0000007F
01562   * @retval None
01563   */
01564 __STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)
01565 {
01566   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01567
01568   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN,
01569               (Length << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
01570 }
01571
01572 /**
01573   * @brief Get Buffer Transfer Length.
01574   * @rmtoll CTCR          TLEN            LL_MDMA_GetBufferTransferLength
01575   * @param  MDMAx MDMAx Instance
01576   * @param  Channel This parameter can be one of the following values:
01577   *         @arg @ref LL_MDMA_CHANNEL_0
01578   *         @arg @ref LL_MDMA_CHANNEL_1
01579   *         @arg @ref LL_MDMA_CHANNEL_2
01580   *         @arg @ref LL_MDMA_CHANNEL_3
01581   *         @arg @ref LL_MDMA_CHANNEL_4
01582   *         @arg @ref LL_MDMA_CHANNEL_5
01583   *         @arg @ref LL_MDMA_CHANNEL_6
01584   *         @arg @ref LL_MDMA_CHANNEL_7
01585   *         @arg @ref LL_MDMA_CHANNEL_8
01586   *         @arg @ref LL_MDMA_CHANNEL_9
01587   *         @arg @ref LL_MDMA_CHANNEL_10
01588   *         @arg @ref LL_MDMA_CHANNEL_11
01589   *         @arg @ref LL_MDMA_CHANNEL_12
01590   *         @arg @ref LL_MDMA_CHANNEL_13
01591   *         @arg @ref LL_MDMA_CHANNEL_14
01592   *         @arg @ref LL_MDMA_CHANNEL_15
01593   * @retval Between 0 to 0x0000007F
01594   * @retval None
01595   */
01596 __STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
01597 {
01598   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01599
01600   return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN) >> MDMA_CTCR_TLEN_Pos);
01601 }
01602
01603 /**
01604   * @brief Set Destination burst transfer.
01605   * @rmtoll CTCR          DBURST            LL_MDMA_SetDestinationBurstSize
01606   * @param  MDMAx MDMAx Instance
01607   * @param  Channel This parameter can be one of the following values:
01608   *         @arg @ref LL_MDMA_CHANNEL_0
01609   *         @arg @ref LL_MDMA_CHANNEL_1
01610   *         @arg @ref LL_MDMA_CHANNEL_2
01611   *         @arg @ref LL_MDMA_CHANNEL_3
01612   *         @arg @ref LL_MDMA_CHANNEL_4
01613   *         @arg @ref LL_MDMA_CHANNEL_5
01614   *         @arg @ref LL_MDMA_CHANNEL_6
01615   *         @arg @ref LL_MDMA_CHANNEL_7
01616   *         @arg @ref LL_MDMA_CHANNEL_8
01617   *         @arg @ref LL_MDMA_CHANNEL_9
01618   *         @arg @ref LL_MDMA_CHANNEL_10
01619   *         @arg @ref LL_MDMA_CHANNEL_11
01620   *         @arg @ref LL_MDMA_CHANNEL_12
01621   *         @arg @ref LL_MDMA_CHANNEL_13
01622   *         @arg @ref LL_MDMA_CHANNEL_14
01623   *         @arg @ref LL_MDMA_CHANNEL_15
01624   * @param  Dburst This parameter can be one of the following values:
01625   *         @arg @ref LL_MDMA_DEST_BURST_SINGLE
01626   *         @arg @ref LL_MDMA_DEST_BURST_2BEATS
01627   *         @arg @ref LL_MDMA_DEST_BURST_4BEATS
01628   *         @arg @ref LL_MDMA_DEST_BURST_8BEATS
01629   *         @arg @ref LL_MDMA_DEST_BURST_16BEATS
01630   *         @arg @ref LL_MDMA_DEST_BURST_32BEATS
01631   *         @arg @ref LL_MDMA_DEST_BURST_64BEATS
01632   *         @arg @ref LL_MDMA_DEST_BURST_128BEATS
01633   * @retval None
01634   */
01635 __STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)
01636 {
01637   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01638
01639   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST, Dburst);
01640 }
01641
01642 /**
01643   * @brief Get Destination burst transfer.
01644   * @rmtoll CTCR          DBURST            LL_MDMA_GetDestinationBurstSize
01645   * @param  MDMAx MDMAx Instance
01646   * @param  Channel This parameter can be one of the following values:
01647   *         @arg @ref LL_MDMA_CHANNEL_0
01648   *         @arg @ref LL_MDMA_CHANNEL_1
01649   *         @arg @ref LL_MDMA_CHANNEL_2
01650   *         @arg @ref LL_MDMA_CHANNEL_3
01651   *         @arg @ref LL_MDMA_CHANNEL_4
01652   *         @arg @ref LL_MDMA_CHANNEL_5
01653   *         @arg @ref LL_MDMA_CHANNEL_6
01654   *         @arg @ref LL_MDMA_CHANNEL_7
01655   *         @arg @ref LL_MDMA_CHANNEL_8
01656   *         @arg @ref LL_MDMA_CHANNEL_9
01657   *         @arg @ref LL_MDMA_CHANNEL_10
01658   *         @arg @ref LL_MDMA_CHANNEL_11
01659   *         @arg @ref LL_MDMA_CHANNEL_12
01660   *         @arg @ref LL_MDMA_CHANNEL_13
01661   *         @arg @ref LL_MDMA_CHANNEL_14
01662   *         @arg @ref LL_MDMA_CHANNEL_15
01663   * @retval Returned value can be one of the following values:
01664   *         @arg @ref LL_MDMA_DEST_BURST_SINGLE
01665   *         @arg @ref LL_MDMA_DEST_BURST_2BEATS
01666   *         @arg @ref LL_MDMA_DEST_BURST_4BEATS
01667   *         @arg @ref LL_MDMA_DEST_BURST_8BEATS
01668   *         @arg @ref LL_MDMA_DEST_BURST_16BEATS
01669   *         @arg @ref LL_MDMA_DEST_BURST_32BEATS
01670   *         @arg @ref LL_MDMA_DEST_BURST_64BEATS
01671   *         @arg @ref LL_MDMA_DEST_BURST_128BEATS
01672   * @retval None
01673   */
01674 __STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
01675 {
01676   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01677
01678   return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST));
01679 }
01680
01681 /**
01682   * @brief Set Source burst transfer.
01683   * @rmtoll CTCR          SBURST            LL_MDMA_SetSourceBurstSize
01684   * @param  MDMAx MDMAx Instance
01685   * @param  Channel This parameter can be one of the following values:
01686   *         @arg @ref LL_MDMA_CHANNEL_0
01687   *         @arg @ref LL_MDMA_CHANNEL_1
01688   *         @arg @ref LL_MDMA_CHANNEL_2
01689   *         @arg @ref LL_MDMA_CHANNEL_3
01690   *         @arg @ref LL_MDMA_CHANNEL_4
01691   *         @arg @ref LL_MDMA_CHANNEL_5
01692   *         @arg @ref LL_MDMA_CHANNEL_6
01693   *         @arg @ref LL_MDMA_CHANNEL_7
01694   *         @arg @ref LL_MDMA_CHANNEL_8
01695   *         @arg @ref LL_MDMA_CHANNEL_9
01696   *         @arg @ref LL_MDMA_CHANNEL_10
01697   *         @arg @ref LL_MDMA_CHANNEL_11
01698   *         @arg @ref LL_MDMA_CHANNEL_12
01699   *         @arg @ref LL_MDMA_CHANNEL_13
01700   *         @arg @ref LL_MDMA_CHANNEL_14
01701   *         @arg @ref LL_MDMA_CHANNEL_15
01702   * @param  Sburst This parameter can be one of the following values:
01703   *         @arg @ref LL_MDMA_SRC_BURST_SINGLE
01704   *         @arg @ref LL_MDMA_SRC_BURST_2BEATS
01705   *         @arg @ref LL_MDMA_SRC_BURST_4BEATS
01706   *         @arg @ref LL_MDMA_SRC_BURST_8BEATS
01707   *         @arg @ref LL_MDMA_SRC_BURST_16BEATS
01708   *         @arg @ref LL_MDMA_SRC_BURST_32BEATS
01709   *         @arg @ref LL_MDMA_SRC_BURST_64BEATS
01710   *         @arg @ref LL_MDMA_SRC_BURST_128BEATS
01711   * @retval None
01712   */
01713 __STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)
01714 {
01715   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01716
01717   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST, Sburst);
01718 }
01719
01720 /**
01721   * @brief Get Source burst transfer.
01722   * @rmtoll CTCR          SBURST            LL_MDMA_GetSourceBurstSize
01723   * @param  MDMAx MDMAx Instance
01724   * @param  Channel This parameter can be one of the following values:
01725   *         @arg @ref LL_MDMA_CHANNEL_0
01726   *         @arg @ref LL_MDMA_CHANNEL_1
01727   *         @arg @ref LL_MDMA_CHANNEL_2
01728   *         @arg @ref LL_MDMA_CHANNEL_3
01729   *         @arg @ref LL_MDMA_CHANNEL_4
01730   *         @arg @ref LL_MDMA_CHANNEL_5
01731   *         @arg @ref LL_MDMA_CHANNEL_6
01732   *         @arg @ref LL_MDMA_CHANNEL_7
01733   *         @arg @ref LL_MDMA_CHANNEL_8
01734   *         @arg @ref LL_MDMA_CHANNEL_9
01735   *         @arg @ref LL_MDMA_CHANNEL_10
01736   *         @arg @ref LL_MDMA_CHANNEL_11
01737   *         @arg @ref LL_MDMA_CHANNEL_12
01738   *         @arg @ref LL_MDMA_CHANNEL_13
01739   *         @arg @ref LL_MDMA_CHANNEL_14
01740   *         @arg @ref LL_MDMA_CHANNEL_15
01741   * @retval Returned value can be one of the following values:
01742   *         @arg @ref LL_MDMA_SRC_BURST_SINGLE
01743   *         @arg @ref LL_MDMA_SRC_BURST_2BEATS
01744   *         @arg @ref LL_MDMA_SRC_BURST_4BEATS
01745   *         @arg @ref LL_MDMA_SRC_BURST_8BEATS
01746   *         @arg @ref LL_MDMA_SRC_BURST_16BEATS
01747   *         @arg @ref LL_MDMA_SRC_BURST_32BEATS
01748   *         @arg @ref LL_MDMA_SRC_BURST_64BEATS
01749   *         @arg @ref LL_MDMA_SRC_BURST_128BEATS
01750   * @retval None
01751   */
01752 __STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
01753 {
01754   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01755
01756   return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST));
01757 }
01758
01759 /**
01760   * @brief Set Destination Increment Offset Size.
01761   * @rmtoll CTCR          DINCOS            LL_MDMA_SetDestinationIncSize
01762   * @param  MDMAx MDMAx Instance
01763   * @param  Channel This parameter can be one of the following values:
01764   *         @arg @ref LL_MDMA_CHANNEL_0
01765   *         @arg @ref LL_MDMA_CHANNEL_1
01766   *         @arg @ref LL_MDMA_CHANNEL_2
01767   *         @arg @ref LL_MDMA_CHANNEL_3
01768   *         @arg @ref LL_MDMA_CHANNEL_4
01769   *         @arg @ref LL_MDMA_CHANNEL_5
01770   *         @arg @ref LL_MDMA_CHANNEL_6
01771   *         @arg @ref LL_MDMA_CHANNEL_7
01772   *         @arg @ref LL_MDMA_CHANNEL_8
01773   *         @arg @ref LL_MDMA_CHANNEL_9
01774   *         @arg @ref LL_MDMA_CHANNEL_10
01775   *         @arg @ref LL_MDMA_CHANNEL_11
01776   *         @arg @ref LL_MDMA_CHANNEL_12
01777   *         @arg @ref LL_MDMA_CHANNEL_13
01778   *         @arg @ref LL_MDMA_CHANNEL_14
01779   *         @arg @ref LL_MDMA_CHANNEL_15
01780   * @param  IncSize This parameter can be one of the following values:
01781   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE
01782   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD
01783   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_WORD
01784   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
01785   * @retval None
01786   */
01787 __STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
01788 {
01789   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01790
01791   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS, IncSize);
01792 }
01793
01794 /**
01795   * @brief Get Destination Increment Offset Size.
01796   * @rmtoll CTCR          DINCOS            LL_MDMA_GetDestinationIncSize
01797   * @param  MDMAx MDMAx Instance
01798   * @param  Channel This parameter can be one of the following values:
01799   *         @arg @ref LL_MDMA_CHANNEL_0
01800   *         @arg @ref LL_MDMA_CHANNEL_1
01801   *         @arg @ref LL_MDMA_CHANNEL_2
01802   *         @arg @ref LL_MDMA_CHANNEL_3
01803   *         @arg @ref LL_MDMA_CHANNEL_4
01804   *         @arg @ref LL_MDMA_CHANNEL_5
01805   *         @arg @ref LL_MDMA_CHANNEL_6
01806   *         @arg @ref LL_MDMA_CHANNEL_7
01807   *         @arg @ref LL_MDMA_CHANNEL_8
01808   *         @arg @ref LL_MDMA_CHANNEL_9
01809   *         @arg @ref LL_MDMA_CHANNEL_10
01810   *         @arg @ref LL_MDMA_CHANNEL_11
01811   *         @arg @ref LL_MDMA_CHANNEL_12
01812   *         @arg @ref LL_MDMA_CHANNEL_13
01813   *         @arg @ref LL_MDMA_CHANNEL_14
01814   *         @arg @ref LL_MDMA_CHANNEL_15
01815   * @retval Returned value can be one of the following values:
01816   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE
01817   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD
01818   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_WORD
01819   *         @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD
01820   * @retval None
01821   */
01822 __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
01823 {
01824   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01825
01826   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS));
01827 }
01828
01829 /**
01830   * @brief Set Source Increment Offset Size.
01831   * @rmtoll CTCR          SINCOS            LL_MDMA_SetSourceIncSize
01832   * @param  MDMAx MDMAx Instance
01833   * @param  Channel This parameter can be one of the following values:
01834   *         @arg @ref LL_MDMA_CHANNEL_0
01835   *         @arg @ref LL_MDMA_CHANNEL_1
01836   *         @arg @ref LL_MDMA_CHANNEL_2
01837   *         @arg @ref LL_MDMA_CHANNEL_3
01838   *         @arg @ref LL_MDMA_CHANNEL_4
01839   *         @arg @ref LL_MDMA_CHANNEL_5
01840   *         @arg @ref LL_MDMA_CHANNEL_6
01841   *         @arg @ref LL_MDMA_CHANNEL_7
01842   *         @arg @ref LL_MDMA_CHANNEL_8
01843   *         @arg @ref LL_MDMA_CHANNEL_9
01844   *         @arg @ref LL_MDMA_CHANNEL_10
01845   *         @arg @ref LL_MDMA_CHANNEL_11
01846   *         @arg @ref LL_MDMA_CHANNEL_12
01847   *         @arg @ref LL_MDMA_CHANNEL_13
01848   *         @arg @ref LL_MDMA_CHANNEL_14
01849   *         @arg @ref LL_MDMA_CHANNEL_15
01850   * @param  IncSize This parameter can be one of the following values:
01851   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE
01852   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD
01853   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_WORD
01854   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
01858 {
01859   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01860
01861   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS, IncSize);
01862 }
01863
01864 /**
01865   * @brief Get Source Increment Offset Size.
01866   * @rmtoll CTCR          SINCOS            LL_MDMA_GetSourceIncSize
01867   * @param  MDMAx MDMAx Instance
01868   * @param  Channel This parameter can be one of the following values:
01869   *         @arg @ref LL_MDMA_CHANNEL_0
01870   *         @arg @ref LL_MDMA_CHANNEL_1
01871   *         @arg @ref LL_MDMA_CHANNEL_2
01872   *         @arg @ref LL_MDMA_CHANNEL_3
01873   *         @arg @ref LL_MDMA_CHANNEL_4
01874   *         @arg @ref LL_MDMA_CHANNEL_5
01875   *         @arg @ref LL_MDMA_CHANNEL_6
01876   *         @arg @ref LL_MDMA_CHANNEL_7
01877   *         @arg @ref LL_MDMA_CHANNEL_8
01878   *         @arg @ref LL_MDMA_CHANNEL_9
01879   *         @arg @ref LL_MDMA_CHANNEL_10
01880   *         @arg @ref LL_MDMA_CHANNEL_11
01881   *         @arg @ref LL_MDMA_CHANNEL_12
01882   *         @arg @ref LL_MDMA_CHANNEL_13
01883   *         @arg @ref LL_MDMA_CHANNEL_14
01884   *         @arg @ref LL_MDMA_CHANNEL_15
01885   * @retval Returned value can be one of the following values:
01886   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE
01887   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD
01888   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_WORD
01889   *         @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD
01890   * @retval None
01891   */
01892 __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
01893 {
01894   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01895
01896   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS));
01897 }
01898
01899 /**
01900   * @brief Set Destination Data Size.
01901   * @rmtoll CTCR          DSIZE            LL_MDMA_SetDestinationDataSize
01902   * @param  MDMAx MDMAx Instance
01903   * @param  Channel This parameter can be one of the following values:
01904   *         @arg @ref LL_MDMA_CHANNEL_0
01905   *         @arg @ref LL_MDMA_CHANNEL_1
01906   *         @arg @ref LL_MDMA_CHANNEL_2
01907   *         @arg @ref LL_MDMA_CHANNEL_3
01908   *         @arg @ref LL_MDMA_CHANNEL_4
01909   *         @arg @ref LL_MDMA_CHANNEL_5
01910   *         @arg @ref LL_MDMA_CHANNEL_6
01911   *         @arg @ref LL_MDMA_CHANNEL_7
01912   *         @arg @ref LL_MDMA_CHANNEL_8
01913   *         @arg @ref LL_MDMA_CHANNEL_9
01914   *         @arg @ref LL_MDMA_CHANNEL_10
01915   *         @arg @ref LL_MDMA_CHANNEL_11
01916   *         @arg @ref LL_MDMA_CHANNEL_12
01917   *         @arg @ref LL_MDMA_CHANNEL_13
01918   *         @arg @ref LL_MDMA_CHANNEL_14
01919   *         @arg @ref LL_MDMA_CHANNEL_15
01920   * @param  DestDataSize This parameter can be one of the following values:
01921   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE
01922   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD
01923   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_WORD
01924   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
01925   * @retval None
01926   */
01927 __STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)
01928 {
01929   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01930
01931   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE, DestDataSize);
01932 }
01933
01934 /**
01935   * @brief Get Destination Data Size.
01936   * @rmtoll CTCR          DSIZE            LL_MDMA_GetDestinationDataSize
01937   * @param  MDMAx MDMAx Instance
01938   * @param  Channel This parameter can be one of the following values:
01939   *         @arg @ref LL_MDMA_CHANNEL_0
01940   *         @arg @ref LL_MDMA_CHANNEL_1
01941   *         @arg @ref LL_MDMA_CHANNEL_2
01942   *         @arg @ref LL_MDMA_CHANNEL_3
01943   *         @arg @ref LL_MDMA_CHANNEL_4
01944   *         @arg @ref LL_MDMA_CHANNEL_5
01945   *         @arg @ref LL_MDMA_CHANNEL_6
01946   *         @arg @ref LL_MDMA_CHANNEL_7
01947   *         @arg @ref LL_MDMA_CHANNEL_8
01948   *         @arg @ref LL_MDMA_CHANNEL_9
01949   *         @arg @ref LL_MDMA_CHANNEL_10
01950   *         @arg @ref LL_MDMA_CHANNEL_11
01951   *         @arg @ref LL_MDMA_CHANNEL_12
01952   *         @arg @ref LL_MDMA_CHANNEL_13
01953   *         @arg @ref LL_MDMA_CHANNEL_14
01954   *         @arg @ref LL_MDMA_CHANNEL_15
01955   * @retval Returned value can be one of the following values:
01956   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE
01957   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD
01958   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_WORD
01959   *         @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD
01960   * @retval None
01961   */
01962 __STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
01963 {
01964   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
01965
01966   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE));
01967 }
01968
01969 /**
01970   * @brief Set Source Data Size.
01971   * @rmtoll CTCR          SSIZE            LL_MDMA_SetSourceDataSize
01972   * @param  MDMAx MDMAx Instance
01973   * @param  Channel This parameter can be one of the following values:
01974   *         @arg @ref LL_MDMA_CHANNEL_0
01975   *         @arg @ref LL_MDMA_CHANNEL_1
01976   *         @arg @ref LL_MDMA_CHANNEL_2
01977   *         @arg @ref LL_MDMA_CHANNEL_3
01978   *         @arg @ref LL_MDMA_CHANNEL_4
01979   *         @arg @ref LL_MDMA_CHANNEL_5
01980   *         @arg @ref LL_MDMA_CHANNEL_6
01981   *         @arg @ref LL_MDMA_CHANNEL_7
01982   *         @arg @ref LL_MDMA_CHANNEL_8
01983   *         @arg @ref LL_MDMA_CHANNEL_9
01984   *         @arg @ref LL_MDMA_CHANNEL_10
01985   *         @arg @ref LL_MDMA_CHANNEL_11
01986   *         @arg @ref LL_MDMA_CHANNEL_12
01987   *         @arg @ref LL_MDMA_CHANNEL_13
01988   *         @arg @ref LL_MDMA_CHANNEL_14
01989   *         @arg @ref LL_MDMA_CHANNEL_15
01990   * @param  SrcDataSize This parameter can be one of the following values:
01991   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE
01992   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD
01993   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_WORD
01994   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
01995   * @retval None
01996   */
01997 __STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)
01998 {
01999   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02000
02001   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE, SrcDataSize);
02002 }
02003
02004 /**
02005   * @brief Get Source Data Size.
02006   * @rmtoll CTCR          SSIZE            LL_MDMA_GetSourceDataSize
02007   * @param  MDMAx MDMAx Instance
02008   * @param  Channel This parameter can be one of the following values:
02009   *         @arg @ref LL_MDMA_CHANNEL_0
02010   *         @arg @ref LL_MDMA_CHANNEL_1
02011   *         @arg @ref LL_MDMA_CHANNEL_2
02012   *         @arg @ref LL_MDMA_CHANNEL_3
02013   *         @arg @ref LL_MDMA_CHANNEL_4
02014   *         @arg @ref LL_MDMA_CHANNEL_5
02015   *         @arg @ref LL_MDMA_CHANNEL_6
02016   *         @arg @ref LL_MDMA_CHANNEL_7
02017   *         @arg @ref LL_MDMA_CHANNEL_8
02018   *         @arg @ref LL_MDMA_CHANNEL_9
02019   *         @arg @ref LL_MDMA_CHANNEL_10
02020   *         @arg @ref LL_MDMA_CHANNEL_11
02021   *         @arg @ref LL_MDMA_CHANNEL_12
02022   *         @arg @ref LL_MDMA_CHANNEL_13
02023   *         @arg @ref LL_MDMA_CHANNEL_14
02024   *         @arg @ref LL_MDMA_CHANNEL_15
02025   * @retval Returned value can be one of the following values:
02026   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE
02027   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD
02028   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_WORD
02029   *         @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD
02030   * @retval None
02031   */
02032 __STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
02033 {
02034   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02035
02036   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE));
02037 }
02038
02039 /**
02040   * @brief Set Destination Increment Mode.
02041   * @rmtoll CTCR          DINC            LL_MDMA_SetDestinationIncMode
02042   * @param  MDMAx MDMAx Instance
02043   * @param  Channel This parameter can be one of the following values:
02044   *         @arg @ref LL_MDMA_CHANNEL_0
02045   *         @arg @ref LL_MDMA_CHANNEL_1
02046   *         @arg @ref LL_MDMA_CHANNEL_2
02047   *         @arg @ref LL_MDMA_CHANNEL_3
02048   *         @arg @ref LL_MDMA_CHANNEL_4
02049   *         @arg @ref LL_MDMA_CHANNEL_5
02050   *         @arg @ref LL_MDMA_CHANNEL_6
02051   *         @arg @ref LL_MDMA_CHANNEL_7
02052   *         @arg @ref LL_MDMA_CHANNEL_8
02053   *         @arg @ref LL_MDMA_CHANNEL_9
02054   *         @arg @ref LL_MDMA_CHANNEL_10
02055   *         @arg @ref LL_MDMA_CHANNEL_11
02056   *         @arg @ref LL_MDMA_CHANNEL_12
02057   *         @arg @ref LL_MDMA_CHANNEL_13
02058   *         @arg @ref LL_MDMA_CHANNEL_14
02059   *         @arg @ref LL_MDMA_CHANNEL_15
02060   * @param  DestIncMode This parameter can be one of the following values:
02061   *         @arg @ref LL_MDMA_DEST_FIXED
02062   *         @arg @ref LL_MDMA_DEST_INCREMENT
02063   *         @arg @ref LL_MDMA_DEST_DECREMENT
02064   * @retval None
02065   */
02066 __STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)
02067 {
02068   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02069
02070   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC, DestIncMode);
02071 }
02072
02073 /**
02074   * @brief Get Destination Increment Mode.
02075   * @rmtoll CTCR          DINC            LL_MDMA_GetDestinationIncMode
02076   * @param  MDMAx MDMAx Instance
02077   * @param  Channel This parameter can be one of the following values:
02078   *         @arg @ref LL_MDMA_CHANNEL_0
02079   *         @arg @ref LL_MDMA_CHANNEL_1
02080   *         @arg @ref LL_MDMA_CHANNEL_2
02081   *         @arg @ref LL_MDMA_CHANNEL_3
02082   *         @arg @ref LL_MDMA_CHANNEL_4
02083   *         @arg @ref LL_MDMA_CHANNEL_5
02084   *         @arg @ref LL_MDMA_CHANNEL_6
02085   *         @arg @ref LL_MDMA_CHANNEL_7
02086   *         @arg @ref LL_MDMA_CHANNEL_8
02087   *         @arg @ref LL_MDMA_CHANNEL_9
02088   *         @arg @ref LL_MDMA_CHANNEL_10
02089   *         @arg @ref LL_MDMA_CHANNEL_11
02090   *         @arg @ref LL_MDMA_CHANNEL_12
02091   *         @arg @ref LL_MDMA_CHANNEL_13
02092   *         @arg @ref LL_MDMA_CHANNEL_14
02093   *         @arg @ref LL_MDMA_CHANNEL_15
02094   * @retval Returned value can be one of the following values:
02095   *         @arg @ref LL_MDMA_DEST_FIXED
02096   *         @arg @ref LL_MDMA_DEST_INCREMENT
02097   *         @arg @ref LL_MDMA_DEST_DECREMENT
02098   * @retval None
02099   */
02100 __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
02101 {
02102   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02103
02104   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC));
02105 }
02106
02107 /**
02108   * @brief Set Source Increment Mode.
02109   * @rmtoll CTCR          SINC            LL_MDMA_SetSourceIncMode
02110   * @param  MDMAx MDMAx Instance
02111   * @param  Channel This parameter can be one of the following values:
02112   *         @arg @ref LL_MDMA_CHANNEL_0
02113   *         @arg @ref LL_MDMA_CHANNEL_1
02114   *         @arg @ref LL_MDMA_CHANNEL_2
02115   *         @arg @ref LL_MDMA_CHANNEL_3
02116   *         @arg @ref LL_MDMA_CHANNEL_4
02117   *         @arg @ref LL_MDMA_CHANNEL_5
02118   *         @arg @ref LL_MDMA_CHANNEL_6
02119   *         @arg @ref LL_MDMA_CHANNEL_7
02120   *         @arg @ref LL_MDMA_CHANNEL_8
02121   *         @arg @ref LL_MDMA_CHANNEL_9
02122   *         @arg @ref LL_MDMA_CHANNEL_10
02123   *         @arg @ref LL_MDMA_CHANNEL_11
02124   *         @arg @ref LL_MDMA_CHANNEL_12
02125   *         @arg @ref LL_MDMA_CHANNEL_13
02126   *         @arg @ref LL_MDMA_CHANNEL_14
02127   *         @arg @ref LL_MDMA_CHANNEL_15
02128   * @param  SrcIncMode This parameter can be one of the following values:
02129   *         @arg @ref LL_MDMA_SRC_FIXED
02130   *         @arg @ref LL_MDMA_SRC_INCREMENT
02131   *         @arg @ref LL_MDMA_SRC_DECREMENT
02132   * @retval None
02133   */
02134 __STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)
02135 {
02136   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02137
02138   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC, SrcIncMode);
02139 }
02140
02141 /**
02142   * @brief Get Source Increment Mode.
02143   * @rmtoll CTCR          SINC            LL_MDMA_GetSourceIncMode
02144   * @param  MDMAx MDMAx Instance
02145   * @param  Channel This parameter can be one of the following values:
02146   *         @arg @ref LL_MDMA_CHANNEL_0
02147   *         @arg @ref LL_MDMA_CHANNEL_1
02148   *         @arg @ref LL_MDMA_CHANNEL_2
02149   *         @arg @ref LL_MDMA_CHANNEL_3
02150   *         @arg @ref LL_MDMA_CHANNEL_4
02151   *         @arg @ref LL_MDMA_CHANNEL_5
02152   *         @arg @ref LL_MDMA_CHANNEL_6
02153   *         @arg @ref LL_MDMA_CHANNEL_7
02154   *         @arg @ref LL_MDMA_CHANNEL_8
02155   *         @arg @ref LL_MDMA_CHANNEL_9
02156   *         @arg @ref LL_MDMA_CHANNEL_10
02157   *         @arg @ref LL_MDMA_CHANNEL_11
02158   *         @arg @ref LL_MDMA_CHANNEL_12
02159   *         @arg @ref LL_MDMA_CHANNEL_13
02160   *         @arg @ref LL_MDMA_CHANNEL_14
02161   *         @arg @ref LL_MDMA_CHANNEL_15
02162   * @retval Returned value can be one of the following values:
02163   *         @arg @ref LL_MDMA_SRC_FIXED
02164   *         @arg @ref LL_MDMA_SRC_INCREMENT
02165   *         @arg @ref LL_MDMA_SRC_DECREMENT
02166   * @retval None
02167   */
02168 __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
02169 {
02170   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02171
02172   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC));
02173 }
02174
02175 /**
02176   * @brief Configure MDMA Block number of data and repeat Count.
02177   * @rmtoll CBNDTR        BRC            LL_MDMA_ConfigBlkCounters\n
02178   * @rmtoll CBNDTR        BNDT           LL_MDMA_ConfigBlkCounters
02179   * @param  MDMAx MDMAx Instance
02180   * @param  Channel This parameter can be one of the following values:
02181   *         @arg @ref LL_MDMA_CHANNEL_0
02182   *         @arg @ref LL_MDMA_CHANNEL_1
02183   *         @arg @ref LL_MDMA_CHANNEL_2
02184   *         @arg @ref LL_MDMA_CHANNEL_3
02185   *         @arg @ref LL_MDMA_CHANNEL_4
02186   *         @arg @ref LL_MDMA_CHANNEL_5
02187   *         @arg @ref LL_MDMA_CHANNEL_6
02188   *         @arg @ref LL_MDMA_CHANNEL_7
02189   *         @arg @ref LL_MDMA_CHANNEL_8
02190   *         @arg @ref LL_MDMA_CHANNEL_9
02191   *         @arg @ref LL_MDMA_CHANNEL_10
02192   *         @arg @ref LL_MDMA_CHANNEL_11
02193   *         @arg @ref LL_MDMA_CHANNEL_12
02194   *         @arg @ref LL_MDMA_CHANNEL_13
02195   *         @arg @ref LL_MDMA_CHANNEL_14
02196   *         @arg @ref LL_MDMA_CHANNEL_15
02197   * @param  BlockRepeatCount Between 0 to 0x00000FFF
02198   * @param  BlkDataLength Between 0 to 0x00010000
02199   * @retval None
02200   */
02201 __STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)
02202 {
02203   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02204
02205   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
02206                MDMA_CBNDTR_BRC | MDMA_CBNDTR_BNDT,
02207               ((BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));
02208 }
02209
02210 /**
02211   * @brief Set Block Number of data bytes to transfer.
02212   * @rmtoll CBNDTR          BNDT            LL_MDMA_SetBlkDataLength
02213   * @param  MDMAx MDMAx Instance
02214   * @param  Channel This parameter can be one of the following values:
02215   *         @arg @ref LL_MDMA_CHANNEL_0
02216   *         @arg @ref LL_MDMA_CHANNEL_1
02217   *         @arg @ref LL_MDMA_CHANNEL_2
02218   *         @arg @ref LL_MDMA_CHANNEL_3
02219   *         @arg @ref LL_MDMA_CHANNEL_4
02220   *         @arg @ref LL_MDMA_CHANNEL_5
02221   *         @arg @ref LL_MDMA_CHANNEL_6
02222   *         @arg @ref LL_MDMA_CHANNEL_7
02223   *         @arg @ref LL_MDMA_CHANNEL_8
02224   *         @arg @ref LL_MDMA_CHANNEL_9
02225   *         @arg @ref LL_MDMA_CHANNEL_10
02226   *         @arg @ref LL_MDMA_CHANNEL_11
02227   *         @arg @ref LL_MDMA_CHANNEL_12
02228   *         @arg @ref LL_MDMA_CHANNEL_13
02229   *         @arg @ref LL_MDMA_CHANNEL_14
02230   *         @arg @ref LL_MDMA_CHANNEL_15
02231   * @param  BlkDataLength Between 0 to 0x00010000
02232   * @retval None
02233   */
02234 __STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)
02235 {
02236   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02237
02238   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT, (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));
02239 }
02240
02241 /**
02242   * @brief Get Block Number of data bytes to transfer.
02243   * @rmtoll CBNDTR          BNDT            LL_MDMA_GetBlkDataLength
02244   * @param  MDMAx MDMAx Instance
02245   * @param  Channel This parameter can be one of the following values:
02246   *         @arg @ref LL_MDMA_CHANNEL_0
02247   *         @arg @ref LL_MDMA_CHANNEL_1
02248   *         @arg @ref LL_MDMA_CHANNEL_2
02249   *         @arg @ref LL_MDMA_CHANNEL_3
02250   *         @arg @ref LL_MDMA_CHANNEL_4
02251   *         @arg @ref LL_MDMA_CHANNEL_5
02252   *         @arg @ref LL_MDMA_CHANNEL_6
02253   *         @arg @ref LL_MDMA_CHANNEL_7
02254   *         @arg @ref LL_MDMA_CHANNEL_8
02255   *         @arg @ref LL_MDMA_CHANNEL_9
02256   *         @arg @ref LL_MDMA_CHANNEL_10
02257   *         @arg @ref LL_MDMA_CHANNEL_11
02258   *         @arg @ref LL_MDMA_CHANNEL_12
02259   *         @arg @ref LL_MDMA_CHANNEL_13
02260   *         @arg @ref LL_MDMA_CHANNEL_14
02261   *         @arg @ref LL_MDMA_CHANNEL_15
02262   * @retval Between 0 to 0x00010000
02263   * @retval None
02264   */
02265 __STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
02266 {
02267   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02268
02269   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT));
02270 }
02271
02272 /**
02273   * @brief Set Block Repeat Count.
02274   * @rmtoll CBNDTR          BRC            LL_MDMA_SetBlkRepeatCount
02275   * @param  MDMAx MDMAx Instance
02276   * @param  Channel This parameter can be one of the following values:
02277   *         @arg @ref LL_MDMA_CHANNEL_0
02278   *         @arg @ref LL_MDMA_CHANNEL_1
02279   *         @arg @ref LL_MDMA_CHANNEL_2
02280   *         @arg @ref LL_MDMA_CHANNEL_3
02281   *         @arg @ref LL_MDMA_CHANNEL_4
02282   *         @arg @ref LL_MDMA_CHANNEL_5
02283   *         @arg @ref LL_MDMA_CHANNEL_6
02284   *         @arg @ref LL_MDMA_CHANNEL_7
02285   *         @arg @ref LL_MDMA_CHANNEL_8
02286   *         @arg @ref LL_MDMA_CHANNEL_9
02287   *         @arg @ref LL_MDMA_CHANNEL_10
02288   *         @arg @ref LL_MDMA_CHANNEL_11
02289   *         @arg @ref LL_MDMA_CHANNEL_12
02290   *         @arg @ref LL_MDMA_CHANNEL_13
02291   *         @arg @ref LL_MDMA_CHANNEL_14
02292   *         @arg @ref LL_MDMA_CHANNEL_15
02293   * @param  BlockRepeatCount Between 0 to 0x00000FFF
02294   * @retval None
02295   */
02296 __STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)
02297 {
02298   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02299
02300   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC,
02301               (BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk);
02302 }
02303
02304 /**
02305   * @brief Get Block Repeat Count.
02306   * @rmtoll CBNDTR          BRC            LL_MDMA_GetBlkRepeatCount
02307   * @param  MDMAx MDMAx Instance
02308   * @param  Channel This parameter can be one of the following values:
02309   *         @arg @ref LL_MDMA_CHANNEL_0
02310   *         @arg @ref LL_MDMA_CHANNEL_1
02311   *         @arg @ref LL_MDMA_CHANNEL_2
02312   *         @arg @ref LL_MDMA_CHANNEL_3
02313   *         @arg @ref LL_MDMA_CHANNEL_4
02314   *         @arg @ref LL_MDMA_CHANNEL_5
02315   *         @arg @ref LL_MDMA_CHANNEL_6
02316   *         @arg @ref LL_MDMA_CHANNEL_7
02317   *         @arg @ref LL_MDMA_CHANNEL_8
02318   *         @arg @ref LL_MDMA_CHANNEL_9
02319   *         @arg @ref LL_MDMA_CHANNEL_10
02320   *         @arg @ref LL_MDMA_CHANNEL_11
02321   *         @arg @ref LL_MDMA_CHANNEL_12
02322   *         @arg @ref LL_MDMA_CHANNEL_13
02323   *         @arg @ref LL_MDMA_CHANNEL_14
02324   *         @arg @ref LL_MDMA_CHANNEL_15
02325   * @retval Between 0 to 0x00000FFF
02326   * @retval None
02327   */
02328 __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel)
02329 {
02330   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02331
02332   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC) >> MDMA_CBNDTR_BRC_Pos);
02333 }
02334
02335 /**
02336   * @brief Configure MDMA block repeat address update mode.
02337   * @rmtoll CBNDTR        BRDUM            LL_MDMA_ConfigBlkRepeatAddrUpdate\n
02338   * @rmtoll CBNDTR        BRSUM            LL_MDMA_ConfigBlkRepeatAddrUpdate
02339   * @param  MDMAx MDMAx Instance
02340   * @param  Channel This parameter can be one of the following values:
02341   *         @arg @ref LL_MDMA_CHANNEL_0
02342   *         @arg @ref LL_MDMA_CHANNEL_1
02343   *         @arg @ref LL_MDMA_CHANNEL_2
02344   *         @arg @ref LL_MDMA_CHANNEL_3
02345   *         @arg @ref LL_MDMA_CHANNEL_4
02346   *         @arg @ref LL_MDMA_CHANNEL_5
02347   *         @arg @ref LL_MDMA_CHANNEL_6
02348   *         @arg @ref LL_MDMA_CHANNEL_7
02349   *         @arg @ref LL_MDMA_CHANNEL_8
02350   *         @arg @ref LL_MDMA_CHANNEL_9
02351   *         @arg @ref LL_MDMA_CHANNEL_10
02352   *         @arg @ref LL_MDMA_CHANNEL_11
02353   *         @arg @ref LL_MDMA_CHANNEL_12
02354   *         @arg @ref LL_MDMA_CHANNEL_13
02355   *         @arg @ref LL_MDMA_CHANNEL_14
02356   *         @arg @ref LL_MDMA_CHANNEL_15
02357   * @param  Configuration This parameter must be a combination of all the following values:
02358   *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
02359   *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
02360   * @retval None
02361   */
02362 __STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
02363 {
02364   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02365
02366   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
02367                MDMA_CBNDTR_BRDUM | MDMA_CBNDTR_BRSUM,
02368                Configuration);
02369 }
02370
02371 /**
02372   * @brief Set Block Repeat Destination address Update Mode.
02373   * @rmtoll CBNDTR          BRDUM            LL_MDMA_SetBlkRepeatDestAddrUpdate
02374   * @param  MDMAx MDMAx Instance
02375   * @param  Channel This parameter can be one of the following values:
02376   *         @arg @ref LL_MDMA_CHANNEL_0
02377   *         @arg @ref LL_MDMA_CHANNEL_1
02378   *         @arg @ref LL_MDMA_CHANNEL_2
02379   *         @arg @ref LL_MDMA_CHANNEL_3
02380   *         @arg @ref LL_MDMA_CHANNEL_4
02381   *         @arg @ref LL_MDMA_CHANNEL_5
02382   *         @arg @ref LL_MDMA_CHANNEL_6
02383   *         @arg @ref LL_MDMA_CHANNEL_7
02384   *         @arg @ref LL_MDMA_CHANNEL_8
02385   *         @arg @ref LL_MDMA_CHANNEL_9
02386   *         @arg @ref LL_MDMA_CHANNEL_10
02387   *         @arg @ref LL_MDMA_CHANNEL_11
02388   *         @arg @ref LL_MDMA_CHANNEL_12
02389   *         @arg @ref LL_MDMA_CHANNEL_13
02390   *         @arg @ref LL_MDMA_CHANNEL_14
02391   *         @arg @ref LL_MDMA_CHANNEL_15
02392   * @param  DestAdrUpdateMode This parameter can be one of the following values:
02393   *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT
02394   *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
02395   * @retval None
02396   */
02397 __STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)
02398 {
02399   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02400
02401   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM, DestAdrUpdateMode);
02402 }
02403
02404 /**
02405   * @brief Get Block Repeat Destination address Update Mode.
02406   * @rmtoll CBNDTR          BRDUM            LL_MDMA_GetBlkRepeatDestAddrUpdate
02407   * @param  MDMAx MDMAx Instance
02408   * @param  Channel This parameter can be one of the following values:
02409   *         @arg @ref LL_MDMA_CHANNEL_0
02410   *         @arg @ref LL_MDMA_CHANNEL_1
02411   *         @arg @ref LL_MDMA_CHANNEL_2
02412   *         @arg @ref LL_MDMA_CHANNEL_3
02413   *         @arg @ref LL_MDMA_CHANNEL_4
02414   *         @arg @ref LL_MDMA_CHANNEL_5
02415   *         @arg @ref LL_MDMA_CHANNEL_6
02416   *         @arg @ref LL_MDMA_CHANNEL_7
02417   *         @arg @ref LL_MDMA_CHANNEL_8
02418   *         @arg @ref LL_MDMA_CHANNEL_9
02419   *         @arg @ref LL_MDMA_CHANNEL_10
02420   *         @arg @ref LL_MDMA_CHANNEL_11
02421   *         @arg @ref LL_MDMA_CHANNEL_12
02422   *         @arg @ref LL_MDMA_CHANNEL_13
02423   *         @arg @ref LL_MDMA_CHANNEL_14
02424   *         @arg @ref LL_MDMA_CHANNEL_15
02425   * @retval Returned value can be one of the following values:
02426   *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT
02427   *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT
02428   * @retval None
02429   */
02430 __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
02431 {
02432   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02433
02434   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM));
02435 }
02436
02437 /**
02438   * @brief Set Block Repeat Source address Update Mode.
02439   * @rmtoll CBNDTR          BRSUM            LL_MDMA_SetBlkRepeatSrcAddrUpdate
02440   * @param  MDMAx MDMAx Instance
02441   * @param  Channel This parameter can be one of the following values:
02442   *         @arg @ref LL_MDMA_CHANNEL_0
02443   *         @arg @ref LL_MDMA_CHANNEL_1
02444   *         @arg @ref LL_MDMA_CHANNEL_2
02445   *         @arg @ref LL_MDMA_CHANNEL_3
02446   *         @arg @ref LL_MDMA_CHANNEL_4
02447   *         @arg @ref LL_MDMA_CHANNEL_5
02448   *         @arg @ref LL_MDMA_CHANNEL_6
02449   *         @arg @ref LL_MDMA_CHANNEL_7
02450   *         @arg @ref LL_MDMA_CHANNEL_8
02451   *         @arg @ref LL_MDMA_CHANNEL_9
02452   *         @arg @ref LL_MDMA_CHANNEL_10
02453   *         @arg @ref LL_MDMA_CHANNEL_11
02454   *         @arg @ref LL_MDMA_CHANNEL_12
02455   *         @arg @ref LL_MDMA_CHANNEL_13
02456   *         @arg @ref LL_MDMA_CHANNEL_14
02457   *         @arg @ref LL_MDMA_CHANNEL_15
02458   * @param  SrcAdrUpdateMode This parameter can be one of the following values:
02459   *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT
02460   *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
02461   * @retval None
02462   */
02463 __STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)
02464 {
02465   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02466
02467   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM, SrcAdrUpdateMode);
02468 }
02469
02470 /**
02471   * @brief Get Block Repeat Source address Update Mode.
02472   * @rmtoll CBNDTR          BRSUM            LL_MDMA_GetBlkRepeatSrcAddrUpdate
02473   * @param  MDMAx MDMAx Instance
02474   * @param  Channel This parameter can be one of the following values:
02475   *         @arg @ref LL_MDMA_CHANNEL_0
02476   *         @arg @ref LL_MDMA_CHANNEL_1
02477   *         @arg @ref LL_MDMA_CHANNEL_2
02478   *         @arg @ref LL_MDMA_CHANNEL_3
02479   *         @arg @ref LL_MDMA_CHANNEL_4
02480   *         @arg @ref LL_MDMA_CHANNEL_5
02481   *         @arg @ref LL_MDMA_CHANNEL_6
02482   *         @arg @ref LL_MDMA_CHANNEL_7
02483   *         @arg @ref LL_MDMA_CHANNEL_8
02484   *         @arg @ref LL_MDMA_CHANNEL_9
02485   *         @arg @ref LL_MDMA_CHANNEL_10
02486   *         @arg @ref LL_MDMA_CHANNEL_11
02487   *         @arg @ref LL_MDMA_CHANNEL_12
02488   *         @arg @ref LL_MDMA_CHANNEL_13
02489   *         @arg @ref LL_MDMA_CHANNEL_14
02490   *         @arg @ref LL_MDMA_CHANNEL_15
02491   * @retval Returned value can be one of the following values:
02492   *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT
02493   *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT
02494   * @retval None
02495   */
02496 __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
02497 {
02498   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02499
02500   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM));
02501 }
02502
02503 /**
02504   * @brief  Configure the Source and Destination addresses.
02505   * @note   This API must not be called when the MDMA channel is enabled.
02506   * @rmtoll CSAR        SAR            LL_MDMA_ConfigAddresses\n
02507   * @rmtoll CDAR        DAR            LL_MDMA_ConfigAddresses
02508   * @param  MDMAx MDMAx Instance
02509   * @param  Channel This parameter can be one of the following values:
02510   *         @arg @ref LL_MDMA_CHANNEL_0
02511   *         @arg @ref LL_MDMA_CHANNEL_1
02512   *         @arg @ref LL_MDMA_CHANNEL_2
02513   *         @arg @ref LL_MDMA_CHANNEL_3
02514   *         @arg @ref LL_MDMA_CHANNEL_4
02515   *         @arg @ref LL_MDMA_CHANNEL_5
02516   *         @arg @ref LL_MDMA_CHANNEL_6
02517   *         @arg @ref LL_MDMA_CHANNEL_7
02518   *         @arg @ref LL_MDMA_CHANNEL_8
02519   *         @arg @ref LL_MDMA_CHANNEL_9
02520   *         @arg @ref LL_MDMA_CHANNEL_10
02521   *         @arg @ref LL_MDMA_CHANNEL_11
02522   *         @arg @ref LL_MDMA_CHANNEL_12
02523   *         @arg @ref LL_MDMA_CHANNEL_13
02524   *         @arg @ref LL_MDMA_CHANNEL_14
02525   *         @arg @ref LL_MDMA_CHANNEL_15
02526   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
02527   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
02528   * @retval None
02529   */
02530 __STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel,  uint32_t SrcAddress, uint32_t DstAddress)
02531 {
02532   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02533
02534   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
02535   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DstAddress);
02536 }
02537 /**
02538   * @brief Set transfer Source address.
02539   * @rmtoll CSAR          SAR            LL_MDMA_SetSourceAddress
02540   * @param  MDMAx MDMAx Instance
02541   * @param  Channel This parameter can be one of the following values:
02542   *         @arg @ref LL_MDMA_CHANNEL_0
02543   *         @arg @ref LL_MDMA_CHANNEL_1
02544   *         @arg @ref LL_MDMA_CHANNEL_2
02545   *         @arg @ref LL_MDMA_CHANNEL_3
02546   *         @arg @ref LL_MDMA_CHANNEL_4
02547   *         @arg @ref LL_MDMA_CHANNEL_5
02548   *         @arg @ref LL_MDMA_CHANNEL_6
02549   *         @arg @ref LL_MDMA_CHANNEL_7
02550   *         @arg @ref LL_MDMA_CHANNEL_8
02551   *         @arg @ref LL_MDMA_CHANNEL_9
02552   *         @arg @ref LL_MDMA_CHANNEL_10
02553   *         @arg @ref LL_MDMA_CHANNEL_11
02554   *         @arg @ref LL_MDMA_CHANNEL_12
02555   *         @arg @ref LL_MDMA_CHANNEL_13
02556   *         @arg @ref LL_MDMA_CHANNEL_14
02557   *         @arg @ref LL_MDMA_CHANNEL_15
02558   * @param  SrcAddress Between 0 to 0xFFFFFFFF
02559   * @retval None
02560   */
02561 __STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)
02562 {
02563   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02564
02565   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
02566 }
02567
02568 /**
02569   * @brief Get transfer Source address.
02570   * @rmtoll CSAR          SAR            LL_MDMA_GetSourceAddress
02571   * @param  MDMAx MDMAx Instance
02572   * @param  Channel This parameter can be one of the following values:
02573   *         @arg @ref LL_MDMA_CHANNEL_0
02574   *         @arg @ref LL_MDMA_CHANNEL_1
02575   *         @arg @ref LL_MDMA_CHANNEL_2
02576   *         @arg @ref LL_MDMA_CHANNEL_3
02577   *         @arg @ref LL_MDMA_CHANNEL_4
02578   *         @arg @ref LL_MDMA_CHANNEL_5
02579   *         @arg @ref LL_MDMA_CHANNEL_6
02580   *         @arg @ref LL_MDMA_CHANNEL_7
02581   *         @arg @ref LL_MDMA_CHANNEL_8
02582   *         @arg @ref LL_MDMA_CHANNEL_9
02583   *         @arg @ref LL_MDMA_CHANNEL_10
02584   *         @arg @ref LL_MDMA_CHANNEL_11
02585   *         @arg @ref LL_MDMA_CHANNEL_12
02586   *         @arg @ref LL_MDMA_CHANNEL_13
02587   *         @arg @ref LL_MDMA_CHANNEL_14
02588   *         @arg @ref LL_MDMA_CHANNEL_15
02589   * @retval Between 0 to 0xFFFFFFFF
02590   * @retval None
02591   */
02592 __STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
02593 {
02594   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02595
02596   return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR));
02597 }
02598
02599 /**
02600   * @brief Set transfer Destination address.
02601   * @rmtoll CDAR          DAR            LL_MDMA_SetDestinationAddress
02602   * @param  MDMAx MDMAx Instance
02603   * @param  Channel This parameter can be one of the following values:
02604   *         @arg @ref LL_MDMA_CHANNEL_0
02605   *         @arg @ref LL_MDMA_CHANNEL_1
02606   *         @arg @ref LL_MDMA_CHANNEL_2
02607   *         @arg @ref LL_MDMA_CHANNEL_3
02608   *         @arg @ref LL_MDMA_CHANNEL_4
02609   *         @arg @ref LL_MDMA_CHANNEL_5
02610   *         @arg @ref LL_MDMA_CHANNEL_6
02611   *         @arg @ref LL_MDMA_CHANNEL_7
02612   *         @arg @ref LL_MDMA_CHANNEL_8
02613   *         @arg @ref LL_MDMA_CHANNEL_9
02614   *         @arg @ref LL_MDMA_CHANNEL_10
02615   *         @arg @ref LL_MDMA_CHANNEL_11
02616   *         @arg @ref LL_MDMA_CHANNEL_12
02617   *         @arg @ref LL_MDMA_CHANNEL_13
02618   *         @arg @ref LL_MDMA_CHANNEL_14
02619   *         @arg @ref LL_MDMA_CHANNEL_15
02620   * @param  DestAddress Between 0 to 0xFFFFFFFF
02621   * @retval None
02622   */
02623 __STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)
02624 {
02625   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02626
02627   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
02628 }
02629
02630 /**
02631   * @brief Get transfer Destination address.
02632   * @rmtoll CDAR          DAR            LL_MDMA_GetDestinationAddress
02633   * @param  MDMAx MDMAx Instance
02634   * @param  Channel This parameter can be one of the following values:
02635   *         @arg @ref LL_MDMA_CHANNEL_0
02636   *         @arg @ref LL_MDMA_CHANNEL_1
02637   *         @arg @ref LL_MDMA_CHANNEL_2
02638   *         @arg @ref LL_MDMA_CHANNEL_3
02639   *         @arg @ref LL_MDMA_CHANNEL_4
02640   *         @arg @ref LL_MDMA_CHANNEL_5
02641   *         @arg @ref LL_MDMA_CHANNEL_6
02642   *         @arg @ref LL_MDMA_CHANNEL_7
02643   *         @arg @ref LL_MDMA_CHANNEL_8
02644   *         @arg @ref LL_MDMA_CHANNEL_9
02645   *         @arg @ref LL_MDMA_CHANNEL_10
02646   *         @arg @ref LL_MDMA_CHANNEL_11
02647   *         @arg @ref LL_MDMA_CHANNEL_12
02648   *         @arg @ref LL_MDMA_CHANNEL_13
02649   *         @arg @ref LL_MDMA_CHANNEL_14
02650   *         @arg @ref LL_MDMA_CHANNEL_15
02651   * @retval Between 0 to 0xFFFFFFFF
02652   * @retval None
02653   */
02654 __STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
02655 {
02656   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02657
02658   return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR));
02659 }
02660
02661 /**
02662   * @brief  Configure the Source and Destination Block repeat addresses Update value.
02663   * @note   This API must not be called when the MDMA channel is enabled.
02664   * @rmtoll CBRUR        DUV            LL_MDMA_ConfigBlkRptAddrUpdateValue\n
02665   * @rmtoll CBRUR        SUV            LL_MDMA_ConfigBlkRptAddrUpdateValue
02666   * @param  MDMAx MDMAx Instance
02667   * @param  Channel This parameter can be one of the following values:
02668   *         @arg @ref LL_MDMA_CHANNEL_0
02669   *         @arg @ref LL_MDMA_CHANNEL_1
02670   *         @arg @ref LL_MDMA_CHANNEL_2
02671   *         @arg @ref LL_MDMA_CHANNEL_3
02672   *         @arg @ref LL_MDMA_CHANNEL_4
02673   *         @arg @ref LL_MDMA_CHANNEL_5
02674   *         @arg @ref LL_MDMA_CHANNEL_6
02675   *         @arg @ref LL_MDMA_CHANNEL_7
02676   *         @arg @ref LL_MDMA_CHANNEL_8
02677   *         @arg @ref LL_MDMA_CHANNEL_9
02678   *         @arg @ref LL_MDMA_CHANNEL_10
02679   *         @arg @ref LL_MDMA_CHANNEL_11
02680   *         @arg @ref LL_MDMA_CHANNEL_12
02681   *         @arg @ref LL_MDMA_CHANNEL_13
02682   *         @arg @ref LL_MDMA_CHANNEL_14
02683   *         @arg @ref LL_MDMA_CHANNEL_15
02684   * @param  SrctAdrUpdateValue Min_Data = 0 and Max_Data = 0x0000FFFF
02685   * @param  DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF
02686   * @retval None
02687   */
02688 __STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel,  uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)
02689 {
02690   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02691
02692   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR,
02693               (SrctAdrUpdateValue & MDMA_CBRUR_SUV_Msk)  | ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
02694 }
02695
02696 /**
02697   * @brief Set transfer Destination address Update Value.
02698   * @rmtoll CBRUR          DUV            LL_MDMA_SetBlkRptDestAddrUpdateValue
02699   * @param  MDMAx MDMAx Instance
02700   * @param  Channel This parameter can be one of the following values:
02701   *         @arg @ref LL_MDMA_CHANNEL_0
02702   *         @arg @ref LL_MDMA_CHANNEL_1
02703   *         @arg @ref LL_MDMA_CHANNEL_2
02704   *         @arg @ref LL_MDMA_CHANNEL_3
02705   *         @arg @ref LL_MDMA_CHANNEL_4
02706   *         @arg @ref LL_MDMA_CHANNEL_5
02707   *         @arg @ref LL_MDMA_CHANNEL_6
02708   *         @arg @ref LL_MDMA_CHANNEL_7
02709   *         @arg @ref LL_MDMA_CHANNEL_8
02710   *         @arg @ref LL_MDMA_CHANNEL_9
02711   *         @arg @ref LL_MDMA_CHANNEL_10
02712   *         @arg @ref LL_MDMA_CHANNEL_11
02713   *         @arg @ref LL_MDMA_CHANNEL_12
02714   *         @arg @ref LL_MDMA_CHANNEL_13
02715   *         @arg @ref LL_MDMA_CHANNEL_14
02716   *         @arg @ref LL_MDMA_CHANNEL_15
02717   * @param  DestAdrUpdateValue Between 0 to 0x0000FFFF
02718   * @retval None
02719   */
02720 __STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)
02721 {
02722   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02723
02724   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV,
02725                ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
02726 }
02727
02728 /**
02729   * @brief Get transfer Destination address Update Value.
02730   * @rmtoll CBRUR          DUV            LL_MDMA_GetBlkRptDestAddrUpdateValue
02731   * @param  MDMAx MDMAx Instance
02732   * @param  Channel This parameter can be one of the following values:
02733   *         @arg @ref LL_MDMA_CHANNEL_0
02734   *         @arg @ref LL_MDMA_CHANNEL_1
02735   *         @arg @ref LL_MDMA_CHANNEL_2
02736   *         @arg @ref LL_MDMA_CHANNEL_3
02737   *         @arg @ref LL_MDMA_CHANNEL_4
02738   *         @arg @ref LL_MDMA_CHANNEL_5
02739   *         @arg @ref LL_MDMA_CHANNEL_6
02740   *         @arg @ref LL_MDMA_CHANNEL_7
02741   *         @arg @ref LL_MDMA_CHANNEL_8
02742   *         @arg @ref LL_MDMA_CHANNEL_9
02743   *         @arg @ref LL_MDMA_CHANNEL_10
02744   *         @arg @ref LL_MDMA_CHANNEL_11
02745   *         @arg @ref LL_MDMA_CHANNEL_12
02746   *         @arg @ref LL_MDMA_CHANNEL_13
02747   *         @arg @ref LL_MDMA_CHANNEL_14
02748   *         @arg @ref LL_MDMA_CHANNEL_15
02749   * @retval Between 0 to 0x0000FFFF
02750   * @retval None
02751   */
02752 __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
02753 {
02754   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02755
02756   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV) >> MDMA_CBRUR_DUV_Pos);
02757 }
02758
02759 /**
02760   * @brief Set transfer Source address Update Value.
02761   * @rmtoll CBRUR          SUV            LL_MDMA_SetBlkRptSrcAddrUpdateValue
02762   * @param  MDMAx MDMAx Instance
02763   * @param  Channel This parameter can be one of the following values:
02764   *         @arg @ref LL_MDMA_CHANNEL_0
02765   *         @arg @ref LL_MDMA_CHANNEL_1
02766   *         @arg @ref LL_MDMA_CHANNEL_2
02767   *         @arg @ref LL_MDMA_CHANNEL_3
02768   *         @arg @ref LL_MDMA_CHANNEL_4
02769   *         @arg @ref LL_MDMA_CHANNEL_5
02770   *         @arg @ref LL_MDMA_CHANNEL_6
02771   *         @arg @ref LL_MDMA_CHANNEL_7
02772   *         @arg @ref LL_MDMA_CHANNEL_8
02773   *         @arg @ref LL_MDMA_CHANNEL_9
02774   *         @arg @ref LL_MDMA_CHANNEL_10
02775   *         @arg @ref LL_MDMA_CHANNEL_11
02776   *         @arg @ref LL_MDMA_CHANNEL_12
02777   *         @arg @ref LL_MDMA_CHANNEL_13
02778   *         @arg @ref LL_MDMA_CHANNEL_14
02779   *         @arg @ref LL_MDMA_CHANNEL_15
02780   * @param  SrcAdrUpdateValue Between 0 to 0x0000FFFF
02781   * @retval None
02782   */
02783 __STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)
02784 {
02785   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02786
02787   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV, SrcAdrUpdateValue);
02788 }
02789
02790 /**
02791   * @brief Get transfer Source address Update Value.
02792   * @rmtoll CBRUR          SUV            LL_MDMA_GetBlkRptSrcAddrUpdateValue
02793   * @param  MDMAx MDMAx Instance
02794   * @param  Channel This parameter can be one of the following values:
02795   *         @arg @ref LL_MDMA_CHANNEL_0
02796   *         @arg @ref LL_MDMA_CHANNEL_1
02797   *         @arg @ref LL_MDMA_CHANNEL_2
02798   *         @arg @ref LL_MDMA_CHANNEL_3
02799   *         @arg @ref LL_MDMA_CHANNEL_4
02800   *         @arg @ref LL_MDMA_CHANNEL_5
02801   *         @arg @ref LL_MDMA_CHANNEL_6
02802   *         @arg @ref LL_MDMA_CHANNEL_7
02803   *         @arg @ref LL_MDMA_CHANNEL_8
02804   *         @arg @ref LL_MDMA_CHANNEL_9
02805   *         @arg @ref LL_MDMA_CHANNEL_10
02806   *         @arg @ref LL_MDMA_CHANNEL_11
02807   *         @arg @ref LL_MDMA_CHANNEL_12
02808   *         @arg @ref LL_MDMA_CHANNEL_13
02809   *         @arg @ref LL_MDMA_CHANNEL_14
02810   *         @arg @ref LL_MDMA_CHANNEL_15
02811   * @retval Between 0 to 0x0000FFFF
02812   * @retval None
02813   */
02814 __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
02815 {
02816   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02817
02818   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV));
02819 }
02820
02821 /**
02822   * @brief Set transfer Link Address.
02823   * @rmtoll CLAR          LAR            LL_MDMA_SetLinkAddress
02824   * @param  MDMAx MDMAx Instance
02825   * @param  Channel This parameter can be one of the following values:
02826   *         @arg @ref LL_MDMA_CHANNEL_0
02827   *         @arg @ref LL_MDMA_CHANNEL_1
02828   *         @arg @ref LL_MDMA_CHANNEL_2
02829   *         @arg @ref LL_MDMA_CHANNEL_3
02830   *         @arg @ref LL_MDMA_CHANNEL_4
02831   *         @arg @ref LL_MDMA_CHANNEL_5
02832   *         @arg @ref LL_MDMA_CHANNEL_6
02833   *         @arg @ref LL_MDMA_CHANNEL_7
02834   *         @arg @ref LL_MDMA_CHANNEL_8
02835   *         @arg @ref LL_MDMA_CHANNEL_9
02836   *         @arg @ref LL_MDMA_CHANNEL_10
02837   *         @arg @ref LL_MDMA_CHANNEL_11
02838   *         @arg @ref LL_MDMA_CHANNEL_12
02839   *         @arg @ref LL_MDMA_CHANNEL_13
02840   *         @arg @ref LL_MDMA_CHANNEL_14
02841   *         @arg @ref LL_MDMA_CHANNEL_15
02842   * @param  LinkAddress Between 0 to 0xFFFFFFFF
02843   * @retval None
02844   */
02845 __STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)
02846 {
02847   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02848
02849   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR, LinkAddress);
02850 }
02851
02852 /**
02853   * @brief Get transfer Link Address.
02854   * @rmtoll CLAR          LAR            LL_MDMA_GetLinkAddress
02855   * @param  MDMAx MDMAx Instance
02856   * @param  Channel This parameter can be one of the following values:
02857   *         @arg @ref LL_MDMA_CHANNEL_0
02858   *         @arg @ref LL_MDMA_CHANNEL_1
02859   *         @arg @ref LL_MDMA_CHANNEL_2
02860   *         @arg @ref LL_MDMA_CHANNEL_3
02861   *         @arg @ref LL_MDMA_CHANNEL_4
02862   *         @arg @ref LL_MDMA_CHANNEL_5
02863   *         @arg @ref LL_MDMA_CHANNEL_6
02864   *         @arg @ref LL_MDMA_CHANNEL_7
02865   *         @arg @ref LL_MDMA_CHANNEL_8
02866   *         @arg @ref LL_MDMA_CHANNEL_9
02867   *         @arg @ref LL_MDMA_CHANNEL_10
02868   *         @arg @ref LL_MDMA_CHANNEL_11
02869   *         @arg @ref LL_MDMA_CHANNEL_12
02870   *         @arg @ref LL_MDMA_CHANNEL_13
02871   *         @arg @ref LL_MDMA_CHANNEL_14
02872   *         @arg @ref LL_MDMA_CHANNEL_15
02873   * @retval Between 0 to 0xFFFFFFFF
02874   * @retval None
02875   */
02876 __STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
02877 {
02878   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02879
02880   return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR));
02881 }
02882
02883 /**
02884   * @brief Configure MDMA source and destination bus selection.
02885   * @rmtoll CTBR        DBUS            LL_MDMA_ConfigBusSelection\n
02886   * @rmtoll CTBR        SBUS            LL_MDMA_ConfigBusSelection
02887   * @param  MDMAx MDMAx Instance
02888   * @param  Channel This parameter can be one of the following values:
02889   *         @arg @ref LL_MDMA_CHANNEL_0
02890   *         @arg @ref LL_MDMA_CHANNEL_1
02891   *         @arg @ref LL_MDMA_CHANNEL_2
02892   *         @arg @ref LL_MDMA_CHANNEL_3
02893   *         @arg @ref LL_MDMA_CHANNEL_4
02894   *         @arg @ref LL_MDMA_CHANNEL_5
02895   *         @arg @ref LL_MDMA_CHANNEL_6
02896   *         @arg @ref LL_MDMA_CHANNEL_7
02897   *         @arg @ref LL_MDMA_CHANNEL_8
02898   *         @arg @ref LL_MDMA_CHANNEL_9
02899   *         @arg @ref LL_MDMA_CHANNEL_10
02900   *         @arg @ref LL_MDMA_CHANNEL_11
02901   *         @arg @ref LL_MDMA_CHANNEL_12
02902   *         @arg @ref LL_MDMA_CHANNEL_13
02903   *         @arg @ref LL_MDMA_CHANNEL_14
02904   *         @arg @ref LL_MDMA_CHANNEL_15
02905   * @param  Configuration This parameter must be a combination of all the following values:
02906   *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI or @ref LL_MDMA_DEST_BUS_AHB_TCM
02907   *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM
02908   * @retval None
02909   */
02910 __STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
02911 {
02912   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02913
02914   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR,
02915                MDMA_CTBR_DBUS | MDMA_CTBR_SBUS,
02916               Configuration);
02917 }
02918
02919 /**
02920   * @brief Set Destination Bus Selection.
02921   * @rmtoll CTBR          DBUS            LL_MDMA_SetDestBusSelection
02922   * @param  MDMAx MDMAx Instance
02923   * @param  Channel This parameter can be one of the following values:
02924   *         @arg @ref LL_MDMA_CHANNEL_0
02925   *         @arg @ref LL_MDMA_CHANNEL_1
02926   *         @arg @ref LL_MDMA_CHANNEL_2
02927   *         @arg @ref LL_MDMA_CHANNEL_3
02928   *         @arg @ref LL_MDMA_CHANNEL_4
02929   *         @arg @ref LL_MDMA_CHANNEL_5
02930   *         @arg @ref LL_MDMA_CHANNEL_6
02931   *         @arg @ref LL_MDMA_CHANNEL_7
02932   *         @arg @ref LL_MDMA_CHANNEL_8
02933   *         @arg @ref LL_MDMA_CHANNEL_9
02934   *         @arg @ref LL_MDMA_CHANNEL_10
02935   *         @arg @ref LL_MDMA_CHANNEL_11
02936   *         @arg @ref LL_MDMA_CHANNEL_12
02937   *         @arg @ref LL_MDMA_CHANNEL_13
02938   *         @arg @ref LL_MDMA_CHANNEL_14
02939   *         @arg @ref LL_MDMA_CHANNEL_15
02940   * @param  DestBus This parameter can be one of the following values:
02941   *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI
02942   *         @arg @ref LL_MDMA_DEST_BUS_AHB_TCM
02943   * @retval None
02944   */
02945 __STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)
02946 {
02947   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02948
02949   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS, DestBus);
02950 }
02951
02952 /**
02953   * @brief Get Destination Bus Selection.
02954   * @rmtoll CTBR          DBUS            LL_MDMA_GetDestBusSelection
02955   * @param  MDMAx MDMAx Instance
02956   * @param  Channel This parameter can be one of the following values:
02957   *         @arg @ref LL_MDMA_CHANNEL_0
02958   *         @arg @ref LL_MDMA_CHANNEL_1
02959   *         @arg @ref LL_MDMA_CHANNEL_2
02960   *         @arg @ref LL_MDMA_CHANNEL_3
02961   *         @arg @ref LL_MDMA_CHANNEL_4
02962   *         @arg @ref LL_MDMA_CHANNEL_5
02963   *         @arg @ref LL_MDMA_CHANNEL_6
02964   *         @arg @ref LL_MDMA_CHANNEL_7
02965   *         @arg @ref LL_MDMA_CHANNEL_8
02966   *         @arg @ref LL_MDMA_CHANNEL_9
02967   *         @arg @ref LL_MDMA_CHANNEL_10
02968   *         @arg @ref LL_MDMA_CHANNEL_11
02969   *         @arg @ref LL_MDMA_CHANNEL_12
02970   *         @arg @ref LL_MDMA_CHANNEL_13
02971   *         @arg @ref LL_MDMA_CHANNEL_14
02972   *         @arg @ref LL_MDMA_CHANNEL_15
02973   * @retval Returned value can be one of the following values:
02974   *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI
02975   *         @arg @ref LL_MDMA_DEST_BUS_AHB_TCM
02976   * @retval None
02977   */
02978 __STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
02979 {
02980   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
02981
02982   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS));
02983 }
02984
02985 /**
02986   * @brief Set Source Bus Selection.
02987   * @rmtoll CTBR          SBUS            LL_MDMA_SetSrcBusSelection
02988   * @param  MDMAx MDMAx Instance
02989   * @param  Channel This parameter can be one of the following values:
02990   *         @arg @ref LL_MDMA_CHANNEL_0
02991   *         @arg @ref LL_MDMA_CHANNEL_1
02992   *         @arg @ref LL_MDMA_CHANNEL_2
02993   *         @arg @ref LL_MDMA_CHANNEL_3
02994   *         @arg @ref LL_MDMA_CHANNEL_4
02995   *         @arg @ref LL_MDMA_CHANNEL_5
02996   *         @arg @ref LL_MDMA_CHANNEL_6
02997   *         @arg @ref LL_MDMA_CHANNEL_7
02998   *         @arg @ref LL_MDMA_CHANNEL_8
02999   *         @arg @ref LL_MDMA_CHANNEL_9
03000   *         @arg @ref LL_MDMA_CHANNEL_10
03001   *         @arg @ref LL_MDMA_CHANNEL_11
03002   *         @arg @ref LL_MDMA_CHANNEL_12
03003   *         @arg @ref LL_MDMA_CHANNEL_13
03004   *         @arg @ref LL_MDMA_CHANNEL_14
03005   *         @arg @ref LL_MDMA_CHANNEL_15
03006   * @param  SrcBus This parameter can be one of the following values:
03007   *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI
03008   *         @arg @ref LL_MDMA_SRC_BUS_AHB_TCM
03009   * @retval None
03010   */
03011 __STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)
03012 {
03013   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03014
03015   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS, SrcBus);
03016 }
03017
03018 /**
03019   * @brief Get Source Bus Selection.
03020   * @rmtoll CTBR          SBUS            LL_MDMA_GetSrcBusSelection
03021   * @param  MDMAx MDMAx Instance
03022   * @param  Channel This parameter can be one of the following values:
03023   *         @arg @ref LL_MDMA_CHANNEL_0
03024   *         @arg @ref LL_MDMA_CHANNEL_1
03025   *         @arg @ref LL_MDMA_CHANNEL_2
03026   *         @arg @ref LL_MDMA_CHANNEL_3
03027   *         @arg @ref LL_MDMA_CHANNEL_4
03028   *         @arg @ref LL_MDMA_CHANNEL_5
03029   *         @arg @ref LL_MDMA_CHANNEL_6
03030   *         @arg @ref LL_MDMA_CHANNEL_7
03031   *         @arg @ref LL_MDMA_CHANNEL_8
03032   *         @arg @ref LL_MDMA_CHANNEL_9
03033   *         @arg @ref LL_MDMA_CHANNEL_10
03034   *         @arg @ref LL_MDMA_CHANNEL_11
03035   *         @arg @ref LL_MDMA_CHANNEL_12
03036   *         @arg @ref LL_MDMA_CHANNEL_13
03037   *         @arg @ref LL_MDMA_CHANNEL_14
03038   *         @arg @ref LL_MDMA_CHANNEL_15
03039   * @retval Returned value can be one of the following values:
03040   *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI
03041   *         @arg @ref LL_MDMA_SRC_BUS_AHB_TCM
03042   * @retval None
03043   */
03044 __STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
03045 {
03046   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03047
03048   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS));
03049 }
03050
03051 /**
03052   * @brief Set Transfer hardware trigger (Request).
03053   * @rmtoll CTBR          TSEL            LL_MDMA_SetHWTrigger
03054   * @param  MDMAx MDMAx Instance
03055   * @param  Channel This parameter can be one of the following values:
03056   *         @arg @ref LL_MDMA_CHANNEL_0
03057   *         @arg @ref LL_MDMA_CHANNEL_1
03058   *         @arg @ref LL_MDMA_CHANNEL_2
03059   *         @arg @ref LL_MDMA_CHANNEL_3
03060   *         @arg @ref LL_MDMA_CHANNEL_4
03061   *         @arg @ref LL_MDMA_CHANNEL_5
03062   *         @arg @ref LL_MDMA_CHANNEL_6
03063   *         @arg @ref LL_MDMA_CHANNEL_7
03064   *         @arg @ref LL_MDMA_CHANNEL_8
03065   *         @arg @ref LL_MDMA_CHANNEL_9
03066   *         @arg @ref LL_MDMA_CHANNEL_10
03067   *         @arg @ref LL_MDMA_CHANNEL_11
03068   *         @arg @ref LL_MDMA_CHANNEL_12
03069   *         @arg @ref LL_MDMA_CHANNEL_13
03070   *         @arg @ref LL_MDMA_CHANNEL_14
03071   *         @arg @ref LL_MDMA_CHANNEL_15
03072   * @param  HWRequest This parameter can be one of the following values:
03073   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM0_TC
03074   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM1_TC
03075   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM2_TC
03076   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM3_TC
03077   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM4_TC
03078   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM5_TC
03079   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM6_TC
03080   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM7_TC
03081   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM0_TC
03082   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM1_TC
03083   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM2_TC
03084   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM3_TC
03085   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM4_TC
03086   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM5_TC
03087   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM6_TC
03088   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM7_TC
03089   *         @arg @ref LL_MDMA_REQ_LTDC_LINE_IT (*)
03090   *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_TH (*)
03091   *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_NF (*)
03092   *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)
03093   *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)
03094   *         @arg @ref LL_MDMA_REQ_JPEG_END_CONVERSION (*)
03095   *         @arg @ref LL_MDMA_REQ_QUADSPI_FIFO_TH (*)
03096   *         @arg @ref LL_MDMA_REQ_QUADSPI_TC (*)
03097   *         @arg @ref LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)
03098   *         @arg @ref LL_MDMA_REQ_OCTOSPI1_TC (*)
03099   *         @arg @ref LL_MDMA_REQ_DMA2D_CLUT_TC
03100   *         @arg @ref LL_MDMA_REQ_DMA2D_TC
03101   *         @arg @ref LL_MDMA_REQ_DMA2D_TW
03102   *         @arg @ref LL_MDMA_REQ_DSI_TEARING_EFFECT (*)
03103   *         @arg @ref LL_MDMA_REQ_DSI_END_REFRESH (*)
03104   *         @arg @ref LL_MDMA_REQ_SDMMC1_END_DATA
03105   *         @arg @ref LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)
03106   *         @arg @ref LL_MDMA_REQ_SDMMC1_COMMAND_END (*)
03107   *         @arg @ref LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)
03108   *         @arg @ref LL_MDMA_REQ_OCTOSPI2_TC (*)
03109   * @note   (*) Availability depends on devices.
03110   * @retval None
03111   */
03112 __STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)
03113 {
03114   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03115
03116   MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL, HWRequest);
03117 }
03118
03119 /**
03120   * @brief Get Transfer hardware trigger (Request).
03121   * @rmtoll CTBR          TSEL            LL_MDMA_GetHWTrigger
03122   * @param  MDMAx MDMAx Instance
03123   * @param  Channel This parameter can be one of the following values:
03124   *         @arg @ref LL_MDMA_CHANNEL_0
03125   *         @arg @ref LL_MDMA_CHANNEL_1
03126   *         @arg @ref LL_MDMA_CHANNEL_2
03127   *         @arg @ref LL_MDMA_CHANNEL_3
03128   *         @arg @ref LL_MDMA_CHANNEL_4
03129   *         @arg @ref LL_MDMA_CHANNEL_5
03130   *         @arg @ref LL_MDMA_CHANNEL_6
03131   *         @arg @ref LL_MDMA_CHANNEL_7
03132   *         @arg @ref LL_MDMA_CHANNEL_8
03133   *         @arg @ref LL_MDMA_CHANNEL_9
03134   *         @arg @ref LL_MDMA_CHANNEL_10
03135   *         @arg @ref LL_MDMA_CHANNEL_11
03136   *         @arg @ref LL_MDMA_CHANNEL_12
03137   *         @arg @ref LL_MDMA_CHANNEL_13
03138   *         @arg @ref LL_MDMA_CHANNEL_14
03139   *         @arg @ref LL_MDMA_CHANNEL_15
03140   * @retval Returned value can be one of the following values:
03141   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM0_TC
03142   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM1_TC
03143   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM2_TC
03144   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM3_TC
03145   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM4_TC
03146   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM5_TC
03147   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM6_TC
03148   *         @arg @ref LL_MDMA_REQ_DMA1_STREAM7_TC
03149   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM0_TC
03150   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM1_TC
03151   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM2_TC
03152   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM3_TC
03153   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM4_TC
03154   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM5_TC
03155   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM6_TC
03156   *         @arg @ref LL_MDMA_REQ_DMA2_STREAM7_TC
03157   *         @arg @ref LL_MDMA_REQ_LTDC_LINE_IT (*)
03158   *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_TH (*)
03159   *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_NF (*)
03160   *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)
03161   *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)
03162   *         @arg @ref LL_MDMA_REQ_JPEG_END_CONVERSION (*)
03163   *         @arg @ref LL_MDMA_REQ_QUADSPI_FIFO_TH (*)
03164   *         @arg @ref LL_MDMA_REQ_QUADSPI_TC (*)
03165   *         @arg @ref LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)
03166   *         @arg @ref LL_MDMA_REQ_OCTOSPI1_TC (*)
03167   *         @arg @ref LL_MDMA_REQ_DMA2D_CLUT_TC
03168   *         @arg @ref LL_MDMA_REQ_DMA2D_TC
03169   *         @arg @ref LL_MDMA_REQ_DMA2D_TW
03170   *         @arg @ref LL_MDMA_REQ_DSI_TEARING_EFFECT (*)
03171   *         @arg @ref LL_MDMA_REQ_DSI_END_REFRESH (*)
03172   *         @arg @ref LL_MDMA_REQ_SDMMC1_END_DATA
03173   *         @arg @ref LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)
03174   *         @arg @ref LL_MDMA_REQ_SDMMC1_COMMAND_END (*)
03175   *         @arg @ref LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)
03176   *         @arg @ref LL_MDMA_REQ_OCTOSPI2_TC (*)
03177   * @note   (*) Availability depends on devices.
03178   * @retval None
03179   */
03180 __STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel)
03181 {
03182   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03183
03184   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL));
03185 }
03186
03187 /**
03188   * @brief Set Mask Address.
03189   * @rmtoll CMAR          MAR            LL_MDMA_SetMaskAddress
03190   * @param  MDMAx MDMAx Instance
03191   * @param  Channel This parameter can be one of the following values:
03192   *         @arg @ref LL_MDMA_CHANNEL_0
03193   *         @arg @ref LL_MDMA_CHANNEL_1
03194   *         @arg @ref LL_MDMA_CHANNEL_2
03195   *         @arg @ref LL_MDMA_CHANNEL_3
03196   *         @arg @ref LL_MDMA_CHANNEL_4
03197   *         @arg @ref LL_MDMA_CHANNEL_5
03198   *         @arg @ref LL_MDMA_CHANNEL_6
03199   *         @arg @ref LL_MDMA_CHANNEL_7
03200   *         @arg @ref LL_MDMA_CHANNEL_8
03201   *         @arg @ref LL_MDMA_CHANNEL_9
03202   *         @arg @ref LL_MDMA_CHANNEL_10
03203   *         @arg @ref LL_MDMA_CHANNEL_11
03204   *         @arg @ref LL_MDMA_CHANNEL_12
03205   *         @arg @ref LL_MDMA_CHANNEL_13
03206   *         @arg @ref LL_MDMA_CHANNEL_14
03207   *         @arg @ref LL_MDMA_CHANNEL_15
03208   * @param  MaskAddress Between 0 to 0xFFFFFFFF
03209   * @retval None
03210   */
03211 __STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)
03212 {
03213   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03214
03215   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR, MaskAddress);
03216 }
03217
03218 /**
03219   * @brief Get Mask Address.
03220   * @rmtoll CMAR          MAR            LL_MDMA_GetMaskAddress
03221   * @param  MDMAx MDMAx Instance
03222   * @param  Channel This parameter can be one of the following values:
03223   *         @arg @ref LL_MDMA_CHANNEL_0
03224   *         @arg @ref LL_MDMA_CHANNEL_1
03225   *         @arg @ref LL_MDMA_CHANNEL_2
03226   *         @arg @ref LL_MDMA_CHANNEL_3
03227   *         @arg @ref LL_MDMA_CHANNEL_4
03228   *         @arg @ref LL_MDMA_CHANNEL_5
03229   *         @arg @ref LL_MDMA_CHANNEL_6
03230   *         @arg @ref LL_MDMA_CHANNEL_7
03231   *         @arg @ref LL_MDMA_CHANNEL_8
03232   *         @arg @ref LL_MDMA_CHANNEL_9
03233   *         @arg @ref LL_MDMA_CHANNEL_10
03234   *         @arg @ref LL_MDMA_CHANNEL_11
03235   *         @arg @ref LL_MDMA_CHANNEL_12
03236   *         @arg @ref LL_MDMA_CHANNEL_13
03237   *         @arg @ref LL_MDMA_CHANNEL_14
03238   *         @arg @ref LL_MDMA_CHANNEL_15
03239   * @retval Between 0 to 0xFFFFFFFF
03240   * @retval None
03241   */
03242 __STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
03243 {
03244   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03245
03246   return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR));
03247 }
03248
03249 /**
03250   * @brief Set Mask Data.
03251   * @rmtoll CMDR          MDR            LL_MDMA_SetMaskData
03252   * @param  MDMAx MDMAx Instance
03253   * @param  Channel This parameter can be one of the following values:
03254   *         @arg @ref LL_MDMA_CHANNEL_0
03255   *         @arg @ref LL_MDMA_CHANNEL_1
03256   *         @arg @ref LL_MDMA_CHANNEL_2
03257   *         @arg @ref LL_MDMA_CHANNEL_3
03258   *         @arg @ref LL_MDMA_CHANNEL_4
03259   *         @arg @ref LL_MDMA_CHANNEL_5
03260   *         @arg @ref LL_MDMA_CHANNEL_6
03261   *         @arg @ref LL_MDMA_CHANNEL_7
03262   *         @arg @ref LL_MDMA_CHANNEL_8
03263   *         @arg @ref LL_MDMA_CHANNEL_9
03264   *         @arg @ref LL_MDMA_CHANNEL_10
03265   *         @arg @ref LL_MDMA_CHANNEL_11
03266   *         @arg @ref LL_MDMA_CHANNEL_12
03267   *         @arg @ref LL_MDMA_CHANNEL_13
03268   *         @arg @ref LL_MDMA_CHANNEL_14
03269   *         @arg @ref LL_MDMA_CHANNEL_15
03270   * @param  MaskData Between 0 to 0xFFFFFFFF
03271   * @retval None
03272   */
03273 __STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)
03274 {
03275   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03276
03277   WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR, MaskData);
03278 }
03279
03280 /**
03281   * @brief Get Mask Data.
03282   * @rmtoll CMDR          MDR            LL_MDMA_GetMaskData
03283   * @param  MDMAx MDMAx Instance
03284   * @param  Channel This parameter can be one of the following values:
03285   *         @arg @ref LL_MDMA_CHANNEL_0
03286   *         @arg @ref LL_MDMA_CHANNEL_1
03287   *         @arg @ref LL_MDMA_CHANNEL_2
03288   *         @arg @ref LL_MDMA_CHANNEL_3
03289   *         @arg @ref LL_MDMA_CHANNEL_4
03290   *         @arg @ref LL_MDMA_CHANNEL_5
03291   *         @arg @ref LL_MDMA_CHANNEL_6
03292   *         @arg @ref LL_MDMA_CHANNEL_7
03293   *         @arg @ref LL_MDMA_CHANNEL_8
03294   *         @arg @ref LL_MDMA_CHANNEL_9
03295   *         @arg @ref LL_MDMA_CHANNEL_10
03296   *         @arg @ref LL_MDMA_CHANNEL_11
03297   *         @arg @ref LL_MDMA_CHANNEL_12
03298   *         @arg @ref LL_MDMA_CHANNEL_13
03299   *         @arg @ref LL_MDMA_CHANNEL_14
03300   *         @arg @ref LL_MDMA_CHANNEL_15
03301   * @retval Between 0 to 0xFFFFFFFF
03302   * @retval None
03303   */
03304 __STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel)
03305 {
03306   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03307
03308   return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR));
03309 }
03310
03311 /**
03312   * @brief Get Transfer Error Direction.
03313   * @rmtoll CESR          TED            LL_MDMA_GetXferErrorDirection
03314   * @param  MDMAx MDMAx Instance
03315   * @param  Channel This parameter can be one of the following values:
03316   *         @arg @ref LL_MDMA_CHANNEL_0
03317   *         @arg @ref LL_MDMA_CHANNEL_1
03318   *         @arg @ref LL_MDMA_CHANNEL_2
03319   *         @arg @ref LL_MDMA_CHANNEL_3
03320   *         @arg @ref LL_MDMA_CHANNEL_4
03321   *         @arg @ref LL_MDMA_CHANNEL_5
03322   *         @arg @ref LL_MDMA_CHANNEL_6
03323   *         @arg @ref LL_MDMA_CHANNEL_7
03324   *         @arg @ref LL_MDMA_CHANNEL_8
03325   *         @arg @ref LL_MDMA_CHANNEL_9
03326   *         @arg @ref LL_MDMA_CHANNEL_10
03327   *         @arg @ref LL_MDMA_CHANNEL_11
03328   *         @arg @ref LL_MDMA_CHANNEL_12
03329   *         @arg @ref LL_MDMA_CHANNEL_13
03330   *         @arg @ref LL_MDMA_CHANNEL_14
03331   *         @arg @ref LL_MDMA_CHANNEL_15
03332   * @retval Returned value can be one of the following values:
03333   *         @arg @ref LL_MDMA_READ_ERROR
03334   *         @arg @ref LL_MDMA_WRITE_ERROR
03335   * @retval None
03336   */
03337 __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel)
03338 {
03339   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03340
03341   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TED));
03342 }
03343
03344 /**
03345   * @brief Get Transfer Error LSB Address.
03346   * @rmtoll CESR          TEA            LL_MDMA_GetXferErrorLSBAddress
03347   * @param  MDMAx MDMAx Instance
03348   * @param  Channel This parameter can be one of the following values:
03349   *         @arg @ref LL_MDMA_CHANNEL_0
03350   *         @arg @ref LL_MDMA_CHANNEL_1
03351   *         @arg @ref LL_MDMA_CHANNEL_2
03352   *         @arg @ref LL_MDMA_CHANNEL_3
03353   *         @arg @ref LL_MDMA_CHANNEL_4
03354   *         @arg @ref LL_MDMA_CHANNEL_5
03355   *         @arg @ref LL_MDMA_CHANNEL_6
03356   *         @arg @ref LL_MDMA_CHANNEL_7
03357   *         @arg @ref LL_MDMA_CHANNEL_8
03358   *         @arg @ref LL_MDMA_CHANNEL_9
03359   *         @arg @ref LL_MDMA_CHANNEL_10
03360   *         @arg @ref LL_MDMA_CHANNEL_11
03361   *         @arg @ref LL_MDMA_CHANNEL_12
03362   *         @arg @ref LL_MDMA_CHANNEL_13
03363   *         @arg @ref LL_MDMA_CHANNEL_14
03364   *         @arg @ref LL_MDMA_CHANNEL_15
03365   * @retval Between 0 to 0x0000007F
03366   * @retval None
03367   */
03368 __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
03369 {
03370   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03371
03372   return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEA));
03373 }
03374
03375 /**
03376   * @}
03377   */
03378
03379 /** @defgroup MDMA_LL_EF_FLAG_Management FLAG_Management
03380   * @{
03381   */
03382
03383 /**
03384   * @brief Get MDMA Channel x Global Interrupt flag.
03385   * @rmtoll GISR0  GIFx    LL_MDMA_IsActiveFlag_GI
03386   * @param  MDMAx MDMAx Instance
03387   * @param  Channel This parameter can be one of the following values:
03388   *         @arg @ref LL_MDMA_CHANNEL_0
03389   *         @arg @ref LL_MDMA_CHANNEL_1
03390   *         @arg @ref LL_MDMA_CHANNEL_2
03391   *         @arg @ref LL_MDMA_CHANNEL_3
03392   *         @arg @ref LL_MDMA_CHANNEL_4
03393   *         @arg @ref LL_MDMA_CHANNEL_5
03394   *         @arg @ref LL_MDMA_CHANNEL_6
03395   *         @arg @ref LL_MDMA_CHANNEL_7
03396   *         @arg @ref LL_MDMA_CHANNEL_8
03397   *         @arg @ref LL_MDMA_CHANNEL_9
03398   *         @arg @ref LL_MDMA_CHANNEL_10
03399   *         @arg @ref LL_MDMA_CHANNEL_11
03400   *         @arg @ref LL_MDMA_CHANNEL_12
03401   *         @arg @ref LL_MDMA_CHANNEL_13
03402   *         @arg @ref LL_MDMA_CHANNEL_14
03403   *         @arg @ref LL_MDMA_CHANNEL_15
03404   * @retval State of bit (1 or 0).
03405   */
03406 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel)
03407 {
03408   return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
03409 }
03410
03411 /**
03412   * @brief Get MDMA Channel x Transfer Error interrupt flag.
03413   * @rmtoll CISR  TEIF    LL_MDMA_IsActiveFlag_TE
03414   * @param  MDMAx MDMAx Instance
03415   * @param  Channel This parameter can be one of the following values:
03416   *         @arg @ref LL_MDMA_CHANNEL_0
03417   *         @arg @ref LL_MDMA_CHANNEL_1
03418   *         @arg @ref LL_MDMA_CHANNEL_2
03419   *         @arg @ref LL_MDMA_CHANNEL_3
03420   *         @arg @ref LL_MDMA_CHANNEL_4
03421   *         @arg @ref LL_MDMA_CHANNEL_5
03422   *         @arg @ref LL_MDMA_CHANNEL_6
03423   *         @arg @ref LL_MDMA_CHANNEL_7
03424   *         @arg @ref LL_MDMA_CHANNEL_8
03425   *         @arg @ref LL_MDMA_CHANNEL_9
03426   *         @arg @ref LL_MDMA_CHANNEL_10
03427   *         @arg @ref LL_MDMA_CHANNEL_11
03428   *         @arg @ref LL_MDMA_CHANNEL_12
03429   *         @arg @ref LL_MDMA_CHANNEL_13
03430   *         @arg @ref LL_MDMA_CHANNEL_14
03431   *         @arg @ref LL_MDMA_CHANNEL_15
03432   * @retval State of bit (1 or 0).
03433   */
03434 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
03435 {
03436   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03437
03438   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TEIF) == (MDMA_CISR_TEIF)) ? 1UL : 0UL);
03439 }
03440
03441 /**
03442   * @brief Get MDMA Channel x Channel Transfer Complete interrupt flag.
03443   * @rmtoll CISR  CTCIF    LL_MDMA_IsActiveFlag_CTC
03444   * @param  MDMAx MDMAx Instance
03445   * @param  Channel This parameter can be one of the following values:
03446   *         @arg @ref LL_MDMA_CHANNEL_0
03447   *         @arg @ref LL_MDMA_CHANNEL_1
03448   *         @arg @ref LL_MDMA_CHANNEL_2
03449   *         @arg @ref LL_MDMA_CHANNEL_3
03450   *         @arg @ref LL_MDMA_CHANNEL_4
03451   *         @arg @ref LL_MDMA_CHANNEL_5
03452   *         @arg @ref LL_MDMA_CHANNEL_6
03453   *         @arg @ref LL_MDMA_CHANNEL_7
03454   *         @arg @ref LL_MDMA_CHANNEL_8
03455   *         @arg @ref LL_MDMA_CHANNEL_9
03456   *         @arg @ref LL_MDMA_CHANNEL_10
03457   *         @arg @ref LL_MDMA_CHANNEL_11
03458   *         @arg @ref LL_MDMA_CHANNEL_12
03459   *         @arg @ref LL_MDMA_CHANNEL_13
03460   *         @arg @ref LL_MDMA_CHANNEL_14
03461   *         @arg @ref LL_MDMA_CHANNEL_15
03462   * @retval State of bit (1 or 0).
03463   */
03464 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
03465 {
03466   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03467
03468   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CTCIF) == (MDMA_CISR_CTCIF)) ? 1UL : 0UL);
03469 }
03470
03471 /**
03472   * @brief Get MDMA Channel x Block Repeat Transfer complete interrupt flag.
03473   * @rmtoll CISR  BRTIF    LL_MDMA_IsActiveFlag_BRT
03474   * @param  MDMAx MDMAx Instance
03475   * @param  Channel This parameter can be one of the following values:
03476   *         @arg @ref LL_MDMA_CHANNEL_0
03477   *         @arg @ref LL_MDMA_CHANNEL_1
03478   *         @arg @ref LL_MDMA_CHANNEL_2
03479   *         @arg @ref LL_MDMA_CHANNEL_3
03480   *         @arg @ref LL_MDMA_CHANNEL_4
03481   *         @arg @ref LL_MDMA_CHANNEL_5
03482   *         @arg @ref LL_MDMA_CHANNEL_6
03483   *         @arg @ref LL_MDMA_CHANNEL_7
03484   *         @arg @ref LL_MDMA_CHANNEL_8
03485   *         @arg @ref LL_MDMA_CHANNEL_9
03486   *         @arg @ref LL_MDMA_CHANNEL_10
03487   *         @arg @ref LL_MDMA_CHANNEL_11
03488   *         @arg @ref LL_MDMA_CHANNEL_12
03489   *         @arg @ref LL_MDMA_CHANNEL_13
03490   *         @arg @ref LL_MDMA_CHANNEL_14
03491   *         @arg @ref LL_MDMA_CHANNEL_15
03492   * @retval State of bit (1 or 0).
03493   */
03494 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03495 {
03496   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03497
03498   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BRTIF) == (MDMA_CISR_BRTIF)) ? 1UL : 0UL);
03499 }
03500
03501 /**
03502   * @brief Get MDMA Channel x Block Transfer complete interrupt flag.
03503   * @rmtoll CISR  BTIF    LL_MDMA_IsActiveFlag_BT
03504   * @param  MDMAx MDMAx Instance
03505   * @param  Channel This parameter can be one of the following values:
03506   *         @arg @ref LL_MDMA_CHANNEL_0
03507   *         @arg @ref LL_MDMA_CHANNEL_1
03508   *         @arg @ref LL_MDMA_CHANNEL_2
03509   *         @arg @ref LL_MDMA_CHANNEL_3
03510   *         @arg @ref LL_MDMA_CHANNEL_4
03511   *         @arg @ref LL_MDMA_CHANNEL_5
03512   *         @arg @ref LL_MDMA_CHANNEL_6
03513   *         @arg @ref LL_MDMA_CHANNEL_7
03514   *         @arg @ref LL_MDMA_CHANNEL_8
03515   *         @arg @ref LL_MDMA_CHANNEL_9
03516   *         @arg @ref LL_MDMA_CHANNEL_10
03517   *         @arg @ref LL_MDMA_CHANNEL_11
03518   *         @arg @ref LL_MDMA_CHANNEL_12
03519   *         @arg @ref LL_MDMA_CHANNEL_13
03520   *         @arg @ref LL_MDMA_CHANNEL_14
03521   *         @arg @ref LL_MDMA_CHANNEL_15
03522   * @retval State of bit (1 or 0).
03523   */
03524 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03525 {
03526   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03527
03528   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BTIF) == (MDMA_CISR_BTIF)) ? 1UL : 0UL);
03529 }
03530
03531 /**
03532   * @brief Get MDMA Channel x buffer transfer complete interrupt flag.
03533   * @rmtoll CISR  TCIF    LL_MDMA_IsActiveFlag_TC
03534   * @param  MDMAx MDMAx Instance
03535   * @param  Channel This parameter can be one of the following values:
03536   *         @arg @ref LL_MDMA_CHANNEL_0
03537   *         @arg @ref LL_MDMA_CHANNEL_1
03538   *         @arg @ref LL_MDMA_CHANNEL_2
03539   *         @arg @ref LL_MDMA_CHANNEL_3
03540   *         @arg @ref LL_MDMA_CHANNEL_4
03541   *         @arg @ref LL_MDMA_CHANNEL_5
03542   *         @arg @ref LL_MDMA_CHANNEL_6
03543   *         @arg @ref LL_MDMA_CHANNEL_7
03544   *         @arg @ref LL_MDMA_CHANNEL_8
03545   *         @arg @ref LL_MDMA_CHANNEL_9
03546   *         @arg @ref LL_MDMA_CHANNEL_10
03547   *         @arg @ref LL_MDMA_CHANNEL_11
03548   *         @arg @ref LL_MDMA_CHANNEL_12
03549   *         @arg @ref LL_MDMA_CHANNEL_13
03550   *         @arg @ref LL_MDMA_CHANNEL_14
03551   *         @arg @ref LL_MDMA_CHANNEL_15
03552   * @retval State of bit (1 or 0).
03553   */
03554 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
03555 {
03556   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03557
03558   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TCIF) == (MDMA_CISR_TCIF)) ? 1UL : 0UL);
03559 }
03560
03561 /**
03562   * @brief Get MDMA Channel x ReQuest Active flag.
03563   * @rmtoll CISR  CRQA    LL_MDMA_IsActiveFlag_CRQA
03564   * @param  MDMAx MDMAx Instance
03565   * @param  Channel This parameter can be one of the following values:
03566   *         @arg @ref LL_MDMA_CHANNEL_0
03567   *         @arg @ref LL_MDMA_CHANNEL_1
03568   *         @arg @ref LL_MDMA_CHANNEL_2
03569   *         @arg @ref LL_MDMA_CHANNEL_3
03570   *         @arg @ref LL_MDMA_CHANNEL_4
03571   *         @arg @ref LL_MDMA_CHANNEL_5
03572   *         @arg @ref LL_MDMA_CHANNEL_6
03573   *         @arg @ref LL_MDMA_CHANNEL_7
03574   *         @arg @ref LL_MDMA_CHANNEL_8
03575   *         @arg @ref LL_MDMA_CHANNEL_9
03576   *         @arg @ref LL_MDMA_CHANNEL_10
03577   *         @arg @ref LL_MDMA_CHANNEL_11
03578   *         @arg @ref LL_MDMA_CHANNEL_12
03579   *         @arg @ref LL_MDMA_CHANNEL_13
03580   *         @arg @ref LL_MDMA_CHANNEL_14
03581   *         @arg @ref LL_MDMA_CHANNEL_15
03582   * @retval State of bit (1 or 0).
03583   */
03584 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel)
03585 {
03586   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03587
03588   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CRQA) == (MDMA_CISR_CRQA)) ? 1UL : 0UL);
03589 }
03590
03591 /**
03592   * @brief Get MDMA Channel x Block Size Error flag.
03593   * @rmtoll CESR  BSE    LL_MDMA_IsActiveFlag_BSE
03594   * @param  MDMAx MDMAx Instance
03595   * @param  Channel This parameter can be one of the following values:
03596   *         @arg @ref LL_MDMA_CHANNEL_0
03597   *         @arg @ref LL_MDMA_CHANNEL_1
03598   *         @arg @ref LL_MDMA_CHANNEL_2
03599   *         @arg @ref LL_MDMA_CHANNEL_3
03600   *         @arg @ref LL_MDMA_CHANNEL_4
03601   *         @arg @ref LL_MDMA_CHANNEL_5
03602   *         @arg @ref LL_MDMA_CHANNEL_6
03603   *         @arg @ref LL_MDMA_CHANNEL_7
03604   *         @arg @ref LL_MDMA_CHANNEL_8
03605   *         @arg @ref LL_MDMA_CHANNEL_9
03606   *         @arg @ref LL_MDMA_CHANNEL_10
03607   *         @arg @ref LL_MDMA_CHANNEL_11
03608   *         @arg @ref LL_MDMA_CHANNEL_12
03609   *         @arg @ref LL_MDMA_CHANNEL_13
03610   *         @arg @ref LL_MDMA_CHANNEL_14
03611   *         @arg @ref LL_MDMA_CHANNEL_15
03612   * @retval State of bit (1 or 0).
03613   */
03614 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel)
03615 {
03616   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03617
03618   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_BSE) == (MDMA_CESR_BSE)) ? 1UL : 0UL);
03619 }
03620
03621 /**
03622   * @brief Get MDMA Channel x Address/Size Error flag.
03623   * @rmtoll CESR  ASE    LL_MDMA_IsActiveFlag_ASE
03624   * @param  MDMAx MDMAx Instance
03625   * @param  Channel This parameter can be one of the following values:
03626   *         @arg @ref LL_MDMA_CHANNEL_0
03627   *         @arg @ref LL_MDMA_CHANNEL_1
03628   *         @arg @ref LL_MDMA_CHANNEL_2
03629   *         @arg @ref LL_MDMA_CHANNEL_3
03630   *         @arg @ref LL_MDMA_CHANNEL_4
03631   *         @arg @ref LL_MDMA_CHANNEL_5
03632   *         @arg @ref LL_MDMA_CHANNEL_6
03633   *         @arg @ref LL_MDMA_CHANNEL_7
03634   *         @arg @ref LL_MDMA_CHANNEL_8
03635   *         @arg @ref LL_MDMA_CHANNEL_9
03636   *         @arg @ref LL_MDMA_CHANNEL_10
03637   *         @arg @ref LL_MDMA_CHANNEL_11
03638   *         @arg @ref LL_MDMA_CHANNEL_12
03639   *         @arg @ref LL_MDMA_CHANNEL_13
03640   *         @arg @ref LL_MDMA_CHANNEL_14
03641   *         @arg @ref LL_MDMA_CHANNEL_15
03642   * @retval State of bit (1 or 0).
03643   */
03644 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel)
03645 {
03646   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03647
03648   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_ASE) == (MDMA_CESR_ASE)) ? 1UL : 0UL);
03649 }
03650
03651 /**
03652   * @brief Get MDMA Channel x Transfer Error Mask Data flag.
03653   * @rmtoll CESR  TEMD    LL_MDMA_IsActiveFlag_TEMD
03654   * @param  MDMAx MDMAx Instance
03655   * @param  Channel This parameter can be one of the following values:
03656   *         @arg @ref LL_MDMA_CHANNEL_0
03657   *         @arg @ref LL_MDMA_CHANNEL_1
03658   *         @arg @ref LL_MDMA_CHANNEL_2
03659   *         @arg @ref LL_MDMA_CHANNEL_3
03660   *         @arg @ref LL_MDMA_CHANNEL_4
03661   *         @arg @ref LL_MDMA_CHANNEL_5
03662   *         @arg @ref LL_MDMA_CHANNEL_6
03663   *         @arg @ref LL_MDMA_CHANNEL_7
03664   *         @arg @ref LL_MDMA_CHANNEL_8
03665   *         @arg @ref LL_MDMA_CHANNEL_9
03666   *         @arg @ref LL_MDMA_CHANNEL_10
03667   *         @arg @ref LL_MDMA_CHANNEL_11
03668   *         @arg @ref LL_MDMA_CHANNEL_12
03669   *         @arg @ref LL_MDMA_CHANNEL_13
03670   *         @arg @ref LL_MDMA_CHANNEL_14
03671   *         @arg @ref LL_MDMA_CHANNEL_15
03672   * @retval State of bit (1 or 0).
03673   */
03674 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel)
03675 {
03676   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03677
03678   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEMD) == (MDMA_CESR_TEMD)) ? 1UL : 0UL);
03679 }
03680
03681 /**
03682   * @brief Get MDMA Channel x Transfer Error Link Data flag.
03683   * @rmtoll CESR  TELD    LL_MDMA_IsActiveFlag_TELD
03684   * @param  MDMAx MDMAx Instance
03685   * @param  Channel This parameter can be one of the following values:
03686   *         @arg @ref LL_MDMA_CHANNEL_0
03687   *         @arg @ref LL_MDMA_CHANNEL_1
03688   *         @arg @ref LL_MDMA_CHANNEL_2
03689   *         @arg @ref LL_MDMA_CHANNEL_3
03690   *         @arg @ref LL_MDMA_CHANNEL_4
03691   *         @arg @ref LL_MDMA_CHANNEL_5
03692   *         @arg @ref LL_MDMA_CHANNEL_6
03693   *         @arg @ref LL_MDMA_CHANNEL_7
03694   *         @arg @ref LL_MDMA_CHANNEL_8
03695   *         @arg @ref LL_MDMA_CHANNEL_9
03696   *         @arg @ref LL_MDMA_CHANNEL_10
03697   *         @arg @ref LL_MDMA_CHANNEL_11
03698   *         @arg @ref LL_MDMA_CHANNEL_12
03699   *         @arg @ref LL_MDMA_CHANNEL_13
03700   *         @arg @ref LL_MDMA_CHANNEL_14
03701   *         @arg @ref LL_MDMA_CHANNEL_15
03702   * @retval State of bit (1 or 0).
03703   */
03704 __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel)
03705 {
03706   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03707
03708   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TELD) == (MDMA_CESR_TELD)) ? 1UL : 0UL);
03709 }
03710
03711 /**
03712   * @brief Clear MDMA Channel x Transfer Error interrupt flag.
03713   * @rmtoll CIFCR  CTEIF    LL_MDMA_ClearFlag_TE
03714   * @param  MDMAx MDMAx Instance
03715   * @param  Channel This parameter can be one of the following values:
03716   *         @arg @ref LL_MDMA_CHANNEL_0
03717   *         @arg @ref LL_MDMA_CHANNEL_1
03718   *         @arg @ref LL_MDMA_CHANNEL_2
03719   *         @arg @ref LL_MDMA_CHANNEL_3
03720   *         @arg @ref LL_MDMA_CHANNEL_4
03721   *         @arg @ref LL_MDMA_CHANNEL_5
03722   *         @arg @ref LL_MDMA_CHANNEL_6
03723   *         @arg @ref LL_MDMA_CHANNEL_7
03724   *         @arg @ref LL_MDMA_CHANNEL_8
03725   *         @arg @ref LL_MDMA_CHANNEL_9
03726   *         @arg @ref LL_MDMA_CHANNEL_10
03727   *         @arg @ref LL_MDMA_CHANNEL_11
03728   *         @arg @ref LL_MDMA_CHANNEL_12
03729   *         @arg @ref LL_MDMA_CHANNEL_13
03730   *         @arg @ref LL_MDMA_CHANNEL_14
03731   *         @arg @ref LL_MDMA_CHANNEL_15
03732   * @retval None
03733   */
03734 __STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
03735 {
03736   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03737
03738   WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CTEIF);
03739 }
03740
03741 /**
03742   * @brief Clear MDMA Channel x Channel Transfer Complete interrupt flag.
03743   * @rmtoll CIFCR  CCTCIF    LL_MDMA_ClearFlag_CTC
03744   * @param  MDMAx MDMAx Instance
03745   * @param  Channel This parameter can be one of the following values:
03746   *         @arg @ref LL_MDMA_CHANNEL_0
03747   *         @arg @ref LL_MDMA_CHANNEL_1
03748   *         @arg @ref LL_MDMA_CHANNEL_2
03749   *         @arg @ref LL_MDMA_CHANNEL_3
03750   *         @arg @ref LL_MDMA_CHANNEL_4
03751   *         @arg @ref LL_MDMA_CHANNEL_5
03752   *         @arg @ref LL_MDMA_CHANNEL_6
03753   *         @arg @ref LL_MDMA_CHANNEL_7
03754   *         @arg @ref LL_MDMA_CHANNEL_8
03755   *         @arg @ref LL_MDMA_CHANNEL_9
03756   *         @arg @ref LL_MDMA_CHANNEL_10
03757   *         @arg @ref LL_MDMA_CHANNEL_11
03758   *         @arg @ref LL_MDMA_CHANNEL_12
03759   *         @arg @ref LL_MDMA_CHANNEL_13
03760   *         @arg @ref LL_MDMA_CHANNEL_14
03761   *         @arg @ref LL_MDMA_CHANNEL_15
03762   * @retval None
03763   */
03764 __STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
03765 {
03766   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03767
03768   WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CCTCIF);
03769 }
03770
03771 /**
03772   * @brief Clear MDMA Channel x Block Repeat Transfer complete interrupt flag.
03773   * @rmtoll CIFCR  CBRTIF    LL_MDMA_ClearFlag_BRT
03774   * @param  MDMAx MDMAx Instance
03775   * @param  Channel This parameter can be one of the following values:
03776   *         @arg @ref LL_MDMA_CHANNEL_0
03777   *         @arg @ref LL_MDMA_CHANNEL_1
03778   *         @arg @ref LL_MDMA_CHANNEL_2
03779   *         @arg @ref LL_MDMA_CHANNEL_3
03780   *         @arg @ref LL_MDMA_CHANNEL_4
03781   *         @arg @ref LL_MDMA_CHANNEL_5
03782   *         @arg @ref LL_MDMA_CHANNEL_6
03783   *         @arg @ref LL_MDMA_CHANNEL_7
03784   *         @arg @ref LL_MDMA_CHANNEL_8
03785   *         @arg @ref LL_MDMA_CHANNEL_9
03786   *         @arg @ref LL_MDMA_CHANNEL_10
03787   *         @arg @ref LL_MDMA_CHANNEL_11
03788   *         @arg @ref LL_MDMA_CHANNEL_12
03789   *         @arg @ref LL_MDMA_CHANNEL_13
03790   *         @arg @ref LL_MDMA_CHANNEL_14
03791   *         @arg @ref LL_MDMA_CHANNEL_15
03792   * @retval None
03793   */
03794 __STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03795 {
03796   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03797
03798   WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBRTIF);
03799 }
03800
03801 /**
03802   * @brief Clear MDMA Channel x Block Transfer complete interrupt flag.
03803   * @rmtoll CIFCR  CBTIF    LL_MDMA_ClearFlag_BT
03804   * @param  MDMAx MDMAx Instance
03805   * @param  Channel This parameter can be one of the following values:
03806   *         @arg @ref LL_MDMA_CHANNEL_0
03807   *         @arg @ref LL_MDMA_CHANNEL_1
03808   *         @arg @ref LL_MDMA_CHANNEL_2
03809   *         @arg @ref LL_MDMA_CHANNEL_3
03810   *         @arg @ref LL_MDMA_CHANNEL_4
03811   *         @arg @ref LL_MDMA_CHANNEL_5
03812   *         @arg @ref LL_MDMA_CHANNEL_6
03813   *         @arg @ref LL_MDMA_CHANNEL_7
03814   *         @arg @ref LL_MDMA_CHANNEL_8
03815   *         @arg @ref LL_MDMA_CHANNEL_9
03816   *         @arg @ref LL_MDMA_CHANNEL_10
03817   *         @arg @ref LL_MDMA_CHANNEL_11
03818   *         @arg @ref LL_MDMA_CHANNEL_12
03819   *         @arg @ref LL_MDMA_CHANNEL_13
03820   *         @arg @ref LL_MDMA_CHANNEL_14
03821   *         @arg @ref LL_MDMA_CHANNEL_15
03822   * @retval None
03823   */
03824 __STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03825 {
03826   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03827
03828   WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBTIF);
03829 }
03830
03831 /**
03832   * @brief Clear MDMA Channel x buffer transfer Complete Interrupt Flag.
03833   * @rmtoll CIFCR  CLTCIF    LL_MDMA_ClearFlag_TC
03834   * @param  MDMAx MDMAx Instance
03835   * @param  Channel This parameter can be one of the following values:
03836   *         @arg @ref LL_MDMA_CHANNEL_0
03837   *         @arg @ref LL_MDMA_CHANNEL_1
03838   *         @arg @ref LL_MDMA_CHANNEL_2
03839   *         @arg @ref LL_MDMA_CHANNEL_3
03840   *         @arg @ref LL_MDMA_CHANNEL_4
03841   *         @arg @ref LL_MDMA_CHANNEL_5
03842   *         @arg @ref LL_MDMA_CHANNEL_6
03843   *         @arg @ref LL_MDMA_CHANNEL_7
03844   *         @arg @ref LL_MDMA_CHANNEL_8
03845   *         @arg @ref LL_MDMA_CHANNEL_9
03846   *         @arg @ref LL_MDMA_CHANNEL_10
03847   *         @arg @ref LL_MDMA_CHANNEL_11
03848   *         @arg @ref LL_MDMA_CHANNEL_12
03849   *         @arg @ref LL_MDMA_CHANNEL_13
03850   *         @arg @ref LL_MDMA_CHANNEL_14
03851   *         @arg @ref LL_MDMA_CHANNEL_15
03852   * @retval None
03853   */
03854 __STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
03855 {
03856   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03857
03858   WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CLTCIF);
03859 }
03860
03861 /**
03862   * @}
03863   */
03864
03865 /** @defgroup MDMA_LL_EF_IT_Management IT_Management
03866   * @{
03867   */
03868
03869 /**
03870   * @brief Enable MDMA Channel x Transfer Error interrupt.
03871   * @rmtoll CCR  TEIE    LL_MDMA_EnableIT_TE
03872   * @param  MDMAx MDMAx Instance
03873   * @param  Channel This parameter can be one of the following values:
03874   *         @arg @ref LL_MDMA_CHANNEL_0
03875   *         @arg @ref LL_MDMA_CHANNEL_1
03876   *         @arg @ref LL_MDMA_CHANNEL_2
03877   *         @arg @ref LL_MDMA_CHANNEL_3
03878   *         @arg @ref LL_MDMA_CHANNEL_4
03879   *         @arg @ref LL_MDMA_CHANNEL_5
03880   *         @arg @ref LL_MDMA_CHANNEL_6
03881   *         @arg @ref LL_MDMA_CHANNEL_7
03882   *         @arg @ref LL_MDMA_CHANNEL_8
03883   *         @arg @ref LL_MDMA_CHANNEL_9
03884   *         @arg @ref LL_MDMA_CHANNEL_10
03885   *         @arg @ref LL_MDMA_CHANNEL_11
03886   *         @arg @ref LL_MDMA_CHANNEL_12
03887   *         @arg @ref LL_MDMA_CHANNEL_13
03888   *         @arg @ref LL_MDMA_CHANNEL_14
03889   *         @arg @ref LL_MDMA_CHANNEL_15
03890   * @retval None
03891   */
03892 __STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
03893 {
03894   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03895
03896   SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
03897 }
03898
03899 /**
03900   * @brief Enable MDMA Channel x Channel Transfer Complete interrupt.
03901   * @rmtoll CCR  CTCIE    LL_MDMA_EnableIT_CTC
03902   * @param  MDMAx MDMAx Instance
03903   * @param  Channel This parameter can be one of the following values:
03904   *         @arg @ref LL_MDMA_CHANNEL_0
03905   *         @arg @ref LL_MDMA_CHANNEL_1
03906   *         @arg @ref LL_MDMA_CHANNEL_2
03907   *         @arg @ref LL_MDMA_CHANNEL_3
03908   *         @arg @ref LL_MDMA_CHANNEL_4
03909   *         @arg @ref LL_MDMA_CHANNEL_5
03910   *         @arg @ref LL_MDMA_CHANNEL_6
03911   *         @arg @ref LL_MDMA_CHANNEL_7
03912   *         @arg @ref LL_MDMA_CHANNEL_8
03913   *         @arg @ref LL_MDMA_CHANNEL_9
03914   *         @arg @ref LL_MDMA_CHANNEL_10
03915   *         @arg @ref LL_MDMA_CHANNEL_11
03916   *         @arg @ref LL_MDMA_CHANNEL_12
03917   *         @arg @ref LL_MDMA_CHANNEL_13
03918   *         @arg @ref LL_MDMA_CHANNEL_14
03919   *         @arg @ref LL_MDMA_CHANNEL_15
03920   * @retval None
03921   */
03922 __STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
03923 {
03924   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03925
03926   SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
03927 }
03928
03929 /**
03930   * @brief Enable MDMA Channel x Block Repeat Transfer interrupt.
03931   * @rmtoll CCR  BRTIE    LL_MDMA_EnableIT_BRT
03932   * @param  MDMAx MDMAx Instance
03933   * @param  Channel This parameter can be one of the following values:
03934   *         @arg @ref LL_MDMA_CHANNEL_0
03935   *         @arg @ref LL_MDMA_CHANNEL_1
03936   *         @arg @ref LL_MDMA_CHANNEL_2
03937   *         @arg @ref LL_MDMA_CHANNEL_3
03938   *         @arg @ref LL_MDMA_CHANNEL_4
03939   *         @arg @ref LL_MDMA_CHANNEL_5
03940   *         @arg @ref LL_MDMA_CHANNEL_6
03941   *         @arg @ref LL_MDMA_CHANNEL_7
03942   *         @arg @ref LL_MDMA_CHANNEL_8
03943   *         @arg @ref LL_MDMA_CHANNEL_9
03944   *         @arg @ref LL_MDMA_CHANNEL_10
03945   *         @arg @ref LL_MDMA_CHANNEL_11
03946   *         @arg @ref LL_MDMA_CHANNEL_12
03947   *         @arg @ref LL_MDMA_CHANNEL_13
03948   *         @arg @ref LL_MDMA_CHANNEL_14
03949   *         @arg @ref LL_MDMA_CHANNEL_15
03950   * @retval None
03951   */
03952 __STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03953 {
03954   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03955
03956   SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
03957 }
03958
03959 /**
03960   * @brief Enable MDMA Channel x Block Transfer interrupt.
03961   * @rmtoll CCR  BTIE    LL_MDMA_EnableIT_BT
03962   * @param  MDMAx MDMAx Instance
03963   * @param  Channel This parameter can be one of the following values:
03964   *         @arg @ref LL_MDMA_CHANNEL_0
03965   *         @arg @ref LL_MDMA_CHANNEL_1
03966   *         @arg @ref LL_MDMA_CHANNEL_2
03967   *         @arg @ref LL_MDMA_CHANNEL_3
03968   *         @arg @ref LL_MDMA_CHANNEL_4
03969   *         @arg @ref LL_MDMA_CHANNEL_5
03970   *         @arg @ref LL_MDMA_CHANNEL_6
03971   *         @arg @ref LL_MDMA_CHANNEL_7
03972   *         @arg @ref LL_MDMA_CHANNEL_8
03973   *         @arg @ref LL_MDMA_CHANNEL_9
03974   *         @arg @ref LL_MDMA_CHANNEL_10
03975   *         @arg @ref LL_MDMA_CHANNEL_11
03976   *         @arg @ref LL_MDMA_CHANNEL_12
03977   *         @arg @ref LL_MDMA_CHANNEL_13
03978   *         @arg @ref LL_MDMA_CHANNEL_14
03979   *         @arg @ref LL_MDMA_CHANNEL_15
03980   * @retval None
03981   */
03982 __STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
03983 {
03984   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
03985
03986   SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
03987 }
03988
03989 /**
03990   * @brief Enable MDMA Channel x buffer transfer complete interrupt.
03991   * @rmtoll CCR  TCIE    LL_MDMA_EnableIT_TC
03992   * @param  MDMAx MDMAx Instance
03993   * @param  Channel This parameter can be one of the following values:
03994   *         @arg @ref LL_MDMA_CHANNEL_0
03995   *         @arg @ref LL_MDMA_CHANNEL_1
03996   *         @arg @ref LL_MDMA_CHANNEL_2
03997   *         @arg @ref LL_MDMA_CHANNEL_3
03998   *         @arg @ref LL_MDMA_CHANNEL_4
03999   *         @arg @ref LL_MDMA_CHANNEL_5
04000   *         @arg @ref LL_MDMA_CHANNEL_6
04001   *         @arg @ref LL_MDMA_CHANNEL_7
04002   *         @arg @ref LL_MDMA_CHANNEL_8
04003   *         @arg @ref LL_MDMA_CHANNEL_9
04004   *         @arg @ref LL_MDMA_CHANNEL_10
04005   *         @arg @ref LL_MDMA_CHANNEL_11
04006   *         @arg @ref LL_MDMA_CHANNEL_12
04007   *         @arg @ref LL_MDMA_CHANNEL_13
04008   *         @arg @ref LL_MDMA_CHANNEL_14
04009   *         @arg @ref LL_MDMA_CHANNEL_15
04010   * @retval None
04011   */
04012 __STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
04013 {
04014   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04015
04016   SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
04017 }
04018
04019 /**
04020   * @brief Disable MDMA Channel x Transfer Error interrupt.
04021   * @rmtoll CCR  TEIE    LL_MDMA_DisableIT_TE
04022   * @param  MDMAx MDMAx Instance
04023   * @param  Channel This parameter can be one of the following values:
04024   *         @arg @ref LL_MDMA_CHANNEL_0
04025   *         @arg @ref LL_MDMA_CHANNEL_1
04026   *         @arg @ref LL_MDMA_CHANNEL_2
04027   *         @arg @ref LL_MDMA_CHANNEL_3
04028   *         @arg @ref LL_MDMA_CHANNEL_4
04029   *         @arg @ref LL_MDMA_CHANNEL_5
04030   *         @arg @ref LL_MDMA_CHANNEL_6
04031   *         @arg @ref LL_MDMA_CHANNEL_7
04032   *         @arg @ref LL_MDMA_CHANNEL_8
04033   *         @arg @ref LL_MDMA_CHANNEL_9
04034   *         @arg @ref LL_MDMA_CHANNEL_10
04035   *         @arg @ref LL_MDMA_CHANNEL_11
04036   *         @arg @ref LL_MDMA_CHANNEL_12
04037   *         @arg @ref LL_MDMA_CHANNEL_13
04038   *         @arg @ref LL_MDMA_CHANNEL_14
04039   *         @arg @ref LL_MDMA_CHANNEL_15
04040   * @retval None
04041   */
04042 __STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
04043 {
04044   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04045
04046   CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
04047 }
04048
04049 /**
04050   * @brief Disable MDMA Channel x Channel Transfer Complete interrupt.
04051   * @rmtoll CCR  CTCIE    LL_MDMA_DisableIT_CTC
04052   * @param  MDMAx MDMAx Instance
04053   * @param  Channel This parameter can be one of the following values:
04054   *         @arg @ref LL_MDMA_CHANNEL_0
04055   *         @arg @ref LL_MDMA_CHANNEL_1
04056   *         @arg @ref LL_MDMA_CHANNEL_2
04057   *         @arg @ref LL_MDMA_CHANNEL_3
04058   *         @arg @ref LL_MDMA_CHANNEL_4
04059   *         @arg @ref LL_MDMA_CHANNEL_5
04060   *         @arg @ref LL_MDMA_CHANNEL_6
04061   *         @arg @ref LL_MDMA_CHANNEL_7
04062   *         @arg @ref LL_MDMA_CHANNEL_8
04063   *         @arg @ref LL_MDMA_CHANNEL_9
04064   *         @arg @ref LL_MDMA_CHANNEL_10
04065   *         @arg @ref LL_MDMA_CHANNEL_11
04066   *         @arg @ref LL_MDMA_CHANNEL_12
04067   *         @arg @ref LL_MDMA_CHANNEL_13
04068   *         @arg @ref LL_MDMA_CHANNEL_14
04069   *         @arg @ref LL_MDMA_CHANNEL_15
04070   * @retval None
04071   */
04072 __STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
04073 {
04074   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04075
04076   CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
04077 }
04078
04079 /**
04080   * @brief Disable MDMA Channel x Block Repeat Transfer interrupt.
04081   * @rmtoll CCR  BRTIE    LL_MDMA_DisableIT_BRT
04082   * @param  MDMAx MDMAx Instance
04083   * @param  Channel This parameter can be one of the following values:
04084   *         @arg @ref LL_MDMA_CHANNEL_0
04085   *         @arg @ref LL_MDMA_CHANNEL_1
04086   *         @arg @ref LL_MDMA_CHANNEL_2
04087   *         @arg @ref LL_MDMA_CHANNEL_3
04088   *         @arg @ref LL_MDMA_CHANNEL_4
04089   *         @arg @ref LL_MDMA_CHANNEL_5
04090   *         @arg @ref LL_MDMA_CHANNEL_6
04091   *         @arg @ref LL_MDMA_CHANNEL_7
04092   *         @arg @ref LL_MDMA_CHANNEL_8
04093   *         @arg @ref LL_MDMA_CHANNEL_9
04094   *         @arg @ref LL_MDMA_CHANNEL_10
04095   *         @arg @ref LL_MDMA_CHANNEL_11
04096   *         @arg @ref LL_MDMA_CHANNEL_12
04097   *         @arg @ref LL_MDMA_CHANNEL_13
04098   *         @arg @ref LL_MDMA_CHANNEL_14
04099   *         @arg @ref LL_MDMA_CHANNEL_15
04100   * @retval None
04101   */
04102 __STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
04103 {
04104   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04105
04106   CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
04107 }
04108
04109 /**
04110   * @brief Disable MDMA Channel x Block Transfer interrupt.
04111   * @rmtoll CCR  BTIE    LL_MDMA_DisableIT_BT
04112   * @param  MDMAx MDMAx Instance
04113   * @param  Channel This parameter can be one of the following values:
04114   *         @arg @ref LL_MDMA_CHANNEL_0
04115   *         @arg @ref LL_MDMA_CHANNEL_1
04116   *         @arg @ref LL_MDMA_CHANNEL_2
04117   *         @arg @ref LL_MDMA_CHANNEL_3
04118   *         @arg @ref LL_MDMA_CHANNEL_4
04119   *         @arg @ref LL_MDMA_CHANNEL_5
04120   *         @arg @ref LL_MDMA_CHANNEL_6
04121   *         @arg @ref LL_MDMA_CHANNEL_7
04122   *         @arg @ref LL_MDMA_CHANNEL_8
04123   *         @arg @ref LL_MDMA_CHANNEL_9
04124   *         @arg @ref LL_MDMA_CHANNEL_10
04125   *         @arg @ref LL_MDMA_CHANNEL_11
04126   *         @arg @ref LL_MDMA_CHANNEL_12
04127   *         @arg @ref LL_MDMA_CHANNEL_13
04128   *         @arg @ref LL_MDMA_CHANNEL_14
04129   *         @arg @ref LL_MDMA_CHANNEL_15
04130   * @retval None
04131   */
04132 __STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
04133 {
04134   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04135
04136   CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
04137 }
04138
04139 /**
04140   * @brief Disable MDMA Channel x buffer transfer complete interrupt.
04141   * @rmtoll CCR  TCIE    LL_MDMA_DisableIT_TC
04142   * @param  MDMAx MDMAx Instance
04143   * @param  Channel This parameter can be one of the following values:
04144   *         @arg @ref LL_MDMA_CHANNEL_0
04145   *         @arg @ref LL_MDMA_CHANNEL_1
04146   *         @arg @ref LL_MDMA_CHANNEL_2
04147   *         @arg @ref LL_MDMA_CHANNEL_3
04148   *         @arg @ref LL_MDMA_CHANNEL_4
04149   *         @arg @ref LL_MDMA_CHANNEL_5
04150   *         @arg @ref LL_MDMA_CHANNEL_6
04151   *         @arg @ref LL_MDMA_CHANNEL_7
04152   *         @arg @ref LL_MDMA_CHANNEL_8
04153   *         @arg @ref LL_MDMA_CHANNEL_9
04154   *         @arg @ref LL_MDMA_CHANNEL_10
04155   *         @arg @ref LL_MDMA_CHANNEL_11
04156   *         @arg @ref LL_MDMA_CHANNEL_12
04157   *         @arg @ref LL_MDMA_CHANNEL_13
04158   *         @arg @ref LL_MDMA_CHANNEL_14
04159   *         @arg @ref LL_MDMA_CHANNEL_15
04160   * @retval None
04161   */
04162 __STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
04163 {
04164   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04165
04166   CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
04167 }
04168
04169 /**
04170   * @brief Check if MDMA Channel x Transfer Error interrupt is enabled.
04171   * @rmtoll CCR  TEIE    LL_MDMA_IsEnabledIT_TE
04172   * @param  MDMAx MDMAx Instance
04173   * @param  Channel This parameter can be one of the following values:
04174   *         @arg @ref LL_MDMA_CHANNEL_0
04175   *         @arg @ref LL_MDMA_CHANNEL_1
04176   *         @arg @ref LL_MDMA_CHANNEL_2
04177   *         @arg @ref LL_MDMA_CHANNEL_3
04178   *         @arg @ref LL_MDMA_CHANNEL_4
04179   *         @arg @ref LL_MDMA_CHANNEL_5
04180   *         @arg @ref LL_MDMA_CHANNEL_6
04181   *         @arg @ref LL_MDMA_CHANNEL_7
04182   *         @arg @ref LL_MDMA_CHANNEL_8
04183   *         @arg @ref LL_MDMA_CHANNEL_9
04184   *         @arg @ref LL_MDMA_CHANNEL_10
04185   *         @arg @ref LL_MDMA_CHANNEL_11
04186   *         @arg @ref LL_MDMA_CHANNEL_12
04187   *         @arg @ref LL_MDMA_CHANNEL_13
04188   *         @arg @ref LL_MDMA_CHANNEL_14
04189   *         @arg @ref LL_MDMA_CHANNEL_15
04190   * @retval State of bit (1 or 0).
04191   */
04192 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
04193 {
04194   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04195
04196   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE) == MDMA_CCR_TEIE) ? 1UL : 0UL);
04197 }
04198
04199 /**
04200   * @brief Check if MDMA Channel x Channel Transfer Complete interrupt is enabled.
04201   * @rmtoll CCR  CTCIE    LL_MDMA_IsEnabledIT_CTC
04202   * @param  MDMAx MDMAx Instance
04203   * @param  Channel This parameter can be one of the following values:
04204   *         @arg @ref LL_MDMA_CHANNEL_0
04205   *         @arg @ref LL_MDMA_CHANNEL_1
04206   *         @arg @ref LL_MDMA_CHANNEL_2
04207   *         @arg @ref LL_MDMA_CHANNEL_3
04208   *         @arg @ref LL_MDMA_CHANNEL_4
04209   *         @arg @ref LL_MDMA_CHANNEL_5
04210   *         @arg @ref LL_MDMA_CHANNEL_6
04211   *         @arg @ref LL_MDMA_CHANNEL_7
04212   *         @arg @ref LL_MDMA_CHANNEL_8
04213   *         @arg @ref LL_MDMA_CHANNEL_9
04214   *         @arg @ref LL_MDMA_CHANNEL_10
04215   *         @arg @ref LL_MDMA_CHANNEL_11
04216   *         @arg @ref LL_MDMA_CHANNEL_12
04217   *         @arg @ref LL_MDMA_CHANNEL_13
04218   *         @arg @ref LL_MDMA_CHANNEL_14
04219   *         @arg @ref LL_MDMA_CHANNEL_15
04220   * @retval State of bit (1 or 0).
04221   */
04222 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
04223 {
04224   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04225
04226   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE) == MDMA_CCR_CTCIE) ? 1UL : 0UL);
04227 }
04228
04229 /**
04230   * @brief Check if MDMA Channel x Block Repeat Transfer complete interrupt is enabled.
04231   * @rmtoll CCR  BRTIE    LL_MDMA_IsEnabledIT_BRT
04232   * @param  MDMAx MDMAx Instance
04233   * @param  Channel This parameter can be one of the following values:
04234   *         @arg @ref LL_MDMA_CHANNEL_0
04235   *         @arg @ref LL_MDMA_CHANNEL_1
04236   *         @arg @ref LL_MDMA_CHANNEL_2
04237   *         @arg @ref LL_MDMA_CHANNEL_3
04238   *         @arg @ref LL_MDMA_CHANNEL_4
04239   *         @arg @ref LL_MDMA_CHANNEL_5
04240   *         @arg @ref LL_MDMA_CHANNEL_6
04241   *         @arg @ref LL_MDMA_CHANNEL_7
04242   *         @arg @ref LL_MDMA_CHANNEL_8
04243   *         @arg @ref LL_MDMA_CHANNEL_9
04244   *         @arg @ref LL_MDMA_CHANNEL_10
04245   *         @arg @ref LL_MDMA_CHANNEL_11
04246   *         @arg @ref LL_MDMA_CHANNEL_12
04247   *         @arg @ref LL_MDMA_CHANNEL_13
04248   *         @arg @ref LL_MDMA_CHANNEL_14
04249   *         @arg @ref LL_MDMA_CHANNEL_15
04250   * @retval State of bit (1 or 0).
04251   */
04252 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
04253 {
04254   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04255
04256   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE) == MDMA_CCR_BRTIE) ? 1UL : 0UL);
04257 }
04258
04259 /**
04260   * @brief Check if MDMA Channel x Block Transfer interrupt is enabled.
04261   * @rmtoll CCR  BTIE    LL_MDMA_IsEnabledIT_BT
04262   * @param  MDMAx MDMAx Instance
04263   * @param  Channel This parameter can be one of the following values:
04264   *         @arg @ref LL_MDMA_CHANNEL_0
04265   *         @arg @ref LL_MDMA_CHANNEL_1
04266   *         @arg @ref LL_MDMA_CHANNEL_2
04267   *         @arg @ref LL_MDMA_CHANNEL_3
04268   *         @arg @ref LL_MDMA_CHANNEL_4
04269   *         @arg @ref LL_MDMA_CHANNEL_5
04270   *         @arg @ref LL_MDMA_CHANNEL_6
04271   *         @arg @ref LL_MDMA_CHANNEL_7
04272   *         @arg @ref LL_MDMA_CHANNEL_8
04273   *         @arg @ref LL_MDMA_CHANNEL_9
04274   *         @arg @ref LL_MDMA_CHANNEL_10
04275   *         @arg @ref LL_MDMA_CHANNEL_11
04276   *         @arg @ref LL_MDMA_CHANNEL_12
04277   *         @arg @ref LL_MDMA_CHANNEL_13
04278   *         @arg @ref LL_MDMA_CHANNEL_14
04279   *         @arg @ref LL_MDMA_CHANNEL_15
04280   * @retval State of bit (1 or 0).
04281   */
04282 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
04283 {
04284   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04285
04286   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE) == MDMA_CCR_BTIE) ? 1UL : 0UL);
04287 }
04288
04289 /**
04290   * @brief Check if MDMA Channel x buffer transfer complete interrupt is enabled.
04291   * @rmtoll CCR  TCIE    LL_MDMA_IsEnabledIT_TC
04292   * @param  MDMAx MDMAx Instance
04293   * @param  Channel This parameter can be one of the following values:
04294   *         @arg @ref LL_MDMA_CHANNEL_0
04295   *         @arg @ref LL_MDMA_CHANNEL_1
04296   *         @arg @ref LL_MDMA_CHANNEL_2
04297   *         @arg @ref LL_MDMA_CHANNEL_3
04298   *         @arg @ref LL_MDMA_CHANNEL_4
04299   *         @arg @ref LL_MDMA_CHANNEL_5
04300   *         @arg @ref LL_MDMA_CHANNEL_6
04301   *         @arg @ref LL_MDMA_CHANNEL_7
04302   *         @arg @ref LL_MDMA_CHANNEL_8
04303   *         @arg @ref LL_MDMA_CHANNEL_9
04304   *         @arg @ref LL_MDMA_CHANNEL_10
04305   *         @arg @ref LL_MDMA_CHANNEL_11
04306   *         @arg @ref LL_MDMA_CHANNEL_12
04307   *         @arg @ref LL_MDMA_CHANNEL_13
04308   *         @arg @ref LL_MDMA_CHANNEL_14
04309   *         @arg @ref LL_MDMA_CHANNEL_15
04310   * @retval State of bit (1 or 0).
04311   */
04312 __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
04313 {
04314   register uint32_t mdma_base_addr = (uint32_t)MDMAx;
04315
04316   return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE) == MDMA_CCR_TCIE) ? 1UL : 0UL);
04317 }
04318
04319 /**
04320   * @}
04321   */
04322
04323 #if defined(USE_FULL_LL_DRIVER)
04324 /** @defgroup MDMA_LL_EF_Init Initialization and de-initialization functions
04325   * @{
04326   */
04327
04328 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct);
04329 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel);
04330 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct);
04331 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode);
04332 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode);
04333 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode);
04334
04335 /**
04336   * @}
04337   */
04338 #endif /* USE_FULL_LL_DRIVER */
04339
04340 /**
04341   * @}
04342   */
04343
04344 /**
04345   * @}
04346   */
04347
04348 #endif /* MDMA */
04349
04350 /**
04351   * @}
04352   */
04353
04354 #ifdef __cplusplus
04355 }
04356 #endif
04357
04358 #endif /* STM32H7xx_LL_MDMA_H */
04359
04360 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_opamp.c Source File

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stm32h7xx_ll_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_opamp.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025   #include "stm32_assert.h"
00026 #else
00027   #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (OPAMP1) || defined (OPAMP2)
00035 /** @addtogroup OPAMP_LL OPAMP
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /** @addtogroup OPAMP_LL_Private_Macros
00045   * @{
00046   */
00047
00048 /* Check of parameters for configuration of OPAMP hierarchical scope:         */
00049 /* OPAMP instance.                                                            */
00050
00051 #define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)                                 \
00052   (   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
00053    || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_HIGHSPEED))
00054
00055 #define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
00056   (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
00057    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
00058    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
00059    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0)                         \
00060    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_BIAS)                    \
00061    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_IO1_BIAS)                \
00062   )
00063
00064 #if defined(DAC2)
00065 #define IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)                 \
00066   (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
00067    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC)               \
00068    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC2)              \
00069   )
00070 #else
00071 #define IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)                 \
00072   (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
00073    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC)               \
00074   )
00075 #endif /* DAC2 */
00076
00077
00078 #define IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)                       \
00079   (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
00080    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
00081    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
00082   )
00083
00084 /**
00085   * @}
00086   */
00087
00088
00089 /* Private function prototypes -----------------------------------------------*/
00090
00091 /* Exported functions --------------------------------------------------------*/
00092 /** @addtogroup OPAMP_LL_Exported_Functions
00093   * @{
00094   */
00095
00096 /** @addtogroup OPAMP_LL_EF_Init
00097   * @{
00098   */
00099
00100 /**
00101   * @brief  De-initialize registers of the selected OPAMP instance
00102   *         to their default reset values.
00103   * @note   If comparator is locked, de-initialization by software is
00104   *         not possible.
00105   *         The only way to unlock the comparator is a device hardware reset.
00106   * @param  OPAMPx OPAMP instance
00107   * @retval An ErrorStatus enumeration value:
00108   *          - SUCCESS: OPAMP registers are de-initialized
00109   *          - ERROR: OPAMP registers are not de-initialized
00110   */
00111 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
00112 {
00113   ErrorStatus status = SUCCESS;
00114
00115   /* Check the parameters */
00116   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00117
00118   LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
00119
00120   return status;
00121 }
00122
00123 /**
00124   * @brief  Initialize some features of OPAMP instance.
00125   * @note   This function reset bit of calibration mode to ensure
00126   *         to be in functional mode, in order to have OPAMP parameters
00127   *         (inputs selection, ...) set with the corresponding OPAMP mode
00128   *         to be effective.
00129   * @param  OPAMPx OPAMP instance
00130   * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
00131   * @retval An ErrorStatus enumeration value:
00132   *          - SUCCESS: OPAMP registers are initialized
00133   *          - ERROR: OPAMP registers are not initialized
00134   */
00135 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00136 {
00137   ErrorStatus status = SUCCESS;
00138
00139   /* Check the parameters */
00140   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00141   assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
00142   assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
00143   assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMP_InitStruct->InputNonInverting));
00144
00145   /* Note: OPAMP inverting input can be used with OPAMP in mode standalone    */
00146   /*       or PGA with external capacitors for filtering circuit.             */
00147   /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
00148   /*       not used (not connected to GPIO pin).                              */
00149   if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00150   {
00151     assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMP_InitStruct->InputInverting));
00152   }
00153
00154   /* Configuration of OPAMP instance :                                      */
00155   /*  - PowerMode                                                           */
00156   /*  - Functional mode                                                     */
00157   /*  - Input non-inverting                                                 */
00158   /*  - Input inverting                                                     */
00159   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode.    */
00160   if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00161   {
00162     MODIFY_REG(OPAMPx->CSR,
00163                  OPAMP_CSR_OPAHSM
00164                | OPAMP_CSR_CALON
00165                | OPAMP_CSR_VMSEL
00166                | OPAMP_CSR_VPSEL
00167                | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1
00168               ,
00169                  (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
00170                | OPAMP_InitStruct->FunctionalMode
00171                | OPAMP_InitStruct->InputNonInverting
00172                | OPAMP_InitStruct->InputInverting
00173               );
00174   }
00175   else
00176   {
00177     MODIFY_REG(OPAMPx->CSR,
00178                  OPAMP_CSR_OPAHSM
00179                | OPAMP_CSR_CALON
00180                | OPAMP_CSR_VMSEL
00181                | OPAMP_CSR_VPSEL
00182                | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1
00183               ,
00184                 (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
00185                | LL_OPAMP_MODE_FOLLOWER
00186                | OPAMP_InitStruct->InputNonInverting
00187               );
00188   }
00189
00190   return status;
00191 }
00192
00193 /**
00194   * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
00195   * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
00196   *                         whose fields will be set to default values.
00197   * @retval None
00198   */
00199 void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00200 {
00201   /* Set OPAMP_InitStruct fields to default values */
00202   OPAMP_InitStruct->PowerMode         = LL_OPAMP_POWERMODE_NORMAL;
00203   OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
00204   OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
00205   /* Note: Parameter discarded if OPAMP in functional mode follower,          */
00206   /*       set anyway to its default value.                                   */
00207   OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
00208 }
00209
00210 /**
00211   * @}
00212   */
00213
00214 /**
00215   * @}
00216   */
00217
00218 /**
00219   * @}
00220   */
00221
00222 #endif /* OPAMP1 || OPAMP2 */
00223
00224 /**
00225   * @}
00226   */
00227
00228 #endif /* USE_FULL_LL_DRIVER */
00229
00230 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_opamp.h Source File

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stm32h7xx_ll_opamp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_LL_OPAMP_H
00022 #define __STM32H7xx_LL_OPAMP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (OPAMP1) || defined (OPAMP2)
00036
00037 /** @defgroup OPAMP_LL OPAMP
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
00046   * @{
00047   */
00048
00049 /* Internal mask for OPAMP power mode:                                        */
00050 /* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for:         */
00051 /* - OPAMP power mode into control register                                   */
00052 /* - OPAMP trimming register offset                                           */
00053
00054 /* Internal register offset for OPAMP trimming configuration */
00055 #define OPAMP_POWERMODE_OTR_REGOFFSET       0x00000000U
00056 #define OPAMP_POWERMODE_HSOTR_REGOFFSET     0x00000001U
00057 #define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_HSOTR_REGOFFSET)
00058
00059 /* Mask for OPAMP power mode into control register */
00060 #define OPAMP_POWERMODE_CSR_BIT_MASK        (OPAMP_CSR_OPAHSM)
00061
00062 /* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
00063 /* or PMOS.                                                                   */
00064 /* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
00065 /* - OPAMP trimming selection of transistors differential pair                */
00066 /* - OPAMP trimming values of transistors differential pair                   */
00067 #define OPAMP_TRIMMING_SELECT_MASK          0x00030000U
00068 #define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
00069
00070 /**
00071   * @}
00072   */
00073
00074
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Driver macro reserved for internal use: set a pointer to
00082   *         a register from a register basis from which an offset
00083   *         is applied.
00084   * @param  __REG__ Register basis from which the offset is applied.
00085   * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
00086   * @retval Register address
00087 */
00088 #define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
00089  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
00090
00091
00092
00093 /**
00094   * @}
00095   */
00096
00097
00098 /* Exported types ------------------------------------------------------------*/
00099 #if defined(USE_FULL_LL_DRIVER)
00100 /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  Structure definition of some features of OPAMP instance.
00106   */
00107 typedef struct
00108 {
00109   uint32_t PowerMode;                   /*!< Set OPAMP power mode.
00110                                              This parameter can be a value of @ref OPAMP_LL_EC_POWER_MODE
00111
00112                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
00113
00114
00115   uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
00116                                              This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
00117                                              @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
00118
00119                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
00120
00121   uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
00122                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
00123
00124                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
00125
00126   uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
00127                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
00128                                              @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
00129
00130                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
00131
00132 } LL_OPAMP_InitTypeDef;
00133
00134 /**
00135   * @}
00136   */
00137 #endif /* USE_FULL_LL_DRIVER */
00138
00139 /* Exported constants --------------------------------------------------------*/
00140 /** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
00141   * @{
00142   */
00143
00144 /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
00145   * @{
00146   */
00147 #define LL_OPAMP_MODE_FUNCTIONAL        0x00000000U                               /*!< OPAMP functional mode */
00148 #define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_CALON)                           /*!< OPAMP calibration mode */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
00154   * @{
00155   */
00156 #define LL_OPAMP_MODE_STANDALONE        0x00000000U                                                 /*!< OPAMP functional mode, OPAMP operation in standalone */
00157 #define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)                       /*!< OPAMP functional mode, OPAMP operation in follower */
00158 #define LL_OPAMP_MODE_PGA               (OPAMP_CSR_VMSEL_1)                                           /*!< OPAMP functional mode, OPAMP operation in PGA */
00159 #define LL_OPAMP_MODE_PGA_IO0           (OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
00160 #define LL_OPAMP_MODE_PGA_IO0_BIAS      (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0
00161                                                                                                           - Input signal on VINM0, bias on VINPx: negative gain
00162                                                                                                           - Bias on VINM0, input signal on VINPx: positive gain */
00163 #define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS  (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)    /*!< In PGA mode, the inverting input is connected to VINM0
00164                                                                                                           - Input signal on VINM0, bias on VINPx: negative gain
00165                                                                                                           - Bias on VINM0, input signal on VINPx: positive gain
00166                                                                                                           And VINM1 is connected too for filtering */
00167
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
00173   * @note Gain sign:
00174   *         - is positive if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
00175   *           @ref LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0
00176   *         - may be positive or negative if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
00177   *           @ref LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00178   *       see @ref OPAMP_LL_EC_FUNCTIONAL_MODE for more details
00179   * @{
00180   */
00181 #define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1             0x00000000U                                                    /*!< OPAMP PGA gain 2  or -1  */
00182 #define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3             (                                          OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4  or -3  */
00183 #define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7             (                     OPAMP_CSR_PGGAIN_1                     ) /*!< OPAMP PGA gain 8  or -7  */
00184 #define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15           (                     OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 16 or -15 */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
00190   * @{
00191   */
00192 #define LL_OPAMP_INPUT_NONINVERT_IO0         0x00000000U           /*!< OPAMP non inverting input connected to I/O VINP0
00193                                                                         (PB0  for OPAMP1, PE9  for OPAMP2)
00194                                                                         Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00195 #define LL_OPAMP_INPUT_NONINVERT_DAC         OPAMP_CSR_VPSEL_0     /*!< OPAMP non inverting input connected internally to DAC channel
00196                                                                         (DAC1_CH1 for OPAMP1, DAC1_CH2  for OPAMP2)
00197                                                                         Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00198 #if defined(DAC2)
00199 #define LL_OPAMP_INPUT_NONINVERT_DAC2        OPAMP_CSR_VPSEL_1     /*!< OPAMP non inverting input connected internally to DAC2 channel
00200                                                                         (DAC3 only for OPAMP2)*/
00201 #endif /* DAC2 */
00202
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
00208   * @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.
00209   *       Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
00210   * @{
00211   */
00212 #define LL_OPAMP_INPUT_INVERT_IO0         0x00000000U              /*!< OPAMP inverting input connected to I/O VINM0
00213                                                                         (PC5  for OPAMP1, PE8  for OPAMP2)
00214                                                                         Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00215 #define LL_OPAMP_INPUT_INVERT_IO1         OPAMP_CSR_VMSEL_0        /*!< OPAMP inverting input connected to I/0 VINM1
00216                                                                         (PA7  for OPAMP1, PG1  for OPAMP2)
00217                                                                         Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00218 #define LL_OPAMP_INPUT_INVERT_CONNECT_NO  OPAMP_CSR_VMSEL_1        /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias).
00219                                                                         Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
00220 /**
00221   * @}
00222   */
00223
00224
00225
00226 /** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode
00227   * @{
00228   */
00229 #define LL_OPAMP_POWERMODE_NORMAL        (OPAMP_POWERMODE_OTR_REGOFFSET)                            /*!< OPAMP output in normal mode */
00230 #define LL_OPAMP_POWERMODE_HIGHSPEED     (OPAMP_POWERMODE_HSOTR_REGOFFSET | OPAMP_CSR_OPAHSM)       /*!< OPAMP output in highspeed mode */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
00236   * @{
00237   */
00238 #define LL_OPAMP_TRIMMING_FACTORY       0x00000000U             /*!< OPAMP trimming factors set to factory values */
00239 #define LL_OPAMP_TRIMMING_USER          OPAMP_CSR_USERTRIM      /*!< OPAMP trimming factors set to user values */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
00245   * @{
00246   */
00247 #define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA  (OPAMP_OTR_TRIMOFFSETN | ((OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) << 4)) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00248 #define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA  (OPAMP_OTR_TRIMOFFSETN                      | (OPAMP_CSR_CALSEL_1 << 4))   /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
00249 #define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA  (OPAMP_OTR_TRIMOFFSETP                      | (OPAMP_CSR_CALSEL_0 << 4))   /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00250 #define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_OTR_TRIMOFFSETP                                          )          /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
00251 #define LL_OPAMP_TRIMMING_NMOS                 (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)                                    /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00252 #define LL_OPAMP_TRIMMING_PMOS                 (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)                                    /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
00258   * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
00259   *         not timeout values.
00260   *         For details on delays values, refer to descriptions in source code
00261   *         above each literal definition.
00262   * @{
00263   */
00264
00265 /* Delay for OPAMP startup time (transition from state disable to enable).    */
00266 /* Note: OPAMP startup time depends on board application environment:         */
00267 /*       impedance connected to OPAMP output.                                 */
00268 /*       The delay below is specified under conditions:                       */
00269 /*        - OPAMP in functional mode follower                                 */
00270 /*        - load impedance of 4kOhm (min), 50pF (max)                         */
00271 /* Literal set to maximum value (refer to device datasheet,                   */
00272 /* parameter "tWAKEUP").                                                      */
00273 /* Unit: us                                                                   */
00274 #define LL_OPAMP_DELAY_STARTUP_US         (3U)  /*!< Delay for OPAMP startup time */
00275 /**
00276   * @}
00277   */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported macro ------------------------------------------------------------*/
00284 /** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
00285   * @{
00286   */
00287 /** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
00288   * @{
00289   */
00290 /**
00291   * @brief  Write a value in OPAMP LL_OPAMP_GetPowerModeregister
00292   * @param  __INSTANCE__ OPAMP Instance
00293   * @param  __REG__ Register to be written
00294   * @param  __VALUE__ Value to be written in the register
00295   * @retval None
00296   */
00297 #define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00298
00299 /**
00300   * @brief  Read a value in OPAMP register
00301   * @param  __INSTANCE__ OPAMP Instance
00302   * @param  __REG__ Register to be read
00303   * @retval Register value
00304   */
00305 #define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00306 /**
00307   * @}
00308   */
00309 /** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro
00310   * @{
00311   */
00312
00313 /**
00314   * @brief  Helper macro to select the OPAMP common instance
00315   *         to which is belonging the selected OPAMP instance.
00316   * @note   OPAMP common register instance can be used to
00317   *         set parameters common to several OPAMP instances.
00318   *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
00319   * @param  __OPAMPx__ OPAMP instance
00320   * @retval OPAMP common instance
00321   */
00322 #if defined(OPAMP1) && defined(OPAMP2)
00323 #define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
00324   (OPAMP12_COMMON)
00325 #endif
00326
00327 /**
00328   * @brief  Helper macro to check if all OPAMP instances sharing the same
00329   *         OPAMP common instance are disabled.
00330   * @note   This check is required by functions with setting conditioned to
00331   *         OPAMP state:
00332   *         All OPAMP instances of the OPAMP common group must be disabled.
00333   *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
00334   * @retval 0: All OPAMP instances sharing the same OPAMP common instance
00335   *            are disabled.
00336   *         1: At least one OPAMP instance sharing the same OPAMP common instance
00337   *            is enabled
00338   */
00339 #if defined(OPAMP1) && defined(OPAMP2)
00340 #define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
00341   (LL_OPAMP_IsEnabled(OPAMP1) |                                                \
00342    LL_OPAMP_IsEnabled(OPAMP2)  )
00343 #endif
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352
00353 /* Exported functions --------------------------------------------------------*/
00354 /** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
00355   * @{
00356   */
00357
00358 /** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
00359   * @{
00360   */
00361
00362 /**
00363   * @brief  Set OPAMP mode calibration or functional.
00364   * @note   OPAMP mode corresponds to functional or calibration mode:
00365   *          - functional mode: OPAMP operation in standalone, follower, ...
00366   *            Set functional mode using function
00367   *            @ref LL_OPAMP_SetFunctionalMode().
00368   *          - calibration mode: offset calibration of the selected
00369   *            transistors differential pair NMOS or PMOS.
00370   * @rmtoll CSR      CALON          LL_OPAMP_SetMode
00371   * @param  OPAMPx OPAMP instance
00372   * @param  Mode This parameter can be one of the following values:
00373   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00374   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00375   * @retval None
00376   */
00377 __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
00378 {
00379   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
00380 }
00381
00382 /**
00383   * @brief  Get OPAMP mode calibration or functional.
00384   * @note   OPAMP mode corresponds to functional or calibration mode:
00385   *          - functional mode: OPAMP operation in standalone, follower, ...
00386   *            Set functional mode using function
00387   *            @ref LL_OPAMP_SetFunctionalMode().
00388   *          - calibration mode: offset calibration of the selected
00389   *            transistors differential pair NMOS or PMOS.
00390   * @rmtoll CSR      CALON          LL_OPAMP_GetMode
00391   * @param  OPAMPx OPAMP instance
00392   * @retval Returned value can be one of the following values:
00393   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00394   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00395   */
00396 __STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
00397 {
00398   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
00399 }
00400
00401 /**
00402   * @brief  Set OPAMP functional mode by setting internal connections.
00403   *         OPAMP operation in standalone, follower, ...
00404   * @note   This function reset bit of calibration mode to ensure
00405   *         to be in functional mode, in order to have OPAMP parameters
00406   *         (inputs selection, ...) set with the corresponding OPAMP mode
00407   *         to be effective.
00408   * @rmtoll CSR      VMSEL          LL_OPAMP_SetFunctionalMode
00409   * @param  OPAMPx OPAMP instance
00410   * @param  FunctionalMode This parameter can be one of the following values:
00411   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00412   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00413   *         @arg @ref LL_OPAMP_MODE_PGA
00414   *         @arg @ref LL_OPAMP_MODE_PGA_IO0
00415   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
00416   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
00420 {
00421   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
00422   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
00423 }
00424
00425 /**
00426   * @brief  Get OPAMP functional mode from setting of internal connections.
00427   *         OPAMP operation in standalone, follower, ...
00428   * @rmtoll CSR      VMSEL          LL_OPAMP_GetFunctionalMode
00429   * @param  OPAMPx OPAMP instance
00430   * @retval Returned value can be one of the following values:
00431   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00432   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00433   *         @arg @ref LL_OPAMP_MODE_PGA
00434   *         @arg @ref LL_OPAMP_MODE_PGA_IO0
00435   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
00436   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00437   */
00438 __STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
00439 {
00440   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
00441 }
00442
00443 /**
00444   * @brief  Set OPAMP PGA gain.
00445   * @note   Preliminarily, OPAMP must be set in mode PGA
00446   *         using function @ref LL_OPAMP_SetFunctionalMode().
00447   * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain
00448   * @param  OPAMPx OPAMP instance
00449   * @param  PGAGain This parameter can be one of the following values:
00450   *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
00451   *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
00452   *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
00453   *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
00454   * @retval None
00455   */
00456 __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
00457 {
00458   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
00459 }
00460
00461 /**
00462   * @brief  Get OPAMP PGA gain.
00463   * @note   Preliminarily, OPAMP must be set in mode PGA
00464   *         using function @ref LL_OPAMP_SetFunctionalMode().
00465   * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain
00466   * @param  OPAMPx OPAMP instance
00467   * @retval Returned value can be one of the following values:
00468   *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
00469   *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
00470   *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
00471   *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
00472   */
00473 __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
00474 {
00475   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
00476 }
00477
00478 /**
00479   * @brief  Set OPAMP power mode normal or highspeed.
00480   * @note   OPAMP highspeed mode allows output stage to have a better slew rate.
00481   * @rmtoll CSR      OPAHSM     LL_OPAMP_SetPowerMode
00482   * @param  OPAMPx OPAMP instance
00483   * @param  PowerMode This parameter can be one of the following values:
00484   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00485   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00486   * @retval None
00487   */
00488 __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
00489 {
00490   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAHSM, (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK));
00491 }
00492
00493 /**
00494   * @brief  Get OPAMP power mode normal or highspeed.
00495   * @note   OPAMP highspeed mode allows output stage to have a better slew rate.
00496   * @rmtoll CSR      OPAHSM     LL_OPAMP_GetPowerMode
00497   * @param  OPAMPx OPAMP instance
00498   * @retval Returned value can be one of the following values:
00499   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00500   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00501   */
00502 __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
00503 {
00504   register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM));
00505
00506   return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPAHSM_Pos)));
00507 }
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
00513   * @{
00514   */
00515
00516 /**
00517   * @brief  Set OPAMP non-inverting input connection.
00518   * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting
00519   * @param  OPAMPx OPAMP instance
00520   * @param  InputNonInverting This parameter can be one of the following values:
00521   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00522   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
00523   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00527 {
00528   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
00529 }
00530
00531 /**
00532   * @brief  Get OPAMP non-inverting input connection.
00533   * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting
00534   * @param  OPAMPx OPAMP instance
00535   * @retval Returned value can be one of the following values:
00536   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00537   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
00538   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)
00539   */
00540 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
00541 {
00542   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
00543 }
00544
00545 /**
00546   * @brief  Set OPAMP inverting input connection.
00547   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00548   *         or PGA with external capacitors for filtering circuit.
00549   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00550   *         is not used (not connected to GPIO pin).
00551   * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting
00552   * @param  OPAMPx OPAMP instance
00553   * @param  InputInverting This parameter can be one of the following values:
00554   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00555   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00556   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00557   * @retval None
00558   */
00559 __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00560 {
00561   /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11)      */
00562   /* to not modify OPAMP mode follower or PGA.                                */
00563   /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
00564   MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
00565 }
00566
00567 /**
00568   * @brief  Get OPAMP inverting input connection.
00569   * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting
00570   * @param  OPAMPx OPAMP instance
00571   * @retval Returned value can be one of the following values:
00572   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00573   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00574   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00575   */
00576 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
00577 {
00578   register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
00579
00580   /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting     */
00581   /* input not connected.                                                     */
00582   return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
00583 }
00584
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
00590   * @{
00591   */
00592
00593 /**
00594   * @brief  Set OPAMP trimming mode.
00595   * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode
00596   * @param  OPAMPx OPAMP instance
00597   * @param  TrimmingMode This parameter can be one of the following values:
00598   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00599   *         @arg @ref LL_OPAMP_TRIMMING_USER
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
00603 {
00604   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
00605 }
00606
00607 /**
00608   * @brief  Get OPAMP trimming mode.
00609   * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode
00610   * @param  OPAMPx OPAMP instance
00611   * @retval Returned value can be one of the following values:
00612   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00613   *         @arg @ref LL_OPAMP_TRIMMING_USER
00614   */
00615 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
00616 {
00617   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
00618 }
00619
00620 /**
00621   * @brief  Set OPAMP offset to calibrate the selected transistors
00622   *         differential pair NMOS or PMOS.
00623   * @note   Preliminarily, OPAMP must be set in mode calibration
00624   *         using function @ref LL_OPAMP_SetMode().
00625   * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection
00626   * @param  OPAMPx OPAMP instance
00627   * @param  TransistorsDiffPair This parameter can be one of the following values:
00628   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00629   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00630   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00631   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00632   *
00633   *         (1) Default parameters to be used for calibration
00634   *             using two trimming steps (one with each transistors differential
00635   *             pair NMOS and PMOS)
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
00639 {
00640   /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
00641   /* containing other bits reserved for other purpose.                        */
00642   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, ((TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK) >> 4));
00643 }
00644
00645 /**
00646   * @brief  Get OPAMP offset to calibrate the selected transistors
00647   *         differential pair NMOS or PMOS.
00648   * @note   Preliminarily, OPAMP must be set in mode calibration
00649   *         using function @ref LL_OPAMP_SetMode().
00650   * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection
00651   * @param  OPAMPx OPAMP instance
00652   * @retval Returned value can be one of the following values:
00653   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00654   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00655   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00656   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00657   *
00658   *         (1) Default parameters to be used for calibration
00659   *             using two trimming steps (one with each transistors differential
00660   *             pair NMOS and PMOS)
00661   */
00662 __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
00663 {
00664   register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
00665
00666   return (uint32_t)((CalibrationSelection << 4)|
00667           (((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));
00668 }
00669
00670 /**
00671   * @brief  Get OPAMP calibration result of toggling output.
00672   * @note   This functions returns:
00673   *         0 if OPAMP calibration output is reset
00674   *         1 if OPAMP calibration output is set
00675   * @rmtoll CSR      OUTCAL         LL_OPAMP_IsCalibrationOutputSet
00676   * @param  OPAMPx OPAMP instance
00677   * @retval State of bit (1 or 0).
00678   */
00679 __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
00680 {
00681   return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL);
00682 }
00683
00684 /**
00685   * @brief  Set OPAMP trimming factor for the selected transistors
00686   *         differential pair NMOS or PMOS, corresponding to the selected
00687   *         power mode.
00688   * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
00689   *         OTR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue\n
00690   *         HSOTR    TRIMHSOFFSETN  LL_OPAMP_SetTrimmingValue\n
00691   *         HSOTR    TRIMHSOFFSETP  LL_OPAMP_SetTrimmingValue
00692   * @param  OPAMPx OPAMP instance
00693   * @param  PowerMode This parameter can be one of the following values:
00694   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00695   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00696   * @param  TransistorsDiffPair This parameter can be one of the following values:
00697   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00698   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00699   * @param  TrimmingValue 0x00...0x1F
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
00703 {
00704   register __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
00705
00706   /* Set bits with position in register depending on parameter                */
00707   /* "TransistorsDiffPair".                                                   */
00708   /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
00709   /* containing other bits reserved for other purpose.                        */
00710   MODIFY_REG(*preg,
00711              (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) << 1U,
00712              TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));
00713 }
00714
00715 /**
00716   * @brief  Get OPAMP trimming factor for the selected transistors
00717   *         differential pair NMOS or PMOS, corresponding to the selected
00718   *         power mode.
00719   * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_GetTrimmingValue\n
00720   *         OTR      TRIMOFFSETP    LL_OPAMP_GetTrimmingValue\n
00721   *         HSOTR    TRIMHSOFFSETN  LL_OPAMP_GetTrimmingValue\n
00722   *         HSOTR    TRIMHSOFFSETP  LL_OPAMP_GetTrimmingValue
00723   * @param  OPAMPx OPAMP instance
00724   * @param  PowerMode This parameter can be one of the following values:
00725   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00726   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00727   * @param  TransistorsDiffPair This parameter can be one of the following values:
00728   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00729   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00730   * @retval 0x0...0x1F
00731   */
00732 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
00733 {
00734   register const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
00735
00736   /* Retrieve bits with position in register depending on parameter           */
00737   /* "TransistorsDiffPair".                                                   */
00738   /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
00739   /* containing other bits reserved for other purpose.                        */
00740   return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00741                     >> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));
00742 }
00743
00744 /**
00745   * @}
00746   */
00747
00748 /** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
00749   * @{
00750   */
00751 /**
00752   * @brief  Enable OPAMP instance.
00753   * @note   After enable from off state, OPAMP requires a delay
00754   *         to fullfill wake up time specification.
00755   *         Refer to device datasheet, parameter "tWAKEUP".
00756   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable
00757   * @param  OPAMPx OPAMP instance
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
00761 {
00762   SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00763 }
00764
00765 /**
00766   * @brief  Disable OPAMP instance.
00767   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable
00768   * @param  OPAMPx OPAMP instance
00769   * @retval None
00770   */
00771 __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
00772 {
00773   CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00774 }
00775
00776 /**
00777   * @brief  Get OPAMP instance enable state
00778   *         (0: OPAMP is disabled, 1: OPAMP is enabled)
00779   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled
00780   * @param  OPAMPx OPAMP instance
00781   * @retval State of bit (1 or 0).
00782   */
00783 __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
00784 {
00785   return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL);
00786 }
00787 /**
00788   * @}
00789   */
00790
00791 #if defined(USE_FULL_LL_DRIVER)
00792 /** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
00793   * @{
00794   */
00795
00796 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
00797 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00798 void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00799
00800 /**
00801   * @}
00802   */
00803 #endif /* USE_FULL_LL_DRIVER */
00804
00805 /**
00806   * @}
00807   */
00808
00809 /**
00810   * @}
00811   */
00812
00813 #endif /* OPAMP1 || OPAMP2 */
00814
00815 /**
00816   * @}
00817   */
00818
00819 #ifdef __cplusplus
00820 }
00821 #endif
00822
00823 #endif /* __STM32H7xx_LL_OPAMP_H */
00824
00825 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_pwr.c Source File

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stm32h7xx_ll_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 #if defined (USE_FULL_LL_DRIVER)
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32h7xx_ll_pwr.h"
00024
00025 /** @addtogroup STM32H7xx_LL_Driver
00026   * @{
00027   */
00028
00029 #if defined (PWR)
00030
00031 /** @defgroup PWR_LL PWR
00032   * @{
00033   */
00034
00035 /* Private types -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 /* Private constants ---------------------------------------------------------*/
00038 /* Private macros ------------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup PWR_LL_Exported_Functions
00043   * @{
00044   */
00045
00046 /** @addtogroup PWR_LL_EF_Init
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  De-initialize the PWR registers to their default reset values.
00052   * @retval An ErrorStatus enumeration value:
00053   *          - SUCCESS: PWR registers are de-initialized
00054   *          - ERROR: not applicable
00055   */
00056 ErrorStatus LL_PWR_DeInit(void)
00057 {
00058   WRITE_REG(PWR->WKUPCR, (PWR_WKUPCR_WKUPC1 | PWR_WKUPCR_WKUPC2 | PWR_WKUPCR_WKUPC3 | \
00059                           PWR_WKUPCR_WKUPC4 | PWR_WKUPCR_WKUPC5 | PWR_WKUPCR_WKUPC6));
00060
00061   return SUCCESS;
00062 }
00063
00064 /**
00065   * @}
00066   */
00067
00068 /**
00069   * @}
00070   */
00071
00072 /**
00073   * @}
00074   */
00075 #endif /* defined (PWR) */
00076 /**
00077   * @}
00078   */
00079
00080 #endif /* defined (USE_FULL_LL_DRIVER) */
00081
00082 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_pwr.h Source File

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stm32h7xx_ll_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_PWR_H
00022 #define STM32H7xx_LL_PWR_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (PWR)
00036
00037 /** @defgroup PWR_LL PWR
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
00045   * @{
00046   */
00047
00048 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
00049   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00050   * @{
00051   */
00052 /* Wake-Up Pins PWR register offsets */
00053 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
00054 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
00055 /**
00056   * @}
00057   */
00058 /**
00059   * @}
00060   */
00061 /* Private macros ------------------------------------------------------------*/
00062 /* Exported types ------------------------------------------------------------*/
00063 /* Exported constants --------------------------------------------------------*/
00064 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00065   * @{
00066   */
00067
00068 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00069   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00070   * @{
00071   */
00072 #define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */
00073 #if defined (DUAL_CORE)
00074 #define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
00075 #endif /* DUAL_CORE */
00076 #define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear WKUP pin 6     */
00077 #define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear WKUP pin 5     */
00078 #define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear WKUP pin 4     */
00079 #define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear WKUP pin 3     */
00080 #define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear WKUP pin 2     */
00081 #define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear WKUP pin 1     */
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00087   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00088   * @{
00089   */
00090 #define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */
00091 #define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */
00092 #define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */
00093 #define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
00094 #if defined (PWR_CSR1_MMCVDO)
00095 #define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */
00096 #endif /* PWR_CSR1_MMCVDO */
00097
00098 #define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */
00099 #define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */
00100 #define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */
00101 #define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */
00102 #define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */
00103
00104 #define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */
00105 #define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */
00106
00107 #if defined (PWR_CPUCR_SBF_D2)
00108 #define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */
00109 #endif /* PWR_CPUCR_SBF_D2 */
00110 #if defined (PWR_CPUCR_SBF_D1)
00111 #define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */
00112 #endif /* PWR_CPUCR_SBF_D1 */
00113 #define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */
00114 #define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */
00115 #if defined (DUAL_CORE)
00116 #define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */
00117 #endif /* DUAL_CORE */
00118
00119 #if defined (DUAL_CORE)
00120 #define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */
00121 #define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */
00122 #define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */
00123 #define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */
00124 #define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */
00125 #endif /* DUAL_CORE */
00126
00127 #if defined (PWR_CPUCR_PDDS_D2)
00128 #define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */
00129 #else
00130 #define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */
00131 #endif /* PWR_CPUCR_PDDS_D2 */
00132
00133 #define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup Pin Flag 6 */
00134 #define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup Pin Flag 5 */
00135 #define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup Pin Flag 4 */
00136 #define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup Pin Flag 3 */
00137 #define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup Pin Flag 2 */
00138 #define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup Pin Flag 1 */
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup PWR_LL_EC_MODE_PWR Power mode
00144   * @{
00145   */
00146 #if defined (PWR_CPUCR_PDDS_D2)
00147 #define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */
00148 #define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */
00149 #else
00150 #define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */
00151 #define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */
00152 #endif /* PWR_CPUCR_PDDS_D2 */
00153
00154 #if defined (PWR_CPUCR_PDDS_D2)
00155 #define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */
00156 #define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */
00157 #endif /* PWR_CPUCR_PDDS_D2 */
00158
00159 #if defined (PWR_CPUCR_PDDS_D2)
00160 #define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */
00161 #define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */
00162 #define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */
00163 #else
00164 #define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */
00165 #define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */
00166 #define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */
00167 #endif /* PWR_CPUCR_PDDS_D2 */
00168
00169 #if defined (DUAL_CORE)
00170 #define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */
00171 #define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */
00172 #define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */
00173 #define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */
00174 #define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */
00175 #define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */
00176 #define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */
00177 #endif /* DUAL_CORE */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
00183   * @{
00184   */
00185 #if defined (PWR_CPUCR_PDDS_D2)
00186 #define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
00187 #define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
00188 #define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
00189 #define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
00190 #else
00191 #define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
00192 #define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
00193 #define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
00194 #define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
00195 #endif /* PWR_CPUCR_PDDS_D2 */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
00201   * @{
00202   */
00203 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
00204 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */
00205 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
00211   * @{
00212   */
00213 #define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
00214 #define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
00220   * @{
00221   */
00222 #define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
00223 #define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */
00224 #define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */
00225 #define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */
00226 #define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */
00227 #define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */
00228 #define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */
00229 #define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
00235   * @{
00236   */
00237 #define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
00238 #define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */
00239 #define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */
00240 #define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
00247   * @{
00248   */
00249 #define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
00250 #define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
00256   * @{
00257   */
00258 #define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
00259 #define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
00260 #define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PC1  */
00261 #define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
00262 #define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI8  */
00263 #define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PI11 */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
00269   * @{
00270   */
00271 #define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
00272 #define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */
00273 #define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
00279   * @{
00280   */
00281 #define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
00282 #if defined (SMPS)
00283 #define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS                                                                    */
00284 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
00285 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
00286 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
00287 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
00288 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
00289 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
00290 #endif /* SMPS */
00291 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */
00292 /**
00293   * @}
00294   */
00295
00296 /**
00297   * @}
00298   */
00299 /* Exported macro ------------------------------------------------------------*/
00300 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00301   * @{
00302   */
00303
00304 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Write a value in PWR register
00310   * @param  __REG__ Register to be written
00311   * @param  __VALUE__ Value to be written in the register
00312   * @retval None
00313   */
00314 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00315
00316 /**
00317   * @brief  Read a value in PWR register
00318   * @param  __REG__ Register to be read
00319   * @retval Register value
00320   */
00321 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329 /* Exported functions --------------------------------------------------------*/
00330 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00331   * @{
00332   */
00333
00334 /** @defgroup PWR_LL_EF_Configuration Configuration
00335   * @{
00336   */
00337
00338   /**
00339   * @brief  Set the voltage Regulator mode during deep sleep mode
00340   * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
00341   * @param  RegulMode This parameter can be one of the following values:
00342   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00343   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00344   * @retval None
00345   */
00346 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
00347 {
00348   MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
00349 }
00350
00351 /**
00352   * @brief  Get the voltage Regulator mode during deep sleep mode
00353   * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
00354   * @retval Returned value can be one of the following values:
00355   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00356   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00357   */
00358 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
00359 {
00360   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
00361 }
00362
00363 /**
00364   * @brief  Enable Power Voltage Detector
00365   * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD
00366   * @retval None
00367   */
00368 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00369 {
00370   SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
00371 }
00372
00373 /**
00374   * @brief  Disable Power Voltage Detector
00375   * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD
00376   * @retval None
00377   */
00378 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00379 {
00380   CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
00381 }
00382
00383 /**
00384   * @brief  Check if Power Voltage Detector is enabled
00385   * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD
00386   * @retval State of bit (1 or 0).
00387   */
00388 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00389 {
00390   return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
00391 }
00392
00393 /**
00394   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00395   * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
00396   * @param  PVDLevel This parameter can be one of the following values:
00397   *         @arg @ref LL_PWR_PVDLEVEL_0
00398   *         @arg @ref LL_PWR_PVDLEVEL_1
00399   *         @arg @ref LL_PWR_PVDLEVEL_2
00400   *         @arg @ref LL_PWR_PVDLEVEL_3
00401   *         @arg @ref LL_PWR_PVDLEVEL_4
00402   *         @arg @ref LL_PWR_PVDLEVEL_5
00403   *         @arg @ref LL_PWR_PVDLEVEL_6
00404   *         @arg @ref LL_PWR_PVDLEVEL_7
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00408 {
00409   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
00410 }
00411
00412 /**
00413   * @brief  Get the voltage threshold detection
00414   * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
00415   * @retval Returned value can be one of the following values:
00416   *         @arg @ref LL_PWR_PVDLEVEL_0
00417   *         @arg @ref LL_PWR_PVDLEVEL_1
00418   *         @arg @ref LL_PWR_PVDLEVEL_2
00419   *         @arg @ref LL_PWR_PVDLEVEL_3
00420   *         @arg @ref LL_PWR_PVDLEVEL_4
00421   *         @arg @ref LL_PWR_PVDLEVEL_5
00422   *         @arg @ref LL_PWR_PVDLEVEL_6
00423   *         @arg @ref LL_PWR_PVDLEVEL_7
00424   */
00425 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00426 {
00427   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
00428 }
00429
00430 /**
00431   * @brief  Enable access to the backup domain
00432   * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
00433   * @retval None
00434   */
00435 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00436 {
00437   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00438 }
00439
00440 /**
00441   * @brief  Disable access to the backup domain
00442   * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
00443   * @retval None
00444   */
00445 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00446 {
00447   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00448 }
00449
00450 /**
00451   * @brief  Check if the backup domain is enabled
00452   * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
00453   * @retval State of bit (1 or 0).
00454   */
00455 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00456 {
00457   return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
00458 }
00459
00460 /**
00461   * @brief  Enable the Flash Power Down in Stop Mode
00462   * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown
00463   * @retval None
00464   */
00465 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
00466 {
00467   SET_BIT(PWR->CR1, PWR_CR1_FLPS);
00468 }
00469
00470 /**
00471   * @brief  Disable the Flash Power Down in Stop Mode
00472   * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
00476 {
00477   CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
00478 }
00479
00480 /**
00481   * @brief  Check if the Flash Power Down in Stop Mode is enabled
00482   * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown
00483   * @retval State of bit (1 or 0).
00484   */
00485 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
00486 {
00487   return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
00488 }
00489
00490 #if defined (PWR_CR1_BOOSTE)
00491 /**
00492   * @brief  Enable the Analog Voltage Booster (VDDA)
00493   * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster
00494   * @retval None
00495   */
00496 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
00497 {
00498   SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
00499 }
00500
00501 /**
00502   * @brief  Disable the Analog Voltage Booster (VDDA)
00503   * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster
00504   * @retval None
00505   */
00506 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
00507 {
00508   CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
00509 }
00510
00511 /**
00512   * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
00513   * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster
00514   * @retval State of bit (1 or 0).
00515   */
00516 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
00517 {
00518   return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
00519 }
00520 #endif /* PWR_CR1_BOOSTE */
00521
00522 #if defined (PWR_CR1_AVD_READY)
00523 /**
00524   * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
00525   * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
00526   * @retval None
00527   */
00528 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
00529 {
00530   SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
00531 }
00532
00533 /**
00534   * @brief  Disable the Analog Voltage Ready (VDDA)
00535   * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady
00536   * @retval None
00537   */
00538 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
00539 {
00540   CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
00541 }
00542
00543 /**
00544   * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
00545   * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady
00546   * @retval State of bit (1 or 0).
00547   */
00548 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
00549 {
00550   return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
00551 }
00552 #endif /* PWR_CR1_AVD_READY */
00553
00554 /**
00555   * @brief  Set the internal Regulator output voltage in STOP mode
00556   * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling
00557   * @param  VoltageScaling This parameter can be one of the following values:
00558   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
00559   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
00560   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
00561   * @retval None
00562   */
00563 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
00564 {
00565   MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
00566 }
00567
00568 /**
00569   * @brief  Get the internal Regulator output voltage in STOP mode
00570   * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling
00571   * @retval Returned value can be one of the following values:
00572   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
00573   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
00574   *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
00575   */
00576 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
00577 {
00578   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
00579 }
00580
00581 /**
00582   * @brief  Enable Analog Power Voltage Detector
00583   * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD
00584   * @retval None
00585   */
00586 __STATIC_INLINE void LL_PWR_EnableAVD(void)
00587 {
00588   SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
00589 }
00590
00591 /**
00592   * @brief  Disable Analog Power Voltage Detector
00593   * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD
00594   * @retval None
00595   */
00596 __STATIC_INLINE void LL_PWR_DisableAVD(void)
00597 {
00598   CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
00599 }
00600
00601 /**
00602   * @brief  Check if Analog Power Voltage Detector is enabled
00603   * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD
00604   * @retval State of bit (1 or 0).
00605   */
00606 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
00607 {
00608   return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
00609 }
00610
00611 /**
00612   * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector
00613   * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel
00614   * @param  AVDLevel This parameter can be one of the following values:
00615   *         @arg @ref LL_PWR_AVDLEVEL_0
00616   *         @arg @ref LL_PWR_AVDLEVEL_1
00617   *         @arg @ref LL_PWR_AVDLEVEL_2
00618   *         @arg @ref LL_PWR_AVDLEVEL_3
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
00622 {
00623   MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
00624 }
00625
00626 /**
00627   * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
00628   * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel
00629   * @retval Returned value can be one of the following values:
00630   *         @arg @ref LL_PWR_AVDLEVEL_0
00631   *         @arg @ref LL_PWR_AVDLEVEL_1
00632   *         @arg @ref LL_PWR_AVDLEVEL_2
00633   *         @arg @ref LL_PWR_AVDLEVEL_3
00634   */
00635 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
00636 {
00637   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
00638 }
00639
00640 #if defined (PWR_CR1_AXIRAM1SO)
00641 /**
00642   * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode
00643   * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
00647 {
00648   SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
00649 }
00650
00651 /**
00652   * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode
00653   * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
00657 {
00658   CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
00659 }
00660
00661 /**
00662   * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
00663   * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff
00664   * @retval State of bit (1 or 0).
00665   */
00666 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
00667 {
00668   return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
00669 }
00670 #endif /* PWR_CR1_AXIRAM1SO */
00671
00672 #if defined (PWR_CR1_AXIRAM2SO)
00673 /**
00674   * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode
00675   * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
00679 {
00680   SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
00681 }
00682
00683 /**
00684   * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode
00685   * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff
00686   * @retval None
00687   */
00688 __STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
00689 {
00690   CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
00691 }
00692
00693 /**
00694   * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
00695   * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff
00696   * @retval State of bit (1 or 0).
00697   */
00698 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
00699 {
00700   return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
00701 }
00702 #endif /* PWR_CR1_AXIRAM2SO */
00703
00704 #if defined (PWR_CR1_AXIRAM3SO)
00705 /**
00706   * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode
00707   * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
00711 {
00712   SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
00713 }
00714
00715 /**
00716   * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode
00717   * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff
00718   * @retval None
00719   */
00720 __STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
00721 {
00722   CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
00723 }
00724
00725 /**
00726   * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
00727   * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff
00728   * @retval State of bit (1 or 0).
00729   */
00730 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
00731 {
00732   return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
00733 }
00734 #endif /* PWR_CR1_AXIRAM3SO */
00735
00736 #if defined (PWR_CR1_AHBRAM1SO)
00737 /**
00738   * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode
00739   * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff
00740   * @retval None
00741   */
00742 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
00743 {
00744   SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
00745 }
00746
00747 /**
00748   * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode
00749   * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
00753 {
00754   CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
00755 }
00756
00757 /**
00758   * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
00759   * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff
00760   * @retval State of bit (1 or 0).
00761   */
00762 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
00763 {
00764   return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
00765 }
00766 #endif /* PWR_CR1_AHBRAM1SO */
00767
00768 #if defined (PWR_CR1_AHBRAM2SO)
00769 /**
00770   * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode
00771   * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff
00772   * @retval None
00773   */
00774 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
00775 {
00776   SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
00777 }
00778
00779 /**
00780   * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode
00781   * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff
00782   * @retval None
00783   */
00784 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
00785 {
00786   CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
00787 }
00788
00789 /**
00790   * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
00791   * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff
00792   * @retval State of bit (1 or 0).
00793   */
00794 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
00795 {
00796   return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
00797 }
00798 #endif /* PWR_CR1_AHBRAM2SO */
00799
00800 #if defined (PWR_CR1_ITCMSO)
00801 /**
00802   * @brief  Enable the ITCM shut-off in DStop/DStop2 mode
00803   * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff
00804   * @retval None
00805   */
00806 __STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
00807 {
00808   SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
00809 }
00810
00811 /**
00812   * @brief  Disable the ITCM shut-off in DStop/DStop2 mode
00813   * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
00817 {
00818   CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
00819 }
00820
00821 /**
00822   * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled
00823   * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff
00824   * @retval State of bit (1 or 0).
00825   */
00826 __STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
00827 {
00828   return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
00829 }
00830 #endif /* PWR_CR1_ITCMSO */
00831
00832 #if defined (PWR_CR1_HSITFSO)
00833 /**
00834   * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode
00835   * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff
00836   * @retval None
00837   */
00838 __STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
00839 {
00840   SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
00841 }
00842
00843 /**
00844   * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode
00845   * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff
00846   * @retval None
00847   */
00848 __STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
00849 {
00850   CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
00851 }
00852
00853 /**
00854   * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
00855   * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff
00856   * @retval State of bit (1 or 0).
00857   */
00858 __STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
00859 {
00860   return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
00861 }
00862 #endif /* PWR_CR1_HSITFSO */
00863
00864 #if defined (PWR_CR1_SRDRAMSO)
00865 /**
00866   * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
00867   * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff
00868   * @retval None
00869   */
00870 __STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
00871 {
00872   SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
00873 }
00874
00875 /**
00876   * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
00877   * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff
00878   * @retval None
00879   */
00880 __STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
00881 {
00882   CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
00883 }
00884
00885 /**
00886   * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
00887   * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff
00888   * @retval State of bit (1 or 0).
00889   */
00890 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
00891 {
00892   return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
00893 }
00894 #endif /* PWR_CR1_SRDRAMSO */
00895
00896 /**
00897   * @brief  Enable Backup Regulator
00898   * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator
00899   * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
00900   *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
00901   *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
00902   *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
00903   *       the data written into the RAM will be maintained in the Standby and VBAT modes.
00904   * @retval None
00905   */
00906 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
00907 {
00908   SET_BIT(PWR->CR2, PWR_CR2_BREN);
00909 }
00910
00911 /**
00912   * @brief  Disable Backup Regulator
00913   * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
00917 {
00918   CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
00919 }
00920
00921 /**
00922   * @brief  Check if the backup Regulator is enabled
00923   * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator
00924   * @retval State of bit (1 or 0).
00925   */
00926 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
00927 {
00928   return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
00929 }
00930
00931 /**
00932   * @brief  Enable VBAT and Temperature monitoring
00933   * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring
00934   * @retval None
00935   */
00936 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
00937 {
00938   SET_BIT(PWR->CR2, PWR_CR2_MONEN);
00939 }
00940
00941 /**
00942   * @brief  Disable VBAT and Temperature monitoring
00943   * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring
00944   * @retval None
00945   */
00946 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
00947 {
00948   CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
00949 }
00950
00951 /**
00952   * @brief  Check if the VBAT and Temperature monitoring is enabled
00953   * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring
00954   * @retval State of bit (1 or 0).
00955   */
00956 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
00957 {
00958   return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
00959 }
00960
00961 #if defined (SMPS)
00962 /**
00963   * @brief  Configure the PWR supply
00964   * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
00965   * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
00966   * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply
00967   * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply
00968   * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply
00969   * @param  SupplySource This parameter can be one of the following values:
00970   *         @arg @ref LL_PWR_LDO_SUPPLY
00971   *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
00972   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
00973   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
00974   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
00975   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
00976   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
00977   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
00978   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
00979   * @retval None
00980   */
00981 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
00982 {
00983   /* Set the power supply configuration */
00984   MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
00985 }
00986 #else
00987 /**
00988   * @brief  Configure the PWR supply
00989   * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
00990   * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
00991   * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply
00992   * @param  SupplySource This parameter can be one of the following values:
00993   *         @arg @ref LL_PWR_LDO_SUPPLY
00994   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
00995   * @retval None
00996   */
00997 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
00998 {
00999   /* Set the power supply configuration */
01000   MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
01001 }
01002 #endif /* defined (SMPS) */
01003
01004 #if defined (SMPS)
01005 /**
01006   * @brief  Get the PWR supply
01007   * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
01008   * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
01009   * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply
01010   * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply
01011   * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply
01012   * @retval Returned value can be one of the following values:
01013   *         @arg @ref LL_PWR_LDO_SUPPLY
01014   *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
01015   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
01016   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
01017   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
01018   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
01019   *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
01020   *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
01021   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
01022   */
01023 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
01024 {
01025   /* Get the power supply configuration */
01026   return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
01027 }
01028 #else
01029 /**
01030   * @brief  Get the PWR supply
01031   * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
01032   * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
01033   * @rmtoll CR3          SCUEN           LL_PWR_GetSupply
01034   * @retval Returned value can be one of the following values:
01035   *         @arg @ref LL_PWR_LDO_SUPPLY
01036   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
01037   */
01038 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
01039 {
01040   /* Get the power supply configuration */
01041   return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
01042 }
01043 #endif /* defined (SMPS) */
01044
01045 /**
01046   * @brief  Enable battery charging
01047   * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
01051 {
01052   SET_BIT(PWR->CR3, PWR_CR3_VBE);
01053 }
01054
01055 /**
01056   * @brief  Disable battery charging
01057   * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging
01058   * @retval None
01059   */
01060 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
01061 {
01062   CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
01063 }
01064
01065 /**
01066   * @brief  Check if battery charging is enabled
01067   * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging
01068   * @retval State of bit (1 or 0).
01069   */
01070 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
01071 {
01072   return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
01073 }
01074
01075 /**
01076   * @brief  Set the Battery charge resistor impedance
01077   * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor
01078   * @param  Resistor This parameter can be one of the following values:
01079   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
01080   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
01084 {
01085   MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
01086 }
01087
01088 /**
01089   * @brief  Get the Battery charge resistor impedance
01090   * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor
01091   * @retval Returned value can be one of the following values:
01092   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
01093   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
01094   */
01095 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
01096 {
01097   return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
01098 }
01099
01100 /**
01101   * @brief  Enable the USB regulator
01102   * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg
01103   * @retval None
01104   */
01105 __STATIC_INLINE void LL_PWR_EnableUSBReg(void)
01106 {
01107   SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
01108 }
01109
01110 /**
01111   * @brief  Disable the USB regulator
01112   * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg
01113   * @retval None
01114   */
01115 __STATIC_INLINE void LL_PWR_DisableUSBReg(void)
01116 {
01117   CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
01118 }
01119
01120 /**
01121   * @brief  Check if the USB regulator is enabled
01122   * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg
01123   * @retval State of bit (1 or 0).
01124   */
01125 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
01126 {
01127   return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
01128 }
01129
01130 /**
01131   * @brief  Enable the USB voltage detector
01132   * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector
01133   * @retval None
01134   */
01135 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
01136 {
01137   SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
01138 }
01139
01140 /**
01141   * @brief  Disable the USB voltage detector
01142   * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector
01143   * @retval None
01144   */
01145 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
01146 {
01147   CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
01148 }
01149
01150 /**
01151   * @brief  Check if the USB voltage detector is enabled
01152   * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector
01153   * @retval State of bit (1 or 0).
01154   */
01155 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
01156 {
01157   return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
01158 }
01159
01160 #if defined (PWR_CPUCR_PDDS_D2)
01161 /**
01162   * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep
01163   * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode
01164   * @param  PDMode This parameter can be one of the following values:
01165   *         @arg @ref LL_PWR_CPU_MODE_D1STOP
01166   *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
01170 {
01171   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
01172 }
01173 #else
01174 /**
01175   * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep
01176   * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode
01177   * @param  PDMode This parameter can be one of the following values:
01178   *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
01179   *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
01180   * @retval None
01181   */
01182 __STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
01183 {
01184   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
01185 }
01186 #endif /* PWR_CPUCR_PDDS_D2 */
01187
01188 #if defined (DUAL_CORE)
01189 /**
01190   * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep
01191   * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode
01192   * @param  PDMode This parameter can be one of the following values:
01193   *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
01194   *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
01195   * @retval None
01196   */
01197 __STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
01198 {
01199   MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
01200 }
01201 #endif /* DUAL_CORE */
01202
01203 #if defined (PWR_CPUCR_PDDS_D2)
01204 /**
01205   * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep
01206   * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode
01207   * @retval Returned value can be one of the following values:
01208   *         @arg @ref LL_PWR_CPU_MODE_D1STOP
01209   *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
01210   */
01211 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
01212 {
01213   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
01214 }
01215 #else
01216 /**
01217   * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep
01218   * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode
01219   * @retval Returned value can be one of the following values:
01220   *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
01221   *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
01222   */
01223 __STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
01224 {
01225   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
01226 }
01227 #endif /* PWR_CPUCR_PDDS_D2 */
01228
01229 #if defined (DUAL_CORE)
01230 /**
01231   * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
01232   * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode
01233   * @retval Returned value can be one of the following values:
01234   *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
01235   *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
01236   */
01237 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
01238 {
01239   return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
01240 }
01241 #endif /* DUAL_CORE */
01242
01243 #if defined (PWR_CPUCR_PDDS_D2)
01244 /**
01245   * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep
01246   * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode
01247   * @param  PDMode This parameter can be one of the following values:
01248   *         @arg @ref LL_PWR_CPU_MODE_D2STOP
01249   *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
01250   * @retval None
01251   */
01252 __STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
01253 {
01254   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
01255 }
01256 #endif /* PWR_CPUCR_PDDS_D2 */
01257
01258 #if defined (DUAL_CORE)
01259 /**
01260   * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep
01261   * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode
01262   * @param  PDMode This parameter can be one of the following values:
01263   *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
01264   *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
01265   * @retval None
01266   */
01267 __STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
01268 {
01269   MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
01270 }
01271 #endif /* DUAL_CORE */
01272
01273 #if defined (PWR_CPUCR_PDDS_D2)
01274 /**
01275   * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep
01276   * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode
01277   * @retval Returned value can be one of the following values:
01278   *         @arg @ref LL_PWR_CPU_MODE_D2STOP
01279   *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
01280   */
01281 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
01282 {
01283   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
01284 }
01285 #endif /* PWR_CPUCR_PDDS_D2 */
01286
01287 #if defined (DUAL_CORE)
01288 /**
01289   * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
01290   * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode
01291   * @retval Returned value can be one of the following values:
01292   *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
01293   *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
01294   */
01295 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
01296 {
01297   return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
01298 }
01299 #endif /* DUAL_CORE */
01300
01301 #if defined (PWR_CPUCR_PDDS_D2)
01302 /**
01303   * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep
01304   * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode
01305   * @param  PDMode This parameter can be one of the following values:
01306   *         @arg @ref LL_PWR_CPU_MODE_D3STOP
01307   *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
01308   * @retval None
01309   */
01310 __STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
01311 {
01312   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
01313 }
01314 #else
01315 /**
01316   * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep
01317   * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode
01318   * @param  PDMode This parameter can be one of the following values:
01319   *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
01320   *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
01324 {
01325   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
01326 }
01327 #endif /* PWR_CPUCR_PDDS_D2 */
01328
01329 #if defined (DUAL_CORE)
01330 /**
01331   * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep
01332   * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode
01333   * @param  PDMode This parameter can be one of the following values:
01334   *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
01335   *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
01336   * @retval None
01337   */
01338 __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
01339 {
01340   MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
01341 }
01342 #endif /* DUAL_CORE */
01343
01344 #if defined (PWR_CPUCR_PDDS_D3)
01345 /**
01346   * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
01347   * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
01348   * @retval Returned value can be one of the following values:
01349   *         @arg @ref LL_PWR_CPU_MODE_D3STOP
01350   *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
01351   */
01352 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
01353 {
01354   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
01355 }
01356 #else
01357 /**
01358   * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep
01359   * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode
01360   * @retval Returned value can be one of the following values:
01361   *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
01362   *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
01363   */
01364 __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
01365 {
01366   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
01367 }
01368 #endif /* PWR_CPUCR_PDDS_D3 */
01369
01370 #if defined (DUAL_CORE)
01371 /**
01372   * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
01373   * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode
01374   * @retval Returned value can be one of the following values:
01375   *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
01376   *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
01377   */
01378 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
01379 {
01380   return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
01381 }
01382 #endif /* DUAL_CORE */
01383
01384 #if defined (DUAL_CORE)
01385 /**
01386   * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode
01387   * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_PWR_HoldCPU1(void)
01391 {
01392   SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
01393 }
01394
01395 /**
01396   * @brief  Release the CPU1 and allocated peripherals
01397   * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1
01398   * @retval None
01399   */
01400 __STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
01401 {
01402   CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
01403 }
01404
01405 /**
01406   * @brief  Ckeck if the CPU1 and allocated peripherals are held
01407   * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held
01408   * @retval State of bit (1 or 0).
01409   */
01410 __STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
01411 {
01412   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
01413 }
01414
01415 /**
01416   * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode
01417   * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2
01418   * @retval None
01419   */
01420 __STATIC_INLINE void LL_PWR_HoldCPU2(void)
01421 {
01422   SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
01423 }
01424
01425 /**
01426   * @brief  Release the CPU2 and allocated peripherals
01427   * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2
01428   * @retval None
01429   */
01430 __STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
01431 {
01432   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
01433 }
01434
01435 /**
01436   * @brief  Ckeck if the CPU2 and allocated peripherals are held
01437   * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held
01438   * @retval State of bit (1 or 0).
01439   */
01440 __STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
01441 {
01442   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
01443 }
01444 #endif /* DUAL_CORE */
01445
01446 #if defined (PWR_CPUCR_PDDS_D2)
01447 /**
01448   * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes
01449   * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode
01450   * @retval None
01451   */
01452 __STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
01453 {
01454   SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
01455 }
01456 #else
01457 /**
01458   * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes
01459   * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode
01460   * @retval None
01461   */
01462 __STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
01463 {
01464   SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
01465 }
01466 #endif /* PWR_CPUCR_PDDS_D2 */
01467
01468 #if defined (DUAL_CORE)
01469 /**
01470   * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes
01471   * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode
01472   * @retval None
01473   */
01474 __STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
01475 {
01476   SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
01477 }
01478 #endif /* DUAL_CORE */
01479
01480 #if defined (PWR_CPUCR_PDDS_D2)
01481 /**
01482   * @brief  D3 domain follows CPU subsystem modes
01483   * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode
01484   * @retval None
01485   */
01486 __STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
01487 {
01488   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
01489 }
01490 #else
01491 /**
01492   * @brief  SRD domain follows CPU subsystem modes
01493   * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode
01494   * @retval None
01495   */
01496 __STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
01497 {
01498   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
01499 }
01500 #endif /* PWR_CPUCR_PDDS_D2 */
01501
01502 #if defined (DUAL_CORE)
01503 /**
01504   * @brief  D3 domain follows CPU2 subsystem modes
01505   * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode
01506   * @retval None
01507   */
01508 __STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
01509 {
01510   CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
01511 }
01512 #endif /* DUAL_CORE */
01513
01514 #if defined (PWR_CPUCR_PDDS_D2)
01515 /**
01516   * @brief  Check if D3 is kept in Run mode when CPU enters low power mode
01517   * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
01518   * @retval State of bit (1 or 0).
01519   */
01520 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
01521 {
01522   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
01523 }
01524 #else
01525 /**
01526   * @brief  Check if SRD is kept in Run mode when CPU enters low power mode
01527   * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
01528   * @retval State of bit (1 or 0).
01529   */
01530 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
01531 {
01532   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
01533 }
01534 #endif /* PWR_CPUCR_PDDS_D2 */
01535
01536 #if defined (DUAL_CORE)
01537 /**
01538   * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode
01539   * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
01540   * @retval State of bit (1 or 0).
01541   */
01542 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
01543 {
01544   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
01545 }
01546 #endif /* DUAL_CORE */
01547
01548 /**
01549   * @brief  Set the main internal Regulator output voltage
01550   * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling
01551   * @param  VoltageScaling This parameter can be one of the following values:
01552   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
01553   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
01554   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
01555   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
01556   * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
01557   *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
01561 {
01562 #if defined (PWR_CPUCR_PDDS_D2)
01563   MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
01564 #else
01565   MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
01566 #endif /* PWR_CPUCR_PDDS_D2 */
01567 }
01568
01569 /**
01570   * @brief  Get the main internal Regulator output voltage
01571   * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
01572   * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
01573   *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
01574   * @retval Returned value can be one of the following values:
01575   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
01576   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
01577   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
01578   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
01579   */
01580 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
01581 {
01582 #if defined (PWR_CPUCR_PDDS_D2)
01583   return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
01584 #else
01585   return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
01586 #endif /* PWR_CPUCR_PDDS_D2 */
01587 }
01588
01589 /**
01590   * @brief  Enable the WakeUp PINx functionality
01591   * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n
01592   *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n
01593   *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n
01594   *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n
01595   *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n
01596   *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin
01597   * @param  WakeUpPin This parameter can be one of the following values:
01598   *         @arg @ref LL_PWR_WAKEUP_PIN1
01599   *         @arg @ref LL_PWR_WAKEUP_PIN2
01600   *         @arg @ref LL_PWR_WAKEUP_PIN3
01601   *         @arg @ref LL_PWR_WAKEUP_PIN4
01602   *         @arg @ref LL_PWR_WAKEUP_PIN5
01603   *         @arg @ref LL_PWR_WAKEUP_PIN6
01604   * @retval None
01605   */
01606 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
01607 {
01608   SET_BIT(PWR->WKUPEPR, WakeUpPin);
01609 }
01610
01611 /**
01612   * @brief  Disable the WakeUp PINx functionality
01613   * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n
01614   *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n
01615   *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n
01616   *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n
01617   *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n
01618   *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin
01619   * @param  WakeUpPin This parameter can be one of the following values:
01620   *         @arg @ref LL_PWR_WAKEUP_PIN1
01621   *         @arg @ref LL_PWR_WAKEUP_PIN2
01622   *         @arg @ref LL_PWR_WAKEUP_PIN3
01623   *         @arg @ref LL_PWR_WAKEUP_PIN4
01624   *         @arg @ref LL_PWR_WAKEUP_PIN5
01625   *         @arg @ref LL_PWR_WAKEUP_PIN6
01626   * @retval None
01627   */
01628 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
01629 {
01630   CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
01631 }
01632
01633 /**
01634   * @brief  Check if the WakeUp PINx functionality is enabled
01635   * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n
01636   *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n
01637   *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n
01638   *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n
01639   *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n
01640   *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin
01641   * @param  WakeUpPin This parameter can be one of the following values:
01642   *         @arg @ref LL_PWR_WAKEUP_PIN1
01643   *         @arg @ref LL_PWR_WAKEUP_PIN2
01644   *         @arg @ref LL_PWR_WAKEUP_PIN3
01645   *         @arg @ref LL_PWR_WAKEUP_PIN4
01646   *         @arg @ref LL_PWR_WAKEUP_PIN5
01647   *         @arg @ref LL_PWR_WAKEUP_PIN6
01648   * @retval State of bit (1 or 0).
01649   */
01650 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
01651 {
01652   return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
01653 }
01654
01655 /**
01656   * @brief  Set the Wake-Up pin polarity low for the event detection
01657   * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
01658   *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
01659   *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
01660   *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
01661   *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
01662   *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow
01663   * @param  WakeUpPin This parameter can be one of the following values:
01664   *         @arg @ref LL_PWR_WAKEUP_PIN1
01665   *         @arg @ref LL_PWR_WAKEUP_PIN2
01666   *         @arg @ref LL_PWR_WAKEUP_PIN3
01667   *         @arg @ref LL_PWR_WAKEUP_PIN4
01668   *         @arg @ref LL_PWR_WAKEUP_PIN5
01669   *         @arg @ref LL_PWR_WAKEUP_PIN6
01670   * @retval None
01671   */
01672 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
01673 {
01674   SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
01675 }
01676
01677 /**
01678   * @brief  Set the Wake-Up pin polarity high for the event detection
01679   * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
01680   *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
01681   *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
01682   *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
01683   *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
01684   *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh
01685   * @param  WakeUpPin This parameter can be one of the following values:
01686   *         @arg @ref LL_PWR_WAKEUP_PIN1
01687   *         @arg @ref LL_PWR_WAKEUP_PIN2
01688   *         @arg @ref LL_PWR_WAKEUP_PIN3
01689   *         @arg @ref LL_PWR_WAKEUP_PIN4
01690   *         @arg @ref LL_PWR_WAKEUP_PIN5
01691   *         @arg @ref LL_PWR_WAKEUP_PIN6
01692   * @retval None
01693   */
01694 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
01695 {
01696   CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
01697 }
01698
01699 /**
01700   * @brief  Get the Wake-Up pin polarity for the event detection
01701   * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
01702   *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
01703   *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
01704   *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
01705   *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
01706   *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow
01707   * @param  WakeUpPin This parameter can be one of the following values:
01708   *         @arg @ref LL_PWR_WAKEUP_PIN1
01709   *         @arg @ref LL_PWR_WAKEUP_PIN2
01710   *         @arg @ref LL_PWR_WAKEUP_PIN3
01711   *         @arg @ref LL_PWR_WAKEUP_PIN4
01712   *         @arg @ref LL_PWR_WAKEUP_PIN5
01713   *         @arg @ref LL_PWR_WAKEUP_PIN6
01714   * @retval State of bit (1 or 0).
01715   */
01716 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
01717 {
01718   return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
01719 }
01720
01721 /**
01722   * @brief  Set the Wake-Up pin Pull None
01723   * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
01724   *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
01725   *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
01726   *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n
01727   *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n
01728   *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone
01729   * @param  WakeUpPin This parameter can be one of the following values:
01730   *         @arg @ref LL_PWR_WAKEUP_PIN1
01731   *         @arg @ref LL_PWR_WAKEUP_PIN2
01732   *         @arg @ref LL_PWR_WAKEUP_PIN3
01733   *         @arg @ref LL_PWR_WAKEUP_PIN4
01734   *         @arg @ref LL_PWR_WAKEUP_PIN5
01735   *         @arg @ref LL_PWR_WAKEUP_PIN6
01736   * @retval None
01737   */
01738 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
01739 {
01740   MODIFY_REG(PWR->WKUPEPR, \
01741             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
01742             (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
01743 }
01744
01745 /**
01746   * @brief  Set the Wake-Up pin Pull Up
01747   * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
01748   *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
01749   *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
01750   *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n
01751   *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n
01752   *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp
01753   * @param  WakeUpPin This parameter can be one of the following values:
01754   *         @arg @ref LL_PWR_WAKEUP_PIN1
01755   *         @arg @ref LL_PWR_WAKEUP_PIN2
01756   *         @arg @ref LL_PWR_WAKEUP_PIN3
01757   *         @arg @ref LL_PWR_WAKEUP_PIN4
01758   *         @arg @ref LL_PWR_WAKEUP_PIN5
01759   *         @arg @ref LL_PWR_WAKEUP_PIN6
01760   * @retval None
01761   */
01762 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
01763 {
01764   MODIFY_REG(PWR->WKUPEPR, \
01765             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
01766             (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
01767 }
01768
01769 /**
01770   * @brief  Set the Wake-Up pin Pull Down
01771   * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
01772   *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
01773   *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
01774   *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n
01775   *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n
01776   *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown
01777   * @param  WakeUpPin This parameter can be one of the following values:
01778   *         @arg @ref LL_PWR_WAKEUP_PIN1
01779   *         @arg @ref LL_PWR_WAKEUP_PIN2
01780   *         @arg @ref LL_PWR_WAKEUP_PIN3
01781   *         @arg @ref LL_PWR_WAKEUP_PIN4
01782   *         @arg @ref LL_PWR_WAKEUP_PIN5
01783   *         @arg @ref LL_PWR_WAKEUP_PIN6
01784   * @retval None
01785   */
01786 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
01787 {
01788   MODIFY_REG(PWR->WKUPEPR, \
01789             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
01790             (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
01791 }
01792
01793 /**
01794   * @brief  Get the Wake-Up pin pull
01795   * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
01796   *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
01797   *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
01798   *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n
01799   *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n
01800   *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull
01801   * @param  WakeUpPin This parameter can be one of the following values:
01802   *         @arg @ref LL_PWR_WAKEUP_PIN1
01803   *         @arg @ref LL_PWR_WAKEUP_PIN2
01804   *         @arg @ref LL_PWR_WAKEUP_PIN3
01805   *         @arg @ref LL_PWR_WAKEUP_PIN4
01806   *         @arg @ref LL_PWR_WAKEUP_PIN5
01807   *         @arg @ref LL_PWR_WAKEUP_PIN6
01808   * @retval Returned value can be one of the following values:
01809   *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
01810   *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
01811   *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
01812   */
01813 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
01814 {
01815   register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
01816
01817   return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
01818 }
01819
01820 /**
01821   * @}
01822   */
01823
01824 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
01825   * @{
01826   */
01827
01828 /**
01829   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
01830   * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
01831   * @retval State of bit (1 or 0).
01832   */
01833 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
01834 {
01835   return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
01836 }
01837
01838 /**
01839   * @brief  Indicate whether the voltage level is ready for current actual used VOS
01840   * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS
01841   * @retval State of bit (1 or 0).
01842   */
01843 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
01844 {
01845   return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
01846 }
01847
01848 /**
01849   * @brief  Indicate whether VDDA voltage is below the selected AVD threshold
01850   * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO
01851   * @retval State of bit (1 or 0).
01852   */
01853 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
01854 {
01855   return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
01856 }
01857
01858 #if defined (PWR_CSR1_MMCVDO)
01859 /**
01860   * @brief  Indicate whether VDDMMC voltage is below 1V2
01861   * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO
01862   * @retval State of bit (1 or 0).
01863   */
01864 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
01865 {
01866   return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
01867 }
01868 #endif /* PWR_CSR1_MMCVDO */
01869
01870 /**
01871   * @brief  Get Backup Regulator ready Flag
01872   * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR
01873   * @retval State of bit (1 or 0).
01874   */
01875 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
01876 {
01877   return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
01878 }
01879
01880 /**
01881   * @brief  Indicate whether the VBAT level is above or below low threshold
01882   * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL
01883   * @retval State of bit (1 or 0).
01884   */
01885 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
01886 {
01887   return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
01888 }
01889
01890 /**
01891   * @brief  Indicate whether the VBAT level is above or below high threshold
01892   * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH
01893   * @retval State of bit (1 or 0).
01894   */
01895 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
01896 {
01897   return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
01898 }
01899
01900 /**
01901   * @brief  Indicate whether the CPU temperature level is above or below low threshold
01902   * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL
01903   * @retval State of bit (1 or 0).
01904   */
01905 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
01906 {
01907   return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
01908 }
01909
01910 /**
01911   * @brief  Indicate whether the CPU temperature level is above or below high threshold
01912   * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH
01913   * @retval State of bit (1 or 0).
01914   */
01915 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
01916 {
01917   return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
01918 }
01919
01920 #if defined (SMPS)
01921 /**
01922   * @brief  Indicate whether the SMPS external supply is ready or not
01923   * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT
01924   * @retval State of bit (1 or 0).
01925   */
01926 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
01927 {
01928   return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
01929 }
01930 #endif /* SMPS */
01931
01932 /**
01933   * @brief  Indicate whether the USB supply is ready or not
01934   * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB
01935   * @retval State of bit (1 or 0).
01936   */
01937 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
01938 {
01939   return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
01940 }
01941
01942 #if defined (DUAL_CORE)
01943 /**
01944   * @brief  Get HOLD2 Flag
01945   * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2
01946   * @retval State of bit (1 or 0).
01947   */
01948 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
01949 {
01950   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
01951 }
01952
01953 /**
01954   * @brief  Get HOLD1 Flag
01955   * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1
01956   * @retval State of bit (1 or 0).
01957   */
01958 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
01959 {
01960   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
01961 }
01962 #endif /* DUAL_CORE */
01963
01964 /**
01965   * @brief  Get CPU System Stop Flag
01966   * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP
01967   * @retval State of bit (1 or 0).
01968   */
01969 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
01970 {
01971   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
01972 }
01973
01974 #if defined (DUAL_CORE)
01975 /**
01976   * @brief  Get CPU2 System Stop Flag
01977   * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP
01978   * @retval State of bit (1 or 0).
01979   */
01980 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
01981 {
01982   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
01983 }
01984 #endif /* DUAL_CORE */
01985
01986 /**
01987   * @brief  Get CPU System Standby Flag
01988   * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB
01989   * @retval State of bit (1 or 0).
01990   */
01991 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
01992 {
01993   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
01994 }
01995
01996 #if defined (DUAL_CORE)
01997 /**
01998   * @brief  Get CPU2 System Standby Flag
01999   * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB
02000   * @retval State of bit (1 or 0).
02001   */
02002 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
02003 {
02004   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
02005 }
02006 #endif /* DUAL_CORE */
02007
02008 #if defined (PWR_CPUCR_SBF_D1)
02009 /**
02010   * @brief  Get CPU D1 Domain Standby Flag
02011   * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1
02012   * @retval State of bit (1 or 0).
02013   */
02014 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
02015 {
02016   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
02017 }
02018 #endif /* PWR_CPUCR_SBF_D1 */
02019
02020 #if defined (DUAL_CORE)
02021 /**
02022   * @brief  Get CPU2 D1 Domain Standby Flag
02023   * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1
02024   * @retval State of bit (1 or 0).
02025   */
02026 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
02027 {
02028   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
02029 }
02030 #endif /* DUAL_CORE */
02031
02032 #if defined (PWR_CPUCR_SBF_D2)
02033 /**
02034   * @brief  Get CPU D2 Domain Standby Flag
02035   * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2
02036   * @retval State of bit (1 or 0).
02037   */
02038 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
02039 {
02040   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
02041 }
02042 #endif /* PWR_CPUCR_SBF_D2 */
02043
02044 #if defined (DUAL_CORE)
02045 /**
02046   * @brief  Get CPU2 D2 Domain Standby Flag
02047   * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2
02048   * @retval State of bit (1 or 0).
02049   */
02050 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
02051 {
02052   return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
02053 }
02054 #endif /* DUAL_CORE */
02055
02056
02057 /**
02058   * @brief  Indicate whether the Regulator is ready in the selected voltage range
02059   *         or if its output voltage is still changing to the required voltage level
02060   * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS
02061   * @retval State of bit (1 or 0).
02062   */
02063 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
02064 {
02065 #if defined (PWR_CPUCR_PDDS_D2)
02066   return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
02067 #else
02068   return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
02069 #endif /* PWR_CPUCR_PDDS_D2 */
02070 }
02071
02072 /**
02073   * @brief  Get Wake-up Flag 6
02074   * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6
02075   * @retval State of bit (1 or 0).
02076   */
02077 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
02078 {
02079   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
02080 }
02081
02082 /**
02083   * @brief  Get Wake-up Flag 5
02084   * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
02085   * @retval State of bit (1 or 0).
02086   */
02087 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
02088 {
02089   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
02090 }
02091
02092 /**
02093   * @brief  Get Wake-up Flag 4
02094   * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4
02095   * @retval State of bit (1 or 0).
02096   */
02097 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
02098 {
02099   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
02100 }
02101
02102 /**
02103   * @brief  Get Wake-up Flag 3
02104   * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
02105   * @retval State of bit (1 or 0).
02106   */
02107 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
02108 {
02109   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
02110 }
02111
02112 /**
02113   * @brief  Get Wake-up Flag 2
02114   * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2
02115   * @retval State of bit (1 or 0).
02116   */
02117 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
02118 {
02119   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
02120 }
02121
02122 /**
02123   * @brief  Get Wake-up Flag 1
02124   * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1
02125   * @retval State of bit (1 or 0).
02126   */
02127 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
02128 {
02129   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
02130 }
02131
02132 /**
02133   * @brief  Clear CPU STANDBY, STOP and HOLD flags
02134   * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
02138 {
02139   SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
02140 }
02141
02142 #if defined (DUAL_CORE)
02143 /**
02144   * @brief  Clear CPU2 STANDBY, STOP and HOLD flags
02145   * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2
02146   * @retval None
02147   */
02148 __STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
02149 {
02150   SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
02151 }
02152 #endif /* DUAL_CORE */
02153
02154 /**
02155   * @brief  Clear Wake-up Flag 6
02156   * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6
02157   * @retval None
02158   */
02159 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
02160 {
02161   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
02162 }
02163
02164 /**
02165   * @brief  Clear Wake-up Flag 5
02166   * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
02167   * @retval None
02168   */
02169 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
02170 {
02171   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
02172 }
02173
02174 /**
02175   * @brief  Clear Wake-up Flag 4
02176   * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4
02177   * @retval None
02178   */
02179 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
02180 {
02181   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
02182 }
02183
02184 /**
02185   * @brief  Clear Wake-up Flag 3
02186   * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
02187   * @retval None
02188   */
02189 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
02190 {
02191   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
02192 }
02193
02194 /**
02195   * @brief  Clear Wake-up Flag 2
02196   * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2
02197   * @retval None
02198   */
02199 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
02200 {
02201   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
02202 }
02203
02204 /**
02205   * @brief  Clear Wake-up Flag 1
02206   * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1
02207   * @retval None
02208   */
02209 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
02210 {
02211   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
02212 }
02213
02214 #if defined (USE_FULL_LL_DRIVER)
02215 /** @defgroup PWR_LL_EF_Init De-initialization function
02216   * @{
02217   */
02218 ErrorStatus LL_PWR_DeInit(void);
02219 /**
02220   * @}
02221   */
02222 #endif /* defined (USE_FULL_LL_DRIVER) */
02223
02224
02225 /**
02226   * @}
02227   */
02228
02229 /**
02230   * @}
02231   */
02232
02233 /**
02234   * @}
02235   */
02236
02237 #endif /* defined (PWR) */
02238
02239 /**
02240   * @}
02241   */
02242
02243 #ifdef __cplusplus
02244 }
02245 #endif
02246
02247 #endif /* STM32H7xx_LL_PWR_H */
02248
02249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rcc.c Source File

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stm32h7xx_ll_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_rcc.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025   #include "stm32_assert.h"
00026 #else
00027   #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(RCC)
00035
00036 /** @addtogroup RCC_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup RCC_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
00049                                             || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
00050
00051
00052 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
00053                                             || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
00054
00055 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
00056                                             || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
00057                                             || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
00058
00059 #if defined(LL_RCC_SAI4A_CLKSOURCE)
00060 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
00061                                             || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
00062                                             || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
00063                                             || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
00064 #else
00065 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
00066                                             || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
00067                                             || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
00068 #endif /* LL_RCC_SAI4A_CLKSOURCE */
00069
00070 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
00071                                             || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
00072                                             || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Private function prototypes -----------------------------------------------*/
00079 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00080   * @{
00081   */
00082 uint32_t RCC_GetSystemClockFreq(void);
00083 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00084 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00085 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00086 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
00087 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
00088
00089 /**
00090   * @}
00091   */
00092
00093
00094 /* Exported functions --------------------------------------------------------*/
00095 /** @addtogroup RCC_LL_Exported_Functions
00096   * @{
00097   */
00098
00099 /** @addtogroup RCC_LL_EF_Init
00100   * @{
00101   */
00102
00103 /**
00104   * @brief  Resets the RCC clock configuration to the default reset state.
00105   * @note   The default reset state of the clock configuration is given below:
00106   *            - HSI ON and used as system clock source
00107   *            - HSE, PLL1, PLL2 and PLL3 OFF
00108   *            - AHB, APB Bus pre-scaler set to 1.
00109   *            - CSS, MCO1 and MCO2 OFF
00110   *            - All interrupts disabled
00111   * @note   This function doesn't modify the configuration of the
00112   *            - Peripheral clocks
00113   *            - LSI, LSE and RTC clocks
00114   * @retval None
00115   */
00116 void LL_RCC_DeInit(void)
00117 {
00118   /* Set HSION bit */
00119   SET_BIT(RCC->CR, RCC_CR_HSION);
00120
00121   /* Wait for HSI READY bit */
00122   while(LL_RCC_HSI_IsReady() == 0U)
00123   {}
00124
00125   /* Reset CFGR register */
00126   CLEAR_REG(RCC->CFGR);
00127
00128   /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
00129   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
00130   |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
00131
00132   /* Wait for PLL1 READY bit to be reset */
00133   while(LL_RCC_PLL1_IsReady() != 0U)
00134   {}
00135
00136   /* Wait for PLL2 READY bit to be reset */
00137   while(LL_RCC_PLL2_IsReady() != 0U)
00138   {}
00139
00140   /* Wait for PLL3 READY bit to be reset */
00141   while(LL_RCC_PLL3_IsReady() != 0U)
00142   {}
00143
00144 #if defined(RCC_D1CFGR_HPRE)
00145   /* Reset D1CFGR register */
00146   CLEAR_REG(RCC->D1CFGR);
00147
00148   /* Reset D2CFGR register */
00149   CLEAR_REG(RCC->D2CFGR);
00150
00151   /* Reset D3CFGR register */
00152   CLEAR_REG(RCC->D3CFGR);
00153 #else
00154   /* Reset CDCFGR1 register */
00155   CLEAR_REG(RCC->CDCFGR1);
00156
00157   /* Reset CDCFGR2 register */
00158   CLEAR_REG(RCC->CDCFGR2);
00159
00160   /* Reset SRDCFGR register */
00161   CLEAR_REG(RCC->SRDCFGR);
00162
00163 #endif /* RCC_D1CFGR_HPRE */
00164
00165   /* Reset PLLCKSELR register to default value */
00166   RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
00167
00168   /* Reset PLLCFGR register to default value */
00169   LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
00170
00171   /* Reset PLL1DIVR register to default value */
00172   LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
00173
00174   /* Reset PLL1FRACR register */
00175   CLEAR_REG(RCC->PLL1FRACR);
00176
00177   /* Reset PLL2DIVR register to default value */
00178   LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
00179
00180   /* Reset PLL2FRACR register */
00181   CLEAR_REG(RCC->PLL2FRACR);
00182
00183   /* Reset PLL3DIVR register to default value */
00184   LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
00185
00186   /* Reset PLL3FRACR register */
00187   CLEAR_REG(RCC->PLL3FRACR);
00188
00189   /* Reset HSEBYP bit */
00190   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00191
00192   /* Disable all interrupts */
00193   CLEAR_REG(RCC->CIER);
00194
00195   /* Clear all interrupts */
00196   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
00197                    | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
00198                    | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
00199
00200   /* Clear reset source flags */
00201   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
00202 }
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @addtogroup RCC_LL_EF_Get_Freq
00209   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
00210   *         and different peripheral clocks available on the device.
00211   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00212   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
00213   * @note   If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
00214   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
00215   *         or HSI_VALUE(*) multiplied/divided by the PLL factors.
00216   * @note   (*) HSI_VALUE is a constant defined in header file (default value
00217   *             64 MHz) divider by HSIDIV, but the real value may vary depending on
00218   *             on the variations in voltage and temperature.
00219   * @note   (**) HSE_VALUE is a constant defined in header file (default value
00220   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
00221   *              frequency of the crystal used. Otherwise, this function may
00222   *              have wrong result.
00223   * @note   (***) CSI_VALUE is a constant defined in header file (default value
00224   *               4 MHz) but the real value may vary depending on the variations
00225   *               in voltage and temperature.
00226   * @note   The result of this function could be incorrect when using fractional
00227   *         value for HSE crystal.
00228   * @note   This function can be used by the user application to compute the
00229   *         baud-rate for the communication peripherals or configure other parameters.
00230   * @{
00231   */
00232
00233 /**
00234   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
00235   * @note   Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
00236   *         must be called to update structure fields. Otherwise, any
00237   *         configuration based on this function will be incorrect.
00238   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00239   * @retval None
00240   */
00241 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00242 {
00243   /* Get SYSCLK frequency */
00244   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00245
00246   /* HCLK clock frequency */
00247   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00248
00249   /* PCLK1 clock frequency */
00250   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00251
00252   /* PCLK2 clock frequency */
00253   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
00254
00255   /* PCLK3 clock frequency */
00256   RCC_Clocks->PCLK3_Frequency  = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
00257
00258   /* PCLK4 clock frequency */
00259   RCC_Clocks->PCLK4_Frequency  = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
00260 }
00261
00262 /**
00263   * @brief  Return PLL1 clocks frequencies
00264   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
00265   * @retval None
00266   */
00267 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
00268 {
00269   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
00270   uint32_t m, n, fracn = 0U;
00271
00272   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
00273      SYSCLK = PLL_VCO / PLLP
00274   */
00275   pllsource = LL_RCC_PLL_GetSource();
00276
00277   switch (pllsource)
00278   {
00279     case LL_RCC_PLLSOURCE_HSI:
00280       if (LL_RCC_HSI_IsReady() != 0U)
00281       {
00282         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00283       }
00284       break;
00285
00286     case LL_RCC_PLLSOURCE_CSI:
00287       if (LL_RCC_CSI_IsReady() != 0U)
00288       {
00289         pllinputfreq = CSI_VALUE;
00290       }
00291       break;
00292
00293     case LL_RCC_PLLSOURCE_HSE:
00294       if (LL_RCC_HSE_IsReady() != 0U)
00295       {
00296         pllinputfreq = HSE_VALUE;
00297       }
00298       break;
00299
00300     case LL_RCC_PLLSOURCE_NONE:
00301     default:
00302       /* PLL clock disabled */
00303       break;
00304   }
00305
00306   PLL_Clocks->PLL_P_Frequency = 0U;
00307   PLL_Clocks->PLL_Q_Frequency = 0U;
00308   PLL_Clocks->PLL_R_Frequency = 0U;
00309
00310   m = LL_RCC_PLL1_GetM();
00311   n = LL_RCC_PLL1_GetN();
00312   if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
00313   {
00314     fracn = LL_RCC_PLL1_GetFRACN();
00315   }
00316
00317   if (m != 0U)
00318   {
00319     if (LL_RCC_PLL1P_IsEnabled() != 0U)
00320     {
00321       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
00322     }
00323
00324     if (LL_RCC_PLL1Q_IsEnabled() != 0U)
00325     {
00326       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
00327     }
00328
00329     if (LL_RCC_PLL1R_IsEnabled() != 0U)
00330     {
00331       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
00332     }
00333   }
00334 }
00335
00336 /**
00337   * @brief  Return PLL2 clocks frequencies
00338   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
00339   * @retval None
00340   */
00341 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
00342 {
00343   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
00344   uint32_t m, n, fracn = 0U;
00345
00346   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
00347      SYSCLK = PLL_VCO / PLLP
00348   */
00349   pllsource = LL_RCC_PLL_GetSource();
00350
00351   switch (pllsource)
00352   {
00353     case LL_RCC_PLLSOURCE_HSI:
00354       if (LL_RCC_HSI_IsReady() != 0U)
00355       {
00356         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00357       }
00358       break;
00359
00360     case LL_RCC_PLLSOURCE_CSI:
00361       if (LL_RCC_CSI_IsReady() != 0U)
00362       {
00363         pllinputfreq = CSI_VALUE;
00364       }
00365       break;
00366
00367     case LL_RCC_PLLSOURCE_HSE:
00368       if (LL_RCC_HSE_IsReady() != 0U)
00369       {
00370         pllinputfreq = HSE_VALUE;
00371       }
00372       break;
00373
00374     case LL_RCC_PLLSOURCE_NONE:
00375     default:
00376       /* PLL clock disabled */
00377       break;
00378   }
00379
00380   PLL_Clocks->PLL_P_Frequency = 0U;
00381   PLL_Clocks->PLL_Q_Frequency = 0U;
00382   PLL_Clocks->PLL_R_Frequency = 0U;
00383
00384   m = LL_RCC_PLL2_GetM();
00385   n = LL_RCC_PLL2_GetN();
00386   if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
00387   {
00388     fracn = LL_RCC_PLL2_GetFRACN();
00389   }
00390
00391   if (m != 0U)
00392   {
00393     if (LL_RCC_PLL2P_IsEnabled() != 0U)
00394     {
00395       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
00396     }
00397
00398     if (LL_RCC_PLL2Q_IsEnabled() != 0U)
00399     {
00400       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
00401     }
00402
00403     if (LL_RCC_PLL2R_IsEnabled() != 0U)
00404     {
00405       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
00406     }
00407   }
00408 }
00409
00410 /**
00411   * @brief  Return PLL3 clocks frequencies
00412   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
00413   * @retval None
00414   */
00415 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
00416 {
00417   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
00418   uint32_t m, n, fracn = 0U;
00419
00420   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
00421      SYSCLK = PLL_VCO / PLLP
00422   */
00423   pllsource = LL_RCC_PLL_GetSource();
00424
00425   switch (pllsource)
00426   {
00427     case LL_RCC_PLLSOURCE_HSI:
00428       if (LL_RCC_HSI_IsReady() != 0U)
00429       {
00430         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00431       }
00432       break;
00433
00434     case LL_RCC_PLLSOURCE_CSI:
00435       if (LL_RCC_CSI_IsReady() != 0U)
00436       {
00437         pllinputfreq = CSI_VALUE;
00438       }
00439       break;
00440
00441     case LL_RCC_PLLSOURCE_HSE:
00442       if (LL_RCC_HSE_IsReady() != 0U)
00443       {
00444         pllinputfreq = HSE_VALUE;
00445       }
00446       break;
00447
00448     case LL_RCC_PLLSOURCE_NONE:
00449     default:
00450       /* PLL clock disabled */
00451       break;
00452   }
00453
00454   PLL_Clocks->PLL_P_Frequency = 0U;
00455   PLL_Clocks->PLL_Q_Frequency = 0U;
00456   PLL_Clocks->PLL_R_Frequency = 0U;
00457
00458   m = LL_RCC_PLL3_GetM();
00459   n = LL_RCC_PLL3_GetN();
00460   if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
00461   {
00462     fracn = LL_RCC_PLL3_GetFRACN();
00463   }
00464
00465   if ((m != 0U) && (pllinputfreq != 0U))
00466   {
00467     if (LL_RCC_PLL3P_IsEnabled() != 0U)
00468     {
00469       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
00470     }
00471
00472     if (LL_RCC_PLL3Q_IsEnabled() != 0U)
00473     {
00474       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
00475     }
00476
00477     if (LL_RCC_PLL3R_IsEnabled() != 0U)
00478     {
00479       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
00480     }
00481   }
00482 }
00483
00484 /**
00485   * @brief  Helper function to calculate the PLL frequency output
00486   * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
00487   *             @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
00488   * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
00489   * @param  M      Between 1 and 63
00490   * @param  N      Between 4 and 512
00491   * @param  FRACN  Between 0 and 0x1FFF
00492   * @param  PQR    VCO output divider (P, Q or R)
00493   *                Between 1 and 128, except for PLL1P Odd value not allowed
00494   * @retval PLL1 clock frequency (in Hz)
00495   */
00496 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
00497 {
00498   float_t freq;
00499
00500   freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
00501
00502   freq = freq/(float_t)PQR;
00503
00504   return (uint32_t)freq;
00505 }
00506
00507 /**
00508   * @brief  Return USARTx clock frequency
00509   * @param  USARTxSource This parameter can be one of the following values:
00510   *         @arg @ref LL_RCC_USART16_CLKSOURCE
00511   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
00512   * @retval USART clock frequency (in Hz)
00513   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00514   */
00515 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00516 {
00517   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00518   LL_PLL_ClocksTypeDef PLL_Clocks;
00519
00520   /* Check parameter */
00521   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00522
00523   switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00524   {
00525     case LL_RCC_USART16_CLKSOURCE_PCLK2:
00526       usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00527       break;
00528
00529     case LL_RCC_USART234578_CLKSOURCE_PCLK1:
00530       usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00531       break;
00532
00533     case LL_RCC_USART16_CLKSOURCE_PLL2Q:
00534     case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
00535       if (LL_RCC_PLL2_IsReady() != 0U)
00536       {
00537         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00538         usart_frequency = PLL_Clocks.PLL_Q_Frequency;
00539       }
00540       break;
00541
00542     case LL_RCC_USART16_CLKSOURCE_PLL3Q:
00543     case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
00544       if (LL_RCC_PLL3_IsReady() != 0U)
00545       {
00546         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00547         usart_frequency = PLL_Clocks.PLL_Q_Frequency;
00548       }
00549       break;
00550
00551     case LL_RCC_USART16_CLKSOURCE_HSI:
00552     case LL_RCC_USART234578_CLKSOURCE_HSI:
00553       if (LL_RCC_HSI_IsReady() != 0U)
00554       {
00555         usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00556       }
00557       break;
00558
00559     case LL_RCC_USART16_CLKSOURCE_CSI:
00560     case LL_RCC_USART234578_CLKSOURCE_CSI:
00561       if (LL_RCC_CSI_IsReady() != 0U)
00562       {
00563         usart_frequency = CSI_VALUE;
00564       }
00565       break;
00566
00567     case LL_RCC_USART16_CLKSOURCE_LSE:
00568     case LL_RCC_USART234578_CLKSOURCE_LSE:
00569       if (LL_RCC_LSE_IsReady() != 0U)
00570       {
00571         usart_frequency = LSE_VALUE;
00572       }
00573       break;
00574
00575     default:
00576       /* Kernel clock disabled */
00577       break;
00578   }
00579
00580   return usart_frequency;
00581 }
00582
00583 /**
00584   * @brief  Return LPUART clock frequency
00585   * @param  LPUARTxSource This parameter can be one of the following values:
00586   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
00587   * @retval LPUART clock frequency (in Hz)
00588   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00589   */
00590 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
00591 {
00592   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00593   LL_PLL_ClocksTypeDef PLL_Clocks;
00594
00595   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00596   {
00597     case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
00598       lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00599       break;
00600
00601     case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
00602       if (LL_RCC_PLL2_IsReady() != 0U)
00603       {
00604         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00605         lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
00606       }
00607       break;
00608
00609     case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
00610       if (LL_RCC_PLL3_IsReady() != 0U)
00611       {
00612         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00613         lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
00614       }
00615       break;
00616
00617     case LL_RCC_LPUART1_CLKSOURCE_HSI:
00618       if (LL_RCC_HSI_IsReady() != 0U)
00619       {
00620         lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00621       }
00622       break;
00623
00624     case LL_RCC_LPUART1_CLKSOURCE_CSI:
00625       if (LL_RCC_CSI_IsReady() != 0U)
00626       {
00627         lpuart_frequency = CSI_VALUE;
00628       }
00629       break;
00630
00631     case LL_RCC_LPUART1_CLKSOURCE_LSE:
00632       if (LL_RCC_LSE_IsReady() != 0U)
00633       {
00634         lpuart_frequency = LSE_VALUE;
00635       }
00636       break;
00637
00638     default:
00639       /* Kernel clock disabled */
00640       break;
00641   }
00642
00643   return lpuart_frequency;
00644 }
00645
00646 /**
00647   * @brief  Return I2Cx clock frequency
00648   * @param  I2CxSource This parameter can be one of the following values:
00649   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
00650   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
00651   * @retval I2C clock frequency (in Hz)
00652   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00653   */
00654 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00655 {
00656   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00657   LL_PLL_ClocksTypeDef PLL_Clocks;
00658
00659   /* Check parameter */
00660   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00661
00662   switch (LL_RCC_GetI2CClockSource(I2CxSource))
00663   {
00664     case LL_RCC_I2C123_CLKSOURCE_PCLK1:
00665       i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00666       break;
00667
00668     case LL_RCC_I2C4_CLKSOURCE_PCLK4:
00669       i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00670       break;
00671
00672     case LL_RCC_I2C123_CLKSOURCE_PLL3R:
00673     case LL_RCC_I2C4_CLKSOURCE_PLL3R:
00674       if (LL_RCC_PLL3_IsReady() != 0U)
00675       {
00676         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00677         i2c_frequency = PLL_Clocks.PLL_R_Frequency;
00678       }
00679       break;
00680
00681     case LL_RCC_I2C123_CLKSOURCE_HSI:
00682     case LL_RCC_I2C4_CLKSOURCE_HSI:
00683       if (LL_RCC_HSI_IsReady() != 0U)
00684       {
00685         i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
00686       }
00687       break;
00688
00689     case LL_RCC_I2C123_CLKSOURCE_CSI:
00690     case LL_RCC_I2C4_CLKSOURCE_CSI:
00691       if (LL_RCC_CSI_IsReady() != 0U)
00692       {
00693         i2c_frequency = CSI_VALUE;
00694       }
00695       break;
00696
00697     default:
00698       /* Nothing to do */
00699       break;
00700   }
00701
00702   return i2c_frequency;
00703 }
00704
00705 /**
00706   * @brief  Return LPTIMx clock frequency
00707   * @param  LPTIMxSource This parameter can be one of the following values:
00708   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
00709   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
00710   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
00711   * @retval LPTIM clock frequency (in Hz)
00712   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00713   */
00714 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
00715 {
00716   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00717   LL_PLL_ClocksTypeDef PLL_Clocks;
00718
00719   /* Check parameter */
00720   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
00721
00722   switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00723   {
00724     case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
00725       lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00726       break;
00727
00728     case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
00729     case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
00730       lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
00731       break;
00732
00733     case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
00734     case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
00735     case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
00736       if (LL_RCC_PLL2_IsReady() != 0U)
00737       {
00738         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00739         lptim_frequency = PLL_Clocks.PLL_P_Frequency;
00740       }
00741       break;
00742
00743     case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
00744     case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
00745     case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
00746       if (LL_RCC_PLL3_IsReady() != 0U)
00747       {
00748         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00749         lptim_frequency = PLL_Clocks.PLL_R_Frequency;
00750       }
00751       break;
00752
00753     case LL_RCC_LPTIM1_CLKSOURCE_LSE:
00754     case LL_RCC_LPTIM2_CLKSOURCE_LSE:
00755     case LL_RCC_LPTIM345_CLKSOURCE_LSE:
00756       if (LL_RCC_LSE_IsReady() != 0U)
00757       {
00758         lptim_frequency = LSE_VALUE;
00759       }
00760       break;
00761
00762     case LL_RCC_LPTIM1_CLKSOURCE_LSI:
00763     case LL_RCC_LPTIM2_CLKSOURCE_LSI:
00764     case LL_RCC_LPTIM345_CLKSOURCE_LSI:
00765       if (LL_RCC_LSI_IsReady() != 0U)
00766       {
00767         lptim_frequency = LSI_VALUE;
00768       }
00769       break;
00770
00771     case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
00772     case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
00773     case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
00774       lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
00775       break;
00776
00777     default:
00778       /* Kernel clock disabled */
00779       break;
00780   }
00781
00782   return lptim_frequency;
00783 }
00784
00785 /**
00786   * @brief  Return SAIx clock frequency
00787   * @param  SAIxSource This parameter can be one of the following values:
00788   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
00789   *         @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
00790   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
00791   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
00792   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
00793   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
00794   * @retval SAI clock frequency (in Hz)
00795   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00796   *
00797   * (*) : Available on some STM32H7 lines only.
00798   */
00799 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
00800 {
00801   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00802   LL_PLL_ClocksTypeDef PLL_Clocks;
00803
00804   /* Check parameter */
00805   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
00806
00807   switch (LL_RCC_GetSAIClockSource(SAIxSource))
00808   {
00809     case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
00810 #if defined(SAI3)
00811     case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
00812 #endif /* SAI3 */
00813 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
00814     case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
00815     case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
00816 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
00817 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
00818     case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
00819     case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
00820 #endif /* (SAI4_Block_A) || (SAI4_Block_B) */
00821       if (LL_RCC_PLL1_IsReady() != 0U)
00822       {
00823         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
00824         sai_frequency = PLL_Clocks.PLL_Q_Frequency;
00825       }
00826       break;
00827
00828     case LL_RCC_SAI1_CLKSOURCE_PLL2P:
00829 #if defined(SAI3)
00830     case LL_RCC_SAI23_CLKSOURCE_PLL2P:
00831 #endif /* SAI3 */
00832 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
00833     case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
00834     case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
00835 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
00836 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
00837     case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
00838     case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
00839 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
00840       if (LL_RCC_PLL2_IsReady() != 0U)
00841       {
00842         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00843         sai_frequency = PLL_Clocks.PLL_P_Frequency;
00844       }
00845       break;
00846
00847     case LL_RCC_SAI1_CLKSOURCE_PLL3P:
00848 #if defined(SAI3)
00849     case LL_RCC_SAI23_CLKSOURCE_PLL3P:
00850 #endif /* SAI3 */
00851 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
00852     case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
00853     case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
00854 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
00855 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
00856     case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
00857     case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
00858 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
00859       if (LL_RCC_PLL3_IsReady() != 0U)
00860       {
00861         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00862         sai_frequency = PLL_Clocks.PLL_P_Frequency;
00863       }
00864       break;
00865
00866     case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
00867 #if defined(SAI3)
00868     case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
00869 #endif /* SAI3 */
00870 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
00871     case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
00872     case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
00873 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
00874 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
00875     case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
00876     case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
00877 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
00878       sai_frequency = EXTERNAL_CLOCK_VALUE;
00879       break;
00880
00881     case LL_RCC_SAI1_CLKSOURCE_CLKP:
00882 #if defined(SAI3)
00883     case LL_RCC_SAI23_CLKSOURCE_CLKP:
00884 #endif /* SAI3 */
00885 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
00886     case LL_RCC_SAI2A_CLKSOURCE_CLKP:
00887     case LL_RCC_SAI2B_CLKSOURCE_CLKP:
00888 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
00889 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
00890     case LL_RCC_SAI4A_CLKSOURCE_CLKP:
00891     case LL_RCC_SAI4B_CLKSOURCE_CLKP:
00892 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
00893       sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
00894       break;
00895
00896     default:
00897       /* Kernel clock disabled */
00898       break;
00899   }
00900
00901   return sai_frequency;
00902 }
00903
00904 /**
00905   * @brief  Return ADC clock frequency
00906   * @param  ADCxSource This parameter can be one of the following values:
00907   *         @arg @ref LL_RCC_ADC_CLKSOURCE
00908   * @retval ADC clock frequency (in Hz)
00909   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00910   */
00911 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00912 {
00913   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00914   LL_PLL_ClocksTypeDef PLL_Clocks;
00915
00916   switch (LL_RCC_GetADCClockSource(ADCxSource))
00917   {
00918     case LL_RCC_ADC_CLKSOURCE_PLL2P:
00919       if (LL_RCC_PLL2_IsReady() != 0U)
00920       {
00921         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00922         adc_frequency = PLL_Clocks.PLL_P_Frequency;
00923       }
00924       break;
00925
00926     case LL_RCC_ADC_CLKSOURCE_PLL3R:
00927       if (LL_RCC_PLL3_IsReady() != 0U)
00928       {
00929         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
00930         adc_frequency = PLL_Clocks.PLL_R_Frequency;
00931       }
00932       break;
00933
00934     case LL_RCC_ADC_CLKSOURCE_CLKP:
00935       adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
00936       break;
00937
00938     default:
00939       /* Kernel clock disabled */
00940       break;
00941   }
00942
00943   return adc_frequency;
00944 }
00945
00946 /**
00947   * @brief  Return SDMMC clock frequency
00948   * @param  SDMMCxSource This parameter can be one of the following values:
00949   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
00950   * @retval SDMMC clock frequency (in Hz)
00951   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00952   */
00953 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
00954 {
00955   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00956   LL_PLL_ClocksTypeDef PLL_Clocks;
00957
00958   switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
00959   {
00960     case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
00961       if (LL_RCC_PLL1_IsReady() != 0U)
00962       {
00963         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
00964         sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
00965       }
00966       break;
00967
00968     case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
00969       if (LL_RCC_PLL2_IsReady() != 0U)
00970       {
00971         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
00972         sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
00973       }
00974       break;
00975
00976     default:
00977       /* Nothing to do */
00978       break;
00979   }
00980
00981   return sdmmc_frequency;
00982 }
00983
00984 /**
00985   * @brief  Return RNG clock frequency
00986   * @param  RNGxSource This parameter can be one of the following values:
00987   *         @arg @ref LL_RCC_RNG_CLKSOURCE
00988   * @retval RNG clock frequency (in Hz)
00989   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00990   */
00991 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
00992 {
00993   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00994   LL_PLL_ClocksTypeDef PLL_Clocks;
00995
00996   switch (LL_RCC_GetRNGClockSource(RNGxSource))
00997   {
00998     case LL_RCC_RNG_CLKSOURCE_PLL1Q:
00999       if (LL_RCC_PLL1_IsReady() != 0U)
01000       {
01001         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01002         rng_frequency = PLL_Clocks.PLL_Q_Frequency;
01003       }
01004       break;
01005
01006     case LL_RCC_RNG_CLKSOURCE_HSI48:
01007       if (LL_RCC_HSI48_IsReady() != 0U)
01008       {
01009         rng_frequency = 48000000U;
01010       }
01011       break;
01012
01013     case LL_RCC_RNG_CLKSOURCE_LSE:
01014       if (LL_RCC_LSE_IsReady() != 0U)
01015       {
01016         rng_frequency = LSE_VALUE;
01017       }
01018       break;
01019
01020     case LL_RCC_RNG_CLKSOURCE_LSI:
01021       if (LL_RCC_LSI_IsReady() != 0U)
01022       {
01023         rng_frequency = LSI_VALUE;
01024       }
01025       break;
01026
01027     default:
01028       /* Nothing to do */
01029       break;
01030   }
01031
01032   return rng_frequency;
01033 }
01034
01035 /**
01036   * @brief  Return CEC clock frequency
01037   * @param  CECxSource This parameter can be one of the following values:
01038   *         @arg @ref LL_RCC_RNG_CLKSOURCE
01039   * @retval CEC clock frequency (in Hz)
01040   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01041   */
01042 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
01043 {
01044   uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01045
01046   switch (LL_RCC_GetCECClockSource(CECxSource))
01047   {
01048     case LL_RCC_CEC_CLKSOURCE_LSE:
01049       if (LL_RCC_LSE_IsReady() != 0U)
01050       {
01051         cec_frequency = LSE_VALUE;
01052       }
01053       break;
01054
01055     case LL_RCC_CEC_CLKSOURCE_LSI:
01056       if (LL_RCC_LSI_IsReady() != 0U)
01057       {
01058         cec_frequency = LSI_VALUE;
01059       }
01060       break;
01061
01062     case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
01063       if (LL_RCC_CSI_IsReady() != 0U)
01064       {
01065         cec_frequency = CSI_VALUE / 122U;
01066       }
01067       break;
01068
01069     default:
01070       /* Kernel clock disabled */
01071       break;
01072   }
01073
01074   return cec_frequency;
01075 }
01076
01077 /**
01078   * @brief  Return USB clock frequency
01079   * @param  USBxSource This parameter can be one of the following values:
01080   *         @arg @ref LL_RCC_USB_CLKSOURCE
01081   * @retval USB clock frequency (in Hz)
01082   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
01083   */
01084 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
01085 {
01086   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01087   LL_PLL_ClocksTypeDef PLL_Clocks;
01088
01089   switch (LL_RCC_GetUSBClockSource(USBxSource))
01090   {
01091     case LL_RCC_USB_CLKSOURCE_PLL1Q:
01092       if (LL_RCC_PLL1_IsReady() != 0U)
01093       {
01094         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01095         usb_frequency = PLL_Clocks.PLL_Q_Frequency;
01096       }
01097       break;
01098
01099     case LL_RCC_USB_CLKSOURCE_PLL3Q:
01100       if (LL_RCC_PLL3_IsReady() != 0U)
01101       {
01102         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
01103         usb_frequency = PLL_Clocks.PLL_Q_Frequency;
01104       }
01105       break;
01106
01107     case LL_RCC_USB_CLKSOURCE_HSI48:
01108       if (LL_RCC_HSI48_IsReady() != 0U)
01109       {
01110         usb_frequency = HSI48_VALUE;
01111       }
01112       break;
01113
01114     case LL_RCC_USB_CLKSOURCE_DISABLE:
01115     default:
01116       /* Nothing to do */
01117       break;
01118   }
01119
01120   return usb_frequency;
01121 }
01122
01123 /**
01124   * @brief  Return DFSDM clock frequency
01125   * @param  DFSDMxSource This parameter can be one of the following values:
01126   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
01127   * @retval DFSDM clock frequency (in Hz)
01128   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01129   */
01130 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
01131 {
01132   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01133
01134   switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
01135   {
01136     case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
01137       dfsdm_frequency = RCC_GetSystemClockFreq();
01138       break;
01139
01140     case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
01141       dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
01142       break;
01143
01144     default:
01145       /* Nothing to do */
01146       break;
01147   }
01148
01149   return dfsdm_frequency;
01150 }
01151
01152 #if defined(DFSDM2_BASE)
01153 /**
01154   * @brief  Return DFSDM clock frequency
01155   * @param  DFSDMxSource This parameter can be one of the following values:
01156   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
01157   * @retval DFSDM clock frequency (in Hz)
01158   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01159   */
01160 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
01161 {
01162   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01163
01164
01165   switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
01166   {
01167
01168     case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
01169       dfsdm_frequency = RCC_GetSystemClockFreq();
01170       break;
01171
01172     case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
01173       dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
01174       break;
01175
01176     default:
01177       /* Nothing to do */
01178       break;
01179   }
01180
01181   return dfsdm_frequency;
01182 }
01183 #endif /* DFSDM2_BASE */
01184
01185 #if defined(DSI)
01186 /**
01187   * @brief  Return DSI clock frequency
01188   * @param  DSIxSource This parameter can be one of the following values:
01189   *         @arg @ref LL_RCC_DSI_CLKSOURCE
01190   * @retval DSI clock frequency (in Hz)
01191   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01192   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
01193   */
01194 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
01195 {
01196   uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01197   LL_PLL_ClocksTypeDef PLL_Clocks;
01198
01199   switch (LL_RCC_GetDSIClockSource(DSIxSource))
01200   {
01201     case LL_RCC_DSI_CLKSOURCE_PLL2Q:
01202       if (LL_RCC_PLL2_IsReady() != 0U)
01203       {
01204         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01205         dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
01206       }
01207       break;
01208
01209     case LL_RCC_DSI_CLKSOURCE_PHY:
01210       dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
01211       break;
01212
01213     default:
01214       /* Nothing to do */
01215       break;
01216   }
01217
01218   return dsi_frequency;
01219 }
01220 #endif /* DSI */
01221
01222 /**
01223   * @brief  Return SPDIF clock frequency
01224   * @param  SPDIFxSource This parameter can be one of the following values:
01225   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
01226   * @retval SPDIF clock frequency (in Hz)
01227   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01228   */
01229 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
01230 {
01231   uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01232   LL_PLL_ClocksTypeDef PLL_Clocks;
01233
01234   switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
01235   {
01236     case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
01237       if (LL_RCC_PLL1_IsReady() != 0U)
01238       {
01239         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01240         spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
01241       }
01242       break;
01243
01244     case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
01245       if (LL_RCC_PLL2_IsReady() != 0U)
01246       {
01247         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01248         spdif_frequency = PLL_Clocks.PLL_R_Frequency;
01249       }
01250       break;
01251
01252     case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
01253       if (LL_RCC_PLL3_IsReady() != 0U)
01254       {
01255         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
01256         spdif_frequency = PLL_Clocks.PLL_R_Frequency;
01257       }
01258       break;
01259
01260     case LL_RCC_SPDIF_CLKSOURCE_HSI:
01261       if (LL_RCC_HSI_IsReady() != 0U)
01262       {
01263         spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
01264       }
01265       break;
01266
01267     default:
01268       /* Nothing to do */
01269       break;
01270   }
01271
01272   return spdif_frequency;
01273 }
01274
01275 /**
01276   * @brief  Return SPIx clock frequency
01277   * @param  SPIxSource This parameter can be one of the following values:
01278   *         @arg @ref LL_RCC_SPI123_CLKSOURCE
01279   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
01280   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
01281   * @retval SPI clock frequency (in Hz)
01282   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01283   */
01284 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
01285 {
01286   uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01287   LL_PLL_ClocksTypeDef PLL_Clocks;
01288
01289   /* Check parameter */
01290   assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
01291
01292   switch (LL_RCC_GetSPIClockSource(SPIxSource))
01293   {
01294     case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
01295       if (LL_RCC_PLL1_IsReady() != 0U)
01296       {
01297         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01298         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
01299       }
01300       break;
01301
01302     case LL_RCC_SPI123_CLKSOURCE_PLL2P:
01303       if (LL_RCC_PLL2_IsReady() != 0U)
01304       {
01305         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01306         spi_frequency = PLL_Clocks.PLL_P_Frequency;
01307       }
01308       break;
01309
01310     case LL_RCC_SPI123_CLKSOURCE_PLL3P:
01311       if (LL_RCC_PLL3_IsReady() != 0U)
01312       {
01313         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
01314         spi_frequency = PLL_Clocks.PLL_P_Frequency;
01315       }
01316       break;
01317
01318     case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
01319 #if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
01320     case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
01321 #endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
01322       spi_frequency = EXTERNAL_CLOCK_VALUE;
01323       break;
01324
01325     case LL_RCC_SPI123_CLKSOURCE_CLKP:
01326       spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
01327       break;
01328
01329     case LL_RCC_SPI45_CLKSOURCE_PCLK2:
01330       spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
01331       break;
01332
01333     case LL_RCC_SPI6_CLKSOURCE_PCLK4:
01334       spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
01335       break;
01336
01337     case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
01338     case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
01339       if (LL_RCC_PLL2_IsReady() != 0U)
01340       {
01341         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01342         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
01343       }
01344       break;
01345
01346     case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
01347     case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
01348       if (LL_RCC_PLL3_IsReady() != 0U)
01349       {
01350         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
01351         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
01352       }
01353       break;
01354
01355     case LL_RCC_SPI45_CLKSOURCE_HSI:
01356     case LL_RCC_SPI6_CLKSOURCE_HSI:
01357       if (LL_RCC_HSI_IsReady() != 0U)
01358       {
01359         spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
01360       }
01361       break;
01362
01363     case LL_RCC_SPI45_CLKSOURCE_CSI:
01364     case LL_RCC_SPI6_CLKSOURCE_CSI:
01365       if (LL_RCC_CSI_IsReady() != 0U)
01366       {
01367         spi_frequency = CSI_VALUE;
01368       }
01369       break;
01370
01371     case LL_RCC_SPI45_CLKSOURCE_HSE:
01372     case LL_RCC_SPI6_CLKSOURCE_HSE:
01373       if (LL_RCC_HSE_IsReady() != 0U)
01374       {
01375         spi_frequency = HSE_VALUE;
01376       }
01377       break;
01378
01379     default:
01380       /* Kernel clock disabled */
01381       break;
01382   }
01383
01384   return spi_frequency;
01385 }
01386
01387 /**
01388   * @brief  Return SWP clock frequency
01389   * @param  SWPxSource This parameter can be one of the following values:
01390   *         @arg @ref LL_RCC_SWP_CLKSOURCE
01391   * @retval SWP clock frequency (in Hz)
01392   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01393   */
01394 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
01395 {
01396   uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01397
01398   switch (LL_RCC_GetSWPClockSource(SWPxSource))
01399   {
01400     case LL_RCC_SWP_CLKSOURCE_PCLK1:
01401       swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
01402       break;
01403
01404     case LL_RCC_SWP_CLKSOURCE_HSI:
01405       if (LL_RCC_HSI_IsReady() != 0U)
01406       {
01407         swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
01408       }
01409       break;
01410
01411     default:
01412       /* Nothing to do */
01413       break;
01414   }
01415
01416   return swp_frequency;
01417 }
01418
01419 /**
01420   * @brief  Return FDCAN clock frequency
01421   * @param  FDCANxSource This parameter can be one of the following values:
01422   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
01423   * @retval FDCAN clock frequency (in Hz)
01424   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01425   */
01426 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
01427 {
01428   uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01429   LL_PLL_ClocksTypeDef PLL_Clocks;
01430
01431   switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
01432   {
01433     case LL_RCC_FDCAN_CLKSOURCE_HSE:
01434       if (LL_RCC_HSE_IsReady() != 0U)
01435       {
01436         fdcan_frequency = HSE_VALUE;
01437       }
01438       break;
01439
01440     case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
01441       if (LL_RCC_PLL1_IsReady() != 0U)
01442       {
01443         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01444         fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
01445       }
01446       break;
01447
01448     case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
01449       if (LL_RCC_PLL2_IsReady() != 0U)
01450       {
01451         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01452         fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
01453       }
01454       break;
01455
01456     default:
01457       /* Kernel clock disabled */
01458       break;
01459   }
01460
01461   return fdcan_frequency;
01462 }
01463
01464 /**
01465   * @brief  Return FMC clock frequency
01466   * @param  FMCxSource This parameter can be one of the following values:
01467   *         @arg @ref LL_RCC_FMC_CLKSOURCE
01468   * @retval FMC clock frequency (in Hz)
01469   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01470   */
01471 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
01472 {
01473   uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01474   LL_PLL_ClocksTypeDef PLL_Clocks;
01475
01476   switch (LL_RCC_GetFMCClockSource(FMCxSource))
01477   {
01478     case LL_RCC_FMC_CLKSOURCE_HCLK:
01479       fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
01480       break;
01481
01482     case LL_RCC_FMC_CLKSOURCE_PLL1Q:
01483       if (LL_RCC_PLL1_IsReady() != 0U)
01484       {
01485         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01486         fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
01487       }
01488       break;
01489
01490     case LL_RCC_FMC_CLKSOURCE_PLL2R:
01491       if (LL_RCC_PLL2_IsReady() != 0U)
01492       {
01493         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01494         fmc_frequency = PLL_Clocks.PLL_R_Frequency;
01495       }
01496       break;
01497
01498     case LL_RCC_FMC_CLKSOURCE_CLKP:
01499       fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
01500       break;
01501
01502     default:
01503       /* Nothing to do */
01504       break;
01505   }
01506
01507   return fmc_frequency;
01508 }
01509
01510 #if defined(QUADSPI)
01511 /**
01512   * @brief  Return QSPI clock frequency
01513   * @param  QSPIxSource This parameter can be one of the following values:
01514   *         @arg @ref LL_RCC_QSPI_CLKSOURCE
01515   * @retval QSPI clock frequency (in Hz)
01516   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01517   */
01518 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
01519 {
01520   uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01521   LL_PLL_ClocksTypeDef PLL_Clocks;
01522
01523   switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
01524   {
01525     case LL_RCC_QSPI_CLKSOURCE_HCLK:
01526       qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
01527       break;
01528
01529     case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
01530       if (LL_RCC_PLL1_IsReady() != 0U)
01531       {
01532         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01533         qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
01534       }
01535       break;
01536
01537     case LL_RCC_QSPI_CLKSOURCE_PLL2R:
01538       if (LL_RCC_PLL2_IsReady() != 0U)
01539       {
01540         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01541         qspi_frequency = PLL_Clocks.PLL_R_Frequency;
01542       }
01543       break;
01544
01545     case LL_RCC_QSPI_CLKSOURCE_CLKP:
01546       qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
01547       break;
01548
01549     default:
01550       /* Nothing to do */
01551       break;
01552   }
01553
01554   return qspi_frequency;
01555 }
01556 #endif /* QUADSPI */
01557
01558 #if defined(OCTOSPI1) || defined(OCTOSPI2)
01559 /**
01560   * @brief  Return OSPI clock frequency
01561   * @param  QSPIxSource This parameter can be one of the following values:
01562   *         @arg @ref LL_RCC_OSPI_CLKSOURCE
01563   * @retval OSPI clock frequency (in Hz)
01564   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01565   */
01566
01567 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
01568 {
01569   uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01570   LL_PLL_ClocksTypeDef PLL_Clocks;
01571
01572   switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
01573   {
01574     case LL_RCC_OSPI_CLKSOURCE_HCLK:
01575       ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
01576       break;
01577
01578     case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
01579       if (LL_RCC_PLL1_IsReady() != 0U)
01580       {
01581         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01582         ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
01583       }
01584       break;
01585
01586     case LL_RCC_OSPI_CLKSOURCE_PLL2R:
01587       if (LL_RCC_PLL2_IsReady() != 0U)
01588       {
01589         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
01590         ospi_frequency = PLL_Clocks.PLL_R_Frequency;
01591       }
01592       break;
01593
01594     case LL_RCC_OSPI_CLKSOURCE_CLKP:
01595       ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
01596       break;
01597
01598     default:
01599       /* Nothing to do */
01600       break;
01601   }
01602
01603   return ospi_frequency;
01604 }
01605 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
01606
01607 /**
01608   * @brief  Return CLKP clock frequency
01609   * @param  CLKPxSource This parameter can be one of the following values:
01610   *         @arg @ref LL_RCC_CLKP_CLKSOURCE
01611   * @retval CLKP clock frequency (in Hz)
01612   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
01613   */
01614 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
01615 {
01616   uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01617
01618   switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
01619   {
01620     case LL_RCC_CLKP_CLKSOURCE_HSI:
01621       if (LL_RCC_HSI_IsReady() != 0U)
01622       {
01623         clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
01624       }
01625       break;
01626
01627     case LL_RCC_CLKP_CLKSOURCE_CSI:
01628       if (LL_RCC_CSI_IsReady() != 0U)
01629       {
01630         clkp_frequency = CSI_VALUE;
01631       }
01632       break;
01633
01634     case LL_RCC_CLKP_CLKSOURCE_HSE:
01635       if (LL_RCC_HSE_IsReady() != 0U)
01636       {
01637         clkp_frequency = HSE_VALUE;
01638       }
01639       break;
01640
01641     default:
01642       /* CLKP clock disabled */
01643       break;
01644   }
01645
01646   return clkp_frequency;
01647 }
01648
01649 /**
01650   * @}
01651   */
01652
01653 /**
01654   * @}
01655   */
01656
01657 /** @addtogroup RCC_LL_Private_Functions
01658   * @{
01659   */
01660
01661 /**
01662   * @brief  Return SYSTEM clock frequency
01663   * @retval SYSTEM clock frequency (in Hz)
01664   */
01665 uint32_t RCC_GetSystemClockFreq(void)
01666 {
01667   uint32_t frequency = 0U;
01668   LL_PLL_ClocksTypeDef PLL_Clocks;
01669
01670   /* Get SYSCLK source -------------------------------------------------------*/
01671   switch (LL_RCC_GetSysClkSource())
01672   {
01673     /* No check on Ready: Won't be selected by hardware if not */
01674     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
01675       frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
01676       break;
01677
01678     case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
01679       frequency = CSI_VALUE;
01680       break;
01681
01682     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
01683       frequency = HSE_VALUE;
01684       break;
01685
01686     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
01687       LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
01688       frequency = PLL_Clocks.PLL_P_Frequency;
01689       break;
01690
01691     default:
01692       /* Nothing to do */
01693       break;
01694   }
01695
01696   return frequency;
01697 }
01698
01699 /**
01700   * @brief  Return HCLK clock frequency
01701   * @param  SYSCLK_Frequency SYSCLK clock frequency
01702   * @retval HCLK clock frequency (in Hz)
01703   */
01704 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
01705 {
01706   /* HCLK clock frequency */
01707   return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
01708 }
01709
01710 /**
01711   * @brief  Return PCLK1 clock frequency
01712   * @param  HCLK_Frequency HCLK clock frequency
01713   * @retval PCLK1 clock frequency (in Hz)
01714   */
01715 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01716 {
01717   /* PCLK1 clock frequency */
01718   return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01719 }
01720
01721 /**
01722   * @brief  Return PCLK2 clock frequency
01723   * @param  HCLK_Frequency HCLK clock frequency
01724   * @retval PCLK2 clock frequency (in Hz)
01725   */
01726 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
01727 {
01728   /* PCLK2 clock frequency */
01729   return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
01730 }
01731
01732 /**
01733   * @brief  Return PCLK3 clock frequency
01734   * @param  HCLK_Frequency HCLK clock frequency
01735   * @retval PCLK3 clock frequency (in Hz)
01736   */
01737 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
01738 {
01739   /* PCLK3 clock frequency */
01740   return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
01741 }
01742
01743 /**
01744   * @brief  Return PCLK4 clock frequency
01745   * @param  HCLK_Frequency HCLK clock frequency
01746   * @retval PCLK4 clock frequency (in Hz)
01747   */
01748 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
01749 {
01750   /* PCLK4 clock frequency */
01751   return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
01752 }
01753
01754 /**
01755   * @}
01756   */
01757
01758 /**
01759   * @}
01760   */
01761
01762 #endif /* defined(RCC) */
01763
01764 /**
01765   * @}
01766   */
01767
01768 #endif /* USE_FULL_LL_DRIVER */
01769
01770 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rcc.h Source File

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stm32h7xx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of RCC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
00012   * All rights reserved.</center></h2>
00013   *
00014   * This software component is licensed by ST under BSD 3-Clause license,
00015   * the "License"; You may not use this file except in compliance with the
00016   * License. You may obtain a copy of the License at:
00017   *                        opensource.org/licenses/BSD-3-Clause
00018   *
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef STM32H7xx_LL_RCC_H
00024 #define STM32H7xx_LL_RCC_H
00025
00026 #ifdef __cplusplus
00027 extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32h7xx.h"
00032 #include <math.h>
00033
00034 /** @addtogroup STM32H7xx_LL_Driver
00035   * @{
00036   */
00037
00038 #if defined(RCC)
00039
00040 /** @defgroup RCC_LL RCC
00041   * @{
00042   */
00043
00044 /* Private types -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00047   * @{
00048   */
00049 extern const uint8_t LL_RCC_PrescTable[16];
00050
00051 /**
00052   * @}
00053   */
00054 /* Private constants ---------------------------------------------------------*/
00055 /* Private macros ------------------------------------------------------------*/
00056 #if !defined(UNUSED)
00057 #define UNUSED(x) ((void)(x))
00058 #endif
00059
00060 /* 32            24           16            8             0
00061    --------------------------------------------------------
00062    | Mask        | ClkSource   |  Bit       | Register    |
00063    |             |  Config     | Position   | Offset      |
00064    --------------------------------------------------------*/
00065
00066 #if defined(RCC_VER_2_0)
00067 /* Clock source register offset Vs CDCCIPR regsiter */
00068 #define CDCCIP    0x0UL
00069 #define CDCCIP1   0x4UL
00070 #define CDCCIP2   0x8UL
00071 #define SRDCCIP   0xCUL
00072 #else
00073 /* Clock source register offset Vs D1CCIPR regsiter */
00074 #define D1CCIP    0x0UL
00075 #define D2CCIP1   0x4UL
00076 #define D2CCIP2   0x8UL
00077 #define D3CCIP    0xCUL
00078 #endif /* RCC_VER_2_0 */
00079
00080 #define LL_RCC_REG_SHIFT     0U
00081 #define LL_RCC_POS_SHIFT     8U
00082 #define LL_RCC_CONFIG_SHIFT  16U
00083 #define LL_RCC_MASK_SHIFT    24U
00084
00085 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
00086
00087 #define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
00088
00089 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
00090
00091 #define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
00092
00093 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
00094                                                                      (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
00095                                                                      (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
00096                                                                      (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
00097
00098 #if defined(USE_FULL_LL_DRIVER)
00099 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00100   * @{
00101   */
00102 /**
00103   * @}
00104   */
00105 #endif /*USE_FULL_LL_DRIVER*/
00106 /* Exported types ------------------------------------------------------------*/
00107 #if defined(USE_FULL_LL_DRIVER)
00108 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00109   * @{
00110   */
00111
00112 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00113   * @{
00114   */
00115
00116 /**
00117   * @brief  RCC Clocks Frequency Structure
00118   */
00119 typedef struct
00120 {
00121   uint32_t SYSCLK_Frequency;
00122   uint32_t CPUCLK_Frequency;
00123   uint32_t HCLK_Frequency;
00124   uint32_t PCLK1_Frequency;
00125   uint32_t PCLK2_Frequency;
00126   uint32_t PCLK3_Frequency;
00127   uint32_t PCLK4_Frequency;
00128 } LL_RCC_ClocksTypeDef;
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @brief  PLL Clocks Frequency Structure
00136   */
00137 typedef struct
00138 {
00139   uint32_t PLL_P_Frequency;
00140   uint32_t PLL_Q_Frequency;
00141   uint32_t PLL_R_Frequency;
00142 } LL_PLL_ClocksTypeDef;
00143
00144 /**
00145   * @}
00146   */
00147
00148 #endif /* USE_FULL_LL_DRIVER */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00152   * @{
00153   */
00154
00155 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00156   * @brief    Defines used to adapt values of different oscillators
00157   * @note     These values could be modified in the user environment according to
00158   *           HW set-up.
00159   * @{
00160   */
00161 #if !defined  (HSE_VALUE)
00162 #if defined(RCC_VER_X)
00163 #define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
00164 #else
00165 #define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
00166 #endif /* RCC_VER_X */
00167 #endif /* HSE_VALUE */
00168
00169 #if !defined  (HSI_VALUE)
00170 #define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
00171 #endif /* HSI_VALUE */
00172
00173 #if !defined  (CSI_VALUE)
00174 #define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
00175 #endif /* CSI_VALUE */
00176
00177 #if !defined  (LSE_VALUE)
00178 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
00179 #endif /* LSE_VALUE */
00180
00181 #if !defined  (LSI_VALUE)
00182 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
00183 #endif /* LSI_VALUE */
00184
00185 #if !defined  (EXTERNAL_CLOCK_VALUE)
00186 #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
00187 #endif /* EXTERNAL_CLOCK_VALUE */
00188
00189 #if !defined  (HSI48_VALUE)
00190 #define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
00191 #endif /* HSI48_VALUE */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
00198   * @{
00199   */
00200 #define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
00201 #define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
00202 #define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
00203 #define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00209   * @{
00210   */
00211 #define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
00212 #define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
00213 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
00214 #define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00220   * @{
00221   */
00222 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
00223 #define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
00224 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
00225 #define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00231   * @{
00232   */
00233 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00234 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
00235 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00236 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
00242   * @{
00243   */
00244 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
00245 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
00251   * @{
00252   */
00253 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
00254 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
00260   * @{
00261   */
00262 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
00263 #define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
00264 #define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
00265 #define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
00266 #define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
00267 #define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
00268 #define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
00269 #define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
00270 #define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
00271 #define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
00272 #else
00273 #define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
00274 #define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
00275 #define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
00276 #define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
00277 #define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
00278 #define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
00279 #define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
00280 #define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
00281 #define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
00282 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
00288   * @{
00289   */
00290 #if defined(RCC_D1CFGR_HPRE_DIV1)
00291 #define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
00292 #define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
00293 #define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
00294 #define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
00295 #define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
00296 #define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
00297 #define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
00298 #define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
00299 #define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
00300 #else
00301 #define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
00302 #define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
00303 #define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
00304 #define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
00305 #define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
00306 #define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
00307 #define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
00308 #define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
00309 #define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
00310 #endif /* RCC_D1CFGR_HPRE_DIV1 */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00316   * @{
00317   */
00318 #if defined(RCC_D2CFGR_D2PPRE1_DIV1)
00319 #define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
00320 #define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
00321 #define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
00322 #define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
00323 #define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
00324 #else
00325 #define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
00326 #define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
00327 #define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
00328 #define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
00329 #define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
00330 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
00336   * @{
00337   */
00338 #if defined(RCC_D2CFGR_D2PPRE2_DIV1)
00339 #define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
00340 #define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
00341 #define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
00342 #define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
00343 #define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
00344 #else
00345 #define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
00346 #define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
00347 #define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
00348 #define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
00349 #define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
00350 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
00356   * @{
00357   */
00358 #if defined(RCC_D1CFGR_D1PPRE_DIV1)
00359 #define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
00360 #define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
00361 #define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
00362 #define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
00363 #define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
00364 #else
00365 #define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
00366 #define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
00367 #define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
00368 #define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
00369 #define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
00370 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
00376   * @{
00377   */
00378 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
00379 #define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
00380 #define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
00381 #define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
00382 #define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
00383 #define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
00384 #else
00385 #define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
00386 #define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
00387 #define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
00388 #define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
00389 #define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
00390 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
00396   * @{
00397   */
00398 #define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
00399 #define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
00400 #define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
00401 #define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
00402 #define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
00403 #define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
00404 #define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
00405 #define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
00406 #define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
00407 #define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
00408 #define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
00414   * @{
00415   */
00416 #define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
00417 #define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
00418 #define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
00419 #define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
00420 #define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
00421 #define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00422 #define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00423 #define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
00424 #define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
00425 #define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00426 #define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00427 #define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00428 #define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00429 #define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00430 #define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
00431 #define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
00432 #define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
00433 #define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
00434 #define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
00435 #define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
00436 #define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
00437 #define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
00438 #define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
00439 #define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
00440 #define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
00441 #define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
00442 #define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
00443 #define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
00444 #define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
00445 #define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
00446
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
00452   * @{
00453   */
00454 #define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
00455 #define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
00456 #define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00457 #define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
00458 #define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00459 #define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00460 #define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00461 #define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
00462 #define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
00463 #define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
00464 #define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00465 #define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
00466 #define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00467 #define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00468 #define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00469 #define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
00470 #define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
00471 #define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
00472 #define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00473 #define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
00474 #define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00475 #define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00476 #define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00477 #define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
00478 #define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
00479 #define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
00480 #define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00481 #define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
00482 #define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00483 #define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00484 #define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00485 #define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
00486 #define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
00487 #define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
00488 #define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00489 #define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
00490 #define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00491 #define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00492 #define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00493 #define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
00494 #define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
00495 #define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
00496 #define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00497 #define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
00498 #define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00499 #define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00500 #define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00501 #define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
00502 #define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
00503 #define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
00504 #define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00505 #define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
00506 #define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00507 #define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00508 #define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00509 #define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
00510 #define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
00511 #define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
00512 #define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00513 #define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
00514 #define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
00515 #define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
00516 #define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
00522   * @{
00523   */
00524 #if defined(RCC_D2CCIP2R_USART16SEL)
00525 #define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
00526 #define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
00527 #define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
00528 #define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
00529 #define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
00530 #define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
00531 #else
00532 #define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
00533 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
00534 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
00535 #define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
00536 #define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
00537 #define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
00538 /*  Aliases */
00539 #define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
00540 #define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
00541 #define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
00542 #define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
00543 #define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
00544 #define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
00545 #endif  /* RCC_D2CCIP2R_USART16SEL */
00546 #if defined(RCC_D2CCIP2R_USART28SEL)
00547 #define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
00548 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
00549 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
00550 #define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00551 #define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
00552 #define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00553 #else
00554 #define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
00555 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
00556 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
00557 #define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
00558 #define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
00559 #define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
00560 #endif /* RCC_D2CCIP2R_USART28SEL */
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
00566   * @{
00567   */
00568 #if defined(RCC_D3CCIPR_LPUART1SEL)
00569 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
00570 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
00571 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
00572 #define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
00573 #define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
00574 #define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
00575 #else
00576 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
00577 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
00578 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
00579 #define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
00580 #define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
00581 #define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
00582 #endif /* RCC_D3CCIPR_LPUART1SEL */
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
00588   * @{
00589   */
00590 #if defined (RCC_D2CCIP2R_I2C123SEL)
00591 #define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
00592 #define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
00593 #define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
00594 #define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
00595 #else
00596 #define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
00597 #define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
00598 #define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
00599 #define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
00600 #endif /* RCC_D2CCIP2R_I2C123SEL */
00601 #if defined (RCC_D3CCIPR_I2C4SEL)
00602 #define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
00603 #define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
00604 #define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
00605 #define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
00606 #else
00607 #define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
00608 #define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
00609 #define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
00610 #define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
00611 #endif /* RCC_D3CCIPR_I2C4SEL */
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
00617   * @{
00618   */
00619 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
00620 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
00621 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
00622 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
00623 #define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
00624 #define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
00625 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
00626 #else
00627 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
00628 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
00629 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
00630 #define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
00631 #define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
00632 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
00633 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
00634 #if defined(RCC_D3CCIPR_LPTIM2SEL)
00635 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
00636 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
00637 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
00638 #define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
00639 #define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
00640 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
00641 #else
00642 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
00643 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
00644 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
00645 #define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
00646 #define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
00647 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
00648 #endif /* RCC_D3CCIPR_LPTIM2SEL */
00649 #if defined(RCC_D3CCIPR_LPTIM345SEL)
00650 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
00651 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
00652 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
00653 #define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
00654 #define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
00655 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
00656 #else
00657 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
00658 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
00659 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
00660 #define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
00661 #define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
00662 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
00663 /* aliases*/
00664 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
00665 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
00666 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
00667 #define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
00668 #define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
00669 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
00670 #endif /* RCC_D3CCIPR_LPTIM345SEL */
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
00676   * @{
00677   */
00678 #if defined(RCC_D2CCIP1R_SAI1SEL)
00679 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
00680 #define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
00681 #define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
00682 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
00683 #define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
00684 #else
00685 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
00686 #define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
00687 #define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
00688 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
00689 #define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
00690 #endif
00691 #if defined(SAI3)
00692 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
00693 #define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
00694 #define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
00695 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
00696 #define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
00697 #endif /* SAI3 */
00698 #if defined(RCC_CDCCIP1R_SAI2ASEL)
00699 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
00700 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
00701 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
00702 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
00703 #define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
00704 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
00705 #endif /* RCC_CDCCIP1R_SAI2ASEL */
00706 #if defined(RCC_CDCCIP1R_SAI2BSEL)
00707 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
00708 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
00709 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
00710 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
00711 #define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
00712 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
00713 #endif /* RCC_CDCCIP1R_SAI2BSEL */
00714 #if defined(SAI4_Block_A)
00715 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
00716 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
00717 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
00718 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
00719 #define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
00720 #endif /* SAI4_Block_A */
00721 #if defined(SAI4_Block_B)
00722 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
00723 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
00724 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
00725 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
00726 #define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
00727 #endif /* SAI4_Block_B */
00728 /**
00729   * @}
00730   */
00731
00732 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
00733   * @{
00734   */
00735 #if defined(RCC_D1CCIPR_SDMMCSEL)
00736 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
00737 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
00738 #else
00739 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
00740 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
00741 #endif /* RCC_D1CCIPR_SDMMCSEL */
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
00747   * @{
00748   */
00749 #if defined(RCC_D2CCIP2R_RNGSEL)
00750 #define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
00751 #define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
00752 #define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
00753 #define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
00754 #else
00755 #define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
00756 #define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
00757 #define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
00758 #define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
00759 #endif /* RCC_D2CCIP2R_RNGSEL */
00760 /**
00761   * @}
00762   */
00763
00764 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
00765   * @{
00766   */
00767 #if defined(RCC_D2CCIP2R_USBSEL)
00768 #define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
00769 #define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
00770 #define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
00771 #define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
00772 #else
00773 #define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
00774 #define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
00775 #define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
00776 #define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
00777 #endif /* RCC_D2CCIP2R_USBSEL */
00778 /**
00779   * @}
00780   */
00781
00782 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
00783   * @{
00784   */
00785 #if defined(RCC_D2CCIP2R_CECSEL)
00786 #define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
00787 #define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
00788 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
00789 #else
00790 #define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
00791 #define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
00792 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
00793 #endif
00794 /**
00795   * @}
00796   */
00797
00798 #if defined(DSI)
00799 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
00800   * @{
00801   */
00802 #define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
00803 #define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
00804 /**
00805   * @}
00806   */
00807 #endif /* DSI */
00808
00809 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
00810   * @{
00811   */
00812 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
00813 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
00814 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
00815 #else
00816 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
00817 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
00818 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
00819 /**
00820   * @}
00821   */
00822
00823 #if defined(DFSDM2_BASE)
00824 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
00825   * @{
00826   */
00827 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
00828 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
00829 /**
00830   * @}
00831   */
00832 #endif /* DFSDM2_BASE */
00833
00834 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
00835   * @{
00836   */
00837 #if defined(RCC_D1CCIPR_FMCSEL)
00838 #define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
00839 #define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
00840 #define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
00841 #define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
00842 #else
00843 #define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
00844 #define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
00845 #define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
00846 #define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
00847 #endif /* RCC_D1CCIPR_FMCSEL */
00848 /**
00849   * @}
00850   */
00851
00852 #if defined(QUADSPI)
00853 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
00854   * @{
00855   */
00856 #define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
00857 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
00858 #define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
00859 #define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
00860 /**
00861   * @}
00862   */
00863 #endif /* QUADSPI */
00864
00865
00866 #if defined(OCTOSPI1) || defined(OCTOSPI2)
00867 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
00868   * @{
00869   */
00870 #define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
00871 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
00872 #define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
00873 #define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
00874 /**
00875   * @}
00876   */
00877 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
00878
00879
00880 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
00881   * @{
00882   */
00883 #if defined(RCC_D1CCIPR_CKPERSEL)
00884 #define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
00885 #define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
00886 #define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
00887 #else
00888 #define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
00889 #define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
00890 #define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
00891 #endif /* RCC_D1CCIPR_CKPERSEL */
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
00897   * @{
00898   */
00899 #if defined(RCC_D2CCIP1R_SPI123SEL)
00900 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
00901 #define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
00902 #define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
00903 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
00904 #define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
00905 #else
00906 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
00907 #define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
00908 #define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
00909 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
00910 #define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
00911 #endif /* RCC_D2CCIP1R_SPI123SEL */
00912 #if defined(RCC_D2CCIP1R_SPI45SEL)
00913 #define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
00914 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
00915 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
00916 #define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
00917 #define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
00918 #define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
00919 #else
00920 #define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
00921 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
00922 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
00923 #define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
00924 #define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
00925 #define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
00926 #endif /* (RCC_D2CCIP1R_SPI45SEL */
00927 #if defined(RCC_D3CCIPR_SPI6SEL)
00928 #define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
00929 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
00930 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
00931 #define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
00932 #define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
00933 #define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
00934 #else
00935 #define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
00936 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
00937 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
00938 #define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
00939 #define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
00940 #define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
00941 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
00942 #endif /* RCC_D3CCIPR_SPI6SEL */
00943 /**
00944   * @}
00945   */
00946
00947 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
00948   * @{
00949   */
00950 #if defined(RCC_D2CCIP1R_SPDIFSEL)
00951 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
00952 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
00953 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
00954 #define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
00955 #else
00956 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
00957 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
00958 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
00959 #define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
00960 #endif /* RCC_D2CCIP1R_SPDIFSEL */
00961 /**
00962   * @}
00963   */
00964
00965 #if defined(FDCAN1) || defined(FDCAN2)
00966 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
00967   * @{
00968   */
00969 #if defined(RCC_D2CCIP1R_FDCANSEL)
00970 #define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
00971 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
00972 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
00973 #else
00974 #define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
00975 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
00976 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
00977 #endif /* RCC_D2CCIP1R_FDCANSEL */
00978 /**
00979   * @}
00980   */
00981 #endif /*FDCAN1 || FDCAN2*/
00982
00983 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
00984   * @{
00985   */
00986 #if defined(RCC_D2CCIP1R_SWPSEL)
00987 #define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
00988 #define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
00989 #else
00990 #define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
00991 #define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
00992 #endif /* RCC_D2CCIP1R_SWPSEL */
00993 /**
00994   * @}
00995   */
00996
00997 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
00998   * @{
00999   */
01000 #if defined(RCC_D3CCIPR_ADCSEL)
01001 #define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
01002 #define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
01003 #define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
01004 #else
01005 #define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
01006 #define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
01007 #define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
01008 #endif /* RCC_D3CCIPR_ADCSEL */
01009 /**
01010   * @}
01011   */
01012
01013 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART get clock source
01014   * @{
01015   */
01016 #if defined (RCC_D2CCIP2R_USART16SEL)
01017 #define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
01018 #else
01019 #define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
01020 /* alias*/
01021 #define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
01022 #endif /* RCC_D2CCIP2R_USART16SEL */
01023 #if defined (RCC_D2CCIP2R_USART28SEL)
01024 #define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
01025 #else
01026 #define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
01027 #endif /* RCC_D2CCIP2R_USART28SEL */
01028 /**
01029   * @}
01030   */
01031
01032 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART get clock source
01033   * @{
01034   */
01035 #if defined(RCC_D3CCIPR_LPUART1SEL)
01036 #define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
01037 #else
01038 #define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
01039 #endif /* RCC_D3CCIPR_LPUART1SEL */
01040 /**
01041   * @}
01042   */
01043
01044 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C get clock source
01045   * @{
01046   */
01047 #if defined(RCC_D2CCIP2R_I2C123SEL)
01048 #define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
01049 #else
01050 #define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
01051 #endif /* RCC_D2CCIP2R_I2C123SEL */
01052 #if defined(RCC_D3CCIPR_I2C4SEL)
01053 #define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
01054 #else
01055 #define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
01056 #endif /* RCC_D3CCIPR_I2C4SEL */
01057 /**
01058   * @}
01059   */
01060
01061 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM get clock source
01062   * @{
01063   */
01064 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
01065 #define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,   0x00000000U)
01066 #else
01067 #define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,   0x00000000U)
01068 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */
01069 #if defined(RCC_D3CCIPR_LPTIM2SEL)
01070 #define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,    0x00000000U)
01071 #else
01072 #define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
01073 #endif /* RCC_D3CCIPR_LPTIM2SEL */
01074 #if defined(RCC_D3CCIPR_LPTIM345SEL)
01075 #define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,  0x00000000U)
01076 #else
01077 #define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,   0x00000000U)
01078 #define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
01079 #endif /* RCC_D3CCIPR_LPTIM345SEL */
01080 /**
01081   * @}
01082   */
01083
01084 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI get clock source
01085   * @{
01086   */
01087 #if defined(RCC_D2CCIP1R_SAI1SEL)
01088 #define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
01089 #else
01090 #define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
01091 #endif /* RCC_D2CCIP1R_SAI1SEL */
01092 #if defined(RCC_D2CCIP1R_SAI23SEL)
01093 #define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
01094 #endif /* RCC_D2CCIP1R_SAI23SEL */
01095 #if defined(RCC_CDCCIP1R_SAI2ASEL)
01096 #define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
01097 #endif /* RCC_CDCCIP1R_SAI2ASEL */
01098 #if defined(RCC_CDCCIP1R_SAI2BSEL)
01099 #define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
01100 #endif /*  RCC_CDCCIP1R_SAI2BSEL */
01101 #if defined(RCC_D3CCIPR_SAI4ASEL)
01102 #define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
01103 #endif /* RCC_D3CCIPR_SAI4ASEL */
01104 #if defined(RCC_D3CCIPR_SAI4BSEL)
01105 #define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
01106 #endif /*  RCC_D3CCIPR_SAI4BSEL */
01107 /**
01108   * @}
01109   */
01110
01111 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC get clock source
01112   * @{
01113   */
01114 #if defined(RCC_D1CCIPR_SDMMCSEL)
01115 #define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
01116 #else
01117 #define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
01118 #endif /* RCC_D1CCIPR_SDMMCSEL */
01119 /**
01120   * @}
01121   */
01122
01123 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG get clock source
01124   * @{
01125   */
01126 #if (RCC_D2CCIP2R_RNGSEL)
01127 #define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
01128 #else
01129 #define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
01130 #endif /* RCC_D2CCIP2R_RNGSEL */
01131 /**
01132   * @}
01133   */
01134
01135 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB get clock source
01136   * @{
01137   */
01138 #if (RCC_D2CCIP2R_USBSEL)
01139 #define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
01140 #else
01141 #define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
01142 #endif  /* RCC_D2CCIP2R_USBSEL */
01143 /**
01144   * @}
01145   */
01146
01147 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC get clock source
01148   * @{
01149   */
01150 #if (RCC_D2CCIP2R_CECSEL)
01151 #define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
01152 #else
01153 #define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
01154 #endif /* RCC_D2CCIP2R_CECSEL */
01155 /**
01156   * @}
01157   */
01158
01159 #if defined(DSI)
01160 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI get clock source
01161   * @{
01162   */
01163 #define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
01164 /**
01165   * @}
01166   */
01167 #endif /* DSI */
01168
01169 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM get clock source
01170   * @{
01171   */
01172 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
01173 #define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
01174 #else
01175 #define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
01176 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
01177 /**
01178   * @}
01179   */
01180
01181 #if defined(DFSDM2_BASE)
01182 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 get clock source
01183   * @{
01184   */
01185 #define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
01186 /**
01187   * @}
01188   */
01189 #endif /* DFSDM2 */
01190
01191
01192 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC get clock source
01193   * @{
01194   */
01195 #if defined(RCC_D1CCIPR_FMCSEL)
01196 #define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
01197 #else
01198 #define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
01199 #endif
01200 /**
01201   * @}
01202   */
01203
01204 #if defined(QUADSPI)
01205 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI get clock source
01206   * @{
01207   */
01208 #define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
01209 /**
01210   * @}
01211   */
01212 #endif /* QUADSPI */
01213
01214 #if defined(OCTOSPI1) || defined(OCTOSPI2)
01215 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI get clock source
01216   * @{
01217   */
01218 #define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
01219 /**
01220   * @}
01221   */
01222 #endif /* OCTOSPI1 || OCTOSPI2 */
01223
01224 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP get clock source
01225   * @{
01226   */
01227 #if defined(RCC_D1CCIPR_CKPERSEL)
01228 #define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
01229 #else
01230 #define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
01231 #endif /* RCC_D1CCIPR_CKPERSEL */
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI get clock source
01237   * @{
01238   */
01239 #if defined(RCC_D2CCIP1R_SPI123SEL)
01240 #define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
01241 #else
01242 #define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
01243 #endif /* RCC_D2CCIP1R_SPI123SEL */
01244 #if defined(RCC_D2CCIP1R_SPI45SEL)
01245 #define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
01246 #else
01247 #define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
01248 #endif /* RCC_D2CCIP1R_SPI45SEL */
01249 #if defined(RCC_D3CCIPR_SPI6SEL)
01250 #define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
01251 #else
01252 #define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
01253 #endif /* RCC_D3CCIPR_SPI6SEL */
01254 /**
01255   * @}
01256   */
01257
01258 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF get clock source
01259   * @{
01260   */
01261 #if defined(RCC_D2CCIP1R_SPDIFSEL)
01262 #define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
01263 #else
01264 #define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
01265 #endif /* RCC_D2CCIP1R_SPDIFSEL */
01266 /**
01267   * @}
01268   */
01269
01270 #if defined(FDCAN1) || defined(FDCAN2)
01271 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN get clock source
01272   * @{
01273   */
01274 #if defined(RCC_D2CCIP1R_FDCANSEL)
01275 #define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
01276 #else
01277 #define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
01278 #endif
01279 /**
01280   * @}
01281   */
01282 #endif /*FDCAN1 || FDCAN2*/
01283
01284 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP get clock source
01285   * @{
01286   */
01287 #if defined(RCC_D2CCIP1R_SWPSEL)
01288 #define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
01289 #else
01290 #define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
01291 #endif /* RCC_D2CCIP1R_SWPSEL */
01292 /**
01293   * @}
01294   */
01295
01296 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC get clock source
01297   * @{
01298   */
01299 #if defined(RCC_D3CCIPR_ADCSEL)
01300 #define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
01301 #else
01302 #define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
01303 #endif /* RCC_D3CCIPR_ADCSEL */
01304 /**
01305   * @}
01306   */
01307
01308 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
01309   * @{
01310   */
01311 #define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
01312 #define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
01313 #define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
01314 #define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
01315 /**
01316   * @}
01317   */
01318
01319 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
01320   * @{
01321   */
01322 #define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
01323 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
01324 /**
01325   * @}
01326   */
01327
01328 #if defined(HRTIM1)
01329 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
01330   * @{
01331   */
01332 #define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
01333 #define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
01334 /**
01335   * @}
01336   */
01337 #endif /* HRTIM1 */
01338
01339 /** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
01340   * @{
01341   */
01342 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
01343 #define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
01344 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
01345 #define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
01346 /**
01347   * @}
01348   */
01349
01350 /** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
01351   * @{
01352   */
01353 #define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
01354 #define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
01355 #define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
01356 #define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
01357 /**
01358   * @}
01359   */
01360
01361 /** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
01362   * @{
01363   */
01364 #define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
01365 #define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
01366 /**
01367   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
01368   * @}
01369   */
01370
01371 /**
01372   * @}
01373   */
01374
01375 /* Exported macro ------------------------------------------------------------*/
01376 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
01377   * @{
01378   */
01379
01380 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
01381   * @{
01382   */
01383
01384 /**
01385   * @brief  Write a value in RCC register
01386   * @param  __REG__ Register to be written
01387   * @param  __VALUE__ Value to be written in the register
01388   * @retval None
01389   */
01390 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
01391
01392 /**
01393   * @brief  Read a value in RCC register
01394   * @param  __REG__ Register to be read
01395   * @retval Register value
01396   */
01397 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
01398 /**
01399   * @}
01400   */
01401
01402 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
01403   * @{
01404   */
01405
01406 /**
01407   * @brief  Helper macro to calculate the SYSCLK frequency
01408   * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
01409   * @param  __SYSPRESCALER__ This parameter can be one of the following values:
01410   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01411   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01412   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01413   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01414   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01415   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01416   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01417   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01418   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01419   * @retval SYSCLK clock frequency (in Hz)
01420   */
01421 #if defined(RCC_D1CFGR_D1CPRE)
01422 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos])
01423 #else
01424 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
01425 #endif /* RCC_D1CFGR_D1CPRE */
01426
01427 /**
01428   * @brief  Helper macro to calculate the HCLK frequency
01429   * @param  __SYSCLKFREQ__ SYSCLK frequency.
01430   * @param  __HPRESCALER__ This parameter can be one of the following values:
01431   *         @arg @ref LL_RCC_AHB_DIV_1
01432   *         @arg @ref LL_RCC_AHB_DIV_2
01433   *         @arg @ref LL_RCC_AHB_DIV_4
01434   *         @arg @ref LL_RCC_AHB_DIV_8
01435   *         @arg @ref LL_RCC_AHB_DIV_16
01436   *         @arg @ref LL_RCC_AHB_DIV_64
01437   *         @arg @ref LL_RCC_AHB_DIV_128
01438   *         @arg @ref LL_RCC_AHB_DIV_256
01439   *         @arg @ref LL_RCC_AHB_DIV_512
01440   * @retval HCLK clock frequency (in Hz)
01441   */
01442 #if defined(RCC_D1CFGR_HPRE)
01443 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos])
01444 #else
01445 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos])
01446 #endif  /* RCC_D1CFGR_HPRE */
01447
01448 /**
01449   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
01450   * @param  __HCLKFREQ__ HCLK frequency
01451   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
01452   *         @arg @ref LL_RCC_APB1_DIV_1
01453   *         @arg @ref LL_RCC_APB1_DIV_2
01454   *         @arg @ref LL_RCC_APB1_DIV_4
01455   *         @arg @ref LL_RCC_APB1_DIV_8
01456   *         @arg @ref LL_RCC_APB1_DIV_16
01457   * @retval PCLK1 clock frequency (in Hz)
01458   */
01459 #if defined(RCC_D2CFGR_D2PPRE1)
01460 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos])
01461 #else
01462 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos])
01463 #endif /* RCC_D2CFGR_D2PPRE1 */
01464
01465 /**
01466   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
01467   * @param  __HCLKFREQ__ HCLK frequency
01468   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
01469   *         @arg @ref LL_RCC_APB2_DIV_1
01470   *         @arg @ref LL_RCC_APB2_DIV_2
01471   *         @arg @ref LL_RCC_APB2_DIV_4
01472   *         @arg @ref LL_RCC_APB2_DIV_8
01473   *         @arg @ref LL_RCC_APB2_DIV_16
01474   * @retval PCLK2 clock frequency (in Hz)
01475   */
01476 #if defined(RCC_D2CFGR_D2PPRE2)
01477 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos])
01478 #else
01479 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >>  RCC_CDCFGR2_CDPPRE2_Pos])
01480 #endif /* RCC_D2CFGR_D2PPRE2 */
01481
01482 /**
01483   * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
01484   * @param  __HCLKFREQ__ HCLK frequency
01485   * @param  __APB3PRESCALER__ This parameter can be one of the following values:
01486   *         @arg @ref LL_RCC_APB3_DIV_1
01487   *         @arg @ref LL_RCC_APB3_DIV_2
01488   *         @arg @ref LL_RCC_APB3_DIV_4
01489   *         @arg @ref LL_RCC_APB3_DIV_8
01490   *         @arg @ref LL_RCC_APB3_DIV_16
01491   * @retval PCLK1 clock frequency (in Hz)
01492   */
01493 #if defined(RCC_D1CFGR_D1PPRE)
01494 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos])
01495 #else
01496 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >>  RCC_CDCFGR1_CDPPRE_Pos])
01497 #endif /* RCC_D1CFGR_D1PPRE */
01498
01499 /**
01500   * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
01501   * @param  __HCLKFREQ__ HCLK frequency
01502   * @param  __APB4PRESCALER__ This parameter can be one of the following values:
01503   *         @arg @ref LL_RCC_APB4_DIV_1
01504   *         @arg @ref LL_RCC_APB4_DIV_2
01505   *         @arg @ref LL_RCC_APB4_DIV_4
01506   *         @arg @ref LL_RCC_APB4_DIV_8
01507   *         @arg @ref LL_RCC_APB4_DIV_16
01508   * @retval PCLK1 clock frequency (in Hz)
01509   */
01510 #if defined(RCC_D3CFGR_D3PPRE)
01511 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos])
01512 #else
01513 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos])
01514 #endif /* RCC_D3CFGR_D3PPRE */
01515
01516 /**
01517   * @}
01518   */
01519
01520 #if defined(USE_FULL_LL_DRIVER)
01521 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
01522   * @{
01523   */
01524 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
01525 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
01526 /**
01527   * @}
01528   */
01529 #endif /* USE_FULL_LL_DRIVER */
01530
01531 /**
01532   * @}
01533   */
01534
01535 /* Exported functions --------------------------------------------------------*/
01536 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
01537   * @{
01538   */
01539
01540 /** @defgroup RCC_LL_EF_HSE HSE
01541   * @{
01542   */
01543
01544 /**
01545   * @brief  Enable the Clock Security System.
01546   * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
01547   *       a reset occurs or system enter in standby mode.
01548   * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
01549   * @retval None
01550   */
01551 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
01552 {
01553   SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
01554 }
01555
01556 /**
01557   * @brief  Enable HSE external oscillator (HSE Bypass)
01558   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
01559   * @retval None
01560   */
01561 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
01562 {
01563   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
01564 }
01565
01566 /**
01567   * @brief  Disable HSE external oscillator (HSE Bypass)
01568   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
01572 {
01573   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
01574 }
01575
01576 #if defined(RCC_CR_HSEEXT)
01577 /**
01578   * @brief  Select the Analog HSE external clock type in Bypass mode
01579   * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
01580   * @retval None
01581   */
01582 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
01583 {
01584   CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
01585 }
01586
01587 /**
01588   * @brief  Select the Digital HSE external clock type in Bypass mode
01589   * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
01590   * @retval None
01591   */
01592 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
01593 {
01594   SET_BIT(RCC->CR, RCC_CR_HSEEXT);
01595 }
01596 #endif /* RCC_CR_HSEEXT */
01597
01598 /**
01599   * @brief  Enable HSE crystal oscillator (HSE ON)
01600   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
01601   * @retval None
01602   */
01603 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
01604 {
01605   SET_BIT(RCC->CR, RCC_CR_HSEON);
01606 }
01607
01608 /**
01609   * @brief  Disable HSE crystal oscillator (HSE ON)
01610   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
01611   * @retval None
01612   */
01613 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
01614 {
01615   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
01616 }
01617
01618 /**
01619   * @brief  Check if HSE oscillator Ready
01620   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
01621   * @retval State of bit (1 or 0).
01622   */
01623 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
01624 {
01625   return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
01626 }
01627
01628 /**
01629   * @}
01630   */
01631
01632 /** @defgroup RCC_LL_EF_HSI HSI
01633   * @{
01634   */
01635
01636 /**
01637   * @brief  Enable HSI oscillator
01638   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01639   * @retval None
01640   */
01641 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01642 {
01643   SET_BIT(RCC->CR, RCC_CR_HSION);
01644 }
01645
01646 /**
01647   * @brief  Disable HSI oscillator
01648   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01649   * @retval None
01650   */
01651 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01652 {
01653   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01654 }
01655
01656 /**
01657   * @brief  Check if HSI clock is ready
01658   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01659   * @retval State of bit (1 or 0).
01660   */
01661 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01662 {
01663   return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
01664 }
01665
01666 /**
01667   * @brief  Check if HSI new divider applied and ready
01668   * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
01669   * @retval State of bit (1 or 0).
01670   */
01671 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
01672 {
01673   return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
01674 }
01675
01676 /**
01677   * @brief  Set HSI divider
01678   * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
01679   * @param  Divider This parameter can be one of the following values:
01680   *         @arg @ref LL_RCC_HSI_DIV1
01681   *         @arg @ref LL_RCC_HSI_DIV2
01682   *         @arg @ref LL_RCC_HSI_DIV4
01683   *         @arg @ref LL_RCC_HSI_DIV8
01684   * @retval None.
01685   */
01686 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
01687 {
01688   MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
01689 }
01690
01691 /**
01692   * @brief  Get HSI divider
01693   * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
01694   * @retval can be one of the following values:
01695   *         @arg @ref LL_RCC_HSI_DIV1
01696   *         @arg @ref LL_RCC_HSI_DIV2
01697   *         @arg @ref LL_RCC_HSI_DIV4
01698   *         @arg @ref LL_RCC_HSI_DIV8
01699   */
01700 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
01701 {
01702   return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
01703 }
01704
01705 /**
01706   * @brief  Enable HSI oscillator in Stop mode
01707   * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
01708   * @retval None
01709   */
01710 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
01711 {
01712   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
01713 }
01714
01715 /**
01716   * @brief  Disable HSI oscillator in Stop mode
01717   * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
01718   * @retval None
01719   */
01720 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
01721 {
01722   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
01723 }
01724
01725 /**
01726   * @brief  Get HSI Calibration value
01727   * @note When HSITRIM is written, HSICAL is updated with the sum of
01728   *       HSITRIM and the factory trim value
01729   * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
01730   * @retval A value between 0 and 4095 (0xFFF)
01731   */
01732 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01733 {
01734   return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
01735 }
01736
01737 /**
01738   * @brief  Set HSI Calibration trimming
01739   * @note user-programmable trimming value that is added to the HSICAL
01740   * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
01741   *       should trim the HSI to 64 MHz +/- 1 %
01742   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01743   * @param  Parameter can be a value between 0 and 127 (63 for Cut1.x)
01744   * @retval None
01745   */
01746 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01747 {
01748 #if defined(RCC_VER_X)
01749   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
01750   {
01751     /* STM32H7 Rev.Y */
01752     MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
01753   }
01754   else
01755   {
01756     /* STM32H7 Rev.V */
01757     MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
01758   }
01759 #else
01760     MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
01761 #endif /* RCC_VER_X */
01762 }
01763
01764 /**
01765   * @brief  Get HSI Calibration trimming
01766   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01767   * @retval A value between 0 and 127 (63 for Cut1.x)
01768   */
01769 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01770 {
01771 #if defined(RCC_VER_X)
01772   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
01773   {
01774     /* STM32H7 Rev.Y */
01775     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
01776   }
01777   else
01778   {
01779     /* STM32H7 Rev.V */
01780     return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
01781   }
01782 #else
01783     return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
01784 #endif /* RCC_VER_X */
01785 }
01786
01787 /**
01788   * @}
01789   */
01790
01791 /** @defgroup RCC_LL_EF_CSI CSI
01792   * @{
01793   */
01794
01795 /**
01796   * @brief  Enable CSI oscillator
01797   * @rmtoll CR           CSION         LL_RCC_CSI_Enable
01798   * @retval None
01799   */
01800 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
01801 {
01802   SET_BIT(RCC->CR, RCC_CR_CSION);
01803 }
01804
01805 /**
01806   * @brief  Disable CSI oscillator
01807   * @rmtoll CR           CSION         LL_RCC_CSI_Disable
01808   * @retval None
01809   */
01810 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
01811 {
01812   CLEAR_BIT(RCC->CR, RCC_CR_CSION);
01813 }
01814
01815 /**
01816   * @brief  Check if CSI clock is ready
01817   * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
01818   * @retval State of bit (1 or 0).
01819   */
01820 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
01821 {
01822   return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
01823 }
01824
01825 /**
01826   * @brief  Enable CSI oscillator in Stop mode
01827   * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
01828   * @retval None
01829   */
01830 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
01831 {
01832   SET_BIT(RCC->CR, RCC_CR_CSIKERON);
01833 }
01834
01835 /**
01836   * @brief  Disable CSI oscillator in Stop mode
01837   * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
01841 {
01842   CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
01843 }
01844
01845 /**
01846   * @brief  Get CSI Calibration value
01847   * @note When CSITRIM is written, CSICAL is updated with the sum of
01848   *       CSITRIM and the factory trim value
01849   * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
01850   * @retval A value between 0 and 255 (0xFF)
01851   */
01852 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
01853 {
01854 #if defined(RCC_VER_X)
01855   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
01856   {
01857     /* STM32H7 Rev.Y */
01858     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
01859   }
01860   else
01861   {
01862     /* STM32H7 Rev.V */
01863     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
01864   }
01865 #else
01866     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
01867 #endif /* RCC_VER_X */
01868 }
01869
01870 /**
01871   * @brief  Set CSI Calibration trimming
01872   * @note user-programmable trimming value that is added to the CSICAL
01873   * @note Default value is 16, which, when added to the CSICAL value,
01874   *       should trim the CSI to 4 MHz +/- 1 %
01875   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
01876   * @param  Value can be a value between 0 and 31
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
01880 {
01881 #if defined(RCC_VER_X)
01882   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
01883   {
01884     /* STM32H7 Rev.Y */
01885     MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
01886   }
01887   else
01888   {
01889     /* STM32H7 Rev.V */
01890     MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
01891   }
01892 #else
01893     MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
01894 #endif /* RCC_VER_X */
01895 }
01896
01897 /**
01898   * @brief  Get CSI Calibration trimming
01899   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
01900   * @retval A value between 0 and 31
01901   */
01902 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
01903 {
01904 #if defined(RCC_VER_X)
01905   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
01906   {
01907     /* STM32H7 Rev.Y */
01908     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
01909   }
01910   else
01911   {
01912     /* STM32H7 Rev.V */
01913     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
01914   }
01915 #else
01916     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
01917 #endif /* RCC_VER_X */
01918 }
01919
01920 /**
01921   * @}
01922   */
01923
01924 /** @defgroup RCC_LL_EF_HSI48 HSI48
01925   * @{
01926   */
01927
01928 /**
01929   * @brief  Enable HSI48 oscillator
01930   * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
01931   * @retval None
01932   */
01933 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
01934 {
01935   SET_BIT(RCC->CR, RCC_CR_HSI48ON);
01936 }
01937
01938 /**
01939   * @brief  Disable HSI48 oscillator
01940   * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
01941   * @retval None
01942   */
01943 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
01944 {
01945   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
01946 }
01947
01948 /**
01949   * @brief  Check if HSI48 clock is ready
01950   * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
01951   * @retval State of bit (1 or 0).
01952   */
01953 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
01954 {
01955   return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
01956 }
01957
01958 /**
01959   * @brief  Get HSI48 Calibration value
01960   * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
01961   *       HSI48TRIM and the factory trim value
01962   * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
01963   * @retval A value between 0 and 1023 (0x3FF)
01964   */
01965 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
01966 {
01967   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
01968 }
01969 /**
01970   * @}
01971   */
01972
01973 #if defined(RCC_CR_D1CKRDY)
01974
01975 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY
01976   * @{
01977   */
01978
01979 /**
01980   * @brief  Check if D1 clock is ready
01981   * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
01982   * @retval State of bit (1 or 0).
01983   */
01984 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
01985 {
01986   return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
01987 }
01988
01989 /**
01990   * @}
01991   */
01992 #else
01993
01994 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
01995   * @{
01996   */
01997
01998 /**
01999   * @brief  Check if CPU clock is ready
02000   * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
02001   * @retval State of bit (1 or 0).
02002   */
02003 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
02004 {
02005   return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
02006 }
02007  /* alias */
02008 #define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
02009 /**
02010   * @}
02011   */
02012 #endif /* RCC_CR_D1CKRDY */
02013
02014 #if defined(RCC_CR_D2CKRDY)
02015
02016 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY
02017   * @{
02018   */
02019
02020 /**
02021   * @brief  Check if D2 clock is ready
02022   * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
02023   * @retval State of bit (1 or 0).
02024   */
02025 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
02026 {
02027   return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
02028 }
02029 /**
02030   * @}
02031   */
02032 #else
02033
02034 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY
02035   * @{
02036   */
02037
02038 /**
02039   * @brief  Check if CD clock is ready
02040   * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
02041   * @retval State of bit (1 or 0).
02042   */
02043 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
02044 {
02045   return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
02046 }
02047 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
02048 /**
02049   * @}
02050   */
02051 #endif /* RCC_CR_D2CKRDY */
02052
02053 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
02054   * @{
02055   */
02056 #if defined(RCC_GCR_WW1RSC)
02057
02058 /**
02059   * @brief  Enable system wide reset for Window Watch Dog 1
02060   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
02061   * @retval None.
02062   */
02063 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
02064 {
02065   SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
02066 }
02067
02068 /**
02069   * @brief  Check if Window Watch Dog 1 reset is system wide
02070   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
02071   * @retval State of bit (1 or 0).
02072   */
02073 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
02074 {
02075   return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
02076 }
02077 #endif  /* RCC_GCR_WW1RSC */
02078
02079 #if defined(DUAL_CORE)
02080 /**
02081   * @brief  Enable system wide reset for Window Watch Dog 2
02082   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
02083   * @retval None.
02084   */
02085 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
02086 {
02087   SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
02088 }
02089
02090 /**
02091   * @brief  Check if Window Watch Dog 2 reset is system wide
02092   * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
02093   * @retval State of bit (1 or 0).
02094   */
02095 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
02096 {
02097   return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
02098 }
02099 #endif  /*DUAL_CORE*/
02100 /**
02101   * @}
02102   */
02103
02104 #if defined(DUAL_CORE)
02105 /** @defgroup RCC_LL_EF_BOOT_CPU CPU
02106   * @{
02107   */
02108
02109 /**
02110   * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
02111   * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
02112   * @retval None.
02113   */
02114 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
02115 {
02116   SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
02117 }
02118
02119 /**
02120   * @brief  Check if CM4 boot is forced
02121   * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
02122   * @retval State of bit (1 or 0).
02123   */
02124 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
02125 {
02126   return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
02127 }
02128
02129 /**
02130   * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
02131   * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
02132   * @retval None.
02133   */
02134 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
02135 {
02136   SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
02137 }
02138
02139 /**
02140   * @brief  Check if CM7 boot is forced
02141   * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
02142   * @retval State of bit (1 or 0).
02143   */
02144 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
02145 {
02146   return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
02147 }
02148
02149 /**
02150   * @}
02151   */
02152 #endif  /*DUAL_CORE*/
02153
02154 /** @defgroup RCC_LL_EF_LSE LSE
02155   * @{
02156   */
02157
02158 /**
02159   * @brief  Enable the Clock Security System on LSE.
02160   * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
02161   *       a clock failure is detected.
02162   * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
02166 {
02167   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
02168 }
02169
02170 /**
02171   * @brief  Check if LSE failure is detected by Clock Security System
02172   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
02173   * @retval State of bit (1 or 0).
02174   */
02175 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
02176 {
02177   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
02178 }
02179
02180 /**
02181   * @brief  Enable  Low Speed External (LSE) crystal.
02182   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
02183   * @retval None
02184   */
02185 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
02186 {
02187   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
02188 }
02189
02190 /**
02191   * @brief  Disable  Low Speed External (LSE) crystal.
02192   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
02193   * @retval None
02194   */
02195 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
02196 {
02197   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
02198 }
02199
02200 /**
02201   * @brief  Enable external clock source (LSE bypass).
02202   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
02203   * @retval None
02204   */
02205 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
02206 {
02207   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
02208 }
02209
02210 /**
02211   * @brief  Disable external clock source (LSE bypass).
02212   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
02213   * @retval None
02214   */
02215 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
02216 {
02217   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
02218 }
02219
02220 #if defined(RCC_BDCR_LSEEXT)
02221 /**
02222   * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
02223   * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
02224   *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
02225   * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
02226   * @retval None
02227   */
02228 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
02229 {
02230   SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
02231 }
02232
02233 /**
02234   * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
02235   * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
02236   *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
02237   * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
02238   * @retval None
02239   */
02240 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
02241 {
02242   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
02243 }
02244 #endif /* RCC_BDCR_LSEEXT */
02245
02246 /**
02247   * @brief  Set LSE oscillator drive capability
02248   * @note The oscillator is in Xtal mode when it is not in bypass mode.
02249   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
02250   * @param  LSEDrive This parameter can be one of the following values:
02251   *         @arg @ref LL_RCC_LSEDRIVE_LOW
02252   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
02253   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
02254   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
02255   * @retval None
02256   */
02257 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
02258 {
02259   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
02260 }
02261
02262 /**
02263   * @brief  Get LSE oscillator drive capability
02264   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
02265   * @retval Returned value can be one of the following values:
02266   *         @arg @ref LL_RCC_LSEDRIVE_LOW
02267   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
02268   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
02269   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
02270   */
02271 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
02272 {
02273   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
02274 }
02275
02276 /**
02277   * @brief  Check if LSE oscillator Ready
02278   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
02279   * @retval State of bit (1 or 0).
02280   */
02281 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
02282 {
02283   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
02284 }
02285
02286 /**
02287   * @}
02288   */
02289
02290 /** @defgroup RCC_LL_EF_LSI LSI
02291   * @{
02292   */
02293
02294 /**
02295   * @brief  Enable LSI Oscillator
02296   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
02297   * @retval None
02298   */
02299 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
02300 {
02301   SET_BIT(RCC->CSR, RCC_CSR_LSION);
02302 }
02303
02304 /**
02305   * @brief  Disable LSI Oscillator
02306   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
02307   * @retval None
02308   */
02309 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
02310 {
02311   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
02312 }
02313
02314 /**
02315   * @brief  Check if LSI is Ready
02316   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
02317   * @retval State of bit (1 or 0).
02318   */
02319 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
02320 {
02321   return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
02322 }
02323
02324 /**
02325   * @}
02326   */
02327
02328 /** @defgroup RCC_LL_EF_System System
02329   * @{
02330   */
02331
02332 /**
02333   * @brief  Configure the system clock source
02334   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
02335   * @param  Source This parameter can be one of the following values:
02336   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
02337   *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
02338   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
02339   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
02340   * @retval None
02341   */
02342 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
02343 {
02344   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
02345 }
02346
02347 /**
02348   * @brief  Get the system clock source
02349   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
02350   * @retval Returned value can be one of the following values:
02351   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
02352   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
02353   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
02354   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
02355   */
02356 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
02357 {
02358   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
02359 }
02360
02361 /**
02362   * @brief  Configure the system wakeup clock source
02363   * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
02364   * @param  Source This parameter can be one of the following values:
02365   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
02366   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
02367   * @retval None
02368   */
02369 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
02370 {
02371   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
02372 }
02373
02374 /**
02375   * @brief  Get the system wakeup clock source
02376   * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
02377   * @retval Returned value can be one of the following values:
02378   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
02379   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
02380   */
02381 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
02382 {
02383   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
02384 }
02385
02386 /**
02387   * @brief  Configure the kernel wakeup clock source
02388   * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
02389   * @param  Source This parameter can be one of the following values:
02390   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
02391   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
02392   * @retval None
02393   */
02394 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
02395 {
02396   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
02397 }
02398
02399 /**
02400   * @brief  Get the kernel wakeup clock source
02401   * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
02402   * @retval Returned value can be one of the following values:
02403   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
02404   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
02405   */
02406 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
02407 {
02408   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
02409 }
02410
02411 /**
02412   * @brief  Set System prescaler
02413   * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
02414   * @param  Prescaler This parameter can be one of the following values:
02415   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02416   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02417   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02418   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02419   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02420   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02421   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02422   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02423   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02424   * @retval None
02425   */
02426 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
02427 {
02428 #if defined(RCC_D1CFGR_D1CPRE)
02429   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
02430 #else
02431   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
02432 #endif /* RCC_D1CFGR_D1CPRE */
02433 }
02434
02435 /**
02436   * @brief  Set AHB prescaler
02437   * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
02438   * @param  Prescaler This parameter can be one of the following values:
02439   *         @arg @ref LL_RCC_AHB_DIV_1
02440   *         @arg @ref LL_RCC_AHB_DIV_2
02441   *         @arg @ref LL_RCC_AHB_DIV_4
02442   *         @arg @ref LL_RCC_AHB_DIV_8
02443   *         @arg @ref LL_RCC_AHB_DIV_16
02444   *         @arg @ref LL_RCC_AHB_DIV_64
02445   *         @arg @ref LL_RCC_AHB_DIV_128
02446   *         @arg @ref LL_RCC_AHB_DIV_256
02447   *         @arg @ref LL_RCC_AHB_DIV_512
02448   * @retval None
02449   */
02450 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
02451 {
02452 #if defined(RCC_D1CFGR_HPRE)
02453   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
02454 #else
02455   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
02456 #endif /* RCC_D1CFGR_HPRE */
02457 }
02458
02459 /**
02460   * @brief  Set APB1 prescaler
02461   * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
02462   * @param  Prescaler This parameter can be one of the following values:
02463   *         @arg @ref LL_RCC_APB1_DIV_1
02464   *         @arg @ref LL_RCC_APB1_DIV_2
02465   *         @arg @ref LL_RCC_APB1_DIV_4
02466   *         @arg @ref LL_RCC_APB1_DIV_8
02467   *         @arg @ref LL_RCC_APB1_DIV_16
02468   * @retval None
02469   */
02470 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
02471 {
02472 #if defined(RCC_D2CFGR_D2PPRE1)
02473   MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
02474 #else
02475   MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
02476 #endif /* RCC_D2CFGR_D2PPRE1 */
02477 }
02478
02479 /**
02480   * @brief  Set APB2 prescaler
02481   * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
02482   * @param  Prescaler This parameter can be one of the following values:
02483   *         @arg @ref LL_RCC_APB2_DIV_1
02484   *         @arg @ref LL_RCC_APB2_DIV_2
02485   *         @arg @ref LL_RCC_APB2_DIV_4
02486   *         @arg @ref LL_RCC_APB2_DIV_8
02487   *         @arg @ref LL_RCC_APB2_DIV_16
02488   * @retval None
02489   */
02490 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
02491 {
02492 #if defined(RCC_D2CFGR_D2PPRE2)
02493   MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
02494 #else
02495   MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
02496 #endif /* RCC_D2CFGR_D2PPRE2 */
02497 }
02498
02499 /**
02500   * @brief  Set APB3 prescaler
02501   * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
02502   * @param  Prescaler This parameter can be one of the following values:
02503   *         @arg @ref LL_RCC_APB3_DIV_1
02504   *         @arg @ref LL_RCC_APB3_DIV_2
02505   *         @arg @ref LL_RCC_APB3_DIV_4
02506   *         @arg @ref LL_RCC_APB3_DIV_8
02507   *         @arg @ref LL_RCC_APB3_DIV_16
02508   * @retval None
02509   */
02510 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
02511 {
02512 #if defined(RCC_D1CFGR_D1PPRE)
02513   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
02514 #else
02515   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
02516 #endif /* RCC_D1CFGR_D1PPRE */
02517 }
02518
02519 /**
02520   * @brief  Set APB4 prescaler
02521   * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
02522   * @param  Prescaler This parameter can be one of the following values:
02523   *         @arg @ref LL_RCC_APB4_DIV_1
02524   *         @arg @ref LL_RCC_APB4_DIV_2
02525   *         @arg @ref LL_RCC_APB4_DIV_4
02526   *         @arg @ref LL_RCC_APB4_DIV_8
02527   *         @arg @ref LL_RCC_APB4_DIV_16
02528   * @retval None
02529   */
02530 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
02531 {
02532 #if defined(RCC_D3CFGR_D3PPRE)
02533   MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
02534 #else
02535   MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
02536 #endif /* RCC_D3CFGR_D3PPRE */
02537 }
02538
02539 /**
02540   * @brief  Get System prescaler
02541   * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
02542   * @retval Returned value can be one of the following values:
02543   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02544   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02545   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02546   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02547   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02548   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02549   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02550   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02551   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02552   */
02553 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
02554 {
02555 #if defined(RCC_D1CFGR_D1CPRE)
02556   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
02557 #else
02558   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
02559 #endif /* RCC_D1CFGR_D1CPRE */
02560 }
02561
02562 /**
02563   * @brief  Get AHB prescaler
02564   * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
02565   * @retval Returned value can be one of the following values:
02566   *         @arg @ref LL_RCC_AHB_DIV_1
02567   *         @arg @ref LL_RCC_AHB_DIV_2
02568   *         @arg @ref LL_RCC_AHB_DIV_4
02569   *         @arg @ref LL_RCC_AHB_DIV_8
02570   *         @arg @ref LL_RCC_AHB_DIV_16
02571   *         @arg @ref LL_RCC_AHB_DIV_64
02572   *         @arg @ref LL_RCC_AHB_DIV_128
02573   *         @arg @ref LL_RCC_AHB_DIV_256
02574   *         @arg @ref LL_RCC_AHB_DIV_512
02575   */
02576 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
02577 {
02578 #if defined(RCC_D1CFGR_HPRE)
02579   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
02580 #else
02581   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
02582 #endif /* RCC_D1CFGR_HPRE */
02583 }
02584
02585 /**
02586   * @brief  Get APB1 prescaler
02587   * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
02588   * @retval Returned value can be one of the following values:
02589   *         @arg @ref LL_RCC_APB1_DIV_1
02590   *         @arg @ref LL_RCC_APB1_DIV_2
02591   *         @arg @ref LL_RCC_APB1_DIV_4
02592   *         @arg @ref LL_RCC_APB1_DIV_8
02593   *         @arg @ref LL_RCC_APB1_DIV_16
02594   */
02595 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
02596 {
02597 #if defined(RCC_D2CFGR_D2PPRE1)
02598   return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
02599 #else
02600   return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
02601 #endif /* RCC_D2CFGR_D2PPRE1 */
02602 }
02603
02604 /**
02605   * @brief  Get APB2 prescaler
02606   * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
02607   * @retval Returned value can be one of the following values:
02608   *         @arg @ref LL_RCC_APB2_DIV_1
02609   *         @arg @ref LL_RCC_APB2_DIV_2
02610   *         @arg @ref LL_RCC_APB2_DIV_4
02611   *         @arg @ref LL_RCC_APB2_DIV_8
02612   *         @arg @ref LL_RCC_APB2_DIV_16
02613   */
02614 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
02615 {
02616 #if defined(RCC_D2CFGR_D2PPRE2)
02617   return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
02618 #else
02619   return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
02620 #endif /* RCC_D2CFGR_D2PPRE2 */
02621 }
02622
02623 /**
02624   * @brief  Get APB3 prescaler
02625   * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
02626   * @retval Returned value can be one of the following values:
02627   *         @arg @ref LL_RCC_APB3_DIV_1
02628   *         @arg @ref LL_RCC_APB3_DIV_2
02629   *         @arg @ref LL_RCC_APB3_DIV_4
02630   *         @arg @ref LL_RCC_APB3_DIV_8
02631   *         @arg @ref LL_RCC_APB3_DIV_16
02632   */
02633 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
02634 {
02635 #if defined(RCC_D1CFGR_D1PPRE)
02636   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
02637 #else
02638   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
02639 #endif /* RCC_D1CFGR_D1PPRE */
02640 }
02641
02642 /**
02643   * @brief  Get APB4 prescaler
02644   * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
02645   * @retval Returned value can be one of the following values:
02646   *         @arg @ref LL_RCC_APB4_DIV_1
02647   *         @arg @ref LL_RCC_APB4_DIV_2
02648   *         @arg @ref LL_RCC_APB4_DIV_4
02649   *         @arg @ref LL_RCC_APB4_DIV_8
02650   *         @arg @ref LL_RCC_APB4_DIV_16
02651   */
02652 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
02653 {
02654 #if defined(RCC_D3CFGR_D3PPRE)
02655   return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
02656 #else
02657   return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
02658 #endif /* RCC_D3CFGR_D3PPRE */
02659 }
02660
02661 /**
02662   * @}
02663   */
02664
02665 /** @defgroup RCC_LL_EF_MCO MCO
02666   * @{
02667   */
02668
02669 /**
02670   * @brief  Configure MCOx
02671   * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
02672   *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
02673   *         CFGR         MCO2          LL_RCC_ConfigMCO\n
02674   *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
02675   * @param  MCOxSource This parameter can be one of the following values:
02676   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
02677   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
02678   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
02679   *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
02680   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
02681   *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
02682   *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
02683   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
02684   *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
02685   *         @arg @ref LL_RCC_MCO2SOURCE_CSI
02686   *         @arg @ref LL_RCC_MCO2SOURCE_LSI
02687   * @param  MCOxPrescaler This parameter can be one of the following values:
02688   *         @arg @ref LL_RCC_MCO1_DIV_1
02689   *         @arg @ref LL_RCC_MCO1_DIV_2
02690   *         @arg @ref LL_RCC_MCO1_DIV_3
02691   *         @arg @ref LL_RCC_MCO1_DIV_4
02692   *         @arg @ref LL_RCC_MCO1_DIV_5
02693   *         @arg @ref LL_RCC_MCO1_DIV_6
02694   *         @arg @ref LL_RCC_MCO1_DIV_7
02695   *         @arg @ref LL_RCC_MCO1_DIV_8
02696   *         @arg @ref LL_RCC_MCO1_DIV_9
02697   *         @arg @ref LL_RCC_MCO1_DIV_10
02698   *         @arg @ref LL_RCC_MCO1_DIV_11
02699   *         @arg @ref LL_RCC_MCO1_DIV_12
02700   *         @arg @ref LL_RCC_MCO1_DIV_13
02701   *         @arg @ref LL_RCC_MCO1_DIV_14
02702   *         @arg @ref LL_RCC_MCO1_DIV_15
02703   *         @arg @ref LL_RCC_MCO2_DIV_1
02704   *         @arg @ref LL_RCC_MCO2_DIV_2
02705   *         @arg @ref LL_RCC_MCO2_DIV_3
02706   *         @arg @ref LL_RCC_MCO2_DIV_4
02707   *         @arg @ref LL_RCC_MCO2_DIV_5
02708   *         @arg @ref LL_RCC_MCO2_DIV_6
02709   *         @arg @ref LL_RCC_MCO2_DIV_7
02710   *         @arg @ref LL_RCC_MCO2_DIV_8
02711   *         @arg @ref LL_RCC_MCO2_DIV_9
02712   *         @arg @ref LL_RCC_MCO2_DIV_10
02713   *         @arg @ref LL_RCC_MCO2_DIV_11
02714   *         @arg @ref LL_RCC_MCO2_DIV_12
02715   *         @arg @ref LL_RCC_MCO2_DIV_13
02716   *         @arg @ref LL_RCC_MCO2_DIV_14
02717   *         @arg @ref LL_RCC_MCO2_DIV_15
02718   * @retval None
02719   */
02720 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
02721 {
02722   MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
02723 }
02724
02725 /**
02726   * @}
02727   */
02728
02729 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
02730   * @{
02731   */
02732
02733 /**
02734   * @brief  Configure periph clock source
02735   * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
02736   *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
02737   *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
02738   * @param  ClkSource This parameter can be one of the following values:
02739   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
02740   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
02741   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
02742   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
02743   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
02744   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
02745   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
02746   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
02747   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
02748   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
02749   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
02750   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
02751   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
02752   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
02753   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
02754   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
02755   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
02756   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
02757   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
02758   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
02759   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02760   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
02761   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
02762   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02763   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02764   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
02765   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
02766   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
02767   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
02768   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02769   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02770   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
02771   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
02772   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
02773   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
02774   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
02775   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
02776   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
02777   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
02778   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
02779   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
02780   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
02781   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
02782   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
02783   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
02784   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
02785   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
02786   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
02787   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
02788   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
02789   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
02790   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
02791   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
02792   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
02793   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
02794   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
02795   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
02796   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
02797   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
02798   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
02799   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
02800   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
02801   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
02802   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
02803   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
02804   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
02805   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
02806   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
02807   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
02808   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
02809   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
02810   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
02811   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
02812   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
02813   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
02814   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
02815   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
02816   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
02817   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
02818   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
02819   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
02820   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
02821   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
02822   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
02823   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
02824   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
02825   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
02826   *
02827   *         (*) value not defined in all devices.
02828   * @retval None
02829   */
02830 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
02831 {
02832 #if defined(RCC_D1CCIPR_FMCSEL)
02833   register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
02834 #else
02835   register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
02836 #endif /*  */
02837   MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
02838 }
02839
02840 /**
02841   * @brief  Configure USARTx clock source
02842   * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
02843   *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
02844   * @param  ClkSource This parameter can be one of the following values:
02845   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
02846   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
02847   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
02848   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
02849   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
02850   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
02851   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
02852   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
02853   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
02854   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
02855   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
02856   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
02857   * @retval None
02858   */
02859 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
02860 {
02861   LL_RCC_SetClockSource(ClkSource);
02862 }
02863
02864 /**
02865   * @brief  Configure LPUARTx clock source
02866   * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
02867   * @param  ClkSource This parameter can be one of the following values:
02868   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
02869   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
02870   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
02871   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02872   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
02873   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02874   * @retval None
02875   */
02876 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
02877 {
02878 #if defined(RCC_D3CCIPR_LPUART1SEL)
02879   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
02880 #else
02881   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
02882 #endif /* RCC_D3CCIPR_LPUART1SEL */
02883 }
02884
02885 /**
02886   * @brief  Configure I2Cx clock source
02887   * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
02888   *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
02889   * @param  ClkSource This parameter can be one of the following values:
02890   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
02891   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
02892   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
02893   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
02894   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
02895   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
02896   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
02897   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
02898   * @retval None
02899   */
02900 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
02901 {
02902   LL_RCC_SetClockSource(ClkSource);
02903 }
02904
02905 /**
02906   * @brief  Configure LPTIMx clock source
02907   * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
02908   *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
02909   *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
02910   * @param  ClkSource This parameter can be one of the following values:
02911   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02912   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
02913   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
02914   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02915   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02916   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
02917   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
02918   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
02919   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
02920   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02921   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02922   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
02923   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
02924   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
02925   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
02926   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
02927   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
02928   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
02929   * @retval None
02930   */
02931 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
02932 {
02933   LL_RCC_SetClockSource(ClkSource);
02934 }
02935
02936 /**
02937   * @brief  Configure SAIx clock source
02938   * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
02939   *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
02940   *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
02941   *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
02942   * @param  ClkSource This parameter can be one of the following values:
02943   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
02944   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
02945   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
02946   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
02947   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
02948   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
02949   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
02950   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
02951   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
02952   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
02953   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
02954   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
02955   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
02956   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
02957   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
02958   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
02959   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
02960   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
02961   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
02962   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
02963   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
02964   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
02965   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
02966   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
02967   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
02968   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
02969   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
02970   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
02971   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
02972   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
02973   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
02974   *
02975   *         (*) value not defined in all devices.
02976   * @retval None
02977   */
02978 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
02979 {
02980   LL_RCC_SetClockSource(ClkSource);
02981 }
02982
02983 /**
02984   * @brief  Configure SDMMCx clock source
02985   * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
02986   * @param  ClkSource This parameter can be one of the following values:
02987   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
02988   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
02989   * @retval None
02990   */
02991 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
02992 {
02993 #if defined(RCC_D1CCIPR_SDMMCSEL)
02994   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
02995 #else
02996   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
02997 #endif /* RCC_D1CCIPR_SDMMCSEL */
02998 }
02999
03000 /**
03001   * @brief  Configure RNGx clock source
03002   * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
03003   * @param  ClkSource This parameter can be one of the following values:
03004   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
03005   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
03006   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
03007   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
03008   * @retval None
03009   */
03010 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
03011 {
03012 #if defined(RCC_D2CCIP2R_RNGSEL)
03013   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
03014 #else
03015   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
03016 #endif /* RCC_D2CCIP2R_RNGSEL */
03017 }
03018
03019 /**
03020   * @brief  Configure USBx clock source
03021   * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
03022   * @param  ClkSource This parameter can be one of the following values:
03023   *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
03024   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
03025   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
03026   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
03027   * @retval None
03028   */
03029 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
03030 {
03031 #if defined(RCC_D2CCIP2R_USBSEL)
03032   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
03033 #else
03034   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
03035 #endif /* RCC_D2CCIP2R_USBSEL */
03036 }
03037
03038 /**
03039   * @brief  Configure CECx clock source
03040   * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
03041   * @param  ClkSource This parameter can be one of the following values:
03042   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
03043   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
03044   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
03045   * @retval None
03046   */
03047 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
03048 {
03049 #if defined(RCC_D2CCIP2R_CECSEL)
03050   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
03051 #else
03052   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
03053 #endif /* RCC_D2CCIP2R_CECSEL */
03054 }
03055
03056 #if defined(DSI)
03057 /**
03058   * @brief  Configure DSIx clock source
03059   * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
03060   * @param  ClkSource This parameter can be one of the following values:
03061   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
03062   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
03063   * @retval None
03064   */
03065 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
03066 {
03067   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
03068 }
03069 #endif /* DSI */
03070
03071 /**
03072   * @brief  Configure DFSDMx Kernel clock source
03073   * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
03074   * @param  ClkSource This parameter can be one of the following values:
03075   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
03076   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
03077   * @retval None
03078   */
03079 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
03080 {
03081 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
03082   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
03083 #else
03084   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
03085 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
03086 }
03087
03088 #if defined(DFSDM2_BASE)
03089 /**
03090   * @brief  Configure DFSDMx Kernel clock source
03091   * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
03092   * @param  ClkSource This parameter can be one of the following values:
03093   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2
03094   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
03095   * @retval None
03096   */
03097 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
03098 {
03099    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
03100 }
03101 #endif /* DFSDM2 */
03102
03103 /**
03104   * @brief  Configure FMCx Kernel clock source
03105   * @rmtoll D1CCIPR / CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
03106   * @param  ClkSource This parameter can be one of the following values:
03107   *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
03108   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
03109   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
03110   *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
03111   * @retval None
03112   */
03113 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
03114 {
03115 #if defined(RCC_D1CCIPR_FMCSEL)
03116   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
03117 #else
03118   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
03119 #endif /* RCC_D1CCIPR_FMCSEL */
03120 }
03121
03122 #if defined(QUADSPI)
03123 /**
03124   * @brief  Configure QSPIx Kernel clock source
03125   * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
03126   * @param  ClkSource This parameter can be one of the following values:
03127   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
03128   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
03129   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
03130   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
03131   * @retval None
03132   */
03133 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
03134 {
03135   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
03136 }
03137 #endif /* QUADSPI */
03138
03139 #if defined(OCTOSPI1) || defined(OCTOSPI2)
03140 /**
03141   * @brief  Configure OSPIx Kernel clock source
03142   * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
03143   * @param  ClkSource This parameter can be one of the following values:
03144   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
03145   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
03146   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
03147   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
03148   * @retval None
03149   */
03150 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
03151 {
03152   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
03153 }
03154 #endif /* OCTOSPI1 || OCTOSPI2 */
03155
03156 /**
03157   * @brief  Configure CLKP Kernel clock source
03158   * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
03159   * @param  ClkSource This parameter can be one of the following values:
03160   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
03161   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
03162   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
03163   * @retval None
03164   */
03165 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
03166 {
03167 #if defined(RCC_D1CCIPR_CKPERSEL)
03168   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
03169 #else
03170   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
03171 #endif /* RCC_D1CCIPR_CKPERSEL */
03172 }
03173
03174 /**
03175   * @brief  Configure SPIx Kernel clock source
03176   * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
03177   *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
03178   *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
03179   * @param  ClkSource This parameter can be one of the following values:
03180   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
03181   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
03182   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
03183   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
03184   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
03185   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
03186   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
03187   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
03188   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
03189   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
03190   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
03191   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
03192   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
03193   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
03194   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
03195   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
03196   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
03197   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
03198   *
03199   *         (*) value not defined in all devices.
03200   * @retval None
03201   */
03202 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
03203 {
03204   LL_RCC_SetClockSource(ClkSource);
03205 }
03206
03207 /**
03208   * @brief  Configure SPDIFx Kernel clock source
03209   * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
03210   * @param  ClkSource This parameter can be one of the following values:
03211   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
03212   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
03213   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
03214   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
03215   * @retval None
03216   */
03217 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
03218 {
03219 #if defined(RCC_D2CCIP1R_SPDIFSEL)
03220   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
03221 #else
03222   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
03223 #endif /* RCC_D2CCIP1R_SPDIFSEL */
03224 }
03225
03226 /**
03227   * @brief  Configure FDCANx Kernel clock source
03228   * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
03229   * @param  ClkSource This parameter can be one of the following values:
03230   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
03231   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
03232   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
03233   * @retval None
03234   */
03235 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
03236 {
03237 #if defined(RCC_D2CCIP1R_FDCANSEL)
03238   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
03239 #else
03240   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
03241 #endif /* RCC_D2CCIP1R_FDCANSEL */
03242 }
03243
03244 /**
03245   * @brief  Configure SWPx Kernel clock source
03246   * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
03247   * @param  ClkSource This parameter can be one of the following values:
03248   *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
03249   *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
03250   * @retval None
03251   */
03252 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
03253 {
03254 #if defined(RCC_D2CCIP1R_SWPSEL)
03255   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
03256 #else
03257   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
03258 #endif /* RCC_D2CCIP1R_SWPSEL */
03259 }
03260
03261 /**
03262   * @brief  Configure ADCx Kernel clock source
03263   * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
03264   * @param  ClkSource This parameter can be one of the following values:
03265   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
03266   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
03267   *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
03268   * @retval None
03269   */
03270 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
03271 {
03272 #if defined(RCC_D3CCIPR_ADCSEL)
03273   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
03274 #else
03275   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
03276 #endif /* RCC_D3CCIPR_ADCSEL */
03277 }
03278
03279 /**
03280   * @brief  Get periph clock source
03281   * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
03282   *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
03283   *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
03284   *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
03285   * @param  Periph This parameter can be one of the following values:
03286   *         @arg @ref LL_RCC_USART16_CLKSOURCE
03287   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
03288   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
03289   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
03290   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
03291   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
03292   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
03293   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
03294   *         @arg @ref LL_RCC_SAI23_CLKSOURCE
03295   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
03296   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
03297   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
03298   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
03299   *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
03300   *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
03301   *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
03302   * @retval Returned value can be one of the following values:
03303   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
03304   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
03305   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
03306   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
03307   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
03308   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
03309   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
03310   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
03311   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
03312   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
03313   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
03314   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
03315   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
03316   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
03317   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
03318   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
03319   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
03320   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
03321   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
03322   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
03323   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
03324   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
03325   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
03326   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
03327   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
03328   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
03329   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
03330   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
03331   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
03332   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
03333   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
03334   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
03335   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
03336   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
03337   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
03338   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
03339   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
03340   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
03341   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
03342   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
03343   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
03344   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
03345   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
03346   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
03347   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
03348   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
03349   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
03350   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
03351   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
03352   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
03353   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
03354   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
03355   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
03356   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
03357   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
03358   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
03359   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
03360   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
03361   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
03362   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
03363   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
03364   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
03365   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
03366   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
03367   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
03368   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
03369   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
03370   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
03371   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
03372   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
03373   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
03374   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
03375   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
03376   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
03377   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
03378   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
03379   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
03380   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
03381   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
03382   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
03383   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
03384   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
03385   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
03386   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
03387   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
03388   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
03389   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
03390   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
03391   *
03392   *         (*) value not defined in all devices.
03393   * @retval None
03394   */
03395 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
03396 {
03397 #if defined(RCC_D1CCIPR_FMCSEL)
03398   register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
03399 #else
03400   register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
03401 #endif /* RCC_D1CCIPR_FMCSEL */
03402   return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
03403 }
03404
03405 /**
03406   * @brief  Get USARTx clock source
03407   * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
03408   *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
03409   * @param  Periph This parameter can be one of the following values:
03410   *         @arg @ref LL_RCC_USART16_CLKSOURCE
03411   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
03412   * @retval Returned value can be one of the following values:
03413   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
03414   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
03415   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
03416   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
03417   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
03418   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
03419   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
03420   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
03421   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
03422   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
03423   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
03424   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
03425   */
03426 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
03427 {
03428   return LL_RCC_GetClockSource(Periph);
03429 }
03430
03431 /**
03432   * @brief  Get LPUART clock source
03433   * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
03434   * @param  Periph This parameter can be one of the following values:
03435   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
03436   * @retval Returned value can be one of the following values:
03437   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
03438   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
03439   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
03440   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
03441   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
03442   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
03443   */
03444 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
03445 {
03446   UNUSED(Periph);
03447 #if defined(RCC_D3CCIPR_LPUART1SEL)
03448   return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
03449 #else
03450   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
03451 #endif  /* RCC_D3CCIPR_LPUART1SEL */
03452 }
03453
03454 /**
03455   * @brief  Get I2Cx clock source
03456   * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
03457   *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
03458   * @param  Periph This parameter can be one of the following values:
03459   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
03460   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
03461   * @retval Returned value can be one of the following values:
03462   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
03463   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
03464   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
03465   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
03466   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
03467   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
03468   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
03469   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
03470   */
03471 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
03472 {
03473   return LL_RCC_GetClockSource(Periph);
03474 }
03475
03476 /**
03477   * @brief  Get LPTIM clock source
03478   * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
03479   *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
03480   *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
03481   * @param  Perihp This parameter can be one of the following values:
03482   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
03483   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
03484   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
03485   * @retval Returned value can be one of the following values:
03486   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
03487   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
03488   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
03489   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
03490   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
03491   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
03492   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
03493   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
03494   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
03495   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
03496   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
03497   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
03498   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
03499   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
03500   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
03501   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
03502   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
03503   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
03504   * @retval None
03505   */
03506 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
03507 {
03508   return LL_RCC_GetClockSource(Periph);
03509 }
03510
03511 /**
03512   * @brief  Get SAIx clock source
03513   * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
03514   *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
03515   *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
03516   *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
03517   * @param  Periph This parameter can be one of the following values:
03518   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
03519   *         @arg @ref LL_RCC_SAI23_CLKSOURCE
03520   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE
03521   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE
03522   * @retval Returned value can be one of the following values:
03523   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
03524   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
03525   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
03526   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
03527   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
03528   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
03529   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
03530   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
03531   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
03532   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
03533   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
03534   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
03535   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
03536   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
03537   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
03538   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
03539   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
03540   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
03541   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
03542   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
03543   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
03544   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
03545   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
03546   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
03547   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
03548   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
03549   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
03550   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
03551   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
03552   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
03553   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
03554   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
03555   *
03556   *  (*) value not defined in all devices.
03557   */
03558 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
03559 {
03560   return LL_RCC_GetClockSource(Periph);
03561 }
03562
03563 /**
03564   * @brief  Get SDMMC clock source
03565   * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
03566   * @param  Periph This parameter can be one of the following values:
03567   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
03568   * @retval Returned value can be one of the following values:
03569   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
03570   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
03571   */
03572 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
03573 {
03574   UNUSED(Periph);
03575 #if defined(RCC_D1CCIPR_SDMMCSEL)
03576   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
03577 #else
03578   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
03579 #endif /* RCC_D1CCIPR_SDMMCSEL */
03580 }
03581
03582 /**
03583   * @brief  Get RNG clock source
03584   * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
03585   * @param  Periph This parameter can be one of the following values:
03586   *         @arg @ref LL_RCC_RNG_CLKSOURCE
03587   * @retval Returned value can be one of the following values:
03588   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
03589   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
03590   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
03591   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
03592   */
03593 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
03594 {
03595   UNUSED(Periph);
03596 #if defined(RCC_D2CCIP2R_RNGSEL)
03597   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
03598 #else
03599   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
03600 #endif /* RCC_D2CCIP2R_RNGSEL */
03601 }
03602
03603 /**
03604   * @brief  Get USB clock source
03605   * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
03606   * @param  Periph This parameter can be one of the following values:
03607   *         @arg @ref LL_RCC_USB_CLKSOURCE
03608   * @retval Returned value can be one of the following values:
03609   *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
03610   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
03611   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
03612   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
03613   */
03614 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
03615 {
03616   UNUSED(Periph);
03617 #if defined(RCC_D2CCIP2R_USBSEL)
03618   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
03619 #else
03620   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
03621 #endif /* RCC_D2CCIP2R_USBSEL */
03622 }
03623
03624 /**
03625   * @brief  Get CEC clock source
03626   * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
03627   * @param  Periph This parameter can be one of the following values:
03628   *         @arg @ref LL_RCC_CEC_CLKSOURCE
03629   * @retval Returned value can be one of the following values:
03630   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
03631   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
03632   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
03633   */
03634 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
03635 {
03636   UNUSED(Periph);
03637 #if defined(RCC_D2CCIP2R_CECSEL)
03638   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
03639 #else
03640   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
03641 #endif  /* RCC_D2CCIP2R_CECSEL */
03642 }
03643
03644 #if defined(DSI)
03645 /**
03646   * @brief  Get DSI clock source
03647   * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
03648   * @param  Periph This parameter can be one of the following values:
03649   *         @arg @ref LL_RCC_DSI_CLKSOURCE
03650   * @retval Returned value can be one of the following values:
03651   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
03652   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
03653   */
03654 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
03655 {
03656   UNUSED(Periph);
03657   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
03658 }
03659 #endif /* DSI */
03660
03661 /**
03662   * @brief  Get DFSDM Kernel clock source
03663   * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
03664   * @param  Periph This parameter can be one of the following values:
03665   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
03666   * @retval Returned value can be one of the following values:
03667   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
03668   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
03669   */
03670 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
03671 {
03672   UNUSED(Periph);
03673 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
03674   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
03675 #else
03676   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
03677 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
03678 }
03679
03680 #if defined(DFSDM2_BASE)
03681 /**
03682   * @brief  Get DFSDM2 Kernel clock source
03683   * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
03684   * @param  Periph This parameter can be one of the following values:
03685   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
03686   * @retval Returned value can be one of the following values:
03687   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
03688   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
03689   */
03690 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
03691 {
03692   UNUSED(Periph);
03693   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
03694 }
03695 #endif /* DFSDM2_BASE */
03696
03697 /**
03698   * @brief  Get FMC Kernel clock source
03699   * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
03700   * @param  Periph This parameter can be one of the following values:
03701   *         @arg @ref LL_RCC_FMC_CLKSOURCE
03702   * @retval Returned value can be one of the following values:
03703   *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
03704   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
03705   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
03706   *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
03707   */
03708 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
03709 {
03710   UNUSED(Periph);
03711 #if defined(RCC_D1CCIPR_FMCSEL)
03712   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
03713 #else
03714   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
03715 #endif /* RCC_D1CCIPR_FMCSEL */
03716 }
03717
03718 #if defined(QUADSPI)
03719 /**
03720   * @brief  Get QSPI Kernel clock source
03721   * @rmtoll D1CCIPR / CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
03722   * @param  Periph This parameter can be one of the following values:
03723   *         @arg @ref LL_RCC_QSPI_CLKSOURCE
03724   * @retval Returned value can be one of the following values:
03725   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
03726   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
03727   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
03728   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
03729   */
03730 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
03731 {
03732   UNUSED(Periph);
03733   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
03734 }
03735 #endif /* QUADSPI */
03736
03737 #if defined(OCTOSPI1) || defined(OCTOSPI2)
03738 /**
03739   * @brief  Get OSPI Kernel clock source
03740   * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
03741   * @param  Periph This parameter can be one of the following values:
03742   *         @arg @ref LL_RCC_OSPI_CLKSOURCE
03743   * @retval Returned value can be one of the following values:
03744   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
03745   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
03746   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
03747   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
03748   */
03749 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
03750 {
03751   UNUSED(Periph);
03752   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
03753 }
03754 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
03755
03756 /**
03757   * @brief  Get CLKP Kernel clock source
03758   * @rmtoll D1CCIPR / CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
03759   * @param  Periph This parameter can be one of the following values:
03760   *         @arg @ref LL_RCC_CLKP_CLKSOURCE
03761   * @retval Returned value can be one of the following values:
03762   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
03763   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
03764   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
03765   */
03766 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
03767 {
03768   UNUSED(Periph);
03769 #if defined(RCC_D1CCIPR_CKPERSEL)
03770   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
03771 #else
03772   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
03773 #endif /* RCC_D1CCIPR_CKPERSEL */
03774 }
03775
03776 /**
03777   * @brief  Get SPIx Kernel clock source
03778   * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
03779   *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
03780   *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
03781   * @param  Periph This parameter can be one of the following values:
03782   *         @arg @ref LL_RCC_SPI123_CLKSOURCE
03783   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
03784   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
03785   * @retval Returned value can be one of the following values:
03786   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
03787   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
03788   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
03789   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
03790   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
03791   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
03792   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
03793   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
03794   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
03795   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
03796   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
03797   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
03798   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
03799   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
03800   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
03801   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
03802   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
03803   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
03804   *
03805   *         (*) value not defined in all stm32h7xx lines.
03806   */
03807 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
03808 {
03809   return LL_RCC_GetClockSource(Periph);
03810 }
03811
03812 /**
03813   * @brief  Get SPDIF Kernel clock source
03814   * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
03815   * @param  Periph This parameter can be one of the following values:
03816   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
03817   * @retval Returned value can be one of the following values:
03818   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
03819   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
03820   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
03821   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
03822   */
03823 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
03824 {
03825   UNUSED(Periph);
03826 #if defined(RCC_D2CCIP1R_SPDIFSEL)
03827   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
03828 #else
03829   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
03830 #endif /* RCC_D2CCIP1R_SPDIFSEL */
03831 }
03832
03833 /**
03834   * @brief  Get FDCAN Kernel clock source
03835   * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
03836   * @param  Periph This parameter can be one of the following values:
03837   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
03838   * @retval Returned value can be one of the following values:
03839   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
03840   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
03841   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
03842   */
03843 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
03844 {
03845   UNUSED(Periph);
03846 #if defined(RCC_D2CCIP1R_FDCANSEL)
03847   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
03848 #else
03849   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
03850 #endif /* RCC_D2CCIP1R_FDCANSEL */
03851 }
03852
03853 /**
03854   * @brief  Get SWP Kernel clock source
03855   * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
03856   * @param  Periph This parameter can be one of the following values:
03857   *         @arg @ref LL_RCC_SWP_CLKSOURCE
03858   * @retval Returned value can be one of the following values:
03859   *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
03860   *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
03861   */
03862 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
03863 {
03864   UNUSED(Periph);
03865 #if defined(RCC_D2CCIP1R_SWPSEL)
03866   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
03867 #else
03868   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
03869 #endif /* RCC_D2CCIP1R_SWPSEL */
03870 }
03871
03872 /**
03873   * @brief  Get ADC Kernel clock source
03874   * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
03875   * @param  Periph This parameter can be one of the following values:
03876   *         @arg @ref LL_RCC_ADC_CLKSOURCE
03877   * @retval Returned value can be one of the following values:
03878   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
03879   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
03880   *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
03881   */
03882 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
03883 {
03884   UNUSED(Periph);
03885 #if defined (RCC_D3CCIPR_ADCSEL)
03886   return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
03887 #else
03888   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
03889 #endif /* RCC_D3CCIPR_ADCSEL */
03890 }
03891
03892 /**
03893   * @}
03894   */
03895
03896 /** @defgroup RCC_LL_EF_RTC RTC
03897   * @{
03898   */
03899
03900 /**
03901   * @brief  Set RTC Clock Source
03902   * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
03903   *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
03904   *         set). The BDRST bit can be used to reset them.
03905   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
03906   * @param  Source This parameter can be one of the following values:
03907   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
03908   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
03909   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
03910   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
03911   * @retval None
03912   */
03913 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
03914 {
03915   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
03916 }
03917
03918 /**
03919   * @brief  Get RTC Clock Source
03920   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
03921   * @retval Returned value can be one of the following values:
03922   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
03923   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
03924   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
03925   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
03926   */
03927 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
03928 {
03929   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
03930 }
03931
03932 /**
03933   * @brief  Enable RTC
03934   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
03935   * @retval None
03936   */
03937 __STATIC_INLINE void LL_RCC_EnableRTC(void)
03938 {
03939   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
03940 }
03941
03942 /**
03943   * @brief  Disable RTC
03944   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
03945   * @retval None
03946   */
03947 __STATIC_INLINE void LL_RCC_DisableRTC(void)
03948 {
03949   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
03950 }
03951
03952 /**
03953   * @brief  Check if RTC has been enabled or not
03954   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
03955   * @retval State of bit (1 or 0).
03956   */
03957 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
03958 {
03959   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
03960 }
03961
03962 /**
03963   * @brief  Force the Backup domain reset
03964   * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
03965   * @retval None
03966   */
03967 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
03968 {
03969   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
03970 }
03971
03972 /**
03973   * @brief  Release the Backup domain reset
03974   * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
03975   * @retval None
03976   */
03977 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
03978 {
03979 #if defined(RCC_BDCR_BDRST)
03980   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
03981 #else
03982   CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
03983 #endif /* RCC_BDCR_BDRST */
03984 }
03985
03986 /**
03987   * @brief  Set HSE Prescalers for RTC Clock
03988   * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
03989   * @param  Prescaler This parameter can be one of the following values:
03990   *         @arg @ref LL_RCC_RTC_NOCLOCK
03991   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
03992   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
03993   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
03994   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
03995   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
03996   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
03997   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
03998   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
03999   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
04000   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
04001   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
04002   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
04003   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
04004   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
04005   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
04006   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
04007   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
04008   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
04009   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
04010   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
04011   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
04012   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
04013   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
04014   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
04015   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
04016   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
04017   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
04018   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
04019   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
04020   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
04021   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
04022   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
04023   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
04024   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
04025   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
04026   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
04027   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
04028   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
04029   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
04030   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
04031   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
04032   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
04033   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
04034   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
04035   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
04036   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
04037   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
04038   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
04039   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
04040   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
04041   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
04042   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
04043   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
04044   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
04045   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
04046   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
04047   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
04048   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
04049   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
04050   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
04051   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
04052   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
04053   * @retval None
04054   */
04055 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
04056 {
04057   MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
04058 }
04059
04060 /**
04061   * @brief  Get HSE Prescalers for RTC Clock
04062   * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
04063   * @retval Returned value can be one of the following values:
04064   *         @arg @ref LL_RCC_RTC_NOCLOCK
04065   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
04066   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
04067   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
04068   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
04069   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
04070   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
04071   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
04072   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
04073   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
04074   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
04075   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
04076   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
04077   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
04078   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
04079   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
04080   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
04081   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
04082   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
04083   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
04084   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
04085   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
04086   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
04087   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
04088   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
04089   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
04090   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
04091   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
04092   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
04093   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
04094   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
04095   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
04096   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
04097   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
04098   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
04099   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
04100   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
04101   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
04102   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
04103   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
04104   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
04105   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
04106   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
04107   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
04108   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
04109   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
04110   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
04111   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
04112   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
04113   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
04114   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
04115   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
04116   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
04117   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
04118   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
04119   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
04120   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
04121   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
04122   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
04123   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
04124   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
04125   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
04126   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
04127   */
04128 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
04129 {
04130   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
04131 }
04132
04133 /**
04134   * @}
04135   */
04136
04137 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
04138   * @{
04139   */
04140
04141 /**
04142   * @brief  Set Timers Clock Prescalers
04143   * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
04144   * @param  Prescaler This parameter can be one of the following values:
04145   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
04146   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
04147   * @retval None
04148   */
04149 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
04150 {
04151   MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
04152 }
04153
04154 /**
04155   * @brief  Get Timers Clock Prescalers
04156   * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
04157   * @retval Returned value can be one of the following values:
04158   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
04159   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
04160   */
04161 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
04162 {
04163   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
04164 }
04165
04166 /**
04167   * @}
04168   */
04169
04170 #if defined(HRTIM1)
04171 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
04172   * @{
04173   */
04174
04175 /**
04176   * @brief  Set High Resolution Timers Clock Source
04177   * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
04178   * @param  Prescaler This parameter can be one of the following values:
04179   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
04180   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
04181   * @retval None
04182   */
04183 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
04184 {
04185   MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
04186 }
04187 #endif /* HRTIM1 */
04188
04189 #if defined(HRTIM1)
04190 /**
04191   * @brief  Get High Resolution Timers Clock Source
04192   * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
04193   * @retval Returned value can be one of the following values:
04194   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
04195   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
04196   */
04197 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
04198 {
04199   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
04200 }
04201 /**
04202   * @}
04203   */
04204 #endif /* HRTIM1 */
04205
04206 /** @defgroup RCC_LL_EF_PLL PLL
04207   * @{
04208   */
04209
04210 /**
04211   * @brief  Set the oscillator used as PLL clock source.
04212   * @note   PLLSRC can be written only when All PLLs are disabled.
04213   * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
04214   * @param  PLLSource parameter can be one of the following values:
04215   *         @arg @ref LL_RCC_PLLSOURCE_HSI
04216   *         @arg @ref LL_RCC_PLLSOURCE_CSI
04217   *         @arg @ref LL_RCC_PLLSOURCE_HSE
04218   *         @arg @ref LL_RCC_PLLSOURCE_NONE
04219   * @retval None
04220   */
04221 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
04222 {
04223   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
04224 }
04225
04226 /**
04227   * @brief  Get the oscillator used as PLL clock source.
04228   * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
04229   * @retval Returned value can be one of the following values:
04230   *         @arg @ref LL_RCC_PLLSOURCE_HSI
04231   *         @arg @ref LL_RCC_PLLSOURCE_CSI
04232   *         @arg @ref LL_RCC_PLLSOURCE_HSE
04233   *         @arg @ref LL_RCC_PLLSOURCE_NONE
04234   */
04235 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
04236 {
04237   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
04238 }
04239
04240 /**
04241   * @brief  Enable PLL1
04242   * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
04243   * @retval None
04244   */
04245 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
04246 {
04247   SET_BIT(RCC->CR, RCC_CR_PLL1ON);
04248 }
04249
04250 /**
04251   * @brief  Disable PLL1
04252   * @note Cannot be disabled if the PLL1 clock is used as the system clock
04253   * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
04254   * @retval None
04255   */
04256 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
04257 {
04258   CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
04259 }
04260
04261 /**
04262   * @brief  Check if PLL1 Ready
04263   * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
04264   * @retval State of bit (1 or 0).
04265   */
04266 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
04267 {
04268   return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
04269 }
04270
04271 /**
04272   * @brief  Enable PLL1P
04273   * @note   This API shall be called only when PLL1 is disabled.
04274   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
04275   * @retval None
04276   */
04277 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
04278 {
04279   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
04280 }
04281
04282 /**
04283   * @brief  Enable PLL1Q
04284   * @note   This API shall be called only when PLL1 is disabled.
04285   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
04286   * @retval None
04287   */
04288 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
04289 {
04290   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
04291 }
04292
04293 /**
04294   * @brief  Enable PLL1R
04295   * @note   This API shall be called only when PLL1 is disabled.
04296   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
04297   * @retval None
04298   */
04299 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
04300 {
04301   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
04302 }
04303
04304 /**
04305   * @brief  Enable PLL1 FRACN
04306   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
04307   * @retval None
04308   */
04309 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
04310 {
04311   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
04312 }
04313
04314 /**
04315   * @brief  Check if PLL1 P is enabled
04316   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
04317   * @retval State of bit (1 or 0).
04318   */
04319 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
04320 {
04321   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
04322 }
04323
04324 /**
04325   * @brief  Check if PLL1 Q is enabled
04326   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
04327   * @retval State of bit (1 or 0).
04328   */
04329 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
04330 {
04331   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
04332 }
04333
04334 /**
04335   * @brief  Check if PLL1 R is enabled
04336   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
04337   * @retval State of bit (1 or 0).
04338   */
04339 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
04340 {
04341   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
04342 }
04343
04344 /**
04345   * @brief  Check if PLL1 FRACN is enabled
04346   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
04347   * @retval State of bit (1 or 0).
04348   */
04349 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
04350 {
04351   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
04352 }
04353
04354 /**
04355   * @brief  Disable PLL1P
04356   * @note   This API shall be called only when PLL1 is disabled.
04357   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
04358   * @retval None
04359   */
04360 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
04361 {
04362   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
04363 }
04364
04365 /**
04366   * @brief  Disable PLL1Q
04367   * @note   This API shall be called only when PLL1 is disabled.
04368   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
04369   * @retval None
04370   */
04371 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
04372 {
04373   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
04374 }
04375
04376 /**
04377   * @brief  Disable PLL1R
04378   * @note   This API shall be called only when PLL1 is disabled.
04379   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
04380   * @retval None
04381   */
04382 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
04383 {
04384   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
04385 }
04386
04387 /**
04388   * @brief  Disable PLL1 FRACN
04389   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
04390   * @retval None
04391   */
04392 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
04393 {
04394   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
04395 }
04396
04397 /**
04398   * @brief  Set PLL1 VCO OutputRange
04399   * @note   This API shall be called only when PLL1 is disabled.
04400   * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
04401   * @param  VCORange This parameter can be one of the following values:
04402   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
04403   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
04404   * @retval None
04405   */
04406 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
04407 {
04408   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
04409 }
04410
04411 /**
04412   * @brief  Set PLL1 VCO Input Range
04413   * @note   This API shall be called only when PLL1 is disabled.
04414   * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
04415   * @param  InputRange This parameter can be one of the following values:
04416   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
04417   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
04418   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
04419   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
04420   * @retval None
04421   */
04422 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
04423 {
04424   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
04425 }
04426
04427 /**
04428   * @brief  Get PLL1 N Coefficient
04429   * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
04430   * @retval A value between 4 and 512
04431   */
04432 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
04433 {
04434   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
04435 }
04436
04437 /**
04438   * @brief  Get PLL1 M Coefficient
04439   * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
04440   * @retval A value between 0 and 63
04441   */
04442 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
04443 {
04444   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
04445 }
04446
04447 /**
04448   * @brief  Get PLL1 P Coefficient
04449   * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
04450   * @retval A value between 2 and 128
04451   */
04452 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
04453 {
04454   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
04455 }
04456
04457 /**
04458   * @brief  Get PLL1 Q Coefficient
04459   * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
04460   * @retval A value between 1 and 128
04461   */
04462 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
04463 {
04464   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
04465 }
04466
04467 /**
04468   * @brief  Get PLL1 R Coefficient
04469   * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
04470   * @retval A value between 1 and 128
04471   */
04472 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
04473 {
04474   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
04475 }
04476
04477 /**
04478   * @brief  Get PLL1 FRACN Coefficient
04479   * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
04480   * @retval A value between 0 and 8191 (0x1FFF)
04481   */
04482 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
04483 {
04484   return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
04485 }
04486
04487 /**
04488   * @brief  Set PLL1 N Coefficient
04489   * @note   This API shall be called only when PLL1 is disabled.
04490   * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
04491   * @param  N parameter can be a value between 4 and 512
04492   */
04493 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
04494 {
04495   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
04496 }
04497
04498 /**
04499   * @brief  Set PLL1 M Coefficient
04500   * @note   This API shall be called only when PLL1 is disabled.
04501   * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
04502   * @param  M parameter can be a value between 0 and 63
04503   */
04504 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
04505 {
04506   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
04507 }
04508
04509 /**
04510   * @brief  Set PLL1 P Coefficient
04511   * @note   This API shall be called only when PLL1 is disabled.
04512   * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
04513   * @param  P parameter can be a value between 2 and 128 (ODD division factor not supportted)
04514   */
04515 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
04516 {
04517   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
04518 }
04519
04520 /**
04521   * @brief  Set PLL1 Q Coefficient
04522   * @note   This API shall be called only when PLL1 is disabled.
04523   * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
04524   * @param  Q parameter can be a value between 1 and 128
04525   */
04526 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
04527 {
04528   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
04529 }
04530
04531 /**
04532   * @brief  Set PLL1 R Coefficient
04533   * @note   This API shall be called only when PLL1 is disabled.
04534   * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
04535   * @param  R parameter can be a value between 1 and 128
04536   */
04537 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
04538 {
04539   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
04540 }
04541
04542 /**
04543   * @brief  Set PLL1 FRACN Coefficient
04544   * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
04545   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
04546   */
04547 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
04548 {
04549   MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
04550 }
04551
04552 /**
04553   * @brief  Enable PLL2
04554   * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
04555   * @retval None
04556   */
04557 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
04558 {
04559   SET_BIT(RCC->CR, RCC_CR_PLL2ON);
04560 }
04561
04562 /**
04563   * @brief  Disable PLL2
04564   * @note Cannot be disabled if the PLL2 clock is used as the system clock
04565   * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
04566   * @retval None
04567   */
04568 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
04569 {
04570   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
04571 }
04572
04573 /**
04574   * @brief  Check if PLL2 Ready
04575   * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
04576   * @retval State of bit (1 or 0).
04577   */
04578 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
04579 {
04580   return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
04581 }
04582
04583 /**
04584   * @brief  Enable PLL2P
04585   * @note   This API shall be called only when PLL2 is disabled.
04586   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
04587   * @retval None
04588   */
04589 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
04590 {
04591   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
04592 }
04593
04594 /**
04595   * @brief  Enable PLL2Q
04596   * @note   This API shall be called only when PLL2 is disabled.
04597   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
04598   * @retval None
04599   */
04600 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
04601 {
04602   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
04603 }
04604
04605 /**
04606   * @brief  Enable PLL2R
04607   * @note   This API shall be called only when PLL2 is disabled.
04608   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
04609   * @retval None
04610   */
04611 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
04612 {
04613   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
04614 }
04615
04616 /**
04617   * @brief  Enable PLL2 FRACN
04618   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
04619   * @retval None
04620   */
04621 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
04622 {
04623   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
04624 }
04625
04626 /**
04627   * @brief  Check if PLL2 P is enabled
04628   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
04629   * @retval State of bit (1 or 0).
04630   */
04631 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
04632 {
04633   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
04634 }
04635
04636 /**
04637   * @brief  Check if PLL2 Q is enabled
04638   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
04639   * @retval State of bit (1 or 0).
04640   */
04641 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
04642 {
04643   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
04644 }
04645
04646 /**
04647   * @brief  Check if PLL2 R is enabled
04648   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
04649   * @retval State of bit (1 or 0).
04650   */
04651 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
04652 {
04653   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
04654 }
04655
04656 /**
04657   * @brief  Check if PLL2 FRACN is enabled
04658   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
04659   * @retval State of bit (1 or 0).
04660   */
04661 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
04662 {
04663   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
04664 }
04665
04666 /**
04667   * @brief  Disable PLL2P
04668   * @note   This API shall be called only when PLL2 is disabled.
04669   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
04670   * @retval None
04671   */
04672 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
04673 {
04674   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
04675 }
04676
04677 /**
04678   * @brief  Disable PLL2Q
04679   * @note   This API shall be called only when PLL2 is disabled.
04680   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
04681   * @retval None
04682   */
04683 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
04684 {
04685   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
04686 }
04687
04688 /**
04689   * @brief  Disable PLL2R
04690   * @note   This API shall be called only when PLL2 is disabled.
04691   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
04692   * @retval None
04693   */
04694 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
04695 {
04696   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
04697 }
04698
04699 /**
04700   * @brief  Disable PLL2 FRACN
04701   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
04702   * @retval None
04703   */
04704 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
04705 {
04706   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
04707 }
04708
04709 /**
04710   * @brief  Set PLL2 VCO OutputRange
04711   * @note   This API shall be called only when PLL2 is disabled.
04712   * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
04713   * @param  VCORange This parameter can be one of the following values:
04714   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
04715   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
04716   * @retval None
04717   */
04718 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
04719 {
04720   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
04721 }
04722
04723 /**
04724   * @brief  Set PLL2 VCO Input Range
04725   * @note   This API shall be called only when PLL2 is disabled.
04726   * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
04727   * @param  InputRange This parameter can be one of the following values:
04728   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
04729   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
04730   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
04731   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
04732   * @retval None
04733   */
04734 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
04735 {
04736   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
04737 }
04738
04739 /**
04740   * @brief  Get PLL2 N Coefficient
04741   * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
04742   * @retval A value between 4 and 512
04743   */
04744 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
04745 {
04746   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
04747 }
04748
04749 /**
04750   * @brief  Get PLL2 M Coefficient
04751   * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
04752   * @retval A value between 0 and 63
04753   */
04754 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
04755 {
04756   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
04757 }
04758
04759 /**
04760   * @brief  Get PLL2 P Coefficient
04761   * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
04762   * @retval A value between 1 and 128
04763   */
04764 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
04765 {
04766   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
04767 }
04768
04769 /**
04770   * @brief  Get PLL2 Q Coefficient
04771   * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
04772   * @retval A value between 1 and 128
04773   */
04774 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
04775 {
04776   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
04777 }
04778
04779 /**
04780   * @brief  Get PLL2 R Coefficient
04781   * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
04782   * @retval A value between 1 and 128
04783   */
04784 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
04785 {
04786   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
04787 }
04788
04789 /**
04790   * @brief  Get PLL2 FRACN Coefficient
04791   * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
04792   * @retval A value between 0 and 8191 (0x1FFF)
04793   */
04794 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
04795 {
04796   return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
04797 }
04798
04799 /**
04800   * @brief  Set PLL2 N Coefficient
04801   * @note   This API shall be called only when PLL2 is disabled.
04802   * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
04803   * @param  N parameter can be a value between 4 and 512
04804   */
04805 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
04806 {
04807   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
04808 }
04809
04810 /**
04811   * @brief  Set PLL2 M Coefficient
04812   * @note   This API shall be called only when PLL2 is disabled.
04813   * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
04814   * @param  M parameter can be a value between 0 and 63
04815   */
04816 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
04817 {
04818   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
04819 }
04820
04821 /**
04822   * @brief  Set PLL2 P Coefficient
04823   * @note   This API shall be called only when PLL2 is disabled.
04824   * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
04825   * @param  P parameter can be a value between 1 and 128
04826   */
04827 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
04828 {
04829   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
04830 }
04831
04832 /**
04833   * @brief  Set PLL2 Q Coefficient
04834   * @note   This API shall be called only when PLL2 is disabled.
04835   * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
04836   * @param  Q parameter can be a value between 1 and 128
04837   */
04838 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
04839 {
04840   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
04841 }
04842
04843 /**
04844   * @brief  Set PLL2 R Coefficient
04845   * @note   This API shall be called only when PLL2 is disabled.
04846   * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
04847   * @param  R parameter can be a value between 1 and 128
04848   */
04849 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
04850 {
04851   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
04852 }
04853
04854 /**
04855   * @brief  Set PLL2 FRACN Coefficient
04856   * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
04857   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
04858   */
04859 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
04860 {
04861   MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
04862 }
04863
04864 /**
04865   * @brief  Enable PLL3
04866   * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
04867   * @retval None
04868   */
04869 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
04870 {
04871   SET_BIT(RCC->CR, RCC_CR_PLL3ON);
04872 }
04873
04874 /**
04875   * @brief  Disable PLL3
04876   * @note Cannot be disabled if the PLL3 clock is used as the system clock
04877   * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
04878   * @retval None
04879   */
04880 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
04881 {
04882   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
04883 }
04884
04885 /**
04886   * @brief  Check if PLL3 Ready
04887   * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
04888   * @retval State of bit (1 or 0).
04889   */
04890 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
04891 {
04892   return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
04893 }
04894
04895 /**
04896   * @brief  Enable PLL3P
04897   * @note   This API shall be called only when PLL3 is disabled.
04898   * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
04899   * @retval None
04900   */
04901 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
04902 {
04903   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
04904 }
04905
04906 /**
04907   * @brief  Enable PLL3Q
04908   * @note   This API shall be called only when PLL3 is disabled.
04909   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
04910   * @retval None
04911   */
04912 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
04913 {
04914   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
04915 }
04916
04917 /**
04918   * @brief  Enable PLL3R
04919   * @note   This API shall be called only when PLL3 is disabled.
04920   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
04921   * @retval None
04922   */
04923 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
04924 {
04925   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
04926 }
04927
04928 /**
04929   * @brief  Enable PLL3 FRACN
04930   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
04931   * @retval None
04932   */
04933 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
04934 {
04935   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
04936 }
04937
04938 /**
04939   * @brief  Check if PLL3 P is enabled
04940   * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
04941   * @retval State of bit (1 or 0).
04942   */
04943 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
04944 {
04945   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
04946 }
04947
04948 /**
04949   * @brief  Check if PLL3 Q is enabled
04950   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
04951   * @retval State of bit (1 or 0).
04952   */
04953 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
04954 {
04955   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
04956 }
04957
04958 /**
04959   * @brief  Check if PLL3 R is enabled
04960   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
04961   * @retval State of bit (1 or 0).
04962   */
04963 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
04964 {
04965   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
04966 }
04967
04968 /**
04969   * @brief  Check if PLL3 FRACN is enabled
04970   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
04971   * @retval State of bit (1 or 0).
04972   */
04973 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
04974 {
04975   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
04976 }
04977
04978 /**
04979   * @brief  Disable PLL3P
04980   * @note   This API shall be called only when PLL3 is disabled.
04981   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
04982   * @retval None
04983   */
04984 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
04985 {
04986   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
04987 }
04988
04989 /**
04990   * @brief  Disable PLL3Q
04991   * @note   This API shall be called only when PLL3 is disabled.
04992   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
04993   * @retval None
04994   */
04995 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
04996 {
04997   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
04998 }
04999
05000 /**
05001   * @brief  Disable PLL3R
05002   * @note   This API shall be called only when PLL3 is disabled.
05003   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
05004   * @retval None
05005   */
05006 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
05007 {
05008   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
05009 }
05010
05011 /**
05012   * @brief  Disable PLL3 FRACN
05013   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
05014   * @retval None
05015   */
05016 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
05017 {
05018   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
05019 }
05020
05021 /**
05022   * @brief  Set PLL3 VCO OutputRange
05023   * @note   This API shall be called only when PLL3 is disabled.
05024   * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
05025   * @param  VCORange This parameter can be one of the following values:
05026   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
05027   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
05028   * @retval None
05029   */
05030 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
05031 {
05032   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
05033 }
05034
05035 /**
05036   * @brief  Set PLL3 VCO Input Range
05037   * @note   This API shall be called only when PLL3 is disabled.
05038   * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
05039   * @param  InputRange This parameter can be one of the following values:
05040   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
05041   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
05042   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
05043   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
05044   * @retval None
05045   */
05046 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
05047 {
05048   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
05049 }
05050
05051 /**
05052   * @brief  Get PLL3 N Coefficient
05053   * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
05054   * @retval A value between 4 and 512
05055   */
05056 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
05057 {
05058   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
05059 }
05060
05061 /**
05062   * @brief  Get PLL3 M Coefficient
05063   * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
05064   * @retval A value between 0 and 63
05065   */
05066 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
05067 {
05068   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
05069 }
05070
05071 /**
05072   * @brief  Get PLL3 P Coefficient
05073   * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
05074   * @retval A value between 1 and 128
05075   */
05076 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
05077 {
05078   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
05079 }
05080
05081 /**
05082   * @brief  Get PLL3 Q Coefficient
05083   * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
05084   * @retval A value between 1 and 128
05085   */
05086 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
05087 {
05088   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
05089 }
05090
05091 /**
05092   * @brief  Get PLL3 R Coefficient
05093   * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
05094   * @retval A value between 1 and 128
05095   */
05096 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
05097 {
05098   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
05099 }
05100
05101 /**
05102   * @brief  Get PLL3 FRACN Coefficient
05103   * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
05104   * @retval A value between 0 and 8191 (0x1FFF)
05105   */
05106 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
05107 {
05108   return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
05109 }
05110
05111 /**
05112   * @brief  Set PLL3 N Coefficient
05113   * @note   This API shall be called only when PLL3 is disabled.
05114   * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
05115   * @param  N parameter can be a value between 4 and 512
05116   */
05117 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
05118 {
05119   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
05120 }
05121
05122 /**
05123   * @brief  Set PLL3 M Coefficient
05124   * @note   This API shall be called only when PLL3 is disabled.
05125   * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
05126   * @param  M parameter can be a value between 0 and 63
05127   */
05128 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
05129 {
05130   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
05131 }
05132
05133 /**
05134   * @brief  Set PLL3 P Coefficient
05135   * @note   This API shall be called only when PLL3 is disabled.
05136   * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
05137   * @param  P parameter can be a value between 1 and 128
05138   */
05139 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
05140 {
05141   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
05142 }
05143
05144 /**
05145   * @brief  Set PLL3 Q Coefficient
05146   * @note   This API shall be called only when PLL3 is disabled.
05147   * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
05148   * @param  Q parameter can be a value between 1 and 128
05149   */
05150 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
05151 {
05152   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
05153 }
05154
05155 /**
05156   * @brief  Set PLL3 R Coefficient
05157   * @note   This API shall be called only when PLL3 is disabled.
05158   * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
05159   * @param  R parameter can be a value between 1 and 128
05160   */
05161 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
05162 {
05163   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
05164 }
05165
05166 /**
05167   * @brief  Set PLL3 FRACN Coefficient
05168   * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
05169   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
05170   */
05171 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
05172 {
05173   MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
05174 }
05175
05176
05177 /**
05178   * @}
05179   */
05180
05181
05182 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
05183   * @{
05184   */
05185
05186 /**
05187   * @brief  Clear LSI ready interrupt flag
05188   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
05189   * @retval None
05190   */
05191 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
05192 {
05193   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
05194 }
05195
05196 /**
05197   * @brief  Clear LSE ready interrupt flag
05198   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
05199   * @retval None
05200   */
05201 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
05202 {
05203   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
05204 }
05205
05206 /**
05207   * @brief  Clear HSI ready interrupt flag
05208   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
05209   * @retval None
05210   */
05211 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
05212 {
05213   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
05214 }
05215
05216 /**
05217   * @brief  Clear HSE ready interrupt flag
05218   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
05219   * @retval None
05220   */
05221 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
05222 {
05223   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
05224 }
05225
05226 /**
05227   * @brief  Clear CSI ready interrupt flag
05228   * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
05229   * @retval None
05230   */
05231 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
05232 {
05233   SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
05234 }
05235
05236 /**
05237   * @brief  Clear HSI48 ready interrupt flag
05238   * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
05239   * @retval None
05240   */
05241 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
05242 {
05243   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
05244 }
05245
05246 /**
05247   * @brief  Clear PLL1 ready interrupt flag
05248   * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
05249   * @retval None
05250   */
05251 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
05252 {
05253   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
05254 }
05255
05256 /**
05257   * @brief  Clear PLL2 ready interrupt flag
05258   * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
05259   * @retval None
05260   */
05261 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
05262 {
05263   SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
05264 }
05265
05266 /**
05267   * @brief  Clear PLL3 ready interrupt flag
05268   * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
05269   * @retval None
05270   */
05271 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
05272 {
05273   SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
05274 }
05275
05276 /**
05277   * @brief  Clear LSE Clock security system interrupt flag
05278   * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
05279   * @retval None
05280   */
05281 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
05282 {
05283   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
05284 }
05285
05286 /**
05287   * @brief  Clear HSE Clock security system interrupt flag
05288   * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
05289   * @retval None
05290   */
05291 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
05292 {
05293   SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
05294 }
05295
05296 /**
05297   * @brief  Check if LSI ready interrupt occurred or not
05298   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
05299   * @retval State of bit (1 or 0).
05300   */
05301 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
05302 {
05303   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
05304 }
05305
05306 /**
05307   * @brief  Check if LSE ready interrupt occurred or not
05308   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
05309   * @retval State of bit (1 or 0).
05310   */
05311 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
05312 {
05313   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
05314 }
05315
05316 /**
05317   * @brief  Check if HSI ready interrupt occurred or not
05318   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
05319   * @retval State of bit (1 or 0).
05320   */
05321 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
05322 {
05323   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
05324 }
05325
05326 /**
05327   * @brief  Check if HSE ready interrupt occurred or not
05328   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
05329   * @retval State of bit (1 or 0).
05330   */
05331 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
05332 {
05333   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
05334 }
05335
05336 /**
05337   * @brief  Check if CSI ready interrupt occurred or not
05338   * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
05339   * @retval State of bit (1 or 0).
05340   */
05341 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
05342 {
05343   return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
05344 }
05345
05346 /**
05347   * @brief  Check if HSI48 ready interrupt occurred or not
05348   * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
05349   * @retval State of bit (1 or 0).
05350   */
05351 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
05352 {
05353   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
05354 }
05355
05356 /**
05357   * @brief  Check if PLL1 ready interrupt occurred or not
05358   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
05359   * @retval State of bit (1 or 0).
05360   */
05361 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
05362 {
05363   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
05364 }
05365
05366 /**
05367   * @brief  Check if PLL2 ready interrupt occurred or not
05368   * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
05369   * @retval State of bit (1 or 0).
05370   */
05371 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
05372 {
05373   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
05374 }
05375
05376 /**
05377   * @brief  Check if PLL3 ready interrupt occurred or not
05378   * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
05379   * @retval State of bit (1 or 0).
05380   */
05381 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
05382 {
05383   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
05384 }
05385
05386 /**
05387   * @brief  Check if LSE Clock security system interrupt occurred or not
05388   * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
05389   * @retval State of bit (1 or 0).
05390   */
05391 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
05392 {
05393   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
05394 }
05395
05396 /**
05397   * @brief  Check if HSE Clock security system interrupt occurred or not
05398   * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
05399   * @retval State of bit (1 or 0).
05400   */
05401 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
05402 {
05403   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
05404 }
05405
05406 /**
05407   * @brief  Check if RCC flag Low Power D1 reset is set or not.
05408   * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
05409   *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
05410   *
05411   * (*) Only available for single core devices
05412   * (**) Only available for Dual core devices
05413   * @retval State of bit (1 or 0).
05414   */
05415 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
05416 {
05417 #if defined(DUAL_CORE)
05418   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
05419 #else
05420   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
05421 #endif /*DUAL_CORE*/
05422 }
05423
05424 #if defined(DUAL_CORE)
05425 /**
05426   * @brief  Check if RCC flag Low Power D2 reset is set or not.
05427   * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
05428   * @retval State of bit (1 or 0).
05429   */
05430 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
05431 {
05432   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
05433 }
05434 #endif  /*DUAL_CORE*/
05435
05436 /**
05437   * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
05438   * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
05439   * @retval State of bit (1 or 0).
05440   */
05441 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
05442 {
05443   return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
05444 }
05445
05446 #if defined(DUAL_CORE)
05447 /**
05448   * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
05449   * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
05450   * @retval State of bit (1 or 0).
05451   */
05452 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
05453 {
05454   return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
05455 }
05456 #endif  /*DUAL_CORE*/
05457
05458 /**
05459   * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
05460   * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
05461   * @retval State of bit (1 or 0).
05462   */
05463 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
05464 {
05465   return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
05466 }
05467
05468 #if defined(DUAL_CORE)
05469 /**
05470   * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
05471   * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
05472   * @retval State of bit (1 or 0).
05473   */
05474 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
05475 {
05476   return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
05477 }
05478 #endif  /*DUAL_CORE*/
05479
05480 /**
05481   * @brief  Check if RCC flag Software reset is set or not.
05482   * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
05483   *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
05484   *
05485   * (*) Only available for single core devices
05486   * (**) Only available for Dual core devices
05487   * @retval State of bit (1 or 0).
05488   */
05489 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
05490 {
05491 #if defined(DUAL_CORE)
05492   return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
05493 #else
05494   return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
05495 #endif  /*DUAL_CORE*/
05496 }
05497
05498 #if defined(DUAL_CORE)
05499 /**
05500   * @brief  Check if RCC flag Software reset is set or not.
05501   * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
05502   * @retval State of bit (1 or 0).
05503   */
05504 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
05505 {
05506   return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
05507 }
05508 #endif  /*DUAL_CORE*/
05509
05510 /**
05511   * @brief  Check if RCC flag POR/PDR reset is set or not.
05512   * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
05513   * @retval State of bit (1 or 0).
05514   */
05515 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
05516 {
05517   return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
05518 }
05519
05520 /**
05521   * @brief  Check if RCC flag Pin reset is set or not.
05522   * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
05523   * @retval State of bit (1 or 0).
05524   */
05525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
05526 {
05527   return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
05528 }
05529
05530 /**
05531   * @brief  Check if RCC flag BOR reset is set or not.
05532   * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
05533   * @retval State of bit (1 or 0).
05534   */
05535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
05536 {
05537   return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
05538 }
05539
05540 #if defined(RCC_RSR_D1RSTF)
05541 /**
05542   * @brief  Check if RCC flag D1 reset is set or not.
05543   * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
05544   * @retval State of bit (1 or 0).
05545   */
05546 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
05547 {
05548   return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
05549 }
05550 #endif /* RCC_RSR_D1RSTF */
05551
05552 #if defined(RCC_RSR_CDRSTF)
05553 /**
05554   * @brief  Check if RCC flag CD reset is set or not.
05555   * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
05556   * @retval State of bit (1 or 0).
05557   */
05558 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
05559 {
05560   return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
05561 }
05562 #endif /* RCC_RSR_CDRSTF */
05563
05564 #if defined(RCC_RSR_D2RSTF)
05565 /**
05566   * @brief  Check if RCC flag D2 reset is set or not.
05567   * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
05568   * @retval State of bit (1 or 0).
05569   */
05570 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
05571 {
05572   return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
05573 }
05574 #endif /* RCC_RSR_D2RSTF */
05575
05576 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
05577 /**
05578   * @brief  Check if RCC flag CPU reset is set or not.
05579   * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
05580   *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
05581   *
05582   * (*) Only available for single core devices
05583   * (**) Only available for Dual core devices
05584   * @retval State of bit (1 or 0).
05585   */
05586 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
05587 {
05588 #if defined(DUAL_CORE)
05589   return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
05590 #else
05591   return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
05592 #endif/*DUAL_CORE*/
05593 }
05594 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
05595
05596 #if defined(DUAL_CORE)
05597 /**
05598   * @brief  Check if RCC flag CPU2 reset is set or not.
05599   * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
05600   * @retval State of bit (1 or 0).
05601   */
05602 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
05603 {
05604   return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
05605 }
05606 #endif  /*DUAL_CORE*/
05607
05608 /**
05609   * @brief  Set RMVF bit to clear all reset flags.
05610   * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
05611   * @retval None
05612   */
05613 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
05614 {
05615   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
05616 }
05617
05618 #if defined(DUAL_CORE)
05619 /**
05620   * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
05621   * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
05622   * @retval State of bit (1 or 0).
05623   */
05624 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
05625 {
05626   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
05627 }
05628
05629 /**
05630   * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
05631   * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
05632   * @retval State of bit (1 or 0).
05633   */
05634 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
05635 {
05636   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
05637 }
05638
05639 /**
05640   * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
05641   * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
05642   * @retval State of bit (1 or 0).
05643   */
05644 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
05645 {
05646   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
05647 }
05648
05649 /**
05650   * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
05651   * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
05652   * @retval State of bit (1 or 0).
05653   */
05654 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
05655 {
05656   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
05657 }
05658
05659 /**
05660   * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
05661   * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
05662   * @retval State of bit (1 or 0).
05663   */
05664 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
05665 {
05666   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
05667 }
05668
05669 /**
05670   * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
05671   * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
05672   * @retval State of bit (1 or 0).
05673   */
05674 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
05675 {
05676   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
05677 }
05678
05679 /**
05680   * @brief  Check if RCC_C1 flag Software reset is set or not.
05681   * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
05682   * @retval State of bit (1 or 0).
05683   */
05684 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
05685 {
05686   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
05687 }
05688
05689 /**
05690   * @brief  Check if RCC_C1 flag Software reset is set or not.
05691   * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
05692   * @retval State of bit (1 or 0).
05693   */
05694 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
05695 {
05696   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
05697 }
05698
05699 /**
05700   * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
05701   * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
05702   * @retval State of bit (1 or 0).
05703   */
05704 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
05705 {
05706   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
05707 }
05708
05709 /**
05710   * @brief  Check if RCC_C1 flag Pin reset is set or not.
05711   * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
05712   * @retval State of bit (1 or 0).
05713   */
05714 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
05715 {
05716   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
05717 }
05718
05719 /**
05720   * @brief  Check if RCC_C1 flag BOR reset is set or not.
05721   * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
05722   * @retval State of bit (1 or 0).
05723   */
05724 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
05725 {
05726   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
05727 }
05728
05729 /**
05730   * @brief  Check if RCC_C1 flag D1 reset is set or not.
05731   * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
05732   * @retval State of bit (1 or 0).
05733   */
05734 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
05735 {
05736   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
05737 }
05738
05739 /**
05740   * @brief  Check if RCC_C1 flag D2 reset is set or not.
05741   * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
05742   * @retval State of bit (1 or 0).
05743   */
05744 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
05745 {
05746   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
05747 }
05748
05749 /**
05750   * @brief  Check if RCC_C1 flag CPU reset is set or not.
05751   * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
05752   * @retval State of bit (1 or 0).
05753   */
05754 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
05755 {
05756   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
05757 }
05758
05759 /**
05760   * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
05761   * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
05762   * @retval State of bit (1 or 0).
05763   */
05764 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
05765 {
05766   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
05767 }
05768
05769 /**
05770   * @brief  Set RMVF bit to clear the reset flags.
05771   * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
05772   * @retval None
05773   */
05774 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
05775 {
05776   SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
05777 }
05778
05779 /**
05780   * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
05781   * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
05782   * @retval State of bit (1 or 0).
05783   */
05784 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
05785 {
05786   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
05787 }
05788
05789 /**
05790   * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
05791   * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
05792   * @retval State of bit (1 or 0).
05793   */
05794 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
05795 {
05796   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
05797 }
05798
05799 /**
05800   * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
05801   * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
05802   * @retval State of bit (1 or 0).
05803   */
05804 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
05805 {
05806   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
05807 }
05808
05809 /**
05810   * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
05811   * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
05812   * @retval State of bit (1 or 0).
05813   */
05814 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
05815 {
05816   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
05817 }
05818
05819 /**
05820   * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
05821   * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
05822   * @retval State of bit (1 or 0).
05823   */
05824 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
05825 {
05826   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
05827 }
05828
05829 /**
05830   * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
05831   * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
05832   * @retval State of bit (1 or 0).
05833   */
05834 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
05835 {
05836   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
05837 }
05838
05839 /**
05840   * @brief  Check if RCC_C2 flag Software reset is set or not.
05841   * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
05842   * @retval State of bit (1 or 0).
05843   */
05844 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
05845 {
05846   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
05847 }
05848
05849 /**
05850   * @brief  Check if RCC_C2 flag Software reset is set or not.
05851   * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
05852   * @retval State of bit (1 or 0).
05853   */
05854 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
05855 {
05856   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
05857 }
05858
05859 /**
05860   * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
05861   * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
05862   * @retval State of bit (1 or 0).
05863   */
05864 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
05865 {
05866   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
05867 }
05868
05869 /**
05870   * @brief  Check if RCC_C2 flag Pin reset is set or not.
05871   * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
05872   * @retval State of bit (1 or 0).
05873   */
05874 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
05875 {
05876   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
05877 }
05878
05879 /**
05880   * @brief  Check if RCC_C2 flag BOR reset is set or not.
05881   * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
05882   * @retval State of bit (1 or 0).
05883   */
05884 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
05885 {
05886   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
05887 }
05888
05889 /**
05890   * @brief  Check if RCC_C2 flag D1 reset is set or not.
05891   * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
05892   * @retval State of bit (1 or 0).
05893   */
05894 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
05895 {
05896   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
05897 }
05898
05899 /**
05900   * @brief  Check if RCC_C2 flag D2 reset is set or not.
05901   * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
05902   * @retval State of bit (1 or 0).
05903   */
05904 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
05905 {
05906   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
05907 }
05908
05909 /**
05910   * @brief  Check if RCC_C2 flag CPU reset is set or not.
05911   * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
05912   * @retval State of bit (1 or 0).
05913   */
05914 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
05915 {
05916   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
05917 }
05918
05919 /**
05920   * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
05921   * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
05922   * @retval State of bit (1 or 0).
05923   */
05924 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
05925 {
05926   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
05927 }
05928
05929 /**
05930   * @brief  Set RMVF bit to clear the reset flags.
05931   * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
05932   * @retval None
05933   */
05934 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
05935 {
05936   SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
05937 }
05938 #endif /*DUAL_CORE*/
05939
05940 /**
05941   * @}
05942   */
05943
05944 /** @defgroup RCC_LL_EF_IT_Management IT Management
05945   * @{
05946   */
05947
05948 /**
05949   * @brief  Enable LSI ready interrupt
05950   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
05951   * @retval None
05952   */
05953 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
05954 {
05955   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
05956 }
05957
05958 /**
05959   * @brief  Enable LSE ready interrupt
05960   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
05961   * @retval None
05962   */
05963 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
05964 {
05965   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
05966 }
05967
05968 /**
05969   * @brief  Enable HSI ready interrupt
05970   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
05971   * @retval None
05972   */
05973 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
05974 {
05975   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
05976 }
05977
05978 /**
05979   * @brief  Enable HSE ready interrupt
05980   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
05981   * @retval None
05982   */
05983 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
05984 {
05985   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
05986 }
05987
05988 /**
05989   * @brief  Enable CSI ready interrupt
05990   * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
05991   * @retval None
05992   */
05993 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
05994 {
05995   SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
05996 }
05997
05998 /**
05999   * @brief  Enable HSI48 ready interrupt
06000   * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
06001   * @retval None
06002   */
06003 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
06004 {
06005   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
06006 }
06007
06008 /**
06009   * @brief  Enable PLL1 ready interrupt
06010   * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
06011   * @retval None
06012   */
06013 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
06014 {
06015   SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
06016 }
06017
06018 /**
06019   * @brief  Enable PLL2 ready interrupt
06020   * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
06021   * @retval None
06022   */
06023 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
06024 {
06025   SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
06026 }
06027
06028 /**
06029   * @brief  Enable PLL3 ready interrupt
06030   * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
06031   * @retval None
06032   */
06033 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
06034 {
06035   SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
06036 }
06037
06038 /**
06039   * @brief  Enable LSECSS interrupt
06040   * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
06041   * @retval None
06042   */
06043 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
06044 {
06045   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
06046 }
06047
06048 /**
06049   * @brief  Disable LSI ready interrupt
06050   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
06051   * @retval None
06052   */
06053 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
06054 {
06055   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
06056 }
06057
06058 /**
06059   * @brief  Disable LSE ready interrupt
06060   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
06061   * @retval None
06062   */
06063 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
06064 {
06065   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
06066 }
06067
06068 /**
06069   * @brief  Disable HSI ready interrupt
06070   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
06071   * @retval None
06072   */
06073 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
06074 {
06075   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
06076 }
06077
06078 /**
06079   * @brief  Disable HSE ready interrupt
06080   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
06081   * @retval None
06082   */
06083 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
06084 {
06085   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
06086 }
06087
06088 /**
06089   * @brief  Disable CSI ready interrupt
06090   * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
06091   * @retval None
06092   */
06093 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
06094 {
06095   CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
06096 }
06097
06098 /**
06099   * @brief  Disable HSI48 ready interrupt
06100   * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
06101   * @retval None
06102   */
06103 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
06104 {
06105   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
06106 }
06107
06108 /**
06109   * @brief  Disable PLL1 ready interrupt
06110   * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
06111   * @retval None
06112   */
06113 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
06114 {
06115   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
06116 }
06117
06118 /**
06119   * @brief  Disable PLL2 ready interrupt
06120   * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
06121   * @retval None
06122   */
06123 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
06124 {
06125   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
06126 }
06127
06128 /**
06129   * @brief  Disable PLL3 ready interrupt
06130   * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
06131   * @retval None
06132   */
06133 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
06134 {
06135   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
06136 }
06137
06138 /**
06139   * @brief  Disable LSECSS interrupt
06140   * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
06141   * @retval None
06142   */
06143 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
06144 {
06145   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
06146 }
06147
06148 /**
06149   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
06150   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
06151   * @retval State of bit (1 or 0).
06152   */
06153 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
06154 {
06155   return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
06156 }
06157
06158 /**
06159   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
06160   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
06161   * @retval State of bit (1 or 0).
06162   */
06163 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
06164 {
06165   return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
06166 }
06167
06168 /**
06169   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
06170   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
06171   * @retval State of bit (1 or 0).
06172   */
06173 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
06174 {
06175   return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
06176 }
06177
06178 /**
06179   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
06180   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
06181   * @retval State of bit (1 or 0).
06182   */
06183 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
06184 {
06185   return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
06186 }
06187
06188 /**
06189   * @brief  Checks if CSI ready interrupt source is enabled or disabled.
06190   * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
06191   * @retval State of bit (1 or 0).
06192   */
06193 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
06194 {
06195   return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
06196 }
06197
06198 /**
06199   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
06200   * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
06201   * @retval State of bit (1 or 0).
06202   */
06203 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
06204 {
06205   return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
06206 }
06207
06208 /**
06209   * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
06210   * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
06211   * @retval State of bit (1 or 0).
06212   */
06213 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
06214 {
06215   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
06216 }
06217
06218 /**
06219   * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
06220   * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
06221   * @retval State of bit (1 or 0).
06222   */
06223 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
06224 {
06225   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
06226 }
06227
06228 /**
06229   * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
06230   * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
06231   * @retval State of bit (1 or 0).
06232   */
06233 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
06234 {
06235   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
06236 }
06237
06238 /**
06239   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
06240   * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
06241   * @retval State of bit (1 or 0).
06242   */
06243 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
06244 {
06245   return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
06246 }
06247 /**
06248   * @}
06249   */
06250
06251 #if defined(USE_FULL_LL_DRIVER)
06252 /** @defgroup RCC_LL_EF_Init De-initialization function
06253   * @{
06254   */
06255 void LL_RCC_DeInit(void);
06256 /**
06257   * @}
06258   */
06259
06260 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
06261   * @{
06262   */
06263 uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
06264
06265 void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
06266 void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
06267 void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
06268 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
06269
06270 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
06271 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
06272 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
06273 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
06274 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
06275 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
06276 uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
06277 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
06278 uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
06279 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
06280 uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
06281 #if defined(DFSDM2_BASE)
06282 uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
06283 #endif /* DFSDM2 */
06284 #if defined(DSI)
06285 uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
06286 #endif /* DSI */
06287 uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
06288 uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
06289 uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
06290 uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
06291 uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
06292 #if defined(QUADSPI)
06293 uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
06294 #endif /* QUADSPI */
06295 #if defined(OCTOSPI1) || defined(OCTOSPI2)
06296 uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
06297 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
06298 uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
06299
06300
06301 /**
06302   * @}
06303   */
06304 #endif /* USE_FULL_LL_DRIVER */
06305
06306 /**
06307   * @}
06308   */
06309
06310
06311 /**
06312   * @}
06313   */
06314 #endif /* defined(RCC) */
06315
06316 /**
06317   * @}
06318   */
06319
06320 #ifdef __cplusplus
06321 }
06322 #endif
06323
06324 #endif /* STM32H7xx_LL_RCC_H */
06325
06326 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rng.c Source File

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stm32h7xx_ll_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_rng.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @addtogroup RNG_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup RNG_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
00049                                  ((__MODE__) == LL_RNG_CED_DISABLE))
00050
00051 #if defined(RNG_CR_CONDRST)
00052 #define IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu)
00053
00054
00055 #define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
00056                                                      ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
00057
00058 #define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
00059
00060 #define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
00061
00062 #define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
00063 #endif /* RNG_CR_CONDRST*/
00064 /**
00065   * @}
00066   */
00067 /* Private function prototypes -----------------------------------------------*/
00068
00069 /* Exported functions --------------------------------------------------------*/
00070 /** @addtogroup RNG_LL_Exported_Functions
00071   * @{
00072   */
00073
00074 /** @addtogroup RNG_LL_EF_Init
00075   * @{
00076   */
00077
00078 /**
00079   * @brief  De-initialize RNG registers (Registers restored to their default values).
00080   * @param  RNGx RNG Instance
00081   * @retval An ErrorStatus enumeration value:
00082   *          - SUCCESS: RNG registers are de-initialized
00083   *          - ERROR: not applicable
00084   */
00085 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
00086 {
00087   /* Check the parameters */
00088   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00089   /* Enable RNG reset state */
00090   LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
00091
00092   /* Release RNG from reset state */
00093   LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
00094   return (SUCCESS);
00095 }
00096
00097 /**
00098   * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
00099   * @param  RNGx RNG Instance
00100   * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
00101   *         that contains the configuration information for the specified RNG peripheral.
00102   * @retval An ErrorStatus enumeration value:
00103   *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
00104   *          - ERROR: not applicable
00105   */
00106 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
00107 {
00108   /* Check the parameters */
00109   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00110   assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
00111
00112 #if defined(RNG_CR_CONDRST)
00113   /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
00114   MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_InitStruct->ClockErrorDetection | RNG_CR_CONDRST);
00115   /* Writing bits CONDRST=0*/
00116   CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
00117 #else
00118   /* Clock Error Detection configuration */
00119   MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
00120 #endif /* RNG_CR_CONDRST */
00121
00122   return (SUCCESS);
00123 }
00124
00125 /**
00126   * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
00127   * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
00128   *                       whose fields will be set to default values.
00129   * @retval None
00130   */
00131 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
00132 {
00133   /* Set RNG_InitStruct fields to default values */
00134   RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
00135
00136 }
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 #endif /* RNG */
00150
00151 /**
00152   * @}
00153   */
00154
00155 #endif /* USE_FULL_LL_DRIVER */
00156
00157 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00158
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rng.h Source File

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stm32h7xx_ll_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_RNG_H
00022 #define STM32H7xx_LL_RNG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @defgroup RNG_LL RNG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 #if defined(USE_FULL_LL_DRIVER)
00048 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
00049   * @{
00050   */
00051
00052
00053 /**
00054   * @brief LL RNG Init Structure Definition
00055   */
00056 typedef struct
00057 {
00058   uint32_t         ClockErrorDetection; /*!< Clock error detection.
00059                                       This parameter can be one value of @ref RNG_LL_CED.
00060
00061                                       This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
00062 } LL_RNG_InitTypeDef;
00063
00064 /**
00065   * @}
00066   */
00067 #endif /* USE_FULL_LL_DRIVER */
00068 /* Exported constants --------------------------------------------------------*/
00069 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
00070   * @{
00071   */
00072
00073 /** @defgroup RNG_LL_CED Clock Error Detection
00074   * @{
00075   */
00076 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
00077 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
00078 /**
00079   * @}
00080   */
00081
00082 #if defined(RNG_CR_CONDRST)
00083 /** @defgroup RNG_LL_Clock_Divider_Factor  Value used to configure an internal
00084  *            programmable divider acting on the incoming RNG clock
00085   * @{
00086   */
00087 #define LL_RNG_CLKDIV_BY_1       (0x00000000UL)                                                           /*!< No clock division                             */
00088 #define LL_RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)                                                        /*!< 2 RNG clock cycles per internal RNG clock     */
00089 #define LL_RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)                                                        /*!< 4 RNG clock cycles per internal RNG clock     */
00090 #define LL_RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                                      /*!< 8 RNG clock cycles per internal RNG clock     */
00091 #define LL_RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)                                                        /*!< 16 RNG clock cycles per internal RNG clock    */
00092 #define LL_RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                                      /*!< 32 RNG clock cycles per internal RNG clock    */
00093 #define LL_RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                                      /*!< 64 RNG clock cycles per internal RNG clock    */
00094 #define LL_RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 128 RNG clock cycles per internal RNG clock   */
00095 #define LL_RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)                                                        /*!< 256 RNG clock cycles per internal RNG clock   */
00096 #define LL_RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)                                      /*!< 512 RNG clock cycles per internal RNG clock   */
00097 #define LL_RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)                                      /*!< 1024 RNG clock cycles per internal RNG clock  */
00098 #define LL_RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 2048 RNG clock cycles per internal RNG clock  */
00099 #define LL_RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)                                      /*!< 4096 RNG clock cycles per internal RNG clock  */
00100 #define LL_RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                    /*!< 8192 RNG clock cycles per internal RNG clock  */
00101 #define LL_RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                    /*!< 16384 RNG clock cycles per internal RNG clock */
00102 #define LL_RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)  /*!< 32768 RNG clock cycles per internal RNG clock */
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup RNG_LL_NIST_Compliance  NIST Compliance configuration
00108   * @{
00109   */
00110 #define LL_RNG_NIST_COMPLIANT     (0x00000000UL) /*!< Default NIST compliant configuration*/
00111 #define LL_RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
00112
00113 /**
00114   * @}
00115   */
00116
00117 #endif/*RNG_CR_CONDRST*/
00118 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
00119   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
00120   * @{
00121   */
00122 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
00123 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
00124 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
00125 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
00126 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup RNG_LL_EC_IT IT Defines
00132   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
00133   * @{
00134   */
00135 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
00136 /**
00137   * @}
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Exported macro ------------------------------------------------------------*/
00145 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
00146   * @{
00147   */
00148
00149 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
00150   * @{
00151   */
00152
00153 /**
00154   * @brief  Write a value in RNG register
00155   * @param  __INSTANCE__ RNG Instance
00156   * @param  __REG__ Register to be written
00157   * @param  __VALUE__ Value to be written in the register
00158   * @retval None
00159   */
00160 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00161
00162 /**
00163   * @brief  Read a value in RNG register
00164   * @param  __INSTANCE__ RNG Instance
00165   * @param  __REG__ Register to be read
00166   * @retval Register value
00167   */
00168 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177
00178 /* Exported functions --------------------------------------------------------*/
00179 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
00180   * @{
00181   */
00182 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Enable Random Number Generation
00188   * @rmtoll CR           RNGEN         LL_RNG_Enable
00189   * @param  RNGx RNG Instance
00190   * @retval None
00191   */
00192 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
00193 {
00194   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
00195 }
00196
00197 /**
00198   * @brief  Disable Random Number Generation
00199   * @rmtoll CR           RNGEN         LL_RNG_Disable
00200   * @param  RNGx RNG Instance
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
00204 {
00205   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
00206 }
00207
00208 /**
00209   * @brief  Check if Random Number Generator is enabled
00210   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
00211   * @param  RNGx RNG Instance
00212   * @retval State of bit (1 or 0).
00213   */
00214 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
00215 {
00216   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
00217 }
00218
00219 /**
00220   * @brief  Enable Clock Error Detection
00221   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
00222   * @param  RNGx RNG Instance
00223   * @retval None
00224   */
00225 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
00226 {
00227   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
00228 }
00229
00230 /**
00231   * @brief  Disable RNG Clock Error Detection
00232   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
00233   * @param  RNGx RNG Instance
00234   * @retval None
00235   */
00236 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
00237 {
00238   SET_BIT(RNGx->CR, RNG_CR_CED);
00239 }
00240
00241 /**
00242   * @brief  Check if RNG Clock Error Detection is enabled
00243   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
00244   * @param  RNGx RNG Instance
00245   * @retval State of bit (1 or 0).
00246   */
00247 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
00248 {
00249   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
00250 }
00251
00252 #if defined(RNG_CR_CONDRST)
00253 /**
00254   * @brief  Set RNG Conditioning Soft Reset bit
00255   * @rmtoll CR           CONDRST          LL_RNG_EnableCondReset
00256   * @param  RNGx RNG Instance
00257   * @retval None
00258   */
00259 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
00260 {
00261   SET_BIT(RNGx->CR, RNG_CR_CONDRST);
00262 }
00263
00264 /**
00265   * @brief  Reset RNG  Conditioning Soft Reset bit
00266   * @rmtoll CR           CONDRST         LL_RNG_DisableCondReset
00267   * @param  RNGx RNG Instance
00268   * @retval None
00269   */
00270 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
00271 {
00272   CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
00273 }
00274
00275 /**
00276   * @brief  Check if RNG Conditioning Soft Reset bit is set
00277   * @rmtoll CR           CONDRST         LL_RNG_IsEnabledCondReset
00278   * @param  RNGx RNG Instance
00279   * @retval State of bit (1 or 0).
00280   */
00281 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
00282 {
00283   return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
00284 }
00285
00286 /**
00287   * @brief  Enable RNG Config Lock
00288   * @rmtoll CR           CONFIGLOCK          LL_RNG_ConfigLock
00289   * @param  RNGx RNG Instance
00290   * @retval None
00291   */
00292 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
00293 {
00294   SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
00295 }
00296
00297 /**
00298   * @brief  Check if RNG Config Lock is enabled
00299   * @rmtoll CR           CONFIGLOCK         LL_RNG_IsConfigLocked
00300   * @param  RNGx RNG Instance
00301   * @retval State of bit (1 or 0).
00302   */
00303 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
00304 {
00305   return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
00306 }
00307
00308 /**
00309   * @brief  Enable NIST Compliance
00310   * @rmtoll CR           NISTC         LL_RNG_EnableNistCompliance
00311   * @param  RNGx RNG Instance
00312   * @retval None
00313   */
00314 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
00315 {
00316   CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
00317 }
00318
00319 /**
00320   * @brief  Disable NIST Compliance
00321   * @rmtoll CR           NISTC         LL_RNG_DisableNistCompliance
00322   * @param  RNGx RNG Instance
00323   * @retval None
00324   */
00325 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
00326 {
00327   SET_BIT(RNGx->CR, RNG_CR_NISTC);
00328 }
00329
00330 /**
00331   * @brief  Check if NIST Compliance is enabled
00332   * @rmtoll CR           NISTC         LL_RNG_IsEnabledNistCompliance
00333   * @param  RNGx RNG Instance
00334   * @retval State of bit (1 or 0).
00335   */
00336 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
00337 {
00338   return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
00339 }
00340
00341 /**
00342   * @brief  Set RNG  Config1 Configuration field value
00343   * @rmtoll CR           RNG_CONFIG1         LL_RNG_SetConfig1
00344   * @param  RNGx RNG Instance
00345   * @param  Config1 Value between 0 and 0x3F
00346   * @retval None
00347   */
00348 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
00349 {
00350   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
00351 }
00352
00353 /**
00354   * @brief  Get RNG  Config1 Configuration field value
00355   * @rmtoll CR           RNG_CONFIG1         LL_RNG_GetConfig1
00356   * @param  RNGx RNG Instance
00357   * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
00358   */
00359 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
00360 {
00361   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
00362 }
00363
00364 /**
00365   * @brief  Set RNG  Config2 Configuration field value
00366   * @rmtoll CR           RNG_CONFIG2         LL_RNG_SetConfig2
00367   * @param  RNGx RNG Instance
00368   * @param  Config2 Value between 0 and 0x7
00369   * @retval None
00370   */
00371 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
00372 {
00373   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
00374 }
00375
00376 /**
00377   * @brief  Get RNG  Config2 Configuration field value
00378   * @rmtoll CR           RNG_CONFIG2         LL_RNG_GetConfig2
00379   * @param  RNGx RNG Instance
00380   * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
00381   */
00382 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
00383 {
00384   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
00385 }
00386
00387 /**
00388   * @brief  Set RNG  Config3 Configuration field value
00389   * @rmtoll CR           RNG_CONFIG3         LL_RNG_SetConfig3
00390   * @param  RNGx RNG Instance
00391   * @param  Config3 Value between 0 and 0xF
00392   * @retval None
00393   */
00394 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
00395 {
00396   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
00397 }
00398
00399 /**
00400   * @brief  Get RNG  Config3 Configuration field value
00401   * @rmtoll CR           RNG_CONFIG3         LL_RNG_GetConfig3
00402   * @param  RNGx RNG Instance
00403   * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
00404   */
00405 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
00406 {
00407   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
00408 }
00409
00410 /**
00411   * @brief  Set RNG  Clock divider factor
00412   * @rmtoll CR           CLKDIV         LL_RNG_SetClockDivider
00413   * @param  RNGx RNG Instance
00414   * @param  Divider can be one of the following values:
00415   *         @arg @ref LL_RNG_CLKDIV_BY_1
00416   *         @arg @ref LL_RNG_CLKDIV_BY_2
00417   *         @arg @ref LL_RNG_CLKDIV_BY_4
00418   *         @arg @ref LL_RNG_CLKDIV_BY_8
00419   *         @arg @ref LL_RNG_CLKDIV_BY_16
00420   *         @arg @ref LL_RNG_CLKDIV_BY_32
00421   *         @arg @ref LL_RNG_CLKDIV_BY_64
00422   *         @arg @ref LL_RNG_CLKDIV_BY_128
00423   *         @arg @ref LL_RNG_CLKDIV_BY_256
00424   *         @arg @ref LL_RNG_CLKDIV_BY_512
00425   *         @arg @ref LL_RNG_CLKDIV_BY_1024
00426   *         @arg @ref LL_RNG_CLKDIV_BY_2048
00427   *         @arg @ref LL_RNG_CLKDIV_BY_4096
00428   *         @arg @ref LL_RNG_CLKDIV_BY_8192
00429   *         @arg @ref LL_RNG_CLKDIV_BY_16384
00430   *         @arg @ref LL_RNG_CLKDIV_BY_32768
00431   * @retval None
00432   */
00433 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
00434 {
00435   MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
00436 }
00437
00438 /**
00439   * @brief  Get RNG  Clock divider factor
00440   * @rmtoll CR           CLKDIV         LL_RNG_GetClockDivider
00441   * @param  RNGx RNG Instance
00442   * @retval Returned value can be one of the following values:
00443   *         @arg @ref LL_RNG_CLKDIV_BY_1
00444   *         @arg @ref LL_RNG_CLKDIV_BY_2
00445   *         @arg @ref LL_RNG_CLKDIV_BY_4
00446   *         @arg @ref LL_RNG_CLKDIV_BY_8
00447   *         @arg @ref LL_RNG_CLKDIV_BY_16
00448   *         @arg @ref LL_RNG_CLKDIV_BY_32
00449   *         @arg @ref LL_RNG_CLKDIV_BY_64
00450   *         @arg @ref LL_RNG_CLKDIV_BY_128
00451   *         @arg @ref LL_RNG_CLKDIV_BY_256
00452   *         @arg @ref LL_RNG_CLKDIV_BY_512
00453   *         @arg @ref LL_RNG_CLKDIV_BY_1024
00454   *         @arg @ref LL_RNG_CLKDIV_BY_2048
00455   *         @arg @ref LL_RNG_CLKDIV_BY_4096
00456   *         @arg @ref LL_RNG_CLKDIV_BY_8192
00457   *         @arg @ref LL_RNG_CLKDIV_BY_16384
00458   *         @arg @ref LL_RNG_CLKDIV_BY_32768
00459   */
00460 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
00461 {
00462   return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
00463 }
00464 #endif /* RNG_CR_CONDRST */
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
00470   * @{
00471   */
00472
00473 /**
00474   * @brief  Indicate if the RNG Data ready Flag is set or not
00475   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
00476   * @param  RNGx RNG Instance
00477   * @retval State of bit (1 or 0).
00478   */
00479 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
00480 {
00481   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
00482 }
00483
00484 /**
00485   * @brief  Indicate if the Clock Error Current Status Flag is set or not
00486   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
00487   * @param  RNGx RNG Instance
00488   * @retval State of bit (1 or 0).
00489   */
00490 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
00491 {
00492   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
00493 }
00494
00495 /**
00496   * @brief  Indicate if the Seed Error Current Status Flag is set or not
00497   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
00498   * @param  RNGx RNG Instance
00499   * @retval State of bit (1 or 0).
00500   */
00501 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
00502 {
00503   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
00504 }
00505
00506 /**
00507   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
00508   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
00509   * @param  RNGx RNG Instance
00510   * @retval State of bit (1 or 0).
00511   */
00512 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
00513 {
00514   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
00515 }
00516
00517 /**
00518   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
00519   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
00520   * @param  RNGx RNG Instance
00521   * @retval State of bit (1 or 0).
00522   */
00523 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
00524 {
00525   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
00526 }
00527
00528 /**
00529   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
00530   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
00531   * @param  RNGx RNG Instance
00532   * @retval None
00533   */
00534 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
00535 {
00536   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
00537 }
00538
00539 /**
00540   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
00541   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
00542   * @param  RNGx RNG Instance
00543   * @retval None
00544   */
00545 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
00546 {
00547   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
00548 }
00549
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup RNG_LL_EF_IT_Management IT Management
00555   * @{
00556   */
00557
00558 /**
00559   * @brief  Enable Random Number Generator Interrupt
00560   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00561   * @rmtoll CR           IE            LL_RNG_EnableIT
00562   * @param  RNGx RNG Instance
00563   * @retval None
00564   */
00565 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
00566 {
00567   SET_BIT(RNGx->CR, RNG_CR_IE);
00568 }
00569
00570 /**
00571   * @brief  Disable Random Number Generator Interrupt
00572   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00573   * @rmtoll CR           IE            LL_RNG_DisableIT
00574   * @param  RNGx RNG Instance
00575   * @retval None
00576   */
00577 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
00578 {
00579   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
00580 }
00581
00582 /**
00583   * @brief  Check if Random Number Generator Interrupt is enabled
00584   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00585   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
00586   * @param  RNGx RNG Instance
00587   * @retval State of bit (1 or 0).
00588   */
00589 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
00590 {
00591   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
00592 }
00593
00594 /**
00595   * @}
00596   */
00597
00598 /** @defgroup RNG_LL_EF_Data_Management Data Management
00599   * @{
00600   */
00601
00602 /**
00603   * @brief  Return32-bit Random Number value
00604   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
00605   * @param  RNGx RNG Instance
00606   * @retval Generated 32-bit random value
00607   */
00608 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
00609 {
00610   return (uint32_t)(READ_REG(RNGx->DR));
00611 }
00612
00613 /**
00614   * @}
00615   */
00616
00617 #if defined (RNG_VER_3_1)
00618 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
00619   * @{
00620   */
00621
00622 /**
00623   * @brief  Set RNG Health Test Control
00624   * @rmtoll HTCR       HTCFG       LL_RNG_SetHealthConfig
00625   * @param  RNGx RNG Instance
00626   * @param  HTCFG can be values of 32 bits
00627   * @retval None
00628   */
00629 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
00630 {
00631   WRITE_REG(RNGx->HTCR, HTCFG);
00632 }
00633
00634 /**
00635   * @brief  Get RNG Health Test Control
00636   * @rmtoll HTCR         HTCFG        LL_RNG_GetHealthConfig
00637   * @param  RNGx RNG Instance
00638   * @retval Return 32-bit RNG Health Test configuration
00639   */
00640 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
00641 {
00642   return (uint32_t)READ_REG(RNGx->HTCR);
00643 }
00644
00645 /**
00646   * @}
00647   */
00648 #endif  /*RNG_VER_3_1*/
00649 #if defined(USE_FULL_LL_DRIVER)
00650 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
00651   * @{
00652   */
00653 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
00654 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
00655 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
00656
00657 /**
00658   * @}
00659   */
00660 #endif /* USE_FULL_LL_DRIVER */
00661
00662 /**
00663   * @}
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 #endif /* RNG */
00671
00672 /**
00673   * @}
00674   */
00675
00676 #ifdef __cplusplus
00677 }
00678 #endif
00679
00680 #endif /* __STM32H7xx_LL_RNG_H */
00681
00682 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rtc.c Source File

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stm32h7xx_ll_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_rtc.h"
00023 #include "stm32h7xx_ll_cortex.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(RTC)
00035
00036 /** @addtogroup RTC_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup RTC_LL_Private_Constants
00044   * @{
00045   */
00046 /* Default values used for prescaler */
00047 #define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
00048 #define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
00049
00050 /* Values used for timeout */
00051 #define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
00052 #define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
00053 /**
00054   * @}
00055   */
00056
00057 /* Private macros ------------------------------------------------------------*/
00058 /** @addtogroup RTC_LL_Private_Macros
00059   * @{
00060   */
00061
00062 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00063                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00064
00065 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
00066
00067 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
00068
00069 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00070                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00071
00072 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00073                                        || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00074
00075 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00076 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00077 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00078 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00079
00080 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00081                                    || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00082                                    || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00083                                    || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00084                                    || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00085                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00086                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00087
00088 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
00089
00090 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
00091                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
00092                                  || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
00093                                  || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
00094                                  || ((__VALUE__) == LL_RTC_MONTH_MAY) \
00095                                  || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
00096                                  || ((__VALUE__) == LL_RTC_MONTH_JULY) \
00097                                  || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
00098                                  || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
00099                                  || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
00100                                  || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
00101                                  || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
00102
00103 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00104
00105 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00106                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00107                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00108                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00109                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00110                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00111
00112 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00113                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00114                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00115                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00116                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00117                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00118
00119
00120 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00121                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00122
00123 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00124                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00125
00126
00127 /**
00128   * @}
00129   */
00130 /* Private function prototypes -----------------------------------------------*/
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @addtogroup RTC_LL_Exported_Functions
00133   * @{
00134   */
00135
00136 /** @addtogroup RTC_LL_EF_Init
00137   * @{
00138   */
00139
00140 /**
00141   * @brief  De-Initializes the RTC registers to their default reset values.
00142   * @note   This function does not reset the RTC Clock source and RTC Backup Data
00143   *         registers.
00144   * @param  RTCx RTC Instance
00145   * @retval An ErrorStatus enumeration value:
00146   *          - SUCCESS: RTC registers are de-initialized
00147   *          - ERROR: RTC registers are not de-initialized
00148   */
00149 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00150 {
00151   ErrorStatus status = ERROR;
00152
00153   /* Check the parameter */
00154   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00155
00156   /* Disable the write protection for RTC registers */
00157   LL_RTC_DisableWriteProtection(RTCx);
00158
00159   /* Set Initialization mode */
00160   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00161   {
00162     /* Reset TR, DR and CR registers */
00163     LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
00164     LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00165
00166     /* Reset All CR bits except CR[2:0] */
00167     LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
00168
00169     LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
00170     LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00171     LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
00172     LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
00173     LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
00174     LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
00175     LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
00176     LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
00177
00178 #if defined(RTC_ICSR_ALRAWF)
00179     /* Reset ICSR register and exit initialization mode */
00180     LL_RTC_WriteReg(RTCx, ICSR,      0x00000000U);
00181 #endif /* RTC_ICSR_ALRAWF */
00182 #if defined(RTC_ISR_ALRAWF)
00183     /* Reset ISR register and exit initialization mode */
00184     LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
00185 #endif /* RTC_ISR_ALRAWF */
00186
00187 #if defined(RTC_TAMPCR_TAMP1E)
00188     /* Reset Tamper and alternate functions configuration register */
00189     LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
00190 #endif /* RTC_TAMPCR_TAMP1E */
00191
00192 #if defined(RTC_OR_ALARMOUTTYPE)
00193     /* Reset Option register */
00194     LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
00195 #endif /* RTC_OR_ALARMOUTTYPE */
00196
00197     /* Wait till the RTC RSF flag is set */
00198     status = LL_RTC_WaitForSynchro(RTCx);
00199   }
00200
00201   /* Enable the write protection for RTC registers */
00202   LL_RTC_EnableWriteProtection(RTCx);
00203
00204 #if defined (TAMP_CR1_TAMP1E)
00205   /* DeInitialization of the TAMP */
00206   LL_RTC_WriteReg(TAMP, CR1,      0xFFFF0000U);
00207   LL_RTC_WriteReg(TAMP, FLTCR,    0x00000000U);
00208   LL_RTC_WriteReg(TAMP, ATCR1,    0x00000000U);
00209   LL_RTC_WriteReg(TAMP, IER,      0x00000000U);
00210   LL_RTC_WriteReg(TAMP, SCR,      0xFFFFFFFFU);
00211 #endif /* TAMP_CR1_TAMP1E */
00212
00213   return status;
00214 }
00215
00216 /**
00217   * @brief  Initializes the RTC registers according to the specified parameters
00218   *         in RTC_InitStruct.
00219   * @param  RTCx RTC Instance
00220   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00221   *         the configuration information for the RTC peripheral.
00222   * @note   The RTC Prescaler register is write protected and can be written in
00223   *         initialization mode only.
00224   * @retval An ErrorStatus enumeration value:
00225   *          - SUCCESS: RTC registers are initialized
00226   *          - ERROR: RTC registers are not initialized
00227   */
00228 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00229 {
00230   ErrorStatus status = ERROR;
00231
00232   /* Check the parameters */
00233   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00234   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00235   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00236   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00237
00238   /* Disable the write protection for RTC registers */
00239   LL_RTC_DisableWriteProtection(RTCx);
00240
00241   /* Set Initialization mode */
00242   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00243   {
00244     /* Set Hour Format */
00245     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00246
00247     /* Configure Synchronous and Asynchronous prescaler factor */
00248     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00249     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00250
00251     /* Exit Initialization mode */
00252     LL_RTC_DisableInitMode(RTCx);
00253
00254     status = SUCCESS;
00255   }
00256   /* Enable the write protection for RTC registers */
00257   LL_RTC_EnableWriteProtection(RTCx);
00258
00259   return status;
00260 }
00261
00262 /**
00263   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00264   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00265   * @retval None
00266   */
00267 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00268 {
00269   /* Set RTC_InitStruct fields to default values */
00270   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00271   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00272   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00273 }
00274
00275 /**
00276   * @brief  Set the RTC current time.
00277   * @param  RTCx RTC Instance
00278   * @param  RTC_Format This parameter can be one of the following values:
00279   *         @arg @ref LL_RTC_FORMAT_BIN
00280   *         @arg @ref LL_RTC_FORMAT_BCD
00281   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00282   *                        the time configuration information for the RTC.
00283   * @retval An ErrorStatus enumeration value:
00284   *          - SUCCESS: RTC Time register is configured
00285   *          - ERROR: RTC Time register is not configured
00286   */
00287 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00288 {
00289   ErrorStatus status = ERROR;
00290
00291   /* Check the parameters */
00292   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00293   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00294
00295   if (RTC_Format == LL_RTC_FORMAT_BIN)
00296   {
00297     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00298     {
00299       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00300       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00301     }
00302     else
00303     {
00304       RTC_TimeStruct->TimeFormat = 0x00U;
00305       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00306     }
00307     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00308     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00309   }
00310   else
00311   {
00312     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00313     {
00314       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00315       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00316     }
00317     else
00318     {
00319       RTC_TimeStruct->TimeFormat = 0x00U;
00320       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00321     }
00322     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00323     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00324   }
00325
00326   /* Disable the write protection for RTC registers */
00327   LL_RTC_DisableWriteProtection(RTCx);
00328
00329   /* Set Initialization mode */
00330   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00331   {
00332     /* Check the input parameters format */
00333     if (RTC_Format != LL_RTC_FORMAT_BIN)
00334     {
00335       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00336                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00337     }
00338     else
00339     {
00340       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00341                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00342                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00343     }
00344
00345     /* Exit Initialization mode */
00346     LL_RTC_DisableInitMode(RTC);
00347
00348     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00349     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00350     {
00351       status = LL_RTC_WaitForSynchro(RTCx);
00352     }
00353     else
00354     {
00355       status = SUCCESS;
00356     }
00357   }
00358   /* Enable the write protection for RTC registers */
00359   LL_RTC_EnableWriteProtection(RTCx);
00360
00361   return status;
00362 }
00363
00364 /**
00365   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00366   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00367   * @retval None
00368   */
00369 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00370 {
00371   /* Time = 00h:00min:00sec */
00372   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00373   RTC_TimeStruct->Hours      = 0U;
00374   RTC_TimeStruct->Minutes    = 0U;
00375   RTC_TimeStruct->Seconds    = 0U;
00376 }
00377
00378 /**
00379   * @brief  Set the RTC current date.
00380   * @param  RTCx RTC Instance
00381   * @param  RTC_Format This parameter can be one of the following values:
00382   *         @arg @ref LL_RTC_FORMAT_BIN
00383   *         @arg @ref LL_RTC_FORMAT_BCD
00384   * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
00385   *                         the date configuration information for the RTC.
00386   * @retval An ErrorStatus enumeration value:
00387   *          - SUCCESS: RTC Day register is configured
00388   *          - ERROR: RTC Day register is not configured
00389   */
00390 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00391 {
00392   ErrorStatus status = ERROR;
00393
00394   /* Check the parameters */
00395   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00396   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00397
00398   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00399   {
00400     RTC_DateStruct->Month = (uint8_t)((RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU);
00401   }
00402   if (RTC_Format == LL_RTC_FORMAT_BIN)
00403   {
00404     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00405     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00406     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00407   }
00408   else
00409   {
00410     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00411     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00412     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00413   }
00414   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00415
00416   /* Disable the write protection for RTC registers */
00417   LL_RTC_DisableWriteProtection(RTCx);
00418
00419   /* Set Initialization mode */
00420   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00421   {
00422     /* Check the input parameters format */
00423     if (RTC_Format != LL_RTC_FORMAT_BIN)
00424     {
00425       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00426     }
00427     else
00428     {
00429       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00430                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00431     }
00432
00433     /* Exit Initialization mode */
00434     LL_RTC_DisableInitMode(RTC);
00435
00436     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00437     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00438     {
00439       status = LL_RTC_WaitForSynchro(RTCx);
00440     }
00441     else
00442     {
00443       status = SUCCESS;
00444     }
00445   }
00446   /* Enable the write protection for RTC registers */
00447   LL_RTC_EnableWriteProtection(RTCx);
00448
00449   return status;
00450 }
00451
00452 /**
00453   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00454   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00455   * @retval None
00456   */
00457 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00458 {
00459   /* Monday, January 01 xx00 */
00460   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00461   RTC_DateStruct->Day     = 1U;
00462   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00463   RTC_DateStruct->Year    = 0U;
00464 }
00465
00466 /**
00467   * @brief  Set the RTC Alarm A.
00468   * @note   The Alarm register can only be written when the corresponding Alarm
00469   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00470   * @param  RTCx RTC Instance
00471   * @param  RTC_Format This parameter can be one of the following values:
00472   *         @arg @ref LL_RTC_FORMAT_BIN
00473   *         @arg @ref LL_RTC_FORMAT_BCD
00474   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00475   *                         contains the alarm configuration parameters.
00476   * @retval An ErrorStatus enumeration value:
00477   *          - SUCCESS: ALARMA registers are configured
00478   *          - ERROR: ALARMA registers are not configured
00479   */
00480 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00481 {
00482   /* Check the parameters */
00483   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00484   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00485   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00486   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00487
00488   if (RTC_Format == LL_RTC_FORMAT_BIN)
00489   {
00490     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00491     {
00492       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00493       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00494     }
00495     else
00496     {
00497       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00498       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00499     }
00500     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00501     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00502
00503     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00504     {
00505       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00506     }
00507     else
00508     {
00509       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00510     }
00511   }
00512   else
00513   {
00514     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00515     {
00516       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00517       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00518     }
00519     else
00520     {
00521       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00522       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00523     }
00524
00525     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00526     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00527
00528     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00529     {
00530       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00531     }
00532     else
00533     {
00534       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00535     }
00536   }
00537
00538   /* Disable the write protection for RTC registers */
00539   LL_RTC_DisableWriteProtection(RTCx);
00540
00541   /* Select weekday selection */
00542   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00543   {
00544     /* Set the date for ALARM */
00545     LL_RTC_ALMA_DisableWeekday(RTCx);
00546     if (RTC_Format != LL_RTC_FORMAT_BIN)
00547     {
00548       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00549     }
00550     else
00551     {
00552       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00553     }
00554   }
00555   else
00556   {
00557     /* Set the week day for ALARM */
00558     LL_RTC_ALMA_EnableWeekday(RTCx);
00559     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00560   }
00561
00562   /* Configure the Alarm register */
00563   if (RTC_Format != LL_RTC_FORMAT_BIN)
00564   {
00565     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00566                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00567   }
00568   else
00569   {
00570     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00571                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00572                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00573                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00574   }
00575   /* Set ALARM mask */
00576   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00577
00578   /* Enable the write protection for RTC registers */
00579   LL_RTC_EnableWriteProtection(RTCx);
00580
00581   return SUCCESS;
00582 }
00583
00584 /**
00585   * @brief  Set the RTC Alarm B.
00586   * @note   The Alarm register can only be written when the corresponding Alarm
00587   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00588   * @param  RTCx RTC Instance
00589   * @param  RTC_Format This parameter can be one of the following values:
00590   *         @arg @ref LL_RTC_FORMAT_BIN
00591   *         @arg @ref LL_RTC_FORMAT_BCD
00592   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00593   *                         contains the alarm configuration parameters.
00594   * @retval An ErrorStatus enumeration value:
00595   *          - SUCCESS: ALARMB registers are configured
00596   *          - ERROR: ALARMB registers are not configured
00597   */
00598 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00599 {
00600   /* Check the parameters */
00601   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00602   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00603   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00604   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00605
00606   if (RTC_Format == LL_RTC_FORMAT_BIN)
00607   {
00608     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00609     {
00610       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00611       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00612     }
00613     else
00614     {
00615       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00616       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00617     }
00618     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00619     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00620
00621     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00622     {
00623       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00624     }
00625     else
00626     {
00627       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00628     }
00629   }
00630   else
00631   {
00632     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00633     {
00634       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00635       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00636     }
00637     else
00638     {
00639       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00640       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00641     }
00642
00643     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00644     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00645
00646     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00647     {
00648       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00649     }
00650     else
00651     {
00652       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00653     }
00654   }
00655
00656   /* Disable the write protection for RTC registers */
00657   LL_RTC_DisableWriteProtection(RTCx);
00658
00659   /* Select weekday selection */
00660   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00661   {
00662     /* Set the date for ALARM */
00663     LL_RTC_ALMB_DisableWeekday(RTCx);
00664     if (RTC_Format != LL_RTC_FORMAT_BIN)
00665     {
00666       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00667     }
00668     else
00669     {
00670       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00671     }
00672   }
00673   else
00674   {
00675     /* Set the week day for ALARM */
00676     LL_RTC_ALMB_EnableWeekday(RTCx);
00677     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00678   }
00679
00680   /* Configure the Alarm register */
00681   if (RTC_Format != LL_RTC_FORMAT_BIN)
00682   {
00683     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00684                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00685   }
00686   else
00687   {
00688     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00689                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00690                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00691                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00692   }
00693   /* Set ALARM mask */
00694   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00695
00696   /* Enable the write protection for RTC registers */
00697   LL_RTC_EnableWriteProtection(RTCx);
00698
00699   return SUCCESS;
00700 }
00701
00702 /**
00703   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00704   *         Day = 1st day of the month/Mask = all fields are masked).
00705   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00706   * @retval None
00707   */
00708 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00709 {
00710   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00711   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00712   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00713   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00714   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00715
00716   /* Alarm Day Settings : Day = 1st day of the month */
00717   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00718   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00719
00720   /* Alarm Masks Settings : Mask =  all fields are not masked */
00721   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00722 }
00723
00724 /**
00725   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00726   *         Day = 1st day of the month/Mask = all fields are masked).
00727   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00728   * @retval None
00729   */
00730 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00731 {
00732   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00733   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00734   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00735   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00736   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00737
00738   /* Alarm Day Settings : Day = 1st day of the month */
00739   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00740   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00741
00742   /* Alarm Masks Settings : Mask =  all fields are not masked */
00743   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00744 }
00745
00746 /**
00747   * @brief  Enters the RTC Initialization mode.
00748   * @note   The RTC Initialization mode is write protected, use the
00749   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00750   * @param  RTCx RTC Instance
00751   * @retval An ErrorStatus enumeration value:
00752   *          - SUCCESS: RTC is in Init mode
00753   *          - ERROR: RTC is not in Init mode
00754   */
00755 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00756 {
00757   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00758   ErrorStatus status = SUCCESS;
00759   uint32_t tmp;
00760
00761   /* Check the parameter */
00762   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00763
00764   /* Check if the Initialization mode is set */
00765   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00766   {
00767     /* Set the Initialization mode */
00768     LL_RTC_EnableInitMode(RTCx);
00769
00770     /* Wait till RTC is in INIT state and if Time out is reached exit */
00771     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00772     while ((timeout != 0U) && (tmp != 1U))
00773     {
00774       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00775       {
00776         timeout --;
00777       }
00778       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00779       if (timeout == 0U)
00780       {
00781         status = ERROR;
00782       }
00783     }
00784   }
00785   return status;
00786 }
00787
00788 /**
00789   * @brief  Exit the RTC Initialization mode.
00790   * @note   When the initialization sequence is complete, the calendar restarts
00791   *         counting after 4 RTCCLK cycles.
00792   * @note   The RTC Initialization mode is write protected, use the
00793   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00794   * @param  RTCx RTC Instance
00795   * @retval An ErrorStatus enumeration value:
00796   *          - SUCCESS: RTC exited from in Init mode
00797   *          - ERROR: Not applicable
00798   */
00799 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00800 {
00801   /* Check the parameter */
00802   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00803
00804   /* Disable initialization mode */
00805   LL_RTC_DisableInitMode(RTCx);
00806
00807   return SUCCESS;
00808 }
00809
00810 /**
00811   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00812   *         synchronized with RTC APB clock.
00813   * @note   The RTC Resynchronization mode is write protected, use the
00814   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00815   * @note   To read the calendar through the shadow registers after Calendar
00816   *         initialization, calendar update or after wakeup from low power modes
00817   *         the software must first clear the RSF flag.
00818   *         The software must then wait until it is set again before reading
00819   *         the calendar, which means that the calendar registers have been
00820   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00821   * @param  RTCx RTC Instance
00822   * @retval An ErrorStatus enumeration value:
00823   *          - SUCCESS: RTC registers are synchronised
00824   *          - ERROR: RTC registers are not synchronised
00825   */
00826 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00827 {
00828   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00829   ErrorStatus status = SUCCESS;
00830   uint32_t tmp;
00831
00832   /* Check the parameter */
00833   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00834
00835   /* Clear RSF flag */
00836   LL_RTC_ClearFlag_RS(RTCx);
00837
00838   /* Wait the registers to be synchronised */
00839   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00840   while ((timeout != 0U) && (tmp != 0U))
00841   {
00842     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00843     {
00844       timeout--;
00845     }
00846     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00847     if (timeout == 0U)
00848     {
00849       status = ERROR;
00850     }
00851   }
00852
00853   if (status != ERROR)
00854   {
00855     timeout = RTC_SYNCHRO_TIMEOUT;
00856     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00857     while ((timeout != 0U) && (tmp != 1U))
00858     {
00859       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00860       {
00861         timeout--;
00862       }
00863       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00864       if (timeout == 0U)
00865       {
00866         status = ERROR;
00867       }
00868     }
00869   }
00870
00871   return (status);
00872 }
00873
00874 /**
00875   * @}
00876   */
00877
00878 /**
00879   * @}
00880   */
00881
00882 /**
00883   * @}
00884   */
00885
00886 #endif /* defined(RTC) */
00887
00888 /**
00889   * @}
00890   */
00891
00892 #endif /* USE_FULL_LL_DRIVER */
00893
00894 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_rtc.h Source File

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stm32h7xx_ll_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_RTC_H
00022 #define STM32H7xx_LL_RTC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(RTC)
00036
00037 /** @defgroup RTC_LL RTC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00045   * @{
00046   */
00047 /* Masks Definition */
00048 #define RTC_LL_INIT_MASK              0xFFFFFFFFU
00049 #define RTC_LL_RSF_MASK               0xFFFFFF5FU
00050
00051 /* Write protection defines */
00052 #define RTC_WRITE_PROTECTION_DISABLE  0xFFU
00053 #define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
00054 #define RTC_WRITE_PROTECTION_ENABLE_2 0x53U
00055
00056 /* Defines used to combine date & time */
00057 #define RTC_OFFSET_WEEKDAY            24U
00058 #define RTC_OFFSET_DAY                16U
00059 #define RTC_OFFSET_MONTH              8U
00060 #define RTC_OFFSET_HOUR               16U
00061 #define RTC_OFFSET_MINUTE             8U
00062
00063 /**
00064   * @}
00065   */
00066
00067 /* Private macros ------------------------------------------------------------*/
00068 #if defined(USE_FULL_LL_DRIVER)
00069 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00070   * @{
00071   */
00072 /**
00073   * @}
00074   */
00075 #endif /*USE_FULL_LL_DRIVER*/
00076
00077 /* Exported types ------------------------------------------------------------*/
00078 #if defined(USE_FULL_LL_DRIVER)
00079 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00080   * @{
00081   */
00082
00083 /**
00084   * @brief  RTC Init structures definition
00085   */
00086 typedef struct
00087 {
00088   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00089                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00090
00091                               This feature can be modified afterwards using unitary function
00092                               @ref LL_RTC_SetHourFormat(). */
00093
00094   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00095                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00096
00097                               This feature can be modified afterwards using unitary function
00098                               @ref LL_RTC_SetAsynchPrescaler(). */
00099
00100   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00101                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00102
00103                               This feature can be modified afterwards using unitary function
00104                               @ref LL_RTC_SetSynchPrescaler(). */
00105 } LL_RTC_InitTypeDef;
00106
00107 /**
00108   * @brief  RTC Time structure definition
00109   */
00110 typedef struct
00111 {
00112   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00113                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00114
00115                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00116
00117   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00118                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00119                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00120
00121                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00122
00123   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00124                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00125
00126                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00127
00128   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00129                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00130
00131                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00132 } LL_RTC_TimeTypeDef;
00133
00134 /**
00135   * @brief  RTC Date structure definition
00136   */
00137 typedef struct
00138 {
00139   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00140                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00141
00142                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00143
00144   uint8_t Month;    /*!< Specifies the RTC Date Month.
00145                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00146
00147                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00148
00149   uint8_t Day;      /*!< Specifies the RTC Date Day.
00150                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00151
00152                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00153
00154   uint8_t Year;     /*!< Specifies the RTC Date Year.
00155                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00156
00157                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00158 } LL_RTC_DateTypeDef;
00159
00160 /**
00161   * @brief  RTC Alarm structure definition
00162   */
00163 typedef struct
00164 {
00165   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00166
00167   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00168                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00169
00170                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00171                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00172                                  */
00173
00174   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00175                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00176
00177                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00178                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00179                                  */
00180
00181   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00182                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00183
00184                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00185                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00186
00187                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00188
00189                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00190                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00191                                  */
00192 } LL_RTC_AlarmTypeDef;
00193
00194 /**
00195   * @}
00196   */
00197 #endif /* USE_FULL_LL_DRIVER */
00198
00199 /* Exported constants --------------------------------------------------------*/
00200 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00201   * @{
00202   */
00203
00204 #if defined(USE_FULL_LL_DRIVER)
00205 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00206   * @{
00207   */
00208 #define LL_RTC_FORMAT_BIN                  0x00000000U /*!< Binary data format */
00209 #define LL_RTC_FORMAT_BCD                  0x00000001U /*!< BCD data format */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00215   * @{
00216   */
00217 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
00218 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00224   * @{
00225   */
00226 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
00227 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00228 /**
00229   * @}
00230   */
00231
00232 #endif /* USE_FULL_LL_DRIVER */
00233
00234 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00235   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00236   * @{
00237   */
00238 #if defined(RTC_SCR_CALRAF)
00239 #define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF
00240 #define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF
00241 #define LL_RTC_SCR_TSF                     RTC_SCR_CTSF
00242 #define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF
00243 #define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF
00244 #define LL_RTC_SCR_ALRAF                   RTC_SCR_CALRAF
00245 #endif /* RTC_SCR_CALRAF */
00246
00247 #if defined(RTC_ICSR_ALRAWF)
00248 #define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF
00249 #define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF
00250 #define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF
00251 #define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS
00252 #define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF
00253 #define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF
00254 #endif /* RTC_ICSR_ALRAWF */
00255 #if defined(RTC_ISR_ALRAWF)
00256 #define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
00257 #define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
00258 #define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
00259 #define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
00260 #define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
00261 #define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
00262 #define LL_RTC_ISR_TSF                     RTC_ISR_TSF
00263 #define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
00264 #define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
00265 #define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
00266 #define LL_RTC_ISR_INITF                   RTC_ISR_INITF
00267 #define LL_RTC_ISR_RSF                     RTC_ISR_RSF
00268 #define LL_RTC_ISR_INITS                   RTC_ISR_INITS
00269 #define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
00270 #define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
00271 #define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
00272 #define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
00273 #endif /* RTC_ISR_ALRAWF */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup RTC_LL_EC_IT IT Defines
00279   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00280   * @{
00281   */
00282 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00283 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00284 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00285 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00286 #if defined(RTC_TAMPCR_TAMP3E)
00287 #define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
00288 #endif /* RTC_TAMPCR_TAMP3E */
00289 #if defined(RTC_TAMPCR_TAMP2E)
00290 #define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
00291 #endif /* RTC_TAMPCR_TAMP2E */
00292 #if defined(RTC_TAMPCR_TAMP1E)
00293 #define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
00294 #endif /* RTC_TAMPCR_TAMP1E */
00295 #if defined(RTC_TAMPCR_TAMPIE)
00296 #define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
00297 #endif /* RTC_TAMPCR_TAMPIE */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00303   * @{
00304   */
00305 #define LL_RTC_WEEKDAY_MONDAY              (uint8_t)0x01 /*!< Monday    */
00306 #define LL_RTC_WEEKDAY_TUESDAY             (uint8_t)0x02 /*!< Tuesday   */
00307 #define LL_RTC_WEEKDAY_WEDNESDAY           (uint8_t)0x03 /*!< Wednesday */
00308 #define LL_RTC_WEEKDAY_THURSDAY            (uint8_t)0x04 /*!< Thrusday  */
00309 #define LL_RTC_WEEKDAY_FRIDAY              (uint8_t)0x05 /*!< Friday    */
00310 #define LL_RTC_WEEKDAY_SATURDAY            (uint8_t)0x06 /*!< Saturday  */
00311 #define LL_RTC_WEEKDAY_SUNDAY              (uint8_t)0x07 /*!< Sunday    */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup RTC_LL_EC_MONTH  MONTH
00317   * @{
00318   */
00319 #define LL_RTC_MONTH_JANUARY               (uint8_t)0x01  /*!< January   */
00320 #define LL_RTC_MONTH_FEBRUARY              (uint8_t)0x02  /*!< February  */
00321 #define LL_RTC_MONTH_MARCH                 (uint8_t)0x03  /*!< March     */
00322 #define LL_RTC_MONTH_APRIL                 (uint8_t)0x04  /*!< April     */
00323 #define LL_RTC_MONTH_MAY                   (uint8_t)0x05  /*!< May       */
00324 #define LL_RTC_MONTH_JUNE                  (uint8_t)0x06  /*!< June      */
00325 #define LL_RTC_MONTH_JULY                  (uint8_t)0x07  /*!< July      */
00326 #define LL_RTC_MONTH_AUGUST                (uint8_t)0x08  /*!< August    */
00327 #define LL_RTC_MONTH_SEPTEMBER             (uint8_t)0x09  /*!< September */
00328 #define LL_RTC_MONTH_OCTOBER               (uint8_t)0x10  /*!< October   */
00329 #define LL_RTC_MONTH_NOVEMBER              (uint8_t)0x11  /*!< November  */
00330 #define LL_RTC_MONTH_DECEMBER              (uint8_t)0x12  /*!< December  */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00336   * @{
00337   */
00338 #define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
00339 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00345   * @{
00346   */
00347 #define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
00348 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00349 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00350 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00356   * @{
00357   */
00358 #if defined(RTC_CR_TAMPALRM_TYPE)
00359 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE   /*!< RTC_ALARM is open-drain output */
00360 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0x00000000U            /*!< RTC_ALARM is push-pull output */
00361 #endif /* RTC_CR_TAMPALRM_TYPE */
00362 #if defined(RTC_OR_ALARMOUTTYPE)
00363 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U            /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
00364 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE    /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
00365 #endif /* RTC_OR_ALARMOUTTYPE */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00371   * @{
00372   */
00373 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00374 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00380   * @{
00381   */
00382 #define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
00383 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00389   * @{
00390   */
00391 #define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00392 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00398   * @{
00399   */
00400 #define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
00401 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00402 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00403 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00404 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00405 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00411   * @{
00412   */
00413 #define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00414 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00420   * @{
00421   */
00422 #define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
00423 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00424 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00425 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00426 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00427 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00433   * @{
00434   */
00435 #define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00436 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00442   * @{
00443   */
00444 #define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
00445 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00451   * @{
00452   */
00453 #define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
00454 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00455 /**
00456   * @}
00457   */
00458
00459 #if defined(TAMP_CR1_TAMP1E)
00460 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00461   * @{
00462   */
00463 #define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
00464 #endif /* TAMP_CR1_TAMP1E */
00465 #if defined(TAMP_CR1_TAMP2E)
00466 #define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
00467 #endif /* TAMP_CR1_TAMP2E */
00468 #if defined(TAMP_CR1_TAMP3E)
00469 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
00470 /**
00471   * @}
00472   */
00473 #endif /* TAMP_CR1_TAMP3E */
00474
00475 #if defined(TAMP_CR1_TAMP1E)
00476 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00477   * @{
00478   */
00479 #define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */
00480 #endif /* TAMP_CR1_TAMP1E */
00481 #if defined(TAMP_CR1_TAMP2E)
00482 #define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00483 #endif /* TAMP_CR1_TAMP2E */
00484 #if defined(TAMP_CR1_TAMP3E)
00485 #define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */
00486 /**
00487   * @}
00488   */
00489 #endif /* TAMP_CR1_TAMP3E */
00490
00491 #if defined(TAMP_CR1_TAMP1E)
00492 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00493   * @{
00494   */
00495 #define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00496 #endif /* TAMP_CR1_TAMP1E */
00497 #if defined(TAMP_CR1_TAMP2E)
00498 #define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00499 #endif /* TAMP_CR1_TAMP2E */
00500 #if defined(TAMP_CR1_TAMP3E)
00501 #define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00502 #endif /* TAMP_CR1_TAMP3E */
00503 /**
00504   * @}
00505   */
00506
00507 #if defined(TAMP_FLTCR_TAMPPRCH)
00508 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00509   * @{
00510   */
00511 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U            /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00512 #define LL_RTC_TAMPER_DURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00513 #define LL_RTC_TAMPER_DURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00514 #define LL_RTC_TAMPER_DURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00515 /**
00516   * @}
00517   */
00518 #endif /* TAMP_FLTCR_TAMPPRCH */
00519
00520 #if defined(TAMP_FLTCR_TAMPFLT)
00521 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00522   * @{
00523   */
00524 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U             /*!< Tamper filter is disabled */
00525 #define LL_RTC_TAMPER_FILTER_2SAMPLE       TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00526 #define LL_RTC_TAMPER_FILTER_4SAMPLE       TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00527 #define LL_RTC_TAMPER_FILTER_8SAMPLE       TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00528 /**
00529   * @}
00530   */
00531 #endif /* TAMP_FLTCR_TAMPFLT */
00532
00533 #if defined(TAMP_FLTCR_TAMPFREQ)
00534 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00535   * @{
00536   */
00537 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00538 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00539 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00540 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00541 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00542 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00543 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00544 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00545 /**
00546   * @}
00547   */
00548 #endif /* TAMP_FLTCR_TAMPFREQ */
00549
00550 #if defined(TAMP_CR1_TAMP1E)
00551 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00552   * @{
00553   */
00554 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00555 #endif /* TAMP_CR1_TAMP1E */
00556 #if defined(TAMP_CR1_TAMP2E)
00557 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00558 #endif /* TAMP_CR1_TAMP2E */
00559 #if defined(TAMP_CR1_TAMP3E)
00560 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00561 /**
00562   * @}
00563   */
00564 #endif /* TAMP_CR1_TAMP3E */
00565
00566 #if defined (RTC_TAMPCR_TAMP1E)
00567 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00568   * @{
00569   */
00570 #define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
00571 #endif /* RTC_TAMPCR_TAMP1E */
00572 #if defined (RTC_TAMPCR_TAMP2E)
00573 #define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
00574 #endif /* RTC_TAMPCR_TAMP2E */
00575 #if defined (RTC_TAMPCR_TAMP3E)
00576 #define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
00577 /**
00578   * @}
00579   */
00580 #endif /* RTC_TAMPCR_TAMP3E */
00581
00582 #if defined (RTC_TAMPCR_TAMP1E)
00583 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00584   * @{
00585   */
00586 #define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00587 #endif /* RTC_TAMPCR_TAMP1E */
00588 #if defined (RTC_TAMPCR_TAMP2E)
00589 #define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00590 #endif /* RTC_TAMPCR_TAMP2E */
00591 #if defined (RTC_TAMPCR_TAMP3E)
00592 #define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
00593 /**
00594   * @}
00595   */
00596 #endif /* RTC_TAMPCR_TAMP3E */
00597
00598 #if defined (RTC_TAMPCR_TAMP1E)
00599 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00600   * @{
00601   */
00602 #define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00603 #endif /* RTC_TAMPCR_TAMP1E */
00604 #if defined (RTC_TAMPCR_TAMP2E)
00605 #define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00606 #endif /* RTC_TAMPCR_TAMP2E */
00607 #if defined (RTC_TAMPCR_TAMP3E)
00608 #define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00609 /**
00610   * @}
00611   */
00612 #endif /* RTC_TAMPCR_TAMP3E */
00613
00614
00615 #if defined(RTC_TAMPCR_TAMPPRCH)
00616 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00617   * @{
00618   */
00619 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00620 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00621 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00622 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00623 /**
00624   * @}
00625   */
00626 #endif /* RTC_TAMPCR_TAMPPRCH */
00627
00628 #if defined(RTC_TAMPCR_TAMPFLT)
00629 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00630   * @{
00631   */
00632 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
00633 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00634 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00635 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00636 /**
00637   * @}
00638   */
00639 #endif /* RTC_TAMPCR_TAMPFLT */
00640
00641 #if defined(RTC_TAMPCR_TAMPFREQ)
00642 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00643   * @{
00644   */
00645 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00646 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00647 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00648 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00649 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00650 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00651 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00652 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00653 /**
00654   * @}
00655   */
00656 #endif /* RTC_TAMPCR_TAMPFREQ */
00657
00658 #if defined (RTC_TAMPCR_TAMP1E)
00659 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00660   * @{
00661   */
00662 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00663 #endif /* RTC_TAMPCR_TAMP1E */
00664 #if defined (RTC_TAMPCR_TAMP2E)
00665 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00666 #endif /* RTC_TAMPCR_TAMP2E */
00667 #if defined (RTC_TAMPCR_TAMP3E)
00668 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00669 /**
00670   * @}
00671   */
00672 #endif /* RTC_TAMPCR_TAMP3E */
00673
00674
00675 #if defined(TAMP_ATCR1_TAMP1AM)
00676 /** @defgroup RTC_LL_EC_ACTIVE_MODE   ACTIVE TAMPER MODE
00677   * @{
00678   */
00679 #define LL_RTC_TAMPER_ATAMP_TAMP1AM               TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */
00680 #endif /* TAMP_ATCR1_TAMP1AM */
00681 #if defined(TAMP_ATCR1_TAMP2AM)
00682 #define LL_RTC_TAMPER_ATAMP_TAMP2AM               TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */
00683 #endif /* TAMP_ATCR1_TAMP2AM */
00684 #if defined(TAMP_ATCR1_TAMP3AM)
00685 #define LL_RTC_TAMPER_ATAMP_TAMP3AM               TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */
00686 /**
00687   * @}
00688   */
00689 #endif /* TAMP_ATCR1_TAMP3AM */
00690
00691
00692 #if defined(TAMP_ATCR1_ATCKSEL)
00693 /** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER   ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
00694   * @{
00695   */
00696 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK      0U                                                                      /*!< RTCCLK */
00697 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2    TAMP_ATCR1_ATCKSEL_0                                                    /*!< RTCCLK/2 */
00698 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4    TAMP_ATCR1_ATCKSEL_1                                                    /*!< RTCCLK/4 */
00699 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8    (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/8 */
00700 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16   TAMP_ATCR1_ATCKSEL_2                                                    /*!< RTCCLK/16 */
00701 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/32 */
00702 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                           /*!< RTCCLK/64 */
00703 #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128  (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)    /*!< RTCCLK/128 */
00704 /**
00705   * @}
00706   */
00707 #endif /* TAMP_ATCR1_ATCKSEL */
00708
00709 #if defined(TAMP_ATCR1_TAMP1AM)
00710 /** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION   ACTIVE TAMPER OUTPUT SELECTION
00711   * @{
00712   */
00713 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL1_Pos)
00714 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL1_Pos)
00715 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL1_Pos)
00716 #endif /* TAMP_ATCR1_TAMP1AM */
00717
00718 #if defined(TAMP_ATCR1_TAMP2AM)
00719 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL2_Pos)
00720 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL2_Pos)
00721 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL2_Pos)
00722 #endif /* TAMP_ATCR1_TAMP2AM */
00723
00724 #if defined(TAMP_ATCR1_TAMP3AM)
00725 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL3_Pos)
00726 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL3_Pos)
00727 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL3_Pos)
00728 #endif /* TAMP_ATCR1_TAMP3AM */
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00734   * @{
00735   */
00736 #define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
00737 #define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                      /*!< RTC/8 clock is selected */
00738 #define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                      /*!< RTC/4 clock is selected */
00739 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00740 #define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                      /*!< ck_spre (usually 1 Hz) clock is selected */
00741 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup RTC_LL_EC_BKP  BACKUP
00747   * @{
00748   */
00749 #define LL_RTC_BKP_DR0                     0x00000000U
00750 #define LL_RTC_BKP_DR1                     0x00000001U
00751 #define LL_RTC_BKP_DR2                     0x00000002U
00752 #define LL_RTC_BKP_DR3                     0x00000003U
00753 #define LL_RTC_BKP_DR4                     0x00000004U
00754 #define LL_RTC_BKP_DR5                     0x00000005U
00755 #define LL_RTC_BKP_DR6                     0x00000006U
00756 #define LL_RTC_BKP_DR7                     0x00000007U
00757 #define LL_RTC_BKP_DR8                     0x00000008U
00758 #define LL_RTC_BKP_DR9                     0x00000009U
00759 #define LL_RTC_BKP_DR10                    0x0000000AU
00760 #define LL_RTC_BKP_DR11                    0x0000000BU
00761 #define LL_RTC_BKP_DR12                    0x0000000CU
00762 #define LL_RTC_BKP_DR13                    0x0000000DU
00763 #define LL_RTC_BKP_DR14                    0x0000000EU
00764 #define LL_RTC_BKP_DR15                    0x0000000FU
00765 #define LL_RTC_BKP_DR16                    0x00000010U
00766 #define LL_RTC_BKP_DR17                    0x00000011U
00767 #define LL_RTC_BKP_DR18                    0x00000012U
00768 #define LL_RTC_BKP_DR19                    0x00000013U
00769 #define LL_RTC_BKP_DR20                    0x00000014U
00770 #define LL_RTC_BKP_DR21                    0x00000015U
00771 #define LL_RTC_BKP_DR22                    0x00000016U
00772 #define LL_RTC_BKP_DR23                    0x00000017U
00773 #define LL_RTC_BKP_DR24                    0x00000018U
00774 #define LL_RTC_BKP_DR25                    0x00000019U
00775 #define LL_RTC_BKP_DR26                    0x0000001AU
00776 #define LL_RTC_BKP_DR27                    0x0000001BU
00777 #define LL_RTC_BKP_DR28                    0x0000001CU
00778 #define LL_RTC_BKP_DR29                    0x0000001DU
00779 #define LL_RTC_BKP_DR30                    0x0000001EU
00780 #define LL_RTC_BKP_DR31                    0x0000001FU
00781 /**
00782   * @}
00783   */
00784
00785 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00786   * @{
00787   */
00788 #define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
00789 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
00790 #define LL_RTC_CALIB_OUTPUT_512HZ           RTC_CR_COE                 /*!< Calibration output is 512 Hz */
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00796   * @{
00797   */
00798 #define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
00799 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00800 /**
00801   * @}
00802   */
00803
00804 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00805   * @{
00806   */
00807 #define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
00808 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00809 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00810 /**
00811   * @}
00812   */
00813
00814 /**
00815   * @}
00816   */
00817
00818 /* Exported macro ------------------------------------------------------------*/
00819 /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
00820   * @{
00821   */
00822
00823 /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
00824   * @{
00825   */
00826
00827 /**
00828   * @brief  Write a value in RTC register
00829   * @param  __INSTANCE__ RTC Instance
00830   * @param  __REG__ Register to be written
00831   * @param  __VALUE__ Value to be written in the register
00832   * @retval None
00833   */
00834 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
00835
00836 /**
00837   * @brief  Read a value in RTC register
00838   * @param  __INSTANCE__ RTC Instance
00839   * @param  __REG__ Register to be read
00840   * @retval Register value
00841   */
00842 #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00848   * @{
00849   */
00850
00851 /**
00852   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00853   * @param  __VALUE__ Byte to be converted
00854   * @retval Converted byte
00855   */
00856 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00857
00858 /**
00859   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00860   * @param  __VALUE__ BCD value to be converted
00861   * @retval Converted byte
00862   */
00863 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
00864
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup RTC_LL_EM_Date Date helper Macros
00870   * @{
00871   */
00872
00873 /**
00874   * @brief  Helper macro to retrieve weekday.
00875   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00876   * @retval Returned value can be one of the following values:
00877   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00878   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00879   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00880   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00881   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00882   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00883   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00884   */
00885 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00886
00887 /**
00888   * @brief  Helper macro to retrieve Year in BCD format
00889   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00890   * @retval Year in BCD format (0x00 . . . 0x99)
00891   */
00892 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00893
00894 /**
00895   * @brief  Helper macro to retrieve Month in BCD format
00896   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00897   * @retval Returned value can be one of the following values:
00898   *         @arg @ref LL_RTC_MONTH_JANUARY
00899   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00900   *         @arg @ref LL_RTC_MONTH_MARCH
00901   *         @arg @ref LL_RTC_MONTH_APRIL
00902   *         @arg @ref LL_RTC_MONTH_MAY
00903   *         @arg @ref LL_RTC_MONTH_JUNE
00904   *         @arg @ref LL_RTC_MONTH_JULY
00905   *         @arg @ref LL_RTC_MONTH_AUGUST
00906   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00907   *         @arg @ref LL_RTC_MONTH_OCTOBER
00908   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00909   *         @arg @ref LL_RTC_MONTH_DECEMBER
00910   */
00911 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00912
00913 /**
00914   * @brief  Helper macro to retrieve Day in BCD format
00915   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00916   * @retval Day in BCD format (0x01 . . . 0x31)
00917   */
00918 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00919
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup RTC_LL_EM_Time Time helper Macros
00925   * @{
00926   */
00927
00928 /**
00929   * @brief  Helper macro to retrieve hour in BCD format
00930   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00931   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00932   */
00933 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00934
00935 /**
00936   * @brief  Helper macro to retrieve minute in BCD format
00937   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00938   * @retval Minutes in BCD format (0x00. . .0x59)
00939   */
00940 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00941
00942 /**
00943   * @brief  Helper macro to retrieve second in BCD format
00944   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00945   * @retval Seconds in  format (0x00. . .0x59)
00946   */
00947 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00948
00949 /**
00950   * @}
00951   */
00952
00953 /**
00954   * @}
00955   */
00956
00957 /* Exported functions --------------------------------------------------------*/
00958 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00959   * @{
00960   */
00961
00962 /** @defgroup RTC_LL_EF_Configuration Configuration
00963   * @{
00964   */
00965
00966 /**
00967   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00968   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00969   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00970   * @rmtoll RTC_CR           FMT           LL_RTC_SetHourFormat
00971   * @param  RTCx RTC Instance
00972   * @param  HourFormat This parameter can be one of the following values:
00973   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00974   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00978 {
00979   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00980 }
00981
00982 /**
00983   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00984   * @rmtoll RTC_CR           FMT           LL_RTC_GetHourFormat
00985   * @param  RTCx RTC Instance
00986   * @retval Returned value can be one of the following values:
00987   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00988   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00989   */
00990 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00991 {
00992   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00993 }
00994
00995 /**
00996   * @brief  Select the flag to be routed to RTC_ALARM output
00997   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00998   * @rmtoll RTC_CR           OSEL          LL_RTC_SetAlarmOutEvent
00999   * @param  RTCx RTC Instance
01000   * @param  AlarmOutput This parameter can be one of the following values:
01001   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
01002   *         @arg @ref LL_RTC_ALARMOUT_ALMA
01003   *         @arg @ref LL_RTC_ALARMOUT_ALMB
01004   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
01005   * @retval None
01006   */
01007 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
01008 {
01009   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
01010 }
01011
01012 /**
01013   * @brief  Get the flag to be routed to RTC_ALARM output
01014   * @rmtoll RTC_CR           OSEL          LL_RTC_GetAlarmOutEvent
01015   * @param  RTCx RTC Instance
01016   * @retval Returned value can be one of the following values:
01017   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
01018   *         @arg @ref LL_RTC_ALARMOUT_ALMA
01019   *         @arg @ref LL_RTC_ALARMOUT_ALMB
01020   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
01021   */
01022 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
01023 {
01024   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
01025 }
01026
01027 #if defined(RTC_CR_TAMPALRM_TYPE)
01028 /**
01029   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
01030   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
01031   * @param  RTCx RTC Instance
01032   * @param  Output This parameter can be one of the following values:
01033   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
01034   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
01035   * @retval None
01036   */
01037 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
01038 {
01039   MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
01040 }
01041
01042 /**
01043   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
01044   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
01045   * @param  RTCx RTC Instance
01046   * @retval Returned value can be one of the following values:
01047   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
01048   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
01049   */
01050 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
01051 {
01052   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
01053 }
01054 #endif /* RTC_CR_TAMPALRM_TYPE */
01055
01056 #if defined(RTC_ICSR_INIT)
01057 /**
01058   * @brief  Enable initialization mode
01059   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
01060   *         and prescaler register (RTC_PRER).
01061   *         Counters are stopped and start counting from the new value when INIT is reset.
01062   * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
01063   * @param  RTCx RTC Instance
01064   * @retval None
01065   */
01066 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
01067 {
01068   /* Set the Initialization mode */
01069   WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
01070 }
01071
01072 /**
01073   * @brief  Disable initialization mode (Free running mode)
01074   * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
01075   * @param  RTCx RTC Instance
01076   * @retval None
01077   */
01078 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
01079 {
01080   /* Exit Initialization mode */
01081   WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
01082 }
01083
01084 #endif /* RTC_ICSR_INIT */
01085
01086 #if defined(RTC_OR_ALARMOUTTYPE)
01087 /**
01088   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
01089   * @note   Used only when RTC_ALARM is mapped on PC13
01090   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
01091   * @param  RTCx RTC Instance
01092   * @param  Output This parameter can be one of the following values:
01093   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
01094   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
01098 {
01099   MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
01100 }
01101
01102 /**
01103   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
01104   * @note   used only when RTC_ALARM is mapped on PC13
01105   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
01106   * @param  RTCx RTC Instance
01107   * @retval Returned value can be one of the following values:
01108   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
01109   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
01110   */
01111 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
01112 {
01113   return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
01114 }
01115 #endif /* RTC_OR_ALARMOUTTYPE */
01116
01117 #if defined(RTC_ISR_INIT)
01118 /**
01119   * @brief  Enable initialization mode
01120   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
01121   *         and prescaler register (RTC_PRER).
01122   *         Counters are stopped and start counting from the new value when INIT is reset.
01123   * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
01124   * @param  RTCx RTC Instance
01125   * @retval None
01126   */
01127 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
01128 {
01129   /* Set the Initialization mode */
01130   WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK);
01131 }
01132
01133 /**
01134   * @brief  Disable initialization mode (Free running mode)
01135   * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
01136   * @param  RTCx RTC Instance
01137   * @retval None
01138   */
01139 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
01140 {
01141   /* Exit Initialization mode */
01142   WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
01143 }
01144 #endif /* RTC_ISR_INIT */
01145
01146 /**
01147   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
01148   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01149   * @rmtoll RTC_CR           POL           LL_RTC_SetOutputPolarity
01150   * @param  RTCx RTC Instance
01151   * @param  Polarity This parameter can be one of the following values:
01152   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
01153   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
01154   * @retval None
01155   */
01156 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
01157 {
01158   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
01159 }
01160
01161 /**
01162   * @brief  Get Output polarity
01163   * @rmtoll RTC_CR           POL           LL_RTC_GetOutputPolarity
01164   * @param  RTCx RTC Instance
01165   * @retval Returned value can be one of the following values:
01166   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
01167   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
01168   */
01169 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
01170 {
01171   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
01172 }
01173
01174 /**
01175   * @brief  Enable Bypass the shadow registers
01176   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01177   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
01178   * @param  RTCx RTC Instance
01179   * @retval None
01180   */
01181 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
01182 {
01183   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
01184 }
01185
01186 /**
01187   * @brief  Disable Bypass the shadow registers
01188   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
01189   * @param  RTCx RTC Instance
01190   * @retval None
01191   */
01192 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
01193 {
01194   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
01195 }
01196
01197 /**
01198   * @brief  Check if Shadow registers bypass is enabled or not.
01199   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
01200   * @param  RTCx RTC Instance
01201   * @retval State of bit (1 or 0).
01202   */
01203 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
01204 {
01205   return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
01206 }
01207
01208 /**
01209   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
01210   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01211   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01212   * @rmtoll RTC_CR           REFCKON       LL_RTC_EnableRefClock
01213   * @param  RTCx RTC Instance
01214   * @retval None
01215   */
01216 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
01217 {
01218   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
01219 }
01220
01221 /**
01222   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
01223   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01224   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01225   * @rmtoll RTC_CR           REFCKON       LL_RTC_DisableRefClock
01226   * @param  RTCx RTC Instance
01227   * @retval None
01228   */
01229 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
01230 {
01231   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
01232 }
01233
01234 /**
01235   * @brief  Set Asynchronous prescaler factor
01236   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
01237   * @param  RTCx RTC Instance
01238   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
01239   * @retval None
01240   */
01241 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
01242 {
01243   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
01244 }
01245
01246 /**
01247   * @brief  Set Synchronous prescaler factor
01248   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
01249   * @param  RTCx RTC Instance
01250   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
01251   * @retval None
01252   */
01253 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
01254 {
01255   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
01256 }
01257
01258 /**
01259   * @brief  Get Asynchronous prescaler factor
01260   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
01261   * @param  RTCx RTC Instance
01262   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
01263   */
01264 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
01265 {
01266   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
01267 }
01268
01269 /**
01270   * @brief  Get Synchronous prescaler factor
01271   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
01272   * @param  RTCx RTC Instance
01273   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
01274   */
01275 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
01276 {
01277   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
01278 }
01279
01280 /**
01281   * @brief  Enable the write protection for RTC registers.
01282   * @rmtoll RTC_WPR          KEY           LL_RTC_EnableWriteProtection
01283   * @param  RTCx RTC Instance
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
01287 {
01288   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
01289 }
01290
01291 /**
01292   * @brief  Disable the write protection for RTC registers.
01293   * @rmtoll RTC_WPR          KEY           LL_RTC_DisableWriteProtection
01294   * @param  RTCx RTC Instance
01295   * @retval None
01296   */
01297 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
01298 {
01299   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
01300   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
01301 }
01302
01303 #if defined(RTC_CR_TAMPOE)
01304 /**
01305   * @brief  Enable tamper output.
01306   * @note When the tamper output is enabled, all external and internal tamper flags
01307   *       are ORed and routed to the TAMPALRM output.
01308   * @rmtoll RTC_CR           TAMPOE       LL_RTC_EnableTamperOutput
01309   * @param  RTCx RTC Instance
01310   * @retval None
01311   */
01312 __STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
01313 {
01314   SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
01315 }
01316
01317 /**
01318   * @brief  Disable tamper output.
01319   * @rmtoll RTC_CR           TAMPOE       LL_RTC_DisableTamperOutput
01320   * @param  RTCx RTC Instance
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
01324 {
01325   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
01326 }
01327
01328 /**
01329   * @brief  Check if tamper output is enabled or not.
01330   * @rmtoll RTC_CR           TAMPOE       LL_RTC_IsTamperOutputEnabled
01331   * @param  RTCx RTC Instance
01332   * @retval State of bit (1 or 0).
01333   */
01334 __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
01335 {
01336   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);
01337 }
01338 #endif /* RTC_CR_TAMPOE */
01339
01340 #if defined(RTC_CR_TAMPALRM_PU)
01341 /**
01342   * @brief  Enable internal pull-up in output mode.
01343   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01344   * @param  RTCx RTC Instance
01345   * @retval None
01346   */
01347 __STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
01348 {
01349   SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01350 }
01351
01352 /**
01353   * @brief  Disable internal pull-up in output mode.
01354   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01355   * @param  RTCx RTC Instance
01356   * @retval None
01357   */
01358 __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
01359 {
01360   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01361 }
01362
01363 /**
01364   * @brief  Check if internal pull-up in output mode is enabled or not.
01365   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_IsAlarmPullUpEnabled
01366   * @param  RTCx RTC Instance
01367   * @retval State of bit (1 or 0).
01368   */
01369 __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
01370 {
01371   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);
01372 }
01373 #endif /* RTC_CR_TAMPALRM_PU */
01374
01375 #if defined(RTC_CR_OUT2EN)
01376 /**
01377   * @brief  Enable RTC_OUT2 output
01378   * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
01379   *       and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
01380   * @note RTC_OUT2 isn't available ins VBAT mode.
01381   * @rmtoll RTC_CR           OUT2EN       LL_RTC_EnableOutput2
01382   * @param  RTCx RTC Instance
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
01386 {
01387   SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
01388 }
01389
01390 /**
01391   * @brief  Disable RTC_OUT2 output
01392   * @rmtoll RTC_CR           OUT2EN       LL_RTC_DisableOutput2
01393   * @param  RTCx RTC Instance
01394   * @retval None
01395   */
01396 __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
01397 {
01398   CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
01399 }
01400
01401 /**
01402   * @brief  Check if RTC_OUT2 output is enabled or not.
01403   * @rmtoll RTC_CR           OUT2EN       LL_RTC_IsOutput2Enabled
01404   * @param  RTCx RTC Instance
01405   * @retval State of bit (1 or 0).
01406   */
01407 __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
01408 {
01409   return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);
01410 }
01411
01412 #endif /* RTC_CR_OUT2EN */
01413
01414 #if defined(RTC_OR_OUT_RMP)
01415 /**
01416   * @brief  Enable RTC_OUT remap
01417   * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
01418   * @param  RTCx RTC Instance
01419   * @retval None
01420   */
01421 __STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
01422 {
01423   SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01424 }
01425
01426 /**
01427   * @brief  Disable RTC_OUT remap
01428   * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
01429   * @param  RTCx RTC Instance
01430   * @retval None
01431   */
01432 __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
01433 {
01434   CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01435 }
01436 #endif /* RTC_OR_OUT_RMP */
01437
01438 /**
01439   * @}
01440   */
01441
01442 /** @defgroup RTC_LL_EF_Time Time
01443   * @{
01444   */
01445
01446 /**
01447   * @brief  Set time format (AM/24-hour or PM notation)
01448   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01449   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01450   * @rmtoll RTC_TR           PM            LL_RTC_TIME_SetFormat
01451   * @param  RTCx RTC Instance
01452   * @param  TimeFormat This parameter can be one of the following values:
01453   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01454   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01455   * @retval None
01456   */
01457 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01458 {
01459   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01460 }
01461
01462 /**
01463   * @brief  Get time format (AM or PM notation)
01464   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01465   *       before reading this bit
01466   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01467   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01468   * @rmtoll RTC_TR           PM            LL_RTC_TIME_GetFormat
01469   * @param  RTCx RTC Instance
01470   * @retval Returned value can be one of the following values:
01471   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01472   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01473   */
01474 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01475 {
01476   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01477 }
01478
01479 /**
01480   * @brief  Set Hours in BCD format
01481   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01482   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01483   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01484   * @rmtoll RTC_TR           HT            LL_RTC_TIME_SetHour
01485   *         RTC_TR           HU            LL_RTC_TIME_SetHour
01486   * @param  RTCx RTC Instance
01487   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01491 {
01492   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01493              (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
01494 }
01495
01496 /**
01497   * @brief  Get Hours in BCD format
01498   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01499   *       before reading this bit
01500   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01501   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01502   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01503   *       Binary format
01504   * @rmtoll RTC_TR           HT            LL_RTC_TIME_GetHour
01505   *         RTC_TR           HU            LL_RTC_TIME_GetHour
01506   * @param  RTCx RTC Instance
01507   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01508   */
01509 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01510 {
01511   return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
01512 }
01513
01514 /**
01515   * @brief  Set Minutes in BCD format
01516   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01517   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01518   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01519   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_SetMinute
01520   *         RTC_TR           MNU           LL_RTC_TIME_SetMinute
01521   * @param  RTCx RTC Instance
01522   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01523   * @retval None
01524   */
01525 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01526 {
01527   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01528              (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
01529 }
01530
01531 /**
01532   * @brief  Get Minutes in BCD format
01533   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01534   *       before reading this bit
01535   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01536   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01537   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01538   *       to Binary format
01539   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_GetMinute
01540   *         RTC_TR           MNU           LL_RTC_TIME_GetMinute
01541   * @param  RTCx RTC Instance
01542   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01543   */
01544 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01545 {
01546   return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
01547 }
01548
01549 /**
01550   * @brief  Set Seconds in BCD format
01551   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01552   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01553   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01554   * @rmtoll RTC_TR           ST            LL_RTC_TIME_SetSecond
01555   *         RTC_TR           SU            LL_RTC_TIME_SetSecond
01556   * @param  RTCx RTC Instance
01557   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01561 {
01562   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01563              (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
01564 }
01565
01566 /**
01567   * @brief  Get Seconds in BCD format
01568   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01569   *       before reading this bit
01570   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01571   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01572   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01573   *       to Binary format
01574   * @rmtoll RTC_TR           ST            LL_RTC_TIME_GetSecond
01575   *         RTC_TR           SU            LL_RTC_TIME_GetSecond
01576   * @param  RTCx RTC Instance
01577   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01578   */
01579 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01580 {
01581   return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
01582 }
01583
01584 /**
01585   * @brief  Set time (hour, minute and second) in BCD format
01586   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01587   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01588   * @note TimeFormat and Hours should follow the same format
01589   * @rmtoll RTC_TR           PM            LL_RTC_TIME_Config
01590   *         RTC_TR           HT            LL_RTC_TIME_Config
01591   *         RTC_TR           HU            LL_RTC_TIME_Config
01592   *         RTC_TR           MNT           LL_RTC_TIME_Config
01593   *         RTC_TR           MNU           LL_RTC_TIME_Config
01594   *         RTC_TR           ST            LL_RTC_TIME_Config
01595   *         RTC_TR           SU            LL_RTC_TIME_Config
01596   * @param  RTCx RTC Instance
01597   * @param  Format12_24 This parameter can be one of the following values:
01598   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01599   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01600   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01601   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01602   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01603   * @retval None
01604   */
01605 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01606 {
01607   register uint32_t temp;
01608
01609   temp = Format12_24                                                                                    | \
01610          (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
01611          (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
01612          (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
01613   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01614 }
01615
01616 /**
01617   * @brief  Get time (hour, minute and second) in BCD format
01618   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01619   *       before reading this bit
01620   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01621   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01622   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01623   *       are available to get independently each parameter.
01624   * @rmtoll RTC_TR           HT            LL_RTC_TIME_Get
01625   *         RTC_TR           HU            LL_RTC_TIME_Get
01626   *         RTC_TR           MNT           LL_RTC_TIME_Get
01627   *         RTC_TR           MNU           LL_RTC_TIME_Get
01628   *         RTC_TR           ST            LL_RTC_TIME_Get
01629   *         RTC_TR           SU            LL_RTC_TIME_Get
01630   * @param  RTCx RTC Instance
01631   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01632   */
01633 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01634 {
01635   register uint32_t temp;
01636
01637   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
01638   return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR)       |  \
01639                     (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
01640                     ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
01641 }
01642
01643 /**
01644   * @brief  Memorize whether the daylight saving time change has been performed
01645   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01646   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_EnableDayLightStore
01647   * @param  RTCx RTC Instance
01648   * @retval None
01649   */
01650 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01651 {
01652   SET_BIT(RTCx->CR, RTC_CR_BKP);
01653 }
01654
01655 /**
01656   * @brief  Disable memorization whether the daylight saving time change has been performed.
01657   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01658   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_DisableDayLightStore
01659   * @param  RTCx RTC Instance
01660   * @retval None
01661   */
01662 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01663 {
01664   CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
01665 }
01666
01667 /**
01668   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01669   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
01670   * @param  RTCx RTC Instance
01671   * @retval State of bit (1 or 0).
01672   */
01673 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01674 {
01675   return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
01676 }
01677
01678 /**
01679   * @brief  Subtract 1 hour (winter time change)
01680   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01681   * @rmtoll RTC_CR           SUB1H         LL_RTC_TIME_DecHour
01682   * @param  RTCx RTC Instance
01683   * @retval None
01684   */
01685 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01686 {
01687   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01688 }
01689
01690 /**
01691   * @brief  Add 1 hour (summer time change)
01692   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01693   * @rmtoll RTC_CR           ADD1H         LL_RTC_TIME_IncHour
01694   * @param  RTCx RTC Instance
01695   * @retval None
01696   */
01697 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01698 {
01699   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01700 }
01701
01702 /**
01703   * @brief  Get Sub second value in the synchronous prescaler counter.
01704   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01705   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01706   *        SubSeconds value in second fraction ratio with time unit following
01707   *        generic formula:
01708   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01709   *        This conversion can be performed only if no shift operation is pending
01710   *        (ie. SHFP=0) when PREDIV_S >= SS.
01711   * @rmtoll RTC_SSR          SS            LL_RTC_TIME_GetSubSecond
01712   * @param  RTCx RTC Instance
01713   * @retval Sub second value (number between 0 and 65535)
01714   */
01715 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01716 {
01717   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01718 }
01719
01720 /**
01721   * @brief  Synchronize to a remote clock with a high degree of precision.
01722   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01723   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01724   * @note   When REFCKON is set, firmware must not write to Shift control register.
01725   * @rmtoll RTC_SHIFTR       ADD1S         LL_RTC_TIME_Synchronize
01726   *         RTC_SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01727   * @param  RTCx RTC Instance
01728   * @param  ShiftSecond This parameter can be one of the following values:
01729   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01730   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01731   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01732   * @retval None
01733   */
01734 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01735 {
01736   WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
01737 }
01738
01739 /**
01740   * @}
01741   */
01742
01743 /** @defgroup RTC_LL_EF_Date Date
01744   * @{
01745   */
01746
01747 /**
01748   * @brief  Set Year in BCD format
01749   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01750   * @rmtoll RTC_DR           YT            LL_RTC_DATE_SetYear
01751   *         RTC_DR           YU            LL_RTC_DATE_SetYear
01752   * @param  RTCx RTC Instance
01753   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01757 {
01758   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01759              (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
01760 }
01761
01762 /**
01763   * @brief  Get Year in BCD format
01764   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01765   *       before reading this bit
01766   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01767   * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear
01768   *         RTC_DR           YU            LL_RTC_DATE_GetYear
01769   * @param  RTCx RTC Instance
01770   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01771   */
01772 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01773 {
01774   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
01775 }
01776
01777 /**
01778   * @brief  Set Week day
01779   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_SetWeekDay
01780   * @param  RTCx RTC Instance
01781   * @param  WeekDay This parameter can be one of the following values:
01782   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01783   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01784   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01785   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01786   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01787   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01788   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01789   * @retval None
01790   */
01791 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01792 {
01793   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
01794 }
01795
01796 /**
01797   * @brief  Get Week day
01798   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01799   *       before reading this bit
01800   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay
01801   * @param  RTCx RTC Instance
01802   * @retval Returned value can be one of the following values:
01803   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01804   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01805   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01806   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01807   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01808   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01809   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01810   */
01811 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01812 {
01813   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
01814 }
01815
01816 /**
01817   * @brief  Set Month in BCD format
01818   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01819   * @rmtoll RTC_DR           MT            LL_RTC_DATE_SetMonth
01820   *         RTC_DR           MU            LL_RTC_DATE_SetMonth
01821   * @param  RTCx RTC Instance
01822   * @param  Month This parameter can be one of the following values:
01823   *         @arg @ref LL_RTC_MONTH_JANUARY
01824   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01825   *         @arg @ref LL_RTC_MONTH_MARCH
01826   *         @arg @ref LL_RTC_MONTH_APRIL
01827   *         @arg @ref LL_RTC_MONTH_MAY
01828   *         @arg @ref LL_RTC_MONTH_JUNE
01829   *         @arg @ref LL_RTC_MONTH_JULY
01830   *         @arg @ref LL_RTC_MONTH_AUGUST
01831   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01832   *         @arg @ref LL_RTC_MONTH_OCTOBER
01833   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01834   *         @arg @ref LL_RTC_MONTH_DECEMBER
01835   * @retval None
01836   */
01837 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01838 {
01839   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01840              (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
01841 }
01842
01843 /**
01844   * @brief  Get Month in BCD format
01845   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01846   *       before reading this bit
01847   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01848   * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth
01849   *         RTC_DR           MU            LL_RTC_DATE_GetMonth
01850   * @param  RTCx RTC Instance
01851   * @retval Returned value can be one of the following values:
01852   *         @arg @ref LL_RTC_MONTH_JANUARY
01853   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01854   *         @arg @ref LL_RTC_MONTH_MARCH
01855   *         @arg @ref LL_RTC_MONTH_APRIL
01856   *         @arg @ref LL_RTC_MONTH_MAY
01857   *         @arg @ref LL_RTC_MONTH_JUNE
01858   *         @arg @ref LL_RTC_MONTH_JULY
01859   *         @arg @ref LL_RTC_MONTH_AUGUST
01860   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01861   *         @arg @ref LL_RTC_MONTH_OCTOBER
01862   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01863   *         @arg @ref LL_RTC_MONTH_DECEMBER
01864   */
01865 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01866 {
01867   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
01868 }
01869
01870 /**
01871   * @brief  Set Day in BCD format
01872   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01873   * @rmtoll RTC_DR           DT            LL_RTC_DATE_SetDay
01874   *         RTC_DR           DU            LL_RTC_DATE_SetDay
01875   * @param  RTCx RTC Instance
01876   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01880 {
01881   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01882              (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
01883 }
01884
01885 /**
01886   * @brief  Get Day in BCD format
01887   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01888   *       before reading this bit
01889   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01890   * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay
01891   *         RTC_DR           DU            LL_RTC_DATE_GetDay
01892   * @param  RTCx RTC Instance
01893   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01894   */
01895 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01896 {
01897   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
01898 }
01899
01900 /**
01901   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01902   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Config
01903   *         RTC_DR           MT            LL_RTC_DATE_Config
01904   *         RTC_DR           MU            LL_RTC_DATE_Config
01905   *         RTC_DR           DT            LL_RTC_DATE_Config
01906   *         RTC_DR           DU            LL_RTC_DATE_Config
01907   *         RTC_DR           YT            LL_RTC_DATE_Config
01908   *         RTC_DR           YU            LL_RTC_DATE_Config
01909   * @param  RTCx RTC Instance
01910   * @param  WeekDay This parameter can be one of the following values:
01911   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01912   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01913   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01914   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01915   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01916   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01917   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01918   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01919   * @param  Month This parameter can be one of the following values:
01920   *         @arg @ref LL_RTC_MONTH_JANUARY
01921   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01922   *         @arg @ref LL_RTC_MONTH_MARCH
01923   *         @arg @ref LL_RTC_MONTH_APRIL
01924   *         @arg @ref LL_RTC_MONTH_MAY
01925   *         @arg @ref LL_RTC_MONTH_JUNE
01926   *         @arg @ref LL_RTC_MONTH_JULY
01927   *         @arg @ref LL_RTC_MONTH_AUGUST
01928   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01929   *         @arg @ref LL_RTC_MONTH_OCTOBER
01930   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01931   *         @arg @ref LL_RTC_MONTH_DECEMBER
01932   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01933   * @retval None
01934   */
01935 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
01936 {
01937   register uint32_t temp;
01938
01939   temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
01940          (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
01941          (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
01942          (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
01943
01944   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01945 }
01946
01947 /**
01948   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01949   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01950   *       before reading this bit
01951   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01952   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01953   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Get
01954   *         RTC_DR           MT            LL_RTC_DATE_Get
01955   *         RTC_DR           MU            LL_RTC_DATE_Get
01956   *         RTC_DR           DT            LL_RTC_DATE_Get
01957   *         RTC_DR           DU            LL_RTC_DATE_Get
01958   *         RTC_DR           YT            LL_RTC_DATE_Get
01959   *         RTC_DR           YU            LL_RTC_DATE_Get
01960   * @param  RTCx RTC Instance
01961   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01962   */
01963 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01964 {
01965   register uint32_t temp;
01966
01967   temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
01968   return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
01969                     (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY)   | \
01970                     (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
01971                     ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
01972 }
01973
01974 /**
01975   * @}
01976   */
01977
01978 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01979   * @{
01980   */
01981
01982 /**
01983   * @brief  Enable Alarm A
01984   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01985   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Enable
01986   * @param  RTCx RTC Instance
01987   * @retval None
01988   */
01989 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01990 {
01991   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01992 }
01993
01994 /**
01995   * @brief  Disable Alarm A
01996   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01997   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Disable
01998   * @param  RTCx RTC Instance
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
02002 {
02003   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
02004 }
02005
02006 /**
02007   * @brief  Specify the Alarm A masks.
02008   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_SetMask
02009   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_SetMask
02010   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_SetMask
02011   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_SetMask
02012   * @param  RTCx RTC Instance
02013   * @param  Mask This parameter can be a combination of the following values:
02014   *         @arg @ref LL_RTC_ALMA_MASK_NONE
02015   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
02016   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
02017   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
02018   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
02019   *         @arg @ref LL_RTC_ALMA_MASK_ALL
02020   * @retval None
02021   */
02022 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02023 {
02024   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
02025 }
02026
02027 /**
02028   * @brief  Get the Alarm A masks.
02029   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_GetMask
02030   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_GetMask
02031   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_GetMask
02032   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_GetMask
02033   * @param  RTCx RTC Instance
02034   * @retval Returned value can be can be a combination of the following values:
02035   *         @arg @ref LL_RTC_ALMA_MASK_NONE
02036   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
02037   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
02038   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
02039   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
02040   *         @arg @ref LL_RTC_ALMA_MASK_ALL
02041   */
02042 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
02043 {
02044   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
02045 }
02046
02047 /**
02048   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02049   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
02050   * @param  RTCx RTC Instance
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
02054 {
02055   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
02056 }
02057
02058 /**
02059   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
02060   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
02061   * @param  RTCx RTC Instance
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
02065 {
02066   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
02067 }
02068
02069 /**
02070   * @brief  Set ALARM A Day in BCD format
02071   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02072   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_SetDay
02073   *         RTC_ALRMAR       DU            LL_RTC_ALMA_SetDay
02074   * @param  RTCx RTC Instance
02075   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02076   * @retval None
02077   */
02078 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02079 {
02080   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
02081              (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
02082 }
02083
02084 /**
02085   * @brief  Get ALARM A Day in BCD format
02086   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02087   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_GetDay
02088   *         RTC_ALRMAR       DU            LL_RTC_ALMA_GetDay
02089   * @param  RTCx RTC Instance
02090   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02091   */
02092 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
02093 {
02094   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
02095 }
02096
02097 /**
02098   * @brief  Set ALARM A Weekday
02099   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
02100   * @param  RTCx RTC Instance
02101   * @param  WeekDay This parameter can be one of the following values:
02102   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02103   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02104   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02105   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02106   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02107   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02108   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02109   * @retval None
02110   */
02111 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02112 {
02113   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
02114 }
02115
02116 /**
02117   * @brief  Get ALARM A Weekday
02118   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
02119   * @param  RTCx RTC Instance
02120   * @retval Returned value can be one of the following values:
02121   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02122   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02123   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02124   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02125   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02126   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02127   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02128   */
02129 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
02130 {
02131   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
02132 }
02133
02134 /**
02135   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
02136   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
02137   * @param  RTCx RTC Instance
02138   * @param  TimeFormat This parameter can be one of the following values:
02139   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
02140   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
02141   * @retval None
02142   */
02143 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02144 {
02145   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
02146 }
02147
02148 /**
02149   * @brief  Get Alarm A time format (AM or PM notation)
02150   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
02151   * @param  RTCx RTC Instance
02152   * @retval Returned value can be one of the following values:
02153   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
02154   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
02155   */
02156 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
02157 {
02158   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
02159 }
02160
02161 /**
02162   * @brief  Set ALARM A Hours in BCD format
02163   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02164   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_SetHour
02165   *         RTC_ALRMAR       HU            LL_RTC_ALMA_SetHour
02166   * @param  RTCx RTC Instance
02167   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02168   * @retval None
02169   */
02170 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02171 {
02172   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
02173              (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
02174 }
02175
02176 /**
02177   * @brief  Get ALARM A Hours in BCD format
02178   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02179   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetHour
02180   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetHour
02181   * @param  RTCx RTC Instance
02182   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02183   */
02184 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
02185 {
02186   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
02187 }
02188
02189 /**
02190   * @brief  Set ALARM A Minutes in BCD format
02191   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02192   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_SetMinute
02193   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_SetMinute
02194   * @param  RTCx RTC Instance
02195   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02196   * @retval None
02197   */
02198 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02199 {
02200   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
02201              (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
02202 }
02203
02204 /**
02205   * @brief  Get ALARM A Minutes in BCD format
02206   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02207   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_GetMinute
02208   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetMinute
02209   * @param  RTCx RTC Instance
02210   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02211   */
02212 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
02213 {
02214   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
02215 }
02216
02217 /**
02218   * @brief  Set ALARM A Seconds in BCD format
02219   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02220   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_SetSecond
02221   *         RTC_ALRMAR       SU            LL_RTC_ALMA_SetSecond
02222   * @param  RTCx RTC Instance
02223   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02224   * @retval None
02225   */
02226 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02227 {
02228   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
02229              (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
02230 }
02231
02232 /**
02233   * @brief  Get ALARM A Seconds in BCD format
02234   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02235   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_GetSecond
02236   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetSecond
02237   * @param  RTCx RTC Instance
02238   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02239   */
02240 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
02241 {
02242   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
02243 }
02244
02245 /**
02246   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
02247   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_ConfigTime
02248   *         RTC_ALRMAR       HT            LL_RTC_ALMA_ConfigTime
02249   *         RTC_ALRMAR       HU            LL_RTC_ALMA_ConfigTime
02250   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_ConfigTime
02251   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_ConfigTime
02252   *         RTC_ALRMAR       ST            LL_RTC_ALMA_ConfigTime
02253   *         RTC_ALRMAR       SU            LL_RTC_ALMA_ConfigTime
02254   * @param  RTCx RTC Instance
02255   * @param  Format12_24 This parameter can be one of the following values:
02256   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
02257   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
02258   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02259   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02260   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02261   * @retval None
02262   */
02263 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02264 {
02265   register uint32_t temp;
02266
02267   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
02268          (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
02269          (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
02270
02271   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
02272 }
02273
02274 /**
02275   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02276   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02277   * are available to get independently each parameter.
02278   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetTime
02279   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetTime
02280   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_GetTime
02281   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetTime
02282   *         RTC_ALRMAR       ST            LL_RTC_ALMA_GetTime
02283   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetTime
02284   * @param  RTCx RTC Instance
02285   * @retval Combination of hours, minutes and seconds.
02286   */
02287 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
02288 {
02289   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
02290 }
02291
02292 /**
02293   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
02294   * @note This register can be written only when ALRAE is reset in RTC_CR register,
02295   *       or in initialization mode.
02296   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
02297   * @param  RTCx RTC Instance
02298   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02299   * @retval None
02300   */
02301 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02302 {
02303   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
02304 }
02305
02306 /**
02307   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
02308   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
02309   * @param  RTCx RTC Instance
02310   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02311   */
02312 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
02313 {
02314   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
02315 }
02316
02317 /**
02318   * @brief  Set Alarm A Sub seconds value
02319   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
02320   * @param  RTCx RTC Instance
02321   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02322   * @retval None
02323   */
02324 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02325 {
02326   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
02327 }
02328
02329 /**
02330   * @brief  Get Alarm A Sub seconds value
02331   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
02332   * @param  RTCx RTC Instance
02333   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02334   */
02335 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
02336 {
02337   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
02338 }
02339
02340 /**
02341   * @}
02342   */
02343
02344 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02345   * @{
02346   */
02347
02348 /**
02349   * @brief  Enable Alarm B
02350   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02351   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Enable
02352   * @param  RTCx RTC Instance
02353   * @retval None
02354   */
02355 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02356 {
02357   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02358 }
02359
02360 /**
02361   * @brief  Disable Alarm B
02362   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02363   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Disable
02364   * @param  RTCx RTC Instance
02365   * @retval None
02366   */
02367 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02368 {
02369   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02370 }
02371
02372 /**
02373   * @brief  Specify the Alarm B masks.
02374   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_SetMask
02375   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_SetMask
02376   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_SetMask
02377   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02378   * @param  RTCx RTC Instance
02379   * @param  Mask This parameter can be a combination of the following values:
02380   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02381   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02382   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02383   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02384   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02385   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02386   * @retval None
02387   */
02388 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02389 {
02390   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02391 }
02392
02393 /**
02394   * @brief  Get the Alarm B masks.
02395   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_GetMask
02396   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_GetMask
02397   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_GetMask
02398   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02399   * @param  RTCx RTC Instance
02400   * @retval Returned value can be can be a combination of the following values:
02401   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02402   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02403   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02404   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02405   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02406   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02407   */
02408 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02409 {
02410   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02411 }
02412
02413 /**
02414   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02415   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02416   * @param  RTCx RTC Instance
02417   * @retval None
02418   */
02419 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02420 {
02421   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02422 }
02423
02424 /**
02425   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02426   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02427   * @param  RTCx RTC Instance
02428   * @retval None
02429   */
02430 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02431 {
02432   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02433 }
02434
02435 /**
02436   * @brief  Set ALARM B Day in BCD format
02437   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02438   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_SetDay
02439   *         RTC_ALRMBR       DU            LL_RTC_ALMB_SetDay
02440   * @param  RTCx RTC Instance
02441   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02442   * @retval None
02443   */
02444 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02445 {
02446   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02447              (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
02448 }
02449
02450 /**
02451   * @brief  Get ALARM B Day in BCD format
02452   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02453   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_GetDay
02454   *         RTC_ALRMBR       DU            LL_RTC_ALMB_GetDay
02455   * @param  RTCx RTC Instance
02456   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02457   */
02458 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02459 {
02460   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
02461 }
02462
02463 /**
02464   * @brief  Set ALARM B Weekday
02465   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02466   * @param  RTCx RTC Instance
02467   * @param  WeekDay This parameter can be one of the following values:
02468   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02469   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02470   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02471   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02472   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02473   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02474   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02475   * @retval None
02476   */
02477 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02478 {
02479   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
02480 }
02481
02482 /**
02483   * @brief  Get ALARM B Weekday
02484   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02485   * @param  RTCx RTC Instance
02486   * @retval Returned value can be one of the following values:
02487   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02488   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02489   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02490   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02491   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02492   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02493   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02494   */
02495 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02496 {
02497   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
02498 }
02499
02500 /**
02501   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02502   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02503   * @param  RTCx RTC Instance
02504   * @param  TimeFormat This parameter can be one of the following values:
02505   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02506   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02507   * @retval None
02508   */
02509 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02510 {
02511   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02512 }
02513
02514 /**
02515   * @brief  Get ALARM B time format (AM or PM notation)
02516   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02517   * @param  RTCx RTC Instance
02518   * @retval Returned value can be one of the following values:
02519   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02520   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02521   */
02522 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02523 {
02524   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02525 }
02526
02527 /**
02528   * @brief  Set ALARM B Hours in BCD format
02529   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02530   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_SetHour
02531   *         RTC_ALRMBR       HU            LL_RTC_ALMB_SetHour
02532   * @param  RTCx RTC Instance
02533   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02534   * @retval None
02535   */
02536 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02537 {
02538   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02539              (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
02540 }
02541
02542 /**
02543   * @brief  Get ALARM B Hours in BCD format
02544   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02545   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetHour
02546   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetHour
02547   * @param  RTCx RTC Instance
02548   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02549   */
02550 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02551 {
02552   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
02553 }
02554
02555 /**
02556   * @brief  Set ALARM B Minutes in BCD format
02557   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02558   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_SetMinute
02559   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02560   * @param  RTCx RTC Instance
02561   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02562   * @retval None
02563   */
02564 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02565 {
02566   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02567              (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
02568 }
02569
02570 /**
02571   * @brief  Get ALARM B Minutes in BCD format
02572   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02573   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_GetMinute
02574   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02575   * @param  RTCx RTC Instance
02576   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02577   */
02578 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02579 {
02580   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
02581 }
02582
02583 /**
02584   * @brief  Set ALARM B Seconds in BCD format
02585   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02586   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_SetSecond
02587   *         RTC_ALRMBR       SU            LL_RTC_ALMB_SetSecond
02588   * @param  RTCx RTC Instance
02589   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02590   * @retval None
02591   */
02592 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02593 {
02594   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02595              (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
02596 }
02597
02598 /**
02599   * @brief  Get ALARM B Seconds in BCD format
02600   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02601   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_GetSecond
02602   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetSecond
02603   * @param  RTCx RTC Instance
02604   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02605   */
02606 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02607 {
02608   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
02609 }
02610
02611 /**
02612   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02613   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_ConfigTime
02614   *         RTC_ALRMBR       HT            LL_RTC_ALMB_ConfigTime
02615   *         RTC_ALRMBR       HU            LL_RTC_ALMB_ConfigTime
02616   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_ConfigTime
02617   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_ConfigTime
02618   *         RTC_ALRMBR       ST            LL_RTC_ALMB_ConfigTime
02619   *         RTC_ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02620   * @param  RTCx RTC Instance
02621   * @param  Format12_24 This parameter can be one of the following values:
02622   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02623   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02624   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02625   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02626   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02627   * @retval None
02628   */
02629 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02630 {
02631   register uint32_t temp;
02632
02633   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
02634          (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
02635          (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
02636
02637   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
02638 }
02639
02640 /**
02641   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02642   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02643   * are available to get independently each parameter.
02644   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetTime
02645   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetTime
02646   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_GetTime
02647   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetTime
02648   *         RTC_ALRMBR       ST            LL_RTC_ALMB_GetTime
02649   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetTime
02650   * @param  RTCx RTC Instance
02651   * @retval Combination of hours, minutes and seconds.
02652   */
02653 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02654 {
02655   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02656 }
02657
02658 /**
02659   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02660   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02661   *       or in initialization mode.
02662   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02663   * @param  RTCx RTC Instance
02664   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02665   * @retval None
02666   */
02667 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02668 {
02669   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
02670 }
02671
02672 /**
02673   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02674   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02675   * @param  RTCx RTC Instance
02676   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02677   */
02678 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02679 {
02680   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
02681 }
02682
02683 /**
02684   * @brief  Set Alarm B Sub seconds value
02685   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02686   * @param  RTCx RTC Instance
02687   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02688   * @retval None
02689   */
02690 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02691 {
02692   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02693 }
02694
02695 /**
02696   * @brief  Get Alarm B Sub seconds value
02697   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02698   * @param  RTCx RTC Instance
02699   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02700   */
02701 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02702 {
02703   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02704 }
02705
02706 /**
02707   * @}
02708   */
02709
02710 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02711   * @{
02712   */
02713
02714 /**
02715   * @brief  Enable internal event timestamp
02716   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02717   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_EnableInternalEvent
02718   * @param  RTCx RTC Instance
02719   * @retval None
02720   */
02721 __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
02722 {
02723   SET_BIT(RTCx->CR, RTC_CR_ITSE);
02724 }
02725
02726 /**
02727   * @brief  Disable internal event timestamp
02728   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02729   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_DisableInternalEvent
02730   * @param  RTCx RTC Instance
02731   * @retval None
02732   */
02733 __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
02734 {
02735   CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
02736 }
02737
02738 /**
02739   * @brief  Enable Timestamp
02740   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02741   * @rmtoll RTC_CR           TSE           LL_RTC_TS_Enable
02742   * @param  RTCx RTC Instance
02743   * @retval None
02744   */
02745 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02746 {
02747   SET_BIT(RTCx->CR, RTC_CR_TSE);
02748 }
02749
02750 /**
02751   * @brief  Disable Timestamp
02752   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02753   * @rmtoll RTC_CR           TSE           LL_RTC_TS_Disable
02754   * @param  RTCx RTC Instance
02755   * @retval None
02756   */
02757 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02758 {
02759   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02760 }
02761
02762 /**
02763   * @brief  Set Time-stamp event active edge
02764   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02765   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02766   * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_SetActiveEdge
02767   * @param  RTCx RTC Instance
02768   * @param  Edge This parameter can be one of the following values:
02769   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02770   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02771   * @retval None
02772   */
02773 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02774 {
02775   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02776 }
02777
02778 /**
02779   * @brief  Get Time-stamp event active edge
02780   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02781   * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_GetActiveEdge
02782   * @param  RTCx RTC Instance
02783   * @retval Returned value can be one of the following values:
02784   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02785   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02786   */
02787 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02788 {
02789   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02790 }
02791
02792 /**
02793   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02794   * @rmtoll RTC_TSTR         PM            LL_RTC_TS_GetTimeFormat
02795   * @param  RTCx RTC Instance
02796   * @retval Returned value can be one of the following values:
02797   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02798   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02799   */
02800 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02801 {
02802   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02803 }
02804
02805 /**
02806   * @brief  Get Timestamp Hours in BCD format
02807   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02808   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetHour
02809   *         RTC_TSTR         HU            LL_RTC_TS_GetHour
02810   * @param  RTCx RTC Instance
02811   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02812   */
02813 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02814 {
02815   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
02816 }
02817
02818 /**
02819   * @brief  Get Timestamp Minutes in BCD format
02820   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02821   * @rmtoll RTC_TSTR         MNT           LL_RTC_TS_GetMinute
02822   *         RTC_TSTR         MNU           LL_RTC_TS_GetMinute
02823   * @param  RTCx RTC Instance
02824   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02825   */
02826 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02827 {
02828   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
02829 }
02830
02831 /**
02832   * @brief  Get Timestamp Seconds in BCD format
02833   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02834   * @rmtoll RTC_TSTR         ST            LL_RTC_TS_GetSecond
02835   *         RTC_TSTR         SU            LL_RTC_TS_GetSecond
02836   * @param  RTCx RTC Instance
02837   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02838   */
02839 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02840 {
02841   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02842 }
02843
02844 /**
02845   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02846   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02847   * are available to get independently each parameter.
02848   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetTime
02849   *         RTC_TSTR         HU            LL_RTC_TS_GetTime
02850   *         RTC_TSTR         MNT           LL_RTC_TS_GetTime
02851   *         RTC_TSTR         MNU           LL_RTC_TS_GetTime
02852   *         RTC_TSTR         ST            LL_RTC_TS_GetTime
02853   *         RTC_TSTR         SU            LL_RTC_TS_GetTime
02854   * @param  RTCx RTC Instance
02855   * @retval Combination of hours, minutes and seconds.
02856   */
02857 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02858 {
02859   return (uint32_t)(READ_BIT(RTCx->TSTR,
02860                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02861 }
02862
02863 /**
02864   * @brief  Get Timestamp Week day
02865   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetWeekDay
02866   * @param  RTCx RTC Instance
02867   * @retval Returned value can be one of the following values:
02868   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02869   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02870   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02871   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02872   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02873   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02874   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02875   */
02876 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02877 {
02878   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
02879 }
02880
02881 /**
02882   * @brief  Get Timestamp Month in BCD format
02883   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02884   * @rmtoll RTC_TSDR         MT            LL_RTC_TS_GetMonth
02885   *         RTC_TSDR         MU            LL_RTC_TS_GetMonth
02886   * @param  RTCx RTC Instance
02887   * @retval Returned value can be one of the following values:
02888   *         @arg @ref LL_RTC_MONTH_JANUARY
02889   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02890   *         @arg @ref LL_RTC_MONTH_MARCH
02891   *         @arg @ref LL_RTC_MONTH_APRIL
02892   *         @arg @ref LL_RTC_MONTH_MAY
02893   *         @arg @ref LL_RTC_MONTH_JUNE
02894   *         @arg @ref LL_RTC_MONTH_JULY
02895   *         @arg @ref LL_RTC_MONTH_AUGUST
02896   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02897   *         @arg @ref LL_RTC_MONTH_OCTOBER
02898   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02899   *         @arg @ref LL_RTC_MONTH_DECEMBER
02900   */
02901 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02902 {
02903   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
02904 }
02905
02906 /**
02907   * @brief  Get Timestamp Day in BCD format
02908   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02909   * @rmtoll RTC_TSDR         DT            LL_RTC_TS_GetDay
02910   *         RTC_TSDR         DU            LL_RTC_TS_GetDay
02911   * @param  RTCx RTC Instance
02912   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02913   */
02914 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02915 {
02916   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02917 }
02918
02919 /**
02920   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02921   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02922   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02923   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetDate
02924   *         RTC_TSDR         MT            LL_RTC_TS_GetDate
02925   *         RTC_TSDR         MU            LL_RTC_TS_GetDate
02926   *         RTC_TSDR         DT            LL_RTC_TS_GetDate
02927   *         RTC_TSDR         DU            LL_RTC_TS_GetDate
02928   * @param  RTCx RTC Instance
02929   * @retval Combination of Weekday, Day and Month
02930   */
02931 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02932 {
02933   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02934 }
02935
02936 /**
02937   * @brief  Get time-stamp sub second value
02938   * @rmtoll RTC_TSSSR         SS            LL_RTC_TS_GetSubSecond
02939   * @param  RTCx RTC Instance
02940   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02941   */
02942 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02943 {
02944   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02945 }
02946
02947 /**
02948   * @}
02949   */
02950
02951 /** @defgroup RTC_LL_EF_Tamper_Timestamp Time-stamp on Tamper
02952   * @{
02953   */
02954
02955 #if defined(RTC_TAMPCR_TAMPTS)
02956 /**
02957   * @brief  Activate timestamp on tamper detection event
02958   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
02959   * @param  RTCx RTC Instance
02960   * @retval None
02961   */
02962 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02963 {
02964   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02965 }
02966
02967 /**
02968   * @brief  Disable timestamp on tamper detection event
02969   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper
02970   * @param  RTCx RTC Instance
02971   * @retval None
02972   */
02973 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02974 {
02975   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02976 }
02977 #endif /* RTC_TAMPCR_TAMPTS */
02978
02979 #if defined(RTC_CR_TAMPTS)
02980 /**
02981   * @brief  Activate timestamp on tamper detection event
02982   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
02983   * @param  RTCx RTC Instance
02984   * @retval None
02985   */
02986
02987 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02988 {
02989   SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
02990 }
02991
02992 /**
02993   * @brief  Disable timestamp on tamper detection event
02994   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper
02995   * @param  RTCx RTC Instance
02996   * @retval None
02997   */
02998 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02999 {
03000   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
03001 }
03002 #endif /* RTC_CR_TAMPTS */
03003
03004 /**
03005   * @}
03006   */
03007
03008 /** @defgroup RTC_LL_EF_Tamper Tamper
03009   * @{
03010   */
03011
03012 #if defined(RTC_TAMPCR_TAMP1E)
03013 /**
03014   * @brief  Enable RTC_TAMPx input detection
03015   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable
03016   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable
03017   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
03018   * @param  RTCx RTC Instance
03019   * @param  Tamper This parameter can be a combination of the following values:
03020   *         @arg @ref LL_RTC_TAMPER_1
03021   *         @arg @ref LL_RTC_TAMPER_2
03022   *         @arg @ref LL_RTC_TAMPER_3
03023   *
03024   * @retval None
03025   */
03026 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
03027 {
03028   SET_BIT(RTCx->TAMPCR, Tamper);
03029 }
03030
03031 /**
03032   * @brief  Clear RTC_TAMPx input detection
03033   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable
03034   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable
03035   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
03036   * @param  RTCx RTC Instance
03037   * @param  Tamper This parameter can be a combination of the following values:
03038   *         @arg @ref LL_RTC_TAMPER_1
03039   *         @arg @ref LL_RTC_TAMPER_2
03040   *         @arg @ref LL_RTC_TAMPER_3
03041   *
03042   * @retval None
03043   */
03044 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
03045 {
03046   CLEAR_BIT(RTCx->TAMPCR, Tamper);
03047 }
03048
03049 /**
03050   * @brief  Enable Tamper mask flag
03051   * @note Associated Tamper IT must not enabled when tamper mask is set.
03052   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask
03053   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask
03054   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
03055   * @param  RTCx RTC Instance
03056   * @param  Mask This parameter can be a combination of the following values:
03057   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
03058   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
03059   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
03060   *
03061   * @retval None
03062   */
03063 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
03064 {
03065   SET_BIT(RTCx->TAMPCR, Mask);
03066 }
03067
03068 /**
03069   * @brief  Disable Tamper mask flag
03070   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask
03071   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask
03072   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
03073   * @param  RTCx RTC Instance
03074   * @param  Mask This parameter can be a combination of the following values:
03075   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
03076   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
03077   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
03078   *
03079   * @retval None
03080   */
03081 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
03082 {
03083   CLEAR_BIT(RTCx->TAMPCR, Mask);
03084 }
03085
03086 /**
03087   * @brief  Enable backup register erase after Tamper event detection
03088   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03089   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03090   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03091   * @param  RTCx RTC Instance
03092   * @param  Tamper This parameter can be a combination of the following values:
03093   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
03094   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
03095   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
03096   *
03097   * @retval None
03098   */
03099 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
03100 {
03101   CLEAR_BIT(RTCx->TAMPCR, Tamper);
03102 }
03103
03104 /**
03105   * @brief  Disable backup register erase after Tamper event detection
03106   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03107   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03108   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03109   * @param  RTCx RTC Instance
03110   * @param  Tamper This parameter can be a combination of the following values:
03111   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
03112   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
03113   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
03114   *
03115   * @retval None
03116   */
03117 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
03118 {
03119   SET_BIT(RTCx->TAMPCR, Tamper);
03120 }
03121 #endif /* RTC_TAMPCR_TAMP1E */
03122
03123 #if defined(RTC_TAMPCR_TAMPPUDIS)
03124 /**
03125   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
03126   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
03127   * @param  RTCx RTC Instance
03128   * @retval None
03129   */
03130 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
03131 {
03132   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
03133 }
03134
03135 /**
03136   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
03137   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
03138   * @param  RTCx RTC Instance
03139   * @retval None
03140   */
03141 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
03142 {
03143   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
03144 }
03145 #endif /* RTC_TAMPCR_TAMPPUDIS */
03146
03147 #if defined(RTC_TAMPCR_TAMPPRCH)
03148 /**
03149   * @brief  Set RTC_TAMPx precharge duration
03150   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
03151   * @param  RTCx RTC Instance
03152   * @param  Duration This parameter can be one of the following values:
03153   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
03154   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
03155   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
03156   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
03157   * @retval None
03158   */
03159 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
03160 {
03161   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
03162 }
03163
03164 /**
03165   * @brief  Get RTC_TAMPx precharge duration
03166   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
03167   * @param  RTCx RTC Instance
03168   * @retval Returned value can be one of the following values:
03169   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
03170   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
03171   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
03172   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
03173   */
03174 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
03175 {
03176   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
03177 }
03178 #endif /* RTC_TAMPCR_TAMPPRCH */
03179
03180 #if defined(RTC_TAMPCR_TAMPFLT)
03181 /**
03182   * @brief  Set RTC_TAMPx filter count
03183   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
03184   * @param  RTCx RTC Instance
03185   * @param  FilterCount This parameter can be one of the following values:
03186   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
03187   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
03188   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
03189   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
03190   * @retval None
03191   */
03192 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
03193 {
03194   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
03195 }
03196
03197 /**
03198   * @brief  Get RTC_TAMPx filter count
03199   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
03200   * @param  RTCx RTC Instance
03201   * @retval Returned value can be one of the following values:
03202   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
03203   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
03204   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
03205   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
03206   */
03207 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
03208 {
03209   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
03210 }
03211 #endif /* RTC_TAMPCR_TAMPFLT */
03212
03213 #if defined(RTC_TAMPCR_TAMPFREQ)
03214 /**
03215   * @brief  Set Tamper sampling frequency
03216   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
03217   * @param  RTCx RTC Instance
03218   * @param  SamplingFreq This parameter can be one of the following values:
03219   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
03220   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
03221   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
03222   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
03223   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
03224   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
03225   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
03226   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
03227   * @retval None
03228   */
03229 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
03230 {
03231   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
03232 }
03233
03234 /**
03235   * @brief  Get Tamper sampling frequency
03236   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
03237   * @param  RTCx RTC Instance
03238   * @retval Returned value can be one of the following values:
03239   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
03240   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
03241   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
03242   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
03243   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
03244   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
03245   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
03246   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
03247   */
03248 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
03249 {
03250   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
03251 }
03252 #endif /* RTC_TAMPCR_TAMPFREQ */
03253
03254 #if defined(RTC_TAMPCR_TAMP1E)
03255 /**
03256   * @brief  Enable Active level for Tamper input
03257   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel
03258   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel
03259   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
03260   * @param  RTCx RTC Instance
03261   * @param  Tamper This parameter can be a combination of the following values:
03262   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
03263   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
03264   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
03265   *
03266   * @retval None
03267   */
03268 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
03269 {
03270   SET_BIT(RTCx->TAMPCR, Tamper);
03271 }
03272
03273 /**
03274   * @brief  Disable Active level for Tamper input
03275   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel
03276   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel
03277   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
03278   * @param  RTCx RTC Instance
03279   * @param  Tamper This parameter can be a combination of the following values:
03280   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
03281   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
03282   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
03283   *
03284   * @retval None
03285   */
03286 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
03287 {
03288   CLEAR_BIT(RTCx->TAMPCR, Tamper);
03289 }
03290 #endif /* RTC_TAMPCR_TAMP1E */
03291
03292 #if defined(TAMP_CR1_TAMP1E)
03293 /**
03294   * @brief  Enable TAMPx input detection
03295   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable
03296   *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Enable
03297   *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Enable
03298   * @param  TAMPx TAMP Instance
03299   * @param  Tamper This parameter can be a combination of the following values:
03300   *         @arg @ref LL_RTC_TAMPER_1
03301   *         @arg @ref LL_RTC_TAMPER_2
03302   *         @arg @ref LL_RTC_TAMPER_3
03303   *
03304   * @retval None
03305   */
03306 __STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03307 {
03308   SET_BIT(TAMPx->CR1, Tamper);
03309 }
03310
03311 /**
03312   * @brief  Clear TAMPx input detection
03313   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Disable
03314   *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Disable
03315   *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Disable
03316   * @param  TAMPx TAMP Instance
03317   * @param  Tamper This parameter can be a combination of the following values:
03318   *         @arg @ref LL_RTC_TAMPER_1
03319   *         @arg @ref LL_RTC_TAMPER_2
03320   *         @arg @ref LL_RTC_TAMPER_3
03321   *
03322   * @retval None
03323   */
03324 __STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03325 {
03326   CLEAR_BIT(TAMPx->CR1, Tamper);
03327 }
03328 #endif /* TAMP_CR1_TAMP1E */
03329
03330 #if defined(TAMP_CR2_TAMP1MSK)
03331 /**
03332   * @brief  Enable Tamper mask flag
03333   * @note Associated Tamper IT must not enabled when tamper mask is set.
03334   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_EnableMask
03335   *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_EnableMask
03336   *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_EnableMask
03337   * @param  TAMPx TAMP Instance
03338   * @param  Mask This parameter can be a combination of the following values:
03339   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
03340   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
03341   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
03342   *
03343   * @retval None
03344   */
03345 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
03346 {
03347   SET_BIT(TAMPx->CR2, Mask);
03348 }
03349
03350 /**
03351   * @brief  Disable Tamper mask flag
03352   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_DisableMask
03353   *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_DisableMask
03354   *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_DisableMask
03355   * @param  TAMPx TAMP Instance
03356   * @param  Mask This parameter can be a combination of the following values:
03357   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
03358   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
03359   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
03360   *
03361   * @retval None
03362   */
03363 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
03364 {
03365   CLEAR_BIT(TAMPx->CR2, Mask);
03366 }
03367
03368 /**
03369   * @brief  Enable backup register erase after Tamper event detection
03370   * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03371   *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03372   *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
03373   * @param  TAMPx TAMP Instance
03374   * @param  Tamper This parameter can be a combination of the following values:
03375   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
03376   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
03377   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
03378   *
03379   * @retval None
03380   */
03381 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03382 {
03383   CLEAR_BIT(TAMPx->CR2, Tamper);
03384 }
03385
03386 /**
03387   * @brief  Disable backup register erase after Tamper event detection
03388   * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03389   *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03390   *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
03391   * @param  TAMPx TAMP Instance
03392   * @param  Tamper This parameter can be a combination of the following values:
03393   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
03394   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
03395   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
03396   *
03397   * @retval None
03398   */
03399 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03400 {
03401   SET_BIT(TAMPx->CR2, Tamper);
03402 }
03403
03404 /**
03405   * @brief  Enable Active level for Tamper input
03406   * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel
03407   *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel
03408   *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
03409   * @param  TAMPx TAMP Instance
03410   * @param  Tamper This parameter can be a combination of the following values:
03411   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
03412   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
03413   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
03414   *
03415   * @retval None
03416   */
03417 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03418 {
03419   SET_BIT(TAMPx->CR2, Tamper);
03420 }
03421
03422 /**
03423   * @brief  Disable Active level for Tamper input
03424   * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel
03425   *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel
03426   *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
03427   * @param  TAMPx TAMP Instance
03428   * @param  Tamper This parameter can be a combination of the following values:
03429   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
03430   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
03431   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
03432   *
03433   * @retval None
03434   */
03435 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
03436 {
03437   CLEAR_BIT(TAMPx->CR2, Tamper);
03438 }
03439 #endif /* TAMP_CR2_TAMP1MSK */
03440
03441 #if defined(TAMP_FLTCR_TAMPPUDIS)
03442 /**
03443   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
03444   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
03445   * @param  TAMPx TAMP Instance
03446   * @retval None
03447   */
03448 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx)
03449 {
03450   SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
03451 }
03452
03453 /**
03454   * @brief  Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling)
03455   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
03456   * @param  TAMPx TAMP Instance
03457   * @retval None
03458   */
03459 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx)
03460 {
03461   CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
03462 }
03463
03464 /**
03465   * @brief  Set RTC_TAMPx precharge duration
03466   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
03467   * @param  TAMPx TAMP Instance
03468   * @param  Duration This parameter can be one of the following values:
03469   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
03470   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
03471   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
03472   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration)
03476 {
03477   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
03478 }
03479
03480 /**
03481   * @brief  Get RTC_TAMPx precharge duration
03482   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
03483   * @param  TAMPx TAMP Instance
03484   * @retval Returned value can be one of the following values:
03485   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
03486   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
03487   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
03488   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
03489   */
03490 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx)
03491 {
03492   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH));
03493 }
03494
03495 /**
03496   * @brief  Set RTC_TAMPx filter count
03497   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
03498   * @param  TAMPx TAMP Instance
03499   * @param  FilterCount This parameter can be one of the following values:
03500   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
03501   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
03502   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
03503   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
03504   * @retval None
03505   */
03506 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount)
03507 {
03508   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
03509 }
03510
03511 /**
03512   * @brief  Get RTC_TAMPx filter count
03513   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
03514   * @param  TAMPx TAMP Instance
03515   * @retval Returned value can be one of the following values:
03516   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
03517   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
03518   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
03519   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
03520   */
03521 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx)
03522 {
03523   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT));
03524 }
03525
03526 /**
03527   * @brief  Set Tamper sampling frequency
03528   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
03529   * @param  TAMPx TAMP Instance
03530   * @param  SamplingFreq This parameter can be one of the following values:
03531   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
03532   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
03533   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
03534   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
03535   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
03536   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
03537   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
03538   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
03539   * @retval None
03540   */
03541 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
03542 {
03543   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
03544 }
03545
03546 /**
03547   * @brief  Get Tamper sampling frequency
03548   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
03549   * @param  TAMPx TAMP Instance
03550   * @retval Returned value can be one of the following values:
03551   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
03552   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
03553   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
03554   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
03555   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
03556   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
03557   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
03558   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
03559   */
03560 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)
03561 {
03562   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));
03563 }
03564 #endif /* TAMP_FLTCR_TAMPPUDIS */
03565
03566 /**
03567   * @}
03568   */
03569
03570 /** @defgroup RTC_LL_EF_Wakeup Wakeup
03571   * @{
03572   */
03573
03574 /**
03575   * @brief  Enable Wakeup timer
03576   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03577   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Enable
03578   * @param  RTCx RTC Instance
03579   * @retval None
03580   */
03581 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
03582 {
03583   SET_BIT(RTCx->CR, RTC_CR_WUTE);
03584 }
03585
03586 /**
03587   * @brief  Disable Wakeup timer
03588   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03589   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Disable
03590   * @param  RTCx RTC Instance
03591   * @retval None
03592   */
03593 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
03594 {
03595   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
03596 }
03597
03598 /**
03599   * @brief  Check if Wakeup timer is enabled or not
03600   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_IsEnabled
03601   * @param  RTCx RTC Instance
03602   * @retval State of bit (1 or 0).
03603   */
03604 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
03605 {
03606   return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
03607 }
03608
03609 /**
03610   * @brief  Select Wakeup clock
03611   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03612   * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
03613   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
03614   * @param  RTCx RTC Instance
03615   * @param  WakeupClock This parameter can be one of the following values:
03616   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03617   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03618   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03619   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03620   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03621   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03622   * @retval None
03623   */
03624 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
03625 {
03626   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
03627 }
03628
03629 /**
03630   * @brief  Get Wakeup clock
03631   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
03632   * @param  RTCx RTC Instance
03633   * @retval Returned value can be one of the following values:
03634   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03635   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03636   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03637   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03638   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03639   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03640   */
03641 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
03642 {
03643   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
03644 }
03645
03646 /**
03647   * @brief  Set Wakeup auto-reload value
03648   * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
03649   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
03650   * @param  RTCx RTC Instance
03651   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
03652   * @retval None
03653   */
03654 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03655 {
03656   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03657 }
03658
03659 /**
03660   * @brief  Get Wakeup auto-reload value
03661   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03662   * @param  RTCx RTC Instance
03663   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03664   */
03665 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03666 {
03667   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03668 }
03669
03670 /**
03671   * @}
03672   */
03673
03674
03675 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03676   * @{
03677   */
03678
03679 #if defined(RTC_BKP0R)
03680 /**
03681   * @brief  Writes a data in a specified RTC Backup data register.
03682   * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
03683   * @param  RTCx RTC Instance
03684   * @param  BackupRegister This parameter can be one of the following values:
03685   *         @arg @ref LL_RTC_BKP_DR0
03686   *         @arg @ref LL_RTC_BKP_DR1
03687   *         @arg @ref LL_RTC_BKP_DR2
03688   *         @arg @ref LL_RTC_BKP_DR3
03689   *         @arg @ref LL_RTC_BKP_DR4
03690   *         @arg @ref LL_RTC_BKP_DR5
03691   *         @arg @ref LL_RTC_BKP_DR6
03692   *         @arg @ref LL_RTC_BKP_DR7
03693   *         @arg @ref LL_RTC_BKP_DR8
03694   *         @arg @ref LL_RTC_BKP_DR9
03695   *         @arg @ref LL_RTC_BKP_DR10
03696   *         @arg @ref LL_RTC_BKP_DR11
03697   *         @arg @ref LL_RTC_BKP_DR12
03698   *         @arg @ref LL_RTC_BKP_DR13
03699   *         @arg @ref LL_RTC_BKP_DR14
03700   *         @arg @ref LL_RTC_BKP_DR15
03701   *         @arg @ref LL_RTC_BKP_DR16
03702   *         @arg @ref LL_RTC_BKP_DR17
03703   *         @arg @ref LL_RTC_BKP_DR18
03704   *         @arg @ref LL_RTC_BKP_DR19
03705   *         @arg @ref LL_RTC_BKP_DR20
03706   *         @arg @ref LL_RTC_BKP_DR21
03707   *         @arg @ref LL_RTC_BKP_DR22
03708   *         @arg @ref LL_RTC_BKP_DR23
03709   *         @arg @ref LL_RTC_BKP_DR24
03710   *         @arg @ref LL_RTC_BKP_DR25
03711   *         @arg @ref LL_RTC_BKP_DR26
03712   *         @arg @ref LL_RTC_BKP_DR27
03713   *         @arg @ref LL_RTC_BKP_DR28
03714   *         @arg @ref LL_RTC_BKP_DR29
03715   *         @arg @ref LL_RTC_BKP_DR30
03716   *         @arg @ref LL_RTC_BKP_DR31
03717   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03718   * @retval None
03719   */
03720 __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
03721 {
03722   register uint32_t tmp;
03723
03724   tmp = (uint32_t)(&(RTCx->BKP0R));
03725   tmp += (BackupRegister * 4U);
03726
03727   /* Write the specified register */
03728   *(__IO uint32_t *)tmp = (uint32_t)Data;
03729 }
03730
03731 /**
03732   * @brief  Reads data from the specified RTC Backup data Register.
03733   * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
03734   * @param  RTCx RTC Instance
03735   * @param  BackupRegister This parameter can be one of the following values:
03736   *         @arg @ref LL_RTC_BKP_DR0
03737   *         @arg @ref LL_RTC_BKP_DR1
03738   *         @arg @ref LL_RTC_BKP_DR2
03739   *         @arg @ref LL_RTC_BKP_DR3
03740   *         @arg @ref LL_RTC_BKP_DR4
03741   *         @arg @ref LL_RTC_BKP_DR5
03742   *         @arg @ref LL_RTC_BKP_DR6
03743   *         @arg @ref LL_RTC_BKP_DR7
03744   *         @arg @ref LL_RTC_BKP_DR8
03745   *         @arg @ref LL_RTC_BKP_DR9
03746   *         @arg @ref LL_RTC_BKP_DR10
03747   *         @arg @ref LL_RTC_BKP_DR11
03748   *         @arg @ref LL_RTC_BKP_DR12
03749   *         @arg @ref LL_RTC_BKP_DR13
03750   *         @arg @ref LL_RTC_BKP_DR14
03751   *         @arg @ref LL_RTC_BKP_DR15
03752   *         @arg @ref LL_RTC_BKP_DR16
03753   *         @arg @ref LL_RTC_BKP_DR17
03754   *         @arg @ref LL_RTC_BKP_DR18
03755   *         @arg @ref LL_RTC_BKP_DR19
03756   *         @arg @ref LL_RTC_BKP_DR20
03757   *         @arg @ref LL_RTC_BKP_DR21
03758   *         @arg @ref LL_RTC_BKP_DR22
03759   *         @arg @ref LL_RTC_BKP_DR23
03760   *         @arg @ref LL_RTC_BKP_DR24
03761   *         @arg @ref LL_RTC_BKP_DR25
03762   *         @arg @ref LL_RTC_BKP_DR26
03763   *         @arg @ref LL_RTC_BKP_DR27
03764   *         @arg @ref LL_RTC_BKP_DR28
03765   *         @arg @ref LL_RTC_BKP_DR29
03766   *         @arg @ref LL_RTC_BKP_DR30
03767   *         @arg @ref LL_RTC_BKP_DR31
03768   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03769   */
03770 __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
03771 {
03772   register uint32_t tmp;
03773
03774   tmp = (uint32_t)(&(RTCx->BKP0R));
03775   tmp += (BackupRegister * 4U);
03776
03777   /* Read the specified register */
03778   return (*(__IO uint32_t *)tmp);
03779 }
03780 #endif /* RTC_BKP0R */
03781
03782 #if defined(TAMP_BKP0R_BKP)
03783 /**
03784   * @brief  Writes a data in a specified Backup data register.
03785   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister
03786   * @param  TAMPx RTC Instance
03787   * @param  BackupRegister This parameter can be one of the following values:
03788   *         @arg @ref LL_RTC_BKP_DR0
03789   *         @arg @ref LL_RTC_BKP_DR1
03790   *         @arg @ref LL_RTC_BKP_DR2
03791   *         @arg @ref LL_RTC_BKP_DR3
03792   *         @arg @ref LL_RTC_BKP_DR4
03793   *         @arg @ref LL_RTC_BKP_DR5
03794   *         @arg @ref LL_RTC_BKP_DR6
03795   *         @arg @ref LL_RTC_BKP_DR7
03796   *         @arg @ref LL_RTC_BKP_DR8
03797   *         @arg @ref LL_RTC_BKP_DR9
03798   *         @arg @ref LL_RTC_BKP_DR10
03799   *         @arg @ref LL_RTC_BKP_DR11
03800   *         @arg @ref LL_RTC_BKP_DR12
03801   *         @arg @ref LL_RTC_BKP_DR13
03802   *         @arg @ref LL_RTC_BKP_DR14
03803   *         @arg @ref LL_RTC_BKP_DR15
03804   *         @arg @ref LL_RTC_BKP_DR16
03805   *         @arg @ref LL_RTC_BKP_DR17
03806   *         @arg @ref LL_RTC_BKP_DR18
03807   *         @arg @ref LL_RTC_BKP_DR19
03808   *         @arg @ref LL_RTC_BKP_DR20
03809   *         @arg @ref LL_RTC_BKP_DR21
03810   *         @arg @ref LL_RTC_BKP_DR22
03811   *         @arg @ref LL_RTC_BKP_DR23
03812   *         @arg @ref LL_RTC_BKP_DR24
03813   *         @arg @ref LL_RTC_BKP_DR25
03814   *         @arg @ref LL_RTC_BKP_DR26
03815   *         @arg @ref LL_RTC_BKP_DR27
03816   *         @arg @ref LL_RTC_BKP_DR28
03817   *         @arg @ref LL_RTC_BKP_DR29
03818   *         @arg @ref LL_RTC_BKP_DR30
03819   *         @arg @ref LL_RTC_BKP_DR31
03820   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03821   * @retval None
03822   */
03823 __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
03824 {
03825   register uint32_t tmp = 0U;
03826
03827   tmp = (uint32_t)(&(TAMPx->BKP0R));
03828   tmp += (BackupRegister * 4U);
03829
03830   /* Write the specified register */
03831   *(__IO uint32_t *)tmp = (uint32_t)Data;
03832 }
03833
03834 /**
03835   * @brief  Reads data from the specified RTC Backup data Register.
03836   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_GetRegister
03837   * @param  TAMPx RTC Instance
03838   * @param  BackupRegister This parameter can be one of the following values:
03839   *         @arg @ref LL_RTC_BKP_DR0
03840   *         @arg @ref LL_RTC_BKP_DR1
03841   *         @arg @ref LL_RTC_BKP_DR2
03842   *         @arg @ref LL_RTC_BKP_DR3
03843   *         @arg @ref LL_RTC_BKP_DR4
03844   *         @arg @ref LL_RTC_BKP_DR5
03845   *         @arg @ref LL_RTC_BKP_DR6
03846   *         @arg @ref LL_RTC_BKP_DR7
03847   *         @arg @ref LL_RTC_BKP_DR8
03848   *         @arg @ref LL_RTC_BKP_DR9
03849   *         @arg @ref LL_RTC_BKP_DR10
03850   *         @arg @ref LL_RTC_BKP_DR11
03851   *         @arg @ref LL_RTC_BKP_DR12
03852   *         @arg @ref LL_RTC_BKP_DR13
03853   *         @arg @ref LL_RTC_BKP_DR14
03854   *         @arg @ref LL_RTC_BKP_DR15
03855   *         @arg @ref LL_RTC_BKP_DR16
03856   *         @arg @ref LL_RTC_BKP_DR17
03857   *         @arg @ref LL_RTC_BKP_DR18
03858   *         @arg @ref LL_RTC_BKP_DR19
03859   *         @arg @ref LL_RTC_BKP_DR20
03860   *         @arg @ref LL_RTC_BKP_DR21
03861   *         @arg @ref LL_RTC_BKP_DR22
03862   *         @arg @ref LL_RTC_BKP_DR23
03863   *         @arg @ref LL_RTC_BKP_DR24
03864   *         @arg @ref LL_RTC_BKP_DR25
03865   *         @arg @ref LL_RTC_BKP_DR26
03866   *         @arg @ref LL_RTC_BKP_DR27
03867   *         @arg @ref LL_RTC_BKP_DR28
03868   *         @arg @ref LL_RTC_BKP_DR29
03869   *         @arg @ref LL_RTC_BKP_DR30
03870   *         @arg @ref LL_RTC_BKP_DR31
03871   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03872   */
03873 __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
03874 {
03875   register uint32_t tmp = 0U;
03876
03877   tmp = (uint32_t)(&(TAMPx->BKP0R));
03878   tmp += (BackupRegister * 4U);
03879
03880   /* Read the specified register */
03881   return (*(__IO uint32_t *)tmp);
03882 }
03883 #endif /* TAMP_BKP0R_BKP */
03884
03885 /**
03886   * @}
03887   */
03888
03889
03890 /** @defgroup RTC_LL_EF_Calibration Calibration
03891   * @{
03892   */
03893
03894 /**
03895   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03896   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03897   * @rmtoll RTC_CR           COE           LL_RTC_CAL_SetOutputFreq
03898   *         RTC_CR           COSEL         LL_RTC_CAL_SetOutputFreq
03899   * @param  RTCx RTC Instance
03900   * @param  Frequency This parameter can be one of the following values:
03901   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03902   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03903   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03904   * @retval None
03905   */
03906 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03907 {
03908   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03909 }
03910
03911 /**
03912   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03913   * @rmtoll RTC_CR           COE           LL_RTC_CAL_GetOutputFreq
03914   *         RTC_CR           COSEL         LL_RTC_CAL_GetOutputFreq
03915   * @param  RTCx RTC Instance
03916   * @retval Returned value can be one of the following values:
03917   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03918   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03919   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03920   */
03921 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03922 {
03923   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03924 }
03925
03926 /**
03927   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03928   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03929   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03930   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_SetPulse
03931   * @param  RTCx RTC Instance
03932   * @param  Pulse This parameter can be one of the following values:
03933   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03934   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03935   * @retval None
03936   */
03937 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03938 {
03939   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03940 }
03941
03942 /**
03943   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03944   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_IsPulseInserted
03945   * @param  RTCx RTC Instance
03946   * @retval State of bit (1 or 0).
03947   */
03948 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03949 {
03950   return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
03951 }
03952
03953 /**
03954   * @brief  Set the calibration cycle period
03955   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03956   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03957   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_SetPeriod
03958   *         RTC_CALR         CALW16        LL_RTC_CAL_SetPeriod
03959   * @param  RTCx RTC Instance
03960   * @param  Period This parameter can be one of the following values:
03961   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03962   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03963   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03964   * @retval None
03965   */
03966 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03967 {
03968   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03969 }
03970
03971 /**
03972   * @brief  Get the calibration cycle period
03973   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_GetPeriod
03974   *         RTC_CALR         CALW16        LL_RTC_CAL_GetPeriod
03975   * @param  RTCx RTC Instance
03976   * @retval Returned value can be one of the following values:
03977   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03978   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03979   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03980   */
03981 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03982 {
03983   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03984 }
03985
03986 /**
03987   * @brief  Set Calibration minus
03988   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03989   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03990   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_SetMinus
03991   * @param  RTCx RTC Instance
03992   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03993   * @retval None
03994   */
03995 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03996 {
03997   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03998 }
03999
04000 /**
04001   * @brief  Get Calibration minus
04002   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_GetMinus
04003   * @param  RTCx RTC Instance
04004   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
04005   */
04006 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
04007 {
04008   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
04009 }
04010
04011 /**
04012   * @}
04013   */
04014
04015
04016 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
04017   * @{
04018   */
04019
04020 #if defined(RTC_ISR_ITSF)
04021 /**
04022   * @brief  Get Internal Time-stamp flag
04023   * @rmtoll RTC_ISR          ITSF          LL_RTC_IsActiveFlag_ITS
04024   * @param  RTCx RTC Instance
04025   * @retval State of bit (1 or 0).
04026   */
04027 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
04028 {
04029   return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);
04030 }
04031
04032 /**
04033   * @brief  Get Recalibration pending Flag
04034   * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
04035   * @param  RTCx RTC Instance
04036   * @retval State of bit (1 or 0).
04037   */
04038 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
04039 {
04040   return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
04041 }
04042
04043 /**
04044   * @brief  Get RTC_TAMP3 detection flag
04045   * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
04046   * @param  RTCx RTC Instance
04047   * @retval State of bit (1 or 0).
04048   */
04049 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
04050 {
04051   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
04052 }
04053
04054 /**
04055   * @brief  Get RTC_TAMP2 detection flag
04056   * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
04057   * @param  RTCx RTC Instance
04058   * @retval State of bit (1 or 0).
04059   */
04060 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
04061 {
04062   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
04063 }
04064
04065 /**
04066   * @brief  Get RTC_TAMP1 detection flag
04067   * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
04068   * @param  RTCx RTC Instance
04069   * @retval State of bit (1 or 0).
04070   */
04071 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
04072 {
04073   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
04074 }
04075
04076 /**
04077   * @brief  Get Time-stamp overflow flag
04078   * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
04079   * @param  RTCx RTC Instance
04080   * @retval State of bit (1 or 0).
04081   */
04082 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
04083 {
04084   return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
04085 }
04086
04087 /**
04088   * @brief  Get Time-stamp flag
04089   * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
04090   * @param  RTCx RTC Instance
04091   * @retval State of bit (1 or 0).
04092   */
04093 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
04094 {
04095   return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
04096 }
04097
04098 /**
04099   * @brief  Get Wakeup timer flag
04100   * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
04101   * @param  RTCx RTC Instance
04102   * @retval State of bit (1 or 0).
04103   */
04104 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
04105 {
04106   return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
04107 }
04108
04109 /**
04110   * @brief  Get Alarm B flag
04111   * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
04112   * @param  RTCx RTC Instance
04113   * @retval State of bit (1 or 0).
04114   */
04115 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
04116 {
04117   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
04118 }
04119
04120 /**
04121   * @brief  Get Alarm A flag
04122   * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
04123   * @param  RTCx RTC Instance
04124   * @retval State of bit (1 or 0).
04125   */
04126 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
04127 {
04128   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
04129 }
04130
04131 /**
04132   * @brief  Clear Internal Time-stamp flag
04133   * @rmtoll ISR          ITSF          LL_RTC_ClearFlag_ITS
04134   * @param  RTCx RTC Instance
04135   * @retval None
04136   */
04137 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
04138 {
04139   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04140 }
04141
04142 /**
04143   * @brief  Clear RTC_TAMP3 detection flag
04144   * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
04145   * @param  RTCx RTC Instance
04146   * @retval None
04147   */
04148 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
04149 {
04150   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04151 }
04152
04153 /**
04154   * @brief  Clear RTC_TAMP2 detection flag
04155   * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
04156   * @param  RTCx RTC Instance
04157   * @retval None
04158   */
04159 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
04160 {
04161   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04162 }
04163
04164 /**
04165   * @brief  Clear RTC_TAMP1 detection flag
04166   * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
04167   * @param  RTCx RTC Instance
04168   * @retval None
04169   */
04170 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
04171 {
04172   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04173 }
04174
04175 /**
04176   * @brief  Clear Time-stamp overflow flag
04177   * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
04178   * @param  RTCx RTC Instance
04179   * @retval None
04180   */
04181 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
04182 {
04183   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04184 }
04185
04186 /**
04187   * @brief  Clear Time-stamp flag
04188   * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
04189   * @param  RTCx RTC Instance
04190   * @retval None
04191   */
04192 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
04193 {
04194   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04195 }
04196
04197 /**
04198   * @brief  Clear Wakeup timer flag
04199   * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
04200   * @param  RTCx RTC Instance
04201   * @retval None
04202   */
04203 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
04204 {
04205   WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04206 }
04207
04208 /**
04209   * @brief  Clear Alarm B flag
04210   * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
04211   * @param  RTCx RTC Instance
04212   * @retval None
04213   */
04214 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
04215 {
04216   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04217 }
04218
04219 /**
04220   * @brief  Clear Alarm A flag
04221   * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
04222   * @param  RTCx RTC Instance
04223   * @retval None
04224   */
04225 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
04226 {
04227   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04228 }
04229
04230 /**
04231   * @brief  Get Initialization flag
04232   * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
04233   * @param  RTCx RTC Instance
04234   * @retval State of bit (1 or 0).
04235   */
04236 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
04237 {
04238   return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
04239 }
04240
04241 /**
04242   * @brief  Get Registers synchronization flag
04243   * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
04244   * @param  RTCx RTC Instance
04245   * @retval State of bit (1 or 0).
04246   */
04247 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
04248 {
04249   return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
04250 }
04251
04252 /**
04253   * @brief  Clear Registers synchronization flag
04254   * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
04255   * @param  RTCx RTC Instance
04256   * @retval None
04257   */
04258 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
04259 {
04260   WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
04261 }
04262
04263 /**
04264   * @brief  Get Initialization status flag
04265   * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
04266   * @param  RTCx RTC Instance
04267   * @retval State of bit (1 or 0).
04268   */
04269 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
04270 {
04271   return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
04272 }
04273
04274 /**
04275   * @brief  Get Shift operation pending flag
04276   * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
04277   * @param  RTCx RTC Instance
04278   * @retval State of bit (1 or 0).
04279   */
04280 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
04281 {
04282   return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
04283 }
04284
04285 /**
04286   * @brief  Get Wakeup timer write flag
04287   * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
04288   * @param  RTCx RTC Instance
04289   * @retval State of bit (1 or 0).
04290   */
04291 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
04292 {
04293   return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
04294 }
04295
04296 /**
04297   * @brief  Get Alarm B write flag
04298   * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
04299   * @param  RTCx RTC Instance
04300   * @retval State of bit (1 or 0).
04301   */
04302 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
04303 {
04304   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
04305 }
04306
04307 /**
04308   * @brief  Get Alarm A write flag
04309   * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
04310   * @param  RTCx RTC Instance
04311   * @retval State of bit (1 or 0).
04312   */
04313 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
04314 {
04315   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
04316 }
04317 #endif /* RTC_ISR_ITSF */
04318
04319 #if defined(RTC_SR_ITSF)
04320 /**
04321   * @brief  Get Internal Time-stamp flag
04322   * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS
04323   * @param  RTCx RTC Instance
04324   * @retval State of bit (1 or 0).
04325   */
04326 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
04327 {
04328   return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);
04329 }
04330
04331 /**
04332   * @brief  Get Time-stamp overflow flag
04333   * @rmtoll RTC_SR          TSOVF         LL_RTC_IsActiveFlag_TSOV
04334   * @param  RTCx RTC Instance
04335   * @retval State of bit (1 or 0).
04336   */
04337 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
04338 {
04339   return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);
04340 }
04341
04342 /**
04343   * @brief  Get Time-stamp flag
04344   * @rmtoll RTC_SR          TSF           LL_RTC_IsActiveFlag_TS
04345   * @param  RTCx RTC Instance
04346   * @retval State of bit (1 or 0).
04347   */
04348 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
04349 {
04350   return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);
04351 }
04352
04353 /**
04354   * @brief  Get Wakeup timer flag
04355   * @rmtoll RTC_SR          WUTF          LL_RTC_IsActiveFlag_WUT
04356   * @param  RTCx RTC Instance
04357   * @retval State of bit (1 or 0).
04358   */
04359 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
04360 {
04361   return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);
04362 }
04363
04364 /**
04365   * @brief  Get Alarm B flag
04366   * @rmtoll RTC_SR          ALRBF         LL_RTC_IsActiveFlag_ALRB
04367   * @param  RTCx RTC Instance
04368   * @retval State of bit (1 or 0).
04369   */
04370 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
04371 {
04372   return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);
04373 }
04374
04375 /**
04376   * @brief  Get Alarm A flag
04377   * @rmtoll RTC_SR          ALRAF         LL_RTC_IsActiveFlag_ALRA
04378   * @param  RTCx RTC Instance
04379   * @retval State of bit (1 or 0).
04380   */
04381 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
04382 {
04383   return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
04384 }
04385 #endif /* RTC_SR_ITSF */
04386
04387 #if defined(RTC_SCR_CITSF)
04388 /**
04389   * @brief  Clear Internal Time-stamp flag
04390   * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS
04391   * @param  RTCx RTC Instance
04392   * @retval None
04393   */
04394 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
04395 {
04396   SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
04397 }
04398
04399 /**
04400   * @brief  Clear Time-stamp overflow flag
04401   * @rmtoll RTC_SCR          CTSOVF         LL_RTC_ClearFlag_TSOV
04402   * @param  RTCx RTC Instance
04403   * @retval None
04404   */
04405 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
04406 {
04407   SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
04408 }
04409
04410 /**
04411   * @brief  Clear Time-stamp flag
04412   * @rmtoll RTC_SCR          CTSF           LL_RTC_ClearFlag_TS
04413   * @param  RTCx RTC Instance
04414   * @retval None
04415   */
04416 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
04417 {
04418   SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
04419 }
04420
04421 /**
04422   * @brief  Clear Wakeup timer flag
04423   * @rmtoll RTC_SCR          CWUTF          LL_RTC_ClearFlag_WUT
04424   * @param  RTCx RTC Instance
04425   * @retval None
04426   */
04427 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
04428 {
04429   SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
04430 }
04431
04432 /**
04433   * @brief  Clear Alarm B flag
04434   * @rmtoll RTC_SCR          CALRBF         LL_RTC_ClearFlag_ALRB
04435   * @param  RTCx RTC Instance
04436   * @retval None
04437   */
04438 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
04439 {
04440   SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
04441 }
04442
04443 /**
04444   * @brief  Clear Alarm A flag
04445   * @rmtoll RTC_SCR          CALRAF         LL_RTC_ClearFlag_ALRA
04446   * @param  RTCx RTC Instance
04447   * @retval None
04448   */
04449 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
04450 {
04451   SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
04452 }
04453 #endif /* RTC_SCR_CITSF */
04454
04455 #if defined(RTC_ICSR_RECALPF)
04456 /**
04457   * @brief  Get Recalibration pending Flag
04458   * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP
04459   * @param  RTCx RTC Instance
04460   * @retval State of bit (1 or 0).
04461   */
04462 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
04463 {
04464   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);
04465 }
04466
04467 /**
04468   * @brief  Get Initialization flag
04469   * @rmtoll RTC_ICSR          INITF         LL_RTC_IsActiveFlag_INIT
04470   * @param  RTCx RTC Instance
04471   * @retval State of bit (1 or 0).
04472   */
04473 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
04474 {
04475   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);
04476 }
04477
04478 /**
04479   * @brief  Get Registers synchronization flag
04480   * @rmtoll RTC_ICSR          RSF           LL_RTC_IsActiveFlag_RS
04481   * @param  RTCx RTC Instance
04482   * @retval State of bit (1 or 0).
04483   */
04484 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
04485 {
04486   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);
04487 }
04488
04489 /**
04490   * @brief  Clear Registers synchronization flag
04491   * @rmtoll RTC_ICSR          RSF           LL_RTC_ClearFlag_RS
04492   * @param  RTCx RTC Instance
04493   * @retval None
04494   */
04495 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
04496 {
04497   WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
04498 }
04499
04500 /**
04501   * @brief  Get Initialization status flag
04502   * @rmtoll RTC_ICSR          INITS         LL_RTC_IsActiveFlag_INITS
04503   * @param  RTCx RTC Instance
04504   * @retval State of bit (1 or 0).
04505   */
04506 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
04507 {
04508   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);
04509 }
04510
04511 /**
04512   * @brief  Get Shift operation pending flag
04513   * @rmtoll RTC_ICSR          SHPF          LL_RTC_IsActiveFlag_SHP
04514   * @param  RTCx RTC Instance
04515   * @retval State of bit (1 or 0).
04516   */
04517 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
04518 {
04519   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);
04520 }
04521
04522 /**
04523   * @brief  Get Wakeup timer write flag
04524   * @rmtoll RTC_ICSR          WUTWF         LL_RTC_IsActiveFlag_WUTW
04525   * @param  RTCx RTC Instance
04526   * @retval State of bit (1 or 0).
04527   */
04528 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
04529 {
04530   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);
04531 }
04532
04533 /**
04534   * @brief  Get Alarm B write flag
04535   * @rmtoll RTC_ICSR         ALRBWF        LL_RTC_IsActiveFlag_ALRBW
04536   * @param  RTCx RTC Instance
04537   * @retval State of bit (1 or 0).
04538   */
04539 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
04540 {
04541   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);
04542 }
04543
04544 /**
04545   * @brief  Get Alarm A write flag
04546   * @rmtoll RTC_ICSR         ALRAWF        LL_RTC_IsActiveFlag_ALRAW
04547   * @param  RTCx RTC Instance
04548   * @retval State of bit (1 or 0).
04549   */
04550 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
04551 {
04552   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
04553 }
04554 #endif /* RTC_ICSR_RECALPF */
04555
04556 #if defined(RTC_MISR_ALRAMF)
04557 /**
04558   * @brief  Get Alarm A masked flag.
04559   * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM
04560   * @param  RTCx RTC Instance
04561   * @retval State of bit (1 or 0).
04562   */
04563 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
04564 {
04565   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);
04566 }
04567
04568 /**
04569   * @brief  Get Alarm B masked flag.
04570   * @rmtoll RTC_MISR          ALRBMF        LL_RTC_IsActiveFlag_ALRBM
04571   * @param  RTCx RTC Instance
04572   * @retval State of bit (1 or 0).
04573   */
04574 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
04575 {
04576   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);
04577 }
04578
04579 /**
04580   * @brief  Get Wakeup timer masked flag.
04581   * @rmtoll RTC_MISR          WUTMF        LL_RTC_IsActiveFlag_WUTM
04582   * @param  RTCx RTC Instance
04583   * @retval State of bit (1 or 0).
04584   */
04585 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
04586 {
04587   return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);
04588 }
04589
04590 /**
04591   * @brief  Get Time-stamp masked flag.
04592   * @rmtoll RTC_MISR          TSMF        LL_RTC_IsActiveFlag_TSM
04593   * @param  RTCx RTC Instance
04594   * @retval State of bit (1 or 0).
04595   */
04596 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
04597 {
04598   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);
04599 }
04600
04601 /**
04602   * @brief  Get Time-stamp overflow masked flag.
04603   * @rmtoll RTC_MISR          TSOVMF        LL_RTC_IsActiveFlag_TSOVM
04604   * @param  RTCx RTC Instance
04605   * @retval State of bit (1 or 0).
04606   */
04607 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
04608 {
04609   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);
04610 }
04611
04612 /**
04613   * @brief  Get Internal Time-stamp masked flag.
04614   * @rmtoll RTC_MISR          ITSMF        LL_RTC_IsActiveFlag_ITSM
04615   * @param  RTCx RTC Instance
04616   * @retval State of bit (1 or 0).
04617   */
04618 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
04619 {
04620   return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
04621 }
04622 #endif /* RTC_MISR_ALRAMF */
04623
04624 #if defined(TAMP_CR1_TAMP1E)
04625 /**
04626   * @brief  Get tamper 1 detection flag.
04627   * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
04628   * @param  TAMPx TAMP Instance
04629   * @retval State of bit (1 or 0).
04630   */
04631 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)
04632 {
04633   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
04634 }
04635 #endif /* TAMP_CR1_TAMP1E */
04636
04637 #if defined(TAMP_CR1_TAMP2E)
04638 /**
04639   * @brief  Get tamper 2 detection flag.
04640   * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
04641   * @param  TAMPx TAMP Instance
04642   * @retval State of bit (1 or 0).
04643   */
04644 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)
04645 {
04646   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
04647 }
04648 #endif /* TAMP_CR1_TAMP2E */
04649
04650 #if defined(TAMP_CR1_TAMP3E)
04651 /**
04652   * @brief  Get tamper 3 detection flag.
04653   * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
04654   * @param  TAMPx TAMP Instance
04655   * @retval State of bit (1 or 0).
04656   */
04657 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)
04658 {
04659   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
04660 }
04661 #endif /* TAMP_CR1_TAMP3E */
04662
04663 #if defined(TAMP_CR1_TAMP1E)
04664 /**
04665   * @brief  Get tamper 1 interrupt masked flag.
04666   * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M
04667   * @param  TAMPx TAMP Instance
04668   * @retval State of bit (1 or 0).
04669   */
04670 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)
04671 {
04672   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
04673 }
04674 #endif /* TAMP_CR1_TAMP1E */
04675
04676 #if defined(TAMP_CR1_TAMP2E)
04677 /**
04678   * @brief  Get tamper 2 interrupt masked flag.
04679   * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M
04680   * @param  TAMPx TAMP Instance
04681   * @retval State of bit (1 or 0).
04682   */
04683 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)
04684 {
04685   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
04686 }
04687 #endif /* TAMP_CR1_TAMP2E */
04688
04689 #if defined(TAMP_CR1_TAMP3E)
04690 /**
04691   * @brief  Get tamper 3 interrupt masked flag.
04692   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
04693   * @param  TAMPx TAMP Instance
04694   * @retval State of bit (1 or 0).
04695   */
04696 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)
04697 {
04698   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
04699 }
04700 #endif /* TAMP_CR1_TAMP3E */
04701
04702 #if defined(TAMP_CR1_TAMP1E)
04703 /**
04704   * @brief  Clear tamper 1 detection flag.
04705   * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1
04706   * @param  TAMPx TAMP Instance
04707   * @retval None
04708   */
04709 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx)
04710 {
04711   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);
04712 }
04713 #endif /* TAMP_CR1_TAMP1E */
04714
04715 #if defined(TAMP_CR1_TAMP2E)
04716 /**
04717   * @brief  Clear tamper 2 detection flag.
04718   * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2
04719   * @param  TAMPx TAMP Instance
04720   * @retval None
04721   */
04722 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx)
04723 {
04724   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);
04725 }
04726 #endif /* TAMP_CR1_TAMP2E */
04727
04728 #if defined(TAMP_CR1_TAMP3E)
04729 /**
04730   * @brief  Clear tamper 3 detection flag.
04731   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
04732   * @param  TAMPx TAMP Instance
04733   * @retval None
04734   */
04735 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx)
04736 {
04737   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);
04738 }
04739 #endif /* TAMP_CR1_TAMP3E */
04740
04741 /**
04742   * @}
04743   */
04744
04745 /** @defgroup RTC_LL_EF_IT_Management IT_Management
04746   * @{
04747   */
04748
04749 /**
04750   * @brief  Enable Time-stamp interrupt
04751   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04752   * @rmtoll RTC_CR          TSIE         LL_RTC_EnableIT_TS
04753   * @param  RTCx RTC Instance
04754   * @retval None
04755   */
04756 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
04757 {
04758   SET_BIT(RTCx->CR, RTC_CR_TSIE);
04759 }
04760
04761 /**
04762   * @brief  Disable Time-stamp interrupt
04763   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04764   * @rmtoll RTC_CR          TSIE         LL_RTC_DisableIT_TS
04765   * @param  RTCx RTC Instance
04766   * @retval None
04767   */
04768 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
04769 {
04770   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
04771 }
04772
04773 /**
04774   * @brief  Enable Wakeup timer interrupt
04775   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04776   * @rmtoll RTC_CR          WUTIE         LL_RTC_EnableIT_WUT
04777   * @param  RTCx RTC Instance
04778   * @retval None
04779   */
04780 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
04781 {
04782   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
04783 }
04784
04785 /**
04786   * @brief  Disable Wakeup timer interrupt
04787   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04788   * @rmtoll RTC_CR          WUTIE         LL_RTC_DisableIT_WUT
04789   * @param  RTCx RTC Instance
04790   * @retval None
04791   */
04792 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
04793 {
04794   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
04795 }
04796
04797 /**
04798   * @brief  Enable Alarm B interrupt
04799   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04800   * @rmtoll RTC_CR           ALRBIE        LL_RTC_EnableIT_ALRB
04801   * @param  RTCx RTC Instance
04802   * @retval None
04803   */
04804 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
04805 {
04806   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
04807 }
04808
04809 /**
04810   * @brief  Disable Alarm B interrupt
04811   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04812   * @rmtoll RTC_CR           ALRBIE        LL_RTC_DisableIT_ALRB
04813   * @param  RTCx RTC Instance
04814   * @retval None
04815   */
04816 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
04817 {
04818   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
04819 }
04820
04821 /**
04822   * @brief  Enable Alarm A interrupt
04823   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04824   * @rmtoll RTC_CR           ALRAIE        LL_RTC_EnableIT_ALRA
04825   * @param  RTCx RTC Instance
04826   * @retval None
04827   */
04828 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
04829 {
04830   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
04831 }
04832
04833 /**
04834   * @brief  Disable Alarm A interrupt
04835   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04836   * @rmtoll RTC_CR           ALRAIE        LL_RTC_DisableIT_ALRA
04837   * @param  RTCx RTC Instance
04838   * @retval None
04839   */
04840 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
04841 {
04842   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
04843 }
04844
04845 #if defined(RTC_TAMPCR_TAMP3E)
04846 /**
04847   * @brief  Enable Tamper 3 interrupt
04848   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
04849   * @param  RTCx RTC Instance
04850   * @retval None
04851   */
04852 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
04853 {
04854   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
04855 }
04856
04857 /**
04858   * @brief  Disable Tamper 3 interrupt
04859   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
04860   * @param  RTCx RTC Instance
04861   * @retval None
04862   */
04863 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
04864 {
04865   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
04866 }
04867 #endif /* RTC_TAMPCR_TAMP3E */
04868
04869 #if defined(RTC_TAMPCR_TAMP2E)
04870 /**
04871   * @brief  Enable Tamper 2 interrupt
04872   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
04873   * @param  RTCx RTC Instance
04874   * @retval None
04875   */
04876 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
04877 {
04878   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
04879 }
04880
04881 /**
04882   * @brief  Disable Tamper 2 interrupt
04883   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
04884   * @param  RTCx RTC Instance
04885   * @retval None
04886   */
04887 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
04888 {
04889   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
04890 }
04891 #endif /* RTC_TAMPCR_TAMP2E */
04892
04893 #if defined(RTC_TAMPCR_TAMP1E)
04894 /**
04895   * @brief  Enable Tamper 1 interrupt
04896   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
04897   * @param  RTCx RTC Instance
04898   * @retval None
04899   */
04900 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
04901 {
04902   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
04903 }
04904
04905 /**
04906   * @brief  Disable Tamper 1 interrupt
04907   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
04908   * @param  RTCx RTC Instance
04909   * @retval None
04910   */
04911 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
04912 {
04913   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
04914 }
04915 #endif /* RTC_TAMPCR_TAMP1E */
04916
04917 #if defined(RTC_TAMPCR_TAMPIE)
04918 /**
04919   * @brief  Enable all Tamper Interrupt
04920   * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
04921   * @param  RTCx RTC Instance
04922   * @retval None
04923   */
04924 __STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
04925 {
04926   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
04927 }
04928
04929 /**
04930   * @brief  Disable all Tamper Interrupt
04931   * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
04932   * @param  RTCx RTC Instance
04933   * @retval None
04934   */
04935 __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
04936 {
04937   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
04938 }
04939 #endif /* RTC_TAMPCR_TAMPIE */
04940
04941 /**
04942   * @brief  Check if  Time-stamp interrupt is enabled or not
04943   * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
04944   * @param  RTCx RTC Instance
04945   * @retval State of bit (1 or 0).
04946   */
04947 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
04948 {
04949   return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
04950 }
04951
04952 /**
04953   * @brief  Check if  Wakeup timer interrupt is enabled or not
04954   * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
04955   * @param  RTCx RTC Instance
04956   * @retval State of bit (1 or 0).
04957   */
04958 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
04959 {
04960   return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
04961 }
04962
04963 /**
04964   * @brief  Check if  Alarm B interrupt is enabled or not
04965   * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
04966   * @param  RTCx RTC Instance
04967   * @retval State of bit (1 or 0).
04968   */
04969 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
04970 {
04971   return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
04972 }
04973
04974 /**
04975   * @brief  Check if  Alarm A interrupt is enabled or not
04976   * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
04977   * @param  RTCx RTC Instance
04978   * @retval State of bit (1 or 0).
04979   */
04980 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
04981 {
04982   return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
04983 }
04984
04985 #if defined(RTC_TAMPCR_TAMP3E)
04986 /**
04987   * @brief  Check if  Tamper 3 interrupt is enabled or not
04988   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
04989   * @param  RTCx RTC Instance
04990   * @retval State of bit (1 or 0).
04991   */
04992 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
04993 {
04994   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
04995 }
04996 #endif /* RTC_TAMPCR_TAMP3E */
04997
04998 #if defined(RTC_TAMPCR_TAMP2E)
04999 /**
05000   * @brief  Check if  Tamper 2 interrupt is enabled or not
05001   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
05002   * @param  RTCx RTC Instance
05003   * @retval State of bit (1 or 0).
05004   */
05005 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
05006 {
05007   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
05008
05009 }
05010 #endif /* RTC_TAMPCR_TAMP2E */
05011
05012 #if defined(RTC_TAMPCR_TAMP1E)
05013 /**
05014   * @brief  Check if  Tamper 1 interrupt is enabled or not
05015   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
05016   * @param  RTCx RTC Instance
05017   * @retval State of bit (1 or 0).
05018   */
05019 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
05020 {
05021   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
05022 }
05023 #endif /* RTC_TAMPCR_TAMP1E */
05024
05025 #if defined(RTC_TAMPCR_TAMPIE)
05026 /**
05027   * @brief  Check if all the TAMPER interrupts are enabled or not
05028   * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
05029   * @param  RTCx RTC Instance
05030   * @retval State of bit (1 or 0).
05031   */
05032 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
05033 {
05034   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
05035 }
05036 #endif /* RTC_TAMPCR_TAMPIE */
05037
05038 #if defined(TAMP_CR1_TAMP1E)
05039 /**
05040   * @brief  Enable tamper 1 interrupt.
05041   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1
05042   * @param  TAMPx TAMP Instance
05043   * @retval None
05044   */
05045 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx)
05046 {
05047   SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
05048 }
05049
05050 /**
05051   * @brief  Disable tamper 1 interrupt.
05052   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_TAMP1
05053   * @param  TAMPx TAMP Instance
05054   * @retval None
05055   */
05056 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx)
05057 {
05058   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
05059 }
05060 #endif /* TAMP_CR1_TAMP1E */
05061
05062 #if defined(TAMP_CR1_TAMP2E)
05063 /**
05064   * @brief  Enable tamper 2 interrupt.
05065   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2
05066   * @param  TAMPx TAMP Instance
05067   * @retval None
05068   */
05069 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx)
05070 {
05071   SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
05072 }
05073
05074 /**
05075   * @brief  Disable tamper 2 interrupt.
05076   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_TAMP2
05077   * @param  TAMPx TAMP Instance
05078   * @retval None
05079   */
05080 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx)
05081 {
05082   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
05083 }
05084 #endif /* TAMP_CR1_TAMP2E */
05085
05086 #if defined(TAMP_CR1_TAMP3E)
05087 /**
05088   * @brief  Enable tamper 3 interrupt.
05089   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
05090   * @param  TAMPx TAMP Instance
05091   * @retval None
05092   */
05093 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(TAMP_TypeDef *TAMPx)
05094 {
05095   SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
05096 }
05097
05098 /**
05099   * @brief  Disable tamper 3 interrupt.
05100   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3
05101   * @param  TAMPx TAMP Instance
05102   * @retval None
05103   */
05104 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx)
05105 {
05106   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
05107 }
05108 #endif /* TAMP_CR1_TAMP3E */
05109
05110 #if defined(TAMP_CR1_TAMP1E)
05111 /**
05112   * @brief  Check if tamper 1 interrupt is enabled or not.
05113   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1
05114   * @param  TAMPx TAMP Instance
05115   * @retval State of bit (1 or 0).
05116   */
05117 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx)
05118 {
05119   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
05120 }
05121 #endif /* TAMP_CR1_TAMP1E */
05122
05123 #if defined(TAMP_CR1_TAMP2E)
05124 /**
05125   * @brief  Check if tamper 2 interrupt is enabled or not.
05126   * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2
05127   * @param  TAMPx TAMP Instance
05128   * @retval State of bit (1 or 0).
05129   */
05130 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx)
05131 {
05132   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
05133 }
05134 #endif /* TAMP_CR1_TAMP2E */
05135
05136 #if defined(TAMP_CR1_TAMP3E)
05137 /**
05138   * @brief  Check if tamper 3 interrupt is enabled or not.
05139   * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
05140   * @param  TAMPx TAMP Instance
05141   * @retval State of bit (1 or 0).
05142   */
05143 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx)
05144 {
05145   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
05146 }
05147 #endif /* TAMP_CR1_TAMP3E */
05148
05149 /**
05150   * @}
05151   */
05152
05153 #if defined (TAMP_ATCR1_TAMP1AM)
05154 /** @defgroup RTC_LL_EF_Active_Tamper Active Tamper
05155   * @{
05156   */
05157 /**
05158   * @brief  Enable tamper active mode.
05159   * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode
05160   * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode
05161   * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_EnableActiveMode
05162   * @param  Tamper to configure as active. This parameter can be a combination of the following values:
05163   *         @arg @ref RTC_LL_EC_ACTIVE_MODE
05164   *
05165   * @retval None
05166   */
05167 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
05168 {
05169   SET_BIT(TAMP->ATCR1, Tamper);
05170 }
05171
05172 /**
05173   * @brief  Disable tamper active mode.
05174   * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode
05175   * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode
05176   * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_DisableActiveMode
05177   * @param  Tamper to configure as active. This parameter can be a combination of the following values:
05178   *         @arg @ref RTC_LL_EC_ACTIVE_MODE
05179   *
05180   * @retval None
05181   */
05182 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
05183 {
05184   CLEAR_BIT(TAMP->ATCR1, Tamper);
05185 }
05186
05187 /**
05188   * @brief  Enable active tamper filter.
05189   * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_EnableFilter
05190   * @retval None
05191   */
05192 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)
05193 {
05194   SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
05195 }
05196
05197 /**
05198   * @brief  Disable active tamper filter.
05199   * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_DisableFilter
05200   * @retval None
05201   */
05202 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)
05203 {
05204   CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
05205 }
05206
05207 /**
05208   * @brief  Set Active tamper output change period.
05209   * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod
05210   * @param  ActiveOutputChangePeriod This parameter can be a value from 0 to 7
05211   * @retval None
05212   */
05213 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
05214 {
05215   MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
05216 }
05217
05218 /**
05219   * @brief  Get Active tamper output change period.
05220   * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod
05221   * @retval Output change period. This parameter can be a value from 0 to 7.
05222   */
05223 __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)
05224 {
05225   return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
05226 }
05227
05228 /**
05229   * @brief  Set Active tamper asynchronous prescaler clock selection.
05230   * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler
05231   * @param  ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock.
05232             This parameter can be a value of the following values:
05233   *         @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
05234   * @retval None
05235   */
05236 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
05237 {
05238   MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
05239 }
05240
05241 /**
05242   * @brief  Get Active tamper asynchronous prescaler clock selection.
05243   * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler
05244   * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
05245   */
05246 __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)
05247 {
05248   return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
05249 }
05250
05251 /**
05252   * @brief  Enable active tamper output sharing.
05253   * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_EnableOutputSharing
05254   * @retval None
05255   */
05256 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)
05257 {
05258   SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
05259 }
05260
05261 /**
05262   * @brief  Disable active tamper output sharing.
05263   * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_DisableOutputSharing
05264   * @retval None
05265   */
05266 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)
05267 {
05268   CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
05269 }
05270
05271 /**
05272   * @brief  Set Active tamper output selection.
05273   * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection
05274   * @param  OutputSelection Specifies all the output selection of the Active Tamper.
05275             This parameter is a combinasation of the following values:
05276   *         One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
05277   * @retval None
05278   */
05279 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
05280 {
05281   MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \
05282              OutputSelection);
05283 }
05284
05285 /**
05286   * @brief  Get Active tamper asynchronous prescaler clock selection.
05287   * @rmtoll TAMP_ATCR2     ATCKSEL       LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler
05288   * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
05289   */
05290 __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
05291 {
05292   return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));
05293 }
05294 #endif /* TAMP_ATCR1_TAMP1AM */
05295
05296 #if defined(ATSEEDR)
05297 /**
05298   * @brief  Write active tamper seed.
05299   * @rmtoll TAMP_ATSEEDR   SEED          LL_RTC_TAMPER_ATAMP_WriteSeed
05300   * @param  Seed
05301   * @retval None
05302   */
05303 __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
05304 {
05305   WRITE_REG(TAMP->ATSEEDR, Seed);
05306 }
05307 #endif /* ATSEEDR */
05308
05309 #if defined(TAMP_ATOR_INITS)
05310 /**
05311   * @brief  Get active tamper initialization status flag.
05312   * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS
05313   * @retval State of bit (1 or 0).
05314   */
05315 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)
05316 {
05317   return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
05318 }
05319
05320 /**
05321   * @brief  Get active tamper seed running status flag.
05322   * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS
05323   * @retval State of bit (1 or 0).
05324   */
05325 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
05326 {
05327   return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
05328 }
05329 #endif /* TAMP_ATOR_INITS */
05330
05331 /**
05332   * @}
05333   */
05334
05335
05336 #if defined(USE_FULL_LL_DRIVER)
05337 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
05338   * @{
05339   */
05340
05341 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
05342 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
05343 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
05344 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
05345 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
05346 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
05347 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
05348 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05349 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05350 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05351 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05352 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
05353 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
05354 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
05355
05356 /**
05357   * @}
05358   */
05359 #endif /* USE_FULL_LL_DRIVER */
05360
05361 /**
05362   * @}
05363   */
05364
05365 /**
05366   * @}
05367   */
05368
05369 #endif /* defined(RTC) */
05370
05371 /**
05372   * @}
05373   */
05374
05375 #ifdef __cplusplus
05376 }
05377 #endif
05378
05379 #endif /* STM32H7xx_LL_RTC_H */
05380
05381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_spi.c Source File

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stm32h7xx_ll_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_spi.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #include "stm32h7xx_ll_rcc.h"
00025 #ifdef GENERATOR_I2S_PRESENT
00026 #include "stm32h7xx_ll_rcc.h"
00027 #endif /* GENERATOR_I2S_PRESENT*/
00028 #ifdef  USE_FULL_ASSERT
00029 #include "stm32_assert.h"
00030 #else
00031 #define assert_param(expr) ((void)0U)
00032 #endif
00033
00034 /** @addtogroup STM32H7xx_LL_Driver
00035   * @{
00036   */
00037
00038 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
00039
00040 /** @addtogroup SPI_LL
00041   * @{
00042   */
00043
00044 /* Private types -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private constants ---------------------------------------------------------*/
00047 /* Private macros ------------------------------------------------------------*/
00048 /** @addtogroup SPI_LL_Private_Macros
00049   * @{
00050   */
00051
00052 #define IS_LL_SPI_MODE(__VALUE__)                   (((__VALUE__) == LL_SPI_MODE_MASTER)                 \
00053                                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00054
00055 #define IS_LL_SPI_SS_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE)         \
00056                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE)         \
00057                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE)         \
00058                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE)         \
00059                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE)         \
00060                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE)         \
00061                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE)         \
00062                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE)         \
00063                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE)         \
00064                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE)         \
00065                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE)         \
00066                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE)         \
00067                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE)         \
00068                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE)         \
00069                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE)         \
00070                                                   || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
00071
00072 #define IS_LL_SPI_ID_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE)         \
00073                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE)         \
00074                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE)         \
00075                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE)         \
00076                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE)         \
00077                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE)         \
00078                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE)         \
00079                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE)         \
00080                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE)         \
00081                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE)         \
00082                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE)         \
00083                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE)         \
00084                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE)         \
00085                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE)         \
00086                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE)         \
00087                                                   || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
00088
00089 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN)  \
00090                                                   || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
00091
00092 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN)  \
00093                                                   || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
00094
00095 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)    (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
00096                                                   || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED)    \
00097                                                   || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
00098
00099 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)  (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
00100                                                   || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME)   \
00101                                                   || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
00102
00103 #define IS_LL_SPI_PROTOCOL(__VALUE__)               (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA)           \
00104                                                   || ((__VALUE__) == LL_SPI_PROTOCOL_TI))
00105
00106 #define IS_LL_SPI_PHASE(__VALUE__)                  (((__VALUE__) == LL_SPI_PHASE_1EDGE)                 \
00107                                                   || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00108
00109 #define IS_LL_SPI_POLARITY(__VALUE__)               (((__VALUE__) == LL_SPI_POLARITY_LOW)                \
00110                                                   || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00111
00112 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)      (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
00113                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)      \
00114                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)      \
00115                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)     \
00116                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)     \
00117                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)     \
00118                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128)    \
00119                                                   || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00120
00121 #define IS_LL_SPI_BITORDER(__VALUE__)               (((__VALUE__) == LL_SPI_LSB_FIRST)                   \
00122                                                   || ((__VALUE__) == LL_SPI_MSB_FIRST))
00123
00124 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)     (((__VALUE__) == LL_SPI_FULL_DUPLEX)                 \
00125                                                   || ((__VALUE__) == LL_SPI_SIMPLEX_TX)                  \
00126                                                   || ((__VALUE__) == LL_SPI_SIMPLEX_RX)                  \
00127                                                   || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX)              \
00128                                                   || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00129
00130 #define IS_LL_SPI_DATAWIDTH(__VALUE__)              (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)              \
00131                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)              \
00132                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)              \
00133                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)              \
00134                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)              \
00135                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)              \
00136                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT)             \
00137                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT)             \
00138                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT)             \
00139                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT)             \
00140                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT)             \
00141                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT)             \
00142                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)             \
00143                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT)             \
00144                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT)             \
00145                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT)             \
00146                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT)             \
00147                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT)             \
00148                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT)             \
00149                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT)             \
00150                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT)             \
00151                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT)             \
00152                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT)             \
00153                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT)             \
00154                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT)             \
00155                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT)             \
00156                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT)             \
00157                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT)             \
00158                                                   || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
00159
00160 #define IS_LL_SPI_FIFO_TH(__VALUE__)                (((__VALUE__) == LL_SPI_FIFO_TH_01DATA)              \
00161                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA)              \
00162                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA)              \
00163                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA)              \
00164                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA)              \
00165                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA)              \
00166                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA)              \
00167                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA)              \
00168                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA)              \
00169                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA)              \
00170                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA)              \
00171                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA)              \
00172                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA)              \
00173                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA)              \
00174                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA)              \
00175                                                   || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
00176
00177 #define IS_LL_SPI_CRC(__VALUE__)                    (((__VALUE__) == LL_SPI_CRC_4BIT)                    \
00178                                                   || ((__VALUE__) == LL_SPI_CRC_5BIT)                    \
00179                                                   || ((__VALUE__) == LL_SPI_CRC_6BIT)                    \
00180                                                   || ((__VALUE__) == LL_SPI_CRC_7BIT)                    \
00181                                                   || ((__VALUE__) == LL_SPI_CRC_8BIT)                    \
00182                                                   || ((__VALUE__) == LL_SPI_CRC_9BIT)                    \
00183                                                   || ((__VALUE__) == LL_SPI_CRC_10BIT)                   \
00184                                                   || ((__VALUE__) == LL_SPI_CRC_11BIT)                   \
00185                                                   || ((__VALUE__) == LL_SPI_CRC_12BIT)                   \
00186                                                   || ((__VALUE__) == LL_SPI_CRC_13BIT)                   \
00187                                                   || ((__VALUE__) == LL_SPI_CRC_14BIT)                   \
00188                                                   || ((__VALUE__) == LL_SPI_CRC_15BIT)                   \
00189                                                   || ((__VALUE__) == LL_SPI_CRC_16BIT)                   \
00190                                                   || ((__VALUE__) == LL_SPI_CRC_17BIT)                   \
00191                                                   || ((__VALUE__) == LL_SPI_CRC_18BIT)                   \
00192                                                   || ((__VALUE__) == LL_SPI_CRC_19BIT)                   \
00193                                                   || ((__VALUE__) == LL_SPI_CRC_20BIT)                   \
00194                                                   || ((__VALUE__) == LL_SPI_CRC_21BIT)                   \
00195                                                   || ((__VALUE__) == LL_SPI_CRC_22BIT)                   \
00196                                                   || ((__VALUE__) == LL_SPI_CRC_23BIT)                   \
00197                                                   || ((__VALUE__) == LL_SPI_CRC_24BIT)                   \
00198                                                   || ((__VALUE__) == LL_SPI_CRC_25BIT)                   \
00199                                                   || ((__VALUE__) == LL_SPI_CRC_26BIT)                   \
00200                                                   || ((__VALUE__) == LL_SPI_CRC_27BIT)                   \
00201                                                   || ((__VALUE__) == LL_SPI_CRC_28BIT)                   \
00202                                                   || ((__VALUE__) == LL_SPI_CRC_29BIT)                   \
00203                                                   || ((__VALUE__) == LL_SPI_CRC_30BIT)                   \
00204                                                   || ((__VALUE__) == LL_SPI_CRC_31BIT)                   \
00205                                                   || ((__VALUE__) == LL_SPI_CRC_32BIT))
00206
00207 #define IS_LL_SPI_NSS(__VALUE__)                    (((__VALUE__) == LL_SPI_NSS_SOFT)                    \
00208                                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT)              \
00209                                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00210
00211 #define IS_LL_SPI_RX_FIFO(__VALUE__)                (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET)             \
00212                                                   || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET)             \
00213                                                   || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET)             \
00214                                                   || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
00215
00216 #define IS_LL_SPI_CRCCALCULATION(__VALUE__)         (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE)       \
00217                                                   || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00218
00219 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__)          ((__VALUE__) >= 0x1UL)
00220
00221 /**
00222   * @}
00223   */
00224
00225 /* Private function prototypes -----------------------------------------------*/
00226
00227 /* Exported functions --------------------------------------------------------*/
00228 /** @addtogroup SPI_LL_Exported_Functions
00229   * @{
00230   */
00231
00232 /** @addtogroup SPI_LL_EF_Init
00233   * @{
00234   */
00235
00236 /**
00237   * @brief  De-initialize the SPI registers to their default reset values.
00238   * @param  SPIx SPI Instance
00239   * @retval An ErrorStatus enumeration value:
00240   *          - SUCCESS: SPI registers are de-initialized
00241   *          - ERROR: SPI registers are not de-initialized
00242   */
00243 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00244 {
00245   ErrorStatus status = ERROR;
00246
00247   /* Check the parameters */
00248   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00249
00250 #if defined(SPI1)
00251   if (SPIx == SPI1)
00252   {
00253     /* Force reset of SPI clock */
00254     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00255
00256     /* Release reset of SPI clock */
00257     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00258
00259     status = SUCCESS;
00260   }
00261 #endif /* SPI1 */
00262 #if defined(SPI2)
00263   if (SPIx == SPI2)
00264   {
00265     /* Force reset of SPI clock */
00266     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00267
00268     /* Release reset of SPI clock */
00269     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00270
00271     status = SUCCESS;
00272   }
00273 #endif /* SPI2 */
00274 #if defined(SPI3)
00275   if (SPIx == SPI3)
00276   {
00277     /* Force reset of SPI clock */
00278     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00279
00280     /* Release reset of SPI clock */
00281     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00282
00283     status = SUCCESS;
00284   }
00285 #endif /* SPI3 */
00286 #if defined(SPI4)
00287   if (SPIx == SPI4)
00288   {
00289     /* Force reset of SPI clock */
00290     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
00291
00292     /* Release reset of SPI clock */
00293     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
00294
00295     status = SUCCESS;
00296   }
00297 #endif /* SPI4 */
00298 #if defined(SPI5)
00299   if (SPIx == SPI5)
00300   {
00301     /* Force reset of SPI clock */
00302     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
00303
00304     /* Release reset of SPI clock */
00305     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
00306
00307     status = SUCCESS;
00308   }
00309 #endif /* SPI5 */
00310 #if defined(SPI6)
00311   if (SPIx == SPI6)
00312   {
00313     /* Force reset of SPI clock */
00314     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
00315
00316     /* Release reset of SPI clock */
00317     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
00318
00319     status = SUCCESS;
00320   }
00321 #endif /* SPI6 */
00322
00323   return status;
00324 }
00325
00326 /**
00327   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00328   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00329   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00330   * @param  SPIx SPI Instance
00331   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00332   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00333   */
00334 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00335 {
00336   ErrorStatus status = ERROR;
00337   uint32_t tmp_nss;
00338   uint32_t tmp_mode;
00339
00340   /* Check the SPI Instance SPIx*/
00341   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00342
00343   /* Check the SPI parameters from SPI_InitStruct*/
00344   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00345   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00346   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00347   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00348   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00349   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00350   assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
00351   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00352   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00353
00354   if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
00355   {
00356     /*---------------------------- SPIx CFG1 Configuration ------------------------
00357        * Configure SPIx CFG1 with parameters:
00358        * - Master Baud Rate       : SPI_CFG1_MBR[2:0] bits
00359        * - CRC Computation Enable : SPI_CFG1_CRCEN bit
00360        * - Length of data frame   : SPI_CFG1_DSIZE[4:0] bits
00361        */
00362     MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR              | SPI_CFG1_CRCEN                 | SPI_CFG1_DSIZE,
00363                SPI_InitStruct->BaudRate  | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
00364
00365     tmp_nss  = SPI_InitStruct->NSS;
00366     tmp_mode = SPI_InitStruct->Mode;
00367
00368     /* Checks to setup Internal SS signal level and avoid a MODF Error */
00369     if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER))
00370     {
00371       LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
00372     }
00373
00374     /*---------------------------- SPIx CFG2 Configuration ------------------------
00375        * Configure SPIx CFG2 with parameters:
00376        * - NSS management         : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
00377        * - ClockPolarity          : SPI_CFG2_CPOL bit
00378        * - ClockPhase             : SPI_CFG2_CPHA bit
00379        * - BitOrder               : SPI_CFG2_LSBFRST bit
00380        * - Master/Slave Mode      : SPI_CFG2_MASTER bit
00381        * - SPI Mode               : SPI_CFG2_COMM[1:0] bits
00382        */
00383     MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM   | SPI_CFG2_SSOE    |
00384                SPI_CFG2_CPOL              | SPI_CFG2_CPHA    |
00385                SPI_CFG2_LSBFRST           | SPI_CFG2_MASTER  | SPI_CFG2_COMM,
00386                SPI_InitStruct->NSS        |   SPI_InitStruct->ClockPolarity                    |
00387                SPI_InitStruct->ClockPhase |   SPI_InitStruct->BitOrder                         |
00388                SPI_InitStruct->Mode       | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
00389
00390     /*---------------------------- SPIx CR1 Configuration ------------------------
00391        * Configure SPIx CR1 with parameter:
00392        * - Half Duplex Direction  : SPI_CR1_HDDIR bit
00393        */
00394     MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
00395
00396     /*---------------------------- SPIx CRCPOLY Configuration ----------------------
00397        * Configure SPIx CRCPOLY with parameter:
00398        * - CRCPoly                : CRCPOLY[31:0] bits
00399        */
00400     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00401     {
00402       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00403       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00404     }
00405
00406     /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00407     CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00408
00409     status = SUCCESS;
00410   }
00411
00412   return status;
00413 }
00414
00415 /**
00416   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00417   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00418   * whose fields will be set to default values.
00419   * @retval None
00420   */
00421 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00422 {
00423   /* Set SPI_InitStruct fields to default values */
00424   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00425   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00426   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00427   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00428   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00429   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00430   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00431   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00432   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00433   SPI_InitStruct->CRCPoly           = 7UL;
00434 }
00435
00436 /**
00437   * @}
00438   */
00439
00440 /**
00441   * @}
00442   */
00443
00444 /**
00445   * @}
00446   */
00447
00448 /** @addtogroup I2S_LL
00449   * @{
00450   */
00451
00452 /* Private types -------------------------------------------------------------*/
00453 /* Private variables ---------------------------------------------------------*/
00454 /* Private constants ---------------------------------------------------------*/
00455 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
00456   * @{
00457   */
00458 /* I2S registers Masks */
00459 #define I2S_I2SCFGR_CLEAR_MASK                       (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
00460                                                       SPI_I2SCFGR_DATFMT  | SPI_I2SCFGR_CKPOL  | \
00461                                                       SPI_I2SCFGR_I2SSTD  | SPI_I2SCFGR_MCKOE  | \
00462                                                       SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
00463
00464 /**
00465   * @}
00466   */
00467 /* Private macros ------------------------------------------------------------*/
00468 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
00469   * @{
00470   */
00471
00472 #define IS_LL_I2S_DATAFORMAT(__VALUE__)            (((__VALUE__) == LL_I2S_DATAFORMAT_16B)              \
00473                                                  || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED)     \
00474                                                  || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)              \
00475                                                  || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
00476                                                  || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
00477
00478 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__)  (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH)    \
00479                                                  || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
00480
00481 #define IS_LL_I2S_CKPOL(__VALUE__)                  (((__VALUE__) == LL_I2S_POLARITY_LOW)               \
00482                                                  || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
00483
00484 #define IS_LL_I2S_STANDARD(__VALUE__)              (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)            \
00485                                                  || ((__VALUE__) == LL_I2S_STANDARD_MSB)                \
00486                                                  || ((__VALUE__) == LL_I2S_STANDARD_LSB)                \
00487                                                  || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT)          \
00488                                                  || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
00489
00490 #define IS_LL_I2S_MODE(__VALUE__)                  (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)               \
00491                                                  || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)               \
00492                                                  || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX)      \
00493                                                  || ((__VALUE__) == LL_I2S_MODE_MASTER_TX)              \
00494                                                  || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)              \
00495                                                  || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
00496
00497 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__)           (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE)          \
00498                                                  || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
00499
00500 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__)           ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)                \
00501                                                  && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K))             \
00502                                                  || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
00503
00504 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)       ((__VALUE__) <= 0xFFUL)
00505
00506 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__)      (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN)       \
00507                                                  || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
00508
00509 #define IS_LL_I2S_FIFO_TH (__VALUE__)              (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA)       \
00510                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA)       \
00511                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA)       \
00512                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA)       \
00513                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA)       \
00514                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA)       \
00515                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA)       \
00516                                                  || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
00517
00518 #define IS_LL_I2S_BIT_ORDER(__VALUE__)             (((__VALUE__) == LL_I2S_LSB_FIRST)                   \
00519                                                  || ((__VALUE__) == LL_I2S_MSB_FIRST))
00520 /**
00521   * @}
00522   */
00523
00524 /* Private function prototypes -----------------------------------------------*/
00525
00526 /* Exported functions --------------------------------------------------------*/
00527 /** @addtogroup I2S_LL_Exported_Functions
00528   * @{
00529   */
00530
00531 /** @addtogroup I2S_LL_EF_Init
00532   * @{
00533   */
00534
00535 /**
00536   * @brief  De-initialize the SPI/I2S registers to their default reset values.
00537   * @param  SPIx SPI Instance
00538   * @retval An ErrorStatus enumeration value:
00539   *          - SUCCESS: SPI registers are de-initialized
00540   *          - ERROR: SPI registers are not de-initialized
00541   */
00542 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
00543 {
00544   return LL_SPI_DeInit(SPIx);
00545 }
00546
00547 /**
00548   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
00549   * @note   As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00550   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00551   * @note   I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
00552   * @param  SPIx SPI Instance
00553   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00554   * @retval An ErrorStatus enumeration value:
00555   *          - SUCCESS: SPI registers are Initialized
00556   *          - ERROR: SPI registers are not Initialized
00557   */
00558 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
00559 {
00560   uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL;
00561   uint32_t tmp;
00562   uint32_t sourceclock;
00563   ErrorStatus status = ERROR;
00564
00565   /* Check the I2S parameters */
00566   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00567   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00568   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00569   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00570   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
00571   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
00572   assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
00573
00574   /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
00575    * In this case, it is useless to check if the I2SMOD bit is set to 0 because
00576    * this bit I2SMOD only serves to select the desired mode.
00577    */
00578   if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
00579   {
00580     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00581      * Configure SPIx I2SCFGR with parameters:
00582      * - Mode           : SPI_I2SCFGR_I2SCFG[2:0] bits
00583      * - Standard       : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00584      * - DataFormat     : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
00585      * - ClockPolarity  : SPI_I2SCFGR_CKPOL bit
00586      * - MCLKOutput     : SPI_I2SPR_MCKOE bit
00587      * - I2S mode       : SPI_I2SCFGR_I2SMOD bit
00588      */
00589
00590     /* Write to SPIx I2SCFGR */
00591     MODIFY_REG(SPIx->I2SCFGR,
00592                I2S_I2SCFGR_CLEAR_MASK,
00593                I2S_InitStruct->Mode       | I2S_InitStruct->Standard      |
00594                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00595                I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
00596
00597     /*---------------------------- SPIx I2SCFGR Configuration ----------------------
00598      * Configure SPIx I2SCFGR with parameters:
00599      * - AudioFreq      : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
00600      */
00601
00602     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
00603      * else, default values are used:  i2sodd = 0U, i2sdiv = 0U.
00604      */
00605     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
00606     {
00607       /* Check the frame length (For the Prescaler computing)
00608        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
00609        */
00610       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
00611       {
00612         /* Packet length is 32 bits */
00613         packetlength = 2UL;
00614       }
00615
00616       /* Check if PCM standard is used */
00617       if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
00618           (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
00619       {
00620         ispcm = 1UL;
00621       }
00622
00623       /* Get the I2S (SPI) source clock value */
00624 #if defined (SPI_SPI6I2S_SUPPORT)
00625       if (SPIx == SPI6)
00626       {
00627         sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
00628       }
00629       else
00630       {
00631         sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
00632       }
00633 #else
00634       sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
00635 #endif
00636
00637       /* Compute the Real divider depending on the MCLK output state with a fixed point */
00638       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
00639       {
00640         /* MCLK output is enabled */
00641         tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
00642       }
00643       else
00644       {
00645         /* MCLK output is disabled */
00646         tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
00647       }
00648
00649       /* Remove the fixed point */
00650       tmp = tmp / 16UL;
00651
00652       /* Check the parity of the divider */
00653       i2sodd = tmp & 0x1UL;
00654
00655       /* Compute the i2sdiv prescaler */
00656       i2sdiv = tmp / 2UL;
00657     }
00658
00659     /* Test if the obtain values are forbiden or out of range */
00660     if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
00661     {
00662       /* Set the default values */
00663       i2sdiv = 0UL;
00664       i2sodd = 0UL;
00665     }
00666
00667     /* Write to SPIx I2SCFGR register the computed value */
00668     MODIFY_REG(SPIx->I2SCFGR,
00669                SPI_I2SCFGR_ODD                 | SPI_I2SCFGR_I2SDIV,
00670                (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
00671
00672     status = SUCCESS;
00673   }
00674
00675   return status;
00676 }
00677
00678 /**
00679   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
00680   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00681   *         whose fields will be set to default values.
00682   * @retval None
00683   */
00684 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
00685 {
00686   /*--------------- Reset I2S init structure parameters values -----------------*/
00687   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
00688   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
00689   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
00690   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
00691   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
00692   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
00693 }
00694
00695 /**
00696   * @brief  Set linear and parity prescaler.
00697   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
00698   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
00699   * @param  SPIx SPI Instance
00700   * @param  PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
00701   * @note   PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
00702   * @param  PrescalerParity This parameter can be one of the following values:
00703   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00704   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00705   * @retval None
00706   */
00707 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
00708 {
00709   /* Check the I2S parameters */
00710   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00711   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
00712   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
00713
00714   /* Write to SPIx I2SPR */
00715   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
00716              (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
00717 }
00718
00719 /**
00720   * @}
00721   */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /**
00728   * @}
00729   */
00730
00731 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
00732
00733 /**
00734   * @}
00735   */
00736 #endif /* USE_FULL_LL_DRIVER */
00737
00738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_spi.h Source File

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stm32h7xx_ll_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_SPI_H
00022 #define STM32H7xx_LL_SPI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
00036
00037 /** @defgroup SPI_LL SPI
00038   * @{
00039   */
00040
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044
00045 /* Private macros ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00048   * @{
00049   */
00050
00051 /**
00052   * @brief  SPI Init structures definition
00053   */
00054 typedef struct
00055 {
00056   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00057                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00058
00059                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00060
00061   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00062                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00063
00064                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00065
00066   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00067                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00068
00069                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00070
00071   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00072                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00073
00074                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00075
00076   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00077                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00078
00079                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00080
00081   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00082                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00083
00084                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00085
00086   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00087                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00088                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00089
00090                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00091
00092   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00094
00095                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00096
00097   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00098                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00099
00100                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00101
00102   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00103                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.
00104
00105                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00106
00107 } LL_SPI_InitTypeDef;
00108
00109 /**
00110   * @}
00111   */
00112 #endif /*USE_FULL_LL_DRIVER*/
00113
00114 /* Exported types ------------------------------------------------------------*/
00115
00116 /* Exported constants --------------------------------------------------------*/
00117 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00122   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00123   * @{
00124   */
00125 #define LL_SPI_SR_RXP                              (SPI_SR_RXP)
00126 #define LL_SPI_SR_TXP                              (SPI_SR_TXP)
00127 #define LL_SPI_SR_DXP                              (SPI_SR_DXP)
00128 #define LL_SPI_SR_EOT                              (SPI_SR_EOT)
00129 #define LL_SPI_SR_TXTF                             (SPI_SR_TXTF)
00130 #define LL_SPI_SR_UDR                              (SPI_SR_UDR)
00131 #define LL_SPI_SR_CRCE                             (SPI_SR_CRCE)
00132 #define LL_SPI_SR_MODF                             (SPI_SR_MODF)
00133 #define LL_SPI_SR_OVR                              (SPI_SR_OVR)
00134 #define LL_SPI_SR_TIFRE                            (SPI_SR_TIFRE)
00135 #define LL_SPI_SR_TSERF                            (SPI_SR_TSERF)
00136 #define LL_SPI_SR_SUSP                             (SPI_SR_SUSP)
00137 #define LL_SPI_SR_TXC                              (SPI_SR_TXC)
00138 #define LL_SPI_SR_RXWNE                            (SPI_SR_RXWNE)
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup SPI_LL_EC_IT IT Defines
00144   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00145   * @{
00146   */
00147 #define LL_SPI_IER_RXPIE                           (SPI_IER_RXPIE)
00148 #define LL_SPI_IER_TXPIE                           (SPI_IER_TXPIE)
00149 #define LL_SPI_IER_DXPIE                           (SPI_IER_DXPIE)
00150 #define LL_SPI_IER_EOTIE                           (SPI_IER_EOTIE)
00151 #define LL_SPI_IER_TXTFIE                          (SPI_IER_TXTFIE)
00152 #define LL_SPI_IER_UDRIE                           (SPI_IER_UDRIE)
00153 #define LL_SPI_IER_OVRIE                           (SPI_IER_OVRIE)
00154 #define LL_SPI_IER_CRCEIE                          (SPI_IER_CRCEIE)
00155 #define LL_SPI_IER_TIFREIE                         (SPI_IER_TIFREIE)
00156 #define LL_SPI_IER_MODFIE                          (SPI_IER_MODFIE)
00157 #define LL_SPI_IER_TSERFIE                         (SPI_IER_TSERFIE)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup SPI_LL_EC_MODE Mode
00163   * @{
00164   */
00165 #define LL_SPI_MODE_MASTER                         (SPI_CFG2_MASTER)
00166 #define LL_SPI_MODE_SLAVE                          (0x00000000UL)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
00172   * @{
00173   */
00174 #define LL_SPI_SS_LEVEL_HIGH                       (SPI_CR1_SSI)
00175 #define LL_SPI_SS_LEVEL_LOW                        (0x00000000UL)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
00181   * @{
00182   */
00183 #define LL_SPI_SS_IDLENESS_00CYCLE                 (0x00000000UL)
00184 #define LL_SPI_SS_IDLENESS_01CYCLE                 (SPI_CFG2_MSSI_0)
00185 #define LL_SPI_SS_IDLENESS_02CYCLE                 (SPI_CFG2_MSSI_1)
00186 #define LL_SPI_SS_IDLENESS_03CYCLE                 (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
00187 #define LL_SPI_SS_IDLENESS_04CYCLE                 (SPI_CFG2_MSSI_2)
00188 #define LL_SPI_SS_IDLENESS_05CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
00189 #define LL_SPI_SS_IDLENESS_06CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
00190 #define LL_SPI_SS_IDLENESS_07CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
00191 #define LL_SPI_SS_IDLENESS_08CYCLE                 (SPI_CFG2_MSSI_3)
00192 #define LL_SPI_SS_IDLENESS_09CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
00193 #define LL_SPI_SS_IDLENESS_10CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
00194 #define LL_SPI_SS_IDLENESS_11CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
00195 #define LL_SPI_SS_IDLENESS_12CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
00196 #define LL_SPI_SS_IDLENESS_13CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
00197 #define LL_SPI_SS_IDLENESS_14CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
00198 #define LL_SPI_SS_IDLENESS_15CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
00204   * @{
00205   */
00206 #define LL_SPI_ID_IDLENESS_00CYCLE                 (0x00000000UL)
00207 #define LL_SPI_ID_IDLENESS_01CYCLE                 (SPI_CFG2_MIDI_0)
00208 #define LL_SPI_ID_IDLENESS_02CYCLE                 (SPI_CFG2_MIDI_1)
00209 #define LL_SPI_ID_IDLENESS_03CYCLE                 (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
00210 #define LL_SPI_ID_IDLENESS_04CYCLE                 (SPI_CFG2_MIDI_2)
00211 #define LL_SPI_ID_IDLENESS_05CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
00212 #define LL_SPI_ID_IDLENESS_06CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
00213 #define LL_SPI_ID_IDLENESS_07CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
00214 #define LL_SPI_ID_IDLENESS_08CYCLE                 (SPI_CFG2_MIDI_3)
00215 #define LL_SPI_ID_IDLENESS_09CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
00216 #define LL_SPI_ID_IDLENESS_10CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
00217 #define LL_SPI_ID_IDLENESS_11CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
00218 #define LL_SPI_ID_IDLENESS_12CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
00219 #define LL_SPI_ID_IDLENESS_13CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
00220 #define LL_SPI_ID_IDLENESS_14CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
00221 #define LL_SPI_ID_IDLENESS_15CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
00227   * @{
00228   */
00229 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)
00230 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_TCRCINI)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
00236   * @{
00237   */
00238 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)
00239 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_RCRCINI)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
00245   * @{
00246   */
00247 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN         (0x00000000UL)
00248 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED            (SPI_CFG1_UDRCFG_0)
00249 #define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED         (SPI_CFG1_UDRCFG_1)
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
00255   * @{
00256   */
00257 #define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME         (0x00000000UL)
00258 #define LL_SPI_UDR_DETECT_END_DATA_FRAME           (SPI_CFG1_UDRDET_0)
00259 #define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS         (SPI_CFG1_UDRDET_1)
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
00265   * @{
00266   */
00267 #define LL_SPI_PROTOCOL_MOTOROLA                   (0x00000000UL)
00268 #define LL_SPI_PROTOCOL_TI                         (SPI_CFG2_SP_0)
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup SPI_LL_EC_PHASE Phase
00274   * @{
00275   */
00276 #define LL_SPI_PHASE_1EDGE                         (0x00000000UL)
00277 #define LL_SPI_PHASE_2EDGE                         (SPI_CFG2_CPHA)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup SPI_LL_EC_POLARITY Polarity
00283   * @{
00284   */
00285 #define LL_SPI_POLARITY_LOW                        (0x00000000UL)
00286 #define LL_SPI_POLARITY_HIGH                       (SPI_CFG2_CPOL)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
00292   * @{
00293   */
00294 #define LL_SPI_NSS_POLARITY_LOW                    (0x00000000UL)
00295 #define LL_SPI_NSS_POLARITY_HIGH                   (SPI_CFG2_SSIOP)
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00301   * @{
00302   */
00303 #define LL_SPI_BAUDRATEPRESCALER_DIV2              (0x00000000UL)
00304 #define LL_SPI_BAUDRATEPRESCALER_DIV4              (SPI_CFG1_MBR_0)
00305 #define LL_SPI_BAUDRATEPRESCALER_DIV8              (SPI_CFG1_MBR_1)
00306 #define LL_SPI_BAUDRATEPRESCALER_DIV16             (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
00307 #define LL_SPI_BAUDRATEPRESCALER_DIV32             (SPI_CFG1_MBR_2)
00308 #define LL_SPI_BAUDRATEPRESCALER_DIV64             (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
00309 #define LL_SPI_BAUDRATEPRESCALER_DIV128            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
00310 #define LL_SPI_BAUDRATEPRESCALER_DIV256            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
00316   * @{
00317   */
00318 #define LL_SPI_LSB_FIRST                           (SPI_CFG2_LSBFRST)
00319 #define LL_SPI_MSB_FIRST                           (0x00000000UL)
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00325   * @{
00326   */
00327 #define LL_SPI_FULL_DUPLEX                         (0x00000000UL)
00328 #define LL_SPI_SIMPLEX_TX                          (SPI_CFG2_COMM_0)
00329 #define LL_SPI_SIMPLEX_RX                          (SPI_CFG2_COMM_1)
00330 #define LL_SPI_HALF_DUPLEX_RX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
00331 #define LL_SPI_HALF_DUPLEX_TX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
00337   * @{
00338   */
00339 #define LL_SPI_DATAWIDTH_4BIT                      (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
00340 #define LL_SPI_DATAWIDTH_5BIT                      (SPI_CFG1_DSIZE_2)
00341 #define LL_SPI_DATAWIDTH_6BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
00342 #define LL_SPI_DATAWIDTH_7BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
00343 #define LL_SPI_DATAWIDTH_8BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00344 #define LL_SPI_DATAWIDTH_9BIT                      (SPI_CFG1_DSIZE_3)
00345 #define LL_SPI_DATAWIDTH_10BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
00346 #define LL_SPI_DATAWIDTH_11BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
00347 #define LL_SPI_DATAWIDTH_12BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00348 #define LL_SPI_DATAWIDTH_13BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
00349 #define LL_SPI_DATAWIDTH_14BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
00350 #define LL_SPI_DATAWIDTH_15BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
00351 #define LL_SPI_DATAWIDTH_16BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00352 #define LL_SPI_DATAWIDTH_17BIT                     (SPI_CFG1_DSIZE_4)
00353 #define LL_SPI_DATAWIDTH_18BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
00354 #define LL_SPI_DATAWIDTH_19BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
00355 #define LL_SPI_DATAWIDTH_20BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
00356 #define LL_SPI_DATAWIDTH_21BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
00357 #define LL_SPI_DATAWIDTH_22BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
00358 #define LL_SPI_DATAWIDTH_23BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
00359 #define LL_SPI_DATAWIDTH_24BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00360 #define LL_SPI_DATAWIDTH_25BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
00361 #define LL_SPI_DATAWIDTH_26BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
00362 #define LL_SPI_DATAWIDTH_27BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
00363 #define LL_SPI_DATAWIDTH_28BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00364 #define LL_SPI_DATAWIDTH_29BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
00365 #define LL_SPI_DATAWIDTH_30BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
00366 #define LL_SPI_DATAWIDTH_31BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
00367 #define LL_SPI_DATAWIDTH_32BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
00373   * @{
00374   */
00375 #define LL_SPI_FIFO_TH_01DATA                      (0x00000000UL)
00376 #define LL_SPI_FIFO_TH_02DATA                      (SPI_CFG1_FTHLV_0)
00377 #define LL_SPI_FIFO_TH_03DATA                      (SPI_CFG1_FTHLV_1)
00378 #define LL_SPI_FIFO_TH_04DATA                      (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
00379 #define LL_SPI_FIFO_TH_05DATA                      (SPI_CFG1_FTHLV_2)
00380 #define LL_SPI_FIFO_TH_06DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
00381 #define LL_SPI_FIFO_TH_07DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
00382 #define LL_SPI_FIFO_TH_08DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
00383 #define LL_SPI_FIFO_TH_09DATA                      (SPI_CFG1_FTHLV_3)
00384 #define LL_SPI_FIFO_TH_10DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
00385 #define LL_SPI_FIFO_TH_11DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
00386 #define LL_SPI_FIFO_TH_12DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
00387 #define LL_SPI_FIFO_TH_13DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
00388 #define LL_SPI_FIFO_TH_14DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
00389 #define LL_SPI_FIFO_TH_15DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
00390 #define LL_SPI_FIFO_TH_16DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
00391 /**
00392   * @}
00393   */
00394
00395 #if defined(USE_FULL_LL_DRIVER)
00396
00397 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00398   * @{
00399   */
00400 #define LL_SPI_CRCCALCULATION_DISABLE              (0x00000000UL)            /*!< CRC calculation disabled */
00401 #define LL_SPI_CRCCALCULATION_ENABLE               (SPI_CFG1_CRCEN)          /*!< CRC calculation enabled  */
00402 /**
00403   * @}
00404   */
00405 #endif /* USE_FULL_LL_DRIVER */
00406
00407 /** @defgroup SPI_LL_EC_CRC CRC
00408   * @{
00409   */
00410 #define LL_SPI_CRC_4BIT                            (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
00411 #define LL_SPI_CRC_5BIT                            (SPI_CFG1_CRCSIZE_2)
00412 #define LL_SPI_CRC_6BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
00413 #define LL_SPI_CRC_7BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
00414 #define LL_SPI_CRC_8BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00415 #define LL_SPI_CRC_9BIT                            (SPI_CFG1_CRCSIZE_3)
00416 #define LL_SPI_CRC_10BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
00417 #define LL_SPI_CRC_11BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
00418 #define LL_SPI_CRC_12BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00419 #define LL_SPI_CRC_13BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
00420 #define LL_SPI_CRC_14BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
00421 #define LL_SPI_CRC_15BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
00422 #define LL_SPI_CRC_16BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00423 #define LL_SPI_CRC_17BIT                           (SPI_CFG1_CRCSIZE_4)
00424 #define LL_SPI_CRC_18BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
00425 #define LL_SPI_CRC_19BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
00426 #define LL_SPI_CRC_20BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
00427 #define LL_SPI_CRC_21BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
00428 #define LL_SPI_CRC_22BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
00429 #define LL_SPI_CRC_23BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
00430 #define LL_SPI_CRC_24BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00431 #define LL_SPI_CRC_25BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
00432 #define LL_SPI_CRC_26BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
00433 #define LL_SPI_CRC_27BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
00434 #define LL_SPI_CRC_28BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00435 #define LL_SPI_CRC_29BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
00436 #define LL_SPI_CRC_30BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
00437 #define LL_SPI_CRC_31BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
00438 #define LL_SPI_CRC_32BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
00444   * @{
00445   */
00446 #define LL_SPI_NSS_SOFT                            (SPI_CFG2_SSM)
00447 #define LL_SPI_NSS_HARD_INPUT                      (0x00000000UL)
00448 #define LL_SPI_NSS_HARD_OUTPUT                     (SPI_CFG2_SSOE)
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
00454   * @{
00455   */
00456 #define LL_SPI_RX_FIFO_0PACKET                     (0x00000000UL)                      /* 0 or multiple of 4 packet available is the RxFIFO */
00457 #define LL_SPI_RX_FIFO_1PACKET                     (SPI_SR_RXPLVL_0)
00458 #define LL_SPI_RX_FIFO_2PACKET                     (SPI_SR_RXPLVL_1)
00459 #define LL_SPI_RX_FIFO_3PACKET                     (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
00460 /**
00461   * @}
00462   */
00463
00464 /**
00465   * @}
00466   */
00467
00468 /* Exported macro ------------------------------------------------------------*/
00469 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00470   * @{
00471   */
00472
00473 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00474   * @{
00475   */
00476
00477 /**
00478   * @brief  Write a value in SPI register
00479   * @param  __INSTANCE__ SPI Instance
00480   * @param  __REG__ Register to be written
00481   * @param  __VALUE__ Value to be written in the register
00482   * @retval None
00483   */
00484 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00485
00486 /**
00487   * @brief  Read a value in SPI register
00488   * @param  __INSTANCE__ SPI Instance
00489   * @param  __REG__ Register to be read
00490   * @retval Register value
00491   */
00492 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00493 /**
00494   * @}
00495   */
00496
00497 /**
00498   * @}
00499   */
00500
00501
00502 /* Exported functions --------------------------------------------------------*/
00503
00504 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00505   * @{
00506   */
00507
00508 /** @defgroup SPI_LL_EF_Configuration Configuration
00509   * @{
00510   */
00511
00512 /**
00513   * @brief  Enable SPI peripheral
00514   * @rmtoll CR1          SPE           LL_SPI_Enable
00515   * @param  SPIx SPI Instance
00516   * @retval None
00517   */
00518 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00519 {
00520   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00521 }
00522
00523 /**
00524   * @brief  Disable SPI peripheral
00525   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00526   * @rmtoll CR1          SPE           LL_SPI_Disable
00527   * @param  SPIx SPI Instance
00528   * @retval None
00529   */
00530 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00531 {
00532   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00533 }
00534
00535 /**
00536   * @brief  Check if SPI peripheral is enabled
00537   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00538   * @param  SPIx SPI Instance
00539   * @retval State of bit (1 or 0)
00540   */
00541 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00542 {
00543   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
00544 }
00545
00546 /**
00547   * @brief  Swap the MOSI and MISO pin
00548   * @note   This configuration can not be changed when SPI is enabled.
00549   * @rmtoll CFG2         IOSWP         LL_SPI_EnableIOSwap
00550   * @param  SPIx SPI Instance
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
00554 {
00555   SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
00556 }
00557
00558 /**
00559   * @brief  Restore default function for MOSI and MISO pin
00560   * @note   This configuration can not be changed when SPI is enabled.
00561   * @rmtoll CFG2         IOSWP         LL_SPI_DisableIOSwap
00562   * @param  SPIx SPI Instance
00563   * @retval None
00564   */
00565 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
00566 {
00567   CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
00568 }
00569
00570 /**
00571   * @brief  Check if MOSI and MISO pin are swapped
00572   * @rmtoll CFG2         IOSWP         LL_SPI_IsEnabledIOSwap
00573   * @param  SPIx SPI Instance
00574   * @retval State of bit (1 or 0)
00575   */
00576 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
00577 {
00578   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
00579 }
00580
00581 /**
00582   * @brief  Enable GPIO control
00583   * @note   This configuration can not be changed when SPI is enabled.
00584   * @rmtoll CFG2         AFCNTR        LL_SPI_EnableGPIOControl
00585   * @param  SPIx SPI Instance
00586   * @retval None
00587   */
00588 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
00589 {
00590   SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
00591 }
00592
00593 /**
00594   * @brief  Disable GPIO control
00595   * @note   This configuration can not be changed when SPI is enabled.
00596   * @rmtoll CFG2         AFCNTR        LL_SPI_DisableGPIOControl
00597   * @param  SPIx SPI Instance
00598   * @retval None
00599   */
00600 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
00601 {
00602   CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
00603 }
00604
00605 /**
00606   * @brief  Check if GPIO control is active
00607   * @rmtoll CFG2         AFCNTR        LL_SPI_IsEnabledGPIOControl
00608   * @param  SPIx SPI Instance
00609   * @retval State of bit (1 or 0)
00610   */
00611 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
00612 {
00613   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
00614 }
00615
00616 /**
00617   * @brief  Set SPI Mode to Master or Slave
00618   * @note   This configuration can not be changed when SPI is enabled.
00619   * @rmtoll CFG2         MASTER        LL_SPI_SetMode
00620   * @param  SPIx SPI Instance
00621   * @param  Mode This parameter can be one of the following values:
00622   *         @arg @ref LL_SPI_MODE_MASTER
00623   *         @arg @ref LL_SPI_MODE_SLAVE
00624   * @retval None
00625   */
00626 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00627 {
00628   MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
00629 }
00630
00631 /**
00632   * @brief  Get SPI Mode (Master or Slave)
00633   * @rmtoll CFG2         MASTER        LL_SPI_GetMode
00634   * @param  SPIx SPI Instance
00635   * @retval Returned value can be one of the following values:
00636   *         @arg @ref LL_SPI_MODE_MASTER
00637   *         @arg @ref LL_SPI_MODE_SLAVE
00638   */
00639 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00640 {
00641   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
00642 }
00643
00644 /**
00645   * @brief  Configure the Idleness applied by master between active edge of SS and first send data
00646   * @rmtoll CFG2         MSSI          LL_SPI_SetMasterSSIdleness
00647   * @param  SPIx SPI Instance
00648   * @param  MasterSSIdleness This parameter can be one of the following values:
00649   *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
00650   *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
00651   *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
00652   *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
00653   *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
00654   *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
00655   *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
00656   *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
00657   *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
00658   *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
00659   *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
00660   *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
00661   *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
00662   *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
00663   *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
00664   *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
00668 {
00669   MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
00670 }
00671
00672 /**
00673   * @brief  Get the configured Idleness applied by master
00674   * @rmtoll CFG2         MSSI          LL_SPI_GetMasterSSIdleness
00675   * @param  SPIx SPI Instance
00676   * @retval Returned value can be one of the following values:
00677   *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
00678   *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
00679   *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
00680   *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
00681   *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
00682   *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
00683   *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
00684   *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
00685   *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
00686   *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
00687   *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
00688   *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
00689   *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
00690   *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
00691   *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
00692   *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
00693   */
00694 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
00695 {
00696   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
00697 }
00698
00699 /**
00700   * @brief  Configure the idleness applied by master between data frame
00701   * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness
00702   * @param  SPIx SPI Instance
00703   * @param  MasterInterDataIdleness This parameter can be one of the following values:
00704   *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
00705   *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
00706   *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
00707   *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
00708   *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
00709   *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
00710   *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
00711   *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
00712   *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
00713   *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
00714   *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
00715   *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
00716   *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
00717   *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
00718   *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
00719   *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
00720   * @retval None
00721   */
00722 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
00723 {
00724   MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
00725 }
00726
00727 /**
00728   * @brief  Get the configured inter data idleness
00729   * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness
00730   * @param  SPIx SPI Instance
00731   * @retval Returned value can be one of the following values:
00732   *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
00733   *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
00734   *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
00735   *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
00736   *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
00737   *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
00738   *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
00739   *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
00740   *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
00741   *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
00742   *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
00743   *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
00744   *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
00745   *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
00746   *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
00747   *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
00748   */
00749 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
00750 {
00751   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
00752 }
00753
00754 /**
00755   * @brief  Set transfer size
00756   * @note    Count is the number of frame to be transferred
00757   * @rmtoll CR2          TSIZE         LL_SPI_SetTransferSize
00758   * @param  SPIx SPI Instance
00759   * @param  Count 0..0xFFFF
00760   * @retval None
00761   */
00762 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
00763 {
00764   MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
00765 }
00766
00767 /**
00768   * @brief  Get transfer size
00769   * @note    Count is the number of frame to be transferred
00770   * @rmtoll CR2          TSIZE         LL_SPI_GetTransferSize
00771   * @param  SPIx SPI Instance
00772   * @retval 0..0xFFFF
00773   */
00774 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
00775 {
00776   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
00777 }
00778
00779 /**
00780   * @brief  Set reload transfer size
00781   * @note    Count is the number of frame to be transferred
00782   * @rmtoll CR2          TSER          LL_SPI_SetReloadSize
00783   * @param  SPIx SPI Instance
00784   * @param  Count 0..0xFFFF
00785   * @retval None
00786   */
00787 __STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
00788 {
00789   MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
00790 }
00791
00792 /**
00793   * @brief  Get reload transfer size
00794   * @note    Count is the number of frame to be transferred
00795   * @rmtoll CR2          TSER          LL_SPI_GetReloadSize
00796   * @param  SPIx SPI Instance
00797   * @retval 0..0xFFFF
00798   */
00799 __STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
00800 {
00801   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
00802 }
00803
00804 /**
00805   * @brief  Lock the AF configuration of associated IOs
00806   * @note   Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
00807   *         the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
00808   * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock
00809   * @param  SPIx SPI Instance
00810   * @retval None
00811   */
00812 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
00813 {
00814   SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
00815 }
00816
00817 /**
00818   * @brief  Check if the AF configuration is locked.
00819   * @rmtoll CR1          IOLOCK        LL_SPI_IsEnabledIOLock
00820   * @param  SPIx SPI Instance
00821   * @retval State of bit (1 or 0)
00822   */
00823 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
00824 {
00825   return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
00826 }
00827
00828 /**
00829   * @brief  Set Tx CRC Initialization Pattern
00830   * @rmtoll CR1          TCRCINI         LL_SPI_SetTxCRCInitPattern
00831   * @param  SPIx SPI Instance
00832   * @param  TXCRCInitAll This parameter can be one of the following values:
00833   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
00834   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
00838 {
00839   MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
00840 }
00841
00842 /**
00843   * @brief  Get Tx CRC Initialization Pattern
00844   * @rmtoll CR1          TCRCINI         LL_SPI_GetTxCRCInitPattern
00845   * @param  SPIx SPI Instance
00846   * @retval Returned value can be one of the following values:
00847   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
00848   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
00849   */
00850 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
00851 {
00852   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
00853 }
00854
00855 /**
00856   * @brief  Set Rx CRC Initialization Pattern
00857   * @rmtoll CR1          RCRCINI         LL_SPI_SetRxCRCInitPattern
00858   * @param  SPIx SPI Instance
00859   * @param  RXCRCInitAll This parameter can be one of the following values:
00860   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
00861   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
00862   * @retval None
00863   */
00864 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
00865 {
00866   MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
00867 }
00868
00869 /**
00870   * @brief  Get Rx CRC Initialization Pattern
00871   * @rmtoll CR1          RCRCINI         LL_SPI_GetRxCRCInitPattern
00872   * @param  SPIx SPI Instance
00873   * @retval Returned value can be one of the following values:
00874   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
00875   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
00876   */
00877 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
00878 {
00879   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
00880 }
00881
00882 /**
00883   * @brief  Set internal SS input level ignoring what comes from PIN.
00884   * @note   This configuration has effect only with config LL_SPI_NSS_SOFT
00885   * @rmtoll CR1          SSI           LL_SPI_SetInternalSSLevel
00886   * @param  SPIx SPI Instance
00887   * @param  SSLevel This parameter can be one of the following values:
00888   *         @arg @ref LL_SPI_SS_LEVEL_HIGH
00889   *         @arg @ref LL_SPI_SS_LEVEL_LOW
00890   * @retval None
00891   */
00892 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
00893 {
00894   MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
00895 }
00896
00897 /**
00898   * @brief  Get internal SS input level
00899   * @rmtoll CR1          SSI           LL_SPI_GetInternalSSLevel
00900   * @param  SPIx SPI Instance
00901   * @retval Returned value can be one of the following values:
00902   *         @arg @ref LL_SPI_SS_LEVEL_HIGH
00903   *         @arg @ref LL_SPI_SS_LEVEL_LOW
00904   */
00905 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
00906 {
00907   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
00908 }
00909
00910 /**
00911   * @brief  Enable CRC computation on 33/17 bits
00912   * @rmtoll CR1          CRC33_17      LL_SPI_EnableFullSizeCRC
00913   * @param  SPIx SPI Instance
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
00917 {
00918   SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
00919 }
00920
00921 /**
00922   * @brief  Disable CRC computation on 33/17 bits
00923   * @rmtoll CR1          CRC33_17      LL_SPI_DisableFullSizeCRC
00924   * @param  SPIx SPI Instance
00925   * @retval None
00926   */
00927 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
00928 {
00929   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
00930 }
00931
00932 /**
00933   * @brief  Check if Enable CRC computation on 33/17 bits is enabled
00934   * @rmtoll CR1          CRC33_17      LL_SPI_IsEnabledFullSizeCRC
00935   * @param  SPIx SPI Instance
00936   * @retval State of bit (1 or 0)
00937   */
00938 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
00939 {
00940   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
00941 }
00942
00943 /**
00944   * @brief  Suspend an ongoing transfer for Master configuration
00945   * @rmtoll CR1          CSUSP         LL_SPI_SuspendMasterTransfer
00946   * @param  SPIx SPI Instance
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
00950 {
00951   SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
00952 }
00953
00954 /**
00955   * @brief  Start effective transfer on wire for Master configuration
00956   * @rmtoll CR1          CSTART        LL_SPI_StartMasterTransfer
00957   * @param  SPIx SPI Instance
00958   * @retval None
00959   */
00960 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
00961 {
00962   SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
00963 }
00964
00965 /**
00966   * @brief  Check if there is an unfinished master transfer
00967   * @rmtoll CR1          CSTART        LL_SPI_IsMasterTransferActive
00968   * @param  SPIx SPI Instance
00969   * @retval State of bit (1 or 0)
00970   */
00971 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
00972 {
00973   return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
00974 }
00975
00976 /**
00977   * @brief  Enable Master Rx auto suspend in case of overrun
00978   * @rmtoll CR1          MASRX         LL_SPI_EnableMasterRxAutoSuspend
00979   * @param  SPIx SPI Instance
00980   * @retval None
00981   */
00982 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
00983 {
00984   SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
00985 }
00986
00987 /**
00988   * @brief  Disable Master Rx auto suspend in case of overrun
00989   * @rmtoll CR1          MASRX         LL_SPI_DisableMasterRxAutoSuspend
00990   * @param  SPIx SPI Instance
00991   * @retval None
00992   */
00993 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
00994 {
00995   CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
00996 }
00997
00998 /**
00999   * @brief  Check if Master Rx auto suspend is activated
01000   * @rmtoll CR1          MASRX         LL_SPI_IsEnabledMasterRxAutoSuspend
01001   * @param  SPIx SPI Instance
01002   * @retval State of bit (1 or 0)
01003   */
01004 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
01005 {
01006   return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
01007 }
01008
01009 /**
01010   * @brief  Set Underrun behavior
01011   * @note   This configuration can not be changed when SPI is enabled.
01012   * @rmtoll CFG1         UDRCFG        LL_SPI_SetUDRConfiguration
01013   * @param  SPIx SPI Instance
01014   * @param  UDRConfig This parameter can be one of the following values:
01015   *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
01016   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
01017   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
01021 {
01022   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
01023 }
01024
01025 /**
01026   * @brief  Get Underrun behavior
01027   * @rmtoll CFG1         UDRCFG        LL_SPI_GetUDRConfiguration
01028   * @param  SPIx SPI Instance
01029   * @retval Returned value can be one of the following values:
01030   *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
01031   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
01032   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
01033   */
01034 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
01035 {
01036   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
01037 }
01038
01039 /**
01040   * @brief  Set Underrun Detection method
01041   * @note   This configuration can not be changed when SPI is enabled.
01042   * @rmtoll CFG1         UDRDET        LL_SPI_SetUDRDetection
01043   * @param  SPIx SPI Instance
01044   * @param  UDRDetection This parameter can be one of the following values:
01045   *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
01046   *         @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
01047   *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
01051 {
01052   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
01053 }
01054
01055 /**
01056   * @brief  Get Underrun Detection method
01057   * @rmtoll CFG1         UDRDET        LL_SPI_GetUDRDetection
01058   * @param  SPIx SPI Instance
01059   * @retval Returned value can be one of the following values:
01060   *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
01061   *         @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
01062   *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
01063   */
01064 __STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
01065 {
01066   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
01067 }
01068
01069 /**
01070   * @brief  Set Serial protocol used
01071   * @note   This configuration can not be changed when SPI is enabled.
01072   * @rmtoll CFG2         SP            LL_SPI_SetStandard
01073   * @param  SPIx SPI Instance
01074   * @param  Standard This parameter can be one of the following values:
01075   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
01076   *         @arg @ref LL_SPI_PROTOCOL_TI
01077   * @retval None
01078   */
01079 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
01080 {
01081   MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
01082 }
01083
01084 /**
01085   * @brief  Get Serial protocol used
01086   * @rmtoll CFG2         SP            LL_SPI_GetStandard
01087   * @param  SPIx SPI Instance
01088   * @retval Returned value can be one of the following values:
01089   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
01090   *         @arg @ref LL_SPI_PROTOCOL_TI
01091   */
01092 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
01093 {
01094   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
01095 }
01096
01097 /**
01098   * @brief  Set Clock phase
01099   * @note   This configuration can not be changed when SPI is enabled.
01100   *         This bit is not used in SPI TI mode.
01101   * @rmtoll CFG2         CPHA          LL_SPI_SetClockPhase
01102   * @param  SPIx SPI Instance
01103   * @param  ClockPhase This parameter can be one of the following values:
01104   *         @arg @ref LL_SPI_PHASE_1EDGE
01105   *         @arg @ref LL_SPI_PHASE_2EDGE
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
01109 {
01110   MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
01111 }
01112
01113 /**
01114   * @brief  Get Clock phase
01115   * @rmtoll CFG2         CPHA          LL_SPI_GetClockPhase
01116   * @param  SPIx SPI Instance
01117   * @retval Returned value can be one of the following values:
01118   *         @arg @ref LL_SPI_PHASE_1EDGE
01119   *         @arg @ref LL_SPI_PHASE_2EDGE
01120   */
01121 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
01122 {
01123   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
01124 }
01125
01126 /**
01127   * @brief  Set Clock polarity
01128   * @note   This configuration can not be changed when SPI is enabled.
01129   *         This bit is not used in SPI TI mode.
01130   * @rmtoll CFG2         CPOL          LL_SPI_SetClockPolarity
01131   * @param  SPIx SPI Instance
01132   * @param  ClockPolarity This parameter can be one of the following values:
01133   *         @arg @ref LL_SPI_POLARITY_LOW
01134   *         @arg @ref LL_SPI_POLARITY_HIGH
01135   * @retval None
01136   */
01137 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
01138 {
01139   MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
01140 }
01141
01142 /**
01143   * @brief  Get Clock polarity
01144   * @rmtoll CFG2         CPOL          LL_SPI_GetClockPolarity
01145   * @param  SPIx SPI Instance
01146   * @retval Returned value can be one of the following values:
01147   *         @arg @ref LL_SPI_POLARITY_LOW
01148   *         @arg @ref LL_SPI_POLARITY_HIGH
01149   */
01150 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
01151 {
01152   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
01153 }
01154
01155 /**
01156   * @brief  Set NSS polarity
01157   * @note   This configuration can not be changed when SPI is enabled.
01158   *         This bit is not used in SPI TI mode.
01159   * @rmtoll CFG2         SSIOP          LL_SPI_SetNSSPolarity
01160   * @param  SPIx SPI Instance
01161   * @param  NSSPolarity This parameter can be one of the following values:
01162   *         @arg @ref LL_SPI_NSS_POLARITY_LOW
01163   *         @arg @ref LL_SPI_NSS_POLARITY_HIGH
01164   * @retval None
01165   */
01166 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
01167 {
01168   MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
01169 }
01170
01171 /**
01172   * @brief  Get NSS polarity
01173   * @rmtoll CFG2         SSIOP          LL_SPI_GetNSSPolarity
01174   * @param  SPIx SPI Instance
01175   * @retval Returned value can be one of the following values:
01176   *         @arg @ref LL_SPI_NSS_POLARITY_LOW
01177   *         @arg @ref LL_SPI_NSS_POLARITY_HIGH
01178   */
01179 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
01180 {
01181   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
01182 }
01183
01184 /**
01185   * @brief  Set Baudrate Prescaler
01186   * @note   This configuration can not be changed when SPI is enabled.
01187   *         SPI BaudRate = fPCLK/Pescaler.
01188   * @rmtoll CFG1         MBR           LL_SPI_SetBaudRatePrescaler
01189   * @param  SPIx SPI Instance
01190   * @param  Baudrate This parameter can be one of the following values:
01191   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
01192   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
01193   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
01194   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
01195   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
01196   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
01197   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
01198   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
01199   * @retval None
01200   */
01201 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
01202 {
01203   MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
01204 }
01205
01206 /**
01207   * @brief  Get Baudrate Prescaler
01208   * @rmtoll CFG1         MBR           LL_SPI_GetBaudRatePrescaler
01209   * @param  SPIx SPI Instance
01210   * @retval Returned value can be one of the following values:
01211   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
01212   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
01213   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
01214   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
01215   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
01216   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
01217   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
01218   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
01219   */
01220 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
01221 {
01222   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
01223 }
01224
01225 /**
01226   * @brief  Set Transfer Bit Order
01227   * @note   This configuration can not be changed when SPI is enabled.
01228   *         This bit is not used in SPI TI mode.
01229   * @rmtoll CFG2         LSBFRST       LL_SPI_SetTransferBitOrder
01230   * @param  SPIx SPI Instance
01231   * @param  BitOrder This parameter can be one of the following values:
01232   *         @arg @ref LL_SPI_LSB_FIRST
01233   *         @arg @ref LL_SPI_MSB_FIRST
01234   * @retval None
01235   */
01236 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
01237 {
01238   MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
01239 }
01240
01241 /**
01242   * @brief  Get Transfer Bit Order
01243   * @rmtoll CFG2         LSBFRST       LL_SPI_GetTransferBitOrder
01244   * @param  SPIx SPI Instance
01245   * @retval Returned value can be one of the following values:
01246   *         @arg @ref LL_SPI_LSB_FIRST
01247   *         @arg @ref LL_SPI_MSB_FIRST
01248   */
01249 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
01250 {
01251   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
01252 }
01253
01254 /**
01255   * @brief  Set Transfer Mode
01256   * @note   This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
01257   * @rmtoll CR1          HDDIR         LL_SPI_SetTransferDirection\n
01258   *         CFG2         COMM          LL_SPI_SetTransferDirection
01259   * @param  SPIx SPI Instance
01260   * @param  TransferDirection This parameter can be one of the following values:
01261   *         @arg @ref LL_SPI_FULL_DUPLEX
01262   *         @arg @ref LL_SPI_SIMPLEX_TX
01263   *         @arg @ref LL_SPI_SIMPLEX_RX
01264   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
01265   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
01266   * @retval None
01267   */
01268 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
01269 {
01270   MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR,  TransferDirection & SPI_CR1_HDDIR);
01271   MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
01272 }
01273
01274 /**
01275   * @brief  Get Transfer Mode
01276   * @rmtoll CR1          HDDIR         LL_SPI_GetTransferDirection\n
01277   *         CFG2         COMM          LL_SPI_GetTransferDirection
01278   * @param  SPIx SPI Instance
01279   * @retval Returned value can be one of the following values:
01280   *         @arg @ref LL_SPI_FULL_DUPLEX
01281   *         @arg @ref LL_SPI_SIMPLEX_TX
01282   *         @arg @ref LL_SPI_SIMPLEX_RX
01283   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
01284   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
01285   */
01286 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
01287 {
01288   register uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
01289   register uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
01290   return (Hddir | Comm);
01291 }
01292
01293 /**
01294   * @brief  Set direction for Half-Duplex Mode
01295   * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
01296   * @rmtoll CR1          HDDIR         LL_SPI_SetHalfDuplexDirection
01297   * @param  SPIx SPI Instance
01298   * @param  HalfDuplexDirection This parameter can be one of the following values:
01299   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
01300   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
01301   * @retval None
01302   */
01303 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
01304 {
01305   MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
01306 }
01307
01308 /**
01309   * @brief  Get direction for Half-Duplex Mode
01310   * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
01311   * @rmtoll CR1          HDDIR         LL_SPI_GetHalfDuplexDirection
01312   * @param  SPIx SPI Instance
01313   * @retval Returned value can be one of the following values:
01314   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
01315   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
01316   */
01317 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
01318 {
01319   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
01320 }
01321
01322 /**
01323   * @brief  Set Frame Data Size
01324   * @note   This configuration can not be changed when SPI is enabled.
01325   * @rmtoll CFG1         DSIZE         LL_SPI_SetDataWidth
01326   * @param  SPIx SPI Instance
01327   * @param  DataWidth This parameter can be one of the following values:
01328   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
01329   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
01330   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
01331   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
01332   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
01333   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
01334   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
01335   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
01336   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
01337   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
01338   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
01339   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
01340   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
01341   *         @arg @ref LL_SPI_DATAWIDTH_17BIT
01342   *         @arg @ref LL_SPI_DATAWIDTH_18BIT
01343   *         @arg @ref LL_SPI_DATAWIDTH_19BIT
01344   *         @arg @ref LL_SPI_DATAWIDTH_20BIT
01345   *         @arg @ref LL_SPI_DATAWIDTH_21BIT
01346   *         @arg @ref LL_SPI_DATAWIDTH_22BIT
01347   *         @arg @ref LL_SPI_DATAWIDTH_23BIT
01348   *         @arg @ref LL_SPI_DATAWIDTH_24BIT
01349   *         @arg @ref LL_SPI_DATAWIDTH_25BIT
01350   *         @arg @ref LL_SPI_DATAWIDTH_26BIT
01351   *         @arg @ref LL_SPI_DATAWIDTH_27BIT
01352   *         @arg @ref LL_SPI_DATAWIDTH_28BIT
01353   *         @arg @ref LL_SPI_DATAWIDTH_29BIT
01354   *         @arg @ref LL_SPI_DATAWIDTH_30BIT
01355   *         @arg @ref LL_SPI_DATAWIDTH_31BIT
01356   *         @arg @ref LL_SPI_DATAWIDTH_32BIT
01357   * @retval None
01358   */
01359 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
01360 {
01361   MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
01362 }
01363
01364 /**
01365   * @brief  Get Frame Data Size
01366   * @rmtoll CFG1         DSIZE         LL_SPI_GetDataWidth
01367   * @param  SPIx SPI Instance
01368   * @retval Returned value can be one of the following values:
01369   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
01370   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
01371   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
01372   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
01373   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
01374   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
01375   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
01376   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
01377   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
01378   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
01379   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
01380   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
01381   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
01382   *         @arg @ref LL_SPI_DATAWIDTH_17BIT
01383   *         @arg @ref LL_SPI_DATAWIDTH_18BIT
01384   *         @arg @ref LL_SPI_DATAWIDTH_19BIT
01385   *         @arg @ref LL_SPI_DATAWIDTH_20BIT
01386   *         @arg @ref LL_SPI_DATAWIDTH_21BIT
01387   *         @arg @ref LL_SPI_DATAWIDTH_22BIT
01388   *         @arg @ref LL_SPI_DATAWIDTH_23BIT
01389   *         @arg @ref LL_SPI_DATAWIDTH_24BIT
01390   *         @arg @ref LL_SPI_DATAWIDTH_25BIT
01391   *         @arg @ref LL_SPI_DATAWIDTH_26BIT
01392   *         @arg @ref LL_SPI_DATAWIDTH_27BIT
01393   *         @arg @ref LL_SPI_DATAWIDTH_28BIT
01394   *         @arg @ref LL_SPI_DATAWIDTH_29BIT
01395   *         @arg @ref LL_SPI_DATAWIDTH_30BIT
01396   *         @arg @ref LL_SPI_DATAWIDTH_31BIT
01397   *         @arg @ref LL_SPI_DATAWIDTH_32BIT
01398   */
01399 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
01400 {
01401   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
01402 }
01403
01404 /**
01405   * @brief  Set threshold of FIFO that triggers a transfer event
01406   * @note   This configuration can not be changed when SPI is enabled.
01407   * @rmtoll CFG1         FTHLV         LL_SPI_SetFIFOThreshold
01408   * @param  SPIx SPI Instance
01409   * @param  Threshold This parameter can be one of the following values:
01410   *         @arg @ref LL_SPI_FIFO_TH_01DATA
01411   *         @arg @ref LL_SPI_FIFO_TH_02DATA
01412   *         @arg @ref LL_SPI_FIFO_TH_03DATA
01413   *         @arg @ref LL_SPI_FIFO_TH_04DATA
01414   *         @arg @ref LL_SPI_FIFO_TH_05DATA
01415   *         @arg @ref LL_SPI_FIFO_TH_06DATA
01416   *         @arg @ref LL_SPI_FIFO_TH_07DATA
01417   *         @arg @ref LL_SPI_FIFO_TH_08DATA
01418   *         @arg @ref LL_SPI_FIFO_TH_09DATA
01419   *         @arg @ref LL_SPI_FIFO_TH_10DATA
01420   *         @arg @ref LL_SPI_FIFO_TH_11DATA
01421   *         @arg @ref LL_SPI_FIFO_TH_12DATA
01422   *         @arg @ref LL_SPI_FIFO_TH_13DATA
01423   *         @arg @ref LL_SPI_FIFO_TH_14DATA
01424   *         @arg @ref LL_SPI_FIFO_TH_15DATA
01425   *         @arg @ref LL_SPI_FIFO_TH_16DATA
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
01429 {
01430   MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
01431 }
01432
01433 /**
01434   * @brief  Get threshold of FIFO that triggers a transfer event
01435   * @rmtoll CFG1         FTHLV         LL_SPI_GetFIFOThreshold
01436   * @param  SPIx SPI Instance
01437   * @retval Returned value can be one of the following values:
01438   *         @arg @ref LL_SPI_FIFO_TH_01DATA
01439   *         @arg @ref LL_SPI_FIFO_TH_02DATA
01440   *         @arg @ref LL_SPI_FIFO_TH_03DATA
01441   *         @arg @ref LL_SPI_FIFO_TH_04DATA
01442   *         @arg @ref LL_SPI_FIFO_TH_05DATA
01443   *         @arg @ref LL_SPI_FIFO_TH_06DATA
01444   *         @arg @ref LL_SPI_FIFO_TH_07DATA
01445   *         @arg @ref LL_SPI_FIFO_TH_08DATA
01446   *         @arg @ref LL_SPI_FIFO_TH_09DATA
01447   *         @arg @ref LL_SPI_FIFO_TH_10DATA
01448   *         @arg @ref LL_SPI_FIFO_TH_11DATA
01449   *         @arg @ref LL_SPI_FIFO_TH_12DATA
01450   *         @arg @ref LL_SPI_FIFO_TH_13DATA
01451   *         @arg @ref LL_SPI_FIFO_TH_14DATA
01452   *         @arg @ref LL_SPI_FIFO_TH_15DATA
01453   *         @arg @ref LL_SPI_FIFO_TH_16DATA
01454   */
01455 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
01456 {
01457   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
01458 }
01459
01460 /**
01461   * @brief  Enable CRC
01462   * @note   This configuration can not be changed when SPI is enabled.
01463   * @rmtoll CFG1         CRCEN         LL_SPI_EnableCRC
01464   * @param  SPIx SPI Instance
01465   * @retval None
01466   */
01467 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
01468 {
01469   SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
01470 }
01471
01472 /**
01473   * @brief  Disable CRC
01474   * @rmtoll CFG1         CRCEN         LL_SPI_DisableCRC
01475   * @param  SPIx SPI Instance
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
01479 {
01480   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
01481 }
01482
01483 /**
01484   * @brief  Check if CRC is enabled
01485   * @rmtoll CFG1         CRCEN         LL_SPI_IsEnabledCRC
01486   * @param  SPIx SPI Instance
01487   * @retval State of bit (1 or 0).
01488   */
01489 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
01490 {
01491   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
01492 }
01493
01494 /**
01495   * @brief  Set CRC Length
01496   * @note   This configuration can not be changed when SPI is enabled.
01497   * @rmtoll CFG1         CRCSIZE       LL_SPI_SetCRCWidth
01498   * @param  SPIx SPI Instance
01499   * @param  CRCLength This parameter can be one of the following values:
01500   *         @arg @ref LL_SPI_CRC_4BIT
01501   *         @arg @ref LL_SPI_CRC_5BIT
01502   *         @arg @ref LL_SPI_CRC_6BIT
01503   *         @arg @ref LL_SPI_CRC_7BIT
01504   *         @arg @ref LL_SPI_CRC_8BIT
01505   *         @arg @ref LL_SPI_CRC_9BIT
01506   *         @arg @ref LL_SPI_CRC_10BIT
01507   *         @arg @ref LL_SPI_CRC_11BIT
01508   *         @arg @ref LL_SPI_CRC_12BIT
01509   *         @arg @ref LL_SPI_CRC_13BIT
01510   *         @arg @ref LL_SPI_CRC_14BIT
01511   *         @arg @ref LL_SPI_CRC_15BIT
01512   *         @arg @ref LL_SPI_CRC_16BIT
01513   *         @arg @ref LL_SPI_CRC_17BIT
01514   *         @arg @ref LL_SPI_CRC_18BIT
01515   *         @arg @ref LL_SPI_CRC_19BIT
01516   *         @arg @ref LL_SPI_CRC_20BIT
01517   *         @arg @ref LL_SPI_CRC_21BIT
01518   *         @arg @ref LL_SPI_CRC_22BIT
01519   *         @arg @ref LL_SPI_CRC_23BIT
01520   *         @arg @ref LL_SPI_CRC_24BIT
01521   *         @arg @ref LL_SPI_CRC_25BIT
01522   *         @arg @ref LL_SPI_CRC_26BIT
01523   *         @arg @ref LL_SPI_CRC_27BIT
01524   *         @arg @ref LL_SPI_CRC_28BIT
01525   *         @arg @ref LL_SPI_CRC_29BIT
01526   *         @arg @ref LL_SPI_CRC_30BIT
01527   *         @arg @ref LL_SPI_CRC_31BIT
01528   *         @arg @ref LL_SPI_CRC_32BIT
01529   * @retval None
01530   */
01531 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
01532 {
01533   MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
01534 }
01535
01536 /**
01537   * @brief  Get CRC Length
01538   * @rmtoll CFG1          CRCSIZE       LL_SPI_GetCRCWidth
01539   * @param  SPIx SPI Instance
01540   * @retval Returned value can be one of the following values:
01541   *         @arg @ref LL_SPI_CRC_4BIT
01542   *         @arg @ref LL_SPI_CRC_5BIT
01543   *         @arg @ref LL_SPI_CRC_6BIT
01544   *         @arg @ref LL_SPI_CRC_7BIT
01545   *         @arg @ref LL_SPI_CRC_8BIT
01546   *         @arg @ref LL_SPI_CRC_9BIT
01547   *         @arg @ref LL_SPI_CRC_10BIT
01548   *         @arg @ref LL_SPI_CRC_11BIT
01549   *         @arg @ref LL_SPI_CRC_12BIT
01550   *         @arg @ref LL_SPI_CRC_13BIT
01551   *         @arg @ref LL_SPI_CRC_14BIT
01552   *         @arg @ref LL_SPI_CRC_15BIT
01553   *         @arg @ref LL_SPI_CRC_16BIT
01554   *         @arg @ref LL_SPI_CRC_17BIT
01555   *         @arg @ref LL_SPI_CRC_18BIT
01556   *         @arg @ref LL_SPI_CRC_19BIT
01557   *         @arg @ref LL_SPI_CRC_20BIT
01558   *         @arg @ref LL_SPI_CRC_21BIT
01559   *         @arg @ref LL_SPI_CRC_22BIT
01560   *         @arg @ref LL_SPI_CRC_23BIT
01561   *         @arg @ref LL_SPI_CRC_24BIT
01562   *         @arg @ref LL_SPI_CRC_25BIT
01563   *         @arg @ref LL_SPI_CRC_26BIT
01564   *         @arg @ref LL_SPI_CRC_27BIT
01565   *         @arg @ref LL_SPI_CRC_28BIT
01566   *         @arg @ref LL_SPI_CRC_29BIT
01567   *         @arg @ref LL_SPI_CRC_30BIT
01568   *         @arg @ref LL_SPI_CRC_31BIT
01569   *         @arg @ref LL_SPI_CRC_32BIT
01570   */
01571 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
01572 {
01573   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
01574 }
01575
01576 /**
01577   * @brief  Set NSS Mode
01578   * @note   This configuration can not be changed when SPI is enabled.
01579   *         This bit is not used in SPI TI mode.
01580   * @rmtoll CFG2         SSM           LL_SPI_SetNSSMode\n
01581   *         CFG2         SSOE          LL_SPI_SetNSSMode
01582   * @param  SPIx SPI Instance
01583   * @param  NSS This parameter can be one of the following values:
01584   *         @arg @ref LL_SPI_NSS_SOFT
01585   *         @arg @ref LL_SPI_NSS_HARD_INPUT
01586   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
01587   * @retval None
01588   */
01589 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
01590 {
01591   MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
01592 }
01593
01594 /**
01595   * @brief  Set NSS Mode
01596   * @rmtoll CFG2         SSM           LL_SPI_GetNSSMode\n
01597   *         CFG2         SSOE          LL_SPI_GetNSSMode
01598   * @param  SPIx SPI Instance
01599   * @retval Returned value can be one of the following values:
01600   *         @arg @ref LL_SPI_NSS_SOFT
01601   *         @arg @ref LL_SPI_NSS_HARD_INPUT
01602   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
01603   */
01604 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
01605 {
01606   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
01607 }
01608
01609 /**
01610   * @brief  Enable NSS pulse mgt
01611   * @note   This configuration can not be changed when SPI is enabled.
01612   *         This bit is not used in SPI TI mode.
01613   * @rmtoll CFG2         SSOM          LL_SPI_EnableNSSPulseMgt
01614   * @param  SPIx SPI Instance
01615   * @retval None
01616   */
01617 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
01618 {
01619   SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
01620 }
01621
01622 /**
01623   * @brief  Disable NSS pulse mgt
01624   * @note   This configuration can not be changed when SPI is enabled.
01625   *         This bit is not used in SPI TI mode.
01626   * @rmtoll CFG2         SSOM          LL_SPI_DisableNSSPulseMgt
01627   * @param  SPIx SPI Instance
01628   * @retval None
01629   */
01630 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
01631 {
01632   CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
01633 }
01634
01635 /**
01636   * @brief  Check if NSS pulse is enabled
01637   * @rmtoll CFG2         SSOM          LL_SPI_IsEnabledNSSPulse
01638   * @param  SPIx SPI Instance
01639   * @retval State of bit (1 or 0)
01640   */
01641 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
01642 {
01643   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
01644 }
01645
01646 /**
01647   * @}
01648   */
01649
01650 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
01651   * @{
01652   */
01653
01654 /**
01655   * @brief  Check if there is enough data in FIFO to read a full packet
01656   * @rmtoll SR           RXP           LL_SPI_IsActiveFlag_RXP
01657   * @param  SPIx SPI Instance
01658   * @retval State of bit (1 or 0)
01659   */
01660 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
01661 {
01662   return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
01663 }
01664
01665 /**
01666   * @brief  Check if there is enough space in FIFO to hold a full packet
01667   * @rmtoll SR           TXP           LL_SPI_IsActiveFlag_TXP
01668   * @param  SPIx SPI Instance
01669   * @retval State of bit (1 or 0)
01670   */
01671 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
01672 {
01673   return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
01674 }
01675
01676 /**
01677   * @brief  Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
01678   * @rmtoll SR           DXP           LL_SPI_IsActiveFlag_DXP
01679   * @param  SPIx SPI Instance
01680   * @retval State of bit (1 or 0)
01681   */
01682 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
01683 {
01684   return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
01685 }
01686
01687 /**
01688   * @brief  Check that end of transfer event occured
01689   * @rmtoll SR           EOT           LL_SPI_IsActiveFlag_EOT
01690   * @param  SPIx SPI Instance
01691   * @retval State of bit (1 or 0).
01692   */
01693 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
01694 {
01695   return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
01696 }
01697
01698 /**
01699   * @brief  Check that all required data has been filled in the fifo according to transfer size
01700   * @rmtoll SR           TXTF          LL_SPI_IsActiveFlag_TXTF
01701   * @param  SPIx SPI Instance
01702   * @retval State of bit (1 or 0).
01703   */
01704 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
01705 {
01706   return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
01707 }
01708
01709 /**
01710   * @brief  Get Underrun error flag
01711   * @rmtoll SR           UDR           LL_SPI_IsActiveFlag_UDR
01712   * @param  SPIx SPI Instance
01713   * @retval State of bit (1 or 0).
01714   */
01715 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
01716 {
01717   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
01718 }
01719
01720 /**
01721   * @brief  Get CRC error flag
01722   * @rmtoll SR           CRCE        LL_SPI_IsActiveFlag_CRCERR
01723   * @param  SPIx SPI Instance
01724   * @retval State of bit (1 or 0).
01725   */
01726 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
01727 {
01728   return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
01729 }
01730
01731 /**
01732   * @brief  Get  Mode fault error flag
01733   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
01734   * @param  SPIx SPI Instance
01735   * @retval State of bit (1 or 0).
01736   */
01737 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
01738 {
01739   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
01740 }
01741
01742 /**
01743   * @brief  Get Overrun error flag
01744   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
01745   * @param  SPIx SPI Instance
01746   * @retval State of bit (1 or 0).
01747   */
01748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
01749 {
01750   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
01751 }
01752
01753 /**
01754   * @brief  Get TI Frame format error flag
01755   * @rmtoll SR           TIFRE         LL_SPI_IsActiveFlag_FRE
01756   * @param  SPIx SPI Instance
01757   * @retval State of bit (1 or 0).
01758   */
01759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
01760 {
01761   return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
01762 }
01763
01764 /**
01765   * @brief  Check if the additional number of data has been reloaded
01766   * @rmtoll SR           TSERF         LL_SPI_IsActiveFlag_TSER
01767   * @param  SPIx SPI Instance
01768   * @retval State of bit (1 or 0).
01769   */
01770 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
01771 {
01772   return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
01773 }
01774
01775 /**
01776   * @brief  Check if a suspend operation is done
01777   * @rmtoll SR           SUSP          LL_SPI_IsActiveFlag_SUSP
01778   * @param  SPIx SPI Instance
01779   * @retval State of bit (1 or 0)
01780   */
01781 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
01782 {
01783   return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
01784 }
01785
01786 /**
01787   * @brief  Check if last TxFIFO or CRC frame transmission is completed
01788   * @rmtoll SR           TXC           LL_SPI_IsActiveFlag_TXC
01789   * @param  SPIx SPI Instance
01790   * @retval State of bit (1 or 0).
01791   */
01792 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
01793 {
01794   return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
01795 }
01796
01797 /**
01798   * @brief  Check if at least one 32-bit data is available in RxFIFO
01799   * @rmtoll SR           RXWNE         LL_SPI_IsActiveFlag_RXWNE
01800   * @param  SPIx SPI Instance
01801   * @retval State of bit (1 or 0)
01802   */
01803 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
01804 {
01805   return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
01806 }
01807
01808 /**
01809   * @brief  Get number of data framed remaining in current TSIZE
01810   * @rmtoll SR           CTSIZE           LL_SPI_GetRemainingDataFrames
01811   * @param  SPIx SPI Instance
01812   * @retval 0..0xFFFF
01813   */
01814 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
01815 {
01816   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
01817 }
01818
01819 /**
01820   * @brief  Get RxFIFO packing Level
01821   * @rmtoll SR           RXPLVL        LL_SPI_GetRxFIFOPackingLevel
01822   * @param  SPIx SPI Instance
01823   * @retval Returned value can be one of the following values:
01824   *         @arg @ref LL_SPI_RX_FIFO_0PACKET
01825   *         @arg @ref LL_SPI_RX_FIFO_1PACKET
01826   *         @arg @ref LL_SPI_RX_FIFO_2PACKET
01827   *         @arg @ref LL_SPI_RX_FIFO_3PACKET
01828   */
01829 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
01830 {
01831   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
01832 }
01833
01834 /**
01835   * @brief  Clear End Of Transfer flag
01836   * @rmtoll IFCR         EOTC          LL_SPI_ClearFlag_EOT
01837   * @param  SPIx SPI Instance
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
01841 {
01842   SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
01843 }
01844
01845 /**
01846   * @brief  Clear TXTF flag
01847   * @rmtoll IFCR         TXTFC         LL_SPI_ClearFlag_TXTF
01848   * @param  SPIx SPI Instance
01849   * @retval None
01850   */
01851 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
01852 {
01853   SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
01854 }
01855
01856 /**
01857   * @brief  Clear Underrun error flag
01858   * @rmtoll IFCR         UDRC          LL_SPI_ClearFlag_UDR
01859   * @param  SPIx SPI Instance
01860   * @retval None
01861   */
01862 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
01863 {
01864   SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
01865 }
01866
01867 /**
01868   * @brief  Clear Overrun error flag
01869   * @rmtoll IFCR         OVRC          LL_SPI_ClearFlag_OVR
01870   * @param  SPIx SPI Instance
01871   * @retval None
01872   */
01873 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01874 {
01875   SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
01876 }
01877
01878 /**
01879   * @brief  Clear CRC error flag
01880   * @rmtoll IFCR         CRCEC        LL_SPI_ClearFlag_CRCERR
01881   * @param  SPIx SPI Instance
01882   * @retval None
01883   */
01884 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01885 {
01886   SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
01887 }
01888
01889 /**
01890   * @brief  Clear  Mode fault error flag
01891   * @rmtoll IFCR         MODFC         LL_SPI_ClearFlag_MODF
01892   * @param  SPIx SPI Instance
01893   * @retval None
01894   */
01895 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01896 {
01897   SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
01898 }
01899
01900 /**
01901   * @brief  Clear Frame format error flag
01902   * @rmtoll IFCR         TIFREC        LL_SPI_ClearFlag_FRE
01903   * @param  SPIx SPI Instance
01904   * @retval None
01905   */
01906 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01907 {
01908   SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
01909 }
01910
01911 /**
01912   * @brief  Clear TSER flag
01913   * @rmtoll IFCR         TSERFC        LL_SPI_ClearFlag_TSER
01914   * @param  SPIx SPI Instance
01915   * @retval None
01916   */
01917 __STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
01918 {
01919   SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
01920 }
01921
01922 /**
01923   * @brief  Clear SUSP flag
01924   * @rmtoll IFCR         SUSPC         LL_SPI_ClearFlag_SUSP
01925   * @param  SPIx SPI Instance
01926   * @retval None
01927   */
01928 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
01929 {
01930   SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
01931 }
01932
01933 /**
01934   * @}
01935   */
01936
01937 /** @defgroup SPI_LL_EF_IT_Management IT_Management
01938   * @{
01939   */
01940
01941 /**
01942   * @brief  Enable Rx Packet available IT
01943   * @rmtoll IER          RXPIE         LL_SPI_EnableIT_RXP
01944   * @param  SPIx SPI Instance
01945   * @retval None
01946   */
01947 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
01948 {
01949   SET_BIT(SPIx->IER, SPI_IER_RXPIE);
01950 }
01951
01952 /**
01953   * @brief  Enable Tx Packet space available IT
01954   * @rmtoll IER          TXPIE         LL_SPI_EnableIT_TXP
01955   * @param  SPIx SPI Instance
01956   * @retval None
01957   */
01958 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
01959 {
01960   SET_BIT(SPIx->IER, SPI_IER_TXPIE);
01961 }
01962
01963 /**
01964   * @brief  Enable Duplex Packet available IT
01965   * @rmtoll IER          DXPIE         LL_SPI_EnableIT_DXP
01966   * @param  SPIx SPI Instance
01967   * @retval None
01968   */
01969 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
01970 {
01971   SET_BIT(SPIx->IER, SPI_IER_DXPIE);
01972 }
01973
01974 /**
01975   * @brief  Enable End Of Transfer IT
01976   * @rmtoll IER          EOTIE         LL_SPI_EnableIT_EOT
01977   * @param  SPIx SPI Instance
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
01981 {
01982   SET_BIT(SPIx->IER, SPI_IER_EOTIE);
01983 }
01984
01985 /**
01986   * @brief  Enable TXTF IT
01987   * @rmtoll IER          TXTFIE        LL_SPI_EnableIT_TXTF
01988   * @param  SPIx SPI Instance
01989   * @retval None
01990   */
01991 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
01992 {
01993   SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
01994 }
01995
01996 /**
01997   * @brief  Enable Underrun IT
01998   * @rmtoll IER          UDRIE         LL_SPI_EnableIT_UDR
01999   * @param  SPIx SPI Instance
02000   * @retval None
02001   */
02002 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
02003 {
02004   SET_BIT(SPIx->IER, SPI_IER_UDRIE);
02005 }
02006
02007 /**
02008   * @brief  Enable Overrun IT
02009   * @rmtoll IER          OVRIE         LL_SPI_EnableIT_OVR
02010   * @param  SPIx SPI Instance
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
02014 {
02015   SET_BIT(SPIx->IER, SPI_IER_OVRIE);
02016 }
02017
02018 /**
02019   * @brief  Enable CRC Error IT
02020   * @rmtoll IER          CRCEIE        LL_SPI_EnableIT_CRCERR
02021   * @param  SPIx SPI Instance
02022   * @retval None
02023   */
02024 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
02025 {
02026   SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
02027 }
02028
02029 /**
02030   * @brief  Enable TI Frame Format Error IT
02031   * @rmtoll IER          TIFREIE       LL_SPI_EnableIT_FRE
02032   * @param  SPIx SPI Instance
02033   * @retval None
02034   */
02035 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
02036 {
02037   SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
02038 }
02039
02040 /**
02041   * @brief  Enable MODF IT
02042   * @rmtoll IER          MODFIE        LL_SPI_EnableIT_MODF
02043   * @param  SPIx SPI Instance
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
02047 {
02048   SET_BIT(SPIx->IER, SPI_IER_MODFIE);
02049 }
02050
02051 /**
02052   * @brief  Enable TSER reload IT
02053   * @rmtoll IER          TSERFIE       LL_SPI_EnableIT_TSER
02054   * @param  SPIx SPI Instance
02055   * @retval None
02056   */
02057 __STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
02058 {
02059   SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
02060 }
02061
02062 /**
02063   * @brief  Disable Rx Packet available IT
02064   * @rmtoll IER          RXPIE         LL_SPI_DisableIT_RXP
02065   * @param  SPIx SPI Instance
02066   * @retval None
02067   */
02068 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
02069 {
02070   CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
02071 }
02072
02073 /**
02074   * @brief  Disable Tx Packet space available IT
02075   * @rmtoll IER          TXPIE         LL_SPI_DisableIT_TXP
02076   * @param  SPIx SPI Instance
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
02080 {
02081   CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
02082 }
02083
02084 /**
02085   * @brief  Disable Duplex Packet available IT
02086   * @rmtoll IER          DXPIE         LL_SPI_DisableIT_DXP
02087   * @param  SPIx SPI Instance
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
02091 {
02092   CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
02093 }
02094
02095 /**
02096   * @brief  Disable End Of Transfer IT
02097   * @rmtoll IER          EOTIE         LL_SPI_DisableIT_EOT
02098   * @param  SPIx SPI Instance
02099   * @retval None
02100   */
02101 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
02102 {
02103   CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
02104 }
02105
02106 /**
02107   * @brief  Disable TXTF IT
02108   * @rmtoll IER          TXTFIE        LL_SPI_DisableIT_TXTF
02109   * @param  SPIx SPI Instance
02110   * @retval None
02111   */
02112 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
02113 {
02114   CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
02115 }
02116
02117 /**
02118   * @brief  Disable Underrun IT
02119   * @rmtoll IER          UDRIE         LL_SPI_DisableIT_UDR
02120   * @param  SPIx SPI Instance
02121   * @retval None
02122   */
02123 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
02124 {
02125   CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
02126 }
02127
02128 /**
02129   * @brief  Disable Overrun IT
02130   * @rmtoll IER          OVRIE         LL_SPI_DisableIT_OVR
02131   * @param  SPIx SPI Instance
02132   * @retval None
02133   */
02134 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
02135 {
02136   CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
02137 }
02138
02139 /**
02140   * @brief  Disable CRC Error IT
02141   * @rmtoll IER          CRCEIE        LL_SPI_DisableIT_CRCERR
02142   * @param  SPIx SPI Instance
02143   * @retval None
02144   */
02145 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
02146 {
02147   CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
02148 }
02149
02150 /**
02151   * @brief  Disable TI Frame Format Error IT
02152   * @rmtoll IER          TIFREIE       LL_SPI_DisableIT_FRE
02153   * @param  SPIx SPI Instance
02154   * @retval None
02155   */
02156 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
02157 {
02158   CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
02159 }
02160
02161 /**
02162   * @brief  Disable MODF IT
02163   * @rmtoll IER          MODFIE        LL_SPI_DisableIT_MODF
02164   * @param  SPIx SPI Instance
02165   * @retval None
02166   */
02167 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
02168 {
02169   CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
02170 }
02171
02172 /**
02173   * @brief  Disable TSER reload IT
02174   * @rmtoll IER          TSERFIE       LL_SPI_DisableIT_TSER
02175   * @param  SPIx SPI Instance
02176   * @retval None
02177   */
02178 __STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
02179 {
02180   CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
02181 }
02182
02183 /**
02184   * @brief  Check if Rx Packet available IT is enabled
02185   * @rmtoll IER          RXPIE         LL_SPI_IsEnabledIT_RXP
02186   * @param  SPIx SPI Instance
02187   * @retval State of bit (1 or 0)
02188   */
02189 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
02190 {
02191   return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
02192 }
02193
02194 /**
02195   * @brief  Check if Tx Packet space available IT is enabled
02196   * @rmtoll IER          TXPIE         LL_SPI_IsEnabledIT_TXP
02197   * @param  SPIx SPI Instance
02198   * @retval State of bit (1 or 0)
02199   */
02200 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
02201 {
02202   return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
02203 }
02204
02205 /**
02206   * @brief  Check if Duplex Packet available IT is enabled
02207   * @rmtoll IER          DXPIE         LL_SPI_IsEnabledIT_DXP
02208   * @param  SPIx SPI Instance
02209   * @retval State of bit (1 or 0)
02210   */
02211 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
02212 {
02213   return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
02214 }
02215
02216 /**
02217   * @brief  Check if End Of Transfer IT is enabled
02218   * @rmtoll IER          EOTIE         LL_SPI_IsEnabledIT_EOT
02219   * @param  SPIx SPI Instance
02220   * @retval State of bit (1 or 0)
02221   */
02222 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
02223 {
02224   return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
02225 }
02226
02227 /**
02228   * @brief  Check if TXTF IT is enabled
02229   * @rmtoll IER          TXTFIE        LL_SPI_IsEnabledIT_TXTF
02230   * @param  SPIx SPI Instance
02231   * @retval State of bit (1 or 0)
02232   */
02233 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
02234 {
02235   return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
02236 }
02237
02238 /**
02239   * @brief  Check if Underrun IT is enabled
02240   * @rmtoll IER          UDRIE         LL_SPI_IsEnabledIT_UDR
02241   * @param  SPIx SPI Instance
02242   * @retval State of bit (1 or 0)
02243   */
02244 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
02245 {
02246   return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
02247 }
02248
02249 /**
02250   * @brief  Check if Overrun IT is enabled
02251   * @rmtoll IER          OVRIE         LL_SPI_IsEnabledIT_OVR
02252   * @param  SPIx SPI Instance
02253   * @retval State of bit (1 or 0)
02254   */
02255 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
02256 {
02257   return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
02258 }
02259
02260 /**
02261   * @brief  Check if CRC Error IT is enabled
02262   * @rmtoll IER          CRCEIE        LL_SPI_IsEnabledIT_CRCERR
02263   * @param  SPIx SPI Instance
02264   * @retval State of bit (1 or 0)
02265   */
02266 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
02267 {
02268   return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
02269 }
02270
02271 /**
02272   * @brief  Check if TI Frame Format Error IT is enabled
02273   * @rmtoll IER          TIFREIE       LL_SPI_IsEnabledIT_FRE
02274   * @param  SPIx SPI Instance
02275   * @retval State of bit (1 or 0)
02276   */
02277 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
02278 {
02279   return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
02280 }
02281
02282 /**
02283   * @brief  Check if MODF IT is enabled
02284   * @rmtoll IER          MODFIE        LL_SPI_IsEnabledIT_MODF
02285   * @param  SPIx SPI Instance
02286   * @retval State of bit (1 or 0)
02287   */
02288 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
02289 {
02290   return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
02291 }
02292
02293 /**
02294   * @brief  Check if TSER reload IT is enabled
02295   * @rmtoll IER          TSERFIE       LL_SPI_IsEnabledIT_TSER
02296   * @param  SPIx SPI Instance
02297   * @retval State of bit (1 or 0)
02298   */
02299 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
02300 {
02301   return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
02302 }
02303
02304 /**
02305   * @}
02306   */
02307
02308 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
02309   * @{
02310   */
02311
02312 /**
02313   * @brief  Enable DMA Rx
02314   * @rmtoll CFG1         RXDMAEN       LL_SPI_EnableDMAReq_RX
02315   * @param  SPIx SPI Instance
02316   * @retval None
02317   */
02318 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
02319 {
02320   SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
02321 }
02322
02323 /**
02324   * @brief  Disable DMA Rx
02325   * @rmtoll CFG1         RXDMAEN       LL_SPI_DisableDMAReq_RX
02326   * @param  SPIx SPI Instance
02327   * @retval None
02328   */
02329 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
02330 {
02331   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
02332 }
02333
02334 /**
02335   * @brief  Check if DMA Rx is enabled
02336   * @rmtoll CFG1         RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
02337   * @param  SPIx SPI Instance
02338   * @retval State of bit (1 or 0)
02339   */
02340 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
02341 {
02342   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
02343 }
02344
02345 /**
02346   * @brief  Enable DMA Tx
02347   * @rmtoll CFG1         TXDMAEN       LL_SPI_EnableDMAReq_TX
02348   * @param  SPIx SPI Instance
02349   * @retval None
02350   */
02351 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
02352 {
02353   SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
02354 }
02355
02356 /**
02357   * @brief  Disable DMA Tx
02358   * @rmtoll CFG1         TXDMAEN       LL_SPI_DisableDMAReq_TX
02359   * @param  SPIx SPI Instance
02360   * @retval None
02361   */
02362 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
02363 {
02364   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
02365 }
02366
02367 /**
02368   * @brief  Check if DMA Tx is enabled
02369   * @rmtoll CFG1         TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
02370   * @param  SPIx SPI Instance
02371   * @retval State of bit (1 or 0)
02372   */
02373 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
02374 {
02375   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
02376 }
02377
02378 /**
02379   * @}
02380   */
02381
02382 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
02383   * @{
02384   */
02385
02386 /**
02387   * @brief  Read Data Register
02388   * @rmtoll RXDR         .       LL_SPI_ReceiveData8
02389   * @param  SPIx SPI Instance
02390   * @retval 0..0xFF
02391   */
02392 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
02393 {
02394   return (*((__IO uint8_t *)&SPIx->RXDR));
02395 }
02396
02397 /**
02398   * @brief  Read Data Register
02399   * @rmtoll RXDR         .       LL_SPI_ReceiveData16
02400   * @param  SPIx SPI Instance
02401   * @retval 0..0xFFFF
02402   */
02403 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
02404 {
02405   return (uint16_t)(READ_REG(SPIx->RXDR));
02406 }
02407
02408 /**
02409   * @brief  Read Data Register
02410   * @rmtoll RXDR         .       LL_SPI_ReceiveData32
02411   * @param  SPIx SPI Instance
02412   * @retval  0..0xFFFFFFFF
02413   */
02414 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
02415 {
02416   return (*((__IO uint32_t *)&SPIx->RXDR));
02417 }
02418
02419 /**
02420   * @brief  Write Data Register
02421   * @rmtoll TXDR         .       LL_SPI_TransmitData8
02422   * @param  SPIx SPI Instance
02423   * @param  TxData 0..0xFF
02424   * @retval None
02425   */
02426 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
02427 {
02428   *((__IO uint8_t *)&SPIx->TXDR) = TxData;
02429 }
02430
02431 /**
02432   * @brief  Write Data Register
02433   * @rmtoll TXDR         .       LL_SPI_TransmitData16
02434   * @param  SPIx SPI Instance
02435   * @param  TxData 0..0xFFFF
02436   * @retval None
02437   */
02438 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
02439 {
02440 #if defined (__GNUC__)
02441   __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
02442   *spitxdr = TxData;
02443 #else
02444   SPIx->TXDR = TxData;
02445 #endif
02446 }
02447
02448 /**
02449   * @brief  Write Data Register
02450   * @rmtoll TXDR         .       LL_SPI_TransmitData32
02451   * @param  SPIx SPI Instance
02452   * @param  TxData 0..0xFFFFFFFF
02453   * @retval None
02454   */
02455 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
02456 {
02457   *((__IO uint32_t *)&SPIx->TXDR) = TxData;
02458 }
02459
02460 /**
02461   * @brief  Set polynomial for CRC calcul
02462   * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_SetCRCPolynomial
02463   * @param  SPIx SPI Instance
02464   * @param  CRCPoly 0..0xFFFFFFFF
02465   * @retval None
02466   */
02467 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
02468 {
02469   WRITE_REG(SPIx->CRCPOLY, CRCPoly);
02470 }
02471
02472 /**
02473   * @brief  Get polynomial for CRC calcul
02474   * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_GetCRCPolynomial
02475   * @param  SPIx SPI Instance
02476   * @retval 0..0xFFFFFFFF
02477   */
02478 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
02479 {
02480   return (uint32_t)(READ_REG(SPIx->CRCPOLY));
02481 }
02482
02483 /**
02484   * @brief  Set the underrun pattern
02485   * @rmtoll UDRDR        UDRDR         LL_SPI_SetUDRPattern
02486   * @param  SPIx SPI Instance
02487   * @param  Pattern 0..0xFFFFFFFF
02488   * @retval None
02489   */
02490 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
02491 {
02492   WRITE_REG(SPIx->UDRDR, Pattern);
02493 }
02494
02495 /**
02496   * @brief  Get the underrun pattern
02497   * @rmtoll UDRDR        UDRDR         LL_SPI_GetUDRPattern
02498   * @param  SPIx SPI Instance
02499   * @retval 0..0xFFFFFFFF
02500   */
02501 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
02502 {
02503   return (uint32_t)(READ_REG(SPIx->UDRDR));
02504 }
02505
02506 /**
02507   * @brief  Get Rx CRC
02508   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
02509   * @param  SPIx SPI Instance
02510   * @retval 0..0xFFFFFFFF
02511   */
02512 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
02513 {
02514   return (uint32_t)(READ_REG(SPIx->RXCRC));
02515 }
02516
02517 /**
02518   * @brief  Get Tx CRC
02519   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
02520   * @param  SPIx SPI Instance
02521   * @retval 0..0xFFFFFFFF
02522   */
02523 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
02524 {
02525   return (uint32_t)(READ_REG(SPIx->TXCRC));
02526 }
02527
02528 /**
02529   * @}
02530   */
02531
02532 #if defined(USE_FULL_LL_DRIVER)
02533 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
02534   * @{
02535   */
02536
02537 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
02538 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
02539 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
02540
02541 /**
02542   * @}
02543   */
02544 #endif /* USE_FULL_LL_DRIVER */
02545 /**
02546   * @}
02547   */
02548
02549 /** @defgroup I2S_LL I2S
02550   * @{
02551   */
02552
02553 /* Private variables ---------------------------------------------------------*/
02554 /* Private constants ---------------------------------------------------------*/
02555 /* Private macros ------------------------------------------------------------*/
02556
02557 /* Exported types ------------------------------------------------------------*/
02558 #if defined(USE_FULL_LL_DRIVER)
02559 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
02560   * @{
02561   */
02562
02563 /**
02564   * @brief  I2S Init structure definition
02565   */
02566
02567 typedef struct
02568 {
02569   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
02570                                          This parameter can be a value of @ref I2S_LL_EC_MODE
02571
02572                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
02573
02574   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
02575                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
02576
02577                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
02578
02579
02580   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
02581                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
02582
02583                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
02584
02585
02586   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
02587                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
02588
02589                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
02590
02591
02592   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
02593                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
02594
02595                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
02596                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
02597
02598
02599   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
02600                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
02601
02602                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
02603
02604 } LL_I2S_InitTypeDef;
02605
02606 /**
02607   * @}
02608   */
02609 #endif /*USE_FULL_LL_DRIVER*/
02610
02611 /* Exported constants --------------------------------------------------------*/
02612 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
02613   * @{
02614   */
02615
02616 /** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
02617   * @{
02618   */
02619 #define LL_I2S_DATAFORMAT_16B               (0x00000000UL)
02620 #define LL_I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
02621 #define LL_I2S_DATAFORMAT_24B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
02622 #define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED  (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
02623 #define LL_I2S_DATAFORMAT_32B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
02624 /**
02625   * @}
02626   */
02627
02628 /** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
02629   * @{
02630   */
02631 #define LL_I2S_SLAVE_VARIABLE_CH_LENGTH     (0x00000000UL)
02632 #define LL_I2S_SLAVE_FIXED_CH_LENGTH        (SPI_I2SCFGR_FIXCH)
02633 /**
02634   * @}
02635   */
02636
02637 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
02638   * @{
02639   */
02640 #define LL_I2S_POLARITY_LOW                 (0x00000000UL)
02641 #define LL_I2S_POLARITY_HIGH                (SPI_I2SCFGR_CKPOL)
02642 /**
02643   * @}
02644   */
02645
02646 /** @defgroup I2S_LL_EC_STANDARD I2S Standard
02647   * @{
02648   */
02649 #define LL_I2S_STANDARD_PHILIPS             (0x00000000UL)
02650 #define LL_I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
02651 #define LL_I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
02652 #define LL_I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
02653 #define LL_I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
02654 /**
02655   * @}
02656   */
02657
02658 /** @defgroup I2S_LL_EC_MODE Operation Mode
02659   * @{
02660   */
02661 #define LL_I2S_MODE_SLAVE_TX                (0x00000000UL)
02662 #define LL_I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
02663 #define LL_I2S_MODE_SLAVE_FULL_DUPLEX       (SPI_I2SCFGR_I2SCFG_2)
02664 #define LL_I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
02665 #define LL_I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
02666 #define LL_I2S_MODE_MASTER_FULL_DUPLEX      (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
02667 /**
02668   * @}
02669   */
02670
02671 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
02672   * @{
02673   */
02674 #define LL_I2S_PRESCALER_PARITY_EVEN        (0x00000000UL)           /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
02675 #define LL_I2S_PRESCALER_PARITY_ODD         (0x00000001UL)           /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
02676 /**
02677   * @}
02678   */
02679
02680 /** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
02681   * @{
02682   */
02683 #define LL_I2S_FIFO_TH_01DATA               (LL_SPI_FIFO_TH_01DATA)
02684 #define LL_I2S_FIFO_TH_02DATA               (LL_SPI_FIFO_TH_02DATA)
02685 #define LL_I2S_FIFO_TH_03DATA               (LL_SPI_FIFO_TH_03DATA)
02686 #define LL_I2S_FIFO_TH_04DATA               (LL_SPI_FIFO_TH_04DATA)
02687 #define LL_I2S_FIFO_TH_05DATA               (LL_SPI_FIFO_TH_05DATA)
02688 #define LL_I2S_FIFO_TH_06DATA               (LL_SPI_FIFO_TH_06DATA)
02689 #define LL_I2S_FIFO_TH_07DATA               (LL_SPI_FIFO_TH_07DATA)
02690 #define LL_I2S_FIFO_TH_08DATA               (LL_SPI_FIFO_TH_08DATA)
02691 /**
02692   * @}
02693   */
02694
02695 /** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
02696   * @{
02697   */
02698 #define LL_I2S_LSB_FIRST                    (LL_SPI_LSB_FIRST)
02699 #define LL_I2S_MSB_FIRST                    (LL_SPI_MSB_FIRST)
02700 /**
02701   * @}
02702   */
02703
02704 #if defined(USE_FULL_LL_DRIVER)
02705
02706 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
02707   * @{
02708   */
02709 #define LL_I2S_MCLK_OUTPUT_DISABLE          (0x00000000UL)
02710 #define LL_I2S_MCLK_OUTPUT_ENABLE           (SPI_I2SCFGR_MCKOE)
02711 /**
02712   * @}
02713   */
02714
02715 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
02716   * @{
02717   */
02718
02719 #define LL_I2S_AUDIOFREQ_192K               192000UL       /*!< Audio Frequency configuration 192000 Hz       */
02720 #define LL_I2S_AUDIOFREQ_96K                96000UL        /*!< Audio Frequency configuration  96000 Hz       */
02721 #define LL_I2S_AUDIOFREQ_48K                48000UL        /*!< Audio Frequency configuration  48000 Hz       */
02722 #define LL_I2S_AUDIOFREQ_44K                44100UL        /*!< Audio Frequency configuration  44100 Hz       */
02723 #define LL_I2S_AUDIOFREQ_32K                32000UL        /*!< Audio Frequency configuration  32000 Hz       */
02724 #define LL_I2S_AUDIOFREQ_22K                22050UL        /*!< Audio Frequency configuration  22050 Hz       */
02725 #define LL_I2S_AUDIOFREQ_16K                16000UL        /*!< Audio Frequency configuration  16000 Hz       */
02726 #define LL_I2S_AUDIOFREQ_11K                11025UL        /*!< Audio Frequency configuration  11025 Hz       */
02727 #define LL_I2S_AUDIOFREQ_8K                 8000UL         /*!< Audio Frequency configuration   8000 Hz       */
02728 #define LL_I2S_AUDIOFREQ_DEFAULT            0UL            /*!< Audio Freq not specified. Register I2SDIV = 0 */
02729 /**
02730   * @}
02731   */
02732 #endif /* USE_FULL_LL_DRIVER */
02733
02734 /**
02735   * @}
02736   */
02737
02738 /* Exported macro ------------------------------------------------------------*/
02739 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
02740   * @{
02741   */
02742
02743 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
02744   * @{
02745   */
02746
02747 /**
02748   * @brief  Write a value in I2S register
02749   * @param  __INSTANCE__ I2S Instance
02750   * @param  __REG__ Register to be written
02751   * @param  __VALUE__ Value to be written in the register
02752   * @retval None
02753   */
02754 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
02755
02756 /**
02757   * @brief  Read a value in I2S register
02758   * @param  __INSTANCE__ I2S Instance
02759   * @param  __REG__ Register to be read
02760   * @retval Register value
02761   */
02762 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
02763 /**
02764   * @}
02765   */
02766
02767 /**
02768   * @}
02769   */
02770
02771
02772 /* Exported functions --------------------------------------------------------*/
02773
02774 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
02775   * @{
02776   */
02777
02778 /** @defgroup I2S_LL_EF_Configuration Configuration
02779   * @{
02780   */
02781
02782 /**
02783   * @brief  Set I2S Data frame format
02784   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
02785   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat\n
02786   *         I2SCFGR      DATFMT        LL_I2S_SetDataFormat
02787   * @param  SPIx SPI Handle
02788   * @param  DataLength This parameter can be one of the following values:
02789   *         @arg @ref LL_I2S_DATAFORMAT_16B
02790   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
02791   *         @arg @ref LL_I2S_DATAFORMAT_24B
02792   *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
02793   *         @arg @ref LL_I2S_DATAFORMAT_32B
02794   * @retval None
02795   */
02796 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
02797 {
02798   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
02799 }
02800
02801 /**
02802   * @brief  Get I2S Data frame format
02803   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
02804   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat\n
02805   *         I2SCFGR      DATFMT        LL_I2S_GetDataFormat
02806   * @param  SPIx SPI Handle
02807   * @retval Return value can be one of the following values:
02808   *         @arg @ref LL_I2S_DATAFORMAT_16B
02809   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
02810   *         @arg @ref LL_I2S_DATAFORMAT_24B
02811   *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
02812   *         @arg @ref LL_I2S_DATAFORMAT_32B
02813   */
02814 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
02815 {
02816   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
02817 }
02818
02819 /**
02820   * @brief  Set I2S Channel Length Type
02821   * @note   This feature is usefull with SLAVE only
02822   * @rmtoll I2SCFGR      FIXCH        LL_I2S_SetChannelLengthType
02823   * @param  SPIx SPI Handle
02824   * @param  ChannelLengthType This parameter can be one of the following values:
02825   *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
02826   *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
02827   * @retval None
02828   */
02829 __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
02830 {
02831   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
02832 }
02833
02834 /**
02835   * @brief  Get I2S Channel Length Type
02836   * @note   This feature is usefull with SLAVE only
02837   * @rmtoll I2SCFGR      FIXCH         LL_I2S_GetChannelLengthType
02838   * @param  SPIx SPI Handle
02839   * @retval Return value can be one of the following values:
02840   *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
02841   *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
02842   */
02843 __STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
02844 {
02845   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
02846 }
02847
02848 /**
02849   * @brief  Invert the default polarity of WS signal
02850   * @rmtoll I2SCFGR      WSINV         LL_I2S_EnableWordSelectInversion
02851   * @param  SPIx SPI Handle
02852   * @retval None
02853   */
02854 __STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
02855 {
02856   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
02857 }
02858
02859 /**
02860   * @brief  Use the default polarity of WS signal
02861   * @rmtoll I2SCFGR      WSINV         LL_I2S_DisableWordSelectInversion
02862   * @param  SPIx SPI Handle
02863   * @retval None
02864   */
02865 __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
02866 {
02867   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
02868 }
02869
02870 /**
02871   * @brief  Check if polarity of WS signal is inverted
02872   * @rmtoll I2SCFGR      WSINV         LL_I2S_IsEnabledWordSelectInversion
02873   * @param  SPIx SPI Handle
02874   * @retval State of bit (1 or 0)
02875   */
02876 __STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
02877 {
02878   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
02879 }
02880
02881 /**
02882   * @brief  Set 2S Clock Polarity
02883   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
02884   * @param  SPIx SPI Handle
02885   * @param  ClockPolarity This parameter can be one of the following values:
02886   *         @arg @ref LL_I2S_POLARITY_LOW
02887   *         @arg @ref LL_I2S_POLARITY_HIGH
02888   * @retval None
02889   */
02890 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
02891 {
02892   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
02893 }
02894
02895 /**
02896   * @brief  Get 2S Clock Polarity
02897   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
02898   * @param  SPIx SPI Handle
02899   * @retval Return value can be one of the following values:
02900   *         @arg @ref LL_I2S_POLARITY_LOW
02901   *         @arg @ref LL_I2S_POLARITY_HIGH
02902   */
02903 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
02904 {
02905   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
02906 }
02907
02908 /**
02909   * @brief  Set I2S standard
02910   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
02911   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
02912   * @param  SPIx SPI Handle
02913   * @param  Standard This parameter can be one of the following values:
02914   *         @arg @ref LL_I2S_STANDARD_PHILIPS
02915   *         @arg @ref LL_I2S_STANDARD_MSB
02916   *         @arg @ref LL_I2S_STANDARD_LSB
02917   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
02918   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
02919   * @retval None
02920   */
02921 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
02922 {
02923   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
02924 }
02925
02926 /**
02927   * @brief  Get I2S standard
02928   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
02929   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
02930   * @param  SPIx SPI Handle
02931   * @retval Return value can be one of the following values:
02932   *         @arg @ref LL_I2S_STANDARD_PHILIPS
02933   *         @arg @ref LL_I2S_STANDARD_MSB
02934   *         @arg @ref LL_I2S_STANDARD_LSB
02935   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
02936   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
02937   */
02938 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
02939 {
02940   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
02941 }
02942
02943 /**
02944   * @brief  Set I2S config
02945   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
02946   * @param  SPIx SPI Handle
02947   * @param  Standard This parameter can be one of the following values:
02948   *         @arg @ref LL_I2S_MODE_SLAVE_TX
02949   *         @arg @ref LL_I2S_MODE_SLAVE_RX
02950   *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
02951   *         @arg @ref LL_I2S_MODE_MASTER_TX
02952   *         @arg @ref LL_I2S_MODE_MASTER_RX
02953   *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
02954   * @retval None
02955   */
02956 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
02957 {
02958   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
02959 }
02960
02961 /**
02962   * @brief  Get I2S config
02963   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
02964   * @param  SPIx SPI Handle
02965   * @retval Return value can be one of the following values:
02966   *         @arg @ref LL_I2S_MODE_SLAVE_TX
02967   *         @arg @ref LL_I2S_MODE_SLAVE_RX
02968   *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
02969   *         @arg @ref LL_I2S_MODE_MASTER_TX
02970   *         @arg @ref LL_I2S_MODE_MASTER_RX
02971   *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
02972   */
02973 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
02974 {
02975   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
02976 }
02977
02978 /**
02979   * @brief  Select I2S mode and Enable I2S peripheral
02980   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
02981   *         CR1          SPE           LL_I2S_Enable
02982   * @param  SPIx SPI Handle
02983   * @retval None
02984   */
02985 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
02986 {
02987   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
02988   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
02989 }
02990
02991 /**
02992   * @brief  Disable I2S peripheral and disable I2S mode
02993   * @rmtoll CR1          SPE           LL_I2S_Disable\n
02994   *         I2SCFGR      I2SMOD        LL_I2S_Disable
02995   * @param  SPIx SPI Handle
02996   * @retval None
02997   */
02998 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
02999 {
03000   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
03001   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
03002 }
03003
03004 /**
03005   * @brief  Swap the SDO and SDI pin
03006   * @note   This configuration can not be changed when I2S is enabled.
03007   * @rmtoll CFG2         IOSWP         LL_I2S_EnableIOSwap
03008   * @param  SPIx SPI Instance
03009   * @retval None
03010   */
03011 __STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
03012 {
03013   LL_SPI_EnableIOSwap(SPIx);
03014 }
03015
03016 /**
03017   * @brief  Restore default function for SDO and SDI pin
03018   * @note   This configuration can not be changed when I2S is enabled.
03019   * @rmtoll CFG2         IOSWP         LL_I2S_DisableIOSwap
03020   * @param  SPIx SPI Instance
03021   * @retval None
03022   */
03023 __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
03024 {
03025   LL_SPI_DisableIOSwap(SPIx);
03026 }
03027
03028 /**
03029   * @brief  Check if SDO and SDI pin are swapped
03030   * @rmtoll CFG2         IOSWP         LL_I2S_IsEnabledIOSwap
03031   * @param  SPIx SPI Instance
03032   * @retval State of bit (1 or 0)
03033   */
03034 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
03035 {
03036   return LL_SPI_IsEnabledIOSwap(SPIx);
03037 }
03038
03039 /**
03040   * @brief  Enable GPIO control
03041   * @note   This configuration can not be changed when I2S is enabled.
03042   * @rmtoll CFG2         AFCNTR        LL_I2S_EnableGPIOControl
03043   * @param  SPIx SPI Instance
03044   * @retval None
03045   */
03046 __STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
03047 {
03048   LL_SPI_EnableGPIOControl(SPIx);
03049 }
03050
03051 /**
03052   * @brief  Disable GPIO control
03053   * @note   This configuration can not be changed when I2S is enabled.
03054   * @rmtoll CFG2         AFCNTR        LL_I2S_DisableGPIOControl
03055   * @param  SPIx SPI Instance
03056   * @retval None
03057   */
03058 __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
03059 {
03060   LL_SPI_DisableGPIOControl(SPIx);
03061 }
03062
03063 /**
03064   * @brief  Check if GPIO control is active
03065   * @rmtoll CFG2         AFCNTR        LL_I2S_IsEnabledGPIOControl
03066   * @param  SPIx SPI Instance
03067   * @retval State of bit (1 or 0)
03068   */
03069 __STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
03070 {
03071   return LL_SPI_IsEnabledGPIOControl(SPIx);
03072 }
03073
03074 /**
03075   * @brief  Lock the AF configuration of associated IOs
03076   * @note   Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
03077   *         The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
03078   * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock
03079   * @param  SPIx SPI Instance
03080   * @retval None
03081   */
03082 __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
03083 {
03084   LL_SPI_EnableIOLock(SPIx);
03085 }
03086
03087 /**
03088   * @brief  Check if the the SPI_CFG2 register is locked
03089   * @rmtoll CR1          IOLOCK        LL_I2S_IsEnabledIOLock
03090   * @param  SPIx SPI Instance
03091   * @retval State of bit (1 or 0)
03092   */
03093 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
03094 {
03095   return LL_SPI_IsEnabledIOLock(SPIx);
03096 }
03097
03098 /**
03099   * @brief  Set Transfer Bit Order
03100   * @note   This configuration can not be changed when I2S is enabled.
03101   * @rmtoll CFG2         LSBFRST       LL_I2S_SetTransferBitOrder
03102   * @param  SPIx SPI Instance
03103   * @param  BitOrder This parameter can be one of the following values:
03104   *         @arg @ref LL_I2S_LSB_FIRST
03105   *         @arg @ref LL_I2S_MSB_FIRST
03106   * @retval None
03107   */
03108 __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
03109 {
03110   LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
03111 }
03112 /**
03113   * @brief  Get Transfer Bit Order
03114   * @rmtoll CFG2         LSBFRST       LL_I2S_GetTransferBitOrder
03115   * @param  SPIx SPI Instance
03116   * @retval Returned value can be one of the following values:
03117   *         @arg @ref LL_I2S_LSB_FIRST
03118   *         @arg @ref LL_I2S_MSB_FIRST
03119   */
03120 __STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
03121 {
03122   return LL_SPI_GetTransferBitOrder(SPIx);
03123 }
03124
03125 /**
03126   * @brief  Start effective transfer on wire
03127   * @rmtoll CR1          CSTART        LL_I2S_StartTransfer
03128   * @param  SPIx SPI Instance
03129   * @retval None
03130   */
03131 __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
03132 {
03133   LL_SPI_StartMasterTransfer(SPIx);
03134 }
03135
03136 /**
03137   * @brief  Check if there is an unfinished transfer
03138   * @rmtoll CR1          CSTART        LL_I2S_IsTransferActive
03139   * @param  SPIx SPI Instance
03140   * @retval State of bit (1 or 0)
03141   */
03142 __STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
03143 {
03144   return LL_SPI_IsActiveMasterTransfer(SPIx);
03145 }
03146
03147 /**
03148   * @brief  Set threshold of FIFO that triggers a transfer event
03149   * @note   This configuration can not be changed when I2S is enabled.
03150   * @rmtoll CFG1         FTHLV         LL_I2S_SetFIFOThreshold
03151   * @param  SPIx SPI Instance
03152   * @param  Threshold This parameter can be one of the following values:
03153   *         @arg @ref LL_I2S_FIFO_TH_01DATA
03154   *         @arg @ref LL_I2S_FIFO_TH_02DATA
03155   *         @arg @ref LL_I2S_FIFO_TH_03DATA
03156   *         @arg @ref LL_I2S_FIFO_TH_04DATA
03157   *         @arg @ref LL_I2S_FIFO_TH_05DATA
03158   *         @arg @ref LL_I2S_FIFO_TH_06DATA
03159   *         @arg @ref LL_I2S_FIFO_TH_07DATA
03160   *         @arg @ref LL_I2S_FIFO_TH_08DATA
03161   * @retval None
03162   */
03163 __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
03164 {
03165   LL_SPI_SetFIFOThreshold(SPIx, Threshold);
03166 }
03167
03168 /**
03169   * @brief  Get threshold of FIFO that triggers a transfer event
03170   * @rmtoll CFG1         FTHLV         LL_I2S_GetFIFOThreshold
03171   * @param  SPIx SPI Instance
03172   * @retval Returned value can be one of the following values:
03173   *         @arg @ref LL_I2S_FIFO_TH_01DATA
03174   *         @arg @ref LL_I2S_FIFO_TH_02DATA
03175   *         @arg @ref LL_I2S_FIFO_TH_03DATA
03176   *         @arg @ref LL_I2S_FIFO_TH_04DATA
03177   *         @arg @ref LL_I2S_FIFO_TH_05DATA
03178   *         @arg @ref LL_I2S_FIFO_TH_06DATA
03179   *         @arg @ref LL_I2S_FIFO_TH_07DATA
03180   *         @arg @ref LL_I2S_FIFO_TH_08DATA
03181   */
03182 __STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
03183 {
03184   return LL_SPI_GetFIFOThreshold(SPIx);
03185 }
03186
03187 /**
03188   * @brief  Set I2S linear prescaler
03189   * @rmtoll I2SCFGR        I2SDIV        LL_I2S_SetPrescalerLinear
03190   * @param  SPIx SPI Instance
03191   * @param  PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
03192   * @note   PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
03193   * @retval None
03194   */
03195 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
03196 {
03197   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
03198 }
03199
03200 /**
03201   * @brief  Get I2S linear prescaler
03202   * @rmtoll I2SCFGR        I2SDIV        LL_I2S_GetPrescalerLinear
03203   * @param  SPIx SPI Instance
03204   * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
03205   */
03206 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
03207 {
03208   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
03209 }
03210
03211 /**
03212   * @brief  Set I2S parity prescaler
03213   * @rmtoll I2SCFGR        ODD           LL_I2S_SetPrescalerParity
03214   * @param  SPIx SPI Instance
03215   * @param  PrescalerParity This parameter can be one of the following values:
03216   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
03217   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
03218   * @retval None
03219   */
03220 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
03221 {
03222   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
03223 }
03224
03225 /**
03226   * @brief  Get I2S parity prescaler
03227   * @rmtoll I2SCFGR        ODD           LL_I2S_GetPrescalerParity
03228   * @param  SPIx SPI Instance
03229   * @retval Returned value can be one of the following values:
03230   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
03231   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
03232   */
03233 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
03234 {
03235   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
03236 }
03237
03238 /**
03239   * @brief  Enable the Master Clock Output (Pin MCK)
03240   * @rmtoll I2SCFGR      MCKOE         LL_I2S_EnableMasterClock
03241   * @param  SPIx SPI Handle
03242   * @retval None
03243   */
03244 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
03245 {
03246   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
03247 }
03248
03249 /**
03250   * @brief  Disable the Master Clock Ouput (Pin MCK)
03251   * @rmtoll I2SCFGR      MCKOE         LL_I2S_DisableMasterClock
03252   * @param  SPIx SPI Handle
03253   * @retval None
03254   */
03255 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
03256 {
03257   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
03258 }
03259
03260 /**
03261   * @brief  Check if the master clock output (Pin MCK) is enabled
03262   * @rmtoll I2SCFGR        MCKOE         LL_I2S_IsEnabledMasterClock
03263   * @param  SPIx SPI Instance
03264   * @retval State of bit (1 or 0)
03265   */
03266 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
03267 {
03268   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
03269 }
03270
03271 /**
03272   * @}
03273   */
03274
03275
03276 /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
03277   * @{
03278   */
03279
03280 /**
03281   * @brief  Check if there enough data in FIFO to read a full packet
03282   * @rmtoll SR           RXP           LL_I2S_IsActiveFlag_RXP
03283   * @param  SPIx SPI Instance
03284   * @retval State of bit (1 or 0)
03285   */
03286 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
03287 {
03288   return LL_SPI_IsActiveFlag_RXP(SPIx);
03289 }
03290
03291 /**
03292   * @brief  Check if there enough space in FIFO to hold a full packet
03293   * @rmtoll SR           TXP           LL_I2S_IsActiveFlag_TXP
03294   * @param  SPIx SPI Instance
03295   * @retval State of bit (1 or 0)
03296   */
03297 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
03298 {
03299   return LL_SPI_IsActiveFlag_TXP(SPIx);
03300 }
03301
03302 /**
03303   * @brief  Get Underrun error flag
03304   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
03305   * @param  SPIx SPI Instance
03306   * @retval State of bit (1 or 0)
03307   */
03308 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
03309 {
03310   return LL_SPI_IsActiveFlag_UDR(SPIx);
03311 }
03312
03313 /**
03314   * @brief  Get Overrun error flag
03315   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
03316   * @param  SPIx SPI Instance
03317   * @retval State of bit (1 or 0).
03318   */
03319 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
03320 {
03321   return LL_SPI_IsActiveFlag_OVR(SPIx);
03322 }
03323
03324 /**
03325   * @brief  Get TI Frame format error flag
03326   * @rmtoll SR           TIFRE         LL_I2S_IsActiveFlag_FRE
03327   * @param  SPIx SPI Instance
03328   * @retval State of bit (1 or 0).
03329   */
03330 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
03331 {
03332   return LL_SPI_IsActiveFlag_FRE(SPIx);
03333 }
03334
03335 /**
03336   * @brief  Clear Underrun error flag
03337   * @rmtoll IFCR         UDRC          LL_I2S_ClearFlag_UDR
03338   * @param  SPIx SPI Instance
03339   * @retval None
03340   */
03341 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
03342 {
03343   LL_SPI_ClearFlag_UDR(SPIx);
03344 }
03345
03346 /**
03347   * @brief  Clear Overrun error flag
03348   * @rmtoll IFCR         OVRC          LL_I2S_ClearFlag_OVR
03349   * @param  SPIx SPI Instance
03350   * @retval None
03351   */
03352 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
03353 {
03354   LL_SPI_ClearFlag_OVR(SPIx);
03355 }
03356
03357 /**
03358   * @brief  Clear Frame format error flag
03359   * @rmtoll IFCR         TIFREC        LL_I2S_ClearFlag_FRE
03360   * @param  SPIx SPI Instance
03361   * @retval None
03362   */
03363 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
03364 {
03365   LL_SPI_ClearFlag_FRE(SPIx);
03366 }
03367
03368 /**
03369   * @}
03370   */
03371
03372 /** @defgroup I2S_LL_EF_IT_Management IT_Management
03373   * @{
03374   */
03375
03376 /**
03377   * @brief  Enable Rx Packet available IT
03378   * @rmtoll IER          RXPIE         LL_I2S_EnableIT_RXP
03379   * @param  SPIx SPI Instance
03380   * @retval None
03381   */
03382 __STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
03383 {
03384   LL_SPI_EnableIT_RXP(SPIx);
03385 }
03386
03387 /**
03388   * @brief  Enable Tx Packet space available IT
03389   * @rmtoll IER          TXPIE         LL_I2S_EnableIT_TXP
03390   * @param  SPIx SPI Instance
03391   * @retval None
03392   */
03393 __STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
03394 {
03395   LL_SPI_EnableIT_TXP(SPIx);
03396 }
03397
03398 /**
03399   * @brief  Enable Underrun IT
03400   * @rmtoll IER          UDRIE         LL_I2S_EnableIT_UDR
03401   * @param  SPIx SPI Instance
03402   * @retval None
03403   */
03404 __STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
03405 {
03406   LL_SPI_EnableIT_UDR(SPIx);
03407 }
03408
03409 /**
03410   * @brief  Enable Overrun IT
03411   * @rmtoll IER          OVRIE         LL_I2S_EnableIT_OVR
03412   * @param  SPIx SPI Instance
03413   * @retval None
03414   */
03415 __STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
03416 {
03417   LL_SPI_EnableIT_OVR(SPIx);
03418 }
03419
03420 /**
03421   * @brief  Enable TI Frame Format Error IT
03422   * @rmtoll IER          TIFREIE       LL_I2S_EnableIT_FRE
03423   * @param  SPIx SPI Instance
03424   * @retval None
03425   */
03426 __STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
03427 {
03428   LL_SPI_EnableIT_FRE(SPIx);
03429 }
03430
03431 /**
03432   * @brief  Disable Rx Packet available IT
03433   * @rmtoll IER          RXPIE         LL_I2S_DisableIT_RXP
03434   * @param  SPIx SPI Instance
03435   * @retval None
03436   */
03437 __STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
03438 {
03439   LL_SPI_DisableIT_RXP(SPIx);
03440 }
03441
03442 /**
03443   * @brief  Disable Tx Packet space available IT
03444   * @rmtoll IER          TXPIE         LL_I2S_DisableIT_TXP
03445   * @param  SPIx SPI Instance
03446   * @retval None
03447   */
03448 __STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
03449 {
03450   LL_SPI_DisableIT_TXP(SPIx);
03451 }
03452
03453 /**
03454   * @brief  Disable Underrun IT
03455   * @rmtoll IER          UDRIE         LL_I2S_DisableIT_UDR
03456   * @param  SPIx SPI Instance
03457   * @retval None
03458   */
03459 __STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
03460 {
03461   LL_SPI_DisableIT_UDR(SPIx);
03462 }
03463
03464 /**
03465   * @brief  Disable Overrun IT
03466   * @rmtoll IER          OVRIE         LL_I2S_DisableIT_OVR
03467   * @param  SPIx SPI Instance
03468   * @retval None
03469   */
03470 __STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
03471 {
03472   LL_SPI_DisableIT_OVR(SPIx);
03473 }
03474
03475 /**
03476   * @brief  Disable TI Frame Format Error IT
03477   * @rmtoll IER          TIFREIE       LL_I2S_DisableIT_FRE
03478   * @param  SPIx SPI Instance
03479   * @retval None
03480   */
03481 __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
03482 {
03483   LL_SPI_DisableIT_FRE(SPIx);
03484 }
03485
03486 /**
03487   * @brief  Check if Rx Packet available IT is enabled
03488   * @rmtoll IER          RXPIE         LL_I2S_IsEnabledIT_RXP
03489   * @param  SPIx SPI Instance
03490   * @retval State of bit (1 or 0)
03491   */
03492 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
03493 {
03494   return LL_SPI_IsEnabledIT_RXP(SPIx);
03495 }
03496
03497 /**
03498   * @brief  Check if Tx Packet space available IT is enabled
03499   * @rmtoll IER          TXPIE         LL_I2S_IsEnabledIT_TXP
03500   * @param  SPIx SPI Instance
03501   * @retval State of bit (1 or 0)
03502   */
03503 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
03504 {
03505   return LL_SPI_IsEnabledIT_TXP(SPIx);
03506 }
03507
03508 /**
03509   * @brief  Check if Underrun IT is enabled
03510   * @rmtoll IER          UDRIE         LL_I2S_IsEnabledIT_UDR
03511   * @param  SPIx SPI Instance
03512   * @retval State of bit (1 or 0)
03513   */
03514 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
03515 {
03516   return LL_SPI_IsEnabledIT_UDR(SPIx);
03517 }
03518
03519 /**
03520   * @brief  Check if Overrun IT is enabled
03521   * @rmtoll IER          OVRIE         LL_I2S_IsEnabledIT_OVR
03522   * @param  SPIx SPI Instance
03523   * @retval State of bit (1 or 0)
03524   */
03525 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
03526 {
03527   return LL_SPI_IsEnabledIT_OVR(SPIx);
03528 }
03529
03530 /**
03531   * @brief  Check if TI Frame Format Error IT is enabled
03532   * @rmtoll IER          TIFREIE       LL_I2S_IsEnabledIT_FRE
03533   * @param  SPIx SPI Instance
03534   * @retval State of bit (1 or 0)
03535   */
03536 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
03537 {
03538   return LL_SPI_IsEnabledIT_FRE(SPIx);
03539 }
03540
03541 /**
03542   * @}
03543   */
03544
03545 /** @defgroup I2S_LL_EF_DMA_Management DMA_Management
03546   * @{
03547   */
03548
03549 /**
03550   * @brief  Enable DMA Rx
03551   * @rmtoll CFG1         RXDMAEN       LL_I2S_EnableDMAReq_RX
03552   * @param  SPIx SPI Instance
03553   * @retval None
03554   */
03555 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
03556 {
03557   LL_SPI_EnableDMAReq_RX(SPIx);
03558 }
03559
03560 /**
03561   * @brief  Disable DMA Rx
03562   * @rmtoll CFG1         RXDMAEN       LL_I2S_DisableDMAReq_RX
03563   * @param  SPIx SPI Instance
03564   * @retval None
03565   */
03566 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
03567 {
03568   LL_SPI_DisableDMAReq_RX(SPIx);
03569 }
03570
03571 /**
03572   * @brief  Check if DMA Rx is enabled
03573   * @rmtoll CFG1         RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
03574   * @param  SPIx SPI Instance
03575   * @retval State of bit (1 or 0)
03576   */
03577 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
03578 {
03579   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
03580 }
03581
03582 /**
03583   * @brief  Enable DMA Tx
03584   * @rmtoll CFG1         TXDMAEN       LL_I2S_EnableDMAReq_TX
03585   * @param  SPIx SPI Instance
03586   * @retval None
03587   */
03588 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
03589 {
03590   LL_SPI_EnableDMAReq_TX(SPIx);
03591 }
03592
03593 /**
03594   * @brief  Disable DMA Tx
03595   * @rmtoll CFG1         TXDMAEN       LL_I2S_DisableDMAReq_TX
03596   * @param  SPIx SPI Instance
03597   * @retval None
03598   */
03599 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
03600 {
03601   LL_SPI_DisableDMAReq_TX(SPIx);
03602 }
03603
03604 /**
03605   * @brief  Check if DMA Tx is enabled
03606   * @rmtoll CFG1         TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
03607   * @param  SPIx SPI Instance
03608   * @retval State of bit (1 or 0)
03609   */
03610 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
03611 {
03612   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
03613 }
03614
03615 /**
03616   * @}
03617   */
03618
03619 /** @defgroup I2S_LL_EF_DATA_Management DATA_Management
03620   * @{
03621   */
03622
03623 /**
03624   * @brief  Read Data Register
03625   * @rmtoll RXDR         .       LL_I2S_ReceiveData16
03626   * @param  SPIx SPI Instance
03627   * @retval 0..0xFFFF
03628   */
03629 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
03630 {
03631   return LL_SPI_ReceiveData16(SPIx);
03632 }
03633
03634 /**
03635   * @brief  Read Data Register
03636   * @rmtoll RXDR         .       LL_I2S_ReceiveData32
03637   * @param  SPIx SPI Instance
03638   * @retval  0..0xFFFFFFFF
03639   */
03640 __STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
03641 {
03642   return LL_SPI_ReceiveData32(SPIx);
03643 }
03644
03645 /**
03646   * @brief  Write Data Register
03647   * @rmtoll TXDR         .       LL_I2S_TransmitData16
03648   * @param  SPIx SPI Instance
03649   * @param  TxData 0..0xFFFF
03650   * @retval None
03651   */
03652 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
03653 {
03654   LL_SPI_TransmitData16(SPIx, TxData);
03655 }
03656
03657 /**
03658   * @brief  Write Data Register
03659   * @rmtoll TXDR         .       LL_I2S_TransmitData32
03660   * @param  SPIx SPI Instance
03661   * @param  TxData 0..0xFFFFFFFF
03662   * @retval None
03663   */
03664 __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
03665 {
03666   LL_SPI_TransmitData32(SPIx, TxData);
03667 }
03668
03669 /**
03670   * @}
03671   */
03672
03673
03674 #if defined(USE_FULL_LL_DRIVER)
03675 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
03676   * @{
03677   */
03678
03679 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
03680 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
03681 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
03682 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
03683
03684 /**
03685   * @}
03686   */
03687 #endif /* USE_FULL_LL_DRIVER */
03688
03689 /**
03690   * @}
03691   */
03692
03693 /**
03694   * @}
03695   */
03696
03697 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
03698
03699 /**
03700   * @}
03701   */
03702
03703 /**
03704   * @}
03705   */
03706 #ifdef __cplusplus
03707 }
03708 #endif
03709
03710 #endif /* STM32H7xx_LL_SPI_H */
03711
03712 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_swpmi.c Source File

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stm32h7xx_ll_swpmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_swpmi.c
00004   * @author  MCD Application Team
00005   * @brief   SWPMI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_swpmi.h"
00023 #include "stm32h7xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034
00035 /** @addtogroup SWPMI_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup SWPMI_LL_Private_Macros
00044   * @{
00045   */
00046
00047 #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
00048
00049 #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
00050                                           || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))
00051
00052 #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
00053                                           || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))
00054
00055 #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
00056                                            || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))
00057
00058 /**
00059   * @}
00060   */
00061
00062 /* Private function prototypes -----------------------------------------------*/
00063
00064 /* Exported functions --------------------------------------------------------*/
00065 /** @addtogroup SWPMI_LL_Exported_Functions
00066   * @{
00067   */
00068
00069 /** @addtogroup SWPMI_LL_EF_Init
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  De-initialize the SWPMI peripheral registers to their default reset values.
00075   * @param  SWPMIx SWPMI Instance
00076   * @retval An ErrorStatus enumeration value
00077   *          - SUCCESS: SWPMI registers are de-initialized
00078   *          - ERROR: Not applicable
00079   */
00080 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
00081 {
00082   ErrorStatus status = SUCCESS;
00083
00084   /* Check the parameter */
00085   assert_param(IS_SWPMI_INSTANCE(SWPMIx));
00086
00087   if (SWPMIx == SWPMI1)
00088   {
00089     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1);
00090     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1);
00091   }
00092   else
00093   {
00094     status = ERROR;
00095   }
00096
00097   return status;
00098 }
00099
00100 /**
00101   * @brief  Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
00102   * @note   As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
00103   *         SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
00104   * @param  SWPMIx           SWPMI Instance
00105   * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
00106   *                          the configuration information for the SWPMI peripheral.
00107   * @retval An ErrorStatus enumeration value
00108   *          - SUCCESS: SWPMI registers are initialized
00109   *          - ERROR: SWPMI registers are not initialized
00110   */
00111 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
00112 {
00113   ErrorStatus status = SUCCESS;
00114
00115   /* Check the parameters */
00116   assert_param(IS_SWPMI_INSTANCE(SWPMIx));
00117   assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler));
00118   assert_param(IS_LL_SWPMI_SW_BUFFER_TX(SWPMI_InitStruct->TxBufferingMode));
00119   assert_param(IS_LL_SWPMI_SW_BUFFER_RX(SWPMI_InitStruct->RxBufferingMode));
00120   assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass));
00121
00122   /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */
00123   if (LL_SWPMI_IsActivated(SWPMIx) == 0U)
00124   {
00125     /* Configure the BRR register (Bitrate) */
00126     LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler);
00127
00128     /* Configure the voltage class */
00129     LL_SWPMI_SetVoltageClass(SWPMIx, SWPMI_InitStruct->VoltageClass);
00130
00131     /* Set the new configuration of the SWPMI peripheral */
00132     MODIFY_REG(SWPMIx->CR,
00133               (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
00134               (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
00135   }
00136   /* Else (SWPMI not in deactivated state => return ERROR) */
00137   else
00138   {
00139     status = ERROR;
00140   }
00141
00142   return status;
00143 }
00144
00145 /**
00146   * @brief  Set each @ref LL_SWPMI_InitTypeDef field to default value.
00147   * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
00148   *                          the configuration information for the SWPMI peripheral.
00149   * @retval None
00150   */
00151 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
00152 {
00153   /* Set SWPMI_InitStruct fields to default values */
00154   SWPMI_InitStruct->VoltageClass     = LL_SWPMI_VOLTAGE_CLASS_C;
00155   SWPMI_InitStruct->BitRatePrescaler = (uint32_t)0x00000001;
00156   SWPMI_InitStruct->TxBufferingMode  = LL_SWPMI_SW_BUFFER_TX_SINGLE;
00157   SWPMI_InitStruct->RxBufferingMode  = LL_SWPMI_SW_BUFFER_RX_SINGLE;
00158 }
00159
00160 /**
00161   * @}
00162   */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /**
00169   * @}
00170   */
00171
00172
00173 /**
00174   * @}
00175   */
00176
00177 #endif /* USE_FULL_LL_DRIVER */
00178
00179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_swpmi.h Source File

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stm32h7xx_ll_swpmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_swpmi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SWPMI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_SWPMI_H
00022 #define STM32H7xx_LL_SWPMI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035
00036 /** @defgroup SWPMI_LL SWPMI
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 #if defined(USE_FULL_LL_DRIVER)
00045 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
00046   * @{
00047   */
00048 /**
00049   * @}
00050   */
00051 #endif /*USE_FULL_LL_DRIVER*/
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 #if defined(USE_FULL_LL_DRIVER)
00055 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
00056   * @{
00057   */
00058
00059 /**
00060   * @brief  SWPMI Init structures definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.
00065                                         This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
00066
00067                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
00068
00069   uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.
00070                                         This parameter must be a number between Min_Data=0 and Max_Data=255U.
00071
00072                                         The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
00073
00074                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
00075
00076   uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.
00077                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
00078
00079                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
00080
00081   uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.
00082                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
00083
00084                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
00085 } LL_SWPMI_InitTypeDef;
00086
00087 /**
00088   * @}
00089   */
00090 #endif /* USE_FULL_LL_DRIVER */
00091
00092 /* Exported constants --------------------------------------------------------*/
00093 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
00094   * @{
00095   */
00096
00097 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
00098   * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
00099   * @{
00100   */
00101 #define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */
00102 #define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */
00103 #define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */
00104 #define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */
00105 #define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
00106 #define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */
00107 #define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
00113   * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
00114   * @{
00115   */
00116 #define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */
00117 #define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */
00118 #define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */
00119 #define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */
00120 #define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */
00121 #define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */
00122 #define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */
00123 #define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */
00124 #define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */
00125 #define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */
00126 #define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SWPMI_LL_EC_IT IT Defines
00132   * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
00133   * @{
00134   */
00135 #define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */
00136 #define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */
00137 #define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */
00138 #define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */
00139 #define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
00140 #define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */
00141 #define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */
00142 #define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */
00143 #define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
00149   * @{
00150   */
00151 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */
00152 #define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
00158   * @{
00159   */
00160 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */
00161 #define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
00167   * @{
00168   */
00169 #define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */
00170 #define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
00176   * @{
00177   */
00178 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */
00179 #define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macro ------------------------------------------------------------*/
00189 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
00190   * @{
00191   */
00192
00193 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
00194   * @{
00195   */
00196
00197 /**
00198   * @brief  Write a value in SWPMI register
00199   * @param  __INSTANCE__ SWPMI Instance
00200   * @param  __REG__ Register to be written
00201   * @param  __VALUE__ Value to be written in the register
00202   * @retval None
00203   */
00204 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00205
00206 /**
00207   * @brief  Read a value in SWPMI register
00208   * @param  __INSTANCE__ SWPMI Instance
00209   * @param  __REG__ Register to be read
00210   * @retval Register value
00211   */
00212 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
00218   * @{
00219   */
00220
00221 /**
00222   * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
00223   * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
00224   * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
00225   * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)
00226   * @retval Bitrate prescaler (BRR register)
00227   */
00228 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
00229
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /* Exported functions --------------------------------------------------------*/
00239 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
00240   * @{
00241   */
00242
00243 /** @defgroup SWPMI_LL_EF_Configuration Configuration
00244   * @{
00245   */
00246
00247 /**
00248   * @brief  Set Reception buffering mode
00249   * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.
00250   * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
00251   * @param  SWPMIx SWPMI Instance
00252   * @param  RxBufferingMode This parameter can be one of the following values:
00253   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00254   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00255   * @retval None
00256   */
00257 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
00258 {
00259   MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
00260 }
00261
00262 /**
00263   * @brief  Get Reception buffering mode
00264   * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
00265   * @param  SWPMIx SWPMI Instance
00266   * @retval Returned value can be one of the following values:
00267   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00268   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00269   */
00270 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
00271 {
00272   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
00273 }
00274
00275 /**
00276   * @brief  Set Transmission buffering mode
00277   * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.
00278   * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
00279   * @param  SWPMIx SWPMI Instance
00280   * @param  TxBufferingMode This parameter can be one of the following values:
00281   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00282   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
00286 {
00287   MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
00288 }
00289
00290 /**
00291   * @brief  Get Transmission buffering mode
00292   * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
00293   * @param  SWPMIx SWPMI Instance
00294   * @retval Returned value can be one of the following values:
00295   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00296   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00297   */
00298 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
00299 {
00300   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
00301 }
00302
00303 /**
00304   * @brief  Enable loopback mode
00305   * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
00306   * @param  SWPMIx SWPMI Instance
00307   * @retval None
00308   */
00309 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
00310 {
00311   SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00312 }
00313
00314 /**
00315   * @brief  Disable loopback mode
00316   * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
00317   * @param  SWPMIx SWPMI Instance
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
00321 {
00322   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00323 }
00324
00325 /**
00326   * @brief  Enable SWPMI transceiver
00327   * @note   SWPMI_IO pin is controlled by SWPMI
00328   * @rmtoll CR           SWPEN          LL_SWPMI_EnableTransceiver
00329   * @param  SWPMIx SWPMI Instance
00330   * @retval None
00331   */
00332 __STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
00333 {
00334   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
00335 }
00336
00337 /**
00338   * @brief  Disable SWPMI transceiver
00339   * @note   SWPMI_IO pin is controlled by GPIO controller
00340   * @rmtoll CR           SWPEN          LL_SWPMI_DisableTransceiver
00341   * @param  SWPMIx SWPMI Instance
00342   * @retval None
00343   */
00344 __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
00345 {
00346   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
00347 }
00348
00349 /**
00350   * @brief  Check if SWPMI transceiver is enabled
00351   * @rmtoll CR           SWPEN         LL_SWPMI_IsEnabledTransceiver
00352   * @param  SWPMIx SWPMI Instance
00353   * @retval State of bit (1 or 0).
00354   */
00355 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)
00356 {
00357   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);
00358 }
00359
00360 /**
00361   * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
00362   * @note   SWP bus stays in the ACTIVATED state as long as there is a communication
00363   *         with the slave, either in transmission or in reception. The SWP bus switches back
00364   *         to the SUSPENDED state as soon as there is no more transmission or reception
00365   *         activity, after 7 idle bits.
00366   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00367   * @param  SWPMIx SWPMI Instance
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
00371 {
00372   /* In order to activate SWP again, the software must clear DEACT bit*/
00373   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00374
00375   /* Set SWACT bit */
00376   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00377 }
00378
00379 /**
00380   * @brief  Check if Single wire protocol bus is in ACTIVATED state.
00381   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00382   * @param  SWPMIx SWPMI Instance
00383   * @retval State of bit (1 or 0).
00384   */
00385 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
00386 {
00387   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
00388 }
00389
00390 /**
00391   * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
00392   *         DEACTIVATED state)
00393   * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
00394   * @param  SWPMIx SWPMI Instance
00395   * @retval None
00396   */
00397 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
00398 {
00399   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00400 }
00401
00402 /**
00403   * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
00404   *         state if no resume from slave)
00405   * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
00406   * @param  SWPMIx SWPMI Instance
00407   * @retval None
00408   */
00409 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
00410 {
00411   SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00412 }
00413
00414 /**
00415   * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00416   * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
00417   * @param  SWPMIx SWPMI Instance
00418   * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=255U
00419   * @retval None
00420   */
00421 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
00422 {
00423   WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
00424 }
00425
00426 /**
00427   * @brief  Get Bitrate prescaler
00428   * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
00429   * @param  SWPMIx SWPMI Instance
00430   * @retval A number between Min_Data=0 and Max_Data=255U
00431   */
00432 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
00433 {
00434   return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
00435 }
00436
00437 /**
00438   * @brief  Set SWP Voltage Class
00439   * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
00440   * @param  SWPMIx SWPMI Instance
00441   * @param  VoltageClass This parameter can be one of the following values:
00442   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00443   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00444   * @retval None
00445   */
00446 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
00447 {
00448   MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
00449 }
00450
00451 /**
00452   * @brief  Get SWP Voltage Class
00453   * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
00454   * @param  SWPMIx SWPMI Instance
00455   * @retval Returned value can be one of the following values:
00456   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00457   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00458   */
00459 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
00460 {
00461   return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
00462 }
00463
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
00469   * @{
00470   */
00471
00472 /**
00473   * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.
00474   * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
00475   * @param  SWPMIx SWPMI Instance
00476   * @retval State of bit (1 or 0).
00477   */
00478 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00479 {
00480   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
00481 }
00482
00483 /**
00484   * @brief  Check if Frame transmission buffer has been emptied
00485   * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
00486   * @param  SWPMIx SWPMI Instance
00487   * @retval State of bit (1 or 0).
00488   */
00489 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00490 {
00491   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
00492 }
00493
00494 /**
00495   * @brief  Check if CRC error in reception has been detected
00496   * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
00497   * @param  SWPMIx SWPMI Instance
00498   * @retval State of bit (1 or 0).
00499   */
00500 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00501 {
00502   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
00503 }
00504
00505 /**
00506   * @brief  Check if Overrun in reception has been detected
00507   * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
00508   * @param  SWPMIx SWPMI Instance
00509   * @retval State of bit (1 or 0).
00510   */
00511 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00512 {
00513   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
00514 }
00515
00516 /**
00517   * @brief  Check if underrun error in transmission has been detected
00518   * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
00519   * @param  SWPMIx SWPMI Instance
00520   * @retval State of bit (1 or 0).
00521   */
00522 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00523 {
00524   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
00525 }
00526
00527 /**
00528   * @brief  Check if Receive data register not empty (it means that Received data is ready
00529   *         to be read in the SWPMI_RDR register)
00530   * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
00531   * @param  SWPMIx SWPMI Instance
00532   * @retval State of bit (1 or 0).
00533   */
00534 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
00535 {
00536   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
00537 }
00538
00539 /**
00540   * @brief  Check if Transmit data register is empty (it means that Data written in transmit
00541   *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
00542   * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
00543   * @param  SWPMIx SWPMI Instance
00544   * @retval State of bit (1 or 0).
00545   */
00546 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
00547 {
00548   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
00549 }
00550
00551 /**
00552   * @brief  Check if Both transmission and reception are completed and SWP is switched to
00553   *         the SUSPENDED state
00554   * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
00555   * @param  SWPMIx SWPMI Instance
00556   * @retval State of bit (1 or 0).
00557   */
00558 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
00559 {
00560   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
00561 }
00562
00563 /**
00564   * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
00565   *         state
00566   * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
00567   * @param  SWPMIx SWPMI Instance
00568   * @retval State of bit (1 or 0).
00569   */
00570 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
00571 {
00572   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
00573 }
00574
00575 /**
00576   * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
00577   * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
00578   * @param  SWPMIx SWPMI Instance
00579   * @retval State of bit (1 or 0).
00580   */
00581 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
00582 {
00583   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
00584 }
00585
00586 /**
00587   * @brief  Check if SWP bus is in DEACTIVATED state
00588   * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
00589   * @param  SWPMIx SWPMI Instance
00590   * @retval State of bit (1 or 0).
00591   */
00592 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
00593 {
00594   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
00595 }
00596
00597 /**
00598   * @brief  Check if SWPMI transceiver is ready
00599   * @rmtoll ISR          RDYF        LL_SWPMI_IsActiveFlag_RDYF
00600   * @param  SWPMIx SWPMI Instance
00601   * @retval State of bit (1 or 0).
00602   */
00603 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)
00604 {
00605   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);
00606 }
00607
00608 /**
00609   * @brief  Clear receive buffer full flag
00610   * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
00611   * @param  SWPMIx SWPMI Instance
00612   * @retval None
00613   */
00614 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00615 {
00616   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
00617 }
00618
00619 /**
00620   * @brief  Clear transmit buffer empty flag
00621   * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
00622   * @param  SWPMIx SWPMI Instance
00623   * @retval None
00624   */
00625 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00626 {
00627   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
00628 }
00629
00630 /**
00631   * @brief  Clear receive CRC error flag
00632   * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
00633   * @param  SWPMIx SWPMI Instance
00634   * @retval None
00635   */
00636 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00637 {
00638   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
00639 }
00640
00641 /**
00642   * @brief  Clear receive overrun error flag
00643   * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
00644   * @param  SWPMIx SWPMI Instance
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00648 {
00649   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
00650 }
00651
00652 /**
00653   * @brief  Clear transmit underrun error flag
00654   * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
00655   * @param  SWPMIx SWPMI Instance
00656   * @retval None
00657   */
00658 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00659 {
00660   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
00661 }
00662
00663 /**
00664   * @brief  Clear transfer complete flag
00665   * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
00666   * @param  SWPMIx SWPMI Instance
00667   * @retval None
00668   */
00669 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
00670 {
00671   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
00672 }
00673
00674 /**
00675   * @brief  Clear slave resume flag
00676   * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
00677   * @param  SWPMIx SWPMI Instance
00678   * @retval None
00679   */
00680 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
00681 {
00682   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
00683 }
00684
00685 /**
00686   * @brief  Clear SWPMI transceiver ready flag
00687   * @rmtoll ISR          CRDYF        LL_SWPMI_ClearFlag_RDY
00688   * @param  SWPMIx SWPMI Instance
00689   * @retval None
00690   */
00691 __STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
00692 {
00693   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);
00694 }
00695
00696 /**
00697   * @}
00698   */
00699
00700 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
00701   * @{
00702   */
00703
00704 /**
00705   * @brief  Enable SWPMI transceiver ready interrupt
00706   * @rmtoll IER          RDYIE         LL_SWPMI_EnableIT_RDY
00707   * @param  SWPMIx SWPMI Instance
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
00711 {
00712   SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
00713 }
00714
00715 /**
00716   * @brief  Enable Slave resume interrupt
00717   * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
00718   * @param  SWPMIx SWPMI Instance
00719   * @retval None
00720   */
00721 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
00722 {
00723   SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00724 }
00725
00726 /**
00727   * @brief  Enable Transmit complete interrupt
00728   * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
00729   * @param  SWPMIx SWPMI Instance
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
00733 {
00734   SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00735 }
00736
00737 /**
00738   * @brief  Enable Transmit interrupt
00739   * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
00740   * @param  SWPMIx SWPMI Instance
00741   * @retval None
00742   */
00743 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
00744 {
00745   SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00746 }
00747
00748 /**
00749   * @brief  Enable Receive interrupt
00750   * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
00751   * @param  SWPMIx SWPMI Instance
00752   * @retval None
00753   */
00754 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
00755 {
00756   SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00757 }
00758
00759 /**
00760   * @brief  Enable Transmit underrun error interrupt
00761   * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
00762   * @param  SWPMIx SWPMI Instance
00763   * @retval None
00764   */
00765 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00766 {
00767   SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00768 }
00769
00770 /**
00771   * @brief  Enable Receive overrun error interrupt
00772   * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
00773   * @param  SWPMIx SWPMI Instance
00774   * @retval None
00775   */
00776 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00777 {
00778   SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00779 }
00780
00781 /**
00782   * @brief  Enable Receive CRC error interrupt
00783   * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
00784   * @param  SWPMIx SWPMI Instance
00785   * @retval None
00786   */
00787 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00788 {
00789   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00790 }
00791
00792 /**
00793   * @brief  Enable Transmit buffer empty interrupt
00794   * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
00795   * @param  SWPMIx SWPMI Instance
00796   * @retval None
00797   */
00798 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00799 {
00800   SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00801 }
00802
00803 /**
00804   * @brief  Enable Receive buffer full interrupt
00805   * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
00806   * @param  SWPMIx SWPMI Instance
00807   * @retval None
00808   */
00809 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00810 {
00811   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00812 }
00813
00814 /**
00815   * @brief  Disable SWPMI transceiver ready interrupt
00816   * @rmtoll IER          RDYIE         LL_SWPMI_DisableIT_RDY
00817   * @param  SWPMIx SWPMI Instance
00818   * @retval None
00819   */
00820 __STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
00821 {
00822   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
00823 }
00824
00825 /**
00826   * @brief  Disable Slave resume interrupt
00827   * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
00828   * @param  SWPMIx SWPMI Instance
00829   * @retval None
00830   */
00831 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
00832 {
00833   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00834 }
00835
00836 /**
00837   * @brief  Disable Transmit complete interrupt
00838   * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
00839   * @param  SWPMIx SWPMI Instance
00840   * @retval None
00841   */
00842 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
00843 {
00844   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00845 }
00846
00847 /**
00848   * @brief  Disable Transmit interrupt
00849   * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
00850   * @param  SWPMIx SWPMI Instance
00851   * @retval None
00852   */
00853 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
00854 {
00855   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00856 }
00857
00858 /**
00859   * @brief  Disable Receive interrupt
00860   * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
00861   * @param  SWPMIx SWPMI Instance
00862   * @retval None
00863   */
00864 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
00865 {
00866   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00867 }
00868
00869 /**
00870   * @brief  Disable Transmit underrun error interrupt
00871   * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
00872   * @param  SWPMIx SWPMI Instance
00873   * @retval None
00874   */
00875 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00876 {
00877   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00878 }
00879
00880 /**
00881   * @brief  Disable Receive overrun error interrupt
00882   * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
00883   * @param  SWPMIx SWPMI Instance
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00887 {
00888   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00889 }
00890
00891 /**
00892   * @brief  Disable Receive CRC error interrupt
00893   * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
00894   * @param  SWPMIx SWPMI Instance
00895   * @retval None
00896   */
00897 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00898 {
00899   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00900 }
00901
00902 /**
00903   * @brief  Disable Transmit buffer empty interrupt
00904   * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
00905   * @param  SWPMIx SWPMI Instance
00906   * @retval None
00907   */
00908 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00909 {
00910   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00911 }
00912
00913 /**
00914   * @brief  Disable Receive buffer full interrupt
00915   * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
00916   * @param  SWPMIx SWPMI Instance
00917   * @retval None
00918   */
00919 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00920 {
00921   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00922 }
00923
00924 /**
00925   * @brief  Check if SWPMI transceiver ready interrupt is enabled
00926   * @rmtoll IER          RDYIE         LL_SWPMI_IsEnabledIT_RDY
00927   * @param  SWPMIx SWPMI Instance
00928   * @retval State of bit (1 or 0).
00929   */
00930 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)
00931 {
00932   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);
00933 }
00934
00935 /**
00936   * @brief  Check if Slave resume interrupt is enabled
00937   * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
00938   * @param  SWPMIx SWPMI Instance
00939   * @retval State of bit (1 or 0).
00940   */
00941 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
00942 {
00943   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
00944 }
00945
00946 /**
00947   * @brief  Check if Transmit complete interrupt is enabled
00948   * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
00949   * @param  SWPMIx SWPMI Instance
00950   * @retval State of bit (1 or 0).
00951   */
00952 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
00953 {
00954   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
00955 }
00956
00957 /**
00958   * @brief  Check if Transmit interrupt is enabled
00959   * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
00960   * @param  SWPMIx SWPMI Instance
00961   * @retval State of bit (1 or 0).
00962   */
00963 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
00964 {
00965   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
00966 }
00967
00968 /**
00969   * @brief  Check if Receive interrupt is enabled
00970   * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
00971   * @param  SWPMIx SWPMI Instance
00972   * @retval State of bit (1 or 0).
00973   */
00974 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
00975 {
00976   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
00977 }
00978
00979 /**
00980   * @brief  Check if Transmit underrun error interrupt is enabled
00981   * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
00982   * @param  SWPMIx SWPMI Instance
00983   * @retval State of bit (1 or 0).
00984   */
00985 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00986 {
00987   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
00988 }
00989
00990 /**
00991   * @brief  Check if Receive overrun error interrupt is enabled
00992   * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
00993   * @param  SWPMIx SWPMI Instance
00994   * @retval State of bit (1 or 0).
00995   */
00996 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00997 {
00998   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
00999 }
01000
01001 /**
01002   * @brief  Check if Receive CRC error interrupt is enabled
01003   * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
01004   * @param  SWPMIx SWPMI Instance
01005   * @retval State of bit (1 or 0).
01006   */
01007 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
01008 {
01009   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
01010 }
01011
01012 /**
01013   * @brief  Check if Transmit buffer empty interrupt is enabled
01014   * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
01015   * @param  SWPMIx SWPMI Instance
01016   * @retval State of bit (1 or 0).
01017   */
01018 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
01019 {
01020   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
01021 }
01022
01023 /**
01024   * @brief  Check if Receive buffer full interrupt is enabled
01025   * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
01026   * @param  SWPMIx SWPMI Instance
01027   * @retval State of bit (1 or 0).
01028   */
01029 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
01030 {
01031   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
01032 }
01033
01034 /**
01035   * @}
01036   */
01037
01038 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
01039   * @{
01040   */
01041
01042 /**
01043   * @brief  Enable DMA mode for reception
01044   * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
01045   * @param  SWPMIx SWPMI Instance
01046   * @retval None
01047   */
01048 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
01049 {
01050   SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
01051 }
01052
01053 /**
01054   * @brief  Disable DMA mode for reception
01055   * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
01056   * @param  SWPMIx SWPMI Instance
01057   * @retval None
01058   */
01059 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
01060 {
01061   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
01062 }
01063
01064 /**
01065   * @brief  Check if DMA mode for reception is enabled
01066   * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
01067   * @param  SWPMIx SWPMI Instance
01068   * @retval State of bit (1 or 0).
01069   */
01070 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
01071 {
01072   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
01073 }
01074
01075 /**
01076   * @brief  Enable DMA mode for transmission
01077   * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
01078   * @param  SWPMIx SWPMI Instance
01079   * @retval None
01080   */
01081 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01082 {
01083   SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01084 }
01085
01086 /**
01087   * @brief  Disable DMA mode for transmission
01088   * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
01089   * @param  SWPMIx SWPMI Instance
01090   * @retval None
01091   */
01092 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01093 {
01094   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01095 }
01096
01097 /**
01098   * @brief  Check if DMA mode for transmission is enabled
01099   * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
01100   * @param  SWPMIx SWPMI Instance
01101   * @retval State of bit (1 or 0).
01102   */
01103 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01104 {
01105   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
01106 }
01107
01108 /**
01109   * @brief  Get the data register address used for DMA transfer
01110   * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
01111   *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
01112   * @param  SWPMIx SWPMI Instance
01113   * @param  Direction This parameter can be one of the following values:
01114   *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
01115   *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
01116   * @retval Address of data register
01117   */
01118 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
01119 {
01120   uint32_t data_reg_addr;
01121
01122   if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
01123   {
01124     /* return address of TDR register */
01125     data_reg_addr = (uint32_t)&(SWPMIx->TDR);
01126   }
01127   else
01128   {
01129     /* return address of RDR register */
01130     data_reg_addr = (uint32_t)&(SWPMIx->RDR);
01131   }
01132
01133   return data_reg_addr;
01134 }
01135
01136 /**
01137   * @}
01138   */
01139
01140 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
01141   * @{
01142   */
01143
01144 /**
01145   * @brief  Retrieve number of data bytes present in payload of received frame
01146   * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
01147   * @param  SWPMIx SWPMI Instance
01148   * @retval Value between Min_Data=0x00 and Max_Data=0x1F
01149   */
01150 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
01151 {
01152   return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
01153 }
01154
01155 /**
01156   * @brief  Transmit Data Register
01157   * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
01158   * @param  SWPMIx SWPMI Instance
01159   * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01160   * @retval None
01161   */
01162 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
01163 {
01164   WRITE_REG(SWPMIx->TDR, TxData);
01165 }
01166
01167 /**
01168   * @brief  Receive Data Register
01169   * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
01170   * @param  SWPMIx SWPMI Instance
01171   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01172   */
01173 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
01174 {
01175   return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
01176 }
01177
01178 /**
01179   * @brief  Enable SWP Transceiver Bypass
01180   * @note   The external interface for SWPMI is SWPMI_IO
01181   *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
01182   * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
01183   * @param  SWPMIx SWPMI Instance
01184   * @retval None
01185   */
01186 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
01187 {
01188   CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01189 }
01190
01191 /**
01192   * @brief  Disable SWP Transceiver Bypass
01193   * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
01194   *         function on GPIOs. This configuration is selected to connect an external transceiver
01195   * @note   In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared
01196   * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
01197   * @param  SWPMIx SWPMI Instance
01198   * @retval None
01199   */
01200 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
01201 {
01202   SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01203 }
01204
01205 /**
01206   * @}
01207   */
01208
01209 #if defined(USE_FULL_LL_DRIVER)
01210 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
01211   * @{
01212   */
01213
01214 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
01215 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01216 void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01217
01218 /**
01219   * @}
01220   */
01221 #endif /*USE_FULL_LL_DRIVER*/
01222
01223 /**
01224   * @}
01225   */
01226
01227 /**
01228   * @}
01229   */
01230
01231
01232 /**
01233   * @}
01234   */
01235
01236 #ifdef __cplusplus
01237 }
01238 #endif
01239
01240 #endif /* STM32H7xx_LL_SWPMI_H */
01241
01242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_system.h Source File

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stm32h7xx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SYSTEM LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL SYSTEM driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00014       (+) Access to DBGCMU registers
00015       (+) Access to SYSCFG registers
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Define to prevent recursive inclusion -------------------------------------*/
00033 #ifndef __STM32H7xx_LL_SYSTEM_H
00034 #define __STM32H7xx_LL_SYSTEM_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32h7xx.h"
00042
00043 /** @addtogroup STM32H7xx_LL_Driver
00044   * @{
00045   */
00046
00047 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
00048
00049 /** @defgroup SYSTEM_LL SYSTEM
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055
00056 /* Private constants ---------------------------------------------------------*/
00057 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00058   * @{
00059   */
00060 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
00061   * @{
00062   */
00063 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U
00064 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U
00065 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U
00066 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U
00067 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U
00068 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U
00069 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U
00070 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
00076   * @{
00077   */
00078 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U
00079 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U
00080 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U
00081 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U
00082 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U
00083 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U
00084 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U
00085 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U
00086 /**
00087   * @}
00088   */
00089 /**
00090   * @}
00091   */
00092
00093 /* Private macros ------------------------------------------------------------*/
00094
00095 /* Exported types ------------------------------------------------------------*/
00096 /* Exported constants --------------------------------------------------------*/
00097 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00102   * @{
00103   */
00104 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
00105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
00106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
00107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
00108 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
00109 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
00110 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
00111 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
00117 * @{
00118 */
00119 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */
00120 #define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */
00121 #define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */
00122 #define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */
00123 #define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */
00124 /**
00125   * @}
00126   */
00127
00128 #if defined(SYSCFG_PMCR_EPIS_SEL)
00129 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
00130 * @{
00131 */
00132 #define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */
00133 #define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL                   /*!< ETH Media RMII interface */
00134 /**
00135   * @}
00136   */
00137 #endif /* SYSCFG_PMCR_EPIS_SEL */
00138
00139 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00140   * @{
00141   */
00142 #define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
00143 #define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
00144 #define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
00145 #define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
00146 #define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
00147 #define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
00148 #define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
00149 #define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
00150 #define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
00151 #define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
00152 #define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00158   * @{
00159   */
00160 #define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
00161 #define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
00162 #define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
00163 #define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
00164 #define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
00165 #define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
00166 #define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
00167 #define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
00168 #define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
00169 #define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
00170 #define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
00171 #define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
00172 #define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
00173 #define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
00174 #define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
00175 #define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00181   * @{
00182   */
00183 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
00184                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00185
00186 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal
00187                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00188
00189 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal
00190                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00191
00192 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal
00193                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00194
00195 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal
00196                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00197
00198 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal
00199                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00200
00201 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal
00202                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00203
00204 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal
00205                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00206
00207 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal
00208                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00209
00210 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal
00211                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00212
00213 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection
00214                                                                      with TIM1/8/15/16/17 and HRTIM Break Input
00215                                                                      and also the PVDE and PLS bits of the Power Control Interface */
00216 #if defined(DUAL_CORE)
00217 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal
00218                                                                      with Break Input of TIM1/8/15/16/17 and HRTIM        */
00219 #endif /* DUAL_CORE */
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
00225   * @{
00226   */
00227 #define LL_SYSCFG_CELL_CODE               0U
00228 #define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
00234   * @{
00235   */
00236 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U
00237 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M
00238 /**
00239   * @}
00240   */
00241
00242 #if defined (DUAL_CORE)
00243 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
00244   * @{
00245   */
00246 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U
00247 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M
00248 /**
00249   * @}
00250   */
00251 #endif /* DUAL_CORE */
00252
00253 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
00254   * @{
00255   */
00256 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U
00257 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U
00258 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U
00259 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U
00260 /**
00261   * @}
00262   */
00263 #ifdef SYSCFG_PKGR_PKG
00264 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
00265   * @{
00266   */
00267 #define LL_SYSCFG_LQFP100_PACKAGE             0U
00268 #define LL_SYSCFG_TQFP144_PACKAGE             2U
00269 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U
00270 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U
00271 /**
00272   * @}
00273   */
00274 #endif /* SYSCFG_PKGR_PKG */
00275
00276 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
00277   * @{
00278   */
00279 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U
00280 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0
00281 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1
00282 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH
00283
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00289   * @{
00290   */
00291 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
00292 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00293 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00294 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00295 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00301   * @{
00302   */
00303 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */
00304 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */
00305 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */
00306 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */
00307 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */
00308 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */
00309 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */
00310 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */
00311 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */
00312 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */
00313 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
00314 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
00315 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
00321   * @{
00322   */
00323 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00329   * @{
00330   */
00331 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */
00332 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */
00333 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */
00334 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */
00335 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */
00336 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
00342   * @{
00343   */
00344 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
00350   * @{
00351   */
00352 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */
00353 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */
00354 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */
00355 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */
00356 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */
00357 #define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */
00358 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00364   * @{
00365   */
00366 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
00367 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
00368 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
00369 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
00370 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
00371 #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
00372 #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
00373 #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382 /* Exported macro ------------------------------------------------------------*/
00383
00384 /* Exported functions --------------------------------------------------------*/
00385 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00386   * @{
00387   */
00388
00389 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00390   * @{
00391   */
00392
00393 #if defined(SYSCFG_PMCR_EPIS_SEL)
00394 /**
00395   * @brief  Select Ethernet PHY interface
00396   * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface
00397   * @param  Interface This parameter can be one of the following values:
00398   *         @arg @ref LL_SYSCFG_ETH_MII
00399   *         @arg @ref LL_SYSCFG_ETH_RMII
00400   * @retval None
00401   */
00402 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
00403 {
00404   MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
00405 }
00406
00407 /**
00408   * @brief  Get Ethernet PHY interface
00409   * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface
00410   * @retval Returned value can be one of the following values:
00411   *         @arg @ref LL_SYSCFG_ETH_MII
00412   *         @arg @ref LL_SYSCFG_ETH_RMII
00413   */
00414 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
00415 {
00416   return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
00417 }
00418
00419 #endif /* SYSCFG_PMCR_EPIS_SEL */
00420 /**
00421   * @brief  Open an Analog Switch
00422   * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch
00423   * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch
00424   * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch
00425   * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch
00426   * @param  AnalogSwitch This parameter can be one of the following values:
00427   *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
00428   *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
00429   *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
00430   *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
00431   * @retval None
00432   */
00433 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
00434 {
00435   SET_BIT(SYSCFG->PMCR, AnalogSwitch);
00436 }
00437
00438 /**
00439   * @brief  Close an Analog Switch
00440   * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch
00441   * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch
00442   * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch
00443   * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch
00444   * @param  AnalogSwitch This parameter can be one of the following values:
00445   *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
00446   *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
00447   *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
00448   *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
00449   * @retval None
00450   */
00451 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
00452 {
00453   CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
00454 }
00455 #ifdef SYSCFG_PMCR_BOOSTEN
00456 /**
00457   * @brief  Enable the Analog booster to reduce the total harmonic distortion
00458   *         of the analog switch when the supply voltage is lower than 2.7 V
00459   * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster
00460   * @note   Activating the booster allows to guaranty the analog switch AC performance
00461   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00462   *         performance is the same on the full voltage range
00463   * @retval None
00464   */
00465 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00466 {
00467  SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00468 }
00469
00470 /**
00471   * @brief  Disable the Analog booster
00472   * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster
00473   * @note   Activating the booster allows to guaranty the analog switch AC performance
00474   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00475   *         performance is the same on the full voltage range
00476   * @retval None
00477   */
00478 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00479 {
00480  CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00481 }
00482 #endif /*SYSCFG_PMCR_BOOSTEN*/
00483 /**
00484   * @brief  Enable the I2C fast mode plus driving capability.
00485   * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
00486   *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
00487   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00488   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00489   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00490   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00491   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00492   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00493   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00494   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00495   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
00496   *
00497   *         (*) value not defined in all devices
00498   * @retval None
00499   */
00500 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00501 {
00502   SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
00503 }
00504
00505 /**
00506   * @brief  Disable the I2C fast mode plus driving capability.
00507   * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
00508   *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
00509   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00510   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00511   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00512   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00513   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00514   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00515   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00516   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00517   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
00518   *         (*) value not defined in all devices
00519   * @retval None
00520   */
00521 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00522 {
00523   CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
00524 }
00525
00526 /**
00527   * @brief  Configure source input for the EXTI external interrupt.
00528   * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n
00529   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
00530   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
00531   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
00532   * @param  Port This parameter can be one of the following values:
00533   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00534   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00535   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00536   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00537   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00538   *         @arg @ref LL_SYSCFG_EXTI_PORTF
00539   *         @arg @ref LL_SYSCFG_EXTI_PORTG
00540   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00541   *         @arg @ref LL_SYSCFG_EXTI_PORTI
00542   *         @arg @ref LL_SYSCFG_EXTI_PORTJ
00543   *         @arg @ref LL_SYSCFG_EXTI_PORTK
00544   *
00545   *         (*) value not defined in all devices
00546   * @param  Line This parameter can be one of the following values:
00547   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00548   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00549   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00550   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00551   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00552   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00553   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00554   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00555   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00556   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00557   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00558   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00559   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00560   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00561   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00562   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00563   * @retval None
00564   */
00565 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
00566 {
00567   MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
00568 }
00569
00570 /**
00571   * @brief  Get the configured defined for specific EXTI Line
00572   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
00573   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
00574   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
00575   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
00576   * @param  Line This parameter can be one of the following values:
00577   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00578   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00579   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00580   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00581   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00582   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00583   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00584   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00585   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00586   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00587   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00588   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00589   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00590   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00591   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00592   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00593   * @retval Returned value can be one of the following values:
00594   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00595   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00596   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00597   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00598   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00599   *         @arg @ref LL_SYSCFG_EXTI_PORTF
00600   *         @arg @ref LL_SYSCFG_EXTI_PORTG
00601   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00602   *         @arg @ref LL_SYSCFG_EXTI_PORTI
00603   *         @arg @ref LL_SYSCFG_EXTI_PORTJ
00604   *         @arg @ref LL_SYSCFG_EXTI_PORTK
00605   *         (*) value not defined in all devices
00606   */
00607 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
00608 {
00609   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
00610 }
00611
00612 /**
00613   * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
00614   * @note this feature is available on STM32H7 rev.B and above
00615   * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n
00616   *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n
00617   *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n
00618   *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n
00619   *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n
00620   *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n
00621   *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n
00622   *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n
00623   *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n
00624   *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n
00625   *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n
00626   *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs
00627   * @param  Break This parameter can be a combination of the following values:
00628   *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
00629   *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
00630   *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
00631   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
00632   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
00633   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
00634   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
00635   *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
00636   *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
00637   *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
00638   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00639   *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
00643 {
00644 #if defined(DUAL_CORE)
00645   MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
00646                            SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
00647                            SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);
00648 #elif defined (SYSCFG_CFGR_AXISRAML)
00649   MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
00650                            SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
00651                            SYSCFG_CFGR_PVDL, Break);
00652 #else
00653   MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\
00654                            SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
00655                            SYSCFG_CFGR_PVDL, Break);
00656 #endif /* DUAL_CORE */
00657 }
00658
00659 /**
00660   * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
00661   * @note this feature is available on STM32H7 rev.B and above
00662   * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n
00663   *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n
00664   *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n
00665   *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n
00666   *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n
00667   *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n
00668   *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n
00669   *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n
00670   *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n
00671   *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n
00672   *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n
00673   *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs
00674   * @retval Returned value can be can be a combination of the following values:
00675   *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
00676   *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
00677   *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
00678   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
00679   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
00680   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
00681   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
00682   *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
00683   *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
00684   *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
00685   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00686   *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
00687   */
00688 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
00689 {
00690 #if defined(DUAL_CORE)
00691   return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
00692                                             SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
00693                                             SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
00694                                             SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));
00695 #elif defined (SYSCFG_CFGR_AXISRAML)
00696   return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
00697                                             SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
00698                                             SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
00699                                             SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
00700 #else
00701   return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \
00702                                             SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
00703 #endif /* DUAL_CORE */
00704 }
00705
00706 /**
00707   * @brief  Enable the Compensation Cell
00708   * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell
00709   * @note   The I/O compensation cell can be used only when the device supply
00710   *         voltage ranges from 2.4 to 3.6 V
00711   * @retval None
00712   */
00713 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
00714 {
00715   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
00716 }
00717
00718 /**
00719   * @brief  Disable the Compensation Cell
00720   * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell
00721   * @note   The I/O compensation cell can be used only when the device supply
00722   *         voltage ranges from 2.4 to 3.6 V
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
00726 {
00727   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
00728 }
00729
00730 /**
00731   * @brief  Check if the Compensation Cell is enabled
00732   * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell
00733   * @retval State of bit (1 or 0).
00734   */
00735 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
00736 {
00737   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
00738 }
00739
00740 /**
00741   * @brief  Get Compensation Cell ready Flag
00742   * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
00746 {
00747   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
00748 }
00749
00750 /**
00751   * @brief  Enable the I/O speed optimization when the product voltage is low.
00752   * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize
00753   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00754   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00755   *         might be destructive.
00756   * @retval None
00757   */
00758 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
00759 {
00760 #if defined(SYSCFG_CCCSR_HSLV)
00761   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
00762 #else
00763   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
00764 #endif   /* SYSCFG_CCCSR_HSLV */
00765 }
00766
00767 #if defined(SYSCFG_CCCSR_HSLV1)
00768 /**
00769   * @brief  Enable the I/O speed optimization when the product voltage is low.
00770   * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize
00771   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00772   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00773   *         might be destructive.
00774   * @retval None
00775   */
00776 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
00777 {
00778   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
00779 }
00780
00781 /**
00782   * @brief  Enable the I/O speed optimization when the product voltage is low.
00783   * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize
00784   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00785   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00786   *         might be destructive.
00787   * @retval None
00788   */
00789 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
00790 {
00791   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
00792 }
00793
00794 /**
00795   * @brief  Enable the I/O speed optimization when the product voltage is low.
00796   * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize
00797   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00798   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00799   *         might be destructive.
00800   * @retval None
00801   */
00802 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
00803 {
00804   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
00805 }
00806 #endif /*SYSCFG_CCCSR_HSLV1*/
00807
00808
00809 /**
00810   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00811   * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize
00812   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00813   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00814   *         might be destructive.
00815   * @retval None
00816   */
00817 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
00818 {
00819 #if defined(SYSCFG_CCCSR_HSLV)
00820   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
00821 #else
00822   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
00823 #endif   /* SYSCFG_CCCSR_HSLV */
00824 }
00825
00826 #if defined(SYSCFG_CCCSR_HSLV1)
00827 /**
00828   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00829   * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize
00830   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00831   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00832   *         might be destructive.
00833   * @retval None
00834   */
00835 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
00836 {
00837   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
00838 }
00839
00840 /**
00841   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00842   * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize
00843   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00844   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00845   *         might be destructive.
00846   * @retval None
00847   */
00848 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
00849 {
00850   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
00851 }
00852
00853 /**
00854   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00855   * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize
00856   * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
00857   *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
00858   *         might be destructive.
00859   * @retval None
00860   */
00861 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
00862 {
00863   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
00864 }
00865 #endif /*SYSCFG_CCCSR_HSLV1*/
00866
00867 /**
00868   * @brief  Check if the I/O speed optimization is enabled
00869   * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization
00870   * @retval State of bit (1 or 0).
00871   */
00872 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
00873 {
00874 #if defined(SYSCFG_CCCSR_HSLV)
00875   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
00876 #else
00877   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
00878 #endif /*SYSCFG_CCCSR_HSLV*/
00879 }
00880
00881 #if defined(SYSCFG_CCCSR_HSLV1)
00882 /**
00883   * @brief  Check if the I/O speed optimization is enabled
00884   * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization
00885   * @retval State of bit (1 or 0).
00886   */
00887 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
00888 {
00889   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
00890 }
00891
00892 /**
00893   * @brief  Check if the I/O speed optimization is enabled
00894   * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization
00895   * @retval State of bit (1 or 0).
00896   */
00897 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
00898 {
00899   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
00900 }
00901
00902 /**
00903   * @brief  Check if the I/O speed optimization is enabled
00904   * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization
00905   * @retval State of bit (1 or 0).
00906   */
00907 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
00908 {
00909   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
00910 }
00911 #endif /*SYSCFG_CCCSR_HSLV1*/
00912
00913 /**
00914   * @brief  Set the code selection for the I/O Compensation cell
00915   * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode
00916   * @param  CompCode: Selects the code to be applied for the I/O compensation cell
00917   *   This parameter can be one of the following values:
00918   *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
00919   *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
00923 {
00924   SET_BIT(SYSCFG->CCCSR, CompCode);
00925 }
00926
00927 /**
00928   * @brief  Get the code selected for the I/O Compensation cell
00929   * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
00930   * @retval Returned value can be one of the following values:
00931   *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
00932   *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
00933   */
00934 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
00935 {
00936   return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
00937 }
00938
00939 #ifdef SYSCFG_CCCSR_CS_MMC
00940
00941 /**
00942   * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail
00943   * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
00944   * @retval Returned value can be one of the following values:
00945   *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
00946   *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
00947   */
00948 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
00949 {
00950   return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
00951 }
00952 #endif /*SYSCFG_CCCSR_CS_MMC*/
00953
00954 /**
00955   * @brief  Get I/O compensation cell value for PMOS transistors
00956   * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue
00957   * @retval Returned value is the I/O compensation cell value for PMOS transistors
00958   */
00959 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
00960 {
00961   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
00962 }
00963
00964 /**
00965   * @brief  Get I/O compensation cell value for NMOS transistors
00966   * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue
00967   * @retval Returned value is the I/O compensation cell value for NMOS transistors
00968   */
00969 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
00970 {
00971   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
00972 }
00973
00974 /**
00975   * @brief  Set I/O compensation cell code for PMOS transistors
00976   * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
00977   * @param  PMOSCode PMOS compensation code
00978   *         This code is applied to the I/O compensation cell when the CS bit of the
00979   *         SYSCFG_CMPCR is set
00980   * @retval None
00981   */
00982 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
00983 {
00984   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
00985 }
00986
00987 /**
00988   * @brief  Get I/O compensation cell code for PMOS transistors
00989   * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
00990   * @retval Returned value is the I/O compensation cell code for PMOS transistors
00991   */
00992 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
00993 {
00994   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
00995 }
00996
00997 #ifdef SYSCFG_CCCR_PCC_MMC
00998
00999 /**
01000   * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
01001   * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
01002   * @param  PMOSCode PMOS compensation code
01003   *         This code is applied to the I/O compensation cell when the CS bit of the
01004   *         SYSCFG_CMPCR is set
01005   * @retval None
01006   */
01007 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
01008 {
01009   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
01010 }
01011
01012 /**
01013   * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
01014   * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
01015   * @retval Returned value is the I/O compensation cell code for PMOS transistors
01016   */
01017 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
01018 {
01019   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
01020 }
01021 #endif /* SYSCFG_CCCR_PCC_MMC */
01022
01023 /**
01024   * @brief  Set I/O compensation cell code for NMOS transistors
01025   * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
01026   * @param  NMOSCode NMOS compensation code
01027   *         This code is applied to the I/O compensation cell when the CS bit of the
01028   *         SYSCFG_CMPCR is set
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
01032 {
01033   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
01034 }
01035
01036 /**
01037   * @brief  Get I/O compensation cell code for NMOS transistors
01038   * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
01039   * @retval Returned value is the I/O compensation cell code for NMOS transistors
01040   */
01041 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
01042 {
01043   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
01044 }
01045
01046 #ifdef SYSCFG_CCCR_NCC_MMC
01047
01048 /**
01049   * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
01050   * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
01051   * @param  NMOSCode: NMOS compensation code
01052   *         This code is applied to the I/O compensation cell when the CS bit of the
01053   *         SYSCFG_CMPCR is set
01054   * @retval None
01055   */
01056 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
01057 {
01058   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
01059 }
01060
01061 /**
01062   * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
01063   * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
01064   * @retval Returned value is the I/O compensation cell code for NMOS transistors
01065   */
01066 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
01067 {
01068   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
01069 }
01070 #endif /*SYSCFG_CCCR_NCC_MMC*/
01071
01072 #ifdef SYSCFG_PKGR_PKG
01073 /**
01074   * @brief  Get the device package
01075   * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage
01076   * @retval Returned value can be one of the following values:
01077   *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE
01078   *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE
01079   *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
01080   *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
01081   */
01082 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
01083 {
01084   return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
01085 }
01086 #endif /*SYSCFG_PKGR_PKG*/
01087
01088 #ifdef SYSCFG_UR0_RDP
01089 /**
01090   * @brief  Get the Flash memory protection level
01091   * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel
01092   * @retval Returned value can be one of the following values:
01093   *         0xAA : RDP level 0
01094   *         0xCC : RDP level 2
01095   *         Any other value : RDP level 1
01096   */
01097 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
01098 {
01099   return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
01100 }
01101 /**
01102   * @brief  Indicate if the Flash memory bank addresses are inverted or not
01103   * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped
01104   * @retval State of bit (1 or 0).
01105   */
01106 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
01107 {
01108   return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
01109 }
01110
01111 /**
01112   * @brief  Get the BOR Threshold Reset Level
01113   * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel
01114   * @retval Returned value can be one of the following values:
01115   *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
01116   *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
01117   *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
01118   *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
01119   */
01120 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
01121 {
01122   return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
01123 }
01124 /**
01125   * @brief  BootCM7 address 0 configuration
01126   * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0
01127   * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
01128   * @retval None
01129   */
01130 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
01131 {
01132   /* Configure CM7 BOOT ADD0 */
01133 #if defined(DUAL_CORE)
01134   MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
01135 #else
01136   MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
01137 #endif /*DUAL_CORE*/
01138
01139 }
01140
01141 /**
01142   * @brief  Get BootCM7 address 0
01143   * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0
01144   * @retval Returned the CM7 Boot Address0
01145   */
01146 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
01147 {
01148   /* Get CM7 BOOT ADD0 */
01149 #if defined(DUAL_CORE)
01150   return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
01151 #else
01152   return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
01153 #endif /*DUAL_CORE*/
01154 }
01155
01156 /**
01157   * @brief  BootCM7 address 1 configuration
01158   * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1
01159   * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
01160   * @retval None
01161   */
01162 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
01163 {
01164   /* Configure CM7 BOOT ADD1 */
01165 #if defined(DUAL_CORE)
01166   MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
01167 #else
01168   MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
01169 #endif /*DUAL_CORE*/
01170 }
01171
01172 /**
01173   * @brief  Get BootCM7 address 1
01174   * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1
01175   * @retval Returned the CM7 Boot Address0
01176   */
01177 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
01178 {
01179   /* Get CM7 BOOT ADD0 */
01180 #if defined(DUAL_CORE)
01181   return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
01182 #else
01183   return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
01184 #endif /* DUAL_CORE */
01185 }
01186
01187 #if defined(DUAL_CORE)
01188 /**
01189   * @brief  BootCM4 address 0 configuration
01190   * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0
01191   * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
01192   * @retval None
01193   */
01194 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
01195 {
01196   /* Configure CM4 BOOT ADD0 */
01197   MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
01198 }
01199
01200 /**
01201   * @brief  Get BootCM4 address 0
01202   * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0
01203   * @retval Returned the CM4 Boot Address0
01204   */
01205 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
01206 {
01207   /* Get CM4 BOOT ADD0 */
01208   return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
01209 }
01210
01211 /**
01212   * @brief  BootCM4 address 1 configuration
01213   * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1
01214   * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
01215   * @retval None
01216   */
01217 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
01218 {
01219   /* Configure CM4 BOOT ADD1 */
01220   MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
01221 }
01222
01223 /**
01224   * @brief  Get BootCM4 address 1
01225   * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1
01226   * @retval Returned the CM4 Boot Address0
01227   */
01228 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
01229 {
01230   /* Get CM4 BOOT ADD0 */
01231   return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
01232 }
01233 #endif /*DUAL_CORE*/
01234
01235 /**
01236   * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase
01237   * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable
01238   * @retval State of bit (1 or 0).
01239   */
01240 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
01241 {
01242   return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
01243 }
01244
01245 /**
01246   * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase
01247   * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable
01248   * @retval State of bit (1 or 0).
01249   */
01250 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
01251 {
01252   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
01253 }
01254
01255 /**
01256   * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected
01257   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected
01258   * @retval State of bit (1 or 0).
01259   */
01260 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
01261 {
01262   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
01263 }
01264
01265 /**
01266   * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected
01267   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected
01268   * @retval State of bit (1 or 0).
01269   */
01270 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
01271 {
01272   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
01273 }
01274
01275 /**
01276   * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected
01277   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected
01278   * @retval State of bit (1 or 0).
01279   */
01280 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
01281 {
01282   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
01283 }
01284
01285 /**
01286   * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected
01287   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected
01288   * @retval State of bit (1 or 0).
01289   */
01290 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
01291 {
01292   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
01293 }
01294
01295 /**
01296   * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected
01297   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected
01298   * @retval State of bit (1 or 0).
01299   */
01300 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
01301 {
01302   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
01303 }
01304
01305 /**
01306   * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected
01307   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected
01308   * @retval State of bit (1 or 0).
01309   */
01310 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
01311 {
01312   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
01313 }
01314
01315 /**
01316   * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected
01317   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected
01318   * @retval State of bit (1 or 0).
01319   */
01320 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
01321 {
01322   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
01323 }
01324
01325 /**
01326   * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected
01327   * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected
01328   * @retval State of bit (1 or 0).
01329   */
01330 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
01331 {
01332   return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
01333 }
01334
01335 /**
01336   * @brief  Get the protected area start address for Flash bank 1
01337   * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
01338   * @retval Returned the protected area start address for Flash bank 1
01339   */
01340 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
01341 {
01342   return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
01343 }
01344
01345 /**
01346   * @brief  Get the protected area end address for Flash bank 1
01347   * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
01348   * @retval Returned the protected area end address for Flash bank 1
01349   */
01350 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
01351 {
01352   return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
01353 }
01354
01355 /**
01356   * @brief  Get the secured area start address for Flash bank 1
01357   * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
01358   * @retval Returned the secured area start address for Flash bank 1
01359   */
01360 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
01361 {
01362   return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
01363 }
01364
01365 /**
01366   * @brief  Get the secured area end address for Flash bank 1
01367   * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
01368   * @retval Returned the secured area end address for Flash bank 1
01369   */
01370 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
01371 {
01372   return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
01373 }
01374
01375 /**
01376   * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase
01377   * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable
01378   * @retval State of bit (1 or 0).
01379   */
01380 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
01381 {
01382   return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
01383 }
01384
01385 /**
01386   * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase
01387   * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable
01388   * @retval State of bit (1 or 0).
01389   */
01390 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
01391 {
01392   return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
01393 }
01394
01395 /**
01396   * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected
01397   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected
01398   * @retval State of bit (1 or 0).
01399   */
01400 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
01401 {
01402   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
01403 }
01404
01405 /**
01406   * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected
01407   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected
01408   * @retval State of bit (1 or 0).
01409   */
01410 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
01411 {
01412   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
01413 }
01414
01415 /**
01416   * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected
01417   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected
01418   * @retval State of bit (1 or 0).
01419   */
01420 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
01421 {
01422   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
01423 }
01424
01425 /**
01426   * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected
01427   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected
01428   * @retval State of bit (1 or 0).
01429   */
01430 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
01431 {
01432   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
01433 }
01434
01435 /**
01436   * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected
01437   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected
01438   * @retval State of bit (1 or 0).
01439   */
01440 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
01441 {
01442   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
01443 }
01444
01445 /**
01446   * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected
01447   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected
01448   * @retval State of bit (1 or 0).
01449   */
01450 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
01451 {
01452   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
01453 }
01454
01455 /**
01456   * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected
01457   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected
01458   * @retval State of bit (1 or 0).
01459   */
01460 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
01461 {
01462   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
01463 }
01464
01465 /**
01466   * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected
01467   * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected
01468   * @retval State of bit (1 or 0).
01469   */
01470 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
01471 {
01472   return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
01473 }
01474
01475 /**
01476   * @brief  Get the protected area start address for Flash bank 2
01477   * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
01478   * @retval Returned the protected area start address for Flash bank 2
01479   */
01480 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
01481 {
01482   return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
01483 }
01484
01485 /**
01486   * @brief  Get the protected area end address for Flash bank 2
01487   * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
01488   * @retval Returned the protected area end address for Flash bank 2
01489   */
01490 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
01491 {
01492   return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
01493 }
01494
01495 /**
01496   * @brief  Get the secured area start address for Flash bank 2
01497   * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
01498   * @retval Returned the secured area start address for Flash bank 2
01499   */
01500 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
01501 {
01502   return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
01503 }
01504
01505 /**
01506   * @brief  Get the secured area end address for Flash bank 2
01507   * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
01508   * @retval Returned the secured area end address for Flash bank 2
01509   */
01510 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
01511 {
01512   return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
01513 }
01514
01515 /**
01516   * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)
01517   * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode
01518   * @retval Returned value can be one of the following values:
01519   *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
01520   *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
01521   */
01522 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
01523 {
01524   return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
01525 }
01526
01527 #if defined (DUAL_CORE)
01528 /**
01529   * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)
01530   * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode
01531   * @retval Returned value can be one of the following values:
01532   *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
01533   *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
01534   */
01535 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
01536 {
01537   return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
01538 }
01539 #endif /* DUAL_CORE */
01540
01541 /**
01542   * @brief  Indicates the Secure mode status
01543   * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled
01544   * @retval State of bit (1 or 0).
01545   */
01546 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
01547 {
01548   return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
01549 }
01550
01551 /**
01552   * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode
01553   * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset
01554   * @retval State of bit (1 or 0).
01555   */
01556 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
01557 {
01558   return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
01559 }
01560
01561 /**
01562   * @brief  Get the secured DTCM RAM size
01563   * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize
01564   * @retval Returned value can be one of the following values:
01565   *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
01566   *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
01567   *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
01568   *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
01569   */
01570 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
01571 {
01572   return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
01573 }
01574
01575 /**
01576   * @brief  Indicates if a reset is generated when D1 domain enters DStop mode
01577   * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset
01578   * @retval State of bit (1 or 0).
01579   */
01580 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
01581 {
01582   return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
01583 }
01584
01585 #if defined (DUAL_CORE)
01586 /**
01587   * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode
01588   * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
01592 {
01593   return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Indicates if a reset is generated when D2 domain enters DStop mode
01598   * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset
01599   * @retval State of bit (1 or 0).
01600   */
01601 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
01602 {
01603   return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
01604 }
01605 #endif /* DUAL_CORE */
01606
01607 /**
01608   * @brief  Indicates if the independent watchdog is frozen in Standby mode
01609   * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode
01610   * @retval State of bit (1 or 0).
01611   */
01612 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
01613 {
01614   return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
01615 }
01616
01617 /**
01618   * @brief  Indicates if the independent watchdog is frozen in Stop mode
01619   * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode
01620   * @retval State of bit (1 or 0).
01621   */
01622 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
01623 {
01624   return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
01625 }
01626
01627 /**
01628   * @brief  Indicates if the device private key is programmed
01629   * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed
01630   * @retval State of bit (1 or 0).
01631   */
01632 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
01633 {
01634   return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
01635 }
01636
01637 /**
01638   * @brief  Indicates if the Product is working on the full voltage range or not
01639   * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV
01640   * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.
01641   *         When the IOHSLV option bit is reset the Product is working on the
01642   *         full voltage range.
01643   * @retval State of bit (1 or 0).
01644   */
01645 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
01646 {
01647   return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
01648 }
01649 #endif /*SYSCFG_UR0_RDP*/
01650
01651 /**
01652   * @}
01653   */
01654
01655 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
01656   * @{
01657   */
01658
01659 /**
01660   * @brief  Return the device identifier
01661   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
01662   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
01663   */
01664 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
01665 {
01666   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
01667 }
01668
01669 /**
01670   * @brief  Return the device revision identifier
01671   * @note This field indicates the revision of the device.
01672           For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
01673   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
01674   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
01675   */
01676 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
01677 {
01678   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
01679 }
01680
01681 /**
01682   * @brief  Enable D1 Domain/CDomain debug during SLEEP mode
01683   * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode
01684   * @retval None
01685   */
01686 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
01687 {
01688   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
01689 }
01690
01691 /**
01692   * @brief  Disable D1 Domain/CDomain debug during SLEEP mode
01693   * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode
01694   * @retval None
01695   */
01696 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
01697 {
01698   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
01699 }
01700
01701 /**
01702   * @brief  Enable D1 Domain/CDomain debug during STOP mode
01703   * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode
01704   * @retval None
01705   */
01706 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
01707 {
01708   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
01709 }
01710
01711 /**
01712   * @brief  Disable D1 Domain/CDomain debug during STOP mode
01713   * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
01717 {
01718   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
01719 }
01720
01721 /**
01722   * @brief  Enable D1 Domain/CDomain debug during STANDBY mode
01723   * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode
01724   * @retval None
01725   */
01726 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
01727 {
01728   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
01729 }
01730
01731 /**
01732   * @brief  Disable D1 Domain/CDomain debug during STANDBY mode
01733   * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode
01734   * @retval None
01735   */
01736 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
01737 {
01738   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
01739 }
01740
01741 #if defined (DUAL_CORE)
01742 /**
01743   * @brief  Enable D2 Domain debug during SLEEP mode
01744   * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode
01745   * @retval None
01746   */
01747 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
01748 {
01749   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
01750 }
01751
01752 /**
01753   * @brief  Disable D2 Domain debug during SLEEP mode
01754   * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode
01755   * @retval None
01756   */
01757 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
01758 {
01759   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
01760 }
01761
01762 /**
01763   * @brief  Enable D2 Domain debug during STOP mode
01764   * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
01768 {
01769   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
01770 }
01771
01772 /**
01773   * @brief  Disable D2 Domain debug during STOP mode
01774   * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode
01775   * @retval None
01776   */
01777 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
01778 {
01779   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
01780 }
01781
01782 /**
01783   * @brief  Enable D2 Domain debug during STANDBY mode
01784   * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode
01785   * @retval None
01786   */
01787 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
01788 {
01789   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
01790 }
01791
01792 /**
01793   * @brief  Disable D2 Domain debug during STANDBY mode
01794   * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
01798 {
01799   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
01800 }
01801 #endif /* DUAL_CORE */
01802
01803
01804 /**
01805   * @brief  Enable D3 Domain/SRDomain debug during STOP mode
01806   * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode
01807   * @retval None
01808   */
01809 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
01810 {
01811   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
01812 }
01813
01814 /**
01815   * @brief  Disable D3 Domain/SRDomain debug during STOP mode
01816   * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode
01817   * @retval None
01818   */
01819 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
01820 {
01821   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
01822 }
01823
01824 /**
01825   * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode
01826   * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode
01827   * @retval None
01828   */
01829 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
01830 {
01831   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
01832 }
01833
01834 /**
01835   * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode
01836   * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode
01837   * @retval None
01838   */
01839 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
01840 {
01841   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
01842 }
01843
01844 /**
01845   * @brief  Enable the trace port clock
01846   * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock
01847   * @retval None
01848   */
01849 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
01850 {
01851   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
01852 }
01853
01854 /**
01855   * @brief  Disable the trace port clock
01856   * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock
01857   * @retval None
01858   */
01859 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
01860 {
01861   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
01862 }
01863
01864 /**
01865   * @brief  Enable the Domain1/CDomain debug clock enable
01866   * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock
01867   * @retval None
01868   */
01869 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
01870 {
01871   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
01872 }
01873
01874 /**
01875   * @brief  Disable the Domain1/CDomain debug clock enable
01876   * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
01880 {
01881   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
01882 }
01883
01884 /**
01885   * @brief  Enable the Domain3/SRDomain debug clock enable
01886   * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock
01887   * @retval None
01888   */
01889 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
01890 {
01891   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
01892 }
01893
01894 /**
01895   * @brief  Disable the Domain3/SRDomain debug clock enable
01896   * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock
01897   * @retval None
01898   */
01899 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
01900 {
01901   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
01902 }
01903
01904 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U
01905 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN
01906 /**
01907   * @brief  Set the direction of the bi-directional trigger pin TRGIO
01908   * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n
01909   * @param  PinDirection This parameter can be one of the following values:
01910   *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
01911   *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
01915 {
01916   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
01917 }
01918
01919 /**
01920   * @brief  Get the direction of the bi-directional trigger pin TRGIO
01921   * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n
01922   * @retval Returned value can be one of the following values:
01923   *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
01924   *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
01925   */
01926 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
01927 {
01928   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
01929 }
01930
01931 /**
01932   * @brief  Freeze APB1 group1 peripherals
01933   * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01934   *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01935   *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01936   *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01937   *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01938   *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01939   *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01940   *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01941   *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01942   *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01943   *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01944   *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01945   *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01946   * @param  Periphs This parameter can be a combination of the following values:
01947   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01948   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01949   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
01950   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
01951   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01952   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
01953   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
01954   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
01955   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
01956   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01957   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01958   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
01959   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01960   * @retval None
01961   */
01962 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01963 {
01964   SET_BIT(DBGMCU->APB1LFZ1, Periphs);
01965 }
01966
01967 /**
01968   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01969   * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01970   *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01971   *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01972   *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01973   *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01974   *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01975   *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01976   *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01977   *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01978   *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01979   *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01980   *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01981   *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01982   * @param  Periphs This parameter can be a combination of the following values:
01983   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01984   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01985   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
01986   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
01987   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01988   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
01989   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
01990   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
01991   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
01992   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01993   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01994   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
01995   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01996   * @retval None
01997   */
01998 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01999 {
02000   CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
02001 }
02002
02003 /**
02004   * @brief  Freeze APB1 group2 peripherals
02005   * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
02006   * @param  Periphs This parameter can be a combination of the following values:
02007   *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
02008   * @retval None
02009   */
02010 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
02011 {
02012   SET_BIT(DBGMCU->APB1HFZ1, Periphs);
02013 }
02014
02015 /**
02016   * @brief  Unfreeze APB1 group2 peripherals
02017   * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
02018   * @param  Periphs This parameter can be a combination of the following values:
02019   *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
02020   * @retval None
02021   */
02022 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
02023 {
02024   CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
02025 }
02026
02027 /**
02028   * @brief  Freeze APB2 peripherals
02029   * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02030   *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02031   *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02032   *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02033   *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
02034   *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
02035   * @param  Periphs This parameter can be a combination of the following values:
02036   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
02037   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
02038   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
02039   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
02040   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
02041   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
02042   * @retval None
02043   */
02044 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
02045 {
02046   SET_BIT(DBGMCU->APB2FZ1, Periphs);
02047 }
02048
02049 /**
02050   * @brief  Unfreeze APB2 peripherals
02051   * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02052   *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02053   *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02054   *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
02055   *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
02056   *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
02057   * @param  Periphs This parameter can be a combination of the following values:
02058   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
02059   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
02060   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
02061   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
02062   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
02063   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
02064   * @retval None
02065   */
02066 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
02067 {
02068   CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
02069 }
02070
02071 /**
02072   * @brief  Freeze APB3 peripherals
02073   * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n
02074   * @param  Periphs This parameter can be a combination of the following values:
02075   *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
02076   * @retval None
02077   */
02078 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
02079 {
02080   SET_BIT(DBGMCU->APB3FZ1, Periphs);
02081 }
02082
02083 /**
02084   * @brief  Unfreeze APB3 peripherals
02085   * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
02086   * @param  Periphs This parameter can be a combination of the following values:
02087   *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
02091 {
02092   CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
02093 }
02094
02095 /**
02096   * @brief  Freeze APB4 peripherals
02097   * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02098   * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02099   * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02100   * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02101   * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02102   * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02103   * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02104   * @param  Periphs This parameter can be a combination of the following values:
02105   *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
02106   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
02107   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
02108   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
02109   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
02110   *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
02111   *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
02112   * @retval None
02113   */
02114 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
02115 {
02116   SET_BIT(DBGMCU->APB4FZ1, Periphs);
02117 }
02118
02119 /**
02120   * @brief  Unfreeze APB4 peripherals
02121   * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02122   * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02123   * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02124   * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02125   * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02126   * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02127   * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
02128   * @param  Periphs This parameter can be a combination of the following values:
02129   *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
02130   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
02131   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
02132   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
02133   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
02134   *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
02135   *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
02136   * @retval None
02137   */
02138 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
02139 {
02140   CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
02141 }
02142 /**
02143   * @}
02144   */
02145
02146 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
02147   * @{
02148   */
02149
02150 /**
02151   * @brief  Set FLASH Latency
02152   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
02153   * @param  Latency This parameter can be one of the following values:
02154   *         @arg @ref LL_FLASH_LATENCY_0
02155   *         @arg @ref LL_FLASH_LATENCY_1
02156   *         @arg @ref LL_FLASH_LATENCY_2
02157   *         @arg @ref LL_FLASH_LATENCY_3
02158   *         @arg @ref LL_FLASH_LATENCY_4
02159   *         @arg @ref LL_FLASH_LATENCY_5
02160   *         @arg @ref LL_FLASH_LATENCY_6
02161   *         @arg @ref LL_FLASH_LATENCY_7
02162   * @retval None
02163   */
02164 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
02165 {
02166   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
02167 }
02168
02169 /**
02170   * @brief  Get FLASH Latency
02171   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
02172   * @retval Returned value can be one of the following values:
02173   *         @arg @ref LL_FLASH_LATENCY_0
02174   *         @arg @ref LL_FLASH_LATENCY_1
02175   *         @arg @ref LL_FLASH_LATENCY_2
02176   *         @arg @ref LL_FLASH_LATENCY_3
02177   *         @arg @ref LL_FLASH_LATENCY_4
02178   *         @arg @ref LL_FLASH_LATENCY_5
02179   *         @arg @ref LL_FLASH_LATENCY_6
02180   *         @arg @ref LL_FLASH_LATENCY_7
02181   */
02182 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
02183 {
02184   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
02185 }
02186
02187 /**
02188   * @}
02189   */
02190
02191 #if defined(DUAL_CORE)
02192 /** @defgroup SYSTEM_LL_EF_ART ART
02193   * @{
02194   */
02195
02196 /**
02197   * @brief  Enable the Cortex-M4 ART cache.
02198   * @rmtoll ART_CTR    EN   LL_ART_Enable
02199   * @retval None
02200   */
02201 __STATIC_INLINE void LL_ART_Enable(void)
02202 {
02203  SET_BIT(ART->CTR, ART_CTR_EN);
02204 }
02205
02206 /**
02207   * @brief  Disable the Cortex-M4 ART cache.
02208   * @rmtoll ART_CTR    EN   LL_ART_Disable
02209   * @retval None
02210   */
02211 __STATIC_INLINE void LL_ART_Disable(void)
02212 {
02213  CLEAR_BIT(ART->CTR, ART_CTR_EN);
02214 }
02215
02216 /**
02217   * @brief  Check if the Cortex-M4 ART cache is enabled
02218   * @rmtoll ART_CTR   EN    LL_ART_IsEnabled
02219   * @retval State of bit (1 or 0).
02220   */
02221 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
02222 {
02223   return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
02224 }
02225
02226 /**
02227   * @brief  Set the Cortex-M4 ART cache Base Address.
02228   * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress
02229   * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
02230             from which the ART accelerator loads code to the cache.
02231   * @retval None
02232   */
02233 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
02234 {
02235  MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
02236 }
02237
02238 /**
02239   * @brief  Get the Cortex-M4 ART cache Base Address.
02240   * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress
02241   * @retval the Base address of 1 Mbyte address page (cacheable page)
02242             from which the ART accelerator loads code to the cache
02243   */
02244 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
02245 {
02246   return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
02247 }
02248 #endif /* DUAL_CORE */
02249
02250 /**
02251   * @}
02252   */
02253
02254 /**
02255   * @}
02256   */
02257
02258 /**
02259   * @}
02260   */
02261
02262 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
02263
02264 /**
02265   * @}
02266   */
02267
02268 #ifdef __cplusplus
02269 }
02270 #endif
02271
02272 #endif /* __STM32H7xx_LL_SYSTEM_H */
02273
02274 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_tim.c Source File

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stm32h7xx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_tim.h"
00023 #include "stm32h7xx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
00036
00037 /** @addtogroup TIM_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup TIM_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00049                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00050                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00051                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00052                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00053
00054 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00055                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00056                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00057
00058 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00059                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00060                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00061                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00062                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00063                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00064                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00065                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00066                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00067                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00068                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00069                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00070                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
00071                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
00072
00073 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00074                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00075
00076 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00077                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00078
00079 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00080                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00081
00082 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00083                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00084                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00085
00086 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00087                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00088                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00089                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00090
00091 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00092                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00093                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00094                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00095                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00096                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00097                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00098                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00099                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00106                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00107
00108 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00109                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00110                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00111
00112 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00113                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00114                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00115
00116 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00117                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00118
00119 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00120                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00121
00122 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00123                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00124
00125 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00126                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00127                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00128                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00129
00130 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00131                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00132
00133 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00134                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00135
00136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
00137                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
00138                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
00139                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
00140                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
00141                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
00142                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
00143                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
00144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
00145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
00146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
00147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
00148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
00149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
00150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
00151                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
00152
00153 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
00154                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
00155
00156 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
00157                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
00158
00159 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
00160                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
00161                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
00162                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
00163                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
00164                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
00165                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
00166                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
00167                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
00168                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
00169                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
00170                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
00171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
00172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
00173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
00174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
00175
00176 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00177                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00178 /**
00179   * @}
00180   */
00181
00182
00183 /* Private function prototypes -----------------------------------------------*/
00184 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00185   * @{
00186   */
00187 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00188 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00189 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00190 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00192 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00193 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00194 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00195 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00196 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00197 /**
00198   * @}
00199   */
00200
00201 /* Exported functions --------------------------------------------------------*/
00202 /** @addtogroup TIM_LL_Exported_Functions
00203   * @{
00204   */
00205
00206 /** @addtogroup TIM_LL_EF_Init
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Set TIMx registers to their reset values.
00212   * @param  TIMx Timer instance
00213   * @retval An ErrorStatus enumeration value:
00214   *          - SUCCESS: TIMx registers are de-initialized
00215   *          - ERROR: invalid TIMx instance
00216   */
00217 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
00218 {
00219   ErrorStatus result = SUCCESS;
00220
00221   /* Check the parameters */
00222   assert_param(IS_TIM_INSTANCE(TIMx));
00223
00224   if (TIMx == TIM1)
00225   {
00226     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00227     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00228   }
00229 #if defined(TIM2)
00230   else if (TIMx == TIM2)
00231   {
00232     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00233     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00234   }
00235 #endif
00236 #if defined(TIM3)
00237   else if (TIMx == TIM3)
00238   {
00239     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00240     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00241   }
00242 #endif
00243 #if defined(TIM4)
00244   else if (TIMx == TIM4)
00245   {
00246     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00247     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00248   }
00249 #endif
00250 #if defined(TIM5)
00251   else if (TIMx == TIM5)
00252   {
00253     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
00254     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
00255   }
00256 #endif
00257 #if defined(TIM6)
00258   else if (TIMx == TIM6)
00259   {
00260     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00261     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00262   }
00263 #endif
00264 #if defined (TIM7)
00265   else if (TIMx == TIM7)
00266   {
00267     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00268     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00269   }
00270 #endif
00271 #if defined(TIM8)
00272   else if (TIMx == TIM8)
00273   {
00274     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
00275     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
00276   }
00277 #endif
00278 #if defined(TIM12)
00279   else if (TIMx == TIM12)
00280   {
00281     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
00282     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
00283   }
00284 #endif
00285 #if defined(TIM13)
00286   else if (TIMx == TIM13)
00287   {
00288     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
00289     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
00290   }
00291 #endif
00292 #if defined(TIM14)
00293   else if (TIMx == TIM14)
00294   {
00295     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
00296     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
00297   }
00298 #endif
00299 #if defined(TIM15)
00300   else if (TIMx == TIM15)
00301   {
00302     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00303     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00304   }
00305 #endif
00306 #if defined(TIM16)
00307   else if (TIMx == TIM16)
00308   {
00309     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00310     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00311   }
00312 #endif
00313 #if defined(TIM17)
00314   else if (TIMx == TIM17)
00315   {
00316     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00317     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00318   }
00319 #endif
00320   else
00321   {
00322     result = ERROR;
00323   }
00324
00325   return result;
00326 }
00327
00328 /**
00329   * @brief  Set the fields of the time base unit configuration data structure
00330   *         to their default values.
00331   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00332   * @retval None
00333   */
00334 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00335 {
00336   /* Set the default configuration */
00337   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
00338   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00339   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00340   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00341   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
00342 }
00343
00344 /**
00345   * @brief  Configure the TIMx time base unit.
00346   * @param  TIMx Timer Instance
00347   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
00348   * @retval An ErrorStatus enumeration value:
00349   *          - SUCCESS: TIMx registers are de-initialized
00350   *          - ERROR: not applicable
00351   */
00352 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
00353 {
00354   uint32_t tmpcr1;
00355
00356   /* Check the parameters */
00357   assert_param(IS_TIM_INSTANCE(TIMx));
00358   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00359   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00360
00361   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00362
00363   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00364   {
00365     /* Select the Counter Mode */
00366     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00367   }
00368
00369   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00370   {
00371     /* Set the clock division */
00372     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00373   }
00374
00375   /* Write to TIMx CR1 */
00376   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00377
00378   /* Set the Autoreload value */
00379   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00380
00381   /* Set the Prescaler value */
00382   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00383
00384   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00385   {
00386     /* Set the Repetition Counter value */
00387     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00388   }
00389
00390   /* Generate an update event to reload the Prescaler
00391      and the repetition counter value (if applicable) immediately */
00392   LL_TIM_GenerateEvent_UPDATE(TIMx);
00393
00394   return SUCCESS;
00395 }
00396
00397 /**
00398   * @brief  Set the fields of the TIMx output channel configuration data
00399   *         structure to their default values.
00400   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
00401   * @retval None
00402   */
00403 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00404 {
00405   /* Set the default configuration */
00406   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00407   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00408   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00409   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00410   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00411   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00412   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00413   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00414 }
00415
00416 /**
00417   * @brief  Configure the TIMx output channel.
00418   * @param  TIMx Timer Instance
00419   * @param  Channel This parameter can be one of the following values:
00420   *         @arg @ref LL_TIM_CHANNEL_CH1
00421   *         @arg @ref LL_TIM_CHANNEL_CH2
00422   *         @arg @ref LL_TIM_CHANNEL_CH3
00423   *         @arg @ref LL_TIM_CHANNEL_CH4
00424   *         @arg @ref LL_TIM_CHANNEL_CH5
00425   *         @arg @ref LL_TIM_CHANNEL_CH6
00426   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
00427   * @retval An ErrorStatus enumeration value:
00428   *          - SUCCESS: TIMx output channel is initialized
00429   *          - ERROR: TIMx output channel is not initialized
00430   */
00431 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00432 {
00433   ErrorStatus result = ERROR;
00434
00435   switch (Channel)
00436   {
00437     case LL_TIM_CHANNEL_CH1:
00438       result = OC1Config(TIMx, TIM_OC_InitStruct);
00439       break;
00440     case LL_TIM_CHANNEL_CH2:
00441       result = OC2Config(TIMx, TIM_OC_InitStruct);
00442       break;
00443     case LL_TIM_CHANNEL_CH3:
00444       result = OC3Config(TIMx, TIM_OC_InitStruct);
00445       break;
00446     case LL_TIM_CHANNEL_CH4:
00447       result = OC4Config(TIMx, TIM_OC_InitStruct);
00448       break;
00449     case LL_TIM_CHANNEL_CH5:
00450       result = OC5Config(TIMx, TIM_OC_InitStruct);
00451       break;
00452     case LL_TIM_CHANNEL_CH6:
00453       result = OC6Config(TIMx, TIM_OC_InitStruct);
00454       break;
00455     default:
00456       break;
00457   }
00458
00459   return result;
00460 }
00461
00462 /**
00463   * @brief  Set the fields of the TIMx input channel configuration data
00464   *         structure to their default values.
00465   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
00466   * @retval None
00467   */
00468 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00469 {
00470   /* Set the default configuration */
00471   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00472   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00473   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00474   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00475 }
00476
00477 /**
00478   * @brief  Configure the TIMx input channel.
00479   * @param  TIMx Timer Instance
00480   * @param  Channel This parameter can be one of the following values:
00481   *         @arg @ref LL_TIM_CHANNEL_CH1
00482   *         @arg @ref LL_TIM_CHANNEL_CH2
00483   *         @arg @ref LL_TIM_CHANNEL_CH3
00484   *         @arg @ref LL_TIM_CHANNEL_CH4
00485   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
00486   * @retval An ErrorStatus enumeration value:
00487   *          - SUCCESS: TIMx output channel is initialized
00488   *          - ERROR: TIMx output channel is not initialized
00489   */
00490 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00491 {
00492   ErrorStatus result = ERROR;
00493
00494   switch (Channel)
00495   {
00496     case LL_TIM_CHANNEL_CH1:
00497       result = IC1Config(TIMx, TIM_IC_InitStruct);
00498       break;
00499     case LL_TIM_CHANNEL_CH2:
00500       result = IC2Config(TIMx, TIM_IC_InitStruct);
00501       break;
00502     case LL_TIM_CHANNEL_CH3:
00503       result = IC3Config(TIMx, TIM_IC_InitStruct);
00504       break;
00505     case LL_TIM_CHANNEL_CH4:
00506       result = IC4Config(TIMx, TIM_IC_InitStruct);
00507       break;
00508     default:
00509       break;
00510   }
00511
00512   return result;
00513 }
00514
00515 /**
00516   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00517   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
00518   * @retval None
00519   */
00520 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00521 {
00522   /* Set the default configuration */
00523   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00524   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00525   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00526   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00527   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00528   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00529   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00530   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00531   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00532 }
00533
00534 /**
00535   * @brief  Configure the encoder interface of the timer instance.
00536   * @param  TIMx Timer Instance
00537   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
00538   * @retval An ErrorStatus enumeration value:
00539   *          - SUCCESS: TIMx registers are de-initialized
00540   *          - ERROR: not applicable
00541   */
00542 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00543 {
00544   uint32_t tmpccmr1;
00545   uint32_t tmpccer;
00546
00547   /* Check the parameters */
00548   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00549   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00550   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00551   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00552   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00553   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00554   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00555   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00556   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00557   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00558
00559   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00560   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00561
00562   /* Get the TIMx CCMR1 register value */
00563   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00564
00565   /* Get the TIMx CCER register value */
00566   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00567
00568   /* Configure TI1 */
00569   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00570   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00571   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00572   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00573
00574   /* Configure TI2 */
00575   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00576   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00577   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00578   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00579
00580   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00581   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00582   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00583   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00584   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00585
00586   /* Set encoder mode */
00587   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00588
00589   /* Write to TIMx CCMR1 */
00590   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00591
00592   /* Write to TIMx CCER */
00593   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00594
00595   return SUCCESS;
00596 }
00597
00598 /**
00599   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00600   *         structure to their default values.
00601   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
00602   * @retval None
00603   */
00604 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00605 {
00606   /* Set the default configuration */
00607   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00608   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00609   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00610   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00611 }
00612
00613 /**
00614   * @brief  Configure the Hall sensor interface of the timer instance.
00615   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00616   *       to the TI1 input channel
00617   * @note TIMx slave mode controller is configured in reset mode.
00618           Selected internal trigger is TI1F_ED.
00619   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00620   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00621   *       between 2 changes on the inputs. It gives information about motor speed.
00622   * @note Channel 2 is configured in output PWM 2 mode.
00623   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00624   * @note OC2REF is selected as trigger output on TRGO.
00625   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00626   *       when TIMx operates in Hall sensor interface mode.
00627   * @param  TIMx Timer Instance
00628   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
00629   * @retval An ErrorStatus enumeration value:
00630   *          - SUCCESS: TIMx registers are de-initialized
00631   *          - ERROR: not applicable
00632   */
00633 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00634 {
00635   uint32_t tmpcr2;
00636   uint32_t tmpccmr1;
00637   uint32_t tmpccer;
00638   uint32_t tmpsmcr;
00639
00640   /* Check the parameters */
00641   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00642   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00643   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00644   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00645
00646   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00647   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00648
00649   /* Get the TIMx CR2 register value */
00650   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00651
00652   /* Get the TIMx CCMR1 register value */
00653   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00654
00655   /* Get the TIMx CCER register value */
00656   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00657
00658   /* Get the TIMx SMCR register value */
00659   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00660
00661   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00662   tmpcr2 |= TIM_CR2_TI1S;
00663
00664   /* OC2REF signal is used as trigger output (TRGO) */
00665   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00666
00667   /* Configure the slave mode controller */
00668   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00669   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00670   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00671
00672   /* Configure input channel 1 */
00673   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00674   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00675   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00676   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00677
00678   /* Configure input channel 2 */
00679   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00680   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00681
00682   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00683   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00684   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00685   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00686
00687   /* Write to TIMx CR2 */
00688   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00689
00690   /* Write to TIMx SMCR */
00691   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00692
00693   /* Write to TIMx CCMR1 */
00694   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00695
00696   /* Write to TIMx CCER */
00697   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00698
00699   /* Write to TIMx CCR2 */
00700   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00701
00702   return SUCCESS;
00703 }
00704
00705 /**
00706   * @brief  Set the fields of the Break and Dead Time configuration data structure
00707   *         to their default values.
00708   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00709   * @retval None
00710   */
00711 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00712 {
00713   /* Set the default configuration */
00714   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00715   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00716   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00717   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
00718   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00719   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00720   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
00721   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
00722   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
00723   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
00724   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00725 }
00726
00727 /**
00728   * @brief  Configure the Break and Dead Time feature of the timer instance.
00729   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
00730   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
00731   *  can be necessary to configure all of them during the first write access to
00732   *  the TIMx_BDTR register.
00733   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00734   *       a timer instance provides a break input.
00735   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
00736   *       a timer instance provides a second break input.
00737   * @param  TIMx Timer Instance
00738   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00739   * @retval An ErrorStatus enumeration value:
00740   *          - SUCCESS: Break and Dead Time is initialized
00741   *          - ERROR: not applicable
00742   */
00743 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00744 {
00745   uint32_t tmpbdtr = 0;
00746
00747   /* Check the parameters */
00748   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00749   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00750   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00751   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00752   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00753   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00754   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00755
00756   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00757   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00758
00759   /* Set the BDTR bits */
00760   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00761   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00762   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00763   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00764   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00765   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00766   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00767   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
00768   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
00769   {
00770     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
00771     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
00772   }
00773
00774   if (IS_TIM_BKIN2_INSTANCE(TIMx))
00775   {
00776     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
00777     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
00778     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
00779
00780     /* Set the BREAK2 input related BDTR bit-fields */
00781     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
00782     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
00783     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
00784   }
00785
00786   /* Set TIMx_BDTR */
00787   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00788
00789   return SUCCESS;
00790 }
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798
00799 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00800   *  @brief   Private functions
00801   * @{
00802   */
00803 /**
00804   * @brief  Configure the TIMx output channel 1.
00805   * @param  TIMx Timer Instance
00806   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00807   * @retval An ErrorStatus enumeration value:
00808   *          - SUCCESS: TIMx registers are de-initialized
00809   *          - ERROR: not applicable
00810   */
00811 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00812 {
00813   uint32_t tmpccmr1;
00814   uint32_t tmpccer;
00815   uint32_t tmpcr2;
00816
00817   /* Check the parameters */
00818   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00819   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00820   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00821   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00822   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00823   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00824
00825   /* Disable the Channel 1: Reset the CC1E Bit */
00826   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00827
00828   /* Get the TIMx CCER register value */
00829   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00830
00831   /* Get the TIMx CR2 register value */
00832   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00833
00834   /* Get the TIMx CCMR1 register value */
00835   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00836
00837   /* Reset Capture/Compare selection Bits */
00838   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00839
00840   /* Set the Output Compare Mode */
00841   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00842
00843   /* Set the Output Compare Polarity */
00844   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00845
00846   /* Set the Output State */
00847   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00848
00849   if (IS_TIM_BREAK_INSTANCE(TIMx))
00850   {
00851     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00852     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00853
00854     /* Set the complementary output Polarity */
00855     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00856
00857     /* Set the complementary output State */
00858     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00859
00860     /* Set the Output Idle state */
00861     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00862
00863     /* Set the complementary output Idle state */
00864     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00865   }
00866
00867   /* Write to TIMx CR2 */
00868   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00869
00870   /* Write to TIMx CCMR1 */
00871   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00872
00873   /* Set the Capture Compare Register value */
00874   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00875
00876   /* Write to TIMx CCER */
00877   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00878
00879   return SUCCESS;
00880 }
00881
00882 /**
00883   * @brief  Configure the TIMx output channel 2.
00884   * @param  TIMx Timer Instance
00885   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00886   * @retval An ErrorStatus enumeration value:
00887   *          - SUCCESS: TIMx registers are de-initialized
00888   *          - ERROR: not applicable
00889   */
00890 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00891 {
00892   uint32_t tmpccmr1;
00893   uint32_t tmpccer;
00894   uint32_t tmpcr2;
00895
00896   /* Check the parameters */
00897   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00898   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00899   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00900   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00901   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00902   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00903
00904   /* Disable the Channel 2: Reset the CC2E Bit */
00905   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00906
00907   /* Get the TIMx CCER register value */
00908   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00909
00910   /* Get the TIMx CR2 register value */
00911   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00912
00913   /* Get the TIMx CCMR1 register value */
00914   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00915
00916   /* Reset Capture/Compare selection Bits */
00917   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00918
00919   /* Select the Output Compare Mode */
00920   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00921
00922   /* Set the Output Compare Polarity */
00923   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00924
00925   /* Set the Output State */
00926   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00927
00928   if (IS_TIM_BREAK_INSTANCE(TIMx))
00929   {
00930     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00931     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00932
00933     /* Set the complementary output Polarity */
00934     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00935
00936     /* Set the complementary output State */
00937     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00938
00939     /* Set the Output Idle state */
00940     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00941
00942     /* Set the complementary output Idle state */
00943     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00944   }
00945
00946   /* Write to TIMx CR2 */
00947   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00948
00949   /* Write to TIMx CCMR1 */
00950   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00951
00952   /* Set the Capture Compare Register value */
00953   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00954
00955   /* Write to TIMx CCER */
00956   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00957
00958   return SUCCESS;
00959 }
00960
00961 /**
00962   * @brief  Configure the TIMx output channel 3.
00963   * @param  TIMx Timer Instance
00964   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00965   * @retval An ErrorStatus enumeration value:
00966   *          - SUCCESS: TIMx registers are de-initialized
00967   *          - ERROR: not applicable
00968   */
00969 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00970 {
00971   uint32_t tmpccmr2;
00972   uint32_t tmpccer;
00973   uint32_t tmpcr2;
00974
00975   /* Check the parameters */
00976   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00977   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00978   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00979   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00980   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00981   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00982
00983   /* Disable the Channel 3: Reset the CC3E Bit */
00984   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00985
00986   /* Get the TIMx CCER register value */
00987   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00988
00989   /* Get the TIMx CR2 register value */
00990   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00991
00992   /* Get the TIMx CCMR2 register value */
00993   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00994
00995   /* Reset Capture/Compare selection Bits */
00996   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00997
00998   /* Select the Output Compare Mode */
00999   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
01000
01001   /* Set the Output Compare Polarity */
01002   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
01003
01004   /* Set the Output State */
01005   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
01006
01007   if (IS_TIM_BREAK_INSTANCE(TIMx))
01008   {
01009     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01010     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01011
01012     /* Set the complementary output Polarity */
01013     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
01014
01015     /* Set the complementary output State */
01016     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
01017
01018     /* Set the Output Idle state */
01019     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
01020
01021     /* Set the complementary output Idle state */
01022     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
01023   }
01024
01025   /* Write to TIMx CR2 */
01026   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01027
01028   /* Write to TIMx CCMR2 */
01029   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01030
01031   /* Set the Capture Compare Register value */
01032   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
01033
01034   /* Write to TIMx CCER */
01035   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01036
01037   return SUCCESS;
01038 }
01039
01040 /**
01041   * @brief  Configure the TIMx output channel 4.
01042   * @param  TIMx Timer Instance
01043   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
01044   * @retval An ErrorStatus enumeration value:
01045   *          - SUCCESS: TIMx registers are de-initialized
01046   *          - ERROR: not applicable
01047   */
01048 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01049 {
01050   uint32_t tmpccmr2;
01051   uint32_t tmpccer;
01052   uint32_t tmpcr2;
01053
01054   /* Check the parameters */
01055   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01056   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01057   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01058   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01059   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01060   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01061
01062   /* Disable the Channel 4: Reset the CC4E Bit */
01063   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
01064
01065   /* Get the TIMx CCER register value */
01066   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01067
01068   /* Get the TIMx CR2 register value */
01069   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
01070
01071   /* Get the TIMx CCMR2 register value */
01072   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01073
01074   /* Reset Capture/Compare selection Bits */
01075   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01076
01077   /* Select the Output Compare Mode */
01078   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01079
01080   /* Set the Output Compare Polarity */
01081   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01082
01083   /* Set the Output State */
01084   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01085
01086   if (IS_TIM_BREAK_INSTANCE(TIMx))
01087   {
01088     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01089     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01090
01091     /* Set the Output Idle state */
01092     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01093   }
01094
01095   /* Write to TIMx CR2 */
01096   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01097
01098   /* Write to TIMx CCMR2 */
01099   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01100
01101   /* Set the Capture Compare Register value */
01102   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01103
01104   /* Write to TIMx CCER */
01105   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01106
01107   return SUCCESS;
01108 }
01109
01110 /**
01111   * @brief  Configure the TIMx output channel 5.
01112   * @param  TIMx Timer Instance
01113   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
01114   * @retval An ErrorStatus enumeration value:
01115   *          - SUCCESS: TIMx registers are de-initialized
01116   *          - ERROR: not applicable
01117   */
01118 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01119 {
01120   uint32_t tmpccmr3;
01121   uint32_t tmpccer;
01122
01123   /* Check the parameters */
01124   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
01125   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01126   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01127   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01128   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01129   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01130
01131   /* Disable the Channel 5: Reset the CC5E Bit */
01132   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
01133
01134   /* Get the TIMx CCER register value */
01135   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01136
01137   /* Get the TIMx CCMR3 register value */
01138   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01139
01140   /* Select the Output Compare Mode */
01141   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
01142
01143   /* Set the Output Compare Polarity */
01144   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
01145
01146   /* Set the Output State */
01147   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
01148
01149   if (IS_TIM_BREAK_INSTANCE(TIMx))
01150   {
01151     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01152     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01153
01154     /* Set the Output Idle state */
01155     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01156
01157   }
01158
01159   /* Write to TIMx CCMR3 */
01160   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01161
01162   /* Set the Capture Compare Register value */
01163   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01164
01165   /* Write to TIMx CCER */
01166   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01167
01168   return SUCCESS;
01169 }
01170
01171 /**
01172   * @brief  Configure the TIMx output channel 6.
01173   * @param  TIMx Timer Instance
01174   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01175   * @retval An ErrorStatus enumeration value:
01176   *          - SUCCESS: TIMx registers are de-initialized
01177   *          - ERROR: not applicable
01178   */
01179 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01180 {
01181   uint32_t tmpccmr3;
01182   uint32_t tmpccer;
01183
01184   /* Check the parameters */
01185   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01186   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01187   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01188   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01189   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01190   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01191
01192   /* Disable the Channel 5: Reset the CC6E Bit */
01193   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01194
01195   /* Get the TIMx CCER register value */
01196   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01197
01198   /* Get the TIMx CCMR3 register value */
01199   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01200
01201   /* Select the Output Compare Mode */
01202   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01203
01204   /* Set the Output Compare Polarity */
01205   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01206
01207   /* Set the Output State */
01208   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01209
01210   if (IS_TIM_BREAK_INSTANCE(TIMx))
01211   {
01212     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01213     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01214
01215     /* Set the Output Idle state */
01216     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01217   }
01218
01219   /* Write to TIMx CCMR3 */
01220   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01221
01222   /* Set the Capture Compare Register value */
01223   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01224
01225   /* Write to TIMx CCER */
01226   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01227
01228   return SUCCESS;
01229 }
01230
01231 /**
01232   * @brief  Configure the TIMx input channel 1.
01233   * @param  TIMx Timer Instance
01234   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01235   * @retval An ErrorStatus enumeration value:
01236   *          - SUCCESS: TIMx registers are de-initialized
01237   *          - ERROR: not applicable
01238   */
01239 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01240 {
01241   /* Check the parameters */
01242   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01243   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01244   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01245   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01246   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01247
01248   /* Disable the Channel 1: Reset the CC1E Bit */
01249   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01250
01251   /* Select the Input and set the filter and the prescaler value */
01252   MODIFY_REG(TIMx->CCMR1,
01253              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01254              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01255
01256   /* Select the Polarity and set the CC1E Bit */
01257   MODIFY_REG(TIMx->CCER,
01258              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01259              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01260
01261   return SUCCESS;
01262 }
01263
01264 /**
01265   * @brief  Configure the TIMx input channel 2.
01266   * @param  TIMx Timer Instance
01267   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01268   * @retval An ErrorStatus enumeration value:
01269   *          - SUCCESS: TIMx registers are de-initialized
01270   *          - ERROR: not applicable
01271   */
01272 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01273 {
01274   /* Check the parameters */
01275   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01276   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01277   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01278   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01279   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01280
01281   /* Disable the Channel 2: Reset the CC2E Bit */
01282   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01283
01284   /* Select the Input and set the filter and the prescaler value */
01285   MODIFY_REG(TIMx->CCMR1,
01286              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01287              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01288
01289   /* Select the Polarity and set the CC2E Bit */
01290   MODIFY_REG(TIMx->CCER,
01291              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01292              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01293
01294   return SUCCESS;
01295 }
01296
01297 /**
01298   * @brief  Configure the TIMx input channel 3.
01299   * @param  TIMx Timer Instance
01300   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01301   * @retval An ErrorStatus enumeration value:
01302   *          - SUCCESS: TIMx registers are de-initialized
01303   *          - ERROR: not applicable
01304   */
01305 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01306 {
01307   /* Check the parameters */
01308   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01309   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01310   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01311   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01312   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01313
01314   /* Disable the Channel 3: Reset the CC3E Bit */
01315   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01316
01317   /* Select the Input and set the filter and the prescaler value */
01318   MODIFY_REG(TIMx->CCMR2,
01319              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01320              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01321
01322   /* Select the Polarity and set the CC3E Bit */
01323   MODIFY_REG(TIMx->CCER,
01324              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01325              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01326
01327   return SUCCESS;
01328 }
01329
01330 /**
01331   * @brief  Configure the TIMx input channel 4.
01332   * @param  TIMx Timer Instance
01333   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01334   * @retval An ErrorStatus enumeration value:
01335   *          - SUCCESS: TIMx registers are de-initialized
01336   *          - ERROR: not applicable
01337   */
01338 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01339 {
01340   /* Check the parameters */
01341   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01342   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01343   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01344   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01345   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01346
01347   /* Disable the Channel 4: Reset the CC4E Bit */
01348   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01349
01350   /* Select the Input and set the filter and the prescaler value */
01351   MODIFY_REG(TIMx->CCMR2,
01352              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01353              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01354
01355   /* Select the Polarity and set the CC2E Bit */
01356   MODIFY_REG(TIMx->CCER,
01357              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01358              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01359
01360   return SUCCESS;
01361 }
01362
01363
01364 /**
01365   * @}
01366   */
01367
01368 /**
01369   * @}
01370   */
01371
01372 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
01373
01374 /**
01375   * @}
01376   */
01377
01378 #endif /* USE_FULL_LL_DRIVER */
01379
01380 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_tim.h Source File

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stm32h7xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_LL_TIM_H
00022 #define __STM32H7xx_LL_TIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
00036
00037 /** @defgroup TIM_LL TIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00044   * @{
00045   */
00046 static const uint8_t OFFSET_TAB_CCMRx[] =
00047 {
00048   0x00U,   /* 0: TIMx_CH1  */
00049   0x00U,   /* 1: TIMx_CH1N */
00050   0x00U,   /* 2: TIMx_CH2  */
00051   0x00U,   /* 3: TIMx_CH2N */
00052   0x04U,   /* 4: TIMx_CH3  */
00053   0x04U,   /* 5: TIMx_CH3N */
00054   0x04U,   /* 6: TIMx_CH4  */
00055   0x3CU,   /* 7: TIMx_CH5  */
00056   0x3CU    /* 8: TIMx_CH6  */
00057 };
00058
00059 static const uint8_t SHIFT_TAB_OCxx[] =
00060 {
00061   0U,            /* 0: OC1M, OC1FE, OC1PE */
00062   0U,            /* 1: - NA */
00063   8U,            /* 2: OC2M, OC2FE, OC2PE */
00064   0U,            /* 3: - NA */
00065   0U,            /* 4: OC3M, OC3FE, OC3PE */
00066   0U,            /* 5: - NA */
00067   8U,            /* 6: OC4M, OC4FE, OC4PE */
00068   0U,            /* 7: OC5M, OC5FE, OC5PE */
00069   8U             /* 8: OC6M, OC6FE, OC6PE */
00070 };
00071
00072 static const uint8_t SHIFT_TAB_ICxx[] =
00073 {
00074   0U,            /* 0: CC1S, IC1PSC, IC1F */
00075   0U,            /* 1: - NA */
00076   8U,            /* 2: CC2S, IC2PSC, IC2F */
00077   0U,            /* 3: - NA */
00078   0U,            /* 4: CC3S, IC3PSC, IC3F */
00079   0U,            /* 5: - NA */
00080   8U,            /* 6: CC4S, IC4PSC, IC4F */
00081   0U,            /* 7: - NA */
00082   0U             /* 8: - NA */
00083 };
00084
00085 static const uint8_t SHIFT_TAB_CCxP[] =
00086 {
00087   0U,            /* 0: CC1P */
00088   2U,            /* 1: CC1NP */
00089   4U,            /* 2: CC2P */
00090   6U,            /* 3: CC2NP */
00091   8U,            /* 4: CC3P */
00092   10U,           /* 5: CC3NP */
00093   12U,           /* 6: CC4P */
00094   16U,           /* 7: CC5P */
00095   20U            /* 8: CC6P */
00096 };
00097
00098 static const uint8_t SHIFT_TAB_OISx[] =
00099 {
00100   0U,            /* 0: OIS1 */
00101   1U,            /* 1: OIS1N */
00102   2U,            /* 2: OIS2 */
00103   3U,            /* 3: OIS2N */
00104   4U,            /* 4: OIS3 */
00105   5U,            /* 5: OIS3N */
00106   6U,            /* 6: OIS4 */
00107   8U,            /* 7: OIS5 */
00108   10U            /* 8: OIS6 */
00109 };
00110 /**
00111   * @}
00112   */
00113
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00116   * @{
00117   */
00118
00119 #if   defined(TIM_BREAK_INPUT_SUPPORT)
00120 /* Defines used for the bit position in the register and perform offsets */
00121 #define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
00122
00123 /* Generic bit definitions for TIMx_AF1 register */
00124 #define TIMx_AF1_BKINE     TIM1_AF1_BKINE     /*!< BRK BKIN input enable */
00125 #define TIMx_AF1_BKCOMP1E  TIM1_AF1_BKCMP1E   /*!< BRK COMP1 enable */
00126 #define TIMx_AF1_BKCOMP2E  TIM1_AF1_BKCMP2E   /*!< BRK COMP2 enable */
00127 #define TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */
00128 #define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
00129 #define TIMx_AF1_BKCOMP1P  TIM1_AF1_BKCMP1P   /*!< BRK COMP1 input polarity */
00130 #define TIMx_AF1_BKCOMP2P  TIM1_AF1_BKCMP2P   /*!< BRK COMP2 input polarity */
00131 #define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
00132
00133 /* Generic bit definitions for TIMx_AF2 register */
00134 #define TIMx_AF2_BK2INE    TIM1_AF2_BK2INE      /*!< BRK2 BKIN2 input enable */
00135 #define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E    /*!< BRK2 COMP1 enable */
00136 #define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E    /*!< BRK2 COMP2 enable */
00137 #define TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */
00138 #define TIMx_AF2_BK2INP    TIM1_AF2_BK2INP      /*!< BRK2 BKIN2 input polarity */
00139 #define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P    /*!< BRK2 COMP1 input polarity */
00140 #define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P    /*!< BRK2 COMP2 input polarity */
00141 #endif /* TIM_BREAK_INPUT_SUPPORT */
00142
00143
00144 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00145 #define DT_DELAY_1 ((uint8_t)0x7F)
00146 #define DT_DELAY_2 ((uint8_t)0x3F)
00147 #define DT_DELAY_3 ((uint8_t)0x1F)
00148 #define DT_DELAY_4 ((uint8_t)0x1F)
00149
00150 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00151 #define DT_RANGE_1 ((uint8_t)0x00)
00152 #define DT_RANGE_2 ((uint8_t)0x80)
00153 #define DT_RANGE_3 ((uint8_t)0xC0)
00154 #define DT_RANGE_4 ((uint8_t)0xE0)
00155
00156
00157 /**
00158   * @}
00159   */
00160
00161 /* Private macros ------------------------------------------------------------*/
00162 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00163   * @{
00164   */
00165 /** @brief  Convert channel id into channel index.
00166   * @param  __CHANNEL__ This parameter can be one of the following values:
00167   *         @arg @ref LL_TIM_CHANNEL_CH1
00168   *         @arg @ref LL_TIM_CHANNEL_CH1N
00169   *         @arg @ref LL_TIM_CHANNEL_CH2
00170   *         @arg @ref LL_TIM_CHANNEL_CH2N
00171   *         @arg @ref LL_TIM_CHANNEL_CH3
00172   *         @arg @ref LL_TIM_CHANNEL_CH3N
00173   *         @arg @ref LL_TIM_CHANNEL_CH4
00174   *         @arg @ref LL_TIM_CHANNEL_CH5
00175   *         @arg @ref LL_TIM_CHANNEL_CH6
00176   * @retval none
00177   */
00178 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00179   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00180    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00181    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00182    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00183    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00184    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00185    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00186    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00187
00188 /** @brief  Calculate the deadtime sampling period(in ps).
00189   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00190   * @param  __CKD__ This parameter can be one of the following values:
00191   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00192   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00193   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00194   * @retval none
00195   */
00196 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00197   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00198    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00199    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00200 /**
00201   * @}
00202   */
00203
00204
00205 /* Exported types ------------------------------------------------------------*/
00206 #if defined(USE_FULL_LL_DRIVER)
00207 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00208   * @{
00209   */
00210
00211 /**
00212   * @brief  TIM Time Base configuration structure definition.
00213   */
00214 typedef struct
00215 {
00216   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00217                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00218
00219                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00220
00221   uint32_t CounterMode;       /*!< Specifies the counter mode.
00222                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00223
00224                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00225
00226   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00227                                    Auto-Reload Register at the next update event.
00228                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00229                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00230
00231                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00232
00233   uint32_t ClockDivision;     /*!< Specifies the clock division.
00234                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00235
00236                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00237
00238   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00239                                    reaches zero, an update event is generated and counting restarts
00240                                    from the RCR value (N).
00241                                    This means in PWM mode that (N+1) corresponds to:
00242                                       - the number of PWM periods in edge-aligned mode
00243                                       - the number of half PWM period in center-aligned mode
00244                                    This parameter must be a number between 0x00 and 0xFF.
00245
00246                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00247 } LL_TIM_InitTypeDef;
00248
00249 /**
00250   * @brief  TIM Output Compare configuration structure definition.
00251   */
00252 typedef struct
00253 {
00254   uint32_t OCMode;        /*!< Specifies the output mode.
00255                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00256
00257                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00258
00259   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00260                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00261
00262                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00263
00264   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00265                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00266
00267                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00268
00269   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00270                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00271
00272                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00273
00274   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00275                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00276
00277                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00278
00279   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00280                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00281
00282                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00283
00284
00285   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00286                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00287
00288                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00289
00290   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00291                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00292
00293                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00294 } LL_TIM_OC_InitTypeDef;
00295
00296 /**
00297   * @brief  TIM Input Capture configuration structure definition.
00298   */
00299
00300 typedef struct
00301 {
00302
00303   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00304                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00305
00306                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00307
00308   uint32_t ICActiveInput; /*!< Specifies the input.
00309                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00310
00311                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00312
00313   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00314                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00315
00316                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00317
00318   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00319                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00320
00321                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00322 } LL_TIM_IC_InitTypeDef;
00323
00324
00325 /**
00326   * @brief  TIM Encoder interface configuration structure definition.
00327   */
00328 typedef struct
00329 {
00330   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00331                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00332
00333                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00334
00335   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00336                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00337
00338                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00339
00340   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00341                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00342
00343                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00344
00345   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00346                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00347
00348                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00349
00350   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00351                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00352
00353                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00354
00355   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00356                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00357
00358                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00359
00360   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00361                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00362
00363                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00364
00365   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00366                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00367
00368                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00369
00370   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00371                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00372
00373                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00374
00375 } LL_TIM_ENCODER_InitTypeDef;
00376
00377 /**
00378   * @brief  TIM Hall sensor interface configuration structure definition.
00379   */
00380 typedef struct
00381 {
00382
00383   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00384                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00385
00386                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00387
00388   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00389                                     Prescaler must be set to get a maximum counter period longer than the
00390                                     time interval between 2 consecutive changes on the Hall inputs.
00391                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00392
00393                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00394
00395   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00396                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00397
00398                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00399
00400   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00401                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00402                                     a change occurs on the Hall inputs.
00403                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00404
00405                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00406 } LL_TIM_HALLSENSOR_InitTypeDef;
00407
00408 /**
00409   * @brief  BDTR (Break and Dead Time) structure definition
00410   */
00411 typedef struct
00412 {
00413   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00414                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00415
00416                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00417
00418                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00419
00420   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00421                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00422
00423                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00424
00425                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00426
00427   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00428                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00429
00430                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
00431                                             has been written, their content is frozen until the next reset.*/
00432
00433   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00434                                       switching-on of the outputs.
00435                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00436
00437                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
00438
00439                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
00440
00441   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00442                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00443
00444                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00445
00446                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00447
00448   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00449                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00450
00451                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00452
00453                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00454
00455   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00456                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00457
00458                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00459
00460                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00461
00462   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00463                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00464
00465                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00466
00467                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00468
00469   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00470                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00471
00472                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00473
00474                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00475
00476   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00477                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00478
00479                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00480
00481                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00482
00483   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00484                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00485
00486                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00487
00488                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00489 } LL_TIM_BDTR_InitTypeDef;
00490
00491 /**
00492   * @}
00493   */
00494 #endif /* USE_FULL_LL_DRIVER */
00495
00496 /* Exported constants --------------------------------------------------------*/
00497 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00498   * @{
00499   */
00500
00501 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00502   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00503   * @{
00504   */
00505 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00506 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00507 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00508 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00509 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00510 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00511 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00512 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00513 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00514 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00515 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00516 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00517 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00518 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00519 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00520 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00521 /**
00522   * @}
00523   */
00524
00525 #if defined(USE_FULL_LL_DRIVER)
00526 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00527   * @{
00528   */
00529 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00530 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00536   * @{
00537   */
00538 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00539 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00545   * @{
00546   */
00547 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00548 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00549 /**
00550   * @}
00551   */
00552 #endif /* USE_FULL_LL_DRIVER */
00553
00554 /** @defgroup TIM_LL_EC_IT IT Defines
00555   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00556   * @{
00557   */
00558 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00559 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00560 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00561 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00562 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00563 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00564 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00565 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00571   * @{
00572   */
00573 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00574 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00580   * @{
00581   */
00582 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
00583 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00589   * @{
00590   */
00591 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00592 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00593 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00594 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00595 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00601   * @{
00602   */
00603 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00604 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00605 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00611   * @{
00612   */
00613 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00614 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00620   * @{
00621   */
00622 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00623 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00629   * @{
00630   */
00631 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00632 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00633 /**
00634   * @}
00635   */
00636
00637 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00638   * @{
00639   */
00640 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00641 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00642 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00643 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup TIM_LL_EC_CHANNEL Channel
00649   * @{
00650   */
00651 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00652 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00653 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00654 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00655 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00656 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00657 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00658 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00659 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00660 /**
00661   * @}
00662   */
00663
00664 #if defined(USE_FULL_LL_DRIVER)
00665 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00666   * @{
00667   */
00668 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00669 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00670 /**
00671   * @}
00672   */
00673 #endif /* USE_FULL_LL_DRIVER */
00674
00675 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00676   * @{
00677   */
00678 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00679 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00680 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00681 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00682 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
00683 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00684 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00685 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00686 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00687 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00688 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00689 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00690 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00691 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00697   * @{
00698   */
00699 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00700 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00706   * @{
00707   */
00708 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00709 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00715   * @{
00716   */
00717 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00718 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00719 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00720 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00726   * @{
00727   */
00728 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00729 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00730 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00736   * @{
00737   */
00738 #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00739 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00740 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00741 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00747   * @{
00748   */
00749 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00750 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00751 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00752 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00753 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00754 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00755 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00756 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00757 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00758 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00759 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00760 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00761 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00762 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00763 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00764 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00770   * @{
00771   */
00772 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00773 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00774 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00780   * @{
00781   */
00782 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00783 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
00784 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00790   * @{
00791   */
00792 #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00793 #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00794 #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00800   * @{
00801   */
00802 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00803 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00804 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00805 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00806 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00807 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00808 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00809 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00815   * @{
00816   */
00817 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00818 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00819 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00820 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00821 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00822 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00823 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00824 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00825 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00826 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00827 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00828 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00829 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00830 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00831 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00832 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00833 /**
00834   * @}
00835   */
00836
00837 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00838   * @{
00839   */
00840 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00841 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00842 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00843 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00844 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00845 /**
00846   * @}
00847   */
00848
00849 /** @defgroup TIM_LL_EC_TS Trigger Selection
00850   * @{
00851   */
00852 #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00853 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00854 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00855 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00856 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00857 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00858 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00859 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
00860 #define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
00861 #define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
00862 #define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
00863 #define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
00864 #define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
00865 #define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
00866 #define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
00867 #define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
00868 #define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
00869 #define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00875   * @{
00876   */
00877 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00878 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00879 /**
00880   * @}
00881   */
00882
00883 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00884   * @{
00885   */
00886 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00887 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00888 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00889 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00895   * @{
00896   */
00897 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00898 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00899 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00900 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00901 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00902 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00903 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00904 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00905 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00906 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00907 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00908 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00909 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00910 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00911 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00912 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00913 /**
00914   * @}
00915   */
00916
00917 #define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
00918 #define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
00919 #define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
00920 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
00921 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
00922 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
00923 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
00924 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
00925 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
00926
00927 #define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
00928 #define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
00929 #define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
00930 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
00931 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
00932 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
00933 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
00934 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
00935 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
00936
00937 #define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM2_ETR is connected to GPIO */
00938 #define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /* !< TIM2_ETR is connected to COMP1 OUT */
00939 #define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /* !< TIM2_ETR is connected to COMP2 OUT */
00940 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to RCC LSE */
00941 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /* !< TIM2_ETR is connected to SAI1 FS_A */
00942 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to SAI1 FS_B */
00943
00944 #define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM3_ETR is connected to GPIO */
00945 #define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /* !< TIM3_ETR is connected to COMP1 OUT */
00946
00947 #define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM5_ETR is connected to GPIO */
00948 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI2 FS_A */
00949 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI2 FS_B */
00950 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI4 FS_A */
00951 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI4 FS_B */
00952
00953 #define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /* !< TIM23_ETR is connected to GPIO */
00954 #define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /* !< TIM23_ETR is connected to COMP1 OUT */
00955 #define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /* !< TIM23_ETR is connected to COMP2 OUT */
00956
00957 #define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /* !< TIM24_ETR is connected to GPIO */
00958 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /* !< TIM24_ETR is connected to SAI4 FS_A */
00959 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /* !< TIM24_ETR is connected to SAI4 FS_B */
00960 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /* !< TIM24_ETR is connected to SAI1 FS_A */
00961 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /* !< TIM24_ETR is connected to SAI1 FS_B */
00962
00963 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00964   * @{
00965   */
00966 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
00967 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00968 /**
00969   * @}
00970   */
00971
00972 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
00973   * @{
00974   */
00975 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
00976 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
00977 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
00978 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
00979 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
00980 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
00981 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
00982 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
00983 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
00984 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
00985 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
00986 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
00987 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
00988 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
00989 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
00990 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
00991 /**
00992   * @}
00993   */
00994
00995 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00996   * @{
00997   */
00998 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
00999 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
01000 /**
01001   * @}
01002   */
01003
01004 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
01005   * @{
01006   */
01007 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
01008 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
01009 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
01010 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
01011 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
01012 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
01013 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
01014 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
01015 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
01016 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
01017 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
01018 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
01019 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
01020 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
01021 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
01022 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup TIM_LL_EC_OSSI OSSI
01028   * @{
01029   */
01030 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01031 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
01032 /**
01033   * @}
01034   */
01035
01036 /** @defgroup TIM_LL_EC_OSSR OSSR
01037   * @{
01038   */
01039 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01040 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
01041 /**
01042   * @}
01043   */
01044
01045 #if   defined(TIM_BREAK_INPUT_SUPPORT)
01046 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
01047   * @{
01048   */
01049 #define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
01050 #define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
01051 /**
01052   * @}
01053   */
01054
01055 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
01056   * @{
01057   */
01058 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
01059 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
01060 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
01061 #define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
01062 /**
01063   * @}
01064   */
01065
01066 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
01067   * @{
01068   */
01069 #define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
01070 #define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
01071 /**
01072   * @}
01073   */
01074 #endif /* TIM_BREAK_INPUT_SUPPORT */
01075
01076 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01077   * @{
01078   */
01079 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01080 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01081 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01082 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01083 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01084 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01085 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01086 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01087 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01088 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01089 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01090 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01091 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01092 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01093 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01094 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01095 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01096 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01097 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01098 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01099 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01100 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
01101 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
01102 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
01103 #endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
01104 #define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
01105 /**
01106   * @}
01107   */
01108
01109 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01110   * @{
01111   */
01112 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01113 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01114 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01115 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01116 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01117 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01118 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01119 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01120 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01121 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01122 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01123 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01124 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01125 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01126 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01127 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01128 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01129 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01130 /**
01131   * @}
01132   */
01133
01134 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
01135   * @{
01136   */
01137 #define TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM1 input 1 is connected to GPIO */
01138 #define TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1 input 1 is connected to COMP1 OUT */
01139 /**
01140   * @}
01141   */
01142
01143 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
01144   * @{
01145   */
01146 #define TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM8 input 1 is connected to GPIO */
01147 #define TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8 input 1 is connected to COMP2 OUT */
01148 /**
01149   * @}
01150   */
01151
01152 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
01153   * @{
01154   */
01155 #define TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /* !< TIM2 input 4 is connected to GPIO */
01156 #define TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2 input 4 is connected to COMP1 OUT */
01157 #define TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2 input 4 is connected to COMP2 OUT */
01158 #define TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
01159 /**
01160   * @}
01161   */
01162
01163 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
01164   * @{
01165   */
01166 #define TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM3 input 1 is connected to GPIO */
01167 #define TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3 input 1 is connected to COMP1 OUT */
01168 #define TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3 input 1 is connected to COMP2 OUT */
01169 #define TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
01175   * @{
01176   */
01177 #define TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM5 input 1 is connected to GPIO */
01178 #define TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5 input 1 is connected to CAN TMP */
01179 #define TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5 input 1 is connected to CAN RTP */
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
01185   * @{
01186   */
01187 #define TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM12 input 1 is connected to GPIO */
01188 #define TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 input 1 is connected to SPDIF FS */
01189 /**
01190   * @}
01191   */
01192
01193 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
01194   * @{
01195   */
01196 #define TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 1 is connected to GPIO */
01197 #define TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15 input 1 is connected to TIM2 CH1 */
01198 #define TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15 input 1 is connected to TIM3 CH1 */
01199 #define TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
01200 #define TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15 input 1 is connected to RCC LSE  */
01201 #define TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI  */
01202 #define TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
01203 /**
01204   * @}
01205   */
01206
01207 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
01208   * @{
01209   */
01210 #define TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 2 is connected to GPIO */
01211 #define TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15 input 2 is connected to TIM2 CH2 */
01212 #define TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15 input 2 is connected to TIM3 CH2 */
01213 #define TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
01214 /**
01215   * @}
01216   */
01217
01218 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
01219   * @{
01220   */
01221 #define TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM16 input 1 is connected to GPIO */
01222 #define TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 input 1 is connected to RCC LSI */
01223 #define TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 input 1 is connected to RCC LSE */
01224 #define TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
01225 /**
01226   * @}
01227   */
01228
01229 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
01230   * @{
01231   */
01232 #define TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM17 input 1 is connected to GPIO */
01233 #define TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 input 1 is connected to SPDIF FS */
01234 #define TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
01235 #define TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
01236 /**
01237   * @}
01238   */
01239
01240 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
01241   * @{
01242   */
01243 #define TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /* !< TIM23 input 4 is connected to GPIO */
01244 #define TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23 input 4 is connected to COMP1 OUT */
01245 #define TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23 input 4 is connected to COMP2 OUT */
01246 #define TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
01247 /**
01248   * @}
01249   */
01250
01251 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
01252   * @{
01253   */
01254 #define TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM24 input 1 is connected to GPIO */
01255 #define TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24 input 1 is connected to CAN TMP  */
01256 #define TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24 input 1 is connected to CAN RTP  */
01257 #define TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
01258
01259 #if defined(TIM_BREAK_INPUT_SUPPORT)
01260 /** Legacy definitions for compatibility purpose
01261 @cond 0
01262   */
01263 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01264 /**
01265 @endcond
01266   */
01267 #endif /* TIM_BREAK_INPUT_SUPPORT */
01268 /**
01269   * @}
01270   */
01271
01272 /**
01273   * @}
01274   */
01275
01276 /* Exported macro ------------------------------------------------------------*/
01277 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01278   * @{
01279   */
01280
01281 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01282   * @{
01283   */
01284 /**
01285   * @brief  Write a value in TIM register.
01286   * @param  __INSTANCE__ TIM Instance
01287   * @param  __REG__ Register to be written
01288   * @param  __VALUE__ Value to be written in the register
01289   * @retval None
01290   */
01291 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
01292
01293 /**
01294   * @brief  Read a value in TIM register.
01295   * @param  __INSTANCE__ TIM Instance
01296   * @param  __REG__ Register to be read
01297   * @retval Register value
01298   */
01299 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
01300 /**
01301   * @}
01302   */
01303
01304 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01305   * @{
01306   */
01307
01308 /**
01309   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01310   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01311   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01312   *        to TIMx_CNT register bit 31)
01313   * @param  __CNT__ Counter value
01314   * @retval UIF status bit
01315   */
01316 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01317   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01318
01319 /**
01320   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01321   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01322   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01323   * @param  __CKD__ This parameter can be one of the following values:
01324   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01325   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01326   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01327   * @param  __DT__ deadtime duration (in ns)
01328   * @retval DTG[0:7]
01329   */
01330 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01331   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
01332     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
01333     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
01334     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
01335     0U)
01336
01337 /**
01338   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01339   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01340   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01341   * @param  __CNTCLK__ counter clock frequency (in Hz)
01342   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01343   */
01344 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01345   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
01346
01347 /**
01348   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01349   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01350   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01351   * @param  __PSC__ prescaler
01352   * @param  __FREQ__ output signal frequency (in Hz)
01353   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01354   */
01355 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01356   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
01357
01358 /**
01359   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
01360   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01361   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01362   * @param  __PSC__ prescaler
01363   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01364   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01365   */
01366 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01367   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01368               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01369
01370 /**
01371   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
01372   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01373   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01374   * @param  __PSC__ prescaler
01375   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01376   * @param  __PULSE__ pulse duration (in us)
01377   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01378   */
01379 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01380   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01381               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01382
01383 /**
01384   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01385   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01386   * @param  __ICPSC__ This parameter can be one of the following values:
01387   *         @arg @ref LL_TIM_ICPSC_DIV1
01388   *         @arg @ref LL_TIM_ICPSC_DIV2
01389   *         @arg @ref LL_TIM_ICPSC_DIV4
01390   *         @arg @ref LL_TIM_ICPSC_DIV8
01391   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01392   */
01393 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01394   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01395
01396
01397 /**
01398   * @}
01399   */
01400
01401
01402 /**
01403   * @}
01404   */
01405
01406 /* Exported functions --------------------------------------------------------*/
01407 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01408   * @{
01409   */
01410
01411 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01412   * @{
01413   */
01414 /**
01415   * @brief  Enable timer counter.
01416   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01417   * @param  TIMx Timer instance
01418   * @retval None
01419   */
01420 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01421 {
01422   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01423 }
01424
01425 /**
01426   * @brief  Disable timer counter.
01427   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01428   * @param  TIMx Timer instance
01429   * @retval None
01430   */
01431 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01432 {
01433   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01434 }
01435
01436 /**
01437   * @brief  Indicates whether the timer counter is enabled.
01438   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01439   * @param  TIMx Timer instance
01440   * @retval State of bit (1 or 0).
01441   */
01442 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
01443 {
01444   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
01445 }
01446
01447 /**
01448   * @brief  Enable update event generation.
01449   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01450   * @param  TIMx Timer instance
01451   * @retval None
01452   */
01453 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01454 {
01455   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01456 }
01457
01458 /**
01459   * @brief  Disable update event generation.
01460   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01461   * @param  TIMx Timer instance
01462   * @retval None
01463   */
01464 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01465 {
01466   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01467 }
01468
01469 /**
01470   * @brief  Indicates whether update event generation is enabled.
01471   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01472   * @param  TIMx Timer instance
01473   * @retval Inverted state of bit (0 or 1).
01474   */
01475 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
01476 {
01477   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
01478 }
01479
01480 /**
01481   * @brief  Set update event source
01482   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01483   *       generate an update interrupt or DMA request if enabled:
01484   *        - Counter overflow/underflow
01485   *        - Setting the UG bit
01486   *        - Update generation through the slave mode controller
01487   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01488   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01489   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01490   * @param  TIMx Timer instance
01491   * @param  UpdateSource This parameter can be one of the following values:
01492   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01493   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01494   * @retval None
01495   */
01496 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01497 {
01498   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01499 }
01500
01501 /**
01502   * @brief  Get actual event update source
01503   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01504   * @param  TIMx Timer instance
01505   * @retval Returned value can be one of the following values:
01506   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01507   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01508   */
01509 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
01510 {
01511   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01512 }
01513
01514 /**
01515   * @brief  Set one pulse mode (one shot v.s. repetitive).
01516   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01517   * @param  TIMx Timer instance
01518   * @param  OnePulseMode This parameter can be one of the following values:
01519   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01520   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01521   * @retval None
01522   */
01523 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01524 {
01525   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01526 }
01527
01528 /**
01529   * @brief  Get actual one pulse mode.
01530   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01531   * @param  TIMx Timer instance
01532   * @retval Returned value can be one of the following values:
01533   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01534   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01535   */
01536 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
01537 {
01538   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01539 }
01540
01541 /**
01542   * @brief  Set the timer counter counting mode.
01543   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01544   *       check whether or not the counter mode selection feature is supported
01545   *       by a timer instance.
01546   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01547   *       requires a timer reset to avoid unexpected direction
01548   *       due to DIR bit readonly in center aligned mode.
01549   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01550   *         CR1          CMS           LL_TIM_SetCounterMode
01551   * @param  TIMx Timer instance
01552   * @param  CounterMode This parameter can be one of the following values:
01553   *         @arg @ref LL_TIM_COUNTERMODE_UP
01554   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01555   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01556   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01557   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01561 {
01562   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
01563 }
01564
01565 /**
01566   * @brief  Get actual counter mode.
01567   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01568   *       check whether or not the counter mode selection feature is supported
01569   *       by a timer instance.
01570   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01571   *         CR1          CMS           LL_TIM_GetCounterMode
01572   * @param  TIMx Timer instance
01573   * @retval Returned value can be one of the following values:
01574   *         @arg @ref LL_TIM_COUNTERMODE_UP
01575   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01576   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01577   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01578   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01579   */
01580 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
01581 {
01582   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01583 }
01584
01585 /**
01586   * @brief  Enable auto-reload (ARR) preload.
01587   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01588   * @param  TIMx Timer instance
01589   * @retval None
01590   */
01591 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01592 {
01593   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01594 }
01595
01596 /**
01597   * @brief  Disable auto-reload (ARR) preload.
01598   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01599   * @param  TIMx Timer instance
01600   * @retval None
01601   */
01602 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01603 {
01604   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01605 }
01606
01607 /**
01608   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01609   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01610   * @param  TIMx Timer instance
01611   * @retval State of bit (1 or 0).
01612   */
01613 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
01614 {
01615   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
01616 }
01617
01618 /**
01619   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01620   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01621   *       whether or not the clock division feature is supported by the timer
01622   *       instance.
01623   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01624   * @param  TIMx Timer instance
01625   * @param  ClockDivision This parameter can be one of the following values:
01626   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01627   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01628   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01629   * @retval None
01630   */
01631 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01632 {
01633   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01634 }
01635
01636 /**
01637   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01638   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01639   *       whether or not the clock division feature is supported by the timer
01640   *       instance.
01641   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01642   * @param  TIMx Timer instance
01643   * @retval Returned value can be one of the following values:
01644   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01645   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01646   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01647   */
01648 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
01649 {
01650   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01651 }
01652
01653 /**
01654   * @brief  Set the counter value.
01655   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01656   *       whether or not a timer instance supports a 32 bits counter.
01657   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01658   * @param  TIMx Timer instance
01659   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01660   * @retval None
01661   */
01662 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01663 {
01664   WRITE_REG(TIMx->CNT, Counter);
01665 }
01666
01667 /**
01668   * @brief  Get the counter value.
01669   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01670   *       whether or not a timer instance supports a 32 bits counter.
01671   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01672   * @param  TIMx Timer instance
01673   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01674   */
01675 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
01676 {
01677   return (uint32_t)(READ_REG(TIMx->CNT));
01678 }
01679
01680 /**
01681   * @brief  Get the current direction of the counter
01682   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01683   * @param  TIMx Timer instance
01684   * @retval Returned value can be one of the following values:
01685   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01686   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01687   */
01688 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
01689 {
01690   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01691 }
01692
01693 /**
01694   * @brief  Set the prescaler value.
01695   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01696   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01697   *       prescaler ratio is taken into account at the next update event.
01698   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01699   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01700   * @param  TIMx Timer instance
01701   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01702   * @retval None
01703   */
01704 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01705 {
01706   WRITE_REG(TIMx->PSC, Prescaler);
01707 }
01708
01709 /**
01710   * @brief  Get the prescaler value.
01711   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01712   * @param  TIMx Timer instance
01713   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01714   */
01715 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
01716 {
01717   return (uint32_t)(READ_REG(TIMx->PSC));
01718 }
01719
01720 /**
01721   * @brief  Set the auto-reload value.
01722   * @note The counter is blocked while the auto-reload value is null.
01723   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01724   *       whether or not a timer instance supports a 32 bits counter.
01725   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01726   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01727   * @param  TIMx Timer instance
01728   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01729   * @retval None
01730   */
01731 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01732 {
01733   WRITE_REG(TIMx->ARR, AutoReload);
01734 }
01735
01736 /**
01737   * @brief  Get the auto-reload value.
01738   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01739   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01740   *       whether or not a timer instance supports a 32 bits counter.
01741   * @param  TIMx Timer instance
01742   * @retval Auto-reload value
01743   */
01744 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
01745 {
01746   return (uint32_t)(READ_REG(TIMx->ARR));
01747 }
01748
01749 /**
01750   * @brief  Set the repetition counter value.
01751   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01752   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01753   *       whether or not a timer instance supports a repetition counter.
01754   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01755   * @param  TIMx Timer instance
01756   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01757   * @retval None
01758   */
01759 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01760 {
01761   WRITE_REG(TIMx->RCR, RepetitionCounter);
01762 }
01763
01764 /**
01765   * @brief  Get the repetition counter value.
01766   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01767   *       whether or not a timer instance supports a repetition counter.
01768   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01769   * @param  TIMx Timer instance
01770   * @retval Repetition counter value
01771   */
01772 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
01773 {
01774   return (uint32_t)(READ_REG(TIMx->RCR));
01775 }
01776
01777 /**
01778   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01779   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01780   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01781   * @param  TIMx Timer instance
01782   * @retval None
01783   */
01784 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
01785 {
01786   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01787 }
01788
01789 /**
01790   * @brief  Disable update interrupt flag (UIF) remapping.
01791   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01792   * @param  TIMx Timer instance
01793   * @retval None
01794   */
01795 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
01796 {
01797   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01798 }
01799
01800 /**
01801   * @}
01802   */
01803
01804 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01805   * @{
01806   */
01807 /**
01808   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01809   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01810   *       they are updated only when a commutation event (COM) occurs.
01811   * @note Only on channels that have a complementary output.
01812   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01813   *       whether or not a timer instance is able to generate a commutation event.
01814   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01815   * @param  TIMx Timer instance
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01819 {
01820   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01821 }
01822
01823 /**
01824   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01825   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01826   *       whether or not a timer instance is able to generate a commutation event.
01827   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01828   * @param  TIMx Timer instance
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
01832 {
01833   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01834 }
01835
01836 /**
01837   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01838   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01839   *       whether or not a timer instance is able to generate a commutation event.
01840   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01841   * @param  TIMx Timer instance
01842   * @param  CCUpdateSource This parameter can be one of the following values:
01843   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01844   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01845   * @retval None
01846   */
01847 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
01848 {
01849   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01850 }
01851
01852 /**
01853   * @brief  Set the trigger of the capture/compare DMA request.
01854   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01855   * @param  TIMx Timer instance
01856   * @param  DMAReqTrigger This parameter can be one of the following values:
01857   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01858   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01859   * @retval None
01860   */
01861 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
01862 {
01863   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01864 }
01865
01866 /**
01867   * @brief  Get actual trigger of the capture/compare DMA request.
01868   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01869   * @param  TIMx Timer instance
01870   * @retval Returned value can be one of the following values:
01871   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01872   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01873   */
01874 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
01875 {
01876   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01877 }
01878
01879 /**
01880   * @brief  Set the lock level to freeze the
01881   *         configuration of several capture/compare parameters.
01882   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01883   *       the lock mechanism is supported by a timer instance.
01884   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01885   * @param  TIMx Timer instance
01886   * @param  LockLevel This parameter can be one of the following values:
01887   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01888   *         @arg @ref LL_TIM_LOCKLEVEL_1
01889   *         @arg @ref LL_TIM_LOCKLEVEL_2
01890   *         @arg @ref LL_TIM_LOCKLEVEL_3
01891   * @retval None
01892   */
01893 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
01894 {
01895   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01896 }
01897
01898 /**
01899   * @brief  Enable capture/compare channels.
01900   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01901   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01902   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01903   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01904   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01905   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01906   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01907   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01908   *         CCER         CC6E          LL_TIM_CC_EnableChannel
01909   * @param  TIMx Timer instance
01910   * @param  Channels This parameter can be a combination of the following values:
01911   *         @arg @ref LL_TIM_CHANNEL_CH1
01912   *         @arg @ref LL_TIM_CHANNEL_CH1N
01913   *         @arg @ref LL_TIM_CHANNEL_CH2
01914   *         @arg @ref LL_TIM_CHANNEL_CH2N
01915   *         @arg @ref LL_TIM_CHANNEL_CH3
01916   *         @arg @ref LL_TIM_CHANNEL_CH3N
01917   *         @arg @ref LL_TIM_CHANNEL_CH4
01918   *         @arg @ref LL_TIM_CHANNEL_CH5
01919   *         @arg @ref LL_TIM_CHANNEL_CH6
01920   * @retval None
01921   */
01922 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01923 {
01924   SET_BIT(TIMx->CCER, Channels);
01925 }
01926
01927 /**
01928   * @brief  Disable capture/compare channels.
01929   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01930   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01931   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01932   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01933   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01934   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01935   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
01936   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
01937   *         CCER         CC6E          LL_TIM_CC_DisableChannel
01938   * @param  TIMx Timer instance
01939   * @param  Channels This parameter can be a combination of the following values:
01940   *         @arg @ref LL_TIM_CHANNEL_CH1
01941   *         @arg @ref LL_TIM_CHANNEL_CH1N
01942   *         @arg @ref LL_TIM_CHANNEL_CH2
01943   *         @arg @ref LL_TIM_CHANNEL_CH2N
01944   *         @arg @ref LL_TIM_CHANNEL_CH3
01945   *         @arg @ref LL_TIM_CHANNEL_CH3N
01946   *         @arg @ref LL_TIM_CHANNEL_CH4
01947   *         @arg @ref LL_TIM_CHANNEL_CH5
01948   *         @arg @ref LL_TIM_CHANNEL_CH6
01949   * @retval None
01950   */
01951 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01952 {
01953   CLEAR_BIT(TIMx->CCER, Channels);
01954 }
01955
01956 /**
01957   * @brief  Indicate whether channel(s) is(are) enabled.
01958   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01959   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01960   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01961   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01962   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01963   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01964   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
01965   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
01966   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
01967   * @param  TIMx Timer instance
01968   * @param  Channels This parameter can be a combination of the following values:
01969   *         @arg @ref LL_TIM_CHANNEL_CH1
01970   *         @arg @ref LL_TIM_CHANNEL_CH1N
01971   *         @arg @ref LL_TIM_CHANNEL_CH2
01972   *         @arg @ref LL_TIM_CHANNEL_CH2N
01973   *         @arg @ref LL_TIM_CHANNEL_CH3
01974   *         @arg @ref LL_TIM_CHANNEL_CH3N
01975   *         @arg @ref LL_TIM_CHANNEL_CH4
01976   *         @arg @ref LL_TIM_CHANNEL_CH5
01977   *         @arg @ref LL_TIM_CHANNEL_CH6
01978   * @retval State of bit (1 or 0).
01979   */
01980 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01981 {
01982   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
01983 }
01984
01985 /**
01986   * @}
01987   */
01988
01989 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01990   * @{
01991   */
01992 /**
01993   * @brief  Configure an output channel.
01994   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01995   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01996   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01997   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01998   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01999   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
02000   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
02001   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
02002   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
02003   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
02004   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
02005   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
02006   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
02007   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
02008   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
02009   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
02010   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
02011   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
02012   * @param  TIMx Timer instance
02013   * @param  Channel This parameter can be one of the following values:
02014   *         @arg @ref LL_TIM_CHANNEL_CH1
02015   *         @arg @ref LL_TIM_CHANNEL_CH2
02016   *         @arg @ref LL_TIM_CHANNEL_CH3
02017   *         @arg @ref LL_TIM_CHANNEL_CH4
02018   *         @arg @ref LL_TIM_CHANNEL_CH5
02019   *         @arg @ref LL_TIM_CHANNEL_CH6
02020   * @param  Configuration This parameter must be a combination of all the following values:
02021   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
02022   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02026 {
02027   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02028   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02029   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
02030   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
02031              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
02032   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
02033              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
02034 }
02035
02036 /**
02037   * @brief  Define the behavior of the output reference signal OCxREF from which
02038   *         OCx and OCxN (when relevant) are derived.
02039   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
02040   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
02041   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
02042   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
02043   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02044   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02045   * @param  TIMx Timer instance
02046   * @param  Channel This parameter can be one of the following values:
02047   *         @arg @ref LL_TIM_CHANNEL_CH1
02048   *         @arg @ref LL_TIM_CHANNEL_CH2
02049   *         @arg @ref LL_TIM_CHANNEL_CH3
02050   *         @arg @ref LL_TIM_CHANNEL_CH4
02051   *         @arg @ref LL_TIM_CHANNEL_CH5
02052   *         @arg @ref LL_TIM_CHANNEL_CH6
02053   * @param  Mode This parameter can be one of the following values:
02054   *         @arg @ref LL_TIM_OCMODE_FROZEN
02055   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02056   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02057   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02058   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02059   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02060   *         @arg @ref LL_TIM_OCMODE_PWM1
02061   *         @arg @ref LL_TIM_OCMODE_PWM2
02062   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02063   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02064   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02065   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02066   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02067   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02068   * @retval None
02069   */
02070 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
02071 {
02072   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02073   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02074   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
02075 }
02076
02077 /**
02078   * @brief  Get the output compare mode of an output channel.
02079   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
02080   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
02081   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
02082   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
02083   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02084   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02085   * @param  TIMx Timer instance
02086   * @param  Channel This parameter can be one of the following values:
02087   *         @arg @ref LL_TIM_CHANNEL_CH1
02088   *         @arg @ref LL_TIM_CHANNEL_CH2
02089   *         @arg @ref LL_TIM_CHANNEL_CH3
02090   *         @arg @ref LL_TIM_CHANNEL_CH4
02091   *         @arg @ref LL_TIM_CHANNEL_CH5
02092   *         @arg @ref LL_TIM_CHANNEL_CH6
02093   * @retval Returned value can be one of the following values:
02094   *         @arg @ref LL_TIM_OCMODE_FROZEN
02095   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02096   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02097   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02098   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02099   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02100   *         @arg @ref LL_TIM_OCMODE_PWM1
02101   *         @arg @ref LL_TIM_OCMODE_PWM2
02102   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02103   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02104   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02105   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02106   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02107   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02108   */
02109 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
02110 {
02111   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02112   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02113   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02114 }
02115
02116 /**
02117   * @brief  Set the polarity of an output channel.
02118   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02119   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02120   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02121   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02122   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02123   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02124   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02125   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02126   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02127   * @param  TIMx Timer instance
02128   * @param  Channel This parameter can be one of the following values:
02129   *         @arg @ref LL_TIM_CHANNEL_CH1
02130   *         @arg @ref LL_TIM_CHANNEL_CH1N
02131   *         @arg @ref LL_TIM_CHANNEL_CH2
02132   *         @arg @ref LL_TIM_CHANNEL_CH2N
02133   *         @arg @ref LL_TIM_CHANNEL_CH3
02134   *         @arg @ref LL_TIM_CHANNEL_CH3N
02135   *         @arg @ref LL_TIM_CHANNEL_CH4
02136   *         @arg @ref LL_TIM_CHANNEL_CH5
02137   *         @arg @ref LL_TIM_CHANNEL_CH6
02138   * @param  Polarity This parameter can be one of the following values:
02139   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02140   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02141   * @retval None
02142   */
02143 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
02144 {
02145   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02146   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02147 }
02148
02149 /**
02150   * @brief  Get the polarity of an output channel.
02151   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02152   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02153   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02154   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02155   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02156   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02157   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02158   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02159   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02160   * @param  TIMx Timer instance
02161   * @param  Channel This parameter can be one of the following values:
02162   *         @arg @ref LL_TIM_CHANNEL_CH1
02163   *         @arg @ref LL_TIM_CHANNEL_CH1N
02164   *         @arg @ref LL_TIM_CHANNEL_CH2
02165   *         @arg @ref LL_TIM_CHANNEL_CH2N
02166   *         @arg @ref LL_TIM_CHANNEL_CH3
02167   *         @arg @ref LL_TIM_CHANNEL_CH3N
02168   *         @arg @ref LL_TIM_CHANNEL_CH4
02169   *         @arg @ref LL_TIM_CHANNEL_CH5
02170   *         @arg @ref LL_TIM_CHANNEL_CH6
02171   * @retval Returned value can be one of the following values:
02172   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02173   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02174   */
02175 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02176 {
02177   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02178   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02179 }
02180
02181 /**
02182   * @brief  Set the IDLE state of an output channel
02183   * @note This function is significant only for the timer instances
02184   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
02185   *       can be used to check whether or not a timer instance provides
02186   *       a break input.
02187   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02188   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02189   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02190   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02191   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02192   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02193   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02194   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02195   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02196   * @param  TIMx Timer instance
02197   * @param  Channel This parameter can be one of the following values:
02198   *         @arg @ref LL_TIM_CHANNEL_CH1
02199   *         @arg @ref LL_TIM_CHANNEL_CH1N
02200   *         @arg @ref LL_TIM_CHANNEL_CH2
02201   *         @arg @ref LL_TIM_CHANNEL_CH2N
02202   *         @arg @ref LL_TIM_CHANNEL_CH3
02203   *         @arg @ref LL_TIM_CHANNEL_CH3N
02204   *         @arg @ref LL_TIM_CHANNEL_CH4
02205   *         @arg @ref LL_TIM_CHANNEL_CH5
02206   *         @arg @ref LL_TIM_CHANNEL_CH6
02207   * @param  IdleState This parameter can be one of the following values:
02208   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02209   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02210   * @retval None
02211   */
02212 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02213 {
02214   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02215   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02216 }
02217
02218 /**
02219   * @brief  Get the IDLE state of an output channel
02220   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02221   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02222   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02223   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02224   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02225   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02226   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02227   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02228   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02229   * @param  TIMx Timer instance
02230   * @param  Channel This parameter can be one of the following values:
02231   *         @arg @ref LL_TIM_CHANNEL_CH1
02232   *         @arg @ref LL_TIM_CHANNEL_CH1N
02233   *         @arg @ref LL_TIM_CHANNEL_CH2
02234   *         @arg @ref LL_TIM_CHANNEL_CH2N
02235   *         @arg @ref LL_TIM_CHANNEL_CH3
02236   *         @arg @ref LL_TIM_CHANNEL_CH3N
02237   *         @arg @ref LL_TIM_CHANNEL_CH4
02238   *         @arg @ref LL_TIM_CHANNEL_CH5
02239   *         @arg @ref LL_TIM_CHANNEL_CH6
02240   * @retval Returned value can be one of the following values:
02241   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02242   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02243   */
02244 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
02245 {
02246   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02247   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02248 }
02249
02250 /**
02251   * @brief  Enable fast mode for the output channel.
02252   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02253   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02254   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02255   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02256   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02257   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02258   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02259   * @param  TIMx Timer instance
02260   * @param  Channel This parameter can be one of the following values:
02261   *         @arg @ref LL_TIM_CHANNEL_CH1
02262   *         @arg @ref LL_TIM_CHANNEL_CH2
02263   *         @arg @ref LL_TIM_CHANNEL_CH3
02264   *         @arg @ref LL_TIM_CHANNEL_CH4
02265   *         @arg @ref LL_TIM_CHANNEL_CH5
02266   *         @arg @ref LL_TIM_CHANNEL_CH6
02267   * @retval None
02268   */
02269 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02270 {
02271   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02272   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02273   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02274
02275 }
02276
02277 /**
02278   * @brief  Disable fast mode for the output channel.
02279   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02280   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02281   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02282   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02283   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02284   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02285   * @param  TIMx Timer instance
02286   * @param  Channel This parameter can be one of the following values:
02287   *         @arg @ref LL_TIM_CHANNEL_CH1
02288   *         @arg @ref LL_TIM_CHANNEL_CH2
02289   *         @arg @ref LL_TIM_CHANNEL_CH3
02290   *         @arg @ref LL_TIM_CHANNEL_CH4
02291   *         @arg @ref LL_TIM_CHANNEL_CH5
02292   *         @arg @ref LL_TIM_CHANNEL_CH6
02293   * @retval None
02294   */
02295 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02296 {
02297   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02298   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02299   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02300
02301 }
02302
02303 /**
02304   * @brief  Indicates whether fast mode is enabled for the output channel.
02305   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02306   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02307   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02308   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02309   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02310   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02311   * @param  TIMx Timer instance
02312   * @param  Channel This parameter can be one of the following values:
02313   *         @arg @ref LL_TIM_CHANNEL_CH1
02314   *         @arg @ref LL_TIM_CHANNEL_CH2
02315   *         @arg @ref LL_TIM_CHANNEL_CH3
02316   *         @arg @ref LL_TIM_CHANNEL_CH4
02317   *         @arg @ref LL_TIM_CHANNEL_CH5
02318   *         @arg @ref LL_TIM_CHANNEL_CH6
02319   * @retval State of bit (1 or 0).
02320   */
02321 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
02322 {
02323   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02324   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02325   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02326   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02327 }
02328
02329 /**
02330   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02331   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02332   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02333   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02334   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02335   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02336   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02337   * @param  TIMx Timer instance
02338   * @param  Channel This parameter can be one of the following values:
02339   *         @arg @ref LL_TIM_CHANNEL_CH1
02340   *         @arg @ref LL_TIM_CHANNEL_CH2
02341   *         @arg @ref LL_TIM_CHANNEL_CH3
02342   *         @arg @ref LL_TIM_CHANNEL_CH4
02343   *         @arg @ref LL_TIM_CHANNEL_CH5
02344   *         @arg @ref LL_TIM_CHANNEL_CH6
02345   * @retval None
02346   */
02347 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02348 {
02349   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02350   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02351   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02352 }
02353
02354 /**
02355   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02356   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02357   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02358   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02359   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02360   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02361   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02362   * @param  TIMx Timer instance
02363   * @param  Channel This parameter can be one of the following values:
02364   *         @arg @ref LL_TIM_CHANNEL_CH1
02365   *         @arg @ref LL_TIM_CHANNEL_CH2
02366   *         @arg @ref LL_TIM_CHANNEL_CH3
02367   *         @arg @ref LL_TIM_CHANNEL_CH4
02368   *         @arg @ref LL_TIM_CHANNEL_CH5
02369   *         @arg @ref LL_TIM_CHANNEL_CH6
02370   * @retval None
02371   */
02372 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02373 {
02374   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02375   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02376   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02377 }
02378
02379 /**
02380   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02381   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02382   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02383   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02384   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02385   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02386   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02387   * @param  TIMx Timer instance
02388   * @param  Channel This parameter can be one of the following values:
02389   *         @arg @ref LL_TIM_CHANNEL_CH1
02390   *         @arg @ref LL_TIM_CHANNEL_CH2
02391   *         @arg @ref LL_TIM_CHANNEL_CH3
02392   *         @arg @ref LL_TIM_CHANNEL_CH4
02393   *         @arg @ref LL_TIM_CHANNEL_CH5
02394   *         @arg @ref LL_TIM_CHANNEL_CH6
02395   * @retval State of bit (1 or 0).
02396   */
02397 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
02398 {
02399   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02400   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02401   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02402   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02403 }
02404
02405 /**
02406   * @brief  Enable clearing the output channel on an external event.
02407   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02408   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02409   *       or not a timer instance can clear the OCxREF signal on an external event.
02410   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02411   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02412   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02413   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02414   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02415   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02416   * @param  TIMx Timer instance
02417   * @param  Channel This parameter can be one of the following values:
02418   *         @arg @ref LL_TIM_CHANNEL_CH1
02419   *         @arg @ref LL_TIM_CHANNEL_CH2
02420   *         @arg @ref LL_TIM_CHANNEL_CH3
02421   *         @arg @ref LL_TIM_CHANNEL_CH4
02422   *         @arg @ref LL_TIM_CHANNEL_CH5
02423   *         @arg @ref LL_TIM_CHANNEL_CH6
02424   * @retval None
02425   */
02426 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02427 {
02428   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02429   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02430   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02431 }
02432
02433 /**
02434   * @brief  Disable clearing the output channel on an external event.
02435   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02436   *       or not a timer instance can clear the OCxREF signal on an external event.
02437   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02438   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02439   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02440   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02441   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02442   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02443   * @param  TIMx Timer instance
02444   * @param  Channel This parameter can be one of the following values:
02445   *         @arg @ref LL_TIM_CHANNEL_CH1
02446   *         @arg @ref LL_TIM_CHANNEL_CH2
02447   *         @arg @ref LL_TIM_CHANNEL_CH3
02448   *         @arg @ref LL_TIM_CHANNEL_CH4
02449   *         @arg @ref LL_TIM_CHANNEL_CH5
02450   *         @arg @ref LL_TIM_CHANNEL_CH6
02451   * @retval None
02452   */
02453 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02454 {
02455   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02456   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02457   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02458 }
02459
02460 /**
02461   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02462   * @note This function enables clearing the output channel on an external event.
02463   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02464   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02465   *       or not a timer instance can clear the OCxREF signal on an external event.
02466   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02467   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02468   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02469   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02470   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02471   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02472   * @param  TIMx Timer instance
02473   * @param  Channel This parameter can be one of the following values:
02474   *         @arg @ref LL_TIM_CHANNEL_CH1
02475   *         @arg @ref LL_TIM_CHANNEL_CH2
02476   *         @arg @ref LL_TIM_CHANNEL_CH3
02477   *         @arg @ref LL_TIM_CHANNEL_CH4
02478   *         @arg @ref LL_TIM_CHANNEL_CH5
02479   *         @arg @ref LL_TIM_CHANNEL_CH6
02480   * @retval State of bit (1 or 0).
02481   */
02482 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
02483 {
02484   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02485   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02486   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02487   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02488 }
02489
02490 /**
02491   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
02492   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02493   *       dead-time insertion feature is supported by a timer instance.
02494   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02495   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02496   * @param  TIMx Timer instance
02497   * @param  DeadTime between Min_Data=0 and Max_Data=255
02498   * @retval None
02499   */
02500 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
02501 {
02502   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02503 }
02504
02505 /**
02506   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02507   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02508   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02509   *       whether or not a timer instance supports a 32 bits counter.
02510   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02511   *       output channel 1 is supported by a timer instance.
02512   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02513   * @param  TIMx Timer instance
02514   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02515   * @retval None
02516   */
02517 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
02518 {
02519   WRITE_REG(TIMx->CCR1, CompareValue);
02520 }
02521
02522 /**
02523   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02524   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02525   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02526   *       whether or not a timer instance supports a 32 bits counter.
02527   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02528   *       output channel 2 is supported by a timer instance.
02529   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02530   * @param  TIMx Timer instance
02531   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02532   * @retval None
02533   */
02534 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02535 {
02536   WRITE_REG(TIMx->CCR2, CompareValue);
02537 }
02538
02539 /**
02540   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02541   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02542   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02543   *       whether or not a timer instance supports a 32 bits counter.
02544   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02545   *       output channel is supported by a timer instance.
02546   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02547   * @param  TIMx Timer instance
02548   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02549   * @retval None
02550   */
02551 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02552 {
02553   WRITE_REG(TIMx->CCR3, CompareValue);
02554 }
02555
02556 /**
02557   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02558   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02559   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02560   *       whether or not a timer instance supports a 32 bits counter.
02561   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02562   *       output channel 4 is supported by a timer instance.
02563   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02564   * @param  TIMx Timer instance
02565   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02569 {
02570   WRITE_REG(TIMx->CCR4, CompareValue);
02571 }
02572
02573 /**
02574   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02575   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02576   *       output channel 5 is supported by a timer instance.
02577   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02578   * @param  TIMx Timer instance
02579   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02580   * @retval None
02581   */
02582 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
02583 {
02584   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
02585 }
02586
02587 /**
02588   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02589   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02590   *       output channel 6 is supported by a timer instance.
02591   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02592   * @param  TIMx Timer instance
02593   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02594   * @retval None
02595   */
02596 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
02597 {
02598   WRITE_REG(TIMx->CCR6, CompareValue);
02599 }
02600
02601 /**
02602   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02603   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02604   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02605   *       whether or not a timer instance supports a 32 bits counter.
02606   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02607   *       output channel 1 is supported by a timer instance.
02608   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02609   * @param  TIMx Timer instance
02610   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02611   */
02612 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
02613 {
02614   return (uint32_t)(READ_REG(TIMx->CCR1));
02615 }
02616
02617 /**
02618   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02619   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02620   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02621   *       whether or not a timer instance supports a 32 bits counter.
02622   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02623   *       output channel 2 is supported by a timer instance.
02624   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02625   * @param  TIMx Timer instance
02626   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02627   */
02628 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
02629 {
02630   return (uint32_t)(READ_REG(TIMx->CCR2));
02631 }
02632
02633 /**
02634   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02635   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02636   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02637   *       whether or not a timer instance supports a 32 bits counter.
02638   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02639   *       output channel 3 is supported by a timer instance.
02640   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02641   * @param  TIMx Timer instance
02642   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02643   */
02644 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
02645 {
02646   return (uint32_t)(READ_REG(TIMx->CCR3));
02647 }
02648
02649 /**
02650   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02651   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02652   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02653   *       whether or not a timer instance supports a 32 bits counter.
02654   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02655   *       output channel 4 is supported by a timer instance.
02656   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02657   * @param  TIMx Timer instance
02658   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02659   */
02660 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
02661 {
02662   return (uint32_t)(READ_REG(TIMx->CCR4));
02663 }
02664
02665 /**
02666   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02667   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02668   *       output channel 5 is supported by a timer instance.
02669   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02670   * @param  TIMx Timer instance
02671   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02672   */
02673 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
02674 {
02675   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
02676 }
02677
02678 /**
02679   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02680   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02681   *       output channel 6 is supported by a timer instance.
02682   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02683   * @param  TIMx Timer instance
02684   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02685   */
02686 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
02687 {
02688   return (uint32_t)(READ_REG(TIMx->CCR6));
02689 }
02690
02691 /**
02692   * @brief  Select on which reference signal the OC5REF is combined to.
02693   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02694   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02695   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02696   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02697   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02698   * @param  TIMx Timer instance
02699   * @param  GroupCH5 This parameter can be a combination of the following values:
02700   *         @arg @ref LL_TIM_GROUPCH5_NONE
02701   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02702   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02703   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02704   * @retval None
02705   */
02706 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
02707 {
02708   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
02709 }
02710
02711 /**
02712   * @}
02713   */
02714
02715 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02716   * @{
02717   */
02718 /**
02719   * @brief  Configure input channel.
02720   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02721   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02722   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02723   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02724   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02725   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02726   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02727   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02728   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02729   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02730   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02731   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02732   *         CCER         CC1P          LL_TIM_IC_Config\n
02733   *         CCER         CC1NP         LL_TIM_IC_Config\n
02734   *         CCER         CC2P          LL_TIM_IC_Config\n
02735   *         CCER         CC2NP         LL_TIM_IC_Config\n
02736   *         CCER         CC3P          LL_TIM_IC_Config\n
02737   *         CCER         CC3NP         LL_TIM_IC_Config\n
02738   *         CCER         CC4P          LL_TIM_IC_Config\n
02739   *         CCER         CC4NP         LL_TIM_IC_Config
02740   * @param  TIMx Timer instance
02741   * @param  Channel This parameter can be one of the following values:
02742   *         @arg @ref LL_TIM_CHANNEL_CH1
02743   *         @arg @ref LL_TIM_CHANNEL_CH2
02744   *         @arg @ref LL_TIM_CHANNEL_CH3
02745   *         @arg @ref LL_TIM_CHANNEL_CH4
02746   * @param  Configuration This parameter must be a combination of all the following values:
02747   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02748   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02749   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02750   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02751   * @retval None
02752   */
02753 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02754 {
02755   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02756   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02757   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02758              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02759   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02760              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02761 }
02762
02763 /**
02764   * @brief  Set the active input.
02765   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02766   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02767   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02768   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02769   * @param  TIMx Timer instance
02770   * @param  Channel This parameter can be one of the following values:
02771   *         @arg @ref LL_TIM_CHANNEL_CH1
02772   *         @arg @ref LL_TIM_CHANNEL_CH2
02773   *         @arg @ref LL_TIM_CHANNEL_CH3
02774   *         @arg @ref LL_TIM_CHANNEL_CH4
02775   * @param  ICActiveInput This parameter can be one of the following values:
02776   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02777   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02778   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02779   * @retval None
02780   */
02781 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02782 {
02783   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02784   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02785   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02786 }
02787
02788 /**
02789   * @brief  Get the current active input.
02790   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02791   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02792   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02793   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02794   * @param  TIMx Timer instance
02795   * @param  Channel This parameter can be one of the following values:
02796   *         @arg @ref LL_TIM_CHANNEL_CH1
02797   *         @arg @ref LL_TIM_CHANNEL_CH2
02798   *         @arg @ref LL_TIM_CHANNEL_CH3
02799   *         @arg @ref LL_TIM_CHANNEL_CH4
02800   * @retval Returned value can be one of the following values:
02801   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02802   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02803   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02804   */
02805 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
02806 {
02807   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02808   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02809   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02810 }
02811
02812 /**
02813   * @brief  Set the prescaler of input channel.
02814   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02815   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02816   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02817   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02818   * @param  TIMx Timer instance
02819   * @param  Channel This parameter can be one of the following values:
02820   *         @arg @ref LL_TIM_CHANNEL_CH1
02821   *         @arg @ref LL_TIM_CHANNEL_CH2
02822   *         @arg @ref LL_TIM_CHANNEL_CH3
02823   *         @arg @ref LL_TIM_CHANNEL_CH4
02824   * @param  ICPrescaler This parameter can be one of the following values:
02825   *         @arg @ref LL_TIM_ICPSC_DIV1
02826   *         @arg @ref LL_TIM_ICPSC_DIV2
02827   *         @arg @ref LL_TIM_ICPSC_DIV4
02828   *         @arg @ref LL_TIM_ICPSC_DIV8
02829   * @retval None
02830   */
02831 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
02832 {
02833   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02834   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02835   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02836 }
02837
02838 /**
02839   * @brief  Get the current prescaler value acting on an  input channel.
02840   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02841   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02842   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02843   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02844   * @param  TIMx Timer instance
02845   * @param  Channel This parameter can be one of the following values:
02846   *         @arg @ref LL_TIM_CHANNEL_CH1
02847   *         @arg @ref LL_TIM_CHANNEL_CH2
02848   *         @arg @ref LL_TIM_CHANNEL_CH3
02849   *         @arg @ref LL_TIM_CHANNEL_CH4
02850   * @retval Returned value can be one of the following values:
02851   *         @arg @ref LL_TIM_ICPSC_DIV1
02852   *         @arg @ref LL_TIM_ICPSC_DIV2
02853   *         @arg @ref LL_TIM_ICPSC_DIV4
02854   *         @arg @ref LL_TIM_ICPSC_DIV8
02855   */
02856 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
02857 {
02858   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02859   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02860   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02861 }
02862
02863 /**
02864   * @brief  Set the input filter duration.
02865   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
02866   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
02867   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
02868   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
02869   * @param  TIMx Timer instance
02870   * @param  Channel This parameter can be one of the following values:
02871   *         @arg @ref LL_TIM_CHANNEL_CH1
02872   *         @arg @ref LL_TIM_CHANNEL_CH2
02873   *         @arg @ref LL_TIM_CHANNEL_CH3
02874   *         @arg @ref LL_TIM_CHANNEL_CH4
02875   * @param  ICFilter This parameter can be one of the following values:
02876   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02877   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02878   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02879   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02880   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02881   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02882   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02883   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02884   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02885   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02886   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02887   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02888   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02889   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02890   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02891   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02892   * @retval None
02893   */
02894 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
02895 {
02896   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02897   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02898   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02899 }
02900
02901 /**
02902   * @brief  Get the input filter duration.
02903   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
02904   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
02905   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
02906   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
02907   * @param  TIMx Timer instance
02908   * @param  Channel This parameter can be one of the following values:
02909   *         @arg @ref LL_TIM_CHANNEL_CH1
02910   *         @arg @ref LL_TIM_CHANNEL_CH2
02911   *         @arg @ref LL_TIM_CHANNEL_CH3
02912   *         @arg @ref LL_TIM_CHANNEL_CH4
02913   * @retval Returned value can be one of the following values:
02914   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02915   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02916   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02917   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02918   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02919   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02920   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02921   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02922   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02923   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02924   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02925   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02926   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02927   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02928   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02929   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02930   */
02931 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
02932 {
02933   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02934   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02935   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02936 }
02937
02938 /**
02939   * @brief  Set the input channel polarity.
02940   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
02941   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
02942   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
02943   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
02944   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
02945   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
02946   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
02947   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
02948   * @param  TIMx Timer instance
02949   * @param  Channel This parameter can be one of the following values:
02950   *         @arg @ref LL_TIM_CHANNEL_CH1
02951   *         @arg @ref LL_TIM_CHANNEL_CH2
02952   *         @arg @ref LL_TIM_CHANNEL_CH3
02953   *         @arg @ref LL_TIM_CHANNEL_CH4
02954   * @param  ICPolarity This parameter can be one of the following values:
02955   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02956   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02957   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02958   * @retval None
02959   */
02960 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
02961 {
02962   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02963   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02964              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02965 }
02966
02967 /**
02968   * @brief  Get the current input channel polarity.
02969   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
02970   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
02971   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
02972   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
02973   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
02974   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
02975   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
02976   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
02977   * @param  TIMx Timer instance
02978   * @param  Channel This parameter can be one of the following values:
02979   *         @arg @ref LL_TIM_CHANNEL_CH1
02980   *         @arg @ref LL_TIM_CHANNEL_CH2
02981   *         @arg @ref LL_TIM_CHANNEL_CH3
02982   *         @arg @ref LL_TIM_CHANNEL_CH4
02983   * @retval Returned value can be one of the following values:
02984   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02985   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02986   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02987   */
02988 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02989 {
02990   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02991   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
02992           SHIFT_TAB_CCxP[iChannel]);
02993 }
02994
02995 /**
02996   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02997   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02998   *       a timer instance provides an XOR input.
02999   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
03000   * @param  TIMx Timer instance
03001   * @retval None
03002   */
03003 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
03004 {
03005   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
03006 }
03007
03008 /**
03009   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
03010   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03011   *       a timer instance provides an XOR input.
03012   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
03013   * @param  TIMx Timer instance
03014   * @retval None
03015   */
03016 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
03017 {
03018   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
03019 }
03020
03021 /**
03022   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
03023   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03024   * a timer instance provides an XOR input.
03025   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
03026   * @param  TIMx Timer instance
03027   * @retval State of bit (1 or 0).
03028   */
03029 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
03030 {
03031   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
03032 }
03033
03034 /**
03035   * @brief  Get captured value for input channel 1.
03036   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03037   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03038   *       whether or not a timer instance supports a 32 bits counter.
03039   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03040   *       input channel 1 is supported by a timer instance.
03041   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
03042   * @param  TIMx Timer instance
03043   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03044   */
03045 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
03046 {
03047   return (uint32_t)(READ_REG(TIMx->CCR1));
03048 }
03049
03050 /**
03051   * @brief  Get captured value for input channel 2.
03052   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03053   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03054   *       whether or not a timer instance supports a 32 bits counter.
03055   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03056   *       input channel 2 is supported by a timer instance.
03057   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
03058   * @param  TIMx Timer instance
03059   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03060   */
03061 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
03062 {
03063   return (uint32_t)(READ_REG(TIMx->CCR2));
03064 }
03065
03066 /**
03067   * @brief  Get captured value for input channel 3.
03068   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03069   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03070   *       whether or not a timer instance supports a 32 bits counter.
03071   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03072   *       input channel 3 is supported by a timer instance.
03073   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
03074   * @param  TIMx Timer instance
03075   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03076   */
03077 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
03078 {
03079   return (uint32_t)(READ_REG(TIMx->CCR3));
03080 }
03081
03082 /**
03083   * @brief  Get captured value for input channel 4.
03084   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03085   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03086   *       whether or not a timer instance supports a 32 bits counter.
03087   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03088   *       input channel 4 is supported by a timer instance.
03089   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
03090   * @param  TIMx Timer instance
03091   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03092   */
03093 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
03094 {
03095   return (uint32_t)(READ_REG(TIMx->CCR4));
03096 }
03097
03098 /**
03099   * @}
03100   */
03101
03102 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03103   * @{
03104   */
03105 /**
03106   * @brief  Enable external clock mode 2.
03107   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03108   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03109   *       whether or not a timer instance supports external clock mode2.
03110   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03111   * @param  TIMx Timer instance
03112   * @retval None
03113   */
03114 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
03115 {
03116   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03117 }
03118
03119 /**
03120   * @brief  Disable external clock mode 2.
03121   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03122   *       whether or not a timer instance supports external clock mode2.
03123   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03124   * @param  TIMx Timer instance
03125   * @retval None
03126   */
03127 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
03128 {
03129   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03130 }
03131
03132 /**
03133   * @brief  Indicate whether external clock mode 2 is enabled.
03134   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03135   *       whether or not a timer instance supports external clock mode2.
03136   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03137   * @param  TIMx Timer instance
03138   * @retval State of bit (1 or 0).
03139   */
03140 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
03141 {
03142   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
03143 }
03144
03145 /**
03146   * @brief  Set the clock source of the counter clock.
03147   * @note when selected clock source is external clock mode 1, the timer input
03148   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03149   *       function. This timer input must be configured by calling
03150   *       the @ref LL_TIM_IC_Config() function.
03151   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03152   *       whether or not a timer instance supports external clock mode1.
03153   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03154   *       whether or not a timer instance supports external clock mode2.
03155   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03156   *         SMCR         ECE           LL_TIM_SetClockSource
03157   * @param  TIMx Timer instance
03158   * @param  ClockSource This parameter can be one of the following values:
03159   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03160   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03161   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03162   * @retval None
03163   */
03164 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
03165 {
03166   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03167 }
03168
03169 /**
03170   * @brief  Set the encoder interface mode.
03171   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03172   *       whether or not a timer instance supports the encoder mode.
03173   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03174   * @param  TIMx Timer instance
03175   * @param  EncoderMode This parameter can be one of the following values:
03176   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03177   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03178   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03179   * @retval None
03180   */
03181 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03182 {
03183   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03184 }
03185
03186 /**
03187   * @}
03188   */
03189
03190 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03191   * @{
03192   */
03193 /**
03194   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03195   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03196   *       whether or not a timer instance can operate as a master timer.
03197   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03198   * @param  TIMx Timer instance
03199   * @param  TimerSynchronization This parameter can be one of the following values:
03200   *         @arg @ref LL_TIM_TRGO_RESET
03201   *         @arg @ref LL_TIM_TRGO_ENABLE
03202   *         @arg @ref LL_TIM_TRGO_UPDATE
03203   *         @arg @ref LL_TIM_TRGO_CC1IF
03204   *         @arg @ref LL_TIM_TRGO_OC1REF
03205   *         @arg @ref LL_TIM_TRGO_OC2REF
03206   *         @arg @ref LL_TIM_TRGO_OC3REF
03207   *         @arg @ref LL_TIM_TRGO_OC4REF
03208   * @retval None
03209   */
03210 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
03211 {
03212   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03213 }
03214
03215 /**
03216   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03217   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03218   *       whether or not a timer instance can be used for ADC synchronization.
03219   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03220   * @param  TIMx Timer Instance
03221   * @param  ADCSynchronization This parameter can be one of the following values:
03222   *         @arg @ref LL_TIM_TRGO2_RESET
03223   *         @arg @ref LL_TIM_TRGO2_ENABLE
03224   *         @arg @ref LL_TIM_TRGO2_UPDATE
03225   *         @arg @ref LL_TIM_TRGO2_CC1F
03226   *         @arg @ref LL_TIM_TRGO2_OC1
03227   *         @arg @ref LL_TIM_TRGO2_OC2
03228   *         @arg @ref LL_TIM_TRGO2_OC3
03229   *         @arg @ref LL_TIM_TRGO2_OC4
03230   *         @arg @ref LL_TIM_TRGO2_OC5
03231   *         @arg @ref LL_TIM_TRGO2_OC6
03232   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03233   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03234   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03235   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03236   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03237   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03238   * @retval None
03239   */
03240 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
03241 {
03242   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03243 }
03244
03245 /**
03246   * @brief  Set the synchronization mode of a slave timer.
03247   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03248   *       a timer instance can operate as a slave timer.
03249   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03250   * @param  TIMx Timer instance
03251   * @param  SlaveMode This parameter can be one of the following values:
03252   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03253   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03254   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03255   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03256   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03257   * @retval None
03258   */
03259 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
03260 {
03261   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03262 }
03263
03264 /**
03265   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03266   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03267   *       a timer instance can operate as a slave timer.
03268   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03269   * @param  TIMx Timer instance
03270   * @param  TriggerInput This parameter can be one of the following values:
03271   *         @arg @ref LL_TIM_TS_ITR0
03272   *         @arg @ref LL_TIM_TS_ITR1
03273   *         @arg @ref LL_TIM_TS_ITR2
03274   *         @arg @ref LL_TIM_TS_ITR3
03275   *         @arg @ref LL_TIM_TS_TI1F_ED
03276   *         @arg @ref LL_TIM_TS_TI1FP1
03277   *         @arg @ref LL_TIM_TS_TI2FP2
03278   *         @arg @ref LL_TIM_TS_ETRF
03279   *         @arg @ref LL_TIM_TS_ITR4
03280   *         @arg @ref LL_TIM_TS_ITR5
03281   *         @arg @ref LL_TIM_TS_ITR6
03282   *         @arg @ref LL_TIM_TS_ITR7
03283   *         @arg @ref LL_TIM_TS_ITR8 (*)
03284   *         @arg @ref LL_TIM_TS_ITR9 (*)
03285   *         @arg @ref LL_TIM_TS_ITR10 (*)
03286   *         @arg @ref LL_TIM_TS_ITR11 (*)
03287   *         @arg @ref LL_TIM_TS_ITR12 (*)
03288   *         @arg @ref LL_TIM_TS_ITR13 (*)
03289   *
03290   *      (*)  Value not defined in all devices.
03291   * @retval None
03292   */
03293 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
03294 {
03295   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03296 }
03297
03298 /**
03299   * @brief  Enable the Master/Slave mode.
03300   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03301   *       a timer instance can operate as a slave timer.
03302   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03303   * @param  TIMx Timer instance
03304   * @retval None
03305   */
03306 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
03307 {
03308   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03309 }
03310
03311 /**
03312   * @brief  Disable the Master/Slave mode.
03313   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03314   *       a timer instance can operate as a slave timer.
03315   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03316   * @param  TIMx Timer instance
03317   * @retval None
03318   */
03319 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
03320 {
03321   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03322 }
03323
03324 /**
03325   * @brief Indicates whether the Master/Slave mode is enabled.
03326   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03327   * a timer instance can operate as a slave timer.
03328   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03329   * @param  TIMx Timer instance
03330   * @retval State of bit (1 or 0).
03331   */
03332 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
03333 {
03334   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
03335 }
03336
03337 /**
03338   * @brief  Configure the external trigger (ETR) input.
03339   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03340   *       a timer instance provides an external trigger input.
03341   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03342   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03343   *         SMCR         ETF           LL_TIM_ConfigETR
03344   * @param  TIMx Timer instance
03345   * @param  ETRPolarity This parameter can be one of the following values:
03346   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03347   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03348   * @param  ETRPrescaler This parameter can be one of the following values:
03349   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03350   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03351   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03352   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03353   * @param  ETRFilter This parameter can be one of the following values:
03354   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03355   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03356   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03357   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03358   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03359   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03360   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03361   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03362   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03363   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03364   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03365   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03366   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03367   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03368   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03369   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03370   * @retval None
03371   */
03372 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
03373                                       uint32_t ETRFilter)
03374 {
03375   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03376 }
03377
03378 /**
03379   * @brief  Select the external trigger (ETR) input source.
03380   * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
03381   *       not a timer instance supports ETR source selection.
03382   * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
03383   * @param  TIMx Timer instance
03384   * @param  ETRSource This parameter can be one of the following values:
03385   *      For TIM1, the parameter is one of the following values:
03386   *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO
03387   *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output
03388   *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output
03389   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
03390   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
03391   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
03392   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
03393   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
03394   *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
03395   *
03396   *      For TIM2, the parameter is one of the following values:
03397   *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO
03398   *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output
03399   *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output
03400   *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE
03401   *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
03402   *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
03403   *
03404   *      For TIM3, the parameter is one of the following values:
03405   *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO
03406   *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output
03407   *
03408   *      For TIM5, the parameter is one of the following values:
03409   *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO
03410   *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
03411   *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
03412   *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
03413   *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
03414   *
03415   *      For TIM8, the parameter is one of the following values:
03416   *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO
03417   *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output
03418   *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output
03419   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
03420   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
03421   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
03422   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
03423   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
03424   *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
03425   *
03426   *      For TIM23, the parameter is one of the following values: (*)
03427   *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO
03428   *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output
03429   *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output
03430   *
03431   *      For TIM24, the parameter is one of the following values: (*)
03432   *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO
03433   *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
03434   *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
03435   *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
03436   *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
03437   *
03438   *      (*)  Value not defined in all devices.
03439   * @retval None
03440   */
03441 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
03442 {
03443
03444   MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
03445 }
03446
03447 /**
03448   * @}
03449   */
03450
03451 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03452   * @{
03453   */
03454 /**
03455   * @brief  Enable the break function.
03456   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03457   *       a timer instance provides a break input.
03458   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03459   * @param  TIMx Timer instance
03460   * @retval None
03461   */
03462 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
03463 {
03464   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03465 }
03466
03467 /**
03468   * @brief  Disable the break function.
03469   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03470   * @param  TIMx Timer instance
03471   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03472   *       a timer instance provides a break input.
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
03476 {
03477   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03478 }
03479
03480 /**
03481   * @brief  Configure the break input.
03482   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03483   *       a timer instance provides a break input.
03484   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03485   *         BDTR         BKF           LL_TIM_ConfigBRK
03486   * @param  TIMx Timer instance
03487   * @param  BreakPolarity This parameter can be one of the following values:
03488   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03489   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03490   * @param  BreakFilter This parameter can be one of the following values:
03491   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03492   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03493   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03494   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03495   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03496   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03497   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03498   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03499   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03500   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03501   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03502   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03503   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03504   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03505   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03506   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03507   * @retval None
03508   */
03509 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
03510                                       uint32_t BreakFilter)
03511 {
03512   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
03513 }
03514
03515 /**
03516   * @brief  Enable the break 2 function.
03517   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03518   *       a timer instance provides a second break input.
03519   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03520   * @param  TIMx Timer instance
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
03524 {
03525   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03526 }
03527
03528 /**
03529   * @brief  Disable the break  2 function.
03530   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03531   *       a timer instance provides a second break input.
03532   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03533   * @param  TIMx Timer instance
03534   * @retval None
03535   */
03536 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
03537 {
03538   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03539 }
03540
03541 /**
03542   * @brief  Configure the break 2 input.
03543   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03544   *       a timer instance provides a second break input.
03545   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03546   *         BDTR         BK2F          LL_TIM_ConfigBRK2
03547   * @param  TIMx Timer instance
03548   * @param  Break2Polarity This parameter can be one of the following values:
03549   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03550   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03551   * @param  Break2Filter This parameter can be one of the following values:
03552   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03553   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03554   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03555   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03556   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03557   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03558   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03559   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03560   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03561   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03562   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03563   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03564   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03565   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03566   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03567   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03568   * @retval None
03569   */
03570 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03571 {
03572   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03573 }
03574
03575 /**
03576   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03577   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03578   *       a timer instance provides a break input.
03579   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03580   *         BDTR         OSSR          LL_TIM_SetOffStates
03581   * @param  TIMx Timer instance
03582   * @param  OffStateIdle This parameter can be one of the following values:
03583   *         @arg @ref LL_TIM_OSSI_DISABLE
03584   *         @arg @ref LL_TIM_OSSI_ENABLE
03585   * @param  OffStateRun This parameter can be one of the following values:
03586   *         @arg @ref LL_TIM_OSSR_DISABLE
03587   *         @arg @ref LL_TIM_OSSR_ENABLE
03588   * @retval None
03589   */
03590 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03591 {
03592   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03593 }
03594
03595 /**
03596   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03597   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03598   *       a timer instance provides a break input.
03599   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03600   * @param  TIMx Timer instance
03601   * @retval None
03602   */
03603 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
03604 {
03605   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03606 }
03607
03608 /**
03609   * @brief  Disable automatic output (MOE can be set only by software).
03610   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03611   *       a timer instance provides a break input.
03612   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03613   * @param  TIMx Timer instance
03614   * @retval None
03615   */
03616 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
03617 {
03618   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03619 }
03620
03621 /**
03622   * @brief  Indicate whether automatic output is enabled.
03623   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03624   *       a timer instance provides a break input.
03625   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03626   * @param  TIMx Timer instance
03627   * @retval State of bit (1 or 0).
03628   */
03629 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
03630 {
03631   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
03632 }
03633
03634 /**
03635   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03636   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03637   *       software and is reset in case of break or break2 event
03638   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03639   *       a timer instance provides a break input.
03640   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03641   * @param  TIMx Timer instance
03642   * @retval None
03643   */
03644 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
03645 {
03646   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03647 }
03648
03649 /**
03650   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03651   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03652   *       software and is reset in case of break or break2 event.
03653   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03654   *       a timer instance provides a break input.
03655   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03656   * @param  TIMx Timer instance
03657   * @retval None
03658   */
03659 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
03660 {
03661   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03662 }
03663
03664 /**
03665   * @brief  Indicates whether outputs are enabled.
03666   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03667   *       a timer instance provides a break input.
03668   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03669   * @param  TIMx Timer instance
03670   * @retval State of bit (1 or 0).
03671   */
03672 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
03673 {
03674   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
03675 }
03676
03677 #if defined(TIM_BREAK_INPUT_SUPPORT)
03678 /**
03679   * @brief  Enable the signals connected to the designated timer break input.
03680   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03681   *       or not a timer instance allows for break input selection.
03682   * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
03683   *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03684   *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03685   *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
03686   *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
03687   *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
03688   *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
03689   *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
03690   * @param  TIMx Timer instance
03691   * @param  BreakInput This parameter can be one of the following values:
03692   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03693   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03694   * @param  Source This parameter can be one of the following values:
03695   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03696   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03697   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03698   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03699   * @retval None
03700   */
03701 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03702 {
03703   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03704   SET_BIT(*pReg, Source);
03705 }
03706
03707 /**
03708   * @brief  Disable the signals connected to the designated timer break input.
03709   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03710   *       or not a timer instance allows for break input selection.
03711   * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
03712   *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03713   *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03714   *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
03715   *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
03716   *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
03717   *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
03718   *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
03719   * @param  TIMx Timer instance
03720   * @param  BreakInput This parameter can be one of the following values:
03721   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03722   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03723   * @param  Source This parameter can be one of the following values:
03724   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03725   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03726   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03727   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03731 {
03732   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03733   CLEAR_BIT(*pReg, Source);
03734 }
03735
03736 /**
03737   * @brief  Set the polarity of the break signal for the timer break input.
03738   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03739   *       or not a timer instance allows for break input selection.
03740   * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03741   *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
03742   *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
03743   *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
03744   *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
03745   *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
03746   * @param  TIMx Timer instance
03747   * @param  BreakInput This parameter can be one of the following values:
03748   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03749   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03750   * @param  Source This parameter can be one of the following values:
03751   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03752   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03753   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03754   * @param  Polarity This parameter can be one of the following values:
03755   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
03756   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
03757   * @retval None
03758   */
03759 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
03760                                                         uint32_t Polarity)
03761 {
03762   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03763   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
03764 }
03765 #endif /* TIM_BREAK_INPUT_SUPPORT */
03766 /**
03767   * @}
03768   */
03769
03770 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
03771   * @{
03772   */
03773 /**
03774   * @brief  Configures the timer DMA burst feature.
03775   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03776   *       not a timer instance supports the DMA burst mode.
03777   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03778   *         DCR          DBA           LL_TIM_ConfigDMABurst
03779   * @param  TIMx Timer instance
03780   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03781   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03782   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03783   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03784   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03785   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03786   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03787   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03788   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03789   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03790   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03791   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03792   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03793   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03794   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03795   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03796   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03797   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03798   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03799   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
03800   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
03801   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
03802   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
03803   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
03804   *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
03805   *
03806   * @param  DMABurstLength This parameter can be one of the following values:
03807   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03808   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03809   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03810   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03811   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03812   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03813   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03814   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03815   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03816   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03817   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03818   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03819   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03820   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03821   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03822   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03823   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03824   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03825   * @retval None
03826   */
03827 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03828 {
03829   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
03830 }
03831
03832 /**
03833   * @}
03834   */
03835
03836 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03837   * @{
03838   */
03839 /**
03840   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03841   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03842   *       a some timer inputs can be remapped.
03843   *         TIM1: one of the following values:
03844   *            @arg TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
03845   *            @arg TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output
03846   *
03847   *         TIM2: one of the following values:
03848   *            @arg TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
03849   *            @arg TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output
03850   *            @arg TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output
03851   *            @arg TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
03852   *
03853   *         TIM3: one of the following values:
03854   *            @arg TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
03855   *            @arg TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output
03856   *            @arg TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output
03857   *            @arg TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
03858   *
03859   *         TIM5: one of the following values:
03860   *            @arg TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
03861   *            @arg TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
03862   *            @arg TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
03863   *
03864   *         TIM8: one of the following values:
03865   *            @arg TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO
03866   *            @arg TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output
03867   *
03868   *         TIM12: one of the following values: (*)
03869   *            @arg TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO
03870   *            @arg TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
03871   *
03872   *         TIM15: one of the following values:
03873   *            @arg TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO
03874   *            @arg TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1
03875   *            @arg TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1
03876   *            @arg TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1
03877   *            @arg TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE
03878   *            @arg TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI
03879   *            @arg TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2
03880   *            @arg TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO
03881   *            @arg TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2
03882   *            @arg TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2
03883   *            @arg TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2
03884   *
03885   *         TIM16: one of the following values:
03886   *            @arg TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO
03887   *            @arg TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI
03888   *            @arg TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE
03889   *            @arg TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
03890   *
03891   *         TIM17: one of the following values:
03892   *            @arg TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO
03893   *            @arg TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
03894   *            @arg TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
03895   *            @arg TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1
03896   *
03897   *         TIM23: one of the following values: (*)
03898   *            @arg TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO
03899   *            @arg TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output
03900   *            @arg TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output
03901   *            @arg TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
03902   *
03903   *         TIM24: one of the following values: (*)
03904   *            @arg TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO
03905   *            @arg TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
03906   *            @arg TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
03907   *            @arg TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
03908   *
03909   *         (*)  Value not defined in all devices. \n
03910   * @retval None
03911   */
03912 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
03913 {
03914   MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
03915 }
03916
03917 /**
03918   * @}
03919   */
03920
03921 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
03922   * @{
03923   */
03924 /**
03925   * @brief  Clear the update interrupt flag (UIF).
03926   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03927   * @param  TIMx Timer instance
03928   * @retval None
03929   */
03930 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
03931 {
03932   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03933 }
03934
03935 /**
03936   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03937   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03938   * @param  TIMx Timer instance
03939   * @retval State of bit (1 or 0).
03940   */
03941 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
03942 {
03943   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
03944 }
03945
03946 /**
03947   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03948   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03949   * @param  TIMx Timer instance
03950   * @retval None
03951   */
03952 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
03953 {
03954   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03955 }
03956
03957 /**
03958   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03959   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03960   * @param  TIMx Timer instance
03961   * @retval State of bit (1 or 0).
03962   */
03963 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
03964 {
03965   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
03966 }
03967
03968 /**
03969   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
03970   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
03971   * @param  TIMx Timer instance
03972   * @retval None
03973   */
03974 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
03975 {
03976   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
03977 }
03978
03979 /**
03980   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
03981   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
03982   * @param  TIMx Timer instance
03983   * @retval State of bit (1 or 0).
03984   */
03985 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
03986 {
03987   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
03988 }
03989
03990 /**
03991   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
03992   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
03993   * @param  TIMx Timer instance
03994   * @retval None
03995   */
03996 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
03997 {
03998   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
03999 }
04000
04001 /**
04002   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
04003   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
04004   * @param  TIMx Timer instance
04005   * @retval State of bit (1 or 0).
04006   */
04007 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
04008 {
04009   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
04010 }
04011
04012 /**
04013   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
04014   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
04015   * @param  TIMx Timer instance
04016   * @retval None
04017   */
04018 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
04019 {
04020   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
04021 }
04022
04023 /**
04024   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
04025   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
04026   * @param  TIMx Timer instance
04027   * @retval State of bit (1 or 0).
04028   */
04029 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
04030 {
04031   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
04032 }
04033
04034 /**
04035   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
04036   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
04037   * @param  TIMx Timer instance
04038   * @retval None
04039   */
04040 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
04041 {
04042   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
04043 }
04044
04045 /**
04046   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
04047   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
04048   * @param  TIMx Timer instance
04049   * @retval State of bit (1 or 0).
04050   */
04051 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
04052 {
04053   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
04054 }
04055
04056 /**
04057   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
04058   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
04059   * @param  TIMx Timer instance
04060   * @retval None
04061   */
04062 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
04063 {
04064   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
04065 }
04066
04067 /**
04068   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
04069   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
04070   * @param  TIMx Timer instance
04071   * @retval State of bit (1 or 0).
04072   */
04073 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
04074 {
04075   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
04076 }
04077
04078 /**
04079   * @brief  Clear the commutation interrupt flag (COMIF).
04080   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
04081   * @param  TIMx Timer instance
04082   * @retval None
04083   */
04084 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
04085 {
04086   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
04087 }
04088
04089 /**
04090   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
04091   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
04092   * @param  TIMx Timer instance
04093   * @retval State of bit (1 or 0).
04094   */
04095 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
04096 {
04097   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
04098 }
04099
04100 /**
04101   * @brief  Clear the trigger interrupt flag (TIF).
04102   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
04103   * @param  TIMx Timer instance
04104   * @retval None
04105   */
04106 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
04107 {
04108   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
04109 }
04110
04111 /**
04112   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
04113   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
04114   * @param  TIMx Timer instance
04115   * @retval State of bit (1 or 0).
04116   */
04117 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
04118 {
04119   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
04120 }
04121
04122 /**
04123   * @brief  Clear the break interrupt flag (BIF).
04124   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
04125   * @param  TIMx Timer instance
04126   * @retval None
04127   */
04128 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
04129 {
04130   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
04131 }
04132
04133 /**
04134   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
04135   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
04136   * @param  TIMx Timer instance
04137   * @retval State of bit (1 or 0).
04138   */
04139 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
04140 {
04141   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
04142 }
04143
04144 /**
04145   * @brief  Clear the break 2 interrupt flag (B2IF).
04146   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
04147   * @param  TIMx Timer instance
04148   * @retval None
04149   */
04150 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
04151 {
04152   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
04153 }
04154
04155 /**
04156   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
04157   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
04158   * @param  TIMx Timer instance
04159   * @retval State of bit (1 or 0).
04160   */
04161 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
04162 {
04163   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
04164 }
04165
04166 /**
04167   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
04168   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
04169   * @param  TIMx Timer instance
04170   * @retval None
04171   */
04172 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
04173 {
04174   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
04175 }
04176
04177 /**
04178   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
04179   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
04180   * @param  TIMx Timer instance
04181   * @retval State of bit (1 or 0).
04182   */
04183 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
04184 {
04185   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
04186 }
04187
04188 /**
04189   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
04190   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
04191   * @param  TIMx Timer instance
04192   * @retval None
04193   */
04194 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
04195 {
04196   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
04197 }
04198
04199 /**
04200   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
04201   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
04202   * @param  TIMx Timer instance
04203   * @retval State of bit (1 or 0).
04204   */
04205 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
04206 {
04207   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
04208 }
04209
04210 /**
04211   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
04212   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
04213   * @param  TIMx Timer instance
04214   * @retval None
04215   */
04216 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
04217 {
04218   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
04219 }
04220
04221 /**
04222   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
04223   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
04224   * @param  TIMx Timer instance
04225   * @retval State of bit (1 or 0).
04226   */
04227 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
04228 {
04229   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
04230 }
04231
04232 /**
04233   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
04234   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
04235   * @param  TIMx Timer instance
04236   * @retval None
04237   */
04238 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
04239 {
04240   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
04241 }
04242
04243 /**
04244   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
04245   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
04246   * @param  TIMx Timer instance
04247   * @retval State of bit (1 or 0).
04248   */
04249 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
04250 {
04251   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
04252 }
04253
04254 /**
04255   * @brief  Clear the system break interrupt flag (SBIF).
04256   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
04257   * @param  TIMx Timer instance
04258   * @retval None
04259   */
04260 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
04261 {
04262   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
04263 }
04264
04265 /**
04266   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
04267   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
04268   * @param  TIMx Timer instance
04269   * @retval State of bit (1 or 0).
04270   */
04271 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
04272 {
04273   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
04274 }
04275
04276 /**
04277   * @}
04278   */
04279
04280 /** @defgroup TIM_LL_EF_IT_Management IT-Management
04281   * @{
04282   */
04283 /**
04284   * @brief  Enable update interrupt (UIE).
04285   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
04286   * @param  TIMx Timer instance
04287   * @retval None
04288   */
04289 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
04290 {
04291   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
04292 }
04293
04294 /**
04295   * @brief  Disable update interrupt (UIE).
04296   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
04297   * @param  TIMx Timer instance
04298   * @retval None
04299   */
04300 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
04301 {
04302   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
04303 }
04304
04305 /**
04306   * @brief  Indicates whether the update interrupt (UIE) is enabled.
04307   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
04308   * @param  TIMx Timer instance
04309   * @retval State of bit (1 or 0).
04310   */
04311 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
04312 {
04313   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
04314 }
04315
04316 /**
04317   * @brief  Enable capture/compare 1 interrupt (CC1IE).
04318   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
04319   * @param  TIMx Timer instance
04320   * @retval None
04321   */
04322 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
04323 {
04324   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04325 }
04326
04327 /**
04328   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04329   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04330   * @param  TIMx Timer instance
04331   * @retval None
04332   */
04333 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
04334 {
04335   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04336 }
04337
04338 /**
04339   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04340   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04341   * @param  TIMx Timer instance
04342   * @retval State of bit (1 or 0).
04343   */
04344 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
04345 {
04346   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
04347 }
04348
04349 /**
04350   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04351   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04352   * @param  TIMx Timer instance
04353   * @retval None
04354   */
04355 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
04356 {
04357   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04358 }
04359
04360 /**
04361   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04362   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04363   * @param  TIMx Timer instance
04364   * @retval None
04365   */
04366 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
04367 {
04368   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04369 }
04370
04371 /**
04372   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04373   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04374   * @param  TIMx Timer instance
04375   * @retval State of bit (1 or 0).
04376   */
04377 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
04378 {
04379   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
04380 }
04381
04382 /**
04383   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04384   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04385   * @param  TIMx Timer instance
04386   * @retval None
04387   */
04388 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
04389 {
04390   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04391 }
04392
04393 /**
04394   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04395   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04396   * @param  TIMx Timer instance
04397   * @retval None
04398   */
04399 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
04400 {
04401   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04402 }
04403
04404 /**
04405   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04406   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04407   * @param  TIMx Timer instance
04408   * @retval State of bit (1 or 0).
04409   */
04410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
04411 {
04412   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
04413 }
04414
04415 /**
04416   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04417   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04418   * @param  TIMx Timer instance
04419   * @retval None
04420   */
04421 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
04422 {
04423   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04424 }
04425
04426 /**
04427   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04428   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04429   * @param  TIMx Timer instance
04430   * @retval None
04431   */
04432 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
04433 {
04434   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04435 }
04436
04437 /**
04438   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04439   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04440   * @param  TIMx Timer instance
04441   * @retval State of bit (1 or 0).
04442   */
04443 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
04444 {
04445   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
04446 }
04447
04448 /**
04449   * @brief  Enable commutation interrupt (COMIE).
04450   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04451   * @param  TIMx Timer instance
04452   * @retval None
04453   */
04454 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
04455 {
04456   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04457 }
04458
04459 /**
04460   * @brief  Disable commutation interrupt (COMIE).
04461   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04462   * @param  TIMx Timer instance
04463   * @retval None
04464   */
04465 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
04466 {
04467   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04468 }
04469
04470 /**
04471   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04472   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04473   * @param  TIMx Timer instance
04474   * @retval State of bit (1 or 0).
04475   */
04476 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
04477 {
04478   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
04479 }
04480
04481 /**
04482   * @brief  Enable trigger interrupt (TIE).
04483   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04484   * @param  TIMx Timer instance
04485   * @retval None
04486   */
04487 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
04488 {
04489   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04490 }
04491
04492 /**
04493   * @brief  Disable trigger interrupt (TIE).
04494   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04495   * @param  TIMx Timer instance
04496   * @retval None
04497   */
04498 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
04499 {
04500   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04501 }
04502
04503 /**
04504   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04505   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04506   * @param  TIMx Timer instance
04507   * @retval State of bit (1 or 0).
04508   */
04509 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
04510 {
04511   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
04512 }
04513
04514 /**
04515   * @brief  Enable break interrupt (BIE).
04516   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04517   * @param  TIMx Timer instance
04518   * @retval None
04519   */
04520 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
04521 {
04522   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04523 }
04524
04525 /**
04526   * @brief  Disable break interrupt (BIE).
04527   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04528   * @param  TIMx Timer instance
04529   * @retval None
04530   */
04531 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
04532 {
04533   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04534 }
04535
04536 /**
04537   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04538   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04539   * @param  TIMx Timer instance
04540   * @retval State of bit (1 or 0).
04541   */
04542 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
04543 {
04544   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
04545 }
04546
04547 /**
04548   * @}
04549   */
04550
04551 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
04552   * @{
04553   */
04554 /**
04555   * @brief  Enable update DMA request (UDE).
04556   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04557   * @param  TIMx Timer instance
04558   * @retval None
04559   */
04560 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04561 {
04562   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04563 }
04564
04565 /**
04566   * @brief  Disable update DMA request (UDE).
04567   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04568   * @param  TIMx Timer instance
04569   * @retval None
04570   */
04571 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04572 {
04573   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04574 }
04575
04576 /**
04577   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04578   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04579   * @param  TIMx Timer instance
04580   * @retval State of bit (1 or 0).
04581   */
04582 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
04583 {
04584   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
04585 }
04586
04587 /**
04588   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04589   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04590   * @param  TIMx Timer instance
04591   * @retval None
04592   */
04593 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
04594 {
04595   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04596 }
04597
04598 /**
04599   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04600   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04601   * @param  TIMx Timer instance
04602   * @retval None
04603   */
04604 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
04605 {
04606   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04607 }
04608
04609 /**
04610   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04611   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04612   * @param  TIMx Timer instance
04613   * @retval State of bit (1 or 0).
04614   */
04615 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
04616 {
04617   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
04618 }
04619
04620 /**
04621   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04622   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04623   * @param  TIMx Timer instance
04624   * @retval None
04625   */
04626 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
04627 {
04628   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04629 }
04630
04631 /**
04632   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04633   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04634   * @param  TIMx Timer instance
04635   * @retval None
04636   */
04637 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
04638 {
04639   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04640 }
04641
04642 /**
04643   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04644   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04645   * @param  TIMx Timer instance
04646   * @retval State of bit (1 or 0).
04647   */
04648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
04649 {
04650   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
04651 }
04652
04653 /**
04654   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04655   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04656   * @param  TIMx Timer instance
04657   * @retval None
04658   */
04659 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
04660 {
04661   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04662 }
04663
04664 /**
04665   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04666   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04667   * @param  TIMx Timer instance
04668   * @retval None
04669   */
04670 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
04671 {
04672   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04673 }
04674
04675 /**
04676   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04677   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04678   * @param  TIMx Timer instance
04679   * @retval State of bit (1 or 0).
04680   */
04681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
04682 {
04683   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
04684 }
04685
04686 /**
04687   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04688   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04689   * @param  TIMx Timer instance
04690   * @retval None
04691   */
04692 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
04693 {
04694   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04695 }
04696
04697 /**
04698   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04699   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04700   * @param  TIMx Timer instance
04701   * @retval None
04702   */
04703 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
04704 {
04705   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04706 }
04707
04708 /**
04709   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04710   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04711   * @param  TIMx Timer instance
04712   * @retval State of bit (1 or 0).
04713   */
04714 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
04715 {
04716   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
04717 }
04718
04719 /**
04720   * @brief  Enable commutation DMA request (COMDE).
04721   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04722   * @param  TIMx Timer instance
04723   * @retval None
04724   */
04725 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
04726 {
04727   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04728 }
04729
04730 /**
04731   * @brief  Disable commutation DMA request (COMDE).
04732   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04733   * @param  TIMx Timer instance
04734   * @retval None
04735   */
04736 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
04737 {
04738   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04739 }
04740
04741 /**
04742   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04743   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04744   * @param  TIMx Timer instance
04745   * @retval State of bit (1 or 0).
04746   */
04747 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
04748 {
04749   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
04750 }
04751
04752 /**
04753   * @brief  Enable trigger interrupt (TDE).
04754   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04755   * @param  TIMx Timer instance
04756   * @retval None
04757   */
04758 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
04759 {
04760   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04761 }
04762
04763 /**
04764   * @brief  Disable trigger interrupt (TDE).
04765   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04766   * @param  TIMx Timer instance
04767   * @retval None
04768   */
04769 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
04770 {
04771   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04772 }
04773
04774 /**
04775   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04776   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04777   * @param  TIMx Timer instance
04778   * @retval State of bit (1 or 0).
04779   */
04780 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
04781 {
04782   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
04783 }
04784
04785 /**
04786   * @}
04787   */
04788
04789 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
04790   * @{
04791   */
04792 /**
04793   * @brief  Generate an update event.
04794   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04795   * @param  TIMx Timer instance
04796   * @retval None
04797   */
04798 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
04799 {
04800   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04801 }
04802
04803 /**
04804   * @brief  Generate Capture/Compare 1 event.
04805   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04806   * @param  TIMx Timer instance
04807   * @retval None
04808   */
04809 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
04810 {
04811   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04812 }
04813
04814 /**
04815   * @brief  Generate Capture/Compare 2 event.
04816   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04817   * @param  TIMx Timer instance
04818   * @retval None
04819   */
04820 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
04821 {
04822   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04823 }
04824
04825 /**
04826   * @brief  Generate Capture/Compare 3 event.
04827   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04828   * @param  TIMx Timer instance
04829   * @retval None
04830   */
04831 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
04832 {
04833   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04834 }
04835
04836 /**
04837   * @brief  Generate Capture/Compare 4 event.
04838   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04839   * @param  TIMx Timer instance
04840   * @retval None
04841   */
04842 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
04843 {
04844   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04845 }
04846
04847 /**
04848   * @brief  Generate commutation event.
04849   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04850   * @param  TIMx Timer instance
04851   * @retval None
04852   */
04853 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
04854 {
04855   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04856 }
04857
04858 /**
04859   * @brief  Generate trigger event.
04860   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04861   * @param  TIMx Timer instance
04862   * @retval None
04863   */
04864 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
04865 {
04866   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04867 }
04868
04869 /**
04870   * @brief  Generate break event.
04871   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04872   * @param  TIMx Timer instance
04873   * @retval None
04874   */
04875 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
04876 {
04877   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04878 }
04879
04880 /**
04881   * @brief  Generate break 2 event.
04882   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04883   * @param  TIMx Timer instance
04884   * @retval None
04885   */
04886 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
04887 {
04888   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04889 }
04890
04891 /**
04892   * @}
04893   */
04894
04895 #if defined(USE_FULL_LL_DRIVER)
04896 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
04897   * @{
04898   */
04899
04900 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
04901 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
04902 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
04903 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04904 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04905 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
04906 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
04907 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04908 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04909 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04910 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04911 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04912 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04913 /**
04914   * @}
04915   */
04916 #endif /* USE_FULL_LL_DRIVER */
04917
04918 /**
04919   * @}
04920   */
04921
04922 /**
04923   * @}
04924   */
04925
04926 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
04927
04928 /**
04929   * @}
04930   */
04931
04932 #ifdef __cplusplus
04933 }
04934 #endif
04935
04936 #endif /* __STM32H7xx_LL_TIM_H */
04937 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:04 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_usart.c Source File

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stm32h7xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_usart.h"
00023 #include "stm32h7xx_ll_rcc.h"
00024 #include "stm32h7xx_ll_bus.h"
00025 #ifdef USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
00036
00037 /** @addtogroup USART_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup USART_LL_Private_Macros
00046   * @{
00047   */
00048
00049 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
00050                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
00051                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
00052                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
00053                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
00054                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
00055                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
00056                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
00057                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
00058                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
00059                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
00060                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
00061
00062 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00063  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00064 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
00065
00066 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00067 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00068
00069 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
00070 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
00071
00072 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00073                                           || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00074                                           || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00075                                           || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00076
00077 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00078                                        || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00079                                        || ((__VALUE__) == LL_USART_PARITY_ODD))
00080
00081 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00082                                           || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00083                                           || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00084
00085 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00086                                              || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00087
00088 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00089                                                  || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00090
00091 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00092                                            || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00093
00094 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00095                                               || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00096
00097 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00098                                             || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00099
00100 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00101                                          || ((__VALUE__) == LL_USART_STOPBITS_1) \
00102                                          || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00103                                          || ((__VALUE__) == LL_USART_STOPBITS_2))
00104
00105 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00106                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00107                                           || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00108                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Private function prototypes -----------------------------------------------*/
00115
00116 /* Exported functions --------------------------------------------------------*/
00117 /** @addtogroup USART_LL_Exported_Functions
00118   * @{
00119   */
00120
00121 /** @addtogroup USART_LL_EF_Init
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  De-initialize USART registers (Registers restored to their default values).
00127   * @param  USARTx USART Instance
00128   * @retval An ErrorStatus enumeration value:
00129   *          - SUCCESS: USART registers are de-initialized
00130   *          - ERROR: USART registers are not de-initialized
00131   */
00132 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00133 {
00134   ErrorStatus status = SUCCESS;
00135
00136   /* Check the parameters */
00137   assert_param(IS_UART_INSTANCE(USARTx));
00138
00139   if (USARTx == USART1)
00140   {
00141     /* Force reset of USART clock */
00142     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00143
00144     /* Release reset of USART clock */
00145     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00146   }
00147   else if (USARTx == USART2)
00148   {
00149     /* Force reset of USART clock */
00150     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00151
00152     /* Release reset of USART clock */
00153     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00154   }
00155   else if (USARTx == USART3)
00156   {
00157     /* Force reset of USART clock */
00158     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00159
00160     /* Release reset of USART clock */
00161     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00162   }
00163   else if (USARTx == UART4)
00164   {
00165     /* Force reset of UART clock */
00166     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00167
00168     /* Release reset of UART clock */
00169     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00170   }
00171   else if (USARTx == UART5)
00172   {
00173     /* Force reset of UART clock */
00174     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00175
00176     /* Release reset of UART clock */
00177     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00178   }
00179   else if (USARTx == USART6)
00180   {
00181     /* Force reset of USART clock */
00182     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
00183
00184     /* Release reset of USART clock */
00185     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
00186   }
00187   else if (USARTx == UART7)
00188   {
00189     /* Force reset of UART clock */
00190     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
00191
00192     /* Release reset of UART clock */
00193     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
00194   }
00195   else if (USARTx == UART8)
00196   {
00197     /* Force reset of UART clock */
00198     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
00199
00200     /* Release reset of UART clock */
00201     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
00202   }
00203 #if defined(UART9)
00204   else if (USARTx == UART9)
00205   {
00206     /* Force reset of UART clock */
00207     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
00208
00209     /* Release reset of UART clock */
00210     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
00211   }
00212 #endif /* UART9 */
00213 #if defined(USART10)
00214   else if (USARTx == USART10)
00215   {
00216     /* Force reset of USART clock */
00217     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
00218
00219     /* Release reset of USART clock */
00220     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
00221   }
00222 #endif /* USART10 */
00223   else
00224   {
00225     status = ERROR;
00226   }
00227
00228   return (status);
00229 }
00230
00231 /**
00232   * @brief  Initialize USART registers according to the specified
00233   *         parameters in USART_InitStruct.
00234   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00235   *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00236   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00237   * @param  USARTx USART Instance
00238   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00239   *         that contains the configuration information for the specified USART peripheral.
00240   * @retval An ErrorStatus enumeration value:
00241   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00242   *          - ERROR: Problem occurred during USART Registers initialization
00243   */
00244 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00245 {
00246   ErrorStatus status = ERROR;
00247   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00248
00249   /* Check the parameters */
00250   assert_param(IS_UART_INSTANCE(USARTx));
00251   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
00252   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00253   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00254   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00255   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00256   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00257   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00258   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00259
00260   /* USART needs to be in disabled state, in order to be able to configure some bits in
00261      CRx registers */
00262   if (LL_USART_IsEnabled(USARTx) == 0U)
00263   {
00264     /*---------------------------- USART CR1 Configuration ---------------------
00265      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00266      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00267      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00268      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00269      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00270      */
00271     MODIFY_REG(USARTx->CR1,
00272                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00273                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00274                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00275                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00276
00277     /*---------------------------- USART CR2 Configuration ---------------------
00278      * Configure USARTx CR2 (Stop bits) with parameters:
00279      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00280      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00281      */
00282     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00283
00284     /*---------------------------- USART CR3 Configuration ---------------------
00285      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00286      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00287      */
00288     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00289
00290     /*---------------------------- USART BRR Configuration ---------------------
00291      * Retrieve Clock frequency used for USART Peripheral
00292      */
00293     if (USARTx == USART1)
00294     {
00295       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00296     }
00297     else if (USARTx == USART2)
00298     {
00299       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00300     }
00301     else if (USARTx == USART3)
00302     {
00303       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00304     }
00305     else if (USARTx == UART4)
00306     {
00307       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00308     }
00309     else if (USARTx == UART5)
00310     {
00311       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00312     }
00313     else if (USARTx == USART6)
00314     {
00315       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00316     }
00317     else if (USARTx == UART7)
00318     {
00319       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00320     }
00321     else if (USARTx == UART8)
00322     {
00323       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00324     }
00325 #if defined(UART9)
00326     else if (USARTx == UART9)
00327     {
00328       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00329     }
00330 #endif /* UART9 */
00331 #if defined(USART10)
00332     else if (USARTx == USART10)
00333     {
00334       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00335     }
00336 #endif /* USART10 */
00337     else
00338     {
00339       /* Nothing to do, as error code is already assigned to ERROR value */
00340     }
00341
00342     /* Configure the USART Baud Rate :
00343        - prescaler value is required
00344        - valid baud rate value (different from 0) is required
00345        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00346     */
00347     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00348         && (USART_InitStruct->BaudRate != 0U))
00349     {
00350       status = SUCCESS;
00351       LL_USART_SetBaudRate(USARTx,
00352                            periphclk,
00353                            USART_InitStruct->PrescalerValue,
00354                            USART_InitStruct->OverSampling,
00355                            USART_InitStruct->BaudRate);
00356
00357       /* Check BRR is greater than or equal to 16d */
00358       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00359
00360       /* Check BRR is lower than or equal to 0xFFFF */
00361       assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
00362     }
00363
00364     /*---------------------------- USART PRESC Configuration -----------------------
00365      * Configure USARTx PRESC (Prescaler) with parameters:
00366      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
00367      */
00368     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
00369   }
00370   /* Endif (=> USART not in Disabled state => return ERROR) */
00371
00372   return (status);
00373 }
00374
00375 /**
00376   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00377   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00378   *                         whose fields will be set to default values.
00379   * @retval None
00380   */
00381
00382 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00383 {
00384   /* Set USART_InitStruct fields to default values */
00385   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
00386   USART_InitStruct->BaudRate            = 9600U;
00387   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00388   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00389   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00390   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00391   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00392   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00393 }
00394
00395 /**
00396   * @brief  Initialize USART Clock related settings according to the
00397   *         specified parameters in the USART_ClockInitStruct.
00398   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00399   *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00400   * @param  USARTx USART Instance
00401   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00402   *         that contains the Clock configuration information for the specified USART peripheral.
00403   * @retval An ErrorStatus enumeration value:
00404   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00405   *          - ERROR: Problem occurred during USART Registers initialization
00406   */
00407 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00408 {
00409   ErrorStatus status = SUCCESS;
00410
00411   /* Check USART Instance and Clock signal output parameters */
00412   assert_param(IS_UART_INSTANCE(USARTx));
00413   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00414
00415   /* USART needs to be in disabled state, in order to be able to configure some bits in
00416      CRx registers */
00417   if (LL_USART_IsEnabled(USARTx) == 0U)
00418   {
00419     /*---------------------------- USART CR2 Configuration -----------------------*/
00420     /* If Clock signal has to be output */
00421     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00422     {
00423       /* Deactivate Clock signal delivery :
00424        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00425        */
00426       LL_USART_DisableSCLKOutput(USARTx);
00427     }
00428     else
00429     {
00430       /* Ensure USART instance is USART capable */
00431       assert_param(IS_USART_INSTANCE(USARTx));
00432
00433       /* Check clock related parameters */
00434       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00435       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00436       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00437
00438       /*---------------------------- USART CR2 Configuration -----------------------
00439        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00440        * - Enable Clock Output:         USART_CR2_CLKEN set
00441        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00442        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00443        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00444        */
00445       MODIFY_REG(USARTx->CR2,
00446                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00447                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00448                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00449     }
00450   }
00451   /* Else (USART not in Disabled state => return ERROR */
00452   else
00453   {
00454     status = ERROR;
00455   }
00456
00457   return (status);
00458 }
00459
00460 /**
00461   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00462   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00463   *                              whose fields will be set to default values.
00464   * @retval None
00465   */
00466 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00467 {
00468   /* Set LL_USART_ClockInitStruct fields with default values */
00469   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00470   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00471   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00472   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00473 }
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
00488
00489 /**
00490   * @}
00491   */
00492
00493 #endif /* USE_FULL_LL_DRIVER */
00494
00495 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00496
Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_usart.h Source File

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stm32h7xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_USART_H
00022 #define STM32H7xx_LL_USART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
00036
00037 /** @defgroup USART_LL USART
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup USART_LL_Private_Variables USART Private Variables
00044   * @{
00045   */
00046 /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
00047 static const uint32_t USART_PRESCALER_TAB[] =
00048 {
00049   1UL,
00050   2UL,
00051   4UL,
00052   6UL,
00053   8UL,
00054   10UL,
00055   12UL,
00056   16UL,
00057   32UL,
00058   64UL,
00059   128UL,
00060   256UL
00061 };
00062 /**
00063   * @}
00064   */
00065
00066 /* Private constants ---------------------------------------------------------*/
00067 /* Private macros ------------------------------------------------------------*/
00068 #if defined(USE_FULL_LL_DRIVER)
00069 /** @defgroup USART_LL_Private_Macros USART Private Macros
00070   * @{
00071   */
00072 /**
00073   * @}
00074   */
00075 #endif /*USE_FULL_LL_DRIVER*/
00076
00077 /* Exported types ------------------------------------------------------------*/
00078 #if defined(USE_FULL_LL_DRIVER)
00079 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00080   * @{
00081   */
00082
00083 /**
00084   * @brief LL USART Init Structure definition
00085   */
00086 typedef struct
00087 {
00088   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00089                                            This parameter can be a value of @ref USART_LL_EC_PRESCALER.
00090
00091                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
00092
00093   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00094
00095                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00096
00097   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00098                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00099
00100                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00101
00102   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00103                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00104
00105                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00106
00107   uint32_t Parity;                    /*!< Specifies the parity mode.
00108                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00109
00110                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00111
00112   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00113                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00114
00115                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00116
00117   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00118                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00119
00120                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00121
00122   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00123                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00124
00125                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00126
00127 } LL_USART_InitTypeDef;
00128
00129 /**
00130   * @brief LL USART Clock Init Structure definition
00131   */
00132 typedef struct
00133 {
00134   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00135                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00136
00137                                            USART HW configuration can be modified afterwards using unitary functions
00138                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00139                                            For more details, refer to description of this function. */
00140
00141   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00142                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00143
00144                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00145                                            For more details, refer to description of this function. */
00146
00147   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00148                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00149
00150                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00151                                            For more details, refer to description of this function. */
00152
00153   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00154                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00155                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00156
00157                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00158                                            For more details, refer to description of this function. */
00159
00160 } LL_USART_ClockInitTypeDef;
00161
00162 /**
00163   * @}
00164   */
00165 #endif /* USE_FULL_LL_DRIVER */
00166
00167 /* Exported constants --------------------------------------------------------*/
00168 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00169   * @{
00170   */
00171
00172 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00173   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00174   * @{
00175   */
00176 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
00177 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
00178 #define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */
00179 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
00180 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
00181 #define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
00182 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
00183 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
00184 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
00185 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
00186 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
00187 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
00188 #define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */
00189 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
00190 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00196   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00197   * @{
00198   */
00199 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00200 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00201 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00202 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00203 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00204 #define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00205 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00206 #define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00207 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00208 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00209 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00210 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00211 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00212 #define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
00213 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00214 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00215 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00216 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00217 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00218 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00219 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00220 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00221 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00222 #define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
00223 #define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
00224 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00225 #define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00226 #define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup USART_LL_EC_IT IT Defines
00232   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00233   * @{
00234   */
00235 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00236 #define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00237 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00238 #define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00239 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00240 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00241 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00242 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00243 #define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00244 #define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00245 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00246 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00247 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00248 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00249 #define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00250 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00251 #define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00257   * @{
00258   */
00259 #define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
00260 #define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
00261 #define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
00262 #define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
00263 #define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
00264 #define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00270   * @{
00271   */
00272 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00273 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00274 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00275 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup USART_LL_EC_PARITY Parity Control
00281   * @{
00282   */
00283 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00284 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00285 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00291   * @{
00292   */
00293 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00294 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00300   * @{
00301   */
00302 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00303 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00304 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00310   * @{
00311   */
00312 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00313 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00314 /**
00315   * @}
00316   */
00317
00318 #if defined(USE_FULL_LL_DRIVER)
00319 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00320   * @{
00321   */
00322
00323 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00324 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00325 /**
00326   * @}
00327   */
00328 #endif /*USE_FULL_LL_DRIVER*/
00329
00330 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00331   * @{
00332   */
00333 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00334 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup USART_LL_EC_PHASE Clock Phase
00340   * @{
00341   */
00342 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00343 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00349   * @{
00350   */
00351 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00352 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
00358   * @{
00359   */
00360 #define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */
00361 #define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
00362 #define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
00363 #define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
00364 #define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
00365 #define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
00366 #define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
00367 #define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
00368 #define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
00369 #define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
00370 #define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
00371 #define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00377   * @{
00378   */
00379 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00380 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00381 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00382 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00388   * @{
00389   */
00390 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00391 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00397   * @{
00398   */
00399 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00400 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00406   * @{
00407   */
00408 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00409 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00415   * @{
00416   */
00417 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00418 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup USART_LL_EC_BITORDER Bit Order
00424   * @{
00425   */
00426 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00427 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00433   * @{
00434   */
00435 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00436 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00437 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00438 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00444   * @{
00445   */
00446 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00447 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00453   * @{
00454   */
00455 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00456 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00457 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00458 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00464   * @{
00465   */
00466 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00467 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00468 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00474   * @{
00475   */
00476 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00477 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00483   * @{
00484   */
00485 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00486 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00492   * @{
00493   */
00494 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00495 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00501   * @{
00502   */
00503 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00504 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00505 /**
00506   * @}
00507   */
00508
00509 /**
00510   * @}
00511   */
00512
00513 /* Exported macro ------------------------------------------------------------*/
00514 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00515   * @{
00516   */
00517
00518 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00519   * @{
00520   */
00521
00522 /**
00523   * @brief  Write a value in USART register
00524   * @param  __INSTANCE__ USART Instance
00525   * @param  __REG__ Register to be written
00526   * @param  __VALUE__ Value to be written in the register
00527   * @retval None
00528   */
00529 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00530
00531 /**
00532   * @brief  Read a value in USART register
00533   * @param  __INSTANCE__ USART Instance
00534   * @param  __REG__ Register to be read
00535   * @retval Register value
00536   */
00537 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00543   * @{
00544   */
00545
00546 /**
00547   * @brief  Compute USARTDIV value according to Peripheral Clock and
00548   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00549   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00550   * @param  __PRESCALER__ This parameter can be one of the following values:
00551   *         @arg @ref LL_USART_PRESCALER_DIV1
00552   *         @arg @ref LL_USART_PRESCALER_DIV2
00553   *         @arg @ref LL_USART_PRESCALER_DIV4
00554   *         @arg @ref LL_USART_PRESCALER_DIV6
00555   *         @arg @ref LL_USART_PRESCALER_DIV8
00556   *         @arg @ref LL_USART_PRESCALER_DIV10
00557   *         @arg @ref LL_USART_PRESCALER_DIV12
00558   *         @arg @ref LL_USART_PRESCALER_DIV16
00559   *         @arg @ref LL_USART_PRESCALER_DIV32
00560   *         @arg @ref LL_USART_PRESCALER_DIV64
00561   *         @arg @ref LL_USART_PRESCALER_DIV128
00562   *         @arg @ref LL_USART_PRESCALER_DIV256
00563   * @param  __BAUDRATE__ Baud rate value to achieve
00564   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00565   */
00566 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
00567                                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00568
00569 /**
00570   * @brief  Compute USARTDIV value according to Peripheral Clock and
00571   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00572   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00573   * @param  __PRESCALER__ This parameter can be one of the following values:
00574   *         @arg @ref LL_USART_PRESCALER_DIV1
00575   *         @arg @ref LL_USART_PRESCALER_DIV2
00576   *         @arg @ref LL_USART_PRESCALER_DIV4
00577   *         @arg @ref LL_USART_PRESCALER_DIV6
00578   *         @arg @ref LL_USART_PRESCALER_DIV8
00579   *         @arg @ref LL_USART_PRESCALER_DIV10
00580   *         @arg @ref LL_USART_PRESCALER_DIV12
00581   *         @arg @ref LL_USART_PRESCALER_DIV16
00582   *         @arg @ref LL_USART_PRESCALER_DIV32
00583   *         @arg @ref LL_USART_PRESCALER_DIV64
00584   *         @arg @ref LL_USART_PRESCALER_DIV128
00585   *         @arg @ref LL_USART_PRESCALER_DIV256
00586   * @param  __BAUDRATE__ Baud rate value to achieve
00587   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00588   */
00589 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
00590                                                                                 + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00591
00592 /**
00593   * @}
00594   */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /* Exported functions --------------------------------------------------------*/
00601
00602 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00603   * @{
00604   */
00605
00606 /** @defgroup USART_LL_EF_Configuration Configuration functions
00607   * @{
00608   */
00609
00610 /**
00611   * @brief  USART Enable
00612   * @rmtoll CR1          UE            LL_USART_Enable
00613   * @param  USARTx USART Instance
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00617 {
00618   SET_BIT(USARTx->CR1, USART_CR1_UE);
00619 }
00620
00621 /**
00622   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00623   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00624   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00625   *         flags, in the USARTx_ISR are set to their default values.
00626   * @rmtoll CR1          UE            LL_USART_Disable
00627   * @param  USARTx USART Instance
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00631 {
00632   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00633 }
00634
00635 /**
00636   * @brief  Indicate if USART is enabled
00637   * @rmtoll CR1          UE            LL_USART_IsEnabled
00638   * @param  USARTx USART Instance
00639   * @retval State of bit (1 or 0).
00640   */
00641 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00642 {
00643   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00644 }
00645
00646 /**
00647   * @brief  FIFO Mode Enable
00648   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00649   *         FIFO mode feature is supported by the USARTx instance.
00650   * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
00651   * @param  USARTx USART Instance
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
00655 {
00656   SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00657 }
00658
00659 /**
00660   * @brief  FIFO Mode Disable
00661   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00662   *         FIFO mode feature is supported by the USARTx instance.
00663   * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
00664   * @param  USARTx USART Instance
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
00668 {
00669   CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00670 }
00671
00672 /**
00673   * @brief  Indicate if FIFO Mode is enabled
00674   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00675   *         FIFO mode feature is supported by the USARTx instance.
00676   * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
00677   * @param  USARTx USART Instance
00678   * @retval State of bit (1 or 0).
00679   */
00680 __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
00681 {
00682   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00683 }
00684
00685 /**
00686   * @brief  Configure TX FIFO Threshold
00687   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00688   *         FIFO mode feature is supported by the USARTx instance.
00689   * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
00690   * @param  USARTx USART Instance
00691   * @param  Threshold This parameter can be one of the following values:
00692   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00693   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00694   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00695   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00696   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00697   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00698   * @retval None
00699   */
00700 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00701 {
00702   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00703 }
00704
00705 /**
00706   * @brief  Return TX FIFO Threshold Configuration
00707   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00708   *         FIFO mode feature is supported by the USARTx instance.
00709   * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
00710   * @param  USARTx USART Instance
00711   * @retval Returned value can be one of the following values:
00712   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00713   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00714   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00715   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00716   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00717   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00718   */
00719 __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
00720 {
00721   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00722 }
00723
00724 /**
00725   * @brief  Configure RX FIFO Threshold
00726   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00727   *         FIFO mode feature is supported by the USARTx instance.
00728   * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
00729   * @param  USARTx USART Instance
00730   * @param  Threshold This parameter can be one of the following values:
00731   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00732   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00733   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00734   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00735   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00736   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00737   * @retval None
00738   */
00739 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00740 {
00741   MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00742 }
00743
00744 /**
00745   * @brief  Return RX FIFO Threshold Configuration
00746   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00747   *         FIFO mode feature is supported by the USARTx instance.
00748   * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
00749   * @param  USARTx USART Instance
00750   * @retval Returned value can be one of the following values:
00751   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00752   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00753   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00754   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00755   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00756   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00757   */
00758 __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
00759 {
00760   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00761 }
00762
00763 /**
00764   * @brief  Configure TX and RX FIFOs Threshold
00765   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00766   *         FIFO mode feature is supported by the USARTx instance.
00767   * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
00768   *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
00769   * @param  USARTx USART Instance
00770   * @param  TXThreshold This parameter can be one of the following values:
00771   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00772   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00773   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00774   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00775   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00776   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00777   * @param  RXThreshold This parameter can be one of the following values:
00778   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00779   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00780   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00781   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00782   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00783   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00784   * @retval None
00785   */
00786 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00787 {
00788   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
00789 }
00790
00791 /**
00792   * @brief  USART enabled in STOP Mode.
00793   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00794   *         USART clock selection is HSI or LSE in RCC.
00795   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00796   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00797   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00798   * @param  USARTx USART Instance
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00802 {
00803   SET_BIT(USARTx->CR1, USART_CR1_UESM);
00804 }
00805
00806 /**
00807   * @brief  USART disabled in STOP Mode.
00808   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00809   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00810   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00811   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00812   * @param  USARTx USART Instance
00813   * @retval None
00814   */
00815 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00816 {
00817   CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00818 }
00819
00820 /**
00821   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00822   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00823   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00824   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00825   * @param  USARTx USART Instance
00826   * @retval State of bit (1 or 0).
00827   */
00828 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
00829 {
00830   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00831 }
00832
00833 /**
00834   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00835   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00836   * @param  USARTx USART Instance
00837   * @retval None
00838   */
00839 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00840 {
00841   SET_BIT(USARTx->CR1, USART_CR1_RE);
00842 }
00843
00844 /**
00845   * @brief  Receiver Disable
00846   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00847   * @param  USARTx USART Instance
00848   * @retval None
00849   */
00850 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00851 {
00852   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00853 }
00854
00855 /**
00856   * @brief  Transmitter Enable
00857   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00858   * @param  USARTx USART Instance
00859   * @retval None
00860   */
00861 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00862 {
00863   SET_BIT(USARTx->CR1, USART_CR1_TE);
00864 }
00865
00866 /**
00867   * @brief  Transmitter Disable
00868   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00869   * @param  USARTx USART Instance
00870   * @retval None
00871   */
00872 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00873 {
00874   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00875 }
00876
00877 /**
00878   * @brief  Configure simultaneously enabled/disabled states
00879   *         of Transmitter and Receiver
00880   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00881   *         CR1          TE            LL_USART_SetTransferDirection
00882   * @param  USARTx USART Instance
00883   * @param  TransferDirection This parameter can be one of the following values:
00884   *         @arg @ref LL_USART_DIRECTION_NONE
00885   *         @arg @ref LL_USART_DIRECTION_RX
00886   *         @arg @ref LL_USART_DIRECTION_TX
00887   *         @arg @ref LL_USART_DIRECTION_TX_RX
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00891 {
00892   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00893 }
00894
00895 /**
00896   * @brief  Return enabled/disabled states of Transmitter and Receiver
00897   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00898   *         CR1          TE            LL_USART_GetTransferDirection
00899   * @param  USARTx USART Instance
00900   * @retval Returned value can be one of the following values:
00901   *         @arg @ref LL_USART_DIRECTION_NONE
00902   *         @arg @ref LL_USART_DIRECTION_RX
00903   *         @arg @ref LL_USART_DIRECTION_TX
00904   *         @arg @ref LL_USART_DIRECTION_TX_RX
00905   */
00906 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00907 {
00908   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00909 }
00910
00911 /**
00912   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00913   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00914   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00915   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00916   * @rmtoll CR1          PS            LL_USART_SetParity\n
00917   *         CR1          PCE           LL_USART_SetParity
00918   * @param  USARTx USART Instance
00919   * @param  Parity This parameter can be one of the following values:
00920   *         @arg @ref LL_USART_PARITY_NONE
00921   *         @arg @ref LL_USART_PARITY_EVEN
00922   *         @arg @ref LL_USART_PARITY_ODD
00923   * @retval None
00924   */
00925 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00926 {
00927   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00928 }
00929
00930 /**
00931   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00932   * @rmtoll CR1          PS            LL_USART_GetParity\n
00933   *         CR1          PCE           LL_USART_GetParity
00934   * @param  USARTx USART Instance
00935   * @retval Returned value can be one of the following values:
00936   *         @arg @ref LL_USART_PARITY_NONE
00937   *         @arg @ref LL_USART_PARITY_EVEN
00938   *         @arg @ref LL_USART_PARITY_ODD
00939   */
00940 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00941 {
00942   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00943 }
00944
00945 /**
00946   * @brief  Set Receiver Wake Up method from Mute mode.
00947   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00948   * @param  USARTx USART Instance
00949   * @param  Method This parameter can be one of the following values:
00950   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00951   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00955 {
00956   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00957 }
00958
00959 /**
00960   * @brief  Return Receiver Wake Up method from Mute mode
00961   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00962   * @param  USARTx USART Instance
00963   * @retval Returned value can be one of the following values:
00964   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00965   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00966   */
00967 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00968 {
00969   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00970 }
00971
00972 /**
00973   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00974   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00975   *         CR1          M1            LL_USART_SetDataWidth
00976   * @param  USARTx USART Instance
00977   * @param  DataWidth This parameter can be one of the following values:
00978   *         @arg @ref LL_USART_DATAWIDTH_7B
00979   *         @arg @ref LL_USART_DATAWIDTH_8B
00980   *         @arg @ref LL_USART_DATAWIDTH_9B
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00984 {
00985   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00986 }
00987
00988 /**
00989   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00990   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
00991   *         CR1          M1            LL_USART_GetDataWidth
00992   * @param  USARTx USART Instance
00993   * @retval Returned value can be one of the following values:
00994   *         @arg @ref LL_USART_DATAWIDTH_7B
00995   *         @arg @ref LL_USART_DATAWIDTH_8B
00996   *         @arg @ref LL_USART_DATAWIDTH_9B
00997   */
00998 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
00999 {
01000   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
01001 }
01002
01003 /**
01004   * @brief  Allow switch between Mute Mode and Active mode
01005   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
01006   * @param  USARTx USART Instance
01007   * @retval None
01008   */
01009 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
01010 {
01011   SET_BIT(USARTx->CR1, USART_CR1_MME);
01012 }
01013
01014 /**
01015   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
01016   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
01017   * @param  USARTx USART Instance
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
01021 {
01022   CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
01023 }
01024
01025 /**
01026   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
01027   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
01028   * @param  USARTx USART Instance
01029   * @retval State of bit (1 or 0).
01030   */
01031 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
01032 {
01033   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
01034 }
01035
01036 /**
01037   * @brief  Set Oversampling to 8-bit or 16-bit mode
01038   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
01039   * @param  USARTx USART Instance
01040   * @param  OverSampling This parameter can be one of the following values:
01041   *         @arg @ref LL_USART_OVERSAMPLING_16
01042   *         @arg @ref LL_USART_OVERSAMPLING_8
01043   * @retval None
01044   */
01045 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
01046 {
01047   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
01048 }
01049
01050 /**
01051   * @brief  Return Oversampling mode
01052   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
01053   * @param  USARTx USART Instance
01054   * @retval Returned value can be one of the following values:
01055   *         @arg @ref LL_USART_OVERSAMPLING_16
01056   *         @arg @ref LL_USART_OVERSAMPLING_8
01057   */
01058 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
01059 {
01060   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
01061 }
01062
01063 /**
01064   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
01065   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01066   *         Synchronous mode is supported by the USARTx instance.
01067   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
01068   * @param  USARTx USART Instance
01069   * @param  LastBitClockPulse This parameter can be one of the following values:
01070   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01071   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01072   * @retval None
01073   */
01074 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
01075 {
01076   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
01077 }
01078
01079 /**
01080   * @brief  Retrieve Clock pulse of the last data bit output configuration
01081   *         (Last bit Clock pulse output to the SCLK pin or not)
01082   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01083   *         Synchronous mode is supported by the USARTx instance.
01084   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
01085   * @param  USARTx USART Instance
01086   * @retval Returned value can be one of the following values:
01087   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01088   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01089   */
01090 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
01091 {
01092   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
01093 }
01094
01095 /**
01096   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
01097   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01098   *         Synchronous mode is supported by the USARTx instance.
01099   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
01100   * @param  USARTx USART Instance
01101   * @param  ClockPhase This parameter can be one of the following values:
01102   *         @arg @ref LL_USART_PHASE_1EDGE
01103   *         @arg @ref LL_USART_PHASE_2EDGE
01104   * @retval None
01105   */
01106 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
01107 {
01108   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
01109 }
01110
01111 /**
01112   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
01113   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01114   *         Synchronous mode is supported by the USARTx instance.
01115   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
01116   * @param  USARTx USART Instance
01117   * @retval Returned value can be one of the following values:
01118   *         @arg @ref LL_USART_PHASE_1EDGE
01119   *         @arg @ref LL_USART_PHASE_2EDGE
01120   */
01121 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
01122 {
01123   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
01124 }
01125
01126 /**
01127   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
01128   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01129   *         Synchronous mode is supported by the USARTx instance.
01130   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
01131   * @param  USARTx USART Instance
01132   * @param  ClockPolarity This parameter can be one of the following values:
01133   *         @arg @ref LL_USART_POLARITY_LOW
01134   *         @arg @ref LL_USART_POLARITY_HIGH
01135   * @retval None
01136   */
01137 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
01138 {
01139   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
01140 }
01141
01142 /**
01143   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
01144   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01145   *         Synchronous mode is supported by the USARTx instance.
01146   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
01147   * @param  USARTx USART Instance
01148   * @retval Returned value can be one of the following values:
01149   *         @arg @ref LL_USART_POLARITY_LOW
01150   *         @arg @ref LL_USART_POLARITY_HIGH
01151   */
01152 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
01153 {
01154   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
01155 }
01156
01157 /**
01158   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
01159   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01160   *         Synchronous mode is supported by the USARTx instance.
01161   * @note   Call of this function is equivalent to following function call sequence :
01162   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
01163   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
01164   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
01165   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
01166   *         CR2          CPOL          LL_USART_ConfigClock\n
01167   *         CR2          LBCL          LL_USART_ConfigClock
01168   * @param  USARTx USART Instance
01169   * @param  Phase This parameter can be one of the following values:
01170   *         @arg @ref LL_USART_PHASE_1EDGE
01171   *         @arg @ref LL_USART_PHASE_2EDGE
01172   * @param  Polarity This parameter can be one of the following values:
01173   *         @arg @ref LL_USART_POLARITY_LOW
01174   *         @arg @ref LL_USART_POLARITY_HIGH
01175   * @param  LBCPOutput This parameter can be one of the following values:
01176   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01177   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01178   * @retval None
01179   */
01180 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
01181 {
01182   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
01183 }
01184
01185 /**
01186   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
01187   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01188   *         FIFO mode feature is supported by the USARTx instance.
01189   * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
01190   * @param  USARTx USART Instance
01191   * @param  PrescalerValue This parameter can be one of the following values:
01192   *         @arg @ref LL_USART_PRESCALER_DIV1
01193   *         @arg @ref LL_USART_PRESCALER_DIV2
01194   *         @arg @ref LL_USART_PRESCALER_DIV4
01195   *         @arg @ref LL_USART_PRESCALER_DIV6
01196   *         @arg @ref LL_USART_PRESCALER_DIV8
01197   *         @arg @ref LL_USART_PRESCALER_DIV10
01198   *         @arg @ref LL_USART_PRESCALER_DIV12
01199   *         @arg @ref LL_USART_PRESCALER_DIV16
01200   *         @arg @ref LL_USART_PRESCALER_DIV32
01201   *         @arg @ref LL_USART_PRESCALER_DIV64
01202   *         @arg @ref LL_USART_PRESCALER_DIV128
01203   *         @arg @ref LL_USART_PRESCALER_DIV256
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01207 {
01208   MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
01209 }
01210
01211 /**
01212   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
01213   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01214   *         FIFO mode feature is supported by the USARTx instance.
01215   * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
01216   * @param  USARTx USART Instance
01217   * @retval Returned value can be one of the following values:
01218   *         @arg @ref LL_USART_PRESCALER_DIV1
01219   *         @arg @ref LL_USART_PRESCALER_DIV2
01220   *         @arg @ref LL_USART_PRESCALER_DIV4
01221   *         @arg @ref LL_USART_PRESCALER_DIV6
01222   *         @arg @ref LL_USART_PRESCALER_DIV8
01223   *         @arg @ref LL_USART_PRESCALER_DIV10
01224   *         @arg @ref LL_USART_PRESCALER_DIV12
01225   *         @arg @ref LL_USART_PRESCALER_DIV16
01226   *         @arg @ref LL_USART_PRESCALER_DIV32
01227   *         @arg @ref LL_USART_PRESCALER_DIV64
01228   *         @arg @ref LL_USART_PRESCALER_DIV128
01229   *         @arg @ref LL_USART_PRESCALER_DIV256
01230   */
01231 __STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
01232 {
01233   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
01234 }
01235
01236 /**
01237   * @brief  Enable Clock output on SCLK pin
01238   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01239   *         Synchronous mode is supported by the USARTx instance.
01240   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
01241   * @param  USARTx USART Instance
01242   * @retval None
01243   */
01244 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
01245 {
01246   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01247 }
01248
01249 /**
01250   * @brief  Disable Clock output on SCLK pin
01251   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01252   *         Synchronous mode is supported by the USARTx instance.
01253   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
01254   * @param  USARTx USART Instance
01255   * @retval None
01256   */
01257 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01258 {
01259   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01260 }
01261
01262 /**
01263   * @brief  Indicate if Clock output on SCLK pin is enabled
01264   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01265   *         Synchronous mode is supported by the USARTx instance.
01266   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01267   * @param  USARTx USART Instance
01268   * @retval State of bit (1 or 0).
01269   */
01270 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
01271 {
01272   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
01273 }
01274
01275 /**
01276   * @brief  Set the length of the stop bits
01277   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01278   * @param  USARTx USART Instance
01279   * @param  StopBits This parameter can be one of the following values:
01280   *         @arg @ref LL_USART_STOPBITS_0_5
01281   *         @arg @ref LL_USART_STOPBITS_1
01282   *         @arg @ref LL_USART_STOPBITS_1_5
01283   *         @arg @ref LL_USART_STOPBITS_2
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01287 {
01288   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01289 }
01290
01291 /**
01292   * @brief  Retrieve the length of the stop bits
01293   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01294   * @param  USARTx USART Instance
01295   * @retval Returned value can be one of the following values:
01296   *         @arg @ref LL_USART_STOPBITS_0_5
01297   *         @arg @ref LL_USART_STOPBITS_1
01298   *         @arg @ref LL_USART_STOPBITS_1_5
01299   *         @arg @ref LL_USART_STOPBITS_2
01300   */
01301 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
01302 {
01303   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01304 }
01305
01306 /**
01307   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01308   * @note   Call of this function is equivalent to following function call sequence :
01309   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01310   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01311   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01312   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01313   *         CR1          PCE           LL_USART_ConfigCharacter\n
01314   *         CR1          M0            LL_USART_ConfigCharacter\n
01315   *         CR1          M1            LL_USART_ConfigCharacter\n
01316   *         CR2          STOP          LL_USART_ConfigCharacter
01317   * @param  USARTx USART Instance
01318   * @param  DataWidth This parameter can be one of the following values:
01319   *         @arg @ref LL_USART_DATAWIDTH_7B
01320   *         @arg @ref LL_USART_DATAWIDTH_8B
01321   *         @arg @ref LL_USART_DATAWIDTH_9B
01322   * @param  Parity This parameter can be one of the following values:
01323   *         @arg @ref LL_USART_PARITY_NONE
01324   *         @arg @ref LL_USART_PARITY_EVEN
01325   *         @arg @ref LL_USART_PARITY_ODD
01326   * @param  StopBits This parameter can be one of the following values:
01327   *         @arg @ref LL_USART_STOPBITS_0_5
01328   *         @arg @ref LL_USART_STOPBITS_1
01329   *         @arg @ref LL_USART_STOPBITS_1_5
01330   *         @arg @ref LL_USART_STOPBITS_2
01331   * @retval None
01332   */
01333 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01334                                               uint32_t StopBits)
01335 {
01336   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01337   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01338 }
01339
01340 /**
01341   * @brief  Configure TX/RX pins swapping setting.
01342   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01343   * @param  USARTx USART Instance
01344   * @param  SwapConfig This parameter can be one of the following values:
01345   *         @arg @ref LL_USART_TXRX_STANDARD
01346   *         @arg @ref LL_USART_TXRX_SWAPPED
01347   * @retval None
01348   */
01349 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01350 {
01351   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01352 }
01353
01354 /**
01355   * @brief  Retrieve TX/RX pins swapping configuration.
01356   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01357   * @param  USARTx USART Instance
01358   * @retval Returned value can be one of the following values:
01359   *         @arg @ref LL_USART_TXRX_STANDARD
01360   *         @arg @ref LL_USART_TXRX_SWAPPED
01361   */
01362 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
01363 {
01364   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01365 }
01366
01367 /**
01368   * @brief  Configure RX pin active level logic
01369   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01370   * @param  USARTx USART Instance
01371   * @param  PinInvMethod This parameter can be one of the following values:
01372   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01373   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01374   * @retval None
01375   */
01376 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01377 {
01378   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01379 }
01380
01381 /**
01382   * @brief  Retrieve RX pin active level logic configuration
01383   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01384   * @param  USARTx USART Instance
01385   * @retval Returned value can be one of the following values:
01386   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01387   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01388   */
01389 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
01390 {
01391   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01392 }
01393
01394 /**
01395   * @brief  Configure TX pin active level logic
01396   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01397   * @param  USARTx USART Instance
01398   * @param  PinInvMethod This parameter can be one of the following values:
01399   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01400   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01401   * @retval None
01402   */
01403 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01404 {
01405   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01406 }
01407
01408 /**
01409   * @brief  Retrieve TX pin active level logic configuration
01410   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01411   * @param  USARTx USART Instance
01412   * @retval Returned value can be one of the following values:
01413   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01414   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01415   */
01416 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
01417 {
01418   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01419 }
01420
01421 /**
01422   * @brief  Configure Binary data logic.
01423   * @note   Allow to define how Logical data from the data register are send/received :
01424   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01425   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01426   * @param  USARTx USART Instance
01427   * @param  DataLogic This parameter can be one of the following values:
01428   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01429   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01430   * @retval None
01431   */
01432 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01433 {
01434   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01435 }
01436
01437 /**
01438   * @brief  Retrieve Binary data configuration
01439   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01440   * @param  USARTx USART Instance
01441   * @retval Returned value can be one of the following values:
01442   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01443   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01444   */
01445 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
01446 {
01447   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01448 }
01449
01450 /**
01451   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01452   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01453   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01454   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01455   * @param  USARTx USART Instance
01456   * @param  BitOrder This parameter can be one of the following values:
01457   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01458   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01459   * @retval None
01460   */
01461 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01462 {
01463   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01464 }
01465
01466 /**
01467   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01468   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01469   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01470   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01471   * @param  USARTx USART Instance
01472   * @retval Returned value can be one of the following values:
01473   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01474   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01475   */
01476 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
01477 {
01478   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01479 }
01480
01481 /**
01482   * @brief  Enable Auto Baud-Rate Detection
01483   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01484   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01485   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01486   * @param  USARTx USART Instance
01487   * @retval None
01488   */
01489 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01490 {
01491   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01492 }
01493
01494 /**
01495   * @brief  Disable Auto Baud-Rate Detection
01496   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01497   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01498   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01499   * @param  USARTx USART Instance
01500   * @retval None
01501   */
01502 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01503 {
01504   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01505 }
01506
01507 /**
01508   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01509   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01510   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01511   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01512   * @param  USARTx USART Instance
01513   * @retval State of bit (1 or 0).
01514   */
01515 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
01516 {
01517   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
01518 }
01519
01520 /**
01521   * @brief  Set Auto Baud-Rate mode bits
01522   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01523   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01524   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01525   * @param  USARTx USART Instance
01526   * @param  AutoBaudRateMode This parameter can be one of the following values:
01527   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01528   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01529   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01530   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01531   * @retval None
01532   */
01533 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01534 {
01535   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01536 }
01537
01538 /**
01539   * @brief  Return Auto Baud-Rate mode
01540   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01541   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01542   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01543   * @param  USARTx USART Instance
01544   * @retval Returned value can be one of the following values:
01545   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01546   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01547   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01548   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01549   */
01550 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01551 {
01552   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01553 }
01554
01555 /**
01556   * @brief  Enable Receiver Timeout
01557   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01558   * @param  USARTx USART Instance
01559   * @retval None
01560   */
01561 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01562 {
01563   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01564 }
01565
01566 /**
01567   * @brief  Disable Receiver Timeout
01568   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01569   * @param  USARTx USART Instance
01570   * @retval None
01571   */
01572 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01573 {
01574   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01575 }
01576
01577 /**
01578   * @brief  Indicate if Receiver Timeout feature is enabled
01579   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01580   * @param  USARTx USART Instance
01581   * @retval State of bit (1 or 0).
01582   */
01583 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
01584 {
01585   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
01586 }
01587
01588 /**
01589   * @brief  Set Address of the USART node.
01590   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01591   *         for wake up with address mark detection.
01592   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01593   *         (b7-b4 should be set to 0)
01594   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01595   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01596   *         for wake up with 7-bit address mark detection.
01597   *         The MSB of the character sent by the transmitter should be equal to 1.
01598   *         It may also be used for character detection during normal reception,
01599   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01600   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01601   *         value and CMF flag is set on match)
01602   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01603   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01604   * @param  USARTx USART Instance
01605   * @param  AddressLen This parameter can be one of the following values:
01606   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01607   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01608   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01609   * @retval None
01610   */
01611 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01612 {
01613   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01614              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01615 }
01616
01617 /**
01618   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01619   * @note   If 4-bit Address Detection is selected in ADDM7,
01620   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01621   *         If 7-bit Address Detection is selected in ADDM7,
01622   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01623   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01624   * @param  USARTx USART Instance
01625   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01626   */
01627 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
01628 {
01629   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01630 }
01631
01632 /**
01633   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01634   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01635   * @param  USARTx USART Instance
01636   * @retval Returned value can be one of the following values:
01637   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01638   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01639   */
01640 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
01641 {
01642   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01643 }
01644
01645 /**
01646   * @brief  Enable RTS HW Flow Control
01647   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01648   *         Hardware Flow control feature is supported by the USARTx instance.
01649   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01650   * @param  USARTx USART Instance
01651   * @retval None
01652   */
01653 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01654 {
01655   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01656 }
01657
01658 /**
01659   * @brief  Disable RTS HW Flow Control
01660   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01661   *         Hardware Flow control feature is supported by the USARTx instance.
01662   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01663   * @param  USARTx USART Instance
01664   * @retval None
01665   */
01666 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01667 {
01668   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01669 }
01670
01671 /**
01672   * @brief  Enable CTS HW Flow Control
01673   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01674   *         Hardware Flow control feature is supported by the USARTx instance.
01675   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01676   * @param  USARTx USART Instance
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01680 {
01681   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01682 }
01683
01684 /**
01685   * @brief  Disable CTS HW Flow Control
01686   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01687   *         Hardware Flow control feature is supported by the USARTx instance.
01688   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01689   * @param  USARTx USART Instance
01690   * @retval None
01691   */
01692 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01693 {
01694   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01695 }
01696
01697 /**
01698   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01699   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01700   *         Hardware Flow control feature is supported by the USARTx instance.
01701   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01702   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01703   * @param  USARTx USART Instance
01704   * @param  HardwareFlowControl This parameter can be one of the following values:
01705   *         @arg @ref LL_USART_HWCONTROL_NONE
01706   *         @arg @ref LL_USART_HWCONTROL_RTS
01707   *         @arg @ref LL_USART_HWCONTROL_CTS
01708   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01712 {
01713   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01714 }
01715
01716 /**
01717   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01718   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01719   *         Hardware Flow control feature is supported by the USARTx instance.
01720   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01721   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01722   * @param  USARTx USART Instance
01723   * @retval Returned value can be one of the following values:
01724   *         @arg @ref LL_USART_HWCONTROL_NONE
01725   *         @arg @ref LL_USART_HWCONTROL_RTS
01726   *         @arg @ref LL_USART_HWCONTROL_CTS
01727   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01728   */
01729 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
01730 {
01731   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01732 }
01733
01734 /**
01735   * @brief  Enable One bit sampling method
01736   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01737   * @param  USARTx USART Instance
01738   * @retval None
01739   */
01740 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01741 {
01742   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01743 }
01744
01745 /**
01746   * @brief  Disable One bit sampling method
01747   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01748   * @param  USARTx USART Instance
01749   * @retval None
01750   */
01751 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01752 {
01753   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01754 }
01755
01756 /**
01757   * @brief  Indicate if One bit sampling method is enabled
01758   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01759   * @param  USARTx USART Instance
01760   * @retval State of bit (1 or 0).
01761   */
01762 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01763 {
01764   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
01765 }
01766
01767 /**
01768   * @brief  Enable Overrun detection
01769   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01770   * @param  USARTx USART Instance
01771   * @retval None
01772   */
01773 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01774 {
01775   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01776 }
01777
01778 /**
01779   * @brief  Disable Overrun detection
01780   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01781   * @param  USARTx USART Instance
01782   * @retval None
01783   */
01784 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01785 {
01786   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01787 }
01788
01789 /**
01790   * @brief  Indicate if Overrun detection is enabled
01791   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01792   * @param  USARTx USART Instance
01793   * @retval State of bit (1 or 0).
01794   */
01795 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
01796 {
01797   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01798 }
01799
01800 /**
01801   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01802   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01803   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01804   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01805   * @param  USARTx USART Instance
01806   * @param  Type This parameter can be one of the following values:
01807   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01808   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01809   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01810   * @retval None
01811   */
01812 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01813 {
01814   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01815 }
01816
01817 /**
01818   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01819   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01820   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01821   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01822   * @param  USARTx USART Instance
01823   * @retval Returned value can be one of the following values:
01824   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01825   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01826   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01827   */
01828 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
01829 {
01830   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01831 }
01832
01833 /**
01834   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01835   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01836   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01837   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01838   *         (Baud rate value != 0)
01839   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01840   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01841   * @param  USARTx USART Instance
01842   * @param  PeriphClk Peripheral Clock
01843   * @param  PrescalerValue This parameter can be one of the following values:
01844   *         @arg @ref LL_USART_PRESCALER_DIV1
01845   *         @arg @ref LL_USART_PRESCALER_DIV2
01846   *         @arg @ref LL_USART_PRESCALER_DIV4
01847   *         @arg @ref LL_USART_PRESCALER_DIV6
01848   *         @arg @ref LL_USART_PRESCALER_DIV8
01849   *         @arg @ref LL_USART_PRESCALER_DIV10
01850   *         @arg @ref LL_USART_PRESCALER_DIV12
01851   *         @arg @ref LL_USART_PRESCALER_DIV16
01852   *         @arg @ref LL_USART_PRESCALER_DIV32
01853   *         @arg @ref LL_USART_PRESCALER_DIV64
01854   *         @arg @ref LL_USART_PRESCALER_DIV128
01855   *         @arg @ref LL_USART_PRESCALER_DIV256
01856   * @param  OverSampling This parameter can be one of the following values:
01857   *         @arg @ref LL_USART_OVERSAMPLING_16
01858   *         @arg @ref LL_USART_OVERSAMPLING_8
01859   * @param  BaudRate Baud Rate
01860   * @retval None
01861   */
01862 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01863                                           uint32_t OverSampling,
01864                                           uint32_t BaudRate)
01865 {
01866   uint32_t usartdiv;
01867   register uint32_t brrtemp;
01868
01869   if (PrescalerValue > LL_USART_PRESCALER_DIV256)
01870   {
01871     /* Do not overstep the size of USART_PRESCALER_TAB */
01872   }
01873   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01874   {
01875     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01876     brrtemp = usartdiv & 0xFFF0U;
01877     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01878     USARTx->BRR = brrtemp;
01879   }
01880   else
01881   {
01882     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01883   }
01884 }
01885
01886 /**
01887   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01888   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01889   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01890   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01891   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01892   * @param  USARTx USART Instance
01893   * @param  PeriphClk Peripheral Clock
01894   * @param  PrescalerValue This parameter can be one of the following values:
01895   *         @arg @ref LL_USART_PRESCALER_DIV1
01896   *         @arg @ref LL_USART_PRESCALER_DIV2
01897   *         @arg @ref LL_USART_PRESCALER_DIV4
01898   *         @arg @ref LL_USART_PRESCALER_DIV6
01899   *         @arg @ref LL_USART_PRESCALER_DIV8
01900   *         @arg @ref LL_USART_PRESCALER_DIV10
01901   *         @arg @ref LL_USART_PRESCALER_DIV12
01902   *         @arg @ref LL_USART_PRESCALER_DIV16
01903   *         @arg @ref LL_USART_PRESCALER_DIV32
01904   *         @arg @ref LL_USART_PRESCALER_DIV64
01905   *         @arg @ref LL_USART_PRESCALER_DIV128
01906   *         @arg @ref LL_USART_PRESCALER_DIV256
01907   * @param  OverSampling This parameter can be one of the following values:
01908   *         @arg @ref LL_USART_OVERSAMPLING_16
01909   *         @arg @ref LL_USART_OVERSAMPLING_8
01910   * @retval Baud Rate
01911   */
01912 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01913                                               uint32_t OverSampling)
01914 {
01915   register uint32_t usartdiv;
01916   register uint32_t brrresult = 0x0U;
01917   register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
01918
01919   usartdiv = USARTx->BRR;
01920
01921   if (usartdiv == 0U)
01922   {
01923     /* Do not perform a division by 0 */
01924   }
01925   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01926   {
01927     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01928     if (usartdiv != 0U)
01929     {
01930       brrresult = (periphclkpresc * 2U) / usartdiv;
01931     }
01932   }
01933   else
01934   {
01935     if ((usartdiv & 0xFFFFU) != 0U)
01936     {
01937       brrresult = periphclkpresc / usartdiv;
01938     }
01939   }
01940   return (brrresult);
01941 }
01942
01943 /**
01944   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01945   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01946   * @param  USARTx USART Instance
01947   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01948   * @retval None
01949   */
01950 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01951 {
01952   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01953 }
01954
01955 /**
01956   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01957   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01958   * @param  USARTx USART Instance
01959   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01960   */
01961 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
01962 {
01963   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01964 }
01965
01966 /**
01967   * @brief  Set Block Length value in reception
01968   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01969   * @param  USARTx USART Instance
01970   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01974 {
01975   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01976 }
01977
01978 /**
01979   * @brief  Get Block Length value in reception
01980   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01981   * @param  USARTx USART Instance
01982   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01983   */
01984 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
01985 {
01986   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
01987 }
01988
01989 /**
01990   * @}
01991   */
01992
01993 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01994   * @{
01995   */
01996
01997 /**
01998   * @brief  Enable IrDA mode
01999   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02000   *         IrDA feature is supported by the USARTx instance.
02001   * @rmtoll CR3          IREN          LL_USART_EnableIrda
02002   * @param  USARTx USART Instance
02003   * @retval None
02004   */
02005 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
02006 {
02007   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02008 }
02009
02010 /**
02011   * @brief  Disable IrDA mode
02012   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02013   *         IrDA feature is supported by the USARTx instance.
02014   * @rmtoll CR3          IREN          LL_USART_DisableIrda
02015   * @param  USARTx USART Instance
02016   * @retval None
02017   */
02018 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
02019 {
02020   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
02021 }
02022
02023 /**
02024   * @brief  Indicate if IrDA mode is enabled
02025   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02026   *         IrDA feature is supported by the USARTx instance.
02027   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
02028   * @param  USARTx USART Instance
02029   * @retval State of bit (1 or 0).
02030   */
02031 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
02032 {
02033   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
02034 }
02035
02036 /**
02037   * @brief  Configure IrDA Power Mode (Normal or Low Power)
02038   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02039   *         IrDA feature is supported by the USARTx instance.
02040   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
02041   * @param  USARTx USART Instance
02042   * @param  PowerMode This parameter can be one of the following values:
02043   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02044   *         @arg @ref LL_USART_IRDA_POWER_LOW
02045   * @retval None
02046   */
02047 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
02048 {
02049   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
02050 }
02051
02052 /**
02053   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
02054   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02055   *         IrDA feature is supported by the USARTx instance.
02056   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
02057   * @param  USARTx USART Instance
02058   * @retval Returned value can be one of the following values:
02059   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02060   *         @arg @ref LL_USART_PHASE_2EDGE
02061   */
02062 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
02063 {
02064   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
02065 }
02066
02067 /**
02068   * @brief  Set Irda prescaler value, used for dividing the USART clock source
02069   *         to achieve the Irda Low Power frequency (8 bits value)
02070   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02071   *         IrDA feature is supported by the USARTx instance.
02072   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
02073   * @param  USARTx USART Instance
02074   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
02075   * @retval None
02076   */
02077 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02078 {
02079   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
02080 }
02081
02082 /**
02083   * @brief  Return Irda prescaler value, used for dividing the USART clock source
02084   *         to achieve the Irda Low Power frequency (8 bits value)
02085   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02086   *         IrDA feature is supported by the USARTx instance.
02087   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
02088   * @param  USARTx USART Instance
02089   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
02090   */
02091 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
02092 {
02093   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02094 }
02095
02096 /**
02097   * @}
02098   */
02099
02100 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
02101   * @{
02102   */
02103
02104 /**
02105   * @brief  Enable Smartcard NACK transmission
02106   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02107   *         Smartcard feature is supported by the USARTx instance.
02108   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
02109   * @param  USARTx USART Instance
02110   * @retval None
02111   */
02112 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
02113 {
02114   SET_BIT(USARTx->CR3, USART_CR3_NACK);
02115 }
02116
02117 /**
02118   * @brief  Disable Smartcard NACK transmission
02119   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02120   *         Smartcard feature is supported by the USARTx instance.
02121   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
02122   * @param  USARTx USART Instance
02123   * @retval None
02124   */
02125 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
02126 {
02127   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
02128 }
02129
02130 /**
02131   * @brief  Indicate if Smartcard NACK transmission is enabled
02132   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02133   *         Smartcard feature is supported by the USARTx instance.
02134   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
02135   * @param  USARTx USART Instance
02136   * @retval State of bit (1 or 0).
02137   */
02138 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
02139 {
02140   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
02141 }
02142
02143 /**
02144   * @brief  Enable Smartcard mode
02145   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02146   *         Smartcard feature is supported by the USARTx instance.
02147   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
02148   * @param  USARTx USART Instance
02149   * @retval None
02150   */
02151 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
02152 {
02153   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02154 }
02155
02156 /**
02157   * @brief  Disable Smartcard mode
02158   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02159   *         Smartcard feature is supported by the USARTx instance.
02160   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
02161   * @param  USARTx USART Instance
02162   * @retval None
02163   */
02164 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
02165 {
02166   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
02167 }
02168
02169 /**
02170   * @brief  Indicate if Smartcard mode is enabled
02171   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02172   *         Smartcard feature is supported by the USARTx instance.
02173   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
02174   * @param  USARTx USART Instance
02175   * @retval State of bit (1 or 0).
02176   */
02177 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
02178 {
02179   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
02180 }
02181
02182 /**
02183   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02184   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02185   *         Smartcard feature is supported by the USARTx instance.
02186   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
02187   *         In transmission mode, it specifies the number of automatic retransmission retries, before
02188   *         generating a transmission error (FE bit set).
02189   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
02190   *         reception error (RXNE and PE bits set)
02191   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
02192   * @param  USARTx USART Instance
02193   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
02194   * @retval None
02195   */
02196 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
02197 {
02198   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
02199 }
02200
02201 /**
02202   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02203   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02204   *         Smartcard feature is supported by the USARTx instance.
02205   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
02206   * @param  USARTx USART Instance
02207   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
02208   */
02209 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
02210 {
02211   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
02212 }
02213
02214 /**
02215   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
02216   *         source to provide the SMARTCARD Clock (5 bits value)
02217   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02218   *         Smartcard feature is supported by the USARTx instance.
02219   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
02220   * @param  USARTx USART Instance
02221   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
02222   * @retval None
02223   */
02224 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02225 {
02226   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
02227 }
02228
02229 /**
02230   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
02231   *         source to provide the SMARTCARD Clock (5 bits value)
02232   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02233   *         Smartcard feature is supported by the USARTx instance.
02234   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
02235   * @param  USARTx USART Instance
02236   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
02237   */
02238 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
02239 {
02240   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02241 }
02242
02243 /**
02244   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
02245   *         (GT[7:0] bits : Guard time value)
02246   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02247   *         Smartcard feature is supported by the USARTx instance.
02248   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
02249   * @param  USARTx USART Instance
02250   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
02251   * @retval None
02252   */
02253 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
02254 {
02255   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
02256 }
02257
02258 /**
02259   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
02260   *         (GT[7:0] bits : Guard time value)
02261   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02262   *         Smartcard feature is supported by the USARTx instance.
02263   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
02264   * @param  USARTx USART Instance
02265   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
02266   */
02267 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
02268 {
02269   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
02270 }
02271
02272 /**
02273   * @}
02274   */
02275
02276 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
02277   * @{
02278   */
02279
02280 /**
02281   * @brief  Enable Single Wire Half-Duplex mode
02282   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02283   *         Half-Duplex mode is supported by the USARTx instance.
02284   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
02285   * @param  USARTx USART Instance
02286   * @retval None
02287   */
02288 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
02289 {
02290   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02291 }
02292
02293 /**
02294   * @brief  Disable Single Wire Half-Duplex mode
02295   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02296   *         Half-Duplex mode is supported by the USARTx instance.
02297   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02298   * @param  USARTx USART Instance
02299   * @retval None
02300   */
02301 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02302 {
02303   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02304 }
02305
02306 /**
02307   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02308   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02309   *         Half-Duplex mode is supported by the USARTx instance.
02310   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02311   * @param  USARTx USART Instance
02312   * @retval State of bit (1 or 0).
02313   */
02314 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
02315 {
02316   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
02317 }
02318
02319 /**
02320   * @}
02321   */
02322
02323 /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
02324   * @{
02325   */
02326 /**
02327   * @brief  Enable SPI Synchronous Slave mode
02328   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02329   *         SPI Slave mode feature is supported by the USARTx instance.
02330   * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
02331   * @param  USARTx USART Instance
02332   * @retval None
02333   */
02334 __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
02335 {
02336   SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
02337 }
02338
02339 /**
02340   * @brief  Disable SPI Synchronous Slave mode
02341   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02342   *         SPI Slave mode feature is supported by the USARTx instance.
02343   * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
02344   * @param  USARTx USART Instance
02345   * @retval None
02346   */
02347 __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
02348 {
02349   CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
02350 }
02351
02352 /**
02353   * @brief  Indicate if  SPI Synchronous Slave mode is enabled
02354   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02355   *         SPI Slave mode feature is supported by the USARTx instance.
02356   * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
02357   * @param  USARTx USART Instance
02358   * @retval State of bit (1 or 0).
02359   */
02360 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
02361 {
02362   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
02363 }
02364
02365 /**
02366   * @brief  Enable SPI Slave Selection using NSS input pin
02367   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02368   *         SPI Slave mode feature is supported by the USARTx instance.
02369   * @note   SPI Slave Selection depends on NSS input pin
02370   *         (The slave is selected when NSS is low and deselected when NSS is high).
02371   * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
02372   * @param  USARTx USART Instance
02373   * @retval None
02374   */
02375 __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
02376 {
02377   CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02378 }
02379
02380 /**
02381   * @brief  Disable SPI Slave Selection using NSS input pin
02382   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02383   *         SPI Slave mode feature is supported by the USARTx instance.
02384   * @note   SPI Slave will be always selected and NSS input pin will be ignored.
02385   * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
02386   * @param  USARTx USART Instance
02387   * @retval None
02388   */
02389 __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
02390 {
02391   SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02392 }
02393
02394 /**
02395   * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
02396   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02397   *         SPI Slave mode feature is supported by the USARTx instance.
02398   * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
02399   * @param  USARTx USART Instance
02400   * @retval State of bit (1 or 0).
02401   */
02402 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
02403 {
02404   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
02405 }
02406
02407 /**
02408   * @}
02409   */
02410
02411 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02412   * @{
02413   */
02414
02415 /**
02416   * @brief  Set LIN Break Detection Length
02417   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02418   *         LIN feature is supported by the USARTx instance.
02419   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02420   * @param  USARTx USART Instance
02421   * @param  LINBDLength This parameter can be one of the following values:
02422   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02423   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02424   * @retval None
02425   */
02426 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02427 {
02428   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02429 }
02430
02431 /**
02432   * @brief  Return LIN Break Detection Length
02433   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02434   *         LIN feature is supported by the USARTx instance.
02435   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02436   * @param  USARTx USART Instance
02437   * @retval Returned value can be one of the following values:
02438   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02439   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02440   */
02441 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
02442 {
02443   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02444 }
02445
02446 /**
02447   * @brief  Enable LIN mode
02448   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02449   *         LIN feature is supported by the USARTx instance.
02450   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02451   * @param  USARTx USART Instance
02452   * @retval None
02453   */
02454 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02455 {
02456   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02457 }
02458
02459 /**
02460   * @brief  Disable LIN mode
02461   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02462   *         LIN feature is supported by the USARTx instance.
02463   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02464   * @param  USARTx USART Instance
02465   * @retval None
02466   */
02467 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02468 {
02469   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02470 }
02471
02472 /**
02473   * @brief  Indicate if LIN mode is enabled
02474   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02475   *         LIN feature is supported by the USARTx instance.
02476   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02477   * @param  USARTx USART Instance
02478   * @retval State of bit (1 or 0).
02479   */
02480 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
02481 {
02482   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
02483 }
02484
02485 /**
02486   * @}
02487   */
02488
02489 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02490   * @{
02491   */
02492
02493 /**
02494   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02495   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02496   *         Driver Enable feature is supported by the USARTx instance.
02497   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02498   * @param  USARTx USART Instance
02499   * @param  Time Value between Min_Data=0 and Max_Data=31
02500   * @retval None
02501   */
02502 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02503 {
02504   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02505 }
02506
02507 /**
02508   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02509   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02510   *         Driver Enable feature is supported by the USARTx instance.
02511   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02512   * @param  USARTx USART Instance
02513   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02514   */
02515 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
02516 {
02517   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02518 }
02519
02520 /**
02521   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02522   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02523   *         Driver Enable feature is supported by the USARTx instance.
02524   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02525   * @param  USARTx USART Instance
02526   * @param  Time Value between Min_Data=0 and Max_Data=31
02527   * @retval None
02528   */
02529 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02530 {
02531   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02532 }
02533
02534 /**
02535   * @brief  Return DEAT (Driver Enable Assertion Time)
02536   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02537   *         Driver Enable feature is supported by the USARTx instance.
02538   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02539   * @param  USARTx USART Instance
02540   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02541   */
02542 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
02543 {
02544   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02545 }
02546
02547 /**
02548   * @brief  Enable Driver Enable (DE) Mode
02549   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02550   *         Driver Enable feature is supported by the USARTx instance.
02551   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02552   * @param  USARTx USART Instance
02553   * @retval None
02554   */
02555 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02556 {
02557   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02558 }
02559
02560 /**
02561   * @brief  Disable Driver Enable (DE) Mode
02562   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02563   *         Driver Enable feature is supported by the USARTx instance.
02564   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02565   * @param  USARTx USART Instance
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02569 {
02570   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02571 }
02572
02573 /**
02574   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02575   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02576   *         Driver Enable feature is supported by the USARTx instance.
02577   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02578   * @param  USARTx USART Instance
02579   * @retval State of bit (1 or 0).
02580   */
02581 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
02582 {
02583   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
02584 }
02585
02586 /**
02587   * @brief  Select Driver Enable Polarity
02588   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02589   *         Driver Enable feature is supported by the USARTx instance.
02590   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02591   * @param  USARTx USART Instance
02592   * @param  Polarity This parameter can be one of the following values:
02593   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02594   *         @arg @ref LL_USART_DE_POLARITY_LOW
02595   * @retval None
02596   */
02597 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02598 {
02599   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02600 }
02601
02602 /**
02603   * @brief  Return Driver Enable Polarity
02604   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02605   *         Driver Enable feature is supported by the USARTx instance.
02606   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02607   * @param  USARTx USART Instance
02608   * @retval Returned value can be one of the following values:
02609   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02610   *         @arg @ref LL_USART_DE_POLARITY_LOW
02611   */
02612 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
02613 {
02614   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02615 }
02616
02617 /**
02618   * @}
02619   */
02620
02621 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02622   * @{
02623   */
02624
02625 /**
02626   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02627   * @note   In UART mode, the following bits must be kept cleared:
02628   *           - LINEN bit in the USART_CR2 register,
02629   *           - CLKEN bit in the USART_CR2 register,
02630   *           - SCEN bit in the USART_CR3 register,
02631   *           - IREN bit in the USART_CR3 register,
02632   *           - HDSEL bit in the USART_CR3 register.
02633   * @note   Call of this function is equivalent to following function call sequence :
02634   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02635   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02636   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02637   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02638   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02639   * @note   Other remaining configurations items related to Asynchronous Mode
02640   *         (as Baud Rate, Word length, Parity, ...) should be set using
02641   *         dedicated functions
02642   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02643   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02644   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02645   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02646   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02647   * @param  USARTx USART Instance
02648   * @retval None
02649   */
02650 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02651 {
02652   /* In Asynchronous mode, the following bits must be kept cleared:
02653   - LINEN, CLKEN bits in the USART_CR2 register,
02654   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02655   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02656   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02657 }
02658
02659 /**
02660   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02661   * @note   In Synchronous mode, the following bits must be kept cleared:
02662   *           - LINEN bit in the USART_CR2 register,
02663   *           - SCEN bit in the USART_CR3 register,
02664   *           - IREN bit in the USART_CR3 register,
02665   *           - HDSEL bit in the USART_CR3 register.
02666   *         This function also sets the USART in Synchronous mode.
02667   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
02668   *         Synchronous mode is supported by the USARTx instance.
02669   * @note   Call of this function is equivalent to following function call sequence :
02670   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02671   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02672   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02673   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02674   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02675   * @note   Other remaining configurations items related to Synchronous Mode
02676   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02677   *         dedicated functions
02678   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02679   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02680   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02681   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02682   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02683   * @param  USARTx USART Instance
02684   * @retval None
02685   */
02686 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02687 {
02688   /* In Synchronous mode, the following bits must be kept cleared:
02689   - LINEN bit in the USART_CR2 register,
02690   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02691   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02692   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02693   /* set the UART/USART in Synchronous mode */
02694   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02695 }
02696
02697 /**
02698   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02699   * @note   In LIN mode, the following bits must be kept cleared:
02700   *           - STOP and CLKEN bits in the USART_CR2 register,
02701   *           - SCEN bit in the USART_CR3 register,
02702   *           - IREN bit in the USART_CR3 register,
02703   *           - HDSEL bit in the USART_CR3 register.
02704   *         This function also set the UART/USART in LIN mode.
02705   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02706   *         LIN feature is supported by the USARTx instance.
02707   * @note   Call of this function is equivalent to following function call sequence :
02708   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02709   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02710   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02711   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02712   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02713   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02714   * @note   Other remaining configurations items related to LIN Mode
02715   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02716   *         dedicated functions
02717   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02718   *         CR2          STOP          LL_USART_ConfigLINMode\n
02719   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02720   *         CR3          IREN          LL_USART_ConfigLINMode\n
02721   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02722   *         CR3          HDSEL         LL_USART_ConfigLINMode
02723   * @param  USARTx USART Instance
02724   * @retval None
02725   */
02726 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02727 {
02728   /* In LIN mode, the following bits must be kept cleared:
02729   - STOP and CLKEN bits in the USART_CR2 register,
02730   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02731   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02732   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02733   /* Set the UART/USART in LIN mode */
02734   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02735 }
02736
02737 /**
02738   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02739   * @note   In Half Duplex mode, the following bits must be kept cleared:
02740   *           - LINEN bit in the USART_CR2 register,
02741   *           - CLKEN bit in the USART_CR2 register,
02742   *           - SCEN bit in the USART_CR3 register,
02743   *           - IREN bit in the USART_CR3 register,
02744   *         This function also sets the UART/USART in Half Duplex mode.
02745   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02746   *         Half-Duplex mode is supported by the USARTx instance.
02747   * @note   Call of this function is equivalent to following function call sequence :
02748   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02749   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02750   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02751   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02752   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02753   * @note   Other remaining configurations items related to Half Duplex Mode
02754   *         (as Baud Rate, Word length, Parity, ...) should be set using
02755   *         dedicated functions
02756   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02757   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02758   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02759   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02760   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02761   * @param  USARTx USART Instance
02762   * @retval None
02763   */
02764 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02765 {
02766   /* In Half Duplex mode, the following bits must be kept cleared:
02767   - LINEN and CLKEN bits in the USART_CR2 register,
02768   - SCEN and IREN bits in the USART_CR3 register.*/
02769   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02770   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02771   /* set the UART/USART in Half Duplex mode */
02772   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02773 }
02774
02775 /**
02776   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02777   * @note   In Smartcard mode, the following bits must be kept cleared:
02778   *           - LINEN bit in the USART_CR2 register,
02779   *           - IREN bit in the USART_CR3 register,
02780   *           - HDSEL bit in the USART_CR3 register.
02781   *         This function also configures Stop bits to 1.5 bits and
02782   *         sets the USART in Smartcard mode (SCEN bit).
02783   *         Clock Output is also enabled (CLKEN).
02784   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02785   *         Smartcard feature is supported by the USARTx instance.
02786   * @note   Call of this function is equivalent to following function call sequence :
02787   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02788   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02789   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02790   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02791   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02792   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02793   * @note   Other remaining configurations items related to Smartcard Mode
02794   *         (as Baud Rate, Word length, Parity, ...) should be set using
02795   *         dedicated functions
02796   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02797   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02798   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02799   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02800   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02801   * @param  USARTx USART Instance
02802   * @retval None
02803   */
02804 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02805 {
02806   /* In Smartcard mode, the following bits must be kept cleared:
02807   - LINEN bit in the USART_CR2 register,
02808   - IREN and HDSEL bits in the USART_CR3 register.*/
02809   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02810   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02811   /* Configure Stop bits to 1.5 bits */
02812   /* Synchronous mode is activated by default */
02813   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02814   /* set the UART/USART in Smartcard mode */
02815   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02816 }
02817
02818 /**
02819   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02820   * @note   In IRDA mode, the following bits must be kept cleared:
02821   *           - LINEN bit in the USART_CR2 register,
02822   *           - STOP and CLKEN bits in the USART_CR2 register,
02823   *           - SCEN bit in the USART_CR3 register,
02824   *           - HDSEL bit in the USART_CR3 register.
02825   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02826   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02827   *         IrDA feature is supported by the USARTx instance.
02828   * @note   Call of this function is equivalent to following function call sequence :
02829   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02830   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02831   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02832   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02833   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02834   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02835   * @note   Other remaining configurations items related to Irda Mode
02836   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02837   *         dedicated functions
02838   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02839   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02840   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02841   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02842   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02843   *         CR3          IREN          LL_USART_ConfigIrdaMode
02844   * @param  USARTx USART Instance
02845   * @retval None
02846   */
02847 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02848 {
02849   /* In IRDA mode, the following bits must be kept cleared:
02850   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02851   - SCEN and HDSEL bits in the USART_CR3 register.*/
02852   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02853   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02854   /* set the UART/USART in IRDA mode */
02855   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02856 }
02857
02858 /**
02859   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02860   *         (several USARTs connected in a network, one of the USARTs can be the master,
02861   *         its TX output connected to the RX inputs of the other slaves USARTs).
02862   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02863   *           - LINEN bit in the USART_CR2 register,
02864   *           - CLKEN bit in the USART_CR2 register,
02865   *           - SCEN bit in the USART_CR3 register,
02866   *           - IREN bit in the USART_CR3 register,
02867   *           - HDSEL bit in the USART_CR3 register.
02868   * @note   Call of this function is equivalent to following function call sequence :
02869   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02870   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02871   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02872   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02873   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02874   * @note   Other remaining configurations items related to Multi processor Mode
02875   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02876   *         dedicated functions
02877   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02878   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02879   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02880   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02881   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02882   * @param  USARTx USART Instance
02883   * @retval None
02884   */
02885 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02886 {
02887   /* In Multi Processor mode, the following bits must be kept cleared:
02888   - LINEN and CLKEN bits in the USART_CR2 register,
02889   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02890   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02891   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02892 }
02893
02894 /**
02895   * @}
02896   */
02897
02898 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02899   * @{
02900   */
02901
02902 /**
02903   * @brief  Check if the USART Parity Error Flag is set or not
02904   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02905   * @param  USARTx USART Instance
02906   * @retval State of bit (1 or 0).
02907   */
02908 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
02909 {
02910   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
02911 }
02912
02913 /**
02914   * @brief  Check if the USART Framing Error Flag is set or not
02915   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02916   * @param  USARTx USART Instance
02917   * @retval State of bit (1 or 0).
02918   */
02919 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
02920 {
02921   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
02922 }
02923
02924 /**
02925   * @brief  Check if the USART Noise error detected Flag is set or not
02926   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
02927   * @param  USARTx USART Instance
02928   * @retval State of bit (1 or 0).
02929   */
02930 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
02931 {
02932   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
02933 }
02934
02935 /**
02936   * @brief  Check if the USART OverRun Error Flag is set or not
02937   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02938   * @param  USARTx USART Instance
02939   * @retval State of bit (1 or 0).
02940   */
02941 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
02942 {
02943   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
02944 }
02945
02946 /**
02947   * @brief  Check if the USART IDLE line detected Flag is set or not
02948   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02949   * @param  USARTx USART Instance
02950   * @retval State of bit (1 or 0).
02951   */
02952 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
02953 {
02954   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
02955 }
02956
02957 /* Legacy define */
02958 #define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
02959
02960 /**
02961   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
02962   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02963   *         FIFO mode feature is supported by the USARTx instance.
02964   * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
02965   * @param  USARTx USART Instance
02966   * @retval State of bit (1 or 0).
02967   */
02968 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
02969 {
02970   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
02971 }
02972
02973 /**
02974   * @brief  Check if the USART Transmission Complete Flag is set or not
02975   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
02976   * @param  USARTx USART Instance
02977   * @retval State of bit (1 or 0).
02978   */
02979 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
02980 {
02981   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
02982 }
02983
02984 /* Legacy define */
02985 #define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
02986
02987 /**
02988   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
02989   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02990   *         FIFO mode feature is supported by the USARTx instance.
02991   * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
02992   * @param  USARTx USART Instance
02993   * @retval State of bit (1 or 0).
02994   */
02995 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
02996 {
02997   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
02998 }
02999
03000 /**
03001   * @brief  Check if the USART LIN Break Detection Flag is set or not
03002   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03003   *         LIN feature is supported by the USARTx instance.
03004   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
03005   * @param  USARTx USART Instance
03006   * @retval State of bit (1 or 0).
03007   */
03008 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
03009 {
03010   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
03011 }
03012
03013 /**
03014   * @brief  Check if the USART CTS interrupt Flag is set or not
03015   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03016   *         Hardware Flow control feature is supported by the USARTx instance.
03017   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
03018   * @param  USARTx USART Instance
03019   * @retval State of bit (1 or 0).
03020   */
03021 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
03022 {
03023   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
03024 }
03025
03026 /**
03027   * @brief  Check if the USART CTS Flag is set or not
03028   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03029   *         Hardware Flow control feature is supported by the USARTx instance.
03030   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
03031   * @param  USARTx USART Instance
03032   * @retval State of bit (1 or 0).
03033   */
03034 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
03035 {
03036   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
03037 }
03038
03039 /**
03040   * @brief  Check if the USART Receiver Time Out Flag is set or not
03041   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
03042   * @param  USARTx USART Instance
03043   * @retval State of bit (1 or 0).
03044   */
03045 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
03046 {
03047   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
03048 }
03049
03050 /**
03051   * @brief  Check if the USART End Of Block Flag is set or not
03052   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03053   *         Smartcard feature is supported by the USARTx instance.
03054   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
03055   * @param  USARTx USART Instance
03056   * @retval State of bit (1 or 0).
03057   */
03058 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
03059 {
03060   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
03061 }
03062
03063 /**
03064   * @brief  Check if the SPI Slave Underrun error flag is set or not
03065   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03066   *         SPI Slave mode feature is supported by the USARTx instance.
03067   * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
03068   * @param  USARTx USART Instance
03069   * @retval State of bit (1 or 0).
03070   */
03071 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
03072 {
03073   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
03074 }
03075
03076 /**
03077   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
03078   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03079   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03080   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
03081   * @param  USARTx USART Instance
03082   * @retval State of bit (1 or 0).
03083   */
03084 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
03085 {
03086   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
03087 }
03088
03089 /**
03090   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
03091   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03092   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03093   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
03094   * @param  USARTx USART Instance
03095   * @retval State of bit (1 or 0).
03096   */
03097 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
03098 {
03099   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
03100 }
03101
03102 /**
03103   * @brief  Check if the USART Busy Flag is set or not
03104   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
03105   * @param  USARTx USART Instance
03106   * @retval State of bit (1 or 0).
03107   */
03108 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
03109 {
03110   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
03111 }
03112
03113 /**
03114   * @brief  Check if the USART Character Match Flag is set or not
03115   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
03116   * @param  USARTx USART Instance
03117   * @retval State of bit (1 or 0).
03118   */
03119 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
03120 {
03121   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
03122 }
03123
03124 /**
03125   * @brief  Check if the USART Send Break Flag is set or not
03126   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
03127   * @param  USARTx USART Instance
03128   * @retval State of bit (1 or 0).
03129   */
03130 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
03131 {
03132   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
03133 }
03134
03135 /**
03136   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
03137   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
03138   * @param  USARTx USART Instance
03139   * @retval State of bit (1 or 0).
03140   */
03141 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
03142 {
03143   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
03144 }
03145
03146 /**
03147   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
03148   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03149   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03150   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
03151   * @param  USARTx USART Instance
03152   * @retval State of bit (1 or 0).
03153   */
03154 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
03155 {
03156   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
03157 }
03158
03159 /**
03160   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
03161   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
03162   * @param  USARTx USART Instance
03163   * @retval State of bit (1 or 0).
03164   */
03165 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
03166 {
03167   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
03168 }
03169
03170 /**
03171   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
03172   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
03173   * @param  USARTx USART Instance
03174   * @retval State of bit (1 or 0).
03175   */
03176 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
03177 {
03178   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
03179 }
03180
03181 /**
03182   * @brief  Check if the USART TX FIFO Empty Flag is set or not
03183   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03184   *         FIFO mode feature is supported by the USARTx instance.
03185   * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
03186   * @param  USARTx USART Instance
03187   * @retval State of bit (1 or 0).
03188   */
03189 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
03190 {
03191   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
03192 }
03193
03194 /**
03195   * @brief  Check if the USART RX FIFO Full Flag is set or not
03196   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03197   *         FIFO mode feature is supported by the USARTx instance.
03198   * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
03199   * @param  USARTx USART Instance
03200   * @retval State of bit (1 or 0).
03201   */
03202 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
03203 {
03204   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
03205 }
03206
03207 /**
03208   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
03209   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
03210   * @param  USARTx USART Instance
03211   * @retval State of bit (1 or 0).
03212   */
03213 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
03214 {
03215   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
03216 }
03217
03218 /**
03219   * @brief  Check if the USART TX FIFO Threshold Flag is set or not
03220   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03221   *         FIFO mode feature is supported by the USARTx instance.
03222   * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
03223   * @param  USARTx USART Instance
03224   * @retval State of bit (1 or 0).
03225   */
03226 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
03227 {
03228   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
03229 }
03230
03231 /**
03232   * @brief  Check if the USART RX FIFO Threshold Flag is set or not
03233   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03234   *         FIFO mode feature is supported by the USARTx instance.
03235   * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
03236   * @param  USARTx USART Instance
03237   * @retval State of bit (1 or 0).
03238   */
03239 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
03240 {
03241   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
03242 }
03243
03244 /**
03245   * @brief  Clear Parity Error Flag
03246   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
03247   * @param  USARTx USART Instance
03248   * @retval None
03249   */
03250 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
03251 {
03252   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
03253 }
03254
03255 /**
03256   * @brief  Clear Framing Error Flag
03257   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
03258   * @param  USARTx USART Instance
03259   * @retval None
03260   */
03261 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
03262 {
03263   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
03264 }
03265
03266 /**
03267   * @brief  Clear Noise Error detected Flag
03268   * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
03269   * @param  USARTx USART Instance
03270   * @retval None
03271   */
03272 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
03273 {
03274   WRITE_REG(USARTx->ICR, USART_ICR_NECF);
03275 }
03276
03277 /**
03278   * @brief  Clear OverRun Error Flag
03279   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
03280   * @param  USARTx USART Instance
03281   * @retval None
03282   */
03283 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
03284 {
03285   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
03286 }
03287
03288 /**
03289   * @brief  Clear IDLE line detected Flag
03290   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
03291   * @param  USARTx USART Instance
03292   * @retval None
03293   */
03294 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
03295 {
03296   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
03297 }
03298
03299 /**
03300   * @brief  Clear TX FIFO Empty Flag
03301   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03302   *         FIFO mode feature is supported by the USARTx instance.
03303   * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
03304   * @param  USARTx USART Instance
03305   * @retval None
03306   */
03307 __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
03308 {
03309   WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
03310 }
03311
03312 /**
03313   * @brief  Clear Transmission Complete Flag
03314   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
03315   * @param  USARTx USART Instance
03316   * @retval None
03317   */
03318 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
03319 {
03320   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
03321 }
03322
03323 /**
03324   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
03325   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
03326   * @param  USARTx USART Instance
03327   * @retval None
03328   */
03329 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
03330 {
03331   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
03332 }
03333
03334 /**
03335   * @brief  Clear LIN Break Detection Flag
03336   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03337   *         LIN feature is supported by the USARTx instance.
03338   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
03339   * @param  USARTx USART Instance
03340   * @retval None
03341   */
03342 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
03343 {
03344   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
03345 }
03346
03347 /**
03348   * @brief  Clear CTS Interrupt Flag
03349   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03350   *         Hardware Flow control feature is supported by the USARTx instance.
03351   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
03352   * @param  USARTx USART Instance
03353   * @retval None
03354   */
03355 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
03356 {
03357   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
03358 }
03359
03360 /**
03361   * @brief  Clear Receiver Time Out Flag
03362   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
03363   * @param  USARTx USART Instance
03364   * @retval None
03365   */
03366 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
03367 {
03368   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
03369 }
03370
03371 /**
03372   * @brief  Clear End Of Block Flag
03373   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03374   *         Smartcard feature is supported by the USARTx instance.
03375   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
03376   * @param  USARTx USART Instance
03377   * @retval None
03378   */
03379 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
03380 {
03381   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
03382 }
03383
03384 /**
03385   * @brief  Clear SPI Slave Underrun Flag
03386   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03387   *         SPI Slave mode feature is supported by the USARTx instance.
03388   * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
03389   * @param  USARTx USART Instance
03390   * @retval None
03391   */
03392 __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
03393 {
03394   WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
03395 }
03396
03397 /**
03398   * @brief  Clear Character Match Flag
03399   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
03400   * @param  USARTx USART Instance
03401   * @retval None
03402   */
03403 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
03404 {
03405   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
03406 }
03407
03408 /**
03409   * @brief  Clear Wake Up from stop mode Flag
03410   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03411   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03412   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
03413   * @param  USARTx USART Instance
03414   * @retval None
03415   */
03416 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
03417 {
03418   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
03419 }
03420
03421 /**
03422   * @}
03423   */
03424
03425 /** @defgroup USART_LL_EF_IT_Management IT_Management
03426   * @{
03427   */
03428
03429 /**
03430   * @brief  Enable IDLE Interrupt
03431   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
03432   * @param  USARTx USART Instance
03433   * @retval None
03434   */
03435 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
03436 {
03437   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03438 }
03439
03440 /* Legacy define */
03441 #define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
03442
03443 /**
03444   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
03445   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03446   *         FIFO mode feature is supported by the USARTx instance.
03447   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
03448   * @param  USARTx USART Instance
03449   * @retval None
03450   */
03451 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03452 {
03453   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03454 }
03455
03456 /**
03457   * @brief  Enable Transmission Complete Interrupt
03458   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
03459   * @param  USARTx USART Instance
03460   * @retval None
03461   */
03462 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
03463 {
03464   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
03465 }
03466
03467 /* Legacy define */
03468 #define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
03469
03470 /**
03471   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
03472   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03473   *         FIFO mode feature is supported by the USARTx instance.
03474   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
03475   * @param  USARTx USART Instance
03476   * @retval None
03477   */
03478 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03479 {
03480   SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03481 }
03482
03483 /**
03484   * @brief  Enable Parity Error Interrupt
03485   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
03486   * @param  USARTx USART Instance
03487   * @retval None
03488   */
03489 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03490 {
03491   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03492 }
03493
03494 /**
03495   * @brief  Enable Character Match Interrupt
03496   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03497   * @param  USARTx USART Instance
03498   * @retval None
03499   */
03500 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03501 {
03502   SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03503 }
03504
03505 /**
03506   * @brief  Enable Receiver Timeout Interrupt
03507   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03508   * @param  USARTx USART Instance
03509   * @retval None
03510   */
03511 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03512 {
03513   SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03514 }
03515
03516 /**
03517   * @brief  Enable End Of Block Interrupt
03518   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03519   *         Smartcard feature is supported by the USARTx instance.
03520   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03521   * @param  USARTx USART Instance
03522   * @retval None
03523   */
03524 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03525 {
03526   SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03527 }
03528
03529 /**
03530   * @brief  Enable TX FIFO Empty Interrupt
03531   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03532   *         FIFO mode feature is supported by the USARTx instance.
03533   * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
03534   * @param  USARTx USART Instance
03535   * @retval None
03536   */
03537 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
03538 {
03539   SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03540 }
03541
03542 /**
03543   * @brief  Enable RX FIFO Full Interrupt
03544   * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
03545   * @param  USARTx USART Instance
03546   * @retval None
03547   */
03548 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
03549 {
03550   SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03551 }
03552
03553 /**
03554   * @brief  Enable LIN Break Detection Interrupt
03555   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03556   *         LIN feature is supported by the USARTx instance.
03557   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03558   * @param  USARTx USART Instance
03559   * @retval None
03560   */
03561 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03562 {
03563   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03564 }
03565
03566 /**
03567   * @brief  Enable Error Interrupt
03568   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03569   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03570   *           0: Interrupt is inhibited
03571   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03572   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03573   * @param  USARTx USART Instance
03574   * @retval None
03575   */
03576 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03577 {
03578   SET_BIT(USARTx->CR3, USART_CR3_EIE);
03579 }
03580
03581 /**
03582   * @brief  Enable CTS Interrupt
03583   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03584   *         Hardware Flow control feature is supported by the USARTx instance.
03585   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03586   * @param  USARTx USART Instance
03587   * @retval None
03588   */
03589 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03590 {
03591   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03592 }
03593
03594 /**
03595   * @brief  Enable Wake Up from Stop Mode Interrupt
03596   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03597   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03598   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03599   * @param  USARTx USART Instance
03600   * @retval None
03601   */
03602 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03603 {
03604   SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03605 }
03606
03607 /**
03608   * @brief  Enable TX FIFO Threshold Interrupt
03609   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03610   *         FIFO mode feature is supported by the USARTx instance.
03611   * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
03612   * @param  USARTx USART Instance
03613   * @retval None
03614   */
03615 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
03616 {
03617   SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03618 }
03619
03620 /**
03621   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03622   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03623   *         Smartcard feature is supported by the USARTx instance.
03624   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03625   * @param  USARTx USART Instance
03626   * @retval None
03627   */
03628 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03629 {
03630   SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03631 }
03632
03633 /**
03634   * @brief  Enable RX FIFO Threshold Interrupt
03635   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03636   *         FIFO mode feature is supported by the USARTx instance.
03637   * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
03638   * @param  USARTx USART Instance
03639   * @retval None
03640   */
03641 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
03642 {
03643   SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03644 }
03645
03646 /**
03647   * @brief  Disable IDLE Interrupt
03648   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03649   * @param  USARTx USART Instance
03650   * @retval None
03651   */
03652 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03653 {
03654   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03655 }
03656
03657 /* Legacy define */
03658 #define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
03659
03660 /**
03661   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
03662   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03663   *         FIFO mode feature is supported by the USARTx instance.
03664   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
03665   * @param  USARTx USART Instance
03666   * @retval None
03667   */
03668 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03669 {
03670   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03671 }
03672
03673 /**
03674   * @brief  Disable Transmission Complete Interrupt
03675   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03676   * @param  USARTx USART Instance
03677   * @retval None
03678   */
03679 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03680 {
03681   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03682 }
03683
03684 /* Legacy define */
03685 #define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
03686
03687 /**
03688   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
03689   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03690   *         FIFO mode feature is supported by the USARTx instance.
03691   * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
03692   * @param  USARTx USART Instance
03693   * @retval None
03694   */
03695 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03696 {
03697   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03698 }
03699
03700 /**
03701   * @brief  Disable Parity Error Interrupt
03702   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03703   * @param  USARTx USART Instance
03704   * @retval None
03705   */
03706 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03707 {
03708   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03709 }
03710
03711 /**
03712   * @brief  Disable Character Match Interrupt
03713   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03714   * @param  USARTx USART Instance
03715   * @retval None
03716   */
03717 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03718 {
03719   CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03720 }
03721
03722 /**
03723   * @brief  Disable Receiver Timeout Interrupt
03724   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03725   * @param  USARTx USART Instance
03726   * @retval None
03727   */
03728 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03729 {
03730   CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03731 }
03732
03733 /**
03734   * @brief  Disable End Of Block Interrupt
03735   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03736   *         Smartcard feature is supported by the USARTx instance.
03737   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03738   * @param  USARTx USART Instance
03739   * @retval None
03740   */
03741 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03742 {
03743   CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03744 }
03745
03746 /**
03747   * @brief  Disable TX FIFO Empty Interrupt
03748   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03749   *         FIFO mode feature is supported by the USARTx instance.
03750   * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
03751   * @param  USARTx USART Instance
03752   * @retval None
03753   */
03754 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
03755 {
03756   CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03757 }
03758
03759 /**
03760   * @brief  Disable RX FIFO Full Interrupt
03761   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03762   *         FIFO mode feature is supported by the USARTx instance.
03763   * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
03764   * @param  USARTx USART Instance
03765   * @retval None
03766   */
03767 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
03768 {
03769   CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03770 }
03771
03772 /**
03773   * @brief  Disable LIN Break Detection Interrupt
03774   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03775   *         LIN feature is supported by the USARTx instance.
03776   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03777   * @param  USARTx USART Instance
03778   * @retval None
03779   */
03780 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03781 {
03782   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03783 }
03784
03785 /**
03786   * @brief  Disable Error Interrupt
03787   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03788   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03789   *           0: Interrupt is inhibited
03790   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03791   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03792   * @param  USARTx USART Instance
03793   * @retval None
03794   */
03795 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03796 {
03797   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03798 }
03799
03800 /**
03801   * @brief  Disable CTS Interrupt
03802   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03803   *         Hardware Flow control feature is supported by the USARTx instance.
03804   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03805   * @param  USARTx USART Instance
03806   * @retval None
03807   */
03808 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03809 {
03810   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03811 }
03812
03813 /**
03814   * @brief  Disable Wake Up from Stop Mode Interrupt
03815   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03816   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03817   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03818   * @param  USARTx USART Instance
03819   * @retval None
03820   */
03821 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03822 {
03823   CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03824 }
03825
03826 /**
03827   * @brief  Disable TX FIFO Threshold Interrupt
03828   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03829   *         FIFO mode feature is supported by the USARTx instance.
03830   * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
03831   * @param  USARTx USART Instance
03832   * @retval None
03833   */
03834 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
03835 {
03836   CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03837 }
03838
03839 /**
03840   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03841   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03842   *         Smartcard feature is supported by the USARTx instance.
03843   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03844   * @param  USARTx USART Instance
03845   * @retval None
03846   */
03847 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03848 {
03849   CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03850 }
03851
03852 /**
03853   * @brief  Disable RX FIFO Threshold Interrupt
03854   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03855   *         FIFO mode feature is supported by the USARTx instance.
03856   * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
03857   * @param  USARTx USART Instance
03858   * @retval None
03859   */
03860 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
03861 {
03862   CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03863 }
03864
03865 /**
03866   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03867   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03868   * @param  USARTx USART Instance
03869   * @retval State of bit (1 or 0).
03870   */
03871 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
03872 {
03873   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
03874 }
03875
03876 /* Legacy define */
03877 #define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
03878
03879 /**
03880   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
03881   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03882   *         FIFO mode feature is supported by the USARTx instance.
03883   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
03884   * @param  USARTx USART Instance
03885   * @retval State of bit (1 or 0).
03886   */
03887 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03888 {
03889   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
03890 }
03891
03892 /**
03893   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03894   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03895   * @param  USARTx USART Instance
03896   * @retval State of bit (1 or 0).
03897   */
03898 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
03899 {
03900   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
03901 }
03902
03903 /* Legacy define */
03904 #define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
03905
03906 /**
03907   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
03908   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03909   *         FIFO mode feature is supported by the USARTx instance.
03910   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
03911   * @param  USARTx USART Instance
03912   * @retval State of bit (1 or 0).
03913   */
03914 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
03915 {
03916   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
03917 }
03918
03919 /**
03920   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03921   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03922   * @param  USARTx USART Instance
03923   * @retval State of bit (1 or 0).
03924   */
03925 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
03926 {
03927   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
03928 }
03929
03930 /**
03931   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03932   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03933   * @param  USARTx USART Instance
03934   * @retval State of bit (1 or 0).
03935   */
03936 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
03937 {
03938   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
03939 }
03940
03941 /**
03942   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03943   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03944   * @param  USARTx USART Instance
03945   * @retval State of bit (1 or 0).
03946   */
03947 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
03948 {
03949   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
03950 }
03951
03952 /**
03953   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03954   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03955   *         Smartcard feature is supported by the USARTx instance.
03956   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03957   * @param  USARTx USART Instance
03958   * @retval State of bit (1 or 0).
03959   */
03960 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
03961 {
03962   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
03963 }
03964
03965 /**
03966   * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
03967   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03968   *         FIFO mode feature is supported by the USARTx instance.
03969   * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
03970   * @param  USARTx USART Instance
03971   * @retval State of bit (1 or 0).
03972   */
03973 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
03974 {
03975   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
03976 }
03977
03978 /**
03979   * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
03980   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03981   *         FIFO mode feature is supported by the USARTx instance.
03982   * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
03983   * @param  USARTx USART Instance
03984   * @retval State of bit (1 or 0).
03985   */
03986 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
03987 {
03988   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
03989 }
03990
03991 /**
03992   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
03993   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03994   *         LIN feature is supported by the USARTx instance.
03995   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
03996   * @param  USARTx USART Instance
03997   * @retval State of bit (1 or 0).
03998   */
03999 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
04000 {
04001   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
04002 }
04003
04004 /**
04005   * @brief  Check if the USART Error Interrupt is enabled or disabled.
04006   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
04007   * @param  USARTx USART Instance
04008   * @retval State of bit (1 or 0).
04009   */
04010 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
04011 {
04012   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
04013 }
04014
04015 /**
04016   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
04017   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
04018   *         Hardware Flow control feature is supported by the USARTx instance.
04019   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
04020   * @param  USARTx USART Instance
04021   * @retval State of bit (1 or 0).
04022   */
04023 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
04024 {
04025   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
04026 }
04027
04028 /**
04029   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
04030   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
04031   *         Wake-up from Stop mode feature is supported by the USARTx instance.
04032   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
04033   * @param  USARTx USART Instance
04034   * @retval State of bit (1 or 0).
04035   */
04036 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
04037 {
04038   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
04039 }
04040
04041 /**
04042   * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
04043   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04044   *         FIFO mode feature is supported by the USARTx instance.
04045   * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
04046   * @param  USARTx USART Instance
04047   * @retval State of bit (1 or 0).
04048   */
04049 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
04050 {
04051   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
04052 }
04053
04054 /**
04055   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
04056   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
04057   *         Smartcard feature is supported by the USARTx instance.
04058   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
04059   * @param  USARTx USART Instance
04060   * @retval State of bit (1 or 0).
04061   */
04062 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
04063 {
04064   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
04065 }
04066
04067 /**
04068   * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
04069   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04070   *         FIFO mode feature is supported by the USARTx instance.
04071   * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
04072   * @param  USARTx USART Instance
04073   * @retval State of bit (1 or 0).
04074   */
04075 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
04076 {
04077   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
04078 }
04079
04080 /**
04081   * @}
04082   */
04083
04084 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
04085   * @{
04086   */
04087
04088 /**
04089   * @brief  Enable DMA Mode for reception
04090   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
04091   * @param  USARTx USART Instance
04092   * @retval None
04093   */
04094 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
04095 {
04096   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
04097 }
04098
04099 /**
04100   * @brief  Disable DMA Mode for reception
04101   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
04102   * @param  USARTx USART Instance
04103   * @retval None
04104   */
04105 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
04106 {
04107   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
04108 }
04109
04110 /**
04111   * @brief  Check if DMA Mode is enabled for reception
04112   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
04113   * @param  USARTx USART Instance
04114   * @retval State of bit (1 or 0).
04115   */
04116 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
04117 {
04118   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
04119 }
04120
04121 /**
04122   * @brief  Enable DMA Mode for transmission
04123   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
04124   * @param  USARTx USART Instance
04125   * @retval None
04126   */
04127 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
04128 {
04129   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
04130 }
04131
04132 /**
04133   * @brief  Disable DMA Mode for transmission
04134   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
04135   * @param  USARTx USART Instance
04136   * @retval None
04137   */
04138 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
04139 {
04140   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
04141 }
04142
04143 /**
04144   * @brief  Check if DMA Mode is enabled for transmission
04145   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
04146   * @param  USARTx USART Instance
04147   * @retval State of bit (1 or 0).
04148   */
04149 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
04150 {
04151   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
04152 }
04153
04154 /**
04155   * @brief  Enable DMA Disabling on Reception Error
04156   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
04157   * @param  USARTx USART Instance
04158   * @retval None
04159   */
04160 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
04161 {
04162   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
04163 }
04164
04165 /**
04166   * @brief  Disable DMA Disabling on Reception Error
04167   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
04168   * @param  USARTx USART Instance
04169   * @retval None
04170   */
04171 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
04172 {
04173   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
04174 }
04175
04176 /**
04177   * @brief  Indicate if DMA Disabling on Reception Error is disabled
04178   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
04179   * @param  USARTx USART Instance
04180   * @retval State of bit (1 or 0).
04181   */
04182 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
04183 {
04184   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
04185 }
04186
04187 /**
04188   * @brief  Get the data register address used for DMA transfer
04189   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
04190   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
04191   * @param  USARTx USART Instance
04192   * @param  Direction This parameter can be one of the following values:
04193   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
04194   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
04195   * @retval Address of data register
04196   */
04197 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
04198 {
04199   register uint32_t data_reg_addr;
04200
04201   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
04202   {
04203     /* return address of TDR register */
04204     data_reg_addr = (uint32_t) &(USARTx->TDR);
04205   }
04206   else
04207   {
04208     /* return address of RDR register */
04209     data_reg_addr = (uint32_t) &(USARTx->RDR);
04210   }
04211
04212   return data_reg_addr;
04213 }
04214
04215 /**
04216   * @}
04217   */
04218
04219 /** @defgroup USART_LL_EF_Data_Management Data_Management
04220   * @{
04221   */
04222
04223 /**
04224   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
04225   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
04226   * @param  USARTx USART Instance
04227   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04228   */
04229 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
04230 {
04231   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
04232 }
04233
04234 /**
04235   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
04236   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
04237   * @param  USARTx USART Instance
04238   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
04239   */
04240 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
04241 {
04242   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04243 }
04244
04245 /**
04246   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
04247   * @rmtoll TDR          TDR           LL_USART_TransmitData8
04248   * @param  USARTx USART Instance
04249   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
04250   * @retval None
04251   */
04252 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
04253 {
04254   USARTx->TDR = Value;
04255 }
04256
04257 /**
04258   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
04259   * @rmtoll TDR          TDR           LL_USART_TransmitData9
04260   * @param  USARTx USART Instance
04261   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
04262   * @retval None
04263   */
04264 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
04265 {
04266   USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
04267 }
04268
04269 /**
04270   * @}
04271   */
04272
04273 /** @defgroup USART_LL_EF_Execution Execution
04274   * @{
04275   */
04276
04277 /**
04278   * @brief  Request an Automatic Baud Rate measurement on next received data frame
04279   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
04280   *         Auto Baud Rate detection feature is supported by the USARTx instance.
04281   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
04282   * @param  USARTx USART Instance
04283   * @retval None
04284   */
04285 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
04286 {
04287   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
04288 }
04289
04290 /**
04291   * @brief  Request Break sending
04292   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
04293   * @param  USARTx USART Instance
04294   * @retval None
04295   */
04296 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
04297 {
04298   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
04299 }
04300
04301 /**
04302   * @brief  Put USART in mute mode and set the RWU flag
04303   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
04304   * @param  USARTx USART Instance
04305   * @retval None
04306   */
04307 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
04308 {
04309   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
04310 }
04311
04312 /**
04313   * @brief  Request a Receive Data and FIFO flush
04314   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04315   *         FIFO mode feature is supported by the USARTx instance.
04316   * @note   Allows to discard the received data without reading them, and avoid an overrun
04317   *         condition.
04318   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
04319   * @param  USARTx USART Instance
04320   * @retval None
04321   */
04322 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
04323 {
04324   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
04325 }
04326
04327 /**
04328   * @brief  Request a Transmit data and FIFO flush
04329   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04330   *         FIFO mode feature is supported by the USARTx instance.
04331   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
04332   * @param  USARTx USART Instance
04333   * @retval None
04334   */
04335 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
04336 {
04337   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
04338 }
04339
04340 /**
04341   * @}
04342   */
04343
04344 #if defined(USE_FULL_LL_DRIVER)
04345 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
04346   * @{
04347   */
04348 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
04349 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
04350 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
04351 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04352 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04353 /**
04354   * @}
04355   */
04356 #endif /* USE_FULL_LL_DRIVER */
04357
04358 /**
04359   * @}
04360   */
04361
04362 /**
04363   * @}
04364   */
04365
04366 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
04367
04368 /**
04369   * @}
04370   */
04371
04372 #ifdef __cplusplus
04373 }
04374 #endif
04375
04376 #endif /* STM32H7xx_LL_USART_H */
04377
04378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_utils.c Source File

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stm32h7xx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32h7xx_ll_utils.h"
00021 #include "stm32h7xx_ll_rcc.h"
00022 #include "stm32h7xx_ll_pwr.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025   #include "stm32_assert.h"
00026 #else
00027   #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UTILS_LL
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /** @addtogroup UTILS_LL_Private_Constants
00042   * @{
00043   */
00044 #define UTILS_MAX_FREQUENCY_SCALE1  400000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
00045 #define UTILS_MAX_FREQUENCY_SCALE2  300000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
00046 #define UTILS_MAX_FREQUENCY_SCALE3  200000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
00047
00048 /* Defines used for PLL range */
00049 #define UTILS_PLLVCO_INPUT_MIN1       1000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00050 #define UTILS_PLLVCO_INPUT_MAX1       2000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00051 #define UTILS_PLLVCO_INPUT_MIN2       2000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00052 #define UTILS_PLLVCO_INPUT_MAX2       4000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00053 #define UTILS_PLLVCO_INPUT_MIN3       4000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00054 #define UTILS_PLLVCO_INPUT_MAX3       8000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00055 #define UTILS_PLLVCO_INPUT_MIN4       8000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00056 #define UTILS_PLLVCO_INPUT_MAX4      16000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00057
00058 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
00059 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN      192000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
00060 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
00061 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX      836000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
00062
00063 /* Defines used for HSE range */
00064 #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
00065 #define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
00066
00067 /* Defines used for FLASH latency according to HCLK Frequency */
00068 #define UTILS_SCALE1_LATENCY0_FREQ   70000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
00069 #define UTILS_SCALE1_LATENCY1_FREQ  140000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
00070 #define UTILS_SCALE1_LATENCY2_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
00071
00072 #define UTILS_SCALE2_LATENCY0_FREQ   55000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
00073 #define UTILS_SCALE2_LATENCY1_FREQ  110000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
00074 #define UTILS_SCALE2_LATENCY2_FREQ  165000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
00075 #define UTILS_SCALE2_LATENCY3_FREQ  220000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
00076
00077 #define UTILS_SCALE3_LATENCY0_FREQ   45000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
00078 #define UTILS_SCALE3_LATENCY1_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
00079 #define UTILS_SCALE3_LATENCY2_FREQ  135000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
00080 #define UTILS_SCALE3_LATENCY3_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
00081 #define UTILS_SCALE3_LATENCY4_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
00082 /**
00083   * @}
00084   */
00085
00086 /* Private macros ------------------------------------------------------------*/
00087 /** @addtogroup UTILS_LL_Private_Macros
00088   * @{
00089   */
00090 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00091                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00092                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00093                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00094                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00095                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00096                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00097                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00098                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00099
00100 #define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1)   \
00101                                         || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
00102                                         || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
00103                                         || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
00104                                         || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
00105                                         || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
00106                                         || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
00107                                         || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
00108                                         || ((__VALUE__) == LL_RCC_AHB_DIV_512))
00109
00110 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00111                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00112                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00113                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00114                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00115
00116 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00117                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00118                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00119                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00120                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00121
00122 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
00123                                       || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
00124                                       || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
00125                                       || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
00126                                       || ((__VALUE__) == LL_RCC_APB3_DIV_16))
00127
00128 #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
00129                                       || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
00130                                       || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
00131                                       || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
00132                                       || ((__VALUE__) == LL_RCC_APB4_DIV_16))
00133
00134 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
00135
00136 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
00137
00138 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
00139
00140 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
00141
00142 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)  ( \
00143 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
00144 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
00145 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
00146 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
00147
00148 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
00149 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
00150 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
00151
00152 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
00153 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
00154 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
00155
00156 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
00157                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
00158                                               ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
00159
00160 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00161                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00162
00163 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00164 /**
00165   * @}
00166   */
00167 /* Private function prototypes -----------------------------------------------*/
00168 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00169   * @{
00170   */
00171 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00172 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
00173 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
00174 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00175 static ErrorStatus UTILS_IsPLLsReady(void);
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported functions --------------------------------------------------------*/
00181 /** @addtogroup UTILS_LL_Exported_Functions
00182   * @{
00183   */
00184
00185 /** @addtogroup UTILS_LL_EF_DELAY
00186   * @{
00187   */
00188 #if defined (DUAL_CORE)
00189 /**
00190   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00191   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00192   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00193   * @param  CPU_Frequency Core frequency in Hz
00194   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00195   *         @ref LL_RCC_GetSystemClocksFreq
00196   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
00197   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
00198   * @retval None
00199   */
00200 #else
00201 /**
00202   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00203   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00204   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00205   * @param  CPU_Frequency Core frequency in Hz
00206   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00207   *         @ref LL_RCC_GetSystemClocksFreq
00208   * @retval None
00209   */
00210 #endif /* DUAL_CORE */
00211 void LL_Init1msTick(uint32_t CPU_Frequency)
00212 {
00213   /* Use frequency provided in argument */
00214   LL_InitTick(CPU_Frequency, 1000U);
00215 }
00216
00217
00218 /**
00219   * @brief  This function provides accurate delay (in milliseconds) based
00220   *         on SysTick counter flag
00221   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00222   *         and use rather osDelay service.
00223   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00224   *         will configure Systick to 1ms
00225   * @param  Delay specifies the delay time length, in milliseconds.
00226   * @retval None
00227   */
00228 void LL_mDelay(uint32_t Delay)
00229 {
00230   uint32_t count = Delay;
00231   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00232   /* Add this code to indicate that local variable is not used */
00233   ((void)tmp);
00234
00235   /* Add a period to guaranty minimum wait */
00236   if(count < LL_MAX_DELAY)
00237   {
00238     count++;
00239   }
00240
00241   while (count != 0U)
00242   {
00243     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00244     {
00245       count--;
00246     }
00247   }
00248 }
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup UTILS_EF_SYSTEM
00255   *  @brief    System Configuration functions
00256   *
00257   @verbatim
00258  ===============================================================================
00259            ##### System Configuration functions #####
00260  ===============================================================================
00261     [..]
00262          System, AHB and APB buses clocks configuration
00263
00264          (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
00265          (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
00266   @endverbatim
00267   @internal
00268              Depending on the device voltage range, the maximum frequency should be
00269              adapted accordingly:
00270              (++) +----------------------------------------------------------------------------+
00271              (++) |  Wait states   |                           HCLK clock frequency (MHz)      |
00272              (++) |                |-----------------------------------------------------------|
00273              (++) |  (Latency)     |   voltage range 1 |   voltage range 2 |   voltage range 3 |
00274              (++) |                |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
00275              (++) |----------------|-------------------|-------------------|-------------------|
00276              (++) |0WS(1CPU cycle) |   0 < HCLK <= 70  |   0 < HCLK <= 55  |   0 < HCLK <= 45  |
00277              (++) |----------------|-------------------|-------------------|-------------------|
00278              (++) |1WS(2CPU cycle) |  70 < HCLK <= 140 |  55 < HCLK <= 110 |  45 < HCLK <= 90  |
00279              (++) |----------------|-------------------|-------------------|-------------------|
00280              (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 |  90 < HCLK <= 135 |
00281              (++) |----------------|-------------------|-------------------|-------------------|
00282              (++) |3WS(4CPU cycle) |        --         | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
00283              (++) |----------------|-------------------|-------------------|-------------------|
00284              (++) |4WS(5CPU cycle) |        --         |        --         | 180 < HCLK <= 225 |
00285              (++) +----------------------------------------------------------------------------+
00286
00287   @endinternal
00288   * @{
00289   */
00290 #if defined (DUAL_CORE)
00291 /**
00292   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00293   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00294   * @param  CPU_Frequency Core frequency in Hz
00295   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00296   *         @ref LL_RCC_GetSystemClocksFreq
00297   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
00298   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
00299   * @retval None
00300   */
00301 #else
00302 /**
00303   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00304   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00305   * @param  CPU_Frequency Core frequency in Hz
00306   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00307   *         @ref LL_RCC_GetSystemClocksFreq
00308   * @retval None
00309   */
00310 #endif /* DUAL_CORE */
00311 void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
00312 {
00313   /* HCLK clock frequency */
00314   SystemCoreClock = CPU_Frequency;
00315 }
00316
00317 /**
00318   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00319   * @note   The application need to ensure that PLL is disabled.
00320   * @note   Function is based on the following formula:
00321   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
00322   *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
00323   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00324   *         - PLLP: ensure that max frequency at 400000000 Hz is reach (PLLVCO_output / PLLP)
00325   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00326   *                             the configuration information for the PLL.
00327   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00328   *                             the configuration information for the BUS prescalers.
00329   * @retval An ErrorStatus enumeration value:
00330   *          - SUCCESS: Max frequency configuration done
00331   *          - ERROR: Max frequency configuration not done
00332   */
00333 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00334                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00335 {
00336   ErrorStatus status;
00337 #ifdef  USE_FULL_ASSERT
00338   uint32_t vcoinput_freq, vcooutput_freq;
00339 #endif
00340   uint32_t pllfreq, hsi_clk;
00341
00342   /* Check the parameters */
00343   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00344   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00345   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00346   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00347
00348   hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
00349
00350   /* Check VCO Input frequency */
00351 #ifdef  USE_FULL_ASSERT
00352   vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
00353 #endif
00354   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
00355
00356   /* Check VCO Output frequency */
00357 #ifdef  USE_FULL_ASSERT
00358   vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
00359 #endif
00360   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
00361
00362   /* Check VCO Input ranges */
00363   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
00364
00365   /* Check if one of the PLL is enabled */
00366   if(UTILS_IsPLLsReady() == SUCCESS)
00367   {
00368     /* Calculate the new PLL output frequency */
00369     pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
00370
00371     /* Enable HSI if not enabled */
00372     if(LL_RCC_HSI_IsReady() != 1U)
00373     {
00374       LL_RCC_HSI_Enable();
00375       while (LL_RCC_HSI_IsReady() != 1U)
00376       {
00377         /* Wait for HSI ready */
00378       }
00379     }
00380
00381     /* Configure PLL */
00382     LL_RCC_PLL1P_Enable();
00383     LL_RCC_PLL1FRACN_Enable();
00384     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
00385     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
00386     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
00387     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
00388     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
00389     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
00390     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
00391
00392     /* Enable PLL and switch system clock to PLL */
00393     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00394   }
00395   else
00396   {
00397     /* Current PLL configuration cannot be modified */
00398     status = ERROR;
00399   }
00400
00401   return status;
00402 }
00403
00404 /**
00405   * @brief  This function configures system clock with HSE as clock source of the PLL
00406   * @note   The application need to ensure that PLL is disabled.
00407   * @note   Function is based on the following formula:
00408   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
00409   *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
00410   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00411   *         - PLLP: ensure that max frequency at 400000000 Hz is reached (PLLVCO_output / PLLP)
00412   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
00413   * @param  HSEBypass This parameter can be one of the following values:
00414   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00415   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00416   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00417   *                             the configuration information for the PLL.
00418   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00419   *                             the configuration information for the BUS prescalers.
00420   * @retval An ErrorStatus enumeration value:
00421   *          - SUCCESS: Max frequency configuration done
00422   *          - ERROR: Max frequency configuration not done
00423   */
00424 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00425                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00426 {
00427   ErrorStatus status;
00428 #ifdef  USE_FULL_ASSERT
00429   uint32_t vcoinput_freq, vcooutput_freq;
00430 #endif
00431   uint32_t pllfreq;
00432
00433   /* Check the parameters */
00434   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00435   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00436   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00437   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00438   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00439   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00440
00441   /* Check VCO Input frequency */
00442 #ifdef  USE_FULL_ASSERT
00443   vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
00444 #endif
00445   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
00446
00447   /* Check VCO output frequency */
00448 #ifdef  USE_FULL_ASSERT
00449   vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
00450 #endif
00451   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
00452
00453   /* Check VCO Input/output ranges compatibility */
00454   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
00455
00456   /* Check if one of the PLL is enabled */
00457   if(UTILS_IsPLLsReady() == SUCCESS)
00458   {
00459     /* Calculate the new PLL output frequency */
00460     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00461
00462     /* Enable HSE if not enabled */
00463     if(LL_RCC_HSE_IsReady() != 1U)
00464     {
00465       /* Check if need to enable HSE bypass feature or not */
00466       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
00467       {
00468         LL_RCC_HSE_EnableBypass();
00469       }
00470       else
00471       {
00472         LL_RCC_HSE_DisableBypass();
00473       }
00474
00475       /* Enable HSE */
00476       LL_RCC_HSE_Enable();
00477       while (LL_RCC_HSE_IsReady() != 1U)
00478       {
00479         /* Wait for HSE ready */
00480       }
00481     }
00482
00483     /* Configure PLL */
00484     LL_RCC_PLL1P_Enable();
00485     LL_RCC_PLL1FRACN_Enable();
00486     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
00487     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
00488     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
00489     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
00490     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
00491     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
00492     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
00493
00494     /* Enable PLL and switch system clock to PLL */
00495     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00496   }
00497   else
00498   {
00499     /* Current PLL configuration cannot be modified */
00500     status = ERROR;
00501   }
00502
00503   return status;
00504 }
00505
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513
00514 /** @addtogroup UTILS_LL_Private_Functions
00515   * @{
00516   */
00517
00518 /**
00519   * @brief  Calculate and check the Flash wait states number according to the
00520             new HCLK frequency and current voltage range.
00521   * @param  HCLK_Frequency  HCLK frequency
00522   * @param  latency This parameter can be one of the following values:
00523   *         @arg @ref LL_FLASH_LATENCY_0
00524   *         @arg @ref LL_FLASH_LATENCY_1
00525   *         @arg @ref LL_FLASH_LATENCY_2
00526   *         @arg @ref LL_FLASH_LATENCY_3
00527   *         @arg @ref LL_FLASH_LATENCY_4
00528   *         @arg @ref LL_FLASH_LATENCY_5
00529   *         @arg @ref LL_FLASH_LATENCY_6
00530   *         @arg @ref LL_FLASH_LATENCY_7
00531   * @retval An ErrorStatus enumeration value:
00532   *          - SUCCESS: Latency has been modified
00533   *          - ERROR: Latency cannot be modified
00534   */
00535 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
00536 {
00537   ErrorStatus status = SUCCESS;
00538
00539   /* Frequency cannot be equal to 0 */
00540   if(HCLK_Frequency == 0U)
00541   {
00542     status = ERROR;
00543   }
00544   else
00545   {
00546     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
00547     {
00548       if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
00549       {
00550         /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
00551         *latency = LL_FLASH_LATENCY_2;
00552       }
00553       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
00554       {
00555         /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
00556         *latency = LL_FLASH_LATENCY_1;
00557       }
00558       else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
00559       {
00560         /* HCLK <= 70 => 0WS (1 CPU cycles) */
00561         *latency = LL_FLASH_LATENCY_0;
00562       }
00563       else
00564       {
00565         status = ERROR;
00566       }
00567     }
00568     else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
00569     {
00570       if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
00571       {
00572         /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
00573         *latency = LL_FLASH_LATENCY_3;
00574       }
00575       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
00576       {
00577         /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
00578         *latency = LL_FLASH_LATENCY_2;
00579       }
00580       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
00581       {
00582         /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
00583         *latency = LL_FLASH_LATENCY_1;
00584       }
00585       else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
00586       {
00587         /* HCLK <= 55 => 0WS (1 CPU cycles) */
00588         *latency = LL_FLASH_LATENCY_0;
00589       }
00590       else
00591       {
00592         status = ERROR;
00593       }
00594     }
00595     else /* Scale 3 */
00596     {
00597       if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
00598       {
00599         /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
00600         *latency = LL_FLASH_LATENCY_4;
00601       }
00602       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
00603       {
00604         /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
00605         *latency = LL_FLASH_LATENCY_3;
00606       }
00607       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
00608       {
00609         /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
00610         *latency = LL_FLASH_LATENCY_2;
00611       }
00612       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
00613       {
00614         /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
00615         *latency = LL_FLASH_LATENCY_1;
00616       }
00617       else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
00618       {
00619         /* HCLK <= 45 => 0WS (1 CPU cycles) */
00620         *latency = LL_FLASH_LATENCY_0;
00621       }
00622       else
00623       {
00624         status = ERROR;
00625       }
00626     }
00627   }
00628
00629   return status;
00630 }
00631
00632 /**
00633   * @brief  Update number of Flash wait states
00634   * @param  latency  Flash Latency
00635   * @retval An ErrorStatus enumeration value:
00636   *          - SUCCESS: Latency has been modified
00637   *          - ERROR: Latency cannot be modified
00638   */
00639 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
00640 {
00641   ErrorStatus status = SUCCESS;
00642
00643   LL_FLASH_SetLatency(latency);
00644
00645   /* Check that the new number of wait states is taken into account to access the Flash
00646      memory by reading the FLASH_ACR register */
00647   if(LL_FLASH_GetLatency() != latency)
00648   {
00649     status = ERROR;
00650   }
00651
00652   return status;
00653 }
00654
00655 /**
00656   * @brief  Function to check that PLL can be modified
00657   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00658   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00659   *                             the configuration information for the PLL.
00660   * @retval PLL output frequency (in Hz)
00661   */
00662 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00663 {
00664   uint32_t pllfreq;
00665
00666   /* Check the parameters */
00667   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00668   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00669   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00670   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00671
00672   pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
00673
00674   return pllfreq;
00675 }
00676
00677 /**
00678   * @brief  Check that all PLLs are ready therefore configuration can be done
00679   * @retval An ErrorStatus enumeration value:
00680   *          - SUCCESS: All PLLs are ready so configuration can be done
00681   *          - ERROR: One PLL at least is busy
00682   */
00683 static ErrorStatus UTILS_IsPLLsReady(void)
00684 {
00685   ErrorStatus status = SUCCESS;
00686
00687   /* Check if one of the PLL1 is busy */
00688   if(LL_RCC_PLL1_IsReady() != 0U)
00689   {
00690     /* PLL1 configuration cannot be done */
00691     status = ERROR;
00692   }
00693
00694   /* Check if one of the PLL2 is busy */
00695   if(LL_RCC_PLL2_IsReady() != 0U)
00696   {
00697     /* PLL2 configuration cannot be done */
00698     status = ERROR;
00699   }
00700
00701   /* Check if one of the PLL3 is busy */
00702   if(LL_RCC_PLL3_IsReady() != 0U)
00703   {
00704     /* PLL3 configuration cannot be done */
00705     status = ERROR;
00706   }
00707
00708   return status;
00709 }
00710
00711 /**
00712   * @brief  Function to enable PLL and switch system clock to PLL
00713   * @param  SYSCLK_Frequency SYSCLK frequency
00714   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00715   *                             the configuration information for the BUS prescalers.
00716   * @retval An ErrorStatus enumeration value:
00717   *          - SUCCESS: No problem to switch system to PLL
00718   *          - ERROR: Problem to switch system to PLL
00719   */
00720 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00721 {
00722   ErrorStatus status;
00723   uint32_t new_hclk_frequency, new_latency;
00724
00725   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
00726   assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00727   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00728   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00729   assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
00730   assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
00731
00732   /* Calculate the new HCLK frequency */
00733   new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
00734
00735   /* Calculate the new FLASH latency according to the new HCLK frequency */
00736   status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
00737
00738   if(status == SUCCESS)
00739   {
00740     /* Increasing the number of wait states because of higher CPU frequency */
00741     if(LL_FLASH_GetLatency() < new_latency)
00742     {
00743       status = UTILS_SetFlashLatency(new_latency);
00744     }
00745
00746     /* Update system clock configuration */
00747     if(status == SUCCESS)
00748     {
00749       /* Enable PLL */
00750       LL_RCC_PLL1_Enable();
00751       while (LL_RCC_PLL1_IsReady() != 1U)
00752       {
00753         /* Wait for PLL ready */
00754       }
00755
00756       /* Set All APBxPrescaler to the Highest Divider */
00757       LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
00758       LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
00759       LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
00760       LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
00761
00762       /* Set SYS prescaler*/
00763       LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
00764
00765       /* Set AHB prescaler*/
00766       LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00767
00768       /* Sysclk activation on the main PLL */
00769       LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
00770       while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
00771       {
00772         /* Wait for system clock switch to PLL */
00773       }
00774
00775       /* Set APBn prescaler*/
00776       LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00777       LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00778       LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
00779       LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
00780
00781       /* Update SystemCoreClock variable */
00782       LL_SetSystemCoreClock(SYSCLK_Frequency);
00783     }
00784
00785     /* Decreasing the number of wait states because of lower CPU frequency */
00786     if(LL_FLASH_GetLatency() > new_latency)
00787     {
00788       status = UTILS_SetFlashLatency(new_latency);
00789     }
00790   }
00791
00792   return status;
00793 }
00794
00795 /**
00796   * @}
00797   */
00798
00799 /**
00800   * @}
00801   */
00802
00803 /**
00804   * @}
00805   */
00806
00807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_utils.h Source File

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stm32h7xx_ll_utils.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL UTILS driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Device electronic signature
00014       (+) Timing functions
00015       (+) PLL configuration functions
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Define to prevent recursive inclusion -------------------------------------*/
00033 #ifndef STM32H7xx_LL_UTILS_H
00034 #define STM32H7xx_LL_UTILS_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32h7xx.h"
00042 #include "stm32h7xx_ll_system.h"
00043 #include "stm32h7xx_ll_bus.h"
00044
00045 /** @addtogroup STM32H7xx_LL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup UTILS_LL UTILS
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055
00056 /* Private constants ---------------------------------------------------------*/
00057 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00058   * @{
00059   */
00060
00061 /* Max delay can be used in LL_mDelay */
00062 #define LL_MAX_DELAY                  0xFFFFFFFFU
00063
00064 /**
00065  * @brief Unique device ID register base address
00066  */
00067 #define UID_BASE_ADDRESS              UID_BASE
00068
00069 /**
00070  * @brief Flash size data register base address
00071  */
00072 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00073
00074 /**
00075  * @brief Package data register base address
00076  */
00077 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00085   * @{
00086   */
00087 /**
00088   * @}
00089   */
00090 /* Exported types ------------------------------------------------------------*/
00091 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00092   * @{
00093   */
00094 /**
00095   * @brief  UTILS PLL structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00100                         This parameter must be a number between Min_Data = 0 and Max_Data = 63
00101
00102                         This feature can be modified afterwards using unitary function
00103                         @ref LL_RCC_PLL1_SetM(). */
00104
00105   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00106                         This parameter must be a number between Min_Data = 4 and Max_Data = 512
00107
00108                         This feature can be modified afterwards using unitary function
00109                         @ref LL_RCC_PLL1_SetN(). */
00110
00111   uint32_t PLLP;   /*!< Division for the main system clock.
00112                         This parameter must be a number between Min_Data = 2 and Max_Data = 128
00113                           odd division factors are not allowed
00114
00115                         This feature can be modified afterwards using unitary function
00116                         @ref LL_RCC_PLL1_SetP(). */
00117
00118   uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
00119                         This parameter can be a value between 0 and 8191
00120
00121                         This feature can be modified afterwards using unitary function
00122                         @ref LL_RCC_PLL1_SetFRACN(). */
00123
00124   uint32_t VCO_Input;  /*!< Fractional part of the multiplication factor for PLL VCO.
00125                         This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
00126
00127                         This feature can be modified afterwards using unitary function
00128                         @ref LL_RCC_PLL1_SetVCOInputRange(). */
00129
00130   uint32_t VCO_Output;  /*!< Fractional part of the multiplication factor for PLL VCO.
00131                         This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
00132
00133                       This feature can be modified afterwards using unitary function
00134                       @ref LL_RCC_PLL1_SetVCOOutputRange(). */
00135
00136 } LL_UTILS_PLLInitTypeDef;
00137
00138 /**
00139   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00140   */
00141 typedef struct
00142 {
00143   uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
00144                                      This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00145
00146                                      This feature can be modified afterwards using unitary function
00147                                      @ref LL_RCC_SetSysPrescaler(). */
00148
00149   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00150                                        This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
00151
00152                                        This feature can be modified afterwards using unitary function
00153                                        @ref LL_RCC_SetAHBPrescaler(). */
00154
00155   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00156                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00157
00158                                        This feature can be modified afterwards using unitary function
00159                                        @ref LL_RCC_SetAPB1Prescaler(). */
00160
00161   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00162                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00163
00164                                        This feature can be modified afterwards using unitary function
00165                                        @ref LL_RCC_SetAPB2Prescaler(). */
00166
00167   uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
00168                                        This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
00169
00170                                        This feature can be modified afterwards using unitary function
00171                                        @ref LL_RCC_SetAPB3Prescaler(). */
00172
00173   uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
00174                                        This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
00175
00176                                        This feature can be modified afterwards using unitary function
00177                                        @ref LL_RCC_SetAPB4Prescaler(). */
00178
00179 } LL_UTILS_ClkInitTypeDef;
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported constants --------------------------------------------------------*/
00186 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00187   * @{
00188   */
00189
00190 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00191   * @{
00192   */
00193 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00194 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00200   * @{
00201   */
00202 #if defined(SYSCFG_PKGR_PKG)
00203 #define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
00204 #define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
00205 #define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
00206 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
00207 #else
00208 #define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
00209 #define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
00210 #define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
00211 #define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
00212 #define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
00213 #define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
00214 #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
00215 #define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
00216 #define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000010UL                  /*!< UFBGA176 or LQFP176 package type */
00217 #define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000011UL                  /*!< LQFP176 with SMPS package type   */
00218 #define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x00000012UL                  /*!< UFBGA176 with SMPS package type  */
00219 #define LL_UTILS_PACKAGETYPE_TFBGA216                0x00000014UL                  /*!< TFBGA216  package type           */
00220 #define LL_UTILS_PACKAGETYPE_TFBGA225                0x00000016UL                  /*!< TFBGA225  package type           */
00221 #endif /* SYSCFG_PKGR_PKG */
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported macro ------------------------------------------------------------*/
00231
00232 /* Exported functions --------------------------------------------------------*/
00233 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00234   * @{
00235   */
00236
00237 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00238   * @{
00239   */
00240
00241 /**
00242   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00243   * @retval UID[31:0]
00244   */
00245 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00246 {
00247   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00248 }
00249
00250 /**
00251   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00252   * @retval UID[63:32]
00253   */
00254 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00255 {
00256   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00257 }
00258
00259 /**
00260   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00261   * @retval UID[95:64]
00262   */
00263 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00264 {
00265   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00266 }
00267
00268 /**
00269   * @brief  Get Flash memory size
00270   * @note   This bitfield indicates the size of the device Flash memory expressed in
00271   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00272   * @retval FLASH_SIZE[15:0]: Flash memory size
00273   */
00274 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00275 {
00276   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
00277 }
00278
00279 /**
00280   * @brief  Get Package type
00281   * @retval Returned value can be one of the following values:
00282   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
00283   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
00284   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
00285   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
00286   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
00287   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
00288   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
00289   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
00290   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
00291   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
00292   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
00293   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
00294   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
00295   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
00296   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
00297   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
00298   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
00299   *
00300   *        (*) Packages available on some STM32H7 lines only.
00301   * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
00302             the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
00303   */
00304 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00305 {
00306 #if defined(SYSCFG_PKGR_PKG)
00307
00308   return LL_SYSCFG_GetPackage();
00309 #else
00310    return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
00311
00312 #endif  /* SYSCFG_PKGR_PKG */
00313 }
00314
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup UTILS_LL_EF_DELAY DELAY
00320   * @{
00321   */
00322
00323 /**
00324   * @brief  This function configures the Cortex-M SysTick source of the time base.
00325   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00326   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00327   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00328   * @param  Ticks Number of ticks
00329   * @retval None
00330   */
00331 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00332 {
00333   /* Configure the SysTick to have interrupt in 1ms time base */
00334   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00335   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00336   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00337                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00338 }
00339
00340 void        LL_Init1msTick(uint32_t CPU_Frequency);
00341 void        LL_mDelay(uint32_t Delay);
00342
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00348   * @{
00349   */
00350
00351 void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
00352 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00353                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00354 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
00355                                          uint32_t HSEBypass,
00356                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00357                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00358
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 #ifdef __cplusplus
00376 }
00377 #endif
00378
00379 #endif /* STM32H7xx_LL_UTILS_H */
00380
00381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: stm32h7xx_ll_wwdg.h Source File

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stm32h7xx_ll_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_WWDG_H
00022 #define STM32H7xx_LL_WWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (WWDG1) || defined (WWDG2)
00036
00037 /** @defgroup WWDG_LL WWDG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup WWDG_LL_EC_IT IT Defines
00052   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00053   * @{
00054   */
00055 #define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00061   * @{
00062   */
00063 #define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
00064 #define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
00065 #define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
00066 #define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
00067 #define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
00068 #define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
00069 #define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
00070 #define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00081   * @{
00082   */
00083 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00084   * @{
00085   */
00086 /**
00087   * @brief  Write a value in WWDG register
00088   * @param  __INSTANCE__ WWDG Instance
00089   * @param  __REG__ Register to be written
00090   * @param  __VALUE__ Value to be written in the register
00091   * @retval None
00092   */
00093 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00094
00095 /**
00096   * @brief  Read a value in WWDG register
00097   * @param  __INSTANCE__ WWDG Instance
00098   * @param  __REG__ Register to be read
00099   * @retval Register value
00100   */
00101 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup WWDG_LL_EF_Configuration Configuration
00116   * @{
00117   */
00118 /**
00119   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00120   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00121   *         then it cannot be disabled again except by a reset.
00122   *         This bit is set by software and only cleared by hardware after a reset.
00123   *         When WDGA = 1, the watchdog can generate a reset.
00124   * @rmtoll CR           WDGA          LL_WWDG_Enable
00125   * @param  WWDGx WWDG Instance
00126   * @retval None
00127   */
00128 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00129 {
00130   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00131 }
00132
00133 /**
00134   * @brief  Checks if Window Watchdog is enabled
00135   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00136   * @param  WWDGx WWDG Instance
00137   * @retval State of bit (1 or 0).
00138   */
00139 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00140 {
00141   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
00142 }
00143
00144 /**
00145   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00146   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00147   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00148   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00149   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00150   * @rmtoll CR           T             LL_WWDG_SetCounter
00151   * @param  WWDGx WWDG Instance
00152   * @param  Counter 0..0x7F (7 bit counter value)
00153   * @retval None
00154   */
00155 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00156 {
00157   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00158 }
00159
00160 /**
00161   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00162   * @rmtoll CR           T             LL_WWDG_GetCounter
00163   * @param  WWDGx WWDG Instance
00164   * @retval 7 bit Watchdog Counter value
00165   */
00166 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00167 {
00168   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
00169 }
00170
00171 /**
00172   * @brief  Set the time base of the prescaler (WDGTB).
00173   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00174   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00175   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00176   * @param  WWDGx WWDG Instance
00177   * @param  Prescaler This parameter can be one of the following values:
00178   *         @arg @ref LL_WWDG_PRESCALER_1
00179   *         @arg @ref LL_WWDG_PRESCALER_2
00180   *         @arg @ref LL_WWDG_PRESCALER_4
00181   *         @arg @ref LL_WWDG_PRESCALER_8
00182   *         @arg @ref LL_WWDG_PRESCALER_16
00183   *         @arg @ref LL_WWDG_PRESCALER_32
00184   *         @arg @ref LL_WWDG_PRESCALER_64
00185   *         @arg @ref LL_WWDG_PRESCALER_128
00186   * @retval None
00187   */
00188 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00189 {
00190   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00191 }
00192
00193 /**
00194   * @brief  Return current Watchdog Prescaler Value
00195   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00196   * @param  WWDGx WWDG Instance
00197   * @retval Returned value can be one of the following values:
00198   *         @arg @ref LL_WWDG_PRESCALER_1
00199   *         @arg @ref LL_WWDG_PRESCALER_2
00200   *         @arg @ref LL_WWDG_PRESCALER_4
00201   *         @arg @ref LL_WWDG_PRESCALER_8
00202   *         @arg @ref LL_WWDG_PRESCALER_16
00203   *         @arg @ref LL_WWDG_PRESCALER_32
00204   *         @arg @ref LL_WWDG_PRESCALER_64
00205   *         @arg @ref LL_WWDG_PRESCALER_128
00206   */
00207 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00208 {
00209   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00210 }
00211
00212 /**
00213   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00214   * @note   This window value defines when write in the WWDG_CR register
00215   *         to program Watchdog counter is allowed.
00216   *         Watchdog counter value update must occur only when the counter value
00217   *         is lower than the Watchdog window register value.
00218   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00219   *         (in the control register) is refreshed before the downcounter has reached
00220   *         the watchdog window register value.
00221   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00222   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00223   * @rmtoll CFR          W             LL_WWDG_SetWindow
00224   * @param  WWDGx WWDG Instance
00225   * @param  Window 0x00..0x7F (7 bit Window value)
00226   * @retval None
00227   */
00228 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00229 {
00230   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00231 }
00232
00233 /**
00234   * @brief  Return current Watchdog Window Value (7 bits value)
00235   * @rmtoll CFR          W             LL_WWDG_GetWindow
00236   * @param  WWDGx WWDG Instance
00237   * @retval 7 bit Watchdog Window value
00238   */
00239 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00240 {
00241   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00242 }
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00249   * @{
00250   */
00251 /**
00252   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00253   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00254   *         It must be cleared by software by writing 0.
00255   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00256   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00257   * @param  WWDGx WWDG Instance
00258   * @retval State of bit (1 or 0).
00259   */
00260 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00261 {
00262   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
00263 }
00264
00265 /**
00266   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00267   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00268   * @param  WWDGx WWDG Instance
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00272 {
00273   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00274 }
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00281   * @{
00282   */
00283 /**
00284   * @brief  Enable the Early Wakeup Interrupt.
00285   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00286   *         This interrupt is only cleared by hardware after a reset
00287   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00288   * @param  WWDGx WWDG Instance
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00292 {
00293   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00294 }
00295
00296 /**
00297   * @brief  Check if Early Wakeup Interrupt is enabled
00298   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00299   * @param  WWDGx WWDG Instance
00300   * @retval State of bit (1 or 0).
00301   */
00302 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00303 {
00304   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 #endif /* WWDG1 || WWDG2 */
00320
00321 /**
00322   * @}
00323   */
00324
00325 #ifdef __cplusplus
00326 }
00327 #endif
00328
00329 #endif /* STM32H7xx_LL_WWDG_H */
00330
00331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Nov 12 2019 18:50:05 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1


STM32H7B3xQ HAL User Manual: userManualMainpage.txt File Reference

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Generated on Tue Nov 12 2019 18:50:11 for STM32H7B3xQ HAL User Manual by doxygen 1.7.6.1